103 lines
4 KiB
C
103 lines
4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch Machine State
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "migration/cpu.h"
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#include "internals.h"
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/* TLB state */
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const VMStateDescription vmstate_tlb = {
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.name = "cpu/tlb",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(tlb_misc, LoongArchTLB),
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VMSTATE_UINT64(tlb_entry0, LoongArchTLB),
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VMSTATE_UINT64(tlb_entry1, LoongArchTLB),
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VMSTATE_END_OF_LIST()
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}
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};
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/* LoongArch CPU state */
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const VMStateDescription vmstate_loongarch_cpu = {
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.name = "cpu",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.gpr, LoongArchCPU, 32),
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VMSTATE_UINTTL(env.pc, LoongArchCPU),
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VMSTATE_UINT64_ARRAY(env.fpr, LoongArchCPU, 32),
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VMSTATE_UINT32(env.fcsr0, LoongArchCPU),
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VMSTATE_BOOL_ARRAY(env.cf, LoongArchCPU, 8),
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/* Remaining CSRs */
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VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU),
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VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16),
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VMSTATE_UINT64(env.CSR_TID, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU),
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VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4),
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/* Debug CSRs */
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VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU),
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VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU),
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/* TLB */
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VMSTATE_STRUCT_ARRAY(env.tlb, LoongArchCPU, LOONGARCH_TLB_MAX,
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0, vmstate_tlb, LoongArchTLB),
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VMSTATE_END_OF_LIST()
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},
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};
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