72 lines
1.9 KiB
C
72 lines
1.9 KiB
C
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/*
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* host-signal.h: signal info dependent on the host architecture
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2021 Linaro Limited
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*
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* This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef RISCV_HOST_SIGNAL_H
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#define RISCV_HOST_SIGNAL_H
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/* The third argument to a SA_SIGINFO handler is ucontext_t. */
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typedef ucontext_t host_sigcontext;
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static inline uintptr_t host_signal_pc(host_sigcontext *uc)
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{
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return uc->uc_mcontext.__gregs[REG_PC];
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}
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static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
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{
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uc->uc_mcontext.__gregs[REG_PC] = pc;
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}
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static inline void *host_signal_mask(host_sigcontext *uc)
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{
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return &uc->uc_sigmask;
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}
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static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
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{
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/*
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* Detect store by reading the instruction at the program counter.
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* Do not read more than 16 bits, because we have not yet determined
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* the size of the instruction.
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*/
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const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc);
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uint16_t insn = pinsn[0];
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/* 16-bit instructions */
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switch (insn & 0xe003) {
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case 0xa000: /* c.fsd */
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case 0xc000: /* c.sw */
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case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */
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case 0xa002: /* c.fsdsp */
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case 0xc002: /* c.swsp */
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case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */
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return true;
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}
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/* 32-bit instructions, major opcodes */
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switch (insn & 0x7f) {
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case 0x23: /* store */
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case 0x27: /* store-fp */
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return true;
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case 0x2f: /* amo */
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/*
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* The AMO function code is in bits 25-31, unread as yet.
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* The AMO functions are LR (read), SC (write), and the
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* rest are all read-modify-write.
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*/
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insn = pinsn[1];
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return (insn >> 11) != 2; /* LR */
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}
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return false;
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}
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#endif
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