449 lines
14 KiB
C
449 lines
14 KiB
C
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/*
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* RISC-V IMSIC (Incoming Message Signaled Interrupt Controller)
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*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "qemu/bswap.h"
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#include "exec/address-spaces.h"
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#include "hw/sysbus.h"
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#include "hw/pci/msi.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/riscv_imsic.h"
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#include "hw/irq.h"
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#include "target/riscv/cpu.h"
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#include "target/riscv/cpu_bits.h"
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#include "sysemu/sysemu.h"
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#include "migration/vmstate.h"
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#define IMSIC_MMIO_PAGE_LE 0x00
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#define IMSIC_MMIO_PAGE_BE 0x04
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#define IMSIC_MIN_ID ((IMSIC_EIPx_BITS * 2) - 1)
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#define IMSIC_MAX_ID (IMSIC_TOPEI_IID_MASK)
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#define IMSIC_EISTATE_PENDING (1U << 0)
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#define IMSIC_EISTATE_ENABLED (1U << 1)
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#define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \
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IMSIC_EISTATE_PENDING)
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static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
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{
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uint32_t i, max_irq, base;
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base = page * imsic->num_irqs;
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max_irq = (imsic->eithreshold[page] &&
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(imsic->eithreshold[page] <= imsic->num_irqs)) ?
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imsic->eithreshold[page] : imsic->num_irqs;
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for (i = 1; i < max_irq; i++) {
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if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
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IMSIC_EISTATE_ENPEND) {
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return (i << IMSIC_TOPEI_IID_SHIFT) | i;
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}
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}
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return 0;
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}
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static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
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{
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if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
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qemu_irq_raise(imsic->external_irqs[page]);
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} else {
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qemu_irq_lower(imsic->external_irqs[page]);
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}
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}
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static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t page,
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target_ulong *val,
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target_ulong new_val,
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target_ulong wr_mask)
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{
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target_ulong old_val = imsic->eidelivery[page];
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if (val) {
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*val = old_val;
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}
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wr_mask &= 0x1;
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imsic->eidelivery[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
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riscv_imsic_update(imsic, page);
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return 0;
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}
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static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t page,
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target_ulong *val,
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target_ulong new_val,
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target_ulong wr_mask)
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{
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target_ulong old_val = imsic->eithreshold[page];
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if (val) {
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*val = old_val;
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}
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wr_mask &= IMSIC_MAX_ID;
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imsic->eithreshold[page] = (old_val & ~wr_mask) | (new_val & wr_mask);
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riscv_imsic_update(imsic, page);
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return 0;
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}
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static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
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target_ulong *val, target_ulong new_val,
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target_ulong wr_mask)
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{
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uint32_t base, topei = riscv_imsic_topei(imsic, page);
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/* Read pending and enabled interrupt with highest priority */
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if (val) {
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*val = topei;
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}
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/* Writes ignore value and clear top pending interrupt */
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if (topei && wr_mask) {
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topei >>= IMSIC_TOPEI_IID_SHIFT;
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base = page * imsic->num_irqs;
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if (topei) {
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imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;
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}
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riscv_imsic_update(imsic, page);
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}
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return 0;
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}
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static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
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uint32_t xlen, uint32_t page,
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uint32_t num, bool pend, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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uint32_t i, base;
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target_ulong mask;
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uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
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if (xlen != 32) {
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if (num & 0x1) {
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return -EINVAL;
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}
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num >>= 1;
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}
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if (num >= (imsic->num_irqs / xlen)) {
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return -EINVAL;
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}
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base = (page * imsic->num_irqs) + (num * xlen);
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if (val) {
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*val = 0;
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for (i = 0; i < xlen; i++) {
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mask = (target_ulong)1 << i;
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*val |= (imsic->eistate[base + i] & state) ? mask : 0;
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}
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}
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for (i = 0; i < xlen; i++) {
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/* Bit0 of eip0 and eie0 are read-only zero */
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if (!num && !i) {
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continue;
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}
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mask = (target_ulong)1 << i;
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if (wr_mask & mask) {
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if (new_val & mask) {
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imsic->eistate[base + i] |= state;
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} else {
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imsic->eistate[base + i] &= ~state;
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}
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}
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}
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riscv_imsic_update(imsic, page);
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return 0;
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}
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static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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RISCVIMSICState *imsic = arg;
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uint32_t isel, priv, virt, vgein, xlen, page;
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priv = AIA_IREG_PRIV(reg);
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virt = AIA_IREG_VIRT(reg);
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isel = AIA_IREG_ISEL(reg);
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vgein = AIA_IREG_VGEIN(reg);
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xlen = AIA_IREG_XLEN(reg);
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if (imsic->mmode) {
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if (priv == PRV_M && !virt) {
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page = 0;
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} else {
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goto err;
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}
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} else {
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if (priv == PRV_S) {
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if (virt) {
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if (vgein && vgein < imsic->num_pages) {
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page = vgein;
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} else {
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goto err;
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}
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} else {
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page = 0;
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}
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} else {
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goto err;
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}
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}
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switch (isel) {
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case ISELECT_IMSIC_EIDELIVERY:
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return riscv_imsic_eidelivery_rmw(imsic, page, val,
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new_val, wr_mask);
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case ISELECT_IMSIC_EITHRESHOLD:
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return riscv_imsic_eithreshold_rmw(imsic, page, val,
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new_val, wr_mask);
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case ISELECT_IMSIC_TOPEI:
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return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask);
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case ISELECT_IMSIC_EIP0 ... ISELECT_IMSIC_EIP63:
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return riscv_imsic_eix_rmw(imsic, xlen, page,
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isel - ISELECT_IMSIC_EIP0,
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true, val, new_val, wr_mask);
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case ISELECT_IMSIC_EIE0 ... ISELECT_IMSIC_EIE63:
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return riscv_imsic_eix_rmw(imsic, xlen, page,
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isel - ISELECT_IMSIC_EIE0,
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false, val, new_val, wr_mask);
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default:
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break;
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};
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err:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid register priv=%d virt=%d isel=%d vgein=%d\n",
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__func__, priv, virt, isel, vgein);
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return -EINVAL;
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}
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static uint64_t riscv_imsic_read(void *opaque, hwaddr addr, unsigned size)
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{
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RISCVIMSICState *imsic = opaque;
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/* Reads must be 4 byte words */
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if ((addr & 0x3) != 0) {
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goto err;
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}
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/* Reads cannot be out of range */
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if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
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goto err;
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}
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return 0;
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err:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid register read 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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return 0;
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}
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static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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RISCVIMSICState *imsic = opaque;
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uint32_t page;
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/* Writes must be 4 byte words */
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if ((addr & 0x3) != 0) {
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goto err;
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}
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/* Writes cannot be out of range */
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if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) {
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goto err;
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}
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/* Writes only supported for MSI little-endian registers */
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page = addr >> IMSIC_MMIO_PAGE_SHIFT;
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if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
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if (value && (value < imsic->num_irqs)) {
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imsic->eistate[(page * imsic->num_irqs) + value] |=
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IMSIC_EISTATE_PENDING;
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}
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}
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/* Update CPU external interrupt status */
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riscv_imsic_update(imsic, page);
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return;
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err:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Invalid register write 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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}
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static const MemoryRegionOps riscv_imsic_ops = {
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.read = riscv_imsic_read,
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.write = riscv_imsic_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static void riscv_imsic_realize(DeviceState *dev, Error **errp)
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{
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RISCVIMSICState *imsic = RISCV_IMSIC(dev);
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RISCVCPU *rcpu = RISCV_CPU(qemu_get_cpu(imsic->hartid));
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CPUState *cpu = qemu_get_cpu(imsic->hartid);
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CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
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imsic->num_eistate = imsic->num_pages * imsic->num_irqs;
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imsic->eidelivery = g_new0(uint32_t, imsic->num_pages);
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imsic->eithreshold = g_new0(uint32_t, imsic->num_pages);
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imsic->eistate = g_new0(uint32_t, imsic->num_eistate);
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memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
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imsic, TYPE_RISCV_IMSIC,
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IMSIC_MMIO_SIZE(imsic->num_pages));
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio);
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/* Claim the CPU interrupt to be triggered by this IMSIC */
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if (riscv_cpu_claim_interrupts(rcpu,
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(imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) {
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error_setg(errp, "%s already claimed",
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(imsic->mmode) ? "MEIP" : "SEIP");
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return;
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}
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/* Create output IRQ lines */
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imsic->external_irqs = g_malloc(sizeof(qemu_irq) * imsic->num_pages);
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qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages);
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/* Force select AIA feature and setup CSR read-modify-write callback */
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if (env) {
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riscv_set_feature(env, RISCV_FEATURE_AIA);
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if (!imsic->mmode) {
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riscv_cpu_set_geilen(env, imsic->num_pages - 1);
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}
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riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S,
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riscv_imsic_rmw, imsic);
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}
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|
|
|
||
|
|
msi_nonbroken = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property riscv_imsic_properties[] = {
|
||
|
|
DEFINE_PROP_BOOL("mmode", RISCVIMSICState, mmode, 0),
|
||
|
|
DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0),
|
||
|
|
DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0),
|
||
|
|
DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0),
|
||
|
|
DEFINE_PROP_END_OF_LIST(),
|
||
|
|
};
|
||
|
|
|
||
|
|
static const VMStateDescription vmstate_riscv_imsic = {
|
||
|
|
.name = "riscv_imsic",
|
||
|
|
.version_id = 1,
|
||
|
|
.minimum_version_id = 1,
|
||
|
|
.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState,
|
||
|
|
num_pages, 0,
|
||
|
|
vmstate_info_uint32, uint32_t),
|
||
|
|
VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState,
|
||
|
|
num_pages, 0,
|
||
|
|
vmstate_info_uint32, uint32_t),
|
||
|
|
VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState,
|
||
|
|
num_eistate, 0,
|
||
|
|
vmstate_info_uint32, uint32_t),
|
||
|
|
VMSTATE_END_OF_LIST()
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
static void riscv_imsic_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
device_class_set_props(dc, riscv_imsic_properties);
|
||
|
|
dc->realize = riscv_imsic_realize;
|
||
|
|
dc->vmsd = &vmstate_riscv_imsic;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo riscv_imsic_info = {
|
||
|
|
.name = TYPE_RISCV_IMSIC,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(RISCVIMSICState),
|
||
|
|
.class_init = riscv_imsic_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void riscv_imsic_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&riscv_imsic_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(riscv_imsic_register_types)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Create IMSIC device.
|
||
|
|
*/
|
||
|
|
DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode,
|
||
|
|
uint32_t num_pages, uint32_t num_ids)
|
||
|
|
{
|
||
|
|
DeviceState *dev = qdev_new(TYPE_RISCV_IMSIC);
|
||
|
|
CPUState *cpu = qemu_get_cpu(hartid);
|
||
|
|
uint32_t i;
|
||
|
|
|
||
|
|
assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1)));
|
||
|
|
if (mmode) {
|
||
|
|
assert(num_pages == 1);
|
||
|
|
} else {
|
||
|
|
assert(num_pages >= 1 && num_pages <= (IRQ_LOCAL_GUEST_MAX + 1));
|
||
|
|
}
|
||
|
|
assert(IMSIC_MIN_ID <= num_ids);
|
||
|
|
assert(num_ids <= IMSIC_MAX_ID);
|
||
|
|
assert((num_ids & IMSIC_MIN_ID) == IMSIC_MIN_ID);
|
||
|
|
|
||
|
|
qdev_prop_set_bit(dev, "mmode", mmode);
|
||
|
|
qdev_prop_set_uint32(dev, "hartid", hartid);
|
||
|
|
qdev_prop_set_uint32(dev, "num-pages", num_pages);
|
||
|
|
qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1);
|
||
|
|
|
||
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
|
||
|
|
|
||
|
|
for (i = 0; i < num_pages; i++) {
|
||
|
|
if (!i) {
|
||
|
|
qdev_connect_gpio_out_named(dev, NULL, i,
|
||
|
|
qdev_get_gpio_in(DEVICE(cpu),
|
||
|
|
(mmode) ? IRQ_M_EXT : IRQ_S_EXT));
|
||
|
|
} else {
|
||
|
|
qdev_connect_gpio_out_named(dev, NULL, i,
|
||
|
|
qdev_get_gpio_in(DEVICE(cpu),
|
||
|
|
IRQ_LOCAL_MAX + i - 1));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return dev;
|
||
|
|
}
|