236 lines
6.4 KiB
C
236 lines
6.4 KiB
C
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/* Blackfin Two Wire Interface (TWI) model
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Copyright (C) 2010-2022 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_twi.h"
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/* XXX: This is merely a stub. */
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struct bfin_twi
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{
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/* This top portion matches common dv_bfin struct. */
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bu32 base;
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struct hw *dma_master;
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bool acked;
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struct hw_event *handler;
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char saved_byte;
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int saved_count;
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bu16 xmt_fifo, rcv_fifo;
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(clkdiv);
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bu16 BFIN_MMR_16(control);
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bu16 BFIN_MMR_16(slave_ctl);
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bu16 BFIN_MMR_16(slave_stat);
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bu16 BFIN_MMR_16(slave_addr);
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bu16 BFIN_MMR_16(master_ctl);
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bu16 BFIN_MMR_16(master_stat);
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bu16 BFIN_MMR_16(master_addr);
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bu16 BFIN_MMR_16(int_stat);
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bu16 BFIN_MMR_16(int_mask);
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bu16 BFIN_MMR_16(fifo_ctl);
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bu16 BFIN_MMR_16(fifo_stat);
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bu32 _pad0[20];
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bu16 BFIN_MMR_16(xmt_data8);
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bu16 BFIN_MMR_16(xmt_data16);
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bu16 BFIN_MMR_16(rcv_data8);
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bu16 BFIN_MMR_16(rcv_data16);
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};
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#define mmr_base() offsetof(struct bfin_twi, clkdiv)
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#define mmr_offset(mmr) (offsetof(struct bfin_twi, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset (mmr) / 4)
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static const char * const mmr_names[] =
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{
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"TWI_CLKDIV", "TWI_CONTROL", "TWI_SLAVE_CTL", "TWI_SLAVE_STAT",
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"TWI_SLAVE_ADDR", "TWI_MASTER_CTL", "TWI_MASTER_STAT", "TWI_MASTER_ADDR",
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"TWI_INT_STAT", "TWI_INT_MASK", "TWI_FIFO_CTL", "TWI_FIFO_STAT",
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[mmr_idx (xmt_data8)] = "TWI_XMT_DATA8", "TWI_XMT_DATA16", "TWI_RCV_DATA8",
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"TWI_RCV_DATA16",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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static unsigned
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bfin_twi_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_twi *twi = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_2 (source);
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mmr_off = addr - twi->base;
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valuep = (void *)((uintptr_t)twi + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(clkdiv):
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case mmr_offset(control):
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case mmr_offset(slave_ctl):
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case mmr_offset(slave_addr):
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case mmr_offset(master_ctl):
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case mmr_offset(master_addr):
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case mmr_offset(int_mask):
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case mmr_offset(fifo_ctl):
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*valuep = value;
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break;
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case mmr_offset(int_stat):
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dv_w1c_2 (valuep, value, -1);
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break;
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case mmr_offset(master_stat):
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dv_w1c_2 (valuep, value, BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB);
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break;
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case mmr_offset(slave_stat):
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case mmr_offset(fifo_stat):
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case mmr_offset(rcv_data8):
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case mmr_offset(rcv_data16):
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/* These are all RO. XXX: Does these throw error ? */
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break;
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case mmr_offset(xmt_data8):
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value &= 0xff;
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case mmr_offset(xmt_data16):
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twi->xmt_fifo = value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_twi_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_twi *twi = hw_data (me);
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bu32 mmr_off;
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bu16 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - twi->base;
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valuep = (void *)((uintptr_t)twi + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(clkdiv):
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case mmr_offset(control):
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case mmr_offset(slave_ctl):
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case mmr_offset(slave_stat):
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case mmr_offset(slave_addr):
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case mmr_offset(master_ctl):
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case mmr_offset(master_stat):
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case mmr_offset(master_addr):
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case mmr_offset(int_stat):
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case mmr_offset(int_mask):
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case mmr_offset(fifo_ctl):
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case mmr_offset(fifo_stat):
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dv_store_2 (dest, *valuep);
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break;
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case mmr_offset(rcv_data8):
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case mmr_offset(rcv_data16):
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dv_store_2 (dest, twi->rcv_fifo);
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break;
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case mmr_offset(xmt_data8):
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case mmr_offset(xmt_data16):
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/* These always read as 0. */
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dv_store_2 (dest, 0);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_twi_ports[] =
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{
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{ "stat", 0, 0, output_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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attach_bfin_twi_regs (struct hw *me, struct bfin_twi *twi)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_TWI_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_TWI_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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twi->base = attach_address;
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}
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static void
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bfin_twi_finish (struct hw *me)
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{
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struct bfin_twi *twi;
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twi = HW_ZALLOC (me, struct bfin_twi);
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set_hw_data (me, twi);
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set_hw_io_read_buffer (me, bfin_twi_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_twi_io_write_buffer);
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set_hw_ports (me, bfin_twi_ports);
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attach_bfin_twi_regs (me, twi);
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}
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const struct hw_descriptor dv_bfin_twi_descriptor[] =
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{
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{"bfin_twi", bfin_twi_finish,},
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{NULL, NULL},
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};
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