695 lines
24 KiB
Text
695 lines
24 KiB
Text
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@c Copyright (C) 2016-2022 Free Software Foundation, Inc.
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@c This is part of the GAS anual.
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@c For copying conditions, see the file as.texinfo
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@c man end
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@ifset GENERIC
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@page
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@node RISC-V-Dependent
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@chapter RISC-V Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter RISC-V Dependent Features
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@end ifclear
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@cindex RISC-V support
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@menu
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* RISC-V-Options:: RISC-V Options
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* RISC-V-Directives:: RISC-V Directives
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* RISC-V-Modifiers:: RISC-V Assembler Modifiers
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* RISC-V-Formats:: RISC-V Instruction Formats
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* RISC-V-ATTRIBUTE:: RISC-V Object Attribute
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@end menu
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@node RISC-V-Options
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@section RISC-V Options
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The following table lists all available RISC-V specific options.
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @samp{-fpic} option, RISC-V
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@item -fpic
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@itemx -fPIC
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Generate position-independent code
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@cindex @samp{-fno-pic} option, RISC-V
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@item -fno-pic
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Don't generate position-independent code (default)
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@cindex @samp{-march=ISA} option, RISC-V
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@item -march=ISA
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Select the base isa, as specified by ISA. For example -march=rv32ima.
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If this option and the architecture attributes aren't set, then assembler
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will check the default configure setting --with-arch=ISA.
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@cindex @samp{-misa-spec=ISAspec} option, RISC-V
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@item -misa-spec=ISAspec
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Select the default isa spec version. If the version of ISA isn't set
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by -march, then assembler helps to set the version according to
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the default chosen spec. If this option isn't set, then assembler will
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check the default configure setting --with-isa-spec=ISAspec.
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@cindex @samp{-mpriv-spec=PRIVspec} option, RISC-V
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@item -mpriv-spec=PRIVspec
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Select the privileged spec version. We can decide whether the CSR is valid or
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not according to the chosen spec. If this option and the privilege attributes
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aren't set, then assembler will check the default configure setting
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--with-priv-spec=PRIVspec.
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@cindex @samp{-mabi=ABI} option, RISC-V
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@item -mabi=ABI
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Selects the ABI, which is either "ilp32" or "lp64", optionally followed
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by "f", "d", or "q" to indicate single-precision, double-precision, or
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quad-precision floating-point calling convention, or none to indicate
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the soft-float calling convention. Also, "ilp32" can optionally be followed
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by "e" to indicate the RVE ABI, which is always soft-float.
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@cindex @samp{-mrelax} option, RISC-V
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@item -mrelax
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Take advantage of linker relaxations to reduce the number of instructions
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required to materialize symbol addresses. (default)
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@cindex @samp{-mno-relax} option, RISC-V
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@item -mno-relax
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Don't do linker relaxations.
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@cindex @samp{-march-attr} option, RISC-V
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@item -march-attr
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Generate the default contents for the riscv elf attribute section if the
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.attribute directives are not set. This section is used to record the
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information that a linker or runtime loader needs to check compatibility.
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This information includes ISA string, stack alignment requirement, unaligned
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memory accesses, and the major, minor and revision version of privileged
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specification.
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@cindex @samp{-mno-arch-attr} option, RISC-V
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@item -mno-arch-attr
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Don't generate the default riscv elf attribute section if the .attribute
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directives are not set.
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@cindex @samp{-mcsr-check} option, RISC-V
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@item -mcsr-check
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Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
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The ISA-dependent CSR are only valid when the specific ISA is set. The
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read-only CSR can not be written by the CSR instructions.
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@cindex @samp{-mno-csr-check} option, RISC-V
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@item -mno-csr-check
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Don't do CSR checking.
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@cindex @samp{-mlittle-endian} option, RISC-V
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@item -mlittle-endian
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Generate code for a little endian machine.
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@cindex @samp{-mbig-endian} option, RISC-V
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@item -mbig-endian
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Generate code for a big endian machine.
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@end table
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@c man end
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@node RISC-V-Directives
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@section RISC-V Directives
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@cindex machine directives, RISC-V
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@cindex RISC-V machine directives
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The following table lists all available RISC-V specific directives.
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@table @code
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@cindex @code{align} directive
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@item .align @var{size-log-2}
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Align to the given boundary, with the size given as log2 the number of bytes to
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align to.
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@cindex Data directives
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@item .half @var{value}
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@itemx .word @var{value}
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@itemx .dword @var{value}
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Emits a half-word, word, or double-word value at the current position.
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@cindex DTP-relative data directives
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@item .dtprelword @var{value}
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@itemx .dtpreldword @var{value}
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Emits a DTP-relative word (or double-word) at the current position. This is
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meant to be used by the compiler in shared libraries for DWARF debug info for
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thread local variables.
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@cindex BSS directive
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@item .bss
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Sets the current section to the BSS section.
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@cindex LEB128 directives
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@item .uleb128 @var{value}
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@itemx .sleb128 @var{value}
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Emits a signed or unsigned LEB128 value at the current position. This only
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accepts constant expressions, because symbol addresses can change with
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relaxation, and we don't support relocations to modify LEB128 values at link
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time.
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@cindex Option directive
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@cindex @code{option} directive
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@item .option @var{argument}
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Modifies RISC-V specific assembler options inline with the assembly code.
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This is used when particular instruction sequences must be assembled with a
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specific set of options. For example, since we relax addressing sequences to
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shorter GP-relative sequences when possible the initial load of GP must not be
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relaxed and should be emitted as something like
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@smallexample
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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@end smallexample
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in order to produce after linker relaxation the expected
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@smallexample
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auipc gp, %pcrel_hi(__global_pointer$)
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addi gp, gp, %pcrel_lo(__global_pointer$)
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@end smallexample
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instead of just
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@smallexample
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addi gp, gp, 0
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@end smallexample
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It's not expected that options are changed in this manner during regular use,
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but there are a handful of esoteric cases like the one above where users need
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to disable particular features of the assembler for particular code sequences.
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The complete list of option arguments is shown below:
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@table @code
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@item push
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@itemx pop
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Pushes or pops the current option stack. These should be used whenever
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changing an option in line with assembly code in order to ensure the user's
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command-line options are respected for the bulk of the file being assembled.
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@item rvc
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@itemx norvc
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Enables or disables the generation of compressed instructions. Instructions
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are opportunistically compressed by the RISC-V assembler when possible, but
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sometimes this behavior is not desirable, especially when handling alignments.
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@item pic
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@itemx nopic
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Enables or disables position-independent code generation. Unless you really
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know what you're doing, this should only be at the top of a file.
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@item relax
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@itemx norelax
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Enables or disables relaxation. The RISC-V assembler and linker
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opportunistically relax some code sequences, but sometimes this behavior is not
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desirable.
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@end table
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@item csr-check
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@itemx no-csr-check
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Enables or disables the CSR checking.
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@item arch, @var{+extension[version]} [,...,@var{+extension_n[version_n]}]
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@itemx arch, @var{-extension} [,...,@var{-extension_n}]
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@itemx arch, @var{=ISA}
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Enables or disables the extensions for specific code region. For example,
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@samp{.option arch, +m2p0} means add m extension with version 2.0, and
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@samp{.option arch, -f, -d} means remove extensions, f and d, from the
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architecture string. Note that, @samp{.option arch, +c, -c} have the same
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behavior as @samp{.option rvc, norvc}. However, they are also undesirable
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sometimes. Besides, @samp{.option arch, -i} is illegal, since we cannot
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remove the base i extension anytime. If you want to reset the whole ISA
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string, you can also use @samp{.option arch, =rv32imac} to overwrite the
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previous settings.
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@cindex INSN directives
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@item .insn @var{type}, @var{operand} [,...,@var{operand_n}]
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@itemx .insn @var{insn_length}, @var{value}
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@itemx .insn @var{value}
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This directive permits the numeric representation of an instructions
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and makes the assembler insert the operands according to one of the
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instruction formats for @samp{.insn} (@ref{RISC-V-Formats}).
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For example, the instruction @samp{add a0, a1, a2} could be written as
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@samp{.insn r 0x33, 0, 0, a0, a1, a2}. But in fact, the instruction
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formats are difficult to use for some users, so most of them are using
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@samp{.word} to encode the instruction directly, rather than using
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@samp{.insn}. It is fine for now, but will be wrong when the mapping
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symbols are supported, since @samp{.word} will not be shown as an
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instruction, it should be shown as data. Therefore, we also support
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two more formats of the @samp{.insn}, the instruction @samp{add a0, a1, a2}
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could also be written as @samp{.insn 0x4, 0xc58533} or @samp{.insn 0xc58533}.
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When the @var{insn_length} is set, then assembler will check if the
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@var{value} is a valid @var{insn_length} bytes instruction.
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@cindex @code{.attribute} directive, RISC-V
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@item .attribute @var{tag}, @var{value}
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Set the object attribute @var{tag} to @var{value}.
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The @var{tag} is either an attribute number, or one of the following:
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@code{Tag_RISCV_arch}, @code{Tag_RISCV_stack_align},
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@code{Tag_RISCV_unaligned_access}, @code{Tag_RISCV_priv_spec},
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@code{Tag_RISCV_priv_spec_minor}, @code{Tag_RISCV_priv_spec_revision}.
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@end table
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@node RISC-V-Modifiers
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@section RISC-V Assembler Modifiers
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The RISC-V assembler supports following modifiers for relocatable addresses
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used in RISC-V instruction operands. However, we also support some pseudo
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instructions that are easier to use than these modifiers.
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@table @code
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@item %lo(@var{symbol})
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The low 12 bits of absolute address for @var{symbol}.
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@item %hi(@var{symbol})
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The high 20 bits of absolute address for @var{symbol}. This is usually
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used with the %lo modifier to represent a 32-bit absolute address.
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@smallexample
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lui a0, %hi(@var{symbol}) // R_RISCV_HI20
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addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I
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lui a0, %hi(@var{symbol}) // R_RISCV_HI20
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load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S
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@end smallexample
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@item %pcrel_lo(@var{label})
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The low 12 bits of relative address between pc and @var{symbol}.
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The @var{symbol} is related to the high part instruction which is marked
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by @var{label}.
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@item %pcrel_hi(@var{symbol})
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The high 20 bits of relative address between pc and @var{symbol}.
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This is usually used with the %pcrel_lo modifier to represent a +/-2GB
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pc-relative range.
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@smallexample
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@var{label}:
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auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
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addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
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@var{label}:
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auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20
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load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
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@end smallexample
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Or you can use the pseudo lla/lw/sw/... instruction to do this.
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@smallexample
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lla a0, @var{symbol}
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@end smallexample
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@item %got_pcrel_hi(@var{symbol})
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The high 20 bits of relative address between pc and the GOT entry of
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@var{symbol}. This is usually used with the %pcrel_lo modifier to access
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the GOT entry.
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@smallexample
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@var{label}:
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auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
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addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
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@var{label}:
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auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20
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load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S
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@end smallexample
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Also, the pseudo la instruction with PIC has similar behavior.
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@item %tprel_add(@var{symbol})
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This is used purely to associate the R_RISCV_TPREL_ADD relocation for
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TLS relaxation. This one is only valid as the fourth operand to the normally
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3 operand add instruction.
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@item %tprel_lo(@var{symbol})
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The low 12 bits of relative address between tp and @var{symbol}.
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@item %tprel_hi(@var{symbol})
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The high 20 bits of relative address between tp and @var{symbol}. This is
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usually used with the %tprel_lo and %tprel_add modifiers to access the thread
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local variable @var{symbol} in TLS Local Exec.
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@smallexample
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lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20
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add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD
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load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S
|
||
|
|
@end smallexample
|
||
|
|
|
||
|
|
@item %tls_ie_pcrel_hi(@var{symbol})
|
||
|
|
The high 20 bits of relative address between pc and GOT entry. It is
|
||
|
|
usually used with the %pcrel_lo modifier to access the thread local
|
||
|
|
variable @var{symbol} in TLS Initial Exec.
|
||
|
|
|
||
|
|
@smallexample
|
||
|
|
la.tls.ie a5, @var{symbol}
|
||
|
|
add a5, a5, tp
|
||
|
|
load/store t0, 0(a5)
|
||
|
|
@end smallexample
|
||
|
|
|
||
|
|
The pseudo la.tls.ie instruction can be expended to
|
||
|
|
|
||
|
|
@smallexample
|
||
|
|
@var{label}:
|
||
|
|
auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20
|
||
|
|
load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I
|
||
|
|
@end smallexample
|
||
|
|
|
||
|
|
@item %tls_gd_pcrel_hi(@var{symbol})
|
||
|
|
The high 20 bits of relative address between pc and GOT entry. It is
|
||
|
|
usually used with the %pcrel_lo modifier to access the thread local variable
|
||
|
|
@var{symbol} in TLS Global Dynamic.
|
||
|
|
|
||
|
|
@smallexample
|
||
|
|
la.tls.gd a0, @var{symbol}
|
||
|
|
call __tls_get_addr@@plt
|
||
|
|
mv a5, a0
|
||
|
|
load/store t0, 0(a5)
|
||
|
|
@end smallexample
|
||
|
|
|
||
|
|
The pseudo la.tls.gd instruction can be expended to
|
||
|
|
|
||
|
|
@smallexample
|
||
|
|
@var{label}:
|
||
|
|
auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20
|
||
|
|
addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I
|
||
|
|
@end smallexample
|
||
|
|
|
||
|
|
@end table
|
||
|
|
|
||
|
|
@node RISC-V-Formats
|
||
|
|
@section RISC-V Instruction Formats
|
||
|
|
@cindex instruction formats, risc-v
|
||
|
|
@cindex RISC-V instruction formats
|
||
|
|
|
||
|
|
The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15
|
||
|
|
instruction formats where some of the formats have multiple variants.
|
||
|
|
For the @samp{.insn} pseudo directive the assembler recognizes some
|
||
|
|
of the formats.
|
||
|
|
Typically, the most general variant of the instruction format is used
|
||
|
|
by the @samp{.insn} directive.
|
||
|
|
|
||
|
|
The following table lists the abbreviations used in the table of
|
||
|
|
instruction formats:
|
||
|
|
|
||
|
|
@display
|
||
|
|
@multitable @columnfractions .15 .40
|
||
|
|
@item opcode @tab Unsigned immediate or opcode name for 7-bits opcode.
|
||
|
|
@item opcode2 @tab Unsigned immediate or opcode name for 2-bits opcode.
|
||
|
|
@item func7 @tab Unsigned immediate for 7-bits function code.
|
||
|
|
@item func6 @tab Unsigned immediate for 6-bits function code.
|
||
|
|
@item func4 @tab Unsigned immediate for 4-bits function code.
|
||
|
|
@item func3 @tab Unsigned immediate for 3-bits function code.
|
||
|
|
@item func2 @tab Unsigned immediate for 2-bits function code.
|
||
|
|
@item rd @tab Destination register number for operand x, can be GPR or FPR.
|
||
|
|
@item rd' @tab Destination register number for operand x,
|
||
|
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||
|
|
@item rs1 @tab First source register number for operand x, can be GPR or FPR.
|
||
|
|
@item rs1' @tab First source register number for operand x,
|
||
|
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||
|
|
@item rs2 @tab Second source register number for operand x, can be GPR or FPR.
|
||
|
|
@item rs2' @tab Second source register number for operand x,
|
||
|
|
only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
|
||
|
|
@item simm12 @tab Sign-extended 12-bit immediate for operand x.
|
||
|
|
@item simm20 @tab Sign-extended 20-bit immediate for operand x.
|
||
|
|
@item simm6 @tab Sign-extended 6-bit immediate for operand x.
|
||
|
|
@item uimm5 @tab Unsigned 5-bit immediate for operand x.
|
||
|
|
@item uimm6 @tab Unsigned 6-bit immediate for operand x.
|
||
|
|
@item uimm8 @tab Unsigned 8-bit immediate for operand x.
|
||
|
|
@item symbol @tab Symbol or lable reference for operand x.
|
||
|
|
@end multitable
|
||
|
|
@end display
|
||
|
|
|
||
|
|
The following table lists all available opcode name:
|
||
|
|
|
||
|
|
@table @code
|
||
|
|
@item C0
|
||
|
|
@item C1
|
||
|
|
@item C2
|
||
|
|
Opcode space for compressed instructions.
|
||
|
|
|
||
|
|
@item LOAD
|
||
|
|
Opcode space for load instructions.
|
||
|
|
|
||
|
|
@item LOAD_FP
|
||
|
|
Opcode space for floating-point load instructions.
|
||
|
|
|
||
|
|
@item STORE
|
||
|
|
Opcode space for store instructions.
|
||
|
|
|
||
|
|
@item STORE_FP
|
||
|
|
Opcode space for floating-point store instructions.
|
||
|
|
|
||
|
|
@item AUIPC
|
||
|
|
Opcode space for auipc instruction.
|
||
|
|
|
||
|
|
@item LUI
|
||
|
|
Opcode space for lui instruction.
|
||
|
|
|
||
|
|
@item BRANCH
|
||
|
|
Opcode space for branch instructions.
|
||
|
|
|
||
|
|
@item JAL
|
||
|
|
Opcode space for jal instruction.
|
||
|
|
|
||
|
|
@item JALR
|
||
|
|
Opcode space for jalr instruction.
|
||
|
|
|
||
|
|
@item OP
|
||
|
|
Opcode space for ALU instructions.
|
||
|
|
|
||
|
|
@item OP_32
|
||
|
|
Opcode space for 32-bits ALU instructions.
|
||
|
|
|
||
|
|
@item OP_IMM
|
||
|
|
Opcode space for ALU with immediate instructions.
|
||
|
|
|
||
|
|
@item OP_IMM_32
|
||
|
|
Opcode space for 32-bits ALU with immediate instructions.
|
||
|
|
|
||
|
|
@item OP_FP
|
||
|
|
Opcode space for floating-point operation instructions.
|
||
|
|
|
||
|
|
@item MADD
|
||
|
|
Opcode space for madd instruction.
|
||
|
|
|
||
|
|
@item MSUB
|
||
|
|
Opcode space for msub instruction.
|
||
|
|
|
||
|
|
@item NMADD
|
||
|
|
Opcode space for nmadd instruction.
|
||
|
|
|
||
|
|
@item NMSUB
|
||
|
|
Opcode space for msub instruction.
|
||
|
|
|
||
|
|
@item AMO
|
||
|
|
Opcode space for atomic memory operation instructions.
|
||
|
|
|
||
|
|
@item MISC_MEM
|
||
|
|
Opcode space for misc instructions.
|
||
|
|
|
||
|
|
@item SYSTEM
|
||
|
|
Opcode space for system instructions.
|
||
|
|
|
||
|
|
@item CUSTOM_0
|
||
|
|
@item CUSTOM_1
|
||
|
|
@item CUSTOM_2
|
||
|
|
@item CUSTOM_3
|
||
|
|
Opcode space for customize instructions.
|
||
|
|
|
||
|
|
@end table
|
||
|
|
|
||
|
|
An instruction is two or four bytes in length and must be aligned
|
||
|
|
on a 2 byte boundary. The first two bits of the instruction specify the
|
||
|
|
length of the instruction, 00, 01 and 10 indicates a two byte instruction,
|
||
|
|
11 indicates a four byte instruction.
|
||
|
|
|
||
|
|
The following table lists the RISC-V instruction formats that are available
|
||
|
|
with the @samp{.insn} pseudo directive:
|
||
|
|
|
||
|
|
@table @code
|
||
|
|
@item R type: .insn r opcode6, func3, func7, rd, rs1, rs2
|
||
|
|
@verbatim
|
||
|
|
+-------+-----+-----+-------+----+---------+
|
||
|
|
| func7 | rs2 | rs1 | func3 | rd | opcode6 |
|
||
|
|
+-------+-----+-----+-------+----+---------+
|
||
|
|
31 25 20 15 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
|
||
|
|
@itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
|
||
|
|
@verbatim
|
||
|
|
+-----+-------+-----+-----+-------+----+---------+
|
||
|
|
| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
|
||
|
|
+-----+-------+-----+-----+-------+----+---------+
|
||
|
|
31 27 25 20 15 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item I type: .insn i opcode6, func3, rd, rs1, simm12
|
||
|
|
@itemx I type: .insn i opcode6, func3, rd, simm12(rs1)
|
||
|
|
@verbatim
|
||
|
|
+--------------+-----+-------+----+---------+
|
||
|
|
| simm12[11:0] | rs1 | func3 | rd | opcode6 |
|
||
|
|
+--------------+-----+-------+----+---------+
|
||
|
|
31 20 15 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item S type: .insn s opcode6, func3, rs2, simm12(rs1)
|
||
|
|
@verbatim
|
||
|
|
+--------------+-----+-----+-------+-------------+---------+
|
||
|
|
| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
|
||
|
|
+--------------+-----+-----+-------+-------------+---------+
|
||
|
|
31 25 20 15 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item B type: .insn s opcode6, func3, rs1, rs2, symbol
|
||
|
|
@itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol
|
||
|
|
@verbatim
|
||
|
|
+-----------------+-----+-----+-------+----------------+---------+
|
||
|
|
| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
|
||
|
|
+-----------------+-----+-----+-------+----------------+---------+
|
||
|
|
31 25 20 15 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item U type: .insn u opcode6, rd, simm20
|
||
|
|
@verbatim
|
||
|
|
+--------------------------+----+---------+
|
||
|
|
| simm20[20|10:1|11|19:12] | rd | opcode6 |
|
||
|
|
+--------------------------+----+---------+
|
||
|
|
31 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item J type: .insn j opcode6, rd, symbol
|
||
|
|
@itemx UJ type: .insn uj opcode6, rd, symbol
|
||
|
|
@verbatim
|
||
|
|
+------------+--------------+------------+---------------+----+---------+
|
||
|
|
| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
|
||
|
|
+------------+--------------+------------+---------------+----+---------+
|
||
|
|
31 30 21 20 12 7 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CR type: .insn cr opcode2, func4, rd, rs2
|
||
|
|
@verbatim
|
||
|
|
+-------+--------+-----+---------+
|
||
|
|
| func4 | rd/rs1 | rs2 | opcode2 |
|
||
|
|
+-------+--------+-----+---------+
|
||
|
|
15 12 7 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CI type: .insn ci opcode2, func3, rd, simm6
|
||
|
|
@verbatim
|
||
|
|
+-------+----------+--------+------------+---------+
|
||
|
|
| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
|
||
|
|
+-------+----------+--------+------------+---------+
|
||
|
|
15 13 12 7 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CIW type: .insn ciw opcode2, func3, rd', uimm8
|
||
|
|
@verbatim
|
||
|
|
+-------+------------+-----+---------+
|
||
|
|
| func3 | uimm8[7:0] | rd' | opcode2 |
|
||
|
|
+-------+-------- ---+-----+---------+
|
||
|
|
15 13 5 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CSS type: .insn css opcode2, func3, rd, uimm6
|
||
|
|
@verbatim
|
||
|
|
+-------+------------+----+---------+
|
||
|
|
| func3 | uimm6[5:0] | rd | opcode2 |
|
||
|
|
+-------+------------+----+---------+
|
||
|
|
15 13 7 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
|
||
|
|
@verbatim
|
||
|
|
+-------+------------+------+------------+------+---------+
|
||
|
|
| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rd' | opcode2 |
|
||
|
|
+-------+------------+------+------------+------+---------+
|
||
|
|
15 13 10 7 5 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
|
||
|
|
@verbatim
|
||
|
|
+-------+------------+------+------------+------+---------+
|
||
|
|
| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
|
||
|
|
+-------+------------+------+------------+------+---------+
|
||
|
|
15 13 10 7 5 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CA type: .insn ca opcode2, func6, func2, rd', rs2'
|
||
|
|
@verbatim
|
||
|
|
+-- ----+----------+-------+------+---------+
|
||
|
|
| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
|
||
|
|
+-------+----------+-------+------+---------+
|
||
|
|
15 10 7 5 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CB type: .insn cb opcode2, func3, rs1', symbol
|
||
|
|
@verbatim
|
||
|
|
+-------+--------------+------+------------------+---------+
|
||
|
|
| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
|
||
|
|
+-------+--------------+------+------------------+---------+
|
||
|
|
15 13 10 7 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
@item CJ type: .insn cj opcode2, symbol
|
||
|
|
@verbatim
|
||
|
|
+-------+-------------------------------+---------+
|
||
|
|
| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
|
||
|
|
+-------+-------------------------------+---------+
|
||
|
|
15 13 2 0
|
||
|
|
@end verbatim
|
||
|
|
|
||
|
|
|
||
|
|
@end table
|
||
|
|
|
||
|
|
For the complete list of all instruction format variants see
|
||
|
|
The RISC-V Instruction Set Manual Volume I: User-Level ISA.
|
||
|
|
|
||
|
|
@node RISC-V-ATTRIBUTE
|
||
|
|
@section RISC-V Object Attribute
|
||
|
|
@cindex Object Attribute, RISC-V
|
||
|
|
|
||
|
|
RISC-V attributes have a string value if the tag number is odd and an integer
|
||
|
|
value if the tag number is even.
|
||
|
|
|
||
|
|
@table @r
|
||
|
|
@item Tag_RISCV_stack_align (4)
|
||
|
|
Tag_RISCV_strict_align records the N-byte stack alignment for this object. The
|
||
|
|
default value is 16 for RV32I or RV64I, and 4 for RV32E.
|
||
|
|
|
||
|
|
The smallest value will be used if object files with different
|
||
|
|
Tag_RISCV_stack_align values are merged.
|
||
|
|
|
||
|
|
@item Tag_RISCV_arch (5)
|
||
|
|
Tag_RISCV_arch contains a string for the target architecture taken from the
|
||
|
|
option @option{-march}. Different architectures will be integrated into a
|
||
|
|
superset when object files are merged.
|
||
|
|
|
||
|
|
Note that the version information of the target architecture must be presented
|
||
|
|
explicitly in the attribute and abbreviations must be expanded. The version
|
||
|
|
information, if not given by @option{-march}, must be in accordance with the
|
||
|
|
default specified by the tool. For example, the architecture @code{RV32I} has
|
||
|
|
to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
|
||
|
|
for the default version of its base ISA. On the other hand, the architecture
|
||
|
|
@code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
|
||
|
|
which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
|
||
|
|
with default versions of the standard extensions.
|
||
|
|
|
||
|
|
@item Tag_RISCV_unaligned_access (6)
|
||
|
|
Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
|
||
|
|
memory accesses, and 1 for files that do allow unaligned memory accesses.
|
||
|
|
|
||
|
|
@item Tag_RISCV_priv_spec (8)
|
||
|
|
@item Tag_RISCV_priv_spec_minor (10)
|
||
|
|
@item Tag_RISCV_priv_spec_revision (12)
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Tag_RISCV_priv_spec contains the major/minor/revision version information of
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the privileged specification. It will report errors if object files of
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different privileged specification versions are merged.
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@end table
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