388 lines
9.5 KiB
Text
388 lines
9.5 KiB
Text
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@c Copyright (C) 2019-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node BPF-Dependent
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@chapter BPF Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter BPF Dependent Features
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@end ifclear
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@cindex BPF support
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@menu
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* BPF Options:: Options
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* BPF Syntax:: Syntax
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* BPF Directives:: Machine Directives
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* BPF Opcodes:: Opcodes
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@end menu
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@node BPF Options
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@section Options
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@cindex BPF options (none)
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@cindex options for BPF (none)
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@c man begin OPTIONS
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@table @gcctabopt
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@cindex @option{-EB} command-line option, BPF
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@item -EB
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This option specifies that the assembler should emit big-endian eBPF.
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@cindex @option{-EL} command-line option, BPF
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@item -EL
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This option specifies that the assembler should emit little-endian
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eBPF.
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@end table
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Note that if no endianness option is specified in the command line,
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the host endianness is used.
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@c man end
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@node BPF Syntax
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@section Syntax
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@menu
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* BPF-Chars:: Special Characters
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* BPF-Regs:: Register Names
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* BPF-Pseudo-Maps:: Pseudo map fds
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@end menu
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@node BPF-Chars
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@subsection Special Characters
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@cindex line comment character, BPF
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@cindex BPF line comment character
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The presence of a @samp{;} on a line indicates the start of a comment
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that extends to the end of the current line. If a @samp{#} appears as
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the first character of a line, the whole line is treated as a comment.
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@cindex statement separator, BPF
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Statements and assembly directives are separated by newlines.
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@node BPF-Regs
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@subsection Register Names
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@cindex BPF register names
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@cindex register names, BPF
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The eBPF processor provides ten general-purpose 64-bit registers,
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which are read-write, and a read-only frame pointer register:
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@table @samp
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@item %r0 .. %r9
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General-purpose registers.
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@item %r10
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Frame pointer register.
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@end table
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Some registers have additional names, to reflect their role in the
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eBPF ABI:
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@table @samp
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@item %a
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This is @samp{%r0}.
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@item %ctx
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This is @samp{%r6}.
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@item %fp
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This is @samp{%r10}.
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@end table
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@node BPF-Pseudo-Maps
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@subsection Pseudo Maps
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@cindex pseudo map fd, BPF
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The @samp{LDDW} instruction can take a literal pseudo map file
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descriptor as its second argument. This uses the syntax
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@samp{%map_fd(N)} where @samp{N} is a signed number.
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For example, to load the address of the pseudo map with file
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descriptor @samp{2} in register @samp{r1} we would do:
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@smallexample
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lddw %r1, %map_fd(2)
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@end smallexample
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@node BPF Directives
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@section Machine Directives
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@cindex machine directives, BPF
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The BPF version of @code{@value{AS}} supports the following additional
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machine directives:
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@table @code
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@cindex @code{half} directive, BPF
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@item .word
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The @code{.half} directive produces a 16 bit value.
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@cindex @code{word} directive, BPF
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@item .word
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The @code{.word} directive produces a 32 bit value.
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@cindex @code{dword} directive, BPF
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@item .dword
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The @code{.dword} directive produces a 64 bit value.
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@end table
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@node BPF Opcodes
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@section Opcodes
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@cindex BPF opcodes
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@cindex opcodes for BPF
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In the instruction descriptions below the following field descriptors
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are used:
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@table @code
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@item %d
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Destination general-purpose register whose role is to be destination
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of an operation.
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@item %s
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Source general-purpose register whose role is to be the source of an
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operation.
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@item disp16
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16-bit signed PC-relative offset, measured in number of 64-bit words,
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minus one.
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@item disp32
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32-bit signed PC-relative offset, measured in number of 64-bit words,
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minus one.
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@item offset16
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Signed 16-bit immediate.
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@item imm32
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Signed 32-bit immediate.
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@item imm64
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Signed 64-bit immediate.
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@end table
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@subsubsection Arithmetic instructions
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The destination register in these instructions act like an
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accumulator.
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@table @code
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@item add %d, (%s|imm32)
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64-bit arithmetic addition.
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@item sub %d, (%s|imm32)
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64-bit arithmetic subtraction.
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@item mul %d, (%s|imm32)
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64-bit arithmetic multiplication.
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@item div %d, (%s|imm32)
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64-bit arithmetic integer division.
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@item mod %d, (%s|imm32)
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64-bit integer remainder.
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@item and %d, (%s|imm32)
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64-bit bit-wise ``and'' operation.
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@item or %d, (%s|imm32)
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64-bit bit-wise ``or'' operation.
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@item xor %d, (%s|imm32)
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64-bit bit-wise exclusive-or operation.
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@item lsh %d, (%s|imm32)
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64-bit left shift, by @code{%s} or @code{imm32} bits.
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@item rsh %d, (%s|imm32)
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64-bit right logical shift, by @code{%s} or @code{imm32} bits.
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@item arsh %d, (%s|imm32)
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64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
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@item neg %d
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64-bit arithmetic negation.
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@item mov %d, (%s|imm32)
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Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}
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in @code{%d}.
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@end table
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@subsubsection 32-bit arithmetic instructions
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The destination register in these instructions act as an accumulator.
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@table @code
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@item add32 %d, (%s|imm32)
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32-bit arithmetic addition.
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@item sub32 %d, (%s|imm32)
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32-bit arithmetic subtraction.
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@item mul32 %d, (%s|imm32)
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32-bit arithmetic multiplication.
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@item div32 %d, (%s|imm32)
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32-bit arithmetic integer division.
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@item mod32 %d, (%s|imm32)
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32-bit integer remainder.
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@item and32 %d, (%s|imm32)
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32-bit bit-wise ``and'' operation.
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@item or32 %d, (%s|imm32)
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32-bit bit-wise ``or'' operation.
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@item xor32 %d, (%s|imm32)
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32-bit bit-wise exclusive-or operation.
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@item lsh32 %d, (%s|imm32)
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32-bit left shift, by @code{%s} or @code{imm32} bits.
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@item rsh32 %d, (%s|imm32)
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32-bit right logical shift, by @code{%s} or @code{imm32} bits.
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@item arsh32 %d, (%s|imm32)
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32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
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@item neg32 %d
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32-bit arithmetic negation.
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@item mov32 %d, (%s|imm32)
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Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}
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in @code{%d}.
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@end table
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@subsubsection Endianness conversion instructions
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@table @code
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@item endle %d, (8|16|32)
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Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to
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little-endian.
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@item endbe %d, (8|16|32)
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Convert the 8-bit, 16-bit or 32-bit value in @code{%d} to big-endian.
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@end table
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@subsubsection 64-bit load and pseudo maps
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@table @code
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@item lddw %d, imm64
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Load the given signed 64-bit immediate, or pseudo map descriptor, to
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the destination register @code{%d}.
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@item lddw %d, %map_fd(N)
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Load the address of the given pseudo map fd @emph{N} to the
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destination register @code{%d}.
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@end table
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@subsubsection Load instructions for socket filters
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The following instructions are intended to be used in socket filters,
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and are therefore not general-purpose: they make assumptions on the
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contents of several registers. See the file
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@file{Documentation/networking/filter.txt} in the Linux kernel source
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tree for more information.
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Absolute loads:
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@table @code
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@item ldabsdw imm32
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Absolute 64-bit load.
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@item ldabsw imm32
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Absolute 32-bit load.
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@item ldabsh imm32
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Absolute 16-bit load.
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@item ldabsb imm32
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Absolute 8-bit load.
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@end table
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Indirect loads:
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@table @code
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@item ldinddw %s, imm32
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Indirect 64-bit load.
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@item ldindw %s, imm32
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Indirect 32-bit load.
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@item ldindh %s, imm32
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Indirect 16-bit load.
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@item ldindb %s, imm32
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Indirect 8-bit load.
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@end table
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@subsubsection Generic load/store instructions
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General-purpose load and store instructions are provided for several
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word sizes.
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Load to register instructions:
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@table @code
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@item ldxdw %d, [%s+offset16]
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Generic 64-bit load.
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@item ldxw %d, [%s+offset16]
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Generic 32-bit load.
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@item ldxh %d, [%s+offset16]
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Generic 16-bit load.
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@item ldxb %d, [%s+offset16]
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Generic 8-bit load.
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@end table
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Store from register instructions:
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@table @code
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@item stxdw [%d+offset16], %s
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Generic 64-bit store.
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@item stxw [%d+offset16], %s
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Generic 32-bit store.
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@item stxh [%d+offset16], %s
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Generic 16-bit store.
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@item stxb [%d+offset16], %s
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Generic 8-bit store.
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@end table
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Store from immediates instructions:
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@table @code
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@item stddw [%d+offset16], imm32
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Store immediate as 64-bit.
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@item stdw [%d+offset16], imm32
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Store immediate as 32-bit.
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@item stdh [%d+offset16], imm32
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Store immediate as 16-bit.
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@item stdb [%d+offset16], imm32
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Store immediate as 8-bit.
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@end table
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@subsubsection Jump instructions
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eBPF provides the following compare-and-jump instructions, which
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compare the values of the two given registers, or the values of a
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register and an immediate, and perform a branch in case the comparison
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holds true.
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@table @code
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@item ja %d,(%s|imm32),disp16
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Jump-always.
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@item jeq %d,(%s|imm32),disp16
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Jump if equal.
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@item jgt %d,(%s|imm32),disp16
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Jump if greater.
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@item jge %d,(%s|imm32),disp16
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Jump if greater or equal.
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@item jlt %d,(%s|imm32),disp16
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Jump if lesser.
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@item jle %d,(%s|imm32),disp16
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Jump if lesser or equal.
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@item jset %d,(%s|imm32),disp16
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Jump if signed equal.
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@item jne %d,(%s|imm32),disp16
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Jump if not equal.
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@item jsgt %d,(%s|imm32),disp16
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Jump if signed greater.
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@item jsge %d,(%s|imm32),disp16
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Jump if signed greater or equal.
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@item jslt %d,(%s|imm32),disp16
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Jump if signed lesser.
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@item jsle %d,(%s|imm32),disp16
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Jump if signed lesser or equal.
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@end table
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A call instruction is provided in order to perform calls to other eBPF
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functions, or to external kernel helpers:
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@table @code
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@item call (disp32|imm32)
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Jump and link to the offset @emph{disp32}, or to the kernel helper
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function identified by @emph{imm32}.
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@end table
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Finally:
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@table @code
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@item exit
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Terminate the eBPF program.
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@end table
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@subsubsection Atomic instructions
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Atomic exchange-and-add instructions are provided in two flavors: one
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for swapping 64-bit quantities and another for 32-bit quantities.
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@table @code
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@item xadddw [%d+offset16],%s
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Exchange-and-add a 64-bit value at the specified location.
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@item xaddw [%d+offset16],%s
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Exchange-and-add a 32-bit value at the specified location.
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||
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@end table
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