328 lines
7.7 KiB
C
328 lines
7.7 KiB
C
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "v850_sim.h"
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#include "sim-assert.h"
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#include "itable.h"
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#include <stdlib.h>
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#include <string.h>
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#include "bfd.h"
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#include "target-newlib-syscall.h"
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static const char * get_insn_name (sim_cpu *, int);
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/* For compatibility. */
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SIM_DESC simulator;
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/* V850 interrupt model. */
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enum interrupt_type
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{
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int_reset,
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int_nmi,
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int_intov1,
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int_intp10,
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int_intp11,
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int_intp12,
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int_intp13,
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int_intcm4,
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num_int_types
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};
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const char *interrupt_names[] =
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{
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"reset",
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"nmi",
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"intov1",
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"intp10",
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"intp11",
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"intp12",
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"intp13",
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"intcm4",
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NULL
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};
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static void
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do_interrupt (SIM_DESC sd, void *data)
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{
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const char **interrupt_name = (const char**)data;
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enum interrupt_type inttype;
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inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
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/* For a hardware reset, drop everything and jump to the start
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address */
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if (inttype == int_reset)
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{
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PC = 0;
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PSW = 0x20;
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ECR = 0;
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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/* Deliver an NMI when allowed */
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if (inttype == int_nmi)
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{
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if (PSW & PSW_NP)
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{
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/* We're already working on an NMI, so this one must wait
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around until the previous one is done. The processor
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ignores subsequent NMIs, so we don't need to count them.
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Just keep re-scheduling a single NMI until it manages to
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be delivered */
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if (STATE_CPU (sd, 0)->pending_nmi != NULL)
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sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
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STATE_CPU (sd, 0)->pending_nmi =
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sim_events_schedule (sd, 1, do_interrupt, data);
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return;
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}
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else
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{
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/* NMI can be delivered. Do not deschedule pending_nmi as
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that, if still in the event queue, is a second NMI that
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needs to be delivered later. */
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FEPC = PC;
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FEPSW = PSW;
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/* Set the FECC part of the ECR. */
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ECR &= 0x0000ffff;
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ECR |= 0x10;
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PSW |= PSW_NP;
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PSW &= ~PSW_EP;
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PSW |= PSW_ID;
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PC = 0x10;
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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}
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/* deliver maskable interrupt when allowed */
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if (inttype > int_nmi && inttype < num_int_types)
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{
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if ((PSW & PSW_NP) || (PSW & PSW_ID))
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{
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/* Can't deliver this interrupt, reschedule it for later */
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sim_events_schedule (sd, 1, do_interrupt, data);
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return;
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}
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else
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{
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/* save context */
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EIPC = PC;
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EIPSW = PSW;
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/* Disable further interrupts. */
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PSW |= PSW_ID;
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/* Indicate that we're doing interrupt not exception processing. */
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PSW &= ~PSW_EP;
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/* Clear the EICC part of the ECR, will set below. */
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ECR &= 0xffff0000;
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switch (inttype)
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{
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case int_intov1:
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PC = 0x80;
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ECR |= 0x80;
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break;
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case int_intp10:
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PC = 0x90;
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ECR |= 0x90;
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break;
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case int_intp11:
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PC = 0xa0;
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ECR |= 0xa0;
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break;
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case int_intp12:
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PC = 0xb0;
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ECR |= 0xb0;
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break;
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case int_intp13:
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PC = 0xc0;
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ECR |= 0xc0;
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break;
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case int_intcm4:
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PC = 0xd0;
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ECR |= 0xd0;
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break;
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default:
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/* Should never be possible. */
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sim_engine_abort (sd, NULL, NULL_CIA,
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"do_interrupt - internal error - bad switch");
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break;
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}
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}
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sim_engine_restart (sd, NULL, NULL, NULL_CIA);
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}
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/* some other interrupt? */
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sim_engine_abort (sd, NULL, NULL_CIA,
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"do_interrupt - internal error - interrupt %d unknown",
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inttype);
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}
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/* Return name of an insn, used by insn profiling. */
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static const char *
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get_insn_name (sim_cpu *cpu, int i)
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{
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return itable[i].name;
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}
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/* These default values correspond to expected usage for the chip. */
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uint32_t OP[4];
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static sim_cia
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v850_pc_get (sim_cpu *cpu)
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{
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return PC;
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}
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static void
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v850_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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PC = pc;
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}
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static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int);
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static int v850_reg_store (SIM_CPU *, int, unsigned char *, int);
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind,
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host_callback * cb,
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struct bfd * abfd,
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char * const * argv)
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{
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int i;
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SIM_DESC sd = sim_state_alloc (kind, cb);
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int mach;
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* Set default options before parsing user options. */
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current_target_byte_order = BFD_ENDIAN_LITTLE;
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cb->syscall_map = cb_v850_syscall_map;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
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return 0;
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/* for compatibility */
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simulator = sd;
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/* FIXME: should be better way of setting up interrupts */
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STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
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STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
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/* Initialize the mechanism for doing insn profiling. */
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CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
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CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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return 0;
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/* Allocate core managed memory */
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/* "Mirror" the ROM addresses below 1MB. */
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sim_do_commandf (sd, "memory region 0,0x100000,0x%x", V850_ROM_SIZE);
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/* Chunk of ram adjacent to rom */
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sim_do_commandf (sd, "memory region 0x100000,0x%x", V850_LOW_END-0x100000);
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/* peripheral I/O region - mirror 1K across 4k (0x1000) */
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sim_do_command (sd, "memory region 0xfff000,0x1000,1024");
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/* similarly if in the internal RAM region */
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sim_do_command (sd, "memory region 0xffe000,0x1000,1024");
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/* The parser will print an error message for us, so we silently return. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* check for/establish the a reference program image */
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if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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/* establish any remaining configuration options */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* determine the machine type */
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if (STATE_ARCHITECTURE (sd) != NULL
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&& (STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850
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|| STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850_rh850))
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mach = STATE_ARCHITECTURE (sd)->mach;
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else
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mach = bfd_mach_v850; /* default */
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/* set machine specific configuration */
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switch (mach)
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{
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case bfd_mach_v850:
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case bfd_mach_v850e:
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case bfd_mach_v850e1:
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case bfd_mach_v850e2:
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case bfd_mach_v850e2v3:
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case bfd_mach_v850e3v5:
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STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
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| PSW_CY | PSW_OV | PSW_S | PSW_Z);
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break;
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}
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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CPU_REG_FETCH (cpu) = v850_reg_fetch;
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CPU_REG_STORE (cpu) = v850_reg_store;
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CPU_PC_FETCH (cpu) = v850_pc_get;
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CPU_PC_STORE (cpu) = v850_pc_set;
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}
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return sd;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd,
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struct bfd * prog_bfd,
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char * const *argv,
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char * const *env)
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{
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memset (&State, 0, sizeof (State));
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if (prog_bfd != NULL)
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PC = bfd_get_start_address (prog_bfd);
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return SIM_RC_OK;
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}
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static int
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v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
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{
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*(uint32_t*)memory = H2T_4 (State.regs[rn]);
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return -1;
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}
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static int
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v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
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{
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State.regs[rn] = T2H_4 (*(uint32_t *) memory);
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return length;
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}
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