352 lines
5.8 KiB
PHP
352 lines
5.8 KiB
PHP
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# Support macros for the Hitachi H8 assembly test cases.
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; Set up a minimal machine state
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.macro start
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.equ h8300, 0
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.equ h8300h, 1
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.equ h8300s, 2
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.equ h8sx, 3
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.if (sim_cpu == h8300s)
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.h8300s
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.else
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.if (sim_cpu == h8300h)
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.h8300h
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.else
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.if (sim_cpu == h8sx)
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.h8300sx
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.endif
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.endif
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.endif
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.text
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.align 2
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.global _start
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_start:
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jmp _main
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.data
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.align 2
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.global pass_str
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.global fail_str
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.global ok_str
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.global pass_loc
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.global fail_loc
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.global ok_loc
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pass_str:
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.ascii "pass\n"
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fail_str:
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.ascii "fail\n"
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ok_str:
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.ascii "ok\n"
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pass_loc16:
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.word pass_str
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pass_loc32:
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.long pass_str
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fail_loc16:
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.word fail_str
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fail_loc32:
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.long fail_str
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ok_loc16:
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.word ok_str
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ok_loc32:
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.long ok_str
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.text
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.global _write_and_exit
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_write_and_exit:
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;ssize_t write(int fd, const void *buf, size_t count);
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;Integer arguments have to be zero extended.
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.if (sim_cpu)
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#if __INT_MAX__ == 32767
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extu.l er0
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#endif
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.endif
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jsr @@0xc7
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mov #0, r0
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jmp _exit
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.global _exit
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_exit:
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mov.b r0l, r0h
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mov.w #0xdead, r1
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mov.w #0xbeef, r2
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sleep
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.global _main
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_main:
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.endm
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; Exit with an exit code
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.macro exit code
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mov.w #\code, r0
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jmp _exit
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.endm
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; Output "pass\n"
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.macro pass
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mov.w #0, r0 ; fd == stdout
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.if (sim_cpu == h8300)
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mov.w #pass_str, r1 ; buf == "pass\n"
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mov.w #5, r2 ; len == 5
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.else
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mov.l #pass_str, er1 ; buf == "pass\n"
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mov.l #5, er2 ; len == 5
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.endif
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jmp _write_and_exit
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.endm
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; Output "fail\n"
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.macro fail
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mov.w #0, r0 ; fd == stdout
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.if (sim_cpu == h8300)
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mov.w #fail_str, r1 ; buf == "fail\n"
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mov.w #5, r2 ; len == 5
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.else
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mov.l #fail_str, er1 ; buf == "fail\n"
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mov.l #5, er2 ; len == 5
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.endif
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jmp _write_and_exit
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.endm
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; Load an 8-bit immediate value into a general register
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; (reg must be r0l - r7l or r0h - r7h)
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.macro mvi_h_gr8 val reg
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mov.b #\val, \reg
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.endm
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; Load a 16-bit immediate value into a general register
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; (reg must be r0 - r7)
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.macro mvi_h_gr16 val reg
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mov.w #\val, \reg
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.endm
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; Load a 32-bit immediate value into a general register
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; (reg must be er0 - er7)
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.macro mvi_h_gr32 val reg
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mov.l #\val, \reg
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.endm
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; Test the value of an 8-bit immediate against a general register
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; (reg must be r0l - r7l or r0h - r7h)
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.macro test_h_gr8 val reg
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cmp.b #\val, \reg
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beq .Ltest_gr8\@
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fail
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.Ltest_gr8\@:
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.endm
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; Test the value of a 16-bit immediate against a general register
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; (reg must be r0 - r7)
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.macro test_h_gr16 val reg h=h l=l
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.if (sim_cpu == h8300)
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test_h_gr8 (\val >> 8) \reg\h
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test_h_gr8 (\val & 0xff) \reg\l
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.else
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cmp.w #\val, \reg
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beq .Ltest_gr16\@
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fail
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.Ltest_gr16\@:
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.endif
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.endm
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; Test the value of a 32-bit immediate against a general register
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; (reg must be er0 - er7)
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.macro test_h_gr32 val reg
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cmp.l #\val, \reg
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beq .Ltest_gr32\@
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fail
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.Ltest_gr32\@:
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.endm
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; Set a general register to the fixed pattern 'a5a5a5a5'
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.macro set_gr_a5a5 reg
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.if (sim_cpu == 0)
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; h8300
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mov.w #0xa5a5, r\reg
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.else
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mov.l #0xa5a5a5a5, er\reg
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.endif
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.endm
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; Set all general registers to the fixed pattern 'a5a5a5a5'
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.macro set_grs_a5a5
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.if (sim_cpu == 0)
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; h8300
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mov.w #0xa5a5, r0
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mov.w #0xa5a5, r1
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mov.w #0xa5a5, r2
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mov.w #0xa5a5, r3
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mov.w #0xa5a5, r4
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mov.w #0xa5a5, r5
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mov.w #0xa5a5, r6
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mov.w #0xa5a5, r7
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.else
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mov.l #0xa5a5a5a5, er0
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mov.l #0xa5a5a5a5, er1
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mov.l #0xa5a5a5a5, er2
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mov.l #0xa5a5a5a5, er3
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mov.l #0xa5a5a5a5, er4
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mov.l #0xa5a5a5a5, er5
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mov.l #0xa5a5a5a5, er6
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mov.l #0xa5a5a5a5, er7
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.endif
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.endm
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; Test that a general register contains the fixed pattern 'a5a5a5a5'
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.macro test_gr_a5a5 reg
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.if (sim_cpu == 0)
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; h8300
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test_h_gr16 0xa5a5 r\reg
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.else
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test_h_gr32 0xa5a5a5a5 er\reg
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.endif
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.endm
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; Test that all general regs contain the fixed pattern 'a5a5a5a5'
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.macro test_grs_a5a5
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test_gr_a5a5 0
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endm
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; Set condition code register to an explicit value
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.macro set_ccr val
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ldc #\val, ccr
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.endm
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; Set all condition code flags to zero
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.macro set_ccr_zero
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ldc #0, ccr
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.endm
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; Set carry flag true
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.macro set_carry_flag
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orc #1, ccr
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.endm
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; Clear carry flag
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.macro clear_carry_flag
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andc 0xfe, ccr
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.endm
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; Set zero flag true
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.macro set_zero_flag
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orc #4, ccr
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.endm
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; Clear zero flag
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.macro clear_zero_flag
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andc 0xfb, ccr
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.endm
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; Set neg flag true
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.macro set_neg_flag
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orc #8, ccr
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.endm
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; Clear neg flag
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.macro clear_neg_flag
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andc 0xf7, ccr
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.endm
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; Test that carry flag is clear
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.macro test_carry_clear
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bcc .Lcc\@
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fail ; carry flag not clear
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.Lcc\@:
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.endm
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; Test that carry flag is set
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.macro test_carry_set
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bcs .Lcs\@
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fail ; carry flag not clear
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.Lcs\@:
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.endm
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; Test that overflow flag is clear
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.macro test_ovf_clear
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bvc .Lvc\@
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fail ; overflow flag not clear
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.Lvc\@:
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.endm
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; Test that overflow flag is set
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.macro test_ovf_set
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bvs .Lvs\@
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fail ; overflow flag not clear
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.Lvs\@:
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.endm
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; Test that zero flag is clear
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.macro test_zero_clear
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bne .Lne\@
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fail ; zero flag not clear
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.Lne\@:
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.endm
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; Test that zero flag is set
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.macro test_zero_set
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beq .Leq\@
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fail ; zero flag not clear
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.Leq\@:
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.endm
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; Test that neg flag is clear
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.macro test_neg_clear
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bpl .Lneg\@
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fail ; negative flag not clear
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.Lneg\@:
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.endm
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; Test that neg flag is set
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.macro test_neg_set
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bmi .Lneg\@
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fail ; negative flag not clear
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.Lneg\@:
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.endm
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; Test ccr against an explicit value
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.macro test_ccr val
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.data
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tccr\@: .byte 0
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.text
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mov.b r0l, @tccr\@
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stc ccr, r0l
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cmp.b #\val, r0l
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bne .Ltcc\@
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fail
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.Ltcc\@:
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mov.b @tccr\@, r0l
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.endm
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; Test that all (accessable) condition codes are clear
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.macro test_cc_clear
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test_carry_clear
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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; leaves H, I, U, and UI untested
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.endm
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; Compare memory, fail if not equal (h8sx only, len > 0).
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.macro memcmp src dst len
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mov.l #\src, er5
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mov.l #\dst, er6
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mov.l #\len, er4
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.Lmemcmp_\@:
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cmp.b @er5+, @er6+
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beq .Lmemcmp2_\@
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fail
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.Lmemcmp2_\@:
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dec.l #1, er4
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bne .Lmemcmp_\@
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.endm
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