96 lines
1.5 KiB
ArmAsm
96 lines
1.5 KiB
ArmAsm
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# Blackfin testcase for push/pop instructions
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# mach: bfin
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.include "testutils.inc"
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start
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# This uses R0/R1 as scratch ... assume those work fine in general
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.macro check loader:req, reg:req
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\loader \reg, 0x12345678
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[--SP] = \reg;
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R0 = [SP];
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R1 = \reg;
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CC = R0 == R1;
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IF !CC JUMP 8f;
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\loader \reg, 0x87654321
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\reg = [SP++];
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CC = R0 == R1;
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IF !CC JUMP 8f;
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# need to do a long jump to avoid PCREL issues
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jump 9f;
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8: jump 1f;
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9:
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.endm
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.macro imm_check reg:req
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check imm32, \reg
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.endm
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.macro dmm_check reg:req
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check dmm32, \reg
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.endm
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imm_check R2
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imm_check R3
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imm_check R4
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imm_check R5
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imm_check R6
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imm_check R7
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imm_check P0
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imm_check P1
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imm_check P2
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imm_check P3
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imm_check P4
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imm_check P5
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imm_check FP
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imm_check I0
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imm_check I1
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imm_check I2
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imm_check I3
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imm_check M0
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imm_check M1
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imm_check M2
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imm_check M3
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imm_check B0
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imm_check B1
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imm_check B2
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imm_check B3
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imm_check L0
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imm_check L1
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imm_check L2
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imm_check L3
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dmm_check A0.X
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dmm_check A0.W
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dmm_check A1.X
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dmm_check A1.W
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dmm_check LC0
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dmm_check LC1
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# Make sure the top/bottom regs have bit 1 set
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dmm_check LT0
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dmm_check LT1
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dmm_check LB0
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dmm_check LB1
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dmm_check RETS
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# These require supervisor resources
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.ifndef BFIN_HOST
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dmm_check RETI
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dmm_check RETX
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dmm_check RETN
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# RETE likes to change on the fly with an ICE
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# dmm_check RETE
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# CYCLES can be user mode, but screws kernel
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dmm_check CYCLES
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dmm_check CYCLES2
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dmm_check USP
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# No one pushes/pops these
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# dmm_check EMUDAT
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dmm_check SEQSTAT
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dmm_check SYSCFG
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.endif
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dmm_check ASTAT
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pass
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1:
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fail
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