649 lines
19 KiB
C
649 lines
19 KiB
C
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/* interrupts.c -- 68HC11 Interrupts Emulation
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Copyright 1999-2022 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@nerim.fr)
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This file is part of GDB, GAS, and the GNU binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "sim-signal.h"
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static const char *interrupt_names[] = {
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"R1",
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"R2",
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"R3",
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"R4",
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"R5",
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"R6",
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"R7",
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"R8",
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"R9",
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"R10",
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"R11",
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"SCI",
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"SPI",
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"AINPUT",
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"AOVERFLOW",
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"TOVERFLOW",
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"OUT5",
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"OUT4",
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"OUT3",
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"OUT2",
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"OUT1",
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"INC3",
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"INC2",
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"INC1",
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"RT",
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"IRQ",
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"XIRQ",
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"SWI",
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"ILL",
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"COPRESET",
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"COPFAIL",
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"RESET"
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};
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struct interrupt_def idefs[] = {
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/* Serial interrupts. */
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{ M6811_INT_SCI, M6811_SCSR, M6811_TDRE, M6811_SCCR2, M6811_TIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_TC, M6811_SCCR2, M6811_TCIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_RDRF, M6811_SCCR2, M6811_RIE },
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{ M6811_INT_SCI, M6811_SCSR, M6811_IDLE, M6811_SCCR2, M6811_ILIE },
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/* SPI interrupts. */
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{ M6811_INT_SPI, M6811_SPSR, M6811_SPIF, M6811_SPCR, M6811_SPIE },
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/* Realtime interrupts. */
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{ M6811_INT_TCTN, M6811_TFLG2, M6811_TOF, M6811_TMSK2, M6811_TOI },
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{ M6811_INT_RT, M6811_TFLG2, M6811_RTIF, M6811_TMSK2, M6811_RTII },
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/* Output compare interrupts. */
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{ M6811_INT_OUTCMP1, M6811_TFLG1, M6811_OC1F, M6811_TMSK1, M6811_OC1I },
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{ M6811_INT_OUTCMP2, M6811_TFLG1, M6811_OC2F, M6811_TMSK1, M6811_OC2I },
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{ M6811_INT_OUTCMP3, M6811_TFLG1, M6811_OC3F, M6811_TMSK1, M6811_OC3I },
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{ M6811_INT_OUTCMP4, M6811_TFLG1, M6811_OC4F, M6811_TMSK1, M6811_OC4I },
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{ M6811_INT_OUTCMP5, M6811_TFLG1, M6811_OC5F, M6811_TMSK1, M6811_OC5I },
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/* Input compare interrupts. */
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{ M6811_INT_INCMP1, M6811_TFLG1, M6811_IC1F, M6811_TMSK1, M6811_IC1I },
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{ M6811_INT_INCMP2, M6811_TFLG1, M6811_IC2F, M6811_TMSK1, M6811_IC2I },
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{ M6811_INT_INCMP3, M6811_TFLG1, M6811_IC3F, M6811_TMSK1, M6811_IC3I },
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/* Pulse accumulator. */
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{ M6811_INT_AINPUT, M6811_TFLG2, M6811_PAIF, M6811_TMSK2, M6811_PAII },
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{ M6811_INT_AOVERFLOW,M6811_TFLG2, M6811_PAOVF, M6811_TMSK2, M6811_PAOVI},
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#if 0
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{ M6811_INT_COPRESET, M6811_CONFIG, M6811_NOCOP, 0, 0 },
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{ M6811_INT_COPFAIL, M6811_CONFIG, M6811_NOCOP, 0, 0 }
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#endif
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};
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#define CYCLES_MAX ((((int64_t) 1) << 62) - 1)
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enum
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{
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OPTION_INTERRUPT_INFO = OPTION_START,
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OPTION_INTERRUPT_CATCH,
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OPTION_INTERRUPT_CLEAR
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};
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static DECLARE_OPTION_HANDLER (interrupt_option_handler);
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static const OPTION interrupt_options[] =
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{
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{ {"interrupt-info", no_argument, NULL, OPTION_INTERRUPT_INFO },
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'\0', NULL, "Print information about interrupts",
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interrupt_option_handler },
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{ {"interrupt-catch", required_argument, NULL, OPTION_INTERRUPT_CATCH },
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'\0', "NAME[,MODE]",
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"Catch interrupts when they are raised or taken\n"
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"NAME Name of the interrupt\n"
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"MODE Optional mode (`taken' or `raised')",
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interrupt_option_handler },
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{ {"interrupt-clear", required_argument, NULL, OPTION_INTERRUPT_CLEAR },
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'\0', "NAME", "No longer catch the interrupt",
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interrupt_option_handler },
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{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
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};
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/* Initialize the interrupts module. */
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void
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interrupts_initialize (SIM_DESC sd, sim_cpu *cpu)
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{
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struct interrupts *interrupts = &cpu->cpu_interrupts;
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interrupts->cpu = cpu;
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sim_add_option_table (sd, 0, interrupt_options);
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}
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/* Initialize the interrupts of the processor. */
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void
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interrupts_reset (struct interrupts *interrupts)
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{
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int i;
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interrupts->pending_mask = 0;
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if (interrupts->cpu->cpu_mode & M6811_SMOD)
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interrupts->vectors_addr = 0xbfc0;
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else
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interrupts->vectors_addr = 0xffc0;
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interrupts->nb_interrupts_raised = 0;
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interrupts->min_mask_cycles = CYCLES_MAX;
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interrupts->max_mask_cycles = 0;
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interrupts->last_mask_cycles = 0;
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interrupts->start_mask_cycle = -1;
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interrupts->xirq_start_mask_cycle = -1;
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interrupts->xirq_max_mask_cycles = 0;
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interrupts->xirq_min_mask_cycles = CYCLES_MAX;
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interrupts->xirq_last_mask_cycles = 0;
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for (i = 0; i < M6811_INT_NUMBER; i++)
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{
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interrupts->interrupt_order[i] = i;
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}
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/* Clear the interrupt history table. */
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interrupts->history_index = 0;
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memset (interrupts->interrupts_history, 0,
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sizeof (interrupts->interrupts_history));
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memset (interrupts->interrupts, 0,
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sizeof (interrupts->interrupts));
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/* In bootstrap mode, initialize the vector table to point
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to the RAM location. */
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if (interrupts->cpu->cpu_mode == M6811_SMOD)
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{
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bfd_vma addr = interrupts->vectors_addr;
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uint16_t vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
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for (i = 0; i < M6811_INT_NUMBER; i++)
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{
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memory_write16 (interrupts->cpu, addr, vector);
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addr += 2;
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vector += 3;
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}
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}
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}
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static int
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find_interrupt (const char *name)
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{
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int i;
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if (name)
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for (i = 0; i < M6811_INT_NUMBER; i++)
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if (strcasecmp (name, interrupt_names[i]) == 0)
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return i;
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return -1;
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}
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static SIM_RC
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interrupt_option_handler (SIM_DESC sd, sim_cpu *cpu,
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int opt, char *arg, int is_command)
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{
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char *p;
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int mode;
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int id;
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struct interrupts *interrupts;
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if (cpu == 0)
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cpu = STATE_CPU (sd, 0);
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interrupts = &cpu->cpu_interrupts;
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switch (opt)
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{
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case OPTION_INTERRUPT_INFO:
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for (id = 0; id < M6811_INT_NUMBER; id++)
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{
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sim_io_eprintf (sd, "%-10.10s ", interrupt_names[id]);
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switch (interrupts->interrupts[id].stop_mode)
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{
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case SIM_STOP_WHEN_RAISED:
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sim_io_eprintf (sd, "catch raised ");
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break;
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case SIM_STOP_WHEN_TAKEN:
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sim_io_eprintf (sd, "catch taken ");
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break;
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case SIM_STOP_WHEN_RAISED | SIM_STOP_WHEN_TAKEN:
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sim_io_eprintf (sd, "catch all ");
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break;
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default:
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sim_io_eprintf (sd, " ");
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break;
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}
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sim_io_eprintf (sd, "%ld\n",
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interrupts->interrupts[id].raised_count);
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}
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break;
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case OPTION_INTERRUPT_CATCH:
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p = strchr (arg, ',');
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if (p)
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*p++ = 0;
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mode = SIM_STOP_WHEN_RAISED;
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id = find_interrupt (arg);
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if (id < 0)
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sim_io_eprintf (sd, "Interrupt name not recognized: %s\n", arg);
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if (p && strcasecmp (p, "raised") == 0)
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mode = SIM_STOP_WHEN_RAISED;
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else if (p && strcasecmp (p, "taken") == 0)
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mode = SIM_STOP_WHEN_TAKEN;
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else if (p && strcasecmp (p, "all") == 0)
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mode = SIM_STOP_WHEN_RAISED | SIM_STOP_WHEN_TAKEN;
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else if (p)
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{
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sim_io_eprintf (sd, "Invalid argument: %s\n", p);
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break;
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}
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if (id >= 0)
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interrupts->interrupts[id].stop_mode = mode;
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break;
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case OPTION_INTERRUPT_CLEAR:
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mode = SIM_STOP_WHEN_RAISED;
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id = find_interrupt (arg);
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if (id < 0)
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sim_io_eprintf (sd, "Interrupt name not recognized: %s\n", arg);
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else
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interrupts->interrupts[id].stop_mode = 0;
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break;
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}
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return SIM_RC_OK;
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}
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/* Update the mask of pending interrupts. This operation must be called
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when the state of some 68HC11 IO register changes. It looks the
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different registers that indicate a pending interrupt (timer, SCI, SPI,
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...) and records the interrupt if it's there and enabled. */
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void
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interrupts_update_pending (struct interrupts *interrupts)
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{
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int i;
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uint8_t *ioregs;
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unsigned long clear_mask;
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unsigned long set_mask;
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clear_mask = 0;
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set_mask = 0;
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ioregs = &interrupts->cpu->ios[0];
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for (i = 0; i < ARRAY_SIZE (idefs); i++)
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{
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struct interrupt_def *idef = &idefs[i];
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uint8_t data;
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/* Look if the interrupt is enabled. */
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if (idef->enable_paddr)
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{
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data = ioregs[idef->enable_paddr];
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if (!(data & idef->enabled_mask))
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{
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/* Disable it. */
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clear_mask |= (1 << idef->int_number);
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continue;
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}
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}
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/* Interrupt is enabled, see if it's there. */
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data = ioregs[idef->int_paddr];
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if (!(data & idef->int_mask))
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{
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/* Disable it. */
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clear_mask |= (1 << idef->int_number);
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continue;
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}
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/* Ok, raise it. */
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set_mask |= (1 << idef->int_number);
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}
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/* Some interrupts are shared (M6811_INT_SCI) so clear
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the interrupts before setting the new ones. */
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interrupts->pending_mask &= ~clear_mask;
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interrupts->pending_mask |= set_mask;
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/* Keep track of when the interrupt is raised by the device.
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Also implements the breakpoint-on-interrupt. */
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if (set_mask)
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{
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int64_t cycle = cpu_current_cycle (interrupts->cpu);
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int must_stop = 0;
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for (i = 0; i < M6811_INT_NUMBER; i++)
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{
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if (!(set_mask & (1 << i)))
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continue;
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interrupts->interrupts[i].cpu_cycle = cycle;
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if (interrupts->interrupts[i].stop_mode & SIM_STOP_WHEN_RAISED)
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{
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must_stop = 1;
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sim_io_printf (CPU_STATE (interrupts->cpu),
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"Interrupt %s raised\n",
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interrupt_names[i]);
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}
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}
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if (must_stop)
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sim_engine_halt (CPU_STATE (interrupts->cpu),
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interrupts->cpu,
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0, cpu_get_pc (interrupts->cpu),
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sim_stopped,
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SIM_SIGTRAP);
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}
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}
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/* Finds the current active and non-masked interrupt.
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Returns the interrupt number (index in the vector table) or -1
|
||
|
|
if no interrupt can be serviced. */
|
||
|
|
int
|
||
|
|
interrupts_get_current (struct interrupts *interrupts)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (interrupts->pending_mask == 0)
|
||
|
|
return -1;
|
||
|
|
|
||
|
|
/* SWI and illegal instructions are simulated by an interrupt.
|
||
|
|
They are not maskable. */
|
||
|
|
if (interrupts->pending_mask & (1 << M6811_INT_SWI))
|
||
|
|
{
|
||
|
|
interrupts->pending_mask &= ~(1 << M6811_INT_SWI);
|
||
|
|
return M6811_INT_SWI;
|
||
|
|
}
|
||
|
|
if (interrupts->pending_mask & (1 << M6811_INT_ILLEGAL))
|
||
|
|
{
|
||
|
|
interrupts->pending_mask &= ~(1 << M6811_INT_ILLEGAL);
|
||
|
|
return M6811_INT_ILLEGAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If there is a non maskable interrupt, go for it (unless we are masked
|
||
|
|
by the X-bit. */
|
||
|
|
if (interrupts->pending_mask & (1 << M6811_INT_XIRQ))
|
||
|
|
{
|
||
|
|
if (cpu_get_ccr_X (interrupts->cpu) == 0)
|
||
|
|
{
|
||
|
|
interrupts->pending_mask &= ~(1 << M6811_INT_XIRQ);
|
||
|
|
return M6811_INT_XIRQ;
|
||
|
|
}
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Interrupts are masked, do nothing. */
|
||
|
|
if (cpu_get_ccr_I (interrupts->cpu) == 1)
|
||
|
|
{
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Returns the first interrupt number which is pending.
|
||
|
|
The interrupt priority is specified by the table `interrupt_order'.
|
||
|
|
For these interrupts, the pending mask is cleared when the program
|
||
|
|
performs some actions on the corresponding device. If the device
|
||
|
|
is not reset, the interrupt remains and will be re-raised when
|
||
|
|
we return from the interrupt (see 68HC11 pink book). */
|
||
|
|
for (i = 0; i < M6811_INT_NUMBER; i++)
|
||
|
|
{
|
||
|
|
enum M6811_INT int_number = interrupts->interrupt_order[i];
|
||
|
|
|
||
|
|
if (interrupts->pending_mask & (1 << int_number))
|
||
|
|
{
|
||
|
|
return int_number;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* Process the current interrupt if there is one. This operation must
|
||
|
|
be called after each instruction to handle the interrupts. If interrupts
|
||
|
|
are masked, it does nothing. */
|
||
|
|
int
|
||
|
|
interrupts_process (struct interrupts *interrupts)
|
||
|
|
{
|
||
|
|
int id;
|
||
|
|
uint8_t ccr;
|
||
|
|
|
||
|
|
/* See if interrupts are enabled/disabled and keep track of the
|
||
|
|
number of cycles the interrupts are masked. Such information is
|
||
|
|
then reported by the info command. */
|
||
|
|
ccr = cpu_get_ccr (interrupts->cpu);
|
||
|
|
if (ccr & M6811_I_BIT)
|
||
|
|
{
|
||
|
|
if (interrupts->start_mask_cycle < 0)
|
||
|
|
interrupts->start_mask_cycle = cpu_current_cycle (interrupts->cpu);
|
||
|
|
}
|
||
|
|
else if (interrupts->start_mask_cycle >= 0
|
||
|
|
&& (ccr & M6811_I_BIT) == 0)
|
||
|
|
{
|
||
|
|
int64_t t = cpu_current_cycle (interrupts->cpu);
|
||
|
|
|
||
|
|
t -= interrupts->start_mask_cycle;
|
||
|
|
if (t < interrupts->min_mask_cycles)
|
||
|
|
interrupts->min_mask_cycles = t;
|
||
|
|
if (t > interrupts->max_mask_cycles)
|
||
|
|
interrupts->max_mask_cycles = t;
|
||
|
|
interrupts->start_mask_cycle = -1;
|
||
|
|
interrupts->last_mask_cycles = t;
|
||
|
|
}
|
||
|
|
if (ccr & M6811_X_BIT)
|
||
|
|
{
|
||
|
|
if (interrupts->xirq_start_mask_cycle < 0)
|
||
|
|
interrupts->xirq_start_mask_cycle
|
||
|
|
= cpu_current_cycle (interrupts->cpu);
|
||
|
|
}
|
||
|
|
else if (interrupts->xirq_start_mask_cycle >= 0
|
||
|
|
&& (ccr & M6811_X_BIT) == 0)
|
||
|
|
{
|
||
|
|
int64_t t = cpu_current_cycle (interrupts->cpu);
|
||
|
|
|
||
|
|
t -= interrupts->xirq_start_mask_cycle;
|
||
|
|
if (t < interrupts->xirq_min_mask_cycles)
|
||
|
|
interrupts->xirq_min_mask_cycles = t;
|
||
|
|
if (t > interrupts->xirq_max_mask_cycles)
|
||
|
|
interrupts->xirq_max_mask_cycles = t;
|
||
|
|
interrupts->xirq_start_mask_cycle = -1;
|
||
|
|
interrupts->xirq_last_mask_cycles = t;
|
||
|
|
}
|
||
|
|
|
||
|
|
id = interrupts_get_current (interrupts);
|
||
|
|
if (id >= 0)
|
||
|
|
{
|
||
|
|
uint16_t addr;
|
||
|
|
struct interrupt_history *h;
|
||
|
|
|
||
|
|
/* Implement the breakpoint-on-interrupt. */
|
||
|
|
if (interrupts->interrupts[id].stop_mode & SIM_STOP_WHEN_TAKEN)
|
||
|
|
{
|
||
|
|
sim_io_printf (CPU_STATE (interrupts->cpu),
|
||
|
|
"Interrupt %s will be handled\n",
|
||
|
|
interrupt_names[id]);
|
||
|
|
sim_engine_halt (CPU_STATE (interrupts->cpu),
|
||
|
|
interrupts->cpu,
|
||
|
|
0, cpu_get_pc (interrupts->cpu),
|
||
|
|
sim_stopped,
|
||
|
|
SIM_SIGTRAP);
|
||
|
|
}
|
||
|
|
|
||
|
|
cpu_push_all (interrupts->cpu);
|
||
|
|
addr = memory_read16 (interrupts->cpu,
|
||
|
|
interrupts->vectors_addr + id * 2);
|
||
|
|
cpu_call (interrupts->cpu, addr);
|
||
|
|
|
||
|
|
/* Now, protect from nested interrupts. */
|
||
|
|
if (id == M6811_INT_XIRQ)
|
||
|
|
{
|
||
|
|
cpu_set_ccr_X (interrupts->cpu, 1);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
cpu_set_ccr_I (interrupts->cpu, 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Update the interrupt history table. */
|
||
|
|
h = &interrupts->interrupts_history[interrupts->history_index];
|
||
|
|
h->type = id;
|
||
|
|
h->taken_cycle = cpu_current_cycle (interrupts->cpu);
|
||
|
|
h->raised_cycle = interrupts->interrupts[id].cpu_cycle;
|
||
|
|
|
||
|
|
if (interrupts->history_index >= MAX_INT_HISTORY-1)
|
||
|
|
interrupts->history_index = 0;
|
||
|
|
else
|
||
|
|
interrupts->history_index++;
|
||
|
|
|
||
|
|
interrupts->nb_interrupts_raised++;
|
||
|
|
cpu_add_cycles (interrupts->cpu, 14);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
interrupts_raise (struct interrupts *interrupts, enum M6811_INT number)
|
||
|
|
{
|
||
|
|
interrupts->pending_mask |= (1 << number);
|
||
|
|
interrupts->nb_interrupts_raised ++;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
|
||
|
|
{
|
||
|
|
int64_t t, prev_interrupt;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
sim_io_printf (sd, "Interrupts Info:\n");
|
||
|
|
sim_io_printf (sd, " Interrupts raised: %lu\n",
|
||
|
|
interrupts->nb_interrupts_raised);
|
||
|
|
|
||
|
|
if (interrupts->start_mask_cycle >= 0)
|
||
|
|
{
|
||
|
|
t = cpu_current_cycle (interrupts->cpu);
|
||
|
|
|
||
|
|
t -= interrupts->start_mask_cycle;
|
||
|
|
if (t > interrupts->max_mask_cycles)
|
||
|
|
interrupts->max_mask_cycles = t;
|
||
|
|
|
||
|
|
sim_io_printf (sd, " Current interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
}
|
||
|
|
t = interrupts->min_mask_cycles == CYCLES_MAX ?
|
||
|
|
interrupts->max_mask_cycles :
|
||
|
|
interrupts->min_mask_cycles;
|
||
|
|
sim_io_printf (sd, " Shortest interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
t = interrupts->max_mask_cycles;
|
||
|
|
sim_io_printf (sd, " Longest interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
t = interrupts->last_mask_cycles;
|
||
|
|
sim_io_printf (sd, " Last interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
if (interrupts->xirq_start_mask_cycle >= 0)
|
||
|
|
{
|
||
|
|
t = cpu_current_cycle (interrupts->cpu);
|
||
|
|
|
||
|
|
t -= interrupts->xirq_start_mask_cycle;
|
||
|
|
if (t > interrupts->xirq_max_mask_cycles)
|
||
|
|
interrupts->xirq_max_mask_cycles = t;
|
||
|
|
|
||
|
|
sim_io_printf (sd, " XIRQ Current interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
}
|
||
|
|
|
||
|
|
t = interrupts->xirq_min_mask_cycles == CYCLES_MAX ?
|
||
|
|
interrupts->xirq_max_mask_cycles :
|
||
|
|
interrupts->xirq_min_mask_cycles;
|
||
|
|
sim_io_printf (sd, " XIRQ Min interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
t = interrupts->xirq_max_mask_cycles;
|
||
|
|
sim_io_printf (sd, " XIRQ Max interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
t = interrupts->xirq_last_mask_cycles;
|
||
|
|
sim_io_printf (sd, " XIRQ Last interrupts masked sequence: %s\n",
|
||
|
|
cycle_to_string (interrupts->cpu, t,
|
||
|
|
PRINT_TIME | PRINT_CYCLE));
|
||
|
|
|
||
|
|
if (interrupts->pending_mask)
|
||
|
|
{
|
||
|
|
sim_io_printf (sd, " Pending interrupts : ");
|
||
|
|
for (i = 0; i < M6811_INT_NUMBER; i++)
|
||
|
|
{
|
||
|
|
enum M6811_INT int_number = interrupts->interrupt_order[i];
|
||
|
|
|
||
|
|
if (interrupts->pending_mask & (1 << int_number))
|
||
|
|
{
|
||
|
|
sim_io_printf (sd, "%s ", interrupt_names[int_number]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
sim_io_printf (sd, "\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
prev_interrupt = 0;
|
||
|
|
sim_io_printf (sd, "N Interrupt Cycle Taken Latency"
|
||
|
|
" Delta between interrupts\n");
|
||
|
|
for (i = 0; i < MAX_INT_HISTORY; i++)
|
||
|
|
{
|
||
|
|
int which;
|
||
|
|
struct interrupt_history *h;
|
||
|
|
int64_t dt;
|
||
|
|
|
||
|
|
which = interrupts->history_index - i - 1;
|
||
|
|
if (which < 0)
|
||
|
|
which += MAX_INT_HISTORY;
|
||
|
|
h = &interrupts->interrupts_history[which];
|
||
|
|
if (h->taken_cycle == 0)
|
||
|
|
break;
|
||
|
|
|
||
|
|
dt = h->taken_cycle - h->raised_cycle;
|
||
|
|
sim_io_printf (sd, "%2d %-9.9s %15.15s ", i,
|
||
|
|
interrupt_names[h->type],
|
||
|
|
cycle_to_string (interrupts->cpu, h->taken_cycle, 0));
|
||
|
|
sim_io_printf (sd, "%15.15s",
|
||
|
|
cycle_to_string (interrupts->cpu, dt, 0));
|
||
|
|
if (prev_interrupt)
|
||
|
|
{
|
||
|
|
dt = prev_interrupt - h->taken_cycle;
|
||
|
|
sim_io_printf (sd, " %s",
|
||
|
|
cycle_to_string (interrupts->cpu, dt, PRINT_TIME));
|
||
|
|
}
|
||
|
|
sim_io_printf (sd, "\n");
|
||
|
|
prev_interrupt = h->taken_cycle;
|
||
|
|
}
|
||
|
|
}
|