46 lines
2 KiB
Text
46 lines
2 KiB
Text
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<<<
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:sectnums:
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==== General Purpose Input and Output Port (GPIO)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_gpio.vhd |
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| Software driver file(s): | neorv32_gpio.c |
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| | neorv32_gpio.h |
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| Top entity port: | `gpio_o` | 64-bit parallel output port
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| | `gpio_i` | 64-bit parallel input port
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| Configuration generics: | _IO_GPIO_EN_ | implement GPIO port when _true_
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| CPU interrupts: | none |
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|=======================
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The general purpose parallel IO port unit provides a simple 64-bit parallel input port and a 64-bit parallel
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output port. These ports can be used chip-externally (for example to drive status LEDs, connect buttons, etc.)
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or chip-internally to provide control signals for other IP modules. The component is disabled for
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implementation when the _IO_GPIO_EN_ generic is set _false_. In this case the GPIO output port `gpio_o` is tied to all-zero.
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.Access Atomicity
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[NOTE]
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The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
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output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
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be performed within a single clock cycle.
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.INPUT is read-only
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[NOTE]
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Write accesses to the `NEORV32_GPIO.INPUT_LO` and `NEORV32_GPIO.INPUT_HI` registers will raise a store bus
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error exception. The BUSKEEPER will indicate a "DEVICE_ERR" in this case.
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**Register Map**
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.GPIO unit register map (`struct NEORV32_GPIO`)
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[cols="<2,<2,^1,^1,<6"]
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[options="header",grid="rows"]
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|=======================
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| Address | Name [C] | Bit(s) | R/W | Function
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| `0xffffffc0` | `NEORV32_GPIO.INPUT_LO` | 31:0 | r/- | parallel input port pins 31:0
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| `0xffffffc4` | `NEORV32_GPIO.INPUT_HI` | 31:0 | r/- | parallel input port pins 63:32
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| `0xffffffc8` | `NEORV32_GPIO.OUTPUT_LO` | 31:0 | r/w | parallel output port pins 31:0
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| `0xffffffcc` | `NEORV32_GPIO.OUTPUT_HI` | 31:0 | r/w | parallel output port pins 63:32
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|=======================
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