39 lines
1.9 KiB
Text
39 lines
1.9 KiB
Text
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<<<
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:sectnums:
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==== Data Memory (DMEM)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_dmem.entity.vhd | entity-only definition
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| | mem/neorv32_dmem.default.vhd | default _platform-agnostic_ memory architecture
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| Software driver file(s): | none | _implicitly used_
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| Top entity port: | none |
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| Configuration generics: | _MEM_INT_DMEM_EN_ | implement processor-internal DMEM when _true_
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| | _MEM_INT_DMEM_SIZE_ | DMEM size in bytes
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| CPU interrupts: | none |
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|=======================
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Implementation of the processor-internal data memory is enabled via the processor's _MEM_INT_DMEM_EN_
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generic. The size in bytes is defined via the _MEM_INT_DMEM_SIZE_ generic. If the DMEM is implemented,
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the memory is mapped into the data memory space and located right at the beginning of the data memory
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space (default `dspace_base_c` = 0x80000000). The DMEM is always implemented as true RAM.
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.Access Latency
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[NOTE]
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By default, the DMEM has a fixed access latency of one clock cycle (like all other processor-internal
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modules). However, custom versions of this module may also have higher access latency. See section <<_bus_interface>>
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for more information.
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.VHDL Source File
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[NOTE]
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The actual DMEM is split into two design files: a plain entity definition (`neorv32_dmem.entity.vhd`) and the actual
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architecture definition (`mem/neorv32_dmem.default.vhd`). This **default architecture** provides a _generic_ and
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_platform independent_ memory design that (should) infers embedded memory block. You can replace/modify the architecture
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source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
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and/or timing.
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.Execute from RAM
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[TIP]
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The CPU is capable of executing code also from DMEM.
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