354 lines
9.9 KiB
C
354 lines
9.9 KiB
C
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/*
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* DMA helper functions
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*
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* Copyright (c) 2009,2020 Red Hat
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*
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* This work is licensed under the terms of the GNU General Public License
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* (GNU GPL), version 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/dma.h"
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#include "trace/trace-root.h"
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#include "qemu/thread.h"
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#include "qemu/main-loop.h"
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#include "sysemu/cpu-timers.h"
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#include "qemu/range.h"
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/* #define DEBUG_IOMMU */
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MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr,
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uint8_t c, dma_addr_t len, MemTxAttrs attrs)
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{
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dma_barrier(as, DMA_DIRECTION_FROM_DEVICE);
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return address_space_set(as, addr, c, len, attrs);
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}
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void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint,
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AddressSpace *as)
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{
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qsg->sg = g_new(ScatterGatherEntry, alloc_hint);
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qsg->nsg = 0;
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qsg->nalloc = alloc_hint;
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qsg->size = 0;
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qsg->as = as;
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qsg->dev = dev;
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object_ref(OBJECT(dev));
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}
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void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
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{
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if (qsg->nsg == qsg->nalloc) {
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qsg->nalloc = 2 * qsg->nalloc + 1;
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qsg->sg = g_renew(ScatterGatherEntry, qsg->sg, qsg->nalloc);
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}
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qsg->sg[qsg->nsg].base = base;
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qsg->sg[qsg->nsg].len = len;
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qsg->size += len;
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++qsg->nsg;
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}
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void qemu_sglist_destroy(QEMUSGList *qsg)
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{
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object_unref(OBJECT(qsg->dev));
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g_free(qsg->sg);
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memset(qsg, 0, sizeof(*qsg));
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}
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typedef struct {
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BlockAIOCB common;
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AioContext *ctx;
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BlockAIOCB *acb;
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QEMUSGList *sg;
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uint32_t align;
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uint64_t offset;
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DMADirection dir;
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int sg_cur_index;
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dma_addr_t sg_cur_byte;
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QEMUIOVector iov;
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QEMUBH *bh;
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DMAIOFunc *io_func;
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void *io_func_opaque;
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} DMAAIOCB;
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static void dma_blk_cb(void *opaque, int ret);
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static void reschedule_dma(void *opaque)
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{
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DMAAIOCB *dbs = (DMAAIOCB *)opaque;
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assert(!dbs->acb && dbs->bh);
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qemu_bh_delete(dbs->bh);
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dbs->bh = NULL;
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dma_blk_cb(dbs, 0);
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}
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static void dma_blk_unmap(DMAAIOCB *dbs)
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{
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int i;
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for (i = 0; i < dbs->iov.niov; ++i) {
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dma_memory_unmap(dbs->sg->as, dbs->iov.iov[i].iov_base,
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dbs->iov.iov[i].iov_len, dbs->dir,
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dbs->iov.iov[i].iov_len);
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}
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qemu_iovec_reset(&dbs->iov);
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}
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static void dma_complete(DMAAIOCB *dbs, int ret)
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{
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trace_dma_complete(dbs, ret, dbs->common.cb);
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assert(!dbs->acb && !dbs->bh);
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dma_blk_unmap(dbs);
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if (dbs->common.cb) {
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dbs->common.cb(dbs->common.opaque, ret);
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}
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qemu_iovec_destroy(&dbs->iov);
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qemu_aio_unref(dbs);
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}
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static void dma_blk_cb(void *opaque, int ret)
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{
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DMAAIOCB *dbs = (DMAAIOCB *)opaque;
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dma_addr_t cur_addr, cur_len;
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void *mem;
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trace_dma_blk_cb(dbs, ret);
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dbs->acb = NULL;
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dbs->offset += dbs->iov.size;
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if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
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dma_complete(dbs, ret);
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return;
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}
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dma_blk_unmap(dbs);
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while (dbs->sg_cur_index < dbs->sg->nsg) {
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cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
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cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
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mem = dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir,
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MEMTXATTRS_UNSPECIFIED);
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/*
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* Make reads deterministic in icount mode. Windows sometimes issues
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* disk read requests with overlapping SGs. It leads
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* to non-determinism, because resulting buffer contents may be mixed
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* from several sectors. This code splits all SGs into several
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* groups. SGs in every group do not overlap.
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*/
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if (mem && icount_enabled() && dbs->dir == DMA_DIRECTION_FROM_DEVICE) {
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int i;
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for (i = 0 ; i < dbs->iov.niov ; ++i) {
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if (ranges_overlap((intptr_t)dbs->iov.iov[i].iov_base,
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dbs->iov.iov[i].iov_len, (intptr_t)mem,
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cur_len)) {
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dma_memory_unmap(dbs->sg->as, mem, cur_len,
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dbs->dir, cur_len);
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mem = NULL;
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break;
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}
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}
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}
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if (!mem)
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break;
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qemu_iovec_add(&dbs->iov, mem, cur_len);
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dbs->sg_cur_byte += cur_len;
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if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
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dbs->sg_cur_byte = 0;
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++dbs->sg_cur_index;
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}
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}
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if (dbs->iov.size == 0) {
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trace_dma_map_wait(dbs);
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dbs->bh = aio_bh_new(dbs->ctx, reschedule_dma, dbs);
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cpu_register_map_client(dbs->bh);
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return;
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}
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if (!QEMU_IS_ALIGNED(dbs->iov.size, dbs->align)) {
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qemu_iovec_discard_back(&dbs->iov,
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QEMU_ALIGN_DOWN(dbs->iov.size, dbs->align));
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}
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aio_context_acquire(dbs->ctx);
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dbs->acb = dbs->io_func(dbs->offset, &dbs->iov,
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dma_blk_cb, dbs, dbs->io_func_opaque);
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aio_context_release(dbs->ctx);
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assert(dbs->acb);
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}
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static void dma_aio_cancel(BlockAIOCB *acb)
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{
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DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
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trace_dma_aio_cancel(dbs);
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assert(!(dbs->acb && dbs->bh));
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if (dbs->acb) {
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/* This will invoke dma_blk_cb. */
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blk_aio_cancel_async(dbs->acb);
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return;
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}
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if (dbs->bh) {
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cpu_unregister_map_client(dbs->bh);
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qemu_bh_delete(dbs->bh);
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dbs->bh = NULL;
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}
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if (dbs->common.cb) {
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dbs->common.cb(dbs->common.opaque, -ECANCELED);
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}
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}
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static AioContext *dma_get_aio_context(BlockAIOCB *acb)
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{
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DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
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return dbs->ctx;
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}
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static const AIOCBInfo dma_aiocb_info = {
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.aiocb_size = sizeof(DMAAIOCB),
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.cancel_async = dma_aio_cancel,
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.get_aio_context = dma_get_aio_context,
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};
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BlockAIOCB *dma_blk_io(AioContext *ctx,
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QEMUSGList *sg, uint64_t offset, uint32_t align,
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DMAIOFunc *io_func, void *io_func_opaque,
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BlockCompletionFunc *cb,
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void *opaque, DMADirection dir)
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{
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DMAAIOCB *dbs = qemu_aio_get(&dma_aiocb_info, NULL, cb, opaque);
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trace_dma_blk_io(dbs, io_func_opaque, offset, (dir == DMA_DIRECTION_TO_DEVICE));
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dbs->acb = NULL;
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dbs->sg = sg;
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dbs->ctx = ctx;
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dbs->offset = offset;
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dbs->align = align;
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dbs->sg_cur_index = 0;
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dbs->sg_cur_byte = 0;
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dbs->dir = dir;
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dbs->io_func = io_func;
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dbs->io_func_opaque = io_func_opaque;
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dbs->bh = NULL;
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qemu_iovec_init(&dbs->iov, sg->nsg);
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dma_blk_cb(dbs, 0);
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return &dbs->common;
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}
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static
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BlockAIOCB *dma_blk_read_io_func(int64_t offset, QEMUIOVector *iov,
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BlockCompletionFunc *cb, void *cb_opaque,
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void *opaque)
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{
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BlockBackend *blk = opaque;
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return blk_aio_preadv(blk, offset, iov, 0, cb, cb_opaque);
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}
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BlockAIOCB *dma_blk_read(BlockBackend *blk,
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QEMUSGList *sg, uint64_t offset, uint32_t align,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
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dma_blk_read_io_func, blk, cb, opaque,
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DMA_DIRECTION_FROM_DEVICE);
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}
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static
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BlockAIOCB *dma_blk_write_io_func(int64_t offset, QEMUIOVector *iov,
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BlockCompletionFunc *cb, void *cb_opaque,
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void *opaque)
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{
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BlockBackend *blk = opaque;
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return blk_aio_pwritev(blk, offset, iov, 0, cb, cb_opaque);
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}
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BlockAIOCB *dma_blk_write(BlockBackend *blk,
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QEMUSGList *sg, uint64_t offset, uint32_t align,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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return dma_blk_io(blk_get_aio_context(blk), sg, offset, align,
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dma_blk_write_io_func, blk, cb, opaque,
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DMA_DIRECTION_TO_DEVICE);
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}
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static MemTxResult dma_buf_rw(void *buf, dma_addr_t len, dma_addr_t *residual,
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QEMUSGList *sg, DMADirection dir,
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MemTxAttrs attrs)
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{
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uint8_t *ptr = buf;
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dma_addr_t xresidual;
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int sg_cur_index;
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MemTxResult res = MEMTX_OK;
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xresidual = sg->size;
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sg_cur_index = 0;
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len = MIN(len, xresidual);
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while (len > 0) {
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ScatterGatherEntry entry = sg->sg[sg_cur_index++];
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dma_addr_t xfer = MIN(len, entry.len);
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res |= dma_memory_rw(sg->as, entry.base, ptr, xfer, dir, attrs);
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ptr += xfer;
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len -= xfer;
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xresidual -= xfer;
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}
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if (residual) {
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*residual = xresidual;
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}
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return res;
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}
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MemTxResult dma_buf_read(void *ptr, dma_addr_t len, dma_addr_t *residual,
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QEMUSGList *sg, MemTxAttrs attrs)
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{
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return dma_buf_rw(ptr, len, residual, sg, DMA_DIRECTION_FROM_DEVICE, attrs);
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}
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MemTxResult dma_buf_write(void *ptr, dma_addr_t len, dma_addr_t *residual,
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QEMUSGList *sg, MemTxAttrs attrs)
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{
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return dma_buf_rw(ptr, len, residual, sg, DMA_DIRECTION_TO_DEVICE, attrs);
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}
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void dma_acct_start(BlockBackend *blk, BlockAcctCookie *cookie,
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QEMUSGList *sg, enum BlockAcctType type)
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{
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block_acct_start(blk_get_stats(blk), cookie, sg->size, type);
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}
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uint64_t dma_aligned_pow2_mask(uint64_t start, uint64_t end, int max_addr_bits)
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{
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uint64_t max_mask = UINT64_MAX, addr_mask = end - start;
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uint64_t alignment_mask, size_mask;
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if (max_addr_bits != 64) {
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max_mask = (1ULL << max_addr_bits) - 1;
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}
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alignment_mask = start ? (start & -start) - 1 : max_mask;
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alignment_mask = MIN(alignment_mask, max_mask);
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size_mask = MIN(addr_mask, max_mask);
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if (alignment_mask <= size_mask) {
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/* Increase the alignment of start */
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return alignment_mask;
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} else {
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/* Find the largest page mask from size */
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if (addr_mask == UINT64_MAX) {
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return UINT64_MAX;
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}
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return (1ULL << (63 - clz64(addr_mask + 1))) - 1;
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}
|
||
|
|
}
|
||
|
|
|