303 lines
9.1 KiB
C
303 lines
9.1 KiB
C
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/*
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* pcie_sriov.c:
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*
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* Implementation of SR/IOV emulation support.
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*
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* Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "trace.h"
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static PCIDevice *register_vf(PCIDevice *pf, int devfn,
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const char *name, uint16_t vf_num);
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static void unregister_vfs(PCIDevice *dev);
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void pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset,
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const char *vfname, uint16_t vf_dev_id,
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uint16_t init_vfs, uint16_t total_vfs,
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uint16_t vf_offset, uint16_t vf_stride)
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{
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uint8_t *cfg = dev->config + offset;
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uint8_t *wmask;
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pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1,
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offset, PCI_EXT_CAP_SRIOV_SIZEOF);
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dev->exp.sriov_cap = offset;
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dev->exp.sriov_pf.num_vfs = 0;
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dev->exp.sriov_pf.vfname = g_strdup(vfname);
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dev->exp.sriov_pf.vf = NULL;
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pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset);
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pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride);
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/*
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* Mandatory page sizes to support.
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* Device implementations can call pcie_sriov_pf_add_sup_pgsize()
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* to set more bits:
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*/
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pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ);
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/*
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* Default is to use 4K pages, software can modify it
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* to any of the supported bits
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*/
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pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1);
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/* Set up device ID and initial/total number of VFs available */
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pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id);
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pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs);
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pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs);
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pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0);
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/* Write enable control bits */
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wmask = dev->wmask + offset;
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pci_set_word(wmask + PCI_SRIOV_CTRL,
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PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI);
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pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff);
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pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553);
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qdev_prop_set_bit(&dev->qdev, "multifunction", true);
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}
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void pcie_sriov_pf_exit(PCIDevice *dev)
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{
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unregister_vfs(dev);
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g_free((char *)dev->exp.sriov_pf.vfname);
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dev->exp.sriov_pf.vfname = NULL;
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}
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void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num,
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uint8_t type, dma_addr_t size)
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{
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uint32_t addr;
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uint64_t wmask;
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uint16_t sriov_cap = dev->exp.sriov_cap;
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assert(sriov_cap > 0);
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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assert(region_num != PCI_ROM_SLOT);
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wmask = ~(size - 1);
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addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4;
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pci_set_long(dev->config + addr, type);
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if (!(type & PCI_BASE_ADDRESS_SPACE_IO) &&
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type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->wmask + addr, wmask);
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pci_set_quad(dev->cmask + addr, ~0ULL);
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} else {
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pci_set_long(dev->wmask + addr, wmask & 0xffffffff);
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pci_set_long(dev->cmask + addr, 0xffffffff);
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}
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dev->exp.sriov_pf.vf_bar_type[region_num] = type;
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}
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void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num,
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MemoryRegion *memory)
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{
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PCIIORegion *r;
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PCIBus *bus = pci_get_bus(dev);
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uint8_t type;
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pcibus_t size = memory_region_size(memory);
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assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */
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assert(region_num >= 0);
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assert(region_num < PCI_NUM_REGIONS);
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type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num];
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if (!is_power_of_2(size)) {
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error_report("%s: PCI region size must be a power"
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" of two - type=0x%x, size=0x%"FMT_PCIBUS,
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__func__, type, size);
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exit(1);
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}
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r = &dev->io_regions[region_num];
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r->memory = memory;
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r->address_space =
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type & PCI_BASE_ADDRESS_SPACE_IO
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? bus->address_space_io
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: bus->address_space_mem;
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r->size = size;
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r->type = type;
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r->addr = pci_bar_address(dev, region_num, r->type, r->size);
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if (r->addr != PCI_BAR_UNMAPPED) {
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memory_region_add_subregion_overlap(r->address_space,
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r->addr, r->memory, 1);
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}
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}
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static PCIDevice *register_vf(PCIDevice *pf, int devfn, const char *name,
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uint16_t vf_num)
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{
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PCIDevice *dev = pci_new(devfn, name);
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dev->exp.sriov_vf.pf = pf;
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dev->exp.sriov_vf.vf_number = vf_num;
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PCIBus *bus = pci_get_bus(pf);
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Error *local_err = NULL;
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qdev_realize(&dev->qdev, &bus->qbus, &local_err);
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if (local_err) {
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error_report_err(local_err);
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return NULL;
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}
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/* set vid/did according to sr/iov spec - they are not used */
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pci_config_set_vendor_id(dev->config, 0xffff);
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pci_config_set_device_id(dev->config, 0xffff);
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return dev;
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}
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static void register_vfs(PCIDevice *dev)
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{
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uint16_t num_vfs;
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uint16_t i;
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uint16_t sriov_cap = dev->exp.sriov_cap;
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uint16_t vf_offset =
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pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_OFFSET);
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uint16_t vf_stride =
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pci_get_word(dev->config + sriov_cap + PCI_SRIOV_VF_STRIDE);
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int32_t devfn = dev->devfn + vf_offset;
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assert(sriov_cap > 0);
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num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF);
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dev->exp.sriov_pf.vf = g_new(PCIDevice *, num_vfs);
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assert(dev->exp.sriov_pf.vf);
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trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), num_vfs);
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for (i = 0; i < num_vfs; i++) {
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dev->exp.sriov_pf.vf[i] = register_vf(dev, devfn,
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dev->exp.sriov_pf.vfname, i);
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if (!dev->exp.sriov_pf.vf[i]) {
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num_vfs = i;
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break;
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}
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devfn += vf_stride;
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}
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dev->exp.sriov_pf.num_vfs = num_vfs;
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}
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static void unregister_vfs(PCIDevice *dev)
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{
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Error *local_err = NULL;
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uint16_t num_vfs = dev->exp.sriov_pf.num_vfs;
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uint16_t i;
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trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), num_vfs);
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for (i = 0; i < num_vfs; i++) {
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PCIDevice *vf = dev->exp.sriov_pf.vf[i];
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object_property_set_bool(OBJECT(vf), "realized", false, &local_err);
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if (local_err) {
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fprintf(stderr, "Failed to unplug: %s\n",
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error_get_pretty(local_err));
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error_free(local_err);
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}
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object_unparent(OBJECT(vf));
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}
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g_free(dev->exp.sriov_pf.vf);
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dev->exp.sriov_pf.vf = NULL;
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dev->exp.sriov_pf.num_vfs = 0;
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pci_set_word(dev->config + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0);
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}
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void pcie_sriov_config_write(PCIDevice *dev, uint32_t address,
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uint32_t val, int len)
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{
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uint32_t off;
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uint16_t sriov_cap = dev->exp.sriov_cap;
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if (!sriov_cap || address < sriov_cap) {
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return;
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}
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off = address - sriov_cap;
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if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) {
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return;
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}
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trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn), off, val, len);
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if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) {
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if (dev->exp.sriov_pf.num_vfs) {
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if (!(val & PCI_SRIOV_CTRL_VFE)) {
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unregister_vfs(dev);
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}
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} else {
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if (val & PCI_SRIOV_CTRL_VFE) {
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register_vfs(dev);
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}
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}
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}
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}
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/* Reset SR/IOV VF Enable bit to trigger an unregister of all VFs */
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void pcie_sriov_pf_disable_vfs(PCIDevice *dev)
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{
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uint16_t sriov_cap = dev->exp.sriov_cap;
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if (sriov_cap) {
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uint32_t val = pci_get_byte(dev->config + sriov_cap + PCI_SRIOV_CTRL);
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if (val & PCI_SRIOV_CTRL_VFE) {
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val &= ~PCI_SRIOV_CTRL_VFE;
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pcie_sriov_config_write(dev, sriov_cap + PCI_SRIOV_CTRL, val, 1);
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}
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}
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}
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/* Add optional supported page sizes to the mask of supported page sizes */
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void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize)
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{
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uint8_t *cfg = dev->config + dev->exp.sriov_cap;
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uint8_t *wmask = dev->wmask + dev->exp.sriov_cap;
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uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE);
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sup_pgsize |= opt_sup_pgsize;
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/*
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* Make sure the new bits are set, and that system page size
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* also can be set to any of the new values according to spec:
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*/
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pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize);
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pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize);
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}
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uint16_t pcie_sriov_vf_number(PCIDevice *dev)
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{
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assert(pci_is_vf(dev));
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return dev->exp.sriov_vf.vf_number;
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}
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PCIDevice *pcie_sriov_get_pf(PCIDevice *dev)
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{
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return dev->exp.sriov_vf.pf;
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}
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PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n)
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{
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assert(!pci_is_vf(dev));
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if (n < dev->exp.sriov_pf.num_vfs) {
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return dev->exp.sriov_pf.vf[n];
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}
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return NULL;
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}
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