Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/v850/mul.cgs

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2023-03-06 14:48:14 +01:00
# v850e mul
# mach: v850e
# as(v850e): -mv850e
.include "testutils.inc"
# Trivial regression test for incorrect sign bit handling in mul
seti -10, r1
seti 2, r2
mul r1, r2, r3
reg r2, -20
reg r3, -1
pass