231 lines
9 KiB
C
231 lines
9 KiB
C
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/* Profiling definitions for the FRV simulator
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Copyright (C) 1998-2022 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef PROFILE_H
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#define PROFILE_H
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#include "frv-desc.h"
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/* This struct defines the state of profiling. All fields are of general
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use to all machines. */
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typedef struct
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{
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long vliw_insns; /* total number of VLIW insns. */
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long vliw_wait; /* number of cycles that the current VLIW insn must wait. */
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long post_wait; /* number of cycles that post processing in the current
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VLIW insn must wait. */
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long vliw_cycles;/* number of cycles used by current VLIW insn. */
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int past_first_p; /* Not the first insns in the VLIW */
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/* Register latencies. Must be signed since they can be temporarily
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negative. */
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int gr_busy[64]; /* Cycles until GR is available. */
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int fr_busy[64]; /* Cycles until FR is available. */
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int acc_busy[64]; /* Cycles until FR is available. */
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int ccr_busy[8]; /* Cycles until ICC/FCC is available. */
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int spr_busy[4096]; /* Cycles until spr is available. */
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int idiv_busy[2]; /* Cycles until integer division unit is available. */
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int fdiv_busy[2]; /* Cycles until float division unit is available. */
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int fsqrt_busy[2]; /* Cycles until square root unit is available. */
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int float_busy[4]; /* Cycles until floating point unit is available. */
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int media_busy[4]; /* Cycles until media unit is available. */
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int branch_penalty; /* Cycles until branch is complete. */
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int gr_latency[64]; /* Cycles until target GR is available. */
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int fr_latency[64]; /* Cycles until target FR is available. */
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int acc_latency[64]; /* Cycles until target FR is available. */
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int ccr_latency[8]; /* Cycles until target ICC/FCC is available. */
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int spr_latency[4096]; /* Cycles until target spr is available. */
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/* Some registers are busy for a shorter number of cycles than normal
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depending on how they are used next. the xxx_busy_adjust arrays keep track
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of how many cycles to adjust down.
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*/
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int fr_busy_adjust[64];
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int acc_busy_adjust[64];
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/* Register flags. Each bit represents one register. */
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DI cur_gr_complex;
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DI prev_gr_complex;
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/* Keep track of the total queued post-processing time required before a
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resource is available. This is applied to the resource's latency once all
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pending loads for the resource are completed. */
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int fr_ptime[64];
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int branch_hint; /* hint field from branch insn. */
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USI branch_address; /* Address of predicted branch. */
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USI insn_fetch_address;/* Address of sequential insns fetched. */
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int mclracc_acc; /* ACC number of register cleared by mclracc. */
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int mclracc_A; /* A field of mclracc. */
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/* We need to know when the first branch of a vliw insn is taken, so that
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we don't consider the remaining branches in the vliw insn. */
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int vliw_branch_taken;
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/* Keep track of the maximum load stall for each VLIW insn. */
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int vliw_load_stall;
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/* Need to know if all cache entries are affected by various cache
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operations. */
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int all_cache_entries;
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} FRV_PROFILE_STATE;
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#define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1)
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#define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1)
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/* Return the GNER register associated with the given GR register.
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There is no GNER associated with gr0. */
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#define GNER_FOR_GR(gr) ((gr) > 63 ? -1 : \
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(gr) > 31 ? H_SPR_GNER0 : \
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(gr) > 0 ? H_SPR_GNER1 : \
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-1)
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/* Return the GNER register associated with the given GR register.
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There is no GNER associated with gr0. */
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#define FNER_FOR_FR(fr) ((fr) > 63 ? -1 : \
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(fr) > 31 ? H_SPR_FNER0 : \
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(fr) > 0 ? H_SPR_FNER1 : \
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-1)
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/* Top up the latency of the given GR by the given number of cycles. */
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void update_GR_latency (SIM_CPU *, INT, int);
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void update_GRdouble_latency (SIM_CPU *, INT, int);
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void update_GR_latency_for_load (SIM_CPU *, INT, int);
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void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
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void update_GR_latency_for_swap (SIM_CPU *, INT, int);
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void update_FR_latency (SIM_CPU *, INT, int);
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void update_FRdouble_latency (SIM_CPU *, INT, int);
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void update_FR_latency_for_load (SIM_CPU *, INT, int);
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void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
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void update_FR_ptime (SIM_CPU *, INT, int);
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void update_FRdouble_ptime (SIM_CPU *, INT, int);
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void decrease_ACC_busy (SIM_CPU *, INT, int);
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void decrease_FR_busy (SIM_CPU *, INT, int);
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void decrease_GR_busy (SIM_CPU *, INT, int);
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void increase_FR_busy (SIM_CPU *, INT, int);
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void increase_ACC_busy (SIM_CPU *, INT, int);
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void update_ACC_latency (SIM_CPU *, INT, int);
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void update_CCR_latency (SIM_CPU *, INT, int);
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void update_SPR_latency (SIM_CPU *, INT, int);
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void update_idiv_resource_latency (SIM_CPU *, INT, int);
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void update_fdiv_resource_latency (SIM_CPU *, INT, int);
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void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
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void update_float_resource_latency (SIM_CPU *, INT, int);
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void update_media_resource_latency (SIM_CPU *, INT, int);
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void update_branch_penalty (SIM_CPU *, int);
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void update_ACC_ptime (SIM_CPU *, INT, int);
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void update_SPR_ptime (SIM_CPU *, INT, int);
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void vliw_wait_for_GR (SIM_CPU *, INT);
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void vliw_wait_for_GRdouble (SIM_CPU *, INT);
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void vliw_wait_for_FR (SIM_CPU *, INT);
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void vliw_wait_for_FRdouble (SIM_CPU *, INT);
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void vliw_wait_for_CCR (SIM_CPU *, INT);
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void vliw_wait_for_ACC (SIM_CPU *, INT);
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void vliw_wait_for_SPR (SIM_CPU *, INT);
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void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
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void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
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void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
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void vliw_wait_for_float_resource (SIM_CPU *, INT);
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void vliw_wait_for_media_resource (SIM_CPU *, INT);
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void load_wait_for_GR (SIM_CPU *, INT);
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void load_wait_for_FR (SIM_CPU *, INT);
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void load_wait_for_GRdouble (SIM_CPU *, INT);
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void load_wait_for_FRdouble (SIM_CPU *, INT);
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void enforce_full_fr_latency (SIM_CPU *, INT);
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void enforce_full_acc_latency (SIM_CPU *, INT);
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void post_wait_for_FR (SIM_CPU *, INT);
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void post_wait_for_FRdouble (SIM_CPU *, INT);
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void post_wait_for_ACC (SIM_CPU *, INT);
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void post_wait_for_CCR (SIM_CPU *, INT);
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void post_wait_for_SPR (SIM_CPU *, INT);
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void post_wait_for_fdiv (SIM_CPU *, INT);
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void post_wait_for_fsqrt (SIM_CPU *, INT);
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void post_wait_for_float (SIM_CPU *, INT);
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void post_wait_for_media (SIM_CPU *, INT);
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void trace_vliw_wait_cycles (SIM_CPU *);
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void handle_resource_wait (SIM_CPU *);
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void request_cache_load (SIM_CPU *, INT, int, int);
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void request_cache_flush (SIM_CPU *, FRV_CACHE *, int);
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void request_cache_invalidate (SIM_CPU *, FRV_CACHE *, int);
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void request_cache_preload (SIM_CPU *, FRV_CACHE *, int);
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void request_cache_unlock (SIM_CPU *, FRV_CACHE *, int);
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int load_pending_for_register (SIM_CPU *, int, int, int);
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void set_use_is_gr_complex (SIM_CPU *, INT);
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void set_use_not_gr_complex (SIM_CPU *, INT);
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int use_is_gr_complex (SIM_CPU *, INT);
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typedef struct
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{
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SI address;
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unsigned reqno;
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} FRV_INSN_FETCH_BUFFER;
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extern FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[];
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PROFILE_INFO_CPU_CALLBACK_FN frv_profile_info;
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enum {
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/* Simulator specific profile bits begin here. */
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/* Profile caches. */
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PROFILE_CACHE_IDX = PROFILE_NEXT_IDX,
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/* Profile parallelization. */
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PROFILE_PARALLEL_IDX
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};
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/* Masks so WITH_PROFILE can have symbolic values.
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The case choice here is on purpose. The lowercase parts are args to
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--with-profile. */
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#define PROFILE_cache (1 << PROFILE_INSN_IDX)
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#define PROFILE_parallel (1 << PROFILE_INSN_IDX)
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/* Preprocessor macros to simplify tests of WITH_PROFILE. */
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#define WITH_PROFILE_CACHE_P (WITH_PROFILE & PROFILE_insn)
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#define WITH_PROFILE_PARALLEL_P (WITH_PROFILE & PROFILE_insn)
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#define FRV_COUNT_CYCLES(cpu, condition) \
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((PROFILE_MODEL_P (cpu) && (condition)) || frv_interrupt_state.timer.enabled)
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/* Modelling support. */
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extern int frv_save_profile_model_p;
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extern enum FRV_INSN_MODELING {
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FRV_INSN_NO_MODELING = 0,
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FRV_INSN_MODEL_PASS_1,
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FRV_INSN_MODEL_PASS_2,
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FRV_INSN_MODEL_WRITEBACK
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} model_insn;
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void
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frv_model_advance_cycles (SIM_CPU *, int);
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void
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frv_model_trace_wait_cycles (SIM_CPU *, int, const char *);
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/* Register types for queued load requests. */
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#define REGTYPE_NONE 0
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#define REGTYPE_FR 1
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#define REGTYPE_ACC 2
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SI frv_ref_SI (SI);
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#endif /* PROFILE_H */
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