2022-10-14 13:21:36 +02:00
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//! Driver for the UART.
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use core::arch::asm;
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use core::fmt;
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use crate::traits::console::{Write, Console};
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2022-10-16 17:14:01 +02:00
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use super::memory_map::uart as mm;
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2022-10-14 13:21:36 +02:00
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2022-10-16 17:14:01 +02:00
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pub struct Uart<'a> {
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initialized: bool,
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memory_map: &'a mm::UartMemoryMap,
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}
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impl<'a> Uart<'a> {
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2022-10-14 13:21:36 +02:00
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// TODO: not sure this should be public outside of bsp.
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/// Constructor for [`Uart`].
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pub const fn new(memory_map: &'a mm::UartMemoryMap) -> Self {
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Uart { initialized: false, memory_map }
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}
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/// Initialise the UART.
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pub fn init(&mut self) {
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// TODO: Recover from possible previous test.
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self.flush();
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// Stop UART
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self.memory_map.cr_uarten.read_and_write(0);
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// Flush the FIFOs
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self.memory_map.lcrh_fen.read_and_write(0);
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// Clear all interrupt
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self.memory_map.icr.write_without_read(0);
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// Config UART
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// 8N1 115_200 bauds.
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// divbaud = freq/16/baudrate = 48_000_000 / 16 / 115_200 = 26.041666666666668
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// => IBRD = 26
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// => FBRD = round(0.041666666666668 * 64) = 3 // TODO: why 64?
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self.memory_map.ibrd.write_without_read(26);
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self.memory_map.fbrd.write_without_read(3);
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// Set word len to 8
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let lcrh_val = self.memory_map.lcrh_wlen.read_and_write_to_u32(0b11, 0);
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// Reenable the FIFOs
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let lcrh_val = self.memory_map.lcrh_fen.read_and_write_to_u32(1, lcrh_val);
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self.memory_map.lcrh.write_without_read(lcrh_val);
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let cr_val = self.memory_map.cr_txe.read_and_write_to_u32(1, 0);
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// TODO: let cr_val = self.memory_map.cr_rxe.read_and_write_to_u32(1, 0); to enable read
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self.memory_map.cr.write_without_read(cr_val);
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// Start the UART
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self.memory_map.cr_uarten.read_and_write(1);
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self.initialized = true;
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}
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/// Test if the UART is busy.
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fn is_busy(&self) -> bool {
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self.memory_map.fr_busy.read() != 0
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}
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/// Test if the the TX FIFO is full.
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fn is_tx_full(&self) -> bool {
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self.memory_map.fr_txff.read() != 0
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}
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}
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// Allow the use of uart for fmt::Write::write_fmt.
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impl fmt::Write for Uart<'_> {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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for c in s.chars() {
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if c == '\n' {
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Write::write_char(self, '\r');
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}
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Write::write_char(self, c);
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}
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Ok(())
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}
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}
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// TODO: add sync
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impl Write for Uart<'_> {
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fn write_char(&self, c: char) {
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if !self.initialized {
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//panic!("Cannot write to a non initialized UART");
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}
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while self.is_tx_full() {
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use super::gpio;
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let _ = gpio::set_pin_output_state(20, gpio::PinOutputState::High);
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unsafe { asm!("nop") };
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}
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self.memory_map.dr_data.write_without_read(c as u32);
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}
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fn write_fmt(&self, args: fmt::Arguments) -> fmt::Result {
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// TODO: use syncronisation here
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let mut new_uart = Uart { initialized: self.initialized, memory_map: self.memory_map};
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fmt::Write::write_fmt(&mut new_uart, args)
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}
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fn flush(&self) {
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while self.is_busy() {
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unsafe { asm!("nop") };
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}
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}
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}
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impl Console for Uart<'_> {}
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static UART: Uart = Uart { initialized: true, memory_map: &mm::UART }; // TODO: use sync
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pub fn init() {
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let mut uart = Uart::new(&mm::UART);
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uart.init();
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}
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// TODO: move?
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/// Return a reference to the Uart Output.
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pub fn console() -> &'static dyn Console {
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&UART
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}
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