leo/Space_Invaders
1
0
Fork 0
Code Issues Pull requests Projects Releases 1 Wiki Activity
Space_Invaders/Debug/Space_Invaders.list
Thomas 67601bf20c Interruption bouton fonctionnelle
2021-04-20 14:32:06 +02:00

75225 lines
2.8 MiB
Raw Blame History

Space_Invaders.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0001bc9c 080001d0 080001d0 000101d0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000050b4 0801be6c 0801be6c 0002be6c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08020f20 08020f20 000400e8 2**0
CONTENTS
4 .ARM 00000008 08020f20 08020f20 00030f20 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08020f28 08020f28 000400e8 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08020f28 08020f28 00030f28 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08020f2c 08020f2c 00030f2c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 000000e8 20000000 08020f30 00040000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000f524 200000e8 08021018 000400e8 2**2
ALLOC
10 ._user_heap_stack 00000604 2000f60c 08021018 0004f60c 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 000400e8 2**0
CONTENTS, READONLY
12 .debug_info 00050ade 00000000 00000000 00040118 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 000096fb 00000000 00000000 00090bf6 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 000030e8 00000000 00000000 0009a2f8 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00002e30 00000000 00000000 0009d3e0 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 0003bc39 00000000 00000000 000a0210 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 0003910d 00000000 00000000 000dbe49 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 00127a3a 00000000 00000000 00114f56 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 0023c990 2**0
CONTENTS, READONLY
20 .debug_frame 0000d120 00000000 00000000 0023ca0c 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080001d0 <__do_global_dtors_aux>:
80001d0: b510 push {r4, lr}
80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
80001d4: 7823 ldrb r3, [r4, #0]
80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
80001de: f3af 8000 nop.w
80001e2: 2301 movs r3, #1
80001e4: 7023 strb r3, [r4, #0]
80001e6: bd10 pop {r4, pc}
80001e8: 200000e8 .word 0x200000e8
80001ec: 00000000 .word 0x00000000
80001f0: 0801be54 .word 0x0801be54
080001f4 <frame_dummy>:
80001f4: b508 push {r3, lr}
80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 <frame_dummy+0x10>)
80001f8: b11b cbz r3, 8000202 <frame_dummy+0xe>
80001fa: 4903 ldr r1, [pc, #12] ; (8000208 <frame_dummy+0x14>)
80001fc: 4803 ldr r0, [pc, #12] ; (800020c <frame_dummy+0x18>)
80001fe: f3af 8000 nop.w
8000202: bd08 pop {r3, pc}
8000204: 00000000 .word 0x00000000
8000208: 200000ec .word 0x200000ec
800020c: 0801be54 .word 0x0801be54
08000210 <memchr>:
8000210: f001 01ff and.w r1, r1, #255 ; 0xff
8000214: 2a10 cmp r2, #16
8000216: db2b blt.n 8000270 <memchr+0x60>
8000218: f010 0f07 tst.w r0, #7
800021c: d008 beq.n 8000230 <memchr+0x20>
800021e: f810 3b01 ldrb.w r3, [r0], #1
8000222: 3a01 subs r2, #1
8000224: 428b cmp r3, r1
8000226: d02d beq.n 8000284 <memchr+0x74>
8000228: f010 0f07 tst.w r0, #7
800022c: b342 cbz r2, 8000280 <memchr+0x70>
800022e: d1f6 bne.n 800021e <memchr+0xe>
8000230: b4f0 push {r4, r5, r6, r7}
8000232: ea41 2101 orr.w r1, r1, r1, lsl #8
8000236: ea41 4101 orr.w r1, r1, r1, lsl #16
800023a: f022 0407 bic.w r4, r2, #7
800023e: f07f 0700 mvns.w r7, #0
8000242: 2300 movs r3, #0
8000244: e8f0 5602 ldrd r5, r6, [r0], #8
8000248: 3c08 subs r4, #8
800024a: ea85 0501 eor.w r5, r5, r1
800024e: ea86 0601 eor.w r6, r6, r1
8000252: fa85 f547 uadd8 r5, r5, r7
8000256: faa3 f587 sel r5, r3, r7
800025a: fa86 f647 uadd8 r6, r6, r7
800025e: faa5 f687 sel r6, r5, r7
8000262: b98e cbnz r6, 8000288 <memchr+0x78>
8000264: d1ee bne.n 8000244 <memchr+0x34>
8000266: bcf0 pop {r4, r5, r6, r7}
8000268: f001 01ff and.w r1, r1, #255 ; 0xff
800026c: f002 0207 and.w r2, r2, #7
8000270: b132 cbz r2, 8000280 <memchr+0x70>
8000272: f810 3b01 ldrb.w r3, [r0], #1
8000276: 3a01 subs r2, #1
8000278: ea83 0301 eor.w r3, r3, r1
800027c: b113 cbz r3, 8000284 <memchr+0x74>
800027e: d1f8 bne.n 8000272 <memchr+0x62>
8000280: 2000 movs r0, #0
8000282: 4770 bx lr
8000284: 3801 subs r0, #1
8000286: 4770 bx lr
8000288: 2d00 cmp r5, #0
800028a: bf06 itte eq
800028c: 4635 moveq r5, r6
800028e: 3803 subeq r0, #3
8000290: 3807 subne r0, #7
8000292: f015 0f01 tst.w r5, #1
8000296: d107 bne.n 80002a8 <memchr+0x98>
8000298: 3001 adds r0, #1
800029a: f415 7f80 tst.w r5, #256 ; 0x100
800029e: bf02 ittt eq
80002a0: 3001 addeq r0, #1
80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
80002a6: 3001 addeq r0, #1
80002a8: bcf0 pop {r4, r5, r6, r7}
80002aa: 3801 subs r0, #1
80002ac: 4770 bx lr
80002ae: bf00 nop
080002b0 <__aeabi_uldivmod>:
80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18>
80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18>
80002b4: 2900 cmp r1, #0
80002b6: bf08 it eq
80002b8: 2800 cmpeq r0, #0
80002ba: bf1c itt ne
80002bc: f04f 31ff movne.w r1, #4294967295
80002c0: f04f 30ff movne.w r0, #4294967295
80002c4: f000 b972 b.w 80005ac <__aeabi_idiv0>
80002c8: f1ad 0c08 sub.w ip, sp, #8
80002cc: e96d ce04 strd ip, lr, [sp, #-16]!
80002d0: f000 f806 bl 80002e0 <__udivmoddi4>
80002d4: f8dd e004 ldr.w lr, [sp, #4]
80002d8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002dc: b004 add sp, #16
80002de: 4770 bx lr
080002e0 <__udivmoddi4>:
80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002e4: 9e08 ldr r6, [sp, #32]
80002e6: 4604 mov r4, r0
80002e8: 4688 mov r8, r1
80002ea: 2b00 cmp r3, #0
80002ec: d14b bne.n 8000386 <__udivmoddi4+0xa6>
80002ee: 428a cmp r2, r1
80002f0: 4615 mov r5, r2
80002f2: d967 bls.n 80003c4 <__udivmoddi4+0xe4>
80002f4: fab2 f282 clz r2, r2
80002f8: b14a cbz r2, 800030e <__udivmoddi4+0x2e>
80002fa: f1c2 0720 rsb r7, r2, #32
80002fe: fa01 f302 lsl.w r3, r1, r2
8000302: fa20 f707 lsr.w r7, r0, r7
8000306: 4095 lsls r5, r2
8000308: ea47 0803 orr.w r8, r7, r3
800030c: 4094 lsls r4, r2
800030e: ea4f 4e15 mov.w lr, r5, lsr #16
8000312: 0c23 lsrs r3, r4, #16
8000314: fbb8 f7fe udiv r7, r8, lr
8000318: fa1f fc85 uxth.w ip, r5
800031c: fb0e 8817 mls r8, lr, r7, r8
8000320: ea43 4308 orr.w r3, r3, r8, lsl #16
8000324: fb07 f10c mul.w r1, r7, ip
8000328: 4299 cmp r1, r3
800032a: d909 bls.n 8000340 <__udivmoddi4+0x60>
800032c: 18eb adds r3, r5, r3
800032e: f107 30ff add.w r0, r7, #4294967295
8000332: f080 811b bcs.w 800056c <__udivmoddi4+0x28c>
8000336: 4299 cmp r1, r3
8000338: f240 8118 bls.w 800056c <__udivmoddi4+0x28c>
800033c: 3f02 subs r7, #2
800033e: 442b add r3, r5
8000340: 1a5b subs r3, r3, r1
8000342: b2a4 uxth r4, r4
8000344: fbb3 f0fe udiv r0, r3, lr
8000348: fb0e 3310 mls r3, lr, r0, r3
800034c: ea44 4403 orr.w r4, r4, r3, lsl #16
8000350: fb00 fc0c mul.w ip, r0, ip
8000354: 45a4 cmp ip, r4
8000356: d909 bls.n 800036c <__udivmoddi4+0x8c>
8000358: 192c adds r4, r5, r4
800035a: f100 33ff add.w r3, r0, #4294967295
800035e: f080 8107 bcs.w 8000570 <__udivmoddi4+0x290>
8000362: 45a4 cmp ip, r4
8000364: f240 8104 bls.w 8000570 <__udivmoddi4+0x290>
8000368: 3802 subs r0, #2
800036a: 442c add r4, r5
800036c: ea40 4007 orr.w r0, r0, r7, lsl #16
8000370: eba4 040c sub.w r4, r4, ip
8000374: 2700 movs r7, #0
8000376: b11e cbz r6, 8000380 <__udivmoddi4+0xa0>
8000378: 40d4 lsrs r4, r2
800037a: 2300 movs r3, #0
800037c: e9c6 4300 strd r4, r3, [r6]
8000380: 4639 mov r1, r7
8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000386: 428b cmp r3, r1
8000388: d909 bls.n 800039e <__udivmoddi4+0xbe>
800038a: 2e00 cmp r6, #0
800038c: f000 80eb beq.w 8000566 <__udivmoddi4+0x286>
8000390: 2700 movs r7, #0
8000392: e9c6 0100 strd r0, r1, [r6]
8000396: 4638 mov r0, r7
8000398: 4639 mov r1, r7
800039a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800039e: fab3 f783 clz r7, r3
80003a2: 2f00 cmp r7, #0
80003a4: d147 bne.n 8000436 <__udivmoddi4+0x156>
80003a6: 428b cmp r3, r1
80003a8: d302 bcc.n 80003b0 <__udivmoddi4+0xd0>
80003aa: 4282 cmp r2, r0
80003ac: f200 80fa bhi.w 80005a4 <__udivmoddi4+0x2c4>
80003b0: 1a84 subs r4, r0, r2
80003b2: eb61 0303 sbc.w r3, r1, r3
80003b6: 2001 movs r0, #1
80003b8: 4698 mov r8, r3
80003ba: 2e00 cmp r6, #0
80003bc: d0e0 beq.n 8000380 <__udivmoddi4+0xa0>
80003be: e9c6 4800 strd r4, r8, [r6]
80003c2: e7dd b.n 8000380 <__udivmoddi4+0xa0>
80003c4: b902 cbnz r2, 80003c8 <__udivmoddi4+0xe8>
80003c6: deff udf #255 ; 0xff
80003c8: fab2 f282 clz r2, r2
80003cc: 2a00 cmp r2, #0
80003ce: f040 808f bne.w 80004f0 <__udivmoddi4+0x210>
80003d2: 1b49 subs r1, r1, r5
80003d4: ea4f 4e15 mov.w lr, r5, lsr #16
80003d8: fa1f f885 uxth.w r8, r5
80003dc: 2701 movs r7, #1
80003de: fbb1 fcfe udiv ip, r1, lr
80003e2: 0c23 lsrs r3, r4, #16
80003e4: fb0e 111c mls r1, lr, ip, r1
80003e8: ea43 4301 orr.w r3, r3, r1, lsl #16
80003ec: fb08 f10c mul.w r1, r8, ip
80003f0: 4299 cmp r1, r3
80003f2: d907 bls.n 8000404 <__udivmoddi4+0x124>
80003f4: 18eb adds r3, r5, r3
80003f6: f10c 30ff add.w r0, ip, #4294967295
80003fa: d202 bcs.n 8000402 <__udivmoddi4+0x122>
80003fc: 4299 cmp r1, r3
80003fe: f200 80cd bhi.w 800059c <__udivmoddi4+0x2bc>
8000402: 4684 mov ip, r0
8000404: 1a59 subs r1, r3, r1
8000406: b2a3 uxth r3, r4
8000408: fbb1 f0fe udiv r0, r1, lr
800040c: fb0e 1410 mls r4, lr, r0, r1
8000410: ea43 4404 orr.w r4, r3, r4, lsl #16
8000414: fb08 f800 mul.w r8, r8, r0
8000418: 45a0 cmp r8, r4
800041a: d907 bls.n 800042c <__udivmoddi4+0x14c>
800041c: 192c adds r4, r5, r4
800041e: f100 33ff add.w r3, r0, #4294967295
8000422: d202 bcs.n 800042a <__udivmoddi4+0x14a>
8000424: 45a0 cmp r8, r4
8000426: f200 80b6 bhi.w 8000596 <__udivmoddi4+0x2b6>
800042a: 4618 mov r0, r3
800042c: eba4 0408 sub.w r4, r4, r8
8000430: ea40 400c orr.w r0, r0, ip, lsl #16
8000434: e79f b.n 8000376 <__udivmoddi4+0x96>
8000436: f1c7 0c20 rsb ip, r7, #32
800043a: 40bb lsls r3, r7
800043c: fa22 fe0c lsr.w lr, r2, ip
8000440: ea4e 0e03 orr.w lr, lr, r3
8000444: fa01 f407 lsl.w r4, r1, r7
8000448: fa20 f50c lsr.w r5, r0, ip
800044c: fa21 f30c lsr.w r3, r1, ip
8000450: ea4f 481e mov.w r8, lr, lsr #16
8000454: 4325 orrs r5, r4
8000456: fbb3 f9f8 udiv r9, r3, r8
800045a: 0c2c lsrs r4, r5, #16
800045c: fb08 3319 mls r3, r8, r9, r3
8000460: fa1f fa8e uxth.w sl, lr
8000464: ea44 4303 orr.w r3, r4, r3, lsl #16
8000468: fb09 f40a mul.w r4, r9, sl
800046c: 429c cmp r4, r3
800046e: fa02 f207 lsl.w r2, r2, r7
8000472: fa00 f107 lsl.w r1, r0, r7
8000476: d90b bls.n 8000490 <__udivmoddi4+0x1b0>
8000478: eb1e 0303 adds.w r3, lr, r3
800047c: f109 30ff add.w r0, r9, #4294967295
8000480: f080 8087 bcs.w 8000592 <__udivmoddi4+0x2b2>
8000484: 429c cmp r4, r3
8000486: f240 8084 bls.w 8000592 <__udivmoddi4+0x2b2>
800048a: f1a9 0902 sub.w r9, r9, #2
800048e: 4473 add r3, lr
8000490: 1b1b subs r3, r3, r4
8000492: b2ad uxth r5, r5
8000494: fbb3 f0f8 udiv r0, r3, r8
8000498: fb08 3310 mls r3, r8, r0, r3
800049c: ea45 4403 orr.w r4, r5, r3, lsl #16
80004a0: fb00 fa0a mul.w sl, r0, sl
80004a4: 45a2 cmp sl, r4
80004a6: d908 bls.n 80004ba <__udivmoddi4+0x1da>
80004a8: eb1e 0404 adds.w r4, lr, r4
80004ac: f100 33ff add.w r3, r0, #4294967295
80004b0: d26b bcs.n 800058a <__udivmoddi4+0x2aa>
80004b2: 45a2 cmp sl, r4
80004b4: d969 bls.n 800058a <__udivmoddi4+0x2aa>
80004b6: 3802 subs r0, #2
80004b8: 4474 add r4, lr
80004ba: ea40 4009 orr.w r0, r0, r9, lsl #16
80004be: fba0 8902 umull r8, r9, r0, r2
80004c2: eba4 040a sub.w r4, r4, sl
80004c6: 454c cmp r4, r9
80004c8: 46c2 mov sl, r8
80004ca: 464b mov r3, r9
80004cc: d354 bcc.n 8000578 <__udivmoddi4+0x298>
80004ce: d051 beq.n 8000574 <__udivmoddi4+0x294>
80004d0: 2e00 cmp r6, #0
80004d2: d069 beq.n 80005a8 <__udivmoddi4+0x2c8>
80004d4: ebb1 050a subs.w r5, r1, sl
80004d8: eb64 0403 sbc.w r4, r4, r3
80004dc: fa04 fc0c lsl.w ip, r4, ip
80004e0: 40fd lsrs r5, r7
80004e2: 40fc lsrs r4, r7
80004e4: ea4c 0505 orr.w r5, ip, r5
80004e8: e9c6 5400 strd r5, r4, [r6]
80004ec: 2700 movs r7, #0
80004ee: e747 b.n 8000380 <__udivmoddi4+0xa0>
80004f0: f1c2 0320 rsb r3, r2, #32
80004f4: fa20 f703 lsr.w r7, r0, r3
80004f8: 4095 lsls r5, r2
80004fa: fa01 f002 lsl.w r0, r1, r2
80004fe: fa21 f303 lsr.w r3, r1, r3
8000502: ea4f 4e15 mov.w lr, r5, lsr #16
8000506: 4338 orrs r0, r7
8000508: 0c01 lsrs r1, r0, #16
800050a: fbb3 f7fe udiv r7, r3, lr
800050e: fa1f f885 uxth.w r8, r5
8000512: fb0e 3317 mls r3, lr, r7, r3
8000516: ea41 4103 orr.w r1, r1, r3, lsl #16
800051a: fb07 f308 mul.w r3, r7, r8
800051e: 428b cmp r3, r1
8000520: fa04 f402 lsl.w r4, r4, r2
8000524: d907 bls.n 8000536 <__udivmoddi4+0x256>
8000526: 1869 adds r1, r5, r1
8000528: f107 3cff add.w ip, r7, #4294967295
800052c: d22f bcs.n 800058e <__udivmoddi4+0x2ae>
800052e: 428b cmp r3, r1
8000530: d92d bls.n 800058e <__udivmoddi4+0x2ae>
8000532: 3f02 subs r7, #2
8000534: 4429 add r1, r5
8000536: 1acb subs r3, r1, r3
8000538: b281 uxth r1, r0
800053a: fbb3 f0fe udiv r0, r3, lr
800053e: fb0e 3310 mls r3, lr, r0, r3
8000542: ea41 4103 orr.w r1, r1, r3, lsl #16
8000546: fb00 f308 mul.w r3, r0, r8
800054a: 428b cmp r3, r1
800054c: d907 bls.n 800055e <__udivmoddi4+0x27e>
800054e: 1869 adds r1, r5, r1
8000550: f100 3cff add.w ip, r0, #4294967295
8000554: d217 bcs.n 8000586 <__udivmoddi4+0x2a6>
8000556: 428b cmp r3, r1
8000558: d915 bls.n 8000586 <__udivmoddi4+0x2a6>
800055a: 3802 subs r0, #2
800055c: 4429 add r1, r5
800055e: 1ac9 subs r1, r1, r3
8000560: ea40 4707 orr.w r7, r0, r7, lsl #16
8000564: e73b b.n 80003de <__udivmoddi4+0xfe>
8000566: 4637 mov r7, r6
8000568: 4630 mov r0, r6
800056a: e709 b.n 8000380 <__udivmoddi4+0xa0>
800056c: 4607 mov r7, r0
800056e: e6e7 b.n 8000340 <__udivmoddi4+0x60>
8000570: 4618 mov r0, r3
8000572: e6fb b.n 800036c <__udivmoddi4+0x8c>
8000574: 4541 cmp r1, r8
8000576: d2ab bcs.n 80004d0 <__udivmoddi4+0x1f0>
8000578: ebb8 0a02 subs.w sl, r8, r2
800057c: eb69 020e sbc.w r2, r9, lr
8000580: 3801 subs r0, #1
8000582: 4613 mov r3, r2
8000584: e7a4 b.n 80004d0 <__udivmoddi4+0x1f0>
8000586: 4660 mov r0, ip
8000588: e7e9 b.n 800055e <__udivmoddi4+0x27e>
800058a: 4618 mov r0, r3
800058c: e795 b.n 80004ba <__udivmoddi4+0x1da>
800058e: 4667 mov r7, ip
8000590: e7d1 b.n 8000536 <__udivmoddi4+0x256>
8000592: 4681 mov r9, r0
8000594: e77c b.n 8000490 <__udivmoddi4+0x1b0>
8000596: 3802 subs r0, #2
8000598: 442c add r4, r5
800059a: e747 b.n 800042c <__udivmoddi4+0x14c>
800059c: f1ac 0c02 sub.w ip, ip, #2
80005a0: 442b add r3, r5
80005a2: e72f b.n 8000404 <__udivmoddi4+0x124>
80005a4: 4638 mov r0, r7
80005a6: e708 b.n 80003ba <__udivmoddi4+0xda>
80005a8: 4637 mov r7, r6
80005aa: e6e9 b.n 8000380 <__udivmoddi4+0xa0>
080005ac <__aeabi_idiv0>:
80005ac: 4770 bx lr
80005ae: bf00 nop
080005b0 <vApplicationIdleHook>:
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
void vApplicationMallocFailedHook(void);
/* USER CODE BEGIN 2 */
__weak void vApplicationIdleHook( void )
{
80005b0: b480 push {r7}
80005b2: af00 add r7, sp, #0
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
80005b4: bf00 nop
80005b6: 46bd mov sp, r7
80005b8: f85d 7b04 ldr.w r7, [sp], #4
80005bc: 4770 bx lr
080005be <vApplicationStackOverflowHook>:
/* USER CODE END 2 */
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
80005be: b480 push {r7}
80005c0: b083 sub sp, #12
80005c2: af00 add r7, sp, #0
80005c4: 6078 str r0, [r7, #4]
80005c6: 6039 str r1, [r7, #0]
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
80005c8: bf00 nop
80005ca: 370c adds r7, #12
80005cc: 46bd mov sp, r7
80005ce: f85d 7b04 ldr.w r7, [sp], #4
80005d2: 4770 bx lr
080005d4 <vApplicationMallocFailedHook>:
/* USER CODE END 4 */
/* USER CODE BEGIN 5 */
__weak void vApplicationMallocFailedHook(void)
{
80005d4: b480 push {r7}
80005d6: af00 add r7, sp, #0
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
}
80005d8: bf00 nop
80005da: 46bd mov sp, r7
80005dc: f85d 7b04 ldr.w r7, [sp], #4
80005e0: 4770 bx lr
...
080005e4 <vApplicationGetIdleTaskMemory>:
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
80005e4: b480 push {r7}
80005e6: b085 sub sp, #20
80005e8: af00 add r7, sp, #0
80005ea: 60f8 str r0, [r7, #12]
80005ec: 60b9 str r1, [r7, #8]
80005ee: 607a str r2, [r7, #4]
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
80005f0: 68fb ldr r3, [r7, #12]
80005f2: 4a07 ldr r2, [pc, #28] ; (8000610 <vApplicationGetIdleTaskMemory+0x2c>)
80005f4: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &xIdleStack[0];
80005f6: 68bb ldr r3, [r7, #8]
80005f8: 4a06 ldr r2, [pc, #24] ; (8000614 <vApplicationGetIdleTaskMemory+0x30>)
80005fa: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
80005fc: 687b ldr r3, [r7, #4]
80005fe: 2280 movs r2, #128 ; 0x80
8000600: 601a str r2, [r3, #0]
/* place for user code */
}
8000602: bf00 nop
8000604: 3714 adds r7, #20
8000606: 46bd mov sp, r7
8000608: f85d 7b04 ldr.w r7, [sp], #4
800060c: 4770 bx lr
800060e: bf00 nop
8000610: 20000104 .word 0x20000104
8000614: 2000015c .word 0x2000015c
08000618 <ft5336_Init>:
* from MCU to FT5336 : ie I2C channel initialization (if required).
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Init(uint16_t DeviceAddr)
{
8000618: b580 push {r7, lr}
800061a: b082 sub sp, #8
800061c: af00 add r7, sp, #0
800061e: 4603 mov r3, r0
8000620: 80fb strh r3, [r7, #6]
/* Wait at least 200ms after power up before accessing registers
* Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */
TS_IO_Delay(200);
8000622: 20c8 movs r0, #200 ; 0xc8
8000624: f002 f99a bl 800295c <TS_IO_Delay>
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000628: f000 fa7a bl 8000b20 <ft5336_I2C_InitializeIfRequired>
}
800062c: bf00 nop
800062e: 3708 adds r7, #8
8000630: 46bd mov sp, r7
8000632: bd80 pop {r7, pc}
08000634 <ft5336_Reset>:
* @note : Not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Reset(uint16_t DeviceAddr)
{
8000634: b480 push {r7}
8000636: b083 sub sp, #12
8000638: af00 add r7, sp, #0
800063a: 4603 mov r3, r0
800063c: 80fb strh r3, [r7, #6]
/* Do nothing */
/* No software reset sequence available in FT5336 IC */
}
800063e: bf00 nop
8000640: 370c adds r7, #12
8000642: 46bd mov sp, r7
8000644: f85d 7b04 ldr.w r7, [sp], #4
8000648: 4770 bx lr
0800064a <ft5336_ReadID>:
* able to read the FT5336 device ID, and verify this is a FT5336.
* @param DeviceAddr: I2C FT5336 Slave address.
* @retval The Device ID (two bytes).
*/
uint16_t ft5336_ReadID(uint16_t DeviceAddr)
{
800064a: b580 push {r7, lr}
800064c: b084 sub sp, #16
800064e: af00 add r7, sp, #0
8000650: 4603 mov r3, r0
8000652: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadId = 0;
8000654: 2300 movs r3, #0
8000656: 737b strb r3, [r7, #13]
uint8_t nbReadAttempts = 0;
8000658: 2300 movs r3, #0
800065a: 73fb strb r3, [r7, #15]
uint8_t bFoundDevice = 0; /* Device not found by default */
800065c: 2300 movs r3, #0
800065e: 73bb strb r3, [r7, #14]
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000660: f000 fa5e bl 8000b20 <ft5336_I2C_InitializeIfRequired>
/* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000664: 2300 movs r3, #0
8000666: 73fb strb r3, [r7, #15]
8000668: e010 b.n 800068c <ft5336_ReadID+0x42>
{
/* Read register FT5336_CHIP_ID_REG as DeviceID detection */
ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG);
800066a: 88fb ldrh r3, [r7, #6]
800066c: b2db uxtb r3, r3
800066e: 21a8 movs r1, #168 ; 0xa8
8000670: 4618 mov r0, r3
8000672: f002 f955 bl 8002920 <TS_IO_Read>
8000676: 4603 mov r3, r0
8000678: 737b strb r3, [r7, #13]
/* Found the searched device ID ? */
if(ucReadId == FT5336_ID_VALUE)
800067a: 7b7b ldrb r3, [r7, #13]
800067c: b2db uxtb r3, r3
800067e: 2b51 cmp r3, #81 ; 0x51
8000680: d101 bne.n 8000686 <ft5336_ReadID+0x3c>
{
/* Set device as found */
bFoundDevice = 1;
8000682: 2301 movs r3, #1
8000684: 73bb strb r3, [r7, #14]
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000686: 7bfb ldrb r3, [r7, #15]
8000688: 3301 adds r3, #1
800068a: 73fb strb r3, [r7, #15]
800068c: 7bfb ldrb r3, [r7, #15]
800068e: 2b02 cmp r3, #2
8000690: d802 bhi.n 8000698 <ft5336_ReadID+0x4e>
8000692: 7bbb ldrb r3, [r7, #14]
8000694: 2b00 cmp r3, #0
8000696: d0e8 beq.n 800066a <ft5336_ReadID+0x20>
}
}
/* Return the device ID value */
return (ucReadId);
8000698: 7b7b ldrb r3, [r7, #13]
800069a: b2db uxtb r3, r3
800069c: b29b uxth r3, r3
}
800069e: 4618 mov r0, r3
80006a0: 3710 adds r7, #16
80006a2: 46bd mov sp, r7
80006a4: bd80 pop {r7, pc}
080006a6 <ft5336_TS_Start>:
* @brief Configures the touch Screen IC device to start detecting touches
* @param DeviceAddr: Device address on communication Bus (I2C slave address).
* @retval None.
*/
void ft5336_TS_Start(uint16_t DeviceAddr)
{
80006a6: b580 push {r7, lr}
80006a8: b082 sub sp, #8
80006aa: af00 add r7, sp, #0
80006ac: 4603 mov r3, r0
80006ae: 80fb strh r3, [r7, #6]
/* Minimum static configuration of FT5336 */
FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr));
80006b0: 88fb ldrh r3, [r7, #6]
80006b2: 4618 mov r0, r3
80006b4: f000 fa44 bl 8000b40 <ft5336_TS_Configure>
/* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */
/* Note TS_INT is active low */
ft5336_TS_DisableIT(DeviceAddr);
80006b8: 88fb ldrh r3, [r7, #6]
80006ba: 4618 mov r0, r3
80006bc: f000 f932 bl 8000924 <ft5336_TS_DisableIT>
}
80006c0: bf00 nop
80006c2: 3708 adds r7, #8
80006c4: 46bd mov sp, r7
80006c6: bd80 pop {r7, pc}
080006c8 <ft5336_TS_DetectTouch>:
* variables).
* @param DeviceAddr: Device address on communication Bus.
* @retval : Number of active touches detected (can be 0, 1 or 2).
*/
uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr)
{
80006c8: b580 push {r7, lr}
80006ca: b084 sub sp, #16
80006cc: af00 add r7, sp, #0
80006ce: 4603 mov r3, r0
80006d0: 80fb strh r3, [r7, #6]
volatile uint8_t nbTouch = 0;
80006d2: 2300 movs r3, #0
80006d4: 73fb strb r3, [r7, #15]
/* Read register FT5336_TD_STAT_REG to check number of touches detection */
nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG);
80006d6: 88fb ldrh r3, [r7, #6]
80006d8: b2db uxtb r3, r3
80006da: 2102 movs r1, #2
80006dc: 4618 mov r0, r3
80006de: f002 f91f bl 8002920 <TS_IO_Read>
80006e2: 4603 mov r3, r0
80006e4: 73fb strb r3, [r7, #15]
nbTouch &= FT5336_TD_STAT_MASK;
80006e6: 7bfb ldrb r3, [r7, #15]
80006e8: b2db uxtb r3, r3
80006ea: f003 030f and.w r3, r3, #15
80006ee: b2db uxtb r3, r3
80006f0: 73fb strb r3, [r7, #15]
if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH)
80006f2: 7bfb ldrb r3, [r7, #15]
80006f4: b2db uxtb r3, r3
80006f6: 2b05 cmp r3, #5
80006f8: d901 bls.n 80006fe <ft5336_TS_DetectTouch+0x36>
{
/* If invalid number of touch detected, set it to zero */
nbTouch = 0;
80006fa: 2300 movs r3, #0
80006fc: 73fb strb r3, [r7, #15]
}
/* Update ft5336 driver internal global : current number of active touches */
ft5336_handle.currActiveTouchNb = nbTouch;
80006fe: 7bfb ldrb r3, [r7, #15]
8000700: b2da uxtb r2, r3
8000702: 4b05 ldr r3, [pc, #20] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
8000704: 705a strb r2, [r3, #1]
/* Reset current active touch index on which to work on */
ft5336_handle.currActiveTouchIdx = 0;
8000706: 4b04 ldr r3, [pc, #16] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
8000708: 2200 movs r2, #0
800070a: 709a strb r2, [r3, #2]
return(nbTouch);
800070c: 7bfb ldrb r3, [r7, #15]
800070e: b2db uxtb r3, r3
}
8000710: 4618 mov r0, r3
8000712: 3710 adds r7, #16
8000714: 46bd mov sp, r7
8000716: bd80 pop {r7, pc}
8000718: 2000035c .word 0x2000035c
0800071c <ft5336_TS_GetXY>:
* @param X: Pointer to X position value
* @param Y: Pointer to Y position value
* @retval None.
*/
void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
{
800071c: b580 push {r7, lr}
800071e: b086 sub sp, #24
8000720: af00 add r7, sp, #0
8000722: 4603 mov r3, r0
8000724: 60b9 str r1, [r7, #8]
8000726: 607a str r2, [r7, #4]
8000728: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
800072a: 2300 movs r3, #0
800072c: 74fb strb r3, [r7, #19]
static uint16_t coord;
uint8_t regAddressXLow = 0;
800072e: 2300 movs r3, #0
8000730: 75fb strb r3, [r7, #23]
uint8_t regAddressXHigh = 0;
8000732: 2300 movs r3, #0
8000734: 75bb strb r3, [r7, #22]
uint8_t regAddressYLow = 0;
8000736: 2300 movs r3, #0
8000738: 757b strb r3, [r7, #21]
uint8_t regAddressYHigh = 0;
800073a: 2300 movs r3, #0
800073c: 753b strb r3, [r7, #20]
if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb)
800073e: 4b6d ldr r3, [pc, #436] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
8000740: 789a ldrb r2, [r3, #2]
8000742: 4b6c ldr r3, [pc, #432] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
8000744: 785b ldrb r3, [r3, #1]
8000746: 429a cmp r2, r3
8000748: f080 80cf bcs.w 80008ea <ft5336_TS_GetXY+0x1ce>
{
switch(ft5336_handle.currActiveTouchIdx)
800074c: 4b69 ldr r3, [pc, #420] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
800074e: 789b ldrb r3, [r3, #2]
8000750: 2b09 cmp r3, #9
8000752: d871 bhi.n 8000838 <ft5336_TS_GetXY+0x11c>
8000754: a201 add r2, pc, #4 ; (adr r2, 800075c <ft5336_TS_GetXY+0x40>)
8000756: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800075a: bf00 nop
800075c: 08000785 .word 0x08000785
8000760: 08000797 .word 0x08000797
8000764: 080007a9 .word 0x080007a9
8000768: 080007bb .word 0x080007bb
800076c: 080007cd .word 0x080007cd
8000770: 080007df .word 0x080007df
8000774: 080007f1 .word 0x080007f1
8000778: 08000803 .word 0x08000803
800077c: 08000815 .word 0x08000815
8000780: 08000827 .word 0x08000827
{
case 0 :
regAddressXLow = FT5336_P1_XL_REG;
8000784: 2304 movs r3, #4
8000786: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P1_XH_REG;
8000788: 2303 movs r3, #3
800078a: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P1_YL_REG;
800078c: 2306 movs r3, #6
800078e: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P1_YH_REG;
8000790: 2305 movs r3, #5
8000792: 753b strb r3, [r7, #20]
break;
8000794: e051 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 1 :
regAddressXLow = FT5336_P2_XL_REG;
8000796: 230a movs r3, #10
8000798: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P2_XH_REG;
800079a: 2309 movs r3, #9
800079c: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P2_YL_REG;
800079e: 230c movs r3, #12
80007a0: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P2_YH_REG;
80007a2: 230b movs r3, #11
80007a4: 753b strb r3, [r7, #20]
break;
80007a6: e048 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 2 :
regAddressXLow = FT5336_P3_XL_REG;
80007a8: 2310 movs r3, #16
80007aa: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P3_XH_REG;
80007ac: 230f movs r3, #15
80007ae: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P3_YL_REG;
80007b0: 2312 movs r3, #18
80007b2: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P3_YH_REG;
80007b4: 2311 movs r3, #17
80007b6: 753b strb r3, [r7, #20]
break;
80007b8: e03f b.n 800083a <ft5336_TS_GetXY+0x11e>
case 3 :
regAddressXLow = FT5336_P4_XL_REG;
80007ba: 2316 movs r3, #22
80007bc: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P4_XH_REG;
80007be: 2315 movs r3, #21
80007c0: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P4_YL_REG;
80007c2: 2318 movs r3, #24
80007c4: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P4_YH_REG;
80007c6: 2317 movs r3, #23
80007c8: 753b strb r3, [r7, #20]
break;
80007ca: e036 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 4 :
regAddressXLow = FT5336_P5_XL_REG;
80007cc: 231c movs r3, #28
80007ce: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P5_XH_REG;
80007d0: 231b movs r3, #27
80007d2: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P5_YL_REG;
80007d4: 231e movs r3, #30
80007d6: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P5_YH_REG;
80007d8: 231d movs r3, #29
80007da: 753b strb r3, [r7, #20]
break;
80007dc: e02d b.n 800083a <ft5336_TS_GetXY+0x11e>
case 5 :
regAddressXLow = FT5336_P6_XL_REG;
80007de: 2322 movs r3, #34 ; 0x22
80007e0: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P6_XH_REG;
80007e2: 2321 movs r3, #33 ; 0x21
80007e4: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P6_YL_REG;
80007e6: 2324 movs r3, #36 ; 0x24
80007e8: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P6_YH_REG;
80007ea: 2323 movs r3, #35 ; 0x23
80007ec: 753b strb r3, [r7, #20]
break;
80007ee: e024 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 6 :
regAddressXLow = FT5336_P7_XL_REG;
80007f0: 2328 movs r3, #40 ; 0x28
80007f2: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P7_XH_REG;
80007f4: 2327 movs r3, #39 ; 0x27
80007f6: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P7_YL_REG;
80007f8: 232a movs r3, #42 ; 0x2a
80007fa: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P7_YH_REG;
80007fc: 2329 movs r3, #41 ; 0x29
80007fe: 753b strb r3, [r7, #20]
break;
8000800: e01b b.n 800083a <ft5336_TS_GetXY+0x11e>
case 7 :
regAddressXLow = FT5336_P8_XL_REG;
8000802: 232e movs r3, #46 ; 0x2e
8000804: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P8_XH_REG;
8000806: 232d movs r3, #45 ; 0x2d
8000808: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P8_YL_REG;
800080a: 2330 movs r3, #48 ; 0x30
800080c: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P8_YH_REG;
800080e: 232f movs r3, #47 ; 0x2f
8000810: 753b strb r3, [r7, #20]
break;
8000812: e012 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 8 :
regAddressXLow = FT5336_P9_XL_REG;
8000814: 2334 movs r3, #52 ; 0x34
8000816: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P9_XH_REG;
8000818: 2333 movs r3, #51 ; 0x33
800081a: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P9_YL_REG;
800081c: 2336 movs r3, #54 ; 0x36
800081e: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P9_YH_REG;
8000820: 2335 movs r3, #53 ; 0x35
8000822: 753b strb r3, [r7, #20]
break;
8000824: e009 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 9 :
regAddressXLow = FT5336_P10_XL_REG;
8000826: 233a movs r3, #58 ; 0x3a
8000828: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P10_XH_REG;
800082a: 2339 movs r3, #57 ; 0x39
800082c: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P10_YL_REG;
800082e: 233c movs r3, #60 ; 0x3c
8000830: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P10_YH_REG;
8000832: 233b movs r3, #59 ; 0x3b
8000834: 753b strb r3, [r7, #20]
break;
8000836: e000 b.n 800083a <ft5336_TS_GetXY+0x11e>
default :
break;
8000838: bf00 nop
} /* end switch(ft5336_handle.currActiveTouchIdx) */
/* Read low part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow);
800083a: 89fb ldrh r3, [r7, #14]
800083c: b2db uxtb r3, r3
800083e: 7dfa ldrb r2, [r7, #23]
8000840: 4611 mov r1, r2
8000842: 4618 mov r0, r3
8000844: f002 f86c bl 8002920 <TS_IO_Read>
8000848: 4603 mov r3, r0
800084a: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
800084c: 7cfb ldrb r3, [r7, #19]
800084e: b2db uxtb r3, r3
8000850: b29a uxth r2, r3
8000852: 4b29 ldr r3, [pc, #164] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000854: 801a strh r2, [r3, #0]
/* Read high part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000856: 89fb ldrh r3, [r7, #14]
8000858: b2db uxtb r3, r3
800085a: 7dba ldrb r2, [r7, #22]
800085c: 4611 mov r1, r2
800085e: 4618 mov r0, r3
8000860: f002 f85e bl 8002920 <TS_IO_Read>
8000864: 4603 mov r3, r0
8000866: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
8000868: 7cfb ldrb r3, [r7, #19]
800086a: b2db uxtb r3, r3
800086c: 021b lsls r3, r3, #8
800086e: f403 6370 and.w r3, r3, #3840 ; 0xf00
8000872: b21a sxth r2, r3
8000874: 4b20 ldr r3, [pc, #128] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000876: 881b ldrh r3, [r3, #0]
8000878: b21b sxth r3, r3
800087a: 4313 orrs r3, r2
800087c: b21b sxth r3, r3
800087e: b29a uxth r2, r3
8000880: 4b1d ldr r3, [pc, #116] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000882: 801a strh r2, [r3, #0]
/* Send back ready X position to caller */
*X = coord;
8000884: 4b1c ldr r3, [pc, #112] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000886: 881a ldrh r2, [r3, #0]
8000888: 68bb ldr r3, [r7, #8]
800088a: 801a strh r2, [r3, #0]
/* Read low part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow);
800088c: 89fb ldrh r3, [r7, #14]
800088e: b2db uxtb r3, r3
8000890: 7d7a ldrb r2, [r7, #21]
8000892: 4611 mov r1, r2
8000894: 4618 mov r0, r3
8000896: f002 f843 bl 8002920 <TS_IO_Read>
800089a: 4603 mov r3, r0
800089c: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
800089e: 7cfb ldrb r3, [r7, #19]
80008a0: b2db uxtb r3, r3
80008a2: b29a uxth r2, r3
80008a4: 4b14 ldr r3, [pc, #80] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008a6: 801a strh r2, [r3, #0]
/* Read high part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh);
80008a8: 89fb ldrh r3, [r7, #14]
80008aa: b2db uxtb r3, r3
80008ac: 7d3a ldrb r2, [r7, #20]
80008ae: 4611 mov r1, r2
80008b0: 4618 mov r0, r3
80008b2: f002 f835 bl 8002920 <TS_IO_Read>
80008b6: 4603 mov r3, r0
80008b8: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
80008ba: 7cfb ldrb r3, [r7, #19]
80008bc: b2db uxtb r3, r3
80008be: 021b lsls r3, r3, #8
80008c0: f403 6370 and.w r3, r3, #3840 ; 0xf00
80008c4: b21a sxth r2, r3
80008c6: 4b0c ldr r3, [pc, #48] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008c8: 881b ldrh r3, [r3, #0]
80008ca: b21b sxth r3, r3
80008cc: 4313 orrs r3, r2
80008ce: b21b sxth r3, r3
80008d0: b29a uxth r2, r3
80008d2: 4b09 ldr r3, [pc, #36] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008d4: 801a strh r2, [r3, #0]
/* Send back ready Y position to caller */
*Y = coord;
80008d6: 4b08 ldr r3, [pc, #32] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008d8: 881a ldrh r2, [r3, #0]
80008da: 687b ldr r3, [r7, #4]
80008dc: 801a strh r2, [r3, #0]
ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */
80008de: 4b05 ldr r3, [pc, #20] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
80008e0: 789b ldrb r3, [r3, #2]
80008e2: 3301 adds r3, #1
80008e4: b2da uxtb r2, r3
80008e6: 4b03 ldr r3, [pc, #12] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
80008e8: 709a strb r2, [r3, #2]
} /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */
}
80008ea: bf00 nop
80008ec: 3718 adds r7, #24
80008ee: 46bd mov sp, r7
80008f0: bd80 pop {r7, pc}
80008f2: bf00 nop
80008f4: 2000035c .word 0x2000035c
80008f8: 20000360 .word 0x20000360
080008fc <ft5336_TS_EnableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_EnableIT(uint16_t DeviceAddr)
{
80008fc: b580 push {r7, lr}
80008fe: b084 sub sp, #16
8000900: af00 add r7, sp, #0
8000902: 4603 mov r3, r0
8000904: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
8000906: 2300 movs r3, #0
8000908: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
800090a: 2301 movs r3, #1
800090c: 73fb strb r3, [r7, #15]
/* Set interrupt trigger mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
800090e: 88fb ldrh r3, [r7, #6]
8000910: b2db uxtb r3, r3
8000912: 7bfa ldrb r2, [r7, #15]
8000914: 21a4 movs r1, #164 ; 0xa4
8000916: 4618 mov r0, r3
8000918: f001 ffe8 bl 80028ec <TS_IO_Write>
}
800091c: bf00 nop
800091e: 3710 adds r7, #16
8000920: 46bd mov sp, r7
8000922: bd80 pop {r7, pc}
08000924 <ft5336_TS_DisableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_DisableIT(uint16_t DeviceAddr)
{
8000924: b580 push {r7, lr}
8000926: b084 sub sp, #16
8000928: af00 add r7, sp, #0
800092a: 4603 mov r3, r0
800092c: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
800092e: 2300 movs r3, #0
8000930: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
8000932: 2300 movs r3, #0
8000934: 73fb strb r3, [r7, #15]
/* Set interrupt polling mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
8000936: 88fb ldrh r3, [r7, #6]
8000938: b2db uxtb r3, r3
800093a: 7bfa ldrb r2, [r7, #15]
800093c: 21a4 movs r1, #164 ; 0xa4
800093e: 4618 mov r0, r3
8000940: f001 ffd4 bl 80028ec <TS_IO_Write>
}
8000944: bf00 nop
8000946: 3710 adds r7, #16
8000948: 46bd mov sp, r7
800094a: bd80 pop {r7, pc}
0800094c <ft5336_TS_ITStatus>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval TS interrupts status : always return 0 here
*/
uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr)
{
800094c: b480 push {r7}
800094e: b083 sub sp, #12
8000950: af00 add r7, sp, #0
8000952: 4603 mov r3, r0
8000954: 80fb strh r3, [r7, #6]
/* Always return 0 as feature not applicable to FT5336 */
return 0;
8000956: 2300 movs r3, #0
}
8000958: 4618 mov r0, r3
800095a: 370c adds r7, #12
800095c: 46bd mov sp, r7
800095e: f85d 7b04 ldr.w r7, [sp], #4
8000962: 4770 bx lr
08000964 <ft5336_TS_ClearIT>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_TS_ClearIT(uint16_t DeviceAddr)
{
8000964: b480 push {r7}
8000966: b083 sub sp, #12
8000968: af00 add r7, sp, #0
800096a: 4603 mov r3, r0
800096c: 80fb strh r3, [r7, #6]
/* Nothing to be done here for FT5336 */
}
800096e: bf00 nop
8000970: 370c adds r7, #12
8000972: 46bd mov sp, r7
8000974: f85d 7b04 ldr.w r7, [sp], #4
8000978: 4770 bx lr
0800097a <ft5336_TS_GetGestureID>:
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @param pGestureId : Pointer to get last touch gesture Identification.
* @retval None.
*/
void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
{
800097a: b580 push {r7, lr}
800097c: b084 sub sp, #16
800097e: af00 add r7, sp, #0
8000980: 4603 mov r3, r0
8000982: 6039 str r1, [r7, #0]
8000984: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadData = 0;
8000986: 2300 movs r3, #0
8000988: 73fb strb r3, [r7, #15]
ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG);
800098a: 88fb ldrh r3, [r7, #6]
800098c: b2db uxtb r3, r3
800098e: 2101 movs r1, #1
8000990: 4618 mov r0, r3
8000992: f001 ffc5 bl 8002920 <TS_IO_Read>
8000996: 4603 mov r3, r0
8000998: 73fb strb r3, [r7, #15]
* pGestureId = ucReadData;
800099a: 7bfb ldrb r3, [r7, #15]
800099c: b2db uxtb r3, r3
800099e: 461a mov r2, r3
80009a0: 683b ldr r3, [r7, #0]
80009a2: 601a str r2, [r3, #0]
}
80009a4: bf00 nop
80009a6: 3710 adds r7, #16
80009a8: 46bd mov sp, r7
80009aa: bd80 pop {r7, pc}
080009ac <ft5336_TS_GetTouchInfo>:
void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr,
uint32_t touchIdx,
uint32_t * pWeight,
uint32_t * pArea,
uint32_t * pEvent)
{
80009ac: b580 push {r7, lr}
80009ae: b086 sub sp, #24
80009b0: af00 add r7, sp, #0
80009b2: 60b9 str r1, [r7, #8]
80009b4: 607a str r2, [r7, #4]
80009b6: 603b str r3, [r7, #0]
80009b8: 4603 mov r3, r0
80009ba: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
80009bc: 2300 movs r3, #0
80009be: 753b strb r3, [r7, #20]
uint8_t regAddressXHigh = 0;
80009c0: 2300 movs r3, #0
80009c2: 75fb strb r3, [r7, #23]
uint8_t regAddressPWeight = 0;
80009c4: 2300 movs r3, #0
80009c6: 75bb strb r3, [r7, #22]
uint8_t regAddressPMisc = 0;
80009c8: 2300 movs r3, #0
80009ca: 757b strb r3, [r7, #21]
if(touchIdx < ft5336_handle.currActiveTouchNb)
80009cc: 4b4d ldr r3, [pc, #308] ; (8000b04 <ft5336_TS_GetTouchInfo+0x158>)
80009ce: 785b ldrb r3, [r3, #1]
80009d0: 461a mov r2, r3
80009d2: 68bb ldr r3, [r7, #8]
80009d4: 4293 cmp r3, r2
80009d6: f080 8090 bcs.w 8000afa <ft5336_TS_GetTouchInfo+0x14e>
{
switch(touchIdx)
80009da: 68bb ldr r3, [r7, #8]
80009dc: 2b09 cmp r3, #9
80009de: d85d bhi.n 8000a9c <ft5336_TS_GetTouchInfo+0xf0>
80009e0: a201 add r2, pc, #4 ; (adr r2, 80009e8 <ft5336_TS_GetTouchInfo+0x3c>)
80009e2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80009e6: bf00 nop
80009e8: 08000a11 .word 0x08000a11
80009ec: 08000a1f .word 0x08000a1f
80009f0: 08000a2d .word 0x08000a2d
80009f4: 08000a3b .word 0x08000a3b
80009f8: 08000a49 .word 0x08000a49
80009fc: 08000a57 .word 0x08000a57
8000a00: 08000a65 .word 0x08000a65
8000a04: 08000a73 .word 0x08000a73
8000a08: 08000a81 .word 0x08000a81
8000a0c: 08000a8f .word 0x08000a8f
{
case 0 :
regAddressXHigh = FT5336_P1_XH_REG;
8000a10: 2303 movs r3, #3
8000a12: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P1_WEIGHT_REG;
8000a14: 2307 movs r3, #7
8000a16: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P1_MISC_REG;
8000a18: 2308 movs r3, #8
8000a1a: 757b strb r3, [r7, #21]
break;
8000a1c: e03f b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 1 :
regAddressXHigh = FT5336_P2_XH_REG;
8000a1e: 2309 movs r3, #9
8000a20: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P2_WEIGHT_REG;
8000a22: 230d movs r3, #13
8000a24: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P2_MISC_REG;
8000a26: 230e movs r3, #14
8000a28: 757b strb r3, [r7, #21]
break;
8000a2a: e038 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 2 :
regAddressXHigh = FT5336_P3_XH_REG;
8000a2c: 230f movs r3, #15
8000a2e: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P3_WEIGHT_REG;
8000a30: 2313 movs r3, #19
8000a32: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P3_MISC_REG;
8000a34: 2314 movs r3, #20
8000a36: 757b strb r3, [r7, #21]
break;
8000a38: e031 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 3 :
regAddressXHigh = FT5336_P4_XH_REG;
8000a3a: 2315 movs r3, #21
8000a3c: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P4_WEIGHT_REG;
8000a3e: 2319 movs r3, #25
8000a40: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P4_MISC_REG;
8000a42: 231a movs r3, #26
8000a44: 757b strb r3, [r7, #21]
break;
8000a46: e02a b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 4 :
regAddressXHigh = FT5336_P5_XH_REG;
8000a48: 231b movs r3, #27
8000a4a: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P5_WEIGHT_REG;
8000a4c: 231f movs r3, #31
8000a4e: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P5_MISC_REG;
8000a50: 2320 movs r3, #32
8000a52: 757b strb r3, [r7, #21]
break;
8000a54: e023 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 5 :
regAddressXHigh = FT5336_P6_XH_REG;
8000a56: 2321 movs r3, #33 ; 0x21
8000a58: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P6_WEIGHT_REG;
8000a5a: 2325 movs r3, #37 ; 0x25
8000a5c: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P6_MISC_REG;
8000a5e: 2326 movs r3, #38 ; 0x26
8000a60: 757b strb r3, [r7, #21]
break;
8000a62: e01c b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 6 :
regAddressXHigh = FT5336_P7_XH_REG;
8000a64: 2327 movs r3, #39 ; 0x27
8000a66: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P7_WEIGHT_REG;
8000a68: 232b movs r3, #43 ; 0x2b
8000a6a: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P7_MISC_REG;
8000a6c: 232c movs r3, #44 ; 0x2c
8000a6e: 757b strb r3, [r7, #21]
break;
8000a70: e015 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 7 :
regAddressXHigh = FT5336_P8_XH_REG;
8000a72: 232d movs r3, #45 ; 0x2d
8000a74: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P8_WEIGHT_REG;
8000a76: 2331 movs r3, #49 ; 0x31
8000a78: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P8_MISC_REG;
8000a7a: 2332 movs r3, #50 ; 0x32
8000a7c: 757b strb r3, [r7, #21]
break;
8000a7e: e00e b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 8 :
regAddressXHigh = FT5336_P9_XH_REG;
8000a80: 2333 movs r3, #51 ; 0x33
8000a82: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P9_WEIGHT_REG;
8000a84: 2337 movs r3, #55 ; 0x37
8000a86: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P9_MISC_REG;
8000a88: 2338 movs r3, #56 ; 0x38
8000a8a: 757b strb r3, [r7, #21]
break;
8000a8c: e007 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 9 :
regAddressXHigh = FT5336_P10_XH_REG;
8000a8e: 2339 movs r3, #57 ; 0x39
8000a90: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P10_WEIGHT_REG;
8000a92: 233d movs r3, #61 ; 0x3d
8000a94: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P10_MISC_REG;
8000a96: 233e movs r3, #62 ; 0x3e
8000a98: 757b strb r3, [r7, #21]
break;
8000a9a: e000 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
default :
break;
8000a9c: bf00 nop
} /* end switch(touchIdx) */
/* Read Event Id of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000a9e: 89fb ldrh r3, [r7, #14]
8000aa0: b2db uxtb r3, r3
8000aa2: 7dfa ldrb r2, [r7, #23]
8000aa4: 4611 mov r1, r2
8000aa6: 4618 mov r0, r3
8000aa8: f001 ff3a bl 8002920 <TS_IO_Read>
8000aac: 4603 mov r3, r0
8000aae: 753b strb r3, [r7, #20]
* pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT;
8000ab0: 7d3b ldrb r3, [r7, #20]
8000ab2: b2db uxtb r3, r3
8000ab4: 119b asrs r3, r3, #6
8000ab6: f003 0203 and.w r2, r3, #3
8000aba: 6a3b ldr r3, [r7, #32]
8000abc: 601a str r2, [r3, #0]
/* Read weight of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight);
8000abe: 89fb ldrh r3, [r7, #14]
8000ac0: b2db uxtb r3, r3
8000ac2: 7dba ldrb r2, [r7, #22]
8000ac4: 4611 mov r1, r2
8000ac6: 4618 mov r0, r3
8000ac8: f001 ff2a bl 8002920 <TS_IO_Read>
8000acc: 4603 mov r3, r0
8000ace: 753b strb r3, [r7, #20]
* pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT;
8000ad0: 7d3b ldrb r3, [r7, #20]
8000ad2: b2db uxtb r3, r3
8000ad4: 461a mov r2, r3
8000ad6: 687b ldr r3, [r7, #4]
8000ad8: 601a str r2, [r3, #0]
/* Read area of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc);
8000ada: 89fb ldrh r3, [r7, #14]
8000adc: b2db uxtb r3, r3
8000ade: 7d7a ldrb r2, [r7, #21]
8000ae0: 4611 mov r1, r2
8000ae2: 4618 mov r0, r3
8000ae4: f001 ff1c bl 8002920 <TS_IO_Read>
8000ae8: 4603 mov r3, r0
8000aea: 753b strb r3, [r7, #20]
* pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT;
8000aec: 7d3b ldrb r3, [r7, #20]
8000aee: b2db uxtb r3, r3
8000af0: 111b asrs r3, r3, #4
8000af2: f003 0204 and.w r2, r3, #4
8000af6: 683b ldr r3, [r7, #0]
8000af8: 601a str r2, [r3, #0]
} /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */
}
8000afa: bf00 nop
8000afc: 3718 adds r7, #24
8000afe: 46bd mov sp, r7
8000b00: bd80 pop {r7, pc}
8000b02: bf00 nop
8000b04: 2000035c .word 0x2000035c
08000b08 <ft5336_Get_I2C_InitializedStatus>:
* @brief Return the status of I2C was initialized or not.
* @param None.
* @retval : I2C initialization status.
*/
static uint8_t ft5336_Get_I2C_InitializedStatus(void)
{
8000b08: b480 push {r7}
8000b0a: af00 add r7, sp, #0
return(ft5336_handle.i2cInitialized);
8000b0c: 4b03 ldr r3, [pc, #12] ; (8000b1c <ft5336_Get_I2C_InitializedStatus+0x14>)
8000b0e: 781b ldrb r3, [r3, #0]
}
8000b10: 4618 mov r0, r3
8000b12: 46bd mov sp, r7
8000b14: f85d 7b04 ldr.w r7, [sp], #4
8000b18: 4770 bx lr
8000b1a: bf00 nop
8000b1c: 2000035c .word 0x2000035c
08000b20 <ft5336_I2C_InitializeIfRequired>:
* @brief I2C initialize if needed.
* @param None.
* @retval : None.
*/
static void ft5336_I2C_InitializeIfRequired(void)
{
8000b20: b580 push {r7, lr}
8000b22: af00 add r7, sp, #0
if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED)
8000b24: f7ff fff0 bl 8000b08 <ft5336_Get_I2C_InitializedStatus>
8000b28: 4603 mov r3, r0
8000b2a: 2b00 cmp r3, #0
8000b2c: d104 bne.n 8000b38 <ft5336_I2C_InitializeIfRequired+0x18>
{
/* Initialize TS IO BUS layer (I2C) */
TS_IO_Init();
8000b2e: f001 fed3 bl 80028d8 <TS_IO_Init>
/* Set state to initialized */
ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED;
8000b32: 4b02 ldr r3, [pc, #8] ; (8000b3c <ft5336_I2C_InitializeIfRequired+0x1c>)
8000b34: 2201 movs r2, #1
8000b36: 701a strb r2, [r3, #0]
}
}
8000b38: bf00 nop
8000b3a: bd80 pop {r7, pc}
8000b3c: 2000035c .word 0x2000035c
08000b40 <ft5336_TS_Configure>:
* @brief Basic static configuration of TouchScreen
* @param DeviceAddr: FT5336 Device address for communication on I2C Bus.
* @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK.
*/
static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr)
{
8000b40: b480 push {r7}
8000b42: b085 sub sp, #20
8000b44: af00 add r7, sp, #0
8000b46: 4603 mov r3, r0
8000b48: 80fb strh r3, [r7, #6]
uint32_t status = FT5336_STATUS_OK;
8000b4a: 2300 movs r3, #0
8000b4c: 60fb str r3, [r7, #12]
/* Nothing special to be done for FT5336 */
return(status);
8000b4e: 68fb ldr r3, [r7, #12]
}
8000b50: 4618 mov r0, r3
8000b52: 3714 adds r7, #20
8000b54: 46bd mov sp, r7
8000b56: f85d 7b04 ldr.w r7, [sp], #4
8000b5a: 4770 bx lr
08000b5c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b5c: b5b0 push {r4, r5, r7, lr}
8000b5e: b0b0 sub sp, #192 ; 0xc0
8000b60: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
static TS_StateTypeDef TS_State;
ADC_ChannelConfTypeDef sConfig = {0};
8000b62: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000b66: 2200 movs r2, #0
8000b68: 601a str r2, [r3, #0]
8000b6a: 605a str r2, [r3, #4]
8000b6c: 609a str r2, [r3, #8]
8000b6e: 60da str r2, [r3, #12]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000b70: 2301 movs r3, #1
8000b72: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000b76: 2300 movs r3, #0
8000b78: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b7c: f003 feeb bl 8004956 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b80: f000 f938 bl 8000df4 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b84: f000 fe46 bl 8001814 <MX_GPIO_Init>
MX_ADC3_Init();
8000b88: f000 fa2a bl 8000fe0 <MX_ADC3_Init>
MX_LTDC_Init();
8000b8c: f000 faf8 bl 8001180 <MX_LTDC_Init>
MX_SPI2_Init();
8000b90: f000 fb8c bl 80012ac <MX_SPI2_Init>
MX_TIM1_Init();
8000b94: f000 fbc8 bl 8001328 <MX_TIM1_Init>
MX_TIM2_Init();
8000b98: f000 fc1a bl 80013d0 <MX_TIM2_Init>
MX_TIM3_Init();
8000b9c: f000 fc66 bl 800146c <MX_TIM3_Init>
MX_TIM5_Init();
8000ba0: f000 fcf2 bl 8001588 <MX_TIM5_Init>
MX_TIM8_Init();
8000ba4: f000 fd3e bl 8001624 <MX_TIM8_Init>
MX_ADC1_Init();
8000ba8: f000 f9c8 bl 8000f3c <MX_ADC1_Init>
MX_DAC_Init();
8000bac: f000 fa8c bl 80010c8 <MX_DAC_Init>
MX_FMC_Init();
8000bb0: f000 fde2 bl 8001778 <MX_FMC_Init>
MX_DMA2D_Init();
8000bb4: f000 fab2 bl 800111c <MX_DMA2D_Init>
MX_CRC_Init();
8000bb8: f000 fa64 bl 8001084 <MX_CRC_Init>
MX_RNG_Init();
8000bbc: f000 fb62 bl 8001284 <MX_RNG_Init>
/* USER CODE BEGIN 2 */
BSP_LCD_Init();
8000bc0: f001 fed8 bl 8002974 <BSP_LCD_Init>
BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS);
8000bc4: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000
8000bc8: 2000 movs r0, #0
8000bca: f001 ff6b bl 8002aa4 <BSP_LCD_LayerDefaultInit>
BSP_LCD_LayerDefaultInit(1,
LCD_FB_START_ADDRESS + BSP_LCD_GetXSize() * BSP_LCD_GetYSize() * 4);
8000bce: f001 ff41 bl 8002a54 <BSP_LCD_GetXSize>
8000bd2: 4604 mov r4, r0
8000bd4: f001 ff52 bl 8002a7c <BSP_LCD_GetYSize>
8000bd8: 4603 mov r3, r0
8000bda: fb03 f304 mul.w r3, r3, r4
BSP_LCD_LayerDefaultInit(1,
8000bde: f103 5340 add.w r3, r3, #805306368 ; 0x30000000
8000be2: 009b lsls r3, r3, #2
8000be4: 4619 mov r1, r3
8000be6: 2001 movs r0, #1
8000be8: f001 ff5c bl 8002aa4 <BSP_LCD_LayerDefaultInit>
BSP_LCD_DisplayOn();
8000bec: f002 fb9e bl 800332c <BSP_LCD_DisplayOn>
BSP_LCD_SelectLayer(1);
8000bf0: 2001 movs r0, #1
8000bf2: f001 ffb7 bl 8002b64 <BSP_LCD_SelectLayer>
BSP_LCD_Clear(LCD_COLOR_BLACK);
8000bf6: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000bfa: f002 f80f bl 8002c1c <BSP_LCD_Clear>
BSP_LCD_SetFont(&Font12);
8000bfe: 486a ldr r0, [pc, #424] ; (8000da8 <main+0x24c>)
8000c00: f001 fff2 bl 8002be8 <BSP_LCD_SetFont>
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8000c04: 4869 ldr r0, [pc, #420] ; (8000dac <main+0x250>)
8000c06: f001 ffbd bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_SetBackColor(LCD_COLOR_BLACK);
8000c0a: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000c0e: f001 ffd1 bl 8002bb4 <BSP_LCD_SetBackColor>
BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
8000c12: f001 ff1f bl 8002a54 <BSP_LCD_GetXSize>
8000c16: 4603 mov r3, r0
8000c18: b29c uxth r4, r3
8000c1a: f001 ff2f bl 8002a7c <BSP_LCD_GetYSize>
8000c1e: 4603 mov r3, r0
8000c20: b29b uxth r3, r3
8000c22: 4619 mov r1, r3
8000c24: 4620 mov r0, r4
8000c26: f002 fedb bl 80039e0 <BSP_TS_Init>
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* Create the queue(s) */
/* definition and creation of Queue_J */
osMessageQDef(Queue_J, 16, uint16_t);
8000c2a: 4b61 ldr r3, [pc, #388] ; (8000db0 <main+0x254>)
8000c2c: f107 04a0 add.w r4, r7, #160 ; 0xa0
8000c30: cb0f ldmia r3, {r0, r1, r2, r3}
8000c32: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
8000c36: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000c3a: 2100 movs r1, #0
8000c3c: 4618 mov r0, r3
8000c3e: f00b f89d bl 800bd7c <osMessageCreate>
8000c42: 4602 mov r2, r0
8000c44: 4b5b ldr r3, [pc, #364] ; (8000db4 <main+0x258>)
8000c46: 601a str r2, [r3, #0]
/* definition and creation of Queue_N */
osMessageQDef(Queue_N, 3, struct Missile);
8000c48: 4b5b ldr r3, [pc, #364] ; (8000db8 <main+0x25c>)
8000c4a: f107 0490 add.w r4, r7, #144 ; 0x90
8000c4e: cb0f ldmia r3, {r0, r1, r2, r3}
8000c50: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_NHandle = osMessageCreate(osMessageQ(Queue_N), NULL);
8000c54: f107 0390 add.w r3, r7, #144 ; 0x90
8000c58: 2100 movs r1, #0
8000c5a: 4618 mov r0, r3
8000c5c: f00b f88e bl 800bd7c <osMessageCreate>
8000c60: 4602 mov r2, r0
8000c62: 4b56 ldr r3, [pc, #344] ; (8000dbc <main+0x260>)
8000c64: 601a str r2, [r3, #0]
/* definition and creation of Queue_F */
osMessageQDef(Queue_F, 16, uint16_t);
8000c66: 4b52 ldr r3, [pc, #328] ; (8000db0 <main+0x254>)
8000c68: f107 0480 add.w r4, r7, #128 ; 0x80
8000c6c: cb0f ldmia r3, {r0, r1, r2, r3}
8000c6e: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_FHandle = osMessageCreate(osMessageQ(Queue_F), NULL);
8000c72: f107 0380 add.w r3, r7, #128 ; 0x80
8000c76: 2100 movs r1, #0
8000c78: 4618 mov r0, r3
8000c7a: f00b f87f bl 800bd7c <osMessageCreate>
8000c7e: 4602 mov r2, r0
8000c80: 4b4f ldr r3, [pc, #316] ; (8000dc0 <main+0x264>)
8000c82: 601a str r2, [r3, #0]
/* definition and creation of Queue_E */
osMessageQDef(Queue_E, 16, uint16_t);
8000c84: 4b4a ldr r3, [pc, #296] ; (8000db0 <main+0x254>)
8000c86: f107 0470 add.w r4, r7, #112 ; 0x70
8000c8a: cb0f ldmia r3, {r0, r1, r2, r3}
8000c8c: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
8000c90: f107 0370 add.w r3, r7, #112 ; 0x70
8000c94: 2100 movs r1, #0
8000c96: 4618 mov r0, r3
8000c98: f00b f870 bl 800bd7c <osMessageCreate>
8000c9c: 4602 mov r2, r0
8000c9e: 4b49 ldr r3, [pc, #292] ; (8000dc4 <main+0x268>)
8000ca0: 601a str r2, [r3, #0]
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of GameMaster */
osThreadDef(GameMaster, f_GameMaster, osPriorityNormal, 0, 128);
8000ca2: 4b49 ldr r3, [pc, #292] ; (8000dc8 <main+0x26c>)
8000ca4: f107 0454 add.w r4, r7, #84 ; 0x54
8000ca8: 461d mov r5, r3
8000caa: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cac: c40f stmia r4!, {r0, r1, r2, r3}
8000cae: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cb2: e884 0007 stmia.w r4, {r0, r1, r2}
GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
8000cb6: f107 0354 add.w r3, r7, #84 ; 0x54
8000cba: 2100 movs r1, #0
8000cbc: 4618 mov r0, r3
8000cbe: f00a fe9c bl 800b9fa <osThreadCreate>
8000cc2: 4602 mov r2, r0
8000cc4: 4b41 ldr r3, [pc, #260] ; (8000dcc <main+0x270>)
8000cc6: 601a str r2, [r3, #0]
/* definition and creation of Joueur_1 */
osThreadDef(Joueur_1, f_Joueur_1, osPriorityNormal, 0, 128);
8000cc8: 4b41 ldr r3, [pc, #260] ; (8000dd0 <main+0x274>)
8000cca: f107 0438 add.w r4, r7, #56 ; 0x38
8000cce: 461d mov r5, r3
8000cd0: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cd2: c40f stmia r4!, {r0, r1, r2, r3}
8000cd4: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cd8: e884 0007 stmia.w r4, {r0, r1, r2}
Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
8000cdc: f107 0338 add.w r3, r7, #56 ; 0x38
8000ce0: 2100 movs r1, #0
8000ce2: 4618 mov r0, r3
8000ce4: f00a fe89 bl 800b9fa <osThreadCreate>
8000ce8: 4602 mov r2, r0
8000cea: 4b3a ldr r3, [pc, #232] ; (8000dd4 <main+0x278>)
8000cec: 601a str r2, [r3, #0]
/* definition and creation of Block_Enemie */
osThreadDef(Block_Enemie, f_block_enemie, osPriorityIdle, 0, 128);
8000cee: 4b3a ldr r3, [pc, #232] ; (8000dd8 <main+0x27c>)
8000cf0: f107 041c add.w r4, r7, #28
8000cf4: 461d mov r5, r3
8000cf6: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cf8: c40f stmia r4!, {r0, r1, r2, r3}
8000cfa: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cfe: e884 0007 stmia.w r4, {r0, r1, r2}
Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
8000d02: f107 031c add.w r3, r7, #28
8000d06: 2100 movs r1, #0
8000d08: 4618 mov r0, r3
8000d0a: f00a fe76 bl 800b9fa <osThreadCreate>
8000d0e: 4602 mov r2, r0
8000d10: 4b32 ldr r3, [pc, #200] ; (8000ddc <main+0x280>)
8000d12: 601a str r2, [r3, #0]
/* definition and creation of Projectile */
osThreadDef(Projectile, f_projectile, osPriorityNormal, 0, 128);
8000d14: 4b32 ldr r3, [pc, #200] ; (8000de0 <main+0x284>)
8000d16: 463c mov r4, r7
8000d18: 461d mov r5, r3
8000d1a: cd0f ldmia r5!, {r0, r1, r2, r3}
8000d1c: c40f stmia r4!, {r0, r1, r2, r3}
8000d1e: e895 0007 ldmia.w r5, {r0, r1, r2}
8000d22: e884 0007 stmia.w r4, {r0, r1, r2}
ProjectileHandle = osThreadCreate(osThread(Projectile), NULL);
8000d26: 463b mov r3, r7
8000d28: 2100 movs r1, #0
8000d2a: 4618 mov r0, r3
8000d2c: f00a fe65 bl 800b9fa <osThreadCreate>
8000d30: 4602 mov r2, r0
8000d32: 4b2c ldr r3, [pc, #176] ; (8000de4 <main+0x288>)
8000d34: 601a str r2, [r3, #0]
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* Start scheduler */
osKernelStart();
8000d36: f00a fe49 bl 800b9cc <osKernelStart>
// BSP_LCD_DisplayStringAtLine(5, (uint8_t *)text);
;
sConfig.Channel = ADC_CHANNEL_7;
8000d3a: 2307 movs r3, #7
8000d3c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d40: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d44: 4619 mov r1, r3
8000d46: 4828 ldr r0, [pc, #160] ; (8000de8 <main+0x28c>)
8000d48: f003 ffea bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d4c: 4826 ldr r0, [pc, #152] ; (8000de8 <main+0x28c>)
8000d4e: f003 fe95 bl 8004a7c <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_6;
8000d52: 2306 movs r3, #6
8000d54: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d58: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d5c: 4619 mov r1, r3
8000d5e: 4822 ldr r0, [pc, #136] ; (8000de8 <main+0x28c>)
8000d60: f003 ffde bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d64: 4820 ldr r0, [pc, #128] ; (8000de8 <main+0x28c>)
8000d66: f003 fe89 bl 8004a7c <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_8;
8000d6a: 2308 movs r3, #8
8000d6c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d70: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d74: 4619 mov r1, r3
8000d76: 481c ldr r0, [pc, #112] ; (8000de8 <main+0x28c>)
8000d78: f003 ffd2 bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d7c: 481a ldr r0, [pc, #104] ; (8000de8 <main+0x28c>)
8000d7e: f003 fe7d bl 8004a7c <HAL_ADC_Start>
HAL_ADC_Start(&hadc1);
8000d82: 481a ldr r0, [pc, #104] ; (8000dec <main+0x290>)
8000d84: f003 fe7a bl 8004a7c <HAL_ADC_Start>
BSP_TS_GetState(&TS_State);
8000d88: 4819 ldr r0, [pc, #100] ; (8000df0 <main+0x294>)
8000d8a: f002 fe69 bl 8003a60 <BSP_TS_GetState>
if (TS_State.touchDetected)
8000d8e: 4b18 ldr r3, [pc, #96] ; (8000df0 <main+0x294>)
8000d90: 781b ldrb r3, [r3, #0]
8000d92: 2b00 cmp r3, #0
8000d94: d0d1 beq.n 8000d3a <main+0x1de>
{
BSP_LCD_FillCircle(TS_State.touchX[0], TS_State.touchY[0], 4);
8000d96: 4b16 ldr r3, [pc, #88] ; (8000df0 <main+0x294>)
8000d98: 8858 ldrh r0, [r3, #2]
8000d9a: 4b15 ldr r3, [pc, #84] ; (8000df0 <main+0x294>)
8000d9c: 899b ldrh r3, [r3, #12]
8000d9e: 2204 movs r2, #4
8000da0: 4619 mov r1, r3
8000da2: f002 fa23 bl 80031ec <BSP_LCD_FillCircle>
sConfig.Channel = ADC_CHANNEL_7;
8000da6: e7c8 b.n 8000d3a <main+0x1de>
8000da8: 20000058 .word 0x20000058
8000dac: ff0000ff .word 0xff0000ff
8000db0: 0801be6c .word 0x0801be6c
8000db4: 20008920 .word 0x20008920
8000db8: 0801be7c .word 0x0801be7c
8000dbc: 20008b04 .word 0x20008b04
8000dc0: 20008b08 .word 0x20008b08
8000dc4: 20008bf8 .word 0x20008bf8
8000dc8: 0801be98 .word 0x0801be98
8000dcc: 20008b74 .word 0x20008b74
8000dd0: 0801bec0 .word 0x0801bec0
8000dd4: 20008948 .word 0x20008948
8000dd8: 0801beec .word 0x0801beec
8000ddc: 20008c30 .word 0x20008c30
8000de0: 0801bf14 .word 0x0801bf14
8000de4: 20008b20 .word 0x20008b20
8000de8: 20008abc .word 0x20008abc
8000dec: 20008a74 .word 0x20008a74
8000df0: 20000364 .word 0x20000364
08000df4 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000df4: b580 push {r7, lr}
8000df6: b0b4 sub sp, #208 ; 0xd0
8000df8: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000dfa: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000dfe: 2230 movs r2, #48 ; 0x30
8000e00: 2100 movs r1, #0
8000e02: 4618 mov r0, r3
8000e04: f01a f8fe bl 801b004 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000e08: f107 038c add.w r3, r7, #140 ; 0x8c
8000e0c: 2200 movs r2, #0
8000e0e: 601a str r2, [r3, #0]
8000e10: 605a str r2, [r3, #4]
8000e12: 609a str r2, [r3, #8]
8000e14: 60da str r2, [r3, #12]
8000e16: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000e18: f107 0308 add.w r3, r7, #8
8000e1c: 2284 movs r2, #132 ; 0x84
8000e1e: 2100 movs r1, #0
8000e20: 4618 mov r0, r3
8000e22: f01a f8ef bl 801b004 <memset>
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000e26: f007 fcc1 bl 80087ac <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000e2a: 4b41 ldr r3, [pc, #260] ; (8000f30 <SystemClock_Config+0x13c>)
8000e2c: 6c1b ldr r3, [r3, #64] ; 0x40
8000e2e: 4a40 ldr r2, [pc, #256] ; (8000f30 <SystemClock_Config+0x13c>)
8000e30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000e34: 6413 str r3, [r2, #64] ; 0x40
8000e36: 4b3e ldr r3, [pc, #248] ; (8000f30 <SystemClock_Config+0x13c>)
8000e38: 6c1b ldr r3, [r3, #64] ; 0x40
8000e3a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e3e: 607b str r3, [r7, #4]
8000e40: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000e42: 4b3c ldr r3, [pc, #240] ; (8000f34 <SystemClock_Config+0x140>)
8000e44: 681b ldr r3, [r3, #0]
8000e46: 4a3b ldr r2, [pc, #236] ; (8000f34 <SystemClock_Config+0x140>)
8000e48: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8000e4c: 6013 str r3, [r2, #0]
8000e4e: 4b39 ldr r3, [pc, #228] ; (8000f34 <SystemClock_Config+0x140>)
8000e50: 681b ldr r3, [r3, #0]
8000e52: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000e56: 603b str r3, [r7, #0]
8000e58: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000e5a: 2301 movs r3, #1
8000e5c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000e60: f44f 3380 mov.w r3, #65536 ; 0x10000
8000e64: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000e68: 2302 movs r3, #2
8000e6a: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000e6e: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000e72: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLM = 25;
8000e76: 2319 movs r3, #25
8000e78: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
RCC_OscInitStruct.PLL.PLLN = 400;
8000e7c: f44f 73c8 mov.w r3, #400 ; 0x190
8000e80: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000e84: 2302 movs r3, #2
8000e86: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
RCC_OscInitStruct.PLL.PLLQ = 9;
8000e8a: 2309 movs r3, #9
8000e8c: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000e90: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000e94: 4618 mov r0, r3
8000e96: f007 fce9 bl 800886c <HAL_RCC_OscConfig>
8000e9a: 4603 mov r3, r0
8000e9c: 2b00 cmp r3, #0
8000e9e: d001 beq.n 8000ea4 <SystemClock_Config+0xb0>
{
Error_Handler();
8000ea0: f001 fbc0 bl 8002624 <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000ea4: f007 fc92 bl 80087cc <HAL_PWREx_EnableOverDrive>
8000ea8: 4603 mov r3, r0
8000eaa: 2b00 cmp r3, #0
8000eac: d001 beq.n 8000eb2 <SystemClock_Config+0xbe>
{
Error_Handler();
8000eae: f001 fbb9 bl 8002624 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000eb2: 230f movs r3, #15
8000eb4: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000eb8: 2302 movs r3, #2
8000eba: f8c7 3090 str.w r3, [r7, #144] ; 0x90
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000ebe: 2300 movs r3, #0
8000ec0: f8c7 3094 str.w r3, [r7, #148] ; 0x94
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000ec4: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000ec8: f8c7 3098 str.w r3, [r7, #152] ; 0x98
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000ecc: f44f 5380 mov.w r3, #4096 ; 0x1000
8000ed0: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
8000ed4: f107 038c add.w r3, r7, #140 ; 0x8c
8000ed8: 2106 movs r1, #6
8000eda: 4618 mov r0, r3
8000edc: f007 ff6a bl 8008db4 <HAL_RCC_ClockConfig>
8000ee0: 4603 mov r3, r0
8000ee2: 2b00 cmp r3, #0
8000ee4: d001 beq.n 8000eea <SystemClock_Config+0xf6>
{
Error_Handler();
8000ee6: f001 fb9d bl 8002624 <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_CLK48;
8000eea: 4b13 ldr r3, [pc, #76] ; (8000f38 <SystemClock_Config+0x144>)
8000eec: 60bb str r3, [r7, #8]
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
8000eee: f44f 73c0 mov.w r3, #384 ; 0x180
8000ef2: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
8000ef4: 2305 movs r3, #5
8000ef6: 627b str r3, [r7, #36] ; 0x24
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
8000ef8: 2302 movs r3, #2
8000efa: 623b str r3, [r7, #32]
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
8000efc: 2303 movs r3, #3
8000efe: 62bb str r3, [r7, #40] ; 0x28
PeriphClkInitStruct.PLLSAIDivQ = 1;
8000f00: 2301 movs r3, #1
8000f02: 633b str r3, [r7, #48] ; 0x30
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
8000f04: f44f 3300 mov.w r3, #131072 ; 0x20000
8000f08: 637b str r3, [r7, #52] ; 0x34
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
8000f0a: f04f 6300 mov.w r3, #134217728 ; 0x8000000
8000f0e: f8c7 3084 str.w r3, [r7, #132] ; 0x84
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000f12: f107 0308 add.w r3, r7, #8
8000f16: 4618 mov r0, r3
8000f18: f008 f93c bl 8009194 <HAL_RCCEx_PeriphCLKConfig>
8000f1c: 4603 mov r3, r0
8000f1e: 2b00 cmp r3, #0
8000f20: d001 beq.n 8000f26 <SystemClock_Config+0x132>
{
Error_Handler();
8000f22: f001 fb7f bl 8002624 <Error_Handler>
}
}
8000f26: bf00 nop
8000f28: 37d0 adds r7, #208 ; 0xd0
8000f2a: 46bd mov sp, r7
8000f2c: bd80 pop {r7, pc}
8000f2e: bf00 nop
8000f30: 40023800 .word 0x40023800
8000f34: 40007000 .word 0x40007000
8000f38: 00200008 .word 0x00200008
08000f3c <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000f3c: b580 push {r7, lr}
8000f3e: b084 sub sp, #16
8000f40: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000f42: 463b mov r3, r7
8000f44: 2200 movs r2, #0
8000f46: 601a str r2, [r3, #0]
8000f48: 605a str r2, [r3, #4]
8000f4a: 609a str r2, [r3, #8]
8000f4c: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
8000f4e: 4b21 ldr r3, [pc, #132] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f50: 4a21 ldr r2, [pc, #132] ; (8000fd8 <MX_ADC1_Init+0x9c>)
8000f52: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000f54: 4b1f ldr r3, [pc, #124] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f56: f44f 3280 mov.w r2, #65536 ; 0x10000
8000f5a: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000f5c: 4b1d ldr r3, [pc, #116] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f5e: 2200 movs r2, #0
8000f60: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000f62: 4b1c ldr r3, [pc, #112] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f64: 2200 movs r2, #0
8000f66: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000f68: 4b1a ldr r3, [pc, #104] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f6a: 2200 movs r2, #0
8000f6c: 619a str r2, [r3, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000f6e: 4b19 ldr r3, [pc, #100] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f70: 2200 movs r2, #0
8000f72: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000f76: 4b17 ldr r3, [pc, #92] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f78: 2200 movs r2, #0
8000f7a: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000f7c: 4b15 ldr r3, [pc, #84] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f7e: 4a17 ldr r2, [pc, #92] ; (8000fdc <MX_ADC1_Init+0xa0>)
8000f80: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000f82: 4b14 ldr r3, [pc, #80] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f84: 2200 movs r2, #0
8000f86: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 1;
8000f88: 4b12 ldr r3, [pc, #72] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f8a: 2201 movs r2, #1
8000f8c: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = DISABLE;
8000f8e: 4b11 ldr r3, [pc, #68] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f90: 2200 movs r2, #0
8000f92: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000f96: 4b0f ldr r3, [pc, #60] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f98: 2201 movs r2, #1
8000f9a: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000f9c: 480d ldr r0, [pc, #52] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f9e: f003 fd29 bl 80049f4 <HAL_ADC_Init>
8000fa2: 4603 mov r3, r0
8000fa4: 2b00 cmp r3, #0
8000fa6: d001 beq.n 8000fac <MX_ADC1_Init+0x70>
{
Error_Handler();
8000fa8: f001 fb3c bl 8002624 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000fac: 2300 movs r3, #0
8000fae: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000fb0: 2301 movs r3, #1
8000fb2: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000fb4: 2300 movs r3, #0
8000fb6: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000fb8: 463b mov r3, r7
8000fba: 4619 mov r1, r3
8000fbc: 4805 ldr r0, [pc, #20] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000fbe: f003 feaf bl 8004d20 <HAL_ADC_ConfigChannel>
8000fc2: 4603 mov r3, r0
8000fc4: 2b00 cmp r3, #0
8000fc6: d001 beq.n 8000fcc <MX_ADC1_Init+0x90>
{
Error_Handler();
8000fc8: f001 fb2c bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000fcc: bf00 nop
8000fce: 3710 adds r7, #16
8000fd0: 46bd mov sp, r7
8000fd2: bd80 pop {r7, pc}
8000fd4: 20008a74 .word 0x20008a74
8000fd8: 40012000 .word 0x40012000
8000fdc: 0f000001 .word 0x0f000001
08000fe0 <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000fe0: b580 push {r7, lr}
8000fe2: b084 sub sp, #16
8000fe4: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000fe6: 463b mov r3, r7
8000fe8: 2200 movs r2, #0
8000fea: 601a str r2, [r3, #0]
8000fec: 605a str r2, [r3, #4]
8000fee: 609a str r2, [r3, #8]
8000ff0: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
8000ff2: 4b21 ldr r3, [pc, #132] ; (8001078 <MX_ADC3_Init+0x98>)
8000ff4: 4a21 ldr r2, [pc, #132] ; (800107c <MX_ADC3_Init+0x9c>)
8000ff6: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000ff8: 4b1f ldr r3, [pc, #124] ; (8001078 <MX_ADC3_Init+0x98>)
8000ffa: f44f 3280 mov.w r2, #65536 ; 0x10000
8000ffe: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
8001000: 4b1d ldr r3, [pc, #116] ; (8001078 <MX_ADC3_Init+0x98>)
8001002: 2200 movs r2, #0
8001004: 609a str r2, [r3, #8]
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001006: 4b1c ldr r3, [pc, #112] ; (8001078 <MX_ADC3_Init+0x98>)
8001008: 2200 movs r2, #0
800100a: 611a str r2, [r3, #16]
hadc3.Init.ContinuousConvMode = DISABLE;
800100c: 4b1a ldr r3, [pc, #104] ; (8001078 <MX_ADC3_Init+0x98>)
800100e: 2200 movs r2, #0
8001010: 619a str r2, [r3, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
8001012: 4b19 ldr r3, [pc, #100] ; (8001078 <MX_ADC3_Init+0x98>)
8001014: 2200 movs r2, #0
8001016: f883 2020 strb.w r2, [r3, #32]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800101a: 4b17 ldr r3, [pc, #92] ; (8001078 <MX_ADC3_Init+0x98>)
800101c: 2200 movs r2, #0
800101e: 62da str r2, [r3, #44] ; 0x2c
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001020: 4b15 ldr r3, [pc, #84] ; (8001078 <MX_ADC3_Init+0x98>)
8001022: 4a17 ldr r2, [pc, #92] ; (8001080 <MX_ADC3_Init+0xa0>)
8001024: 629a str r2, [r3, #40] ; 0x28
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001026: 4b14 ldr r3, [pc, #80] ; (8001078 <MX_ADC3_Init+0x98>)
8001028: 2200 movs r2, #0
800102a: 60da str r2, [r3, #12]
hadc3.Init.NbrOfConversion = 1;
800102c: 4b12 ldr r3, [pc, #72] ; (8001078 <MX_ADC3_Init+0x98>)
800102e: 2201 movs r2, #1
8001030: 61da str r2, [r3, #28]
hadc3.Init.DMAContinuousRequests = DISABLE;
8001032: 4b11 ldr r3, [pc, #68] ; (8001078 <MX_ADC3_Init+0x98>)
8001034: 2200 movs r2, #0
8001036: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800103a: 4b0f ldr r3, [pc, #60] ; (8001078 <MX_ADC3_Init+0x98>)
800103c: 2201 movs r2, #1
800103e: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
8001040: 480d ldr r0, [pc, #52] ; (8001078 <MX_ADC3_Init+0x98>)
8001042: f003 fcd7 bl 80049f4 <HAL_ADC_Init>
8001046: 4603 mov r3, r0
8001048: 2b00 cmp r3, #0
800104a: d001 beq.n 8001050 <MX_ADC3_Init+0x70>
{
Error_Handler();
800104c: f001 faea bl 8002624 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_8;
8001050: 2308 movs r3, #8
8001052: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001054: 2301 movs r3, #1
8001056: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001058: 2300 movs r3, #0
800105a: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
800105c: 463b mov r3, r7
800105e: 4619 mov r1, r3
8001060: 4805 ldr r0, [pc, #20] ; (8001078 <MX_ADC3_Init+0x98>)
8001062: f003 fe5d bl 8004d20 <HAL_ADC_ConfigChannel>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <MX_ADC3_Init+0x90>
{
Error_Handler();
800106c: f001 fada bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
8001070: bf00 nop
8001072: 3710 adds r7, #16
8001074: 46bd mov sp, r7
8001076: bd80 pop {r7, pc}
8001078: 20008abc .word 0x20008abc
800107c: 40012200 .word 0x40012200
8001080: 0f000001 .word 0x0f000001
08001084 <MX_CRC_Init>:
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
8001084: b580 push {r7, lr}
8001086: af00 add r7, sp, #0
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
8001088: 4b0d ldr r3, [pc, #52] ; (80010c0 <MX_CRC_Init+0x3c>)
800108a: 4a0e ldr r2, [pc, #56] ; (80010c4 <MX_CRC_Init+0x40>)
800108c: 601a str r2, [r3, #0]
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
800108e: 4b0c ldr r3, [pc, #48] ; (80010c0 <MX_CRC_Init+0x3c>)
8001090: 2200 movs r2, #0
8001092: 711a strb r2, [r3, #4]
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
8001094: 4b0a ldr r3, [pc, #40] ; (80010c0 <MX_CRC_Init+0x3c>)
8001096: 2200 movs r2, #0
8001098: 715a strb r2, [r3, #5]
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
800109a: 4b09 ldr r3, [pc, #36] ; (80010c0 <MX_CRC_Init+0x3c>)
800109c: 2200 movs r2, #0
800109e: 615a str r2, [r3, #20]
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
80010a0: 4b07 ldr r3, [pc, #28] ; (80010c0 <MX_CRC_Init+0x3c>)
80010a2: 2200 movs r2, #0
80010a4: 619a str r2, [r3, #24]
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
80010a6: 4b06 ldr r3, [pc, #24] ; (80010c0 <MX_CRC_Init+0x3c>)
80010a8: 2201 movs r2, #1
80010aa: 621a str r2, [r3, #32]
if (HAL_CRC_Init(&hcrc) != HAL_OK)
80010ac: 4804 ldr r0, [pc, #16] ; (80010c0 <MX_CRC_Init+0x3c>)
80010ae: f004 f95d bl 800536c <HAL_CRC_Init>
80010b2: 4603 mov r3, r0
80010b4: 2b00 cmp r3, #0
80010b6: d001 beq.n 80010bc <MX_CRC_Init+0x38>
{
Error_Handler();
80010b8: f001 fab4 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
80010bc: bf00 nop
80010be: bd80 pop {r7, pc}
80010c0: 20008924 .word 0x20008924
80010c4: 40023000 .word 0x40023000
080010c8 <MX_DAC_Init>:
* @brief DAC Initialization Function
* @param None
* @retval None
*/
static void MX_DAC_Init(void)
{
80010c8: b580 push {r7, lr}
80010ca: b082 sub sp, #8
80010cc: af00 add r7, sp, #0
/* USER CODE BEGIN DAC_Init 0 */
/* USER CODE END DAC_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
80010ce: 463b mov r3, r7
80010d0: 2200 movs r2, #0
80010d2: 601a str r2, [r3, #0]
80010d4: 605a str r2, [r3, #4]
/* USER CODE BEGIN DAC_Init 1 */
/* USER CODE END DAC_Init 1 */
/** DAC Initialization
*/
hdac.Instance = DAC;
80010d6: 4b0f ldr r3, [pc, #60] ; (8001114 <MX_DAC_Init+0x4c>)
80010d8: 4a0f ldr r2, [pc, #60] ; (8001118 <MX_DAC_Init+0x50>)
80010da: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac) != HAL_OK)
80010dc: 480d ldr r0, [pc, #52] ; (8001114 <MX_DAC_Init+0x4c>)
80010de: f004 fa2f bl 8005540 <HAL_DAC_Init>
80010e2: 4603 mov r3, r0
80010e4: 2b00 cmp r3, #0
80010e6: d001 beq.n 80010ec <MX_DAC_Init+0x24>
{
Error_Handler();
80010e8: f001 fa9c bl 8002624 <Error_Handler>
}
/** DAC channel OUT1 config
*/
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
80010ec: 2300 movs r3, #0
80010ee: 603b str r3, [r7, #0]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
80010f0: 2300 movs r3, #0
80010f2: 607b str r3, [r7, #4]
if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
80010f4: 463b mov r3, r7
80010f6: 2200 movs r2, #0
80010f8: 4619 mov r1, r3
80010fa: 4806 ldr r0, [pc, #24] ; (8001114 <MX_DAC_Init+0x4c>)
80010fc: f004 fa96 bl 800562c <HAL_DAC_ConfigChannel>
8001100: 4603 mov r3, r0
8001102: 2b00 cmp r3, #0
8001104: d001 beq.n 800110a <MX_DAC_Init+0x42>
{
Error_Handler();
8001106: f001 fa8d bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN DAC_Init 2 */
/* USER CODE END DAC_Init 2 */
}
800110a: bf00 nop
800110c: 3708 adds r7, #8
800110e: 46bd mov sp, r7
8001110: bd80 pop {r7, pc}
8001112: bf00 nop
8001114: 20008b0c .word 0x20008b0c
8001118: 40007400 .word 0x40007400
0800111c <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
800111c: b580 push {r7, lr}
800111e: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
8001120: 4b15 ldr r3, [pc, #84] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001122: 4a16 ldr r2, [pc, #88] ; (800117c <MX_DMA2D_Init+0x60>)
8001124: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
8001126: 4b14 ldr r3, [pc, #80] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001128: 2200 movs r2, #0
800112a: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
800112c: 4b12 ldr r3, [pc, #72] ; (8001178 <MX_DMA2D_Init+0x5c>)
800112e: 2200 movs r2, #0
8001130: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
8001132: 4b11 ldr r3, [pc, #68] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001134: 2200 movs r2, #0
8001136: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
8001138: 4b0f ldr r3, [pc, #60] ; (8001178 <MX_DMA2D_Init+0x5c>)
800113a: 2200 movs r2, #0
800113c: 629a str r2, [r3, #40] ; 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
800113e: 4b0e ldr r3, [pc, #56] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001140: 2200 movs r2, #0
8001142: 62da str r2, [r3, #44] ; 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
8001144: 4b0c ldr r3, [pc, #48] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001146: 2200 movs r2, #0
8001148: 631a str r2, [r3, #48] ; 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
800114a: 4b0b ldr r3, [pc, #44] ; (8001178 <MX_DMA2D_Init+0x5c>)
800114c: 2200 movs r2, #0
800114e: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
8001150: 4809 ldr r0, [pc, #36] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001152: f004 fc7f bl 8005a54 <HAL_DMA2D_Init>
8001156: 4603 mov r3, r0
8001158: 2b00 cmp r3, #0
800115a: d001 beq.n 8001160 <MX_DMA2D_Init+0x44>
{
Error_Handler();
800115c: f001 fa62 bl 8002624 <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
8001160: 2101 movs r1, #1
8001162: 4805 ldr r0, [pc, #20] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001164: f004 fdd4 bl 8005d10 <HAL_DMA2D_ConfigLayer>
8001168: 4603 mov r3, r0
800116a: 2b00 cmp r3, #0
800116c: d001 beq.n 8001172 <MX_DMA2D_Init+0x56>
{
Error_Handler();
800116e: f001 fa59 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
8001172: bf00 nop
8001174: bd80 pop {r7, pc}
8001176: bf00 nop
8001178: 20008b78 .word 0x20008b78
800117c: 4002b000 .word 0x4002b000
08001180 <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
8001180: b580 push {r7, lr}
8001182: b08e sub sp, #56 ; 0x38
8001184: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
8001186: 1d3b adds r3, r7, #4
8001188: 2234 movs r2, #52 ; 0x34
800118a: 2100 movs r1, #0
800118c: 4618 mov r0, r3
800118e: f019 ff39 bl 801b004 <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
8001192: 4b3a ldr r3, [pc, #232] ; (800127c <MX_LTDC_Init+0xfc>)
8001194: 4a3a ldr r2, [pc, #232] ; (8001280 <MX_LTDC_Init+0x100>)
8001196: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
8001198: 4b38 ldr r3, [pc, #224] ; (800127c <MX_LTDC_Init+0xfc>)
800119a: 2200 movs r2, #0
800119c: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
800119e: 4b37 ldr r3, [pc, #220] ; (800127c <MX_LTDC_Init+0xfc>)
80011a0: 2200 movs r2, #0
80011a2: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80011a4: 4b35 ldr r3, [pc, #212] ; (800127c <MX_LTDC_Init+0xfc>)
80011a6: 2200 movs r2, #0
80011a8: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80011aa: 4b34 ldr r3, [pc, #208] ; (800127c <MX_LTDC_Init+0xfc>)
80011ac: 2200 movs r2, #0
80011ae: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 40;
80011b0: 4b32 ldr r3, [pc, #200] ; (800127c <MX_LTDC_Init+0xfc>)
80011b2: 2228 movs r2, #40 ; 0x28
80011b4: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 9;
80011b6: 4b31 ldr r3, [pc, #196] ; (800127c <MX_LTDC_Init+0xfc>)
80011b8: 2209 movs r2, #9
80011ba: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 53;
80011bc: 4b2f ldr r3, [pc, #188] ; (800127c <MX_LTDC_Init+0xfc>)
80011be: 2235 movs r2, #53 ; 0x35
80011c0: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 11;
80011c2: 4b2e ldr r3, [pc, #184] ; (800127c <MX_LTDC_Init+0xfc>)
80011c4: 220b movs r2, #11
80011c6: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 533;
80011c8: 4b2c ldr r3, [pc, #176] ; (800127c <MX_LTDC_Init+0xfc>)
80011ca: f240 2215 movw r2, #533 ; 0x215
80011ce: 625a str r2, [r3, #36] ; 0x24
hltdc.Init.AccumulatedActiveH = 283;
80011d0: 4b2a ldr r3, [pc, #168] ; (800127c <MX_LTDC_Init+0xfc>)
80011d2: f240 121b movw r2, #283 ; 0x11b
80011d6: 629a str r2, [r3, #40] ; 0x28
hltdc.Init.TotalWidth = 565;
80011d8: 4b28 ldr r3, [pc, #160] ; (800127c <MX_LTDC_Init+0xfc>)
80011da: f240 2235 movw r2, #565 ; 0x235
80011de: 62da str r2, [r3, #44] ; 0x2c
hltdc.Init.TotalHeigh = 285;
80011e0: 4b26 ldr r3, [pc, #152] ; (800127c <MX_LTDC_Init+0xfc>)
80011e2: f240 121d movw r2, #285 ; 0x11d
80011e6: 631a str r2, [r3, #48] ; 0x30
hltdc.Init.Backcolor.Blue = 0;
80011e8: 4b24 ldr r3, [pc, #144] ; (800127c <MX_LTDC_Init+0xfc>)
80011ea: 2200 movs r2, #0
80011ec: f883 2034 strb.w r2, [r3, #52] ; 0x34
hltdc.Init.Backcolor.Green = 0;
80011f0: 4b22 ldr r3, [pc, #136] ; (800127c <MX_LTDC_Init+0xfc>)
80011f2: 2200 movs r2, #0
80011f4: f883 2035 strb.w r2, [r3, #53] ; 0x35
hltdc.Init.Backcolor.Red = 0;
80011f8: 4b20 ldr r3, [pc, #128] ; (800127c <MX_LTDC_Init+0xfc>)
80011fa: 2200 movs r2, #0
80011fc: f883 2036 strb.w r2, [r3, #54] ; 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
8001200: 481e ldr r0, [pc, #120] ; (800127c <MX_LTDC_Init+0xfc>)
8001202: f006 ff5b bl 80080bc <HAL_LTDC_Init>
8001206: 4603 mov r3, r0
8001208: 2b00 cmp r3, #0
800120a: d001 beq.n 8001210 <MX_LTDC_Init+0x90>
{
Error_Handler();
800120c: f001 fa0a bl 8002624 <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
8001210: 2300 movs r3, #0
8001212: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 480;
8001214: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001218: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
800121a: 2300 movs r3, #0
800121c: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 272;
800121e: f44f 7388 mov.w r3, #272 ; 0x110
8001222: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
8001224: 2302 movs r3, #2
8001226: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
8001228: 23ff movs r3, #255 ; 0xff
800122a: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
800122c: 2300 movs r3, #0
800122e: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8001230: f44f 63c0 mov.w r3, #1536 ; 0x600
8001234: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8001236: 2307 movs r3, #7
8001238: 627b str r3, [r7, #36] ; 0x24
pLayerCfg.FBStartAdress = 0xC0000000;
800123a: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000
800123e: 62bb str r3, [r7, #40] ; 0x28
pLayerCfg.ImageWidth = 480;
8001240: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001244: 62fb str r3, [r7, #44] ; 0x2c
pLayerCfg.ImageHeight = 272;
8001246: f44f 7388 mov.w r3, #272 ; 0x110
800124a: 633b str r3, [r7, #48] ; 0x30
pLayerCfg.Backcolor.Blue = 0;
800124c: 2300 movs r3, #0
800124e: f887 3034 strb.w r3, [r7, #52] ; 0x34
pLayerCfg.Backcolor.Green = 0;
8001252: 2300 movs r3, #0
8001254: f887 3035 strb.w r3, [r7, #53] ; 0x35
pLayerCfg.Backcolor.Red = 0;
8001258: 2300 movs r3, #0
800125a: f887 3036 strb.w r3, [r7, #54] ; 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
800125e: 1d3b adds r3, r7, #4
8001260: 2200 movs r2, #0
8001262: 4619 mov r1, r3
8001264: 4805 ldr r0, [pc, #20] ; (800127c <MX_LTDC_Init+0xfc>)
8001266: f007 f8bb bl 80083e0 <HAL_LTDC_ConfigLayer>
800126a: 4603 mov r3, r0
800126c: 2b00 cmp r3, #0
800126e: d001 beq.n 8001274 <MX_LTDC_Init+0xf4>
{
Error_Handler();
8001270: f001 f9d8 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
8001274: bf00 nop
8001276: 3738 adds r7, #56 ; 0x38
8001278: 46bd mov sp, r7
800127a: bd80 pop {r7, pc}
800127c: 200089cc .word 0x200089cc
8001280: 40016800 .word 0x40016800
08001284 <MX_RNG_Init>:
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
8001284: b580 push {r7, lr}
8001286: af00 add r7, sp, #0
/* USER CODE END RNG_Init 0 */
/* USER CODE BEGIN RNG_Init 1 */
/* USER CODE END RNG_Init 1 */
hrng.Instance = RNG;
8001288: 4b06 ldr r3, [pc, #24] ; (80012a4 <MX_RNG_Init+0x20>)
800128a: 4a07 ldr r2, [pc, #28] ; (80012a8 <MX_RNG_Init+0x24>)
800128c: 601a str r2, [r3, #0]
if (HAL_RNG_Init(&hrng) != HAL_OK)
800128e: 4805 ldr r0, [pc, #20] ; (80012a4 <MX_RNG_Init+0x20>)
8001290: f008 fb6e bl 8009970 <HAL_RNG_Init>
8001294: 4603 mov r3, r0
8001296: 2b00 cmp r3, #0
8001298: d001 beq.n 800129e <MX_RNG_Init+0x1a>
{
Error_Handler();
800129a: f001 f9c3 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN RNG_Init 2 */
/* USER CODE END RNG_Init 2 */
}
800129e: bf00 nop
80012a0: bd80 pop {r7, pc}
80012a2: bf00 nop
80012a4: 20008b64 .word 0x20008b64
80012a8: 50060800 .word 0x50060800
080012ac <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
80012ac: b580 push {r7, lr}
80012ae: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
80012b0: 4b1b ldr r3, [pc, #108] ; (8001320 <MX_SPI2_Init+0x74>)
80012b2: 4a1c ldr r2, [pc, #112] ; (8001324 <MX_SPI2_Init+0x78>)
80012b4: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
80012b6: 4b1a ldr r3, [pc, #104] ; (8001320 <MX_SPI2_Init+0x74>)
80012b8: f44f 7282 mov.w r2, #260 ; 0x104
80012bc: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
80012be: 4b18 ldr r3, [pc, #96] ; (8001320 <MX_SPI2_Init+0x74>)
80012c0: 2200 movs r2, #0
80012c2: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
80012c4: 4b16 ldr r3, [pc, #88] ; (8001320 <MX_SPI2_Init+0x74>)
80012c6: f44f 7240 mov.w r2, #768 ; 0x300
80012ca: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
80012cc: 4b14 ldr r3, [pc, #80] ; (8001320 <MX_SPI2_Init+0x74>)
80012ce: 2200 movs r2, #0
80012d0: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
80012d2: 4b13 ldr r3, [pc, #76] ; (8001320 <MX_SPI2_Init+0x74>)
80012d4: 2200 movs r2, #0
80012d6: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
80012d8: 4b11 ldr r3, [pc, #68] ; (8001320 <MX_SPI2_Init+0x74>)
80012da: f44f 2280 mov.w r2, #262144 ; 0x40000
80012de: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80012e0: 4b0f ldr r3, [pc, #60] ; (8001320 <MX_SPI2_Init+0x74>)
80012e2: 2200 movs r2, #0
80012e4: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
80012e6: 4b0e ldr r3, [pc, #56] ; (8001320 <MX_SPI2_Init+0x74>)
80012e8: 2200 movs r2, #0
80012ea: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
80012ec: 4b0c ldr r3, [pc, #48] ; (8001320 <MX_SPI2_Init+0x74>)
80012ee: 2200 movs r2, #0
80012f0: 625a str r2, [r3, #36] ; 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80012f2: 4b0b ldr r3, [pc, #44] ; (8001320 <MX_SPI2_Init+0x74>)
80012f4: 2200 movs r2, #0
80012f6: 629a str r2, [r3, #40] ; 0x28
hspi2.Init.CRCPolynomial = 7;
80012f8: 4b09 ldr r3, [pc, #36] ; (8001320 <MX_SPI2_Init+0x74>)
80012fa: 2207 movs r2, #7
80012fc: 62da str r2, [r3, #44] ; 0x2c
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80012fe: 4b08 ldr r3, [pc, #32] ; (8001320 <MX_SPI2_Init+0x74>)
8001300: 2200 movs r2, #0
8001302: 631a str r2, [r3, #48] ; 0x30
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
8001304: 4b06 ldr r3, [pc, #24] ; (8001320 <MX_SPI2_Init+0x74>)
8001306: 2208 movs r2, #8
8001308: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi2) != HAL_OK)
800130a: 4805 ldr r0, [pc, #20] ; (8001320 <MX_SPI2_Init+0x74>)
800130c: f008 fbd9 bl 8009ac2 <HAL_SPI_Init>
8001310: 4603 mov r3, r0
8001312: 2b00 cmp r3, #0
8001314: d001 beq.n 800131a <MX_SPI2_Init+0x6e>
{
Error_Handler();
8001316: f001 f985 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
800131a: bf00 nop
800131c: bd80 pop {r7, pc}
800131e: bf00 nop
8001320: 2000887c .word 0x2000887c
8001324: 40003800 .word 0x40003800
08001328 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8001328: b580 push {r7, lr}
800132a: b088 sub sp, #32
800132c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800132e: f107 0310 add.w r3, r7, #16
8001332: 2200 movs r2, #0
8001334: 601a str r2, [r3, #0]
8001336: 605a str r2, [r3, #4]
8001338: 609a str r2, [r3, #8]
800133a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800133c: 1d3b adds r3, r7, #4
800133e: 2200 movs r2, #0
8001340: 601a str r2, [r3, #0]
8001342: 605a str r2, [r3, #4]
8001344: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8001346: 4b20 ldr r3, [pc, #128] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001348: 4a20 ldr r2, [pc, #128] ; (80013cc <MX_TIM1_Init+0xa4>)
800134a: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800134c: 4b1e ldr r3, [pc, #120] ; (80013c8 <MX_TIM1_Init+0xa0>)
800134e: 2200 movs r2, #0
8001350: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8001352: 4b1d ldr r3, [pc, #116] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001354: 2200 movs r2, #0
8001356: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
8001358: 4b1b ldr r3, [pc, #108] ; (80013c8 <MX_TIM1_Init+0xa0>)
800135a: f64f 72ff movw r2, #65535 ; 0xffff
800135e: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001360: 4b19 ldr r3, [pc, #100] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001362: 2200 movs r2, #0
8001364: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8001366: 4b18 ldr r3, [pc, #96] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001368: 2200 movs r2, #0
800136a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800136c: 4b16 ldr r3, [pc, #88] ; (80013c8 <MX_TIM1_Init+0xa0>)
800136e: 2200 movs r2, #0
8001370: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001372: 4815 ldr r0, [pc, #84] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001374: f008 fc37 bl 8009be6 <HAL_TIM_Base_Init>
8001378: 4603 mov r3, r0
800137a: 2b00 cmp r3, #0
800137c: d001 beq.n 8001382 <MX_TIM1_Init+0x5a>
{
Error_Handler();
800137e: f001 f951 bl 8002624 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001382: f44f 5380 mov.w r3, #4096 ; 0x1000
8001386: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001388: f107 0310 add.w r3, r7, #16
800138c: 4619 mov r1, r3
800138e: 480e ldr r0, [pc, #56] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001390: f008 feea bl 800a168 <HAL_TIM_ConfigClockSource>
8001394: 4603 mov r3, r0
8001396: 2b00 cmp r3, #0
8001398: d001 beq.n 800139e <MX_TIM1_Init+0x76>
{
Error_Handler();
800139a: f001 f943 bl 8002624 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800139e: 2300 movs r3, #0
80013a0: 607b str r3, [r7, #4]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
80013a2: 2300 movs r3, #0
80013a4: 60bb str r3, [r7, #8]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80013a6: 2300 movs r3, #0
80013a8: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
80013aa: 1d3b adds r3, r7, #4
80013ac: 4619 mov r1, r3
80013ae: 4806 ldr r0, [pc, #24] ; (80013c8 <MX_TIM1_Init+0xa0>)
80013b0: f009 fc1e bl 800abf0 <HAL_TIMEx_MasterConfigSynchronization>
80013b4: 4603 mov r3, r0
80013b6: 2b00 cmp r3, #0
80013b8: d001 beq.n 80013be <MX_TIM1_Init+0x96>
{
Error_Handler();
80013ba: f001 f933 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
80013be: bf00 nop
80013c0: 3720 adds r7, #32
80013c2: 46bd mov sp, r7
80013c4: bd80 pop {r7, pc}
80013c6: bf00 nop
80013c8: 20008b24 .word 0x20008b24
80013cc: 40010000 .word 0x40010000
080013d0 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80013d0: b580 push {r7, lr}
80013d2: b088 sub sp, #32
80013d4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80013d6: f107 0310 add.w r3, r7, #16
80013da: 2200 movs r2, #0
80013dc: 601a str r2, [r3, #0]
80013de: 605a str r2, [r3, #4]
80013e0: 609a str r2, [r3, #8]
80013e2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80013e4: 1d3b adds r3, r7, #4
80013e6: 2200 movs r2, #0
80013e8: 601a str r2, [r3, #0]
80013ea: 605a str r2, [r3, #4]
80013ec: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80013ee: 4b1e ldr r3, [pc, #120] ; (8001468 <MX_TIM2_Init+0x98>)
80013f0: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
80013f4: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80013f6: 4b1c ldr r3, [pc, #112] ; (8001468 <MX_TIM2_Init+0x98>)
80013f8: 2200 movs r2, #0
80013fa: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80013fc: 4b1a ldr r3, [pc, #104] ; (8001468 <MX_TIM2_Init+0x98>)
80013fe: 2200 movs r2, #0
8001400: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
8001402: 4b19 ldr r3, [pc, #100] ; (8001468 <MX_TIM2_Init+0x98>)
8001404: f04f 32ff mov.w r2, #4294967295
8001408: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800140a: 4b17 ldr r3, [pc, #92] ; (8001468 <MX_TIM2_Init+0x98>)
800140c: 2200 movs r2, #0
800140e: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001410: 4b15 ldr r3, [pc, #84] ; (8001468 <MX_TIM2_Init+0x98>)
8001412: 2200 movs r2, #0
8001414: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8001416: 4814 ldr r0, [pc, #80] ; (8001468 <MX_TIM2_Init+0x98>)
8001418: f008 fbe5 bl 8009be6 <HAL_TIM_Base_Init>
800141c: 4603 mov r3, r0
800141e: 2b00 cmp r3, #0
8001420: d001 beq.n 8001426 <MX_TIM2_Init+0x56>
{
Error_Handler();
8001422: f001 f8ff bl 8002624 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001426: f44f 5380 mov.w r3, #4096 ; 0x1000
800142a: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
800142c: f107 0310 add.w r3, r7, #16
8001430: 4619 mov r1, r3
8001432: 480d ldr r0, [pc, #52] ; (8001468 <MX_TIM2_Init+0x98>)
8001434: f008 fe98 bl 800a168 <HAL_TIM_ConfigClockSource>
8001438: 4603 mov r3, r0
800143a: 2b00 cmp r3, #0
800143c: d001 beq.n 8001442 <MX_TIM2_Init+0x72>
{
Error_Handler();
800143e: f001 f8f1 bl 8002624 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001442: 2300 movs r3, #0
8001444: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001446: 2300 movs r3, #0
8001448: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
800144a: 1d3b adds r3, r7, #4
800144c: 4619 mov r1, r3
800144e: 4806 ldr r0, [pc, #24] ; (8001468 <MX_TIM2_Init+0x98>)
8001450: f009 fbce bl 800abf0 <HAL_TIMEx_MasterConfigSynchronization>
8001454: 4603 mov r3, r0
8001456: 2b00 cmp r3, #0
8001458: d001 beq.n 800145e <MX_TIM2_Init+0x8e>
{
Error_Handler();
800145a: f001 f8e3 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
800145e: bf00 nop
8001460: 3720 adds r7, #32
8001462: 46bd mov sp, r7
8001464: bd80 pop {r7, pc}
8001466: bf00 nop
8001468: 20008bb8 .word 0x20008bb8
0800146c <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
800146c: b580 push {r7, lr}
800146e: b094 sub sp, #80 ; 0x50
8001470: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001472: f107 0340 add.w r3, r7, #64 ; 0x40
8001476: 2200 movs r2, #0
8001478: 601a str r2, [r3, #0]
800147a: 605a str r2, [r3, #4]
800147c: 609a str r2, [r3, #8]
800147e: 60da str r2, [r3, #12]
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
8001480: f107 032c add.w r3, r7, #44 ; 0x2c
8001484: 2200 movs r2, #0
8001486: 601a str r2, [r3, #0]
8001488: 605a str r2, [r3, #4]
800148a: 609a str r2, [r3, #8]
800148c: 60da str r2, [r3, #12]
800148e: 611a str r2, [r3, #16]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001490: f107 0320 add.w r3, r7, #32
8001494: 2200 movs r2, #0
8001496: 601a str r2, [r3, #0]
8001498: 605a str r2, [r3, #4]
800149a: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
800149c: 1d3b adds r3, r7, #4
800149e: 2200 movs r2, #0
80014a0: 601a str r2, [r3, #0]
80014a2: 605a str r2, [r3, #4]
80014a4: 609a str r2, [r3, #8]
80014a6: 60da str r2, [r3, #12]
80014a8: 611a str r2, [r3, #16]
80014aa: 615a str r2, [r3, #20]
80014ac: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80014ae: 4b34 ldr r3, [pc, #208] ; (8001580 <MX_TIM3_Init+0x114>)
80014b0: 4a34 ldr r2, [pc, #208] ; (8001584 <MX_TIM3_Init+0x118>)
80014b2: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80014b4: 4b32 ldr r3, [pc, #200] ; (8001580 <MX_TIM3_Init+0x114>)
80014b6: 2200 movs r2, #0
80014b8: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80014ba: 4b31 ldr r3, [pc, #196] ; (8001580 <MX_TIM3_Init+0x114>)
80014bc: 2200 movs r2, #0
80014be: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
80014c0: 4b2f ldr r3, [pc, #188] ; (8001580 <MX_TIM3_Init+0x114>)
80014c2: f64f 72ff movw r2, #65535 ; 0xffff
80014c6: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80014c8: 4b2d ldr r3, [pc, #180] ; (8001580 <MX_TIM3_Init+0x114>)
80014ca: 2200 movs r2, #0
80014cc: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80014ce: 4b2c ldr r3, [pc, #176] ; (8001580 <MX_TIM3_Init+0x114>)
80014d0: 2200 movs r2, #0
80014d2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
80014d4: 482a ldr r0, [pc, #168] ; (8001580 <MX_TIM3_Init+0x114>)
80014d6: f008 fb86 bl 8009be6 <HAL_TIM_Base_Init>
80014da: 4603 mov r3, r0
80014dc: 2b00 cmp r3, #0
80014de: d001 beq.n 80014e4 <MX_TIM3_Init+0x78>
{
Error_Handler();
80014e0: f001 f8a0 bl 8002624 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80014e4: f44f 5380 mov.w r3, #4096 ; 0x1000
80014e8: 643b str r3, [r7, #64] ; 0x40
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
80014ea: f107 0340 add.w r3, r7, #64 ; 0x40
80014ee: 4619 mov r1, r3
80014f0: 4823 ldr r0, [pc, #140] ; (8001580 <MX_TIM3_Init+0x114>)
80014f2: f008 fe39 bl 800a168 <HAL_TIM_ConfigClockSource>
80014f6: 4603 mov r3, r0
80014f8: 2b00 cmp r3, #0
80014fa: d001 beq.n 8001500 <MX_TIM3_Init+0x94>
{
Error_Handler();
80014fc: f001 f892 bl 8002624 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8001500: 481f ldr r0, [pc, #124] ; (8001580 <MX_TIM3_Init+0x114>)
8001502: f008 fbc5 bl 8009c90 <HAL_TIM_PWM_Init>
8001506: 4603 mov r3, r0
8001508: 2b00 cmp r3, #0
800150a: d001 beq.n 8001510 <MX_TIM3_Init+0xa4>
{
Error_Handler();
800150c: f001 f88a bl 8002624 <Error_Handler>
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE;
8001510: 2300 movs r3, #0
8001512: 62fb str r3, [r7, #44] ; 0x2c
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
8001514: 2300 movs r3, #0
8001516: 633b str r3, [r7, #48] ; 0x30
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
8001518: f107 032c add.w r3, r7, #44 ; 0x2c
800151c: 4619 mov r1, r3
800151e: 4818 ldr r0, [pc, #96] ; (8001580 <MX_TIM3_Init+0x114>)
8001520: f008 fedc bl 800a2dc <HAL_TIM_SlaveConfigSynchro>
8001524: 4603 mov r3, r0
8001526: 2b00 cmp r3, #0
8001528: d001 beq.n 800152e <MX_TIM3_Init+0xc2>
{
Error_Handler();
800152a: f001 f87b bl 8002624 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800152e: 2300 movs r3, #0
8001530: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001532: 2300 movs r3, #0
8001534: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001536: f107 0320 add.w r3, r7, #32
800153a: 4619 mov r1, r3
800153c: 4810 ldr r0, [pc, #64] ; (8001580 <MX_TIM3_Init+0x114>)
800153e: f009 fb57 bl 800abf0 <HAL_TIMEx_MasterConfigSynchronization>
8001542: 4603 mov r3, r0
8001544: 2b00 cmp r3, #0
8001546: d001 beq.n 800154c <MX_TIM3_Init+0xe0>
{
Error_Handler();
8001548: f001 f86c bl 8002624 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800154c: 2360 movs r3, #96 ; 0x60
800154e: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
8001550: 2300 movs r3, #0
8001552: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001554: 2300 movs r3, #0
8001556: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001558: 2300 movs r3, #0
800155a: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800155c: 1d3b adds r3, r7, #4
800155e: 2200 movs r2, #0
8001560: 4619 mov r1, r3
8001562: 4807 ldr r0, [pc, #28] ; (8001580 <MX_TIM3_Init+0x114>)
8001564: f008 fce8 bl 8009f38 <HAL_TIM_PWM_ConfigChannel>
8001568: 4603 mov r3, r0
800156a: 2b00 cmp r3, #0
800156c: d001 beq.n 8001572 <MX_TIM3_Init+0x106>
{
Error_Handler();
800156e: f001 f859 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8001572: 4803 ldr r0, [pc, #12] ; (8001580 <MX_TIM3_Init+0x114>)
8001574: f002 ff7a bl 800446c <HAL_TIM_MspPostInit>
}
8001578: bf00 nop
800157a: 3750 adds r7, #80 ; 0x50
800157c: 46bd mov sp, r7
800157e: bd80 pop {r7, pc}
8001580: 2000898c .word 0x2000898c
8001584: 40000400 .word 0x40000400
08001588 <MX_TIM5_Init>:
* @brief TIM5 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM5_Init(void)
{
8001588: b580 push {r7, lr}
800158a: b088 sub sp, #32
800158c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800158e: f107 0310 add.w r3, r7, #16
8001592: 2200 movs r2, #0
8001594: 601a str r2, [r3, #0]
8001596: 605a str r2, [r3, #4]
8001598: 609a str r2, [r3, #8]
800159a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800159c: 1d3b adds r3, r7, #4
800159e: 2200 movs r2, #0
80015a0: 601a str r2, [r3, #0]
80015a2: 605a str r2, [r3, #4]
80015a4: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
80015a6: 4b1d ldr r3, [pc, #116] ; (800161c <MX_TIM5_Init+0x94>)
80015a8: 4a1d ldr r2, [pc, #116] ; (8001620 <MX_TIM5_Init+0x98>)
80015aa: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
80015ac: 4b1b ldr r3, [pc, #108] ; (800161c <MX_TIM5_Init+0x94>)
80015ae: 2200 movs r2, #0
80015b0: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
80015b2: 4b1a ldr r3, [pc, #104] ; (800161c <MX_TIM5_Init+0x94>)
80015b4: 2200 movs r2, #0
80015b6: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
80015b8: 4b18 ldr r3, [pc, #96] ; (800161c <MX_TIM5_Init+0x94>)
80015ba: f04f 32ff mov.w r2, #4294967295
80015be: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80015c0: 4b16 ldr r3, [pc, #88] ; (800161c <MX_TIM5_Init+0x94>)
80015c2: 2200 movs r2, #0
80015c4: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80015c6: 4b15 ldr r3, [pc, #84] ; (800161c <MX_TIM5_Init+0x94>)
80015c8: 2200 movs r2, #0
80015ca: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
80015cc: 4813 ldr r0, [pc, #76] ; (800161c <MX_TIM5_Init+0x94>)
80015ce: f008 fb0a bl 8009be6 <HAL_TIM_Base_Init>
80015d2: 4603 mov r3, r0
80015d4: 2b00 cmp r3, #0
80015d6: d001 beq.n 80015dc <MX_TIM5_Init+0x54>
{
Error_Handler();
80015d8: f001 f824 bl 8002624 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80015dc: f44f 5380 mov.w r3, #4096 ; 0x1000
80015e0: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
80015e2: f107 0310 add.w r3, r7, #16
80015e6: 4619 mov r1, r3
80015e8: 480c ldr r0, [pc, #48] ; (800161c <MX_TIM5_Init+0x94>)
80015ea: f008 fdbd bl 800a168 <HAL_TIM_ConfigClockSource>
80015ee: 4603 mov r3, r0
80015f0: 2b00 cmp r3, #0
80015f2: d001 beq.n 80015f8 <MX_TIM5_Init+0x70>
{
Error_Handler();
80015f4: f001 f816 bl 8002624 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80015f8: 2300 movs r3, #0
80015fa: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80015fc: 2300 movs r3, #0
80015fe: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
8001600: 1d3b adds r3, r7, #4
8001602: 4619 mov r1, r3
8001604: 4805 ldr r0, [pc, #20] ; (800161c <MX_TIM5_Init+0x94>)
8001606: f009 faf3 bl 800abf0 <HAL_TIMEx_MasterConfigSynchronization>
800160a: 4603 mov r3, r0
800160c: 2b00 cmp r3, #0
800160e: d001 beq.n 8001614 <MX_TIM5_Init+0x8c>
{
Error_Handler();
8001610: f001 f808 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
8001614: bf00 nop
8001616: 3720 adds r7, #32
8001618: 46bd mov sp, r7
800161a: bd80 pop {r7, pc}
800161c: 2000894c .word 0x2000894c
8001620: 40000c00 .word 0x40000c00
08001624 <MX_TIM8_Init>:
* @brief TIM8 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM8_Init(void)
{
8001624: b580 push {r7, lr}
8001626: b09a sub sp, #104 ; 0x68
8001628: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_Init 0 */
/* USER CODE END TIM8_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800162a: f107 0358 add.w r3, r7, #88 ; 0x58
800162e: 2200 movs r2, #0
8001630: 601a str r2, [r3, #0]
8001632: 605a str r2, [r3, #4]
8001634: 609a str r2, [r3, #8]
8001636: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001638: f107 034c add.w r3, r7, #76 ; 0x4c
800163c: 2200 movs r2, #0
800163e: 601a str r2, [r3, #0]
8001640: 605a str r2, [r3, #4]
8001642: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8001644: f107 0330 add.w r3, r7, #48 ; 0x30
8001648: 2200 movs r2, #0
800164a: 601a str r2, [r3, #0]
800164c: 605a str r2, [r3, #4]
800164e: 609a str r2, [r3, #8]
8001650: 60da str r2, [r3, #12]
8001652: 611a str r2, [r3, #16]
8001654: 615a str r2, [r3, #20]
8001656: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8001658: 1d3b adds r3, r7, #4
800165a: 222c movs r2, #44 ; 0x2c
800165c: 2100 movs r1, #0
800165e: 4618 mov r0, r3
8001660: f019 fcd0 bl 801b004 <memset>
/* USER CODE BEGIN TIM8_Init 1 */
/* USER CODE END TIM8_Init 1 */
htim8.Instance = TIM8;
8001664: 4b42 ldr r3, [pc, #264] ; (8001770 <MX_TIM8_Init+0x14c>)
8001666: 4a43 ldr r2, [pc, #268] ; (8001774 <MX_TIM8_Init+0x150>)
8001668: 601a str r2, [r3, #0]
htim8.Init.Prescaler = 0;
800166a: 4b41 ldr r3, [pc, #260] ; (8001770 <MX_TIM8_Init+0x14c>)
800166c: 2200 movs r2, #0
800166e: 605a str r2, [r3, #4]
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
8001670: 4b3f ldr r3, [pc, #252] ; (8001770 <MX_TIM8_Init+0x14c>)
8001672: 2200 movs r2, #0
8001674: 609a str r2, [r3, #8]
htim8.Init.Period = 65535;
8001676: 4b3e ldr r3, [pc, #248] ; (8001770 <MX_TIM8_Init+0x14c>)
8001678: f64f 72ff movw r2, #65535 ; 0xffff
800167c: 60da str r2, [r3, #12]
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800167e: 4b3c ldr r3, [pc, #240] ; (8001770 <MX_TIM8_Init+0x14c>)
8001680: 2200 movs r2, #0
8001682: 611a str r2, [r3, #16]
htim8.Init.RepetitionCounter = 0;
8001684: 4b3a ldr r3, [pc, #232] ; (8001770 <MX_TIM8_Init+0x14c>)
8001686: 2200 movs r2, #0
8001688: 615a str r2, [r3, #20]
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800168a: 4b39 ldr r3, [pc, #228] ; (8001770 <MX_TIM8_Init+0x14c>)
800168c: 2200 movs r2, #0
800168e: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
8001690: 4837 ldr r0, [pc, #220] ; (8001770 <MX_TIM8_Init+0x14c>)
8001692: f008 faa8 bl 8009be6 <HAL_TIM_Base_Init>
8001696: 4603 mov r3, r0
8001698: 2b00 cmp r3, #0
800169a: d001 beq.n 80016a0 <MX_TIM8_Init+0x7c>
{
Error_Handler();
800169c: f000 ffc2 bl 8002624 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80016a0: f44f 5380 mov.w r3, #4096 ; 0x1000
80016a4: 65bb str r3, [r7, #88] ; 0x58
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
80016a6: f107 0358 add.w r3, r7, #88 ; 0x58
80016aa: 4619 mov r1, r3
80016ac: 4830 ldr r0, [pc, #192] ; (8001770 <MX_TIM8_Init+0x14c>)
80016ae: f008 fd5b bl 800a168 <HAL_TIM_ConfigClockSource>
80016b2: 4603 mov r3, r0
80016b4: 2b00 cmp r3, #0
80016b6: d001 beq.n 80016bc <MX_TIM8_Init+0x98>
{
Error_Handler();
80016b8: f000 ffb4 bl 8002624 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
80016bc: 482c ldr r0, [pc, #176] ; (8001770 <MX_TIM8_Init+0x14c>)
80016be: f008 fae7 bl 8009c90 <HAL_TIM_PWM_Init>
80016c2: 4603 mov r3, r0
80016c4: 2b00 cmp r3, #0
80016c6: d001 beq.n 80016cc <MX_TIM8_Init+0xa8>
{
Error_Handler();
80016c8: f000 ffac bl 8002624 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80016cc: 2300 movs r3, #0
80016ce: 64fb str r3, [r7, #76] ; 0x4c
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
80016d0: 2300 movs r3, #0
80016d2: 653b str r3, [r7, #80] ; 0x50
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80016d4: 2300 movs r3, #0
80016d6: 657b str r3, [r7, #84] ; 0x54
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
80016d8: f107 034c add.w r3, r7, #76 ; 0x4c
80016dc: 4619 mov r1, r3
80016de: 4824 ldr r0, [pc, #144] ; (8001770 <MX_TIM8_Init+0x14c>)
80016e0: f009 fa86 bl 800abf0 <HAL_TIMEx_MasterConfigSynchronization>
80016e4: 4603 mov r3, r0
80016e6: 2b00 cmp r3, #0
80016e8: d001 beq.n 80016ee <MX_TIM8_Init+0xca>
{
Error_Handler();
80016ea: f000 ff9b bl 8002624 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80016ee: 2360 movs r3, #96 ; 0x60
80016f0: 633b str r3, [r7, #48] ; 0x30
sConfigOC.Pulse = 0;
80016f2: 2300 movs r3, #0
80016f4: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80016f6: 2300 movs r3, #0
80016f8: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80016fa: 2300 movs r3, #0
80016fc: 643b str r3, [r7, #64] ; 0x40
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80016fe: 2300 movs r3, #0
8001700: 647b str r3, [r7, #68] ; 0x44
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8001702: 2300 movs r3, #0
8001704: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8001706: f107 0330 add.w r3, r7, #48 ; 0x30
800170a: 220c movs r2, #12
800170c: 4619 mov r1, r3
800170e: 4818 ldr r0, [pc, #96] ; (8001770 <MX_TIM8_Init+0x14c>)
8001710: f008 fc12 bl 8009f38 <HAL_TIM_PWM_ConfigChannel>
8001714: 4603 mov r3, r0
8001716: 2b00 cmp r3, #0
8001718: d001 beq.n 800171e <MX_TIM8_Init+0xfa>
{
Error_Handler();
800171a: f000 ff83 bl 8002624 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800171e: 2300 movs r3, #0
8001720: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8001722: 2300 movs r3, #0
8001724: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8001726: 2300 movs r3, #0
8001728: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
800172a: 2300 movs r3, #0
800172c: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800172e: 2300 movs r3, #0
8001730: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001732: f44f 5300 mov.w r3, #8192 ; 0x2000
8001736: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.BreakFilter = 0;
8001738: 2300 movs r3, #0
800173a: 61fb str r3, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
800173c: 2300 movs r3, #0
800173e: 623b str r3, [r7, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8001740: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8001744: 627b str r3, [r7, #36] ; 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
8001746: 2300 movs r3, #0
8001748: 62bb str r3, [r7, #40] ; 0x28
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800174a: 2300 movs r3, #0
800174c: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
800174e: 1d3b adds r3, r7, #4
8001750: 4619 mov r1, r3
8001752: 4807 ldr r0, [pc, #28] ; (8001770 <MX_TIM8_Init+0x14c>)
8001754: f009 fada bl 800ad0c <HAL_TIMEx_ConfigBreakDeadTime>
8001758: 4603 mov r3, r0
800175a: 2b00 cmp r3, #0
800175c: d001 beq.n 8001762 <MX_TIM8_Init+0x13e>
{
Error_Handler();
800175e: f000 ff61 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN TIM8_Init 2 */
/* USER CODE END TIM8_Init 2 */
HAL_TIM_MspPostInit(&htim8);
8001762: 4803 ldr r0, [pc, #12] ; (8001770 <MX_TIM8_Init+0x14c>)
8001764: f002 fe82 bl 800446c <HAL_TIM_MspPostInit>
}
8001768: bf00 nop
800176a: 3768 adds r7, #104 ; 0x68
800176c: 46bd mov sp, r7
800176e: bd80 pop {r7, pc}
8001770: 200088e0 .word 0x200088e0
8001774: 40010400 .word 0x40010400
08001778 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8001778: b580 push {r7, lr}
800177a: b088 sub sp, #32
800177c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
800177e: 1d3b adds r3, r7, #4
8001780: 2200 movs r2, #0
8001782: 601a str r2, [r3, #0]
8001784: 605a str r2, [r3, #4]
8001786: 609a str r2, [r3, #8]
8001788: 60da str r2, [r3, #12]
800178a: 611a str r2, [r3, #16]
800178c: 615a str r2, [r3, #20]
800178e: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8001790: 4b1e ldr r3, [pc, #120] ; (800180c <MX_FMC_Init+0x94>)
8001792: 4a1f ldr r2, [pc, #124] ; (8001810 <MX_FMC_Init+0x98>)
8001794: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
8001796: 4b1d ldr r3, [pc, #116] ; (800180c <MX_FMC_Init+0x94>)
8001798: 2200 movs r2, #0
800179a: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
800179c: 4b1b ldr r3, [pc, #108] ; (800180c <MX_FMC_Init+0x94>)
800179e: 2200 movs r2, #0
80017a0: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
80017a2: 4b1a ldr r3, [pc, #104] ; (800180c <MX_FMC_Init+0x94>)
80017a4: 2204 movs r2, #4
80017a6: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
80017a8: 4b18 ldr r3, [pc, #96] ; (800180c <MX_FMC_Init+0x94>)
80017aa: 2210 movs r2, #16
80017ac: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
80017ae: 4b17 ldr r3, [pc, #92] ; (800180c <MX_FMC_Init+0x94>)
80017b0: 2240 movs r2, #64 ; 0x40
80017b2: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
80017b4: 4b15 ldr r3, [pc, #84] ; (800180c <MX_FMC_Init+0x94>)
80017b6: 2280 movs r2, #128 ; 0x80
80017b8: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
80017ba: 4b14 ldr r3, [pc, #80] ; (800180c <MX_FMC_Init+0x94>)
80017bc: 2200 movs r2, #0
80017be: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
80017c0: 4b12 ldr r3, [pc, #72] ; (800180c <MX_FMC_Init+0x94>)
80017c2: 2200 movs r2, #0
80017c4: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
80017c6: 4b11 ldr r3, [pc, #68] ; (800180c <MX_FMC_Init+0x94>)
80017c8: 2200 movs r2, #0
80017ca: 625a str r2, [r3, #36] ; 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
80017cc: 4b0f ldr r3, [pc, #60] ; (800180c <MX_FMC_Init+0x94>)
80017ce: 2200 movs r2, #0
80017d0: 629a str r2, [r3, #40] ; 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 16;
80017d2: 2310 movs r3, #16
80017d4: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 16;
80017d6: 2310 movs r3, #16
80017d8: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 16;
80017da: 2310 movs r3, #16
80017dc: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 16;
80017de: 2310 movs r3, #16
80017e0: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 16;
80017e2: 2310 movs r3, #16
80017e4: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 16;
80017e6: 2310 movs r3, #16
80017e8: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 16;
80017ea: 2310 movs r3, #16
80017ec: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
80017ee: 1d3b adds r3, r7, #4
80017f0: 4619 mov r1, r3
80017f2: 4806 ldr r0, [pc, #24] ; (800180c <MX_FMC_Init+0x94>)
80017f4: f008 f8e6 bl 80099c4 <HAL_SDRAM_Init>
80017f8: 4603 mov r3, r0
80017fa: 2b00 cmp r3, #0
80017fc: d001 beq.n 8001802 <MX_FMC_Init+0x8a>
{
Error_Handler( );
80017fe: f000 ff11 bl 8002624 <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8001802: bf00 nop
8001804: 3720 adds r7, #32
8001806: 46bd mov sp, r7
8001808: bd80 pop {r7, pc}
800180a: bf00 nop
800180c: 20008bfc .word 0x20008bfc
8001810: a0000140 .word 0xa0000140
08001814 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001814: b580 push {r7, lr}
8001816: b090 sub sp, #64 ; 0x40
8001818: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800181a: f107 032c add.w r3, r7, #44 ; 0x2c
800181e: 2200 movs r2, #0
8001820: 601a str r2, [r3, #0]
8001822: 605a str r2, [r3, #4]
8001824: 609a str r2, [r3, #8]
8001826: 60da str r2, [r3, #12]
8001828: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
800182a: 4baf ldr r3, [pc, #700] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800182c: 6b1b ldr r3, [r3, #48] ; 0x30
800182e: 4aae ldr r2, [pc, #696] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001830: f043 0310 orr.w r3, r3, #16
8001834: 6313 str r3, [r2, #48] ; 0x30
8001836: 4bac ldr r3, [pc, #688] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001838: 6b1b ldr r3, [r3, #48] ; 0x30
800183a: f003 0310 and.w r3, r3, #16
800183e: 62bb str r3, [r7, #40] ; 0x28
8001840: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_GPIOG_CLK_ENABLE();
8001842: 4ba9 ldr r3, [pc, #676] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001844: 6b1b ldr r3, [r3, #48] ; 0x30
8001846: 4aa8 ldr r2, [pc, #672] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001848: f043 0340 orr.w r3, r3, #64 ; 0x40
800184c: 6313 str r3, [r2, #48] ; 0x30
800184e: 4ba6 ldr r3, [pc, #664] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001850: 6b1b ldr r3, [r3, #48] ; 0x30
8001852: f003 0340 and.w r3, r3, #64 ; 0x40
8001856: 627b str r3, [r7, #36] ; 0x24
8001858: 6a7b ldr r3, [r7, #36] ; 0x24
__HAL_RCC_GPIOB_CLK_ENABLE();
800185a: 4ba3 ldr r3, [pc, #652] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800185c: 6b1b ldr r3, [r3, #48] ; 0x30
800185e: 4aa2 ldr r2, [pc, #648] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001860: f043 0302 orr.w r3, r3, #2
8001864: 6313 str r3, [r2, #48] ; 0x30
8001866: 4ba0 ldr r3, [pc, #640] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001868: 6b1b ldr r3, [r3, #48] ; 0x30
800186a: f003 0302 and.w r3, r3, #2
800186e: 623b str r3, [r7, #32]
8001870: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001872: 4b9d ldr r3, [pc, #628] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001874: 6b1b ldr r3, [r3, #48] ; 0x30
8001876: 4a9c ldr r2, [pc, #624] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001878: f043 0301 orr.w r3, r3, #1
800187c: 6313 str r3, [r2, #48] ; 0x30
800187e: 4b9a ldr r3, [pc, #616] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001880: 6b1b ldr r3, [r3, #48] ; 0x30
8001882: f003 0301 and.w r3, r3, #1
8001886: 61fb str r3, [r7, #28]
8001888: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
800188a: 4b97 ldr r3, [pc, #604] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800188c: 6b1b ldr r3, [r3, #48] ; 0x30
800188e: 4a96 ldr r2, [pc, #600] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001890: f443 7300 orr.w r3, r3, #512 ; 0x200
8001894: 6313 str r3, [r2, #48] ; 0x30
8001896: 4b94 ldr r3, [pc, #592] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001898: 6b1b ldr r3, [r3, #48] ; 0x30
800189a: f403 7300 and.w r3, r3, #512 ; 0x200
800189e: 61bb str r3, [r7, #24]
80018a0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
80018a2: 4b91 ldr r3, [pc, #580] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018a4: 6b1b ldr r3, [r3, #48] ; 0x30
80018a6: 4a90 ldr r2, [pc, #576] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018a8: f043 0308 orr.w r3, r3, #8
80018ac: 6313 str r3, [r2, #48] ; 0x30
80018ae: 4b8e ldr r3, [pc, #568] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018b0: 6b1b ldr r3, [r3, #48] ; 0x30
80018b2: f003 0308 and.w r3, r3, #8
80018b6: 617b str r3, [r7, #20]
80018b8: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOI_CLK_ENABLE();
80018ba: 4b8b ldr r3, [pc, #556] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018bc: 6b1b ldr r3, [r3, #48] ; 0x30
80018be: 4a8a ldr r2, [pc, #552] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018c0: f443 7380 orr.w r3, r3, #256 ; 0x100
80018c4: 6313 str r3, [r2, #48] ; 0x30
80018c6: 4b88 ldr r3, [pc, #544] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018c8: 6b1b ldr r3, [r3, #48] ; 0x30
80018ca: f403 7380 and.w r3, r3, #256 ; 0x100
80018ce: 613b str r3, [r7, #16]
80018d0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOK_CLK_ENABLE();
80018d2: 4b85 ldr r3, [pc, #532] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018d4: 6b1b ldr r3, [r3, #48] ; 0x30
80018d6: 4a84 ldr r2, [pc, #528] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018d8: f443 6380 orr.w r3, r3, #1024 ; 0x400
80018dc: 6313 str r3, [r2, #48] ; 0x30
80018de: 4b82 ldr r3, [pc, #520] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018e0: 6b1b ldr r3, [r3, #48] ; 0x30
80018e2: f403 6380 and.w r3, r3, #1024 ; 0x400
80018e6: 60fb str r3, [r7, #12]
80018e8: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
80018ea: 4b7f ldr r3, [pc, #508] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018ec: 6b1b ldr r3, [r3, #48] ; 0x30
80018ee: 4a7e ldr r2, [pc, #504] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018f0: f043 0304 orr.w r3, r3, #4
80018f4: 6313 str r3, [r2, #48] ; 0x30
80018f6: 4b7c ldr r3, [pc, #496] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018f8: 6b1b ldr r3, [r3, #48] ; 0x30
80018fa: f003 0304 and.w r3, r3, #4
80018fe: 60bb str r3, [r7, #8]
8001900: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOF_CLK_ENABLE();
8001902: 4b79 ldr r3, [pc, #484] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001904: 6b1b ldr r3, [r3, #48] ; 0x30
8001906: 4a78 ldr r2, [pc, #480] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001908: f043 0320 orr.w r3, r3, #32
800190c: 6313 str r3, [r2, #48] ; 0x30
800190e: 4b76 ldr r3, [pc, #472] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001910: 6b1b ldr r3, [r3, #48] ; 0x30
8001912: f003 0320 and.w r3, r3, #32
8001916: 607b str r3, [r7, #4]
8001918: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOH_CLK_ENABLE();
800191a: 4b73 ldr r3, [pc, #460] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800191c: 6b1b ldr r3, [r3, #48] ; 0x30
800191e: 4a72 ldr r2, [pc, #456] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001920: f043 0380 orr.w r3, r3, #128 ; 0x80
8001924: 6313 str r3, [r2, #48] ; 0x30
8001926: 4b70 ldr r3, [pc, #448] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001928: 6b1b ldr r3, [r3, #48] ; 0x30
800192a: f003 0380 and.w r3, r3, #128 ; 0x80
800192e: 603b str r3, [r7, #0]
8001930: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET);
8001932: 2200 movs r2, #0
8001934: 2160 movs r1, #96 ; 0x60
8001936: 486d ldr r0, [pc, #436] ; (8001aec <MX_GPIO_Init+0x2d8>)
8001938: f005 fe48 bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET);
800193c: 2201 movs r2, #1
800193e: 2120 movs r1, #32
8001940: 486b ldr r0, [pc, #428] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001942: f005 fe43 bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET);
8001946: 2200 movs r2, #0
8001948: 2108 movs r1, #8
800194a: 4869 ldr r0, [pc, #420] ; (8001af0 <MX_GPIO_Init+0x2dc>)
800194c: f005 fe3e bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
8001950: 2200 movs r2, #0
8001952: 2108 movs r1, #8
8001954: 4867 ldr r0, [pc, #412] ; (8001af4 <MX_GPIO_Init+0x2e0>)
8001956: f005 fe39 bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET);
800195a: 2201 movs r2, #1
800195c: 2108 movs r1, #8
800195e: 4866 ldr r0, [pc, #408] ; (8001af8 <MX_GPIO_Init+0x2e4>)
8001960: f005 fe34 bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET);
8001964: 2201 movs r2, #1
8001966: f44f 5180 mov.w r1, #4096 ; 0x1000
800196a: 4862 ldr r0, [pc, #392] ; (8001af4 <MX_GPIO_Init+0x2e0>)
800196c: f005 fe2e bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001970: 2200 movs r2, #0
8001972: f645 6140 movw r1, #24128 ; 0x5e40
8001976: 4861 ldr r0, [pc, #388] ; (8001afc <MX_GPIO_Init+0x2e8>)
8001978: f005 fe28 bl 80075cc <HAL_GPIO_WritePin>
|LED2_Pin|LED18_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET);
800197c: 2200 movs r2, #0
800197e: 2108 movs r1, #8
8001980: 485f ldr r0, [pc, #380] ; (8001b00 <MX_GPIO_Init+0x2ec>)
8001982: f005 fe23 bl 80075cc <HAL_GPIO_WritePin>
/*Configure GPIO pin : PE3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001986: 2308 movs r3, #8
8001988: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800198a: 2300 movs r3, #0
800198c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
800198e: 2300 movs r3, #0
8001990: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001992: f107 032c add.w r3, r7, #44 ; 0x2c
8001996: 4619 mov r1, r3
8001998: 4854 ldr r0, [pc, #336] ; (8001aec <MX_GPIO_Init+0x2d8>)
800199a: f005 fc6d bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : ARDUINO_SCL_D15_Pin ARDUINO_SDA_D14_Pin */
GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin;
800199e: f44f 7340 mov.w r3, #768 ; 0x300
80019a2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80019a4: 2312 movs r3, #18
80019a6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
80019a8: 2301 movs r3, #1
80019aa: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80019ac: 2300 movs r3, #0
80019ae: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80019b0: 2304 movs r3, #4
80019b2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019b4: f107 032c add.w r3, r7, #44 ; 0x2c
80019b8: 4619 mov r1, r3
80019ba: 4852 ldr r0, [pc, #328] ; (8001b04 <MX_GPIO_Init+0x2f0>)
80019bc: f005 fc5c bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin
ULPI_D1_Pin ULPI_D4_Pin */
GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin
80019c0: f643 0323 movw r3, #14371 ; 0x3823
80019c4: 62fb str r3, [r7, #44] ; 0x2c
|ULPI_D1_Pin|ULPI_D4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019c6: 2302 movs r3, #2
80019c8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019ca: 2300 movs r3, #0
80019cc: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019ce: 2303 movs r3, #3
80019d0: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
80019d2: 230a movs r3, #10
80019d4: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019d6: f107 032c add.w r3, r7, #44 ; 0x2c
80019da: 4619 mov r1, r3
80019dc: 4849 ldr r0, [pc, #292] ; (8001b04 <MX_GPIO_Init+0x2f0>)
80019de: f005 fc4b bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : BP2_Pin */
GPIO_InitStruct.Pin = BP2_Pin;
80019e2: f44f 4300 mov.w r3, #32768 ; 0x8000
80019e6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80019e8: 2300 movs r3, #0
80019ea: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019ec: 2300 movs r3, #0
80019ee: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(BP2_GPIO_Port, &GPIO_InitStruct);
80019f0: f107 032c add.w r3, r7, #44 ; 0x2c
80019f4: 4619 mov r1, r3
80019f6: 4844 ldr r0, [pc, #272] ; (8001b08 <MX_GPIO_Init+0x2f4>)
80019f8: f005 fc3e bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : LED14_Pin LED15_Pin */
GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin;
80019fc: 2360 movs r3, #96 ; 0x60
80019fe: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a00: 2301 movs r3, #1
8001a02: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a04: 2300 movs r3, #0
8001a06: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a08: 2300 movs r3, #0
8001a0a: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001a0c: f107 032c add.w r3, r7, #44 ; 0x2c
8001a10: 4619 mov r1, r3
8001a12: 4836 ldr r0, [pc, #216] ; (8001aec <MX_GPIO_Init+0x2d8>)
8001a14: f005 fc30 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_RX_Pin */
GPIO_InitStruct.Pin = VCP_RX_Pin;
8001a18: 2380 movs r3, #128 ; 0x80
8001a1a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a1c: 2302 movs r3, #2
8001a1e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a20: 2300 movs r3, #0
8001a22: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a24: 2300 movs r3, #0
8001a26: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001a28: 2307 movs r3, #7
8001a2a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
8001a2c: f107 032c add.w r3, r7, #44 ; 0x2c
8001a30: 4619 mov r1, r3
8001a32: 4834 ldr r0, [pc, #208] ; (8001b04 <MX_GPIO_Init+0x2f0>)
8001a34: f005 fc20 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_VBUS_Pin */
GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin;
8001a38: f44f 5380 mov.w r3, #4096 ; 0x1000
8001a3c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001a3e: 2300 movs r3, #0
8001a40: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a42: 2300 movs r3, #0
8001a44: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
8001a46: f107 032c add.w r3, r7, #44 ; 0x2c
8001a4a: 4619 mov r1, r3
8001a4c: 482f ldr r0, [pc, #188] ; (8001b0c <MX_GPIO_Init+0x2f8>)
8001a4e: f005 fc13 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : Audio_INT_Pin */
GPIO_InitStruct.Pin = Audio_INT_Pin;
8001a52: 2340 movs r3, #64 ; 0x40
8001a54: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001a56: 4b2e ldr r3, [pc, #184] ; (8001b10 <MX_GPIO_Init+0x2fc>)
8001a58: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a5a: 2300 movs r3, #0
8001a5c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct);
8001a5e: f107 032c add.w r3, r7, #44 ; 0x2c
8001a62: 4619 mov r1, r3
8001a64: 4822 ldr r0, [pc, #136] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001a66: f005 fc07 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */
GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin;
8001a6a: 2328 movs r3, #40 ; 0x28
8001a6c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a6e: 2301 movs r3, #1
8001a70: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a72: 2300 movs r3, #0
8001a74: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a76: 2300 movs r3, #0
8001a78: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001a7a: f107 032c add.w r3, r7, #44 ; 0x2c
8001a7e: 4619 mov r1, r3
8001a80: 481b ldr r0, [pc, #108] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001a82: f005 fbf9 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */
GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin;
8001a86: f241 0308 movw r3, #4104 ; 0x1008
8001a8a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a8c: 2301 movs r3, #1
8001a8e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a90: 2300 movs r3, #0
8001a92: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a94: 2300 movs r3, #0
8001a96: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001a98: f107 032c add.w r3, r7, #44 ; 0x2c
8001a9c: 4619 mov r1, r3
8001a9e: 4815 ldr r0, [pc, #84] ; (8001af4 <MX_GPIO_Init+0x2e0>)
8001aa0: f005 fbea bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : uSD_Detect_Pin */
GPIO_InitStruct.Pin = uSD_Detect_Pin;
8001aa4: f44f 5300 mov.w r3, #8192 ; 0x2000
8001aa8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001aaa: 2300 movs r3, #0
8001aac: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001aae: 2300 movs r3, #0
8001ab0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
8001ab2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ab6: 4619 mov r1, r3
8001ab8: 4816 ldr r0, [pc, #88] ; (8001b14 <MX_GPIO_Init+0x300>)
8001aba: f005 fbdd bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_CTRL_Pin */
GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
8001abe: 2308 movs r3, #8
8001ac0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001ac2: 2301 movs r3, #1
8001ac4: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ac6: 2300 movs r3, #0
8001ac8: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001aca: 2300 movs r3, #0
8001acc: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
8001ace: f107 032c add.w r3, r7, #44 ; 0x2c
8001ad2: 4619 mov r1, r3
8001ad4: 4808 ldr r0, [pc, #32] ; (8001af8 <MX_GPIO_Init+0x2e4>)
8001ad6: f005 fbcf bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OverCurrent_Pin */
GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin;
8001ada: 2310 movs r3, #16
8001adc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001ade: 2300 movs r3, #0
8001ae0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ae2: 2300 movs r3, #0
8001ae4: 637b str r3, [r7, #52] ; 0x34
8001ae6: e017 b.n 8001b18 <MX_GPIO_Init+0x304>
8001ae8: 40023800 .word 0x40023800
8001aec: 40021000 .word 0x40021000
8001af0: 40020c00 .word 0x40020c00
8001af4: 40022000 .word 0x40022000
8001af8: 40022800 .word 0x40022800
8001afc: 40021c00 .word 0x40021c00
8001b00: 40021800 .word 0x40021800
8001b04: 40020400 .word 0x40020400
8001b08: 40020000 .word 0x40020000
8001b0c: 40022400 .word 0x40022400
8001b10: 10120000 .word 0x10120000
8001b14: 40020800 .word 0x40020800
HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8001b18: f107 032c add.w r3, r7, #44 ; 0x2c
8001b1c: 4619 mov r1, r3
8001b1e: 486f ldr r0, [pc, #444] ; (8001cdc <MX_GPIO_Init+0x4c8>)
8001b20: f005 fbaa bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : TP3_Pin NC2_Pin */
GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin;
8001b24: f248 0304 movw r3, #32772 ; 0x8004
8001b28: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001b2a: 2300 movs r3, #0
8001b2c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b2e: 2300 movs r3, #0
8001b30: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001b32: f107 032c add.w r3, r7, #44 ; 0x2c
8001b36: 4619 mov r1, r3
8001b38: 4869 ldr r0, [pc, #420] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001b3a: f005 fb9d bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
LED2_Pin LED18_Pin */
GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001b3e: f645 6340 movw r3, #24128 ; 0x5e40
8001b42: 62fb str r3, [r7, #44] ; 0x2c
|LED2_Pin|LED18_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001b44: 2301 movs r3, #1
8001b46: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b48: 2300 movs r3, #0
8001b4a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b4c: 2300 movs r3, #0
8001b4e: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001b50: f107 032c add.w r3, r7, #44 ; 0x2c
8001b54: 4619 mov r1, r3
8001b56: 4862 ldr r0, [pc, #392] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001b58: f005 fb8e bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_TX_Pin */
GPIO_InitStruct.Pin = VCP_TX_Pin;
8001b5c: f44f 7300 mov.w r3, #512 ; 0x200
8001b60: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b62: 2302 movs r3, #2
8001b64: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b66: 2300 movs r3, #0
8001b68: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b6a: 2300 movs r3, #0
8001b6c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001b6e: 2307 movs r3, #7
8001b70: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
8001b72: f107 032c add.w r3, r7, #44 ; 0x2c
8001b76: 4619 mov r1, r3
8001b78: 485a ldr r0, [pc, #360] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001b7a: f005 fb7d bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : BP_interrupt1_Pin */
GPIO_InitStruct.Pin = BP_interrupt1_Pin;
8001b7e: f44f 6300 mov.w r3, #2048 ; 0x800
8001b82: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001b84: 4b58 ldr r3, [pc, #352] ; (8001ce8 <MX_GPIO_Init+0x4d4>)
8001b86: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b88: 2300 movs r3, #0
8001b8a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(BP_interrupt1_GPIO_Port, &GPIO_InitStruct);
8001b8c: f107 032c add.w r3, r7, #44 ; 0x2c
8001b90: 4619 mov r1, r3
8001b92: 4856 ldr r0, [pc, #344] ; (8001cec <MX_GPIO_Init+0x4d8>)
8001b94: f005 fb70 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : PB_Pin */
GPIO_InitStruct.Pin = PB_Pin;
8001b98: f44f 7380 mov.w r3, #256 ; 0x100
8001b9c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001b9e: 4b52 ldr r3, [pc, #328] ; (8001ce8 <MX_GPIO_Init+0x4d4>)
8001ba0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ba2: 2300 movs r3, #0
8001ba4: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(PB_GPIO_Port, &GPIO_InitStruct);
8001ba6: f107 032c add.w r3, r7, #44 ; 0x2c
8001baa: 4619 mov r1, r3
8001bac: 484d ldr r0, [pc, #308] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001bae: f005 fb63 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_INT_Pin */
GPIO_InitStruct.Pin = LCD_INT_Pin;
8001bb2: f44f 5300 mov.w r3, #8192 ; 0x2000
8001bb6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001bb8: 4b4d ldr r3, [pc, #308] ; (8001cf0 <MX_GPIO_Init+0x4dc>)
8001bba: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bbc: 2300 movs r3, #0
8001bbe: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
8001bc0: f107 032c add.w r3, r7, #44 ; 0x2c
8001bc4: 4619 mov r1, r3
8001bc6: 4849 ldr r0, [pc, #292] ; (8001cec <MX_GPIO_Init+0x4d8>)
8001bc8: f005 fb56 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : PC7 PC6 */
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
8001bcc: 23c0 movs r3, #192 ; 0xc0
8001bce: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bd0: 2302 movs r3, #2
8001bd2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bd4: 2300 movs r3, #0
8001bd6: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bd8: 2303 movs r3, #3
8001bda: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001bdc: 2308 movs r3, #8
8001bde: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001be0: f107 032c add.w r3, r7, #44 ; 0x2c
8001be4: 4619 mov r1, r3
8001be6: 4843 ldr r0, [pc, #268] ; (8001cf4 <MX_GPIO_Init+0x4e0>)
8001be8: f005 fb46 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : ULPI_NXT_Pin */
GPIO_InitStruct.Pin = ULPI_NXT_Pin;
8001bec: 2310 movs r3, #16
8001bee: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bf0: 2302 movs r3, #2
8001bf2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bf4: 2300 movs r3, #0
8001bf6: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bf8: 2303 movs r3, #3
8001bfa: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001bfc: 230a movs r3, #10
8001bfe: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct);
8001c00: f107 032c add.w r3, r7, #44 ; 0x2c
8001c04: 4619 mov r1, r3
8001c06: 4836 ldr r0, [pc, #216] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001c08: f005 fb36 bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */
GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin;
8001c0c: 2384 movs r3, #132 ; 0x84
8001c0e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001c10: 2300 movs r3, #0
8001c12: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c14: 2300 movs r3, #0
8001c16: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001c18: f107 032c add.w r3, r7, #44 ; 0x2c
8001c1c: 4619 mov r1, r3
8001c1e: 4836 ldr r0, [pc, #216] ; (8001cf8 <MX_GPIO_Init+0x4e4>)
8001c20: f005 fb2a bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : PF7 */
GPIO_InitStruct.Pin = GPIO_PIN_7;
8001c24: 2380 movs r3, #128 ; 0x80
8001c26: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c28: 2302 movs r3, #2
8001c2a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c2c: 2300 movs r3, #0
8001c2e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c30: 2303 movs r3, #3
8001c32: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
8001c34: 2308 movs r3, #8
8001c36: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8001c38: f107 032c add.w r3, r7, #44 ; 0x2c
8001c3c: 4619 mov r1, r3
8001c3e: 482f ldr r0, [pc, #188] ; (8001cfc <MX_GPIO_Init+0x4e8>)
8001c40: f005 fb1a bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */
GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin;
8001c44: 2305 movs r3, #5
8001c46: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c48: 2302 movs r3, #2
8001c4a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c4c: 2300 movs r3, #0
8001c4e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c50: 2303 movs r3, #3
8001c52: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001c54: 230a movs r3, #10
8001c56: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001c58: f107 032c add.w r3, r7, #44 ; 0x2c
8001c5c: 4619 mov r1, r3
8001c5e: 4825 ldr r0, [pc, #148] ; (8001cf4 <MX_GPIO_Init+0x4e0>)
8001c60: f005 fb0a bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pin : EXT_RST_Pin */
GPIO_InitStruct.Pin = EXT_RST_Pin;
8001c64: 2308 movs r3, #8
8001c66: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001c68: 2301 movs r3, #1
8001c6a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c6c: 2300 movs r3, #0
8001c6e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c70: 2300 movs r3, #0
8001c72: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct);
8001c74: f107 032c add.w r3, r7, #44 ; 0x2c
8001c78: 4619 mov r1, r3
8001c7a: 481f ldr r0, [pc, #124] ; (8001cf8 <MX_GPIO_Init+0x4e4>)
8001c7c: f005 fafc bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : LCD_SCL_Pin LCD_SDA_Pin */
GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin;
8001c80: f44f 73c0 mov.w r3, #384 ; 0x180
8001c84: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001c86: 2312 movs r3, #18
8001c88: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001c8a: 2301 movs r3, #1
8001c8c: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c8e: 2303 movs r3, #3
8001c90: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8001c92: 2304 movs r3, #4
8001c94: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001c96: f107 032c add.w r3, r7, #44 ; 0x2c
8001c9a: 4619 mov r1, r3
8001c9c: 4810 ldr r0, [pc, #64] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001c9e: f005 faeb bl 8007278 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */
GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin;
8001ca2: 2328 movs r3, #40 ; 0x28
8001ca4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001ca6: 2302 movs r3, #2
8001ca8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001caa: 2300 movs r3, #0
8001cac: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001cae: 2303 movs r3, #3
8001cb0: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001cb2: 230a movs r3, #10
8001cb4: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001cb6: f107 032c add.w r3, r7, #44 ; 0x2c
8001cba: 4619 mov r1, r3
8001cbc: 4809 ldr r0, [pc, #36] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001cbe: f005 fadb bl 8007278 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
8001cc2: 2200 movs r2, #0
8001cc4: 2105 movs r1, #5
8001cc6: 2017 movs r0, #23
8001cc8: f003 fb26 bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
8001ccc: 2017 movs r0, #23
8001cce: f003 fb3f bl 8005350 <HAL_NVIC_EnableIRQ>
}
8001cd2: bf00 nop
8001cd4: 3740 adds r7, #64 ; 0x40
8001cd6: 46bd mov sp, r7
8001cd8: bd80 pop {r7, pc}
8001cda: bf00 nop
8001cdc: 40020c00 .word 0x40020c00
8001ce0: 40021c00 .word 0x40021c00
8001ce4: 40020000 .word 0x40020000
8001ce8: 10110000 .word 0x10110000
8001cec: 40022000 .word 0x40022000
8001cf0: 10120000 .word 0x10120000
8001cf4: 40020800 .word 0x40020800
8001cf8: 40021800 .word 0x40021800
8001cfc: 40021400 .word 0x40021400
08001d00 <HAL_GPIO_EXTI_Callback>:
/* USER CODE BEGIN 4 */
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001d00: b580 push {r7, lr}
8001d02: b088 sub sp, #32
8001d04: af00 add r7, sp, #0
8001d06: 4603 mov r3, r0
8001d08: 80fb strh r3, [r7, #6]
/* Prevent unused argument(s) compilation warning */
BaseType_t pxHigherPriorityTaskWoken = pdTRUE;
8001d0a: 2301 movs r3, #1
8001d0c: 61fb str r3, [r7, #28]
// &pxHigherPriorityTaskWoken =
struct Missile missile = {joueur.x, joueur.y, 1, 0, 1, LCD_COLOR_LIGHTBLUE, 2, 1};
8001d0e: 4b13 ldr r3, [pc, #76] ; (8001d5c <HAL_GPIO_EXTI_Callback+0x5c>)
8001d10: 681b ldr r3, [r3, #0]
8001d12: b29b uxth r3, r3
8001d14: 81bb strh r3, [r7, #12]
8001d16: 4b11 ldr r3, [pc, #68] ; (8001d5c <HAL_GPIO_EXTI_Callback+0x5c>)
8001d18: 685b ldr r3, [r3, #4]
8001d1a: b29b uxth r3, r3
8001d1c: 81fb strh r3, [r7, #14]
8001d1e: 2301 movs r3, #1
8001d20: 743b strb r3, [r7, #16]
8001d22: 2300 movs r3, #0
8001d24: 747b strb r3, [r7, #17]
8001d26: 2301 movs r3, #1
8001d28: 74bb strb r3, [r7, #18]
8001d2a: 4b0d ldr r3, [pc, #52] ; (8001d60 <HAL_GPIO_EXTI_Callback+0x60>)
8001d2c: 617b str r3, [r7, #20]
8001d2e: 2302 movs r3, #2
8001d30: 763b strb r3, [r7, #24]
8001d32: 2301 movs r3, #1
8001d34: 767b strb r3, [r7, #25]
HAL_GPIO_TogglePin(LED13_GPIO_Port, LED13_Pin);
8001d36: f44f 4180 mov.w r1, #16384 ; 0x4000
8001d3a: 480a ldr r0, [pc, #40] ; (8001d64 <HAL_GPIO_EXTI_Callback+0x64>)
8001d3c: f005 fc5f bl 80075fe <HAL_GPIO_TogglePin>
xQueueSendFromISR(Queue_NHandle, &missile, &pxHigherPriorityTaskWoken);
8001d40: 4b09 ldr r3, [pc, #36] ; (8001d68 <HAL_GPIO_EXTI_Callback+0x68>)
8001d42: 6818 ldr r0, [r3, #0]
8001d44: f107 021c add.w r2, r7, #28
8001d48: f107 010c add.w r1, r7, #12
8001d4c: 2300 movs r3, #0
8001d4e: f00a fcab bl 800c6a8 <xQueueGenericSendFromISR>
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
8001d52: bf00 nop
8001d54: 3720 adds r7, #32
8001d56: 46bd mov sp, r7
8001d58: bd80 pop {r7, pc}
8001d5a: bf00 nop
8001d5c: 20000028 .word 0x20000028
8001d60: ff8080ff .word 0xff8080ff
8001d64: 40021c00 .word 0x40021c00
8001d68: 20008b04 .word 0x20008b04
08001d6c <f_GameMaster>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_GameMaster */
void f_GameMaster(void const * argument)
{
8001d6c: b580 push {r7, lr}
8001d6e: b086 sub sp, #24
8001d70: af00 add r7, sp, #0
8001d72: 6078 str r0, [r7, #4]
/* init code for LWIP */
MX_LWIP_Init();
8001d74: f009 f98c bl 800b090 <MX_LWIP_Init>
/* USER CODE BEGIN 5 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8001d78: 230a movs r3, #10
8001d7a: 617b str r3, [r7, #20]
// Si la variable end est à 1, le jeu s'arrete.
uint8_t end = 0;
8001d7c: 2300 movs r3, #0
8001d7e: 73fb strb r3, [r7, #15]
/* Infinite loop */
for (;;)
{
xQueueReceive(Queue_FHandle, &end, 0);
8001d80: 4b1b ldr r3, [pc, #108] ; (8001df0 <f_GameMaster+0x84>)
8001d82: 681b ldr r3, [r3, #0]
8001d84: f107 010f add.w r1, r7, #15
8001d88: 2200 movs r2, #0
8001d8a: 4618 mov r0, r3
8001d8c: f00a fdba bl 800c904 <xQueueReceive>
if (end == 1){
8001d90: 7bfb ldrb r3, [r7, #15]
8001d92: 2b01 cmp r3, #1
8001d94: d10e bne.n 8001db4 <f_GameMaster+0x48>
vTaskDelete(Block_EnemieHandle);
8001d96: 4b17 ldr r3, [pc, #92] ; (8001df4 <f_GameMaster+0x88>)
8001d98: 681b ldr r3, [r3, #0]
8001d9a: 4618 mov r0, r3
8001d9c: f00b faf2 bl 800d384 <vTaskDelete>
vTaskDelete(ProjectileHandle);
8001da0: 4b15 ldr r3, [pc, #84] ; (8001df8 <f_GameMaster+0x8c>)
8001da2: 681b ldr r3, [r3, #0]
8001da4: 4618 mov r0, r3
8001da6: f00b faed bl 800d384 <vTaskDelete>
vTaskDelete(Joueur_1Handle);
8001daa: 4b14 ldr r3, [pc, #80] ; (8001dfc <f_GameMaster+0x90>)
8001dac: 681b ldr r3, [r3, #0]
8001dae: 4618 mov r0, r3
8001db0: f00b fae8 bl 800d384 <vTaskDelete>
//TODO L'affichage de l'écran de fin et des scores
}
if (end == 0){
8001db4: 7bfb ldrb r3, [r7, #15]
8001db6: 2b00 cmp r3, #0
8001db8: d112 bne.n 8001de0 <f_GameMaster+0x74>
if (waves_left == 0){
8001dba: 4b11 ldr r3, [pc, #68] ; (8001e00 <f_GameMaster+0x94>)
8001dbc: 781b ldrb r3, [r3, #0]
8001dbe: 2b00 cmp r3, #0
8001dc0: d10e bne.n 8001de0 <f_GameMaster+0x74>
vTaskDelete(Block_EnemieHandle);
8001dc2: 4b0c ldr r3, [pc, #48] ; (8001df4 <f_GameMaster+0x88>)
8001dc4: 681b ldr r3, [r3, #0]
8001dc6: 4618 mov r0, r3
8001dc8: f00b fadc bl 800d384 <vTaskDelete>
vTaskDelete(ProjectileHandle);
8001dcc: 4b0a ldr r3, [pc, #40] ; (8001df8 <f_GameMaster+0x8c>)
8001dce: 681b ldr r3, [r3, #0]
8001dd0: 4618 mov r0, r3
8001dd2: f00b fad7 bl 800d384 <vTaskDelete>
vTaskDelete(Joueur_1Handle);
8001dd6: 4b09 ldr r3, [pc, #36] ; (8001dfc <f_GameMaster+0x90>)
8001dd8: 681b ldr r3, [r3, #0]
8001dda: 4618 mov r0, r3
8001ddc: f00b fad2 bl 800d384 <vTaskDelete>
}
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8001de0: f107 0310 add.w r3, r7, #16
8001de4: 6979 ldr r1, [r7, #20]
8001de6: 4618 mov r0, r3
8001de8: f00b fb5c bl 800d4a4 <vTaskDelayUntil>
xQueueReceive(Queue_FHandle, &end, 0);
8001dec: e7c8 b.n 8001d80 <f_GameMaster+0x14>
8001dee: bf00 nop
8001df0: 20008b08 .word 0x20008b08
8001df4: 20008c30 .word 0x20008c30
8001df8: 20008b20 .word 0x20008b20
8001dfc: 20008948 .word 0x20008948
8001e00: 20000048 .word 0x20000048
08001e04 <f_Joueur_1>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_Joueur_1 */
void f_Joueur_1(void const * argument)
{
8001e04: b580 push {r7, lr}
8001e06: b096 sub sp, #88 ; 0x58
8001e08: af00 add r7, sp, #0
8001e0a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN f_Joueur_1 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8001e0c: 230a movs r3, #10
8001e0e: 657b str r3, [r7, #84] ; 0x54
uint16_t Width = 20;
8001e10: 2314 movs r3, #20
8001e12: f8a7 3052 strh.w r3, [r7, #82] ; 0x52
uint16_t Height = 20;
8001e16: 2314 movs r3, #20
8001e18: f8a7 3050 strh.w r3, [r7, #80] ; 0x50
uint32_t joystick_h, joystick_v;
uint8_t stop = 1;
8001e1c: 2301 movs r3, #1
8001e1e: f887 303b strb.w r3, [r7, #59] ; 0x3b
struct Missile missile;
ADC_ChannelConfTypeDef sConfig3 = {0};
8001e22: f107 0318 add.w r3, r7, #24
8001e26: 2200 movs r2, #0
8001e28: 601a str r2, [r3, #0]
8001e2a: 605a str r2, [r3, #4]
8001e2c: 609a str r2, [r3, #8]
8001e2e: 60da str r2, [r3, #12]
sConfig3.Rank = ADC_REGULAR_RANK_1;
8001e30: 2301 movs r3, #1
8001e32: 61fb str r3, [r7, #28]
sConfig3.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001e34: 2300 movs r3, #0
8001e36: 623b str r3, [r7, #32]
sConfig3.Channel = ADC_CHANNEL_8;
8001e38: 2308 movs r3, #8
8001e3a: 61bb str r3, [r7, #24]
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8001e3c: f107 0318 add.w r3, r7, #24
8001e40: 4619 mov r1, r3
8001e42: 4872 ldr r0, [pc, #456] ; (800200c <f_Joueur_1+0x208>)
8001e44: f002 ff6c bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8001e48: 4870 ldr r0, [pc, #448] ; (800200c <f_Joueur_1+0x208>)
8001e4a: f002 fe17 bl 8004a7c <HAL_ADC_Start>
ADC_ChannelConfTypeDef sConfig1 = {0};
8001e4e: f107 0308 add.w r3, r7, #8
8001e52: 2200 movs r2, #0
8001e54: 601a str r2, [r3, #0]
8001e56: 605a str r2, [r3, #4]
8001e58: 609a str r2, [r3, #8]
8001e5a: 60da str r2, [r3, #12]
sConfig1.Rank = ADC_REGULAR_RANK_1;
8001e5c: 2301 movs r3, #1
8001e5e: 60fb str r3, [r7, #12]
sConfig1.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001e60: 2300 movs r3, #0
8001e62: 613b str r3, [r7, #16]
sConfig1.Channel = ADC_CHANNEL_0;
8001e64: 2300 movs r3, #0
8001e66: 60bb str r3, [r7, #8]
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
8001e68: f107 0308 add.w r3, r7, #8
8001e6c: 4619 mov r1, r3
8001e6e: 4868 ldr r0, [pc, #416] ; (8002010 <f_Joueur_1+0x20c>)
8001e70: f002 ff56 bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
8001e74: 4866 ldr r0, [pc, #408] ; (8002010 <f_Joueur_1+0x20c>)
8001e76: f002 fe01 bl 8004a7c <HAL_ADC_Start>
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
8001e7a: f000 fdeb bl 8002a54 <BSP_LCD_GetXSize>
8001e7e: 64f8 str r0, [r7, #76] ; 0x4c
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
8001e80: f000 fdfc bl 8002a7c <BSP_LCD_GetYSize>
8001e84: 64b8 str r0, [r7, #72] ; 0x48
/* Infinite loop */
for (;;)
{
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
8001e86: 4b63 ldr r3, [pc, #396] ; (8002014 <f_Joueur_1+0x210>)
8001e88: 681b ldr r3, [r3, #0]
8001e8a: 4618 mov r0, r3
8001e8c: f000 fe7a bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
8001e90: 4b61 ldr r3, [pc, #388] ; (8002018 <f_Joueur_1+0x214>)
8001e92: 681b ldr r3, [r3, #0]
8001e94: b298 uxth r0, r3
8001e96: 4b60 ldr r3, [pc, #384] ; (8002018 <f_Joueur_1+0x214>)
8001e98: 685b ldr r3, [r3, #4]
8001e9a: b299 uxth r1, r3
8001e9c: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001ea0: f8b7 2052 ldrh.w r2, [r7, #82] ; 0x52
8001ea4: f001 f928 bl 80030f8 <BSP_LCD_FillRect>
// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8001ea8: f107 0318 add.w r3, r7, #24
8001eac: 4619 mov r1, r3
8001eae: 4857 ldr r0, [pc, #348] ; (800200c <f_Joueur_1+0x208>)
8001eb0: f002 ff36 bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8001eb4: 4855 ldr r0, [pc, #340] ; (800200c <f_Joueur_1+0x208>)
8001eb6: f002 fde1 bl 8004a7c <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc3, 100) != HAL_OK);
8001eba: bf00 nop
8001ebc: 2164 movs r1, #100 ; 0x64
8001ebe: 4853 ldr r0, [pc, #332] ; (800200c <f_Joueur_1+0x208>)
8001ec0: f002 fe9c bl 8004bfc <HAL_ADC_PollForConversion>
8001ec4: 4603 mov r3, r0
8001ec6: 2b00 cmp r3, #0
8001ec8: d1f8 bne.n 8001ebc <f_Joueur_1+0xb8>
joystick_h = HAL_ADC_GetValue(&hadc3);
8001eca: 4850 ldr r0, [pc, #320] ; (800200c <f_Joueur_1+0x208>)
8001ecc: f002 ff1a bl 8004d04 <HAL_ADC_GetValue>
8001ed0: 6478 str r0, [r7, #68] ; 0x44
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
8001ed2: f107 0308 add.w r3, r7, #8
8001ed6: 4619 mov r1, r3
8001ed8: 484d ldr r0, [pc, #308] ; (8002010 <f_Joueur_1+0x20c>)
8001eda: f002 ff21 bl 8004d20 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
8001ede: 484c ldr r0, [pc, #304] ; (8002010 <f_Joueur_1+0x20c>)
8001ee0: f002 fdcc bl 8004a7c <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc1, 100) != HAL_OK);
8001ee4: bf00 nop
8001ee6: 2164 movs r1, #100 ; 0x64
8001ee8: 4849 ldr r0, [pc, #292] ; (8002010 <f_Joueur_1+0x20c>)
8001eea: f002 fe87 bl 8004bfc <HAL_ADC_PollForConversion>
8001eee: 4603 mov r3, r0
8001ef0: 2b00 cmp r3, #0
8001ef2: d1f8 bne.n 8001ee6 <f_Joueur_1+0xe2>
joystick_v = HAL_ADC_GetValue(&hadc1);
8001ef4: 4846 ldr r0, [pc, #280] ; (8002010 <f_Joueur_1+0x20c>)
8001ef6: f002 ff05 bl 8004d04 <HAL_ADC_GetValue>
8001efa: 6438 str r0, [r7, #64] ; 0x40
if ((joueur.y < LCD_WIDTH- Width - joueur.dy)&&(joystick_h < 1900)) joueur.y += joueur.dy;
8001efc: 4b46 ldr r3, [pc, #280] ; (8002018 <f_Joueur_1+0x214>)
8001efe: 685a ldr r2, [r3, #4]
8001f00: f8b7 3052 ldrh.w r3, [r7, #82] ; 0x52
8001f04: 6cb9 ldr r1, [r7, #72] ; 0x48
8001f06: 1acb subs r3, r1, r3
8001f08: 4943 ldr r1, [pc, #268] ; (8002018 <f_Joueur_1+0x214>)
8001f0a: 7a49 ldrb r1, [r1, #9]
8001f0c: 1a5b subs r3, r3, r1
8001f0e: 429a cmp r2, r3
8001f10: d20b bcs.n 8001f2a <f_Joueur_1+0x126>
8001f12: 6c7b ldr r3, [r7, #68] ; 0x44
8001f14: f240 726b movw r2, #1899 ; 0x76b
8001f18: 4293 cmp r3, r2
8001f1a: d806 bhi.n 8001f2a <f_Joueur_1+0x126>
8001f1c: 4b3e ldr r3, [pc, #248] ; (8002018 <f_Joueur_1+0x214>)
8001f1e: 685b ldr r3, [r3, #4]
8001f20: 4a3d ldr r2, [pc, #244] ; (8002018 <f_Joueur_1+0x214>)
8001f22: 7a52 ldrb r2, [r2, #9]
8001f24: 4413 add r3, r2
8001f26: 4a3c ldr r2, [pc, #240] ; (8002018 <f_Joueur_1+0x214>)
8001f28: 6053 str r3, [r2, #4]
if ((joueur.y > joueur.dy)&&(joystick_h > 2100)) joueur.y -= joueur.dy;
8001f2a: 4b3b ldr r3, [pc, #236] ; (8002018 <f_Joueur_1+0x214>)
8001f2c: 685b ldr r3, [r3, #4]
8001f2e: 4a3a ldr r2, [pc, #232] ; (8002018 <f_Joueur_1+0x214>)
8001f30: 7a52 ldrb r2, [r2, #9]
8001f32: 4293 cmp r3, r2
8001f34: d90b bls.n 8001f4e <f_Joueur_1+0x14a>
8001f36: 6c7b ldr r3, [r7, #68] ; 0x44
8001f38: f640 0234 movw r2, #2100 ; 0x834
8001f3c: 4293 cmp r3, r2
8001f3e: d906 bls.n 8001f4e <f_Joueur_1+0x14a>
8001f40: 4b35 ldr r3, [pc, #212] ; (8002018 <f_Joueur_1+0x214>)
8001f42: 685b ldr r3, [r3, #4]
8001f44: 4a34 ldr r2, [pc, #208] ; (8002018 <f_Joueur_1+0x214>)
8001f46: 7a52 ldrb r2, [r2, #9]
8001f48: 1a9b subs r3, r3, r2
8001f4a: 4a33 ldr r2, [pc, #204] ; (8002018 <f_Joueur_1+0x214>)
8001f4c: 6053 str r3, [r2, #4]
if ((joueur.x < LCD_HEIGHT - Height - joueur.dx)&&(joystick_v < 1900)) joueur.x += joueur.dx;
8001f4e: 4b32 ldr r3, [pc, #200] ; (8002018 <f_Joueur_1+0x214>)
8001f50: 681a ldr r2, [r3, #0]
8001f52: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001f56: 6cf9 ldr r1, [r7, #76] ; 0x4c
8001f58: 1acb subs r3, r1, r3
8001f5a: 492f ldr r1, [pc, #188] ; (8002018 <f_Joueur_1+0x214>)
8001f5c: 7a09 ldrb r1, [r1, #8]
8001f5e: 1a5b subs r3, r3, r1
8001f60: 429a cmp r2, r3
8001f62: d20b bcs.n 8001f7c <f_Joueur_1+0x178>
8001f64: 6c3b ldr r3, [r7, #64] ; 0x40
8001f66: f240 726b movw r2, #1899 ; 0x76b
8001f6a: 4293 cmp r3, r2
8001f6c: d806 bhi.n 8001f7c <f_Joueur_1+0x178>
8001f6e: 4b2a ldr r3, [pc, #168] ; (8002018 <f_Joueur_1+0x214>)
8001f70: 681b ldr r3, [r3, #0]
8001f72: 4a29 ldr r2, [pc, #164] ; (8002018 <f_Joueur_1+0x214>)
8001f74: 7a12 ldrb r2, [r2, #8]
8001f76: 4413 add r3, r2
8001f78: 4a27 ldr r2, [pc, #156] ; (8002018 <f_Joueur_1+0x214>)
8001f7a: 6013 str r3, [r2, #0]
if ((joueur.x > joueur.dx)&&(joystick_v > 2100)) joueur.x -= joueur.dx;
8001f7c: 4b26 ldr r3, [pc, #152] ; (8002018 <f_Joueur_1+0x214>)
8001f7e: 681b ldr r3, [r3, #0]
8001f80: 4a25 ldr r2, [pc, #148] ; (8002018 <f_Joueur_1+0x214>)
8001f82: 7a12 ldrb r2, [r2, #8]
8001f84: 4293 cmp r3, r2
8001f86: d90b bls.n 8001fa0 <f_Joueur_1+0x19c>
8001f88: 6c3b ldr r3, [r7, #64] ; 0x40
8001f8a: f640 0234 movw r2, #2100 ; 0x834
8001f8e: 4293 cmp r3, r2
8001f90: d906 bls.n 8001fa0 <f_Joueur_1+0x19c>
8001f92: 4b21 ldr r3, [pc, #132] ; (8002018 <f_Joueur_1+0x214>)
8001f94: 681b ldr r3, [r3, #0]
8001f96: 4a20 ldr r2, [pc, #128] ; (8002018 <f_Joueur_1+0x214>)
8001f98: 7a12 ldrb r2, [r2, #8]
8001f9a: 1a9b subs r3, r3, r2
8001f9c: 4a1e ldr r2, [pc, #120] ; (8002018 <f_Joueur_1+0x214>)
8001f9e: 6013 str r3, [r2, #0]
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8001fa0: 481e ldr r0, [pc, #120] ; (800201c <f_Joueur_1+0x218>)
8001fa2: f000 fdef bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
8001fa6: 4b1c ldr r3, [pc, #112] ; (8002018 <f_Joueur_1+0x214>)
8001fa8: 681b ldr r3, [r3, #0]
8001faa: b298 uxth r0, r3
8001fac: 4b1a ldr r3, [pc, #104] ; (8002018 <f_Joueur_1+0x214>)
8001fae: 685b ldr r3, [r3, #4]
8001fb0: b299 uxth r1, r3
8001fb2: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001fb6: f8b7 2052 ldrh.w r2, [r7, #82] ; 0x52
8001fba: f001 f89d bl 80030f8 <BSP_LCD_FillRect>
if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
8001fbe: 4b18 ldr r3, [pc, #96] ; (8002020 <f_Joueur_1+0x21c>)
8001fc0: 681b ldr r3, [r3, #0]
8001fc2: f107 0128 add.w r1, r7, #40 ; 0x28
8001fc6: 2200 movs r2, #0
8001fc8: 4618 mov r0, r3
8001fca: f00a fc9b bl 800c904 <xQueueReceive>
8001fce: 4603 mov r3, r0
8001fd0: 2b01 cmp r3, #1
8001fd2: d107 bne.n 8001fe4 <f_Joueur_1+0x1e0>
joueur.health = joueur.health - missile.damage;
8001fd4: 4b10 ldr r3, [pc, #64] ; (8002018 <f_Joueur_1+0x214>)
8001fd6: 7a9a ldrb r2, [r3, #10]
8001fd8: f897 3034 ldrb.w r3, [r7, #52] ; 0x34
8001fdc: 1ad3 subs r3, r2, r3
8001fde: b2da uxtb r2, r3
8001fe0: 4b0d ldr r3, [pc, #52] ; (8002018 <f_Joueur_1+0x214>)
8001fe2: 729a strb r2, [r3, #10]
// On envoie 1 si le joueur est mort et on envoie 0 si les enemis sont tous morts
if (joueur.health == 0)xQueueSend(Queue_FHandle,&stop,0);
8001fe4: 4b0c ldr r3, [pc, #48] ; (8002018 <f_Joueur_1+0x214>)
8001fe6: 7a9b ldrb r3, [r3, #10]
8001fe8: 2b00 cmp r3, #0
8001fea: d107 bne.n 8001ffc <f_Joueur_1+0x1f8>
8001fec: 4b0d ldr r3, [pc, #52] ; (8002024 <f_Joueur_1+0x220>)
8001fee: 6818 ldr r0, [r3, #0]
8001ff0: f107 013b add.w r1, r7, #59 ; 0x3b
8001ff4: 2300 movs r3, #0
8001ff6: 2200 movs r2, #0
8001ff8: f00a fa54 bl 800c4a4 <xQueueGenericSend>
// TODO La condition sur une entrée analogique pour envoyer un missile
// struct Missile missile = {joueur.x, joueur.y,joueur.missile.dx, joueur.missile.dy, 1, joueur.missile.color, joueur.missile.damage};
// xQueueSend(Queue_NHandle,&missile,0);
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8001ffc: f107 033c add.w r3, r7, #60 ; 0x3c
8002000: 6d79 ldr r1, [r7, #84] ; 0x54
8002002: 4618 mov r0, r3
8002004: f00b fa4e bl 800d4a4 <vTaskDelayUntil>
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
8002008: e73d b.n 8001e86 <f_Joueur_1+0x82>
800200a: bf00 nop
800200c: 20008abc .word 0x20008abc
8002010: 20008a74 .word 0x20008a74
8002014: 20000044 .word 0x20000044
8002018: 20000028 .word 0x20000028
800201c: ff0000ff .word 0xff0000ff
8002020: 20008920 .word 0x20008920
8002024: 20008b08 .word 0x20008b08
08002028 <f_block_enemie>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_block_enemie */
void f_block_enemie(void const * argument)
{
8002028: b580 push {r7, lr}
800202a: f5ad 7d7c sub.w sp, sp, #1008 ; 0x3f0
800202e: af00 add r7, sp, #0
8002030: 1d3b adds r3, r7, #4
8002032: 6018 str r0, [r3, #0]
/* USER CODE BEGIN f_block_enemie */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8002034: 230a movs r3, #10
8002036: f8c7 33e4 str.w r3, [r7, #996] ; 0x3e4
uint8_t number_monsters = 30;
800203a: 231e movs r3, #30
800203c: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
struct Monster list_monsters[30];
uint8_t end = 0;
8002040: f107 031f add.w r3, r7, #31
8002044: 2200 movs r2, #0
8002046: 701a strb r2, [r3, #0]
uint8_t deplacement = 1;
8002048: 2301 movs r3, #1
800204a: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
struct Missile missile = {0,0,0,0,0,0,0,0};
800204e: f107 030c add.w r3, r7, #12
8002052: 461a mov r2, r3
8002054: 2300 movs r3, #0
8002056: 6013 str r3, [r2, #0]
8002058: 6053 str r3, [r2, #4]
800205a: 6093 str r3, [r2, #8]
800205c: 60d3 str r3, [r2, #12]
/* Infinite loop */
for (;;)
{
xQueueReceive(Queue_EHandle, &missile, 0);
800205e: 4b52 ldr r3, [pc, #328] ; (80021a8 <f_block_enemie+0x180>)
8002060: 681b ldr r3, [r3, #0]
8002062: f107 010c add.w r1, r7, #12
8002066: 2200 movs r2, #0
8002068: 4618 mov r0, r3
800206a: f00a fc4b bl 800c904 <xQueueReceive>
if (number_monsters == 0){
800206e: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
8002072: 2b00 cmp r3, #0
8002074: d107 bne.n 8002086 <f_block_enemie+0x5e>
xQueueSend(Queue_FHandle, &end, 0);
8002076: 4b4d ldr r3, [pc, #308] ; (80021ac <f_block_enemie+0x184>)
8002078: 6818 ldr r0, [r3, #0]
800207a: f107 011f add.w r1, r7, #31
800207e: 2300 movs r3, #0
8002080: 2200 movs r2, #0
8002082: f00a fa0f bl 800c4a4 <xQueueGenericSend>
}
for (int i=0;i< number_monsters;i++){
8002086: 2300 movs r3, #0
8002088: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
800208c: e07a b.n 8002184 <f_block_enemie+0x15c>
if (list_monsters[i].health > 0 ){
800208e: f107 0220 add.w r2, r7, #32
8002092: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
8002096: 015b lsls r3, r3, #5
8002098: 4413 add r3, r2
800209a: 331d adds r3, #29
800209c: 781b ldrb r3, [r3, #0]
800209e: 2b00 cmp r3, #0
80020a0: d06b beq.n 800217a <f_block_enemie+0x152>
if ((missile.x == list_monsters[i].x)&&(missile.y == list_monsters[i].y))
80020a2: f107 030c add.w r3, r7, #12
80020a6: 881b ldrh r3, [r3, #0]
80020a8: 4619 mov r1, r3
80020aa: f107 0220 add.w r2, r7, #32
80020ae: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020b2: 015b lsls r3, r3, #5
80020b4: 4413 add r3, r2
80020b6: 681b ldr r3, [r3, #0]
80020b8: 4299 cmp r1, r3
80020ba: d133 bne.n 8002124 <f_block_enemie+0xfc>
80020bc: f107 030c add.w r3, r7, #12
80020c0: 885b ldrh r3, [r3, #2]
80020c2: 4619 mov r1, r3
80020c4: f107 0220 add.w r2, r7, #32
80020c8: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020cc: 015b lsls r3, r3, #5
80020ce: 4413 add r3, r2
80020d0: 3304 adds r3, #4
80020d2: 681b ldr r3, [r3, #0]
80020d4: 4299 cmp r1, r3
80020d6: d125 bne.n 8002124 <f_block_enemie+0xfc>
{
list_monsters[i].health = list_monsters[i].health -1;
80020d8: f107 0220 add.w r2, r7, #32
80020dc: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020e0: 015b lsls r3, r3, #5
80020e2: 4413 add r3, r2
80020e4: 331d adds r3, #29
80020e6: 781b ldrb r3, [r3, #0]
80020e8: 3b01 subs r3, #1
80020ea: b2d9 uxtb r1, r3
80020ec: f107 0220 add.w r2, r7, #32
80020f0: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020f4: 015b lsls r3, r3, #5
80020f6: 4413 add r3, r2
80020f8: 331d adds r3, #29
80020fa: 460a mov r2, r1
80020fc: 701a strb r2, [r3, #0]
// Est ce que cette ligne va marcher sachant que je transmets l'adresse dans la queue ?
missile.valide = 0;
80020fe: f107 030c add.w r3, r7, #12
8002102: 2200 movs r2, #0
8002104: 735a strb r2, [r3, #13]
if (list_monsters[i].health == 0){
8002106: f107 0220 add.w r2, r7, #32
800210a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800210e: 015b lsls r3, r3, #5
8002110: 4413 add r3, r2
8002112: 331d adds r3, #29
8002114: 781b ldrb r3, [r3, #0]
8002116: 2b00 cmp r3, #0
8002118: d104 bne.n 8002124 <f_block_enemie+0xfc>
//TODO explosion du plaisir ?
number_monsters = number_monsters -1;
800211a: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
800211e: 3b01 subs r3, #1
8002120: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
}
}
BSP_LCD_DrawBitmap(list_monsters[i].x, list_monsters[i].y, &list_monsters[i].pbmp);
8002124: f107 0220 add.w r2, r7, #32
8002128: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800212c: 015b lsls r3, r3, #5
800212e: 4413 add r3, r2
8002130: 6818 ldr r0, [r3, #0]
8002132: f107 0220 add.w r2, r7, #32
8002136: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800213a: 015b lsls r3, r3, #5
800213c: 4413 add r3, r2
800213e: 3304 adds r3, #4
8002140: 6819 ldr r1, [r3, #0]
8002142: f107 0220 add.w r2, r7, #32
8002146: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800214a: 015b lsls r3, r3, #5
800214c: 3308 adds r3, #8
800214e: 4413 add r3, r2
8002150: 461a mov r2, r3
8002152: f000 ff21 bl 8002f98 <BSP_LCD_DrawBitmap>
// On alterne le deplacement des méchants comme dans le vrai jeux
//TODO est ce que ca va posé un décalage entre l'affichage et la hitboxe ?
list_monsters[i].x = list_monsters[i].x + deplacement*2;
8002156: f107 0220 add.w r2, r7, #32
800215a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800215e: 015b lsls r3, r3, #5
8002160: 4413 add r3, r2
8002162: 681b ldr r3, [r3, #0]
8002164: f897 23ee ldrb.w r2, [r7, #1006] ; 0x3ee
8002168: 0052 lsls r2, r2, #1
800216a: 441a add r2, r3
800216c: f107 0120 add.w r1, r7, #32
8002170: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
8002174: 015b lsls r3, r3, #5
8002176: 440b add r3, r1
8002178: 601a str r2, [r3, #0]
for (int i=0;i< number_monsters;i++){
800217a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800217e: 3301 adds r3, #1
8002180: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
8002184: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
8002188: f8d7 23e8 ldr.w r2, [r7, #1000] ; 0x3e8
800218c: 429a cmp r2, r3
800218e: f6ff af7e blt.w 800208e <f_block_enemie+0x66>
}
}
deplacement = -1;
8002192: 23ff movs r3, #255 ; 0xff
8002194: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8002198: f507 7378 add.w r3, r7, #992 ; 0x3e0
800219c: f8d7 13e4 ldr.w r1, [r7, #996] ; 0x3e4
80021a0: 4618 mov r0, r3
80021a2: f00b f97f bl 800d4a4 <vTaskDelayUntil>
xQueueReceive(Queue_EHandle, &missile, 0);
80021a6: e75a b.n 800205e <f_block_enemie+0x36>
80021a8: 20008bf8 .word 0x20008bf8
80021ac: 20008b08 .word 0x20008b08
080021b0 <f_projectile>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_projectile */
void f_projectile(void const * argument)
{
80021b0: b590 push {r4, r7, lr}
80021b2: b0dd sub sp, #372 ; 0x174
80021b4: af00 add r7, sp, #0
80021b6: 1d3b adds r3, r7, #4
80021b8: 6018 str r0, [r3, #0]
/* USER CODE BEGIN f_projectile */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 50000;
80021ba: f24c 3350 movw r3, #50000 ; 0xc350
80021be: f8c7 3164 str.w r3, [r7, #356] ; 0x164
/* Infinite loop */
struct Missile liste_missile[20];
struct Missile missile;
uint8_t indice = 0;
80021c2: 2300 movs r3, #0
80021c4: f887 316f strb.w r3, [r7, #367] ; 0x16f
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
80021c8: f000 fc44 bl 8002a54 <BSP_LCD_GetXSize>
80021cc: f8c7 0160 str.w r0, [r7, #352] ; 0x160
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
80021d0: f000 fc54 bl 8002a7c <BSP_LCD_GetYSize>
80021d4: f8c7 015c str.w r0, [r7, #348] ; 0x15c
for (;;)
{
if (xQueueReceive(Queue_NHandle, &missile, 0) == pdPASS)
80021d8: 4b80 ldr r3, [pc, #512] ; (80023dc <f_projectile+0x22c>)
80021da: 681b ldr r3, [r3, #0]
80021dc: f107 0108 add.w r1, r7, #8
80021e0: 2200 movs r2, #0
80021e2: 4618 mov r0, r3
80021e4: f00a fb8e bl 800c904 <xQueueReceive>
80021e8: 4603 mov r3, r0
80021ea: 2b01 cmp r3, #1
80021ec: d10e bne.n 800220c <f_projectile+0x5c>
{
liste_missile[indice++] = missile;
80021ee: f897 316f ldrb.w r3, [r7, #367] ; 0x16f
80021f2: 1c5a adds r2, r3, #1
80021f4: f887 216f strb.w r2, [r7, #367] ; 0x16f
80021f8: f107 0218 add.w r2, r7, #24
80021fc: 011b lsls r3, r3, #4
80021fe: 441a add r2, r3
8002200: f107 0308 add.w r3, r7, #8
8002204: 4614 mov r4, r2
8002206: cb0f ldmia r3, {r0, r1, r2, r3}
8002208: e884 000f stmia.w r4, {r0, r1, r2, r3}
}
for (int i=0;i< indice;i++)
800220c: 2300 movs r3, #0
800220e: f8c7 3168 str.w r3, [r7, #360] ; 0x168
8002212: e1e0 b.n 80025d6 <f_projectile+0x426>
{
// Si le missile n'est pas sur un bord
if (liste_missile[i].valide == 1)
8002214: f107 0218 add.w r2, r7, #24
8002218: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800221c: 011b lsls r3, r3, #4
800221e: 4413 add r3, r2
8002220: 330d adds r3, #13
8002222: 781b ldrb r3, [r3, #0]
8002224: 2b01 cmp r3, #1
8002226: f040 81d1 bne.w 80025cc <f_projectile+0x41c>
{
// Si le missile appartient au joueur :
if (liste_missile[i].equipe == 1)
800222a: f107 0218 add.w r2, r7, #24
800222e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002232: 011b lsls r3, r3, #4
8002234: 4413 add r3, r2
8002236: 3306 adds r3, #6
8002238: 781b ldrb r3, [r3, #0]
800223a: 2b01 cmp r3, #1
800223c: f040 80d8 bne.w 80023f0 <f_projectile+0x240>
{
if (liste_missile[i].x >= Limit_ennemis_x)
8002240: f107 0218 add.w r2, r7, #24
8002244: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002248: 011b lsls r3, r3, #4
800224a: 4413 add r3, r2
800224c: 881b ldrh r3, [r3, #0]
800224e: 461a mov r2, r3
8002250: 4b63 ldr r3, [pc, #396] ; (80023e0 <f_projectile+0x230>)
8002252: 681b ldr r3, [r3, #0]
8002254: 429a cmp r2, r3
8002256: d30f bcc.n 8002278 <f_projectile+0xc8>
{
xQueueSend(Queue_EHandle, &liste_missile+indice,0);
8002258: 4b62 ldr r3, [pc, #392] ; (80023e4 <f_projectile+0x234>)
800225a: 6818 ldr r0, [r3, #0]
800225c: f897 216f ldrb.w r2, [r7, #367] ; 0x16f
8002260: 4613 mov r3, r2
8002262: 009b lsls r3, r3, #2
8002264: 4413 add r3, r2
8002266: 019b lsls r3, r3, #6
8002268: 461a mov r2, r3
800226a: f107 0318 add.w r3, r7, #24
800226e: 1899 adds r1, r3, r2
8002270: 2300 movs r3, #0
8002272: 2200 movs r2, #0
8002274: f00a f916 bl 800c4a4 <xQueueGenericSend>
// TODO Une petite animation d'explosion ?
}
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
8002278: f107 0218 add.w r2, r7, #24
800227c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002280: 011b lsls r3, r3, #4
8002282: 4413 add r3, r2
8002284: 881b ldrh r3, [r3, #0]
8002286: 2b01 cmp r3, #1
8002288: f240 8089 bls.w 800239e <f_projectile+0x1ee>
800228c: f107 0218 add.w r2, r7, #24
8002290: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002294: 011b lsls r3, r3, #4
8002296: 4413 add r3, r2
8002298: 881b ldrh r3, [r3, #0]
800229a: 461a mov r2, r3
800229c: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
80022a0: 3b01 subs r3, #1
80022a2: 429a cmp r2, r3
80022a4: d27b bcs.n 800239e <f_projectile+0x1ee>
80022a6: f107 0218 add.w r2, r7, #24
80022aa: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80022ae: 011b lsls r3, r3, #4
80022b0: 4413 add r3, r2
80022b2: 3302 adds r3, #2
80022b4: 881b ldrh r3, [r3, #0]
80022b6: 461a mov r2, r3
80022b8: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
80022bc: 3b01 subs r3, #1
80022be: 429a cmp r2, r3
80022c0: d26d bcs.n 800239e <f_projectile+0x1ee>
80022c2: f107 0218 add.w r2, r7, #24
80022c6: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80022ca: 011b lsls r3, r3, #4
80022cc: 4413 add r3, r2
80022ce: 3302 adds r3, #2
80022d0: 881b ldrh r3, [r3, #0]
80022d2: 2b01 cmp r3, #1
80022d4: d963 bls.n 800239e <f_projectile+0x1ee>
{
//BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
80022d6: 4b44 ldr r3, [pc, #272] ; (80023e8 <f_projectile+0x238>)
80022d8: 681b ldr r3, [r3, #0]
80022da: 4618 mov r0, r3
80022dc: f000 fc52 bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, 20, 20);
80022e0: 4b42 ldr r3, [pc, #264] ; (80023ec <f_projectile+0x23c>)
80022e2: 681b ldr r3, [r3, #0]
80022e4: b298 uxth r0, r3
80022e6: 4b41 ldr r3, [pc, #260] ; (80023ec <f_projectile+0x23c>)
80022e8: 685b ldr r3, [r3, #4]
80022ea: b299 uxth r1, r3
80022ec: 2314 movs r3, #20
80022ee: 2214 movs r2, #20
80022f0: f000 ff02 bl 80030f8 <BSP_LCD_FillRect>
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
80022f4: f107 0218 add.w r2, r7, #24
80022f8: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80022fc: 011b lsls r3, r3, #4
80022fe: 4413 add r3, r2
8002300: 881a ldrh r2, [r3, #0]
8002302: f107 0118 add.w r1, r7, #24
8002306: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800230a: 011b lsls r3, r3, #4
800230c: 440b add r3, r1
800230e: 3304 adds r3, #4
8002310: 781b ldrb r3, [r3, #0]
8002312: b29b uxth r3, r3
8002314: 4413 add r3, r2
8002316: b299 uxth r1, r3
8002318: f107 0218 add.w r2, r7, #24
800231c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002320: 011b lsls r3, r3, #4
8002322: 4413 add r3, r2
8002324: 460a mov r2, r1
8002326: 801a strh r2, [r3, #0]
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
8002328: f107 0218 add.w r2, r7, #24
800232c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002330: 011b lsls r3, r3, #4
8002332: 4413 add r3, r2
8002334: 3302 adds r3, #2
8002336: 881a ldrh r2, [r3, #0]
8002338: f107 0118 add.w r1, r7, #24
800233c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002340: 011b lsls r3, r3, #4
8002342: 440b add r3, r1
8002344: 3305 adds r3, #5
8002346: 781b ldrb r3, [r3, #0]
8002348: b29b uxth r3, r3
800234a: 4413 add r3, r2
800234c: b299 uxth r1, r3
800234e: f107 0218 add.w r2, r7, #24
8002352: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002356: 011b lsls r3, r3, #4
8002358: 4413 add r3, r2
800235a: 3302 adds r3, #2
800235c: 460a mov r2, r1
800235e: 801a strh r2, [r3, #0]
//BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
BSP_LCD_SetTextColor(liste_missile[i].color);
8002360: f107 0218 add.w r2, r7, #24
8002364: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002368: 011b lsls r3, r3, #4
800236a: 4413 add r3, r2
800236c: 3308 adds r3, #8
800236e: 681b ldr r3, [r3, #0]
8002370: 4618 mov r0, r3
8002372: f000 fc07 bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(liste_missile[i].x, liste_missile[i].y, 20, 20);
8002376: f107 0218 add.w r2, r7, #24
800237a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800237e: 011b lsls r3, r3, #4
8002380: 4413 add r3, r2
8002382: 8818 ldrh r0, [r3, #0]
8002384: f107 0218 add.w r2, r7, #24
8002388: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800238c: 011b lsls r3, r3, #4
800238e: 4413 add r3, r2
8002390: 3302 adds r3, #2
8002392: 8819 ldrh r1, [r3, #0]
8002394: 2314 movs r3, #20
8002396: 2214 movs r2, #20
8002398: f000 feae bl 80030f8 <BSP_LCD_FillRect>
800239c: e116 b.n 80025cc <f_projectile+0x41c>
}
//TODO test sur tous les ennemis
else
{
liste_missile[i].valide = 0;
800239e: f107 0218 add.w r2, r7, #24
80023a2: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023a6: 011b lsls r3, r3, #4
80023a8: 4413 add r3, r2
80023aa: 330d adds r3, #13
80023ac: 2200 movs r2, #0
80023ae: 701a strb r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80023b0: f107 0218 add.w r2, r7, #24
80023b4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023b8: 011b lsls r3, r3, #4
80023ba: 4413 add r3, r2
80023bc: 8818 ldrh r0, [r3, #0]
80023be: f107 0218 add.w r2, r7, #24
80023c2: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023c6: 011b lsls r3, r3, #4
80023c8: 4413 add r3, r2
80023ca: 3302 adds r3, #2
80023cc: 8819 ldrh r1, [r3, #0]
80023ce: 4b06 ldr r3, [pc, #24] ; (80023e8 <f_projectile+0x238>)
80023d0: 681b ldr r3, [r3, #0]
80023d2: 461a mov r2, r3
80023d4: f000 fd98 bl 8002f08 <BSP_LCD_DrawPixel>
80023d8: e0f8 b.n 80025cc <f_projectile+0x41c>
80023da: bf00 nop
80023dc: 20008b04 .word 0x20008b04
80023e0: 2000004c .word 0x2000004c
80023e4: 20008bf8 .word 0x20008bf8
80023e8: 20000044 .word 0x20000044
80023ec: 20000028 .word 0x20000028
}
}
// Si le missile appartient aux ennemis
else if (liste_missile[i].equipe == 0)
80023f0: f107 0218 add.w r2, r7, #24
80023f4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023f8: 011b lsls r3, r3, #4
80023fa: 4413 add r3, r2
80023fc: 3306 adds r3, #6
80023fe: 781b ldrb r3, [r3, #0]
8002400: 2b00 cmp r3, #0
8002402: f040 80e3 bne.w 80025cc <f_projectile+0x41c>
{
if ((liste_missile[i].x == joueur.x)&&(liste_missile[i].y == joueur.y))
8002406: f107 0218 add.w r2, r7, #24
800240a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800240e: 011b lsls r3, r3, #4
8002410: 4413 add r3, r2
8002412: 881b ldrh r3, [r3, #0]
8002414: 461a mov r2, r3
8002416: 4b77 ldr r3, [pc, #476] ; (80025f4 <f_projectile+0x444>)
8002418: 681b ldr r3, [r3, #0]
800241a: 429a cmp r2, r3
800241c: d125 bne.n 800246a <f_projectile+0x2ba>
800241e: f107 0218 add.w r2, r7, #24
8002422: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002426: 011b lsls r3, r3, #4
8002428: 4413 add r3, r2
800242a: 3302 adds r3, #2
800242c: 881b ldrh r3, [r3, #0]
800242e: 461a mov r2, r3
8002430: 4b70 ldr r3, [pc, #448] ; (80025f4 <f_projectile+0x444>)
8002432: 685b ldr r3, [r3, #4]
8002434: 429a cmp r2, r3
8002436: d118 bne.n 800246a <f_projectile+0x2ba>
{
xQueueSend(Queue_JHandle, &liste_missile+indice,0);
8002438: 4b6f ldr r3, [pc, #444] ; (80025f8 <f_projectile+0x448>)
800243a: 6818 ldr r0, [r3, #0]
800243c: f897 216f ldrb.w r2, [r7, #367] ; 0x16f
8002440: 4613 mov r3, r2
8002442: 009b lsls r3, r3, #2
8002444: 4413 add r3, r2
8002446: 019b lsls r3, r3, #6
8002448: 461a mov r2, r3
800244a: f107 0318 add.w r3, r7, #24
800244e: 1899 adds r1, r3, r2
8002450: 2300 movs r3, #0
8002452: 2200 movs r2, #0
8002454: f00a f826 bl 800c4a4 <xQueueGenericSend>
liste_missile[i].valide = 0;
8002458: f107 0218 add.w r2, r7, #24
800245c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002460: 011b lsls r3, r3, #4
8002462: 4413 add r3, r2
8002464: 330d adds r3, #13
8002466: 2200 movs r2, #0
8002468: 701a strb r2, [r3, #0]
// TODO Une petite animation d'explosion ?
}
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
800246a: f107 0218 add.w r2, r7, #24
800246e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002472: 011b lsls r3, r3, #4
8002474: 4413 add r3, r2
8002476: 881b ldrh r3, [r3, #0]
8002478: 2b01 cmp r3, #1
800247a: f240 808a bls.w 8002592 <f_projectile+0x3e2>
800247e: f107 0218 add.w r2, r7, #24
8002482: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002486: 011b lsls r3, r3, #4
8002488: 4413 add r3, r2
800248a: 881b ldrh r3, [r3, #0]
800248c: 461a mov r2, r3
800248e: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
8002492: 3b01 subs r3, #1
8002494: 429a cmp r2, r3
8002496: d27c bcs.n 8002592 <f_projectile+0x3e2>
8002498: f107 0218 add.w r2, r7, #24
800249c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024a0: 011b lsls r3, r3, #4
80024a2: 4413 add r3, r2
80024a4: 3302 adds r3, #2
80024a6: 881b ldrh r3, [r3, #0]
80024a8: 461a mov r2, r3
80024aa: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
80024ae: 3b01 subs r3, #1
80024b0: 429a cmp r2, r3
80024b2: d26e bcs.n 8002592 <f_projectile+0x3e2>
80024b4: f107 0218 add.w r2, r7, #24
80024b8: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024bc: 011b lsls r3, r3, #4
80024be: 4413 add r3, r2
80024c0: 3302 adds r3, #2
80024c2: 881b ldrh r3, [r3, #0]
80024c4: 2b01 cmp r3, #1
80024c6: d964 bls.n 8002592 <f_projectile+0x3e2>
{
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80024c8: f107 0218 add.w r2, r7, #24
80024cc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024d0: 011b lsls r3, r3, #4
80024d2: 4413 add r3, r2
80024d4: 8818 ldrh r0, [r3, #0]
80024d6: f107 0218 add.w r2, r7, #24
80024da: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024de: 011b lsls r3, r3, #4
80024e0: 4413 add r3, r2
80024e2: 3302 adds r3, #2
80024e4: 8819 ldrh r1, [r3, #0]
80024e6: 4b45 ldr r3, [pc, #276] ; (80025fc <f_projectile+0x44c>)
80024e8: 681b ldr r3, [r3, #0]
80024ea: 461a mov r2, r3
80024ec: f000 fd0c bl 8002f08 <BSP_LCD_DrawPixel>
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
80024f0: f107 0218 add.w r2, r7, #24
80024f4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024f8: 011b lsls r3, r3, #4
80024fa: 4413 add r3, r2
80024fc: 881a ldrh r2, [r3, #0]
80024fe: f107 0118 add.w r1, r7, #24
8002502: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002506: 011b lsls r3, r3, #4
8002508: 440b add r3, r1
800250a: 3304 adds r3, #4
800250c: 781b ldrb r3, [r3, #0]
800250e: b29b uxth r3, r3
8002510: 4413 add r3, r2
8002512: b299 uxth r1, r3
8002514: f107 0218 add.w r2, r7, #24
8002518: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800251c: 011b lsls r3, r3, #4
800251e: 4413 add r3, r2
8002520: 460a mov r2, r1
8002522: 801a strh r2, [r3, #0]
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
8002524: f107 0218 add.w r2, r7, #24
8002528: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800252c: 011b lsls r3, r3, #4
800252e: 4413 add r3, r2
8002530: 3302 adds r3, #2
8002532: 881a ldrh r2, [r3, #0]
8002534: f107 0118 add.w r1, r7, #24
8002538: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800253c: 011b lsls r3, r3, #4
800253e: 440b add r3, r1
8002540: 3305 adds r3, #5
8002542: 781b ldrb r3, [r3, #0]
8002544: b29b uxth r3, r3
8002546: 4413 add r3, r2
8002548: b299 uxth r1, r3
800254a: f107 0218 add.w r2, r7, #24
800254e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002552: 011b lsls r3, r3, #4
8002554: 4413 add r3, r2
8002556: 3302 adds r3, #2
8002558: 460a mov r2, r1
800255a: 801a strh r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
800255c: f107 0218 add.w r2, r7, #24
8002560: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002564: 011b lsls r3, r3, #4
8002566: 4413 add r3, r2
8002568: 8818 ldrh r0, [r3, #0]
800256a: f107 0218 add.w r2, r7, #24
800256e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002572: 011b lsls r3, r3, #4
8002574: 4413 add r3, r2
8002576: 3302 adds r3, #2
8002578: 8819 ldrh r1, [r3, #0]
800257a: f107 0218 add.w r2, r7, #24
800257e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002582: 011b lsls r3, r3, #4
8002584: 4413 add r3, r2
8002586: 3308 adds r3, #8
8002588: 681b ldr r3, [r3, #0]
800258a: 461a mov r2, r3
800258c: f000 fcbc bl 8002f08 <BSP_LCD_DrawPixel>
8002590: e01c b.n 80025cc <f_projectile+0x41c>
}
else
{
liste_missile[i].valide = 0;
8002592: f107 0218 add.w r2, r7, #24
8002596: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800259a: 011b lsls r3, r3, #4
800259c: 4413 add r3, r2
800259e: 330d adds r3, #13
80025a0: 2200 movs r2, #0
80025a2: 701a strb r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80025a4: f107 0218 add.w r2, r7, #24
80025a8: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025ac: 011b lsls r3, r3, #4
80025ae: 4413 add r3, r2
80025b0: 8818 ldrh r0, [r3, #0]
80025b2: f107 0218 add.w r2, r7, #24
80025b6: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025ba: 011b lsls r3, r3, #4
80025bc: 4413 add r3, r2
80025be: 3302 adds r3, #2
80025c0: 8819 ldrh r1, [r3, #0]
80025c2: 4b0e ldr r3, [pc, #56] ; (80025fc <f_projectile+0x44c>)
80025c4: 681b ldr r3, [r3, #0]
80025c6: 461a mov r2, r3
80025c8: f000 fc9e bl 8002f08 <BSP_LCD_DrawPixel>
for (int i=0;i< indice;i++)
80025cc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025d0: 3301 adds r3, #1
80025d2: f8c7 3168 str.w r3, [r7, #360] ; 0x168
80025d6: f897 316f ldrb.w r3, [r7, #367] ; 0x16f
80025da: f8d7 2168 ldr.w r2, [r7, #360] ; 0x168
80025de: 429a cmp r2, r3
80025e0: f6ff ae18 blt.w 8002214 <f_projectile+0x64>
}
}
}
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
80025e4: f507 73ac add.w r3, r7, #344 ; 0x158
80025e8: f8d7 1164 ldr.w r1, [r7, #356] ; 0x164
80025ec: 4618 mov r0, r3
80025ee: f00a ff59 bl 800d4a4 <vTaskDelayUntil>
if (xQueueReceive(Queue_NHandle, &missile, 0) == pdPASS)
80025f2: e5f1 b.n 80021d8 <f_projectile+0x28>
80025f4: 20000028 .word 0x20000028
80025f8: 20008920 .word 0x20008920
80025fc: 20000044 .word 0x20000044
08002600 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002600: b580 push {r7, lr}
8002602: b082 sub sp, #8
8002604: af00 add r7, sp, #0
8002606: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
8002608: 687b ldr r3, [r7, #4]
800260a: 681b ldr r3, [r3, #0]
800260c: 4a04 ldr r2, [pc, #16] ; (8002620 <HAL_TIM_PeriodElapsedCallback+0x20>)
800260e: 4293 cmp r3, r2
8002610: d101 bne.n 8002616 <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8002612: f002 f9ad bl 8004970 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8002616: bf00 nop
8002618: 3708 adds r7, #8
800261a: 46bd mov sp, r7
800261c: bd80 pop {r7, pc}
800261e: bf00 nop
8002620: 40001000 .word 0x40001000
08002624 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8002624: b480 push {r7}
8002626: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002628: b672 cpsid i
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800262a: e7fe b.n 800262a <Error_Handler+0x6>
0800262c <I2Cx_MspInit>:
* @brief Initializes I2C MSP.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
{
800262c: b580 push {r7, lr}
800262e: b08c sub sp, #48 ; 0x30
8002630: af00 add r7, sp, #0
8002632: 6078 str r0, [r7, #4]
GPIO_InitTypeDef gpio_init_structure;
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
8002634: 687b ldr r3, [r7, #4]
8002636: 4a51 ldr r2, [pc, #324] ; (800277c <I2Cx_MspInit+0x150>)
8002638: 4293 cmp r3, r2
800263a: d14d bne.n 80026d8 <I2Cx_MspInit+0xac>
{
/* AUDIO and LCD I2C MSP init */
/*** Configure the GPIOs ***/
/* Enable GPIO clock */
DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
800263c: 4b50 ldr r3, [pc, #320] ; (8002780 <I2Cx_MspInit+0x154>)
800263e: 6b1b ldr r3, [r3, #48] ; 0x30
8002640: 4a4f ldr r2, [pc, #316] ; (8002780 <I2Cx_MspInit+0x154>)
8002642: f043 0380 orr.w r3, r3, #128 ; 0x80
8002646: 6313 str r3, [r2, #48] ; 0x30
8002648: 4b4d ldr r3, [pc, #308] ; (8002780 <I2Cx_MspInit+0x154>)
800264a: 6b1b ldr r3, [r3, #48] ; 0x30
800264c: f003 0380 and.w r3, r3, #128 ; 0x80
8002650: 61bb str r3, [r7, #24]
8002652: 69bb ldr r3, [r7, #24]
/* Configure I2C Tx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN;
8002654: 2380 movs r3, #128 ; 0x80
8002656: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
8002658: 2312 movs r3, #18
800265a: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
800265c: 2300 movs r3, #0
800265e: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8002660: 2302 movs r3, #2
8002662: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF;
8002664: 2304 movs r3, #4
8002666: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002668: f107 031c add.w r3, r7, #28
800266c: 4619 mov r1, r3
800266e: 4845 ldr r0, [pc, #276] ; (8002784 <I2Cx_MspInit+0x158>)
8002670: f004 fe02 bl 8007278 <HAL_GPIO_Init>
/* Configure I2C Rx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN;
8002674: f44f 7380 mov.w r3, #256 ; 0x100
8002678: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
800267a: f107 031c add.w r3, r7, #28
800267e: 4619 mov r1, r3
8002680: 4840 ldr r0, [pc, #256] ; (8002784 <I2Cx_MspInit+0x158>)
8002682: f004 fdf9 bl 8007278 <HAL_GPIO_Init>
/*** Configure the I2C peripheral ***/
/* Enable I2C clock */
DISCOVERY_AUDIO_I2Cx_CLK_ENABLE();
8002686: 4b3e ldr r3, [pc, #248] ; (8002780 <I2Cx_MspInit+0x154>)
8002688: 6c1b ldr r3, [r3, #64] ; 0x40
800268a: 4a3d ldr r2, [pc, #244] ; (8002780 <I2Cx_MspInit+0x154>)
800268c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8002690: 6413 str r3, [r2, #64] ; 0x40
8002692: 4b3b ldr r3, [pc, #236] ; (8002780 <I2Cx_MspInit+0x154>)
8002694: 6c1b ldr r3, [r3, #64] ; 0x40
8002696: f403 0300 and.w r3, r3, #8388608 ; 0x800000
800269a: 617b str r3, [r7, #20]
800269c: 697b ldr r3, [r7, #20]
/* Force the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_FORCE_RESET();
800269e: 4b38 ldr r3, [pc, #224] ; (8002780 <I2Cx_MspInit+0x154>)
80026a0: 6a1b ldr r3, [r3, #32]
80026a2: 4a37 ldr r2, [pc, #220] ; (8002780 <I2Cx_MspInit+0x154>)
80026a4: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80026a8: 6213 str r3, [r2, #32]
/* Release the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_RELEASE_RESET();
80026aa: 4b35 ldr r3, [pc, #212] ; (8002780 <I2Cx_MspInit+0x154>)
80026ac: 6a1b ldr r3, [r3, #32]
80026ae: 4a34 ldr r2, [pc, #208] ; (8002780 <I2Cx_MspInit+0x154>)
80026b0: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
80026b4: 6213 str r3, [r2, #32]
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0);
80026b6: 2200 movs r2, #0
80026b8: 210f movs r1, #15
80026ba: 2048 movs r0, #72 ; 0x48
80026bc: f002 fe2c bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn);
80026c0: 2048 movs r0, #72 ; 0x48
80026c2: f002 fe45 bl 8005350 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0);
80026c6: 2200 movs r2, #0
80026c8: 210f movs r1, #15
80026ca: 2049 movs r0, #73 ; 0x49
80026cc: f002 fe24 bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn);
80026d0: 2049 movs r0, #73 ; 0x49
80026d2: f002 fe3d bl 8005350 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
}
}
80026d6: e04d b.n 8002774 <I2Cx_MspInit+0x148>
DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
80026d8: 4b29 ldr r3, [pc, #164] ; (8002780 <I2Cx_MspInit+0x154>)
80026da: 6b1b ldr r3, [r3, #48] ; 0x30
80026dc: 4a28 ldr r2, [pc, #160] ; (8002780 <I2Cx_MspInit+0x154>)
80026de: f043 0302 orr.w r3, r3, #2
80026e2: 6313 str r3, [r2, #48] ; 0x30
80026e4: 4b26 ldr r3, [pc, #152] ; (8002780 <I2Cx_MspInit+0x154>)
80026e6: 6b1b ldr r3, [r3, #48] ; 0x30
80026e8: f003 0302 and.w r3, r3, #2
80026ec: 613b str r3, [r7, #16]
80026ee: 693b ldr r3, [r7, #16]
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN;
80026f0: f44f 7380 mov.w r3, #256 ; 0x100
80026f4: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
80026f6: 2312 movs r3, #18
80026f8: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
80026fa: 2300 movs r3, #0
80026fc: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
80026fe: 2302 movs r3, #2
8002700: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF;
8002702: 2304 movs r3, #4
8002704: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002706: f107 031c add.w r3, r7, #28
800270a: 4619 mov r1, r3
800270c: 481e ldr r0, [pc, #120] ; (8002788 <I2Cx_MspInit+0x15c>)
800270e: f004 fdb3 bl 8007278 <HAL_GPIO_Init>
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN;
8002712: f44f 7300 mov.w r3, #512 ; 0x200
8002716: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002718: f107 031c add.w r3, r7, #28
800271c: 4619 mov r1, r3
800271e: 481a ldr r0, [pc, #104] ; (8002788 <I2Cx_MspInit+0x15c>)
8002720: f004 fdaa bl 8007278 <HAL_GPIO_Init>
DISCOVERY_EXT_I2Cx_CLK_ENABLE();
8002724: 4b16 ldr r3, [pc, #88] ; (8002780 <I2Cx_MspInit+0x154>)
8002726: 6c1b ldr r3, [r3, #64] ; 0x40
8002728: 4a15 ldr r2, [pc, #84] ; (8002780 <I2Cx_MspInit+0x154>)
800272a: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
800272e: 6413 str r3, [r2, #64] ; 0x40
8002730: 4b13 ldr r3, [pc, #76] ; (8002780 <I2Cx_MspInit+0x154>)
8002732: 6c1b ldr r3, [r3, #64] ; 0x40
8002734: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002738: 60fb str r3, [r7, #12]
800273a: 68fb ldr r3, [r7, #12]
DISCOVERY_EXT_I2Cx_FORCE_RESET();
800273c: 4b10 ldr r3, [pc, #64] ; (8002780 <I2Cx_MspInit+0x154>)
800273e: 6a1b ldr r3, [r3, #32]
8002740: 4a0f ldr r2, [pc, #60] ; (8002780 <I2Cx_MspInit+0x154>)
8002742: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8002746: 6213 str r3, [r2, #32]
DISCOVERY_EXT_I2Cx_RELEASE_RESET();
8002748: 4b0d ldr r3, [pc, #52] ; (8002780 <I2Cx_MspInit+0x154>)
800274a: 6a1b ldr r3, [r3, #32]
800274c: 4a0c ldr r2, [pc, #48] ; (8002780 <I2Cx_MspInit+0x154>)
800274e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
8002752: 6213 str r3, [r2, #32]
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0);
8002754: 2200 movs r2, #0
8002756: 210f movs r1, #15
8002758: 201f movs r0, #31
800275a: f002 fddd bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn);
800275e: 201f movs r0, #31
8002760: f002 fdf6 bl 8005350 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
8002764: 2200 movs r2, #0
8002766: 210f movs r1, #15
8002768: 2020 movs r0, #32
800276a: f002 fdd5 bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
800276e: 2020 movs r0, #32
8002770: f002 fdee bl 8005350 <HAL_NVIC_EnableIRQ>
}
8002774: bf00 nop
8002776: 3730 adds r7, #48 ; 0x30
8002778: 46bd mov sp, r7
800277a: bd80 pop {r7, pc}
800277c: 20000390 .word 0x20000390
8002780: 40023800 .word 0x40023800
8002784: 40021c00 .word 0x40021c00
8002788: 40020400 .word 0x40020400
0800278c <I2Cx_Init>:
* @brief Initializes I2C HAL.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
{
800278c: b580 push {r7, lr}
800278e: b082 sub sp, #8
8002790: af00 add r7, sp, #0
8002792: 6078 str r0, [r7, #4]
if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET)
8002794: 6878 ldr r0, [r7, #4]
8002796: f005 fa67 bl 8007c68 <HAL_I2C_GetState>
800279a: 4603 mov r3, r0
800279c: 2b00 cmp r3, #0
800279e: d125 bne.n 80027ec <I2Cx_Init+0x60>
{
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
80027a0: 687b ldr r3, [r7, #4]
80027a2: 4a14 ldr r2, [pc, #80] ; (80027f4 <I2Cx_Init+0x68>)
80027a4: 4293 cmp r3, r2
80027a6: d103 bne.n 80027b0 <I2Cx_Init+0x24>
{
/* Audio and LCD I2C configuration */
i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx;
80027a8: 687b ldr r3, [r7, #4]
80027aa: 4a13 ldr r2, [pc, #76] ; (80027f8 <I2Cx_Init+0x6c>)
80027ac: 601a str r2, [r3, #0]
80027ae: e002 b.n 80027b6 <I2Cx_Init+0x2a>
}
else
{
/* External, camera and Arduino connector I2C configuration */
i2c_handler->Instance = DISCOVERY_EXT_I2Cx;
80027b0: 687b ldr r3, [r7, #4]
80027b2: 4a12 ldr r2, [pc, #72] ; (80027fc <I2Cx_Init+0x70>)
80027b4: 601a str r2, [r3, #0]
}
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
80027b6: 687b ldr r3, [r7, #4]
80027b8: 4a11 ldr r2, [pc, #68] ; (8002800 <I2Cx_Init+0x74>)
80027ba: 605a str r2, [r3, #4]
i2c_handler->Init.OwnAddress1 = 0;
80027bc: 687b ldr r3, [r7, #4]
80027be: 2200 movs r2, #0
80027c0: 609a str r2, [r3, #8]
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80027c2: 687b ldr r3, [r7, #4]
80027c4: 2201 movs r2, #1
80027c6: 60da str r2, [r3, #12]
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80027c8: 687b ldr r3, [r7, #4]
80027ca: 2200 movs r2, #0
80027cc: 611a str r2, [r3, #16]
i2c_handler->Init.OwnAddress2 = 0;
80027ce: 687b ldr r3, [r7, #4]
80027d0: 2200 movs r2, #0
80027d2: 615a str r2, [r3, #20]
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80027d4: 687b ldr r3, [r7, #4]
80027d6: 2200 movs r2, #0
80027d8: 61da str r2, [r3, #28]
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80027da: 687b ldr r3, [r7, #4]
80027dc: 2200 movs r2, #0
80027de: 621a str r2, [r3, #32]
/* Init the I2C */
I2Cx_MspInit(i2c_handler);
80027e0: 6878 ldr r0, [r7, #4]
80027e2: f7ff ff23 bl 800262c <I2Cx_MspInit>
HAL_I2C_Init(i2c_handler);
80027e6: 6878 ldr r0, [r7, #4]
80027e8: f004 ff3c bl 8007664 <HAL_I2C_Init>
}
}
80027ec: bf00 nop
80027ee: 3708 adds r7, #8
80027f0: 46bd mov sp, r7
80027f2: bd80 pop {r7, pc}
80027f4: 20000390 .word 0x20000390
80027f8: 40005c00 .word 0x40005c00
80027fc: 40005400 .word 0x40005400
8002800: 40912732 .word 0x40912732
08002804 <I2Cx_ReadMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
8002804: b580 push {r7, lr}
8002806: b08a sub sp, #40 ; 0x28
8002808: af04 add r7, sp, #16
800280a: 60f8 str r0, [r7, #12]
800280c: 4608 mov r0, r1
800280e: 4611 mov r1, r2
8002810: 461a mov r2, r3
8002812: 4603 mov r3, r0
8002814: 72fb strb r3, [r7, #11]
8002816: 460b mov r3, r1
8002818: 813b strh r3, [r7, #8]
800281a: 4613 mov r3, r2
800281c: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
800281e: 2300 movs r3, #0
8002820: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
8002822: 7afb ldrb r3, [r7, #11]
8002824: b299 uxth r1, r3
8002826: 88f8 ldrh r0, [r7, #6]
8002828: 893a ldrh r2, [r7, #8]
800282a: f44f 737a mov.w r3, #1000 ; 0x3e8
800282e: 9302 str r3, [sp, #8]
8002830: 8cbb ldrh r3, [r7, #36] ; 0x24
8002832: 9301 str r3, [sp, #4]
8002834: 6a3b ldr r3, [r7, #32]
8002836: 9300 str r3, [sp, #0]
8002838: 4603 mov r3, r0
800283a: 68f8 ldr r0, [r7, #12]
800283c: f005 f8fa bl 8007a34 <HAL_I2C_Mem_Read>
8002840: 4603 mov r3, r0
8002842: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
8002844: 7dfb ldrb r3, [r7, #23]
8002846: 2b00 cmp r3, #0
8002848: d004 beq.n 8002854 <I2Cx_ReadMultiple+0x50>
{
/* I2C error occurred */
I2Cx_Error(i2c_handler, Addr);
800284a: 7afb ldrb r3, [r7, #11]
800284c: 4619 mov r1, r3
800284e: 68f8 ldr r0, [r7, #12]
8002850: f000 f832 bl 80028b8 <I2Cx_Error>
}
return status;
8002854: 7dfb ldrb r3, [r7, #23]
}
8002856: 4618 mov r0, r3
8002858: 3718 adds r7, #24
800285a: 46bd mov sp, r7
800285c: bd80 pop {r7, pc}
0800285e <I2Cx_WriteMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
800285e: b580 push {r7, lr}
8002860: b08a sub sp, #40 ; 0x28
8002862: af04 add r7, sp, #16
8002864: 60f8 str r0, [r7, #12]
8002866: 4608 mov r0, r1
8002868: 4611 mov r1, r2
800286a: 461a mov r2, r3
800286c: 4603 mov r3, r0
800286e: 72fb strb r3, [r7, #11]
8002870: 460b mov r3, r1
8002872: 813b strh r3, [r7, #8]
8002874: 4613 mov r3, r2
8002876: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
8002878: 2300 movs r3, #0
800287a: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
800287c: 7afb ldrb r3, [r7, #11]
800287e: b299 uxth r1, r3
8002880: 88f8 ldrh r0, [r7, #6]
8002882: 893a ldrh r2, [r7, #8]
8002884: f44f 737a mov.w r3, #1000 ; 0x3e8
8002888: 9302 str r3, [sp, #8]
800288a: 8cbb ldrh r3, [r7, #36] ; 0x24
800288c: 9301 str r3, [sp, #4]
800288e: 6a3b ldr r3, [r7, #32]
8002890: 9300 str r3, [sp, #0]
8002892: 4603 mov r3, r0
8002894: 68f8 ldr r0, [r7, #12]
8002896: f004 ffb9 bl 800780c <HAL_I2C_Mem_Write>
800289a: 4603 mov r3, r0
800289c: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
800289e: 7dfb ldrb r3, [r7, #23]
80028a0: 2b00 cmp r3, #0
80028a2: d004 beq.n 80028ae <I2Cx_WriteMultiple+0x50>
{
/* Re-Initiaize the I2C Bus */
I2Cx_Error(i2c_handler, Addr);
80028a4: 7afb ldrb r3, [r7, #11]
80028a6: 4619 mov r1, r3
80028a8: 68f8 ldr r0, [r7, #12]
80028aa: f000 f805 bl 80028b8 <I2Cx_Error>
}
return status;
80028ae: 7dfb ldrb r3, [r7, #23]
}
80028b0: 4618 mov r0, r3
80028b2: 3718 adds r7, #24
80028b4: 46bd mov sp, r7
80028b6: bd80 pop {r7, pc}
080028b8 <I2Cx_Error>:
* @param i2c_handler : I2C handler
* @param Addr: I2C Address
* @retval None
*/
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
{
80028b8: b580 push {r7, lr}
80028ba: b082 sub sp, #8
80028bc: af00 add r7, sp, #0
80028be: 6078 str r0, [r7, #4]
80028c0: 460b mov r3, r1
80028c2: 70fb strb r3, [r7, #3]
/* De-initialize the I2C communication bus */
HAL_I2C_DeInit(i2c_handler);
80028c4: 6878 ldr r0, [r7, #4]
80028c6: f004 ff5d bl 8007784 <HAL_I2C_DeInit>
/* Re-Initialize the I2C communication bus */
I2Cx_Init(i2c_handler);
80028ca: 6878 ldr r0, [r7, #4]
80028cc: f7ff ff5e bl 800278c <I2Cx_Init>
}
80028d0: bf00 nop
80028d2: 3708 adds r7, #8
80028d4: 46bd mov sp, r7
80028d6: bd80 pop {r7, pc}
080028d8 <TS_IO_Init>:
/**
* @brief Initializes Touchscreen low level.
* @retval None
*/
void TS_IO_Init(void)
{
80028d8: b580 push {r7, lr}
80028da: af00 add r7, sp, #0
I2Cx_Init(&hI2cAudioHandler);
80028dc: 4802 ldr r0, [pc, #8] ; (80028e8 <TS_IO_Init+0x10>)
80028de: f7ff ff55 bl 800278c <I2Cx_Init>
}
80028e2: bf00 nop
80028e4: bd80 pop {r7, pc}
80028e6: bf00 nop
80028e8: 20000390 .word 0x20000390
080028ec <TS_IO_Write>:
* @param Reg: Reg address
* @param Value: Data to be written
* @retval None
*/
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
{
80028ec: b580 push {r7, lr}
80028ee: b084 sub sp, #16
80028f0: af02 add r7, sp, #8
80028f2: 4603 mov r3, r0
80028f4: 71fb strb r3, [r7, #7]
80028f6: 460b mov r3, r1
80028f8: 71bb strb r3, [r7, #6]
80028fa: 4613 mov r3, r2
80028fc: 717b strb r3, [r7, #5]
I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
80028fe: 79bb ldrb r3, [r7, #6]
8002900: b29a uxth r2, r3
8002902: 79f9 ldrb r1, [r7, #7]
8002904: 2301 movs r3, #1
8002906: 9301 str r3, [sp, #4]
8002908: 1d7b adds r3, r7, #5
800290a: 9300 str r3, [sp, #0]
800290c: 2301 movs r3, #1
800290e: 4803 ldr r0, [pc, #12] ; (800291c <TS_IO_Write+0x30>)
8002910: f7ff ffa5 bl 800285e <I2Cx_WriteMultiple>
}
8002914: bf00 nop
8002916: 3708 adds r7, #8
8002918: 46bd mov sp, r7
800291a: bd80 pop {r7, pc}
800291c: 20000390 .word 0x20000390
08002920 <TS_IO_Read>:
* @param Addr: I2C address
* @param Reg: Reg address
* @retval Data to be read
*/
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
{
8002920: b580 push {r7, lr}
8002922: b086 sub sp, #24
8002924: af02 add r7, sp, #8
8002926: 4603 mov r3, r0
8002928: 460a mov r2, r1
800292a: 71fb strb r3, [r7, #7]
800292c: 4613 mov r3, r2
800292e: 71bb strb r3, [r7, #6]
uint8_t read_value = 0;
8002930: 2300 movs r3, #0
8002932: 73fb strb r3, [r7, #15]
I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
8002934: 79bb ldrb r3, [r7, #6]
8002936: b29a uxth r2, r3
8002938: 79f9 ldrb r1, [r7, #7]
800293a: 2301 movs r3, #1
800293c: 9301 str r3, [sp, #4]
800293e: f107 030f add.w r3, r7, #15
8002942: 9300 str r3, [sp, #0]
8002944: 2301 movs r3, #1
8002946: 4804 ldr r0, [pc, #16] ; (8002958 <TS_IO_Read+0x38>)
8002948: f7ff ff5c bl 8002804 <I2Cx_ReadMultiple>
return read_value;
800294c: 7bfb ldrb r3, [r7, #15]
}
800294e: 4618 mov r0, r3
8002950: 3710 adds r7, #16
8002952: 46bd mov sp, r7
8002954: bd80 pop {r7, pc}
8002956: bf00 nop
8002958: 20000390 .word 0x20000390
0800295c <TS_IO_Delay>:
* @brief TS delay
* @param Delay: Delay in ms
* @retval None
*/
void TS_IO_Delay(uint32_t Delay)
{
800295c: b580 push {r7, lr}
800295e: b082 sub sp, #8
8002960: af00 add r7, sp, #0
8002962: 6078 str r0, [r7, #4]
HAL_Delay(Delay);
8002964: 6878 ldr r0, [r7, #4]
8002966: f002 f823 bl 80049b0 <HAL_Delay>
}
800296a: bf00 nop
800296c: 3708 adds r7, #8
800296e: 46bd mov sp, r7
8002970: bd80 pop {r7, pc}
...
08002974 <BSP_LCD_Init>:
/**
* @brief Initializes the LCD.
* @retval LCD state
*/
uint8_t BSP_LCD_Init(void)
{
8002974: b580 push {r7, lr}
8002976: af00 add r7, sp, #0
/* Select the used LCD */
/* The RK043FN48H LCD 480x272 is selected */
/* Timing Configuration */
hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
8002978: 4b31 ldr r3, [pc, #196] ; (8002a40 <BSP_LCD_Init+0xcc>)
800297a: 2228 movs r2, #40 ; 0x28
800297c: 615a str r2, [r3, #20]
hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
800297e: 4b30 ldr r3, [pc, #192] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002980: 2209 movs r2, #9
8002982: 619a str r2, [r3, #24]
hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
8002984: 4b2e ldr r3, [pc, #184] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002986: 2235 movs r2, #53 ; 0x35
8002988: 61da str r2, [r3, #28]
hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
800298a: 4b2d ldr r3, [pc, #180] ; (8002a40 <BSP_LCD_Init+0xcc>)
800298c: 220b movs r2, #11
800298e: 621a str r2, [r3, #32]
hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
8002990: 4b2b ldr r3, [pc, #172] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002992: f240 121b movw r2, #283 ; 0x11b
8002996: 629a str r2, [r3, #40] ; 0x28
hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
8002998: 4b29 ldr r3, [pc, #164] ; (8002a40 <BSP_LCD_Init+0xcc>)
800299a: f240 2215 movw r2, #533 ; 0x215
800299e: 625a str r2, [r3, #36] ; 0x24
hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
80029a0: 4b27 ldr r3, [pc, #156] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029a2: f240 121d movw r2, #285 ; 0x11d
80029a6: 631a str r2, [r3, #48] ; 0x30
hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
80029a8: 4b25 ldr r3, [pc, #148] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029aa: f240 2235 movw r2, #565 ; 0x235
80029ae: 62da str r2, [r3, #44] ; 0x2c
/* LCD clock configuration */
BSP_LCD_ClockConfig(&hLtdcHandler, NULL);
80029b0: 2100 movs r1, #0
80029b2: 4823 ldr r0, [pc, #140] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029b4: f000 fdb2 bl 800351c <BSP_LCD_ClockConfig>
/* Initialize the LCD pixel width and pixel height */
hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH;
80029b8: 4b21 ldr r3, [pc, #132] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029ba: f44f 72f0 mov.w r2, #480 ; 0x1e0
80029be: 661a str r2, [r3, #96] ; 0x60
hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;
80029c0: 4b1f ldr r3, [pc, #124] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029c2: f44f 7288 mov.w r2, #272 ; 0x110
80029c6: 665a str r2, [r3, #100] ; 0x64
/* Background value */
hLtdcHandler.Init.Backcolor.Blue = 0;
80029c8: 4b1d ldr r3, [pc, #116] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029ca: 2200 movs r2, #0
80029cc: f883 2034 strb.w r2, [r3, #52] ; 0x34
hLtdcHandler.Init.Backcolor.Green = 0;
80029d0: 4b1b ldr r3, [pc, #108] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029d2: 2200 movs r2, #0
80029d4: f883 2035 strb.w r2, [r3, #53] ; 0x35
hLtdcHandler.Init.Backcolor.Red = 0;
80029d8: 4b19 ldr r3, [pc, #100] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029da: 2200 movs r2, #0
80029dc: f883 2036 strb.w r2, [r3, #54] ; 0x36
/* Polarity */
hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL;
80029e0: 4b17 ldr r3, [pc, #92] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029e2: 2200 movs r2, #0
80029e4: 605a str r2, [r3, #4]
hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL;
80029e6: 4b16 ldr r3, [pc, #88] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029e8: 2200 movs r2, #0
80029ea: 609a str r2, [r3, #8]
hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80029ec: 4b14 ldr r3, [pc, #80] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029ee: 2200 movs r2, #0
80029f0: 60da str r2, [r3, #12]
hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80029f2: 4b13 ldr r3, [pc, #76] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029f4: 2200 movs r2, #0
80029f6: 611a str r2, [r3, #16]
hLtdcHandler.Instance = LTDC;
80029f8: 4b11 ldr r3, [pc, #68] ; (8002a40 <BSP_LCD_Init+0xcc>)
80029fa: 4a12 ldr r2, [pc, #72] ; (8002a44 <BSP_LCD_Init+0xd0>)
80029fc: 601a str r2, [r3, #0]
if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET)
80029fe: 4810 ldr r0, [pc, #64] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002a00: f005 fd2c bl 800845c <HAL_LTDC_GetState>
8002a04: 4603 mov r3, r0
8002a06: 2b00 cmp r3, #0
8002a08: d103 bne.n 8002a12 <BSP_LCD_Init+0x9e>
{
/* Initialize the LCD Msp: this __weak function can be rewritten by the application */
BSP_LCD_MspInit(&hLtdcHandler, NULL);
8002a0a: 2100 movs r1, #0
8002a0c: 480c ldr r0, [pc, #48] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002a0e: f000 fcab bl 8003368 <BSP_LCD_MspInit>
}
HAL_LTDC_Init(&hLtdcHandler);
8002a12: 480b ldr r0, [pc, #44] ; (8002a40 <BSP_LCD_Init+0xcc>)
8002a14: f005 fb52 bl 80080bc <HAL_LTDC_Init>
/* Assert display enable LCD_DISP pin */
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
8002a18: 2201 movs r2, #1
8002a1a: f44f 5180 mov.w r1, #4096 ; 0x1000
8002a1e: 480a ldr r0, [pc, #40] ; (8002a48 <BSP_LCD_Init+0xd4>)
8002a20: f004 fdd4 bl 80075cc <HAL_GPIO_WritePin>
/* Assert backlight LCD_BL_CTRL pin */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
8002a24: 2201 movs r2, #1
8002a26: 2108 movs r1, #8
8002a28: 4808 ldr r0, [pc, #32] ; (8002a4c <BSP_LCD_Init+0xd8>)
8002a2a: f004 fdcf bl 80075cc <HAL_GPIO_WritePin>
#if !defined(DATA_IN_ExtSDRAM)
/* Initialize the SDRAM */
BSP_SDRAM_Init();
8002a2e: f000 fe21 bl 8003674 <BSP_SDRAM_Init>
#endif
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
8002a32: 4807 ldr r0, [pc, #28] ; (8002a50 <BSP_LCD_Init+0xdc>)
8002a34: f000 f8d8 bl 8002be8 <BSP_LCD_SetFont>
return LCD_OK;
8002a38: 2300 movs r3, #0
}
8002a3a: 4618 mov r0, r3
8002a3c: bd80 pop {r7, pc}
8002a3e: bf00 nop
8002a40: 20008c34 .word 0x20008c34
8002a44: 40016800 .word 0x40016800
8002a48: 40022000 .word 0x40022000
8002a4c: 40022800 .word 0x40022800
8002a50: 20000050 .word 0x20000050
08002a54 <BSP_LCD_GetXSize>:
/**
* @brief Gets the LCD X size.
* @retval Used LCD X size
*/
uint32_t BSP_LCD_GetXSize(void)
{
8002a54: b480 push {r7}
8002a56: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth;
8002a58: 4b06 ldr r3, [pc, #24] ; (8002a74 <BSP_LCD_GetXSize+0x20>)
8002a5a: 681b ldr r3, [r3, #0]
8002a5c: 4a06 ldr r2, [pc, #24] ; (8002a78 <BSP_LCD_GetXSize+0x24>)
8002a5e: 2134 movs r1, #52 ; 0x34
8002a60: fb01 f303 mul.w r3, r1, r3
8002a64: 4413 add r3, r2
8002a66: 3360 adds r3, #96 ; 0x60
8002a68: 681b ldr r3, [r3, #0]
}
8002a6a: 4618 mov r0, r3
8002a6c: 46bd mov sp, r7
8002a6e: f85d 7b04 ldr.w r7, [sp], #4
8002a72: 4770 bx lr
8002a74: 2000041c .word 0x2000041c
8002a78: 20008c34 .word 0x20008c34
08002a7c <BSP_LCD_GetYSize>:
/**
* @brief Gets the LCD Y size.
* @retval Used LCD Y size
*/
uint32_t BSP_LCD_GetYSize(void)
{
8002a7c: b480 push {r7}
8002a7e: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight;
8002a80: 4b06 ldr r3, [pc, #24] ; (8002a9c <BSP_LCD_GetYSize+0x20>)
8002a82: 681b ldr r3, [r3, #0]
8002a84: 4a06 ldr r2, [pc, #24] ; (8002aa0 <BSP_LCD_GetYSize+0x24>)
8002a86: 2134 movs r1, #52 ; 0x34
8002a88: fb01 f303 mul.w r3, r1, r3
8002a8c: 4413 add r3, r2
8002a8e: 3364 adds r3, #100 ; 0x64
8002a90: 681b ldr r3, [r3, #0]
}
8002a92: 4618 mov r0, r3
8002a94: 46bd mov sp, r7
8002a96: f85d 7b04 ldr.w r7, [sp], #4
8002a9a: 4770 bx lr
8002a9c: 2000041c .word 0x2000041c
8002aa0: 20008c34 .word 0x20008c34
08002aa4 <BSP_LCD_LayerDefaultInit>:
* @param LayerIndex: Layer foreground or background
* @param FB_Address: Layer frame buffer
* @retval None
*/
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
{
8002aa4: b580 push {r7, lr}
8002aa6: b090 sub sp, #64 ; 0x40
8002aa8: af00 add r7, sp, #0
8002aaa: 4603 mov r3, r0
8002aac: 6039 str r1, [r7, #0]
8002aae: 80fb strh r3, [r7, #6]
LCD_LayerCfgTypeDef layer_cfg;
/* Layer Init */
layer_cfg.WindowX0 = 0;
8002ab0: 2300 movs r3, #0
8002ab2: 60fb str r3, [r7, #12]
layer_cfg.WindowX1 = BSP_LCD_GetXSize();
8002ab4: f7ff ffce bl 8002a54 <BSP_LCD_GetXSize>
8002ab8: 4603 mov r3, r0
8002aba: 613b str r3, [r7, #16]
layer_cfg.WindowY0 = 0;
8002abc: 2300 movs r3, #0
8002abe: 617b str r3, [r7, #20]
layer_cfg.WindowY1 = BSP_LCD_GetYSize();
8002ac0: f7ff ffdc bl 8002a7c <BSP_LCD_GetYSize>
8002ac4: 4603 mov r3, r0
8002ac6: 61bb str r3, [r7, #24]
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
8002ac8: 2300 movs r3, #0
8002aca: 61fb str r3, [r7, #28]
layer_cfg.FBStartAdress = FB_Address;
8002acc: 683b ldr r3, [r7, #0]
8002ace: 633b str r3, [r7, #48] ; 0x30
layer_cfg.Alpha = 255;
8002ad0: 23ff movs r3, #255 ; 0xff
8002ad2: 623b str r3, [r7, #32]
layer_cfg.Alpha0 = 0;
8002ad4: 2300 movs r3, #0
8002ad6: 627b str r3, [r7, #36] ; 0x24
layer_cfg.Backcolor.Blue = 0;
8002ad8: 2300 movs r3, #0
8002ada: f887 303c strb.w r3, [r7, #60] ; 0x3c
layer_cfg.Backcolor.Green = 0;
8002ade: 2300 movs r3, #0
8002ae0: f887 303d strb.w r3, [r7, #61] ; 0x3d
layer_cfg.Backcolor.Red = 0;
8002ae4: 2300 movs r3, #0
8002ae6: f887 303e strb.w r3, [r7, #62] ; 0x3e
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8002aea: f44f 63c0 mov.w r3, #1536 ; 0x600
8002aee: 62bb str r3, [r7, #40] ; 0x28
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8002af0: 2307 movs r3, #7
8002af2: 62fb str r3, [r7, #44] ; 0x2c
layer_cfg.ImageWidth = BSP_LCD_GetXSize();
8002af4: f7ff ffae bl 8002a54 <BSP_LCD_GetXSize>
8002af8: 4603 mov r3, r0
8002afa: 637b str r3, [r7, #52] ; 0x34
layer_cfg.ImageHeight = BSP_LCD_GetYSize();
8002afc: f7ff ffbe bl 8002a7c <BSP_LCD_GetYSize>
8002b00: 4603 mov r3, r0
8002b02: 63bb str r3, [r7, #56] ; 0x38
HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex);
8002b04: 88fa ldrh r2, [r7, #6]
8002b06: f107 030c add.w r3, r7, #12
8002b0a: 4619 mov r1, r3
8002b0c: 4812 ldr r0, [pc, #72] ; (8002b58 <BSP_LCD_LayerDefaultInit+0xb4>)
8002b0e: f005 fc67 bl 80083e0 <HAL_LTDC_ConfigLayer>
DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
8002b12: 88fa ldrh r2, [r7, #6]
8002b14: 4911 ldr r1, [pc, #68] ; (8002b5c <BSP_LCD_LayerDefaultInit+0xb8>)
8002b16: 4613 mov r3, r2
8002b18: 005b lsls r3, r3, #1
8002b1a: 4413 add r3, r2
8002b1c: 009b lsls r3, r3, #2
8002b1e: 440b add r3, r1
8002b20: 3304 adds r3, #4
8002b22: f04f 32ff mov.w r2, #4294967295
8002b26: 601a str r2, [r3, #0]
DrawProp[LayerIndex].pFont = &Font24;
8002b28: 88fa ldrh r2, [r7, #6]
8002b2a: 490c ldr r1, [pc, #48] ; (8002b5c <BSP_LCD_LayerDefaultInit+0xb8>)
8002b2c: 4613 mov r3, r2
8002b2e: 005b lsls r3, r3, #1
8002b30: 4413 add r3, r2
8002b32: 009b lsls r3, r3, #2
8002b34: 440b add r3, r1
8002b36: 3308 adds r3, #8
8002b38: 4a09 ldr r2, [pc, #36] ; (8002b60 <BSP_LCD_LayerDefaultInit+0xbc>)
8002b3a: 601a str r2, [r3, #0]
DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
8002b3c: 88fa ldrh r2, [r7, #6]
8002b3e: 4907 ldr r1, [pc, #28] ; (8002b5c <BSP_LCD_LayerDefaultInit+0xb8>)
8002b40: 4613 mov r3, r2
8002b42: 005b lsls r3, r3, #1
8002b44: 4413 add r3, r2
8002b46: 009b lsls r3, r3, #2
8002b48: 440b add r3, r1
8002b4a: f04f 427f mov.w r2, #4278190080 ; 0xff000000
8002b4e: 601a str r2, [r3, #0]
}
8002b50: bf00 nop
8002b52: 3740 adds r7, #64 ; 0x40
8002b54: 46bd mov sp, r7
8002b56: bd80 pop {r7, pc}
8002b58: 20008c34 .word 0x20008c34
8002b5c: 20000420 .word 0x20000420
8002b60: 20000050 .word 0x20000050
08002b64 <BSP_LCD_SelectLayer>:
* @brief Selects the LCD Layer.
* @param LayerIndex: Layer foreground or background
* @retval None
*/
void BSP_LCD_SelectLayer(uint32_t LayerIndex)
{
8002b64: b480 push {r7}
8002b66: b083 sub sp, #12
8002b68: af00 add r7, sp, #0
8002b6a: 6078 str r0, [r7, #4]
ActiveLayer = LayerIndex;
8002b6c: 4a04 ldr r2, [pc, #16] ; (8002b80 <BSP_LCD_SelectLayer+0x1c>)
8002b6e: 687b ldr r3, [r7, #4]
8002b70: 6013 str r3, [r2, #0]
}
8002b72: bf00 nop
8002b74: 370c adds r7, #12
8002b76: 46bd mov sp, r7
8002b78: f85d 7b04 ldr.w r7, [sp], #4
8002b7c: 4770 bx lr
8002b7e: bf00 nop
8002b80: 2000041c .word 0x2000041c
08002b84 <BSP_LCD_SetTextColor>:
* @brief Sets the LCD text color.
* @param Color: Text color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetTextColor(uint32_t Color)
{
8002b84: b480 push {r7}
8002b86: b083 sub sp, #12
8002b88: af00 add r7, sp, #0
8002b8a: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].TextColor = Color;
8002b8c: 4b07 ldr r3, [pc, #28] ; (8002bac <BSP_LCD_SetTextColor+0x28>)
8002b8e: 681a ldr r2, [r3, #0]
8002b90: 4907 ldr r1, [pc, #28] ; (8002bb0 <BSP_LCD_SetTextColor+0x2c>)
8002b92: 4613 mov r3, r2
8002b94: 005b lsls r3, r3, #1
8002b96: 4413 add r3, r2
8002b98: 009b lsls r3, r3, #2
8002b9a: 440b add r3, r1
8002b9c: 687a ldr r2, [r7, #4]
8002b9e: 601a str r2, [r3, #0]
}
8002ba0: bf00 nop
8002ba2: 370c adds r7, #12
8002ba4: 46bd mov sp, r7
8002ba6: f85d 7b04 ldr.w r7, [sp], #4
8002baa: 4770 bx lr
8002bac: 2000041c .word 0x2000041c
8002bb0: 20000420 .word 0x20000420
08002bb4 <BSP_LCD_SetBackColor>:
* @brief Sets the LCD background color.
* @param Color: Layer background color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetBackColor(uint32_t Color)
{
8002bb4: b480 push {r7}
8002bb6: b083 sub sp, #12
8002bb8: af00 add r7, sp, #0
8002bba: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].BackColor = Color;
8002bbc: 4b08 ldr r3, [pc, #32] ; (8002be0 <BSP_LCD_SetBackColor+0x2c>)
8002bbe: 681a ldr r2, [r3, #0]
8002bc0: 4908 ldr r1, [pc, #32] ; (8002be4 <BSP_LCD_SetBackColor+0x30>)
8002bc2: 4613 mov r3, r2
8002bc4: 005b lsls r3, r3, #1
8002bc6: 4413 add r3, r2
8002bc8: 009b lsls r3, r3, #2
8002bca: 440b add r3, r1
8002bcc: 3304 adds r3, #4
8002bce: 687a ldr r2, [r7, #4]
8002bd0: 601a str r2, [r3, #0]
}
8002bd2: bf00 nop
8002bd4: 370c adds r7, #12
8002bd6: 46bd mov sp, r7
8002bd8: f85d 7b04 ldr.w r7, [sp], #4
8002bdc: 4770 bx lr
8002bde: bf00 nop
8002be0: 2000041c .word 0x2000041c
8002be4: 20000420 .word 0x20000420
08002be8 <BSP_LCD_SetFont>:
* @brief Sets the LCD text font.
* @param fonts: Layer font to be used
* @retval None
*/
void BSP_LCD_SetFont(sFONT *fonts)
{
8002be8: b480 push {r7}
8002bea: b083 sub sp, #12
8002bec: af00 add r7, sp, #0
8002bee: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].pFont = fonts;
8002bf0: 4b08 ldr r3, [pc, #32] ; (8002c14 <BSP_LCD_SetFont+0x2c>)
8002bf2: 681a ldr r2, [r3, #0]
8002bf4: 4908 ldr r1, [pc, #32] ; (8002c18 <BSP_LCD_SetFont+0x30>)
8002bf6: 4613 mov r3, r2
8002bf8: 005b lsls r3, r3, #1
8002bfa: 4413 add r3, r2
8002bfc: 009b lsls r3, r3, #2
8002bfe: 440b add r3, r1
8002c00: 3308 adds r3, #8
8002c02: 687a ldr r2, [r7, #4]
8002c04: 601a str r2, [r3, #0]
}
8002c06: bf00 nop
8002c08: 370c adds r7, #12
8002c0a: 46bd mov sp, r7
8002c0c: f85d 7b04 ldr.w r7, [sp], #4
8002c10: 4770 bx lr
8002c12: bf00 nop
8002c14: 2000041c .word 0x2000041c
8002c18: 20000420 .word 0x20000420
08002c1c <BSP_LCD_Clear>:
* @brief Clears the hole LCD.
* @param Color: Color of the background
* @retval None
*/
void BSP_LCD_Clear(uint32_t Color)
{
8002c1c: b5f0 push {r4, r5, r6, r7, lr}
8002c1e: b085 sub sp, #20
8002c20: af02 add r7, sp, #8
8002c22: 6078 str r0, [r7, #4]
/* Clear the LCD */
LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
8002c24: 4b0f ldr r3, [pc, #60] ; (8002c64 <BSP_LCD_Clear+0x48>)
8002c26: 681c ldr r4, [r3, #0]
8002c28: 4b0e ldr r3, [pc, #56] ; (8002c64 <BSP_LCD_Clear+0x48>)
8002c2a: 681b ldr r3, [r3, #0]
8002c2c: 4a0e ldr r2, [pc, #56] ; (8002c68 <BSP_LCD_Clear+0x4c>)
8002c2e: 2134 movs r1, #52 ; 0x34
8002c30: fb01 f303 mul.w r3, r1, r3
8002c34: 4413 add r3, r2
8002c36: 335c adds r3, #92 ; 0x5c
8002c38: 681b ldr r3, [r3, #0]
8002c3a: 461d mov r5, r3
8002c3c: f7ff ff0a bl 8002a54 <BSP_LCD_GetXSize>
8002c40: 4606 mov r6, r0
8002c42: f7ff ff1b bl 8002a7c <BSP_LCD_GetYSize>
8002c46: 4602 mov r2, r0
8002c48: 687b ldr r3, [r7, #4]
8002c4a: 9301 str r3, [sp, #4]
8002c4c: 2300 movs r3, #0
8002c4e: 9300 str r3, [sp, #0]
8002c50: 4613 mov r3, r2
8002c52: 4632 mov r2, r6
8002c54: 4629 mov r1, r5
8002c56: 4620 mov r0, r4
8002c58: f000 fc7c bl 8003554 <LL_FillBuffer>
}
8002c5c: bf00 nop
8002c5e: 370c adds r7, #12
8002c60: 46bd mov sp, r7
8002c62: bdf0 pop {r4, r5, r6, r7, pc}
8002c64: 2000041c .word 0x2000041c
8002c68: 20008c34 .word 0x20008c34
08002c6c <BSP_LCD_DrawHLine>:
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
8002c6c: b5b0 push {r4, r5, r7, lr}
8002c6e: b086 sub sp, #24
8002c70: af02 add r7, sp, #8
8002c72: 4603 mov r3, r0
8002c74: 80fb strh r3, [r7, #6]
8002c76: 460b mov r3, r1
8002c78: 80bb strh r3, [r7, #4]
8002c7a: 4613 mov r3, r2
8002c7c: 807b strh r3, [r7, #2]
uint32_t Xaddress = 0;
8002c7e: 2300 movs r3, #0
8002c80: 60fb str r3, [r7, #12]
/* Get the line address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002c82: 4b26 ldr r3, [pc, #152] ; (8002d1c <BSP_LCD_DrawHLine+0xb0>)
8002c84: 681b ldr r3, [r3, #0]
8002c86: 4a26 ldr r2, [pc, #152] ; (8002d20 <BSP_LCD_DrawHLine+0xb4>)
8002c88: 2134 movs r1, #52 ; 0x34
8002c8a: fb01 f303 mul.w r3, r1, r3
8002c8e: 4413 add r3, r2
8002c90: 3348 adds r3, #72 ; 0x48
8002c92: 681b ldr r3, [r3, #0]
8002c94: 2b02 cmp r3, #2
8002c96: d114 bne.n 8002cc2 <BSP_LCD_DrawHLine+0x56>
{ /* RGB565 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002c98: 4b20 ldr r3, [pc, #128] ; (8002d1c <BSP_LCD_DrawHLine+0xb0>)
8002c9a: 681b ldr r3, [r3, #0]
8002c9c: 4a20 ldr r2, [pc, #128] ; (8002d20 <BSP_LCD_DrawHLine+0xb4>)
8002c9e: 2134 movs r1, #52 ; 0x34
8002ca0: fb01 f303 mul.w r3, r1, r3
8002ca4: 4413 add r3, r2
8002ca6: 335c adds r3, #92 ; 0x5c
8002ca8: 681c ldr r4, [r3, #0]
8002caa: f7ff fed3 bl 8002a54 <BSP_LCD_GetXSize>
8002cae: 4602 mov r2, r0
8002cb0: 88bb ldrh r3, [r7, #4]
8002cb2: fb03 f202 mul.w r2, r3, r2
8002cb6: 88fb ldrh r3, [r7, #6]
8002cb8: 4413 add r3, r2
8002cba: 005b lsls r3, r3, #1
8002cbc: 4423 add r3, r4
8002cbe: 60fb str r3, [r7, #12]
8002cc0: e013 b.n 8002cea <BSP_LCD_DrawHLine+0x7e>
}
else
{ /* ARGB8888 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002cc2: 4b16 ldr r3, [pc, #88] ; (8002d1c <BSP_LCD_DrawHLine+0xb0>)
8002cc4: 681b ldr r3, [r3, #0]
8002cc6: 4a16 ldr r2, [pc, #88] ; (8002d20 <BSP_LCD_DrawHLine+0xb4>)
8002cc8: 2134 movs r1, #52 ; 0x34
8002cca: fb01 f303 mul.w r3, r1, r3
8002cce: 4413 add r3, r2
8002cd0: 335c adds r3, #92 ; 0x5c
8002cd2: 681c ldr r4, [r3, #0]
8002cd4: f7ff febe bl 8002a54 <BSP_LCD_GetXSize>
8002cd8: 4602 mov r2, r0
8002cda: 88bb ldrh r3, [r7, #4]
8002cdc: fb03 f202 mul.w r2, r3, r2
8002ce0: 88fb ldrh r3, [r7, #6]
8002ce2: 4413 add r3, r2
8002ce4: 009b lsls r3, r3, #2
8002ce6: 4423 add r3, r4
8002ce8: 60fb str r3, [r7, #12]
}
/* Write line */
LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
8002cea: 4b0c ldr r3, [pc, #48] ; (8002d1c <BSP_LCD_DrawHLine+0xb0>)
8002cec: 6818 ldr r0, [r3, #0]
8002cee: 68fc ldr r4, [r7, #12]
8002cf0: 887d ldrh r5, [r7, #2]
8002cf2: 4b0a ldr r3, [pc, #40] ; (8002d1c <BSP_LCD_DrawHLine+0xb0>)
8002cf4: 681a ldr r2, [r3, #0]
8002cf6: 490b ldr r1, [pc, #44] ; (8002d24 <BSP_LCD_DrawHLine+0xb8>)
8002cf8: 4613 mov r3, r2
8002cfa: 005b lsls r3, r3, #1
8002cfc: 4413 add r3, r2
8002cfe: 009b lsls r3, r3, #2
8002d00: 440b add r3, r1
8002d02: 681b ldr r3, [r3, #0]
8002d04: 9301 str r3, [sp, #4]
8002d06: 2300 movs r3, #0
8002d08: 9300 str r3, [sp, #0]
8002d0a: 2301 movs r3, #1
8002d0c: 462a mov r2, r5
8002d0e: 4621 mov r1, r4
8002d10: f000 fc20 bl 8003554 <LL_FillBuffer>
}
8002d14: bf00 nop
8002d16: 3710 adds r7, #16
8002d18: 46bd mov sp, r7
8002d1a: bdb0 pop {r4, r5, r7, pc}
8002d1c: 2000041c .word 0x2000041c
8002d20: 20008c34 .word 0x20008c34
8002d24: 20000420 .word 0x20000420
08002d28 <BSP_LCD_DrawCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
8002d28: b590 push {r4, r7, lr}
8002d2a: b087 sub sp, #28
8002d2c: af00 add r7, sp, #0
8002d2e: 4603 mov r3, r0
8002d30: 80fb strh r3, [r7, #6]
8002d32: 460b mov r3, r1
8002d34: 80bb strh r3, [r7, #4]
8002d36: 4613 mov r3, r2
8002d38: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
8002d3a: 887b ldrh r3, [r7, #2]
8002d3c: 005b lsls r3, r3, #1
8002d3e: f1c3 0303 rsb r3, r3, #3
8002d42: 617b str r3, [r7, #20]
current_x = 0;
8002d44: 2300 movs r3, #0
8002d46: 613b str r3, [r7, #16]
current_y = Radius;
8002d48: 887b ldrh r3, [r7, #2]
8002d4a: 60fb str r3, [r7, #12]
while (current_x <= current_y)
8002d4c: e0cf b.n 8002eee <BSP_LCD_DrawCircle+0x1c6>
{
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002d4e: 693b ldr r3, [r7, #16]
8002d50: b29a uxth r2, r3
8002d52: 88fb ldrh r3, [r7, #6]
8002d54: 4413 add r3, r2
8002d56: b298 uxth r0, r3
8002d58: 68fb ldr r3, [r7, #12]
8002d5a: b29b uxth r3, r3
8002d5c: 88ba ldrh r2, [r7, #4]
8002d5e: 1ad3 subs r3, r2, r3
8002d60: b29c uxth r4, r3
8002d62: 4b67 ldr r3, [pc, #412] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002d64: 681a ldr r2, [r3, #0]
8002d66: 4967 ldr r1, [pc, #412] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002d68: 4613 mov r3, r2
8002d6a: 005b lsls r3, r3, #1
8002d6c: 4413 add r3, r2
8002d6e: 009b lsls r3, r3, #2
8002d70: 440b add r3, r1
8002d72: 681b ldr r3, [r3, #0]
8002d74: 461a mov r2, r3
8002d76: 4621 mov r1, r4
8002d78: f000 f8c6 bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002d7c: 693b ldr r3, [r7, #16]
8002d7e: b29b uxth r3, r3
8002d80: 88fa ldrh r2, [r7, #6]
8002d82: 1ad3 subs r3, r2, r3
8002d84: b298 uxth r0, r3
8002d86: 68fb ldr r3, [r7, #12]
8002d88: b29b uxth r3, r3
8002d8a: 88ba ldrh r2, [r7, #4]
8002d8c: 1ad3 subs r3, r2, r3
8002d8e: b29c uxth r4, r3
8002d90: 4b5b ldr r3, [pc, #364] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002d92: 681a ldr r2, [r3, #0]
8002d94: 495b ldr r1, [pc, #364] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002d96: 4613 mov r3, r2
8002d98: 005b lsls r3, r3, #1
8002d9a: 4413 add r3, r2
8002d9c: 009b lsls r3, r3, #2
8002d9e: 440b add r3, r1
8002da0: 681b ldr r3, [r3, #0]
8002da2: 461a mov r2, r3
8002da4: 4621 mov r1, r4
8002da6: f000 f8af bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002daa: 68fb ldr r3, [r7, #12]
8002dac: b29a uxth r2, r3
8002dae: 88fb ldrh r3, [r7, #6]
8002db0: 4413 add r3, r2
8002db2: b298 uxth r0, r3
8002db4: 693b ldr r3, [r7, #16]
8002db6: b29b uxth r3, r3
8002db8: 88ba ldrh r2, [r7, #4]
8002dba: 1ad3 subs r3, r2, r3
8002dbc: b29c uxth r4, r3
8002dbe: 4b50 ldr r3, [pc, #320] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002dc0: 681a ldr r2, [r3, #0]
8002dc2: 4950 ldr r1, [pc, #320] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002dc4: 4613 mov r3, r2
8002dc6: 005b lsls r3, r3, #1
8002dc8: 4413 add r3, r2
8002dca: 009b lsls r3, r3, #2
8002dcc: 440b add r3, r1
8002dce: 681b ldr r3, [r3, #0]
8002dd0: 461a mov r2, r3
8002dd2: 4621 mov r1, r4
8002dd4: f000 f898 bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002dd8: 68fb ldr r3, [r7, #12]
8002dda: b29b uxth r3, r3
8002ddc: 88fa ldrh r2, [r7, #6]
8002dde: 1ad3 subs r3, r2, r3
8002de0: b298 uxth r0, r3
8002de2: 693b ldr r3, [r7, #16]
8002de4: b29b uxth r3, r3
8002de6: 88ba ldrh r2, [r7, #4]
8002de8: 1ad3 subs r3, r2, r3
8002dea: b29c uxth r4, r3
8002dec: 4b44 ldr r3, [pc, #272] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002dee: 681a ldr r2, [r3, #0]
8002df0: 4944 ldr r1, [pc, #272] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002df2: 4613 mov r3, r2
8002df4: 005b lsls r3, r3, #1
8002df6: 4413 add r3, r2
8002df8: 009b lsls r3, r3, #2
8002dfa: 440b add r3, r1
8002dfc: 681b ldr r3, [r3, #0]
8002dfe: 461a mov r2, r3
8002e00: 4621 mov r1, r4
8002e02: f000 f881 bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e06: 693b ldr r3, [r7, #16]
8002e08: b29a uxth r2, r3
8002e0a: 88fb ldrh r3, [r7, #6]
8002e0c: 4413 add r3, r2
8002e0e: b298 uxth r0, r3
8002e10: 68fb ldr r3, [r7, #12]
8002e12: b29a uxth r2, r3
8002e14: 88bb ldrh r3, [r7, #4]
8002e16: 4413 add r3, r2
8002e18: b29c uxth r4, r3
8002e1a: 4b39 ldr r3, [pc, #228] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002e1c: 681a ldr r2, [r3, #0]
8002e1e: 4939 ldr r1, [pc, #228] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002e20: 4613 mov r3, r2
8002e22: 005b lsls r3, r3, #1
8002e24: 4413 add r3, r2
8002e26: 009b lsls r3, r3, #2
8002e28: 440b add r3, r1
8002e2a: 681b ldr r3, [r3, #0]
8002e2c: 461a mov r2, r3
8002e2e: 4621 mov r1, r4
8002e30: f000 f86a bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e34: 693b ldr r3, [r7, #16]
8002e36: b29b uxth r3, r3
8002e38: 88fa ldrh r2, [r7, #6]
8002e3a: 1ad3 subs r3, r2, r3
8002e3c: b298 uxth r0, r3
8002e3e: 68fb ldr r3, [r7, #12]
8002e40: b29a uxth r2, r3
8002e42: 88bb ldrh r3, [r7, #4]
8002e44: 4413 add r3, r2
8002e46: b29c uxth r4, r3
8002e48: 4b2d ldr r3, [pc, #180] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002e4a: 681a ldr r2, [r3, #0]
8002e4c: 492d ldr r1, [pc, #180] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002e4e: 4613 mov r3, r2
8002e50: 005b lsls r3, r3, #1
8002e52: 4413 add r3, r2
8002e54: 009b lsls r3, r3, #2
8002e56: 440b add r3, r1
8002e58: 681b ldr r3, [r3, #0]
8002e5a: 461a mov r2, r3
8002e5c: 4621 mov r1, r4
8002e5e: f000 f853 bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002e62: 68fb ldr r3, [r7, #12]
8002e64: b29a uxth r2, r3
8002e66: 88fb ldrh r3, [r7, #6]
8002e68: 4413 add r3, r2
8002e6a: b298 uxth r0, r3
8002e6c: 693b ldr r3, [r7, #16]
8002e6e: b29a uxth r2, r3
8002e70: 88bb ldrh r3, [r7, #4]
8002e72: 4413 add r3, r2
8002e74: b29c uxth r4, r3
8002e76: 4b22 ldr r3, [pc, #136] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002e78: 681a ldr r2, [r3, #0]
8002e7a: 4922 ldr r1, [pc, #136] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002e7c: 4613 mov r3, r2
8002e7e: 005b lsls r3, r3, #1
8002e80: 4413 add r3, r2
8002e82: 009b lsls r3, r3, #2
8002e84: 440b add r3, r1
8002e86: 681b ldr r3, [r3, #0]
8002e88: 461a mov r2, r3
8002e8a: 4621 mov r1, r4
8002e8c: f000 f83c bl 8002f08 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002e90: 68fb ldr r3, [r7, #12]
8002e92: b29b uxth r3, r3
8002e94: 88fa ldrh r2, [r7, #6]
8002e96: 1ad3 subs r3, r2, r3
8002e98: b298 uxth r0, r3
8002e9a: 693b ldr r3, [r7, #16]
8002e9c: b29a uxth r2, r3
8002e9e: 88bb ldrh r3, [r7, #4]
8002ea0: 4413 add r3, r2
8002ea2: b29c uxth r4, r3
8002ea4: 4b16 ldr r3, [pc, #88] ; (8002f00 <BSP_LCD_DrawCircle+0x1d8>)
8002ea6: 681a ldr r2, [r3, #0]
8002ea8: 4916 ldr r1, [pc, #88] ; (8002f04 <BSP_LCD_DrawCircle+0x1dc>)
8002eaa: 4613 mov r3, r2
8002eac: 005b lsls r3, r3, #1
8002eae: 4413 add r3, r2
8002eb0: 009b lsls r3, r3, #2
8002eb2: 440b add r3, r1
8002eb4: 681b ldr r3, [r3, #0]
8002eb6: 461a mov r2, r3
8002eb8: 4621 mov r1, r4
8002eba: f000 f825 bl 8002f08 <BSP_LCD_DrawPixel>
if (decision < 0)
8002ebe: 697b ldr r3, [r7, #20]
8002ec0: 2b00 cmp r3, #0
8002ec2: da06 bge.n 8002ed2 <BSP_LCD_DrawCircle+0x1aa>
{
decision += (current_x << 2) + 6;
8002ec4: 693b ldr r3, [r7, #16]
8002ec6: 009a lsls r2, r3, #2
8002ec8: 697b ldr r3, [r7, #20]
8002eca: 4413 add r3, r2
8002ecc: 3306 adds r3, #6
8002ece: 617b str r3, [r7, #20]
8002ed0: e00a b.n 8002ee8 <BSP_LCD_DrawCircle+0x1c0>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
8002ed2: 693a ldr r2, [r7, #16]
8002ed4: 68fb ldr r3, [r7, #12]
8002ed6: 1ad3 subs r3, r2, r3
8002ed8: 009a lsls r2, r3, #2
8002eda: 697b ldr r3, [r7, #20]
8002edc: 4413 add r3, r2
8002ede: 330a adds r3, #10
8002ee0: 617b str r3, [r7, #20]
current_y--;
8002ee2: 68fb ldr r3, [r7, #12]
8002ee4: 3b01 subs r3, #1
8002ee6: 60fb str r3, [r7, #12]
}
current_x++;
8002ee8: 693b ldr r3, [r7, #16]
8002eea: 3301 adds r3, #1
8002eec: 613b str r3, [r7, #16]
while (current_x <= current_y)
8002eee: 693a ldr r2, [r7, #16]
8002ef0: 68fb ldr r3, [r7, #12]
8002ef2: 429a cmp r2, r3
8002ef4: f67f af2b bls.w 8002d4e <BSP_LCD_DrawCircle+0x26>
}
}
8002ef8: bf00 nop
8002efa: 371c adds r7, #28
8002efc: 46bd mov sp, r7
8002efe: bd90 pop {r4, r7, pc}
8002f00: 2000041c .word 0x2000041c
8002f04: 20000420 .word 0x20000420
08002f08 <BSP_LCD_DrawPixel>:
* @param Ypos: Y position
* @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)
* @retval None
*/
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
{
8002f08: b5b0 push {r4, r5, r7, lr}
8002f0a: b082 sub sp, #8
8002f0c: af00 add r7, sp, #0
8002f0e: 4603 mov r3, r0
8002f10: 603a str r2, [r7, #0]
8002f12: 80fb strh r3, [r7, #6]
8002f14: 460b mov r3, r1
8002f16: 80bb strh r3, [r7, #4]
/* Write data value to all SDRAM memory */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002f18: 4b1d ldr r3, [pc, #116] ; (8002f90 <BSP_LCD_DrawPixel+0x88>)
8002f1a: 681b ldr r3, [r3, #0]
8002f1c: 4a1d ldr r2, [pc, #116] ; (8002f94 <BSP_LCD_DrawPixel+0x8c>)
8002f1e: 2134 movs r1, #52 ; 0x34
8002f20: fb01 f303 mul.w r3, r1, r3
8002f24: 4413 add r3, r2
8002f26: 3348 adds r3, #72 ; 0x48
8002f28: 681b ldr r3, [r3, #0]
8002f2a: 2b02 cmp r3, #2
8002f2c: d116 bne.n 8002f5c <BSP_LCD_DrawPixel+0x54>
{ /* RGB565 format */
*(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code;
8002f2e: 4b18 ldr r3, [pc, #96] ; (8002f90 <BSP_LCD_DrawPixel+0x88>)
8002f30: 681b ldr r3, [r3, #0]
8002f32: 4a18 ldr r2, [pc, #96] ; (8002f94 <BSP_LCD_DrawPixel+0x8c>)
8002f34: 2134 movs r1, #52 ; 0x34
8002f36: fb01 f303 mul.w r3, r1, r3
8002f3a: 4413 add r3, r2
8002f3c: 335c adds r3, #92 ; 0x5c
8002f3e: 681c ldr r4, [r3, #0]
8002f40: 88bd ldrh r5, [r7, #4]
8002f42: f7ff fd87 bl 8002a54 <BSP_LCD_GetXSize>
8002f46: 4603 mov r3, r0
8002f48: fb03 f205 mul.w r2, r3, r5
8002f4c: 88fb ldrh r3, [r7, #6]
8002f4e: 4413 add r3, r2
8002f50: 005b lsls r3, r3, #1
8002f52: 4423 add r3, r4
8002f54: 683a ldr r2, [r7, #0]
8002f56: b292 uxth r2, r2
8002f58: 801a strh r2, [r3, #0]
}
else
{ /* ARGB8888 format */
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
}
}
8002f5a: e015 b.n 8002f88 <BSP_LCD_DrawPixel+0x80>
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
8002f5c: 4b0c ldr r3, [pc, #48] ; (8002f90 <BSP_LCD_DrawPixel+0x88>)
8002f5e: 681b ldr r3, [r3, #0]
8002f60: 4a0c ldr r2, [pc, #48] ; (8002f94 <BSP_LCD_DrawPixel+0x8c>)
8002f62: 2134 movs r1, #52 ; 0x34
8002f64: fb01 f303 mul.w r3, r1, r3
8002f68: 4413 add r3, r2
8002f6a: 335c adds r3, #92 ; 0x5c
8002f6c: 681c ldr r4, [r3, #0]
8002f6e: 88bd ldrh r5, [r7, #4]
8002f70: f7ff fd70 bl 8002a54 <BSP_LCD_GetXSize>
8002f74: 4603 mov r3, r0
8002f76: fb03 f205 mul.w r2, r3, r5
8002f7a: 88fb ldrh r3, [r7, #6]
8002f7c: 4413 add r3, r2
8002f7e: 009b lsls r3, r3, #2
8002f80: 4423 add r3, r4
8002f82: 461a mov r2, r3
8002f84: 683b ldr r3, [r7, #0]
8002f86: 6013 str r3, [r2, #0]
}
8002f88: bf00 nop
8002f8a: 3708 adds r7, #8
8002f8c: 46bd mov sp, r7
8002f8e: bdb0 pop {r4, r5, r7, pc}
8002f90: 2000041c .word 0x2000041c
8002f94: 20008c34 .word 0x20008c34
08002f98 <BSP_LCD_DrawBitmap>:
* @param Ypos: Bmp Y position in the LCD
* @param pbmp: Pointer to Bmp picture address in the internal Flash
* @retval None
*/
void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
{
8002f98: b590 push {r4, r7, lr}
8002f9a: b08b sub sp, #44 ; 0x2c
8002f9c: af00 add r7, sp, #0
8002f9e: 60f8 str r0, [r7, #12]
8002fa0: 60b9 str r1, [r7, #8]
8002fa2: 607a str r2, [r7, #4]
uint32_t index = 0, width = 0, height = 0, bit_pixel = 0;
8002fa4: 2300 movs r3, #0
8002fa6: 627b str r3, [r7, #36] ; 0x24
8002fa8: 2300 movs r3, #0
8002faa: 61bb str r3, [r7, #24]
8002fac: 2300 movs r3, #0
8002fae: 617b str r3, [r7, #20]
8002fb0: 2300 movs r3, #0
8002fb2: 613b str r3, [r7, #16]
uint32_t address;
uint32_t input_color_mode = 0;
8002fb4: 2300 movs r3, #0
8002fb6: 61fb str r3, [r7, #28]
/* Get bitmap data address offset */
index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24);
8002fb8: 687b ldr r3, [r7, #4]
8002fba: 330a adds r3, #10
8002fbc: 781b ldrb r3, [r3, #0]
8002fbe: 461a mov r2, r3
8002fc0: 687b ldr r3, [r7, #4]
8002fc2: 330b adds r3, #11
8002fc4: 781b ldrb r3, [r3, #0]
8002fc6: 021b lsls r3, r3, #8
8002fc8: 441a add r2, r3
8002fca: 687b ldr r3, [r7, #4]
8002fcc: 330c adds r3, #12
8002fce: 781b ldrb r3, [r3, #0]
8002fd0: 041b lsls r3, r3, #16
8002fd2: 441a add r2, r3
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 330d adds r3, #13
8002fd8: 781b ldrb r3, [r3, #0]
8002fda: 061b lsls r3, r3, #24
8002fdc: 4413 add r3, r2
8002fde: 627b str r3, [r7, #36] ; 0x24
/* Read bitmap width */
width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16) + (pbmp[21] << 24);
8002fe0: 687b ldr r3, [r7, #4]
8002fe2: 3312 adds r3, #18
8002fe4: 781b ldrb r3, [r3, #0]
8002fe6: 461a mov r2, r3
8002fe8: 687b ldr r3, [r7, #4]
8002fea: 3313 adds r3, #19
8002fec: 781b ldrb r3, [r3, #0]
8002fee: 021b lsls r3, r3, #8
8002ff0: 441a add r2, r3
8002ff2: 687b ldr r3, [r7, #4]
8002ff4: 3314 adds r3, #20
8002ff6: 781b ldrb r3, [r3, #0]
8002ff8: 041b lsls r3, r3, #16
8002ffa: 441a add r2, r3
8002ffc: 687b ldr r3, [r7, #4]
8002ffe: 3315 adds r3, #21
8003000: 781b ldrb r3, [r3, #0]
8003002: 061b lsls r3, r3, #24
8003004: 4413 add r3, r2
8003006: 61bb str r3, [r7, #24]
/* Read bitmap height */
height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16) + (pbmp[25] << 24);
8003008: 687b ldr r3, [r7, #4]
800300a: 3316 adds r3, #22
800300c: 781b ldrb r3, [r3, #0]
800300e: 461a mov r2, r3
8003010: 687b ldr r3, [r7, #4]
8003012: 3317 adds r3, #23
8003014: 781b ldrb r3, [r3, #0]
8003016: 021b lsls r3, r3, #8
8003018: 441a add r2, r3
800301a: 687b ldr r3, [r7, #4]
800301c: 3318 adds r3, #24
800301e: 781b ldrb r3, [r3, #0]
8003020: 041b lsls r3, r3, #16
8003022: 441a add r2, r3
8003024: 687b ldr r3, [r7, #4]
8003026: 3319 adds r3, #25
8003028: 781b ldrb r3, [r3, #0]
800302a: 061b lsls r3, r3, #24
800302c: 4413 add r3, r2
800302e: 617b str r3, [r7, #20]
/* Read bit/pixel */
bit_pixel = pbmp[28] + (pbmp[29] << 8);
8003030: 687b ldr r3, [r7, #4]
8003032: 331c adds r3, #28
8003034: 781b ldrb r3, [r3, #0]
8003036: 461a mov r2, r3
8003038: 687b ldr r3, [r7, #4]
800303a: 331d adds r3, #29
800303c: 781b ldrb r3, [r3, #0]
800303e: 021b lsls r3, r3, #8
8003040: 4413 add r3, r2
8003042: 613b str r3, [r7, #16]
/* Set the address */
address = hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4));
8003044: 4b2a ldr r3, [pc, #168] ; (80030f0 <BSP_LCD_DrawBitmap+0x158>)
8003046: 681b ldr r3, [r3, #0]
8003048: 4a2a ldr r2, [pc, #168] ; (80030f4 <BSP_LCD_DrawBitmap+0x15c>)
800304a: 2134 movs r1, #52 ; 0x34
800304c: fb01 f303 mul.w r3, r1, r3
8003050: 4413 add r3, r2
8003052: 335c adds r3, #92 ; 0x5c
8003054: 681c ldr r4, [r3, #0]
8003056: f7ff fcfd bl 8002a54 <BSP_LCD_GetXSize>
800305a: 4602 mov r2, r0
800305c: 68bb ldr r3, [r7, #8]
800305e: fb03 f202 mul.w r2, r3, r2
8003062: 68fb ldr r3, [r7, #12]
8003064: 4413 add r3, r2
8003066: 009b lsls r3, r3, #2
8003068: 4423 add r3, r4
800306a: 623b str r3, [r7, #32]
/* Get the layer pixel format */
if ((bit_pixel/8) == 4)
800306c: 693b ldr r3, [r7, #16]
800306e: 3b20 subs r3, #32
8003070: 2b07 cmp r3, #7
8003072: d802 bhi.n 800307a <BSP_LCD_DrawBitmap+0xe2>
{
input_color_mode = CM_ARGB8888;
8003074: 2300 movs r3, #0
8003076: 61fb str r3, [r7, #28]
8003078: e008 b.n 800308c <BSP_LCD_DrawBitmap+0xf4>
}
else if ((bit_pixel/8) == 2)
800307a: 693b ldr r3, [r7, #16]
800307c: 3b10 subs r3, #16
800307e: 2b07 cmp r3, #7
8003080: d802 bhi.n 8003088 <BSP_LCD_DrawBitmap+0xf0>
{
input_color_mode = CM_RGB565;
8003082: 2302 movs r3, #2
8003084: 61fb str r3, [r7, #28]
8003086: e001 b.n 800308c <BSP_LCD_DrawBitmap+0xf4>
}
else
{
input_color_mode = CM_RGB888;
8003088: 2301 movs r3, #1
800308a: 61fb str r3, [r7, #28]
}
/* Bypass the bitmap header */
pbmp += (index + (width * (height - 1) * (bit_pixel/8)));
800308c: 697b ldr r3, [r7, #20]
800308e: 3b01 subs r3, #1
8003090: 69ba ldr r2, [r7, #24]
8003092: fb02 f303 mul.w r3, r2, r3
8003096: 693a ldr r2, [r7, #16]
8003098: 08d2 lsrs r2, r2, #3
800309a: fb02 f203 mul.w r2, r2, r3
800309e: 6a7b ldr r3, [r7, #36] ; 0x24
80030a0: 4413 add r3, r2
80030a2: 687a ldr r2, [r7, #4]
80030a4: 4413 add r3, r2
80030a6: 607b str r3, [r7, #4]
/* Convert picture to ARGB8888 pixel format */
for(index=0; index < height; index++)
80030a8: 2300 movs r3, #0
80030aa: 627b str r3, [r7, #36] ; 0x24
80030ac: e018 b.n 80030e0 <BSP_LCD_DrawBitmap+0x148>
{
/* Pixel format conversion */
LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)address, width, input_color_mode);
80030ae: 6a39 ldr r1, [r7, #32]
80030b0: 69fb ldr r3, [r7, #28]
80030b2: 69ba ldr r2, [r7, #24]
80030b4: 6878 ldr r0, [r7, #4]
80030b6: f000 fa99 bl 80035ec <LL_ConvertLineToARGB8888>
/* Increment the source and destination buffers */
address+= (BSP_LCD_GetXSize()*4);
80030ba: f7ff fccb bl 8002a54 <BSP_LCD_GetXSize>
80030be: 4603 mov r3, r0
80030c0: 009b lsls r3, r3, #2
80030c2: 6a3a ldr r2, [r7, #32]
80030c4: 4413 add r3, r2
80030c6: 623b str r3, [r7, #32]
pbmp -= width*(bit_pixel/8);
80030c8: 693b ldr r3, [r7, #16]
80030ca: 08db lsrs r3, r3, #3
80030cc: 69ba ldr r2, [r7, #24]
80030ce: fb02 f303 mul.w r3, r2, r3
80030d2: 425b negs r3, r3
80030d4: 687a ldr r2, [r7, #4]
80030d6: 4413 add r3, r2
80030d8: 607b str r3, [r7, #4]
for(index=0; index < height; index++)
80030da: 6a7b ldr r3, [r7, #36] ; 0x24
80030dc: 3301 adds r3, #1
80030de: 627b str r3, [r7, #36] ; 0x24
80030e0: 6a7a ldr r2, [r7, #36] ; 0x24
80030e2: 697b ldr r3, [r7, #20]
80030e4: 429a cmp r2, r3
80030e6: d3e2 bcc.n 80030ae <BSP_LCD_DrawBitmap+0x116>
}
}
80030e8: bf00 nop
80030ea: 372c adds r7, #44 ; 0x2c
80030ec: 46bd mov sp, r7
80030ee: bd90 pop {r4, r7, pc}
80030f0: 2000041c .word 0x2000041c
80030f4: 20008c34 .word 0x20008c34
080030f8 <BSP_LCD_FillRect>:
* @param Width: Rectangle width
* @param Height: Rectangle height
* @retval None
*/
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
80030f8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
80030fc: b086 sub sp, #24
80030fe: af02 add r7, sp, #8
8003100: 4604 mov r4, r0
8003102: 4608 mov r0, r1
8003104: 4611 mov r1, r2
8003106: 461a mov r2, r3
8003108: 4623 mov r3, r4
800310a: 80fb strh r3, [r7, #6]
800310c: 4603 mov r3, r0
800310e: 80bb strh r3, [r7, #4]
8003110: 460b mov r3, r1
8003112: 807b strh r3, [r7, #2]
8003114: 4613 mov r3, r2
8003116: 803b strh r3, [r7, #0]
uint32_t x_address = 0;
8003118: 2300 movs r3, #0
800311a: 60fb str r3, [r7, #12]
/* Set the text color */
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
800311c: 4b30 ldr r3, [pc, #192] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
800311e: 681a ldr r2, [r3, #0]
8003120: 4930 ldr r1, [pc, #192] ; (80031e4 <BSP_LCD_FillRect+0xec>)
8003122: 4613 mov r3, r2
8003124: 005b lsls r3, r3, #1
8003126: 4413 add r3, r2
8003128: 009b lsls r3, r3, #2
800312a: 440b add r3, r1
800312c: 681b ldr r3, [r3, #0]
800312e: 4618 mov r0, r3
8003130: f7ff fd28 bl 8002b84 <BSP_LCD_SetTextColor>
/* Get the rectangle start address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8003134: 4b2a ldr r3, [pc, #168] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
8003136: 681b ldr r3, [r3, #0]
8003138: 4a2b ldr r2, [pc, #172] ; (80031e8 <BSP_LCD_FillRect+0xf0>)
800313a: 2134 movs r1, #52 ; 0x34
800313c: fb01 f303 mul.w r3, r1, r3
8003140: 4413 add r3, r2
8003142: 3348 adds r3, #72 ; 0x48
8003144: 681b ldr r3, [r3, #0]
8003146: 2b02 cmp r3, #2
8003148: d114 bne.n 8003174 <BSP_LCD_FillRect+0x7c>
{ /* RGB565 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
800314a: 4b25 ldr r3, [pc, #148] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
800314c: 681b ldr r3, [r3, #0]
800314e: 4a26 ldr r2, [pc, #152] ; (80031e8 <BSP_LCD_FillRect+0xf0>)
8003150: 2134 movs r1, #52 ; 0x34
8003152: fb01 f303 mul.w r3, r1, r3
8003156: 4413 add r3, r2
8003158: 335c adds r3, #92 ; 0x5c
800315a: 681c ldr r4, [r3, #0]
800315c: f7ff fc7a bl 8002a54 <BSP_LCD_GetXSize>
8003160: 4602 mov r2, r0
8003162: 88bb ldrh r3, [r7, #4]
8003164: fb03 f202 mul.w r2, r3, r2
8003168: 88fb ldrh r3, [r7, #6]
800316a: 4413 add r3, r2
800316c: 005b lsls r3, r3, #1
800316e: 4423 add r3, r4
8003170: 60fb str r3, [r7, #12]
8003172: e013 b.n 800319c <BSP_LCD_FillRect+0xa4>
}
else
{ /* ARGB8888 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
8003174: 4b1a ldr r3, [pc, #104] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
8003176: 681b ldr r3, [r3, #0]
8003178: 4a1b ldr r2, [pc, #108] ; (80031e8 <BSP_LCD_FillRect+0xf0>)
800317a: 2134 movs r1, #52 ; 0x34
800317c: fb01 f303 mul.w r3, r1, r3
8003180: 4413 add r3, r2
8003182: 335c adds r3, #92 ; 0x5c
8003184: 681c ldr r4, [r3, #0]
8003186: f7ff fc65 bl 8002a54 <BSP_LCD_GetXSize>
800318a: 4602 mov r2, r0
800318c: 88bb ldrh r3, [r7, #4]
800318e: fb03 f202 mul.w r2, r3, r2
8003192: 88fb ldrh r3, [r7, #6]
8003194: 4413 add r3, r2
8003196: 009b lsls r3, r3, #2
8003198: 4423 add r3, r4
800319a: 60fb str r3, [r7, #12]
}
/* Fill the rectangle */
LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);
800319c: 4b10 ldr r3, [pc, #64] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
800319e: 681c ldr r4, [r3, #0]
80031a0: 68fd ldr r5, [r7, #12]
80031a2: 887e ldrh r6, [r7, #2]
80031a4: f8b7 8000 ldrh.w r8, [r7]
80031a8: f7ff fc54 bl 8002a54 <BSP_LCD_GetXSize>
80031ac: 4602 mov r2, r0
80031ae: 887b ldrh r3, [r7, #2]
80031b0: 1ad1 subs r1, r2, r3
80031b2: 4b0b ldr r3, [pc, #44] ; (80031e0 <BSP_LCD_FillRect+0xe8>)
80031b4: 681a ldr r2, [r3, #0]
80031b6: 480b ldr r0, [pc, #44] ; (80031e4 <BSP_LCD_FillRect+0xec>)
80031b8: 4613 mov r3, r2
80031ba: 005b lsls r3, r3, #1
80031bc: 4413 add r3, r2
80031be: 009b lsls r3, r3, #2
80031c0: 4403 add r3, r0
80031c2: 681b ldr r3, [r3, #0]
80031c4: 9301 str r3, [sp, #4]
80031c6: 9100 str r1, [sp, #0]
80031c8: 4643 mov r3, r8
80031ca: 4632 mov r2, r6
80031cc: 4629 mov r1, r5
80031ce: 4620 mov r0, r4
80031d0: f000 f9c0 bl 8003554 <LL_FillBuffer>
}
80031d4: bf00 nop
80031d6: 3710 adds r7, #16
80031d8: 46bd mov sp, r7
80031da: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80031de: bf00 nop
80031e0: 2000041c .word 0x2000041c
80031e4: 20000420 .word 0x20000420
80031e8: 20008c34 .word 0x20008c34
080031ec <BSP_LCD_FillCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
80031ec: b580 push {r7, lr}
80031ee: b086 sub sp, #24
80031f0: af00 add r7, sp, #0
80031f2: 4603 mov r3, r0
80031f4: 80fb strh r3, [r7, #6]
80031f6: 460b mov r3, r1
80031f8: 80bb strh r3, [r7, #4]
80031fa: 4613 mov r3, r2
80031fc: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
80031fe: 887b ldrh r3, [r7, #2]
8003200: 005b lsls r3, r3, #1
8003202: f1c3 0303 rsb r3, r3, #3
8003206: 617b str r3, [r7, #20]
current_x = 0;
8003208: 2300 movs r3, #0
800320a: 613b str r3, [r7, #16]
current_y = Radius;
800320c: 887b ldrh r3, [r7, #2]
800320e: 60fb str r3, [r7, #12]
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8003210: 4b44 ldr r3, [pc, #272] ; (8003324 <BSP_LCD_FillCircle+0x138>)
8003212: 681a ldr r2, [r3, #0]
8003214: 4944 ldr r1, [pc, #272] ; (8003328 <BSP_LCD_FillCircle+0x13c>)
8003216: 4613 mov r3, r2
8003218: 005b lsls r3, r3, #1
800321a: 4413 add r3, r2
800321c: 009b lsls r3, r3, #2
800321e: 440b add r3, r1
8003220: 681b ldr r3, [r3, #0]
8003222: 4618 mov r0, r3
8003224: f7ff fcae bl 8002b84 <BSP_LCD_SetTextColor>
while (current_x <= current_y)
8003228: e061 b.n 80032ee <BSP_LCD_FillCircle+0x102>
{
if(current_y > 0)
800322a: 68fb ldr r3, [r7, #12]
800322c: 2b00 cmp r3, #0
800322e: d021 beq.n 8003274 <BSP_LCD_FillCircle+0x88>
{
BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);
8003230: 68fb ldr r3, [r7, #12]
8003232: b29b uxth r3, r3
8003234: 88fa ldrh r2, [r7, #6]
8003236: 1ad3 subs r3, r2, r3
8003238: b298 uxth r0, r3
800323a: 693b ldr r3, [r7, #16]
800323c: b29a uxth r2, r3
800323e: 88bb ldrh r3, [r7, #4]
8003240: 4413 add r3, r2
8003242: b299 uxth r1, r3
8003244: 68fb ldr r3, [r7, #12]
8003246: b29b uxth r3, r3
8003248: 005b lsls r3, r3, #1
800324a: b29b uxth r3, r3
800324c: 461a mov r2, r3
800324e: f7ff fd0d bl 8002c6c <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);
8003252: 68fb ldr r3, [r7, #12]
8003254: b29b uxth r3, r3
8003256: 88fa ldrh r2, [r7, #6]
8003258: 1ad3 subs r3, r2, r3
800325a: b298 uxth r0, r3
800325c: 693b ldr r3, [r7, #16]
800325e: b29b uxth r3, r3
8003260: 88ba ldrh r2, [r7, #4]
8003262: 1ad3 subs r3, r2, r3
8003264: b299 uxth r1, r3
8003266: 68fb ldr r3, [r7, #12]
8003268: b29b uxth r3, r3
800326a: 005b lsls r3, r3, #1
800326c: b29b uxth r3, r3
800326e: 461a mov r2, r3
8003270: f7ff fcfc bl 8002c6c <BSP_LCD_DrawHLine>
}
if(current_x > 0)
8003274: 693b ldr r3, [r7, #16]
8003276: 2b00 cmp r3, #0
8003278: d021 beq.n 80032be <BSP_LCD_FillCircle+0xd2>
{
BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);
800327a: 693b ldr r3, [r7, #16]
800327c: b29b uxth r3, r3
800327e: 88fa ldrh r2, [r7, #6]
8003280: 1ad3 subs r3, r2, r3
8003282: b298 uxth r0, r3
8003284: 68fb ldr r3, [r7, #12]
8003286: b29b uxth r3, r3
8003288: 88ba ldrh r2, [r7, #4]
800328a: 1ad3 subs r3, r2, r3
800328c: b299 uxth r1, r3
800328e: 693b ldr r3, [r7, #16]
8003290: b29b uxth r3, r3
8003292: 005b lsls r3, r3, #1
8003294: b29b uxth r3, r3
8003296: 461a mov r2, r3
8003298: f7ff fce8 bl 8002c6c <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);
800329c: 693b ldr r3, [r7, #16]
800329e: b29b uxth r3, r3
80032a0: 88fa ldrh r2, [r7, #6]
80032a2: 1ad3 subs r3, r2, r3
80032a4: b298 uxth r0, r3
80032a6: 68fb ldr r3, [r7, #12]
80032a8: b29a uxth r2, r3
80032aa: 88bb ldrh r3, [r7, #4]
80032ac: 4413 add r3, r2
80032ae: b299 uxth r1, r3
80032b0: 693b ldr r3, [r7, #16]
80032b2: b29b uxth r3, r3
80032b4: 005b lsls r3, r3, #1
80032b6: b29b uxth r3, r3
80032b8: 461a mov r2, r3
80032ba: f7ff fcd7 bl 8002c6c <BSP_LCD_DrawHLine>
}
if (decision < 0)
80032be: 697b ldr r3, [r7, #20]
80032c0: 2b00 cmp r3, #0
80032c2: da06 bge.n 80032d2 <BSP_LCD_FillCircle+0xe6>
{
decision += (current_x << 2) + 6;
80032c4: 693b ldr r3, [r7, #16]
80032c6: 009a lsls r2, r3, #2
80032c8: 697b ldr r3, [r7, #20]
80032ca: 4413 add r3, r2
80032cc: 3306 adds r3, #6
80032ce: 617b str r3, [r7, #20]
80032d0: e00a b.n 80032e8 <BSP_LCD_FillCircle+0xfc>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
80032d2: 693a ldr r2, [r7, #16]
80032d4: 68fb ldr r3, [r7, #12]
80032d6: 1ad3 subs r3, r2, r3
80032d8: 009a lsls r2, r3, #2
80032da: 697b ldr r3, [r7, #20]
80032dc: 4413 add r3, r2
80032de: 330a adds r3, #10
80032e0: 617b str r3, [r7, #20]
current_y--;
80032e2: 68fb ldr r3, [r7, #12]
80032e4: 3b01 subs r3, #1
80032e6: 60fb str r3, [r7, #12]
}
current_x++;
80032e8: 693b ldr r3, [r7, #16]
80032ea: 3301 adds r3, #1
80032ec: 613b str r3, [r7, #16]
while (current_x <= current_y)
80032ee: 693a ldr r2, [r7, #16]
80032f0: 68fb ldr r3, [r7, #12]
80032f2: 429a cmp r2, r3
80032f4: d999 bls.n 800322a <BSP_LCD_FillCircle+0x3e>
}
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
80032f6: 4b0b ldr r3, [pc, #44] ; (8003324 <BSP_LCD_FillCircle+0x138>)
80032f8: 681a ldr r2, [r3, #0]
80032fa: 490b ldr r1, [pc, #44] ; (8003328 <BSP_LCD_FillCircle+0x13c>)
80032fc: 4613 mov r3, r2
80032fe: 005b lsls r3, r3, #1
8003300: 4413 add r3, r2
8003302: 009b lsls r3, r3, #2
8003304: 440b add r3, r1
8003306: 681b ldr r3, [r3, #0]
8003308: 4618 mov r0, r3
800330a: f7ff fc3b bl 8002b84 <BSP_LCD_SetTextColor>
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
800330e: 887a ldrh r2, [r7, #2]
8003310: 88b9 ldrh r1, [r7, #4]
8003312: 88fb ldrh r3, [r7, #6]
8003314: 4618 mov r0, r3
8003316: f7ff fd07 bl 8002d28 <BSP_LCD_DrawCircle>
}
800331a: bf00 nop
800331c: 3718 adds r7, #24
800331e: 46bd mov sp, r7
8003320: bd80 pop {r7, pc}
8003322: bf00 nop
8003324: 2000041c .word 0x2000041c
8003328: 20000420 .word 0x20000420
0800332c <BSP_LCD_DisplayOn>:
/**
* @brief Enables the display.
* @retval None
*/
void BSP_LCD_DisplayOn(void)
{
800332c: b580 push {r7, lr}
800332e: af00 add r7, sp, #0
/* Display On */
__HAL_LTDC_ENABLE(&hLtdcHandler);
8003330: 4b0a ldr r3, [pc, #40] ; (800335c <BSP_LCD_DisplayOn+0x30>)
8003332: 681b ldr r3, [r3, #0]
8003334: 699a ldr r2, [r3, #24]
8003336: 4b09 ldr r3, [pc, #36] ; (800335c <BSP_LCD_DisplayOn+0x30>)
8003338: 681b ldr r3, [r3, #0]
800333a: f042 0201 orr.w r2, r2, #1
800333e: 619a str r2, [r3, #24]
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */
8003340: 2201 movs r2, #1
8003342: f44f 5180 mov.w r1, #4096 ; 0x1000
8003346: 4806 ldr r0, [pc, #24] ; (8003360 <BSP_LCD_DisplayOn+0x34>)
8003348: f004 f940 bl 80075cc <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */
800334c: 2201 movs r2, #1
800334e: 2108 movs r1, #8
8003350: 4804 ldr r0, [pc, #16] ; (8003364 <BSP_LCD_DisplayOn+0x38>)
8003352: f004 f93b bl 80075cc <HAL_GPIO_WritePin>
}
8003356: bf00 nop
8003358: bd80 pop {r7, pc}
800335a: bf00 nop
800335c: 20008c34 .word 0x20008c34
8003360: 40022000 .word 0x40022000
8003364: 40022800 .word 0x40022800
08003368 <BSP_LCD_MspInit>:
* @param hltdc: LTDC handle
* @param Params
* @retval None
*/
__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
{
8003368: b580 push {r7, lr}
800336a: b090 sub sp, #64 ; 0x40
800336c: af00 add r7, sp, #0
800336e: 6078 str r0, [r7, #4]
8003370: 6039 str r1, [r7, #0]
GPIO_InitTypeDef gpio_init_structure;
/* Enable the LTDC and DMA2D clocks */
__HAL_RCC_LTDC_CLK_ENABLE();
8003372: 4b64 ldr r3, [pc, #400] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003374: 6c5b ldr r3, [r3, #68] ; 0x44
8003376: 4a63 ldr r2, [pc, #396] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003378: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800337c: 6453 str r3, [r2, #68] ; 0x44
800337e: 4b61 ldr r3, [pc, #388] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003380: 6c5b ldr r3, [r3, #68] ; 0x44
8003382: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003386: 62bb str r3, [r7, #40] ; 0x28
8003388: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_DMA2D_CLK_ENABLE();
800338a: 4b5e ldr r3, [pc, #376] ; (8003504 <BSP_LCD_MspInit+0x19c>)
800338c: 6b1b ldr r3, [r3, #48] ; 0x30
800338e: 4a5d ldr r2, [pc, #372] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003390: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8003394: 6313 str r3, [r2, #48] ; 0x30
8003396: 4b5b ldr r3, [pc, #364] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003398: 6b1b ldr r3, [r3, #48] ; 0x30
800339a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
800339e: 627b str r3, [r7, #36] ; 0x24
80033a0: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOE_CLK_ENABLE();
80033a2: 4b58 ldr r3, [pc, #352] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033a4: 6b1b ldr r3, [r3, #48] ; 0x30
80033a6: 4a57 ldr r2, [pc, #348] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033a8: f043 0310 orr.w r3, r3, #16
80033ac: 6313 str r3, [r2, #48] ; 0x30
80033ae: 4b55 ldr r3, [pc, #340] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033b0: 6b1b ldr r3, [r3, #48] ; 0x30
80033b2: f003 0310 and.w r3, r3, #16
80033b6: 623b str r3, [r7, #32]
80033b8: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOG_CLK_ENABLE();
80033ba: 4b52 ldr r3, [pc, #328] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033bc: 6b1b ldr r3, [r3, #48] ; 0x30
80033be: 4a51 ldr r2, [pc, #324] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033c0: f043 0340 orr.w r3, r3, #64 ; 0x40
80033c4: 6313 str r3, [r2, #48] ; 0x30
80033c6: 4b4f ldr r3, [pc, #316] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033c8: 6b1b ldr r3, [r3, #48] ; 0x30
80033ca: f003 0340 and.w r3, r3, #64 ; 0x40
80033ce: 61fb str r3, [r7, #28]
80033d0: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOI_CLK_ENABLE();
80033d2: 4b4c ldr r3, [pc, #304] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033d4: 6b1b ldr r3, [r3, #48] ; 0x30
80033d6: 4a4b ldr r2, [pc, #300] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033d8: f443 7380 orr.w r3, r3, #256 ; 0x100
80033dc: 6313 str r3, [r2, #48] ; 0x30
80033de: 4b49 ldr r3, [pc, #292] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033e0: 6b1b ldr r3, [r3, #48] ; 0x30
80033e2: f403 7380 and.w r3, r3, #256 ; 0x100
80033e6: 61bb str r3, [r7, #24]
80033e8: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOJ_CLK_ENABLE();
80033ea: 4b46 ldr r3, [pc, #280] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033ec: 6b1b ldr r3, [r3, #48] ; 0x30
80033ee: 4a45 ldr r2, [pc, #276] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033f0: f443 7300 orr.w r3, r3, #512 ; 0x200
80033f4: 6313 str r3, [r2, #48] ; 0x30
80033f6: 4b43 ldr r3, [pc, #268] ; (8003504 <BSP_LCD_MspInit+0x19c>)
80033f8: 6b1b ldr r3, [r3, #48] ; 0x30
80033fa: f403 7300 and.w r3, r3, #512 ; 0x200
80033fe: 617b str r3, [r7, #20]
8003400: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOK_CLK_ENABLE();
8003402: 4b40 ldr r3, [pc, #256] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003404: 6b1b ldr r3, [r3, #48] ; 0x30
8003406: 4a3f ldr r2, [pc, #252] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003408: f443 6380 orr.w r3, r3, #1024 ; 0x400
800340c: 6313 str r3, [r2, #48] ; 0x30
800340e: 4b3d ldr r3, [pc, #244] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003410: 6b1b ldr r3, [r3, #48] ; 0x30
8003412: f403 6380 and.w r3, r3, #1024 ; 0x400
8003416: 613b str r3, [r7, #16]
8003418: 693b ldr r3, [r7, #16]
LCD_DISP_GPIO_CLK_ENABLE();
800341a: 4b3a ldr r3, [pc, #232] ; (8003504 <BSP_LCD_MspInit+0x19c>)
800341c: 6b1b ldr r3, [r3, #48] ; 0x30
800341e: 4a39 ldr r2, [pc, #228] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003420: f443 7380 orr.w r3, r3, #256 ; 0x100
8003424: 6313 str r3, [r2, #48] ; 0x30
8003426: 4b37 ldr r3, [pc, #220] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003428: 6b1b ldr r3, [r3, #48] ; 0x30
800342a: f403 7380 and.w r3, r3, #256 ; 0x100
800342e: 60fb str r3, [r7, #12]
8003430: 68fb ldr r3, [r7, #12]
LCD_BL_CTRL_GPIO_CLK_ENABLE();
8003432: 4b34 ldr r3, [pc, #208] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003434: 6b1b ldr r3, [r3, #48] ; 0x30
8003436: 4a33 ldr r2, [pc, #204] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003438: f443 6380 orr.w r3, r3, #1024 ; 0x400
800343c: 6313 str r3, [r2, #48] ; 0x30
800343e: 4b31 ldr r3, [pc, #196] ; (8003504 <BSP_LCD_MspInit+0x19c>)
8003440: 6b1b ldr r3, [r3, #48] ; 0x30
8003442: f403 6380 and.w r3, r3, #1024 ; 0x400
8003446: 60bb str r3, [r7, #8]
8003448: 68bb ldr r3, [r7, #8]
/*** LTDC Pins configuration ***/
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_4;
800344a: 2310 movs r3, #16
800344c: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
800344e: 2302 movs r3, #2
8003450: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_NOPULL;
8003452: 2300 movs r3, #0
8003454: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8003456: 2302 movs r3, #2
8003458: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
800345a: 230e movs r3, #14
800345c: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
800345e: f107 032c add.w r3, r7, #44 ; 0x2c
8003462: 4619 mov r1, r3
8003464: 4828 ldr r0, [pc, #160] ; (8003508 <BSP_LCD_MspInit+0x1a0>)
8003466: f003 ff07 bl 8007278 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_12;
800346a: f44f 5380 mov.w r3, #4096 ; 0x1000
800346e: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003470: 2302 movs r3, #2
8003472: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
8003474: 2309 movs r3, #9
8003476: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
8003478: f107 032c add.w r3, r7, #44 ; 0x2c
800347c: 4619 mov r1, r3
800347e: 4823 ldr r0, [pc, #140] ; (800350c <BSP_LCD_MspInit+0x1a4>)
8003480: f003 fefa bl 8007278 <HAL_GPIO_Init>
/* GPIOI LTDC alternate configuration */
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
8003484: f44f 4366 mov.w r3, #58880 ; 0xe600
8003488: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
800348a: 2302 movs r3, #2
800348c: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
800348e: 230e movs r3, #14
8003490: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
8003492: f107 032c add.w r3, r7, #44 ; 0x2c
8003496: 4619 mov r1, r3
8003498: 481d ldr r0, [pc, #116] ; (8003510 <BSP_LCD_MspInit+0x1a8>)
800349a: f003 feed bl 8007278 <HAL_GPIO_Init>
/* GPIOJ configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
800349e: f64e 73ff movw r3, #61439 ; 0xefff
80034a2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80034a4: 2302 movs r3, #2
80034a6: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
80034a8: 230e movs r3, #14
80034aa: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
80034ac: f107 032c add.w r3, r7, #44 ; 0x2c
80034b0: 4619 mov r1, r3
80034b2: 4818 ldr r0, [pc, #96] ; (8003514 <BSP_LCD_MspInit+0x1ac>)
80034b4: f003 fee0 bl 8007278 <HAL_GPIO_Init>
/* GPIOK configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
80034b8: 23f7 movs r3, #247 ; 0xf7
80034ba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80034bc: 2302 movs r3, #2
80034be: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
80034c0: 230e movs r3, #14
80034c2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
80034c4: f107 032c add.w r3, r7, #44 ; 0x2c
80034c8: 4619 mov r1, r3
80034ca: 4813 ldr r0, [pc, #76] ; (8003518 <BSP_LCD_MspInit+0x1b0>)
80034cc: f003 fed4 bl 8007278 <HAL_GPIO_Init>
/* LCD_DISP GPIO configuration */
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
80034d0: f44f 5380 mov.w r3, #4096 ; 0x1000
80034d4: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80034d6: 2301 movs r3, #1
80034d8: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
80034da: f107 032c add.w r3, r7, #44 ; 0x2c
80034de: 4619 mov r1, r3
80034e0: 480b ldr r0, [pc, #44] ; (8003510 <BSP_LCD_MspInit+0x1a8>)
80034e2: f003 fec9 bl 8007278 <HAL_GPIO_Init>
/* LCD_BL_CTRL GPIO configuration */
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
80034e6: 2308 movs r3, #8
80034e8: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80034ea: 2301 movs r3, #1
80034ec: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
80034ee: f107 032c add.w r3, r7, #44 ; 0x2c
80034f2: 4619 mov r1, r3
80034f4: 4808 ldr r0, [pc, #32] ; (8003518 <BSP_LCD_MspInit+0x1b0>)
80034f6: f003 febf bl 8007278 <HAL_GPIO_Init>
}
80034fa: bf00 nop
80034fc: 3740 adds r7, #64 ; 0x40
80034fe: 46bd mov sp, r7
8003500: bd80 pop {r7, pc}
8003502: bf00 nop
8003504: 40023800 .word 0x40023800
8003508: 40021000 .word 0x40021000
800350c: 40021800 .word 0x40021800
8003510: 40022000 .word 0x40022000
8003514: 40022400 .word 0x40022400
8003518: 40022800 .word 0x40022800
0800351c <BSP_LCD_ClockConfig>:
* @note This API is called by BSP_LCD_Init()
* Being __weak it can be overwritten by the application
* @retval None
*/
__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)
{
800351c: b580 push {r7, lr}
800351e: b082 sub sp, #8
8003520: af00 add r7, sp, #0
8003522: 6078 str r0, [r7, #4]
8003524: 6039 str r1, [r7, #0]
/* RK043FN48H LCD clock configuration */
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
8003526: 4b0a ldr r3, [pc, #40] ; (8003550 <BSP_LCD_ClockConfig+0x34>)
8003528: 2208 movs r2, #8
800352a: 601a str r2, [r3, #0]
periph_clk_init_struct.PLLSAI.PLLSAIN = 192;
800352c: 4b08 ldr r3, [pc, #32] ; (8003550 <BSP_LCD_ClockConfig+0x34>)
800352e: 22c0 movs r2, #192 ; 0xc0
8003530: 615a str r2, [r3, #20]
periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER;
8003532: 4b07 ldr r3, [pc, #28] ; (8003550 <BSP_LCD_ClockConfig+0x34>)
8003534: 2205 movs r2, #5
8003536: 61da str r2, [r3, #28]
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
8003538: 4b05 ldr r3, [pc, #20] ; (8003550 <BSP_LCD_ClockConfig+0x34>)
800353a: f44f 3280 mov.w r2, #65536 ; 0x10000
800353e: 62da str r2, [r3, #44] ; 0x2c
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
8003540: 4803 ldr r0, [pc, #12] ; (8003550 <BSP_LCD_ClockConfig+0x34>)
8003542: f005 fe27 bl 8009194 <HAL_RCCEx_PeriphCLKConfig>
}
8003546: bf00 nop
8003548: 3708 adds r7, #8
800354a: 46bd mov sp, r7
800354c: bd80 pop {r7, pc}
800354e: bf00 nop
8003550: 20000438 .word 0x20000438
08003554 <LL_FillBuffer>:
* @param OffLine: Offset
* @param ColorIndex: Color index
* @retval None
*/
static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
{
8003554: b580 push {r7, lr}
8003556: b086 sub sp, #24
8003558: af02 add r7, sp, #8
800355a: 60f8 str r0, [r7, #12]
800355c: 60b9 str r1, [r7, #8]
800355e: 607a str r2, [r7, #4]
8003560: 603b str r3, [r7, #0]
/* Register to memory mode with ARGB8888 as color Mode */
hDma2dHandler.Init.Mode = DMA2D_R2M;
8003562: 4b1e ldr r3, [pc, #120] ; (80035dc <LL_FillBuffer+0x88>)
8003564: f44f 3240 mov.w r2, #196608 ; 0x30000
8003568: 605a str r2, [r3, #4]
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
800356a: 4b1d ldr r3, [pc, #116] ; (80035e0 <LL_FillBuffer+0x8c>)
800356c: 681b ldr r3, [r3, #0]
800356e: 4a1d ldr r2, [pc, #116] ; (80035e4 <LL_FillBuffer+0x90>)
8003570: 2134 movs r1, #52 ; 0x34
8003572: fb01 f303 mul.w r3, r1, r3
8003576: 4413 add r3, r2
8003578: 3348 adds r3, #72 ; 0x48
800357a: 681b ldr r3, [r3, #0]
800357c: 2b02 cmp r3, #2
800357e: d103 bne.n 8003588 <LL_FillBuffer+0x34>
{ /* RGB565 format */
hDma2dHandler.Init.ColorMode = DMA2D_RGB565;
8003580: 4b16 ldr r3, [pc, #88] ; (80035dc <LL_FillBuffer+0x88>)
8003582: 2202 movs r2, #2
8003584: 609a str r2, [r3, #8]
8003586: e002 b.n 800358e <LL_FillBuffer+0x3a>
}
else
{ /* ARGB8888 format */
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
8003588: 4b14 ldr r3, [pc, #80] ; (80035dc <LL_FillBuffer+0x88>)
800358a: 2200 movs r2, #0
800358c: 609a str r2, [r3, #8]
}
hDma2dHandler.Init.OutputOffset = OffLine;
800358e: 4a13 ldr r2, [pc, #76] ; (80035dc <LL_FillBuffer+0x88>)
8003590: 69bb ldr r3, [r7, #24]
8003592: 60d3 str r3, [r2, #12]
hDma2dHandler.Instance = DMA2D;
8003594: 4b11 ldr r3, [pc, #68] ; (80035dc <LL_FillBuffer+0x88>)
8003596: 4a14 ldr r2, [pc, #80] ; (80035e8 <LL_FillBuffer+0x94>)
8003598: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
800359a: 4810 ldr r0, [pc, #64] ; (80035dc <LL_FillBuffer+0x88>)
800359c: f002 fa5a bl 8005a54 <HAL_DMA2D_Init>
80035a0: 4603 mov r3, r0
80035a2: 2b00 cmp r3, #0
80035a4: d115 bne.n 80035d2 <LL_FillBuffer+0x7e>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK)
80035a6: 68f9 ldr r1, [r7, #12]
80035a8: 480c ldr r0, [pc, #48] ; (80035dc <LL_FillBuffer+0x88>)
80035aa: f002 fbb1 bl 8005d10 <HAL_DMA2D_ConfigLayer>
80035ae: 4603 mov r3, r0
80035b0: 2b00 cmp r3, #0
80035b2: d10e bne.n 80035d2 <LL_FillBuffer+0x7e>
{
if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
80035b4: 68ba ldr r2, [r7, #8]
80035b6: 683b ldr r3, [r7, #0]
80035b8: 9300 str r3, [sp, #0]
80035ba: 687b ldr r3, [r7, #4]
80035bc: 69f9 ldr r1, [r7, #28]
80035be: 4807 ldr r0, [pc, #28] ; (80035dc <LL_FillBuffer+0x88>)
80035c0: f002 fa92 bl 8005ae8 <HAL_DMA2D_Start>
80035c4: 4603 mov r3, r0
80035c6: 2b00 cmp r3, #0
80035c8: d103 bne.n 80035d2 <LL_FillBuffer+0x7e>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
80035ca: 210a movs r1, #10
80035cc: 4803 ldr r0, [pc, #12] ; (80035dc <LL_FillBuffer+0x88>)
80035ce: f002 fab6 bl 8005b3e <HAL_DMA2D_PollForTransfer>
}
}
}
}
80035d2: bf00 nop
80035d4: 3710 adds r7, #16
80035d6: 46bd mov sp, r7
80035d8: bd80 pop {r7, pc}
80035da: bf00 nop
80035dc: 200003dc .word 0x200003dc
80035e0: 2000041c .word 0x2000041c
80035e4: 20008c34 .word 0x20008c34
80035e8: 4002b000 .word 0x4002b000
080035ec <LL_ConvertLineToARGB8888>:
* @param xSize: Buffer width
* @param ColorMode: Input color mode
* @retval None
*/
static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode)
{
80035ec: b580 push {r7, lr}
80035ee: b086 sub sp, #24
80035f0: af02 add r7, sp, #8
80035f2: 60f8 str r0, [r7, #12]
80035f4: 60b9 str r1, [r7, #8]
80035f6: 607a str r2, [r7, #4]
80035f8: 603b str r3, [r7, #0]
/* Configure the DMA2D Mode, Color Mode and output offset */
hDma2dHandler.Init.Mode = DMA2D_M2M_PFC;
80035fa: 4b1c ldr r3, [pc, #112] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
80035fc: f44f 3280 mov.w r2, #65536 ; 0x10000
8003600: 605a str r2, [r3, #4]
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
8003602: 4b1a ldr r3, [pc, #104] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003604: 2200 movs r2, #0
8003606: 609a str r2, [r3, #8]
hDma2dHandler.Init.OutputOffset = 0;
8003608: 4b18 ldr r3, [pc, #96] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
800360a: 2200 movs r2, #0
800360c: 60da str r2, [r3, #12]
/* Foreground Configuration */
hDma2dHandler.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
800360e: 4b17 ldr r3, [pc, #92] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003610: 2200 movs r2, #0
8003612: 631a str r2, [r3, #48] ; 0x30
hDma2dHandler.LayerCfg[1].InputAlpha = 0xFF;
8003614: 4b15 ldr r3, [pc, #84] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003616: 22ff movs r2, #255 ; 0xff
8003618: 635a str r2, [r3, #52] ; 0x34
hDma2dHandler.LayerCfg[1].InputColorMode = ColorMode;
800361a: 4a14 ldr r2, [pc, #80] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
800361c: 683b ldr r3, [r7, #0]
800361e: 62d3 str r3, [r2, #44] ; 0x2c
hDma2dHandler.LayerCfg[1].InputOffset = 0;
8003620: 4b12 ldr r3, [pc, #72] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003622: 2200 movs r2, #0
8003624: 629a str r2, [r3, #40] ; 0x28
hDma2dHandler.Instance = DMA2D;
8003626: 4b11 ldr r3, [pc, #68] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003628: 4a11 ldr r2, [pc, #68] ; (8003670 <LL_ConvertLineToARGB8888+0x84>)
800362a: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
800362c: 480f ldr r0, [pc, #60] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
800362e: f002 fa11 bl 8005a54 <HAL_DMA2D_Init>
8003632: 4603 mov r3, r0
8003634: 2b00 cmp r3, #0
8003636: d115 bne.n 8003664 <LL_ConvertLineToARGB8888+0x78>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, 1) == HAL_OK)
8003638: 2101 movs r1, #1
800363a: 480c ldr r0, [pc, #48] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
800363c: f002 fb68 bl 8005d10 <HAL_DMA2D_ConfigLayer>
8003640: 4603 mov r3, r0
8003642: 2b00 cmp r3, #0
8003644: d10e bne.n 8003664 <LL_ConvertLineToARGB8888+0x78>
{
if (HAL_DMA2D_Start(&hDma2dHandler, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK)
8003646: 68f9 ldr r1, [r7, #12]
8003648: 68ba ldr r2, [r7, #8]
800364a: 2301 movs r3, #1
800364c: 9300 str r3, [sp, #0]
800364e: 687b ldr r3, [r7, #4]
8003650: 4806 ldr r0, [pc, #24] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003652: f002 fa49 bl 8005ae8 <HAL_DMA2D_Start>
8003656: 4603 mov r3, r0
8003658: 2b00 cmp r3, #0
800365a: d103 bne.n 8003664 <LL_ConvertLineToARGB8888+0x78>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
800365c: 210a movs r1, #10
800365e: 4803 ldr r0, [pc, #12] ; (800366c <LL_ConvertLineToARGB8888+0x80>)
8003660: f002 fa6d bl 8005b3e <HAL_DMA2D_PollForTransfer>
}
}
}
}
8003664: bf00 nop
8003666: 3710 adds r7, #16
8003668: 46bd mov sp, r7
800366a: bd80 pop {r7, pc}
800366c: 200003dc .word 0x200003dc
8003670: 4002b000 .word 0x4002b000
08003674 <BSP_SDRAM_Init>:
/**
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
{
8003674: b580 push {r7, lr}
8003676: af00 add r7, sp, #0
static uint8_t sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
8003678: 4b29 ldr r3, [pc, #164] ; (8003720 <BSP_SDRAM_Init+0xac>)
800367a: 4a2a ldr r2, [pc, #168] ; (8003724 <BSP_SDRAM_Init+0xb0>)
800367c: 601a str r2, [r3, #0]
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
Timing.LoadToActiveDelay = 2;
800367e: 4b2a ldr r3, [pc, #168] ; (8003728 <BSP_SDRAM_Init+0xb4>)
8003680: 2202 movs r2, #2
8003682: 601a str r2, [r3, #0]
Timing.ExitSelfRefreshDelay = 7;
8003684: 4b28 ldr r3, [pc, #160] ; (8003728 <BSP_SDRAM_Init+0xb4>)
8003686: 2207 movs r2, #7
8003688: 605a str r2, [r3, #4]
Timing.SelfRefreshTime = 4;
800368a: 4b27 ldr r3, [pc, #156] ; (8003728 <BSP_SDRAM_Init+0xb4>)
800368c: 2204 movs r2, #4
800368e: 609a str r2, [r3, #8]
Timing.RowCycleDelay = 7;
8003690: 4b25 ldr r3, [pc, #148] ; (8003728 <BSP_SDRAM_Init+0xb4>)
8003692: 2207 movs r2, #7
8003694: 60da str r2, [r3, #12]
Timing.WriteRecoveryTime = 2;
8003696: 4b24 ldr r3, [pc, #144] ; (8003728 <BSP_SDRAM_Init+0xb4>)
8003698: 2202 movs r2, #2
800369a: 611a str r2, [r3, #16]
Timing.RPDelay = 2;
800369c: 4b22 ldr r3, [pc, #136] ; (8003728 <BSP_SDRAM_Init+0xb4>)
800369e: 2202 movs r2, #2
80036a0: 615a str r2, [r3, #20]
Timing.RCDDelay = 2;
80036a2: 4b21 ldr r3, [pc, #132] ; (8003728 <BSP_SDRAM_Init+0xb4>)
80036a4: 2202 movs r2, #2
80036a6: 619a str r2, [r3, #24]
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
80036a8: 4b1d ldr r3, [pc, #116] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036aa: 2200 movs r2, #0
80036ac: 605a str r2, [r3, #4]
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
80036ae: 4b1c ldr r3, [pc, #112] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036b0: 2200 movs r2, #0
80036b2: 609a str r2, [r3, #8]
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
80036b4: 4b1a ldr r3, [pc, #104] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036b6: 2204 movs r2, #4
80036b8: 60da str r2, [r3, #12]
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
80036ba: 4b19 ldr r3, [pc, #100] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036bc: 2210 movs r2, #16
80036be: 611a str r2, [r3, #16]
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
80036c0: 4b17 ldr r3, [pc, #92] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036c2: 2240 movs r2, #64 ; 0x40
80036c4: 615a str r2, [r3, #20]
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
80036c6: 4b16 ldr r3, [pc, #88] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036c8: f44f 7280 mov.w r2, #256 ; 0x100
80036cc: 619a str r2, [r3, #24]
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
80036ce: 4b14 ldr r3, [pc, #80] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036d0: 2200 movs r2, #0
80036d2: 61da str r2, [r3, #28]
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
80036d4: 4b12 ldr r3, [pc, #72] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036d6: f44f 6200 mov.w r2, #2048 ; 0x800
80036da: 621a str r2, [r3, #32]
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
80036dc: 4b10 ldr r3, [pc, #64] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036de: f44f 5280 mov.w r2, #4096 ; 0x1000
80036e2: 625a str r2, [r3, #36] ; 0x24
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
80036e4: 4b0e ldr r3, [pc, #56] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036e6: 2200 movs r2, #0
80036e8: 629a str r2, [r3, #40] ; 0x28
/* SDRAM controller initialization */
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
80036ea: 2100 movs r1, #0
80036ec: 480c ldr r0, [pc, #48] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036ee: f000 f87f bl 80037f0 <BSP_SDRAM_MspInit>
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
80036f2: 490d ldr r1, [pc, #52] ; (8003728 <BSP_SDRAM_Init+0xb4>)
80036f4: 480a ldr r0, [pc, #40] ; (8003720 <BSP_SDRAM_Init+0xac>)
80036f6: f006 f965 bl 80099c4 <HAL_SDRAM_Init>
80036fa: 4603 mov r3, r0
80036fc: 2b00 cmp r3, #0
80036fe: d003 beq.n 8003708 <BSP_SDRAM_Init+0x94>
{
sdramstatus = SDRAM_ERROR;
8003700: 4b0a ldr r3, [pc, #40] ; (800372c <BSP_SDRAM_Init+0xb8>)
8003702: 2201 movs r2, #1
8003704: 701a strb r2, [r3, #0]
8003706: e002 b.n 800370e <BSP_SDRAM_Init+0x9a>
}
else
{
sdramstatus = SDRAM_OK;
8003708: 4b08 ldr r3, [pc, #32] ; (800372c <BSP_SDRAM_Init+0xb8>)
800370a: 2200 movs r2, #0
800370c: 701a strb r2, [r3, #0]
}
/* SDRAM initialization sequence */
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
800370e: f240 6003 movw r0, #1539 ; 0x603
8003712: f000 f80d bl 8003730 <BSP_SDRAM_Initialization_sequence>
return sdramstatus;
8003716: 4b05 ldr r3, [pc, #20] ; (800372c <BSP_SDRAM_Init+0xb8>)
8003718: 781b ldrb r3, [r3, #0]
}
800371a: 4618 mov r0, r3
800371c: bd80 pop {r7, pc}
800371e: bf00 nop
8003720: 20008cdc .word 0x20008cdc
8003724: a0000140 .word 0xa0000140
8003728: 200004bc .word 0x200004bc
800372c: 20000060 .word 0x20000060
08003730 <BSP_SDRAM_Initialization_sequence>:
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
* @retval None
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
{
8003730: b580 push {r7, lr}
8003732: b084 sub sp, #16
8003734: af00 add r7, sp, #0
8003736: 6078 str r0, [r7, #4]
__IO uint32_t tmpmrd = 0;
8003738: 2300 movs r3, #0
800373a: 60fb str r3, [r7, #12]
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
800373c: 4b2a ldr r3, [pc, #168] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800373e: 2201 movs r2, #1
8003740: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003742: 4b29 ldr r3, [pc, #164] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003744: 2210 movs r2, #16
8003746: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003748: 4b27 ldr r3, [pc, #156] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800374a: 2201 movs r2, #1
800374c: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
800374e: 4b26 ldr r3, [pc, #152] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003750: 2200 movs r2, #0
8003752: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003754: f64f 72ff movw r2, #65535 ; 0xffff
8003758: 4923 ldr r1, [pc, #140] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800375a: 4824 ldr r0, [pc, #144] ; (80037ec <BSP_SDRAM_Initialization_sequence+0xbc>)
800375c: f006 f966 bl 8009a2c <HAL_SDRAM_SendCommand>
/* Step 2: Insert 100 us minimum delay */
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
HAL_Delay(1);
8003760: 2001 movs r0, #1
8003762: f001 f925 bl 80049b0 <HAL_Delay>
/* Step 3: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
8003766: 4b20 ldr r3, [pc, #128] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003768: 2202 movs r2, #2
800376a: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
800376c: 4b1e ldr r3, [pc, #120] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800376e: 2210 movs r2, #16
8003770: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003772: 4b1d ldr r3, [pc, #116] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003774: 2201 movs r2, #1
8003776: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003778: 4b1b ldr r3, [pc, #108] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800377a: 2200 movs r2, #0
800377c: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
800377e: f64f 72ff movw r2, #65535 ; 0xffff
8003782: 4919 ldr r1, [pc, #100] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003784: 4819 ldr r0, [pc, #100] ; (80037ec <BSP_SDRAM_Initialization_sequence+0xbc>)
8003786: f006 f951 bl 8009a2c <HAL_SDRAM_SendCommand>
/* Step 4: Configure an Auto Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
800378a: 4b17 ldr r3, [pc, #92] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800378c: 2203 movs r2, #3
800378e: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003790: 4b15 ldr r3, [pc, #84] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003792: 2210 movs r2, #16
8003794: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 8;
8003796: 4b14 ldr r3, [pc, #80] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003798: 2208 movs r2, #8
800379a: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
800379c: 4b12 ldr r3, [pc, #72] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
800379e: 2200 movs r2, #0
80037a0: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80037a2: f64f 72ff movw r2, #65535 ; 0xffff
80037a6: 4910 ldr r1, [pc, #64] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037a8: 4810 ldr r0, [pc, #64] ; (80037ec <BSP_SDRAM_Initialization_sequence+0xbc>)
80037aa: f006 f93f bl 8009a2c <HAL_SDRAM_SendCommand>
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
80037ae: f44f 7308 mov.w r3, #544 ; 0x220
80037b2: 60fb str r3, [r7, #12]
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_2 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
80037b4: 4b0c ldr r3, [pc, #48] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037b6: 2204 movs r2, #4
80037b8: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80037ba: 4b0b ldr r3, [pc, #44] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037bc: 2210 movs r2, #16
80037be: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
80037c0: 4b09 ldr r3, [pc, #36] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037c2: 2201 movs r2, #1
80037c4: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = tmpmrd;
80037c6: 68fb ldr r3, [r7, #12]
80037c8: 4a07 ldr r2, [pc, #28] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037ca: 60d3 str r3, [r2, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80037cc: f64f 72ff movw r2, #65535 ; 0xffff
80037d0: 4905 ldr r1, [pc, #20] ; (80037e8 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037d2: 4806 ldr r0, [pc, #24] ; (80037ec <BSP_SDRAM_Initialization_sequence+0xbc>)
80037d4: f006 f92a bl 8009a2c <HAL_SDRAM_SendCommand>
/* Step 6: Set the refresh rate counter */
/* Set the device refresh rate */
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
80037d8: 6879 ldr r1, [r7, #4]
80037da: 4804 ldr r0, [pc, #16] ; (80037ec <BSP_SDRAM_Initialization_sequence+0xbc>)
80037dc: f006 f951 bl 8009a82 <HAL_SDRAM_ProgramRefreshRate>
}
80037e0: bf00 nop
80037e2: 3710 adds r7, #16
80037e4: 46bd mov sp, r7
80037e6: bd80 pop {r7, pc}
80037e8: 200004d8 .word 0x200004d8
80037ec: 20008cdc .word 0x20008cdc
080037f0 <BSP_SDRAM_MspInit>:
* @param hsdram: SDRAM handle
* @param Params
* @retval None
*/
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
{
80037f0: b580 push {r7, lr}
80037f2: b090 sub sp, #64 ; 0x40
80037f4: af00 add r7, sp, #0
80037f6: 6078 str r0, [r7, #4]
80037f8: 6039 str r1, [r7, #0]
static DMA_HandleTypeDef dma_handle;
GPIO_InitTypeDef gpio_init_structure;
/* Enable FMC clock */
__HAL_RCC_FMC_CLK_ENABLE();
80037fa: 4b70 ldr r3, [pc, #448] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
80037fc: 6b9b ldr r3, [r3, #56] ; 0x38
80037fe: 4a6f ldr r2, [pc, #444] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003800: f043 0301 orr.w r3, r3, #1
8003804: 6393 str r3, [r2, #56] ; 0x38
8003806: 4b6d ldr r3, [pc, #436] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003808: 6b9b ldr r3, [r3, #56] ; 0x38
800380a: f003 0301 and.w r3, r3, #1
800380e: 62bb str r3, [r7, #40] ; 0x28
8003810: 6abb ldr r3, [r7, #40] ; 0x28
/* Enable chosen DMAx clock */
__DMAx_CLK_ENABLE();
8003812: 4b6a ldr r3, [pc, #424] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003814: 6b1b ldr r3, [r3, #48] ; 0x30
8003816: 4a69 ldr r2, [pc, #420] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003818: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
800381c: 6313 str r3, [r2, #48] ; 0x30
800381e: 4b67 ldr r3, [pc, #412] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003820: 6b1b ldr r3, [r3, #48] ; 0x30
8003822: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8003826: 627b str r3, [r7, #36] ; 0x24
8003828: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOC_CLK_ENABLE();
800382a: 4b64 ldr r3, [pc, #400] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
800382c: 6b1b ldr r3, [r3, #48] ; 0x30
800382e: 4a63 ldr r2, [pc, #396] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003830: f043 0304 orr.w r3, r3, #4
8003834: 6313 str r3, [r2, #48] ; 0x30
8003836: 4b61 ldr r3, [pc, #388] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003838: 6b1b ldr r3, [r3, #48] ; 0x30
800383a: f003 0304 and.w r3, r3, #4
800383e: 623b str r3, [r7, #32]
8003840: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOD_CLK_ENABLE();
8003842: 4b5e ldr r3, [pc, #376] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003844: 6b1b ldr r3, [r3, #48] ; 0x30
8003846: 4a5d ldr r2, [pc, #372] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003848: f043 0308 orr.w r3, r3, #8
800384c: 6313 str r3, [r2, #48] ; 0x30
800384e: 4b5b ldr r3, [pc, #364] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003850: 6b1b ldr r3, [r3, #48] ; 0x30
8003852: f003 0308 and.w r3, r3, #8
8003856: 61fb str r3, [r7, #28]
8003858: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOE_CLK_ENABLE();
800385a: 4b58 ldr r3, [pc, #352] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
800385c: 6b1b ldr r3, [r3, #48] ; 0x30
800385e: 4a57 ldr r2, [pc, #348] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003860: f043 0310 orr.w r3, r3, #16
8003864: 6313 str r3, [r2, #48] ; 0x30
8003866: 4b55 ldr r3, [pc, #340] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003868: 6b1b ldr r3, [r3, #48] ; 0x30
800386a: f003 0310 and.w r3, r3, #16
800386e: 61bb str r3, [r7, #24]
8003870: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003872: 4b52 ldr r3, [pc, #328] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003874: 6b1b ldr r3, [r3, #48] ; 0x30
8003876: 4a51 ldr r2, [pc, #324] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003878: f043 0320 orr.w r3, r3, #32
800387c: 6313 str r3, [r2, #48] ; 0x30
800387e: 4b4f ldr r3, [pc, #316] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003880: 6b1b ldr r3, [r3, #48] ; 0x30
8003882: f003 0320 and.w r3, r3, #32
8003886: 617b str r3, [r7, #20]
8003888: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
800388a: 4b4c ldr r3, [pc, #304] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
800388c: 6b1b ldr r3, [r3, #48] ; 0x30
800388e: 4a4b ldr r2, [pc, #300] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003890: f043 0340 orr.w r3, r3, #64 ; 0x40
8003894: 6313 str r3, [r2, #48] ; 0x30
8003896: 4b49 ldr r3, [pc, #292] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
8003898: 6b1b ldr r3, [r3, #48] ; 0x30
800389a: f003 0340 and.w r3, r3, #64 ; 0x40
800389e: 613b str r3, [r7, #16]
80038a0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80038a2: 4b46 ldr r3, [pc, #280] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
80038a4: 6b1b ldr r3, [r3, #48] ; 0x30
80038a6: 4a45 ldr r2, [pc, #276] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
80038a8: f043 0380 orr.w r3, r3, #128 ; 0x80
80038ac: 6313 str r3, [r2, #48] ; 0x30
80038ae: 4b43 ldr r3, [pc, #268] ; (80039bc <BSP_SDRAM_MspInit+0x1cc>)
80038b0: 6b1b ldr r3, [r3, #48] ; 0x30
80038b2: f003 0380 and.w r3, r3, #128 ; 0x80
80038b6: 60fb str r3, [r7, #12]
80038b8: 68fb ldr r3, [r7, #12]
/* Common GPIO configuration */
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80038ba: 2302 movs r3, #2
80038bc: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_PULLUP;
80038be: 2301 movs r3, #1
80038c0: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
80038c2: 2302 movs r3, #2
80038c4: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF12_FMC;
80038c6: 230c movs r3, #12
80038c8: 63fb str r3, [r7, #60] ; 0x3c
/* GPIOC configuration */
gpio_init_structure.Pin = GPIO_PIN_3;
80038ca: 2308 movs r3, #8
80038cc: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
80038ce: f107 032c add.w r3, r7, #44 ; 0x2c
80038d2: 4619 mov r1, r3
80038d4: 483a ldr r0, [pc, #232] ; (80039c0 <BSP_SDRAM_MspInit+0x1d0>)
80038d6: f003 fccf bl 8007278 <HAL_GPIO_Init>
/* GPIOD configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
80038da: f24c 7303 movw r3, #50947 ; 0xc703
80038de: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
80038e0: f107 032c add.w r3, r7, #44 ; 0x2c
80038e4: 4619 mov r1, r3
80038e6: 4837 ldr r0, [pc, #220] ; (80039c4 <BSP_SDRAM_MspInit+0x1d4>)
80038e8: f003 fcc6 bl 8007278 <HAL_GPIO_Init>
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
80038ec: f64f 7383 movw r3, #65411 ; 0xff83
80038f0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
80038f2: f107 032c add.w r3, r7, #44 ; 0x2c
80038f6: 4619 mov r1, r3
80038f8: 4833 ldr r0, [pc, #204] ; (80039c8 <BSP_SDRAM_MspInit+0x1d8>)
80038fa: f003 fcbd bl 8007278 <HAL_GPIO_Init>
/* GPIOF configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
80038fe: f64f 033f movw r3, #63551 ; 0xf83f
8003902: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
8003904: f107 032c add.w r3, r7, #44 ; 0x2c
8003908: 4619 mov r1, r3
800390a: 4830 ldr r0, [pc, #192] ; (80039cc <BSP_SDRAM_MspInit+0x1dc>)
800390c: f003 fcb4 bl 8007278 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
8003910: f248 1333 movw r3, #33075 ; 0x8133
8003914: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
8003916: f107 032c add.w r3, r7, #44 ; 0x2c
800391a: 4619 mov r1, r3
800391c: 482c ldr r0, [pc, #176] ; (80039d0 <BSP_SDRAM_MspInit+0x1e0>)
800391e: f003 fcab bl 8007278 <HAL_GPIO_Init>
/* GPIOH configuration */
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
8003922: 2328 movs r3, #40 ; 0x28
8003924: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
8003926: f107 032c add.w r3, r7, #44 ; 0x2c
800392a: 4619 mov r1, r3
800392c: 4829 ldr r0, [pc, #164] ; (80039d4 <BSP_SDRAM_MspInit+0x1e4>)
800392e: f003 fca3 bl 8007278 <HAL_GPIO_Init>
/* Configure common DMA parameters */
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
8003932: 4b29 ldr r3, [pc, #164] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003934: 2200 movs r2, #0
8003936: 605a str r2, [r3, #4]
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
8003938: 4b27 ldr r3, [pc, #156] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
800393a: 2280 movs r2, #128 ; 0x80
800393c: 609a str r2, [r3, #8]
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
800393e: 4b26 ldr r3, [pc, #152] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003940: f44f 7200 mov.w r2, #512 ; 0x200
8003944: 60da str r2, [r3, #12]
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
8003946: 4b24 ldr r3, [pc, #144] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003948: f44f 6280 mov.w r2, #1024 ; 0x400
800394c: 611a str r2, [r3, #16]
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
800394e: 4b22 ldr r3, [pc, #136] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003950: f44f 5280 mov.w r2, #4096 ; 0x1000
8003954: 615a str r2, [r3, #20]
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
8003956: 4b20 ldr r3, [pc, #128] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003958: f44f 4280 mov.w r2, #16384 ; 0x4000
800395c: 619a str r2, [r3, #24]
dma_handle.Init.Mode = DMA_NORMAL;
800395e: 4b1e ldr r3, [pc, #120] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003960: 2200 movs r2, #0
8003962: 61da str r2, [r3, #28]
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
8003964: 4b1c ldr r3, [pc, #112] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003966: f44f 3200 mov.w r2, #131072 ; 0x20000
800396a: 621a str r2, [r3, #32]
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
800396c: 4b1a ldr r3, [pc, #104] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
800396e: 2200 movs r2, #0
8003970: 625a str r2, [r3, #36] ; 0x24
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
8003972: 4b19 ldr r3, [pc, #100] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003974: 2203 movs r2, #3
8003976: 629a str r2, [r3, #40] ; 0x28
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
8003978: 4b17 ldr r3, [pc, #92] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
800397a: 2200 movs r2, #0
800397c: 62da str r2, [r3, #44] ; 0x2c
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
800397e: 4b16 ldr r3, [pc, #88] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003980: 2200 movs r2, #0
8003982: 631a str r2, [r3, #48] ; 0x30
dma_handle.Instance = SDRAM_DMAx_STREAM;
8003984: 4b14 ldr r3, [pc, #80] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003986: 4a15 ldr r2, [pc, #84] ; (80039dc <BSP_SDRAM_MspInit+0x1ec>)
8003988: 601a str r2, [r3, #0]
/* Associate the DMA handle */
__HAL_LINKDMA(hsdram, hdma, dma_handle);
800398a: 687b ldr r3, [r7, #4]
800398c: 4a12 ldr r2, [pc, #72] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
800398e: 631a str r2, [r3, #48] ; 0x30
8003990: 4a11 ldr r2, [pc, #68] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003992: 687b ldr r3, [r7, #4]
8003994: 6393 str r3, [r2, #56] ; 0x38
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dma_handle);
8003996: 4810 ldr r0, [pc, #64] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
8003998: f001 ff4e bl 8005838 <HAL_DMA_DeInit>
/* Configure the DMA stream */
HAL_DMA_Init(&dma_handle);
800399c: 480e ldr r0, [pc, #56] ; (80039d8 <BSP_SDRAM_MspInit+0x1e8>)
800399e: f001 fe9d bl 80056dc <HAL_DMA_Init>
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
80039a2: 2200 movs r2, #0
80039a4: 210f movs r1, #15
80039a6: 2038 movs r0, #56 ; 0x38
80039a8: f001 fcb6 bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
80039ac: 2038 movs r0, #56 ; 0x38
80039ae: f001 fccf bl 8005350 <HAL_NVIC_EnableIRQ>
}
80039b2: bf00 nop
80039b4: 3740 adds r7, #64 ; 0x40
80039b6: 46bd mov sp, r7
80039b8: bd80 pop {r7, pc}
80039ba: bf00 nop
80039bc: 40023800 .word 0x40023800
80039c0: 40020800 .word 0x40020800
80039c4: 40020c00 .word 0x40020c00
80039c8: 40021000 .word 0x40021000
80039cc: 40021400 .word 0x40021400
80039d0: 40021800 .word 0x40021800
80039d4: 40021c00 .word 0x40021c00
80039d8: 200004e8 .word 0x200004e8
80039dc: 40026410 .word 0x40026410
080039e0 <BSP_TS_Init>:
* @param ts_SizeX: Maximum X size of the TS area on LCD
* @param ts_SizeY: Maximum Y size of the TS area on LCD
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
{
80039e0: b580 push {r7, lr}
80039e2: b084 sub sp, #16
80039e4: af00 add r7, sp, #0
80039e6: 4603 mov r3, r0
80039e8: 460a mov r2, r1
80039ea: 80fb strh r3, [r7, #6]
80039ec: 4613 mov r3, r2
80039ee: 80bb strh r3, [r7, #4]
uint8_t status = TS_OK;
80039f0: 2300 movs r3, #0
80039f2: 73fb strb r3, [r7, #15]
tsXBoundary = ts_SizeX;
80039f4: 4a14 ldr r2, [pc, #80] ; (8003a48 <BSP_TS_Init+0x68>)
80039f6: 88fb ldrh r3, [r7, #6]
80039f8: 8013 strh r3, [r2, #0]
tsYBoundary = ts_SizeY;
80039fa: 4a14 ldr r2, [pc, #80] ; (8003a4c <BSP_TS_Init+0x6c>)
80039fc: 88bb ldrh r3, [r7, #4]
80039fe: 8013 strh r3, [r2, #0]
/* Read ID and verify if the touch screen driver is ready */
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
8003a00: 4b13 ldr r3, [pc, #76] ; (8003a50 <BSP_TS_Init+0x70>)
8003a02: 681b ldr r3, [r3, #0]
8003a04: 2070 movs r0, #112 ; 0x70
8003a06: 4798 blx r3
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
8003a08: 4b11 ldr r3, [pc, #68] ; (8003a50 <BSP_TS_Init+0x70>)
8003a0a: 685b ldr r3, [r3, #4]
8003a0c: 2070 movs r0, #112 ; 0x70
8003a0e: 4798 blx r3
8003a10: 4603 mov r3, r0
8003a12: 2b51 cmp r3, #81 ; 0x51
8003a14: d111 bne.n 8003a3a <BSP_TS_Init+0x5a>
{
/* Initialize the TS driver structure */
tsDriver = &ft5336_ts_drv;
8003a16: 4b0f ldr r3, [pc, #60] ; (8003a54 <BSP_TS_Init+0x74>)
8003a18: 4a0d ldr r2, [pc, #52] ; (8003a50 <BSP_TS_Init+0x70>)
8003a1a: 601a str r2, [r3, #0]
I2cAddress = TS_I2C_ADDRESS;
8003a1c: 4b0e ldr r3, [pc, #56] ; (8003a58 <BSP_TS_Init+0x78>)
8003a1e: 2270 movs r2, #112 ; 0x70
8003a20: 701a strb r2, [r3, #0]
tsOrientation = TS_SWAP_XY;
8003a22: 4b0e ldr r3, [pc, #56] ; (8003a5c <BSP_TS_Init+0x7c>)
8003a24: 2208 movs r2, #8
8003a26: 701a strb r2, [r3, #0]
/* Initialize the TS driver */
tsDriver->Start(I2cAddress);
8003a28: 4b0a ldr r3, [pc, #40] ; (8003a54 <BSP_TS_Init+0x74>)
8003a2a: 681b ldr r3, [r3, #0]
8003a2c: 68db ldr r3, [r3, #12]
8003a2e: 4a0a ldr r2, [pc, #40] ; (8003a58 <BSP_TS_Init+0x78>)
8003a30: 7812 ldrb r2, [r2, #0]
8003a32: b292 uxth r2, r2
8003a34: 4610 mov r0, r2
8003a36: 4798 blx r3
8003a38: e001 b.n 8003a3e <BSP_TS_Init+0x5e>
}
else
{
status = TS_DEVICE_NOT_FOUND;
8003a3a: 2303 movs r3, #3
8003a3c: 73fb strb r3, [r7, #15]
}
return status;
8003a3e: 7bfb ldrb r3, [r7, #15]
}
8003a40: 4618 mov r0, r3
8003a42: 3710 adds r7, #16
8003a44: 46bd mov sp, r7
8003a46: bd80 pop {r7, pc}
8003a48: 2000054c .word 0x2000054c
8003a4c: 2000054e .word 0x2000054e
8003a50: 20000000 .word 0x20000000
8003a54: 20000548 .word 0x20000548
8003a58: 20000551 .word 0x20000551
8003a5c: 20000550 .word 0x20000550
08003a60 <BSP_TS_GetState>:
* @brief Returns status and positions of the touch screen.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
{
8003a60: b590 push {r4, r7, lr}
8003a62: b097 sub sp, #92 ; 0x5c
8003a64: af02 add r7, sp, #8
8003a66: 6078 str r0, [r7, #4]
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
uint8_t ts_status = TS_OK;
8003a68: 2300 movs r3, #0
8003a6a: f887 304f strb.w r3, [r7, #79] ; 0x4f
uint16_t brute_y[TS_MAX_NB_TOUCH];
uint16_t x_diff;
uint16_t y_diff;
uint32_t index;
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
uint32_t weight = 0;
8003a6e: 2300 movs r3, #0
8003a70: 613b str r3, [r7, #16]
uint32_t area = 0;
8003a72: 2300 movs r3, #0
8003a74: 60fb str r3, [r7, #12]
uint32_t event = 0;
8003a76: 2300 movs r3, #0
8003a78: 60bb str r3, [r7, #8]
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
/* Check and update the number of touches active detected */
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
8003a7a: 4b97 ldr r3, [pc, #604] ; (8003cd8 <BSP_TS_GetState+0x278>)
8003a7c: 681b ldr r3, [r3, #0]
8003a7e: 691b ldr r3, [r3, #16]
8003a80: 4a96 ldr r2, [pc, #600] ; (8003cdc <BSP_TS_GetState+0x27c>)
8003a82: 7812 ldrb r2, [r2, #0]
8003a84: b292 uxth r2, r2
8003a86: 4610 mov r0, r2
8003a88: 4798 blx r3
8003a8a: 4603 mov r3, r0
8003a8c: 461a mov r2, r3
8003a8e: 687b ldr r3, [r7, #4]
8003a90: 701a strb r2, [r3, #0]
if(TS_State->touchDetected)
8003a92: 687b ldr r3, [r7, #4]
8003a94: 781b ldrb r3, [r3, #0]
8003a96: 2b00 cmp r3, #0
8003a98: f000 81a8 beq.w 8003dec <BSP_TS_GetState+0x38c>
{
for(index=0; index < TS_State->touchDetected; index++)
8003a9c: 2300 movs r3, #0
8003a9e: 64bb str r3, [r7, #72] ; 0x48
8003aa0: e197 b.n 8003dd2 <BSP_TS_GetState+0x372>
{
/* Get each touch coordinates */
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
8003aa2: 4b8d ldr r3, [pc, #564] ; (8003cd8 <BSP_TS_GetState+0x278>)
8003aa4: 681b ldr r3, [r3, #0]
8003aa6: 695b ldr r3, [r3, #20]
8003aa8: 4a8c ldr r2, [pc, #560] ; (8003cdc <BSP_TS_GetState+0x27c>)
8003aaa: 7812 ldrb r2, [r2, #0]
8003aac: b290 uxth r0, r2
8003aae: f107 0120 add.w r1, r7, #32
8003ab2: 6cba ldr r2, [r7, #72] ; 0x48
8003ab4: 0052 lsls r2, r2, #1
8003ab6: 188c adds r4, r1, r2
8003ab8: f107 0114 add.w r1, r7, #20
8003abc: 6cba ldr r2, [r7, #72] ; 0x48
8003abe: 0052 lsls r2, r2, #1
8003ac0: 440a add r2, r1
8003ac2: 4621 mov r1, r4
8003ac4: 4798 blx r3
if(tsOrientation == TS_SWAP_NONE)
8003ac6: 4b86 ldr r3, [pc, #536] ; (8003ce0 <BSP_TS_GetState+0x280>)
8003ac8: 781b ldrb r3, [r3, #0]
8003aca: 2b01 cmp r3, #1
8003acc: d11b bne.n 8003b06 <BSP_TS_GetState+0xa6>
{
x[index] = brute_x[index];
8003ace: 6cbb ldr r3, [r7, #72] ; 0x48
8003ad0: 005b lsls r3, r3, #1
8003ad2: f107 0250 add.w r2, r7, #80 ; 0x50
8003ad6: 4413 add r3, r2
8003ad8: f833 2c30 ldrh.w r2, [r3, #-48]
8003adc: 6cbb ldr r3, [r7, #72] ; 0x48
8003ade: 005b lsls r3, r3, #1
8003ae0: f107 0150 add.w r1, r7, #80 ; 0x50
8003ae4: 440b add r3, r1
8003ae6: f823 2c18 strh.w r2, [r3, #-24]
y[index] = brute_y[index];
8003aea: 6cbb ldr r3, [r7, #72] ; 0x48
8003aec: 005b lsls r3, r3, #1
8003aee: f107 0250 add.w r2, r7, #80 ; 0x50
8003af2: 4413 add r3, r2
8003af4: f833 2c3c ldrh.w r2, [r3, #-60]
8003af8: 6cbb ldr r3, [r7, #72] ; 0x48
8003afa: 005b lsls r3, r3, #1
8003afc: f107 0150 add.w r1, r7, #80 ; 0x50
8003b00: 440b add r3, r1
8003b02: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_X)
8003b06: 4b76 ldr r3, [pc, #472] ; (8003ce0 <BSP_TS_GetState+0x280>)
8003b08: 781b ldrb r3, [r3, #0]
8003b0a: f003 0302 and.w r3, r3, #2
8003b0e: 2b00 cmp r3, #0
8003b10: d010 beq.n 8003b34 <BSP_TS_GetState+0xd4>
{
x[index] = 4096 - brute_x[index];
8003b12: 6cbb ldr r3, [r7, #72] ; 0x48
8003b14: 005b lsls r3, r3, #1
8003b16: f107 0250 add.w r2, r7, #80 ; 0x50
8003b1a: 4413 add r3, r2
8003b1c: f833 3c30 ldrh.w r3, [r3, #-48]
8003b20: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
8003b24: b29a uxth r2, r3
8003b26: 6cbb ldr r3, [r7, #72] ; 0x48
8003b28: 005b lsls r3, r3, #1
8003b2a: f107 0150 add.w r1, r7, #80 ; 0x50
8003b2e: 440b add r3, r1
8003b30: f823 2c18 strh.w r2, [r3, #-24]
}
if(tsOrientation & TS_SWAP_Y)
8003b34: 4b6a ldr r3, [pc, #424] ; (8003ce0 <BSP_TS_GetState+0x280>)
8003b36: 781b ldrb r3, [r3, #0]
8003b38: f003 0304 and.w r3, r3, #4
8003b3c: 2b00 cmp r3, #0
8003b3e: d010 beq.n 8003b62 <BSP_TS_GetState+0x102>
{
y[index] = 4096 - brute_y[index];
8003b40: 6cbb ldr r3, [r7, #72] ; 0x48
8003b42: 005b lsls r3, r3, #1
8003b44: f107 0250 add.w r2, r7, #80 ; 0x50
8003b48: 4413 add r3, r2
8003b4a: f833 3c3c ldrh.w r3, [r3, #-60]
8003b4e: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
8003b52: b29a uxth r2, r3
8003b54: 6cbb ldr r3, [r7, #72] ; 0x48
8003b56: 005b lsls r3, r3, #1
8003b58: f107 0150 add.w r1, r7, #80 ; 0x50
8003b5c: 440b add r3, r1
8003b5e: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_XY)
8003b62: 4b5f ldr r3, [pc, #380] ; (8003ce0 <BSP_TS_GetState+0x280>)
8003b64: 781b ldrb r3, [r3, #0]
8003b66: f003 0308 and.w r3, r3, #8
8003b6a: 2b00 cmp r3, #0
8003b6c: d01b beq.n 8003ba6 <BSP_TS_GetState+0x146>
{
y[index] = brute_x[index];
8003b6e: 6cbb ldr r3, [r7, #72] ; 0x48
8003b70: 005b lsls r3, r3, #1
8003b72: f107 0250 add.w r2, r7, #80 ; 0x50
8003b76: 4413 add r3, r2
8003b78: f833 2c30 ldrh.w r2, [r3, #-48]
8003b7c: 6cbb ldr r3, [r7, #72] ; 0x48
8003b7e: 005b lsls r3, r3, #1
8003b80: f107 0150 add.w r1, r7, #80 ; 0x50
8003b84: 440b add r3, r1
8003b86: f823 2c24 strh.w r2, [r3, #-36]
x[index] = brute_y[index];
8003b8a: 6cbb ldr r3, [r7, #72] ; 0x48
8003b8c: 005b lsls r3, r3, #1
8003b8e: f107 0250 add.w r2, r7, #80 ; 0x50
8003b92: 4413 add r3, r2
8003b94: f833 2c3c ldrh.w r2, [r3, #-60]
8003b98: 6cbb ldr r3, [r7, #72] ; 0x48
8003b9a: 005b lsls r3, r3, #1
8003b9c: f107 0150 add.w r1, r7, #80 ; 0x50
8003ba0: 440b add r3, r1
8003ba2: f823 2c18 strh.w r2, [r3, #-24]
}
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
8003ba6: 6cbb ldr r3, [r7, #72] ; 0x48
8003ba8: 005b lsls r3, r3, #1
8003baa: f107 0250 add.w r2, r7, #80 ; 0x50
8003bae: 4413 add r3, r2
8003bb0: f833 3c18 ldrh.w r3, [r3, #-24]
8003bb4: 4619 mov r1, r3
8003bb6: 4a4b ldr r2, [pc, #300] ; (8003ce4 <BSP_TS_GetState+0x284>)
8003bb8: 6cbb ldr r3, [r7, #72] ; 0x48
8003bba: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003bbe: 4299 cmp r1, r3
8003bc0: d90e bls.n 8003be0 <BSP_TS_GetState+0x180>
8003bc2: 6cbb ldr r3, [r7, #72] ; 0x48
8003bc4: 005b lsls r3, r3, #1
8003bc6: f107 0250 add.w r2, r7, #80 ; 0x50
8003bca: 4413 add r3, r2
8003bcc: f833 2c18 ldrh.w r2, [r3, #-24]
8003bd0: 4944 ldr r1, [pc, #272] ; (8003ce4 <BSP_TS_GetState+0x284>)
8003bd2: 6cbb ldr r3, [r7, #72] ; 0x48
8003bd4: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003bd8: b29b uxth r3, r3
8003bda: 1ad3 subs r3, r2, r3
8003bdc: b29b uxth r3, r3
8003bde: e00d b.n 8003bfc <BSP_TS_GetState+0x19c>
8003be0: 4a40 ldr r2, [pc, #256] ; (8003ce4 <BSP_TS_GetState+0x284>)
8003be2: 6cbb ldr r3, [r7, #72] ; 0x48
8003be4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003be8: b29a uxth r2, r3
8003bea: 6cbb ldr r3, [r7, #72] ; 0x48
8003bec: 005b lsls r3, r3, #1
8003bee: f107 0150 add.w r1, r7, #80 ; 0x50
8003bf2: 440b add r3, r1
8003bf4: f833 3c18 ldrh.w r3, [r3, #-24]
8003bf8: 1ad3 subs r3, r2, r3
8003bfa: b29b uxth r3, r3
8003bfc: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
8003c00: 6cbb ldr r3, [r7, #72] ; 0x48
8003c02: 005b lsls r3, r3, #1
8003c04: f107 0250 add.w r2, r7, #80 ; 0x50
8003c08: 4413 add r3, r2
8003c0a: f833 3c24 ldrh.w r3, [r3, #-36]
8003c0e: 4619 mov r1, r3
8003c10: 4a35 ldr r2, [pc, #212] ; (8003ce8 <BSP_TS_GetState+0x288>)
8003c12: 6cbb ldr r3, [r7, #72] ; 0x48
8003c14: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c18: 4299 cmp r1, r3
8003c1a: d90e bls.n 8003c3a <BSP_TS_GetState+0x1da>
8003c1c: 6cbb ldr r3, [r7, #72] ; 0x48
8003c1e: 005b lsls r3, r3, #1
8003c20: f107 0250 add.w r2, r7, #80 ; 0x50
8003c24: 4413 add r3, r2
8003c26: f833 2c24 ldrh.w r2, [r3, #-36]
8003c2a: 492f ldr r1, [pc, #188] ; (8003ce8 <BSP_TS_GetState+0x288>)
8003c2c: 6cbb ldr r3, [r7, #72] ; 0x48
8003c2e: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003c32: b29b uxth r3, r3
8003c34: 1ad3 subs r3, r2, r3
8003c36: b29b uxth r3, r3
8003c38: e00d b.n 8003c56 <BSP_TS_GetState+0x1f6>
8003c3a: 4a2b ldr r2, [pc, #172] ; (8003ce8 <BSP_TS_GetState+0x288>)
8003c3c: 6cbb ldr r3, [r7, #72] ; 0x48
8003c3e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c42: b29a uxth r2, r3
8003c44: 6cbb ldr r3, [r7, #72] ; 0x48
8003c46: 005b lsls r3, r3, #1
8003c48: f107 0150 add.w r1, r7, #80 ; 0x50
8003c4c: 440b add r3, r1
8003c4e: f833 3c24 ldrh.w r3, [r3, #-36]
8003c52: 1ad3 subs r3, r2, r3
8003c54: b29b uxth r3, r3
8003c56: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if ((x_diff + y_diff) > 5)
8003c5a: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
8003c5e: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
8003c62: 4413 add r3, r2
8003c64: 2b05 cmp r3, #5
8003c66: dd17 ble.n 8003c98 <BSP_TS_GetState+0x238>
{
_x[index] = x[index];
8003c68: 6cbb ldr r3, [r7, #72] ; 0x48
8003c6a: 005b lsls r3, r3, #1
8003c6c: f107 0250 add.w r2, r7, #80 ; 0x50
8003c70: 4413 add r3, r2
8003c72: f833 3c18 ldrh.w r3, [r3, #-24]
8003c76: 4619 mov r1, r3
8003c78: 4a1a ldr r2, [pc, #104] ; (8003ce4 <BSP_TS_GetState+0x284>)
8003c7a: 6cbb ldr r3, [r7, #72] ; 0x48
8003c7c: f842 1023 str.w r1, [r2, r3, lsl #2]
_y[index] = y[index];
8003c80: 6cbb ldr r3, [r7, #72] ; 0x48
8003c82: 005b lsls r3, r3, #1
8003c84: f107 0250 add.w r2, r7, #80 ; 0x50
8003c88: 4413 add r3, r2
8003c8a: f833 3c24 ldrh.w r3, [r3, #-36]
8003c8e: 4619 mov r1, r3
8003c90: 4a15 ldr r2, [pc, #84] ; (8003ce8 <BSP_TS_GetState+0x288>)
8003c92: 6cbb ldr r3, [r7, #72] ; 0x48
8003c94: f842 1023 str.w r1, [r2, r3, lsl #2]
}
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
8003c98: 4b10 ldr r3, [pc, #64] ; (8003cdc <BSP_TS_GetState+0x27c>)
8003c9a: 781b ldrb r3, [r3, #0]
8003c9c: 2b70 cmp r3, #112 ; 0x70
8003c9e: d125 bne.n 8003cec <BSP_TS_GetState+0x28c>
{
TS_State->touchX[index] = x[index];
8003ca0: 6cbb ldr r3, [r7, #72] ; 0x48
8003ca2: 005b lsls r3, r3, #1
8003ca4: f107 0250 add.w r2, r7, #80 ; 0x50
8003ca8: 4413 add r3, r2
8003caa: f833 1c18 ldrh.w r1, [r3, #-24]
8003cae: 687a ldr r2, [r7, #4]
8003cb0: 6cbb ldr r3, [r7, #72] ; 0x48
8003cb2: 005b lsls r3, r3, #1
8003cb4: 4413 add r3, r2
8003cb6: 460a mov r2, r1
8003cb8: 805a strh r2, [r3, #2]
TS_State->touchY[index] = y[index];
8003cba: 6cbb ldr r3, [r7, #72] ; 0x48
8003cbc: 005b lsls r3, r3, #1
8003cbe: f107 0250 add.w r2, r7, #80 ; 0x50
8003cc2: 4413 add r3, r2
8003cc4: f833 1c24 ldrh.w r1, [r3, #-36]
8003cc8: 687a ldr r2, [r7, #4]
8003cca: 6cbb ldr r3, [r7, #72] ; 0x48
8003ccc: 3304 adds r3, #4
8003cce: 005b lsls r3, r3, #1
8003cd0: 4413 add r3, r2
8003cd2: 460a mov r2, r1
8003cd4: 809a strh r2, [r3, #4]
8003cd6: e02c b.n 8003d32 <BSP_TS_GetState+0x2d2>
8003cd8: 20000548 .word 0x20000548
8003cdc: 20000551 .word 0x20000551
8003ce0: 20000550 .word 0x20000550
8003ce4: 20000554 .word 0x20000554
8003ce8: 20000568 .word 0x20000568
}
else
{
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
8003cec: 4b42 ldr r3, [pc, #264] ; (8003df8 <BSP_TS_GetState+0x398>)
8003cee: 881b ldrh r3, [r3, #0]
8003cf0: 4619 mov r1, r3
8003cf2: 4a42 ldr r2, [pc, #264] ; (8003dfc <BSP_TS_GetState+0x39c>)
8003cf4: 6cbb ldr r3, [r7, #72] ; 0x48
8003cf6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003cfa: fb03 f301 mul.w r3, r3, r1
8003cfe: 0b1b lsrs r3, r3, #12
8003d00: b299 uxth r1, r3
8003d02: 687a ldr r2, [r7, #4]
8003d04: 6cbb ldr r3, [r7, #72] ; 0x48
8003d06: 005b lsls r3, r3, #1
8003d08: 4413 add r3, r2
8003d0a: 460a mov r2, r1
8003d0c: 805a strh r2, [r3, #2]
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
8003d0e: 4b3c ldr r3, [pc, #240] ; (8003e00 <BSP_TS_GetState+0x3a0>)
8003d10: 881b ldrh r3, [r3, #0]
8003d12: 4619 mov r1, r3
8003d14: 4a3b ldr r2, [pc, #236] ; (8003e04 <BSP_TS_GetState+0x3a4>)
8003d16: 6cbb ldr r3, [r7, #72] ; 0x48
8003d18: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003d1c: fb03 f301 mul.w r3, r3, r1
8003d20: 0b1b lsrs r3, r3, #12
8003d22: b299 uxth r1, r3
8003d24: 687a ldr r2, [r7, #4]
8003d26: 6cbb ldr r3, [r7, #72] ; 0x48
8003d28: 3304 adds r3, #4
8003d2a: 005b lsls r3, r3, #1
8003d2c: 4413 add r3, r2
8003d2e: 460a mov r2, r1
8003d30: 809a strh r2, [r3, #4]
}
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get touch info related to the current touch */
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
8003d32: 4b35 ldr r3, [pc, #212] ; (8003e08 <BSP_TS_GetState+0x3a8>)
8003d34: 781b ldrb r3, [r3, #0]
8003d36: b298 uxth r0, r3
8003d38: f107 010c add.w r1, r7, #12
8003d3c: f107 0210 add.w r2, r7, #16
8003d40: f107 0308 add.w r3, r7, #8
8003d44: 9300 str r3, [sp, #0]
8003d46: 460b mov r3, r1
8003d48: 6cb9 ldr r1, [r7, #72] ; 0x48
8003d4a: f7fc fe2f bl 80009ac <ft5336_TS_GetTouchInfo>
/* Update TS_State structure */
TS_State->touchWeight[index] = weight;
8003d4e: 693b ldr r3, [r7, #16]
8003d50: b2d9 uxtb r1, r3
8003d52: 687a ldr r2, [r7, #4]
8003d54: 6cbb ldr r3, [r7, #72] ; 0x48
8003d56: 4413 add r3, r2
8003d58: 3316 adds r3, #22
8003d5a: 460a mov r2, r1
8003d5c: 701a strb r2, [r3, #0]
TS_State->touchArea[index] = area;
8003d5e: 68fb ldr r3, [r7, #12]
8003d60: b2d9 uxtb r1, r3
8003d62: 687a ldr r2, [r7, #4]
8003d64: 6cbb ldr r3, [r7, #72] ; 0x48
8003d66: 4413 add r3, r2
8003d68: 3320 adds r3, #32
8003d6a: 460a mov r2, r1
8003d6c: 701a strb r2, [r3, #0]
/* Remap touch event */
switch(event)
8003d6e: 68bb ldr r3, [r7, #8]
8003d70: 2b03 cmp r3, #3
8003d72: d827 bhi.n 8003dc4 <BSP_TS_GetState+0x364>
8003d74: a201 add r2, pc, #4 ; (adr r2, 8003d7c <BSP_TS_GetState+0x31c>)
8003d76: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003d7a: bf00 nop
8003d7c: 08003d8d .word 0x08003d8d
8003d80: 08003d9b .word 0x08003d9b
8003d84: 08003da9 .word 0x08003da9
8003d88: 08003db7 .word 0x08003db7
{
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
8003d8c: 687a ldr r2, [r7, #4]
8003d8e: 6cbb ldr r3, [r7, #72] ; 0x48
8003d90: 4413 add r3, r2
8003d92: 331b adds r3, #27
8003d94: 2201 movs r2, #1
8003d96: 701a strb r2, [r3, #0]
break;
8003d98: e018 b.n 8003dcc <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
8003d9a: 687a ldr r2, [r7, #4]
8003d9c: 6cbb ldr r3, [r7, #72] ; 0x48
8003d9e: 4413 add r3, r2
8003da0: 331b adds r3, #27
8003da2: 2202 movs r2, #2
8003da4: 701a strb r2, [r3, #0]
break;
8003da6: e011 b.n 8003dcc <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_CONTACT :
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
8003da8: 687a ldr r2, [r7, #4]
8003daa: 6cbb ldr r3, [r7, #72] ; 0x48
8003dac: 4413 add r3, r2
8003dae: 331b adds r3, #27
8003db0: 2203 movs r2, #3
8003db2: 701a strb r2, [r3, #0]
break;
8003db4: e00a b.n 8003dcc <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
8003db6: 687a ldr r2, [r7, #4]
8003db8: 6cbb ldr r3, [r7, #72] ; 0x48
8003dba: 4413 add r3, r2
8003dbc: 331b adds r3, #27
8003dbe: 2200 movs r2, #0
8003dc0: 701a strb r2, [r3, #0]
break;
8003dc2: e003 b.n 8003dcc <BSP_TS_GetState+0x36c>
default :
ts_status = TS_ERROR;
8003dc4: 2301 movs r3, #1
8003dc6: f887 304f strb.w r3, [r7, #79] ; 0x4f
break;
8003dca: bf00 nop
for(index=0; index < TS_State->touchDetected; index++)
8003dcc: 6cbb ldr r3, [r7, #72] ; 0x48
8003dce: 3301 adds r3, #1
8003dd0: 64bb str r3, [r7, #72] ; 0x48
8003dd2: 687b ldr r3, [r7, #4]
8003dd4: 781b ldrb r3, [r3, #0]
8003dd6: 461a mov r2, r3
8003dd8: 6cbb ldr r3, [r7, #72] ; 0x48
8003dda: 4293 cmp r3, r2
8003ddc: f4ff ae61 bcc.w 8003aa2 <BSP_TS_GetState+0x42>
} /* of for(index=0; index < TS_State->touchDetected; index++) */
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get gesture Id */
ts_status = BSP_TS_Get_GestureId(TS_State);
8003de0: 6878 ldr r0, [r7, #4]
8003de2: f000 f813 bl 8003e0c <BSP_TS_Get_GestureId>
8003de6: 4603 mov r3, r0
8003de8: f887 304f strb.w r3, [r7, #79] ; 0x4f
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
} /* end of if(TS_State->touchDetected != 0) */
return (ts_status);
8003dec: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
}
8003df0: 4618 mov r0, r3
8003df2: 3754 adds r7, #84 ; 0x54
8003df4: 46bd mov sp, r7
8003df6: bd90 pop {r4, r7, pc}
8003df8: 2000054c .word 0x2000054c
8003dfc: 20000554 .word 0x20000554
8003e00: 2000054e .word 0x2000054e
8003e04: 20000568 .word 0x20000568
8003e08: 20000551 .word 0x20000551
08003e0c <BSP_TS_Get_GestureId>:
* @brief Update gesture Id following a touch detected.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
{
8003e0c: b580 push {r7, lr}
8003e0e: b084 sub sp, #16
8003e10: af00 add r7, sp, #0
8003e12: 6078 str r0, [r7, #4]
uint32_t gestureId = 0;
8003e14: 2300 movs r3, #0
8003e16: 60bb str r3, [r7, #8]
uint8_t ts_status = TS_OK;
8003e18: 2300 movs r3, #0
8003e1a: 73fb strb r3, [r7, #15]
/* Get gesture Id */
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
8003e1c: 4b1f ldr r3, [pc, #124] ; (8003e9c <BSP_TS_Get_GestureId+0x90>)
8003e1e: 781b ldrb r3, [r3, #0]
8003e20: b29b uxth r3, r3
8003e22: f107 0208 add.w r2, r7, #8
8003e26: 4611 mov r1, r2
8003e28: 4618 mov r0, r3
8003e2a: f7fc fda6 bl 800097a <ft5336_TS_GetGestureID>
/* Remap gesture Id to a TS_GestureIdTypeDef value */
switch(gestureId)
8003e2e: 68bb ldr r3, [r7, #8]
8003e30: 2b18 cmp r3, #24
8003e32: d01b beq.n 8003e6c <BSP_TS_Get_GestureId+0x60>
8003e34: 2b18 cmp r3, #24
8003e36: d806 bhi.n 8003e46 <BSP_TS_Get_GestureId+0x3a>
8003e38: 2b10 cmp r3, #16
8003e3a: d00f beq.n 8003e5c <BSP_TS_Get_GestureId+0x50>
8003e3c: 2b14 cmp r3, #20
8003e3e: d011 beq.n 8003e64 <BSP_TS_Get_GestureId+0x58>
8003e40: 2b00 cmp r3, #0
8003e42: d007 beq.n 8003e54 <BSP_TS_Get_GestureId+0x48>
8003e44: e022 b.n 8003e8c <BSP_TS_Get_GestureId+0x80>
8003e46: 2b40 cmp r3, #64 ; 0x40
8003e48: d018 beq.n 8003e7c <BSP_TS_Get_GestureId+0x70>
8003e4a: 2b49 cmp r3, #73 ; 0x49
8003e4c: d01a beq.n 8003e84 <BSP_TS_Get_GestureId+0x78>
8003e4e: 2b1c cmp r3, #28
8003e50: d010 beq.n 8003e74 <BSP_TS_Get_GestureId+0x68>
8003e52: e01b b.n 8003e8c <BSP_TS_Get_GestureId+0x80>
{
case FT5336_GEST_ID_NO_GESTURE :
TS_State->gestureId = GEST_ID_NO_GESTURE;
8003e54: 687b ldr r3, [r7, #4]
8003e56: 2200 movs r2, #0
8003e58: 629a str r2, [r3, #40] ; 0x28
break;
8003e5a: e01a b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_UP :
TS_State->gestureId = GEST_ID_MOVE_UP;
8003e5c: 687b ldr r3, [r7, #4]
8003e5e: 2201 movs r2, #1
8003e60: 629a str r2, [r3, #40] ; 0x28
break;
8003e62: e016 b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_RIGHT :
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
8003e64: 687b ldr r3, [r7, #4]
8003e66: 2202 movs r2, #2
8003e68: 629a str r2, [r3, #40] ; 0x28
break;
8003e6a: e012 b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_DOWN :
TS_State->gestureId = GEST_ID_MOVE_DOWN;
8003e6c: 687b ldr r3, [r7, #4]
8003e6e: 2203 movs r2, #3
8003e70: 629a str r2, [r3, #40] ; 0x28
break;
8003e72: e00e b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_LEFT :
TS_State->gestureId = GEST_ID_MOVE_LEFT;
8003e74: 687b ldr r3, [r7, #4]
8003e76: 2204 movs r2, #4
8003e78: 629a str r2, [r3, #40] ; 0x28
break;
8003e7a: e00a b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_IN :
TS_State->gestureId = GEST_ID_ZOOM_IN;
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 2205 movs r2, #5
8003e80: 629a str r2, [r3, #40] ; 0x28
break;
8003e82: e006 b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_OUT :
TS_State->gestureId = GEST_ID_ZOOM_OUT;
8003e84: 687b ldr r3, [r7, #4]
8003e86: 2206 movs r2, #6
8003e88: 629a str r2, [r3, #40] ; 0x28
break;
8003e8a: e002 b.n 8003e92 <BSP_TS_Get_GestureId+0x86>
default :
ts_status = TS_ERROR;
8003e8c: 2301 movs r3, #1
8003e8e: 73fb strb r3, [r7, #15]
break;
8003e90: bf00 nop
} /* of switch(gestureId) */
return(ts_status);
8003e92: 7bfb ldrb r3, [r7, #15]
}
8003e94: 4618 mov r0, r3
8003e96: 3710 adds r7, #16
8003e98: 46bd mov sp, r7
8003e9a: bd80 pop {r7, pc}
8003e9c: 20000551 .word 0x20000551
08003ea0 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8003ea0: b580 push {r7, lr}
8003ea2: b082 sub sp, #8
8003ea4: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
8003ea6: 4b11 ldr r3, [pc, #68] ; (8003eec <HAL_MspInit+0x4c>)
8003ea8: 6c1b ldr r3, [r3, #64] ; 0x40
8003eaa: 4a10 ldr r2, [pc, #64] ; (8003eec <HAL_MspInit+0x4c>)
8003eac: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003eb0: 6413 str r3, [r2, #64] ; 0x40
8003eb2: 4b0e ldr r3, [pc, #56] ; (8003eec <HAL_MspInit+0x4c>)
8003eb4: 6c1b ldr r3, [r3, #64] ; 0x40
8003eb6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003eba: 607b str r3, [r7, #4]
8003ebc: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003ebe: 4b0b ldr r3, [pc, #44] ; (8003eec <HAL_MspInit+0x4c>)
8003ec0: 6c5b ldr r3, [r3, #68] ; 0x44
8003ec2: 4a0a ldr r2, [pc, #40] ; (8003eec <HAL_MspInit+0x4c>)
8003ec4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8003ec8: 6453 str r3, [r2, #68] ; 0x44
8003eca: 4b08 ldr r3, [pc, #32] ; (8003eec <HAL_MspInit+0x4c>)
8003ecc: 6c5b ldr r3, [r3, #68] ; 0x44
8003ece: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003ed2: 603b str r3, [r7, #0]
8003ed4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8003ed6: 2200 movs r2, #0
8003ed8: 210f movs r1, #15
8003eda: f06f 0001 mvn.w r0, #1
8003ede: f001 fa1b bl 8005318 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8003ee2: bf00 nop
8003ee4: 3708 adds r7, #8
8003ee6: 46bd mov sp, r7
8003ee8: bd80 pop {r7, pc}
8003eea: bf00 nop
8003eec: 40023800 .word 0x40023800
08003ef0 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8003ef0: b580 push {r7, lr}
8003ef2: b08c sub sp, #48 ; 0x30
8003ef4: af00 add r7, sp, #0
8003ef6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003ef8: f107 031c add.w r3, r7, #28
8003efc: 2200 movs r2, #0
8003efe: 601a str r2, [r3, #0]
8003f00: 605a str r2, [r3, #4]
8003f02: 609a str r2, [r3, #8]
8003f04: 60da str r2, [r3, #12]
8003f06: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
8003f08: 687b ldr r3, [r7, #4]
8003f0a: 681b ldr r3, [r3, #0]
8003f0c: 4a2a ldr r2, [pc, #168] ; (8003fb8 <HAL_ADC_MspInit+0xc8>)
8003f0e: 4293 cmp r3, r2
8003f10: d124 bne.n 8003f5c <HAL_ADC_MspInit+0x6c>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8003f12: 4b2a ldr r3, [pc, #168] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f14: 6c5b ldr r3, [r3, #68] ; 0x44
8003f16: 4a29 ldr r2, [pc, #164] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f18: f443 7380 orr.w r3, r3, #256 ; 0x100
8003f1c: 6453 str r3, [r2, #68] ; 0x44
8003f1e: 4b27 ldr r3, [pc, #156] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f20: 6c5b ldr r3, [r3, #68] ; 0x44
8003f22: f403 7380 and.w r3, r3, #256 ; 0x100
8003f26: 61bb str r3, [r7, #24]
8003f28: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
8003f2a: 4b24 ldr r3, [pc, #144] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f2c: 6b1b ldr r3, [r3, #48] ; 0x30
8003f2e: 4a23 ldr r2, [pc, #140] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f30: f043 0301 orr.w r3, r3, #1
8003f34: 6313 str r3, [r2, #48] ; 0x30
8003f36: 4b21 ldr r3, [pc, #132] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f38: 6b1b ldr r3, [r3, #48] ; 0x30
8003f3a: f003 0301 and.w r3, r3, #1
8003f3e: 617b str r3, [r7, #20]
8003f40: 697b ldr r3, [r7, #20]
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
8003f42: 2301 movs r3, #1
8003f44: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003f46: 2303 movs r3, #3
8003f48: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003f4a: 2300 movs r3, #0
8003f4c: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8003f4e: f107 031c add.w r3, r7, #28
8003f52: 4619 mov r1, r3
8003f54: 481a ldr r0, [pc, #104] ; (8003fc0 <HAL_ADC_MspInit+0xd0>)
8003f56: f003 f98f bl 8007278 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
8003f5a: e029 b.n 8003fb0 <HAL_ADC_MspInit+0xc0>
else if(hadc->Instance==ADC3)
8003f5c: 687b ldr r3, [r7, #4]
8003f5e: 681b ldr r3, [r3, #0]
8003f60: 4a18 ldr r2, [pc, #96] ; (8003fc4 <HAL_ADC_MspInit+0xd4>)
8003f62: 4293 cmp r3, r2
8003f64: d124 bne.n 8003fb0 <HAL_ADC_MspInit+0xc0>
__HAL_RCC_ADC3_CLK_ENABLE();
8003f66: 4b15 ldr r3, [pc, #84] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f68: 6c5b ldr r3, [r3, #68] ; 0x44
8003f6a: 4a14 ldr r2, [pc, #80] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f6c: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003f70: 6453 str r3, [r2, #68] ; 0x44
8003f72: 4b12 ldr r3, [pc, #72] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f74: 6c5b ldr r3, [r3, #68] ; 0x44
8003f76: f403 6380 and.w r3, r3, #1024 ; 0x400
8003f7a: 613b str r3, [r7, #16]
8003f7c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003f7e: 4b0f ldr r3, [pc, #60] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f80: 6b1b ldr r3, [r3, #48] ; 0x30
8003f82: 4a0e ldr r2, [pc, #56] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f84: f043 0320 orr.w r3, r3, #32
8003f88: 6313 str r3, [r2, #48] ; 0x30
8003f8a: 4b0c ldr r3, [pc, #48] ; (8003fbc <HAL_ADC_MspInit+0xcc>)
8003f8c: 6b1b ldr r3, [r3, #48] ; 0x30
8003f8e: f003 0320 and.w r3, r3, #32
8003f92: 60fb str r3, [r7, #12]
8003f94: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
8003f96: f44f 63e0 mov.w r3, #1792 ; 0x700
8003f9a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003f9c: 2303 movs r3, #3
8003f9e: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003fa0: 2300 movs r3, #0
8003fa2: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8003fa4: f107 031c add.w r3, r7, #28
8003fa8: 4619 mov r1, r3
8003faa: 4807 ldr r0, [pc, #28] ; (8003fc8 <HAL_ADC_MspInit+0xd8>)
8003fac: f003 f964 bl 8007278 <HAL_GPIO_Init>
}
8003fb0: bf00 nop
8003fb2: 3730 adds r7, #48 ; 0x30
8003fb4: 46bd mov sp, r7
8003fb6: bd80 pop {r7, pc}
8003fb8: 40012000 .word 0x40012000
8003fbc: 40023800 .word 0x40023800
8003fc0: 40020000 .word 0x40020000
8003fc4: 40012200 .word 0x40012200
8003fc8: 40021400 .word 0x40021400
08003fcc <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
8003fcc: b480 push {r7}
8003fce: b085 sub sp, #20
8003fd0: af00 add r7, sp, #0
8003fd2: 6078 str r0, [r7, #4]
if(hcrc->Instance==CRC)
8003fd4: 687b ldr r3, [r7, #4]
8003fd6: 681b ldr r3, [r3, #0]
8003fd8: 4a0a ldr r2, [pc, #40] ; (8004004 <HAL_CRC_MspInit+0x38>)
8003fda: 4293 cmp r3, r2
8003fdc: d10b bne.n 8003ff6 <HAL_CRC_MspInit+0x2a>
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
8003fde: 4b0a ldr r3, [pc, #40] ; (8004008 <HAL_CRC_MspInit+0x3c>)
8003fe0: 6b1b ldr r3, [r3, #48] ; 0x30
8003fe2: 4a09 ldr r2, [pc, #36] ; (8004008 <HAL_CRC_MspInit+0x3c>)
8003fe4: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8003fe8: 6313 str r3, [r2, #48] ; 0x30
8003fea: 4b07 ldr r3, [pc, #28] ; (8004008 <HAL_CRC_MspInit+0x3c>)
8003fec: 6b1b ldr r3, [r3, #48] ; 0x30
8003fee: f403 5380 and.w r3, r3, #4096 ; 0x1000
8003ff2: 60fb str r3, [r7, #12]
8003ff4: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
8003ff6: bf00 nop
8003ff8: 3714 adds r7, #20
8003ffa: 46bd mov sp, r7
8003ffc: f85d 7b04 ldr.w r7, [sp], #4
8004000: 4770 bx lr
8004002: bf00 nop
8004004: 40023000 .word 0x40023000
8004008: 40023800 .word 0x40023800
0800400c <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
800400c: b580 push {r7, lr}
800400e: b08a sub sp, #40 ; 0x28
8004010: af00 add r7, sp, #0
8004012: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004014: f107 0314 add.w r3, r7, #20
8004018: 2200 movs r2, #0
800401a: 601a str r2, [r3, #0]
800401c: 605a str r2, [r3, #4]
800401e: 609a str r2, [r3, #8]
8004020: 60da str r2, [r3, #12]
8004022: 611a str r2, [r3, #16]
if(hdac->Instance==DAC)
8004024: 687b ldr r3, [r7, #4]
8004026: 681b ldr r3, [r3, #0]
8004028: 4a19 ldr r2, [pc, #100] ; (8004090 <HAL_DAC_MspInit+0x84>)
800402a: 4293 cmp r3, r2
800402c: d12b bne.n 8004086 <HAL_DAC_MspInit+0x7a>
{
/* USER CODE BEGIN DAC_MspInit 0 */
/* USER CODE END DAC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC_CLK_ENABLE();
800402e: 4b19 ldr r3, [pc, #100] ; (8004094 <HAL_DAC_MspInit+0x88>)
8004030: 6c1b ldr r3, [r3, #64] ; 0x40
8004032: 4a18 ldr r2, [pc, #96] ; (8004094 <HAL_DAC_MspInit+0x88>)
8004034: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8004038: 6413 str r3, [r2, #64] ; 0x40
800403a: 4b16 ldr r3, [pc, #88] ; (8004094 <HAL_DAC_MspInit+0x88>)
800403c: 6c1b ldr r3, [r3, #64] ; 0x40
800403e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8004042: 613b str r3, [r7, #16]
8004044: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8004046: 4b13 ldr r3, [pc, #76] ; (8004094 <HAL_DAC_MspInit+0x88>)
8004048: 6b1b ldr r3, [r3, #48] ; 0x30
800404a: 4a12 ldr r2, [pc, #72] ; (8004094 <HAL_DAC_MspInit+0x88>)
800404c: f043 0301 orr.w r3, r3, #1
8004050: 6313 str r3, [r2, #48] ; 0x30
8004052: 4b10 ldr r3, [pc, #64] ; (8004094 <HAL_DAC_MspInit+0x88>)
8004054: 6b1b ldr r3, [r3, #48] ; 0x30
8004056: f003 0301 and.w r3, r3, #1
800405a: 60fb str r3, [r7, #12]
800405c: 68fb ldr r3, [r7, #12]
/**DAC GPIO Configuration
PA4 ------> DAC_OUT1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
800405e: 2310 movs r3, #16
8004060: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8004062: 2303 movs r3, #3
8004064: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004066: 2300 movs r3, #0
8004068: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800406a: f107 0314 add.w r3, r7, #20
800406e: 4619 mov r1, r3
8004070: 4809 ldr r0, [pc, #36] ; (8004098 <HAL_DAC_MspInit+0x8c>)
8004072: f003 f901 bl 8007278 <HAL_GPIO_Init>
/* DAC interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8004076: 2200 movs r2, #0
8004078: 2100 movs r1, #0
800407a: 2036 movs r0, #54 ; 0x36
800407c: f001 f94c bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8004080: 2036 movs r0, #54 ; 0x36
8004082: f001 f965 bl 8005350 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN DAC_MspInit 1 */
/* USER CODE END DAC_MspInit 1 */
}
}
8004086: bf00 nop
8004088: 3728 adds r7, #40 ; 0x28
800408a: 46bd mov sp, r7
800408c: bd80 pop {r7, pc}
800408e: bf00 nop
8004090: 40007400 .word 0x40007400
8004094: 40023800 .word 0x40023800
8004098: 40020000 .word 0x40020000
0800409c <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
800409c: b480 push {r7}
800409e: b085 sub sp, #20
80040a0: af00 add r7, sp, #0
80040a2: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
80040a4: 687b ldr r3, [r7, #4]
80040a6: 681b ldr r3, [r3, #0]
80040a8: 4a0a ldr r2, [pc, #40] ; (80040d4 <HAL_DMA2D_MspInit+0x38>)
80040aa: 4293 cmp r3, r2
80040ac: d10b bne.n 80040c6 <HAL_DMA2D_MspInit+0x2a>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
80040ae: 4b0a ldr r3, [pc, #40] ; (80040d8 <HAL_DMA2D_MspInit+0x3c>)
80040b0: 6b1b ldr r3, [r3, #48] ; 0x30
80040b2: 4a09 ldr r2, [pc, #36] ; (80040d8 <HAL_DMA2D_MspInit+0x3c>)
80040b4: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80040b8: 6313 str r3, [r2, #48] ; 0x30
80040ba: 4b07 ldr r3, [pc, #28] ; (80040d8 <HAL_DMA2D_MspInit+0x3c>)
80040bc: 6b1b ldr r3, [r3, #48] ; 0x30
80040be: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80040c2: 60fb str r3, [r7, #12]
80040c4: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
80040c6: bf00 nop
80040c8: 3714 adds r7, #20
80040ca: 46bd mov sp, r7
80040cc: f85d 7b04 ldr.w r7, [sp], #4
80040d0: 4770 bx lr
80040d2: bf00 nop
80040d4: 4002b000 .word 0x4002b000
80040d8: 40023800 .word 0x40023800
080040dc <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
80040dc: b580 push {r7, lr}
80040de: b08e sub sp, #56 ; 0x38
80040e0: af00 add r7, sp, #0
80040e2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80040e4: f107 0324 add.w r3, r7, #36 ; 0x24
80040e8: 2200 movs r2, #0
80040ea: 601a str r2, [r3, #0]
80040ec: 605a str r2, [r3, #4]
80040ee: 609a str r2, [r3, #8]
80040f0: 60da str r2, [r3, #12]
80040f2: 611a str r2, [r3, #16]
if(hltdc->Instance==LTDC)
80040f4: 687b ldr r3, [r7, #4]
80040f6: 681b ldr r3, [r3, #0]
80040f8: 4a55 ldr r2, [pc, #340] ; (8004250 <HAL_LTDC_MspInit+0x174>)
80040fa: 4293 cmp r3, r2
80040fc: f040 80a3 bne.w 8004246 <HAL_LTDC_MspInit+0x16a>
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8004100: 4b54 ldr r3, [pc, #336] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004102: 6c5b ldr r3, [r3, #68] ; 0x44
8004104: 4a53 ldr r2, [pc, #332] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004106: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800410a: 6453 str r3, [r2, #68] ; 0x44
800410c: 4b51 ldr r3, [pc, #324] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800410e: 6c5b ldr r3, [r3, #68] ; 0x44
8004110: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8004114: 623b str r3, [r7, #32]
8004116: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOE_CLK_ENABLE();
8004118: 4b4e ldr r3, [pc, #312] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800411a: 6b1b ldr r3, [r3, #48] ; 0x30
800411c: 4a4d ldr r2, [pc, #308] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800411e: f043 0310 orr.w r3, r3, #16
8004122: 6313 str r3, [r2, #48] ; 0x30
8004124: 4b4b ldr r3, [pc, #300] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004126: 6b1b ldr r3, [r3, #48] ; 0x30
8004128: f003 0310 and.w r3, r3, #16
800412c: 61fb str r3, [r7, #28]
800412e: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8004130: 4b48 ldr r3, [pc, #288] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004132: 6b1b ldr r3, [r3, #48] ; 0x30
8004134: 4a47 ldr r2, [pc, #284] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004136: f443 7300 orr.w r3, r3, #512 ; 0x200
800413a: 6313 str r3, [r2, #48] ; 0x30
800413c: 4b45 ldr r3, [pc, #276] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800413e: 6b1b ldr r3, [r3, #48] ; 0x30
8004140: f403 7300 and.w r3, r3, #512 ; 0x200
8004144: 61bb str r3, [r7, #24]
8004146: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOK_CLK_ENABLE();
8004148: 4b42 ldr r3, [pc, #264] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800414a: 6b1b ldr r3, [r3, #48] ; 0x30
800414c: 4a41 ldr r2, [pc, #260] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800414e: f443 6380 orr.w r3, r3, #1024 ; 0x400
8004152: 6313 str r3, [r2, #48] ; 0x30
8004154: 4b3f ldr r3, [pc, #252] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004156: 6b1b ldr r3, [r3, #48] ; 0x30
8004158: f403 6380 and.w r3, r3, #1024 ; 0x400
800415c: 617b str r3, [r7, #20]
800415e: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8004160: 4b3c ldr r3, [pc, #240] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004162: 6b1b ldr r3, [r3, #48] ; 0x30
8004164: 4a3b ldr r2, [pc, #236] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004166: f043 0340 orr.w r3, r3, #64 ; 0x40
800416a: 6313 str r3, [r2, #48] ; 0x30
800416c: 4b39 ldr r3, [pc, #228] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800416e: 6b1b ldr r3, [r3, #48] ; 0x30
8004170: f003 0340 and.w r3, r3, #64 ; 0x40
8004174: 613b str r3, [r7, #16]
8004176: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
8004178: 4b36 ldr r3, [pc, #216] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800417a: 6b1b ldr r3, [r3, #48] ; 0x30
800417c: 4a35 ldr r2, [pc, #212] ; (8004254 <HAL_LTDC_MspInit+0x178>)
800417e: f443 7380 orr.w r3, r3, #256 ; 0x100
8004182: 6313 str r3, [r2, #48] ; 0x30
8004184: 4b33 ldr r3, [pc, #204] ; (8004254 <HAL_LTDC_MspInit+0x178>)
8004186: 6b1b ldr r3, [r3, #48] ; 0x30
8004188: f403 7380 and.w r3, r3, #256 ; 0x100
800418c: 60fb str r3, [r7, #12]
800418e: 68fb ldr r3, [r7, #12]
PJ3 ------> LTDC_R4
PJ2 ------> LTDC_R3
PJ0 ------> LTDC_R1
PJ1 ------> LTDC_R2
*/
GPIO_InitStruct.Pin = LCD_B0_Pin;
8004190: 2310 movs r3, #16
8004192: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004194: 2302 movs r3, #2
8004196: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004198: 2300 movs r3, #0
800419a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800419c: 2300 movs r3, #0
800419e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041a0: 230e movs r3, #14
80041a2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct);
80041a4: f107 0324 add.w r3, r7, #36 ; 0x24
80041a8: 4619 mov r1, r3
80041aa: 482b ldr r0, [pc, #172] ; (8004258 <HAL_LTDC_MspInit+0x17c>)
80041ac: f003 f864 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin
80041b0: f64e 73ff movw r3, #61439 ; 0xefff
80041b4: 627b str r3, [r7, #36] ; 0x24
|LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin
|LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin
|LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041b6: 2302 movs r3, #2
80041b8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041ba: 2300 movs r3, #0
80041bc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80041be: 2300 movs r3, #0
80041c0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041c2: 230e movs r3, #14
80041c4: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
80041c6: f107 0324 add.w r3, r7, #36 ; 0x24
80041ca: 4619 mov r1, r3
80041cc: 4823 ldr r0, [pc, #140] ; (800425c <HAL_LTDC_MspInit+0x180>)
80041ce: f003 f853 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin
80041d2: 23f7 movs r3, #247 ; 0xf7
80041d4: 627b str r3, [r7, #36] ; 0x24
|LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041d6: 2302 movs r3, #2
80041d8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041da: 2300 movs r3, #0
80041dc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80041de: 2300 movs r3, #0
80041e0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041e2: 230e movs r3, #14
80041e4: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
80041e6: f107 0324 add.w r3, r7, #36 ; 0x24
80041ea: 4619 mov r1, r3
80041ec: 481c ldr r0, [pc, #112] ; (8004260 <HAL_LTDC_MspInit+0x184>)
80041ee: f003 f843 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B4_Pin;
80041f2: f44f 5380 mov.w r3, #4096 ; 0x1000
80041f6: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041f8: 2302 movs r3, #2
80041fa: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041fc: 2300 movs r3, #0
80041fe: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004200: 2300 movs r3, #0
8004202: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8004204: 2309 movs r3, #9
8004206: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct);
8004208: f107 0324 add.w r3, r7, #36 ; 0x24
800420c: 4619 mov r1, r3
800420e: 4815 ldr r0, [pc, #84] ; (8004264 <HAL_LTDC_MspInit+0x188>)
8004210: f003 f832 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin;
8004214: f44f 4346 mov.w r3, #50688 ; 0xc600
8004218: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800421a: 2302 movs r3, #2
800421c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800421e: 2300 movs r3, #0
8004220: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004222: 2300 movs r3, #0
8004224: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8004226: 230e movs r3, #14
8004228: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
800422a: f107 0324 add.w r3, r7, #36 ; 0x24
800422e: 4619 mov r1, r3
8004230: 480d ldr r0, [pc, #52] ; (8004268 <HAL_LTDC_MspInit+0x18c>)
8004232: f003 f821 bl 8007278 <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
8004236: 2200 movs r2, #0
8004238: 2105 movs r1, #5
800423a: 2058 movs r0, #88 ; 0x58
800423c: f001 f86c bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
8004240: 2058 movs r0, #88 ; 0x58
8004242: f001 f885 bl 8005350 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
8004246: bf00 nop
8004248: 3738 adds r7, #56 ; 0x38
800424a: 46bd mov sp, r7
800424c: bd80 pop {r7, pc}
800424e: bf00 nop
8004250: 40016800 .word 0x40016800
8004254: 40023800 .word 0x40023800
8004258: 40021000 .word 0x40021000
800425c: 40022400 .word 0x40022400
8004260: 40022800 .word 0x40022800
8004264: 40021800 .word 0x40021800
8004268: 40022000 .word 0x40022000
0800426c <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
800426c: b480 push {r7}
800426e: b085 sub sp, #20
8004270: af00 add r7, sp, #0
8004272: 6078 str r0, [r7, #4]
if(hrng->Instance==RNG)
8004274: 687b ldr r3, [r7, #4]
8004276: 681b ldr r3, [r3, #0]
8004278: 4a0a ldr r2, [pc, #40] ; (80042a4 <HAL_RNG_MspInit+0x38>)
800427a: 4293 cmp r3, r2
800427c: d10b bne.n 8004296 <HAL_RNG_MspInit+0x2a>
{
/* USER CODE BEGIN RNG_MspInit 0 */
/* USER CODE END RNG_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RNG_CLK_ENABLE();
800427e: 4b0a ldr r3, [pc, #40] ; (80042a8 <HAL_RNG_MspInit+0x3c>)
8004280: 6b5b ldr r3, [r3, #52] ; 0x34
8004282: 4a09 ldr r2, [pc, #36] ; (80042a8 <HAL_RNG_MspInit+0x3c>)
8004284: f043 0340 orr.w r3, r3, #64 ; 0x40
8004288: 6353 str r3, [r2, #52] ; 0x34
800428a: 4b07 ldr r3, [pc, #28] ; (80042a8 <HAL_RNG_MspInit+0x3c>)
800428c: 6b5b ldr r3, [r3, #52] ; 0x34
800428e: f003 0340 and.w r3, r3, #64 ; 0x40
8004292: 60fb str r3, [r7, #12]
8004294: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN RNG_MspInit 1 */
/* USER CODE END RNG_MspInit 1 */
}
}
8004296: bf00 nop
8004298: 3714 adds r7, #20
800429a: 46bd mov sp, r7
800429c: f85d 7b04 ldr.w r7, [sp], #4
80042a0: 4770 bx lr
80042a2: bf00 nop
80042a4: 50060800 .word 0x50060800
80042a8: 40023800 .word 0x40023800
080042ac <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80042ac: b580 push {r7, lr}
80042ae: b08a sub sp, #40 ; 0x28
80042b0: af00 add r7, sp, #0
80042b2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80042b4: f107 0314 add.w r3, r7, #20
80042b8: 2200 movs r2, #0
80042ba: 601a str r2, [r3, #0]
80042bc: 605a str r2, [r3, #4]
80042be: 609a str r2, [r3, #8]
80042c0: 60da str r2, [r3, #12]
80042c2: 611a str r2, [r3, #16]
if(hspi->Instance==SPI2)
80042c4: 687b ldr r3, [r7, #4]
80042c6: 681b ldr r3, [r3, #0]
80042c8: 4a2d ldr r2, [pc, #180] ; (8004380 <HAL_SPI_MspInit+0xd4>)
80042ca: 4293 cmp r3, r2
80042cc: d154 bne.n 8004378 <HAL_SPI_MspInit+0xcc>
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
80042ce: 4b2d ldr r3, [pc, #180] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042d0: 6c1b ldr r3, [r3, #64] ; 0x40
80042d2: 4a2c ldr r2, [pc, #176] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042d4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80042d8: 6413 str r3, [r2, #64] ; 0x40
80042da: 4b2a ldr r3, [pc, #168] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042dc: 6c1b ldr r3, [r3, #64] ; 0x40
80042de: f403 4380 and.w r3, r3, #16384 ; 0x4000
80042e2: 613b str r3, [r7, #16]
80042e4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
80042e6: 4b27 ldr r3, [pc, #156] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042e8: 6b1b ldr r3, [r3, #48] ; 0x30
80042ea: 4a26 ldr r2, [pc, #152] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042ec: f443 7380 orr.w r3, r3, #256 ; 0x100
80042f0: 6313 str r3, [r2, #48] ; 0x30
80042f2: 4b24 ldr r3, [pc, #144] ; (8004384 <HAL_SPI_MspInit+0xd8>)
80042f4: 6b1b ldr r3, [r3, #48] ; 0x30
80042f6: f403 7380 and.w r3, r3, #256 ; 0x100
80042fa: 60fb str r3, [r7, #12]
80042fc: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
80042fe: 4b21 ldr r3, [pc, #132] ; (8004384 <HAL_SPI_MspInit+0xd8>)
8004300: 6b1b ldr r3, [r3, #48] ; 0x30
8004302: 4a20 ldr r2, [pc, #128] ; (8004384 <HAL_SPI_MspInit+0xd8>)
8004304: f043 0302 orr.w r3, r3, #2
8004308: 6313 str r3, [r2, #48] ; 0x30
800430a: 4b1e ldr r3, [pc, #120] ; (8004384 <HAL_SPI_MspInit+0xd8>)
800430c: 6b1b ldr r3, [r3, #48] ; 0x30
800430e: f003 0302 and.w r3, r3, #2
8004312: 60bb str r3, [r7, #8]
8004314: 68bb ldr r3, [r7, #8]
PI1 ------> SPI2_SCK
PI0 ------> SPI2_NSS
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
8004316: 2302 movs r3, #2
8004318: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800431a: 2302 movs r3, #2
800431c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800431e: 2300 movs r3, #0
8004320: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004322: 2300 movs r3, #0
8004324: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004326: 2305 movs r3, #5
8004328: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
800432a: f107 0314 add.w r3, r7, #20
800432e: 4619 mov r1, r3
8004330: 4815 ldr r0, [pc, #84] ; (8004388 <HAL_SPI_MspInit+0xdc>)
8004332: f002 ffa1 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0;
8004336: 2301 movs r3, #1
8004338: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800433a: 2302 movs r3, #2
800433c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800433e: 2300 movs r3, #0
8004340: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004342: 2303 movs r3, #3
8004344: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004346: 2305 movs r3, #5
8004348: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
800434a: f107 0314 add.w r3, r7, #20
800434e: 4619 mov r1, r3
8004350: 480d ldr r0, [pc, #52] ; (8004388 <HAL_SPI_MspInit+0xdc>)
8004352: f002 ff91 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
8004356: f44f 4340 mov.w r3, #49152 ; 0xc000
800435a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800435c: 2302 movs r3, #2
800435e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004360: 2300 movs r3, #0
8004362: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004364: 2303 movs r3, #3
8004366: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004368: 2305 movs r3, #5
800436a: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800436c: f107 0314 add.w r3, r7, #20
8004370: 4619 mov r1, r3
8004372: 4806 ldr r0, [pc, #24] ; (800438c <HAL_SPI_MspInit+0xe0>)
8004374: f002 ff80 bl 8007278 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8004378: bf00 nop
800437a: 3728 adds r7, #40 ; 0x28
800437c: 46bd mov sp, r7
800437e: bd80 pop {r7, pc}
8004380: 40003800 .word 0x40003800
8004384: 40023800 .word 0x40023800
8004388: 40022000 .word 0x40022000
800438c: 40020400 .word 0x40020400
08004390 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8004390: b480 push {r7}
8004392: b089 sub sp, #36 ; 0x24
8004394: af00 add r7, sp, #0
8004396: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8004398: 687b ldr r3, [r7, #4]
800439a: 681b ldr r3, [r3, #0]
800439c: 4a2e ldr r2, [pc, #184] ; (8004458 <HAL_TIM_Base_MspInit+0xc8>)
800439e: 4293 cmp r3, r2
80043a0: d10c bne.n 80043bc <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
80043a2: 4b2e ldr r3, [pc, #184] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043a4: 6c5b ldr r3, [r3, #68] ; 0x44
80043a6: 4a2d ldr r2, [pc, #180] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043a8: f043 0301 orr.w r3, r3, #1
80043ac: 6453 str r3, [r2, #68] ; 0x44
80043ae: 4b2b ldr r3, [pc, #172] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043b0: 6c5b ldr r3, [r3, #68] ; 0x44
80043b2: f003 0301 and.w r3, r3, #1
80043b6: 61fb str r3, [r7, #28]
80043b8: 69fb ldr r3, [r7, #28]
/* USER CODE BEGIN TIM8_MspInit 1 */
/* USER CODE END TIM8_MspInit 1 */
}
}
80043ba: e046 b.n 800444a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM2)
80043bc: 687b ldr r3, [r7, #4]
80043be: 681b ldr r3, [r3, #0]
80043c0: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80043c4: d10c bne.n 80043e0 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
80043c6: 4b25 ldr r3, [pc, #148] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043c8: 6c1b ldr r3, [r3, #64] ; 0x40
80043ca: 4a24 ldr r2, [pc, #144] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043cc: f043 0301 orr.w r3, r3, #1
80043d0: 6413 str r3, [r2, #64] ; 0x40
80043d2: 4b22 ldr r3, [pc, #136] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043d4: 6c1b ldr r3, [r3, #64] ; 0x40
80043d6: f003 0301 and.w r3, r3, #1
80043da: 61bb str r3, [r7, #24]
80043dc: 69bb ldr r3, [r7, #24]
}
80043de: e034 b.n 800444a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM3)
80043e0: 687b ldr r3, [r7, #4]
80043e2: 681b ldr r3, [r3, #0]
80043e4: 4a1e ldr r2, [pc, #120] ; (8004460 <HAL_TIM_Base_MspInit+0xd0>)
80043e6: 4293 cmp r3, r2
80043e8: d10c bne.n 8004404 <HAL_TIM_Base_MspInit+0x74>
__HAL_RCC_TIM3_CLK_ENABLE();
80043ea: 4b1c ldr r3, [pc, #112] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043ec: 6c1b ldr r3, [r3, #64] ; 0x40
80043ee: 4a1b ldr r2, [pc, #108] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043f0: f043 0302 orr.w r3, r3, #2
80043f4: 6413 str r3, [r2, #64] ; 0x40
80043f6: 4b19 ldr r3, [pc, #100] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
80043f8: 6c1b ldr r3, [r3, #64] ; 0x40
80043fa: f003 0302 and.w r3, r3, #2
80043fe: 617b str r3, [r7, #20]
8004400: 697b ldr r3, [r7, #20]
}
8004402: e022 b.n 800444a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM5)
8004404: 687b ldr r3, [r7, #4]
8004406: 681b ldr r3, [r3, #0]
8004408: 4a16 ldr r2, [pc, #88] ; (8004464 <HAL_TIM_Base_MspInit+0xd4>)
800440a: 4293 cmp r3, r2
800440c: d10c bne.n 8004428 <HAL_TIM_Base_MspInit+0x98>
__HAL_RCC_TIM5_CLK_ENABLE();
800440e: 4b13 ldr r3, [pc, #76] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
8004410: 6c1b ldr r3, [r3, #64] ; 0x40
8004412: 4a12 ldr r2, [pc, #72] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
8004414: f043 0308 orr.w r3, r3, #8
8004418: 6413 str r3, [r2, #64] ; 0x40
800441a: 4b10 ldr r3, [pc, #64] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
800441c: 6c1b ldr r3, [r3, #64] ; 0x40
800441e: f003 0308 and.w r3, r3, #8
8004422: 613b str r3, [r7, #16]
8004424: 693b ldr r3, [r7, #16]
}
8004426: e010 b.n 800444a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM8)
8004428: 687b ldr r3, [r7, #4]
800442a: 681b ldr r3, [r3, #0]
800442c: 4a0e ldr r2, [pc, #56] ; (8004468 <HAL_TIM_Base_MspInit+0xd8>)
800442e: 4293 cmp r3, r2
8004430: d10b bne.n 800444a <HAL_TIM_Base_MspInit+0xba>
__HAL_RCC_TIM8_CLK_ENABLE();
8004432: 4b0a ldr r3, [pc, #40] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
8004434: 6c5b ldr r3, [r3, #68] ; 0x44
8004436: 4a09 ldr r2, [pc, #36] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
8004438: f043 0302 orr.w r3, r3, #2
800443c: 6453 str r3, [r2, #68] ; 0x44
800443e: 4b07 ldr r3, [pc, #28] ; (800445c <HAL_TIM_Base_MspInit+0xcc>)
8004440: 6c5b ldr r3, [r3, #68] ; 0x44
8004442: f003 0302 and.w r3, r3, #2
8004446: 60fb str r3, [r7, #12]
8004448: 68fb ldr r3, [r7, #12]
}
800444a: bf00 nop
800444c: 3724 adds r7, #36 ; 0x24
800444e: 46bd mov sp, r7
8004450: f85d 7b04 ldr.w r7, [sp], #4
8004454: 4770 bx lr
8004456: bf00 nop
8004458: 40010000 .word 0x40010000
800445c: 40023800 .word 0x40023800
8004460: 40000400 .word 0x40000400
8004464: 40000c00 .word 0x40000c00
8004468: 40010400 .word 0x40010400
0800446c <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
800446c: b580 push {r7, lr}
800446e: b08a sub sp, #40 ; 0x28
8004470: af00 add r7, sp, #0
8004472: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004474: f107 0314 add.w r3, r7, #20
8004478: 2200 movs r2, #0
800447a: 601a str r2, [r3, #0]
800447c: 605a str r2, [r3, #4]
800447e: 609a str r2, [r3, #8]
8004480: 60da str r2, [r3, #12]
8004482: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
8004484: 687b ldr r3, [r7, #4]
8004486: 681b ldr r3, [r3, #0]
8004488: 4a22 ldr r2, [pc, #136] ; (8004514 <HAL_TIM_MspPostInit+0xa8>)
800448a: 4293 cmp r3, r2
800448c: d11c bne.n 80044c8 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
800448e: 4b22 ldr r3, [pc, #136] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
8004490: 6b1b ldr r3, [r3, #48] ; 0x30
8004492: 4a21 ldr r2, [pc, #132] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
8004494: f043 0302 orr.w r3, r3, #2
8004498: 6313 str r3, [r2, #48] ; 0x30
800449a: 4b1f ldr r3, [pc, #124] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
800449c: 6b1b ldr r3, [r3, #48] ; 0x30
800449e: f003 0302 and.w r3, r3, #2
80044a2: 613b str r3, [r7, #16]
80044a4: 693b ldr r3, [r7, #16]
/**TIM3 GPIO Configuration
PB4 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
80044a6: 2310 movs r3, #16
80044a8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80044aa: 2302 movs r3, #2
80044ac: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80044ae: 2300 movs r3, #0
80044b0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80044b2: 2300 movs r3, #0
80044b4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
80044b6: 2302 movs r3, #2
80044b8: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80044ba: f107 0314 add.w r3, r7, #20
80044be: 4619 mov r1, r3
80044c0: 4816 ldr r0, [pc, #88] ; (800451c <HAL_TIM_MspPostInit+0xb0>)
80044c2: f002 fed9 bl 8007278 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM8_MspPostInit 1 */
/* USER CODE END TIM8_MspPostInit 1 */
}
}
80044c6: e020 b.n 800450a <HAL_TIM_MspPostInit+0x9e>
else if(htim->Instance==TIM8)
80044c8: 687b ldr r3, [r7, #4]
80044ca: 681b ldr r3, [r3, #0]
80044cc: 4a14 ldr r2, [pc, #80] ; (8004520 <HAL_TIM_MspPostInit+0xb4>)
80044ce: 4293 cmp r3, r2
80044d0: d11b bne.n 800450a <HAL_TIM_MspPostInit+0x9e>
__HAL_RCC_GPIOI_CLK_ENABLE();
80044d2: 4b11 ldr r3, [pc, #68] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
80044d4: 6b1b ldr r3, [r3, #48] ; 0x30
80044d6: 4a10 ldr r2, [pc, #64] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
80044d8: f443 7380 orr.w r3, r3, #256 ; 0x100
80044dc: 6313 str r3, [r2, #48] ; 0x30
80044de: 4b0e ldr r3, [pc, #56] ; (8004518 <HAL_TIM_MspPostInit+0xac>)
80044e0: 6b1b ldr r3, [r3, #48] ; 0x30
80044e2: f403 7380 and.w r3, r3, #256 ; 0x100
80044e6: 60fb str r3, [r7, #12]
80044e8: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_2;
80044ea: 2304 movs r3, #4
80044ec: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80044ee: 2302 movs r3, #2
80044f0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80044f2: 2300 movs r3, #0
80044f4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80044f6: 2300 movs r3, #0
80044f8: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
80044fa: 2303 movs r3, #3
80044fc: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
80044fe: f107 0314 add.w r3, r7, #20
8004502: 4619 mov r1, r3
8004504: 4807 ldr r0, [pc, #28] ; (8004524 <HAL_TIM_MspPostInit+0xb8>)
8004506: f002 feb7 bl 8007278 <HAL_GPIO_Init>
}
800450a: bf00 nop
800450c: 3728 adds r7, #40 ; 0x28
800450e: 46bd mov sp, r7
8004510: bd80 pop {r7, pc}
8004512: bf00 nop
8004514: 40000400 .word 0x40000400
8004518: 40023800 .word 0x40023800
800451c: 40020400 .word 0x40020400
8004520: 40010400 .word 0x40010400
8004524: 40022000 .word 0x40022000
08004528 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
8004528: b580 push {r7, lr}
800452a: b086 sub sp, #24
800452c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
800452e: 1d3b adds r3, r7, #4
8004530: 2200 movs r2, #0
8004532: 601a str r2, [r3, #0]
8004534: 605a str r2, [r3, #4]
8004536: 609a str r2, [r3, #8]
8004538: 60da str r2, [r3, #12]
800453a: 611a str r2, [r3, #16]
if (FMC_Initialized) {
800453c: 4b3a ldr r3, [pc, #232] ; (8004628 <HAL_FMC_MspInit+0x100>)
800453e: 681b ldr r3, [r3, #0]
8004540: 2b00 cmp r3, #0
8004542: d16d bne.n 8004620 <HAL_FMC_MspInit+0xf8>
return;
}
FMC_Initialized = 1;
8004544: 4b38 ldr r3, [pc, #224] ; (8004628 <HAL_FMC_MspInit+0x100>)
8004546: 2201 movs r2, #1
8004548: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
800454a: 4b38 ldr r3, [pc, #224] ; (800462c <HAL_FMC_MspInit+0x104>)
800454c: 6b9b ldr r3, [r3, #56] ; 0x38
800454e: 4a37 ldr r2, [pc, #220] ; (800462c <HAL_FMC_MspInit+0x104>)
8004550: f043 0301 orr.w r3, r3, #1
8004554: 6393 str r3, [r2, #56] ; 0x38
8004556: 4b35 ldr r3, [pc, #212] ; (800462c <HAL_FMC_MspInit+0x104>)
8004558: 6b9b ldr r3, [r3, #56] ; 0x38
800455a: f003 0301 and.w r3, r3, #1
800455e: 603b str r3, [r7, #0]
8004560: 683b ldr r3, [r7, #0]
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
8004562: f64f 7383 movw r3, #65411 ; 0xff83
8004566: 607b str r3, [r7, #4]
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004568: 2302 movs r3, #2
800456a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800456c: 2300 movs r3, #0
800456e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004570: 2303 movs r3, #3
8004572: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004574: 230c movs r3, #12
8004576: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8004578: 1d3b adds r3, r7, #4
800457a: 4619 mov r1, r3
800457c: 482c ldr r0, [pc, #176] ; (8004630 <HAL_FMC_MspInit+0x108>)
800457e: f002 fe7b bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
8004582: f248 1333 movw r3, #33075 ; 0x8133
8004586: 607b str r3, [r7, #4]
|GPIO_PIN_5|GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004588: 2302 movs r3, #2
800458a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800458c: 2300 movs r3, #0
800458e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004590: 2303 movs r3, #3
8004592: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004594: 230c movs r3, #12
8004596: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8004598: 1d3b adds r3, r7, #4
800459a: 4619 mov r1, r3
800459c: 4825 ldr r0, [pc, #148] ; (8004634 <HAL_FMC_MspInit+0x10c>)
800459e: f002 fe6b bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
80045a2: f24c 7303 movw r3, #50947 ; 0xc703
80045a6: 607b str r3, [r7, #4]
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045a8: 2302 movs r3, #2
80045aa: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045ac: 2300 movs r3, #0
80045ae: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045b0: 2303 movs r3, #3
80045b2: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045b4: 230c movs r3, #12
80045b6: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80045b8: 1d3b adds r3, r7, #4
80045ba: 4619 mov r1, r3
80045bc: 481e ldr r0, [pc, #120] ; (8004638 <HAL_FMC_MspInit+0x110>)
80045be: f002 fe5b bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
80045c2: f64f 033f movw r3, #63551 ; 0xf83f
80045c6: 607b str r3, [r7, #4]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045c8: 2302 movs r3, #2
80045ca: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045cc: 2300 movs r3, #0
80045ce: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045d0: 2303 movs r3, #3
80045d2: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045d4: 230c movs r3, #12
80045d6: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80045d8: 1d3b adds r3, r7, #4
80045da: 4619 mov r1, r3
80045dc: 4817 ldr r0, [pc, #92] ; (800463c <HAL_FMC_MspInit+0x114>)
80045de: f002 fe4b bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
80045e2: 2328 movs r3, #40 ; 0x28
80045e4: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045e6: 2302 movs r3, #2
80045e8: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045ea: 2300 movs r3, #0
80045ec: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045ee: 2303 movs r3, #3
80045f0: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045f2: 230c movs r3, #12
80045f4: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
80045f6: 1d3b adds r3, r7, #4
80045f8: 4619 mov r1, r3
80045fa: 4811 ldr r0, [pc, #68] ; (8004640 <HAL_FMC_MspInit+0x118>)
80045fc: f002 fe3c bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
8004600: 2308 movs r3, #8
8004602: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004604: 2302 movs r3, #2
8004606: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004608: 2300 movs r3, #0
800460a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800460c: 2303 movs r3, #3
800460e: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004610: 230c movs r3, #12
8004612: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8004614: 1d3b adds r3, r7, #4
8004616: 4619 mov r1, r3
8004618: 480a ldr r0, [pc, #40] ; (8004644 <HAL_FMC_MspInit+0x11c>)
800461a: f002 fe2d bl 8007278 <HAL_GPIO_Init>
800461e: e000 b.n 8004622 <HAL_FMC_MspInit+0xfa>
return;
8004620: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
8004622: 3718 adds r7, #24
8004624: 46bd mov sp, r7
8004626: bd80 pop {r7, pc}
8004628: 2000057c .word 0x2000057c
800462c: 40023800 .word 0x40023800
8004630: 40021000 .word 0x40021000
8004634: 40021800 .word 0x40021800
8004638: 40020c00 .word 0x40020c00
800463c: 40021400 .word 0x40021400
8004640: 40021c00 .word 0x40021c00
8004644: 40020800 .word 0x40020800
08004648 <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
8004648: b580 push {r7, lr}
800464a: b082 sub sp, #8
800464c: af00 add r7, sp, #0
800464e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
8004650: f7ff ff6a bl 8004528 <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
8004654: bf00 nop
8004656: 3708 adds r7, #8
8004658: 46bd mov sp, r7
800465a: bd80 pop {r7, pc}
0800465c <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800465c: b580 push {r7, lr}
800465e: b08c sub sp, #48 ; 0x30
8004660: af00 add r7, sp, #0
8004662: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
8004664: 2300 movs r3, #0
8004666: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
8004668: 2300 movs r3, #0
800466a: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
800466c: 2200 movs r2, #0
800466e: 6879 ldr r1, [r7, #4]
8004670: 2036 movs r0, #54 ; 0x36
8004672: f000 fe51 bl 8005318 <HAL_NVIC_SetPriority>
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8004676: 2036 movs r0, #54 ; 0x36
8004678: f000 fe6a bl 8005350 <HAL_NVIC_EnableIRQ>
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
800467c: 4b1f ldr r3, [pc, #124] ; (80046fc <HAL_InitTick+0xa0>)
800467e: 6c1b ldr r3, [r3, #64] ; 0x40
8004680: 4a1e ldr r2, [pc, #120] ; (80046fc <HAL_InitTick+0xa0>)
8004682: f043 0310 orr.w r3, r3, #16
8004686: 6413 str r3, [r2, #64] ; 0x40
8004688: 4b1c ldr r3, [pc, #112] ; (80046fc <HAL_InitTick+0xa0>)
800468a: 6c1b ldr r3, [r3, #64] ; 0x40
800468c: f003 0310 and.w r3, r3, #16
8004690: 60fb str r3, [r7, #12]
8004692: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8004694: f107 0210 add.w r2, r7, #16
8004698: f107 0314 add.w r3, r7, #20
800469c: 4611 mov r1, r2
800469e: 4618 mov r0, r3
80046a0: f004 fd46 bl 8009130 <HAL_RCC_GetClockConfig>
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
80046a4: f004 fd30 bl 8009108 <HAL_RCC_GetPCLK1Freq>
80046a8: 4603 mov r3, r0
80046aa: 005b lsls r3, r3, #1
80046ac: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
80046ae: 6afb ldr r3, [r7, #44] ; 0x2c
80046b0: 4a13 ldr r2, [pc, #76] ; (8004700 <HAL_InitTick+0xa4>)
80046b2: fba2 2303 umull r2, r3, r2, r3
80046b6: 0c9b lsrs r3, r3, #18
80046b8: 3b01 subs r3, #1
80046ba: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
80046bc: 4b11 ldr r3, [pc, #68] ; (8004704 <HAL_InitTick+0xa8>)
80046be: 4a12 ldr r2, [pc, #72] ; (8004708 <HAL_InitTick+0xac>)
80046c0: 601a str r2, [r3, #0]
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
80046c2: 4b10 ldr r3, [pc, #64] ; (8004704 <HAL_InitTick+0xa8>)
80046c4: f240 32e7 movw r2, #999 ; 0x3e7
80046c8: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
80046ca: 4a0e ldr r2, [pc, #56] ; (8004704 <HAL_InitTick+0xa8>)
80046cc: 6abb ldr r3, [r7, #40] ; 0x28
80046ce: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
80046d0: 4b0c ldr r3, [pc, #48] ; (8004704 <HAL_InitTick+0xa8>)
80046d2: 2200 movs r2, #0
80046d4: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
80046d6: 4b0b ldr r3, [pc, #44] ; (8004704 <HAL_InitTick+0xa8>)
80046d8: 2200 movs r2, #0
80046da: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
80046dc: 4809 ldr r0, [pc, #36] ; (8004704 <HAL_InitTick+0xa8>)
80046de: f005 fa82 bl 8009be6 <HAL_TIM_Base_Init>
80046e2: 4603 mov r3, r0
80046e4: 2b00 cmp r3, #0
80046e6: d104 bne.n 80046f2 <HAL_InitTick+0x96>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
80046e8: 4806 ldr r0, [pc, #24] ; (8004704 <HAL_InitTick+0xa8>)
80046ea: f005 faa7 bl 8009c3c <HAL_TIM_Base_Start_IT>
80046ee: 4603 mov r3, r0
80046f0: e000 b.n 80046f4 <HAL_InitTick+0x98>
}
/* Return function status */
return HAL_ERROR;
80046f2: 2301 movs r3, #1
}
80046f4: 4618 mov r0, r3
80046f6: 3730 adds r7, #48 ; 0x30
80046f8: 46bd mov sp, r7
80046fa: bd80 pop {r7, pc}
80046fc: 40023800 .word 0x40023800
8004700: 431bde83 .word 0x431bde83
8004704: 20008d10 .word 0x20008d10
8004708: 40001000 .word 0x40001000
0800470c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800470c: b480 push {r7}
800470e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8004710: e7fe b.n 8004710 <NMI_Handler+0x4>
08004712 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8004712: b480 push {r7}
8004714: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8004716: e7fe b.n 8004716 <HardFault_Handler+0x4>
08004718 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8004718: b480 push {r7}
800471a: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
800471c: e7fe b.n 800471c <MemManage_Handler+0x4>
0800471e <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800471e: b480 push {r7}
8004720: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8004722: e7fe b.n 8004722 <BusFault_Handler+0x4>
08004724 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8004724: b480 push {r7}
8004726: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8004728: e7fe b.n 8004728 <UsageFault_Handler+0x4>
0800472a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800472a: b480 push {r7}
800472c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800472e: bf00 nop
8004730: 46bd mov sp, r7
8004732: f85d 7b04 ldr.w r7, [sp], #4
8004736: 4770 bx lr
08004738 <EXTI9_5_IRQHandler>:
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void EXTI9_5_IRQHandler(void)
{
8004738: b580 push {r7, lr}
800473a: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
/* USER CODE END EXTI9_5_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
800473c: f44f 7080 mov.w r0, #256 ; 0x100
8004740: f002 ff78 bl 8007634 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
/* USER CODE END EXTI9_5_IRQn 1 */
}
8004744: bf00 nop
8004746: bd80 pop {r7, pc}
08004748 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
8004748: b580 push {r7, lr}
800474a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_DAC_IRQHandler(&hdac);
800474c: 4803 ldr r0, [pc, #12] ; (800475c <TIM6_DAC_IRQHandler+0x14>)
800474e: f000 ff19 bl 8005584 <HAL_DAC_IRQHandler>
HAL_TIM_IRQHandler(&htim6);
8004752: 4803 ldr r0, [pc, #12] ; (8004760 <TIM6_DAC_IRQHandler+0x18>)
8004754: f005 fad1 bl 8009cfa <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
8004758: bf00 nop
800475a: bd80 pop {r7, pc}
800475c: 20008b0c .word 0x20008b0c
8004760: 20008d10 .word 0x20008d10
08004764 <ETH_IRQHandler>:
/**
* @brief This function handles Ethernet global interrupt.
*/
void ETH_IRQHandler(void)
{
8004764: b580 push {r7, lr}
8004766: af00 add r7, sp, #0
/* USER CODE BEGIN ETH_IRQn 0 */
/* USER CODE END ETH_IRQn 0 */
HAL_ETH_IRQHandler(&heth);
8004768: 4802 ldr r0, [pc, #8] ; (8004774 <ETH_IRQHandler+0x10>)
800476a: f001 ffe3 bl 8006734 <HAL_ETH_IRQHandler>
/* USER CODE BEGIN ETH_IRQn 1 */
/* USER CODE END ETH_IRQn 1 */
}
800476e: bf00 nop
8004770: bd80 pop {r7, pc}
8004772: bf00 nop
8004774: 2000a670 .word 0x2000a670
08004778 <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
8004778: b580 push {r7, lr}
800477a: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
800477c: 4802 ldr r0, [pc, #8] ; (8004788 <LTDC_IRQHandler+0x10>)
800477e: f003 fd6d bl 800825c <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
8004782: bf00 nop
8004784: bd80 pop {r7, pc}
8004786: bf00 nop
8004788: 200089cc .word 0x200089cc
0800478c <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
800478c: b580 push {r7, lr}
800478e: b086 sub sp, #24
8004790: af00 add r7, sp, #0
8004792: 60f8 str r0, [r7, #12]
8004794: 60b9 str r1, [r7, #8]
8004796: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
8004798: 2300 movs r3, #0
800479a: 617b str r3, [r7, #20]
800479c: e00a b.n 80047b4 <_read+0x28>
{
*ptr++ = __io_getchar();
800479e: f3af 8000 nop.w
80047a2: 4601 mov r1, r0
80047a4: 68bb ldr r3, [r7, #8]
80047a6: 1c5a adds r2, r3, #1
80047a8: 60ba str r2, [r7, #8]
80047aa: b2ca uxtb r2, r1
80047ac: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047ae: 697b ldr r3, [r7, #20]
80047b0: 3301 adds r3, #1
80047b2: 617b str r3, [r7, #20]
80047b4: 697a ldr r2, [r7, #20]
80047b6: 687b ldr r3, [r7, #4]
80047b8: 429a cmp r2, r3
80047ba: dbf0 blt.n 800479e <_read+0x12>
}
return len;
80047bc: 687b ldr r3, [r7, #4]
}
80047be: 4618 mov r0, r3
80047c0: 3718 adds r7, #24
80047c2: 46bd mov sp, r7
80047c4: bd80 pop {r7, pc}
080047c6 <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
80047c6: b580 push {r7, lr}
80047c8: b086 sub sp, #24
80047ca: af00 add r7, sp, #0
80047cc: 60f8 str r0, [r7, #12]
80047ce: 60b9 str r1, [r7, #8]
80047d0: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047d2: 2300 movs r3, #0
80047d4: 617b str r3, [r7, #20]
80047d6: e009 b.n 80047ec <_write+0x26>
{
__io_putchar(*ptr++);
80047d8: 68bb ldr r3, [r7, #8]
80047da: 1c5a adds r2, r3, #1
80047dc: 60ba str r2, [r7, #8]
80047de: 781b ldrb r3, [r3, #0]
80047e0: 4618 mov r0, r3
80047e2: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047e6: 697b ldr r3, [r7, #20]
80047e8: 3301 adds r3, #1
80047ea: 617b str r3, [r7, #20]
80047ec: 697a ldr r2, [r7, #20]
80047ee: 687b ldr r3, [r7, #4]
80047f0: 429a cmp r2, r3
80047f2: dbf1 blt.n 80047d8 <_write+0x12>
}
return len;
80047f4: 687b ldr r3, [r7, #4]
}
80047f6: 4618 mov r0, r3
80047f8: 3718 adds r7, #24
80047fa: 46bd mov sp, r7
80047fc: bd80 pop {r7, pc}
080047fe <_close>:
int _close(int file)
{
80047fe: b480 push {r7}
8004800: b083 sub sp, #12
8004802: af00 add r7, sp, #0
8004804: 6078 str r0, [r7, #4]
return -1;
8004806: f04f 33ff mov.w r3, #4294967295
}
800480a: 4618 mov r0, r3
800480c: 370c adds r7, #12
800480e: 46bd mov sp, r7
8004810: f85d 7b04 ldr.w r7, [sp], #4
8004814: 4770 bx lr
08004816 <_fstat>:
int _fstat(int file, struct stat *st)
{
8004816: b480 push {r7}
8004818: b083 sub sp, #12
800481a: af00 add r7, sp, #0
800481c: 6078 str r0, [r7, #4]
800481e: 6039 str r1, [r7, #0]
st->st_mode = S_IFCHR;
8004820: 683b ldr r3, [r7, #0]
8004822: f44f 5200 mov.w r2, #8192 ; 0x2000
8004826: 605a str r2, [r3, #4]
return 0;
8004828: 2300 movs r3, #0
}
800482a: 4618 mov r0, r3
800482c: 370c adds r7, #12
800482e: 46bd mov sp, r7
8004830: f85d 7b04 ldr.w r7, [sp], #4
8004834: 4770 bx lr
08004836 <_isatty>:
int _isatty(int file)
{
8004836: b480 push {r7}
8004838: b083 sub sp, #12
800483a: af00 add r7, sp, #0
800483c: 6078 str r0, [r7, #4]
return 1;
800483e: 2301 movs r3, #1
}
8004840: 4618 mov r0, r3
8004842: 370c adds r7, #12
8004844: 46bd mov sp, r7
8004846: f85d 7b04 ldr.w r7, [sp], #4
800484a: 4770 bx lr
0800484c <_lseek>:
int _lseek(int file, int ptr, int dir)
{
800484c: b480 push {r7}
800484e: b085 sub sp, #20
8004850: af00 add r7, sp, #0
8004852: 60f8 str r0, [r7, #12]
8004854: 60b9 str r1, [r7, #8]
8004856: 607a str r2, [r7, #4]
return 0;
8004858: 2300 movs r3, #0
}
800485a: 4618 mov r0, r3
800485c: 3714 adds r7, #20
800485e: 46bd mov sp, r7
8004860: f85d 7b04 ldr.w r7, [sp], #4
8004864: 4770 bx lr
...
08004868 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8004868: b480 push {r7}
800486a: b087 sub sp, #28
800486c: af00 add r7, sp, #0
800486e: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8004870: 4a14 ldr r2, [pc, #80] ; (80048c4 <_sbrk+0x5c>)
8004872: 4b15 ldr r3, [pc, #84] ; (80048c8 <_sbrk+0x60>)
8004874: 1ad3 subs r3, r2, r3
8004876: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8004878: 697b ldr r3, [r7, #20]
800487a: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
800487c: 4b13 ldr r3, [pc, #76] ; (80048cc <_sbrk+0x64>)
800487e: 681b ldr r3, [r3, #0]
8004880: 2b00 cmp r3, #0
8004882: d102 bne.n 800488a <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8004884: 4b11 ldr r3, [pc, #68] ; (80048cc <_sbrk+0x64>)
8004886: 4a12 ldr r2, [pc, #72] ; (80048d0 <_sbrk+0x68>)
8004888: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
800488a: 4b10 ldr r3, [pc, #64] ; (80048cc <_sbrk+0x64>)
800488c: 681a ldr r2, [r3, #0]
800488e: 687b ldr r3, [r7, #4]
8004890: 4413 add r3, r2
8004892: 693a ldr r2, [r7, #16]
8004894: 429a cmp r2, r3
8004896: d205 bcs.n 80048a4 <_sbrk+0x3c>
{
errno = ENOMEM;
8004898: 4b0e ldr r3, [pc, #56] ; (80048d4 <_sbrk+0x6c>)
800489a: 220c movs r2, #12
800489c: 601a str r2, [r3, #0]
return (void *)-1;
800489e: f04f 33ff mov.w r3, #4294967295
80048a2: e009 b.n 80048b8 <_sbrk+0x50>
}
prev_heap_end = __sbrk_heap_end;
80048a4: 4b09 ldr r3, [pc, #36] ; (80048cc <_sbrk+0x64>)
80048a6: 681b ldr r3, [r3, #0]
80048a8: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80048aa: 4b08 ldr r3, [pc, #32] ; (80048cc <_sbrk+0x64>)
80048ac: 681a ldr r2, [r3, #0]
80048ae: 687b ldr r3, [r7, #4]
80048b0: 4413 add r3, r2
80048b2: 4a06 ldr r2, [pc, #24] ; (80048cc <_sbrk+0x64>)
80048b4: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80048b6: 68fb ldr r3, [r7, #12]
}
80048b8: 4618 mov r0, r3
80048ba: 371c adds r7, #28
80048bc: 46bd mov sp, r7
80048be: f85d 7b04 ldr.w r7, [sp], #4
80048c2: 4770 bx lr
80048c4: 20050000 .word 0x20050000
80048c8: 00000400 .word 0x00000400
80048cc: 20000580 .word 0x20000580
80048d0: 2000f610 .word 0x2000f610
80048d4: 2000f604 .word 0x2000f604
080048d8 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
80048d8: b480 push {r7}
80048da: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80048dc: 4b08 ldr r3, [pc, #32] ; (8004900 <SystemInit+0x28>)
80048de: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80048e2: 4a07 ldr r2, [pc, #28] ; (8004900 <SystemInit+0x28>)
80048e4: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
80048e8: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
80048ec: 4b04 ldr r3, [pc, #16] ; (8004900 <SystemInit+0x28>)
80048ee: f04f 6200 mov.w r2, #134217728 ; 0x8000000
80048f2: 609a str r2, [r3, #8]
#endif
}
80048f4: bf00 nop
80048f6: 46bd mov sp, r7
80048f8: f85d 7b04 ldr.w r7, [sp], #4
80048fc: 4770 bx lr
80048fe: bf00 nop
8004900: e000ed00 .word 0xe000ed00
08004904 <Reset_Handler>:
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler: ldr sp, =_estack /* set stack pointer */
8004904: f8df d034 ldr.w sp, [pc, #52] ; 800493c <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8004908: 2100 movs r1, #0
b LoopCopyDataInit
800490a: e003 b.n 8004914 <LoopCopyDataInit>
0800490c <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
800490c: 4b0c ldr r3, [pc, #48] ; (8004940 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
800490e: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8004910: 5043 str r3, [r0, r1]
adds r1, r1, #4
8004912: 3104 adds r1, #4
08004914 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8004914: 480b ldr r0, [pc, #44] ; (8004944 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
8004916: 4b0c ldr r3, [pc, #48] ; (8004948 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8004918: 1842 adds r2, r0, r1
cmp r2, r3
800491a: 429a cmp r2, r3
bcc CopyDataInit
800491c: d3f6 bcc.n 800490c <CopyDataInit>
ldr r2, =_sbss
800491e: 4a0b ldr r2, [pc, #44] ; (800494c <LoopFillZerobss+0x24>)
b LoopFillZerobss
8004920: e002 b.n 8004928 <LoopFillZerobss>
08004922 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
8004922: 2300 movs r3, #0
str r3, [r2], #4
8004924: f842 3b04 str.w r3, [r2], #4
08004928 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8004928: 4b09 ldr r3, [pc, #36] ; (8004950 <LoopFillZerobss+0x28>)
cmp r2, r3
800492a: 429a cmp r2, r3
bcc FillZerobss
800492c: d3f9 bcc.n 8004922 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
800492e: f7ff ffd3 bl 80048d8 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8004932: f016 fb29 bl 801af88 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8004936: f7fc f911 bl 8000b5c <main>
bx lr
800493a: 4770 bx lr
Reset_Handler: ldr sp, =_estack /* set stack pointer */
800493c: 20050000 .word 0x20050000
ldr r3, =_sidata
8004940: 08020f30 .word 0x08020f30
ldr r0, =_sdata
8004944: 20000000 .word 0x20000000
ldr r3, =_edata
8004948: 200000e8 .word 0x200000e8
ldr r2, =_sbss
800494c: 200000e8 .word 0x200000e8
ldr r3, = _ebss
8004950: 2000f60c .word 0x2000f60c
08004954 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8004954: e7fe b.n 8004954 <ADC_IRQHandler>
08004956 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8004956: b580 push {r7, lr}
8004958: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800495a: 2003 movs r0, #3
800495c: f000 fcd1 bl 8005302 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8004960: 2000 movs r0, #0
8004962: f7ff fe7b bl 800465c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8004966: f7ff fa9b bl 8003ea0 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800496a: 2300 movs r3, #0
}
800496c: 4618 mov r0, r3
800496e: bd80 pop {r7, pc}
08004970 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8004970: b480 push {r7}
8004972: af00 add r7, sp, #0
uwTick += uwTickFreq;
8004974: 4b06 ldr r3, [pc, #24] ; (8004990 <HAL_IncTick+0x20>)
8004976: 781b ldrb r3, [r3, #0]
8004978: 461a mov r2, r3
800497a: 4b06 ldr r3, [pc, #24] ; (8004994 <HAL_IncTick+0x24>)
800497c: 681b ldr r3, [r3, #0]
800497e: 4413 add r3, r2
8004980: 4a04 ldr r2, [pc, #16] ; (8004994 <HAL_IncTick+0x24>)
8004982: 6013 str r3, [r2, #0]
}
8004984: bf00 nop
8004986: 46bd mov sp, r7
8004988: f85d 7b04 ldr.w r7, [sp], #4
800498c: 4770 bx lr
800498e: bf00 nop
8004990: 2000006c .word 0x2000006c
8004994: 20008d50 .word 0x20008d50
08004998 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8004998: b480 push {r7}
800499a: af00 add r7, sp, #0
return uwTick;
800499c: 4b03 ldr r3, [pc, #12] ; (80049ac <HAL_GetTick+0x14>)
800499e: 681b ldr r3, [r3, #0]
}
80049a0: 4618 mov r0, r3
80049a2: 46bd mov sp, r7
80049a4: f85d 7b04 ldr.w r7, [sp], #4
80049a8: 4770 bx lr
80049aa: bf00 nop
80049ac: 20008d50 .word 0x20008d50
080049b0 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80049b0: b580 push {r7, lr}
80049b2: b084 sub sp, #16
80049b4: af00 add r7, sp, #0
80049b6: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80049b8: f7ff ffee bl 8004998 <HAL_GetTick>
80049bc: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80049be: 687b ldr r3, [r7, #4]
80049c0: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80049c2: 68fb ldr r3, [r7, #12]
80049c4: f1b3 3fff cmp.w r3, #4294967295
80049c8: d005 beq.n 80049d6 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80049ca: 4b09 ldr r3, [pc, #36] ; (80049f0 <HAL_Delay+0x40>)
80049cc: 781b ldrb r3, [r3, #0]
80049ce: 461a mov r2, r3
80049d0: 68fb ldr r3, [r7, #12]
80049d2: 4413 add r3, r2
80049d4: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80049d6: bf00 nop
80049d8: f7ff ffde bl 8004998 <HAL_GetTick>
80049dc: 4602 mov r2, r0
80049de: 68bb ldr r3, [r7, #8]
80049e0: 1ad3 subs r3, r2, r3
80049e2: 68fa ldr r2, [r7, #12]
80049e4: 429a cmp r2, r3
80049e6: d8f7 bhi.n 80049d8 <HAL_Delay+0x28>
{
}
}
80049e8: bf00 nop
80049ea: 3710 adds r7, #16
80049ec: 46bd mov sp, r7
80049ee: bd80 pop {r7, pc}
80049f0: 2000006c .word 0x2000006c
080049f4 <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80049f4: b580 push {r7, lr}
80049f6: b084 sub sp, #16
80049f8: af00 add r7, sp, #0
80049fa: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80049fc: 2300 movs r3, #0
80049fe: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
8004a00: 687b ldr r3, [r7, #4]
8004a02: 2b00 cmp r3, #0
8004a04: d101 bne.n 8004a0a <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8004a06: 2301 movs r3, #1
8004a08: e031 b.n 8004a6e <HAL_ADC_Init+0x7a>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 6c1b ldr r3, [r3, #64] ; 0x40
8004a0e: 2b00 cmp r3, #0
8004a10: d109 bne.n 8004a26 <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8004a12: 6878 ldr r0, [r7, #4]
8004a14: f7ff fa6c bl 8003ef0 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8004a18: 687b ldr r3, [r7, #4]
8004a1a: 2200 movs r2, #0
8004a1c: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8004a1e: 687b ldr r3, [r7, #4]
8004a20: 2200 movs r2, #0
8004a22: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8004a26: 687b ldr r3, [r7, #4]
8004a28: 6c1b ldr r3, [r3, #64] ; 0x40
8004a2a: f003 0310 and.w r3, r3, #16
8004a2e: 2b00 cmp r3, #0
8004a30: d116 bne.n 8004a60 <HAL_ADC_Init+0x6c>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8004a32: 687b ldr r3, [r7, #4]
8004a34: 6c1a ldr r2, [r3, #64] ; 0x40
8004a36: 4b10 ldr r3, [pc, #64] ; (8004a78 <HAL_ADC_Init+0x84>)
8004a38: 4013 ands r3, r2
8004a3a: f043 0202 orr.w r2, r3, #2
8004a3e: 687b ldr r3, [r7, #4]
8004a40: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
8004a42: 6878 ldr r0, [r7, #4]
8004a44: f000 fab6 bl 8004fb4 <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8004a48: 687b ldr r3, [r7, #4]
8004a4a: 2200 movs r2, #0
8004a4c: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8004a4e: 687b ldr r3, [r7, #4]
8004a50: 6c1b ldr r3, [r3, #64] ; 0x40
8004a52: f023 0303 bic.w r3, r3, #3
8004a56: f043 0201 orr.w r2, r3, #1
8004a5a: 687b ldr r3, [r7, #4]
8004a5c: 641a str r2, [r3, #64] ; 0x40
8004a5e: e001 b.n 8004a64 <HAL_ADC_Init+0x70>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
8004a60: 2301 movs r3, #1
8004a62: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
8004a64: 687b ldr r3, [r7, #4]
8004a66: 2200 movs r2, #0
8004a68: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
8004a6c: 7bfb ldrb r3, [r7, #15]
}
8004a6e: 4618 mov r0, r3
8004a70: 3710 adds r7, #16
8004a72: 46bd mov sp, r7
8004a74: bd80 pop {r7, pc}
8004a76: bf00 nop
8004a78: ffffeefd .word 0xffffeefd
08004a7c <HAL_ADC_Start>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8004a7c: b480 push {r7}
8004a7e: b085 sub sp, #20
8004a80: af00 add r7, sp, #0
8004a82: 6078 str r0, [r7, #4]
__IO uint32_t counter = 0;
8004a84: 2300 movs r3, #0
8004a86: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
8004a88: 687b ldr r3, [r7, #4]
8004a8a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004a8e: 2b01 cmp r3, #1
8004a90: d101 bne.n 8004a96 <HAL_ADC_Start+0x1a>
8004a92: 2302 movs r3, #2
8004a94: e0a0 b.n 8004bd8 <HAL_ADC_Start+0x15c>
8004a96: 687b ldr r3, [r7, #4]
8004a98: 2201 movs r2, #1
8004a9a: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
8004a9e: 687b ldr r3, [r7, #4]
8004aa0: 681b ldr r3, [r3, #0]
8004aa2: 689b ldr r3, [r3, #8]
8004aa4: f003 0301 and.w r3, r3, #1
8004aa8: 2b01 cmp r3, #1
8004aaa: d018 beq.n 8004ade <HAL_ADC_Start+0x62>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8004aac: 687b ldr r3, [r7, #4]
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 689a ldr r2, [r3, #8]
8004ab2: 687b ldr r3, [r7, #4]
8004ab4: 681b ldr r3, [r3, #0]
8004ab6: f042 0201 orr.w r2, r2, #1
8004aba: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
8004abc: 4b49 ldr r3, [pc, #292] ; (8004be4 <HAL_ADC_Start+0x168>)
8004abe: 681b ldr r3, [r3, #0]
8004ac0: 4a49 ldr r2, [pc, #292] ; (8004be8 <HAL_ADC_Start+0x16c>)
8004ac2: fba2 2303 umull r2, r3, r2, r3
8004ac6: 0c9a lsrs r2, r3, #18
8004ac8: 4613 mov r3, r2
8004aca: 005b lsls r3, r3, #1
8004acc: 4413 add r3, r2
8004ace: 60fb str r3, [r7, #12]
while(counter != 0)
8004ad0: e002 b.n 8004ad8 <HAL_ADC_Start+0x5c>
{
counter--;
8004ad2: 68fb ldr r3, [r7, #12]
8004ad4: 3b01 subs r3, #1
8004ad6: 60fb str r3, [r7, #12]
while(counter != 0)
8004ad8: 68fb ldr r3, [r7, #12]
8004ada: 2b00 cmp r3, #0
8004adc: d1f9 bne.n 8004ad2 <HAL_ADC_Start+0x56>
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
8004ade: 687b ldr r3, [r7, #4]
8004ae0: 681b ldr r3, [r3, #0]
8004ae2: 689b ldr r3, [r3, #8]
8004ae4: f003 0301 and.w r3, r3, #1
8004ae8: 2b01 cmp r3, #1
8004aea: d174 bne.n 8004bd6 <HAL_ADC_Start+0x15a>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
8004aec: 687b ldr r3, [r7, #4]
8004aee: 6c1a ldr r2, [r3, #64] ; 0x40
8004af0: 4b3e ldr r3, [pc, #248] ; (8004bec <HAL_ADC_Start+0x170>)
8004af2: 4013 ands r3, r2
8004af4: f443 7280 orr.w r2, r3, #256 ; 0x100
8004af8: 687b ldr r3, [r7, #4]
8004afa: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8004afc: 687b ldr r3, [r7, #4]
8004afe: 681b ldr r3, [r3, #0]
8004b00: 685b ldr r3, [r3, #4]
8004b02: f403 6380 and.w r3, r3, #1024 ; 0x400
8004b06: 2b00 cmp r3, #0
8004b08: d007 beq.n 8004b1a <HAL_ADC_Start+0x9e>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8004b0a: 687b ldr r3, [r7, #4]
8004b0c: 6c1b ldr r3, [r3, #64] ; 0x40
8004b0e: f423 5340 bic.w r3, r3, #12288 ; 0x3000
8004b12: f443 5280 orr.w r2, r3, #4096 ; 0x1000
8004b16: 687b ldr r3, [r7, #4]
8004b18: 641a str r2, [r3, #64] ; 0x40
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004b1a: 687b ldr r3, [r7, #4]
8004b1c: 6c1b ldr r3, [r3, #64] ; 0x40
8004b1e: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004b22: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004b26: d106 bne.n 8004b36 <HAL_ADC_Start+0xba>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8004b28: 687b ldr r3, [r7, #4]
8004b2a: 6c5b ldr r3, [r3, #68] ; 0x44
8004b2c: f023 0206 bic.w r2, r3, #6
8004b30: 687b ldr r3, [r7, #4]
8004b32: 645a str r2, [r3, #68] ; 0x44
8004b34: e002 b.n 8004b3c <HAL_ADC_Start+0xc0>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8004b36: 687b ldr r3, [r7, #4]
8004b38: 2200 movs r2, #0
8004b3a: 645a str r2, [r3, #68] ; 0x44
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8004b3c: 687b ldr r3, [r7, #4]
8004b3e: 2200 movs r2, #0
8004b40: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
8004b44: 687b ldr r3, [r7, #4]
8004b46: 681b ldr r3, [r3, #0]
8004b48: f06f 0222 mvn.w r2, #34 ; 0x22
8004b4c: 601a str r2, [r3, #0]
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
8004b4e: 4b28 ldr r3, [pc, #160] ; (8004bf0 <HAL_ADC_Start+0x174>)
8004b50: 685b ldr r3, [r3, #4]
8004b52: f003 031f and.w r3, r3, #31
8004b56: 2b00 cmp r3, #0
8004b58: d10f bne.n 8004b7a <HAL_ADC_Start+0xfe>
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
8004b5a: 687b ldr r3, [r7, #4]
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: 689b ldr r3, [r3, #8]
8004b60: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004b64: 2b00 cmp r3, #0
8004b66: d136 bne.n 8004bd6 <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004b68: 687b ldr r3, [r7, #4]
8004b6a: 681b ldr r3, [r3, #0]
8004b6c: 689a ldr r2, [r3, #8]
8004b6e: 687b ldr r3, [r7, #4]
8004b70: 681b ldr r3, [r3, #0]
8004b72: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004b76: 609a str r2, [r3, #8]
8004b78: e02d b.n 8004bd6 <HAL_ADC_Start+0x15a>
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8004b7a: 687b ldr r3, [r7, #4]
8004b7c: 681b ldr r3, [r3, #0]
8004b7e: 4a1d ldr r2, [pc, #116] ; (8004bf4 <HAL_ADC_Start+0x178>)
8004b80: 4293 cmp r3, r2
8004b82: d10e bne.n 8004ba2 <HAL_ADC_Start+0x126>
8004b84: 687b ldr r3, [r7, #4]
8004b86: 681b ldr r3, [r3, #0]
8004b88: 689b ldr r3, [r3, #8]
8004b8a: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004b8e: 2b00 cmp r3, #0
8004b90: d107 bne.n 8004ba2 <HAL_ADC_Start+0x126>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004b92: 687b ldr r3, [r7, #4]
8004b94: 681b ldr r3, [r3, #0]
8004b96: 689a ldr r2, [r3, #8]
8004b98: 687b ldr r3, [r7, #4]
8004b9a: 681b ldr r3, [r3, #0]
8004b9c: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004ba0: 609a str r2, [r3, #8]
}
/* if dual mode is selected, ADC3 works independently. */
/* check if the mode selected is not triple */
if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
8004ba2: 4b13 ldr r3, [pc, #76] ; (8004bf0 <HAL_ADC_Start+0x174>)
8004ba4: 685b ldr r3, [r3, #4]
8004ba6: f003 0310 and.w r3, r3, #16
8004baa: 2b00 cmp r3, #0
8004bac: d113 bne.n 8004bd6 <HAL_ADC_Start+0x15a>
{
/* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8004bae: 687b ldr r3, [r7, #4]
8004bb0: 681b ldr r3, [r3, #0]
8004bb2: 4a11 ldr r2, [pc, #68] ; (8004bf8 <HAL_ADC_Start+0x17c>)
8004bb4: 4293 cmp r3, r2
8004bb6: d10e bne.n 8004bd6 <HAL_ADC_Start+0x15a>
8004bb8: 687b ldr r3, [r7, #4]
8004bba: 681b ldr r3, [r3, #0]
8004bbc: 689b ldr r3, [r3, #8]
8004bbe: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004bc2: 2b00 cmp r3, #0
8004bc4: d107 bne.n 8004bd6 <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004bc6: 687b ldr r3, [r7, #4]
8004bc8: 681b ldr r3, [r3, #0]
8004bca: 689a ldr r2, [r3, #8]
8004bcc: 687b ldr r3, [r7, #4]
8004bce: 681b ldr r3, [r3, #0]
8004bd0: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004bd4: 609a str r2, [r3, #8]
}
}
}
/* Return function status */
return HAL_OK;
8004bd6: 2300 movs r3, #0
}
8004bd8: 4618 mov r0, r3
8004bda: 3714 adds r7, #20
8004bdc: 46bd mov sp, r7
8004bde: f85d 7b04 ldr.w r7, [sp], #4
8004be2: 4770 bx lr
8004be4: 20000064 .word 0x20000064
8004be8: 431bde83 .word 0x431bde83
8004bec: fffff8fe .word 0xfffff8fe
8004bf0: 40012300 .word 0x40012300
8004bf4: 40012000 .word 0x40012000
8004bf8: 40012200 .word 0x40012200
08004bfc <HAL_ADC_PollForConversion>:
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8004bfc: b580 push {r7, lr}
8004bfe: b084 sub sp, #16
8004c00: af00 add r7, sp, #0
8004c02: 6078 str r0, [r7, #4]
8004c04: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8004c06: 2300 movs r3, #0
8004c08: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004c0a: 687b ldr r3, [r7, #4]
8004c0c: 681b ldr r3, [r3, #0]
8004c0e: 689b ldr r3, [r3, #8]
8004c10: f403 6380 and.w r3, r3, #1024 ; 0x400
8004c14: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8004c18: d113 bne.n 8004c42 <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
8004c1a: 687b ldr r3, [r7, #4]
8004c1c: 681b ldr r3, [r3, #0]
8004c1e: 689b ldr r3, [r3, #8]
8004c20: f403 7380 and.w r3, r3, #256 ; 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004c24: f5b3 7f80 cmp.w r3, #256 ; 0x100
8004c28: d10b bne.n 8004c42 <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8004c2a: 687b ldr r3, [r7, #4]
8004c2c: 6c1b ldr r3, [r3, #64] ; 0x40
8004c2e: f043 0220 orr.w r2, r3, #32
8004c32: 687b ldr r3, [r7, #4]
8004c34: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004c36: 687b ldr r3, [r7, #4]
8004c38: 2200 movs r2, #0
8004c3a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8004c3e: 2301 movs r3, #1
8004c40: e05c b.n 8004cfc <HAL_ADC_PollForConversion+0x100>
}
/* Get tick */
tickstart = HAL_GetTick();
8004c42: f7ff fea9 bl 8004998 <HAL_GetTick>
8004c46: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004c48: e01a b.n 8004c80 <HAL_ADC_PollForConversion+0x84>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
8004c4a: 683b ldr r3, [r7, #0]
8004c4c: f1b3 3fff cmp.w r3, #4294967295
8004c50: d016 beq.n 8004c80 <HAL_ADC_PollForConversion+0x84>
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
8004c52: 683b ldr r3, [r7, #0]
8004c54: 2b00 cmp r3, #0
8004c56: d007 beq.n 8004c68 <HAL_ADC_PollForConversion+0x6c>
8004c58: f7ff fe9e bl 8004998 <HAL_GetTick>
8004c5c: 4602 mov r2, r0
8004c5e: 68fb ldr r3, [r7, #12]
8004c60: 1ad3 subs r3, r2, r3
8004c62: 683a ldr r2, [r7, #0]
8004c64: 429a cmp r2, r3
8004c66: d20b bcs.n 8004c80 <HAL_ADC_PollForConversion+0x84>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8004c68: 687b ldr r3, [r7, #4]
8004c6a: 6c1b ldr r3, [r3, #64] ; 0x40
8004c6c: f043 0204 orr.w r2, r3, #4
8004c70: 687b ldr r3, [r7, #4]
8004c72: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004c74: 687b ldr r3, [r7, #4]
8004c76: 2200 movs r2, #0
8004c78: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8004c7c: 2303 movs r3, #3
8004c7e: e03d b.n 8004cfc <HAL_ADC_PollForConversion+0x100>
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004c80: 687b ldr r3, [r7, #4]
8004c82: 681b ldr r3, [r3, #0]
8004c84: 681b ldr r3, [r3, #0]
8004c86: f003 0302 and.w r3, r3, #2
8004c8a: 2b02 cmp r3, #2
8004c8c: d1dd bne.n 8004c4a <HAL_ADC_PollForConversion+0x4e>
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8004c8e: 687b ldr r3, [r7, #4]
8004c90: 681b ldr r3, [r3, #0]
8004c92: f06f 0212 mvn.w r2, #18
8004c96: 601a str r2, [r3, #0]
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8004c98: 687b ldr r3, [r7, #4]
8004c9a: 6c1b ldr r3, [r3, #64] ; 0x40
8004c9c: f443 7200 orr.w r2, r3, #512 ; 0x200
8004ca0: 687b ldr r3, [r7, #4]
8004ca2: 641a str r2, [r3, #64] ; 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004ca4: 687b ldr r3, [r7, #4]
8004ca6: 681b ldr r3, [r3, #0]
8004ca8: 689b ldr r3, [r3, #8]
8004caa: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004cae: 2b00 cmp r3, #0
8004cb0: d123 bne.n 8004cfa <HAL_ADC_PollForConversion+0xfe>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004cb2: 687b ldr r3, [r7, #4]
8004cb4: 699b ldr r3, [r3, #24]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004cb6: 2b00 cmp r3, #0
8004cb8: d11f bne.n 8004cfa <HAL_ADC_PollForConversion+0xfe>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 681b ldr r3, [r3, #0]
8004cbe: 6adb ldr r3, [r3, #44] ; 0x2c
8004cc0: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004cc4: 2b00 cmp r3, #0
8004cc6: d006 beq.n 8004cd6 <HAL_ADC_PollForConversion+0xda>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
8004cc8: 687b ldr r3, [r7, #4]
8004cca: 681b ldr r3, [r3, #0]
8004ccc: 689b ldr r3, [r3, #8]
8004cce: f403 6380 and.w r3, r3, #1024 ; 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004cd2: 2b00 cmp r3, #0
8004cd4: d111 bne.n 8004cfa <HAL_ADC_PollForConversion+0xfe>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8004cd6: 687b ldr r3, [r7, #4]
8004cd8: 6c1b ldr r3, [r3, #64] ; 0x40
8004cda: f423 7280 bic.w r2, r3, #256 ; 0x100
8004cde: 687b ldr r3, [r7, #4]
8004ce0: 641a str r2, [r3, #64] ; 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004ce2: 687b ldr r3, [r7, #4]
8004ce4: 6c1b ldr r3, [r3, #64] ; 0x40
8004ce6: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004cea: 2b00 cmp r3, #0
8004cec: d105 bne.n 8004cfa <HAL_ADC_PollForConversion+0xfe>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8004cee: 687b ldr r3, [r7, #4]
8004cf0: 6c1b ldr r3, [r3, #64] ; 0x40
8004cf2: f043 0201 orr.w r2, r3, #1
8004cf6: 687b ldr r3, [r7, #4]
8004cf8: 641a str r2, [r3, #64] ; 0x40
}
}
/* Return ADC state */
return HAL_OK;
8004cfa: 2300 movs r3, #0
}
8004cfc: 4618 mov r0, r3
8004cfe: 3710 adds r7, #16
8004d00: 46bd mov sp, r7
8004d02: bd80 pop {r7, pc}
08004d04 <HAL_ADC_GetValue>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8004d04: b480 push {r7}
8004d06: b083 sub sp, #12
8004d08: af00 add r7, sp, #0
8004d0a: 6078 str r0, [r7, #4]
/* Return the selected ADC converted value */
return hadc->Instance->DR;
8004d0c: 687b ldr r3, [r7, #4]
8004d0e: 681b ldr r3, [r3, #0]
8004d10: 6cdb ldr r3, [r3, #76] ; 0x4c
}
8004d12: 4618 mov r0, r3
8004d14: 370c adds r7, #12
8004d16: 46bd mov sp, r7
8004d18: f85d 7b04 ldr.w r7, [sp], #4
8004d1c: 4770 bx lr
...
08004d20 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8004d20: b480 push {r7}
8004d22: b085 sub sp, #20
8004d24: af00 add r7, sp, #0
8004d26: 6078 str r0, [r7, #4]
8004d28: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0;
8004d2a: 2300 movs r3, #0
8004d2c: 60fb str r3, [r7, #12]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8004d2e: 687b ldr r3, [r7, #4]
8004d30: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004d34: 2b01 cmp r3, #1
8004d36: d101 bne.n 8004d3c <HAL_ADC_ConfigChannel+0x1c>
8004d38: 2302 movs r3, #2
8004d3a: e12a b.n 8004f92 <HAL_ADC_ConfigChannel+0x272>
8004d3c: 687b ldr r3, [r7, #4]
8004d3e: 2201 movs r2, #1
8004d40: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
8004d44: 683b ldr r3, [r7, #0]
8004d46: 681b ldr r3, [r3, #0]
8004d48: 2b09 cmp r3, #9
8004d4a: d93a bls.n 8004dc2 <HAL_ADC_ConfigChannel+0xa2>
8004d4c: 683b ldr r3, [r7, #0]
8004d4e: 681b ldr r3, [r3, #0]
8004d50: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004d54: d035 beq.n 8004dc2 <HAL_ADC_ConfigChannel+0xa2>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
8004d56: 687b ldr r3, [r7, #4]
8004d58: 681b ldr r3, [r3, #0]
8004d5a: 68d9 ldr r1, [r3, #12]
8004d5c: 683b ldr r3, [r7, #0]
8004d5e: 681b ldr r3, [r3, #0]
8004d60: b29b uxth r3, r3
8004d62: 461a mov r2, r3
8004d64: 4613 mov r3, r2
8004d66: 005b lsls r3, r3, #1
8004d68: 4413 add r3, r2
8004d6a: 3b1e subs r3, #30
8004d6c: 2207 movs r2, #7
8004d6e: fa02 f303 lsl.w r3, r2, r3
8004d72: 43da mvns r2, r3
8004d74: 687b ldr r3, [r7, #4]
8004d76: 681b ldr r3, [r3, #0]
8004d78: 400a ands r2, r1
8004d7a: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004d7c: 683b ldr r3, [r7, #0]
8004d7e: 681b ldr r3, [r3, #0]
8004d80: 4a87 ldr r2, [pc, #540] ; (8004fa0 <HAL_ADC_ConfigChannel+0x280>)
8004d82: 4293 cmp r3, r2
8004d84: d10a bne.n 8004d9c <HAL_ADC_ConfigChannel+0x7c>
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
8004d86: 687b ldr r3, [r7, #4]
8004d88: 681b ldr r3, [r3, #0]
8004d8a: 68d9 ldr r1, [r3, #12]
8004d8c: 683b ldr r3, [r7, #0]
8004d8e: 689b ldr r3, [r3, #8]
8004d90: 061a lsls r2, r3, #24
8004d92: 687b ldr r3, [r7, #4]
8004d94: 681b ldr r3, [r3, #0]
8004d96: 430a orrs r2, r1
8004d98: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004d9a: e035 b.n 8004e08 <HAL_ADC_ConfigChannel+0xe8>
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
8004d9c: 687b ldr r3, [r7, #4]
8004d9e: 681b ldr r3, [r3, #0]
8004da0: 68d9 ldr r1, [r3, #12]
8004da2: 683b ldr r3, [r7, #0]
8004da4: 689a ldr r2, [r3, #8]
8004da6: 683b ldr r3, [r7, #0]
8004da8: 681b ldr r3, [r3, #0]
8004daa: b29b uxth r3, r3
8004dac: 4618 mov r0, r3
8004dae: 4603 mov r3, r0
8004db0: 005b lsls r3, r3, #1
8004db2: 4403 add r3, r0
8004db4: 3b1e subs r3, #30
8004db6: 409a lsls r2, r3
8004db8: 687b ldr r3, [r7, #4]
8004dba: 681b ldr r3, [r3, #0]
8004dbc: 430a orrs r2, r1
8004dbe: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004dc0: e022 b.n 8004e08 <HAL_ADC_ConfigChannel+0xe8>
}
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
8004dc2: 687b ldr r3, [r7, #4]
8004dc4: 681b ldr r3, [r3, #0]
8004dc6: 6919 ldr r1, [r3, #16]
8004dc8: 683b ldr r3, [r7, #0]
8004dca: 681b ldr r3, [r3, #0]
8004dcc: b29b uxth r3, r3
8004dce: 461a mov r2, r3
8004dd0: 4613 mov r3, r2
8004dd2: 005b lsls r3, r3, #1
8004dd4: 4413 add r3, r2
8004dd6: 2207 movs r2, #7
8004dd8: fa02 f303 lsl.w r3, r2, r3
8004ddc: 43da mvns r2, r3
8004dde: 687b ldr r3, [r7, #4]
8004de0: 681b ldr r3, [r3, #0]
8004de2: 400a ands r2, r1
8004de4: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
8004de6: 687b ldr r3, [r7, #4]
8004de8: 681b ldr r3, [r3, #0]
8004dea: 6919 ldr r1, [r3, #16]
8004dec: 683b ldr r3, [r7, #0]
8004dee: 689a ldr r2, [r3, #8]
8004df0: 683b ldr r3, [r7, #0]
8004df2: 681b ldr r3, [r3, #0]
8004df4: b29b uxth r3, r3
8004df6: 4618 mov r0, r3
8004df8: 4603 mov r3, r0
8004dfa: 005b lsls r3, r3, #1
8004dfc: 4403 add r3, r0
8004dfe: 409a lsls r2, r3
8004e00: 687b ldr r3, [r7, #4]
8004e02: 681b ldr r3, [r3, #0]
8004e04: 430a orrs r2, r1
8004e06: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
8004e08: 683b ldr r3, [r7, #0]
8004e0a: 685b ldr r3, [r3, #4]
8004e0c: 2b06 cmp r3, #6
8004e0e: d824 bhi.n 8004e5a <HAL_ADC_ConfigChannel+0x13a>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8004e10: 687b ldr r3, [r7, #4]
8004e12: 681b ldr r3, [r3, #0]
8004e14: 6b59 ldr r1, [r3, #52] ; 0x34
8004e16: 683b ldr r3, [r7, #0]
8004e18: 685a ldr r2, [r3, #4]
8004e1a: 4613 mov r3, r2
8004e1c: 009b lsls r3, r3, #2
8004e1e: 4413 add r3, r2
8004e20: 3b05 subs r3, #5
8004e22: 221f movs r2, #31
8004e24: fa02 f303 lsl.w r3, r2, r3
8004e28: 43da mvns r2, r3
8004e2a: 687b ldr r3, [r7, #4]
8004e2c: 681b ldr r3, [r3, #0]
8004e2e: 400a ands r2, r1
8004e30: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
8004e32: 687b ldr r3, [r7, #4]
8004e34: 681b ldr r3, [r3, #0]
8004e36: 6b59 ldr r1, [r3, #52] ; 0x34
8004e38: 683b ldr r3, [r7, #0]
8004e3a: 681b ldr r3, [r3, #0]
8004e3c: b29b uxth r3, r3
8004e3e: 4618 mov r0, r3
8004e40: 683b ldr r3, [r7, #0]
8004e42: 685a ldr r2, [r3, #4]
8004e44: 4613 mov r3, r2
8004e46: 009b lsls r3, r3, #2
8004e48: 4413 add r3, r2
8004e4a: 3b05 subs r3, #5
8004e4c: fa00 f203 lsl.w r2, r0, r3
8004e50: 687b ldr r3, [r7, #4]
8004e52: 681b ldr r3, [r3, #0]
8004e54: 430a orrs r2, r1
8004e56: 635a str r2, [r3, #52] ; 0x34
8004e58: e04c b.n 8004ef4 <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
8004e5a: 683b ldr r3, [r7, #0]
8004e5c: 685b ldr r3, [r3, #4]
8004e5e: 2b0c cmp r3, #12
8004e60: d824 bhi.n 8004eac <HAL_ADC_ConfigChannel+0x18c>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
8004e62: 687b ldr r3, [r7, #4]
8004e64: 681b ldr r3, [r3, #0]
8004e66: 6b19 ldr r1, [r3, #48] ; 0x30
8004e68: 683b ldr r3, [r7, #0]
8004e6a: 685a ldr r2, [r3, #4]
8004e6c: 4613 mov r3, r2
8004e6e: 009b lsls r3, r3, #2
8004e70: 4413 add r3, r2
8004e72: 3b23 subs r3, #35 ; 0x23
8004e74: 221f movs r2, #31
8004e76: fa02 f303 lsl.w r3, r2, r3
8004e7a: 43da mvns r2, r3
8004e7c: 687b ldr r3, [r7, #4]
8004e7e: 681b ldr r3, [r3, #0]
8004e80: 400a ands r2, r1
8004e82: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
8004e84: 687b ldr r3, [r7, #4]
8004e86: 681b ldr r3, [r3, #0]
8004e88: 6b19 ldr r1, [r3, #48] ; 0x30
8004e8a: 683b ldr r3, [r7, #0]
8004e8c: 681b ldr r3, [r3, #0]
8004e8e: b29b uxth r3, r3
8004e90: 4618 mov r0, r3
8004e92: 683b ldr r3, [r7, #0]
8004e94: 685a ldr r2, [r3, #4]
8004e96: 4613 mov r3, r2
8004e98: 009b lsls r3, r3, #2
8004e9a: 4413 add r3, r2
8004e9c: 3b23 subs r3, #35 ; 0x23
8004e9e: fa00 f203 lsl.w r2, r0, r3
8004ea2: 687b ldr r3, [r7, #4]
8004ea4: 681b ldr r3, [r3, #0]
8004ea6: 430a orrs r2, r1
8004ea8: 631a str r2, [r3, #48] ; 0x30
8004eaa: e023 b.n 8004ef4 <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
8004eac: 687b ldr r3, [r7, #4]
8004eae: 681b ldr r3, [r3, #0]
8004eb0: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004eb2: 683b ldr r3, [r7, #0]
8004eb4: 685a ldr r2, [r3, #4]
8004eb6: 4613 mov r3, r2
8004eb8: 009b lsls r3, r3, #2
8004eba: 4413 add r3, r2
8004ebc: 3b41 subs r3, #65 ; 0x41
8004ebe: 221f movs r2, #31
8004ec0: fa02 f303 lsl.w r3, r2, r3
8004ec4: 43da mvns r2, r3
8004ec6: 687b ldr r3, [r7, #4]
8004ec8: 681b ldr r3, [r3, #0]
8004eca: 400a ands r2, r1
8004ecc: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8004ece: 687b ldr r3, [r7, #4]
8004ed0: 681b ldr r3, [r3, #0]
8004ed2: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004ed4: 683b ldr r3, [r7, #0]
8004ed6: 681b ldr r3, [r3, #0]
8004ed8: b29b uxth r3, r3
8004eda: 4618 mov r0, r3
8004edc: 683b ldr r3, [r7, #0]
8004ede: 685a ldr r2, [r3, #4]
8004ee0: 4613 mov r3, r2
8004ee2: 009b lsls r3, r3, #2
8004ee4: 4413 add r3, r2
8004ee6: 3b41 subs r3, #65 ; 0x41
8004ee8: fa00 f203 lsl.w r2, r0, r3
8004eec: 687b ldr r3, [r7, #4]
8004eee: 681b ldr r3, [r3, #0]
8004ef0: 430a orrs r2, r1
8004ef2: 62da str r2, [r3, #44] ; 0x2c
}
/* if no internal channel selected */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
8004ef4: 687b ldr r3, [r7, #4]
8004ef6: 681b ldr r3, [r3, #0]
8004ef8: 4a2a ldr r2, [pc, #168] ; (8004fa4 <HAL_ADC_ConfigChannel+0x284>)
8004efa: 4293 cmp r3, r2
8004efc: d10a bne.n 8004f14 <HAL_ADC_ConfigChannel+0x1f4>
8004efe: 683b ldr r3, [r7, #0]
8004f00: 681b ldr r3, [r3, #0]
8004f02: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004f06: d105 bne.n 8004f14 <HAL_ADC_ConfigChannel+0x1f4>
{
/* Disable the VBAT & TSVREFE channel*/
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
8004f08: 4b27 ldr r3, [pc, #156] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f0a: 685b ldr r3, [r3, #4]
8004f0c: 4a26 ldr r2, [pc, #152] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f0e: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000
8004f12: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
8004f14: 687b ldr r3, [r7, #4]
8004f16: 681b ldr r3, [r3, #0]
8004f18: 4a22 ldr r2, [pc, #136] ; (8004fa4 <HAL_ADC_ConfigChannel+0x284>)
8004f1a: 4293 cmp r3, r2
8004f1c: d109 bne.n 8004f32 <HAL_ADC_ConfigChannel+0x212>
8004f1e: 683b ldr r3, [r7, #0]
8004f20: 681b ldr r3, [r3, #0]
8004f22: 2b12 cmp r3, #18
8004f24: d105 bne.n 8004f32 <HAL_ADC_ConfigChannel+0x212>
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
8004f26: 4b20 ldr r3, [pc, #128] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f28: 685b ldr r3, [r3, #4]
8004f2a: 4a1f ldr r2, [pc, #124] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f2c: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8004f30: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8004f32: 687b ldr r3, [r7, #4]
8004f34: 681b ldr r3, [r3, #0]
8004f36: 4a1b ldr r2, [pc, #108] ; (8004fa4 <HAL_ADC_ConfigChannel+0x284>)
8004f38: 4293 cmp r3, r2
8004f3a: d125 bne.n 8004f88 <HAL_ADC_ConfigChannel+0x268>
8004f3c: 683b ldr r3, [r7, #0]
8004f3e: 681b ldr r3, [r3, #0]
8004f40: 4a17 ldr r2, [pc, #92] ; (8004fa0 <HAL_ADC_ConfigChannel+0x280>)
8004f42: 4293 cmp r3, r2
8004f44: d003 beq.n 8004f4e <HAL_ADC_ConfigChannel+0x22e>
8004f46: 683b ldr r3, [r7, #0]
8004f48: 681b ldr r3, [r3, #0]
8004f4a: 2b11 cmp r3, #17
8004f4c: d11c bne.n 8004f88 <HAL_ADC_ConfigChannel+0x268>
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
8004f4e: 4b16 ldr r3, [pc, #88] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f50: 685b ldr r3, [r3, #4]
8004f52: 4a15 ldr r2, [pc, #84] ; (8004fa8 <HAL_ADC_ConfigChannel+0x288>)
8004f54: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8004f58: 6053 str r3, [r2, #4]
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004f5a: 683b ldr r3, [r7, #0]
8004f5c: 681b ldr r3, [r3, #0]
8004f5e: 4a10 ldr r2, [pc, #64] ; (8004fa0 <HAL_ADC_ConfigChannel+0x280>)
8004f60: 4293 cmp r3, r2
8004f62: d111 bne.n 8004f88 <HAL_ADC_ConfigChannel+0x268>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
8004f64: 4b11 ldr r3, [pc, #68] ; (8004fac <HAL_ADC_ConfigChannel+0x28c>)
8004f66: 681b ldr r3, [r3, #0]
8004f68: 4a11 ldr r2, [pc, #68] ; (8004fb0 <HAL_ADC_ConfigChannel+0x290>)
8004f6a: fba2 2303 umull r2, r3, r2, r3
8004f6e: 0c9a lsrs r2, r3, #18
8004f70: 4613 mov r3, r2
8004f72: 009b lsls r3, r3, #2
8004f74: 4413 add r3, r2
8004f76: 005b lsls r3, r3, #1
8004f78: 60fb str r3, [r7, #12]
while(counter != 0)
8004f7a: e002 b.n 8004f82 <HAL_ADC_ConfigChannel+0x262>
{
counter--;
8004f7c: 68fb ldr r3, [r7, #12]
8004f7e: 3b01 subs r3, #1
8004f80: 60fb str r3, [r7, #12]
while(counter != 0)
8004f82: 68fb ldr r3, [r7, #12]
8004f84: 2b00 cmp r3, #0
8004f86: d1f9 bne.n 8004f7c <HAL_ADC_ConfigChannel+0x25c>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004f88: 687b ldr r3, [r7, #4]
8004f8a: 2200 movs r2, #0
8004f8c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8004f90: 2300 movs r3, #0
}
8004f92: 4618 mov r0, r3
8004f94: 3714 adds r7, #20
8004f96: 46bd mov sp, r7
8004f98: f85d 7b04 ldr.w r7, [sp], #4
8004f9c: 4770 bx lr
8004f9e: bf00 nop
8004fa0: 10000012 .word 0x10000012
8004fa4: 40012000 .word 0x40012000
8004fa8: 40012300 .word 0x40012300
8004fac: 20000064 .word 0x20000064
8004fb0: 431bde83 .word 0x431bde83
08004fb4 <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
8004fb4: b480 push {r7}
8004fb6: b083 sub sp, #12
8004fb8: af00 add r7, sp, #0
8004fba: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
8004fbc: 4b78 ldr r3, [pc, #480] ; (80051a0 <ADC_Init+0x1ec>)
8004fbe: 685b ldr r3, [r3, #4]
8004fc0: 4a77 ldr r2, [pc, #476] ; (80051a0 <ADC_Init+0x1ec>)
8004fc2: f423 3340 bic.w r3, r3, #196608 ; 0x30000
8004fc6: 6053 str r3, [r2, #4]
ADC->CCR |= hadc->Init.ClockPrescaler;
8004fc8: 4b75 ldr r3, [pc, #468] ; (80051a0 <ADC_Init+0x1ec>)
8004fca: 685a ldr r2, [r3, #4]
8004fcc: 687b ldr r3, [r7, #4]
8004fce: 685b ldr r3, [r3, #4]
8004fd0: 4973 ldr r1, [pc, #460] ; (80051a0 <ADC_Init+0x1ec>)
8004fd2: 4313 orrs r3, r2
8004fd4: 604b str r3, [r1, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
8004fd6: 687b ldr r3, [r7, #4]
8004fd8: 681b ldr r3, [r3, #0]
8004fda: 685a ldr r2, [r3, #4]
8004fdc: 687b ldr r3, [r7, #4]
8004fde: 681b ldr r3, [r3, #0]
8004fe0: f422 7280 bic.w r2, r2, #256 ; 0x100
8004fe4: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
8004fe6: 687b ldr r3, [r7, #4]
8004fe8: 681b ldr r3, [r3, #0]
8004fea: 6859 ldr r1, [r3, #4]
8004fec: 687b ldr r3, [r7, #4]
8004fee: 691b ldr r3, [r3, #16]
8004ff0: 021a lsls r2, r3, #8
8004ff2: 687b ldr r3, [r7, #4]
8004ff4: 681b ldr r3, [r3, #0]
8004ff6: 430a orrs r2, r1
8004ff8: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
8004ffa: 687b ldr r3, [r7, #4]
8004ffc: 681b ldr r3, [r3, #0]
8004ffe: 685a ldr r2, [r3, #4]
8005000: 687b ldr r3, [r7, #4]
8005002: 681b ldr r3, [r3, #0]
8005004: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
8005008: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
800500a: 687b ldr r3, [r7, #4]
800500c: 681b ldr r3, [r3, #0]
800500e: 6859 ldr r1, [r3, #4]
8005010: 687b ldr r3, [r7, #4]
8005012: 689a ldr r2, [r3, #8]
8005014: 687b ldr r3, [r7, #4]
8005016: 681b ldr r3, [r3, #0]
8005018: 430a orrs r2, r1
800501a: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
800501c: 687b ldr r3, [r7, #4]
800501e: 681b ldr r3, [r3, #0]
8005020: 689a ldr r2, [r3, #8]
8005022: 687b ldr r3, [r7, #4]
8005024: 681b ldr r3, [r3, #0]
8005026: f422 6200 bic.w r2, r2, #2048 ; 0x800
800502a: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
800502c: 687b ldr r3, [r7, #4]
800502e: 681b ldr r3, [r3, #0]
8005030: 6899 ldr r1, [r3, #8]
8005032: 687b ldr r3, [r7, #4]
8005034: 68da ldr r2, [r3, #12]
8005036: 687b ldr r3, [r7, #4]
8005038: 681b ldr r3, [r3, #0]
800503a: 430a orrs r2, r1
800503c: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
800503e: 687b ldr r3, [r7, #4]
8005040: 6a9b ldr r3, [r3, #40] ; 0x28
8005042: 4a58 ldr r2, [pc, #352] ; (80051a4 <ADC_Init+0x1f0>)
8005044: 4293 cmp r3, r2
8005046: d022 beq.n 800508e <ADC_Init+0xda>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8005048: 687b ldr r3, [r7, #4]
800504a: 681b ldr r3, [r3, #0]
800504c: 689a ldr r2, [r3, #8]
800504e: 687b ldr r3, [r7, #4]
8005050: 681b ldr r3, [r3, #0]
8005052: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8005056: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
8005058: 687b ldr r3, [r7, #4]
800505a: 681b ldr r3, [r3, #0]
800505c: 6899 ldr r1, [r3, #8]
800505e: 687b ldr r3, [r7, #4]
8005060: 6a9a ldr r2, [r3, #40] ; 0x28
8005062: 687b ldr r3, [r7, #4]
8005064: 681b ldr r3, [r3, #0]
8005066: 430a orrs r2, r1
8005068: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
800506a: 687b ldr r3, [r7, #4]
800506c: 681b ldr r3, [r3, #0]
800506e: 689a ldr r2, [r3, #8]
8005070: 687b ldr r3, [r7, #4]
8005072: 681b ldr r3, [r3, #0]
8005074: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8005078: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
800507a: 687b ldr r3, [r7, #4]
800507c: 681b ldr r3, [r3, #0]
800507e: 6899 ldr r1, [r3, #8]
8005080: 687b ldr r3, [r7, #4]
8005082: 6ada ldr r2, [r3, #44] ; 0x2c
8005084: 687b ldr r3, [r7, #4]
8005086: 681b ldr r3, [r3, #0]
8005088: 430a orrs r2, r1
800508a: 609a str r2, [r3, #8]
800508c: e00f b.n 80050ae <ADC_Init+0xfa>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
800508e: 687b ldr r3, [r7, #4]
8005090: 681b ldr r3, [r3, #0]
8005092: 689a ldr r2, [r3, #8]
8005094: 687b ldr r3, [r7, #4]
8005096: 681b ldr r3, [r3, #0]
8005098: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
800509c: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
800509e: 687b ldr r3, [r7, #4]
80050a0: 681b ldr r3, [r3, #0]
80050a2: 689a ldr r2, [r3, #8]
80050a4: 687b ldr r3, [r7, #4]
80050a6: 681b ldr r3, [r3, #0]
80050a8: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
80050ac: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
80050ae: 687b ldr r3, [r7, #4]
80050b0: 681b ldr r3, [r3, #0]
80050b2: 689a ldr r2, [r3, #8]
80050b4: 687b ldr r3, [r7, #4]
80050b6: 681b ldr r3, [r3, #0]
80050b8: f022 0202 bic.w r2, r2, #2
80050bc: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
80050be: 687b ldr r3, [r7, #4]
80050c0: 681b ldr r3, [r3, #0]
80050c2: 6899 ldr r1, [r3, #8]
80050c4: 687b ldr r3, [r7, #4]
80050c6: 699b ldr r3, [r3, #24]
80050c8: 005a lsls r2, r3, #1
80050ca: 687b ldr r3, [r7, #4]
80050cc: 681b ldr r3, [r3, #0]
80050ce: 430a orrs r2, r1
80050d0: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
80050d2: 687b ldr r3, [r7, #4]
80050d4: f893 3020 ldrb.w r3, [r3, #32]
80050d8: 2b00 cmp r3, #0
80050da: d01b beq.n 8005114 <ADC_Init+0x160>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
80050dc: 687b ldr r3, [r7, #4]
80050de: 681b ldr r3, [r3, #0]
80050e0: 685a ldr r2, [r3, #4]
80050e2: 687b ldr r3, [r7, #4]
80050e4: 681b ldr r3, [r3, #0]
80050e6: f442 6200 orr.w r2, r2, #2048 ; 0x800
80050ea: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
80050ec: 687b ldr r3, [r7, #4]
80050ee: 681b ldr r3, [r3, #0]
80050f0: 685a ldr r2, [r3, #4]
80050f2: 687b ldr r3, [r7, #4]
80050f4: 681b ldr r3, [r3, #0]
80050f6: f422 4260 bic.w r2, r2, #57344 ; 0xe000
80050fa: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
80050fc: 687b ldr r3, [r7, #4]
80050fe: 681b ldr r3, [r3, #0]
8005100: 6859 ldr r1, [r3, #4]
8005102: 687b ldr r3, [r7, #4]
8005104: 6a5b ldr r3, [r3, #36] ; 0x24
8005106: 3b01 subs r3, #1
8005108: 035a lsls r2, r3, #13
800510a: 687b ldr r3, [r7, #4]
800510c: 681b ldr r3, [r3, #0]
800510e: 430a orrs r2, r1
8005110: 605a str r2, [r3, #4]
8005112: e007 b.n 8005124 <ADC_Init+0x170>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
8005114: 687b ldr r3, [r7, #4]
8005116: 681b ldr r3, [r3, #0]
8005118: 685a ldr r2, [r3, #4]
800511a: 687b ldr r3, [r7, #4]
800511c: 681b ldr r3, [r3, #0]
800511e: f422 6200 bic.w r2, r2, #2048 ; 0x800
8005122: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
8005124: 687b ldr r3, [r7, #4]
8005126: 681b ldr r3, [r3, #0]
8005128: 6ada ldr r2, [r3, #44] ; 0x2c
800512a: 687b ldr r3, [r7, #4]
800512c: 681b ldr r3, [r3, #0]
800512e: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
8005132: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
8005134: 687b ldr r3, [r7, #4]
8005136: 681b ldr r3, [r3, #0]
8005138: 6ad9 ldr r1, [r3, #44] ; 0x2c
800513a: 687b ldr r3, [r7, #4]
800513c: 69db ldr r3, [r3, #28]
800513e: 3b01 subs r3, #1
8005140: 051a lsls r2, r3, #20
8005142: 687b ldr r3, [r7, #4]
8005144: 681b ldr r3, [r3, #0]
8005146: 430a orrs r2, r1
8005148: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
800514a: 687b ldr r3, [r7, #4]
800514c: 681b ldr r3, [r3, #0]
800514e: 689a ldr r2, [r3, #8]
8005150: 687b ldr r3, [r7, #4]
8005152: 681b ldr r3, [r3, #0]
8005154: f422 7200 bic.w r2, r2, #512 ; 0x200
8005158: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
800515a: 687b ldr r3, [r7, #4]
800515c: 681b ldr r3, [r3, #0]
800515e: 6899 ldr r1, [r3, #8]
8005160: 687b ldr r3, [r7, #4]
8005162: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8005166: 025a lsls r2, r3, #9
8005168: 687b ldr r3, [r7, #4]
800516a: 681b ldr r3, [r3, #0]
800516c: 430a orrs r2, r1
800516e: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8005170: 687b ldr r3, [r7, #4]
8005172: 681b ldr r3, [r3, #0]
8005174: 689a ldr r2, [r3, #8]
8005176: 687b ldr r3, [r7, #4]
8005178: 681b ldr r3, [r3, #0]
800517a: f422 6280 bic.w r2, r2, #1024 ; 0x400
800517e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8005180: 687b ldr r3, [r7, #4]
8005182: 681b ldr r3, [r3, #0]
8005184: 6899 ldr r1, [r3, #8]
8005186: 687b ldr r3, [r7, #4]
8005188: 695b ldr r3, [r3, #20]
800518a: 029a lsls r2, r3, #10
800518c: 687b ldr r3, [r7, #4]
800518e: 681b ldr r3, [r3, #0]
8005190: 430a orrs r2, r1
8005192: 609a str r2, [r3, #8]
}
8005194: bf00 nop
8005196: 370c adds r7, #12
8005198: 46bd mov sp, r7
800519a: f85d 7b04 ldr.w r7, [sp], #4
800519e: 4770 bx lr
80051a0: 40012300 .word 0x40012300
80051a4: 0f000001 .word 0x0f000001
080051a8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80051a8: b480 push {r7}
80051aa: b085 sub sp, #20
80051ac: af00 add r7, sp, #0
80051ae: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80051b0: 687b ldr r3, [r7, #4]
80051b2: f003 0307 and.w r3, r3, #7
80051b6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80051b8: 4b0b ldr r3, [pc, #44] ; (80051e8 <__NVIC_SetPriorityGrouping+0x40>)
80051ba: 68db ldr r3, [r3, #12]
80051bc: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80051be: 68ba ldr r2, [r7, #8]
80051c0: f64f 03ff movw r3, #63743 ; 0xf8ff
80051c4: 4013 ands r3, r2
80051c6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80051c8: 68fb ldr r3, [r7, #12]
80051ca: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80051cc: 68bb ldr r3, [r7, #8]
80051ce: 431a orrs r2, r3
reg_value = (reg_value |
80051d0: 4b06 ldr r3, [pc, #24] ; (80051ec <__NVIC_SetPriorityGrouping+0x44>)
80051d2: 4313 orrs r3, r2
80051d4: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80051d6: 4a04 ldr r2, [pc, #16] ; (80051e8 <__NVIC_SetPriorityGrouping+0x40>)
80051d8: 68bb ldr r3, [r7, #8]
80051da: 60d3 str r3, [r2, #12]
}
80051dc: bf00 nop
80051de: 3714 adds r7, #20
80051e0: 46bd mov sp, r7
80051e2: f85d 7b04 ldr.w r7, [sp], #4
80051e6: 4770 bx lr
80051e8: e000ed00 .word 0xe000ed00
80051ec: 05fa0000 .word 0x05fa0000
080051f0 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80051f0: b480 push {r7}
80051f2: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80051f4: 4b04 ldr r3, [pc, #16] ; (8005208 <__NVIC_GetPriorityGrouping+0x18>)
80051f6: 68db ldr r3, [r3, #12]
80051f8: 0a1b lsrs r3, r3, #8
80051fa: f003 0307 and.w r3, r3, #7
}
80051fe: 4618 mov r0, r3
8005200: 46bd mov sp, r7
8005202: f85d 7b04 ldr.w r7, [sp], #4
8005206: 4770 bx lr
8005208: e000ed00 .word 0xe000ed00
0800520c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800520c: b480 push {r7}
800520e: b083 sub sp, #12
8005210: af00 add r7, sp, #0
8005212: 4603 mov r3, r0
8005214: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8005216: f997 3007 ldrsb.w r3, [r7, #7]
800521a: 2b00 cmp r3, #0
800521c: db0b blt.n 8005236 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
800521e: 79fb ldrb r3, [r7, #7]
8005220: f003 021f and.w r2, r3, #31
8005224: 4907 ldr r1, [pc, #28] ; (8005244 <__NVIC_EnableIRQ+0x38>)
8005226: f997 3007 ldrsb.w r3, [r7, #7]
800522a: 095b lsrs r3, r3, #5
800522c: 2001 movs r0, #1
800522e: fa00 f202 lsl.w r2, r0, r2
8005232: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8005236: bf00 nop
8005238: 370c adds r7, #12
800523a: 46bd mov sp, r7
800523c: f85d 7b04 ldr.w r7, [sp], #4
8005240: 4770 bx lr
8005242: bf00 nop
8005244: e000e100 .word 0xe000e100
08005248 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8005248: b480 push {r7}
800524a: b083 sub sp, #12
800524c: af00 add r7, sp, #0
800524e: 4603 mov r3, r0
8005250: 6039 str r1, [r7, #0]
8005252: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8005254: f997 3007 ldrsb.w r3, [r7, #7]
8005258: 2b00 cmp r3, #0
800525a: db0a blt.n 8005272 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800525c: 683b ldr r3, [r7, #0]
800525e: b2da uxtb r2, r3
8005260: 490c ldr r1, [pc, #48] ; (8005294 <__NVIC_SetPriority+0x4c>)
8005262: f997 3007 ldrsb.w r3, [r7, #7]
8005266: 0112 lsls r2, r2, #4
8005268: b2d2 uxtb r2, r2
800526a: 440b add r3, r1
800526c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8005270: e00a b.n 8005288 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8005272: 683b ldr r3, [r7, #0]
8005274: b2da uxtb r2, r3
8005276: 4908 ldr r1, [pc, #32] ; (8005298 <__NVIC_SetPriority+0x50>)
8005278: 79fb ldrb r3, [r7, #7]
800527a: f003 030f and.w r3, r3, #15
800527e: 3b04 subs r3, #4
8005280: 0112 lsls r2, r2, #4
8005282: b2d2 uxtb r2, r2
8005284: 440b add r3, r1
8005286: 761a strb r2, [r3, #24]
}
8005288: bf00 nop
800528a: 370c adds r7, #12
800528c: 46bd mov sp, r7
800528e: f85d 7b04 ldr.w r7, [sp], #4
8005292: 4770 bx lr
8005294: e000e100 .word 0xe000e100
8005298: e000ed00 .word 0xe000ed00
0800529c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
800529c: b480 push {r7}
800529e: b089 sub sp, #36 ; 0x24
80052a0: af00 add r7, sp, #0
80052a2: 60f8 str r0, [r7, #12]
80052a4: 60b9 str r1, [r7, #8]
80052a6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80052a8: 68fb ldr r3, [r7, #12]
80052aa: f003 0307 and.w r3, r3, #7
80052ae: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80052b0: 69fb ldr r3, [r7, #28]
80052b2: f1c3 0307 rsb r3, r3, #7
80052b6: 2b04 cmp r3, #4
80052b8: bf28 it cs
80052ba: 2304 movcs r3, #4
80052bc: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80052be: 69fb ldr r3, [r7, #28]
80052c0: 3304 adds r3, #4
80052c2: 2b06 cmp r3, #6
80052c4: d902 bls.n 80052cc <NVIC_EncodePriority+0x30>
80052c6: 69fb ldr r3, [r7, #28]
80052c8: 3b03 subs r3, #3
80052ca: e000 b.n 80052ce <NVIC_EncodePriority+0x32>
80052cc: 2300 movs r3, #0
80052ce: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80052d0: f04f 32ff mov.w r2, #4294967295
80052d4: 69bb ldr r3, [r7, #24]
80052d6: fa02 f303 lsl.w r3, r2, r3
80052da: 43da mvns r2, r3
80052dc: 68bb ldr r3, [r7, #8]
80052de: 401a ands r2, r3
80052e0: 697b ldr r3, [r7, #20]
80052e2: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80052e4: f04f 31ff mov.w r1, #4294967295
80052e8: 697b ldr r3, [r7, #20]
80052ea: fa01 f303 lsl.w r3, r1, r3
80052ee: 43d9 mvns r1, r3
80052f0: 687b ldr r3, [r7, #4]
80052f2: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80052f4: 4313 orrs r3, r2
);
}
80052f6: 4618 mov r0, r3
80052f8: 3724 adds r7, #36 ; 0x24
80052fa: 46bd mov sp, r7
80052fc: f85d 7b04 ldr.w r7, [sp], #4
8005300: 4770 bx lr
08005302 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8005302: b580 push {r7, lr}
8005304: b082 sub sp, #8
8005306: af00 add r7, sp, #0
8005308: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
800530a: 6878 ldr r0, [r7, #4]
800530c: f7ff ff4c bl 80051a8 <__NVIC_SetPriorityGrouping>
}
8005310: bf00 nop
8005312: 3708 adds r7, #8
8005314: 46bd mov sp, r7
8005316: bd80 pop {r7, pc}
08005318 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8005318: b580 push {r7, lr}
800531a: b086 sub sp, #24
800531c: af00 add r7, sp, #0
800531e: 4603 mov r3, r0
8005320: 60b9 str r1, [r7, #8]
8005322: 607a str r2, [r7, #4]
8005324: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8005326: 2300 movs r3, #0
8005328: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
800532a: f7ff ff61 bl 80051f0 <__NVIC_GetPriorityGrouping>
800532e: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8005330: 687a ldr r2, [r7, #4]
8005332: 68b9 ldr r1, [r7, #8]
8005334: 6978 ldr r0, [r7, #20]
8005336: f7ff ffb1 bl 800529c <NVIC_EncodePriority>
800533a: 4602 mov r2, r0
800533c: f997 300f ldrsb.w r3, [r7, #15]
8005340: 4611 mov r1, r2
8005342: 4618 mov r0, r3
8005344: f7ff ff80 bl 8005248 <__NVIC_SetPriority>
}
8005348: bf00 nop
800534a: 3718 adds r7, #24
800534c: 46bd mov sp, r7
800534e: bd80 pop {r7, pc}
08005350 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8005350: b580 push {r7, lr}
8005352: b082 sub sp, #8
8005354: af00 add r7, sp, #0
8005356: 4603 mov r3, r0
8005358: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
800535a: f997 3007 ldrsb.w r3, [r7, #7]
800535e: 4618 mov r0, r3
8005360: f7ff ff54 bl 800520c <__NVIC_EnableIRQ>
}
8005364: bf00 nop
8005366: 3708 adds r7, #8
8005368: 46bd mov sp, r7
800536a: bd80 pop {r7, pc}
0800536c <HAL_CRC_Init>:
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
800536c: b580 push {r7, lr}
800536e: b082 sub sp, #8
8005370: af00 add r7, sp, #0
8005372: 6078 str r0, [r7, #4]
/* Check the CRC handle allocation */
if (hcrc == NULL)
8005374: 687b ldr r3, [r7, #4]
8005376: 2b00 cmp r3, #0
8005378: d101 bne.n 800537e <HAL_CRC_Init+0x12>
{
return HAL_ERROR;
800537a: 2301 movs r3, #1
800537c: e054 b.n 8005428 <HAL_CRC_Init+0xbc>
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
800537e: 687b ldr r3, [r7, #4]
8005380: 7f5b ldrb r3, [r3, #29]
8005382: b2db uxtb r3, r3
8005384: 2b00 cmp r3, #0
8005386: d105 bne.n 8005394 <HAL_CRC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
8005388: 687b ldr r3, [r7, #4]
800538a: 2200 movs r2, #0
800538c: 771a strb r2, [r3, #28]
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
800538e: 6878 ldr r0, [r7, #4]
8005390: f7fe fe1c bl 8003fcc <HAL_CRC_MspInit>
}
hcrc->State = HAL_CRC_STATE_BUSY;
8005394: 687b ldr r3, [r7, #4]
8005396: 2202 movs r2, #2
8005398: 775a strb r2, [r3, #29]
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
800539a: 687b ldr r3, [r7, #4]
800539c: 791b ldrb r3, [r3, #4]
800539e: 2b00 cmp r3, #0
80053a0: d10c bne.n 80053bc <HAL_CRC_Init+0x50>
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
80053a2: 687b ldr r3, [r7, #4]
80053a4: 681b ldr r3, [r3, #0]
80053a6: 4a22 ldr r2, [pc, #136] ; (8005430 <HAL_CRC_Init+0xc4>)
80053a8: 615a str r2, [r3, #20]
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
80053aa: 687b ldr r3, [r7, #4]
80053ac: 681b ldr r3, [r3, #0]
80053ae: 689a ldr r2, [r3, #8]
80053b0: 687b ldr r3, [r7, #4]
80053b2: 681b ldr r3, [r3, #0]
80053b4: f022 0218 bic.w r2, r2, #24
80053b8: 609a str r2, [r3, #8]
80053ba: e00c b.n 80053d6 <HAL_CRC_Init+0x6a>
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
80053bc: 687b ldr r3, [r7, #4]
80053be: 6899 ldr r1, [r3, #8]
80053c0: 687b ldr r3, [r7, #4]
80053c2: 68db ldr r3, [r3, #12]
80053c4: 461a mov r2, r3
80053c6: 6878 ldr r0, [r7, #4]
80053c8: f000 f834 bl 8005434 <HAL_CRCEx_Polynomial_Set>
80053cc: 4603 mov r3, r0
80053ce: 2b00 cmp r3, #0
80053d0: d001 beq.n 80053d6 <HAL_CRC_Init+0x6a>
{
return HAL_ERROR;
80053d2: 2301 movs r3, #1
80053d4: e028 b.n 8005428 <HAL_CRC_Init+0xbc>
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
80053d6: 687b ldr r3, [r7, #4]
80053d8: 795b ldrb r3, [r3, #5]
80053da: 2b00 cmp r3, #0
80053dc: d105 bne.n 80053ea <HAL_CRC_Init+0x7e>
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
80053de: 687b ldr r3, [r7, #4]
80053e0: 681b ldr r3, [r3, #0]
80053e2: f04f 32ff mov.w r2, #4294967295
80053e6: 611a str r2, [r3, #16]
80053e8: e004 b.n 80053f4 <HAL_CRC_Init+0x88>
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
80053ea: 687b ldr r3, [r7, #4]
80053ec: 681b ldr r3, [r3, #0]
80053ee: 687a ldr r2, [r7, #4]
80053f0: 6912 ldr r2, [r2, #16]
80053f2: 611a str r2, [r3, #16]
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
80053f4: 687b ldr r3, [r7, #4]
80053f6: 681b ldr r3, [r3, #0]
80053f8: 689b ldr r3, [r3, #8]
80053fa: f023 0160 bic.w r1, r3, #96 ; 0x60
80053fe: 687b ldr r3, [r7, #4]
8005400: 695a ldr r2, [r3, #20]
8005402: 687b ldr r3, [r7, #4]
8005404: 681b ldr r3, [r3, #0]
8005406: 430a orrs r2, r1
8005408: 609a str r2, [r3, #8]
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
800540a: 687b ldr r3, [r7, #4]
800540c: 681b ldr r3, [r3, #0]
800540e: 689b ldr r3, [r3, #8]
8005410: f023 0180 bic.w r1, r3, #128 ; 0x80
8005414: 687b ldr r3, [r7, #4]
8005416: 699a ldr r2, [r3, #24]
8005418: 687b ldr r3, [r7, #4]
800541a: 681b ldr r3, [r3, #0]
800541c: 430a orrs r2, r1
800541e: 609a str r2, [r3, #8]
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
8005420: 687b ldr r3, [r7, #4]
8005422: 2201 movs r2, #1
8005424: 775a strb r2, [r3, #29]
/* Return function status */
return HAL_OK;
8005426: 2300 movs r3, #0
}
8005428: 4618 mov r0, r3
800542a: 3708 adds r7, #8
800542c: 46bd mov sp, r7
800542e: bd80 pop {r7, pc}
8005430: 04c11db7 .word 0x04c11db7
08005434 <HAL_CRCEx_Polynomial_Set>:
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
8005434: b480 push {r7}
8005436: b087 sub sp, #28
8005438: af00 add r7, sp, #0
800543a: 60f8 str r0, [r7, #12]
800543c: 60b9 str r1, [r7, #8]
800543e: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005440: 2300 movs r3, #0
8005442: 75fb strb r3, [r7, #23]
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
8005444: 231f movs r3, #31
8005446: 613b str r3, [r7, #16]
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
8005448: bf00 nop
800544a: 693b ldr r3, [r7, #16]
800544c: 1e5a subs r2, r3, #1
800544e: 613a str r2, [r7, #16]
8005450: 2b00 cmp r3, #0
8005452: d009 beq.n 8005468 <HAL_CRCEx_Polynomial_Set+0x34>
8005454: 693b ldr r3, [r7, #16]
8005456: f003 031f and.w r3, r3, #31
800545a: 68ba ldr r2, [r7, #8]
800545c: fa22 f303 lsr.w r3, r2, r3
8005460: f003 0301 and.w r3, r3, #1
8005464: 2b00 cmp r3, #0
8005466: d0f0 beq.n 800544a <HAL_CRCEx_Polynomial_Set+0x16>
{
}
switch (PolyLength)
8005468: 687b ldr r3, [r7, #4]
800546a: 2b18 cmp r3, #24
800546c: d846 bhi.n 80054fc <HAL_CRCEx_Polynomial_Set+0xc8>
800546e: a201 add r2, pc, #4 ; (adr r2, 8005474 <HAL_CRCEx_Polynomial_Set+0x40>)
8005470: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005474: 08005503 .word 0x08005503
8005478: 080054fd .word 0x080054fd
800547c: 080054fd .word 0x080054fd
8005480: 080054fd .word 0x080054fd
8005484: 080054fd .word 0x080054fd
8005488: 080054fd .word 0x080054fd
800548c: 080054fd .word 0x080054fd
8005490: 080054fd .word 0x080054fd
8005494: 080054f1 .word 0x080054f1
8005498: 080054fd .word 0x080054fd
800549c: 080054fd .word 0x080054fd
80054a0: 080054fd .word 0x080054fd
80054a4: 080054fd .word 0x080054fd
80054a8: 080054fd .word 0x080054fd
80054ac: 080054fd .word 0x080054fd
80054b0: 080054fd .word 0x080054fd
80054b4: 080054e5 .word 0x080054e5
80054b8: 080054fd .word 0x080054fd
80054bc: 080054fd .word 0x080054fd
80054c0: 080054fd .word 0x080054fd
80054c4: 080054fd .word 0x080054fd
80054c8: 080054fd .word 0x080054fd
80054cc: 080054fd .word 0x080054fd
80054d0: 080054fd .word 0x080054fd
80054d4: 080054d9 .word 0x080054d9
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
80054d8: 693b ldr r3, [r7, #16]
80054da: 2b06 cmp r3, #6
80054dc: d913 bls.n 8005506 <HAL_CRCEx_Polynomial_Set+0xd2>
{
status = HAL_ERROR;
80054de: 2301 movs r3, #1
80054e0: 75fb strb r3, [r7, #23]
}
break;
80054e2: e010 b.n 8005506 <HAL_CRCEx_Polynomial_Set+0xd2>
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
80054e4: 693b ldr r3, [r7, #16]
80054e6: 2b07 cmp r3, #7
80054e8: d90f bls.n 800550a <HAL_CRCEx_Polynomial_Set+0xd6>
{
status = HAL_ERROR;
80054ea: 2301 movs r3, #1
80054ec: 75fb strb r3, [r7, #23]
}
break;
80054ee: e00c b.n 800550a <HAL_CRCEx_Polynomial_Set+0xd6>
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
80054f0: 693b ldr r3, [r7, #16]
80054f2: 2b0f cmp r3, #15
80054f4: d90b bls.n 800550e <HAL_CRCEx_Polynomial_Set+0xda>
{
status = HAL_ERROR;
80054f6: 2301 movs r3, #1
80054f8: 75fb strb r3, [r7, #23]
}
break;
80054fa: e008 b.n 800550e <HAL_CRCEx_Polynomial_Set+0xda>
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
80054fc: 2301 movs r3, #1
80054fe: 75fb strb r3, [r7, #23]
break;
8005500: e006 b.n 8005510 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005502: bf00 nop
8005504: e004 b.n 8005510 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005506: bf00 nop
8005508: e002 b.n 8005510 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800550a: bf00 nop
800550c: e000 b.n 8005510 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800550e: bf00 nop
}
if (status == HAL_OK)
8005510: 7dfb ldrb r3, [r7, #23]
8005512: 2b00 cmp r3, #0
8005514: d10d bne.n 8005532 <HAL_CRCEx_Polynomial_Set+0xfe>
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
8005516: 68fb ldr r3, [r7, #12]
8005518: 681b ldr r3, [r3, #0]
800551a: 68ba ldr r2, [r7, #8]
800551c: 615a str r2, [r3, #20]
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
800551e: 68fb ldr r3, [r7, #12]
8005520: 681b ldr r3, [r3, #0]
8005522: 689b ldr r3, [r3, #8]
8005524: f023 0118 bic.w r1, r3, #24
8005528: 68fb ldr r3, [r7, #12]
800552a: 681b ldr r3, [r3, #0]
800552c: 687a ldr r2, [r7, #4]
800552e: 430a orrs r2, r1
8005530: 609a str r2, [r3, #8]
}
/* Return function status */
return status;
8005532: 7dfb ldrb r3, [r7, #23]
}
8005534: 4618 mov r0, r3
8005536: 371c adds r7, #28
8005538: 46bd mov sp, r7
800553a: f85d 7b04 ldr.w r7, [sp], #4
800553e: 4770 bx lr
08005540 <HAL_DAC_Init>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
{
8005540: b580 push {r7, lr}
8005542: b082 sub sp, #8
8005544: af00 add r7, sp, #0
8005546: 6078 str r0, [r7, #4]
/* Check DAC handle */
if(hdac == NULL)
8005548: 687b ldr r3, [r7, #4]
800554a: 2b00 cmp r3, #0
800554c: d101 bne.n 8005552 <HAL_DAC_Init+0x12>
{
return HAL_ERROR;
800554e: 2301 movs r3, #1
8005550: e014 b.n 800557c <HAL_DAC_Init+0x3c>
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if(hdac->State == HAL_DAC_STATE_RESET)
8005552: 687b ldr r3, [r7, #4]
8005554: 791b ldrb r3, [r3, #4]
8005556: b2db uxtb r3, r3
8005558: 2b00 cmp r3, #0
800555a: d105 bne.n 8005568 <HAL_DAC_Init+0x28>
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
800555c: 687b ldr r3, [r7, #4]
800555e: 2200 movs r2, #0
8005560: 715a strb r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
8005562: 6878 ldr r0, [r7, #4]
8005564: f7fe fd52 bl 800400c <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
8005568: 687b ldr r3, [r7, #4]
800556a: 2202 movs r2, #2
800556c: 711a strb r2, [r3, #4]
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
800556e: 687b ldr r3, [r7, #4]
8005570: 2200 movs r2, #0
8005572: 611a str r2, [r3, #16]
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
8005574: 687b ldr r3, [r7, #4]
8005576: 2201 movs r2, #1
8005578: 711a strb r2, [r3, #4]
/* Return function status */
return HAL_OK;
800557a: 2300 movs r3, #0
}
800557c: 4618 mov r0, r3
800557e: 3708 adds r7, #8
8005580: 46bd mov sp, r7
8005582: bd80 pop {r7, pc}
08005584 <HAL_DAC_IRQHandler>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
8005584: b580 push {r7, lr}
8005586: b082 sub sp, #8
8005588: af00 add r7, sp, #0
800558a: 6078 str r0, [r7, #4]
/* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
800558c: 687b ldr r3, [r7, #4]
800558e: 681b ldr r3, [r3, #0]
8005590: 6b5b ldr r3, [r3, #52] ; 0x34
8005592: f403 5300 and.w r3, r3, #8192 ; 0x2000
8005596: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800559a: d118 bne.n 80055ce <HAL_DAC_IRQHandler+0x4a>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
800559c: 687b ldr r3, [r7, #4]
800559e: 2204 movs r2, #4
80055a0: 711a strb r2, [r3, #4]
/* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
80055a2: 687b ldr r3, [r7, #4]
80055a4: 691b ldr r3, [r3, #16]
80055a6: f043 0201 orr.w r2, r3, #1
80055aa: 687b ldr r3, [r7, #4]
80055ac: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
80055ae: 687b ldr r3, [r7, #4]
80055b0: 681b ldr r3, [r3, #0]
80055b2: f44f 5200 mov.w r2, #8192 ; 0x2000
80055b6: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
80055b8: 687b ldr r3, [r7, #4]
80055ba: 681b ldr r3, [r3, #0]
80055bc: 681a ldr r2, [r3, #0]
80055be: 687b ldr r3, [r7, #4]
80055c0: 681b ldr r3, [r3, #0]
80055c2: f422 5280 bic.w r2, r2, #4096 ; 0x1000
80055c6: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
80055c8: 6878 ldr r0, [r7, #4]
80055ca: f000 f825 bl 8005618 <HAL_DAC_DMAUnderrunCallbackCh1>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
80055ce: 687b ldr r3, [r7, #4]
80055d0: 681b ldr r3, [r3, #0]
80055d2: 6b5b ldr r3, [r3, #52] ; 0x34
80055d4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80055d8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
80055dc: d118 bne.n 8005610 <HAL_DAC_IRQHandler+0x8c>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
80055de: 687b ldr r3, [r7, #4]
80055e0: 2204 movs r2, #4
80055e2: 711a strb r2, [r3, #4]
/* Set DAC error code to channel2 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
80055e4: 687b ldr r3, [r7, #4]
80055e6: 691b ldr r3, [r3, #16]
80055e8: f043 0202 orr.w r2, r3, #2
80055ec: 687b ldr r3, [r7, #4]
80055ee: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
80055f0: 687b ldr r3, [r7, #4]
80055f2: 681b ldr r3, [r3, #0]
80055f4: f04f 5200 mov.w r2, #536870912 ; 0x20000000
80055f8: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
80055fa: 687b ldr r3, [r7, #4]
80055fc: 681b ldr r3, [r3, #0]
80055fe: 681a ldr r2, [r3, #0]
8005600: 687b ldr r3, [r7, #4]
8005602: 681b ldr r3, [r3, #0]
8005604: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
8005608: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
800560a: 6878 ldr r0, [r7, #4]
800560c: f000 f85b bl 80056c6 <HAL_DACEx_DMAUnderrunCallbackCh2>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
8005610: bf00 nop
8005612: 3708 adds r7, #8
8005614: 46bd mov sp, r7
8005616: bd80 pop {r7, pc}
08005618 <HAL_DAC_DMAUnderrunCallbackCh1>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
8005618: b480 push {r7}
800561a: b083 sub sp, #12
800561c: af00 add r7, sp, #0
800561e: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
8005620: bf00 nop
8005622: 370c adds r7, #12
8005624: 46bd mov sp, r7
8005626: f85d 7b04 ldr.w r7, [sp], #4
800562a: 4770 bx lr
0800562c <HAL_DAC_ConfigChannel>:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
800562c: b480 push {r7}
800562e: b087 sub sp, #28
8005630: af00 add r7, sp, #0
8005632: 60f8 str r0, [r7, #12]
8005634: 60b9 str r1, [r7, #8]
8005636: 607a str r2, [r7, #4]
uint32_t tmpreg1 = 0, tmpreg2 = 0;
8005638: 2300 movs r3, #0
800563a: 617b str r3, [r7, #20]
800563c: 2300 movs r3, #0
800563e: 613b str r3, [r7, #16]
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
8005640: 68fb ldr r3, [r7, #12]
8005642: 795b ldrb r3, [r3, #5]
8005644: 2b01 cmp r3, #1
8005646: d101 bne.n 800564c <HAL_DAC_ConfigChannel+0x20>
8005648: 2302 movs r3, #2
800564a: e036 b.n 80056ba <HAL_DAC_ConfigChannel+0x8e>
800564c: 68fb ldr r3, [r7, #12]
800564e: 2201 movs r2, #1
8005650: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
8005652: 68fb ldr r3, [r7, #12]
8005654: 2202 movs r2, #2
8005656: 711a strb r2, [r3, #4]
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
8005658: 68fb ldr r3, [r7, #12]
800565a: 681b ldr r3, [r3, #0]
800565c: 681b ldr r3, [r3, #0]
800565e: 617b str r3, [r7, #20]
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
8005660: f640 72fe movw r2, #4094 ; 0xffe
8005664: 687b ldr r3, [r7, #4]
8005666: fa02 f303 lsl.w r3, r2, r3
800566a: 43db mvns r3, r3
800566c: 697a ldr r2, [r7, #20]
800566e: 4013 ands r3, r2
8005670: 617b str r3, [r7, #20]
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
8005672: 68bb ldr r3, [r7, #8]
8005674: 681a ldr r2, [r3, #0]
8005676: 68bb ldr r3, [r7, #8]
8005678: 685b ldr r3, [r3, #4]
800567a: 4313 orrs r3, r2
800567c: 613b str r3, [r7, #16]
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
800567e: 693a ldr r2, [r7, #16]
8005680: 687b ldr r3, [r7, #4]
8005682: fa02 f303 lsl.w r3, r2, r3
8005686: 697a ldr r2, [r7, #20]
8005688: 4313 orrs r3, r2
800568a: 617b str r3, [r7, #20]
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
800568c: 68fb ldr r3, [r7, #12]
800568e: 681b ldr r3, [r3, #0]
8005690: 697a ldr r2, [r7, #20]
8005692: 601a str r2, [r3, #0]
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
8005694: 68fb ldr r3, [r7, #12]
8005696: 681b ldr r3, [r3, #0]
8005698: 6819 ldr r1, [r3, #0]
800569a: 22c0 movs r2, #192 ; 0xc0
800569c: 687b ldr r3, [r7, #4]
800569e: fa02 f303 lsl.w r3, r2, r3
80056a2: 43da mvns r2, r3
80056a4: 68fb ldr r3, [r7, #12]
80056a6: 681b ldr r3, [r3, #0]
80056a8: 400a ands r2, r1
80056aa: 601a str r2, [r3, #0]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
80056ac: 68fb ldr r3, [r7, #12]
80056ae: 2201 movs r2, #1
80056b0: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
80056b2: 68fb ldr r3, [r7, #12]
80056b4: 2200 movs r2, #0
80056b6: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
80056b8: 2300 movs r3, #0
}
80056ba: 4618 mov r0, r3
80056bc: 371c adds r7, #28
80056be: 46bd mov sp, r7
80056c0: f85d 7b04 ldr.w r7, [sp], #4
80056c4: 4770 bx lr
080056c6 <HAL_DACEx_DMAUnderrunCallbackCh2>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
80056c6: b480 push {r7}
80056c8: b083 sub sp, #12
80056ca: af00 add r7, sp, #0
80056cc: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
80056ce: bf00 nop
80056d0: 370c adds r7, #12
80056d2: 46bd mov sp, r7
80056d4: f85d 7b04 ldr.w r7, [sp], #4
80056d8: 4770 bx lr
...
080056dc <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
80056dc: b580 push {r7, lr}
80056de: b086 sub sp, #24
80056e0: af00 add r7, sp, #0
80056e2: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
80056e4: 2300 movs r3, #0
80056e6: 617b str r3, [r7, #20]
uint32_t tickstart = HAL_GetTick();
80056e8: f7ff f956 bl 8004998 <HAL_GetTick>
80056ec: 6138 str r0, [r7, #16]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
80056ee: 687b ldr r3, [r7, #4]
80056f0: 2b00 cmp r3, #0
80056f2: d101 bne.n 80056f8 <HAL_DMA_Init+0x1c>
{
return HAL_ERROR;
80056f4: 2301 movs r3, #1
80056f6: e099 b.n 800582c <HAL_DMA_Init+0x150>
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
80056f8: 687b ldr r3, [r7, #4]
80056fa: 2200 movs r2, #0
80056fc: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8005700: 687b ldr r3, [r7, #4]
8005702: 2202 movs r2, #2
8005704: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8005708: 687b ldr r3, [r7, #4]
800570a: 681b ldr r3, [r3, #0]
800570c: 681a ldr r2, [r3, #0]
800570e: 687b ldr r3, [r7, #4]
8005710: 681b ldr r3, [r3, #0]
8005712: f022 0201 bic.w r2, r2, #1
8005716: 601a str r2, [r3, #0]
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
8005718: e00f b.n 800573a <HAL_DMA_Init+0x5e>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
800571a: f7ff f93d bl 8004998 <HAL_GetTick>
800571e: 4602 mov r2, r0
8005720: 693b ldr r3, [r7, #16]
8005722: 1ad3 subs r3, r2, r3
8005724: 2b05 cmp r3, #5
8005726: d908 bls.n 800573a <HAL_DMA_Init+0x5e>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
8005728: 687b ldr r3, [r7, #4]
800572a: 2220 movs r2, #32
800572c: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
800572e: 687b ldr r3, [r7, #4]
8005730: 2203 movs r2, #3
8005732: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_TIMEOUT;
8005736: 2303 movs r3, #3
8005738: e078 b.n 800582c <HAL_DMA_Init+0x150>
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
800573a: 687b ldr r3, [r7, #4]
800573c: 681b ldr r3, [r3, #0]
800573e: 681b ldr r3, [r3, #0]
8005740: f003 0301 and.w r3, r3, #1
8005744: 2b00 cmp r3, #0
8005746: d1e8 bne.n 800571a <HAL_DMA_Init+0x3e>
}
}
/* Get the CR register value */
tmp = hdma->Instance->CR;
8005748: 687b ldr r3, [r7, #4]
800574a: 681b ldr r3, [r3, #0]
800574c: 681b ldr r3, [r3, #0]
800574e: 617b str r3, [r7, #20]
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
8005750: 697a ldr r2, [r7, #20]
8005752: 4b38 ldr r3, [pc, #224] ; (8005834 <HAL_DMA_Init+0x158>)
8005754: 4013 ands r3, r2
8005756: 617b str r3, [r7, #20]
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
8005758: 687b ldr r3, [r7, #4]
800575a: 685a ldr r2, [r3, #4]
800575c: 687b ldr r3, [r7, #4]
800575e: 689b ldr r3, [r3, #8]
8005760: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8005762: 687b ldr r3, [r7, #4]
8005764: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Channel | hdma->Init.Direction |
8005766: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8005768: 687b ldr r3, [r7, #4]
800576a: 691b ldr r3, [r3, #16]
800576c: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800576e: 687b ldr r3, [r7, #4]
8005770: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8005772: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005774: 687b ldr r3, [r7, #4]
8005776: 699b ldr r3, [r3, #24]
8005778: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
800577a: 687b ldr r3, [r7, #4]
800577c: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800577e: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005780: 687b ldr r3, [r7, #4]
8005782: 6a1b ldr r3, [r3, #32]
8005784: 4313 orrs r3, r2
tmp |= hdma->Init.Channel | hdma->Init.Direction |
8005786: 697a ldr r2, [r7, #20]
8005788: 4313 orrs r3, r2
800578a: 617b str r3, [r7, #20]
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
800578c: 687b ldr r3, [r7, #4]
800578e: 6a5b ldr r3, [r3, #36] ; 0x24
8005790: 2b04 cmp r3, #4
8005792: d107 bne.n 80057a4 <HAL_DMA_Init+0xc8>
{
/* Get memory burst and peripheral burst */
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
8005794: 687b ldr r3, [r7, #4]
8005796: 6ada ldr r2, [r3, #44] ; 0x2c
8005798: 687b ldr r3, [r7, #4]
800579a: 6b1b ldr r3, [r3, #48] ; 0x30
800579c: 4313 orrs r3, r2
800579e: 697a ldr r2, [r7, #20]
80057a0: 4313 orrs r3, r2
80057a2: 617b str r3, [r7, #20]
}
/* Write to DMA Stream CR register */
hdma->Instance->CR = tmp;
80057a4: 687b ldr r3, [r7, #4]
80057a6: 681b ldr r3, [r3, #0]
80057a8: 697a ldr r2, [r7, #20]
80057aa: 601a str r2, [r3, #0]
/* Get the FCR register value */
tmp = hdma->Instance->FCR;
80057ac: 687b ldr r3, [r7, #4]
80057ae: 681b ldr r3, [r3, #0]
80057b0: 695b ldr r3, [r3, #20]
80057b2: 617b str r3, [r7, #20]
/* Clear Direct mode and FIFO threshold bits */
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
80057b4: 697b ldr r3, [r7, #20]
80057b6: f023 0307 bic.w r3, r3, #7
80057ba: 617b str r3, [r7, #20]
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
80057bc: 687b ldr r3, [r7, #4]
80057be: 6a5b ldr r3, [r3, #36] ; 0x24
80057c0: 697a ldr r2, [r7, #20]
80057c2: 4313 orrs r3, r2
80057c4: 617b str r3, [r7, #20]
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
80057c6: 687b ldr r3, [r7, #4]
80057c8: 6a5b ldr r3, [r3, #36] ; 0x24
80057ca: 2b04 cmp r3, #4
80057cc: d117 bne.n 80057fe <HAL_DMA_Init+0x122>
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
80057ce: 687b ldr r3, [r7, #4]
80057d0: 6a9b ldr r3, [r3, #40] ; 0x28
80057d2: 697a ldr r2, [r7, #20]
80057d4: 4313 orrs r3, r2
80057d6: 617b str r3, [r7, #20]
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
80057d8: 687b ldr r3, [r7, #4]
80057da: 6adb ldr r3, [r3, #44] ; 0x2c
80057dc: 2b00 cmp r3, #0
80057de: d00e beq.n 80057fe <HAL_DMA_Init+0x122>
{
if (DMA_CheckFifoParam(hdma) != HAL_OK)
80057e0: 6878 ldr r0, [r7, #4]
80057e2: f000 f8bd bl 8005960 <DMA_CheckFifoParam>
80057e6: 4603 mov r3, r0
80057e8: 2b00 cmp r3, #0
80057ea: d008 beq.n 80057fe <HAL_DMA_Init+0x122>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
80057ec: 687b ldr r3, [r7, #4]
80057ee: 2240 movs r2, #64 ; 0x40
80057f0: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80057f2: 687b ldr r3, [r7, #4]
80057f4: 2201 movs r2, #1
80057f6: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_ERROR;
80057fa: 2301 movs r3, #1
80057fc: e016 b.n 800582c <HAL_DMA_Init+0x150>
}
}
}
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
80057fe: 687b ldr r3, [r7, #4]
8005800: 681b ldr r3, [r3, #0]
8005802: 697a ldr r2, [r7, #20]
8005804: 615a str r2, [r3, #20]
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
8005806: 6878 ldr r0, [r7, #4]
8005808: f000 f874 bl 80058f4 <DMA_CalcBaseAndBitshift>
800580c: 4603 mov r3, r0
800580e: 60fb str r3, [r7, #12]
/* Clear all interrupt flags */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8005810: 687b ldr r3, [r7, #4]
8005812: 6ddb ldr r3, [r3, #92] ; 0x5c
8005814: 223f movs r2, #63 ; 0x3f
8005816: 409a lsls r2, r3
8005818: 68fb ldr r3, [r7, #12]
800581a: 609a str r2, [r3, #8]
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
800581c: 687b ldr r3, [r7, #4]
800581e: 2200 movs r2, #0
8005820: 655a str r2, [r3, #84] ; 0x54
/* Initialize the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8005822: 687b ldr r3, [r7, #4]
8005824: 2201 movs r2, #1
8005826: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_OK;
800582a: 2300 movs r3, #0
}
800582c: 4618 mov r0, r3
800582e: 3718 adds r7, #24
8005830: 46bd mov sp, r7
8005832: bd80 pop {r7, pc}
8005834: f010803f .word 0xf010803f
08005838 <HAL_DMA_DeInit>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
8005838: b580 push {r7, lr}
800583a: b084 sub sp, #16
800583c: af00 add r7, sp, #0
800583e: 6078 str r0, [r7, #4]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
8005840: 687b ldr r3, [r7, #4]
8005842: 2b00 cmp r3, #0
8005844: d101 bne.n 800584a <HAL_DMA_DeInit+0x12>
{
return HAL_ERROR;
8005846: 2301 movs r3, #1
8005848: e050 b.n 80058ec <HAL_DMA_DeInit+0xb4>
}
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
800584a: 687b ldr r3, [r7, #4]
800584c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8005850: b2db uxtb r3, r3
8005852: 2b02 cmp r3, #2
8005854: d101 bne.n 800585a <HAL_DMA_DeInit+0x22>
{
/* Return error status */
return HAL_BUSY;
8005856: 2302 movs r3, #2
8005858: e048 b.n 80058ec <HAL_DMA_DeInit+0xb4>
/* Check the parameters */
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
800585a: 687b ldr r3, [r7, #4]
800585c: 681b ldr r3, [r3, #0]
800585e: 681a ldr r2, [r3, #0]
8005860: 687b ldr r3, [r7, #4]
8005862: 681b ldr r3, [r3, #0]
8005864: f022 0201 bic.w r2, r2, #1
8005868: 601a str r2, [r3, #0]
/* Reset DMA Streamx control register */
hdma->Instance->CR = 0U;
800586a: 687b ldr r3, [r7, #4]
800586c: 681b ldr r3, [r3, #0]
800586e: 2200 movs r2, #0
8005870: 601a str r2, [r3, #0]
/* Reset DMA Streamx number of data to transfer register */
hdma->Instance->NDTR = 0U;
8005872: 687b ldr r3, [r7, #4]
8005874: 681b ldr r3, [r3, #0]
8005876: 2200 movs r2, #0
8005878: 605a str r2, [r3, #4]
/* Reset DMA Streamx peripheral address register */
hdma->Instance->PAR = 0U;
800587a: 687b ldr r3, [r7, #4]
800587c: 681b ldr r3, [r3, #0]
800587e: 2200 movs r2, #0
8005880: 609a str r2, [r3, #8]
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0U;
8005882: 687b ldr r3, [r7, #4]
8005884: 681b ldr r3, [r3, #0]
8005886: 2200 movs r2, #0
8005888: 60da str r2, [r3, #12]
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0U;
800588a: 687b ldr r3, [r7, #4]
800588c: 681b ldr r3, [r3, #0]
800588e: 2200 movs r2, #0
8005890: 611a str r2, [r3, #16]
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
8005892: 687b ldr r3, [r7, #4]
8005894: 681b ldr r3, [r3, #0]
8005896: 2221 movs r2, #33 ; 0x21
8005898: 615a str r2, [r3, #20]
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
800589a: 6878 ldr r0, [r7, #4]
800589c: f000 f82a bl 80058f4 <DMA_CalcBaseAndBitshift>
80058a0: 4603 mov r3, r0
80058a2: 60fb str r3, [r7, #12]
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
80058a4: 687b ldr r3, [r7, #4]
80058a6: 6ddb ldr r3, [r3, #92] ; 0x5c
80058a8: 223f movs r2, #63 ; 0x3f
80058aa: 409a lsls r2, r3
80058ac: 68fb ldr r3, [r7, #12]
80058ae: 609a str r2, [r3, #8]
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
80058b0: 687b ldr r3, [r7, #4]
80058b2: 2200 movs r2, #0
80058b4: 63da str r2, [r3, #60] ; 0x3c
hdma->XferHalfCpltCallback = NULL;
80058b6: 687b ldr r3, [r7, #4]
80058b8: 2200 movs r2, #0
80058ba: 641a str r2, [r3, #64] ; 0x40
hdma->XferM1CpltCallback = NULL;
80058bc: 687b ldr r3, [r7, #4]
80058be: 2200 movs r2, #0
80058c0: 645a str r2, [r3, #68] ; 0x44
hdma->XferM1HalfCpltCallback = NULL;
80058c2: 687b ldr r3, [r7, #4]
80058c4: 2200 movs r2, #0
80058c6: 649a str r2, [r3, #72] ; 0x48
hdma->XferErrorCallback = NULL;
80058c8: 687b ldr r3, [r7, #4]
80058ca: 2200 movs r2, #0
80058cc: 64da str r2, [r3, #76] ; 0x4c
hdma->XferAbortCallback = NULL;
80058ce: 687b ldr r3, [r7, #4]
80058d0: 2200 movs r2, #0
80058d2: 651a str r2, [r3, #80] ; 0x50
/* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80058d4: 687b ldr r3, [r7, #4]
80058d6: 2200 movs r2, #0
80058d8: 655a str r2, [r3, #84] ; 0x54
/* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
80058da: 687b ldr r3, [r7, #4]
80058dc: 2200 movs r2, #0
80058de: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Release Lock */
__HAL_UNLOCK(hdma);
80058e2: 687b ldr r3, [r7, #4]
80058e4: 2200 movs r2, #0
80058e6: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_OK;
80058ea: 2300 movs r3, #0
}
80058ec: 4618 mov r0, r3
80058ee: 3710 adds r7, #16
80058f0: 46bd mov sp, r7
80058f2: bd80 pop {r7, pc}
080058f4 <DMA_CalcBaseAndBitshift>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
80058f4: b480 push {r7}
80058f6: b085 sub sp, #20
80058f8: af00 add r7, sp, #0
80058fa: 6078 str r0, [r7, #4]
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
80058fc: 687b ldr r3, [r7, #4]
80058fe: 681b ldr r3, [r3, #0]
8005900: b2db uxtb r3, r3
8005902: 3b10 subs r3, #16
8005904: 4a13 ldr r2, [pc, #76] ; (8005954 <DMA_CalcBaseAndBitshift+0x60>)
8005906: fba2 2303 umull r2, r3, r2, r3
800590a: 091b lsrs r3, r3, #4
800590c: 60fb str r3, [r7, #12]
/* lookup table for necessary bitshift of flags within status registers */
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
hdma->StreamIndex = flagBitshiftOffset[stream_number];
800590e: 4a12 ldr r2, [pc, #72] ; (8005958 <DMA_CalcBaseAndBitshift+0x64>)
8005910: 68fb ldr r3, [r7, #12]
8005912: 4413 add r3, r2
8005914: 781b ldrb r3, [r3, #0]
8005916: 461a mov r2, r3
8005918: 687b ldr r3, [r7, #4]
800591a: 65da str r2, [r3, #92] ; 0x5c
if (stream_number > 3U)
800591c: 68fb ldr r3, [r7, #12]
800591e: 2b03 cmp r3, #3
8005920: d908 bls.n 8005934 <DMA_CalcBaseAndBitshift+0x40>
{
/* return pointer to HISR and HIFCR */
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
8005922: 687b ldr r3, [r7, #4]
8005924: 681b ldr r3, [r3, #0]
8005926: 461a mov r2, r3
8005928: 4b0c ldr r3, [pc, #48] ; (800595c <DMA_CalcBaseAndBitshift+0x68>)
800592a: 4013 ands r3, r2
800592c: 1d1a adds r2, r3, #4
800592e: 687b ldr r3, [r7, #4]
8005930: 659a str r2, [r3, #88] ; 0x58
8005932: e006 b.n 8005942 <DMA_CalcBaseAndBitshift+0x4e>
}
else
{
/* return pointer to LISR and LIFCR */
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
8005934: 687b ldr r3, [r7, #4]
8005936: 681b ldr r3, [r3, #0]
8005938: 461a mov r2, r3
800593a: 4b08 ldr r3, [pc, #32] ; (800595c <DMA_CalcBaseAndBitshift+0x68>)
800593c: 4013 ands r3, r2
800593e: 687a ldr r2, [r7, #4]
8005940: 6593 str r3, [r2, #88] ; 0x58
}
return hdma->StreamBaseAddress;
8005942: 687b ldr r3, [r7, #4]
8005944: 6d9b ldr r3, [r3, #88] ; 0x58
}
8005946: 4618 mov r0, r3
8005948: 3714 adds r7, #20
800594a: 46bd mov sp, r7
800594c: f85d 7b04 ldr.w r7, [sp], #4
8005950: 4770 bx lr
8005952: bf00 nop
8005954: aaaaaaab .word 0xaaaaaaab
8005958: 08020d40 .word 0x08020d40
800595c: fffffc00 .word 0xfffffc00
08005960 <DMA_CheckFifoParam>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
8005960: b480 push {r7}
8005962: b085 sub sp, #20
8005964: af00 add r7, sp, #0
8005966: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005968: 2300 movs r3, #0
800596a: 73fb strb r3, [r7, #15]
uint32_t tmp = hdma->Init.FIFOThreshold;
800596c: 687b ldr r3, [r7, #4]
800596e: 6a9b ldr r3, [r3, #40] ; 0x28
8005970: 60bb str r3, [r7, #8]
/* Memory Data size equal to Byte */
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
8005972: 687b ldr r3, [r7, #4]
8005974: 699b ldr r3, [r3, #24]
8005976: 2b00 cmp r3, #0
8005978: d11f bne.n 80059ba <DMA_CheckFifoParam+0x5a>
{
switch (tmp)
800597a: 68bb ldr r3, [r7, #8]
800597c: 2b03 cmp r3, #3
800597e: d855 bhi.n 8005a2c <DMA_CheckFifoParam+0xcc>
8005980: a201 add r2, pc, #4 ; (adr r2, 8005988 <DMA_CheckFifoParam+0x28>)
8005982: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005986: bf00 nop
8005988: 08005999 .word 0x08005999
800598c: 080059ab .word 0x080059ab
8005990: 08005999 .word 0x08005999
8005994: 08005a2d .word 0x08005a2d
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
8005998: 687b ldr r3, [r7, #4]
800599a: 6adb ldr r3, [r3, #44] ; 0x2c
800599c: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80059a0: 2b00 cmp r3, #0
80059a2: d045 beq.n 8005a30 <DMA_CheckFifoParam+0xd0>
{
status = HAL_ERROR;
80059a4: 2301 movs r3, #1
80059a6: 73fb strb r3, [r7, #15]
}
break;
80059a8: e042 b.n 8005a30 <DMA_CheckFifoParam+0xd0>
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
80059aa: 687b ldr r3, [r7, #4]
80059ac: 6adb ldr r3, [r3, #44] ; 0x2c
80059ae: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
80059b2: d13f bne.n 8005a34 <DMA_CheckFifoParam+0xd4>
{
status = HAL_ERROR;
80059b4: 2301 movs r3, #1
80059b6: 73fb strb r3, [r7, #15]
}
break;
80059b8: e03c b.n 8005a34 <DMA_CheckFifoParam+0xd4>
break;
}
}
/* Memory Data size equal to Half-Word */
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
80059ba: 687b ldr r3, [r7, #4]
80059bc: 699b ldr r3, [r3, #24]
80059be: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80059c2: d121 bne.n 8005a08 <DMA_CheckFifoParam+0xa8>
{
switch (tmp)
80059c4: 68bb ldr r3, [r7, #8]
80059c6: 2b03 cmp r3, #3
80059c8: d836 bhi.n 8005a38 <DMA_CheckFifoParam+0xd8>
80059ca: a201 add r2, pc, #4 ; (adr r2, 80059d0 <DMA_CheckFifoParam+0x70>)
80059cc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80059d0: 080059e1 .word 0x080059e1
80059d4: 080059e7 .word 0x080059e7
80059d8: 080059e1 .word 0x080059e1
80059dc: 080059f9 .word 0x080059f9
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
80059e0: 2301 movs r3, #1
80059e2: 73fb strb r3, [r7, #15]
break;
80059e4: e02f b.n 8005a46 <DMA_CheckFifoParam+0xe6>
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
80059e6: 687b ldr r3, [r7, #4]
80059e8: 6adb ldr r3, [r3, #44] ; 0x2c
80059ea: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80059ee: 2b00 cmp r3, #0
80059f0: d024 beq.n 8005a3c <DMA_CheckFifoParam+0xdc>
{
status = HAL_ERROR;
80059f2: 2301 movs r3, #1
80059f4: 73fb strb r3, [r7, #15]
}
break;
80059f6: e021 b.n 8005a3c <DMA_CheckFifoParam+0xdc>
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
80059f8: 687b ldr r3, [r7, #4]
80059fa: 6adb ldr r3, [r3, #44] ; 0x2c
80059fc: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
8005a00: d11e bne.n 8005a40 <DMA_CheckFifoParam+0xe0>
{
status = HAL_ERROR;
8005a02: 2301 movs r3, #1
8005a04: 73fb strb r3, [r7, #15]
}
break;
8005a06: e01b b.n 8005a40 <DMA_CheckFifoParam+0xe0>
}
/* Memory Data size equal to Word */
else
{
switch (tmp)
8005a08: 68bb ldr r3, [r7, #8]
8005a0a: 2b02 cmp r3, #2
8005a0c: d902 bls.n 8005a14 <DMA_CheckFifoParam+0xb4>
8005a0e: 2b03 cmp r3, #3
8005a10: d003 beq.n 8005a1a <DMA_CheckFifoParam+0xba>
{
status = HAL_ERROR;
}
break;
default:
break;
8005a12: e018 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
status = HAL_ERROR;
8005a14: 2301 movs r3, #1
8005a16: 73fb strb r3, [r7, #15]
break;
8005a18: e015 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
8005a1a: 687b ldr r3, [r7, #4]
8005a1c: 6adb ldr r3, [r3, #44] ; 0x2c
8005a1e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005a22: 2b00 cmp r3, #0
8005a24: d00e beq.n 8005a44 <DMA_CheckFifoParam+0xe4>
status = HAL_ERROR;
8005a26: 2301 movs r3, #1
8005a28: 73fb strb r3, [r7, #15]
break;
8005a2a: e00b b.n 8005a44 <DMA_CheckFifoParam+0xe4>
break;
8005a2c: bf00 nop
8005a2e: e00a b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a30: bf00 nop
8005a32: e008 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a34: bf00 nop
8005a36: e006 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a38: bf00 nop
8005a3a: e004 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a3c: bf00 nop
8005a3e: e002 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a40: bf00 nop
8005a42: e000 b.n 8005a46 <DMA_CheckFifoParam+0xe6>
break;
8005a44: bf00 nop
}
}
return status;
8005a46: 7bfb ldrb r3, [r7, #15]
}
8005a48: 4618 mov r0, r3
8005a4a: 3714 adds r7, #20
8005a4c: 46bd mov sp, r7
8005a4e: f85d 7b04 ldr.w r7, [sp], #4
8005a52: 4770 bx lr
08005a54 <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
8005a54: b580 push {r7, lr}
8005a56: b082 sub sp, #8
8005a58: af00 add r7, sp, #0
8005a5a: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if(hdma2d == NULL)
8005a5c: 687b ldr r3, [r7, #4]
8005a5e: 2b00 cmp r3, #0
8005a60: d101 bne.n 8005a66 <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
8005a62: 2301 movs r3, #1
8005a64: e039 b.n 8005ada <HAL_DMA2D_Init+0x86>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
8005a66: 687b ldr r3, [r7, #4]
8005a68: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8005a6c: b2db uxtb r3, r3
8005a6e: 2b00 cmp r3, #0
8005a70: d106 bne.n 8005a80 <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
8005a72: 687b ldr r3, [r7, #4]
8005a74: 2200 movs r2, #0
8005a76: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
8005a7a: 6878 ldr r0, [r7, #4]
8005a7c: f7fe fb0e bl 800409c <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005a80: 687b ldr r3, [r7, #4]
8005a82: 2202 movs r2, #2
8005a84: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
8005a88: 687b ldr r3, [r7, #4]
8005a8a: 681b ldr r3, [r3, #0]
8005a8c: 681b ldr r3, [r3, #0]
8005a8e: f423 3140 bic.w r1, r3, #196608 ; 0x30000
8005a92: 687b ldr r3, [r7, #4]
8005a94: 685a ldr r2, [r3, #4]
8005a96: 687b ldr r3, [r7, #4]
8005a98: 681b ldr r3, [r3, #0]
8005a9a: 430a orrs r2, r1
8005a9c: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
8005a9e: 687b ldr r3, [r7, #4]
8005aa0: 681b ldr r3, [r3, #0]
8005aa2: 6b5b ldr r3, [r3, #52] ; 0x34
8005aa4: f023 0107 bic.w r1, r3, #7
8005aa8: 687b ldr r3, [r7, #4]
8005aaa: 689a ldr r2, [r3, #8]
8005aac: 687b ldr r3, [r7, #4]
8005aae: 681b ldr r3, [r3, #0]
8005ab0: 430a orrs r2, r1
8005ab2: 635a str r2, [r3, #52] ; 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
8005ab4: 687b ldr r3, [r7, #4]
8005ab6: 681b ldr r3, [r3, #0]
8005ab8: 6c1a ldr r2, [r3, #64] ; 0x40
8005aba: 4b0a ldr r3, [pc, #40] ; (8005ae4 <HAL_DMA2D_Init+0x90>)
8005abc: 4013 ands r3, r2
8005abe: 687a ldr r2, [r7, #4]
8005ac0: 68d1 ldr r1, [r2, #12]
8005ac2: 687a ldr r2, [r7, #4]
8005ac4: 6812 ldr r2, [r2, #0]
8005ac6: 430b orrs r3, r1
8005ac8: 6413 str r3, [r2, #64] ; 0x40
MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
8005aca: 687b ldr r3, [r7, #4]
8005acc: 2200 movs r2, #0
8005ace: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005ad0: 687b ldr r3, [r7, #4]
8005ad2: 2201 movs r2, #1
8005ad4: f883 2039 strb.w r2, [r3, #57] ; 0x39
return HAL_OK;
8005ad8: 2300 movs r3, #0
}
8005ada: 4618 mov r0, r3
8005adc: 3708 adds r7, #8
8005ade: 46bd mov sp, r7
8005ae0: bd80 pop {r7, pc}
8005ae2: bf00 nop
8005ae4: ffffc000 .word 0xffffc000
08005ae8 <HAL_DMA2D_Start>:
* @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
8005ae8: b580 push {r7, lr}
8005aea: b086 sub sp, #24
8005aec: af02 add r7, sp, #8
8005aee: 60f8 str r0, [r7, #12]
8005af0: 60b9 str r1, [r7, #8]
8005af2: 607a str r2, [r7, #4]
8005af4: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
8005af6: 68fb ldr r3, [r7, #12]
8005af8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005afc: 2b01 cmp r3, #1
8005afe: d101 bne.n 8005b04 <HAL_DMA2D_Start+0x1c>
8005b00: 2302 movs r3, #2
8005b02: e018 b.n 8005b36 <HAL_DMA2D_Start+0x4e>
8005b04: 68fb ldr r3, [r7, #12]
8005b06: 2201 movs r2, #1
8005b08: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005b0c: 68fb ldr r3, [r7, #12]
8005b0e: 2202 movs r2, #2
8005b10: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
8005b14: 69bb ldr r3, [r7, #24]
8005b16: 9300 str r3, [sp, #0]
8005b18: 683b ldr r3, [r7, #0]
8005b1a: 687a ldr r2, [r7, #4]
8005b1c: 68b9 ldr r1, [r7, #8]
8005b1e: 68f8 ldr r0, [r7, #12]
8005b20: f000 f988 bl 8005e34 <DMA2D_SetConfig>
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
8005b24: 68fb ldr r3, [r7, #12]
8005b26: 681b ldr r3, [r3, #0]
8005b28: 681a ldr r2, [r3, #0]
8005b2a: 68fb ldr r3, [r7, #12]
8005b2c: 681b ldr r3, [r3, #0]
8005b2e: f042 0201 orr.w r2, r2, #1
8005b32: 601a str r2, [r3, #0]
return HAL_OK;
8005b34: 2300 movs r3, #0
}
8005b36: 4618 mov r0, r3
8005b38: 3710 adds r7, #16
8005b3a: 46bd mov sp, r7
8005b3c: bd80 pop {r7, pc}
08005b3e <HAL_DMA2D_PollForTransfer>:
* the configuration information for the DMA2D.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
8005b3e: b580 push {r7, lr}
8005b40: b086 sub sp, #24
8005b42: af00 add r7, sp, #0
8005b44: 6078 str r0, [r7, #4]
8005b46: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
8005b48: 2300 movs r3, #0
8005b4a: 60fb str r3, [r7, #12]
/* Polling for DMA2D transfer */
if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
8005b4c: 687b ldr r3, [r7, #4]
8005b4e: 681b ldr r3, [r3, #0]
8005b50: 681b ldr r3, [r3, #0]
8005b52: f003 0301 and.w r3, r3, #1
8005b56: 2b00 cmp r3, #0
8005b58: d056 beq.n 8005c08 <HAL_DMA2D_PollForTransfer+0xca>
{
/* Get tick */
tickstart = HAL_GetTick();
8005b5a: f7fe ff1d bl 8004998 <HAL_GetTick>
8005b5e: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
8005b60: e04b b.n 8005bfa <HAL_DMA2D_PollForTransfer+0xbc>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
8005b62: 687b ldr r3, [r7, #4]
8005b64: 681b ldr r3, [r3, #0]
8005b66: 685b ldr r3, [r3, #4]
8005b68: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
8005b6a: 68fb ldr r3, [r7, #12]
8005b6c: f003 0321 and.w r3, r3, #33 ; 0x21
8005b70: 2b00 cmp r3, #0
8005b72: d023 beq.n 8005bbc <HAL_DMA2D_PollForTransfer+0x7e>
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005b74: 68fb ldr r3, [r7, #12]
8005b76: f003 0320 and.w r3, r3, #32
8005b7a: 2b00 cmp r3, #0
8005b7c: d005 beq.n 8005b8a <HAL_DMA2D_PollForTransfer+0x4c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005b7e: 687b ldr r3, [r7, #4]
8005b80: 6bdb ldr r3, [r3, #60] ; 0x3c
8005b82: f043 0202 orr.w r2, r3, #2
8005b86: 687b ldr r3, [r7, #4]
8005b88: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005b8a: 68fb ldr r3, [r7, #12]
8005b8c: f003 0301 and.w r3, r3, #1
8005b90: 2b00 cmp r3, #0
8005b92: d005 beq.n 8005ba0 <HAL_DMA2D_PollForTransfer+0x62>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005b94: 687b ldr r3, [r7, #4]
8005b96: 6bdb ldr r3, [r3, #60] ; 0x3c
8005b98: f043 0201 orr.w r2, r3, #1
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the transfer and configuration error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005ba0: 687b ldr r3, [r7, #4]
8005ba2: 681b ldr r3, [r3, #0]
8005ba4: 2221 movs r2, #33 ; 0x21
8005ba6: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8005ba8: 687b ldr r3, [r7, #4]
8005baa: 2204 movs r2, #4
8005bac: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005bb0: 687b ldr r3, [r7, #4]
8005bb2: 2200 movs r2, #0
8005bb4: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005bb8: 2301 movs r3, #1
8005bba: e0a5 b.n 8005d08 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005bbc: 683b ldr r3, [r7, #0]
8005bbe: f1b3 3fff cmp.w r3, #4294967295
8005bc2: d01a beq.n 8005bfa <HAL_DMA2D_PollForTransfer+0xbc>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
8005bc4: f7fe fee8 bl 8004998 <HAL_GetTick>
8005bc8: 4602 mov r2, r0
8005bca: 697b ldr r3, [r7, #20]
8005bcc: 1ad3 subs r3, r2, r3
8005bce: 683a ldr r2, [r7, #0]
8005bd0: 429a cmp r2, r3
8005bd2: d302 bcc.n 8005bda <HAL_DMA2D_PollForTransfer+0x9c>
8005bd4: 683b ldr r3, [r7, #0]
8005bd6: 2b00 cmp r3, #0
8005bd8: d10f bne.n 8005bfa <HAL_DMA2D_PollForTransfer+0xbc>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005bda: 687b ldr r3, [r7, #4]
8005bdc: 6bdb ldr r3, [r3, #60] ; 0x3c
8005bde: f043 0220 orr.w r2, r3, #32
8005be2: 687b ldr r3, [r7, #4]
8005be4: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
8005be6: 687b ldr r3, [r7, #4]
8005be8: 2203 movs r2, #3
8005bea: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005bee: 687b ldr r3, [r7, #4]
8005bf0: 2200 movs r2, #0
8005bf2: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005bf6: 2303 movs r3, #3
8005bf8: e086 b.n 8005d08 <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
8005bfa: 687b ldr r3, [r7, #4]
8005bfc: 681b ldr r3, [r3, #0]
8005bfe: 685b ldr r3, [r3, #4]
8005c00: f003 0302 and.w r3, r3, #2
8005c04: 2b00 cmp r3, #0
8005c06: d0ac beq.n 8005b62 <HAL_DMA2D_PollForTransfer+0x24>
}
}
}
}
/* Polling for CLUT loading (foreground or background) */
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
8005c08: 687b ldr r3, [r7, #4]
8005c0a: 681b ldr r3, [r3, #0]
8005c0c: 69db ldr r3, [r3, #28]
8005c0e: f003 0320 and.w r3, r3, #32
8005c12: 613b str r3, [r7, #16]
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
8005c14: 687b ldr r3, [r7, #4]
8005c16: 681b ldr r3, [r3, #0]
8005c18: 6a5b ldr r3, [r3, #36] ; 0x24
8005c1a: f003 0320 and.w r3, r3, #32
8005c1e: 693a ldr r2, [r7, #16]
8005c20: 4313 orrs r3, r2
8005c22: 613b str r3, [r7, #16]
if (layer_start != 0U)
8005c24: 693b ldr r3, [r7, #16]
8005c26: 2b00 cmp r3, #0
8005c28: d061 beq.n 8005cee <HAL_DMA2D_PollForTransfer+0x1b0>
{
/* Get tick */
tickstart = HAL_GetTick();
8005c2a: f7fe feb5 bl 8004998 <HAL_GetTick>
8005c2e: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005c30: e056 b.n 8005ce0 <HAL_DMA2D_PollForTransfer+0x1a2>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
8005c32: 687b ldr r3, [r7, #4]
8005c34: 681b ldr r3, [r3, #0]
8005c36: 685b ldr r3, [r3, #4]
8005c38: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
8005c3a: 68fb ldr r3, [r7, #12]
8005c3c: f003 0329 and.w r3, r3, #41 ; 0x29
8005c40: 2b00 cmp r3, #0
8005c42: d02e beq.n 8005ca2 <HAL_DMA2D_PollForTransfer+0x164>
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
8005c44: 68fb ldr r3, [r7, #12]
8005c46: f003 0308 and.w r3, r3, #8
8005c4a: 2b00 cmp r3, #0
8005c4c: d005 beq.n 8005c5a <HAL_DMA2D_PollForTransfer+0x11c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
8005c4e: 687b ldr r3, [r7, #4]
8005c50: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c52: f043 0204 orr.w r2, r3, #4
8005c56: 687b ldr r3, [r7, #4]
8005c58: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005c5a: 68fb ldr r3, [r7, #12]
8005c5c: f003 0320 and.w r3, r3, #32
8005c60: 2b00 cmp r3, #0
8005c62: d005 beq.n 8005c70 <HAL_DMA2D_PollForTransfer+0x132>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005c64: 687b ldr r3, [r7, #4]
8005c66: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c68: f043 0202 orr.w r2, r3, #2
8005c6c: 687b ldr r3, [r7, #4]
8005c6e: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005c70: 68fb ldr r3, [r7, #12]
8005c72: f003 0301 and.w r3, r3, #1
8005c76: 2b00 cmp r3, #0
8005c78: d005 beq.n 8005c86 <HAL_DMA2D_PollForTransfer+0x148>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005c7a: 687b ldr r3, [r7, #4]
8005c7c: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c7e: f043 0201 orr.w r2, r3, #1
8005c82: 687b ldr r3, [r7, #4]
8005c84: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005c86: 687b ldr r3, [r7, #4]
8005c88: 681b ldr r3, [r3, #0]
8005c8a: 2229 movs r2, #41 ; 0x29
8005c8c: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_ERROR;
8005c8e: 687b ldr r3, [r7, #4]
8005c90: 2204 movs r2, #4
8005c92: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005c96: 687b ldr r3, [r7, #4]
8005c98: 2200 movs r2, #0
8005c9a: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005c9e: 2301 movs r3, #1
8005ca0: e032 b.n 8005d08 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005ca2: 683b ldr r3, [r7, #0]
8005ca4: f1b3 3fff cmp.w r3, #4294967295
8005ca8: d01a beq.n 8005ce0 <HAL_DMA2D_PollForTransfer+0x1a2>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
8005caa: f7fe fe75 bl 8004998 <HAL_GetTick>
8005cae: 4602 mov r2, r0
8005cb0: 697b ldr r3, [r7, #20]
8005cb2: 1ad3 subs r3, r2, r3
8005cb4: 683a ldr r2, [r7, #0]
8005cb6: 429a cmp r2, r3
8005cb8: d302 bcc.n 8005cc0 <HAL_DMA2D_PollForTransfer+0x182>
8005cba: 683b ldr r3, [r7, #0]
8005cbc: 2b00 cmp r3, #0
8005cbe: d10f bne.n 8005ce0 <HAL_DMA2D_PollForTransfer+0x1a2>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005cc0: 687b ldr r3, [r7, #4]
8005cc2: 6bdb ldr r3, [r3, #60] ; 0x3c
8005cc4: f043 0220 orr.w r2, r3, #32
8005cc8: 687b ldr r3, [r7, #4]
8005cca: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
8005ccc: 687b ldr r3, [r7, #4]
8005cce: 2203 movs r2, #3
8005cd0: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005cd4: 687b ldr r3, [r7, #4]
8005cd6: 2200 movs r2, #0
8005cd8: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005cdc: 2303 movs r3, #3
8005cde: e013 b.n 8005d08 <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005ce0: 687b ldr r3, [r7, #4]
8005ce2: 681b ldr r3, [r3, #0]
8005ce4: 685b ldr r3, [r3, #4]
8005ce6: f003 0310 and.w r3, r3, #16
8005cea: 2b00 cmp r3, #0
8005cec: d0a1 beq.n 8005c32 <HAL_DMA2D_PollForTransfer+0xf4>
}
}
}
/* Clear the transfer complete and CLUT loading flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
8005cee: 687b ldr r3, [r7, #4]
8005cf0: 681b ldr r3, [r3, #0]
8005cf2: 2212 movs r2, #18
8005cf4: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8005cf6: 687b ldr r3, [r7, #4]
8005cf8: 2201 movs r2, #1
8005cfa: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005cfe: 687b ldr r3, [r7, #4]
8005d00: 2200 movs r2, #0
8005d02: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005d06: 2300 movs r3, #0
}
8005d08: 4618 mov r0, r3
8005d0a: 3718 adds r7, #24
8005d0c: 46bd mov sp, r7
8005d0e: bd80 pop {r7, pc}
08005d10 <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8005d10: b480 push {r7}
8005d12: b087 sub sp, #28
8005d14: af00 add r7, sp, #0
8005d16: 6078 str r0, [r7, #4]
8005d18: 6039 str r1, [r7, #0]
uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
8005d1a: 687b ldr r3, [r7, #4]
8005d1c: 685b ldr r3, [r3, #4]
8005d1e: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Process locked */
__HAL_LOCK(hdma2d);
8005d22: 687b ldr r3, [r7, #4]
8005d24: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005d28: 2b01 cmp r3, #1
8005d2a: d101 bne.n 8005d30 <HAL_DMA2D_ConfigLayer+0x20>
8005d2c: 2302 movs r3, #2
8005d2e: e079 b.n 8005e24 <HAL_DMA2D_ConfigLayer+0x114>
8005d30: 687b ldr r3, [r7, #4]
8005d32: 2201 movs r2, #1
8005d34: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005d38: 687b ldr r3, [r7, #4]
8005d3a: 2202 movs r2, #2
8005d3c: f883 2039 strb.w r2, [r3, #57] ; 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
8005d40: 683b ldr r3, [r7, #0]
8005d42: 011b lsls r3, r3, #4
8005d44: 3318 adds r3, #24
8005d46: 687a ldr r2, [r7, #4]
8005d48: 4413 add r3, r2
8005d4a: 613b str r3, [r7, #16]
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
#else
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
8005d4c: 693b ldr r3, [r7, #16]
8005d4e: 685a ldr r2, [r3, #4]
8005d50: 693b ldr r3, [r7, #16]
8005d52: 689b ldr r3, [r3, #8]
8005d54: 041b lsls r3, r3, #16
8005d56: 4313 orrs r3, r2
8005d58: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
8005d5a: 4b35 ldr r3, [pc, #212] ; (8005e30 <HAL_DMA2D_ConfigLayer+0x120>)
8005d5c: 60fb str r3, [r7, #12]
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005d5e: 693b ldr r3, [r7, #16]
8005d60: 685b ldr r3, [r3, #4]
8005d62: 2b0a cmp r3, #10
8005d64: d003 beq.n 8005d6e <HAL_DMA2D_ConfigLayer+0x5e>
8005d66: 693b ldr r3, [r7, #16]
8005d68: 685b ldr r3, [r3, #4]
8005d6a: 2b09 cmp r3, #9
8005d6c: d107 bne.n 8005d7e <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
8005d6e: 693b ldr r3, [r7, #16]
8005d70: 68db ldr r3, [r3, #12]
8005d72: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005d76: 697a ldr r2, [r7, #20]
8005d78: 4313 orrs r3, r2
8005d7a: 617b str r3, [r7, #20]
8005d7c: e005 b.n 8005d8a <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8005d7e: 693b ldr r3, [r7, #16]
8005d80: 68db ldr r3, [r3, #12]
8005d82: 061b lsls r3, r3, #24
8005d84: 697a ldr r2, [r7, #20]
8005d86: 4313 orrs r3, r2
8005d88: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
8005d8a: 683b ldr r3, [r7, #0]
8005d8c: 2b00 cmp r3, #0
8005d8e: d120 bne.n 8005dd2 <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8005d90: 687b ldr r3, [r7, #4]
8005d92: 681b ldr r3, [r3, #0]
8005d94: 6a5a ldr r2, [r3, #36] ; 0x24
8005d96: 68fb ldr r3, [r7, #12]
8005d98: 43db mvns r3, r3
8005d9a: ea02 0103 and.w r1, r2, r3
8005d9e: 687b ldr r3, [r7, #4]
8005da0: 681b ldr r3, [r3, #0]
8005da2: 697a ldr r2, [r7, #20]
8005da4: 430a orrs r2, r1
8005da6: 625a str r2, [r3, #36] ; 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
8005da8: 687b ldr r3, [r7, #4]
8005daa: 681b ldr r3, [r3, #0]
8005dac: 693a ldr r2, [r7, #16]
8005dae: 6812 ldr r2, [r2, #0]
8005db0: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005db2: 693b ldr r3, [r7, #16]
8005db4: 685b ldr r3, [r3, #4]
8005db6: 2b0a cmp r3, #10
8005db8: d003 beq.n 8005dc2 <HAL_DMA2D_ConfigLayer+0xb2>
8005dba: 693b ldr r3, [r7, #16]
8005dbc: 685b ldr r3, [r3, #4]
8005dbe: 2b09 cmp r3, #9
8005dc0: d127 bne.n 8005e12 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
8005dc2: 693b ldr r3, [r7, #16]
8005dc4: 68da ldr r2, [r3, #12]
8005dc6: 687b ldr r3, [r7, #4]
8005dc8: 681b ldr r3, [r3, #0]
8005dca: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005dce: 629a str r2, [r3, #40] ; 0x28
8005dd0: e01f b.n 8005e12 <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8005dd2: 687b ldr r3, [r7, #4]
8005dd4: 681b ldr r3, [r3, #0]
8005dd6: 69da ldr r2, [r3, #28]
8005dd8: 68fb ldr r3, [r7, #12]
8005dda: 43db mvns r3, r3
8005ddc: ea02 0103 and.w r1, r2, r3
8005de0: 687b ldr r3, [r7, #4]
8005de2: 681b ldr r3, [r3, #0]
8005de4: 697a ldr r2, [r7, #20]
8005de6: 430a orrs r2, r1
8005de8: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
8005dea: 687b ldr r3, [r7, #4]
8005dec: 681b ldr r3, [r3, #0]
8005dee: 693a ldr r2, [r7, #16]
8005df0: 6812 ldr r2, [r2, #0]
8005df2: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005df4: 693b ldr r3, [r7, #16]
8005df6: 685b ldr r3, [r3, #4]
8005df8: 2b0a cmp r3, #10
8005dfa: d003 beq.n 8005e04 <HAL_DMA2D_ConfigLayer+0xf4>
8005dfc: 693b ldr r3, [r7, #16]
8005dfe: 685b ldr r3, [r3, #4]
8005e00: 2b09 cmp r3, #9
8005e02: d106 bne.n 8005e12 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
8005e04: 693b ldr r3, [r7, #16]
8005e06: 68da ldr r2, [r3, #12]
8005e08: 687b ldr r3, [r7, #4]
8005e0a: 681b ldr r3, [r3, #0]
8005e0c: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005e10: 621a str r2, [r3, #32]
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005e12: 687b ldr r3, [r7, #4]
8005e14: 2201 movs r2, #1
8005e16: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005e1a: 687b ldr r3, [r7, #4]
8005e1c: 2200 movs r2, #0
8005e1e: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005e22: 2300 movs r3, #0
}
8005e24: 4618 mov r0, r3
8005e26: 371c adds r7, #28
8005e28: 46bd mov sp, r7
8005e2a: f85d 7b04 ldr.w r7, [sp], #4
8005e2e: 4770 bx lr
8005e30: ff03000f .word 0xff03000f
08005e34 <DMA2D_SetConfig>:
* @param Width The width of data to be transferred from source to destination.
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
8005e34: b480 push {r7}
8005e36: b08b sub sp, #44 ; 0x2c
8005e38: af00 add r7, sp, #0
8005e3a: 60f8 str r0, [r7, #12]
8005e3c: 60b9 str r1, [r7, #8]
8005e3e: 607a str r2, [r7, #4]
8005e40: 603b str r3, [r7, #0]
uint32_t tmp2;
uint32_t tmp3;
uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
8005e42: 68fb ldr r3, [r7, #12]
8005e44: 681b ldr r3, [r3, #0]
8005e46: 6c5b ldr r3, [r3, #68] ; 0x44
8005e48: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
8005e4c: 683b ldr r3, [r7, #0]
8005e4e: 041a lsls r2, r3, #16
8005e50: 6b3b ldr r3, [r7, #48] ; 0x30
8005e52: 431a orrs r2, r3
8005e54: 68fb ldr r3, [r7, #12]
8005e56: 681b ldr r3, [r3, #0]
8005e58: 430a orrs r2, r1
8005e5a: 645a str r2, [r3, #68] ; 0x44
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
8005e5c: 68fb ldr r3, [r7, #12]
8005e5e: 681b ldr r3, [r3, #0]
8005e60: 687a ldr r2, [r7, #4]
8005e62: 63da str r2, [r3, #60] ; 0x3c
/* Register to memory DMA2D mode selected */
if (hdma2d->Init.Mode == DMA2D_R2M)
8005e64: 68fb ldr r3, [r7, #12]
8005e66: 685b ldr r3, [r3, #4]
8005e68: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
8005e6c: d174 bne.n 8005f58 <DMA2D_SetConfig+0x124>
{
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
8005e6e: 68bb ldr r3, [r7, #8]
8005e70: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005e74: 623b str r3, [r7, #32]
tmp2 = pdata & DMA2D_OCOLR_RED_1;
8005e76: 68bb ldr r3, [r7, #8]
8005e78: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8005e7c: 61fb str r3, [r7, #28]
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
8005e7e: 68bb ldr r3, [r7, #8]
8005e80: f403 437f and.w r3, r3, #65280 ; 0xff00
8005e84: 61bb str r3, [r7, #24]
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
8005e86: 68bb ldr r3, [r7, #8]
8005e88: b2db uxtb r3, r3
8005e8a: 617b str r3, [r7, #20]
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
8005e8c: 68fb ldr r3, [r7, #12]
8005e8e: 689b ldr r3, [r3, #8]
8005e90: 2b00 cmp r3, #0
8005e92: d108 bne.n 8005ea6 <DMA2D_SetConfig+0x72>
{
tmp = (tmp3 | tmp2 | tmp1| tmp4);
8005e94: 69ba ldr r2, [r7, #24]
8005e96: 69fb ldr r3, [r7, #28]
8005e98: 431a orrs r2, r3
8005e9a: 6a3b ldr r3, [r7, #32]
8005e9c: 4313 orrs r3, r2
8005e9e: 697a ldr r2, [r7, #20]
8005ea0: 4313 orrs r3, r2
8005ea2: 627b str r3, [r7, #36] ; 0x24
8005ea4: e053 b.n 8005f4e <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
8005ea6: 68fb ldr r3, [r7, #12]
8005ea8: 689b ldr r3, [r3, #8]
8005eaa: 2b01 cmp r3, #1
8005eac: d106 bne.n 8005ebc <DMA2D_SetConfig+0x88>
{
tmp = (tmp3 | tmp2 | tmp4);
8005eae: 69ba ldr r2, [r7, #24]
8005eb0: 69fb ldr r3, [r7, #28]
8005eb2: 4313 orrs r3, r2
8005eb4: 697a ldr r2, [r7, #20]
8005eb6: 4313 orrs r3, r2
8005eb8: 627b str r3, [r7, #36] ; 0x24
8005eba: e048 b.n 8005f4e <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
8005ebc: 68fb ldr r3, [r7, #12]
8005ebe: 689b ldr r3, [r3, #8]
8005ec0: 2b02 cmp r3, #2
8005ec2: d111 bne.n 8005ee8 <DMA2D_SetConfig+0xb4>
{
tmp2 = (tmp2 >> 19U);
8005ec4: 69fb ldr r3, [r7, #28]
8005ec6: 0cdb lsrs r3, r3, #19
8005ec8: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 10U);
8005eca: 69bb ldr r3, [r7, #24]
8005ecc: 0a9b lsrs r3, r3, #10
8005ece: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005ed0: 697b ldr r3, [r7, #20]
8005ed2: 08db lsrs r3, r3, #3
8005ed4: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
8005ed6: 69bb ldr r3, [r7, #24]
8005ed8: 015a lsls r2, r3, #5
8005eda: 69fb ldr r3, [r7, #28]
8005edc: 02db lsls r3, r3, #11
8005ede: 4313 orrs r3, r2
8005ee0: 697a ldr r2, [r7, #20]
8005ee2: 4313 orrs r3, r2
8005ee4: 627b str r3, [r7, #36] ; 0x24
8005ee6: e032 b.n 8005f4e <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
8005ee8: 68fb ldr r3, [r7, #12]
8005eea: 689b ldr r3, [r3, #8]
8005eec: 2b03 cmp r3, #3
8005eee: d117 bne.n 8005f20 <DMA2D_SetConfig+0xec>
{
tmp1 = (tmp1 >> 31U);
8005ef0: 6a3b ldr r3, [r7, #32]
8005ef2: 0fdb lsrs r3, r3, #31
8005ef4: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 19U);
8005ef6: 69fb ldr r3, [r7, #28]
8005ef8: 0cdb lsrs r3, r3, #19
8005efa: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 11U);
8005efc: 69bb ldr r3, [r7, #24]
8005efe: 0adb lsrs r3, r3, #11
8005f00: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005f02: 697b ldr r3, [r7, #20]
8005f04: 08db lsrs r3, r3, #3
8005f06: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
8005f08: 69bb ldr r3, [r7, #24]
8005f0a: 015a lsls r2, r3, #5
8005f0c: 69fb ldr r3, [r7, #28]
8005f0e: 029b lsls r3, r3, #10
8005f10: 431a orrs r2, r3
8005f12: 6a3b ldr r3, [r7, #32]
8005f14: 03db lsls r3, r3, #15
8005f16: 4313 orrs r3, r2
8005f18: 697a ldr r2, [r7, #20]
8005f1a: 4313 orrs r3, r2
8005f1c: 627b str r3, [r7, #36] ; 0x24
8005f1e: e016 b.n 8005f4e <DMA2D_SetConfig+0x11a>
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
tmp1 = (tmp1 >> 28U);
8005f20: 6a3b ldr r3, [r7, #32]
8005f22: 0f1b lsrs r3, r3, #28
8005f24: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 20U);
8005f26: 69fb ldr r3, [r7, #28]
8005f28: 0d1b lsrs r3, r3, #20
8005f2a: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 12U);
8005f2c: 69bb ldr r3, [r7, #24]
8005f2e: 0b1b lsrs r3, r3, #12
8005f30: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 4U );
8005f32: 697b ldr r3, [r7, #20]
8005f34: 091b lsrs r3, r3, #4
8005f36: 617b str r3, [r7, #20]
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
8005f38: 69bb ldr r3, [r7, #24]
8005f3a: 011a lsls r2, r3, #4
8005f3c: 69fb ldr r3, [r7, #28]
8005f3e: 021b lsls r3, r3, #8
8005f40: 431a orrs r2, r3
8005f42: 6a3b ldr r3, [r7, #32]
8005f44: 031b lsls r3, r3, #12
8005f46: 4313 orrs r3, r2
8005f48: 697a ldr r2, [r7, #20]
8005f4a: 4313 orrs r3, r2
8005f4c: 627b str r3, [r7, #36] ; 0x24
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
8005f4e: 68fb ldr r3, [r7, #12]
8005f50: 681b ldr r3, [r3, #0]
8005f52: 6a7a ldr r2, [r7, #36] ; 0x24
8005f54: 639a str r2, [r3, #56] ; 0x38
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
}
}
8005f56: e003 b.n 8005f60 <DMA2D_SetConfig+0x12c>
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
8005f58: 68fb ldr r3, [r7, #12]
8005f5a: 681b ldr r3, [r3, #0]
8005f5c: 68ba ldr r2, [r7, #8]
8005f5e: 60da str r2, [r3, #12]
}
8005f60: bf00 nop
8005f62: 372c adds r7, #44 ; 0x2c
8005f64: 46bd mov sp, r7
8005f66: f85d 7b04 ldr.w r7, [sp], #4
8005f6a: 4770 bx lr
08005f6c <HAL_ETH_Init>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
8005f6c: b580 push {r7, lr}
8005f6e: b088 sub sp, #32
8005f70: af00 add r7, sp, #0
8005f72: 6078 str r0, [r7, #4]
uint32_t tempreg = 0, phyreg = 0;
8005f74: 2300 movs r3, #0
8005f76: 61fb str r3, [r7, #28]
8005f78: 2300 movs r3, #0
8005f7a: 60fb str r3, [r7, #12]
uint32_t hclk = 60000000;
8005f7c: 4ba9 ldr r3, [pc, #676] ; (8006224 <HAL_ETH_Init+0x2b8>)
8005f7e: 61bb str r3, [r7, #24]
uint32_t tickstart = 0;
8005f80: 2300 movs r3, #0
8005f82: 617b str r3, [r7, #20]
uint32_t err = ETH_SUCCESS;
8005f84: 2300 movs r3, #0
8005f86: 613b str r3, [r7, #16]
/* Check the ETH peripheral state */
if(heth == NULL)
8005f88: 687b ldr r3, [r7, #4]
8005f8a: 2b00 cmp r3, #0
8005f8c: d101 bne.n 8005f92 <HAL_ETH_Init+0x26>
{
return HAL_ERROR;
8005f8e: 2301 movs r3, #1
8005f90: e183 b.n 800629a <HAL_ETH_Init+0x32e>
assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
if(heth->State == HAL_ETH_STATE_RESET)
8005f92: 687b ldr r3, [r7, #4]
8005f94: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8005f98: b2db uxtb r3, r3
8005f9a: 2b00 cmp r3, #0
8005f9c: d106 bne.n 8005fac <HAL_ETH_Init+0x40>
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
8005f9e: 687b ldr r3, [r7, #4]
8005fa0: 2200 movs r2, #0
8005fa2: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
8005fa6: 6878 ldr r0, [r7, #4]
8005fa8: f005 f8e2 bl 800b170 <HAL_ETH_MspInit>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8005fac: 4b9e ldr r3, [pc, #632] ; (8006228 <HAL_ETH_Init+0x2bc>)
8005fae: 6c5b ldr r3, [r3, #68] ; 0x44
8005fb0: 4a9d ldr r2, [pc, #628] ; (8006228 <HAL_ETH_Init+0x2bc>)
8005fb2: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8005fb6: 6453 str r3, [r2, #68] ; 0x44
8005fb8: 4b9b ldr r3, [pc, #620] ; (8006228 <HAL_ETH_Init+0x2bc>)
8005fba: 6c5b ldr r3, [r3, #68] ; 0x44
8005fbc: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005fc0: 60bb str r3, [r7, #8]
8005fc2: 68bb ldr r3, [r7, #8]
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
8005fc4: 4b99 ldr r3, [pc, #612] ; (800622c <HAL_ETH_Init+0x2c0>)
8005fc6: 685b ldr r3, [r3, #4]
8005fc8: 4a98 ldr r2, [pc, #608] ; (800622c <HAL_ETH_Init+0x2c0>)
8005fca: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8005fce: 6053 str r3, [r2, #4]
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
8005fd0: 4b96 ldr r3, [pc, #600] ; (800622c <HAL_ETH_Init+0x2c0>)
8005fd2: 685a ldr r2, [r3, #4]
8005fd4: 687b ldr r3, [r7, #4]
8005fd6: 6a1b ldr r3, [r3, #32]
8005fd8: 4994 ldr r1, [pc, #592] ; (800622c <HAL_ETH_Init+0x2c0>)
8005fda: 4313 orrs r3, r2
8005fdc: 604b str r3, [r1, #4]
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
8005fde: 687b ldr r3, [r7, #4]
8005fe0: 681b ldr r3, [r3, #0]
8005fe2: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005fe6: 681a ldr r2, [r3, #0]
8005fe8: 687b ldr r3, [r7, #4]
8005fea: 681b ldr r3, [r3, #0]
8005fec: f042 0201 orr.w r2, r2, #1
8005ff0: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005ff4: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8005ff6: f7fe fccf bl 8004998 <HAL_GetTick>
8005ffa: 6178 str r0, [r7, #20]
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
8005ffc: e011 b.n 8006022 <HAL_ETH_Init+0xb6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
8005ffe: f7fe fccb bl 8004998 <HAL_GetTick>
8006002: 4602 mov r2, r0
8006004: 697b ldr r3, [r7, #20]
8006006: 1ad3 subs r3, r2, r3
8006008: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
800600c: d909 bls.n 8006022 <HAL_ETH_Init+0xb6>
{
heth->State= HAL_ETH_STATE_TIMEOUT;
800600e: 687b ldr r3, [r7, #4]
8006010: 2203 movs r2, #3
8006012: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006016: 687b ldr r3, [r7, #4]
8006018: 2200 movs r2, #0
800601a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
800601e: 2303 movs r3, #3
8006020: e13b b.n 800629a <HAL_ETH_Init+0x32e>
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
8006022: 687b ldr r3, [r7, #4]
8006024: 681b ldr r3, [r3, #0]
8006026: f503 5380 add.w r3, r3, #4096 ; 0x1000
800602a: 681b ldr r3, [r3, #0]
800602c: f003 0301 and.w r3, r3, #1
8006030: 2b00 cmp r3, #0
8006032: d1e4 bne.n 8005ffe <HAL_ETH_Init+0x92>
}
}
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
tempreg = (heth->Instance)->MACMIIAR;
8006034: 687b ldr r3, [r7, #4]
8006036: 681b ldr r3, [r3, #0]
8006038: 691b ldr r3, [r3, #16]
800603a: 61fb str r3, [r7, #28]
/* Clear CSR Clock Range CR[2:0] bits */
tempreg &= ETH_MACMIIAR_CR_MASK;
800603c: 69fb ldr r3, [r7, #28]
800603e: f023 031c bic.w r3, r3, #28
8006042: 61fb str r3, [r7, #28]
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
8006044: f003 f854 bl 80090f0 <HAL_RCC_GetHCLKFreq>
8006048: 61b8 str r0, [r7, #24]
/* Set CR bits depending on hclk value */
if((hclk >= 20000000)&&(hclk < 35000000))
800604a: 69bb ldr r3, [r7, #24]
800604c: 4a78 ldr r2, [pc, #480] ; (8006230 <HAL_ETH_Init+0x2c4>)
800604e: 4293 cmp r3, r2
8006050: d908 bls.n 8006064 <HAL_ETH_Init+0xf8>
8006052: 69bb ldr r3, [r7, #24]
8006054: 4a77 ldr r2, [pc, #476] ; (8006234 <HAL_ETH_Init+0x2c8>)
8006056: 4293 cmp r3, r2
8006058: d804 bhi.n 8006064 <HAL_ETH_Init+0xf8>
{
/* CSR Clock Range between 20-35 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
800605a: 69fb ldr r3, [r7, #28]
800605c: f043 0308 orr.w r3, r3, #8
8006060: 61fb str r3, [r7, #28]
8006062: e027 b.n 80060b4 <HAL_ETH_Init+0x148>
}
else if((hclk >= 35000000)&&(hclk < 60000000))
8006064: 69bb ldr r3, [r7, #24]
8006066: 4a73 ldr r2, [pc, #460] ; (8006234 <HAL_ETH_Init+0x2c8>)
8006068: 4293 cmp r3, r2
800606a: d908 bls.n 800607e <HAL_ETH_Init+0x112>
800606c: 69bb ldr r3, [r7, #24]
800606e: 4a72 ldr r2, [pc, #456] ; (8006238 <HAL_ETH_Init+0x2cc>)
8006070: 4293 cmp r3, r2
8006072: d804 bhi.n 800607e <HAL_ETH_Init+0x112>
{
/* CSR Clock Range between 35-60 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
8006074: 69fb ldr r3, [r7, #28]
8006076: f043 030c orr.w r3, r3, #12
800607a: 61fb str r3, [r7, #28]
800607c: e01a b.n 80060b4 <HAL_ETH_Init+0x148>
}
else if((hclk >= 60000000)&&(hclk < 100000000))
800607e: 69bb ldr r3, [r7, #24]
8006080: 4a6d ldr r2, [pc, #436] ; (8006238 <HAL_ETH_Init+0x2cc>)
8006082: 4293 cmp r3, r2
8006084: d903 bls.n 800608e <HAL_ETH_Init+0x122>
8006086: 69bb ldr r3, [r7, #24]
8006088: 4a6c ldr r2, [pc, #432] ; (800623c <HAL_ETH_Init+0x2d0>)
800608a: 4293 cmp r3, r2
800608c: d911 bls.n 80060b2 <HAL_ETH_Init+0x146>
{
/* CSR Clock Range between 60-100 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if((hclk >= 100000000)&&(hclk < 150000000))
800608e: 69bb ldr r3, [r7, #24]
8006090: 4a6a ldr r2, [pc, #424] ; (800623c <HAL_ETH_Init+0x2d0>)
8006092: 4293 cmp r3, r2
8006094: d908 bls.n 80060a8 <HAL_ETH_Init+0x13c>
8006096: 69bb ldr r3, [r7, #24]
8006098: 4a69 ldr r2, [pc, #420] ; (8006240 <HAL_ETH_Init+0x2d4>)
800609a: 4293 cmp r3, r2
800609c: d804 bhi.n 80060a8 <HAL_ETH_Init+0x13c>
{
/* CSR Clock Range between 100-150 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
800609e: 69fb ldr r3, [r7, #28]
80060a0: f043 0304 orr.w r3, r3, #4
80060a4: 61fb str r3, [r7, #28]
80060a6: e005 b.n 80060b4 <HAL_ETH_Init+0x148>
}
else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
{
/* CSR Clock Range between 150-216 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
80060a8: 69fb ldr r3, [r7, #28]
80060aa: f043 0310 orr.w r3, r3, #16
80060ae: 61fb str r3, [r7, #28]
80060b0: e000 b.n 80060b4 <HAL_ETH_Init+0x148>
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
80060b2: bf00 nop
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
(heth->Instance)->MACMIIAR = (uint32_t)tempreg;
80060b4: 687b ldr r3, [r7, #4]
80060b6: 681b ldr r3, [r3, #0]
80060b8: 69fa ldr r2, [r7, #28]
80060ba: 611a str r2, [r3, #16]
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
80060bc: f44f 4200 mov.w r2, #32768 ; 0x8000
80060c0: 2100 movs r1, #0
80060c2: 6878 ldr r0, [r7, #4]
80060c4: f000 fc19 bl 80068fa <HAL_ETH_WritePHYRegister>
80060c8: 4603 mov r3, r0
80060ca: 2b00 cmp r3, #0
80060cc: d00b beq.n 80060e6 <HAL_ETH_Init+0x17a>
{
/* In case of write timeout */
err = ETH_ERROR;
80060ce: 2301 movs r3, #1
80060d0: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80060d2: 6939 ldr r1, [r7, #16]
80060d4: 6878 ldr r0, [r7, #4]
80060d6: f000 fdcf bl 8006c78 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
80060da: 687b ldr r3, [r7, #4]
80060dc: 2201 movs r2, #1
80060de: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
80060e2: 2301 movs r3, #1
80060e4: e0d9 b.n 800629a <HAL_ETH_Init+0x32e>
}
/* Delay to assure PHY reset */
HAL_Delay(PHY_RESET_DELAY);
80060e6: 20ff movs r0, #255 ; 0xff
80060e8: f7fe fc62 bl 80049b0 <HAL_Delay>
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
80060ec: 687b ldr r3, [r7, #4]
80060ee: 685b ldr r3, [r3, #4]
80060f0: 2b00 cmp r3, #0
80060f2: f000 80a7 beq.w 8006244 <HAL_ETH_Init+0x2d8>
{
/* Get tick */
tickstart = HAL_GetTick();
80060f6: f7fe fc4f bl 8004998 <HAL_GetTick>
80060fa: 6178 str r0, [r7, #20]
/* We wait for linked status */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
80060fc: f107 030c add.w r3, r7, #12
8006100: 461a mov r2, r3
8006102: 2101 movs r1, #1
8006104: 6878 ldr r0, [r7, #4]
8006106: f000 fb90 bl 800682a <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
800610a: f7fe fc45 bl 8004998 <HAL_GetTick>
800610e: 4602 mov r2, r0
8006110: 697b ldr r3, [r7, #20]
8006112: 1ad3 subs r3, r2, r3
8006114: f241 3288 movw r2, #5000 ; 0x1388
8006118: 4293 cmp r3, r2
800611a: d90f bls.n 800613c <HAL_ETH_Init+0x1d0>
{
/* In case of write timeout */
err = ETH_ERROR;
800611c: 2301 movs r3, #1
800611e: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006120: 6939 ldr r1, [r7, #16]
8006122: 6878 ldr r0, [r7, #4]
8006124: f000 fda8 bl 8006c78 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
8006128: 687b ldr r3, [r7, #4]
800612a: 2201 movs r2, #1
800612c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006130: 687b ldr r3, [r7, #4]
8006132: 2200 movs r2, #0
8006134: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
8006138: 2303 movs r3, #3
800613a: e0ae b.n 800629a <HAL_ETH_Init+0x32e>
}
} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
800613c: 68fb ldr r3, [r7, #12]
800613e: f003 0304 and.w r3, r3, #4
8006142: 2b00 cmp r3, #0
8006144: d0da beq.n 80060fc <HAL_ETH_Init+0x190>
/* Enable Auto-Negotiation */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
8006146: f44f 5280 mov.w r2, #4096 ; 0x1000
800614a: 2100 movs r1, #0
800614c: 6878 ldr r0, [r7, #4]
800614e: f000 fbd4 bl 80068fa <HAL_ETH_WritePHYRegister>
8006152: 4603 mov r3, r0
8006154: 2b00 cmp r3, #0
8006156: d00b beq.n 8006170 <HAL_ETH_Init+0x204>
{
/* In case of write timeout */
err = ETH_ERROR;
8006158: 2301 movs r3, #1
800615a: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
800615c: 6939 ldr r1, [r7, #16]
800615e: 6878 ldr r0, [r7, #4]
8006160: f000 fd8a bl 8006c78 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
8006164: 687b ldr r3, [r7, #4]
8006166: 2201 movs r2, #1
8006168: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
800616c: 2301 movs r3, #1
800616e: e094 b.n 800629a <HAL_ETH_Init+0x32e>
}
/* Get tick */
tickstart = HAL_GetTick();
8006170: f7fe fc12 bl 8004998 <HAL_GetTick>
8006174: 6178 str r0, [r7, #20]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
8006176: f107 030c add.w r3, r7, #12
800617a: 461a mov r2, r3
800617c: 2101 movs r1, #1
800617e: 6878 ldr r0, [r7, #4]
8006180: f000 fb53 bl 800682a <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
8006184: f7fe fc08 bl 8004998 <HAL_GetTick>
8006188: 4602 mov r2, r0
800618a: 697b ldr r3, [r7, #20]
800618c: 1ad3 subs r3, r2, r3
800618e: f241 3288 movw r2, #5000 ; 0x1388
8006192: 4293 cmp r3, r2
8006194: d90f bls.n 80061b6 <HAL_ETH_Init+0x24a>
{
/* In case of write timeout */
err = ETH_ERROR;
8006196: 2301 movs r3, #1
8006198: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
800619a: 6939 ldr r1, [r7, #16]
800619c: 6878 ldr r0, [r7, #4]
800619e: f000 fd6b bl 8006c78 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
80061a2: 687b ldr r3, [r7, #4]
80061a4: 2201 movs r2, #1
80061a6: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80061aa: 687b ldr r3, [r7, #4]
80061ac: 2200 movs r2, #0
80061ae: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
80061b2: 2303 movs r3, #3
80061b4: e071 b.n 800629a <HAL_ETH_Init+0x32e>
}
} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
80061b6: 68fb ldr r3, [r7, #12]
80061b8: f003 0320 and.w r3, r3, #32
80061bc: 2b00 cmp r3, #0
80061be: d0da beq.n 8006176 <HAL_ETH_Init+0x20a>
/* Read the result of the auto-negotiation */
if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
80061c0: f107 030c add.w r3, r7, #12
80061c4: 461a mov r2, r3
80061c6: 211f movs r1, #31
80061c8: 6878 ldr r0, [r7, #4]
80061ca: f000 fb2e bl 800682a <HAL_ETH_ReadPHYRegister>
80061ce: 4603 mov r3, r0
80061d0: 2b00 cmp r3, #0
80061d2: d00b beq.n 80061ec <HAL_ETH_Init+0x280>
{
/* In case of write timeout */
err = ETH_ERROR;
80061d4: 2301 movs r3, #1
80061d6: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80061d8: 6939 ldr r1, [r7, #16]
80061da: 6878 ldr r0, [r7, #4]
80061dc: f000 fd4c bl 8006c78 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
80061e0: 687b ldr r3, [r7, #4]
80061e2: 2201 movs r2, #1
80061e4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
80061e8: 2301 movs r3, #1
80061ea: e056 b.n 800629a <HAL_ETH_Init+0x32e>
}
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
80061ec: 68fb ldr r3, [r7, #12]
80061ee: f003 0310 and.w r3, r3, #16
80061f2: 2b00 cmp r3, #0
80061f4: d004 beq.n 8006200 <HAL_ETH_Init+0x294>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
80061f6: 687b ldr r3, [r7, #4]
80061f8: f44f 6200 mov.w r2, #2048 ; 0x800
80061fc: 60da str r2, [r3, #12]
80061fe: e002 b.n 8006206 <HAL_ETH_Init+0x29a>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
8006200: 687b ldr r3, [r7, #4]
8006202: 2200 movs r2, #0
8006204: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
8006206: 68fb ldr r3, [r7, #12]
8006208: f003 0304 and.w r3, r3, #4
800620c: 2b00 cmp r3, #0
800620e: d003 beq.n 8006218 <HAL_ETH_Init+0x2ac>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_10M;
8006210: 687b ldr r3, [r7, #4]
8006212: 2200 movs r2, #0
8006214: 609a str r2, [r3, #8]
8006216: e037 b.n 8006288 <HAL_ETH_Init+0x31c>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_100M;
8006218: 687b ldr r3, [r7, #4]
800621a: f44f 4280 mov.w r2, #16384 ; 0x4000
800621e: 609a str r2, [r3, #8]
8006220: e032 b.n 8006288 <HAL_ETH_Init+0x31c>
8006222: bf00 nop
8006224: 03938700 .word 0x03938700
8006228: 40023800 .word 0x40023800
800622c: 40013800 .word 0x40013800
8006230: 01312cff .word 0x01312cff
8006234: 02160ebf .word 0x02160ebf
8006238: 039386ff .word 0x039386ff
800623c: 05f5e0ff .word 0x05f5e0ff
8006240: 08f0d17f .word 0x08f0d17f
/* Check parameters */
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
8006244: 687b ldr r3, [r7, #4]
8006246: 68db ldr r3, [r3, #12]
8006248: 08db lsrs r3, r3, #3
800624a: b29a uxth r2, r3
(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
800624c: 687b ldr r3, [r7, #4]
800624e: 689b ldr r3, [r3, #8]
8006250: 085b lsrs r3, r3, #1
8006252: b29b uxth r3, r3
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
8006254: 4313 orrs r3, r2
8006256: b29b uxth r3, r3
8006258: 461a mov r2, r3
800625a: 2100 movs r1, #0
800625c: 6878 ldr r0, [r7, #4]
800625e: f000 fb4c bl 80068fa <HAL_ETH_WritePHYRegister>
8006262: 4603 mov r3, r0
8006264: 2b00 cmp r3, #0
8006266: d00b beq.n 8006280 <HAL_ETH_Init+0x314>
{
/* In case of write timeout */
err = ETH_ERROR;
8006268: 2301 movs r3, #1
800626a: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
800626c: 6939 ldr r1, [r7, #16]
800626e: 6878 ldr r0, [r7, #4]
8006270: f000 fd02 bl 8006c78 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
8006274: 687b ldr r3, [r7, #4]
8006276: 2201 movs r2, #1
8006278: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
800627c: 2301 movs r3, #1
800627e: e00c b.n 800629a <HAL_ETH_Init+0x32e>
}
/* Delay to assure PHY configuration */
HAL_Delay(PHY_CONFIG_DELAY);
8006280: f640 70ff movw r0, #4095 ; 0xfff
8006284: f7fe fb94 bl 80049b0 <HAL_Delay>
}
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006288: 6939 ldr r1, [r7, #16]
800628a: 6878 ldr r0, [r7, #4]
800628c: f000 fcf4 bl 8006c78 <ETH_MACDMAConfig>
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006290: 687b ldr r3, [r7, #4]
8006292: 2201 movs r2, #1
8006294: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
8006298: 2300 movs r3, #0
}
800629a: 4618 mov r0, r3
800629c: 3720 adds r7, #32
800629e: 46bd mov sp, r7
80062a0: bd80 pop {r7, pc}
80062a2: bf00 nop
080062a4 <HAL_ETH_DMATxDescListInit>:
* @param TxBuff Pointer to the first TxBuffer list
* @param TxBuffCount Number of the used Tx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
{
80062a4: b480 push {r7}
80062a6: b087 sub sp, #28
80062a8: af00 add r7, sp, #0
80062aa: 60f8 str r0, [r7, #12]
80062ac: 60b9 str r1, [r7, #8]
80062ae: 607a str r2, [r7, #4]
80062b0: 603b str r3, [r7, #0]
uint32_t i = 0;
80062b2: 2300 movs r3, #0
80062b4: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *dmatxdesc;
/* Process Locked */
__HAL_LOCK(heth);
80062b6: 68fb ldr r3, [r7, #12]
80062b8: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80062bc: 2b01 cmp r3, #1
80062be: d101 bne.n 80062c4 <HAL_ETH_DMATxDescListInit+0x20>
80062c0: 2302 movs r3, #2
80062c2: e052 b.n 800636a <HAL_ETH_DMATxDescListInit+0xc6>
80062c4: 68fb ldr r3, [r7, #12]
80062c6: 2201 movs r2, #1
80062c8: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80062cc: 68fb ldr r3, [r7, #12]
80062ce: 2202 movs r2, #2
80062d0: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
heth->TxDesc = DMATxDescTab;
80062d4: 68fb ldr r3, [r7, #12]
80062d6: 68ba ldr r2, [r7, #8]
80062d8: 62da str r2, [r3, #44] ; 0x2c
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
80062da: 2300 movs r3, #0
80062dc: 617b str r3, [r7, #20]
80062de: e030 b.n 8006342 <HAL_ETH_DMATxDescListInit+0x9e>
{
/* Get the pointer on the ith member of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
80062e0: 697b ldr r3, [r7, #20]
80062e2: 015b lsls r3, r3, #5
80062e4: 68ba ldr r2, [r7, #8]
80062e6: 4413 add r3, r2
80062e8: 613b str r3, [r7, #16]
/* Set Second Address Chained bit */
dmatxdesc->Status = ETH_DMATXDESC_TCH;
80062ea: 693b ldr r3, [r7, #16]
80062ec: f44f 1280 mov.w r2, #1048576 ; 0x100000
80062f0: 601a str r2, [r3, #0]
/* Set Buffer1 address pointer */
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
80062f2: 697b ldr r3, [r7, #20]
80062f4: f240 52f4 movw r2, #1524 ; 0x5f4
80062f8: fb02 f303 mul.w r3, r2, r3
80062fc: 687a ldr r2, [r7, #4]
80062fe: 4413 add r3, r2
8006300: 461a mov r2, r3
8006302: 693b ldr r3, [r7, #16]
8006304: 609a str r2, [r3, #8]
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
8006306: 68fb ldr r3, [r7, #12]
8006308: 69db ldr r3, [r3, #28]
800630a: 2b00 cmp r3, #0
800630c: d105 bne.n 800631a <HAL_ETH_DMATxDescListInit+0x76>
{
/* Set the DMA Tx descriptors checksum insertion */
dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
800630e: 693b ldr r3, [r7, #16]
8006310: 681b ldr r3, [r3, #0]
8006312: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000
8006316: 693b ldr r3, [r7, #16]
8006318: 601a str r2, [r3, #0]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (TxBuffCount-1))
800631a: 683b ldr r3, [r7, #0]
800631c: 3b01 subs r3, #1
800631e: 697a ldr r2, [r7, #20]
8006320: 429a cmp r2, r3
8006322: d208 bcs.n 8006336 <HAL_ETH_DMATxDescListInit+0x92>
{
/* Set next descriptor address register with next descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
8006324: 697b ldr r3, [r7, #20]
8006326: 3301 adds r3, #1
8006328: 015b lsls r3, r3, #5
800632a: 68ba ldr r2, [r7, #8]
800632c: 4413 add r3, r2
800632e: 461a mov r2, r3
8006330: 693b ldr r3, [r7, #16]
8006332: 60da str r2, [r3, #12]
8006334: e002 b.n 800633c <HAL_ETH_DMATxDescListInit+0x98>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
8006336: 68ba ldr r2, [r7, #8]
8006338: 693b ldr r3, [r7, #16]
800633a: 60da str r2, [r3, #12]
for(i=0; i < TxBuffCount; i++)
800633c: 697b ldr r3, [r7, #20]
800633e: 3301 adds r3, #1
8006340: 617b str r3, [r7, #20]
8006342: 697a ldr r2, [r7, #20]
8006344: 683b ldr r3, [r7, #0]
8006346: 429a cmp r2, r3
8006348: d3ca bcc.n 80062e0 <HAL_ETH_DMATxDescListInit+0x3c>
}
}
/* Set Transmit Descriptor List Address Register */
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
800634a: 68fb ldr r3, [r7, #12]
800634c: 6819 ldr r1, [r3, #0]
800634e: 68ba ldr r2, [r7, #8]
8006350: f241 0310 movw r3, #4112 ; 0x1010
8006354: 440b add r3, r1
8006356: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006358: 68fb ldr r3, [r7, #12]
800635a: 2201 movs r2, #1
800635c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006360: 68fb ldr r3, [r7, #12]
8006362: 2200 movs r2, #0
8006364: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006368: 2300 movs r3, #0
}
800636a: 4618 mov r0, r3
800636c: 371c adds r7, #28
800636e: 46bd mov sp, r7
8006370: f85d 7b04 ldr.w r7, [sp], #4
8006374: 4770 bx lr
08006376 <HAL_ETH_DMARxDescListInit>:
* @param RxBuff Pointer to the first RxBuffer list
* @param RxBuffCount Number of the used Rx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
{
8006376: b480 push {r7}
8006378: b087 sub sp, #28
800637a: af00 add r7, sp, #0
800637c: 60f8 str r0, [r7, #12]
800637e: 60b9 str r1, [r7, #8]
8006380: 607a str r2, [r7, #4]
8006382: 603b str r3, [r7, #0]
uint32_t i = 0;
8006384: 2300 movs r3, #0
8006386: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *DMARxDesc;
/* Process Locked */
__HAL_LOCK(heth);
8006388: 68fb ldr r3, [r7, #12]
800638a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800638e: 2b01 cmp r3, #1
8006390: d101 bne.n 8006396 <HAL_ETH_DMARxDescListInit+0x20>
8006392: 2302 movs r3, #2
8006394: e056 b.n 8006444 <HAL_ETH_DMARxDescListInit+0xce>
8006396: 68fb ldr r3, [r7, #12]
8006398: 2201 movs r2, #1
800639a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
800639e: 68fb ldr r3, [r7, #12]
80063a0: 2202 movs r2, #2
80063a2: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
heth->RxDesc = DMARxDescTab;
80063a6: 68fb ldr r3, [r7, #12]
80063a8: 68ba ldr r2, [r7, #8]
80063aa: 629a str r2, [r3, #40] ; 0x28
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
80063ac: 2300 movs r3, #0
80063ae: 617b str r3, [r7, #20]
80063b0: e034 b.n 800641c <HAL_ETH_DMARxDescListInit+0xa6>
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
80063b2: 697b ldr r3, [r7, #20]
80063b4: 015b lsls r3, r3, #5
80063b6: 68ba ldr r2, [r7, #8]
80063b8: 4413 add r3, r2
80063ba: 613b str r3, [r7, #16]
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARXDESC_OWN;
80063bc: 693b ldr r3, [r7, #16]
80063be: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
80063c2: 601a str r2, [r3, #0]
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
80063c4: 693b ldr r3, [r7, #16]
80063c6: f244 52f4 movw r2, #17908 ; 0x45f4
80063ca: 605a str r2, [r3, #4]
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
80063cc: 697b ldr r3, [r7, #20]
80063ce: f240 52f4 movw r2, #1524 ; 0x5f4
80063d2: fb02 f303 mul.w r3, r2, r3
80063d6: 687a ldr r2, [r7, #4]
80063d8: 4413 add r3, r2
80063da: 461a mov r2, r3
80063dc: 693b ldr r3, [r7, #16]
80063de: 609a str r2, [r3, #8]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
80063e0: 68fb ldr r3, [r7, #12]
80063e2: 699b ldr r3, [r3, #24]
80063e4: 2b01 cmp r3, #1
80063e6: d105 bne.n 80063f4 <HAL_ETH_DMARxDescListInit+0x7e>
{
/* Enable Ethernet DMA Rx Descriptor interrupt */
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
80063e8: 693b ldr r3, [r7, #16]
80063ea: 685b ldr r3, [r3, #4]
80063ec: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
80063f0: 693b ldr r3, [r7, #16]
80063f2: 605a str r2, [r3, #4]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (RxBuffCount-1))
80063f4: 683b ldr r3, [r7, #0]
80063f6: 3b01 subs r3, #1
80063f8: 697a ldr r2, [r7, #20]
80063fa: 429a cmp r2, r3
80063fc: d208 bcs.n 8006410 <HAL_ETH_DMARxDescListInit+0x9a>
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
80063fe: 697b ldr r3, [r7, #20]
8006400: 3301 adds r3, #1
8006402: 015b lsls r3, r3, #5
8006404: 68ba ldr r2, [r7, #8]
8006406: 4413 add r3, r2
8006408: 461a mov r2, r3
800640a: 693b ldr r3, [r7, #16]
800640c: 60da str r2, [r3, #12]
800640e: e002 b.n 8006416 <HAL_ETH_DMARxDescListInit+0xa0>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
8006410: 68ba ldr r2, [r7, #8]
8006412: 693b ldr r3, [r7, #16]
8006414: 60da str r2, [r3, #12]
for(i=0; i < RxBuffCount; i++)
8006416: 697b ldr r3, [r7, #20]
8006418: 3301 adds r3, #1
800641a: 617b str r3, [r7, #20]
800641c: 697a ldr r2, [r7, #20]
800641e: 683b ldr r3, [r7, #0]
8006420: 429a cmp r2, r3
8006422: d3c6 bcc.n 80063b2 <HAL_ETH_DMARxDescListInit+0x3c>
}
}
/* Set Receive Descriptor List Address Register */
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
8006424: 68fb ldr r3, [r7, #12]
8006426: 6819 ldr r1, [r3, #0]
8006428: 68ba ldr r2, [r7, #8]
800642a: f241 030c movw r3, #4108 ; 0x100c
800642e: 440b add r3, r1
8006430: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006432: 68fb ldr r3, [r7, #12]
8006434: 2201 movs r2, #1
8006436: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800643a: 68fb ldr r3, [r7, #12]
800643c: 2200 movs r2, #0
800643e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006442: 2300 movs r3, #0
}
8006444: 4618 mov r0, r3
8006446: 371c adds r7, #28
8006448: 46bd mov sp, r7
800644a: f85d 7b04 ldr.w r7, [sp], #4
800644e: 4770 bx lr
08006450 <HAL_ETH_TransmitFrame>:
* the configuration information for ETHERNET module
* @param FrameLength Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
8006450: b480 push {r7}
8006452: b087 sub sp, #28
8006454: af00 add r7, sp, #0
8006456: 6078 str r0, [r7, #4]
8006458: 6039 str r1, [r7, #0]
uint32_t bufcount = 0, size = 0, i = 0;
800645a: 2300 movs r3, #0
800645c: 617b str r3, [r7, #20]
800645e: 2300 movs r3, #0
8006460: 60fb str r3, [r7, #12]
8006462: 2300 movs r3, #0
8006464: 613b str r3, [r7, #16]
/* Process Locked */
__HAL_LOCK(heth);
8006466: 687b ldr r3, [r7, #4]
8006468: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800646c: 2b01 cmp r3, #1
800646e: d101 bne.n 8006474 <HAL_ETH_TransmitFrame+0x24>
8006470: 2302 movs r3, #2
8006472: e0cd b.n 8006610 <HAL_ETH_TransmitFrame+0x1c0>
8006474: 687b ldr r3, [r7, #4]
8006476: 2201 movs r2, #1
8006478: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
800647c: 687b ldr r3, [r7, #4]
800647e: 2202 movs r2, #2
8006480: f883 2044 strb.w r2, [r3, #68] ; 0x44
if (FrameLength == 0)
8006484: 683b ldr r3, [r7, #0]
8006486: 2b00 cmp r3, #0
8006488: d109 bne.n 800649e <HAL_ETH_TransmitFrame+0x4e>
{
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
800648a: 687b ldr r3, [r7, #4]
800648c: 2201 movs r2, #1
800648e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006492: 687b ldr r3, [r7, #4]
8006494: 2200 movs r2, #0
8006496: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
800649a: 2301 movs r3, #1
800649c: e0b8 b.n 8006610 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800649e: 687b ldr r3, [r7, #4]
80064a0: 6adb ldr r3, [r3, #44] ; 0x2c
80064a2: 681b ldr r3, [r3, #0]
80064a4: 2b00 cmp r3, #0
80064a6: da09 bge.n 80064bc <HAL_ETH_TransmitFrame+0x6c>
{
/* OWN bit set */
heth->State = HAL_ETH_STATE_BUSY_TX;
80064a8: 687b ldr r3, [r7, #4]
80064aa: 2212 movs r2, #18
80064ac: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80064b0: 687b ldr r3, [r7, #4]
80064b2: 2200 movs r2, #0
80064b4: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
80064b8: 2301 movs r3, #1
80064ba: e0a9 b.n 8006610 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Get the number of needed Tx buffers for the current frame */
if (FrameLength > ETH_TX_BUF_SIZE)
80064bc: 683b ldr r3, [r7, #0]
80064be: f240 52f4 movw r2, #1524 ; 0x5f4
80064c2: 4293 cmp r3, r2
80064c4: d915 bls.n 80064f2 <HAL_ETH_TransmitFrame+0xa2>
{
bufcount = FrameLength/ETH_TX_BUF_SIZE;
80064c6: 683b ldr r3, [r7, #0]
80064c8: 4a54 ldr r2, [pc, #336] ; (800661c <HAL_ETH_TransmitFrame+0x1cc>)
80064ca: fba2 2303 umull r2, r3, r2, r3
80064ce: 0a9b lsrs r3, r3, #10
80064d0: 617b str r3, [r7, #20]
if (FrameLength % ETH_TX_BUF_SIZE)
80064d2: 683a ldr r2, [r7, #0]
80064d4: 4b51 ldr r3, [pc, #324] ; (800661c <HAL_ETH_TransmitFrame+0x1cc>)
80064d6: fba3 1302 umull r1, r3, r3, r2
80064da: 0a9b lsrs r3, r3, #10
80064dc: f240 51f4 movw r1, #1524 ; 0x5f4
80064e0: fb01 f303 mul.w r3, r1, r3
80064e4: 1ad3 subs r3, r2, r3
80064e6: 2b00 cmp r3, #0
80064e8: d005 beq.n 80064f6 <HAL_ETH_TransmitFrame+0xa6>
{
bufcount++;
80064ea: 697b ldr r3, [r7, #20]
80064ec: 3301 adds r3, #1
80064ee: 617b str r3, [r7, #20]
80064f0: e001 b.n 80064f6 <HAL_ETH_TransmitFrame+0xa6>
}
}
else
{
bufcount = 1;
80064f2: 2301 movs r3, #1
80064f4: 617b str r3, [r7, #20]
}
if (bufcount == 1)
80064f6: 697b ldr r3, [r7, #20]
80064f8: 2b01 cmp r3, #1
80064fa: d11c bne.n 8006536 <HAL_ETH_TransmitFrame+0xe6>
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
80064fc: 687b ldr r3, [r7, #4]
80064fe: 6adb ldr r3, [r3, #44] ; 0x2c
8006500: 681a ldr r2, [r3, #0]
8006502: 687b ldr r3, [r7, #4]
8006504: 6adb ldr r3, [r3, #44] ; 0x2c
8006506: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
800650a: 601a str r2, [r3, #0]
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
800650c: 687b ldr r3, [r7, #4]
800650e: 6adb ldr r3, [r3, #44] ; 0x2c
8006510: 683a ldr r2, [r7, #0]
8006512: f3c2 020c ubfx r2, r2, #0, #13
8006516: 605a str r2, [r3, #4]
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
8006518: 687b ldr r3, [r7, #4]
800651a: 6adb ldr r3, [r3, #44] ; 0x2c
800651c: 681a ldr r2, [r3, #0]
800651e: 687b ldr r3, [r7, #4]
8006520: 6adb ldr r3, [r3, #44] ; 0x2c
8006522: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
8006526: 601a str r2, [r3, #0]
/* Point to next descriptor */
heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
8006528: 687b ldr r3, [r7, #4]
800652a: 6adb ldr r3, [r3, #44] ; 0x2c
800652c: 68db ldr r3, [r3, #12]
800652e: 461a mov r2, r3
8006530: 687b ldr r3, [r7, #4]
8006532: 62da str r2, [r3, #44] ; 0x2c
8006534: e04b b.n 80065ce <HAL_ETH_TransmitFrame+0x17e>
}
else
{
for (i=0; i< bufcount; i++)
8006536: 2300 movs r3, #0
8006538: 613b str r3, [r7, #16]
800653a: e044 b.n 80065c6 <HAL_ETH_TransmitFrame+0x176>
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
800653c: 687b ldr r3, [r7, #4]
800653e: 6adb ldr r3, [r3, #44] ; 0x2c
8006540: 681a ldr r2, [r3, #0]
8006542: 687b ldr r3, [r7, #4]
8006544: 6adb ldr r3, [r3, #44] ; 0x2c
8006546: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
800654a: 601a str r2, [r3, #0]
if (i == 0)
800654c: 693b ldr r3, [r7, #16]
800654e: 2b00 cmp r3, #0
8006550: d107 bne.n 8006562 <HAL_ETH_TransmitFrame+0x112>
{
/* Setting the first segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
8006552: 687b ldr r3, [r7, #4]
8006554: 6adb ldr r3, [r3, #44] ; 0x2c
8006556: 681a ldr r2, [r3, #0]
8006558: 687b ldr r3, [r7, #4]
800655a: 6adb ldr r3, [r3, #44] ; 0x2c
800655c: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
8006560: 601a str r2, [r3, #0]
}
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
8006562: 687b ldr r3, [r7, #4]
8006564: 6adb ldr r3, [r3, #44] ; 0x2c
8006566: f240 52f4 movw r2, #1524 ; 0x5f4
800656a: 605a str r2, [r3, #4]
if (i == (bufcount-1))
800656c: 697b ldr r3, [r7, #20]
800656e: 3b01 subs r3, #1
8006570: 693a ldr r2, [r7, #16]
8006572: 429a cmp r2, r3
8006574: d116 bne.n 80065a4 <HAL_ETH_TransmitFrame+0x154>
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
8006576: 687b ldr r3, [r7, #4]
8006578: 6adb ldr r3, [r3, #44] ; 0x2c
800657a: 681a ldr r2, [r3, #0]
800657c: 687b ldr r3, [r7, #4]
800657e: 6adb ldr r3, [r3, #44] ; 0x2c
8006580: f042 5200 orr.w r2, r2, #536870912 ; 0x20000000
8006584: 601a str r2, [r3, #0]
size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
8006586: 697b ldr r3, [r7, #20]
8006588: 4a25 ldr r2, [pc, #148] ; (8006620 <HAL_ETH_TransmitFrame+0x1d0>)
800658a: fb02 f203 mul.w r2, r2, r3
800658e: 683b ldr r3, [r7, #0]
8006590: 4413 add r3, r2
8006592: f203 53f4 addw r3, r3, #1524 ; 0x5f4
8006596: 60fb str r3, [r7, #12]
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
8006598: 687b ldr r3, [r7, #4]
800659a: 6adb ldr r3, [r3, #44] ; 0x2c
800659c: 68fa ldr r2, [r7, #12]
800659e: f3c2 020c ubfx r2, r2, #0, #13
80065a2: 605a str r2, [r3, #4]
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
80065a4: 687b ldr r3, [r7, #4]
80065a6: 6adb ldr r3, [r3, #44] ; 0x2c
80065a8: 681a ldr r2, [r3, #0]
80065aa: 687b ldr r3, [r7, #4]
80065ac: 6adb ldr r3, [r3, #44] ; 0x2c
80065ae: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
80065b2: 601a str r2, [r3, #0]
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
80065b4: 687b ldr r3, [r7, #4]
80065b6: 6adb ldr r3, [r3, #44] ; 0x2c
80065b8: 68db ldr r3, [r3, #12]
80065ba: 461a mov r2, r3
80065bc: 687b ldr r3, [r7, #4]
80065be: 62da str r2, [r3, #44] ; 0x2c
for (i=0; i< bufcount; i++)
80065c0: 693b ldr r3, [r7, #16]
80065c2: 3301 adds r3, #1
80065c4: 613b str r3, [r7, #16]
80065c6: 693a ldr r2, [r7, #16]
80065c8: 697b ldr r3, [r7, #20]
80065ca: 429a cmp r2, r3
80065cc: d3b6 bcc.n 800653c <HAL_ETH_TransmitFrame+0xec>
}
}
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
80065ce: 687b ldr r3, [r7, #4]
80065d0: 681a ldr r2, [r3, #0]
80065d2: f241 0314 movw r3, #4116 ; 0x1014
80065d6: 4413 add r3, r2
80065d8: 681b ldr r3, [r3, #0]
80065da: f003 0304 and.w r3, r3, #4
80065de: 2b00 cmp r3, #0
80065e0: d00d beq.n 80065fe <HAL_ETH_TransmitFrame+0x1ae>
{
/* Clear TBUS ETHERNET DMA flag */
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
80065e2: 687b ldr r3, [r7, #4]
80065e4: 681a ldr r2, [r3, #0]
80065e6: f241 0314 movw r3, #4116 ; 0x1014
80065ea: 4413 add r3, r2
80065ec: 2204 movs r2, #4
80065ee: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
(heth->Instance)->DMATPDR = 0;
80065f0: 687b ldr r3, [r7, #4]
80065f2: 681a ldr r2, [r3, #0]
80065f4: f241 0304 movw r3, #4100 ; 0x1004
80065f8: 4413 add r3, r2
80065fa: 2200 movs r2, #0
80065fc: 601a str r2, [r3, #0]
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80065fe: 687b ldr r3, [r7, #4]
8006600: 2201 movs r2, #1
8006602: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006606: 687b ldr r3, [r7, #4]
8006608: 2200 movs r2, #0
800660a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
800660e: 2300 movs r3, #0
}
8006610: 4618 mov r0, r3
8006612: 371c adds r7, #28
8006614: 46bd mov sp, r7
8006616: f85d 7b04 ldr.w r7, [sp], #4
800661a: 4770 bx lr
800661c: ac02b00b .word 0xac02b00b
8006620: fffffa0c .word 0xfffffa0c
08006624 <HAL_ETH_GetReceivedFrame_IT>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
8006624: b480 push {r7}
8006626: b085 sub sp, #20
8006628: af00 add r7, sp, #0
800662a: 6078 str r0, [r7, #4]
uint32_t descriptorscancounter = 0;
800662c: 2300 movs r3, #0
800662e: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
8006630: 687b ldr r3, [r7, #4]
8006632: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006636: 2b01 cmp r3, #1
8006638: d101 bne.n 800663e <HAL_ETH_GetReceivedFrame_IT+0x1a>
800663a: 2302 movs r3, #2
800663c: e074 b.n 8006728 <HAL_ETH_GetReceivedFrame_IT+0x104>
800663e: 687b ldr r3, [r7, #4]
8006640: 2201 movs r2, #1
8006642: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006646: 687b ldr r3, [r7, #4]
8006648: 2202 movs r2, #2
800664a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Scan descriptors owned by CPU */
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
800664e: e05a b.n 8006706 <HAL_ETH_GetReceivedFrame_IT+0xe2>
{
/* Just for security */
descriptorscancounter++;
8006650: 68fb ldr r3, [r7, #12]
8006652: 3301 adds r3, #1
8006654: 60fb str r3, [r7, #12]
/* Check if first segment in frame */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
8006656: 687b ldr r3, [r7, #4]
8006658: 6a9b ldr r3, [r3, #40] ; 0x28
800665a: 681b ldr r3, [r3, #0]
800665c: f403 7340 and.w r3, r3, #768 ; 0x300
8006660: f5b3 7f00 cmp.w r3, #512 ; 0x200
8006664: d10d bne.n 8006682 <HAL_ETH_GetReceivedFrame_IT+0x5e>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
8006666: 687b ldr r3, [r7, #4]
8006668: 6a9a ldr r2, [r3, #40] ; 0x28
800666a: 687b ldr r3, [r7, #4]
800666c: 631a str r2, [r3, #48] ; 0x30
heth->RxFrameInfos.SegCount = 1;
800666e: 687b ldr r3, [r7, #4]
8006670: 2201 movs r2, #1
8006672: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
8006674: 687b ldr r3, [r7, #4]
8006676: 6a9b ldr r3, [r3, #40] ; 0x28
8006678: 68db ldr r3, [r3, #12]
800667a: 461a mov r2, r3
800667c: 687b ldr r3, [r7, #4]
800667e: 629a str r2, [r3, #40] ; 0x28
8006680: e041 b.n 8006706 <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Check if intermediate segment */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
8006682: 687b ldr r3, [r7, #4]
8006684: 6a9b ldr r3, [r3, #40] ; 0x28
8006686: 681b ldr r3, [r3, #0]
8006688: f403 7340 and.w r3, r3, #768 ; 0x300
800668c: 2b00 cmp r3, #0
800668e: d10b bne.n 80066a8 <HAL_ETH_GetReceivedFrame_IT+0x84>
{
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
8006690: 687b ldr r3, [r7, #4]
8006692: 6b9b ldr r3, [r3, #56] ; 0x38
8006694: 1c5a adds r2, r3, #1
8006696: 687b ldr r3, [r7, #4]
8006698: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
800669a: 687b ldr r3, [r7, #4]
800669c: 6a9b ldr r3, [r3, #40] ; 0x28
800669e: 68db ldr r3, [r3, #12]
80066a0: 461a mov r2, r3
80066a2: 687b ldr r3, [r7, #4]
80066a4: 629a str r2, [r3, #40] ; 0x28
80066a6: e02e b.n 8006706 <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Should be last segment */
else
{
/* Last segment */
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
80066a8: 687b ldr r3, [r7, #4]
80066aa: 6a9a ldr r2, [r3, #40] ; 0x28
80066ac: 687b ldr r3, [r7, #4]
80066ae: 635a str r2, [r3, #52] ; 0x34
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
80066b0: 687b ldr r3, [r7, #4]
80066b2: 6b9b ldr r3, [r3, #56] ; 0x38
80066b4: 1c5a adds r2, r3, #1
80066b6: 687b ldr r3, [r7, #4]
80066b8: 639a str r2, [r3, #56] ; 0x38
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos.SegCount) == 1)
80066ba: 687b ldr r3, [r7, #4]
80066bc: 6b9b ldr r3, [r3, #56] ; 0x38
80066be: 2b01 cmp r3, #1
80066c0: d103 bne.n 80066ca <HAL_ETH_GetReceivedFrame_IT+0xa6>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
80066c2: 687b ldr r3, [r7, #4]
80066c4: 6a9a ldr r2, [r3, #40] ; 0x28
80066c6: 687b ldr r3, [r7, #4]
80066c8: 631a str r2, [r3, #48] ; 0x30
}
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
80066ca: 687b ldr r3, [r7, #4]
80066cc: 6a9b ldr r3, [r3, #40] ; 0x28
80066ce: 681b ldr r3, [r3, #0]
80066d0: 0c1b lsrs r3, r3, #16
80066d2: f3c3 030d ubfx r3, r3, #0, #14
80066d6: 1f1a subs r2, r3, #4
80066d8: 687b ldr r3, [r7, #4]
80066da: 63da str r2, [r3, #60] ; 0x3c
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
80066dc: 687b ldr r3, [r7, #4]
80066de: 6b1b ldr r3, [r3, #48] ; 0x30
80066e0: 689a ldr r2, [r3, #8]
80066e2: 687b ldr r3, [r7, #4]
80066e4: 641a str r2, [r3, #64] ; 0x40
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
80066e6: 687b ldr r3, [r7, #4]
80066e8: 6a9b ldr r3, [r3, #40] ; 0x28
80066ea: 68db ldr r3, [r3, #12]
80066ec: 461a mov r2, r3
80066ee: 687b ldr r3, [r7, #4]
80066f0: 629a str r2, [r3, #40] ; 0x28
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80066f2: 687b ldr r3, [r7, #4]
80066f4: 2201 movs r2, #1
80066f6: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80066fa: 687b ldr r3, [r7, #4]
80066fc: 2200 movs r2, #0
80066fe: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006702: 2300 movs r3, #0
8006704: e010 b.n 8006728 <HAL_ETH_GetReceivedFrame_IT+0x104>
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
8006706: 687b ldr r3, [r7, #4]
8006708: 6a9b ldr r3, [r3, #40] ; 0x28
800670a: 681b ldr r3, [r3, #0]
800670c: 2b00 cmp r3, #0
800670e: db02 blt.n 8006716 <HAL_ETH_GetReceivedFrame_IT+0xf2>
8006710: 68fb ldr r3, [r7, #12]
8006712: 2b03 cmp r3, #3
8006714: d99c bls.n 8006650 <HAL_ETH_GetReceivedFrame_IT+0x2c>
}
}
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006716: 687b ldr r3, [r7, #4]
8006718: 2201 movs r2, #1
800671a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800671e: 687b ldr r3, [r7, #4]
8006720: 2200 movs r2, #0
8006722: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_ERROR;
8006726: 2301 movs r3, #1
}
8006728: 4618 mov r0, r3
800672a: 3714 adds r7, #20
800672c: 46bd mov sp, r7
800672e: f85d 7b04 ldr.w r7, [sp], #4
8006732: 4770 bx lr
08006734 <HAL_ETH_IRQHandler>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
8006734: b580 push {r7, lr}
8006736: b082 sub sp, #8
8006738: af00 add r7, sp, #0
800673a: 6078 str r0, [r7, #4]
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
800673c: 687b ldr r3, [r7, #4]
800673e: 681a ldr r2, [r3, #0]
8006740: f241 0314 movw r3, #4116 ; 0x1014
8006744: 4413 add r3, r2
8006746: 681b ldr r3, [r3, #0]
8006748: f003 0340 and.w r3, r3, #64 ; 0x40
800674c: 2b40 cmp r3, #64 ; 0x40
800674e: d112 bne.n 8006776 <HAL_ETH_IRQHandler+0x42>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
8006750: 6878 ldr r0, [r7, #4]
8006752: f004 fdaf bl 800b2b4 <HAL_ETH_RxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
8006756: 687b ldr r3, [r7, #4]
8006758: 681a ldr r2, [r3, #0]
800675a: f241 0314 movw r3, #4116 ; 0x1014
800675e: 4413 add r3, r2
8006760: 2240 movs r2, #64 ; 0x40
8006762: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006764: 687b ldr r3, [r7, #4]
8006766: 2201 movs r2, #1
8006768: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800676c: 687b ldr r3, [r7, #4]
800676e: 2200 movs r2, #0
8006770: f883 2045 strb.w r2, [r3, #69] ; 0x45
8006774: e01b b.n 80067ae <HAL_ETH_IRQHandler+0x7a>
}
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
8006776: 687b ldr r3, [r7, #4]
8006778: 681a ldr r2, [r3, #0]
800677a: f241 0314 movw r3, #4116 ; 0x1014
800677e: 4413 add r3, r2
8006780: 681b ldr r3, [r3, #0]
8006782: f003 0301 and.w r3, r3, #1
8006786: 2b01 cmp r3, #1
8006788: d111 bne.n 80067ae <HAL_ETH_IRQHandler+0x7a>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call resgistered Transfer complete callback*/
heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
800678a: 6878 ldr r0, [r7, #4]
800678c: f000 f839 bl 8006802 <HAL_ETH_TxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
8006790: 687b ldr r3, [r7, #4]
8006792: 681a ldr r2, [r3, #0]
8006794: f241 0314 movw r3, #4116 ; 0x1014
8006798: 4413 add r3, r2
800679a: 2201 movs r2, #1
800679c: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
800679e: 687b ldr r3, [r7, #4]
80067a0: 2201 movs r2, #1
80067a2: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80067a6: 687b ldr r3, [r7, #4]
80067a8: 2200 movs r2, #0
80067aa: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
80067ae: 687b ldr r3, [r7, #4]
80067b0: 681a ldr r2, [r3, #0]
80067b2: f241 0314 movw r3, #4116 ; 0x1014
80067b6: 4413 add r3, r2
80067b8: f44f 3280 mov.w r2, #65536 ; 0x10000
80067bc: 601a str r2, [r3, #0]
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
80067be: 687b ldr r3, [r7, #4]
80067c0: 681a ldr r2, [r3, #0]
80067c2: f241 0314 movw r3, #4116 ; 0x1014
80067c6: 4413 add r3, r2
80067c8: 681b ldr r3, [r3, #0]
80067ca: f403 4300 and.w r3, r3, #32768 ; 0x8000
80067ce: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80067d2: d112 bne.n 80067fa <HAL_ETH_IRQHandler+0xc6>
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
heth->DMAErrorCallback(heth);
#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
80067d4: 6878 ldr r0, [r7, #4]
80067d6: f000 f81e bl 8006816 <HAL_ETH_ErrorCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
80067da: 687b ldr r3, [r7, #4]
80067dc: 681a ldr r2, [r3, #0]
80067de: f241 0314 movw r3, #4116 ; 0x1014
80067e2: 4413 add r3, r2
80067e4: f44f 4200 mov.w r2, #32768 ; 0x8000
80067e8: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80067ea: 687b ldr r3, [r7, #4]
80067ec: 2201 movs r2, #1
80067ee: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80067f2: 687b ldr r3, [r7, #4]
80067f4: 2200 movs r2, #0
80067f6: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
}
80067fa: bf00 nop
80067fc: 3708 adds r7, #8
80067fe: 46bd mov sp, r7
8006800: bd80 pop {r7, pc}
08006802 <HAL_ETH_TxCpltCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
{
8006802: b480 push {r7}
8006804: b083 sub sp, #12
8006806: af00 add r7, sp, #0
8006808: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
800680a: bf00 nop
800680c: 370c adds r7, #12
800680e: 46bd mov sp, r7
8006810: f85d 7b04 ldr.w r7, [sp], #4
8006814: 4770 bx lr
08006816 <HAL_ETH_ErrorCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
8006816: b480 push {r7}
8006818: b083 sub sp, #12
800681a: af00 add r7, sp, #0
800681c: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_ErrorCallback could be implemented in the user file
*/
}
800681e: bf00 nop
8006820: 370c adds r7, #12
8006822: 46bd mov sp, r7
8006824: f85d 7b04 ldr.w r7, [sp], #4
8006828: 4770 bx lr
0800682a <HAL_ETH_ReadPHYRegister>:
* More PHY register could be read depending on the used PHY
* @param RegValue PHY register value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
800682a: b580 push {r7, lr}
800682c: b086 sub sp, #24
800682e: af00 add r7, sp, #0
8006830: 60f8 str r0, [r7, #12]
8006832: 460b mov r3, r1
8006834: 607a str r2, [r7, #4]
8006836: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
8006838: 2300 movs r3, #0
800683a: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
800683c: 2300 movs r3, #0
800683e: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_RD)
8006840: 68fb ldr r3, [r7, #12]
8006842: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8006846: b2db uxtb r3, r3
8006848: 2b82 cmp r3, #130 ; 0x82
800684a: d101 bne.n 8006850 <HAL_ETH_ReadPHYRegister+0x26>
{
return HAL_BUSY;
800684c: 2302 movs r3, #2
800684e: e050 b.n 80068f2 <HAL_ETH_ReadPHYRegister+0xc8>
}
/* Set ETH HAL State to BUSY_RD */
heth->State = HAL_ETH_STATE_BUSY_RD;
8006850: 68fb ldr r3, [r7, #12]
8006852: 2282 movs r2, #130 ; 0x82
8006854: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
8006858: 68fb ldr r3, [r7, #12]
800685a: 681b ldr r3, [r3, #0]
800685c: 691b ldr r3, [r3, #16]
800685e: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
8006860: 697b ldr r3, [r7, #20]
8006862: f003 031c and.w r3, r3, #28
8006866: 617b str r3, [r7, #20]
/* Prepare the MII address register value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
8006868: 68fb ldr r3, [r7, #12]
800686a: 8a1b ldrh r3, [r3, #16]
800686c: 02db lsls r3, r3, #11
800686e: b29b uxth r3, r3
8006870: 697a ldr r2, [r7, #20]
8006872: 4313 orrs r3, r2
8006874: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
8006876: 897b ldrh r3, [r7, #10]
8006878: 019b lsls r3, r3, #6
800687a: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
800687e: 697a ldr r2, [r7, #20]
8006880: 4313 orrs r3, r2
8006882: 617b str r3, [r7, #20]
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
8006884: 697b ldr r3, [r7, #20]
8006886: f023 0302 bic.w r3, r3, #2
800688a: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
800688c: 697b ldr r3, [r7, #20]
800688e: f043 0301 orr.w r3, r3, #1
8006892: 617b str r3, [r7, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
8006894: 68fb ldr r3, [r7, #12]
8006896: 681b ldr r3, [r3, #0]
8006898: 697a ldr r2, [r7, #20]
800689a: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
800689c: f7fe f87c bl 8004998 <HAL_GetTick>
80068a0: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80068a2: e015 b.n 80068d0 <HAL_ETH_ReadPHYRegister+0xa6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
80068a4: f7fe f878 bl 8004998 <HAL_GetTick>
80068a8: 4602 mov r2, r0
80068aa: 693b ldr r3, [r7, #16]
80068ac: 1ad3 subs r3, r2, r3
80068ae: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80068b2: d309 bcc.n 80068c8 <HAL_ETH_ReadPHYRegister+0x9e>
{
heth->State= HAL_ETH_STATE_READY;
80068b4: 68fb ldr r3, [r7, #12]
80068b6: 2201 movs r2, #1
80068b8: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80068bc: 68fb ldr r3, [r7, #12]
80068be: 2200 movs r2, #0
80068c0: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
80068c4: 2303 movs r3, #3
80068c6: e014 b.n 80068f2 <HAL_ETH_ReadPHYRegister+0xc8>
}
tmpreg = heth->Instance->MACMIIAR;
80068c8: 68fb ldr r3, [r7, #12]
80068ca: 681b ldr r3, [r3, #0]
80068cc: 691b ldr r3, [r3, #16]
80068ce: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80068d0: 697b ldr r3, [r7, #20]
80068d2: f003 0301 and.w r3, r3, #1
80068d6: 2b00 cmp r3, #0
80068d8: d1e4 bne.n 80068a4 <HAL_ETH_ReadPHYRegister+0x7a>
}
/* Get MACMIIDR value */
*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
80068da: 68fb ldr r3, [r7, #12]
80068dc: 681b ldr r3, [r3, #0]
80068de: 695b ldr r3, [r3, #20]
80068e0: b29b uxth r3, r3
80068e2: 461a mov r2, r3
80068e4: 687b ldr r3, [r7, #4]
80068e6: 601a str r2, [r3, #0]
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
80068e8: 68fb ldr r3, [r7, #12]
80068ea: 2201 movs r2, #1
80068ec: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
80068f0: 2300 movs r3, #0
}
80068f2: 4618 mov r0, r3
80068f4: 3718 adds r7, #24
80068f6: 46bd mov sp, r7
80068f8: bd80 pop {r7, pc}
080068fa <HAL_ETH_WritePHYRegister>:
* More PHY register could be written depending on the used PHY
* @param RegValue the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
80068fa: b580 push {r7, lr}
80068fc: b086 sub sp, #24
80068fe: af00 add r7, sp, #0
8006900: 60f8 str r0, [r7, #12]
8006902: 460b mov r3, r1
8006904: 607a str r2, [r7, #4]
8006906: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
8006908: 2300 movs r3, #0
800690a: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
800690c: 2300 movs r3, #0
800690e: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_WR)
8006910: 68fb ldr r3, [r7, #12]
8006912: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8006916: b2db uxtb r3, r3
8006918: 2b42 cmp r3, #66 ; 0x42
800691a: d101 bne.n 8006920 <HAL_ETH_WritePHYRegister+0x26>
{
return HAL_BUSY;
800691c: 2302 movs r3, #2
800691e: e04e b.n 80069be <HAL_ETH_WritePHYRegister+0xc4>
}
/* Set ETH HAL State to BUSY_WR */
heth->State = HAL_ETH_STATE_BUSY_WR;
8006920: 68fb ldr r3, [r7, #12]
8006922: 2242 movs r2, #66 ; 0x42
8006924: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
8006928: 68fb ldr r3, [r7, #12]
800692a: 681b ldr r3, [r3, #0]
800692c: 691b ldr r3, [r3, #16]
800692e: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
8006930: 697b ldr r3, [r7, #20]
8006932: f003 031c and.w r3, r3, #28
8006936: 617b str r3, [r7, #20]
/* Prepare the MII register address value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
8006938: 68fb ldr r3, [r7, #12]
800693a: 8a1b ldrh r3, [r3, #16]
800693c: 02db lsls r3, r3, #11
800693e: b29b uxth r3, r3
8006940: 697a ldr r2, [r7, #20]
8006942: 4313 orrs r3, r2
8006944: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
8006946: 897b ldrh r3, [r7, #10]
8006948: 019b lsls r3, r3, #6
800694a: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
800694e: 697a ldr r2, [r7, #20]
8006950: 4313 orrs r3, r2
8006952: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
8006954: 697b ldr r3, [r7, #20]
8006956: f043 0302 orr.w r3, r3, #2
800695a: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
800695c: 697b ldr r3, [r7, #20]
800695e: f043 0301 orr.w r3, r3, #1
8006962: 617b str r3, [r7, #20]
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
8006964: 687b ldr r3, [r7, #4]
8006966: b29a uxth r2, r3
8006968: 68fb ldr r3, [r7, #12]
800696a: 681b ldr r3, [r3, #0]
800696c: 615a str r2, [r3, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
800696e: 68fb ldr r3, [r7, #12]
8006970: 681b ldr r3, [r3, #0]
8006972: 697a ldr r2, [r7, #20]
8006974: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
8006976: f7fe f80f bl 8004998 <HAL_GetTick>
800697a: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
800697c: e015 b.n 80069aa <HAL_ETH_WritePHYRegister+0xb0>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
800697e: f7fe f80b bl 8004998 <HAL_GetTick>
8006982: 4602 mov r2, r0
8006984: 693b ldr r3, [r7, #16]
8006986: 1ad3 subs r3, r2, r3
8006988: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800698c: d309 bcc.n 80069a2 <HAL_ETH_WritePHYRegister+0xa8>
{
heth->State= HAL_ETH_STATE_READY;
800698e: 68fb ldr r3, [r7, #12]
8006990: 2201 movs r2, #1
8006992: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006996: 68fb ldr r3, [r7, #12]
8006998: 2200 movs r2, #0
800699a: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
800699e: 2303 movs r3, #3
80069a0: e00d b.n 80069be <HAL_ETH_WritePHYRegister+0xc4>
}
tmpreg = heth->Instance->MACMIIAR;
80069a2: 68fb ldr r3, [r7, #12]
80069a4: 681b ldr r3, [r3, #0]
80069a6: 691b ldr r3, [r3, #16]
80069a8: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80069aa: 697b ldr r3, [r7, #20]
80069ac: f003 0301 and.w r3, r3, #1
80069b0: 2b00 cmp r3, #0
80069b2: d1e4 bne.n 800697e <HAL_ETH_WritePHYRegister+0x84>
}
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
80069b4: 68fb ldr r3, [r7, #12]
80069b6: 2201 movs r2, #1
80069b8: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
80069bc: 2300 movs r3, #0
}
80069be: 4618 mov r0, r3
80069c0: 3718 adds r7, #24
80069c2: 46bd mov sp, r7
80069c4: bd80 pop {r7, pc}
080069c6 <HAL_ETH_Start>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
80069c6: b580 push {r7, lr}
80069c8: b082 sub sp, #8
80069ca: af00 add r7, sp, #0
80069cc: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
80069ce: 687b ldr r3, [r7, #4]
80069d0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80069d4: 2b01 cmp r3, #1
80069d6: d101 bne.n 80069dc <HAL_ETH_Start+0x16>
80069d8: 2302 movs r3, #2
80069da: e01f b.n 8006a1c <HAL_ETH_Start+0x56>
80069dc: 687b ldr r3, [r7, #4]
80069de: 2201 movs r2, #1
80069e0: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80069e4: 687b ldr r3, [r7, #4]
80069e6: 2202 movs r2, #2
80069e8: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Enable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionEnable(heth);
80069ec: 6878 ldr r0, [r7, #4]
80069ee: f000 fb45 bl 800707c <ETH_MACTransmissionEnable>
/* Enable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionEnable(heth);
80069f2: 6878 ldr r0, [r7, #4]
80069f4: f000 fb7c bl 80070f0 <ETH_MACReceptionEnable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
80069f8: 6878 ldr r0, [r7, #4]
80069fa: f000 fc13 bl 8007224 <ETH_FlushTransmitFIFO>
/* Start DMA transmission */
ETH_DMATransmissionEnable(heth);
80069fe: 6878 ldr r0, [r7, #4]
8006a00: f000 fbb0 bl 8007164 <ETH_DMATransmissionEnable>
/* Start DMA reception */
ETH_DMAReceptionEnable(heth);
8006a04: 6878 ldr r0, [r7, #4]
8006a06: f000 fbdd bl 80071c4 <ETH_DMAReceptionEnable>
/* Set the ETH state to READY*/
heth->State= HAL_ETH_STATE_READY;
8006a0a: 687b ldr r3, [r7, #4]
8006a0c: 2201 movs r2, #1
8006a0e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006a12: 687b ldr r3, [r7, #4]
8006a14: 2200 movs r2, #0
8006a16: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006a1a: 2300 movs r3, #0
}
8006a1c: 4618 mov r0, r3
8006a1e: 3708 adds r7, #8
8006a20: 46bd mov sp, r7
8006a22: bd80 pop {r7, pc}
08006a24 <HAL_ETH_Stop>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
8006a24: b580 push {r7, lr}
8006a26: b082 sub sp, #8
8006a28: af00 add r7, sp, #0
8006a2a: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
8006a2c: 687b ldr r3, [r7, #4]
8006a2e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006a32: 2b01 cmp r3, #1
8006a34: d101 bne.n 8006a3a <HAL_ETH_Stop+0x16>
8006a36: 2302 movs r3, #2
8006a38: e01f b.n 8006a7a <HAL_ETH_Stop+0x56>
8006a3a: 687b ldr r3, [r7, #4]
8006a3c: 2201 movs r2, #1
8006a3e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006a42: 687b ldr r3, [r7, #4]
8006a44: 2202 movs r2, #2
8006a46: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Stop DMA transmission */
ETH_DMATransmissionDisable(heth);
8006a4a: 6878 ldr r0, [r7, #4]
8006a4c: f000 fba2 bl 8007194 <ETH_DMATransmissionDisable>
/* Stop DMA reception */
ETH_DMAReceptionDisable(heth);
8006a50: 6878 ldr r0, [r7, #4]
8006a52: f000 fbcf bl 80071f4 <ETH_DMAReceptionDisable>
/* Disable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionDisable(heth);
8006a56: 6878 ldr r0, [r7, #4]
8006a58: f000 fb67 bl 800712a <ETH_MACReceptionDisable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
8006a5c: 6878 ldr r0, [r7, #4]
8006a5e: f000 fbe1 bl 8007224 <ETH_FlushTransmitFIFO>
/* Disable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionDisable(heth);
8006a62: 6878 ldr r0, [r7, #4]
8006a64: f000 fb27 bl 80070b6 <ETH_MACTransmissionDisable>
/* Set the ETH state*/
heth->State = HAL_ETH_STATE_READY;
8006a68: 687b ldr r3, [r7, #4]
8006a6a: 2201 movs r2, #1
8006a6c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006a70: 687b ldr r3, [r7, #4]
8006a72: 2200 movs r2, #0
8006a74: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006a78: 2300 movs r3, #0
}
8006a7a: 4618 mov r0, r3
8006a7c: 3708 adds r7, #8
8006a7e: 46bd mov sp, r7
8006a80: bd80 pop {r7, pc}
...
08006a84 <HAL_ETH_ConfigMAC>:
* the configuration information for ETHERNET module
* @param macconf MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
8006a84: b580 push {r7, lr}
8006a86: b084 sub sp, #16
8006a88: af00 add r7, sp, #0
8006a8a: 6078 str r0, [r7, #4]
8006a8c: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
8006a8e: 2300 movs r3, #0
8006a90: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
8006a92: 687b ldr r3, [r7, #4]
8006a94: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006a98: 2b01 cmp r3, #1
8006a9a: d101 bne.n 8006aa0 <HAL_ETH_ConfigMAC+0x1c>
8006a9c: 2302 movs r3, #2
8006a9e: e0e4 b.n 8006c6a <HAL_ETH_ConfigMAC+0x1e6>
8006aa0: 687b ldr r3, [r7, #4]
8006aa2: 2201 movs r2, #1
8006aa4: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State= HAL_ETH_STATE_BUSY;
8006aa8: 687b ldr r3, [r7, #4]
8006aaa: 2202 movs r2, #2
8006aac: f883 2044 strb.w r2, [r3, #68] ; 0x44
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
if (macconf != NULL)
8006ab0: 683b ldr r3, [r7, #0]
8006ab2: 2b00 cmp r3, #0
8006ab4: f000 80b1 beq.w 8006c1a <HAL_ETH_ConfigMAC+0x196>
assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006ab8: 687b ldr r3, [r7, #4]
8006aba: 681b ldr r3, [r3, #0]
8006abc: 681b ldr r3, [r3, #0]
8006abe: 60fb str r3, [r7, #12]
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006ac0: 68fa ldr r2, [r7, #12]
8006ac2: 4b6c ldr r3, [pc, #432] ; (8006c74 <HAL_ETH_ConfigMAC+0x1f0>)
8006ac4: 4013 ands r3, r2
8006ac6: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006ac8: 683b ldr r3, [r7, #0]
8006aca: 681a ldr r2, [r3, #0]
macconf->Jabber |
8006acc: 683b ldr r3, [r7, #0]
8006ace: 685b ldr r3, [r3, #4]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006ad0: 431a orrs r2, r3
macconf->InterFrameGap |
8006ad2: 683b ldr r3, [r7, #0]
8006ad4: 689b ldr r3, [r3, #8]
macconf->Jabber |
8006ad6: 431a orrs r2, r3
macconf->CarrierSense |
8006ad8: 683b ldr r3, [r7, #0]
8006ada: 68db ldr r3, [r3, #12]
macconf->InterFrameGap |
8006adc: 431a orrs r2, r3
(heth->Init).Speed |
8006ade: 687b ldr r3, [r7, #4]
8006ae0: 689b ldr r3, [r3, #8]
macconf->CarrierSense |
8006ae2: 431a orrs r2, r3
macconf->ReceiveOwn |
8006ae4: 683b ldr r3, [r7, #0]
8006ae6: 691b ldr r3, [r3, #16]
(heth->Init).Speed |
8006ae8: 431a orrs r2, r3
macconf->LoopbackMode |
8006aea: 683b ldr r3, [r7, #0]
8006aec: 695b ldr r3, [r3, #20]
macconf->ReceiveOwn |
8006aee: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006af0: 687b ldr r3, [r7, #4]
8006af2: 68db ldr r3, [r3, #12]
macconf->LoopbackMode |
8006af4: 431a orrs r2, r3
macconf->ChecksumOffload |
8006af6: 683b ldr r3, [r7, #0]
8006af8: 699b ldr r3, [r3, #24]
(heth->Init).DuplexMode |
8006afa: 431a orrs r2, r3
macconf->RetryTransmission |
8006afc: 683b ldr r3, [r7, #0]
8006afe: 69db ldr r3, [r3, #28]
macconf->ChecksumOffload |
8006b00: 431a orrs r2, r3
macconf->AutomaticPadCRCStrip |
8006b02: 683b ldr r3, [r7, #0]
8006b04: 6a1b ldr r3, [r3, #32]
macconf->RetryTransmission |
8006b06: 431a orrs r2, r3
macconf->BackOffLimit |
8006b08: 683b ldr r3, [r7, #0]
8006b0a: 6a5b ldr r3, [r3, #36] ; 0x24
macconf->AutomaticPadCRCStrip |
8006b0c: 431a orrs r2, r3
macconf->DeferralCheck);
8006b0e: 683b ldr r3, [r7, #0]
8006b10: 6a9b ldr r3, [r3, #40] ; 0x28
macconf->BackOffLimit |
8006b12: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macconf->Watchdog |
8006b14: 68fa ldr r2, [r7, #12]
8006b16: 4313 orrs r3, r2
8006b18: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006b1a: 687b ldr r3, [r7, #4]
8006b1c: 681b ldr r3, [r3, #0]
8006b1e: 68fa ldr r2, [r7, #12]
8006b20: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006b22: 687b ldr r3, [r7, #4]
8006b24: 681b ldr r3, [r3, #0]
8006b26: 681b ldr r3, [r3, #0]
8006b28: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006b2a: 2001 movs r0, #1
8006b2c: f7fd ff40 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006b30: 687b ldr r3, [r7, #4]
8006b32: 681b ldr r3, [r3, #0]
8006b34: 68fa ldr r2, [r7, #12]
8006b36: 601a str r2, [r3, #0]
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b38: 683b ldr r3, [r7, #0]
8006b3a: 6ada ldr r2, [r3, #44] ; 0x2c
macconf->SourceAddrFilter |
8006b3c: 683b ldr r3, [r7, #0]
8006b3e: 6b1b ldr r3, [r3, #48] ; 0x30
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b40: 431a orrs r2, r3
macconf->PassControlFrames |
8006b42: 683b ldr r3, [r7, #0]
8006b44: 6b5b ldr r3, [r3, #52] ; 0x34
macconf->SourceAddrFilter |
8006b46: 431a orrs r2, r3
macconf->BroadcastFramesReception |
8006b48: 683b ldr r3, [r7, #0]
8006b4a: 6b9b ldr r3, [r3, #56] ; 0x38
macconf->PassControlFrames |
8006b4c: 431a orrs r2, r3
macconf->DestinationAddrFilter |
8006b4e: 683b ldr r3, [r7, #0]
8006b50: 6bdb ldr r3, [r3, #60] ; 0x3c
macconf->BroadcastFramesReception |
8006b52: 431a orrs r2, r3
macconf->PromiscuousMode |
8006b54: 683b ldr r3, [r7, #0]
8006b56: 6c1b ldr r3, [r3, #64] ; 0x40
macconf->DestinationAddrFilter |
8006b58: 431a orrs r2, r3
macconf->MulticastFramesFilter |
8006b5a: 683b ldr r3, [r7, #0]
8006b5c: 6c5b ldr r3, [r3, #68] ; 0x44
macconf->PromiscuousMode |
8006b5e: ea42 0103 orr.w r1, r2, r3
macconf->UnicastFramesFilter);
8006b62: 683b ldr r3, [r7, #0]
8006b64: 6c9a ldr r2, [r3, #72] ; 0x48
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b66: 687b ldr r3, [r7, #4]
8006b68: 681b ldr r3, [r3, #0]
macconf->MulticastFramesFilter |
8006b6a: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b6c: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
8006b6e: 687b ldr r3, [r7, #4]
8006b70: 681b ldr r3, [r3, #0]
8006b72: 685b ldr r3, [r3, #4]
8006b74: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006b76: 2001 movs r0, #1
8006b78: f7fd ff1a bl 80049b0 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006b7c: 687b ldr r3, [r7, #4]
8006b7e: 681b ldr r3, [r3, #0]
8006b80: 68fa ldr r2, [r7, #12]
8006b82: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
8006b84: 687b ldr r3, [r7, #4]
8006b86: 681b ldr r3, [r3, #0]
8006b88: 683a ldr r2, [r7, #0]
8006b8a: 6cd2 ldr r2, [r2, #76] ; 0x4c
8006b8c: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
8006b8e: 687b ldr r3, [r7, #4]
8006b90: 681b ldr r3, [r3, #0]
8006b92: 683a ldr r2, [r7, #0]
8006b94: 6d12 ldr r2, [r2, #80] ; 0x50
8006b96: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006b98: 687b ldr r3, [r7, #4]
8006b9a: 681b ldr r3, [r3, #0]
8006b9c: 699b ldr r3, [r3, #24]
8006b9e: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006ba0: 68fa ldr r2, [r7, #12]
8006ba2: f64f 7341 movw r3, #65345 ; 0xff41
8006ba6: 4013 ands r3, r2
8006ba8: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006baa: 683b ldr r3, [r7, #0]
8006bac: 6d5b ldr r3, [r3, #84] ; 0x54
8006bae: 041a lsls r2, r3, #16
macconf->ZeroQuantaPause |
8006bb0: 683b ldr r3, [r7, #0]
8006bb2: 6d9b ldr r3, [r3, #88] ; 0x58
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006bb4: 431a orrs r2, r3
macconf->PauseLowThreshold |
8006bb6: 683b ldr r3, [r7, #0]
8006bb8: 6ddb ldr r3, [r3, #92] ; 0x5c
macconf->ZeroQuantaPause |
8006bba: 431a orrs r2, r3
macconf->UnicastPauseFrameDetect |
8006bbc: 683b ldr r3, [r7, #0]
8006bbe: 6e1b ldr r3, [r3, #96] ; 0x60
macconf->PauseLowThreshold |
8006bc0: 431a orrs r2, r3
macconf->ReceiveFlowControl |
8006bc2: 683b ldr r3, [r7, #0]
8006bc4: 6e5b ldr r3, [r3, #100] ; 0x64
macconf->UnicastPauseFrameDetect |
8006bc6: 431a orrs r2, r3
macconf->TransmitFlowControl);
8006bc8: 683b ldr r3, [r7, #0]
8006bca: 6e9b ldr r3, [r3, #104] ; 0x68
macconf->ReceiveFlowControl |
8006bcc: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006bce: 68fa ldr r2, [r7, #12]
8006bd0: 4313 orrs r3, r2
8006bd2: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006bd4: 687b ldr r3, [r7, #4]
8006bd6: 681b ldr r3, [r3, #0]
8006bd8: 68fa ldr r2, [r7, #12]
8006bda: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006bdc: 687b ldr r3, [r7, #4]
8006bde: 681b ldr r3, [r3, #0]
8006be0: 699b ldr r3, [r3, #24]
8006be2: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006be4: 2001 movs r0, #1
8006be6: f7fd fee3 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006bea: 687b ldr r3, [r7, #4]
8006bec: 681b ldr r3, [r3, #0]
8006bee: 68fa ldr r2, [r7, #12]
8006bf0: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006bf2: 683b ldr r3, [r7, #0]
8006bf4: 6ed9 ldr r1, [r3, #108] ; 0x6c
macconf->VLANTagIdentifier);
8006bf6: 683b ldr r3, [r7, #0]
8006bf8: 6f1a ldr r2, [r3, #112] ; 0x70
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006bfa: 687b ldr r3, [r7, #4]
8006bfc: 681b ldr r3, [r3, #0]
8006bfe: 430a orrs r2, r1
8006c00: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006c02: 687b ldr r3, [r7, #4]
8006c04: 681b ldr r3, [r3, #0]
8006c06: 69db ldr r3, [r3, #28]
8006c08: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c0a: 2001 movs r0, #1
8006c0c: f7fd fed0 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006c10: 687b ldr r3, [r7, #4]
8006c12: 681b ldr r3, [r3, #0]
8006c14: 68fa ldr r2, [r7, #12]
8006c16: 61da str r2, [r3, #28]
8006c18: e01e b.n 8006c58 <HAL_ETH_ConfigMAC+0x1d4>
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006c1a: 687b ldr r3, [r7, #4]
8006c1c: 681b ldr r3, [r3, #0]
8006c1e: 681b ldr r3, [r3, #0]
8006c20: 60fb str r3, [r7, #12]
/* Clear FES and DM bits */
tmpreg &= ~((uint32_t)0x00004800);
8006c22: 68fb ldr r3, [r7, #12]
8006c24: f423 4390 bic.w r3, r3, #18432 ; 0x4800
8006c28: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
8006c2a: 687b ldr r3, [r7, #4]
8006c2c: 689a ldr r2, [r3, #8]
8006c2e: 687b ldr r3, [r7, #4]
8006c30: 68db ldr r3, [r3, #12]
8006c32: 4313 orrs r3, r2
8006c34: 68fa ldr r2, [r7, #12]
8006c36: 4313 orrs r3, r2
8006c38: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006c3a: 687b ldr r3, [r7, #4]
8006c3c: 681b ldr r3, [r3, #0]
8006c3e: 68fa ldr r2, [r7, #12]
8006c40: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006c42: 687b ldr r3, [r7, #4]
8006c44: 681b ldr r3, [r3, #0]
8006c46: 681b ldr r3, [r3, #0]
8006c48: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c4a: 2001 movs r0, #1
8006c4c: f7fd feb0 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006c50: 687b ldr r3, [r7, #4]
8006c52: 681b ldr r3, [r3, #0]
8006c54: 68fa ldr r2, [r7, #12]
8006c56: 601a str r2, [r3, #0]
}
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
8006c58: 687b ldr r3, [r7, #4]
8006c5a: 2201 movs r2, #1
8006c5c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006c60: 687b ldr r3, [r7, #4]
8006c62: 2200 movs r2, #0
8006c64: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006c68: 2300 movs r3, #0
}
8006c6a: 4618 mov r0, r3
8006c6c: 3710 adds r7, #16
8006c6e: 46bd mov sp, r7
8006c70: bd80 pop {r7, pc}
8006c72: bf00 nop
8006c74: ff20810f .word 0xff20810f
08006c78 <ETH_MACDMAConfig>:
* the configuration information for ETHERNET module
* @param err Ethernet Init error
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
8006c78: b580 push {r7, lr}
8006c7a: b0b0 sub sp, #192 ; 0xc0
8006c7c: af00 add r7, sp, #0
8006c7e: 6078 str r0, [r7, #4]
8006c80: 6039 str r1, [r7, #0]
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
uint32_t tmpreg = 0;
8006c82: 2300 movs r3, #0
8006c84: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
8006c88: 683b ldr r3, [r7, #0]
8006c8a: 2b00 cmp r3, #0
8006c8c: d007 beq.n 8006c9e <ETH_MACDMAConfig+0x26>
{
/* Set Ethernet duplex mode to Full-duplex */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
8006c8e: 687b ldr r3, [r7, #4]
8006c90: f44f 6200 mov.w r2, #2048 ; 0x800
8006c94: 60da str r2, [r3, #12]
/* Set Ethernet speed to 100M */
(heth->Init).Speed = ETH_SPEED_100M;
8006c96: 687b ldr r3, [r7, #4]
8006c98: f44f 4280 mov.w r2, #16384 ; 0x4000
8006c9c: 609a str r2, [r3, #8]
}
/* Ethernet MAC default initialization **************************************/
macinit.Watchdog = ETH_WATCHDOG_ENABLE;
8006c9e: 2300 movs r3, #0
8006ca0: 64bb str r3, [r7, #72] ; 0x48
macinit.Jabber = ETH_JABBER_ENABLE;
8006ca2: 2300 movs r3, #0
8006ca4: 64fb str r3, [r7, #76] ; 0x4c
macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
8006ca6: 2300 movs r3, #0
8006ca8: 653b str r3, [r7, #80] ; 0x50
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
8006caa: 2300 movs r3, #0
8006cac: 657b str r3, [r7, #84] ; 0x54
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
8006cae: 2300 movs r3, #0
8006cb0: 65bb str r3, [r7, #88] ; 0x58
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
8006cb2: 2300 movs r3, #0
8006cb4: 65fb str r3, [r7, #92] ; 0x5c
if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
8006cb6: 687b ldr r3, [r7, #4]
8006cb8: 69db ldr r3, [r3, #28]
8006cba: 2b00 cmp r3, #0
8006cbc: d103 bne.n 8006cc6 <ETH_MACDMAConfig+0x4e>
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
8006cbe: f44f 6380 mov.w r3, #1024 ; 0x400
8006cc2: 663b str r3, [r7, #96] ; 0x60
8006cc4: e001 b.n 8006cca <ETH_MACDMAConfig+0x52>
}
else
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
8006cc6: 2300 movs r3, #0
8006cc8: 663b str r3, [r7, #96] ; 0x60
}
macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
8006cca: f44f 7300 mov.w r3, #512 ; 0x200
8006cce: 667b str r3, [r7, #100] ; 0x64
macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
8006cd0: 2300 movs r3, #0
8006cd2: 66bb str r3, [r7, #104] ; 0x68
macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
8006cd4: 2300 movs r3, #0
8006cd6: 66fb str r3, [r7, #108] ; 0x6c
macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
8006cd8: 2300 movs r3, #0
8006cda: 673b str r3, [r7, #112] ; 0x70
macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
8006cdc: 2300 movs r3, #0
8006cde: 677b str r3, [r7, #116] ; 0x74
macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
8006ce0: 2300 movs r3, #0
8006ce2: 67bb str r3, [r7, #120] ; 0x78
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
8006ce4: 2340 movs r3, #64 ; 0x40
8006ce6: 67fb str r3, [r7, #124] ; 0x7c
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
8006ce8: 2300 movs r3, #0
8006cea: f8c7 3080 str.w r3, [r7, #128] ; 0x80
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
8006cee: 2300 movs r3, #0
8006cf0: f8c7 3084 str.w r3, [r7, #132] ; 0x84
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
8006cf4: 2300 movs r3, #0
8006cf6: f8c7 3088 str.w r3, [r7, #136] ; 0x88
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
8006cfa: 2300 movs r3, #0
8006cfc: f8c7 308c str.w r3, [r7, #140] ; 0x8c
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
8006d00: 2300 movs r3, #0
8006d02: f8c7 3090 str.w r3, [r7, #144] ; 0x90
macinit.HashTableHigh = 0x0;
8006d06: 2300 movs r3, #0
8006d08: f8c7 3094 str.w r3, [r7, #148] ; 0x94
macinit.HashTableLow = 0x0;
8006d0c: 2300 movs r3, #0
8006d0e: f8c7 3098 str.w r3, [r7, #152] ; 0x98
macinit.PauseTime = 0x0;
8006d12: 2300 movs r3, #0
8006d14: f8c7 309c str.w r3, [r7, #156] ; 0x9c
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
8006d18: 2380 movs r3, #128 ; 0x80
8006d1a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
8006d1e: 2300 movs r3, #0
8006d20: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
8006d24: 2300 movs r3, #0
8006d26: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
8006d2a: 2300 movs r3, #0
8006d2c: f8c7 30ac str.w r3, [r7, #172] ; 0xac
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
8006d30: 2300 movs r3, #0
8006d32: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
8006d36: 2300 movs r3, #0
8006d38: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier = 0x0;
8006d3c: 2300 movs r3, #0
8006d3e: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006d42: 687b ldr r3, [r7, #4]
8006d44: 681b ldr r3, [r3, #0]
8006d46: 681b ldr r3, [r3, #0]
8006d48: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006d4c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d50: 4bab ldr r3, [pc, #684] ; (8007000 <ETH_MACDMAConfig+0x388>)
8006d52: 4013 ands r3, r2
8006d54: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the IPCO bit according to ETH ChecksumOffload value */
/* Set the DR bit according to ETH RetryTransmission value */
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d58: 6cba ldr r2, [r7, #72] ; 0x48
macinit.Jabber |
8006d5a: 6cfb ldr r3, [r7, #76] ; 0x4c
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d5c: 431a orrs r2, r3
macinit.InterFrameGap |
8006d5e: 6d3b ldr r3, [r7, #80] ; 0x50
macinit.Jabber |
8006d60: 431a orrs r2, r3
macinit.CarrierSense |
8006d62: 6d7b ldr r3, [r7, #84] ; 0x54
macinit.InterFrameGap |
8006d64: 431a orrs r2, r3
(heth->Init).Speed |
8006d66: 687b ldr r3, [r7, #4]
8006d68: 689b ldr r3, [r3, #8]
macinit.CarrierSense |
8006d6a: 431a orrs r2, r3
macinit.ReceiveOwn |
8006d6c: 6dbb ldr r3, [r7, #88] ; 0x58
(heth->Init).Speed |
8006d6e: 431a orrs r2, r3
macinit.LoopbackMode |
8006d70: 6dfb ldr r3, [r7, #92] ; 0x5c
macinit.ReceiveOwn |
8006d72: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006d74: 687b ldr r3, [r7, #4]
8006d76: 68db ldr r3, [r3, #12]
macinit.LoopbackMode |
8006d78: 431a orrs r2, r3
macinit.ChecksumOffload |
8006d7a: 6e3b ldr r3, [r7, #96] ; 0x60
(heth->Init).DuplexMode |
8006d7c: 431a orrs r2, r3
macinit.RetryTransmission |
8006d7e: 6e7b ldr r3, [r7, #100] ; 0x64
macinit.ChecksumOffload |
8006d80: 431a orrs r2, r3
macinit.AutomaticPadCRCStrip |
8006d82: 6ebb ldr r3, [r7, #104] ; 0x68
macinit.RetryTransmission |
8006d84: 431a orrs r2, r3
macinit.BackOffLimit |
8006d86: 6efb ldr r3, [r7, #108] ; 0x6c
macinit.AutomaticPadCRCStrip |
8006d88: 431a orrs r2, r3
macinit.DeferralCheck);
8006d8a: 6f3b ldr r3, [r7, #112] ; 0x70
macinit.BackOffLimit |
8006d8c: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d8e: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d92: 4313 orrs r3, r2
8006d94: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006d98: 687b ldr r3, [r7, #4]
8006d9a: 681b ldr r3, [r3, #0]
8006d9c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006da0: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006da2: 687b ldr r3, [r7, #4]
8006da4: 681b ldr r3, [r3, #0]
8006da6: 681b ldr r3, [r3, #0]
8006da8: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006dac: 2001 movs r0, #1
8006dae: f7fd fdff bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006db2: 687b ldr r3, [r7, #4]
8006db4: 681b ldr r3, [r3, #0]
8006db6: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006dba: 601a str r2, [r3, #0]
/* Set the DAIF bit according to ETH DestinationAddrFilter value */
/* Set the PR bit according to ETH PromiscuousMode value */
/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dbc: 6f7a ldr r2, [r7, #116] ; 0x74
macinit.SourceAddrFilter |
8006dbe: 6fbb ldr r3, [r7, #120] ; 0x78
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dc0: 431a orrs r2, r3
macinit.PassControlFrames |
8006dc2: 6ffb ldr r3, [r7, #124] ; 0x7c
macinit.SourceAddrFilter |
8006dc4: 431a orrs r2, r3
macinit.BroadcastFramesReception |
8006dc6: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
macinit.PassControlFrames |
8006dca: 431a orrs r2, r3
macinit.DestinationAddrFilter |
8006dcc: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
macinit.BroadcastFramesReception |
8006dd0: 431a orrs r2, r3
macinit.PromiscuousMode |
8006dd2: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
macinit.DestinationAddrFilter |
8006dd6: 431a orrs r2, r3
macinit.MulticastFramesFilter |
8006dd8: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
macinit.PromiscuousMode |
8006ddc: ea42 0103 orr.w r1, r2, r3
macinit.UnicastFramesFilter);
8006de0: f8d7 2090 ldr.w r2, [r7, #144] ; 0x90
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006de4: 687b ldr r3, [r7, #4]
8006de6: 681b ldr r3, [r3, #0]
macinit.MulticastFramesFilter |
8006de8: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dea: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
8006dec: 687b ldr r3, [r7, #4]
8006dee: 681b ldr r3, [r3, #0]
8006df0: 685b ldr r3, [r3, #4]
8006df2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006df6: 2001 movs r0, #1
8006df8: f7fd fdda bl 80049b0 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006dfc: 687b ldr r3, [r7, #4]
8006dfe: 681b ldr r3, [r3, #0]
8006e00: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e04: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
8006e06: 687b ldr r3, [r7, #4]
8006e08: 681b ldr r3, [r3, #0]
8006e0a: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
8006e0e: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
8006e10: 687b ldr r3, [r7, #4]
8006e12: 681b ldr r3, [r3, #0]
8006e14: f8d7 2098 ldr.w r2, [r7, #152] ; 0x98
8006e18: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006e1a: 687b ldr r3, [r7, #4]
8006e1c: 681b ldr r3, [r3, #0]
8006e1e: 699b ldr r3, [r3, #24]
8006e20: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006e24: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e28: f64f 7341 movw r3, #65345 ; 0xff41
8006e2c: 4013 ands r3, r2
8006e2e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
/* Set the PLT bit according to ETH PauseLowThreshold value */
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e32: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8006e36: 041a lsls r2, r3, #16
macinit.ZeroQuantaPause |
8006e38: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e3c: 431a orrs r2, r3
macinit.PauseLowThreshold |
8006e3e: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
macinit.ZeroQuantaPause |
8006e42: 431a orrs r2, r3
macinit.UnicastPauseFrameDetect |
8006e44: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
macinit.PauseLowThreshold |
8006e48: 431a orrs r2, r3
macinit.ReceiveFlowControl |
8006e4a: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
macinit.UnicastPauseFrameDetect |
8006e4e: 431a orrs r2, r3
macinit.TransmitFlowControl);
8006e50: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
macinit.ReceiveFlowControl |
8006e54: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e56: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e5a: 4313 orrs r3, r2
8006e5c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006e60: 687b ldr r3, [r7, #4]
8006e62: 681b ldr r3, [r3, #0]
8006e64: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e68: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006e6a: 687b ldr r3, [r7, #4]
8006e6c: 681b ldr r3, [r3, #0]
8006e6e: 699b ldr r3, [r3, #24]
8006e70: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006e74: 2001 movs r0, #1
8006e76: f7fd fd9b bl 80049b0 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006e7a: 687b ldr r3, [r7, #4]
8006e7c: 681b ldr r3, [r3, #0]
8006e7e: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e82: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
/* Set the VL bit according to ETH VLANTagIdentifier value */
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006e84: f8d7 10b4 ldr.w r1, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier);
8006e88: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006e8c: 687b ldr r3, [r7, #4]
8006e8e: 681b ldr r3, [r3, #0]
8006e90: 430a orrs r2, r1
8006e92: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006e94: 687b ldr r3, [r7, #4]
8006e96: 681b ldr r3, [r3, #0]
8006e98: 69db ldr r3, [r3, #28]
8006e9a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006e9e: 2001 movs r0, #1
8006ea0: f7fd fd86 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006ea4: 687b ldr r3, [r7, #4]
8006ea6: 681b ldr r3, [r3, #0]
8006ea8: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006eac: 61da str r2, [r3, #28]
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
8006eae: 2300 movs r3, #0
8006eb0: 60bb str r3, [r7, #8]
dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
8006eb2: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006eb6: 60fb str r3, [r7, #12]
dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
8006eb8: 2300 movs r3, #0
8006eba: 613b str r3, [r7, #16]
dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
8006ebc: f44f 1300 mov.w r3, #2097152 ; 0x200000
8006ec0: 617b str r3, [r7, #20]
dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
8006ec2: 2300 movs r3, #0
8006ec4: 61bb str r3, [r7, #24]
dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
8006ec6: 2300 movs r3, #0
8006ec8: 61fb str r3, [r7, #28]
dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
8006eca: 2300 movs r3, #0
8006ecc: 623b str r3, [r7, #32]
dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
8006ece: 2300 movs r3, #0
8006ed0: 627b str r3, [r7, #36] ; 0x24
dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
8006ed2: 2304 movs r3, #4
8006ed4: 62bb str r3, [r7, #40] ; 0x28
dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
8006ed6: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006eda: 62fb str r3, [r7, #44] ; 0x2c
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
8006edc: f44f 3380 mov.w r3, #65536 ; 0x10000
8006ee0: 633b str r3, [r7, #48] ; 0x30
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
8006ee2: f44f 0380 mov.w r3, #4194304 ; 0x400000
8006ee6: 637b str r3, [r7, #52] ; 0x34
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
8006ee8: f44f 5300 mov.w r3, #8192 ; 0x2000
8006eec: 63bb str r3, [r7, #56] ; 0x38
dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
8006eee: 2380 movs r3, #128 ; 0x80
8006ef0: 63fb str r3, [r7, #60] ; 0x3c
dmainit.DescriptorSkipLength = 0x0;
8006ef2: 2300 movs r3, #0
8006ef4: 643b str r3, [r7, #64] ; 0x40
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
8006ef6: 2300 movs r3, #0
8006ef8: 647b str r3, [r7, #68] ; 0x44
/* Get the ETHERNET DMAOMR value */
tmpreg = (heth->Instance)->DMAOMR;
8006efa: 687b ldr r3, [r7, #4]
8006efc: 681a ldr r2, [r3, #0]
8006efe: f241 0318 movw r3, #4120 ; 0x1018
8006f02: 4413 add r3, r2
8006f04: 681b ldr r3, [r3, #0]
8006f06: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_DMAOMR_CLEAR_MASK;
8006f0a: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f0e: 4b3d ldr r3, [pc, #244] ; (8007004 <ETH_MACDMAConfig+0x38c>)
8006f10: 4013 ands r3, r2
8006f12: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the TTC bit according to ETH TransmitThresholdControl value */
/* Set the FEF bit according to ETH ForwardErrorFrames value */
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f16: 68ba ldr r2, [r7, #8]
dmainit.ReceiveStoreForward |
8006f18: 68fb ldr r3, [r7, #12]
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f1a: 431a orrs r2, r3
dmainit.FlushReceivedFrame |
8006f1c: 693b ldr r3, [r7, #16]
dmainit.ReceiveStoreForward |
8006f1e: 431a orrs r2, r3
dmainit.TransmitStoreForward |
8006f20: 697b ldr r3, [r7, #20]
dmainit.FlushReceivedFrame |
8006f22: 431a orrs r2, r3
dmainit.TransmitThresholdControl |
8006f24: 69bb ldr r3, [r7, #24]
dmainit.TransmitStoreForward |
8006f26: 431a orrs r2, r3
dmainit.ForwardErrorFrames |
8006f28: 69fb ldr r3, [r7, #28]
dmainit.TransmitThresholdControl |
8006f2a: 431a orrs r2, r3
dmainit.ForwardUndersizedGoodFrames |
8006f2c: 6a3b ldr r3, [r7, #32]
dmainit.ForwardErrorFrames |
8006f2e: 431a orrs r2, r3
dmainit.ReceiveThresholdControl |
8006f30: 6a7b ldr r3, [r7, #36] ; 0x24
dmainit.ForwardUndersizedGoodFrames |
8006f32: 431a orrs r2, r3
dmainit.SecondFrameOperate);
8006f34: 6abb ldr r3, [r7, #40] ; 0x28
dmainit.ReceiveThresholdControl |
8006f36: 4313 orrs r3, r2
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f38: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f3c: 4313 orrs r3, r2
8006f3e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
8006f42: 687b ldr r3, [r7, #4]
8006f44: 681a ldr r2, [r3, #0]
8006f46: f241 0318 movw r3, #4120 ; 0x1018
8006f4a: 4413 add r3, r2
8006f4c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f50: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
8006f52: 687b ldr r3, [r7, #4]
8006f54: 681a ldr r2, [r3, #0]
8006f56: f241 0318 movw r3, #4120 ; 0x1018
8006f5a: 4413 add r3, r2
8006f5c: 681b ldr r3, [r3, #0]
8006f5e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006f62: 2001 movs r0, #1
8006f64: f7fd fd24 bl 80049b0 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
8006f68: 687b ldr r3, [r7, #4]
8006f6a: 681a ldr r2, [r3, #0]
8006f6c: f241 0318 movw r3, #4120 ; 0x1018
8006f70: 4413 add r3, r2
8006f72: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f76: 601a str r2, [r3, #0]
/* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
/* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
/* Set the DSL bit according to ETH DesciptorSkipLength value */
/* Set the PR and DA bits according to ETH DMAArbitration value */
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f78: 6afa ldr r2, [r7, #44] ; 0x2c
dmainit.FixedBurst |
8006f7a: 6b3b ldr r3, [r7, #48] ; 0x30
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f7c: 431a orrs r2, r3
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006f7e: 6b7b ldr r3, [r7, #52] ; 0x34
dmainit.FixedBurst |
8006f80: 431a orrs r2, r3
dmainit.TxDMABurstLength |
8006f82: 6bbb ldr r3, [r7, #56] ; 0x38
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006f84: 431a orrs r2, r3
dmainit.EnhancedDescriptorFormat |
8006f86: 6bfb ldr r3, [r7, #60] ; 0x3c
dmainit.TxDMABurstLength |
8006f88: 431a orrs r2, r3
(dmainit.DescriptorSkipLength << 2) |
8006f8a: 6c3b ldr r3, [r7, #64] ; 0x40
8006f8c: 009b lsls r3, r3, #2
dmainit.EnhancedDescriptorFormat |
8006f8e: 431a orrs r2, r3
dmainit.DMAArbitration |
8006f90: 6c7b ldr r3, [r7, #68] ; 0x44
(dmainit.DescriptorSkipLength << 2) |
8006f92: 431a orrs r2, r3
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f94: 687b ldr r3, [r7, #4]
8006f96: 681b ldr r3, [r3, #0]
8006f98: f442 0200 orr.w r2, r2, #8388608 ; 0x800000
8006f9c: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006fa0: 601a str r2, [r3, #0]
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMABMR;
8006fa2: 687b ldr r3, [r7, #4]
8006fa4: 681b ldr r3, [r3, #0]
8006fa6: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006faa: 681b ldr r3, [r3, #0]
8006fac: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006fb0: 2001 movs r0, #1
8006fb2: f7fd fcfd bl 80049b0 <HAL_Delay>
(heth->Instance)->DMABMR = tmpreg;
8006fb6: 687b ldr r3, [r7, #4]
8006fb8: 681b ldr r3, [r3, #0]
8006fba: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006fbe: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006fc2: 601a str r2, [r3, #0]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
8006fc4: 687b ldr r3, [r7, #4]
8006fc6: 699b ldr r3, [r3, #24]
8006fc8: 2b01 cmp r3, #1
8006fca: d10d bne.n 8006fe8 <ETH_MACDMAConfig+0x370>
{
/* Enable the Ethernet Rx Interrupt */
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
8006fcc: 687b ldr r3, [r7, #4]
8006fce: 681a ldr r2, [r3, #0]
8006fd0: f241 031c movw r3, #4124 ; 0x101c
8006fd4: 4413 add r3, r2
8006fd6: 681b ldr r3, [r3, #0]
8006fd8: 687a ldr r2, [r7, #4]
8006fda: 6811 ldr r1, [r2, #0]
8006fdc: 4a0a ldr r2, [pc, #40] ; (8007008 <ETH_MACDMAConfig+0x390>)
8006fde: 431a orrs r2, r3
8006fe0: f241 031c movw r3, #4124 ; 0x101c
8006fe4: 440b add r3, r1
8006fe6: 601a str r2, [r3, #0]
}
/* Initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
8006fe8: 687b ldr r3, [r7, #4]
8006fea: 695b ldr r3, [r3, #20]
8006fec: 461a mov r2, r3
8006fee: 2100 movs r1, #0
8006ff0: 6878 ldr r0, [r7, #4]
8006ff2: f000 f80b bl 800700c <ETH_MACAddressConfig>
}
8006ff6: bf00 nop
8006ff8: 37c0 adds r7, #192 ; 0xc0
8006ffa: 46bd mov sp, r7
8006ffc: bd80 pop {r7, pc}
8006ffe: bf00 nop
8007000: ff20810f .word 0xff20810f
8007004: f8de3f23 .word 0xf8de3f23
8007008: 00010040 .word 0x00010040
0800700c <ETH_MACAddressConfig>:
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
800700c: b480 push {r7}
800700e: b087 sub sp, #28
8007010: af00 add r7, sp, #0
8007012: 60f8 str r0, [r7, #12]
8007014: 60b9 str r1, [r7, #8]
8007016: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
8007018: 687b ldr r3, [r7, #4]
800701a: 3305 adds r3, #5
800701c: 781b ldrb r3, [r3, #0]
800701e: 021b lsls r3, r3, #8
8007020: 687a ldr r2, [r7, #4]
8007022: 3204 adds r2, #4
8007024: 7812 ldrb r2, [r2, #0]
8007026: 4313 orrs r3, r2
8007028: 617b str r3, [r7, #20]
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
800702a: 68ba ldr r2, [r7, #8]
800702c: 4b11 ldr r3, [pc, #68] ; (8007074 <ETH_MACAddressConfig+0x68>)
800702e: 4413 add r3, r2
8007030: 461a mov r2, r3
8007032: 697b ldr r3, [r7, #20]
8007034: 6013 str r3, [r2, #0]
/* Calculate the selected MAC address low register */
tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
8007036: 687b ldr r3, [r7, #4]
8007038: 3303 adds r3, #3
800703a: 781b ldrb r3, [r3, #0]
800703c: 061a lsls r2, r3, #24
800703e: 687b ldr r3, [r7, #4]
8007040: 3302 adds r3, #2
8007042: 781b ldrb r3, [r3, #0]
8007044: 041b lsls r3, r3, #16
8007046: 431a orrs r2, r3
8007048: 687b ldr r3, [r7, #4]
800704a: 3301 adds r3, #1
800704c: 781b ldrb r3, [r3, #0]
800704e: 021b lsls r3, r3, #8
8007050: 4313 orrs r3, r2
8007052: 687a ldr r2, [r7, #4]
8007054: 7812 ldrb r2, [r2, #0]
8007056: 4313 orrs r3, r2
8007058: 617b str r3, [r7, #20]
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
800705a: 68ba ldr r2, [r7, #8]
800705c: 4b06 ldr r3, [pc, #24] ; (8007078 <ETH_MACAddressConfig+0x6c>)
800705e: 4413 add r3, r2
8007060: 461a mov r2, r3
8007062: 697b ldr r3, [r7, #20]
8007064: 6013 str r3, [r2, #0]
}
8007066: bf00 nop
8007068: 371c adds r7, #28
800706a: 46bd mov sp, r7
800706c: f85d 7b04 ldr.w r7, [sp], #4
8007070: 4770 bx lr
8007072: bf00 nop
8007074: 40028040 .word 0x40028040
8007078: 40028044 .word 0x40028044
0800707c <ETH_MACTransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
800707c: b580 push {r7, lr}
800707e: b084 sub sp, #16
8007080: af00 add r7, sp, #0
8007082: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8007084: 2300 movs r3, #0
8007086: 60fb str r3, [r7, #12]
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
8007088: 687b ldr r3, [r7, #4]
800708a: 681b ldr r3, [r3, #0]
800708c: 681a ldr r2, [r3, #0]
800708e: 687b ldr r3, [r7, #4]
8007090: 681b ldr r3, [r3, #0]
8007092: f042 0208 orr.w r2, r2, #8
8007096: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8007098: 687b ldr r3, [r7, #4]
800709a: 681b ldr r3, [r3, #0]
800709c: 681b ldr r3, [r3, #0]
800709e: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80070a0: 2001 movs r0, #1
80070a2: f7fd fc85 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
80070a6: 687b ldr r3, [r7, #4]
80070a8: 681b ldr r3, [r3, #0]
80070aa: 68fa ldr r2, [r7, #12]
80070ac: 601a str r2, [r3, #0]
}
80070ae: bf00 nop
80070b0: 3710 adds r7, #16
80070b2: 46bd mov sp, r7
80070b4: bd80 pop {r7, pc}
080070b6 <ETH_MACTransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
80070b6: b580 push {r7, lr}
80070b8: b084 sub sp, #16
80070ba: af00 add r7, sp, #0
80070bc: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
80070be: 2300 movs r3, #0
80070c0: 60fb str r3, [r7, #12]
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
80070c2: 687b ldr r3, [r7, #4]
80070c4: 681b ldr r3, [r3, #0]
80070c6: 681a ldr r2, [r3, #0]
80070c8: 687b ldr r3, [r7, #4]
80070ca: 681b ldr r3, [r3, #0]
80070cc: f022 0208 bic.w r2, r2, #8
80070d0: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
80070d2: 687b ldr r3, [r7, #4]
80070d4: 681b ldr r3, [r3, #0]
80070d6: 681b ldr r3, [r3, #0]
80070d8: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80070da: 2001 movs r0, #1
80070dc: f7fd fc68 bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
80070e0: 687b ldr r3, [r7, #4]
80070e2: 681b ldr r3, [r3, #0]
80070e4: 68fa ldr r2, [r7, #12]
80070e6: 601a str r2, [r3, #0]
}
80070e8: bf00 nop
80070ea: 3710 adds r7, #16
80070ec: 46bd mov sp, r7
80070ee: bd80 pop {r7, pc}
080070f0 <ETH_MACReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
80070f0: b580 push {r7, lr}
80070f2: b084 sub sp, #16
80070f4: af00 add r7, sp, #0
80070f6: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
80070f8: 2300 movs r3, #0
80070fa: 60fb str r3, [r7, #12]
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
80070fc: 687b ldr r3, [r7, #4]
80070fe: 681b ldr r3, [r3, #0]
8007100: 681a ldr r2, [r3, #0]
8007102: 687b ldr r3, [r7, #4]
8007104: 681b ldr r3, [r3, #0]
8007106: f042 0204 orr.w r2, r2, #4
800710a: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
800710c: 687b ldr r3, [r7, #4]
800710e: 681b ldr r3, [r3, #0]
8007110: 681b ldr r3, [r3, #0]
8007112: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8007114: 2001 movs r0, #1
8007116: f7fd fc4b bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
800711a: 687b ldr r3, [r7, #4]
800711c: 681b ldr r3, [r3, #0]
800711e: 68fa ldr r2, [r7, #12]
8007120: 601a str r2, [r3, #0]
}
8007122: bf00 nop
8007124: 3710 adds r7, #16
8007126: 46bd mov sp, r7
8007128: bd80 pop {r7, pc}
0800712a <ETH_MACReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
800712a: b580 push {r7, lr}
800712c: b084 sub sp, #16
800712e: af00 add r7, sp, #0
8007130: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8007132: 2300 movs r3, #0
8007134: 60fb str r3, [r7, #12]
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
8007136: 687b ldr r3, [r7, #4]
8007138: 681b ldr r3, [r3, #0]
800713a: 681a ldr r2, [r3, #0]
800713c: 687b ldr r3, [r7, #4]
800713e: 681b ldr r3, [r3, #0]
8007140: f022 0204 bic.w r2, r2, #4
8007144: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8007146: 687b ldr r3, [r7, #4]
8007148: 681b ldr r3, [r3, #0]
800714a: 681b ldr r3, [r3, #0]
800714c: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
800714e: 2001 movs r0, #1
8007150: f7fd fc2e bl 80049b0 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8007154: 687b ldr r3, [r7, #4]
8007156: 681b ldr r3, [r3, #0]
8007158: 68fa ldr r2, [r7, #12]
800715a: 601a str r2, [r3, #0]
}
800715c: bf00 nop
800715e: 3710 adds r7, #16
8007160: 46bd mov sp, r7
8007162: bd80 pop {r7, pc}
08007164 <ETH_DMATransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
{
8007164: b480 push {r7}
8007166: b083 sub sp, #12
8007168: af00 add r7, sp, #0
800716a: 6078 str r0, [r7, #4]
/* Enable the DMA transmission */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
800716c: 687b ldr r3, [r7, #4]
800716e: 681a ldr r2, [r3, #0]
8007170: f241 0318 movw r3, #4120 ; 0x1018
8007174: 4413 add r3, r2
8007176: 681b ldr r3, [r3, #0]
8007178: 687a ldr r2, [r7, #4]
800717a: 6811 ldr r1, [r2, #0]
800717c: f443 5200 orr.w r2, r3, #8192 ; 0x2000
8007180: f241 0318 movw r3, #4120 ; 0x1018
8007184: 440b add r3, r1
8007186: 601a str r2, [r3, #0]
}
8007188: bf00 nop
800718a: 370c adds r7, #12
800718c: 46bd mov sp, r7
800718e: f85d 7b04 ldr.w r7, [sp], #4
8007192: 4770 bx lr
08007194 <ETH_DMATransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
{
8007194: b480 push {r7}
8007196: b083 sub sp, #12
8007198: af00 add r7, sp, #0
800719a: 6078 str r0, [r7, #4]
/* Disable the DMA transmission */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
800719c: 687b ldr r3, [r7, #4]
800719e: 681a ldr r2, [r3, #0]
80071a0: f241 0318 movw r3, #4120 ; 0x1018
80071a4: 4413 add r3, r2
80071a6: 681b ldr r3, [r3, #0]
80071a8: 687a ldr r2, [r7, #4]
80071aa: 6811 ldr r1, [r2, #0]
80071ac: f423 5200 bic.w r2, r3, #8192 ; 0x2000
80071b0: f241 0318 movw r3, #4120 ; 0x1018
80071b4: 440b add r3, r1
80071b6: 601a str r2, [r3, #0]
}
80071b8: bf00 nop
80071ba: 370c adds r7, #12
80071bc: 46bd mov sp, r7
80071be: f85d 7b04 ldr.w r7, [sp], #4
80071c2: 4770 bx lr
080071c4 <ETH_DMAReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
{
80071c4: b480 push {r7}
80071c6: b083 sub sp, #12
80071c8: af00 add r7, sp, #0
80071ca: 6078 str r0, [r7, #4]
/* Enable the DMA reception */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
80071cc: 687b ldr r3, [r7, #4]
80071ce: 681a ldr r2, [r3, #0]
80071d0: f241 0318 movw r3, #4120 ; 0x1018
80071d4: 4413 add r3, r2
80071d6: 681b ldr r3, [r3, #0]
80071d8: 687a ldr r2, [r7, #4]
80071da: 6811 ldr r1, [r2, #0]
80071dc: f043 0202 orr.w r2, r3, #2
80071e0: f241 0318 movw r3, #4120 ; 0x1018
80071e4: 440b add r3, r1
80071e6: 601a str r2, [r3, #0]
}
80071e8: bf00 nop
80071ea: 370c adds r7, #12
80071ec: 46bd mov sp, r7
80071ee: f85d 7b04 ldr.w r7, [sp], #4
80071f2: 4770 bx lr
080071f4 <ETH_DMAReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
{
80071f4: b480 push {r7}
80071f6: b083 sub sp, #12
80071f8: af00 add r7, sp, #0
80071fa: 6078 str r0, [r7, #4]
/* Disable the DMA reception */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
80071fc: 687b ldr r3, [r7, #4]
80071fe: 681a ldr r2, [r3, #0]
8007200: f241 0318 movw r3, #4120 ; 0x1018
8007204: 4413 add r3, r2
8007206: 681b ldr r3, [r3, #0]
8007208: 687a ldr r2, [r7, #4]
800720a: 6811 ldr r1, [r2, #0]
800720c: f023 0202 bic.w r2, r3, #2
8007210: f241 0318 movw r3, #4120 ; 0x1018
8007214: 440b add r3, r1
8007216: 601a str r2, [r3, #0]
}
8007218: bf00 nop
800721a: 370c adds r7, #12
800721c: 46bd mov sp, r7
800721e: f85d 7b04 ldr.w r7, [sp], #4
8007222: 4770 bx lr
08007224 <ETH_FlushTransmitFIFO>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
8007224: b580 push {r7, lr}
8007226: b084 sub sp, #16
8007228: af00 add r7, sp, #0
800722a: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
800722c: 2300 movs r3, #0
800722e: 60fb str r3, [r7, #12]
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
8007230: 687b ldr r3, [r7, #4]
8007232: 681a ldr r2, [r3, #0]
8007234: f241 0318 movw r3, #4120 ; 0x1018
8007238: 4413 add r3, r2
800723a: 681b ldr r3, [r3, #0]
800723c: 687a ldr r2, [r7, #4]
800723e: 6811 ldr r1, [r2, #0]
8007240: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
8007244: f241 0318 movw r3, #4120 ; 0x1018
8007248: 440b add r3, r1
800724a: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
800724c: 687b ldr r3, [r7, #4]
800724e: 681a ldr r2, [r3, #0]
8007250: f241 0318 movw r3, #4120 ; 0x1018
8007254: 4413 add r3, r2
8007256: 681b ldr r3, [r3, #0]
8007258: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
800725a: 2001 movs r0, #1
800725c: f7fd fba8 bl 80049b0 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
8007260: 687b ldr r3, [r7, #4]
8007262: 6819 ldr r1, [r3, #0]
8007264: 68fa ldr r2, [r7, #12]
8007266: f241 0318 movw r3, #4120 ; 0x1018
800726a: 440b add r3, r1
800726c: 601a str r2, [r3, #0]
}
800726e: bf00 nop
8007270: 3710 adds r7, #16
8007272: 46bd mov sp, r7
8007274: bd80 pop {r7, pc}
...
08007278 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8007278: b480 push {r7}
800727a: b089 sub sp, #36 ; 0x24
800727c: af00 add r7, sp, #0
800727e: 6078 str r0, [r7, #4]
8007280: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
8007282: 2300 movs r3, #0
8007284: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
8007286: 2300 movs r3, #0
8007288: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
800728a: 2300 movs r3, #0
800728c: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
800728e: 2300 movs r3, #0
8007290: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
8007292: 2300 movs r3, #0
8007294: 61fb str r3, [r7, #28]
8007296: e175 b.n 8007584 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8007298: 2201 movs r2, #1
800729a: 69fb ldr r3, [r7, #28]
800729c: fa02 f303 lsl.w r3, r2, r3
80072a0: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80072a2: 683b ldr r3, [r7, #0]
80072a4: 681b ldr r3, [r3, #0]
80072a6: 697a ldr r2, [r7, #20]
80072a8: 4013 ands r3, r2
80072aa: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80072ac: 693a ldr r2, [r7, #16]
80072ae: 697b ldr r3, [r7, #20]
80072b0: 429a cmp r2, r3
80072b2: f040 8164 bne.w 800757e <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
80072b6: 683b ldr r3, [r7, #0]
80072b8: 685b ldr r3, [r3, #4]
80072ba: 2b01 cmp r3, #1
80072bc: d00b beq.n 80072d6 <HAL_GPIO_Init+0x5e>
80072be: 683b ldr r3, [r7, #0]
80072c0: 685b ldr r3, [r3, #4]
80072c2: 2b02 cmp r3, #2
80072c4: d007 beq.n 80072d6 <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80072c6: 683b ldr r3, [r7, #0]
80072c8: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
80072ca: 2b11 cmp r3, #17
80072cc: d003 beq.n 80072d6 <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80072ce: 683b ldr r3, [r7, #0]
80072d0: 685b ldr r3, [r3, #4]
80072d2: 2b12 cmp r3, #18
80072d4: d130 bne.n 8007338 <HAL_GPIO_Init+0xc0>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80072d6: 687b ldr r3, [r7, #4]
80072d8: 689b ldr r3, [r3, #8]
80072da: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
80072dc: 69fb ldr r3, [r7, #28]
80072de: 005b lsls r3, r3, #1
80072e0: 2203 movs r2, #3
80072e2: fa02 f303 lsl.w r3, r2, r3
80072e6: 43db mvns r3, r3
80072e8: 69ba ldr r2, [r7, #24]
80072ea: 4013 ands r3, r2
80072ec: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
80072ee: 683b ldr r3, [r7, #0]
80072f0: 68da ldr r2, [r3, #12]
80072f2: 69fb ldr r3, [r7, #28]
80072f4: 005b lsls r3, r3, #1
80072f6: fa02 f303 lsl.w r3, r2, r3
80072fa: 69ba ldr r2, [r7, #24]
80072fc: 4313 orrs r3, r2
80072fe: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8007300: 687b ldr r3, [r7, #4]
8007302: 69ba ldr r2, [r7, #24]
8007304: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8007306: 687b ldr r3, [r7, #4]
8007308: 685b ldr r3, [r3, #4]
800730a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
800730c: 2201 movs r2, #1
800730e: 69fb ldr r3, [r7, #28]
8007310: fa02 f303 lsl.w r3, r2, r3
8007314: 43db mvns r3, r3
8007316: 69ba ldr r2, [r7, #24]
8007318: 4013 ands r3, r2
800731a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
800731c: 683b ldr r3, [r7, #0]
800731e: 685b ldr r3, [r3, #4]
8007320: 091b lsrs r3, r3, #4
8007322: f003 0201 and.w r2, r3, #1
8007326: 69fb ldr r3, [r7, #28]
8007328: fa02 f303 lsl.w r3, r2, r3
800732c: 69ba ldr r2, [r7, #24]
800732e: 4313 orrs r3, r2
8007330: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8007332: 687b ldr r3, [r7, #4]
8007334: 69ba ldr r2, [r7, #24]
8007336: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8007338: 687b ldr r3, [r7, #4]
800733a: 68db ldr r3, [r3, #12]
800733c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
800733e: 69fb ldr r3, [r7, #28]
8007340: 005b lsls r3, r3, #1
8007342: 2203 movs r2, #3
8007344: fa02 f303 lsl.w r3, r2, r3
8007348: 43db mvns r3, r3
800734a: 69ba ldr r2, [r7, #24]
800734c: 4013 ands r3, r2
800734e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
8007350: 683b ldr r3, [r7, #0]
8007352: 689a ldr r2, [r3, #8]
8007354: 69fb ldr r3, [r7, #28]
8007356: 005b lsls r3, r3, #1
8007358: fa02 f303 lsl.w r3, r2, r3
800735c: 69ba ldr r2, [r7, #24]
800735e: 4313 orrs r3, r2
8007360: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8007362: 687b ldr r3, [r7, #4]
8007364: 69ba ldr r2, [r7, #24]
8007366: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8007368: 683b ldr r3, [r7, #0]
800736a: 685b ldr r3, [r3, #4]
800736c: 2b02 cmp r3, #2
800736e: d003 beq.n 8007378 <HAL_GPIO_Init+0x100>
8007370: 683b ldr r3, [r7, #0]
8007372: 685b ldr r3, [r3, #4]
8007374: 2b12 cmp r3, #18
8007376: d123 bne.n 80073c0 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
8007378: 69fb ldr r3, [r7, #28]
800737a: 08da lsrs r2, r3, #3
800737c: 687b ldr r3, [r7, #4]
800737e: 3208 adds r2, #8
8007380: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8007384: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
8007386: 69fb ldr r3, [r7, #28]
8007388: f003 0307 and.w r3, r3, #7
800738c: 009b lsls r3, r3, #2
800738e: 220f movs r2, #15
8007390: fa02 f303 lsl.w r3, r2, r3
8007394: 43db mvns r3, r3
8007396: 69ba ldr r2, [r7, #24]
8007398: 4013 ands r3, r2
800739a: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
800739c: 683b ldr r3, [r7, #0]
800739e: 691a ldr r2, [r3, #16]
80073a0: 69fb ldr r3, [r7, #28]
80073a2: f003 0307 and.w r3, r3, #7
80073a6: 009b lsls r3, r3, #2
80073a8: fa02 f303 lsl.w r3, r2, r3
80073ac: 69ba ldr r2, [r7, #24]
80073ae: 4313 orrs r3, r2
80073b0: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
80073b2: 69fb ldr r3, [r7, #28]
80073b4: 08da lsrs r2, r3, #3
80073b6: 687b ldr r3, [r7, #4]
80073b8: 3208 adds r2, #8
80073ba: 69b9 ldr r1, [r7, #24]
80073bc: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80073c0: 687b ldr r3, [r7, #4]
80073c2: 681b ldr r3, [r3, #0]
80073c4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
80073c6: 69fb ldr r3, [r7, #28]
80073c8: 005b lsls r3, r3, #1
80073ca: 2203 movs r2, #3
80073cc: fa02 f303 lsl.w r3, r2, r3
80073d0: 43db mvns r3, r3
80073d2: 69ba ldr r2, [r7, #24]
80073d4: 4013 ands r3, r2
80073d6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
80073d8: 683b ldr r3, [r7, #0]
80073da: 685b ldr r3, [r3, #4]
80073dc: f003 0203 and.w r2, r3, #3
80073e0: 69fb ldr r3, [r7, #28]
80073e2: 005b lsls r3, r3, #1
80073e4: fa02 f303 lsl.w r3, r2, r3
80073e8: 69ba ldr r2, [r7, #24]
80073ea: 4313 orrs r3, r2
80073ec: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
80073ee: 687b ldr r3, [r7, #4]
80073f0: 69ba ldr r2, [r7, #24]
80073f2: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80073f4: 683b ldr r3, [r7, #0]
80073f6: 685b ldr r3, [r3, #4]
80073f8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80073fc: 2b00 cmp r3, #0
80073fe: f000 80be beq.w 800757e <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8007402: 4b65 ldr r3, [pc, #404] ; (8007598 <HAL_GPIO_Init+0x320>)
8007404: 6c5b ldr r3, [r3, #68] ; 0x44
8007406: 4a64 ldr r2, [pc, #400] ; (8007598 <HAL_GPIO_Init+0x320>)
8007408: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800740c: 6453 str r3, [r2, #68] ; 0x44
800740e: 4b62 ldr r3, [pc, #392] ; (8007598 <HAL_GPIO_Init+0x320>)
8007410: 6c5b ldr r3, [r3, #68] ; 0x44
8007412: f403 4380 and.w r3, r3, #16384 ; 0x4000
8007416: 60fb str r3, [r7, #12]
8007418: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
800741a: 4a60 ldr r2, [pc, #384] ; (800759c <HAL_GPIO_Init+0x324>)
800741c: 69fb ldr r3, [r7, #28]
800741e: 089b lsrs r3, r3, #2
8007420: 3302 adds r3, #2
8007422: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8007426: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8007428: 69fb ldr r3, [r7, #28]
800742a: f003 0303 and.w r3, r3, #3
800742e: 009b lsls r3, r3, #2
8007430: 220f movs r2, #15
8007432: fa02 f303 lsl.w r3, r2, r3
8007436: 43db mvns r3, r3
8007438: 69ba ldr r2, [r7, #24]
800743a: 4013 ands r3, r2
800743c: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
800743e: 687b ldr r3, [r7, #4]
8007440: 4a57 ldr r2, [pc, #348] ; (80075a0 <HAL_GPIO_Init+0x328>)
8007442: 4293 cmp r3, r2
8007444: d037 beq.n 80074b6 <HAL_GPIO_Init+0x23e>
8007446: 687b ldr r3, [r7, #4]
8007448: 4a56 ldr r2, [pc, #344] ; (80075a4 <HAL_GPIO_Init+0x32c>)
800744a: 4293 cmp r3, r2
800744c: d031 beq.n 80074b2 <HAL_GPIO_Init+0x23a>
800744e: 687b ldr r3, [r7, #4]
8007450: 4a55 ldr r2, [pc, #340] ; (80075a8 <HAL_GPIO_Init+0x330>)
8007452: 4293 cmp r3, r2
8007454: d02b beq.n 80074ae <HAL_GPIO_Init+0x236>
8007456: 687b ldr r3, [r7, #4]
8007458: 4a54 ldr r2, [pc, #336] ; (80075ac <HAL_GPIO_Init+0x334>)
800745a: 4293 cmp r3, r2
800745c: d025 beq.n 80074aa <HAL_GPIO_Init+0x232>
800745e: 687b ldr r3, [r7, #4]
8007460: 4a53 ldr r2, [pc, #332] ; (80075b0 <HAL_GPIO_Init+0x338>)
8007462: 4293 cmp r3, r2
8007464: d01f beq.n 80074a6 <HAL_GPIO_Init+0x22e>
8007466: 687b ldr r3, [r7, #4]
8007468: 4a52 ldr r2, [pc, #328] ; (80075b4 <HAL_GPIO_Init+0x33c>)
800746a: 4293 cmp r3, r2
800746c: d019 beq.n 80074a2 <HAL_GPIO_Init+0x22a>
800746e: 687b ldr r3, [r7, #4]
8007470: 4a51 ldr r2, [pc, #324] ; (80075b8 <HAL_GPIO_Init+0x340>)
8007472: 4293 cmp r3, r2
8007474: d013 beq.n 800749e <HAL_GPIO_Init+0x226>
8007476: 687b ldr r3, [r7, #4]
8007478: 4a50 ldr r2, [pc, #320] ; (80075bc <HAL_GPIO_Init+0x344>)
800747a: 4293 cmp r3, r2
800747c: d00d beq.n 800749a <HAL_GPIO_Init+0x222>
800747e: 687b ldr r3, [r7, #4]
8007480: 4a4f ldr r2, [pc, #316] ; (80075c0 <HAL_GPIO_Init+0x348>)
8007482: 4293 cmp r3, r2
8007484: d007 beq.n 8007496 <HAL_GPIO_Init+0x21e>
8007486: 687b ldr r3, [r7, #4]
8007488: 4a4e ldr r2, [pc, #312] ; (80075c4 <HAL_GPIO_Init+0x34c>)
800748a: 4293 cmp r3, r2
800748c: d101 bne.n 8007492 <HAL_GPIO_Init+0x21a>
800748e: 2309 movs r3, #9
8007490: e012 b.n 80074b8 <HAL_GPIO_Init+0x240>
8007492: 230a movs r3, #10
8007494: e010 b.n 80074b8 <HAL_GPIO_Init+0x240>
8007496: 2308 movs r3, #8
8007498: e00e b.n 80074b8 <HAL_GPIO_Init+0x240>
800749a: 2307 movs r3, #7
800749c: e00c b.n 80074b8 <HAL_GPIO_Init+0x240>
800749e: 2306 movs r3, #6
80074a0: e00a b.n 80074b8 <HAL_GPIO_Init+0x240>
80074a2: 2305 movs r3, #5
80074a4: e008 b.n 80074b8 <HAL_GPIO_Init+0x240>
80074a6: 2304 movs r3, #4
80074a8: e006 b.n 80074b8 <HAL_GPIO_Init+0x240>
80074aa: 2303 movs r3, #3
80074ac: e004 b.n 80074b8 <HAL_GPIO_Init+0x240>
80074ae: 2302 movs r3, #2
80074b0: e002 b.n 80074b8 <HAL_GPIO_Init+0x240>
80074b2: 2301 movs r3, #1
80074b4: e000 b.n 80074b8 <HAL_GPIO_Init+0x240>
80074b6: 2300 movs r3, #0
80074b8: 69fa ldr r2, [r7, #28]
80074ba: f002 0203 and.w r2, r2, #3
80074be: 0092 lsls r2, r2, #2
80074c0: 4093 lsls r3, r2
80074c2: 69ba ldr r2, [r7, #24]
80074c4: 4313 orrs r3, r2
80074c6: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
80074c8: 4934 ldr r1, [pc, #208] ; (800759c <HAL_GPIO_Init+0x324>)
80074ca: 69fb ldr r3, [r7, #28]
80074cc: 089b lsrs r3, r3, #2
80074ce: 3302 adds r3, #2
80074d0: 69ba ldr r2, [r7, #24]
80074d2: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80074d6: 4b3c ldr r3, [pc, #240] ; (80075c8 <HAL_GPIO_Init+0x350>)
80074d8: 681b ldr r3, [r3, #0]
80074da: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80074dc: 693b ldr r3, [r7, #16]
80074de: 43db mvns r3, r3
80074e0: 69ba ldr r2, [r7, #24]
80074e2: 4013 ands r3, r2
80074e4: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80074e6: 683b ldr r3, [r7, #0]
80074e8: 685b ldr r3, [r3, #4]
80074ea: f403 3380 and.w r3, r3, #65536 ; 0x10000
80074ee: 2b00 cmp r3, #0
80074f0: d003 beq.n 80074fa <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
80074f2: 69ba ldr r2, [r7, #24]
80074f4: 693b ldr r3, [r7, #16]
80074f6: 4313 orrs r3, r2
80074f8: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80074fa: 4a33 ldr r2, [pc, #204] ; (80075c8 <HAL_GPIO_Init+0x350>)
80074fc: 69bb ldr r3, [r7, #24]
80074fe: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8007500: 4b31 ldr r3, [pc, #196] ; (80075c8 <HAL_GPIO_Init+0x350>)
8007502: 685b ldr r3, [r3, #4]
8007504: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8007506: 693b ldr r3, [r7, #16]
8007508: 43db mvns r3, r3
800750a: 69ba ldr r2, [r7, #24]
800750c: 4013 ands r3, r2
800750e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8007510: 683b ldr r3, [r7, #0]
8007512: 685b ldr r3, [r3, #4]
8007514: f403 3300 and.w r3, r3, #131072 ; 0x20000
8007518: 2b00 cmp r3, #0
800751a: d003 beq.n 8007524 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
800751c: 69ba ldr r2, [r7, #24]
800751e: 693b ldr r3, [r7, #16]
8007520: 4313 orrs r3, r2
8007522: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8007524: 4a28 ldr r2, [pc, #160] ; (80075c8 <HAL_GPIO_Init+0x350>)
8007526: 69bb ldr r3, [r7, #24]
8007528: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
800752a: 4b27 ldr r3, [pc, #156] ; (80075c8 <HAL_GPIO_Init+0x350>)
800752c: 689b ldr r3, [r3, #8]
800752e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8007530: 693b ldr r3, [r7, #16]
8007532: 43db mvns r3, r3
8007534: 69ba ldr r2, [r7, #24]
8007536: 4013 ands r3, r2
8007538: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
800753a: 683b ldr r3, [r7, #0]
800753c: 685b ldr r3, [r3, #4]
800753e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8007542: 2b00 cmp r3, #0
8007544: d003 beq.n 800754e <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8007546: 69ba ldr r2, [r7, #24]
8007548: 693b ldr r3, [r7, #16]
800754a: 4313 orrs r3, r2
800754c: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
800754e: 4a1e ldr r2, [pc, #120] ; (80075c8 <HAL_GPIO_Init+0x350>)
8007550: 69bb ldr r3, [r7, #24]
8007552: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8007554: 4b1c ldr r3, [pc, #112] ; (80075c8 <HAL_GPIO_Init+0x350>)
8007556: 68db ldr r3, [r3, #12]
8007558: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800755a: 693b ldr r3, [r7, #16]
800755c: 43db mvns r3, r3
800755e: 69ba ldr r2, [r7, #24]
8007560: 4013 ands r3, r2
8007562: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8007564: 683b ldr r3, [r7, #0]
8007566: 685b ldr r3, [r3, #4]
8007568: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800756c: 2b00 cmp r3, #0
800756e: d003 beq.n 8007578 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8007570: 69ba ldr r2, [r7, #24]
8007572: 693b ldr r3, [r7, #16]
8007574: 4313 orrs r3, r2
8007576: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8007578: 4a13 ldr r2, [pc, #76] ; (80075c8 <HAL_GPIO_Init+0x350>)
800757a: 69bb ldr r3, [r7, #24]
800757c: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
800757e: 69fb ldr r3, [r7, #28]
8007580: 3301 adds r3, #1
8007582: 61fb str r3, [r7, #28]
8007584: 69fb ldr r3, [r7, #28]
8007586: 2b0f cmp r3, #15
8007588: f67f ae86 bls.w 8007298 <HAL_GPIO_Init+0x20>
}
}
}
}
800758c: bf00 nop
800758e: 3724 adds r7, #36 ; 0x24
8007590: 46bd mov sp, r7
8007592: f85d 7b04 ldr.w r7, [sp], #4
8007596: 4770 bx lr
8007598: 40023800 .word 0x40023800
800759c: 40013800 .word 0x40013800
80075a0: 40020000 .word 0x40020000
80075a4: 40020400 .word 0x40020400
80075a8: 40020800 .word 0x40020800
80075ac: 40020c00 .word 0x40020c00
80075b0: 40021000 .word 0x40021000
80075b4: 40021400 .word 0x40021400
80075b8: 40021800 .word 0x40021800
80075bc: 40021c00 .word 0x40021c00
80075c0: 40022000 .word 0x40022000
80075c4: 40022400 .word 0x40022400
80075c8: 40013c00 .word 0x40013c00
080075cc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80075cc: b480 push {r7}
80075ce: b083 sub sp, #12
80075d0: af00 add r7, sp, #0
80075d2: 6078 str r0, [r7, #4]
80075d4: 460b mov r3, r1
80075d6: 807b strh r3, [r7, #2]
80075d8: 4613 mov r3, r2
80075da: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80075dc: 787b ldrb r3, [r7, #1]
80075de: 2b00 cmp r3, #0
80075e0: d003 beq.n 80075ea <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80075e2: 887a ldrh r2, [r7, #2]
80075e4: 687b ldr r3, [r7, #4]
80075e6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
80075e8: e003 b.n 80075f2 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
80075ea: 887b ldrh r3, [r7, #2]
80075ec: 041a lsls r2, r3, #16
80075ee: 687b ldr r3, [r7, #4]
80075f0: 619a str r2, [r3, #24]
}
80075f2: bf00 nop
80075f4: 370c adds r7, #12
80075f6: 46bd mov sp, r7
80075f8: f85d 7b04 ldr.w r7, [sp], #4
80075fc: 4770 bx lr
080075fe <HAL_GPIO_TogglePin>:
* @param GPIOx Where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
80075fe: b480 push {r7}
8007600: b083 sub sp, #12
8007602: af00 add r7, sp, #0
8007604: 6078 str r0, [r7, #4]
8007606: 460b mov r3, r1
8007608: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
800760a: 687b ldr r3, [r7, #4]
800760c: 695a ldr r2, [r3, #20]
800760e: 887b ldrh r3, [r7, #2]
8007610: 4013 ands r3, r2
8007612: 2b00 cmp r3, #0
8007614: d004 beq.n 8007620 <HAL_GPIO_TogglePin+0x22>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
8007616: 887b ldrh r3, [r7, #2]
8007618: 041a lsls r2, r3, #16
800761a: 687b ldr r3, [r7, #4]
800761c: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
800761e: e002 b.n 8007626 <HAL_GPIO_TogglePin+0x28>
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8007620: 887a ldrh r2, [r7, #2]
8007622: 687b ldr r3, [r7, #4]
8007624: 619a str r2, [r3, #24]
}
8007626: bf00 nop
8007628: 370c adds r7, #12
800762a: 46bd mov sp, r7
800762c: f85d 7b04 ldr.w r7, [sp], #4
8007630: 4770 bx lr
...
08007634 <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8007634: b580 push {r7, lr}
8007636: b082 sub sp, #8
8007638: af00 add r7, sp, #0
800763a: 4603 mov r3, r0
800763c: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
800763e: 4b08 ldr r3, [pc, #32] ; (8007660 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8007640: 695a ldr r2, [r3, #20]
8007642: 88fb ldrh r3, [r7, #6]
8007644: 4013 ands r3, r2
8007646: 2b00 cmp r3, #0
8007648: d006 beq.n 8007658 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
800764a: 4a05 ldr r2, [pc, #20] ; (8007660 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
800764c: 88fb ldrh r3, [r7, #6]
800764e: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8007650: 88fb ldrh r3, [r7, #6]
8007652: 4618 mov r0, r3
8007654: f7fa fb54 bl 8001d00 <HAL_GPIO_EXTI_Callback>
}
}
8007658: bf00 nop
800765a: 3708 adds r7, #8
800765c: 46bd mov sp, r7
800765e: bd80 pop {r7, pc}
8007660: 40013c00 .word 0x40013c00
08007664 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8007664: b580 push {r7, lr}
8007666: b082 sub sp, #8
8007668: af00 add r7, sp, #0
800766a: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
800766c: 687b ldr r3, [r7, #4]
800766e: 2b00 cmp r3, #0
8007670: d101 bne.n 8007676 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8007672: 2301 movs r3, #1
8007674: e07f b.n 8007776 <HAL_I2C_Init+0x112>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8007676: 687b ldr r3, [r7, #4]
8007678: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800767c: b2db uxtb r3, r3
800767e: 2b00 cmp r3, #0
8007680: d106 bne.n 8007690 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8007682: 687b ldr r3, [r7, #4]
8007684: 2200 movs r2, #0
8007686: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
800768a: 6878 ldr r0, [r7, #4]
800768c: f000 f8a9 bl 80077e2 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8007690: 687b ldr r3, [r7, #4]
8007692: 2224 movs r2, #36 ; 0x24
8007694: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8007698: 687b ldr r3, [r7, #4]
800769a: 681b ldr r3, [r3, #0]
800769c: 681a ldr r2, [r3, #0]
800769e: 687b ldr r3, [r7, #4]
80076a0: 681b ldr r3, [r3, #0]
80076a2: f022 0201 bic.w r2, r2, #1
80076a6: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80076a8: 687b ldr r3, [r7, #4]
80076aa: 685a ldr r2, [r3, #4]
80076ac: 687b ldr r3, [r7, #4]
80076ae: 681b ldr r3, [r3, #0]
80076b0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80076b4: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80076b6: 687b ldr r3, [r7, #4]
80076b8: 681b ldr r3, [r3, #0]
80076ba: 689a ldr r2, [r3, #8]
80076bc: 687b ldr r3, [r7, #4]
80076be: 681b ldr r3, [r3, #0]
80076c0: f422 4200 bic.w r2, r2, #32768 ; 0x8000
80076c4: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80076c6: 687b ldr r3, [r7, #4]
80076c8: 68db ldr r3, [r3, #12]
80076ca: 2b01 cmp r3, #1
80076cc: d107 bne.n 80076de <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80076ce: 687b ldr r3, [r7, #4]
80076d0: 689a ldr r2, [r3, #8]
80076d2: 687b ldr r3, [r7, #4]
80076d4: 681b ldr r3, [r3, #0]
80076d6: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80076da: 609a str r2, [r3, #8]
80076dc: e006 b.n 80076ec <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
80076de: 687b ldr r3, [r7, #4]
80076e0: 689a ldr r2, [r3, #8]
80076e2: 687b ldr r3, [r7, #4]
80076e4: 681b ldr r3, [r3, #0]
80076e6: f442 4204 orr.w r2, r2, #33792 ; 0x8400
80076ea: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
80076ec: 687b ldr r3, [r7, #4]
80076ee: 68db ldr r3, [r3, #12]
80076f0: 2b02 cmp r3, #2
80076f2: d104 bne.n 80076fe <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
80076f4: 687b ldr r3, [r7, #4]
80076f6: 681b ldr r3, [r3, #0]
80076f8: f44f 6200 mov.w r2, #2048 ; 0x800
80076fc: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
80076fe: 687b ldr r3, [r7, #4]
8007700: 681b ldr r3, [r3, #0]
8007702: 6859 ldr r1, [r3, #4]
8007704: 687b ldr r3, [r7, #4]
8007706: 681a ldr r2, [r3, #0]
8007708: 4b1d ldr r3, [pc, #116] ; (8007780 <HAL_I2C_Init+0x11c>)
800770a: 430b orrs r3, r1
800770c: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
800770e: 687b ldr r3, [r7, #4]
8007710: 681b ldr r3, [r3, #0]
8007712: 68da ldr r2, [r3, #12]
8007714: 687b ldr r3, [r7, #4]
8007716: 681b ldr r3, [r3, #0]
8007718: f422 4200 bic.w r2, r2, #32768 ; 0x8000
800771c: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
800771e: 687b ldr r3, [r7, #4]
8007720: 691a ldr r2, [r3, #16]
8007722: 687b ldr r3, [r7, #4]
8007724: 695b ldr r3, [r3, #20]
8007726: ea42 0103 orr.w r1, r2, r3
800772a: 687b ldr r3, [r7, #4]
800772c: 699b ldr r3, [r3, #24]
800772e: 021a lsls r2, r3, #8
8007730: 687b ldr r3, [r7, #4]
8007732: 681b ldr r3, [r3, #0]
8007734: 430a orrs r2, r1
8007736: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8007738: 687b ldr r3, [r7, #4]
800773a: 69d9 ldr r1, [r3, #28]
800773c: 687b ldr r3, [r7, #4]
800773e: 6a1a ldr r2, [r3, #32]
8007740: 687b ldr r3, [r7, #4]
8007742: 681b ldr r3, [r3, #0]
8007744: 430a orrs r2, r1
8007746: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8007748: 687b ldr r3, [r7, #4]
800774a: 681b ldr r3, [r3, #0]
800774c: 681a ldr r2, [r3, #0]
800774e: 687b ldr r3, [r7, #4]
8007750: 681b ldr r3, [r3, #0]
8007752: f042 0201 orr.w r2, r2, #1
8007756: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007758: 687b ldr r3, [r7, #4]
800775a: 2200 movs r2, #0
800775c: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
800775e: 687b ldr r3, [r7, #4]
8007760: 2220 movs r2, #32
8007762: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8007766: 687b ldr r3, [r7, #4]
8007768: 2200 movs r2, #0
800776a: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
800776c: 687b ldr r3, [r7, #4]
800776e: 2200 movs r2, #0
8007770: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
8007774: 2300 movs r3, #0
}
8007776: 4618 mov r0, r3
8007778: 3708 adds r7, #8
800777a: 46bd mov sp, r7
800777c: bd80 pop {r7, pc}
800777e: bf00 nop
8007780: 02008000 .word 0x02008000
08007784 <HAL_I2C_DeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
8007784: b580 push {r7, lr}
8007786: b082 sub sp, #8
8007788: af00 add r7, sp, #0
800778a: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
800778c: 687b ldr r3, [r7, #4]
800778e: 2b00 cmp r3, #0
8007790: d101 bne.n 8007796 <HAL_I2C_DeInit+0x12>
{
return HAL_ERROR;
8007792: 2301 movs r3, #1
8007794: e021 b.n 80077da <HAL_I2C_DeInit+0x56>
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
hi2c->State = HAL_I2C_STATE_BUSY;
8007796: 687b ldr r3, [r7, #4]
8007798: 2224 movs r2, #36 ; 0x24
800779a: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
800779e: 687b ldr r3, [r7, #4]
80077a0: 681b ldr r3, [r3, #0]
80077a2: 681a ldr r2, [r3, #0]
80077a4: 687b ldr r3, [r7, #4]
80077a6: 681b ldr r3, [r3, #0]
80077a8: f022 0201 bic.w r2, r2, #1
80077ac: 601a str r2, [r3, #0]
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hi2c->MspDeInitCallback(hi2c);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
80077ae: 6878 ldr r0, [r7, #4]
80077b0: f000 f821 bl 80077f6 <HAL_I2C_MspDeInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80077b4: 687b ldr r3, [r7, #4]
80077b6: 2200 movs r2, #0
80077b8: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_RESET;
80077ba: 687b ldr r3, [r7, #4]
80077bc: 2200 movs r2, #0
80077be: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80077c2: 687b ldr r3, [r7, #4]
80077c4: 2200 movs r2, #0
80077c6: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80077c8: 687b ldr r3, [r7, #4]
80077ca: 2200 movs r2, #0
80077cc: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Release Lock */
__HAL_UNLOCK(hi2c);
80077d0: 687b ldr r3, [r7, #4]
80077d2: 2200 movs r2, #0
80077d4: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
80077d8: 2300 movs r3, #0
}
80077da: 4618 mov r0, r3
80077dc: 3708 adds r7, #8
80077de: 46bd mov sp, r7
80077e0: bd80 pop {r7, pc}
080077e2 <HAL_I2C_MspInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
80077e2: b480 push {r7}
80077e4: b083 sub sp, #12
80077e6: af00 add r7, sp, #0
80077e8: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
80077ea: bf00 nop
80077ec: 370c adds r7, #12
80077ee: 46bd mov sp, r7
80077f0: f85d 7b04 ldr.w r7, [sp], #4
80077f4: 4770 bx lr
080077f6 <HAL_I2C_MspDeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
80077f6: b480 push {r7}
80077f8: b083 sub sp, #12
80077fa: af00 add r7, sp, #0
80077fc: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
80077fe: bf00 nop
8007800: 370c adds r7, #12
8007802: 46bd mov sp, r7
8007804: f85d 7b04 ldr.w r7, [sp], #4
8007808: 4770 bx lr
...
0800780c <HAL_I2C_Mem_Write>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800780c: b580 push {r7, lr}
800780e: b088 sub sp, #32
8007810: af02 add r7, sp, #8
8007812: 60f8 str r0, [r7, #12]
8007814: 4608 mov r0, r1
8007816: 4611 mov r1, r2
8007818: 461a mov r2, r3
800781a: 4603 mov r3, r0
800781c: 817b strh r3, [r7, #10]
800781e: 460b mov r3, r1
8007820: 813b strh r3, [r7, #8]
8007822: 4613 mov r3, r2
8007824: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8007826: 68fb ldr r3, [r7, #12]
8007828: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800782c: b2db uxtb r3, r3
800782e: 2b20 cmp r3, #32
8007830: f040 80f9 bne.w 8007a26 <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
8007834: 6a3b ldr r3, [r7, #32]
8007836: 2b00 cmp r3, #0
8007838: d002 beq.n 8007840 <HAL_I2C_Mem_Write+0x34>
800783a: 8cbb ldrh r3, [r7, #36] ; 0x24
800783c: 2b00 cmp r3, #0
800783e: d105 bne.n 800784c <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007840: 68fb ldr r3, [r7, #12]
8007842: f44f 7200 mov.w r2, #512 ; 0x200
8007846: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007848: 2301 movs r3, #1
800784a: e0ed b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800784c: 68fb ldr r3, [r7, #12]
800784e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8007852: 2b01 cmp r3, #1
8007854: d101 bne.n 800785a <HAL_I2C_Mem_Write+0x4e>
8007856: 2302 movs r3, #2
8007858: e0e6 b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
800785a: 68fb ldr r3, [r7, #12]
800785c: 2201 movs r2, #1
800785e: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8007862: f7fd f899 bl 8004998 <HAL_GetTick>
8007866: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8007868: 697b ldr r3, [r7, #20]
800786a: 9300 str r3, [sp, #0]
800786c: 2319 movs r3, #25
800786e: 2201 movs r2, #1
8007870: f44f 4100 mov.w r1, #32768 ; 0x8000
8007874: 68f8 ldr r0, [r7, #12]
8007876: f000 fad1 bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
800787a: 4603 mov r3, r0
800787c: 2b00 cmp r3, #0
800787e: d001 beq.n 8007884 <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
8007880: 2301 movs r3, #1
8007882: e0d1 b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
8007884: 68fb ldr r3, [r7, #12]
8007886: 2221 movs r2, #33 ; 0x21
8007888: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
800788c: 68fb ldr r3, [r7, #12]
800788e: 2240 movs r2, #64 ; 0x40
8007890: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007894: 68fb ldr r3, [r7, #12]
8007896: 2200 movs r2, #0
8007898: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
800789a: 68fb ldr r3, [r7, #12]
800789c: 6a3a ldr r2, [r7, #32]
800789e: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80078a0: 68fb ldr r3, [r7, #12]
80078a2: 8cba ldrh r2, [r7, #36] ; 0x24
80078a4: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80078a6: 68fb ldr r3, [r7, #12]
80078a8: 2200 movs r2, #0
80078aa: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80078ac: 88f8 ldrh r0, [r7, #6]
80078ae: 893a ldrh r2, [r7, #8]
80078b0: 8979 ldrh r1, [r7, #10]
80078b2: 697b ldr r3, [r7, #20]
80078b4: 9301 str r3, [sp, #4]
80078b6: 6abb ldr r3, [r7, #40] ; 0x28
80078b8: 9300 str r3, [sp, #0]
80078ba: 4603 mov r3, r0
80078bc: 68f8 ldr r0, [r7, #12]
80078be: f000 f9e1 bl 8007c84 <I2C_RequestMemoryWrite>
80078c2: 4603 mov r3, r0
80078c4: 2b00 cmp r3, #0
80078c6: d005 beq.n 80078d4 <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80078c8: 68fb ldr r3, [r7, #12]
80078ca: 2200 movs r2, #0
80078cc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
80078d0: 2301 movs r3, #1
80078d2: e0a9 b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80078d4: 68fb ldr r3, [r7, #12]
80078d6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80078d8: b29b uxth r3, r3
80078da: 2bff cmp r3, #255 ; 0xff
80078dc: d90e bls.n 80078fc <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80078de: 68fb ldr r3, [r7, #12]
80078e0: 22ff movs r2, #255 ; 0xff
80078e2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80078e4: 68fb ldr r3, [r7, #12]
80078e6: 8d1b ldrh r3, [r3, #40] ; 0x28
80078e8: b2da uxtb r2, r3
80078ea: 8979 ldrh r1, [r7, #10]
80078ec: 2300 movs r3, #0
80078ee: 9300 str r3, [sp, #0]
80078f0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80078f4: 68f8 ldr r0, [r7, #12]
80078f6: f000 fbb3 bl 8008060 <I2C_TransferConfig>
80078fa: e00f b.n 800791c <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80078fc: 68fb ldr r3, [r7, #12]
80078fe: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007900: b29a uxth r2, r3
8007902: 68fb ldr r3, [r7, #12]
8007904: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8007906: 68fb ldr r3, [r7, #12]
8007908: 8d1b ldrh r3, [r3, #40] ; 0x28
800790a: b2da uxtb r2, r3
800790c: 8979 ldrh r1, [r7, #10]
800790e: 2300 movs r3, #0
8007910: 9300 str r3, [sp, #0]
8007912: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007916: 68f8 ldr r0, [r7, #12]
8007918: f000 fba2 bl 8008060 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800791c: 697a ldr r2, [r7, #20]
800791e: 6ab9 ldr r1, [r7, #40] ; 0x28
8007920: 68f8 ldr r0, [r7, #12]
8007922: f000 fabb bl 8007e9c <I2C_WaitOnTXISFlagUntilTimeout>
8007926: 4603 mov r3, r0
8007928: 2b00 cmp r3, #0
800792a: d001 beq.n 8007930 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
800792c: 2301 movs r3, #1
800792e: e07b b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8007930: 68fb ldr r3, [r7, #12]
8007932: 6a5b ldr r3, [r3, #36] ; 0x24
8007934: 781a ldrb r2, [r3, #0]
8007936: 68fb ldr r3, [r7, #12]
8007938: 681b ldr r3, [r3, #0]
800793a: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800793c: 68fb ldr r3, [r7, #12]
800793e: 6a5b ldr r3, [r3, #36] ; 0x24
8007940: 1c5a adds r2, r3, #1
8007942: 68fb ldr r3, [r7, #12]
8007944: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
8007946: 68fb ldr r3, [r7, #12]
8007948: 8d5b ldrh r3, [r3, #42] ; 0x2a
800794a: b29b uxth r3, r3
800794c: 3b01 subs r3, #1
800794e: b29a uxth r2, r3
8007950: 68fb ldr r3, [r7, #12]
8007952: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
8007954: 68fb ldr r3, [r7, #12]
8007956: 8d1b ldrh r3, [r3, #40] ; 0x28
8007958: 3b01 subs r3, #1
800795a: b29a uxth r2, r3
800795c: 68fb ldr r3, [r7, #12]
800795e: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8007960: 68fb ldr r3, [r7, #12]
8007962: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007964: b29b uxth r3, r3
8007966: 2b00 cmp r3, #0
8007968: d034 beq.n 80079d4 <HAL_I2C_Mem_Write+0x1c8>
800796a: 68fb ldr r3, [r7, #12]
800796c: 8d1b ldrh r3, [r3, #40] ; 0x28
800796e: 2b00 cmp r3, #0
8007970: d130 bne.n 80079d4 <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8007972: 697b ldr r3, [r7, #20]
8007974: 9300 str r3, [sp, #0]
8007976: 6abb ldr r3, [r7, #40] ; 0x28
8007978: 2200 movs r2, #0
800797a: 2180 movs r1, #128 ; 0x80
800797c: 68f8 ldr r0, [r7, #12]
800797e: f000 fa4d bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007982: 4603 mov r3, r0
8007984: 2b00 cmp r3, #0
8007986: d001 beq.n 800798c <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
8007988: 2301 movs r3, #1
800798a: e04d b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800798c: 68fb ldr r3, [r7, #12]
800798e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007990: b29b uxth r3, r3
8007992: 2bff cmp r3, #255 ; 0xff
8007994: d90e bls.n 80079b4 <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007996: 68fb ldr r3, [r7, #12]
8007998: 22ff movs r2, #255 ; 0xff
800799a: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
800799c: 68fb ldr r3, [r7, #12]
800799e: 8d1b ldrh r3, [r3, #40] ; 0x28
80079a0: b2da uxtb r2, r3
80079a2: 8979 ldrh r1, [r7, #10]
80079a4: 2300 movs r3, #0
80079a6: 9300 str r3, [sp, #0]
80079a8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80079ac: 68f8 ldr r0, [r7, #12]
80079ae: f000 fb57 bl 8008060 <I2C_TransferConfig>
80079b2: e00f b.n 80079d4 <HAL_I2C_Mem_Write+0x1c8>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80079b4: 68fb ldr r3, [r7, #12]
80079b6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079b8: b29a uxth r2, r3
80079ba: 68fb ldr r3, [r7, #12]
80079bc: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
80079be: 68fb ldr r3, [r7, #12]
80079c0: 8d1b ldrh r3, [r3, #40] ; 0x28
80079c2: b2da uxtb r2, r3
80079c4: 8979 ldrh r1, [r7, #10]
80079c6: 2300 movs r3, #0
80079c8: 9300 str r3, [sp, #0]
80079ca: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80079ce: 68f8 ldr r0, [r7, #12]
80079d0: f000 fb46 bl 8008060 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
80079d4: 68fb ldr r3, [r7, #12]
80079d6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079d8: b29b uxth r3, r3
80079da: 2b00 cmp r3, #0
80079dc: d19e bne.n 800791c <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
80079de: 697a ldr r2, [r7, #20]
80079e0: 6ab9 ldr r1, [r7, #40] ; 0x28
80079e2: 68f8 ldr r0, [r7, #12]
80079e4: f000 fa9a bl 8007f1c <I2C_WaitOnSTOPFlagUntilTimeout>
80079e8: 4603 mov r3, r0
80079ea: 2b00 cmp r3, #0
80079ec: d001 beq.n 80079f2 <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
80079ee: 2301 movs r3, #1
80079f0: e01a b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80079f2: 68fb ldr r3, [r7, #12]
80079f4: 681b ldr r3, [r3, #0]
80079f6: 2220 movs r2, #32
80079f8: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
80079fa: 68fb ldr r3, [r7, #12]
80079fc: 681b ldr r3, [r3, #0]
80079fe: 6859 ldr r1, [r3, #4]
8007a00: 68fb ldr r3, [r7, #12]
8007a02: 681a ldr r2, [r3, #0]
8007a04: 4b0a ldr r3, [pc, #40] ; (8007a30 <HAL_I2C_Mem_Write+0x224>)
8007a06: 400b ands r3, r1
8007a08: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007a0a: 68fb ldr r3, [r7, #12]
8007a0c: 2220 movs r2, #32
8007a0e: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007a12: 68fb ldr r3, [r7, #12]
8007a14: 2200 movs r2, #0
8007a16: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007a1a: 68fb ldr r3, [r7, #12]
8007a1c: 2200 movs r2, #0
8007a1e: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007a22: 2300 movs r3, #0
8007a24: e000 b.n 8007a28 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
8007a26: 2302 movs r3, #2
}
}
8007a28: 4618 mov r0, r3
8007a2a: 3718 adds r7, #24
8007a2c: 46bd mov sp, r7
8007a2e: bd80 pop {r7, pc}
8007a30: fe00e800 .word 0xfe00e800
08007a34 <HAL_I2C_Mem_Read>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8007a34: b580 push {r7, lr}
8007a36: b088 sub sp, #32
8007a38: af02 add r7, sp, #8
8007a3a: 60f8 str r0, [r7, #12]
8007a3c: 4608 mov r0, r1
8007a3e: 4611 mov r1, r2
8007a40: 461a mov r2, r3
8007a42: 4603 mov r3, r0
8007a44: 817b strh r3, [r7, #10]
8007a46: 460b mov r3, r1
8007a48: 813b strh r3, [r7, #8]
8007a4a: 4613 mov r3, r2
8007a4c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8007a4e: 68fb ldr r3, [r7, #12]
8007a50: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007a54: b2db uxtb r3, r3
8007a56: 2b20 cmp r3, #32
8007a58: f040 80fd bne.w 8007c56 <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
8007a5c: 6a3b ldr r3, [r7, #32]
8007a5e: 2b00 cmp r3, #0
8007a60: d002 beq.n 8007a68 <HAL_I2C_Mem_Read+0x34>
8007a62: 8cbb ldrh r3, [r7, #36] ; 0x24
8007a64: 2b00 cmp r3, #0
8007a66: d105 bne.n 8007a74 <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007a68: 68fb ldr r3, [r7, #12]
8007a6a: f44f 7200 mov.w r2, #512 ; 0x200
8007a6e: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007a70: 2301 movs r3, #1
8007a72: e0f1 b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8007a74: 68fb ldr r3, [r7, #12]
8007a76: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8007a7a: 2b01 cmp r3, #1
8007a7c: d101 bne.n 8007a82 <HAL_I2C_Mem_Read+0x4e>
8007a7e: 2302 movs r3, #2
8007a80: e0ea b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
8007a82: 68fb ldr r3, [r7, #12]
8007a84: 2201 movs r2, #1
8007a86: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8007a8a: f7fc ff85 bl 8004998 <HAL_GetTick>
8007a8e: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8007a90: 697b ldr r3, [r7, #20]
8007a92: 9300 str r3, [sp, #0]
8007a94: 2319 movs r3, #25
8007a96: 2201 movs r2, #1
8007a98: f44f 4100 mov.w r1, #32768 ; 0x8000
8007a9c: 68f8 ldr r0, [r7, #12]
8007a9e: f000 f9bd bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007aa2: 4603 mov r3, r0
8007aa4: 2b00 cmp r3, #0
8007aa6: d001 beq.n 8007aac <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
8007aa8: 2301 movs r3, #1
8007aaa: e0d5 b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
8007aac: 68fb ldr r3, [r7, #12]
8007aae: 2222 movs r2, #34 ; 0x22
8007ab0: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
8007ab4: 68fb ldr r3, [r7, #12]
8007ab6: 2240 movs r2, #64 ; 0x40
8007ab8: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007abc: 68fb ldr r3, [r7, #12]
8007abe: 2200 movs r2, #0
8007ac0: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8007ac2: 68fb ldr r3, [r7, #12]
8007ac4: 6a3a ldr r2, [r7, #32]
8007ac6: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
8007ac8: 68fb ldr r3, [r7, #12]
8007aca: 8cba ldrh r2, [r7, #36] ; 0x24
8007acc: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
8007ace: 68fb ldr r3, [r7, #12]
8007ad0: 2200 movs r2, #0
8007ad2: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
8007ad4: 88f8 ldrh r0, [r7, #6]
8007ad6: 893a ldrh r2, [r7, #8]
8007ad8: 8979 ldrh r1, [r7, #10]
8007ada: 697b ldr r3, [r7, #20]
8007adc: 9301 str r3, [sp, #4]
8007ade: 6abb ldr r3, [r7, #40] ; 0x28
8007ae0: 9300 str r3, [sp, #0]
8007ae2: 4603 mov r3, r0
8007ae4: 68f8 ldr r0, [r7, #12]
8007ae6: f000 f921 bl 8007d2c <I2C_RequestMemoryRead>
8007aea: 4603 mov r3, r0
8007aec: 2b00 cmp r3, #0
8007aee: d005 beq.n 8007afc <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007af0: 68fb ldr r3, [r7, #12]
8007af2: 2200 movs r2, #0
8007af4: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007af8: 2301 movs r3, #1
8007afa: e0ad b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007afc: 68fb ldr r3, [r7, #12]
8007afe: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b00: b29b uxth r3, r3
8007b02: 2bff cmp r3, #255 ; 0xff
8007b04: d90e bls.n 8007b24 <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007b06: 68fb ldr r3, [r7, #12]
8007b08: 22ff movs r2, #255 ; 0xff
8007b0a: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
8007b0c: 68fb ldr r3, [r7, #12]
8007b0e: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b10: b2da uxtb r2, r3
8007b12: 8979 ldrh r1, [r7, #10]
8007b14: 4b52 ldr r3, [pc, #328] ; (8007c60 <HAL_I2C_Mem_Read+0x22c>)
8007b16: 9300 str r3, [sp, #0]
8007b18: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007b1c: 68f8 ldr r0, [r7, #12]
8007b1e: f000 fa9f bl 8008060 <I2C_TransferConfig>
8007b22: e00f b.n 8007b44 <HAL_I2C_Mem_Read+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007b24: 68fb ldr r3, [r7, #12]
8007b26: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b28: b29a uxth r2, r3
8007b2a: 68fb ldr r3, [r7, #12]
8007b2c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
8007b2e: 68fb ldr r3, [r7, #12]
8007b30: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b32: b2da uxtb r2, r3
8007b34: 8979 ldrh r1, [r7, #10]
8007b36: 4b4a ldr r3, [pc, #296] ; (8007c60 <HAL_I2C_Mem_Read+0x22c>)
8007b38: 9300 str r3, [sp, #0]
8007b3a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007b3e: 68f8 ldr r0, [r7, #12]
8007b40: f000 fa8e bl 8008060 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
8007b44: 697b ldr r3, [r7, #20]
8007b46: 9300 str r3, [sp, #0]
8007b48: 6abb ldr r3, [r7, #40] ; 0x28
8007b4a: 2200 movs r2, #0
8007b4c: 2104 movs r1, #4
8007b4e: 68f8 ldr r0, [r7, #12]
8007b50: f000 f964 bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007b54: 4603 mov r3, r0
8007b56: 2b00 cmp r3, #0
8007b58: d001 beq.n 8007b5e <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
8007b5a: 2301 movs r3, #1
8007b5c: e07c b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8007b5e: 68fb ldr r3, [r7, #12]
8007b60: 681b ldr r3, [r3, #0]
8007b62: 6a5a ldr r2, [r3, #36] ; 0x24
8007b64: 68fb ldr r3, [r7, #12]
8007b66: 6a5b ldr r3, [r3, #36] ; 0x24
8007b68: b2d2 uxtb r2, r2
8007b6a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007b6c: 68fb ldr r3, [r7, #12]
8007b6e: 6a5b ldr r3, [r3, #36] ; 0x24
8007b70: 1c5a adds r2, r3, #1
8007b72: 68fb ldr r3, [r7, #12]
8007b74: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
8007b76: 68fb ldr r3, [r7, #12]
8007b78: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b7a: 3b01 subs r3, #1
8007b7c: b29a uxth r2, r3
8007b7e: 68fb ldr r3, [r7, #12]
8007b80: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
8007b82: 68fb ldr r3, [r7, #12]
8007b84: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b86: b29b uxth r3, r3
8007b88: 3b01 subs r3, #1
8007b8a: b29a uxth r2, r3
8007b8c: 68fb ldr r3, [r7, #12]
8007b8e: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8007b90: 68fb ldr r3, [r7, #12]
8007b92: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b94: b29b uxth r3, r3
8007b96: 2b00 cmp r3, #0
8007b98: d034 beq.n 8007c04 <HAL_I2C_Mem_Read+0x1d0>
8007b9a: 68fb ldr r3, [r7, #12]
8007b9c: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b9e: 2b00 cmp r3, #0
8007ba0: d130 bne.n 8007c04 <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8007ba2: 697b ldr r3, [r7, #20]
8007ba4: 9300 str r3, [sp, #0]
8007ba6: 6abb ldr r3, [r7, #40] ; 0x28
8007ba8: 2200 movs r2, #0
8007baa: 2180 movs r1, #128 ; 0x80
8007bac: 68f8 ldr r0, [r7, #12]
8007bae: f000 f935 bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007bb2: 4603 mov r3, r0
8007bb4: 2b00 cmp r3, #0
8007bb6: d001 beq.n 8007bbc <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
8007bb8: 2301 movs r3, #1
8007bba: e04d b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007bbc: 68fb ldr r3, [r7, #12]
8007bbe: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007bc0: b29b uxth r3, r3
8007bc2: 2bff cmp r3, #255 ; 0xff
8007bc4: d90e bls.n 8007be4 <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007bc6: 68fb ldr r3, [r7, #12]
8007bc8: 22ff movs r2, #255 ; 0xff
8007bca: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
8007bcc: 68fb ldr r3, [r7, #12]
8007bce: 8d1b ldrh r3, [r3, #40] ; 0x28
8007bd0: b2da uxtb r2, r3
8007bd2: 8979 ldrh r1, [r7, #10]
8007bd4: 2300 movs r3, #0
8007bd6: 9300 str r3, [sp, #0]
8007bd8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007bdc: 68f8 ldr r0, [r7, #12]
8007bde: f000 fa3f bl 8008060 <I2C_TransferConfig>
8007be2: e00f b.n 8007c04 <HAL_I2C_Mem_Read+0x1d0>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007be4: 68fb ldr r3, [r7, #12]
8007be6: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007be8: b29a uxth r2, r3
8007bea: 68fb ldr r3, [r7, #12]
8007bec: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8007bee: 68fb ldr r3, [r7, #12]
8007bf0: 8d1b ldrh r3, [r3, #40] ; 0x28
8007bf2: b2da uxtb r2, r3
8007bf4: 8979 ldrh r1, [r7, #10]
8007bf6: 2300 movs r3, #0
8007bf8: 9300 str r3, [sp, #0]
8007bfa: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007bfe: 68f8 ldr r0, [r7, #12]
8007c00: f000 fa2e bl 8008060 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
8007c04: 68fb ldr r3, [r7, #12]
8007c06: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007c08: b29b uxth r3, r3
8007c0a: 2b00 cmp r3, #0
8007c0c: d19a bne.n 8007b44 <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007c0e: 697a ldr r2, [r7, #20]
8007c10: 6ab9 ldr r1, [r7, #40] ; 0x28
8007c12: 68f8 ldr r0, [r7, #12]
8007c14: f000 f982 bl 8007f1c <I2C_WaitOnSTOPFlagUntilTimeout>
8007c18: 4603 mov r3, r0
8007c1a: 2b00 cmp r3, #0
8007c1c: d001 beq.n 8007c22 <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
8007c1e: 2301 movs r3, #1
8007c20: e01a b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007c22: 68fb ldr r3, [r7, #12]
8007c24: 681b ldr r3, [r3, #0]
8007c26: 2220 movs r2, #32
8007c28: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007c2a: 68fb ldr r3, [r7, #12]
8007c2c: 681b ldr r3, [r3, #0]
8007c2e: 6859 ldr r1, [r3, #4]
8007c30: 68fb ldr r3, [r7, #12]
8007c32: 681a ldr r2, [r3, #0]
8007c34: 4b0b ldr r3, [pc, #44] ; (8007c64 <HAL_I2C_Mem_Read+0x230>)
8007c36: 400b ands r3, r1
8007c38: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007c3a: 68fb ldr r3, [r7, #12]
8007c3c: 2220 movs r2, #32
8007c3e: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007c42: 68fb ldr r3, [r7, #12]
8007c44: 2200 movs r2, #0
8007c46: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007c4a: 68fb ldr r3, [r7, #12]
8007c4c: 2200 movs r2, #0
8007c4e: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007c52: 2300 movs r3, #0
8007c54: e000 b.n 8007c58 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8007c56: 2302 movs r3, #2
}
}
8007c58: 4618 mov r0, r3
8007c5a: 3718 adds r7, #24
8007c5c: 46bd mov sp, r7
8007c5e: bd80 pop {r7, pc}
8007c60: 80002400 .word 0x80002400
8007c64: fe00e800 .word 0xfe00e800
08007c68 <HAL_I2C_GetState>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
8007c68: b480 push {r7}
8007c6a: b083 sub sp, #12
8007c6c: af00 add r7, sp, #0
8007c6e: 6078 str r0, [r7, #4]
/* Return I2C handle state */
return hi2c->State;
8007c70: 687b ldr r3, [r7, #4]
8007c72: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007c76: b2db uxtb r3, r3
}
8007c78: 4618 mov r0, r3
8007c7a: 370c adds r7, #12
8007c7c: 46bd mov sp, r7
8007c7e: f85d 7b04 ldr.w r7, [sp], #4
8007c82: 4770 bx lr
08007c84 <I2C_RequestMemoryWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007c84: b580 push {r7, lr}
8007c86: b086 sub sp, #24
8007c88: af02 add r7, sp, #8
8007c8a: 60f8 str r0, [r7, #12]
8007c8c: 4608 mov r0, r1
8007c8e: 4611 mov r1, r2
8007c90: 461a mov r2, r3
8007c92: 4603 mov r3, r0
8007c94: 817b strh r3, [r7, #10]
8007c96: 460b mov r3, r1
8007c98: 813b strh r3, [r7, #8]
8007c9a: 4613 mov r3, r2
8007c9c: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
8007c9e: 88fb ldrh r3, [r7, #6]
8007ca0: b2da uxtb r2, r3
8007ca2: 8979 ldrh r1, [r7, #10]
8007ca4: 4b20 ldr r3, [pc, #128] ; (8007d28 <I2C_RequestMemoryWrite+0xa4>)
8007ca6: 9300 str r3, [sp, #0]
8007ca8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007cac: 68f8 ldr r0, [r7, #12]
8007cae: f000 f9d7 bl 8008060 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007cb2: 69fa ldr r2, [r7, #28]
8007cb4: 69b9 ldr r1, [r7, #24]
8007cb6: 68f8 ldr r0, [r7, #12]
8007cb8: f000 f8f0 bl 8007e9c <I2C_WaitOnTXISFlagUntilTimeout>
8007cbc: 4603 mov r3, r0
8007cbe: 2b00 cmp r3, #0
8007cc0: d001 beq.n 8007cc6 <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
8007cc2: 2301 movs r3, #1
8007cc4: e02c b.n 8007d20 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007cc6: 88fb ldrh r3, [r7, #6]
8007cc8: 2b01 cmp r3, #1
8007cca: d105 bne.n 8007cd8 <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007ccc: 893b ldrh r3, [r7, #8]
8007cce: b2da uxtb r2, r3
8007cd0: 68fb ldr r3, [r7, #12]
8007cd2: 681b ldr r3, [r3, #0]
8007cd4: 629a str r2, [r3, #40] ; 0x28
8007cd6: e015 b.n 8007d04 <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007cd8: 893b ldrh r3, [r7, #8]
8007cda: 0a1b lsrs r3, r3, #8
8007cdc: b29b uxth r3, r3
8007cde: b2da uxtb r2, r3
8007ce0: 68fb ldr r3, [r7, #12]
8007ce2: 681b ldr r3, [r3, #0]
8007ce4: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007ce6: 69fa ldr r2, [r7, #28]
8007ce8: 69b9 ldr r1, [r7, #24]
8007cea: 68f8 ldr r0, [r7, #12]
8007cec: f000 f8d6 bl 8007e9c <I2C_WaitOnTXISFlagUntilTimeout>
8007cf0: 4603 mov r3, r0
8007cf2: 2b00 cmp r3, #0
8007cf4: d001 beq.n 8007cfa <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
8007cf6: 2301 movs r3, #1
8007cf8: e012 b.n 8007d20 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007cfa: 893b ldrh r3, [r7, #8]
8007cfc: b2da uxtb r2, r3
8007cfe: 68fb ldr r3, [r7, #12]
8007d00: 681b ldr r3, [r3, #0]
8007d02: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8007d04: 69fb ldr r3, [r7, #28]
8007d06: 9300 str r3, [sp, #0]
8007d08: 69bb ldr r3, [r7, #24]
8007d0a: 2200 movs r2, #0
8007d0c: 2180 movs r1, #128 ; 0x80
8007d0e: 68f8 ldr r0, [r7, #12]
8007d10: f000 f884 bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007d14: 4603 mov r3, r0
8007d16: 2b00 cmp r3, #0
8007d18: d001 beq.n 8007d1e <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
8007d1a: 2301 movs r3, #1
8007d1c: e000 b.n 8007d20 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
8007d1e: 2300 movs r3, #0
}
8007d20: 4618 mov r0, r3
8007d22: 3710 adds r7, #16
8007d24: 46bd mov sp, r7
8007d26: bd80 pop {r7, pc}
8007d28: 80002000 .word 0x80002000
08007d2c <I2C_RequestMemoryRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007d2c: b580 push {r7, lr}
8007d2e: b086 sub sp, #24
8007d30: af02 add r7, sp, #8
8007d32: 60f8 str r0, [r7, #12]
8007d34: 4608 mov r0, r1
8007d36: 4611 mov r1, r2
8007d38: 461a mov r2, r3
8007d3a: 4603 mov r3, r0
8007d3c: 817b strh r3, [r7, #10]
8007d3e: 460b mov r3, r1
8007d40: 813b strh r3, [r7, #8]
8007d42: 4613 mov r3, r2
8007d44: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
8007d46: 88fb ldrh r3, [r7, #6]
8007d48: b2da uxtb r2, r3
8007d4a: 8979 ldrh r1, [r7, #10]
8007d4c: 4b20 ldr r3, [pc, #128] ; (8007dd0 <I2C_RequestMemoryRead+0xa4>)
8007d4e: 9300 str r3, [sp, #0]
8007d50: 2300 movs r3, #0
8007d52: 68f8 ldr r0, [r7, #12]
8007d54: f000 f984 bl 8008060 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007d58: 69fa ldr r2, [r7, #28]
8007d5a: 69b9 ldr r1, [r7, #24]
8007d5c: 68f8 ldr r0, [r7, #12]
8007d5e: f000 f89d bl 8007e9c <I2C_WaitOnTXISFlagUntilTimeout>
8007d62: 4603 mov r3, r0
8007d64: 2b00 cmp r3, #0
8007d66: d001 beq.n 8007d6c <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
8007d68: 2301 movs r3, #1
8007d6a: e02c b.n 8007dc6 <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007d6c: 88fb ldrh r3, [r7, #6]
8007d6e: 2b01 cmp r3, #1
8007d70: d105 bne.n 8007d7e <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007d72: 893b ldrh r3, [r7, #8]
8007d74: b2da uxtb r2, r3
8007d76: 68fb ldr r3, [r7, #12]
8007d78: 681b ldr r3, [r3, #0]
8007d7a: 629a str r2, [r3, #40] ; 0x28
8007d7c: e015 b.n 8007daa <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007d7e: 893b ldrh r3, [r7, #8]
8007d80: 0a1b lsrs r3, r3, #8
8007d82: b29b uxth r3, r3
8007d84: b2da uxtb r2, r3
8007d86: 68fb ldr r3, [r7, #12]
8007d88: 681b ldr r3, [r3, #0]
8007d8a: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007d8c: 69fa ldr r2, [r7, #28]
8007d8e: 69b9 ldr r1, [r7, #24]
8007d90: 68f8 ldr r0, [r7, #12]
8007d92: f000 f883 bl 8007e9c <I2C_WaitOnTXISFlagUntilTimeout>
8007d96: 4603 mov r3, r0
8007d98: 2b00 cmp r3, #0
8007d9a: d001 beq.n 8007da0 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
8007d9c: 2301 movs r3, #1
8007d9e: e012 b.n 8007dc6 <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007da0: 893b ldrh r3, [r7, #8]
8007da2: b2da uxtb r2, r3
8007da4: 68fb ldr r3, [r7, #12]
8007da6: 681b ldr r3, [r3, #0]
8007da8: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
8007daa: 69fb ldr r3, [r7, #28]
8007dac: 9300 str r3, [sp, #0]
8007dae: 69bb ldr r3, [r7, #24]
8007db0: 2200 movs r2, #0
8007db2: 2140 movs r1, #64 ; 0x40
8007db4: 68f8 ldr r0, [r7, #12]
8007db6: f000 f831 bl 8007e1c <I2C_WaitOnFlagUntilTimeout>
8007dba: 4603 mov r3, r0
8007dbc: 2b00 cmp r3, #0
8007dbe: d001 beq.n 8007dc4 <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
8007dc0: 2301 movs r3, #1
8007dc2: e000 b.n 8007dc6 <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
8007dc4: 2300 movs r3, #0
}
8007dc6: 4618 mov r0, r3
8007dc8: 3710 adds r7, #16
8007dca: 46bd mov sp, r7
8007dcc: bd80 pop {r7, pc}
8007dce: bf00 nop
8007dd0: 80002000 .word 0x80002000
08007dd4 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8007dd4: b480 push {r7}
8007dd6: b083 sub sp, #12
8007dd8: af00 add r7, sp, #0
8007dda: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8007ddc: 687b ldr r3, [r7, #4]
8007dde: 681b ldr r3, [r3, #0]
8007de0: 699b ldr r3, [r3, #24]
8007de2: f003 0302 and.w r3, r3, #2
8007de6: 2b02 cmp r3, #2
8007de8: d103 bne.n 8007df2 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8007dea: 687b ldr r3, [r7, #4]
8007dec: 681b ldr r3, [r3, #0]
8007dee: 2200 movs r2, #0
8007df0: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8007df2: 687b ldr r3, [r7, #4]
8007df4: 681b ldr r3, [r3, #0]
8007df6: 699b ldr r3, [r3, #24]
8007df8: f003 0301 and.w r3, r3, #1
8007dfc: 2b01 cmp r3, #1
8007dfe: d007 beq.n 8007e10 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8007e00: 687b ldr r3, [r7, #4]
8007e02: 681b ldr r3, [r3, #0]
8007e04: 699a ldr r2, [r3, #24]
8007e06: 687b ldr r3, [r7, #4]
8007e08: 681b ldr r3, [r3, #0]
8007e0a: f042 0201 orr.w r2, r2, #1
8007e0e: 619a str r2, [r3, #24]
}
}
8007e10: bf00 nop
8007e12: 370c adds r7, #12
8007e14: 46bd mov sp, r7
8007e16: f85d 7b04 ldr.w r7, [sp], #4
8007e1a: 4770 bx lr
08007e1c <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
8007e1c: b580 push {r7, lr}
8007e1e: b084 sub sp, #16
8007e20: af00 add r7, sp, #0
8007e22: 60f8 str r0, [r7, #12]
8007e24: 60b9 str r1, [r7, #8]
8007e26: 603b str r3, [r7, #0]
8007e28: 4613 mov r3, r2
8007e2a: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007e2c: e022 b.n 8007e74 <I2C_WaitOnFlagUntilTimeout+0x58>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007e2e: 683b ldr r3, [r7, #0]
8007e30: f1b3 3fff cmp.w r3, #4294967295
8007e34: d01e beq.n 8007e74 <I2C_WaitOnFlagUntilTimeout+0x58>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007e36: f7fc fdaf bl 8004998 <HAL_GetTick>
8007e3a: 4602 mov r2, r0
8007e3c: 69bb ldr r3, [r7, #24]
8007e3e: 1ad3 subs r3, r2, r3
8007e40: 683a ldr r2, [r7, #0]
8007e42: 429a cmp r2, r3
8007e44: d302 bcc.n 8007e4c <I2C_WaitOnFlagUntilTimeout+0x30>
8007e46: 683b ldr r3, [r7, #0]
8007e48: 2b00 cmp r3, #0
8007e4a: d113 bne.n 8007e74 <I2C_WaitOnFlagUntilTimeout+0x58>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007e4c: 68fb ldr r3, [r7, #12]
8007e4e: 6c5b ldr r3, [r3, #68] ; 0x44
8007e50: f043 0220 orr.w r2, r3, #32
8007e54: 68fb ldr r3, [r7, #12]
8007e56: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007e58: 68fb ldr r3, [r7, #12]
8007e5a: 2220 movs r2, #32
8007e5c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007e60: 68fb ldr r3, [r7, #12]
8007e62: 2200 movs r2, #0
8007e64: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007e68: 68fb ldr r3, [r7, #12]
8007e6a: 2200 movs r2, #0
8007e6c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007e70: 2301 movs r3, #1
8007e72: e00f b.n 8007e94 <I2C_WaitOnFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007e74: 68fb ldr r3, [r7, #12]
8007e76: 681b ldr r3, [r3, #0]
8007e78: 699a ldr r2, [r3, #24]
8007e7a: 68bb ldr r3, [r7, #8]
8007e7c: 4013 ands r3, r2
8007e7e: 68ba ldr r2, [r7, #8]
8007e80: 429a cmp r2, r3
8007e82: bf0c ite eq
8007e84: 2301 moveq r3, #1
8007e86: 2300 movne r3, #0
8007e88: b2db uxtb r3, r3
8007e8a: 461a mov r2, r3
8007e8c: 79fb ldrb r3, [r7, #7]
8007e8e: 429a cmp r2, r3
8007e90: d0cd beq.n 8007e2e <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8007e92: 2300 movs r3, #0
}
8007e94: 4618 mov r0, r3
8007e96: 3710 adds r7, #16
8007e98: 46bd mov sp, r7
8007e9a: bd80 pop {r7, pc}
08007e9c <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007e9c: b580 push {r7, lr}
8007e9e: b084 sub sp, #16
8007ea0: af00 add r7, sp, #0
8007ea2: 60f8 str r0, [r7, #12]
8007ea4: 60b9 str r1, [r7, #8]
8007ea6: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007ea8: e02c b.n 8007f04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007eaa: 687a ldr r2, [r7, #4]
8007eac: 68b9 ldr r1, [r7, #8]
8007eae: 68f8 ldr r0, [r7, #12]
8007eb0: f000 f870 bl 8007f94 <I2C_IsAcknowledgeFailed>
8007eb4: 4603 mov r3, r0
8007eb6: 2b00 cmp r3, #0
8007eb8: d001 beq.n 8007ebe <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007eba: 2301 movs r3, #1
8007ebc: e02a b.n 8007f14 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007ebe: 68bb ldr r3, [r7, #8]
8007ec0: f1b3 3fff cmp.w r3, #4294967295
8007ec4: d01e beq.n 8007f04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007ec6: f7fc fd67 bl 8004998 <HAL_GetTick>
8007eca: 4602 mov r2, r0
8007ecc: 687b ldr r3, [r7, #4]
8007ece: 1ad3 subs r3, r2, r3
8007ed0: 68ba ldr r2, [r7, #8]
8007ed2: 429a cmp r2, r3
8007ed4: d302 bcc.n 8007edc <I2C_WaitOnTXISFlagUntilTimeout+0x40>
8007ed6: 68bb ldr r3, [r7, #8]
8007ed8: 2b00 cmp r3, #0
8007eda: d113 bne.n 8007f04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007edc: 68fb ldr r3, [r7, #12]
8007ede: 6c5b ldr r3, [r3, #68] ; 0x44
8007ee0: f043 0220 orr.w r2, r3, #32
8007ee4: 68fb ldr r3, [r7, #12]
8007ee6: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007ee8: 68fb ldr r3, [r7, #12]
8007eea: 2220 movs r2, #32
8007eec: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007ef0: 68fb ldr r3, [r7, #12]
8007ef2: 2200 movs r2, #0
8007ef4: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007ef8: 68fb ldr r3, [r7, #12]
8007efa: 2200 movs r2, #0
8007efc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007f00: 2301 movs r3, #1
8007f02: e007 b.n 8007f14 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007f04: 68fb ldr r3, [r7, #12]
8007f06: 681b ldr r3, [r3, #0]
8007f08: 699b ldr r3, [r3, #24]
8007f0a: f003 0302 and.w r3, r3, #2
8007f0e: 2b02 cmp r3, #2
8007f10: d1cb bne.n 8007eaa <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8007f12: 2300 movs r3, #0
}
8007f14: 4618 mov r0, r3
8007f16: 3710 adds r7, #16
8007f18: 46bd mov sp, r7
8007f1a: bd80 pop {r7, pc}
08007f1c <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007f1c: b580 push {r7, lr}
8007f1e: b084 sub sp, #16
8007f20: af00 add r7, sp, #0
8007f22: 60f8 str r0, [r7, #12]
8007f24: 60b9 str r1, [r7, #8]
8007f26: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007f28: e028 b.n 8007f7c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007f2a: 687a ldr r2, [r7, #4]
8007f2c: 68b9 ldr r1, [r7, #8]
8007f2e: 68f8 ldr r0, [r7, #12]
8007f30: f000 f830 bl 8007f94 <I2C_IsAcknowledgeFailed>
8007f34: 4603 mov r3, r0
8007f36: 2b00 cmp r3, #0
8007f38: d001 beq.n 8007f3e <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007f3a: 2301 movs r3, #1
8007f3c: e026 b.n 8007f8c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007f3e: f7fc fd2b bl 8004998 <HAL_GetTick>
8007f42: 4602 mov r2, r0
8007f44: 687b ldr r3, [r7, #4]
8007f46: 1ad3 subs r3, r2, r3
8007f48: 68ba ldr r2, [r7, #8]
8007f4a: 429a cmp r2, r3
8007f4c: d302 bcc.n 8007f54 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
8007f4e: 68bb ldr r3, [r7, #8]
8007f50: 2b00 cmp r3, #0
8007f52: d113 bne.n 8007f7c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007f54: 68fb ldr r3, [r7, #12]
8007f56: 6c5b ldr r3, [r3, #68] ; 0x44
8007f58: f043 0220 orr.w r2, r3, #32
8007f5c: 68fb ldr r3, [r7, #12]
8007f5e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007f60: 68fb ldr r3, [r7, #12]
8007f62: 2220 movs r2, #32
8007f64: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007f68: 68fb ldr r3, [r7, #12]
8007f6a: 2200 movs r2, #0
8007f6c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007f70: 68fb ldr r3, [r7, #12]
8007f72: 2200 movs r2, #0
8007f74: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007f78: 2301 movs r3, #1
8007f7a: e007 b.n 8007f8c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007f7c: 68fb ldr r3, [r7, #12]
8007f7e: 681b ldr r3, [r3, #0]
8007f80: 699b ldr r3, [r3, #24]
8007f82: f003 0320 and.w r3, r3, #32
8007f86: 2b20 cmp r3, #32
8007f88: d1cf bne.n 8007f2a <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
8007f8a: 2300 movs r3, #0
}
8007f8c: 4618 mov r0, r3
8007f8e: 3710 adds r7, #16
8007f90: 46bd mov sp, r7
8007f92: bd80 pop {r7, pc}
08007f94 <I2C_IsAcknowledgeFailed>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007f94: b580 push {r7, lr}
8007f96: b084 sub sp, #16
8007f98: af00 add r7, sp, #0
8007f9a: 60f8 str r0, [r7, #12]
8007f9c: 60b9 str r1, [r7, #8]
8007f9e: 607a str r2, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8007fa0: 68fb ldr r3, [r7, #12]
8007fa2: 681b ldr r3, [r3, #0]
8007fa4: 699b ldr r3, [r3, #24]
8007fa6: f003 0310 and.w r3, r3, #16
8007faa: 2b10 cmp r3, #16
8007fac: d151 bne.n 8008052 <I2C_IsAcknowledgeFailed+0xbe>
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007fae: e022 b.n 8007ff6 <I2C_IsAcknowledgeFailed+0x62>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007fb0: 68bb ldr r3, [r7, #8]
8007fb2: f1b3 3fff cmp.w r3, #4294967295
8007fb6: d01e beq.n 8007ff6 <I2C_IsAcknowledgeFailed+0x62>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007fb8: f7fc fcee bl 8004998 <HAL_GetTick>
8007fbc: 4602 mov r2, r0
8007fbe: 687b ldr r3, [r7, #4]
8007fc0: 1ad3 subs r3, r2, r3
8007fc2: 68ba ldr r2, [r7, #8]
8007fc4: 429a cmp r2, r3
8007fc6: d302 bcc.n 8007fce <I2C_IsAcknowledgeFailed+0x3a>
8007fc8: 68bb ldr r3, [r7, #8]
8007fca: 2b00 cmp r3, #0
8007fcc: d113 bne.n 8007ff6 <I2C_IsAcknowledgeFailed+0x62>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007fce: 68fb ldr r3, [r7, #12]
8007fd0: 6c5b ldr r3, [r3, #68] ; 0x44
8007fd2: f043 0220 orr.w r2, r3, #32
8007fd6: 68fb ldr r3, [r7, #12]
8007fd8: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007fda: 68fb ldr r3, [r7, #12]
8007fdc: 2220 movs r2, #32
8007fde: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007fe2: 68fb ldr r3, [r7, #12]
8007fe4: 2200 movs r2, #0
8007fe6: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007fea: 68fb ldr r3, [r7, #12]
8007fec: 2200 movs r2, #0
8007fee: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007ff2: 2301 movs r3, #1
8007ff4: e02e b.n 8008054 <I2C_IsAcknowledgeFailed+0xc0>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007ff6: 68fb ldr r3, [r7, #12]
8007ff8: 681b ldr r3, [r3, #0]
8007ffa: 699b ldr r3, [r3, #24]
8007ffc: f003 0320 and.w r3, r3, #32
8008000: 2b20 cmp r3, #32
8008002: d1d5 bne.n 8007fb0 <I2C_IsAcknowledgeFailed+0x1c>
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8008004: 68fb ldr r3, [r7, #12]
8008006: 681b ldr r3, [r3, #0]
8008008: 2210 movs r2, #16
800800a: 61da str r2, [r3, #28]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800800c: 68fb ldr r3, [r7, #12]
800800e: 681b ldr r3, [r3, #0]
8008010: 2220 movs r2, #32
8008012: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8008014: 68f8 ldr r0, [r7, #12]
8008016: f7ff fedd bl 8007dd4 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800801a: 68fb ldr r3, [r7, #12]
800801c: 681b ldr r3, [r3, #0]
800801e: 6859 ldr r1, [r3, #4]
8008020: 68fb ldr r3, [r7, #12]
8008022: 681a ldr r2, [r3, #0]
8008024: 4b0d ldr r3, [pc, #52] ; (800805c <I2C_IsAcknowledgeFailed+0xc8>)
8008026: 400b ands r3, r1
8008028: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800802a: 68fb ldr r3, [r7, #12]
800802c: 6c5b ldr r3, [r3, #68] ; 0x44
800802e: f043 0204 orr.w r2, r3, #4
8008032: 68fb ldr r3, [r7, #12]
8008034: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8008036: 68fb ldr r3, [r7, #12]
8008038: 2220 movs r2, #32
800803a: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800803e: 68fb ldr r3, [r7, #12]
8008040: 2200 movs r2, #0
8008042: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8008046: 68fb ldr r3, [r7, #12]
8008048: 2200 movs r2, #0
800804a: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
800804e: 2301 movs r3, #1
8008050: e000 b.n 8008054 <I2C_IsAcknowledgeFailed+0xc0>
}
return HAL_OK;
8008052: 2300 movs r3, #0
}
8008054: 4618 mov r0, r3
8008056: 3710 adds r7, #16
8008058: 46bd mov sp, r7
800805a: bd80 pop {r7, pc}
800805c: fe00e800 .word 0xfe00e800
08008060 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
8008060: b480 push {r7}
8008062: b085 sub sp, #20
8008064: af00 add r7, sp, #0
8008066: 60f8 str r0, [r7, #12]
8008068: 607b str r3, [r7, #4]
800806a: 460b mov r3, r1
800806c: 817b strh r3, [r7, #10]
800806e: 4613 mov r3, r2
8008070: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
8008072: 68fb ldr r3, [r7, #12]
8008074: 681b ldr r3, [r3, #0]
8008076: 685a ldr r2, [r3, #4]
8008078: 69bb ldr r3, [r7, #24]
800807a: 0d5b lsrs r3, r3, #21
800807c: f403 6180 and.w r1, r3, #1024 ; 0x400
8008080: 4b0d ldr r3, [pc, #52] ; (80080b8 <I2C_TransferConfig+0x58>)
8008082: 430b orrs r3, r1
8008084: 43db mvns r3, r3
8008086: ea02 0103 and.w r1, r2, r3
800808a: 897b ldrh r3, [r7, #10]
800808c: f3c3 0209 ubfx r2, r3, #0, #10
8008090: 7a7b ldrb r3, [r7, #9]
8008092: 041b lsls r3, r3, #16
8008094: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8008098: 431a orrs r2, r3
800809a: 687b ldr r3, [r7, #4]
800809c: 431a orrs r2, r3
800809e: 69bb ldr r3, [r7, #24]
80080a0: 431a orrs r2, r3
80080a2: 68fb ldr r3, [r7, #12]
80080a4: 681b ldr r3, [r3, #0]
80080a6: 430a orrs r2, r1
80080a8: 605a str r2, [r3, #4]
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
80080aa: bf00 nop
80080ac: 3714 adds r7, #20
80080ae: 46bd mov sp, r7
80080b0: f85d 7b04 ldr.w r7, [sp], #4
80080b4: 4770 bx lr
80080b6: bf00 nop
80080b8: 03ff63ff .word 0x03ff63ff
080080bc <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
80080bc: b580 push {r7, lr}
80080be: b084 sub sp, #16
80080c0: af00 add r7, sp, #0
80080c2: 6078 str r0, [r7, #4]
uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
80080c4: 687b ldr r3, [r7, #4]
80080c6: 2b00 cmp r3, #0
80080c8: d101 bne.n 80080ce <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
80080ca: 2301 movs r3, #1
80080cc: e0bf b.n 800824e <HAL_LTDC_Init+0x192>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
80080ce: 687b ldr r3, [r7, #4]
80080d0: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
80080d4: b2db uxtb r3, r3
80080d6: 2b00 cmp r3, #0
80080d8: d106 bne.n 80080e8 <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
80080da: 687b ldr r3, [r7, #4]
80080dc: 2200 movs r2, #0
80080de: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
80080e2: 6878 ldr r0, [r7, #4]
80080e4: f7fb fffa bl 80040dc <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
80080e8: 687b ldr r3, [r7, #4]
80080ea: 2202 movs r2, #2
80080ec: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
80080f0: 687b ldr r3, [r7, #4]
80080f2: 681b ldr r3, [r3, #0]
80080f4: 699a ldr r2, [r3, #24]
80080f6: 687b ldr r3, [r7, #4]
80080f8: 681b ldr r3, [r3, #0]
80080fa: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
80080fe: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8008100: 687b ldr r3, [r7, #4]
8008102: 681b ldr r3, [r3, #0]
8008104: 6999 ldr r1, [r3, #24]
8008106: 687b ldr r3, [r7, #4]
8008108: 685a ldr r2, [r3, #4]
800810a: 687b ldr r3, [r7, #4]
800810c: 689b ldr r3, [r3, #8]
800810e: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8008110: 687b ldr r3, [r7, #4]
8008112: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8008114: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8008116: 687b ldr r3, [r7, #4]
8008118: 691b ldr r3, [r3, #16]
800811a: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
800811c: 687b ldr r3, [r7, #4]
800811e: 681b ldr r3, [r3, #0]
8008120: 430a orrs r2, r1
8008122: 619a str r2, [r3, #24]
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
8008124: 687b ldr r3, [r7, #4]
8008126: 681b ldr r3, [r3, #0]
8008128: 6899 ldr r1, [r3, #8]
800812a: 687b ldr r3, [r7, #4]
800812c: 681a ldr r2, [r3, #0]
800812e: 4b4a ldr r3, [pc, #296] ; (8008258 <HAL_LTDC_Init+0x19c>)
8008130: 400b ands r3, r1
8008132: 6093 str r3, [r2, #8]
tmp = (hltdc->Init.HorizontalSync << 16U);
8008134: 687b ldr r3, [r7, #4]
8008136: 695b ldr r3, [r3, #20]
8008138: 041b lsls r3, r3, #16
800813a: 60fb str r3, [r7, #12]
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
800813c: 687b ldr r3, [r7, #4]
800813e: 681b ldr r3, [r3, #0]
8008140: 6899 ldr r1, [r3, #8]
8008142: 687b ldr r3, [r7, #4]
8008144: 699a ldr r2, [r3, #24]
8008146: 68fb ldr r3, [r7, #12]
8008148: 431a orrs r2, r3
800814a: 687b ldr r3, [r7, #4]
800814c: 681b ldr r3, [r3, #0]
800814e: 430a orrs r2, r1
8008150: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
8008152: 687b ldr r3, [r7, #4]
8008154: 681b ldr r3, [r3, #0]
8008156: 68d9 ldr r1, [r3, #12]
8008158: 687b ldr r3, [r7, #4]
800815a: 681a ldr r2, [r3, #0]
800815c: 4b3e ldr r3, [pc, #248] ; (8008258 <HAL_LTDC_Init+0x19c>)
800815e: 400b ands r3, r1
8008160: 60d3 str r3, [r2, #12]
tmp = (hltdc->Init.AccumulatedHBP << 16U);
8008162: 687b ldr r3, [r7, #4]
8008164: 69db ldr r3, [r3, #28]
8008166: 041b lsls r3, r3, #16
8008168: 60fb str r3, [r7, #12]
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
800816a: 687b ldr r3, [r7, #4]
800816c: 681b ldr r3, [r3, #0]
800816e: 68d9 ldr r1, [r3, #12]
8008170: 687b ldr r3, [r7, #4]
8008172: 6a1a ldr r2, [r3, #32]
8008174: 68fb ldr r3, [r7, #12]
8008176: 431a orrs r2, r3
8008178: 687b ldr r3, [r7, #4]
800817a: 681b ldr r3, [r3, #0]
800817c: 430a orrs r2, r1
800817e: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
8008180: 687b ldr r3, [r7, #4]
8008182: 681b ldr r3, [r3, #0]
8008184: 6919 ldr r1, [r3, #16]
8008186: 687b ldr r3, [r7, #4]
8008188: 681a ldr r2, [r3, #0]
800818a: 4b33 ldr r3, [pc, #204] ; (8008258 <HAL_LTDC_Init+0x19c>)
800818c: 400b ands r3, r1
800818e: 6113 str r3, [r2, #16]
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
8008190: 687b ldr r3, [r7, #4]
8008192: 6a5b ldr r3, [r3, #36] ; 0x24
8008194: 041b lsls r3, r3, #16
8008196: 60fb str r3, [r7, #12]
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
8008198: 687b ldr r3, [r7, #4]
800819a: 681b ldr r3, [r3, #0]
800819c: 6919 ldr r1, [r3, #16]
800819e: 687b ldr r3, [r7, #4]
80081a0: 6a9a ldr r2, [r3, #40] ; 0x28
80081a2: 68fb ldr r3, [r7, #12]
80081a4: 431a orrs r2, r3
80081a6: 687b ldr r3, [r7, #4]
80081a8: 681b ldr r3, [r3, #0]
80081aa: 430a orrs r2, r1
80081ac: 611a str r2, [r3, #16]
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
80081ae: 687b ldr r3, [r7, #4]
80081b0: 681b ldr r3, [r3, #0]
80081b2: 6959 ldr r1, [r3, #20]
80081b4: 687b ldr r3, [r7, #4]
80081b6: 681a ldr r2, [r3, #0]
80081b8: 4b27 ldr r3, [pc, #156] ; (8008258 <HAL_LTDC_Init+0x19c>)
80081ba: 400b ands r3, r1
80081bc: 6153 str r3, [r2, #20]
tmp = (hltdc->Init.TotalWidth << 16U);
80081be: 687b ldr r3, [r7, #4]
80081c0: 6adb ldr r3, [r3, #44] ; 0x2c
80081c2: 041b lsls r3, r3, #16
80081c4: 60fb str r3, [r7, #12]
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
80081c6: 687b ldr r3, [r7, #4]
80081c8: 681b ldr r3, [r3, #0]
80081ca: 6959 ldr r1, [r3, #20]
80081cc: 687b ldr r3, [r7, #4]
80081ce: 6b1a ldr r2, [r3, #48] ; 0x30
80081d0: 68fb ldr r3, [r7, #12]
80081d2: 431a orrs r2, r3
80081d4: 687b ldr r3, [r7, #4]
80081d6: 681b ldr r3, [r3, #0]
80081d8: 430a orrs r2, r1
80081da: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
80081dc: 687b ldr r3, [r7, #4]
80081de: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
80081e2: 021b lsls r3, r3, #8
80081e4: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
80081e6: 687b ldr r3, [r7, #4]
80081e8: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
80081ec: 041b lsls r3, r3, #16
80081ee: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
80081f0: 687b ldr r3, [r7, #4]
80081f2: 681b ldr r3, [r3, #0]
80081f4: 6ada ldr r2, [r3, #44] ; 0x2c
80081f6: 687b ldr r3, [r7, #4]
80081f8: 681b ldr r3, [r3, #0]
80081fa: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
80081fe: 62da str r2, [r3, #44] ; 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8008200: 687b ldr r3, [r7, #4]
8008202: 681b ldr r3, [r3, #0]
8008204: 6ad9 ldr r1, [r3, #44] ; 0x2c
8008206: 68ba ldr r2, [r7, #8]
8008208: 68fb ldr r3, [r7, #12]
800820a: 4313 orrs r3, r2
800820c: 687a ldr r2, [r7, #4]
800820e: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
8008212: 431a orrs r2, r3
8008214: 687b ldr r3, [r7, #4]
8008216: 681b ldr r3, [r3, #0]
8008218: 430a orrs r2, r1
800821a: 62da str r2, [r3, #44] ; 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
800821c: 687b ldr r3, [r7, #4]
800821e: 681b ldr r3, [r3, #0]
8008220: 6b5a ldr r2, [r3, #52] ; 0x34
8008222: 687b ldr r3, [r7, #4]
8008224: 681b ldr r3, [r3, #0]
8008226: f042 0206 orr.w r2, r2, #6
800822a: 635a str r2, [r3, #52] ; 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
800822c: 687b ldr r3, [r7, #4]
800822e: 681b ldr r3, [r3, #0]
8008230: 699a ldr r2, [r3, #24]
8008232: 687b ldr r3, [r7, #4]
8008234: 681b ldr r3, [r3, #0]
8008236: f042 0201 orr.w r2, r2, #1
800823a: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
800823c: 687b ldr r3, [r7, #4]
800823e: 2200 movs r2, #0
8008240: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8008244: 687b ldr r3, [r7, #4]
8008246: 2201 movs r2, #1
8008248: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
return HAL_OK;
800824c: 2300 movs r3, #0
}
800824e: 4618 mov r0, r3
8008250: 3710 adds r7, #16
8008252: 46bd mov sp, r7
8008254: bd80 pop {r7, pc}
8008256: bf00 nop
8008258: f000f800 .word 0xf000f800
0800825c <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
800825c: b580 push {r7, lr}
800825e: b084 sub sp, #16
8008260: af00 add r7, sp, #0
8008262: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
8008264: 687b ldr r3, [r7, #4]
8008266: 681b ldr r3, [r3, #0]
8008268: 6b9b ldr r3, [r3, #56] ; 0x38
800826a: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
800826c: 687b ldr r3, [r7, #4]
800826e: 681b ldr r3, [r3, #0]
8008270: 6b5b ldr r3, [r3, #52] ; 0x34
8008272: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
8008274: 68fb ldr r3, [r7, #12]
8008276: f003 0304 and.w r3, r3, #4
800827a: 2b00 cmp r3, #0
800827c: d023 beq.n 80082c6 <HAL_LTDC_IRQHandler+0x6a>
800827e: 68bb ldr r3, [r7, #8]
8008280: f003 0304 and.w r3, r3, #4
8008284: 2b00 cmp r3, #0
8008286: d01e beq.n 80082c6 <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
8008288: 687b ldr r3, [r7, #4]
800828a: 681b ldr r3, [r3, #0]
800828c: 6b5a ldr r2, [r3, #52] ; 0x34
800828e: 687b ldr r3, [r7, #4]
8008290: 681b ldr r3, [r3, #0]
8008292: f022 0204 bic.w r2, r2, #4
8008296: 635a str r2, [r3, #52] ; 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
8008298: 687b ldr r3, [r7, #4]
800829a: 681b ldr r3, [r3, #0]
800829c: 2204 movs r2, #4
800829e: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
80082a0: 687b ldr r3, [r7, #4]
80082a2: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
80082a6: f043 0201 orr.w r2, r3, #1
80082aa: 687b ldr r3, [r7, #4]
80082ac: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
80082b0: 687b ldr r3, [r7, #4]
80082b2: 2204 movs r2, #4
80082b4: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80082b8: 687b ldr r3, [r7, #4]
80082ba: 2200 movs r2, #0
80082bc: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
80082c0: 6878 ldr r0, [r7, #4]
80082c2: f000 f86f bl 80083a4 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
80082c6: 68fb ldr r3, [r7, #12]
80082c8: f003 0302 and.w r3, r3, #2
80082cc: 2b00 cmp r3, #0
80082ce: d023 beq.n 8008318 <HAL_LTDC_IRQHandler+0xbc>
80082d0: 68bb ldr r3, [r7, #8]
80082d2: f003 0302 and.w r3, r3, #2
80082d6: 2b00 cmp r3, #0
80082d8: d01e beq.n 8008318 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
80082da: 687b ldr r3, [r7, #4]
80082dc: 681b ldr r3, [r3, #0]
80082de: 6b5a ldr r2, [r3, #52] ; 0x34
80082e0: 687b ldr r3, [r7, #4]
80082e2: 681b ldr r3, [r3, #0]
80082e4: f022 0202 bic.w r2, r2, #2
80082e8: 635a str r2, [r3, #52] ; 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
80082ea: 687b ldr r3, [r7, #4]
80082ec: 681b ldr r3, [r3, #0]
80082ee: 2202 movs r2, #2
80082f0: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
80082f2: 687b ldr r3, [r7, #4]
80082f4: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
80082f8: f043 0202 orr.w r2, r3, #2
80082fc: 687b ldr r3, [r7, #4]
80082fe: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
8008302: 687b ldr r3, [r7, #4]
8008304: 2204 movs r2, #4
8008306: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800830a: 687b ldr r3, [r7, #4]
800830c: 2200 movs r2, #0
800830e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
8008312: 6878 ldr r0, [r7, #4]
8008314: f000 f846 bl 80083a4 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
8008318: 68fb ldr r3, [r7, #12]
800831a: f003 0301 and.w r3, r3, #1
800831e: 2b00 cmp r3, #0
8008320: d01b beq.n 800835a <HAL_LTDC_IRQHandler+0xfe>
8008322: 68bb ldr r3, [r7, #8]
8008324: f003 0301 and.w r3, r3, #1
8008328: 2b00 cmp r3, #0
800832a: d016 beq.n 800835a <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
800832c: 687b ldr r3, [r7, #4]
800832e: 681b ldr r3, [r3, #0]
8008330: 6b5a ldr r2, [r3, #52] ; 0x34
8008332: 687b ldr r3, [r7, #4]
8008334: 681b ldr r3, [r3, #0]
8008336: f022 0201 bic.w r2, r2, #1
800833a: 635a str r2, [r3, #52] ; 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
800833c: 687b ldr r3, [r7, #4]
800833e: 681b ldr r3, [r3, #0]
8008340: 2201 movs r2, #1
8008342: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8008344: 687b ldr r3, [r7, #4]
8008346: 2201 movs r2, #1
8008348: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800834c: 687b ldr r3, [r7, #4]
800834e: 2200 movs r2, #0
8008350: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
8008354: 6878 ldr r0, [r7, #4]
8008356: f000 f82f bl 80083b8 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
800835a: 68fb ldr r3, [r7, #12]
800835c: f003 0308 and.w r3, r3, #8
8008360: 2b00 cmp r3, #0
8008362: d01b beq.n 800839c <HAL_LTDC_IRQHandler+0x140>
8008364: 68bb ldr r3, [r7, #8]
8008366: f003 0308 and.w r3, r3, #8
800836a: 2b00 cmp r3, #0
800836c: d016 beq.n 800839c <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
800836e: 687b ldr r3, [r7, #4]
8008370: 681b ldr r3, [r3, #0]
8008372: 6b5a ldr r2, [r3, #52] ; 0x34
8008374: 687b ldr r3, [r7, #4]
8008376: 681b ldr r3, [r3, #0]
8008378: f022 0208 bic.w r2, r2, #8
800837c: 635a str r2, [r3, #52] ; 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
800837e: 687b ldr r3, [r7, #4]
8008380: 681b ldr r3, [r3, #0]
8008382: 2208 movs r2, #8
8008384: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8008386: 687b ldr r3, [r7, #4]
8008388: 2201 movs r2, #1
800838a: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800838e: 687b ldr r3, [r7, #4]
8008390: 2200 movs r2, #0
8008392: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
8008396: 6878 ldr r0, [r7, #4]
8008398: f000 f818 bl 80083cc <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
800839c: bf00 nop
800839e: 3710 adds r7, #16
80083a0: 46bd mov sp, r7
80083a2: bd80 pop {r7, pc}
080083a4 <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
80083a4: b480 push {r7}
80083a6: b083 sub sp, #12
80083a8: af00 add r7, sp, #0
80083aa: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
80083ac: bf00 nop
80083ae: 370c adds r7, #12
80083b0: 46bd mov sp, r7
80083b2: f85d 7b04 ldr.w r7, [sp], #4
80083b6: 4770 bx lr
080083b8 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
80083b8: b480 push {r7}
80083ba: b083 sub sp, #12
80083bc: af00 add r7, sp, #0
80083be: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
80083c0: bf00 nop
80083c2: 370c adds r7, #12
80083c4: 46bd mov sp, r7
80083c6: f85d 7b04 ldr.w r7, [sp], #4
80083ca: 4770 bx lr
080083cc <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
80083cc: b480 push {r7}
80083ce: b083 sub sp, #12
80083d0: af00 add r7, sp, #0
80083d2: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
80083d4: bf00 nop
80083d6: 370c adds r7, #12
80083d8: 46bd mov sp, r7
80083da: f85d 7b04 ldr.w r7, [sp], #4
80083de: 4770 bx lr
080083e0 <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
80083e0: b5b0 push {r4, r5, r7, lr}
80083e2: b084 sub sp, #16
80083e4: af00 add r7, sp, #0
80083e6: 60f8 str r0, [r7, #12]
80083e8: 60b9 str r1, [r7, #8]
80083ea: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
80083ec: 68fb ldr r3, [r7, #12]
80083ee: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
80083f2: 2b01 cmp r3, #1
80083f4: d101 bne.n 80083fa <HAL_LTDC_ConfigLayer+0x1a>
80083f6: 2302 movs r3, #2
80083f8: e02c b.n 8008454 <HAL_LTDC_ConfigLayer+0x74>
80083fa: 68fb ldr r3, [r7, #12]
80083fc: 2201 movs r2, #1
80083fe: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8008402: 68fb ldr r3, [r7, #12]
8008404: 2202 movs r2, #2
8008406: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
800840a: 68fa ldr r2, [r7, #12]
800840c: 687b ldr r3, [r7, #4]
800840e: 2134 movs r1, #52 ; 0x34
8008410: fb01 f303 mul.w r3, r1, r3
8008414: 4413 add r3, r2
8008416: f103 0238 add.w r2, r3, #56 ; 0x38
800841a: 68bb ldr r3, [r7, #8]
800841c: 4614 mov r4, r2
800841e: 461d mov r5, r3
8008420: cd0f ldmia r5!, {r0, r1, r2, r3}
8008422: c40f stmia r4!, {r0, r1, r2, r3}
8008424: cd0f ldmia r5!, {r0, r1, r2, r3}
8008426: c40f stmia r4!, {r0, r1, r2, r3}
8008428: cd0f ldmia r5!, {r0, r1, r2, r3}
800842a: c40f stmia r4!, {r0, r1, r2, r3}
800842c: 682b ldr r3, [r5, #0]
800842e: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
8008430: 687a ldr r2, [r7, #4]
8008432: 68b9 ldr r1, [r7, #8]
8008434: 68f8 ldr r0, [r7, #12]
8008436: f000 f81f bl 8008478 <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
800843a: 68fb ldr r3, [r7, #12]
800843c: 681b ldr r3, [r3, #0]
800843e: 2201 movs r2, #1
8008440: 625a str r2, [r3, #36] ; 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8008442: 68fb ldr r3, [r7, #12]
8008444: 2201 movs r2, #1
8008446: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800844a: 68fb ldr r3, [r7, #12]
800844c: 2200 movs r2, #0
800844e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
return HAL_OK;
8008452: 2300 movs r3, #0
}
8008454: 4618 mov r0, r3
8008456: 3710 adds r7, #16
8008458: 46bd mov sp, r7
800845a: bdb0 pop {r4, r5, r7, pc}
0800845c <HAL_LTDC_GetState>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
{
800845c: b480 push {r7}
800845e: b083 sub sp, #12
8008460: af00 add r7, sp, #0
8008462: 6078 str r0, [r7, #4]
return hltdc->State;
8008464: 687b ldr r3, [r7, #4]
8008466: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
800846a: b2db uxtb r3, r3
}
800846c: 4618 mov r0, r3
800846e: 370c adds r7, #12
8008470: 46bd mov sp, r7
8008472: f85d 7b04 ldr.w r7, [sp], #4
8008476: 4770 bx lr
08008478 <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8008478: b480 push {r7}
800847a: b089 sub sp, #36 ; 0x24
800847c: af00 add r7, sp, #0
800847e: 60f8 str r0, [r7, #12]
8008480: 60b9 str r1, [r7, #8]
8008482: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
8008484: 68bb ldr r3, [r7, #8]
8008486: 685a ldr r2, [r3, #4]
8008488: 68fb ldr r3, [r7, #12]
800848a: 681b ldr r3, [r3, #0]
800848c: 68db ldr r3, [r3, #12]
800848e: 0c1b lsrs r3, r3, #16
8008490: f3c3 030b ubfx r3, r3, #0, #12
8008494: 4413 add r3, r2
8008496: 041b lsls r3, r3, #16
8008498: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
800849a: 68fb ldr r3, [r7, #12]
800849c: 681b ldr r3, [r3, #0]
800849e: 461a mov r2, r3
80084a0: 687b ldr r3, [r7, #4]
80084a2: 01db lsls r3, r3, #7
80084a4: 4413 add r3, r2
80084a6: 3384 adds r3, #132 ; 0x84
80084a8: 685b ldr r3, [r3, #4]
80084aa: 68fa ldr r2, [r7, #12]
80084ac: 6812 ldr r2, [r2, #0]
80084ae: 4611 mov r1, r2
80084b0: 687a ldr r2, [r7, #4]
80084b2: 01d2 lsls r2, r2, #7
80084b4: 440a add r2, r1
80084b6: 3284 adds r2, #132 ; 0x84
80084b8: f403 4370 and.w r3, r3, #61440 ; 0xf000
80084bc: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
80084be: 68bb ldr r3, [r7, #8]
80084c0: 681a ldr r2, [r3, #0]
80084c2: 68fb ldr r3, [r7, #12]
80084c4: 681b ldr r3, [r3, #0]
80084c6: 68db ldr r3, [r3, #12]
80084c8: 0c1b lsrs r3, r3, #16
80084ca: f3c3 030b ubfx r3, r3, #0, #12
80084ce: 4413 add r3, r2
80084d0: 1c5a adds r2, r3, #1
80084d2: 68fb ldr r3, [r7, #12]
80084d4: 681b ldr r3, [r3, #0]
80084d6: 4619 mov r1, r3
80084d8: 687b ldr r3, [r7, #4]
80084da: 01db lsls r3, r3, #7
80084dc: 440b add r3, r1
80084de: 3384 adds r3, #132 ; 0x84
80084e0: 4619 mov r1, r3
80084e2: 69fb ldr r3, [r7, #28]
80084e4: 4313 orrs r3, r2
80084e6: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
80084e8: 68bb ldr r3, [r7, #8]
80084ea: 68da ldr r2, [r3, #12]
80084ec: 68fb ldr r3, [r7, #12]
80084ee: 681b ldr r3, [r3, #0]
80084f0: 68db ldr r3, [r3, #12]
80084f2: f3c3 030a ubfx r3, r3, #0, #11
80084f6: 4413 add r3, r2
80084f8: 041b lsls r3, r3, #16
80084fa: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
80084fc: 68fb ldr r3, [r7, #12]
80084fe: 681b ldr r3, [r3, #0]
8008500: 461a mov r2, r3
8008502: 687b ldr r3, [r7, #4]
8008504: 01db lsls r3, r3, #7
8008506: 4413 add r3, r2
8008508: 3384 adds r3, #132 ; 0x84
800850a: 689b ldr r3, [r3, #8]
800850c: 68fa ldr r2, [r7, #12]
800850e: 6812 ldr r2, [r2, #0]
8008510: 4611 mov r1, r2
8008512: 687a ldr r2, [r7, #4]
8008514: 01d2 lsls r2, r2, #7
8008516: 440a add r2, r1
8008518: 3284 adds r2, #132 ; 0x84
800851a: f403 4370 and.w r3, r3, #61440 ; 0xf000
800851e: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
8008520: 68bb ldr r3, [r7, #8]
8008522: 689a ldr r2, [r3, #8]
8008524: 68fb ldr r3, [r7, #12]
8008526: 681b ldr r3, [r3, #0]
8008528: 68db ldr r3, [r3, #12]
800852a: f3c3 030a ubfx r3, r3, #0, #11
800852e: 4413 add r3, r2
8008530: 1c5a adds r2, r3, #1
8008532: 68fb ldr r3, [r7, #12]
8008534: 681b ldr r3, [r3, #0]
8008536: 4619 mov r1, r3
8008538: 687b ldr r3, [r7, #4]
800853a: 01db lsls r3, r3, #7
800853c: 440b add r3, r1
800853e: 3384 adds r3, #132 ; 0x84
8008540: 4619 mov r1, r3
8008542: 69fb ldr r3, [r7, #28]
8008544: 4313 orrs r3, r2
8008546: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
8008548: 68fb ldr r3, [r7, #12]
800854a: 681b ldr r3, [r3, #0]
800854c: 461a mov r2, r3
800854e: 687b ldr r3, [r7, #4]
8008550: 01db lsls r3, r3, #7
8008552: 4413 add r3, r2
8008554: 3384 adds r3, #132 ; 0x84
8008556: 691b ldr r3, [r3, #16]
8008558: 68fa ldr r2, [r7, #12]
800855a: 6812 ldr r2, [r2, #0]
800855c: 4611 mov r1, r2
800855e: 687a ldr r2, [r7, #4]
8008560: 01d2 lsls r2, r2, #7
8008562: 440a add r2, r1
8008564: 3284 adds r2, #132 ; 0x84
8008566: f023 0307 bic.w r3, r3, #7
800856a: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
800856c: 68fb ldr r3, [r7, #12]
800856e: 681b ldr r3, [r3, #0]
8008570: 461a mov r2, r3
8008572: 687b ldr r3, [r7, #4]
8008574: 01db lsls r3, r3, #7
8008576: 4413 add r3, r2
8008578: 3384 adds r3, #132 ; 0x84
800857a: 461a mov r2, r3
800857c: 68bb ldr r3, [r7, #8]
800857e: 691b ldr r3, [r3, #16]
8008580: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
8008582: 68bb ldr r3, [r7, #8]
8008584: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8008588: 021b lsls r3, r3, #8
800858a: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
800858c: 68bb ldr r3, [r7, #8]
800858e: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
8008592: 041b lsls r3, r3, #16
8008594: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
8008596: 68bb ldr r3, [r7, #8]
8008598: 699b ldr r3, [r3, #24]
800859a: 061b lsls r3, r3, #24
800859c: 617b str r3, [r7, #20]
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
800859e: 68fb ldr r3, [r7, #12]
80085a0: 681b ldr r3, [r3, #0]
80085a2: 461a mov r2, r3
80085a4: 687b ldr r3, [r7, #4]
80085a6: 01db lsls r3, r3, #7
80085a8: 4413 add r3, r2
80085aa: 3384 adds r3, #132 ; 0x84
80085ac: 699b ldr r3, [r3, #24]
80085ae: 68fb ldr r3, [r7, #12]
80085b0: 681b ldr r3, [r3, #0]
80085b2: 461a mov r2, r3
80085b4: 687b ldr r3, [r7, #4]
80085b6: 01db lsls r3, r3, #7
80085b8: 4413 add r3, r2
80085ba: 3384 adds r3, #132 ; 0x84
80085bc: 461a mov r2, r3
80085be: 2300 movs r3, #0
80085c0: 6193 str r3, [r2, #24]
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
80085c2: 68bb ldr r3, [r7, #8]
80085c4: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80085c8: 461a mov r2, r3
80085ca: 69fb ldr r3, [r7, #28]
80085cc: 431a orrs r2, r3
80085ce: 69bb ldr r3, [r7, #24]
80085d0: 431a orrs r2, r3
80085d2: 68fb ldr r3, [r7, #12]
80085d4: 681b ldr r3, [r3, #0]
80085d6: 4619 mov r1, r3
80085d8: 687b ldr r3, [r7, #4]
80085da: 01db lsls r3, r3, #7
80085dc: 440b add r3, r1
80085de: 3384 adds r3, #132 ; 0x84
80085e0: 4619 mov r1, r3
80085e2: 697b ldr r3, [r7, #20]
80085e4: 4313 orrs r3, r2
80085e6: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
80085e8: 68fb ldr r3, [r7, #12]
80085ea: 681b ldr r3, [r3, #0]
80085ec: 461a mov r2, r3
80085ee: 687b ldr r3, [r7, #4]
80085f0: 01db lsls r3, r3, #7
80085f2: 4413 add r3, r2
80085f4: 3384 adds r3, #132 ; 0x84
80085f6: 695b ldr r3, [r3, #20]
80085f8: 68fa ldr r2, [r7, #12]
80085fa: 6812 ldr r2, [r2, #0]
80085fc: 4611 mov r1, r2
80085fe: 687a ldr r2, [r7, #4]
8008600: 01d2 lsls r2, r2, #7
8008602: 440a add r2, r1
8008604: 3284 adds r2, #132 ; 0x84
8008606: f023 03ff bic.w r3, r3, #255 ; 0xff
800860a: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
800860c: 68fb ldr r3, [r7, #12]
800860e: 681b ldr r3, [r3, #0]
8008610: 461a mov r2, r3
8008612: 687b ldr r3, [r7, #4]
8008614: 01db lsls r3, r3, #7
8008616: 4413 add r3, r2
8008618: 3384 adds r3, #132 ; 0x84
800861a: 461a mov r2, r3
800861c: 68bb ldr r3, [r7, #8]
800861e: 695b ldr r3, [r3, #20]
8008620: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
8008622: 68fb ldr r3, [r7, #12]
8008624: 681b ldr r3, [r3, #0]
8008626: 461a mov r2, r3
8008628: 687b ldr r3, [r7, #4]
800862a: 01db lsls r3, r3, #7
800862c: 4413 add r3, r2
800862e: 3384 adds r3, #132 ; 0x84
8008630: 69da ldr r2, [r3, #28]
8008632: 68fb ldr r3, [r7, #12]
8008634: 681b ldr r3, [r3, #0]
8008636: 4619 mov r1, r3
8008638: 687b ldr r3, [r7, #4]
800863a: 01db lsls r3, r3, #7
800863c: 440b add r3, r1
800863e: 3384 adds r3, #132 ; 0x84
8008640: 4619 mov r1, r3
8008642: 4b58 ldr r3, [pc, #352] ; (80087a4 <LTDC_SetConfig+0x32c>)
8008644: 4013 ands r3, r2
8008646: 61cb str r3, [r1, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
8008648: 68bb ldr r3, [r7, #8]
800864a: 69da ldr r2, [r3, #28]
800864c: 68bb ldr r3, [r7, #8]
800864e: 6a1b ldr r3, [r3, #32]
8008650: 68f9 ldr r1, [r7, #12]
8008652: 6809 ldr r1, [r1, #0]
8008654: 4608 mov r0, r1
8008656: 6879 ldr r1, [r7, #4]
8008658: 01c9 lsls r1, r1, #7
800865a: 4401 add r1, r0
800865c: 3184 adds r1, #132 ; 0x84
800865e: 4313 orrs r3, r2
8008660: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
8008662: 68fb ldr r3, [r7, #12]
8008664: 681b ldr r3, [r3, #0]
8008666: 461a mov r2, r3
8008668: 687b ldr r3, [r7, #4]
800866a: 01db lsls r3, r3, #7
800866c: 4413 add r3, r2
800866e: 3384 adds r3, #132 ; 0x84
8008670: 6a9b ldr r3, [r3, #40] ; 0x28
8008672: 68fb ldr r3, [r7, #12]
8008674: 681b ldr r3, [r3, #0]
8008676: 461a mov r2, r3
8008678: 687b ldr r3, [r7, #4]
800867a: 01db lsls r3, r3, #7
800867c: 4413 add r3, r2
800867e: 3384 adds r3, #132 ; 0x84
8008680: 461a mov r2, r3
8008682: 2300 movs r3, #0
8008684: 6293 str r3, [r2, #40] ; 0x28
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
8008686: 68fb ldr r3, [r7, #12]
8008688: 681b ldr r3, [r3, #0]
800868a: 461a mov r2, r3
800868c: 687b ldr r3, [r7, #4]
800868e: 01db lsls r3, r3, #7
8008690: 4413 add r3, r2
8008692: 3384 adds r3, #132 ; 0x84
8008694: 461a mov r2, r3
8008696: 68bb ldr r3, [r7, #8]
8008698: 6a5b ldr r3, [r3, #36] ; 0x24
800869a: 6293 str r3, [r2, #40] ; 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
800869c: 68bb ldr r3, [r7, #8]
800869e: 691b ldr r3, [r3, #16]
80086a0: 2b00 cmp r3, #0
80086a2: d102 bne.n 80086aa <LTDC_SetConfig+0x232>
{
tmp = 4U;
80086a4: 2304 movs r3, #4
80086a6: 61fb str r3, [r7, #28]
80086a8: e01b b.n 80086e2 <LTDC_SetConfig+0x26a>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
80086aa: 68bb ldr r3, [r7, #8]
80086ac: 691b ldr r3, [r3, #16]
80086ae: 2b01 cmp r3, #1
80086b0: d102 bne.n 80086b8 <LTDC_SetConfig+0x240>
{
tmp = 3U;
80086b2: 2303 movs r3, #3
80086b4: 61fb str r3, [r7, #28]
80086b6: e014 b.n 80086e2 <LTDC_SetConfig+0x26a>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80086b8: 68bb ldr r3, [r7, #8]
80086ba: 691b ldr r3, [r3, #16]
80086bc: 2b04 cmp r3, #4
80086be: d00b beq.n 80086d8 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80086c0: 68bb ldr r3, [r7, #8]
80086c2: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80086c4: 2b02 cmp r3, #2
80086c6: d007 beq.n 80086d8 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80086c8: 68bb ldr r3, [r7, #8]
80086ca: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80086cc: 2b03 cmp r3, #3
80086ce: d003 beq.n 80086d8 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
80086d0: 68bb ldr r3, [r7, #8]
80086d2: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80086d4: 2b07 cmp r3, #7
80086d6: d102 bne.n 80086de <LTDC_SetConfig+0x266>
{
tmp = 2U;
80086d8: 2302 movs r3, #2
80086da: 61fb str r3, [r7, #28]
80086dc: e001 b.n 80086e2 <LTDC_SetConfig+0x26a>
}
else
{
tmp = 1U;
80086de: 2301 movs r3, #1
80086e0: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
80086e2: 68fb ldr r3, [r7, #12]
80086e4: 681b ldr r3, [r3, #0]
80086e6: 461a mov r2, r3
80086e8: 687b ldr r3, [r7, #4]
80086ea: 01db lsls r3, r3, #7
80086ec: 4413 add r3, r2
80086ee: 3384 adds r3, #132 ; 0x84
80086f0: 6adb ldr r3, [r3, #44] ; 0x2c
80086f2: 68fa ldr r2, [r7, #12]
80086f4: 6812 ldr r2, [r2, #0]
80086f6: 4611 mov r1, r2
80086f8: 687a ldr r2, [r7, #4]
80086fa: 01d2 lsls r2, r2, #7
80086fc: 440a add r2, r1
80086fe: 3284 adds r2, #132 ; 0x84
8008700: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
8008704: 62d3 str r3, [r2, #44] ; 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
8008706: 68bb ldr r3, [r7, #8]
8008708: 6a9b ldr r3, [r3, #40] ; 0x28
800870a: 69fa ldr r2, [r7, #28]
800870c: fb02 f303 mul.w r3, r2, r3
8008710: 041a lsls r2, r3, #16
8008712: 68bb ldr r3, [r7, #8]
8008714: 6859 ldr r1, [r3, #4]
8008716: 68bb ldr r3, [r7, #8]
8008718: 681b ldr r3, [r3, #0]
800871a: 1acb subs r3, r1, r3
800871c: 69f9 ldr r1, [r7, #28]
800871e: fb01 f303 mul.w r3, r1, r3
8008722: 3303 adds r3, #3
8008724: 68f9 ldr r1, [r7, #12]
8008726: 6809 ldr r1, [r1, #0]
8008728: 4608 mov r0, r1
800872a: 6879 ldr r1, [r7, #4]
800872c: 01c9 lsls r1, r1, #7
800872e: 4401 add r1, r0
8008730: 3184 adds r1, #132 ; 0x84
8008732: 4313 orrs r3, r2
8008734: 62cb str r3, [r1, #44] ; 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
8008736: 68fb ldr r3, [r7, #12]
8008738: 681b ldr r3, [r3, #0]
800873a: 461a mov r2, r3
800873c: 687b ldr r3, [r7, #4]
800873e: 01db lsls r3, r3, #7
8008740: 4413 add r3, r2
8008742: 3384 adds r3, #132 ; 0x84
8008744: 6b1a ldr r2, [r3, #48] ; 0x30
8008746: 68fb ldr r3, [r7, #12]
8008748: 681b ldr r3, [r3, #0]
800874a: 4619 mov r1, r3
800874c: 687b ldr r3, [r7, #4]
800874e: 01db lsls r3, r3, #7
8008750: 440b add r3, r1
8008752: 3384 adds r3, #132 ; 0x84
8008754: 4619 mov r1, r3
8008756: 4b14 ldr r3, [pc, #80] ; (80087a8 <LTDC_SetConfig+0x330>)
8008758: 4013 ands r3, r2
800875a: 630b str r3, [r1, #48] ; 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
800875c: 68fb ldr r3, [r7, #12]
800875e: 681b ldr r3, [r3, #0]
8008760: 461a mov r2, r3
8008762: 687b ldr r3, [r7, #4]
8008764: 01db lsls r3, r3, #7
8008766: 4413 add r3, r2
8008768: 3384 adds r3, #132 ; 0x84
800876a: 461a mov r2, r3
800876c: 68bb ldr r3, [r7, #8]
800876e: 6adb ldr r3, [r3, #44] ; 0x2c
8008770: 6313 str r3, [r2, #48] ; 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
8008772: 68fb ldr r3, [r7, #12]
8008774: 681b ldr r3, [r3, #0]
8008776: 461a mov r2, r3
8008778: 687b ldr r3, [r7, #4]
800877a: 01db lsls r3, r3, #7
800877c: 4413 add r3, r2
800877e: 3384 adds r3, #132 ; 0x84
8008780: 681b ldr r3, [r3, #0]
8008782: 68fa ldr r2, [r7, #12]
8008784: 6812 ldr r2, [r2, #0]
8008786: 4611 mov r1, r2
8008788: 687a ldr r2, [r7, #4]
800878a: 01d2 lsls r2, r2, #7
800878c: 440a add r2, r1
800878e: 3284 adds r2, #132 ; 0x84
8008790: f043 0301 orr.w r3, r3, #1
8008794: 6013 str r3, [r2, #0]
}
8008796: bf00 nop
8008798: 3724 adds r7, #36 ; 0x24
800879a: 46bd mov sp, r7
800879c: f85d 7b04 ldr.w r7, [sp], #4
80087a0: 4770 bx lr
80087a2: bf00 nop
80087a4: fffff8f8 .word 0xfffff8f8
80087a8: fffff800 .word 0xfffff800
080087ac <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
80087ac: b480 push {r7}
80087ae: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80087b0: 4b05 ldr r3, [pc, #20] ; (80087c8 <HAL_PWR_EnableBkUpAccess+0x1c>)
80087b2: 681b ldr r3, [r3, #0]
80087b4: 4a04 ldr r2, [pc, #16] ; (80087c8 <HAL_PWR_EnableBkUpAccess+0x1c>)
80087b6: f443 7380 orr.w r3, r3, #256 ; 0x100
80087ba: 6013 str r3, [r2, #0]
}
80087bc: bf00 nop
80087be: 46bd mov sp, r7
80087c0: f85d 7b04 ldr.w r7, [sp], #4
80087c4: 4770 bx lr
80087c6: bf00 nop
80087c8: 40007000 .word 0x40007000
080087cc <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
80087cc: b580 push {r7, lr}
80087ce: b082 sub sp, #8
80087d0: af00 add r7, sp, #0
uint32_t tickstart = 0;
80087d2: 2300 movs r3, #0
80087d4: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80087d6: 4b23 ldr r3, [pc, #140] ; (8008864 <HAL_PWREx_EnableOverDrive+0x98>)
80087d8: 6c1b ldr r3, [r3, #64] ; 0x40
80087da: 4a22 ldr r2, [pc, #136] ; (8008864 <HAL_PWREx_EnableOverDrive+0x98>)
80087dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80087e0: 6413 str r3, [r2, #64] ; 0x40
80087e2: 4b20 ldr r3, [pc, #128] ; (8008864 <HAL_PWREx_EnableOverDrive+0x98>)
80087e4: 6c1b ldr r3, [r3, #64] ; 0x40
80087e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80087ea: 603b str r3, [r7, #0]
80087ec: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
80087ee: 4b1e ldr r3, [pc, #120] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
80087f0: 681b ldr r3, [r3, #0]
80087f2: 4a1d ldr r2, [pc, #116] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
80087f4: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80087f8: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
80087fa: f7fc f8cd bl 8004998 <HAL_GetTick>
80087fe: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8008800: e009 b.n 8008816 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8008802: f7fc f8c9 bl 8004998 <HAL_GetTick>
8008806: 4602 mov r2, r0
8008808: 687b ldr r3, [r7, #4]
800880a: 1ad3 subs r3, r2, r3
800880c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008810: d901 bls.n 8008816 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8008812: 2303 movs r3, #3
8008814: e022 b.n 800885c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8008816: 4b14 ldr r3, [pc, #80] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
8008818: 685b ldr r3, [r3, #4]
800881a: f403 3380 and.w r3, r3, #65536 ; 0x10000
800881e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8008822: d1ee bne.n 8008802 <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8008824: 4b10 ldr r3, [pc, #64] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
8008826: 681b ldr r3, [r3, #0]
8008828: 4a0f ldr r2, [pc, #60] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
800882a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800882e: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8008830: f7fc f8b2 bl 8004998 <HAL_GetTick>
8008834: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8008836: e009 b.n 800884c <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8008838: f7fc f8ae bl 8004998 <HAL_GetTick>
800883c: 4602 mov r2, r0
800883e: 687b ldr r3, [r7, #4]
8008840: 1ad3 subs r3, r2, r3
8008842: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008846: d901 bls.n 800884c <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8008848: 2303 movs r3, #3
800884a: e007 b.n 800885c <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
800884c: 4b06 ldr r3, [pc, #24] ; (8008868 <HAL_PWREx_EnableOverDrive+0x9c>)
800884e: 685b ldr r3, [r3, #4]
8008850: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008854: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
8008858: d1ee bne.n 8008838 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
800885a: 2300 movs r3, #0
}
800885c: 4618 mov r0, r3
800885e: 3708 adds r7, #8
8008860: 46bd mov sp, r7
8008862: bd80 pop {r7, pc}
8008864: 40023800 .word 0x40023800
8008868: 40007000 .word 0x40007000
0800886c <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800886c: b580 push {r7, lr}
800886e: b086 sub sp, #24
8008870: af00 add r7, sp, #0
8008872: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
8008874: 2300 movs r3, #0
8008876: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8008878: 687b ldr r3, [r7, #4]
800887a: 2b00 cmp r3, #0
800887c: d101 bne.n 8008882 <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
800887e: 2301 movs r3, #1
8008880: e291 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8008882: 687b ldr r3, [r7, #4]
8008884: 681b ldr r3, [r3, #0]
8008886: f003 0301 and.w r3, r3, #1
800888a: 2b00 cmp r3, #0
800888c: f000 8087 beq.w 800899e <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8008890: 4b96 ldr r3, [pc, #600] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008892: 689b ldr r3, [r3, #8]
8008894: f003 030c and.w r3, r3, #12
8008898: 2b04 cmp r3, #4
800889a: d00c beq.n 80088b6 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
800889c: 4b93 ldr r3, [pc, #588] ; (8008aec <HAL_RCC_OscConfig+0x280>)
800889e: 689b ldr r3, [r3, #8]
80088a0: f003 030c and.w r3, r3, #12
80088a4: 2b08 cmp r3, #8
80088a6: d112 bne.n 80088ce <HAL_RCC_OscConfig+0x62>
80088a8: 4b90 ldr r3, [pc, #576] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088aa: 685b ldr r3, [r3, #4]
80088ac: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80088b0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80088b4: d10b bne.n 80088ce <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80088b6: 4b8d ldr r3, [pc, #564] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088b8: 681b ldr r3, [r3, #0]
80088ba: f403 3300 and.w r3, r3, #131072 ; 0x20000
80088be: 2b00 cmp r3, #0
80088c0: d06c beq.n 800899c <HAL_RCC_OscConfig+0x130>
80088c2: 687b ldr r3, [r7, #4]
80088c4: 685b ldr r3, [r3, #4]
80088c6: 2b00 cmp r3, #0
80088c8: d168 bne.n 800899c <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
80088ca: 2301 movs r3, #1
80088cc: e26b b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80088ce: 687b ldr r3, [r7, #4]
80088d0: 685b ldr r3, [r3, #4]
80088d2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80088d6: d106 bne.n 80088e6 <HAL_RCC_OscConfig+0x7a>
80088d8: 4b84 ldr r3, [pc, #528] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088da: 681b ldr r3, [r3, #0]
80088dc: 4a83 ldr r2, [pc, #524] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088de: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80088e2: 6013 str r3, [r2, #0]
80088e4: e02e b.n 8008944 <HAL_RCC_OscConfig+0xd8>
80088e6: 687b ldr r3, [r7, #4]
80088e8: 685b ldr r3, [r3, #4]
80088ea: 2b00 cmp r3, #0
80088ec: d10c bne.n 8008908 <HAL_RCC_OscConfig+0x9c>
80088ee: 4b7f ldr r3, [pc, #508] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088f0: 681b ldr r3, [r3, #0]
80088f2: 4a7e ldr r2, [pc, #504] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088f4: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80088f8: 6013 str r3, [r2, #0]
80088fa: 4b7c ldr r3, [pc, #496] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80088fc: 681b ldr r3, [r3, #0]
80088fe: 4a7b ldr r2, [pc, #492] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008900: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8008904: 6013 str r3, [r2, #0]
8008906: e01d b.n 8008944 <HAL_RCC_OscConfig+0xd8>
8008908: 687b ldr r3, [r7, #4]
800890a: 685b ldr r3, [r3, #4]
800890c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8008910: d10c bne.n 800892c <HAL_RCC_OscConfig+0xc0>
8008912: 4b76 ldr r3, [pc, #472] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008914: 681b ldr r3, [r3, #0]
8008916: 4a75 ldr r2, [pc, #468] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008918: f443 2380 orr.w r3, r3, #262144 ; 0x40000
800891c: 6013 str r3, [r2, #0]
800891e: 4b73 ldr r3, [pc, #460] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008920: 681b ldr r3, [r3, #0]
8008922: 4a72 ldr r2, [pc, #456] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008924: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8008928: 6013 str r3, [r2, #0]
800892a: e00b b.n 8008944 <HAL_RCC_OscConfig+0xd8>
800892c: 4b6f ldr r3, [pc, #444] ; (8008aec <HAL_RCC_OscConfig+0x280>)
800892e: 681b ldr r3, [r3, #0]
8008930: 4a6e ldr r2, [pc, #440] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008932: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8008936: 6013 str r3, [r2, #0]
8008938: 4b6c ldr r3, [pc, #432] ; (8008aec <HAL_RCC_OscConfig+0x280>)
800893a: 681b ldr r3, [r3, #0]
800893c: 4a6b ldr r2, [pc, #428] ; (8008aec <HAL_RCC_OscConfig+0x280>)
800893e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8008942: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8008944: 687b ldr r3, [r7, #4]
8008946: 685b ldr r3, [r3, #4]
8008948: 2b00 cmp r3, #0
800894a: d013 beq.n 8008974 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800894c: f7fc f824 bl 8004998 <HAL_GetTick>
8008950: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8008952: e008 b.n 8008966 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8008954: f7fc f820 bl 8004998 <HAL_GetTick>
8008958: 4602 mov r2, r0
800895a: 693b ldr r3, [r7, #16]
800895c: 1ad3 subs r3, r2, r3
800895e: 2b64 cmp r3, #100 ; 0x64
8008960: d901 bls.n 8008966 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8008962: 2303 movs r3, #3
8008964: e21f b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8008966: 4b61 ldr r3, [pc, #388] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008968: 681b ldr r3, [r3, #0]
800896a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800896e: 2b00 cmp r3, #0
8008970: d0f0 beq.n 8008954 <HAL_RCC_OscConfig+0xe8>
8008972: e014 b.n 800899e <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008974: f7fc f810 bl 8004998 <HAL_GetTick>
8008978: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800897a: e008 b.n 800898e <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800897c: f7fc f80c bl 8004998 <HAL_GetTick>
8008980: 4602 mov r2, r0
8008982: 693b ldr r3, [r7, #16]
8008984: 1ad3 subs r3, r2, r3
8008986: 2b64 cmp r3, #100 ; 0x64
8008988: d901 bls.n 800898e <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
800898a: 2303 movs r3, #3
800898c: e20b b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800898e: 4b57 ldr r3, [pc, #348] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008990: 681b ldr r3, [r3, #0]
8008992: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008996: 2b00 cmp r3, #0
8008998: d1f0 bne.n 800897c <HAL_RCC_OscConfig+0x110>
800899a: e000 b.n 800899e <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800899c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800899e: 687b ldr r3, [r7, #4]
80089a0: 681b ldr r3, [r3, #0]
80089a2: f003 0302 and.w r3, r3, #2
80089a6: 2b00 cmp r3, #0
80089a8: d069 beq.n 8008a7e <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80089aa: 4b50 ldr r3, [pc, #320] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089ac: 689b ldr r3, [r3, #8]
80089ae: f003 030c and.w r3, r3, #12
80089b2: 2b00 cmp r3, #0
80089b4: d00b beq.n 80089ce <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80089b6: 4b4d ldr r3, [pc, #308] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089b8: 689b ldr r3, [r3, #8]
80089ba: f003 030c and.w r3, r3, #12
80089be: 2b08 cmp r3, #8
80089c0: d11c bne.n 80089fc <HAL_RCC_OscConfig+0x190>
80089c2: 4b4a ldr r3, [pc, #296] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089c4: 685b ldr r3, [r3, #4]
80089c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80089ca: 2b00 cmp r3, #0
80089cc: d116 bne.n 80089fc <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80089ce: 4b47 ldr r3, [pc, #284] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089d0: 681b ldr r3, [r3, #0]
80089d2: f003 0302 and.w r3, r3, #2
80089d6: 2b00 cmp r3, #0
80089d8: d005 beq.n 80089e6 <HAL_RCC_OscConfig+0x17a>
80089da: 687b ldr r3, [r7, #4]
80089dc: 68db ldr r3, [r3, #12]
80089de: 2b01 cmp r3, #1
80089e0: d001 beq.n 80089e6 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
80089e2: 2301 movs r3, #1
80089e4: e1df b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80089e6: 4b41 ldr r3, [pc, #260] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089e8: 681b ldr r3, [r3, #0]
80089ea: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80089ee: 687b ldr r3, [r7, #4]
80089f0: 691b ldr r3, [r3, #16]
80089f2: 00db lsls r3, r3, #3
80089f4: 493d ldr r1, [pc, #244] ; (8008aec <HAL_RCC_OscConfig+0x280>)
80089f6: 4313 orrs r3, r2
80089f8: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80089fa: e040 b.n 8008a7e <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
80089fc: 687b ldr r3, [r7, #4]
80089fe: 68db ldr r3, [r3, #12]
8008a00: 2b00 cmp r3, #0
8008a02: d023 beq.n 8008a4c <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8008a04: 4b39 ldr r3, [pc, #228] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a06: 681b ldr r3, [r3, #0]
8008a08: 4a38 ldr r2, [pc, #224] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a0a: f043 0301 orr.w r3, r3, #1
8008a0e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a10: f7fb ffc2 bl 8004998 <HAL_GetTick>
8008a14: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008a16: e008 b.n 8008a2a <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008a18: f7fb ffbe bl 8004998 <HAL_GetTick>
8008a1c: 4602 mov r2, r0
8008a1e: 693b ldr r3, [r7, #16]
8008a20: 1ad3 subs r3, r2, r3
8008a22: 2b02 cmp r3, #2
8008a24: d901 bls.n 8008a2a <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8008a26: 2303 movs r3, #3
8008a28: e1bd b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008a2a: 4b30 ldr r3, [pc, #192] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a2c: 681b ldr r3, [r3, #0]
8008a2e: f003 0302 and.w r3, r3, #2
8008a32: 2b00 cmp r3, #0
8008a34: d0f0 beq.n 8008a18 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8008a36: 4b2d ldr r3, [pc, #180] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a38: 681b ldr r3, [r3, #0]
8008a3a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8008a3e: 687b ldr r3, [r7, #4]
8008a40: 691b ldr r3, [r3, #16]
8008a42: 00db lsls r3, r3, #3
8008a44: 4929 ldr r1, [pc, #164] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a46: 4313 orrs r3, r2
8008a48: 600b str r3, [r1, #0]
8008a4a: e018 b.n 8008a7e <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8008a4c: 4b27 ldr r3, [pc, #156] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a4e: 681b ldr r3, [r3, #0]
8008a50: 4a26 ldr r2, [pc, #152] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a52: f023 0301 bic.w r3, r3, #1
8008a56: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a58: f7fb ff9e bl 8004998 <HAL_GetTick>
8008a5c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8008a5e: e008 b.n 8008a72 <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008a60: f7fb ff9a bl 8004998 <HAL_GetTick>
8008a64: 4602 mov r2, r0
8008a66: 693b ldr r3, [r7, #16]
8008a68: 1ad3 subs r3, r2, r3
8008a6a: 2b02 cmp r3, #2
8008a6c: d901 bls.n 8008a72 <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8008a6e: 2303 movs r3, #3
8008a70: e199 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8008a72: 4b1e ldr r3, [pc, #120] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a74: 681b ldr r3, [r3, #0]
8008a76: f003 0302 and.w r3, r3, #2
8008a7a: 2b00 cmp r3, #0
8008a7c: d1f0 bne.n 8008a60 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8008a7e: 687b ldr r3, [r7, #4]
8008a80: 681b ldr r3, [r3, #0]
8008a82: f003 0308 and.w r3, r3, #8
8008a86: 2b00 cmp r3, #0
8008a88: d038 beq.n 8008afc <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8008a8a: 687b ldr r3, [r7, #4]
8008a8c: 695b ldr r3, [r3, #20]
8008a8e: 2b00 cmp r3, #0
8008a90: d019 beq.n 8008ac6 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8008a92: 4b16 ldr r3, [pc, #88] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a94: 6f5b ldr r3, [r3, #116] ; 0x74
8008a96: 4a15 ldr r2, [pc, #84] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008a98: f043 0301 orr.w r3, r3, #1
8008a9c: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a9e: f7fb ff7b bl 8004998 <HAL_GetTick>
8008aa2: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8008aa4: e008 b.n 8008ab8 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8008aa6: f7fb ff77 bl 8004998 <HAL_GetTick>
8008aaa: 4602 mov r2, r0
8008aac: 693b ldr r3, [r7, #16]
8008aae: 1ad3 subs r3, r2, r3
8008ab0: 2b02 cmp r3, #2
8008ab2: d901 bls.n 8008ab8 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8008ab4: 2303 movs r3, #3
8008ab6: e176 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8008ab8: 4b0c ldr r3, [pc, #48] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008aba: 6f5b ldr r3, [r3, #116] ; 0x74
8008abc: f003 0302 and.w r3, r3, #2
8008ac0: 2b00 cmp r3, #0
8008ac2: d0f0 beq.n 8008aa6 <HAL_RCC_OscConfig+0x23a>
8008ac4: e01a b.n 8008afc <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8008ac6: 4b09 ldr r3, [pc, #36] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008ac8: 6f5b ldr r3, [r3, #116] ; 0x74
8008aca: 4a08 ldr r2, [pc, #32] ; (8008aec <HAL_RCC_OscConfig+0x280>)
8008acc: f023 0301 bic.w r3, r3, #1
8008ad0: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008ad2: f7fb ff61 bl 8004998 <HAL_GetTick>
8008ad6: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008ad8: e00a b.n 8008af0 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8008ada: f7fb ff5d bl 8004998 <HAL_GetTick>
8008ade: 4602 mov r2, r0
8008ae0: 693b ldr r3, [r7, #16]
8008ae2: 1ad3 subs r3, r2, r3
8008ae4: 2b02 cmp r3, #2
8008ae6: d903 bls.n 8008af0 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8008ae8: 2303 movs r3, #3
8008aea: e15c b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
8008aec: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008af0: 4b91 ldr r3, [pc, #580] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008af2: 6f5b ldr r3, [r3, #116] ; 0x74
8008af4: f003 0302 and.w r3, r3, #2
8008af8: 2b00 cmp r3, #0
8008afa: d1ee bne.n 8008ada <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8008afc: 687b ldr r3, [r7, #4]
8008afe: 681b ldr r3, [r3, #0]
8008b00: f003 0304 and.w r3, r3, #4
8008b04: 2b00 cmp r3, #0
8008b06: f000 80a4 beq.w 8008c52 <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8008b0a: 4b8b ldr r3, [pc, #556] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b0c: 6c1b ldr r3, [r3, #64] ; 0x40
8008b0e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008b12: 2b00 cmp r3, #0
8008b14: d10d bne.n 8008b32 <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8008b16: 4b88 ldr r3, [pc, #544] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b18: 6c1b ldr r3, [r3, #64] ; 0x40
8008b1a: 4a87 ldr r2, [pc, #540] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b1c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8008b20: 6413 str r3, [r2, #64] ; 0x40
8008b22: 4b85 ldr r3, [pc, #532] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b24: 6c1b ldr r3, [r3, #64] ; 0x40
8008b26: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008b2a: 60bb str r3, [r7, #8]
8008b2c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8008b2e: 2301 movs r3, #1
8008b30: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b32: 4b82 ldr r3, [pc, #520] ; (8008d3c <HAL_RCC_OscConfig+0x4d0>)
8008b34: 681b ldr r3, [r3, #0]
8008b36: f403 7380 and.w r3, r3, #256 ; 0x100
8008b3a: 2b00 cmp r3, #0
8008b3c: d118 bne.n 8008b70 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8008b3e: 4b7f ldr r3, [pc, #508] ; (8008d3c <HAL_RCC_OscConfig+0x4d0>)
8008b40: 681b ldr r3, [r3, #0]
8008b42: 4a7e ldr r2, [pc, #504] ; (8008d3c <HAL_RCC_OscConfig+0x4d0>)
8008b44: f443 7380 orr.w r3, r3, #256 ; 0x100
8008b48: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8008b4a: f7fb ff25 bl 8004998 <HAL_GetTick>
8008b4e: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b50: e008 b.n 8008b64 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8008b52: f7fb ff21 bl 8004998 <HAL_GetTick>
8008b56: 4602 mov r2, r0
8008b58: 693b ldr r3, [r7, #16]
8008b5a: 1ad3 subs r3, r2, r3
8008b5c: 2b64 cmp r3, #100 ; 0x64
8008b5e: d901 bls.n 8008b64 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8008b60: 2303 movs r3, #3
8008b62: e120 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b64: 4b75 ldr r3, [pc, #468] ; (8008d3c <HAL_RCC_OscConfig+0x4d0>)
8008b66: 681b ldr r3, [r3, #0]
8008b68: f403 7380 and.w r3, r3, #256 ; 0x100
8008b6c: 2b00 cmp r3, #0
8008b6e: d0f0 beq.n 8008b52 <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8008b70: 687b ldr r3, [r7, #4]
8008b72: 689b ldr r3, [r3, #8]
8008b74: 2b01 cmp r3, #1
8008b76: d106 bne.n 8008b86 <HAL_RCC_OscConfig+0x31a>
8008b78: 4b6f ldr r3, [pc, #444] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b7a: 6f1b ldr r3, [r3, #112] ; 0x70
8008b7c: 4a6e ldr r2, [pc, #440] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b7e: f043 0301 orr.w r3, r3, #1
8008b82: 6713 str r3, [r2, #112] ; 0x70
8008b84: e02d b.n 8008be2 <HAL_RCC_OscConfig+0x376>
8008b86: 687b ldr r3, [r7, #4]
8008b88: 689b ldr r3, [r3, #8]
8008b8a: 2b00 cmp r3, #0
8008b8c: d10c bne.n 8008ba8 <HAL_RCC_OscConfig+0x33c>
8008b8e: 4b6a ldr r3, [pc, #424] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b90: 6f1b ldr r3, [r3, #112] ; 0x70
8008b92: 4a69 ldr r2, [pc, #420] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b94: f023 0301 bic.w r3, r3, #1
8008b98: 6713 str r3, [r2, #112] ; 0x70
8008b9a: 4b67 ldr r3, [pc, #412] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008b9c: 6f1b ldr r3, [r3, #112] ; 0x70
8008b9e: 4a66 ldr r2, [pc, #408] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008ba0: f023 0304 bic.w r3, r3, #4
8008ba4: 6713 str r3, [r2, #112] ; 0x70
8008ba6: e01c b.n 8008be2 <HAL_RCC_OscConfig+0x376>
8008ba8: 687b ldr r3, [r7, #4]
8008baa: 689b ldr r3, [r3, #8]
8008bac: 2b05 cmp r3, #5
8008bae: d10c bne.n 8008bca <HAL_RCC_OscConfig+0x35e>
8008bb0: 4b61 ldr r3, [pc, #388] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bb2: 6f1b ldr r3, [r3, #112] ; 0x70
8008bb4: 4a60 ldr r2, [pc, #384] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bb6: f043 0304 orr.w r3, r3, #4
8008bba: 6713 str r3, [r2, #112] ; 0x70
8008bbc: 4b5e ldr r3, [pc, #376] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bbe: 6f1b ldr r3, [r3, #112] ; 0x70
8008bc0: 4a5d ldr r2, [pc, #372] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bc2: f043 0301 orr.w r3, r3, #1
8008bc6: 6713 str r3, [r2, #112] ; 0x70
8008bc8: e00b b.n 8008be2 <HAL_RCC_OscConfig+0x376>
8008bca: 4b5b ldr r3, [pc, #364] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bcc: 6f1b ldr r3, [r3, #112] ; 0x70
8008bce: 4a5a ldr r2, [pc, #360] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bd0: f023 0301 bic.w r3, r3, #1
8008bd4: 6713 str r3, [r2, #112] ; 0x70
8008bd6: 4b58 ldr r3, [pc, #352] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bd8: 6f1b ldr r3, [r3, #112] ; 0x70
8008bda: 4a57 ldr r2, [pc, #348] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008bdc: f023 0304 bic.w r3, r3, #4
8008be0: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8008be2: 687b ldr r3, [r7, #4]
8008be4: 689b ldr r3, [r3, #8]
8008be6: 2b00 cmp r3, #0
8008be8: d015 beq.n 8008c16 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008bea: f7fb fed5 bl 8004998 <HAL_GetTick>
8008bee: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008bf0: e00a b.n 8008c08 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008bf2: f7fb fed1 bl 8004998 <HAL_GetTick>
8008bf6: 4602 mov r2, r0
8008bf8: 693b ldr r3, [r7, #16]
8008bfa: 1ad3 subs r3, r2, r3
8008bfc: f241 3288 movw r2, #5000 ; 0x1388
8008c00: 4293 cmp r3, r2
8008c02: d901 bls.n 8008c08 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8008c04: 2303 movs r3, #3
8008c06: e0ce b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008c08: 4b4b ldr r3, [pc, #300] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c0a: 6f1b ldr r3, [r3, #112] ; 0x70
8008c0c: f003 0302 and.w r3, r3, #2
8008c10: 2b00 cmp r3, #0
8008c12: d0ee beq.n 8008bf2 <HAL_RCC_OscConfig+0x386>
8008c14: e014 b.n 8008c40 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008c16: f7fb febf bl 8004998 <HAL_GetTick>
8008c1a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008c1c: e00a b.n 8008c34 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008c1e: f7fb febb bl 8004998 <HAL_GetTick>
8008c22: 4602 mov r2, r0
8008c24: 693b ldr r3, [r7, #16]
8008c26: 1ad3 subs r3, r2, r3
8008c28: f241 3288 movw r2, #5000 ; 0x1388
8008c2c: 4293 cmp r3, r2
8008c2e: d901 bls.n 8008c34 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8008c30: 2303 movs r3, #3
8008c32: e0b8 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008c34: 4b40 ldr r3, [pc, #256] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c36: 6f1b ldr r3, [r3, #112] ; 0x70
8008c38: f003 0302 and.w r3, r3, #2
8008c3c: 2b00 cmp r3, #0
8008c3e: d1ee bne.n 8008c1e <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8008c40: 7dfb ldrb r3, [r7, #23]
8008c42: 2b01 cmp r3, #1
8008c44: d105 bne.n 8008c52 <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8008c46: 4b3c ldr r3, [pc, #240] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c48: 6c1b ldr r3, [r3, #64] ; 0x40
8008c4a: 4a3b ldr r2, [pc, #236] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c4c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8008c50: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8008c52: 687b ldr r3, [r7, #4]
8008c54: 699b ldr r3, [r3, #24]
8008c56: 2b00 cmp r3, #0
8008c58: f000 80a4 beq.w 8008da4 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8008c5c: 4b36 ldr r3, [pc, #216] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c5e: 689b ldr r3, [r3, #8]
8008c60: f003 030c and.w r3, r3, #12
8008c64: 2b08 cmp r3, #8
8008c66: d06b beq.n 8008d40 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8008c68: 687b ldr r3, [r7, #4]
8008c6a: 699b ldr r3, [r3, #24]
8008c6c: 2b02 cmp r3, #2
8008c6e: d149 bne.n 8008d04 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008c70: 4b31 ldr r3, [pc, #196] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c72: 681b ldr r3, [r3, #0]
8008c74: 4a30 ldr r2, [pc, #192] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c76: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008c7a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008c7c: f7fb fe8c bl 8004998 <HAL_GetTick>
8008c80: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008c82: e008 b.n 8008c96 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008c84: f7fb fe88 bl 8004998 <HAL_GetTick>
8008c88: 4602 mov r2, r0
8008c8a: 693b ldr r3, [r7, #16]
8008c8c: 1ad3 subs r3, r2, r3
8008c8e: 2b02 cmp r3, #2
8008c90: d901 bls.n 8008c96 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8008c92: 2303 movs r3, #3
8008c94: e087 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008c96: 4b28 ldr r3, [pc, #160] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008c98: 681b ldr r3, [r3, #0]
8008c9a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008c9e: 2b00 cmp r3, #0
8008ca0: d1f0 bne.n 8008c84 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8008ca2: 687b ldr r3, [r7, #4]
8008ca4: 69da ldr r2, [r3, #28]
8008ca6: 687b ldr r3, [r7, #4]
8008ca8: 6a1b ldr r3, [r3, #32]
8008caa: 431a orrs r2, r3
8008cac: 687b ldr r3, [r7, #4]
8008cae: 6a5b ldr r3, [r3, #36] ; 0x24
8008cb0: 019b lsls r3, r3, #6
8008cb2: 431a orrs r2, r3
8008cb4: 687b ldr r3, [r7, #4]
8008cb6: 6a9b ldr r3, [r3, #40] ; 0x28
8008cb8: 085b lsrs r3, r3, #1
8008cba: 3b01 subs r3, #1
8008cbc: 041b lsls r3, r3, #16
8008cbe: 431a orrs r2, r3
8008cc0: 687b ldr r3, [r7, #4]
8008cc2: 6adb ldr r3, [r3, #44] ; 0x2c
8008cc4: 061b lsls r3, r3, #24
8008cc6: 4313 orrs r3, r2
8008cc8: 4a1b ldr r2, [pc, #108] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008cca: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8008cce: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8008cd0: 4b19 ldr r3, [pc, #100] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008cd2: 681b ldr r3, [r3, #0]
8008cd4: 4a18 ldr r2, [pc, #96] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008cd6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8008cda: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008cdc: f7fb fe5c bl 8004998 <HAL_GetTick>
8008ce0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008ce2: e008 b.n 8008cf6 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008ce4: f7fb fe58 bl 8004998 <HAL_GetTick>
8008ce8: 4602 mov r2, r0
8008cea: 693b ldr r3, [r7, #16]
8008cec: 1ad3 subs r3, r2, r3
8008cee: 2b02 cmp r3, #2
8008cf0: d901 bls.n 8008cf6 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8008cf2: 2303 movs r3, #3
8008cf4: e057 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008cf6: 4b10 ldr r3, [pc, #64] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008cf8: 681b ldr r3, [r3, #0]
8008cfa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008cfe: 2b00 cmp r3, #0
8008d00: d0f0 beq.n 8008ce4 <HAL_RCC_OscConfig+0x478>
8008d02: e04f b.n 8008da4 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008d04: 4b0c ldr r3, [pc, #48] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008d06: 681b ldr r3, [r3, #0]
8008d08: 4a0b ldr r2, [pc, #44] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008d0a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008d0e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008d10: f7fb fe42 bl 8004998 <HAL_GetTick>
8008d14: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008d16: e008 b.n 8008d2a <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008d18: f7fb fe3e bl 8004998 <HAL_GetTick>
8008d1c: 4602 mov r2, r0
8008d1e: 693b ldr r3, [r7, #16]
8008d20: 1ad3 subs r3, r2, r3
8008d22: 2b02 cmp r3, #2
8008d24: d901 bls.n 8008d2a <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8008d26: 2303 movs r3, #3
8008d28: e03d b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008d2a: 4b03 ldr r3, [pc, #12] ; (8008d38 <HAL_RCC_OscConfig+0x4cc>)
8008d2c: 681b ldr r3, [r3, #0]
8008d2e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008d32: 2b00 cmp r3, #0
8008d34: d1f0 bne.n 8008d18 <HAL_RCC_OscConfig+0x4ac>
8008d36: e035 b.n 8008da4 <HAL_RCC_OscConfig+0x538>
8008d38: 40023800 .word 0x40023800
8008d3c: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8008d40: 4b1b ldr r3, [pc, #108] ; (8008db0 <HAL_RCC_OscConfig+0x544>)
8008d42: 685b ldr r3, [r3, #4]
8008d44: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008d46: 687b ldr r3, [r7, #4]
8008d48: 699b ldr r3, [r3, #24]
8008d4a: 2b01 cmp r3, #1
8008d4c: d028 beq.n 8008da0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008d4e: 68fb ldr r3, [r7, #12]
8008d50: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8008d54: 687b ldr r3, [r7, #4]
8008d56: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008d58: 429a cmp r2, r3
8008d5a: d121 bne.n 8008da0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008d5c: 68fb ldr r3, [r7, #12]
8008d5e: f003 023f and.w r2, r3, #63 ; 0x3f
8008d62: 687b ldr r3, [r7, #4]
8008d64: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008d66: 429a cmp r2, r3
8008d68: d11a bne.n 8008da0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008d6a: 68fa ldr r2, [r7, #12]
8008d6c: f647 73c0 movw r3, #32704 ; 0x7fc0
8008d70: 4013 ands r3, r2
8008d72: 687a ldr r2, [r7, #4]
8008d74: 6a52 ldr r2, [r2, #36] ; 0x24
8008d76: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008d78: 4293 cmp r3, r2
8008d7a: d111 bne.n 8008da0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008d7c: 68fb ldr r3, [r7, #12]
8008d7e: f403 3240 and.w r2, r3, #196608 ; 0x30000
8008d82: 687b ldr r3, [r7, #4]
8008d84: 6a9b ldr r3, [r3, #40] ; 0x28
8008d86: 085b lsrs r3, r3, #1
8008d88: 3b01 subs r3, #1
8008d8a: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008d8c: 429a cmp r2, r3
8008d8e: d107 bne.n 8008da0 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8008d90: 68fb ldr r3, [r7, #12]
8008d92: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8008d96: 687b ldr r3, [r7, #4]
8008d98: 6adb ldr r3, [r3, #44] ; 0x2c
8008d9a: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008d9c: 429a cmp r2, r3
8008d9e: d001 beq.n 8008da4 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8008da0: 2301 movs r3, #1
8008da2: e000 b.n 8008da6 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8008da4: 2300 movs r3, #0
}
8008da6: 4618 mov r0, r3
8008da8: 3718 adds r7, #24
8008daa: 46bd mov sp, r7
8008dac: bd80 pop {r7, pc}
8008dae: bf00 nop
8008db0: 40023800 .word 0x40023800
08008db4 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8008db4: b580 push {r7, lr}
8008db6: b084 sub sp, #16
8008db8: af00 add r7, sp, #0
8008dba: 6078 str r0, [r7, #4]
8008dbc: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8008dbe: 2300 movs r3, #0
8008dc0: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8008dc2: 687b ldr r3, [r7, #4]
8008dc4: 2b00 cmp r3, #0
8008dc6: d101 bne.n 8008dcc <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8008dc8: 2301 movs r3, #1
8008dca: e0d0 b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8008dcc: 4b6a ldr r3, [pc, #424] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008dce: 681b ldr r3, [r3, #0]
8008dd0: f003 030f and.w r3, r3, #15
8008dd4: 683a ldr r2, [r7, #0]
8008dd6: 429a cmp r2, r3
8008dd8: d910 bls.n 8008dfc <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008dda: 4b67 ldr r3, [pc, #412] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008ddc: 681b ldr r3, [r3, #0]
8008dde: f023 020f bic.w r2, r3, #15
8008de2: 4965 ldr r1, [pc, #404] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008de4: 683b ldr r3, [r7, #0]
8008de6: 4313 orrs r3, r2
8008de8: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008dea: 4b63 ldr r3, [pc, #396] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008dec: 681b ldr r3, [r3, #0]
8008dee: f003 030f and.w r3, r3, #15
8008df2: 683a ldr r2, [r7, #0]
8008df4: 429a cmp r2, r3
8008df6: d001 beq.n 8008dfc <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8008df8: 2301 movs r3, #1
8008dfa: e0b8 b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8008dfc: 687b ldr r3, [r7, #4]
8008dfe: 681b ldr r3, [r3, #0]
8008e00: f003 0302 and.w r3, r3, #2
8008e04: 2b00 cmp r3, #0
8008e06: d020 beq.n 8008e4a <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008e08: 687b ldr r3, [r7, #4]
8008e0a: 681b ldr r3, [r3, #0]
8008e0c: f003 0304 and.w r3, r3, #4
8008e10: 2b00 cmp r3, #0
8008e12: d005 beq.n 8008e20 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8008e14: 4b59 ldr r3, [pc, #356] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e16: 689b ldr r3, [r3, #8]
8008e18: 4a58 ldr r2, [pc, #352] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e1a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8008e1e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008e20: 687b ldr r3, [r7, #4]
8008e22: 681b ldr r3, [r3, #0]
8008e24: f003 0308 and.w r3, r3, #8
8008e28: 2b00 cmp r3, #0
8008e2a: d005 beq.n 8008e38 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8008e2c: 4b53 ldr r3, [pc, #332] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e2e: 689b ldr r3, [r3, #8]
8008e30: 4a52 ldr r2, [pc, #328] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e32: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8008e36: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8008e38: 4b50 ldr r3, [pc, #320] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e3a: 689b ldr r3, [r3, #8]
8008e3c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8008e40: 687b ldr r3, [r7, #4]
8008e42: 689b ldr r3, [r3, #8]
8008e44: 494d ldr r1, [pc, #308] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e46: 4313 orrs r3, r2
8008e48: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8008e4a: 687b ldr r3, [r7, #4]
8008e4c: 681b ldr r3, [r3, #0]
8008e4e: f003 0301 and.w r3, r3, #1
8008e52: 2b00 cmp r3, #0
8008e54: d040 beq.n 8008ed8 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8008e56: 687b ldr r3, [r7, #4]
8008e58: 685b ldr r3, [r3, #4]
8008e5a: 2b01 cmp r3, #1
8008e5c: d107 bne.n 8008e6e <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8008e5e: 4b47 ldr r3, [pc, #284] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e60: 681b ldr r3, [r3, #0]
8008e62: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008e66: 2b00 cmp r3, #0
8008e68: d115 bne.n 8008e96 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e6a: 2301 movs r3, #1
8008e6c: e07f b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8008e6e: 687b ldr r3, [r7, #4]
8008e70: 685b ldr r3, [r3, #4]
8008e72: 2b02 cmp r3, #2
8008e74: d107 bne.n 8008e86 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008e76: 4b41 ldr r3, [pc, #260] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e78: 681b ldr r3, [r3, #0]
8008e7a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008e7e: 2b00 cmp r3, #0
8008e80: d109 bne.n 8008e96 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e82: 2301 movs r3, #1
8008e84: e073 b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008e86: 4b3d ldr r3, [pc, #244] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e88: 681b ldr r3, [r3, #0]
8008e8a: f003 0302 and.w r3, r3, #2
8008e8e: 2b00 cmp r3, #0
8008e90: d101 bne.n 8008e96 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e92: 2301 movs r3, #1
8008e94: e06b b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8008e96: 4b39 ldr r3, [pc, #228] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008e98: 689b ldr r3, [r3, #8]
8008e9a: f023 0203 bic.w r2, r3, #3
8008e9e: 687b ldr r3, [r7, #4]
8008ea0: 685b ldr r3, [r3, #4]
8008ea2: 4936 ldr r1, [pc, #216] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008ea4: 4313 orrs r3, r2
8008ea6: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008ea8: f7fb fd76 bl 8004998 <HAL_GetTick>
8008eac: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008eae: e00a b.n 8008ec6 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8008eb0: f7fb fd72 bl 8004998 <HAL_GetTick>
8008eb4: 4602 mov r2, r0
8008eb6: 68fb ldr r3, [r7, #12]
8008eb8: 1ad3 subs r3, r2, r3
8008eba: f241 3288 movw r2, #5000 ; 0x1388
8008ebe: 4293 cmp r3, r2
8008ec0: d901 bls.n 8008ec6 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8008ec2: 2303 movs r3, #3
8008ec4: e053 b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008ec6: 4b2d ldr r3, [pc, #180] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008ec8: 689b ldr r3, [r3, #8]
8008eca: f003 020c and.w r2, r3, #12
8008ece: 687b ldr r3, [r7, #4]
8008ed0: 685b ldr r3, [r3, #4]
8008ed2: 009b lsls r3, r3, #2
8008ed4: 429a cmp r2, r3
8008ed6: d1eb bne.n 8008eb0 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8008ed8: 4b27 ldr r3, [pc, #156] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008eda: 681b ldr r3, [r3, #0]
8008edc: f003 030f and.w r3, r3, #15
8008ee0: 683a ldr r2, [r7, #0]
8008ee2: 429a cmp r2, r3
8008ee4: d210 bcs.n 8008f08 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008ee6: 4b24 ldr r3, [pc, #144] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008ee8: 681b ldr r3, [r3, #0]
8008eea: f023 020f bic.w r2, r3, #15
8008eee: 4922 ldr r1, [pc, #136] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008ef0: 683b ldr r3, [r7, #0]
8008ef2: 4313 orrs r3, r2
8008ef4: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008ef6: 4b20 ldr r3, [pc, #128] ; (8008f78 <HAL_RCC_ClockConfig+0x1c4>)
8008ef8: 681b ldr r3, [r3, #0]
8008efa: f003 030f and.w r3, r3, #15
8008efe: 683a ldr r2, [r7, #0]
8008f00: 429a cmp r2, r3
8008f02: d001 beq.n 8008f08 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8008f04: 2301 movs r3, #1
8008f06: e032 b.n 8008f6e <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008f08: 687b ldr r3, [r7, #4]
8008f0a: 681b ldr r3, [r3, #0]
8008f0c: f003 0304 and.w r3, r3, #4
8008f10: 2b00 cmp r3, #0
8008f12: d008 beq.n 8008f26 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8008f14: 4b19 ldr r3, [pc, #100] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008f16: 689b ldr r3, [r3, #8]
8008f18: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8008f1c: 687b ldr r3, [r7, #4]
8008f1e: 68db ldr r3, [r3, #12]
8008f20: 4916 ldr r1, [pc, #88] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008f22: 4313 orrs r3, r2
8008f24: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008f26: 687b ldr r3, [r7, #4]
8008f28: 681b ldr r3, [r3, #0]
8008f2a: f003 0308 and.w r3, r3, #8
8008f2e: 2b00 cmp r3, #0
8008f30: d009 beq.n 8008f46 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8008f32: 4b12 ldr r3, [pc, #72] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008f34: 689b ldr r3, [r3, #8]
8008f36: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8008f3a: 687b ldr r3, [r7, #4]
8008f3c: 691b ldr r3, [r3, #16]
8008f3e: 00db lsls r3, r3, #3
8008f40: 490e ldr r1, [pc, #56] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008f42: 4313 orrs r3, r2
8008f44: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8008f46: f000 f821 bl 8008f8c <HAL_RCC_GetSysClockFreq>
8008f4a: 4601 mov r1, r0
8008f4c: 4b0b ldr r3, [pc, #44] ; (8008f7c <HAL_RCC_ClockConfig+0x1c8>)
8008f4e: 689b ldr r3, [r3, #8]
8008f50: 091b lsrs r3, r3, #4
8008f52: f003 030f and.w r3, r3, #15
8008f56: 4a0a ldr r2, [pc, #40] ; (8008f80 <HAL_RCC_ClockConfig+0x1cc>)
8008f58: 5cd3 ldrb r3, [r2, r3]
8008f5a: fa21 f303 lsr.w r3, r1, r3
8008f5e: 4a09 ldr r2, [pc, #36] ; (8008f84 <HAL_RCC_ClockConfig+0x1d0>)
8008f60: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8008f62: 4b09 ldr r3, [pc, #36] ; (8008f88 <HAL_RCC_ClockConfig+0x1d4>)
8008f64: 681b ldr r3, [r3, #0]
8008f66: 4618 mov r0, r3
8008f68: f7fb fb78 bl 800465c <HAL_InitTick>
return HAL_OK;
8008f6c: 2300 movs r3, #0
}
8008f6e: 4618 mov r0, r3
8008f70: 3710 adds r7, #16
8008f72: 46bd mov sp, r7
8008f74: bd80 pop {r7, pc}
8008f76: bf00 nop
8008f78: 40023c00 .word 0x40023c00
8008f7c: 40023800 .word 0x40023800
8008f80: 08020d28 .word 0x08020d28
8008f84: 20000064 .word 0x20000064
8008f88: 20000068 .word 0x20000068
08008f8c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8008f8c: b5f0 push {r4, r5, r6, r7, lr}
8008f8e: b085 sub sp, #20
8008f90: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8008f92: 2300 movs r3, #0
8008f94: 607b str r3, [r7, #4]
8008f96: 2300 movs r3, #0
8008f98: 60fb str r3, [r7, #12]
8008f9a: 2300 movs r3, #0
8008f9c: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
8008f9e: 2300 movs r3, #0
8008fa0: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8008fa2: 4b50 ldr r3, [pc, #320] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
8008fa4: 689b ldr r3, [r3, #8]
8008fa6: f003 030c and.w r3, r3, #12
8008faa: 2b04 cmp r3, #4
8008fac: d007 beq.n 8008fbe <HAL_RCC_GetSysClockFreq+0x32>
8008fae: 2b08 cmp r3, #8
8008fb0: d008 beq.n 8008fc4 <HAL_RCC_GetSysClockFreq+0x38>
8008fb2: 2b00 cmp r3, #0
8008fb4: f040 808d bne.w 80090d2 <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8008fb8: 4b4b ldr r3, [pc, #300] ; (80090e8 <HAL_RCC_GetSysClockFreq+0x15c>)
8008fba: 60bb str r3, [r7, #8]
break;
8008fbc: e08c b.n 80090d8 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8008fbe: 4b4b ldr r3, [pc, #300] ; (80090ec <HAL_RCC_GetSysClockFreq+0x160>)
8008fc0: 60bb str r3, [r7, #8]
break;
8008fc2: e089 b.n 80090d8 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8008fc4: 4b47 ldr r3, [pc, #284] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
8008fc6: 685b ldr r3, [r3, #4]
8008fc8: f003 033f and.w r3, r3, #63 ; 0x3f
8008fcc: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8008fce: 4b45 ldr r3, [pc, #276] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
8008fd0: 685b ldr r3, [r3, #4]
8008fd2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8008fd6: 2b00 cmp r3, #0
8008fd8: d023 beq.n 8009022 <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8008fda: 4b42 ldr r3, [pc, #264] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
8008fdc: 685b ldr r3, [r3, #4]
8008fde: 099b lsrs r3, r3, #6
8008fe0: f04f 0400 mov.w r4, #0
8008fe4: f240 11ff movw r1, #511 ; 0x1ff
8008fe8: f04f 0200 mov.w r2, #0
8008fec: ea03 0501 and.w r5, r3, r1
8008ff0: ea04 0602 and.w r6, r4, r2
8008ff4: 4a3d ldr r2, [pc, #244] ; (80090ec <HAL_RCC_GetSysClockFreq+0x160>)
8008ff6: fb02 f106 mul.w r1, r2, r6
8008ffa: 2200 movs r2, #0
8008ffc: fb02 f205 mul.w r2, r2, r5
8009000: 440a add r2, r1
8009002: 493a ldr r1, [pc, #232] ; (80090ec <HAL_RCC_GetSysClockFreq+0x160>)
8009004: fba5 0101 umull r0, r1, r5, r1
8009008: 1853 adds r3, r2, r1
800900a: 4619 mov r1, r3
800900c: 687b ldr r3, [r7, #4]
800900e: f04f 0400 mov.w r4, #0
8009012: 461a mov r2, r3
8009014: 4623 mov r3, r4
8009016: f7f7 f94b bl 80002b0 <__aeabi_uldivmod>
800901a: 4603 mov r3, r0
800901c: 460c mov r4, r1
800901e: 60fb str r3, [r7, #12]
8009020: e049 b.n 80090b6 <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8009022: 4b30 ldr r3, [pc, #192] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
8009024: 685b ldr r3, [r3, #4]
8009026: 099b lsrs r3, r3, #6
8009028: f04f 0400 mov.w r4, #0
800902c: f240 11ff movw r1, #511 ; 0x1ff
8009030: f04f 0200 mov.w r2, #0
8009034: ea03 0501 and.w r5, r3, r1
8009038: ea04 0602 and.w r6, r4, r2
800903c: 4629 mov r1, r5
800903e: 4632 mov r2, r6
8009040: f04f 0300 mov.w r3, #0
8009044: f04f 0400 mov.w r4, #0
8009048: 0154 lsls r4, r2, #5
800904a: ea44 64d1 orr.w r4, r4, r1, lsr #27
800904e: 014b lsls r3, r1, #5
8009050: 4619 mov r1, r3
8009052: 4622 mov r2, r4
8009054: 1b49 subs r1, r1, r5
8009056: eb62 0206 sbc.w r2, r2, r6
800905a: f04f 0300 mov.w r3, #0
800905e: f04f 0400 mov.w r4, #0
8009062: 0194 lsls r4, r2, #6
8009064: ea44 6491 orr.w r4, r4, r1, lsr #26
8009068: 018b lsls r3, r1, #6
800906a: 1a5b subs r3, r3, r1
800906c: eb64 0402 sbc.w r4, r4, r2
8009070: f04f 0100 mov.w r1, #0
8009074: f04f 0200 mov.w r2, #0
8009078: 00e2 lsls r2, r4, #3
800907a: ea42 7253 orr.w r2, r2, r3, lsr #29
800907e: 00d9 lsls r1, r3, #3
8009080: 460b mov r3, r1
8009082: 4614 mov r4, r2
8009084: 195b adds r3, r3, r5
8009086: eb44 0406 adc.w r4, r4, r6
800908a: f04f 0100 mov.w r1, #0
800908e: f04f 0200 mov.w r2, #0
8009092: 02a2 lsls r2, r4, #10
8009094: ea42 5293 orr.w r2, r2, r3, lsr #22
8009098: 0299 lsls r1, r3, #10
800909a: 460b mov r3, r1
800909c: 4614 mov r4, r2
800909e: 4618 mov r0, r3
80090a0: 4621 mov r1, r4
80090a2: 687b ldr r3, [r7, #4]
80090a4: f04f 0400 mov.w r4, #0
80090a8: 461a mov r2, r3
80090aa: 4623 mov r3, r4
80090ac: f7f7 f900 bl 80002b0 <__aeabi_uldivmod>
80090b0: 4603 mov r3, r0
80090b2: 460c mov r4, r1
80090b4: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
80090b6: 4b0b ldr r3, [pc, #44] ; (80090e4 <HAL_RCC_GetSysClockFreq+0x158>)
80090b8: 685b ldr r3, [r3, #4]
80090ba: 0c1b lsrs r3, r3, #16
80090bc: f003 0303 and.w r3, r3, #3
80090c0: 3301 adds r3, #1
80090c2: 005b lsls r3, r3, #1
80090c4: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllp;
80090c6: 68fa ldr r2, [r7, #12]
80090c8: 683b ldr r3, [r7, #0]
80090ca: fbb2 f3f3 udiv r3, r2, r3
80090ce: 60bb str r3, [r7, #8]
break;
80090d0: e002 b.n 80090d8 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
80090d2: 4b05 ldr r3, [pc, #20] ; (80090e8 <HAL_RCC_GetSysClockFreq+0x15c>)
80090d4: 60bb str r3, [r7, #8]
break;
80090d6: bf00 nop
}
}
return sysclockfreq;
80090d8: 68bb ldr r3, [r7, #8]
}
80090da: 4618 mov r0, r3
80090dc: 3714 adds r7, #20
80090de: 46bd mov sp, r7
80090e0: bdf0 pop {r4, r5, r6, r7, pc}
80090e2: bf00 nop
80090e4: 40023800 .word 0x40023800
80090e8: 00f42400 .word 0x00f42400
80090ec: 017d7840 .word 0x017d7840
080090f0 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80090f0: b480 push {r7}
80090f2: af00 add r7, sp, #0
return SystemCoreClock;
80090f4: 4b03 ldr r3, [pc, #12] ; (8009104 <HAL_RCC_GetHCLKFreq+0x14>)
80090f6: 681b ldr r3, [r3, #0]
}
80090f8: 4618 mov r0, r3
80090fa: 46bd mov sp, r7
80090fc: f85d 7b04 ldr.w r7, [sp], #4
8009100: 4770 bx lr
8009102: bf00 nop
8009104: 20000064 .word 0x20000064
08009108 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8009108: b580 push {r7, lr}
800910a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
800910c: f7ff fff0 bl 80090f0 <HAL_RCC_GetHCLKFreq>
8009110: 4601 mov r1, r0
8009112: 4b05 ldr r3, [pc, #20] ; (8009128 <HAL_RCC_GetPCLK1Freq+0x20>)
8009114: 689b ldr r3, [r3, #8]
8009116: 0a9b lsrs r3, r3, #10
8009118: f003 0307 and.w r3, r3, #7
800911c: 4a03 ldr r2, [pc, #12] ; (800912c <HAL_RCC_GetPCLK1Freq+0x24>)
800911e: 5cd3 ldrb r3, [r2, r3]
8009120: fa21 f303 lsr.w r3, r1, r3
}
8009124: 4618 mov r0, r3
8009126: bd80 pop {r7, pc}
8009128: 40023800 .word 0x40023800
800912c: 08020d38 .word 0x08020d38
08009130 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8009130: b480 push {r7}
8009132: b083 sub sp, #12
8009134: af00 add r7, sp, #0
8009136: 6078 str r0, [r7, #4]
8009138: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
800913a: 687b ldr r3, [r7, #4]
800913c: 220f movs r2, #15
800913e: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8009140: 4b12 ldr r3, [pc, #72] ; (800918c <HAL_RCC_GetClockConfig+0x5c>)
8009142: 689b ldr r3, [r3, #8]
8009144: f003 0203 and.w r2, r3, #3
8009148: 687b ldr r3, [r7, #4]
800914a: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
800914c: 4b0f ldr r3, [pc, #60] ; (800918c <HAL_RCC_GetClockConfig+0x5c>)
800914e: 689b ldr r3, [r3, #8]
8009150: f003 02f0 and.w r2, r3, #240 ; 0xf0
8009154: 687b ldr r3, [r7, #4]
8009156: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8009158: 4b0c ldr r3, [pc, #48] ; (800918c <HAL_RCC_GetClockConfig+0x5c>)
800915a: 689b ldr r3, [r3, #8]
800915c: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8009160: 687b ldr r3, [r7, #4]
8009162: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8009164: 4b09 ldr r3, [pc, #36] ; (800918c <HAL_RCC_GetClockConfig+0x5c>)
8009166: 689b ldr r3, [r3, #8]
8009168: 08db lsrs r3, r3, #3
800916a: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
800916e: 687b ldr r3, [r7, #4]
8009170: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8009172: 4b07 ldr r3, [pc, #28] ; (8009190 <HAL_RCC_GetClockConfig+0x60>)
8009174: 681b ldr r3, [r3, #0]
8009176: f003 020f and.w r2, r3, #15
800917a: 683b ldr r3, [r7, #0]
800917c: 601a str r2, [r3, #0]
}
800917e: bf00 nop
8009180: 370c adds r7, #12
8009182: 46bd mov sp, r7
8009184: f85d 7b04 ldr.w r7, [sp], #4
8009188: 4770 bx lr
800918a: bf00 nop
800918c: 40023800 .word 0x40023800
8009190: 40023c00 .word 0x40023c00
08009194 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8009194: b580 push {r7, lr}
8009196: b088 sub sp, #32
8009198: af00 add r7, sp, #0
800919a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
800919c: 2300 movs r3, #0
800919e: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
80091a0: 2300 movs r3, #0
80091a2: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
80091a4: 2300 movs r3, #0
80091a6: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
80091a8: 2300 movs r3, #0
80091aa: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
80091ac: 2300 movs r3, #0
80091ae: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
80091b0: 687b ldr r3, [r7, #4]
80091b2: 681b ldr r3, [r3, #0]
80091b4: f003 0301 and.w r3, r3, #1
80091b8: 2b00 cmp r3, #0
80091ba: d012 beq.n 80091e2 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80091bc: 4b69 ldr r3, [pc, #420] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091be: 689b ldr r3, [r3, #8]
80091c0: 4a68 ldr r2, [pc, #416] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091c2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
80091c6: 6093 str r3, [r2, #8]
80091c8: 4b66 ldr r3, [pc, #408] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091ca: 689a ldr r2, [r3, #8]
80091cc: 687b ldr r3, [r7, #4]
80091ce: 6b5b ldr r3, [r3, #52] ; 0x34
80091d0: 4964 ldr r1, [pc, #400] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091d2: 4313 orrs r3, r2
80091d4: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
80091d6: 687b ldr r3, [r7, #4]
80091d8: 6b5b ldr r3, [r3, #52] ; 0x34
80091da: 2b00 cmp r3, #0
80091dc: d101 bne.n 80091e2 <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
80091de: 2301 movs r3, #1
80091e0: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
80091e2: 687b ldr r3, [r7, #4]
80091e4: 681b ldr r3, [r3, #0]
80091e6: f403 2300 and.w r3, r3, #524288 ; 0x80000
80091ea: 2b00 cmp r3, #0
80091ec: d017 beq.n 800921e <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80091ee: 4b5d ldr r3, [pc, #372] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091f0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80091f4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
80091f8: 687b ldr r3, [r7, #4]
80091fa: 6bdb ldr r3, [r3, #60] ; 0x3c
80091fc: 4959 ldr r1, [pc, #356] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091fe: 4313 orrs r3, r2
8009200: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
8009204: 687b ldr r3, [r7, #4]
8009206: 6bdb ldr r3, [r3, #60] ; 0x3c
8009208: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
800920c: d101 bne.n 8009212 <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
800920e: 2301 movs r3, #1
8009210: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
8009212: 687b ldr r3, [r7, #4]
8009214: 6bdb ldr r3, [r3, #60] ; 0x3c
8009216: 2b00 cmp r3, #0
8009218: d101 bne.n 800921e <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
800921a: 2301 movs r3, #1
800921c: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
800921e: 687b ldr r3, [r7, #4]
8009220: 681b ldr r3, [r3, #0]
8009222: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8009226: 2b00 cmp r3, #0
8009228: d017 beq.n 800925a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
800922a: 4b4e ldr r3, [pc, #312] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800922c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009230: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8009234: 687b ldr r3, [r7, #4]
8009236: 6c1b ldr r3, [r3, #64] ; 0x40
8009238: 494a ldr r1, [pc, #296] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800923a: 4313 orrs r3, r2
800923c: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
8009240: 687b ldr r3, [r7, #4]
8009242: 6c1b ldr r3, [r3, #64] ; 0x40
8009244: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8009248: d101 bne.n 800924e <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
800924a: 2301 movs r3, #1
800924c: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
800924e: 687b ldr r3, [r7, #4]
8009250: 6c1b ldr r3, [r3, #64] ; 0x40
8009252: 2b00 cmp r3, #0
8009254: d101 bne.n 800925a <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
8009256: 2301 movs r3, #1
8009258: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
800925a: 687b ldr r3, [r7, #4]
800925c: 681b ldr r3, [r3, #0]
800925e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8009262: 2b00 cmp r3, #0
8009264: d001 beq.n 800926a <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
8009266: 2301 movs r3, #1
8009268: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
800926a: 687b ldr r3, [r7, #4]
800926c: 681b ldr r3, [r3, #0]
800926e: f003 0320 and.w r3, r3, #32
8009272: 2b00 cmp r3, #0
8009274: f000 808b beq.w 800938e <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8009278: 4b3a ldr r3, [pc, #232] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800927a: 6c1b ldr r3, [r3, #64] ; 0x40
800927c: 4a39 ldr r2, [pc, #228] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800927e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8009282: 6413 str r3, [r2, #64] ; 0x40
8009284: 4b37 ldr r3, [pc, #220] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009286: 6c1b ldr r3, [r3, #64] ; 0x40
8009288: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800928c: 60bb str r3, [r7, #8]
800928e: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8009290: 4b35 ldr r3, [pc, #212] ; (8009368 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8009292: 681b ldr r3, [r3, #0]
8009294: 4a34 ldr r2, [pc, #208] ; (8009368 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8009296: f443 7380 orr.w r3, r3, #256 ; 0x100
800929a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800929c: f7fb fb7c bl 8004998 <HAL_GetTick>
80092a0: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80092a2: e008 b.n 80092b6 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80092a4: f7fb fb78 bl 8004998 <HAL_GetTick>
80092a8: 4602 mov r2, r0
80092aa: 697b ldr r3, [r7, #20]
80092ac: 1ad3 subs r3, r2, r3
80092ae: 2b64 cmp r3, #100 ; 0x64
80092b0: d901 bls.n 80092b6 <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
80092b2: 2303 movs r3, #3
80092b4: e355 b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80092b6: 4b2c ldr r3, [pc, #176] ; (8009368 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80092b8: 681b ldr r3, [r3, #0]
80092ba: f403 7380 and.w r3, r3, #256 ; 0x100
80092be: 2b00 cmp r3, #0
80092c0: d0f0 beq.n 80092a4 <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
80092c2: 4b28 ldr r3, [pc, #160] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092c4: 6f1b ldr r3, [r3, #112] ; 0x70
80092c6: f403 7340 and.w r3, r3, #768 ; 0x300
80092ca: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80092cc: 693b ldr r3, [r7, #16]
80092ce: 2b00 cmp r3, #0
80092d0: d035 beq.n 800933e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
80092d2: 687b ldr r3, [r7, #4]
80092d4: 6b1b ldr r3, [r3, #48] ; 0x30
80092d6: f403 7340 and.w r3, r3, #768 ; 0x300
80092da: 693a ldr r2, [r7, #16]
80092dc: 429a cmp r2, r3
80092de: d02e beq.n 800933e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80092e0: 4b20 ldr r3, [pc, #128] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092e2: 6f1b ldr r3, [r3, #112] ; 0x70
80092e4: f423 7340 bic.w r3, r3, #768 ; 0x300
80092e8: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80092ea: 4b1e ldr r3, [pc, #120] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092ec: 6f1b ldr r3, [r3, #112] ; 0x70
80092ee: 4a1d ldr r2, [pc, #116] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80092f4: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
80092f6: 4b1b ldr r3, [pc, #108] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092f8: 6f1b ldr r3, [r3, #112] ; 0x70
80092fa: 4a1a ldr r2, [pc, #104] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092fc: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8009300: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
8009302: 4a18 ldr r2, [pc, #96] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009304: 693b ldr r3, [r7, #16]
8009306: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8009308: 4b16 ldr r3, [pc, #88] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800930a: 6f1b ldr r3, [r3, #112] ; 0x70
800930c: f003 0301 and.w r3, r3, #1
8009310: 2b01 cmp r3, #1
8009312: d114 bne.n 800933e <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009314: f7fb fb40 bl 8004998 <HAL_GetTick>
8009318: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800931a: e00a b.n 8009332 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800931c: f7fb fb3c bl 8004998 <HAL_GetTick>
8009320: 4602 mov r2, r0
8009322: 697b ldr r3, [r7, #20]
8009324: 1ad3 subs r3, r2, r3
8009326: f241 3288 movw r2, #5000 ; 0x1388
800932a: 4293 cmp r3, r2
800932c: d901 bls.n 8009332 <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
800932e: 2303 movs r3, #3
8009330: e317 b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8009332: 4b0c ldr r3, [pc, #48] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009334: 6f1b ldr r3, [r3, #112] ; 0x70
8009336: f003 0302 and.w r3, r3, #2
800933a: 2b00 cmp r3, #0
800933c: d0ee beq.n 800931c <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800933e: 687b ldr r3, [r7, #4]
8009340: 6b1b ldr r3, [r3, #48] ; 0x30
8009342: f403 7340 and.w r3, r3, #768 ; 0x300
8009346: f5b3 7f40 cmp.w r3, #768 ; 0x300
800934a: d111 bne.n 8009370 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
800934c: 4b05 ldr r3, [pc, #20] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800934e: 689b ldr r3, [r3, #8]
8009350: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
8009354: 687b ldr r3, [r7, #4]
8009356: 6b19 ldr r1, [r3, #48] ; 0x30
8009358: 4b04 ldr r3, [pc, #16] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
800935a: 400b ands r3, r1
800935c: 4901 ldr r1, [pc, #4] ; (8009364 <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800935e: 4313 orrs r3, r2
8009360: 608b str r3, [r1, #8]
8009362: e00b b.n 800937c <HAL_RCCEx_PeriphCLKConfig+0x1e8>
8009364: 40023800 .word 0x40023800
8009368: 40007000 .word 0x40007000
800936c: 0ffffcff .word 0x0ffffcff
8009370: 4bb0 ldr r3, [pc, #704] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009372: 689b ldr r3, [r3, #8]
8009374: 4aaf ldr r2, [pc, #700] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009376: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
800937a: 6093 str r3, [r2, #8]
800937c: 4bad ldr r3, [pc, #692] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800937e: 6f1a ldr r2, [r3, #112] ; 0x70
8009380: 687b ldr r3, [r7, #4]
8009382: 6b1b ldr r3, [r3, #48] ; 0x30
8009384: f3c3 030b ubfx r3, r3, #0, #12
8009388: 49aa ldr r1, [pc, #680] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800938a: 4313 orrs r3, r2
800938c: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
800938e: 687b ldr r3, [r7, #4]
8009390: 681b ldr r3, [r3, #0]
8009392: f003 0310 and.w r3, r3, #16
8009396: 2b00 cmp r3, #0
8009398: d010 beq.n 80093bc <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
800939a: 4ba6 ldr r3, [pc, #664] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800939c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80093a0: 4aa4 ldr r2, [pc, #656] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093a2: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80093a6: f8c2 308c str.w r3, [r2, #140] ; 0x8c
80093aa: 4ba2 ldr r3, [pc, #648] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093ac: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
80093b0: 687b ldr r3, [r7, #4]
80093b2: 6b9b ldr r3, [r3, #56] ; 0x38
80093b4: 499f ldr r1, [pc, #636] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093b6: 4313 orrs r3, r2
80093b8: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80093bc: 687b ldr r3, [r7, #4]
80093be: 681b ldr r3, [r3, #0]
80093c0: f403 4380 and.w r3, r3, #16384 ; 0x4000
80093c4: 2b00 cmp r3, #0
80093c6: d00a beq.n 80093de <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80093c8: 4b9a ldr r3, [pc, #616] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093ca: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093ce: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80093d2: 687b ldr r3, [r7, #4]
80093d4: 6e5b ldr r3, [r3, #100] ; 0x64
80093d6: 4997 ldr r1, [pc, #604] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093d8: 4313 orrs r3, r2
80093da: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80093de: 687b ldr r3, [r7, #4]
80093e0: 681b ldr r3, [r3, #0]
80093e2: f403 4300 and.w r3, r3, #32768 ; 0x8000
80093e6: 2b00 cmp r3, #0
80093e8: d00a beq.n 8009400 <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80093ea: 4b92 ldr r3, [pc, #584] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093f0: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
80093f4: 687b ldr r3, [r7, #4]
80093f6: 6e9b ldr r3, [r3, #104] ; 0x68
80093f8: 498e ldr r1, [pc, #568] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093fa: 4313 orrs r3, r2
80093fc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8009400: 687b ldr r3, [r7, #4]
8009402: 681b ldr r3, [r3, #0]
8009404: f403 3380 and.w r3, r3, #65536 ; 0x10000
8009408: 2b00 cmp r3, #0
800940a: d00a beq.n 8009422 <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
800940c: 4b89 ldr r3, [pc, #548] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800940e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009412: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8009416: 687b ldr r3, [r7, #4]
8009418: 6edb ldr r3, [r3, #108] ; 0x6c
800941a: 4986 ldr r1, [pc, #536] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800941c: 4313 orrs r3, r2
800941e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8009422: 687b ldr r3, [r7, #4]
8009424: 681b ldr r3, [r3, #0]
8009426: f403 3300 and.w r3, r3, #131072 ; 0x20000
800942a: 2b00 cmp r3, #0
800942c: d00a beq.n 8009444 <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
800942e: 4b81 ldr r3, [pc, #516] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009430: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009434: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8009438: 687b ldr r3, [r7, #4]
800943a: 6f1b ldr r3, [r3, #112] ; 0x70
800943c: 497d ldr r1, [pc, #500] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800943e: 4313 orrs r3, r2
8009440: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8009444: 687b ldr r3, [r7, #4]
8009446: 681b ldr r3, [r3, #0]
8009448: f003 0340 and.w r3, r3, #64 ; 0x40
800944c: 2b00 cmp r3, #0
800944e: d00a beq.n 8009466 <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8009450: 4b78 ldr r3, [pc, #480] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009452: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009456: f023 0203 bic.w r2, r3, #3
800945a: 687b ldr r3, [r7, #4]
800945c: 6c5b ldr r3, [r3, #68] ; 0x44
800945e: 4975 ldr r1, [pc, #468] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009460: 4313 orrs r3, r2
8009462: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8009466: 687b ldr r3, [r7, #4]
8009468: 681b ldr r3, [r3, #0]
800946a: f003 0380 and.w r3, r3, #128 ; 0x80
800946e: 2b00 cmp r3, #0
8009470: d00a beq.n 8009488 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8009472: 4b70 ldr r3, [pc, #448] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009474: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009478: f023 020c bic.w r2, r3, #12
800947c: 687b ldr r3, [r7, #4]
800947e: 6c9b ldr r3, [r3, #72] ; 0x48
8009480: 496c ldr r1, [pc, #432] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009482: 4313 orrs r3, r2
8009484: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8009488: 687b ldr r3, [r7, #4]
800948a: 681b ldr r3, [r3, #0]
800948c: f403 7380 and.w r3, r3, #256 ; 0x100
8009490: 2b00 cmp r3, #0
8009492: d00a beq.n 80094aa <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8009494: 4b67 ldr r3, [pc, #412] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009496: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800949a: f023 0230 bic.w r2, r3, #48 ; 0x30
800949e: 687b ldr r3, [r7, #4]
80094a0: 6cdb ldr r3, [r3, #76] ; 0x4c
80094a2: 4964 ldr r1, [pc, #400] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094a4: 4313 orrs r3, r2
80094a6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80094aa: 687b ldr r3, [r7, #4]
80094ac: 681b ldr r3, [r3, #0]
80094ae: f403 7300 and.w r3, r3, #512 ; 0x200
80094b2: 2b00 cmp r3, #0
80094b4: d00a beq.n 80094cc <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80094b6: 4b5f ldr r3, [pc, #380] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094b8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80094bc: f023 02c0 bic.w r2, r3, #192 ; 0xc0
80094c0: 687b ldr r3, [r7, #4]
80094c2: 6d1b ldr r3, [r3, #80] ; 0x50
80094c4: 495b ldr r1, [pc, #364] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094c6: 4313 orrs r3, r2
80094c8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
80094cc: 687b ldr r3, [r7, #4]
80094ce: 681b ldr r3, [r3, #0]
80094d0: f403 6380 and.w r3, r3, #1024 ; 0x400
80094d4: 2b00 cmp r3, #0
80094d6: d00a beq.n 80094ee <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
80094d8: 4b56 ldr r3, [pc, #344] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094da: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80094de: f423 7240 bic.w r2, r3, #768 ; 0x300
80094e2: 687b ldr r3, [r7, #4]
80094e4: 6d5b ldr r3, [r3, #84] ; 0x54
80094e6: 4953 ldr r1, [pc, #332] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094e8: 4313 orrs r3, r2
80094ea: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
80094ee: 687b ldr r3, [r7, #4]
80094f0: 681b ldr r3, [r3, #0]
80094f2: f403 6300 and.w r3, r3, #2048 ; 0x800
80094f6: 2b00 cmp r3, #0
80094f8: d00a beq.n 8009510 <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
80094fa: 4b4e ldr r3, [pc, #312] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009500: f423 6240 bic.w r2, r3, #3072 ; 0xc00
8009504: 687b ldr r3, [r7, #4]
8009506: 6d9b ldr r3, [r3, #88] ; 0x58
8009508: 494a ldr r1, [pc, #296] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800950a: 4313 orrs r3, r2
800950c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8009510: 687b ldr r3, [r7, #4]
8009512: 681b ldr r3, [r3, #0]
8009514: f403 5380 and.w r3, r3, #4096 ; 0x1000
8009518: 2b00 cmp r3, #0
800951a: d00a beq.n 8009532 <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
800951c: 4b45 ldr r3, [pc, #276] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800951e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009522: f423 5240 bic.w r2, r3, #12288 ; 0x3000
8009526: 687b ldr r3, [r7, #4]
8009528: 6ddb ldr r3, [r3, #92] ; 0x5c
800952a: 4942 ldr r1, [pc, #264] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800952c: 4313 orrs r3, r2
800952e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
8009532: 687b ldr r3, [r7, #4]
8009534: 681b ldr r3, [r3, #0]
8009536: f403 5300 and.w r3, r3, #8192 ; 0x2000
800953a: 2b00 cmp r3, #0
800953c: d00a beq.n 8009554 <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
800953e: 4b3d ldr r3, [pc, #244] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009540: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009544: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8009548: 687b ldr r3, [r7, #4]
800954a: 6e1b ldr r3, [r3, #96] ; 0x60
800954c: 4939 ldr r1, [pc, #228] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800954e: 4313 orrs r3, r2
8009550: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8009554: 687b ldr r3, [r7, #4]
8009556: 681b ldr r3, [r3, #0]
8009558: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800955c: 2b00 cmp r3, #0
800955e: d00a beq.n 8009576 <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8009560: 4b34 ldr r3, [pc, #208] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009562: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009566: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
800956a: 687b ldr r3, [r7, #4]
800956c: 6f9b ldr r3, [r3, #120] ; 0x78
800956e: 4931 ldr r1, [pc, #196] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009570: 4313 orrs r3, r2
8009572: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
8009576: 687b ldr r3, [r7, #4]
8009578: 681b ldr r3, [r3, #0]
800957a: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800957e: 2b00 cmp r3, #0
8009580: d011 beq.n 80095a6 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
8009582: 4b2c ldr r3, [pc, #176] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009584: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009588: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
800958c: 687b ldr r3, [r7, #4]
800958e: 6fdb ldr r3, [r3, #124] ; 0x7c
8009590: 4928 ldr r1, [pc, #160] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009592: 4313 orrs r3, r2
8009594: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
8009598: 687b ldr r3, [r7, #4]
800959a: 6fdb ldr r3, [r3, #124] ; 0x7c
800959c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80095a0: d101 bne.n 80095a6 <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
80095a2: 2301 movs r3, #1
80095a4: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
80095a6: 687b ldr r3, [r7, #4]
80095a8: 681b ldr r3, [r3, #0]
80095aa: f003 0308 and.w r3, r3, #8
80095ae: 2b00 cmp r3, #0
80095b0: d001 beq.n 80095b6 <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
80095b2: 2301 movs r3, #1
80095b4: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80095b6: 687b ldr r3, [r7, #4]
80095b8: 681b ldr r3, [r3, #0]
80095ba: f403 2380 and.w r3, r3, #262144 ; 0x40000
80095be: 2b00 cmp r3, #0
80095c0: d00a beq.n 80095d8 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80095c2: 4b1c ldr r3, [pc, #112] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095c4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80095c8: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
80095cc: 687b ldr r3, [r7, #4]
80095ce: 6f5b ldr r3, [r3, #116] ; 0x74
80095d0: 4918 ldr r1, [pc, #96] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095d2: 4313 orrs r3, r2
80095d4: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
80095d8: 687b ldr r3, [r7, #4]
80095da: 681b ldr r3, [r3, #0]
80095dc: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80095e0: 2b00 cmp r3, #0
80095e2: d00b beq.n 80095fc <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
80095e4: 4b13 ldr r3, [pc, #76] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095e6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80095ea: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
80095ee: 687b ldr r3, [r7, #4]
80095f0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80095f4: 490f ldr r1, [pc, #60] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095f6: 4313 orrs r3, r2
80095f8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
80095fc: 69fb ldr r3, [r7, #28]
80095fe: 2b01 cmp r3, #1
8009600: d005 beq.n 800960e <HAL_RCCEx_PeriphCLKConfig+0x47a>
8009602: 687b ldr r3, [r7, #4]
8009604: 681b ldr r3, [r3, #0]
8009606: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
800960a: f040 80d8 bne.w 80097be <HAL_RCCEx_PeriphCLKConfig+0x62a>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
800960e: 4b09 ldr r3, [pc, #36] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009610: 681b ldr r3, [r3, #0]
8009612: 4a08 ldr r2, [pc, #32] ; (8009634 <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009614: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
8009618: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800961a: f7fb f9bd bl 8004998 <HAL_GetTick>
800961e: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8009620: e00a b.n 8009638 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8009622: f7fb f9b9 bl 8004998 <HAL_GetTick>
8009626: 4602 mov r2, r0
8009628: 697b ldr r3, [r7, #20]
800962a: 1ad3 subs r3, r2, r3
800962c: 2b64 cmp r3, #100 ; 0x64
800962e: d903 bls.n 8009638 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8009630: 2303 movs r3, #3
8009632: e196 b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
8009634: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8009638: 4b6c ldr r3, [pc, #432] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
800963a: 681b ldr r3, [r3, #0]
800963c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8009640: 2b00 cmp r3, #0
8009642: d1ee bne.n 8009622 <HAL_RCCEx_PeriphCLKConfig+0x48e>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8009644: 687b ldr r3, [r7, #4]
8009646: 681b ldr r3, [r3, #0]
8009648: f003 0301 and.w r3, r3, #1
800964c: 2b00 cmp r3, #0
800964e: d021 beq.n 8009694 <HAL_RCCEx_PeriphCLKConfig+0x500>
8009650: 687b ldr r3, [r7, #4]
8009652: 6b5b ldr r3, [r3, #52] ; 0x34
8009654: 2b00 cmp r3, #0
8009656: d11d bne.n 8009694 <HAL_RCCEx_PeriphCLKConfig+0x500>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8009658: 4b64 ldr r3, [pc, #400] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
800965a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800965e: 0c1b lsrs r3, r3, #16
8009660: f003 0303 and.w r3, r3, #3
8009664: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8009666: 4b61 ldr r3, [pc, #388] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009668: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800966c: 0e1b lsrs r3, r3, #24
800966e: f003 030f and.w r3, r3, #15
8009672: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
8009674: 687b ldr r3, [r7, #4]
8009676: 685b ldr r3, [r3, #4]
8009678: 019a lsls r2, r3, #6
800967a: 693b ldr r3, [r7, #16]
800967c: 041b lsls r3, r3, #16
800967e: 431a orrs r2, r3
8009680: 68fb ldr r3, [r7, #12]
8009682: 061b lsls r3, r3, #24
8009684: 431a orrs r2, r3
8009686: 687b ldr r3, [r7, #4]
8009688: 689b ldr r3, [r3, #8]
800968a: 071b lsls r3, r3, #28
800968c: 4957 ldr r1, [pc, #348] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
800968e: 4313 orrs r3, r2
8009690: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
8009694: 687b ldr r3, [r7, #4]
8009696: 681b ldr r3, [r3, #0]
8009698: f403 2300 and.w r3, r3, #524288 ; 0x80000
800969c: 2b00 cmp r3, #0
800969e: d004 beq.n 80096aa <HAL_RCCEx_PeriphCLKConfig+0x516>
80096a0: 687b ldr r3, [r7, #4]
80096a2: 6bdb ldr r3, [r3, #60] ; 0x3c
80096a4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80096a8: d00a beq.n 80096c0 <HAL_RCCEx_PeriphCLKConfig+0x52c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80096aa: 687b ldr r3, [r7, #4]
80096ac: 681b ldr r3, [r3, #0]
80096ae: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80096b2: 2b00 cmp r3, #0
80096b4: d02e beq.n 8009714 <HAL_RCCEx_PeriphCLKConfig+0x580>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80096b6: 687b ldr r3, [r7, #4]
80096b8: 6c1b ldr r3, [r3, #64] ; 0x40
80096ba: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80096be: d129 bne.n 8009714 <HAL_RCCEx_PeriphCLKConfig+0x580>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
80096c0: 4b4a ldr r3, [pc, #296] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096c2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80096c6: 0c1b lsrs r3, r3, #16
80096c8: f003 0303 and.w r3, r3, #3
80096cc: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
80096ce: 4b47 ldr r3, [pc, #284] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096d0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80096d4: 0f1b lsrs r3, r3, #28
80096d6: f003 0307 and.w r3, r3, #7
80096da: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
80096dc: 687b ldr r3, [r7, #4]
80096de: 685b ldr r3, [r3, #4]
80096e0: 019a lsls r2, r3, #6
80096e2: 693b ldr r3, [r7, #16]
80096e4: 041b lsls r3, r3, #16
80096e6: 431a orrs r2, r3
80096e8: 687b ldr r3, [r7, #4]
80096ea: 68db ldr r3, [r3, #12]
80096ec: 061b lsls r3, r3, #24
80096ee: 431a orrs r2, r3
80096f0: 68fb ldr r3, [r7, #12]
80096f2: 071b lsls r3, r3, #28
80096f4: 493d ldr r1, [pc, #244] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096f6: 4313 orrs r3, r2
80096f8: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
80096fc: 4b3b ldr r3, [pc, #236] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096fe: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009702: f023 021f bic.w r2, r3, #31
8009706: 687b ldr r3, [r7, #4]
8009708: 6a5b ldr r3, [r3, #36] ; 0x24
800970a: 3b01 subs r3, #1
800970c: 4937 ldr r1, [pc, #220] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
800970e: 4313 orrs r3, r2
8009710: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8009714: 687b ldr r3, [r7, #4]
8009716: 681b ldr r3, [r3, #0]
8009718: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
800971c: 2b00 cmp r3, #0
800971e: d01d beq.n 800975c <HAL_RCCEx_PeriphCLKConfig+0x5c8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8009720: 4b32 ldr r3, [pc, #200] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009722: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009726: 0e1b lsrs r3, r3, #24
8009728: f003 030f and.w r3, r3, #15
800972c: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
800972e: 4b2f ldr r3, [pc, #188] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009730: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009734: 0f1b lsrs r3, r3, #28
8009736: f003 0307 and.w r3, r3, #7
800973a: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
800973c: 687b ldr r3, [r7, #4]
800973e: 685b ldr r3, [r3, #4]
8009740: 019a lsls r2, r3, #6
8009742: 687b ldr r3, [r7, #4]
8009744: 691b ldr r3, [r3, #16]
8009746: 041b lsls r3, r3, #16
8009748: 431a orrs r2, r3
800974a: 693b ldr r3, [r7, #16]
800974c: 061b lsls r3, r3, #24
800974e: 431a orrs r2, r3
8009750: 68fb ldr r3, [r7, #12]
8009752: 071b lsls r3, r3, #28
8009754: 4925 ldr r1, [pc, #148] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009756: 4313 orrs r3, r2
8009758: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
800975c: 687b ldr r3, [r7, #4]
800975e: 681b ldr r3, [r3, #0]
8009760: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8009764: 2b00 cmp r3, #0
8009766: d011 beq.n 800978c <HAL_RCCEx_PeriphCLKConfig+0x5f8>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8009768: 687b ldr r3, [r7, #4]
800976a: 685b ldr r3, [r3, #4]
800976c: 019a lsls r2, r3, #6
800976e: 687b ldr r3, [r7, #4]
8009770: 691b ldr r3, [r3, #16]
8009772: 041b lsls r3, r3, #16
8009774: 431a orrs r2, r3
8009776: 687b ldr r3, [r7, #4]
8009778: 68db ldr r3, [r3, #12]
800977a: 061b lsls r3, r3, #24
800977c: 431a orrs r2, r3
800977e: 687b ldr r3, [r7, #4]
8009780: 689b ldr r3, [r3, #8]
8009782: 071b lsls r3, r3, #28
8009784: 4919 ldr r1, [pc, #100] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009786: 4313 orrs r3, r2
8009788: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
800978c: 4b17 ldr r3, [pc, #92] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
800978e: 681b ldr r3, [r3, #0]
8009790: 4a16 ldr r2, [pc, #88] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009792: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8009796: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009798: f7fb f8fe bl 8004998 <HAL_GetTick>
800979c: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
800979e: e008 b.n 80097b2 <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
80097a0: f7fb f8fa bl 8004998 <HAL_GetTick>
80097a4: 4602 mov r2, r0
80097a6: 697b ldr r3, [r7, #20]
80097a8: 1ad3 subs r3, r2, r3
80097aa: 2b64 cmp r3, #100 ; 0x64
80097ac: d901 bls.n 80097b2 <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80097ae: 2303 movs r3, #3
80097b0: e0d7 b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80097b2: 4b0e ldr r3, [pc, #56] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097b4: 681b ldr r3, [r3, #0]
80097b6: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
80097ba: 2b00 cmp r3, #0
80097bc: d0f0 beq.n 80097a0 <HAL_RCCEx_PeriphCLKConfig+0x60c>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
80097be: 69bb ldr r3, [r7, #24]
80097c0: 2b01 cmp r3, #1
80097c2: f040 80cd bne.w 8009960 <HAL_RCCEx_PeriphCLKConfig+0x7cc>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
80097c6: 4b09 ldr r3, [pc, #36] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097c8: 681b ldr r3, [r3, #0]
80097ca: 4a08 ldr r2, [pc, #32] ; (80097ec <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097cc: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80097d0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80097d2: f7fb f8e1 bl 8004998 <HAL_GetTick>
80097d6: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80097d8: e00a b.n 80097f0 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80097da: f7fb f8dd bl 8004998 <HAL_GetTick>
80097de: 4602 mov r2, r0
80097e0: 697b ldr r3, [r7, #20]
80097e2: 1ad3 subs r3, r2, r3
80097e4: 2b64 cmp r3, #100 ; 0x64
80097e6: d903 bls.n 80097f0 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80097e8: 2303 movs r3, #3
80097ea: e0ba b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
80097ec: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80097f0: 4b5e ldr r3, [pc, #376] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80097f2: 681b ldr r3, [r3, #0]
80097f4: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80097f8: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
80097fc: d0ed beq.n 80097da <HAL_RCCEx_PeriphCLKConfig+0x646>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80097fe: 687b ldr r3, [r7, #4]
8009800: 681b ldr r3, [r3, #0]
8009802: f403 2300 and.w r3, r3, #524288 ; 0x80000
8009806: 2b00 cmp r3, #0
8009808: d003 beq.n 8009812 <HAL_RCCEx_PeriphCLKConfig+0x67e>
800980a: 687b ldr r3, [r7, #4]
800980c: 6bdb ldr r3, [r3, #60] ; 0x3c
800980e: 2b00 cmp r3, #0
8009810: d009 beq.n 8009826 <HAL_RCCEx_PeriphCLKConfig+0x692>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8009812: 687b ldr r3, [r7, #4]
8009814: 681b ldr r3, [r3, #0]
8009816: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
800981a: 2b00 cmp r3, #0
800981c: d02e beq.n 800987c <HAL_RCCEx_PeriphCLKConfig+0x6e8>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
800981e: 687b ldr r3, [r7, #4]
8009820: 6c1b ldr r3, [r3, #64] ; 0x40
8009822: 2b00 cmp r3, #0
8009824: d12a bne.n 800987c <HAL_RCCEx_PeriphCLKConfig+0x6e8>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8009826: 4b51 ldr r3, [pc, #324] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009828: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800982c: 0c1b lsrs r3, r3, #16
800982e: f003 0303 and.w r3, r3, #3
8009832: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8009834: 4b4d ldr r3, [pc, #308] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009836: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800983a: 0f1b lsrs r3, r3, #28
800983c: f003 0307 and.w r3, r3, #7
8009840: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
8009842: 687b ldr r3, [r7, #4]
8009844: 695b ldr r3, [r3, #20]
8009846: 019a lsls r2, r3, #6
8009848: 693b ldr r3, [r7, #16]
800984a: 041b lsls r3, r3, #16
800984c: 431a orrs r2, r3
800984e: 687b ldr r3, [r7, #4]
8009850: 699b ldr r3, [r3, #24]
8009852: 061b lsls r3, r3, #24
8009854: 431a orrs r2, r3
8009856: 68fb ldr r3, [r7, #12]
8009858: 071b lsls r3, r3, #28
800985a: 4944 ldr r1, [pc, #272] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800985c: 4313 orrs r3, r2
800985e: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
8009862: 4b42 ldr r3, [pc, #264] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009864: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009868: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
800986c: 687b ldr r3, [r7, #4]
800986e: 6a9b ldr r3, [r3, #40] ; 0x28
8009870: 3b01 subs r3, #1
8009872: 021b lsls r3, r3, #8
8009874: 493d ldr r1, [pc, #244] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009876: 4313 orrs r3, r2
8009878: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
800987c: 687b ldr r3, [r7, #4]
800987e: 681b ldr r3, [r3, #0]
8009880: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8009884: 2b00 cmp r3, #0
8009886: d022 beq.n 80098ce <HAL_RCCEx_PeriphCLKConfig+0x73a>
8009888: 687b ldr r3, [r7, #4]
800988a: 6fdb ldr r3, [r3, #124] ; 0x7c
800988c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
8009890: d11d bne.n 80098ce <HAL_RCCEx_PeriphCLKConfig+0x73a>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8009892: 4b36 ldr r3, [pc, #216] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009894: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009898: 0e1b lsrs r3, r3, #24
800989a: f003 030f and.w r3, r3, #15
800989e: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
80098a0: 4b32 ldr r3, [pc, #200] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098a2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098a6: 0f1b lsrs r3, r3, #28
80098a8: f003 0307 and.w r3, r3, #7
80098ac: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
80098ae: 687b ldr r3, [r7, #4]
80098b0: 695b ldr r3, [r3, #20]
80098b2: 019a lsls r2, r3, #6
80098b4: 687b ldr r3, [r7, #4]
80098b6: 6a1b ldr r3, [r3, #32]
80098b8: 041b lsls r3, r3, #16
80098ba: 431a orrs r2, r3
80098bc: 693b ldr r3, [r7, #16]
80098be: 061b lsls r3, r3, #24
80098c0: 431a orrs r2, r3
80098c2: 68fb ldr r3, [r7, #12]
80098c4: 071b lsls r3, r3, #28
80098c6: 4929 ldr r1, [pc, #164] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098c8: 4313 orrs r3, r2
80098ca: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
80098ce: 687b ldr r3, [r7, #4]
80098d0: 681b ldr r3, [r3, #0]
80098d2: f003 0308 and.w r3, r3, #8
80098d6: 2b00 cmp r3, #0
80098d8: d028 beq.n 800992c <HAL_RCCEx_PeriphCLKConfig+0x798>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
80098da: 4b24 ldr r3, [pc, #144] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098dc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098e0: 0e1b lsrs r3, r3, #24
80098e2: f003 030f and.w r3, r3, #15
80098e6: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
80098e8: 4b20 ldr r3, [pc, #128] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098ea: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098ee: 0c1b lsrs r3, r3, #16
80098f0: f003 0303 and.w r3, r3, #3
80098f4: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
80098f6: 687b ldr r3, [r7, #4]
80098f8: 695b ldr r3, [r3, #20]
80098fa: 019a lsls r2, r3, #6
80098fc: 68fb ldr r3, [r7, #12]
80098fe: 041b lsls r3, r3, #16
8009900: 431a orrs r2, r3
8009902: 693b ldr r3, [r7, #16]
8009904: 061b lsls r3, r3, #24
8009906: 431a orrs r2, r3
8009908: 687b ldr r3, [r7, #4]
800990a: 69db ldr r3, [r3, #28]
800990c: 071b lsls r3, r3, #28
800990e: 4917 ldr r1, [pc, #92] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009910: 4313 orrs r3, r2
8009912: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
8009916: 4b15 ldr r3, [pc, #84] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009918: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
800991c: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8009920: 687b ldr r3, [r7, #4]
8009922: 6adb ldr r3, [r3, #44] ; 0x2c
8009924: 4911 ldr r1, [pc, #68] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009926: 4313 orrs r3, r2
8009928: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
800992c: 4b0f ldr r3, [pc, #60] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800992e: 681b ldr r3, [r3, #0]
8009930: 4a0e ldr r2, [pc, #56] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009932: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8009936: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009938: f7fb f82e bl 8004998 <HAL_GetTick>
800993c: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
800993e: e008 b.n 8009952 <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8009940: f7fb f82a bl 8004998 <HAL_GetTick>
8009944: 4602 mov r2, r0
8009946: 697b ldr r3, [r7, #20]
8009948: 1ad3 subs r3, r2, r3
800994a: 2b64 cmp r3, #100 ; 0x64
800994c: d901 bls.n 8009952 <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800994e: 2303 movs r3, #3
8009950: e007 b.n 8009962 <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8009952: 4b06 ldr r3, [pc, #24] ; (800996c <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009954: 681b ldr r3, [r3, #0]
8009956: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800995a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
800995e: d1ef bne.n 8009940 <HAL_RCCEx_PeriphCLKConfig+0x7ac>
}
}
}
return HAL_OK;
8009960: 2300 movs r3, #0
}
8009962: 4618 mov r0, r3
8009964: 3720 adds r7, #32
8009966: 46bd mov sp, r7
8009968: bd80 pop {r7, pc}
800996a: bf00 nop
800996c: 40023800 .word 0x40023800
08009970 <HAL_RNG_Init>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
8009970: b580 push {r7, lr}
8009972: b082 sub sp, #8
8009974: af00 add r7, sp, #0
8009976: 6078 str r0, [r7, #4]
/* Check the RNG handle allocation */
if (hrng == NULL)
8009978: 687b ldr r3, [r7, #4]
800997a: 2b00 cmp r3, #0
800997c: d101 bne.n 8009982 <HAL_RNG_Init+0x12>
{
return HAL_ERROR;
800997e: 2301 movs r3, #1
8009980: e01c b.n 80099bc <HAL_RNG_Init+0x4c>
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
8009982: 687b ldr r3, [r7, #4]
8009984: 795b ldrb r3, [r3, #5]
8009986: b2db uxtb r3, r3
8009988: 2b00 cmp r3, #0
800998a: d105 bne.n 8009998 <HAL_RNG_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
800998c: 687b ldr r3, [r7, #4]
800998e: 2200 movs r2, #0
8009990: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
8009992: 6878 ldr r0, [r7, #4]
8009994: f7fa fc6a bl 800426c <HAL_RNG_MspInit>
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
8009998: 687b ldr r3, [r7, #4]
800999a: 2202 movs r2, #2
800999c: 715a strb r2, [r3, #5]
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
800999e: 687b ldr r3, [r7, #4]
80099a0: 681b ldr r3, [r3, #0]
80099a2: 681a ldr r2, [r3, #0]
80099a4: 687b ldr r3, [r7, #4]
80099a6: 681b ldr r3, [r3, #0]
80099a8: f042 0204 orr.w r2, r2, #4
80099ac: 601a str r2, [r3, #0]
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
80099ae: 687b ldr r3, [r7, #4]
80099b0: 2201 movs r2, #1
80099b2: 715a strb r2, [r3, #5]
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
80099b4: 687b ldr r3, [r7, #4]
80099b6: 2200 movs r2, #0
80099b8: 609a str r2, [r3, #8]
/* Return function status */
return HAL_OK;
80099ba: 2300 movs r3, #0
}
80099bc: 4618 mov r0, r3
80099be: 3708 adds r7, #8
80099c0: 46bd mov sp, r7
80099c2: bd80 pop {r7, pc}
080099c4 <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
80099c4: b580 push {r7, lr}
80099c6: b082 sub sp, #8
80099c8: af00 add r7, sp, #0
80099ca: 6078 str r0, [r7, #4]
80099cc: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
80099ce: 687b ldr r3, [r7, #4]
80099d0: 2b00 cmp r3, #0
80099d2: d101 bne.n 80099d8 <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
80099d4: 2301 movs r3, #1
80099d6: e025 b.n 8009a24 <HAL_SDRAM_Init+0x60>
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
80099d8: 687b ldr r3, [r7, #4]
80099da: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
80099de: b2db uxtb r3, r3
80099e0: 2b00 cmp r3, #0
80099e2: d106 bne.n 80099f2 <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
80099e4: 687b ldr r3, [r7, #4]
80099e6: 2200 movs r2, #0
80099e8: f883 202d strb.w r2, [r3, #45] ; 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
80099ec: 6878 ldr r0, [r7, #4]
80099ee: f7fa fe2b bl 8004648 <HAL_SDRAM_MspInit>
#endif
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
80099f2: 687b ldr r3, [r7, #4]
80099f4: 2202 movs r2, #2
80099f6: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
80099fa: 687b ldr r3, [r7, #4]
80099fc: 681a ldr r2, [r3, #0]
80099fe: 687b ldr r3, [r7, #4]
8009a00: 3304 adds r3, #4
8009a02: 4619 mov r1, r3
8009a04: 4610 mov r0, r2
8009a06: f001 fa1d bl 800ae44 <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
8009a0a: 687b ldr r3, [r7, #4]
8009a0c: 6818 ldr r0, [r3, #0]
8009a0e: 687b ldr r3, [r7, #4]
8009a10: 685b ldr r3, [r3, #4]
8009a12: 461a mov r2, r3
8009a14: 6839 ldr r1, [r7, #0]
8009a16: f001 fa87 bl 800af28 <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
8009a1a: 687b ldr r3, [r7, #4]
8009a1c: 2201 movs r2, #1
8009a1e: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8009a22: 2300 movs r3, #0
}
8009a24: 4618 mov r0, r3
8009a26: 3708 adds r7, #8
8009a28: 46bd mov sp, r7
8009a2a: bd80 pop {r7, pc}
08009a2c <HAL_SDRAM_SendCommand>:
* @param Command SDRAM command structure
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
8009a2c: b580 push {r7, lr}
8009a2e: b084 sub sp, #16
8009a30: af00 add r7, sp, #0
8009a32: 60f8 str r0, [r7, #12]
8009a34: 60b9 str r1, [r7, #8]
8009a36: 607a str r2, [r7, #4]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8009a38: 68fb ldr r3, [r7, #12]
8009a3a: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009a3e: b2db uxtb r3, r3
8009a40: 2b02 cmp r3, #2
8009a42: d101 bne.n 8009a48 <HAL_SDRAM_SendCommand+0x1c>
{
return HAL_BUSY;
8009a44: 2302 movs r3, #2
8009a46: e018 b.n 8009a7a <HAL_SDRAM_SendCommand+0x4e>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8009a48: 68fb ldr r3, [r7, #12]
8009a4a: 2202 movs r2, #2
8009a4c: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
8009a50: 68fb ldr r3, [r7, #12]
8009a52: 681b ldr r3, [r3, #0]
8009a54: 687a ldr r2, [r7, #4]
8009a56: 68b9 ldr r1, [r7, #8]
8009a58: 4618 mov r0, r3
8009a5a: f001 fae5 bl 800b028 <FMC_SDRAM_SendCommand>
/* Update the SDRAM controller state state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
8009a5e: 68bb ldr r3, [r7, #8]
8009a60: 681b ldr r3, [r3, #0]
8009a62: 2b02 cmp r3, #2
8009a64: d104 bne.n 8009a70 <HAL_SDRAM_SendCommand+0x44>
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
8009a66: 68fb ldr r3, [r7, #12]
8009a68: 2205 movs r2, #5
8009a6a: f883 202c strb.w r2, [r3, #44] ; 0x2c
8009a6e: e003 b.n 8009a78 <HAL_SDRAM_SendCommand+0x4c>
}
else
{
hsdram->State = HAL_SDRAM_STATE_READY;
8009a70: 68fb ldr r3, [r7, #12]
8009a72: 2201 movs r2, #1
8009a74: f883 202c strb.w r2, [r3, #44] ; 0x2c
}
return HAL_OK;
8009a78: 2300 movs r3, #0
}
8009a7a: 4618 mov r0, r3
8009a7c: 3710 adds r7, #16
8009a7e: 46bd mov sp, r7
8009a80: bd80 pop {r7, pc}
08009a82 <HAL_SDRAM_ProgramRefreshRate>:
* the configuration information for SDRAM module.
* @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
8009a82: b580 push {r7, lr}
8009a84: b082 sub sp, #8
8009a86: af00 add r7, sp, #0
8009a88: 6078 str r0, [r7, #4]
8009a8a: 6039 str r1, [r7, #0]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8009a8c: 687b ldr r3, [r7, #4]
8009a8e: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009a92: b2db uxtb r3, r3
8009a94: 2b02 cmp r3, #2
8009a96: d101 bne.n 8009a9c <HAL_SDRAM_ProgramRefreshRate+0x1a>
{
return HAL_BUSY;
8009a98: 2302 movs r3, #2
8009a9a: e00e b.n 8009aba <HAL_SDRAM_ProgramRefreshRate+0x38>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8009a9c: 687b ldr r3, [r7, #4]
8009a9e: 2202 movs r2, #2
8009aa0: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Program the refresh rate */
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
8009aa4: 687b ldr r3, [r7, #4]
8009aa6: 681b ldr r3, [r3, #0]
8009aa8: 6839 ldr r1, [r7, #0]
8009aaa: 4618 mov r0, r3
8009aac: f001 fadd bl 800b06a <FMC_SDRAM_ProgramRefreshRate>
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
8009ab0: 687b ldr r3, [r7, #4]
8009ab2: 2201 movs r2, #1
8009ab4: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8009ab8: 2300 movs r3, #0
}
8009aba: 4618 mov r0, r3
8009abc: 3708 adds r7, #8
8009abe: 46bd mov sp, r7
8009ac0: bd80 pop {r7, pc}
08009ac2 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8009ac2: b580 push {r7, lr}
8009ac4: b084 sub sp, #16
8009ac6: af00 add r7, sp, #0
8009ac8: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8009aca: 687b ldr r3, [r7, #4]
8009acc: 2b00 cmp r3, #0
8009ace: d101 bne.n 8009ad4 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8009ad0: 2301 movs r3, #1
8009ad2: e084 b.n 8009bde <HAL_SPI_Init+0x11c>
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8009ad4: 687b ldr r3, [r7, #4]
8009ad6: 2200 movs r2, #0
8009ad8: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8009ada: 687b ldr r3, [r7, #4]
8009adc: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
8009ae0: b2db uxtb r3, r3
8009ae2: 2b00 cmp r3, #0
8009ae4: d106 bne.n 8009af4 <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8009ae6: 687b ldr r3, [r7, #4]
8009ae8: 2200 movs r2, #0
8009aea: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8009aee: 6878 ldr r0, [r7, #4]
8009af0: f7fa fbdc bl 80042ac <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8009af4: 687b ldr r3, [r7, #4]
8009af6: 2202 movs r2, #2
8009af8: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8009afc: 687b ldr r3, [r7, #4]
8009afe: 681b ldr r3, [r3, #0]
8009b00: 681a ldr r2, [r3, #0]
8009b02: 687b ldr r3, [r7, #4]
8009b04: 681b ldr r3, [r3, #0]
8009b06: f022 0240 bic.w r2, r2, #64 ; 0x40
8009b0a: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8009b0c: 687b ldr r3, [r7, #4]
8009b0e: 68db ldr r3, [r3, #12]
8009b10: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b14: d902 bls.n 8009b1c <HAL_SPI_Init+0x5a>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8009b16: 2300 movs r3, #0
8009b18: 60fb str r3, [r7, #12]
8009b1a: e002 b.n 8009b22 <HAL_SPI_Init+0x60>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8009b1c: f44f 5380 mov.w r3, #4096 ; 0x1000
8009b20: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8009b22: 687b ldr r3, [r7, #4]
8009b24: 68db ldr r3, [r3, #12]
8009b26: f5b3 6f70 cmp.w r3, #3840 ; 0xf00
8009b2a: d007 beq.n 8009b3c <HAL_SPI_Init+0x7a>
8009b2c: 687b ldr r3, [r7, #4]
8009b2e: 68db ldr r3, [r3, #12]
8009b30: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b34: d002 beq.n 8009b3c <HAL_SPI_Init+0x7a>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8009b36: 687b ldr r3, [r7, #4]
8009b38: 2200 movs r2, #0
8009b3a: 629a str r2, [r3, #40] ; 0x28
}
/* Align the CRC Length on the data size */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
8009b3c: 687b ldr r3, [r7, #4]
8009b3e: 6b1b ldr r3, [r3, #48] ; 0x30
8009b40: 2b00 cmp r3, #0
8009b42: d10b bne.n 8009b5c <HAL_SPI_Init+0x9a>
{
/* CRC Length aligned on the data size : value set by default */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8009b44: 687b ldr r3, [r7, #4]
8009b46: 68db ldr r3, [r3, #12]
8009b48: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b4c: d903 bls.n 8009b56 <HAL_SPI_Init+0x94>
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
8009b4e: 687b ldr r3, [r7, #4]
8009b50: 2202 movs r2, #2
8009b52: 631a str r2, [r3, #48] ; 0x30
8009b54: e002 b.n 8009b5c <HAL_SPI_Init+0x9a>
}
else
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
8009b56: 687b ldr r3, [r7, #4]
8009b58: 2201 movs r2, #1
8009b5a: 631a str r2, [r3, #48] ; 0x30
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
8009b5c: 687b ldr r3, [r7, #4]
8009b5e: 685a ldr r2, [r3, #4]
8009b60: 687b ldr r3, [r7, #4]
8009b62: 689b ldr r3, [r3, #8]
8009b64: 431a orrs r2, r3
8009b66: 687b ldr r3, [r7, #4]
8009b68: 691b ldr r3, [r3, #16]
8009b6a: 431a orrs r2, r3
8009b6c: 687b ldr r3, [r7, #4]
8009b6e: 695b ldr r3, [r3, #20]
8009b70: 431a orrs r2, r3
8009b72: 687b ldr r3, [r7, #4]
8009b74: 699b ldr r3, [r3, #24]
8009b76: f403 7300 and.w r3, r3, #512 ; 0x200
8009b7a: 431a orrs r2, r3
8009b7c: 687b ldr r3, [r7, #4]
8009b7e: 69db ldr r3, [r3, #28]
8009b80: 431a orrs r2, r3
8009b82: 687b ldr r3, [r7, #4]
8009b84: 6a1b ldr r3, [r3, #32]
8009b86: ea42 0103 orr.w r1, r2, r3
8009b8a: 687b ldr r3, [r7, #4]
8009b8c: 6a9a ldr r2, [r3, #40] ; 0x28
8009b8e: 687b ldr r3, [r7, #4]
8009b90: 681b ldr r3, [r3, #0]
8009b92: 430a orrs r2, r1
8009b94: 601a str r2, [r3, #0]
hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
8009b96: 687b ldr r3, [r7, #4]
8009b98: 699b ldr r3, [r3, #24]
8009b9a: 0c1b lsrs r3, r3, #16
8009b9c: f003 0204 and.w r2, r3, #4
8009ba0: 687b ldr r3, [r7, #4]
8009ba2: 6a5b ldr r3, [r3, #36] ; 0x24
8009ba4: 431a orrs r2, r3
8009ba6: 687b ldr r3, [r7, #4]
8009ba8: 6b5b ldr r3, [r3, #52] ; 0x34
8009baa: 431a orrs r2, r3
8009bac: 687b ldr r3, [r7, #4]
8009bae: 68db ldr r3, [r3, #12]
8009bb0: ea42 0103 orr.w r1, r2, r3
8009bb4: 687b ldr r3, [r7, #4]
8009bb6: 681b ldr r3, [r3, #0]
8009bb8: 68fa ldr r2, [r7, #12]
8009bba: 430a orrs r2, r1
8009bbc: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8009bbe: 687b ldr r3, [r7, #4]
8009bc0: 681b ldr r3, [r3, #0]
8009bc2: 69da ldr r2, [r3, #28]
8009bc4: 687b ldr r3, [r7, #4]
8009bc6: 681b ldr r3, [r3, #0]
8009bc8: f422 6200 bic.w r2, r2, #2048 ; 0x800
8009bcc: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8009bce: 687b ldr r3, [r7, #4]
8009bd0: 2200 movs r2, #0
8009bd2: 661a str r2, [r3, #96] ; 0x60
hspi->State = HAL_SPI_STATE_READY;
8009bd4: 687b ldr r3, [r7, #4]
8009bd6: 2201 movs r2, #1
8009bd8: f883 205d strb.w r2, [r3, #93] ; 0x5d
return HAL_OK;
8009bdc: 2300 movs r3, #0
}
8009bde: 4618 mov r0, r3
8009be0: 3710 adds r7, #16
8009be2: 46bd mov sp, r7
8009be4: bd80 pop {r7, pc}
08009be6 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8009be6: b580 push {r7, lr}
8009be8: b082 sub sp, #8
8009bea: af00 add r7, sp, #0
8009bec: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8009bee: 687b ldr r3, [r7, #4]
8009bf0: 2b00 cmp r3, #0
8009bf2: d101 bne.n 8009bf8 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8009bf4: 2301 movs r3, #1
8009bf6: e01d b.n 8009c34 <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8009bf8: 687b ldr r3, [r7, #4]
8009bfa: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009bfe: b2db uxtb r3, r3
8009c00: 2b00 cmp r3, #0
8009c02: d106 bne.n 8009c12 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8009c04: 687b ldr r3, [r7, #4]
8009c06: 2200 movs r2, #0
8009c08: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8009c0c: 6878 ldr r0, [r7, #4]
8009c0e: f7fa fbbf bl 8004390 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009c12: 687b ldr r3, [r7, #4]
8009c14: 2202 movs r2, #2
8009c16: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8009c1a: 687b ldr r3, [r7, #4]
8009c1c: 681a ldr r2, [r3, #0]
8009c1e: 687b ldr r3, [r7, #4]
8009c20: 3304 adds r3, #4
8009c22: 4619 mov r1, r3
8009c24: 4610 mov r0, r2
8009c26: f000 fbc3 bl 800a3b0 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009c2a: 687b ldr r3, [r7, #4]
8009c2c: 2201 movs r2, #1
8009c2e: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009c32: 2300 movs r3, #0
}
8009c34: 4618 mov r0, r3
8009c36: 3708 adds r7, #8
8009c38: 46bd mov sp, r7
8009c3a: bd80 pop {r7, pc}
08009c3c <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8009c3c: b480 push {r7}
8009c3e: b085 sub sp, #20
8009c40: af00 add r7, sp, #0
8009c42: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8009c44: 687b ldr r3, [r7, #4]
8009c46: 681b ldr r3, [r3, #0]
8009c48: 68da ldr r2, [r3, #12]
8009c4a: 687b ldr r3, [r7, #4]
8009c4c: 681b ldr r3, [r3, #0]
8009c4e: f042 0201 orr.w r2, r2, #1
8009c52: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8009c54: 687b ldr r3, [r7, #4]
8009c56: 681b ldr r3, [r3, #0]
8009c58: 689a ldr r2, [r3, #8]
8009c5a: 4b0c ldr r3, [pc, #48] ; (8009c8c <HAL_TIM_Base_Start_IT+0x50>)
8009c5c: 4013 ands r3, r2
8009c5e: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8009c60: 68fb ldr r3, [r7, #12]
8009c62: 2b06 cmp r3, #6
8009c64: d00b beq.n 8009c7e <HAL_TIM_Base_Start_IT+0x42>
8009c66: 68fb ldr r3, [r7, #12]
8009c68: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8009c6c: d007 beq.n 8009c7e <HAL_TIM_Base_Start_IT+0x42>
{
__HAL_TIM_ENABLE(htim);
8009c6e: 687b ldr r3, [r7, #4]
8009c70: 681b ldr r3, [r3, #0]
8009c72: 681a ldr r2, [r3, #0]
8009c74: 687b ldr r3, [r7, #4]
8009c76: 681b ldr r3, [r3, #0]
8009c78: f042 0201 orr.w r2, r2, #1
8009c7c: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8009c7e: 2300 movs r3, #0
}
8009c80: 4618 mov r0, r3
8009c82: 3714 adds r7, #20
8009c84: 46bd mov sp, r7
8009c86: f85d 7b04 ldr.w r7, [sp], #4
8009c8a: 4770 bx lr
8009c8c: 00010007 .word 0x00010007
08009c90 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8009c90: b580 push {r7, lr}
8009c92: b082 sub sp, #8
8009c94: af00 add r7, sp, #0
8009c96: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8009c98: 687b ldr r3, [r7, #4]
8009c9a: 2b00 cmp r3, #0
8009c9c: d101 bne.n 8009ca2 <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8009c9e: 2301 movs r3, #1
8009ca0: e01d b.n 8009cde <HAL_TIM_PWM_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8009ca2: 687b ldr r3, [r7, #4]
8009ca4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009ca8: b2db uxtb r3, r3
8009caa: 2b00 cmp r3, #0
8009cac: d106 bne.n 8009cbc <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8009cae: 687b ldr r3, [r7, #4]
8009cb0: 2200 movs r2, #0
8009cb2: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8009cb6: 6878 ldr r0, [r7, #4]
8009cb8: f000 f815 bl 8009ce6 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009cbc: 687b ldr r3, [r7, #4]
8009cbe: 2202 movs r2, #2
8009cc0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8009cc4: 687b ldr r3, [r7, #4]
8009cc6: 681a ldr r2, [r3, #0]
8009cc8: 687b ldr r3, [r7, #4]
8009cca: 3304 adds r3, #4
8009ccc: 4619 mov r1, r3
8009cce: 4610 mov r0, r2
8009cd0: f000 fb6e bl 800a3b0 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009cd4: 687b ldr r3, [r7, #4]
8009cd6: 2201 movs r2, #1
8009cd8: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009cdc: 2300 movs r3, #0
}
8009cde: 4618 mov r0, r3
8009ce0: 3708 adds r7, #8
8009ce2: 46bd mov sp, r7
8009ce4: bd80 pop {r7, pc}
08009ce6 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8009ce6: b480 push {r7}
8009ce8: b083 sub sp, #12
8009cea: af00 add r7, sp, #0
8009cec: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8009cee: bf00 nop
8009cf0: 370c adds r7, #12
8009cf2: 46bd mov sp, r7
8009cf4: f85d 7b04 ldr.w r7, [sp], #4
8009cf8: 4770 bx lr
08009cfa <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8009cfa: b580 push {r7, lr}
8009cfc: b082 sub sp, #8
8009cfe: af00 add r7, sp, #0
8009d00: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8009d02: 687b ldr r3, [r7, #4]
8009d04: 681b ldr r3, [r3, #0]
8009d06: 691b ldr r3, [r3, #16]
8009d08: f003 0302 and.w r3, r3, #2
8009d0c: 2b02 cmp r3, #2
8009d0e: d122 bne.n 8009d56 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8009d10: 687b ldr r3, [r7, #4]
8009d12: 681b ldr r3, [r3, #0]
8009d14: 68db ldr r3, [r3, #12]
8009d16: f003 0302 and.w r3, r3, #2
8009d1a: 2b02 cmp r3, #2
8009d1c: d11b bne.n 8009d56 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8009d1e: 687b ldr r3, [r7, #4]
8009d20: 681b ldr r3, [r3, #0]
8009d22: f06f 0202 mvn.w r2, #2
8009d26: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8009d28: 687b ldr r3, [r7, #4]
8009d2a: 2201 movs r2, #1
8009d2c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8009d2e: 687b ldr r3, [r7, #4]
8009d30: 681b ldr r3, [r3, #0]
8009d32: 699b ldr r3, [r3, #24]
8009d34: f003 0303 and.w r3, r3, #3
8009d38: 2b00 cmp r3, #0
8009d3a: d003 beq.n 8009d44 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009d3c: 6878 ldr r0, [r7, #4]
8009d3e: f000 fb19 bl 800a374 <HAL_TIM_IC_CaptureCallback>
8009d42: e005 b.n 8009d50 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009d44: 6878 ldr r0, [r7, #4]
8009d46: f000 fb0b bl 800a360 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009d4a: 6878 ldr r0, [r7, #4]
8009d4c: f000 fb1c bl 800a388 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009d50: 687b ldr r3, [r7, #4]
8009d52: 2200 movs r2, #0
8009d54: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8009d56: 687b ldr r3, [r7, #4]
8009d58: 681b ldr r3, [r3, #0]
8009d5a: 691b ldr r3, [r3, #16]
8009d5c: f003 0304 and.w r3, r3, #4
8009d60: 2b04 cmp r3, #4
8009d62: d122 bne.n 8009daa <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8009d64: 687b ldr r3, [r7, #4]
8009d66: 681b ldr r3, [r3, #0]
8009d68: 68db ldr r3, [r3, #12]
8009d6a: f003 0304 and.w r3, r3, #4
8009d6e: 2b04 cmp r3, #4
8009d70: d11b bne.n 8009daa <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8009d72: 687b ldr r3, [r7, #4]
8009d74: 681b ldr r3, [r3, #0]
8009d76: f06f 0204 mvn.w r2, #4
8009d7a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8009d7c: 687b ldr r3, [r7, #4]
8009d7e: 2202 movs r2, #2
8009d80: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8009d82: 687b ldr r3, [r7, #4]
8009d84: 681b ldr r3, [r3, #0]
8009d86: 699b ldr r3, [r3, #24]
8009d88: f403 7340 and.w r3, r3, #768 ; 0x300
8009d8c: 2b00 cmp r3, #0
8009d8e: d003 beq.n 8009d98 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009d90: 6878 ldr r0, [r7, #4]
8009d92: f000 faef bl 800a374 <HAL_TIM_IC_CaptureCallback>
8009d96: e005 b.n 8009da4 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009d98: 6878 ldr r0, [r7, #4]
8009d9a: f000 fae1 bl 800a360 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009d9e: 6878 ldr r0, [r7, #4]
8009da0: f000 faf2 bl 800a388 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009da4: 687b ldr r3, [r7, #4]
8009da6: 2200 movs r2, #0
8009da8: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8009daa: 687b ldr r3, [r7, #4]
8009dac: 681b ldr r3, [r3, #0]
8009dae: 691b ldr r3, [r3, #16]
8009db0: f003 0308 and.w r3, r3, #8
8009db4: 2b08 cmp r3, #8
8009db6: d122 bne.n 8009dfe <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8009db8: 687b ldr r3, [r7, #4]
8009dba: 681b ldr r3, [r3, #0]
8009dbc: 68db ldr r3, [r3, #12]
8009dbe: f003 0308 and.w r3, r3, #8
8009dc2: 2b08 cmp r3, #8
8009dc4: d11b bne.n 8009dfe <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8009dc6: 687b ldr r3, [r7, #4]
8009dc8: 681b ldr r3, [r3, #0]
8009dca: f06f 0208 mvn.w r2, #8
8009dce: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8009dd0: 687b ldr r3, [r7, #4]
8009dd2: 2204 movs r2, #4
8009dd4: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8009dd6: 687b ldr r3, [r7, #4]
8009dd8: 681b ldr r3, [r3, #0]
8009dda: 69db ldr r3, [r3, #28]
8009ddc: f003 0303 and.w r3, r3, #3
8009de0: 2b00 cmp r3, #0
8009de2: d003 beq.n 8009dec <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009de4: 6878 ldr r0, [r7, #4]
8009de6: f000 fac5 bl 800a374 <HAL_TIM_IC_CaptureCallback>
8009dea: e005 b.n 8009df8 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009dec: 6878 ldr r0, [r7, #4]
8009dee: f000 fab7 bl 800a360 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009df2: 6878 ldr r0, [r7, #4]
8009df4: f000 fac8 bl 800a388 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009df8: 687b ldr r3, [r7, #4]
8009dfa: 2200 movs r2, #0
8009dfc: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8009dfe: 687b ldr r3, [r7, #4]
8009e00: 681b ldr r3, [r3, #0]
8009e02: 691b ldr r3, [r3, #16]
8009e04: f003 0310 and.w r3, r3, #16
8009e08: 2b10 cmp r3, #16
8009e0a: d122 bne.n 8009e52 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8009e0c: 687b ldr r3, [r7, #4]
8009e0e: 681b ldr r3, [r3, #0]
8009e10: 68db ldr r3, [r3, #12]
8009e12: f003 0310 and.w r3, r3, #16
8009e16: 2b10 cmp r3, #16
8009e18: d11b bne.n 8009e52 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8009e1a: 687b ldr r3, [r7, #4]
8009e1c: 681b ldr r3, [r3, #0]
8009e1e: f06f 0210 mvn.w r2, #16
8009e22: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8009e24: 687b ldr r3, [r7, #4]
8009e26: 2208 movs r2, #8
8009e28: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8009e2a: 687b ldr r3, [r7, #4]
8009e2c: 681b ldr r3, [r3, #0]
8009e2e: 69db ldr r3, [r3, #28]
8009e30: f403 7340 and.w r3, r3, #768 ; 0x300
8009e34: 2b00 cmp r3, #0
8009e36: d003 beq.n 8009e40 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009e38: 6878 ldr r0, [r7, #4]
8009e3a: f000 fa9b bl 800a374 <HAL_TIM_IC_CaptureCallback>
8009e3e: e005 b.n 8009e4c <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009e40: 6878 ldr r0, [r7, #4]
8009e42: f000 fa8d bl 800a360 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009e46: 6878 ldr r0, [r7, #4]
8009e48: f000 fa9e bl 800a388 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009e4c: 687b ldr r3, [r7, #4]
8009e4e: 2200 movs r2, #0
8009e50: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8009e52: 687b ldr r3, [r7, #4]
8009e54: 681b ldr r3, [r3, #0]
8009e56: 691b ldr r3, [r3, #16]
8009e58: f003 0301 and.w r3, r3, #1
8009e5c: 2b01 cmp r3, #1
8009e5e: d10e bne.n 8009e7e <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8009e60: 687b ldr r3, [r7, #4]
8009e62: 681b ldr r3, [r3, #0]
8009e64: 68db ldr r3, [r3, #12]
8009e66: f003 0301 and.w r3, r3, #1
8009e6a: 2b01 cmp r3, #1
8009e6c: d107 bne.n 8009e7e <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8009e6e: 687b ldr r3, [r7, #4]
8009e70: 681b ldr r3, [r3, #0]
8009e72: f06f 0201 mvn.w r2, #1
8009e76: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8009e78: 6878 ldr r0, [r7, #4]
8009e7a: f7f8 fbc1 bl 8002600 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8009e7e: 687b ldr r3, [r7, #4]
8009e80: 681b ldr r3, [r3, #0]
8009e82: 691b ldr r3, [r3, #16]
8009e84: f003 0380 and.w r3, r3, #128 ; 0x80
8009e88: 2b80 cmp r3, #128 ; 0x80
8009e8a: d10e bne.n 8009eaa <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009e8c: 687b ldr r3, [r7, #4]
8009e8e: 681b ldr r3, [r3, #0]
8009e90: 68db ldr r3, [r3, #12]
8009e92: f003 0380 and.w r3, r3, #128 ; 0x80
8009e96: 2b80 cmp r3, #128 ; 0x80
8009e98: d107 bne.n 8009eaa <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8009e9a: 687b ldr r3, [r7, #4]
8009e9c: 681b ldr r3, [r3, #0]
8009e9e: f06f 0280 mvn.w r2, #128 ; 0x80
8009ea2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8009ea4: 6878 ldr r0, [r7, #4]
8009ea6: f000 ffb9 bl 800ae1c <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8009eaa: 687b ldr r3, [r7, #4]
8009eac: 681b ldr r3, [r3, #0]
8009eae: 691b ldr r3, [r3, #16]
8009eb0: f403 7380 and.w r3, r3, #256 ; 0x100
8009eb4: f5b3 7f80 cmp.w r3, #256 ; 0x100
8009eb8: d10e bne.n 8009ed8 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009eba: 687b ldr r3, [r7, #4]
8009ebc: 681b ldr r3, [r3, #0]
8009ebe: 68db ldr r3, [r3, #12]
8009ec0: f003 0380 and.w r3, r3, #128 ; 0x80
8009ec4: 2b80 cmp r3, #128 ; 0x80
8009ec6: d107 bne.n 8009ed8 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8009ec8: 687b ldr r3, [r7, #4]
8009eca: 681b ldr r3, [r3, #0]
8009ecc: f46f 7280 mvn.w r2, #256 ; 0x100
8009ed0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8009ed2: 6878 ldr r0, [r7, #4]
8009ed4: f000 ffac bl 800ae30 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8009ed8: 687b ldr r3, [r7, #4]
8009eda: 681b ldr r3, [r3, #0]
8009edc: 691b ldr r3, [r3, #16]
8009ede: f003 0340 and.w r3, r3, #64 ; 0x40
8009ee2: 2b40 cmp r3, #64 ; 0x40
8009ee4: d10e bne.n 8009f04 <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8009ee6: 687b ldr r3, [r7, #4]
8009ee8: 681b ldr r3, [r3, #0]
8009eea: 68db ldr r3, [r3, #12]
8009eec: f003 0340 and.w r3, r3, #64 ; 0x40
8009ef0: 2b40 cmp r3, #64 ; 0x40
8009ef2: d107 bne.n 8009f04 <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8009ef4: 687b ldr r3, [r7, #4]
8009ef6: 681b ldr r3, [r3, #0]
8009ef8: f06f 0240 mvn.w r2, #64 ; 0x40
8009efc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8009efe: 6878 ldr r0, [r7, #4]
8009f00: f000 fa4c bl 800a39c <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8009f04: 687b ldr r3, [r7, #4]
8009f06: 681b ldr r3, [r3, #0]
8009f08: 691b ldr r3, [r3, #16]
8009f0a: f003 0320 and.w r3, r3, #32
8009f0e: 2b20 cmp r3, #32
8009f10: d10e bne.n 8009f30 <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8009f12: 687b ldr r3, [r7, #4]
8009f14: 681b ldr r3, [r3, #0]
8009f16: 68db ldr r3, [r3, #12]
8009f18: f003 0320 and.w r3, r3, #32
8009f1c: 2b20 cmp r3, #32
8009f1e: d107 bne.n 8009f30 <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8009f20: 687b ldr r3, [r7, #4]
8009f22: 681b ldr r3, [r3, #0]
8009f24: f06f 0220 mvn.w r2, #32
8009f28: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8009f2a: 6878 ldr r0, [r7, #4]
8009f2c: f000 ff6c bl 800ae08 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8009f30: bf00 nop
8009f32: 3708 adds r7, #8
8009f34: 46bd mov sp, r7
8009f36: bd80 pop {r7, pc}
08009f38 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8009f38: b580 push {r7, lr}
8009f3a: b084 sub sp, #16
8009f3c: af00 add r7, sp, #0
8009f3e: 60f8 str r0, [r7, #12]
8009f40: 60b9 str r1, [r7, #8]
8009f42: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8009f44: 68fb ldr r3, [r7, #12]
8009f46: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009f4a: 2b01 cmp r3, #1
8009f4c: d101 bne.n 8009f52 <HAL_TIM_PWM_ConfigChannel+0x1a>
8009f4e: 2302 movs r3, #2
8009f50: e105 b.n 800a15e <HAL_TIM_PWM_ConfigChannel+0x226>
8009f52: 68fb ldr r3, [r7, #12]
8009f54: 2201 movs r2, #1
8009f56: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8009f5a: 68fb ldr r3, [r7, #12]
8009f5c: 2202 movs r2, #2
8009f5e: f883 203d strb.w r2, [r3, #61] ; 0x3d
switch (Channel)
8009f62: 687b ldr r3, [r7, #4]
8009f64: 2b14 cmp r3, #20
8009f66: f200 80f0 bhi.w 800a14a <HAL_TIM_PWM_ConfigChannel+0x212>
8009f6a: a201 add r2, pc, #4 ; (adr r2, 8009f70 <HAL_TIM_PWM_ConfigChannel+0x38>)
8009f6c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009f70: 08009fc5 .word 0x08009fc5
8009f74: 0800a14b .word 0x0800a14b
8009f78: 0800a14b .word 0x0800a14b
8009f7c: 0800a14b .word 0x0800a14b
8009f80: 0800a005 .word 0x0800a005
8009f84: 0800a14b .word 0x0800a14b
8009f88: 0800a14b .word 0x0800a14b
8009f8c: 0800a14b .word 0x0800a14b
8009f90: 0800a047 .word 0x0800a047
8009f94: 0800a14b .word 0x0800a14b
8009f98: 0800a14b .word 0x0800a14b
8009f9c: 0800a14b .word 0x0800a14b
8009fa0: 0800a087 .word 0x0800a087
8009fa4: 0800a14b .word 0x0800a14b
8009fa8: 0800a14b .word 0x0800a14b
8009fac: 0800a14b .word 0x0800a14b
8009fb0: 0800a0c9 .word 0x0800a0c9
8009fb4: 0800a14b .word 0x0800a14b
8009fb8: 0800a14b .word 0x0800a14b
8009fbc: 0800a14b .word 0x0800a14b
8009fc0: 0800a109 .word 0x0800a109
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8009fc4: 68fb ldr r3, [r7, #12]
8009fc6: 681b ldr r3, [r3, #0]
8009fc8: 68b9 ldr r1, [r7, #8]
8009fca: 4618 mov r0, r3
8009fcc: f000 fa90 bl 800a4f0 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8009fd0: 68fb ldr r3, [r7, #12]
8009fd2: 681b ldr r3, [r3, #0]
8009fd4: 699a ldr r2, [r3, #24]
8009fd6: 68fb ldr r3, [r7, #12]
8009fd8: 681b ldr r3, [r3, #0]
8009fda: f042 0208 orr.w r2, r2, #8
8009fde: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8009fe0: 68fb ldr r3, [r7, #12]
8009fe2: 681b ldr r3, [r3, #0]
8009fe4: 699a ldr r2, [r3, #24]
8009fe6: 68fb ldr r3, [r7, #12]
8009fe8: 681b ldr r3, [r3, #0]
8009fea: f022 0204 bic.w r2, r2, #4
8009fee: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8009ff0: 68fb ldr r3, [r7, #12]
8009ff2: 681b ldr r3, [r3, #0]
8009ff4: 6999 ldr r1, [r3, #24]
8009ff6: 68bb ldr r3, [r7, #8]
8009ff8: 691a ldr r2, [r3, #16]
8009ffa: 68fb ldr r3, [r7, #12]
8009ffc: 681b ldr r3, [r3, #0]
8009ffe: 430a orrs r2, r1
800a000: 619a str r2, [r3, #24]
break;
800a002: e0a3 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
800a004: 68fb ldr r3, [r7, #12]
800a006: 681b ldr r3, [r3, #0]
800a008: 68b9 ldr r1, [r7, #8]
800a00a: 4618 mov r0, r3
800a00c: f000 fae2 bl 800a5d4 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
800a010: 68fb ldr r3, [r7, #12]
800a012: 681b ldr r3, [r3, #0]
800a014: 699a ldr r2, [r3, #24]
800a016: 68fb ldr r3, [r7, #12]
800a018: 681b ldr r3, [r3, #0]
800a01a: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a01e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
800a020: 68fb ldr r3, [r7, #12]
800a022: 681b ldr r3, [r3, #0]
800a024: 699a ldr r2, [r3, #24]
800a026: 68fb ldr r3, [r7, #12]
800a028: 681b ldr r3, [r3, #0]
800a02a: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a02e: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
800a030: 68fb ldr r3, [r7, #12]
800a032: 681b ldr r3, [r3, #0]
800a034: 6999 ldr r1, [r3, #24]
800a036: 68bb ldr r3, [r7, #8]
800a038: 691b ldr r3, [r3, #16]
800a03a: 021a lsls r2, r3, #8
800a03c: 68fb ldr r3, [r7, #12]
800a03e: 681b ldr r3, [r3, #0]
800a040: 430a orrs r2, r1
800a042: 619a str r2, [r3, #24]
break;
800a044: e082 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800a046: 68fb ldr r3, [r7, #12]
800a048: 681b ldr r3, [r3, #0]
800a04a: 68b9 ldr r1, [r7, #8]
800a04c: 4618 mov r0, r3
800a04e: f000 fb39 bl 800a6c4 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800a052: 68fb ldr r3, [r7, #12]
800a054: 681b ldr r3, [r3, #0]
800a056: 69da ldr r2, [r3, #28]
800a058: 68fb ldr r3, [r7, #12]
800a05a: 681b ldr r3, [r3, #0]
800a05c: f042 0208 orr.w r2, r2, #8
800a060: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800a062: 68fb ldr r3, [r7, #12]
800a064: 681b ldr r3, [r3, #0]
800a066: 69da ldr r2, [r3, #28]
800a068: 68fb ldr r3, [r7, #12]
800a06a: 681b ldr r3, [r3, #0]
800a06c: f022 0204 bic.w r2, r2, #4
800a070: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800a072: 68fb ldr r3, [r7, #12]
800a074: 681b ldr r3, [r3, #0]
800a076: 69d9 ldr r1, [r3, #28]
800a078: 68bb ldr r3, [r7, #8]
800a07a: 691a ldr r2, [r3, #16]
800a07c: 68fb ldr r3, [r7, #12]
800a07e: 681b ldr r3, [r3, #0]
800a080: 430a orrs r2, r1
800a082: 61da str r2, [r3, #28]
break;
800a084: e062 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800a086: 68fb ldr r3, [r7, #12]
800a088: 681b ldr r3, [r3, #0]
800a08a: 68b9 ldr r1, [r7, #8]
800a08c: 4618 mov r0, r3
800a08e: f000 fb8f bl 800a7b0 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800a092: 68fb ldr r3, [r7, #12]
800a094: 681b ldr r3, [r3, #0]
800a096: 69da ldr r2, [r3, #28]
800a098: 68fb ldr r3, [r7, #12]
800a09a: 681b ldr r3, [r3, #0]
800a09c: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a0a0: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800a0a2: 68fb ldr r3, [r7, #12]
800a0a4: 681b ldr r3, [r3, #0]
800a0a6: 69da ldr r2, [r3, #28]
800a0a8: 68fb ldr r3, [r7, #12]
800a0aa: 681b ldr r3, [r3, #0]
800a0ac: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a0b0: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800a0b2: 68fb ldr r3, [r7, #12]
800a0b4: 681b ldr r3, [r3, #0]
800a0b6: 69d9 ldr r1, [r3, #28]
800a0b8: 68bb ldr r3, [r7, #8]
800a0ba: 691b ldr r3, [r3, #16]
800a0bc: 021a lsls r2, r3, #8
800a0be: 68fb ldr r3, [r7, #12]
800a0c0: 681b ldr r3, [r3, #0]
800a0c2: 430a orrs r2, r1
800a0c4: 61da str r2, [r3, #28]
break;
800a0c6: e041 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
800a0c8: 68fb ldr r3, [r7, #12]
800a0ca: 681b ldr r3, [r3, #0]
800a0cc: 68b9 ldr r1, [r7, #8]
800a0ce: 4618 mov r0, r3
800a0d0: f000 fbc6 bl 800a860 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
800a0d4: 68fb ldr r3, [r7, #12]
800a0d6: 681b ldr r3, [r3, #0]
800a0d8: 6d5a ldr r2, [r3, #84] ; 0x54
800a0da: 68fb ldr r3, [r7, #12]
800a0dc: 681b ldr r3, [r3, #0]
800a0de: f042 0208 orr.w r2, r2, #8
800a0e2: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
800a0e4: 68fb ldr r3, [r7, #12]
800a0e6: 681b ldr r3, [r3, #0]
800a0e8: 6d5a ldr r2, [r3, #84] ; 0x54
800a0ea: 68fb ldr r3, [r7, #12]
800a0ec: 681b ldr r3, [r3, #0]
800a0ee: f022 0204 bic.w r2, r2, #4
800a0f2: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
800a0f4: 68fb ldr r3, [r7, #12]
800a0f6: 681b ldr r3, [r3, #0]
800a0f8: 6d59 ldr r1, [r3, #84] ; 0x54
800a0fa: 68bb ldr r3, [r7, #8]
800a0fc: 691a ldr r2, [r3, #16]
800a0fe: 68fb ldr r3, [r7, #12]
800a100: 681b ldr r3, [r3, #0]
800a102: 430a orrs r2, r1
800a104: 655a str r2, [r3, #84] ; 0x54
break;
800a106: e021 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
800a108: 68fb ldr r3, [r7, #12]
800a10a: 681b ldr r3, [r3, #0]
800a10c: 68b9 ldr r1, [r7, #8]
800a10e: 4618 mov r0, r3
800a110: f000 fbf8 bl 800a904 <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
800a114: 68fb ldr r3, [r7, #12]
800a116: 681b ldr r3, [r3, #0]
800a118: 6d5a ldr r2, [r3, #84] ; 0x54
800a11a: 68fb ldr r3, [r7, #12]
800a11c: 681b ldr r3, [r3, #0]
800a11e: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a122: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800a124: 68fb ldr r3, [r7, #12]
800a126: 681b ldr r3, [r3, #0]
800a128: 6d5a ldr r2, [r3, #84] ; 0x54
800a12a: 68fb ldr r3, [r7, #12]
800a12c: 681b ldr r3, [r3, #0]
800a12e: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a132: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
800a134: 68fb ldr r3, [r7, #12]
800a136: 681b ldr r3, [r3, #0]
800a138: 6d59 ldr r1, [r3, #84] ; 0x54
800a13a: 68bb ldr r3, [r7, #8]
800a13c: 691b ldr r3, [r3, #16]
800a13e: 021a lsls r2, r3, #8
800a140: 68fb ldr r3, [r7, #12]
800a142: 681b ldr r3, [r3, #0]
800a144: 430a orrs r2, r1
800a146: 655a str r2, [r3, #84] ; 0x54
break;
800a148: e000 b.n 800a14c <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
break;
800a14a: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800a14c: 68fb ldr r3, [r7, #12]
800a14e: 2201 movs r2, #1
800a150: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a154: 68fb ldr r3, [r7, #12]
800a156: 2200 movs r2, #0
800a158: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a15c: 2300 movs r3, #0
}
800a15e: 4618 mov r0, r3
800a160: 3710 adds r7, #16
800a162: 46bd mov sp, r7
800a164: bd80 pop {r7, pc}
800a166: bf00 nop
0800a168 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800a168: b580 push {r7, lr}
800a16a: b084 sub sp, #16
800a16c: af00 add r7, sp, #0
800a16e: 6078 str r0, [r7, #4]
800a170: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800a172: 687b ldr r3, [r7, #4]
800a174: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a178: 2b01 cmp r3, #1
800a17a: d101 bne.n 800a180 <HAL_TIM_ConfigClockSource+0x18>
800a17c: 2302 movs r3, #2
800a17e: e0a6 b.n 800a2ce <HAL_TIM_ConfigClockSource+0x166>
800a180: 687b ldr r3, [r7, #4]
800a182: 2201 movs r2, #1
800a184: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a188: 687b ldr r3, [r7, #4]
800a18a: 2202 movs r2, #2
800a18c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800a190: 687b ldr r3, [r7, #4]
800a192: 681b ldr r3, [r3, #0]
800a194: 689b ldr r3, [r3, #8]
800a196: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
800a198: 68fa ldr r2, [r7, #12]
800a19a: 4b4f ldr r3, [pc, #316] ; (800a2d8 <HAL_TIM_ConfigClockSource+0x170>)
800a19c: 4013 ands r3, r2
800a19e: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800a1a0: 68fb ldr r3, [r7, #12]
800a1a2: f423 437f bic.w r3, r3, #65280 ; 0xff00
800a1a6: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a1a8: 687b ldr r3, [r7, #4]
800a1aa: 681b ldr r3, [r3, #0]
800a1ac: 68fa ldr r2, [r7, #12]
800a1ae: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800a1b0: 683b ldr r3, [r7, #0]
800a1b2: 681b ldr r3, [r3, #0]
800a1b4: 2b40 cmp r3, #64 ; 0x40
800a1b6: d067 beq.n 800a288 <HAL_TIM_ConfigClockSource+0x120>
800a1b8: 2b40 cmp r3, #64 ; 0x40
800a1ba: d80b bhi.n 800a1d4 <HAL_TIM_ConfigClockSource+0x6c>
800a1bc: 2b10 cmp r3, #16
800a1be: d073 beq.n 800a2a8 <HAL_TIM_ConfigClockSource+0x140>
800a1c0: 2b10 cmp r3, #16
800a1c2: d802 bhi.n 800a1ca <HAL_TIM_ConfigClockSource+0x62>
800a1c4: 2b00 cmp r3, #0
800a1c6: d06f beq.n 800a2a8 <HAL_TIM_ConfigClockSource+0x140>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
800a1c8: e078 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1ca: 2b20 cmp r3, #32
800a1cc: d06c beq.n 800a2a8 <HAL_TIM_ConfigClockSource+0x140>
800a1ce: 2b30 cmp r3, #48 ; 0x30
800a1d0: d06a beq.n 800a2a8 <HAL_TIM_ConfigClockSource+0x140>
break;
800a1d2: e073 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1d4: 2b70 cmp r3, #112 ; 0x70
800a1d6: d00d beq.n 800a1f4 <HAL_TIM_ConfigClockSource+0x8c>
800a1d8: 2b70 cmp r3, #112 ; 0x70
800a1da: d804 bhi.n 800a1e6 <HAL_TIM_ConfigClockSource+0x7e>
800a1dc: 2b50 cmp r3, #80 ; 0x50
800a1de: d033 beq.n 800a248 <HAL_TIM_ConfigClockSource+0xe0>
800a1e0: 2b60 cmp r3, #96 ; 0x60
800a1e2: d041 beq.n 800a268 <HAL_TIM_ConfigClockSource+0x100>
break;
800a1e4: e06a b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1e6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a1ea: d066 beq.n 800a2ba <HAL_TIM_ConfigClockSource+0x152>
800a1ec: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800a1f0: d017 beq.n 800a222 <HAL_TIM_ConfigClockSource+0xba>
break;
800a1f2: e063 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
800a1f4: 687b ldr r3, [r7, #4]
800a1f6: 6818 ldr r0, [r3, #0]
800a1f8: 683b ldr r3, [r7, #0]
800a1fa: 6899 ldr r1, [r3, #8]
800a1fc: 683b ldr r3, [r7, #0]
800a1fe: 685a ldr r2, [r3, #4]
800a200: 683b ldr r3, [r7, #0]
800a202: 68db ldr r3, [r3, #12]
800a204: f000 fcd4 bl 800abb0 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
800a208: 687b ldr r3, [r7, #4]
800a20a: 681b ldr r3, [r3, #0]
800a20c: 689b ldr r3, [r3, #8]
800a20e: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800a210: 68fb ldr r3, [r7, #12]
800a212: f043 0377 orr.w r3, r3, #119 ; 0x77
800a216: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a218: 687b ldr r3, [r7, #4]
800a21a: 681b ldr r3, [r3, #0]
800a21c: 68fa ldr r2, [r7, #12]
800a21e: 609a str r2, [r3, #8]
break;
800a220: e04c b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
800a222: 687b ldr r3, [r7, #4]
800a224: 6818 ldr r0, [r3, #0]
800a226: 683b ldr r3, [r7, #0]
800a228: 6899 ldr r1, [r3, #8]
800a22a: 683b ldr r3, [r7, #0]
800a22c: 685a ldr r2, [r3, #4]
800a22e: 683b ldr r3, [r7, #0]
800a230: 68db ldr r3, [r3, #12]
800a232: f000 fcbd bl 800abb0 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
800a236: 687b ldr r3, [r7, #4]
800a238: 681b ldr r3, [r3, #0]
800a23a: 689a ldr r2, [r3, #8]
800a23c: 687b ldr r3, [r7, #4]
800a23e: 681b ldr r3, [r3, #0]
800a240: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800a244: 609a str r2, [r3, #8]
break;
800a246: e039 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
800a248: 687b ldr r3, [r7, #4]
800a24a: 6818 ldr r0, [r3, #0]
800a24c: 683b ldr r3, [r7, #0]
800a24e: 6859 ldr r1, [r3, #4]
800a250: 683b ldr r3, [r7, #0]
800a252: 68db ldr r3, [r3, #12]
800a254: 461a mov r2, r3
800a256: f000 fc31 bl 800aabc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800a25a: 687b ldr r3, [r7, #4]
800a25c: 681b ldr r3, [r3, #0]
800a25e: 2150 movs r1, #80 ; 0x50
800a260: 4618 mov r0, r3
800a262: f000 fc8a bl 800ab7a <TIM_ITRx_SetConfig>
break;
800a266: e029 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI2_ConfigInputStage(htim->Instance,
800a268: 687b ldr r3, [r7, #4]
800a26a: 6818 ldr r0, [r3, #0]
800a26c: 683b ldr r3, [r7, #0]
800a26e: 6859 ldr r1, [r3, #4]
800a270: 683b ldr r3, [r7, #0]
800a272: 68db ldr r3, [r3, #12]
800a274: 461a mov r2, r3
800a276: f000 fc50 bl 800ab1a <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800a27a: 687b ldr r3, [r7, #4]
800a27c: 681b ldr r3, [r3, #0]
800a27e: 2160 movs r1, #96 ; 0x60
800a280: 4618 mov r0, r3
800a282: f000 fc7a bl 800ab7a <TIM_ITRx_SetConfig>
break;
800a286: e019 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
800a288: 687b ldr r3, [r7, #4]
800a28a: 6818 ldr r0, [r3, #0]
800a28c: 683b ldr r3, [r7, #0]
800a28e: 6859 ldr r1, [r3, #4]
800a290: 683b ldr r3, [r7, #0]
800a292: 68db ldr r3, [r3, #12]
800a294: 461a mov r2, r3
800a296: f000 fc11 bl 800aabc <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800a29a: 687b ldr r3, [r7, #4]
800a29c: 681b ldr r3, [r3, #0]
800a29e: 2140 movs r1, #64 ; 0x40
800a2a0: 4618 mov r0, r3
800a2a2: f000 fc6a bl 800ab7a <TIM_ITRx_SetConfig>
break;
800a2a6: e009 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800a2a8: 687b ldr r3, [r7, #4]
800a2aa: 681a ldr r2, [r3, #0]
800a2ac: 683b ldr r3, [r7, #0]
800a2ae: 681b ldr r3, [r3, #0]
800a2b0: 4619 mov r1, r3
800a2b2: 4610 mov r0, r2
800a2b4: f000 fc61 bl 800ab7a <TIM_ITRx_SetConfig>
break;
800a2b8: e000 b.n 800a2bc <HAL_TIM_ConfigClockSource+0x154>
break;
800a2ba: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800a2bc: 687b ldr r3, [r7, #4]
800a2be: 2201 movs r2, #1
800a2c0: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a2c4: 687b ldr r3, [r7, #4]
800a2c6: 2200 movs r2, #0
800a2c8: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a2cc: 2300 movs r3, #0
}
800a2ce: 4618 mov r0, r3
800a2d0: 3710 adds r7, #16
800a2d2: 46bd mov sp, r7
800a2d4: bd80 pop {r7, pc}
800a2d6: bf00 nop
800a2d8: fffeff88 .word 0xfffeff88
0800a2dc <HAL_TIM_SlaveConfigSynchro>:
* timer input or external trigger input) and the Slave mode
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a2dc: b580 push {r7, lr}
800a2de: b082 sub sp, #8
800a2e0: af00 add r7, sp, #0
800a2e2: 6078 str r0, [r7, #4]
800a2e4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
__HAL_LOCK(htim);
800a2e6: 687b ldr r3, [r7, #4]
800a2e8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a2ec: 2b01 cmp r3, #1
800a2ee: d101 bne.n 800a2f4 <HAL_TIM_SlaveConfigSynchro+0x18>
800a2f0: 2302 movs r3, #2
800a2f2: e031 b.n 800a358 <HAL_TIM_SlaveConfigSynchro+0x7c>
800a2f4: 687b ldr r3, [r7, #4]
800a2f6: 2201 movs r2, #1
800a2f8: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a2fc: 687b ldr r3, [r7, #4]
800a2fe: 2202 movs r2, #2
800a300: f883 203d strb.w r2, [r3, #61] ; 0x3d
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
800a304: 6839 ldr r1, [r7, #0]
800a306: 6878 ldr r0, [r7, #4]
800a308: f000 fb50 bl 800a9ac <TIM_SlaveTimer_SetConfig>
800a30c: 4603 mov r3, r0
800a30e: 2b00 cmp r3, #0
800a310: d009 beq.n 800a326 <HAL_TIM_SlaveConfigSynchro+0x4a>
{
htim->State = HAL_TIM_STATE_READY;
800a312: 687b ldr r3, [r7, #4]
800a314: 2201 movs r2, #1
800a316: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a31a: 687b ldr r3, [r7, #4]
800a31c: 2200 movs r2, #0
800a31e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
800a322: 2301 movs r3, #1
800a324: e018 b.n 800a358 <HAL_TIM_SlaveConfigSynchro+0x7c>
}
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
800a326: 687b ldr r3, [r7, #4]
800a328: 681b ldr r3, [r3, #0]
800a32a: 68da ldr r2, [r3, #12]
800a32c: 687b ldr r3, [r7, #4]
800a32e: 681b ldr r3, [r3, #0]
800a330: f022 0240 bic.w r2, r2, #64 ; 0x40
800a334: 60da str r2, [r3, #12]
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
800a336: 687b ldr r3, [r7, #4]
800a338: 681b ldr r3, [r3, #0]
800a33a: 68da ldr r2, [r3, #12]
800a33c: 687b ldr r3, [r7, #4]
800a33e: 681b ldr r3, [r3, #0]
800a340: f422 4280 bic.w r2, r2, #16384 ; 0x4000
800a344: 60da str r2, [r3, #12]
htim->State = HAL_TIM_STATE_READY;
800a346: 687b ldr r3, [r7, #4]
800a348: 2201 movs r2, #1
800a34a: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a34e: 687b ldr r3, [r7, #4]
800a350: 2200 movs r2, #0
800a352: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a356: 2300 movs r3, #0
}
800a358: 4618 mov r0, r3
800a35a: 3708 adds r7, #8
800a35c: 46bd mov sp, r7
800a35e: bd80 pop {r7, pc}
0800a360 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800a360: b480 push {r7}
800a362: b083 sub sp, #12
800a364: af00 add r7, sp, #0
800a366: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800a368: bf00 nop
800a36a: 370c adds r7, #12
800a36c: 46bd mov sp, r7
800a36e: f85d 7b04 ldr.w r7, [sp], #4
800a372: 4770 bx lr
0800a374 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800a374: b480 push {r7}
800a376: b083 sub sp, #12
800a378: af00 add r7, sp, #0
800a37a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800a37c: bf00 nop
800a37e: 370c adds r7, #12
800a380: 46bd mov sp, r7
800a382: f85d 7b04 ldr.w r7, [sp], #4
800a386: 4770 bx lr
0800a388 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800a388: b480 push {r7}
800a38a: b083 sub sp, #12
800a38c: af00 add r7, sp, #0
800a38e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800a390: bf00 nop
800a392: 370c adds r7, #12
800a394: 46bd mov sp, r7
800a396: f85d 7b04 ldr.w r7, [sp], #4
800a39a: 4770 bx lr
0800a39c <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800a39c: b480 push {r7}
800a39e: b083 sub sp, #12
800a3a0: af00 add r7, sp, #0
800a3a2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800a3a4: bf00 nop
800a3a6: 370c adds r7, #12
800a3a8: 46bd mov sp, r7
800a3aa: f85d 7b04 ldr.w r7, [sp], #4
800a3ae: 4770 bx lr
0800a3b0 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
800a3b0: b480 push {r7}
800a3b2: b085 sub sp, #20
800a3b4: af00 add r7, sp, #0
800a3b6: 6078 str r0, [r7, #4]
800a3b8: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800a3ba: 687b ldr r3, [r7, #4]
800a3bc: 681b ldr r3, [r3, #0]
800a3be: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800a3c0: 687b ldr r3, [r7, #4]
800a3c2: 4a40 ldr r2, [pc, #256] ; (800a4c4 <TIM_Base_SetConfig+0x114>)
800a3c4: 4293 cmp r3, r2
800a3c6: d013 beq.n 800a3f0 <TIM_Base_SetConfig+0x40>
800a3c8: 687b ldr r3, [r7, #4]
800a3ca: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a3ce: d00f beq.n 800a3f0 <TIM_Base_SetConfig+0x40>
800a3d0: 687b ldr r3, [r7, #4]
800a3d2: 4a3d ldr r2, [pc, #244] ; (800a4c8 <TIM_Base_SetConfig+0x118>)
800a3d4: 4293 cmp r3, r2
800a3d6: d00b beq.n 800a3f0 <TIM_Base_SetConfig+0x40>
800a3d8: 687b ldr r3, [r7, #4]
800a3da: 4a3c ldr r2, [pc, #240] ; (800a4cc <TIM_Base_SetConfig+0x11c>)
800a3dc: 4293 cmp r3, r2
800a3de: d007 beq.n 800a3f0 <TIM_Base_SetConfig+0x40>
800a3e0: 687b ldr r3, [r7, #4]
800a3e2: 4a3b ldr r2, [pc, #236] ; (800a4d0 <TIM_Base_SetConfig+0x120>)
800a3e4: 4293 cmp r3, r2
800a3e6: d003 beq.n 800a3f0 <TIM_Base_SetConfig+0x40>
800a3e8: 687b ldr r3, [r7, #4]
800a3ea: 4a3a ldr r2, [pc, #232] ; (800a4d4 <TIM_Base_SetConfig+0x124>)
800a3ec: 4293 cmp r3, r2
800a3ee: d108 bne.n 800a402 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800a3f0: 68fb ldr r3, [r7, #12]
800a3f2: f023 0370 bic.w r3, r3, #112 ; 0x70
800a3f6: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800a3f8: 683b ldr r3, [r7, #0]
800a3fa: 685b ldr r3, [r3, #4]
800a3fc: 68fa ldr r2, [r7, #12]
800a3fe: 4313 orrs r3, r2
800a400: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800a402: 687b ldr r3, [r7, #4]
800a404: 4a2f ldr r2, [pc, #188] ; (800a4c4 <TIM_Base_SetConfig+0x114>)
800a406: 4293 cmp r3, r2
800a408: d02b beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a40a: 687b ldr r3, [r7, #4]
800a40c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a410: d027 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a412: 687b ldr r3, [r7, #4]
800a414: 4a2c ldr r2, [pc, #176] ; (800a4c8 <TIM_Base_SetConfig+0x118>)
800a416: 4293 cmp r3, r2
800a418: d023 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a41a: 687b ldr r3, [r7, #4]
800a41c: 4a2b ldr r2, [pc, #172] ; (800a4cc <TIM_Base_SetConfig+0x11c>)
800a41e: 4293 cmp r3, r2
800a420: d01f beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a422: 687b ldr r3, [r7, #4]
800a424: 4a2a ldr r2, [pc, #168] ; (800a4d0 <TIM_Base_SetConfig+0x120>)
800a426: 4293 cmp r3, r2
800a428: d01b beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a42a: 687b ldr r3, [r7, #4]
800a42c: 4a29 ldr r2, [pc, #164] ; (800a4d4 <TIM_Base_SetConfig+0x124>)
800a42e: 4293 cmp r3, r2
800a430: d017 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a432: 687b ldr r3, [r7, #4]
800a434: 4a28 ldr r2, [pc, #160] ; (800a4d8 <TIM_Base_SetConfig+0x128>)
800a436: 4293 cmp r3, r2
800a438: d013 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a43a: 687b ldr r3, [r7, #4]
800a43c: 4a27 ldr r2, [pc, #156] ; (800a4dc <TIM_Base_SetConfig+0x12c>)
800a43e: 4293 cmp r3, r2
800a440: d00f beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a442: 687b ldr r3, [r7, #4]
800a444: 4a26 ldr r2, [pc, #152] ; (800a4e0 <TIM_Base_SetConfig+0x130>)
800a446: 4293 cmp r3, r2
800a448: d00b beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a44a: 687b ldr r3, [r7, #4]
800a44c: 4a25 ldr r2, [pc, #148] ; (800a4e4 <TIM_Base_SetConfig+0x134>)
800a44e: 4293 cmp r3, r2
800a450: d007 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a452: 687b ldr r3, [r7, #4]
800a454: 4a24 ldr r2, [pc, #144] ; (800a4e8 <TIM_Base_SetConfig+0x138>)
800a456: 4293 cmp r3, r2
800a458: d003 beq.n 800a462 <TIM_Base_SetConfig+0xb2>
800a45a: 687b ldr r3, [r7, #4]
800a45c: 4a23 ldr r2, [pc, #140] ; (800a4ec <TIM_Base_SetConfig+0x13c>)
800a45e: 4293 cmp r3, r2
800a460: d108 bne.n 800a474 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800a462: 68fb ldr r3, [r7, #12]
800a464: f423 7340 bic.w r3, r3, #768 ; 0x300
800a468: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800a46a: 683b ldr r3, [r7, #0]
800a46c: 68db ldr r3, [r3, #12]
800a46e: 68fa ldr r2, [r7, #12]
800a470: 4313 orrs r3, r2
800a472: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800a474: 68fb ldr r3, [r7, #12]
800a476: f023 0280 bic.w r2, r3, #128 ; 0x80
800a47a: 683b ldr r3, [r7, #0]
800a47c: 695b ldr r3, [r3, #20]
800a47e: 4313 orrs r3, r2
800a480: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800a482: 687b ldr r3, [r7, #4]
800a484: 68fa ldr r2, [r7, #12]
800a486: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800a488: 683b ldr r3, [r7, #0]
800a48a: 689a ldr r2, [r3, #8]
800a48c: 687b ldr r3, [r7, #4]
800a48e: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800a490: 683b ldr r3, [r7, #0]
800a492: 681a ldr r2, [r3, #0]
800a494: 687b ldr r3, [r7, #4]
800a496: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800a498: 687b ldr r3, [r7, #4]
800a49a: 4a0a ldr r2, [pc, #40] ; (800a4c4 <TIM_Base_SetConfig+0x114>)
800a49c: 4293 cmp r3, r2
800a49e: d003 beq.n 800a4a8 <TIM_Base_SetConfig+0xf8>
800a4a0: 687b ldr r3, [r7, #4]
800a4a2: 4a0c ldr r2, [pc, #48] ; (800a4d4 <TIM_Base_SetConfig+0x124>)
800a4a4: 4293 cmp r3, r2
800a4a6: d103 bne.n 800a4b0 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800a4a8: 683b ldr r3, [r7, #0]
800a4aa: 691a ldr r2, [r3, #16]
800a4ac: 687b ldr r3, [r7, #4]
800a4ae: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800a4b0: 687b ldr r3, [r7, #4]
800a4b2: 2201 movs r2, #1
800a4b4: 615a str r2, [r3, #20]
}
800a4b6: bf00 nop
800a4b8: 3714 adds r7, #20
800a4ba: 46bd mov sp, r7
800a4bc: f85d 7b04 ldr.w r7, [sp], #4
800a4c0: 4770 bx lr
800a4c2: bf00 nop
800a4c4: 40010000 .word 0x40010000
800a4c8: 40000400 .word 0x40000400
800a4cc: 40000800 .word 0x40000800
800a4d0: 40000c00 .word 0x40000c00
800a4d4: 40010400 .word 0x40010400
800a4d8: 40014000 .word 0x40014000
800a4dc: 40014400 .word 0x40014400
800a4e0: 40014800 .word 0x40014800
800a4e4: 40001800 .word 0x40001800
800a4e8: 40001c00 .word 0x40001c00
800a4ec: 40002000 .word 0x40002000
0800a4f0 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a4f0: b480 push {r7}
800a4f2: b087 sub sp, #28
800a4f4: af00 add r7, sp, #0
800a4f6: 6078 str r0, [r7, #4]
800a4f8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800a4fa: 687b ldr r3, [r7, #4]
800a4fc: 6a1b ldr r3, [r3, #32]
800a4fe: f023 0201 bic.w r2, r3, #1
800a502: 687b ldr r3, [r7, #4]
800a504: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a506: 687b ldr r3, [r7, #4]
800a508: 6a1b ldr r3, [r3, #32]
800a50a: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a50c: 687b ldr r3, [r7, #4]
800a50e: 685b ldr r3, [r3, #4]
800a510: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a512: 687b ldr r3, [r7, #4]
800a514: 699b ldr r3, [r3, #24]
800a516: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800a518: 68fa ldr r2, [r7, #12]
800a51a: 4b2b ldr r3, [pc, #172] ; (800a5c8 <TIM_OC1_SetConfig+0xd8>)
800a51c: 4013 ands r3, r2
800a51e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800a520: 68fb ldr r3, [r7, #12]
800a522: f023 0303 bic.w r3, r3, #3
800a526: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a528: 683b ldr r3, [r7, #0]
800a52a: 681b ldr r3, [r3, #0]
800a52c: 68fa ldr r2, [r7, #12]
800a52e: 4313 orrs r3, r2
800a530: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800a532: 697b ldr r3, [r7, #20]
800a534: f023 0302 bic.w r3, r3, #2
800a538: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800a53a: 683b ldr r3, [r7, #0]
800a53c: 689b ldr r3, [r3, #8]
800a53e: 697a ldr r2, [r7, #20]
800a540: 4313 orrs r3, r2
800a542: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800a544: 687b ldr r3, [r7, #4]
800a546: 4a21 ldr r2, [pc, #132] ; (800a5cc <TIM_OC1_SetConfig+0xdc>)
800a548: 4293 cmp r3, r2
800a54a: d003 beq.n 800a554 <TIM_OC1_SetConfig+0x64>
800a54c: 687b ldr r3, [r7, #4]
800a54e: 4a20 ldr r2, [pc, #128] ; (800a5d0 <TIM_OC1_SetConfig+0xe0>)
800a550: 4293 cmp r3, r2
800a552: d10c bne.n 800a56e <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800a554: 697b ldr r3, [r7, #20]
800a556: f023 0308 bic.w r3, r3, #8
800a55a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800a55c: 683b ldr r3, [r7, #0]
800a55e: 68db ldr r3, [r3, #12]
800a560: 697a ldr r2, [r7, #20]
800a562: 4313 orrs r3, r2
800a564: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800a566: 697b ldr r3, [r7, #20]
800a568: f023 0304 bic.w r3, r3, #4
800a56c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a56e: 687b ldr r3, [r7, #4]
800a570: 4a16 ldr r2, [pc, #88] ; (800a5cc <TIM_OC1_SetConfig+0xdc>)
800a572: 4293 cmp r3, r2
800a574: d003 beq.n 800a57e <TIM_OC1_SetConfig+0x8e>
800a576: 687b ldr r3, [r7, #4]
800a578: 4a15 ldr r2, [pc, #84] ; (800a5d0 <TIM_OC1_SetConfig+0xe0>)
800a57a: 4293 cmp r3, r2
800a57c: d111 bne.n 800a5a2 <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800a57e: 693b ldr r3, [r7, #16]
800a580: f423 7380 bic.w r3, r3, #256 ; 0x100
800a584: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800a586: 693b ldr r3, [r7, #16]
800a588: f423 7300 bic.w r3, r3, #512 ; 0x200
800a58c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800a58e: 683b ldr r3, [r7, #0]
800a590: 695b ldr r3, [r3, #20]
800a592: 693a ldr r2, [r7, #16]
800a594: 4313 orrs r3, r2
800a596: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800a598: 683b ldr r3, [r7, #0]
800a59a: 699b ldr r3, [r3, #24]
800a59c: 693a ldr r2, [r7, #16]
800a59e: 4313 orrs r3, r2
800a5a0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a5a2: 687b ldr r3, [r7, #4]
800a5a4: 693a ldr r2, [r7, #16]
800a5a6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a5a8: 687b ldr r3, [r7, #4]
800a5aa: 68fa ldr r2, [r7, #12]
800a5ac: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800a5ae: 683b ldr r3, [r7, #0]
800a5b0: 685a ldr r2, [r3, #4]
800a5b2: 687b ldr r3, [r7, #4]
800a5b4: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a5b6: 687b ldr r3, [r7, #4]
800a5b8: 697a ldr r2, [r7, #20]
800a5ba: 621a str r2, [r3, #32]
}
800a5bc: bf00 nop
800a5be: 371c adds r7, #28
800a5c0: 46bd mov sp, r7
800a5c2: f85d 7b04 ldr.w r7, [sp], #4
800a5c6: 4770 bx lr
800a5c8: fffeff8f .word 0xfffeff8f
800a5cc: 40010000 .word 0x40010000
800a5d0: 40010400 .word 0x40010400
0800a5d4 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a5d4: b480 push {r7}
800a5d6: b087 sub sp, #28
800a5d8: af00 add r7, sp, #0
800a5da: 6078 str r0, [r7, #4]
800a5dc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800a5de: 687b ldr r3, [r7, #4]
800a5e0: 6a1b ldr r3, [r3, #32]
800a5e2: f023 0210 bic.w r2, r3, #16
800a5e6: 687b ldr r3, [r7, #4]
800a5e8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a5ea: 687b ldr r3, [r7, #4]
800a5ec: 6a1b ldr r3, [r3, #32]
800a5ee: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a5f0: 687b ldr r3, [r7, #4]
800a5f2: 685b ldr r3, [r3, #4]
800a5f4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a5f6: 687b ldr r3, [r7, #4]
800a5f8: 699b ldr r3, [r3, #24]
800a5fa: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800a5fc: 68fa ldr r2, [r7, #12]
800a5fe: 4b2e ldr r3, [pc, #184] ; (800a6b8 <TIM_OC2_SetConfig+0xe4>)
800a600: 4013 ands r3, r2
800a602: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800a604: 68fb ldr r3, [r7, #12]
800a606: f423 7340 bic.w r3, r3, #768 ; 0x300
800a60a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a60c: 683b ldr r3, [r7, #0]
800a60e: 681b ldr r3, [r3, #0]
800a610: 021b lsls r3, r3, #8
800a612: 68fa ldr r2, [r7, #12]
800a614: 4313 orrs r3, r2
800a616: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800a618: 697b ldr r3, [r7, #20]
800a61a: f023 0320 bic.w r3, r3, #32
800a61e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800a620: 683b ldr r3, [r7, #0]
800a622: 689b ldr r3, [r3, #8]
800a624: 011b lsls r3, r3, #4
800a626: 697a ldr r2, [r7, #20]
800a628: 4313 orrs r3, r2
800a62a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800a62c: 687b ldr r3, [r7, #4]
800a62e: 4a23 ldr r2, [pc, #140] ; (800a6bc <TIM_OC2_SetConfig+0xe8>)
800a630: 4293 cmp r3, r2
800a632: d003 beq.n 800a63c <TIM_OC2_SetConfig+0x68>
800a634: 687b ldr r3, [r7, #4]
800a636: 4a22 ldr r2, [pc, #136] ; (800a6c0 <TIM_OC2_SetConfig+0xec>)
800a638: 4293 cmp r3, r2
800a63a: d10d bne.n 800a658 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800a63c: 697b ldr r3, [r7, #20]
800a63e: f023 0380 bic.w r3, r3, #128 ; 0x80
800a642: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800a644: 683b ldr r3, [r7, #0]
800a646: 68db ldr r3, [r3, #12]
800a648: 011b lsls r3, r3, #4
800a64a: 697a ldr r2, [r7, #20]
800a64c: 4313 orrs r3, r2
800a64e: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800a650: 697b ldr r3, [r7, #20]
800a652: f023 0340 bic.w r3, r3, #64 ; 0x40
800a656: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a658: 687b ldr r3, [r7, #4]
800a65a: 4a18 ldr r2, [pc, #96] ; (800a6bc <TIM_OC2_SetConfig+0xe8>)
800a65c: 4293 cmp r3, r2
800a65e: d003 beq.n 800a668 <TIM_OC2_SetConfig+0x94>
800a660: 687b ldr r3, [r7, #4]
800a662: 4a17 ldr r2, [pc, #92] ; (800a6c0 <TIM_OC2_SetConfig+0xec>)
800a664: 4293 cmp r3, r2
800a666: d113 bne.n 800a690 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800a668: 693b ldr r3, [r7, #16]
800a66a: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a66e: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800a670: 693b ldr r3, [r7, #16]
800a672: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a676: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800a678: 683b ldr r3, [r7, #0]
800a67a: 695b ldr r3, [r3, #20]
800a67c: 009b lsls r3, r3, #2
800a67e: 693a ldr r2, [r7, #16]
800a680: 4313 orrs r3, r2
800a682: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800a684: 683b ldr r3, [r7, #0]
800a686: 699b ldr r3, [r3, #24]
800a688: 009b lsls r3, r3, #2
800a68a: 693a ldr r2, [r7, #16]
800a68c: 4313 orrs r3, r2
800a68e: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a690: 687b ldr r3, [r7, #4]
800a692: 693a ldr r2, [r7, #16]
800a694: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a696: 687b ldr r3, [r7, #4]
800a698: 68fa ldr r2, [r7, #12]
800a69a: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800a69c: 683b ldr r3, [r7, #0]
800a69e: 685a ldr r2, [r3, #4]
800a6a0: 687b ldr r3, [r7, #4]
800a6a2: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a6a4: 687b ldr r3, [r7, #4]
800a6a6: 697a ldr r2, [r7, #20]
800a6a8: 621a str r2, [r3, #32]
}
800a6aa: bf00 nop
800a6ac: 371c adds r7, #28
800a6ae: 46bd mov sp, r7
800a6b0: f85d 7b04 ldr.w r7, [sp], #4
800a6b4: 4770 bx lr
800a6b6: bf00 nop
800a6b8: feff8fff .word 0xfeff8fff
800a6bc: 40010000 .word 0x40010000
800a6c0: 40010400 .word 0x40010400
0800a6c4 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a6c4: b480 push {r7}
800a6c6: b087 sub sp, #28
800a6c8: af00 add r7, sp, #0
800a6ca: 6078 str r0, [r7, #4]
800a6cc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800a6ce: 687b ldr r3, [r7, #4]
800a6d0: 6a1b ldr r3, [r3, #32]
800a6d2: f423 7280 bic.w r2, r3, #256 ; 0x100
800a6d6: 687b ldr r3, [r7, #4]
800a6d8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a6da: 687b ldr r3, [r7, #4]
800a6dc: 6a1b ldr r3, [r3, #32]
800a6de: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a6e0: 687b ldr r3, [r7, #4]
800a6e2: 685b ldr r3, [r3, #4]
800a6e4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a6e6: 687b ldr r3, [r7, #4]
800a6e8: 69db ldr r3, [r3, #28]
800a6ea: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800a6ec: 68fa ldr r2, [r7, #12]
800a6ee: 4b2d ldr r3, [pc, #180] ; (800a7a4 <TIM_OC3_SetConfig+0xe0>)
800a6f0: 4013 ands r3, r2
800a6f2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800a6f4: 68fb ldr r3, [r7, #12]
800a6f6: f023 0303 bic.w r3, r3, #3
800a6fa: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a6fc: 683b ldr r3, [r7, #0]
800a6fe: 681b ldr r3, [r3, #0]
800a700: 68fa ldr r2, [r7, #12]
800a702: 4313 orrs r3, r2
800a704: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800a706: 697b ldr r3, [r7, #20]
800a708: f423 7300 bic.w r3, r3, #512 ; 0x200
800a70c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
800a70e: 683b ldr r3, [r7, #0]
800a710: 689b ldr r3, [r3, #8]
800a712: 021b lsls r3, r3, #8
800a714: 697a ldr r2, [r7, #20]
800a716: 4313 orrs r3, r2
800a718: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800a71a: 687b ldr r3, [r7, #4]
800a71c: 4a22 ldr r2, [pc, #136] ; (800a7a8 <TIM_OC3_SetConfig+0xe4>)
800a71e: 4293 cmp r3, r2
800a720: d003 beq.n 800a72a <TIM_OC3_SetConfig+0x66>
800a722: 687b ldr r3, [r7, #4]
800a724: 4a21 ldr r2, [pc, #132] ; (800a7ac <TIM_OC3_SetConfig+0xe8>)
800a726: 4293 cmp r3, r2
800a728: d10d bne.n 800a746 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800a72a: 697b ldr r3, [r7, #20]
800a72c: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a730: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800a732: 683b ldr r3, [r7, #0]
800a734: 68db ldr r3, [r3, #12]
800a736: 021b lsls r3, r3, #8
800a738: 697a ldr r2, [r7, #20]
800a73a: 4313 orrs r3, r2
800a73c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800a73e: 697b ldr r3, [r7, #20]
800a740: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a744: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a746: 687b ldr r3, [r7, #4]
800a748: 4a17 ldr r2, [pc, #92] ; (800a7a8 <TIM_OC3_SetConfig+0xe4>)
800a74a: 4293 cmp r3, r2
800a74c: d003 beq.n 800a756 <TIM_OC3_SetConfig+0x92>
800a74e: 687b ldr r3, [r7, #4]
800a750: 4a16 ldr r2, [pc, #88] ; (800a7ac <TIM_OC3_SetConfig+0xe8>)
800a752: 4293 cmp r3, r2
800a754: d113 bne.n 800a77e <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800a756: 693b ldr r3, [r7, #16]
800a758: f423 5380 bic.w r3, r3, #4096 ; 0x1000
800a75c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800a75e: 693b ldr r3, [r7, #16]
800a760: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a764: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800a766: 683b ldr r3, [r7, #0]
800a768: 695b ldr r3, [r3, #20]
800a76a: 011b lsls r3, r3, #4
800a76c: 693a ldr r2, [r7, #16]
800a76e: 4313 orrs r3, r2
800a770: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800a772: 683b ldr r3, [r7, #0]
800a774: 699b ldr r3, [r3, #24]
800a776: 011b lsls r3, r3, #4
800a778: 693a ldr r2, [r7, #16]
800a77a: 4313 orrs r3, r2
800a77c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a77e: 687b ldr r3, [r7, #4]
800a780: 693a ldr r2, [r7, #16]
800a782: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a784: 687b ldr r3, [r7, #4]
800a786: 68fa ldr r2, [r7, #12]
800a788: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800a78a: 683b ldr r3, [r7, #0]
800a78c: 685a ldr r2, [r3, #4]
800a78e: 687b ldr r3, [r7, #4]
800a790: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a792: 687b ldr r3, [r7, #4]
800a794: 697a ldr r2, [r7, #20]
800a796: 621a str r2, [r3, #32]
}
800a798: bf00 nop
800a79a: 371c adds r7, #28
800a79c: 46bd mov sp, r7
800a79e: f85d 7b04 ldr.w r7, [sp], #4
800a7a2: 4770 bx lr
800a7a4: fffeff8f .word 0xfffeff8f
800a7a8: 40010000 .word 0x40010000
800a7ac: 40010400 .word 0x40010400
0800a7b0 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a7b0: b480 push {r7}
800a7b2: b087 sub sp, #28
800a7b4: af00 add r7, sp, #0
800a7b6: 6078 str r0, [r7, #4]
800a7b8: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800a7ba: 687b ldr r3, [r7, #4]
800a7bc: 6a1b ldr r3, [r3, #32]
800a7be: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800a7c2: 687b ldr r3, [r7, #4]
800a7c4: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a7c6: 687b ldr r3, [r7, #4]
800a7c8: 6a1b ldr r3, [r3, #32]
800a7ca: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a7cc: 687b ldr r3, [r7, #4]
800a7ce: 685b ldr r3, [r3, #4]
800a7d0: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a7d2: 687b ldr r3, [r7, #4]
800a7d4: 69db ldr r3, [r3, #28]
800a7d6: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800a7d8: 68fa ldr r2, [r7, #12]
800a7da: 4b1e ldr r3, [pc, #120] ; (800a854 <TIM_OC4_SetConfig+0xa4>)
800a7dc: 4013 ands r3, r2
800a7de: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800a7e0: 68fb ldr r3, [r7, #12]
800a7e2: f423 7340 bic.w r3, r3, #768 ; 0x300
800a7e6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a7e8: 683b ldr r3, [r7, #0]
800a7ea: 681b ldr r3, [r3, #0]
800a7ec: 021b lsls r3, r3, #8
800a7ee: 68fa ldr r2, [r7, #12]
800a7f0: 4313 orrs r3, r2
800a7f2: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800a7f4: 693b ldr r3, [r7, #16]
800a7f6: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a7fa: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800a7fc: 683b ldr r3, [r7, #0]
800a7fe: 689b ldr r3, [r3, #8]
800a800: 031b lsls r3, r3, #12
800a802: 693a ldr r2, [r7, #16]
800a804: 4313 orrs r3, r2
800a806: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a808: 687b ldr r3, [r7, #4]
800a80a: 4a13 ldr r2, [pc, #76] ; (800a858 <TIM_OC4_SetConfig+0xa8>)
800a80c: 4293 cmp r3, r2
800a80e: d003 beq.n 800a818 <TIM_OC4_SetConfig+0x68>
800a810: 687b ldr r3, [r7, #4]
800a812: 4a12 ldr r2, [pc, #72] ; (800a85c <TIM_OC4_SetConfig+0xac>)
800a814: 4293 cmp r3, r2
800a816: d109 bne.n 800a82c <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800a818: 697b ldr r3, [r7, #20]
800a81a: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800a81e: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800a820: 683b ldr r3, [r7, #0]
800a822: 695b ldr r3, [r3, #20]
800a824: 019b lsls r3, r3, #6
800a826: 697a ldr r2, [r7, #20]
800a828: 4313 orrs r3, r2
800a82a: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a82c: 687b ldr r3, [r7, #4]
800a82e: 697a ldr r2, [r7, #20]
800a830: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a832: 687b ldr r3, [r7, #4]
800a834: 68fa ldr r2, [r7, #12]
800a836: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800a838: 683b ldr r3, [r7, #0]
800a83a: 685a ldr r2, [r3, #4]
800a83c: 687b ldr r3, [r7, #4]
800a83e: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a840: 687b ldr r3, [r7, #4]
800a842: 693a ldr r2, [r7, #16]
800a844: 621a str r2, [r3, #32]
}
800a846: bf00 nop
800a848: 371c adds r7, #28
800a84a: 46bd mov sp, r7
800a84c: f85d 7b04 ldr.w r7, [sp], #4
800a850: 4770 bx lr
800a852: bf00 nop
800a854: feff8fff .word 0xfeff8fff
800a858: 40010000 .word 0x40010000
800a85c: 40010400 .word 0x40010400
0800a860 <TIM_OC5_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a860: b480 push {r7}
800a862: b087 sub sp, #28
800a864: af00 add r7, sp, #0
800a866: 6078 str r0, [r7, #4]
800a868: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800a86a: 687b ldr r3, [r7, #4]
800a86c: 6a1b ldr r3, [r3, #32]
800a86e: f423 3280 bic.w r2, r3, #65536 ; 0x10000
800a872: 687b ldr r3, [r7, #4]
800a874: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a876: 687b ldr r3, [r7, #4]
800a878: 6a1b ldr r3, [r3, #32]
800a87a: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a87c: 687b ldr r3, [r7, #4]
800a87e: 685b ldr r3, [r3, #4]
800a880: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a882: 687b ldr r3, [r7, #4]
800a884: 6d5b ldr r3, [r3, #84] ; 0x54
800a886: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800a888: 68fa ldr r2, [r7, #12]
800a88a: 4b1b ldr r3, [pc, #108] ; (800a8f8 <TIM_OC5_SetConfig+0x98>)
800a88c: 4013 ands r3, r2
800a88e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a890: 683b ldr r3, [r7, #0]
800a892: 681b ldr r3, [r3, #0]
800a894: 68fa ldr r2, [r7, #12]
800a896: 4313 orrs r3, r2
800a898: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800a89a: 693b ldr r3, [r7, #16]
800a89c: f423 3300 bic.w r3, r3, #131072 ; 0x20000
800a8a0: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800a8a2: 683b ldr r3, [r7, #0]
800a8a4: 689b ldr r3, [r3, #8]
800a8a6: 041b lsls r3, r3, #16
800a8a8: 693a ldr r2, [r7, #16]
800a8aa: 4313 orrs r3, r2
800a8ac: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a8ae: 687b ldr r3, [r7, #4]
800a8b0: 4a12 ldr r2, [pc, #72] ; (800a8fc <TIM_OC5_SetConfig+0x9c>)
800a8b2: 4293 cmp r3, r2
800a8b4: d003 beq.n 800a8be <TIM_OC5_SetConfig+0x5e>
800a8b6: 687b ldr r3, [r7, #4]
800a8b8: 4a11 ldr r2, [pc, #68] ; (800a900 <TIM_OC5_SetConfig+0xa0>)
800a8ba: 4293 cmp r3, r2
800a8bc: d109 bne.n 800a8d2 <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800a8be: 697b ldr r3, [r7, #20]
800a8c0: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800a8c4: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800a8c6: 683b ldr r3, [r7, #0]
800a8c8: 695b ldr r3, [r3, #20]
800a8ca: 021b lsls r3, r3, #8
800a8cc: 697a ldr r2, [r7, #20]
800a8ce: 4313 orrs r3, r2
800a8d0: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a8d2: 687b ldr r3, [r7, #4]
800a8d4: 697a ldr r2, [r7, #20]
800a8d6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a8d8: 687b ldr r3, [r7, #4]
800a8da: 68fa ldr r2, [r7, #12]
800a8dc: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800a8de: 683b ldr r3, [r7, #0]
800a8e0: 685a ldr r2, [r3, #4]
800a8e2: 687b ldr r3, [r7, #4]
800a8e4: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a8e6: 687b ldr r3, [r7, #4]
800a8e8: 693a ldr r2, [r7, #16]
800a8ea: 621a str r2, [r3, #32]
}
800a8ec: bf00 nop
800a8ee: 371c adds r7, #28
800a8f0: 46bd mov sp, r7
800a8f2: f85d 7b04 ldr.w r7, [sp], #4
800a8f6: 4770 bx lr
800a8f8: fffeff8f .word 0xfffeff8f
800a8fc: 40010000 .word 0x40010000
800a900: 40010400 .word 0x40010400
0800a904 <TIM_OC6_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a904: b480 push {r7}
800a906: b087 sub sp, #28
800a908: af00 add r7, sp, #0
800a90a: 6078 str r0, [r7, #4]
800a90c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
800a90e: 687b ldr r3, [r7, #4]
800a910: 6a1b ldr r3, [r3, #32]
800a912: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
800a916: 687b ldr r3, [r7, #4]
800a918: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a91a: 687b ldr r3, [r7, #4]
800a91c: 6a1b ldr r3, [r3, #32]
800a91e: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a920: 687b ldr r3, [r7, #4]
800a922: 685b ldr r3, [r3, #4]
800a924: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a926: 687b ldr r3, [r7, #4]
800a928: 6d5b ldr r3, [r3, #84] ; 0x54
800a92a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
800a92c: 68fa ldr r2, [r7, #12]
800a92e: 4b1c ldr r3, [pc, #112] ; (800a9a0 <TIM_OC6_SetConfig+0x9c>)
800a930: 4013 ands r3, r2
800a932: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a934: 683b ldr r3, [r7, #0]
800a936: 681b ldr r3, [r3, #0]
800a938: 021b lsls r3, r3, #8
800a93a: 68fa ldr r2, [r7, #12]
800a93c: 4313 orrs r3, r2
800a93e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
800a940: 693b ldr r3, [r7, #16]
800a942: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
800a946: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
800a948: 683b ldr r3, [r7, #0]
800a94a: 689b ldr r3, [r3, #8]
800a94c: 051b lsls r3, r3, #20
800a94e: 693a ldr r2, [r7, #16]
800a950: 4313 orrs r3, r2
800a952: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a954: 687b ldr r3, [r7, #4]
800a956: 4a13 ldr r2, [pc, #76] ; (800a9a4 <TIM_OC6_SetConfig+0xa0>)
800a958: 4293 cmp r3, r2
800a95a: d003 beq.n 800a964 <TIM_OC6_SetConfig+0x60>
800a95c: 687b ldr r3, [r7, #4]
800a95e: 4a12 ldr r2, [pc, #72] ; (800a9a8 <TIM_OC6_SetConfig+0xa4>)
800a960: 4293 cmp r3, r2
800a962: d109 bne.n 800a978 <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800a964: 697b ldr r3, [r7, #20]
800a966: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800a96a: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
800a96c: 683b ldr r3, [r7, #0]
800a96e: 695b ldr r3, [r3, #20]
800a970: 029b lsls r3, r3, #10
800a972: 697a ldr r2, [r7, #20]
800a974: 4313 orrs r3, r2
800a976: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a978: 687b ldr r3, [r7, #4]
800a97a: 697a ldr r2, [r7, #20]
800a97c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a97e: 687b ldr r3, [r7, #4]
800a980: 68fa ldr r2, [r7, #12]
800a982: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800a984: 683b ldr r3, [r7, #0]
800a986: 685a ldr r2, [r3, #4]
800a988: 687b ldr r3, [r7, #4]
800a98a: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a98c: 687b ldr r3, [r7, #4]
800a98e: 693a ldr r2, [r7, #16]
800a990: 621a str r2, [r3, #32]
}
800a992: bf00 nop
800a994: 371c adds r7, #28
800a996: 46bd mov sp, r7
800a998: f85d 7b04 ldr.w r7, [sp], #4
800a99c: 4770 bx lr
800a99e: bf00 nop
800a9a0: feff8fff .word 0xfeff8fff
800a9a4: 40010000 .word 0x40010000
800a9a8: 40010400 .word 0x40010400
0800a9ac <TIM_SlaveTimer_SetConfig>:
* @param sSlaveConfig Slave timer configuration
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a9ac: b580 push {r7, lr}
800a9ae: b086 sub sp, #24
800a9b0: af00 add r7, sp, #0
800a9b2: 6078 str r0, [r7, #4]
800a9b4: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800a9b6: 687b ldr r3, [r7, #4]
800a9b8: 681b ldr r3, [r3, #0]
800a9ba: 689b ldr r3, [r3, #8]
800a9bc: 617b str r3, [r7, #20]
/* Reset the Trigger Selection Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800a9be: 697b ldr r3, [r7, #20]
800a9c0: f023 0370 bic.w r3, r3, #112 ; 0x70
800a9c4: 617b str r3, [r7, #20]
/* Set the Input Trigger source */
tmpsmcr |= sSlaveConfig->InputTrigger;
800a9c6: 683b ldr r3, [r7, #0]
800a9c8: 685b ldr r3, [r3, #4]
800a9ca: 697a ldr r2, [r7, #20]
800a9cc: 4313 orrs r3, r2
800a9ce: 617b str r3, [r7, #20]
/* Reset the slave mode Bits */
tmpsmcr &= ~TIM_SMCR_SMS;
800a9d0: 697a ldr r2, [r7, #20]
800a9d2: 4b39 ldr r3, [pc, #228] ; (800aab8 <TIM_SlaveTimer_SetConfig+0x10c>)
800a9d4: 4013 ands r3, r2
800a9d6: 617b str r3, [r7, #20]
/* Set the slave mode */
tmpsmcr |= sSlaveConfig->SlaveMode;
800a9d8: 683b ldr r3, [r7, #0]
800a9da: 681b ldr r3, [r3, #0]
800a9dc: 697a ldr r2, [r7, #20]
800a9de: 4313 orrs r3, r2
800a9e0: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800a9e2: 687b ldr r3, [r7, #4]
800a9e4: 681b ldr r3, [r3, #0]
800a9e6: 697a ldr r2, [r7, #20]
800a9e8: 609a str r2, [r3, #8]
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
800a9ea: 683b ldr r3, [r7, #0]
800a9ec: 685b ldr r3, [r3, #4]
800a9ee: 2b30 cmp r3, #48 ; 0x30
800a9f0: d05c beq.n 800aaac <TIM_SlaveTimer_SetConfig+0x100>
800a9f2: 2b30 cmp r3, #48 ; 0x30
800a9f4: d806 bhi.n 800aa04 <TIM_SlaveTimer_SetConfig+0x58>
800a9f6: 2b10 cmp r3, #16
800a9f8: d058 beq.n 800aaac <TIM_SlaveTimer_SetConfig+0x100>
800a9fa: 2b20 cmp r3, #32
800a9fc: d056 beq.n 800aaac <TIM_SlaveTimer_SetConfig+0x100>
800a9fe: 2b00 cmp r3, #0
800aa00: d054 beq.n 800aaac <TIM_SlaveTimer_SetConfig+0x100>
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
break;
}
default:
break;
800aa02: e054 b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
800aa04: 2b50 cmp r3, #80 ; 0x50
800aa06: d03d beq.n 800aa84 <TIM_SlaveTimer_SetConfig+0xd8>
800aa08: 2b50 cmp r3, #80 ; 0x50
800aa0a: d802 bhi.n 800aa12 <TIM_SlaveTimer_SetConfig+0x66>
800aa0c: 2b40 cmp r3, #64 ; 0x40
800aa0e: d010 beq.n 800aa32 <TIM_SlaveTimer_SetConfig+0x86>
break;
800aa10: e04d b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
800aa12: 2b60 cmp r3, #96 ; 0x60
800aa14: d040 beq.n 800aa98 <TIM_SlaveTimer_SetConfig+0xec>
800aa16: 2b70 cmp r3, #112 ; 0x70
800aa18: d000 beq.n 800aa1c <TIM_SlaveTimer_SetConfig+0x70>
break;
800aa1a: e048 b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
TIM_ETR_SetConfig(htim->Instance,
800aa1c: 687b ldr r3, [r7, #4]
800aa1e: 6818 ldr r0, [r3, #0]
800aa20: 683b ldr r3, [r7, #0]
800aa22: 68d9 ldr r1, [r3, #12]
800aa24: 683b ldr r3, [r7, #0]
800aa26: 689a ldr r2, [r3, #8]
800aa28: 683b ldr r3, [r7, #0]
800aa2a: 691b ldr r3, [r3, #16]
800aa2c: f000 f8c0 bl 800abb0 <TIM_ETR_SetConfig>
break;
800aa30: e03d b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
800aa32: 683b ldr r3, [r7, #0]
800aa34: 681b ldr r3, [r3, #0]
800aa36: 2b05 cmp r3, #5
800aa38: d101 bne.n 800aa3e <TIM_SlaveTimer_SetConfig+0x92>
return HAL_ERROR;
800aa3a: 2301 movs r3, #1
800aa3c: e038 b.n 800aab0 <TIM_SlaveTimer_SetConfig+0x104>
tmpccer = htim->Instance->CCER;
800aa3e: 687b ldr r3, [r7, #4]
800aa40: 681b ldr r3, [r3, #0]
800aa42: 6a1b ldr r3, [r3, #32]
800aa44: 613b str r3, [r7, #16]
htim->Instance->CCER &= ~TIM_CCER_CC1E;
800aa46: 687b ldr r3, [r7, #4]
800aa48: 681b ldr r3, [r3, #0]
800aa4a: 6a1a ldr r2, [r3, #32]
800aa4c: 687b ldr r3, [r7, #4]
800aa4e: 681b ldr r3, [r3, #0]
800aa50: f022 0201 bic.w r2, r2, #1
800aa54: 621a str r2, [r3, #32]
tmpccmr1 = htim->Instance->CCMR1;
800aa56: 687b ldr r3, [r7, #4]
800aa58: 681b ldr r3, [r3, #0]
800aa5a: 699b ldr r3, [r3, #24]
800aa5c: 60fb str r3, [r7, #12]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800aa5e: 68fb ldr r3, [r7, #12]
800aa60: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800aa64: 60fb str r3, [r7, #12]
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
800aa66: 683b ldr r3, [r7, #0]
800aa68: 691b ldr r3, [r3, #16]
800aa6a: 011b lsls r3, r3, #4
800aa6c: 68fa ldr r2, [r7, #12]
800aa6e: 4313 orrs r3, r2
800aa70: 60fb str r3, [r7, #12]
htim->Instance->CCMR1 = tmpccmr1;
800aa72: 687b ldr r3, [r7, #4]
800aa74: 681b ldr r3, [r3, #0]
800aa76: 68fa ldr r2, [r7, #12]
800aa78: 619a str r2, [r3, #24]
htim->Instance->CCER = tmpccer;
800aa7a: 687b ldr r3, [r7, #4]
800aa7c: 681b ldr r3, [r3, #0]
800aa7e: 693a ldr r2, [r7, #16]
800aa80: 621a str r2, [r3, #32]
break;
800aa82: e014 b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI1_ConfigInputStage(htim->Instance,
800aa84: 687b ldr r3, [r7, #4]
800aa86: 6818 ldr r0, [r3, #0]
800aa88: 683b ldr r3, [r7, #0]
800aa8a: 6899 ldr r1, [r3, #8]
800aa8c: 683b ldr r3, [r7, #0]
800aa8e: 691b ldr r3, [r3, #16]
800aa90: 461a mov r2, r3
800aa92: f000 f813 bl 800aabc <TIM_TI1_ConfigInputStage>
break;
800aa96: e00a b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI2_ConfigInputStage(htim->Instance,
800aa98: 687b ldr r3, [r7, #4]
800aa9a: 6818 ldr r0, [r3, #0]
800aa9c: 683b ldr r3, [r7, #0]
800aa9e: 6899 ldr r1, [r3, #8]
800aaa0: 683b ldr r3, [r7, #0]
800aaa2: 691b ldr r3, [r3, #16]
800aaa4: 461a mov r2, r3
800aaa6: f000 f838 bl 800ab1a <TIM_TI2_ConfigInputStage>
break;
800aaaa: e000 b.n 800aaae <TIM_SlaveTimer_SetConfig+0x102>
break;
800aaac: bf00 nop
}
return HAL_OK;
800aaae: 2300 movs r3, #0
}
800aab0: 4618 mov r0, r3
800aab2: 3718 adds r7, #24
800aab4: 46bd mov sp, r7
800aab6: bd80 pop {r7, pc}
800aab8: fffefff8 .word 0xfffefff8
0800aabc <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800aabc: b480 push {r7}
800aabe: b087 sub sp, #28
800aac0: af00 add r7, sp, #0
800aac2: 60f8 str r0, [r7, #12]
800aac4: 60b9 str r1, [r7, #8]
800aac6: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
800aac8: 68fb ldr r3, [r7, #12]
800aaca: 6a1b ldr r3, [r3, #32]
800aacc: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800aace: 68fb ldr r3, [r7, #12]
800aad0: 6a1b ldr r3, [r3, #32]
800aad2: f023 0201 bic.w r2, r3, #1
800aad6: 68fb ldr r3, [r7, #12]
800aad8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800aada: 68fb ldr r3, [r7, #12]
800aadc: 699b ldr r3, [r3, #24]
800aade: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800aae0: 693b ldr r3, [r7, #16]
800aae2: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800aae6: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
800aae8: 687b ldr r3, [r7, #4]
800aaea: 011b lsls r3, r3, #4
800aaec: 693a ldr r2, [r7, #16]
800aaee: 4313 orrs r3, r2
800aaf0: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800aaf2: 697b ldr r3, [r7, #20]
800aaf4: f023 030a bic.w r3, r3, #10
800aaf8: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800aafa: 697a ldr r2, [r7, #20]
800aafc: 68bb ldr r3, [r7, #8]
800aafe: 4313 orrs r3, r2
800ab00: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800ab02: 68fb ldr r3, [r7, #12]
800ab04: 693a ldr r2, [r7, #16]
800ab06: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800ab08: 68fb ldr r3, [r7, #12]
800ab0a: 697a ldr r2, [r7, #20]
800ab0c: 621a str r2, [r3, #32]
}
800ab0e: bf00 nop
800ab10: 371c adds r7, #28
800ab12: 46bd mov sp, r7
800ab14: f85d 7b04 ldr.w r7, [sp], #4
800ab18: 4770 bx lr
0800ab1a <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800ab1a: b480 push {r7}
800ab1c: b087 sub sp, #28
800ab1e: af00 add r7, sp, #0
800ab20: 60f8 str r0, [r7, #12]
800ab22: 60b9 str r1, [r7, #8]
800ab24: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800ab26: 68fb ldr r3, [r7, #12]
800ab28: 6a1b ldr r3, [r3, #32]
800ab2a: f023 0210 bic.w r2, r3, #16
800ab2e: 68fb ldr r3, [r7, #12]
800ab30: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800ab32: 68fb ldr r3, [r7, #12]
800ab34: 699b ldr r3, [r3, #24]
800ab36: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
800ab38: 68fb ldr r3, [r7, #12]
800ab3a: 6a1b ldr r3, [r3, #32]
800ab3c: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800ab3e: 697b ldr r3, [r7, #20]
800ab40: f423 4370 bic.w r3, r3, #61440 ; 0xf000
800ab44: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
800ab46: 687b ldr r3, [r7, #4]
800ab48: 031b lsls r3, r3, #12
800ab4a: 697a ldr r2, [r7, #20]
800ab4c: 4313 orrs r3, r2
800ab4e: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800ab50: 693b ldr r3, [r7, #16]
800ab52: f023 03a0 bic.w r3, r3, #160 ; 0xa0
800ab56: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
800ab58: 68bb ldr r3, [r7, #8]
800ab5a: 011b lsls r3, r3, #4
800ab5c: 693a ldr r2, [r7, #16]
800ab5e: 4313 orrs r3, r2
800ab60: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800ab62: 68fb ldr r3, [r7, #12]
800ab64: 697a ldr r2, [r7, #20]
800ab66: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800ab68: 68fb ldr r3, [r7, #12]
800ab6a: 693a ldr r2, [r7, #16]
800ab6c: 621a str r2, [r3, #32]
}
800ab6e: bf00 nop
800ab70: 371c adds r7, #28
800ab72: 46bd mov sp, r7
800ab74: f85d 7b04 ldr.w r7, [sp], #4
800ab78: 4770 bx lr
0800ab7a <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
800ab7a: b480 push {r7}
800ab7c: b085 sub sp, #20
800ab7e: af00 add r7, sp, #0
800ab80: 6078 str r0, [r7, #4]
800ab82: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800ab84: 687b ldr r3, [r7, #4]
800ab86: 689b ldr r3, [r3, #8]
800ab88: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800ab8a: 68fb ldr r3, [r7, #12]
800ab8c: f023 0370 bic.w r3, r3, #112 ; 0x70
800ab90: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800ab92: 683a ldr r2, [r7, #0]
800ab94: 68fb ldr r3, [r7, #12]
800ab96: 4313 orrs r3, r2
800ab98: f043 0307 orr.w r3, r3, #7
800ab9c: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800ab9e: 687b ldr r3, [r7, #4]
800aba0: 68fa ldr r2, [r7, #12]
800aba2: 609a str r2, [r3, #8]
}
800aba4: bf00 nop
800aba6: 3714 adds r7, #20
800aba8: 46bd mov sp, r7
800abaa: f85d 7b04 ldr.w r7, [sp], #4
800abae: 4770 bx lr
0800abb0 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800abb0: b480 push {r7}
800abb2: b087 sub sp, #28
800abb4: af00 add r7, sp, #0
800abb6: 60f8 str r0, [r7, #12]
800abb8: 60b9 str r1, [r7, #8]
800abba: 607a str r2, [r7, #4]
800abbc: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800abbe: 68fb ldr r3, [r7, #12]
800abc0: 689b ldr r3, [r3, #8]
800abc2: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800abc4: 697b ldr r3, [r7, #20]
800abc6: f423 437f bic.w r3, r3, #65280 ; 0xff00
800abca: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
800abcc: 683b ldr r3, [r7, #0]
800abce: 021a lsls r2, r3, #8
800abd0: 687b ldr r3, [r7, #4]
800abd2: 431a orrs r2, r3
800abd4: 68bb ldr r3, [r7, #8]
800abd6: 4313 orrs r3, r2
800abd8: 697a ldr r2, [r7, #20]
800abda: 4313 orrs r3, r2
800abdc: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800abde: 68fb ldr r3, [r7, #12]
800abe0: 697a ldr r2, [r7, #20]
800abe2: 609a str r2, [r3, #8]
}
800abe4: bf00 nop
800abe6: 371c adds r7, #28
800abe8: 46bd mov sp, r7
800abea: f85d 7b04 ldr.w r7, [sp], #4
800abee: 4770 bx lr
0800abf0 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
800abf0: b480 push {r7}
800abf2: b085 sub sp, #20
800abf4: af00 add r7, sp, #0
800abf6: 6078 str r0, [r7, #4]
800abf8: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800abfa: 687b ldr r3, [r7, #4]
800abfc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ac00: 2b01 cmp r3, #1
800ac02: d101 bne.n 800ac08 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800ac04: 2302 movs r3, #2
800ac06: e06d b.n 800ace4 <HAL_TIMEx_MasterConfigSynchronization+0xf4>
800ac08: 687b ldr r3, [r7, #4]
800ac0a: 2201 movs r2, #1
800ac0c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800ac10: 687b ldr r3, [r7, #4]
800ac12: 2202 movs r2, #2
800ac14: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
800ac18: 687b ldr r3, [r7, #4]
800ac1a: 681b ldr r3, [r3, #0]
800ac1c: 685b ldr r3, [r3, #4]
800ac1e: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800ac20: 687b ldr r3, [r7, #4]
800ac22: 681b ldr r3, [r3, #0]
800ac24: 689b ldr r3, [r3, #8]
800ac26: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
800ac28: 687b ldr r3, [r7, #4]
800ac2a: 681b ldr r3, [r3, #0]
800ac2c: 4a30 ldr r2, [pc, #192] ; (800acf0 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ac2e: 4293 cmp r3, r2
800ac30: d004 beq.n 800ac3c <HAL_TIMEx_MasterConfigSynchronization+0x4c>
800ac32: 687b ldr r3, [r7, #4]
800ac34: 681b ldr r3, [r3, #0]
800ac36: 4a2f ldr r2, [pc, #188] ; (800acf4 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800ac38: 4293 cmp r3, r2
800ac3a: d108 bne.n 800ac4e <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800ac3c: 68fb ldr r3, [r7, #12]
800ac3e: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
800ac42: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800ac44: 683b ldr r3, [r7, #0]
800ac46: 685b ldr r3, [r3, #4]
800ac48: 68fa ldr r2, [r7, #12]
800ac4a: 4313 orrs r3, r2
800ac4c: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800ac4e: 68fb ldr r3, [r7, #12]
800ac50: f023 0370 bic.w r3, r3, #112 ; 0x70
800ac54: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800ac56: 683b ldr r3, [r7, #0]
800ac58: 681b ldr r3, [r3, #0]
800ac5a: 68fa ldr r2, [r7, #12]
800ac5c: 4313 orrs r3, r2
800ac5e: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800ac60: 687b ldr r3, [r7, #4]
800ac62: 681b ldr r3, [r3, #0]
800ac64: 68fa ldr r2, [r7, #12]
800ac66: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800ac68: 687b ldr r3, [r7, #4]
800ac6a: 681b ldr r3, [r3, #0]
800ac6c: 4a20 ldr r2, [pc, #128] ; (800acf0 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ac6e: 4293 cmp r3, r2
800ac70: d022 beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac72: 687b ldr r3, [r7, #4]
800ac74: 681b ldr r3, [r3, #0]
800ac76: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800ac7a: d01d beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac7c: 687b ldr r3, [r7, #4]
800ac7e: 681b ldr r3, [r3, #0]
800ac80: 4a1d ldr r2, [pc, #116] ; (800acf8 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
800ac82: 4293 cmp r3, r2
800ac84: d018 beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac86: 687b ldr r3, [r7, #4]
800ac88: 681b ldr r3, [r3, #0]
800ac8a: 4a1c ldr r2, [pc, #112] ; (800acfc <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
800ac8c: 4293 cmp r3, r2
800ac8e: d013 beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac90: 687b ldr r3, [r7, #4]
800ac92: 681b ldr r3, [r3, #0]
800ac94: 4a1a ldr r2, [pc, #104] ; (800ad00 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
800ac96: 4293 cmp r3, r2
800ac98: d00e beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac9a: 687b ldr r3, [r7, #4]
800ac9c: 681b ldr r3, [r3, #0]
800ac9e: 4a15 ldr r2, [pc, #84] ; (800acf4 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800aca0: 4293 cmp r3, r2
800aca2: d009 beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800aca4: 687b ldr r3, [r7, #4]
800aca6: 681b ldr r3, [r3, #0]
800aca8: 4a16 ldr r2, [pc, #88] ; (800ad04 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
800acaa: 4293 cmp r3, r2
800acac: d004 beq.n 800acb8 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800acae: 687b ldr r3, [r7, #4]
800acb0: 681b ldr r3, [r3, #0]
800acb2: 4a15 ldr r2, [pc, #84] ; (800ad08 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
800acb4: 4293 cmp r3, r2
800acb6: d10c bne.n 800acd2 <HAL_TIMEx_MasterConfigSynchronization+0xe2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800acb8: 68bb ldr r3, [r7, #8]
800acba: f023 0380 bic.w r3, r3, #128 ; 0x80
800acbe: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800acc0: 683b ldr r3, [r7, #0]
800acc2: 689b ldr r3, [r3, #8]
800acc4: 68ba ldr r2, [r7, #8]
800acc6: 4313 orrs r3, r2
800acc8: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800acca: 687b ldr r3, [r7, #4]
800accc: 681b ldr r3, [r3, #0]
800acce: 68ba ldr r2, [r7, #8]
800acd0: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800acd2: 687b ldr r3, [r7, #4]
800acd4: 2201 movs r2, #1
800acd6: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800acda: 687b ldr r3, [r7, #4]
800acdc: 2200 movs r2, #0
800acde: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800ace2: 2300 movs r3, #0
}
800ace4: 4618 mov r0, r3
800ace6: 3714 adds r7, #20
800ace8: 46bd mov sp, r7
800acea: f85d 7b04 ldr.w r7, [sp], #4
800acee: 4770 bx lr
800acf0: 40010000 .word 0x40010000
800acf4: 40010400 .word 0x40010400
800acf8: 40000400 .word 0x40000400
800acfc: 40000800 .word 0x40000800
800ad00: 40000c00 .word 0x40000c00
800ad04: 40014000 .word 0x40014000
800ad08: 40001800 .word 0x40001800
0800ad0c <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
800ad0c: b480 push {r7}
800ad0e: b085 sub sp, #20
800ad10: af00 add r7, sp, #0
800ad12: 6078 str r0, [r7, #4]
800ad14: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800ad16: 2300 movs r3, #0
800ad18: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
800ad1a: 687b ldr r3, [r7, #4]
800ad1c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ad20: 2b01 cmp r3, #1
800ad22: d101 bne.n 800ad28 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
800ad24: 2302 movs r3, #2
800ad26: e065 b.n 800adf4 <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
800ad28: 687b ldr r3, [r7, #4]
800ad2a: 2201 movs r2, #1
800ad2c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
800ad30: 68fb ldr r3, [r7, #12]
800ad32: f023 02ff bic.w r2, r3, #255 ; 0xff
800ad36: 683b ldr r3, [r7, #0]
800ad38: 68db ldr r3, [r3, #12]
800ad3a: 4313 orrs r3, r2
800ad3c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
800ad3e: 68fb ldr r3, [r7, #12]
800ad40: f423 7240 bic.w r2, r3, #768 ; 0x300
800ad44: 683b ldr r3, [r7, #0]
800ad46: 689b ldr r3, [r3, #8]
800ad48: 4313 orrs r3, r2
800ad4a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
800ad4c: 68fb ldr r3, [r7, #12]
800ad4e: f423 6280 bic.w r2, r3, #1024 ; 0x400
800ad52: 683b ldr r3, [r7, #0]
800ad54: 685b ldr r3, [r3, #4]
800ad56: 4313 orrs r3, r2
800ad58: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800ad5a: 68fb ldr r3, [r7, #12]
800ad5c: f423 6200 bic.w r2, r3, #2048 ; 0x800
800ad60: 683b ldr r3, [r7, #0]
800ad62: 681b ldr r3, [r3, #0]
800ad64: 4313 orrs r3, r2
800ad66: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
800ad68: 68fb ldr r3, [r7, #12]
800ad6a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800ad6e: 683b ldr r3, [r7, #0]
800ad70: 691b ldr r3, [r3, #16]
800ad72: 4313 orrs r3, r2
800ad74: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
800ad76: 68fb ldr r3, [r7, #12]
800ad78: f423 5200 bic.w r2, r3, #8192 ; 0x2000
800ad7c: 683b ldr r3, [r7, #0]
800ad7e: 695b ldr r3, [r3, #20]
800ad80: 4313 orrs r3, r2
800ad82: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
800ad84: 68fb ldr r3, [r7, #12]
800ad86: f423 4280 bic.w r2, r3, #16384 ; 0x4000
800ad8a: 683b ldr r3, [r7, #0]
800ad8c: 6a9b ldr r3, [r3, #40] ; 0x28
800ad8e: 4313 orrs r3, r2
800ad90: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
800ad92: 68fb ldr r3, [r7, #12]
800ad94: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
800ad98: 683b ldr r3, [r7, #0]
800ad9a: 699b ldr r3, [r3, #24]
800ad9c: 041b lsls r3, r3, #16
800ad9e: 4313 orrs r3, r2
800ada0: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
800ada2: 687b ldr r3, [r7, #4]
800ada4: 681b ldr r3, [r3, #0]
800ada6: 4a16 ldr r2, [pc, #88] ; (800ae00 <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
800ada8: 4293 cmp r3, r2
800adaa: d004 beq.n 800adb6 <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
800adac: 687b ldr r3, [r7, #4]
800adae: 681b ldr r3, [r3, #0]
800adb0: 4a14 ldr r2, [pc, #80] ; (800ae04 <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
800adb2: 4293 cmp r3, r2
800adb4: d115 bne.n 800ade2 <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
800adb6: 68fb ldr r3, [r7, #12]
800adb8: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
800adbc: 683b ldr r3, [r7, #0]
800adbe: 6a5b ldr r3, [r3, #36] ; 0x24
800adc0: 051b lsls r3, r3, #20
800adc2: 4313 orrs r3, r2
800adc4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
800adc6: 68fb ldr r3, [r7, #12]
800adc8: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
800adcc: 683b ldr r3, [r7, #0]
800adce: 69db ldr r3, [r3, #28]
800add0: 4313 orrs r3, r2
800add2: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
800add4: 68fb ldr r3, [r7, #12]
800add6: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
800adda: 683b ldr r3, [r7, #0]
800addc: 6a1b ldr r3, [r3, #32]
800adde: 4313 orrs r3, r2
800ade0: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
800ade2: 687b ldr r3, [r7, #4]
800ade4: 681b ldr r3, [r3, #0]
800ade6: 68fa ldr r2, [r7, #12]
800ade8: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
800adea: 687b ldr r3, [r7, #4]
800adec: 2200 movs r2, #0
800adee: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800adf2: 2300 movs r3, #0
}
800adf4: 4618 mov r0, r3
800adf6: 3714 adds r7, #20
800adf8: 46bd mov sp, r7
800adfa: f85d 7b04 ldr.w r7, [sp], #4
800adfe: 4770 bx lr
800ae00: 40010000 .word 0x40010000
800ae04: 40010400 .word 0x40010400
0800ae08 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800ae08: b480 push {r7}
800ae0a: b083 sub sp, #12
800ae0c: af00 add r7, sp, #0
800ae0e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800ae10: bf00 nop
800ae12: 370c adds r7, #12
800ae14: 46bd mov sp, r7
800ae16: f85d 7b04 ldr.w r7, [sp], #4
800ae1a: 4770 bx lr
0800ae1c <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800ae1c: b480 push {r7}
800ae1e: b083 sub sp, #12
800ae20: af00 add r7, sp, #0
800ae22: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800ae24: bf00 nop
800ae26: 370c adds r7, #12
800ae28: 46bd mov sp, r7
800ae2a: f85d 7b04 ldr.w r7, [sp], #4
800ae2e: 4770 bx lr
0800ae30 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800ae30: b480 push {r7}
800ae32: b083 sub sp, #12
800ae34: af00 add r7, sp, #0
800ae36: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
800ae38: bf00 nop
800ae3a: 370c adds r7, #12
800ae3c: 46bd mov sp, r7
800ae3e: f85d 7b04 ldr.w r7, [sp], #4
800ae42: 4770 bx lr
0800ae44 <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
800ae44: b480 push {r7}
800ae46: b085 sub sp, #20
800ae48: af00 add r7, sp, #0
800ae4a: 6078 str r0, [r7, #4]
800ae4c: 6039 str r1, [r7, #0]
uint32_t tmpr1 = 0;
800ae4e: 2300 movs r3, #0
800ae50: 60fb str r3, [r7, #12]
uint32_t tmpr2 = 0;
800ae52: 2300 movs r3, #0
800ae54: 60bb str r3, [r7, #8]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
800ae56: 683b ldr r3, [r7, #0]
800ae58: 681b ldr r3, [r3, #0]
800ae5a: 2b01 cmp r3, #1
800ae5c: d027 beq.n 800aeae <FMC_SDRAM_Init+0x6a>
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800ae5e: 687b ldr r3, [r7, #4]
800ae60: 681b ldr r3, [r3, #0]
800ae62: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800ae64: 68fa ldr r2, [r7, #12]
800ae66: 4b2f ldr r3, [pc, #188] ; (800af24 <FMC_SDRAM_Init+0xe0>)
800ae68: 4013 ands r3, r2
800ae6a: 60fb str r3, [r7, #12]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ae6c: 683b ldr r3, [r7, #0]
800ae6e: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800ae70: 683b ldr r3, [r7, #0]
800ae72: 689b ldr r3, [r3, #8]
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ae74: 431a orrs r2, r3
Init->MemoryDataWidth |\
800ae76: 683b ldr r3, [r7, #0]
800ae78: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800ae7a: 431a orrs r2, r3
Init->InternalBankNumber |\
800ae7c: 683b ldr r3, [r7, #0]
800ae7e: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800ae80: 431a orrs r2, r3
Init->CASLatency |\
800ae82: 683b ldr r3, [r7, #0]
800ae84: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800ae86: 431a orrs r2, r3
Init->WriteProtection |\
800ae88: 683b ldr r3, [r7, #0]
800ae8a: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800ae8c: 431a orrs r2, r3
Init->SDClockPeriod |\
800ae8e: 683b ldr r3, [r7, #0]
800ae90: 69db ldr r3, [r3, #28]
Init->WriteProtection |\
800ae92: 431a orrs r2, r3
Init->ReadBurst |\
800ae94: 683b ldr r3, [r7, #0]
800ae96: 6a1b ldr r3, [r3, #32]
Init->SDClockPeriod |\
800ae98: 431a orrs r2, r3
Init->ReadPipeDelay
800ae9a: 683b ldr r3, [r7, #0]
800ae9c: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800ae9e: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800aea0: 68fa ldr r2, [r7, #12]
800aea2: 4313 orrs r3, r2
800aea4: 60fb str r3, [r7, #12]
);
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800aea6: 687b ldr r3, [r7, #4]
800aea8: 68fa ldr r2, [r7, #12]
800aeaa: 601a str r2, [r3, #0]
800aeac: e032 b.n 800af14 <FMC_SDRAM_Init+0xd0>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800aeae: 687b ldr r3, [r7, #4]
800aeb0: 681b ldr r3, [r3, #0]
800aeb2: 60fb str r3, [r7, #12]
/* Clear SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
800aeb4: 68fb ldr r3, [r7, #12]
800aeb6: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
800aeba: 60fb str r3, [r7, #12]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aebc: 683b ldr r3, [r7, #0]
800aebe: 69da ldr r2, [r3, #28]
Init->ReadBurst |\
800aec0: 683b ldr r3, [r7, #0]
800aec2: 6a1b ldr r3, [r3, #32]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aec4: 431a orrs r2, r3
Init->ReadPipeDelay);
800aec6: 683b ldr r3, [r7, #0]
800aec8: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800aeca: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aecc: 68fa ldr r2, [r7, #12]
800aece: 4313 orrs r3, r2
800aed0: 60fb str r3, [r7, #12]
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
800aed2: 687b ldr r3, [r7, #4]
800aed4: 685b ldr r3, [r3, #4]
800aed6: 60bb str r3, [r7, #8]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800aed8: 68ba ldr r2, [r7, #8]
800aeda: 4b12 ldr r3, [pc, #72] ; (800af24 <FMC_SDRAM_Init+0xe0>)
800aedc: 4013 ands r3, r2
800aede: 60bb str r3, [r7, #8]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800aee0: 683b ldr r3, [r7, #0]
800aee2: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800aee4: 683b ldr r3, [r7, #0]
800aee6: 689b ldr r3, [r3, #8]
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800aee8: 431a orrs r2, r3
Init->MemoryDataWidth |\
800aeea: 683b ldr r3, [r7, #0]
800aeec: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800aeee: 431a orrs r2, r3
Init->InternalBankNumber |\
800aef0: 683b ldr r3, [r7, #0]
800aef2: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800aef4: 431a orrs r2, r3
Init->CASLatency |\
800aef6: 683b ldr r3, [r7, #0]
800aef8: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800aefa: 431a orrs r2, r3
Init->WriteProtection);
800aefc: 683b ldr r3, [r7, #0]
800aefe: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800af00: 4313 orrs r3, r2
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800af02: 68ba ldr r2, [r7, #8]
800af04: 4313 orrs r3, r2
800af06: 60bb str r3, [r7, #8]
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800af08: 687b ldr r3, [r7, #4]
800af0a: 68fa ldr r2, [r7, #12]
800af0c: 601a str r2, [r3, #0]
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
800af0e: 687b ldr r3, [r7, #4]
800af10: 68ba ldr r2, [r7, #8]
800af12: 605a str r2, [r3, #4]
}
return HAL_OK;
800af14: 2300 movs r3, #0
}
800af16: 4618 mov r0, r3
800af18: 3714 adds r7, #20
800af1a: 46bd mov sp, r7
800af1c: f85d 7b04 ldr.w r7, [sp], #4
800af20: 4770 bx lr
800af22: bf00 nop
800af24: ffff8000 .word 0xffff8000
0800af28 <FMC_SDRAM_Timing_Init>:
* @param Timing Pointer to SDRAM Timing structure
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
800af28: b480 push {r7}
800af2a: b087 sub sp, #28
800af2c: af00 add r7, sp, #0
800af2e: 60f8 str r0, [r7, #12]
800af30: 60b9 str r1, [r7, #8]
800af32: 607a str r2, [r7, #4]
uint32_t tmpr1 = 0;
800af34: 2300 movs r3, #0
800af36: 617b str r3, [r7, #20]
uint32_t tmpr2 = 0;
800af38: 2300 movs r3, #0
800af3a: 613b str r3, [r7, #16]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
800af3c: 687b ldr r3, [r7, #4]
800af3e: 2b01 cmp r3, #1
800af40: d02e beq.n 800afa0 <FMC_SDRAM_Timing_Init+0x78>
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800af42: 68fb ldr r3, [r7, #12]
800af44: 689b ldr r3, [r3, #8]
800af46: 617b str r3, [r7, #20]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800af48: 697b ldr r3, [r7, #20]
800af4a: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800af4e: 617b str r3, [r7, #20]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af50: 68bb ldr r3, [r7, #8]
800af52: 681b ldr r3, [r3, #0]
800af54: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800af56: 68bb ldr r3, [r7, #8]
800af58: 685b ldr r3, [r3, #4]
800af5a: 3b01 subs r3, #1
800af5c: 011b lsls r3, r3, #4
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af5e: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800af60: 68bb ldr r3, [r7, #8]
800af62: 689b ldr r3, [r3, #8]
800af64: 3b01 subs r3, #1
800af66: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800af68: 431a orrs r2, r3
(((Timing->RowCycleDelay)-1) << 12) |\
800af6a: 68bb ldr r3, [r7, #8]
800af6c: 68db ldr r3, [r3, #12]
800af6e: 3b01 subs r3, #1
800af70: 031b lsls r3, r3, #12
(((Timing->SelfRefreshTime)-1) << 8) |\
800af72: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800af74: 68bb ldr r3, [r7, #8]
800af76: 691b ldr r3, [r3, #16]
800af78: 3b01 subs r3, #1
800af7a: 041b lsls r3, r3, #16
(((Timing->RowCycleDelay)-1) << 12) |\
800af7c: 431a orrs r2, r3
(((Timing->RPDelay)-1) << 20) |\
800af7e: 68bb ldr r3, [r7, #8]
800af80: 695b ldr r3, [r3, #20]
800af82: 3b01 subs r3, #1
800af84: 051b lsls r3, r3, #20
(((Timing->WriteRecoveryTime)-1) <<16) |\
800af86: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800af88: 68bb ldr r3, [r7, #8]
800af8a: 699b ldr r3, [r3, #24]
800af8c: 3b01 subs r3, #1
800af8e: 061b lsls r3, r3, #24
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af90: 4313 orrs r3, r2
800af92: 697a ldr r2, [r7, #20]
800af94: 4313 orrs r3, r2
800af96: 617b str r3, [r7, #20]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800af98: 68fb ldr r3, [r7, #12]
800af9a: 697a ldr r2, [r7, #20]
800af9c: 609a str r2, [r3, #8]
800af9e: e039 b.n 800b014 <FMC_SDRAM_Timing_Init+0xec>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800afa0: 68fb ldr r3, [r7, #12]
800afa2: 689b ldr r3, [r3, #8]
800afa4: 617b str r3, [r7, #20]
/* Clear TRC and TRP bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
800afa6: 697a ldr r2, [r7, #20]
800afa8: 4b1e ldr r3, [pc, #120] ; (800b024 <FMC_SDRAM_Timing_Init+0xfc>)
800afaa: 4013 ands r3, r2
800afac: 617b str r3, [r7, #20]
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800afae: 68bb ldr r3, [r7, #8]
800afb0: 68db ldr r3, [r3, #12]
800afb2: 3b01 subs r3, #1
800afb4: 031a lsls r2, r3, #12
(((Timing->RPDelay)-1) << 20));
800afb6: 68bb ldr r3, [r7, #8]
800afb8: 695b ldr r3, [r3, #20]
800afba: 3b01 subs r3, #1
800afbc: 051b lsls r3, r3, #20
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800afbe: 4313 orrs r3, r2
800afc0: 697a ldr r2, [r7, #20]
800afc2: 4313 orrs r3, r2
800afc4: 617b str r3, [r7, #20]
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
800afc6: 68fb ldr r3, [r7, #12]
800afc8: 68db ldr r3, [r3, #12]
800afca: 613b str r3, [r7, #16]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800afcc: 693b ldr r3, [r7, #16]
800afce: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800afd2: 613b str r3, [r7, #16]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800afd4: 68bb ldr r3, [r7, #8]
800afd6: 681b ldr r3, [r3, #0]
800afd8: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800afda: 68bb ldr r3, [r7, #8]
800afdc: 685b ldr r3, [r3, #4]
800afde: 3b01 subs r3, #1
800afe0: 011b lsls r3, r3, #4
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800afe2: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800afe4: 68bb ldr r3, [r7, #8]
800afe6: 689b ldr r3, [r3, #8]
800afe8: 3b01 subs r3, #1
800afea: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800afec: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800afee: 68bb ldr r3, [r7, #8]
800aff0: 691b ldr r3, [r3, #16]
800aff2: 3b01 subs r3, #1
800aff4: 041b lsls r3, r3, #16
(((Timing->SelfRefreshTime)-1) << 8) |\
800aff6: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800aff8: 68bb ldr r3, [r7, #8]
800affa: 699b ldr r3, [r3, #24]
800affc: 3b01 subs r3, #1
800affe: 061b lsls r3, r3, #24
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800b000: 4313 orrs r3, r2
800b002: 693a ldr r2, [r7, #16]
800b004: 4313 orrs r3, r2
800b006: 613b str r3, [r7, #16]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800b008: 68fb ldr r3, [r7, #12]
800b00a: 697a ldr r2, [r7, #20]
800b00c: 609a str r2, [r3, #8]
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
800b00e: 68fb ldr r3, [r7, #12]
800b010: 693a ldr r2, [r7, #16]
800b012: 60da str r2, [r3, #12]
}
return HAL_OK;
800b014: 2300 movs r3, #0
}
800b016: 4618 mov r0, r3
800b018: 371c adds r7, #28
800b01a: 46bd mov sp, r7
800b01c: f85d 7b04 ldr.w r7, [sp], #4
800b020: 4770 bx lr
800b022: bf00 nop
800b024: ff0f0fff .word 0xff0f0fff
0800b028 <FMC_SDRAM_SendCommand>:
* @param Timing Pointer to SDRAM Timing structure
* @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
800b028: b480 push {r7}
800b02a: b087 sub sp, #28
800b02c: af00 add r7, sp, #0
800b02e: 60f8 str r0, [r7, #12]
800b030: 60b9 str r1, [r7, #8]
800b032: 607a str r2, [r7, #4]
__IO uint32_t tmpr = 0;
800b034: 2300 movs r3, #0
800b036: 617b str r3, [r7, #20]
assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
tmpr = (uint32_t)((Command->CommandMode) |\
800b038: 68bb ldr r3, [r7, #8]
800b03a: 681a ldr r2, [r3, #0]
(Command->CommandTarget) |\
800b03c: 68bb ldr r3, [r7, #8]
800b03e: 685b ldr r3, [r3, #4]
tmpr = (uint32_t)((Command->CommandMode) |\
800b040: 431a orrs r2, r3
(((Command->AutoRefreshNumber)-1) << 5) |\
800b042: 68bb ldr r3, [r7, #8]
800b044: 689b ldr r3, [r3, #8]
800b046: 3b01 subs r3, #1
800b048: 015b lsls r3, r3, #5
(Command->CommandTarget) |\
800b04a: 431a orrs r2, r3
((Command->ModeRegisterDefinition) << 9)
800b04c: 68bb ldr r3, [r7, #8]
800b04e: 68db ldr r3, [r3, #12]
800b050: 025b lsls r3, r3, #9
tmpr = (uint32_t)((Command->CommandMode) |\
800b052: 4313 orrs r3, r2
800b054: 617b str r3, [r7, #20]
);
Device->SDCMR = tmpr;
800b056: 697a ldr r2, [r7, #20]
800b058: 68fb ldr r3, [r7, #12]
800b05a: 611a str r2, [r3, #16]
return HAL_OK;
800b05c: 2300 movs r3, #0
}
800b05e: 4618 mov r0, r3
800b060: 371c adds r7, #28
800b062: 46bd mov sp, r7
800b064: f85d 7b04 ldr.w r7, [sp], #4
800b068: 4770 bx lr
0800b06a <FMC_SDRAM_ProgramRefreshRate>:
* @param Device Pointer to SDRAM device instance
* @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
{
800b06a: b480 push {r7}
800b06c: b083 sub sp, #12
800b06e: af00 add r7, sp, #0
800b070: 6078 str r0, [r7, #4]
800b072: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
/* Set the refresh rate in command register */
Device->SDRTR |= (RefreshRate<<1);
800b074: 687b ldr r3, [r7, #4]
800b076: 695a ldr r2, [r3, #20]
800b078: 683b ldr r3, [r7, #0]
800b07a: 005b lsls r3, r3, #1
800b07c: 431a orrs r2, r3
800b07e: 687b ldr r3, [r7, #4]
800b080: 615a str r2, [r3, #20]
return HAL_OK;
800b082: 2300 movs r3, #0
}
800b084: 4618 mov r0, r3
800b086: 370c adds r7, #12
800b088: 46bd mov sp, r7
800b08a: f85d 7b04 ldr.w r7, [sp], #4
800b08e: 4770 bx lr
0800b090 <MX_LWIP_Init>:
/**
* LwIP initialization function
*/
void MX_LWIP_Init(void)
{
800b090: b5b0 push {r4, r5, r7, lr}
800b092: b08e sub sp, #56 ; 0x38
800b094: af04 add r7, sp, #16
/* Initilialize the LwIP stack with RTOS */
tcpip_init( NULL, NULL );
800b096: 2100 movs r1, #0
800b098: 2000 movs r0, #0
800b09a: f003 fea7 bl 800edec <tcpip_init>
/* IP addresses initialization with DHCP (IPv4) */
ipaddr.addr = 0;
800b09e: 4b2a ldr r3, [pc, #168] ; (800b148 <MX_LWIP_Init+0xb8>)
800b0a0: 2200 movs r2, #0
800b0a2: 601a str r2, [r3, #0]
netmask.addr = 0;
800b0a4: 4b29 ldr r3, [pc, #164] ; (800b14c <MX_LWIP_Init+0xbc>)
800b0a6: 2200 movs r2, #0
800b0a8: 601a str r2, [r3, #0]
gw.addr = 0;
800b0aa: 4b29 ldr r3, [pc, #164] ; (800b150 <MX_LWIP_Init+0xc0>)
800b0ac: 2200 movs r2, #0
800b0ae: 601a str r2, [r3, #0]
/* add the network interface (IPv4/IPv6) with RTOS */
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &tcpip_input);
800b0b0: 4b28 ldr r3, [pc, #160] ; (800b154 <MX_LWIP_Init+0xc4>)
800b0b2: 9302 str r3, [sp, #8]
800b0b4: 4b28 ldr r3, [pc, #160] ; (800b158 <MX_LWIP_Init+0xc8>)
800b0b6: 9301 str r3, [sp, #4]
800b0b8: 2300 movs r3, #0
800b0ba: 9300 str r3, [sp, #0]
800b0bc: 4b24 ldr r3, [pc, #144] ; (800b150 <MX_LWIP_Init+0xc0>)
800b0be: 4a23 ldr r2, [pc, #140] ; (800b14c <MX_LWIP_Init+0xbc>)
800b0c0: 4921 ldr r1, [pc, #132] ; (800b148 <MX_LWIP_Init+0xb8>)
800b0c2: 4826 ldr r0, [pc, #152] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0c4: f004 fc16 bl 800f8f4 <netif_add>
/* Registers the default network interface */
netif_set_default(&gnetif);
800b0c8: 4824 ldr r0, [pc, #144] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0ca: f004 fdcd bl 800fc68 <netif_set_default>
if (netif_is_link_up(&gnetif))
800b0ce: 4b23 ldr r3, [pc, #140] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0d0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b0d4: 089b lsrs r3, r3, #2
800b0d6: f003 0301 and.w r3, r3, #1
800b0da: b2db uxtb r3, r3
800b0dc: 2b00 cmp r3, #0
800b0de: d003 beq.n 800b0e8 <MX_LWIP_Init+0x58>
{
/* When the netif is fully configured this function must be called */
netif_set_up(&gnetif);
800b0e0: 481e ldr r0, [pc, #120] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0e2: f004 fdd1 bl 800fc88 <netif_set_up>
800b0e6: e002 b.n 800b0ee <MX_LWIP_Init+0x5e>
}
else
{
/* When the netif link is down this function must be called */
netif_set_down(&gnetif);
800b0e8: 481c ldr r0, [pc, #112] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0ea: f004 fe39 bl 800fd60 <netif_set_down>
}
/* Set the link callback function, this function is called on change of link status*/
netif_set_link_callback(&gnetif, ethernetif_update_config);
800b0ee: 491c ldr r1, [pc, #112] ; (800b160 <MX_LWIP_Init+0xd0>)
800b0f0: 481a ldr r0, [pc, #104] ; (800b15c <MX_LWIP_Init+0xcc>)
800b0f2: f004 fecf bl 800fe94 <netif_set_link_callback>
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(Netif_SEM);
800b0f6: 2300 movs r3, #0
800b0f8: 623b str r3, [r7, #32]
800b0fa: 2300 movs r3, #0
800b0fc: 627b str r3, [r7, #36] ; 0x24
Netif_LinkSemaphore = osSemaphoreCreate(osSemaphore(Netif_SEM) , 1 );
800b0fe: f107 0320 add.w r3, r7, #32
800b102: 2101 movs r1, #1
800b104: 4618 mov r0, r3
800b106: f000 fd75 bl 800bbf4 <osSemaphoreCreate>
800b10a: 4602 mov r2, r0
800b10c: 4b15 ldr r3, [pc, #84] ; (800b164 <MX_LWIP_Init+0xd4>)
800b10e: 601a str r2, [r3, #0]
link_arg.netif = &gnetif;
800b110: 4b15 ldr r3, [pc, #84] ; (800b168 <MX_LWIP_Init+0xd8>)
800b112: 4a12 ldr r2, [pc, #72] ; (800b15c <MX_LWIP_Init+0xcc>)
800b114: 601a str r2, [r3, #0]
link_arg.semaphore = Netif_LinkSemaphore;
800b116: 4b13 ldr r3, [pc, #76] ; (800b164 <MX_LWIP_Init+0xd4>)
800b118: 681b ldr r3, [r3, #0]
800b11a: 4a13 ldr r2, [pc, #76] ; (800b168 <MX_LWIP_Init+0xd8>)
800b11c: 6053 str r3, [r2, #4]
/* Create the Ethernet link handler thread */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(LinkThr, ethernetif_set_link, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE * 2);
800b11e: 4b13 ldr r3, [pc, #76] ; (800b16c <MX_LWIP_Init+0xdc>)
800b120: 1d3c adds r4, r7, #4
800b122: 461d mov r5, r3
800b124: cd0f ldmia r5!, {r0, r1, r2, r3}
800b126: c40f stmia r4!, {r0, r1, r2, r3}
800b128: e895 0007 ldmia.w r5, {r0, r1, r2}
800b12c: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(LinkThr), &link_arg);
800b130: 1d3b adds r3, r7, #4
800b132: 490d ldr r1, [pc, #52] ; (800b168 <MX_LWIP_Init+0xd8>)
800b134: 4618 mov r0, r3
800b136: f000 fc60 bl 800b9fa <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Start DHCP negotiation for a network interface (IPv4) */
dhcp_start(&gnetif);
800b13a: 4808 ldr r0, [pc, #32] ; (800b15c <MX_LWIP_Init+0xcc>)
800b13c: f00c f80c bl 8017158 <dhcp_start>
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
}
800b140: bf00 nop
800b142: 3728 adds r7, #40 ; 0x28
800b144: 46bd mov sp, r7
800b146: bdb0 pop {r4, r5, r7, pc}
800b148: 20008d94 .word 0x20008d94
800b14c: 20008d98 .word 0x20008d98
800b150: 20008d9c .word 0x20008d9c
800b154: 0800ed29 .word 0x0800ed29
800b158: 0800b789 .word 0x0800b789
800b15c: 20008d5c .word 0x20008d5c
800b160: 0800b86d .word 0x0800b86d
800b164: 20000584 .word 0x20000584
800b168: 20008d54 .word 0x20008d54
800b16c: 0801bf38 .word 0x0801bf38
0800b170 <HAL_ETH_MspInit>:
/* USER CODE END 3 */
/* Private functions ---------------------------------------------------------*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
{
800b170: b580 push {r7, lr}
800b172: b08e sub sp, #56 ; 0x38
800b174: af00 add r7, sp, #0
800b176: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800b178: f107 0324 add.w r3, r7, #36 ; 0x24
800b17c: 2200 movs r2, #0
800b17e: 601a str r2, [r3, #0]
800b180: 605a str r2, [r3, #4]
800b182: 609a str r2, [r3, #8]
800b184: 60da str r2, [r3, #12]
800b186: 611a str r2, [r3, #16]
if(ethHandle->Instance==ETH)
800b188: 687b ldr r3, [r7, #4]
800b18a: 681b ldr r3, [r3, #0]
800b18c: 4a44 ldr r2, [pc, #272] ; (800b2a0 <HAL_ETH_MspInit+0x130>)
800b18e: 4293 cmp r3, r2
800b190: f040 8081 bne.w 800b296 <HAL_ETH_MspInit+0x126>
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Enable Peripheral clock */
__HAL_RCC_ETH_CLK_ENABLE();
800b194: 4b43 ldr r3, [pc, #268] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b196: 6b1b ldr r3, [r3, #48] ; 0x30
800b198: 4a42 ldr r2, [pc, #264] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b19a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800b19e: 6313 str r3, [r2, #48] ; 0x30
800b1a0: 4b40 ldr r3, [pc, #256] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1a2: 6b1b ldr r3, [r3, #48] ; 0x30
800b1a4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800b1a8: 623b str r3, [r7, #32]
800b1aa: 6a3b ldr r3, [r7, #32]
800b1ac: 4b3d ldr r3, [pc, #244] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1ae: 6b1b ldr r3, [r3, #48] ; 0x30
800b1b0: 4a3c ldr r2, [pc, #240] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1b2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800b1b6: 6313 str r3, [r2, #48] ; 0x30
800b1b8: 4b3a ldr r3, [pc, #232] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1ba: 6b1b ldr r3, [r3, #48] ; 0x30
800b1bc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800b1c0: 61fb str r3, [r7, #28]
800b1c2: 69fb ldr r3, [r7, #28]
800b1c4: 4b37 ldr r3, [pc, #220] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1c6: 6b1b ldr r3, [r3, #48] ; 0x30
800b1c8: 4a36 ldr r2, [pc, #216] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1ca: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
800b1ce: 6313 str r3, [r2, #48] ; 0x30
800b1d0: 4b34 ldr r3, [pc, #208] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1d2: 6b1b ldr r3, [r3, #48] ; 0x30
800b1d4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
800b1d8: 61bb str r3, [r7, #24]
800b1da: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOG_CLK_ENABLE();
800b1dc: 4b31 ldr r3, [pc, #196] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1de: 6b1b ldr r3, [r3, #48] ; 0x30
800b1e0: 4a30 ldr r2, [pc, #192] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1e2: f043 0340 orr.w r3, r3, #64 ; 0x40
800b1e6: 6313 str r3, [r2, #48] ; 0x30
800b1e8: 4b2e ldr r3, [pc, #184] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1ea: 6b1b ldr r3, [r3, #48] ; 0x30
800b1ec: f003 0340 and.w r3, r3, #64 ; 0x40
800b1f0: 617b str r3, [r7, #20]
800b1f2: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
800b1f4: 4b2b ldr r3, [pc, #172] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1f6: 6b1b ldr r3, [r3, #48] ; 0x30
800b1f8: 4a2a ldr r2, [pc, #168] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b1fa: f043 0304 orr.w r3, r3, #4
800b1fe: 6313 str r3, [r2, #48] ; 0x30
800b200: 4b28 ldr r3, [pc, #160] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b202: 6b1b ldr r3, [r3, #48] ; 0x30
800b204: f003 0304 and.w r3, r3, #4
800b208: 613b str r3, [r7, #16]
800b20a: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800b20c: 4b25 ldr r3, [pc, #148] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b20e: 6b1b ldr r3, [r3, #48] ; 0x30
800b210: 4a24 ldr r2, [pc, #144] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b212: f043 0301 orr.w r3, r3, #1
800b216: 6313 str r3, [r2, #48] ; 0x30
800b218: 4b22 ldr r3, [pc, #136] ; (800b2a4 <HAL_ETH_MspInit+0x134>)
800b21a: 6b1b ldr r3, [r3, #48] ; 0x30
800b21c: f003 0301 and.w r3, r3, #1
800b220: 60fb str r3, [r7, #12]
800b222: 68fb ldr r3, [r7, #12]
PC4 ------> ETH_RXD0
PA2 ------> ETH_MDIO
PC5 ------> ETH_RXD1
PA7 ------> ETH_CRS_DV
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11;
800b224: f44f 43d0 mov.w r3, #26624 ; 0x6800
800b228: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b22a: 2302 movs r3, #2
800b22c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b22e: 2300 movs r3, #0
800b230: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b232: 2303 movs r3, #3
800b234: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b236: 230b movs r3, #11
800b238: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800b23a: f107 0324 add.w r3, r7, #36 ; 0x24
800b23e: 4619 mov r1, r3
800b240: 4819 ldr r0, [pc, #100] ; (800b2a8 <HAL_ETH_MspInit+0x138>)
800b242: f7fc f819 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
800b246: 2332 movs r3, #50 ; 0x32
800b248: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b24a: 2302 movs r3, #2
800b24c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b24e: 2300 movs r3, #0
800b250: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b252: 2303 movs r3, #3
800b254: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b256: 230b movs r3, #11
800b258: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800b25a: f107 0324 add.w r3, r7, #36 ; 0x24
800b25e: 4619 mov r1, r3
800b260: 4812 ldr r0, [pc, #72] ; (800b2ac <HAL_ETH_MspInit+0x13c>)
800b262: f7fc f809 bl 8007278 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
800b266: 2386 movs r3, #134 ; 0x86
800b268: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b26a: 2302 movs r3, #2
800b26c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b26e: 2300 movs r3, #0
800b270: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b272: 2303 movs r3, #3
800b274: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b276: 230b movs r3, #11
800b278: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800b27a: f107 0324 add.w r3, r7, #36 ; 0x24
800b27e: 4619 mov r1, r3
800b280: 480b ldr r0, [pc, #44] ; (800b2b0 <HAL_ETH_MspInit+0x140>)
800b282: f7fb fff9 bl 8007278 <HAL_GPIO_Init>
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
800b286: 2200 movs r2, #0
800b288: 2105 movs r1, #5
800b28a: 203d movs r0, #61 ; 0x3d
800b28c: f7fa f844 bl 8005318 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ETH_IRQn);
800b290: 203d movs r0, #61 ; 0x3d
800b292: f7fa f85d bl 8005350 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
800b296: bf00 nop
800b298: 3738 adds r7, #56 ; 0x38
800b29a: 46bd mov sp, r7
800b29c: bd80 pop {r7, pc}
800b29e: bf00 nop
800b2a0: 40028000 .word 0x40028000
800b2a4: 40023800 .word 0x40023800
800b2a8: 40021800 .word 0x40021800
800b2ac: 40020800 .word 0x40020800
800b2b0: 40020000 .word 0x40020000
0800b2b4 <HAL_ETH_RxCpltCallback>:
* @brief Ethernet Rx Transfer completed callback
* @param heth: ETH handle
* @retval None
*/
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
800b2b4: b580 push {r7, lr}
800b2b6: b082 sub sp, #8
800b2b8: af00 add r7, sp, #0
800b2ba: 6078 str r0, [r7, #4]
osSemaphoreRelease(s_xSemaphore);
800b2bc: 4b04 ldr r3, [pc, #16] ; (800b2d0 <HAL_ETH_RxCpltCallback+0x1c>)
800b2be: 681b ldr r3, [r3, #0]
800b2c0: 4618 mov r0, r3
800b2c2: f000 fd25 bl 800bd10 <osSemaphoreRelease>
}
800b2c6: bf00 nop
800b2c8: 3708 adds r7, #8
800b2ca: 46bd mov sp, r7
800b2cc: bd80 pop {r7, pc}
800b2ce: bf00 nop
800b2d0: 20000588 .word 0x20000588
0800b2d4 <low_level_init>:
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
800b2d4: b5b0 push {r4, r5, r7, lr}
800b2d6: b090 sub sp, #64 ; 0x40
800b2d8: af00 add r7, sp, #0
800b2da: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b2dc: 2300 movs r3, #0
800b2de: 63bb str r3, [r7, #56] ; 0x38
HAL_StatusTypeDef hal_eth_init_status;
/* Init ETH */
uint8_t MACAddr[6] ;
heth.Instance = ETH;
800b2e0: 4b60 ldr r3, [pc, #384] ; (800b464 <low_level_init+0x190>)
800b2e2: 4a61 ldr r2, [pc, #388] ; (800b468 <low_level_init+0x194>)
800b2e4: 601a str r2, [r3, #0]
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
800b2e6: 4b5f ldr r3, [pc, #380] ; (800b464 <low_level_init+0x190>)
800b2e8: 2201 movs r2, #1
800b2ea: 605a str r2, [r3, #4]
heth.Init.Speed = ETH_SPEED_100M;
800b2ec: 4b5d ldr r3, [pc, #372] ; (800b464 <low_level_init+0x190>)
800b2ee: f44f 4280 mov.w r2, #16384 ; 0x4000
800b2f2: 609a str r2, [r3, #8]
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b2f4: 4b5b ldr r3, [pc, #364] ; (800b464 <low_level_init+0x190>)
800b2f6: f44f 6200 mov.w r2, #2048 ; 0x800
800b2fa: 60da str r2, [r3, #12]
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
800b2fc: 4b59 ldr r3, [pc, #356] ; (800b464 <low_level_init+0x190>)
800b2fe: 2201 movs r2, #1
800b300: 821a strh r2, [r3, #16]
MACAddr[0] = 0x00;
800b302: 2300 movs r3, #0
800b304: f887 3030 strb.w r3, [r7, #48] ; 0x30
MACAddr[1] = 0x80;
800b308: 2380 movs r3, #128 ; 0x80
800b30a: f887 3031 strb.w r3, [r7, #49] ; 0x31
MACAddr[2] = 0xE1;
800b30e: 23e1 movs r3, #225 ; 0xe1
800b310: f887 3032 strb.w r3, [r7, #50] ; 0x32
MACAddr[3] = 0x00;
800b314: 2300 movs r3, #0
800b316: f887 3033 strb.w r3, [r7, #51] ; 0x33
MACAddr[4] = 0x00;
800b31a: 2300 movs r3, #0
800b31c: f887 3034 strb.w r3, [r7, #52] ; 0x34
MACAddr[5] = 0x00;
800b320: 2300 movs r3, #0
800b322: f887 3035 strb.w r3, [r7, #53] ; 0x35
heth.Init.MACAddr = &MACAddr[0];
800b326: 4a4f ldr r2, [pc, #316] ; (800b464 <low_level_init+0x190>)
800b328: f107 0330 add.w r3, r7, #48 ; 0x30
800b32c: 6153 str r3, [r2, #20]
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
800b32e: 4b4d ldr r3, [pc, #308] ; (800b464 <low_level_init+0x190>)
800b330: 2201 movs r2, #1
800b332: 619a str r2, [r3, #24]
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
800b334: 4b4b ldr r3, [pc, #300] ; (800b464 <low_level_init+0x190>)
800b336: 2200 movs r2, #0
800b338: 61da str r2, [r3, #28]
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
800b33a: 4b4a ldr r3, [pc, #296] ; (800b464 <low_level_init+0x190>)
800b33c: f44f 0200 mov.w r2, #8388608 ; 0x800000
800b340: 621a str r2, [r3, #32]
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
hal_eth_init_status = HAL_ETH_Init(&heth);
800b342: 4848 ldr r0, [pc, #288] ; (800b464 <low_level_init+0x190>)
800b344: f7fa fe12 bl 8005f6c <HAL_ETH_Init>
800b348: 4603 mov r3, r0
800b34a: f887 303f strb.w r3, [r7, #63] ; 0x3f
if (hal_eth_init_status == HAL_OK)
800b34e: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
800b352: 2b00 cmp r3, #0
800b354: d108 bne.n 800b368 <low_level_init+0x94>
{
/* Set netif link flag */
netif->flags |= NETIF_FLAG_LINK_UP;
800b356: 687b ldr r3, [r7, #4]
800b358: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b35c: f043 0304 orr.w r3, r3, #4
800b360: b2da uxtb r2, r3
800b362: 687b ldr r3, [r7, #4]
800b364: f883 2031 strb.w r2, [r3, #49] ; 0x31
}
/* Initialize Tx Descriptors list: Chain Mode */
HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
800b368: 2304 movs r3, #4
800b36a: 4a40 ldr r2, [pc, #256] ; (800b46c <low_level_init+0x198>)
800b36c: 4940 ldr r1, [pc, #256] ; (800b470 <low_level_init+0x19c>)
800b36e: 483d ldr r0, [pc, #244] ; (800b464 <low_level_init+0x190>)
800b370: f7fa ff98 bl 80062a4 <HAL_ETH_DMATxDescListInit>
/* Initialize Rx Descriptors list: Chain Mode */
HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
800b374: 2304 movs r3, #4
800b376: 4a3f ldr r2, [pc, #252] ; (800b474 <low_level_init+0x1a0>)
800b378: 493f ldr r1, [pc, #252] ; (800b478 <low_level_init+0x1a4>)
800b37a: 483a ldr r0, [pc, #232] ; (800b464 <low_level_init+0x190>)
800b37c: f7fa fffb bl 8006376 <HAL_ETH_DMARxDescListInit>
#if LWIP_ARP || LWIP_ETHERNET
/* set MAC hardware address length */
netif->hwaddr_len = ETH_HWADDR_LEN;
800b380: 687b ldr r3, [r7, #4]
800b382: 2206 movs r2, #6
800b384: f883 2030 strb.w r2, [r3, #48] ; 0x30
/* set MAC hardware address */
netif->hwaddr[0] = heth.Init.MACAddr[0];
800b388: 4b36 ldr r3, [pc, #216] ; (800b464 <low_level_init+0x190>)
800b38a: 695b ldr r3, [r3, #20]
800b38c: 781a ldrb r2, [r3, #0]
800b38e: 687b ldr r3, [r7, #4]
800b390: f883 202a strb.w r2, [r3, #42] ; 0x2a
netif->hwaddr[1] = heth.Init.MACAddr[1];
800b394: 4b33 ldr r3, [pc, #204] ; (800b464 <low_level_init+0x190>)
800b396: 695b ldr r3, [r3, #20]
800b398: 785a ldrb r2, [r3, #1]
800b39a: 687b ldr r3, [r7, #4]
800b39c: f883 202b strb.w r2, [r3, #43] ; 0x2b
netif->hwaddr[2] = heth.Init.MACAddr[2];
800b3a0: 4b30 ldr r3, [pc, #192] ; (800b464 <low_level_init+0x190>)
800b3a2: 695b ldr r3, [r3, #20]
800b3a4: 789a ldrb r2, [r3, #2]
800b3a6: 687b ldr r3, [r7, #4]
800b3a8: f883 202c strb.w r2, [r3, #44] ; 0x2c
netif->hwaddr[3] = heth.Init.MACAddr[3];
800b3ac: 4b2d ldr r3, [pc, #180] ; (800b464 <low_level_init+0x190>)
800b3ae: 695b ldr r3, [r3, #20]
800b3b0: 78da ldrb r2, [r3, #3]
800b3b2: 687b ldr r3, [r7, #4]
800b3b4: f883 202d strb.w r2, [r3, #45] ; 0x2d
netif->hwaddr[4] = heth.Init.MACAddr[4];
800b3b8: 4b2a ldr r3, [pc, #168] ; (800b464 <low_level_init+0x190>)
800b3ba: 695b ldr r3, [r3, #20]
800b3bc: 791a ldrb r2, [r3, #4]
800b3be: 687b ldr r3, [r7, #4]
800b3c0: f883 202e strb.w r2, [r3, #46] ; 0x2e
netif->hwaddr[5] = heth.Init.MACAddr[5];
800b3c4: 4b27 ldr r3, [pc, #156] ; (800b464 <low_level_init+0x190>)
800b3c6: 695b ldr r3, [r3, #20]
800b3c8: 795a ldrb r2, [r3, #5]
800b3ca: 687b ldr r3, [r7, #4]
800b3cc: f883 202f strb.w r2, [r3, #47] ; 0x2f
/* maximum transfer unit */
netif->mtu = 1500;
800b3d0: 687b ldr r3, [r7, #4]
800b3d2: f240 52dc movw r2, #1500 ; 0x5dc
800b3d6: 851a strh r2, [r3, #40] ; 0x28
/* Accept broadcast address and ARP traffic */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
#if LWIP_ARP
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
800b3d8: 687b ldr r3, [r7, #4]
800b3da: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b3de: f043 030a orr.w r3, r3, #10
800b3e2: b2da uxtb r2, r3
800b3e4: 687b ldr r3, [r7, #4]
800b3e6: f883 2031 strb.w r2, [r3, #49] ; 0x31
#else
netif->flags |= NETIF_FLAG_BROADCAST;
#endif /* LWIP_ARP */
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(SEM);
800b3ea: 2300 movs r3, #0
800b3ec: 62bb str r3, [r7, #40] ; 0x28
800b3ee: 2300 movs r3, #0
800b3f0: 62fb str r3, [r7, #44] ; 0x2c
s_xSemaphore = osSemaphoreCreate(osSemaphore(SEM), 1);
800b3f2: f107 0328 add.w r3, r7, #40 ; 0x28
800b3f6: 2101 movs r1, #1
800b3f8: 4618 mov r0, r3
800b3fa: f000 fbfb bl 800bbf4 <osSemaphoreCreate>
800b3fe: 4602 mov r2, r0
800b400: 4b1e ldr r3, [pc, #120] ; (800b47c <low_level_init+0x1a8>)
800b402: 601a str r2, [r3, #0]
/* create the task that handles the ETH_MAC */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
800b404: 4b1e ldr r3, [pc, #120] ; (800b480 <low_level_init+0x1ac>)
800b406: f107 040c add.w r4, r7, #12
800b40a: 461d mov r5, r3
800b40c: cd0f ldmia r5!, {r0, r1, r2, r3}
800b40e: c40f stmia r4!, {r0, r1, r2, r3}
800b410: e895 0007 ldmia.w r5, {r0, r1, r2}
800b414: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(EthIf), netif);
800b418: f107 030c add.w r3, r7, #12
800b41c: 6879 ldr r1, [r7, #4]
800b41e: 4618 mov r0, r3
800b420: f000 faeb bl 800b9fa <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Enable MAC and DMA transmission and reception */
HAL_ETH_Start(&heth);
800b424: 480f ldr r0, [pc, #60] ; (800b464 <low_level_init+0x190>)
800b426: f7fb face bl 80069c6 <HAL_ETH_Start>
/* USER CODE BEGIN PHY_PRE_CONFIG */
/* USER CODE END PHY_PRE_CONFIG */
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR, &regvalue);
800b42a: f107 0338 add.w r3, r7, #56 ; 0x38
800b42e: 461a mov r2, r3
800b430: 211d movs r1, #29
800b432: 480c ldr r0, [pc, #48] ; (800b464 <low_level_init+0x190>)
800b434: f7fb f9f9 bl 800682a <HAL_ETH_ReadPHYRegister>
regvalue |= (PHY_ISFR_INT4);
800b438: 6bbb ldr r3, [r7, #56] ; 0x38
800b43a: f043 030b orr.w r3, r3, #11
800b43e: 63bb str r3, [r7, #56] ; 0x38
/* Enable Interrupt on change of link status */
HAL_ETH_WritePHYRegister(&heth, PHY_ISFR , regvalue );
800b440: 6bbb ldr r3, [r7, #56] ; 0x38
800b442: 461a mov r2, r3
800b444: 211d movs r1, #29
800b446: 4807 ldr r0, [pc, #28] ; (800b464 <low_level_init+0x190>)
800b448: f7fb fa57 bl 80068fa <HAL_ETH_WritePHYRegister>
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , &regvalue);
800b44c: f107 0338 add.w r3, r7, #56 ; 0x38
800b450: 461a mov r2, r3
800b452: 211d movs r1, #29
800b454: 4803 ldr r0, [pc, #12] ; (800b464 <low_level_init+0x190>)
800b456: f7fb f9e8 bl 800682a <HAL_ETH_ReadPHYRegister>
#endif /* LWIP_ARP || LWIP_ETHERNET */
/* USER CODE BEGIN LOW_LEVEL_INIT */
/* USER CODE END LOW_LEVEL_INIT */
}
800b45a: bf00 nop
800b45c: 3740 adds r7, #64 ; 0x40
800b45e: 46bd mov sp, r7
800b460: bdb0 pop {r4, r5, r7, pc}
800b462: bf00 nop
800b464: 2000a670 .word 0x2000a670
800b468: 40028000 .word 0x40028000
800b46c: 2000a6b8 .word 0x2000a6b8
800b470: 20008da0 .word 0x20008da0
800b474: 20008e20 .word 0x20008e20
800b478: 2000a5f0 .word 0x2000a5f0
800b47c: 20000588 .word 0x20000588
800b480: 0801bf5c .word 0x0801bf5c
0800b484 <low_level_output>:
* to become availale since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
800b484: b580 push {r7, lr}
800b486: b08a sub sp, #40 ; 0x28
800b488: af00 add r7, sp, #0
800b48a: 6078 str r0, [r7, #4]
800b48c: 6039 str r1, [r7, #0]
err_t errval;
struct pbuf *q;
uint8_t *buffer = (uint8_t *)(heth.TxDesc->Buffer1Addr);
800b48e: 4b4b ldr r3, [pc, #300] ; (800b5bc <low_level_output+0x138>)
800b490: 6adb ldr r3, [r3, #44] ; 0x2c
800b492: 689b ldr r3, [r3, #8]
800b494: 61fb str r3, [r7, #28]
__IO ETH_DMADescTypeDef *DmaTxDesc;
uint32_t framelength = 0;
800b496: 2300 movs r3, #0
800b498: 617b str r3, [r7, #20]
uint32_t bufferoffset = 0;
800b49a: 2300 movs r3, #0
800b49c: 613b str r3, [r7, #16]
uint32_t byteslefttocopy = 0;
800b49e: 2300 movs r3, #0
800b4a0: 60fb str r3, [r7, #12]
uint32_t payloadoffset = 0;
800b4a2: 2300 movs r3, #0
800b4a4: 60bb str r3, [r7, #8]
DmaTxDesc = heth.TxDesc;
800b4a6: 4b45 ldr r3, [pc, #276] ; (800b5bc <low_level_output+0x138>)
800b4a8: 6adb ldr r3, [r3, #44] ; 0x2c
800b4aa: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b4ac: 2300 movs r3, #0
800b4ae: 613b str r3, [r7, #16]
/* copy frame from pbufs to driver buffers */
for(q = p; q != NULL; q = q->next)
800b4b0: 683b ldr r3, [r7, #0]
800b4b2: 623b str r3, [r7, #32]
800b4b4: e05a b.n 800b56c <low_level_output+0xe8>
{
/* Is this buffer available? If not, goto error */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b4b6: 69bb ldr r3, [r7, #24]
800b4b8: 681b ldr r3, [r3, #0]
800b4ba: 2b00 cmp r3, #0
800b4bc: da03 bge.n 800b4c6 <low_level_output+0x42>
{
errval = ERR_USE;
800b4be: 23f8 movs r3, #248 ; 0xf8
800b4c0: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b4c4: e05c b.n 800b580 <low_level_output+0xfc>
}
/* Get bytes in current lwIP buffer */
byteslefttocopy = q->len;
800b4c6: 6a3b ldr r3, [r7, #32]
800b4c8: 895b ldrh r3, [r3, #10]
800b4ca: 60fb str r3, [r7, #12]
payloadoffset = 0;
800b4cc: 2300 movs r3, #0
800b4ce: 60bb str r3, [r7, #8]
/* Check if the length of data to copy is bigger than Tx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b4d0: e02f b.n 800b532 <low_level_output+0xae>
{
/* Copy data to Tx buffer*/
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
800b4d2: 69fa ldr r2, [r7, #28]
800b4d4: 693b ldr r3, [r7, #16]
800b4d6: 18d0 adds r0, r2, r3
800b4d8: 6a3b ldr r3, [r7, #32]
800b4da: 685a ldr r2, [r3, #4]
800b4dc: 68bb ldr r3, [r7, #8]
800b4de: 18d1 adds r1, r2, r3
800b4e0: 693a ldr r2, [r7, #16]
800b4e2: f240 53f4 movw r3, #1524 ; 0x5f4
800b4e6: 1a9b subs r3, r3, r2
800b4e8: 461a mov r2, r3
800b4ea: f00f fd80 bl 801afee <memcpy>
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
800b4ee: 69bb ldr r3, [r7, #24]
800b4f0: 68db ldr r3, [r3, #12]
800b4f2: 61bb str r3, [r7, #24]
/* Check if the buffer is available */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b4f4: 69bb ldr r3, [r7, #24]
800b4f6: 681b ldr r3, [r3, #0]
800b4f8: 2b00 cmp r3, #0
800b4fa: da03 bge.n 800b504 <low_level_output+0x80>
{
errval = ERR_USE;
800b4fc: 23f8 movs r3, #248 ; 0xf8
800b4fe: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b502: e03d b.n 800b580 <low_level_output+0xfc>
}
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
800b504: 69bb ldr r3, [r7, #24]
800b506: 689b ldr r3, [r3, #8]
800b508: 61fb str r3, [r7, #28]
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
800b50a: 693a ldr r2, [r7, #16]
800b50c: 68fb ldr r3, [r7, #12]
800b50e: 4413 add r3, r2
800b510: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b514: 60fb str r3, [r7, #12]
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
800b516: 68ba ldr r2, [r7, #8]
800b518: 693b ldr r3, [r7, #16]
800b51a: 1ad3 subs r3, r2, r3
800b51c: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b520: 60bb str r3, [r7, #8]
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
800b522: 697a ldr r2, [r7, #20]
800b524: 693b ldr r3, [r7, #16]
800b526: 1ad3 subs r3, r2, r3
800b528: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b52c: 617b str r3, [r7, #20]
bufferoffset = 0;
800b52e: 2300 movs r3, #0
800b530: 613b str r3, [r7, #16]
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b532: 68fa ldr r2, [r7, #12]
800b534: 693b ldr r3, [r7, #16]
800b536: 4413 add r3, r2
800b538: f240 52f4 movw r2, #1524 ; 0x5f4
800b53c: 4293 cmp r3, r2
800b53e: d8c8 bhi.n 800b4d2 <low_level_output+0x4e>
}
/* Copy the remaining bytes */
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
800b540: 69fa ldr r2, [r7, #28]
800b542: 693b ldr r3, [r7, #16]
800b544: 18d0 adds r0, r2, r3
800b546: 6a3b ldr r3, [r7, #32]
800b548: 685a ldr r2, [r3, #4]
800b54a: 68bb ldr r3, [r7, #8]
800b54c: 4413 add r3, r2
800b54e: 68fa ldr r2, [r7, #12]
800b550: 4619 mov r1, r3
800b552: f00f fd4c bl 801afee <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b556: 693a ldr r2, [r7, #16]
800b558: 68fb ldr r3, [r7, #12]
800b55a: 4413 add r3, r2
800b55c: 613b str r3, [r7, #16]
framelength = framelength + byteslefttocopy;
800b55e: 697a ldr r2, [r7, #20]
800b560: 68fb ldr r3, [r7, #12]
800b562: 4413 add r3, r2
800b564: 617b str r3, [r7, #20]
for(q = p; q != NULL; q = q->next)
800b566: 6a3b ldr r3, [r7, #32]
800b568: 681b ldr r3, [r3, #0]
800b56a: 623b str r3, [r7, #32]
800b56c: 6a3b ldr r3, [r7, #32]
800b56e: 2b00 cmp r3, #0
800b570: d1a1 bne.n 800b4b6 <low_level_output+0x32>
}
/* Prepare transmit descriptors to give to DMA */
HAL_ETH_TransmitFrame(&heth, framelength);
800b572: 6979 ldr r1, [r7, #20]
800b574: 4811 ldr r0, [pc, #68] ; (800b5bc <low_level_output+0x138>)
800b576: f7fa ff6b bl 8006450 <HAL_ETH_TransmitFrame>
errval = ERR_OK;
800b57a: 2300 movs r3, #0
800b57c: f887 3027 strb.w r3, [r7, #39] ; 0x27
error:
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
800b580: 4b0e ldr r3, [pc, #56] ; (800b5bc <low_level_output+0x138>)
800b582: 681a ldr r2, [r3, #0]
800b584: f241 0314 movw r3, #4116 ; 0x1014
800b588: 4413 add r3, r2
800b58a: 681b ldr r3, [r3, #0]
800b58c: f003 0320 and.w r3, r3, #32
800b590: 2b00 cmp r3, #0
800b592: d00d beq.n 800b5b0 <low_level_output+0x12c>
{
/* Clear TUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_TUS;
800b594: 4b09 ldr r3, [pc, #36] ; (800b5bc <low_level_output+0x138>)
800b596: 681a ldr r2, [r3, #0]
800b598: f241 0314 movw r3, #4116 ; 0x1014
800b59c: 4413 add r3, r2
800b59e: 2220 movs r2, #32
800b5a0: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
heth.Instance->DMATPDR = 0;
800b5a2: 4b06 ldr r3, [pc, #24] ; (800b5bc <low_level_output+0x138>)
800b5a4: 681a ldr r2, [r3, #0]
800b5a6: f241 0304 movw r3, #4100 ; 0x1004
800b5aa: 4413 add r3, r2
800b5ac: 2200 movs r2, #0
800b5ae: 601a str r2, [r3, #0]
}
return errval;
800b5b0: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
800b5b4: 4618 mov r0, r3
800b5b6: 3728 adds r7, #40 ; 0x28
800b5b8: 46bd mov sp, r7
800b5ba: bd80 pop {r7, pc}
800b5bc: 2000a670 .word 0x2000a670
0800b5c0 <low_level_input>:
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf * low_level_input(struct netif *netif)
{
800b5c0: b580 push {r7, lr}
800b5c2: b08c sub sp, #48 ; 0x30
800b5c4: af00 add r7, sp, #0
800b5c6: 6078 str r0, [r7, #4]
struct pbuf *p = NULL;
800b5c8: 2300 movs r3, #0
800b5ca: 62fb str r3, [r7, #44] ; 0x2c
struct pbuf *q = NULL;
800b5cc: 2300 movs r3, #0
800b5ce: 62bb str r3, [r7, #40] ; 0x28
uint16_t len = 0;
800b5d0: 2300 movs r3, #0
800b5d2: 81fb strh r3, [r7, #14]
uint8_t *buffer;
__IO ETH_DMADescTypeDef *dmarxdesc;
uint32_t bufferoffset = 0;
800b5d4: 2300 movs r3, #0
800b5d6: 61fb str r3, [r7, #28]
uint32_t payloadoffset = 0;
800b5d8: 2300 movs r3, #0
800b5da: 61bb str r3, [r7, #24]
uint32_t byteslefttocopy = 0;
800b5dc: 2300 movs r3, #0
800b5de: 617b str r3, [r7, #20]
uint32_t i=0;
800b5e0: 2300 movs r3, #0
800b5e2: 613b str r3, [r7, #16]
/* get received frame */
if (HAL_ETH_GetReceivedFrame_IT(&heth) != HAL_OK)
800b5e4: 484f ldr r0, [pc, #316] ; (800b724 <low_level_input+0x164>)
800b5e6: f7fb f81d bl 8006624 <HAL_ETH_GetReceivedFrame_IT>
800b5ea: 4603 mov r3, r0
800b5ec: 2b00 cmp r3, #0
800b5ee: d001 beq.n 800b5f4 <low_level_input+0x34>
return NULL;
800b5f0: 2300 movs r3, #0
800b5f2: e092 b.n 800b71a <low_level_input+0x15a>
/* Obtain the size of the packet and put it into the "len" variable. */
len = heth.RxFrameInfos.length;
800b5f4: 4b4b ldr r3, [pc, #300] ; (800b724 <low_level_input+0x164>)
800b5f6: 6bdb ldr r3, [r3, #60] ; 0x3c
800b5f8: 81fb strh r3, [r7, #14]
buffer = (uint8_t *)heth.RxFrameInfos.buffer;
800b5fa: 4b4a ldr r3, [pc, #296] ; (800b724 <low_level_input+0x164>)
800b5fc: 6c1b ldr r3, [r3, #64] ; 0x40
800b5fe: 627b str r3, [r7, #36] ; 0x24
if (len > 0)
800b600: 89fb ldrh r3, [r7, #14]
800b602: 2b00 cmp r3, #0
800b604: d007 beq.n 800b616 <low_level_input+0x56>
{
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
800b606: 89fb ldrh r3, [r7, #14]
800b608: f44f 72c1 mov.w r2, #386 ; 0x182
800b60c: 4619 mov r1, r3
800b60e: 2000 movs r0, #0
800b610: f004 fd0a bl 8010028 <pbuf_alloc>
800b614: 62f8 str r0, [r7, #44] ; 0x2c
}
if (p != NULL)
800b616: 6afb ldr r3, [r7, #44] ; 0x2c
800b618: 2b00 cmp r3, #0
800b61a: d04b beq.n 800b6b4 <low_level_input+0xf4>
{
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b61c: 4b41 ldr r3, [pc, #260] ; (800b724 <low_level_input+0x164>)
800b61e: 6b1b ldr r3, [r3, #48] ; 0x30
800b620: 623b str r3, [r7, #32]
bufferoffset = 0;
800b622: 2300 movs r3, #0
800b624: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b626: 6afb ldr r3, [r7, #44] ; 0x2c
800b628: 62bb str r3, [r7, #40] ; 0x28
800b62a: e040 b.n 800b6ae <low_level_input+0xee>
{
byteslefttocopy = q->len;
800b62c: 6abb ldr r3, [r7, #40] ; 0x28
800b62e: 895b ldrh r3, [r3, #10]
800b630: 617b str r3, [r7, #20]
payloadoffset = 0;
800b632: 2300 movs r3, #0
800b634: 61bb str r3, [r7, #24]
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b636: e021 b.n 800b67c <low_level_input+0xbc>
{
/* Copy data to pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
800b638: 6abb ldr r3, [r7, #40] ; 0x28
800b63a: 685a ldr r2, [r3, #4]
800b63c: 69bb ldr r3, [r7, #24]
800b63e: 18d0 adds r0, r2, r3
800b640: 6a7a ldr r2, [r7, #36] ; 0x24
800b642: 69fb ldr r3, [r7, #28]
800b644: 18d1 adds r1, r2, r3
800b646: 69fa ldr r2, [r7, #28]
800b648: f240 53f4 movw r3, #1524 ; 0x5f4
800b64c: 1a9b subs r3, r3, r2
800b64e: 461a mov r2, r3
800b650: f00f fccd bl 801afee <memcpy>
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b654: 6a3b ldr r3, [r7, #32]
800b656: 68db ldr r3, [r3, #12]
800b658: 623b str r3, [r7, #32]
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
800b65a: 6a3b ldr r3, [r7, #32]
800b65c: 689b ldr r3, [r3, #8]
800b65e: 627b str r3, [r7, #36] ; 0x24
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
800b660: 69fa ldr r2, [r7, #28]
800b662: 697b ldr r3, [r7, #20]
800b664: 4413 add r3, r2
800b666: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b66a: 617b str r3, [r7, #20]
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
800b66c: 69ba ldr r2, [r7, #24]
800b66e: 69fb ldr r3, [r7, #28]
800b670: 1ad3 subs r3, r2, r3
800b672: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b676: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b678: 2300 movs r3, #0
800b67a: 61fb str r3, [r7, #28]
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b67c: 697a ldr r2, [r7, #20]
800b67e: 69fb ldr r3, [r7, #28]
800b680: 4413 add r3, r2
800b682: f240 52f4 movw r2, #1524 ; 0x5f4
800b686: 4293 cmp r3, r2
800b688: d8d6 bhi.n 800b638 <low_level_input+0x78>
}
/* Copy remaining data in pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
800b68a: 6abb ldr r3, [r7, #40] ; 0x28
800b68c: 685a ldr r2, [r3, #4]
800b68e: 69bb ldr r3, [r7, #24]
800b690: 18d0 adds r0, r2, r3
800b692: 6a7a ldr r2, [r7, #36] ; 0x24
800b694: 69fb ldr r3, [r7, #28]
800b696: 4413 add r3, r2
800b698: 697a ldr r2, [r7, #20]
800b69a: 4619 mov r1, r3
800b69c: f00f fca7 bl 801afee <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b6a0: 69fa ldr r2, [r7, #28]
800b6a2: 697b ldr r3, [r7, #20]
800b6a4: 4413 add r3, r2
800b6a6: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b6a8: 6abb ldr r3, [r7, #40] ; 0x28
800b6aa: 681b ldr r3, [r3, #0]
800b6ac: 62bb str r3, [r7, #40] ; 0x28
800b6ae: 6abb ldr r3, [r7, #40] ; 0x28
800b6b0: 2b00 cmp r3, #0
800b6b2: d1bb bne.n 800b62c <low_level_input+0x6c>
}
}
/* Release descriptors to DMA */
/* Point to first descriptor */
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b6b4: 4b1b ldr r3, [pc, #108] ; (800b724 <low_level_input+0x164>)
800b6b6: 6b1b ldr r3, [r3, #48] ; 0x30
800b6b8: 623b str r3, [r7, #32]
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b6ba: 2300 movs r3, #0
800b6bc: 613b str r3, [r7, #16]
800b6be: e00b b.n 800b6d8 <low_level_input+0x118>
{
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
800b6c0: 6a3b ldr r3, [r7, #32]
800b6c2: 681b ldr r3, [r3, #0]
800b6c4: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
800b6c8: 6a3b ldr r3, [r7, #32]
800b6ca: 601a str r2, [r3, #0]
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b6cc: 6a3b ldr r3, [r7, #32]
800b6ce: 68db ldr r3, [r3, #12]
800b6d0: 623b str r3, [r7, #32]
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b6d2: 693b ldr r3, [r7, #16]
800b6d4: 3301 adds r3, #1
800b6d6: 613b str r3, [r7, #16]
800b6d8: 4b12 ldr r3, [pc, #72] ; (800b724 <low_level_input+0x164>)
800b6da: 6b9b ldr r3, [r3, #56] ; 0x38
800b6dc: 693a ldr r2, [r7, #16]
800b6de: 429a cmp r2, r3
800b6e0: d3ee bcc.n 800b6c0 <low_level_input+0x100>
}
/* Clear Segment_Count */
heth.RxFrameInfos.SegCount =0;
800b6e2: 4b10 ldr r3, [pc, #64] ; (800b724 <low_level_input+0x164>)
800b6e4: 2200 movs r2, #0
800b6e6: 639a str r2, [r3, #56] ; 0x38
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
800b6e8: 4b0e ldr r3, [pc, #56] ; (800b724 <low_level_input+0x164>)
800b6ea: 681a ldr r2, [r3, #0]
800b6ec: f241 0314 movw r3, #4116 ; 0x1014
800b6f0: 4413 add r3, r2
800b6f2: 681b ldr r3, [r3, #0]
800b6f4: f003 0380 and.w r3, r3, #128 ; 0x80
800b6f8: 2b00 cmp r3, #0
800b6fa: d00d beq.n 800b718 <low_level_input+0x158>
{
/* Clear RBUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_RBUS;
800b6fc: 4b09 ldr r3, [pc, #36] ; (800b724 <low_level_input+0x164>)
800b6fe: 681a ldr r2, [r3, #0]
800b700: f241 0314 movw r3, #4116 ; 0x1014
800b704: 4413 add r3, r2
800b706: 2280 movs r2, #128 ; 0x80
800b708: 601a str r2, [r3, #0]
/* Resume DMA reception */
heth.Instance->DMARPDR = 0;
800b70a: 4b06 ldr r3, [pc, #24] ; (800b724 <low_level_input+0x164>)
800b70c: 681a ldr r2, [r3, #0]
800b70e: f241 0308 movw r3, #4104 ; 0x1008
800b712: 4413 add r3, r2
800b714: 2200 movs r2, #0
800b716: 601a str r2, [r3, #0]
}
return p;
800b718: 6afb ldr r3, [r7, #44] ; 0x2c
}
800b71a: 4618 mov r0, r3
800b71c: 3730 adds r7, #48 ; 0x30
800b71e: 46bd mov sp, r7
800b720: bd80 pop {r7, pc}
800b722: bf00 nop
800b724: 2000a670 .word 0x2000a670
0800b728 <ethernetif_input>:
* the appropriate input function is called.
*
* @param netif the lwip network interface structure for this ethernetif
*/
void ethernetif_input(void const * argument)
{
800b728: b580 push {r7, lr}
800b72a: b084 sub sp, #16
800b72c: af00 add r7, sp, #0
800b72e: 6078 str r0, [r7, #4]
struct pbuf *p;
struct netif *netif = (struct netif *) argument;
800b730: 687b ldr r3, [r7, #4]
800b732: 60fb str r3, [r7, #12]
for( ;; )
{
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b734: 4b12 ldr r3, [pc, #72] ; (800b780 <ethernetif_input+0x58>)
800b736: 681b ldr r3, [r3, #0]
800b738: f04f 31ff mov.w r1, #4294967295
800b73c: 4618 mov r0, r3
800b73e: f000 fa99 bl 800bc74 <osSemaphoreWait>
800b742: 4603 mov r3, r0
800b744: 2b00 cmp r3, #0
800b746: d1f5 bne.n 800b734 <ethernetif_input+0xc>
{
do
{
LOCK_TCPIP_CORE();
800b748: 480e ldr r0, [pc, #56] ; (800b784 <ethernetif_input+0x5c>)
800b74a: f00f fbbd bl 801aec8 <sys_mutex_lock>
p = low_level_input( netif );
800b74e: 68f8 ldr r0, [r7, #12]
800b750: f7ff ff36 bl 800b5c0 <low_level_input>
800b754: 60b8 str r0, [r7, #8]
if (p != NULL)
800b756: 68bb ldr r3, [r7, #8]
800b758: 2b00 cmp r3, #0
800b75a: d00a beq.n 800b772 <ethernetif_input+0x4a>
{
if (netif->input( p, netif) != ERR_OK )
800b75c: 68fb ldr r3, [r7, #12]
800b75e: 691b ldr r3, [r3, #16]
800b760: 68f9 ldr r1, [r7, #12]
800b762: 68b8 ldr r0, [r7, #8]
800b764: 4798 blx r3
800b766: 4603 mov r3, r0
800b768: 2b00 cmp r3, #0
800b76a: d002 beq.n 800b772 <ethernetif_input+0x4a>
{
pbuf_free(p);
800b76c: 68b8 ldr r0, [r7, #8]
800b76e: f004 ff3b bl 80105e8 <pbuf_free>
}
}
UNLOCK_TCPIP_CORE();
800b772: 4804 ldr r0, [pc, #16] ; (800b784 <ethernetif_input+0x5c>)
800b774: f00f fbb7 bl 801aee6 <sys_mutex_unlock>
} while(p!=NULL);
800b778: 68bb ldr r3, [r7, #8]
800b77a: 2b00 cmp r3, #0
800b77c: d1e4 bne.n 800b748 <ethernetif_input+0x20>
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b77e: e7d9 b.n 800b734 <ethernetif_input+0xc>
800b780: 20000588 .word 0x20000588
800b784: 2000be88 .word 0x2000be88
0800b788 <ethernetif_init>:
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t ethernetif_init(struct netif *netif)
{
800b788: b580 push {r7, lr}
800b78a: b082 sub sp, #8
800b78c: af00 add r7, sp, #0
800b78e: 6078 str r0, [r7, #4]
LWIP_ASSERT("netif != NULL", (netif != NULL));
800b790: 687b ldr r3, [r7, #4]
800b792: 2b00 cmp r3, #0
800b794: d106 bne.n 800b7a4 <ethernetif_init+0x1c>
800b796: 4b0e ldr r3, [pc, #56] ; (800b7d0 <ethernetif_init+0x48>)
800b798: f240 222b movw r2, #555 ; 0x22b
800b79c: 490d ldr r1, [pc, #52] ; (800b7d4 <ethernetif_init+0x4c>)
800b79e: 480e ldr r0, [pc, #56] ; (800b7d8 <ethernetif_init+0x50>)
800b7a0: f00f fc38 bl 801b014 <iprintf>
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = "lwip";
#endif /* LWIP_NETIF_HOSTNAME */
netif->name[0] = IFNAME0;
800b7a4: 687b ldr r3, [r7, #4]
800b7a6: 2273 movs r2, #115 ; 0x73
800b7a8: f883 2032 strb.w r2, [r3, #50] ; 0x32
netif->name[1] = IFNAME1;
800b7ac: 687b ldr r3, [r7, #4]
800b7ae: 2274 movs r2, #116 ; 0x74
800b7b0: f883 2033 strb.w r2, [r3, #51] ; 0x33
* is available...) */
#if LWIP_IPV4
#if LWIP_ARP || LWIP_ETHERNET
#if LWIP_ARP
netif->output = etharp_output;
800b7b4: 687b ldr r3, [r7, #4]
800b7b6: 4a09 ldr r2, [pc, #36] ; (800b7dc <ethernetif_init+0x54>)
800b7b8: 615a str r2, [r3, #20]
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif /* LWIP_IPV6 */
netif->linkoutput = low_level_output;
800b7ba: 687b ldr r3, [r7, #4]
800b7bc: 4a08 ldr r2, [pc, #32] ; (800b7e0 <ethernetif_init+0x58>)
800b7be: 619a str r2, [r3, #24]
/* initialize the hardware */
low_level_init(netif);
800b7c0: 6878 ldr r0, [r7, #4]
800b7c2: f7ff fd87 bl 800b2d4 <low_level_init>
return ERR_OK;
800b7c6: 2300 movs r3, #0
}
800b7c8: 4618 mov r0, r3
800b7ca: 3708 adds r7, #8
800b7cc: 46bd mov sp, r7
800b7ce: bd80 pop {r7, pc}
800b7d0: 0801bf78 .word 0x0801bf78
800b7d4: 0801bf94 .word 0x0801bf94
800b7d8: 0801bfa4 .word 0x0801bfa4
800b7dc: 08019045 .word 0x08019045
800b7e0: 0800b485 .word 0x0800b485
0800b7e4 <sys_now>:
* when LWIP_TIMERS == 1 and NO_SYS == 1
* @param None
* @retval Time
*/
u32_t sys_now(void)
{
800b7e4: b580 push {r7, lr}
800b7e6: af00 add r7, sp, #0
return HAL_GetTick();
800b7e8: f7f9 f8d6 bl 8004998 <HAL_GetTick>
800b7ec: 4603 mov r3, r0
}
800b7ee: 4618 mov r0, r3
800b7f0: bd80 pop {r7, pc}
...
0800b7f4 <ethernetif_set_link>:
* @param netif: the network interface
* @retval None
*/
void ethernetif_set_link(void const *argument)
{
800b7f4: b580 push {r7, lr}
800b7f6: b084 sub sp, #16
800b7f8: af00 add r7, sp, #0
800b7fa: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b7fc: 2300 movs r3, #0
800b7fe: 60bb str r3, [r7, #8]
struct link_str *link_arg = (struct link_str *)argument;
800b800: 687b ldr r3, [r7, #4]
800b802: 60fb str r3, [r7, #12]
for(;;)
{
/* Read PHY_BSR*/
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b804: f107 0308 add.w r3, r7, #8
800b808: 461a mov r2, r3
800b80a: 2101 movs r1, #1
800b80c: 4816 ldr r0, [pc, #88] ; (800b868 <ethernetif_set_link+0x74>)
800b80e: f7fb f80c bl 800682a <HAL_ETH_ReadPHYRegister>
regvalue &= PHY_LINKED_STATUS;
800b812: 68bb ldr r3, [r7, #8]
800b814: f003 0304 and.w r3, r3, #4
800b818: 60bb str r3, [r7, #8]
/* Check whether the netif link down and the PHY link is up */
if(!netif_is_link_up(link_arg->netif) && (regvalue))
800b81a: 68fb ldr r3, [r7, #12]
800b81c: 681b ldr r3, [r3, #0]
800b81e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b822: f003 0304 and.w r3, r3, #4
800b826: 2b00 cmp r3, #0
800b828: d108 bne.n 800b83c <ethernetif_set_link+0x48>
800b82a: 68bb ldr r3, [r7, #8]
800b82c: 2b00 cmp r3, #0
800b82e: d005 beq.n 800b83c <ethernetif_set_link+0x48>
{
/* network cable is connected */
netif_set_link_up(link_arg->netif);
800b830: 68fb ldr r3, [r7, #12]
800b832: 681b ldr r3, [r3, #0]
800b834: 4618 mov r0, r3
800b836: f004 fac5 bl 800fdc4 <netif_set_link_up>
800b83a: e011 b.n 800b860 <ethernetif_set_link+0x6c>
}
else if(netif_is_link_up(link_arg->netif) && (!regvalue))
800b83c: 68fb ldr r3, [r7, #12]
800b83e: 681b ldr r3, [r3, #0]
800b840: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b844: 089b lsrs r3, r3, #2
800b846: f003 0301 and.w r3, r3, #1
800b84a: b2db uxtb r3, r3
800b84c: 2b00 cmp r3, #0
800b84e: d007 beq.n 800b860 <ethernetif_set_link+0x6c>
800b850: 68bb ldr r3, [r7, #8]
800b852: 2b00 cmp r3, #0
800b854: d104 bne.n 800b860 <ethernetif_set_link+0x6c>
{
/* network cable is dis-connected */
netif_set_link_down(link_arg->netif);
800b856: 68fb ldr r3, [r7, #12]
800b858: 681b ldr r3, [r3, #0]
800b85a: 4618 mov r0, r3
800b85c: f004 faea bl 800fe34 <netif_set_link_down>
}
/* Suspend thread for 200 ms */
osDelay(200);
800b860: 20c8 movs r0, #200 ; 0xc8
800b862: f000 f916 bl 800ba92 <osDelay>
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b866: e7cd b.n 800b804 <ethernetif_set_link+0x10>
800b868: 2000a670 .word 0x2000a670
0800b86c <ethernetif_update_config>:
* to update low level driver configuration.
* @param netif: The network interface
* @retval None
*/
void ethernetif_update_config(struct netif *netif)
{
800b86c: b580 push {r7, lr}
800b86e: b084 sub sp, #16
800b870: af00 add r7, sp, #0
800b872: 6078 str r0, [r7, #4]
__IO uint32_t tickstart = 0;
800b874: 2300 movs r3, #0
800b876: 60fb str r3, [r7, #12]
uint32_t regvalue = 0;
800b878: 2300 movs r3, #0
800b87a: 60bb str r3, [r7, #8]
if(netif_is_link_up(netif))
800b87c: 687b ldr r3, [r7, #4]
800b87e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b882: 089b lsrs r3, r3, #2
800b884: f003 0301 and.w r3, r3, #1
800b888: b2db uxtb r3, r3
800b88a: 2b00 cmp r3, #0
800b88c: d05d beq.n 800b94a <ethernetif_update_config+0xde>
{
/* Restart the auto-negotiation */
if(heth.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
800b88e: 4b34 ldr r3, [pc, #208] ; (800b960 <ethernetif_update_config+0xf4>)
800b890: 685b ldr r3, [r3, #4]
800b892: 2b00 cmp r3, #0
800b894: d03f beq.n 800b916 <ethernetif_update_config+0xaa>
{
/* Enable Auto-Negotiation */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, PHY_AUTONEGOTIATION);
800b896: f44f 5280 mov.w r2, #4096 ; 0x1000
800b89a: 2100 movs r1, #0
800b89c: 4830 ldr r0, [pc, #192] ; (800b960 <ethernetif_update_config+0xf4>)
800b89e: f7fb f82c bl 80068fa <HAL_ETH_WritePHYRegister>
/* Get tick */
tickstart = HAL_GetTick();
800b8a2: f7f9 f879 bl 8004998 <HAL_GetTick>
800b8a6: 4603 mov r3, r0
800b8a8: 60fb str r3, [r7, #12]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b8aa: f107 0308 add.w r3, r7, #8
800b8ae: 461a mov r2, r3
800b8b0: 2101 movs r1, #1
800b8b2: 482b ldr r0, [pc, #172] ; (800b960 <ethernetif_update_config+0xf4>)
800b8b4: f7fa ffb9 bl 800682a <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout ( 1s ) */
if((HAL_GetTick() - tickstart ) > 1000)
800b8b8: f7f9 f86e bl 8004998 <HAL_GetTick>
800b8bc: 4602 mov r2, r0
800b8be: 68fb ldr r3, [r7, #12]
800b8c0: 1ad3 subs r3, r2, r3
800b8c2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800b8c6: d828 bhi.n 800b91a <ethernetif_update_config+0xae>
{
/* In case of timeout */
goto error;
}
} while (((regvalue & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
800b8c8: 68bb ldr r3, [r7, #8]
800b8ca: f003 0320 and.w r3, r3, #32
800b8ce: 2b00 cmp r3, #0
800b8d0: d0eb beq.n 800b8aa <ethernetif_update_config+0x3e>
/* Read the result of the auto-negotiation */
HAL_ETH_ReadPHYRegister(&heth, PHY_SR, &regvalue);
800b8d2: f107 0308 add.w r3, r7, #8
800b8d6: 461a mov r2, r3
800b8d8: 211f movs r1, #31
800b8da: 4821 ldr r0, [pc, #132] ; (800b960 <ethernetif_update_config+0xf4>)
800b8dc: f7fa ffa5 bl 800682a <HAL_ETH_ReadPHYRegister>
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((regvalue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
800b8e0: 68bb ldr r3, [r7, #8]
800b8e2: f003 0310 and.w r3, r3, #16
800b8e6: 2b00 cmp r3, #0
800b8e8: d004 beq.n 800b8f4 <ethernetif_update_config+0x88>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b8ea: 4b1d ldr r3, [pc, #116] ; (800b960 <ethernetif_update_config+0xf4>)
800b8ec: f44f 6200 mov.w r2, #2048 ; 0x800
800b8f0: 60da str r2, [r3, #12]
800b8f2: e002 b.n 800b8fa <ethernetif_update_config+0x8e>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
800b8f4: 4b1a ldr r3, [pc, #104] ; (800b960 <ethernetif_update_config+0xf4>)
800b8f6: 2200 movs r2, #0
800b8f8: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if(regvalue & PHY_SPEED_STATUS)
800b8fa: 68bb ldr r3, [r7, #8]
800b8fc: f003 0304 and.w r3, r3, #4
800b900: 2b00 cmp r3, #0
800b902: d003 beq.n 800b90c <ethernetif_update_config+0xa0>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_10M;
800b904: 4b16 ldr r3, [pc, #88] ; (800b960 <ethernetif_update_config+0xf4>)
800b906: 2200 movs r2, #0
800b908: 609a str r2, [r3, #8]
800b90a: e016 b.n 800b93a <ethernetif_update_config+0xce>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_100M;
800b90c: 4b14 ldr r3, [pc, #80] ; (800b960 <ethernetif_update_config+0xf4>)
800b90e: f44f 4280 mov.w r2, #16384 ; 0x4000
800b912: 609a str r2, [r3, #8]
800b914: e011 b.n 800b93a <ethernetif_update_config+0xce>
}
}
else /* AutoNegotiation Disable */
{
error :
800b916: bf00 nop
800b918: e000 b.n 800b91c <ethernetif_update_config+0xb0>
goto error;
800b91a: bf00 nop
/* Check parameters */
assert_param(IS_ETH_SPEED(heth.Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth.Init.DuplexMode));
/* Set MAC Speed and Duplex Mode to PHY */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b91c: 4b10 ldr r3, [pc, #64] ; (800b960 <ethernetif_update_config+0xf4>)
800b91e: 68db ldr r3, [r3, #12]
800b920: 08db lsrs r3, r3, #3
800b922: b29a uxth r2, r3
(uint16_t)(heth.Init.Speed >> 1)));
800b924: 4b0e ldr r3, [pc, #56] ; (800b960 <ethernetif_update_config+0xf4>)
800b926: 689b ldr r3, [r3, #8]
800b928: 085b lsrs r3, r3, #1
800b92a: b29b uxth r3, r3
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b92c: 4313 orrs r3, r2
800b92e: b29b uxth r3, r3
800b930: 461a mov r2, r3
800b932: 2100 movs r1, #0
800b934: 480a ldr r0, [pc, #40] ; (800b960 <ethernetif_update_config+0xf4>)
800b936: f7fa ffe0 bl 80068fa <HAL_ETH_WritePHYRegister>
}
/* ETHERNET MAC Re-Configuration */
HAL_ETH_ConfigMAC(&heth, (ETH_MACInitTypeDef *) NULL);
800b93a: 2100 movs r1, #0
800b93c: 4808 ldr r0, [pc, #32] ; (800b960 <ethernetif_update_config+0xf4>)
800b93e: f7fb f8a1 bl 8006a84 <HAL_ETH_ConfigMAC>
/* Restart MAC interface */
HAL_ETH_Start(&heth);
800b942: 4807 ldr r0, [pc, #28] ; (800b960 <ethernetif_update_config+0xf4>)
800b944: f7fb f83f bl 80069c6 <HAL_ETH_Start>
800b948: e002 b.n 800b950 <ethernetif_update_config+0xe4>
}
else
{
/* Stop MAC interface */
HAL_ETH_Stop(&heth);
800b94a: 4805 ldr r0, [pc, #20] ; (800b960 <ethernetif_update_config+0xf4>)
800b94c: f7fb f86a bl 8006a24 <HAL_ETH_Stop>
}
ethernetif_notify_conn_changed(netif);
800b950: 6878 ldr r0, [r7, #4]
800b952: f000 f807 bl 800b964 <ethernetif_notify_conn_changed>
}
800b956: bf00 nop
800b958: 3710 adds r7, #16
800b95a: 46bd mov sp, r7
800b95c: bd80 pop {r7, pc}
800b95e: bf00 nop
800b960: 2000a670 .word 0x2000a670
0800b964 <ethernetif_notify_conn_changed>:
* @brief This function notify user about link status changement.
* @param netif: the network interface
* @retval None
*/
__weak void ethernetif_notify_conn_changed(struct netif *netif)
{
800b964: b480 push {r7}
800b966: b083 sub sp, #12
800b968: af00 add r7, sp, #0
800b96a: 6078 str r0, [r7, #4]
/* NOTE : This is function could be implemented in user file
when the callback is needed,
*/
}
800b96c: bf00 nop
800b96e: 370c adds r7, #12
800b970: 46bd mov sp, r7
800b972: f85d 7b04 ldr.w r7, [sp], #4
800b976: 4770 bx lr
0800b978 <makeFreeRtosPriority>:
extern void xPortSysTickHandler(void);
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
{
800b978: b480 push {r7}
800b97a: b085 sub sp, #20
800b97c: af00 add r7, sp, #0
800b97e: 4603 mov r3, r0
800b980: 80fb strh r3, [r7, #6]
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
800b982: 2300 movs r3, #0
800b984: 60fb str r3, [r7, #12]
if (priority != osPriorityError) {
800b986: f9b7 3006 ldrsh.w r3, [r7, #6]
800b98a: 2b84 cmp r3, #132 ; 0x84
800b98c: d005 beq.n 800b99a <makeFreeRtosPriority+0x22>
fpriority += (priority - osPriorityIdle);
800b98e: f9b7 2006 ldrsh.w r2, [r7, #6]
800b992: 68fb ldr r3, [r7, #12]
800b994: 4413 add r3, r2
800b996: 3303 adds r3, #3
800b998: 60fb str r3, [r7, #12]
}
return fpriority;
800b99a: 68fb ldr r3, [r7, #12]
}
800b99c: 4618 mov r0, r3
800b99e: 3714 adds r7, #20
800b9a0: 46bd mov sp, r7
800b9a2: f85d 7b04 ldr.w r7, [sp], #4
800b9a6: 4770 bx lr
0800b9a8 <inHandlerMode>:
#endif
/* Determine whether we are in thread mode or handler mode. */
static int inHandlerMode (void)
{
800b9a8: b480 push {r7}
800b9aa: b083 sub sp, #12
800b9ac: af00 add r7, sp, #0
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
800b9ae: f3ef 8305 mrs r3, IPSR
800b9b2: 607b str r3, [r7, #4]
return(result);
800b9b4: 687b ldr r3, [r7, #4]
return __get_IPSR() != 0;
800b9b6: 2b00 cmp r3, #0
800b9b8: bf14 ite ne
800b9ba: 2301 movne r3, #1
800b9bc: 2300 moveq r3, #0
800b9be: b2db uxtb r3, r3
}
800b9c0: 4618 mov r0, r3
800b9c2: 370c adds r7, #12
800b9c4: 46bd mov sp, r7
800b9c6: f85d 7b04 ldr.w r7, [sp], #4
800b9ca: 4770 bx lr
0800b9cc <osKernelStart>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval status code that indicates the execution status of the function
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
*/
osStatus osKernelStart (void)
{
800b9cc: b580 push {r7, lr}
800b9ce: af00 add r7, sp, #0
vTaskStartScheduler();
800b9d0: f001 fe1e bl 800d610 <vTaskStartScheduler>
return osOK;
800b9d4: 2300 movs r3, #0
}
800b9d6: 4618 mov r0, r3
800b9d8: bd80 pop {r7, pc}
0800b9da <osKernelSysTick>:
* @param None
* @retval None
* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
*/
uint32_t osKernelSysTick(void)
{
800b9da: b580 push {r7, lr}
800b9dc: af00 add r7, sp, #0
if (inHandlerMode()) {
800b9de: f7ff ffe3 bl 800b9a8 <inHandlerMode>
800b9e2: 4603 mov r3, r0
800b9e4: 2b00 cmp r3, #0
800b9e6: d003 beq.n 800b9f0 <osKernelSysTick+0x16>
return xTaskGetTickCountFromISR();
800b9e8: f001 ff30 bl 800d84c <xTaskGetTickCountFromISR>
800b9ec: 4603 mov r3, r0
800b9ee: e002 b.n 800b9f6 <osKernelSysTick+0x1c>
}
else {
return xTaskGetTickCount();
800b9f0: f001 ff1c bl 800d82c <xTaskGetTickCount>
800b9f4: 4603 mov r3, r0
}
}
800b9f6: 4618 mov r0, r3
800b9f8: bd80 pop {r7, pc}
0800b9fa <osThreadCreate>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval thread ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
*/
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
{
800b9fa: b5f0 push {r4, r5, r6, r7, lr}
800b9fc: b089 sub sp, #36 ; 0x24
800b9fe: af04 add r7, sp, #16
800ba00: 6078 str r0, [r7, #4]
800ba02: 6039 str r1, [r7, #0]
TaskHandle_t handle;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
800ba04: 687b ldr r3, [r7, #4]
800ba06: 695b ldr r3, [r3, #20]
800ba08: 2b00 cmp r3, #0
800ba0a: d020 beq.n 800ba4e <osThreadCreate+0x54>
800ba0c: 687b ldr r3, [r7, #4]
800ba0e: 699b ldr r3, [r3, #24]
800ba10: 2b00 cmp r3, #0
800ba12: d01c beq.n 800ba4e <osThreadCreate+0x54>
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba14: 687b ldr r3, [r7, #4]
800ba16: 685c ldr r4, [r3, #4]
800ba18: 687b ldr r3, [r7, #4]
800ba1a: 681d ldr r5, [r3, #0]
800ba1c: 687b ldr r3, [r7, #4]
800ba1e: 691e ldr r6, [r3, #16]
800ba20: 687b ldr r3, [r7, #4]
800ba22: f9b3 3008 ldrsh.w r3, [r3, #8]
800ba26: 4618 mov r0, r3
800ba28: f7ff ffa6 bl 800b978 <makeFreeRtosPriority>
800ba2c: 4601 mov r1, r0
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
thread_def->buffer, thread_def->controlblock);
800ba2e: 687b ldr r3, [r7, #4]
800ba30: 695b ldr r3, [r3, #20]
800ba32: 687a ldr r2, [r7, #4]
800ba34: 6992 ldr r2, [r2, #24]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba36: 9202 str r2, [sp, #8]
800ba38: 9301 str r3, [sp, #4]
800ba3a: 9100 str r1, [sp, #0]
800ba3c: 683b ldr r3, [r7, #0]
800ba3e: 4632 mov r2, r6
800ba40: 4629 mov r1, r5
800ba42: 4620 mov r0, r4
800ba44: f001 fafb bl 800d03e <xTaskCreateStatic>
800ba48: 4603 mov r3, r0
800ba4a: 60fb str r3, [r7, #12]
800ba4c: e01c b.n 800ba88 <osThreadCreate+0x8e>
}
else {
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba4e: 687b ldr r3, [r7, #4]
800ba50: 685c ldr r4, [r3, #4]
800ba52: 687b ldr r3, [r7, #4]
800ba54: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
800ba56: 687b ldr r3, [r7, #4]
800ba58: 691b ldr r3, [r3, #16]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba5a: b29e uxth r6, r3
800ba5c: 687b ldr r3, [r7, #4]
800ba5e: f9b3 3008 ldrsh.w r3, [r3, #8]
800ba62: 4618 mov r0, r3
800ba64: f7ff ff88 bl 800b978 <makeFreeRtosPriority>
800ba68: 4602 mov r2, r0
800ba6a: f107 030c add.w r3, r7, #12
800ba6e: 9301 str r3, [sp, #4]
800ba70: 9200 str r2, [sp, #0]
800ba72: 683b ldr r3, [r7, #0]
800ba74: 4632 mov r2, r6
800ba76: 4629 mov r1, r5
800ba78: 4620 mov r0, r4
800ba7a: f001 fb40 bl 800d0fe <xTaskCreate>
800ba7e: 4603 mov r3, r0
800ba80: 2b01 cmp r3, #1
800ba82: d001 beq.n 800ba88 <osThreadCreate+0x8e>
&handle) != pdPASS) {
return NULL;
800ba84: 2300 movs r3, #0
800ba86: e000 b.n 800ba8a <osThreadCreate+0x90>
&handle) != pdPASS) {
return NULL;
}
#endif
return handle;
800ba88: 68fb ldr r3, [r7, #12]
}
800ba8a: 4618 mov r0, r3
800ba8c: 3714 adds r7, #20
800ba8e: 46bd mov sp, r7
800ba90: bdf0 pop {r4, r5, r6, r7, pc}
0800ba92 <osDelay>:
* @brief Wait for Timeout (Time Delay)
* @param millisec time delay value
* @retval status code that indicates the execution status of the function.
*/
osStatus osDelay (uint32_t millisec)
{
800ba92: b580 push {r7, lr}
800ba94: b084 sub sp, #16
800ba96: af00 add r7, sp, #0
800ba98: 6078 str r0, [r7, #4]
#if INCLUDE_vTaskDelay
TickType_t ticks = millisec / portTICK_PERIOD_MS;
800ba9a: 687b ldr r3, [r7, #4]
800ba9c: 60fb str r3, [r7, #12]
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
800ba9e: 68fb ldr r3, [r7, #12]
800baa0: 2b00 cmp r3, #0
800baa2: d001 beq.n 800baa8 <osDelay+0x16>
800baa4: 68fb ldr r3, [r7, #12]
800baa6: e000 b.n 800baaa <osDelay+0x18>
800baa8: 2301 movs r3, #1
800baaa: 4618 mov r0, r3
800baac: f001 fd7a bl 800d5a4 <vTaskDelay>
return osOK;
800bab0: 2300 movs r3, #0
#else
(void) millisec;
return osErrorResource;
#endif
}
800bab2: 4618 mov r0, r3
800bab4: 3710 adds r7, #16
800bab6: 46bd mov sp, r7
800bab8: bd80 pop {r7, pc}
0800baba <osMutexCreate>:
* @param mutex_def mutex definition referenced with \ref osMutex.
* @retval mutex ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
*/
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
{
800baba: b580 push {r7, lr}
800babc: b082 sub sp, #8
800babe: af00 add r7, sp, #0
800bac0: 6078 str r0, [r7, #4]
#if ( configUSE_MUTEXES == 1)
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if (mutex_def->controlblock != NULL) {
800bac2: 687b ldr r3, [r7, #4]
800bac4: 685b ldr r3, [r3, #4]
800bac6: 2b00 cmp r3, #0
800bac8: d007 beq.n 800bada <osMutexCreate+0x20>
return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
800baca: 687b ldr r3, [r7, #4]
800bacc: 685b ldr r3, [r3, #4]
800bace: 4619 mov r1, r3
800bad0: 2001 movs r0, #1
800bad2: f000 fc5e bl 800c392 <xQueueCreateMutexStatic>
800bad6: 4603 mov r3, r0
800bad8: e003 b.n 800bae2 <osMutexCreate+0x28>
}
else {
return xSemaphoreCreateMutex();
800bada: 2001 movs r0, #1
800badc: f000 fc41 bl 800c362 <xQueueCreateMutex>
800bae0: 4603 mov r3, r0
return xSemaphoreCreateMutex();
#endif
#else
return NULL;
#endif
}
800bae2: 4618 mov r0, r3
800bae4: 3708 adds r7, #8
800bae6: 46bd mov sp, r7
800bae8: bd80 pop {r7, pc}
...
0800baec <osMutexWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
{
800baec: b580 push {r7, lr}
800baee: b084 sub sp, #16
800baf0: af00 add r7, sp, #0
800baf2: 6078 str r0, [r7, #4]
800baf4: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800baf6: 2300 movs r3, #0
800baf8: 60bb str r3, [r7, #8]
if (mutex_id == NULL) {
800bafa: 687b ldr r3, [r7, #4]
800bafc: 2b00 cmp r3, #0
800bafe: d101 bne.n 800bb04 <osMutexWait+0x18>
return osErrorParameter;
800bb00: 2380 movs r3, #128 ; 0x80
800bb02: e03a b.n 800bb7a <osMutexWait+0x8e>
}
ticks = 0;
800bb04: 2300 movs r3, #0
800bb06: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800bb08: 683b ldr r3, [r7, #0]
800bb0a: f1b3 3fff cmp.w r3, #4294967295
800bb0e: d103 bne.n 800bb18 <osMutexWait+0x2c>
ticks = portMAX_DELAY;
800bb10: f04f 33ff mov.w r3, #4294967295
800bb14: 60fb str r3, [r7, #12]
800bb16: e009 b.n 800bb2c <osMutexWait+0x40>
}
else if (millisec != 0) {
800bb18: 683b ldr r3, [r7, #0]
800bb1a: 2b00 cmp r3, #0
800bb1c: d006 beq.n 800bb2c <osMutexWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800bb1e: 683b ldr r3, [r7, #0]
800bb20: 60fb str r3, [r7, #12]
if (ticks == 0) {
800bb22: 68fb ldr r3, [r7, #12]
800bb24: 2b00 cmp r3, #0
800bb26: d101 bne.n 800bb2c <osMutexWait+0x40>
ticks = 1;
800bb28: 2301 movs r3, #1
800bb2a: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800bb2c: f7ff ff3c bl 800b9a8 <inHandlerMode>
800bb30: 4603 mov r3, r0
800bb32: 2b00 cmp r3, #0
800bb34: d017 beq.n 800bb66 <osMutexWait+0x7a>
if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
800bb36: f107 0308 add.w r3, r7, #8
800bb3a: 461a mov r2, r3
800bb3c: 2100 movs r1, #0
800bb3e: 6878 ldr r0, [r7, #4]
800bb40: f001 f8d2 bl 800cce8 <xQueueReceiveFromISR>
800bb44: 4603 mov r3, r0
800bb46: 2b01 cmp r3, #1
800bb48: d001 beq.n 800bb4e <osMutexWait+0x62>
return osErrorOS;
800bb4a: 23ff movs r3, #255 ; 0xff
800bb4c: e015 b.n 800bb7a <osMutexWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800bb4e: 68bb ldr r3, [r7, #8]
800bb50: 2b00 cmp r3, #0
800bb52: d011 beq.n 800bb78 <osMutexWait+0x8c>
800bb54: 4b0b ldr r3, [pc, #44] ; (800bb84 <osMutexWait+0x98>)
800bb56: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bb5a: 601a str r2, [r3, #0]
800bb5c: f3bf 8f4f dsb sy
800bb60: f3bf 8f6f isb sy
800bb64: e008 b.n 800bb78 <osMutexWait+0x8c>
}
else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
800bb66: 68f9 ldr r1, [r7, #12]
800bb68: 6878 ldr r0, [r7, #4]
800bb6a: f000 ffad bl 800cac8 <xQueueSemaphoreTake>
800bb6e: 4603 mov r3, r0
800bb70: 2b01 cmp r3, #1
800bb72: d001 beq.n 800bb78 <osMutexWait+0x8c>
return osErrorOS;
800bb74: 23ff movs r3, #255 ; 0xff
800bb76: e000 b.n 800bb7a <osMutexWait+0x8e>
}
return osOK;
800bb78: 2300 movs r3, #0
}
800bb7a: 4618 mov r0, r3
800bb7c: 3710 adds r7, #16
800bb7e: 46bd mov sp, r7
800bb80: bd80 pop {r7, pc}
800bb82: bf00 nop
800bb84: e000ed04 .word 0xe000ed04
0800bb88 <osMutexRelease>:
* @param mutex_id mutex ID obtained by \ref osMutexCreate.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexRelease (osMutexId mutex_id)
{
800bb88: b580 push {r7, lr}
800bb8a: b084 sub sp, #16
800bb8c: af00 add r7, sp, #0
800bb8e: 6078 str r0, [r7, #4]
osStatus result = osOK;
800bb90: 2300 movs r3, #0
800bb92: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bb94: 2300 movs r3, #0
800bb96: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bb98: f7ff ff06 bl 800b9a8 <inHandlerMode>
800bb9c: 4603 mov r3, r0
800bb9e: 2b00 cmp r3, #0
800bba0: d016 beq.n 800bbd0 <osMutexRelease+0x48>
if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
800bba2: f107 0308 add.w r3, r7, #8
800bba6: 4619 mov r1, r3
800bba8: 6878 ldr r0, [r7, #4]
800bbaa: f000 fe19 bl 800c7e0 <xQueueGiveFromISR>
800bbae: 4603 mov r3, r0
800bbb0: 2b01 cmp r3, #1
800bbb2: d001 beq.n 800bbb8 <osMutexRelease+0x30>
return osErrorOS;
800bbb4: 23ff movs r3, #255 ; 0xff
800bbb6: e017 b.n 800bbe8 <osMutexRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bbb8: 68bb ldr r3, [r7, #8]
800bbba: 2b00 cmp r3, #0
800bbbc: d013 beq.n 800bbe6 <osMutexRelease+0x5e>
800bbbe: 4b0c ldr r3, [pc, #48] ; (800bbf0 <osMutexRelease+0x68>)
800bbc0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bbc4: 601a str r2, [r3, #0]
800bbc6: f3bf 8f4f dsb sy
800bbca: f3bf 8f6f isb sy
800bbce: e00a b.n 800bbe6 <osMutexRelease+0x5e>
}
else if (xSemaphoreGive(mutex_id) != pdTRUE)
800bbd0: 2300 movs r3, #0
800bbd2: 2200 movs r2, #0
800bbd4: 2100 movs r1, #0
800bbd6: 6878 ldr r0, [r7, #4]
800bbd8: f000 fc64 bl 800c4a4 <xQueueGenericSend>
800bbdc: 4603 mov r3, r0
800bbde: 2b01 cmp r3, #1
800bbe0: d001 beq.n 800bbe6 <osMutexRelease+0x5e>
{
result = osErrorOS;
800bbe2: 23ff movs r3, #255 ; 0xff
800bbe4: 60fb str r3, [r7, #12]
}
return result;
800bbe6: 68fb ldr r3, [r7, #12]
}
800bbe8: 4618 mov r0, r3
800bbea: 3710 adds r7, #16
800bbec: 46bd mov sp, r7
800bbee: bd80 pop {r7, pc}
800bbf0: e000ed04 .word 0xe000ed04
0800bbf4 <osSemaphoreCreate>:
* @param count number of available resources.
* @retval semaphore ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
*/
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
{
800bbf4: b580 push {r7, lr}
800bbf6: b086 sub sp, #24
800bbf8: af02 add r7, sp, #8
800bbfa: 6078 str r0, [r7, #4]
800bbfc: 6039 str r1, [r7, #0]
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
osSemaphoreId sema;
if (semaphore_def->controlblock != NULL){
800bbfe: 687b ldr r3, [r7, #4]
800bc00: 685b ldr r3, [r3, #4]
800bc02: 2b00 cmp r3, #0
800bc04: d017 beq.n 800bc36 <osSemaphoreCreate+0x42>
if (count == 1) {
800bc06: 683b ldr r3, [r7, #0]
800bc08: 2b01 cmp r3, #1
800bc0a: d10b bne.n 800bc24 <osSemaphoreCreate+0x30>
return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
800bc0c: 687b ldr r3, [r7, #4]
800bc0e: 685a ldr r2, [r3, #4]
800bc10: 2303 movs r3, #3
800bc12: 9300 str r3, [sp, #0]
800bc14: 4613 mov r3, r2
800bc16: 2200 movs r2, #0
800bc18: 2100 movs r1, #0
800bc1a: 2001 movs r0, #1
800bc1c: f000 faaa bl 800c174 <xQueueGenericCreateStatic>
800bc20: 4603 mov r3, r0
800bc22: e023 b.n 800bc6c <osSemaphoreCreate+0x78>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
800bc24: 6838 ldr r0, [r7, #0]
800bc26: 6839 ldr r1, [r7, #0]
800bc28: 687b ldr r3, [r7, #4]
800bc2a: 685b ldr r3, [r3, #4]
800bc2c: 461a mov r2, r3
800bc2e: f000 fbcb bl 800c3c8 <xQueueCreateCountingSemaphoreStatic>
800bc32: 4603 mov r3, r0
800bc34: e01a b.n 800bc6c <osSemaphoreCreate+0x78>
return NULL;
#endif
}
}
else {
if (count == 1) {
800bc36: 683b ldr r3, [r7, #0]
800bc38: 2b01 cmp r3, #1
800bc3a: d110 bne.n 800bc5e <osSemaphoreCreate+0x6a>
vSemaphoreCreateBinary(sema);
800bc3c: 2203 movs r2, #3
800bc3e: 2100 movs r1, #0
800bc40: 2001 movs r0, #1
800bc42: f000 fb14 bl 800c26e <xQueueGenericCreate>
800bc46: 60f8 str r0, [r7, #12]
800bc48: 68fb ldr r3, [r7, #12]
800bc4a: 2b00 cmp r3, #0
800bc4c: d005 beq.n 800bc5a <osSemaphoreCreate+0x66>
800bc4e: 2300 movs r3, #0
800bc50: 2200 movs r2, #0
800bc52: 2100 movs r1, #0
800bc54: 68f8 ldr r0, [r7, #12]
800bc56: f000 fc25 bl 800c4a4 <xQueueGenericSend>
return sema;
800bc5a: 68fb ldr r3, [r7, #12]
800bc5c: e006 b.n 800bc6c <osSemaphoreCreate+0x78>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCounting(count, count);
800bc5e: 683b ldr r3, [r7, #0]
800bc60: 683a ldr r2, [r7, #0]
800bc62: 4611 mov r1, r2
800bc64: 4618 mov r0, r3
800bc66: f000 fbe8 bl 800c43a <xQueueCreateCountingSemaphore>
800bc6a: 4603 mov r3, r0
#else
return NULL;
#endif
}
#endif
}
800bc6c: 4618 mov r0, r3
800bc6e: 3710 adds r7, #16
800bc70: 46bd mov sp, r7
800bc72: bd80 pop {r7, pc}
0800bc74 <osSemaphoreWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval number of available tokens, or -1 in case of incorrect parameters.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
*/
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
{
800bc74: b580 push {r7, lr}
800bc76: b084 sub sp, #16
800bc78: af00 add r7, sp, #0
800bc7a: 6078 str r0, [r7, #4]
800bc7c: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800bc7e: 2300 movs r3, #0
800bc80: 60bb str r3, [r7, #8]
if (semaphore_id == NULL) {
800bc82: 687b ldr r3, [r7, #4]
800bc84: 2b00 cmp r3, #0
800bc86: d101 bne.n 800bc8c <osSemaphoreWait+0x18>
return osErrorParameter;
800bc88: 2380 movs r3, #128 ; 0x80
800bc8a: e03a b.n 800bd02 <osSemaphoreWait+0x8e>
}
ticks = 0;
800bc8c: 2300 movs r3, #0
800bc8e: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800bc90: 683b ldr r3, [r7, #0]
800bc92: f1b3 3fff cmp.w r3, #4294967295
800bc96: d103 bne.n 800bca0 <osSemaphoreWait+0x2c>
ticks = portMAX_DELAY;
800bc98: f04f 33ff mov.w r3, #4294967295
800bc9c: 60fb str r3, [r7, #12]
800bc9e: e009 b.n 800bcb4 <osSemaphoreWait+0x40>
}
else if (millisec != 0) {
800bca0: 683b ldr r3, [r7, #0]
800bca2: 2b00 cmp r3, #0
800bca4: d006 beq.n 800bcb4 <osSemaphoreWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800bca6: 683b ldr r3, [r7, #0]
800bca8: 60fb str r3, [r7, #12]
if (ticks == 0) {
800bcaa: 68fb ldr r3, [r7, #12]
800bcac: 2b00 cmp r3, #0
800bcae: d101 bne.n 800bcb4 <osSemaphoreWait+0x40>
ticks = 1;
800bcb0: 2301 movs r3, #1
800bcb2: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800bcb4: f7ff fe78 bl 800b9a8 <inHandlerMode>
800bcb8: 4603 mov r3, r0
800bcba: 2b00 cmp r3, #0
800bcbc: d017 beq.n 800bcee <osSemaphoreWait+0x7a>
if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bcbe: f107 0308 add.w r3, r7, #8
800bcc2: 461a mov r2, r3
800bcc4: 2100 movs r1, #0
800bcc6: 6878 ldr r0, [r7, #4]
800bcc8: f001 f80e bl 800cce8 <xQueueReceiveFromISR>
800bccc: 4603 mov r3, r0
800bcce: 2b01 cmp r3, #1
800bcd0: d001 beq.n 800bcd6 <osSemaphoreWait+0x62>
return osErrorOS;
800bcd2: 23ff movs r3, #255 ; 0xff
800bcd4: e015 b.n 800bd02 <osSemaphoreWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800bcd6: 68bb ldr r3, [r7, #8]
800bcd8: 2b00 cmp r3, #0
800bcda: d011 beq.n 800bd00 <osSemaphoreWait+0x8c>
800bcdc: 4b0b ldr r3, [pc, #44] ; (800bd0c <osSemaphoreWait+0x98>)
800bcde: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bce2: 601a str r2, [r3, #0]
800bce4: f3bf 8f4f dsb sy
800bce8: f3bf 8f6f isb sy
800bcec: e008 b.n 800bd00 <osSemaphoreWait+0x8c>
}
else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
800bcee: 68f9 ldr r1, [r7, #12]
800bcf0: 6878 ldr r0, [r7, #4]
800bcf2: f000 fee9 bl 800cac8 <xQueueSemaphoreTake>
800bcf6: 4603 mov r3, r0
800bcf8: 2b01 cmp r3, #1
800bcfa: d001 beq.n 800bd00 <osSemaphoreWait+0x8c>
return osErrorOS;
800bcfc: 23ff movs r3, #255 ; 0xff
800bcfe: e000 b.n 800bd02 <osSemaphoreWait+0x8e>
}
return osOK;
800bd00: 2300 movs r3, #0
}
800bd02: 4618 mov r0, r3
800bd04: 3710 adds r7, #16
800bd06: 46bd mov sp, r7
800bd08: bd80 pop {r7, pc}
800bd0a: bf00 nop
800bd0c: e000ed04 .word 0xe000ed04
0800bd10 <osSemaphoreRelease>:
* @param semaphore_id semaphore object referenced with \ref osSemaphore.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
{
800bd10: b580 push {r7, lr}
800bd12: b084 sub sp, #16
800bd14: af00 add r7, sp, #0
800bd16: 6078 str r0, [r7, #4]
osStatus result = osOK;
800bd18: 2300 movs r3, #0
800bd1a: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bd1c: 2300 movs r3, #0
800bd1e: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bd20: f7ff fe42 bl 800b9a8 <inHandlerMode>
800bd24: 4603 mov r3, r0
800bd26: 2b00 cmp r3, #0
800bd28: d016 beq.n 800bd58 <osSemaphoreRelease+0x48>
if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bd2a: f107 0308 add.w r3, r7, #8
800bd2e: 4619 mov r1, r3
800bd30: 6878 ldr r0, [r7, #4]
800bd32: f000 fd55 bl 800c7e0 <xQueueGiveFromISR>
800bd36: 4603 mov r3, r0
800bd38: 2b01 cmp r3, #1
800bd3a: d001 beq.n 800bd40 <osSemaphoreRelease+0x30>
return osErrorOS;
800bd3c: 23ff movs r3, #255 ; 0xff
800bd3e: e017 b.n 800bd70 <osSemaphoreRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bd40: 68bb ldr r3, [r7, #8]
800bd42: 2b00 cmp r3, #0
800bd44: d013 beq.n 800bd6e <osSemaphoreRelease+0x5e>
800bd46: 4b0c ldr r3, [pc, #48] ; (800bd78 <osSemaphoreRelease+0x68>)
800bd48: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bd4c: 601a str r2, [r3, #0]
800bd4e: f3bf 8f4f dsb sy
800bd52: f3bf 8f6f isb sy
800bd56: e00a b.n 800bd6e <osSemaphoreRelease+0x5e>
}
else {
if (xSemaphoreGive(semaphore_id) != pdTRUE) {
800bd58: 2300 movs r3, #0
800bd5a: 2200 movs r2, #0
800bd5c: 2100 movs r1, #0
800bd5e: 6878 ldr r0, [r7, #4]
800bd60: f000 fba0 bl 800c4a4 <xQueueGenericSend>
800bd64: 4603 mov r3, r0
800bd66: 2b01 cmp r3, #1
800bd68: d001 beq.n 800bd6e <osSemaphoreRelease+0x5e>
result = osErrorOS;
800bd6a: 23ff movs r3, #255 ; 0xff
800bd6c: 60fb str r3, [r7, #12]
}
}
return result;
800bd6e: 68fb ldr r3, [r7, #12]
}
800bd70: 4618 mov r0, r3
800bd72: 3710 adds r7, #16
800bd74: 46bd mov sp, r7
800bd76: bd80 pop {r7, pc}
800bd78: e000ed04 .word 0xe000ed04
0800bd7c <osMessageCreate>:
* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
* @retval message queue ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
*/
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
{
800bd7c: b590 push {r4, r7, lr}
800bd7e: b085 sub sp, #20
800bd80: af02 add r7, sp, #8
800bd82: 6078 str r0, [r7, #4]
800bd84: 6039 str r1, [r7, #0]
(void) thread_id;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
800bd86: 687b ldr r3, [r7, #4]
800bd88: 689b ldr r3, [r3, #8]
800bd8a: 2b00 cmp r3, #0
800bd8c: d012 beq.n 800bdb4 <osMessageCreate+0x38>
800bd8e: 687b ldr r3, [r7, #4]
800bd90: 68db ldr r3, [r3, #12]
800bd92: 2b00 cmp r3, #0
800bd94: d00e beq.n 800bdb4 <osMessageCreate+0x38>
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
800bd96: 687b ldr r3, [r7, #4]
800bd98: 6818 ldr r0, [r3, #0]
800bd9a: 687b ldr r3, [r7, #4]
800bd9c: 6859 ldr r1, [r3, #4]
800bd9e: 687b ldr r3, [r7, #4]
800bda0: 689a ldr r2, [r3, #8]
800bda2: 687b ldr r3, [r7, #4]
800bda4: 68dc ldr r4, [r3, #12]
800bda6: 2300 movs r3, #0
800bda8: 9300 str r3, [sp, #0]
800bdaa: 4623 mov r3, r4
800bdac: f000 f9e2 bl 800c174 <xQueueGenericCreateStatic>
800bdb0: 4603 mov r3, r0
800bdb2: e008 b.n 800bdc6 <osMessageCreate+0x4a>
}
else {
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
800bdb4: 687b ldr r3, [r7, #4]
800bdb6: 6818 ldr r0, [r3, #0]
800bdb8: 687b ldr r3, [r7, #4]
800bdba: 685b ldr r3, [r3, #4]
800bdbc: 2200 movs r2, #0
800bdbe: 4619 mov r1, r3
800bdc0: f000 fa55 bl 800c26e <xQueueGenericCreate>
800bdc4: 4603 mov r3, r0
#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
#else
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
#endif
}
800bdc6: 4618 mov r0, r3
800bdc8: 370c adds r7, #12
800bdca: 46bd mov sp, r7
800bdcc: bd90 pop {r4, r7, pc}
...
0800bdd0 <osMessagePut>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
*/
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
{
800bdd0: b580 push {r7, lr}
800bdd2: b086 sub sp, #24
800bdd4: af00 add r7, sp, #0
800bdd6: 60f8 str r0, [r7, #12]
800bdd8: 60b9 str r1, [r7, #8]
800bdda: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken = pdFALSE;
800bddc: 2300 movs r3, #0
800bdde: 613b str r3, [r7, #16]
TickType_t ticks;
ticks = millisec / portTICK_PERIOD_MS;
800bde0: 687b ldr r3, [r7, #4]
800bde2: 617b str r3, [r7, #20]
if (ticks == 0) {
800bde4: 697b ldr r3, [r7, #20]
800bde6: 2b00 cmp r3, #0
800bde8: d101 bne.n 800bdee <osMessagePut+0x1e>
ticks = 1;
800bdea: 2301 movs r3, #1
800bdec: 617b str r3, [r7, #20]
}
if (inHandlerMode()) {
800bdee: f7ff fddb bl 800b9a8 <inHandlerMode>
800bdf2: 4603 mov r3, r0
800bdf4: 2b00 cmp r3, #0
800bdf6: d018 beq.n 800be2a <osMessagePut+0x5a>
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
800bdf8: f107 0210 add.w r2, r7, #16
800bdfc: f107 0108 add.w r1, r7, #8
800be00: 2300 movs r3, #0
800be02: 68f8 ldr r0, [r7, #12]
800be04: f000 fc50 bl 800c6a8 <xQueueGenericSendFromISR>
800be08: 4603 mov r3, r0
800be0a: 2b01 cmp r3, #1
800be0c: d001 beq.n 800be12 <osMessagePut+0x42>
return osErrorOS;
800be0e: 23ff movs r3, #255 ; 0xff
800be10: e018 b.n 800be44 <osMessagePut+0x74>
}
portEND_SWITCHING_ISR(taskWoken);
800be12: 693b ldr r3, [r7, #16]
800be14: 2b00 cmp r3, #0
800be16: d014 beq.n 800be42 <osMessagePut+0x72>
800be18: 4b0c ldr r3, [pc, #48] ; (800be4c <osMessagePut+0x7c>)
800be1a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800be1e: 601a str r2, [r3, #0]
800be20: f3bf 8f4f dsb sy
800be24: f3bf 8f6f isb sy
800be28: e00b b.n 800be42 <osMessagePut+0x72>
}
else {
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
800be2a: f107 0108 add.w r1, r7, #8
800be2e: 2300 movs r3, #0
800be30: 697a ldr r2, [r7, #20]
800be32: 68f8 ldr r0, [r7, #12]
800be34: f000 fb36 bl 800c4a4 <xQueueGenericSend>
800be38: 4603 mov r3, r0
800be3a: 2b01 cmp r3, #1
800be3c: d001 beq.n 800be42 <osMessagePut+0x72>
return osErrorOS;
800be3e: 23ff movs r3, #255 ; 0xff
800be40: e000 b.n 800be44 <osMessagePut+0x74>
}
}
return osOK;
800be42: 2300 movs r3, #0
}
800be44: 4618 mov r0, r3
800be46: 3718 adds r7, #24
800be48: 46bd mov sp, r7
800be4a: bd80 pop {r7, pc}
800be4c: e000ed04 .word 0xe000ed04
0800be50 <osMessageGet>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval event information that includes status code.
* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
*/
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
{
800be50: b590 push {r4, r7, lr}
800be52: b08b sub sp, #44 ; 0x2c
800be54: af00 add r7, sp, #0
800be56: 60f8 str r0, [r7, #12]
800be58: 60b9 str r1, [r7, #8]
800be5a: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken;
TickType_t ticks;
osEvent event;
event.def.message_id = queue_id;
800be5c: 68bb ldr r3, [r7, #8]
800be5e: 61fb str r3, [r7, #28]
event.value.v = 0;
800be60: 2300 movs r3, #0
800be62: 61bb str r3, [r7, #24]
if (queue_id == NULL) {
800be64: 68bb ldr r3, [r7, #8]
800be66: 2b00 cmp r3, #0
800be68: d10a bne.n 800be80 <osMessageGet+0x30>
event.status = osErrorParameter;
800be6a: 2380 movs r3, #128 ; 0x80
800be6c: 617b str r3, [r7, #20]
return event;
800be6e: 68fb ldr r3, [r7, #12]
800be70: 461c mov r4, r3
800be72: f107 0314 add.w r3, r7, #20
800be76: e893 0007 ldmia.w r3, {r0, r1, r2}
800be7a: e884 0007 stmia.w r4, {r0, r1, r2}
800be7e: e054 b.n 800bf2a <osMessageGet+0xda>
}
taskWoken = pdFALSE;
800be80: 2300 movs r3, #0
800be82: 623b str r3, [r7, #32]
ticks = 0;
800be84: 2300 movs r3, #0
800be86: 627b str r3, [r7, #36] ; 0x24
if (millisec == osWaitForever) {
800be88: 687b ldr r3, [r7, #4]
800be8a: f1b3 3fff cmp.w r3, #4294967295
800be8e: d103 bne.n 800be98 <osMessageGet+0x48>
ticks = portMAX_DELAY;
800be90: f04f 33ff mov.w r3, #4294967295
800be94: 627b str r3, [r7, #36] ; 0x24
800be96: e009 b.n 800beac <osMessageGet+0x5c>
}
else if (millisec != 0) {
800be98: 687b ldr r3, [r7, #4]
800be9a: 2b00 cmp r3, #0
800be9c: d006 beq.n 800beac <osMessageGet+0x5c>
ticks = millisec / portTICK_PERIOD_MS;
800be9e: 687b ldr r3, [r7, #4]
800bea0: 627b str r3, [r7, #36] ; 0x24
if (ticks == 0) {
800bea2: 6a7b ldr r3, [r7, #36] ; 0x24
800bea4: 2b00 cmp r3, #0
800bea6: d101 bne.n 800beac <osMessageGet+0x5c>
ticks = 1;
800bea8: 2301 movs r3, #1
800beaa: 627b str r3, [r7, #36] ; 0x24
}
}
if (inHandlerMode()) {
800beac: f7ff fd7c bl 800b9a8 <inHandlerMode>
800beb0: 4603 mov r3, r0
800beb2: 2b00 cmp r3, #0
800beb4: d01c beq.n 800bef0 <osMessageGet+0xa0>
if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
800beb6: f107 0220 add.w r2, r7, #32
800beba: f107 0314 add.w r3, r7, #20
800bebe: 3304 adds r3, #4
800bec0: 4619 mov r1, r3
800bec2: 68b8 ldr r0, [r7, #8]
800bec4: f000 ff10 bl 800cce8 <xQueueReceiveFromISR>
800bec8: 4603 mov r3, r0
800beca: 2b01 cmp r3, #1
800becc: d102 bne.n 800bed4 <osMessageGet+0x84>
/* We have mail */
event.status = osEventMessage;
800bece: 2310 movs r3, #16
800bed0: 617b str r3, [r7, #20]
800bed2: e001 b.n 800bed8 <osMessageGet+0x88>
}
else {
event.status = osOK;
800bed4: 2300 movs r3, #0
800bed6: 617b str r3, [r7, #20]
}
portEND_SWITCHING_ISR(taskWoken);
800bed8: 6a3b ldr r3, [r7, #32]
800beda: 2b00 cmp r3, #0
800bedc: d01d beq.n 800bf1a <osMessageGet+0xca>
800bede: 4b15 ldr r3, [pc, #84] ; (800bf34 <osMessageGet+0xe4>)
800bee0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bee4: 601a str r2, [r3, #0]
800bee6: f3bf 8f4f dsb sy
800beea: f3bf 8f6f isb sy
800beee: e014 b.n 800bf1a <osMessageGet+0xca>
}
else {
if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
800bef0: f107 0314 add.w r3, r7, #20
800bef4: 3304 adds r3, #4
800bef6: 6a7a ldr r2, [r7, #36] ; 0x24
800bef8: 4619 mov r1, r3
800befa: 68b8 ldr r0, [r7, #8]
800befc: f000 fd02 bl 800c904 <xQueueReceive>
800bf00: 4603 mov r3, r0
800bf02: 2b01 cmp r3, #1
800bf04: d102 bne.n 800bf0c <osMessageGet+0xbc>
/* We have mail */
event.status = osEventMessage;
800bf06: 2310 movs r3, #16
800bf08: 617b str r3, [r7, #20]
800bf0a: e006 b.n 800bf1a <osMessageGet+0xca>
}
else {
event.status = (ticks == 0) ? osOK : osEventTimeout;
800bf0c: 6a7b ldr r3, [r7, #36] ; 0x24
800bf0e: 2b00 cmp r3, #0
800bf10: d101 bne.n 800bf16 <osMessageGet+0xc6>
800bf12: 2300 movs r3, #0
800bf14: e000 b.n 800bf18 <osMessageGet+0xc8>
800bf16: 2340 movs r3, #64 ; 0x40
800bf18: 617b str r3, [r7, #20]
}
}
return event;
800bf1a: 68fb ldr r3, [r7, #12]
800bf1c: 461c mov r4, r3
800bf1e: f107 0314 add.w r3, r7, #20
800bf22: e893 0007 ldmia.w r3, {r0, r1, r2}
800bf26: e884 0007 stmia.w r4, {r0, r1, r2}
}
800bf2a: 68f8 ldr r0, [r7, #12]
800bf2c: 372c adds r7, #44 ; 0x2c
800bf2e: 46bd mov sp, r7
800bf30: bd90 pop {r4, r7, pc}
800bf32: bf00 nop
800bf34: e000ed04 .word 0xe000ed04
0800bf38 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
800bf38: b480 push {r7}
800bf3a: b083 sub sp, #12
800bf3c: af00 add r7, sp, #0
800bf3e: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf40: 687b ldr r3, [r7, #4]
800bf42: f103 0208 add.w r2, r3, #8
800bf46: 687b ldr r3, [r7, #4]
800bf48: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
800bf4a: 687b ldr r3, [r7, #4]
800bf4c: f04f 32ff mov.w r2, #4294967295
800bf50: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf52: 687b ldr r3, [r7, #4]
800bf54: f103 0208 add.w r2, r3, #8
800bf58: 687b ldr r3, [r7, #4]
800bf5a: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf5c: 687b ldr r3, [r7, #4]
800bf5e: f103 0208 add.w r2, r3, #8
800bf62: 687b ldr r3, [r7, #4]
800bf64: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
800bf66: 687b ldr r3, [r7, #4]
800bf68: 2200 movs r2, #0
800bf6a: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
800bf6c: bf00 nop
800bf6e: 370c adds r7, #12
800bf70: 46bd mov sp, r7
800bf72: f85d 7b04 ldr.w r7, [sp], #4
800bf76: 4770 bx lr
0800bf78 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
800bf78: b480 push {r7}
800bf7a: b083 sub sp, #12
800bf7c: af00 add r7, sp, #0
800bf7e: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
800bf80: 687b ldr r3, [r7, #4]
800bf82: 2200 movs r2, #0
800bf84: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
800bf86: bf00 nop
800bf88: 370c adds r7, #12
800bf8a: 46bd mov sp, r7
800bf8c: f85d 7b04 ldr.w r7, [sp], #4
800bf90: 4770 bx lr
0800bf92 <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800bf92: b480 push {r7}
800bf94: b085 sub sp, #20
800bf96: af00 add r7, sp, #0
800bf98: 6078 str r0, [r7, #4]
800bf9a: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
800bf9c: 687b ldr r3, [r7, #4]
800bf9e: 685b ldr r3, [r3, #4]
800bfa0: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
800bfa2: 683b ldr r3, [r7, #0]
800bfa4: 68fa ldr r2, [r7, #12]
800bfa6: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
800bfa8: 68fb ldr r3, [r7, #12]
800bfaa: 689a ldr r2, [r3, #8]
800bfac: 683b ldr r3, [r7, #0]
800bfae: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
800bfb0: 68fb ldr r3, [r7, #12]
800bfb2: 689b ldr r3, [r3, #8]
800bfb4: 683a ldr r2, [r7, #0]
800bfb6: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
800bfb8: 68fb ldr r3, [r7, #12]
800bfba: 683a ldr r2, [r7, #0]
800bfbc: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
800bfbe: 683b ldr r3, [r7, #0]
800bfc0: 687a ldr r2, [r7, #4]
800bfc2: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800bfc4: 687b ldr r3, [r7, #4]
800bfc6: 681b ldr r3, [r3, #0]
800bfc8: 1c5a adds r2, r3, #1
800bfca: 687b ldr r3, [r7, #4]
800bfcc: 601a str r2, [r3, #0]
}
800bfce: bf00 nop
800bfd0: 3714 adds r7, #20
800bfd2: 46bd mov sp, r7
800bfd4: f85d 7b04 ldr.w r7, [sp], #4
800bfd8: 4770 bx lr
0800bfda <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800bfda: b480 push {r7}
800bfdc: b085 sub sp, #20
800bfde: af00 add r7, sp, #0
800bfe0: 6078 str r0, [r7, #4]
800bfe2: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
800bfe4: 683b ldr r3, [r7, #0]
800bfe6: 681b ldr r3, [r3, #0]
800bfe8: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
800bfea: 68bb ldr r3, [r7, #8]
800bfec: f1b3 3fff cmp.w r3, #4294967295
800bff0: d103 bne.n 800bffa <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
800bff2: 687b ldr r3, [r7, #4]
800bff4: 691b ldr r3, [r3, #16]
800bff6: 60fb str r3, [r7, #12]
800bff8: e00c b.n 800c014 <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
800bffa: 687b ldr r3, [r7, #4]
800bffc: 3308 adds r3, #8
800bffe: 60fb str r3, [r7, #12]
800c000: e002 b.n 800c008 <vListInsert+0x2e>
800c002: 68fb ldr r3, [r7, #12]
800c004: 685b ldr r3, [r3, #4]
800c006: 60fb str r3, [r7, #12]
800c008: 68fb ldr r3, [r7, #12]
800c00a: 685b ldr r3, [r3, #4]
800c00c: 681b ldr r3, [r3, #0]
800c00e: 68ba ldr r2, [r7, #8]
800c010: 429a cmp r2, r3
800c012: d2f6 bcs.n 800c002 <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
800c014: 68fb ldr r3, [r7, #12]
800c016: 685a ldr r2, [r3, #4]
800c018: 683b ldr r3, [r7, #0]
800c01a: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
800c01c: 683b ldr r3, [r7, #0]
800c01e: 685b ldr r3, [r3, #4]
800c020: 683a ldr r2, [r7, #0]
800c022: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
800c024: 683b ldr r3, [r7, #0]
800c026: 68fa ldr r2, [r7, #12]
800c028: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
800c02a: 68fb ldr r3, [r7, #12]
800c02c: 683a ldr r2, [r7, #0]
800c02e: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
800c030: 683b ldr r3, [r7, #0]
800c032: 687a ldr r2, [r7, #4]
800c034: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800c036: 687b ldr r3, [r7, #4]
800c038: 681b ldr r3, [r3, #0]
800c03a: 1c5a adds r2, r3, #1
800c03c: 687b ldr r3, [r7, #4]
800c03e: 601a str r2, [r3, #0]
}
800c040: bf00 nop
800c042: 3714 adds r7, #20
800c044: 46bd mov sp, r7
800c046: f85d 7b04 ldr.w r7, [sp], #4
800c04a: 4770 bx lr
0800c04c <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
800c04c: b480 push {r7}
800c04e: b085 sub sp, #20
800c050: af00 add r7, sp, #0
800c052: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
800c054: 687b ldr r3, [r7, #4]
800c056: 691b ldr r3, [r3, #16]
800c058: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
800c05a: 687b ldr r3, [r7, #4]
800c05c: 685b ldr r3, [r3, #4]
800c05e: 687a ldr r2, [r7, #4]
800c060: 6892 ldr r2, [r2, #8]
800c062: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
800c064: 687b ldr r3, [r7, #4]
800c066: 689b ldr r3, [r3, #8]
800c068: 687a ldr r2, [r7, #4]
800c06a: 6852 ldr r2, [r2, #4]
800c06c: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
800c06e: 68fb ldr r3, [r7, #12]
800c070: 685b ldr r3, [r3, #4]
800c072: 687a ldr r2, [r7, #4]
800c074: 429a cmp r2, r3
800c076: d103 bne.n 800c080 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
800c078: 687b ldr r3, [r7, #4]
800c07a: 689a ldr r2, [r3, #8]
800c07c: 68fb ldr r3, [r7, #12]
800c07e: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
800c080: 687b ldr r3, [r7, #4]
800c082: 2200 movs r2, #0
800c084: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
800c086: 68fb ldr r3, [r7, #12]
800c088: 681b ldr r3, [r3, #0]
800c08a: 1e5a subs r2, r3, #1
800c08c: 68fb ldr r3, [r7, #12]
800c08e: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
800c090: 68fb ldr r3, [r7, #12]
800c092: 681b ldr r3, [r3, #0]
}
800c094: 4618 mov r0, r3
800c096: 3714 adds r7, #20
800c098: 46bd mov sp, r7
800c09a: f85d 7b04 ldr.w r7, [sp], #4
800c09e: 4770 bx lr
0800c0a0 <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
800c0a0: b580 push {r7, lr}
800c0a2: b084 sub sp, #16
800c0a4: af00 add r7, sp, #0
800c0a6: 6078 str r0, [r7, #4]
800c0a8: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
800c0aa: 687b ldr r3, [r7, #4]
800c0ac: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
800c0ae: 68fb ldr r3, [r7, #12]
800c0b0: 2b00 cmp r3, #0
800c0b2: d10b bne.n 800c0cc <xQueueGenericReset+0x2c>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
800c0b4: f04f 0350 mov.w r3, #80 ; 0x50
800c0b8: b672 cpsid i
800c0ba: f383 8811 msr BASEPRI, r3
800c0be: f3bf 8f6f isb sy
800c0c2: f3bf 8f4f dsb sy
800c0c6: b662 cpsie i
800c0c8: 60bb str r3, [r7, #8]
800c0ca: e7fe b.n 800c0ca <xQueueGenericReset+0x2a>
taskENTER_CRITICAL();
800c0cc: f002 fa34 bl 800e538 <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c0d0: 68fb ldr r3, [r7, #12]
800c0d2: 681a ldr r2, [r3, #0]
800c0d4: 68fb ldr r3, [r7, #12]
800c0d6: 6bdb ldr r3, [r3, #60] ; 0x3c
800c0d8: 68f9 ldr r1, [r7, #12]
800c0da: 6c09 ldr r1, [r1, #64] ; 0x40
800c0dc: fb01 f303 mul.w r3, r1, r3
800c0e0: 441a add r2, r3
800c0e2: 68fb ldr r3, [r7, #12]
800c0e4: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
800c0e6: 68fb ldr r3, [r7, #12]
800c0e8: 2200 movs r2, #0
800c0ea: 639a str r2, [r3, #56] ; 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
800c0ec: 68fb ldr r3, [r7, #12]
800c0ee: 681a ldr r2, [r3, #0]
800c0f0: 68fb ldr r3, [r7, #12]
800c0f2: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c0f4: 68fb ldr r3, [r7, #12]
800c0f6: 681a ldr r2, [r3, #0]
800c0f8: 68fb ldr r3, [r7, #12]
800c0fa: 6bdb ldr r3, [r3, #60] ; 0x3c
800c0fc: 3b01 subs r3, #1
800c0fe: 68f9 ldr r1, [r7, #12]
800c100: 6c09 ldr r1, [r1, #64] ; 0x40
800c102: fb01 f303 mul.w r3, r1, r3
800c106: 441a add r2, r3
800c108: 68fb ldr r3, [r7, #12]
800c10a: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
800c10c: 68fb ldr r3, [r7, #12]
800c10e: 22ff movs r2, #255 ; 0xff
800c110: f883 2044 strb.w r2, [r3, #68] ; 0x44
pxQueue->cTxLock = queueUNLOCKED;
800c114: 68fb ldr r3, [r7, #12]
800c116: 22ff movs r2, #255 ; 0xff
800c118: f883 2045 strb.w r2, [r3, #69] ; 0x45
if( xNewQueue == pdFALSE )
800c11c: 683b ldr r3, [r7, #0]
800c11e: 2b00 cmp r3, #0
800c120: d114 bne.n 800c14c <xQueueGenericReset+0xac>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c122: 68fb ldr r3, [r7, #12]
800c124: 691b ldr r3, [r3, #16]
800c126: 2b00 cmp r3, #0
800c128: d01a beq.n 800c160 <xQueueGenericReset+0xc0>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c12a: 68fb ldr r3, [r7, #12]
800c12c: 3310 adds r3, #16
800c12e: 4618 mov r0, r3
800c130: f001 fd00 bl 800db34 <xTaskRemoveFromEventList>
800c134: 4603 mov r3, r0
800c136: 2b00 cmp r3, #0
800c138: d012 beq.n 800c160 <xQueueGenericReset+0xc0>
{
queueYIELD_IF_USING_PREEMPTION();
800c13a: 4b0d ldr r3, [pc, #52] ; (800c170 <xQueueGenericReset+0xd0>)
800c13c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c140: 601a str r2, [r3, #0]
800c142: f3bf 8f4f dsb sy
800c146: f3bf 8f6f isb sy
800c14a: e009 b.n 800c160 <xQueueGenericReset+0xc0>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
800c14c: 68fb ldr r3, [r7, #12]
800c14e: 3310 adds r3, #16
800c150: 4618 mov r0, r3
800c152: f7ff fef1 bl 800bf38 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
800c156: 68fb ldr r3, [r7, #12]
800c158: 3324 adds r3, #36 ; 0x24
800c15a: 4618 mov r0, r3
800c15c: f7ff feec bl 800bf38 <vListInitialise>
}
}
taskEXIT_CRITICAL();
800c160: f002 fa1c bl 800e59c <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
800c164: 2301 movs r3, #1
}
800c166: 4618 mov r0, r3
800c168: 3710 adds r7, #16
800c16a: 46bd mov sp, r7
800c16c: bd80 pop {r7, pc}
800c16e: bf00 nop
800c170: e000ed04 .word 0xe000ed04
0800c174 <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
800c174: b580 push {r7, lr}
800c176: b08e sub sp, #56 ; 0x38
800c178: af02 add r7, sp, #8
800c17a: 60f8 str r0, [r7, #12]
800c17c: 60b9 str r1, [r7, #8]
800c17e: 607a str r2, [r7, #4]
800c180: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c182: 68fb ldr r3, [r7, #12]
800c184: 2b00 cmp r3, #0
800c186: d10b bne.n 800c1a0 <xQueueGenericCreateStatic+0x2c>
800c188: f04f 0350 mov.w r3, #80 ; 0x50
800c18c: b672 cpsid i
800c18e: f383 8811 msr BASEPRI, r3
800c192: f3bf 8f6f isb sy
800c196: f3bf 8f4f dsb sy
800c19a: b662 cpsie i
800c19c: 62bb str r3, [r7, #40] ; 0x28
800c19e: e7fe b.n 800c19e <xQueueGenericCreateStatic+0x2a>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
800c1a0: 683b ldr r3, [r7, #0]
800c1a2: 2b00 cmp r3, #0
800c1a4: d10b bne.n 800c1be <xQueueGenericCreateStatic+0x4a>
800c1a6: f04f 0350 mov.w r3, #80 ; 0x50
800c1aa: b672 cpsid i
800c1ac: f383 8811 msr BASEPRI, r3
800c1b0: f3bf 8f6f isb sy
800c1b4: f3bf 8f4f dsb sy
800c1b8: b662 cpsie i
800c1ba: 627b str r3, [r7, #36] ; 0x24
800c1bc: e7fe b.n 800c1bc <xQueueGenericCreateStatic+0x48>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
800c1be: 687b ldr r3, [r7, #4]
800c1c0: 2b00 cmp r3, #0
800c1c2: d002 beq.n 800c1ca <xQueueGenericCreateStatic+0x56>
800c1c4: 68bb ldr r3, [r7, #8]
800c1c6: 2b00 cmp r3, #0
800c1c8: d001 beq.n 800c1ce <xQueueGenericCreateStatic+0x5a>
800c1ca: 2301 movs r3, #1
800c1cc: e000 b.n 800c1d0 <xQueueGenericCreateStatic+0x5c>
800c1ce: 2300 movs r3, #0
800c1d0: 2b00 cmp r3, #0
800c1d2: d10b bne.n 800c1ec <xQueueGenericCreateStatic+0x78>
800c1d4: f04f 0350 mov.w r3, #80 ; 0x50
800c1d8: b672 cpsid i
800c1da: f383 8811 msr BASEPRI, r3
800c1de: f3bf 8f6f isb sy
800c1e2: f3bf 8f4f dsb sy
800c1e6: b662 cpsie i
800c1e8: 623b str r3, [r7, #32]
800c1ea: e7fe b.n 800c1ea <xQueueGenericCreateStatic+0x76>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
800c1ec: 687b ldr r3, [r7, #4]
800c1ee: 2b00 cmp r3, #0
800c1f0: d102 bne.n 800c1f8 <xQueueGenericCreateStatic+0x84>
800c1f2: 68bb ldr r3, [r7, #8]
800c1f4: 2b00 cmp r3, #0
800c1f6: d101 bne.n 800c1fc <xQueueGenericCreateStatic+0x88>
800c1f8: 2301 movs r3, #1
800c1fa: e000 b.n 800c1fe <xQueueGenericCreateStatic+0x8a>
800c1fc: 2300 movs r3, #0
800c1fe: 2b00 cmp r3, #0
800c200: d10b bne.n 800c21a <xQueueGenericCreateStatic+0xa6>
800c202: f04f 0350 mov.w r3, #80 ; 0x50
800c206: b672 cpsid i
800c208: f383 8811 msr BASEPRI, r3
800c20c: f3bf 8f6f isb sy
800c210: f3bf 8f4f dsb sy
800c214: b662 cpsie i
800c216: 61fb str r3, [r7, #28]
800c218: e7fe b.n 800c218 <xQueueGenericCreateStatic+0xa4>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
800c21a: 2348 movs r3, #72 ; 0x48
800c21c: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
800c21e: 697b ldr r3, [r7, #20]
800c220: 2b48 cmp r3, #72 ; 0x48
800c222: d00b beq.n 800c23c <xQueueGenericCreateStatic+0xc8>
800c224: f04f 0350 mov.w r3, #80 ; 0x50
800c228: b672 cpsid i
800c22a: f383 8811 msr BASEPRI, r3
800c22e: f3bf 8f6f isb sy
800c232: f3bf 8f4f dsb sy
800c236: b662 cpsie i
800c238: 61bb str r3, [r7, #24]
800c23a: e7fe b.n 800c23a <xQueueGenericCreateStatic+0xc6>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
800c23c: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800c23e: 683b ldr r3, [r7, #0]
800c240: 62fb str r3, [r7, #44] ; 0x2c
if( pxNewQueue != NULL )
800c242: 6afb ldr r3, [r7, #44] ; 0x2c
800c244: 2b00 cmp r3, #0
800c246: d00d beq.n 800c264 <xQueueGenericCreateStatic+0xf0>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
800c248: 6afb ldr r3, [r7, #44] ; 0x2c
800c24a: 2201 movs r2, #1
800c24c: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c250: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
800c254: 6afb ldr r3, [r7, #44] ; 0x2c
800c256: 9300 str r3, [sp, #0]
800c258: 4613 mov r3, r2
800c25a: 687a ldr r2, [r7, #4]
800c25c: 68b9 ldr r1, [r7, #8]
800c25e: 68f8 ldr r0, [r7, #12]
800c260: f000 f846 bl 800c2f0 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c264: 6afb ldr r3, [r7, #44] ; 0x2c
}
800c266: 4618 mov r0, r3
800c268: 3730 adds r7, #48 ; 0x30
800c26a: 46bd mov sp, r7
800c26c: bd80 pop {r7, pc}
0800c26e <xQueueGenericCreate>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
{
800c26e: b580 push {r7, lr}
800c270: b08a sub sp, #40 ; 0x28
800c272: af02 add r7, sp, #8
800c274: 60f8 str r0, [r7, #12]
800c276: 60b9 str r1, [r7, #8]
800c278: 4613 mov r3, r2
800c27a: 71fb strb r3, [r7, #7]
Queue_t *pxNewQueue;
size_t xQueueSizeInBytes;
uint8_t *pucQueueStorage;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c27c: 68fb ldr r3, [r7, #12]
800c27e: 2b00 cmp r3, #0
800c280: d10b bne.n 800c29a <xQueueGenericCreate+0x2c>
800c282: f04f 0350 mov.w r3, #80 ; 0x50
800c286: b672 cpsid i
800c288: f383 8811 msr BASEPRI, r3
800c28c: f3bf 8f6f isb sy
800c290: f3bf 8f4f dsb sy
800c294: b662 cpsie i
800c296: 613b str r3, [r7, #16]
800c298: e7fe b.n 800c298 <xQueueGenericCreate+0x2a>
if( uxItemSize == ( UBaseType_t ) 0 )
800c29a: 68bb ldr r3, [r7, #8]
800c29c: 2b00 cmp r3, #0
800c29e: d102 bne.n 800c2a6 <xQueueGenericCreate+0x38>
{
/* There is not going to be a queue storage area. */
xQueueSizeInBytes = ( size_t ) 0;
800c2a0: 2300 movs r3, #0
800c2a2: 61fb str r3, [r7, #28]
800c2a4: e004 b.n 800c2b0 <xQueueGenericCreate+0x42>
}
else
{
/* Allocate enough space to hold the maximum number of items that
can be in the queue at any time. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800c2a6: 68fb ldr r3, [r7, #12]
800c2a8: 68ba ldr r2, [r7, #8]
800c2aa: fb02 f303 mul.w r3, r2, r3
800c2ae: 61fb str r3, [r7, #28]
alignment requirements of the Queue_t structure - which in this case
is an int8_t *. Therefore, whenever the stack alignment requirements
are greater than or equal to the pointer to char requirements the cast
is safe. In other cases alignment requirements are not strict (one or
two bytes). */
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
800c2b0: 69fb ldr r3, [r7, #28]
800c2b2: 3348 adds r3, #72 ; 0x48
800c2b4: 4618 mov r0, r3
800c2b6: f002 fa61 bl 800e77c <pvPortMalloc>
800c2ba: 61b8 str r0, [r7, #24]
if( pxNewQueue != NULL )
800c2bc: 69bb ldr r3, [r7, #24]
800c2be: 2b00 cmp r3, #0
800c2c0: d011 beq.n 800c2e6 <xQueueGenericCreate+0x78>
{
/* Jump past the queue structure to find the location of the queue
storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
800c2c2: 69bb ldr r3, [r7, #24]
800c2c4: 617b str r3, [r7, #20]
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c2c6: 697b ldr r3, [r7, #20]
800c2c8: 3348 adds r3, #72 ; 0x48
800c2ca: 617b str r3, [r7, #20]
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
/* Queues can be created either statically or dynamically, so
note this task was created dynamically in case it is later
deleted. */
pxNewQueue->ucStaticallyAllocated = pdFALSE;
800c2cc: 69bb ldr r3, [r7, #24]
800c2ce: 2200 movs r2, #0
800c2d0: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c2d4: 79fa ldrb r2, [r7, #7]
800c2d6: 69bb ldr r3, [r7, #24]
800c2d8: 9300 str r3, [sp, #0]
800c2da: 4613 mov r3, r2
800c2dc: 697a ldr r2, [r7, #20]
800c2de: 68b9 ldr r1, [r7, #8]
800c2e0: 68f8 ldr r0, [r7, #12]
800c2e2: f000 f805 bl 800c2f0 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c2e6: 69bb ldr r3, [r7, #24]
}
800c2e8: 4618 mov r0, r3
800c2ea: 3720 adds r7, #32
800c2ec: 46bd mov sp, r7
800c2ee: bd80 pop {r7, pc}
0800c2f0 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
800c2f0: b580 push {r7, lr}
800c2f2: b084 sub sp, #16
800c2f4: af00 add r7, sp, #0
800c2f6: 60f8 str r0, [r7, #12]
800c2f8: 60b9 str r1, [r7, #8]
800c2fa: 607a str r2, [r7, #4]
800c2fc: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
800c2fe: 68bb ldr r3, [r7, #8]
800c300: 2b00 cmp r3, #0
800c302: d103 bne.n 800c30c <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
800c304: 69bb ldr r3, [r7, #24]
800c306: 69ba ldr r2, [r7, #24]
800c308: 601a str r2, [r3, #0]
800c30a: e002 b.n 800c312 <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
800c30c: 69bb ldr r3, [r7, #24]
800c30e: 687a ldr r2, [r7, #4]
800c310: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
800c312: 69bb ldr r3, [r7, #24]
800c314: 68fa ldr r2, [r7, #12]
800c316: 63da str r2, [r3, #60] ; 0x3c
pxNewQueue->uxItemSize = uxItemSize;
800c318: 69bb ldr r3, [r7, #24]
800c31a: 68ba ldr r2, [r7, #8]
800c31c: 641a str r2, [r3, #64] ; 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
800c31e: 2101 movs r1, #1
800c320: 69b8 ldr r0, [r7, #24]
800c322: f7ff febd bl 800c0a0 <xQueueGenericReset>
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
800c326: bf00 nop
800c328: 3710 adds r7, #16
800c32a: 46bd mov sp, r7
800c32c: bd80 pop {r7, pc}
0800c32e <prvInitialiseMutex>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static void prvInitialiseMutex( Queue_t *pxNewQueue )
{
800c32e: b580 push {r7, lr}
800c330: b082 sub sp, #8
800c332: af00 add r7, sp, #0
800c334: 6078 str r0, [r7, #4]
if( pxNewQueue != NULL )
800c336: 687b ldr r3, [r7, #4]
800c338: 2b00 cmp r3, #0
800c33a: d00e beq.n 800c35a <prvInitialiseMutex+0x2c>
{
/* The queue create function will set all the queue structure members
correctly for a generic queue, but this function is creating a
mutex. Overwrite those members that need to be set differently -
in particular the information required for priority inheritance. */
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
800c33c: 687b ldr r3, [r7, #4]
800c33e: 2200 movs r2, #0
800c340: 609a str r2, [r3, #8]
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
800c342: 687b ldr r3, [r7, #4]
800c344: 2200 movs r2, #0
800c346: 601a str r2, [r3, #0]
/* In case this is a recursive mutex. */
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
800c348: 687b ldr r3, [r7, #4]
800c34a: 2200 movs r2, #0
800c34c: 60da str r2, [r3, #12]
traceCREATE_MUTEX( pxNewQueue );
/* Start with the semaphore in the expected state. */
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
800c34e: 2300 movs r3, #0
800c350: 2200 movs r2, #0
800c352: 2100 movs r1, #0
800c354: 6878 ldr r0, [r7, #4]
800c356: f000 f8a5 bl 800c4a4 <xQueueGenericSend>
}
else
{
traceCREATE_MUTEX_FAILED();
}
}
800c35a: bf00 nop
800c35c: 3708 adds r7, #8
800c35e: 46bd mov sp, r7
800c360: bd80 pop {r7, pc}
0800c362 <xQueueCreateMutex>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
800c362: b580 push {r7, lr}
800c364: b086 sub sp, #24
800c366: af00 add r7, sp, #0
800c368: 4603 mov r3, r0
800c36a: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c36c: 2301 movs r3, #1
800c36e: 617b str r3, [r7, #20]
800c370: 2300 movs r3, #0
800c372: 613b str r3, [r7, #16]
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
800c374: 79fb ldrb r3, [r7, #7]
800c376: 461a mov r2, r3
800c378: 6939 ldr r1, [r7, #16]
800c37a: 6978 ldr r0, [r7, #20]
800c37c: f7ff ff77 bl 800c26e <xQueueGenericCreate>
800c380: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c382: 68f8 ldr r0, [r7, #12]
800c384: f7ff ffd3 bl 800c32e <prvInitialiseMutex>
return xNewQueue;
800c388: 68fb ldr r3, [r7, #12]
}
800c38a: 4618 mov r0, r3
800c38c: 3718 adds r7, #24
800c38e: 46bd mov sp, r7
800c390: bd80 pop {r7, pc}
0800c392 <xQueueCreateMutexStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
{
800c392: b580 push {r7, lr}
800c394: b088 sub sp, #32
800c396: af02 add r7, sp, #8
800c398: 4603 mov r3, r0
800c39a: 6039 str r1, [r7, #0]
800c39c: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c39e: 2301 movs r3, #1
800c3a0: 617b str r3, [r7, #20]
800c3a2: 2300 movs r3, #0
800c3a4: 613b str r3, [r7, #16]
/* Prevent compiler warnings about unused parameters if
configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
800c3a6: 79fb ldrb r3, [r7, #7]
800c3a8: 9300 str r3, [sp, #0]
800c3aa: 683b ldr r3, [r7, #0]
800c3ac: 2200 movs r2, #0
800c3ae: 6939 ldr r1, [r7, #16]
800c3b0: 6978 ldr r0, [r7, #20]
800c3b2: f7ff fedf bl 800c174 <xQueueGenericCreateStatic>
800c3b6: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c3b8: 68f8 ldr r0, [r7, #12]
800c3ba: f7ff ffb8 bl 800c32e <prvInitialiseMutex>
return xNewQueue;
800c3be: 68fb ldr r3, [r7, #12]
}
800c3c0: 4618 mov r0, r3
800c3c2: 3718 adds r7, #24
800c3c4: 46bd mov sp, r7
800c3c6: bd80 pop {r7, pc}
0800c3c8 <xQueueCreateCountingSemaphoreStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
{
800c3c8: b580 push {r7, lr}
800c3ca: b08a sub sp, #40 ; 0x28
800c3cc: af02 add r7, sp, #8
800c3ce: 60f8 str r0, [r7, #12]
800c3d0: 60b9 str r1, [r7, #8]
800c3d2: 607a str r2, [r7, #4]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c3d4: 68fb ldr r3, [r7, #12]
800c3d6: 2b00 cmp r3, #0
800c3d8: d10b bne.n 800c3f2 <xQueueCreateCountingSemaphoreStatic+0x2a>
800c3da: f04f 0350 mov.w r3, #80 ; 0x50
800c3de: b672 cpsid i
800c3e0: f383 8811 msr BASEPRI, r3
800c3e4: f3bf 8f6f isb sy
800c3e8: f3bf 8f4f dsb sy
800c3ec: b662 cpsie i
800c3ee: 61bb str r3, [r7, #24]
800c3f0: e7fe b.n 800c3f0 <xQueueCreateCountingSemaphoreStatic+0x28>
configASSERT( uxInitialCount <= uxMaxCount );
800c3f2: 68ba ldr r2, [r7, #8]
800c3f4: 68fb ldr r3, [r7, #12]
800c3f6: 429a cmp r2, r3
800c3f8: d90b bls.n 800c412 <xQueueCreateCountingSemaphoreStatic+0x4a>
800c3fa: f04f 0350 mov.w r3, #80 ; 0x50
800c3fe: b672 cpsid i
800c400: f383 8811 msr BASEPRI, r3
800c404: f3bf 8f6f isb sy
800c408: f3bf 8f4f dsb sy
800c40c: b662 cpsie i
800c40e: 617b str r3, [r7, #20]
800c410: e7fe b.n 800c410 <xQueueCreateCountingSemaphoreStatic+0x48>
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c412: 2302 movs r3, #2
800c414: 9300 str r3, [sp, #0]
800c416: 687b ldr r3, [r7, #4]
800c418: 2200 movs r2, #0
800c41a: 2100 movs r1, #0
800c41c: 68f8 ldr r0, [r7, #12]
800c41e: f7ff fea9 bl 800c174 <xQueueGenericCreateStatic>
800c422: 61f8 str r0, [r7, #28]
if( xHandle != NULL )
800c424: 69fb ldr r3, [r7, #28]
800c426: 2b00 cmp r3, #0
800c428: d002 beq.n 800c430 <xQueueCreateCountingSemaphoreStatic+0x68>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c42a: 69fb ldr r3, [r7, #28]
800c42c: 68ba ldr r2, [r7, #8]
800c42e: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c430: 69fb ldr r3, [r7, #28]
}
800c432: 4618 mov r0, r3
800c434: 3720 adds r7, #32
800c436: 46bd mov sp, r7
800c438: bd80 pop {r7, pc}
0800c43a <xQueueCreateCountingSemaphore>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
{
800c43a: b580 push {r7, lr}
800c43c: b086 sub sp, #24
800c43e: af00 add r7, sp, #0
800c440: 6078 str r0, [r7, #4]
800c442: 6039 str r1, [r7, #0]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c444: 687b ldr r3, [r7, #4]
800c446: 2b00 cmp r3, #0
800c448: d10b bne.n 800c462 <xQueueCreateCountingSemaphore+0x28>
800c44a: f04f 0350 mov.w r3, #80 ; 0x50
800c44e: b672 cpsid i
800c450: f383 8811 msr BASEPRI, r3
800c454: f3bf 8f6f isb sy
800c458: f3bf 8f4f dsb sy
800c45c: b662 cpsie i
800c45e: 613b str r3, [r7, #16]
800c460: e7fe b.n 800c460 <xQueueCreateCountingSemaphore+0x26>
configASSERT( uxInitialCount <= uxMaxCount );
800c462: 683a ldr r2, [r7, #0]
800c464: 687b ldr r3, [r7, #4]
800c466: 429a cmp r2, r3
800c468: d90b bls.n 800c482 <xQueueCreateCountingSemaphore+0x48>
800c46a: f04f 0350 mov.w r3, #80 ; 0x50
800c46e: b672 cpsid i
800c470: f383 8811 msr BASEPRI, r3
800c474: f3bf 8f6f isb sy
800c478: f3bf 8f4f dsb sy
800c47c: b662 cpsie i
800c47e: 60fb str r3, [r7, #12]
800c480: e7fe b.n 800c480 <xQueueCreateCountingSemaphore+0x46>
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c482: 2202 movs r2, #2
800c484: 2100 movs r1, #0
800c486: 6878 ldr r0, [r7, #4]
800c488: f7ff fef1 bl 800c26e <xQueueGenericCreate>
800c48c: 6178 str r0, [r7, #20]
if( xHandle != NULL )
800c48e: 697b ldr r3, [r7, #20]
800c490: 2b00 cmp r3, #0
800c492: d002 beq.n 800c49a <xQueueCreateCountingSemaphore+0x60>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c494: 697b ldr r3, [r7, #20]
800c496: 683a ldr r2, [r7, #0]
800c498: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c49a: 697b ldr r3, [r7, #20]
}
800c49c: 4618 mov r0, r3
800c49e: 3718 adds r7, #24
800c4a0: 46bd mov sp, r7
800c4a2: bd80 pop {r7, pc}
0800c4a4 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
800c4a4: b580 push {r7, lr}
800c4a6: b08e sub sp, #56 ; 0x38
800c4a8: af00 add r7, sp, #0
800c4aa: 60f8 str r0, [r7, #12]
800c4ac: 60b9 str r1, [r7, #8]
800c4ae: 607a str r2, [r7, #4]
800c4b0: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
800c4b2: 2300 movs r3, #0
800c4b4: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c4b6: 68fb ldr r3, [r7, #12]
800c4b8: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c4ba: 6b3b ldr r3, [r7, #48] ; 0x30
800c4bc: 2b00 cmp r3, #0
800c4be: d10b bne.n 800c4d8 <xQueueGenericSend+0x34>
800c4c0: f04f 0350 mov.w r3, #80 ; 0x50
800c4c4: b672 cpsid i
800c4c6: f383 8811 msr BASEPRI, r3
800c4ca: f3bf 8f6f isb sy
800c4ce: f3bf 8f4f dsb sy
800c4d2: b662 cpsie i
800c4d4: 62bb str r3, [r7, #40] ; 0x28
800c4d6: e7fe b.n 800c4d6 <xQueueGenericSend+0x32>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c4d8: 68bb ldr r3, [r7, #8]
800c4da: 2b00 cmp r3, #0
800c4dc: d103 bne.n 800c4e6 <xQueueGenericSend+0x42>
800c4de: 6b3b ldr r3, [r7, #48] ; 0x30
800c4e0: 6c1b ldr r3, [r3, #64] ; 0x40
800c4e2: 2b00 cmp r3, #0
800c4e4: d101 bne.n 800c4ea <xQueueGenericSend+0x46>
800c4e6: 2301 movs r3, #1
800c4e8: e000 b.n 800c4ec <xQueueGenericSend+0x48>
800c4ea: 2300 movs r3, #0
800c4ec: 2b00 cmp r3, #0
800c4ee: d10b bne.n 800c508 <xQueueGenericSend+0x64>
800c4f0: f04f 0350 mov.w r3, #80 ; 0x50
800c4f4: b672 cpsid i
800c4f6: f383 8811 msr BASEPRI, r3
800c4fa: f3bf 8f6f isb sy
800c4fe: f3bf 8f4f dsb sy
800c502: b662 cpsie i
800c504: 627b str r3, [r7, #36] ; 0x24
800c506: e7fe b.n 800c506 <xQueueGenericSend+0x62>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c508: 683b ldr r3, [r7, #0]
800c50a: 2b02 cmp r3, #2
800c50c: d103 bne.n 800c516 <xQueueGenericSend+0x72>
800c50e: 6b3b ldr r3, [r7, #48] ; 0x30
800c510: 6bdb ldr r3, [r3, #60] ; 0x3c
800c512: 2b01 cmp r3, #1
800c514: d101 bne.n 800c51a <xQueueGenericSend+0x76>
800c516: 2301 movs r3, #1
800c518: e000 b.n 800c51c <xQueueGenericSend+0x78>
800c51a: 2300 movs r3, #0
800c51c: 2b00 cmp r3, #0
800c51e: d10b bne.n 800c538 <xQueueGenericSend+0x94>
800c520: f04f 0350 mov.w r3, #80 ; 0x50
800c524: b672 cpsid i
800c526: f383 8811 msr BASEPRI, r3
800c52a: f3bf 8f6f isb sy
800c52e: f3bf 8f4f dsb sy
800c532: b662 cpsie i
800c534: 623b str r3, [r7, #32]
800c536: e7fe b.n 800c536 <xQueueGenericSend+0x92>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c538: f001 fcbc bl 800deb4 <xTaskGetSchedulerState>
800c53c: 4603 mov r3, r0
800c53e: 2b00 cmp r3, #0
800c540: d102 bne.n 800c548 <xQueueGenericSend+0xa4>
800c542: 687b ldr r3, [r7, #4]
800c544: 2b00 cmp r3, #0
800c546: d101 bne.n 800c54c <xQueueGenericSend+0xa8>
800c548: 2301 movs r3, #1
800c54a: e000 b.n 800c54e <xQueueGenericSend+0xaa>
800c54c: 2300 movs r3, #0
800c54e: 2b00 cmp r3, #0
800c550: d10b bne.n 800c56a <xQueueGenericSend+0xc6>
800c552: f04f 0350 mov.w r3, #80 ; 0x50
800c556: b672 cpsid i
800c558: f383 8811 msr BASEPRI, r3
800c55c: f3bf 8f6f isb sy
800c560: f3bf 8f4f dsb sy
800c564: b662 cpsie i
800c566: 61fb str r3, [r7, #28]
800c568: e7fe b.n 800c568 <xQueueGenericSend+0xc4>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c56a: f001 ffe5 bl 800e538 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c56e: 6b3b ldr r3, [r7, #48] ; 0x30
800c570: 6b9a ldr r2, [r3, #56] ; 0x38
800c572: 6b3b ldr r3, [r7, #48] ; 0x30
800c574: 6bdb ldr r3, [r3, #60] ; 0x3c
800c576: 429a cmp r2, r3
800c578: d302 bcc.n 800c580 <xQueueGenericSend+0xdc>
800c57a: 683b ldr r3, [r7, #0]
800c57c: 2b02 cmp r3, #2
800c57e: d129 bne.n 800c5d4 <xQueueGenericSend+0x130>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c580: 683a ldr r2, [r7, #0]
800c582: 68b9 ldr r1, [r7, #8]
800c584: 6b38 ldr r0, [r7, #48] ; 0x30
800c586: f000 fc4a bl 800ce1e <prvCopyDataToQueue>
800c58a: 62f8 str r0, [r7, #44] ; 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c58c: 6b3b ldr r3, [r7, #48] ; 0x30
800c58e: 6a5b ldr r3, [r3, #36] ; 0x24
800c590: 2b00 cmp r3, #0
800c592: d010 beq.n 800c5b6 <xQueueGenericSend+0x112>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c594: 6b3b ldr r3, [r7, #48] ; 0x30
800c596: 3324 adds r3, #36 ; 0x24
800c598: 4618 mov r0, r3
800c59a: f001 facb bl 800db34 <xTaskRemoveFromEventList>
800c59e: 4603 mov r3, r0
800c5a0: 2b00 cmp r3, #0
800c5a2: d013 beq.n 800c5cc <xQueueGenericSend+0x128>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
800c5a4: 4b3f ldr r3, [pc, #252] ; (800c6a4 <xQueueGenericSend+0x200>)
800c5a6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c5aa: 601a str r2, [r3, #0]
800c5ac: f3bf 8f4f dsb sy
800c5b0: f3bf 8f6f isb sy
800c5b4: e00a b.n 800c5cc <xQueueGenericSend+0x128>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800c5b6: 6afb ldr r3, [r7, #44] ; 0x2c
800c5b8: 2b00 cmp r3, #0
800c5ba: d007 beq.n 800c5cc <xQueueGenericSend+0x128>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
800c5bc: 4b39 ldr r3, [pc, #228] ; (800c6a4 <xQueueGenericSend+0x200>)
800c5be: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c5c2: 601a str r2, [r3, #0]
800c5c4: f3bf 8f4f dsb sy
800c5c8: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
800c5cc: f001 ffe6 bl 800e59c <vPortExitCritical>
return pdPASS;
800c5d0: 2301 movs r3, #1
800c5d2: e063 b.n 800c69c <xQueueGenericSend+0x1f8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c5d4: 687b ldr r3, [r7, #4]
800c5d6: 2b00 cmp r3, #0
800c5d8: d103 bne.n 800c5e2 <xQueueGenericSend+0x13e>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c5da: f001 ffdf bl 800e59c <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c5de: 2300 movs r3, #0
800c5e0: e05c b.n 800c69c <xQueueGenericSend+0x1f8>
}
else if( xEntryTimeSet == pdFALSE )
800c5e2: 6b7b ldr r3, [r7, #52] ; 0x34
800c5e4: 2b00 cmp r3, #0
800c5e6: d106 bne.n 800c5f6 <xQueueGenericSend+0x152>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800c5e8: f107 0314 add.w r3, r7, #20
800c5ec: 4618 mov r0, r3
800c5ee: f001 fb05 bl 800dbfc <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800c5f2: 2301 movs r3, #1
800c5f4: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800c5f6: f001 ffd1 bl 800e59c <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800c5fa: f001 f86b bl 800d6d4 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800c5fe: f001 ff9b bl 800e538 <vPortEnterCritical>
800c602: 6b3b ldr r3, [r7, #48] ; 0x30
800c604: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800c608: b25b sxtb r3, r3
800c60a: f1b3 3fff cmp.w r3, #4294967295
800c60e: d103 bne.n 800c618 <xQueueGenericSend+0x174>
800c610: 6b3b ldr r3, [r7, #48] ; 0x30
800c612: 2200 movs r2, #0
800c614: f883 2044 strb.w r2, [r3, #68] ; 0x44
800c618: 6b3b ldr r3, [r7, #48] ; 0x30
800c61a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c61e: b25b sxtb r3, r3
800c620: f1b3 3fff cmp.w r3, #4294967295
800c624: d103 bne.n 800c62e <xQueueGenericSend+0x18a>
800c626: 6b3b ldr r3, [r7, #48] ; 0x30
800c628: 2200 movs r2, #0
800c62a: f883 2045 strb.w r2, [r3, #69] ; 0x45
800c62e: f001 ffb5 bl 800e59c <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800c632: 1d3a adds r2, r7, #4
800c634: f107 0314 add.w r3, r7, #20
800c638: 4611 mov r1, r2
800c63a: 4618 mov r0, r3
800c63c: f001 faf4 bl 800dc28 <xTaskCheckForTimeOut>
800c640: 4603 mov r3, r0
800c642: 2b00 cmp r3, #0
800c644: d124 bne.n 800c690 <xQueueGenericSend+0x1ec>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
800c646: 6b38 ldr r0, [r7, #48] ; 0x30
800c648: f000 fce1 bl 800d00e <prvIsQueueFull>
800c64c: 4603 mov r3, r0
800c64e: 2b00 cmp r3, #0
800c650: d018 beq.n 800c684 <xQueueGenericSend+0x1e0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
800c652: 6b3b ldr r3, [r7, #48] ; 0x30
800c654: 3310 adds r3, #16
800c656: 687a ldr r2, [r7, #4]
800c658: 4611 mov r1, r2
800c65a: 4618 mov r0, r3
800c65c: f001 fa44 bl 800dae8 <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
800c660: 6b38 ldr r0, [r7, #48] ; 0x30
800c662: f000 fc6c bl 800cf3e <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
800c666: f001 f843 bl 800d6f0 <xTaskResumeAll>
800c66a: 4603 mov r3, r0
800c66c: 2b00 cmp r3, #0
800c66e: f47f af7c bne.w 800c56a <xQueueGenericSend+0xc6>
{
portYIELD_WITHIN_API();
800c672: 4b0c ldr r3, [pc, #48] ; (800c6a4 <xQueueGenericSend+0x200>)
800c674: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c678: 601a str r2, [r3, #0]
800c67a: f3bf 8f4f dsb sy
800c67e: f3bf 8f6f isb sy
800c682: e772 b.n 800c56a <xQueueGenericSend+0xc6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
800c684: 6b38 ldr r0, [r7, #48] ; 0x30
800c686: f000 fc5a bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800c68a: f001 f831 bl 800d6f0 <xTaskResumeAll>
800c68e: e76c b.n 800c56a <xQueueGenericSend+0xc6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
800c690: 6b38 ldr r0, [r7, #48] ; 0x30
800c692: f000 fc54 bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800c696: f001 f82b bl 800d6f0 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c69a: 2300 movs r3, #0
}
} /*lint -restore */
}
800c69c: 4618 mov r0, r3
800c69e: 3738 adds r7, #56 ; 0x38
800c6a0: 46bd mov sp, r7
800c6a2: bd80 pop {r7, pc}
800c6a4: e000ed04 .word 0xe000ed04
0800c6a8 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
800c6a8: b580 push {r7, lr}
800c6aa: b08e sub sp, #56 ; 0x38
800c6ac: af00 add r7, sp, #0
800c6ae: 60f8 str r0, [r7, #12]
800c6b0: 60b9 str r1, [r7, #8]
800c6b2: 607a str r2, [r7, #4]
800c6b4: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c6b6: 68fb ldr r3, [r7, #12]
800c6b8: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c6ba: 6b3b ldr r3, [r7, #48] ; 0x30
800c6bc: 2b00 cmp r3, #0
800c6be: d10b bne.n 800c6d8 <xQueueGenericSendFromISR+0x30>
800c6c0: f04f 0350 mov.w r3, #80 ; 0x50
800c6c4: b672 cpsid i
800c6c6: f383 8811 msr BASEPRI, r3
800c6ca: f3bf 8f6f isb sy
800c6ce: f3bf 8f4f dsb sy
800c6d2: b662 cpsie i
800c6d4: 627b str r3, [r7, #36] ; 0x24
800c6d6: e7fe b.n 800c6d6 <xQueueGenericSendFromISR+0x2e>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c6d8: 68bb ldr r3, [r7, #8]
800c6da: 2b00 cmp r3, #0
800c6dc: d103 bne.n 800c6e6 <xQueueGenericSendFromISR+0x3e>
800c6de: 6b3b ldr r3, [r7, #48] ; 0x30
800c6e0: 6c1b ldr r3, [r3, #64] ; 0x40
800c6e2: 2b00 cmp r3, #0
800c6e4: d101 bne.n 800c6ea <xQueueGenericSendFromISR+0x42>
800c6e6: 2301 movs r3, #1
800c6e8: e000 b.n 800c6ec <xQueueGenericSendFromISR+0x44>
800c6ea: 2300 movs r3, #0
800c6ec: 2b00 cmp r3, #0
800c6ee: d10b bne.n 800c708 <xQueueGenericSendFromISR+0x60>
800c6f0: f04f 0350 mov.w r3, #80 ; 0x50
800c6f4: b672 cpsid i
800c6f6: f383 8811 msr BASEPRI, r3
800c6fa: f3bf 8f6f isb sy
800c6fe: f3bf 8f4f dsb sy
800c702: b662 cpsie i
800c704: 623b str r3, [r7, #32]
800c706: e7fe b.n 800c706 <xQueueGenericSendFromISR+0x5e>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c708: 683b ldr r3, [r7, #0]
800c70a: 2b02 cmp r3, #2
800c70c: d103 bne.n 800c716 <xQueueGenericSendFromISR+0x6e>
800c70e: 6b3b ldr r3, [r7, #48] ; 0x30
800c710: 6bdb ldr r3, [r3, #60] ; 0x3c
800c712: 2b01 cmp r3, #1
800c714: d101 bne.n 800c71a <xQueueGenericSendFromISR+0x72>
800c716: 2301 movs r3, #1
800c718: e000 b.n 800c71c <xQueueGenericSendFromISR+0x74>
800c71a: 2300 movs r3, #0
800c71c: 2b00 cmp r3, #0
800c71e: d10b bne.n 800c738 <xQueueGenericSendFromISR+0x90>
800c720: f04f 0350 mov.w r3, #80 ; 0x50
800c724: b672 cpsid i
800c726: f383 8811 msr BASEPRI, r3
800c72a: f3bf 8f6f isb sy
800c72e: f3bf 8f4f dsb sy
800c732: b662 cpsie i
800c734: 61fb str r3, [r7, #28]
800c736: e7fe b.n 800c736 <xQueueGenericSendFromISR+0x8e>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c738: f001 ffde bl 800e6f8 <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
800c73c: f3ef 8211 mrs r2, BASEPRI
800c740: f04f 0350 mov.w r3, #80 ; 0x50
800c744: b672 cpsid i
800c746: f383 8811 msr BASEPRI, r3
800c74a: f3bf 8f6f isb sy
800c74e: f3bf 8f4f dsb sy
800c752: b662 cpsie i
800c754: 61ba str r2, [r7, #24]
800c756: 617b str r3, [r7, #20]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
800c758: 69bb ldr r3, [r7, #24]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c75a: 62fb str r3, [r7, #44] ; 0x2c
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c75c: 6b3b ldr r3, [r7, #48] ; 0x30
800c75e: 6b9a ldr r2, [r3, #56] ; 0x38
800c760: 6b3b ldr r3, [r7, #48] ; 0x30
800c762: 6bdb ldr r3, [r3, #60] ; 0x3c
800c764: 429a cmp r2, r3
800c766: d302 bcc.n 800c76e <xQueueGenericSendFromISR+0xc6>
800c768: 683b ldr r3, [r7, #0]
800c76a: 2b02 cmp r3, #2
800c76c: d12c bne.n 800c7c8 <xQueueGenericSendFromISR+0x120>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c76e: 6b3b ldr r3, [r7, #48] ; 0x30
800c770: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c774: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c778: 683a ldr r2, [r7, #0]
800c77a: 68b9 ldr r1, [r7, #8]
800c77c: 6b38 ldr r0, [r7, #48] ; 0x30
800c77e: f000 fb4e bl 800ce1e <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c782: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b
800c786: f1b3 3fff cmp.w r3, #4294967295
800c78a: d112 bne.n 800c7b2 <xQueueGenericSendFromISR+0x10a>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c78c: 6b3b ldr r3, [r7, #48] ; 0x30
800c78e: 6a5b ldr r3, [r3, #36] ; 0x24
800c790: 2b00 cmp r3, #0
800c792: d016 beq.n 800c7c2 <xQueueGenericSendFromISR+0x11a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c794: 6b3b ldr r3, [r7, #48] ; 0x30
800c796: 3324 adds r3, #36 ; 0x24
800c798: 4618 mov r0, r3
800c79a: f001 f9cb bl 800db34 <xTaskRemoveFromEventList>
800c79e: 4603 mov r3, r0
800c7a0: 2b00 cmp r3, #0
800c7a2: d00e beq.n 800c7c2 <xQueueGenericSendFromISR+0x11a>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c7a4: 687b ldr r3, [r7, #4]
800c7a6: 2b00 cmp r3, #0
800c7a8: d00b beq.n 800c7c2 <xQueueGenericSendFromISR+0x11a>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c7aa: 687b ldr r3, [r7, #4]
800c7ac: 2201 movs r2, #1
800c7ae: 601a str r2, [r3, #0]
800c7b0: e007 b.n 800c7c2 <xQueueGenericSendFromISR+0x11a>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c7b2: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
800c7b6: 3301 adds r3, #1
800c7b8: b2db uxtb r3, r3
800c7ba: b25a sxtb r2, r3
800c7bc: 6b3b ldr r3, [r7, #48] ; 0x30
800c7be: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c7c2: 2301 movs r3, #1
800c7c4: 637b str r3, [r7, #52] ; 0x34
{
800c7c6: e001 b.n 800c7cc <xQueueGenericSendFromISR+0x124>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c7c8: 2300 movs r3, #0
800c7ca: 637b str r3, [r7, #52] ; 0x34
800c7cc: 6afb ldr r3, [r7, #44] ; 0x2c
800c7ce: 613b str r3, [r7, #16]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
800c7d0: 693b ldr r3, [r7, #16]
800c7d2: f383 8811 msr BASEPRI, r3
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c7d6: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c7d8: 4618 mov r0, r3
800c7da: 3738 adds r7, #56 ; 0x38
800c7dc: 46bd mov sp, r7
800c7de: bd80 pop {r7, pc}
0800c7e0 <xQueueGiveFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
{
800c7e0: b580 push {r7, lr}
800c7e2: b08e sub sp, #56 ; 0x38
800c7e4: af00 add r7, sp, #0
800c7e6: 6078 str r0, [r7, #4]
800c7e8: 6039 str r1, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c7ea: 687b ldr r3, [r7, #4]
800c7ec: 633b str r3, [r7, #48] ; 0x30
item size is 0. Don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
configASSERT( pxQueue );
800c7ee: 6b3b ldr r3, [r7, #48] ; 0x30
800c7f0: 2b00 cmp r3, #0
800c7f2: d10b bne.n 800c80c <xQueueGiveFromISR+0x2c>
__asm volatile
800c7f4: f04f 0350 mov.w r3, #80 ; 0x50
800c7f8: b672 cpsid i
800c7fa: f383 8811 msr BASEPRI, r3
800c7fe: f3bf 8f6f isb sy
800c802: f3bf 8f4f dsb sy
800c806: b662 cpsie i
800c808: 623b str r3, [r7, #32]
800c80a: e7fe b.n 800c80a <xQueueGiveFromISR+0x2a>
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
if the item size is not 0. */
configASSERT( pxQueue->uxItemSize == 0 );
800c80c: 6b3b ldr r3, [r7, #48] ; 0x30
800c80e: 6c1b ldr r3, [r3, #64] ; 0x40
800c810: 2b00 cmp r3, #0
800c812: d00b beq.n 800c82c <xQueueGiveFromISR+0x4c>
800c814: f04f 0350 mov.w r3, #80 ; 0x50
800c818: b672 cpsid i
800c81a: f383 8811 msr BASEPRI, r3
800c81e: f3bf 8f6f isb sy
800c822: f3bf 8f4f dsb sy
800c826: b662 cpsie i
800c828: 61fb str r3, [r7, #28]
800c82a: e7fe b.n 800c82a <xQueueGiveFromISR+0x4a>
/* Normally a mutex would not be given from an interrupt, especially if
there is a mutex holder, as priority inheritance makes no sense for an
interrupts, only tasks. */
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
800c82c: 6b3b ldr r3, [r7, #48] ; 0x30
800c82e: 681b ldr r3, [r3, #0]
800c830: 2b00 cmp r3, #0
800c832: d103 bne.n 800c83c <xQueueGiveFromISR+0x5c>
800c834: 6b3b ldr r3, [r7, #48] ; 0x30
800c836: 689b ldr r3, [r3, #8]
800c838: 2b00 cmp r3, #0
800c83a: d101 bne.n 800c840 <xQueueGiveFromISR+0x60>
800c83c: 2301 movs r3, #1
800c83e: e000 b.n 800c842 <xQueueGiveFromISR+0x62>
800c840: 2300 movs r3, #0
800c842: 2b00 cmp r3, #0
800c844: d10b bne.n 800c85e <xQueueGiveFromISR+0x7e>
800c846: f04f 0350 mov.w r3, #80 ; 0x50
800c84a: b672 cpsid i
800c84c: f383 8811 msr BASEPRI, r3
800c850: f3bf 8f6f isb sy
800c854: f3bf 8f4f dsb sy
800c858: b662 cpsie i
800c85a: 61bb str r3, [r7, #24]
800c85c: e7fe b.n 800c85c <xQueueGiveFromISR+0x7c>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c85e: f001 ff4b bl 800e6f8 <vPortValidateInterruptPriority>
__asm volatile
800c862: f3ef 8211 mrs r2, BASEPRI
800c866: f04f 0350 mov.w r3, #80 ; 0x50
800c86a: b672 cpsid i
800c86c: f383 8811 msr BASEPRI, r3
800c870: f3bf 8f6f isb sy
800c874: f3bf 8f4f dsb sy
800c878: b662 cpsie i
800c87a: 617a str r2, [r7, #20]
800c87c: 613b str r3, [r7, #16]
return ulOriginalBASEPRI;
800c87e: 697b ldr r3, [r7, #20]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c880: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c882: 6b3b ldr r3, [r7, #48] ; 0x30
800c884: 6b9b ldr r3, [r3, #56] ; 0x38
800c886: 62bb str r3, [r7, #40] ; 0x28
/* When the queue is used to implement a semaphore no data is ever
moved through the queue but it is still valid to see if the queue 'has
space'. */
if( uxMessagesWaiting < pxQueue->uxLength )
800c888: 6b3b ldr r3, [r7, #48] ; 0x30
800c88a: 6bdb ldr r3, [r3, #60] ; 0x3c
800c88c: 6aba ldr r2, [r7, #40] ; 0x28
800c88e: 429a cmp r2, r3
800c890: d22b bcs.n 800c8ea <xQueueGiveFromISR+0x10a>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c892: 6b3b ldr r3, [r7, #48] ; 0x30
800c894: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c898: f887 3027 strb.w r3, [r7, #39] ; 0x27
holder - and if there is a mutex holder then the mutex cannot be
given from an ISR. As this is the ISR version of the function it
can be assumed there is no mutex holder and no need to determine if
priority disinheritance is needed. Simply increase the count of
messages (semaphores) available. */
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800c89c: 6abb ldr r3, [r7, #40] ; 0x28
800c89e: 1c5a adds r2, r3, #1
800c8a0: 6b3b ldr r3, [r7, #48] ; 0x30
800c8a2: 639a str r2, [r3, #56] ; 0x38
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c8a4: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800c8a8: f1b3 3fff cmp.w r3, #4294967295
800c8ac: d112 bne.n 800c8d4 <xQueueGiveFromISR+0xf4>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c8ae: 6b3b ldr r3, [r7, #48] ; 0x30
800c8b0: 6a5b ldr r3, [r3, #36] ; 0x24
800c8b2: 2b00 cmp r3, #0
800c8b4: d016 beq.n 800c8e4 <xQueueGiveFromISR+0x104>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c8b6: 6b3b ldr r3, [r7, #48] ; 0x30
800c8b8: 3324 adds r3, #36 ; 0x24
800c8ba: 4618 mov r0, r3
800c8bc: f001 f93a bl 800db34 <xTaskRemoveFromEventList>
800c8c0: 4603 mov r3, r0
800c8c2: 2b00 cmp r3, #0
800c8c4: d00e beq.n 800c8e4 <xQueueGiveFromISR+0x104>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c8c6: 683b ldr r3, [r7, #0]
800c8c8: 2b00 cmp r3, #0
800c8ca: d00b beq.n 800c8e4 <xQueueGiveFromISR+0x104>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c8cc: 683b ldr r3, [r7, #0]
800c8ce: 2201 movs r2, #1
800c8d0: 601a str r2, [r3, #0]
800c8d2: e007 b.n 800c8e4 <xQueueGiveFromISR+0x104>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c8d4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800c8d8: 3301 adds r3, #1
800c8da: b2db uxtb r3, r3
800c8dc: b25a sxtb r2, r3
800c8de: 6b3b ldr r3, [r7, #48] ; 0x30
800c8e0: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c8e4: 2301 movs r3, #1
800c8e6: 637b str r3, [r7, #52] ; 0x34
800c8e8: e001 b.n 800c8ee <xQueueGiveFromISR+0x10e>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c8ea: 2300 movs r3, #0
800c8ec: 637b str r3, [r7, #52] ; 0x34
800c8ee: 6afb ldr r3, [r7, #44] ; 0x2c
800c8f0: 60fb str r3, [r7, #12]
__asm volatile
800c8f2: 68fb ldr r3, [r7, #12]
800c8f4: f383 8811 msr BASEPRI, r3
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c8f8: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c8fa: 4618 mov r0, r3
800c8fc: 3738 adds r7, #56 ; 0x38
800c8fe: 46bd mov sp, r7
800c900: bd80 pop {r7, pc}
...
0800c904 <xQueueReceive>:
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
800c904: b580 push {r7, lr}
800c906: b08c sub sp, #48 ; 0x30
800c908: af00 add r7, sp, #0
800c90a: 60f8 str r0, [r7, #12]
800c90c: 60b9 str r1, [r7, #8]
800c90e: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
800c910: 2300 movs r3, #0
800c912: 62fb str r3, [r7, #44] ; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c914: 68fb ldr r3, [r7, #12]
800c916: 62bb str r3, [r7, #40] ; 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
800c918: 6abb ldr r3, [r7, #40] ; 0x28
800c91a: 2b00 cmp r3, #0
800c91c: d10b bne.n 800c936 <xQueueReceive+0x32>
__asm volatile
800c91e: f04f 0350 mov.w r3, #80 ; 0x50
800c922: b672 cpsid i
800c924: f383 8811 msr BASEPRI, r3
800c928: f3bf 8f6f isb sy
800c92c: f3bf 8f4f dsb sy
800c930: b662 cpsie i
800c932: 623b str r3, [r7, #32]
800c934: e7fe b.n 800c934 <xQueueReceive+0x30>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c936: 68bb ldr r3, [r7, #8]
800c938: 2b00 cmp r3, #0
800c93a: d103 bne.n 800c944 <xQueueReceive+0x40>
800c93c: 6abb ldr r3, [r7, #40] ; 0x28
800c93e: 6c1b ldr r3, [r3, #64] ; 0x40
800c940: 2b00 cmp r3, #0
800c942: d101 bne.n 800c948 <xQueueReceive+0x44>
800c944: 2301 movs r3, #1
800c946: e000 b.n 800c94a <xQueueReceive+0x46>
800c948: 2300 movs r3, #0
800c94a: 2b00 cmp r3, #0
800c94c: d10b bne.n 800c966 <xQueueReceive+0x62>
800c94e: f04f 0350 mov.w r3, #80 ; 0x50
800c952: b672 cpsid i
800c954: f383 8811 msr BASEPRI, r3
800c958: f3bf 8f6f isb sy
800c95c: f3bf 8f4f dsb sy
800c960: b662 cpsie i
800c962: 61fb str r3, [r7, #28]
800c964: e7fe b.n 800c964 <xQueueReceive+0x60>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c966: f001 faa5 bl 800deb4 <xTaskGetSchedulerState>
800c96a: 4603 mov r3, r0
800c96c: 2b00 cmp r3, #0
800c96e: d102 bne.n 800c976 <xQueueReceive+0x72>
800c970: 687b ldr r3, [r7, #4]
800c972: 2b00 cmp r3, #0
800c974: d101 bne.n 800c97a <xQueueReceive+0x76>
800c976: 2301 movs r3, #1
800c978: e000 b.n 800c97c <xQueueReceive+0x78>
800c97a: 2300 movs r3, #0
800c97c: 2b00 cmp r3, #0
800c97e: d10b bne.n 800c998 <xQueueReceive+0x94>
800c980: f04f 0350 mov.w r3, #80 ; 0x50
800c984: b672 cpsid i
800c986: f383 8811 msr BASEPRI, r3
800c98a: f3bf 8f6f isb sy
800c98e: f3bf 8f4f dsb sy
800c992: b662 cpsie i
800c994: 61bb str r3, [r7, #24]
800c996: e7fe b.n 800c996 <xQueueReceive+0x92>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c998: f001 fdce bl 800e538 <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c99c: 6abb ldr r3, [r7, #40] ; 0x28
800c99e: 6b9b ldr r3, [r3, #56] ; 0x38
800c9a0: 627b str r3, [r7, #36] ; 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800c9a2: 6a7b ldr r3, [r7, #36] ; 0x24
800c9a4: 2b00 cmp r3, #0
800c9a6: d01f beq.n 800c9e8 <xQueueReceive+0xe4>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
800c9a8: 68b9 ldr r1, [r7, #8]
800c9aa: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9ac: f000 faa1 bl 800cef2 <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800c9b0: 6a7b ldr r3, [r7, #36] ; 0x24
800c9b2: 1e5a subs r2, r3, #1
800c9b4: 6abb ldr r3, [r7, #40] ; 0x28
800c9b6: 639a str r2, [r3, #56] ; 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c9b8: 6abb ldr r3, [r7, #40] ; 0x28
800c9ba: 691b ldr r3, [r3, #16]
800c9bc: 2b00 cmp r3, #0
800c9be: d00f beq.n 800c9e0 <xQueueReceive+0xdc>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c9c0: 6abb ldr r3, [r7, #40] ; 0x28
800c9c2: 3310 adds r3, #16
800c9c4: 4618 mov r0, r3
800c9c6: f001 f8b5 bl 800db34 <xTaskRemoveFromEventList>
800c9ca: 4603 mov r3, r0
800c9cc: 2b00 cmp r3, #0
800c9ce: d007 beq.n 800c9e0 <xQueueReceive+0xdc>
{
queueYIELD_IF_USING_PREEMPTION();
800c9d0: 4b3c ldr r3, [pc, #240] ; (800cac4 <xQueueReceive+0x1c0>)
800c9d2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c9d6: 601a str r2, [r3, #0]
800c9d8: f3bf 8f4f dsb sy
800c9dc: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800c9e0: f001 fddc bl 800e59c <vPortExitCritical>
return pdPASS;
800c9e4: 2301 movs r3, #1
800c9e6: e069 b.n 800cabc <xQueueReceive+0x1b8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c9e8: 687b ldr r3, [r7, #4]
800c9ea: 2b00 cmp r3, #0
800c9ec: d103 bne.n 800c9f6 <xQueueReceive+0xf2>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c9ee: f001 fdd5 bl 800e59c <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800c9f2: 2300 movs r3, #0
800c9f4: e062 b.n 800cabc <xQueueReceive+0x1b8>
}
else if( xEntryTimeSet == pdFALSE )
800c9f6: 6afb ldr r3, [r7, #44] ; 0x2c
800c9f8: 2b00 cmp r3, #0
800c9fa: d106 bne.n 800ca0a <xQueueReceive+0x106>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800c9fc: f107 0310 add.w r3, r7, #16
800ca00: 4618 mov r0, r3
800ca02: f001 f8fb bl 800dbfc <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800ca06: 2301 movs r3, #1
800ca08: 62fb str r3, [r7, #44] ; 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800ca0a: f001 fdc7 bl 800e59c <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800ca0e: f000 fe61 bl 800d6d4 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800ca12: f001 fd91 bl 800e538 <vPortEnterCritical>
800ca16: 6abb ldr r3, [r7, #40] ; 0x28
800ca18: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800ca1c: b25b sxtb r3, r3
800ca1e: f1b3 3fff cmp.w r3, #4294967295
800ca22: d103 bne.n 800ca2c <xQueueReceive+0x128>
800ca24: 6abb ldr r3, [r7, #40] ; 0x28
800ca26: 2200 movs r2, #0
800ca28: f883 2044 strb.w r2, [r3, #68] ; 0x44
800ca2c: 6abb ldr r3, [r7, #40] ; 0x28
800ca2e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800ca32: b25b sxtb r3, r3
800ca34: f1b3 3fff cmp.w r3, #4294967295
800ca38: d103 bne.n 800ca42 <xQueueReceive+0x13e>
800ca3a: 6abb ldr r3, [r7, #40] ; 0x28
800ca3c: 2200 movs r2, #0
800ca3e: f883 2045 strb.w r2, [r3, #69] ; 0x45
800ca42: f001 fdab bl 800e59c <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800ca46: 1d3a adds r2, r7, #4
800ca48: f107 0310 add.w r3, r7, #16
800ca4c: 4611 mov r1, r2
800ca4e: 4618 mov r0, r3
800ca50: f001 f8ea bl 800dc28 <xTaskCheckForTimeOut>
800ca54: 4603 mov r3, r0
800ca56: 2b00 cmp r3, #0
800ca58: d123 bne.n 800caa2 <xQueueReceive+0x19e>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800ca5a: 6ab8 ldr r0, [r7, #40] ; 0x28
800ca5c: f000 fac1 bl 800cfe2 <prvIsQueueEmpty>
800ca60: 4603 mov r3, r0
800ca62: 2b00 cmp r3, #0
800ca64: d017 beq.n 800ca96 <xQueueReceive+0x192>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800ca66: 6abb ldr r3, [r7, #40] ; 0x28
800ca68: 3324 adds r3, #36 ; 0x24
800ca6a: 687a ldr r2, [r7, #4]
800ca6c: 4611 mov r1, r2
800ca6e: 4618 mov r0, r3
800ca70: f001 f83a bl 800dae8 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800ca74: 6ab8 ldr r0, [r7, #40] ; 0x28
800ca76: f000 fa62 bl 800cf3e <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800ca7a: f000 fe39 bl 800d6f0 <xTaskResumeAll>
800ca7e: 4603 mov r3, r0
800ca80: 2b00 cmp r3, #0
800ca82: d189 bne.n 800c998 <xQueueReceive+0x94>
{
portYIELD_WITHIN_API();
800ca84: 4b0f ldr r3, [pc, #60] ; (800cac4 <xQueueReceive+0x1c0>)
800ca86: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800ca8a: 601a str r2, [r3, #0]
800ca8c: f3bf 8f4f dsb sy
800ca90: f3bf 8f6f isb sy
800ca94: e780 b.n 800c998 <xQueueReceive+0x94>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
800ca96: 6ab8 ldr r0, [r7, #40] ; 0x28
800ca98: f000 fa51 bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800ca9c: f000 fe28 bl 800d6f0 <xTaskResumeAll>
800caa0: e77a b.n 800c998 <xQueueReceive+0x94>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
800caa2: 6ab8 ldr r0, [r7, #40] ; 0x28
800caa4: f000 fa4b bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800caa8: f000 fe22 bl 800d6f0 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800caac: 6ab8 ldr r0, [r7, #40] ; 0x28
800caae: f000 fa98 bl 800cfe2 <prvIsQueueEmpty>
800cab2: 4603 mov r3, r0
800cab4: 2b00 cmp r3, #0
800cab6: f43f af6f beq.w 800c998 <xQueueReceive+0x94>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800caba: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800cabc: 4618 mov r0, r3
800cabe: 3730 adds r7, #48 ; 0x30
800cac0: 46bd mov sp, r7
800cac2: bd80 pop {r7, pc}
800cac4: e000ed04 .word 0xe000ed04
0800cac8 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
800cac8: b580 push {r7, lr}
800caca: b08e sub sp, #56 ; 0x38
800cacc: af00 add r7, sp, #0
800cace: 6078 str r0, [r7, #4]
800cad0: 6039 str r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
800cad2: 2300 movs r3, #0
800cad4: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800cad6: 687b ldr r3, [r7, #4]
800cad8: 62fb str r3, [r7, #44] ; 0x2c
#if( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
800cada: 2300 movs r3, #0
800cadc: 633b str r3, [r7, #48] ; 0x30
#endif
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
800cade: 6afb ldr r3, [r7, #44] ; 0x2c
800cae0: 2b00 cmp r3, #0
800cae2: d10b bne.n 800cafc <xQueueSemaphoreTake+0x34>
800cae4: f04f 0350 mov.w r3, #80 ; 0x50
800cae8: b672 cpsid i
800caea: f383 8811 msr BASEPRI, r3
800caee: f3bf 8f6f isb sy
800caf2: f3bf 8f4f dsb sy
800caf6: b662 cpsie i
800caf8: 623b str r3, [r7, #32]
800cafa: e7fe b.n 800cafa <xQueueSemaphoreTake+0x32>
/* Check this really is a semaphore, in which case the item size will be
0. */
configASSERT( pxQueue->uxItemSize == 0 );
800cafc: 6afb ldr r3, [r7, #44] ; 0x2c
800cafe: 6c1b ldr r3, [r3, #64] ; 0x40
800cb00: 2b00 cmp r3, #0
800cb02: d00b beq.n 800cb1c <xQueueSemaphoreTake+0x54>
800cb04: f04f 0350 mov.w r3, #80 ; 0x50
800cb08: b672 cpsid i
800cb0a: f383 8811 msr BASEPRI, r3
800cb0e: f3bf 8f6f isb sy
800cb12: f3bf 8f4f dsb sy
800cb16: b662 cpsie i
800cb18: 61fb str r3, [r7, #28]
800cb1a: e7fe b.n 800cb1a <xQueueSemaphoreTake+0x52>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800cb1c: f001 f9ca bl 800deb4 <xTaskGetSchedulerState>
800cb20: 4603 mov r3, r0
800cb22: 2b00 cmp r3, #0
800cb24: d102 bne.n 800cb2c <xQueueSemaphoreTake+0x64>
800cb26: 683b ldr r3, [r7, #0]
800cb28: 2b00 cmp r3, #0
800cb2a: d101 bne.n 800cb30 <xQueueSemaphoreTake+0x68>
800cb2c: 2301 movs r3, #1
800cb2e: e000 b.n 800cb32 <xQueueSemaphoreTake+0x6a>
800cb30: 2300 movs r3, #0
800cb32: 2b00 cmp r3, #0
800cb34: d10b bne.n 800cb4e <xQueueSemaphoreTake+0x86>
800cb36: f04f 0350 mov.w r3, #80 ; 0x50
800cb3a: b672 cpsid i
800cb3c: f383 8811 msr BASEPRI, r3
800cb40: f3bf 8f6f isb sy
800cb44: f3bf 8f4f dsb sy
800cb48: b662 cpsie i
800cb4a: 61bb str r3, [r7, #24]
800cb4c: e7fe b.n 800cb4c <xQueueSemaphoreTake+0x84>
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800cb4e: f001 fcf3 bl 800e538 <vPortEnterCritical>
{
/* Semaphores are queues with an item size of 0, and where the
number of messages in the queue is the semaphore's count value. */
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
800cb52: 6afb ldr r3, [r7, #44] ; 0x2c
800cb54: 6b9b ldr r3, [r3, #56] ; 0x38
800cb56: 62bb str r3, [r7, #40] ; 0x28
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
800cb58: 6abb ldr r3, [r7, #40] ; 0x28
800cb5a: 2b00 cmp r3, #0
800cb5c: d024 beq.n 800cba8 <xQueueSemaphoreTake+0xe0>
{
traceQUEUE_RECEIVE( pxQueue );
/* Semaphores are queues with a data size of zero and where the
messages waiting is the semaphore's count. Reduce the count. */
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
800cb5e: 6abb ldr r3, [r7, #40] ; 0x28
800cb60: 1e5a subs r2, r3, #1
800cb62: 6afb ldr r3, [r7, #44] ; 0x2c
800cb64: 639a str r2, [r3, #56] ; 0x38
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cb66: 6afb ldr r3, [r7, #44] ; 0x2c
800cb68: 681b ldr r3, [r3, #0]
800cb6a: 2b00 cmp r3, #0
800cb6c: d104 bne.n 800cb78 <xQueueSemaphoreTake+0xb0>
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
800cb6e: f001 fb63 bl 800e238 <pvTaskIncrementMutexHeldCount>
800cb72: 4602 mov r2, r0
800cb74: 6afb ldr r3, [r7, #44] ; 0x2c
800cb76: 609a str r2, [r3, #8]
}
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
semaphore, and if so, unblock the highest priority such task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cb78: 6afb ldr r3, [r7, #44] ; 0x2c
800cb7a: 691b ldr r3, [r3, #16]
800cb7c: 2b00 cmp r3, #0
800cb7e: d00f beq.n 800cba0 <xQueueSemaphoreTake+0xd8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cb80: 6afb ldr r3, [r7, #44] ; 0x2c
800cb82: 3310 adds r3, #16
800cb84: 4618 mov r0, r3
800cb86: f000 ffd5 bl 800db34 <xTaskRemoveFromEventList>
800cb8a: 4603 mov r3, r0
800cb8c: 2b00 cmp r3, #0
800cb8e: d007 beq.n 800cba0 <xQueueSemaphoreTake+0xd8>
{
queueYIELD_IF_USING_PREEMPTION();
800cb90: 4b54 ldr r3, [pc, #336] ; (800cce4 <xQueueSemaphoreTake+0x21c>)
800cb92: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cb96: 601a str r2, [r3, #0]
800cb98: f3bf 8f4f dsb sy
800cb9c: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800cba0: f001 fcfc bl 800e59c <vPortExitCritical>
return pdPASS;
800cba4: 2301 movs r3, #1
800cba6: e098 b.n 800ccda <xQueueSemaphoreTake+0x212>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800cba8: 683b ldr r3, [r7, #0]
800cbaa: 2b00 cmp r3, #0
800cbac: d112 bne.n 800cbd4 <xQueueSemaphoreTake+0x10c>
/* For inheritance to have occurred there must have been an
initial timeout, and an adjusted timeout cannot become 0, as
if it were 0 the function would have exited. */
#if( configUSE_MUTEXES == 1 )
{
configASSERT( xInheritanceOccurred == pdFALSE );
800cbae: 6b3b ldr r3, [r7, #48] ; 0x30
800cbb0: 2b00 cmp r3, #0
800cbb2: d00b beq.n 800cbcc <xQueueSemaphoreTake+0x104>
800cbb4: f04f 0350 mov.w r3, #80 ; 0x50
800cbb8: b672 cpsid i
800cbba: f383 8811 msr BASEPRI, r3
800cbbe: f3bf 8f6f isb sy
800cbc2: f3bf 8f4f dsb sy
800cbc6: b662 cpsie i
800cbc8: 617b str r3, [r7, #20]
800cbca: e7fe b.n 800cbca <xQueueSemaphoreTake+0x102>
}
#endif /* configUSE_MUTEXES */
/* The semaphore count was 0 and no block time is specified
(or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
800cbcc: f001 fce6 bl 800e59c <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cbd0: 2300 movs r3, #0
800cbd2: e082 b.n 800ccda <xQueueSemaphoreTake+0x212>
}
else if( xEntryTimeSet == pdFALSE )
800cbd4: 6b7b ldr r3, [r7, #52] ; 0x34
800cbd6: 2b00 cmp r3, #0
800cbd8: d106 bne.n 800cbe8 <xQueueSemaphoreTake+0x120>
{
/* The semaphore count was 0 and a block time was specified
so configure the timeout structure ready to block. */
vTaskInternalSetTimeOutState( &xTimeOut );
800cbda: f107 030c add.w r3, r7, #12
800cbde: 4618 mov r0, r3
800cbe0: f001 f80c bl 800dbfc <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800cbe4: 2301 movs r3, #1
800cbe6: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800cbe8: f001 fcd8 bl 800e59c <vPortExitCritical>
/* Interrupts and other tasks can give to and take from the semaphore
now the critical section has been exited. */
vTaskSuspendAll();
800cbec: f000 fd72 bl 800d6d4 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800cbf0: f001 fca2 bl 800e538 <vPortEnterCritical>
800cbf4: 6afb ldr r3, [r7, #44] ; 0x2c
800cbf6: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cbfa: b25b sxtb r3, r3
800cbfc: f1b3 3fff cmp.w r3, #4294967295
800cc00: d103 bne.n 800cc0a <xQueueSemaphoreTake+0x142>
800cc02: 6afb ldr r3, [r7, #44] ; 0x2c
800cc04: 2200 movs r2, #0
800cc06: f883 2044 strb.w r2, [r3, #68] ; 0x44
800cc0a: 6afb ldr r3, [r7, #44] ; 0x2c
800cc0c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800cc10: b25b sxtb r3, r3
800cc12: f1b3 3fff cmp.w r3, #4294967295
800cc16: d103 bne.n 800cc20 <xQueueSemaphoreTake+0x158>
800cc18: 6afb ldr r3, [r7, #44] ; 0x2c
800cc1a: 2200 movs r2, #0
800cc1c: f883 2045 strb.w r2, [r3, #69] ; 0x45
800cc20: f001 fcbc bl 800e59c <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800cc24: 463a mov r2, r7
800cc26: f107 030c add.w r3, r7, #12
800cc2a: 4611 mov r1, r2
800cc2c: 4618 mov r0, r3
800cc2e: f000 fffb bl 800dc28 <xTaskCheckForTimeOut>
800cc32: 4603 mov r3, r0
800cc34: 2b00 cmp r3, #0
800cc36: d132 bne.n 800cc9e <xQueueSemaphoreTake+0x1d6>
{
/* A block time is specified and not expired. If the semaphore
count is 0 then enter the Blocked state to wait for a semaphore to
become available. As semaphores are implemented with queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cc38: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc3a: f000 f9d2 bl 800cfe2 <prvIsQueueEmpty>
800cc3e: 4603 mov r3, r0
800cc40: 2b00 cmp r3, #0
800cc42: d026 beq.n 800cc92 <xQueueSemaphoreTake+0x1ca>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cc44: 6afb ldr r3, [r7, #44] ; 0x2c
800cc46: 681b ldr r3, [r3, #0]
800cc48: 2b00 cmp r3, #0
800cc4a: d109 bne.n 800cc60 <xQueueSemaphoreTake+0x198>
{
taskENTER_CRITICAL();
800cc4c: f001 fc74 bl 800e538 <vPortEnterCritical>
{
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
800cc50: 6afb ldr r3, [r7, #44] ; 0x2c
800cc52: 689b ldr r3, [r3, #8]
800cc54: 4618 mov r0, r3
800cc56: f001 f94b bl 800def0 <xTaskPriorityInherit>
800cc5a: 6338 str r0, [r7, #48] ; 0x30
}
taskEXIT_CRITICAL();
800cc5c: f001 fc9e bl 800e59c <vPortExitCritical>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800cc60: 6afb ldr r3, [r7, #44] ; 0x2c
800cc62: 3324 adds r3, #36 ; 0x24
800cc64: 683a ldr r2, [r7, #0]
800cc66: 4611 mov r1, r2
800cc68: 4618 mov r0, r3
800cc6a: f000 ff3d bl 800dae8 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800cc6e: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc70: f000 f965 bl 800cf3e <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800cc74: f000 fd3c bl 800d6f0 <xTaskResumeAll>
800cc78: 4603 mov r3, r0
800cc7a: 2b00 cmp r3, #0
800cc7c: f47f af67 bne.w 800cb4e <xQueueSemaphoreTake+0x86>
{
portYIELD_WITHIN_API();
800cc80: 4b18 ldr r3, [pc, #96] ; (800cce4 <xQueueSemaphoreTake+0x21c>)
800cc82: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cc86: 601a str r2, [r3, #0]
800cc88: f3bf 8f4f dsb sy
800cc8c: f3bf 8f6f isb sy
800cc90: e75d b.n 800cb4e <xQueueSemaphoreTake+0x86>
}
else
{
/* There was no timeout and the semaphore count was not 0, so
attempt to take the semaphore again. */
prvUnlockQueue( pxQueue );
800cc92: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc94: f000 f953 bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800cc98: f000 fd2a bl 800d6f0 <xTaskResumeAll>
800cc9c: e757 b.n 800cb4e <xQueueSemaphoreTake+0x86>
}
}
else
{
/* Timed out. */
prvUnlockQueue( pxQueue );
800cc9e: 6af8 ldr r0, [r7, #44] ; 0x2c
800cca0: f000 f94d bl 800cf3e <prvUnlockQueue>
( void ) xTaskResumeAll();
800cca4: f000 fd24 bl 800d6f0 <xTaskResumeAll>
/* If the semaphore count is 0 exit now as the timeout has
expired. Otherwise return to attempt to take the semaphore that is
known to be available. As semaphores are implemented by queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cca8: 6af8 ldr r0, [r7, #44] ; 0x2c
800ccaa: f000 f99a bl 800cfe2 <prvIsQueueEmpty>
800ccae: 4603 mov r3, r0
800ccb0: 2b00 cmp r3, #0
800ccb2: f43f af4c beq.w 800cb4e <xQueueSemaphoreTake+0x86>
#if ( configUSE_MUTEXES == 1 )
{
/* xInheritanceOccurred could only have be set if
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
test the mutex type again to check it is actually a mutex. */
if( xInheritanceOccurred != pdFALSE )
800ccb6: 6b3b ldr r3, [r7, #48] ; 0x30
800ccb8: 2b00 cmp r3, #0
800ccba: d00d beq.n 800ccd8 <xQueueSemaphoreTake+0x210>
{
taskENTER_CRITICAL();
800ccbc: f001 fc3c bl 800e538 <vPortEnterCritical>
/* This task blocking on the mutex caused another
task to inherit this task's priority. Now this task
has timed out the priority should be disinherited
again, but only as low as the next highest priority
task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
800ccc0: 6af8 ldr r0, [r7, #44] ; 0x2c
800ccc2: f000 f894 bl 800cdee <prvGetDisinheritPriorityAfterTimeout>
800ccc6: 6278 str r0, [r7, #36] ; 0x24
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
800ccc8: 6afb ldr r3, [r7, #44] ; 0x2c
800ccca: 689b ldr r3, [r3, #8]
800cccc: 6a79 ldr r1, [r7, #36] ; 0x24
800ccce: 4618 mov r0, r3
800ccd0: f001 fa16 bl 800e100 <vTaskPriorityDisinheritAfterTimeout>
}
taskEXIT_CRITICAL();
800ccd4: f001 fc62 bl 800e59c <vPortExitCritical>
}
}
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800ccd8: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800ccda: 4618 mov r0, r3
800ccdc: 3738 adds r7, #56 ; 0x38
800ccde: 46bd mov sp, r7
800cce0: bd80 pop {r7, pc}
800cce2: bf00 nop
800cce4: e000ed04 .word 0xe000ed04
0800cce8 <xQueueReceiveFromISR>:
} /*lint -restore */
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
{
800cce8: b580 push {r7, lr}
800ccea: b08e sub sp, #56 ; 0x38
800ccec: af00 add r7, sp, #0
800ccee: 60f8 str r0, [r7, #12]
800ccf0: 60b9 str r1, [r7, #8]
800ccf2: 607a str r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800ccf4: 68fb ldr r3, [r7, #12]
800ccf6: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800ccf8: 6b3b ldr r3, [r7, #48] ; 0x30
800ccfa: 2b00 cmp r3, #0
800ccfc: d10b bne.n 800cd16 <xQueueReceiveFromISR+0x2e>
800ccfe: f04f 0350 mov.w r3, #80 ; 0x50
800cd02: b672 cpsid i
800cd04: f383 8811 msr BASEPRI, r3
800cd08: f3bf 8f6f isb sy
800cd0c: f3bf 8f4f dsb sy
800cd10: b662 cpsie i
800cd12: 623b str r3, [r7, #32]
800cd14: e7fe b.n 800cd14 <xQueueReceiveFromISR+0x2c>
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800cd16: 68bb ldr r3, [r7, #8]
800cd18: 2b00 cmp r3, #0
800cd1a: d103 bne.n 800cd24 <xQueueReceiveFromISR+0x3c>
800cd1c: 6b3b ldr r3, [r7, #48] ; 0x30
800cd1e: 6c1b ldr r3, [r3, #64] ; 0x40
800cd20: 2b00 cmp r3, #0
800cd22: d101 bne.n 800cd28 <xQueueReceiveFromISR+0x40>
800cd24: 2301 movs r3, #1
800cd26: e000 b.n 800cd2a <xQueueReceiveFromISR+0x42>
800cd28: 2300 movs r3, #0
800cd2a: 2b00 cmp r3, #0
800cd2c: d10b bne.n 800cd46 <xQueueReceiveFromISR+0x5e>
800cd2e: f04f 0350 mov.w r3, #80 ; 0x50
800cd32: b672 cpsid i
800cd34: f383 8811 msr BASEPRI, r3
800cd38: f3bf 8f6f isb sy
800cd3c: f3bf 8f4f dsb sy
800cd40: b662 cpsie i
800cd42: 61fb str r3, [r7, #28]
800cd44: e7fe b.n 800cd44 <xQueueReceiveFromISR+0x5c>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800cd46: f001 fcd7 bl 800e6f8 <vPortValidateInterruptPriority>
__asm volatile
800cd4a: f3ef 8211 mrs r2, BASEPRI
800cd4e: f04f 0350 mov.w r3, #80 ; 0x50
800cd52: b672 cpsid i
800cd54: f383 8811 msr BASEPRI, r3
800cd58: f3bf 8f6f isb sy
800cd5c: f3bf 8f4f dsb sy
800cd60: b662 cpsie i
800cd62: 61ba str r2, [r7, #24]
800cd64: 617b str r3, [r7, #20]
return ulOriginalBASEPRI;
800cd66: 69bb ldr r3, [r7, #24]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800cd68: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800cd6a: 6b3b ldr r3, [r7, #48] ; 0x30
800cd6c: 6b9b ldr r3, [r3, #56] ; 0x38
800cd6e: 62bb str r3, [r7, #40] ; 0x28
/* Cannot block in an ISR, so check there is data available. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800cd70: 6abb ldr r3, [r7, #40] ; 0x28
800cd72: 2b00 cmp r3, #0
800cd74: d02f beq.n 800cdd6 <xQueueReceiveFromISR+0xee>
{
const int8_t cRxLock = pxQueue->cRxLock;
800cd76: 6b3b ldr r3, [r7, #48] ; 0x30
800cd78: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cd7c: f887 3027 strb.w r3, [r7, #39] ; 0x27
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
800cd80: 68b9 ldr r1, [r7, #8]
800cd82: 6b38 ldr r0, [r7, #48] ; 0x30
800cd84: f000 f8b5 bl 800cef2 <prvCopyDataFromQueue>
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800cd88: 6abb ldr r3, [r7, #40] ; 0x28
800cd8a: 1e5a subs r2, r3, #1
800cd8c: 6b3b ldr r3, [r7, #48] ; 0x30
800cd8e: 639a str r2, [r3, #56] ; 0x38
/* If the queue is locked the event list will not be modified.
Instead update the lock count so the task that unlocks the queue
will know that an ISR has removed data while the queue was
locked. */
if( cRxLock == queueUNLOCKED )
800cd90: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800cd94: f1b3 3fff cmp.w r3, #4294967295
800cd98: d112 bne.n 800cdc0 <xQueueReceiveFromISR+0xd8>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cd9a: 6b3b ldr r3, [r7, #48] ; 0x30
800cd9c: 691b ldr r3, [r3, #16]
800cd9e: 2b00 cmp r3, #0
800cda0: d016 beq.n 800cdd0 <xQueueReceiveFromISR+0xe8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cda2: 6b3b ldr r3, [r7, #48] ; 0x30
800cda4: 3310 adds r3, #16
800cda6: 4618 mov r0, r3
800cda8: f000 fec4 bl 800db34 <xTaskRemoveFromEventList>
800cdac: 4603 mov r3, r0
800cdae: 2b00 cmp r3, #0
800cdb0: d00e beq.n 800cdd0 <xQueueReceiveFromISR+0xe8>
{
/* The task waiting has a higher priority than us so
force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
800cdb2: 687b ldr r3, [r7, #4]
800cdb4: 2b00 cmp r3, #0
800cdb6: d00b beq.n 800cdd0 <xQueueReceiveFromISR+0xe8>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800cdb8: 687b ldr r3, [r7, #4]
800cdba: 2201 movs r2, #1
800cdbc: 601a str r2, [r3, #0]
800cdbe: e007 b.n 800cdd0 <xQueueReceiveFromISR+0xe8>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was removed while it was locked. */
pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
800cdc0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800cdc4: 3301 adds r3, #1
800cdc6: b2db uxtb r3, r3
800cdc8: b25a sxtb r2, r3
800cdca: 6b3b ldr r3, [r7, #48] ; 0x30
800cdcc: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
xReturn = pdPASS;
800cdd0: 2301 movs r3, #1
800cdd2: 637b str r3, [r7, #52] ; 0x34
800cdd4: e001 b.n 800cdda <xQueueReceiveFromISR+0xf2>
}
else
{
xReturn = pdFAIL;
800cdd6: 2300 movs r3, #0
800cdd8: 637b str r3, [r7, #52] ; 0x34
800cdda: 6afb ldr r3, [r7, #44] ; 0x2c
800cddc: 613b str r3, [r7, #16]
__asm volatile
800cdde: 693b ldr r3, [r7, #16]
800cde0: f383 8811 msr BASEPRI, r3
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800cde4: 6b7b ldr r3, [r7, #52] ; 0x34
}
800cde6: 4618 mov r0, r3
800cde8: 3738 adds r7, #56 ; 0x38
800cdea: 46bd mov sp, r7
800cdec: bd80 pop {r7, pc}
0800cdee <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
{
800cdee: b480 push {r7}
800cdf0: b085 sub sp, #20
800cdf2: af00 add r7, sp, #0
800cdf4: 6078 str r0, [r7, #4]
priority, but the waiting task times out, then the holder should
disinherit the priority - but only down to the highest priority of any
other tasks that are waiting for the same mutex. For this purpose,
return the priority of the highest priority task that is waiting for the
mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
800cdf6: 687b ldr r3, [r7, #4]
800cdf8: 6a5b ldr r3, [r3, #36] ; 0x24
800cdfa: 2b00 cmp r3, #0
800cdfc: d006 beq.n 800ce0c <prvGetDisinheritPriorityAfterTimeout+0x1e>
{
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
800cdfe: 687b ldr r3, [r7, #4]
800ce00: 6b1b ldr r3, [r3, #48] ; 0x30
800ce02: 681b ldr r3, [r3, #0]
800ce04: f1c3 0307 rsb r3, r3, #7
800ce08: 60fb str r3, [r7, #12]
800ce0a: e001 b.n 800ce10 <prvGetDisinheritPriorityAfterTimeout+0x22>
}
else
{
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
800ce0c: 2300 movs r3, #0
800ce0e: 60fb str r3, [r7, #12]
}
return uxHighestPriorityOfWaitingTasks;
800ce10: 68fb ldr r3, [r7, #12]
}
800ce12: 4618 mov r0, r3
800ce14: 3714 adds r7, #20
800ce16: 46bd mov sp, r7
800ce18: f85d 7b04 ldr.w r7, [sp], #4
800ce1c: 4770 bx lr
0800ce1e <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
800ce1e: b580 push {r7, lr}
800ce20: b086 sub sp, #24
800ce22: af00 add r7, sp, #0
800ce24: 60f8 str r0, [r7, #12]
800ce26: 60b9 str r1, [r7, #8]
800ce28: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
800ce2a: 2300 movs r3, #0
800ce2c: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800ce2e: 68fb ldr r3, [r7, #12]
800ce30: 6b9b ldr r3, [r3, #56] ; 0x38
800ce32: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800ce34: 68fb ldr r3, [r7, #12]
800ce36: 6c1b ldr r3, [r3, #64] ; 0x40
800ce38: 2b00 cmp r3, #0
800ce3a: d10d bne.n 800ce58 <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800ce3c: 68fb ldr r3, [r7, #12]
800ce3e: 681b ldr r3, [r3, #0]
800ce40: 2b00 cmp r3, #0
800ce42: d14d bne.n 800cee0 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800ce44: 68fb ldr r3, [r7, #12]
800ce46: 689b ldr r3, [r3, #8]
800ce48: 4618 mov r0, r3
800ce4a: f001 f8d1 bl 800dff0 <xTaskPriorityDisinherit>
800ce4e: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
800ce50: 68fb ldr r3, [r7, #12]
800ce52: 2200 movs r2, #0
800ce54: 609a str r2, [r3, #8]
800ce56: e043 b.n 800cee0 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
800ce58: 687b ldr r3, [r7, #4]
800ce5a: 2b00 cmp r3, #0
800ce5c: d119 bne.n 800ce92 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800ce5e: 68fb ldr r3, [r7, #12]
800ce60: 6858 ldr r0, [r3, #4]
800ce62: 68fb ldr r3, [r7, #12]
800ce64: 6c1b ldr r3, [r3, #64] ; 0x40
800ce66: 461a mov r2, r3
800ce68: 68b9 ldr r1, [r7, #8]
800ce6a: f00e f8c0 bl 801afee <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800ce6e: 68fb ldr r3, [r7, #12]
800ce70: 685a ldr r2, [r3, #4]
800ce72: 68fb ldr r3, [r7, #12]
800ce74: 6c1b ldr r3, [r3, #64] ; 0x40
800ce76: 441a add r2, r3
800ce78: 68fb ldr r3, [r7, #12]
800ce7a: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800ce7c: 68fb ldr r3, [r7, #12]
800ce7e: 685a ldr r2, [r3, #4]
800ce80: 68fb ldr r3, [r7, #12]
800ce82: 689b ldr r3, [r3, #8]
800ce84: 429a cmp r2, r3
800ce86: d32b bcc.n 800cee0 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
800ce88: 68fb ldr r3, [r7, #12]
800ce8a: 681a ldr r2, [r3, #0]
800ce8c: 68fb ldr r3, [r7, #12]
800ce8e: 605a str r2, [r3, #4]
800ce90: e026 b.n 800cee0 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
800ce92: 68fb ldr r3, [r7, #12]
800ce94: 68d8 ldr r0, [r3, #12]
800ce96: 68fb ldr r3, [r7, #12]
800ce98: 6c1b ldr r3, [r3, #64] ; 0x40
800ce9a: 461a mov r2, r3
800ce9c: 68b9 ldr r1, [r7, #8]
800ce9e: f00e f8a6 bl 801afee <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
800cea2: 68fb ldr r3, [r7, #12]
800cea4: 68da ldr r2, [r3, #12]
800cea6: 68fb ldr r3, [r7, #12]
800cea8: 6c1b ldr r3, [r3, #64] ; 0x40
800ceaa: 425b negs r3, r3
800ceac: 441a add r2, r3
800ceae: 68fb ldr r3, [r7, #12]
800ceb0: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800ceb2: 68fb ldr r3, [r7, #12]
800ceb4: 68da ldr r2, [r3, #12]
800ceb6: 68fb ldr r3, [r7, #12]
800ceb8: 681b ldr r3, [r3, #0]
800ceba: 429a cmp r2, r3
800cebc: d207 bcs.n 800cece <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
800cebe: 68fb ldr r3, [r7, #12]
800cec0: 689a ldr r2, [r3, #8]
800cec2: 68fb ldr r3, [r7, #12]
800cec4: 6c1b ldr r3, [r3, #64] ; 0x40
800cec6: 425b negs r3, r3
800cec8: 441a add r2, r3
800ceca: 68fb ldr r3, [r7, #12]
800cecc: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
800cece: 687b ldr r3, [r7, #4]
800ced0: 2b02 cmp r3, #2
800ced2: d105 bne.n 800cee0 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800ced4: 693b ldr r3, [r7, #16]
800ced6: 2b00 cmp r3, #0
800ced8: d002 beq.n 800cee0 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
800ceda: 693b ldr r3, [r7, #16]
800cedc: 3b01 subs r3, #1
800cede: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800cee0: 693b ldr r3, [r7, #16]
800cee2: 1c5a adds r2, r3, #1
800cee4: 68fb ldr r3, [r7, #12]
800cee6: 639a str r2, [r3, #56] ; 0x38
return xReturn;
800cee8: 697b ldr r3, [r7, #20]
}
800ceea: 4618 mov r0, r3
800ceec: 3718 adds r7, #24
800ceee: 46bd mov sp, r7
800cef0: bd80 pop {r7, pc}
0800cef2 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
800cef2: b580 push {r7, lr}
800cef4: b082 sub sp, #8
800cef6: af00 add r7, sp, #0
800cef8: 6078 str r0, [r7, #4]
800cefa: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
800cefc: 687b ldr r3, [r7, #4]
800cefe: 6c1b ldr r3, [r3, #64] ; 0x40
800cf00: 2b00 cmp r3, #0
800cf02: d018 beq.n 800cf36 <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800cf04: 687b ldr r3, [r7, #4]
800cf06: 68da ldr r2, [r3, #12]
800cf08: 687b ldr r3, [r7, #4]
800cf0a: 6c1b ldr r3, [r3, #64] ; 0x40
800cf0c: 441a add r2, r3
800cf0e: 687b ldr r3, [r7, #4]
800cf10: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
800cf12: 687b ldr r3, [r7, #4]
800cf14: 68da ldr r2, [r3, #12]
800cf16: 687b ldr r3, [r7, #4]
800cf18: 689b ldr r3, [r3, #8]
800cf1a: 429a cmp r2, r3
800cf1c: d303 bcc.n 800cf26 <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
800cf1e: 687b ldr r3, [r7, #4]
800cf20: 681a ldr r2, [r3, #0]
800cf22: 687b ldr r3, [r7, #4]
800cf24: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800cf26: 687b ldr r3, [r7, #4]
800cf28: 68d9 ldr r1, [r3, #12]
800cf2a: 687b ldr r3, [r7, #4]
800cf2c: 6c1b ldr r3, [r3, #64] ; 0x40
800cf2e: 461a mov r2, r3
800cf30: 6838 ldr r0, [r7, #0]
800cf32: f00e f85c bl 801afee <memcpy>
}
}
800cf36: bf00 nop
800cf38: 3708 adds r7, #8
800cf3a: 46bd mov sp, r7
800cf3c: bd80 pop {r7, pc}
0800cf3e <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
800cf3e: b580 push {r7, lr}
800cf40: b084 sub sp, #16
800cf42: af00 add r7, sp, #0
800cf44: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
800cf46: f001 faf7 bl 800e538 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
800cf4a: 687b ldr r3, [r7, #4]
800cf4c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800cf50: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
800cf52: e011 b.n 800cf78 <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800cf54: 687b ldr r3, [r7, #4]
800cf56: 6a5b ldr r3, [r3, #36] ; 0x24
800cf58: 2b00 cmp r3, #0
800cf5a: d012 beq.n 800cf82 <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800cf5c: 687b ldr r3, [r7, #4]
800cf5e: 3324 adds r3, #36 ; 0x24
800cf60: 4618 mov r0, r3
800cf62: f000 fde7 bl 800db34 <xTaskRemoveFromEventList>
800cf66: 4603 mov r3, r0
800cf68: 2b00 cmp r3, #0
800cf6a: d001 beq.n 800cf70 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
800cf6c: f000 fec0 bl 800dcf0 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
800cf70: 7bfb ldrb r3, [r7, #15]
800cf72: 3b01 subs r3, #1
800cf74: b2db uxtb r3, r3
800cf76: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
800cf78: f997 300f ldrsb.w r3, [r7, #15]
800cf7c: 2b00 cmp r3, #0
800cf7e: dce9 bgt.n 800cf54 <prvUnlockQueue+0x16>
800cf80: e000 b.n 800cf84 <prvUnlockQueue+0x46>
break;
800cf82: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800cf84: 687b ldr r3, [r7, #4]
800cf86: 22ff movs r2, #255 ; 0xff
800cf88: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
taskEXIT_CRITICAL();
800cf8c: f001 fb06 bl 800e59c <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
800cf90: f001 fad2 bl 800e538 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800cf94: 687b ldr r3, [r7, #4]
800cf96: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cf9a: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cf9c: e011 b.n 800cfc2 <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cf9e: 687b ldr r3, [r7, #4]
800cfa0: 691b ldr r3, [r3, #16]
800cfa2: 2b00 cmp r3, #0
800cfa4: d012 beq.n 800cfcc <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cfa6: 687b ldr r3, [r7, #4]
800cfa8: 3310 adds r3, #16
800cfaa: 4618 mov r0, r3
800cfac: f000 fdc2 bl 800db34 <xTaskRemoveFromEventList>
800cfb0: 4603 mov r3, r0
800cfb2: 2b00 cmp r3, #0
800cfb4: d001 beq.n 800cfba <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
800cfb6: f000 fe9b bl 800dcf0 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
800cfba: 7bbb ldrb r3, [r7, #14]
800cfbc: 3b01 subs r3, #1
800cfbe: b2db uxtb r3, r3
800cfc0: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cfc2: f997 300e ldrsb.w r3, [r7, #14]
800cfc6: 2b00 cmp r3, #0
800cfc8: dce9 bgt.n 800cf9e <prvUnlockQueue+0x60>
800cfca: e000 b.n 800cfce <prvUnlockQueue+0x90>
}
else
{
break;
800cfcc: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
800cfce: 687b ldr r3, [r7, #4]
800cfd0: 22ff movs r2, #255 ; 0xff
800cfd2: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
taskEXIT_CRITICAL();
800cfd6: f001 fae1 bl 800e59c <vPortExitCritical>
}
800cfda: bf00 nop
800cfdc: 3710 adds r7, #16
800cfde: 46bd mov sp, r7
800cfe0: bd80 pop {r7, pc}
0800cfe2 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
800cfe2: b580 push {r7, lr}
800cfe4: b084 sub sp, #16
800cfe6: af00 add r7, sp, #0
800cfe8: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800cfea: f001 faa5 bl 800e538 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
800cfee: 687b ldr r3, [r7, #4]
800cff0: 6b9b ldr r3, [r3, #56] ; 0x38
800cff2: 2b00 cmp r3, #0
800cff4: d102 bne.n 800cffc <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
800cff6: 2301 movs r3, #1
800cff8: 60fb str r3, [r7, #12]
800cffa: e001 b.n 800d000 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
800cffc: 2300 movs r3, #0
800cffe: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800d000: f001 facc bl 800e59c <vPortExitCritical>
return xReturn;
800d004: 68fb ldr r3, [r7, #12]
}
800d006: 4618 mov r0, r3
800d008: 3710 adds r7, #16
800d00a: 46bd mov sp, r7
800d00c: bd80 pop {r7, pc}
0800d00e <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
800d00e: b580 push {r7, lr}
800d010: b084 sub sp, #16
800d012: af00 add r7, sp, #0
800d014: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800d016: f001 fa8f bl 800e538 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
800d01a: 687b ldr r3, [r7, #4]
800d01c: 6b9a ldr r2, [r3, #56] ; 0x38
800d01e: 687b ldr r3, [r7, #4]
800d020: 6bdb ldr r3, [r3, #60] ; 0x3c
800d022: 429a cmp r2, r3
800d024: d102 bne.n 800d02c <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
800d026: 2301 movs r3, #1
800d028: 60fb str r3, [r7, #12]
800d02a: e001 b.n 800d030 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
800d02c: 2300 movs r3, #0
800d02e: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800d030: f001 fab4 bl 800e59c <vPortExitCritical>
return xReturn;
800d034: 68fb ldr r3, [r7, #12]
}
800d036: 4618 mov r0, r3
800d038: 3710 adds r7, #16
800d03a: 46bd mov sp, r7
800d03c: bd80 pop {r7, pc}
0800d03e <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
800d03e: b580 push {r7, lr}
800d040: b08e sub sp, #56 ; 0x38
800d042: af04 add r7, sp, #16
800d044: 60f8 str r0, [r7, #12]
800d046: 60b9 str r1, [r7, #8]
800d048: 607a str r2, [r7, #4]
800d04a: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800d04c: 6b7b ldr r3, [r7, #52] ; 0x34
800d04e: 2b00 cmp r3, #0
800d050: d10b bne.n 800d06a <xTaskCreateStatic+0x2c>
__asm volatile
800d052: f04f 0350 mov.w r3, #80 ; 0x50
800d056: b672 cpsid i
800d058: f383 8811 msr BASEPRI, r3
800d05c: f3bf 8f6f isb sy
800d060: f3bf 8f4f dsb sy
800d064: b662 cpsie i
800d066: 623b str r3, [r7, #32]
800d068: e7fe b.n 800d068 <xTaskCreateStatic+0x2a>
configASSERT( pxTaskBuffer != NULL );
800d06a: 6bbb ldr r3, [r7, #56] ; 0x38
800d06c: 2b00 cmp r3, #0
800d06e: d10b bne.n 800d088 <xTaskCreateStatic+0x4a>
800d070: f04f 0350 mov.w r3, #80 ; 0x50
800d074: b672 cpsid i
800d076: f383 8811 msr BASEPRI, r3
800d07a: f3bf 8f6f isb sy
800d07e: f3bf 8f4f dsb sy
800d082: b662 cpsie i
800d084: 61fb str r3, [r7, #28]
800d086: e7fe b.n 800d086 <xTaskCreateStatic+0x48>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
800d088: 2358 movs r3, #88 ; 0x58
800d08a: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800d08c: 693b ldr r3, [r7, #16]
800d08e: 2b58 cmp r3, #88 ; 0x58
800d090: d00b beq.n 800d0aa <xTaskCreateStatic+0x6c>
800d092: f04f 0350 mov.w r3, #80 ; 0x50
800d096: b672 cpsid i
800d098: f383 8811 msr BASEPRI, r3
800d09c: f3bf 8f6f isb sy
800d0a0: f3bf 8f4f dsb sy
800d0a4: b662 cpsie i
800d0a6: 61bb str r3, [r7, #24]
800d0a8: e7fe b.n 800d0a8 <xTaskCreateStatic+0x6a>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800d0aa: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800d0ac: 6bbb ldr r3, [r7, #56] ; 0x38
800d0ae: 2b00 cmp r3, #0
800d0b0: d01e beq.n 800d0f0 <xTaskCreateStatic+0xb2>
800d0b2: 6b7b ldr r3, [r7, #52] ; 0x34
800d0b4: 2b00 cmp r3, #0
800d0b6: d01b beq.n 800d0f0 <xTaskCreateStatic+0xb2>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800d0b8: 6bbb ldr r3, [r7, #56] ; 0x38
800d0ba: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800d0bc: 6a7b ldr r3, [r7, #36] ; 0x24
800d0be: 6b7a ldr r2, [r7, #52] ; 0x34
800d0c0: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
800d0c2: 6a7b ldr r3, [r7, #36] ; 0x24
800d0c4: 2202 movs r2, #2
800d0c6: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800d0ca: 2300 movs r3, #0
800d0cc: 9303 str r3, [sp, #12]
800d0ce: 6a7b ldr r3, [r7, #36] ; 0x24
800d0d0: 9302 str r3, [sp, #8]
800d0d2: f107 0314 add.w r3, r7, #20
800d0d6: 9301 str r3, [sp, #4]
800d0d8: 6b3b ldr r3, [r7, #48] ; 0x30
800d0da: 9300 str r3, [sp, #0]
800d0dc: 683b ldr r3, [r7, #0]
800d0de: 687a ldr r2, [r7, #4]
800d0e0: 68b9 ldr r1, [r7, #8]
800d0e2: 68f8 ldr r0, [r7, #12]
800d0e4: f000 f850 bl 800d188 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d0e8: 6a78 ldr r0, [r7, #36] ; 0x24
800d0ea: f000 f8e1 bl 800d2b0 <prvAddNewTaskToReadyList>
800d0ee: e001 b.n 800d0f4 <xTaskCreateStatic+0xb6>
}
else
{
xReturn = NULL;
800d0f0: 2300 movs r3, #0
800d0f2: 617b str r3, [r7, #20]
}
return xReturn;
800d0f4: 697b ldr r3, [r7, #20]
}
800d0f6: 4618 mov r0, r3
800d0f8: 3728 adds r7, #40 ; 0x28
800d0fa: 46bd mov sp, r7
800d0fc: bd80 pop {r7, pc}
0800d0fe <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
800d0fe: b580 push {r7, lr}
800d100: b08c sub sp, #48 ; 0x30
800d102: af04 add r7, sp, #16
800d104: 60f8 str r0, [r7, #12]
800d106: 60b9 str r1, [r7, #8]
800d108: 603b str r3, [r7, #0]
800d10a: 4613 mov r3, r2
800d10c: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
800d10e: 88fb ldrh r3, [r7, #6]
800d110: 009b lsls r3, r3, #2
800d112: 4618 mov r0, r3
800d114: f001 fb32 bl 800e77c <pvPortMalloc>
800d118: 6178 str r0, [r7, #20]
if( pxStack != NULL )
800d11a: 697b ldr r3, [r7, #20]
800d11c: 2b00 cmp r3, #0
800d11e: d00e beq.n 800d13e <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
800d120: 2058 movs r0, #88 ; 0x58
800d122: f001 fb2b bl 800e77c <pvPortMalloc>
800d126: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
800d128: 69fb ldr r3, [r7, #28]
800d12a: 2b00 cmp r3, #0
800d12c: d003 beq.n 800d136 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
800d12e: 69fb ldr r3, [r7, #28]
800d130: 697a ldr r2, [r7, #20]
800d132: 631a str r2, [r3, #48] ; 0x30
800d134: e005 b.n 800d142 <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
800d136: 6978 ldr r0, [r7, #20]
800d138: f001 fbec bl 800e914 <vPortFree>
800d13c: e001 b.n 800d142 <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
800d13e: 2300 movs r3, #0
800d140: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
800d142: 69fb ldr r3, [r7, #28]
800d144: 2b00 cmp r3, #0
800d146: d017 beq.n 800d178 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
800d148: 69fb ldr r3, [r7, #28]
800d14a: 2200 movs r2, #0
800d14c: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
800d150: 88fa ldrh r2, [r7, #6]
800d152: 2300 movs r3, #0
800d154: 9303 str r3, [sp, #12]
800d156: 69fb ldr r3, [r7, #28]
800d158: 9302 str r3, [sp, #8]
800d15a: 6afb ldr r3, [r7, #44] ; 0x2c
800d15c: 9301 str r3, [sp, #4]
800d15e: 6abb ldr r3, [r7, #40] ; 0x28
800d160: 9300 str r3, [sp, #0]
800d162: 683b ldr r3, [r7, #0]
800d164: 68b9 ldr r1, [r7, #8]
800d166: 68f8 ldr r0, [r7, #12]
800d168: f000 f80e bl 800d188 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d16c: 69f8 ldr r0, [r7, #28]
800d16e: f000 f89f bl 800d2b0 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
800d172: 2301 movs r3, #1
800d174: 61bb str r3, [r7, #24]
800d176: e002 b.n 800d17e <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
800d178: f04f 33ff mov.w r3, #4294967295
800d17c: 61bb str r3, [r7, #24]
}
return xReturn;
800d17e: 69bb ldr r3, [r7, #24]
}
800d180: 4618 mov r0, r3
800d182: 3720 adds r7, #32
800d184: 46bd mov sp, r7
800d186: bd80 pop {r7, pc}
0800d188 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
800d188: b580 push {r7, lr}
800d18a: b088 sub sp, #32
800d18c: af00 add r7, sp, #0
800d18e: 60f8 str r0, [r7, #12]
800d190: 60b9 str r1, [r7, #8]
800d192: 607a str r2, [r7, #4]
800d194: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
800d196: 6b3b ldr r3, [r7, #48] ; 0x30
800d198: 6b18 ldr r0, [r3, #48] ; 0x30
800d19a: 687b ldr r3, [r7, #4]
800d19c: 009b lsls r3, r3, #2
800d19e: 461a mov r2, r3
800d1a0: 21a5 movs r1, #165 ; 0xa5
800d1a2: f00d ff2f bl 801b004 <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
800d1a6: 6b3b ldr r3, [r7, #48] ; 0x30
800d1a8: 6b1a ldr r2, [r3, #48] ; 0x30
800d1aa: 6879 ldr r1, [r7, #4]
800d1ac: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000
800d1b0: 440b add r3, r1
800d1b2: 009b lsls r3, r3, #2
800d1b4: 4413 add r3, r2
800d1b6: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
800d1b8: 69bb ldr r3, [r7, #24]
800d1ba: f023 0307 bic.w r3, r3, #7
800d1be: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
800d1c0: 69bb ldr r3, [r7, #24]
800d1c2: f003 0307 and.w r3, r3, #7
800d1c6: 2b00 cmp r3, #0
800d1c8: d00b beq.n 800d1e2 <prvInitialiseNewTask+0x5a>
800d1ca: f04f 0350 mov.w r3, #80 ; 0x50
800d1ce: b672 cpsid i
800d1d0: f383 8811 msr BASEPRI, r3
800d1d4: f3bf 8f6f isb sy
800d1d8: f3bf 8f4f dsb sy
800d1dc: b662 cpsie i
800d1de: 617b str r3, [r7, #20]
800d1e0: e7fe b.n 800d1e0 <prvInitialiseNewTask+0x58>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
800d1e2: 68bb ldr r3, [r7, #8]
800d1e4: 2b00 cmp r3, #0
800d1e6: d01f beq.n 800d228 <prvInitialiseNewTask+0xa0>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d1e8: 2300 movs r3, #0
800d1ea: 61fb str r3, [r7, #28]
800d1ec: e012 b.n 800d214 <prvInitialiseNewTask+0x8c>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
800d1ee: 68ba ldr r2, [r7, #8]
800d1f0: 69fb ldr r3, [r7, #28]
800d1f2: 4413 add r3, r2
800d1f4: 7819 ldrb r1, [r3, #0]
800d1f6: 6b3a ldr r2, [r7, #48] ; 0x30
800d1f8: 69fb ldr r3, [r7, #28]
800d1fa: 4413 add r3, r2
800d1fc: 3334 adds r3, #52 ; 0x34
800d1fe: 460a mov r2, r1
800d200: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
800d202: 68ba ldr r2, [r7, #8]
800d204: 69fb ldr r3, [r7, #28]
800d206: 4413 add r3, r2
800d208: 781b ldrb r3, [r3, #0]
800d20a: 2b00 cmp r3, #0
800d20c: d006 beq.n 800d21c <prvInitialiseNewTask+0x94>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d20e: 69fb ldr r3, [r7, #28]
800d210: 3301 adds r3, #1
800d212: 61fb str r3, [r7, #28]
800d214: 69fb ldr r3, [r7, #28]
800d216: 2b0f cmp r3, #15
800d218: d9e9 bls.n 800d1ee <prvInitialiseNewTask+0x66>
800d21a: e000 b.n 800d21e <prvInitialiseNewTask+0x96>
{
break;
800d21c: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
800d21e: 6b3b ldr r3, [r7, #48] ; 0x30
800d220: 2200 movs r2, #0
800d222: f883 2043 strb.w r2, [r3, #67] ; 0x43
800d226: e003 b.n 800d230 <prvInitialiseNewTask+0xa8>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
800d228: 6b3b ldr r3, [r7, #48] ; 0x30
800d22a: 2200 movs r2, #0
800d22c: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
800d230: 6abb ldr r3, [r7, #40] ; 0x28
800d232: 2b06 cmp r3, #6
800d234: d901 bls.n 800d23a <prvInitialiseNewTask+0xb2>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
800d236: 2306 movs r3, #6
800d238: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
800d23a: 6b3b ldr r3, [r7, #48] ; 0x30
800d23c: 6aba ldr r2, [r7, #40] ; 0x28
800d23e: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
800d240: 6b3b ldr r3, [r7, #48] ; 0x30
800d242: 6aba ldr r2, [r7, #40] ; 0x28
800d244: 645a str r2, [r3, #68] ; 0x44
pxNewTCB->uxMutexesHeld = 0;
800d246: 6b3b ldr r3, [r7, #48] ; 0x30
800d248: 2200 movs r2, #0
800d24a: 649a str r2, [r3, #72] ; 0x48
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
800d24c: 6b3b ldr r3, [r7, #48] ; 0x30
800d24e: 3304 adds r3, #4
800d250: 4618 mov r0, r3
800d252: f7fe fe91 bl 800bf78 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
800d256: 6b3b ldr r3, [r7, #48] ; 0x30
800d258: 3318 adds r3, #24
800d25a: 4618 mov r0, r3
800d25c: f7fe fe8c bl 800bf78 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
800d260: 6b3b ldr r3, [r7, #48] ; 0x30
800d262: 6b3a ldr r2, [r7, #48] ; 0x30
800d264: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d266: 6abb ldr r3, [r7, #40] ; 0x28
800d268: f1c3 0207 rsb r2, r3, #7
800d26c: 6b3b ldr r3, [r7, #48] ; 0x30
800d26e: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800d270: 6b3b ldr r3, [r7, #48] ; 0x30
800d272: 6b3a ldr r2, [r7, #48] ; 0x30
800d274: 625a str r2, [r3, #36] ; 0x24
}
#endif /* portCRITICAL_NESTING_IN_TCB */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
{
pxNewTCB->pxTaskTag = NULL;
800d276: 6b3b ldr r3, [r7, #48] ; 0x30
800d278: 2200 movs r2, #0
800d27a: 64da str r2, [r3, #76] ; 0x4c
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
800d27c: 6b3b ldr r3, [r7, #48] ; 0x30
800d27e: 2200 movs r2, #0
800d280: 651a str r2, [r3, #80] ; 0x50
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
800d282: 6b3b ldr r3, [r7, #48] ; 0x30
800d284: 2200 movs r2, #0
800d286: f883 2054 strb.w r2, [r3, #84] ; 0x54
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
800d28a: 683a ldr r2, [r7, #0]
800d28c: 68f9 ldr r1, [r7, #12]
800d28e: 69b8 ldr r0, [r7, #24]
800d290: f001 f84c bl 800e32c <pxPortInitialiseStack>
800d294: 4602 mov r2, r0
800d296: 6b3b ldr r3, [r7, #48] ; 0x30
800d298: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
800d29a: 6afb ldr r3, [r7, #44] ; 0x2c
800d29c: 2b00 cmp r3, #0
800d29e: d002 beq.n 800d2a6 <prvInitialiseNewTask+0x11e>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
800d2a0: 6afb ldr r3, [r7, #44] ; 0x2c
800d2a2: 6b3a ldr r2, [r7, #48] ; 0x30
800d2a4: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d2a6: bf00 nop
800d2a8: 3720 adds r7, #32
800d2aa: 46bd mov sp, r7
800d2ac: bd80 pop {r7, pc}
...
0800d2b0 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
800d2b0: b580 push {r7, lr}
800d2b2: b082 sub sp, #8
800d2b4: af00 add r7, sp, #0
800d2b6: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
800d2b8: f001 f93e bl 800e538 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
800d2bc: 4b2a ldr r3, [pc, #168] ; (800d368 <prvAddNewTaskToReadyList+0xb8>)
800d2be: 681b ldr r3, [r3, #0]
800d2c0: 3301 adds r3, #1
800d2c2: 4a29 ldr r2, [pc, #164] ; (800d368 <prvAddNewTaskToReadyList+0xb8>)
800d2c4: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
800d2c6: 4b29 ldr r3, [pc, #164] ; (800d36c <prvAddNewTaskToReadyList+0xbc>)
800d2c8: 681b ldr r3, [r3, #0]
800d2ca: 2b00 cmp r3, #0
800d2cc: d109 bne.n 800d2e2 <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
800d2ce: 4a27 ldr r2, [pc, #156] ; (800d36c <prvAddNewTaskToReadyList+0xbc>)
800d2d0: 687b ldr r3, [r7, #4]
800d2d2: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
800d2d4: 4b24 ldr r3, [pc, #144] ; (800d368 <prvAddNewTaskToReadyList+0xb8>)
800d2d6: 681b ldr r3, [r3, #0]
800d2d8: 2b01 cmp r3, #1
800d2da: d110 bne.n 800d2fe <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
800d2dc: f000 fd2e bl 800dd3c <prvInitialiseTaskLists>
800d2e0: e00d b.n 800d2fe <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
800d2e2: 4b23 ldr r3, [pc, #140] ; (800d370 <prvAddNewTaskToReadyList+0xc0>)
800d2e4: 681b ldr r3, [r3, #0]
800d2e6: 2b00 cmp r3, #0
800d2e8: d109 bne.n 800d2fe <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
800d2ea: 4b20 ldr r3, [pc, #128] ; (800d36c <prvAddNewTaskToReadyList+0xbc>)
800d2ec: 681b ldr r3, [r3, #0]
800d2ee: 6ada ldr r2, [r3, #44] ; 0x2c
800d2f0: 687b ldr r3, [r7, #4]
800d2f2: 6adb ldr r3, [r3, #44] ; 0x2c
800d2f4: 429a cmp r2, r3
800d2f6: d802 bhi.n 800d2fe <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
800d2f8: 4a1c ldr r2, [pc, #112] ; (800d36c <prvAddNewTaskToReadyList+0xbc>)
800d2fa: 687b ldr r3, [r7, #4]
800d2fc: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
800d2fe: 4b1d ldr r3, [pc, #116] ; (800d374 <prvAddNewTaskToReadyList+0xc4>)
800d300: 681b ldr r3, [r3, #0]
800d302: 3301 adds r3, #1
800d304: 4a1b ldr r2, [pc, #108] ; (800d374 <prvAddNewTaskToReadyList+0xc4>)
800d306: 6013 str r3, [r2, #0]
pxNewTCB->uxTCBNumber = uxTaskNumber;
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
800d308: 687b ldr r3, [r7, #4]
800d30a: 6adb ldr r3, [r3, #44] ; 0x2c
800d30c: 2201 movs r2, #1
800d30e: 409a lsls r2, r3
800d310: 4b19 ldr r3, [pc, #100] ; (800d378 <prvAddNewTaskToReadyList+0xc8>)
800d312: 681b ldr r3, [r3, #0]
800d314: 4313 orrs r3, r2
800d316: 4a18 ldr r2, [pc, #96] ; (800d378 <prvAddNewTaskToReadyList+0xc8>)
800d318: 6013 str r3, [r2, #0]
800d31a: 687b ldr r3, [r7, #4]
800d31c: 6ada ldr r2, [r3, #44] ; 0x2c
800d31e: 4613 mov r3, r2
800d320: 009b lsls r3, r3, #2
800d322: 4413 add r3, r2
800d324: 009b lsls r3, r3, #2
800d326: 4a15 ldr r2, [pc, #84] ; (800d37c <prvAddNewTaskToReadyList+0xcc>)
800d328: 441a add r2, r3
800d32a: 687b ldr r3, [r7, #4]
800d32c: 3304 adds r3, #4
800d32e: 4619 mov r1, r3
800d330: 4610 mov r0, r2
800d332: f7fe fe2e bl 800bf92 <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
800d336: f001 f931 bl 800e59c <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
800d33a: 4b0d ldr r3, [pc, #52] ; (800d370 <prvAddNewTaskToReadyList+0xc0>)
800d33c: 681b ldr r3, [r3, #0]
800d33e: 2b00 cmp r3, #0
800d340: d00e beq.n 800d360 <prvAddNewTaskToReadyList+0xb0>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
800d342: 4b0a ldr r3, [pc, #40] ; (800d36c <prvAddNewTaskToReadyList+0xbc>)
800d344: 681b ldr r3, [r3, #0]
800d346: 6ada ldr r2, [r3, #44] ; 0x2c
800d348: 687b ldr r3, [r7, #4]
800d34a: 6adb ldr r3, [r3, #44] ; 0x2c
800d34c: 429a cmp r2, r3
800d34e: d207 bcs.n 800d360 <prvAddNewTaskToReadyList+0xb0>
{
taskYIELD_IF_USING_PREEMPTION();
800d350: 4b0b ldr r3, [pc, #44] ; (800d380 <prvAddNewTaskToReadyList+0xd0>)
800d352: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d356: 601a str r2, [r3, #0]
800d358: f3bf 8f4f dsb sy
800d35c: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d360: bf00 nop
800d362: 3708 adds r7, #8
800d364: 46bd mov sp, r7
800d366: bd80 pop {r7, pc}
800d368: 2000068c .word 0x2000068c
800d36c: 2000058c .word 0x2000058c
800d370: 20000698 .word 0x20000698
800d374: 200006a8 .word 0x200006a8
800d378: 20000694 .word 0x20000694
800d37c: 20000590 .word 0x20000590
800d380: e000ed04 .word 0xe000ed04
0800d384 <vTaskDelete>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
void vTaskDelete( TaskHandle_t xTaskToDelete )
{
800d384: b580 push {r7, lr}
800d386: b084 sub sp, #16
800d388: af00 add r7, sp, #0
800d38a: 6078 str r0, [r7, #4]
TCB_t *pxTCB;
taskENTER_CRITICAL();
800d38c: f001 f8d4 bl 800e538 <vPortEnterCritical>
{
/* If null is passed in here then it is the calling task that is
being deleted. */
pxTCB = prvGetTCBFromHandle( xTaskToDelete );
800d390: 687b ldr r3, [r7, #4]
800d392: 2b00 cmp r3, #0
800d394: d102 bne.n 800d39c <vTaskDelete+0x18>
800d396: 4b39 ldr r3, [pc, #228] ; (800d47c <vTaskDelete+0xf8>)
800d398: 681b ldr r3, [r3, #0]
800d39a: e000 b.n 800d39e <vTaskDelete+0x1a>
800d39c: 687b ldr r3, [r7, #4]
800d39e: 60fb str r3, [r7, #12]
/* Remove task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800d3a0: 68fb ldr r3, [r7, #12]
800d3a2: 3304 adds r3, #4
800d3a4: 4618 mov r0, r3
800d3a6: f7fe fe51 bl 800c04c <uxListRemove>
800d3aa: 4603 mov r3, r0
800d3ac: 2b00 cmp r3, #0
800d3ae: d115 bne.n 800d3dc <vTaskDelete+0x58>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800d3b0: 68fb ldr r3, [r7, #12]
800d3b2: 6ada ldr r2, [r3, #44] ; 0x2c
800d3b4: 4932 ldr r1, [pc, #200] ; (800d480 <vTaskDelete+0xfc>)
800d3b6: 4613 mov r3, r2
800d3b8: 009b lsls r3, r3, #2
800d3ba: 4413 add r3, r2
800d3bc: 009b lsls r3, r3, #2
800d3be: 440b add r3, r1
800d3c0: 681b ldr r3, [r3, #0]
800d3c2: 2b00 cmp r3, #0
800d3c4: d10a bne.n 800d3dc <vTaskDelete+0x58>
800d3c6: 68fb ldr r3, [r7, #12]
800d3c8: 6adb ldr r3, [r3, #44] ; 0x2c
800d3ca: 2201 movs r2, #1
800d3cc: fa02 f303 lsl.w r3, r2, r3
800d3d0: 43da mvns r2, r3
800d3d2: 4b2c ldr r3, [pc, #176] ; (800d484 <vTaskDelete+0x100>)
800d3d4: 681b ldr r3, [r3, #0]
800d3d6: 4013 ands r3, r2
800d3d8: 4a2a ldr r2, [pc, #168] ; (800d484 <vTaskDelete+0x100>)
800d3da: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Is the task waiting on an event also? */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d3dc: 68fb ldr r3, [r7, #12]
800d3de: 6a9b ldr r3, [r3, #40] ; 0x28
800d3e0: 2b00 cmp r3, #0
800d3e2: d004 beq.n 800d3ee <vTaskDelete+0x6a>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d3e4: 68fb ldr r3, [r7, #12]
800d3e6: 3318 adds r3, #24
800d3e8: 4618 mov r0, r3
800d3ea: f7fe fe2f bl 800c04c <uxListRemove>
/* Increment the uxTaskNumber also so kernel aware debuggers can
detect that the task lists need re-generating. This is done before
portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
not return. */
uxTaskNumber++;
800d3ee: 4b26 ldr r3, [pc, #152] ; (800d488 <vTaskDelete+0x104>)
800d3f0: 681b ldr r3, [r3, #0]
800d3f2: 3301 adds r3, #1
800d3f4: 4a24 ldr r2, [pc, #144] ; (800d488 <vTaskDelete+0x104>)
800d3f6: 6013 str r3, [r2, #0]
if( pxTCB == pxCurrentTCB )
800d3f8: 4b20 ldr r3, [pc, #128] ; (800d47c <vTaskDelete+0xf8>)
800d3fa: 681b ldr r3, [r3, #0]
800d3fc: 68fa ldr r2, [r7, #12]
800d3fe: 429a cmp r2, r3
800d400: d10b bne.n 800d41a <vTaskDelete+0x96>
/* A task is deleting itself. This cannot complete within the
task itself, as a context switch to another task is required.
Place the task in the termination list. The idle task will
check the termination list and free up any memory allocated by
the scheduler for the TCB and stack of the deleted task. */
vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
800d402: 68fb ldr r3, [r7, #12]
800d404: 3304 adds r3, #4
800d406: 4619 mov r1, r3
800d408: 4820 ldr r0, [pc, #128] ; (800d48c <vTaskDelete+0x108>)
800d40a: f7fe fdc2 bl 800bf92 <vListInsertEnd>
/* Increment the ucTasksDeleted variable so the idle task knows
there is a task that has been deleted and that it should therefore
check the xTasksWaitingTermination list. */
++uxDeletedTasksWaitingCleanUp;
800d40e: 4b20 ldr r3, [pc, #128] ; (800d490 <vTaskDelete+0x10c>)
800d410: 681b ldr r3, [r3, #0]
800d412: 3301 adds r3, #1
800d414: 4a1e ldr r2, [pc, #120] ; (800d490 <vTaskDelete+0x10c>)
800d416: 6013 str r3, [r2, #0]
800d418: e009 b.n 800d42e <vTaskDelete+0xaa>
required. */
portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
}
else
{
--uxCurrentNumberOfTasks;
800d41a: 4b1e ldr r3, [pc, #120] ; (800d494 <vTaskDelete+0x110>)
800d41c: 681b ldr r3, [r3, #0]
800d41e: 3b01 subs r3, #1
800d420: 4a1c ldr r2, [pc, #112] ; (800d494 <vTaskDelete+0x110>)
800d422: 6013 str r3, [r2, #0]
prvDeleteTCB( pxTCB );
800d424: 68f8 ldr r0, [r7, #12]
800d426: f000 fcf5 bl 800de14 <prvDeleteTCB>
/* Reset the next expected unblock time in case it referred to
the task that has just been deleted. */
prvResetNextTaskUnblockTime();
800d42a: f000 fd23 bl 800de74 <prvResetNextTaskUnblockTime>
}
traceTASK_DELETE( pxTCB );
}
taskEXIT_CRITICAL();
800d42e: f001 f8b5 bl 800e59c <vPortExitCritical>
/* Force a reschedule if it is the currently running task that has just
been deleted. */
if( xSchedulerRunning != pdFALSE )
800d432: 4b19 ldr r3, [pc, #100] ; (800d498 <vTaskDelete+0x114>)
800d434: 681b ldr r3, [r3, #0]
800d436: 2b00 cmp r3, #0
800d438: d01c beq.n 800d474 <vTaskDelete+0xf0>
{
if( pxTCB == pxCurrentTCB )
800d43a: 4b10 ldr r3, [pc, #64] ; (800d47c <vTaskDelete+0xf8>)
800d43c: 681b ldr r3, [r3, #0]
800d43e: 68fa ldr r2, [r7, #12]
800d440: 429a cmp r2, r3
800d442: d117 bne.n 800d474 <vTaskDelete+0xf0>
{
configASSERT( uxSchedulerSuspended == 0 );
800d444: 4b15 ldr r3, [pc, #84] ; (800d49c <vTaskDelete+0x118>)
800d446: 681b ldr r3, [r3, #0]
800d448: 2b00 cmp r3, #0
800d44a: d00b beq.n 800d464 <vTaskDelete+0xe0>
800d44c: f04f 0350 mov.w r3, #80 ; 0x50
800d450: b672 cpsid i
800d452: f383 8811 msr BASEPRI, r3
800d456: f3bf 8f6f isb sy
800d45a: f3bf 8f4f dsb sy
800d45e: b662 cpsie i
800d460: 60bb str r3, [r7, #8]
800d462: e7fe b.n 800d462 <vTaskDelete+0xde>
portYIELD_WITHIN_API();
800d464: 4b0e ldr r3, [pc, #56] ; (800d4a0 <vTaskDelete+0x11c>)
800d466: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d46a: 601a str r2, [r3, #0]
800d46c: f3bf 8f4f dsb sy
800d470: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800d474: bf00 nop
800d476: 3710 adds r7, #16
800d478: 46bd mov sp, r7
800d47a: bd80 pop {r7, pc}
800d47c: 2000058c .word 0x2000058c
800d480: 20000590 .word 0x20000590
800d484: 20000694 .word 0x20000694
800d488: 200006a8 .word 0x200006a8
800d48c: 20000660 .word 0x20000660
800d490: 20000674 .word 0x20000674
800d494: 2000068c .word 0x2000068c
800d498: 20000698 .word 0x20000698
800d49c: 200006b4 .word 0x200006b4
800d4a0: e000ed04 .word 0xe000ed04
0800d4a4 <vTaskDelayUntil>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelayUntil == 1 )
void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
{
800d4a4: b580 push {r7, lr}
800d4a6: b08a sub sp, #40 ; 0x28
800d4a8: af00 add r7, sp, #0
800d4aa: 6078 str r0, [r7, #4]
800d4ac: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
800d4ae: 2300 movs r3, #0
800d4b0: 627b str r3, [r7, #36] ; 0x24
configASSERT( pxPreviousWakeTime );
800d4b2: 687b ldr r3, [r7, #4]
800d4b4: 2b00 cmp r3, #0
800d4b6: d10b bne.n 800d4d0 <vTaskDelayUntil+0x2c>
800d4b8: f04f 0350 mov.w r3, #80 ; 0x50
800d4bc: b672 cpsid i
800d4be: f383 8811 msr BASEPRI, r3
800d4c2: f3bf 8f6f isb sy
800d4c6: f3bf 8f4f dsb sy
800d4ca: b662 cpsie i
800d4cc: 617b str r3, [r7, #20]
800d4ce: e7fe b.n 800d4ce <vTaskDelayUntil+0x2a>
configASSERT( ( xTimeIncrement > 0U ) );
800d4d0: 683b ldr r3, [r7, #0]
800d4d2: 2b00 cmp r3, #0
800d4d4: d10b bne.n 800d4ee <vTaskDelayUntil+0x4a>
800d4d6: f04f 0350 mov.w r3, #80 ; 0x50
800d4da: b672 cpsid i
800d4dc: f383 8811 msr BASEPRI, r3
800d4e0: f3bf 8f6f isb sy
800d4e4: f3bf 8f4f dsb sy
800d4e8: b662 cpsie i
800d4ea: 613b str r3, [r7, #16]
800d4ec: e7fe b.n 800d4ec <vTaskDelayUntil+0x48>
configASSERT( uxSchedulerSuspended == 0 );
800d4ee: 4b2a ldr r3, [pc, #168] ; (800d598 <vTaskDelayUntil+0xf4>)
800d4f0: 681b ldr r3, [r3, #0]
800d4f2: 2b00 cmp r3, #0
800d4f4: d00b beq.n 800d50e <vTaskDelayUntil+0x6a>
800d4f6: f04f 0350 mov.w r3, #80 ; 0x50
800d4fa: b672 cpsid i
800d4fc: f383 8811 msr BASEPRI, r3
800d500: f3bf 8f6f isb sy
800d504: f3bf 8f4f dsb sy
800d508: b662 cpsie i
800d50a: 60fb str r3, [r7, #12]
800d50c: e7fe b.n 800d50c <vTaskDelayUntil+0x68>
vTaskSuspendAll();
800d50e: f000 f8e1 bl 800d6d4 <vTaskSuspendAll>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount;
800d512: 4b22 ldr r3, [pc, #136] ; (800d59c <vTaskDelayUntil+0xf8>)
800d514: 681b ldr r3, [r3, #0]
800d516: 623b str r3, [r7, #32]
/* Generate the tick time at which the task wants to wake. */
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
800d518: 687b ldr r3, [r7, #4]
800d51a: 681b ldr r3, [r3, #0]
800d51c: 683a ldr r2, [r7, #0]
800d51e: 4413 add r3, r2
800d520: 61fb str r3, [r7, #28]
if( xConstTickCount < *pxPreviousWakeTime )
800d522: 687b ldr r3, [r7, #4]
800d524: 681b ldr r3, [r3, #0]
800d526: 6a3a ldr r2, [r7, #32]
800d528: 429a cmp r2, r3
800d52a: d20b bcs.n 800d544 <vTaskDelayUntil+0xa0>
/* The tick count has overflowed since this function was
lasted called. In this case the only time we should ever
actually delay is if the wake time has also overflowed,
and the wake time is greater than the tick time. When this
is the case it is as if neither time had overflowed. */
if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
800d52c: 687b ldr r3, [r7, #4]
800d52e: 681b ldr r3, [r3, #0]
800d530: 69fa ldr r2, [r7, #28]
800d532: 429a cmp r2, r3
800d534: d211 bcs.n 800d55a <vTaskDelayUntil+0xb6>
800d536: 69fa ldr r2, [r7, #28]
800d538: 6a3b ldr r3, [r7, #32]
800d53a: 429a cmp r2, r3
800d53c: d90d bls.n 800d55a <vTaskDelayUntil+0xb6>
{
xShouldDelay = pdTRUE;
800d53e: 2301 movs r3, #1
800d540: 627b str r3, [r7, #36] ; 0x24
800d542: e00a b.n 800d55a <vTaskDelayUntil+0xb6>
else
{
/* The tick time has not overflowed. In this case we will
delay if either the wake time has overflowed, and/or the
tick time is less than the wake time. */
if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
800d544: 687b ldr r3, [r7, #4]
800d546: 681b ldr r3, [r3, #0]
800d548: 69fa ldr r2, [r7, #28]
800d54a: 429a cmp r2, r3
800d54c: d303 bcc.n 800d556 <vTaskDelayUntil+0xb2>
800d54e: 69fa ldr r2, [r7, #28]
800d550: 6a3b ldr r3, [r7, #32]
800d552: 429a cmp r2, r3
800d554: d901 bls.n 800d55a <vTaskDelayUntil+0xb6>
{
xShouldDelay = pdTRUE;
800d556: 2301 movs r3, #1
800d558: 627b str r3, [r7, #36] ; 0x24
mtCOVERAGE_TEST_MARKER();
}
}
/* Update the wake time ready for the next call. */
*pxPreviousWakeTime = xTimeToWake;
800d55a: 687b ldr r3, [r7, #4]
800d55c: 69fa ldr r2, [r7, #28]
800d55e: 601a str r2, [r3, #0]
if( xShouldDelay != pdFALSE )
800d560: 6a7b ldr r3, [r7, #36] ; 0x24
800d562: 2b00 cmp r3, #0
800d564: d006 beq.n 800d574 <vTaskDelayUntil+0xd0>
{
traceTASK_DELAY_UNTIL( xTimeToWake );
/* prvAddCurrentTaskToDelayedList() needs the block time, not
the time to wake, so subtract the current tick count. */
prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
800d566: 69fa ldr r2, [r7, #28]
800d568: 6a3b ldr r3, [r7, #32]
800d56a: 1ad3 subs r3, r2, r3
800d56c: 2100 movs r1, #0
800d56e: 4618 mov r0, r3
800d570: f000 fe76 bl 800e260 <prvAddCurrentTaskToDelayedList>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
xAlreadyYielded = xTaskResumeAll();
800d574: f000 f8bc bl 800d6f0 <xTaskResumeAll>
800d578: 61b8 str r0, [r7, #24]
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d57a: 69bb ldr r3, [r7, #24]
800d57c: 2b00 cmp r3, #0
800d57e: d107 bne.n 800d590 <vTaskDelayUntil+0xec>
{
portYIELD_WITHIN_API();
800d580: 4b07 ldr r3, [pc, #28] ; (800d5a0 <vTaskDelayUntil+0xfc>)
800d582: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d586: 601a str r2, [r3, #0]
800d588: f3bf 8f4f dsb sy
800d58c: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d590: bf00 nop
800d592: 3728 adds r7, #40 ; 0x28
800d594: 46bd mov sp, r7
800d596: bd80 pop {r7, pc}
800d598: 200006b4 .word 0x200006b4
800d59c: 20000690 .word 0x20000690
800d5a0: e000ed04 .word 0xe000ed04
0800d5a4 <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
800d5a4: b580 push {r7, lr}
800d5a6: b084 sub sp, #16
800d5a8: af00 add r7, sp, #0
800d5aa: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
800d5ac: 2300 movs r3, #0
800d5ae: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
800d5b0: 687b ldr r3, [r7, #4]
800d5b2: 2b00 cmp r3, #0
800d5b4: d018 beq.n 800d5e8 <vTaskDelay+0x44>
{
configASSERT( uxSchedulerSuspended == 0 );
800d5b6: 4b14 ldr r3, [pc, #80] ; (800d608 <vTaskDelay+0x64>)
800d5b8: 681b ldr r3, [r3, #0]
800d5ba: 2b00 cmp r3, #0
800d5bc: d00b beq.n 800d5d6 <vTaskDelay+0x32>
800d5be: f04f 0350 mov.w r3, #80 ; 0x50
800d5c2: b672 cpsid i
800d5c4: f383 8811 msr BASEPRI, r3
800d5c8: f3bf 8f6f isb sy
800d5cc: f3bf 8f4f dsb sy
800d5d0: b662 cpsie i
800d5d2: 60bb str r3, [r7, #8]
800d5d4: e7fe b.n 800d5d4 <vTaskDelay+0x30>
vTaskSuspendAll();
800d5d6: f000 f87d bl 800d6d4 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
800d5da: 2100 movs r1, #0
800d5dc: 6878 ldr r0, [r7, #4]
800d5de: f000 fe3f bl 800e260 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
800d5e2: f000 f885 bl 800d6f0 <xTaskResumeAll>
800d5e6: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d5e8: 68fb ldr r3, [r7, #12]
800d5ea: 2b00 cmp r3, #0
800d5ec: d107 bne.n 800d5fe <vTaskDelay+0x5a>
{
portYIELD_WITHIN_API();
800d5ee: 4b07 ldr r3, [pc, #28] ; (800d60c <vTaskDelay+0x68>)
800d5f0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d5f4: 601a str r2, [r3, #0]
800d5f6: f3bf 8f4f dsb sy
800d5fa: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d5fe: bf00 nop
800d600: 3710 adds r7, #16
800d602: 46bd mov sp, r7
800d604: bd80 pop {r7, pc}
800d606: bf00 nop
800d608: 200006b4 .word 0x200006b4
800d60c: e000ed04 .word 0xe000ed04
0800d610 <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
800d610: b580 push {r7, lr}
800d612: b08a sub sp, #40 ; 0x28
800d614: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
800d616: 2300 movs r3, #0
800d618: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
800d61a: 2300 movs r3, #0
800d61c: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
800d61e: 463a mov r2, r7
800d620: 1d39 adds r1, r7, #4
800d622: f107 0308 add.w r3, r7, #8
800d626: 4618 mov r0, r3
800d628: f7f2 ffdc bl 80005e4 <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
800d62c: 6839 ldr r1, [r7, #0]
800d62e: 687b ldr r3, [r7, #4]
800d630: 68ba ldr r2, [r7, #8]
800d632: 9202 str r2, [sp, #8]
800d634: 9301 str r3, [sp, #4]
800d636: 2300 movs r3, #0
800d638: 9300 str r3, [sp, #0]
800d63a: 2300 movs r3, #0
800d63c: 460a mov r2, r1
800d63e: 491f ldr r1, [pc, #124] ; (800d6bc <vTaskStartScheduler+0xac>)
800d640: 481f ldr r0, [pc, #124] ; (800d6c0 <vTaskStartScheduler+0xb0>)
800d642: f7ff fcfc bl 800d03e <xTaskCreateStatic>
800d646: 4602 mov r2, r0
800d648: 4b1e ldr r3, [pc, #120] ; (800d6c4 <vTaskStartScheduler+0xb4>)
800d64a: 601a str r2, [r3, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
800d64c: 4b1d ldr r3, [pc, #116] ; (800d6c4 <vTaskStartScheduler+0xb4>)
800d64e: 681b ldr r3, [r3, #0]
800d650: 2b00 cmp r3, #0
800d652: d002 beq.n 800d65a <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
800d654: 2301 movs r3, #1
800d656: 617b str r3, [r7, #20]
800d658: e001 b.n 800d65e <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
800d65a: 2300 movs r3, #0
800d65c: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
800d65e: 697b ldr r3, [r7, #20]
800d660: 2b01 cmp r3, #1
800d662: d117 bne.n 800d694 <vTaskStartScheduler+0x84>
800d664: f04f 0350 mov.w r3, #80 ; 0x50
800d668: b672 cpsid i
800d66a: f383 8811 msr BASEPRI, r3
800d66e: f3bf 8f6f isb sy
800d672: f3bf 8f4f dsb sy
800d676: b662 cpsie i
800d678: 613b str r3, [r7, #16]
structure specific to the task that will run first. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
800d67a: 4b13 ldr r3, [pc, #76] ; (800d6c8 <vTaskStartScheduler+0xb8>)
800d67c: f04f 32ff mov.w r2, #4294967295
800d680: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
800d682: 4b12 ldr r3, [pc, #72] ; (800d6cc <vTaskStartScheduler+0xbc>)
800d684: 2201 movs r2, #1
800d686: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
800d688: 4b11 ldr r3, [pc, #68] ; (800d6d0 <vTaskStartScheduler+0xc0>)
800d68a: 2200 movs r2, #0
800d68c: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
800d68e: f000 fed7 bl 800e440 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
800d692: e00f b.n 800d6b4 <vTaskStartScheduler+0xa4>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
800d694: 697b ldr r3, [r7, #20]
800d696: f1b3 3fff cmp.w r3, #4294967295
800d69a: d10b bne.n 800d6b4 <vTaskStartScheduler+0xa4>
800d69c: f04f 0350 mov.w r3, #80 ; 0x50
800d6a0: b672 cpsid i
800d6a2: f383 8811 msr BASEPRI, r3
800d6a6: f3bf 8f6f isb sy
800d6aa: f3bf 8f4f dsb sy
800d6ae: b662 cpsie i
800d6b0: 60fb str r3, [r7, #12]
800d6b2: e7fe b.n 800d6b2 <vTaskStartScheduler+0xa2>
}
800d6b4: bf00 nop
800d6b6: 3718 adds r7, #24
800d6b8: 46bd mov sp, r7
800d6ba: bd80 pop {r7, pc}
800d6bc: 0801bfcc .word 0x0801bfcc
800d6c0: 0800dd09 .word 0x0800dd09
800d6c4: 200006b0 .word 0x200006b0
800d6c8: 200006ac .word 0x200006ac
800d6cc: 20000698 .word 0x20000698
800d6d0: 20000690 .word 0x20000690
0800d6d4 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
800d6d4: b480 push {r7}
800d6d6: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
800d6d8: 4b04 ldr r3, [pc, #16] ; (800d6ec <vTaskSuspendAll+0x18>)
800d6da: 681b ldr r3, [r3, #0]
800d6dc: 3301 adds r3, #1
800d6de: 4a03 ldr r2, [pc, #12] ; (800d6ec <vTaskSuspendAll+0x18>)
800d6e0: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
800d6e2: bf00 nop
800d6e4: 46bd mov sp, r7
800d6e6: f85d 7b04 ldr.w r7, [sp], #4
800d6ea: 4770 bx lr
800d6ec: 200006b4 .word 0x200006b4
0800d6f0 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
800d6f0: b580 push {r7, lr}
800d6f2: b084 sub sp, #16
800d6f4: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
800d6f6: 2300 movs r3, #0
800d6f8: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
800d6fa: 2300 movs r3, #0
800d6fc: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
800d6fe: 4b42 ldr r3, [pc, #264] ; (800d808 <xTaskResumeAll+0x118>)
800d700: 681b ldr r3, [r3, #0]
800d702: 2b00 cmp r3, #0
800d704: d10b bne.n 800d71e <xTaskResumeAll+0x2e>
800d706: f04f 0350 mov.w r3, #80 ; 0x50
800d70a: b672 cpsid i
800d70c: f383 8811 msr BASEPRI, r3
800d710: f3bf 8f6f isb sy
800d714: f3bf 8f4f dsb sy
800d718: b662 cpsie i
800d71a: 603b str r3, [r7, #0]
800d71c: e7fe b.n 800d71c <xTaskResumeAll+0x2c>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
800d71e: f000 ff0b bl 800e538 <vPortEnterCritical>
{
--uxSchedulerSuspended;
800d722: 4b39 ldr r3, [pc, #228] ; (800d808 <xTaskResumeAll+0x118>)
800d724: 681b ldr r3, [r3, #0]
800d726: 3b01 subs r3, #1
800d728: 4a37 ldr r2, [pc, #220] ; (800d808 <xTaskResumeAll+0x118>)
800d72a: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d72c: 4b36 ldr r3, [pc, #216] ; (800d808 <xTaskResumeAll+0x118>)
800d72e: 681b ldr r3, [r3, #0]
800d730: 2b00 cmp r3, #0
800d732: d161 bne.n 800d7f8 <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
800d734: 4b35 ldr r3, [pc, #212] ; (800d80c <xTaskResumeAll+0x11c>)
800d736: 681b ldr r3, [r3, #0]
800d738: 2b00 cmp r3, #0
800d73a: d05d beq.n 800d7f8 <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d73c: e02e b.n 800d79c <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d73e: 4b34 ldr r3, [pc, #208] ; (800d810 <xTaskResumeAll+0x120>)
800d740: 68db ldr r3, [r3, #12]
800d742: 68db ldr r3, [r3, #12]
800d744: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d746: 68fb ldr r3, [r7, #12]
800d748: 3318 adds r3, #24
800d74a: 4618 mov r0, r3
800d74c: f7fe fc7e bl 800c04c <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d750: 68fb ldr r3, [r7, #12]
800d752: 3304 adds r3, #4
800d754: 4618 mov r0, r3
800d756: f7fe fc79 bl 800c04c <uxListRemove>
prvAddTaskToReadyList( pxTCB );
800d75a: 68fb ldr r3, [r7, #12]
800d75c: 6adb ldr r3, [r3, #44] ; 0x2c
800d75e: 2201 movs r2, #1
800d760: 409a lsls r2, r3
800d762: 4b2c ldr r3, [pc, #176] ; (800d814 <xTaskResumeAll+0x124>)
800d764: 681b ldr r3, [r3, #0]
800d766: 4313 orrs r3, r2
800d768: 4a2a ldr r2, [pc, #168] ; (800d814 <xTaskResumeAll+0x124>)
800d76a: 6013 str r3, [r2, #0]
800d76c: 68fb ldr r3, [r7, #12]
800d76e: 6ada ldr r2, [r3, #44] ; 0x2c
800d770: 4613 mov r3, r2
800d772: 009b lsls r3, r3, #2
800d774: 4413 add r3, r2
800d776: 009b lsls r3, r3, #2
800d778: 4a27 ldr r2, [pc, #156] ; (800d818 <xTaskResumeAll+0x128>)
800d77a: 441a add r2, r3
800d77c: 68fb ldr r3, [r7, #12]
800d77e: 3304 adds r3, #4
800d780: 4619 mov r1, r3
800d782: 4610 mov r0, r2
800d784: f7fe fc05 bl 800bf92 <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d788: 68fb ldr r3, [r7, #12]
800d78a: 6ada ldr r2, [r3, #44] ; 0x2c
800d78c: 4b23 ldr r3, [pc, #140] ; (800d81c <xTaskResumeAll+0x12c>)
800d78e: 681b ldr r3, [r3, #0]
800d790: 6adb ldr r3, [r3, #44] ; 0x2c
800d792: 429a cmp r2, r3
800d794: d302 bcc.n 800d79c <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
800d796: 4b22 ldr r3, [pc, #136] ; (800d820 <xTaskResumeAll+0x130>)
800d798: 2201 movs r2, #1
800d79a: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d79c: 4b1c ldr r3, [pc, #112] ; (800d810 <xTaskResumeAll+0x120>)
800d79e: 681b ldr r3, [r3, #0]
800d7a0: 2b00 cmp r3, #0
800d7a2: d1cc bne.n 800d73e <xTaskResumeAll+0x4e>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
800d7a4: 68fb ldr r3, [r7, #12]
800d7a6: 2b00 cmp r3, #0
800d7a8: d001 beq.n 800d7ae <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
800d7aa: f000 fb63 bl 800de74 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
800d7ae: 4b1d ldr r3, [pc, #116] ; (800d824 <xTaskResumeAll+0x134>)
800d7b0: 681b ldr r3, [r3, #0]
800d7b2: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
800d7b4: 687b ldr r3, [r7, #4]
800d7b6: 2b00 cmp r3, #0
800d7b8: d010 beq.n 800d7dc <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
800d7ba: f000 f859 bl 800d870 <xTaskIncrementTick>
800d7be: 4603 mov r3, r0
800d7c0: 2b00 cmp r3, #0
800d7c2: d002 beq.n 800d7ca <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
800d7c4: 4b16 ldr r3, [pc, #88] ; (800d820 <xTaskResumeAll+0x130>)
800d7c6: 2201 movs r2, #1
800d7c8: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
800d7ca: 687b ldr r3, [r7, #4]
800d7cc: 3b01 subs r3, #1
800d7ce: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
800d7d0: 687b ldr r3, [r7, #4]
800d7d2: 2b00 cmp r3, #0
800d7d4: d1f1 bne.n 800d7ba <xTaskResumeAll+0xca>
uxPendedTicks = 0;
800d7d6: 4b13 ldr r3, [pc, #76] ; (800d824 <xTaskResumeAll+0x134>)
800d7d8: 2200 movs r2, #0
800d7da: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
800d7dc: 4b10 ldr r3, [pc, #64] ; (800d820 <xTaskResumeAll+0x130>)
800d7de: 681b ldr r3, [r3, #0]
800d7e0: 2b00 cmp r3, #0
800d7e2: d009 beq.n 800d7f8 <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
800d7e4: 2301 movs r3, #1
800d7e6: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
800d7e8: 4b0f ldr r3, [pc, #60] ; (800d828 <xTaskResumeAll+0x138>)
800d7ea: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d7ee: 601a str r2, [r3, #0]
800d7f0: f3bf 8f4f dsb sy
800d7f4: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
800d7f8: f000 fed0 bl 800e59c <vPortExitCritical>
return xAlreadyYielded;
800d7fc: 68bb ldr r3, [r7, #8]
}
800d7fe: 4618 mov r0, r3
800d800: 3710 adds r7, #16
800d802: 46bd mov sp, r7
800d804: bd80 pop {r7, pc}
800d806: bf00 nop
800d808: 200006b4 .word 0x200006b4
800d80c: 2000068c .word 0x2000068c
800d810: 2000064c .word 0x2000064c
800d814: 20000694 .word 0x20000694
800d818: 20000590 .word 0x20000590
800d81c: 2000058c .word 0x2000058c
800d820: 200006a0 .word 0x200006a0
800d824: 2000069c .word 0x2000069c
800d828: e000ed04 .word 0xe000ed04
0800d82c <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
800d82c: b480 push {r7}
800d82e: b083 sub sp, #12
800d830: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
800d832: 4b05 ldr r3, [pc, #20] ; (800d848 <xTaskGetTickCount+0x1c>)
800d834: 681b ldr r3, [r3, #0]
800d836: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
800d838: 687b ldr r3, [r7, #4]
}
800d83a: 4618 mov r0, r3
800d83c: 370c adds r7, #12
800d83e: 46bd mov sp, r7
800d840: f85d 7b04 ldr.w r7, [sp], #4
800d844: 4770 bx lr
800d846: bf00 nop
800d848: 20000690 .word 0x20000690
0800d84c <xTaskGetTickCountFromISR>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCountFromISR( void )
{
800d84c: b580 push {r7, lr}
800d84e: b082 sub sp, #8
800d850: af00 add r7, sp, #0
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800d852: f000 ff51 bl 800e6f8 <vPortValidateInterruptPriority>
uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
800d856: 2300 movs r3, #0
800d858: 607b str r3, [r7, #4]
{
xReturn = xTickCount;
800d85a: 4b04 ldr r3, [pc, #16] ; (800d86c <xTaskGetTickCountFromISR+0x20>)
800d85c: 681b ldr r3, [r3, #0]
800d85e: 603b str r3, [r7, #0]
}
portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800d860: 683b ldr r3, [r7, #0]
}
800d862: 4618 mov r0, r3
800d864: 3708 adds r7, #8
800d866: 46bd mov sp, r7
800d868: bd80 pop {r7, pc}
800d86a: bf00 nop
800d86c: 20000690 .word 0x20000690
0800d870 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
800d870: b580 push {r7, lr}
800d872: b086 sub sp, #24
800d874: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
800d876: 2300 movs r3, #0
800d878: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d87a: 4b4f ldr r3, [pc, #316] ; (800d9b8 <xTaskIncrementTick+0x148>)
800d87c: 681b ldr r3, [r3, #0]
800d87e: 2b00 cmp r3, #0
800d880: f040 8089 bne.w 800d996 <xTaskIncrementTick+0x126>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
800d884: 4b4d ldr r3, [pc, #308] ; (800d9bc <xTaskIncrementTick+0x14c>)
800d886: 681b ldr r3, [r3, #0]
800d888: 3301 adds r3, #1
800d88a: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
800d88c: 4a4b ldr r2, [pc, #300] ; (800d9bc <xTaskIncrementTick+0x14c>)
800d88e: 693b ldr r3, [r7, #16]
800d890: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
800d892: 693b ldr r3, [r7, #16]
800d894: 2b00 cmp r3, #0
800d896: d121 bne.n 800d8dc <xTaskIncrementTick+0x6c>
{
taskSWITCH_DELAYED_LISTS();
800d898: 4b49 ldr r3, [pc, #292] ; (800d9c0 <xTaskIncrementTick+0x150>)
800d89a: 681b ldr r3, [r3, #0]
800d89c: 681b ldr r3, [r3, #0]
800d89e: 2b00 cmp r3, #0
800d8a0: d00b beq.n 800d8ba <xTaskIncrementTick+0x4a>
800d8a2: f04f 0350 mov.w r3, #80 ; 0x50
800d8a6: b672 cpsid i
800d8a8: f383 8811 msr BASEPRI, r3
800d8ac: f3bf 8f6f isb sy
800d8b0: f3bf 8f4f dsb sy
800d8b4: b662 cpsie i
800d8b6: 603b str r3, [r7, #0]
800d8b8: e7fe b.n 800d8b8 <xTaskIncrementTick+0x48>
800d8ba: 4b41 ldr r3, [pc, #260] ; (800d9c0 <xTaskIncrementTick+0x150>)
800d8bc: 681b ldr r3, [r3, #0]
800d8be: 60fb str r3, [r7, #12]
800d8c0: 4b40 ldr r3, [pc, #256] ; (800d9c4 <xTaskIncrementTick+0x154>)
800d8c2: 681b ldr r3, [r3, #0]
800d8c4: 4a3e ldr r2, [pc, #248] ; (800d9c0 <xTaskIncrementTick+0x150>)
800d8c6: 6013 str r3, [r2, #0]
800d8c8: 4a3e ldr r2, [pc, #248] ; (800d9c4 <xTaskIncrementTick+0x154>)
800d8ca: 68fb ldr r3, [r7, #12]
800d8cc: 6013 str r3, [r2, #0]
800d8ce: 4b3e ldr r3, [pc, #248] ; (800d9c8 <xTaskIncrementTick+0x158>)
800d8d0: 681b ldr r3, [r3, #0]
800d8d2: 3301 adds r3, #1
800d8d4: 4a3c ldr r2, [pc, #240] ; (800d9c8 <xTaskIncrementTick+0x158>)
800d8d6: 6013 str r3, [r2, #0]
800d8d8: f000 facc bl 800de74 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
800d8dc: 4b3b ldr r3, [pc, #236] ; (800d9cc <xTaskIncrementTick+0x15c>)
800d8de: 681b ldr r3, [r3, #0]
800d8e0: 693a ldr r2, [r7, #16]
800d8e2: 429a cmp r2, r3
800d8e4: d348 bcc.n 800d978 <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d8e6: 4b36 ldr r3, [pc, #216] ; (800d9c0 <xTaskIncrementTick+0x150>)
800d8e8: 681b ldr r3, [r3, #0]
800d8ea: 681b ldr r3, [r3, #0]
800d8ec: 2b00 cmp r3, #0
800d8ee: d104 bne.n 800d8fa <xTaskIncrementTick+0x8a>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d8f0: 4b36 ldr r3, [pc, #216] ; (800d9cc <xTaskIncrementTick+0x15c>)
800d8f2: f04f 32ff mov.w r2, #4294967295
800d8f6: 601a str r2, [r3, #0]
break;
800d8f8: e03e b.n 800d978 <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d8fa: 4b31 ldr r3, [pc, #196] ; (800d9c0 <xTaskIncrementTick+0x150>)
800d8fc: 681b ldr r3, [r3, #0]
800d8fe: 68db ldr r3, [r3, #12]
800d900: 68db ldr r3, [r3, #12]
800d902: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
800d904: 68bb ldr r3, [r7, #8]
800d906: 685b ldr r3, [r3, #4]
800d908: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800d90a: 693a ldr r2, [r7, #16]
800d90c: 687b ldr r3, [r7, #4]
800d90e: 429a cmp r2, r3
800d910: d203 bcs.n 800d91a <xTaskIncrementTick+0xaa>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
800d912: 4a2e ldr r2, [pc, #184] ; (800d9cc <xTaskIncrementTick+0x15c>)
800d914: 687b ldr r3, [r7, #4]
800d916: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
800d918: e02e b.n 800d978 <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d91a: 68bb ldr r3, [r7, #8]
800d91c: 3304 adds r3, #4
800d91e: 4618 mov r0, r3
800d920: f7fe fb94 bl 800c04c <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d924: 68bb ldr r3, [r7, #8]
800d926: 6a9b ldr r3, [r3, #40] ; 0x28
800d928: 2b00 cmp r3, #0
800d92a: d004 beq.n 800d936 <xTaskIncrementTick+0xc6>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d92c: 68bb ldr r3, [r7, #8]
800d92e: 3318 adds r3, #24
800d930: 4618 mov r0, r3
800d932: f7fe fb8b bl 800c04c <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800d936: 68bb ldr r3, [r7, #8]
800d938: 6adb ldr r3, [r3, #44] ; 0x2c
800d93a: 2201 movs r2, #1
800d93c: 409a lsls r2, r3
800d93e: 4b24 ldr r3, [pc, #144] ; (800d9d0 <xTaskIncrementTick+0x160>)
800d940: 681b ldr r3, [r3, #0]
800d942: 4313 orrs r3, r2
800d944: 4a22 ldr r2, [pc, #136] ; (800d9d0 <xTaskIncrementTick+0x160>)
800d946: 6013 str r3, [r2, #0]
800d948: 68bb ldr r3, [r7, #8]
800d94a: 6ada ldr r2, [r3, #44] ; 0x2c
800d94c: 4613 mov r3, r2
800d94e: 009b lsls r3, r3, #2
800d950: 4413 add r3, r2
800d952: 009b lsls r3, r3, #2
800d954: 4a1f ldr r2, [pc, #124] ; (800d9d4 <xTaskIncrementTick+0x164>)
800d956: 441a add r2, r3
800d958: 68bb ldr r3, [r7, #8]
800d95a: 3304 adds r3, #4
800d95c: 4619 mov r1, r3
800d95e: 4610 mov r0, r2
800d960: f7fe fb17 bl 800bf92 <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d964: 68bb ldr r3, [r7, #8]
800d966: 6ada ldr r2, [r3, #44] ; 0x2c
800d968: 4b1b ldr r3, [pc, #108] ; (800d9d8 <xTaskIncrementTick+0x168>)
800d96a: 681b ldr r3, [r3, #0]
800d96c: 6adb ldr r3, [r3, #44] ; 0x2c
800d96e: 429a cmp r2, r3
800d970: d3b9 bcc.n 800d8e6 <xTaskIncrementTick+0x76>
{
xSwitchRequired = pdTRUE;
800d972: 2301 movs r3, #1
800d974: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d976: e7b6 b.n 800d8e6 <xTaskIncrementTick+0x76>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800d978: 4b17 ldr r3, [pc, #92] ; (800d9d8 <xTaskIncrementTick+0x168>)
800d97a: 681b ldr r3, [r3, #0]
800d97c: 6ada ldr r2, [r3, #44] ; 0x2c
800d97e: 4915 ldr r1, [pc, #84] ; (800d9d4 <xTaskIncrementTick+0x164>)
800d980: 4613 mov r3, r2
800d982: 009b lsls r3, r3, #2
800d984: 4413 add r3, r2
800d986: 009b lsls r3, r3, #2
800d988: 440b add r3, r1
800d98a: 681b ldr r3, [r3, #0]
800d98c: 2b01 cmp r3, #1
800d98e: d907 bls.n 800d9a0 <xTaskIncrementTick+0x130>
{
xSwitchRequired = pdTRUE;
800d990: 2301 movs r3, #1
800d992: 617b str r3, [r7, #20]
800d994: e004 b.n 800d9a0 <xTaskIncrementTick+0x130>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
800d996: 4b11 ldr r3, [pc, #68] ; (800d9dc <xTaskIncrementTick+0x16c>)
800d998: 681b ldr r3, [r3, #0]
800d99a: 3301 adds r3, #1
800d99c: 4a0f ldr r2, [pc, #60] ; (800d9dc <xTaskIncrementTick+0x16c>)
800d99e: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
800d9a0: 4b0f ldr r3, [pc, #60] ; (800d9e0 <xTaskIncrementTick+0x170>)
800d9a2: 681b ldr r3, [r3, #0]
800d9a4: 2b00 cmp r3, #0
800d9a6: d001 beq.n 800d9ac <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
800d9a8: 2301 movs r3, #1
800d9aa: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
800d9ac: 697b ldr r3, [r7, #20]
}
800d9ae: 4618 mov r0, r3
800d9b0: 3718 adds r7, #24
800d9b2: 46bd mov sp, r7
800d9b4: bd80 pop {r7, pc}
800d9b6: bf00 nop
800d9b8: 200006b4 .word 0x200006b4
800d9bc: 20000690 .word 0x20000690
800d9c0: 20000644 .word 0x20000644
800d9c4: 20000648 .word 0x20000648
800d9c8: 200006a4 .word 0x200006a4
800d9cc: 200006ac .word 0x200006ac
800d9d0: 20000694 .word 0x20000694
800d9d4: 20000590 .word 0x20000590
800d9d8: 2000058c .word 0x2000058c
800d9dc: 2000069c .word 0x2000069c
800d9e0: 200006a0 .word 0x200006a0
0800d9e4 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
800d9e4: b580 push {r7, lr}
800d9e6: b088 sub sp, #32
800d9e8: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
800d9ea: 4b3a ldr r3, [pc, #232] ; (800dad4 <vTaskSwitchContext+0xf0>)
800d9ec: 681b ldr r3, [r3, #0]
800d9ee: 2b00 cmp r3, #0
800d9f0: d003 beq.n 800d9fa <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
800d9f2: 4b39 ldr r3, [pc, #228] ; (800dad8 <vTaskSwitchContext+0xf4>)
800d9f4: 2201 movs r2, #1
800d9f6: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
800d9f8: e067 b.n 800daca <vTaskSwitchContext+0xe6>
xYieldPending = pdFALSE;
800d9fa: 4b37 ldr r3, [pc, #220] ; (800dad8 <vTaskSwitchContext+0xf4>)
800d9fc: 2200 movs r2, #0
800d9fe: 601a str r2, [r3, #0]
taskCHECK_FOR_STACK_OVERFLOW();
800da00: 4b36 ldr r3, [pc, #216] ; (800dadc <vTaskSwitchContext+0xf8>)
800da02: 681b ldr r3, [r3, #0]
800da04: 6b1b ldr r3, [r3, #48] ; 0x30
800da06: 61fb str r3, [r7, #28]
800da08: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5
800da0c: 61bb str r3, [r7, #24]
800da0e: 69fb ldr r3, [r7, #28]
800da10: 681b ldr r3, [r3, #0]
800da12: 69ba ldr r2, [r7, #24]
800da14: 429a cmp r2, r3
800da16: d111 bne.n 800da3c <vTaskSwitchContext+0x58>
800da18: 69fb ldr r3, [r7, #28]
800da1a: 3304 adds r3, #4
800da1c: 681b ldr r3, [r3, #0]
800da1e: 69ba ldr r2, [r7, #24]
800da20: 429a cmp r2, r3
800da22: d10b bne.n 800da3c <vTaskSwitchContext+0x58>
800da24: 69fb ldr r3, [r7, #28]
800da26: 3308 adds r3, #8
800da28: 681b ldr r3, [r3, #0]
800da2a: 69ba ldr r2, [r7, #24]
800da2c: 429a cmp r2, r3
800da2e: d105 bne.n 800da3c <vTaskSwitchContext+0x58>
800da30: 69fb ldr r3, [r7, #28]
800da32: 330c adds r3, #12
800da34: 681b ldr r3, [r3, #0]
800da36: 69ba ldr r2, [r7, #24]
800da38: 429a cmp r2, r3
800da3a: d008 beq.n 800da4e <vTaskSwitchContext+0x6a>
800da3c: 4b27 ldr r3, [pc, #156] ; (800dadc <vTaskSwitchContext+0xf8>)
800da3e: 681a ldr r2, [r3, #0]
800da40: 4b26 ldr r3, [pc, #152] ; (800dadc <vTaskSwitchContext+0xf8>)
800da42: 681b ldr r3, [r3, #0]
800da44: 3334 adds r3, #52 ; 0x34
800da46: 4619 mov r1, r3
800da48: 4610 mov r0, r2
800da4a: f7f2 fdb8 bl 80005be <vApplicationStackOverflowHook>
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800da4e: 4b24 ldr r3, [pc, #144] ; (800dae0 <vTaskSwitchContext+0xfc>)
800da50: 681b ldr r3, [r3, #0]
800da52: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
800da54: 68fb ldr r3, [r7, #12]
800da56: fab3 f383 clz r3, r3
800da5a: 72fb strb r3, [r7, #11]
return ucReturn;
800da5c: 7afb ldrb r3, [r7, #11]
800da5e: f1c3 031f rsb r3, r3, #31
800da62: 617b str r3, [r7, #20]
800da64: 491f ldr r1, [pc, #124] ; (800dae4 <vTaskSwitchContext+0x100>)
800da66: 697a ldr r2, [r7, #20]
800da68: 4613 mov r3, r2
800da6a: 009b lsls r3, r3, #2
800da6c: 4413 add r3, r2
800da6e: 009b lsls r3, r3, #2
800da70: 440b add r3, r1
800da72: 681b ldr r3, [r3, #0]
800da74: 2b00 cmp r3, #0
800da76: d10b bne.n 800da90 <vTaskSwitchContext+0xac>
__asm volatile
800da78: f04f 0350 mov.w r3, #80 ; 0x50
800da7c: b672 cpsid i
800da7e: f383 8811 msr BASEPRI, r3
800da82: f3bf 8f6f isb sy
800da86: f3bf 8f4f dsb sy
800da8a: b662 cpsie i
800da8c: 607b str r3, [r7, #4]
800da8e: e7fe b.n 800da8e <vTaskSwitchContext+0xaa>
800da90: 697a ldr r2, [r7, #20]
800da92: 4613 mov r3, r2
800da94: 009b lsls r3, r3, #2
800da96: 4413 add r3, r2
800da98: 009b lsls r3, r3, #2
800da9a: 4a12 ldr r2, [pc, #72] ; (800dae4 <vTaskSwitchContext+0x100>)
800da9c: 4413 add r3, r2
800da9e: 613b str r3, [r7, #16]
800daa0: 693b ldr r3, [r7, #16]
800daa2: 685b ldr r3, [r3, #4]
800daa4: 685a ldr r2, [r3, #4]
800daa6: 693b ldr r3, [r7, #16]
800daa8: 605a str r2, [r3, #4]
800daaa: 693b ldr r3, [r7, #16]
800daac: 685a ldr r2, [r3, #4]
800daae: 693b ldr r3, [r7, #16]
800dab0: 3308 adds r3, #8
800dab2: 429a cmp r2, r3
800dab4: d104 bne.n 800dac0 <vTaskSwitchContext+0xdc>
800dab6: 693b ldr r3, [r7, #16]
800dab8: 685b ldr r3, [r3, #4]
800daba: 685a ldr r2, [r3, #4]
800dabc: 693b ldr r3, [r7, #16]
800dabe: 605a str r2, [r3, #4]
800dac0: 693b ldr r3, [r7, #16]
800dac2: 685b ldr r3, [r3, #4]
800dac4: 68db ldr r3, [r3, #12]
800dac6: 4a05 ldr r2, [pc, #20] ; (800dadc <vTaskSwitchContext+0xf8>)
800dac8: 6013 str r3, [r2, #0]
}
800daca: bf00 nop
800dacc: 3720 adds r7, #32
800dace: 46bd mov sp, r7
800dad0: bd80 pop {r7, pc}
800dad2: bf00 nop
800dad4: 200006b4 .word 0x200006b4
800dad8: 200006a0 .word 0x200006a0
800dadc: 2000058c .word 0x2000058c
800dae0: 20000694 .word 0x20000694
800dae4: 20000590 .word 0x20000590
0800dae8 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
800dae8: b580 push {r7, lr}
800daea: b084 sub sp, #16
800daec: af00 add r7, sp, #0
800daee: 6078 str r0, [r7, #4]
800daf0: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
800daf2: 687b ldr r3, [r7, #4]
800daf4: 2b00 cmp r3, #0
800daf6: d10b bne.n 800db10 <vTaskPlaceOnEventList+0x28>
800daf8: f04f 0350 mov.w r3, #80 ; 0x50
800dafc: b672 cpsid i
800dafe: f383 8811 msr BASEPRI, r3
800db02: f3bf 8f6f isb sy
800db06: f3bf 8f4f dsb sy
800db0a: b662 cpsie i
800db0c: 60fb str r3, [r7, #12]
800db0e: e7fe b.n 800db0e <vTaskPlaceOnEventList+0x26>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
800db10: 4b07 ldr r3, [pc, #28] ; (800db30 <vTaskPlaceOnEventList+0x48>)
800db12: 681b ldr r3, [r3, #0]
800db14: 3318 adds r3, #24
800db16: 4619 mov r1, r3
800db18: 6878 ldr r0, [r7, #4]
800db1a: f7fe fa5e bl 800bfda <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
800db1e: 2101 movs r1, #1
800db20: 6838 ldr r0, [r7, #0]
800db22: f000 fb9d bl 800e260 <prvAddCurrentTaskToDelayedList>
}
800db26: bf00 nop
800db28: 3710 adds r7, #16
800db2a: 46bd mov sp, r7
800db2c: bd80 pop {r7, pc}
800db2e: bf00 nop
800db30: 2000058c .word 0x2000058c
0800db34 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
800db34: b580 push {r7, lr}
800db36: b086 sub sp, #24
800db38: af00 add r7, sp, #0
800db3a: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800db3c: 687b ldr r3, [r7, #4]
800db3e: 68db ldr r3, [r3, #12]
800db40: 68db ldr r3, [r3, #12]
800db42: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
800db44: 693b ldr r3, [r7, #16]
800db46: 2b00 cmp r3, #0
800db48: d10b bne.n 800db62 <xTaskRemoveFromEventList+0x2e>
800db4a: f04f 0350 mov.w r3, #80 ; 0x50
800db4e: b672 cpsid i
800db50: f383 8811 msr BASEPRI, r3
800db54: f3bf 8f6f isb sy
800db58: f3bf 8f4f dsb sy
800db5c: b662 cpsie i
800db5e: 60fb str r3, [r7, #12]
800db60: e7fe b.n 800db60 <xTaskRemoveFromEventList+0x2c>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
800db62: 693b ldr r3, [r7, #16]
800db64: 3318 adds r3, #24
800db66: 4618 mov r0, r3
800db68: f7fe fa70 bl 800c04c <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800db6c: 4b1d ldr r3, [pc, #116] ; (800dbe4 <xTaskRemoveFromEventList+0xb0>)
800db6e: 681b ldr r3, [r3, #0]
800db70: 2b00 cmp r3, #0
800db72: d11c bne.n 800dbae <xTaskRemoveFromEventList+0x7a>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
800db74: 693b ldr r3, [r7, #16]
800db76: 3304 adds r3, #4
800db78: 4618 mov r0, r3
800db7a: f7fe fa67 bl 800c04c <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
800db7e: 693b ldr r3, [r7, #16]
800db80: 6adb ldr r3, [r3, #44] ; 0x2c
800db82: 2201 movs r2, #1
800db84: 409a lsls r2, r3
800db86: 4b18 ldr r3, [pc, #96] ; (800dbe8 <xTaskRemoveFromEventList+0xb4>)
800db88: 681b ldr r3, [r3, #0]
800db8a: 4313 orrs r3, r2
800db8c: 4a16 ldr r2, [pc, #88] ; (800dbe8 <xTaskRemoveFromEventList+0xb4>)
800db8e: 6013 str r3, [r2, #0]
800db90: 693b ldr r3, [r7, #16]
800db92: 6ada ldr r2, [r3, #44] ; 0x2c
800db94: 4613 mov r3, r2
800db96: 009b lsls r3, r3, #2
800db98: 4413 add r3, r2
800db9a: 009b lsls r3, r3, #2
800db9c: 4a13 ldr r2, [pc, #76] ; (800dbec <xTaskRemoveFromEventList+0xb8>)
800db9e: 441a add r2, r3
800dba0: 693b ldr r3, [r7, #16]
800dba2: 3304 adds r3, #4
800dba4: 4619 mov r1, r3
800dba6: 4610 mov r0, r2
800dba8: f7fe f9f3 bl 800bf92 <vListInsertEnd>
800dbac: e005 b.n 800dbba <xTaskRemoveFromEventList+0x86>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
800dbae: 693b ldr r3, [r7, #16]
800dbb0: 3318 adds r3, #24
800dbb2: 4619 mov r1, r3
800dbb4: 480e ldr r0, [pc, #56] ; (800dbf0 <xTaskRemoveFromEventList+0xbc>)
800dbb6: f7fe f9ec bl 800bf92 <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
800dbba: 693b ldr r3, [r7, #16]
800dbbc: 6ada ldr r2, [r3, #44] ; 0x2c
800dbbe: 4b0d ldr r3, [pc, #52] ; (800dbf4 <xTaskRemoveFromEventList+0xc0>)
800dbc0: 681b ldr r3, [r3, #0]
800dbc2: 6adb ldr r3, [r3, #44] ; 0x2c
800dbc4: 429a cmp r2, r3
800dbc6: d905 bls.n 800dbd4 <xTaskRemoveFromEventList+0xa0>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
800dbc8: 2301 movs r3, #1
800dbca: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
800dbcc: 4b0a ldr r3, [pc, #40] ; (800dbf8 <xTaskRemoveFromEventList+0xc4>)
800dbce: 2201 movs r2, #1
800dbd0: 601a str r2, [r3, #0]
800dbd2: e001 b.n 800dbd8 <xTaskRemoveFromEventList+0xa4>
}
else
{
xReturn = pdFALSE;
800dbd4: 2300 movs r3, #0
800dbd6: 617b str r3, [r7, #20]
}
return xReturn;
800dbd8: 697b ldr r3, [r7, #20]
}
800dbda: 4618 mov r0, r3
800dbdc: 3718 adds r7, #24
800dbde: 46bd mov sp, r7
800dbe0: bd80 pop {r7, pc}
800dbe2: bf00 nop
800dbe4: 200006b4 .word 0x200006b4
800dbe8: 20000694 .word 0x20000694
800dbec: 20000590 .word 0x20000590
800dbf0: 2000064c .word 0x2000064c
800dbf4: 2000058c .word 0x2000058c
800dbf8: 200006a0 .word 0x200006a0
0800dbfc <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
800dbfc: b480 push {r7}
800dbfe: b083 sub sp, #12
800dc00: af00 add r7, sp, #0
800dc02: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
800dc04: 4b06 ldr r3, [pc, #24] ; (800dc20 <vTaskInternalSetTimeOutState+0x24>)
800dc06: 681a ldr r2, [r3, #0]
800dc08: 687b ldr r3, [r7, #4]
800dc0a: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
800dc0c: 4b05 ldr r3, [pc, #20] ; (800dc24 <vTaskInternalSetTimeOutState+0x28>)
800dc0e: 681a ldr r2, [r3, #0]
800dc10: 687b ldr r3, [r7, #4]
800dc12: 605a str r2, [r3, #4]
}
800dc14: bf00 nop
800dc16: 370c adds r7, #12
800dc18: 46bd mov sp, r7
800dc1a: f85d 7b04 ldr.w r7, [sp], #4
800dc1e: 4770 bx lr
800dc20: 200006a4 .word 0x200006a4
800dc24: 20000690 .word 0x20000690
0800dc28 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
800dc28: b580 push {r7, lr}
800dc2a: b088 sub sp, #32
800dc2c: af00 add r7, sp, #0
800dc2e: 6078 str r0, [r7, #4]
800dc30: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
800dc32: 687b ldr r3, [r7, #4]
800dc34: 2b00 cmp r3, #0
800dc36: d10b bne.n 800dc50 <xTaskCheckForTimeOut+0x28>
800dc38: f04f 0350 mov.w r3, #80 ; 0x50
800dc3c: b672 cpsid i
800dc3e: f383 8811 msr BASEPRI, r3
800dc42: f3bf 8f6f isb sy
800dc46: f3bf 8f4f dsb sy
800dc4a: b662 cpsie i
800dc4c: 613b str r3, [r7, #16]
800dc4e: e7fe b.n 800dc4e <xTaskCheckForTimeOut+0x26>
configASSERT( pxTicksToWait );
800dc50: 683b ldr r3, [r7, #0]
800dc52: 2b00 cmp r3, #0
800dc54: d10b bne.n 800dc6e <xTaskCheckForTimeOut+0x46>
800dc56: f04f 0350 mov.w r3, #80 ; 0x50
800dc5a: b672 cpsid i
800dc5c: f383 8811 msr BASEPRI, r3
800dc60: f3bf 8f6f isb sy
800dc64: f3bf 8f4f dsb sy
800dc68: b662 cpsie i
800dc6a: 60fb str r3, [r7, #12]
800dc6c: e7fe b.n 800dc6c <xTaskCheckForTimeOut+0x44>
taskENTER_CRITICAL();
800dc6e: f000 fc63 bl 800e538 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
800dc72: 4b1d ldr r3, [pc, #116] ; (800dce8 <xTaskCheckForTimeOut+0xc0>)
800dc74: 681b ldr r3, [r3, #0]
800dc76: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800dc78: 687b ldr r3, [r7, #4]
800dc7a: 685b ldr r3, [r3, #4]
800dc7c: 69ba ldr r2, [r7, #24]
800dc7e: 1ad3 subs r3, r2, r3
800dc80: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
800dc82: 683b ldr r3, [r7, #0]
800dc84: 681b ldr r3, [r3, #0]
800dc86: f1b3 3fff cmp.w r3, #4294967295
800dc8a: d102 bne.n 800dc92 <xTaskCheckForTimeOut+0x6a>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
800dc8c: 2300 movs r3, #0
800dc8e: 61fb str r3, [r7, #28]
800dc90: e023 b.n 800dcda <xTaskCheckForTimeOut+0xb2>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
800dc92: 687b ldr r3, [r7, #4]
800dc94: 681a ldr r2, [r3, #0]
800dc96: 4b15 ldr r3, [pc, #84] ; (800dcec <xTaskCheckForTimeOut+0xc4>)
800dc98: 681b ldr r3, [r3, #0]
800dc9a: 429a cmp r2, r3
800dc9c: d007 beq.n 800dcae <xTaskCheckForTimeOut+0x86>
800dc9e: 687b ldr r3, [r7, #4]
800dca0: 685b ldr r3, [r3, #4]
800dca2: 69ba ldr r2, [r7, #24]
800dca4: 429a cmp r2, r3
800dca6: d302 bcc.n 800dcae <xTaskCheckForTimeOut+0x86>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
800dca8: 2301 movs r3, #1
800dcaa: 61fb str r3, [r7, #28]
800dcac: e015 b.n 800dcda <xTaskCheckForTimeOut+0xb2>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
800dcae: 683b ldr r3, [r7, #0]
800dcb0: 681b ldr r3, [r3, #0]
800dcb2: 697a ldr r2, [r7, #20]
800dcb4: 429a cmp r2, r3
800dcb6: d20b bcs.n 800dcd0 <xTaskCheckForTimeOut+0xa8>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
800dcb8: 683b ldr r3, [r7, #0]
800dcba: 681a ldr r2, [r3, #0]
800dcbc: 697b ldr r3, [r7, #20]
800dcbe: 1ad2 subs r2, r2, r3
800dcc0: 683b ldr r3, [r7, #0]
800dcc2: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
800dcc4: 6878 ldr r0, [r7, #4]
800dcc6: f7ff ff99 bl 800dbfc <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
800dcca: 2300 movs r3, #0
800dccc: 61fb str r3, [r7, #28]
800dcce: e004 b.n 800dcda <xTaskCheckForTimeOut+0xb2>
}
else
{
*pxTicksToWait = 0;
800dcd0: 683b ldr r3, [r7, #0]
800dcd2: 2200 movs r2, #0
800dcd4: 601a str r2, [r3, #0]
xReturn = pdTRUE;
800dcd6: 2301 movs r3, #1
800dcd8: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
800dcda: f000 fc5f bl 800e59c <vPortExitCritical>
return xReturn;
800dcde: 69fb ldr r3, [r7, #28]
}
800dce0: 4618 mov r0, r3
800dce2: 3720 adds r7, #32
800dce4: 46bd mov sp, r7
800dce6: bd80 pop {r7, pc}
800dce8: 20000690 .word 0x20000690
800dcec: 200006a4 .word 0x200006a4
0800dcf0 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
800dcf0: b480 push {r7}
800dcf2: af00 add r7, sp, #0
xYieldPending = pdTRUE;
800dcf4: 4b03 ldr r3, [pc, #12] ; (800dd04 <vTaskMissedYield+0x14>)
800dcf6: 2201 movs r2, #1
800dcf8: 601a str r2, [r3, #0]
}
800dcfa: bf00 nop
800dcfc: 46bd mov sp, r7
800dcfe: f85d 7b04 ldr.w r7, [sp], #4
800dd02: 4770 bx lr
800dd04: 200006a0 .word 0x200006a0
0800dd08 <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
800dd08: b580 push {r7, lr}
800dd0a: b082 sub sp, #8
800dd0c: af00 add r7, sp, #0
800dd0e: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
800dd10: f000 f854 bl 800ddbc <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
800dd14: 4b07 ldr r3, [pc, #28] ; (800dd34 <prvIdleTask+0x2c>)
800dd16: 681b ldr r3, [r3, #0]
800dd18: 2b01 cmp r3, #1
800dd1a: d907 bls.n 800dd2c <prvIdleTask+0x24>
{
taskYIELD();
800dd1c: 4b06 ldr r3, [pc, #24] ; (800dd38 <prvIdleTask+0x30>)
800dd1e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800dd22: 601a str r2, [r3, #0]
800dd24: f3bf 8f4f dsb sy
800dd28: f3bf 8f6f isb sy
/* Call the user defined function from within the idle task. This
allows the application designer to add background functionality
without the overhead of a separate task.
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
CALL A FUNCTION THAT MIGHT BLOCK. */
vApplicationIdleHook();
800dd2c: f7f2 fc40 bl 80005b0 <vApplicationIdleHook>
prvCheckTasksWaitingTermination();
800dd30: e7ee b.n 800dd10 <prvIdleTask+0x8>
800dd32: bf00 nop
800dd34: 20000590 .word 0x20000590
800dd38: e000ed04 .word 0xe000ed04
0800dd3c <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800dd3c: b580 push {r7, lr}
800dd3e: b082 sub sp, #8
800dd40: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dd42: 2300 movs r3, #0
800dd44: 607b str r3, [r7, #4]
800dd46: e00c b.n 800dd62 <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
800dd48: 687a ldr r2, [r7, #4]
800dd4a: 4613 mov r3, r2
800dd4c: 009b lsls r3, r3, #2
800dd4e: 4413 add r3, r2
800dd50: 009b lsls r3, r3, #2
800dd52: 4a12 ldr r2, [pc, #72] ; (800dd9c <prvInitialiseTaskLists+0x60>)
800dd54: 4413 add r3, r2
800dd56: 4618 mov r0, r3
800dd58: f7fe f8ee bl 800bf38 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dd5c: 687b ldr r3, [r7, #4]
800dd5e: 3301 adds r3, #1
800dd60: 607b str r3, [r7, #4]
800dd62: 687b ldr r3, [r7, #4]
800dd64: 2b06 cmp r3, #6
800dd66: d9ef bls.n 800dd48 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
800dd68: 480d ldr r0, [pc, #52] ; (800dda0 <prvInitialiseTaskLists+0x64>)
800dd6a: f7fe f8e5 bl 800bf38 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800dd6e: 480d ldr r0, [pc, #52] ; (800dda4 <prvInitialiseTaskLists+0x68>)
800dd70: f7fe f8e2 bl 800bf38 <vListInitialise>
vListInitialise( &xPendingReadyList );
800dd74: 480c ldr r0, [pc, #48] ; (800dda8 <prvInitialiseTaskLists+0x6c>)
800dd76: f7fe f8df bl 800bf38 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800dd7a: 480c ldr r0, [pc, #48] ; (800ddac <prvInitialiseTaskLists+0x70>)
800dd7c: f7fe f8dc bl 800bf38 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
800dd80: 480b ldr r0, [pc, #44] ; (800ddb0 <prvInitialiseTaskLists+0x74>)
800dd82: f7fe f8d9 bl 800bf38 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
800dd86: 4b0b ldr r3, [pc, #44] ; (800ddb4 <prvInitialiseTaskLists+0x78>)
800dd88: 4a05 ldr r2, [pc, #20] ; (800dda0 <prvInitialiseTaskLists+0x64>)
800dd8a: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800dd8c: 4b0a ldr r3, [pc, #40] ; (800ddb8 <prvInitialiseTaskLists+0x7c>)
800dd8e: 4a05 ldr r2, [pc, #20] ; (800dda4 <prvInitialiseTaskLists+0x68>)
800dd90: 601a str r2, [r3, #0]
}
800dd92: bf00 nop
800dd94: 3708 adds r7, #8
800dd96: 46bd mov sp, r7
800dd98: bd80 pop {r7, pc}
800dd9a: bf00 nop
800dd9c: 20000590 .word 0x20000590
800dda0: 2000061c .word 0x2000061c
800dda4: 20000630 .word 0x20000630
800dda8: 2000064c .word 0x2000064c
800ddac: 20000660 .word 0x20000660
800ddb0: 20000678 .word 0x20000678
800ddb4: 20000644 .word 0x20000644
800ddb8: 20000648 .word 0x20000648
0800ddbc <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
800ddbc: b580 push {r7, lr}
800ddbe: b082 sub sp, #8
800ddc0: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800ddc2: e019 b.n 800ddf8 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
800ddc4: f000 fbb8 bl 800e538 <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800ddc8: 4b0f ldr r3, [pc, #60] ; (800de08 <prvCheckTasksWaitingTermination+0x4c>)
800ddca: 68db ldr r3, [r3, #12]
800ddcc: 68db ldr r3, [r3, #12]
800ddce: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800ddd0: 687b ldr r3, [r7, #4]
800ddd2: 3304 adds r3, #4
800ddd4: 4618 mov r0, r3
800ddd6: f7fe f939 bl 800c04c <uxListRemove>
--uxCurrentNumberOfTasks;
800ddda: 4b0c ldr r3, [pc, #48] ; (800de0c <prvCheckTasksWaitingTermination+0x50>)
800dddc: 681b ldr r3, [r3, #0]
800ddde: 3b01 subs r3, #1
800dde0: 4a0a ldr r2, [pc, #40] ; (800de0c <prvCheckTasksWaitingTermination+0x50>)
800dde2: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
800dde4: 4b0a ldr r3, [pc, #40] ; (800de10 <prvCheckTasksWaitingTermination+0x54>)
800dde6: 681b ldr r3, [r3, #0]
800dde8: 3b01 subs r3, #1
800ddea: 4a09 ldr r2, [pc, #36] ; (800de10 <prvCheckTasksWaitingTermination+0x54>)
800ddec: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
800ddee: f000 fbd5 bl 800e59c <vPortExitCritical>
prvDeleteTCB( pxTCB );
800ddf2: 6878 ldr r0, [r7, #4]
800ddf4: f000 f80e bl 800de14 <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800ddf8: 4b05 ldr r3, [pc, #20] ; (800de10 <prvCheckTasksWaitingTermination+0x54>)
800ddfa: 681b ldr r3, [r3, #0]
800ddfc: 2b00 cmp r3, #0
800ddfe: d1e1 bne.n 800ddc4 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
800de00: bf00 nop
800de02: 3708 adds r7, #8
800de04: 46bd mov sp, r7
800de06: bd80 pop {r7, pc}
800de08: 20000660 .word 0x20000660
800de0c: 2000068c .word 0x2000068c
800de10: 20000674 .word 0x20000674
0800de14 <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
800de14: b580 push {r7, lr}
800de16: b084 sub sp, #16
800de18: af00 add r7, sp, #0
800de1a: 6078 str r0, [r7, #4]
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
800de1c: 687b ldr r3, [r7, #4]
800de1e: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de22: 2b00 cmp r3, #0
800de24: d108 bne.n 800de38 <prvDeleteTCB+0x24>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
800de26: 687b ldr r3, [r7, #4]
800de28: 6b1b ldr r3, [r3, #48] ; 0x30
800de2a: 4618 mov r0, r3
800de2c: f000 fd72 bl 800e914 <vPortFree>
vPortFree( pxTCB );
800de30: 6878 ldr r0, [r7, #4]
800de32: f000 fd6f bl 800e914 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
800de36: e019 b.n 800de6c <prvDeleteTCB+0x58>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
800de38: 687b ldr r3, [r7, #4]
800de3a: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de3e: 2b01 cmp r3, #1
800de40: d103 bne.n 800de4a <prvDeleteTCB+0x36>
vPortFree( pxTCB );
800de42: 6878 ldr r0, [r7, #4]
800de44: f000 fd66 bl 800e914 <vPortFree>
}
800de48: e010 b.n 800de6c <prvDeleteTCB+0x58>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
800de4a: 687b ldr r3, [r7, #4]
800de4c: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de50: 2b02 cmp r3, #2
800de52: d00b beq.n 800de6c <prvDeleteTCB+0x58>
800de54: f04f 0350 mov.w r3, #80 ; 0x50
800de58: b672 cpsid i
800de5a: f383 8811 msr BASEPRI, r3
800de5e: f3bf 8f6f isb sy
800de62: f3bf 8f4f dsb sy
800de66: b662 cpsie i
800de68: 60fb str r3, [r7, #12]
800de6a: e7fe b.n 800de6a <prvDeleteTCB+0x56>
}
800de6c: bf00 nop
800de6e: 3710 adds r7, #16
800de70: 46bd mov sp, r7
800de72: bd80 pop {r7, pc}
0800de74 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
800de74: b480 push {r7}
800de76: b083 sub sp, #12
800de78: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800de7a: 4b0c ldr r3, [pc, #48] ; (800deac <prvResetNextTaskUnblockTime+0x38>)
800de7c: 681b ldr r3, [r3, #0]
800de7e: 681b ldr r3, [r3, #0]
800de80: 2b00 cmp r3, #0
800de82: d104 bne.n 800de8e <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
800de84: 4b0a ldr r3, [pc, #40] ; (800deb0 <prvResetNextTaskUnblockTime+0x3c>)
800de86: f04f 32ff mov.w r2, #4294967295
800de8a: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
800de8c: e008 b.n 800dea0 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800de8e: 4b07 ldr r3, [pc, #28] ; (800deac <prvResetNextTaskUnblockTime+0x38>)
800de90: 681b ldr r3, [r3, #0]
800de92: 68db ldr r3, [r3, #12]
800de94: 68db ldr r3, [r3, #12]
800de96: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
800de98: 687b ldr r3, [r7, #4]
800de9a: 685b ldr r3, [r3, #4]
800de9c: 4a04 ldr r2, [pc, #16] ; (800deb0 <prvResetNextTaskUnblockTime+0x3c>)
800de9e: 6013 str r3, [r2, #0]
}
800dea0: bf00 nop
800dea2: 370c adds r7, #12
800dea4: 46bd mov sp, r7
800dea6: f85d 7b04 ldr.w r7, [sp], #4
800deaa: 4770 bx lr
800deac: 20000644 .word 0x20000644
800deb0: 200006ac .word 0x200006ac
0800deb4 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
800deb4: b480 push {r7}
800deb6: b083 sub sp, #12
800deb8: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
800deba: 4b0b ldr r3, [pc, #44] ; (800dee8 <xTaskGetSchedulerState+0x34>)
800debc: 681b ldr r3, [r3, #0]
800debe: 2b00 cmp r3, #0
800dec0: d102 bne.n 800dec8 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800dec2: 2301 movs r3, #1
800dec4: 607b str r3, [r7, #4]
800dec6: e008 b.n 800deda <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800dec8: 4b08 ldr r3, [pc, #32] ; (800deec <xTaskGetSchedulerState+0x38>)
800deca: 681b ldr r3, [r3, #0]
800decc: 2b00 cmp r3, #0
800dece: d102 bne.n 800ded6 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
800ded0: 2302 movs r3, #2
800ded2: 607b str r3, [r7, #4]
800ded4: e001 b.n 800deda <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
800ded6: 2300 movs r3, #0
800ded8: 607b str r3, [r7, #4]
}
}
return xReturn;
800deda: 687b ldr r3, [r7, #4]
}
800dedc: 4618 mov r0, r3
800dede: 370c adds r7, #12
800dee0: 46bd mov sp, r7
800dee2: f85d 7b04 ldr.w r7, [sp], #4
800dee6: 4770 bx lr
800dee8: 20000698 .word 0x20000698
800deec: 200006b4 .word 0x200006b4
0800def0 <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
800def0: b580 push {r7, lr}
800def2: b084 sub sp, #16
800def4: af00 add r7, sp, #0
800def6: 6078 str r0, [r7, #4]
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
800def8: 687b ldr r3, [r7, #4]
800defa: 60bb str r3, [r7, #8]
BaseType_t xReturn = pdFALSE;
800defc: 2300 movs r3, #0
800defe: 60fb str r3, [r7, #12]
/* If the mutex was given back by an interrupt while the queue was
locked then the mutex holder might now be NULL. _RB_ Is this still
needed as interrupts can no longer use mutexes? */
if( pxMutexHolder != NULL )
800df00: 687b ldr r3, [r7, #4]
800df02: 2b00 cmp r3, #0
800df04: d069 beq.n 800dfda <xTaskPriorityInherit+0xea>
{
/* If the holder of the mutex has a priority below the priority of
the task attempting to obtain the mutex then it will temporarily
inherit the priority of the task attempting to obtain the mutex. */
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
800df06: 68bb ldr r3, [r7, #8]
800df08: 6ada ldr r2, [r3, #44] ; 0x2c
800df0a: 4b36 ldr r3, [pc, #216] ; (800dfe4 <xTaskPriorityInherit+0xf4>)
800df0c: 681b ldr r3, [r3, #0]
800df0e: 6adb ldr r3, [r3, #44] ; 0x2c
800df10: 429a cmp r2, r3
800df12: d259 bcs.n 800dfc8 <xTaskPriorityInherit+0xd8>
{
/* Adjust the mutex holder state to account for its new
priority. Only reset the event list item value if the value is
not being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800df14: 68bb ldr r3, [r7, #8]
800df16: 699b ldr r3, [r3, #24]
800df18: 2b00 cmp r3, #0
800df1a: db06 blt.n 800df2a <xTaskPriorityInherit+0x3a>
{
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800df1c: 4b31 ldr r3, [pc, #196] ; (800dfe4 <xTaskPriorityInherit+0xf4>)
800df1e: 681b ldr r3, [r3, #0]
800df20: 6adb ldr r3, [r3, #44] ; 0x2c
800df22: f1c3 0207 rsb r2, r3, #7
800df26: 68bb ldr r3, [r7, #8]
800df28: 619a str r2, [r3, #24]
mtCOVERAGE_TEST_MARKER();
}
/* If the task being modified is in the ready state it will need
to be moved into a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
800df2a: 68bb ldr r3, [r7, #8]
800df2c: 6959 ldr r1, [r3, #20]
800df2e: 68bb ldr r3, [r7, #8]
800df30: 6ada ldr r2, [r3, #44] ; 0x2c
800df32: 4613 mov r3, r2
800df34: 009b lsls r3, r3, #2
800df36: 4413 add r3, r2
800df38: 009b lsls r3, r3, #2
800df3a: 4a2b ldr r2, [pc, #172] ; (800dfe8 <xTaskPriorityInherit+0xf8>)
800df3c: 4413 add r3, r2
800df3e: 4299 cmp r1, r3
800df40: d13a bne.n 800dfb8 <xTaskPriorityInherit+0xc8>
{
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800df42: 68bb ldr r3, [r7, #8]
800df44: 3304 adds r3, #4
800df46: 4618 mov r0, r3
800df48: f7fe f880 bl 800c04c <uxListRemove>
800df4c: 4603 mov r3, r0
800df4e: 2b00 cmp r3, #0
800df50: d115 bne.n 800df7e <xTaskPriorityInherit+0x8e>
{
taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
800df52: 68bb ldr r3, [r7, #8]
800df54: 6ada ldr r2, [r3, #44] ; 0x2c
800df56: 4924 ldr r1, [pc, #144] ; (800dfe8 <xTaskPriorityInherit+0xf8>)
800df58: 4613 mov r3, r2
800df5a: 009b lsls r3, r3, #2
800df5c: 4413 add r3, r2
800df5e: 009b lsls r3, r3, #2
800df60: 440b add r3, r1
800df62: 681b ldr r3, [r3, #0]
800df64: 2b00 cmp r3, #0
800df66: d10a bne.n 800df7e <xTaskPriorityInherit+0x8e>
800df68: 68bb ldr r3, [r7, #8]
800df6a: 6adb ldr r3, [r3, #44] ; 0x2c
800df6c: 2201 movs r2, #1
800df6e: fa02 f303 lsl.w r3, r2, r3
800df72: 43da mvns r2, r3
800df74: 4b1d ldr r3, [pc, #116] ; (800dfec <xTaskPriorityInherit+0xfc>)
800df76: 681b ldr r3, [r3, #0]
800df78: 4013 ands r3, r2
800df7a: 4a1c ldr r2, [pc, #112] ; (800dfec <xTaskPriorityInherit+0xfc>)
800df7c: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800df7e: 4b19 ldr r3, [pc, #100] ; (800dfe4 <xTaskPriorityInherit+0xf4>)
800df80: 681b ldr r3, [r3, #0]
800df82: 6ada ldr r2, [r3, #44] ; 0x2c
800df84: 68bb ldr r3, [r7, #8]
800df86: 62da str r2, [r3, #44] ; 0x2c
prvAddTaskToReadyList( pxMutexHolderTCB );
800df88: 68bb ldr r3, [r7, #8]
800df8a: 6adb ldr r3, [r3, #44] ; 0x2c
800df8c: 2201 movs r2, #1
800df8e: 409a lsls r2, r3
800df90: 4b16 ldr r3, [pc, #88] ; (800dfec <xTaskPriorityInherit+0xfc>)
800df92: 681b ldr r3, [r3, #0]
800df94: 4313 orrs r3, r2
800df96: 4a15 ldr r2, [pc, #84] ; (800dfec <xTaskPriorityInherit+0xfc>)
800df98: 6013 str r3, [r2, #0]
800df9a: 68bb ldr r3, [r7, #8]
800df9c: 6ada ldr r2, [r3, #44] ; 0x2c
800df9e: 4613 mov r3, r2
800dfa0: 009b lsls r3, r3, #2
800dfa2: 4413 add r3, r2
800dfa4: 009b lsls r3, r3, #2
800dfa6: 4a10 ldr r2, [pc, #64] ; (800dfe8 <xTaskPriorityInherit+0xf8>)
800dfa8: 441a add r2, r3
800dfaa: 68bb ldr r3, [r7, #8]
800dfac: 3304 adds r3, #4
800dfae: 4619 mov r1, r3
800dfb0: 4610 mov r0, r2
800dfb2: f7fd ffee bl 800bf92 <vListInsertEnd>
800dfb6: e004 b.n 800dfc2 <xTaskPriorityInherit+0xd2>
}
else
{
/* Just inherit the priority. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800dfb8: 4b0a ldr r3, [pc, #40] ; (800dfe4 <xTaskPriorityInherit+0xf4>)
800dfba: 681b ldr r3, [r3, #0]
800dfbc: 6ada ldr r2, [r3, #44] ; 0x2c
800dfbe: 68bb ldr r3, [r7, #8]
800dfc0: 62da str r2, [r3, #44] ; 0x2c
}
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
/* Inheritance occurred. */
xReturn = pdTRUE;
800dfc2: 2301 movs r3, #1
800dfc4: 60fb str r3, [r7, #12]
800dfc6: e008 b.n 800dfda <xTaskPriorityInherit+0xea>
}
else
{
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
800dfc8: 68bb ldr r3, [r7, #8]
800dfca: 6c5a ldr r2, [r3, #68] ; 0x44
800dfcc: 4b05 ldr r3, [pc, #20] ; (800dfe4 <xTaskPriorityInherit+0xf4>)
800dfce: 681b ldr r3, [r3, #0]
800dfd0: 6adb ldr r3, [r3, #44] ; 0x2c
800dfd2: 429a cmp r2, r3
800dfd4: d201 bcs.n 800dfda <xTaskPriorityInherit+0xea>
current priority of the mutex holder is not lower than the
priority of the task attempting to take the mutex.
Therefore the mutex holder must have already inherited a
priority, but inheritance would have occurred if that had
not been the case. */
xReturn = pdTRUE;
800dfd6: 2301 movs r3, #1
800dfd8: 60fb str r3, [r7, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800dfda: 68fb ldr r3, [r7, #12]
}
800dfdc: 4618 mov r0, r3
800dfde: 3710 adds r7, #16
800dfe0: 46bd mov sp, r7
800dfe2: bd80 pop {r7, pc}
800dfe4: 2000058c .word 0x2000058c
800dfe8: 20000590 .word 0x20000590
800dfec: 20000694 .word 0x20000694
0800dff0 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
800dff0: b580 push {r7, lr}
800dff2: b086 sub sp, #24
800dff4: af00 add r7, sp, #0
800dff6: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
800dff8: 687b ldr r3, [r7, #4]
800dffa: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
800dffc: 2300 movs r3, #0
800dffe: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800e000: 687b ldr r3, [r7, #4]
800e002: 2b00 cmp r3, #0
800e004: d070 beq.n 800e0e8 <xTaskPriorityDisinherit+0xf8>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
800e006: 4b3b ldr r3, [pc, #236] ; (800e0f4 <xTaskPriorityDisinherit+0x104>)
800e008: 681b ldr r3, [r3, #0]
800e00a: 693a ldr r2, [r7, #16]
800e00c: 429a cmp r2, r3
800e00e: d00b beq.n 800e028 <xTaskPriorityDisinherit+0x38>
800e010: f04f 0350 mov.w r3, #80 ; 0x50
800e014: b672 cpsid i
800e016: f383 8811 msr BASEPRI, r3
800e01a: f3bf 8f6f isb sy
800e01e: f3bf 8f4f dsb sy
800e022: b662 cpsie i
800e024: 60fb str r3, [r7, #12]
800e026: e7fe b.n 800e026 <xTaskPriorityDisinherit+0x36>
configASSERT( pxTCB->uxMutexesHeld );
800e028: 693b ldr r3, [r7, #16]
800e02a: 6c9b ldr r3, [r3, #72] ; 0x48
800e02c: 2b00 cmp r3, #0
800e02e: d10b bne.n 800e048 <xTaskPriorityDisinherit+0x58>
800e030: f04f 0350 mov.w r3, #80 ; 0x50
800e034: b672 cpsid i
800e036: f383 8811 msr BASEPRI, r3
800e03a: f3bf 8f6f isb sy
800e03e: f3bf 8f4f dsb sy
800e042: b662 cpsie i
800e044: 60bb str r3, [r7, #8]
800e046: e7fe b.n 800e046 <xTaskPriorityDisinherit+0x56>
( pxTCB->uxMutexesHeld )--;
800e048: 693b ldr r3, [r7, #16]
800e04a: 6c9b ldr r3, [r3, #72] ; 0x48
800e04c: 1e5a subs r2, r3, #1
800e04e: 693b ldr r3, [r7, #16]
800e050: 649a str r2, [r3, #72] ; 0x48
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
800e052: 693b ldr r3, [r7, #16]
800e054: 6ada ldr r2, [r3, #44] ; 0x2c
800e056: 693b ldr r3, [r7, #16]
800e058: 6c5b ldr r3, [r3, #68] ; 0x44
800e05a: 429a cmp r2, r3
800e05c: d044 beq.n 800e0e8 <xTaskPriorityDisinherit+0xf8>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
800e05e: 693b ldr r3, [r7, #16]
800e060: 6c9b ldr r3, [r3, #72] ; 0x48
800e062: 2b00 cmp r3, #0
800e064: d140 bne.n 800e0e8 <xTaskPriorityDisinherit+0xf8>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e066: 693b ldr r3, [r7, #16]
800e068: 3304 adds r3, #4
800e06a: 4618 mov r0, r3
800e06c: f7fd ffee bl 800c04c <uxListRemove>
800e070: 4603 mov r3, r0
800e072: 2b00 cmp r3, #0
800e074: d115 bne.n 800e0a2 <xTaskPriorityDisinherit+0xb2>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800e076: 693b ldr r3, [r7, #16]
800e078: 6ada ldr r2, [r3, #44] ; 0x2c
800e07a: 491f ldr r1, [pc, #124] ; (800e0f8 <xTaskPriorityDisinherit+0x108>)
800e07c: 4613 mov r3, r2
800e07e: 009b lsls r3, r3, #2
800e080: 4413 add r3, r2
800e082: 009b lsls r3, r3, #2
800e084: 440b add r3, r1
800e086: 681b ldr r3, [r3, #0]
800e088: 2b00 cmp r3, #0
800e08a: d10a bne.n 800e0a2 <xTaskPriorityDisinherit+0xb2>
800e08c: 693b ldr r3, [r7, #16]
800e08e: 6adb ldr r3, [r3, #44] ; 0x2c
800e090: 2201 movs r2, #1
800e092: fa02 f303 lsl.w r3, r2, r3
800e096: 43da mvns r2, r3
800e098: 4b18 ldr r3, [pc, #96] ; (800e0fc <xTaskPriorityDisinherit+0x10c>)
800e09a: 681b ldr r3, [r3, #0]
800e09c: 4013 ands r3, r2
800e09e: 4a17 ldr r2, [pc, #92] ; (800e0fc <xTaskPriorityDisinherit+0x10c>)
800e0a0: 6013 str r3, [r2, #0]
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
800e0a2: 693b ldr r3, [r7, #16]
800e0a4: 6c5a ldr r2, [r3, #68] ; 0x44
800e0a6: 693b ldr r3, [r7, #16]
800e0a8: 62da str r2, [r3, #44] ; 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e0aa: 693b ldr r3, [r7, #16]
800e0ac: 6adb ldr r3, [r3, #44] ; 0x2c
800e0ae: f1c3 0207 rsb r2, r3, #7
800e0b2: 693b ldr r3, [r7, #16]
800e0b4: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
800e0b6: 693b ldr r3, [r7, #16]
800e0b8: 6adb ldr r3, [r3, #44] ; 0x2c
800e0ba: 2201 movs r2, #1
800e0bc: 409a lsls r2, r3
800e0be: 4b0f ldr r3, [pc, #60] ; (800e0fc <xTaskPriorityDisinherit+0x10c>)
800e0c0: 681b ldr r3, [r3, #0]
800e0c2: 4313 orrs r3, r2
800e0c4: 4a0d ldr r2, [pc, #52] ; (800e0fc <xTaskPriorityDisinherit+0x10c>)
800e0c6: 6013 str r3, [r2, #0]
800e0c8: 693b ldr r3, [r7, #16]
800e0ca: 6ada ldr r2, [r3, #44] ; 0x2c
800e0cc: 4613 mov r3, r2
800e0ce: 009b lsls r3, r3, #2
800e0d0: 4413 add r3, r2
800e0d2: 009b lsls r3, r3, #2
800e0d4: 4a08 ldr r2, [pc, #32] ; (800e0f8 <xTaskPriorityDisinherit+0x108>)
800e0d6: 441a add r2, r3
800e0d8: 693b ldr r3, [r7, #16]
800e0da: 3304 adds r3, #4
800e0dc: 4619 mov r1, r3
800e0de: 4610 mov r0, r2
800e0e0: f7fd ff57 bl 800bf92 <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
800e0e4: 2301 movs r3, #1
800e0e6: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800e0e8: 697b ldr r3, [r7, #20]
}
800e0ea: 4618 mov r0, r3
800e0ec: 3718 adds r7, #24
800e0ee: 46bd mov sp, r7
800e0f0: bd80 pop {r7, pc}
800e0f2: bf00 nop
800e0f4: 2000058c .word 0x2000058c
800e0f8: 20000590 .word 0x20000590
800e0fc: 20000694 .word 0x20000694
0800e100 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
{
800e100: b580 push {r7, lr}
800e102: b088 sub sp, #32
800e104: af00 add r7, sp, #0
800e106: 6078 str r0, [r7, #4]
800e108: 6039 str r1, [r7, #0]
TCB_t * const pxTCB = pxMutexHolder;
800e10a: 687b ldr r3, [r7, #4]
800e10c: 61bb str r3, [r7, #24]
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
800e10e: 2301 movs r3, #1
800e110: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800e112: 687b ldr r3, [r7, #4]
800e114: 2b00 cmp r3, #0
800e116: f000 8085 beq.w 800e224 <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* If pxMutexHolder is not NULL then the holder must hold at least
one mutex. */
configASSERT( pxTCB->uxMutexesHeld );
800e11a: 69bb ldr r3, [r7, #24]
800e11c: 6c9b ldr r3, [r3, #72] ; 0x48
800e11e: 2b00 cmp r3, #0
800e120: d10b bne.n 800e13a <vTaskPriorityDisinheritAfterTimeout+0x3a>
800e122: f04f 0350 mov.w r3, #80 ; 0x50
800e126: b672 cpsid i
800e128: f383 8811 msr BASEPRI, r3
800e12c: f3bf 8f6f isb sy
800e130: f3bf 8f4f dsb sy
800e134: b662 cpsie i
800e136: 60fb str r3, [r7, #12]
800e138: e7fe b.n 800e138 <vTaskPriorityDisinheritAfterTimeout+0x38>
/* Determine the priority to which the priority of the task that
holds the mutex should be set. This will be the greater of the
holding task's base priority and the priority of the highest
priority task that is waiting to obtain the mutex. */
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
800e13a: 69bb ldr r3, [r7, #24]
800e13c: 6c5b ldr r3, [r3, #68] ; 0x44
800e13e: 683a ldr r2, [r7, #0]
800e140: 429a cmp r2, r3
800e142: d902 bls.n 800e14a <vTaskPriorityDisinheritAfterTimeout+0x4a>
{
uxPriorityToUse = uxHighestPriorityWaitingTask;
800e144: 683b ldr r3, [r7, #0]
800e146: 61fb str r3, [r7, #28]
800e148: e002 b.n 800e150 <vTaskPriorityDisinheritAfterTimeout+0x50>
}
else
{
uxPriorityToUse = pxTCB->uxBasePriority;
800e14a: 69bb ldr r3, [r7, #24]
800e14c: 6c5b ldr r3, [r3, #68] ; 0x44
800e14e: 61fb str r3, [r7, #28]
}
/* Does the priority need to change? */
if( pxTCB->uxPriority != uxPriorityToUse )
800e150: 69bb ldr r3, [r7, #24]
800e152: 6adb ldr r3, [r3, #44] ; 0x2c
800e154: 69fa ldr r2, [r7, #28]
800e156: 429a cmp r2, r3
800e158: d064 beq.n 800e224 <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* Only disinherit if no other mutexes are held. This is a
simplification in the priority inheritance implementation. If
the task that holds the mutex is also holding other mutexes then
the other mutexes may have caused the priority inheritance. */
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
800e15a: 69bb ldr r3, [r7, #24]
800e15c: 6c9b ldr r3, [r3, #72] ; 0x48
800e15e: 697a ldr r2, [r7, #20]
800e160: 429a cmp r2, r3
800e162: d15f bne.n 800e224 <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* If a task has timed out because it already holds the
mutex it was trying to obtain then it cannot of inherited
its own priority. */
configASSERT( pxTCB != pxCurrentTCB );
800e164: 4b31 ldr r3, [pc, #196] ; (800e22c <vTaskPriorityDisinheritAfterTimeout+0x12c>)
800e166: 681b ldr r3, [r3, #0]
800e168: 69ba ldr r2, [r7, #24]
800e16a: 429a cmp r2, r3
800e16c: d10b bne.n 800e186 <vTaskPriorityDisinheritAfterTimeout+0x86>
800e16e: f04f 0350 mov.w r3, #80 ; 0x50
800e172: b672 cpsid i
800e174: f383 8811 msr BASEPRI, r3
800e178: f3bf 8f6f isb sy
800e17c: f3bf 8f4f dsb sy
800e180: b662 cpsie i
800e182: 60bb str r3, [r7, #8]
800e184: e7fe b.n 800e184 <vTaskPriorityDisinheritAfterTimeout+0x84>
/* Disinherit the priority, remembering the previous
priority to facilitate determining the subject task's
state. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
uxPriorityUsedOnEntry = pxTCB->uxPriority;
800e186: 69bb ldr r3, [r7, #24]
800e188: 6adb ldr r3, [r3, #44] ; 0x2c
800e18a: 613b str r3, [r7, #16]
pxTCB->uxPriority = uxPriorityToUse;
800e18c: 69bb ldr r3, [r7, #24]
800e18e: 69fa ldr r2, [r7, #28]
800e190: 62da str r2, [r3, #44] ; 0x2c
/* Only reset the event list item value if the value is not
being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800e192: 69bb ldr r3, [r7, #24]
800e194: 699b ldr r3, [r3, #24]
800e196: 2b00 cmp r3, #0
800e198: db04 blt.n 800e1a4 <vTaskPriorityDisinheritAfterTimeout+0xa4>
{
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e19a: 69fb ldr r3, [r7, #28]
800e19c: f1c3 0207 rsb r2, r3, #7
800e1a0: 69bb ldr r3, [r7, #24]
800e1a2: 619a str r2, [r3, #24]
then the task that holds the mutex could be in either the
Ready, Blocked or Suspended states. Only remove the task
from its current state list if it is in the Ready state as
the task's priority is going to change and there is one
Ready list per priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
800e1a4: 69bb ldr r3, [r7, #24]
800e1a6: 6959 ldr r1, [r3, #20]
800e1a8: 693a ldr r2, [r7, #16]
800e1aa: 4613 mov r3, r2
800e1ac: 009b lsls r3, r3, #2
800e1ae: 4413 add r3, r2
800e1b0: 009b lsls r3, r3, #2
800e1b2: 4a1f ldr r2, [pc, #124] ; (800e230 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e1b4: 4413 add r3, r2
800e1b6: 4299 cmp r1, r3
800e1b8: d134 bne.n 800e224 <vTaskPriorityDisinheritAfterTimeout+0x124>
{
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e1ba: 69bb ldr r3, [r7, #24]
800e1bc: 3304 adds r3, #4
800e1be: 4618 mov r0, r3
800e1c0: f7fd ff44 bl 800c04c <uxListRemove>
800e1c4: 4603 mov r3, r0
800e1c6: 2b00 cmp r3, #0
800e1c8: d115 bne.n 800e1f6 <vTaskPriorityDisinheritAfterTimeout+0xf6>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800e1ca: 69bb ldr r3, [r7, #24]
800e1cc: 6ada ldr r2, [r3, #44] ; 0x2c
800e1ce: 4918 ldr r1, [pc, #96] ; (800e230 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e1d0: 4613 mov r3, r2
800e1d2: 009b lsls r3, r3, #2
800e1d4: 4413 add r3, r2
800e1d6: 009b lsls r3, r3, #2
800e1d8: 440b add r3, r1
800e1da: 681b ldr r3, [r3, #0]
800e1dc: 2b00 cmp r3, #0
800e1de: d10a bne.n 800e1f6 <vTaskPriorityDisinheritAfterTimeout+0xf6>
800e1e0: 69bb ldr r3, [r7, #24]
800e1e2: 6adb ldr r3, [r3, #44] ; 0x2c
800e1e4: 2201 movs r2, #1
800e1e6: fa02 f303 lsl.w r3, r2, r3
800e1ea: 43da mvns r2, r3
800e1ec: 4b11 ldr r3, [pc, #68] ; (800e234 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e1ee: 681b ldr r3, [r3, #0]
800e1f0: 4013 ands r3, r2
800e1f2: 4a10 ldr r2, [pc, #64] ; (800e234 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e1f4: 6013 str r3, [r2, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
prvAddTaskToReadyList( pxTCB );
800e1f6: 69bb ldr r3, [r7, #24]
800e1f8: 6adb ldr r3, [r3, #44] ; 0x2c
800e1fa: 2201 movs r2, #1
800e1fc: 409a lsls r2, r3
800e1fe: 4b0d ldr r3, [pc, #52] ; (800e234 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e200: 681b ldr r3, [r3, #0]
800e202: 4313 orrs r3, r2
800e204: 4a0b ldr r2, [pc, #44] ; (800e234 <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e206: 6013 str r3, [r2, #0]
800e208: 69bb ldr r3, [r7, #24]
800e20a: 6ada ldr r2, [r3, #44] ; 0x2c
800e20c: 4613 mov r3, r2
800e20e: 009b lsls r3, r3, #2
800e210: 4413 add r3, r2
800e212: 009b lsls r3, r3, #2
800e214: 4a06 ldr r2, [pc, #24] ; (800e230 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e216: 441a add r2, r3
800e218: 69bb ldr r3, [r7, #24]
800e21a: 3304 adds r3, #4
800e21c: 4619 mov r1, r3
800e21e: 4610 mov r0, r2
800e220: f7fd feb7 bl 800bf92 <vListInsertEnd>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800e224: bf00 nop
800e226: 3720 adds r7, #32
800e228: 46bd mov sp, r7
800e22a: bd80 pop {r7, pc}
800e22c: 2000058c .word 0x2000058c
800e230: 20000590 .word 0x20000590
800e234: 20000694 .word 0x20000694
0800e238 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
800e238: b480 push {r7}
800e23a: af00 add r7, sp, #0
/* If xSemaphoreCreateMutex() is called before any tasks have been created
then pxCurrentTCB will be NULL. */
if( pxCurrentTCB != NULL )
800e23c: 4b07 ldr r3, [pc, #28] ; (800e25c <pvTaskIncrementMutexHeldCount+0x24>)
800e23e: 681b ldr r3, [r3, #0]
800e240: 2b00 cmp r3, #0
800e242: d004 beq.n 800e24e <pvTaskIncrementMutexHeldCount+0x16>
{
( pxCurrentTCB->uxMutexesHeld )++;
800e244: 4b05 ldr r3, [pc, #20] ; (800e25c <pvTaskIncrementMutexHeldCount+0x24>)
800e246: 681b ldr r3, [r3, #0]
800e248: 6c9a ldr r2, [r3, #72] ; 0x48
800e24a: 3201 adds r2, #1
800e24c: 649a str r2, [r3, #72] ; 0x48
}
return pxCurrentTCB;
800e24e: 4b03 ldr r3, [pc, #12] ; (800e25c <pvTaskIncrementMutexHeldCount+0x24>)
800e250: 681b ldr r3, [r3, #0]
}
800e252: 4618 mov r0, r3
800e254: 46bd mov sp, r7
800e256: f85d 7b04 ldr.w r7, [sp], #4
800e25a: 4770 bx lr
800e25c: 2000058c .word 0x2000058c
0800e260 <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
800e260: b580 push {r7, lr}
800e262: b084 sub sp, #16
800e264: af00 add r7, sp, #0
800e266: 6078 str r0, [r7, #4]
800e268: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
800e26a: 4b29 ldr r3, [pc, #164] ; (800e310 <prvAddCurrentTaskToDelayedList+0xb0>)
800e26c: 681b ldr r3, [r3, #0]
800e26e: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e270: 4b28 ldr r3, [pc, #160] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e272: 681b ldr r3, [r3, #0]
800e274: 3304 adds r3, #4
800e276: 4618 mov r0, r3
800e278: f7fd fee8 bl 800c04c <uxListRemove>
800e27c: 4603 mov r3, r0
800e27e: 2b00 cmp r3, #0
800e280: d10b bne.n 800e29a <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
800e282: 4b24 ldr r3, [pc, #144] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e284: 681b ldr r3, [r3, #0]
800e286: 6adb ldr r3, [r3, #44] ; 0x2c
800e288: 2201 movs r2, #1
800e28a: fa02 f303 lsl.w r3, r2, r3
800e28e: 43da mvns r2, r3
800e290: 4b21 ldr r3, [pc, #132] ; (800e318 <prvAddCurrentTaskToDelayedList+0xb8>)
800e292: 681b ldr r3, [r3, #0]
800e294: 4013 ands r3, r2
800e296: 4a20 ldr r2, [pc, #128] ; (800e318 <prvAddCurrentTaskToDelayedList+0xb8>)
800e298: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
800e29a: 687b ldr r3, [r7, #4]
800e29c: f1b3 3fff cmp.w r3, #4294967295
800e2a0: d10a bne.n 800e2b8 <prvAddCurrentTaskToDelayedList+0x58>
800e2a2: 683b ldr r3, [r7, #0]
800e2a4: 2b00 cmp r3, #0
800e2a6: d007 beq.n 800e2b8 <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2a8: 4b1a ldr r3, [pc, #104] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e2aa: 681b ldr r3, [r3, #0]
800e2ac: 3304 adds r3, #4
800e2ae: 4619 mov r1, r3
800e2b0: 481a ldr r0, [pc, #104] ; (800e31c <prvAddCurrentTaskToDelayedList+0xbc>)
800e2b2: f7fd fe6e bl 800bf92 <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
800e2b6: e026 b.n 800e306 <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
800e2b8: 68fa ldr r2, [r7, #12]
800e2ba: 687b ldr r3, [r7, #4]
800e2bc: 4413 add r3, r2
800e2be: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
800e2c0: 4b14 ldr r3, [pc, #80] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e2c2: 681b ldr r3, [r3, #0]
800e2c4: 68ba ldr r2, [r7, #8]
800e2c6: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
800e2c8: 68ba ldr r2, [r7, #8]
800e2ca: 68fb ldr r3, [r7, #12]
800e2cc: 429a cmp r2, r3
800e2ce: d209 bcs.n 800e2e4 <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2d0: 4b13 ldr r3, [pc, #76] ; (800e320 <prvAddCurrentTaskToDelayedList+0xc0>)
800e2d2: 681a ldr r2, [r3, #0]
800e2d4: 4b0f ldr r3, [pc, #60] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e2d6: 681b ldr r3, [r3, #0]
800e2d8: 3304 adds r3, #4
800e2da: 4619 mov r1, r3
800e2dc: 4610 mov r0, r2
800e2de: f7fd fe7c bl 800bfda <vListInsert>
}
800e2e2: e010 b.n 800e306 <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2e4: 4b0f ldr r3, [pc, #60] ; (800e324 <prvAddCurrentTaskToDelayedList+0xc4>)
800e2e6: 681a ldr r2, [r3, #0]
800e2e8: 4b0a ldr r3, [pc, #40] ; (800e314 <prvAddCurrentTaskToDelayedList+0xb4>)
800e2ea: 681b ldr r3, [r3, #0]
800e2ec: 3304 adds r3, #4
800e2ee: 4619 mov r1, r3
800e2f0: 4610 mov r0, r2
800e2f2: f7fd fe72 bl 800bfda <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
800e2f6: 4b0c ldr r3, [pc, #48] ; (800e328 <prvAddCurrentTaskToDelayedList+0xc8>)
800e2f8: 681b ldr r3, [r3, #0]
800e2fa: 68ba ldr r2, [r7, #8]
800e2fc: 429a cmp r2, r3
800e2fe: d202 bcs.n 800e306 <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
800e300: 4a09 ldr r2, [pc, #36] ; (800e328 <prvAddCurrentTaskToDelayedList+0xc8>)
800e302: 68bb ldr r3, [r7, #8]
800e304: 6013 str r3, [r2, #0]
}
800e306: bf00 nop
800e308: 3710 adds r7, #16
800e30a: 46bd mov sp, r7
800e30c: bd80 pop {r7, pc}
800e30e: bf00 nop
800e310: 20000690 .word 0x20000690
800e314: 2000058c .word 0x2000058c
800e318: 20000694 .word 0x20000694
800e31c: 20000678 .word 0x20000678
800e320: 20000648 .word 0x20000648
800e324: 20000644 .word 0x20000644
800e328: 200006ac .word 0x200006ac
0800e32c <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
800e32c: b480 push {r7}
800e32e: b085 sub sp, #20
800e330: af00 add r7, sp, #0
800e332: 60f8 str r0, [r7, #12]
800e334: 60b9 str r1, [r7, #8]
800e336: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
800e338: 68fb ldr r3, [r7, #12]
800e33a: 3b04 subs r3, #4
800e33c: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
800e33e: 68fb ldr r3, [r7, #12]
800e340: f04f 7280 mov.w r2, #16777216 ; 0x1000000
800e344: 601a str r2, [r3, #0]
pxTopOfStack--;
800e346: 68fb ldr r3, [r7, #12]
800e348: 3b04 subs r3, #4
800e34a: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
800e34c: 68bb ldr r3, [r7, #8]
800e34e: f023 0201 bic.w r2, r3, #1
800e352: 68fb ldr r3, [r7, #12]
800e354: 601a str r2, [r3, #0]
pxTopOfStack--;
800e356: 68fb ldr r3, [r7, #12]
800e358: 3b04 subs r3, #4
800e35a: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
800e35c: 4a0c ldr r2, [pc, #48] ; (800e390 <pxPortInitialiseStack+0x64>)
800e35e: 68fb ldr r3, [r7, #12]
800e360: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
800e362: 68fb ldr r3, [r7, #12]
800e364: 3b14 subs r3, #20
800e366: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
800e368: 687a ldr r2, [r7, #4]
800e36a: 68fb ldr r3, [r7, #12]
800e36c: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
800e36e: 68fb ldr r3, [r7, #12]
800e370: 3b04 subs r3, #4
800e372: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
800e374: 68fb ldr r3, [r7, #12]
800e376: f06f 0202 mvn.w r2, #2
800e37a: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
800e37c: 68fb ldr r3, [r7, #12]
800e37e: 3b20 subs r3, #32
800e380: 60fb str r3, [r7, #12]
return pxTopOfStack;
800e382: 68fb ldr r3, [r7, #12]
}
800e384: 4618 mov r0, r3
800e386: 3714 adds r7, #20
800e388: 46bd mov sp, r7
800e38a: f85d 7b04 ldr.w r7, [sp], #4
800e38e: 4770 bx lr
800e390: 0800e395 .word 0x0800e395
0800e394 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
800e394: b480 push {r7}
800e396: b085 sub sp, #20
800e398: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
800e39a: 2300 movs r3, #0
800e39c: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
800e39e: 4b13 ldr r3, [pc, #76] ; (800e3ec <prvTaskExitError+0x58>)
800e3a0: 681b ldr r3, [r3, #0]
800e3a2: f1b3 3fff cmp.w r3, #4294967295
800e3a6: d00b beq.n 800e3c0 <prvTaskExitError+0x2c>
800e3a8: f04f 0350 mov.w r3, #80 ; 0x50
800e3ac: b672 cpsid i
800e3ae: f383 8811 msr BASEPRI, r3
800e3b2: f3bf 8f6f isb sy
800e3b6: f3bf 8f4f dsb sy
800e3ba: b662 cpsie i
800e3bc: 60fb str r3, [r7, #12]
800e3be: e7fe b.n 800e3be <prvTaskExitError+0x2a>
800e3c0: f04f 0350 mov.w r3, #80 ; 0x50
800e3c4: b672 cpsid i
800e3c6: f383 8811 msr BASEPRI, r3
800e3ca: f3bf 8f6f isb sy
800e3ce: f3bf 8f4f dsb sy
800e3d2: b662 cpsie i
800e3d4: 60bb str r3, [r7, #8]
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
800e3d6: bf00 nop
800e3d8: 687b ldr r3, [r7, #4]
800e3da: 2b00 cmp r3, #0
800e3dc: d0fc beq.n 800e3d8 <prvTaskExitError+0x44>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
800e3de: bf00 nop
800e3e0: 3714 adds r7, #20
800e3e2: 46bd mov sp, r7
800e3e4: f85d 7b04 ldr.w r7, [sp], #4
800e3e8: 4770 bx lr
800e3ea: bf00 nop
800e3ec: 20000070 .word 0x20000070
0800e3f0 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
800e3f0: 4b07 ldr r3, [pc, #28] ; (800e410 <pxCurrentTCBConst2>)
800e3f2: 6819 ldr r1, [r3, #0]
800e3f4: 6808 ldr r0, [r1, #0]
800e3f6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e3fa: f380 8809 msr PSP, r0
800e3fe: f3bf 8f6f isb sy
800e402: f04f 0000 mov.w r0, #0
800e406: f380 8811 msr BASEPRI, r0
800e40a: 4770 bx lr
800e40c: f3af 8000 nop.w
0800e410 <pxCurrentTCBConst2>:
800e410: 2000058c .word 0x2000058c
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
800e414: bf00 nop
800e416: bf00 nop
0800e418 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
800e418: 4808 ldr r0, [pc, #32] ; (800e43c <prvPortStartFirstTask+0x24>)
800e41a: 6800 ldr r0, [r0, #0]
800e41c: 6800 ldr r0, [r0, #0]
800e41e: f380 8808 msr MSP, r0
800e422: f04f 0000 mov.w r0, #0
800e426: f380 8814 msr CONTROL, r0
800e42a: b662 cpsie i
800e42c: b661 cpsie f
800e42e: f3bf 8f4f dsb sy
800e432: f3bf 8f6f isb sy
800e436: df00 svc 0
800e438: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
800e43a: bf00 nop
800e43c: e000ed08 .word 0xe000ed08
0800e440 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
800e440: b580 push {r7, lr}
800e442: b084 sub sp, #16
800e444: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
800e446: 4b36 ldr r3, [pc, #216] ; (800e520 <xPortStartScheduler+0xe0>)
800e448: 60fb str r3, [r7, #12]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
800e44a: 68fb ldr r3, [r7, #12]
800e44c: 781b ldrb r3, [r3, #0]
800e44e: b2db uxtb r3, r3
800e450: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
800e452: 68fb ldr r3, [r7, #12]
800e454: 22ff movs r2, #255 ; 0xff
800e456: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
800e458: 68fb ldr r3, [r7, #12]
800e45a: 781b ldrb r3, [r3, #0]
800e45c: b2db uxtb r3, r3
800e45e: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
800e460: 78fb ldrb r3, [r7, #3]
800e462: b2db uxtb r3, r3
800e464: f003 0350 and.w r3, r3, #80 ; 0x50
800e468: b2da uxtb r2, r3
800e46a: 4b2e ldr r3, [pc, #184] ; (800e524 <xPortStartScheduler+0xe4>)
800e46c: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
800e46e: 4b2e ldr r3, [pc, #184] ; (800e528 <xPortStartScheduler+0xe8>)
800e470: 2207 movs r2, #7
800e472: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e474: e009 b.n 800e48a <xPortStartScheduler+0x4a>
{
ulMaxPRIGROUPValue--;
800e476: 4b2c ldr r3, [pc, #176] ; (800e528 <xPortStartScheduler+0xe8>)
800e478: 681b ldr r3, [r3, #0]
800e47a: 3b01 subs r3, #1
800e47c: 4a2a ldr r2, [pc, #168] ; (800e528 <xPortStartScheduler+0xe8>)
800e47e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
800e480: 78fb ldrb r3, [r7, #3]
800e482: b2db uxtb r3, r3
800e484: 005b lsls r3, r3, #1
800e486: b2db uxtb r3, r3
800e488: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e48a: 78fb ldrb r3, [r7, #3]
800e48c: b2db uxtb r3, r3
800e48e: f003 0380 and.w r3, r3, #128 ; 0x80
800e492: 2b80 cmp r3, #128 ; 0x80
800e494: d0ef beq.n 800e476 <xPortStartScheduler+0x36>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
800e496: 4b24 ldr r3, [pc, #144] ; (800e528 <xPortStartScheduler+0xe8>)
800e498: 681b ldr r3, [r3, #0]
800e49a: f1c3 0307 rsb r3, r3, #7
800e49e: 2b04 cmp r3, #4
800e4a0: d00b beq.n 800e4ba <xPortStartScheduler+0x7a>
800e4a2: f04f 0350 mov.w r3, #80 ; 0x50
800e4a6: b672 cpsid i
800e4a8: f383 8811 msr BASEPRI, r3
800e4ac: f3bf 8f6f isb sy
800e4b0: f3bf 8f4f dsb sy
800e4b4: b662 cpsie i
800e4b6: 60bb str r3, [r7, #8]
800e4b8: e7fe b.n 800e4b8 <xPortStartScheduler+0x78>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
800e4ba: 4b1b ldr r3, [pc, #108] ; (800e528 <xPortStartScheduler+0xe8>)
800e4bc: 681b ldr r3, [r3, #0]
800e4be: 021b lsls r3, r3, #8
800e4c0: 4a19 ldr r2, [pc, #100] ; (800e528 <xPortStartScheduler+0xe8>)
800e4c2: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
800e4c4: 4b18 ldr r3, [pc, #96] ; (800e528 <xPortStartScheduler+0xe8>)
800e4c6: 681b ldr r3, [r3, #0]
800e4c8: f403 63e0 and.w r3, r3, #1792 ; 0x700
800e4cc: 4a16 ldr r2, [pc, #88] ; (800e528 <xPortStartScheduler+0xe8>)
800e4ce: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
800e4d0: 687b ldr r3, [r7, #4]
800e4d2: b2da uxtb r2, r3
800e4d4: 68fb ldr r3, [r7, #12]
800e4d6: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
800e4d8: 4b14 ldr r3, [pc, #80] ; (800e52c <xPortStartScheduler+0xec>)
800e4da: 681b ldr r3, [r3, #0]
800e4dc: 4a13 ldr r2, [pc, #76] ; (800e52c <xPortStartScheduler+0xec>)
800e4de: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
800e4e2: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
800e4e4: 4b11 ldr r3, [pc, #68] ; (800e52c <xPortStartScheduler+0xec>)
800e4e6: 681b ldr r3, [r3, #0]
800e4e8: 4a10 ldr r2, [pc, #64] ; (800e52c <xPortStartScheduler+0xec>)
800e4ea: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
800e4ee: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
800e4f0: f000 f8d4 bl 800e69c <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
800e4f4: 4b0e ldr r3, [pc, #56] ; (800e530 <xPortStartScheduler+0xf0>)
800e4f6: 2200 movs r2, #0
800e4f8: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
800e4fa: f000 f8f3 bl 800e6e4 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
800e4fe: 4b0d ldr r3, [pc, #52] ; (800e534 <xPortStartScheduler+0xf4>)
800e500: 681b ldr r3, [r3, #0]
800e502: 4a0c ldr r2, [pc, #48] ; (800e534 <xPortStartScheduler+0xf4>)
800e504: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
800e508: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
800e50a: f7ff ff85 bl 800e418 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
800e50e: f7ff fa69 bl 800d9e4 <vTaskSwitchContext>
prvTaskExitError();
800e512: f7ff ff3f bl 800e394 <prvTaskExitError>
/* Should not get here! */
return 0;
800e516: 2300 movs r3, #0
}
800e518: 4618 mov r0, r3
800e51a: 3710 adds r7, #16
800e51c: 46bd mov sp, r7
800e51e: bd80 pop {r7, pc}
800e520: e000e400 .word 0xe000e400
800e524: 200006b8 .word 0x200006b8
800e528: 200006bc .word 0x200006bc
800e52c: e000ed20 .word 0xe000ed20
800e530: 20000070 .word 0x20000070
800e534: e000ef34 .word 0xe000ef34
0800e538 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
800e538: b480 push {r7}
800e53a: b083 sub sp, #12
800e53c: af00 add r7, sp, #0
800e53e: f04f 0350 mov.w r3, #80 ; 0x50
800e542: b672 cpsid i
800e544: f383 8811 msr BASEPRI, r3
800e548: f3bf 8f6f isb sy
800e54c: f3bf 8f4f dsb sy
800e550: b662 cpsie i
800e552: 607b str r3, [r7, #4]
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
800e554: 4b0f ldr r3, [pc, #60] ; (800e594 <vPortEnterCritical+0x5c>)
800e556: 681b ldr r3, [r3, #0]
800e558: 3301 adds r3, #1
800e55a: 4a0e ldr r2, [pc, #56] ; (800e594 <vPortEnterCritical+0x5c>)
800e55c: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
800e55e: 4b0d ldr r3, [pc, #52] ; (800e594 <vPortEnterCritical+0x5c>)
800e560: 681b ldr r3, [r3, #0]
800e562: 2b01 cmp r3, #1
800e564: d110 bne.n 800e588 <vPortEnterCritical+0x50>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
800e566: 4b0c ldr r3, [pc, #48] ; (800e598 <vPortEnterCritical+0x60>)
800e568: 681b ldr r3, [r3, #0]
800e56a: b2db uxtb r3, r3
800e56c: 2b00 cmp r3, #0
800e56e: d00b beq.n 800e588 <vPortEnterCritical+0x50>
800e570: f04f 0350 mov.w r3, #80 ; 0x50
800e574: b672 cpsid i
800e576: f383 8811 msr BASEPRI, r3
800e57a: f3bf 8f6f isb sy
800e57e: f3bf 8f4f dsb sy
800e582: b662 cpsie i
800e584: 603b str r3, [r7, #0]
800e586: e7fe b.n 800e586 <vPortEnterCritical+0x4e>
}
}
800e588: bf00 nop
800e58a: 370c adds r7, #12
800e58c: 46bd mov sp, r7
800e58e: f85d 7b04 ldr.w r7, [sp], #4
800e592: 4770 bx lr
800e594: 20000070 .word 0x20000070
800e598: e000ed04 .word 0xe000ed04
0800e59c <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
800e59c: b480 push {r7}
800e59e: b083 sub sp, #12
800e5a0: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800e5a2: 4b12 ldr r3, [pc, #72] ; (800e5ec <vPortExitCritical+0x50>)
800e5a4: 681b ldr r3, [r3, #0]
800e5a6: 2b00 cmp r3, #0
800e5a8: d10b bne.n 800e5c2 <vPortExitCritical+0x26>
800e5aa: f04f 0350 mov.w r3, #80 ; 0x50
800e5ae: b672 cpsid i
800e5b0: f383 8811 msr BASEPRI, r3
800e5b4: f3bf 8f6f isb sy
800e5b8: f3bf 8f4f dsb sy
800e5bc: b662 cpsie i
800e5be: 607b str r3, [r7, #4]
800e5c0: e7fe b.n 800e5c0 <vPortExitCritical+0x24>
uxCriticalNesting--;
800e5c2: 4b0a ldr r3, [pc, #40] ; (800e5ec <vPortExitCritical+0x50>)
800e5c4: 681b ldr r3, [r3, #0]
800e5c6: 3b01 subs r3, #1
800e5c8: 4a08 ldr r2, [pc, #32] ; (800e5ec <vPortExitCritical+0x50>)
800e5ca: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
800e5cc: 4b07 ldr r3, [pc, #28] ; (800e5ec <vPortExitCritical+0x50>)
800e5ce: 681b ldr r3, [r3, #0]
800e5d0: 2b00 cmp r3, #0
800e5d2: d104 bne.n 800e5de <vPortExitCritical+0x42>
800e5d4: 2300 movs r3, #0
800e5d6: 603b str r3, [r7, #0]
__asm volatile
800e5d8: 683b ldr r3, [r7, #0]
800e5da: f383 8811 msr BASEPRI, r3
{
portENABLE_INTERRUPTS();
}
}
800e5de: bf00 nop
800e5e0: 370c adds r7, #12
800e5e2: 46bd mov sp, r7
800e5e4: f85d 7b04 ldr.w r7, [sp], #4
800e5e8: 4770 bx lr
800e5ea: bf00 nop
800e5ec: 20000070 .word 0x20000070
0800e5f0 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
800e5f0: f3ef 8009 mrs r0, PSP
800e5f4: f3bf 8f6f isb sy
800e5f8: 4b15 ldr r3, [pc, #84] ; (800e650 <pxCurrentTCBConst>)
800e5fa: 681a ldr r2, [r3, #0]
800e5fc: f01e 0f10 tst.w lr, #16
800e600: bf08 it eq
800e602: ed20 8a10 vstmdbeq r0!, {s16-s31}
800e606: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e60a: 6010 str r0, [r2, #0]
800e60c: e92d 0009 stmdb sp!, {r0, r3}
800e610: f04f 0050 mov.w r0, #80 ; 0x50
800e614: b672 cpsid i
800e616: f380 8811 msr BASEPRI, r0
800e61a: f3bf 8f4f dsb sy
800e61e: f3bf 8f6f isb sy
800e622: b662 cpsie i
800e624: f7ff f9de bl 800d9e4 <vTaskSwitchContext>
800e628: f04f 0000 mov.w r0, #0
800e62c: f380 8811 msr BASEPRI, r0
800e630: bc09 pop {r0, r3}
800e632: 6819 ldr r1, [r3, #0]
800e634: 6808 ldr r0, [r1, #0]
800e636: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e63a: f01e 0f10 tst.w lr, #16
800e63e: bf08 it eq
800e640: ecb0 8a10 vldmiaeq r0!, {s16-s31}
800e644: f380 8809 msr PSP, r0
800e648: f3bf 8f6f isb sy
800e64c: 4770 bx lr
800e64e: bf00 nop
0800e650 <pxCurrentTCBConst>:
800e650: 2000058c .word 0x2000058c
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
800e654: bf00 nop
800e656: bf00 nop
0800e658 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
800e658: b580 push {r7, lr}
800e65a: b082 sub sp, #8
800e65c: af00 add r7, sp, #0
__asm volatile
800e65e: f04f 0350 mov.w r3, #80 ; 0x50
800e662: b672 cpsid i
800e664: f383 8811 msr BASEPRI, r3
800e668: f3bf 8f6f isb sy
800e66c: f3bf 8f4f dsb sy
800e670: b662 cpsie i
800e672: 607b str r3, [r7, #4]
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
800e674: f7ff f8fc bl 800d870 <xTaskIncrementTick>
800e678: 4603 mov r3, r0
800e67a: 2b00 cmp r3, #0
800e67c: d003 beq.n 800e686 <SysTick_Handler+0x2e>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
800e67e: 4b06 ldr r3, [pc, #24] ; (800e698 <SysTick_Handler+0x40>)
800e680: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800e684: 601a str r2, [r3, #0]
800e686: 2300 movs r3, #0
800e688: 603b str r3, [r7, #0]
__asm volatile
800e68a: 683b ldr r3, [r7, #0]
800e68c: f383 8811 msr BASEPRI, r3
}
}
portENABLE_INTERRUPTS();
}
800e690: bf00 nop
800e692: 3708 adds r7, #8
800e694: 46bd mov sp, r7
800e696: bd80 pop {r7, pc}
800e698: e000ed04 .word 0xe000ed04
0800e69c <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
800e69c: b480 push {r7}
800e69e: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
800e6a0: 4b0b ldr r3, [pc, #44] ; (800e6d0 <vPortSetupTimerInterrupt+0x34>)
800e6a2: 2200 movs r2, #0
800e6a4: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
800e6a6: 4b0b ldr r3, [pc, #44] ; (800e6d4 <vPortSetupTimerInterrupt+0x38>)
800e6a8: 2200 movs r2, #0
800e6aa: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
800e6ac: 4b0a ldr r3, [pc, #40] ; (800e6d8 <vPortSetupTimerInterrupt+0x3c>)
800e6ae: 681b ldr r3, [r3, #0]
800e6b0: 4a0a ldr r2, [pc, #40] ; (800e6dc <vPortSetupTimerInterrupt+0x40>)
800e6b2: fba2 2303 umull r2, r3, r2, r3
800e6b6: 099b lsrs r3, r3, #6
800e6b8: 4a09 ldr r2, [pc, #36] ; (800e6e0 <vPortSetupTimerInterrupt+0x44>)
800e6ba: 3b01 subs r3, #1
800e6bc: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
800e6be: 4b04 ldr r3, [pc, #16] ; (800e6d0 <vPortSetupTimerInterrupt+0x34>)
800e6c0: 2207 movs r2, #7
800e6c2: 601a str r2, [r3, #0]
}
800e6c4: bf00 nop
800e6c6: 46bd mov sp, r7
800e6c8: f85d 7b04 ldr.w r7, [sp], #4
800e6cc: 4770 bx lr
800e6ce: bf00 nop
800e6d0: e000e010 .word 0xe000e010
800e6d4: e000e018 .word 0xe000e018
800e6d8: 20000064 .word 0x20000064
800e6dc: 10624dd3 .word 0x10624dd3
800e6e0: e000e014 .word 0xe000e014
0800e6e4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
800e6e4: f8df 000c ldr.w r0, [pc, #12] ; 800e6f4 <vPortEnableVFP+0x10>
800e6e8: 6801 ldr r1, [r0, #0]
800e6ea: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
800e6ee: 6001 str r1, [r0, #0]
800e6f0: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
800e6f2: bf00 nop
800e6f4: e000ed88 .word 0xe000ed88
0800e6f8 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
800e6f8: b480 push {r7}
800e6fa: b085 sub sp, #20
800e6fc: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
800e6fe: f3ef 8305 mrs r3, IPSR
800e702: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
800e704: 68fb ldr r3, [r7, #12]
800e706: 2b0f cmp r3, #15
800e708: d915 bls.n 800e736 <vPortValidateInterruptPriority+0x3e>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
800e70a: 4a18 ldr r2, [pc, #96] ; (800e76c <vPortValidateInterruptPriority+0x74>)
800e70c: 68fb ldr r3, [r7, #12]
800e70e: 4413 add r3, r2
800e710: 781b ldrb r3, [r3, #0]
800e712: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
800e714: 4b16 ldr r3, [pc, #88] ; (800e770 <vPortValidateInterruptPriority+0x78>)
800e716: 781b ldrb r3, [r3, #0]
800e718: 7afa ldrb r2, [r7, #11]
800e71a: 429a cmp r2, r3
800e71c: d20b bcs.n 800e736 <vPortValidateInterruptPriority+0x3e>
__asm volatile
800e71e: f04f 0350 mov.w r3, #80 ; 0x50
800e722: b672 cpsid i
800e724: f383 8811 msr BASEPRI, r3
800e728: f3bf 8f6f isb sy
800e72c: f3bf 8f4f dsb sy
800e730: b662 cpsie i
800e732: 607b str r3, [r7, #4]
800e734: e7fe b.n 800e734 <vPortValidateInterruptPriority+0x3c>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
800e736: 4b0f ldr r3, [pc, #60] ; (800e774 <vPortValidateInterruptPriority+0x7c>)
800e738: 681b ldr r3, [r3, #0]
800e73a: f403 62e0 and.w r2, r3, #1792 ; 0x700
800e73e: 4b0e ldr r3, [pc, #56] ; (800e778 <vPortValidateInterruptPriority+0x80>)
800e740: 681b ldr r3, [r3, #0]
800e742: 429a cmp r2, r3
800e744: d90b bls.n 800e75e <vPortValidateInterruptPriority+0x66>
800e746: f04f 0350 mov.w r3, #80 ; 0x50
800e74a: b672 cpsid i
800e74c: f383 8811 msr BASEPRI, r3
800e750: f3bf 8f6f isb sy
800e754: f3bf 8f4f dsb sy
800e758: b662 cpsie i
800e75a: 603b str r3, [r7, #0]
800e75c: e7fe b.n 800e75c <vPortValidateInterruptPriority+0x64>
}
800e75e: bf00 nop
800e760: 3714 adds r7, #20
800e762: 46bd mov sp, r7
800e764: f85d 7b04 ldr.w r7, [sp], #4
800e768: 4770 bx lr
800e76a: bf00 nop
800e76c: e000e3f0 .word 0xe000e3f0
800e770: 200006b8 .word 0x200006b8
800e774: e000ed0c .word 0xe000ed0c
800e778: 200006bc .word 0x200006bc
0800e77c <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
800e77c: b580 push {r7, lr}
800e77e: b08a sub sp, #40 ; 0x28
800e780: af00 add r7, sp, #0
800e782: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
800e784: 2300 movs r3, #0
800e786: 61fb str r3, [r7, #28]
vTaskSuspendAll();
800e788: f7fe ffa4 bl 800d6d4 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
800e78c: 4b5c ldr r3, [pc, #368] ; (800e900 <pvPortMalloc+0x184>)
800e78e: 681b ldr r3, [r3, #0]
800e790: 2b00 cmp r3, #0
800e792: d101 bne.n 800e798 <pvPortMalloc+0x1c>
{
prvHeapInit();
800e794: f000 f91a bl 800e9cc <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
800e798: 4b5a ldr r3, [pc, #360] ; (800e904 <pvPortMalloc+0x188>)
800e79a: 681a ldr r2, [r3, #0]
800e79c: 687b ldr r3, [r7, #4]
800e79e: 4013 ands r3, r2
800e7a0: 2b00 cmp r3, #0
800e7a2: f040 8090 bne.w 800e8c6 <pvPortMalloc+0x14a>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
800e7a6: 687b ldr r3, [r7, #4]
800e7a8: 2b00 cmp r3, #0
800e7aa: d01e beq.n 800e7ea <pvPortMalloc+0x6e>
{
xWantedSize += xHeapStructSize;
800e7ac: 2208 movs r2, #8
800e7ae: 687b ldr r3, [r7, #4]
800e7b0: 4413 add r3, r2
800e7b2: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
800e7b4: 687b ldr r3, [r7, #4]
800e7b6: f003 0307 and.w r3, r3, #7
800e7ba: 2b00 cmp r3, #0
800e7bc: d015 beq.n 800e7ea <pvPortMalloc+0x6e>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800e7be: 687b ldr r3, [r7, #4]
800e7c0: f023 0307 bic.w r3, r3, #7
800e7c4: 3308 adds r3, #8
800e7c6: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
800e7c8: 687b ldr r3, [r7, #4]
800e7ca: f003 0307 and.w r3, r3, #7
800e7ce: 2b00 cmp r3, #0
800e7d0: d00b beq.n 800e7ea <pvPortMalloc+0x6e>
800e7d2: f04f 0350 mov.w r3, #80 ; 0x50
800e7d6: b672 cpsid i
800e7d8: f383 8811 msr BASEPRI, r3
800e7dc: f3bf 8f6f isb sy
800e7e0: f3bf 8f4f dsb sy
800e7e4: b662 cpsie i
800e7e6: 617b str r3, [r7, #20]
800e7e8: e7fe b.n 800e7e8 <pvPortMalloc+0x6c>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800e7ea: 687b ldr r3, [r7, #4]
800e7ec: 2b00 cmp r3, #0
800e7ee: d06a beq.n 800e8c6 <pvPortMalloc+0x14a>
800e7f0: 4b45 ldr r3, [pc, #276] ; (800e908 <pvPortMalloc+0x18c>)
800e7f2: 681b ldr r3, [r3, #0]
800e7f4: 687a ldr r2, [r7, #4]
800e7f6: 429a cmp r2, r3
800e7f8: d865 bhi.n 800e8c6 <pvPortMalloc+0x14a>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800e7fa: 4b44 ldr r3, [pc, #272] ; (800e90c <pvPortMalloc+0x190>)
800e7fc: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
800e7fe: 4b43 ldr r3, [pc, #268] ; (800e90c <pvPortMalloc+0x190>)
800e800: 681b ldr r3, [r3, #0]
800e802: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e804: e004 b.n 800e810 <pvPortMalloc+0x94>
{
pxPreviousBlock = pxBlock;
800e806: 6a7b ldr r3, [r7, #36] ; 0x24
800e808: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
800e80a: 6a7b ldr r3, [r7, #36] ; 0x24
800e80c: 681b ldr r3, [r3, #0]
800e80e: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e810: 6a7b ldr r3, [r7, #36] ; 0x24
800e812: 685b ldr r3, [r3, #4]
800e814: 687a ldr r2, [r7, #4]
800e816: 429a cmp r2, r3
800e818: d903 bls.n 800e822 <pvPortMalloc+0xa6>
800e81a: 6a7b ldr r3, [r7, #36] ; 0x24
800e81c: 681b ldr r3, [r3, #0]
800e81e: 2b00 cmp r3, #0
800e820: d1f1 bne.n 800e806 <pvPortMalloc+0x8a>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800e822: 4b37 ldr r3, [pc, #220] ; (800e900 <pvPortMalloc+0x184>)
800e824: 681b ldr r3, [r3, #0]
800e826: 6a7a ldr r2, [r7, #36] ; 0x24
800e828: 429a cmp r2, r3
800e82a: d04c beq.n 800e8c6 <pvPortMalloc+0x14a>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
800e82c: 6a3b ldr r3, [r7, #32]
800e82e: 681b ldr r3, [r3, #0]
800e830: 2208 movs r2, #8
800e832: 4413 add r3, r2
800e834: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
800e836: 6a7b ldr r3, [r7, #36] ; 0x24
800e838: 681a ldr r2, [r3, #0]
800e83a: 6a3b ldr r3, [r7, #32]
800e83c: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
800e83e: 6a7b ldr r3, [r7, #36] ; 0x24
800e840: 685a ldr r2, [r3, #4]
800e842: 687b ldr r3, [r7, #4]
800e844: 1ad2 subs r2, r2, r3
800e846: 2308 movs r3, #8
800e848: 005b lsls r3, r3, #1
800e84a: 429a cmp r2, r3
800e84c: d920 bls.n 800e890 <pvPortMalloc+0x114>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
800e84e: 6a7a ldr r2, [r7, #36] ; 0x24
800e850: 687b ldr r3, [r7, #4]
800e852: 4413 add r3, r2
800e854: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
800e856: 69bb ldr r3, [r7, #24]
800e858: f003 0307 and.w r3, r3, #7
800e85c: 2b00 cmp r3, #0
800e85e: d00b beq.n 800e878 <pvPortMalloc+0xfc>
800e860: f04f 0350 mov.w r3, #80 ; 0x50
800e864: b672 cpsid i
800e866: f383 8811 msr BASEPRI, r3
800e86a: f3bf 8f6f isb sy
800e86e: f3bf 8f4f dsb sy
800e872: b662 cpsie i
800e874: 613b str r3, [r7, #16]
800e876: e7fe b.n 800e876 <pvPortMalloc+0xfa>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
800e878: 6a7b ldr r3, [r7, #36] ; 0x24
800e87a: 685a ldr r2, [r3, #4]
800e87c: 687b ldr r3, [r7, #4]
800e87e: 1ad2 subs r2, r2, r3
800e880: 69bb ldr r3, [r7, #24]
800e882: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800e884: 6a7b ldr r3, [r7, #36] ; 0x24
800e886: 687a ldr r2, [r7, #4]
800e888: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
800e88a: 69b8 ldr r0, [r7, #24]
800e88c: f000 f900 bl 800ea90 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
800e890: 4b1d ldr r3, [pc, #116] ; (800e908 <pvPortMalloc+0x18c>)
800e892: 681a ldr r2, [r3, #0]
800e894: 6a7b ldr r3, [r7, #36] ; 0x24
800e896: 685b ldr r3, [r3, #4]
800e898: 1ad3 subs r3, r2, r3
800e89a: 4a1b ldr r2, [pc, #108] ; (800e908 <pvPortMalloc+0x18c>)
800e89c: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
800e89e: 4b1a ldr r3, [pc, #104] ; (800e908 <pvPortMalloc+0x18c>)
800e8a0: 681a ldr r2, [r3, #0]
800e8a2: 4b1b ldr r3, [pc, #108] ; (800e910 <pvPortMalloc+0x194>)
800e8a4: 681b ldr r3, [r3, #0]
800e8a6: 429a cmp r2, r3
800e8a8: d203 bcs.n 800e8b2 <pvPortMalloc+0x136>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
800e8aa: 4b17 ldr r3, [pc, #92] ; (800e908 <pvPortMalloc+0x18c>)
800e8ac: 681b ldr r3, [r3, #0]
800e8ae: 4a18 ldr r2, [pc, #96] ; (800e910 <pvPortMalloc+0x194>)
800e8b0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800e8b2: 6a7b ldr r3, [r7, #36] ; 0x24
800e8b4: 685a ldr r2, [r3, #4]
800e8b6: 4b13 ldr r3, [pc, #76] ; (800e904 <pvPortMalloc+0x188>)
800e8b8: 681b ldr r3, [r3, #0]
800e8ba: 431a orrs r2, r3
800e8bc: 6a7b ldr r3, [r7, #36] ; 0x24
800e8be: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
800e8c0: 6a7b ldr r3, [r7, #36] ; 0x24
800e8c2: 2200 movs r2, #0
800e8c4: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800e8c6: f7fe ff13 bl 800d6f0 <xTaskResumeAll>
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
{
if( pvReturn == NULL )
800e8ca: 69fb ldr r3, [r7, #28]
800e8cc: 2b00 cmp r3, #0
800e8ce: d101 bne.n 800e8d4 <pvPortMalloc+0x158>
{
extern void vApplicationMallocFailedHook( void );
vApplicationMallocFailedHook();
800e8d0: f7f1 fe80 bl 80005d4 <vApplicationMallocFailedHook>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
800e8d4: 69fb ldr r3, [r7, #28]
800e8d6: f003 0307 and.w r3, r3, #7
800e8da: 2b00 cmp r3, #0
800e8dc: d00b beq.n 800e8f6 <pvPortMalloc+0x17a>
800e8de: f04f 0350 mov.w r3, #80 ; 0x50
800e8e2: b672 cpsid i
800e8e4: f383 8811 msr BASEPRI, r3
800e8e8: f3bf 8f6f isb sy
800e8ec: f3bf 8f4f dsb sy
800e8f0: b662 cpsie i
800e8f2: 60fb str r3, [r7, #12]
800e8f4: e7fe b.n 800e8f4 <pvPortMalloc+0x178>
return pvReturn;
800e8f6: 69fb ldr r3, [r7, #28]
}
800e8f8: 4618 mov r0, r3
800e8fa: 3728 adds r7, #40 ; 0x28
800e8fc: 46bd mov sp, r7
800e8fe: bd80 pop {r7, pc}
800e900: 200086c8 .word 0x200086c8
800e904: 200086d4 .word 0x200086d4
800e908: 200086cc .word 0x200086cc
800e90c: 200086c0 .word 0x200086c0
800e910: 200086d0 .word 0x200086d0
0800e914 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
800e914: b580 push {r7, lr}
800e916: b086 sub sp, #24
800e918: af00 add r7, sp, #0
800e91a: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
800e91c: 687b ldr r3, [r7, #4]
800e91e: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800e920: 687b ldr r3, [r7, #4]
800e922: 2b00 cmp r3, #0
800e924: d04a beq.n 800e9bc <vPortFree+0xa8>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
800e926: 2308 movs r3, #8
800e928: 425b negs r3, r3
800e92a: 697a ldr r2, [r7, #20]
800e92c: 4413 add r3, r2
800e92e: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800e930: 697b ldr r3, [r7, #20]
800e932: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
800e934: 693b ldr r3, [r7, #16]
800e936: 685a ldr r2, [r3, #4]
800e938: 4b22 ldr r3, [pc, #136] ; (800e9c4 <vPortFree+0xb0>)
800e93a: 681b ldr r3, [r3, #0]
800e93c: 4013 ands r3, r2
800e93e: 2b00 cmp r3, #0
800e940: d10b bne.n 800e95a <vPortFree+0x46>
800e942: f04f 0350 mov.w r3, #80 ; 0x50
800e946: b672 cpsid i
800e948: f383 8811 msr BASEPRI, r3
800e94c: f3bf 8f6f isb sy
800e950: f3bf 8f4f dsb sy
800e954: b662 cpsie i
800e956: 60fb str r3, [r7, #12]
800e958: e7fe b.n 800e958 <vPortFree+0x44>
configASSERT( pxLink->pxNextFreeBlock == NULL );
800e95a: 693b ldr r3, [r7, #16]
800e95c: 681b ldr r3, [r3, #0]
800e95e: 2b00 cmp r3, #0
800e960: d00b beq.n 800e97a <vPortFree+0x66>
800e962: f04f 0350 mov.w r3, #80 ; 0x50
800e966: b672 cpsid i
800e968: f383 8811 msr BASEPRI, r3
800e96c: f3bf 8f6f isb sy
800e970: f3bf 8f4f dsb sy
800e974: b662 cpsie i
800e976: 60bb str r3, [r7, #8]
800e978: e7fe b.n 800e978 <vPortFree+0x64>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
800e97a: 693b ldr r3, [r7, #16]
800e97c: 685a ldr r2, [r3, #4]
800e97e: 4b11 ldr r3, [pc, #68] ; (800e9c4 <vPortFree+0xb0>)
800e980: 681b ldr r3, [r3, #0]
800e982: 4013 ands r3, r2
800e984: 2b00 cmp r3, #0
800e986: d019 beq.n 800e9bc <vPortFree+0xa8>
{
if( pxLink->pxNextFreeBlock == NULL )
800e988: 693b ldr r3, [r7, #16]
800e98a: 681b ldr r3, [r3, #0]
800e98c: 2b00 cmp r3, #0
800e98e: d115 bne.n 800e9bc <vPortFree+0xa8>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
800e990: 693b ldr r3, [r7, #16]
800e992: 685a ldr r2, [r3, #4]
800e994: 4b0b ldr r3, [pc, #44] ; (800e9c4 <vPortFree+0xb0>)
800e996: 681b ldr r3, [r3, #0]
800e998: 43db mvns r3, r3
800e99a: 401a ands r2, r3
800e99c: 693b ldr r3, [r7, #16]
800e99e: 605a str r2, [r3, #4]
vTaskSuspendAll();
800e9a0: f7fe fe98 bl 800d6d4 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800e9a4: 693b ldr r3, [r7, #16]
800e9a6: 685a ldr r2, [r3, #4]
800e9a8: 4b07 ldr r3, [pc, #28] ; (800e9c8 <vPortFree+0xb4>)
800e9aa: 681b ldr r3, [r3, #0]
800e9ac: 4413 add r3, r2
800e9ae: 4a06 ldr r2, [pc, #24] ; (800e9c8 <vPortFree+0xb4>)
800e9b0: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800e9b2: 6938 ldr r0, [r7, #16]
800e9b4: f000 f86c bl 800ea90 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
800e9b8: f7fe fe9a bl 800d6f0 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800e9bc: bf00 nop
800e9be: 3718 adds r7, #24
800e9c0: 46bd mov sp, r7
800e9c2: bd80 pop {r7, pc}
800e9c4: 200086d4 .word 0x200086d4
800e9c8: 200086cc .word 0x200086cc
0800e9cc <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
800e9cc: b480 push {r7}
800e9ce: b085 sub sp, #20
800e9d0: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
800e9d2: f44f 4300 mov.w r3, #32768 ; 0x8000
800e9d6: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
800e9d8: 4b27 ldr r3, [pc, #156] ; (800ea78 <prvHeapInit+0xac>)
800e9da: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
800e9dc: 68fb ldr r3, [r7, #12]
800e9de: f003 0307 and.w r3, r3, #7
800e9e2: 2b00 cmp r3, #0
800e9e4: d00c beq.n 800ea00 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800e9e6: 68fb ldr r3, [r7, #12]
800e9e8: 3307 adds r3, #7
800e9ea: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800e9ec: 68fb ldr r3, [r7, #12]
800e9ee: f023 0307 bic.w r3, r3, #7
800e9f2: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800e9f4: 68ba ldr r2, [r7, #8]
800e9f6: 68fb ldr r3, [r7, #12]
800e9f8: 1ad3 subs r3, r2, r3
800e9fa: 4a1f ldr r2, [pc, #124] ; (800ea78 <prvHeapInit+0xac>)
800e9fc: 4413 add r3, r2
800e9fe: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
800ea00: 68fb ldr r3, [r7, #12]
800ea02: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
800ea04: 4a1d ldr r2, [pc, #116] ; (800ea7c <prvHeapInit+0xb0>)
800ea06: 687b ldr r3, [r7, #4]
800ea08: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
800ea0a: 4b1c ldr r3, [pc, #112] ; (800ea7c <prvHeapInit+0xb0>)
800ea0c: 2200 movs r2, #0
800ea0e: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
800ea10: 687b ldr r3, [r7, #4]
800ea12: 68ba ldr r2, [r7, #8]
800ea14: 4413 add r3, r2
800ea16: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
800ea18: 2208 movs r2, #8
800ea1a: 68fb ldr r3, [r7, #12]
800ea1c: 1a9b subs r3, r3, r2
800ea1e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800ea20: 68fb ldr r3, [r7, #12]
800ea22: f023 0307 bic.w r3, r3, #7
800ea26: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
800ea28: 68fb ldr r3, [r7, #12]
800ea2a: 4a15 ldr r2, [pc, #84] ; (800ea80 <prvHeapInit+0xb4>)
800ea2c: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
800ea2e: 4b14 ldr r3, [pc, #80] ; (800ea80 <prvHeapInit+0xb4>)
800ea30: 681b ldr r3, [r3, #0]
800ea32: 2200 movs r2, #0
800ea34: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800ea36: 4b12 ldr r3, [pc, #72] ; (800ea80 <prvHeapInit+0xb4>)
800ea38: 681b ldr r3, [r3, #0]
800ea3a: 2200 movs r2, #0
800ea3c: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
800ea3e: 687b ldr r3, [r7, #4]
800ea40: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800ea42: 683b ldr r3, [r7, #0]
800ea44: 68fa ldr r2, [r7, #12]
800ea46: 1ad2 subs r2, r2, r3
800ea48: 683b ldr r3, [r7, #0]
800ea4a: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
800ea4c: 4b0c ldr r3, [pc, #48] ; (800ea80 <prvHeapInit+0xb4>)
800ea4e: 681a ldr r2, [r3, #0]
800ea50: 683b ldr r3, [r7, #0]
800ea52: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea54: 683b ldr r3, [r7, #0]
800ea56: 685b ldr r3, [r3, #4]
800ea58: 4a0a ldr r2, [pc, #40] ; (800ea84 <prvHeapInit+0xb8>)
800ea5a: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea5c: 683b ldr r3, [r7, #0]
800ea5e: 685b ldr r3, [r3, #4]
800ea60: 4a09 ldr r2, [pc, #36] ; (800ea88 <prvHeapInit+0xbc>)
800ea62: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800ea64: 4b09 ldr r3, [pc, #36] ; (800ea8c <prvHeapInit+0xc0>)
800ea66: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
800ea6a: 601a str r2, [r3, #0]
}
800ea6c: bf00 nop
800ea6e: 3714 adds r7, #20
800ea70: 46bd mov sp, r7
800ea72: f85d 7b04 ldr.w r7, [sp], #4
800ea76: 4770 bx lr
800ea78: 200006c0 .word 0x200006c0
800ea7c: 200086c0 .word 0x200086c0
800ea80: 200086c8 .word 0x200086c8
800ea84: 200086d0 .word 0x200086d0
800ea88: 200086cc .word 0x200086cc
800ea8c: 200086d4 .word 0x200086d4
0800ea90 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
800ea90: b480 push {r7}
800ea92: b085 sub sp, #20
800ea94: af00 add r7, sp, #0
800ea96: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
800ea98: 4b28 ldr r3, [pc, #160] ; (800eb3c <prvInsertBlockIntoFreeList+0xac>)
800ea9a: 60fb str r3, [r7, #12]
800ea9c: e002 b.n 800eaa4 <prvInsertBlockIntoFreeList+0x14>
800ea9e: 68fb ldr r3, [r7, #12]
800eaa0: 681b ldr r3, [r3, #0]
800eaa2: 60fb str r3, [r7, #12]
800eaa4: 68fb ldr r3, [r7, #12]
800eaa6: 681b ldr r3, [r3, #0]
800eaa8: 687a ldr r2, [r7, #4]
800eaaa: 429a cmp r2, r3
800eaac: d8f7 bhi.n 800ea9e <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
800eaae: 68fb ldr r3, [r7, #12]
800eab0: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
800eab2: 68fb ldr r3, [r7, #12]
800eab4: 685b ldr r3, [r3, #4]
800eab6: 68ba ldr r2, [r7, #8]
800eab8: 4413 add r3, r2
800eaba: 687a ldr r2, [r7, #4]
800eabc: 429a cmp r2, r3
800eabe: d108 bne.n 800ead2 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
800eac0: 68fb ldr r3, [r7, #12]
800eac2: 685a ldr r2, [r3, #4]
800eac4: 687b ldr r3, [r7, #4]
800eac6: 685b ldr r3, [r3, #4]
800eac8: 441a add r2, r3
800eaca: 68fb ldr r3, [r7, #12]
800eacc: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
800eace: 68fb ldr r3, [r7, #12]
800ead0: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
800ead2: 687b ldr r3, [r7, #4]
800ead4: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800ead6: 687b ldr r3, [r7, #4]
800ead8: 685b ldr r3, [r3, #4]
800eada: 68ba ldr r2, [r7, #8]
800eadc: 441a add r2, r3
800eade: 68fb ldr r3, [r7, #12]
800eae0: 681b ldr r3, [r3, #0]
800eae2: 429a cmp r2, r3
800eae4: d118 bne.n 800eb18 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800eae6: 68fb ldr r3, [r7, #12]
800eae8: 681a ldr r2, [r3, #0]
800eaea: 4b15 ldr r3, [pc, #84] ; (800eb40 <prvInsertBlockIntoFreeList+0xb0>)
800eaec: 681b ldr r3, [r3, #0]
800eaee: 429a cmp r2, r3
800eaf0: d00d beq.n 800eb0e <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800eaf2: 687b ldr r3, [r7, #4]
800eaf4: 685a ldr r2, [r3, #4]
800eaf6: 68fb ldr r3, [r7, #12]
800eaf8: 681b ldr r3, [r3, #0]
800eafa: 685b ldr r3, [r3, #4]
800eafc: 441a add r2, r3
800eafe: 687b ldr r3, [r7, #4]
800eb00: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
800eb02: 68fb ldr r3, [r7, #12]
800eb04: 681b ldr r3, [r3, #0]
800eb06: 681a ldr r2, [r3, #0]
800eb08: 687b ldr r3, [r7, #4]
800eb0a: 601a str r2, [r3, #0]
800eb0c: e008 b.n 800eb20 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
800eb0e: 4b0c ldr r3, [pc, #48] ; (800eb40 <prvInsertBlockIntoFreeList+0xb0>)
800eb10: 681a ldr r2, [r3, #0]
800eb12: 687b ldr r3, [r7, #4]
800eb14: 601a str r2, [r3, #0]
800eb16: e003 b.n 800eb20 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
800eb18: 68fb ldr r3, [r7, #12]
800eb1a: 681a ldr r2, [r3, #0]
800eb1c: 687b ldr r3, [r7, #4]
800eb1e: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
800eb20: 68fa ldr r2, [r7, #12]
800eb22: 687b ldr r3, [r7, #4]
800eb24: 429a cmp r2, r3
800eb26: d002 beq.n 800eb2e <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
800eb28: 68fb ldr r3, [r7, #12]
800eb2a: 687a ldr r2, [r7, #4]
800eb2c: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800eb2e: bf00 nop
800eb30: 3714 adds r7, #20
800eb32: 46bd mov sp, r7
800eb34: f85d 7b04 ldr.w r7, [sp], #4
800eb38: 4770 bx lr
800eb3a: bf00 nop
800eb3c: 200086c0 .word 0x200086c0
800eb40: 200086c8 .word 0x200086c8
0800eb44 <tcpip_timeouts_mbox_fetch>:
* @param mbox the mbox to fetch the message from
* @param msg the place to store the message
*/
static void
tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
{
800eb44: b580 push {r7, lr}
800eb46: b084 sub sp, #16
800eb48: af00 add r7, sp, #0
800eb4a: 6078 str r0, [r7, #4]
800eb4c: 6039 str r1, [r7, #0]
u32_t sleeptime, res;
again:
LWIP_ASSERT_CORE_LOCKED();
sleeptime = sys_timeouts_sleeptime();
800eb4e: f007 fa91 bl 8016074 <sys_timeouts_sleeptime>
800eb52: 60f8 str r0, [r7, #12]
if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
800eb54: 68fb ldr r3, [r7, #12]
800eb56: f1b3 3fff cmp.w r3, #4294967295
800eb5a: d10b bne.n 800eb74 <tcpip_timeouts_mbox_fetch+0x30>
UNLOCK_TCPIP_CORE();
800eb5c: 4813 ldr r0, [pc, #76] ; (800ebac <tcpip_timeouts_mbox_fetch+0x68>)
800eb5e: f00c f9c2 bl 801aee6 <sys_mutex_unlock>
sys_arch_mbox_fetch(mbox, msg, 0);
800eb62: 2200 movs r2, #0
800eb64: 6839 ldr r1, [r7, #0]
800eb66: 6878 ldr r0, [r7, #4]
800eb68: f00c f934 bl 801add4 <sys_arch_mbox_fetch>
LOCK_TCPIP_CORE();
800eb6c: 480f ldr r0, [pc, #60] ; (800ebac <tcpip_timeouts_mbox_fetch+0x68>)
800eb6e: f00c f9ab bl 801aec8 <sys_mutex_lock>
return;
800eb72: e018 b.n 800eba6 <tcpip_timeouts_mbox_fetch+0x62>
} else if (sleeptime == 0) {
800eb74: 68fb ldr r3, [r7, #12]
800eb76: 2b00 cmp r3, #0
800eb78: d102 bne.n 800eb80 <tcpip_timeouts_mbox_fetch+0x3c>
sys_check_timeouts();
800eb7a: f007 fa41 bl 8016000 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800eb7e: e7e6 b.n 800eb4e <tcpip_timeouts_mbox_fetch+0xa>
}
UNLOCK_TCPIP_CORE();
800eb80: 480a ldr r0, [pc, #40] ; (800ebac <tcpip_timeouts_mbox_fetch+0x68>)
800eb82: f00c f9b0 bl 801aee6 <sys_mutex_unlock>
res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
800eb86: 68fa ldr r2, [r7, #12]
800eb88: 6839 ldr r1, [r7, #0]
800eb8a: 6878 ldr r0, [r7, #4]
800eb8c: f00c f922 bl 801add4 <sys_arch_mbox_fetch>
800eb90: 60b8 str r0, [r7, #8]
LOCK_TCPIP_CORE();
800eb92: 4806 ldr r0, [pc, #24] ; (800ebac <tcpip_timeouts_mbox_fetch+0x68>)
800eb94: f00c f998 bl 801aec8 <sys_mutex_lock>
if (res == SYS_ARCH_TIMEOUT) {
800eb98: 68bb ldr r3, [r7, #8]
800eb9a: f1b3 3fff cmp.w r3, #4294967295
800eb9e: d102 bne.n 800eba6 <tcpip_timeouts_mbox_fetch+0x62>
/* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
before a message could be fetched. */
sys_check_timeouts();
800eba0: f007 fa2e bl 8016000 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800eba4: e7d3 b.n 800eb4e <tcpip_timeouts_mbox_fetch+0xa>
}
}
800eba6: 3710 adds r7, #16
800eba8: 46bd mov sp, r7
800ebaa: bd80 pop {r7, pc}
800ebac: 2000be88 .word 0x2000be88
0800ebb0 <tcpip_thread>:
*
* @param arg unused argument
*/
static void
tcpip_thread(void *arg)
{
800ebb0: b580 push {r7, lr}
800ebb2: b084 sub sp, #16
800ebb4: af00 add r7, sp, #0
800ebb6: 6078 str r0, [r7, #4]
struct tcpip_msg *msg;
LWIP_UNUSED_ARG(arg);
LWIP_MARK_TCPIP_THREAD();
LOCK_TCPIP_CORE();
800ebb8: 4810 ldr r0, [pc, #64] ; (800ebfc <tcpip_thread+0x4c>)
800ebba: f00c f985 bl 801aec8 <sys_mutex_lock>
if (tcpip_init_done != NULL) {
800ebbe: 4b10 ldr r3, [pc, #64] ; (800ec00 <tcpip_thread+0x50>)
800ebc0: 681b ldr r3, [r3, #0]
800ebc2: 2b00 cmp r3, #0
800ebc4: d005 beq.n 800ebd2 <tcpip_thread+0x22>
tcpip_init_done(tcpip_init_done_arg);
800ebc6: 4b0e ldr r3, [pc, #56] ; (800ec00 <tcpip_thread+0x50>)
800ebc8: 681b ldr r3, [r3, #0]
800ebca: 4a0e ldr r2, [pc, #56] ; (800ec04 <tcpip_thread+0x54>)
800ebcc: 6812 ldr r2, [r2, #0]
800ebce: 4610 mov r0, r2
800ebd0: 4798 blx r3
}
while (1) { /* MAIN Loop */
LWIP_TCPIP_THREAD_ALIVE();
/* wait for a message, timeouts are processed while waiting */
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800ebd2: f107 030c add.w r3, r7, #12
800ebd6: 4619 mov r1, r3
800ebd8: 480b ldr r0, [pc, #44] ; (800ec08 <tcpip_thread+0x58>)
800ebda: f7ff ffb3 bl 800eb44 <tcpip_timeouts_mbox_fetch>
if (msg == NULL) {
800ebde: 68fb ldr r3, [r7, #12]
800ebe0: 2b00 cmp r3, #0
800ebe2: d106 bne.n 800ebf2 <tcpip_thread+0x42>
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800ebe4: 4b09 ldr r3, [pc, #36] ; (800ec0c <tcpip_thread+0x5c>)
800ebe6: 2291 movs r2, #145 ; 0x91
800ebe8: 4909 ldr r1, [pc, #36] ; (800ec10 <tcpip_thread+0x60>)
800ebea: 480a ldr r0, [pc, #40] ; (800ec14 <tcpip_thread+0x64>)
800ebec: f00c fa12 bl 801b014 <iprintf>
continue;
800ebf0: e003 b.n 800ebfa <tcpip_thread+0x4a>
}
tcpip_thread_handle_msg(msg);
800ebf2: 68fb ldr r3, [r7, #12]
800ebf4: 4618 mov r0, r3
800ebf6: f000 f80f bl 800ec18 <tcpip_thread_handle_msg>
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800ebfa: e7ea b.n 800ebd2 <tcpip_thread+0x22>
800ebfc: 2000be88 .word 0x2000be88
800ec00: 200086d8 .word 0x200086d8
800ec04: 200086dc .word 0x200086dc
800ec08: 200086e0 .word 0x200086e0
800ec0c: 0801bfd4 .word 0x0801bfd4
800ec10: 0801c004 .word 0x0801c004
800ec14: 0801c024 .word 0x0801c024
0800ec18 <tcpip_thread_handle_msg>:
/* Handle a single tcpip_msg
* This is in its own function for access by tests only.
*/
static void
tcpip_thread_handle_msg(struct tcpip_msg *msg)
{
800ec18: b580 push {r7, lr}
800ec1a: b082 sub sp, #8
800ec1c: af00 add r7, sp, #0
800ec1e: 6078 str r0, [r7, #4]
switch (msg->type) {
800ec20: 687b ldr r3, [r7, #4]
800ec22: 781b ldrb r3, [r3, #0]
800ec24: 2b01 cmp r3, #1
800ec26: d018 beq.n 800ec5a <tcpip_thread_handle_msg+0x42>
800ec28: 2b02 cmp r3, #2
800ec2a: d021 beq.n 800ec70 <tcpip_thread_handle_msg+0x58>
800ec2c: 2b00 cmp r3, #0
800ec2e: d126 bne.n 800ec7e <tcpip_thread_handle_msg+0x66>
#endif /* !LWIP_TCPIP_CORE_LOCKING */
#if !LWIP_TCPIP_CORE_LOCKING_INPUT
case TCPIP_MSG_INPKT:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
800ec30: 687b ldr r3, [r7, #4]
800ec32: 68db ldr r3, [r3, #12]
800ec34: 687a ldr r2, [r7, #4]
800ec36: 6850 ldr r0, [r2, #4]
800ec38: 687a ldr r2, [r7, #4]
800ec3a: 6892 ldr r2, [r2, #8]
800ec3c: 4611 mov r1, r2
800ec3e: 4798 blx r3
800ec40: 4603 mov r3, r0
800ec42: 2b00 cmp r3, #0
800ec44: d004 beq.n 800ec50 <tcpip_thread_handle_msg+0x38>
pbuf_free(msg->msg.inp.p);
800ec46: 687b ldr r3, [r7, #4]
800ec48: 685b ldr r3, [r3, #4]
800ec4a: 4618 mov r0, r3
800ec4c: f001 fccc bl 80105e8 <pbuf_free>
}
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ec50: 6879 ldr r1, [r7, #4]
800ec52: 2009 movs r0, #9
800ec54: f000 fe1c bl 800f890 <memp_free>
break;
800ec58: e018 b.n 800ec8c <tcpip_thread_handle_msg+0x74>
break;
#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
case TCPIP_MSG_CALLBACK:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec5a: 687b ldr r3, [r7, #4]
800ec5c: 685b ldr r3, [r3, #4]
800ec5e: 687a ldr r2, [r7, #4]
800ec60: 6892 ldr r2, [r2, #8]
800ec62: 4610 mov r0, r2
800ec64: 4798 blx r3
memp_free(MEMP_TCPIP_MSG_API, msg);
800ec66: 6879 ldr r1, [r7, #4]
800ec68: 2008 movs r0, #8
800ec6a: f000 fe11 bl 800f890 <memp_free>
break;
800ec6e: e00d b.n 800ec8c <tcpip_thread_handle_msg+0x74>
case TCPIP_MSG_CALLBACK_STATIC:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec70: 687b ldr r3, [r7, #4]
800ec72: 685b ldr r3, [r3, #4]
800ec74: 687a ldr r2, [r7, #4]
800ec76: 6892 ldr r2, [r2, #8]
800ec78: 4610 mov r0, r2
800ec7a: 4798 blx r3
break;
800ec7c: e006 b.n 800ec8c <tcpip_thread_handle_msg+0x74>
default:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800ec7e: 4b05 ldr r3, [pc, #20] ; (800ec94 <tcpip_thread_handle_msg+0x7c>)
800ec80: 22cf movs r2, #207 ; 0xcf
800ec82: 4905 ldr r1, [pc, #20] ; (800ec98 <tcpip_thread_handle_msg+0x80>)
800ec84: 4805 ldr r0, [pc, #20] ; (800ec9c <tcpip_thread_handle_msg+0x84>)
800ec86: f00c f9c5 bl 801b014 <iprintf>
break;
800ec8a: bf00 nop
}
}
800ec8c: bf00 nop
800ec8e: 3708 adds r7, #8
800ec90: 46bd mov sp, r7
800ec92: bd80 pop {r7, pc}
800ec94: 0801bfd4 .word 0x0801bfd4
800ec98: 0801c004 .word 0x0801c004
800ec9c: 0801c024 .word 0x0801c024
0800eca0 <tcpip_inpkt>:
* @param inp the network interface on which the packet was received
* @param input_fn input function to call
*/
err_t
tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
{
800eca0: b580 push {r7, lr}
800eca2: b086 sub sp, #24
800eca4: af00 add r7, sp, #0
800eca6: 60f8 str r0, [r7, #12]
800eca8: 60b9 str r1, [r7, #8]
800ecaa: 607a str r2, [r7, #4]
UNLOCK_TCPIP_CORE();
return ret;
#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ecac: 481a ldr r0, [pc, #104] ; (800ed18 <tcpip_inpkt+0x78>)
800ecae: f00c f8d0 bl 801ae52 <sys_mbox_valid>
800ecb2: 4603 mov r3, r0
800ecb4: 2b00 cmp r3, #0
800ecb6: d105 bne.n 800ecc4 <tcpip_inpkt+0x24>
800ecb8: 4b18 ldr r3, [pc, #96] ; (800ed1c <tcpip_inpkt+0x7c>)
800ecba: 22fc movs r2, #252 ; 0xfc
800ecbc: 4918 ldr r1, [pc, #96] ; (800ed20 <tcpip_inpkt+0x80>)
800ecbe: 4819 ldr r0, [pc, #100] ; (800ed24 <tcpip_inpkt+0x84>)
800ecc0: f00c f9a8 bl 801b014 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
800ecc4: 2009 movs r0, #9
800ecc6: f000 fd91 bl 800f7ec <memp_malloc>
800ecca: 6178 str r0, [r7, #20]
if (msg == NULL) {
800eccc: 697b ldr r3, [r7, #20]
800ecce: 2b00 cmp r3, #0
800ecd0: d102 bne.n 800ecd8 <tcpip_inpkt+0x38>
return ERR_MEM;
800ecd2: f04f 33ff mov.w r3, #4294967295
800ecd6: e01a b.n 800ed0e <tcpip_inpkt+0x6e>
}
msg->type = TCPIP_MSG_INPKT;
800ecd8: 697b ldr r3, [r7, #20]
800ecda: 2200 movs r2, #0
800ecdc: 701a strb r2, [r3, #0]
msg->msg.inp.p = p;
800ecde: 697b ldr r3, [r7, #20]
800ece0: 68fa ldr r2, [r7, #12]
800ece2: 605a str r2, [r3, #4]
msg->msg.inp.netif = inp;
800ece4: 697b ldr r3, [r7, #20]
800ece6: 68ba ldr r2, [r7, #8]
800ece8: 609a str r2, [r3, #8]
msg->msg.inp.input_fn = input_fn;
800ecea: 697b ldr r3, [r7, #20]
800ecec: 687a ldr r2, [r7, #4]
800ecee: 60da str r2, [r3, #12]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800ecf0: 6979 ldr r1, [r7, #20]
800ecf2: 4809 ldr r0, [pc, #36] ; (800ed18 <tcpip_inpkt+0x78>)
800ecf4: f00c f854 bl 801ada0 <sys_mbox_trypost>
800ecf8: 4603 mov r3, r0
800ecfa: 2b00 cmp r3, #0
800ecfc: d006 beq.n 800ed0c <tcpip_inpkt+0x6c>
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ecfe: 6979 ldr r1, [r7, #20]
800ed00: 2009 movs r0, #9
800ed02: f000 fdc5 bl 800f890 <memp_free>
return ERR_MEM;
800ed06: f04f 33ff mov.w r3, #4294967295
800ed0a: e000 b.n 800ed0e <tcpip_inpkt+0x6e>
}
return ERR_OK;
800ed0c: 2300 movs r3, #0
#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
}
800ed0e: 4618 mov r0, r3
800ed10: 3718 adds r7, #24
800ed12: 46bd mov sp, r7
800ed14: bd80 pop {r7, pc}
800ed16: bf00 nop
800ed18: 200086e0 .word 0x200086e0
800ed1c: 0801bfd4 .word 0x0801bfd4
800ed20: 0801c04c .word 0x0801c04c
800ed24: 0801c024 .word 0x0801c024
0800ed28 <tcpip_input>:
* NETIF_FLAG_ETHERNET flags)
* @param inp the network interface on which the packet was received
*/
err_t
tcpip_input(struct pbuf *p, struct netif *inp)
{
800ed28: b580 push {r7, lr}
800ed2a: b082 sub sp, #8
800ed2c: af00 add r7, sp, #0
800ed2e: 6078 str r0, [r7, #4]
800ed30: 6039 str r1, [r7, #0]
#if LWIP_ETHERNET
if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
800ed32: 683b ldr r3, [r7, #0]
800ed34: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800ed38: f003 0318 and.w r3, r3, #24
800ed3c: 2b00 cmp r3, #0
800ed3e: d006 beq.n 800ed4e <tcpip_input+0x26>
return tcpip_inpkt(p, inp, ethernet_input);
800ed40: 4a08 ldr r2, [pc, #32] ; (800ed64 <tcpip_input+0x3c>)
800ed42: 6839 ldr r1, [r7, #0]
800ed44: 6878 ldr r0, [r7, #4]
800ed46: f7ff ffab bl 800eca0 <tcpip_inpkt>
800ed4a: 4603 mov r3, r0
800ed4c: e005 b.n 800ed5a <tcpip_input+0x32>
} else
#endif /* LWIP_ETHERNET */
return tcpip_inpkt(p, inp, ip_input);
800ed4e: 4a06 ldr r2, [pc, #24] ; (800ed68 <tcpip_input+0x40>)
800ed50: 6839 ldr r1, [r7, #0]
800ed52: 6878 ldr r0, [r7, #4]
800ed54: f7ff ffa4 bl 800eca0 <tcpip_inpkt>
800ed58: 4603 mov r3, r0
}
800ed5a: 4618 mov r0, r3
800ed5c: 3708 adds r7, #8
800ed5e: 46bd mov sp, r7
800ed60: bd80 pop {r7, pc}
800ed62: bf00 nop
800ed64: 0801abb1 .word 0x0801abb1
800ed68: 08019a95 .word 0x08019a95
0800ed6c <tcpip_try_callback>:
*
* @see tcpip_callback
*/
err_t
tcpip_try_callback(tcpip_callback_fn function, void *ctx)
{
800ed6c: b580 push {r7, lr}
800ed6e: b084 sub sp, #16
800ed70: af00 add r7, sp, #0
800ed72: 6078 str r0, [r7, #4]
800ed74: 6039 str r1, [r7, #0]
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ed76: 4819 ldr r0, [pc, #100] ; (800eddc <tcpip_try_callback+0x70>)
800ed78: f00c f86b bl 801ae52 <sys_mbox_valid>
800ed7c: 4603 mov r3, r0
800ed7e: 2b00 cmp r3, #0
800ed80: d106 bne.n 800ed90 <tcpip_try_callback+0x24>
800ed82: 4b17 ldr r3, [pc, #92] ; (800ede0 <tcpip_try_callback+0x74>)
800ed84: f240 125d movw r2, #349 ; 0x15d
800ed88: 4916 ldr r1, [pc, #88] ; (800ede4 <tcpip_try_callback+0x78>)
800ed8a: 4817 ldr r0, [pc, #92] ; (800ede8 <tcpip_try_callback+0x7c>)
800ed8c: f00c f942 bl 801b014 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
800ed90: 2008 movs r0, #8
800ed92: f000 fd2b bl 800f7ec <memp_malloc>
800ed96: 60f8 str r0, [r7, #12]
if (msg == NULL) {
800ed98: 68fb ldr r3, [r7, #12]
800ed9a: 2b00 cmp r3, #0
800ed9c: d102 bne.n 800eda4 <tcpip_try_callback+0x38>
return ERR_MEM;
800ed9e: f04f 33ff mov.w r3, #4294967295
800eda2: e017 b.n 800edd4 <tcpip_try_callback+0x68>
}
msg->type = TCPIP_MSG_CALLBACK;
800eda4: 68fb ldr r3, [r7, #12]
800eda6: 2201 movs r2, #1
800eda8: 701a strb r2, [r3, #0]
msg->msg.cb.function = function;
800edaa: 68fb ldr r3, [r7, #12]
800edac: 687a ldr r2, [r7, #4]
800edae: 605a str r2, [r3, #4]
msg->msg.cb.ctx = ctx;
800edb0: 68fb ldr r3, [r7, #12]
800edb2: 683a ldr r2, [r7, #0]
800edb4: 609a str r2, [r3, #8]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800edb6: 68f9 ldr r1, [r7, #12]
800edb8: 4808 ldr r0, [pc, #32] ; (800eddc <tcpip_try_callback+0x70>)
800edba: f00b fff1 bl 801ada0 <sys_mbox_trypost>
800edbe: 4603 mov r3, r0
800edc0: 2b00 cmp r3, #0
800edc2: d006 beq.n 800edd2 <tcpip_try_callback+0x66>
memp_free(MEMP_TCPIP_MSG_API, msg);
800edc4: 68f9 ldr r1, [r7, #12]
800edc6: 2008 movs r0, #8
800edc8: f000 fd62 bl 800f890 <memp_free>
return ERR_MEM;
800edcc: f04f 33ff mov.w r3, #4294967295
800edd0: e000 b.n 800edd4 <tcpip_try_callback+0x68>
}
return ERR_OK;
800edd2: 2300 movs r3, #0
}
800edd4: 4618 mov r0, r3
800edd6: 3710 adds r7, #16
800edd8: 46bd mov sp, r7
800edda: bd80 pop {r7, pc}
800eddc: 200086e0 .word 0x200086e0
800ede0: 0801bfd4 .word 0x0801bfd4
800ede4: 0801c04c .word 0x0801c04c
800ede8: 0801c024 .word 0x0801c024
0800edec <tcpip_init>:
* @param initfunc a function to call when tcpip_thread is running and finished initializing
* @param arg argument to pass to initfunc
*/
void
tcpip_init(tcpip_init_done_fn initfunc, void *arg)
{
800edec: b580 push {r7, lr}
800edee: b084 sub sp, #16
800edf0: af02 add r7, sp, #8
800edf2: 6078 str r0, [r7, #4]
800edf4: 6039 str r1, [r7, #0]
lwip_init();
800edf6: f000 f871 bl 800eedc <lwip_init>
tcpip_init_done = initfunc;
800edfa: 4a17 ldr r2, [pc, #92] ; (800ee58 <tcpip_init+0x6c>)
800edfc: 687b ldr r3, [r7, #4]
800edfe: 6013 str r3, [r2, #0]
tcpip_init_done_arg = arg;
800ee00: 4a16 ldr r2, [pc, #88] ; (800ee5c <tcpip_init+0x70>)
800ee02: 683b ldr r3, [r7, #0]
800ee04: 6013 str r3, [r2, #0]
if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
800ee06: 2106 movs r1, #6
800ee08: 4815 ldr r0, [pc, #84] ; (800ee60 <tcpip_init+0x74>)
800ee0a: f00b ffa7 bl 801ad5c <sys_mbox_new>
800ee0e: 4603 mov r3, r0
800ee10: 2b00 cmp r3, #0
800ee12: d006 beq.n 800ee22 <tcpip_init+0x36>
LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
800ee14: 4b13 ldr r3, [pc, #76] ; (800ee64 <tcpip_init+0x78>)
800ee16: f240 2261 movw r2, #609 ; 0x261
800ee1a: 4913 ldr r1, [pc, #76] ; (800ee68 <tcpip_init+0x7c>)
800ee1c: 4813 ldr r0, [pc, #76] ; (800ee6c <tcpip_init+0x80>)
800ee1e: f00c f8f9 bl 801b014 <iprintf>
}
#if LWIP_TCPIP_CORE_LOCKING
if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
800ee22: 4813 ldr r0, [pc, #76] ; (800ee70 <tcpip_init+0x84>)
800ee24: f00c f834 bl 801ae90 <sys_mutex_new>
800ee28: 4603 mov r3, r0
800ee2a: 2b00 cmp r3, #0
800ee2c: d006 beq.n 800ee3c <tcpip_init+0x50>
LWIP_ASSERT("failed to create lock_tcpip_core", 0);
800ee2e: 4b0d ldr r3, [pc, #52] ; (800ee64 <tcpip_init+0x78>)
800ee30: f240 2265 movw r2, #613 ; 0x265
800ee34: 490f ldr r1, [pc, #60] ; (800ee74 <tcpip_init+0x88>)
800ee36: 480d ldr r0, [pc, #52] ; (800ee6c <tcpip_init+0x80>)
800ee38: f00c f8ec bl 801b014 <iprintf>
}
#endif /* LWIP_TCPIP_CORE_LOCKING */
sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
800ee3c: 2300 movs r3, #0
800ee3e: 9300 str r3, [sp, #0]
800ee40: f44f 6380 mov.w r3, #1024 ; 0x400
800ee44: 2200 movs r2, #0
800ee46: 490c ldr r1, [pc, #48] ; (800ee78 <tcpip_init+0x8c>)
800ee48: 480c ldr r0, [pc, #48] ; (800ee7c <tcpip_init+0x90>)
800ee4a: f00c f859 bl 801af00 <sys_thread_new>
}
800ee4e: bf00 nop
800ee50: 3708 adds r7, #8
800ee52: 46bd mov sp, r7
800ee54: bd80 pop {r7, pc}
800ee56: bf00 nop
800ee58: 200086d8 .word 0x200086d8
800ee5c: 200086dc .word 0x200086dc
800ee60: 200086e0 .word 0x200086e0
800ee64: 0801bfd4 .word 0x0801bfd4
800ee68: 0801c05c .word 0x0801c05c
800ee6c: 0801c024 .word 0x0801c024
800ee70: 2000be88 .word 0x2000be88
800ee74: 0801c080 .word 0x0801c080
800ee78: 0800ebb1 .word 0x0800ebb1
800ee7c: 0801c0a4 .word 0x0801c0a4
0800ee80 <lwip_htons>:
* @param n u16_t in host byte order
* @return n in network byte order
*/
u16_t
lwip_htons(u16_t n)
{
800ee80: b480 push {r7}
800ee82: b083 sub sp, #12
800ee84: af00 add r7, sp, #0
800ee86: 4603 mov r3, r0
800ee88: 80fb strh r3, [r7, #6]
return PP_HTONS(n);
800ee8a: 88fb ldrh r3, [r7, #6]
800ee8c: 021b lsls r3, r3, #8
800ee8e: b21a sxth r2, r3
800ee90: 88fb ldrh r3, [r7, #6]
800ee92: 0a1b lsrs r3, r3, #8
800ee94: b29b uxth r3, r3
800ee96: b21b sxth r3, r3
800ee98: 4313 orrs r3, r2
800ee9a: b21b sxth r3, r3
800ee9c: b29b uxth r3, r3
}
800ee9e: 4618 mov r0, r3
800eea0: 370c adds r7, #12
800eea2: 46bd mov sp, r7
800eea4: f85d 7b04 ldr.w r7, [sp], #4
800eea8: 4770 bx lr
0800eeaa <lwip_htonl>:
* @param n u32_t in host byte order
* @return n in network byte order
*/
u32_t
lwip_htonl(u32_t n)
{
800eeaa: b480 push {r7}
800eeac: b083 sub sp, #12
800eeae: af00 add r7, sp, #0
800eeb0: 6078 str r0, [r7, #4]
return PP_HTONL(n);
800eeb2: 687b ldr r3, [r7, #4]
800eeb4: 061a lsls r2, r3, #24
800eeb6: 687b ldr r3, [r7, #4]
800eeb8: 021b lsls r3, r3, #8
800eeba: f403 037f and.w r3, r3, #16711680 ; 0xff0000
800eebe: 431a orrs r2, r3
800eec0: 687b ldr r3, [r7, #4]
800eec2: 0a1b lsrs r3, r3, #8
800eec4: f403 437f and.w r3, r3, #65280 ; 0xff00
800eec8: 431a orrs r2, r3
800eeca: 687b ldr r3, [r7, #4]
800eecc: 0e1b lsrs r3, r3, #24
800eece: 4313 orrs r3, r2
}
800eed0: 4618 mov r0, r3
800eed2: 370c adds r7, #12
800eed4: 46bd mov sp, r7
800eed6: f85d 7b04 ldr.w r7, [sp], #4
800eeda: 4770 bx lr
0800eedc <lwip_init>:
* Initialize all modules.
* Use this in NO_SYS mode. Use tcpip_init() otherwise.
*/
void
lwip_init(void)
{
800eedc: b580 push {r7, lr}
800eede: b082 sub sp, #8
800eee0: af00 add r7, sp, #0
#ifndef LWIP_SKIP_CONST_CHECK
int a = 0;
800eee2: 2300 movs r3, #0
800eee4: 607b str r3, [r7, #4]
#endif
/* Modules initialization */
stats_init();
#if !NO_SYS
sys_init();
800eee6: f00b ffc5 bl 801ae74 <sys_init>
#endif /* !NO_SYS */
mem_init();
800eeea: f000 f8d5 bl 800f098 <mem_init>
memp_init();
800eeee: f000 fc31 bl 800f754 <memp_init>
pbuf_init();
netif_init();
800eef2: f000 fcf7 bl 800f8e4 <netif_init>
#endif /* LWIP_IPV4 */
#if LWIP_RAW
raw_init();
#endif /* LWIP_RAW */
#if LWIP_UDP
udp_init();
800eef6: f007 f8f5 bl 80160e4 <udp_init>
#endif /* LWIP_UDP */
#if LWIP_TCP
tcp_init();
800eefa: f001 fe1f bl 8010b3c <tcp_init>
#if PPP_SUPPORT
ppp_init();
#endif
#if LWIP_TIMERS
sys_timeouts_init();
800eefe: f007 f839 bl 8015f74 <sys_timeouts_init>
#endif /* LWIP_TIMERS */
}
800ef02: bf00 nop
800ef04: 3708 adds r7, #8
800ef06: 46bd mov sp, r7
800ef08: bd80 pop {r7, pc}
...
0800ef0c <ptr_to_mem>:
#define mem_overflow_check_element(mem)
#endif /* MEM_OVERFLOW_CHECK */
static struct mem *
ptr_to_mem(mem_size_t ptr)
{
800ef0c: b480 push {r7}
800ef0e: b083 sub sp, #12
800ef10: af00 add r7, sp, #0
800ef12: 4603 mov r3, r0
800ef14: 80fb strh r3, [r7, #6]
return (struct mem *)(void *)&ram[ptr];
800ef16: 4b05 ldr r3, [pc, #20] ; (800ef2c <ptr_to_mem+0x20>)
800ef18: 681a ldr r2, [r3, #0]
800ef1a: 88fb ldrh r3, [r7, #6]
800ef1c: 4413 add r3, r2
}
800ef1e: 4618 mov r0, r3
800ef20: 370c adds r7, #12
800ef22: 46bd mov sp, r7
800ef24: f85d 7b04 ldr.w r7, [sp], #4
800ef28: 4770 bx lr
800ef2a: bf00 nop
800ef2c: 200086e4 .word 0x200086e4
0800ef30 <mem_to_ptr>:
static mem_size_t
mem_to_ptr(void *mem)
{
800ef30: b480 push {r7}
800ef32: b083 sub sp, #12
800ef34: af00 add r7, sp, #0
800ef36: 6078 str r0, [r7, #4]
return (mem_size_t)((u8_t *)mem - ram);
800ef38: 687b ldr r3, [r7, #4]
800ef3a: 4a05 ldr r2, [pc, #20] ; (800ef50 <mem_to_ptr+0x20>)
800ef3c: 6812 ldr r2, [r2, #0]
800ef3e: 1a9b subs r3, r3, r2
800ef40: b29b uxth r3, r3
}
800ef42: 4618 mov r0, r3
800ef44: 370c adds r7, #12
800ef46: 46bd mov sp, r7
800ef48: f85d 7b04 ldr.w r7, [sp], #4
800ef4c: 4770 bx lr
800ef4e: bf00 nop
800ef50: 200086e4 .word 0x200086e4
0800ef54 <plug_holes>:
* This assumes access to the heap is protected by the calling function
* already.
*/
static void
plug_holes(struct mem *mem)
{
800ef54: b590 push {r4, r7, lr}
800ef56: b085 sub sp, #20
800ef58: af00 add r7, sp, #0
800ef5a: 6078 str r0, [r7, #4]
struct mem *nmem;
struct mem *pmem;
LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
800ef5c: 4b45 ldr r3, [pc, #276] ; (800f074 <plug_holes+0x120>)
800ef5e: 681b ldr r3, [r3, #0]
800ef60: 687a ldr r2, [r7, #4]
800ef62: 429a cmp r2, r3
800ef64: d206 bcs.n 800ef74 <plug_holes+0x20>
800ef66: 4b44 ldr r3, [pc, #272] ; (800f078 <plug_holes+0x124>)
800ef68: f240 12df movw r2, #479 ; 0x1df
800ef6c: 4943 ldr r1, [pc, #268] ; (800f07c <plug_holes+0x128>)
800ef6e: 4844 ldr r0, [pc, #272] ; (800f080 <plug_holes+0x12c>)
800ef70: f00c f850 bl 801b014 <iprintf>
LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
800ef74: 4b43 ldr r3, [pc, #268] ; (800f084 <plug_holes+0x130>)
800ef76: 681b ldr r3, [r3, #0]
800ef78: 687a ldr r2, [r7, #4]
800ef7a: 429a cmp r2, r3
800ef7c: d306 bcc.n 800ef8c <plug_holes+0x38>
800ef7e: 4b3e ldr r3, [pc, #248] ; (800f078 <plug_holes+0x124>)
800ef80: f44f 72f0 mov.w r2, #480 ; 0x1e0
800ef84: 4940 ldr r1, [pc, #256] ; (800f088 <plug_holes+0x134>)
800ef86: 483e ldr r0, [pc, #248] ; (800f080 <plug_holes+0x12c>)
800ef88: f00c f844 bl 801b014 <iprintf>
LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
800ef8c: 687b ldr r3, [r7, #4]
800ef8e: 791b ldrb r3, [r3, #4]
800ef90: 2b00 cmp r3, #0
800ef92: d006 beq.n 800efa2 <plug_holes+0x4e>
800ef94: 4b38 ldr r3, [pc, #224] ; (800f078 <plug_holes+0x124>)
800ef96: f240 12e1 movw r2, #481 ; 0x1e1
800ef9a: 493c ldr r1, [pc, #240] ; (800f08c <plug_holes+0x138>)
800ef9c: 4838 ldr r0, [pc, #224] ; (800f080 <plug_holes+0x12c>)
800ef9e: f00c f839 bl 801b014 <iprintf>
/* plug hole forward */
LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
800efa2: 687b ldr r3, [r7, #4]
800efa4: 881b ldrh r3, [r3, #0]
800efa6: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800efaa: d906 bls.n 800efba <plug_holes+0x66>
800efac: 4b32 ldr r3, [pc, #200] ; (800f078 <plug_holes+0x124>)
800efae: f44f 72f2 mov.w r2, #484 ; 0x1e4
800efb2: 4937 ldr r1, [pc, #220] ; (800f090 <plug_holes+0x13c>)
800efb4: 4832 ldr r0, [pc, #200] ; (800f080 <plug_holes+0x12c>)
800efb6: f00c f82d bl 801b014 <iprintf>
nmem = ptr_to_mem(mem->next);
800efba: 687b ldr r3, [r7, #4]
800efbc: 881b ldrh r3, [r3, #0]
800efbe: 4618 mov r0, r3
800efc0: f7ff ffa4 bl 800ef0c <ptr_to_mem>
800efc4: 60f8 str r0, [r7, #12]
if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
800efc6: 687a ldr r2, [r7, #4]
800efc8: 68fb ldr r3, [r7, #12]
800efca: 429a cmp r2, r3
800efcc: d024 beq.n 800f018 <plug_holes+0xc4>
800efce: 68fb ldr r3, [r7, #12]
800efd0: 791b ldrb r3, [r3, #4]
800efd2: 2b00 cmp r3, #0
800efd4: d120 bne.n 800f018 <plug_holes+0xc4>
800efd6: 4b2b ldr r3, [pc, #172] ; (800f084 <plug_holes+0x130>)
800efd8: 681b ldr r3, [r3, #0]
800efda: 68fa ldr r2, [r7, #12]
800efdc: 429a cmp r2, r3
800efde: d01b beq.n 800f018 <plug_holes+0xc4>
/* if mem->next is unused and not end of ram, combine mem and mem->next */
if (lfree == nmem) {
800efe0: 4b2c ldr r3, [pc, #176] ; (800f094 <plug_holes+0x140>)
800efe2: 681b ldr r3, [r3, #0]
800efe4: 68fa ldr r2, [r7, #12]
800efe6: 429a cmp r2, r3
800efe8: d102 bne.n 800eff0 <plug_holes+0x9c>
lfree = mem;
800efea: 4a2a ldr r2, [pc, #168] ; (800f094 <plug_holes+0x140>)
800efec: 687b ldr r3, [r7, #4]
800efee: 6013 str r3, [r2, #0]
}
mem->next = nmem->next;
800eff0: 68fb ldr r3, [r7, #12]
800eff2: 881a ldrh r2, [r3, #0]
800eff4: 687b ldr r3, [r7, #4]
800eff6: 801a strh r2, [r3, #0]
if (nmem->next != MEM_SIZE_ALIGNED) {
800eff8: 68fb ldr r3, [r7, #12]
800effa: 881b ldrh r3, [r3, #0]
800effc: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f000: d00a beq.n 800f018 <plug_holes+0xc4>
ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
800f002: 68fb ldr r3, [r7, #12]
800f004: 881b ldrh r3, [r3, #0]
800f006: 4618 mov r0, r3
800f008: f7ff ff80 bl 800ef0c <ptr_to_mem>
800f00c: 4604 mov r4, r0
800f00e: 6878 ldr r0, [r7, #4]
800f010: f7ff ff8e bl 800ef30 <mem_to_ptr>
800f014: 4603 mov r3, r0
800f016: 8063 strh r3, [r4, #2]
}
}
/* plug hole backward */
pmem = ptr_to_mem(mem->prev);
800f018: 687b ldr r3, [r7, #4]
800f01a: 885b ldrh r3, [r3, #2]
800f01c: 4618 mov r0, r3
800f01e: f7ff ff75 bl 800ef0c <ptr_to_mem>
800f022: 60b8 str r0, [r7, #8]
if (pmem != mem && pmem->used == 0) {
800f024: 68ba ldr r2, [r7, #8]
800f026: 687b ldr r3, [r7, #4]
800f028: 429a cmp r2, r3
800f02a: d01f beq.n 800f06c <plug_holes+0x118>
800f02c: 68bb ldr r3, [r7, #8]
800f02e: 791b ldrb r3, [r3, #4]
800f030: 2b00 cmp r3, #0
800f032: d11b bne.n 800f06c <plug_holes+0x118>
/* if mem->prev is unused, combine mem and mem->prev */
if (lfree == mem) {
800f034: 4b17 ldr r3, [pc, #92] ; (800f094 <plug_holes+0x140>)
800f036: 681b ldr r3, [r3, #0]
800f038: 687a ldr r2, [r7, #4]
800f03a: 429a cmp r2, r3
800f03c: d102 bne.n 800f044 <plug_holes+0xf0>
lfree = pmem;
800f03e: 4a15 ldr r2, [pc, #84] ; (800f094 <plug_holes+0x140>)
800f040: 68bb ldr r3, [r7, #8]
800f042: 6013 str r3, [r2, #0]
}
pmem->next = mem->next;
800f044: 687b ldr r3, [r7, #4]
800f046: 881a ldrh r2, [r3, #0]
800f048: 68bb ldr r3, [r7, #8]
800f04a: 801a strh r2, [r3, #0]
if (mem->next != MEM_SIZE_ALIGNED) {
800f04c: 687b ldr r3, [r7, #4]
800f04e: 881b ldrh r3, [r3, #0]
800f050: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f054: d00a beq.n 800f06c <plug_holes+0x118>
ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
800f056: 687b ldr r3, [r7, #4]
800f058: 881b ldrh r3, [r3, #0]
800f05a: 4618 mov r0, r3
800f05c: f7ff ff56 bl 800ef0c <ptr_to_mem>
800f060: 4604 mov r4, r0
800f062: 68b8 ldr r0, [r7, #8]
800f064: f7ff ff64 bl 800ef30 <mem_to_ptr>
800f068: 4603 mov r3, r0
800f06a: 8063 strh r3, [r4, #2]
}
}
}
800f06c: bf00 nop
800f06e: 3714 adds r7, #20
800f070: 46bd mov sp, r7
800f072: bd90 pop {r4, r7, pc}
800f074: 200086e4 .word 0x200086e4
800f078: 0801c0b4 .word 0x0801c0b4
800f07c: 0801c0e4 .word 0x0801c0e4
800f080: 0801c0fc .word 0x0801c0fc
800f084: 200086e8 .word 0x200086e8
800f088: 0801c124 .word 0x0801c124
800f08c: 0801c140 .word 0x0801c140
800f090: 0801c15c .word 0x0801c15c
800f094: 200086f0 .word 0x200086f0
0800f098 <mem_init>:
/**
* Zero the heap and initialize start, end and lowest-free
*/
void
mem_init(void)
{
800f098: b580 push {r7, lr}
800f09a: b082 sub sp, #8
800f09c: af00 add r7, sp, #0
LWIP_ASSERT("Sanity check alignment",
(SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
/* align the heap */
ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
800f09e: 4b1f ldr r3, [pc, #124] ; (800f11c <mem_init+0x84>)
800f0a0: 3303 adds r3, #3
800f0a2: f023 0303 bic.w r3, r3, #3
800f0a6: 461a mov r2, r3
800f0a8: 4b1d ldr r3, [pc, #116] ; (800f120 <mem_init+0x88>)
800f0aa: 601a str r2, [r3, #0]
/* initialize the start of the heap */
mem = (struct mem *)(void *)ram;
800f0ac: 4b1c ldr r3, [pc, #112] ; (800f120 <mem_init+0x88>)
800f0ae: 681b ldr r3, [r3, #0]
800f0b0: 607b str r3, [r7, #4]
mem->next = MEM_SIZE_ALIGNED;
800f0b2: 687b ldr r3, [r7, #4]
800f0b4: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0b8: 801a strh r2, [r3, #0]
mem->prev = 0;
800f0ba: 687b ldr r3, [r7, #4]
800f0bc: 2200 movs r2, #0
800f0be: 805a strh r2, [r3, #2]
mem->used = 0;
800f0c0: 687b ldr r3, [r7, #4]
800f0c2: 2200 movs r2, #0
800f0c4: 711a strb r2, [r3, #4]
/* initialize the end of the heap */
ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
800f0c6: f44f 60c8 mov.w r0, #1600 ; 0x640
800f0ca: f7ff ff1f bl 800ef0c <ptr_to_mem>
800f0ce: 4602 mov r2, r0
800f0d0: 4b14 ldr r3, [pc, #80] ; (800f124 <mem_init+0x8c>)
800f0d2: 601a str r2, [r3, #0]
ram_end->used = 1;
800f0d4: 4b13 ldr r3, [pc, #76] ; (800f124 <mem_init+0x8c>)
800f0d6: 681b ldr r3, [r3, #0]
800f0d8: 2201 movs r2, #1
800f0da: 711a strb r2, [r3, #4]
ram_end->next = MEM_SIZE_ALIGNED;
800f0dc: 4b11 ldr r3, [pc, #68] ; (800f124 <mem_init+0x8c>)
800f0de: 681b ldr r3, [r3, #0]
800f0e0: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0e4: 801a strh r2, [r3, #0]
ram_end->prev = MEM_SIZE_ALIGNED;
800f0e6: 4b0f ldr r3, [pc, #60] ; (800f124 <mem_init+0x8c>)
800f0e8: 681b ldr r3, [r3, #0]
800f0ea: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0ee: 805a strh r2, [r3, #2]
MEM_SANITY();
/* initialize the lowest-free pointer to the start of the heap */
lfree = (struct mem *)(void *)ram;
800f0f0: 4b0b ldr r3, [pc, #44] ; (800f120 <mem_init+0x88>)
800f0f2: 681b ldr r3, [r3, #0]
800f0f4: 4a0c ldr r2, [pc, #48] ; (800f128 <mem_init+0x90>)
800f0f6: 6013 str r3, [r2, #0]
MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
if (sys_mutex_new(&mem_mutex) != ERR_OK) {
800f0f8: 480c ldr r0, [pc, #48] ; (800f12c <mem_init+0x94>)
800f0fa: f00b fec9 bl 801ae90 <sys_mutex_new>
800f0fe: 4603 mov r3, r0
800f100: 2b00 cmp r3, #0
800f102: d006 beq.n 800f112 <mem_init+0x7a>
LWIP_ASSERT("failed to create mem_mutex", 0);
800f104: 4b0a ldr r3, [pc, #40] ; (800f130 <mem_init+0x98>)
800f106: f240 221f movw r2, #543 ; 0x21f
800f10a: 490a ldr r1, [pc, #40] ; (800f134 <mem_init+0x9c>)
800f10c: 480a ldr r0, [pc, #40] ; (800f138 <mem_init+0xa0>)
800f10e: f00b ff81 bl 801b014 <iprintf>
}
}
800f112: bf00 nop
800f114: 3708 adds r7, #8
800f116: 46bd mov sp, r7
800f118: bd80 pop {r7, pc}
800f11a: bf00 nop
800f11c: 2000bea4 .word 0x2000bea4
800f120: 200086e4 .word 0x200086e4
800f124: 200086e8 .word 0x200086e8
800f128: 200086f0 .word 0x200086f0
800f12c: 200086ec .word 0x200086ec
800f130: 0801c0b4 .word 0x0801c0b4
800f134: 0801c188 .word 0x0801c188
800f138: 0801c0fc .word 0x0801c0fc
0800f13c <mem_link_valid>:
/* Check if a struct mem is correctly linked.
* If not, double-free is a possible reason.
*/
static int
mem_link_valid(struct mem *mem)
{
800f13c: b580 push {r7, lr}
800f13e: b086 sub sp, #24
800f140: af00 add r7, sp, #0
800f142: 6078 str r0, [r7, #4]
struct mem *nmem, *pmem;
mem_size_t rmem_idx;
rmem_idx = mem_to_ptr(mem);
800f144: 6878 ldr r0, [r7, #4]
800f146: f7ff fef3 bl 800ef30 <mem_to_ptr>
800f14a: 4603 mov r3, r0
800f14c: 82fb strh r3, [r7, #22]
nmem = ptr_to_mem(mem->next);
800f14e: 687b ldr r3, [r7, #4]
800f150: 881b ldrh r3, [r3, #0]
800f152: 4618 mov r0, r3
800f154: f7ff feda bl 800ef0c <ptr_to_mem>
800f158: 6138 str r0, [r7, #16]
pmem = ptr_to_mem(mem->prev);
800f15a: 687b ldr r3, [r7, #4]
800f15c: 885b ldrh r3, [r3, #2]
800f15e: 4618 mov r0, r3
800f160: f7ff fed4 bl 800ef0c <ptr_to_mem>
800f164: 60f8 str r0, [r7, #12]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f166: 687b ldr r3, [r7, #4]
800f168: 881b ldrh r3, [r3, #0]
800f16a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f16e: d818 bhi.n 800f1a2 <mem_link_valid+0x66>
800f170: 687b ldr r3, [r7, #4]
800f172: 885b ldrh r3, [r3, #2]
800f174: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f178: d813 bhi.n 800f1a2 <mem_link_valid+0x66>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f17a: 687b ldr r3, [r7, #4]
800f17c: 885b ldrh r3, [r3, #2]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f17e: 8afa ldrh r2, [r7, #22]
800f180: 429a cmp r2, r3
800f182: d004 beq.n 800f18e <mem_link_valid+0x52>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f184: 68fb ldr r3, [r7, #12]
800f186: 881b ldrh r3, [r3, #0]
800f188: 8afa ldrh r2, [r7, #22]
800f18a: 429a cmp r2, r3
800f18c: d109 bne.n 800f1a2 <mem_link_valid+0x66>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f18e: 4b08 ldr r3, [pc, #32] ; (800f1b0 <mem_link_valid+0x74>)
800f190: 681b ldr r3, [r3, #0]
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f192: 693a ldr r2, [r7, #16]
800f194: 429a cmp r2, r3
800f196: d006 beq.n 800f1a6 <mem_link_valid+0x6a>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f198: 693b ldr r3, [r7, #16]
800f19a: 885b ldrh r3, [r3, #2]
800f19c: 8afa ldrh r2, [r7, #22]
800f19e: 429a cmp r2, r3
800f1a0: d001 beq.n 800f1a6 <mem_link_valid+0x6a>
return 0;
800f1a2: 2300 movs r3, #0
800f1a4: e000 b.n 800f1a8 <mem_link_valid+0x6c>
}
return 1;
800f1a6: 2301 movs r3, #1
}
800f1a8: 4618 mov r0, r3
800f1aa: 3718 adds r7, #24
800f1ac: 46bd mov sp, r7
800f1ae: bd80 pop {r7, pc}
800f1b0: 200086e8 .word 0x200086e8
0800f1b4 <mem_free>:
* @param rmem is the data portion of a struct mem as returned by a previous
* call to mem_malloc()
*/
void
mem_free(void *rmem)
{
800f1b4: b580 push {r7, lr}
800f1b6: b088 sub sp, #32
800f1b8: af00 add r7, sp, #0
800f1ba: 6078 str r0, [r7, #4]
struct mem *mem;
LWIP_MEM_FREE_DECL_PROTECT();
if (rmem == NULL) {
800f1bc: 687b ldr r3, [r7, #4]
800f1be: 2b00 cmp r3, #0
800f1c0: d070 beq.n 800f2a4 <mem_free+0xf0>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
return;
}
if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
800f1c2: 687b ldr r3, [r7, #4]
800f1c4: f003 0303 and.w r3, r3, #3
800f1c8: 2b00 cmp r3, #0
800f1ca: d00d beq.n 800f1e8 <mem_free+0x34>
LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
800f1cc: 4b37 ldr r3, [pc, #220] ; (800f2ac <mem_free+0xf8>)
800f1ce: f240 2273 movw r2, #627 ; 0x273
800f1d2: 4937 ldr r1, [pc, #220] ; (800f2b0 <mem_free+0xfc>)
800f1d4: 4837 ldr r0, [pc, #220] ; (800f2b4 <mem_free+0x100>)
800f1d6: f00b ff1d bl 801b014 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f1da: f00b feb7 bl 801af4c <sys_arch_protect>
800f1de: 60f8 str r0, [r7, #12]
800f1e0: 68f8 ldr r0, [r7, #12]
800f1e2: f00b fec1 bl 801af68 <sys_arch_unprotect>
return;
800f1e6: e05e b.n 800f2a6 <mem_free+0xf2>
}
/* Get the corresponding struct mem: */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f1e8: 687b ldr r3, [r7, #4]
800f1ea: 3b08 subs r3, #8
800f1ec: 61fb str r3, [r7, #28]
if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
800f1ee: 4b32 ldr r3, [pc, #200] ; (800f2b8 <mem_free+0x104>)
800f1f0: 681b ldr r3, [r3, #0]
800f1f2: 69fa ldr r2, [r7, #28]
800f1f4: 429a cmp r2, r3
800f1f6: d306 bcc.n 800f206 <mem_free+0x52>
800f1f8: 687b ldr r3, [r7, #4]
800f1fa: f103 020c add.w r2, r3, #12
800f1fe: 4b2f ldr r3, [pc, #188] ; (800f2bc <mem_free+0x108>)
800f200: 681b ldr r3, [r3, #0]
800f202: 429a cmp r2, r3
800f204: d90d bls.n 800f222 <mem_free+0x6e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
800f206: 4b29 ldr r3, [pc, #164] ; (800f2ac <mem_free+0xf8>)
800f208: f240 227f movw r2, #639 ; 0x27f
800f20c: 492c ldr r1, [pc, #176] ; (800f2c0 <mem_free+0x10c>)
800f20e: 4829 ldr r0, [pc, #164] ; (800f2b4 <mem_free+0x100>)
800f210: f00b ff00 bl 801b014 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f214: f00b fe9a bl 801af4c <sys_arch_protect>
800f218: 6138 str r0, [r7, #16]
800f21a: 6938 ldr r0, [r7, #16]
800f21c: f00b fea4 bl 801af68 <sys_arch_unprotect>
return;
800f220: e041 b.n 800f2a6 <mem_free+0xf2>
}
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f222: 4828 ldr r0, [pc, #160] ; (800f2c4 <mem_free+0x110>)
800f224: f00b fe50 bl 801aec8 <sys_mutex_lock>
/* mem has to be in a used state */
if (!mem->used) {
800f228: 69fb ldr r3, [r7, #28]
800f22a: 791b ldrb r3, [r3, #4]
800f22c: 2b00 cmp r3, #0
800f22e: d110 bne.n 800f252 <mem_free+0x9e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
800f230: 4b1e ldr r3, [pc, #120] ; (800f2ac <mem_free+0xf8>)
800f232: f44f 7223 mov.w r2, #652 ; 0x28c
800f236: 4924 ldr r1, [pc, #144] ; (800f2c8 <mem_free+0x114>)
800f238: 481e ldr r0, [pc, #120] ; (800f2b4 <mem_free+0x100>)
800f23a: f00b feeb bl 801b014 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f23e: 4821 ldr r0, [pc, #132] ; (800f2c4 <mem_free+0x110>)
800f240: f00b fe51 bl 801aee6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f244: f00b fe82 bl 801af4c <sys_arch_protect>
800f248: 6178 str r0, [r7, #20]
800f24a: 6978 ldr r0, [r7, #20]
800f24c: f00b fe8c bl 801af68 <sys_arch_unprotect>
return;
800f250: e029 b.n 800f2a6 <mem_free+0xf2>
}
if (!mem_link_valid(mem)) {
800f252: 69f8 ldr r0, [r7, #28]
800f254: f7ff ff72 bl 800f13c <mem_link_valid>
800f258: 4603 mov r3, r0
800f25a: 2b00 cmp r3, #0
800f25c: d110 bne.n 800f280 <mem_free+0xcc>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
800f25e: 4b13 ldr r3, [pc, #76] ; (800f2ac <mem_free+0xf8>)
800f260: f240 2295 movw r2, #661 ; 0x295
800f264: 4919 ldr r1, [pc, #100] ; (800f2cc <mem_free+0x118>)
800f266: 4813 ldr r0, [pc, #76] ; (800f2b4 <mem_free+0x100>)
800f268: f00b fed4 bl 801b014 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f26c: 4815 ldr r0, [pc, #84] ; (800f2c4 <mem_free+0x110>)
800f26e: f00b fe3a bl 801aee6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f272: f00b fe6b bl 801af4c <sys_arch_protect>
800f276: 61b8 str r0, [r7, #24]
800f278: 69b8 ldr r0, [r7, #24]
800f27a: f00b fe75 bl 801af68 <sys_arch_unprotect>
return;
800f27e: e012 b.n 800f2a6 <mem_free+0xf2>
}
/* mem is now unused. */
mem->used = 0;
800f280: 69fb ldr r3, [r7, #28]
800f282: 2200 movs r2, #0
800f284: 711a strb r2, [r3, #4]
if (mem < lfree) {
800f286: 4b12 ldr r3, [pc, #72] ; (800f2d0 <mem_free+0x11c>)
800f288: 681b ldr r3, [r3, #0]
800f28a: 69fa ldr r2, [r7, #28]
800f28c: 429a cmp r2, r3
800f28e: d202 bcs.n 800f296 <mem_free+0xe2>
/* the newly freed struct is now the lowest */
lfree = mem;
800f290: 4a0f ldr r2, [pc, #60] ; (800f2d0 <mem_free+0x11c>)
800f292: 69fb ldr r3, [r7, #28]
800f294: 6013 str r3, [r2, #0]
}
MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
/* finally, see if prev or next are free also */
plug_holes(mem);
800f296: 69f8 ldr r0, [r7, #28]
800f298: f7ff fe5c bl 800ef54 <plug_holes>
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f29c: 4809 ldr r0, [pc, #36] ; (800f2c4 <mem_free+0x110>)
800f29e: f00b fe22 bl 801aee6 <sys_mutex_unlock>
800f2a2: e000 b.n 800f2a6 <mem_free+0xf2>
return;
800f2a4: bf00 nop
}
800f2a6: 3720 adds r7, #32
800f2a8: 46bd mov sp, r7
800f2aa: bd80 pop {r7, pc}
800f2ac: 0801c0b4 .word 0x0801c0b4
800f2b0: 0801c1a4 .word 0x0801c1a4
800f2b4: 0801c0fc .word 0x0801c0fc
800f2b8: 200086e4 .word 0x200086e4
800f2bc: 200086e8 .word 0x200086e8
800f2c0: 0801c1c8 .word 0x0801c1c8
800f2c4: 200086ec .word 0x200086ec
800f2c8: 0801c1e4 .word 0x0801c1e4
800f2cc: 0801c20c .word 0x0801c20c
800f2d0: 200086f0 .word 0x200086f0
0800f2d4 <mem_trim>:
* or NULL if newsize is > old size, in which case rmem is NOT touched
* or freed!
*/
void *
mem_trim(void *rmem, mem_size_t new_size)
{
800f2d4: b580 push {r7, lr}
800f2d6: b088 sub sp, #32
800f2d8: af00 add r7, sp, #0
800f2da: 6078 str r0, [r7, #4]
800f2dc: 460b mov r3, r1
800f2de: 807b strh r3, [r7, #2]
/* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
LWIP_MEM_FREE_DECL_PROTECT();
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
800f2e0: 887b ldrh r3, [r7, #2]
800f2e2: 3303 adds r3, #3
800f2e4: b29b uxth r3, r3
800f2e6: f023 0303 bic.w r3, r3, #3
800f2ea: 83fb strh r3, [r7, #30]
if (newsize < MIN_SIZE_ALIGNED) {
800f2ec: 8bfb ldrh r3, [r7, #30]
800f2ee: 2b0b cmp r3, #11
800f2f0: d801 bhi.n 800f2f6 <mem_trim+0x22>
/* every data block must be at least MIN_SIZE_ALIGNED long */
newsize = MIN_SIZE_ALIGNED;
800f2f2: 230c movs r3, #12
800f2f4: 83fb strh r3, [r7, #30]
}
#if MEM_OVERFLOW_CHECK
newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
800f2f6: 8bfb ldrh r3, [r7, #30]
800f2f8: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f2fc: d803 bhi.n 800f306 <mem_trim+0x32>
800f2fe: 8bfa ldrh r2, [r7, #30]
800f300: 887b ldrh r3, [r7, #2]
800f302: 429a cmp r2, r3
800f304: d201 bcs.n 800f30a <mem_trim+0x36>
return NULL;
800f306: 2300 movs r3, #0
800f308: e0d8 b.n 800f4bc <mem_trim+0x1e8>
}
LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
800f30a: 4b6e ldr r3, [pc, #440] ; (800f4c4 <mem_trim+0x1f0>)
800f30c: 681b ldr r3, [r3, #0]
800f30e: 687a ldr r2, [r7, #4]
800f310: 429a cmp r2, r3
800f312: d304 bcc.n 800f31e <mem_trim+0x4a>
800f314: 4b6c ldr r3, [pc, #432] ; (800f4c8 <mem_trim+0x1f4>)
800f316: 681b ldr r3, [r3, #0]
800f318: 687a ldr r2, [r7, #4]
800f31a: 429a cmp r2, r3
800f31c: d306 bcc.n 800f32c <mem_trim+0x58>
800f31e: 4b6b ldr r3, [pc, #428] ; (800f4cc <mem_trim+0x1f8>)
800f320: f240 22d2 movw r2, #722 ; 0x2d2
800f324: 496a ldr r1, [pc, #424] ; (800f4d0 <mem_trim+0x1fc>)
800f326: 486b ldr r0, [pc, #428] ; (800f4d4 <mem_trim+0x200>)
800f328: f00b fe74 bl 801b014 <iprintf>
(u8_t *)rmem < (u8_t *)ram_end);
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
800f32c: 4b65 ldr r3, [pc, #404] ; (800f4c4 <mem_trim+0x1f0>)
800f32e: 681b ldr r3, [r3, #0]
800f330: 687a ldr r2, [r7, #4]
800f332: 429a cmp r2, r3
800f334: d304 bcc.n 800f340 <mem_trim+0x6c>
800f336: 4b64 ldr r3, [pc, #400] ; (800f4c8 <mem_trim+0x1f4>)
800f338: 681b ldr r3, [r3, #0]
800f33a: 687a ldr r2, [r7, #4]
800f33c: 429a cmp r2, r3
800f33e: d307 bcc.n 800f350 <mem_trim+0x7c>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f340: f00b fe04 bl 801af4c <sys_arch_protect>
800f344: 60b8 str r0, [r7, #8]
800f346: 68b8 ldr r0, [r7, #8]
800f348: f00b fe0e bl 801af68 <sys_arch_unprotect>
return rmem;
800f34c: 687b ldr r3, [r7, #4]
800f34e: e0b5 b.n 800f4bc <mem_trim+0x1e8>
}
/* Get the corresponding struct mem ... */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f350: 687b ldr r3, [r7, #4]
800f352: 3b08 subs r3, #8
800f354: 61bb str r3, [r7, #24]
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* ... and its offset pointer */
ptr = mem_to_ptr(mem);
800f356: 69b8 ldr r0, [r7, #24]
800f358: f7ff fdea bl 800ef30 <mem_to_ptr>
800f35c: 4603 mov r3, r0
800f35e: 82fb strh r3, [r7, #22]
size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
800f360: 69bb ldr r3, [r7, #24]
800f362: 881a ldrh r2, [r3, #0]
800f364: 8afb ldrh r3, [r7, #22]
800f366: 1ad3 subs r3, r2, r3
800f368: b29b uxth r3, r3
800f36a: 3b08 subs r3, #8
800f36c: 82bb strh r3, [r7, #20]
LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
800f36e: 8bfa ldrh r2, [r7, #30]
800f370: 8abb ldrh r3, [r7, #20]
800f372: 429a cmp r2, r3
800f374: d906 bls.n 800f384 <mem_trim+0xb0>
800f376: 4b55 ldr r3, [pc, #340] ; (800f4cc <mem_trim+0x1f8>)
800f378: f44f 7239 mov.w r2, #740 ; 0x2e4
800f37c: 4956 ldr r1, [pc, #344] ; (800f4d8 <mem_trim+0x204>)
800f37e: 4855 ldr r0, [pc, #340] ; (800f4d4 <mem_trim+0x200>)
800f380: f00b fe48 bl 801b014 <iprintf>
if (newsize > size) {
800f384: 8bfa ldrh r2, [r7, #30]
800f386: 8abb ldrh r3, [r7, #20]
800f388: 429a cmp r2, r3
800f38a: d901 bls.n 800f390 <mem_trim+0xbc>
/* not supported */
return NULL;
800f38c: 2300 movs r3, #0
800f38e: e095 b.n 800f4bc <mem_trim+0x1e8>
}
if (newsize == size) {
800f390: 8bfa ldrh r2, [r7, #30]
800f392: 8abb ldrh r3, [r7, #20]
800f394: 429a cmp r2, r3
800f396: d101 bne.n 800f39c <mem_trim+0xc8>
/* No change in size, simply return */
return rmem;
800f398: 687b ldr r3, [r7, #4]
800f39a: e08f b.n 800f4bc <mem_trim+0x1e8>
}
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f39c: 484f ldr r0, [pc, #316] ; (800f4dc <mem_trim+0x208>)
800f39e: f00b fd93 bl 801aec8 <sys_mutex_lock>
mem2 = ptr_to_mem(mem->next);
800f3a2: 69bb ldr r3, [r7, #24]
800f3a4: 881b ldrh r3, [r3, #0]
800f3a6: 4618 mov r0, r3
800f3a8: f7ff fdb0 bl 800ef0c <ptr_to_mem>
800f3ac: 6138 str r0, [r7, #16]
if (mem2->used == 0) {
800f3ae: 693b ldr r3, [r7, #16]
800f3b0: 791b ldrb r3, [r3, #4]
800f3b2: 2b00 cmp r3, #0
800f3b4: d13f bne.n 800f436 <mem_trim+0x162>
/* The next struct is unused, we can simply move it at little */
mem_size_t next;
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f3b6: 69bb ldr r3, [r7, #24]
800f3b8: 881b ldrh r3, [r3, #0]
800f3ba: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f3be: d106 bne.n 800f3ce <mem_trim+0xfa>
800f3c0: 4b42 ldr r3, [pc, #264] ; (800f4cc <mem_trim+0x1f8>)
800f3c2: f240 22f5 movw r2, #757 ; 0x2f5
800f3c6: 4946 ldr r1, [pc, #280] ; (800f4e0 <mem_trim+0x20c>)
800f3c8: 4842 ldr r0, [pc, #264] ; (800f4d4 <mem_trim+0x200>)
800f3ca: f00b fe23 bl 801b014 <iprintf>
/* remember the old next pointer */
next = mem2->next;
800f3ce: 693b ldr r3, [r7, #16]
800f3d0: 881b ldrh r3, [r3, #0]
800f3d2: 81bb strh r3, [r7, #12]
/* create new struct mem which is moved directly after the shrinked mem */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f3d4: 8afa ldrh r2, [r7, #22]
800f3d6: 8bfb ldrh r3, [r7, #30]
800f3d8: 4413 add r3, r2
800f3da: b29b uxth r3, r3
800f3dc: 3308 adds r3, #8
800f3de: 81fb strh r3, [r7, #14]
if (lfree == mem2) {
800f3e0: 4b40 ldr r3, [pc, #256] ; (800f4e4 <mem_trim+0x210>)
800f3e2: 681b ldr r3, [r3, #0]
800f3e4: 693a ldr r2, [r7, #16]
800f3e6: 429a cmp r2, r3
800f3e8: d106 bne.n 800f3f8 <mem_trim+0x124>
lfree = ptr_to_mem(ptr2);
800f3ea: 89fb ldrh r3, [r7, #14]
800f3ec: 4618 mov r0, r3
800f3ee: f7ff fd8d bl 800ef0c <ptr_to_mem>
800f3f2: 4602 mov r2, r0
800f3f4: 4b3b ldr r3, [pc, #236] ; (800f4e4 <mem_trim+0x210>)
800f3f6: 601a str r2, [r3, #0]
}
mem2 = ptr_to_mem(ptr2);
800f3f8: 89fb ldrh r3, [r7, #14]
800f3fa: 4618 mov r0, r3
800f3fc: f7ff fd86 bl 800ef0c <ptr_to_mem>
800f400: 6138 str r0, [r7, #16]
mem2->used = 0;
800f402: 693b ldr r3, [r7, #16]
800f404: 2200 movs r2, #0
800f406: 711a strb r2, [r3, #4]
/* restore the next pointer */
mem2->next = next;
800f408: 693b ldr r3, [r7, #16]
800f40a: 89ba ldrh r2, [r7, #12]
800f40c: 801a strh r2, [r3, #0]
/* link it back to mem */
mem2->prev = ptr;
800f40e: 693b ldr r3, [r7, #16]
800f410: 8afa ldrh r2, [r7, #22]
800f412: 805a strh r2, [r3, #2]
/* link mem to it */
mem->next = ptr2;
800f414: 69bb ldr r3, [r7, #24]
800f416: 89fa ldrh r2, [r7, #14]
800f418: 801a strh r2, [r3, #0]
/* last thing to restore linked list: as we have moved mem2,
* let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
* the end of the heap */
if (mem2->next != MEM_SIZE_ALIGNED) {
800f41a: 693b ldr r3, [r7, #16]
800f41c: 881b ldrh r3, [r3, #0]
800f41e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f422: d047 beq.n 800f4b4 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f424: 693b ldr r3, [r7, #16]
800f426: 881b ldrh r3, [r3, #0]
800f428: 4618 mov r0, r3
800f42a: f7ff fd6f bl 800ef0c <ptr_to_mem>
800f42e: 4602 mov r2, r0
800f430: 89fb ldrh r3, [r7, #14]
800f432: 8053 strh r3, [r2, #2]
800f434: e03e b.n 800f4b4 <mem_trim+0x1e0>
}
MEM_STATS_DEC_USED(used, (size - newsize));
/* no need to plug holes, we've already done that */
} else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
800f436: 8bfb ldrh r3, [r7, #30]
800f438: f103 0214 add.w r2, r3, #20
800f43c: 8abb ldrh r3, [r7, #20]
800f43e: 429a cmp r2, r3
800f440: d838 bhi.n 800f4b4 <mem_trim+0x1e0>
* Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
* ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f442: 8afa ldrh r2, [r7, #22]
800f444: 8bfb ldrh r3, [r7, #30]
800f446: 4413 add r3, r2
800f448: b29b uxth r3, r3
800f44a: 3308 adds r3, #8
800f44c: 81fb strh r3, [r7, #14]
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f44e: 69bb ldr r3, [r7, #24]
800f450: 881b ldrh r3, [r3, #0]
800f452: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f456: d106 bne.n 800f466 <mem_trim+0x192>
800f458: 4b1c ldr r3, [pc, #112] ; (800f4cc <mem_trim+0x1f8>)
800f45a: f240 3216 movw r2, #790 ; 0x316
800f45e: 4920 ldr r1, [pc, #128] ; (800f4e0 <mem_trim+0x20c>)
800f460: 481c ldr r0, [pc, #112] ; (800f4d4 <mem_trim+0x200>)
800f462: f00b fdd7 bl 801b014 <iprintf>
mem2 = ptr_to_mem(ptr2);
800f466: 89fb ldrh r3, [r7, #14]
800f468: 4618 mov r0, r3
800f46a: f7ff fd4f bl 800ef0c <ptr_to_mem>
800f46e: 6138 str r0, [r7, #16]
if (mem2 < lfree) {
800f470: 4b1c ldr r3, [pc, #112] ; (800f4e4 <mem_trim+0x210>)
800f472: 681b ldr r3, [r3, #0]
800f474: 693a ldr r2, [r7, #16]
800f476: 429a cmp r2, r3
800f478: d202 bcs.n 800f480 <mem_trim+0x1ac>
lfree = mem2;
800f47a: 4a1a ldr r2, [pc, #104] ; (800f4e4 <mem_trim+0x210>)
800f47c: 693b ldr r3, [r7, #16]
800f47e: 6013 str r3, [r2, #0]
}
mem2->used = 0;
800f480: 693b ldr r3, [r7, #16]
800f482: 2200 movs r2, #0
800f484: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f486: 69bb ldr r3, [r7, #24]
800f488: 881a ldrh r2, [r3, #0]
800f48a: 693b ldr r3, [r7, #16]
800f48c: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f48e: 693b ldr r3, [r7, #16]
800f490: 8afa ldrh r2, [r7, #22]
800f492: 805a strh r2, [r3, #2]
mem->next = ptr2;
800f494: 69bb ldr r3, [r7, #24]
800f496: 89fa ldrh r2, [r7, #14]
800f498: 801a strh r2, [r3, #0]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f49a: 693b ldr r3, [r7, #16]
800f49c: 881b ldrh r3, [r3, #0]
800f49e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f4a2: d007 beq.n 800f4b4 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f4a4: 693b ldr r3, [r7, #16]
800f4a6: 881b ldrh r3, [r3, #0]
800f4a8: 4618 mov r0, r3
800f4aa: f7ff fd2f bl 800ef0c <ptr_to_mem>
800f4ae: 4602 mov r2, r0
800f4b0: 89fb ldrh r3, [r7, #14]
800f4b2: 8053 strh r3, [r2, #2]
#endif
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f4b4: 4809 ldr r0, [pc, #36] ; (800f4dc <mem_trim+0x208>)
800f4b6: f00b fd16 bl 801aee6 <sys_mutex_unlock>
return rmem;
800f4ba: 687b ldr r3, [r7, #4]
}
800f4bc: 4618 mov r0, r3
800f4be: 3720 adds r7, #32
800f4c0: 46bd mov sp, r7
800f4c2: bd80 pop {r7, pc}
800f4c4: 200086e4 .word 0x200086e4
800f4c8: 200086e8 .word 0x200086e8
800f4cc: 0801c0b4 .word 0x0801c0b4
800f4d0: 0801c240 .word 0x0801c240
800f4d4: 0801c0fc .word 0x0801c0fc
800f4d8: 0801c258 .word 0x0801c258
800f4dc: 200086ec .word 0x200086ec
800f4e0: 0801c278 .word 0x0801c278
800f4e4: 200086f0 .word 0x200086f0
0800f4e8 <mem_malloc>:
*
* Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
*/
void *
mem_malloc(mem_size_t size_in)
{
800f4e8: b580 push {r7, lr}
800f4ea: b088 sub sp, #32
800f4ec: af00 add r7, sp, #0
800f4ee: 4603 mov r3, r0
800f4f0: 80fb strh r3, [r7, #6]
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
u8_t local_mem_free_count = 0;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_ALLOC_DECL_PROTECT();
if (size_in == 0) {
800f4f2: 88fb ldrh r3, [r7, #6]
800f4f4: 2b00 cmp r3, #0
800f4f6: d101 bne.n 800f4fc <mem_malloc+0x14>
return NULL;
800f4f8: 2300 movs r3, #0
800f4fa: e0e2 b.n 800f6c2 <mem_malloc+0x1da>
}
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
800f4fc: 88fb ldrh r3, [r7, #6]
800f4fe: 3303 adds r3, #3
800f500: b29b uxth r3, r3
800f502: f023 0303 bic.w r3, r3, #3
800f506: 83bb strh r3, [r7, #28]
if (size < MIN_SIZE_ALIGNED) {
800f508: 8bbb ldrh r3, [r7, #28]
800f50a: 2b0b cmp r3, #11
800f50c: d801 bhi.n 800f512 <mem_malloc+0x2a>
/* every data block must be at least MIN_SIZE_ALIGNED long */
size = MIN_SIZE_ALIGNED;
800f50e: 230c movs r3, #12
800f510: 83bb strh r3, [r7, #28]
}
#if MEM_OVERFLOW_CHECK
size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
800f512: 8bbb ldrh r3, [r7, #28]
800f514: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f518: d803 bhi.n 800f522 <mem_malloc+0x3a>
800f51a: 8bba ldrh r2, [r7, #28]
800f51c: 88fb ldrh r3, [r7, #6]
800f51e: 429a cmp r2, r3
800f520: d201 bcs.n 800f526 <mem_malloc+0x3e>
return NULL;
800f522: 2300 movs r3, #0
800f524: e0cd b.n 800f6c2 <mem_malloc+0x1da>
}
/* protect the heap from concurrent access */
sys_mutex_lock(&mem_mutex);
800f526: 4869 ldr r0, [pc, #420] ; (800f6cc <mem_malloc+0x1e4>)
800f528: f00b fcce bl 801aec8 <sys_mutex_lock>
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
/* Scan through the heap searching for a free block that is big enough,
* beginning with the lowest free block.
*/
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f52c: 4b68 ldr r3, [pc, #416] ; (800f6d0 <mem_malloc+0x1e8>)
800f52e: 681b ldr r3, [r3, #0]
800f530: 4618 mov r0, r3
800f532: f7ff fcfd bl 800ef30 <mem_to_ptr>
800f536: 4603 mov r3, r0
800f538: 83fb strh r3, [r7, #30]
800f53a: e0b7 b.n 800f6ac <mem_malloc+0x1c4>
ptr = ptr_to_mem(ptr)->next) {
mem = ptr_to_mem(ptr);
800f53c: 8bfb ldrh r3, [r7, #30]
800f53e: 4618 mov r0, r3
800f540: f7ff fce4 bl 800ef0c <ptr_to_mem>
800f544: 6178 str r0, [r7, #20]
local_mem_free_count = 1;
break;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if ((!mem->used) &&
800f546: 697b ldr r3, [r7, #20]
800f548: 791b ldrb r3, [r3, #4]
800f54a: 2b00 cmp r3, #0
800f54c: f040 80a7 bne.w 800f69e <mem_malloc+0x1b6>
(mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
800f550: 697b ldr r3, [r7, #20]
800f552: 881b ldrh r3, [r3, #0]
800f554: 461a mov r2, r3
800f556: 8bfb ldrh r3, [r7, #30]
800f558: 1ad3 subs r3, r2, r3
800f55a: f1a3 0208 sub.w r2, r3, #8
800f55e: 8bbb ldrh r3, [r7, #28]
if ((!mem->used) &&
800f560: 429a cmp r2, r3
800f562: f0c0 809c bcc.w 800f69e <mem_malloc+0x1b6>
/* mem is not used and at least perfect fit is possible:
* mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
800f566: 697b ldr r3, [r7, #20]
800f568: 881b ldrh r3, [r3, #0]
800f56a: 461a mov r2, r3
800f56c: 8bfb ldrh r3, [r7, #30]
800f56e: 1ad3 subs r3, r2, r3
800f570: f1a3 0208 sub.w r2, r3, #8
800f574: 8bbb ldrh r3, [r7, #28]
800f576: 3314 adds r3, #20
800f578: 429a cmp r2, r3
800f57a: d333 bcc.n 800f5e4 <mem_malloc+0xfc>
* struct mem would fit in but no data between mem2 and mem2->next
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory
*/
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
800f57c: 8bfa ldrh r2, [r7, #30]
800f57e: 8bbb ldrh r3, [r7, #28]
800f580: 4413 add r3, r2
800f582: b29b uxth r3, r3
800f584: 3308 adds r3, #8
800f586: 827b strh r3, [r7, #18]
LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
800f588: 8a7b ldrh r3, [r7, #18]
800f58a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f58e: d106 bne.n 800f59e <mem_malloc+0xb6>
800f590: 4b50 ldr r3, [pc, #320] ; (800f6d4 <mem_malloc+0x1ec>)
800f592: f240 3287 movw r2, #903 ; 0x387
800f596: 4950 ldr r1, [pc, #320] ; (800f6d8 <mem_malloc+0x1f0>)
800f598: 4850 ldr r0, [pc, #320] ; (800f6dc <mem_malloc+0x1f4>)
800f59a: f00b fd3b bl 801b014 <iprintf>
/* create mem2 struct */
mem2 = ptr_to_mem(ptr2);
800f59e: 8a7b ldrh r3, [r7, #18]
800f5a0: 4618 mov r0, r3
800f5a2: f7ff fcb3 bl 800ef0c <ptr_to_mem>
800f5a6: 60f8 str r0, [r7, #12]
mem2->used = 0;
800f5a8: 68fb ldr r3, [r7, #12]
800f5aa: 2200 movs r2, #0
800f5ac: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f5ae: 697b ldr r3, [r7, #20]
800f5b0: 881a ldrh r2, [r3, #0]
800f5b2: 68fb ldr r3, [r7, #12]
800f5b4: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f5b6: 68fb ldr r3, [r7, #12]
800f5b8: 8bfa ldrh r2, [r7, #30]
800f5ba: 805a strh r2, [r3, #2]
/* and insert it between mem and mem->next */
mem->next = ptr2;
800f5bc: 697b ldr r3, [r7, #20]
800f5be: 8a7a ldrh r2, [r7, #18]
800f5c0: 801a strh r2, [r3, #0]
mem->used = 1;
800f5c2: 697b ldr r3, [r7, #20]
800f5c4: 2201 movs r2, #1
800f5c6: 711a strb r2, [r3, #4]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f5c8: 68fb ldr r3, [r7, #12]
800f5ca: 881b ldrh r3, [r3, #0]
800f5cc: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f5d0: d00b beq.n 800f5ea <mem_malloc+0x102>
ptr_to_mem(mem2->next)->prev = ptr2;
800f5d2: 68fb ldr r3, [r7, #12]
800f5d4: 881b ldrh r3, [r3, #0]
800f5d6: 4618 mov r0, r3
800f5d8: f7ff fc98 bl 800ef0c <ptr_to_mem>
800f5dc: 4602 mov r2, r0
800f5de: 8a7b ldrh r3, [r7, #18]
800f5e0: 8053 strh r3, [r2, #2]
800f5e2: e002 b.n 800f5ea <mem_malloc+0x102>
* take care of this).
* -> near fit or exact fit: do not split, no mem2 creation
* also can't move mem->next directly behind mem, since mem->next
* will always be used at this point!
*/
mem->used = 1;
800f5e4: 697b ldr r3, [r7, #20]
800f5e6: 2201 movs r2, #1
800f5e8: 711a strb r2, [r3, #4]
MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
}
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_malloc_adjust_lfree:
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if (mem == lfree) {
800f5ea: 4b39 ldr r3, [pc, #228] ; (800f6d0 <mem_malloc+0x1e8>)
800f5ec: 681b ldr r3, [r3, #0]
800f5ee: 697a ldr r2, [r7, #20]
800f5f0: 429a cmp r2, r3
800f5f2: d127 bne.n 800f644 <mem_malloc+0x15c>
struct mem *cur = lfree;
800f5f4: 4b36 ldr r3, [pc, #216] ; (800f6d0 <mem_malloc+0x1e8>)
800f5f6: 681b ldr r3, [r3, #0]
800f5f8: 61bb str r3, [r7, #24]
/* Find next free block after mem and update lowest free pointer */
while (cur->used && cur != ram_end) {
800f5fa: e005 b.n 800f608 <mem_malloc+0x120>
/* If mem_free or mem_trim have run, we have to restart since they
could have altered our current struct mem or lfree. */
goto mem_malloc_adjust_lfree;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
cur = ptr_to_mem(cur->next);
800f5fc: 69bb ldr r3, [r7, #24]
800f5fe: 881b ldrh r3, [r3, #0]
800f600: 4618 mov r0, r3
800f602: f7ff fc83 bl 800ef0c <ptr_to_mem>
800f606: 61b8 str r0, [r7, #24]
while (cur->used && cur != ram_end) {
800f608: 69bb ldr r3, [r7, #24]
800f60a: 791b ldrb r3, [r3, #4]
800f60c: 2b00 cmp r3, #0
800f60e: d004 beq.n 800f61a <mem_malloc+0x132>
800f610: 4b33 ldr r3, [pc, #204] ; (800f6e0 <mem_malloc+0x1f8>)
800f612: 681b ldr r3, [r3, #0]
800f614: 69ba ldr r2, [r7, #24]
800f616: 429a cmp r2, r3
800f618: d1f0 bne.n 800f5fc <mem_malloc+0x114>
}
lfree = cur;
800f61a: 4a2d ldr r2, [pc, #180] ; (800f6d0 <mem_malloc+0x1e8>)
800f61c: 69bb ldr r3, [r7, #24]
800f61e: 6013 str r3, [r2, #0]
LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
800f620: 4b2b ldr r3, [pc, #172] ; (800f6d0 <mem_malloc+0x1e8>)
800f622: 681a ldr r2, [r3, #0]
800f624: 4b2e ldr r3, [pc, #184] ; (800f6e0 <mem_malloc+0x1f8>)
800f626: 681b ldr r3, [r3, #0]
800f628: 429a cmp r2, r3
800f62a: d00b beq.n 800f644 <mem_malloc+0x15c>
800f62c: 4b28 ldr r3, [pc, #160] ; (800f6d0 <mem_malloc+0x1e8>)
800f62e: 681b ldr r3, [r3, #0]
800f630: 791b ldrb r3, [r3, #4]
800f632: 2b00 cmp r3, #0
800f634: d006 beq.n 800f644 <mem_malloc+0x15c>
800f636: 4b27 ldr r3, [pc, #156] ; (800f6d4 <mem_malloc+0x1ec>)
800f638: f240 32b5 movw r2, #949 ; 0x3b5
800f63c: 4929 ldr r1, [pc, #164] ; (800f6e4 <mem_malloc+0x1fc>)
800f63e: 4827 ldr r0, [pc, #156] ; (800f6dc <mem_malloc+0x1f4>)
800f640: f00b fce8 bl 801b014 <iprintf>
}
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f644: 4821 ldr r0, [pc, #132] ; (800f6cc <mem_malloc+0x1e4>)
800f646: f00b fc4e bl 801aee6 <sys_mutex_unlock>
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
800f64a: 8bba ldrh r2, [r7, #28]
800f64c: 697b ldr r3, [r7, #20]
800f64e: 4413 add r3, r2
800f650: 3308 adds r3, #8
800f652: 4a23 ldr r2, [pc, #140] ; (800f6e0 <mem_malloc+0x1f8>)
800f654: 6812 ldr r2, [r2, #0]
800f656: 4293 cmp r3, r2
800f658: d906 bls.n 800f668 <mem_malloc+0x180>
800f65a: 4b1e ldr r3, [pc, #120] ; (800f6d4 <mem_malloc+0x1ec>)
800f65c: f240 32ba movw r2, #954 ; 0x3ba
800f660: 4921 ldr r1, [pc, #132] ; (800f6e8 <mem_malloc+0x200>)
800f662: 481e ldr r0, [pc, #120] ; (800f6dc <mem_malloc+0x1f4>)
800f664: f00b fcd6 bl 801b014 <iprintf>
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
800f668: 697b ldr r3, [r7, #20]
800f66a: f003 0303 and.w r3, r3, #3
800f66e: 2b00 cmp r3, #0
800f670: d006 beq.n 800f680 <mem_malloc+0x198>
800f672: 4b18 ldr r3, [pc, #96] ; (800f6d4 <mem_malloc+0x1ec>)
800f674: f44f 726f mov.w r2, #956 ; 0x3bc
800f678: 491c ldr r1, [pc, #112] ; (800f6ec <mem_malloc+0x204>)
800f67a: 4818 ldr r0, [pc, #96] ; (800f6dc <mem_malloc+0x1f4>)
800f67c: f00b fcca bl 801b014 <iprintf>
((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
LWIP_ASSERT("mem_malloc: sanity check alignment",
800f680: 697b ldr r3, [r7, #20]
800f682: f003 0303 and.w r3, r3, #3
800f686: 2b00 cmp r3, #0
800f688: d006 beq.n 800f698 <mem_malloc+0x1b0>
800f68a: 4b12 ldr r3, [pc, #72] ; (800f6d4 <mem_malloc+0x1ec>)
800f68c: f240 32be movw r2, #958 ; 0x3be
800f690: 4917 ldr r1, [pc, #92] ; (800f6f0 <mem_malloc+0x208>)
800f692: 4812 ldr r0, [pc, #72] ; (800f6dc <mem_malloc+0x1f4>)
800f694: f00b fcbe bl 801b014 <iprintf>
#if MEM_OVERFLOW_CHECK
mem_overflow_init_element(mem, size_in);
#endif
MEM_SANITY();
return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
800f698: 697b ldr r3, [r7, #20]
800f69a: 3308 adds r3, #8
800f69c: e011 b.n 800f6c2 <mem_malloc+0x1da>
ptr = ptr_to_mem(ptr)->next) {
800f69e: 8bfb ldrh r3, [r7, #30]
800f6a0: 4618 mov r0, r3
800f6a2: f7ff fc33 bl 800ef0c <ptr_to_mem>
800f6a6: 4603 mov r3, r0
800f6a8: 881b ldrh r3, [r3, #0]
800f6aa: 83fb strh r3, [r7, #30]
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f6ac: 8bfa ldrh r2, [r7, #30]
800f6ae: 8bbb ldrh r3, [r7, #28]
800f6b0: f5c3 63c8 rsb r3, r3, #1600 ; 0x640
800f6b4: 429a cmp r2, r3
800f6b6: f4ff af41 bcc.w 800f53c <mem_malloc+0x54>
/* if we got interrupted by a mem_free, try again */
} while (local_mem_free_count != 0);
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
MEM_STATS_INC(err);
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f6ba: 4804 ldr r0, [pc, #16] ; (800f6cc <mem_malloc+0x1e4>)
800f6bc: f00b fc13 bl 801aee6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
return NULL;
800f6c0: 2300 movs r3, #0
}
800f6c2: 4618 mov r0, r3
800f6c4: 3720 adds r7, #32
800f6c6: 46bd mov sp, r7
800f6c8: bd80 pop {r7, pc}
800f6ca: bf00 nop
800f6cc: 200086ec .word 0x200086ec
800f6d0: 200086f0 .word 0x200086f0
800f6d4: 0801c0b4 .word 0x0801c0b4
800f6d8: 0801c278 .word 0x0801c278
800f6dc: 0801c0fc .word 0x0801c0fc
800f6e0: 200086e8 .word 0x200086e8
800f6e4: 0801c28c .word 0x0801c28c
800f6e8: 0801c2a8 .word 0x0801c2a8
800f6ec: 0801c2d8 .word 0x0801c2d8
800f6f0: 0801c308 .word 0x0801c308
0800f6f4 <memp_init_pool>:
*
* @param desc pool to initialize
*/
void
memp_init_pool(const struct memp_desc *desc)
{
800f6f4: b480 push {r7}
800f6f6: b085 sub sp, #20
800f6f8: af00 add r7, sp, #0
800f6fa: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(desc);
#else
int i;
struct memp *memp;
*desc->tab = NULL;
800f6fc: 687b ldr r3, [r7, #4]
800f6fe: 689b ldr r3, [r3, #8]
800f700: 2200 movs r2, #0
800f702: 601a str r2, [r3, #0]
memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
800f704: 687b ldr r3, [r7, #4]
800f706: 685b ldr r3, [r3, #4]
800f708: 3303 adds r3, #3
800f70a: f023 0303 bic.w r3, r3, #3
800f70e: 60bb str r3, [r7, #8]
+ MEM_SANITY_REGION_AFTER_ALIGNED
#endif
));
#endif
/* create a linked list of memp elements */
for (i = 0; i < desc->num; ++i) {
800f710: 2300 movs r3, #0
800f712: 60fb str r3, [r7, #12]
800f714: e011 b.n 800f73a <memp_init_pool+0x46>
memp->next = *desc->tab;
800f716: 687b ldr r3, [r7, #4]
800f718: 689b ldr r3, [r3, #8]
800f71a: 681a ldr r2, [r3, #0]
800f71c: 68bb ldr r3, [r7, #8]
800f71e: 601a str r2, [r3, #0]
*desc->tab = memp;
800f720: 687b ldr r3, [r7, #4]
800f722: 689b ldr r3, [r3, #8]
800f724: 68ba ldr r2, [r7, #8]
800f726: 601a str r2, [r3, #0]
#if MEMP_OVERFLOW_CHECK
memp_overflow_init_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
800f728: 687b ldr r3, [r7, #4]
800f72a: 881b ldrh r3, [r3, #0]
800f72c: 461a mov r2, r3
800f72e: 68bb ldr r3, [r7, #8]
800f730: 4413 add r3, r2
800f732: 60bb str r3, [r7, #8]
for (i = 0; i < desc->num; ++i) {
800f734: 68fb ldr r3, [r7, #12]
800f736: 3301 adds r3, #1
800f738: 60fb str r3, [r7, #12]
800f73a: 687b ldr r3, [r7, #4]
800f73c: 885b ldrh r3, [r3, #2]
800f73e: 461a mov r2, r3
800f740: 68fb ldr r3, [r7, #12]
800f742: 4293 cmp r3, r2
800f744: dbe7 blt.n 800f716 <memp_init_pool+0x22>
#endif /* !MEMP_MEM_MALLOC */
#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
desc->stats->name = desc->desc;
#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
}
800f746: bf00 nop
800f748: 3714 adds r7, #20
800f74a: 46bd mov sp, r7
800f74c: f85d 7b04 ldr.w r7, [sp], #4
800f750: 4770 bx lr
...
0800f754 <memp_init>:
*
* Carves out memp_memory into linked lists for each pool-type.
*/
void
memp_init(void)
{
800f754: b580 push {r7, lr}
800f756: b082 sub sp, #8
800f758: af00 add r7, sp, #0
u16_t i;
/* for every pool: */
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f75a: 2300 movs r3, #0
800f75c: 80fb strh r3, [r7, #6]
800f75e: e009 b.n 800f774 <memp_init+0x20>
memp_init_pool(memp_pools[i]);
800f760: 88fb ldrh r3, [r7, #6]
800f762: 4a08 ldr r2, [pc, #32] ; (800f784 <memp_init+0x30>)
800f764: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f768: 4618 mov r0, r3
800f76a: f7ff ffc3 bl 800f6f4 <memp_init_pool>
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f76e: 88fb ldrh r3, [r7, #6]
800f770: 3301 adds r3, #1
800f772: 80fb strh r3, [r7, #6]
800f774: 88fb ldrh r3, [r7, #6]
800f776: 2b0c cmp r3, #12
800f778: d9f2 bls.n 800f760 <memp_init+0xc>
#if MEMP_OVERFLOW_CHECK >= 2
/* check everything a first time to see if it worked */
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
}
800f77a: bf00 nop
800f77c: 3708 adds r7, #8
800f77e: 46bd mov sp, r7
800f780: bd80 pop {r7, pc}
800f782: bf00 nop
800f784: 08020de4 .word 0x08020de4
0800f788 <do_memp_malloc_pool>:
#if !MEMP_OVERFLOW_CHECK
do_memp_malloc_pool(const struct memp_desc *desc)
#else
do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
#endif
{
800f788: b580 push {r7, lr}
800f78a: b084 sub sp, #16
800f78c: af00 add r7, sp, #0
800f78e: 6078 str r0, [r7, #4]
#if MEMP_MEM_MALLOC
memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
SYS_ARCH_PROTECT(old_level);
#else /* MEMP_MEM_MALLOC */
SYS_ARCH_PROTECT(old_level);
800f790: f00b fbdc bl 801af4c <sys_arch_protect>
800f794: 60f8 str r0, [r7, #12]
memp = *desc->tab;
800f796: 687b ldr r3, [r7, #4]
800f798: 689b ldr r3, [r3, #8]
800f79a: 681b ldr r3, [r3, #0]
800f79c: 60bb str r3, [r7, #8]
#endif /* MEMP_MEM_MALLOC */
if (memp != NULL) {
800f79e: 68bb ldr r3, [r7, #8]
800f7a0: 2b00 cmp r3, #0
800f7a2: d015 beq.n 800f7d0 <do_memp_malloc_pool+0x48>
#if !MEMP_MEM_MALLOC
#if MEMP_OVERFLOW_CHECK == 1
memp_overflow_check_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
*desc->tab = memp->next;
800f7a4: 687b ldr r3, [r7, #4]
800f7a6: 689b ldr r3, [r3, #8]
800f7a8: 68ba ldr r2, [r7, #8]
800f7aa: 6812 ldr r2, [r2, #0]
800f7ac: 601a str r2, [r3, #0]
memp->line = line;
#if MEMP_MEM_MALLOC
memp_overflow_init_element(memp, desc);
#endif /* MEMP_MEM_MALLOC */
#endif /* MEMP_OVERFLOW_CHECK */
LWIP_ASSERT("memp_malloc: memp properly aligned",
800f7ae: 68bb ldr r3, [r7, #8]
800f7b0: f003 0303 and.w r3, r3, #3
800f7b4: 2b00 cmp r3, #0
800f7b6: d006 beq.n 800f7c6 <do_memp_malloc_pool+0x3e>
800f7b8: 4b09 ldr r3, [pc, #36] ; (800f7e0 <do_memp_malloc_pool+0x58>)
800f7ba: f240 1219 movw r2, #281 ; 0x119
800f7be: 4909 ldr r1, [pc, #36] ; (800f7e4 <do_memp_malloc_pool+0x5c>)
800f7c0: 4809 ldr r0, [pc, #36] ; (800f7e8 <do_memp_malloc_pool+0x60>)
800f7c2: f00b fc27 bl 801b014 <iprintf>
desc->stats->used++;
if (desc->stats->used > desc->stats->max) {
desc->stats->max = desc->stats->used;
}
#endif
SYS_ARCH_UNPROTECT(old_level);
800f7c6: 68f8 ldr r0, [r7, #12]
800f7c8: f00b fbce bl 801af68 <sys_arch_unprotect>
/* cast through u8_t* to get rid of alignment warnings */
return ((u8_t *)memp + MEMP_SIZE);
800f7cc: 68bb ldr r3, [r7, #8]
800f7ce: e003 b.n 800f7d8 <do_memp_malloc_pool+0x50>
} else {
#if MEMP_STATS
desc->stats->err++;
#endif
SYS_ARCH_UNPROTECT(old_level);
800f7d0: 68f8 ldr r0, [r7, #12]
800f7d2: f00b fbc9 bl 801af68 <sys_arch_unprotect>
LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
}
return NULL;
800f7d6: 2300 movs r3, #0
}
800f7d8: 4618 mov r0, r3
800f7da: 3710 adds r7, #16
800f7dc: 46bd mov sp, r7
800f7de: bd80 pop {r7, pc}
800f7e0: 0801c32c .word 0x0801c32c
800f7e4: 0801c35c .word 0x0801c35c
800f7e8: 0801c380 .word 0x0801c380
0800f7ec <memp_malloc>:
#if !MEMP_OVERFLOW_CHECK
memp_malloc(memp_t type)
#else
memp_malloc_fn(memp_t type, const char *file, const int line)
#endif
{
800f7ec: b580 push {r7, lr}
800f7ee: b084 sub sp, #16
800f7f0: af00 add r7, sp, #0
800f7f2: 4603 mov r3, r0
800f7f4: 71fb strb r3, [r7, #7]
void *memp;
LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
800f7f6: 79fb ldrb r3, [r7, #7]
800f7f8: 2b0c cmp r3, #12
800f7fa: d908 bls.n 800f80e <memp_malloc+0x22>
800f7fc: 4b0a ldr r3, [pc, #40] ; (800f828 <memp_malloc+0x3c>)
800f7fe: f240 1257 movw r2, #343 ; 0x157
800f802: 490a ldr r1, [pc, #40] ; (800f82c <memp_malloc+0x40>)
800f804: 480a ldr r0, [pc, #40] ; (800f830 <memp_malloc+0x44>)
800f806: f00b fc05 bl 801b014 <iprintf>
800f80a: 2300 movs r3, #0
800f80c: e008 b.n 800f820 <memp_malloc+0x34>
#if MEMP_OVERFLOW_CHECK >= 2
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
#if !MEMP_OVERFLOW_CHECK
memp = do_memp_malloc_pool(memp_pools[type]);
800f80e: 79fb ldrb r3, [r7, #7]
800f810: 4a08 ldr r2, [pc, #32] ; (800f834 <memp_malloc+0x48>)
800f812: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f816: 4618 mov r0, r3
800f818: f7ff ffb6 bl 800f788 <do_memp_malloc_pool>
800f81c: 60f8 str r0, [r7, #12]
#else
memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
#endif
return memp;
800f81e: 68fb ldr r3, [r7, #12]
}
800f820: 4618 mov r0, r3
800f822: 3710 adds r7, #16
800f824: 46bd mov sp, r7
800f826: bd80 pop {r7, pc}
800f828: 0801c32c .word 0x0801c32c
800f82c: 0801c3bc .word 0x0801c3bc
800f830: 0801c380 .word 0x0801c380
800f834: 08020de4 .word 0x08020de4
0800f838 <do_memp_free_pool>:
static void
do_memp_free_pool(const struct memp_desc *desc, void *mem)
{
800f838: b580 push {r7, lr}
800f83a: b084 sub sp, #16
800f83c: af00 add r7, sp, #0
800f83e: 6078 str r0, [r7, #4]
800f840: 6039 str r1, [r7, #0]
struct memp *memp;
SYS_ARCH_DECL_PROTECT(old_level);
LWIP_ASSERT("memp_free: mem properly aligned",
800f842: 683b ldr r3, [r7, #0]
800f844: f003 0303 and.w r3, r3, #3
800f848: 2b00 cmp r3, #0
800f84a: d006 beq.n 800f85a <do_memp_free_pool+0x22>
800f84c: 4b0d ldr r3, [pc, #52] ; (800f884 <do_memp_free_pool+0x4c>)
800f84e: f240 126d movw r2, #365 ; 0x16d
800f852: 490d ldr r1, [pc, #52] ; (800f888 <do_memp_free_pool+0x50>)
800f854: 480d ldr r0, [pc, #52] ; (800f88c <do_memp_free_pool+0x54>)
800f856: f00b fbdd bl 801b014 <iprintf>
((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
800f85a: 683b ldr r3, [r7, #0]
800f85c: 60fb str r3, [r7, #12]
SYS_ARCH_PROTECT(old_level);
800f85e: f00b fb75 bl 801af4c <sys_arch_protect>
800f862: 60b8 str r0, [r7, #8]
#if MEMP_MEM_MALLOC
LWIP_UNUSED_ARG(desc);
SYS_ARCH_UNPROTECT(old_level);
mem_free(memp);
#else /* MEMP_MEM_MALLOC */
memp->next = *desc->tab;
800f864: 687b ldr r3, [r7, #4]
800f866: 689b ldr r3, [r3, #8]
800f868: 681a ldr r2, [r3, #0]
800f86a: 68fb ldr r3, [r7, #12]
800f86c: 601a str r2, [r3, #0]
*desc->tab = memp;
800f86e: 687b ldr r3, [r7, #4]
800f870: 689b ldr r3, [r3, #8]
800f872: 68fa ldr r2, [r7, #12]
800f874: 601a str r2, [r3, #0]
#if MEMP_SANITY_CHECK
LWIP_ASSERT("memp sanity", memp_sanity(desc));
#endif /* MEMP_SANITY_CHECK */
SYS_ARCH_UNPROTECT(old_level);
800f876: 68b8 ldr r0, [r7, #8]
800f878: f00b fb76 bl 801af68 <sys_arch_unprotect>
#endif /* !MEMP_MEM_MALLOC */
}
800f87c: bf00 nop
800f87e: 3710 adds r7, #16
800f880: 46bd mov sp, r7
800f882: bd80 pop {r7, pc}
800f884: 0801c32c .word 0x0801c32c
800f888: 0801c3dc .word 0x0801c3dc
800f88c: 0801c380 .word 0x0801c380
0800f890 <memp_free>:
* @param type the pool where to put mem
* @param mem the memp element to free
*/
void
memp_free(memp_t type, void *mem)
{
800f890: b580 push {r7, lr}
800f892: b082 sub sp, #8
800f894: af00 add r7, sp, #0
800f896: 4603 mov r3, r0
800f898: 6039 str r1, [r7, #0]
800f89a: 71fb strb r3, [r7, #7]
#ifdef LWIP_HOOK_MEMP_AVAILABLE
struct memp *old_first;
#endif
LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
800f89c: 79fb ldrb r3, [r7, #7]
800f89e: 2b0c cmp r3, #12
800f8a0: d907 bls.n 800f8b2 <memp_free+0x22>
800f8a2: 4b0c ldr r3, [pc, #48] ; (800f8d4 <memp_free+0x44>)
800f8a4: f44f 72d5 mov.w r2, #426 ; 0x1aa
800f8a8: 490b ldr r1, [pc, #44] ; (800f8d8 <memp_free+0x48>)
800f8aa: 480c ldr r0, [pc, #48] ; (800f8dc <memp_free+0x4c>)
800f8ac: f00b fbb2 bl 801b014 <iprintf>
800f8b0: e00c b.n 800f8cc <memp_free+0x3c>
if (mem == NULL) {
800f8b2: 683b ldr r3, [r7, #0]
800f8b4: 2b00 cmp r3, #0
800f8b6: d008 beq.n 800f8ca <memp_free+0x3a>
#ifdef LWIP_HOOK_MEMP_AVAILABLE
old_first = *memp_pools[type]->tab;
#endif
do_memp_free_pool(memp_pools[type], mem);
800f8b8: 79fb ldrb r3, [r7, #7]
800f8ba: 4a09 ldr r2, [pc, #36] ; (800f8e0 <memp_free+0x50>)
800f8bc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f8c0: 6839 ldr r1, [r7, #0]
800f8c2: 4618 mov r0, r3
800f8c4: f7ff ffb8 bl 800f838 <do_memp_free_pool>
800f8c8: e000 b.n 800f8cc <memp_free+0x3c>
return;
800f8ca: bf00 nop
#ifdef LWIP_HOOK_MEMP_AVAILABLE
if (old_first == NULL) {
LWIP_HOOK_MEMP_AVAILABLE(type);
}
#endif
}
800f8cc: 3708 adds r7, #8
800f8ce: 46bd mov sp, r7
800f8d0: bd80 pop {r7, pc}
800f8d2: bf00 nop
800f8d4: 0801c32c .word 0x0801c32c
800f8d8: 0801c3fc .word 0x0801c3fc
800f8dc: 0801c380 .word 0x0801c380
800f8e0: 08020de4 .word 0x08020de4
0800f8e4 <netif_init>:
}
#endif /* LWIP_HAVE_LOOPIF */
void
netif_init(void)
{
800f8e4: b480 push {r7}
800f8e6: af00 add r7, sp, #0
netif_set_link_up(&loop_netif);
netif_set_up(&loop_netif);
#endif /* LWIP_HAVE_LOOPIF */
}
800f8e8: bf00 nop
800f8ea: 46bd mov sp, r7
800f8ec: f85d 7b04 ldr.w r7, [sp], #4
800f8f0: 4770 bx lr
...
0800f8f4 <netif_add>:
netif_add(struct netif *netif,
#if LWIP_IPV4
const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
#endif /* LWIP_IPV4 */
void *state, netif_init_fn init, netif_input_fn input)
{
800f8f4: b580 push {r7, lr}
800f8f6: b086 sub sp, #24
800f8f8: af00 add r7, sp, #0
800f8fa: 60f8 str r0, [r7, #12]
800f8fc: 60b9 str r1, [r7, #8]
800f8fe: 607a str r2, [r7, #4]
800f900: 603b str r3, [r7, #0]
LWIP_ASSERT("single netif already set", 0);
return NULL;
}
#endif
LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
800f902: 68fb ldr r3, [r7, #12]
800f904: 2b00 cmp r3, #0
800f906: d108 bne.n 800f91a <netif_add+0x26>
800f908: 4b5b ldr r3, [pc, #364] ; (800fa78 <netif_add+0x184>)
800f90a: f240 1227 movw r2, #295 ; 0x127
800f90e: 495b ldr r1, [pc, #364] ; (800fa7c <netif_add+0x188>)
800f910: 485b ldr r0, [pc, #364] ; (800fa80 <netif_add+0x18c>)
800f912: f00b fb7f bl 801b014 <iprintf>
800f916: 2300 movs r3, #0
800f918: e0a9 b.n 800fa6e <netif_add+0x17a>
LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
800f91a: 6a7b ldr r3, [r7, #36] ; 0x24
800f91c: 2b00 cmp r3, #0
800f91e: d108 bne.n 800f932 <netif_add+0x3e>
800f920: 4b55 ldr r3, [pc, #340] ; (800fa78 <netif_add+0x184>)
800f922: f44f 7294 mov.w r2, #296 ; 0x128
800f926: 4957 ldr r1, [pc, #348] ; (800fa84 <netif_add+0x190>)
800f928: 4855 ldr r0, [pc, #340] ; (800fa80 <netif_add+0x18c>)
800f92a: f00b fb73 bl 801b014 <iprintf>
800f92e: 2300 movs r3, #0
800f930: e09d b.n 800fa6e <netif_add+0x17a>
#if LWIP_IPV4
if (ipaddr == NULL) {
800f932: 68bb ldr r3, [r7, #8]
800f934: 2b00 cmp r3, #0
800f936: d101 bne.n 800f93c <netif_add+0x48>
ipaddr = ip_2_ip4(IP4_ADDR_ANY);
800f938: 4b53 ldr r3, [pc, #332] ; (800fa88 <netif_add+0x194>)
800f93a: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800f93c: 687b ldr r3, [r7, #4]
800f93e: 2b00 cmp r3, #0
800f940: d101 bne.n 800f946 <netif_add+0x52>
netmask = ip_2_ip4(IP4_ADDR_ANY);
800f942: 4b51 ldr r3, [pc, #324] ; (800fa88 <netif_add+0x194>)
800f944: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800f946: 683b ldr r3, [r7, #0]
800f948: 2b00 cmp r3, #0
800f94a: d101 bne.n 800f950 <netif_add+0x5c>
gw = ip_2_ip4(IP4_ADDR_ANY);
800f94c: 4b4e ldr r3, [pc, #312] ; (800fa88 <netif_add+0x194>)
800f94e: 603b str r3, [r7, #0]
}
/* reset new interface configuration state */
ip_addr_set_zero_ip4(&netif->ip_addr);
800f950: 68fb ldr r3, [r7, #12]
800f952: 2200 movs r2, #0
800f954: 605a str r2, [r3, #4]
ip_addr_set_zero_ip4(&netif->netmask);
800f956: 68fb ldr r3, [r7, #12]
800f958: 2200 movs r2, #0
800f95a: 609a str r2, [r3, #8]
ip_addr_set_zero_ip4(&netif->gw);
800f95c: 68fb ldr r3, [r7, #12]
800f95e: 2200 movs r2, #0
800f960: 60da str r2, [r3, #12]
netif->output = netif_null_output_ip4;
800f962: 68fb ldr r3, [r7, #12]
800f964: 4a49 ldr r2, [pc, #292] ; (800fa8c <netif_add+0x198>)
800f966: 615a str r2, [r3, #20]
#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
}
netif->output_ip6 = netif_null_output_ip6;
#endif /* LWIP_IPV6 */
NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
netif->mtu = 0;
800f968: 68fb ldr r3, [r7, #12]
800f96a: 2200 movs r2, #0
800f96c: 851a strh r2, [r3, #40] ; 0x28
netif->flags = 0;
800f96e: 68fb ldr r3, [r7, #12]
800f970: 2200 movs r2, #0
800f972: f883 2031 strb.w r2, [r3, #49] ; 0x31
#ifdef netif_get_client_data
memset(netif->client_data, 0, sizeof(netif->client_data));
800f976: 68fb ldr r3, [r7, #12]
800f978: 3324 adds r3, #36 ; 0x24
800f97a: 2204 movs r2, #4
800f97c: 2100 movs r1, #0
800f97e: 4618 mov r0, r3
800f980: f00b fb40 bl 801b004 <memset>
#endif /* LWIP_IPV6 */
#if LWIP_NETIF_STATUS_CALLBACK
netif->status_callback = NULL;
#endif /* LWIP_NETIF_STATUS_CALLBACK */
#if LWIP_NETIF_LINK_CALLBACK
netif->link_callback = NULL;
800f984: 68fb ldr r3, [r7, #12]
800f986: 2200 movs r2, #0
800f988: 61da str r2, [r3, #28]
netif->loop_first = NULL;
netif->loop_last = NULL;
#endif /* ENABLE_LOOPBACK */
/* remember netif specific state information data */
netif->state = state;
800f98a: 68fb ldr r3, [r7, #12]
800f98c: 6a3a ldr r2, [r7, #32]
800f98e: 621a str r2, [r3, #32]
netif->num = netif_num;
800f990: 4b3f ldr r3, [pc, #252] ; (800fa90 <netif_add+0x19c>)
800f992: 781a ldrb r2, [r3, #0]
800f994: 68fb ldr r3, [r7, #12]
800f996: f883 2034 strb.w r2, [r3, #52] ; 0x34
netif->input = input;
800f99a: 68fb ldr r3, [r7, #12]
800f99c: 6aba ldr r2, [r7, #40] ; 0x28
800f99e: 611a str r2, [r3, #16]
#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
netif->loop_cnt_current = 0;
#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
#if LWIP_IPV4
netif_set_addr(netif, ipaddr, netmask, gw);
800f9a0: 683b ldr r3, [r7, #0]
800f9a2: 687a ldr r2, [r7, #4]
800f9a4: 68b9 ldr r1, [r7, #8]
800f9a6: 68f8 ldr r0, [r7, #12]
800f9a8: f000 f914 bl 800fbd4 <netif_set_addr>
#endif /* LWIP_IPV4 */
/* call user specified initialization function for netif */
if (init(netif) != ERR_OK) {
800f9ac: 6a7b ldr r3, [r7, #36] ; 0x24
800f9ae: 68f8 ldr r0, [r7, #12]
800f9b0: 4798 blx r3
800f9b2: 4603 mov r3, r0
800f9b4: 2b00 cmp r3, #0
800f9b6: d001 beq.n 800f9bc <netif_add+0xc8>
return NULL;
800f9b8: 2300 movs r3, #0
800f9ba: e058 b.n 800fa6e <netif_add+0x17a>
*/
{
struct netif *netif2;
int num_netifs;
do {
if (netif->num == 255) {
800f9bc: 68fb ldr r3, [r7, #12]
800f9be: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800f9c2: 2bff cmp r3, #255 ; 0xff
800f9c4: d103 bne.n 800f9ce <netif_add+0xda>
netif->num = 0;
800f9c6: 68fb ldr r3, [r7, #12]
800f9c8: 2200 movs r2, #0
800f9ca: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
num_netifs = 0;
800f9ce: 2300 movs r3, #0
800f9d0: 613b str r3, [r7, #16]
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800f9d2: 4b30 ldr r3, [pc, #192] ; (800fa94 <netif_add+0x1a0>)
800f9d4: 681b ldr r3, [r3, #0]
800f9d6: 617b str r3, [r7, #20]
800f9d8: e02b b.n 800fa32 <netif_add+0x13e>
LWIP_ASSERT("netif already added", netif2 != netif);
800f9da: 697a ldr r2, [r7, #20]
800f9dc: 68fb ldr r3, [r7, #12]
800f9de: 429a cmp r2, r3
800f9e0: d106 bne.n 800f9f0 <netif_add+0xfc>
800f9e2: 4b25 ldr r3, [pc, #148] ; (800fa78 <netif_add+0x184>)
800f9e4: f240 128b movw r2, #395 ; 0x18b
800f9e8: 492b ldr r1, [pc, #172] ; (800fa98 <netif_add+0x1a4>)
800f9ea: 4825 ldr r0, [pc, #148] ; (800fa80 <netif_add+0x18c>)
800f9ec: f00b fb12 bl 801b014 <iprintf>
num_netifs++;
800f9f0: 693b ldr r3, [r7, #16]
800f9f2: 3301 adds r3, #1
800f9f4: 613b str r3, [r7, #16]
LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
800f9f6: 693b ldr r3, [r7, #16]
800f9f8: 2bff cmp r3, #255 ; 0xff
800f9fa: dd06 ble.n 800fa0a <netif_add+0x116>
800f9fc: 4b1e ldr r3, [pc, #120] ; (800fa78 <netif_add+0x184>)
800f9fe: f240 128d movw r2, #397 ; 0x18d
800fa02: 4926 ldr r1, [pc, #152] ; (800fa9c <netif_add+0x1a8>)
800fa04: 481e ldr r0, [pc, #120] ; (800fa80 <netif_add+0x18c>)
800fa06: f00b fb05 bl 801b014 <iprintf>
if (netif2->num == netif->num) {
800fa0a: 697b ldr r3, [r7, #20]
800fa0c: f893 2034 ldrb.w r2, [r3, #52] ; 0x34
800fa10: 68fb ldr r3, [r7, #12]
800fa12: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa16: 429a cmp r2, r3
800fa18: d108 bne.n 800fa2c <netif_add+0x138>
netif->num++;
800fa1a: 68fb ldr r3, [r7, #12]
800fa1c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa20: 3301 adds r3, #1
800fa22: b2da uxtb r2, r3
800fa24: 68fb ldr r3, [r7, #12]
800fa26: f883 2034 strb.w r2, [r3, #52] ; 0x34
break;
800fa2a: e005 b.n 800fa38 <netif_add+0x144>
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800fa2c: 697b ldr r3, [r7, #20]
800fa2e: 681b ldr r3, [r3, #0]
800fa30: 617b str r3, [r7, #20]
800fa32: 697b ldr r3, [r7, #20]
800fa34: 2b00 cmp r3, #0
800fa36: d1d0 bne.n 800f9da <netif_add+0xe6>
}
}
} while (netif2 != NULL);
800fa38: 697b ldr r3, [r7, #20]
800fa3a: 2b00 cmp r3, #0
800fa3c: d1be bne.n 800f9bc <netif_add+0xc8>
}
if (netif->num == 254) {
800fa3e: 68fb ldr r3, [r7, #12]
800fa40: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa44: 2bfe cmp r3, #254 ; 0xfe
800fa46: d103 bne.n 800fa50 <netif_add+0x15c>
netif_num = 0;
800fa48: 4b11 ldr r3, [pc, #68] ; (800fa90 <netif_add+0x19c>)
800fa4a: 2200 movs r2, #0
800fa4c: 701a strb r2, [r3, #0]
800fa4e: e006 b.n 800fa5e <netif_add+0x16a>
} else {
netif_num = (u8_t)(netif->num + 1);
800fa50: 68fb ldr r3, [r7, #12]
800fa52: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa56: 3301 adds r3, #1
800fa58: b2da uxtb r2, r3
800fa5a: 4b0d ldr r3, [pc, #52] ; (800fa90 <netif_add+0x19c>)
800fa5c: 701a strb r2, [r3, #0]
}
/* add this netif to the list */
netif->next = netif_list;
800fa5e: 4b0d ldr r3, [pc, #52] ; (800fa94 <netif_add+0x1a0>)
800fa60: 681a ldr r2, [r3, #0]
800fa62: 68fb ldr r3, [r7, #12]
800fa64: 601a str r2, [r3, #0]
netif_list = netif;
800fa66: 4a0b ldr r2, [pc, #44] ; (800fa94 <netif_add+0x1a0>)
800fa68: 68fb ldr r3, [r7, #12]
800fa6a: 6013 str r3, [r2, #0]
#endif /* LWIP_IPV4 */
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
return netif;
800fa6c: 68fb ldr r3, [r7, #12]
}
800fa6e: 4618 mov r0, r3
800fa70: 3718 adds r7, #24
800fa72: 46bd mov sp, r7
800fa74: bd80 pop {r7, pc}
800fa76: bf00 nop
800fa78: 0801c418 .word 0x0801c418
800fa7c: 0801c4ac .word 0x0801c4ac
800fa80: 0801c468 .word 0x0801c468
800fa84: 0801c4c8 .word 0x0801c4c8
800fa88: 08020e68 .word 0x08020e68
800fa8c: 0800feb7 .word 0x0800feb7
800fa90: 20008728 .word 0x20008728
800fa94: 2000f5b0 .word 0x2000f5b0
800fa98: 0801c4ec .word 0x0801c4ec
800fa9c: 0801c500 .word 0x0801c500
0800faa0 <netif_do_ip_addr_changed>:
static void
netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
800faa0: b580 push {r7, lr}
800faa2: b082 sub sp, #8
800faa4: af00 add r7, sp, #0
800faa6: 6078 str r0, [r7, #4]
800faa8: 6039 str r1, [r7, #0]
#if LWIP_TCP
tcp_netif_ip_addr_changed(old_addr, new_addr);
800faaa: 6839 ldr r1, [r7, #0]
800faac: 6878 ldr r0, [r7, #4]
800faae: f002 fb81 bl 80121b4 <tcp_netif_ip_addr_changed>
#endif /* LWIP_TCP */
#if LWIP_UDP
udp_netif_ip_addr_changed(old_addr, new_addr);
800fab2: 6839 ldr r1, [r7, #0]
800fab4: 6878 ldr r0, [r7, #4]
800fab6: f006 ffa1 bl 80169fc <udp_netif_ip_addr_changed>
#endif /* LWIP_UDP */
#if LWIP_RAW
raw_netif_ip_addr_changed(old_addr, new_addr);
#endif /* LWIP_RAW */
}
800faba: bf00 nop
800fabc: 3708 adds r7, #8
800fabe: 46bd mov sp, r7
800fac0: bd80 pop {r7, pc}
...
0800fac4 <netif_do_set_ipaddr>:
#if LWIP_IPV4
static int
netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
{
800fac4: b580 push {r7, lr}
800fac6: b086 sub sp, #24
800fac8: af00 add r7, sp, #0
800faca: 60f8 str r0, [r7, #12]
800facc: 60b9 str r1, [r7, #8]
800face: 607a str r2, [r7, #4]
LWIP_ASSERT("invalid pointer", ipaddr != NULL);
800fad0: 68bb ldr r3, [r7, #8]
800fad2: 2b00 cmp r3, #0
800fad4: d106 bne.n 800fae4 <netif_do_set_ipaddr+0x20>
800fad6: 4b1d ldr r3, [pc, #116] ; (800fb4c <netif_do_set_ipaddr+0x88>)
800fad8: f240 12cb movw r2, #459 ; 0x1cb
800fadc: 491c ldr r1, [pc, #112] ; (800fb50 <netif_do_set_ipaddr+0x8c>)
800fade: 481d ldr r0, [pc, #116] ; (800fb54 <netif_do_set_ipaddr+0x90>)
800fae0: f00b fa98 bl 801b014 <iprintf>
LWIP_ASSERT("invalid pointer", old_addr != NULL);
800fae4: 687b ldr r3, [r7, #4]
800fae6: 2b00 cmp r3, #0
800fae8: d106 bne.n 800faf8 <netif_do_set_ipaddr+0x34>
800faea: 4b18 ldr r3, [pc, #96] ; (800fb4c <netif_do_set_ipaddr+0x88>)
800faec: f44f 72e6 mov.w r2, #460 ; 0x1cc
800faf0: 4917 ldr r1, [pc, #92] ; (800fb50 <netif_do_set_ipaddr+0x8c>)
800faf2: 4818 ldr r0, [pc, #96] ; (800fb54 <netif_do_set_ipaddr+0x90>)
800faf4: f00b fa8e bl 801b014 <iprintf>
/* address is actually being changed? */
if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
800faf8: 68bb ldr r3, [r7, #8]
800fafa: 681a ldr r2, [r3, #0]
800fafc: 68fb ldr r3, [r7, #12]
800fafe: 3304 adds r3, #4
800fb00: 681b ldr r3, [r3, #0]
800fb02: 429a cmp r2, r3
800fb04: d01c beq.n 800fb40 <netif_do_set_ipaddr+0x7c>
ip_addr_t new_addr;
*ip_2_ip4(&new_addr) = *ipaddr;
800fb06: 68bb ldr r3, [r7, #8]
800fb08: 681b ldr r3, [r3, #0]
800fb0a: 617b str r3, [r7, #20]
IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
800fb0c: 68fb ldr r3, [r7, #12]
800fb0e: 3304 adds r3, #4
800fb10: 681a ldr r2, [r3, #0]
800fb12: 687b ldr r3, [r7, #4]
800fb14: 601a str r2, [r3, #0]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
netif_do_ip_addr_changed(old_addr, &new_addr);
800fb16: f107 0314 add.w r3, r7, #20
800fb1a: 4619 mov r1, r3
800fb1c: 6878 ldr r0, [r7, #4]
800fb1e: f7ff ffbf bl 800faa0 <netif_do_ip_addr_changed>
mib2_remove_ip4(netif);
mib2_remove_route_ip4(0, netif);
/* set new IP address to netif */
ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
800fb22: 68bb ldr r3, [r7, #8]
800fb24: 2b00 cmp r3, #0
800fb26: d002 beq.n 800fb2e <netif_do_set_ipaddr+0x6a>
800fb28: 68bb ldr r3, [r7, #8]
800fb2a: 681b ldr r3, [r3, #0]
800fb2c: e000 b.n 800fb30 <netif_do_set_ipaddr+0x6c>
800fb2e: 2300 movs r3, #0
800fb30: 68fa ldr r2, [r7, #12]
800fb32: 6053 str r3, [r2, #4]
IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
mib2_add_ip4(netif);
mib2_add_route_ip4(0, netif);
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
800fb34: 2101 movs r1, #1
800fb36: 68f8 ldr r0, [r7, #12]
800fb38: f000 f8d2 bl 800fce0 <netif_issue_reports>
NETIF_STATUS_CALLBACK(netif);
return 1; /* address changed */
800fb3c: 2301 movs r3, #1
800fb3e: e000 b.n 800fb42 <netif_do_set_ipaddr+0x7e>
}
return 0; /* address unchanged */
800fb40: 2300 movs r3, #0
}
800fb42: 4618 mov r0, r3
800fb44: 3718 adds r7, #24
800fb46: 46bd mov sp, r7
800fb48: bd80 pop {r7, pc}
800fb4a: bf00 nop
800fb4c: 0801c418 .word 0x0801c418
800fb50: 0801c530 .word 0x0801c530
800fb54: 0801c468 .word 0x0801c468
0800fb58 <netif_do_set_netmask>:
}
}
static int
netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
{
800fb58: b480 push {r7}
800fb5a: b085 sub sp, #20
800fb5c: af00 add r7, sp, #0
800fb5e: 60f8 str r0, [r7, #12]
800fb60: 60b9 str r1, [r7, #8]
800fb62: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
800fb64: 68bb ldr r3, [r7, #8]
800fb66: 681a ldr r2, [r3, #0]
800fb68: 68fb ldr r3, [r7, #12]
800fb6a: 3308 adds r3, #8
800fb6c: 681b ldr r3, [r3, #0]
800fb6e: 429a cmp r2, r3
800fb70: d00a beq.n 800fb88 <netif_do_set_netmask+0x30>
#else
LWIP_UNUSED_ARG(old_nm);
#endif
mib2_remove_route_ip4(0, netif);
/* set new netmask to netif */
ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
800fb72: 68bb ldr r3, [r7, #8]
800fb74: 2b00 cmp r3, #0
800fb76: d002 beq.n 800fb7e <netif_do_set_netmask+0x26>
800fb78: 68bb ldr r3, [r7, #8]
800fb7a: 681b ldr r3, [r3, #0]
800fb7c: e000 b.n 800fb80 <netif_do_set_netmask+0x28>
800fb7e: 2300 movs r3, #0
800fb80: 68fa ldr r2, [r7, #12]
800fb82: 6093 str r3, [r2, #8]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_netmask(netif)),
ip4_addr2_16(netif_ip4_netmask(netif)),
ip4_addr3_16(netif_ip4_netmask(netif)),
ip4_addr4_16(netif_ip4_netmask(netif))));
return 1; /* netmask changed */
800fb84: 2301 movs r3, #1
800fb86: e000 b.n 800fb8a <netif_do_set_netmask+0x32>
}
return 0; /* netmask unchanged */
800fb88: 2300 movs r3, #0
}
800fb8a: 4618 mov r0, r3
800fb8c: 3714 adds r7, #20
800fb8e: 46bd mov sp, r7
800fb90: f85d 7b04 ldr.w r7, [sp], #4
800fb94: 4770 bx lr
0800fb96 <netif_do_set_gw>:
}
}
static int
netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
{
800fb96: b480 push {r7}
800fb98: b085 sub sp, #20
800fb9a: af00 add r7, sp, #0
800fb9c: 60f8 str r0, [r7, #12]
800fb9e: 60b9 str r1, [r7, #8]
800fba0: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
800fba2: 68bb ldr r3, [r7, #8]
800fba4: 681a ldr r2, [r3, #0]
800fba6: 68fb ldr r3, [r7, #12]
800fba8: 330c adds r3, #12
800fbaa: 681b ldr r3, [r3, #0]
800fbac: 429a cmp r2, r3
800fbae: d00a beq.n 800fbc6 <netif_do_set_gw+0x30>
ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
#else
LWIP_UNUSED_ARG(old_gw);
#endif
ip4_addr_set(ip_2_ip4(&netif->gw), gw);
800fbb0: 68bb ldr r3, [r7, #8]
800fbb2: 2b00 cmp r3, #0
800fbb4: d002 beq.n 800fbbc <netif_do_set_gw+0x26>
800fbb6: 68bb ldr r3, [r7, #8]
800fbb8: 681b ldr r3, [r3, #0]
800fbba: e000 b.n 800fbbe <netif_do_set_gw+0x28>
800fbbc: 2300 movs r3, #0
800fbbe: 68fa ldr r2, [r7, #12]
800fbc0: 60d3 str r3, [r2, #12]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_gw(netif)),
ip4_addr2_16(netif_ip4_gw(netif)),
ip4_addr3_16(netif_ip4_gw(netif)),
ip4_addr4_16(netif_ip4_gw(netif))));
return 1; /* gateway changed */
800fbc2: 2301 movs r3, #1
800fbc4: e000 b.n 800fbc8 <netif_do_set_gw+0x32>
}
return 0; /* gateway unchanged */
800fbc6: 2300 movs r3, #0
}
800fbc8: 4618 mov r0, r3
800fbca: 3714 adds r7, #20
800fbcc: 46bd mov sp, r7
800fbce: f85d 7b04 ldr.w r7, [sp], #4
800fbd2: 4770 bx lr
0800fbd4 <netif_set_addr>:
* @param gw the new default gateway
*/
void
netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
const ip4_addr_t *gw)
{
800fbd4: b580 push {r7, lr}
800fbd6: b088 sub sp, #32
800fbd8: af00 add r7, sp, #0
800fbda: 60f8 str r0, [r7, #12]
800fbdc: 60b9 str r1, [r7, #8]
800fbde: 607a str r2, [r7, #4]
800fbe0: 603b str r3, [r7, #0]
ip_addr_t old_nm_val;
ip_addr_t old_gw_val;
ip_addr_t *old_nm = &old_nm_val;
ip_addr_t *old_gw = &old_gw_val;
#else
ip_addr_t *old_nm = NULL;
800fbe2: 2300 movs r3, #0
800fbe4: 61fb str r3, [r7, #28]
ip_addr_t *old_gw = NULL;
800fbe6: 2300 movs r3, #0
800fbe8: 61bb str r3, [r7, #24]
int remove;
LWIP_ASSERT_CORE_LOCKED();
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
800fbea: 68bb ldr r3, [r7, #8]
800fbec: 2b00 cmp r3, #0
800fbee: d101 bne.n 800fbf4 <netif_set_addr+0x20>
ipaddr = IP4_ADDR_ANY4;
800fbf0: 4b1c ldr r3, [pc, #112] ; (800fc64 <netif_set_addr+0x90>)
800fbf2: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800fbf4: 687b ldr r3, [r7, #4]
800fbf6: 2b00 cmp r3, #0
800fbf8: d101 bne.n 800fbfe <netif_set_addr+0x2a>
netmask = IP4_ADDR_ANY4;
800fbfa: 4b1a ldr r3, [pc, #104] ; (800fc64 <netif_set_addr+0x90>)
800fbfc: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800fbfe: 683b ldr r3, [r7, #0]
800fc00: 2b00 cmp r3, #0
800fc02: d101 bne.n 800fc08 <netif_set_addr+0x34>
gw = IP4_ADDR_ANY4;
800fc04: 4b17 ldr r3, [pc, #92] ; (800fc64 <netif_set_addr+0x90>)
800fc06: 603b str r3, [r7, #0]
}
remove = ip4_addr_isany(ipaddr);
800fc08: 68bb ldr r3, [r7, #8]
800fc0a: 2b00 cmp r3, #0
800fc0c: d003 beq.n 800fc16 <netif_set_addr+0x42>
800fc0e: 68bb ldr r3, [r7, #8]
800fc10: 681b ldr r3, [r3, #0]
800fc12: 2b00 cmp r3, #0
800fc14: d101 bne.n 800fc1a <netif_set_addr+0x46>
800fc16: 2301 movs r3, #1
800fc18: e000 b.n 800fc1c <netif_set_addr+0x48>
800fc1a: 2300 movs r3, #0
800fc1c: 617b str r3, [r7, #20]
if (remove) {
800fc1e: 697b ldr r3, [r7, #20]
800fc20: 2b00 cmp r3, #0
800fc22: d006 beq.n 800fc32 <netif_set_addr+0x5e>
/* when removing an address, we have to remove it *before* changing netmask/gw
to ensure that tcp RST segment can be sent correctly */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fc24: f107 0310 add.w r3, r7, #16
800fc28: 461a mov r2, r3
800fc2a: 68b9 ldr r1, [r7, #8]
800fc2c: 68f8 ldr r0, [r7, #12]
800fc2e: f7ff ff49 bl 800fac4 <netif_do_set_ipaddr>
change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
cb_args.ipv4_changed.old_address = &old_addr;
#endif
}
}
if (netif_do_set_netmask(netif, netmask, old_nm)) {
800fc32: 69fa ldr r2, [r7, #28]
800fc34: 6879 ldr r1, [r7, #4]
800fc36: 68f8 ldr r0, [r7, #12]
800fc38: f7ff ff8e bl 800fb58 <netif_do_set_netmask>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
cb_args.ipv4_changed.old_netmask = old_nm;
#endif
}
if (netif_do_set_gw(netif, gw, old_gw)) {
800fc3c: 69ba ldr r2, [r7, #24]
800fc3e: 6839 ldr r1, [r7, #0]
800fc40: 68f8 ldr r0, [r7, #12]
800fc42: f7ff ffa8 bl 800fb96 <netif_do_set_gw>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
cb_args.ipv4_changed.old_gw = old_gw;
#endif
}
if (!remove) {
800fc46: 697b ldr r3, [r7, #20]
800fc48: 2b00 cmp r3, #0
800fc4a: d106 bne.n 800fc5a <netif_set_addr+0x86>
/* set ipaddr last to ensure netmask/gw have been set when status callback is called */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fc4c: f107 0310 add.w r3, r7, #16
800fc50: 461a mov r2, r3
800fc52: 68b9 ldr r1, [r7, #8]
800fc54: 68f8 ldr r0, [r7, #12]
800fc56: f7ff ff35 bl 800fac4 <netif_do_set_ipaddr>
if (change_reason != LWIP_NSC_NONE) {
change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
netif_invoke_ext_callback(netif, change_reason, &cb_args);
}
#endif
}
800fc5a: bf00 nop
800fc5c: 3720 adds r7, #32
800fc5e: 46bd mov sp, r7
800fc60: bd80 pop {r7, pc}
800fc62: bf00 nop
800fc64: 08020e68 .word 0x08020e68
0800fc68 <netif_set_default>:
*
* @param netif the default network interface
*/
void
netif_set_default(struct netif *netif)
{
800fc68: b480 push {r7}
800fc6a: b083 sub sp, #12
800fc6c: af00 add r7, sp, #0
800fc6e: 6078 str r0, [r7, #4]
mib2_remove_route_ip4(1, netif);
} else {
/* install default route */
mib2_add_route_ip4(1, netif);
}
netif_default = netif;
800fc70: 4a04 ldr r2, [pc, #16] ; (800fc84 <netif_set_default+0x1c>)
800fc72: 687b ldr r3, [r7, #4]
800fc74: 6013 str r3, [r2, #0]
LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
}
800fc76: bf00 nop
800fc78: 370c adds r7, #12
800fc7a: 46bd mov sp, r7
800fc7c: f85d 7b04 ldr.w r7, [sp], #4
800fc80: 4770 bx lr
800fc82: bf00 nop
800fc84: 2000f5b4 .word 0x2000f5b4
0800fc88 <netif_set_up>:
* Bring an interface up, available for processing
* traffic.
*/
void
netif_set_up(struct netif *netif)
{
800fc88: b580 push {r7, lr}
800fc8a: b082 sub sp, #8
800fc8c: af00 add r7, sp, #0
800fc8e: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
800fc90: 687b ldr r3, [r7, #4]
800fc92: 2b00 cmp r3, #0
800fc94: d107 bne.n 800fca6 <netif_set_up+0x1e>
800fc96: 4b0f ldr r3, [pc, #60] ; (800fcd4 <netif_set_up+0x4c>)
800fc98: f44f 7254 mov.w r2, #848 ; 0x350
800fc9c: 490e ldr r1, [pc, #56] ; (800fcd8 <netif_set_up+0x50>)
800fc9e: 480f ldr r0, [pc, #60] ; (800fcdc <netif_set_up+0x54>)
800fca0: f00b f9b8 bl 801b014 <iprintf>
800fca4: e013 b.n 800fcce <netif_set_up+0x46>
if (!(netif->flags & NETIF_FLAG_UP)) {
800fca6: 687b ldr r3, [r7, #4]
800fca8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcac: f003 0301 and.w r3, r3, #1
800fcb0: 2b00 cmp r3, #0
800fcb2: d10c bne.n 800fcce <netif_set_up+0x46>
netif_set_flags(netif, NETIF_FLAG_UP);
800fcb4: 687b ldr r3, [r7, #4]
800fcb6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcba: f043 0301 orr.w r3, r3, #1
800fcbe: b2da uxtb r2, r3
800fcc0: 687b ldr r3, [r7, #4]
800fcc2: f883 2031 strb.w r2, [r3, #49] ; 0x31
args.status_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fcc6: 2103 movs r1, #3
800fcc8: 6878 ldr r0, [r7, #4]
800fcca: f000 f809 bl 800fce0 <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
}
}
800fcce: 3708 adds r7, #8
800fcd0: 46bd mov sp, r7
800fcd2: bd80 pop {r7, pc}
800fcd4: 0801c418 .word 0x0801c418
800fcd8: 0801c5a0 .word 0x0801c5a0
800fcdc: 0801c468 .word 0x0801c468
0800fce0 <netif_issue_reports>:
/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
*/
static void
netif_issue_reports(struct netif *netif, u8_t report_type)
{
800fce0: b580 push {r7, lr}
800fce2: b082 sub sp, #8
800fce4: af00 add r7, sp, #0
800fce6: 6078 str r0, [r7, #4]
800fce8: 460b mov r3, r1
800fcea: 70fb strb r3, [r7, #3]
LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
800fcec: 687b ldr r3, [r7, #4]
800fcee: 2b00 cmp r3, #0
800fcf0: d106 bne.n 800fd00 <netif_issue_reports+0x20>
800fcf2: 4b18 ldr r3, [pc, #96] ; (800fd54 <netif_issue_reports+0x74>)
800fcf4: f240 326d movw r2, #877 ; 0x36d
800fcf8: 4917 ldr r1, [pc, #92] ; (800fd58 <netif_issue_reports+0x78>)
800fcfa: 4818 ldr r0, [pc, #96] ; (800fd5c <netif_issue_reports+0x7c>)
800fcfc: f00b f98a bl 801b014 <iprintf>
/* Only send reports when both link and admin states are up */
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fd00: 687b ldr r3, [r7, #4]
800fd02: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd06: f003 0304 and.w r3, r3, #4
800fd0a: 2b00 cmp r3, #0
800fd0c: d01e beq.n 800fd4c <netif_issue_reports+0x6c>
!(netif->flags & NETIF_FLAG_UP)) {
800fd0e: 687b ldr r3, [r7, #4]
800fd10: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd14: f003 0301 and.w r3, r3, #1
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fd18: 2b00 cmp r3, #0
800fd1a: d017 beq.n 800fd4c <netif_issue_reports+0x6c>
return;
}
#if LWIP_IPV4
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fd1c: 78fb ldrb r3, [r7, #3]
800fd1e: f003 0301 and.w r3, r3, #1
800fd22: 2b00 cmp r3, #0
800fd24: d013 beq.n 800fd4e <netif_issue_reports+0x6e>
!ip4_addr_isany_val(*netif_ip4_addr(netif))) {
800fd26: 687b ldr r3, [r7, #4]
800fd28: 3304 adds r3, #4
800fd2a: 681b ldr r3, [r3, #0]
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fd2c: 2b00 cmp r3, #0
800fd2e: d00e beq.n 800fd4e <netif_issue_reports+0x6e>
#if LWIP_ARP
/* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
if (netif->flags & (NETIF_FLAG_ETHARP)) {
800fd30: 687b ldr r3, [r7, #4]
800fd32: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd36: f003 0308 and.w r3, r3, #8
800fd3a: 2b00 cmp r3, #0
800fd3c: d007 beq.n 800fd4e <netif_issue_reports+0x6e>
etharp_gratuitous(netif);
800fd3e: 687b ldr r3, [r7, #4]
800fd40: 3304 adds r3, #4
800fd42: 4619 mov r1, r3
800fd44: 6878 ldr r0, [r7, #4]
800fd46: f009 fc6b bl 8019620 <etharp_request>
800fd4a: e000 b.n 800fd4e <netif_issue_reports+0x6e>
return;
800fd4c: bf00 nop
/* send mld memberships */
mld6_report_groups(netif);
#endif /* LWIP_IPV6_MLD */
}
#endif /* LWIP_IPV6 */
}
800fd4e: 3708 adds r7, #8
800fd50: 46bd mov sp, r7
800fd52: bd80 pop {r7, pc}
800fd54: 0801c418 .word 0x0801c418
800fd58: 0801c5bc .word 0x0801c5bc
800fd5c: 0801c468 .word 0x0801c468
0800fd60 <netif_set_down>:
* @ingroup netif
* Bring an interface down, disabling any traffic processing.
*/
void
netif_set_down(struct netif *netif)
{
800fd60: b580 push {r7, lr}
800fd62: b082 sub sp, #8
800fd64: af00 add r7, sp, #0
800fd66: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
800fd68: 687b ldr r3, [r7, #4]
800fd6a: 2b00 cmp r3, #0
800fd6c: d107 bne.n 800fd7e <netif_set_down+0x1e>
800fd6e: 4b12 ldr r3, [pc, #72] ; (800fdb8 <netif_set_down+0x58>)
800fd70: f240 329b movw r2, #923 ; 0x39b
800fd74: 4911 ldr r1, [pc, #68] ; (800fdbc <netif_set_down+0x5c>)
800fd76: 4812 ldr r0, [pc, #72] ; (800fdc0 <netif_set_down+0x60>)
800fd78: f00b f94c bl 801b014 <iprintf>
800fd7c: e019 b.n 800fdb2 <netif_set_down+0x52>
if (netif->flags & NETIF_FLAG_UP) {
800fd7e: 687b ldr r3, [r7, #4]
800fd80: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd84: f003 0301 and.w r3, r3, #1
800fd88: 2b00 cmp r3, #0
800fd8a: d012 beq.n 800fdb2 <netif_set_down+0x52>
args.status_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_clear_flags(netif, NETIF_FLAG_UP);
800fd8c: 687b ldr r3, [r7, #4]
800fd8e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd92: f023 0301 bic.w r3, r3, #1
800fd96: b2da uxtb r2, r3
800fd98: 687b ldr r3, [r7, #4]
800fd9a: f883 2031 strb.w r2, [r3, #49] ; 0x31
MIB2_COPY_SYSUPTIME_TO(&netif->ts);
#if LWIP_IPV4 && LWIP_ARP
if (netif->flags & NETIF_FLAG_ETHARP) {
800fd9e: 687b ldr r3, [r7, #4]
800fda0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fda4: f003 0308 and.w r3, r3, #8
800fda8: 2b00 cmp r3, #0
800fdaa: d002 beq.n 800fdb2 <netif_set_down+0x52>
etharp_cleanup_netif(netif);
800fdac: 6878 ldr r0, [r7, #4]
800fdae: f008 fff1 bl 8018d94 <etharp_cleanup_netif>
nd6_cleanup_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_STATUS_CALLBACK(netif);
}
}
800fdb2: 3708 adds r7, #8
800fdb4: 46bd mov sp, r7
800fdb6: bd80 pop {r7, pc}
800fdb8: 0801c418 .word 0x0801c418
800fdbc: 0801c5e0 .word 0x0801c5e0
800fdc0: 0801c468 .word 0x0801c468
0800fdc4 <netif_set_link_up>:
* @ingroup netif
* Called by a driver when its link goes up
*/
void
netif_set_link_up(struct netif *netif)
{
800fdc4: b580 push {r7, lr}
800fdc6: b082 sub sp, #8
800fdc8: af00 add r7, sp, #0
800fdca: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
800fdcc: 687b ldr r3, [r7, #4]
800fdce: 2b00 cmp r3, #0
800fdd0: d107 bne.n 800fde2 <netif_set_link_up+0x1e>
800fdd2: 4b15 ldr r3, [pc, #84] ; (800fe28 <netif_set_link_up+0x64>)
800fdd4: f44f 7278 mov.w r2, #992 ; 0x3e0
800fdd8: 4914 ldr r1, [pc, #80] ; (800fe2c <netif_set_link_up+0x68>)
800fdda: 4815 ldr r0, [pc, #84] ; (800fe30 <netif_set_link_up+0x6c>)
800fddc: f00b f91a bl 801b014 <iprintf>
800fde0: e01e b.n 800fe20 <netif_set_link_up+0x5c>
if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
800fde2: 687b ldr r3, [r7, #4]
800fde4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fde8: f003 0304 and.w r3, r3, #4
800fdec: 2b00 cmp r3, #0
800fdee: d117 bne.n 800fe20 <netif_set_link_up+0x5c>
netif_set_flags(netif, NETIF_FLAG_LINK_UP);
800fdf0: 687b ldr r3, [r7, #4]
800fdf2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fdf6: f043 0304 orr.w r3, r3, #4
800fdfa: b2da uxtb r2, r3
800fdfc: 687b ldr r3, [r7, #4]
800fdfe: f883 2031 strb.w r2, [r3, #49] ; 0x31
#if LWIP_DHCP
dhcp_network_changed(netif);
800fe02: 6878 ldr r0, [r7, #4]
800fe04: f007 fa26 bl 8017254 <dhcp_network_changed>
#if LWIP_AUTOIP
autoip_network_changed(netif);
#endif /* LWIP_AUTOIP */
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fe08: 2103 movs r1, #3
800fe0a: 6878 ldr r0, [r7, #4]
800fe0c: f7ff ff68 bl 800fce0 <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_LINK_CALLBACK(netif);
800fe10: 687b ldr r3, [r7, #4]
800fe12: 69db ldr r3, [r3, #28]
800fe14: 2b00 cmp r3, #0
800fe16: d003 beq.n 800fe20 <netif_set_link_up+0x5c>
800fe18: 687b ldr r3, [r7, #4]
800fe1a: 69db ldr r3, [r3, #28]
800fe1c: 6878 ldr r0, [r7, #4]
800fe1e: 4798 blx r3
args.link_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fe20: 3708 adds r7, #8
800fe22: 46bd mov sp, r7
800fe24: bd80 pop {r7, pc}
800fe26: bf00 nop
800fe28: 0801c418 .word 0x0801c418
800fe2c: 0801c600 .word 0x0801c600
800fe30: 0801c468 .word 0x0801c468
0800fe34 <netif_set_link_down>:
* @ingroup netif
* Called by a driver when its link goes down
*/
void
netif_set_link_down(struct netif *netif)
{
800fe34: b580 push {r7, lr}
800fe36: b082 sub sp, #8
800fe38: af00 add r7, sp, #0
800fe3a: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
800fe3c: 687b ldr r3, [r7, #4]
800fe3e: 2b00 cmp r3, #0
800fe40: d107 bne.n 800fe52 <netif_set_link_down+0x1e>
800fe42: 4b11 ldr r3, [pc, #68] ; (800fe88 <netif_set_link_down+0x54>)
800fe44: f240 4206 movw r2, #1030 ; 0x406
800fe48: 4910 ldr r1, [pc, #64] ; (800fe8c <netif_set_link_down+0x58>)
800fe4a: 4811 ldr r0, [pc, #68] ; (800fe90 <netif_set_link_down+0x5c>)
800fe4c: f00b f8e2 bl 801b014 <iprintf>
800fe50: e017 b.n 800fe82 <netif_set_link_down+0x4e>
if (netif->flags & NETIF_FLAG_LINK_UP) {
800fe52: 687b ldr r3, [r7, #4]
800fe54: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe58: f003 0304 and.w r3, r3, #4
800fe5c: 2b00 cmp r3, #0
800fe5e: d010 beq.n 800fe82 <netif_set_link_down+0x4e>
netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
800fe60: 687b ldr r3, [r7, #4]
800fe62: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe66: f023 0304 bic.w r3, r3, #4
800fe6a: b2da uxtb r2, r3
800fe6c: 687b ldr r3, [r7, #4]
800fe6e: f883 2031 strb.w r2, [r3, #49] ; 0x31
NETIF_LINK_CALLBACK(netif);
800fe72: 687b ldr r3, [r7, #4]
800fe74: 69db ldr r3, [r3, #28]
800fe76: 2b00 cmp r3, #0
800fe78: d003 beq.n 800fe82 <netif_set_link_down+0x4e>
800fe7a: 687b ldr r3, [r7, #4]
800fe7c: 69db ldr r3, [r3, #28]
800fe7e: 6878 ldr r0, [r7, #4]
800fe80: 4798 blx r3
args.link_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fe82: 3708 adds r7, #8
800fe84: 46bd mov sp, r7
800fe86: bd80 pop {r7, pc}
800fe88: 0801c418 .word 0x0801c418
800fe8c: 0801c624 .word 0x0801c624
800fe90: 0801c468 .word 0x0801c468
0800fe94 <netif_set_link_callback>:
* @ingroup netif
* Set callback to be called when link is brought up/down
*/
void
netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
{
800fe94: b480 push {r7}
800fe96: b083 sub sp, #12
800fe98: af00 add r7, sp, #0
800fe9a: 6078 str r0, [r7, #4]
800fe9c: 6039 str r1, [r7, #0]
LWIP_ASSERT_CORE_LOCKED();
if (netif) {
800fe9e: 687b ldr r3, [r7, #4]
800fea0: 2b00 cmp r3, #0
800fea2: d002 beq.n 800feaa <netif_set_link_callback+0x16>
netif->link_callback = link_callback;
800fea4: 687b ldr r3, [r7, #4]
800fea6: 683a ldr r2, [r7, #0]
800fea8: 61da str r2, [r3, #28]
}
}
800feaa: bf00 nop
800feac: 370c adds r7, #12
800feae: 46bd mov sp, r7
800feb0: f85d 7b04 ldr.w r7, [sp], #4
800feb4: 4770 bx lr
0800feb6 <netif_null_output_ip4>:
#if LWIP_IPV4
/** Dummy IPv4 output function for netifs not supporting IPv4
*/
static err_t
netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
{
800feb6: b480 push {r7}
800feb8: b085 sub sp, #20
800feba: af00 add r7, sp, #0
800febc: 60f8 str r0, [r7, #12]
800febe: 60b9 str r1, [r7, #8]
800fec0: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(netif);
LWIP_UNUSED_ARG(p);
LWIP_UNUSED_ARG(ipaddr);
return ERR_IF;
800fec2: f06f 030b mvn.w r3, #11
}
800fec6: 4618 mov r0, r3
800fec8: 3714 adds r7, #20
800feca: 46bd mov sp, r7
800fecc: f85d 7b04 ldr.w r7, [sp], #4
800fed0: 4770 bx lr
...
0800fed4 <netif_get_by_index>:
*
* @param idx index of netif to find
*/
struct netif *
netif_get_by_index(u8_t idx)
{
800fed4: b480 push {r7}
800fed6: b085 sub sp, #20
800fed8: af00 add r7, sp, #0
800feda: 4603 mov r3, r0
800fedc: 71fb strb r3, [r7, #7]
struct netif *netif;
LWIP_ASSERT_CORE_LOCKED();
if (idx != NETIF_NO_INDEX) {
800fede: 79fb ldrb r3, [r7, #7]
800fee0: 2b00 cmp r3, #0
800fee2: d013 beq.n 800ff0c <netif_get_by_index+0x38>
NETIF_FOREACH(netif) {
800fee4: 4b0d ldr r3, [pc, #52] ; (800ff1c <netif_get_by_index+0x48>)
800fee6: 681b ldr r3, [r3, #0]
800fee8: 60fb str r3, [r7, #12]
800feea: e00c b.n 800ff06 <netif_get_by_index+0x32>
if (idx == netif_get_index(netif)) {
800feec: 68fb ldr r3, [r7, #12]
800feee: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fef2: 3301 adds r3, #1
800fef4: b2db uxtb r3, r3
800fef6: 79fa ldrb r2, [r7, #7]
800fef8: 429a cmp r2, r3
800fefa: d101 bne.n 800ff00 <netif_get_by_index+0x2c>
return netif; /* found! */
800fefc: 68fb ldr r3, [r7, #12]
800fefe: e006 b.n 800ff0e <netif_get_by_index+0x3a>
NETIF_FOREACH(netif) {
800ff00: 68fb ldr r3, [r7, #12]
800ff02: 681b ldr r3, [r3, #0]
800ff04: 60fb str r3, [r7, #12]
800ff06: 68fb ldr r3, [r7, #12]
800ff08: 2b00 cmp r3, #0
800ff0a: d1ef bne.n 800feec <netif_get_by_index+0x18>
}
}
}
return NULL;
800ff0c: 2300 movs r3, #0
}
800ff0e: 4618 mov r0, r3
800ff10: 3714 adds r7, #20
800ff12: 46bd mov sp, r7
800ff14: f85d 7b04 ldr.w r7, [sp], #4
800ff18: 4770 bx lr
800ff1a: bf00 nop
800ff1c: 2000f5b0 .word 0x2000f5b0
0800ff20 <pbuf_free_ooseq>:
#if !NO_SYS
static
#endif /* !NO_SYS */
void
pbuf_free_ooseq(void)
{
800ff20: b580 push {r7, lr}
800ff22: b082 sub sp, #8
800ff24: af00 add r7, sp, #0
struct tcp_pcb *pcb;
SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
800ff26: f00b f811 bl 801af4c <sys_arch_protect>
800ff2a: 6038 str r0, [r7, #0]
800ff2c: 4b0d ldr r3, [pc, #52] ; (800ff64 <pbuf_free_ooseq+0x44>)
800ff2e: 2200 movs r2, #0
800ff30: 701a strb r2, [r3, #0]
800ff32: 6838 ldr r0, [r7, #0]
800ff34: f00b f818 bl 801af68 <sys_arch_unprotect>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800ff38: 4b0b ldr r3, [pc, #44] ; (800ff68 <pbuf_free_ooseq+0x48>)
800ff3a: 681b ldr r3, [r3, #0]
800ff3c: 607b str r3, [r7, #4]
800ff3e: e00a b.n 800ff56 <pbuf_free_ooseq+0x36>
if (pcb->ooseq != NULL) {
800ff40: 687b ldr r3, [r7, #4]
800ff42: 6f5b ldr r3, [r3, #116] ; 0x74
800ff44: 2b00 cmp r3, #0
800ff46: d003 beq.n 800ff50 <pbuf_free_ooseq+0x30>
/** Free the ooseq pbufs of one PCB only */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
tcp_free_ooseq(pcb);
800ff48: 6878 ldr r0, [r7, #4]
800ff4a: f002 f971 bl 8012230 <tcp_free_ooseq>
return;
800ff4e: e005 b.n 800ff5c <pbuf_free_ooseq+0x3c>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800ff50: 687b ldr r3, [r7, #4]
800ff52: 68db ldr r3, [r3, #12]
800ff54: 607b str r3, [r7, #4]
800ff56: 687b ldr r3, [r7, #4]
800ff58: 2b00 cmp r3, #0
800ff5a: d1f1 bne.n 800ff40 <pbuf_free_ooseq+0x20>
}
}
}
800ff5c: 3708 adds r7, #8
800ff5e: 46bd mov sp, r7
800ff60: bd80 pop {r7, pc}
800ff62: bf00 nop
800ff64: 2000f5b8 .word 0x2000f5b8
800ff68: 2000f5c0 .word 0x2000f5c0
0800ff6c <pbuf_free_ooseq_callback>:
/**
* Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
*/
static void
pbuf_free_ooseq_callback(void *arg)
{
800ff6c: b580 push {r7, lr}
800ff6e: b082 sub sp, #8
800ff70: af00 add r7, sp, #0
800ff72: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
pbuf_free_ooseq();
800ff74: f7ff ffd4 bl 800ff20 <pbuf_free_ooseq>
}
800ff78: bf00 nop
800ff7a: 3708 adds r7, #8
800ff7c: 46bd mov sp, r7
800ff7e: bd80 pop {r7, pc}
0800ff80 <pbuf_pool_is_empty>:
#endif /* !NO_SYS */
/** Queue a call to pbuf_free_ooseq if not already queued. */
static void
pbuf_pool_is_empty(void)
{
800ff80: b580 push {r7, lr}
800ff82: b082 sub sp, #8
800ff84: af00 add r7, sp, #0
#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
u8_t queued;
SYS_ARCH_DECL_PROTECT(old_level);
SYS_ARCH_PROTECT(old_level);
800ff86: f00a ffe1 bl 801af4c <sys_arch_protect>
800ff8a: 6078 str r0, [r7, #4]
queued = pbuf_free_ooseq_pending;
800ff8c: 4b0f ldr r3, [pc, #60] ; (800ffcc <pbuf_pool_is_empty+0x4c>)
800ff8e: 781b ldrb r3, [r3, #0]
800ff90: 70fb strb r3, [r7, #3]
pbuf_free_ooseq_pending = 1;
800ff92: 4b0e ldr r3, [pc, #56] ; (800ffcc <pbuf_pool_is_empty+0x4c>)
800ff94: 2201 movs r2, #1
800ff96: 701a strb r2, [r3, #0]
SYS_ARCH_UNPROTECT(old_level);
800ff98: 6878 ldr r0, [r7, #4]
800ff9a: f00a ffe5 bl 801af68 <sys_arch_unprotect>
if (!queued) {
800ff9e: 78fb ldrb r3, [r7, #3]
800ffa0: 2b00 cmp r3, #0
800ffa2: d10f bne.n 800ffc4 <pbuf_pool_is_empty+0x44>
/* queue a call to pbuf_free_ooseq if not already queued */
PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
800ffa4: 2100 movs r1, #0
800ffa6: 480a ldr r0, [pc, #40] ; (800ffd0 <pbuf_pool_is_empty+0x50>)
800ffa8: f7fe fee0 bl 800ed6c <tcpip_try_callback>
800ffac: 4603 mov r3, r0
800ffae: 2b00 cmp r3, #0
800ffb0: d008 beq.n 800ffc4 <pbuf_pool_is_empty+0x44>
800ffb2: f00a ffcb bl 801af4c <sys_arch_protect>
800ffb6: 6078 str r0, [r7, #4]
800ffb8: 4b04 ldr r3, [pc, #16] ; (800ffcc <pbuf_pool_is_empty+0x4c>)
800ffba: 2200 movs r2, #0
800ffbc: 701a strb r2, [r3, #0]
800ffbe: 6878 ldr r0, [r7, #4]
800ffc0: f00a ffd2 bl 801af68 <sys_arch_unprotect>
}
#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
}
800ffc4: bf00 nop
800ffc6: 3708 adds r7, #8
800ffc8: 46bd mov sp, r7
800ffca: bd80 pop {r7, pc}
800ffcc: 2000f5b8 .word 0x2000f5b8
800ffd0: 0800ff6d .word 0x0800ff6d
0800ffd4 <pbuf_init_alloced_pbuf>:
#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
/* Initialize members of struct pbuf after allocation */
static void
pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
{
800ffd4: b480 push {r7}
800ffd6: b085 sub sp, #20
800ffd8: af00 add r7, sp, #0
800ffda: 60f8 str r0, [r7, #12]
800ffdc: 60b9 str r1, [r7, #8]
800ffde: 4611 mov r1, r2
800ffe0: 461a mov r2, r3
800ffe2: 460b mov r3, r1
800ffe4: 80fb strh r3, [r7, #6]
800ffe6: 4613 mov r3, r2
800ffe8: 80bb strh r3, [r7, #4]
p->next = NULL;
800ffea: 68fb ldr r3, [r7, #12]
800ffec: 2200 movs r2, #0
800ffee: 601a str r2, [r3, #0]
p->payload = payload;
800fff0: 68fb ldr r3, [r7, #12]
800fff2: 68ba ldr r2, [r7, #8]
800fff4: 605a str r2, [r3, #4]
p->tot_len = tot_len;
800fff6: 68fb ldr r3, [r7, #12]
800fff8: 88fa ldrh r2, [r7, #6]
800fffa: 811a strh r2, [r3, #8]
p->len = len;
800fffc: 68fb ldr r3, [r7, #12]
800fffe: 88ba ldrh r2, [r7, #4]
8010000: 815a strh r2, [r3, #10]
p->type_internal = (u8_t)type;
8010002: 8b3b ldrh r3, [r7, #24]
8010004: b2da uxtb r2, r3
8010006: 68fb ldr r3, [r7, #12]
8010008: 731a strb r2, [r3, #12]
p->flags = flags;
801000a: 68fb ldr r3, [r7, #12]
801000c: 7f3a ldrb r2, [r7, #28]
801000e: 735a strb r2, [r3, #13]
p->ref = 1;
8010010: 68fb ldr r3, [r7, #12]
8010012: 2201 movs r2, #1
8010014: 739a strb r2, [r3, #14]
p->if_idx = NETIF_NO_INDEX;
8010016: 68fb ldr r3, [r7, #12]
8010018: 2200 movs r2, #0
801001a: 73da strb r2, [r3, #15]
}
801001c: bf00 nop
801001e: 3714 adds r7, #20
8010020: 46bd mov sp, r7
8010022: f85d 7b04 ldr.w r7, [sp], #4
8010026: 4770 bx lr
08010028 <pbuf_alloc>:
* @return the allocated pbuf. If multiple pbufs where allocated, this
* is the first pbuf of a pbuf chain.
*/
struct pbuf *
pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
{
8010028: b580 push {r7, lr}
801002a: b08c sub sp, #48 ; 0x30
801002c: af02 add r7, sp, #8
801002e: 4603 mov r3, r0
8010030: 71fb strb r3, [r7, #7]
8010032: 460b mov r3, r1
8010034: 80bb strh r3, [r7, #4]
8010036: 4613 mov r3, r2
8010038: 807b strh r3, [r7, #2]
struct pbuf *p;
u16_t offset = (u16_t)layer;
801003a: 79fb ldrb r3, [r7, #7]
801003c: 847b strh r3, [r7, #34] ; 0x22
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
switch (type) {
801003e: 887b ldrh r3, [r7, #2]
8010040: 2b41 cmp r3, #65 ; 0x41
8010042: d00b beq.n 801005c <pbuf_alloc+0x34>
8010044: 2b41 cmp r3, #65 ; 0x41
8010046: dc02 bgt.n 801004e <pbuf_alloc+0x26>
8010048: 2b01 cmp r3, #1
801004a: d007 beq.n 801005c <pbuf_alloc+0x34>
801004c: e0c2 b.n 80101d4 <pbuf_alloc+0x1ac>
801004e: f5b3 7fc1 cmp.w r3, #386 ; 0x182
8010052: d00b beq.n 801006c <pbuf_alloc+0x44>
8010054: f5b3 7f20 cmp.w r3, #640 ; 0x280
8010058: d070 beq.n 801013c <pbuf_alloc+0x114>
801005a: e0bb b.n 80101d4 <pbuf_alloc+0x1ac>
case PBUF_REF: /* fall through */
case PBUF_ROM:
p = pbuf_alloc_reference(NULL, length, type);
801005c: 887a ldrh r2, [r7, #2]
801005e: 88bb ldrh r3, [r7, #4]
8010060: 4619 mov r1, r3
8010062: 2000 movs r0, #0
8010064: f000 f8d2 bl 801020c <pbuf_alloc_reference>
8010068: 6278 str r0, [r7, #36] ; 0x24
break;
801006a: e0bd b.n 80101e8 <pbuf_alloc+0x1c0>
case PBUF_POOL: {
struct pbuf *q, *last;
u16_t rem_len; /* remaining length */
p = NULL;
801006c: 2300 movs r3, #0
801006e: 627b str r3, [r7, #36] ; 0x24
last = NULL;
8010070: 2300 movs r3, #0
8010072: 61fb str r3, [r7, #28]
rem_len = length;
8010074: 88bb ldrh r3, [r7, #4]
8010076: 837b strh r3, [r7, #26]
do {
u16_t qlen;
q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
8010078: 200c movs r0, #12
801007a: f7ff fbb7 bl 800f7ec <memp_malloc>
801007e: 6138 str r0, [r7, #16]
if (q == NULL) {
8010080: 693b ldr r3, [r7, #16]
8010082: 2b00 cmp r3, #0
8010084: d109 bne.n 801009a <pbuf_alloc+0x72>
PBUF_POOL_IS_EMPTY();
8010086: f7ff ff7b bl 800ff80 <pbuf_pool_is_empty>
/* free chain so far allocated */
if (p) {
801008a: 6a7b ldr r3, [r7, #36] ; 0x24
801008c: 2b00 cmp r3, #0
801008e: d002 beq.n 8010096 <pbuf_alloc+0x6e>
pbuf_free(p);
8010090: 6a78 ldr r0, [r7, #36] ; 0x24
8010092: f000 faa9 bl 80105e8 <pbuf_free>
}
/* bail out unsuccessfully */
return NULL;
8010096: 2300 movs r3, #0
8010098: e0a7 b.n 80101ea <pbuf_alloc+0x1c2>
}
qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
801009a: 8c7b ldrh r3, [r7, #34] ; 0x22
801009c: 3303 adds r3, #3
801009e: b29b uxth r3, r3
80100a0: f023 0303 bic.w r3, r3, #3
80100a4: b29b uxth r3, r3
80100a6: f5c3 7314 rsb r3, r3, #592 ; 0x250
80100aa: b29b uxth r3, r3
80100ac: 8b7a ldrh r2, [r7, #26]
80100ae: 4293 cmp r3, r2
80100b0: bf28 it cs
80100b2: 4613 movcs r3, r2
80100b4: 81fb strh r3, [r7, #14]
pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
80100b6: 8c7b ldrh r3, [r7, #34] ; 0x22
80100b8: 3310 adds r3, #16
80100ba: 693a ldr r2, [r7, #16]
80100bc: 4413 add r3, r2
80100be: 3303 adds r3, #3
80100c0: f023 0303 bic.w r3, r3, #3
80100c4: 4618 mov r0, r3
80100c6: 89f9 ldrh r1, [r7, #14]
80100c8: 8b7a ldrh r2, [r7, #26]
80100ca: 2300 movs r3, #0
80100cc: 9301 str r3, [sp, #4]
80100ce: 887b ldrh r3, [r7, #2]
80100d0: 9300 str r3, [sp, #0]
80100d2: 460b mov r3, r1
80100d4: 4601 mov r1, r0
80100d6: 6938 ldr r0, [r7, #16]
80100d8: f7ff ff7c bl 800ffd4 <pbuf_init_alloced_pbuf>
rem_len, qlen, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
80100dc: 693b ldr r3, [r7, #16]
80100de: 685b ldr r3, [r3, #4]
80100e0: f003 0303 and.w r3, r3, #3
80100e4: 2b00 cmp r3, #0
80100e6: d006 beq.n 80100f6 <pbuf_alloc+0xce>
80100e8: 4b42 ldr r3, [pc, #264] ; (80101f4 <pbuf_alloc+0x1cc>)
80100ea: f240 1201 movw r2, #257 ; 0x101
80100ee: 4942 ldr r1, [pc, #264] ; (80101f8 <pbuf_alloc+0x1d0>)
80100f0: 4842 ldr r0, [pc, #264] ; (80101fc <pbuf_alloc+0x1d4>)
80100f2: f00a ff8f bl 801b014 <iprintf>
((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
80100f6: 8c7b ldrh r3, [r7, #34] ; 0x22
80100f8: 3303 adds r3, #3
80100fa: f023 0303 bic.w r3, r3, #3
80100fe: f5b3 7f14 cmp.w r3, #592 ; 0x250
8010102: d106 bne.n 8010112 <pbuf_alloc+0xea>
8010104: 4b3b ldr r3, [pc, #236] ; (80101f4 <pbuf_alloc+0x1cc>)
8010106: f240 1203 movw r2, #259 ; 0x103
801010a: 493d ldr r1, [pc, #244] ; (8010200 <pbuf_alloc+0x1d8>)
801010c: 483b ldr r0, [pc, #236] ; (80101fc <pbuf_alloc+0x1d4>)
801010e: f00a ff81 bl 801b014 <iprintf>
(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
if (p == NULL) {
8010112: 6a7b ldr r3, [r7, #36] ; 0x24
8010114: 2b00 cmp r3, #0
8010116: d102 bne.n 801011e <pbuf_alloc+0xf6>
/* allocated head of pbuf chain (into p) */
p = q;
8010118: 693b ldr r3, [r7, #16]
801011a: 627b str r3, [r7, #36] ; 0x24
801011c: e002 b.n 8010124 <pbuf_alloc+0xfc>
} else {
/* make previous pbuf point to this pbuf */
last->next = q;
801011e: 69fb ldr r3, [r7, #28]
8010120: 693a ldr r2, [r7, #16]
8010122: 601a str r2, [r3, #0]
}
last = q;
8010124: 693b ldr r3, [r7, #16]
8010126: 61fb str r3, [r7, #28]
rem_len = (u16_t)(rem_len - qlen);
8010128: 8b7a ldrh r2, [r7, #26]
801012a: 89fb ldrh r3, [r7, #14]
801012c: 1ad3 subs r3, r2, r3
801012e: 837b strh r3, [r7, #26]
offset = 0;
8010130: 2300 movs r3, #0
8010132: 847b strh r3, [r7, #34] ; 0x22
} while (rem_len > 0);
8010134: 8b7b ldrh r3, [r7, #26]
8010136: 2b00 cmp r3, #0
8010138: d19e bne.n 8010078 <pbuf_alloc+0x50>
break;
801013a: e055 b.n 80101e8 <pbuf_alloc+0x1c0>
}
case PBUF_RAM: {
u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
801013c: 8c7b ldrh r3, [r7, #34] ; 0x22
801013e: 3303 adds r3, #3
8010140: b29b uxth r3, r3
8010142: f023 0303 bic.w r3, r3, #3
8010146: b29a uxth r2, r3
8010148: 88bb ldrh r3, [r7, #4]
801014a: 3303 adds r3, #3
801014c: b29b uxth r3, r3
801014e: f023 0303 bic.w r3, r3, #3
8010152: b29b uxth r3, r3
8010154: 4413 add r3, r2
8010156: 833b strh r3, [r7, #24]
mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
8010158: 8b3b ldrh r3, [r7, #24]
801015a: 3310 adds r3, #16
801015c: 82fb strh r3, [r7, #22]
/* bug #50040: Check for integer overflow when calculating alloc_len */
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
801015e: 8b3a ldrh r2, [r7, #24]
8010160: 88bb ldrh r3, [r7, #4]
8010162: 3303 adds r3, #3
8010164: f023 0303 bic.w r3, r3, #3
8010168: 429a cmp r2, r3
801016a: d306 bcc.n 801017a <pbuf_alloc+0x152>
(alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
801016c: 8afa ldrh r2, [r7, #22]
801016e: 88bb ldrh r3, [r7, #4]
8010170: 3303 adds r3, #3
8010172: f023 0303 bic.w r3, r3, #3
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
8010176: 429a cmp r2, r3
8010178: d201 bcs.n 801017e <pbuf_alloc+0x156>
return NULL;
801017a: 2300 movs r3, #0
801017c: e035 b.n 80101ea <pbuf_alloc+0x1c2>
}
/* If pbuf is to be allocated in RAM, allocate memory for it. */
p = (struct pbuf *)mem_malloc(alloc_len);
801017e: 8afb ldrh r3, [r7, #22]
8010180: 4618 mov r0, r3
8010182: f7ff f9b1 bl 800f4e8 <mem_malloc>
8010186: 6278 str r0, [r7, #36] ; 0x24
if (p == NULL) {
8010188: 6a7b ldr r3, [r7, #36] ; 0x24
801018a: 2b00 cmp r3, #0
801018c: d101 bne.n 8010192 <pbuf_alloc+0x16a>
return NULL;
801018e: 2300 movs r3, #0
8010190: e02b b.n 80101ea <pbuf_alloc+0x1c2>
}
pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
8010192: 8c7b ldrh r3, [r7, #34] ; 0x22
8010194: 3310 adds r3, #16
8010196: 6a7a ldr r2, [r7, #36] ; 0x24
8010198: 4413 add r3, r2
801019a: 3303 adds r3, #3
801019c: f023 0303 bic.w r3, r3, #3
80101a0: 4618 mov r0, r3
80101a2: 88b9 ldrh r1, [r7, #4]
80101a4: 88ba ldrh r2, [r7, #4]
80101a6: 2300 movs r3, #0
80101a8: 9301 str r3, [sp, #4]
80101aa: 887b ldrh r3, [r7, #2]
80101ac: 9300 str r3, [sp, #0]
80101ae: 460b mov r3, r1
80101b0: 4601 mov r1, r0
80101b2: 6a78 ldr r0, [r7, #36] ; 0x24
80101b4: f7ff ff0e bl 800ffd4 <pbuf_init_alloced_pbuf>
length, length, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
80101b8: 6a7b ldr r3, [r7, #36] ; 0x24
80101ba: 685b ldr r3, [r3, #4]
80101bc: f003 0303 and.w r3, r3, #3
80101c0: 2b00 cmp r3, #0
80101c2: d010 beq.n 80101e6 <pbuf_alloc+0x1be>
80101c4: 4b0b ldr r3, [pc, #44] ; (80101f4 <pbuf_alloc+0x1cc>)
80101c6: f240 1223 movw r2, #291 ; 0x123
80101ca: 490e ldr r1, [pc, #56] ; (8010204 <pbuf_alloc+0x1dc>)
80101cc: 480b ldr r0, [pc, #44] ; (80101fc <pbuf_alloc+0x1d4>)
80101ce: f00a ff21 bl 801b014 <iprintf>
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
break;
80101d2: e008 b.n 80101e6 <pbuf_alloc+0x1be>
}
default:
LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
80101d4: 4b07 ldr r3, [pc, #28] ; (80101f4 <pbuf_alloc+0x1cc>)
80101d6: f240 1227 movw r2, #295 ; 0x127
80101da: 490b ldr r1, [pc, #44] ; (8010208 <pbuf_alloc+0x1e0>)
80101dc: 4807 ldr r0, [pc, #28] ; (80101fc <pbuf_alloc+0x1d4>)
80101de: f00a ff19 bl 801b014 <iprintf>
return NULL;
80101e2: 2300 movs r3, #0
80101e4: e001 b.n 80101ea <pbuf_alloc+0x1c2>
break;
80101e6: bf00 nop
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
return p;
80101e8: 6a7b ldr r3, [r7, #36] ; 0x24
}
80101ea: 4618 mov r0, r3
80101ec: 3728 adds r7, #40 ; 0x28
80101ee: 46bd mov sp, r7
80101f0: bd80 pop {r7, pc}
80101f2: bf00 nop
80101f4: 0801c648 .word 0x0801c648
80101f8: 0801c678 .word 0x0801c678
80101fc: 0801c6a8 .word 0x0801c6a8
8010200: 0801c6d0 .word 0x0801c6d0
8010204: 0801c704 .word 0x0801c704
8010208: 0801c730 .word 0x0801c730
0801020c <pbuf_alloc_reference>:
*
* @return the allocated pbuf.
*/
struct pbuf *
pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
{
801020c: b580 push {r7, lr}
801020e: b086 sub sp, #24
8010210: af02 add r7, sp, #8
8010212: 6078 str r0, [r7, #4]
8010214: 460b mov r3, r1
8010216: 807b strh r3, [r7, #2]
8010218: 4613 mov r3, r2
801021a: 803b strh r3, [r7, #0]
struct pbuf *p;
LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
801021c: 883b ldrh r3, [r7, #0]
801021e: 2b41 cmp r3, #65 ; 0x41
8010220: d009 beq.n 8010236 <pbuf_alloc_reference+0x2a>
8010222: 883b ldrh r3, [r7, #0]
8010224: 2b01 cmp r3, #1
8010226: d006 beq.n 8010236 <pbuf_alloc_reference+0x2a>
8010228: 4b0f ldr r3, [pc, #60] ; (8010268 <pbuf_alloc_reference+0x5c>)
801022a: f44f 72a5 mov.w r2, #330 ; 0x14a
801022e: 490f ldr r1, [pc, #60] ; (801026c <pbuf_alloc_reference+0x60>)
8010230: 480f ldr r0, [pc, #60] ; (8010270 <pbuf_alloc_reference+0x64>)
8010232: f00a feef bl 801b014 <iprintf>
/* only allocate memory for the pbuf structure */
p = (struct pbuf *)memp_malloc(MEMP_PBUF);
8010236: 200b movs r0, #11
8010238: f7ff fad8 bl 800f7ec <memp_malloc>
801023c: 60f8 str r0, [r7, #12]
if (p == NULL) {
801023e: 68fb ldr r3, [r7, #12]
8010240: 2b00 cmp r3, #0
8010242: d101 bne.n 8010248 <pbuf_alloc_reference+0x3c>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
(type == PBUF_ROM) ? "ROM" : "REF"));
return NULL;
8010244: 2300 movs r3, #0
8010246: e00b b.n 8010260 <pbuf_alloc_reference+0x54>
}
pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
8010248: 8879 ldrh r1, [r7, #2]
801024a: 887a ldrh r2, [r7, #2]
801024c: 2300 movs r3, #0
801024e: 9301 str r3, [sp, #4]
8010250: 883b ldrh r3, [r7, #0]
8010252: 9300 str r3, [sp, #0]
8010254: 460b mov r3, r1
8010256: 6879 ldr r1, [r7, #4]
8010258: 68f8 ldr r0, [r7, #12]
801025a: f7ff febb bl 800ffd4 <pbuf_init_alloced_pbuf>
return p;
801025e: 68fb ldr r3, [r7, #12]
}
8010260: 4618 mov r0, r3
8010262: 3710 adds r7, #16
8010264: 46bd mov sp, r7
8010266: bd80 pop {r7, pc}
8010268: 0801c648 .word 0x0801c648
801026c: 0801c74c .word 0x0801c74c
8010270: 0801c6a8 .word 0x0801c6a8
08010274 <pbuf_alloced_custom>:
* big enough to hold 'length' plus the header size
*/
struct pbuf *
pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
void *payload_mem, u16_t payload_mem_len)
{
8010274: b580 push {r7, lr}
8010276: b088 sub sp, #32
8010278: af02 add r7, sp, #8
801027a: 607b str r3, [r7, #4]
801027c: 4603 mov r3, r0
801027e: 73fb strb r3, [r7, #15]
8010280: 460b mov r3, r1
8010282: 81bb strh r3, [r7, #12]
8010284: 4613 mov r3, r2
8010286: 817b strh r3, [r7, #10]
u16_t offset = (u16_t)l;
8010288: 7bfb ldrb r3, [r7, #15]
801028a: 827b strh r3, [r7, #18]
void *payload;
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
801028c: 8a7b ldrh r3, [r7, #18]
801028e: 3303 adds r3, #3
8010290: f023 0203 bic.w r2, r3, #3
8010294: 89bb ldrh r3, [r7, #12]
8010296: 441a add r2, r3
8010298: 8cbb ldrh r3, [r7, #36] ; 0x24
801029a: 429a cmp r2, r3
801029c: d901 bls.n 80102a2 <pbuf_alloced_custom+0x2e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
return NULL;
801029e: 2300 movs r3, #0
80102a0: e018 b.n 80102d4 <pbuf_alloced_custom+0x60>
}
if (payload_mem != NULL) {
80102a2: 6a3b ldr r3, [r7, #32]
80102a4: 2b00 cmp r3, #0
80102a6: d007 beq.n 80102b8 <pbuf_alloced_custom+0x44>
payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
80102a8: 8a7b ldrh r3, [r7, #18]
80102aa: 3303 adds r3, #3
80102ac: f023 0303 bic.w r3, r3, #3
80102b0: 6a3a ldr r2, [r7, #32]
80102b2: 4413 add r3, r2
80102b4: 617b str r3, [r7, #20]
80102b6: e001 b.n 80102bc <pbuf_alloced_custom+0x48>
} else {
payload = NULL;
80102b8: 2300 movs r3, #0
80102ba: 617b str r3, [r7, #20]
}
pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
80102bc: 6878 ldr r0, [r7, #4]
80102be: 89b9 ldrh r1, [r7, #12]
80102c0: 89ba ldrh r2, [r7, #12]
80102c2: 2302 movs r3, #2
80102c4: 9301 str r3, [sp, #4]
80102c6: 897b ldrh r3, [r7, #10]
80102c8: 9300 str r3, [sp, #0]
80102ca: 460b mov r3, r1
80102cc: 6979 ldr r1, [r7, #20]
80102ce: f7ff fe81 bl 800ffd4 <pbuf_init_alloced_pbuf>
return &p->pbuf;
80102d2: 687b ldr r3, [r7, #4]
}
80102d4: 4618 mov r0, r3
80102d6: 3718 adds r7, #24
80102d8: 46bd mov sp, r7
80102da: bd80 pop {r7, pc}
080102dc <pbuf_realloc>:
*
* @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
*/
void
pbuf_realloc(struct pbuf *p, u16_t new_len)
{
80102dc: b580 push {r7, lr}
80102de: b084 sub sp, #16
80102e0: af00 add r7, sp, #0
80102e2: 6078 str r0, [r7, #4]
80102e4: 460b mov r3, r1
80102e6: 807b strh r3, [r7, #2]
struct pbuf *q;
u16_t rem_len; /* remaining length */
u16_t shrink;
LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
80102e8: 687b ldr r3, [r7, #4]
80102ea: 2b00 cmp r3, #0
80102ec: d106 bne.n 80102fc <pbuf_realloc+0x20>
80102ee: 4b3a ldr r3, [pc, #232] ; (80103d8 <pbuf_realloc+0xfc>)
80102f0: f44f 72cc mov.w r2, #408 ; 0x198
80102f4: 4939 ldr r1, [pc, #228] ; (80103dc <pbuf_realloc+0x100>)
80102f6: 483a ldr r0, [pc, #232] ; (80103e0 <pbuf_realloc+0x104>)
80102f8: f00a fe8c bl 801b014 <iprintf>
/* desired length larger than current length? */
if (new_len >= p->tot_len) {
80102fc: 687b ldr r3, [r7, #4]
80102fe: 891b ldrh r3, [r3, #8]
8010300: 887a ldrh r2, [r7, #2]
8010302: 429a cmp r2, r3
8010304: d264 bcs.n 80103d0 <pbuf_realloc+0xf4>
return;
}
/* the pbuf chain grows by (new_len - p->tot_len) bytes
* (which may be negative in case of shrinking) */
shrink = (u16_t)(p->tot_len - new_len);
8010306: 687b ldr r3, [r7, #4]
8010308: 891a ldrh r2, [r3, #8]
801030a: 887b ldrh r3, [r7, #2]
801030c: 1ad3 subs r3, r2, r3
801030e: 813b strh r3, [r7, #8]
/* first, step over any pbufs that should remain in the chain */
rem_len = new_len;
8010310: 887b ldrh r3, [r7, #2]
8010312: 817b strh r3, [r7, #10]
q = p;
8010314: 687b ldr r3, [r7, #4]
8010316: 60fb str r3, [r7, #12]
/* should this pbuf be kept? */
while (rem_len > q->len) {
8010318: e018 b.n 801034c <pbuf_realloc+0x70>
/* decrease remaining length by pbuf length */
rem_len = (u16_t)(rem_len - q->len);
801031a: 68fb ldr r3, [r7, #12]
801031c: 895b ldrh r3, [r3, #10]
801031e: 897a ldrh r2, [r7, #10]
8010320: 1ad3 subs r3, r2, r3
8010322: 817b strh r3, [r7, #10]
/* decrease total length indicator */
q->tot_len = (u16_t)(q->tot_len - shrink);
8010324: 68fb ldr r3, [r7, #12]
8010326: 891a ldrh r2, [r3, #8]
8010328: 893b ldrh r3, [r7, #8]
801032a: 1ad3 subs r3, r2, r3
801032c: b29a uxth r2, r3
801032e: 68fb ldr r3, [r7, #12]
8010330: 811a strh r2, [r3, #8]
/* proceed to next pbuf in chain */
q = q->next;
8010332: 68fb ldr r3, [r7, #12]
8010334: 681b ldr r3, [r3, #0]
8010336: 60fb str r3, [r7, #12]
LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
8010338: 68fb ldr r3, [r7, #12]
801033a: 2b00 cmp r3, #0
801033c: d106 bne.n 801034c <pbuf_realloc+0x70>
801033e: 4b26 ldr r3, [pc, #152] ; (80103d8 <pbuf_realloc+0xfc>)
8010340: f240 12af movw r2, #431 ; 0x1af
8010344: 4927 ldr r1, [pc, #156] ; (80103e4 <pbuf_realloc+0x108>)
8010346: 4826 ldr r0, [pc, #152] ; (80103e0 <pbuf_realloc+0x104>)
8010348: f00a fe64 bl 801b014 <iprintf>
while (rem_len > q->len) {
801034c: 68fb ldr r3, [r7, #12]
801034e: 895b ldrh r3, [r3, #10]
8010350: 897a ldrh r2, [r7, #10]
8010352: 429a cmp r2, r3
8010354: d8e1 bhi.n 801031a <pbuf_realloc+0x3e>
/* we have now reached the new last pbuf (in q) */
/* rem_len == desired length for pbuf q */
/* shrink allocated memory for PBUF_RAM */
/* (other types merely adjust their length fields */
if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
8010356: 68fb ldr r3, [r7, #12]
8010358: 7b1b ldrb r3, [r3, #12]
801035a: f003 030f and.w r3, r3, #15
801035e: 2b00 cmp r3, #0
8010360: d122 bne.n 80103a8 <pbuf_realloc+0xcc>
8010362: 68fb ldr r3, [r7, #12]
8010364: 895b ldrh r3, [r3, #10]
8010366: 897a ldrh r2, [r7, #10]
8010368: 429a cmp r2, r3
801036a: d01d beq.n 80103a8 <pbuf_realloc+0xcc>
#if LWIP_SUPPORT_CUSTOM_PBUF
&& ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
801036c: 68fb ldr r3, [r7, #12]
801036e: 7b5b ldrb r3, [r3, #13]
8010370: f003 0302 and.w r3, r3, #2
8010374: 2b00 cmp r3, #0
8010376: d117 bne.n 80103a8 <pbuf_realloc+0xcc>
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
) {
/* reallocate and adjust the length of the pbuf that will be split */
q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
8010378: 68fb ldr r3, [r7, #12]
801037a: 685b ldr r3, [r3, #4]
801037c: 461a mov r2, r3
801037e: 68fb ldr r3, [r7, #12]
8010380: 1ad3 subs r3, r2, r3
8010382: b29a uxth r2, r3
8010384: 897b ldrh r3, [r7, #10]
8010386: 4413 add r3, r2
8010388: b29b uxth r3, r3
801038a: 4619 mov r1, r3
801038c: 68f8 ldr r0, [r7, #12]
801038e: f7fe ffa1 bl 800f2d4 <mem_trim>
8010392: 60f8 str r0, [r7, #12]
LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
8010394: 68fb ldr r3, [r7, #12]
8010396: 2b00 cmp r3, #0
8010398: d106 bne.n 80103a8 <pbuf_realloc+0xcc>
801039a: 4b0f ldr r3, [pc, #60] ; (80103d8 <pbuf_realloc+0xfc>)
801039c: f240 12bd movw r2, #445 ; 0x1bd
80103a0: 4911 ldr r1, [pc, #68] ; (80103e8 <pbuf_realloc+0x10c>)
80103a2: 480f ldr r0, [pc, #60] ; (80103e0 <pbuf_realloc+0x104>)
80103a4: f00a fe36 bl 801b014 <iprintf>
}
/* adjust length fields for new last pbuf */
q->len = rem_len;
80103a8: 68fb ldr r3, [r7, #12]
80103aa: 897a ldrh r2, [r7, #10]
80103ac: 815a strh r2, [r3, #10]
q->tot_len = q->len;
80103ae: 68fb ldr r3, [r7, #12]
80103b0: 895a ldrh r2, [r3, #10]
80103b2: 68fb ldr r3, [r7, #12]
80103b4: 811a strh r2, [r3, #8]
/* any remaining pbufs in chain? */
if (q->next != NULL) {
80103b6: 68fb ldr r3, [r7, #12]
80103b8: 681b ldr r3, [r3, #0]
80103ba: 2b00 cmp r3, #0
80103bc: d004 beq.n 80103c8 <pbuf_realloc+0xec>
/* free remaining pbufs in chain */
pbuf_free(q->next);
80103be: 68fb ldr r3, [r7, #12]
80103c0: 681b ldr r3, [r3, #0]
80103c2: 4618 mov r0, r3
80103c4: f000 f910 bl 80105e8 <pbuf_free>
}
/* q is last packet in chain */
q->next = NULL;
80103c8: 68fb ldr r3, [r7, #12]
80103ca: 2200 movs r2, #0
80103cc: 601a str r2, [r3, #0]
80103ce: e000 b.n 80103d2 <pbuf_realloc+0xf6>
return;
80103d0: bf00 nop
}
80103d2: 3710 adds r7, #16
80103d4: 46bd mov sp, r7
80103d6: bd80 pop {r7, pc}
80103d8: 0801c648 .word 0x0801c648
80103dc: 0801c760 .word 0x0801c760
80103e0: 0801c6a8 .word 0x0801c6a8
80103e4: 0801c778 .word 0x0801c778
80103e8: 0801c790 .word 0x0801c790
080103ec <pbuf_add_header_impl>:
* @return non-zero on failure, zero on success.
*
*/
static u8_t
pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
{
80103ec: b580 push {r7, lr}
80103ee: b086 sub sp, #24
80103f0: af00 add r7, sp, #0
80103f2: 60f8 str r0, [r7, #12]
80103f4: 60b9 str r1, [r7, #8]
80103f6: 4613 mov r3, r2
80103f8: 71fb strb r3, [r7, #7]
u16_t type_internal;
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
80103fa: 68fb ldr r3, [r7, #12]
80103fc: 2b00 cmp r3, #0
80103fe: d106 bne.n 801040e <pbuf_add_header_impl+0x22>
8010400: 4b2b ldr r3, [pc, #172] ; (80104b0 <pbuf_add_header_impl+0xc4>)
8010402: f240 12df movw r2, #479 ; 0x1df
8010406: 492b ldr r1, [pc, #172] ; (80104b4 <pbuf_add_header_impl+0xc8>)
8010408: 482b ldr r0, [pc, #172] ; (80104b8 <pbuf_add_header_impl+0xcc>)
801040a: f00a fe03 bl 801b014 <iprintf>
if ((p == NULL) || (header_size_increment > 0xFFFF)) {
801040e: 68fb ldr r3, [r7, #12]
8010410: 2b00 cmp r3, #0
8010412: d003 beq.n 801041c <pbuf_add_header_impl+0x30>
8010414: 68bb ldr r3, [r7, #8]
8010416: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801041a: d301 bcc.n 8010420 <pbuf_add_header_impl+0x34>
return 1;
801041c: 2301 movs r3, #1
801041e: e043 b.n 80104a8 <pbuf_add_header_impl+0xbc>
}
if (header_size_increment == 0) {
8010420: 68bb ldr r3, [r7, #8]
8010422: 2b00 cmp r3, #0
8010424: d101 bne.n 801042a <pbuf_add_header_impl+0x3e>
return 0;
8010426: 2300 movs r3, #0
8010428: e03e b.n 80104a8 <pbuf_add_header_impl+0xbc>
}
increment_magnitude = (u16_t)header_size_increment;
801042a: 68bb ldr r3, [r7, #8]
801042c: 827b strh r3, [r7, #18]
/* Do not allow tot_len to wrap as a result. */
if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
801042e: 68fb ldr r3, [r7, #12]
8010430: 891a ldrh r2, [r3, #8]
8010432: 8a7b ldrh r3, [r7, #18]
8010434: 4413 add r3, r2
8010436: b29b uxth r3, r3
8010438: 8a7a ldrh r2, [r7, #18]
801043a: 429a cmp r2, r3
801043c: d901 bls.n 8010442 <pbuf_add_header_impl+0x56>
return 1;
801043e: 2301 movs r3, #1
8010440: e032 b.n 80104a8 <pbuf_add_header_impl+0xbc>
}
type_internal = p->type_internal;
8010442: 68fb ldr r3, [r7, #12]
8010444: 7b1b ldrb r3, [r3, #12]
8010446: 823b strh r3, [r7, #16]
/* pbuf types containing payloads? */
if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
8010448: 8a3b ldrh r3, [r7, #16]
801044a: f003 0380 and.w r3, r3, #128 ; 0x80
801044e: 2b00 cmp r3, #0
8010450: d00c beq.n 801046c <pbuf_add_header_impl+0x80>
/* set new payload pointer */
payload = (u8_t *)p->payload - header_size_increment;
8010452: 68fb ldr r3, [r7, #12]
8010454: 685a ldr r2, [r3, #4]
8010456: 68bb ldr r3, [r7, #8]
8010458: 425b negs r3, r3
801045a: 4413 add r3, r2
801045c: 617b str r3, [r7, #20]
/* boundary check fails? */
if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
801045e: 68fb ldr r3, [r7, #12]
8010460: 3310 adds r3, #16
8010462: 697a ldr r2, [r7, #20]
8010464: 429a cmp r2, r3
8010466: d20d bcs.n 8010484 <pbuf_add_header_impl+0x98>
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
(void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
/* bail out unsuccessfully */
return 1;
8010468: 2301 movs r3, #1
801046a: e01d b.n 80104a8 <pbuf_add_header_impl+0xbc>
}
/* pbuf types referring to external payloads? */
} else {
/* hide a header in the payload? */
if (force) {
801046c: 79fb ldrb r3, [r7, #7]
801046e: 2b00 cmp r3, #0
8010470: d006 beq.n 8010480 <pbuf_add_header_impl+0x94>
payload = (u8_t *)p->payload - header_size_increment;
8010472: 68fb ldr r3, [r7, #12]
8010474: 685a ldr r2, [r3, #4]
8010476: 68bb ldr r3, [r7, #8]
8010478: 425b negs r3, r3
801047a: 4413 add r3, r2
801047c: 617b str r3, [r7, #20]
801047e: e001 b.n 8010484 <pbuf_add_header_impl+0x98>
} else {
/* cannot expand payload to front (yet!)
* bail out unsuccessfully */
return 1;
8010480: 2301 movs r3, #1
8010482: e011 b.n 80104a8 <pbuf_add_header_impl+0xbc>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
(void *)p->payload, (void *)payload, increment_magnitude));
/* modify pbuf fields */
p->payload = payload;
8010484: 68fb ldr r3, [r7, #12]
8010486: 697a ldr r2, [r7, #20]
8010488: 605a str r2, [r3, #4]
p->len = (u16_t)(p->len + increment_magnitude);
801048a: 68fb ldr r3, [r7, #12]
801048c: 895a ldrh r2, [r3, #10]
801048e: 8a7b ldrh r3, [r7, #18]
8010490: 4413 add r3, r2
8010492: b29a uxth r2, r3
8010494: 68fb ldr r3, [r7, #12]
8010496: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
8010498: 68fb ldr r3, [r7, #12]
801049a: 891a ldrh r2, [r3, #8]
801049c: 8a7b ldrh r3, [r7, #18]
801049e: 4413 add r3, r2
80104a0: b29a uxth r2, r3
80104a2: 68fb ldr r3, [r7, #12]
80104a4: 811a strh r2, [r3, #8]
return 0;
80104a6: 2300 movs r3, #0
}
80104a8: 4618 mov r0, r3
80104aa: 3718 adds r7, #24
80104ac: 46bd mov sp, r7
80104ae: bd80 pop {r7, pc}
80104b0: 0801c648 .word 0x0801c648
80104b4: 0801c7ac .word 0x0801c7ac
80104b8: 0801c6a8 .word 0x0801c6a8
080104bc <pbuf_add_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_add_header(struct pbuf *p, size_t header_size_increment)
{
80104bc: b580 push {r7, lr}
80104be: b082 sub sp, #8
80104c0: af00 add r7, sp, #0
80104c2: 6078 str r0, [r7, #4]
80104c4: 6039 str r1, [r7, #0]
return pbuf_add_header_impl(p, header_size_increment, 0);
80104c6: 2200 movs r2, #0
80104c8: 6839 ldr r1, [r7, #0]
80104ca: 6878 ldr r0, [r7, #4]
80104cc: f7ff ff8e bl 80103ec <pbuf_add_header_impl>
80104d0: 4603 mov r3, r0
}
80104d2: 4618 mov r0, r3
80104d4: 3708 adds r7, #8
80104d6: 46bd mov sp, r7
80104d8: bd80 pop {r7, pc}
...
080104dc <pbuf_remove_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
{
80104dc: b580 push {r7, lr}
80104de: b084 sub sp, #16
80104e0: af00 add r7, sp, #0
80104e2: 6078 str r0, [r7, #4]
80104e4: 6039 str r1, [r7, #0]
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
80104e6: 687b ldr r3, [r7, #4]
80104e8: 2b00 cmp r3, #0
80104ea: d106 bne.n 80104fa <pbuf_remove_header+0x1e>
80104ec: 4b20 ldr r3, [pc, #128] ; (8010570 <pbuf_remove_header+0x94>)
80104ee: f240 224b movw r2, #587 ; 0x24b
80104f2: 4920 ldr r1, [pc, #128] ; (8010574 <pbuf_remove_header+0x98>)
80104f4: 4820 ldr r0, [pc, #128] ; (8010578 <pbuf_remove_header+0x9c>)
80104f6: f00a fd8d bl 801b014 <iprintf>
if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
80104fa: 687b ldr r3, [r7, #4]
80104fc: 2b00 cmp r3, #0
80104fe: d003 beq.n 8010508 <pbuf_remove_header+0x2c>
8010500: 683b ldr r3, [r7, #0]
8010502: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8010506: d301 bcc.n 801050c <pbuf_remove_header+0x30>
return 1;
8010508: 2301 movs r3, #1
801050a: e02c b.n 8010566 <pbuf_remove_header+0x8a>
}
if (header_size_decrement == 0) {
801050c: 683b ldr r3, [r7, #0]
801050e: 2b00 cmp r3, #0
8010510: d101 bne.n 8010516 <pbuf_remove_header+0x3a>
return 0;
8010512: 2300 movs r3, #0
8010514: e027 b.n 8010566 <pbuf_remove_header+0x8a>
}
increment_magnitude = (u16_t)header_size_decrement;
8010516: 683b ldr r3, [r7, #0]
8010518: 81fb strh r3, [r7, #14]
/* Check that we aren't going to move off the end of the pbuf */
LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
801051a: 687b ldr r3, [r7, #4]
801051c: 895b ldrh r3, [r3, #10]
801051e: 89fa ldrh r2, [r7, #14]
8010520: 429a cmp r2, r3
8010522: d908 bls.n 8010536 <pbuf_remove_header+0x5a>
8010524: 4b12 ldr r3, [pc, #72] ; (8010570 <pbuf_remove_header+0x94>)
8010526: f240 2255 movw r2, #597 ; 0x255
801052a: 4914 ldr r1, [pc, #80] ; (801057c <pbuf_remove_header+0xa0>)
801052c: 4812 ldr r0, [pc, #72] ; (8010578 <pbuf_remove_header+0x9c>)
801052e: f00a fd71 bl 801b014 <iprintf>
8010532: 2301 movs r3, #1
8010534: e017 b.n 8010566 <pbuf_remove_header+0x8a>
/* remember current payload pointer */
payload = p->payload;
8010536: 687b ldr r3, [r7, #4]
8010538: 685b ldr r3, [r3, #4]
801053a: 60bb str r3, [r7, #8]
LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
/* increase payload pointer (guarded by length check above) */
p->payload = (u8_t *)p->payload + header_size_decrement;
801053c: 687b ldr r3, [r7, #4]
801053e: 685a ldr r2, [r3, #4]
8010540: 683b ldr r3, [r7, #0]
8010542: 441a add r2, r3
8010544: 687b ldr r3, [r7, #4]
8010546: 605a str r2, [r3, #4]
/* modify pbuf length fields */
p->len = (u16_t)(p->len - increment_magnitude);
8010548: 687b ldr r3, [r7, #4]
801054a: 895a ldrh r2, [r3, #10]
801054c: 89fb ldrh r3, [r7, #14]
801054e: 1ad3 subs r3, r2, r3
8010550: b29a uxth r2, r3
8010552: 687b ldr r3, [r7, #4]
8010554: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
8010556: 687b ldr r3, [r7, #4]
8010558: 891a ldrh r2, [r3, #8]
801055a: 89fb ldrh r3, [r7, #14]
801055c: 1ad3 subs r3, r2, r3
801055e: b29a uxth r2, r3
8010560: 687b ldr r3, [r7, #4]
8010562: 811a strh r2, [r3, #8]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
(void *)payload, (void *)p->payload, increment_magnitude));
return 0;
8010564: 2300 movs r3, #0
}
8010566: 4618 mov r0, r3
8010568: 3710 adds r7, #16
801056a: 46bd mov sp, r7
801056c: bd80 pop {r7, pc}
801056e: bf00 nop
8010570: 0801c648 .word 0x0801c648
8010574: 0801c7ac .word 0x0801c7ac
8010578: 0801c6a8 .word 0x0801c6a8
801057c: 0801c7b8 .word 0x0801c7b8
08010580 <pbuf_header_impl>:
static u8_t
pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
{
8010580: b580 push {r7, lr}
8010582: b082 sub sp, #8
8010584: af00 add r7, sp, #0
8010586: 6078 str r0, [r7, #4]
8010588: 460b mov r3, r1
801058a: 807b strh r3, [r7, #2]
801058c: 4613 mov r3, r2
801058e: 707b strb r3, [r7, #1]
if (header_size_increment < 0) {
8010590: f9b7 3002 ldrsh.w r3, [r7, #2]
8010594: 2b00 cmp r3, #0
8010596: da08 bge.n 80105aa <pbuf_header_impl+0x2a>
return pbuf_remove_header(p, (size_t) - header_size_increment);
8010598: f9b7 3002 ldrsh.w r3, [r7, #2]
801059c: 425b negs r3, r3
801059e: 4619 mov r1, r3
80105a0: 6878 ldr r0, [r7, #4]
80105a2: f7ff ff9b bl 80104dc <pbuf_remove_header>
80105a6: 4603 mov r3, r0
80105a8: e007 b.n 80105ba <pbuf_header_impl+0x3a>
} else {
return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
80105aa: f9b7 3002 ldrsh.w r3, [r7, #2]
80105ae: 787a ldrb r2, [r7, #1]
80105b0: 4619 mov r1, r3
80105b2: 6878 ldr r0, [r7, #4]
80105b4: f7ff ff1a bl 80103ec <pbuf_add_header_impl>
80105b8: 4603 mov r3, r0
}
}
80105ba: 4618 mov r0, r3
80105bc: 3708 adds r7, #8
80105be: 46bd mov sp, r7
80105c0: bd80 pop {r7, pc}
080105c2 <pbuf_header_force>:
* Same as pbuf_header but does not check if 'header_size > 0' is allowed.
* This is used internally only, to allow PBUF_REF for RX.
*/
u8_t
pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
{
80105c2: b580 push {r7, lr}
80105c4: b082 sub sp, #8
80105c6: af00 add r7, sp, #0
80105c8: 6078 str r0, [r7, #4]
80105ca: 460b mov r3, r1
80105cc: 807b strh r3, [r7, #2]
return pbuf_header_impl(p, header_size_increment, 1);
80105ce: f9b7 3002 ldrsh.w r3, [r7, #2]
80105d2: 2201 movs r2, #1
80105d4: 4619 mov r1, r3
80105d6: 6878 ldr r0, [r7, #4]
80105d8: f7ff ffd2 bl 8010580 <pbuf_header_impl>
80105dc: 4603 mov r3, r0
}
80105de: 4618 mov r0, r3
80105e0: 3708 adds r7, #8
80105e2: 46bd mov sp, r7
80105e4: bd80 pop {r7, pc}
...
080105e8 <pbuf_free>:
* 1->1->1 becomes .......
*
*/
u8_t
pbuf_free(struct pbuf *p)
{
80105e8: b580 push {r7, lr}
80105ea: b088 sub sp, #32
80105ec: af00 add r7, sp, #0
80105ee: 6078 str r0, [r7, #4]
u8_t alloc_src;
struct pbuf *q;
u8_t count;
if (p == NULL) {
80105f0: 687b ldr r3, [r7, #4]
80105f2: 2b00 cmp r3, #0
80105f4: d10b bne.n 801060e <pbuf_free+0x26>
LWIP_ASSERT("p != NULL", p != NULL);
80105f6: 687b ldr r3, [r7, #4]
80105f8: 2b00 cmp r3, #0
80105fa: d106 bne.n 801060a <pbuf_free+0x22>
80105fc: 4b3b ldr r3, [pc, #236] ; (80106ec <pbuf_free+0x104>)
80105fe: f44f 7237 mov.w r2, #732 ; 0x2dc
8010602: 493b ldr r1, [pc, #236] ; (80106f0 <pbuf_free+0x108>)
8010604: 483b ldr r0, [pc, #236] ; (80106f4 <pbuf_free+0x10c>)
8010606: f00a fd05 bl 801b014 <iprintf>
/* if assertions are disabled, proceed with debug output */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_free(p == NULL) was called.\n"));
return 0;
801060a: 2300 movs r3, #0
801060c: e069 b.n 80106e2 <pbuf_free+0xfa>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
PERF_START;
count = 0;
801060e: 2300 movs r3, #0
8010610: 77fb strb r3, [r7, #31]
/* de-allocate all consecutive pbufs from the head of the chain that
* obtain a zero reference count after decrementing*/
while (p != NULL) {
8010612: e062 b.n 80106da <pbuf_free+0xf2>
LWIP_PBUF_REF_T ref;
SYS_ARCH_DECL_PROTECT(old_level);
/* Since decrementing ref cannot be guaranteed to be a single machine operation
* we must protect it. We put the new ref into a local variable to prevent
* further protection. */
SYS_ARCH_PROTECT(old_level);
8010614: f00a fc9a bl 801af4c <sys_arch_protect>
8010618: 61b8 str r0, [r7, #24]
/* all pbufs in a chain are referenced at least once */
LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
801061a: 687b ldr r3, [r7, #4]
801061c: 7b9b ldrb r3, [r3, #14]
801061e: 2b00 cmp r3, #0
8010620: d106 bne.n 8010630 <pbuf_free+0x48>
8010622: 4b32 ldr r3, [pc, #200] ; (80106ec <pbuf_free+0x104>)
8010624: f240 22f1 movw r2, #753 ; 0x2f1
8010628: 4933 ldr r1, [pc, #204] ; (80106f8 <pbuf_free+0x110>)
801062a: 4832 ldr r0, [pc, #200] ; (80106f4 <pbuf_free+0x10c>)
801062c: f00a fcf2 bl 801b014 <iprintf>
/* decrease reference count (number of pointers to pbuf) */
ref = --(p->ref);
8010630: 687b ldr r3, [r7, #4]
8010632: 7b9b ldrb r3, [r3, #14]
8010634: 3b01 subs r3, #1
8010636: b2da uxtb r2, r3
8010638: 687b ldr r3, [r7, #4]
801063a: 739a strb r2, [r3, #14]
801063c: 687b ldr r3, [r7, #4]
801063e: 7b9b ldrb r3, [r3, #14]
8010640: 75fb strb r3, [r7, #23]
SYS_ARCH_UNPROTECT(old_level);
8010642: 69b8 ldr r0, [r7, #24]
8010644: f00a fc90 bl 801af68 <sys_arch_unprotect>
/* this pbuf is no longer referenced to? */
if (ref == 0) {
8010648: 7dfb ldrb r3, [r7, #23]
801064a: 2b00 cmp r3, #0
801064c: d143 bne.n 80106d6 <pbuf_free+0xee>
/* remember next pbuf in chain for next iteration */
q = p->next;
801064e: 687b ldr r3, [r7, #4]
8010650: 681b ldr r3, [r3, #0]
8010652: 613b str r3, [r7, #16]
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
alloc_src = pbuf_get_allocsrc(p);
8010654: 687b ldr r3, [r7, #4]
8010656: 7b1b ldrb r3, [r3, #12]
8010658: f003 030f and.w r3, r3, #15
801065c: 73fb strb r3, [r7, #15]
#if LWIP_SUPPORT_CUSTOM_PBUF
/* is this a custom pbuf? */
if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
801065e: 687b ldr r3, [r7, #4]
8010660: 7b5b ldrb r3, [r3, #13]
8010662: f003 0302 and.w r3, r3, #2
8010666: 2b00 cmp r3, #0
8010668: d011 beq.n 801068e <pbuf_free+0xa6>
struct pbuf_custom *pc = (struct pbuf_custom *)p;
801066a: 687b ldr r3, [r7, #4]
801066c: 60bb str r3, [r7, #8]
LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
801066e: 68bb ldr r3, [r7, #8]
8010670: 691b ldr r3, [r3, #16]
8010672: 2b00 cmp r3, #0
8010674: d106 bne.n 8010684 <pbuf_free+0x9c>
8010676: 4b1d ldr r3, [pc, #116] ; (80106ec <pbuf_free+0x104>)
8010678: f240 22ff movw r2, #767 ; 0x2ff
801067c: 491f ldr r1, [pc, #124] ; (80106fc <pbuf_free+0x114>)
801067e: 481d ldr r0, [pc, #116] ; (80106f4 <pbuf_free+0x10c>)
8010680: f00a fcc8 bl 801b014 <iprintf>
pc->custom_free_function(p);
8010684: 68bb ldr r3, [r7, #8]
8010686: 691b ldr r3, [r3, #16]
8010688: 6878 ldr r0, [r7, #4]
801068a: 4798 blx r3
801068c: e01d b.n 80106ca <pbuf_free+0xe2>
} else
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
{
/* is this a pbuf from the pool? */
if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
801068e: 7bfb ldrb r3, [r7, #15]
8010690: 2b02 cmp r3, #2
8010692: d104 bne.n 801069e <pbuf_free+0xb6>
memp_free(MEMP_PBUF_POOL, p);
8010694: 6879 ldr r1, [r7, #4]
8010696: 200c movs r0, #12
8010698: f7ff f8fa bl 800f890 <memp_free>
801069c: e015 b.n 80106ca <pbuf_free+0xe2>
/* is this a ROM or RAM referencing pbuf? */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
801069e: 7bfb ldrb r3, [r7, #15]
80106a0: 2b01 cmp r3, #1
80106a2: d104 bne.n 80106ae <pbuf_free+0xc6>
memp_free(MEMP_PBUF, p);
80106a4: 6879 ldr r1, [r7, #4]
80106a6: 200b movs r0, #11
80106a8: f7ff f8f2 bl 800f890 <memp_free>
80106ac: e00d b.n 80106ca <pbuf_free+0xe2>
/* type == PBUF_RAM */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
80106ae: 7bfb ldrb r3, [r7, #15]
80106b0: 2b00 cmp r3, #0
80106b2: d103 bne.n 80106bc <pbuf_free+0xd4>
mem_free(p);
80106b4: 6878 ldr r0, [r7, #4]
80106b6: f7fe fd7d bl 800f1b4 <mem_free>
80106ba: e006 b.n 80106ca <pbuf_free+0xe2>
} else {
/* @todo: support freeing other types */
LWIP_ASSERT("invalid pbuf type", 0);
80106bc: 4b0b ldr r3, [pc, #44] ; (80106ec <pbuf_free+0x104>)
80106be: f240 320f movw r2, #783 ; 0x30f
80106c2: 490f ldr r1, [pc, #60] ; (8010700 <pbuf_free+0x118>)
80106c4: 480b ldr r0, [pc, #44] ; (80106f4 <pbuf_free+0x10c>)
80106c6: f00a fca5 bl 801b014 <iprintf>
}
}
count++;
80106ca: 7ffb ldrb r3, [r7, #31]
80106cc: 3301 adds r3, #1
80106ce: 77fb strb r3, [r7, #31]
/* proceed to next pbuf */
p = q;
80106d0: 693b ldr r3, [r7, #16]
80106d2: 607b str r3, [r7, #4]
80106d4: e001 b.n 80106da <pbuf_free+0xf2>
/* p->ref > 0, this pbuf is still referenced to */
/* (and so the remaining pbufs in chain as well) */
} else {
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
/* stop walking through the chain */
p = NULL;
80106d6: 2300 movs r3, #0
80106d8: 607b str r3, [r7, #4]
while (p != NULL) {
80106da: 687b ldr r3, [r7, #4]
80106dc: 2b00 cmp r3, #0
80106de: d199 bne.n 8010614 <pbuf_free+0x2c>
}
}
PERF_STOP("pbuf_free");
/* return number of de-allocated pbufs */
return count;
80106e0: 7ffb ldrb r3, [r7, #31]
}
80106e2: 4618 mov r0, r3
80106e4: 3720 adds r7, #32
80106e6: 46bd mov sp, r7
80106e8: bd80 pop {r7, pc}
80106ea: bf00 nop
80106ec: 0801c648 .word 0x0801c648
80106f0: 0801c7ac .word 0x0801c7ac
80106f4: 0801c6a8 .word 0x0801c6a8
80106f8: 0801c7d8 .word 0x0801c7d8
80106fc: 0801c7f0 .word 0x0801c7f0
8010700: 0801c814 .word 0x0801c814
08010704 <pbuf_clen>:
* @param p first pbuf of chain
* @return the number of pbufs in a chain
*/
u16_t
pbuf_clen(const struct pbuf *p)
{
8010704: b480 push {r7}
8010706: b085 sub sp, #20
8010708: af00 add r7, sp, #0
801070a: 6078 str r0, [r7, #4]
u16_t len;
len = 0;
801070c: 2300 movs r3, #0
801070e: 81fb strh r3, [r7, #14]
while (p != NULL) {
8010710: e005 b.n 801071e <pbuf_clen+0x1a>
++len;
8010712: 89fb ldrh r3, [r7, #14]
8010714: 3301 adds r3, #1
8010716: 81fb strh r3, [r7, #14]
p = p->next;
8010718: 687b ldr r3, [r7, #4]
801071a: 681b ldr r3, [r3, #0]
801071c: 607b str r3, [r7, #4]
while (p != NULL) {
801071e: 687b ldr r3, [r7, #4]
8010720: 2b00 cmp r3, #0
8010722: d1f6 bne.n 8010712 <pbuf_clen+0xe>
}
return len;
8010724: 89fb ldrh r3, [r7, #14]
}
8010726: 4618 mov r0, r3
8010728: 3714 adds r7, #20
801072a: 46bd mov sp, r7
801072c: f85d 7b04 ldr.w r7, [sp], #4
8010730: 4770 bx lr
...
08010734 <pbuf_ref>:
* @param p pbuf to increase reference counter of
*
*/
void
pbuf_ref(struct pbuf *p)
{
8010734: b580 push {r7, lr}
8010736: b084 sub sp, #16
8010738: af00 add r7, sp, #0
801073a: 6078 str r0, [r7, #4]
/* pbuf given? */
if (p != NULL) {
801073c: 687b ldr r3, [r7, #4]
801073e: 2b00 cmp r3, #0
8010740: d016 beq.n 8010770 <pbuf_ref+0x3c>
SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
8010742: f00a fc03 bl 801af4c <sys_arch_protect>
8010746: 60f8 str r0, [r7, #12]
8010748: 687b ldr r3, [r7, #4]
801074a: 7b9b ldrb r3, [r3, #14]
801074c: 3301 adds r3, #1
801074e: b2da uxtb r2, r3
8010750: 687b ldr r3, [r7, #4]
8010752: 739a strb r2, [r3, #14]
8010754: 68f8 ldr r0, [r7, #12]
8010756: f00a fc07 bl 801af68 <sys_arch_unprotect>
LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
801075a: 687b ldr r3, [r7, #4]
801075c: 7b9b ldrb r3, [r3, #14]
801075e: 2b00 cmp r3, #0
8010760: d106 bne.n 8010770 <pbuf_ref+0x3c>
8010762: 4b05 ldr r3, [pc, #20] ; (8010778 <pbuf_ref+0x44>)
8010764: f240 3242 movw r2, #834 ; 0x342
8010768: 4904 ldr r1, [pc, #16] ; (801077c <pbuf_ref+0x48>)
801076a: 4805 ldr r0, [pc, #20] ; (8010780 <pbuf_ref+0x4c>)
801076c: f00a fc52 bl 801b014 <iprintf>
}
}
8010770: bf00 nop
8010772: 3710 adds r7, #16
8010774: 46bd mov sp, r7
8010776: bd80 pop {r7, pc}
8010778: 0801c648 .word 0x0801c648
801077c: 0801c828 .word 0x0801c828
8010780: 0801c6a8 .word 0x0801c6a8
08010784 <pbuf_cat>:
*
* @see pbuf_chain()
*/
void
pbuf_cat(struct pbuf *h, struct pbuf *t)
{
8010784: b580 push {r7, lr}
8010786: b084 sub sp, #16
8010788: af00 add r7, sp, #0
801078a: 6078 str r0, [r7, #4]
801078c: 6039 str r1, [r7, #0]
struct pbuf *p;
LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
801078e: 687b ldr r3, [r7, #4]
8010790: 2b00 cmp r3, #0
8010792: d002 beq.n 801079a <pbuf_cat+0x16>
8010794: 683b ldr r3, [r7, #0]
8010796: 2b00 cmp r3, #0
8010798: d107 bne.n 80107aa <pbuf_cat+0x26>
801079a: 4b20 ldr r3, [pc, #128] ; (801081c <pbuf_cat+0x98>)
801079c: f240 325a movw r2, #858 ; 0x35a
80107a0: 491f ldr r1, [pc, #124] ; (8010820 <pbuf_cat+0x9c>)
80107a2: 4820 ldr r0, [pc, #128] ; (8010824 <pbuf_cat+0xa0>)
80107a4: f00a fc36 bl 801b014 <iprintf>
80107a8: e034 b.n 8010814 <pbuf_cat+0x90>
((h != NULL) && (t != NULL)), return;);
/* proceed to last pbuf of chain */
for (p = h; p->next != NULL; p = p->next) {
80107aa: 687b ldr r3, [r7, #4]
80107ac: 60fb str r3, [r7, #12]
80107ae: e00a b.n 80107c6 <pbuf_cat+0x42>
/* add total length of second chain to all totals of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
80107b0: 68fb ldr r3, [r7, #12]
80107b2: 891a ldrh r2, [r3, #8]
80107b4: 683b ldr r3, [r7, #0]
80107b6: 891b ldrh r3, [r3, #8]
80107b8: 4413 add r3, r2
80107ba: b29a uxth r2, r3
80107bc: 68fb ldr r3, [r7, #12]
80107be: 811a strh r2, [r3, #8]
for (p = h; p->next != NULL; p = p->next) {
80107c0: 68fb ldr r3, [r7, #12]
80107c2: 681b ldr r3, [r3, #0]
80107c4: 60fb str r3, [r7, #12]
80107c6: 68fb ldr r3, [r7, #12]
80107c8: 681b ldr r3, [r3, #0]
80107ca: 2b00 cmp r3, #0
80107cc: d1f0 bne.n 80107b0 <pbuf_cat+0x2c>
}
/* { p is last pbuf of first h chain, p->next == NULL } */
LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
80107ce: 68fb ldr r3, [r7, #12]
80107d0: 891a ldrh r2, [r3, #8]
80107d2: 68fb ldr r3, [r7, #12]
80107d4: 895b ldrh r3, [r3, #10]
80107d6: 429a cmp r2, r3
80107d8: d006 beq.n 80107e8 <pbuf_cat+0x64>
80107da: 4b10 ldr r3, [pc, #64] ; (801081c <pbuf_cat+0x98>)
80107dc: f240 3262 movw r2, #866 ; 0x362
80107e0: 4911 ldr r1, [pc, #68] ; (8010828 <pbuf_cat+0xa4>)
80107e2: 4810 ldr r0, [pc, #64] ; (8010824 <pbuf_cat+0xa0>)
80107e4: f00a fc16 bl 801b014 <iprintf>
LWIP_ASSERT("p->next == NULL", p->next == NULL);
80107e8: 68fb ldr r3, [r7, #12]
80107ea: 681b ldr r3, [r3, #0]
80107ec: 2b00 cmp r3, #0
80107ee: d006 beq.n 80107fe <pbuf_cat+0x7a>
80107f0: 4b0a ldr r3, [pc, #40] ; (801081c <pbuf_cat+0x98>)
80107f2: f240 3263 movw r2, #867 ; 0x363
80107f6: 490d ldr r1, [pc, #52] ; (801082c <pbuf_cat+0xa8>)
80107f8: 480a ldr r0, [pc, #40] ; (8010824 <pbuf_cat+0xa0>)
80107fa: f00a fc0b bl 801b014 <iprintf>
/* add total length of second chain to last pbuf total of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
80107fe: 68fb ldr r3, [r7, #12]
8010800: 891a ldrh r2, [r3, #8]
8010802: 683b ldr r3, [r7, #0]
8010804: 891b ldrh r3, [r3, #8]
8010806: 4413 add r3, r2
8010808: b29a uxth r2, r3
801080a: 68fb ldr r3, [r7, #12]
801080c: 811a strh r2, [r3, #8]
/* chain last pbuf of head (p) with first of tail (t) */
p->next = t;
801080e: 68fb ldr r3, [r7, #12]
8010810: 683a ldr r2, [r7, #0]
8010812: 601a str r2, [r3, #0]
/* p->next now references t, but the caller will drop its reference to t,
* so netto there is no change to the reference count of t.
*/
}
8010814: 3710 adds r7, #16
8010816: 46bd mov sp, r7
8010818: bd80 pop {r7, pc}
801081a: bf00 nop
801081c: 0801c648 .word 0x0801c648
8010820: 0801c83c .word 0x0801c83c
8010824: 0801c6a8 .word 0x0801c6a8
8010828: 0801c874 .word 0x0801c874
801082c: 0801c8a4 .word 0x0801c8a4
08010830 <pbuf_chain>:
* The ->ref field of the first pbuf of the tail chain is adjusted.
*
*/
void
pbuf_chain(struct pbuf *h, struct pbuf *t)
{
8010830: b580 push {r7, lr}
8010832: b082 sub sp, #8
8010834: af00 add r7, sp, #0
8010836: 6078 str r0, [r7, #4]
8010838: 6039 str r1, [r7, #0]
pbuf_cat(h, t);
801083a: 6839 ldr r1, [r7, #0]
801083c: 6878 ldr r0, [r7, #4]
801083e: f7ff ffa1 bl 8010784 <pbuf_cat>
/* t is now referenced by h */
pbuf_ref(t);
8010842: 6838 ldr r0, [r7, #0]
8010844: f7ff ff76 bl 8010734 <pbuf_ref>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
}
8010848: bf00 nop
801084a: 3708 adds r7, #8
801084c: 46bd mov sp, r7
801084e: bd80 pop {r7, pc}
08010850 <pbuf_copy>:
* ERR_ARG if one of the pbufs is NULL or p_to is not big
* enough to hold p_from
*/
err_t
pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
{
8010850: b580 push {r7, lr}
8010852: b086 sub sp, #24
8010854: af00 add r7, sp, #0
8010856: 6078 str r0, [r7, #4]
8010858: 6039 str r1, [r7, #0]
size_t offset_to = 0, offset_from = 0, len;
801085a: 2300 movs r3, #0
801085c: 617b str r3, [r7, #20]
801085e: 2300 movs r3, #0
8010860: 613b str r3, [r7, #16]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
(const void *)p_to, (const void *)p_from));
/* is the target big enough to hold the source? */
LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
8010862: 687b ldr r3, [r7, #4]
8010864: 2b00 cmp r3, #0
8010866: d008 beq.n 801087a <pbuf_copy+0x2a>
8010868: 683b ldr r3, [r7, #0]
801086a: 2b00 cmp r3, #0
801086c: d005 beq.n 801087a <pbuf_copy+0x2a>
801086e: 687b ldr r3, [r7, #4]
8010870: 891a ldrh r2, [r3, #8]
8010872: 683b ldr r3, [r7, #0]
8010874: 891b ldrh r3, [r3, #8]
8010876: 429a cmp r2, r3
8010878: d209 bcs.n 801088e <pbuf_copy+0x3e>
801087a: 4b57 ldr r3, [pc, #348] ; (80109d8 <pbuf_copy+0x188>)
801087c: f240 32ca movw r2, #970 ; 0x3ca
8010880: 4956 ldr r1, [pc, #344] ; (80109dc <pbuf_copy+0x18c>)
8010882: 4857 ldr r0, [pc, #348] ; (80109e0 <pbuf_copy+0x190>)
8010884: f00a fbc6 bl 801b014 <iprintf>
8010888: f06f 030f mvn.w r3, #15
801088c: e09f b.n 80109ce <pbuf_copy+0x17e>
(p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
/* iterate through pbuf chain */
do {
/* copy one part of the original chain */
if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
801088e: 687b ldr r3, [r7, #4]
8010890: 895b ldrh r3, [r3, #10]
8010892: 461a mov r2, r3
8010894: 697b ldr r3, [r7, #20]
8010896: 1ad2 subs r2, r2, r3
8010898: 683b ldr r3, [r7, #0]
801089a: 895b ldrh r3, [r3, #10]
801089c: 4619 mov r1, r3
801089e: 693b ldr r3, [r7, #16]
80108a0: 1acb subs r3, r1, r3
80108a2: 429a cmp r2, r3
80108a4: d306 bcc.n 80108b4 <pbuf_copy+0x64>
/* complete current p_from fits into current p_to */
len = p_from->len - offset_from;
80108a6: 683b ldr r3, [r7, #0]
80108a8: 895b ldrh r3, [r3, #10]
80108aa: 461a mov r2, r3
80108ac: 693b ldr r3, [r7, #16]
80108ae: 1ad3 subs r3, r2, r3
80108b0: 60fb str r3, [r7, #12]
80108b2: e005 b.n 80108c0 <pbuf_copy+0x70>
} else {
/* current p_from does not fit into current p_to */
len = p_to->len - offset_to;
80108b4: 687b ldr r3, [r7, #4]
80108b6: 895b ldrh r3, [r3, #10]
80108b8: 461a mov r2, r3
80108ba: 697b ldr r3, [r7, #20]
80108bc: 1ad3 subs r3, r2, r3
80108be: 60fb str r3, [r7, #12]
}
MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
80108c0: 687b ldr r3, [r7, #4]
80108c2: 685a ldr r2, [r3, #4]
80108c4: 697b ldr r3, [r7, #20]
80108c6: 18d0 adds r0, r2, r3
80108c8: 683b ldr r3, [r7, #0]
80108ca: 685a ldr r2, [r3, #4]
80108cc: 693b ldr r3, [r7, #16]
80108ce: 4413 add r3, r2
80108d0: 68fa ldr r2, [r7, #12]
80108d2: 4619 mov r1, r3
80108d4: f00a fb8b bl 801afee <memcpy>
offset_to += len;
80108d8: 697a ldr r2, [r7, #20]
80108da: 68fb ldr r3, [r7, #12]
80108dc: 4413 add r3, r2
80108de: 617b str r3, [r7, #20]
offset_from += len;
80108e0: 693a ldr r2, [r7, #16]
80108e2: 68fb ldr r3, [r7, #12]
80108e4: 4413 add r3, r2
80108e6: 613b str r3, [r7, #16]
LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
80108e8: 687b ldr r3, [r7, #4]
80108ea: 895b ldrh r3, [r3, #10]
80108ec: 461a mov r2, r3
80108ee: 697b ldr r3, [r7, #20]
80108f0: 4293 cmp r3, r2
80108f2: d906 bls.n 8010902 <pbuf_copy+0xb2>
80108f4: 4b38 ldr r3, [pc, #224] ; (80109d8 <pbuf_copy+0x188>)
80108f6: f240 32d9 movw r2, #985 ; 0x3d9
80108fa: 493a ldr r1, [pc, #232] ; (80109e4 <pbuf_copy+0x194>)
80108fc: 4838 ldr r0, [pc, #224] ; (80109e0 <pbuf_copy+0x190>)
80108fe: f00a fb89 bl 801b014 <iprintf>
LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
8010902: 683b ldr r3, [r7, #0]
8010904: 895b ldrh r3, [r3, #10]
8010906: 461a mov r2, r3
8010908: 693b ldr r3, [r7, #16]
801090a: 4293 cmp r3, r2
801090c: d906 bls.n 801091c <pbuf_copy+0xcc>
801090e: 4b32 ldr r3, [pc, #200] ; (80109d8 <pbuf_copy+0x188>)
8010910: f240 32da movw r2, #986 ; 0x3da
8010914: 4934 ldr r1, [pc, #208] ; (80109e8 <pbuf_copy+0x198>)
8010916: 4832 ldr r0, [pc, #200] ; (80109e0 <pbuf_copy+0x190>)
8010918: f00a fb7c bl 801b014 <iprintf>
if (offset_from >= p_from->len) {
801091c: 683b ldr r3, [r7, #0]
801091e: 895b ldrh r3, [r3, #10]
8010920: 461a mov r2, r3
8010922: 693b ldr r3, [r7, #16]
8010924: 4293 cmp r3, r2
8010926: d304 bcc.n 8010932 <pbuf_copy+0xe2>
/* on to next p_from (if any) */
offset_from = 0;
8010928: 2300 movs r3, #0
801092a: 613b str r3, [r7, #16]
p_from = p_from->next;
801092c: 683b ldr r3, [r7, #0]
801092e: 681b ldr r3, [r3, #0]
8010930: 603b str r3, [r7, #0]
}
if (offset_to == p_to->len) {
8010932: 687b ldr r3, [r7, #4]
8010934: 895b ldrh r3, [r3, #10]
8010936: 461a mov r2, r3
8010938: 697b ldr r3, [r7, #20]
801093a: 4293 cmp r3, r2
801093c: d114 bne.n 8010968 <pbuf_copy+0x118>
/* on to next p_to (if any) */
offset_to = 0;
801093e: 2300 movs r3, #0
8010940: 617b str r3, [r7, #20]
p_to = p_to->next;
8010942: 687b ldr r3, [r7, #4]
8010944: 681b ldr r3, [r3, #0]
8010946: 607b str r3, [r7, #4]
LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
8010948: 687b ldr r3, [r7, #4]
801094a: 2b00 cmp r3, #0
801094c: d10c bne.n 8010968 <pbuf_copy+0x118>
801094e: 683b ldr r3, [r7, #0]
8010950: 2b00 cmp r3, #0
8010952: d009 beq.n 8010968 <pbuf_copy+0x118>
8010954: 4b20 ldr r3, [pc, #128] ; (80109d8 <pbuf_copy+0x188>)
8010956: f44f 7279 mov.w r2, #996 ; 0x3e4
801095a: 4924 ldr r1, [pc, #144] ; (80109ec <pbuf_copy+0x19c>)
801095c: 4820 ldr r0, [pc, #128] ; (80109e0 <pbuf_copy+0x190>)
801095e: f00a fb59 bl 801b014 <iprintf>
8010962: f06f 030f mvn.w r3, #15
8010966: e032 b.n 80109ce <pbuf_copy+0x17e>
}
if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
8010968: 683b ldr r3, [r7, #0]
801096a: 2b00 cmp r3, #0
801096c: d013 beq.n 8010996 <pbuf_copy+0x146>
801096e: 683b ldr r3, [r7, #0]
8010970: 895a ldrh r2, [r3, #10]
8010972: 683b ldr r3, [r7, #0]
8010974: 891b ldrh r3, [r3, #8]
8010976: 429a cmp r2, r3
8010978: d10d bne.n 8010996 <pbuf_copy+0x146>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
801097a: 683b ldr r3, [r7, #0]
801097c: 681b ldr r3, [r3, #0]
801097e: 2b00 cmp r3, #0
8010980: d009 beq.n 8010996 <pbuf_copy+0x146>
8010982: 4b15 ldr r3, [pc, #84] ; (80109d8 <pbuf_copy+0x188>)
8010984: f240 32ea movw r2, #1002 ; 0x3ea
8010988: 4919 ldr r1, [pc, #100] ; (80109f0 <pbuf_copy+0x1a0>)
801098a: 4815 ldr r0, [pc, #84] ; (80109e0 <pbuf_copy+0x190>)
801098c: f00a fb42 bl 801b014 <iprintf>
8010990: f06f 0305 mvn.w r3, #5
8010994: e01b b.n 80109ce <pbuf_copy+0x17e>
(p_from->next == NULL), return ERR_VAL;);
}
if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
8010996: 687b ldr r3, [r7, #4]
8010998: 2b00 cmp r3, #0
801099a: d013 beq.n 80109c4 <pbuf_copy+0x174>
801099c: 687b ldr r3, [r7, #4]
801099e: 895a ldrh r2, [r3, #10]
80109a0: 687b ldr r3, [r7, #4]
80109a2: 891b ldrh r3, [r3, #8]
80109a4: 429a cmp r2, r3
80109a6: d10d bne.n 80109c4 <pbuf_copy+0x174>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
80109a8: 687b ldr r3, [r7, #4]
80109aa: 681b ldr r3, [r3, #0]
80109ac: 2b00 cmp r3, #0
80109ae: d009 beq.n 80109c4 <pbuf_copy+0x174>
80109b0: 4b09 ldr r3, [pc, #36] ; (80109d8 <pbuf_copy+0x188>)
80109b2: f240 32ef movw r2, #1007 ; 0x3ef
80109b6: 490e ldr r1, [pc, #56] ; (80109f0 <pbuf_copy+0x1a0>)
80109b8: 4809 ldr r0, [pc, #36] ; (80109e0 <pbuf_copy+0x190>)
80109ba: f00a fb2b bl 801b014 <iprintf>
80109be: f06f 0305 mvn.w r3, #5
80109c2: e004 b.n 80109ce <pbuf_copy+0x17e>
(p_to->next == NULL), return ERR_VAL;);
}
} while (p_from);
80109c4: 683b ldr r3, [r7, #0]
80109c6: 2b00 cmp r3, #0
80109c8: f47f af61 bne.w 801088e <pbuf_copy+0x3e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
return ERR_OK;
80109cc: 2300 movs r3, #0
}
80109ce: 4618 mov r0, r3
80109d0: 3718 adds r7, #24
80109d2: 46bd mov sp, r7
80109d4: bd80 pop {r7, pc}
80109d6: bf00 nop
80109d8: 0801c648 .word 0x0801c648
80109dc: 0801c8f0 .word 0x0801c8f0
80109e0: 0801c6a8 .word 0x0801c6a8
80109e4: 0801c920 .word 0x0801c920
80109e8: 0801c938 .word 0x0801c938
80109ec: 0801c954 .word 0x0801c954
80109f0: 0801c964 .word 0x0801c964
080109f4 <pbuf_copy_partial>:
* @param offset offset into the packet buffer from where to begin copying len bytes
* @return the number of bytes copied, or 0 on failure
*/
u16_t
pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
{
80109f4: b580 push {r7, lr}
80109f6: b088 sub sp, #32
80109f8: af00 add r7, sp, #0
80109fa: 60f8 str r0, [r7, #12]
80109fc: 60b9 str r1, [r7, #8]
80109fe: 4611 mov r1, r2
8010a00: 461a mov r2, r3
8010a02: 460b mov r3, r1
8010a04: 80fb strh r3, [r7, #6]
8010a06: 4613 mov r3, r2
8010a08: 80bb strh r3, [r7, #4]
const struct pbuf *p;
u16_t left = 0;
8010a0a: 2300 movs r3, #0
8010a0c: 837b strh r3, [r7, #26]
u16_t buf_copy_len;
u16_t copied_total = 0;
8010a0e: 2300 movs r3, #0
8010a10: 82fb strh r3, [r7, #22]
LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
8010a12: 68fb ldr r3, [r7, #12]
8010a14: 2b00 cmp r3, #0
8010a16: d108 bne.n 8010a2a <pbuf_copy_partial+0x36>
8010a18: 4b2b ldr r3, [pc, #172] ; (8010ac8 <pbuf_copy_partial+0xd4>)
8010a1a: f240 420a movw r2, #1034 ; 0x40a
8010a1e: 492b ldr r1, [pc, #172] ; (8010acc <pbuf_copy_partial+0xd8>)
8010a20: 482b ldr r0, [pc, #172] ; (8010ad0 <pbuf_copy_partial+0xdc>)
8010a22: f00a faf7 bl 801b014 <iprintf>
8010a26: 2300 movs r3, #0
8010a28: e04a b.n 8010ac0 <pbuf_copy_partial+0xcc>
LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
8010a2a: 68bb ldr r3, [r7, #8]
8010a2c: 2b00 cmp r3, #0
8010a2e: d108 bne.n 8010a42 <pbuf_copy_partial+0x4e>
8010a30: 4b25 ldr r3, [pc, #148] ; (8010ac8 <pbuf_copy_partial+0xd4>)
8010a32: f240 420b movw r2, #1035 ; 0x40b
8010a36: 4927 ldr r1, [pc, #156] ; (8010ad4 <pbuf_copy_partial+0xe0>)
8010a38: 4825 ldr r0, [pc, #148] ; (8010ad0 <pbuf_copy_partial+0xdc>)
8010a3a: f00a faeb bl 801b014 <iprintf>
8010a3e: 2300 movs r3, #0
8010a40: e03e b.n 8010ac0 <pbuf_copy_partial+0xcc>
/* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010a42: 68fb ldr r3, [r7, #12]
8010a44: 61fb str r3, [r7, #28]
8010a46: e034 b.n 8010ab2 <pbuf_copy_partial+0xbe>
if ((offset != 0) && (offset >= p->len)) {
8010a48: 88bb ldrh r3, [r7, #4]
8010a4a: 2b00 cmp r3, #0
8010a4c: d00a beq.n 8010a64 <pbuf_copy_partial+0x70>
8010a4e: 69fb ldr r3, [r7, #28]
8010a50: 895b ldrh r3, [r3, #10]
8010a52: 88ba ldrh r2, [r7, #4]
8010a54: 429a cmp r2, r3
8010a56: d305 bcc.n 8010a64 <pbuf_copy_partial+0x70>
/* don't copy from this buffer -> on to the next */
offset = (u16_t)(offset - p->len);
8010a58: 69fb ldr r3, [r7, #28]
8010a5a: 895b ldrh r3, [r3, #10]
8010a5c: 88ba ldrh r2, [r7, #4]
8010a5e: 1ad3 subs r3, r2, r3
8010a60: 80bb strh r3, [r7, #4]
8010a62: e023 b.n 8010aac <pbuf_copy_partial+0xb8>
} else {
/* copy from this buffer. maybe only partially. */
buf_copy_len = (u16_t)(p->len - offset);
8010a64: 69fb ldr r3, [r7, #28]
8010a66: 895a ldrh r2, [r3, #10]
8010a68: 88bb ldrh r3, [r7, #4]
8010a6a: 1ad3 subs r3, r2, r3
8010a6c: 833b strh r3, [r7, #24]
if (buf_copy_len > len) {
8010a6e: 8b3a ldrh r2, [r7, #24]
8010a70: 88fb ldrh r3, [r7, #6]
8010a72: 429a cmp r2, r3
8010a74: d901 bls.n 8010a7a <pbuf_copy_partial+0x86>
buf_copy_len = len;
8010a76: 88fb ldrh r3, [r7, #6]
8010a78: 833b strh r3, [r7, #24]
}
/* copy the necessary parts of the buffer */
MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
8010a7a: 8b7b ldrh r3, [r7, #26]
8010a7c: 68ba ldr r2, [r7, #8]
8010a7e: 18d0 adds r0, r2, r3
8010a80: 69fb ldr r3, [r7, #28]
8010a82: 685a ldr r2, [r3, #4]
8010a84: 88bb ldrh r3, [r7, #4]
8010a86: 4413 add r3, r2
8010a88: 8b3a ldrh r2, [r7, #24]
8010a8a: 4619 mov r1, r3
8010a8c: f00a faaf bl 801afee <memcpy>
copied_total = (u16_t)(copied_total + buf_copy_len);
8010a90: 8afa ldrh r2, [r7, #22]
8010a92: 8b3b ldrh r3, [r7, #24]
8010a94: 4413 add r3, r2
8010a96: 82fb strh r3, [r7, #22]
left = (u16_t)(left + buf_copy_len);
8010a98: 8b7a ldrh r2, [r7, #26]
8010a9a: 8b3b ldrh r3, [r7, #24]
8010a9c: 4413 add r3, r2
8010a9e: 837b strh r3, [r7, #26]
len = (u16_t)(len - buf_copy_len);
8010aa0: 88fa ldrh r2, [r7, #6]
8010aa2: 8b3b ldrh r3, [r7, #24]
8010aa4: 1ad3 subs r3, r2, r3
8010aa6: 80fb strh r3, [r7, #6]
offset = 0;
8010aa8: 2300 movs r3, #0
8010aaa: 80bb strh r3, [r7, #4]
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010aac: 69fb ldr r3, [r7, #28]
8010aae: 681b ldr r3, [r3, #0]
8010ab0: 61fb str r3, [r7, #28]
8010ab2: 88fb ldrh r3, [r7, #6]
8010ab4: 2b00 cmp r3, #0
8010ab6: d002 beq.n 8010abe <pbuf_copy_partial+0xca>
8010ab8: 69fb ldr r3, [r7, #28]
8010aba: 2b00 cmp r3, #0
8010abc: d1c4 bne.n 8010a48 <pbuf_copy_partial+0x54>
}
}
return copied_total;
8010abe: 8afb ldrh r3, [r7, #22]
}
8010ac0: 4618 mov r0, r3
8010ac2: 3720 adds r7, #32
8010ac4: 46bd mov sp, r7
8010ac6: bd80 pop {r7, pc}
8010ac8: 0801c648 .word 0x0801c648
8010acc: 0801c990 .word 0x0801c990
8010ad0: 0801c6a8 .word 0x0801c6a8
8010ad4: 0801c9b0 .word 0x0801c9b0
08010ad8 <pbuf_clone>:
*
* @return a new pbuf or NULL if allocation fails
*/
struct pbuf *
pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
{
8010ad8: b580 push {r7, lr}
8010ada: b084 sub sp, #16
8010adc: af00 add r7, sp, #0
8010ade: 4603 mov r3, r0
8010ae0: 603a str r2, [r7, #0]
8010ae2: 71fb strb r3, [r7, #7]
8010ae4: 460b mov r3, r1
8010ae6: 80bb strh r3, [r7, #4]
struct pbuf *q;
err_t err;
q = pbuf_alloc(layer, p->tot_len, type);
8010ae8: 683b ldr r3, [r7, #0]
8010aea: 8919 ldrh r1, [r3, #8]
8010aec: 88ba ldrh r2, [r7, #4]
8010aee: 79fb ldrb r3, [r7, #7]
8010af0: 4618 mov r0, r3
8010af2: f7ff fa99 bl 8010028 <pbuf_alloc>
8010af6: 60f8 str r0, [r7, #12]
if (q == NULL) {
8010af8: 68fb ldr r3, [r7, #12]
8010afa: 2b00 cmp r3, #0
8010afc: d101 bne.n 8010b02 <pbuf_clone+0x2a>
return NULL;
8010afe: 2300 movs r3, #0
8010b00: e011 b.n 8010b26 <pbuf_clone+0x4e>
}
err = pbuf_copy(q, p);
8010b02: 6839 ldr r1, [r7, #0]
8010b04: 68f8 ldr r0, [r7, #12]
8010b06: f7ff fea3 bl 8010850 <pbuf_copy>
8010b0a: 4603 mov r3, r0
8010b0c: 72fb strb r3, [r7, #11]
LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
8010b0e: f997 300b ldrsb.w r3, [r7, #11]
8010b12: 2b00 cmp r3, #0
8010b14: d006 beq.n 8010b24 <pbuf_clone+0x4c>
8010b16: 4b06 ldr r3, [pc, #24] ; (8010b30 <pbuf_clone+0x58>)
8010b18: f240 5224 movw r2, #1316 ; 0x524
8010b1c: 4905 ldr r1, [pc, #20] ; (8010b34 <pbuf_clone+0x5c>)
8010b1e: 4806 ldr r0, [pc, #24] ; (8010b38 <pbuf_clone+0x60>)
8010b20: f00a fa78 bl 801b014 <iprintf>
return q;
8010b24: 68fb ldr r3, [r7, #12]
}
8010b26: 4618 mov r0, r3
8010b28: 3710 adds r7, #16
8010b2a: 46bd mov sp, r7
8010b2c: bd80 pop {r7, pc}
8010b2e: bf00 nop
8010b30: 0801c648 .word 0x0801c648
8010b34: 0801cabc .word 0x0801cabc
8010b38: 0801c6a8 .word 0x0801c6a8
08010b3c <tcp_init>:
/**
* Initialize this module.
*/
void
tcp_init(void)
{
8010b3c: b580 push {r7, lr}
8010b3e: af00 add r7, sp, #0
#ifdef LWIP_RAND
tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
8010b40: f00a fa80 bl 801b044 <rand>
8010b44: 4603 mov r3, r0
8010b46: b29b uxth r3, r3
8010b48: f3c3 030d ubfx r3, r3, #0, #14
8010b4c: b29b uxth r3, r3
8010b4e: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
8010b52: b29a uxth r2, r3
8010b54: 4b01 ldr r3, [pc, #4] ; (8010b5c <tcp_init+0x20>)
8010b56: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
8010b58: bf00 nop
8010b5a: bd80 pop {r7, pc}
8010b5c: 20000074 .word 0x20000074
08010b60 <tcp_free>:
/** Free a tcp pcb */
void
tcp_free(struct tcp_pcb *pcb)
{
8010b60: b580 push {r7, lr}
8010b62: b082 sub sp, #8
8010b64: af00 add r7, sp, #0
8010b66: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
8010b68: 687b ldr r3, [r7, #4]
8010b6a: 7d1b ldrb r3, [r3, #20]
8010b6c: 2b01 cmp r3, #1
8010b6e: d105 bne.n 8010b7c <tcp_free+0x1c>
8010b70: 4b06 ldr r3, [pc, #24] ; (8010b8c <tcp_free+0x2c>)
8010b72: 22d4 movs r2, #212 ; 0xd4
8010b74: 4906 ldr r1, [pc, #24] ; (8010b90 <tcp_free+0x30>)
8010b76: 4807 ldr r0, [pc, #28] ; (8010b94 <tcp_free+0x34>)
8010b78: f00a fa4c bl 801b014 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB, pcb);
8010b7c: 6879 ldr r1, [r7, #4]
8010b7e: 2001 movs r0, #1
8010b80: f7fe fe86 bl 800f890 <memp_free>
}
8010b84: bf00 nop
8010b86: 3708 adds r7, #8
8010b88: 46bd mov sp, r7
8010b8a: bd80 pop {r7, pc}
8010b8c: 0801cb48 .word 0x0801cb48
8010b90: 0801cb78 .word 0x0801cb78
8010b94: 0801cb8c .word 0x0801cb8c
08010b98 <tcp_free_listen>:
/** Free a tcp listen pcb */
static void
tcp_free_listen(struct tcp_pcb *pcb)
{
8010b98: b580 push {r7, lr}
8010b9a: b082 sub sp, #8
8010b9c: af00 add r7, sp, #0
8010b9e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
8010ba0: 687b ldr r3, [r7, #4]
8010ba2: 7d1b ldrb r3, [r3, #20]
8010ba4: 2b01 cmp r3, #1
8010ba6: d105 bne.n 8010bb4 <tcp_free_listen+0x1c>
8010ba8: 4b06 ldr r3, [pc, #24] ; (8010bc4 <tcp_free_listen+0x2c>)
8010baa: 22df movs r2, #223 ; 0xdf
8010bac: 4906 ldr r1, [pc, #24] ; (8010bc8 <tcp_free_listen+0x30>)
8010bae: 4807 ldr r0, [pc, #28] ; (8010bcc <tcp_free_listen+0x34>)
8010bb0: f00a fa30 bl 801b014 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB_LISTEN, pcb);
8010bb4: 6879 ldr r1, [r7, #4]
8010bb6: 2002 movs r0, #2
8010bb8: f7fe fe6a bl 800f890 <memp_free>
}
8010bbc: bf00 nop
8010bbe: 3708 adds r7, #8
8010bc0: 46bd mov sp, r7
8010bc2: bd80 pop {r7, pc}
8010bc4: 0801cb48 .word 0x0801cb48
8010bc8: 0801cbb4 .word 0x0801cbb4
8010bcc: 0801cb8c .word 0x0801cb8c
08010bd0 <tcp_tmr>:
/**
* Called periodically to dispatch TCP timers.
*/
void
tcp_tmr(void)
{
8010bd0: b580 push {r7, lr}
8010bd2: af00 add r7, sp, #0
/* Call tcp_fasttmr() every 250 ms */
tcp_fasttmr();
8010bd4: f000 fe98 bl 8011908 <tcp_fasttmr>
if (++tcp_timer & 1) {
8010bd8: 4b07 ldr r3, [pc, #28] ; (8010bf8 <tcp_tmr+0x28>)
8010bda: 781b ldrb r3, [r3, #0]
8010bdc: 3301 adds r3, #1
8010bde: b2da uxtb r2, r3
8010be0: 4b05 ldr r3, [pc, #20] ; (8010bf8 <tcp_tmr+0x28>)
8010be2: 701a strb r2, [r3, #0]
8010be4: 4b04 ldr r3, [pc, #16] ; (8010bf8 <tcp_tmr+0x28>)
8010be6: 781b ldrb r3, [r3, #0]
8010be8: f003 0301 and.w r3, r3, #1
8010bec: 2b00 cmp r3, #0
8010bee: d001 beq.n 8010bf4 <tcp_tmr+0x24>
/* Call tcp_slowtmr() every 500 ms, i.e., every other timer
tcp_tmr() is called. */
tcp_slowtmr();
8010bf0: f000 fb4c bl 801128c <tcp_slowtmr>
}
}
8010bf4: bf00 nop
8010bf6: bd80 pop {r7, pc}
8010bf8: 20008729 .word 0x20008729
08010bfc <tcp_remove_listener>:
/** Called when a listen pcb is closed. Iterates one pcb list and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
{
8010bfc: b580 push {r7, lr}
8010bfe: b084 sub sp, #16
8010c00: af00 add r7, sp, #0
8010c02: 6078 str r0, [r7, #4]
8010c04: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
8010c06: 683b ldr r3, [r7, #0]
8010c08: 2b00 cmp r3, #0
8010c0a: d105 bne.n 8010c18 <tcp_remove_listener+0x1c>
8010c0c: 4b0d ldr r3, [pc, #52] ; (8010c44 <tcp_remove_listener+0x48>)
8010c0e: 22ff movs r2, #255 ; 0xff
8010c10: 490d ldr r1, [pc, #52] ; (8010c48 <tcp_remove_listener+0x4c>)
8010c12: 480e ldr r0, [pc, #56] ; (8010c4c <tcp_remove_listener+0x50>)
8010c14: f00a f9fe bl 801b014 <iprintf>
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010c18: 687b ldr r3, [r7, #4]
8010c1a: 60fb str r3, [r7, #12]
8010c1c: e00a b.n 8010c34 <tcp_remove_listener+0x38>
if (pcb->listener == lpcb) {
8010c1e: 68fb ldr r3, [r7, #12]
8010c20: 6fdb ldr r3, [r3, #124] ; 0x7c
8010c22: 683a ldr r2, [r7, #0]
8010c24: 429a cmp r2, r3
8010c26: d102 bne.n 8010c2e <tcp_remove_listener+0x32>
pcb->listener = NULL;
8010c28: 68fb ldr r3, [r7, #12]
8010c2a: 2200 movs r2, #0
8010c2c: 67da str r2, [r3, #124] ; 0x7c
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010c2e: 68fb ldr r3, [r7, #12]
8010c30: 68db ldr r3, [r3, #12]
8010c32: 60fb str r3, [r7, #12]
8010c34: 68fb ldr r3, [r7, #12]
8010c36: 2b00 cmp r3, #0
8010c38: d1f1 bne.n 8010c1e <tcp_remove_listener+0x22>
}
}
}
8010c3a: bf00 nop
8010c3c: 3710 adds r7, #16
8010c3e: 46bd mov sp, r7
8010c40: bd80 pop {r7, pc}
8010c42: bf00 nop
8010c44: 0801cb48 .word 0x0801cb48
8010c48: 0801cbd0 .word 0x0801cbd0
8010c4c: 0801cb8c .word 0x0801cb8c
08010c50 <tcp_listen_closed>:
/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_listen_closed(struct tcp_pcb *pcb)
{
8010c50: b580 push {r7, lr}
8010c52: b084 sub sp, #16
8010c54: af00 add r7, sp, #0
8010c56: 6078 str r0, [r7, #4]
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
size_t i;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010c58: 687b ldr r3, [r7, #4]
8010c5a: 2b00 cmp r3, #0
8010c5c: d106 bne.n 8010c6c <tcp_listen_closed+0x1c>
8010c5e: 4b14 ldr r3, [pc, #80] ; (8010cb0 <tcp_listen_closed+0x60>)
8010c60: f240 1211 movw r2, #273 ; 0x111
8010c64: 4913 ldr r1, [pc, #76] ; (8010cb4 <tcp_listen_closed+0x64>)
8010c66: 4814 ldr r0, [pc, #80] ; (8010cb8 <tcp_listen_closed+0x68>)
8010c68: f00a f9d4 bl 801b014 <iprintf>
LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
8010c6c: 687b ldr r3, [r7, #4]
8010c6e: 7d1b ldrb r3, [r3, #20]
8010c70: 2b01 cmp r3, #1
8010c72: d006 beq.n 8010c82 <tcp_listen_closed+0x32>
8010c74: 4b0e ldr r3, [pc, #56] ; (8010cb0 <tcp_listen_closed+0x60>)
8010c76: f44f 7289 mov.w r2, #274 ; 0x112
8010c7a: 4910 ldr r1, [pc, #64] ; (8010cbc <tcp_listen_closed+0x6c>)
8010c7c: 480e ldr r0, [pc, #56] ; (8010cb8 <tcp_listen_closed+0x68>)
8010c7e: f00a f9c9 bl 801b014 <iprintf>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010c82: 2301 movs r3, #1
8010c84: 60fb str r3, [r7, #12]
8010c86: e00b b.n 8010ca0 <tcp_listen_closed+0x50>
tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
8010c88: 4a0d ldr r2, [pc, #52] ; (8010cc0 <tcp_listen_closed+0x70>)
8010c8a: 68fb ldr r3, [r7, #12]
8010c8c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8010c90: 681b ldr r3, [r3, #0]
8010c92: 6879 ldr r1, [r7, #4]
8010c94: 4618 mov r0, r3
8010c96: f7ff ffb1 bl 8010bfc <tcp_remove_listener>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010c9a: 68fb ldr r3, [r7, #12]
8010c9c: 3301 adds r3, #1
8010c9e: 60fb str r3, [r7, #12]
8010ca0: 68fb ldr r3, [r7, #12]
8010ca2: 2b03 cmp r3, #3
8010ca4: d9f0 bls.n 8010c88 <tcp_listen_closed+0x38>
}
#endif
LWIP_UNUSED_ARG(pcb);
}
8010ca6: bf00 nop
8010ca8: 3710 adds r7, #16
8010caa: 46bd mov sp, r7
8010cac: bd80 pop {r7, pc}
8010cae: bf00 nop
8010cb0: 0801cb48 .word 0x0801cb48
8010cb4: 0801cbf8 .word 0x0801cbf8
8010cb8: 0801cb8c .word 0x0801cb8c
8010cbc: 0801cc04 .word 0x0801cc04
8010cc0: 08020e30 .word 0x08020e30
08010cc4 <tcp_close_shutdown>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
static err_t
tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
{
8010cc4: b5b0 push {r4, r5, r7, lr}
8010cc6: b088 sub sp, #32
8010cc8: af04 add r7, sp, #16
8010cca: 6078 str r0, [r7, #4]
8010ccc: 460b mov r3, r1
8010cce: 70fb strb r3, [r7, #3]
LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
8010cd0: 687b ldr r3, [r7, #4]
8010cd2: 2b00 cmp r3, #0
8010cd4: d106 bne.n 8010ce4 <tcp_close_shutdown+0x20>
8010cd6: 4b61 ldr r3, [pc, #388] ; (8010e5c <tcp_close_shutdown+0x198>)
8010cd8: f44f 72af mov.w r2, #350 ; 0x15e
8010cdc: 4960 ldr r1, [pc, #384] ; (8010e60 <tcp_close_shutdown+0x19c>)
8010cde: 4861 ldr r0, [pc, #388] ; (8010e64 <tcp_close_shutdown+0x1a0>)
8010ce0: f00a f998 bl 801b014 <iprintf>
if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
8010ce4: 78fb ldrb r3, [r7, #3]
8010ce6: 2b00 cmp r3, #0
8010ce8: d066 beq.n 8010db8 <tcp_close_shutdown+0xf4>
8010cea: 687b ldr r3, [r7, #4]
8010cec: 7d1b ldrb r3, [r3, #20]
8010cee: 2b04 cmp r3, #4
8010cf0: d003 beq.n 8010cfa <tcp_close_shutdown+0x36>
8010cf2: 687b ldr r3, [r7, #4]
8010cf4: 7d1b ldrb r3, [r3, #20]
8010cf6: 2b07 cmp r3, #7
8010cf8: d15e bne.n 8010db8 <tcp_close_shutdown+0xf4>
if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
8010cfa: 687b ldr r3, [r7, #4]
8010cfc: 6f9b ldr r3, [r3, #120] ; 0x78
8010cfe: 2b00 cmp r3, #0
8010d00: d104 bne.n 8010d0c <tcp_close_shutdown+0x48>
8010d02: 687b ldr r3, [r7, #4]
8010d04: 8d1b ldrh r3, [r3, #40] ; 0x28
8010d06: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8010d0a: d055 beq.n 8010db8 <tcp_close_shutdown+0xf4>
/* Not all data received by application, send RST to tell the remote
side about this. */
LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
8010d0c: 687b ldr r3, [r7, #4]
8010d0e: 8b5b ldrh r3, [r3, #26]
8010d10: f003 0310 and.w r3, r3, #16
8010d14: 2b00 cmp r3, #0
8010d16: d106 bne.n 8010d26 <tcp_close_shutdown+0x62>
8010d18: 4b50 ldr r3, [pc, #320] ; (8010e5c <tcp_close_shutdown+0x198>)
8010d1a: f44f 72b2 mov.w r2, #356 ; 0x164
8010d1e: 4952 ldr r1, [pc, #328] ; (8010e68 <tcp_close_shutdown+0x1a4>)
8010d20: 4850 ldr r0, [pc, #320] ; (8010e64 <tcp_close_shutdown+0x1a0>)
8010d22: f00a f977 bl 801b014 <iprintf>
/* don't call tcp_abort here: we must not deallocate the pcb since
that might not be expected when calling tcp_close */
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
8010d26: 687b ldr r3, [r7, #4]
8010d28: 6d18 ldr r0, [r3, #80] ; 0x50
8010d2a: 687b ldr r3, [r7, #4]
8010d2c: 6a5c ldr r4, [r3, #36] ; 0x24
8010d2e: 687d ldr r5, [r7, #4]
8010d30: 687b ldr r3, [r7, #4]
8010d32: 3304 adds r3, #4
8010d34: 687a ldr r2, [r7, #4]
8010d36: 8ad2 ldrh r2, [r2, #22]
8010d38: 6879 ldr r1, [r7, #4]
8010d3a: 8b09 ldrh r1, [r1, #24]
8010d3c: 9102 str r1, [sp, #8]
8010d3e: 9201 str r2, [sp, #4]
8010d40: 9300 str r3, [sp, #0]
8010d42: 462b mov r3, r5
8010d44: 4622 mov r2, r4
8010d46: 4601 mov r1, r0
8010d48: 6878 ldr r0, [r7, #4]
8010d4a: f004 fe91 bl 8015a70 <tcp_rst>
pcb->local_port, pcb->remote_port);
tcp_pcb_purge(pcb);
8010d4e: 6878 ldr r0, [r7, #4]
8010d50: f001 f8ba bl 8011ec8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8010d54: 4b45 ldr r3, [pc, #276] ; (8010e6c <tcp_close_shutdown+0x1a8>)
8010d56: 681b ldr r3, [r3, #0]
8010d58: 687a ldr r2, [r7, #4]
8010d5a: 429a cmp r2, r3
8010d5c: d105 bne.n 8010d6a <tcp_close_shutdown+0xa6>
8010d5e: 4b43 ldr r3, [pc, #268] ; (8010e6c <tcp_close_shutdown+0x1a8>)
8010d60: 681b ldr r3, [r3, #0]
8010d62: 68db ldr r3, [r3, #12]
8010d64: 4a41 ldr r2, [pc, #260] ; (8010e6c <tcp_close_shutdown+0x1a8>)
8010d66: 6013 str r3, [r2, #0]
8010d68: e013 b.n 8010d92 <tcp_close_shutdown+0xce>
8010d6a: 4b40 ldr r3, [pc, #256] ; (8010e6c <tcp_close_shutdown+0x1a8>)
8010d6c: 681b ldr r3, [r3, #0]
8010d6e: 60fb str r3, [r7, #12]
8010d70: e00c b.n 8010d8c <tcp_close_shutdown+0xc8>
8010d72: 68fb ldr r3, [r7, #12]
8010d74: 68db ldr r3, [r3, #12]
8010d76: 687a ldr r2, [r7, #4]
8010d78: 429a cmp r2, r3
8010d7a: d104 bne.n 8010d86 <tcp_close_shutdown+0xc2>
8010d7c: 687b ldr r3, [r7, #4]
8010d7e: 68da ldr r2, [r3, #12]
8010d80: 68fb ldr r3, [r7, #12]
8010d82: 60da str r2, [r3, #12]
8010d84: e005 b.n 8010d92 <tcp_close_shutdown+0xce>
8010d86: 68fb ldr r3, [r7, #12]
8010d88: 68db ldr r3, [r3, #12]
8010d8a: 60fb str r3, [r7, #12]
8010d8c: 68fb ldr r3, [r7, #12]
8010d8e: 2b00 cmp r3, #0
8010d90: d1ef bne.n 8010d72 <tcp_close_shutdown+0xae>
8010d92: 687b ldr r3, [r7, #4]
8010d94: 2200 movs r2, #0
8010d96: 60da str r2, [r3, #12]
8010d98: 4b35 ldr r3, [pc, #212] ; (8010e70 <tcp_close_shutdown+0x1ac>)
8010d9a: 2201 movs r2, #1
8010d9c: 701a strb r2, [r3, #0]
/* Deallocate the pcb since we already sent a RST for it */
if (tcp_input_pcb == pcb) {
8010d9e: 4b35 ldr r3, [pc, #212] ; (8010e74 <tcp_close_shutdown+0x1b0>)
8010da0: 681b ldr r3, [r3, #0]
8010da2: 687a ldr r2, [r7, #4]
8010da4: 429a cmp r2, r3
8010da6: d102 bne.n 8010dae <tcp_close_shutdown+0xea>
/* prevent using a deallocated pcb: free it from tcp_input later */
tcp_trigger_input_pcb_close();
8010da8: f003 fd4c bl 8014844 <tcp_trigger_input_pcb_close>
8010dac: e002 b.n 8010db4 <tcp_close_shutdown+0xf0>
} else {
tcp_free(pcb);
8010dae: 6878 ldr r0, [r7, #4]
8010db0: f7ff fed6 bl 8010b60 <tcp_free>
}
return ERR_OK;
8010db4: 2300 movs r3, #0
8010db6: e04d b.n 8010e54 <tcp_close_shutdown+0x190>
}
}
/* - states which free the pcb are handled here,
- states which send FIN and change state are handled in tcp_close_shutdown_fin() */
switch (pcb->state) {
8010db8: 687b ldr r3, [r7, #4]
8010dba: 7d1b ldrb r3, [r3, #20]
8010dbc: 2b01 cmp r3, #1
8010dbe: d02d beq.n 8010e1c <tcp_close_shutdown+0x158>
8010dc0: 2b02 cmp r3, #2
8010dc2: d036 beq.n 8010e32 <tcp_close_shutdown+0x16e>
8010dc4: 2b00 cmp r3, #0
8010dc6: d13f bne.n 8010e48 <tcp_close_shutdown+0x184>
* and the user needs some way to free it should the need arise.
* Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
* or for a pcb that has been used and then entered the CLOSED state
* is erroneous, but this should never happen as the pcb has in those cases
* been freed, and so any remaining handles are bogus. */
if (pcb->local_port != 0) {
8010dc8: 687b ldr r3, [r7, #4]
8010dca: 8adb ldrh r3, [r3, #22]
8010dcc: 2b00 cmp r3, #0
8010dce: d021 beq.n 8010e14 <tcp_close_shutdown+0x150>
TCP_RMV(&tcp_bound_pcbs, pcb);
8010dd0: 4b29 ldr r3, [pc, #164] ; (8010e78 <tcp_close_shutdown+0x1b4>)
8010dd2: 681b ldr r3, [r3, #0]
8010dd4: 687a ldr r2, [r7, #4]
8010dd6: 429a cmp r2, r3
8010dd8: d105 bne.n 8010de6 <tcp_close_shutdown+0x122>
8010dda: 4b27 ldr r3, [pc, #156] ; (8010e78 <tcp_close_shutdown+0x1b4>)
8010ddc: 681b ldr r3, [r3, #0]
8010dde: 68db ldr r3, [r3, #12]
8010de0: 4a25 ldr r2, [pc, #148] ; (8010e78 <tcp_close_shutdown+0x1b4>)
8010de2: 6013 str r3, [r2, #0]
8010de4: e013 b.n 8010e0e <tcp_close_shutdown+0x14a>
8010de6: 4b24 ldr r3, [pc, #144] ; (8010e78 <tcp_close_shutdown+0x1b4>)
8010de8: 681b ldr r3, [r3, #0]
8010dea: 60bb str r3, [r7, #8]
8010dec: e00c b.n 8010e08 <tcp_close_shutdown+0x144>
8010dee: 68bb ldr r3, [r7, #8]
8010df0: 68db ldr r3, [r3, #12]
8010df2: 687a ldr r2, [r7, #4]
8010df4: 429a cmp r2, r3
8010df6: d104 bne.n 8010e02 <tcp_close_shutdown+0x13e>
8010df8: 687b ldr r3, [r7, #4]
8010dfa: 68da ldr r2, [r3, #12]
8010dfc: 68bb ldr r3, [r7, #8]
8010dfe: 60da str r2, [r3, #12]
8010e00: e005 b.n 8010e0e <tcp_close_shutdown+0x14a>
8010e02: 68bb ldr r3, [r7, #8]
8010e04: 68db ldr r3, [r3, #12]
8010e06: 60bb str r3, [r7, #8]
8010e08: 68bb ldr r3, [r7, #8]
8010e0a: 2b00 cmp r3, #0
8010e0c: d1ef bne.n 8010dee <tcp_close_shutdown+0x12a>
8010e0e: 687b ldr r3, [r7, #4]
8010e10: 2200 movs r2, #0
8010e12: 60da str r2, [r3, #12]
}
tcp_free(pcb);
8010e14: 6878 ldr r0, [r7, #4]
8010e16: f7ff fea3 bl 8010b60 <tcp_free>
break;
8010e1a: e01a b.n 8010e52 <tcp_close_shutdown+0x18e>
case LISTEN:
tcp_listen_closed(pcb);
8010e1c: 6878 ldr r0, [r7, #4]
8010e1e: f7ff ff17 bl 8010c50 <tcp_listen_closed>
tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
8010e22: 6879 ldr r1, [r7, #4]
8010e24: 4815 ldr r0, [pc, #84] ; (8010e7c <tcp_close_shutdown+0x1b8>)
8010e26: f001 f89f bl 8011f68 <tcp_pcb_remove>
tcp_free_listen(pcb);
8010e2a: 6878 ldr r0, [r7, #4]
8010e2c: f7ff feb4 bl 8010b98 <tcp_free_listen>
break;
8010e30: e00f b.n 8010e52 <tcp_close_shutdown+0x18e>
case SYN_SENT:
TCP_PCB_REMOVE_ACTIVE(pcb);
8010e32: 6879 ldr r1, [r7, #4]
8010e34: 480d ldr r0, [pc, #52] ; (8010e6c <tcp_close_shutdown+0x1a8>)
8010e36: f001 f897 bl 8011f68 <tcp_pcb_remove>
8010e3a: 4b0d ldr r3, [pc, #52] ; (8010e70 <tcp_close_shutdown+0x1ac>)
8010e3c: 2201 movs r2, #1
8010e3e: 701a strb r2, [r3, #0]
tcp_free(pcb);
8010e40: 6878 ldr r0, [r7, #4]
8010e42: f7ff fe8d bl 8010b60 <tcp_free>
MIB2_STATS_INC(mib2.tcpattemptfails);
break;
8010e46: e004 b.n 8010e52 <tcp_close_shutdown+0x18e>
default:
return tcp_close_shutdown_fin(pcb);
8010e48: 6878 ldr r0, [r7, #4]
8010e4a: f000 f819 bl 8010e80 <tcp_close_shutdown_fin>
8010e4e: 4603 mov r3, r0
8010e50: e000 b.n 8010e54 <tcp_close_shutdown+0x190>
}
return ERR_OK;
8010e52: 2300 movs r3, #0
}
8010e54: 4618 mov r0, r3
8010e56: 3710 adds r7, #16
8010e58: 46bd mov sp, r7
8010e5a: bdb0 pop {r4, r5, r7, pc}
8010e5c: 0801cb48 .word 0x0801cb48
8010e60: 0801cc1c .word 0x0801cc1c
8010e64: 0801cb8c .word 0x0801cb8c
8010e68: 0801cc3c .word 0x0801cc3c
8010e6c: 2000f5c0 .word 0x2000f5c0
8010e70: 2000f5bc .word 0x2000f5bc
8010e74: 2000f5d4 .word 0x2000f5d4
8010e78: 2000f5cc .word 0x2000f5cc
8010e7c: 2000f5c8 .word 0x2000f5c8
08010e80 <tcp_close_shutdown_fin>:
static err_t
tcp_close_shutdown_fin(struct tcp_pcb *pcb)
{
8010e80: b580 push {r7, lr}
8010e82: b084 sub sp, #16
8010e84: af00 add r7, sp, #0
8010e86: 6078 str r0, [r7, #4]
err_t err;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010e88: 687b ldr r3, [r7, #4]
8010e8a: 2b00 cmp r3, #0
8010e8c: d106 bne.n 8010e9c <tcp_close_shutdown_fin+0x1c>
8010e8e: 4b2c ldr r3, [pc, #176] ; (8010f40 <tcp_close_shutdown_fin+0xc0>)
8010e90: f44f 72ce mov.w r2, #412 ; 0x19c
8010e94: 492b ldr r1, [pc, #172] ; (8010f44 <tcp_close_shutdown_fin+0xc4>)
8010e96: 482c ldr r0, [pc, #176] ; (8010f48 <tcp_close_shutdown_fin+0xc8>)
8010e98: f00a f8bc bl 801b014 <iprintf>
switch (pcb->state) {
8010e9c: 687b ldr r3, [r7, #4]
8010e9e: 7d1b ldrb r3, [r3, #20]
8010ea0: 2b04 cmp r3, #4
8010ea2: d010 beq.n 8010ec6 <tcp_close_shutdown_fin+0x46>
8010ea4: 2b07 cmp r3, #7
8010ea6: d01b beq.n 8010ee0 <tcp_close_shutdown_fin+0x60>
8010ea8: 2b03 cmp r3, #3
8010eaa: d126 bne.n 8010efa <tcp_close_shutdown_fin+0x7a>
case SYN_RCVD:
err = tcp_send_fin(pcb);
8010eac: 6878 ldr r0, [r7, #4]
8010eae: f003 fedb bl 8014c68 <tcp_send_fin>
8010eb2: 4603 mov r3, r0
8010eb4: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010eb6: f997 300f ldrsb.w r3, [r7, #15]
8010eba: 2b00 cmp r3, #0
8010ebc: d11f bne.n 8010efe <tcp_close_shutdown_fin+0x7e>
tcp_backlog_accepted(pcb);
MIB2_STATS_INC(mib2.tcpattemptfails);
pcb->state = FIN_WAIT_1;
8010ebe: 687b ldr r3, [r7, #4]
8010ec0: 2205 movs r2, #5
8010ec2: 751a strb r2, [r3, #20]
}
break;
8010ec4: e01b b.n 8010efe <tcp_close_shutdown_fin+0x7e>
case ESTABLISHED:
err = tcp_send_fin(pcb);
8010ec6: 6878 ldr r0, [r7, #4]
8010ec8: f003 fece bl 8014c68 <tcp_send_fin>
8010ecc: 4603 mov r3, r0
8010ece: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010ed0: f997 300f ldrsb.w r3, [r7, #15]
8010ed4: 2b00 cmp r3, #0
8010ed6: d114 bne.n 8010f02 <tcp_close_shutdown_fin+0x82>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = FIN_WAIT_1;
8010ed8: 687b ldr r3, [r7, #4]
8010eda: 2205 movs r2, #5
8010edc: 751a strb r2, [r3, #20]
}
break;
8010ede: e010 b.n 8010f02 <tcp_close_shutdown_fin+0x82>
case CLOSE_WAIT:
err = tcp_send_fin(pcb);
8010ee0: 6878 ldr r0, [r7, #4]
8010ee2: f003 fec1 bl 8014c68 <tcp_send_fin>
8010ee6: 4603 mov r3, r0
8010ee8: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010eea: f997 300f ldrsb.w r3, [r7, #15]
8010eee: 2b00 cmp r3, #0
8010ef0: d109 bne.n 8010f06 <tcp_close_shutdown_fin+0x86>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = LAST_ACK;
8010ef2: 687b ldr r3, [r7, #4]
8010ef4: 2209 movs r2, #9
8010ef6: 751a strb r2, [r3, #20]
}
break;
8010ef8: e005 b.n 8010f06 <tcp_close_shutdown_fin+0x86>
default:
/* Has already been closed, do nothing. */
return ERR_OK;
8010efa: 2300 movs r3, #0
8010efc: e01c b.n 8010f38 <tcp_close_shutdown_fin+0xb8>
break;
8010efe: bf00 nop
8010f00: e002 b.n 8010f08 <tcp_close_shutdown_fin+0x88>
break;
8010f02: bf00 nop
8010f04: e000 b.n 8010f08 <tcp_close_shutdown_fin+0x88>
break;
8010f06: bf00 nop
}
if (err == ERR_OK) {
8010f08: f997 300f ldrsb.w r3, [r7, #15]
8010f0c: 2b00 cmp r3, #0
8010f0e: d103 bne.n 8010f18 <tcp_close_shutdown_fin+0x98>
/* To ensure all data has been sent when tcp_close returns, we have
to make sure tcp_output doesn't fail.
Since we don't really have to ensure all data has been sent when tcp_close
returns (unsent data is sent from tcp timer functions, also), we don't care
for the return value of tcp_output for now. */
tcp_output(pcb);
8010f10: 6878 ldr r0, [r7, #4]
8010f12: f003 ffe7 bl 8014ee4 <tcp_output>
8010f16: e00d b.n 8010f34 <tcp_close_shutdown_fin+0xb4>
} else if (err == ERR_MEM) {
8010f18: f997 300f ldrsb.w r3, [r7, #15]
8010f1c: f1b3 3fff cmp.w r3, #4294967295
8010f20: d108 bne.n 8010f34 <tcp_close_shutdown_fin+0xb4>
/* Mark this pcb for closing. Closing is retried from tcp_tmr. */
tcp_set_flags(pcb, TF_CLOSEPEND);
8010f22: 687b ldr r3, [r7, #4]
8010f24: 8b5b ldrh r3, [r3, #26]
8010f26: f043 0308 orr.w r3, r3, #8
8010f2a: b29a uxth r2, r3
8010f2c: 687b ldr r3, [r7, #4]
8010f2e: 835a strh r2, [r3, #26]
/* We have to return ERR_OK from here to indicate to the callers that this
pcb should not be used any more as it will be freed soon via tcp_tmr.
This is OK here since sending FIN does not guarantee a time frime for
actually freeing the pcb, either (it is left in closure states for
remote ACK or timeout) */
return ERR_OK;
8010f30: 2300 movs r3, #0
8010f32: e001 b.n 8010f38 <tcp_close_shutdown_fin+0xb8>
}
return err;
8010f34: f997 300f ldrsb.w r3, [r7, #15]
}
8010f38: 4618 mov r0, r3
8010f3a: 3710 adds r7, #16
8010f3c: 46bd mov sp, r7
8010f3e: bd80 pop {r7, pc}
8010f40: 0801cb48 .word 0x0801cb48
8010f44: 0801cbf8 .word 0x0801cbf8
8010f48: 0801cb8c .word 0x0801cb8c
08010f4c <tcp_close>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
err_t
tcp_close(struct tcp_pcb *pcb)
{
8010f4c: b580 push {r7, lr}
8010f4e: b082 sub sp, #8
8010f50: af00 add r7, sp, #0
8010f52: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
8010f54: 687b ldr r3, [r7, #4]
8010f56: 2b00 cmp r3, #0
8010f58: d109 bne.n 8010f6e <tcp_close+0x22>
8010f5a: 4b0f ldr r3, [pc, #60] ; (8010f98 <tcp_close+0x4c>)
8010f5c: f44f 72f4 mov.w r2, #488 ; 0x1e8
8010f60: 490e ldr r1, [pc, #56] ; (8010f9c <tcp_close+0x50>)
8010f62: 480f ldr r0, [pc, #60] ; (8010fa0 <tcp_close+0x54>)
8010f64: f00a f856 bl 801b014 <iprintf>
8010f68: f06f 030f mvn.w r3, #15
8010f6c: e00f b.n 8010f8e <tcp_close+0x42>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
tcp_debug_print_state(pcb->state);
if (pcb->state != LISTEN) {
8010f6e: 687b ldr r3, [r7, #4]
8010f70: 7d1b ldrb r3, [r3, #20]
8010f72: 2b01 cmp r3, #1
8010f74: d006 beq.n 8010f84 <tcp_close+0x38>
/* Set a flag not to receive any more data... */
tcp_set_flags(pcb, TF_RXCLOSED);
8010f76: 687b ldr r3, [r7, #4]
8010f78: 8b5b ldrh r3, [r3, #26]
8010f7a: f043 0310 orr.w r3, r3, #16
8010f7e: b29a uxth r2, r3
8010f80: 687b ldr r3, [r7, #4]
8010f82: 835a strh r2, [r3, #26]
}
/* ... and close */
return tcp_close_shutdown(pcb, 1);
8010f84: 2101 movs r1, #1
8010f86: 6878 ldr r0, [r7, #4]
8010f88: f7ff fe9c bl 8010cc4 <tcp_close_shutdown>
8010f8c: 4603 mov r3, r0
}
8010f8e: 4618 mov r0, r3
8010f90: 3708 adds r7, #8
8010f92: 46bd mov sp, r7
8010f94: bd80 pop {r7, pc}
8010f96: bf00 nop
8010f98: 0801cb48 .word 0x0801cb48
8010f9c: 0801cc58 .word 0x0801cc58
8010fa0: 0801cb8c .word 0x0801cb8c
08010fa4 <tcp_abandon>:
* @param pcb the tcp_pcb to abort
* @param reset boolean to indicate whether a reset should be sent
*/
void
tcp_abandon(struct tcp_pcb *pcb, int reset)
{
8010fa4: b580 push {r7, lr}
8010fa6: b08e sub sp, #56 ; 0x38
8010fa8: af04 add r7, sp, #16
8010faa: 6078 str r0, [r7, #4]
8010fac: 6039 str r1, [r7, #0]
#endif /* LWIP_CALLBACK_API */
void *errf_arg;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
8010fae: 687b ldr r3, [r7, #4]
8010fb0: 2b00 cmp r3, #0
8010fb2: d107 bne.n 8010fc4 <tcp_abandon+0x20>
8010fb4: 4b52 ldr r3, [pc, #328] ; (8011100 <tcp_abandon+0x15c>)
8010fb6: f240 223d movw r2, #573 ; 0x23d
8010fba: 4952 ldr r1, [pc, #328] ; (8011104 <tcp_abandon+0x160>)
8010fbc: 4852 ldr r0, [pc, #328] ; (8011108 <tcp_abandon+0x164>)
8010fbe: f00a f829 bl 801b014 <iprintf>
8010fc2: e099 b.n 80110f8 <tcp_abandon+0x154>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
8010fc4: 687b ldr r3, [r7, #4]
8010fc6: 7d1b ldrb r3, [r3, #20]
8010fc8: 2b01 cmp r3, #1
8010fca: d106 bne.n 8010fda <tcp_abandon+0x36>
8010fcc: 4b4c ldr r3, [pc, #304] ; (8011100 <tcp_abandon+0x15c>)
8010fce: f240 2241 movw r2, #577 ; 0x241
8010fd2: 494e ldr r1, [pc, #312] ; (801110c <tcp_abandon+0x168>)
8010fd4: 484c ldr r0, [pc, #304] ; (8011108 <tcp_abandon+0x164>)
8010fd6: f00a f81d bl 801b014 <iprintf>
pcb->state != LISTEN);
/* Figure out on which TCP PCB list we are, and remove us. If we
are in an active state, call the receive function associated with
the PCB with a NULL argument, and send an RST to the remote end. */
if (pcb->state == TIME_WAIT) {
8010fda: 687b ldr r3, [r7, #4]
8010fdc: 7d1b ldrb r3, [r3, #20]
8010fde: 2b0a cmp r3, #10
8010fe0: d107 bne.n 8010ff2 <tcp_abandon+0x4e>
tcp_pcb_remove(&tcp_tw_pcbs, pcb);
8010fe2: 6879 ldr r1, [r7, #4]
8010fe4: 484a ldr r0, [pc, #296] ; (8011110 <tcp_abandon+0x16c>)
8010fe6: f000 ffbf bl 8011f68 <tcp_pcb_remove>
tcp_free(pcb);
8010fea: 6878 ldr r0, [r7, #4]
8010fec: f7ff fdb8 bl 8010b60 <tcp_free>
8010ff0: e082 b.n 80110f8 <tcp_abandon+0x154>
} else {
int send_rst = 0;
8010ff2: 2300 movs r3, #0
8010ff4: 627b str r3, [r7, #36] ; 0x24
u16_t local_port = 0;
8010ff6: 2300 movs r3, #0
8010ff8: 847b strh r3, [r7, #34] ; 0x22
enum tcp_state last_state;
seqno = pcb->snd_nxt;
8010ffa: 687b ldr r3, [r7, #4]
8010ffc: 6d1b ldr r3, [r3, #80] ; 0x50
8010ffe: 61bb str r3, [r7, #24]
ackno = pcb->rcv_nxt;
8011000: 687b ldr r3, [r7, #4]
8011002: 6a5b ldr r3, [r3, #36] ; 0x24
8011004: 617b str r3, [r7, #20]
#if LWIP_CALLBACK_API
errf = pcb->errf;
8011006: 687b ldr r3, [r7, #4]
8011008: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
801100c: 613b str r3, [r7, #16]
#endif /* LWIP_CALLBACK_API */
errf_arg = pcb->callback_arg;
801100e: 687b ldr r3, [r7, #4]
8011010: 691b ldr r3, [r3, #16]
8011012: 60fb str r3, [r7, #12]
if (pcb->state == CLOSED) {
8011014: 687b ldr r3, [r7, #4]
8011016: 7d1b ldrb r3, [r3, #20]
8011018: 2b00 cmp r3, #0
801101a: d126 bne.n 801106a <tcp_abandon+0xc6>
if (pcb->local_port != 0) {
801101c: 687b ldr r3, [r7, #4]
801101e: 8adb ldrh r3, [r3, #22]
8011020: 2b00 cmp r3, #0
8011022: d02e beq.n 8011082 <tcp_abandon+0xde>
/* bound, not yet opened */
TCP_RMV(&tcp_bound_pcbs, pcb);
8011024: 4b3b ldr r3, [pc, #236] ; (8011114 <tcp_abandon+0x170>)
8011026: 681b ldr r3, [r3, #0]
8011028: 687a ldr r2, [r7, #4]
801102a: 429a cmp r2, r3
801102c: d105 bne.n 801103a <tcp_abandon+0x96>
801102e: 4b39 ldr r3, [pc, #228] ; (8011114 <tcp_abandon+0x170>)
8011030: 681b ldr r3, [r3, #0]
8011032: 68db ldr r3, [r3, #12]
8011034: 4a37 ldr r2, [pc, #220] ; (8011114 <tcp_abandon+0x170>)
8011036: 6013 str r3, [r2, #0]
8011038: e013 b.n 8011062 <tcp_abandon+0xbe>
801103a: 4b36 ldr r3, [pc, #216] ; (8011114 <tcp_abandon+0x170>)
801103c: 681b ldr r3, [r3, #0]
801103e: 61fb str r3, [r7, #28]
8011040: e00c b.n 801105c <tcp_abandon+0xb8>
8011042: 69fb ldr r3, [r7, #28]
8011044: 68db ldr r3, [r3, #12]
8011046: 687a ldr r2, [r7, #4]
8011048: 429a cmp r2, r3
801104a: d104 bne.n 8011056 <tcp_abandon+0xb2>
801104c: 687b ldr r3, [r7, #4]
801104e: 68da ldr r2, [r3, #12]
8011050: 69fb ldr r3, [r7, #28]
8011052: 60da str r2, [r3, #12]
8011054: e005 b.n 8011062 <tcp_abandon+0xbe>
8011056: 69fb ldr r3, [r7, #28]
8011058: 68db ldr r3, [r3, #12]
801105a: 61fb str r3, [r7, #28]
801105c: 69fb ldr r3, [r7, #28]
801105e: 2b00 cmp r3, #0
8011060: d1ef bne.n 8011042 <tcp_abandon+0x9e>
8011062: 687b ldr r3, [r7, #4]
8011064: 2200 movs r2, #0
8011066: 60da str r2, [r3, #12]
8011068: e00b b.n 8011082 <tcp_abandon+0xde>
}
} else {
send_rst = reset;
801106a: 683b ldr r3, [r7, #0]
801106c: 627b str r3, [r7, #36] ; 0x24
local_port = pcb->local_port;
801106e: 687b ldr r3, [r7, #4]
8011070: 8adb ldrh r3, [r3, #22]
8011072: 847b strh r3, [r7, #34] ; 0x22
TCP_PCB_REMOVE_ACTIVE(pcb);
8011074: 6879 ldr r1, [r7, #4]
8011076: 4828 ldr r0, [pc, #160] ; (8011118 <tcp_abandon+0x174>)
8011078: f000 ff76 bl 8011f68 <tcp_pcb_remove>
801107c: 4b27 ldr r3, [pc, #156] ; (801111c <tcp_abandon+0x178>)
801107e: 2201 movs r2, #1
8011080: 701a strb r2, [r3, #0]
}
if (pcb->unacked != NULL) {
8011082: 687b ldr r3, [r7, #4]
8011084: 6f1b ldr r3, [r3, #112] ; 0x70
8011086: 2b00 cmp r3, #0
8011088: d004 beq.n 8011094 <tcp_abandon+0xf0>
tcp_segs_free(pcb->unacked);
801108a: 687b ldr r3, [r7, #4]
801108c: 6f1b ldr r3, [r3, #112] ; 0x70
801108e: 4618 mov r0, r3
8011090: f000 fd1a bl 8011ac8 <tcp_segs_free>
}
if (pcb->unsent != NULL) {
8011094: 687b ldr r3, [r7, #4]
8011096: 6edb ldr r3, [r3, #108] ; 0x6c
8011098: 2b00 cmp r3, #0
801109a: d004 beq.n 80110a6 <tcp_abandon+0x102>
tcp_segs_free(pcb->unsent);
801109c: 687b ldr r3, [r7, #4]
801109e: 6edb ldr r3, [r3, #108] ; 0x6c
80110a0: 4618 mov r0, r3
80110a2: f000 fd11 bl 8011ac8 <tcp_segs_free>
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
80110a6: 687b ldr r3, [r7, #4]
80110a8: 6f5b ldr r3, [r3, #116] ; 0x74
80110aa: 2b00 cmp r3, #0
80110ac: d004 beq.n 80110b8 <tcp_abandon+0x114>
tcp_segs_free(pcb->ooseq);
80110ae: 687b ldr r3, [r7, #4]
80110b0: 6f5b ldr r3, [r3, #116] ; 0x74
80110b2: 4618 mov r0, r3
80110b4: f000 fd08 bl 8011ac8 <tcp_segs_free>
}
#endif /* TCP_QUEUE_OOSEQ */
tcp_backlog_accepted(pcb);
if (send_rst) {
80110b8: 6a7b ldr r3, [r7, #36] ; 0x24
80110ba: 2b00 cmp r3, #0
80110bc: d00e beq.n 80110dc <tcp_abandon+0x138>
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
80110be: 6879 ldr r1, [r7, #4]
80110c0: 687b ldr r3, [r7, #4]
80110c2: 3304 adds r3, #4
80110c4: 687a ldr r2, [r7, #4]
80110c6: 8b12 ldrh r2, [r2, #24]
80110c8: 9202 str r2, [sp, #8]
80110ca: 8c7a ldrh r2, [r7, #34] ; 0x22
80110cc: 9201 str r2, [sp, #4]
80110ce: 9300 str r3, [sp, #0]
80110d0: 460b mov r3, r1
80110d2: 697a ldr r2, [r7, #20]
80110d4: 69b9 ldr r1, [r7, #24]
80110d6: 6878 ldr r0, [r7, #4]
80110d8: f004 fcca bl 8015a70 <tcp_rst>
}
last_state = pcb->state;
80110dc: 687b ldr r3, [r7, #4]
80110de: 7d1b ldrb r3, [r3, #20]
80110e0: 72fb strb r3, [r7, #11]
tcp_free(pcb);
80110e2: 6878 ldr r0, [r7, #4]
80110e4: f7ff fd3c bl 8010b60 <tcp_free>
TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
80110e8: 693b ldr r3, [r7, #16]
80110ea: 2b00 cmp r3, #0
80110ec: d004 beq.n 80110f8 <tcp_abandon+0x154>
80110ee: 693b ldr r3, [r7, #16]
80110f0: f06f 010c mvn.w r1, #12
80110f4: 68f8 ldr r0, [r7, #12]
80110f6: 4798 blx r3
}
}
80110f8: 3728 adds r7, #40 ; 0x28
80110fa: 46bd mov sp, r7
80110fc: bd80 pop {r7, pc}
80110fe: bf00 nop
8011100: 0801cb48 .word 0x0801cb48
8011104: 0801cc8c .word 0x0801cc8c
8011108: 0801cb8c .word 0x0801cb8c
801110c: 0801cca8 .word 0x0801cca8
8011110: 2000f5d0 .word 0x2000f5d0
8011114: 2000f5cc .word 0x2000f5cc
8011118: 2000f5c0 .word 0x2000f5c0
801111c: 2000f5bc .word 0x2000f5bc
08011120 <tcp_abort>:
*
* @param pcb the tcp pcb to abort
*/
void
tcp_abort(struct tcp_pcb *pcb)
{
8011120: b580 push {r7, lr}
8011122: b082 sub sp, #8
8011124: af00 add r7, sp, #0
8011126: 6078 str r0, [r7, #4]
tcp_abandon(pcb, 1);
8011128: 2101 movs r1, #1
801112a: 6878 ldr r0, [r7, #4]
801112c: f7ff ff3a bl 8010fa4 <tcp_abandon>
}
8011130: bf00 nop
8011132: 3708 adds r7, #8
8011134: 46bd mov sp, r7
8011136: bd80 pop {r7, pc}
08011138 <tcp_update_rcv_ann_wnd>:
* Returns how much extra window would be advertised if we sent an
* update now.
*/
u32_t
tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
{
8011138: b580 push {r7, lr}
801113a: b084 sub sp, #16
801113c: af00 add r7, sp, #0
801113e: 6078 str r0, [r7, #4]
u32_t new_right_edge;
LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
8011140: 687b ldr r3, [r7, #4]
8011142: 2b00 cmp r3, #0
8011144: d106 bne.n 8011154 <tcp_update_rcv_ann_wnd+0x1c>
8011146: 4b25 ldr r3, [pc, #148] ; (80111dc <tcp_update_rcv_ann_wnd+0xa4>)
8011148: f240 32a6 movw r2, #934 ; 0x3a6
801114c: 4924 ldr r1, [pc, #144] ; (80111e0 <tcp_update_rcv_ann_wnd+0xa8>)
801114e: 4825 ldr r0, [pc, #148] ; (80111e4 <tcp_update_rcv_ann_wnd+0xac>)
8011150: f009 ff60 bl 801b014 <iprintf>
new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
8011154: 687b ldr r3, [r7, #4]
8011156: 6a5b ldr r3, [r3, #36] ; 0x24
8011158: 687a ldr r2, [r7, #4]
801115a: 8d12 ldrh r2, [r2, #40] ; 0x28
801115c: 4413 add r3, r2
801115e: 60fb str r3, [r7, #12]
if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
8011160: 687b ldr r3, [r7, #4]
8011162: 6adb ldr r3, [r3, #44] ; 0x2c
8011164: 687a ldr r2, [r7, #4]
8011166: 8e52 ldrh r2, [r2, #50] ; 0x32
8011168: f5b2 6f86 cmp.w r2, #1072 ; 0x430
801116c: bf28 it cs
801116e: f44f 6286 movcs.w r2, #1072 ; 0x430
8011172: b292 uxth r2, r2
8011174: 4413 add r3, r2
8011176: 68fa ldr r2, [r7, #12]
8011178: 1ad3 subs r3, r2, r3
801117a: 2b00 cmp r3, #0
801117c: db08 blt.n 8011190 <tcp_update_rcv_ann_wnd+0x58>
/* we can advertise more window */
pcb->rcv_ann_wnd = pcb->rcv_wnd;
801117e: 687b ldr r3, [r7, #4]
8011180: 8d1a ldrh r2, [r3, #40] ; 0x28
8011182: 687b ldr r3, [r7, #4]
8011184: 855a strh r2, [r3, #42] ; 0x2a
return new_right_edge - pcb->rcv_ann_right_edge;
8011186: 687b ldr r3, [r7, #4]
8011188: 6adb ldr r3, [r3, #44] ; 0x2c
801118a: 68fa ldr r2, [r7, #12]
801118c: 1ad3 subs r3, r2, r3
801118e: e020 b.n 80111d2 <tcp_update_rcv_ann_wnd+0x9a>
} else {
if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
8011190: 687b ldr r3, [r7, #4]
8011192: 6a5a ldr r2, [r3, #36] ; 0x24
8011194: 687b ldr r3, [r7, #4]
8011196: 6adb ldr r3, [r3, #44] ; 0x2c
8011198: 1ad3 subs r3, r2, r3
801119a: 2b00 cmp r3, #0
801119c: dd03 ble.n 80111a6 <tcp_update_rcv_ann_wnd+0x6e>
/* Can happen due to other end sending out of advertised window,
* but within actual available (but not yet advertised) window */
pcb->rcv_ann_wnd = 0;
801119e: 687b ldr r3, [r7, #4]
80111a0: 2200 movs r2, #0
80111a2: 855a strh r2, [r3, #42] ; 0x2a
80111a4: e014 b.n 80111d0 <tcp_update_rcv_ann_wnd+0x98>
} else {
/* keep the right edge of window constant */
u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
80111a6: 687b ldr r3, [r7, #4]
80111a8: 6ada ldr r2, [r3, #44] ; 0x2c
80111aa: 687b ldr r3, [r7, #4]
80111ac: 6a5b ldr r3, [r3, #36] ; 0x24
80111ae: 1ad3 subs r3, r2, r3
80111b0: 60bb str r3, [r7, #8]
#if !LWIP_WND_SCALE
LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
80111b2: 68bb ldr r3, [r7, #8]
80111b4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80111b8: d306 bcc.n 80111c8 <tcp_update_rcv_ann_wnd+0x90>
80111ba: 4b08 ldr r3, [pc, #32] ; (80111dc <tcp_update_rcv_ann_wnd+0xa4>)
80111bc: f240 32b6 movw r2, #950 ; 0x3b6
80111c0: 4909 ldr r1, [pc, #36] ; (80111e8 <tcp_update_rcv_ann_wnd+0xb0>)
80111c2: 4808 ldr r0, [pc, #32] ; (80111e4 <tcp_update_rcv_ann_wnd+0xac>)
80111c4: f009 ff26 bl 801b014 <iprintf>
#endif
pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
80111c8: 68bb ldr r3, [r7, #8]
80111ca: b29a uxth r2, r3
80111cc: 687b ldr r3, [r7, #4]
80111ce: 855a strh r2, [r3, #42] ; 0x2a
}
return 0;
80111d0: 2300 movs r3, #0
}
}
80111d2: 4618 mov r0, r3
80111d4: 3710 adds r7, #16
80111d6: 46bd mov sp, r7
80111d8: bd80 pop {r7, pc}
80111da: bf00 nop
80111dc: 0801cb48 .word 0x0801cb48
80111e0: 0801cda4 .word 0x0801cda4
80111e4: 0801cb8c .word 0x0801cb8c
80111e8: 0801cdc8 .word 0x0801cdc8
080111ec <tcp_recved>:
* @param pcb the tcp_pcb for which data is read
* @param len the amount of bytes that have been read by the application
*/
void
tcp_recved(struct tcp_pcb *pcb, u16_t len)
{
80111ec: b580 push {r7, lr}
80111ee: b084 sub sp, #16
80111f0: af00 add r7, sp, #0
80111f2: 6078 str r0, [r7, #4]
80111f4: 460b mov r3, r1
80111f6: 807b strh r3, [r7, #2]
u32_t wnd_inflation;
tcpwnd_size_t rcv_wnd;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
80111f8: 687b ldr r3, [r7, #4]
80111fa: 2b00 cmp r3, #0
80111fc: d107 bne.n 801120e <tcp_recved+0x22>
80111fe: 4b1f ldr r3, [pc, #124] ; (801127c <tcp_recved+0x90>)
8011200: f240 32cf movw r2, #975 ; 0x3cf
8011204: 491e ldr r1, [pc, #120] ; (8011280 <tcp_recved+0x94>)
8011206: 481f ldr r0, [pc, #124] ; (8011284 <tcp_recved+0x98>)
8011208: f009 ff04 bl 801b014 <iprintf>
801120c: e032 b.n 8011274 <tcp_recved+0x88>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
801120e: 687b ldr r3, [r7, #4]
8011210: 7d1b ldrb r3, [r3, #20]
8011212: 2b01 cmp r3, #1
8011214: d106 bne.n 8011224 <tcp_recved+0x38>
8011216: 4b19 ldr r3, [pc, #100] ; (801127c <tcp_recved+0x90>)
8011218: f240 32d3 movw r2, #979 ; 0x3d3
801121c: 491a ldr r1, [pc, #104] ; (8011288 <tcp_recved+0x9c>)
801121e: 4819 ldr r0, [pc, #100] ; (8011284 <tcp_recved+0x98>)
8011220: f009 fef8 bl 801b014 <iprintf>
pcb->state != LISTEN);
rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
8011224: 687b ldr r3, [r7, #4]
8011226: 8d1a ldrh r2, [r3, #40] ; 0x28
8011228: 887b ldrh r3, [r7, #2]
801122a: 4413 add r3, r2
801122c: 81fb strh r3, [r7, #14]
if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
801122e: 89fb ldrh r3, [r7, #14]
8011230: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011234: d804 bhi.n 8011240 <tcp_recved+0x54>
8011236: 687b ldr r3, [r7, #4]
8011238: 8d1b ldrh r3, [r3, #40] ; 0x28
801123a: 89fa ldrh r2, [r7, #14]
801123c: 429a cmp r2, r3
801123e: d204 bcs.n 801124a <tcp_recved+0x5e>
/* window got too big or tcpwnd_size_t overflow */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
pcb->rcv_wnd = TCP_WND_MAX(pcb);
8011240: 687b ldr r3, [r7, #4]
8011242: f44f 6206 mov.w r2, #2144 ; 0x860
8011246: 851a strh r2, [r3, #40] ; 0x28
8011248: e002 b.n 8011250 <tcp_recved+0x64>
} else {
pcb->rcv_wnd = rcv_wnd;
801124a: 687b ldr r3, [r7, #4]
801124c: 89fa ldrh r2, [r7, #14]
801124e: 851a strh r2, [r3, #40] ; 0x28
}
wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
8011250: 6878 ldr r0, [r7, #4]
8011252: f7ff ff71 bl 8011138 <tcp_update_rcv_ann_wnd>
8011256: 60b8 str r0, [r7, #8]
/* If the change in the right edge of window is significant (default
* watermark is TCP_WND/4), then send an explicit update now.
* Otherwise wait for a packet to be sent in the normal course of
* events (or more window to be available later) */
if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
8011258: 68bb ldr r3, [r7, #8]
801125a: f5b3 7f06 cmp.w r3, #536 ; 0x218
801125e: d309 bcc.n 8011274 <tcp_recved+0x88>
tcp_ack_now(pcb);
8011260: 687b ldr r3, [r7, #4]
8011262: 8b5b ldrh r3, [r3, #26]
8011264: f043 0302 orr.w r3, r3, #2
8011268: b29a uxth r2, r3
801126a: 687b ldr r3, [r7, #4]
801126c: 835a strh r2, [r3, #26]
tcp_output(pcb);
801126e: 6878 ldr r0, [r7, #4]
8011270: f003 fe38 bl 8014ee4 <tcp_output>
}
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
}
8011274: 3710 adds r7, #16
8011276: 46bd mov sp, r7
8011278: bd80 pop {r7, pc}
801127a: bf00 nop
801127c: 0801cb48 .word 0x0801cb48
8011280: 0801cde4 .word 0x0801cde4
8011284: 0801cb8c .word 0x0801cb8c
8011288: 0801cdfc .word 0x0801cdfc
0801128c <tcp_slowtmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_slowtmr(void)
{
801128c: b5b0 push {r4, r5, r7, lr}
801128e: b090 sub sp, #64 ; 0x40
8011290: af04 add r7, sp, #16
tcpwnd_size_t eff_wnd;
u8_t pcb_remove; /* flag if a PCB should be removed */
u8_t pcb_reset; /* flag if a RST should be sent when removing */
err_t err;
err = ERR_OK;
8011292: 2300 movs r3, #0
8011294: f887 3025 strb.w r3, [r7, #37] ; 0x25
++tcp_ticks;
8011298: 4b94 ldr r3, [pc, #592] ; (80114ec <tcp_slowtmr+0x260>)
801129a: 681b ldr r3, [r3, #0]
801129c: 3301 adds r3, #1
801129e: 4a93 ldr r2, [pc, #588] ; (80114ec <tcp_slowtmr+0x260>)
80112a0: 6013 str r3, [r2, #0]
++tcp_timer_ctr;
80112a2: 4b93 ldr r3, [pc, #588] ; (80114f0 <tcp_slowtmr+0x264>)
80112a4: 781b ldrb r3, [r3, #0]
80112a6: 3301 adds r3, #1
80112a8: b2da uxtb r2, r3
80112aa: 4b91 ldr r3, [pc, #580] ; (80114f0 <tcp_slowtmr+0x264>)
80112ac: 701a strb r2, [r3, #0]
tcp_slowtmr_start:
/* Steps through all of the active PCBs. */
prev = NULL;
80112ae: 2300 movs r3, #0
80112b0: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_active_pcbs;
80112b2: 4b90 ldr r3, [pc, #576] ; (80114f4 <tcp_slowtmr+0x268>)
80112b4: 681b ldr r3, [r3, #0]
80112b6: 62fb str r3, [r7, #44] ; 0x2c
if (pcb == NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
}
while (pcb != NULL) {
80112b8: e29d b.n 80117f6 <tcp_slowtmr+0x56a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
80112ba: 6afb ldr r3, [r7, #44] ; 0x2c
80112bc: 7d1b ldrb r3, [r3, #20]
80112be: 2b00 cmp r3, #0
80112c0: d106 bne.n 80112d0 <tcp_slowtmr+0x44>
80112c2: 4b8d ldr r3, [pc, #564] ; (80114f8 <tcp_slowtmr+0x26c>)
80112c4: f240 42be movw r2, #1214 ; 0x4be
80112c8: 498c ldr r1, [pc, #560] ; (80114fc <tcp_slowtmr+0x270>)
80112ca: 488d ldr r0, [pc, #564] ; (8011500 <tcp_slowtmr+0x274>)
80112cc: f009 fea2 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
80112d0: 6afb ldr r3, [r7, #44] ; 0x2c
80112d2: 7d1b ldrb r3, [r3, #20]
80112d4: 2b01 cmp r3, #1
80112d6: d106 bne.n 80112e6 <tcp_slowtmr+0x5a>
80112d8: 4b87 ldr r3, [pc, #540] ; (80114f8 <tcp_slowtmr+0x26c>)
80112da: f240 42bf movw r2, #1215 ; 0x4bf
80112de: 4989 ldr r1, [pc, #548] ; (8011504 <tcp_slowtmr+0x278>)
80112e0: 4887 ldr r0, [pc, #540] ; (8011500 <tcp_slowtmr+0x274>)
80112e2: f009 fe97 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
80112e6: 6afb ldr r3, [r7, #44] ; 0x2c
80112e8: 7d1b ldrb r3, [r3, #20]
80112ea: 2b0a cmp r3, #10
80112ec: d106 bne.n 80112fc <tcp_slowtmr+0x70>
80112ee: 4b82 ldr r3, [pc, #520] ; (80114f8 <tcp_slowtmr+0x26c>)
80112f0: f44f 6298 mov.w r2, #1216 ; 0x4c0
80112f4: 4984 ldr r1, [pc, #528] ; (8011508 <tcp_slowtmr+0x27c>)
80112f6: 4882 ldr r0, [pc, #520] ; (8011500 <tcp_slowtmr+0x274>)
80112f8: f009 fe8c bl 801b014 <iprintf>
if (pcb->last_timer == tcp_timer_ctr) {
80112fc: 6afb ldr r3, [r7, #44] ; 0x2c
80112fe: 7f9a ldrb r2, [r3, #30]
8011300: 4b7b ldr r3, [pc, #492] ; (80114f0 <tcp_slowtmr+0x264>)
8011302: 781b ldrb r3, [r3, #0]
8011304: 429a cmp r2, r3
8011306: d105 bne.n 8011314 <tcp_slowtmr+0x88>
/* skip this pcb, we have already processed it */
prev = pcb;
8011308: 6afb ldr r3, [r7, #44] ; 0x2c
801130a: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
801130c: 6afb ldr r3, [r7, #44] ; 0x2c
801130e: 68db ldr r3, [r3, #12]
8011310: 62fb str r3, [r7, #44] ; 0x2c
continue;
8011312: e270 b.n 80117f6 <tcp_slowtmr+0x56a>
}
pcb->last_timer = tcp_timer_ctr;
8011314: 4b76 ldr r3, [pc, #472] ; (80114f0 <tcp_slowtmr+0x264>)
8011316: 781a ldrb r2, [r3, #0]
8011318: 6afb ldr r3, [r7, #44] ; 0x2c
801131a: 779a strb r2, [r3, #30]
pcb_remove = 0;
801131c: 2300 movs r3, #0
801131e: f887 3027 strb.w r3, [r7, #39] ; 0x27
pcb_reset = 0;
8011322: 2300 movs r3, #0
8011324: f887 3026 strb.w r3, [r7, #38] ; 0x26
if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
8011328: 6afb ldr r3, [r7, #44] ; 0x2c
801132a: 7d1b ldrb r3, [r3, #20]
801132c: 2b02 cmp r3, #2
801132e: d10a bne.n 8011346 <tcp_slowtmr+0xba>
8011330: 6afb ldr r3, [r7, #44] ; 0x2c
8011332: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8011336: 2b05 cmp r3, #5
8011338: d905 bls.n 8011346 <tcp_slowtmr+0xba>
++pcb_remove;
801133a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801133e: 3301 adds r3, #1
8011340: f887 3027 strb.w r3, [r7, #39] ; 0x27
8011344: e11e b.n 8011584 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
} else if (pcb->nrtx >= TCP_MAXRTX) {
8011346: 6afb ldr r3, [r7, #44] ; 0x2c
8011348: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801134c: 2b0b cmp r3, #11
801134e: d905 bls.n 801135c <tcp_slowtmr+0xd0>
++pcb_remove;
8011350: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011354: 3301 adds r3, #1
8011356: f887 3027 strb.w r3, [r7, #39] ; 0x27
801135a: e113 b.n 8011584 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
} else {
if (pcb->persist_backoff > 0) {
801135c: 6afb ldr r3, [r7, #44] ; 0x2c
801135e: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011362: 2b00 cmp r3, #0
8011364: d075 beq.n 8011452 <tcp_slowtmr+0x1c6>
LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
8011366: 6afb ldr r3, [r7, #44] ; 0x2c
8011368: 6f1b ldr r3, [r3, #112] ; 0x70
801136a: 2b00 cmp r3, #0
801136c: d006 beq.n 801137c <tcp_slowtmr+0xf0>
801136e: 4b62 ldr r3, [pc, #392] ; (80114f8 <tcp_slowtmr+0x26c>)
8011370: f240 42d4 movw r2, #1236 ; 0x4d4
8011374: 4965 ldr r1, [pc, #404] ; (801150c <tcp_slowtmr+0x280>)
8011376: 4862 ldr r0, [pc, #392] ; (8011500 <tcp_slowtmr+0x274>)
8011378: f009 fe4c bl 801b014 <iprintf>
LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
801137c: 6afb ldr r3, [r7, #44] ; 0x2c
801137e: 6edb ldr r3, [r3, #108] ; 0x6c
8011380: 2b00 cmp r3, #0
8011382: d106 bne.n 8011392 <tcp_slowtmr+0x106>
8011384: 4b5c ldr r3, [pc, #368] ; (80114f8 <tcp_slowtmr+0x26c>)
8011386: f240 42d5 movw r2, #1237 ; 0x4d5
801138a: 4961 ldr r1, [pc, #388] ; (8011510 <tcp_slowtmr+0x284>)
801138c: 485c ldr r0, [pc, #368] ; (8011500 <tcp_slowtmr+0x274>)
801138e: f009 fe41 bl 801b014 <iprintf>
if (pcb->persist_probe >= TCP_MAXRTX) {
8011392: 6afb ldr r3, [r7, #44] ; 0x2c
8011394: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8011398: 2b0b cmp r3, #11
801139a: d905 bls.n 80113a8 <tcp_slowtmr+0x11c>
++pcb_remove; /* max probes reached */
801139c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80113a0: 3301 adds r3, #1
80113a2: f887 3027 strb.w r3, [r7, #39] ; 0x27
80113a6: e0ed b.n 8011584 <tcp_slowtmr+0x2f8>
} else {
u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
80113a8: 6afb ldr r3, [r7, #44] ; 0x2c
80113aa: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
80113ae: 3b01 subs r3, #1
80113b0: 4a58 ldr r2, [pc, #352] ; (8011514 <tcp_slowtmr+0x288>)
80113b2: 5cd3 ldrb r3, [r2, r3]
80113b4: 747b strb r3, [r7, #17]
if (pcb->persist_cnt < backoff_cnt) {
80113b6: 6afb ldr r3, [r7, #44] ; 0x2c
80113b8: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113bc: 7c7a ldrb r2, [r7, #17]
80113be: 429a cmp r2, r3
80113c0: d907 bls.n 80113d2 <tcp_slowtmr+0x146>
pcb->persist_cnt++;
80113c2: 6afb ldr r3, [r7, #44] ; 0x2c
80113c4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113c8: 3301 adds r3, #1
80113ca: b2da uxtb r2, r3
80113cc: 6afb ldr r3, [r7, #44] ; 0x2c
80113ce: f883 2098 strb.w r2, [r3, #152] ; 0x98
}
if (pcb->persist_cnt >= backoff_cnt) {
80113d2: 6afb ldr r3, [r7, #44] ; 0x2c
80113d4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113d8: 7c7a ldrb r2, [r7, #17]
80113da: 429a cmp r2, r3
80113dc: f200 80d2 bhi.w 8011584 <tcp_slowtmr+0x2f8>
int next_slot = 1; /* increment timer to next slot */
80113e0: 2301 movs r3, #1
80113e2: 623b str r3, [r7, #32]
/* If snd_wnd is zero, send 1 byte probes */
if (pcb->snd_wnd == 0) {
80113e4: 6afb ldr r3, [r7, #44] ; 0x2c
80113e6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
80113ea: 2b00 cmp r3, #0
80113ec: d108 bne.n 8011400 <tcp_slowtmr+0x174>
if (tcp_zero_window_probe(pcb) != ERR_OK) {
80113ee: 6af8 ldr r0, [r7, #44] ; 0x2c
80113f0: f004 fc32 bl 8015c58 <tcp_zero_window_probe>
80113f4: 4603 mov r3, r0
80113f6: 2b00 cmp r3, #0
80113f8: d014 beq.n 8011424 <tcp_slowtmr+0x198>
next_slot = 0; /* try probe again with current slot */
80113fa: 2300 movs r3, #0
80113fc: 623b str r3, [r7, #32]
80113fe: e011 b.n 8011424 <tcp_slowtmr+0x198>
}
/* snd_wnd not fully closed, split unsent head and fill window */
} else {
if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
8011400: 6afb ldr r3, [r7, #44] ; 0x2c
8011402: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8011406: 4619 mov r1, r3
8011408: 6af8 ldr r0, [r7, #44] ; 0x2c
801140a: f003 fae5 bl 80149d8 <tcp_split_unsent_seg>
801140e: 4603 mov r3, r0
8011410: 2b00 cmp r3, #0
8011412: d107 bne.n 8011424 <tcp_slowtmr+0x198>
if (tcp_output(pcb) == ERR_OK) {
8011414: 6af8 ldr r0, [r7, #44] ; 0x2c
8011416: f003 fd65 bl 8014ee4 <tcp_output>
801141a: 4603 mov r3, r0
801141c: 2b00 cmp r3, #0
801141e: d101 bne.n 8011424 <tcp_slowtmr+0x198>
/* sending will cancel persist timer, else retry with current slot */
next_slot = 0;
8011420: 2300 movs r3, #0
8011422: 623b str r3, [r7, #32]
}
}
}
if (next_slot) {
8011424: 6a3b ldr r3, [r7, #32]
8011426: 2b00 cmp r3, #0
8011428: f000 80ac beq.w 8011584 <tcp_slowtmr+0x2f8>
pcb->persist_cnt = 0;
801142c: 6afb ldr r3, [r7, #44] ; 0x2c
801142e: 2200 movs r2, #0
8011430: f883 2098 strb.w r2, [r3, #152] ; 0x98
if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
8011434: 6afb ldr r3, [r7, #44] ; 0x2c
8011436: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
801143a: 2b06 cmp r3, #6
801143c: f200 80a2 bhi.w 8011584 <tcp_slowtmr+0x2f8>
pcb->persist_backoff++;
8011440: 6afb ldr r3, [r7, #44] ; 0x2c
8011442: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011446: 3301 adds r3, #1
8011448: b2da uxtb r2, r3
801144a: 6afb ldr r3, [r7, #44] ; 0x2c
801144c: f883 2099 strb.w r2, [r3, #153] ; 0x99
8011450: e098 b.n 8011584 <tcp_slowtmr+0x2f8>
}
}
}
} else {
/* Increase the retransmission timer if it is running */
if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
8011452: 6afb ldr r3, [r7, #44] ; 0x2c
8011454: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011458: 2b00 cmp r3, #0
801145a: db0f blt.n 801147c <tcp_slowtmr+0x1f0>
801145c: 6afb ldr r3, [r7, #44] ; 0x2c
801145e: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011462: f647 72ff movw r2, #32767 ; 0x7fff
8011466: 4293 cmp r3, r2
8011468: d008 beq.n 801147c <tcp_slowtmr+0x1f0>
++pcb->rtime;
801146a: 6afb ldr r3, [r7, #44] ; 0x2c
801146c: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011470: b29b uxth r3, r3
8011472: 3301 adds r3, #1
8011474: b29b uxth r3, r3
8011476: b21a sxth r2, r3
8011478: 6afb ldr r3, [r7, #44] ; 0x2c
801147a: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rtime >= pcb->rto) {
801147c: 6afb ldr r3, [r7, #44] ; 0x2c
801147e: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30
8011482: 6afb ldr r3, [r7, #44] ; 0x2c
8011484: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
8011488: 429a cmp r2, r3
801148a: db7b blt.n 8011584 <tcp_slowtmr+0x2f8>
" pcb->rto %"S16_F"\n",
pcb->rtime, pcb->rto));
/* If prepare phase fails but we have unsent data but no unacked data,
still execute the backoff calculations below, as this means we somehow
failed to send segment. */
if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
801148c: 6af8 ldr r0, [r7, #44] ; 0x2c
801148e: f004 f821 bl 80154d4 <tcp_rexmit_rto_prepare>
8011492: 4603 mov r3, r0
8011494: 2b00 cmp r3, #0
8011496: d007 beq.n 80114a8 <tcp_slowtmr+0x21c>
8011498: 6afb ldr r3, [r7, #44] ; 0x2c
801149a: 6f1b ldr r3, [r3, #112] ; 0x70
801149c: 2b00 cmp r3, #0
801149e: d171 bne.n 8011584 <tcp_slowtmr+0x2f8>
80114a0: 6afb ldr r3, [r7, #44] ; 0x2c
80114a2: 6edb ldr r3, [r3, #108] ; 0x6c
80114a4: 2b00 cmp r3, #0
80114a6: d06d beq.n 8011584 <tcp_slowtmr+0x2f8>
/* Double retransmission time-out unless we are trying to
* connect to somebody (i.e., we are in SYN_SENT). */
if (pcb->state != SYN_SENT) {
80114a8: 6afb ldr r3, [r7, #44] ; 0x2c
80114aa: 7d1b ldrb r3, [r3, #20]
80114ac: 2b02 cmp r3, #2
80114ae: d03a beq.n 8011526 <tcp_slowtmr+0x29a>
u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
80114b0: 6afb ldr r3, [r7, #44] ; 0x2c
80114b2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80114b6: 2b0c cmp r3, #12
80114b8: bf28 it cs
80114ba: 230c movcs r3, #12
80114bc: 76fb strb r3, [r7, #27]
int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
80114be: 6afb ldr r3, [r7, #44] ; 0x2c
80114c0: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
80114c4: 10db asrs r3, r3, #3
80114c6: b21b sxth r3, r3
80114c8: 461a mov r2, r3
80114ca: 6afb ldr r3, [r7, #44] ; 0x2c
80114cc: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
80114d0: 4413 add r3, r2
80114d2: 7efa ldrb r2, [r7, #27]
80114d4: 4910 ldr r1, [pc, #64] ; (8011518 <tcp_slowtmr+0x28c>)
80114d6: 5c8a ldrb r2, [r1, r2]
80114d8: 4093 lsls r3, r2
80114da: 617b str r3, [r7, #20]
pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
80114dc: 697b ldr r3, [r7, #20]
80114de: f647 72fe movw r2, #32766 ; 0x7ffe
80114e2: 4293 cmp r3, r2
80114e4: dc1a bgt.n 801151c <tcp_slowtmr+0x290>
80114e6: 697b ldr r3, [r7, #20]
80114e8: b21a sxth r2, r3
80114ea: e019 b.n 8011520 <tcp_slowtmr+0x294>
80114ec: 2000f5c4 .word 0x2000f5c4
80114f0: 2000872a .word 0x2000872a
80114f4: 2000f5c0 .word 0x2000f5c0
80114f8: 0801cb48 .word 0x0801cb48
80114fc: 0801ce8c .word 0x0801ce8c
8011500: 0801cb8c .word 0x0801cb8c
8011504: 0801ceb8 .word 0x0801ceb8
8011508: 0801cee4 .word 0x0801cee4
801150c: 0801cf14 .word 0x0801cf14
8011510: 0801cf48 .word 0x0801cf48
8011514: 08020e28 .word 0x08020e28
8011518: 08020e18 .word 0x08020e18
801151c: f647 72ff movw r2, #32767 ; 0x7fff
8011520: 6afb ldr r3, [r7, #44] ; 0x2c
8011522: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
}
/* Reset the retransmission timer. */
pcb->rtime = 0;
8011526: 6afb ldr r3, [r7, #44] ; 0x2c
8011528: 2200 movs r2, #0
801152a: 861a strh r2, [r3, #48] ; 0x30
/* Reduce congestion window and ssthresh. */
eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
801152c: 6afb ldr r3, [r7, #44] ; 0x2c
801152e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8011532: 6afb ldr r3, [r7, #44] ; 0x2c
8011534: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8011538: 4293 cmp r3, r2
801153a: bf28 it cs
801153c: 4613 movcs r3, r2
801153e: 827b strh r3, [r7, #18]
pcb->ssthresh = eff_wnd >> 1;
8011540: 8a7b ldrh r3, [r7, #18]
8011542: 085b lsrs r3, r3, #1
8011544: b29a uxth r2, r3
8011546: 6afb ldr r3, [r7, #44] ; 0x2c
8011548: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
801154c: 6afb ldr r3, [r7, #44] ; 0x2c
801154e: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
8011552: 6afb ldr r3, [r7, #44] ; 0x2c
8011554: 8e5b ldrh r3, [r3, #50] ; 0x32
8011556: 005b lsls r3, r3, #1
8011558: b29b uxth r3, r3
801155a: 429a cmp r2, r3
801155c: d206 bcs.n 801156c <tcp_slowtmr+0x2e0>
pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
801155e: 6afb ldr r3, [r7, #44] ; 0x2c
8011560: 8e5b ldrh r3, [r3, #50] ; 0x32
8011562: 005b lsls r3, r3, #1
8011564: b29a uxth r2, r3
8011566: 6afb ldr r3, [r7, #44] ; 0x2c
8011568: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->mss;
801156c: 6afb ldr r3, [r7, #44] ; 0x2c
801156e: 8e5a ldrh r2, [r3, #50] ; 0x32
8011570: 6afb ldr r3, [r7, #44] ; 0x2c
8011572: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
pcb->bytes_acked = 0;
8011576: 6afb ldr r3, [r7, #44] ; 0x2c
8011578: 2200 movs r2, #0
801157a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
/* The following needs to be called AFTER cwnd is set to one
mss - STJ */
tcp_rexmit_rto_commit(pcb);
801157e: 6af8 ldr r0, [r7, #44] ; 0x2c
8011580: f004 f818 bl 80155b4 <tcp_rexmit_rto_commit>
}
}
}
}
/* Check if this PCB has stayed too long in FIN-WAIT-2 */
if (pcb->state == FIN_WAIT_2) {
8011584: 6afb ldr r3, [r7, #44] ; 0x2c
8011586: 7d1b ldrb r3, [r3, #20]
8011588: 2b06 cmp r3, #6
801158a: d111 bne.n 80115b0 <tcp_slowtmr+0x324>
/* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
if (pcb->flags & TF_RXCLOSED) {
801158c: 6afb ldr r3, [r7, #44] ; 0x2c
801158e: 8b5b ldrh r3, [r3, #26]
8011590: f003 0310 and.w r3, r3, #16
8011594: 2b00 cmp r3, #0
8011596: d00b beq.n 80115b0 <tcp_slowtmr+0x324>
/* PCB was fully closed (either through close() or SHUT_RDWR):
normal FIN-WAIT timeout handling. */
if ((u32_t)(tcp_ticks - pcb->tmr) >
8011598: 4b9c ldr r3, [pc, #624] ; (801180c <tcp_slowtmr+0x580>)
801159a: 681a ldr r2, [r3, #0]
801159c: 6afb ldr r3, [r7, #44] ; 0x2c
801159e: 6a1b ldr r3, [r3, #32]
80115a0: 1ad3 subs r3, r2, r3
80115a2: 2b28 cmp r3, #40 ; 0x28
80115a4: d904 bls.n 80115b0 <tcp_slowtmr+0x324>
TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
80115a6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80115aa: 3301 adds r3, #1
80115ac: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
}
/* Check if KEEPALIVE should be sent */
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
80115b0: 6afb ldr r3, [r7, #44] ; 0x2c
80115b2: 7a5b ldrb r3, [r3, #9]
80115b4: f003 0308 and.w r3, r3, #8
80115b8: 2b00 cmp r3, #0
80115ba: d04a beq.n 8011652 <tcp_slowtmr+0x3c6>
((pcb->state == ESTABLISHED) ||
80115bc: 6afb ldr r3, [r7, #44] ; 0x2c
80115be: 7d1b ldrb r3, [r3, #20]
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
80115c0: 2b04 cmp r3, #4
80115c2: d003 beq.n 80115cc <tcp_slowtmr+0x340>
(pcb->state == CLOSE_WAIT))) {
80115c4: 6afb ldr r3, [r7, #44] ; 0x2c
80115c6: 7d1b ldrb r3, [r3, #20]
((pcb->state == ESTABLISHED) ||
80115c8: 2b07 cmp r3, #7
80115ca: d142 bne.n 8011652 <tcp_slowtmr+0x3c6>
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115cc: 4b8f ldr r3, [pc, #572] ; (801180c <tcp_slowtmr+0x580>)
80115ce: 681a ldr r2, [r3, #0]
80115d0: 6afb ldr r3, [r7, #44] ; 0x2c
80115d2: 6a1b ldr r3, [r3, #32]
80115d4: 1ad2 subs r2, r2, r3
(pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
80115d6: 6afb ldr r3, [r7, #44] ; 0x2c
80115d8: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
80115dc: 4b8c ldr r3, [pc, #560] ; (8011810 <tcp_slowtmr+0x584>)
80115de: 440b add r3, r1
80115e0: 498c ldr r1, [pc, #560] ; (8011814 <tcp_slowtmr+0x588>)
80115e2: fba1 1303 umull r1, r3, r1, r3
80115e6: 095b lsrs r3, r3, #5
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115e8: 429a cmp r2, r3
80115ea: d90a bls.n 8011602 <tcp_slowtmr+0x376>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
++pcb_remove;
80115ec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80115f0: 3301 adds r3, #1
80115f2: f887 3027 strb.w r3, [r7, #39] ; 0x27
++pcb_reset;
80115f6: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80115fa: 3301 adds r3, #1
80115fc: f887 3026 strb.w r3, [r7, #38] ; 0x26
8011600: e027 b.n 8011652 <tcp_slowtmr+0x3c6>
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
8011602: 4b82 ldr r3, [pc, #520] ; (801180c <tcp_slowtmr+0x580>)
8011604: 681a ldr r2, [r3, #0]
8011606: 6afb ldr r3, [r7, #44] ; 0x2c
8011608: 6a1b ldr r3, [r3, #32]
801160a: 1ad2 subs r2, r2, r3
(pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
801160c: 6afb ldr r3, [r7, #44] ; 0x2c
801160e: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
8011612: 6afb ldr r3, [r7, #44] ; 0x2c
8011614: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
8011618: 4618 mov r0, r3
801161a: 4b7f ldr r3, [pc, #508] ; (8011818 <tcp_slowtmr+0x58c>)
801161c: fb03 f300 mul.w r3, r3, r0
8011620: 440b add r3, r1
/ TCP_SLOW_INTERVAL) {
8011622: 497c ldr r1, [pc, #496] ; (8011814 <tcp_slowtmr+0x588>)
8011624: fba1 1303 umull r1, r3, r1, r3
8011628: 095b lsrs r3, r3, #5
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
801162a: 429a cmp r2, r3
801162c: d911 bls.n 8011652 <tcp_slowtmr+0x3c6>
err = tcp_keepalive(pcb);
801162e: 6af8 ldr r0, [r7, #44] ; 0x2c
8011630: f004 fad2 bl 8015bd8 <tcp_keepalive>
8011634: 4603 mov r3, r0
8011636: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (err == ERR_OK) {
801163a: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
801163e: 2b00 cmp r3, #0
8011640: d107 bne.n 8011652 <tcp_slowtmr+0x3c6>
pcb->keep_cnt_sent++;
8011642: 6afb ldr r3, [r7, #44] ; 0x2c
8011644: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
8011648: 3301 adds r3, #1
801164a: b2da uxtb r2, r3
801164c: 6afb ldr r3, [r7, #44] ; 0x2c
801164e: f883 209b strb.w r2, [r3, #155] ; 0x9b
/* If this PCB has queued out of sequence data, but has been
inactive for too long, will drop the data (it will eventually
be retransmitted). */
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL &&
8011652: 6afb ldr r3, [r7, #44] ; 0x2c
8011654: 6f5b ldr r3, [r3, #116] ; 0x74
8011656: 2b00 cmp r3, #0
8011658: d011 beq.n 801167e <tcp_slowtmr+0x3f2>
(tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
801165a: 4b6c ldr r3, [pc, #432] ; (801180c <tcp_slowtmr+0x580>)
801165c: 681a ldr r2, [r3, #0]
801165e: 6afb ldr r3, [r7, #44] ; 0x2c
8011660: 6a1b ldr r3, [r3, #32]
8011662: 1ad2 subs r2, r2, r3
8011664: 6afb ldr r3, [r7, #44] ; 0x2c
8011666: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
801166a: 4619 mov r1, r3
801166c: 460b mov r3, r1
801166e: 005b lsls r3, r3, #1
8011670: 440b add r3, r1
8011672: 005b lsls r3, r3, #1
if (pcb->ooseq != NULL &&
8011674: 429a cmp r2, r3
8011676: d302 bcc.n 801167e <tcp_slowtmr+0x3f2>
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
tcp_free_ooseq(pcb);
8011678: 6af8 ldr r0, [r7, #44] ; 0x2c
801167a: f000 fdd9 bl 8012230 <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Check if this PCB has stayed too long in SYN-RCVD */
if (pcb->state == SYN_RCVD) {
801167e: 6afb ldr r3, [r7, #44] ; 0x2c
8011680: 7d1b ldrb r3, [r3, #20]
8011682: 2b03 cmp r3, #3
8011684: d10b bne.n 801169e <tcp_slowtmr+0x412>
if ((u32_t)(tcp_ticks - pcb->tmr) >
8011686: 4b61 ldr r3, [pc, #388] ; (801180c <tcp_slowtmr+0x580>)
8011688: 681a ldr r2, [r3, #0]
801168a: 6afb ldr r3, [r7, #44] ; 0x2c
801168c: 6a1b ldr r3, [r3, #32]
801168e: 1ad3 subs r3, r2, r3
8011690: 2b28 cmp r3, #40 ; 0x28
8011692: d904 bls.n 801169e <tcp_slowtmr+0x412>
TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
8011694: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011698: 3301 adds r3, #1
801169a: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
}
}
/* Check if this PCB has stayed too long in LAST-ACK */
if (pcb->state == LAST_ACK) {
801169e: 6afb ldr r3, [r7, #44] ; 0x2c
80116a0: 7d1b ldrb r3, [r3, #20]
80116a2: 2b09 cmp r3, #9
80116a4: d10b bne.n 80116be <tcp_slowtmr+0x432>
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
80116a6: 4b59 ldr r3, [pc, #356] ; (801180c <tcp_slowtmr+0x580>)
80116a8: 681a ldr r2, [r3, #0]
80116aa: 6afb ldr r3, [r7, #44] ; 0x2c
80116ac: 6a1b ldr r3, [r3, #32]
80116ae: 1ad3 subs r3, r2, r3
80116b0: 2bf0 cmp r3, #240 ; 0xf0
80116b2: d904 bls.n 80116be <tcp_slowtmr+0x432>
++pcb_remove;
80116b4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80116b8: 3301 adds r3, #1
80116ba: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
}
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
80116be: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80116c2: 2b00 cmp r3, #0
80116c4: d060 beq.n 8011788 <tcp_slowtmr+0x4fc>
struct tcp_pcb *pcb2;
#if LWIP_CALLBACK_API
tcp_err_fn err_fn = pcb->errf;
80116c6: 6afb ldr r3, [r7, #44] ; 0x2c
80116c8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80116cc: 60fb str r3, [r7, #12]
#endif /* LWIP_CALLBACK_API */
void *err_arg;
enum tcp_state last_state;
tcp_pcb_purge(pcb);
80116ce: 6af8 ldr r0, [r7, #44] ; 0x2c
80116d0: f000 fbfa bl 8011ec8 <tcp_pcb_purge>
/* Remove PCB from tcp_active_pcbs list. */
if (prev != NULL) {
80116d4: 6abb ldr r3, [r7, #40] ; 0x28
80116d6: 2b00 cmp r3, #0
80116d8: d010 beq.n 80116fc <tcp_slowtmr+0x470>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
80116da: 4b50 ldr r3, [pc, #320] ; (801181c <tcp_slowtmr+0x590>)
80116dc: 681b ldr r3, [r3, #0]
80116de: 6afa ldr r2, [r7, #44] ; 0x2c
80116e0: 429a cmp r2, r3
80116e2: d106 bne.n 80116f2 <tcp_slowtmr+0x466>
80116e4: 4b4e ldr r3, [pc, #312] ; (8011820 <tcp_slowtmr+0x594>)
80116e6: f240 526d movw r2, #1389 ; 0x56d
80116ea: 494e ldr r1, [pc, #312] ; (8011824 <tcp_slowtmr+0x598>)
80116ec: 484e ldr r0, [pc, #312] ; (8011828 <tcp_slowtmr+0x59c>)
80116ee: f009 fc91 bl 801b014 <iprintf>
prev->next = pcb->next;
80116f2: 6afb ldr r3, [r7, #44] ; 0x2c
80116f4: 68da ldr r2, [r3, #12]
80116f6: 6abb ldr r3, [r7, #40] ; 0x28
80116f8: 60da str r2, [r3, #12]
80116fa: e00f b.n 801171c <tcp_slowtmr+0x490>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
80116fc: 4b47 ldr r3, [pc, #284] ; (801181c <tcp_slowtmr+0x590>)
80116fe: 681b ldr r3, [r3, #0]
8011700: 6afa ldr r2, [r7, #44] ; 0x2c
8011702: 429a cmp r2, r3
8011704: d006 beq.n 8011714 <tcp_slowtmr+0x488>
8011706: 4b46 ldr r3, [pc, #280] ; (8011820 <tcp_slowtmr+0x594>)
8011708: f240 5271 movw r2, #1393 ; 0x571
801170c: 4947 ldr r1, [pc, #284] ; (801182c <tcp_slowtmr+0x5a0>)
801170e: 4846 ldr r0, [pc, #280] ; (8011828 <tcp_slowtmr+0x59c>)
8011710: f009 fc80 bl 801b014 <iprintf>
tcp_active_pcbs = pcb->next;
8011714: 6afb ldr r3, [r7, #44] ; 0x2c
8011716: 68db ldr r3, [r3, #12]
8011718: 4a40 ldr r2, [pc, #256] ; (801181c <tcp_slowtmr+0x590>)
801171a: 6013 str r3, [r2, #0]
}
if (pcb_reset) {
801171c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8011720: 2b00 cmp r3, #0
8011722: d013 beq.n 801174c <tcp_slowtmr+0x4c0>
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
8011724: 6afb ldr r3, [r7, #44] ; 0x2c
8011726: 6d18 ldr r0, [r3, #80] ; 0x50
8011728: 6afb ldr r3, [r7, #44] ; 0x2c
801172a: 6a5c ldr r4, [r3, #36] ; 0x24
801172c: 6afd ldr r5, [r7, #44] ; 0x2c
801172e: 6afb ldr r3, [r7, #44] ; 0x2c
8011730: 3304 adds r3, #4
8011732: 6afa ldr r2, [r7, #44] ; 0x2c
8011734: 8ad2 ldrh r2, [r2, #22]
8011736: 6af9 ldr r1, [r7, #44] ; 0x2c
8011738: 8b09 ldrh r1, [r1, #24]
801173a: 9102 str r1, [sp, #8]
801173c: 9201 str r2, [sp, #4]
801173e: 9300 str r3, [sp, #0]
8011740: 462b mov r3, r5
8011742: 4622 mov r2, r4
8011744: 4601 mov r1, r0
8011746: 6af8 ldr r0, [r7, #44] ; 0x2c
8011748: f004 f992 bl 8015a70 <tcp_rst>
pcb->local_port, pcb->remote_port);
}
err_arg = pcb->callback_arg;
801174c: 6afb ldr r3, [r7, #44] ; 0x2c
801174e: 691b ldr r3, [r3, #16]
8011750: 60bb str r3, [r7, #8]
last_state = pcb->state;
8011752: 6afb ldr r3, [r7, #44] ; 0x2c
8011754: 7d1b ldrb r3, [r3, #20]
8011756: 71fb strb r3, [r7, #7]
pcb2 = pcb;
8011758: 6afb ldr r3, [r7, #44] ; 0x2c
801175a: 603b str r3, [r7, #0]
pcb = pcb->next;
801175c: 6afb ldr r3, [r7, #44] ; 0x2c
801175e: 68db ldr r3, [r3, #12]
8011760: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
8011762: 6838 ldr r0, [r7, #0]
8011764: f7ff f9fc bl 8010b60 <tcp_free>
tcp_active_pcbs_changed = 0;
8011768: 4b31 ldr r3, [pc, #196] ; (8011830 <tcp_slowtmr+0x5a4>)
801176a: 2200 movs r2, #0
801176c: 701a strb r2, [r3, #0]
TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
801176e: 68fb ldr r3, [r7, #12]
8011770: 2b00 cmp r3, #0
8011772: d004 beq.n 801177e <tcp_slowtmr+0x4f2>
8011774: 68fb ldr r3, [r7, #12]
8011776: f06f 010c mvn.w r1, #12
801177a: 68b8 ldr r0, [r7, #8]
801177c: 4798 blx r3
if (tcp_active_pcbs_changed) {
801177e: 4b2c ldr r3, [pc, #176] ; (8011830 <tcp_slowtmr+0x5a4>)
8011780: 781b ldrb r3, [r3, #0]
8011782: 2b00 cmp r3, #0
8011784: d037 beq.n 80117f6 <tcp_slowtmr+0x56a>
goto tcp_slowtmr_start;
8011786: e592 b.n 80112ae <tcp_slowtmr+0x22>
}
} else {
/* get the 'next' element now and work with 'prev' below (in case of abort) */
prev = pcb;
8011788: 6afb ldr r3, [r7, #44] ; 0x2c
801178a: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
801178c: 6afb ldr r3, [r7, #44] ; 0x2c
801178e: 68db ldr r3, [r3, #12]
8011790: 62fb str r3, [r7, #44] ; 0x2c
/* We check if we should poll the connection. */
++prev->polltmr;
8011792: 6abb ldr r3, [r7, #40] ; 0x28
8011794: 7f1b ldrb r3, [r3, #28]
8011796: 3301 adds r3, #1
8011798: b2da uxtb r2, r3
801179a: 6abb ldr r3, [r7, #40] ; 0x28
801179c: 771a strb r2, [r3, #28]
if (prev->polltmr >= prev->pollinterval) {
801179e: 6abb ldr r3, [r7, #40] ; 0x28
80117a0: 7f1a ldrb r2, [r3, #28]
80117a2: 6abb ldr r3, [r7, #40] ; 0x28
80117a4: 7f5b ldrb r3, [r3, #29]
80117a6: 429a cmp r2, r3
80117a8: d325 bcc.n 80117f6 <tcp_slowtmr+0x56a>
prev->polltmr = 0;
80117aa: 6abb ldr r3, [r7, #40] ; 0x28
80117ac: 2200 movs r2, #0
80117ae: 771a strb r2, [r3, #28]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
tcp_active_pcbs_changed = 0;
80117b0: 4b1f ldr r3, [pc, #124] ; (8011830 <tcp_slowtmr+0x5a4>)
80117b2: 2200 movs r2, #0
80117b4: 701a strb r2, [r3, #0]
TCP_EVENT_POLL(prev, err);
80117b6: 6abb ldr r3, [r7, #40] ; 0x28
80117b8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80117bc: 2b00 cmp r3, #0
80117be: d00b beq.n 80117d8 <tcp_slowtmr+0x54c>
80117c0: 6abb ldr r3, [r7, #40] ; 0x28
80117c2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80117c6: 6aba ldr r2, [r7, #40] ; 0x28
80117c8: 6912 ldr r2, [r2, #16]
80117ca: 6ab9 ldr r1, [r7, #40] ; 0x28
80117cc: 4610 mov r0, r2
80117ce: 4798 blx r3
80117d0: 4603 mov r3, r0
80117d2: f887 3025 strb.w r3, [r7, #37] ; 0x25
80117d6: e002 b.n 80117de <tcp_slowtmr+0x552>
80117d8: 2300 movs r3, #0
80117da: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (tcp_active_pcbs_changed) {
80117de: 4b14 ldr r3, [pc, #80] ; (8011830 <tcp_slowtmr+0x5a4>)
80117e0: 781b ldrb r3, [r3, #0]
80117e2: 2b00 cmp r3, #0
80117e4: d000 beq.n 80117e8 <tcp_slowtmr+0x55c>
goto tcp_slowtmr_start;
80117e6: e562 b.n 80112ae <tcp_slowtmr+0x22>
}
/* if err == ERR_ABRT, 'prev' is already deallocated */
if (err == ERR_OK) {
80117e8: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
80117ec: 2b00 cmp r3, #0
80117ee: d102 bne.n 80117f6 <tcp_slowtmr+0x56a>
tcp_output(prev);
80117f0: 6ab8 ldr r0, [r7, #40] ; 0x28
80117f2: f003 fb77 bl 8014ee4 <tcp_output>
while (pcb != NULL) {
80117f6: 6afb ldr r3, [r7, #44] ; 0x2c
80117f8: 2b00 cmp r3, #0
80117fa: f47f ad5e bne.w 80112ba <tcp_slowtmr+0x2e>
}
}
/* Steps through all of the TIME-WAIT PCBs. */
prev = NULL;
80117fe: 2300 movs r3, #0
8011800: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_tw_pcbs;
8011802: 4b0c ldr r3, [pc, #48] ; (8011834 <tcp_slowtmr+0x5a8>)
8011804: 681b ldr r3, [r3, #0]
8011806: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
8011808: e069 b.n 80118de <tcp_slowtmr+0x652>
801180a: bf00 nop
801180c: 2000f5c4 .word 0x2000f5c4
8011810: 000a4cb8 .word 0x000a4cb8
8011814: 10624dd3 .word 0x10624dd3
8011818: 000124f8 .word 0x000124f8
801181c: 2000f5c0 .word 0x2000f5c0
8011820: 0801cb48 .word 0x0801cb48
8011824: 0801cf80 .word 0x0801cf80
8011828: 0801cb8c .word 0x0801cb8c
801182c: 0801cfac .word 0x0801cfac
8011830: 2000f5bc .word 0x2000f5bc
8011834: 2000f5d0 .word 0x2000f5d0
LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
8011838: 6afb ldr r3, [r7, #44] ; 0x2c
801183a: 7d1b ldrb r3, [r3, #20]
801183c: 2b0a cmp r3, #10
801183e: d006 beq.n 801184e <tcp_slowtmr+0x5c2>
8011840: 4b2a ldr r3, [pc, #168] ; (80118ec <tcp_slowtmr+0x660>)
8011842: f240 52a1 movw r2, #1441 ; 0x5a1
8011846: 492a ldr r1, [pc, #168] ; (80118f0 <tcp_slowtmr+0x664>)
8011848: 482a ldr r0, [pc, #168] ; (80118f4 <tcp_slowtmr+0x668>)
801184a: f009 fbe3 bl 801b014 <iprintf>
pcb_remove = 0;
801184e: 2300 movs r3, #0
8011850: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* Check if this PCB has stayed long enough in TIME-WAIT */
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
8011854: 4b28 ldr r3, [pc, #160] ; (80118f8 <tcp_slowtmr+0x66c>)
8011856: 681a ldr r2, [r3, #0]
8011858: 6afb ldr r3, [r7, #44] ; 0x2c
801185a: 6a1b ldr r3, [r3, #32]
801185c: 1ad3 subs r3, r2, r3
801185e: 2bf0 cmp r3, #240 ; 0xf0
8011860: d904 bls.n 801186c <tcp_slowtmr+0x5e0>
++pcb_remove;
8011862: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011866: 3301 adds r3, #1
8011868: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
801186c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011870: 2b00 cmp r3, #0
8011872: d02f beq.n 80118d4 <tcp_slowtmr+0x648>
struct tcp_pcb *pcb2;
tcp_pcb_purge(pcb);
8011874: 6af8 ldr r0, [r7, #44] ; 0x2c
8011876: f000 fb27 bl 8011ec8 <tcp_pcb_purge>
/* Remove PCB from tcp_tw_pcbs list. */
if (prev != NULL) {
801187a: 6abb ldr r3, [r7, #40] ; 0x28
801187c: 2b00 cmp r3, #0
801187e: d010 beq.n 80118a2 <tcp_slowtmr+0x616>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
8011880: 4b1e ldr r3, [pc, #120] ; (80118fc <tcp_slowtmr+0x670>)
8011882: 681b ldr r3, [r3, #0]
8011884: 6afa ldr r2, [r7, #44] ; 0x2c
8011886: 429a cmp r2, r3
8011888: d106 bne.n 8011898 <tcp_slowtmr+0x60c>
801188a: 4b18 ldr r3, [pc, #96] ; (80118ec <tcp_slowtmr+0x660>)
801188c: f240 52af movw r2, #1455 ; 0x5af
8011890: 491b ldr r1, [pc, #108] ; (8011900 <tcp_slowtmr+0x674>)
8011892: 4818 ldr r0, [pc, #96] ; (80118f4 <tcp_slowtmr+0x668>)
8011894: f009 fbbe bl 801b014 <iprintf>
prev->next = pcb->next;
8011898: 6afb ldr r3, [r7, #44] ; 0x2c
801189a: 68da ldr r2, [r3, #12]
801189c: 6abb ldr r3, [r7, #40] ; 0x28
801189e: 60da str r2, [r3, #12]
80118a0: e00f b.n 80118c2 <tcp_slowtmr+0x636>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
80118a2: 4b16 ldr r3, [pc, #88] ; (80118fc <tcp_slowtmr+0x670>)
80118a4: 681b ldr r3, [r3, #0]
80118a6: 6afa ldr r2, [r7, #44] ; 0x2c
80118a8: 429a cmp r2, r3
80118aa: d006 beq.n 80118ba <tcp_slowtmr+0x62e>
80118ac: 4b0f ldr r3, [pc, #60] ; (80118ec <tcp_slowtmr+0x660>)
80118ae: f240 52b3 movw r2, #1459 ; 0x5b3
80118b2: 4914 ldr r1, [pc, #80] ; (8011904 <tcp_slowtmr+0x678>)
80118b4: 480f ldr r0, [pc, #60] ; (80118f4 <tcp_slowtmr+0x668>)
80118b6: f009 fbad bl 801b014 <iprintf>
tcp_tw_pcbs = pcb->next;
80118ba: 6afb ldr r3, [r7, #44] ; 0x2c
80118bc: 68db ldr r3, [r3, #12]
80118be: 4a0f ldr r2, [pc, #60] ; (80118fc <tcp_slowtmr+0x670>)
80118c0: 6013 str r3, [r2, #0]
}
pcb2 = pcb;
80118c2: 6afb ldr r3, [r7, #44] ; 0x2c
80118c4: 61fb str r3, [r7, #28]
pcb = pcb->next;
80118c6: 6afb ldr r3, [r7, #44] ; 0x2c
80118c8: 68db ldr r3, [r3, #12]
80118ca: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
80118cc: 69f8 ldr r0, [r7, #28]
80118ce: f7ff f947 bl 8010b60 <tcp_free>
80118d2: e004 b.n 80118de <tcp_slowtmr+0x652>
} else {
prev = pcb;
80118d4: 6afb ldr r3, [r7, #44] ; 0x2c
80118d6: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
80118d8: 6afb ldr r3, [r7, #44] ; 0x2c
80118da: 68db ldr r3, [r3, #12]
80118dc: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
80118de: 6afb ldr r3, [r7, #44] ; 0x2c
80118e0: 2b00 cmp r3, #0
80118e2: d1a9 bne.n 8011838 <tcp_slowtmr+0x5ac>
}
}
}
80118e4: bf00 nop
80118e6: 3730 adds r7, #48 ; 0x30
80118e8: 46bd mov sp, r7
80118ea: bdb0 pop {r4, r5, r7, pc}
80118ec: 0801cb48 .word 0x0801cb48
80118f0: 0801cfd8 .word 0x0801cfd8
80118f4: 0801cb8c .word 0x0801cb8c
80118f8: 2000f5c4 .word 0x2000f5c4
80118fc: 2000f5d0 .word 0x2000f5d0
8011900: 0801d008 .word 0x0801d008
8011904: 0801d030 .word 0x0801d030
08011908 <tcp_fasttmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_fasttmr(void)
{
8011908: b580 push {r7, lr}
801190a: b082 sub sp, #8
801190c: af00 add r7, sp, #0
struct tcp_pcb *pcb;
++tcp_timer_ctr;
801190e: 4b2d ldr r3, [pc, #180] ; (80119c4 <tcp_fasttmr+0xbc>)
8011910: 781b ldrb r3, [r3, #0]
8011912: 3301 adds r3, #1
8011914: b2da uxtb r2, r3
8011916: 4b2b ldr r3, [pc, #172] ; (80119c4 <tcp_fasttmr+0xbc>)
8011918: 701a strb r2, [r3, #0]
tcp_fasttmr_start:
pcb = tcp_active_pcbs;
801191a: 4b2b ldr r3, [pc, #172] ; (80119c8 <tcp_fasttmr+0xc0>)
801191c: 681b ldr r3, [r3, #0]
801191e: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011920: e048 b.n 80119b4 <tcp_fasttmr+0xac>
if (pcb->last_timer != tcp_timer_ctr) {
8011922: 687b ldr r3, [r7, #4]
8011924: 7f9a ldrb r2, [r3, #30]
8011926: 4b27 ldr r3, [pc, #156] ; (80119c4 <tcp_fasttmr+0xbc>)
8011928: 781b ldrb r3, [r3, #0]
801192a: 429a cmp r2, r3
801192c: d03f beq.n 80119ae <tcp_fasttmr+0xa6>
struct tcp_pcb *next;
pcb->last_timer = tcp_timer_ctr;
801192e: 4b25 ldr r3, [pc, #148] ; (80119c4 <tcp_fasttmr+0xbc>)
8011930: 781a ldrb r2, [r3, #0]
8011932: 687b ldr r3, [r7, #4]
8011934: 779a strb r2, [r3, #30]
/* send delayed ACKs */
if (pcb->flags & TF_ACK_DELAY) {
8011936: 687b ldr r3, [r7, #4]
8011938: 8b5b ldrh r3, [r3, #26]
801193a: f003 0301 and.w r3, r3, #1
801193e: 2b00 cmp r3, #0
8011940: d010 beq.n 8011964 <tcp_fasttmr+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
tcp_ack_now(pcb);
8011942: 687b ldr r3, [r7, #4]
8011944: 8b5b ldrh r3, [r3, #26]
8011946: f043 0302 orr.w r3, r3, #2
801194a: b29a uxth r2, r3
801194c: 687b ldr r3, [r7, #4]
801194e: 835a strh r2, [r3, #26]
tcp_output(pcb);
8011950: 6878 ldr r0, [r7, #4]
8011952: f003 fac7 bl 8014ee4 <tcp_output>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8011956: 687b ldr r3, [r7, #4]
8011958: 8b5b ldrh r3, [r3, #26]
801195a: f023 0303 bic.w r3, r3, #3
801195e: b29a uxth r2, r3
8011960: 687b ldr r3, [r7, #4]
8011962: 835a strh r2, [r3, #26]
}
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
8011964: 687b ldr r3, [r7, #4]
8011966: 8b5b ldrh r3, [r3, #26]
8011968: f003 0308 and.w r3, r3, #8
801196c: 2b00 cmp r3, #0
801196e: d009 beq.n 8011984 <tcp_fasttmr+0x7c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011970: 687b ldr r3, [r7, #4]
8011972: 8b5b ldrh r3, [r3, #26]
8011974: f023 0308 bic.w r3, r3, #8
8011978: b29a uxth r2, r3
801197a: 687b ldr r3, [r7, #4]
801197c: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
801197e: 6878 ldr r0, [r7, #4]
8011980: f7ff fa7e bl 8010e80 <tcp_close_shutdown_fin>
}
next = pcb->next;
8011984: 687b ldr r3, [r7, #4]
8011986: 68db ldr r3, [r3, #12]
8011988: 603b str r3, [r7, #0]
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
801198a: 687b ldr r3, [r7, #4]
801198c: 6f9b ldr r3, [r3, #120] ; 0x78
801198e: 2b00 cmp r3, #0
8011990: d00a beq.n 80119a8 <tcp_fasttmr+0xa0>
tcp_active_pcbs_changed = 0;
8011992: 4b0e ldr r3, [pc, #56] ; (80119cc <tcp_fasttmr+0xc4>)
8011994: 2200 movs r2, #0
8011996: 701a strb r2, [r3, #0]
tcp_process_refused_data(pcb);
8011998: 6878 ldr r0, [r7, #4]
801199a: f000 f819 bl 80119d0 <tcp_process_refused_data>
if (tcp_active_pcbs_changed) {
801199e: 4b0b ldr r3, [pc, #44] ; (80119cc <tcp_fasttmr+0xc4>)
80119a0: 781b ldrb r3, [r3, #0]
80119a2: 2b00 cmp r3, #0
80119a4: d000 beq.n 80119a8 <tcp_fasttmr+0xa0>
/* application callback has changed the pcb list: restart the loop */
goto tcp_fasttmr_start;
80119a6: e7b8 b.n 801191a <tcp_fasttmr+0x12>
}
}
pcb = next;
80119a8: 683b ldr r3, [r7, #0]
80119aa: 607b str r3, [r7, #4]
80119ac: e002 b.n 80119b4 <tcp_fasttmr+0xac>
} else {
pcb = pcb->next;
80119ae: 687b ldr r3, [r7, #4]
80119b0: 68db ldr r3, [r3, #12]
80119b2: 607b str r3, [r7, #4]
while (pcb != NULL) {
80119b4: 687b ldr r3, [r7, #4]
80119b6: 2b00 cmp r3, #0
80119b8: d1b3 bne.n 8011922 <tcp_fasttmr+0x1a>
}
}
}
80119ba: bf00 nop
80119bc: 3708 adds r7, #8
80119be: 46bd mov sp, r7
80119c0: bd80 pop {r7, pc}
80119c2: bf00 nop
80119c4: 2000872a .word 0x2000872a
80119c8: 2000f5c0 .word 0x2000f5c0
80119cc: 2000f5bc .word 0x2000f5bc
080119d0 <tcp_process_refused_data>:
}
/** Pass pcb->refused_data to the recv callback */
err_t
tcp_process_refused_data(struct tcp_pcb *pcb)
{
80119d0: b590 push {r4, r7, lr}
80119d2: b085 sub sp, #20
80119d4: af00 add r7, sp, #0
80119d6: 6078 str r0, [r7, #4]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
struct pbuf *rest;
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
80119d8: 687b ldr r3, [r7, #4]
80119da: 2b00 cmp r3, #0
80119dc: d109 bne.n 80119f2 <tcp_process_refused_data+0x22>
80119de: 4b37 ldr r3, [pc, #220] ; (8011abc <tcp_process_refused_data+0xec>)
80119e0: f240 6209 movw r2, #1545 ; 0x609
80119e4: 4936 ldr r1, [pc, #216] ; (8011ac0 <tcp_process_refused_data+0xf0>)
80119e6: 4837 ldr r0, [pc, #220] ; (8011ac4 <tcp_process_refused_data+0xf4>)
80119e8: f009 fb14 bl 801b014 <iprintf>
80119ec: f06f 030f mvn.w r3, #15
80119f0: e060 b.n 8011ab4 <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (pcb->refused_data != NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
{
err_t err;
u8_t refused_flags = pcb->refused_data->flags;
80119f2: 687b ldr r3, [r7, #4]
80119f4: 6f9b ldr r3, [r3, #120] ; 0x78
80119f6: 7b5b ldrb r3, [r3, #13]
80119f8: 73bb strb r3, [r7, #14]
/* set pcb->refused_data to NULL in case the callback frees it and then
closes the pcb */
struct pbuf *refused_data = pcb->refused_data;
80119fa: 687b ldr r3, [r7, #4]
80119fc: 6f9b ldr r3, [r3, #120] ; 0x78
80119fe: 60bb str r3, [r7, #8]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
pbuf_split_64k(refused_data, &rest);
pcb->refused_data = rest;
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = NULL;
8011a00: 687b ldr r3, [r7, #4]
8011a02: 2200 movs r2, #0
8011a04: 679a str r2, [r3, #120] ; 0x78
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
/* Notify again application with data previously received. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
8011a06: 687b ldr r3, [r7, #4]
8011a08: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8011a0c: 2b00 cmp r3, #0
8011a0e: d00b beq.n 8011a28 <tcp_process_refused_data+0x58>
8011a10: 687b ldr r3, [r7, #4]
8011a12: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8011a16: 687b ldr r3, [r7, #4]
8011a18: 6918 ldr r0, [r3, #16]
8011a1a: 2300 movs r3, #0
8011a1c: 68ba ldr r2, [r7, #8]
8011a1e: 6879 ldr r1, [r7, #4]
8011a20: 47a0 blx r4
8011a22: 4603 mov r3, r0
8011a24: 73fb strb r3, [r7, #15]
8011a26: e007 b.n 8011a38 <tcp_process_refused_data+0x68>
8011a28: 2300 movs r3, #0
8011a2a: 68ba ldr r2, [r7, #8]
8011a2c: 6879 ldr r1, [r7, #4]
8011a2e: 2000 movs r0, #0
8011a30: f000 f8a2 bl 8011b78 <tcp_recv_null>
8011a34: 4603 mov r3, r0
8011a36: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8011a38: f997 300f ldrsb.w r3, [r7, #15]
8011a3c: 2b00 cmp r3, #0
8011a3e: d12a bne.n 8011a96 <tcp_process_refused_data+0xc6>
/* did refused_data include a FIN? */
if ((refused_flags & PBUF_FLAG_TCP_FIN)
8011a40: 7bbb ldrb r3, [r7, #14]
8011a42: f003 0320 and.w r3, r3, #32
8011a46: 2b00 cmp r3, #0
8011a48: d033 beq.n 8011ab2 <tcp_process_refused_data+0xe2>
&& (rest == NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
) {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
8011a4a: 687b ldr r3, [r7, #4]
8011a4c: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a4e: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011a52: d005 beq.n 8011a60 <tcp_process_refused_data+0x90>
pcb->rcv_wnd++;
8011a54: 687b ldr r3, [r7, #4]
8011a56: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a58: 3301 adds r3, #1
8011a5a: b29a uxth r2, r3
8011a5c: 687b ldr r3, [r7, #4]
8011a5e: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
8011a60: 687b ldr r3, [r7, #4]
8011a62: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8011a66: 2b00 cmp r3, #0
8011a68: d00b beq.n 8011a82 <tcp_process_refused_data+0xb2>
8011a6a: 687b ldr r3, [r7, #4]
8011a6c: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8011a70: 687b ldr r3, [r7, #4]
8011a72: 6918 ldr r0, [r3, #16]
8011a74: 2300 movs r3, #0
8011a76: 2200 movs r2, #0
8011a78: 6879 ldr r1, [r7, #4]
8011a7a: 47a0 blx r4
8011a7c: 4603 mov r3, r0
8011a7e: 73fb strb r3, [r7, #15]
8011a80: e001 b.n 8011a86 <tcp_process_refused_data+0xb6>
8011a82: 2300 movs r3, #0
8011a84: 73fb strb r3, [r7, #15]
if (err == ERR_ABRT) {
8011a86: f997 300f ldrsb.w r3, [r7, #15]
8011a8a: f113 0f0d cmn.w r3, #13
8011a8e: d110 bne.n 8011ab2 <tcp_process_refused_data+0xe2>
return ERR_ABRT;
8011a90: f06f 030c mvn.w r3, #12
8011a94: e00e b.n 8011ab4 <tcp_process_refused_data+0xe4>
}
}
} else if (err == ERR_ABRT) {
8011a96: f997 300f ldrsb.w r3, [r7, #15]
8011a9a: f113 0f0d cmn.w r3, #13
8011a9e: d102 bne.n 8011aa6 <tcp_process_refused_data+0xd6>
/* if err == ERR_ABRT, 'pcb' is already deallocated */
/* Drop incoming packets because pcb is "full" (only if the incoming
segment contains data). */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
return ERR_ABRT;
8011aa0: f06f 030c mvn.w r3, #12
8011aa4: e006 b.n 8011ab4 <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(refused_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = refused_data;
8011aa6: 687b ldr r3, [r7, #4]
8011aa8: 68ba ldr r2, [r7, #8]
8011aaa: 679a str r2, [r3, #120] ; 0x78
return ERR_INPROGRESS;
8011aac: f06f 0304 mvn.w r3, #4
8011ab0: e000 b.n 8011ab4 <tcp_process_refused_data+0xe4>
}
}
return ERR_OK;
8011ab2: 2300 movs r3, #0
}
8011ab4: 4618 mov r0, r3
8011ab6: 3714 adds r7, #20
8011ab8: 46bd mov sp, r7
8011aba: bd90 pop {r4, r7, pc}
8011abc: 0801cb48 .word 0x0801cb48
8011ac0: 0801d058 .word 0x0801d058
8011ac4: 0801cb8c .word 0x0801cb8c
08011ac8 <tcp_segs_free>:
*
* @param seg tcp_seg list of TCP segments to free
*/
void
tcp_segs_free(struct tcp_seg *seg)
{
8011ac8: b580 push {r7, lr}
8011aca: b084 sub sp, #16
8011acc: af00 add r7, sp, #0
8011ace: 6078 str r0, [r7, #4]
while (seg != NULL) {
8011ad0: e007 b.n 8011ae2 <tcp_segs_free+0x1a>
struct tcp_seg *next = seg->next;
8011ad2: 687b ldr r3, [r7, #4]
8011ad4: 681b ldr r3, [r3, #0]
8011ad6: 60fb str r3, [r7, #12]
tcp_seg_free(seg);
8011ad8: 6878 ldr r0, [r7, #4]
8011ada: f000 f809 bl 8011af0 <tcp_seg_free>
seg = next;
8011ade: 68fb ldr r3, [r7, #12]
8011ae0: 607b str r3, [r7, #4]
while (seg != NULL) {
8011ae2: 687b ldr r3, [r7, #4]
8011ae4: 2b00 cmp r3, #0
8011ae6: d1f4 bne.n 8011ad2 <tcp_segs_free+0xa>
}
}
8011ae8: bf00 nop
8011aea: 3710 adds r7, #16
8011aec: 46bd mov sp, r7
8011aee: bd80 pop {r7, pc}
08011af0 <tcp_seg_free>:
*
* @param seg single tcp_seg to free
*/
void
tcp_seg_free(struct tcp_seg *seg)
{
8011af0: b580 push {r7, lr}
8011af2: b082 sub sp, #8
8011af4: af00 add r7, sp, #0
8011af6: 6078 str r0, [r7, #4]
if (seg != NULL) {
8011af8: 687b ldr r3, [r7, #4]
8011afa: 2b00 cmp r3, #0
8011afc: d00c beq.n 8011b18 <tcp_seg_free+0x28>
if (seg->p != NULL) {
8011afe: 687b ldr r3, [r7, #4]
8011b00: 685b ldr r3, [r3, #4]
8011b02: 2b00 cmp r3, #0
8011b04: d004 beq.n 8011b10 <tcp_seg_free+0x20>
pbuf_free(seg->p);
8011b06: 687b ldr r3, [r7, #4]
8011b08: 685b ldr r3, [r3, #4]
8011b0a: 4618 mov r0, r3
8011b0c: f7fe fd6c bl 80105e8 <pbuf_free>
#if TCP_DEBUG
seg->p = NULL;
#endif /* TCP_DEBUG */
}
memp_free(MEMP_TCP_SEG, seg);
8011b10: 6879 ldr r1, [r7, #4]
8011b12: 2003 movs r0, #3
8011b14: f7fd febc bl 800f890 <memp_free>
}
}
8011b18: bf00 nop
8011b1a: 3708 adds r7, #8
8011b1c: 46bd mov sp, r7
8011b1e: bd80 pop {r7, pc}
08011b20 <tcp_seg_copy>:
* @param seg the old tcp_seg
* @return a copy of seg
*/
struct tcp_seg *
tcp_seg_copy(struct tcp_seg *seg)
{
8011b20: b580 push {r7, lr}
8011b22: b084 sub sp, #16
8011b24: af00 add r7, sp, #0
8011b26: 6078 str r0, [r7, #4]
struct tcp_seg *cseg;
LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
8011b28: 687b ldr r3, [r7, #4]
8011b2a: 2b00 cmp r3, #0
8011b2c: d106 bne.n 8011b3c <tcp_seg_copy+0x1c>
8011b2e: 4b0f ldr r3, [pc, #60] ; (8011b6c <tcp_seg_copy+0x4c>)
8011b30: f240 6282 movw r2, #1666 ; 0x682
8011b34: 490e ldr r1, [pc, #56] ; (8011b70 <tcp_seg_copy+0x50>)
8011b36: 480f ldr r0, [pc, #60] ; (8011b74 <tcp_seg_copy+0x54>)
8011b38: f009 fa6c bl 801b014 <iprintf>
cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
8011b3c: 2003 movs r0, #3
8011b3e: f7fd fe55 bl 800f7ec <memp_malloc>
8011b42: 60f8 str r0, [r7, #12]
if (cseg == NULL) {
8011b44: 68fb ldr r3, [r7, #12]
8011b46: 2b00 cmp r3, #0
8011b48: d101 bne.n 8011b4e <tcp_seg_copy+0x2e>
return NULL;
8011b4a: 2300 movs r3, #0
8011b4c: e00a b.n 8011b64 <tcp_seg_copy+0x44>
}
SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
8011b4e: 2210 movs r2, #16
8011b50: 6879 ldr r1, [r7, #4]
8011b52: 68f8 ldr r0, [r7, #12]
8011b54: f009 fa4b bl 801afee <memcpy>
pbuf_ref(cseg->p);
8011b58: 68fb ldr r3, [r7, #12]
8011b5a: 685b ldr r3, [r3, #4]
8011b5c: 4618 mov r0, r3
8011b5e: f7fe fde9 bl 8010734 <pbuf_ref>
return cseg;
8011b62: 68fb ldr r3, [r7, #12]
}
8011b64: 4618 mov r0, r3
8011b66: 3710 adds r7, #16
8011b68: 46bd mov sp, r7
8011b6a: bd80 pop {r7, pc}
8011b6c: 0801cb48 .word 0x0801cb48
8011b70: 0801d09c .word 0x0801d09c
8011b74: 0801cb8c .word 0x0801cb8c
08011b78 <tcp_recv_null>:
* Default receive callback that is called if the user didn't register
* a recv callback for the pcb.
*/
err_t
tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
{
8011b78: b580 push {r7, lr}
8011b7a: b084 sub sp, #16
8011b7c: af00 add r7, sp, #0
8011b7e: 60f8 str r0, [r7, #12]
8011b80: 60b9 str r1, [r7, #8]
8011b82: 607a str r2, [r7, #4]
8011b84: 70fb strb r3, [r7, #3]
LWIP_UNUSED_ARG(arg);
LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
8011b86: 68bb ldr r3, [r7, #8]
8011b88: 2b00 cmp r3, #0
8011b8a: d109 bne.n 8011ba0 <tcp_recv_null+0x28>
8011b8c: 4b12 ldr r3, [pc, #72] ; (8011bd8 <tcp_recv_null+0x60>)
8011b8e: f44f 62d3 mov.w r2, #1688 ; 0x698
8011b92: 4912 ldr r1, [pc, #72] ; (8011bdc <tcp_recv_null+0x64>)
8011b94: 4812 ldr r0, [pc, #72] ; (8011be0 <tcp_recv_null+0x68>)
8011b96: f009 fa3d bl 801b014 <iprintf>
8011b9a: f06f 030f mvn.w r3, #15
8011b9e: e016 b.n 8011bce <tcp_recv_null+0x56>
if (p != NULL) {
8011ba0: 687b ldr r3, [r7, #4]
8011ba2: 2b00 cmp r3, #0
8011ba4: d009 beq.n 8011bba <tcp_recv_null+0x42>
tcp_recved(pcb, p->tot_len);
8011ba6: 687b ldr r3, [r7, #4]
8011ba8: 891b ldrh r3, [r3, #8]
8011baa: 4619 mov r1, r3
8011bac: 68b8 ldr r0, [r7, #8]
8011bae: f7ff fb1d bl 80111ec <tcp_recved>
pbuf_free(p);
8011bb2: 6878 ldr r0, [r7, #4]
8011bb4: f7fe fd18 bl 80105e8 <pbuf_free>
8011bb8: e008 b.n 8011bcc <tcp_recv_null+0x54>
} else if (err == ERR_OK) {
8011bba: f997 3003 ldrsb.w r3, [r7, #3]
8011bbe: 2b00 cmp r3, #0
8011bc0: d104 bne.n 8011bcc <tcp_recv_null+0x54>
return tcp_close(pcb);
8011bc2: 68b8 ldr r0, [r7, #8]
8011bc4: f7ff f9c2 bl 8010f4c <tcp_close>
8011bc8: 4603 mov r3, r0
8011bca: e000 b.n 8011bce <tcp_recv_null+0x56>
}
return ERR_OK;
8011bcc: 2300 movs r3, #0
}
8011bce: 4618 mov r0, r3
8011bd0: 3710 adds r7, #16
8011bd2: 46bd mov sp, r7
8011bd4: bd80 pop {r7, pc}
8011bd6: bf00 nop
8011bd8: 0801cb48 .word 0x0801cb48
8011bdc: 0801d0b8 .word 0x0801d0b8
8011be0: 0801cb8c .word 0x0801cb8c
08011be4 <tcp_kill_prio>:
*
* @param prio minimum priority
*/
static void
tcp_kill_prio(u8_t prio)
{
8011be4: b580 push {r7, lr}
8011be6: b086 sub sp, #24
8011be8: af00 add r7, sp, #0
8011bea: 4603 mov r3, r0
8011bec: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
u8_t mprio;
mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
8011bee: f997 3007 ldrsb.w r3, [r7, #7]
8011bf2: 2b00 cmp r3, #0
8011bf4: db01 blt.n 8011bfa <tcp_kill_prio+0x16>
8011bf6: 79fb ldrb r3, [r7, #7]
8011bf8: e000 b.n 8011bfc <tcp_kill_prio+0x18>
8011bfa: 237f movs r3, #127 ; 0x7f
8011bfc: 72fb strb r3, [r7, #11]
/* We want to kill connections with a lower prio, so bail out if
* supplied prio is 0 - there can never be a lower prio
*/
if (mprio == 0) {
8011bfe: 7afb ldrb r3, [r7, #11]
8011c00: 2b00 cmp r3, #0
8011c02: d034 beq.n 8011c6e <tcp_kill_prio+0x8a>
/* We only want kill connections with a lower prio, so decrement prio by one
* and start searching for oldest connection with same or lower priority than mprio.
* We want to find the connections with the lowest possible prio, and among
* these the one with the longest inactivity time.
*/
mprio--;
8011c04: 7afb ldrb r3, [r7, #11]
8011c06: 3b01 subs r3, #1
8011c08: 72fb strb r3, [r7, #11]
inactivity = 0;
8011c0a: 2300 movs r3, #0
8011c0c: 60fb str r3, [r7, #12]
inactive = NULL;
8011c0e: 2300 movs r3, #0
8011c10: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c12: 4b19 ldr r3, [pc, #100] ; (8011c78 <tcp_kill_prio+0x94>)
8011c14: 681b ldr r3, [r3, #0]
8011c16: 617b str r3, [r7, #20]
8011c18: e01f b.n 8011c5a <tcp_kill_prio+0x76>
/* lower prio is always a kill candidate */
if ((pcb->prio < mprio) ||
8011c1a: 697b ldr r3, [r7, #20]
8011c1c: 7d5b ldrb r3, [r3, #21]
8011c1e: 7afa ldrb r2, [r7, #11]
8011c20: 429a cmp r2, r3
8011c22: d80c bhi.n 8011c3e <tcp_kill_prio+0x5a>
/* longer inactivity is also a kill candidate */
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c24: 697b ldr r3, [r7, #20]
8011c26: 7d5b ldrb r3, [r3, #21]
if ((pcb->prio < mprio) ||
8011c28: 7afa ldrb r2, [r7, #11]
8011c2a: 429a cmp r2, r3
8011c2c: d112 bne.n 8011c54 <tcp_kill_prio+0x70>
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c2e: 4b13 ldr r3, [pc, #76] ; (8011c7c <tcp_kill_prio+0x98>)
8011c30: 681a ldr r2, [r3, #0]
8011c32: 697b ldr r3, [r7, #20]
8011c34: 6a1b ldr r3, [r3, #32]
8011c36: 1ad3 subs r3, r2, r3
8011c38: 68fa ldr r2, [r7, #12]
8011c3a: 429a cmp r2, r3
8011c3c: d80a bhi.n 8011c54 <tcp_kill_prio+0x70>
inactivity = tcp_ticks - pcb->tmr;
8011c3e: 4b0f ldr r3, [pc, #60] ; (8011c7c <tcp_kill_prio+0x98>)
8011c40: 681a ldr r2, [r3, #0]
8011c42: 697b ldr r3, [r7, #20]
8011c44: 6a1b ldr r3, [r3, #32]
8011c46: 1ad3 subs r3, r2, r3
8011c48: 60fb str r3, [r7, #12]
inactive = pcb;
8011c4a: 697b ldr r3, [r7, #20]
8011c4c: 613b str r3, [r7, #16]
mprio = pcb->prio;
8011c4e: 697b ldr r3, [r7, #20]
8011c50: 7d5b ldrb r3, [r3, #21]
8011c52: 72fb strb r3, [r7, #11]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c54: 697b ldr r3, [r7, #20]
8011c56: 68db ldr r3, [r3, #12]
8011c58: 617b str r3, [r7, #20]
8011c5a: 697b ldr r3, [r7, #20]
8011c5c: 2b00 cmp r3, #0
8011c5e: d1dc bne.n 8011c1a <tcp_kill_prio+0x36>
}
}
if (inactive != NULL) {
8011c60: 693b ldr r3, [r7, #16]
8011c62: 2b00 cmp r3, #0
8011c64: d004 beq.n 8011c70 <tcp_kill_prio+0x8c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011c66: 6938 ldr r0, [r7, #16]
8011c68: f7ff fa5a bl 8011120 <tcp_abort>
8011c6c: e000 b.n 8011c70 <tcp_kill_prio+0x8c>
return;
8011c6e: bf00 nop
}
}
8011c70: 3718 adds r7, #24
8011c72: 46bd mov sp, r7
8011c74: bd80 pop {r7, pc}
8011c76: bf00 nop
8011c78: 2000f5c0 .word 0x2000f5c0
8011c7c: 2000f5c4 .word 0x2000f5c4
08011c80 <tcp_kill_state>:
* Kills the oldest connection that is in specific state.
* Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
*/
static void
tcp_kill_state(enum tcp_state state)
{
8011c80: b580 push {r7, lr}
8011c82: b086 sub sp, #24
8011c84: af00 add r7, sp, #0
8011c86: 4603 mov r3, r0
8011c88: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
8011c8a: 79fb ldrb r3, [r7, #7]
8011c8c: 2b08 cmp r3, #8
8011c8e: d009 beq.n 8011ca4 <tcp_kill_state+0x24>
8011c90: 79fb ldrb r3, [r7, #7]
8011c92: 2b09 cmp r3, #9
8011c94: d006 beq.n 8011ca4 <tcp_kill_state+0x24>
8011c96: 4b1a ldr r3, [pc, #104] ; (8011d00 <tcp_kill_state+0x80>)
8011c98: f240 62dd movw r2, #1757 ; 0x6dd
8011c9c: 4919 ldr r1, [pc, #100] ; (8011d04 <tcp_kill_state+0x84>)
8011c9e: 481a ldr r0, [pc, #104] ; (8011d08 <tcp_kill_state+0x88>)
8011ca0: f009 f9b8 bl 801b014 <iprintf>
inactivity = 0;
8011ca4: 2300 movs r3, #0
8011ca6: 60fb str r3, [r7, #12]
inactive = NULL;
8011ca8: 2300 movs r3, #0
8011caa: 613b str r3, [r7, #16]
/* Go through the list of active pcbs and get the oldest pcb that is in state
CLOSING/LAST_ACK. */
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011cac: 4b17 ldr r3, [pc, #92] ; (8011d0c <tcp_kill_state+0x8c>)
8011cae: 681b ldr r3, [r3, #0]
8011cb0: 617b str r3, [r7, #20]
8011cb2: e017 b.n 8011ce4 <tcp_kill_state+0x64>
if (pcb->state == state) {
8011cb4: 697b ldr r3, [r7, #20]
8011cb6: 7d1b ldrb r3, [r3, #20]
8011cb8: 79fa ldrb r2, [r7, #7]
8011cba: 429a cmp r2, r3
8011cbc: d10f bne.n 8011cde <tcp_kill_state+0x5e>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011cbe: 4b14 ldr r3, [pc, #80] ; (8011d10 <tcp_kill_state+0x90>)
8011cc0: 681a ldr r2, [r3, #0]
8011cc2: 697b ldr r3, [r7, #20]
8011cc4: 6a1b ldr r3, [r3, #32]
8011cc6: 1ad3 subs r3, r2, r3
8011cc8: 68fa ldr r2, [r7, #12]
8011cca: 429a cmp r2, r3
8011ccc: d807 bhi.n 8011cde <tcp_kill_state+0x5e>
inactivity = tcp_ticks - pcb->tmr;
8011cce: 4b10 ldr r3, [pc, #64] ; (8011d10 <tcp_kill_state+0x90>)
8011cd0: 681a ldr r2, [r3, #0]
8011cd2: 697b ldr r3, [r7, #20]
8011cd4: 6a1b ldr r3, [r3, #32]
8011cd6: 1ad3 subs r3, r2, r3
8011cd8: 60fb str r3, [r7, #12]
inactive = pcb;
8011cda: 697b ldr r3, [r7, #20]
8011cdc: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011cde: 697b ldr r3, [r7, #20]
8011ce0: 68db ldr r3, [r3, #12]
8011ce2: 617b str r3, [r7, #20]
8011ce4: 697b ldr r3, [r7, #20]
8011ce6: 2b00 cmp r3, #0
8011ce8: d1e4 bne.n 8011cb4 <tcp_kill_state+0x34>
}
}
}
if (inactive != NULL) {
8011cea: 693b ldr r3, [r7, #16]
8011cec: 2b00 cmp r3, #0
8011cee: d003 beq.n 8011cf8 <tcp_kill_state+0x78>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
tcp_state_str[state], (void *)inactive, inactivity));
/* Don't send a RST, since no data is lost. */
tcp_abandon(inactive, 0);
8011cf0: 2100 movs r1, #0
8011cf2: 6938 ldr r0, [r7, #16]
8011cf4: f7ff f956 bl 8010fa4 <tcp_abandon>
}
}
8011cf8: bf00 nop
8011cfa: 3718 adds r7, #24
8011cfc: 46bd mov sp, r7
8011cfe: bd80 pop {r7, pc}
8011d00: 0801cb48 .word 0x0801cb48
8011d04: 0801d0d4 .word 0x0801d0d4
8011d08: 0801cb8c .word 0x0801cb8c
8011d0c: 2000f5c0 .word 0x2000f5c0
8011d10: 2000f5c4 .word 0x2000f5c4
08011d14 <tcp_kill_timewait>:
* Kills the oldest connection that is in TIME_WAIT state.
* Called from tcp_alloc() if no more connections are available.
*/
static void
tcp_kill_timewait(void)
{
8011d14: b580 push {r7, lr}
8011d16: b084 sub sp, #16
8011d18: af00 add r7, sp, #0
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
inactivity = 0;
8011d1a: 2300 movs r3, #0
8011d1c: 607b str r3, [r7, #4]
inactive = NULL;
8011d1e: 2300 movs r3, #0
8011d20: 60bb str r3, [r7, #8]
/* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011d22: 4b12 ldr r3, [pc, #72] ; (8011d6c <tcp_kill_timewait+0x58>)
8011d24: 681b ldr r3, [r3, #0]
8011d26: 60fb str r3, [r7, #12]
8011d28: e012 b.n 8011d50 <tcp_kill_timewait+0x3c>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011d2a: 4b11 ldr r3, [pc, #68] ; (8011d70 <tcp_kill_timewait+0x5c>)
8011d2c: 681a ldr r2, [r3, #0]
8011d2e: 68fb ldr r3, [r7, #12]
8011d30: 6a1b ldr r3, [r3, #32]
8011d32: 1ad3 subs r3, r2, r3
8011d34: 687a ldr r2, [r7, #4]
8011d36: 429a cmp r2, r3
8011d38: d807 bhi.n 8011d4a <tcp_kill_timewait+0x36>
inactivity = tcp_ticks - pcb->tmr;
8011d3a: 4b0d ldr r3, [pc, #52] ; (8011d70 <tcp_kill_timewait+0x5c>)
8011d3c: 681a ldr r2, [r3, #0]
8011d3e: 68fb ldr r3, [r7, #12]
8011d40: 6a1b ldr r3, [r3, #32]
8011d42: 1ad3 subs r3, r2, r3
8011d44: 607b str r3, [r7, #4]
inactive = pcb;
8011d46: 68fb ldr r3, [r7, #12]
8011d48: 60bb str r3, [r7, #8]
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011d4a: 68fb ldr r3, [r7, #12]
8011d4c: 68db ldr r3, [r3, #12]
8011d4e: 60fb str r3, [r7, #12]
8011d50: 68fb ldr r3, [r7, #12]
8011d52: 2b00 cmp r3, #0
8011d54: d1e9 bne.n 8011d2a <tcp_kill_timewait+0x16>
}
}
if (inactive != NULL) {
8011d56: 68bb ldr r3, [r7, #8]
8011d58: 2b00 cmp r3, #0
8011d5a: d002 beq.n 8011d62 <tcp_kill_timewait+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011d5c: 68b8 ldr r0, [r7, #8]
8011d5e: f7ff f9df bl 8011120 <tcp_abort>
}
}
8011d62: bf00 nop
8011d64: 3710 adds r7, #16
8011d66: 46bd mov sp, r7
8011d68: bd80 pop {r7, pc}
8011d6a: bf00 nop
8011d6c: 2000f5d0 .word 0x2000f5d0
8011d70: 2000f5c4 .word 0x2000f5c4
08011d74 <tcp_handle_closepend>:
* now send the FIN (which failed before), the pcb might be in a state that is
* OK for us to now free it.
*/
static void
tcp_handle_closepend(void)
{
8011d74: b580 push {r7, lr}
8011d76: b082 sub sp, #8
8011d78: af00 add r7, sp, #0
struct tcp_pcb *pcb = tcp_active_pcbs;
8011d7a: 4b10 ldr r3, [pc, #64] ; (8011dbc <tcp_handle_closepend+0x48>)
8011d7c: 681b ldr r3, [r3, #0]
8011d7e: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011d80: e014 b.n 8011dac <tcp_handle_closepend+0x38>
struct tcp_pcb *next = pcb->next;
8011d82: 687b ldr r3, [r7, #4]
8011d84: 68db ldr r3, [r3, #12]
8011d86: 603b str r3, [r7, #0]
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
8011d88: 687b ldr r3, [r7, #4]
8011d8a: 8b5b ldrh r3, [r3, #26]
8011d8c: f003 0308 and.w r3, r3, #8
8011d90: 2b00 cmp r3, #0
8011d92: d009 beq.n 8011da8 <tcp_handle_closepend+0x34>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011d94: 687b ldr r3, [r7, #4]
8011d96: 8b5b ldrh r3, [r3, #26]
8011d98: f023 0308 bic.w r3, r3, #8
8011d9c: b29a uxth r2, r3
8011d9e: 687b ldr r3, [r7, #4]
8011da0: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
8011da2: 6878 ldr r0, [r7, #4]
8011da4: f7ff f86c bl 8010e80 <tcp_close_shutdown_fin>
}
pcb = next;
8011da8: 683b ldr r3, [r7, #0]
8011daa: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011dac: 687b ldr r3, [r7, #4]
8011dae: 2b00 cmp r3, #0
8011db0: d1e7 bne.n 8011d82 <tcp_handle_closepend+0xe>
}
}
8011db2: bf00 nop
8011db4: 3708 adds r7, #8
8011db6: 46bd mov sp, r7
8011db8: bd80 pop {r7, pc}
8011dba: bf00 nop
8011dbc: 2000f5c0 .word 0x2000f5c0
08011dc0 <tcp_alloc>:
* @param prio priority for the new pcb
* @return a new tcp_pcb that initially is in state CLOSED
*/
struct tcp_pcb *
tcp_alloc(u8_t prio)
{
8011dc0: b580 push {r7, lr}
8011dc2: b084 sub sp, #16
8011dc4: af00 add r7, sp, #0
8011dc6: 4603 mov r3, r0
8011dc8: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011dca: 2001 movs r0, #1
8011dcc: f7fd fd0e bl 800f7ec <memp_malloc>
8011dd0: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dd2: 68fb ldr r3, [r7, #12]
8011dd4: 2b00 cmp r3, #0
8011dd6: d126 bne.n 8011e26 <tcp_alloc+0x66>
/* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
tcp_handle_closepend();
8011dd8: f7ff ffcc bl 8011d74 <tcp_handle_closepend>
/* Try killing oldest connection in TIME-WAIT. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
tcp_kill_timewait();
8011ddc: f7ff ff9a bl 8011d14 <tcp_kill_timewait>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011de0: 2001 movs r0, #1
8011de2: f7fd fd03 bl 800f7ec <memp_malloc>
8011de6: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011de8: 68fb ldr r3, [r7, #12]
8011dea: 2b00 cmp r3, #0
8011dec: d11b bne.n 8011e26 <tcp_alloc+0x66>
/* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
tcp_kill_state(LAST_ACK);
8011dee: 2009 movs r0, #9
8011df0: f7ff ff46 bl 8011c80 <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011df4: 2001 movs r0, #1
8011df6: f7fd fcf9 bl 800f7ec <memp_malloc>
8011dfa: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011dfc: 68fb ldr r3, [r7, #12]
8011dfe: 2b00 cmp r3, #0
8011e00: d111 bne.n 8011e26 <tcp_alloc+0x66>
/* Try killing oldest connection in CLOSING. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
tcp_kill_state(CLOSING);
8011e02: 2008 movs r0, #8
8011e04: f7ff ff3c bl 8011c80 <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011e08: 2001 movs r0, #1
8011e0a: f7fd fcef bl 800f7ec <memp_malloc>
8011e0e: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011e10: 68fb ldr r3, [r7, #12]
8011e12: 2b00 cmp r3, #0
8011e14: d107 bne.n 8011e26 <tcp_alloc+0x66>
/* Try killing oldest active connection with lower priority than the new one. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
tcp_kill_prio(prio);
8011e16: 79fb ldrb r3, [r7, #7]
8011e18: 4618 mov r0, r3
8011e1a: f7ff fee3 bl 8011be4 <tcp_kill_prio>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011e1e: 2001 movs r0, #1
8011e20: f7fd fce4 bl 800f7ec <memp_malloc>
8011e24: 60f8 str r0, [r7, #12]
if (pcb != NULL) {
/* adjust err stats: memp_malloc failed above */
MEMP_STATS_DEC(err, MEMP_TCP_PCB);
}
}
if (pcb != NULL) {
8011e26: 68fb ldr r3, [r7, #12]
8011e28: 2b00 cmp r3, #0
8011e2a: d03f beq.n 8011eac <tcp_alloc+0xec>
/* zero out the whole pcb, so there is no need to initialize members to zero */
memset(pcb, 0, sizeof(struct tcp_pcb));
8011e2c: 229c movs r2, #156 ; 0x9c
8011e2e: 2100 movs r1, #0
8011e30: 68f8 ldr r0, [r7, #12]
8011e32: f009 f8e7 bl 801b004 <memset>
pcb->prio = prio;
8011e36: 68fb ldr r3, [r7, #12]
8011e38: 79fa ldrb r2, [r7, #7]
8011e3a: 755a strb r2, [r3, #21]
pcb->snd_buf = TCP_SND_BUF;
8011e3c: 68fb ldr r3, [r7, #12]
8011e3e: f44f 6286 mov.w r2, #1072 ; 0x430
8011e42: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* Start with a window that does not need scaling. When window scaling is
enabled and used, the window is enlarged when both sides agree on scaling. */
pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
8011e46: 68fb ldr r3, [r7, #12]
8011e48: f44f 6206 mov.w r2, #2144 ; 0x860
8011e4c: 855a strh r2, [r3, #42] ; 0x2a
8011e4e: 68fb ldr r3, [r7, #12]
8011e50: 8d5a ldrh r2, [r3, #42] ; 0x2a
8011e52: 68fb ldr r3, [r7, #12]
8011e54: 851a strh r2, [r3, #40] ; 0x28
pcb->ttl = TCP_TTL;
8011e56: 68fb ldr r3, [r7, #12]
8011e58: 22ff movs r2, #255 ; 0xff
8011e5a: 72da strb r2, [r3, #11]
/* As initial send MSS, we use TCP_MSS but limit it to 536.
The send MSS is updated when an MSS option is received. */
pcb->mss = INITIAL_MSS;
8011e5c: 68fb ldr r3, [r7, #12]
8011e5e: f44f 7206 mov.w r2, #536 ; 0x218
8011e62: 865a strh r2, [r3, #50] ; 0x32
pcb->rto = 3000 / TCP_SLOW_INTERVAL;
8011e64: 68fb ldr r3, [r7, #12]
8011e66: 2206 movs r2, #6
8011e68: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
pcb->sv = 3000 / TCP_SLOW_INTERVAL;
8011e6c: 68fb ldr r3, [r7, #12]
8011e6e: 2206 movs r2, #6
8011e70: 87da strh r2, [r3, #62] ; 0x3e
pcb->rtime = -1;
8011e72: 68fb ldr r3, [r7, #12]
8011e74: f64f 72ff movw r2, #65535 ; 0xffff
8011e78: 861a strh r2, [r3, #48] ; 0x30
pcb->cwnd = 1;
8011e7a: 68fb ldr r3, [r7, #12]
8011e7c: 2201 movs r2, #1
8011e7e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->tmr = tcp_ticks;
8011e82: 4b0d ldr r3, [pc, #52] ; (8011eb8 <tcp_alloc+0xf8>)
8011e84: 681a ldr r2, [r3, #0]
8011e86: 68fb ldr r3, [r7, #12]
8011e88: 621a str r2, [r3, #32]
pcb->last_timer = tcp_timer_ctr;
8011e8a: 4b0c ldr r3, [pc, #48] ; (8011ebc <tcp_alloc+0xfc>)
8011e8c: 781a ldrb r2, [r3, #0]
8011e8e: 68fb ldr r3, [r7, #12]
8011e90: 779a strb r2, [r3, #30]
of using the largest advertised receive window. We've seen complications with
receiving TCPs that use window scaling and/or window auto-tuning where the
initial advertised window is very small and then grows rapidly once the
connection is established. To avoid these complications, we set ssthresh to the
largest effective cwnd (amount of in-flight data) that the sender can have. */
pcb->ssthresh = TCP_SND_BUF;
8011e92: 68fb ldr r3, [r7, #12]
8011e94: f44f 6286 mov.w r2, #1072 ; 0x430
8011e98: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
#if LWIP_CALLBACK_API
pcb->recv = tcp_recv_null;
8011e9c: 68fb ldr r3, [r7, #12]
8011e9e: 4a08 ldr r2, [pc, #32] ; (8011ec0 <tcp_alloc+0x100>)
8011ea0: f8c3 2084 str.w r2, [r3, #132] ; 0x84
#endif /* LWIP_CALLBACK_API */
/* Init KEEPALIVE timer */
pcb->keep_idle = TCP_KEEPIDLE_DEFAULT;
8011ea4: 68fb ldr r3, [r7, #12]
8011ea6: 4a07 ldr r2, [pc, #28] ; (8011ec4 <tcp_alloc+0x104>)
8011ea8: f8c3 2094 str.w r2, [r3, #148] ; 0x94
#if LWIP_TCP_KEEPALIVE
pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
pcb->keep_cnt = TCP_KEEPCNT_DEFAULT;
#endif /* LWIP_TCP_KEEPALIVE */
}
return pcb;
8011eac: 68fb ldr r3, [r7, #12]
}
8011eae: 4618 mov r0, r3
8011eb0: 3710 adds r7, #16
8011eb2: 46bd mov sp, r7
8011eb4: bd80 pop {r7, pc}
8011eb6: bf00 nop
8011eb8: 2000f5c4 .word 0x2000f5c4
8011ebc: 2000872a .word 0x2000872a
8011ec0: 08011b79 .word 0x08011b79
8011ec4: 006ddd00 .word 0x006ddd00
08011ec8 <tcp_pcb_purge>:
*
* @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
*/
void
tcp_pcb_purge(struct tcp_pcb *pcb)
{
8011ec8: b580 push {r7, lr}
8011eca: b082 sub sp, #8
8011ecc: af00 add r7, sp, #0
8011ece: 6078 str r0, [r7, #4]
LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
8011ed0: 687b ldr r3, [r7, #4]
8011ed2: 2b00 cmp r3, #0
8011ed4: d107 bne.n 8011ee6 <tcp_pcb_purge+0x1e>
8011ed6: 4b21 ldr r3, [pc, #132] ; (8011f5c <tcp_pcb_purge+0x94>)
8011ed8: f640 0251 movw r2, #2129 ; 0x851
8011edc: 4920 ldr r1, [pc, #128] ; (8011f60 <tcp_pcb_purge+0x98>)
8011ede: 4821 ldr r0, [pc, #132] ; (8011f64 <tcp_pcb_purge+0x9c>)
8011ee0: f009 f898 bl 801b014 <iprintf>
8011ee4: e037 b.n 8011f56 <tcp_pcb_purge+0x8e>
if (pcb->state != CLOSED &&
8011ee6: 687b ldr r3, [r7, #4]
8011ee8: 7d1b ldrb r3, [r3, #20]
8011eea: 2b00 cmp r3, #0
8011eec: d033 beq.n 8011f56 <tcp_pcb_purge+0x8e>
pcb->state != TIME_WAIT &&
8011eee: 687b ldr r3, [r7, #4]
8011ef0: 7d1b ldrb r3, [r3, #20]
if (pcb->state != CLOSED &&
8011ef2: 2b0a cmp r3, #10
8011ef4: d02f beq.n 8011f56 <tcp_pcb_purge+0x8e>
pcb->state != LISTEN) {
8011ef6: 687b ldr r3, [r7, #4]
8011ef8: 7d1b ldrb r3, [r3, #20]
pcb->state != TIME_WAIT &&
8011efa: 2b01 cmp r3, #1
8011efc: d02b beq.n 8011f56 <tcp_pcb_purge+0x8e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
tcp_backlog_accepted(pcb);
if (pcb->refused_data != NULL) {
8011efe: 687b ldr r3, [r7, #4]
8011f00: 6f9b ldr r3, [r3, #120] ; 0x78
8011f02: 2b00 cmp r3, #0
8011f04: d007 beq.n 8011f16 <tcp_pcb_purge+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
pbuf_free(pcb->refused_data);
8011f06: 687b ldr r3, [r7, #4]
8011f08: 6f9b ldr r3, [r3, #120] ; 0x78
8011f0a: 4618 mov r0, r3
8011f0c: f7fe fb6c bl 80105e8 <pbuf_free>
pcb->refused_data = NULL;
8011f10: 687b ldr r3, [r7, #4]
8011f12: 2200 movs r2, #0
8011f14: 679a str r2, [r3, #120] ; 0x78
}
if (pcb->unacked != NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
8011f16: 687b ldr r3, [r7, #4]
8011f18: 6f5b ldr r3, [r3, #116] ; 0x74
8011f1a: 2b00 cmp r3, #0
8011f1c: d002 beq.n 8011f24 <tcp_pcb_purge+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
tcp_free_ooseq(pcb);
8011f1e: 6878 ldr r0, [r7, #4]
8011f20: f000 f986 bl 8012230 <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Stop the retransmission timer as it will expect data on unacked
queue if it fires */
pcb->rtime = -1;
8011f24: 687b ldr r3, [r7, #4]
8011f26: f64f 72ff movw r2, #65535 ; 0xffff
8011f2a: 861a strh r2, [r3, #48] ; 0x30
tcp_segs_free(pcb->unsent);
8011f2c: 687b ldr r3, [r7, #4]
8011f2e: 6edb ldr r3, [r3, #108] ; 0x6c
8011f30: 4618 mov r0, r3
8011f32: f7ff fdc9 bl 8011ac8 <tcp_segs_free>
tcp_segs_free(pcb->unacked);
8011f36: 687b ldr r3, [r7, #4]
8011f38: 6f1b ldr r3, [r3, #112] ; 0x70
8011f3a: 4618 mov r0, r3
8011f3c: f7ff fdc4 bl 8011ac8 <tcp_segs_free>
pcb->unacked = pcb->unsent = NULL;
8011f40: 687b ldr r3, [r7, #4]
8011f42: 2200 movs r2, #0
8011f44: 66da str r2, [r3, #108] ; 0x6c
8011f46: 687b ldr r3, [r7, #4]
8011f48: 6eda ldr r2, [r3, #108] ; 0x6c
8011f4a: 687b ldr r3, [r7, #4]
8011f4c: 671a str r2, [r3, #112] ; 0x70
#if TCP_OVERSIZE
pcb->unsent_oversize = 0;
8011f4e: 687b ldr r3, [r7, #4]
8011f50: 2200 movs r2, #0
8011f52: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
}
}
8011f56: 3708 adds r7, #8
8011f58: 46bd mov sp, r7
8011f5a: bd80 pop {r7, pc}
8011f5c: 0801cb48 .word 0x0801cb48
8011f60: 0801d194 .word 0x0801d194
8011f64: 0801cb8c .word 0x0801cb8c
08011f68 <tcp_pcb_remove>:
* @param pcblist PCB list to purge.
* @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
*/
void
tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
{
8011f68: b580 push {r7, lr}
8011f6a: b084 sub sp, #16
8011f6c: af00 add r7, sp, #0
8011f6e: 6078 str r0, [r7, #4]
8011f70: 6039 str r1, [r7, #0]
LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
8011f72: 683b ldr r3, [r7, #0]
8011f74: 2b00 cmp r3, #0
8011f76: d106 bne.n 8011f86 <tcp_pcb_remove+0x1e>
8011f78: 4b3e ldr r3, [pc, #248] ; (8012074 <tcp_pcb_remove+0x10c>)
8011f7a: f640 0283 movw r2, #2179 ; 0x883
8011f7e: 493e ldr r1, [pc, #248] ; (8012078 <tcp_pcb_remove+0x110>)
8011f80: 483e ldr r0, [pc, #248] ; (801207c <tcp_pcb_remove+0x114>)
8011f82: f009 f847 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
8011f86: 687b ldr r3, [r7, #4]
8011f88: 2b00 cmp r3, #0
8011f8a: d106 bne.n 8011f9a <tcp_pcb_remove+0x32>
8011f8c: 4b39 ldr r3, [pc, #228] ; (8012074 <tcp_pcb_remove+0x10c>)
8011f8e: f640 0284 movw r2, #2180 ; 0x884
8011f92: 493b ldr r1, [pc, #236] ; (8012080 <tcp_pcb_remove+0x118>)
8011f94: 4839 ldr r0, [pc, #228] ; (801207c <tcp_pcb_remove+0x114>)
8011f96: f009 f83d bl 801b014 <iprintf>
TCP_RMV(pcblist, pcb);
8011f9a: 687b ldr r3, [r7, #4]
8011f9c: 681b ldr r3, [r3, #0]
8011f9e: 683a ldr r2, [r7, #0]
8011fa0: 429a cmp r2, r3
8011fa2: d105 bne.n 8011fb0 <tcp_pcb_remove+0x48>
8011fa4: 687b ldr r3, [r7, #4]
8011fa6: 681b ldr r3, [r3, #0]
8011fa8: 68da ldr r2, [r3, #12]
8011faa: 687b ldr r3, [r7, #4]
8011fac: 601a str r2, [r3, #0]
8011fae: e013 b.n 8011fd8 <tcp_pcb_remove+0x70>
8011fb0: 687b ldr r3, [r7, #4]
8011fb2: 681b ldr r3, [r3, #0]
8011fb4: 60fb str r3, [r7, #12]
8011fb6: e00c b.n 8011fd2 <tcp_pcb_remove+0x6a>
8011fb8: 68fb ldr r3, [r7, #12]
8011fba: 68db ldr r3, [r3, #12]
8011fbc: 683a ldr r2, [r7, #0]
8011fbe: 429a cmp r2, r3
8011fc0: d104 bne.n 8011fcc <tcp_pcb_remove+0x64>
8011fc2: 683b ldr r3, [r7, #0]
8011fc4: 68da ldr r2, [r3, #12]
8011fc6: 68fb ldr r3, [r7, #12]
8011fc8: 60da str r2, [r3, #12]
8011fca: e005 b.n 8011fd8 <tcp_pcb_remove+0x70>
8011fcc: 68fb ldr r3, [r7, #12]
8011fce: 68db ldr r3, [r3, #12]
8011fd0: 60fb str r3, [r7, #12]
8011fd2: 68fb ldr r3, [r7, #12]
8011fd4: 2b00 cmp r3, #0
8011fd6: d1ef bne.n 8011fb8 <tcp_pcb_remove+0x50>
8011fd8: 683b ldr r3, [r7, #0]
8011fda: 2200 movs r2, #0
8011fdc: 60da str r2, [r3, #12]
tcp_pcb_purge(pcb);
8011fde: 6838 ldr r0, [r7, #0]
8011fe0: f7ff ff72 bl 8011ec8 <tcp_pcb_purge>
/* if there is an outstanding delayed ACKs, send it */
if ((pcb->state != TIME_WAIT) &&
8011fe4: 683b ldr r3, [r7, #0]
8011fe6: 7d1b ldrb r3, [r3, #20]
8011fe8: 2b0a cmp r3, #10
8011fea: d013 beq.n 8012014 <tcp_pcb_remove+0xac>
(pcb->state != LISTEN) &&
8011fec: 683b ldr r3, [r7, #0]
8011fee: 7d1b ldrb r3, [r3, #20]
if ((pcb->state != TIME_WAIT) &&
8011ff0: 2b01 cmp r3, #1
8011ff2: d00f beq.n 8012014 <tcp_pcb_remove+0xac>
(pcb->flags & TF_ACK_DELAY)) {
8011ff4: 683b ldr r3, [r7, #0]
8011ff6: 8b5b ldrh r3, [r3, #26]
8011ff8: f003 0301 and.w r3, r3, #1
(pcb->state != LISTEN) &&
8011ffc: 2b00 cmp r3, #0
8011ffe: d009 beq.n 8012014 <tcp_pcb_remove+0xac>
tcp_ack_now(pcb);
8012000: 683b ldr r3, [r7, #0]
8012002: 8b5b ldrh r3, [r3, #26]
8012004: f043 0302 orr.w r3, r3, #2
8012008: b29a uxth r2, r3
801200a: 683b ldr r3, [r7, #0]
801200c: 835a strh r2, [r3, #26]
tcp_output(pcb);
801200e: 6838 ldr r0, [r7, #0]
8012010: f002 ff68 bl 8014ee4 <tcp_output>
}
if (pcb->state != LISTEN) {
8012014: 683b ldr r3, [r7, #0]
8012016: 7d1b ldrb r3, [r3, #20]
8012018: 2b01 cmp r3, #1
801201a: d020 beq.n 801205e <tcp_pcb_remove+0xf6>
LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
801201c: 683b ldr r3, [r7, #0]
801201e: 6edb ldr r3, [r3, #108] ; 0x6c
8012020: 2b00 cmp r3, #0
8012022: d006 beq.n 8012032 <tcp_pcb_remove+0xca>
8012024: 4b13 ldr r3, [pc, #76] ; (8012074 <tcp_pcb_remove+0x10c>)
8012026: f640 0293 movw r2, #2195 ; 0x893
801202a: 4916 ldr r1, [pc, #88] ; (8012084 <tcp_pcb_remove+0x11c>)
801202c: 4813 ldr r0, [pc, #76] ; (801207c <tcp_pcb_remove+0x114>)
801202e: f008 fff1 bl 801b014 <iprintf>
LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
8012032: 683b ldr r3, [r7, #0]
8012034: 6f1b ldr r3, [r3, #112] ; 0x70
8012036: 2b00 cmp r3, #0
8012038: d006 beq.n 8012048 <tcp_pcb_remove+0xe0>
801203a: 4b0e ldr r3, [pc, #56] ; (8012074 <tcp_pcb_remove+0x10c>)
801203c: f640 0294 movw r2, #2196 ; 0x894
8012040: 4911 ldr r1, [pc, #68] ; (8012088 <tcp_pcb_remove+0x120>)
8012042: 480e ldr r0, [pc, #56] ; (801207c <tcp_pcb_remove+0x114>)
8012044: f008 ffe6 bl 801b014 <iprintf>
#if TCP_QUEUE_OOSEQ
LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
8012048: 683b ldr r3, [r7, #0]
801204a: 6f5b ldr r3, [r3, #116] ; 0x74
801204c: 2b00 cmp r3, #0
801204e: d006 beq.n 801205e <tcp_pcb_remove+0xf6>
8012050: 4b08 ldr r3, [pc, #32] ; (8012074 <tcp_pcb_remove+0x10c>)
8012052: f640 0296 movw r2, #2198 ; 0x896
8012056: 490d ldr r1, [pc, #52] ; (801208c <tcp_pcb_remove+0x124>)
8012058: 4808 ldr r0, [pc, #32] ; (801207c <tcp_pcb_remove+0x114>)
801205a: f008 ffdb bl 801b014 <iprintf>
#endif /* TCP_QUEUE_OOSEQ */
}
pcb->state = CLOSED;
801205e: 683b ldr r3, [r7, #0]
8012060: 2200 movs r2, #0
8012062: 751a strb r2, [r3, #20]
/* reset the local port to prevent the pcb from being 'bound' */
pcb->local_port = 0;
8012064: 683b ldr r3, [r7, #0]
8012066: 2200 movs r2, #0
8012068: 82da strh r2, [r3, #22]
LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
}
801206a: bf00 nop
801206c: 3710 adds r7, #16
801206e: 46bd mov sp, r7
8012070: bd80 pop {r7, pc}
8012072: bf00 nop
8012074: 0801cb48 .word 0x0801cb48
8012078: 0801d1b0 .word 0x0801d1b0
801207c: 0801cb8c .word 0x0801cb8c
8012080: 0801d1cc .word 0x0801d1cc
8012084: 0801d1ec .word 0x0801d1ec
8012088: 0801d204 .word 0x0801d204
801208c: 0801d220 .word 0x0801d220
08012090 <tcp_next_iss>:
*
* @return u32_t pseudo random sequence number
*/
u32_t
tcp_next_iss(struct tcp_pcb *pcb)
{
8012090: b580 push {r7, lr}
8012092: b082 sub sp, #8
8012094: af00 add r7, sp, #0
8012096: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
#else /* LWIP_HOOK_TCP_ISN */
static u32_t iss = 6510;
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
8012098: 687b ldr r3, [r7, #4]
801209a: 2b00 cmp r3, #0
801209c: d106 bne.n 80120ac <tcp_next_iss+0x1c>
801209e: 4b0a ldr r3, [pc, #40] ; (80120c8 <tcp_next_iss+0x38>)
80120a0: f640 02af movw r2, #2223 ; 0x8af
80120a4: 4909 ldr r1, [pc, #36] ; (80120cc <tcp_next_iss+0x3c>)
80120a6: 480a ldr r0, [pc, #40] ; (80120d0 <tcp_next_iss+0x40>)
80120a8: f008 ffb4 bl 801b014 <iprintf>
LWIP_UNUSED_ARG(pcb);
iss += tcp_ticks; /* XXX */
80120ac: 4b09 ldr r3, [pc, #36] ; (80120d4 <tcp_next_iss+0x44>)
80120ae: 681a ldr r2, [r3, #0]
80120b0: 4b09 ldr r3, [pc, #36] ; (80120d8 <tcp_next_iss+0x48>)
80120b2: 681b ldr r3, [r3, #0]
80120b4: 4413 add r3, r2
80120b6: 4a07 ldr r2, [pc, #28] ; (80120d4 <tcp_next_iss+0x44>)
80120b8: 6013 str r3, [r2, #0]
return iss;
80120ba: 4b06 ldr r3, [pc, #24] ; (80120d4 <tcp_next_iss+0x44>)
80120bc: 681b ldr r3, [r3, #0]
#endif /* LWIP_HOOK_TCP_ISN */
}
80120be: 4618 mov r0, r3
80120c0: 3708 adds r7, #8
80120c2: 46bd mov sp, r7
80120c4: bd80 pop {r7, pc}
80120c6: bf00 nop
80120c8: 0801cb48 .word 0x0801cb48
80120cc: 0801d238 .word 0x0801d238
80120d0: 0801cb8c .word 0x0801cb8c
80120d4: 20000078 .word 0x20000078
80120d8: 2000f5c4 .word 0x2000f5c4
080120dc <tcp_eff_send_mss_netif>:
* by calculating the minimum of TCP_MSS and the mtu (if set) of the target
* netif (if not NULL).
*/
u16_t
tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
{
80120dc: b580 push {r7, lr}
80120de: b086 sub sp, #24
80120e0: af00 add r7, sp, #0
80120e2: 4603 mov r3, r0
80120e4: 60b9 str r1, [r7, #8]
80120e6: 607a str r2, [r7, #4]
80120e8: 81fb strh r3, [r7, #14]
u16_t mss_s;
u16_t mtu;
LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
80120ea: 687b ldr r3, [r7, #4]
80120ec: 2b00 cmp r3, #0
80120ee: d106 bne.n 80120fe <tcp_eff_send_mss_netif+0x22>
80120f0: 4b14 ldr r3, [pc, #80] ; (8012144 <tcp_eff_send_mss_netif+0x68>)
80120f2: f640 02c5 movw r2, #2245 ; 0x8c5
80120f6: 4914 ldr r1, [pc, #80] ; (8012148 <tcp_eff_send_mss_netif+0x6c>)
80120f8: 4814 ldr r0, [pc, #80] ; (801214c <tcp_eff_send_mss_netif+0x70>)
80120fa: f008 ff8b bl 801b014 <iprintf>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
if (outif == NULL) {
80120fe: 68bb ldr r3, [r7, #8]
8012100: 2b00 cmp r3, #0
8012102: d101 bne.n 8012108 <tcp_eff_send_mss_netif+0x2c>
return sendmss;
8012104: 89fb ldrh r3, [r7, #14]
8012106: e019 b.n 801213c <tcp_eff_send_mss_netif+0x60>
}
mtu = outif->mtu;
8012108: 68bb ldr r3, [r7, #8]
801210a: 8d1b ldrh r3, [r3, #40] ; 0x28
801210c: 82fb strh r3, [r7, #22]
}
#endif /* LWIP_IPV4 */
if (mtu != 0) {
801210e: 8afb ldrh r3, [r7, #22]
8012110: 2b00 cmp r3, #0
8012112: d012 beq.n 801213a <tcp_eff_send_mss_netif+0x5e>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
offset = IP_HLEN + TCP_HLEN;
8012114: 2328 movs r3, #40 ; 0x28
8012116: 82bb strh r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
8012118: 8afa ldrh r2, [r7, #22]
801211a: 8abb ldrh r3, [r7, #20]
801211c: 429a cmp r2, r3
801211e: d904 bls.n 801212a <tcp_eff_send_mss_netif+0x4e>
8012120: 8afa ldrh r2, [r7, #22]
8012122: 8abb ldrh r3, [r7, #20]
8012124: 1ad3 subs r3, r2, r3
8012126: b29b uxth r3, r3
8012128: e000 b.n 801212c <tcp_eff_send_mss_netif+0x50>
801212a: 2300 movs r3, #0
801212c: 827b strh r3, [r7, #18]
/* RFC 1122, chap 4.2.2.6:
* Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
* We correct for TCP options in tcp_write(), and don't support IP options.
*/
sendmss = LWIP_MIN(sendmss, mss_s);
801212e: 8a7a ldrh r2, [r7, #18]
8012130: 89fb ldrh r3, [r7, #14]
8012132: 4293 cmp r3, r2
8012134: bf28 it cs
8012136: 4613 movcs r3, r2
8012138: 81fb strh r3, [r7, #14]
}
return sendmss;
801213a: 89fb ldrh r3, [r7, #14]
}
801213c: 4618 mov r0, r3
801213e: 3718 adds r7, #24
8012140: 46bd mov sp, r7
8012142: bd80 pop {r7, pc}
8012144: 0801cb48 .word 0x0801cb48
8012148: 0801d254 .word 0x0801d254
801214c: 0801cb8c .word 0x0801cb8c
08012150 <tcp_netif_ip_addr_changed_pcblist>:
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
static void
tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
{
8012150: b580 push {r7, lr}
8012152: b084 sub sp, #16
8012154: af00 add r7, sp, #0
8012156: 6078 str r0, [r7, #4]
8012158: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
pcb = pcb_list;
801215a: 683b ldr r3, [r7, #0]
801215c: 60fb str r3, [r7, #12]
LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
801215e: 687b ldr r3, [r7, #4]
8012160: 2b00 cmp r3, #0
8012162: d119 bne.n 8012198 <tcp_netif_ip_addr_changed_pcblist+0x48>
8012164: 4b10 ldr r3, [pc, #64] ; (80121a8 <tcp_netif_ip_addr_changed_pcblist+0x58>)
8012166: f44f 6210 mov.w r2, #2304 ; 0x900
801216a: 4910 ldr r1, [pc, #64] ; (80121ac <tcp_netif_ip_addr_changed_pcblist+0x5c>)
801216c: 4810 ldr r0, [pc, #64] ; (80121b0 <tcp_netif_ip_addr_changed_pcblist+0x60>)
801216e: f008 ff51 bl 801b014 <iprintf>
while (pcb != NULL) {
8012172: e011 b.n 8012198 <tcp_netif_ip_addr_changed_pcblist+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&pcb->local_ip, old_addr)
8012174: 68fb ldr r3, [r7, #12]
8012176: 681a ldr r2, [r3, #0]
8012178: 687b ldr r3, [r7, #4]
801217a: 681b ldr r3, [r3, #0]
801217c: 429a cmp r2, r3
801217e: d108 bne.n 8012192 <tcp_netif_ip_addr_changed_pcblist+0x42>
/* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
&& (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
#endif /* LWIP_AUTOIP */
) {
/* this connection must be aborted */
struct tcp_pcb *next = pcb->next;
8012180: 68fb ldr r3, [r7, #12]
8012182: 68db ldr r3, [r3, #12]
8012184: 60bb str r3, [r7, #8]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
tcp_abort(pcb);
8012186: 68f8 ldr r0, [r7, #12]
8012188: f7fe ffca bl 8011120 <tcp_abort>
pcb = next;
801218c: 68bb ldr r3, [r7, #8]
801218e: 60fb str r3, [r7, #12]
8012190: e002 b.n 8012198 <tcp_netif_ip_addr_changed_pcblist+0x48>
} else {
pcb = pcb->next;
8012192: 68fb ldr r3, [r7, #12]
8012194: 68db ldr r3, [r3, #12]
8012196: 60fb str r3, [r7, #12]
while (pcb != NULL) {
8012198: 68fb ldr r3, [r7, #12]
801219a: 2b00 cmp r3, #0
801219c: d1ea bne.n 8012174 <tcp_netif_ip_addr_changed_pcblist+0x24>
}
}
}
801219e: bf00 nop
80121a0: 3710 adds r7, #16
80121a2: 46bd mov sp, r7
80121a4: bd80 pop {r7, pc}
80121a6: bf00 nop
80121a8: 0801cb48 .word 0x0801cb48
80121ac: 0801d27c .word 0x0801d27c
80121b0: 0801cb8c .word 0x0801cb8c
080121b4 <tcp_netif_ip_addr_changed>:
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change or NULL if netif has been removed
*/
void
tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
80121b4: b580 push {r7, lr}
80121b6: b084 sub sp, #16
80121b8: af00 add r7, sp, #0
80121ba: 6078 str r0, [r7, #4]
80121bc: 6039 str r1, [r7, #0]
struct tcp_pcb_listen *lpcb;
if (!ip_addr_isany(old_addr)) {
80121be: 687b ldr r3, [r7, #4]
80121c0: 2b00 cmp r3, #0
80121c2: d02a beq.n 801221a <tcp_netif_ip_addr_changed+0x66>
80121c4: 687b ldr r3, [r7, #4]
80121c6: 681b ldr r3, [r3, #0]
80121c8: 2b00 cmp r3, #0
80121ca: d026 beq.n 801221a <tcp_netif_ip_addr_changed+0x66>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
80121cc: 4b15 ldr r3, [pc, #84] ; (8012224 <tcp_netif_ip_addr_changed+0x70>)
80121ce: 681b ldr r3, [r3, #0]
80121d0: 4619 mov r1, r3
80121d2: 6878 ldr r0, [r7, #4]
80121d4: f7ff ffbc bl 8012150 <tcp_netif_ip_addr_changed_pcblist>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
80121d8: 4b13 ldr r3, [pc, #76] ; (8012228 <tcp_netif_ip_addr_changed+0x74>)
80121da: 681b ldr r3, [r3, #0]
80121dc: 4619 mov r1, r3
80121de: 6878 ldr r0, [r7, #4]
80121e0: f7ff ffb6 bl 8012150 <tcp_netif_ip_addr_changed_pcblist>
if (!ip_addr_isany(new_addr)) {
80121e4: 683b ldr r3, [r7, #0]
80121e6: 2b00 cmp r3, #0
80121e8: d017 beq.n 801221a <tcp_netif_ip_addr_changed+0x66>
80121ea: 683b ldr r3, [r7, #0]
80121ec: 681b ldr r3, [r3, #0]
80121ee: 2b00 cmp r3, #0
80121f0: d013 beq.n 801221a <tcp_netif_ip_addr_changed+0x66>
/* PCB bound to current local interface address? */
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
80121f2: 4b0e ldr r3, [pc, #56] ; (801222c <tcp_netif_ip_addr_changed+0x78>)
80121f4: 681b ldr r3, [r3, #0]
80121f6: 60fb str r3, [r7, #12]
80121f8: e00c b.n 8012214 <tcp_netif_ip_addr_changed+0x60>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
80121fa: 68fb ldr r3, [r7, #12]
80121fc: 681a ldr r2, [r3, #0]
80121fe: 687b ldr r3, [r7, #4]
8012200: 681b ldr r3, [r3, #0]
8012202: 429a cmp r2, r3
8012204: d103 bne.n 801220e <tcp_netif_ip_addr_changed+0x5a>
/* The PCB is listening to the old ipaddr and
* is set to listen to the new one instead */
ip_addr_copy(lpcb->local_ip, *new_addr);
8012206: 683b ldr r3, [r7, #0]
8012208: 681a ldr r2, [r3, #0]
801220a: 68fb ldr r3, [r7, #12]
801220c: 601a str r2, [r3, #0]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
801220e: 68fb ldr r3, [r7, #12]
8012210: 68db ldr r3, [r3, #12]
8012212: 60fb str r3, [r7, #12]
8012214: 68fb ldr r3, [r7, #12]
8012216: 2b00 cmp r3, #0
8012218: d1ef bne.n 80121fa <tcp_netif_ip_addr_changed+0x46>
}
}
}
}
}
801221a: bf00 nop
801221c: 3710 adds r7, #16
801221e: 46bd mov sp, r7
8012220: bd80 pop {r7, pc}
8012222: bf00 nop
8012224: 2000f5c0 .word 0x2000f5c0
8012228: 2000f5cc .word 0x2000f5cc
801222c: 2000f5c8 .word 0x2000f5c8
08012230 <tcp_free_ooseq>:
#if TCP_QUEUE_OOSEQ
/* Free all ooseq pbufs (and possibly reset SACK state) */
void
tcp_free_ooseq(struct tcp_pcb *pcb)
{
8012230: b580 push {r7, lr}
8012232: b082 sub sp, #8
8012234: af00 add r7, sp, #0
8012236: 6078 str r0, [r7, #4]
if (pcb->ooseq) {
8012238: 687b ldr r3, [r7, #4]
801223a: 6f5b ldr r3, [r3, #116] ; 0x74
801223c: 2b00 cmp r3, #0
801223e: d007 beq.n 8012250 <tcp_free_ooseq+0x20>
tcp_segs_free(pcb->ooseq);
8012240: 687b ldr r3, [r7, #4]
8012242: 6f5b ldr r3, [r3, #116] ; 0x74
8012244: 4618 mov r0, r3
8012246: f7ff fc3f bl 8011ac8 <tcp_segs_free>
pcb->ooseq = NULL;
801224a: 687b ldr r3, [r7, #4]
801224c: 2200 movs r2, #0
801224e: 675a str r2, [r3, #116] ; 0x74
#if LWIP_TCP_SACK_OUT
memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
#endif /* LWIP_TCP_SACK_OUT */
}
}
8012250: bf00 nop
8012252: 3708 adds r7, #8
8012254: 46bd mov sp, r7
8012256: bd80 pop {r7, pc}
08012258 <tcp_input>:
* @param p received TCP segment to process (p->payload pointing to the TCP header)
* @param inp network interface on which this segment was received
*/
void
tcp_input(struct pbuf *p, struct netif *inp)
{
8012258: b590 push {r4, r7, lr}
801225a: b08d sub sp, #52 ; 0x34
801225c: af04 add r7, sp, #16
801225e: 6078 str r0, [r7, #4]
8012260: 6039 str r1, [r7, #0]
u8_t hdrlen_bytes;
err_t err;
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
8012262: 687b ldr r3, [r7, #4]
8012264: 2b00 cmp r3, #0
8012266: d105 bne.n 8012274 <tcp_input+0x1c>
8012268: 4b9b ldr r3, [pc, #620] ; (80124d8 <tcp_input+0x280>)
801226a: 2283 movs r2, #131 ; 0x83
801226c: 499b ldr r1, [pc, #620] ; (80124dc <tcp_input+0x284>)
801226e: 489c ldr r0, [pc, #624] ; (80124e0 <tcp_input+0x288>)
8012270: f008 fed0 bl 801b014 <iprintf>
PERF_START;
TCP_STATS_INC(tcp.recv);
MIB2_STATS_INC(mib2.tcpinsegs);
tcphdr = (struct tcp_hdr *)p->payload;
8012274: 687b ldr r3, [r7, #4]
8012276: 685b ldr r3, [r3, #4]
8012278: 4a9a ldr r2, [pc, #616] ; (80124e4 <tcp_input+0x28c>)
801227a: 6013 str r3, [r2, #0]
#if TCP_INPUT_DEBUG
tcp_debug_print(tcphdr);
#endif
/* Check that TCP header fits in payload */
if (p->len < TCP_HLEN) {
801227c: 687b ldr r3, [r7, #4]
801227e: 895b ldrh r3, [r3, #10]
8012280: 2b13 cmp r3, #19
8012282: f240 83c4 bls.w 8012a0e <tcp_input+0x7b6>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* Don't even process incoming broadcasts/multicasts. */
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
8012286: 4b98 ldr r3, [pc, #608] ; (80124e8 <tcp_input+0x290>)
8012288: 695a ldr r2, [r3, #20]
801228a: 4b97 ldr r3, [pc, #604] ; (80124e8 <tcp_input+0x290>)
801228c: 681b ldr r3, [r3, #0]
801228e: 4619 mov r1, r3
8012290: 4610 mov r0, r2
8012292: f007 fe17 bl 8019ec4 <ip4_addr_isbroadcast_u32>
8012296: 4603 mov r3, r0
8012298: 2b00 cmp r3, #0
801229a: f040 83ba bne.w 8012a12 <tcp_input+0x7ba>
ip_addr_ismulticast(ip_current_dest_addr())) {
801229e: 4b92 ldr r3, [pc, #584] ; (80124e8 <tcp_input+0x290>)
80122a0: 695b ldr r3, [r3, #20]
80122a2: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
80122a6: 2be0 cmp r3, #224 ; 0xe0
80122a8: f000 83b3 beq.w 8012a12 <tcp_input+0x7ba>
}
}
#endif /* CHECKSUM_CHECK_TCP */
/* sanity-check header length */
hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
80122ac: 4b8d ldr r3, [pc, #564] ; (80124e4 <tcp_input+0x28c>)
80122ae: 681b ldr r3, [r3, #0]
80122b0: 899b ldrh r3, [r3, #12]
80122b2: b29b uxth r3, r3
80122b4: 4618 mov r0, r3
80122b6: f7fc fde3 bl 800ee80 <lwip_htons>
80122ba: 4603 mov r3, r0
80122bc: 0b1b lsrs r3, r3, #12
80122be: b29b uxth r3, r3
80122c0: b2db uxtb r3, r3
80122c2: 009b lsls r3, r3, #2
80122c4: 74bb strb r3, [r7, #18]
if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
80122c6: 7cbb ldrb r3, [r7, #18]
80122c8: 2b13 cmp r3, #19
80122ca: f240 83a2 bls.w 8012a12 <tcp_input+0x7ba>
80122ce: 7cbb ldrb r3, [r7, #18]
80122d0: b29a uxth r2, r3
80122d2: 687b ldr r3, [r7, #4]
80122d4: 891b ldrh r3, [r3, #8]
80122d6: 429a cmp r2, r3
80122d8: f200 839b bhi.w 8012a12 <tcp_input+0x7ba>
goto dropped;
}
/* Move the payload pointer in the pbuf so that it points to the
TCP data instead of the TCP header. */
tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
80122dc: 7cbb ldrb r3, [r7, #18]
80122de: b29b uxth r3, r3
80122e0: 3b14 subs r3, #20
80122e2: b29a uxth r2, r3
80122e4: 4b81 ldr r3, [pc, #516] ; (80124ec <tcp_input+0x294>)
80122e6: 801a strh r2, [r3, #0]
tcphdr_opt2 = NULL;
80122e8: 4b81 ldr r3, [pc, #516] ; (80124f0 <tcp_input+0x298>)
80122ea: 2200 movs r2, #0
80122ec: 601a str r2, [r3, #0]
if (p->len >= hdrlen_bytes) {
80122ee: 687b ldr r3, [r7, #4]
80122f0: 895a ldrh r2, [r3, #10]
80122f2: 7cbb ldrb r3, [r7, #18]
80122f4: b29b uxth r3, r3
80122f6: 429a cmp r2, r3
80122f8: d309 bcc.n 801230e <tcp_input+0xb6>
/* all options are in the first pbuf */
tcphdr_opt1len = tcphdr_optlen;
80122fa: 4b7c ldr r3, [pc, #496] ; (80124ec <tcp_input+0x294>)
80122fc: 881a ldrh r2, [r3, #0]
80122fe: 4b7d ldr r3, [pc, #500] ; (80124f4 <tcp_input+0x29c>)
8012300: 801a strh r2, [r3, #0]
pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
8012302: 7cbb ldrb r3, [r7, #18]
8012304: 4619 mov r1, r3
8012306: 6878 ldr r0, [r7, #4]
8012308: f7fe f8e8 bl 80104dc <pbuf_remove_header>
801230c: e04e b.n 80123ac <tcp_input+0x154>
} else {
u16_t opt2len;
/* TCP header fits into first pbuf, options don't - data is in the next pbuf */
/* there must be a next pbuf, due to hdrlen_bytes sanity check above */
LWIP_ASSERT("p->next != NULL", p->next != NULL);
801230e: 687b ldr r3, [r7, #4]
8012310: 681b ldr r3, [r3, #0]
8012312: 2b00 cmp r3, #0
8012314: d105 bne.n 8012322 <tcp_input+0xca>
8012316: 4b70 ldr r3, [pc, #448] ; (80124d8 <tcp_input+0x280>)
8012318: 22c2 movs r2, #194 ; 0xc2
801231a: 4977 ldr r1, [pc, #476] ; (80124f8 <tcp_input+0x2a0>)
801231c: 4870 ldr r0, [pc, #448] ; (80124e0 <tcp_input+0x288>)
801231e: f008 fe79 bl 801b014 <iprintf>
/* advance over the TCP header (cannot fail) */
pbuf_remove_header(p, TCP_HLEN);
8012322: 2114 movs r1, #20
8012324: 6878 ldr r0, [r7, #4]
8012326: f7fe f8d9 bl 80104dc <pbuf_remove_header>
/* determine how long the first and second parts of the options are */
tcphdr_opt1len = p->len;
801232a: 687b ldr r3, [r7, #4]
801232c: 895a ldrh r2, [r3, #10]
801232e: 4b71 ldr r3, [pc, #452] ; (80124f4 <tcp_input+0x29c>)
8012330: 801a strh r2, [r3, #0]
opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
8012332: 4b6e ldr r3, [pc, #440] ; (80124ec <tcp_input+0x294>)
8012334: 881a ldrh r2, [r3, #0]
8012336: 4b6f ldr r3, [pc, #444] ; (80124f4 <tcp_input+0x29c>)
8012338: 881b ldrh r3, [r3, #0]
801233a: 1ad3 subs r3, r2, r3
801233c: 823b strh r3, [r7, #16]
/* options continue in the next pbuf: set p to zero length and hide the
options in the next pbuf (adjusting p->tot_len) */
pbuf_remove_header(p, tcphdr_opt1len);
801233e: 4b6d ldr r3, [pc, #436] ; (80124f4 <tcp_input+0x29c>)
8012340: 881b ldrh r3, [r3, #0]
8012342: 4619 mov r1, r3
8012344: 6878 ldr r0, [r7, #4]
8012346: f7fe f8c9 bl 80104dc <pbuf_remove_header>
/* check that the options fit in the second pbuf */
if (opt2len > p->next->len) {
801234a: 687b ldr r3, [r7, #4]
801234c: 681b ldr r3, [r3, #0]
801234e: 895b ldrh r3, [r3, #10]
8012350: 8a3a ldrh r2, [r7, #16]
8012352: 429a cmp r2, r3
8012354: f200 835f bhi.w 8012a16 <tcp_input+0x7be>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* remember the pointer to the second part of the options */
tcphdr_opt2 = (u8_t *)p->next->payload;
8012358: 687b ldr r3, [r7, #4]
801235a: 681b ldr r3, [r3, #0]
801235c: 685b ldr r3, [r3, #4]
801235e: 4a64 ldr r2, [pc, #400] ; (80124f0 <tcp_input+0x298>)
8012360: 6013 str r3, [r2, #0]
/* advance p->next to point after the options, and manually
adjust p->tot_len to keep it consistent with the changed p->next */
pbuf_remove_header(p->next, opt2len);
8012362: 687b ldr r3, [r7, #4]
8012364: 681b ldr r3, [r3, #0]
8012366: 8a3a ldrh r2, [r7, #16]
8012368: 4611 mov r1, r2
801236a: 4618 mov r0, r3
801236c: f7fe f8b6 bl 80104dc <pbuf_remove_header>
p->tot_len = (u16_t)(p->tot_len - opt2len);
8012370: 687b ldr r3, [r7, #4]
8012372: 891a ldrh r2, [r3, #8]
8012374: 8a3b ldrh r3, [r7, #16]
8012376: 1ad3 subs r3, r2, r3
8012378: b29a uxth r2, r3
801237a: 687b ldr r3, [r7, #4]
801237c: 811a strh r2, [r3, #8]
LWIP_ASSERT("p->len == 0", p->len == 0);
801237e: 687b ldr r3, [r7, #4]
8012380: 895b ldrh r3, [r3, #10]
8012382: 2b00 cmp r3, #0
8012384: d005 beq.n 8012392 <tcp_input+0x13a>
8012386: 4b54 ldr r3, [pc, #336] ; (80124d8 <tcp_input+0x280>)
8012388: 22df movs r2, #223 ; 0xdf
801238a: 495c ldr r1, [pc, #368] ; (80124fc <tcp_input+0x2a4>)
801238c: 4854 ldr r0, [pc, #336] ; (80124e0 <tcp_input+0x288>)
801238e: f008 fe41 bl 801b014 <iprintf>
LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
8012392: 687b ldr r3, [r7, #4]
8012394: 891a ldrh r2, [r3, #8]
8012396: 687b ldr r3, [r7, #4]
8012398: 681b ldr r3, [r3, #0]
801239a: 891b ldrh r3, [r3, #8]
801239c: 429a cmp r2, r3
801239e: d005 beq.n 80123ac <tcp_input+0x154>
80123a0: 4b4d ldr r3, [pc, #308] ; (80124d8 <tcp_input+0x280>)
80123a2: 22e0 movs r2, #224 ; 0xe0
80123a4: 4956 ldr r1, [pc, #344] ; (8012500 <tcp_input+0x2a8>)
80123a6: 484e ldr r0, [pc, #312] ; (80124e0 <tcp_input+0x288>)
80123a8: f008 fe34 bl 801b014 <iprintf>
}
/* Convert fields in TCP header to host byte order. */
tcphdr->src = lwip_ntohs(tcphdr->src);
80123ac: 4b4d ldr r3, [pc, #308] ; (80124e4 <tcp_input+0x28c>)
80123ae: 681b ldr r3, [r3, #0]
80123b0: 881b ldrh r3, [r3, #0]
80123b2: b29a uxth r2, r3
80123b4: 4b4b ldr r3, [pc, #300] ; (80124e4 <tcp_input+0x28c>)
80123b6: 681c ldr r4, [r3, #0]
80123b8: 4610 mov r0, r2
80123ba: f7fc fd61 bl 800ee80 <lwip_htons>
80123be: 4603 mov r3, r0
80123c0: 8023 strh r3, [r4, #0]
tcphdr->dest = lwip_ntohs(tcphdr->dest);
80123c2: 4b48 ldr r3, [pc, #288] ; (80124e4 <tcp_input+0x28c>)
80123c4: 681b ldr r3, [r3, #0]
80123c6: 885b ldrh r3, [r3, #2]
80123c8: b29a uxth r2, r3
80123ca: 4b46 ldr r3, [pc, #280] ; (80124e4 <tcp_input+0x28c>)
80123cc: 681c ldr r4, [r3, #0]
80123ce: 4610 mov r0, r2
80123d0: f7fc fd56 bl 800ee80 <lwip_htons>
80123d4: 4603 mov r3, r0
80123d6: 8063 strh r3, [r4, #2]
seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
80123d8: 4b42 ldr r3, [pc, #264] ; (80124e4 <tcp_input+0x28c>)
80123da: 681b ldr r3, [r3, #0]
80123dc: 685a ldr r2, [r3, #4]
80123de: 4b41 ldr r3, [pc, #260] ; (80124e4 <tcp_input+0x28c>)
80123e0: 681c ldr r4, [r3, #0]
80123e2: 4610 mov r0, r2
80123e4: f7fc fd61 bl 800eeaa <lwip_htonl>
80123e8: 4603 mov r3, r0
80123ea: 6063 str r3, [r4, #4]
80123ec: 6863 ldr r3, [r4, #4]
80123ee: 4a45 ldr r2, [pc, #276] ; (8012504 <tcp_input+0x2ac>)
80123f0: 6013 str r3, [r2, #0]
ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
80123f2: 4b3c ldr r3, [pc, #240] ; (80124e4 <tcp_input+0x28c>)
80123f4: 681b ldr r3, [r3, #0]
80123f6: 689a ldr r2, [r3, #8]
80123f8: 4b3a ldr r3, [pc, #232] ; (80124e4 <tcp_input+0x28c>)
80123fa: 681c ldr r4, [r3, #0]
80123fc: 4610 mov r0, r2
80123fe: f7fc fd54 bl 800eeaa <lwip_htonl>
8012402: 4603 mov r3, r0
8012404: 60a3 str r3, [r4, #8]
8012406: 68a3 ldr r3, [r4, #8]
8012408: 4a3f ldr r2, [pc, #252] ; (8012508 <tcp_input+0x2b0>)
801240a: 6013 str r3, [r2, #0]
tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
801240c: 4b35 ldr r3, [pc, #212] ; (80124e4 <tcp_input+0x28c>)
801240e: 681b ldr r3, [r3, #0]
8012410: 89db ldrh r3, [r3, #14]
8012412: b29a uxth r2, r3
8012414: 4b33 ldr r3, [pc, #204] ; (80124e4 <tcp_input+0x28c>)
8012416: 681c ldr r4, [r3, #0]
8012418: 4610 mov r0, r2
801241a: f7fc fd31 bl 800ee80 <lwip_htons>
801241e: 4603 mov r3, r0
8012420: 81e3 strh r3, [r4, #14]
flags = TCPH_FLAGS(tcphdr);
8012422: 4b30 ldr r3, [pc, #192] ; (80124e4 <tcp_input+0x28c>)
8012424: 681b ldr r3, [r3, #0]
8012426: 899b ldrh r3, [r3, #12]
8012428: b29b uxth r3, r3
801242a: 4618 mov r0, r3
801242c: f7fc fd28 bl 800ee80 <lwip_htons>
8012430: 4603 mov r3, r0
8012432: b2db uxtb r3, r3
8012434: f003 033f and.w r3, r3, #63 ; 0x3f
8012438: b2da uxtb r2, r3
801243a: 4b34 ldr r3, [pc, #208] ; (801250c <tcp_input+0x2b4>)
801243c: 701a strb r2, [r3, #0]
tcplen = p->tot_len;
801243e: 687b ldr r3, [r7, #4]
8012440: 891a ldrh r2, [r3, #8]
8012442: 4b33 ldr r3, [pc, #204] ; (8012510 <tcp_input+0x2b8>)
8012444: 801a strh r2, [r3, #0]
if (flags & (TCP_FIN | TCP_SYN)) {
8012446: 4b31 ldr r3, [pc, #196] ; (801250c <tcp_input+0x2b4>)
8012448: 781b ldrb r3, [r3, #0]
801244a: f003 0303 and.w r3, r3, #3
801244e: 2b00 cmp r3, #0
8012450: d00c beq.n 801246c <tcp_input+0x214>
tcplen++;
8012452: 4b2f ldr r3, [pc, #188] ; (8012510 <tcp_input+0x2b8>)
8012454: 881b ldrh r3, [r3, #0]
8012456: 3301 adds r3, #1
8012458: b29a uxth r2, r3
801245a: 4b2d ldr r3, [pc, #180] ; (8012510 <tcp_input+0x2b8>)
801245c: 801a strh r2, [r3, #0]
if (tcplen < p->tot_len) {
801245e: 687b ldr r3, [r7, #4]
8012460: 891a ldrh r2, [r3, #8]
8012462: 4b2b ldr r3, [pc, #172] ; (8012510 <tcp_input+0x2b8>)
8012464: 881b ldrh r3, [r3, #0]
8012466: 429a cmp r2, r3
8012468: f200 82d7 bhi.w 8012a1a <tcp_input+0x7c2>
}
}
/* Demultiplex an incoming segment. First, we check if it is destined
for an active connection. */
prev = NULL;
801246c: 2300 movs r3, #0
801246e: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8012470: 4b28 ldr r3, [pc, #160] ; (8012514 <tcp_input+0x2bc>)
8012472: 681b ldr r3, [r3, #0]
8012474: 61fb str r3, [r7, #28]
8012476: e09d b.n 80125b4 <tcp_input+0x35c>
LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
8012478: 69fb ldr r3, [r7, #28]
801247a: 7d1b ldrb r3, [r3, #20]
801247c: 2b00 cmp r3, #0
801247e: d105 bne.n 801248c <tcp_input+0x234>
8012480: 4b15 ldr r3, [pc, #84] ; (80124d8 <tcp_input+0x280>)
8012482: 22fb movs r2, #251 ; 0xfb
8012484: 4924 ldr r1, [pc, #144] ; (8012518 <tcp_input+0x2c0>)
8012486: 4816 ldr r0, [pc, #88] ; (80124e0 <tcp_input+0x288>)
8012488: f008 fdc4 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
801248c: 69fb ldr r3, [r7, #28]
801248e: 7d1b ldrb r3, [r3, #20]
8012490: 2b0a cmp r3, #10
8012492: d105 bne.n 80124a0 <tcp_input+0x248>
8012494: 4b10 ldr r3, [pc, #64] ; (80124d8 <tcp_input+0x280>)
8012496: 22fc movs r2, #252 ; 0xfc
8012498: 4920 ldr r1, [pc, #128] ; (801251c <tcp_input+0x2c4>)
801249a: 4811 ldr r0, [pc, #68] ; (80124e0 <tcp_input+0x288>)
801249c: f008 fdba bl 801b014 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
80124a0: 69fb ldr r3, [r7, #28]
80124a2: 7d1b ldrb r3, [r3, #20]
80124a4: 2b01 cmp r3, #1
80124a6: d105 bne.n 80124b4 <tcp_input+0x25c>
80124a8: 4b0b ldr r3, [pc, #44] ; (80124d8 <tcp_input+0x280>)
80124aa: 22fd movs r2, #253 ; 0xfd
80124ac: 491c ldr r1, [pc, #112] ; (8012520 <tcp_input+0x2c8>)
80124ae: 480c ldr r0, [pc, #48] ; (80124e0 <tcp_input+0x288>)
80124b0: f008 fdb0 bl 801b014 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80124b4: 69fb ldr r3, [r7, #28]
80124b6: 7a1b ldrb r3, [r3, #8]
80124b8: 2b00 cmp r3, #0
80124ba: d033 beq.n 8012524 <tcp_input+0x2cc>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80124bc: 69fb ldr r3, [r7, #28]
80124be: 7a1a ldrb r2, [r3, #8]
80124c0: 4b09 ldr r3, [pc, #36] ; (80124e8 <tcp_input+0x290>)
80124c2: 685b ldr r3, [r3, #4]
80124c4: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80124c8: 3301 adds r3, #1
80124ca: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80124cc: 429a cmp r2, r3
80124ce: d029 beq.n 8012524 <tcp_input+0x2cc>
prev = pcb;
80124d0: 69fb ldr r3, [r7, #28]
80124d2: 61bb str r3, [r7, #24]
continue;
80124d4: e06b b.n 80125ae <tcp_input+0x356>
80124d6: bf00 nop
80124d8: 0801d2b0 .word 0x0801d2b0
80124dc: 0801d2e4 .word 0x0801d2e4
80124e0: 0801d2fc .word 0x0801d2fc
80124e4: 2000873c .word 0x2000873c
80124e8: 2000be8c .word 0x2000be8c
80124ec: 20008740 .word 0x20008740
80124f0: 20008744 .word 0x20008744
80124f4: 20008742 .word 0x20008742
80124f8: 0801d324 .word 0x0801d324
80124fc: 0801d334 .word 0x0801d334
8012500: 0801d340 .word 0x0801d340
8012504: 2000874c .word 0x2000874c
8012508: 20008750 .word 0x20008750
801250c: 20008758 .word 0x20008758
8012510: 20008756 .word 0x20008756
8012514: 2000f5c0 .word 0x2000f5c0
8012518: 0801d360 .word 0x0801d360
801251c: 0801d388 .word 0x0801d388
8012520: 0801d3b4 .word 0x0801d3b4
}
if (pcb->remote_port == tcphdr->src &&
8012524: 69fb ldr r3, [r7, #28]
8012526: 8b1a ldrh r2, [r3, #24]
8012528: 4b94 ldr r3, [pc, #592] ; (801277c <tcp_input+0x524>)
801252a: 681b ldr r3, [r3, #0]
801252c: 881b ldrh r3, [r3, #0]
801252e: b29b uxth r3, r3
8012530: 429a cmp r2, r3
8012532: d13a bne.n 80125aa <tcp_input+0x352>
pcb->local_port == tcphdr->dest &&
8012534: 69fb ldr r3, [r7, #28]
8012536: 8ada ldrh r2, [r3, #22]
8012538: 4b90 ldr r3, [pc, #576] ; (801277c <tcp_input+0x524>)
801253a: 681b ldr r3, [r3, #0]
801253c: 885b ldrh r3, [r3, #2]
801253e: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
8012540: 429a cmp r2, r3
8012542: d132 bne.n 80125aa <tcp_input+0x352>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012544: 69fb ldr r3, [r7, #28]
8012546: 685a ldr r2, [r3, #4]
8012548: 4b8d ldr r3, [pc, #564] ; (8012780 <tcp_input+0x528>)
801254a: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
801254c: 429a cmp r2, r3
801254e: d12c bne.n 80125aa <tcp_input+0x352>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
8012550: 69fb ldr r3, [r7, #28]
8012552: 681a ldr r2, [r3, #0]
8012554: 4b8a ldr r3, [pc, #552] ; (8012780 <tcp_input+0x528>)
8012556: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012558: 429a cmp r2, r3
801255a: d126 bne.n 80125aa <tcp_input+0x352>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
801255c: 69fb ldr r3, [r7, #28]
801255e: 68db ldr r3, [r3, #12]
8012560: 69fa ldr r2, [r7, #28]
8012562: 429a cmp r2, r3
8012564: d106 bne.n 8012574 <tcp_input+0x31c>
8012566: 4b87 ldr r3, [pc, #540] ; (8012784 <tcp_input+0x52c>)
8012568: f240 120d movw r2, #269 ; 0x10d
801256c: 4986 ldr r1, [pc, #536] ; (8012788 <tcp_input+0x530>)
801256e: 4887 ldr r0, [pc, #540] ; (801278c <tcp_input+0x534>)
8012570: f008 fd50 bl 801b014 <iprintf>
if (prev != NULL) {
8012574: 69bb ldr r3, [r7, #24]
8012576: 2b00 cmp r3, #0
8012578: d00a beq.n 8012590 <tcp_input+0x338>
prev->next = pcb->next;
801257a: 69fb ldr r3, [r7, #28]
801257c: 68da ldr r2, [r3, #12]
801257e: 69bb ldr r3, [r7, #24]
8012580: 60da str r2, [r3, #12]
pcb->next = tcp_active_pcbs;
8012582: 4b83 ldr r3, [pc, #524] ; (8012790 <tcp_input+0x538>)
8012584: 681a ldr r2, [r3, #0]
8012586: 69fb ldr r3, [r7, #28]
8012588: 60da str r2, [r3, #12]
tcp_active_pcbs = pcb;
801258a: 4a81 ldr r2, [pc, #516] ; (8012790 <tcp_input+0x538>)
801258c: 69fb ldr r3, [r7, #28]
801258e: 6013 str r3, [r2, #0]
} else {
TCP_STATS_INC(tcp.cachehit);
}
LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
8012590: 69fb ldr r3, [r7, #28]
8012592: 68db ldr r3, [r3, #12]
8012594: 69fa ldr r2, [r7, #28]
8012596: 429a cmp r2, r3
8012598: d111 bne.n 80125be <tcp_input+0x366>
801259a: 4b7a ldr r3, [pc, #488] ; (8012784 <tcp_input+0x52c>)
801259c: f240 1215 movw r2, #277 ; 0x115
80125a0: 497c ldr r1, [pc, #496] ; (8012794 <tcp_input+0x53c>)
80125a2: 487a ldr r0, [pc, #488] ; (801278c <tcp_input+0x534>)
80125a4: f008 fd36 bl 801b014 <iprintf>
break;
80125a8: e009 b.n 80125be <tcp_input+0x366>
}
prev = pcb;
80125aa: 69fb ldr r3, [r7, #28]
80125ac: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
80125ae: 69fb ldr r3, [r7, #28]
80125b0: 68db ldr r3, [r3, #12]
80125b2: 61fb str r3, [r7, #28]
80125b4: 69fb ldr r3, [r7, #28]
80125b6: 2b00 cmp r3, #0
80125b8: f47f af5e bne.w 8012478 <tcp_input+0x220>
80125bc: e000 b.n 80125c0 <tcp_input+0x368>
break;
80125be: bf00 nop
}
if (pcb == NULL) {
80125c0: 69fb ldr r3, [r7, #28]
80125c2: 2b00 cmp r3, #0
80125c4: f040 8095 bne.w 80126f2 <tcp_input+0x49a>
/* If it did not go to an active connection, we check the connections
in the TIME-WAIT state. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
80125c8: 4b73 ldr r3, [pc, #460] ; (8012798 <tcp_input+0x540>)
80125ca: 681b ldr r3, [r3, #0]
80125cc: 61fb str r3, [r7, #28]
80125ce: e03f b.n 8012650 <tcp_input+0x3f8>
LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
80125d0: 69fb ldr r3, [r7, #28]
80125d2: 7d1b ldrb r3, [r3, #20]
80125d4: 2b0a cmp r3, #10
80125d6: d006 beq.n 80125e6 <tcp_input+0x38e>
80125d8: 4b6a ldr r3, [pc, #424] ; (8012784 <tcp_input+0x52c>)
80125da: f240 121f movw r2, #287 ; 0x11f
80125de: 496f ldr r1, [pc, #444] ; (801279c <tcp_input+0x544>)
80125e0: 486a ldr r0, [pc, #424] ; (801278c <tcp_input+0x534>)
80125e2: f008 fd17 bl 801b014 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80125e6: 69fb ldr r3, [r7, #28]
80125e8: 7a1b ldrb r3, [r3, #8]
80125ea: 2b00 cmp r3, #0
80125ec: d009 beq.n 8012602 <tcp_input+0x3aa>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80125ee: 69fb ldr r3, [r7, #28]
80125f0: 7a1a ldrb r2, [r3, #8]
80125f2: 4b63 ldr r3, [pc, #396] ; (8012780 <tcp_input+0x528>)
80125f4: 685b ldr r3, [r3, #4]
80125f6: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80125fa: 3301 adds r3, #1
80125fc: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80125fe: 429a cmp r2, r3
8012600: d122 bne.n 8012648 <tcp_input+0x3f0>
continue;
}
if (pcb->remote_port == tcphdr->src &&
8012602: 69fb ldr r3, [r7, #28]
8012604: 8b1a ldrh r2, [r3, #24]
8012606: 4b5d ldr r3, [pc, #372] ; (801277c <tcp_input+0x524>)
8012608: 681b ldr r3, [r3, #0]
801260a: 881b ldrh r3, [r3, #0]
801260c: b29b uxth r3, r3
801260e: 429a cmp r2, r3
8012610: d11b bne.n 801264a <tcp_input+0x3f2>
pcb->local_port == tcphdr->dest &&
8012612: 69fb ldr r3, [r7, #28]
8012614: 8ada ldrh r2, [r3, #22]
8012616: 4b59 ldr r3, [pc, #356] ; (801277c <tcp_input+0x524>)
8012618: 681b ldr r3, [r3, #0]
801261a: 885b ldrh r3, [r3, #2]
801261c: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
801261e: 429a cmp r2, r3
8012620: d113 bne.n 801264a <tcp_input+0x3f2>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012622: 69fb ldr r3, [r7, #28]
8012624: 685a ldr r2, [r3, #4]
8012626: 4b56 ldr r3, [pc, #344] ; (8012780 <tcp_input+0x528>)
8012628: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
801262a: 429a cmp r2, r3
801262c: d10d bne.n 801264a <tcp_input+0x3f2>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
801262e: 69fb ldr r3, [r7, #28]
8012630: 681a ldr r2, [r3, #0]
8012632: 4b53 ldr r3, [pc, #332] ; (8012780 <tcp_input+0x528>)
8012634: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012636: 429a cmp r2, r3
8012638: d107 bne.n 801264a <tcp_input+0x3f2>
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_timewait_input(pcb);
801263a: 69f8 ldr r0, [r7, #28]
801263c: f000 fb52 bl 8012ce4 <tcp_timewait_input>
}
pbuf_free(p);
8012640: 6878 ldr r0, [r7, #4]
8012642: f7fd ffd1 bl 80105e8 <pbuf_free>
return;
8012646: e1ee b.n 8012a26 <tcp_input+0x7ce>
continue;
8012648: bf00 nop
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
801264a: 69fb ldr r3, [r7, #28]
801264c: 68db ldr r3, [r3, #12]
801264e: 61fb str r3, [r7, #28]
8012650: 69fb ldr r3, [r7, #28]
8012652: 2b00 cmp r3, #0
8012654: d1bc bne.n 80125d0 <tcp_input+0x378>
}
}
/* Finally, if we still did not get a match, we check all PCBs that
are LISTENing for incoming connections. */
prev = NULL;
8012656: 2300 movs r3, #0
8012658: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
801265a: 4b51 ldr r3, [pc, #324] ; (80127a0 <tcp_input+0x548>)
801265c: 681b ldr r3, [r3, #0]
801265e: 617b str r3, [r7, #20]
8012660: e02a b.n 80126b8 <tcp_input+0x460>
/* check if PCB is bound to specific netif */
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
8012662: 697b ldr r3, [r7, #20]
8012664: 7a1b ldrb r3, [r3, #8]
8012666: 2b00 cmp r3, #0
8012668: d00c beq.n 8012684 <tcp_input+0x42c>
(lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
801266a: 697b ldr r3, [r7, #20]
801266c: 7a1a ldrb r2, [r3, #8]
801266e: 4b44 ldr r3, [pc, #272] ; (8012780 <tcp_input+0x528>)
8012670: 685b ldr r3, [r3, #4]
8012672: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
8012676: 3301 adds r3, #1
8012678: b2db uxtb r3, r3
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
801267a: 429a cmp r2, r3
801267c: d002 beq.n 8012684 <tcp_input+0x42c>
prev = (struct tcp_pcb *)lpcb;
801267e: 697b ldr r3, [r7, #20]
8012680: 61bb str r3, [r7, #24]
continue;
8012682: e016 b.n 80126b2 <tcp_input+0x45a>
}
if (lpcb->local_port == tcphdr->dest) {
8012684: 697b ldr r3, [r7, #20]
8012686: 8ada ldrh r2, [r3, #22]
8012688: 4b3c ldr r3, [pc, #240] ; (801277c <tcp_input+0x524>)
801268a: 681b ldr r3, [r3, #0]
801268c: 885b ldrh r3, [r3, #2]
801268e: b29b uxth r3, r3
8012690: 429a cmp r2, r3
8012692: d10c bne.n 80126ae <tcp_input+0x456>
lpcb_prev = prev;
#else /* SO_REUSE */
break;
#endif /* SO_REUSE */
} else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
8012694: 697b ldr r3, [r7, #20]
8012696: 681a ldr r2, [r3, #0]
8012698: 4b39 ldr r3, [pc, #228] ; (8012780 <tcp_input+0x528>)
801269a: 695b ldr r3, [r3, #20]
801269c: 429a cmp r2, r3
801269e: d00f beq.n 80126c0 <tcp_input+0x468>
/* found an exact match */
break;
} else if (ip_addr_isany(&lpcb->local_ip)) {
80126a0: 697b ldr r3, [r7, #20]
80126a2: 2b00 cmp r3, #0
80126a4: d00d beq.n 80126c2 <tcp_input+0x46a>
80126a6: 697b ldr r3, [r7, #20]
80126a8: 681b ldr r3, [r3, #0]
80126aa: 2b00 cmp r3, #0
80126ac: d009 beq.n 80126c2 <tcp_input+0x46a>
break;
#endif /* SO_REUSE */
}
}
}
prev = (struct tcp_pcb *)lpcb;
80126ae: 697b ldr r3, [r7, #20]
80126b0: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
80126b2: 697b ldr r3, [r7, #20]
80126b4: 68db ldr r3, [r3, #12]
80126b6: 617b str r3, [r7, #20]
80126b8: 697b ldr r3, [r7, #20]
80126ba: 2b00 cmp r3, #0
80126bc: d1d1 bne.n 8012662 <tcp_input+0x40a>
80126be: e000 b.n 80126c2 <tcp_input+0x46a>
break;
80126c0: bf00 nop
/* only pass to ANY if no specific local IP has been found */
lpcb = lpcb_any;
prev = lpcb_prev;
}
#endif /* SO_REUSE */
if (lpcb != NULL) {
80126c2: 697b ldr r3, [r7, #20]
80126c4: 2b00 cmp r3, #0
80126c6: d014 beq.n 80126f2 <tcp_input+0x49a>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
if (prev != NULL) {
80126c8: 69bb ldr r3, [r7, #24]
80126ca: 2b00 cmp r3, #0
80126cc: d00a beq.n 80126e4 <tcp_input+0x48c>
((struct tcp_pcb_listen *)prev)->next = lpcb->next;
80126ce: 697b ldr r3, [r7, #20]
80126d0: 68da ldr r2, [r3, #12]
80126d2: 69bb ldr r3, [r7, #24]
80126d4: 60da str r2, [r3, #12]
/* our successor is the remainder of the listening list */
lpcb->next = tcp_listen_pcbs.listen_pcbs;
80126d6: 4b32 ldr r3, [pc, #200] ; (80127a0 <tcp_input+0x548>)
80126d8: 681a ldr r2, [r3, #0]
80126da: 697b ldr r3, [r7, #20]
80126dc: 60da str r2, [r3, #12]
/* put this listening pcb at the head of the listening list */
tcp_listen_pcbs.listen_pcbs = lpcb;
80126de: 4a30 ldr r2, [pc, #192] ; (80127a0 <tcp_input+0x548>)
80126e0: 697b ldr r3, [r7, #20]
80126e2: 6013 str r3, [r2, #0]
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_listen_input(lpcb);
80126e4: 6978 ldr r0, [r7, #20]
80126e6: f000 f9ff bl 8012ae8 <tcp_listen_input>
}
pbuf_free(p);
80126ea: 6878 ldr r0, [r7, #4]
80126ec: f7fd ff7c bl 80105e8 <pbuf_free>
return;
80126f0: e199 b.n 8012a26 <tcp_input+0x7ce>
tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
pbuf_free(p);
return;
}
#endif
if (pcb != NULL) {
80126f2: 69fb ldr r3, [r7, #28]
80126f4: 2b00 cmp r3, #0
80126f6: f000 8160 beq.w 80129ba <tcp_input+0x762>
#if TCP_INPUT_DEBUG
tcp_debug_print_state(pcb->state);
#endif /* TCP_INPUT_DEBUG */
/* Set up a tcp_seg structure. */
inseg.next = NULL;
80126fa: 4b2a ldr r3, [pc, #168] ; (80127a4 <tcp_input+0x54c>)
80126fc: 2200 movs r2, #0
80126fe: 601a str r2, [r3, #0]
inseg.len = p->tot_len;
8012700: 687b ldr r3, [r7, #4]
8012702: 891a ldrh r2, [r3, #8]
8012704: 4b27 ldr r3, [pc, #156] ; (80127a4 <tcp_input+0x54c>)
8012706: 811a strh r2, [r3, #8]
inseg.p = p;
8012708: 4a26 ldr r2, [pc, #152] ; (80127a4 <tcp_input+0x54c>)
801270a: 687b ldr r3, [r7, #4]
801270c: 6053 str r3, [r2, #4]
inseg.tcphdr = tcphdr;
801270e: 4b1b ldr r3, [pc, #108] ; (801277c <tcp_input+0x524>)
8012710: 681b ldr r3, [r3, #0]
8012712: 4a24 ldr r2, [pc, #144] ; (80127a4 <tcp_input+0x54c>)
8012714: 60d3 str r3, [r2, #12]
recv_data = NULL;
8012716: 4b24 ldr r3, [pc, #144] ; (80127a8 <tcp_input+0x550>)
8012718: 2200 movs r2, #0
801271a: 601a str r2, [r3, #0]
recv_flags = 0;
801271c: 4b23 ldr r3, [pc, #140] ; (80127ac <tcp_input+0x554>)
801271e: 2200 movs r2, #0
8012720: 701a strb r2, [r3, #0]
recv_acked = 0;
8012722: 4b23 ldr r3, [pc, #140] ; (80127b0 <tcp_input+0x558>)
8012724: 2200 movs r2, #0
8012726: 801a strh r2, [r3, #0]
if (flags & TCP_PSH) {
8012728: 4b22 ldr r3, [pc, #136] ; (80127b4 <tcp_input+0x55c>)
801272a: 781b ldrb r3, [r3, #0]
801272c: f003 0308 and.w r3, r3, #8
8012730: 2b00 cmp r3, #0
8012732: d006 beq.n 8012742 <tcp_input+0x4ea>
p->flags |= PBUF_FLAG_PUSH;
8012734: 687b ldr r3, [r7, #4]
8012736: 7b5b ldrb r3, [r3, #13]
8012738: f043 0301 orr.w r3, r3, #1
801273c: b2da uxtb r2, r3
801273e: 687b ldr r3, [r7, #4]
8012740: 735a strb r2, [r3, #13]
}
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
8012742: 69fb ldr r3, [r7, #28]
8012744: 6f9b ldr r3, [r3, #120] ; 0x78
8012746: 2b00 cmp r3, #0
8012748: d038 beq.n 80127bc <tcp_input+0x564>
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
801274a: 69f8 ldr r0, [r7, #28]
801274c: f7ff f940 bl 80119d0 <tcp_process_refused_data>
8012750: 4603 mov r3, r0
8012752: f113 0f0d cmn.w r3, #13
8012756: d007 beq.n 8012768 <tcp_input+0x510>
((pcb->refused_data != NULL) && (tcplen > 0))) {
8012758: 69fb ldr r3, [r7, #28]
801275a: 6f9b ldr r3, [r3, #120] ; 0x78
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
801275c: 2b00 cmp r3, #0
801275e: d02d beq.n 80127bc <tcp_input+0x564>
((pcb->refused_data != NULL) && (tcplen > 0))) {
8012760: 4b15 ldr r3, [pc, #84] ; (80127b8 <tcp_input+0x560>)
8012762: 881b ldrh r3, [r3, #0]
8012764: 2b00 cmp r3, #0
8012766: d029 beq.n 80127bc <tcp_input+0x564>
/* pcb has been aborted or refused data is still refused and the new
segment contains data */
if (pcb->rcv_ann_wnd == 0) {
8012768: 69fb ldr r3, [r7, #28]
801276a: 8d5b ldrh r3, [r3, #42] ; 0x2a
801276c: 2b00 cmp r3, #0
801276e: f040 8104 bne.w 801297a <tcp_input+0x722>
/* this is a zero-window probe, we respond to it with current RCV.NXT
and drop the data segment */
tcp_send_empty_ack(pcb);
8012772: 69f8 ldr r0, [r7, #28]
8012774: f003 f9ce bl 8015b14 <tcp_send_empty_ack>
}
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
goto aborted;
8012778: e0ff b.n 801297a <tcp_input+0x722>
801277a: bf00 nop
801277c: 2000873c .word 0x2000873c
8012780: 2000be8c .word 0x2000be8c
8012784: 0801d2b0 .word 0x0801d2b0
8012788: 0801d3dc .word 0x0801d3dc
801278c: 0801d2fc .word 0x0801d2fc
8012790: 2000f5c0 .word 0x2000f5c0
8012794: 0801d408 .word 0x0801d408
8012798: 2000f5d0 .word 0x2000f5d0
801279c: 0801d434 .word 0x0801d434
80127a0: 2000f5c8 .word 0x2000f5c8
80127a4: 2000872c .word 0x2000872c
80127a8: 2000875c .word 0x2000875c
80127ac: 20008759 .word 0x20008759
80127b0: 20008754 .word 0x20008754
80127b4: 20008758 .word 0x20008758
80127b8: 20008756 .word 0x20008756
}
}
tcp_input_pcb = pcb;
80127bc: 4a9b ldr r2, [pc, #620] ; (8012a2c <tcp_input+0x7d4>)
80127be: 69fb ldr r3, [r7, #28]
80127c0: 6013 str r3, [r2, #0]
err = tcp_process(pcb);
80127c2: 69f8 ldr r0, [r7, #28]
80127c4: f000 fb0a bl 8012ddc <tcp_process>
80127c8: 4603 mov r3, r0
80127ca: 74fb strb r3, [r7, #19]
/* A return value of ERR_ABRT means that tcp_abort() was called
and that the pcb has been freed. If so, we don't do anything. */
if (err != ERR_ABRT) {
80127cc: f997 3013 ldrsb.w r3, [r7, #19]
80127d0: f113 0f0d cmn.w r3, #13
80127d4: f000 80d3 beq.w 801297e <tcp_input+0x726>
if (recv_flags & TF_RESET) {
80127d8: 4b95 ldr r3, [pc, #596] ; (8012a30 <tcp_input+0x7d8>)
80127da: 781b ldrb r3, [r3, #0]
80127dc: f003 0308 and.w r3, r3, #8
80127e0: 2b00 cmp r3, #0
80127e2: d015 beq.n 8012810 <tcp_input+0x5b8>
/* TF_RESET means that the connection was reset by the other
end. We then call the error callback to inform the
application that the connection is dead before we
deallocate the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
80127e4: 69fb ldr r3, [r7, #28]
80127e6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80127ea: 2b00 cmp r3, #0
80127ec: d008 beq.n 8012800 <tcp_input+0x5a8>
80127ee: 69fb ldr r3, [r7, #28]
80127f0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80127f4: 69fa ldr r2, [r7, #28]
80127f6: 6912 ldr r2, [r2, #16]
80127f8: f06f 010d mvn.w r1, #13
80127fc: 4610 mov r0, r2
80127fe: 4798 blx r3
tcp_pcb_remove(&tcp_active_pcbs, pcb);
8012800: 69f9 ldr r1, [r7, #28]
8012802: 488c ldr r0, [pc, #560] ; (8012a34 <tcp_input+0x7dc>)
8012804: f7ff fbb0 bl 8011f68 <tcp_pcb_remove>
tcp_free(pcb);
8012808: 69f8 ldr r0, [r7, #28]
801280a: f7fe f9a9 bl 8010b60 <tcp_free>
801280e: e0c1 b.n 8012994 <tcp_input+0x73c>
} else {
err = ERR_OK;
8012810: 2300 movs r3, #0
8012812: 74fb strb r3, [r7, #19]
/* If the application has registered a "sent" function to be
called when new send buffer space is available, we call it
now. */
if (recv_acked > 0) {
8012814: 4b88 ldr r3, [pc, #544] ; (8012a38 <tcp_input+0x7e0>)
8012816: 881b ldrh r3, [r3, #0]
8012818: 2b00 cmp r3, #0
801281a: d01d beq.n 8012858 <tcp_input+0x600>
while (acked > 0) {
acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
acked -= acked16;
#else
{
acked16 = recv_acked;
801281c: 4b86 ldr r3, [pc, #536] ; (8012a38 <tcp_input+0x7e0>)
801281e: 881b ldrh r3, [r3, #0]
8012820: 81fb strh r3, [r7, #14]
#endif
TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
8012822: 69fb ldr r3, [r7, #28]
8012824: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8012828: 2b00 cmp r3, #0
801282a: d00a beq.n 8012842 <tcp_input+0x5ea>
801282c: 69fb ldr r3, [r7, #28]
801282e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8012832: 69fa ldr r2, [r7, #28]
8012834: 6910 ldr r0, [r2, #16]
8012836: 89fa ldrh r2, [r7, #14]
8012838: 69f9 ldr r1, [r7, #28]
801283a: 4798 blx r3
801283c: 4603 mov r3, r0
801283e: 74fb strb r3, [r7, #19]
8012840: e001 b.n 8012846 <tcp_input+0x5ee>
8012842: 2300 movs r3, #0
8012844: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012846: f997 3013 ldrsb.w r3, [r7, #19]
801284a: f113 0f0d cmn.w r3, #13
801284e: f000 8098 beq.w 8012982 <tcp_input+0x72a>
goto aborted;
}
}
recv_acked = 0;
8012852: 4b79 ldr r3, [pc, #484] ; (8012a38 <tcp_input+0x7e0>)
8012854: 2200 movs r2, #0
8012856: 801a strh r2, [r3, #0]
}
if (tcp_input_delayed_close(pcb)) {
8012858: 69f8 ldr r0, [r7, #28]
801285a: f000 f905 bl 8012a68 <tcp_input_delayed_close>
801285e: 4603 mov r3, r0
8012860: 2b00 cmp r3, #0
8012862: f040 8090 bne.w 8012986 <tcp_input+0x72e>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (recv_data != NULL) {
struct pbuf *rest = NULL;
pbuf_split_64k(recv_data, &rest);
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
if (recv_data != NULL) {
8012866: 4b75 ldr r3, [pc, #468] ; (8012a3c <tcp_input+0x7e4>)
8012868: 681b ldr r3, [r3, #0]
801286a: 2b00 cmp r3, #0
801286c: d041 beq.n 80128f2 <tcp_input+0x69a>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
801286e: 69fb ldr r3, [r7, #28]
8012870: 6f9b ldr r3, [r3, #120] ; 0x78
8012872: 2b00 cmp r3, #0
8012874: d006 beq.n 8012884 <tcp_input+0x62c>
8012876: 4b72 ldr r3, [pc, #456] ; (8012a40 <tcp_input+0x7e8>)
8012878: f44f 72f3 mov.w r2, #486 ; 0x1e6
801287c: 4971 ldr r1, [pc, #452] ; (8012a44 <tcp_input+0x7ec>)
801287e: 4872 ldr r0, [pc, #456] ; (8012a48 <tcp_input+0x7f0>)
8012880: f008 fbc8 bl 801b014 <iprintf>
if (pcb->flags & TF_RXCLOSED) {
8012884: 69fb ldr r3, [r7, #28]
8012886: 8b5b ldrh r3, [r3, #26]
8012888: f003 0310 and.w r3, r3, #16
801288c: 2b00 cmp r3, #0
801288e: d008 beq.n 80128a2 <tcp_input+0x64a>
/* received data although already closed -> abort (send RST) to
notify the remote host that not all data has been processed */
pbuf_free(recv_data);
8012890: 4b6a ldr r3, [pc, #424] ; (8012a3c <tcp_input+0x7e4>)
8012892: 681b ldr r3, [r3, #0]
8012894: 4618 mov r0, r3
8012896: f7fd fea7 bl 80105e8 <pbuf_free>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_free(rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
tcp_abort(pcb);
801289a: 69f8 ldr r0, [r7, #28]
801289c: f7fe fc40 bl 8011120 <tcp_abort>
goto aborted;
80128a0: e078 b.n 8012994 <tcp_input+0x73c>
}
/* Notify application that data has been received. */
TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
80128a2: 69fb ldr r3, [r7, #28]
80128a4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80128a8: 2b00 cmp r3, #0
80128aa: d00c beq.n 80128c6 <tcp_input+0x66e>
80128ac: 69fb ldr r3, [r7, #28]
80128ae: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
80128b2: 69fb ldr r3, [r7, #28]
80128b4: 6918 ldr r0, [r3, #16]
80128b6: 4b61 ldr r3, [pc, #388] ; (8012a3c <tcp_input+0x7e4>)
80128b8: 681a ldr r2, [r3, #0]
80128ba: 2300 movs r3, #0
80128bc: 69f9 ldr r1, [r7, #28]
80128be: 47a0 blx r4
80128c0: 4603 mov r3, r0
80128c2: 74fb strb r3, [r7, #19]
80128c4: e008 b.n 80128d8 <tcp_input+0x680>
80128c6: 4b5d ldr r3, [pc, #372] ; (8012a3c <tcp_input+0x7e4>)
80128c8: 681a ldr r2, [r3, #0]
80128ca: 2300 movs r3, #0
80128cc: 69f9 ldr r1, [r7, #28]
80128ce: 2000 movs r0, #0
80128d0: f7ff f952 bl 8011b78 <tcp_recv_null>
80128d4: 4603 mov r3, r0
80128d6: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
80128d8: f997 3013 ldrsb.w r3, [r7, #19]
80128dc: f113 0f0d cmn.w r3, #13
80128e0: d053 beq.n 801298a <tcp_input+0x732>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
goto aborted;
}
/* If the upper layer can't receive this data, store it */
if (err != ERR_OK) {
80128e2: f997 3013 ldrsb.w r3, [r7, #19]
80128e6: 2b00 cmp r3, #0
80128e8: d003 beq.n 80128f2 <tcp_input+0x69a>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(recv_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = recv_data;
80128ea: 4b54 ldr r3, [pc, #336] ; (8012a3c <tcp_input+0x7e4>)
80128ec: 681a ldr r2, [r3, #0]
80128ee: 69fb ldr r3, [r7, #28]
80128f0: 679a str r2, [r3, #120] ; 0x78
}
}
/* If a FIN segment was received, we call the callback
function with a NULL buffer to indicate EOF. */
if (recv_flags & TF_GOT_FIN) {
80128f2: 4b4f ldr r3, [pc, #316] ; (8012a30 <tcp_input+0x7d8>)
80128f4: 781b ldrb r3, [r3, #0]
80128f6: f003 0320 and.w r3, r3, #32
80128fa: 2b00 cmp r3, #0
80128fc: d030 beq.n 8012960 <tcp_input+0x708>
if (pcb->refused_data != NULL) {
80128fe: 69fb ldr r3, [r7, #28]
8012900: 6f9b ldr r3, [r3, #120] ; 0x78
8012902: 2b00 cmp r3, #0
8012904: d009 beq.n 801291a <tcp_input+0x6c2>
/* Delay this if we have refused data. */
pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
8012906: 69fb ldr r3, [r7, #28]
8012908: 6f9b ldr r3, [r3, #120] ; 0x78
801290a: 7b5a ldrb r2, [r3, #13]
801290c: 69fb ldr r3, [r7, #28]
801290e: 6f9b ldr r3, [r3, #120] ; 0x78
8012910: f042 0220 orr.w r2, r2, #32
8012914: b2d2 uxtb r2, r2
8012916: 735a strb r2, [r3, #13]
8012918: e022 b.n 8012960 <tcp_input+0x708>
} else {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
801291a: 69fb ldr r3, [r7, #28]
801291c: 8d1b ldrh r3, [r3, #40] ; 0x28
801291e: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8012922: d005 beq.n 8012930 <tcp_input+0x6d8>
pcb->rcv_wnd++;
8012924: 69fb ldr r3, [r7, #28]
8012926: 8d1b ldrh r3, [r3, #40] ; 0x28
8012928: 3301 adds r3, #1
801292a: b29a uxth r2, r3
801292c: 69fb ldr r3, [r7, #28]
801292e: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
8012930: 69fb ldr r3, [r7, #28]
8012932: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8012936: 2b00 cmp r3, #0
8012938: d00b beq.n 8012952 <tcp_input+0x6fa>
801293a: 69fb ldr r3, [r7, #28]
801293c: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8012940: 69fb ldr r3, [r7, #28]
8012942: 6918 ldr r0, [r3, #16]
8012944: 2300 movs r3, #0
8012946: 2200 movs r2, #0
8012948: 69f9 ldr r1, [r7, #28]
801294a: 47a0 blx r4
801294c: 4603 mov r3, r0
801294e: 74fb strb r3, [r7, #19]
8012950: e001 b.n 8012956 <tcp_input+0x6fe>
8012952: 2300 movs r3, #0
8012954: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012956: f997 3013 ldrsb.w r3, [r7, #19]
801295a: f113 0f0d cmn.w r3, #13
801295e: d016 beq.n 801298e <tcp_input+0x736>
goto aborted;
}
}
}
tcp_input_pcb = NULL;
8012960: 4b32 ldr r3, [pc, #200] ; (8012a2c <tcp_input+0x7d4>)
8012962: 2200 movs r2, #0
8012964: 601a str r2, [r3, #0]
if (tcp_input_delayed_close(pcb)) {
8012966: 69f8 ldr r0, [r7, #28]
8012968: f000 f87e bl 8012a68 <tcp_input_delayed_close>
801296c: 4603 mov r3, r0
801296e: 2b00 cmp r3, #0
8012970: d10f bne.n 8012992 <tcp_input+0x73a>
goto aborted;
}
/* Try to send something out. */
tcp_output(pcb);
8012972: 69f8 ldr r0, [r7, #28]
8012974: f002 fab6 bl 8014ee4 <tcp_output>
8012978: e00c b.n 8012994 <tcp_input+0x73c>
goto aborted;
801297a: bf00 nop
801297c: e00a b.n 8012994 <tcp_input+0x73c>
#endif /* TCP_INPUT_DEBUG */
}
}
/* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
Below this line, 'pcb' may not be dereferenced! */
aborted:
801297e: bf00 nop
8012980: e008 b.n 8012994 <tcp_input+0x73c>
goto aborted;
8012982: bf00 nop
8012984: e006 b.n 8012994 <tcp_input+0x73c>
goto aborted;
8012986: bf00 nop
8012988: e004 b.n 8012994 <tcp_input+0x73c>
goto aborted;
801298a: bf00 nop
801298c: e002 b.n 8012994 <tcp_input+0x73c>
goto aborted;
801298e: bf00 nop
8012990: e000 b.n 8012994 <tcp_input+0x73c>
goto aborted;
8012992: bf00 nop
tcp_input_pcb = NULL;
8012994: 4b25 ldr r3, [pc, #148] ; (8012a2c <tcp_input+0x7d4>)
8012996: 2200 movs r2, #0
8012998: 601a str r2, [r3, #0]
recv_data = NULL;
801299a: 4b28 ldr r3, [pc, #160] ; (8012a3c <tcp_input+0x7e4>)
801299c: 2200 movs r2, #0
801299e: 601a str r2, [r3, #0]
/* give up our reference to inseg.p */
if (inseg.p != NULL) {
80129a0: 4b2a ldr r3, [pc, #168] ; (8012a4c <tcp_input+0x7f4>)
80129a2: 685b ldr r3, [r3, #4]
80129a4: 2b00 cmp r3, #0
80129a6: d03d beq.n 8012a24 <tcp_input+0x7cc>
pbuf_free(inseg.p);
80129a8: 4b28 ldr r3, [pc, #160] ; (8012a4c <tcp_input+0x7f4>)
80129aa: 685b ldr r3, [r3, #4]
80129ac: 4618 mov r0, r3
80129ae: f7fd fe1b bl 80105e8 <pbuf_free>
inseg.p = NULL;
80129b2: 4b26 ldr r3, [pc, #152] ; (8012a4c <tcp_input+0x7f4>)
80129b4: 2200 movs r2, #0
80129b6: 605a str r2, [r3, #4]
pbuf_free(p);
}
LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
PERF_STOP("tcp_input");
return;
80129b8: e034 b.n 8012a24 <tcp_input+0x7cc>
if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
80129ba: 4b25 ldr r3, [pc, #148] ; (8012a50 <tcp_input+0x7f8>)
80129bc: 681b ldr r3, [r3, #0]
80129be: 899b ldrh r3, [r3, #12]
80129c0: b29b uxth r3, r3
80129c2: 4618 mov r0, r3
80129c4: f7fc fa5c bl 800ee80 <lwip_htons>
80129c8: 4603 mov r3, r0
80129ca: b2db uxtb r3, r3
80129cc: f003 0304 and.w r3, r3, #4
80129d0: 2b00 cmp r3, #0
80129d2: d118 bne.n 8012a06 <tcp_input+0x7ae>
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129d4: 4b1f ldr r3, [pc, #124] ; (8012a54 <tcp_input+0x7fc>)
80129d6: 6819 ldr r1, [r3, #0]
80129d8: 4b1f ldr r3, [pc, #124] ; (8012a58 <tcp_input+0x800>)
80129da: 881b ldrh r3, [r3, #0]
80129dc: 461a mov r2, r3
80129de: 4b1f ldr r3, [pc, #124] ; (8012a5c <tcp_input+0x804>)
80129e0: 681b ldr r3, [r3, #0]
80129e2: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129e4: 4b1a ldr r3, [pc, #104] ; (8012a50 <tcp_input+0x7f8>)
80129e6: 681b ldr r3, [r3, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129e8: 885b ldrh r3, [r3, #2]
80129ea: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129ec: 4a18 ldr r2, [pc, #96] ; (8012a50 <tcp_input+0x7f8>)
80129ee: 6812 ldr r2, [r2, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129f0: 8812 ldrh r2, [r2, #0]
80129f2: b292 uxth r2, r2
80129f4: 9202 str r2, [sp, #8]
80129f6: 9301 str r3, [sp, #4]
80129f8: 4b19 ldr r3, [pc, #100] ; (8012a60 <tcp_input+0x808>)
80129fa: 9300 str r3, [sp, #0]
80129fc: 4b19 ldr r3, [pc, #100] ; (8012a64 <tcp_input+0x80c>)
80129fe: 4602 mov r2, r0
8012a00: 2000 movs r0, #0
8012a02: f003 f835 bl 8015a70 <tcp_rst>
pbuf_free(p);
8012a06: 6878 ldr r0, [r7, #4]
8012a08: f7fd fdee bl 80105e8 <pbuf_free>
return;
8012a0c: e00a b.n 8012a24 <tcp_input+0x7cc>
goto dropped;
8012a0e: bf00 nop
8012a10: e004 b.n 8012a1c <tcp_input+0x7c4>
dropped:
8012a12: bf00 nop
8012a14: e002 b.n 8012a1c <tcp_input+0x7c4>
goto dropped;
8012a16: bf00 nop
8012a18: e000 b.n 8012a1c <tcp_input+0x7c4>
goto dropped;
8012a1a: bf00 nop
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
pbuf_free(p);
8012a1c: 6878 ldr r0, [r7, #4]
8012a1e: f7fd fde3 bl 80105e8 <pbuf_free>
8012a22: e000 b.n 8012a26 <tcp_input+0x7ce>
return;
8012a24: bf00 nop
}
8012a26: 3724 adds r7, #36 ; 0x24
8012a28: 46bd mov sp, r7
8012a2a: bd90 pop {r4, r7, pc}
8012a2c: 2000f5d4 .word 0x2000f5d4
8012a30: 20008759 .word 0x20008759
8012a34: 2000f5c0 .word 0x2000f5c0
8012a38: 20008754 .word 0x20008754
8012a3c: 2000875c .word 0x2000875c
8012a40: 0801d2b0 .word 0x0801d2b0
8012a44: 0801d464 .word 0x0801d464
8012a48: 0801d2fc .word 0x0801d2fc
8012a4c: 2000872c .word 0x2000872c
8012a50: 2000873c .word 0x2000873c
8012a54: 20008750 .word 0x20008750
8012a58: 20008756 .word 0x20008756
8012a5c: 2000874c .word 0x2000874c
8012a60: 2000be9c .word 0x2000be9c
8012a64: 2000bea0 .word 0x2000bea0
08012a68 <tcp_input_delayed_close>:
* any more.
* @returns 1 if the pcb has been closed and deallocated, 0 otherwise
*/
static int
tcp_input_delayed_close(struct tcp_pcb *pcb)
{
8012a68: b580 push {r7, lr}
8012a6a: b082 sub sp, #8
8012a6c: af00 add r7, sp, #0
8012a6e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
8012a70: 687b ldr r3, [r7, #4]
8012a72: 2b00 cmp r3, #0
8012a74: d106 bne.n 8012a84 <tcp_input_delayed_close+0x1c>
8012a76: 4b17 ldr r3, [pc, #92] ; (8012ad4 <tcp_input_delayed_close+0x6c>)
8012a78: f240 225a movw r2, #602 ; 0x25a
8012a7c: 4916 ldr r1, [pc, #88] ; (8012ad8 <tcp_input_delayed_close+0x70>)
8012a7e: 4817 ldr r0, [pc, #92] ; (8012adc <tcp_input_delayed_close+0x74>)
8012a80: f008 fac8 bl 801b014 <iprintf>
if (recv_flags & TF_CLOSED) {
8012a84: 4b16 ldr r3, [pc, #88] ; (8012ae0 <tcp_input_delayed_close+0x78>)
8012a86: 781b ldrb r3, [r3, #0]
8012a88: f003 0310 and.w r3, r3, #16
8012a8c: 2b00 cmp r3, #0
8012a8e: d01c beq.n 8012aca <tcp_input_delayed_close+0x62>
/* The connection has been closed and we will deallocate the
PCB. */
if (!(pcb->flags & TF_RXCLOSED)) {
8012a90: 687b ldr r3, [r7, #4]
8012a92: 8b5b ldrh r3, [r3, #26]
8012a94: f003 0310 and.w r3, r3, #16
8012a98: 2b00 cmp r3, #0
8012a9a: d10d bne.n 8012ab8 <tcp_input_delayed_close+0x50>
/* Connection closed although the application has only shut down the
tx side: call the PCB's err callback and indicate the closure to
ensure the application doesn't continue using the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
8012a9c: 687b ldr r3, [r7, #4]
8012a9e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012aa2: 2b00 cmp r3, #0
8012aa4: d008 beq.n 8012ab8 <tcp_input_delayed_close+0x50>
8012aa6: 687b ldr r3, [r7, #4]
8012aa8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012aac: 687a ldr r2, [r7, #4]
8012aae: 6912 ldr r2, [r2, #16]
8012ab0: f06f 010e mvn.w r1, #14
8012ab4: 4610 mov r0, r2
8012ab6: 4798 blx r3
}
tcp_pcb_remove(&tcp_active_pcbs, pcb);
8012ab8: 6879 ldr r1, [r7, #4]
8012aba: 480a ldr r0, [pc, #40] ; (8012ae4 <tcp_input_delayed_close+0x7c>)
8012abc: f7ff fa54 bl 8011f68 <tcp_pcb_remove>
tcp_free(pcb);
8012ac0: 6878 ldr r0, [r7, #4]
8012ac2: f7fe f84d bl 8010b60 <tcp_free>
return 1;
8012ac6: 2301 movs r3, #1
8012ac8: e000 b.n 8012acc <tcp_input_delayed_close+0x64>
}
return 0;
8012aca: 2300 movs r3, #0
}
8012acc: 4618 mov r0, r3
8012ace: 3708 adds r7, #8
8012ad0: 46bd mov sp, r7
8012ad2: bd80 pop {r7, pc}
8012ad4: 0801d2b0 .word 0x0801d2b0
8012ad8: 0801d480 .word 0x0801d480
8012adc: 0801d2fc .word 0x0801d2fc
8012ae0: 20008759 .word 0x20008759
8012ae4: 2000f5c0 .word 0x2000f5c0
08012ae8 <tcp_listen_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_listen_input(struct tcp_pcb_listen *pcb)
{
8012ae8: b590 push {r4, r7, lr}
8012aea: b08b sub sp, #44 ; 0x2c
8012aec: af04 add r7, sp, #16
8012aee: 6078 str r0, [r7, #4]
struct tcp_pcb *npcb;
u32_t iss;
err_t rc;
if (flags & TCP_RST) {
8012af0: 4b6f ldr r3, [pc, #444] ; (8012cb0 <tcp_listen_input+0x1c8>)
8012af2: 781b ldrb r3, [r3, #0]
8012af4: f003 0304 and.w r3, r3, #4
8012af8: 2b00 cmp r3, #0
8012afa: f040 80d3 bne.w 8012ca4 <tcp_listen_input+0x1bc>
/* An incoming RST should be ignored. Return. */
return;
}
LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
8012afe: 687b ldr r3, [r7, #4]
8012b00: 2b00 cmp r3, #0
8012b02: d106 bne.n 8012b12 <tcp_listen_input+0x2a>
8012b04: 4b6b ldr r3, [pc, #428] ; (8012cb4 <tcp_listen_input+0x1cc>)
8012b06: f240 2281 movw r2, #641 ; 0x281
8012b0a: 496b ldr r1, [pc, #428] ; (8012cb8 <tcp_listen_input+0x1d0>)
8012b0c: 486b ldr r0, [pc, #428] ; (8012cbc <tcp_listen_input+0x1d4>)
8012b0e: f008 fa81 bl 801b014 <iprintf>
/* In the LISTEN state, we check for incoming SYN segments,
creates a new PCB, and responds with a SYN|ACK. */
if (flags & TCP_ACK) {
8012b12: 4b67 ldr r3, [pc, #412] ; (8012cb0 <tcp_listen_input+0x1c8>)
8012b14: 781b ldrb r3, [r3, #0]
8012b16: f003 0310 and.w r3, r3, #16
8012b1a: 2b00 cmp r3, #0
8012b1c: d019 beq.n 8012b52 <tcp_listen_input+0x6a>
/* For incoming segments with the ACK flag set, respond with a
RST. */
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b1e: 4b68 ldr r3, [pc, #416] ; (8012cc0 <tcp_listen_input+0x1d8>)
8012b20: 6819 ldr r1, [r3, #0]
8012b22: 4b68 ldr r3, [pc, #416] ; (8012cc4 <tcp_listen_input+0x1dc>)
8012b24: 881b ldrh r3, [r3, #0]
8012b26: 461a mov r2, r3
8012b28: 4b67 ldr r3, [pc, #412] ; (8012cc8 <tcp_listen_input+0x1e0>)
8012b2a: 681b ldr r3, [r3, #0]
8012b2c: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b2e: 4b67 ldr r3, [pc, #412] ; (8012ccc <tcp_listen_input+0x1e4>)
8012b30: 681b ldr r3, [r3, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b32: 885b ldrh r3, [r3, #2]
8012b34: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b36: 4a65 ldr r2, [pc, #404] ; (8012ccc <tcp_listen_input+0x1e4>)
8012b38: 6812 ldr r2, [r2, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b3a: 8812 ldrh r2, [r2, #0]
8012b3c: b292 uxth r2, r2
8012b3e: 9202 str r2, [sp, #8]
8012b40: 9301 str r3, [sp, #4]
8012b42: 4b63 ldr r3, [pc, #396] ; (8012cd0 <tcp_listen_input+0x1e8>)
8012b44: 9300 str r3, [sp, #0]
8012b46: 4b63 ldr r3, [pc, #396] ; (8012cd4 <tcp_listen_input+0x1ec>)
8012b48: 4602 mov r2, r0
8012b4a: 6878 ldr r0, [r7, #4]
8012b4c: f002 ff90 bl 8015a70 <tcp_rst>
tcp_abandon(npcb, 0);
return;
}
tcp_output(npcb);
}
return;
8012b50: e0aa b.n 8012ca8 <tcp_listen_input+0x1c0>
} else if (flags & TCP_SYN) {
8012b52: 4b57 ldr r3, [pc, #348] ; (8012cb0 <tcp_listen_input+0x1c8>)
8012b54: 781b ldrb r3, [r3, #0]
8012b56: f003 0302 and.w r3, r3, #2
8012b5a: 2b00 cmp r3, #0
8012b5c: f000 80a4 beq.w 8012ca8 <tcp_listen_input+0x1c0>
npcb = tcp_alloc(pcb->prio);
8012b60: 687b ldr r3, [r7, #4]
8012b62: 7d5b ldrb r3, [r3, #21]
8012b64: 4618 mov r0, r3
8012b66: f7ff f92b bl 8011dc0 <tcp_alloc>
8012b6a: 6178 str r0, [r7, #20]
if (npcb == NULL) {
8012b6c: 697b ldr r3, [r7, #20]
8012b6e: 2b00 cmp r3, #0
8012b70: d111 bne.n 8012b96 <tcp_listen_input+0xae>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012b72: 687b ldr r3, [r7, #4]
8012b74: 699b ldr r3, [r3, #24]
8012b76: 2b00 cmp r3, #0
8012b78: d00a beq.n 8012b90 <tcp_listen_input+0xa8>
8012b7a: 687b ldr r3, [r7, #4]
8012b7c: 699b ldr r3, [r3, #24]
8012b7e: 687a ldr r2, [r7, #4]
8012b80: 6910 ldr r0, [r2, #16]
8012b82: f04f 32ff mov.w r2, #4294967295
8012b86: 2100 movs r1, #0
8012b88: 4798 blx r3
8012b8a: 4603 mov r3, r0
8012b8c: 73bb strb r3, [r7, #14]
return;
8012b8e: e08c b.n 8012caa <tcp_listen_input+0x1c2>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012b90: 23f0 movs r3, #240 ; 0xf0
8012b92: 73bb strb r3, [r7, #14]
return;
8012b94: e089 b.n 8012caa <tcp_listen_input+0x1c2>
ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
8012b96: 4b50 ldr r3, [pc, #320] ; (8012cd8 <tcp_listen_input+0x1f0>)
8012b98: 695a ldr r2, [r3, #20]
8012b9a: 697b ldr r3, [r7, #20]
8012b9c: 601a str r2, [r3, #0]
ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
8012b9e: 4b4e ldr r3, [pc, #312] ; (8012cd8 <tcp_listen_input+0x1f0>)
8012ba0: 691a ldr r2, [r3, #16]
8012ba2: 697b ldr r3, [r7, #20]
8012ba4: 605a str r2, [r3, #4]
npcb->local_port = pcb->local_port;
8012ba6: 687b ldr r3, [r7, #4]
8012ba8: 8ada ldrh r2, [r3, #22]
8012baa: 697b ldr r3, [r7, #20]
8012bac: 82da strh r2, [r3, #22]
npcb->remote_port = tcphdr->src;
8012bae: 4b47 ldr r3, [pc, #284] ; (8012ccc <tcp_listen_input+0x1e4>)
8012bb0: 681b ldr r3, [r3, #0]
8012bb2: 881b ldrh r3, [r3, #0]
8012bb4: b29a uxth r2, r3
8012bb6: 697b ldr r3, [r7, #20]
8012bb8: 831a strh r2, [r3, #24]
npcb->state = SYN_RCVD;
8012bba: 697b ldr r3, [r7, #20]
8012bbc: 2203 movs r2, #3
8012bbe: 751a strb r2, [r3, #20]
npcb->rcv_nxt = seqno + 1;
8012bc0: 4b41 ldr r3, [pc, #260] ; (8012cc8 <tcp_listen_input+0x1e0>)
8012bc2: 681b ldr r3, [r3, #0]
8012bc4: 1c5a adds r2, r3, #1
8012bc6: 697b ldr r3, [r7, #20]
8012bc8: 625a str r2, [r3, #36] ; 0x24
npcb->rcv_ann_right_edge = npcb->rcv_nxt;
8012bca: 697b ldr r3, [r7, #20]
8012bcc: 6a5a ldr r2, [r3, #36] ; 0x24
8012bce: 697b ldr r3, [r7, #20]
8012bd0: 62da str r2, [r3, #44] ; 0x2c
iss = tcp_next_iss(npcb);
8012bd2: 6978 ldr r0, [r7, #20]
8012bd4: f7ff fa5c bl 8012090 <tcp_next_iss>
8012bd8: 6138 str r0, [r7, #16]
npcb->snd_wl2 = iss;
8012bda: 697b ldr r3, [r7, #20]
8012bdc: 693a ldr r2, [r7, #16]
8012bde: 659a str r2, [r3, #88] ; 0x58
npcb->snd_nxt = iss;
8012be0: 697b ldr r3, [r7, #20]
8012be2: 693a ldr r2, [r7, #16]
8012be4: 651a str r2, [r3, #80] ; 0x50
npcb->lastack = iss;
8012be6: 697b ldr r3, [r7, #20]
8012be8: 693a ldr r2, [r7, #16]
8012bea: 645a str r2, [r3, #68] ; 0x44
npcb->snd_lbb = iss;
8012bec: 697b ldr r3, [r7, #20]
8012bee: 693a ldr r2, [r7, #16]
8012bf0: 65da str r2, [r3, #92] ; 0x5c
npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
8012bf2: 4b35 ldr r3, [pc, #212] ; (8012cc8 <tcp_listen_input+0x1e0>)
8012bf4: 681b ldr r3, [r3, #0]
8012bf6: 1e5a subs r2, r3, #1
8012bf8: 697b ldr r3, [r7, #20]
8012bfa: 655a str r2, [r3, #84] ; 0x54
npcb->callback_arg = pcb->callback_arg;
8012bfc: 687b ldr r3, [r7, #4]
8012bfe: 691a ldr r2, [r3, #16]
8012c00: 697b ldr r3, [r7, #20]
8012c02: 611a str r2, [r3, #16]
npcb->listener = pcb;
8012c04: 697b ldr r3, [r7, #20]
8012c06: 687a ldr r2, [r7, #4]
8012c08: 67da str r2, [r3, #124] ; 0x7c
npcb->so_options = pcb->so_options & SOF_INHERITED;
8012c0a: 687b ldr r3, [r7, #4]
8012c0c: 7a5b ldrb r3, [r3, #9]
8012c0e: f003 030c and.w r3, r3, #12
8012c12: b2da uxtb r2, r3
8012c14: 697b ldr r3, [r7, #20]
8012c16: 725a strb r2, [r3, #9]
npcb->netif_idx = pcb->netif_idx;
8012c18: 687b ldr r3, [r7, #4]
8012c1a: 7a1a ldrb r2, [r3, #8]
8012c1c: 697b ldr r3, [r7, #20]
8012c1e: 721a strb r2, [r3, #8]
TCP_REG_ACTIVE(npcb);
8012c20: 4b2e ldr r3, [pc, #184] ; (8012cdc <tcp_listen_input+0x1f4>)
8012c22: 681a ldr r2, [r3, #0]
8012c24: 697b ldr r3, [r7, #20]
8012c26: 60da str r2, [r3, #12]
8012c28: 4a2c ldr r2, [pc, #176] ; (8012cdc <tcp_listen_input+0x1f4>)
8012c2a: 697b ldr r3, [r7, #20]
8012c2c: 6013 str r3, [r2, #0]
8012c2e: f003 f8e1 bl 8015df4 <tcp_timer_needed>
8012c32: 4b2b ldr r3, [pc, #172] ; (8012ce0 <tcp_listen_input+0x1f8>)
8012c34: 2201 movs r2, #1
8012c36: 701a strb r2, [r3, #0]
tcp_parseopt(npcb);
8012c38: 6978 ldr r0, [r7, #20]
8012c3a: f001 fd8f bl 801475c <tcp_parseopt>
npcb->snd_wnd = tcphdr->wnd;
8012c3e: 4b23 ldr r3, [pc, #140] ; (8012ccc <tcp_listen_input+0x1e4>)
8012c40: 681b ldr r3, [r3, #0]
8012c42: 89db ldrh r3, [r3, #14]
8012c44: b29a uxth r2, r3
8012c46: 697b ldr r3, [r7, #20]
8012c48: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
npcb->snd_wnd_max = npcb->snd_wnd;
8012c4c: 697b ldr r3, [r7, #20]
8012c4e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012c52: 697b ldr r3, [r7, #20]
8012c54: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
8012c58: 697b ldr r3, [r7, #20]
8012c5a: 8e5c ldrh r4, [r3, #50] ; 0x32
8012c5c: 697b ldr r3, [r7, #20]
8012c5e: 3304 adds r3, #4
8012c60: 4618 mov r0, r3
8012c62: f006 fe7d bl 8019960 <ip4_route>
8012c66: 4601 mov r1, r0
8012c68: 697b ldr r3, [r7, #20]
8012c6a: 3304 adds r3, #4
8012c6c: 461a mov r2, r3
8012c6e: 4620 mov r0, r4
8012c70: f7ff fa34 bl 80120dc <tcp_eff_send_mss_netif>
8012c74: 4603 mov r3, r0
8012c76: 461a mov r2, r3
8012c78: 697b ldr r3, [r7, #20]
8012c7a: 865a strh r2, [r3, #50] ; 0x32
rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
8012c7c: 2112 movs r1, #18
8012c7e: 6978 ldr r0, [r7, #20]
8012c80: f002 f842 bl 8014d08 <tcp_enqueue_flags>
8012c84: 4603 mov r3, r0
8012c86: 73fb strb r3, [r7, #15]
if (rc != ERR_OK) {
8012c88: f997 300f ldrsb.w r3, [r7, #15]
8012c8c: 2b00 cmp r3, #0
8012c8e: d004 beq.n 8012c9a <tcp_listen_input+0x1b2>
tcp_abandon(npcb, 0);
8012c90: 2100 movs r1, #0
8012c92: 6978 ldr r0, [r7, #20]
8012c94: f7fe f986 bl 8010fa4 <tcp_abandon>
return;
8012c98: e007 b.n 8012caa <tcp_listen_input+0x1c2>
tcp_output(npcb);
8012c9a: 6978 ldr r0, [r7, #20]
8012c9c: f002 f922 bl 8014ee4 <tcp_output>
return;
8012ca0: bf00 nop
8012ca2: e001 b.n 8012ca8 <tcp_listen_input+0x1c0>
return;
8012ca4: bf00 nop
8012ca6: e000 b.n 8012caa <tcp_listen_input+0x1c2>
return;
8012ca8: bf00 nop
}
8012caa: 371c adds r7, #28
8012cac: 46bd mov sp, r7
8012cae: bd90 pop {r4, r7, pc}
8012cb0: 20008758 .word 0x20008758
8012cb4: 0801d2b0 .word 0x0801d2b0
8012cb8: 0801d4a8 .word 0x0801d4a8
8012cbc: 0801d2fc .word 0x0801d2fc
8012cc0: 20008750 .word 0x20008750
8012cc4: 20008756 .word 0x20008756
8012cc8: 2000874c .word 0x2000874c
8012ccc: 2000873c .word 0x2000873c
8012cd0: 2000be9c .word 0x2000be9c
8012cd4: 2000bea0 .word 0x2000bea0
8012cd8: 2000be8c .word 0x2000be8c
8012cdc: 2000f5c0 .word 0x2000f5c0
8012ce0: 2000f5bc .word 0x2000f5bc
08012ce4 <tcp_timewait_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_timewait_input(struct tcp_pcb *pcb)
{
8012ce4: b580 push {r7, lr}
8012ce6: b086 sub sp, #24
8012ce8: af04 add r7, sp, #16
8012cea: 6078 str r0, [r7, #4]
/* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
/* RFC 793 3.9 Event Processing - Segment Arrives:
* - first check sequence number - we skip that one in TIME_WAIT (always
* acceptable since we only send ACKs)
* - second check the RST bit (... return) */
if (flags & TCP_RST) {
8012cec: 4b30 ldr r3, [pc, #192] ; (8012db0 <tcp_timewait_input+0xcc>)
8012cee: 781b ldrb r3, [r3, #0]
8012cf0: f003 0304 and.w r3, r3, #4
8012cf4: 2b00 cmp r3, #0
8012cf6: d154 bne.n 8012da2 <tcp_timewait_input+0xbe>
return;
}
LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
8012cf8: 687b ldr r3, [r7, #4]
8012cfa: 2b00 cmp r3, #0
8012cfc: d106 bne.n 8012d0c <tcp_timewait_input+0x28>
8012cfe: 4b2d ldr r3, [pc, #180] ; (8012db4 <tcp_timewait_input+0xd0>)
8012d00: f240 22ee movw r2, #750 ; 0x2ee
8012d04: 492c ldr r1, [pc, #176] ; (8012db8 <tcp_timewait_input+0xd4>)
8012d06: 482d ldr r0, [pc, #180] ; (8012dbc <tcp_timewait_input+0xd8>)
8012d08: f008 f984 bl 801b014 <iprintf>
/* - fourth, check the SYN bit, */
if (flags & TCP_SYN) {
8012d0c: 4b28 ldr r3, [pc, #160] ; (8012db0 <tcp_timewait_input+0xcc>)
8012d0e: 781b ldrb r3, [r3, #0]
8012d10: f003 0302 and.w r3, r3, #2
8012d14: 2b00 cmp r3, #0
8012d16: d02a beq.n 8012d6e <tcp_timewait_input+0x8a>
/* If an incoming segment is not acceptable, an acknowledgment
should be sent in reply */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
8012d18: 4b29 ldr r3, [pc, #164] ; (8012dc0 <tcp_timewait_input+0xdc>)
8012d1a: 681a ldr r2, [r3, #0]
8012d1c: 687b ldr r3, [r7, #4]
8012d1e: 6a5b ldr r3, [r3, #36] ; 0x24
8012d20: 1ad3 subs r3, r2, r3
8012d22: 2b00 cmp r3, #0
8012d24: db2d blt.n 8012d82 <tcp_timewait_input+0x9e>
8012d26: 4b26 ldr r3, [pc, #152] ; (8012dc0 <tcp_timewait_input+0xdc>)
8012d28: 681a ldr r2, [r3, #0]
8012d2a: 687b ldr r3, [r7, #4]
8012d2c: 6a5b ldr r3, [r3, #36] ; 0x24
8012d2e: 6879 ldr r1, [r7, #4]
8012d30: 8d09 ldrh r1, [r1, #40] ; 0x28
8012d32: 440b add r3, r1
8012d34: 1ad3 subs r3, r2, r3
8012d36: 2b00 cmp r3, #0
8012d38: dc23 bgt.n 8012d82 <tcp_timewait_input+0x9e>
/* If the SYN is in the window it is an error, send a reset */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d3a: 4b22 ldr r3, [pc, #136] ; (8012dc4 <tcp_timewait_input+0xe0>)
8012d3c: 6819 ldr r1, [r3, #0]
8012d3e: 4b22 ldr r3, [pc, #136] ; (8012dc8 <tcp_timewait_input+0xe4>)
8012d40: 881b ldrh r3, [r3, #0]
8012d42: 461a mov r2, r3
8012d44: 4b1e ldr r3, [pc, #120] ; (8012dc0 <tcp_timewait_input+0xdc>)
8012d46: 681b ldr r3, [r3, #0]
8012d48: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d4a: 4b20 ldr r3, [pc, #128] ; (8012dcc <tcp_timewait_input+0xe8>)
8012d4c: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d4e: 885b ldrh r3, [r3, #2]
8012d50: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d52: 4a1e ldr r2, [pc, #120] ; (8012dcc <tcp_timewait_input+0xe8>)
8012d54: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d56: 8812 ldrh r2, [r2, #0]
8012d58: b292 uxth r2, r2
8012d5a: 9202 str r2, [sp, #8]
8012d5c: 9301 str r3, [sp, #4]
8012d5e: 4b1c ldr r3, [pc, #112] ; (8012dd0 <tcp_timewait_input+0xec>)
8012d60: 9300 str r3, [sp, #0]
8012d62: 4b1c ldr r3, [pc, #112] ; (8012dd4 <tcp_timewait_input+0xf0>)
8012d64: 4602 mov r2, r0
8012d66: 6878 ldr r0, [r7, #4]
8012d68: f002 fe82 bl 8015a70 <tcp_rst>
return;
8012d6c: e01c b.n 8012da8 <tcp_timewait_input+0xc4>
}
} else if (flags & TCP_FIN) {
8012d6e: 4b10 ldr r3, [pc, #64] ; (8012db0 <tcp_timewait_input+0xcc>)
8012d70: 781b ldrb r3, [r3, #0]
8012d72: f003 0301 and.w r3, r3, #1
8012d76: 2b00 cmp r3, #0
8012d78: d003 beq.n 8012d82 <tcp_timewait_input+0x9e>
/* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
Restart the 2 MSL time-wait timeout.*/
pcb->tmr = tcp_ticks;
8012d7a: 4b17 ldr r3, [pc, #92] ; (8012dd8 <tcp_timewait_input+0xf4>)
8012d7c: 681a ldr r2, [r3, #0]
8012d7e: 687b ldr r3, [r7, #4]
8012d80: 621a str r2, [r3, #32]
}
if ((tcplen > 0)) {
8012d82: 4b11 ldr r3, [pc, #68] ; (8012dc8 <tcp_timewait_input+0xe4>)
8012d84: 881b ldrh r3, [r3, #0]
8012d86: 2b00 cmp r3, #0
8012d88: d00d beq.n 8012da6 <tcp_timewait_input+0xc2>
/* Acknowledge data, FIN or out-of-window SYN */
tcp_ack_now(pcb);
8012d8a: 687b ldr r3, [r7, #4]
8012d8c: 8b5b ldrh r3, [r3, #26]
8012d8e: f043 0302 orr.w r3, r3, #2
8012d92: b29a uxth r2, r3
8012d94: 687b ldr r3, [r7, #4]
8012d96: 835a strh r2, [r3, #26]
tcp_output(pcb);
8012d98: 6878 ldr r0, [r7, #4]
8012d9a: f002 f8a3 bl 8014ee4 <tcp_output>
}
return;
8012d9e: bf00 nop
8012da0: e001 b.n 8012da6 <tcp_timewait_input+0xc2>
return;
8012da2: bf00 nop
8012da4: e000 b.n 8012da8 <tcp_timewait_input+0xc4>
return;
8012da6: bf00 nop
}
8012da8: 3708 adds r7, #8
8012daa: 46bd mov sp, r7
8012dac: bd80 pop {r7, pc}
8012dae: bf00 nop
8012db0: 20008758 .word 0x20008758
8012db4: 0801d2b0 .word 0x0801d2b0
8012db8: 0801d4c8 .word 0x0801d4c8
8012dbc: 0801d2fc .word 0x0801d2fc
8012dc0: 2000874c .word 0x2000874c
8012dc4: 20008750 .word 0x20008750
8012dc8: 20008756 .word 0x20008756
8012dcc: 2000873c .word 0x2000873c
8012dd0: 2000be9c .word 0x2000be9c
8012dd4: 2000bea0 .word 0x2000bea0
8012dd8: 2000f5c4 .word 0x2000f5c4
08012ddc <tcp_process>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static err_t
tcp_process(struct tcp_pcb *pcb)
{
8012ddc: b590 push {r4, r7, lr}
8012dde: b08d sub sp, #52 ; 0x34
8012de0: af04 add r7, sp, #16
8012de2: 6078 str r0, [r7, #4]
struct tcp_seg *rseg;
u8_t acceptable = 0;
8012de4: 2300 movs r3, #0
8012de6: 76fb strb r3, [r7, #27]
err_t err;
err = ERR_OK;
8012de8: 2300 movs r3, #0
8012dea: 76bb strb r3, [r7, #26]
LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
8012dec: 687b ldr r3, [r7, #4]
8012dee: 2b00 cmp r3, #0
8012df0: d106 bne.n 8012e00 <tcp_process+0x24>
8012df2: 4ba5 ldr r3, [pc, #660] ; (8013088 <tcp_process+0x2ac>)
8012df4: f44f 7247 mov.w r2, #796 ; 0x31c
8012df8: 49a4 ldr r1, [pc, #656] ; (801308c <tcp_process+0x2b0>)
8012dfa: 48a5 ldr r0, [pc, #660] ; (8013090 <tcp_process+0x2b4>)
8012dfc: f008 f90a bl 801b014 <iprintf>
/* Process incoming RST segments. */
if (flags & TCP_RST) {
8012e00: 4ba4 ldr r3, [pc, #656] ; (8013094 <tcp_process+0x2b8>)
8012e02: 781b ldrb r3, [r3, #0]
8012e04: f003 0304 and.w r3, r3, #4
8012e08: 2b00 cmp r3, #0
8012e0a: d04e beq.n 8012eaa <tcp_process+0xce>
/* First, determine if the reset is acceptable. */
if (pcb->state == SYN_SENT) {
8012e0c: 687b ldr r3, [r7, #4]
8012e0e: 7d1b ldrb r3, [r3, #20]
8012e10: 2b02 cmp r3, #2
8012e12: d108 bne.n 8012e26 <tcp_process+0x4a>
/* "In the SYN-SENT state (a RST received in response to an initial SYN),
the RST is acceptable if the ACK field acknowledges the SYN." */
if (ackno == pcb->snd_nxt) {
8012e14: 687b ldr r3, [r7, #4]
8012e16: 6d1a ldr r2, [r3, #80] ; 0x50
8012e18: 4b9f ldr r3, [pc, #636] ; (8013098 <tcp_process+0x2bc>)
8012e1a: 681b ldr r3, [r3, #0]
8012e1c: 429a cmp r2, r3
8012e1e: d123 bne.n 8012e68 <tcp_process+0x8c>
acceptable = 1;
8012e20: 2301 movs r3, #1
8012e22: 76fb strb r3, [r7, #27]
8012e24: e020 b.n 8012e68 <tcp_process+0x8c>
}
} else {
/* "In all states except SYN-SENT, all reset (RST) segments are validated
by checking their SEQ-fields." */
if (seqno == pcb->rcv_nxt) {
8012e26: 687b ldr r3, [r7, #4]
8012e28: 6a5a ldr r2, [r3, #36] ; 0x24
8012e2a: 4b9c ldr r3, [pc, #624] ; (801309c <tcp_process+0x2c0>)
8012e2c: 681b ldr r3, [r3, #0]
8012e2e: 429a cmp r2, r3
8012e30: d102 bne.n 8012e38 <tcp_process+0x5c>
acceptable = 1;
8012e32: 2301 movs r3, #1
8012e34: 76fb strb r3, [r7, #27]
8012e36: e017 b.n 8012e68 <tcp_process+0x8c>
} else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8012e38: 4b98 ldr r3, [pc, #608] ; (801309c <tcp_process+0x2c0>)
8012e3a: 681a ldr r2, [r3, #0]
8012e3c: 687b ldr r3, [r7, #4]
8012e3e: 6a5b ldr r3, [r3, #36] ; 0x24
8012e40: 1ad3 subs r3, r2, r3
8012e42: 2b00 cmp r3, #0
8012e44: db10 blt.n 8012e68 <tcp_process+0x8c>
8012e46: 4b95 ldr r3, [pc, #596] ; (801309c <tcp_process+0x2c0>)
8012e48: 681a ldr r2, [r3, #0]
8012e4a: 687b ldr r3, [r7, #4]
8012e4c: 6a5b ldr r3, [r3, #36] ; 0x24
8012e4e: 6879 ldr r1, [r7, #4]
8012e50: 8d09 ldrh r1, [r1, #40] ; 0x28
8012e52: 440b add r3, r1
8012e54: 1ad3 subs r3, r2, r3
8012e56: 2b00 cmp r3, #0
8012e58: dc06 bgt.n 8012e68 <tcp_process+0x8c>
pcb->rcv_nxt + pcb->rcv_wnd)) {
/* If the sequence number is inside the window, we send a challenge ACK
and wait for a re-send with matching sequence number.
This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
(RST spoofing attack), which is present in RFC 793 RST handling. */
tcp_ack_now(pcb);
8012e5a: 687b ldr r3, [r7, #4]
8012e5c: 8b5b ldrh r3, [r3, #26]
8012e5e: f043 0302 orr.w r3, r3, #2
8012e62: b29a uxth r2, r3
8012e64: 687b ldr r3, [r7, #4]
8012e66: 835a strh r2, [r3, #26]
}
}
if (acceptable) {
8012e68: 7efb ldrb r3, [r7, #27]
8012e6a: 2b00 cmp r3, #0
8012e6c: d01b beq.n 8012ea6 <tcp_process+0xca>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
8012e6e: 687b ldr r3, [r7, #4]
8012e70: 7d1b ldrb r3, [r3, #20]
8012e72: 2b00 cmp r3, #0
8012e74: d106 bne.n 8012e84 <tcp_process+0xa8>
8012e76: 4b84 ldr r3, [pc, #528] ; (8013088 <tcp_process+0x2ac>)
8012e78: f44f 724e mov.w r2, #824 ; 0x338
8012e7c: 4988 ldr r1, [pc, #544] ; (80130a0 <tcp_process+0x2c4>)
8012e7e: 4884 ldr r0, [pc, #528] ; (8013090 <tcp_process+0x2b4>)
8012e80: f008 f8c8 bl 801b014 <iprintf>
recv_flags |= TF_RESET;
8012e84: 4b87 ldr r3, [pc, #540] ; (80130a4 <tcp_process+0x2c8>)
8012e86: 781b ldrb r3, [r3, #0]
8012e88: f043 0308 orr.w r3, r3, #8
8012e8c: b2da uxtb r2, r3
8012e8e: 4b85 ldr r3, [pc, #532] ; (80130a4 <tcp_process+0x2c8>)
8012e90: 701a strb r2, [r3, #0]
tcp_clear_flags(pcb, TF_ACK_DELAY);
8012e92: 687b ldr r3, [r7, #4]
8012e94: 8b5b ldrh r3, [r3, #26]
8012e96: f023 0301 bic.w r3, r3, #1
8012e9a: b29a uxth r2, r3
8012e9c: 687b ldr r3, [r7, #4]
8012e9e: 835a strh r2, [r3, #26]
return ERR_RST;
8012ea0: f06f 030d mvn.w r3, #13
8012ea4: e37a b.n 801359c <tcp_process+0x7c0>
} else {
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
return ERR_OK;
8012ea6: 2300 movs r3, #0
8012ea8: e378 b.n 801359c <tcp_process+0x7c0>
}
}
if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
8012eaa: 4b7a ldr r3, [pc, #488] ; (8013094 <tcp_process+0x2b8>)
8012eac: 781b ldrb r3, [r3, #0]
8012eae: f003 0302 and.w r3, r3, #2
8012eb2: 2b00 cmp r3, #0
8012eb4: d010 beq.n 8012ed8 <tcp_process+0xfc>
8012eb6: 687b ldr r3, [r7, #4]
8012eb8: 7d1b ldrb r3, [r3, #20]
8012eba: 2b02 cmp r3, #2
8012ebc: d00c beq.n 8012ed8 <tcp_process+0xfc>
8012ebe: 687b ldr r3, [r7, #4]
8012ec0: 7d1b ldrb r3, [r3, #20]
8012ec2: 2b03 cmp r3, #3
8012ec4: d008 beq.n 8012ed8 <tcp_process+0xfc>
/* Cope with new connection attempt after remote end crashed */
tcp_ack_now(pcb);
8012ec6: 687b ldr r3, [r7, #4]
8012ec8: 8b5b ldrh r3, [r3, #26]
8012eca: f043 0302 orr.w r3, r3, #2
8012ece: b29a uxth r2, r3
8012ed0: 687b ldr r3, [r7, #4]
8012ed2: 835a strh r2, [r3, #26]
return ERR_OK;
8012ed4: 2300 movs r3, #0
8012ed6: e361 b.n 801359c <tcp_process+0x7c0>
}
if ((pcb->flags & TF_RXCLOSED) == 0) {
8012ed8: 687b ldr r3, [r7, #4]
8012eda: 8b5b ldrh r3, [r3, #26]
8012edc: f003 0310 and.w r3, r3, #16
8012ee0: 2b00 cmp r3, #0
8012ee2: d103 bne.n 8012eec <tcp_process+0x110>
/* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
pcb->tmr = tcp_ticks;
8012ee4: 4b70 ldr r3, [pc, #448] ; (80130a8 <tcp_process+0x2cc>)
8012ee6: 681a ldr r2, [r3, #0]
8012ee8: 687b ldr r3, [r7, #4]
8012eea: 621a str r2, [r3, #32]
}
pcb->keep_cnt_sent = 0;
8012eec: 687b ldr r3, [r7, #4]
8012eee: 2200 movs r2, #0
8012ef0: f883 209b strb.w r2, [r3, #155] ; 0x9b
pcb->persist_probe = 0;
8012ef4: 687b ldr r3, [r7, #4]
8012ef6: 2200 movs r2, #0
8012ef8: f883 209a strb.w r2, [r3, #154] ; 0x9a
tcp_parseopt(pcb);
8012efc: 6878 ldr r0, [r7, #4]
8012efe: f001 fc2d bl 801475c <tcp_parseopt>
/* Do different things depending on the TCP state. */
switch (pcb->state) {
8012f02: 687b ldr r3, [r7, #4]
8012f04: 7d1b ldrb r3, [r3, #20]
8012f06: 3b02 subs r3, #2
8012f08: 2b07 cmp r3, #7
8012f0a: f200 8337 bhi.w 801357c <tcp_process+0x7a0>
8012f0e: a201 add r2, pc, #4 ; (adr r2, 8012f14 <tcp_process+0x138>)
8012f10: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8012f14: 08012f35 .word 0x08012f35
8012f18: 08013165 .word 0x08013165
8012f1c: 080132dd .word 0x080132dd
8012f20: 08013307 .word 0x08013307
8012f24: 0801342b .word 0x0801342b
8012f28: 080132dd .word 0x080132dd
8012f2c: 080134b7 .word 0x080134b7
8012f30: 08013547 .word 0x08013547
case SYN_SENT:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
/* received SYN ACK with expected sequence number? */
if ((flags & TCP_ACK) && (flags & TCP_SYN)
8012f34: 4b57 ldr r3, [pc, #348] ; (8013094 <tcp_process+0x2b8>)
8012f36: 781b ldrb r3, [r3, #0]
8012f38: f003 0310 and.w r3, r3, #16
8012f3c: 2b00 cmp r3, #0
8012f3e: f000 80e4 beq.w 801310a <tcp_process+0x32e>
8012f42: 4b54 ldr r3, [pc, #336] ; (8013094 <tcp_process+0x2b8>)
8012f44: 781b ldrb r3, [r3, #0]
8012f46: f003 0302 and.w r3, r3, #2
8012f4a: 2b00 cmp r3, #0
8012f4c: f000 80dd beq.w 801310a <tcp_process+0x32e>
&& (ackno == pcb->lastack + 1)) {
8012f50: 687b ldr r3, [r7, #4]
8012f52: 6c5b ldr r3, [r3, #68] ; 0x44
8012f54: 1c5a adds r2, r3, #1
8012f56: 4b50 ldr r3, [pc, #320] ; (8013098 <tcp_process+0x2bc>)
8012f58: 681b ldr r3, [r3, #0]
8012f5a: 429a cmp r2, r3
8012f5c: f040 80d5 bne.w 801310a <tcp_process+0x32e>
pcb->rcv_nxt = seqno + 1;
8012f60: 4b4e ldr r3, [pc, #312] ; (801309c <tcp_process+0x2c0>)
8012f62: 681b ldr r3, [r3, #0]
8012f64: 1c5a adds r2, r3, #1
8012f66: 687b ldr r3, [r7, #4]
8012f68: 625a str r2, [r3, #36] ; 0x24
pcb->rcv_ann_right_edge = pcb->rcv_nxt;
8012f6a: 687b ldr r3, [r7, #4]
8012f6c: 6a5a ldr r2, [r3, #36] ; 0x24
8012f6e: 687b ldr r3, [r7, #4]
8012f70: 62da str r2, [r3, #44] ; 0x2c
pcb->lastack = ackno;
8012f72: 4b49 ldr r3, [pc, #292] ; (8013098 <tcp_process+0x2bc>)
8012f74: 681a ldr r2, [r3, #0]
8012f76: 687b ldr r3, [r7, #4]
8012f78: 645a str r2, [r3, #68] ; 0x44
pcb->snd_wnd = tcphdr->wnd;
8012f7a: 4b4c ldr r3, [pc, #304] ; (80130ac <tcp_process+0x2d0>)
8012f7c: 681b ldr r3, [r3, #0]
8012f7e: 89db ldrh r3, [r3, #14]
8012f80: b29a uxth r2, r3
8012f82: 687b ldr r3, [r7, #4]
8012f84: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
pcb->snd_wnd_max = pcb->snd_wnd;
8012f88: 687b ldr r3, [r7, #4]
8012f8a: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012f8e: 687b ldr r3, [r7, #4]
8012f90: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
8012f94: 4b41 ldr r3, [pc, #260] ; (801309c <tcp_process+0x2c0>)
8012f96: 681b ldr r3, [r3, #0]
8012f98: 1e5a subs r2, r3, #1
8012f9a: 687b ldr r3, [r7, #4]
8012f9c: 655a str r2, [r3, #84] ; 0x54
pcb->state = ESTABLISHED;
8012f9e: 687b ldr r3, [r7, #4]
8012fa0: 2204 movs r2, #4
8012fa2: 751a strb r2, [r3, #20]
#if TCP_CALCULATE_EFF_SEND_MSS
pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
8012fa4: 687b ldr r3, [r7, #4]
8012fa6: 8e5c ldrh r4, [r3, #50] ; 0x32
8012fa8: 687b ldr r3, [r7, #4]
8012faa: 3304 adds r3, #4
8012fac: 4618 mov r0, r3
8012fae: f006 fcd7 bl 8019960 <ip4_route>
8012fb2: 4601 mov r1, r0
8012fb4: 687b ldr r3, [r7, #4]
8012fb6: 3304 adds r3, #4
8012fb8: 461a mov r2, r3
8012fba: 4620 mov r0, r4
8012fbc: f7ff f88e bl 80120dc <tcp_eff_send_mss_netif>
8012fc0: 4603 mov r3, r0
8012fc2: 461a mov r2, r3
8012fc4: 687b ldr r3, [r7, #4]
8012fc6: 865a strh r2, [r3, #50] ; 0x32
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
8012fc8: 687b ldr r3, [r7, #4]
8012fca: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fcc: 009a lsls r2, r3, #2
8012fce: 687b ldr r3, [r7, #4]
8012fd0: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fd2: 005b lsls r3, r3, #1
8012fd4: f241 111c movw r1, #4380 ; 0x111c
8012fd8: 428b cmp r3, r1
8012fda: bf38 it cc
8012fdc: 460b movcc r3, r1
8012fde: 429a cmp r2, r3
8012fe0: d204 bcs.n 8012fec <tcp_process+0x210>
8012fe2: 687b ldr r3, [r7, #4]
8012fe4: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fe6: 009b lsls r3, r3, #2
8012fe8: b29b uxth r3, r3
8012fea: e00d b.n 8013008 <tcp_process+0x22c>
8012fec: 687b ldr r3, [r7, #4]
8012fee: 8e5b ldrh r3, [r3, #50] ; 0x32
8012ff0: 005b lsls r3, r3, #1
8012ff2: f241 121c movw r2, #4380 ; 0x111c
8012ff6: 4293 cmp r3, r2
8012ff8: d904 bls.n 8013004 <tcp_process+0x228>
8012ffa: 687b ldr r3, [r7, #4]
8012ffc: 8e5b ldrh r3, [r3, #50] ; 0x32
8012ffe: 005b lsls r3, r3, #1
8013000: b29b uxth r3, r3
8013002: e001 b.n 8013008 <tcp_process+0x22c>
8013004: f241 131c movw r3, #4380 ; 0x111c
8013008: 687a ldr r2, [r7, #4]
801300a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
801300e: 687b ldr r3, [r7, #4]
8013010: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8013014: 2b00 cmp r3, #0
8013016: d106 bne.n 8013026 <tcp_process+0x24a>
8013018: 4b1b ldr r3, [pc, #108] ; (8013088 <tcp_process+0x2ac>)
801301a: f44f 725b mov.w r2, #876 ; 0x36c
801301e: 4924 ldr r1, [pc, #144] ; (80130b0 <tcp_process+0x2d4>)
8013020: 481b ldr r0, [pc, #108] ; (8013090 <tcp_process+0x2b4>)
8013022: f007 fff7 bl 801b014 <iprintf>
--pcb->snd_queuelen;
8013026: 687b ldr r3, [r7, #4]
8013028: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
801302c: 3b01 subs r3, #1
801302e: b29a uxth r2, r3
8013030: 687b ldr r3, [r7, #4]
8013032: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
rseg = pcb->unacked;
8013036: 687b ldr r3, [r7, #4]
8013038: 6f1b ldr r3, [r3, #112] ; 0x70
801303a: 61fb str r3, [r7, #28]
if (rseg == NULL) {
801303c: 69fb ldr r3, [r7, #28]
801303e: 2b00 cmp r3, #0
8013040: d111 bne.n 8013066 <tcp_process+0x28a>
/* might happen if tcp_output fails in tcp_rexmit_rto()
in which case the segment is on the unsent list */
rseg = pcb->unsent;
8013042: 687b ldr r3, [r7, #4]
8013044: 6edb ldr r3, [r3, #108] ; 0x6c
8013046: 61fb str r3, [r7, #28]
LWIP_ASSERT("no segment to free", rseg != NULL);
8013048: 69fb ldr r3, [r7, #28]
801304a: 2b00 cmp r3, #0
801304c: d106 bne.n 801305c <tcp_process+0x280>
801304e: 4b0e ldr r3, [pc, #56] ; (8013088 <tcp_process+0x2ac>)
8013050: f44f 725d mov.w r2, #884 ; 0x374
8013054: 4917 ldr r1, [pc, #92] ; (80130b4 <tcp_process+0x2d8>)
8013056: 480e ldr r0, [pc, #56] ; (8013090 <tcp_process+0x2b4>)
8013058: f007 ffdc bl 801b014 <iprintf>
pcb->unsent = rseg->next;
801305c: 69fb ldr r3, [r7, #28]
801305e: 681a ldr r2, [r3, #0]
8013060: 687b ldr r3, [r7, #4]
8013062: 66da str r2, [r3, #108] ; 0x6c
8013064: e003 b.n 801306e <tcp_process+0x292>
} else {
pcb->unacked = rseg->next;
8013066: 69fb ldr r3, [r7, #28]
8013068: 681a ldr r2, [r3, #0]
801306a: 687b ldr r3, [r7, #4]
801306c: 671a str r2, [r3, #112] ; 0x70
}
tcp_seg_free(rseg);
801306e: 69f8 ldr r0, [r7, #28]
8013070: f7fe fd3e bl 8011af0 <tcp_seg_free>
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013074: 687b ldr r3, [r7, #4]
8013076: 6f1b ldr r3, [r3, #112] ; 0x70
8013078: 2b00 cmp r3, #0
801307a: d11d bne.n 80130b8 <tcp_process+0x2dc>
pcb->rtime = -1;
801307c: 687b ldr r3, [r7, #4]
801307e: f64f 72ff movw r2, #65535 ; 0xffff
8013082: 861a strh r2, [r3, #48] ; 0x30
8013084: e01f b.n 80130c6 <tcp_process+0x2ea>
8013086: bf00 nop
8013088: 0801d2b0 .word 0x0801d2b0
801308c: 0801d4e8 .word 0x0801d4e8
8013090: 0801d2fc .word 0x0801d2fc
8013094: 20008758 .word 0x20008758
8013098: 20008750 .word 0x20008750
801309c: 2000874c .word 0x2000874c
80130a0: 0801d504 .word 0x0801d504
80130a4: 20008759 .word 0x20008759
80130a8: 2000f5c4 .word 0x2000f5c4
80130ac: 2000873c .word 0x2000873c
80130b0: 0801d524 .word 0x0801d524
80130b4: 0801d53c .word 0x0801d53c
} else {
pcb->rtime = 0;
80130b8: 687b ldr r3, [r7, #4]
80130ba: 2200 movs r2, #0
80130bc: 861a strh r2, [r3, #48] ; 0x30
pcb->nrtx = 0;
80130be: 687b ldr r3, [r7, #4]
80130c0: 2200 movs r2, #0
80130c2: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Call the user specified function to call when successfully
* connected. */
TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
80130c6: 687b ldr r3, [r7, #4]
80130c8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130cc: 2b00 cmp r3, #0
80130ce: d00a beq.n 80130e6 <tcp_process+0x30a>
80130d0: 687b ldr r3, [r7, #4]
80130d2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130d6: 687a ldr r2, [r7, #4]
80130d8: 6910 ldr r0, [r2, #16]
80130da: 2200 movs r2, #0
80130dc: 6879 ldr r1, [r7, #4]
80130de: 4798 blx r3
80130e0: 4603 mov r3, r0
80130e2: 76bb strb r3, [r7, #26]
80130e4: e001 b.n 80130ea <tcp_process+0x30e>
80130e6: 2300 movs r3, #0
80130e8: 76bb strb r3, [r7, #26]
if (err == ERR_ABRT) {
80130ea: f997 301a ldrsb.w r3, [r7, #26]
80130ee: f113 0f0d cmn.w r3, #13
80130f2: d102 bne.n 80130fa <tcp_process+0x31e>
return ERR_ABRT;
80130f4: f06f 030c mvn.w r3, #12
80130f8: e250 b.n 801359c <tcp_process+0x7c0>
}
tcp_ack_now(pcb);
80130fa: 687b ldr r3, [r7, #4]
80130fc: 8b5b ldrh r3, [r3, #26]
80130fe: f043 0302 orr.w r3, r3, #2
8013102: b29a uxth r2, r3
8013104: 687b ldr r3, [r7, #4]
8013106: 835a strh r2, [r3, #26]
if (pcb->nrtx < TCP_SYNMAXRTX) {
pcb->rtime = 0;
tcp_rexmit_rto(pcb);
}
}
break;
8013108: e23a b.n 8013580 <tcp_process+0x7a4>
else if (flags & TCP_ACK) {
801310a: 4b9d ldr r3, [pc, #628] ; (8013380 <tcp_process+0x5a4>)
801310c: 781b ldrb r3, [r3, #0]
801310e: f003 0310 and.w r3, r3, #16
8013112: 2b00 cmp r3, #0
8013114: f000 8234 beq.w 8013580 <tcp_process+0x7a4>
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013118: 4b9a ldr r3, [pc, #616] ; (8013384 <tcp_process+0x5a8>)
801311a: 6819 ldr r1, [r3, #0]
801311c: 4b9a ldr r3, [pc, #616] ; (8013388 <tcp_process+0x5ac>)
801311e: 881b ldrh r3, [r3, #0]
8013120: 461a mov r2, r3
8013122: 4b9a ldr r3, [pc, #616] ; (801338c <tcp_process+0x5b0>)
8013124: 681b ldr r3, [r3, #0]
8013126: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013128: 4b99 ldr r3, [pc, #612] ; (8013390 <tcp_process+0x5b4>)
801312a: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
801312c: 885b ldrh r3, [r3, #2]
801312e: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013130: 4a97 ldr r2, [pc, #604] ; (8013390 <tcp_process+0x5b4>)
8013132: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013134: 8812 ldrh r2, [r2, #0]
8013136: b292 uxth r2, r2
8013138: 9202 str r2, [sp, #8]
801313a: 9301 str r3, [sp, #4]
801313c: 4b95 ldr r3, [pc, #596] ; (8013394 <tcp_process+0x5b8>)
801313e: 9300 str r3, [sp, #0]
8013140: 4b95 ldr r3, [pc, #596] ; (8013398 <tcp_process+0x5bc>)
8013142: 4602 mov r2, r0
8013144: 6878 ldr r0, [r7, #4]
8013146: f002 fc93 bl 8015a70 <tcp_rst>
if (pcb->nrtx < TCP_SYNMAXRTX) {
801314a: 687b ldr r3, [r7, #4]
801314c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8013150: 2b05 cmp r3, #5
8013152: f200 8215 bhi.w 8013580 <tcp_process+0x7a4>
pcb->rtime = 0;
8013156: 687b ldr r3, [r7, #4]
8013158: 2200 movs r2, #0
801315a: 861a strh r2, [r3, #48] ; 0x30
tcp_rexmit_rto(pcb);
801315c: 6878 ldr r0, [r7, #4]
801315e: f002 fa51 bl 8015604 <tcp_rexmit_rto>
break;
8013162: e20d b.n 8013580 <tcp_process+0x7a4>
case SYN_RCVD:
if (flags & TCP_ACK) {
8013164: 4b86 ldr r3, [pc, #536] ; (8013380 <tcp_process+0x5a4>)
8013166: 781b ldrb r3, [r3, #0]
8013168: f003 0310 and.w r3, r3, #16
801316c: 2b00 cmp r3, #0
801316e: f000 80a1 beq.w 80132b4 <tcp_process+0x4d8>
/* expected ACK number? */
if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013172: 4b84 ldr r3, [pc, #528] ; (8013384 <tcp_process+0x5a8>)
8013174: 681a ldr r2, [r3, #0]
8013176: 687b ldr r3, [r7, #4]
8013178: 6c5b ldr r3, [r3, #68] ; 0x44
801317a: 1ad3 subs r3, r2, r3
801317c: 3b01 subs r3, #1
801317e: 2b00 cmp r3, #0
8013180: db7e blt.n 8013280 <tcp_process+0x4a4>
8013182: 4b80 ldr r3, [pc, #512] ; (8013384 <tcp_process+0x5a8>)
8013184: 681a ldr r2, [r3, #0]
8013186: 687b ldr r3, [r7, #4]
8013188: 6d1b ldr r3, [r3, #80] ; 0x50
801318a: 1ad3 subs r3, r2, r3
801318c: 2b00 cmp r3, #0
801318e: dc77 bgt.n 8013280 <tcp_process+0x4a4>
pcb->state = ESTABLISHED;
8013190: 687b ldr r3, [r7, #4]
8013192: 2204 movs r2, #4
8013194: 751a strb r2, [r3, #20]
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
if (pcb->listener == NULL) {
8013196: 687b ldr r3, [r7, #4]
8013198: 6fdb ldr r3, [r3, #124] ; 0x7c
801319a: 2b00 cmp r3, #0
801319c: d102 bne.n 80131a4 <tcp_process+0x3c8>
/* listen pcb might be closed by now */
err = ERR_VAL;
801319e: 23fa movs r3, #250 ; 0xfa
80131a0: 76bb strb r3, [r7, #26]
80131a2: e01d b.n 80131e0 <tcp_process+0x404>
} else
#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
{
#if LWIP_CALLBACK_API
LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
80131a4: 687b ldr r3, [r7, #4]
80131a6: 6fdb ldr r3, [r3, #124] ; 0x7c
80131a8: 699b ldr r3, [r3, #24]
80131aa: 2b00 cmp r3, #0
80131ac: d106 bne.n 80131bc <tcp_process+0x3e0>
80131ae: 4b7b ldr r3, [pc, #492] ; (801339c <tcp_process+0x5c0>)
80131b0: f44f 726a mov.w r2, #936 ; 0x3a8
80131b4: 497a ldr r1, [pc, #488] ; (80133a0 <tcp_process+0x5c4>)
80131b6: 487b ldr r0, [pc, #492] ; (80133a4 <tcp_process+0x5c8>)
80131b8: f007 ff2c bl 801b014 <iprintf>
#endif
tcp_backlog_accepted(pcb);
/* Call the accept function. */
TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
80131bc: 687b ldr r3, [r7, #4]
80131be: 6fdb ldr r3, [r3, #124] ; 0x7c
80131c0: 699b ldr r3, [r3, #24]
80131c2: 2b00 cmp r3, #0
80131c4: d00a beq.n 80131dc <tcp_process+0x400>
80131c6: 687b ldr r3, [r7, #4]
80131c8: 6fdb ldr r3, [r3, #124] ; 0x7c
80131ca: 699b ldr r3, [r3, #24]
80131cc: 687a ldr r2, [r7, #4]
80131ce: 6910 ldr r0, [r2, #16]
80131d0: 2200 movs r2, #0
80131d2: 6879 ldr r1, [r7, #4]
80131d4: 4798 blx r3
80131d6: 4603 mov r3, r0
80131d8: 76bb strb r3, [r7, #26]
80131da: e001 b.n 80131e0 <tcp_process+0x404>
80131dc: 23f0 movs r3, #240 ; 0xf0
80131de: 76bb strb r3, [r7, #26]
}
if (err != ERR_OK) {
80131e0: f997 301a ldrsb.w r3, [r7, #26]
80131e4: 2b00 cmp r3, #0
80131e6: d00a beq.n 80131fe <tcp_process+0x422>
/* If the accept function returns with an error, we abort
* the connection. */
/* Already aborted? */
if (err != ERR_ABRT) {
80131e8: f997 301a ldrsb.w r3, [r7, #26]
80131ec: f113 0f0d cmn.w r3, #13
80131f0: d002 beq.n 80131f8 <tcp_process+0x41c>
tcp_abort(pcb);
80131f2: 6878 ldr r0, [r7, #4]
80131f4: f7fd ff94 bl 8011120 <tcp_abort>
}
return ERR_ABRT;
80131f8: f06f 030c mvn.w r3, #12
80131fc: e1ce b.n 801359c <tcp_process+0x7c0>
}
/* If there was any data contained within this ACK,
* we'd better pass it on to the application as well. */
tcp_receive(pcb);
80131fe: 6878 ldr r0, [r7, #4]
8013200: f000 fae0 bl 80137c4 <tcp_receive>
/* Prevent ACK for SYN to generate a sent event */
if (recv_acked != 0) {
8013204: 4b68 ldr r3, [pc, #416] ; (80133a8 <tcp_process+0x5cc>)
8013206: 881b ldrh r3, [r3, #0]
8013208: 2b00 cmp r3, #0
801320a: d005 beq.n 8013218 <tcp_process+0x43c>
recv_acked--;
801320c: 4b66 ldr r3, [pc, #408] ; (80133a8 <tcp_process+0x5cc>)
801320e: 881b ldrh r3, [r3, #0]
8013210: 3b01 subs r3, #1
8013212: b29a uxth r2, r3
8013214: 4b64 ldr r3, [pc, #400] ; (80133a8 <tcp_process+0x5cc>)
8013216: 801a strh r2, [r3, #0]
}
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
8013218: 687b ldr r3, [r7, #4]
801321a: 8e5b ldrh r3, [r3, #50] ; 0x32
801321c: 009a lsls r2, r3, #2
801321e: 687b ldr r3, [r7, #4]
8013220: 8e5b ldrh r3, [r3, #50] ; 0x32
8013222: 005b lsls r3, r3, #1
8013224: f241 111c movw r1, #4380 ; 0x111c
8013228: 428b cmp r3, r1
801322a: bf38 it cc
801322c: 460b movcc r3, r1
801322e: 429a cmp r2, r3
8013230: d204 bcs.n 801323c <tcp_process+0x460>
8013232: 687b ldr r3, [r7, #4]
8013234: 8e5b ldrh r3, [r3, #50] ; 0x32
8013236: 009b lsls r3, r3, #2
8013238: b29b uxth r3, r3
801323a: e00d b.n 8013258 <tcp_process+0x47c>
801323c: 687b ldr r3, [r7, #4]
801323e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013240: 005b lsls r3, r3, #1
8013242: f241 121c movw r2, #4380 ; 0x111c
8013246: 4293 cmp r3, r2
8013248: d904 bls.n 8013254 <tcp_process+0x478>
801324a: 687b ldr r3, [r7, #4]
801324c: 8e5b ldrh r3, [r3, #50] ; 0x32
801324e: 005b lsls r3, r3, #1
8013250: b29b uxth r3, r3
8013252: e001 b.n 8013258 <tcp_process+0x47c>
8013254: f241 131c movw r3, #4380 ; 0x111c
8013258: 687a ldr r2, [r7, #4]
801325a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
if (recv_flags & TF_GOT_FIN) {
801325e: 4b53 ldr r3, [pc, #332] ; (80133ac <tcp_process+0x5d0>)
8013260: 781b ldrb r3, [r3, #0]
8013262: f003 0320 and.w r3, r3, #32
8013266: 2b00 cmp r3, #0
8013268: d037 beq.n 80132da <tcp_process+0x4fe>
tcp_ack_now(pcb);
801326a: 687b ldr r3, [r7, #4]
801326c: 8b5b ldrh r3, [r3, #26]
801326e: f043 0302 orr.w r3, r3, #2
8013272: b29a uxth r2, r3
8013274: 687b ldr r3, [r7, #4]
8013276: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
8013278: 687b ldr r3, [r7, #4]
801327a: 2207 movs r2, #7
801327c: 751a strb r2, [r3, #20]
if (recv_flags & TF_GOT_FIN) {
801327e: e02c b.n 80132da <tcp_process+0x4fe>
}
} else {
/* incorrect ACK number, send RST */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013280: 4b40 ldr r3, [pc, #256] ; (8013384 <tcp_process+0x5a8>)
8013282: 6819 ldr r1, [r3, #0]
8013284: 4b40 ldr r3, [pc, #256] ; (8013388 <tcp_process+0x5ac>)
8013286: 881b ldrh r3, [r3, #0]
8013288: 461a mov r2, r3
801328a: 4b40 ldr r3, [pc, #256] ; (801338c <tcp_process+0x5b0>)
801328c: 681b ldr r3, [r3, #0]
801328e: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013290: 4b3f ldr r3, [pc, #252] ; (8013390 <tcp_process+0x5b4>)
8013292: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013294: 885b ldrh r3, [r3, #2]
8013296: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013298: 4a3d ldr r2, [pc, #244] ; (8013390 <tcp_process+0x5b4>)
801329a: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
801329c: 8812 ldrh r2, [r2, #0]
801329e: b292 uxth r2, r2
80132a0: 9202 str r2, [sp, #8]
80132a2: 9301 str r3, [sp, #4]
80132a4: 4b3b ldr r3, [pc, #236] ; (8013394 <tcp_process+0x5b8>)
80132a6: 9300 str r3, [sp, #0]
80132a8: 4b3b ldr r3, [pc, #236] ; (8013398 <tcp_process+0x5bc>)
80132aa: 4602 mov r2, r0
80132ac: 6878 ldr r0, [r7, #4]
80132ae: f002 fbdf bl 8015a70 <tcp_rst>
}
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
/* Looks like another copy of the SYN - retransmit our SYN-ACK */
tcp_rexmit(pcb);
}
break;
80132b2: e167 b.n 8013584 <tcp_process+0x7a8>
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
80132b4: 4b32 ldr r3, [pc, #200] ; (8013380 <tcp_process+0x5a4>)
80132b6: 781b ldrb r3, [r3, #0]
80132b8: f003 0302 and.w r3, r3, #2
80132bc: 2b00 cmp r3, #0
80132be: f000 8161 beq.w 8013584 <tcp_process+0x7a8>
80132c2: 687b ldr r3, [r7, #4]
80132c4: 6a5b ldr r3, [r3, #36] ; 0x24
80132c6: 1e5a subs r2, r3, #1
80132c8: 4b30 ldr r3, [pc, #192] ; (801338c <tcp_process+0x5b0>)
80132ca: 681b ldr r3, [r3, #0]
80132cc: 429a cmp r2, r3
80132ce: f040 8159 bne.w 8013584 <tcp_process+0x7a8>
tcp_rexmit(pcb);
80132d2: 6878 ldr r0, [r7, #4]
80132d4: f002 f9b8 bl 8015648 <tcp_rexmit>
break;
80132d8: e154 b.n 8013584 <tcp_process+0x7a8>
80132da: e153 b.n 8013584 <tcp_process+0x7a8>
case CLOSE_WAIT:
/* FALLTHROUGH */
case ESTABLISHED:
tcp_receive(pcb);
80132dc: 6878 ldr r0, [r7, #4]
80132de: f000 fa71 bl 80137c4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) { /* passive close */
80132e2: 4b32 ldr r3, [pc, #200] ; (80133ac <tcp_process+0x5d0>)
80132e4: 781b ldrb r3, [r3, #0]
80132e6: f003 0320 and.w r3, r3, #32
80132ea: 2b00 cmp r3, #0
80132ec: f000 814c beq.w 8013588 <tcp_process+0x7ac>
tcp_ack_now(pcb);
80132f0: 687b ldr r3, [r7, #4]
80132f2: 8b5b ldrh r3, [r3, #26]
80132f4: f043 0302 orr.w r3, r3, #2
80132f8: b29a uxth r2, r3
80132fa: 687b ldr r3, [r7, #4]
80132fc: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
80132fe: 687b ldr r3, [r7, #4]
8013300: 2207 movs r2, #7
8013302: 751a strb r2, [r3, #20]
}
break;
8013304: e140 b.n 8013588 <tcp_process+0x7ac>
case FIN_WAIT_1:
tcp_receive(pcb);
8013306: 6878 ldr r0, [r7, #4]
8013308: f000 fa5c bl 80137c4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
801330c: 4b27 ldr r3, [pc, #156] ; (80133ac <tcp_process+0x5d0>)
801330e: 781b ldrb r3, [r3, #0]
8013310: f003 0320 and.w r3, r3, #32
8013314: 2b00 cmp r3, #0
8013316: d071 beq.n 80133fc <tcp_process+0x620>
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
8013318: 4b19 ldr r3, [pc, #100] ; (8013380 <tcp_process+0x5a4>)
801331a: 781b ldrb r3, [r3, #0]
801331c: f003 0310 and.w r3, r3, #16
8013320: 2b00 cmp r3, #0
8013322: d060 beq.n 80133e6 <tcp_process+0x60a>
8013324: 687b ldr r3, [r7, #4]
8013326: 6d1a ldr r2, [r3, #80] ; 0x50
8013328: 4b16 ldr r3, [pc, #88] ; (8013384 <tcp_process+0x5a8>)
801332a: 681b ldr r3, [r3, #0]
801332c: 429a cmp r2, r3
801332e: d15a bne.n 80133e6 <tcp_process+0x60a>
pcb->unsent == NULL) {
8013330: 687b ldr r3, [r7, #4]
8013332: 6edb ldr r3, [r3, #108] ; 0x6c
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
8013334: 2b00 cmp r3, #0
8013336: d156 bne.n 80133e6 <tcp_process+0x60a>
LWIP_DEBUGF(TCP_DEBUG,
("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
8013338: 687b ldr r3, [r7, #4]
801333a: 8b5b ldrh r3, [r3, #26]
801333c: f043 0302 orr.w r3, r3, #2
8013340: b29a uxth r2, r3
8013342: 687b ldr r3, [r7, #4]
8013344: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
8013346: 6878 ldr r0, [r7, #4]
8013348: f7fe fdbe bl 8011ec8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
801334c: 4b18 ldr r3, [pc, #96] ; (80133b0 <tcp_process+0x5d4>)
801334e: 681b ldr r3, [r3, #0]
8013350: 687a ldr r2, [r7, #4]
8013352: 429a cmp r2, r3
8013354: d105 bne.n 8013362 <tcp_process+0x586>
8013356: 4b16 ldr r3, [pc, #88] ; (80133b0 <tcp_process+0x5d4>)
8013358: 681b ldr r3, [r3, #0]
801335a: 68db ldr r3, [r3, #12]
801335c: 4a14 ldr r2, [pc, #80] ; (80133b0 <tcp_process+0x5d4>)
801335e: 6013 str r3, [r2, #0]
8013360: e02e b.n 80133c0 <tcp_process+0x5e4>
8013362: 4b13 ldr r3, [pc, #76] ; (80133b0 <tcp_process+0x5d4>)
8013364: 681b ldr r3, [r3, #0]
8013366: 617b str r3, [r7, #20]
8013368: e027 b.n 80133ba <tcp_process+0x5de>
801336a: 697b ldr r3, [r7, #20]
801336c: 68db ldr r3, [r3, #12]
801336e: 687a ldr r2, [r7, #4]
8013370: 429a cmp r2, r3
8013372: d11f bne.n 80133b4 <tcp_process+0x5d8>
8013374: 687b ldr r3, [r7, #4]
8013376: 68da ldr r2, [r3, #12]
8013378: 697b ldr r3, [r7, #20]
801337a: 60da str r2, [r3, #12]
801337c: e020 b.n 80133c0 <tcp_process+0x5e4>
801337e: bf00 nop
8013380: 20008758 .word 0x20008758
8013384: 20008750 .word 0x20008750
8013388: 20008756 .word 0x20008756
801338c: 2000874c .word 0x2000874c
8013390: 2000873c .word 0x2000873c
8013394: 2000be9c .word 0x2000be9c
8013398: 2000bea0 .word 0x2000bea0
801339c: 0801d2b0 .word 0x0801d2b0
80133a0: 0801d550 .word 0x0801d550
80133a4: 0801d2fc .word 0x0801d2fc
80133a8: 20008754 .word 0x20008754
80133ac: 20008759 .word 0x20008759
80133b0: 2000f5c0 .word 0x2000f5c0
80133b4: 697b ldr r3, [r7, #20]
80133b6: 68db ldr r3, [r3, #12]
80133b8: 617b str r3, [r7, #20]
80133ba: 697b ldr r3, [r7, #20]
80133bc: 2b00 cmp r3, #0
80133be: d1d4 bne.n 801336a <tcp_process+0x58e>
80133c0: 687b ldr r3, [r7, #4]
80133c2: 2200 movs r2, #0
80133c4: 60da str r2, [r3, #12]
80133c6: 4b77 ldr r3, [pc, #476] ; (80135a4 <tcp_process+0x7c8>)
80133c8: 2201 movs r2, #1
80133ca: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
80133cc: 687b ldr r3, [r7, #4]
80133ce: 220a movs r2, #10
80133d0: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
80133d2: 4b75 ldr r3, [pc, #468] ; (80135a8 <tcp_process+0x7cc>)
80133d4: 681a ldr r2, [r3, #0]
80133d6: 687b ldr r3, [r7, #4]
80133d8: 60da str r2, [r3, #12]
80133da: 4a73 ldr r2, [pc, #460] ; (80135a8 <tcp_process+0x7cc>)
80133dc: 687b ldr r3, [r7, #4]
80133de: 6013 str r3, [r2, #0]
80133e0: f002 fd08 bl 8015df4 <tcp_timer_needed>
}
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
pcb->unsent == NULL) {
pcb->state = FIN_WAIT_2;
}
break;
80133e4: e0d2 b.n 801358c <tcp_process+0x7b0>
tcp_ack_now(pcb);
80133e6: 687b ldr r3, [r7, #4]
80133e8: 8b5b ldrh r3, [r3, #26]
80133ea: f043 0302 orr.w r3, r3, #2
80133ee: b29a uxth r2, r3
80133f0: 687b ldr r3, [r7, #4]
80133f2: 835a strh r2, [r3, #26]
pcb->state = CLOSING;
80133f4: 687b ldr r3, [r7, #4]
80133f6: 2208 movs r2, #8
80133f8: 751a strb r2, [r3, #20]
break;
80133fa: e0c7 b.n 801358c <tcp_process+0x7b0>
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
80133fc: 4b6b ldr r3, [pc, #428] ; (80135ac <tcp_process+0x7d0>)
80133fe: 781b ldrb r3, [r3, #0]
8013400: f003 0310 and.w r3, r3, #16
8013404: 2b00 cmp r3, #0
8013406: f000 80c1 beq.w 801358c <tcp_process+0x7b0>
801340a: 687b ldr r3, [r7, #4]
801340c: 6d1a ldr r2, [r3, #80] ; 0x50
801340e: 4b68 ldr r3, [pc, #416] ; (80135b0 <tcp_process+0x7d4>)
8013410: 681b ldr r3, [r3, #0]
8013412: 429a cmp r2, r3
8013414: f040 80ba bne.w 801358c <tcp_process+0x7b0>
pcb->unsent == NULL) {
8013418: 687b ldr r3, [r7, #4]
801341a: 6edb ldr r3, [r3, #108] ; 0x6c
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
801341c: 2b00 cmp r3, #0
801341e: f040 80b5 bne.w 801358c <tcp_process+0x7b0>
pcb->state = FIN_WAIT_2;
8013422: 687b ldr r3, [r7, #4]
8013424: 2206 movs r2, #6
8013426: 751a strb r2, [r3, #20]
break;
8013428: e0b0 b.n 801358c <tcp_process+0x7b0>
case FIN_WAIT_2:
tcp_receive(pcb);
801342a: 6878 ldr r0, [r7, #4]
801342c: f000 f9ca bl 80137c4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
8013430: 4b60 ldr r3, [pc, #384] ; (80135b4 <tcp_process+0x7d8>)
8013432: 781b ldrb r3, [r3, #0]
8013434: f003 0320 and.w r3, r3, #32
8013438: 2b00 cmp r3, #0
801343a: f000 80a9 beq.w 8013590 <tcp_process+0x7b4>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
801343e: 687b ldr r3, [r7, #4]
8013440: 8b5b ldrh r3, [r3, #26]
8013442: f043 0302 orr.w r3, r3, #2
8013446: b29a uxth r2, r3
8013448: 687b ldr r3, [r7, #4]
801344a: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
801344c: 6878 ldr r0, [r7, #4]
801344e: f7fe fd3b bl 8011ec8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8013452: 4b59 ldr r3, [pc, #356] ; (80135b8 <tcp_process+0x7dc>)
8013454: 681b ldr r3, [r3, #0]
8013456: 687a ldr r2, [r7, #4]
8013458: 429a cmp r2, r3
801345a: d105 bne.n 8013468 <tcp_process+0x68c>
801345c: 4b56 ldr r3, [pc, #344] ; (80135b8 <tcp_process+0x7dc>)
801345e: 681b ldr r3, [r3, #0]
8013460: 68db ldr r3, [r3, #12]
8013462: 4a55 ldr r2, [pc, #340] ; (80135b8 <tcp_process+0x7dc>)
8013464: 6013 str r3, [r2, #0]
8013466: e013 b.n 8013490 <tcp_process+0x6b4>
8013468: 4b53 ldr r3, [pc, #332] ; (80135b8 <tcp_process+0x7dc>)
801346a: 681b ldr r3, [r3, #0]
801346c: 613b str r3, [r7, #16]
801346e: e00c b.n 801348a <tcp_process+0x6ae>
8013470: 693b ldr r3, [r7, #16]
8013472: 68db ldr r3, [r3, #12]
8013474: 687a ldr r2, [r7, #4]
8013476: 429a cmp r2, r3
8013478: d104 bne.n 8013484 <tcp_process+0x6a8>
801347a: 687b ldr r3, [r7, #4]
801347c: 68da ldr r2, [r3, #12]
801347e: 693b ldr r3, [r7, #16]
8013480: 60da str r2, [r3, #12]
8013482: e005 b.n 8013490 <tcp_process+0x6b4>
8013484: 693b ldr r3, [r7, #16]
8013486: 68db ldr r3, [r3, #12]
8013488: 613b str r3, [r7, #16]
801348a: 693b ldr r3, [r7, #16]
801348c: 2b00 cmp r3, #0
801348e: d1ef bne.n 8013470 <tcp_process+0x694>
8013490: 687b ldr r3, [r7, #4]
8013492: 2200 movs r2, #0
8013494: 60da str r2, [r3, #12]
8013496: 4b43 ldr r3, [pc, #268] ; (80135a4 <tcp_process+0x7c8>)
8013498: 2201 movs r2, #1
801349a: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
801349c: 687b ldr r3, [r7, #4]
801349e: 220a movs r2, #10
80134a0: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
80134a2: 4b41 ldr r3, [pc, #260] ; (80135a8 <tcp_process+0x7cc>)
80134a4: 681a ldr r2, [r3, #0]
80134a6: 687b ldr r3, [r7, #4]
80134a8: 60da str r2, [r3, #12]
80134aa: 4a3f ldr r2, [pc, #252] ; (80135a8 <tcp_process+0x7cc>)
80134ac: 687b ldr r3, [r7, #4]
80134ae: 6013 str r3, [r2, #0]
80134b0: f002 fca0 bl 8015df4 <tcp_timer_needed>
}
break;
80134b4: e06c b.n 8013590 <tcp_process+0x7b4>
case CLOSING:
tcp_receive(pcb);
80134b6: 6878 ldr r0, [r7, #4]
80134b8: f000 f984 bl 80137c4 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
80134bc: 4b3b ldr r3, [pc, #236] ; (80135ac <tcp_process+0x7d0>)
80134be: 781b ldrb r3, [r3, #0]
80134c0: f003 0310 and.w r3, r3, #16
80134c4: 2b00 cmp r3, #0
80134c6: d065 beq.n 8013594 <tcp_process+0x7b8>
80134c8: 687b ldr r3, [r7, #4]
80134ca: 6d1a ldr r2, [r3, #80] ; 0x50
80134cc: 4b38 ldr r3, [pc, #224] ; (80135b0 <tcp_process+0x7d4>)
80134ce: 681b ldr r3, [r3, #0]
80134d0: 429a cmp r2, r3
80134d2: d15f bne.n 8013594 <tcp_process+0x7b8>
80134d4: 687b ldr r3, [r7, #4]
80134d6: 6edb ldr r3, [r3, #108] ; 0x6c
80134d8: 2b00 cmp r3, #0
80134da: d15b bne.n 8013594 <tcp_process+0x7b8>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_pcb_purge(pcb);
80134dc: 6878 ldr r0, [r7, #4]
80134de: f7fe fcf3 bl 8011ec8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
80134e2: 4b35 ldr r3, [pc, #212] ; (80135b8 <tcp_process+0x7dc>)
80134e4: 681b ldr r3, [r3, #0]
80134e6: 687a ldr r2, [r7, #4]
80134e8: 429a cmp r2, r3
80134ea: d105 bne.n 80134f8 <tcp_process+0x71c>
80134ec: 4b32 ldr r3, [pc, #200] ; (80135b8 <tcp_process+0x7dc>)
80134ee: 681b ldr r3, [r3, #0]
80134f0: 68db ldr r3, [r3, #12]
80134f2: 4a31 ldr r2, [pc, #196] ; (80135b8 <tcp_process+0x7dc>)
80134f4: 6013 str r3, [r2, #0]
80134f6: e013 b.n 8013520 <tcp_process+0x744>
80134f8: 4b2f ldr r3, [pc, #188] ; (80135b8 <tcp_process+0x7dc>)
80134fa: 681b ldr r3, [r3, #0]
80134fc: 60fb str r3, [r7, #12]
80134fe: e00c b.n 801351a <tcp_process+0x73e>
8013500: 68fb ldr r3, [r7, #12]
8013502: 68db ldr r3, [r3, #12]
8013504: 687a ldr r2, [r7, #4]
8013506: 429a cmp r2, r3
8013508: d104 bne.n 8013514 <tcp_process+0x738>
801350a: 687b ldr r3, [r7, #4]
801350c: 68da ldr r2, [r3, #12]
801350e: 68fb ldr r3, [r7, #12]
8013510: 60da str r2, [r3, #12]
8013512: e005 b.n 8013520 <tcp_process+0x744>
8013514: 68fb ldr r3, [r7, #12]
8013516: 68db ldr r3, [r3, #12]
8013518: 60fb str r3, [r7, #12]
801351a: 68fb ldr r3, [r7, #12]
801351c: 2b00 cmp r3, #0
801351e: d1ef bne.n 8013500 <tcp_process+0x724>
8013520: 687b ldr r3, [r7, #4]
8013522: 2200 movs r2, #0
8013524: 60da str r2, [r3, #12]
8013526: 4b1f ldr r3, [pc, #124] ; (80135a4 <tcp_process+0x7c8>)
8013528: 2201 movs r2, #1
801352a: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
801352c: 687b ldr r3, [r7, #4]
801352e: 220a movs r2, #10
8013530: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
8013532: 4b1d ldr r3, [pc, #116] ; (80135a8 <tcp_process+0x7cc>)
8013534: 681a ldr r2, [r3, #0]
8013536: 687b ldr r3, [r7, #4]
8013538: 60da str r2, [r3, #12]
801353a: 4a1b ldr r2, [pc, #108] ; (80135a8 <tcp_process+0x7cc>)
801353c: 687b ldr r3, [r7, #4]
801353e: 6013 str r3, [r2, #0]
8013540: f002 fc58 bl 8015df4 <tcp_timer_needed>
}
break;
8013544: e026 b.n 8013594 <tcp_process+0x7b8>
case LAST_ACK:
tcp_receive(pcb);
8013546: 6878 ldr r0, [r7, #4]
8013548: f000 f93c bl 80137c4 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
801354c: 4b17 ldr r3, [pc, #92] ; (80135ac <tcp_process+0x7d0>)
801354e: 781b ldrb r3, [r3, #0]
8013550: f003 0310 and.w r3, r3, #16
8013554: 2b00 cmp r3, #0
8013556: d01f beq.n 8013598 <tcp_process+0x7bc>
8013558: 687b ldr r3, [r7, #4]
801355a: 6d1a ldr r2, [r3, #80] ; 0x50
801355c: 4b14 ldr r3, [pc, #80] ; (80135b0 <tcp_process+0x7d4>)
801355e: 681b ldr r3, [r3, #0]
8013560: 429a cmp r2, r3
8013562: d119 bne.n 8013598 <tcp_process+0x7bc>
8013564: 687b ldr r3, [r7, #4]
8013566: 6edb ldr r3, [r3, #108] ; 0x6c
8013568: 2b00 cmp r3, #0
801356a: d115 bne.n 8013598 <tcp_process+0x7bc>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
/* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
recv_flags |= TF_CLOSED;
801356c: 4b11 ldr r3, [pc, #68] ; (80135b4 <tcp_process+0x7d8>)
801356e: 781b ldrb r3, [r3, #0]
8013570: f043 0310 orr.w r3, r3, #16
8013574: b2da uxtb r2, r3
8013576: 4b0f ldr r3, [pc, #60] ; (80135b4 <tcp_process+0x7d8>)
8013578: 701a strb r2, [r3, #0]
}
break;
801357a: e00d b.n 8013598 <tcp_process+0x7bc>
default:
break;
801357c: bf00 nop
801357e: e00c b.n 801359a <tcp_process+0x7be>
break;
8013580: bf00 nop
8013582: e00a b.n 801359a <tcp_process+0x7be>
break;
8013584: bf00 nop
8013586: e008 b.n 801359a <tcp_process+0x7be>
break;
8013588: bf00 nop
801358a: e006 b.n 801359a <tcp_process+0x7be>
break;
801358c: bf00 nop
801358e: e004 b.n 801359a <tcp_process+0x7be>
break;
8013590: bf00 nop
8013592: e002 b.n 801359a <tcp_process+0x7be>
break;
8013594: bf00 nop
8013596: e000 b.n 801359a <tcp_process+0x7be>
break;
8013598: bf00 nop
}
return ERR_OK;
801359a: 2300 movs r3, #0
}
801359c: 4618 mov r0, r3
801359e: 3724 adds r7, #36 ; 0x24
80135a0: 46bd mov sp, r7
80135a2: bd90 pop {r4, r7, pc}
80135a4: 2000f5bc .word 0x2000f5bc
80135a8: 2000f5d0 .word 0x2000f5d0
80135ac: 20008758 .word 0x20008758
80135b0: 20008750 .word 0x20008750
80135b4: 20008759 .word 0x20008759
80135b8: 2000f5c0 .word 0x2000f5c0
080135bc <tcp_oos_insert_segment>:
*
* Called from tcp_receive()
*/
static void
tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
{
80135bc: b590 push {r4, r7, lr}
80135be: b085 sub sp, #20
80135c0: af00 add r7, sp, #0
80135c2: 6078 str r0, [r7, #4]
80135c4: 6039 str r1, [r7, #0]
struct tcp_seg *old_seg;
LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
80135c6: 687b ldr r3, [r7, #4]
80135c8: 2b00 cmp r3, #0
80135ca: d106 bne.n 80135da <tcp_oos_insert_segment+0x1e>
80135cc: 4b3b ldr r3, [pc, #236] ; (80136bc <tcp_oos_insert_segment+0x100>)
80135ce: f240 421f movw r2, #1055 ; 0x41f
80135d2: 493b ldr r1, [pc, #236] ; (80136c0 <tcp_oos_insert_segment+0x104>)
80135d4: 483b ldr r0, [pc, #236] ; (80136c4 <tcp_oos_insert_segment+0x108>)
80135d6: f007 fd1d bl 801b014 <iprintf>
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
80135da: 687b ldr r3, [r7, #4]
80135dc: 68db ldr r3, [r3, #12]
80135de: 899b ldrh r3, [r3, #12]
80135e0: b29b uxth r3, r3
80135e2: 4618 mov r0, r3
80135e4: f7fb fc4c bl 800ee80 <lwip_htons>
80135e8: 4603 mov r3, r0
80135ea: b2db uxtb r3, r3
80135ec: f003 0301 and.w r3, r3, #1
80135f0: 2b00 cmp r3, #0
80135f2: d028 beq.n 8013646 <tcp_oos_insert_segment+0x8a>
/* received segment overlaps all following segments */
tcp_segs_free(next);
80135f4: 6838 ldr r0, [r7, #0]
80135f6: f7fe fa67 bl 8011ac8 <tcp_segs_free>
next = NULL;
80135fa: 2300 movs r3, #0
80135fc: 603b str r3, [r7, #0]
80135fe: e056 b.n 80136ae <tcp_oos_insert_segment+0xf2>
oos queue may have segments with FIN flag */
while (next &&
TCP_SEQ_GEQ((seqno + cseg->len),
(next->tcphdr->seqno + next->len))) {
/* cseg with FIN already processed */
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
8013600: 683b ldr r3, [r7, #0]
8013602: 68db ldr r3, [r3, #12]
8013604: 899b ldrh r3, [r3, #12]
8013606: b29b uxth r3, r3
8013608: 4618 mov r0, r3
801360a: f7fb fc39 bl 800ee80 <lwip_htons>
801360e: 4603 mov r3, r0
8013610: b2db uxtb r3, r3
8013612: f003 0301 and.w r3, r3, #1
8013616: 2b00 cmp r3, #0
8013618: d00d beq.n 8013636 <tcp_oos_insert_segment+0x7a>
TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
801361a: 687b ldr r3, [r7, #4]
801361c: 68db ldr r3, [r3, #12]
801361e: 899b ldrh r3, [r3, #12]
8013620: b29c uxth r4, r3
8013622: 2001 movs r0, #1
8013624: f7fb fc2c bl 800ee80 <lwip_htons>
8013628: 4603 mov r3, r0
801362a: 461a mov r2, r3
801362c: 687b ldr r3, [r7, #4]
801362e: 68db ldr r3, [r3, #12]
8013630: 4322 orrs r2, r4
8013632: b292 uxth r2, r2
8013634: 819a strh r2, [r3, #12]
}
old_seg = next;
8013636: 683b ldr r3, [r7, #0]
8013638: 60fb str r3, [r7, #12]
next = next->next;
801363a: 683b ldr r3, [r7, #0]
801363c: 681b ldr r3, [r3, #0]
801363e: 603b str r3, [r7, #0]
tcp_seg_free(old_seg);
8013640: 68f8 ldr r0, [r7, #12]
8013642: f7fe fa55 bl 8011af0 <tcp_seg_free>
while (next &&
8013646: 683b ldr r3, [r7, #0]
8013648: 2b00 cmp r3, #0
801364a: d00e beq.n 801366a <tcp_oos_insert_segment+0xae>
TCP_SEQ_GEQ((seqno + cseg->len),
801364c: 687b ldr r3, [r7, #4]
801364e: 891b ldrh r3, [r3, #8]
8013650: 461a mov r2, r3
8013652: 4b1d ldr r3, [pc, #116] ; (80136c8 <tcp_oos_insert_segment+0x10c>)
8013654: 681b ldr r3, [r3, #0]
8013656: 441a add r2, r3
8013658: 683b ldr r3, [r7, #0]
801365a: 68db ldr r3, [r3, #12]
801365c: 685b ldr r3, [r3, #4]
801365e: 6839 ldr r1, [r7, #0]
8013660: 8909 ldrh r1, [r1, #8]
8013662: 440b add r3, r1
8013664: 1ad3 subs r3, r2, r3
while (next &&
8013666: 2b00 cmp r3, #0
8013668: daca bge.n 8013600 <tcp_oos_insert_segment+0x44>
}
if (next &&
801366a: 683b ldr r3, [r7, #0]
801366c: 2b00 cmp r3, #0
801366e: d01e beq.n 80136ae <tcp_oos_insert_segment+0xf2>
TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
8013670: 687b ldr r3, [r7, #4]
8013672: 891b ldrh r3, [r3, #8]
8013674: 461a mov r2, r3
8013676: 4b14 ldr r3, [pc, #80] ; (80136c8 <tcp_oos_insert_segment+0x10c>)
8013678: 681b ldr r3, [r3, #0]
801367a: 441a add r2, r3
801367c: 683b ldr r3, [r7, #0]
801367e: 68db ldr r3, [r3, #12]
8013680: 685b ldr r3, [r3, #4]
8013682: 1ad3 subs r3, r2, r3
if (next &&
8013684: 2b00 cmp r3, #0
8013686: dd12 ble.n 80136ae <tcp_oos_insert_segment+0xf2>
/* We need to trim the incoming segment. */
cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
8013688: 683b ldr r3, [r7, #0]
801368a: 68db ldr r3, [r3, #12]
801368c: 685b ldr r3, [r3, #4]
801368e: b29a uxth r2, r3
8013690: 4b0d ldr r3, [pc, #52] ; (80136c8 <tcp_oos_insert_segment+0x10c>)
8013692: 681b ldr r3, [r3, #0]
8013694: b29b uxth r3, r3
8013696: 1ad3 subs r3, r2, r3
8013698: b29a uxth r2, r3
801369a: 687b ldr r3, [r7, #4]
801369c: 811a strh r2, [r3, #8]
pbuf_realloc(cseg->p, cseg->len);
801369e: 687b ldr r3, [r7, #4]
80136a0: 685a ldr r2, [r3, #4]
80136a2: 687b ldr r3, [r7, #4]
80136a4: 891b ldrh r3, [r3, #8]
80136a6: 4619 mov r1, r3
80136a8: 4610 mov r0, r2
80136aa: f7fc fe17 bl 80102dc <pbuf_realloc>
}
}
cseg->next = next;
80136ae: 687b ldr r3, [r7, #4]
80136b0: 683a ldr r2, [r7, #0]
80136b2: 601a str r2, [r3, #0]
}
80136b4: bf00 nop
80136b6: 3714 adds r7, #20
80136b8: 46bd mov sp, r7
80136ba: bd90 pop {r4, r7, pc}
80136bc: 0801d2b0 .word 0x0801d2b0
80136c0: 0801d570 .word 0x0801d570
80136c4: 0801d2fc .word 0x0801d2fc
80136c8: 2000874c .word 0x2000874c
080136cc <tcp_free_acked_segments>:
/** Remove segments from a list if the incoming ACK acknowledges them */
static struct tcp_seg *
tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
struct tcp_seg *dbg_other_seg_list)
{
80136cc: b5b0 push {r4, r5, r7, lr}
80136ce: b086 sub sp, #24
80136d0: af00 add r7, sp, #0
80136d2: 60f8 str r0, [r7, #12]
80136d4: 60b9 str r1, [r7, #8]
80136d6: 607a str r2, [r7, #4]
80136d8: 603b str r3, [r7, #0]
u16_t clen;
LWIP_UNUSED_ARG(dbg_list_name);
LWIP_UNUSED_ARG(dbg_other_seg_list);
while (seg_list != NULL &&
80136da: e03e b.n 801375a <tcp_free_acked_segments+0x8e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
lwip_ntohl(seg_list->tcphdr->seqno),
lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
dbg_list_name));
next = seg_list;
80136dc: 68bb ldr r3, [r7, #8]
80136de: 617b str r3, [r7, #20]
seg_list = seg_list->next;
80136e0: 68bb ldr r3, [r7, #8]
80136e2: 681b ldr r3, [r3, #0]
80136e4: 60bb str r3, [r7, #8]
clen = pbuf_clen(next->p);
80136e6: 697b ldr r3, [r7, #20]
80136e8: 685b ldr r3, [r3, #4]
80136ea: 4618 mov r0, r3
80136ec: f7fd f80a bl 8010704 <pbuf_clen>
80136f0: 4603 mov r3, r0
80136f2: 827b strh r3, [r7, #18]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
(tcpwnd_size_t)pcb->snd_queuelen));
LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
80136f4: 68fb ldr r3, [r7, #12]
80136f6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
80136fa: 8a7a ldrh r2, [r7, #18]
80136fc: 429a cmp r2, r3
80136fe: d906 bls.n 801370e <tcp_free_acked_segments+0x42>
8013700: 4b2a ldr r3, [pc, #168] ; (80137ac <tcp_free_acked_segments+0xe0>)
8013702: f240 4257 movw r2, #1111 ; 0x457
8013706: 492a ldr r1, [pc, #168] ; (80137b0 <tcp_free_acked_segments+0xe4>)
8013708: 482a ldr r0, [pc, #168] ; (80137b4 <tcp_free_acked_segments+0xe8>)
801370a: f007 fc83 bl 801b014 <iprintf>
pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
801370e: 68fb ldr r3, [r7, #12]
8013710: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66
8013714: 8a7b ldrh r3, [r7, #18]
8013716: 1ad3 subs r3, r2, r3
8013718: b29a uxth r2, r3
801371a: 68fb ldr r3, [r7, #12]
801371c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
8013720: 697b ldr r3, [r7, #20]
8013722: 891a ldrh r2, [r3, #8]
8013724: 4b24 ldr r3, [pc, #144] ; (80137b8 <tcp_free_acked_segments+0xec>)
8013726: 881b ldrh r3, [r3, #0]
8013728: 4413 add r3, r2
801372a: b29a uxth r2, r3
801372c: 4b22 ldr r3, [pc, #136] ; (80137b8 <tcp_free_acked_segments+0xec>)
801372e: 801a strh r2, [r3, #0]
tcp_seg_free(next);
8013730: 6978 ldr r0, [r7, #20]
8013732: f7fe f9dd bl 8011af0 <tcp_seg_free>
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
(tcpwnd_size_t)pcb->snd_queuelen,
dbg_list_name));
if (pcb->snd_queuelen != 0) {
8013736: 68fb ldr r3, [r7, #12]
8013738: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
801373c: 2b00 cmp r3, #0
801373e: d00c beq.n 801375a <tcp_free_acked_segments+0x8e>
LWIP_ASSERT("tcp_receive: valid queue length",
8013740: 68bb ldr r3, [r7, #8]
8013742: 2b00 cmp r3, #0
8013744: d109 bne.n 801375a <tcp_free_acked_segments+0x8e>
8013746: 683b ldr r3, [r7, #0]
8013748: 2b00 cmp r3, #0
801374a: d106 bne.n 801375a <tcp_free_acked_segments+0x8e>
801374c: 4b17 ldr r3, [pc, #92] ; (80137ac <tcp_free_acked_segments+0xe0>)
801374e: f240 4262 movw r2, #1122 ; 0x462
8013752: 491a ldr r1, [pc, #104] ; (80137bc <tcp_free_acked_segments+0xf0>)
8013754: 4817 ldr r0, [pc, #92] ; (80137b4 <tcp_free_acked_segments+0xe8>)
8013756: f007 fc5d bl 801b014 <iprintf>
while (seg_list != NULL &&
801375a: 68bb ldr r3, [r7, #8]
801375c: 2b00 cmp r3, #0
801375e: d020 beq.n 80137a2 <tcp_free_acked_segments+0xd6>
TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
8013760: 68bb ldr r3, [r7, #8]
8013762: 68db ldr r3, [r3, #12]
8013764: 685b ldr r3, [r3, #4]
8013766: 4618 mov r0, r3
8013768: f7fb fb9f bl 800eeaa <lwip_htonl>
801376c: 4604 mov r4, r0
801376e: 68bb ldr r3, [r7, #8]
8013770: 891b ldrh r3, [r3, #8]
8013772: 461d mov r5, r3
8013774: 68bb ldr r3, [r7, #8]
8013776: 68db ldr r3, [r3, #12]
8013778: 899b ldrh r3, [r3, #12]
801377a: b29b uxth r3, r3
801377c: 4618 mov r0, r3
801377e: f7fb fb7f bl 800ee80 <lwip_htons>
8013782: 4603 mov r3, r0
8013784: b2db uxtb r3, r3
8013786: f003 0303 and.w r3, r3, #3
801378a: 2b00 cmp r3, #0
801378c: d001 beq.n 8013792 <tcp_free_acked_segments+0xc6>
801378e: 2301 movs r3, #1
8013790: e000 b.n 8013794 <tcp_free_acked_segments+0xc8>
8013792: 2300 movs r3, #0
8013794: 442b add r3, r5
8013796: 18e2 adds r2, r4, r3
8013798: 4b09 ldr r3, [pc, #36] ; (80137c0 <tcp_free_acked_segments+0xf4>)
801379a: 681b ldr r3, [r3, #0]
801379c: 1ad3 subs r3, r2, r3
while (seg_list != NULL &&
801379e: 2b00 cmp r3, #0
80137a0: dd9c ble.n 80136dc <tcp_free_acked_segments+0x10>
seg_list != NULL || dbg_other_seg_list != NULL);
}
}
return seg_list;
80137a2: 68bb ldr r3, [r7, #8]
}
80137a4: 4618 mov r0, r3
80137a6: 3718 adds r7, #24
80137a8: 46bd mov sp, r7
80137aa: bdb0 pop {r4, r5, r7, pc}
80137ac: 0801d2b0 .word 0x0801d2b0
80137b0: 0801d598 .word 0x0801d598
80137b4: 0801d2fc .word 0x0801d2fc
80137b8: 20008754 .word 0x20008754
80137bc: 0801d5c0 .word 0x0801d5c0
80137c0: 20008750 .word 0x20008750
080137c4 <tcp_receive>:
*
* Called from tcp_process().
*/
static void
tcp_receive(struct tcp_pcb *pcb)
{
80137c4: b5b0 push {r4, r5, r7, lr}
80137c6: b094 sub sp, #80 ; 0x50
80137c8: af00 add r7, sp, #0
80137ca: 6078 str r0, [r7, #4]
s16_t m;
u32_t right_wnd_edge;
int found_dupack = 0;
80137cc: 2300 movs r3, #0
80137ce: 64bb str r3, [r7, #72] ; 0x48
LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
80137d0: 687b ldr r3, [r7, #4]
80137d2: 2b00 cmp r3, #0
80137d4: d106 bne.n 80137e4 <tcp_receive+0x20>
80137d6: 4ba6 ldr r3, [pc, #664] ; (8013a70 <tcp_receive+0x2ac>)
80137d8: f240 427b movw r2, #1147 ; 0x47b
80137dc: 49a5 ldr r1, [pc, #660] ; (8013a74 <tcp_receive+0x2b0>)
80137de: 48a6 ldr r0, [pc, #664] ; (8013a78 <tcp_receive+0x2b4>)
80137e0: f007 fc18 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
80137e4: 687b ldr r3, [r7, #4]
80137e6: 7d1b ldrb r3, [r3, #20]
80137e8: 2b03 cmp r3, #3
80137ea: d806 bhi.n 80137fa <tcp_receive+0x36>
80137ec: 4ba0 ldr r3, [pc, #640] ; (8013a70 <tcp_receive+0x2ac>)
80137ee: f240 427c movw r2, #1148 ; 0x47c
80137f2: 49a2 ldr r1, [pc, #648] ; (8013a7c <tcp_receive+0x2b8>)
80137f4: 48a0 ldr r0, [pc, #640] ; (8013a78 <tcp_receive+0x2b4>)
80137f6: f007 fc0d bl 801b014 <iprintf>
if (flags & TCP_ACK) {
80137fa: 4ba1 ldr r3, [pc, #644] ; (8013a80 <tcp_receive+0x2bc>)
80137fc: 781b ldrb r3, [r3, #0]
80137fe: f003 0310 and.w r3, r3, #16
8013802: 2b00 cmp r3, #0
8013804: f000 8263 beq.w 8013cce <tcp_receive+0x50a>
right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
8013808: 687b ldr r3, [r7, #4]
801380a: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
801380e: 461a mov r2, r3
8013810: 687b ldr r3, [r7, #4]
8013812: 6d9b ldr r3, [r3, #88] ; 0x58
8013814: 4413 add r3, r2
8013816: 633b str r3, [r7, #48] ; 0x30
/* Update window. */
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
8013818: 687b ldr r3, [r7, #4]
801381a: 6d5a ldr r2, [r3, #84] ; 0x54
801381c: 4b99 ldr r3, [pc, #612] ; (8013a84 <tcp_receive+0x2c0>)
801381e: 681b ldr r3, [r3, #0]
8013820: 1ad3 subs r3, r2, r3
8013822: 2b00 cmp r3, #0
8013824: db1b blt.n 801385e <tcp_receive+0x9a>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013826: 687b ldr r3, [r7, #4]
8013828: 6d5a ldr r2, [r3, #84] ; 0x54
801382a: 4b96 ldr r3, [pc, #600] ; (8013a84 <tcp_receive+0x2c0>)
801382c: 681b ldr r3, [r3, #0]
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
801382e: 429a cmp r2, r3
8013830: d106 bne.n 8013840 <tcp_receive+0x7c>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013832: 687b ldr r3, [r7, #4]
8013834: 6d9a ldr r2, [r3, #88] ; 0x58
8013836: 4b94 ldr r3, [pc, #592] ; (8013a88 <tcp_receive+0x2c4>)
8013838: 681b ldr r3, [r3, #0]
801383a: 1ad3 subs r3, r2, r3
801383c: 2b00 cmp r3, #0
801383e: db0e blt.n 801385e <tcp_receive+0x9a>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
8013840: 687b ldr r3, [r7, #4]
8013842: 6d9a ldr r2, [r3, #88] ; 0x58
8013844: 4b90 ldr r3, [pc, #576] ; (8013a88 <tcp_receive+0x2c4>)
8013846: 681b ldr r3, [r3, #0]
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013848: 429a cmp r2, r3
801384a: d125 bne.n 8013898 <tcp_receive+0xd4>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
801384c: 4b8f ldr r3, [pc, #572] ; (8013a8c <tcp_receive+0x2c8>)
801384e: 681b ldr r3, [r3, #0]
8013850: 89db ldrh r3, [r3, #14]
8013852: b29a uxth r2, r3
8013854: 687b ldr r3, [r7, #4]
8013856: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
801385a: 429a cmp r2, r3
801385c: d91c bls.n 8013898 <tcp_receive+0xd4>
pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
801385e: 4b8b ldr r3, [pc, #556] ; (8013a8c <tcp_receive+0x2c8>)
8013860: 681b ldr r3, [r3, #0]
8013862: 89db ldrh r3, [r3, #14]
8013864: b29a uxth r2, r3
8013866: 687b ldr r3, [r7, #4]
8013868: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
/* keep track of the biggest window announced by the remote host to calculate
the maximum segment size */
if (pcb->snd_wnd_max < pcb->snd_wnd) {
801386c: 687b ldr r3, [r7, #4]
801386e: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62
8013872: 687b ldr r3, [r7, #4]
8013874: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8013878: 429a cmp r2, r3
801387a: d205 bcs.n 8013888 <tcp_receive+0xc4>
pcb->snd_wnd_max = pcb->snd_wnd;
801387c: 687b ldr r3, [r7, #4]
801387e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8013882: 687b ldr r3, [r7, #4]
8013884: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
}
pcb->snd_wl1 = seqno;
8013888: 4b7e ldr r3, [pc, #504] ; (8013a84 <tcp_receive+0x2c0>)
801388a: 681a ldr r2, [r3, #0]
801388c: 687b ldr r3, [r7, #4]
801388e: 655a str r2, [r3, #84] ; 0x54
pcb->snd_wl2 = ackno;
8013890: 4b7d ldr r3, [pc, #500] ; (8013a88 <tcp_receive+0x2c4>)
8013892: 681a ldr r2, [r3, #0]
8013894: 687b ldr r3, [r7, #4]
8013896: 659a str r2, [r3, #88] ; 0x58
* If it only passes 1, should reset dupack counter
*
*/
/* Clause 1 */
if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
8013898: 4b7b ldr r3, [pc, #492] ; (8013a88 <tcp_receive+0x2c4>)
801389a: 681a ldr r2, [r3, #0]
801389c: 687b ldr r3, [r7, #4]
801389e: 6c5b ldr r3, [r3, #68] ; 0x44
80138a0: 1ad3 subs r3, r2, r3
80138a2: 2b00 cmp r3, #0
80138a4: dc58 bgt.n 8013958 <tcp_receive+0x194>
/* Clause 2 */
if (tcplen == 0) {
80138a6: 4b7a ldr r3, [pc, #488] ; (8013a90 <tcp_receive+0x2cc>)
80138a8: 881b ldrh r3, [r3, #0]
80138aa: 2b00 cmp r3, #0
80138ac: d14b bne.n 8013946 <tcp_receive+0x182>
/* Clause 3 */
if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
80138ae: 687b ldr r3, [r7, #4]
80138b0: 6d9b ldr r3, [r3, #88] ; 0x58
80138b2: 687a ldr r2, [r7, #4]
80138b4: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60
80138b8: 4413 add r3, r2
80138ba: 6b3a ldr r2, [r7, #48] ; 0x30
80138bc: 429a cmp r2, r3
80138be: d142 bne.n 8013946 <tcp_receive+0x182>
/* Clause 4 */
if (pcb->rtime >= 0) {
80138c0: 687b ldr r3, [r7, #4]
80138c2: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80138c6: 2b00 cmp r3, #0
80138c8: db3d blt.n 8013946 <tcp_receive+0x182>
/* Clause 5 */
if (pcb->lastack == ackno) {
80138ca: 687b ldr r3, [r7, #4]
80138cc: 6c5a ldr r2, [r3, #68] ; 0x44
80138ce: 4b6e ldr r3, [pc, #440] ; (8013a88 <tcp_receive+0x2c4>)
80138d0: 681b ldr r3, [r3, #0]
80138d2: 429a cmp r2, r3
80138d4: d137 bne.n 8013946 <tcp_receive+0x182>
found_dupack = 1;
80138d6: 2301 movs r3, #1
80138d8: 64bb str r3, [r7, #72] ; 0x48
if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
80138da: 687b ldr r3, [r7, #4]
80138dc: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138e0: 2bff cmp r3, #255 ; 0xff
80138e2: d007 beq.n 80138f4 <tcp_receive+0x130>
++pcb->dupacks;
80138e4: 687b ldr r3, [r7, #4]
80138e6: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138ea: 3301 adds r3, #1
80138ec: b2da uxtb r2, r3
80138ee: 687b ldr r3, [r7, #4]
80138f0: f883 2043 strb.w r2, [r3, #67] ; 0x43
}
if (pcb->dupacks > 3) {
80138f4: 687b ldr r3, [r7, #4]
80138f6: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138fa: 2b03 cmp r3, #3
80138fc: d91b bls.n 8013936 <tcp_receive+0x172>
/* Inflate the congestion window */
TCP_WND_INC(pcb->cwnd, pcb->mss);
80138fe: 687b ldr r3, [r7, #4]
8013900: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013904: 687b ldr r3, [r7, #4]
8013906: 8e5b ldrh r3, [r3, #50] ; 0x32
8013908: 4413 add r3, r2
801390a: b29a uxth r2, r3
801390c: 687b ldr r3, [r7, #4]
801390e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013912: 429a cmp r2, r3
8013914: d30a bcc.n 801392c <tcp_receive+0x168>
8013916: 687b ldr r3, [r7, #4]
8013918: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
801391c: 687b ldr r3, [r7, #4]
801391e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013920: 4413 add r3, r2
8013922: b29a uxth r2, r3
8013924: 687b ldr r3, [r7, #4]
8013926: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
801392a: e004 b.n 8013936 <tcp_receive+0x172>
801392c: 687b ldr r3, [r7, #4]
801392e: f64f 72ff movw r2, #65535 ; 0xffff
8013932: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
}
if (pcb->dupacks >= 3) {
8013936: 687b ldr r3, [r7, #4]
8013938: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
801393c: 2b02 cmp r3, #2
801393e: d902 bls.n 8013946 <tcp_receive+0x182>
/* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
tcp_rexmit_fast(pcb);
8013940: 6878 ldr r0, [r7, #4]
8013942: f001 feed bl 8015720 <tcp_rexmit_fast>
}
}
}
/* If Clause (1) or more is true, but not a duplicate ack, reset
* count of consecutive duplicate acks */
if (!found_dupack) {
8013946: 6cbb ldr r3, [r7, #72] ; 0x48
8013948: 2b00 cmp r3, #0
801394a: f040 8160 bne.w 8013c0e <tcp_receive+0x44a>
pcb->dupacks = 0;
801394e: 687b ldr r3, [r7, #4]
8013950: 2200 movs r2, #0
8013952: f883 2043 strb.w r2, [r3, #67] ; 0x43
8013956: e15a b.n 8013c0e <tcp_receive+0x44a>
}
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013958: 4b4b ldr r3, [pc, #300] ; (8013a88 <tcp_receive+0x2c4>)
801395a: 681a ldr r2, [r3, #0]
801395c: 687b ldr r3, [r7, #4]
801395e: 6c5b ldr r3, [r3, #68] ; 0x44
8013960: 1ad3 subs r3, r2, r3
8013962: 3b01 subs r3, #1
8013964: 2b00 cmp r3, #0
8013966: f2c0 814d blt.w 8013c04 <tcp_receive+0x440>
801396a: 4b47 ldr r3, [pc, #284] ; (8013a88 <tcp_receive+0x2c4>)
801396c: 681a ldr r2, [r3, #0]
801396e: 687b ldr r3, [r7, #4]
8013970: 6d1b ldr r3, [r3, #80] ; 0x50
8013972: 1ad3 subs r3, r2, r3
8013974: 2b00 cmp r3, #0
8013976: f300 8145 bgt.w 8013c04 <tcp_receive+0x440>
tcpwnd_size_t acked;
/* Reset the "IN Fast Retransmit" flag, since we are no longer
in fast retransmit. Also reset the congestion window to the
slow start threshold. */
if (pcb->flags & TF_INFR) {
801397a: 687b ldr r3, [r7, #4]
801397c: 8b5b ldrh r3, [r3, #26]
801397e: f003 0304 and.w r3, r3, #4
8013982: 2b00 cmp r3, #0
8013984: d010 beq.n 80139a8 <tcp_receive+0x1e4>
tcp_clear_flags(pcb, TF_INFR);
8013986: 687b ldr r3, [r7, #4]
8013988: 8b5b ldrh r3, [r3, #26]
801398a: f023 0304 bic.w r3, r3, #4
801398e: b29a uxth r2, r3
8013990: 687b ldr r3, [r7, #4]
8013992: 835a strh r2, [r3, #26]
pcb->cwnd = pcb->ssthresh;
8013994: 687b ldr r3, [r7, #4]
8013996: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
801399a: 687b ldr r3, [r7, #4]
801399c: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->bytes_acked = 0;
80139a0: 687b ldr r3, [r7, #4]
80139a2: 2200 movs r2, #0
80139a4: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
}
/* Reset the number of retransmissions. */
pcb->nrtx = 0;
80139a8: 687b ldr r3, [r7, #4]
80139aa: 2200 movs r2, #0
80139ac: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Reset the retransmission time-out. */
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
80139b0: 687b ldr r3, [r7, #4]
80139b2: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
80139b6: 10db asrs r3, r3, #3
80139b8: b21b sxth r3, r3
80139ba: b29a uxth r2, r3
80139bc: 687b ldr r3, [r7, #4]
80139be: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
80139c2: b29b uxth r3, r3
80139c4: 4413 add r3, r2
80139c6: b29b uxth r3, r3
80139c8: b21a sxth r2, r3
80139ca: 687b ldr r3, [r7, #4]
80139cc: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* Record how much data this ACK acks */
acked = (tcpwnd_size_t)(ackno - pcb->lastack);
80139d0: 4b2d ldr r3, [pc, #180] ; (8013a88 <tcp_receive+0x2c4>)
80139d2: 681b ldr r3, [r3, #0]
80139d4: b29a uxth r2, r3
80139d6: 687b ldr r3, [r7, #4]
80139d8: 6c5b ldr r3, [r3, #68] ; 0x44
80139da: b29b uxth r3, r3
80139dc: 1ad3 subs r3, r2, r3
80139de: 85fb strh r3, [r7, #46] ; 0x2e
/* Reset the fast retransmit variables. */
pcb->dupacks = 0;
80139e0: 687b ldr r3, [r7, #4]
80139e2: 2200 movs r2, #0
80139e4: f883 2043 strb.w r2, [r3, #67] ; 0x43
pcb->lastack = ackno;
80139e8: 4b27 ldr r3, [pc, #156] ; (8013a88 <tcp_receive+0x2c4>)
80139ea: 681a ldr r2, [r3, #0]
80139ec: 687b ldr r3, [r7, #4]
80139ee: 645a str r2, [r3, #68] ; 0x44
/* Update the congestion control variables (cwnd and
ssthresh). */
if (pcb->state >= ESTABLISHED) {
80139f0: 687b ldr r3, [r7, #4]
80139f2: 7d1b ldrb r3, [r3, #20]
80139f4: 2b03 cmp r3, #3
80139f6: f240 8096 bls.w 8013b26 <tcp_receive+0x362>
if (pcb->cwnd < pcb->ssthresh) {
80139fa: 687b ldr r3, [r7, #4]
80139fc: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a00: 687b ldr r3, [r7, #4]
8013a02: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
8013a06: 429a cmp r2, r3
8013a08: d244 bcs.n 8013a94 <tcp_receive+0x2d0>
tcpwnd_size_t increase;
/* limit to 1 SMSS segment during period following RTO */
u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
8013a0a: 687b ldr r3, [r7, #4]
8013a0c: 8b5b ldrh r3, [r3, #26]
8013a0e: f403 6300 and.w r3, r3, #2048 ; 0x800
8013a12: 2b00 cmp r3, #0
8013a14: d001 beq.n 8013a1a <tcp_receive+0x256>
8013a16: 2301 movs r3, #1
8013a18: e000 b.n 8013a1c <tcp_receive+0x258>
8013a1a: 2302 movs r3, #2
8013a1c: f887 302d strb.w r3, [r7, #45] ; 0x2d
/* RFC 3465, section 2.2 Slow Start */
increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
8013a20: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
8013a24: b29a uxth r2, r3
8013a26: 687b ldr r3, [r7, #4]
8013a28: 8e5b ldrh r3, [r3, #50] ; 0x32
8013a2a: fb12 f303 smulbb r3, r2, r3
8013a2e: b29b uxth r3, r3
8013a30: 8dfa ldrh r2, [r7, #46] ; 0x2e
8013a32: 4293 cmp r3, r2
8013a34: bf28 it cs
8013a36: 4613 movcs r3, r2
8013a38: 857b strh r3, [r7, #42] ; 0x2a
TCP_WND_INC(pcb->cwnd, increase);
8013a3a: 687b ldr r3, [r7, #4]
8013a3c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a40: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a42: 4413 add r3, r2
8013a44: b29a uxth r2, r3
8013a46: 687b ldr r3, [r7, #4]
8013a48: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013a4c: 429a cmp r2, r3
8013a4e: d309 bcc.n 8013a64 <tcp_receive+0x2a0>
8013a50: 687b ldr r3, [r7, #4]
8013a52: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a56: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a58: 4413 add r3, r2
8013a5a: b29a uxth r2, r3
8013a5c: 687b ldr r3, [r7, #4]
8013a5e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a62: e060 b.n 8013b26 <tcp_receive+0x362>
8013a64: 687b ldr r3, [r7, #4]
8013a66: f64f 72ff movw r2, #65535 ; 0xffff
8013a6a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a6e: e05a b.n 8013b26 <tcp_receive+0x362>
8013a70: 0801d2b0 .word 0x0801d2b0
8013a74: 0801d5e0 .word 0x0801d5e0
8013a78: 0801d2fc .word 0x0801d2fc
8013a7c: 0801d5fc .word 0x0801d5fc
8013a80: 20008758 .word 0x20008758
8013a84: 2000874c .word 0x2000874c
8013a88: 20008750 .word 0x20008750
8013a8c: 2000873c .word 0x2000873c
8013a90: 20008756 .word 0x20008756
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
} else {
/* RFC 3465, section 2.1 Congestion Avoidance */
TCP_WND_INC(pcb->bytes_acked, acked);
8013a94: 687b ldr r3, [r7, #4]
8013a96: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013a9a: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013a9c: 4413 add r3, r2
8013a9e: b29a uxth r2, r3
8013aa0: 687b ldr r3, [r7, #4]
8013aa2: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a
8013aa6: 429a cmp r2, r3
8013aa8: d309 bcc.n 8013abe <tcp_receive+0x2fa>
8013aaa: 687b ldr r3, [r7, #4]
8013aac: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013ab0: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013ab2: 4413 add r3, r2
8013ab4: b29a uxth r2, r3
8013ab6: 687b ldr r3, [r7, #4]
8013ab8: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
8013abc: e004 b.n 8013ac8 <tcp_receive+0x304>
8013abe: 687b ldr r3, [r7, #4]
8013ac0: f64f 72ff movw r2, #65535 ; 0xffff
8013ac4: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
if (pcb->bytes_acked >= pcb->cwnd) {
8013ac8: 687b ldr r3, [r7, #4]
8013aca: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013ace: 687b ldr r3, [r7, #4]
8013ad0: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ad4: 429a cmp r2, r3
8013ad6: d326 bcc.n 8013b26 <tcp_receive+0x362>
pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
8013ad8: 687b ldr r3, [r7, #4]
8013ada: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013ade: 687b ldr r3, [r7, #4]
8013ae0: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ae4: 1ad3 subs r3, r2, r3
8013ae6: b29a uxth r2, r3
8013ae8: 687b ldr r3, [r7, #4]
8013aea: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
TCP_WND_INC(pcb->cwnd, pcb->mss);
8013aee: 687b ldr r3, [r7, #4]
8013af0: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013af4: 687b ldr r3, [r7, #4]
8013af6: 8e5b ldrh r3, [r3, #50] ; 0x32
8013af8: 4413 add r3, r2
8013afa: b29a uxth r2, r3
8013afc: 687b ldr r3, [r7, #4]
8013afe: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013b02: 429a cmp r2, r3
8013b04: d30a bcc.n 8013b1c <tcp_receive+0x358>
8013b06: 687b ldr r3, [r7, #4]
8013b08: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013b0c: 687b ldr r3, [r7, #4]
8013b0e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013b10: 4413 add r3, r2
8013b12: b29a uxth r2, r3
8013b14: 687b ldr r3, [r7, #4]
8013b16: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013b1a: e004 b.n 8013b26 <tcp_receive+0x362>
8013b1c: 687b ldr r3, [r7, #4]
8013b1e: f64f 72ff movw r2, #65535 ; 0xffff
8013b22: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->unacked != NULL ?
lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
/* Remove segment from the unacknowledged list if the incoming
ACK acknowledges them. */
pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
8013b26: 687b ldr r3, [r7, #4]
8013b28: 6f19 ldr r1, [r3, #112] ; 0x70
8013b2a: 687b ldr r3, [r7, #4]
8013b2c: 6edb ldr r3, [r3, #108] ; 0x6c
8013b2e: 4a98 ldr r2, [pc, #608] ; (8013d90 <tcp_receive+0x5cc>)
8013b30: 6878 ldr r0, [r7, #4]
8013b32: f7ff fdcb bl 80136cc <tcp_free_acked_segments>
8013b36: 4602 mov r2, r0
8013b38: 687b ldr r3, [r7, #4]
8013b3a: 671a str r2, [r3, #112] ; 0x70
on the list are acknowledged by the ACK. This may seem
strange since an "unsent" segment shouldn't be acked. The
rationale is that lwIP puts all outstanding segments on the
->unsent list after a retransmission, so these segments may
in fact have been sent once. */
pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
8013b3c: 687b ldr r3, [r7, #4]
8013b3e: 6ed9 ldr r1, [r3, #108] ; 0x6c
8013b40: 687b ldr r3, [r7, #4]
8013b42: 6f1b ldr r3, [r3, #112] ; 0x70
8013b44: 4a93 ldr r2, [pc, #588] ; (8013d94 <tcp_receive+0x5d0>)
8013b46: 6878 ldr r0, [r7, #4]
8013b48: f7ff fdc0 bl 80136cc <tcp_free_acked_segments>
8013b4c: 4602 mov r2, r0
8013b4e: 687b ldr r3, [r7, #4]
8013b50: 66da str r2, [r3, #108] ; 0x6c
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013b52: 687b ldr r3, [r7, #4]
8013b54: 6f1b ldr r3, [r3, #112] ; 0x70
8013b56: 2b00 cmp r3, #0
8013b58: d104 bne.n 8013b64 <tcp_receive+0x3a0>
pcb->rtime = -1;
8013b5a: 687b ldr r3, [r7, #4]
8013b5c: f64f 72ff movw r2, #65535 ; 0xffff
8013b60: 861a strh r2, [r3, #48] ; 0x30
8013b62: e002 b.n 8013b6a <tcp_receive+0x3a6>
} else {
pcb->rtime = 0;
8013b64: 687b ldr r3, [r7, #4]
8013b66: 2200 movs r2, #0
8013b68: 861a strh r2, [r3, #48] ; 0x30
}
pcb->polltmr = 0;
8013b6a: 687b ldr r3, [r7, #4]
8013b6c: 2200 movs r2, #0
8013b6e: 771a strb r2, [r3, #28]
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
8013b70: 687b ldr r3, [r7, #4]
8013b72: 6edb ldr r3, [r3, #108] ; 0x6c
8013b74: 2b00 cmp r3, #0
8013b76: d103 bne.n 8013b80 <tcp_receive+0x3bc>
pcb->unsent_oversize = 0;
8013b78: 687b ldr r3, [r7, #4]
8013b7a: 2200 movs r2, #0
8013b7c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
/* Inform neighbor reachability of forward progress. */
nd6_reachability_hint(ip6_current_src_addr());
}
#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
8013b80: 687b ldr r3, [r7, #4]
8013b82: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64
8013b86: 4b84 ldr r3, [pc, #528] ; (8013d98 <tcp_receive+0x5d4>)
8013b88: 881b ldrh r3, [r3, #0]
8013b8a: 4413 add r3, r2
8013b8c: b29a uxth r2, r3
8013b8e: 687b ldr r3, [r7, #4]
8013b90: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* check if this ACK ends our retransmission of in-flight data */
if (pcb->flags & TF_RTO) {
8013b94: 687b ldr r3, [r7, #4]
8013b96: 8b5b ldrh r3, [r3, #26]
8013b98: f403 6300 and.w r3, r3, #2048 ; 0x800
8013b9c: 2b00 cmp r3, #0
8013b9e: d035 beq.n 8013c0c <tcp_receive+0x448>
/* RTO is done if
1) both queues are empty or
2) unacked is empty and unsent head contains data not part of RTO or
3) unacked head contains data not part of RTO */
if (pcb->unacked == NULL) {
8013ba0: 687b ldr r3, [r7, #4]
8013ba2: 6f1b ldr r3, [r3, #112] ; 0x70
8013ba4: 2b00 cmp r3, #0
8013ba6: d118 bne.n 8013bda <tcp_receive+0x416>
if ((pcb->unsent == NULL) ||
8013ba8: 687b ldr r3, [r7, #4]
8013baa: 6edb ldr r3, [r3, #108] ; 0x6c
8013bac: 2b00 cmp r3, #0
8013bae: d00c beq.n 8013bca <tcp_receive+0x406>
(TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
8013bb0: 687b ldr r3, [r7, #4]
8013bb2: 6cdc ldr r4, [r3, #76] ; 0x4c
8013bb4: 687b ldr r3, [r7, #4]
8013bb6: 6edb ldr r3, [r3, #108] ; 0x6c
8013bb8: 68db ldr r3, [r3, #12]
8013bba: 685b ldr r3, [r3, #4]
8013bbc: 4618 mov r0, r3
8013bbe: f7fb f974 bl 800eeaa <lwip_htonl>
8013bc2: 4603 mov r3, r0
8013bc4: 1ae3 subs r3, r4, r3
if ((pcb->unsent == NULL) ||
8013bc6: 2b00 cmp r3, #0
8013bc8: dc20 bgt.n 8013c0c <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013bca: 687b ldr r3, [r7, #4]
8013bcc: 8b5b ldrh r3, [r3, #26]
8013bce: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013bd2: b29a uxth r2, r3
8013bd4: 687b ldr r3, [r7, #4]
8013bd6: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013bd8: e018 b.n 8013c0c <tcp_receive+0x448>
}
} else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
8013bda: 687b ldr r3, [r7, #4]
8013bdc: 6cdc ldr r4, [r3, #76] ; 0x4c
8013bde: 687b ldr r3, [r7, #4]
8013be0: 6f1b ldr r3, [r3, #112] ; 0x70
8013be2: 68db ldr r3, [r3, #12]
8013be4: 685b ldr r3, [r3, #4]
8013be6: 4618 mov r0, r3
8013be8: f7fb f95f bl 800eeaa <lwip_htonl>
8013bec: 4603 mov r3, r0
8013bee: 1ae3 subs r3, r4, r3
8013bf0: 2b00 cmp r3, #0
8013bf2: dc0b bgt.n 8013c0c <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013bf4: 687b ldr r3, [r7, #4]
8013bf6: 8b5b ldrh r3, [r3, #26]
8013bf8: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013bfc: b29a uxth r2, r3
8013bfe: 687b ldr r3, [r7, #4]
8013c00: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013c02: e003 b.n 8013c0c <tcp_receive+0x448>
}
}
/* End of ACK for new data processing. */
} else {
/* Out of sequence ACK, didn't really ack anything */
tcp_send_empty_ack(pcb);
8013c04: 6878 ldr r0, [r7, #4]
8013c06: f001 ff85 bl 8015b14 <tcp_send_empty_ack>
8013c0a: e000 b.n 8013c0e <tcp_receive+0x44a>
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013c0c: bf00 nop
pcb->rttest, pcb->rtseq, ackno));
/* RTT estimation calculations. This is done by checking if the
incoming segment acknowledges the segment we use to take a
round-trip time measurement. */
if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
8013c0e: 687b ldr r3, [r7, #4]
8013c10: 6b5b ldr r3, [r3, #52] ; 0x34
8013c12: 2b00 cmp r3, #0
8013c14: d05b beq.n 8013cce <tcp_receive+0x50a>
8013c16: 687b ldr r3, [r7, #4]
8013c18: 6b9a ldr r2, [r3, #56] ; 0x38
8013c1a: 4b60 ldr r3, [pc, #384] ; (8013d9c <tcp_receive+0x5d8>)
8013c1c: 681b ldr r3, [r3, #0]
8013c1e: 1ad3 subs r3, r2, r3
8013c20: 2b00 cmp r3, #0
8013c22: da54 bge.n 8013cce <tcp_receive+0x50a>
/* diff between this shouldn't exceed 32K since this are tcp timer ticks
and a round-trip shouldn't be that long... */
m = (s16_t)(tcp_ticks - pcb->rttest);
8013c24: 4b5e ldr r3, [pc, #376] ; (8013da0 <tcp_receive+0x5dc>)
8013c26: 681b ldr r3, [r3, #0]
8013c28: b29a uxth r2, r3
8013c2a: 687b ldr r3, [r7, #4]
8013c2c: 6b5b ldr r3, [r3, #52] ; 0x34
8013c2e: b29b uxth r3, r3
8013c30: 1ad3 subs r3, r2, r3
8013c32: b29b uxth r3, r3
8013c34: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
m, (u16_t)(m * TCP_SLOW_INTERVAL)));
/* This is taken directly from VJs original code in his paper */
m = (s16_t)(m - (pcb->sa >> 3));
8013c38: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c3c: 687b ldr r3, [r7, #4]
8013c3e: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c42: 10db asrs r3, r3, #3
8013c44: b21b sxth r3, r3
8013c46: b29b uxth r3, r3
8013c48: 1ad3 subs r3, r2, r3
8013c4a: b29b uxth r3, r3
8013c4c: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sa = (s16_t)(pcb->sa + m);
8013c50: 687b ldr r3, [r7, #4]
8013c52: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c56: b29a uxth r2, r3
8013c58: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c5c: 4413 add r3, r2
8013c5e: b29b uxth r3, r3
8013c60: b21a sxth r2, r3
8013c62: 687b ldr r3, [r7, #4]
8013c64: 879a strh r2, [r3, #60] ; 0x3c
if (m < 0) {
8013c66: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e
8013c6a: 2b00 cmp r3, #0
8013c6c: da05 bge.n 8013c7a <tcp_receive+0x4b6>
m = (s16_t) - m;
8013c6e: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c72: 425b negs r3, r3
8013c74: b29b uxth r3, r3
8013c76: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
}
m = (s16_t)(m - (pcb->sv >> 2));
8013c7a: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c7e: 687b ldr r3, [r7, #4]
8013c80: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c84: 109b asrs r3, r3, #2
8013c86: b21b sxth r3, r3
8013c88: b29b uxth r3, r3
8013c8a: 1ad3 subs r3, r2, r3
8013c8c: b29b uxth r3, r3
8013c8e: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sv = (s16_t)(pcb->sv + m);
8013c92: 687b ldr r3, [r7, #4]
8013c94: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c98: b29a uxth r2, r3
8013c9a: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c9e: 4413 add r3, r2
8013ca0: b29b uxth r3, r3
8013ca2: b21a sxth r2, r3
8013ca4: 687b ldr r3, [r7, #4]
8013ca6: 87da strh r2, [r3, #62] ; 0x3e
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
8013ca8: 687b ldr r3, [r7, #4]
8013caa: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013cae: 10db asrs r3, r3, #3
8013cb0: b21b sxth r3, r3
8013cb2: b29a uxth r2, r3
8013cb4: 687b ldr r3, [r7, #4]
8013cb6: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013cba: b29b uxth r3, r3
8013cbc: 4413 add r3, r2
8013cbe: b29b uxth r3, r3
8013cc0: b21a sxth r2, r3
8013cc2: 687b ldr r3, [r7, #4]
8013cc4: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
pcb->rttest = 0;
8013cc8: 687b ldr r3, [r7, #4]
8013cca: 2200 movs r2, #0
8013ccc: 635a str r2, [r3, #52] ; 0x34
/* If the incoming segment contains data, we must process it
further unless the pcb already received a FIN.
(RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
8013cce: 4b35 ldr r3, [pc, #212] ; (8013da4 <tcp_receive+0x5e0>)
8013cd0: 881b ldrh r3, [r3, #0]
8013cd2: 2b00 cmp r3, #0
8013cd4: f000 84e1 beq.w 801469a <tcp_receive+0xed6>
8013cd8: 687b ldr r3, [r7, #4]
8013cda: 7d1b ldrb r3, [r3, #20]
8013cdc: 2b06 cmp r3, #6
8013cde: f200 84dc bhi.w 801469a <tcp_receive+0xed6>
this if the sequence number of the incoming segment is less
than rcv_nxt, and the sequence number plus the length of the
segment is larger than rcv_nxt. */
/* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013ce2: 687b ldr r3, [r7, #4]
8013ce4: 6a5a ldr r2, [r3, #36] ; 0x24
8013ce6: 4b30 ldr r3, [pc, #192] ; (8013da8 <tcp_receive+0x5e4>)
8013ce8: 681b ldr r3, [r3, #0]
8013cea: 1ad3 subs r3, r2, r3
8013cec: 3b01 subs r3, #1
8013cee: 2b00 cmp r3, #0
8013cf0: f2c0 808e blt.w 8013e10 <tcp_receive+0x64c>
8013cf4: 687b ldr r3, [r7, #4]
8013cf6: 6a5a ldr r2, [r3, #36] ; 0x24
8013cf8: 4b2a ldr r3, [pc, #168] ; (8013da4 <tcp_receive+0x5e0>)
8013cfa: 881b ldrh r3, [r3, #0]
8013cfc: 4619 mov r1, r3
8013cfe: 4b2a ldr r3, [pc, #168] ; (8013da8 <tcp_receive+0x5e4>)
8013d00: 681b ldr r3, [r3, #0]
8013d02: 440b add r3, r1
8013d04: 1ad3 subs r3, r2, r3
8013d06: 3301 adds r3, #1
8013d08: 2b00 cmp r3, #0
8013d0a: f300 8081 bgt.w 8013e10 <tcp_receive+0x64c>
After we are done with adjusting the pbuf pointers we must
adjust the ->data pointer in the seg and the segment
length.*/
struct pbuf *p = inseg.p;
8013d0e: 4b27 ldr r3, [pc, #156] ; (8013dac <tcp_receive+0x5e8>)
8013d10: 685b ldr r3, [r3, #4]
8013d12: 647b str r3, [r7, #68] ; 0x44
u32_t off32 = pcb->rcv_nxt - seqno;
8013d14: 687b ldr r3, [r7, #4]
8013d16: 6a5a ldr r2, [r3, #36] ; 0x24
8013d18: 4b23 ldr r3, [pc, #140] ; (8013da8 <tcp_receive+0x5e4>)
8013d1a: 681b ldr r3, [r3, #0]
8013d1c: 1ad3 subs r3, r2, r3
8013d1e: 627b str r3, [r7, #36] ; 0x24
u16_t new_tot_len, off;
LWIP_ASSERT("inseg.p != NULL", inseg.p);
8013d20: 4b22 ldr r3, [pc, #136] ; (8013dac <tcp_receive+0x5e8>)
8013d22: 685b ldr r3, [r3, #4]
8013d24: 2b00 cmp r3, #0
8013d26: d106 bne.n 8013d36 <tcp_receive+0x572>
8013d28: 4b21 ldr r3, [pc, #132] ; (8013db0 <tcp_receive+0x5ec>)
8013d2a: f240 5294 movw r2, #1428 ; 0x594
8013d2e: 4921 ldr r1, [pc, #132] ; (8013db4 <tcp_receive+0x5f0>)
8013d30: 4821 ldr r0, [pc, #132] ; (8013db8 <tcp_receive+0x5f4>)
8013d32: f007 f96f bl 801b014 <iprintf>
LWIP_ASSERT("insane offset!", (off32 < 0xffff));
8013d36: 6a7b ldr r3, [r7, #36] ; 0x24
8013d38: f64f 72fe movw r2, #65534 ; 0xfffe
8013d3c: 4293 cmp r3, r2
8013d3e: d906 bls.n 8013d4e <tcp_receive+0x58a>
8013d40: 4b1b ldr r3, [pc, #108] ; (8013db0 <tcp_receive+0x5ec>)
8013d42: f240 5295 movw r2, #1429 ; 0x595
8013d46: 491d ldr r1, [pc, #116] ; (8013dbc <tcp_receive+0x5f8>)
8013d48: 481b ldr r0, [pc, #108] ; (8013db8 <tcp_receive+0x5f4>)
8013d4a: f007 f963 bl 801b014 <iprintf>
off = (u16_t)off32;
8013d4e: 6a7b ldr r3, [r7, #36] ; 0x24
8013d50: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
8013d54: 4b15 ldr r3, [pc, #84] ; (8013dac <tcp_receive+0x5e8>)
8013d56: 685b ldr r3, [r3, #4]
8013d58: 891b ldrh r3, [r3, #8]
8013d5a: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013d5e: 429a cmp r2, r3
8013d60: d906 bls.n 8013d70 <tcp_receive+0x5ac>
8013d62: 4b13 ldr r3, [pc, #76] ; (8013db0 <tcp_receive+0x5ec>)
8013d64: f240 5297 movw r2, #1431 ; 0x597
8013d68: 4915 ldr r1, [pc, #84] ; (8013dc0 <tcp_receive+0x5fc>)
8013d6a: 4813 ldr r0, [pc, #76] ; (8013db8 <tcp_receive+0x5f4>)
8013d6c: f007 f952 bl 801b014 <iprintf>
inseg.len -= off;
8013d70: 4b0e ldr r3, [pc, #56] ; (8013dac <tcp_receive+0x5e8>)
8013d72: 891a ldrh r2, [r3, #8]
8013d74: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d78: 1ad3 subs r3, r2, r3
8013d7a: b29a uxth r2, r3
8013d7c: 4b0b ldr r3, [pc, #44] ; (8013dac <tcp_receive+0x5e8>)
8013d7e: 811a strh r2, [r3, #8]
new_tot_len = (u16_t)(inseg.p->tot_len - off);
8013d80: 4b0a ldr r3, [pc, #40] ; (8013dac <tcp_receive+0x5e8>)
8013d82: 685b ldr r3, [r3, #4]
8013d84: 891a ldrh r2, [r3, #8]
8013d86: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d8a: 1ad3 subs r3, r2, r3
8013d8c: 847b strh r3, [r7, #34] ; 0x22
while (p->len < off) {
8013d8e: e029 b.n 8013de4 <tcp_receive+0x620>
8013d90: 0801d618 .word 0x0801d618
8013d94: 0801d620 .word 0x0801d620
8013d98: 20008754 .word 0x20008754
8013d9c: 20008750 .word 0x20008750
8013da0: 2000f5c4 .word 0x2000f5c4
8013da4: 20008756 .word 0x20008756
8013da8: 2000874c .word 0x2000874c
8013dac: 2000872c .word 0x2000872c
8013db0: 0801d2b0 .word 0x0801d2b0
8013db4: 0801d628 .word 0x0801d628
8013db8: 0801d2fc .word 0x0801d2fc
8013dbc: 0801d638 .word 0x0801d638
8013dc0: 0801d648 .word 0x0801d648
off -= p->len;
8013dc4: 6c7b ldr r3, [r7, #68] ; 0x44
8013dc6: 895b ldrh r3, [r3, #10]
8013dc8: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013dcc: 1ad3 subs r3, r2, r3
8013dce: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
/* all pbufs up to and including this one have len==0, so tot_len is equal */
p->tot_len = new_tot_len;
8013dd2: 6c7b ldr r3, [r7, #68] ; 0x44
8013dd4: 8c7a ldrh r2, [r7, #34] ; 0x22
8013dd6: 811a strh r2, [r3, #8]
p->len = 0;
8013dd8: 6c7b ldr r3, [r7, #68] ; 0x44
8013dda: 2200 movs r2, #0
8013ddc: 815a strh r2, [r3, #10]
p = p->next;
8013dde: 6c7b ldr r3, [r7, #68] ; 0x44
8013de0: 681b ldr r3, [r3, #0]
8013de2: 647b str r3, [r7, #68] ; 0x44
while (p->len < off) {
8013de4: 6c7b ldr r3, [r7, #68] ; 0x44
8013de6: 895b ldrh r3, [r3, #10]
8013de8: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013dec: 429a cmp r2, r3
8013dee: d8e9 bhi.n 8013dc4 <tcp_receive+0x600>
}
/* cannot fail... */
pbuf_remove_header(p, off);
8013df0: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013df4: 4619 mov r1, r3
8013df6: 6c78 ldr r0, [r7, #68] ; 0x44
8013df8: f7fc fb70 bl 80104dc <pbuf_remove_header>
inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
8013dfc: 687b ldr r3, [r7, #4]
8013dfe: 6a5b ldr r3, [r3, #36] ; 0x24
8013e00: 4a91 ldr r2, [pc, #580] ; (8014048 <tcp_receive+0x884>)
8013e02: 6013 str r3, [r2, #0]
8013e04: 4b91 ldr r3, [pc, #580] ; (801404c <tcp_receive+0x888>)
8013e06: 68db ldr r3, [r3, #12]
8013e08: 4a8f ldr r2, [pc, #572] ; (8014048 <tcp_receive+0x884>)
8013e0a: 6812 ldr r2, [r2, #0]
8013e0c: 605a str r2, [r3, #4]
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013e0e: e00d b.n 8013e2c <tcp_receive+0x668>
} else {
if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
8013e10: 4b8d ldr r3, [pc, #564] ; (8014048 <tcp_receive+0x884>)
8013e12: 681a ldr r2, [r3, #0]
8013e14: 687b ldr r3, [r7, #4]
8013e16: 6a5b ldr r3, [r3, #36] ; 0x24
8013e18: 1ad3 subs r3, r2, r3
8013e1a: 2b00 cmp r3, #0
8013e1c: da06 bge.n 8013e2c <tcp_receive+0x668>
/* the whole segment is < rcv_nxt */
/* must be a duplicate of a packet that has already been correctly handled */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
tcp_ack_now(pcb);
8013e1e: 687b ldr r3, [r7, #4]
8013e20: 8b5b ldrh r3, [r3, #26]
8013e22: f043 0302 orr.w r3, r3, #2
8013e26: b29a uxth r2, r3
8013e28: 687b ldr r3, [r7, #4]
8013e2a: 835a strh r2, [r3, #26]
}
/* The sequence number must be within the window (above rcv_nxt
and below rcv_nxt + rcv_wnd) in order to be further
processed. */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8013e2c: 4b86 ldr r3, [pc, #536] ; (8014048 <tcp_receive+0x884>)
8013e2e: 681a ldr r2, [r3, #0]
8013e30: 687b ldr r3, [r7, #4]
8013e32: 6a5b ldr r3, [r3, #36] ; 0x24
8013e34: 1ad3 subs r3, r2, r3
8013e36: 2b00 cmp r3, #0
8013e38: f2c0 842a blt.w 8014690 <tcp_receive+0xecc>
8013e3c: 4b82 ldr r3, [pc, #520] ; (8014048 <tcp_receive+0x884>)
8013e3e: 681a ldr r2, [r3, #0]
8013e40: 687b ldr r3, [r7, #4]
8013e42: 6a5b ldr r3, [r3, #36] ; 0x24
8013e44: 6879 ldr r1, [r7, #4]
8013e46: 8d09 ldrh r1, [r1, #40] ; 0x28
8013e48: 440b add r3, r1
8013e4a: 1ad3 subs r3, r2, r3
8013e4c: 3301 adds r3, #1
8013e4e: 2b00 cmp r3, #0
8013e50: f300 841e bgt.w 8014690 <tcp_receive+0xecc>
pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
if (pcb->rcv_nxt == seqno) {
8013e54: 687b ldr r3, [r7, #4]
8013e56: 6a5a ldr r2, [r3, #36] ; 0x24
8013e58: 4b7b ldr r3, [pc, #492] ; (8014048 <tcp_receive+0x884>)
8013e5a: 681b ldr r3, [r3, #0]
8013e5c: 429a cmp r2, r3
8013e5e: f040 829a bne.w 8014396 <tcp_receive+0xbd2>
/* The incoming segment is the next in sequence. We check if
we have to trim the end of the segment and update rcv_nxt
and pass the data to the application. */
tcplen = TCP_TCPLEN(&inseg);
8013e62: 4b7a ldr r3, [pc, #488] ; (801404c <tcp_receive+0x888>)
8013e64: 891c ldrh r4, [r3, #8]
8013e66: 4b79 ldr r3, [pc, #484] ; (801404c <tcp_receive+0x888>)
8013e68: 68db ldr r3, [r3, #12]
8013e6a: 899b ldrh r3, [r3, #12]
8013e6c: b29b uxth r3, r3
8013e6e: 4618 mov r0, r3
8013e70: f7fb f806 bl 800ee80 <lwip_htons>
8013e74: 4603 mov r3, r0
8013e76: b2db uxtb r3, r3
8013e78: f003 0303 and.w r3, r3, #3
8013e7c: 2b00 cmp r3, #0
8013e7e: d001 beq.n 8013e84 <tcp_receive+0x6c0>
8013e80: 2301 movs r3, #1
8013e82: e000 b.n 8013e86 <tcp_receive+0x6c2>
8013e84: 2300 movs r3, #0
8013e86: 4423 add r3, r4
8013e88: b29a uxth r2, r3
8013e8a: 4b71 ldr r3, [pc, #452] ; (8014050 <tcp_receive+0x88c>)
8013e8c: 801a strh r2, [r3, #0]
if (tcplen > pcb->rcv_wnd) {
8013e8e: 687b ldr r3, [r7, #4]
8013e90: 8d1a ldrh r2, [r3, #40] ; 0x28
8013e92: 4b6f ldr r3, [pc, #444] ; (8014050 <tcp_receive+0x88c>)
8013e94: 881b ldrh r3, [r3, #0]
8013e96: 429a cmp r2, r3
8013e98: d275 bcs.n 8013f86 <tcp_receive+0x7c2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013e9a: 4b6c ldr r3, [pc, #432] ; (801404c <tcp_receive+0x888>)
8013e9c: 68db ldr r3, [r3, #12]
8013e9e: 899b ldrh r3, [r3, #12]
8013ea0: b29b uxth r3, r3
8013ea2: 4618 mov r0, r3
8013ea4: f7fa ffec bl 800ee80 <lwip_htons>
8013ea8: 4603 mov r3, r0
8013eaa: b2db uxtb r3, r3
8013eac: f003 0301 and.w r3, r3, #1
8013eb0: 2b00 cmp r3, #0
8013eb2: d01f beq.n 8013ef4 <tcp_receive+0x730>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
8013eb4: 4b65 ldr r3, [pc, #404] ; (801404c <tcp_receive+0x888>)
8013eb6: 68db ldr r3, [r3, #12]
8013eb8: 899b ldrh r3, [r3, #12]
8013eba: b29b uxth r3, r3
8013ebc: b21b sxth r3, r3
8013ebe: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8013ec2: b21c sxth r4, r3
8013ec4: 4b61 ldr r3, [pc, #388] ; (801404c <tcp_receive+0x888>)
8013ec6: 68db ldr r3, [r3, #12]
8013ec8: 899b ldrh r3, [r3, #12]
8013eca: b29b uxth r3, r3
8013ecc: 4618 mov r0, r3
8013ece: f7fa ffd7 bl 800ee80 <lwip_htons>
8013ed2: 4603 mov r3, r0
8013ed4: b2db uxtb r3, r3
8013ed6: b29b uxth r3, r3
8013ed8: f003 033e and.w r3, r3, #62 ; 0x3e
8013edc: b29b uxth r3, r3
8013ede: 4618 mov r0, r3
8013ee0: f7fa ffce bl 800ee80 <lwip_htons>
8013ee4: 4603 mov r3, r0
8013ee6: b21b sxth r3, r3
8013ee8: 4323 orrs r3, r4
8013eea: b21a sxth r2, r3
8013eec: 4b57 ldr r3, [pc, #348] ; (801404c <tcp_receive+0x888>)
8013eee: 68db ldr r3, [r3, #12]
8013ef0: b292 uxth r2, r2
8013ef2: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
TCPWND_CHECK16(pcb->rcv_wnd);
inseg.len = (u16_t)pcb->rcv_wnd;
8013ef4: 687b ldr r3, [r7, #4]
8013ef6: 8d1a ldrh r2, [r3, #40] ; 0x28
8013ef8: 4b54 ldr r3, [pc, #336] ; (801404c <tcp_receive+0x888>)
8013efa: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
8013efc: 4b53 ldr r3, [pc, #332] ; (801404c <tcp_receive+0x888>)
8013efe: 68db ldr r3, [r3, #12]
8013f00: 899b ldrh r3, [r3, #12]
8013f02: b29b uxth r3, r3
8013f04: 4618 mov r0, r3
8013f06: f7fa ffbb bl 800ee80 <lwip_htons>
8013f0a: 4603 mov r3, r0
8013f0c: b2db uxtb r3, r3
8013f0e: f003 0302 and.w r3, r3, #2
8013f12: 2b00 cmp r3, #0
8013f14: d005 beq.n 8013f22 <tcp_receive+0x75e>
inseg.len -= 1;
8013f16: 4b4d ldr r3, [pc, #308] ; (801404c <tcp_receive+0x888>)
8013f18: 891b ldrh r3, [r3, #8]
8013f1a: 3b01 subs r3, #1
8013f1c: b29a uxth r2, r3
8013f1e: 4b4b ldr r3, [pc, #300] ; (801404c <tcp_receive+0x888>)
8013f20: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
8013f22: 4b4a ldr r3, [pc, #296] ; (801404c <tcp_receive+0x888>)
8013f24: 685a ldr r2, [r3, #4]
8013f26: 4b49 ldr r3, [pc, #292] ; (801404c <tcp_receive+0x888>)
8013f28: 891b ldrh r3, [r3, #8]
8013f2a: 4619 mov r1, r3
8013f2c: 4610 mov r0, r2
8013f2e: f7fc f9d5 bl 80102dc <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
8013f32: 4b46 ldr r3, [pc, #280] ; (801404c <tcp_receive+0x888>)
8013f34: 891c ldrh r4, [r3, #8]
8013f36: 4b45 ldr r3, [pc, #276] ; (801404c <tcp_receive+0x888>)
8013f38: 68db ldr r3, [r3, #12]
8013f3a: 899b ldrh r3, [r3, #12]
8013f3c: b29b uxth r3, r3
8013f3e: 4618 mov r0, r3
8013f40: f7fa ff9e bl 800ee80 <lwip_htons>
8013f44: 4603 mov r3, r0
8013f46: b2db uxtb r3, r3
8013f48: f003 0303 and.w r3, r3, #3
8013f4c: 2b00 cmp r3, #0
8013f4e: d001 beq.n 8013f54 <tcp_receive+0x790>
8013f50: 2301 movs r3, #1
8013f52: e000 b.n 8013f56 <tcp_receive+0x792>
8013f54: 2300 movs r3, #0
8013f56: 4423 add r3, r4
8013f58: b29a uxth r2, r3
8013f5a: 4b3d ldr r3, [pc, #244] ; (8014050 <tcp_receive+0x88c>)
8013f5c: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8013f5e: 4b3c ldr r3, [pc, #240] ; (8014050 <tcp_receive+0x88c>)
8013f60: 881b ldrh r3, [r3, #0]
8013f62: 461a mov r2, r3
8013f64: 4b38 ldr r3, [pc, #224] ; (8014048 <tcp_receive+0x884>)
8013f66: 681b ldr r3, [r3, #0]
8013f68: 441a add r2, r3
8013f6a: 687b ldr r3, [r7, #4]
8013f6c: 6a5b ldr r3, [r3, #36] ; 0x24
8013f6e: 6879 ldr r1, [r7, #4]
8013f70: 8d09 ldrh r1, [r1, #40] ; 0x28
8013f72: 440b add r3, r1
8013f74: 429a cmp r2, r3
8013f76: d006 beq.n 8013f86 <tcp_receive+0x7c2>
8013f78: 4b36 ldr r3, [pc, #216] ; (8014054 <tcp_receive+0x890>)
8013f7a: f240 52cc movw r2, #1484 ; 0x5cc
8013f7e: 4936 ldr r1, [pc, #216] ; (8014058 <tcp_receive+0x894>)
8013f80: 4836 ldr r0, [pc, #216] ; (801405c <tcp_receive+0x898>)
8013f82: f007 f847 bl 801b014 <iprintf>
}
#if TCP_QUEUE_OOSEQ
/* Received in-sequence data, adjust ooseq data if:
- FIN has been received or
- inseq overlaps with ooseq */
if (pcb->ooseq != NULL) {
8013f86: 687b ldr r3, [r7, #4]
8013f88: 6f5b ldr r3, [r3, #116] ; 0x74
8013f8a: 2b00 cmp r3, #0
8013f8c: f000 80e7 beq.w 801415e <tcp_receive+0x99a>
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013f90: 4b2e ldr r3, [pc, #184] ; (801404c <tcp_receive+0x888>)
8013f92: 68db ldr r3, [r3, #12]
8013f94: 899b ldrh r3, [r3, #12]
8013f96: b29b uxth r3, r3
8013f98: 4618 mov r0, r3
8013f9a: f7fa ff71 bl 800ee80 <lwip_htons>
8013f9e: 4603 mov r3, r0
8013fa0: b2db uxtb r3, r3
8013fa2: f003 0301 and.w r3, r3, #1
8013fa6: 2b00 cmp r3, #0
8013fa8: d010 beq.n 8013fcc <tcp_receive+0x808>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: received in-order FIN, binning ooseq queue\n"));
/* Received in-order FIN means anything that was received
* out of order must now have been received in-order, so
* bin the ooseq queue */
while (pcb->ooseq != NULL) {
8013faa: e00a b.n 8013fc2 <tcp_receive+0x7fe>
struct tcp_seg *old_ooseq = pcb->ooseq;
8013fac: 687b ldr r3, [r7, #4]
8013fae: 6f5b ldr r3, [r3, #116] ; 0x74
8013fb0: 60fb str r3, [r7, #12]
pcb->ooseq = pcb->ooseq->next;
8013fb2: 687b ldr r3, [r7, #4]
8013fb4: 6f5b ldr r3, [r3, #116] ; 0x74
8013fb6: 681a ldr r2, [r3, #0]
8013fb8: 687b ldr r3, [r7, #4]
8013fba: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(old_ooseq);
8013fbc: 68f8 ldr r0, [r7, #12]
8013fbe: f7fd fd97 bl 8011af0 <tcp_seg_free>
while (pcb->ooseq != NULL) {
8013fc2: 687b ldr r3, [r7, #4]
8013fc4: 6f5b ldr r3, [r3, #116] ; 0x74
8013fc6: 2b00 cmp r3, #0
8013fc8: d1f0 bne.n 8013fac <tcp_receive+0x7e8>
8013fca: e0c8 b.n 801415e <tcp_receive+0x99a>
}
} else {
struct tcp_seg *next = pcb->ooseq;
8013fcc: 687b ldr r3, [r7, #4]
8013fce: 6f5b ldr r3, [r3, #116] ; 0x74
8013fd0: 63fb str r3, [r7, #60] ; 0x3c
/* Remove all segments on ooseq that are covered by inseg already.
* FIN is copied from ooseq to inseg if present. */
while (next &&
8013fd2: e052 b.n 801407a <tcp_receive+0x8b6>
TCP_SEQ_GEQ(seqno + tcplen,
next->tcphdr->seqno + next->len)) {
struct tcp_seg *tmp;
/* inseg cannot have FIN here (already processed above) */
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8013fd4: 6bfb ldr r3, [r7, #60] ; 0x3c
8013fd6: 68db ldr r3, [r3, #12]
8013fd8: 899b ldrh r3, [r3, #12]
8013fda: b29b uxth r3, r3
8013fdc: 4618 mov r0, r3
8013fde: f7fa ff4f bl 800ee80 <lwip_htons>
8013fe2: 4603 mov r3, r0
8013fe4: b2db uxtb r3, r3
8013fe6: f003 0301 and.w r3, r3, #1
8013fea: 2b00 cmp r3, #0
8013fec: d03d beq.n 801406a <tcp_receive+0x8a6>
(TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
8013fee: 4b17 ldr r3, [pc, #92] ; (801404c <tcp_receive+0x888>)
8013ff0: 68db ldr r3, [r3, #12]
8013ff2: 899b ldrh r3, [r3, #12]
8013ff4: b29b uxth r3, r3
8013ff6: 4618 mov r0, r3
8013ff8: f7fa ff42 bl 800ee80 <lwip_htons>
8013ffc: 4603 mov r3, r0
8013ffe: b2db uxtb r3, r3
8014000: f003 0302 and.w r3, r3, #2
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8014004: 2b00 cmp r3, #0
8014006: d130 bne.n 801406a <tcp_receive+0x8a6>
TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
8014008: 4b10 ldr r3, [pc, #64] ; (801404c <tcp_receive+0x888>)
801400a: 68db ldr r3, [r3, #12]
801400c: 899b ldrh r3, [r3, #12]
801400e: b29c uxth r4, r3
8014010: 2001 movs r0, #1
8014012: f7fa ff35 bl 800ee80 <lwip_htons>
8014016: 4603 mov r3, r0
8014018: 461a mov r2, r3
801401a: 4b0c ldr r3, [pc, #48] ; (801404c <tcp_receive+0x888>)
801401c: 68db ldr r3, [r3, #12]
801401e: 4322 orrs r2, r4
8014020: b292 uxth r2, r2
8014022: 819a strh r2, [r3, #12]
tcplen = TCP_TCPLEN(&inseg);
8014024: 4b09 ldr r3, [pc, #36] ; (801404c <tcp_receive+0x888>)
8014026: 891c ldrh r4, [r3, #8]
8014028: 4b08 ldr r3, [pc, #32] ; (801404c <tcp_receive+0x888>)
801402a: 68db ldr r3, [r3, #12]
801402c: 899b ldrh r3, [r3, #12]
801402e: b29b uxth r3, r3
8014030: 4618 mov r0, r3
8014032: f7fa ff25 bl 800ee80 <lwip_htons>
8014036: 4603 mov r3, r0
8014038: b2db uxtb r3, r3
801403a: f003 0303 and.w r3, r3, #3
801403e: 2b00 cmp r3, #0
8014040: d00e beq.n 8014060 <tcp_receive+0x89c>
8014042: 2301 movs r3, #1
8014044: e00d b.n 8014062 <tcp_receive+0x89e>
8014046: bf00 nop
8014048: 2000874c .word 0x2000874c
801404c: 2000872c .word 0x2000872c
8014050: 20008756 .word 0x20008756
8014054: 0801d2b0 .word 0x0801d2b0
8014058: 0801d658 .word 0x0801d658
801405c: 0801d2fc .word 0x0801d2fc
8014060: 2300 movs r3, #0
8014062: 4423 add r3, r4
8014064: b29a uxth r2, r3
8014066: 4b98 ldr r3, [pc, #608] ; (80142c8 <tcp_receive+0xb04>)
8014068: 801a strh r2, [r3, #0]
}
tmp = next;
801406a: 6bfb ldr r3, [r7, #60] ; 0x3c
801406c: 613b str r3, [r7, #16]
next = next->next;
801406e: 6bfb ldr r3, [r7, #60] ; 0x3c
8014070: 681b ldr r3, [r3, #0]
8014072: 63fb str r3, [r7, #60] ; 0x3c
tcp_seg_free(tmp);
8014074: 6938 ldr r0, [r7, #16]
8014076: f7fd fd3b bl 8011af0 <tcp_seg_free>
while (next &&
801407a: 6bfb ldr r3, [r7, #60] ; 0x3c
801407c: 2b00 cmp r3, #0
801407e: d00e beq.n 801409e <tcp_receive+0x8da>
TCP_SEQ_GEQ(seqno + tcplen,
8014080: 4b91 ldr r3, [pc, #580] ; (80142c8 <tcp_receive+0xb04>)
8014082: 881b ldrh r3, [r3, #0]
8014084: 461a mov r2, r3
8014086: 4b91 ldr r3, [pc, #580] ; (80142cc <tcp_receive+0xb08>)
8014088: 681b ldr r3, [r3, #0]
801408a: 441a add r2, r3
801408c: 6bfb ldr r3, [r7, #60] ; 0x3c
801408e: 68db ldr r3, [r3, #12]
8014090: 685b ldr r3, [r3, #4]
8014092: 6bf9 ldr r1, [r7, #60] ; 0x3c
8014094: 8909 ldrh r1, [r1, #8]
8014096: 440b add r3, r1
8014098: 1ad3 subs r3, r2, r3
while (next &&
801409a: 2b00 cmp r3, #0
801409c: da9a bge.n 8013fd4 <tcp_receive+0x810>
}
/* Now trim right side of inseg if it overlaps with the first
* segment on ooseq */
if (next &&
801409e: 6bfb ldr r3, [r7, #60] ; 0x3c
80140a0: 2b00 cmp r3, #0
80140a2: d059 beq.n 8014158 <tcp_receive+0x994>
TCP_SEQ_GT(seqno + tcplen,
80140a4: 4b88 ldr r3, [pc, #544] ; (80142c8 <tcp_receive+0xb04>)
80140a6: 881b ldrh r3, [r3, #0]
80140a8: 461a mov r2, r3
80140aa: 4b88 ldr r3, [pc, #544] ; (80142cc <tcp_receive+0xb08>)
80140ac: 681b ldr r3, [r3, #0]
80140ae: 441a add r2, r3
80140b0: 6bfb ldr r3, [r7, #60] ; 0x3c
80140b2: 68db ldr r3, [r3, #12]
80140b4: 685b ldr r3, [r3, #4]
80140b6: 1ad3 subs r3, r2, r3
if (next &&
80140b8: 2b00 cmp r3, #0
80140ba: dd4d ble.n 8014158 <tcp_receive+0x994>
next->tcphdr->seqno)) {
/* inseg cannot have FIN here (already processed above) */
inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
80140bc: 6bfb ldr r3, [r7, #60] ; 0x3c
80140be: 68db ldr r3, [r3, #12]
80140c0: 685b ldr r3, [r3, #4]
80140c2: b29a uxth r2, r3
80140c4: 4b81 ldr r3, [pc, #516] ; (80142cc <tcp_receive+0xb08>)
80140c6: 681b ldr r3, [r3, #0]
80140c8: b29b uxth r3, r3
80140ca: 1ad3 subs r3, r2, r3
80140cc: b29a uxth r2, r3
80140ce: 4b80 ldr r3, [pc, #512] ; (80142d0 <tcp_receive+0xb0c>)
80140d0: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
80140d2: 4b7f ldr r3, [pc, #508] ; (80142d0 <tcp_receive+0xb0c>)
80140d4: 68db ldr r3, [r3, #12]
80140d6: 899b ldrh r3, [r3, #12]
80140d8: b29b uxth r3, r3
80140da: 4618 mov r0, r3
80140dc: f7fa fed0 bl 800ee80 <lwip_htons>
80140e0: 4603 mov r3, r0
80140e2: b2db uxtb r3, r3
80140e4: f003 0302 and.w r3, r3, #2
80140e8: 2b00 cmp r3, #0
80140ea: d005 beq.n 80140f8 <tcp_receive+0x934>
inseg.len -= 1;
80140ec: 4b78 ldr r3, [pc, #480] ; (80142d0 <tcp_receive+0xb0c>)
80140ee: 891b ldrh r3, [r3, #8]
80140f0: 3b01 subs r3, #1
80140f2: b29a uxth r2, r3
80140f4: 4b76 ldr r3, [pc, #472] ; (80142d0 <tcp_receive+0xb0c>)
80140f6: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
80140f8: 4b75 ldr r3, [pc, #468] ; (80142d0 <tcp_receive+0xb0c>)
80140fa: 685a ldr r2, [r3, #4]
80140fc: 4b74 ldr r3, [pc, #464] ; (80142d0 <tcp_receive+0xb0c>)
80140fe: 891b ldrh r3, [r3, #8]
8014100: 4619 mov r1, r3
8014102: 4610 mov r0, r2
8014104: f7fc f8ea bl 80102dc <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
8014108: 4b71 ldr r3, [pc, #452] ; (80142d0 <tcp_receive+0xb0c>)
801410a: 891c ldrh r4, [r3, #8]
801410c: 4b70 ldr r3, [pc, #448] ; (80142d0 <tcp_receive+0xb0c>)
801410e: 68db ldr r3, [r3, #12]
8014110: 899b ldrh r3, [r3, #12]
8014112: b29b uxth r3, r3
8014114: 4618 mov r0, r3
8014116: f7fa feb3 bl 800ee80 <lwip_htons>
801411a: 4603 mov r3, r0
801411c: b2db uxtb r3, r3
801411e: f003 0303 and.w r3, r3, #3
8014122: 2b00 cmp r3, #0
8014124: d001 beq.n 801412a <tcp_receive+0x966>
8014126: 2301 movs r3, #1
8014128: e000 b.n 801412c <tcp_receive+0x968>
801412a: 2300 movs r3, #0
801412c: 4423 add r3, r4
801412e: b29a uxth r2, r3
8014130: 4b65 ldr r3, [pc, #404] ; (80142c8 <tcp_receive+0xb04>)
8014132: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
8014134: 4b64 ldr r3, [pc, #400] ; (80142c8 <tcp_receive+0xb04>)
8014136: 881b ldrh r3, [r3, #0]
8014138: 461a mov r2, r3
801413a: 4b64 ldr r3, [pc, #400] ; (80142cc <tcp_receive+0xb08>)
801413c: 681b ldr r3, [r3, #0]
801413e: 441a add r2, r3
8014140: 6bfb ldr r3, [r7, #60] ; 0x3c
8014142: 68db ldr r3, [r3, #12]
8014144: 685b ldr r3, [r3, #4]
8014146: 429a cmp r2, r3
8014148: d006 beq.n 8014158 <tcp_receive+0x994>
801414a: 4b62 ldr r3, [pc, #392] ; (80142d4 <tcp_receive+0xb10>)
801414c: f240 52fd movw r2, #1533 ; 0x5fd
8014150: 4961 ldr r1, [pc, #388] ; (80142d8 <tcp_receive+0xb14>)
8014152: 4862 ldr r0, [pc, #392] ; (80142dc <tcp_receive+0xb18>)
8014154: f006 ff5e bl 801b014 <iprintf>
(seqno + tcplen) == next->tcphdr->seqno);
}
pcb->ooseq = next;
8014158: 687b ldr r3, [r7, #4]
801415a: 6bfa ldr r2, [r7, #60] ; 0x3c
801415c: 675a str r2, [r3, #116] ; 0x74
}
}
#endif /* TCP_QUEUE_OOSEQ */
pcb->rcv_nxt = seqno + tcplen;
801415e: 4b5a ldr r3, [pc, #360] ; (80142c8 <tcp_receive+0xb04>)
8014160: 881b ldrh r3, [r3, #0]
8014162: 461a mov r2, r3
8014164: 4b59 ldr r3, [pc, #356] ; (80142cc <tcp_receive+0xb08>)
8014166: 681b ldr r3, [r3, #0]
8014168: 441a add r2, r3
801416a: 687b ldr r3, [r7, #4]
801416c: 625a str r2, [r3, #36] ; 0x24
/* Update the receiver's (our) window. */
LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
801416e: 687b ldr r3, [r7, #4]
8014170: 8d1a ldrh r2, [r3, #40] ; 0x28
8014172: 4b55 ldr r3, [pc, #340] ; (80142c8 <tcp_receive+0xb04>)
8014174: 881b ldrh r3, [r3, #0]
8014176: 429a cmp r2, r3
8014178: d206 bcs.n 8014188 <tcp_receive+0x9c4>
801417a: 4b56 ldr r3, [pc, #344] ; (80142d4 <tcp_receive+0xb10>)
801417c: f240 6207 movw r2, #1543 ; 0x607
8014180: 4957 ldr r1, [pc, #348] ; (80142e0 <tcp_receive+0xb1c>)
8014182: 4856 ldr r0, [pc, #344] ; (80142dc <tcp_receive+0xb18>)
8014184: f006 ff46 bl 801b014 <iprintf>
pcb->rcv_wnd -= tcplen;
8014188: 687b ldr r3, [r7, #4]
801418a: 8d1a ldrh r2, [r3, #40] ; 0x28
801418c: 4b4e ldr r3, [pc, #312] ; (80142c8 <tcp_receive+0xb04>)
801418e: 881b ldrh r3, [r3, #0]
8014190: 1ad3 subs r3, r2, r3
8014192: b29a uxth r2, r3
8014194: 687b ldr r3, [r7, #4]
8014196: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
8014198: 6878 ldr r0, [r7, #4]
801419a: f7fc ffcd bl 8011138 <tcp_update_rcv_ann_wnd>
chains its data on this pbuf as well.
If the segment was a FIN, we set the TF_GOT_FIN flag that will
be used to indicate to the application that the remote side has
closed its end of the connection. */
if (inseg.p->tot_len > 0) {
801419e: 4b4c ldr r3, [pc, #304] ; (80142d0 <tcp_receive+0xb0c>)
80141a0: 685b ldr r3, [r3, #4]
80141a2: 891b ldrh r3, [r3, #8]
80141a4: 2b00 cmp r3, #0
80141a6: d006 beq.n 80141b6 <tcp_receive+0x9f2>
recv_data = inseg.p;
80141a8: 4b49 ldr r3, [pc, #292] ; (80142d0 <tcp_receive+0xb0c>)
80141aa: 685b ldr r3, [r3, #4]
80141ac: 4a4d ldr r2, [pc, #308] ; (80142e4 <tcp_receive+0xb20>)
80141ae: 6013 str r3, [r2, #0]
/* Since this pbuf now is the responsibility of the
application, we delete our reference to it so that we won't
(mistakingly) deallocate it. */
inseg.p = NULL;
80141b0: 4b47 ldr r3, [pc, #284] ; (80142d0 <tcp_receive+0xb0c>)
80141b2: 2200 movs r2, #0
80141b4: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
80141b6: 4b46 ldr r3, [pc, #280] ; (80142d0 <tcp_receive+0xb0c>)
80141b8: 68db ldr r3, [r3, #12]
80141ba: 899b ldrh r3, [r3, #12]
80141bc: b29b uxth r3, r3
80141be: 4618 mov r0, r3
80141c0: f7fa fe5e bl 800ee80 <lwip_htons>
80141c4: 4603 mov r3, r0
80141c6: b2db uxtb r3, r3
80141c8: f003 0301 and.w r3, r3, #1
80141cc: 2b00 cmp r3, #0
80141ce: f000 80b8 beq.w 8014342 <tcp_receive+0xb7e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
recv_flags |= TF_GOT_FIN;
80141d2: 4b45 ldr r3, [pc, #276] ; (80142e8 <tcp_receive+0xb24>)
80141d4: 781b ldrb r3, [r3, #0]
80141d6: f043 0320 orr.w r3, r3, #32
80141da: b2da uxtb r2, r3
80141dc: 4b42 ldr r3, [pc, #264] ; (80142e8 <tcp_receive+0xb24>)
80141de: 701a strb r2, [r3, #0]
}
#if TCP_QUEUE_OOSEQ
/* We now check if we have segments on the ->ooseq queue that
are now in sequence. */
while (pcb->ooseq != NULL &&
80141e0: e0af b.n 8014342 <tcp_receive+0xb7e>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
struct tcp_seg *cseg = pcb->ooseq;
80141e2: 687b ldr r3, [r7, #4]
80141e4: 6f5b ldr r3, [r3, #116] ; 0x74
80141e6: 60bb str r3, [r7, #8]
seqno = pcb->ooseq->tcphdr->seqno;
80141e8: 687b ldr r3, [r7, #4]
80141ea: 6f5b ldr r3, [r3, #116] ; 0x74
80141ec: 68db ldr r3, [r3, #12]
80141ee: 685b ldr r3, [r3, #4]
80141f0: 4a36 ldr r2, [pc, #216] ; (80142cc <tcp_receive+0xb08>)
80141f2: 6013 str r3, [r2, #0]
pcb->rcv_nxt += TCP_TCPLEN(cseg);
80141f4: 68bb ldr r3, [r7, #8]
80141f6: 891b ldrh r3, [r3, #8]
80141f8: 461c mov r4, r3
80141fa: 68bb ldr r3, [r7, #8]
80141fc: 68db ldr r3, [r3, #12]
80141fe: 899b ldrh r3, [r3, #12]
8014200: b29b uxth r3, r3
8014202: 4618 mov r0, r3
8014204: f7fa fe3c bl 800ee80 <lwip_htons>
8014208: 4603 mov r3, r0
801420a: b2db uxtb r3, r3
801420c: f003 0303 and.w r3, r3, #3
8014210: 2b00 cmp r3, #0
8014212: d001 beq.n 8014218 <tcp_receive+0xa54>
8014214: 2301 movs r3, #1
8014216: e000 b.n 801421a <tcp_receive+0xa56>
8014218: 2300 movs r3, #0
801421a: 191a adds r2, r3, r4
801421c: 687b ldr r3, [r7, #4]
801421e: 6a5b ldr r3, [r3, #36] ; 0x24
8014220: 441a add r2, r3
8014222: 687b ldr r3, [r7, #4]
8014224: 625a str r2, [r3, #36] ; 0x24
LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
8014226: 687b ldr r3, [r7, #4]
8014228: 8d1b ldrh r3, [r3, #40] ; 0x28
801422a: 461c mov r4, r3
801422c: 68bb ldr r3, [r7, #8]
801422e: 891b ldrh r3, [r3, #8]
8014230: 461d mov r5, r3
8014232: 68bb ldr r3, [r7, #8]
8014234: 68db ldr r3, [r3, #12]
8014236: 899b ldrh r3, [r3, #12]
8014238: b29b uxth r3, r3
801423a: 4618 mov r0, r3
801423c: f7fa fe20 bl 800ee80 <lwip_htons>
8014240: 4603 mov r3, r0
8014242: b2db uxtb r3, r3
8014244: f003 0303 and.w r3, r3, #3
8014248: 2b00 cmp r3, #0
801424a: d001 beq.n 8014250 <tcp_receive+0xa8c>
801424c: 2301 movs r3, #1
801424e: e000 b.n 8014252 <tcp_receive+0xa8e>
8014250: 2300 movs r3, #0
8014252: 442b add r3, r5
8014254: 429c cmp r4, r3
8014256: d206 bcs.n 8014266 <tcp_receive+0xaa2>
8014258: 4b1e ldr r3, [pc, #120] ; (80142d4 <tcp_receive+0xb10>)
801425a: f240 622c movw r2, #1580 ; 0x62c
801425e: 4923 ldr r1, [pc, #140] ; (80142ec <tcp_receive+0xb28>)
8014260: 481e ldr r0, [pc, #120] ; (80142dc <tcp_receive+0xb18>)
8014262: f006 fed7 bl 801b014 <iprintf>
pcb->rcv_wnd >= TCP_TCPLEN(cseg));
pcb->rcv_wnd -= TCP_TCPLEN(cseg);
8014266: 68bb ldr r3, [r7, #8]
8014268: 891b ldrh r3, [r3, #8]
801426a: 461c mov r4, r3
801426c: 68bb ldr r3, [r7, #8]
801426e: 68db ldr r3, [r3, #12]
8014270: 899b ldrh r3, [r3, #12]
8014272: b29b uxth r3, r3
8014274: 4618 mov r0, r3
8014276: f7fa fe03 bl 800ee80 <lwip_htons>
801427a: 4603 mov r3, r0
801427c: b2db uxtb r3, r3
801427e: f003 0303 and.w r3, r3, #3
8014282: 2b00 cmp r3, #0
8014284: d001 beq.n 801428a <tcp_receive+0xac6>
8014286: 2301 movs r3, #1
8014288: e000 b.n 801428c <tcp_receive+0xac8>
801428a: 2300 movs r3, #0
801428c: 1919 adds r1, r3, r4
801428e: 687b ldr r3, [r7, #4]
8014290: 8d1a ldrh r2, [r3, #40] ; 0x28
8014292: b28b uxth r3, r1
8014294: 1ad3 subs r3, r2, r3
8014296: b29a uxth r2, r3
8014298: 687b ldr r3, [r7, #4]
801429a: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
801429c: 6878 ldr r0, [r7, #4]
801429e: f7fc ff4b bl 8011138 <tcp_update_rcv_ann_wnd>
if (cseg->p->tot_len > 0) {
80142a2: 68bb ldr r3, [r7, #8]
80142a4: 685b ldr r3, [r3, #4]
80142a6: 891b ldrh r3, [r3, #8]
80142a8: 2b00 cmp r3, #0
80142aa: d028 beq.n 80142fe <tcp_receive+0xb3a>
/* Chain this pbuf onto the pbuf that we will pass to
the application. */
/* With window scaling, this can overflow recv_data->tot_len, but
that's not a problem since we explicitly fix that before passing
recv_data to the application. */
if (recv_data) {
80142ac: 4b0d ldr r3, [pc, #52] ; (80142e4 <tcp_receive+0xb20>)
80142ae: 681b ldr r3, [r3, #0]
80142b0: 2b00 cmp r3, #0
80142b2: d01d beq.n 80142f0 <tcp_receive+0xb2c>
pbuf_cat(recv_data, cseg->p);
80142b4: 4b0b ldr r3, [pc, #44] ; (80142e4 <tcp_receive+0xb20>)
80142b6: 681a ldr r2, [r3, #0]
80142b8: 68bb ldr r3, [r7, #8]
80142ba: 685b ldr r3, [r3, #4]
80142bc: 4619 mov r1, r3
80142be: 4610 mov r0, r2
80142c0: f7fc fa60 bl 8010784 <pbuf_cat>
80142c4: e018 b.n 80142f8 <tcp_receive+0xb34>
80142c6: bf00 nop
80142c8: 20008756 .word 0x20008756
80142cc: 2000874c .word 0x2000874c
80142d0: 2000872c .word 0x2000872c
80142d4: 0801d2b0 .word 0x0801d2b0
80142d8: 0801d690 .word 0x0801d690
80142dc: 0801d2fc .word 0x0801d2fc
80142e0: 0801d6cc .word 0x0801d6cc
80142e4: 2000875c .word 0x2000875c
80142e8: 20008759 .word 0x20008759
80142ec: 0801d6ec .word 0x0801d6ec
} else {
recv_data = cseg->p;
80142f0: 68bb ldr r3, [r7, #8]
80142f2: 685b ldr r3, [r3, #4]
80142f4: 4a70 ldr r2, [pc, #448] ; (80144b8 <tcp_receive+0xcf4>)
80142f6: 6013 str r3, [r2, #0]
}
cseg->p = NULL;
80142f8: 68bb ldr r3, [r7, #8]
80142fa: 2200 movs r2, #0
80142fc: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
80142fe: 68bb ldr r3, [r7, #8]
8014300: 68db ldr r3, [r3, #12]
8014302: 899b ldrh r3, [r3, #12]
8014304: b29b uxth r3, r3
8014306: 4618 mov r0, r3
8014308: f7fa fdba bl 800ee80 <lwip_htons>
801430c: 4603 mov r3, r0
801430e: b2db uxtb r3, r3
8014310: f003 0301 and.w r3, r3, #1
8014314: 2b00 cmp r3, #0
8014316: d00d beq.n 8014334 <tcp_receive+0xb70>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
recv_flags |= TF_GOT_FIN;
8014318: 4b68 ldr r3, [pc, #416] ; (80144bc <tcp_receive+0xcf8>)
801431a: 781b ldrb r3, [r3, #0]
801431c: f043 0320 orr.w r3, r3, #32
8014320: b2da uxtb r2, r3
8014322: 4b66 ldr r3, [pc, #408] ; (80144bc <tcp_receive+0xcf8>)
8014324: 701a strb r2, [r3, #0]
if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
8014326: 687b ldr r3, [r7, #4]
8014328: 7d1b ldrb r3, [r3, #20]
801432a: 2b04 cmp r3, #4
801432c: d102 bne.n 8014334 <tcp_receive+0xb70>
pcb->state = CLOSE_WAIT;
801432e: 687b ldr r3, [r7, #4]
8014330: 2207 movs r2, #7
8014332: 751a strb r2, [r3, #20]
}
}
pcb->ooseq = cseg->next;
8014334: 68bb ldr r3, [r7, #8]
8014336: 681a ldr r2, [r3, #0]
8014338: 687b ldr r3, [r7, #4]
801433a: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(cseg);
801433c: 68b8 ldr r0, [r7, #8]
801433e: f7fd fbd7 bl 8011af0 <tcp_seg_free>
while (pcb->ooseq != NULL &&
8014342: 687b ldr r3, [r7, #4]
8014344: 6f5b ldr r3, [r3, #116] ; 0x74
8014346: 2b00 cmp r3, #0
8014348: d008 beq.n 801435c <tcp_receive+0xb98>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
801434a: 687b ldr r3, [r7, #4]
801434c: 6f5b ldr r3, [r3, #116] ; 0x74
801434e: 68db ldr r3, [r3, #12]
8014350: 685a ldr r2, [r3, #4]
8014352: 687b ldr r3, [r7, #4]
8014354: 6a5b ldr r3, [r3, #36] ; 0x24
while (pcb->ooseq != NULL &&
8014356: 429a cmp r2, r3
8014358: f43f af43 beq.w 80141e2 <tcp_receive+0xa1e>
#endif /* LWIP_TCP_SACK_OUT */
#endif /* TCP_QUEUE_OOSEQ */
/* Acknowledge the segment(s). */
tcp_ack(pcb);
801435c: 687b ldr r3, [r7, #4]
801435e: 8b5b ldrh r3, [r3, #26]
8014360: f003 0301 and.w r3, r3, #1
8014364: 2b00 cmp r3, #0
8014366: d00e beq.n 8014386 <tcp_receive+0xbc2>
8014368: 687b ldr r3, [r7, #4]
801436a: 8b5b ldrh r3, [r3, #26]
801436c: f023 0301 bic.w r3, r3, #1
8014370: b29a uxth r2, r3
8014372: 687b ldr r3, [r7, #4]
8014374: 835a strh r2, [r3, #26]
8014376: 687b ldr r3, [r7, #4]
8014378: 8b5b ldrh r3, [r3, #26]
801437a: f043 0302 orr.w r3, r3, #2
801437e: b29a uxth r2, r3
8014380: 687b ldr r3, [r7, #4]
8014382: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
8014384: e188 b.n 8014698 <tcp_receive+0xed4>
tcp_ack(pcb);
8014386: 687b ldr r3, [r7, #4]
8014388: 8b5b ldrh r3, [r3, #26]
801438a: f043 0301 orr.w r3, r3, #1
801438e: b29a uxth r2, r3
8014390: 687b ldr r3, [r7, #4]
8014392: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
8014394: e180 b.n 8014698 <tcp_receive+0xed4>
} else {
/* We get here if the incoming segment is out-of-sequence. */
#if TCP_QUEUE_OOSEQ
/* We queue the segment on the ->ooseq queue. */
if (pcb->ooseq == NULL) {
8014396: 687b ldr r3, [r7, #4]
8014398: 6f5b ldr r3, [r3, #116] ; 0x74
801439a: 2b00 cmp r3, #0
801439c: d106 bne.n 80143ac <tcp_receive+0xbe8>
pcb->ooseq = tcp_seg_copy(&inseg);
801439e: 4848 ldr r0, [pc, #288] ; (80144c0 <tcp_receive+0xcfc>)
80143a0: f7fd fbbe bl 8011b20 <tcp_seg_copy>
80143a4: 4602 mov r2, r0
80143a6: 687b ldr r3, [r7, #4]
80143a8: 675a str r2, [r3, #116] ; 0x74
80143aa: e16d b.n 8014688 <tcp_receive+0xec4>
#if LWIP_TCP_SACK_OUT
/* This is the left edge of the lowest possible SACK range.
It may start before the newly received segment (possibly adjusted below). */
u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
#endif /* LWIP_TCP_SACK_OUT */
struct tcp_seg *next, *prev = NULL;
80143ac: 2300 movs r3, #0
80143ae: 637b str r3, [r7, #52] ; 0x34
for (next = pcb->ooseq; next != NULL; next = next->next) {
80143b0: 687b ldr r3, [r7, #4]
80143b2: 6f5b ldr r3, [r3, #116] ; 0x74
80143b4: 63bb str r3, [r7, #56] ; 0x38
80143b6: e157 b.n 8014668 <tcp_receive+0xea4>
if (seqno == next->tcphdr->seqno) {
80143b8: 6bbb ldr r3, [r7, #56] ; 0x38
80143ba: 68db ldr r3, [r3, #12]
80143bc: 685a ldr r2, [r3, #4]
80143be: 4b41 ldr r3, [pc, #260] ; (80144c4 <tcp_receive+0xd00>)
80143c0: 681b ldr r3, [r3, #0]
80143c2: 429a cmp r2, r3
80143c4: d11d bne.n 8014402 <tcp_receive+0xc3e>
/* The sequence number of the incoming segment is the
same as the sequence number of the segment on
->ooseq. We check the lengths to see which one to
discard. */
if (inseg.len > next->len) {
80143c6: 4b3e ldr r3, [pc, #248] ; (80144c0 <tcp_receive+0xcfc>)
80143c8: 891a ldrh r2, [r3, #8]
80143ca: 6bbb ldr r3, [r7, #56] ; 0x38
80143cc: 891b ldrh r3, [r3, #8]
80143ce: 429a cmp r2, r3
80143d0: f240 814f bls.w 8014672 <tcp_receive+0xeae>
/* The incoming segment is larger than the old
segment. We replace some segments with the new
one. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
80143d4: 483a ldr r0, [pc, #232] ; (80144c0 <tcp_receive+0xcfc>)
80143d6: f7fd fba3 bl 8011b20 <tcp_seg_copy>
80143da: 6178 str r0, [r7, #20]
if (cseg != NULL) {
80143dc: 697b ldr r3, [r7, #20]
80143de: 2b00 cmp r3, #0
80143e0: f000 8149 beq.w 8014676 <tcp_receive+0xeb2>
if (prev != NULL) {
80143e4: 6b7b ldr r3, [r7, #52] ; 0x34
80143e6: 2b00 cmp r3, #0
80143e8: d003 beq.n 80143f2 <tcp_receive+0xc2e>
prev->next = cseg;
80143ea: 6b7b ldr r3, [r7, #52] ; 0x34
80143ec: 697a ldr r2, [r7, #20]
80143ee: 601a str r2, [r3, #0]
80143f0: e002 b.n 80143f8 <tcp_receive+0xc34>
} else {
pcb->ooseq = cseg;
80143f2: 687b ldr r3, [r7, #4]
80143f4: 697a ldr r2, [r7, #20]
80143f6: 675a str r2, [r3, #116] ; 0x74
}
tcp_oos_insert_segment(cseg, next);
80143f8: 6bb9 ldr r1, [r7, #56] ; 0x38
80143fa: 6978 ldr r0, [r7, #20]
80143fc: f7ff f8de bl 80135bc <tcp_oos_insert_segment>
}
break;
8014400: e139 b.n 8014676 <tcp_receive+0xeb2>
segment was smaller than the old one; in either
case, we ditch the incoming segment. */
break;
}
} else {
if (prev == NULL) {
8014402: 6b7b ldr r3, [r7, #52] ; 0x34
8014404: 2b00 cmp r3, #0
8014406: d117 bne.n 8014438 <tcp_receive+0xc74>
if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
8014408: 4b2e ldr r3, [pc, #184] ; (80144c4 <tcp_receive+0xd00>)
801440a: 681a ldr r2, [r3, #0]
801440c: 6bbb ldr r3, [r7, #56] ; 0x38
801440e: 68db ldr r3, [r3, #12]
8014410: 685b ldr r3, [r3, #4]
8014412: 1ad3 subs r3, r2, r3
8014414: 2b00 cmp r3, #0
8014416: da57 bge.n 80144c8 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is lower
than the sequence number of the first segment on the
queue. We put the incoming segment first on the
queue. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
8014418: 4829 ldr r0, [pc, #164] ; (80144c0 <tcp_receive+0xcfc>)
801441a: f7fd fb81 bl 8011b20 <tcp_seg_copy>
801441e: 61b8 str r0, [r7, #24]
if (cseg != NULL) {
8014420: 69bb ldr r3, [r7, #24]
8014422: 2b00 cmp r3, #0
8014424: f000 8129 beq.w 801467a <tcp_receive+0xeb6>
pcb->ooseq = cseg;
8014428: 687b ldr r3, [r7, #4]
801442a: 69ba ldr r2, [r7, #24]
801442c: 675a str r2, [r3, #116] ; 0x74
tcp_oos_insert_segment(cseg, next);
801442e: 6bb9 ldr r1, [r7, #56] ; 0x38
8014430: 69b8 ldr r0, [r7, #24]
8014432: f7ff f8c3 bl 80135bc <tcp_oos_insert_segment>
}
break;
8014436: e120 b.n 801467a <tcp_receive+0xeb6>
}
} else {
/*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
8014438: 4b22 ldr r3, [pc, #136] ; (80144c4 <tcp_receive+0xd00>)
801443a: 681a ldr r2, [r3, #0]
801443c: 6b7b ldr r3, [r7, #52] ; 0x34
801443e: 68db ldr r3, [r3, #12]
8014440: 685b ldr r3, [r3, #4]
8014442: 1ad3 subs r3, r2, r3
8014444: 3b01 subs r3, #1
8014446: 2b00 cmp r3, #0
8014448: db3e blt.n 80144c8 <tcp_receive+0xd04>
801444a: 4b1e ldr r3, [pc, #120] ; (80144c4 <tcp_receive+0xd00>)
801444c: 681a ldr r2, [r3, #0]
801444e: 6bbb ldr r3, [r7, #56] ; 0x38
8014450: 68db ldr r3, [r3, #12]
8014452: 685b ldr r3, [r3, #4]
8014454: 1ad3 subs r3, r2, r3
8014456: 3301 adds r3, #1
8014458: 2b00 cmp r3, #0
801445a: dc35 bgt.n 80144c8 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is in
between the sequence numbers of the previous and
the next segment on ->ooseq. We trim trim the previous
segment, delete next segments that included in received segment
and trim received, if needed. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
801445c: 4818 ldr r0, [pc, #96] ; (80144c0 <tcp_receive+0xcfc>)
801445e: f7fd fb5f bl 8011b20 <tcp_seg_copy>
8014462: 61f8 str r0, [r7, #28]
if (cseg != NULL) {
8014464: 69fb ldr r3, [r7, #28]
8014466: 2b00 cmp r3, #0
8014468: f000 8109 beq.w 801467e <tcp_receive+0xeba>
if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
801446c: 6b7b ldr r3, [r7, #52] ; 0x34
801446e: 68db ldr r3, [r3, #12]
8014470: 685b ldr r3, [r3, #4]
8014472: 6b7a ldr r2, [r7, #52] ; 0x34
8014474: 8912 ldrh r2, [r2, #8]
8014476: 441a add r2, r3
8014478: 4b12 ldr r3, [pc, #72] ; (80144c4 <tcp_receive+0xd00>)
801447a: 681b ldr r3, [r3, #0]
801447c: 1ad3 subs r3, r2, r3
801447e: 2b00 cmp r3, #0
8014480: dd12 ble.n 80144a8 <tcp_receive+0xce4>
/* We need to trim the prev segment. */
prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
8014482: 4b10 ldr r3, [pc, #64] ; (80144c4 <tcp_receive+0xd00>)
8014484: 681b ldr r3, [r3, #0]
8014486: b29a uxth r2, r3
8014488: 6b7b ldr r3, [r7, #52] ; 0x34
801448a: 68db ldr r3, [r3, #12]
801448c: 685b ldr r3, [r3, #4]
801448e: b29b uxth r3, r3
8014490: 1ad3 subs r3, r2, r3
8014492: b29a uxth r2, r3
8014494: 6b7b ldr r3, [r7, #52] ; 0x34
8014496: 811a strh r2, [r3, #8]
pbuf_realloc(prev->p, prev->len);
8014498: 6b7b ldr r3, [r7, #52] ; 0x34
801449a: 685a ldr r2, [r3, #4]
801449c: 6b7b ldr r3, [r7, #52] ; 0x34
801449e: 891b ldrh r3, [r3, #8]
80144a0: 4619 mov r1, r3
80144a2: 4610 mov r0, r2
80144a4: f7fb ff1a bl 80102dc <pbuf_realloc>
}
prev->next = cseg;
80144a8: 6b7b ldr r3, [r7, #52] ; 0x34
80144aa: 69fa ldr r2, [r7, #28]
80144ac: 601a str r2, [r3, #0]
tcp_oos_insert_segment(cseg, next);
80144ae: 6bb9 ldr r1, [r7, #56] ; 0x38
80144b0: 69f8 ldr r0, [r7, #28]
80144b2: f7ff f883 bl 80135bc <tcp_oos_insert_segment>
}
break;
80144b6: e0e2 b.n 801467e <tcp_receive+0xeba>
80144b8: 2000875c .word 0x2000875c
80144bc: 20008759 .word 0x20008759
80144c0: 2000872c .word 0x2000872c
80144c4: 2000874c .word 0x2000874c
#endif /* LWIP_TCP_SACK_OUT */
/* We don't use 'prev' below, so let's set it to current 'next'.
This way even if we break the loop below, 'prev' will be pointing
at the segment right in front of the newly added one. */
prev = next;
80144c8: 6bbb ldr r3, [r7, #56] ; 0x38
80144ca: 637b str r3, [r7, #52] ; 0x34
/* If the "next" segment is the last segment on the
ooseq queue, we add the incoming segment to the end
of the list. */
if (next->next == NULL &&
80144cc: 6bbb ldr r3, [r7, #56] ; 0x38
80144ce: 681b ldr r3, [r3, #0]
80144d0: 2b00 cmp r3, #0
80144d2: f040 80c6 bne.w 8014662 <tcp_receive+0xe9e>
TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
80144d6: 4b80 ldr r3, [pc, #512] ; (80146d8 <tcp_receive+0xf14>)
80144d8: 681a ldr r2, [r3, #0]
80144da: 6bbb ldr r3, [r7, #56] ; 0x38
80144dc: 68db ldr r3, [r3, #12]
80144de: 685b ldr r3, [r3, #4]
80144e0: 1ad3 subs r3, r2, r3
if (next->next == NULL &&
80144e2: 2b00 cmp r3, #0
80144e4: f340 80bd ble.w 8014662 <tcp_receive+0xe9e>
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
80144e8: 6bbb ldr r3, [r7, #56] ; 0x38
80144ea: 68db ldr r3, [r3, #12]
80144ec: 899b ldrh r3, [r3, #12]
80144ee: b29b uxth r3, r3
80144f0: 4618 mov r0, r3
80144f2: f7fa fcc5 bl 800ee80 <lwip_htons>
80144f6: 4603 mov r3, r0
80144f8: b2db uxtb r3, r3
80144fa: f003 0301 and.w r3, r3, #1
80144fe: 2b00 cmp r3, #0
8014500: f040 80bf bne.w 8014682 <tcp_receive+0xebe>
/* segment "next" already contains all data */
break;
}
next->next = tcp_seg_copy(&inseg);
8014504: 4875 ldr r0, [pc, #468] ; (80146dc <tcp_receive+0xf18>)
8014506: f7fd fb0b bl 8011b20 <tcp_seg_copy>
801450a: 4602 mov r2, r0
801450c: 6bbb ldr r3, [r7, #56] ; 0x38
801450e: 601a str r2, [r3, #0]
if (next->next != NULL) {
8014510: 6bbb ldr r3, [r7, #56] ; 0x38
8014512: 681b ldr r3, [r3, #0]
8014514: 2b00 cmp r3, #0
8014516: f000 80b6 beq.w 8014686 <tcp_receive+0xec2>
if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
801451a: 6bbb ldr r3, [r7, #56] ; 0x38
801451c: 68db ldr r3, [r3, #12]
801451e: 685b ldr r3, [r3, #4]
8014520: 6bba ldr r2, [r7, #56] ; 0x38
8014522: 8912 ldrh r2, [r2, #8]
8014524: 441a add r2, r3
8014526: 4b6c ldr r3, [pc, #432] ; (80146d8 <tcp_receive+0xf14>)
8014528: 681b ldr r3, [r3, #0]
801452a: 1ad3 subs r3, r2, r3
801452c: 2b00 cmp r3, #0
801452e: dd12 ble.n 8014556 <tcp_receive+0xd92>
/* We need to trim the last segment. */
next->len = (u16_t)(seqno - next->tcphdr->seqno);
8014530: 4b69 ldr r3, [pc, #420] ; (80146d8 <tcp_receive+0xf14>)
8014532: 681b ldr r3, [r3, #0]
8014534: b29a uxth r2, r3
8014536: 6bbb ldr r3, [r7, #56] ; 0x38
8014538: 68db ldr r3, [r3, #12]
801453a: 685b ldr r3, [r3, #4]
801453c: b29b uxth r3, r3
801453e: 1ad3 subs r3, r2, r3
8014540: b29a uxth r2, r3
8014542: 6bbb ldr r3, [r7, #56] ; 0x38
8014544: 811a strh r2, [r3, #8]
pbuf_realloc(next->p, next->len);
8014546: 6bbb ldr r3, [r7, #56] ; 0x38
8014548: 685a ldr r2, [r3, #4]
801454a: 6bbb ldr r3, [r7, #56] ; 0x38
801454c: 891b ldrh r3, [r3, #8]
801454e: 4619 mov r1, r3
8014550: 4610 mov r0, r2
8014552: f7fb fec3 bl 80102dc <pbuf_realloc>
}
/* check if the remote side overruns our receive window */
if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
8014556: 4b62 ldr r3, [pc, #392] ; (80146e0 <tcp_receive+0xf1c>)
8014558: 881b ldrh r3, [r3, #0]
801455a: 461a mov r2, r3
801455c: 4b5e ldr r3, [pc, #376] ; (80146d8 <tcp_receive+0xf14>)
801455e: 681b ldr r3, [r3, #0]
8014560: 441a add r2, r3
8014562: 687b ldr r3, [r7, #4]
8014564: 6a5b ldr r3, [r3, #36] ; 0x24
8014566: 6879 ldr r1, [r7, #4]
8014568: 8d09 ldrh r1, [r1, #40] ; 0x28
801456a: 440b add r3, r1
801456c: 1ad3 subs r3, r2, r3
801456e: 2b00 cmp r3, #0
8014570: f340 8089 ble.w 8014686 <tcp_receive+0xec2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
8014574: 6bbb ldr r3, [r7, #56] ; 0x38
8014576: 681b ldr r3, [r3, #0]
8014578: 68db ldr r3, [r3, #12]
801457a: 899b ldrh r3, [r3, #12]
801457c: b29b uxth r3, r3
801457e: 4618 mov r0, r3
8014580: f7fa fc7e bl 800ee80 <lwip_htons>
8014584: 4603 mov r3, r0
8014586: b2db uxtb r3, r3
8014588: f003 0301 and.w r3, r3, #1
801458c: 2b00 cmp r3, #0
801458e: d022 beq.n 80145d6 <tcp_receive+0xe12>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
8014590: 6bbb ldr r3, [r7, #56] ; 0x38
8014592: 681b ldr r3, [r3, #0]
8014594: 68db ldr r3, [r3, #12]
8014596: 899b ldrh r3, [r3, #12]
8014598: b29b uxth r3, r3
801459a: b21b sxth r3, r3
801459c: f423 537c bic.w r3, r3, #16128 ; 0x3f00
80145a0: b21c sxth r4, r3
80145a2: 6bbb ldr r3, [r7, #56] ; 0x38
80145a4: 681b ldr r3, [r3, #0]
80145a6: 68db ldr r3, [r3, #12]
80145a8: 899b ldrh r3, [r3, #12]
80145aa: b29b uxth r3, r3
80145ac: 4618 mov r0, r3
80145ae: f7fa fc67 bl 800ee80 <lwip_htons>
80145b2: 4603 mov r3, r0
80145b4: b2db uxtb r3, r3
80145b6: b29b uxth r3, r3
80145b8: f003 033e and.w r3, r3, #62 ; 0x3e
80145bc: b29b uxth r3, r3
80145be: 4618 mov r0, r3
80145c0: f7fa fc5e bl 800ee80 <lwip_htons>
80145c4: 4603 mov r3, r0
80145c6: b21b sxth r3, r3
80145c8: 4323 orrs r3, r4
80145ca: b21a sxth r2, r3
80145cc: 6bbb ldr r3, [r7, #56] ; 0x38
80145ce: 681b ldr r3, [r3, #0]
80145d0: 68db ldr r3, [r3, #12]
80145d2: b292 uxth r2, r2
80145d4: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
80145d6: 687b ldr r3, [r7, #4]
80145d8: 6a5b ldr r3, [r3, #36] ; 0x24
80145da: b29a uxth r2, r3
80145dc: 687b ldr r3, [r7, #4]
80145de: 8d1b ldrh r3, [r3, #40] ; 0x28
80145e0: 4413 add r3, r2
80145e2: b299 uxth r1, r3
80145e4: 4b3c ldr r3, [pc, #240] ; (80146d8 <tcp_receive+0xf14>)
80145e6: 681b ldr r3, [r3, #0]
80145e8: b29a uxth r2, r3
80145ea: 6bbb ldr r3, [r7, #56] ; 0x38
80145ec: 681b ldr r3, [r3, #0]
80145ee: 1a8a subs r2, r1, r2
80145f0: b292 uxth r2, r2
80145f2: 811a strh r2, [r3, #8]
pbuf_realloc(next->next->p, next->next->len);
80145f4: 6bbb ldr r3, [r7, #56] ; 0x38
80145f6: 681b ldr r3, [r3, #0]
80145f8: 685a ldr r2, [r3, #4]
80145fa: 6bbb ldr r3, [r7, #56] ; 0x38
80145fc: 681b ldr r3, [r3, #0]
80145fe: 891b ldrh r3, [r3, #8]
8014600: 4619 mov r1, r3
8014602: 4610 mov r0, r2
8014604: f7fb fe6a bl 80102dc <pbuf_realloc>
tcplen = TCP_TCPLEN(next->next);
8014608: 6bbb ldr r3, [r7, #56] ; 0x38
801460a: 681b ldr r3, [r3, #0]
801460c: 891c ldrh r4, [r3, #8]
801460e: 6bbb ldr r3, [r7, #56] ; 0x38
8014610: 681b ldr r3, [r3, #0]
8014612: 68db ldr r3, [r3, #12]
8014614: 899b ldrh r3, [r3, #12]
8014616: b29b uxth r3, r3
8014618: 4618 mov r0, r3
801461a: f7fa fc31 bl 800ee80 <lwip_htons>
801461e: 4603 mov r3, r0
8014620: b2db uxtb r3, r3
8014622: f003 0303 and.w r3, r3, #3
8014626: 2b00 cmp r3, #0
8014628: d001 beq.n 801462e <tcp_receive+0xe6a>
801462a: 2301 movs r3, #1
801462c: e000 b.n 8014630 <tcp_receive+0xe6c>
801462e: 2300 movs r3, #0
8014630: 4423 add r3, r4
8014632: b29a uxth r2, r3
8014634: 4b2a ldr r3, [pc, #168] ; (80146e0 <tcp_receive+0xf1c>)
8014636: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8014638: 4b29 ldr r3, [pc, #164] ; (80146e0 <tcp_receive+0xf1c>)
801463a: 881b ldrh r3, [r3, #0]
801463c: 461a mov r2, r3
801463e: 4b26 ldr r3, [pc, #152] ; (80146d8 <tcp_receive+0xf14>)
8014640: 681b ldr r3, [r3, #0]
8014642: 441a add r2, r3
8014644: 687b ldr r3, [r7, #4]
8014646: 6a5b ldr r3, [r3, #36] ; 0x24
8014648: 6879 ldr r1, [r7, #4]
801464a: 8d09 ldrh r1, [r1, #40] ; 0x28
801464c: 440b add r3, r1
801464e: 429a cmp r2, r3
8014650: d019 beq.n 8014686 <tcp_receive+0xec2>
8014652: 4b24 ldr r3, [pc, #144] ; (80146e4 <tcp_receive+0xf20>)
8014654: f240 62f9 movw r2, #1785 ; 0x6f9
8014658: 4923 ldr r1, [pc, #140] ; (80146e8 <tcp_receive+0xf24>)
801465a: 4824 ldr r0, [pc, #144] ; (80146ec <tcp_receive+0xf28>)
801465c: f006 fcda bl 801b014 <iprintf>
(seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
}
}
break;
8014660: e011 b.n 8014686 <tcp_receive+0xec2>
for (next = pcb->ooseq; next != NULL; next = next->next) {
8014662: 6bbb ldr r3, [r7, #56] ; 0x38
8014664: 681b ldr r3, [r3, #0]
8014666: 63bb str r3, [r7, #56] ; 0x38
8014668: 6bbb ldr r3, [r7, #56] ; 0x38
801466a: 2b00 cmp r3, #0
801466c: f47f aea4 bne.w 80143b8 <tcp_receive+0xbf4>
8014670: e00a b.n 8014688 <tcp_receive+0xec4>
break;
8014672: bf00 nop
8014674: e008 b.n 8014688 <tcp_receive+0xec4>
break;
8014676: bf00 nop
8014678: e006 b.n 8014688 <tcp_receive+0xec4>
break;
801467a: bf00 nop
801467c: e004 b.n 8014688 <tcp_receive+0xec4>
break;
801467e: bf00 nop
8014680: e002 b.n 8014688 <tcp_receive+0xec4>
break;
8014682: bf00 nop
8014684: e000 b.n 8014688 <tcp_receive+0xec4>
break;
8014686: bf00 nop
#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
#endif /* TCP_QUEUE_OOSEQ */
/* We send the ACK packet after we've (potentially) dealt with SACKs,
so they can be included in the acknowledgment. */
tcp_send_empty_ack(pcb);
8014688: 6878 ldr r0, [r7, #4]
801468a: f001 fa43 bl 8015b14 <tcp_send_empty_ack>
if (pcb->rcv_nxt == seqno) {
801468e: e003 b.n 8014698 <tcp_receive+0xed4>
}
} else {
/* The incoming segment is not within the window. */
tcp_send_empty_ack(pcb);
8014690: 6878 ldr r0, [r7, #4]
8014692: f001 fa3f bl 8015b14 <tcp_send_empty_ack>
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8014696: e01a b.n 80146ce <tcp_receive+0xf0a>
8014698: e019 b.n 80146ce <tcp_receive+0xf0a>
}
} else {
/* Segments with length 0 is taken care of here. Segments that
fall out of the window are ACKed. */
if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
801469a: 4b0f ldr r3, [pc, #60] ; (80146d8 <tcp_receive+0xf14>)
801469c: 681a ldr r2, [r3, #0]
801469e: 687b ldr r3, [r7, #4]
80146a0: 6a5b ldr r3, [r3, #36] ; 0x24
80146a2: 1ad3 subs r3, r2, r3
80146a4: 2b00 cmp r3, #0
80146a6: db0a blt.n 80146be <tcp_receive+0xefa>
80146a8: 4b0b ldr r3, [pc, #44] ; (80146d8 <tcp_receive+0xf14>)
80146aa: 681a ldr r2, [r3, #0]
80146ac: 687b ldr r3, [r7, #4]
80146ae: 6a5b ldr r3, [r3, #36] ; 0x24
80146b0: 6879 ldr r1, [r7, #4]
80146b2: 8d09 ldrh r1, [r1, #40] ; 0x28
80146b4: 440b add r3, r1
80146b6: 1ad3 subs r3, r2, r3
80146b8: 3301 adds r3, #1
80146ba: 2b00 cmp r3, #0
80146bc: dd07 ble.n 80146ce <tcp_receive+0xf0a>
tcp_ack_now(pcb);
80146be: 687b ldr r3, [r7, #4]
80146c0: 8b5b ldrh r3, [r3, #26]
80146c2: f043 0302 orr.w r3, r3, #2
80146c6: b29a uxth r2, r3
80146c8: 687b ldr r3, [r7, #4]
80146ca: 835a strh r2, [r3, #26]
}
}
}
80146cc: e7ff b.n 80146ce <tcp_receive+0xf0a>
80146ce: bf00 nop
80146d0: 3750 adds r7, #80 ; 0x50
80146d2: 46bd mov sp, r7
80146d4: bdb0 pop {r4, r5, r7, pc}
80146d6: bf00 nop
80146d8: 2000874c .word 0x2000874c
80146dc: 2000872c .word 0x2000872c
80146e0: 20008756 .word 0x20008756
80146e4: 0801d2b0 .word 0x0801d2b0
80146e8: 0801d658 .word 0x0801d658
80146ec: 0801d2fc .word 0x0801d2fc
080146f0 <tcp_get_next_optbyte>:
static u8_t
tcp_get_next_optbyte(void)
{
80146f0: b480 push {r7}
80146f2: b083 sub sp, #12
80146f4: af00 add r7, sp, #0
u16_t optidx = tcp_optidx++;
80146f6: 4b15 ldr r3, [pc, #84] ; (801474c <tcp_get_next_optbyte+0x5c>)
80146f8: 881b ldrh r3, [r3, #0]
80146fa: 1c5a adds r2, r3, #1
80146fc: b291 uxth r1, r2
80146fe: 4a13 ldr r2, [pc, #76] ; (801474c <tcp_get_next_optbyte+0x5c>)
8014700: 8011 strh r1, [r2, #0]
8014702: 80fb strh r3, [r7, #6]
if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
8014704: 4b12 ldr r3, [pc, #72] ; (8014750 <tcp_get_next_optbyte+0x60>)
8014706: 681b ldr r3, [r3, #0]
8014708: 2b00 cmp r3, #0
801470a: d004 beq.n 8014716 <tcp_get_next_optbyte+0x26>
801470c: 4b11 ldr r3, [pc, #68] ; (8014754 <tcp_get_next_optbyte+0x64>)
801470e: 881b ldrh r3, [r3, #0]
8014710: 88fa ldrh r2, [r7, #6]
8014712: 429a cmp r2, r3
8014714: d208 bcs.n 8014728 <tcp_get_next_optbyte+0x38>
u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
8014716: 4b10 ldr r3, [pc, #64] ; (8014758 <tcp_get_next_optbyte+0x68>)
8014718: 681b ldr r3, [r3, #0]
801471a: 3314 adds r3, #20
801471c: 603b str r3, [r7, #0]
return opts[optidx];
801471e: 88fb ldrh r3, [r7, #6]
8014720: 683a ldr r2, [r7, #0]
8014722: 4413 add r3, r2
8014724: 781b ldrb r3, [r3, #0]
8014726: e00b b.n 8014740 <tcp_get_next_optbyte+0x50>
} else {
u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
8014728: 88fb ldrh r3, [r7, #6]
801472a: b2da uxtb r2, r3
801472c: 4b09 ldr r3, [pc, #36] ; (8014754 <tcp_get_next_optbyte+0x64>)
801472e: 881b ldrh r3, [r3, #0]
8014730: b2db uxtb r3, r3
8014732: 1ad3 subs r3, r2, r3
8014734: 717b strb r3, [r7, #5]
return tcphdr_opt2[idx];
8014736: 4b06 ldr r3, [pc, #24] ; (8014750 <tcp_get_next_optbyte+0x60>)
8014738: 681a ldr r2, [r3, #0]
801473a: 797b ldrb r3, [r7, #5]
801473c: 4413 add r3, r2
801473e: 781b ldrb r3, [r3, #0]
}
}
8014740: 4618 mov r0, r3
8014742: 370c adds r7, #12
8014744: 46bd mov sp, r7
8014746: f85d 7b04 ldr.w r7, [sp], #4
801474a: 4770 bx lr
801474c: 20008748 .word 0x20008748
8014750: 20008744 .word 0x20008744
8014754: 20008742 .word 0x20008742
8014758: 2000873c .word 0x2000873c
0801475c <tcp_parseopt>:
*
* @param pcb the tcp_pcb for which a segment arrived
*/
static void
tcp_parseopt(struct tcp_pcb *pcb)
{
801475c: b580 push {r7, lr}
801475e: b084 sub sp, #16
8014760: af00 add r7, sp, #0
8014762: 6078 str r0, [r7, #4]
u16_t mss;
#if LWIP_TCP_TIMESTAMPS
u32_t tsval;
#endif
LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
8014764: 687b ldr r3, [r7, #4]
8014766: 2b00 cmp r3, #0
8014768: d106 bne.n 8014778 <tcp_parseopt+0x1c>
801476a: 4b31 ldr r3, [pc, #196] ; (8014830 <tcp_parseopt+0xd4>)
801476c: f240 727d movw r2, #1917 ; 0x77d
8014770: 4930 ldr r1, [pc, #192] ; (8014834 <tcp_parseopt+0xd8>)
8014772: 4831 ldr r0, [pc, #196] ; (8014838 <tcp_parseopt+0xdc>)
8014774: f006 fc4e bl 801b014 <iprintf>
/* Parse the TCP MSS option, if present. */
if (tcphdr_optlen != 0) {
8014778: 4b30 ldr r3, [pc, #192] ; (801483c <tcp_parseopt+0xe0>)
801477a: 881b ldrh r3, [r3, #0]
801477c: 2b00 cmp r3, #0
801477e: d053 beq.n 8014828 <tcp_parseopt+0xcc>
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
8014780: 4b2f ldr r3, [pc, #188] ; (8014840 <tcp_parseopt+0xe4>)
8014782: 2200 movs r2, #0
8014784: 801a strh r2, [r3, #0]
8014786: e043 b.n 8014810 <tcp_parseopt+0xb4>
u8_t opt = tcp_get_next_optbyte();
8014788: f7ff ffb2 bl 80146f0 <tcp_get_next_optbyte>
801478c: 4603 mov r3, r0
801478e: 73fb strb r3, [r7, #15]
switch (opt) {
8014790: 7bfb ldrb r3, [r7, #15]
8014792: 2b01 cmp r3, #1
8014794: d03c beq.n 8014810 <tcp_parseopt+0xb4>
8014796: 2b02 cmp r3, #2
8014798: d002 beq.n 80147a0 <tcp_parseopt+0x44>
801479a: 2b00 cmp r3, #0
801479c: d03f beq.n 801481e <tcp_parseopt+0xc2>
801479e: e026 b.n 80147ee <tcp_parseopt+0x92>
/* NOP option. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
break;
case LWIP_TCP_OPT_MSS:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
80147a0: f7ff ffa6 bl 80146f0 <tcp_get_next_optbyte>
80147a4: 4603 mov r3, r0
80147a6: 2b04 cmp r3, #4
80147a8: d13b bne.n 8014822 <tcp_parseopt+0xc6>
80147aa: 4b25 ldr r3, [pc, #148] ; (8014840 <tcp_parseopt+0xe4>)
80147ac: 881b ldrh r3, [r3, #0]
80147ae: 3302 adds r3, #2
80147b0: 4a22 ldr r2, [pc, #136] ; (801483c <tcp_parseopt+0xe0>)
80147b2: 8812 ldrh r2, [r2, #0]
80147b4: 4293 cmp r3, r2
80147b6: dc34 bgt.n 8014822 <tcp_parseopt+0xc6>
/* Bad length */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
return;
}
/* An MSS option with the right option length. */
mss = (u16_t)(tcp_get_next_optbyte() << 8);
80147b8: f7ff ff9a bl 80146f0 <tcp_get_next_optbyte>
80147bc: 4603 mov r3, r0
80147be: b29b uxth r3, r3
80147c0: 021b lsls r3, r3, #8
80147c2: 81bb strh r3, [r7, #12]
mss |= tcp_get_next_optbyte();
80147c4: f7ff ff94 bl 80146f0 <tcp_get_next_optbyte>
80147c8: 4603 mov r3, r0
80147ca: b29a uxth r2, r3
80147cc: 89bb ldrh r3, [r7, #12]
80147ce: 4313 orrs r3, r2
80147d0: 81bb strh r3, [r7, #12]
/* Limit the mss to the configured TCP_MSS and prevent division by zero */
pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
80147d2: 89bb ldrh r3, [r7, #12]
80147d4: f5b3 7f06 cmp.w r3, #536 ; 0x218
80147d8: d804 bhi.n 80147e4 <tcp_parseopt+0x88>
80147da: 89bb ldrh r3, [r7, #12]
80147dc: 2b00 cmp r3, #0
80147de: d001 beq.n 80147e4 <tcp_parseopt+0x88>
80147e0: 89ba ldrh r2, [r7, #12]
80147e2: e001 b.n 80147e8 <tcp_parseopt+0x8c>
80147e4: f44f 7206 mov.w r2, #536 ; 0x218
80147e8: 687b ldr r3, [r7, #4]
80147ea: 865a strh r2, [r3, #50] ; 0x32
break;
80147ec: e010 b.n 8014810 <tcp_parseopt+0xb4>
}
break;
#endif /* LWIP_TCP_SACK_OUT */
default:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
data = tcp_get_next_optbyte();
80147ee: f7ff ff7f bl 80146f0 <tcp_get_next_optbyte>
80147f2: 4603 mov r3, r0
80147f4: 72fb strb r3, [r7, #11]
if (data < 2) {
80147f6: 7afb ldrb r3, [r7, #11]
80147f8: 2b01 cmp r3, #1
80147fa: d914 bls.n 8014826 <tcp_parseopt+0xca>
and we don't process them further. */
return;
}
/* All other options have a length field, so that we easily
can skip past them. */
tcp_optidx += data - 2;
80147fc: 7afb ldrb r3, [r7, #11]
80147fe: b29a uxth r2, r3
8014800: 4b0f ldr r3, [pc, #60] ; (8014840 <tcp_parseopt+0xe4>)
8014802: 881b ldrh r3, [r3, #0]
8014804: 4413 add r3, r2
8014806: b29b uxth r3, r3
8014808: 3b02 subs r3, #2
801480a: b29a uxth r2, r3
801480c: 4b0c ldr r3, [pc, #48] ; (8014840 <tcp_parseopt+0xe4>)
801480e: 801a strh r2, [r3, #0]
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
8014810: 4b0b ldr r3, [pc, #44] ; (8014840 <tcp_parseopt+0xe4>)
8014812: 881a ldrh r2, [r3, #0]
8014814: 4b09 ldr r3, [pc, #36] ; (801483c <tcp_parseopt+0xe0>)
8014816: 881b ldrh r3, [r3, #0]
8014818: 429a cmp r2, r3
801481a: d3b5 bcc.n 8014788 <tcp_parseopt+0x2c>
801481c: e004 b.n 8014828 <tcp_parseopt+0xcc>
return;
801481e: bf00 nop
8014820: e002 b.n 8014828 <tcp_parseopt+0xcc>
return;
8014822: bf00 nop
8014824: e000 b.n 8014828 <tcp_parseopt+0xcc>
return;
8014826: bf00 nop
}
}
}
}
8014828: 3710 adds r7, #16
801482a: 46bd mov sp, r7
801482c: bd80 pop {r7, pc}
801482e: bf00 nop
8014830: 0801d2b0 .word 0x0801d2b0
8014834: 0801d714 .word 0x0801d714
8014838: 0801d2fc .word 0x0801d2fc
801483c: 20008740 .word 0x20008740
8014840: 20008748 .word 0x20008748
08014844 <tcp_trigger_input_pcb_close>:
void
tcp_trigger_input_pcb_close(void)
{
8014844: b480 push {r7}
8014846: af00 add r7, sp, #0
recv_flags |= TF_CLOSED;
8014848: 4b05 ldr r3, [pc, #20] ; (8014860 <tcp_trigger_input_pcb_close+0x1c>)
801484a: 781b ldrb r3, [r3, #0]
801484c: f043 0310 orr.w r3, r3, #16
8014850: b2da uxtb r2, r3
8014852: 4b03 ldr r3, [pc, #12] ; (8014860 <tcp_trigger_input_pcb_close+0x1c>)
8014854: 701a strb r2, [r3, #0]
}
8014856: bf00 nop
8014858: 46bd mov sp, r7
801485a: f85d 7b04 ldr.w r7, [sp], #4
801485e: 4770 bx lr
8014860: 20008759 .word 0x20008759
08014864 <tcp_route>:
static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
static struct netif *
tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
{
8014864: b580 push {r7, lr}
8014866: b084 sub sp, #16
8014868: af00 add r7, sp, #0
801486a: 60f8 str r0, [r7, #12]
801486c: 60b9 str r1, [r7, #8]
801486e: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
8014870: 68fb ldr r3, [r7, #12]
8014872: 2b00 cmp r3, #0
8014874: d00a beq.n 801488c <tcp_route+0x28>
8014876: 68fb ldr r3, [r7, #12]
8014878: 7a1b ldrb r3, [r3, #8]
801487a: 2b00 cmp r3, #0
801487c: d006 beq.n 801488c <tcp_route+0x28>
return netif_get_by_index(pcb->netif_idx);
801487e: 68fb ldr r3, [r7, #12]
8014880: 7a1b ldrb r3, [r3, #8]
8014882: 4618 mov r0, r3
8014884: f7fb fb26 bl 800fed4 <netif_get_by_index>
8014888: 4603 mov r3, r0
801488a: e003 b.n 8014894 <tcp_route+0x30>
} else {
return ip_route(src, dst);
801488c: 6878 ldr r0, [r7, #4]
801488e: f005 f867 bl 8019960 <ip4_route>
8014892: 4603 mov r3, r0
}
}
8014894: 4618 mov r0, r3
8014896: 3710 adds r7, #16
8014898: 46bd mov sp, r7
801489a: bd80 pop {r7, pc}
0801489c <tcp_create_segment>:
* The TCP header is filled in except ackno and wnd.
* p is freed on failure.
*/
static struct tcp_seg *
tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
{
801489c: b590 push {r4, r7, lr}
801489e: b087 sub sp, #28
80148a0: af00 add r7, sp, #0
80148a2: 60f8 str r0, [r7, #12]
80148a4: 60b9 str r1, [r7, #8]
80148a6: 603b str r3, [r7, #0]
80148a8: 4613 mov r3, r2
80148aa: 71fb strb r3, [r7, #7]
struct tcp_seg *seg;
u8_t optlen;
LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
80148ac: 68fb ldr r3, [r7, #12]
80148ae: 2b00 cmp r3, #0
80148b0: d105 bne.n 80148be <tcp_create_segment+0x22>
80148b2: 4b44 ldr r3, [pc, #272] ; (80149c4 <tcp_create_segment+0x128>)
80148b4: 22a3 movs r2, #163 ; 0xa3
80148b6: 4944 ldr r1, [pc, #272] ; (80149c8 <tcp_create_segment+0x12c>)
80148b8: 4844 ldr r0, [pc, #272] ; (80149cc <tcp_create_segment+0x130>)
80148ba: f006 fbab bl 801b014 <iprintf>
LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
80148be: 68bb ldr r3, [r7, #8]
80148c0: 2b00 cmp r3, #0
80148c2: d105 bne.n 80148d0 <tcp_create_segment+0x34>
80148c4: 4b3f ldr r3, [pc, #252] ; (80149c4 <tcp_create_segment+0x128>)
80148c6: 22a4 movs r2, #164 ; 0xa4
80148c8: 4941 ldr r1, [pc, #260] ; (80149d0 <tcp_create_segment+0x134>)
80148ca: 4840 ldr r0, [pc, #256] ; (80149cc <tcp_create_segment+0x130>)
80148cc: f006 fba2 bl 801b014 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
80148d0: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
80148d4: 009b lsls r3, r3, #2
80148d6: b2db uxtb r3, r3
80148d8: f003 0304 and.w r3, r3, #4
80148dc: 75fb strb r3, [r7, #23]
if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
80148de: 2003 movs r0, #3
80148e0: f7fa ff84 bl 800f7ec <memp_malloc>
80148e4: 6138 str r0, [r7, #16]
80148e6: 693b ldr r3, [r7, #16]
80148e8: 2b00 cmp r3, #0
80148ea: d104 bne.n 80148f6 <tcp_create_segment+0x5a>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
pbuf_free(p);
80148ec: 68b8 ldr r0, [r7, #8]
80148ee: f7fb fe7b bl 80105e8 <pbuf_free>
return NULL;
80148f2: 2300 movs r3, #0
80148f4: e061 b.n 80149ba <tcp_create_segment+0x11e>
}
seg->flags = optflags;
80148f6: 693b ldr r3, [r7, #16]
80148f8: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
80148fc: 729a strb r2, [r3, #10]
seg->next = NULL;
80148fe: 693b ldr r3, [r7, #16]
8014900: 2200 movs r2, #0
8014902: 601a str r2, [r3, #0]
seg->p = p;
8014904: 693b ldr r3, [r7, #16]
8014906: 68ba ldr r2, [r7, #8]
8014908: 605a str r2, [r3, #4]
LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
801490a: 68bb ldr r3, [r7, #8]
801490c: 891a ldrh r2, [r3, #8]
801490e: 7dfb ldrb r3, [r7, #23]
8014910: b29b uxth r3, r3
8014912: 429a cmp r2, r3
8014914: d205 bcs.n 8014922 <tcp_create_segment+0x86>
8014916: 4b2b ldr r3, [pc, #172] ; (80149c4 <tcp_create_segment+0x128>)
8014918: 22b0 movs r2, #176 ; 0xb0
801491a: 492e ldr r1, [pc, #184] ; (80149d4 <tcp_create_segment+0x138>)
801491c: 482b ldr r0, [pc, #172] ; (80149cc <tcp_create_segment+0x130>)
801491e: f006 fb79 bl 801b014 <iprintf>
seg->len = p->tot_len - optlen;
8014922: 68bb ldr r3, [r7, #8]
8014924: 891a ldrh r2, [r3, #8]
8014926: 7dfb ldrb r3, [r7, #23]
8014928: b29b uxth r3, r3
801492a: 1ad3 subs r3, r2, r3
801492c: b29a uxth r2, r3
801492e: 693b ldr r3, [r7, #16]
8014930: 811a strh r2, [r3, #8]
LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
(optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
#endif /* TCP_CHECKSUM_ON_COPY */
/* build TCP header */
if (pbuf_add_header(p, TCP_HLEN)) {
8014932: 2114 movs r1, #20
8014934: 68b8 ldr r0, [r7, #8]
8014936: f7fb fdc1 bl 80104bc <pbuf_add_header>
801493a: 4603 mov r3, r0
801493c: 2b00 cmp r3, #0
801493e: d004 beq.n 801494a <tcp_create_segment+0xae>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
TCP_STATS_INC(tcp.err);
tcp_seg_free(seg);
8014940: 6938 ldr r0, [r7, #16]
8014942: f7fd f8d5 bl 8011af0 <tcp_seg_free>
return NULL;
8014946: 2300 movs r3, #0
8014948: e037 b.n 80149ba <tcp_create_segment+0x11e>
}
seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
801494a: 693b ldr r3, [r7, #16]
801494c: 685b ldr r3, [r3, #4]
801494e: 685a ldr r2, [r3, #4]
8014950: 693b ldr r3, [r7, #16]
8014952: 60da str r2, [r3, #12]
seg->tcphdr->src = lwip_htons(pcb->local_port);
8014954: 68fb ldr r3, [r7, #12]
8014956: 8ada ldrh r2, [r3, #22]
8014958: 693b ldr r3, [r7, #16]
801495a: 68dc ldr r4, [r3, #12]
801495c: 4610 mov r0, r2
801495e: f7fa fa8f bl 800ee80 <lwip_htons>
8014962: 4603 mov r3, r0
8014964: 8023 strh r3, [r4, #0]
seg->tcphdr->dest = lwip_htons(pcb->remote_port);
8014966: 68fb ldr r3, [r7, #12]
8014968: 8b1a ldrh r2, [r3, #24]
801496a: 693b ldr r3, [r7, #16]
801496c: 68dc ldr r4, [r3, #12]
801496e: 4610 mov r0, r2
8014970: f7fa fa86 bl 800ee80 <lwip_htons>
8014974: 4603 mov r3, r0
8014976: 8063 strh r3, [r4, #2]
seg->tcphdr->seqno = lwip_htonl(seqno);
8014978: 693b ldr r3, [r7, #16]
801497a: 68dc ldr r4, [r3, #12]
801497c: 6838 ldr r0, [r7, #0]
801497e: f7fa fa94 bl 800eeaa <lwip_htonl>
8014982: 4603 mov r3, r0
8014984: 6063 str r3, [r4, #4]
/* ackno is set in tcp_output */
TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
8014986: 7dfb ldrb r3, [r7, #23]
8014988: 089b lsrs r3, r3, #2
801498a: b2db uxtb r3, r3
801498c: b29b uxth r3, r3
801498e: 3305 adds r3, #5
8014990: b29b uxth r3, r3
8014992: 031b lsls r3, r3, #12
8014994: b29a uxth r2, r3
8014996: 79fb ldrb r3, [r7, #7]
8014998: b29b uxth r3, r3
801499a: 4313 orrs r3, r2
801499c: b29a uxth r2, r3
801499e: 693b ldr r3, [r7, #16]
80149a0: 68dc ldr r4, [r3, #12]
80149a2: 4610 mov r0, r2
80149a4: f7fa fa6c bl 800ee80 <lwip_htons>
80149a8: 4603 mov r3, r0
80149aa: 81a3 strh r3, [r4, #12]
/* wnd and chksum are set in tcp_output */
seg->tcphdr->urgp = 0;
80149ac: 693b ldr r3, [r7, #16]
80149ae: 68db ldr r3, [r3, #12]
80149b0: 2200 movs r2, #0
80149b2: 749a strb r2, [r3, #18]
80149b4: 2200 movs r2, #0
80149b6: 74da strb r2, [r3, #19]
return seg;
80149b8: 693b ldr r3, [r7, #16]
}
80149ba: 4618 mov r0, r3
80149bc: 371c adds r7, #28
80149be: 46bd mov sp, r7
80149c0: bd90 pop {r4, r7, pc}
80149c2: bf00 nop
80149c4: 0801d730 .word 0x0801d730
80149c8: 0801d764 .word 0x0801d764
80149cc: 0801d784 .word 0x0801d784
80149d0: 0801d7ac .word 0x0801d7ac
80149d4: 0801d7d0 .word 0x0801d7d0
080149d8 <tcp_split_unsent_seg>:
* @param pcb the tcp_pcb for which to split the unsent head
* @param split the amount of payload to remain in the head
*/
err_t
tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
{
80149d8: b590 push {r4, r7, lr}
80149da: b08b sub sp, #44 ; 0x2c
80149dc: af02 add r7, sp, #8
80149de: 6078 str r0, [r7, #4]
80149e0: 460b mov r3, r1
80149e2: 807b strh r3, [r7, #2]
struct tcp_seg *seg = NULL, *useg = NULL;
80149e4: 2300 movs r3, #0
80149e6: 61fb str r3, [r7, #28]
80149e8: 2300 movs r3, #0
80149ea: 617b str r3, [r7, #20]
struct pbuf *p = NULL;
80149ec: 2300 movs r3, #0
80149ee: 613b str r3, [r7, #16]
u16_t chksum = 0;
u8_t chksum_swapped = 0;
struct pbuf *q;
#endif /* TCP_CHECKSUM_ON_COPY */
LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
80149f0: 687b ldr r3, [r7, #4]
80149f2: 2b00 cmp r3, #0
80149f4: d106 bne.n 8014a04 <tcp_split_unsent_seg+0x2c>
80149f6: 4b95 ldr r3, [pc, #596] ; (8014c4c <tcp_split_unsent_seg+0x274>)
80149f8: f240 324b movw r2, #843 ; 0x34b
80149fc: 4994 ldr r1, [pc, #592] ; (8014c50 <tcp_split_unsent_seg+0x278>)
80149fe: 4895 ldr r0, [pc, #596] ; (8014c54 <tcp_split_unsent_seg+0x27c>)
8014a00: f006 fb08 bl 801b014 <iprintf>
useg = pcb->unsent;
8014a04: 687b ldr r3, [r7, #4]
8014a06: 6edb ldr r3, [r3, #108] ; 0x6c
8014a08: 617b str r3, [r7, #20]
if (useg == NULL) {
8014a0a: 697b ldr r3, [r7, #20]
8014a0c: 2b00 cmp r3, #0
8014a0e: d102 bne.n 8014a16 <tcp_split_unsent_seg+0x3e>
return ERR_MEM;
8014a10: f04f 33ff mov.w r3, #4294967295
8014a14: e116 b.n 8014c44 <tcp_split_unsent_seg+0x26c>
}
if (split == 0) {
8014a16: 887b ldrh r3, [r7, #2]
8014a18: 2b00 cmp r3, #0
8014a1a: d109 bne.n 8014a30 <tcp_split_unsent_seg+0x58>
LWIP_ASSERT("Can't split segment into length 0", 0);
8014a1c: 4b8b ldr r3, [pc, #556] ; (8014c4c <tcp_split_unsent_seg+0x274>)
8014a1e: f240 3253 movw r2, #851 ; 0x353
8014a22: 498d ldr r1, [pc, #564] ; (8014c58 <tcp_split_unsent_seg+0x280>)
8014a24: 488b ldr r0, [pc, #556] ; (8014c54 <tcp_split_unsent_seg+0x27c>)
8014a26: f006 faf5 bl 801b014 <iprintf>
return ERR_VAL;
8014a2a: f06f 0305 mvn.w r3, #5
8014a2e: e109 b.n 8014c44 <tcp_split_unsent_seg+0x26c>
}
if (useg->len <= split) {
8014a30: 697b ldr r3, [r7, #20]
8014a32: 891b ldrh r3, [r3, #8]
8014a34: 887a ldrh r2, [r7, #2]
8014a36: 429a cmp r2, r3
8014a38: d301 bcc.n 8014a3e <tcp_split_unsent_seg+0x66>
return ERR_OK;
8014a3a: 2300 movs r3, #0
8014a3c: e102 b.n 8014c44 <tcp_split_unsent_seg+0x26c>
}
LWIP_ASSERT("split <= mss", split <= pcb->mss);
8014a3e: 687b ldr r3, [r7, #4]
8014a40: 8e5b ldrh r3, [r3, #50] ; 0x32
8014a42: 887a ldrh r2, [r7, #2]
8014a44: 429a cmp r2, r3
8014a46: d906 bls.n 8014a56 <tcp_split_unsent_seg+0x7e>
8014a48: 4b80 ldr r3, [pc, #512] ; (8014c4c <tcp_split_unsent_seg+0x274>)
8014a4a: f240 325b movw r2, #859 ; 0x35b
8014a4e: 4983 ldr r1, [pc, #524] ; (8014c5c <tcp_split_unsent_seg+0x284>)
8014a50: 4880 ldr r0, [pc, #512] ; (8014c54 <tcp_split_unsent_seg+0x27c>)
8014a52: f006 fadf bl 801b014 <iprintf>
LWIP_ASSERT("useg->len > 0", useg->len > 0);
8014a56: 697b ldr r3, [r7, #20]
8014a58: 891b ldrh r3, [r3, #8]
8014a5a: 2b00 cmp r3, #0
8014a5c: d106 bne.n 8014a6c <tcp_split_unsent_seg+0x94>
8014a5e: 4b7b ldr r3, [pc, #492] ; (8014c4c <tcp_split_unsent_seg+0x274>)
8014a60: f44f 7257 mov.w r2, #860 ; 0x35c
8014a64: 497e ldr r1, [pc, #504] ; (8014c60 <tcp_split_unsent_seg+0x288>)
8014a66: 487b ldr r0, [pc, #492] ; (8014c54 <tcp_split_unsent_seg+0x27c>)
8014a68: f006 fad4 bl 801b014 <iprintf>
* to split this packet so we may actually exceed the max value by
* one!
*/
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
optflags = useg->flags;
8014a6c: 697b ldr r3, [r7, #20]
8014a6e: 7a9b ldrb r3, [r3, #10]
8014a70: 73fb strb r3, [r7, #15]
#if TCP_CHECKSUM_ON_COPY
/* Remove since checksum is not stored until after tcp_create_segment() */
optflags &= ~TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
optlen = LWIP_TCP_OPT_LENGTH(optflags);
8014a72: 7bfb ldrb r3, [r7, #15]
8014a74: 009b lsls r3, r3, #2
8014a76: b2db uxtb r3, r3
8014a78: f003 0304 and.w r3, r3, #4
8014a7c: 73bb strb r3, [r7, #14]
remainder = useg->len - split;
8014a7e: 697b ldr r3, [r7, #20]
8014a80: 891a ldrh r2, [r3, #8]
8014a82: 887b ldrh r3, [r7, #2]
8014a84: 1ad3 subs r3, r2, r3
8014a86: 81bb strh r3, [r7, #12]
/* Create new pbuf for the remainder of the split */
p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
8014a88: 7bbb ldrb r3, [r7, #14]
8014a8a: b29a uxth r2, r3
8014a8c: 89bb ldrh r3, [r7, #12]
8014a8e: 4413 add r3, r2
8014a90: b29b uxth r3, r3
8014a92: f44f 7220 mov.w r2, #640 ; 0x280
8014a96: 4619 mov r1, r3
8014a98: 2036 movs r0, #54 ; 0x36
8014a9a: f7fb fac5 bl 8010028 <pbuf_alloc>
8014a9e: 6138 str r0, [r7, #16]
if (p == NULL) {
8014aa0: 693b ldr r3, [r7, #16]
8014aa2: 2b00 cmp r3, #0
8014aa4: f000 80b7 beq.w 8014c16 <tcp_split_unsent_seg+0x23e>
("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
goto memerr;
}
/* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
offset = useg->p->tot_len - useg->len + split;
8014aa8: 697b ldr r3, [r7, #20]
8014aaa: 685b ldr r3, [r3, #4]
8014aac: 891a ldrh r2, [r3, #8]
8014aae: 697b ldr r3, [r7, #20]
8014ab0: 891b ldrh r3, [r3, #8]
8014ab2: 1ad3 subs r3, r2, r3
8014ab4: b29a uxth r2, r3
8014ab6: 887b ldrh r3, [r7, #2]
8014ab8: 4413 add r3, r2
8014aba: 817b strh r3, [r7, #10]
/* Copy remainder into new pbuf, headers and options will not be filled out */
if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
8014abc: 697b ldr r3, [r7, #20]
8014abe: 6858 ldr r0, [r3, #4]
8014ac0: 693b ldr r3, [r7, #16]
8014ac2: 685a ldr r2, [r3, #4]
8014ac4: 7bbb ldrb r3, [r7, #14]
8014ac6: 18d1 adds r1, r2, r3
8014ac8: 897b ldrh r3, [r7, #10]
8014aca: 89ba ldrh r2, [r7, #12]
8014acc: f7fb ff92 bl 80109f4 <pbuf_copy_partial>
8014ad0: 4603 mov r3, r0
8014ad2: 461a mov r2, r3
8014ad4: 89bb ldrh r3, [r7, #12]
8014ad6: 4293 cmp r3, r2
8014ad8: f040 809f bne.w 8014c1a <tcp_split_unsent_seg+0x242>
#endif /* TCP_CHECKSUM_ON_COPY */
/* Options are created when calling tcp_output() */
/* Migrate flags from original segment */
split_flags = TCPH_FLAGS(useg->tcphdr);
8014adc: 697b ldr r3, [r7, #20]
8014ade: 68db ldr r3, [r3, #12]
8014ae0: 899b ldrh r3, [r3, #12]
8014ae2: b29b uxth r3, r3
8014ae4: 4618 mov r0, r3
8014ae6: f7fa f9cb bl 800ee80 <lwip_htons>
8014aea: 4603 mov r3, r0
8014aec: b2db uxtb r3, r3
8014aee: f003 033f and.w r3, r3, #63 ; 0x3f
8014af2: 76fb strb r3, [r7, #27]
remainder_flags = 0; /* ACK added in tcp_output() */
8014af4: 2300 movs r3, #0
8014af6: 76bb strb r3, [r7, #26]
if (split_flags & TCP_PSH) {
8014af8: 7efb ldrb r3, [r7, #27]
8014afa: f003 0308 and.w r3, r3, #8
8014afe: 2b00 cmp r3, #0
8014b00: d007 beq.n 8014b12 <tcp_split_unsent_seg+0x13a>
split_flags &= ~TCP_PSH;
8014b02: 7efb ldrb r3, [r7, #27]
8014b04: f023 0308 bic.w r3, r3, #8
8014b08: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_PSH;
8014b0a: 7ebb ldrb r3, [r7, #26]
8014b0c: f043 0308 orr.w r3, r3, #8
8014b10: 76bb strb r3, [r7, #26]
}
if (split_flags & TCP_FIN) {
8014b12: 7efb ldrb r3, [r7, #27]
8014b14: f003 0301 and.w r3, r3, #1
8014b18: 2b00 cmp r3, #0
8014b1a: d007 beq.n 8014b2c <tcp_split_unsent_seg+0x154>
split_flags &= ~TCP_FIN;
8014b1c: 7efb ldrb r3, [r7, #27]
8014b1e: f023 0301 bic.w r3, r3, #1
8014b22: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_FIN;
8014b24: 7ebb ldrb r3, [r7, #26]
8014b26: f043 0301 orr.w r3, r3, #1
8014b2a: 76bb strb r3, [r7, #26]
}
/* SYN should be left on split, RST should not be present with data */
seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
8014b2c: 697b ldr r3, [r7, #20]
8014b2e: 68db ldr r3, [r3, #12]
8014b30: 685b ldr r3, [r3, #4]
8014b32: 4618 mov r0, r3
8014b34: f7fa f9b9 bl 800eeaa <lwip_htonl>
8014b38: 4602 mov r2, r0
8014b3a: 887b ldrh r3, [r7, #2]
8014b3c: 18d1 adds r1, r2, r3
8014b3e: 7eba ldrb r2, [r7, #26]
8014b40: 7bfb ldrb r3, [r7, #15]
8014b42: 9300 str r3, [sp, #0]
8014b44: 460b mov r3, r1
8014b46: 6939 ldr r1, [r7, #16]
8014b48: 6878 ldr r0, [r7, #4]
8014b4a: f7ff fea7 bl 801489c <tcp_create_segment>
8014b4e: 61f8 str r0, [r7, #28]
if (seg == NULL) {
8014b50: 69fb ldr r3, [r7, #28]
8014b52: 2b00 cmp r3, #0
8014b54: d063 beq.n 8014c1e <tcp_split_unsent_seg+0x246>
seg->chksum_swapped = chksum_swapped;
seg->flags |= TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
/* Remove this segment from the queue since trimming it may free pbufs */
pcb->snd_queuelen -= pbuf_clen(useg->p);
8014b56: 697b ldr r3, [r7, #20]
8014b58: 685b ldr r3, [r3, #4]
8014b5a: 4618 mov r0, r3
8014b5c: f7fb fdd2 bl 8010704 <pbuf_clen>
8014b60: 4603 mov r3, r0
8014b62: 461a mov r2, r3
8014b64: 687b ldr r3, [r7, #4]
8014b66: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014b6a: 1a9b subs r3, r3, r2
8014b6c: b29a uxth r2, r3
8014b6e: 687b ldr r3, [r7, #4]
8014b70: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Trim the original pbuf into our split size. At this point our remainder segment must be setup
successfully because we are modifying the original segment */
pbuf_realloc(useg->p, useg->p->tot_len - remainder);
8014b74: 697b ldr r3, [r7, #20]
8014b76: 6858 ldr r0, [r3, #4]
8014b78: 697b ldr r3, [r7, #20]
8014b7a: 685b ldr r3, [r3, #4]
8014b7c: 891a ldrh r2, [r3, #8]
8014b7e: 89bb ldrh r3, [r7, #12]
8014b80: 1ad3 subs r3, r2, r3
8014b82: b29b uxth r3, r3
8014b84: 4619 mov r1, r3
8014b86: f7fb fba9 bl 80102dc <pbuf_realloc>
useg->len -= remainder;
8014b8a: 697b ldr r3, [r7, #20]
8014b8c: 891a ldrh r2, [r3, #8]
8014b8e: 89bb ldrh r3, [r7, #12]
8014b90: 1ad3 subs r3, r2, r3
8014b92: b29a uxth r2, r3
8014b94: 697b ldr r3, [r7, #20]
8014b96: 811a strh r2, [r3, #8]
TCPH_SET_FLAG(useg->tcphdr, split_flags);
8014b98: 697b ldr r3, [r7, #20]
8014b9a: 68db ldr r3, [r3, #12]
8014b9c: 899b ldrh r3, [r3, #12]
8014b9e: b29c uxth r4, r3
8014ba0: 7efb ldrb r3, [r7, #27]
8014ba2: b29b uxth r3, r3
8014ba4: 4618 mov r0, r3
8014ba6: f7fa f96b bl 800ee80 <lwip_htons>
8014baa: 4603 mov r3, r0
8014bac: 461a mov r2, r3
8014bae: 697b ldr r3, [r7, #20]
8014bb0: 68db ldr r3, [r3, #12]
8014bb2: 4322 orrs r2, r4
8014bb4: b292 uxth r2, r2
8014bb6: 819a strh r2, [r3, #12]
/* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
useg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
/* Add back to the queue with new trimmed pbuf */
pcb->snd_queuelen += pbuf_clen(useg->p);
8014bb8: 697b ldr r3, [r7, #20]
8014bba: 685b ldr r3, [r3, #4]
8014bbc: 4618 mov r0, r3
8014bbe: f7fb fda1 bl 8010704 <pbuf_clen>
8014bc2: 4603 mov r3, r0
8014bc4: 461a mov r2, r3
8014bc6: 687b ldr r3, [r7, #4]
8014bc8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bcc: 4413 add r3, r2
8014bce: b29a uxth r2, r3
8014bd0: 687b ldr r3, [r7, #4]
8014bd2: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
#endif /* TCP_CHECKSUM_ON_COPY */
/* Update number of segments on the queues. Note that length now may
* exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
* because the total amount of data is constant when packet is split */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014bd6: 69fb ldr r3, [r7, #28]
8014bd8: 685b ldr r3, [r3, #4]
8014bda: 4618 mov r0, r3
8014bdc: f7fb fd92 bl 8010704 <pbuf_clen>
8014be0: 4603 mov r3, r0
8014be2: 461a mov r2, r3
8014be4: 687b ldr r3, [r7, #4]
8014be6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bea: 4413 add r3, r2
8014bec: b29a uxth r2, r3
8014bee: 687b ldr r3, [r7, #4]
8014bf0: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Finally insert remainder into queue after split (which stays head) */
seg->next = useg->next;
8014bf4: 697b ldr r3, [r7, #20]
8014bf6: 681a ldr r2, [r3, #0]
8014bf8: 69fb ldr r3, [r7, #28]
8014bfa: 601a str r2, [r3, #0]
useg->next = seg;
8014bfc: 697b ldr r3, [r7, #20]
8014bfe: 69fa ldr r2, [r7, #28]
8014c00: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
/* If remainder is last segment on the unsent, ensure we clear the oversize amount
* because the remainder is always sized to the exact remaining amount */
if (seg->next == NULL) {
8014c02: 69fb ldr r3, [r7, #28]
8014c04: 681b ldr r3, [r3, #0]
8014c06: 2b00 cmp r3, #0
8014c08: d103 bne.n 8014c12 <tcp_split_unsent_seg+0x23a>
pcb->unsent_oversize = 0;
8014c0a: 687b ldr r3, [r7, #4]
8014c0c: 2200 movs r2, #0
8014c0e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
return ERR_OK;
8014c12: 2300 movs r3, #0
8014c14: e016 b.n 8014c44 <tcp_split_unsent_seg+0x26c>
goto memerr;
8014c16: bf00 nop
8014c18: e002 b.n 8014c20 <tcp_split_unsent_seg+0x248>
goto memerr;
8014c1a: bf00 nop
8014c1c: e000 b.n 8014c20 <tcp_split_unsent_seg+0x248>
goto memerr;
8014c1e: bf00 nop
memerr:
TCP_STATS_INC(tcp.memerr);
LWIP_ASSERT("seg == NULL", seg == NULL);
8014c20: 69fb ldr r3, [r7, #28]
8014c22: 2b00 cmp r3, #0
8014c24: d006 beq.n 8014c34 <tcp_split_unsent_seg+0x25c>
8014c26: 4b09 ldr r3, [pc, #36] ; (8014c4c <tcp_split_unsent_seg+0x274>)
8014c28: f44f 7276 mov.w r2, #984 ; 0x3d8
8014c2c: 490d ldr r1, [pc, #52] ; (8014c64 <tcp_split_unsent_seg+0x28c>)
8014c2e: 4809 ldr r0, [pc, #36] ; (8014c54 <tcp_split_unsent_seg+0x27c>)
8014c30: f006 f9f0 bl 801b014 <iprintf>
if (p != NULL) {
8014c34: 693b ldr r3, [r7, #16]
8014c36: 2b00 cmp r3, #0
8014c38: d002 beq.n 8014c40 <tcp_split_unsent_seg+0x268>
pbuf_free(p);
8014c3a: 6938 ldr r0, [r7, #16]
8014c3c: f7fb fcd4 bl 80105e8 <pbuf_free>
}
return ERR_MEM;
8014c40: f04f 33ff mov.w r3, #4294967295
}
8014c44: 4618 mov r0, r3
8014c46: 3724 adds r7, #36 ; 0x24
8014c48: 46bd mov sp, r7
8014c4a: bd90 pop {r4, r7, pc}
8014c4c: 0801d730 .word 0x0801d730
8014c50: 0801dac4 .word 0x0801dac4
8014c54: 0801d784 .word 0x0801d784
8014c58: 0801dae8 .word 0x0801dae8
8014c5c: 0801db0c .word 0x0801db0c
8014c60: 0801db1c .word 0x0801db1c
8014c64: 0801db2c .word 0x0801db2c
08014c68 <tcp_send_fin>:
* @param pcb the tcp_pcb over which to send a segment
* @return ERR_OK if sent, another err_t otherwise
*/
err_t
tcp_send_fin(struct tcp_pcb *pcb)
{
8014c68: b590 push {r4, r7, lr}
8014c6a: b085 sub sp, #20
8014c6c: af00 add r7, sp, #0
8014c6e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
8014c70: 687b ldr r3, [r7, #4]
8014c72: 2b00 cmp r3, #0
8014c74: d106 bne.n 8014c84 <tcp_send_fin+0x1c>
8014c76: 4b21 ldr r3, [pc, #132] ; (8014cfc <tcp_send_fin+0x94>)
8014c78: f240 32eb movw r2, #1003 ; 0x3eb
8014c7c: 4920 ldr r1, [pc, #128] ; (8014d00 <tcp_send_fin+0x98>)
8014c7e: 4821 ldr r0, [pc, #132] ; (8014d04 <tcp_send_fin+0x9c>)
8014c80: f006 f9c8 bl 801b014 <iprintf>
/* first, try to add the fin to the last unsent segment */
if (pcb->unsent != NULL) {
8014c84: 687b ldr r3, [r7, #4]
8014c86: 6edb ldr r3, [r3, #108] ; 0x6c
8014c88: 2b00 cmp r3, #0
8014c8a: d02e beq.n 8014cea <tcp_send_fin+0x82>
struct tcp_seg *last_unsent;
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014c8c: 687b ldr r3, [r7, #4]
8014c8e: 6edb ldr r3, [r3, #108] ; 0x6c
8014c90: 60fb str r3, [r7, #12]
8014c92: e002 b.n 8014c9a <tcp_send_fin+0x32>
last_unsent = last_unsent->next);
8014c94: 68fb ldr r3, [r7, #12]
8014c96: 681b ldr r3, [r3, #0]
8014c98: 60fb str r3, [r7, #12]
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014c9a: 68fb ldr r3, [r7, #12]
8014c9c: 681b ldr r3, [r3, #0]
8014c9e: 2b00 cmp r3, #0
8014ca0: d1f8 bne.n 8014c94 <tcp_send_fin+0x2c>
if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
8014ca2: 68fb ldr r3, [r7, #12]
8014ca4: 68db ldr r3, [r3, #12]
8014ca6: 899b ldrh r3, [r3, #12]
8014ca8: b29b uxth r3, r3
8014caa: 4618 mov r0, r3
8014cac: f7fa f8e8 bl 800ee80 <lwip_htons>
8014cb0: 4603 mov r3, r0
8014cb2: b2db uxtb r3, r3
8014cb4: f003 0307 and.w r3, r3, #7
8014cb8: 2b00 cmp r3, #0
8014cba: d116 bne.n 8014cea <tcp_send_fin+0x82>
/* no SYN/FIN/RST flag in the header, we can add the FIN flag */
TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
8014cbc: 68fb ldr r3, [r7, #12]
8014cbe: 68db ldr r3, [r3, #12]
8014cc0: 899b ldrh r3, [r3, #12]
8014cc2: b29c uxth r4, r3
8014cc4: 2001 movs r0, #1
8014cc6: f7fa f8db bl 800ee80 <lwip_htons>
8014cca: 4603 mov r3, r0
8014ccc: 461a mov r2, r3
8014cce: 68fb ldr r3, [r7, #12]
8014cd0: 68db ldr r3, [r3, #12]
8014cd2: 4322 orrs r2, r4
8014cd4: b292 uxth r2, r2
8014cd6: 819a strh r2, [r3, #12]
tcp_set_flags(pcb, TF_FIN);
8014cd8: 687b ldr r3, [r7, #4]
8014cda: 8b5b ldrh r3, [r3, #26]
8014cdc: f043 0320 orr.w r3, r3, #32
8014ce0: b29a uxth r2, r3
8014ce2: 687b ldr r3, [r7, #4]
8014ce4: 835a strh r2, [r3, #26]
return ERR_OK;
8014ce6: 2300 movs r3, #0
8014ce8: e004 b.n 8014cf4 <tcp_send_fin+0x8c>
}
}
/* no data, no length, flags, copy=1, no optdata */
return tcp_enqueue_flags(pcb, TCP_FIN);
8014cea: 2101 movs r1, #1
8014cec: 6878 ldr r0, [r7, #4]
8014cee: f000 f80b bl 8014d08 <tcp_enqueue_flags>
8014cf2: 4603 mov r3, r0
}
8014cf4: 4618 mov r0, r3
8014cf6: 3714 adds r7, #20
8014cf8: 46bd mov sp, r7
8014cfa: bd90 pop {r4, r7, pc}
8014cfc: 0801d730 .word 0x0801d730
8014d00: 0801db38 .word 0x0801db38
8014d04: 0801d784 .word 0x0801d784
08014d08 <tcp_enqueue_flags>:
* @param pcb Protocol control block for the TCP connection.
* @param flags TCP header flags to set in the outgoing segment.
*/
err_t
tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
{
8014d08: b580 push {r7, lr}
8014d0a: b08a sub sp, #40 ; 0x28
8014d0c: af02 add r7, sp, #8
8014d0e: 6078 str r0, [r7, #4]
8014d10: 460b mov r3, r1
8014d12: 70fb strb r3, [r7, #3]
struct pbuf *p;
struct tcp_seg *seg;
u8_t optflags = 0;
8014d14: 2300 movs r3, #0
8014d16: 77fb strb r3, [r7, #31]
u8_t optlen = 0;
8014d18: 2300 movs r3, #0
8014d1a: 75fb strb r3, [r7, #23]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
8014d1c: 78fb ldrb r3, [r7, #3]
8014d1e: f003 0303 and.w r3, r3, #3
8014d22: 2b00 cmp r3, #0
8014d24: d106 bne.n 8014d34 <tcp_enqueue_flags+0x2c>
8014d26: 4b67 ldr r3, [pc, #412] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014d28: f240 4212 movw r2, #1042 ; 0x412
8014d2c: 4966 ldr r1, [pc, #408] ; (8014ec8 <tcp_enqueue_flags+0x1c0>)
8014d2e: 4867 ldr r0, [pc, #412] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014d30: f006 f970 bl 801b014 <iprintf>
(flags & (TCP_SYN | TCP_FIN)) != 0);
LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
8014d34: 687b ldr r3, [r7, #4]
8014d36: 2b00 cmp r3, #0
8014d38: d106 bne.n 8014d48 <tcp_enqueue_flags+0x40>
8014d3a: 4b62 ldr r3, [pc, #392] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014d3c: f240 4213 movw r2, #1043 ; 0x413
8014d40: 4963 ldr r1, [pc, #396] ; (8014ed0 <tcp_enqueue_flags+0x1c8>)
8014d42: 4862 ldr r0, [pc, #392] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014d44: f006 f966 bl 801b014 <iprintf>
/* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
/* Get options for this segment. This is a special case since this is the
only place where a SYN can be sent. */
if (flags & TCP_SYN) {
8014d48: 78fb ldrb r3, [r7, #3]
8014d4a: f003 0302 and.w r3, r3, #2
8014d4e: 2b00 cmp r3, #0
8014d50: d001 beq.n 8014d56 <tcp_enqueue_flags+0x4e>
optflags = TF_SEG_OPTS_MSS;
8014d52: 2301 movs r3, #1
8014d54: 77fb strb r3, [r7, #31]
/* Make sure the timestamp option is only included in data segments if we
agreed about it with the remote host (and in active open SYN segments). */
optflags |= TF_SEG_OPTS_TS;
}
#endif /* LWIP_TCP_TIMESTAMPS */
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8014d56: 7ffb ldrb r3, [r7, #31]
8014d58: 009b lsls r3, r3, #2
8014d5a: b2db uxtb r3, r3
8014d5c: f003 0304 and.w r3, r3, #4
8014d60: 75fb strb r3, [r7, #23]
/* Allocate pbuf with room for TCP header + options */
if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
8014d62: 7dfb ldrb r3, [r7, #23]
8014d64: b29b uxth r3, r3
8014d66: f44f 7220 mov.w r2, #640 ; 0x280
8014d6a: 4619 mov r1, r3
8014d6c: 2036 movs r0, #54 ; 0x36
8014d6e: f7fb f95b bl 8010028 <pbuf_alloc>
8014d72: 6138 str r0, [r7, #16]
8014d74: 693b ldr r3, [r7, #16]
8014d76: 2b00 cmp r3, #0
8014d78: d109 bne.n 8014d8e <tcp_enqueue_flags+0x86>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014d7a: 687b ldr r3, [r7, #4]
8014d7c: 8b5b ldrh r3, [r3, #26]
8014d7e: f043 0380 orr.w r3, r3, #128 ; 0x80
8014d82: b29a uxth r2, r3
8014d84: 687b ldr r3, [r7, #4]
8014d86: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014d88: f04f 33ff mov.w r3, #4294967295
8014d8c: e095 b.n 8014eba <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
8014d8e: 693b ldr r3, [r7, #16]
8014d90: 895a ldrh r2, [r3, #10]
8014d92: 7dfb ldrb r3, [r7, #23]
8014d94: b29b uxth r3, r3
8014d96: 429a cmp r2, r3
8014d98: d206 bcs.n 8014da8 <tcp_enqueue_flags+0xa0>
8014d9a: 4b4a ldr r3, [pc, #296] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014d9c: f240 423a movw r2, #1082 ; 0x43a
8014da0: 494c ldr r1, [pc, #304] ; (8014ed4 <tcp_enqueue_flags+0x1cc>)
8014da2: 484a ldr r0, [pc, #296] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014da4: f006 f936 bl 801b014 <iprintf>
(p->len >= optlen));
/* Allocate memory for tcp_seg, and fill in fields. */
if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
8014da8: 687b ldr r3, [r7, #4]
8014daa: 6dd9 ldr r1, [r3, #92] ; 0x5c
8014dac: 78fa ldrb r2, [r7, #3]
8014dae: 7ffb ldrb r3, [r7, #31]
8014db0: 9300 str r3, [sp, #0]
8014db2: 460b mov r3, r1
8014db4: 6939 ldr r1, [r7, #16]
8014db6: 6878 ldr r0, [r7, #4]
8014db8: f7ff fd70 bl 801489c <tcp_create_segment>
8014dbc: 60f8 str r0, [r7, #12]
8014dbe: 68fb ldr r3, [r7, #12]
8014dc0: 2b00 cmp r3, #0
8014dc2: d109 bne.n 8014dd8 <tcp_enqueue_flags+0xd0>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014dc4: 687b ldr r3, [r7, #4]
8014dc6: 8b5b ldrh r3, [r3, #26]
8014dc8: f043 0380 orr.w r3, r3, #128 ; 0x80
8014dcc: b29a uxth r2, r3
8014dce: 687b ldr r3, [r7, #4]
8014dd0: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014dd2: f04f 33ff mov.w r3, #4294967295
8014dd6: e070 b.n 8014eba <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
8014dd8: 68fb ldr r3, [r7, #12]
8014dda: 68db ldr r3, [r3, #12]
8014ddc: f003 0303 and.w r3, r3, #3
8014de0: 2b00 cmp r3, #0
8014de2: d006 beq.n 8014df2 <tcp_enqueue_flags+0xea>
8014de4: 4b37 ldr r3, [pc, #220] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014de6: f240 4242 movw r2, #1090 ; 0x442
8014dea: 493b ldr r1, [pc, #236] ; (8014ed8 <tcp_enqueue_flags+0x1d0>)
8014dec: 4837 ldr r0, [pc, #220] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014dee: f006 f911 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
8014df2: 68fb ldr r3, [r7, #12]
8014df4: 891b ldrh r3, [r3, #8]
8014df6: 2b00 cmp r3, #0
8014df8: d006 beq.n 8014e08 <tcp_enqueue_flags+0x100>
8014dfa: 4b32 ldr r3, [pc, #200] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014dfc: f240 4243 movw r2, #1091 ; 0x443
8014e00: 4936 ldr r1, [pc, #216] ; (8014edc <tcp_enqueue_flags+0x1d4>)
8014e02: 4832 ldr r0, [pc, #200] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014e04: f006 f906 bl 801b014 <iprintf>
lwip_ntohl(seg->tcphdr->seqno),
lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
(u16_t)flags));
/* Now append seg to pcb->unsent queue */
if (pcb->unsent == NULL) {
8014e08: 687b ldr r3, [r7, #4]
8014e0a: 6edb ldr r3, [r3, #108] ; 0x6c
8014e0c: 2b00 cmp r3, #0
8014e0e: d103 bne.n 8014e18 <tcp_enqueue_flags+0x110>
pcb->unsent = seg;
8014e10: 687b ldr r3, [r7, #4]
8014e12: 68fa ldr r2, [r7, #12]
8014e14: 66da str r2, [r3, #108] ; 0x6c
8014e16: e00d b.n 8014e34 <tcp_enqueue_flags+0x12c>
} else {
struct tcp_seg *useg;
for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
8014e18: 687b ldr r3, [r7, #4]
8014e1a: 6edb ldr r3, [r3, #108] ; 0x6c
8014e1c: 61bb str r3, [r7, #24]
8014e1e: e002 b.n 8014e26 <tcp_enqueue_flags+0x11e>
8014e20: 69bb ldr r3, [r7, #24]
8014e22: 681b ldr r3, [r3, #0]
8014e24: 61bb str r3, [r7, #24]
8014e26: 69bb ldr r3, [r7, #24]
8014e28: 681b ldr r3, [r3, #0]
8014e2a: 2b00 cmp r3, #0
8014e2c: d1f8 bne.n 8014e20 <tcp_enqueue_flags+0x118>
useg->next = seg;
8014e2e: 69bb ldr r3, [r7, #24]
8014e30: 68fa ldr r2, [r7, #12]
8014e32: 601a str r2, [r3, #0]
}
#if TCP_OVERSIZE
/* The new unsent tail has no space */
pcb->unsent_oversize = 0;
8014e34: 687b ldr r3, [r7, #4]
8014e36: 2200 movs r2, #0
8014e38: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
/* SYN and FIN bump the sequence number */
if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
8014e3c: 78fb ldrb r3, [r7, #3]
8014e3e: f003 0302 and.w r3, r3, #2
8014e42: 2b00 cmp r3, #0
8014e44: d104 bne.n 8014e50 <tcp_enqueue_flags+0x148>
8014e46: 78fb ldrb r3, [r7, #3]
8014e48: f003 0301 and.w r3, r3, #1
8014e4c: 2b00 cmp r3, #0
8014e4e: d004 beq.n 8014e5a <tcp_enqueue_flags+0x152>
pcb->snd_lbb++;
8014e50: 687b ldr r3, [r7, #4]
8014e52: 6ddb ldr r3, [r3, #92] ; 0x5c
8014e54: 1c5a adds r2, r3, #1
8014e56: 687b ldr r3, [r7, #4]
8014e58: 65da str r2, [r3, #92] ; 0x5c
/* optlen does not influence snd_buf */
}
if (flags & TCP_FIN) {
8014e5a: 78fb ldrb r3, [r7, #3]
8014e5c: f003 0301 and.w r3, r3, #1
8014e60: 2b00 cmp r3, #0
8014e62: d006 beq.n 8014e72 <tcp_enqueue_flags+0x16a>
tcp_set_flags(pcb, TF_FIN);
8014e64: 687b ldr r3, [r7, #4]
8014e66: 8b5b ldrh r3, [r3, #26]
8014e68: f043 0320 orr.w r3, r3, #32
8014e6c: b29a uxth r2, r3
8014e6e: 687b ldr r3, [r7, #4]
8014e70: 835a strh r2, [r3, #26]
}
/* update number of segments on the queues */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014e72: 68fb ldr r3, [r7, #12]
8014e74: 685b ldr r3, [r3, #4]
8014e76: 4618 mov r0, r3
8014e78: f7fb fc44 bl 8010704 <pbuf_clen>
8014e7c: 4603 mov r3, r0
8014e7e: 461a mov r2, r3
8014e80: 687b ldr r3, [r7, #4]
8014e82: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014e86: 4413 add r3, r2
8014e88: b29a uxth r2, r3
8014e8a: 687b ldr r3, [r7, #4]
8014e8c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
if (pcb->snd_queuelen != 0) {
8014e90: 687b ldr r3, [r7, #4]
8014e92: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014e96: 2b00 cmp r3, #0
8014e98: d00e beq.n 8014eb8 <tcp_enqueue_flags+0x1b0>
LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
8014e9a: 687b ldr r3, [r7, #4]
8014e9c: 6f1b ldr r3, [r3, #112] ; 0x70
8014e9e: 2b00 cmp r3, #0
8014ea0: d10a bne.n 8014eb8 <tcp_enqueue_flags+0x1b0>
8014ea2: 687b ldr r3, [r7, #4]
8014ea4: 6edb ldr r3, [r3, #108] ; 0x6c
8014ea6: 2b00 cmp r3, #0
8014ea8: d106 bne.n 8014eb8 <tcp_enqueue_flags+0x1b0>
8014eaa: 4b06 ldr r3, [pc, #24] ; (8014ec4 <tcp_enqueue_flags+0x1bc>)
8014eac: f240 4266 movw r2, #1126 ; 0x466
8014eb0: 490b ldr r1, [pc, #44] ; (8014ee0 <tcp_enqueue_flags+0x1d8>)
8014eb2: 4806 ldr r0, [pc, #24] ; (8014ecc <tcp_enqueue_flags+0x1c4>)
8014eb4: f006 f8ae bl 801b014 <iprintf>
pcb->unacked != NULL || pcb->unsent != NULL);
}
return ERR_OK;
8014eb8: 2300 movs r3, #0
}
8014eba: 4618 mov r0, r3
8014ebc: 3720 adds r7, #32
8014ebe: 46bd mov sp, r7
8014ec0: bd80 pop {r7, pc}
8014ec2: bf00 nop
8014ec4: 0801d730 .word 0x0801d730
8014ec8: 0801db54 .word 0x0801db54
8014ecc: 0801d784 .word 0x0801d784
8014ed0: 0801dbac .word 0x0801dbac
8014ed4: 0801dbcc .word 0x0801dbcc
8014ed8: 0801dc08 .word 0x0801dc08
8014edc: 0801dc20 .word 0x0801dc20
8014ee0: 0801dc4c .word 0x0801dc4c
08014ee4 <tcp_output>:
* @return ERR_OK if data has been sent or nothing to send
* another err_t on error
*/
err_t
tcp_output(struct tcp_pcb *pcb)
{
8014ee4: b5b0 push {r4, r5, r7, lr}
8014ee6: b08a sub sp, #40 ; 0x28
8014ee8: af00 add r7, sp, #0
8014eea: 6078 str r0, [r7, #4]
s16_t i = 0;
#endif /* TCP_CWND_DEBUG */
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
8014eec: 687b ldr r3, [r7, #4]
8014eee: 2b00 cmp r3, #0
8014ef0: d106 bne.n 8014f00 <tcp_output+0x1c>
8014ef2: 4ba0 ldr r3, [pc, #640] ; (8015174 <tcp_output+0x290>)
8014ef4: f240 42e1 movw r2, #1249 ; 0x4e1
8014ef8: 499f ldr r1, [pc, #636] ; (8015178 <tcp_output+0x294>)
8014efa: 48a0 ldr r0, [pc, #640] ; (801517c <tcp_output+0x298>)
8014efc: f006 f88a bl 801b014 <iprintf>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_output for listen-pcbs",
8014f00: 687b ldr r3, [r7, #4]
8014f02: 7d1b ldrb r3, [r3, #20]
8014f04: 2b01 cmp r3, #1
8014f06: d106 bne.n 8014f16 <tcp_output+0x32>
8014f08: 4b9a ldr r3, [pc, #616] ; (8015174 <tcp_output+0x290>)
8014f0a: f240 42e4 movw r2, #1252 ; 0x4e4
8014f0e: 499c ldr r1, [pc, #624] ; (8015180 <tcp_output+0x29c>)
8014f10: 489a ldr r0, [pc, #616] ; (801517c <tcp_output+0x298>)
8014f12: f006 f87f bl 801b014 <iprintf>
/* First, check if we are invoked by the TCP input processing
code. If so, we do not output anything. Instead, we rely on the
input processing code to call us when input processing is done
with. */
if (tcp_input_pcb == pcb) {
8014f16: 4b9b ldr r3, [pc, #620] ; (8015184 <tcp_output+0x2a0>)
8014f18: 681b ldr r3, [r3, #0]
8014f1a: 687a ldr r2, [r7, #4]
8014f1c: 429a cmp r2, r3
8014f1e: d101 bne.n 8014f24 <tcp_output+0x40>
return ERR_OK;
8014f20: 2300 movs r3, #0
8014f22: e1d2 b.n 80152ca <tcp_output+0x3e6>
}
wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
8014f24: 687b ldr r3, [r7, #4]
8014f26: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8014f2a: 687b ldr r3, [r7, #4]
8014f2c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8014f30: 429a cmp r2, r3
8014f32: d203 bcs.n 8014f3c <tcp_output+0x58>
8014f34: 687b ldr r3, [r7, #4]
8014f36: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014f3a: e002 b.n 8014f42 <tcp_output+0x5e>
8014f3c: 687b ldr r3, [r7, #4]
8014f3e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8014f42: 61bb str r3, [r7, #24]
seg = pcb->unsent;
8014f44: 687b ldr r3, [r7, #4]
8014f46: 6edb ldr r3, [r3, #108] ; 0x6c
8014f48: 627b str r3, [r7, #36] ; 0x24
if (seg == NULL) {
8014f4a: 6a7b ldr r3, [r7, #36] ; 0x24
8014f4c: 2b00 cmp r3, #0
8014f4e: d10b bne.n 8014f68 <tcp_output+0x84>
", seg == NULL, ack %"U32_F"\n",
pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
/* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
* an empty ACK segment and send it. */
if (pcb->flags & TF_ACK_NOW) {
8014f50: 687b ldr r3, [r7, #4]
8014f52: 8b5b ldrh r3, [r3, #26]
8014f54: f003 0302 and.w r3, r3, #2
8014f58: 2b00 cmp r3, #0
8014f5a: f000 81a9 beq.w 80152b0 <tcp_output+0x3cc>
return tcp_send_empty_ack(pcb);
8014f5e: 6878 ldr r0, [r7, #4]
8014f60: f000 fdd8 bl 8015b14 <tcp_send_empty_ack>
8014f64: 4603 mov r3, r0
8014f66: e1b0 b.n 80152ca <tcp_output+0x3e6>
pcb->snd_wnd, pcb->cwnd, wnd,
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
}
netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
8014f68: 6879 ldr r1, [r7, #4]
8014f6a: 687b ldr r3, [r7, #4]
8014f6c: 3304 adds r3, #4
8014f6e: 461a mov r2, r3
8014f70: 6878 ldr r0, [r7, #4]
8014f72: f7ff fc77 bl 8014864 <tcp_route>
8014f76: 6178 str r0, [r7, #20]
if (netif == NULL) {
8014f78: 697b ldr r3, [r7, #20]
8014f7a: 2b00 cmp r3, #0
8014f7c: d102 bne.n 8014f84 <tcp_output+0xa0>
return ERR_RTE;
8014f7e: f06f 0303 mvn.w r3, #3
8014f82: e1a2 b.n 80152ca <tcp_output+0x3e6>
}
/* If we don't have a local IP address, we get one from netif */
if (ip_addr_isany(&pcb->local_ip)) {
8014f84: 687b ldr r3, [r7, #4]
8014f86: 2b00 cmp r3, #0
8014f88: d003 beq.n 8014f92 <tcp_output+0xae>
8014f8a: 687b ldr r3, [r7, #4]
8014f8c: 681b ldr r3, [r3, #0]
8014f8e: 2b00 cmp r3, #0
8014f90: d111 bne.n 8014fb6 <tcp_output+0xd2>
const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
8014f92: 697b ldr r3, [r7, #20]
8014f94: 2b00 cmp r3, #0
8014f96: d002 beq.n 8014f9e <tcp_output+0xba>
8014f98: 697b ldr r3, [r7, #20]
8014f9a: 3304 adds r3, #4
8014f9c: e000 b.n 8014fa0 <tcp_output+0xbc>
8014f9e: 2300 movs r3, #0
8014fa0: 613b str r3, [r7, #16]
if (local_ip == NULL) {
8014fa2: 693b ldr r3, [r7, #16]
8014fa4: 2b00 cmp r3, #0
8014fa6: d102 bne.n 8014fae <tcp_output+0xca>
return ERR_RTE;
8014fa8: f06f 0303 mvn.w r3, #3
8014fac: e18d b.n 80152ca <tcp_output+0x3e6>
}
ip_addr_copy(pcb->local_ip, *local_ip);
8014fae: 693b ldr r3, [r7, #16]
8014fb0: 681a ldr r2, [r3, #0]
8014fb2: 687b ldr r3, [r7, #4]
8014fb4: 601a str r2, [r3, #0]
}
/* Handle the current segment not fitting within the window */
if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
8014fb6: 6a7b ldr r3, [r7, #36] ; 0x24
8014fb8: 68db ldr r3, [r3, #12]
8014fba: 685b ldr r3, [r3, #4]
8014fbc: 4618 mov r0, r3
8014fbe: f7f9 ff74 bl 800eeaa <lwip_htonl>
8014fc2: 4602 mov r2, r0
8014fc4: 687b ldr r3, [r7, #4]
8014fc6: 6c5b ldr r3, [r3, #68] ; 0x44
8014fc8: 1ad3 subs r3, r2, r3
8014fca: 6a7a ldr r2, [r7, #36] ; 0x24
8014fcc: 8912 ldrh r2, [r2, #8]
8014fce: 4413 add r3, r2
8014fd0: 69ba ldr r2, [r7, #24]
8014fd2: 429a cmp r2, r3
8014fd4: d227 bcs.n 8015026 <tcp_output+0x142>
* within the remaining (could be 0) send window and RTO timer is not running (we
* have no in-flight data). If window is still too small after persist timer fires,
* then we split the segment. We don't consider the congestion window since a cwnd
* smaller than 1 SMSS implies in-flight data
*/
if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
8014fd6: 687b ldr r3, [r7, #4]
8014fd8: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014fdc: 461a mov r2, r3
8014fde: 69bb ldr r3, [r7, #24]
8014fe0: 4293 cmp r3, r2
8014fe2: d114 bne.n 801500e <tcp_output+0x12a>
8014fe4: 687b ldr r3, [r7, #4]
8014fe6: 6f1b ldr r3, [r3, #112] ; 0x70
8014fe8: 2b00 cmp r3, #0
8014fea: d110 bne.n 801500e <tcp_output+0x12a>
8014fec: 687b ldr r3, [r7, #4]
8014fee: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8014ff2: 2b00 cmp r3, #0
8014ff4: d10b bne.n 801500e <tcp_output+0x12a>
pcb->persist_cnt = 0;
8014ff6: 687b ldr r3, [r7, #4]
8014ff8: 2200 movs r2, #0
8014ffa: f883 2098 strb.w r2, [r3, #152] ; 0x98
pcb->persist_backoff = 1;
8014ffe: 687b ldr r3, [r7, #4]
8015000: 2201 movs r2, #1
8015002: f883 2099 strb.w r2, [r3, #153] ; 0x99
pcb->persist_probe = 0;
8015006: 687b ldr r3, [r7, #4]
8015008: 2200 movs r2, #0
801500a: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
/* We need an ACK, but can't send data now, so send an empty ACK */
if (pcb->flags & TF_ACK_NOW) {
801500e: 687b ldr r3, [r7, #4]
8015010: 8b5b ldrh r3, [r3, #26]
8015012: f003 0302 and.w r3, r3, #2
8015016: 2b00 cmp r3, #0
8015018: f000 814c beq.w 80152b4 <tcp_output+0x3d0>
return tcp_send_empty_ack(pcb);
801501c: 6878 ldr r0, [r7, #4]
801501e: f000 fd79 bl 8015b14 <tcp_send_empty_ack>
8015022: 4603 mov r3, r0
8015024: e151 b.n 80152ca <tcp_output+0x3e6>
}
goto output_done;
}
/* Stop persist timer, above conditions are not active */
pcb->persist_backoff = 0;
8015026: 687b ldr r3, [r7, #4]
8015028: 2200 movs r2, #0
801502a: f883 2099 strb.w r2, [r3, #153] ; 0x99
/* useg should point to last segment on unacked queue */
useg = pcb->unacked;
801502e: 687b ldr r3, [r7, #4]
8015030: 6f1b ldr r3, [r3, #112] ; 0x70
8015032: 623b str r3, [r7, #32]
if (useg != NULL) {
8015034: 6a3b ldr r3, [r7, #32]
8015036: 2b00 cmp r3, #0
8015038: f000 811b beq.w 8015272 <tcp_output+0x38e>
for (; useg->next != NULL; useg = useg->next);
801503c: e002 b.n 8015044 <tcp_output+0x160>
801503e: 6a3b ldr r3, [r7, #32]
8015040: 681b ldr r3, [r3, #0]
8015042: 623b str r3, [r7, #32]
8015044: 6a3b ldr r3, [r7, #32]
8015046: 681b ldr r3, [r3, #0]
8015048: 2b00 cmp r3, #0
801504a: d1f8 bne.n 801503e <tcp_output+0x15a>
}
/* data available and window allows it to be sent? */
while (seg != NULL &&
801504c: e111 b.n 8015272 <tcp_output+0x38e>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
LWIP_ASSERT("RST not expected here!",
801504e: 6a7b ldr r3, [r7, #36] ; 0x24
8015050: 68db ldr r3, [r3, #12]
8015052: 899b ldrh r3, [r3, #12]
8015054: b29b uxth r3, r3
8015056: 4618 mov r0, r3
8015058: f7f9 ff12 bl 800ee80 <lwip_htons>
801505c: 4603 mov r3, r0
801505e: b2db uxtb r3, r3
8015060: f003 0304 and.w r3, r3, #4
8015064: 2b00 cmp r3, #0
8015066: d006 beq.n 8015076 <tcp_output+0x192>
8015068: 4b42 ldr r3, [pc, #264] ; (8015174 <tcp_output+0x290>)
801506a: f240 5237 movw r2, #1335 ; 0x537
801506e: 4946 ldr r1, [pc, #280] ; (8015188 <tcp_output+0x2a4>)
8015070: 4842 ldr r0, [pc, #264] ; (801517c <tcp_output+0x298>)
8015072: f005 ffcf bl 801b014 <iprintf>
* - if tcp_write had a memory error before (prevent delayed ACK timeout) or
* - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
* either seg->next != NULL or pcb->unacked == NULL;
* RST is no sent using tcp_write/tcp_output.
*/
if ((tcp_do_output_nagle(pcb) == 0) &&
8015076: 687b ldr r3, [r7, #4]
8015078: 6f1b ldr r3, [r3, #112] ; 0x70
801507a: 2b00 cmp r3, #0
801507c: d01f beq.n 80150be <tcp_output+0x1da>
801507e: 687b ldr r3, [r7, #4]
8015080: 8b5b ldrh r3, [r3, #26]
8015082: f003 0344 and.w r3, r3, #68 ; 0x44
8015086: 2b00 cmp r3, #0
8015088: d119 bne.n 80150be <tcp_output+0x1da>
801508a: 687b ldr r3, [r7, #4]
801508c: 6edb ldr r3, [r3, #108] ; 0x6c
801508e: 2b00 cmp r3, #0
8015090: d00b beq.n 80150aa <tcp_output+0x1c6>
8015092: 687b ldr r3, [r7, #4]
8015094: 6edb ldr r3, [r3, #108] ; 0x6c
8015096: 681b ldr r3, [r3, #0]
8015098: 2b00 cmp r3, #0
801509a: d110 bne.n 80150be <tcp_output+0x1da>
801509c: 687b ldr r3, [r7, #4]
801509e: 6edb ldr r3, [r3, #108] ; 0x6c
80150a0: 891a ldrh r2, [r3, #8]
80150a2: 687b ldr r3, [r7, #4]
80150a4: 8e5b ldrh r3, [r3, #50] ; 0x32
80150a6: 429a cmp r2, r3
80150a8: d209 bcs.n 80150be <tcp_output+0x1da>
80150aa: 687b ldr r3, [r7, #4]
80150ac: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64
80150b0: 2b00 cmp r3, #0
80150b2: d004 beq.n 80150be <tcp_output+0x1da>
80150b4: 687b ldr r3, [r7, #4]
80150b6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
80150ba: 2b08 cmp r3, #8
80150bc: d901 bls.n 80150c2 <tcp_output+0x1de>
80150be: 2301 movs r3, #1
80150c0: e000 b.n 80150c4 <tcp_output+0x1e0>
80150c2: 2300 movs r3, #0
80150c4: 2b00 cmp r3, #0
80150c6: d106 bne.n 80150d6 <tcp_output+0x1f2>
((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
80150c8: 687b ldr r3, [r7, #4]
80150ca: 8b5b ldrh r3, [r3, #26]
80150cc: f003 03a0 and.w r3, r3, #160 ; 0xa0
if ((tcp_do_output_nagle(pcb) == 0) &&
80150d0: 2b00 cmp r3, #0
80150d2: f000 80e3 beq.w 801529c <tcp_output+0x3b8>
pcb->lastack,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
++i;
#endif /* TCP_CWND_DEBUG */
if (pcb->state != SYN_SENT) {
80150d6: 687b ldr r3, [r7, #4]
80150d8: 7d1b ldrb r3, [r3, #20]
80150da: 2b02 cmp r3, #2
80150dc: d00d beq.n 80150fa <tcp_output+0x216>
TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
80150de: 6a7b ldr r3, [r7, #36] ; 0x24
80150e0: 68db ldr r3, [r3, #12]
80150e2: 899b ldrh r3, [r3, #12]
80150e4: b29c uxth r4, r3
80150e6: 2010 movs r0, #16
80150e8: f7f9 feca bl 800ee80 <lwip_htons>
80150ec: 4603 mov r3, r0
80150ee: 461a mov r2, r3
80150f0: 6a7b ldr r3, [r7, #36] ; 0x24
80150f2: 68db ldr r3, [r3, #12]
80150f4: 4322 orrs r2, r4
80150f6: b292 uxth r2, r2
80150f8: 819a strh r2, [r3, #12]
}
err = tcp_output_segment(seg, pcb, netif);
80150fa: 697a ldr r2, [r7, #20]
80150fc: 6879 ldr r1, [r7, #4]
80150fe: 6a78 ldr r0, [r7, #36] ; 0x24
8015100: f000 f908 bl 8015314 <tcp_output_segment>
8015104: 4603 mov r3, r0
8015106: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
8015108: f997 300f ldrsb.w r3, [r7, #15]
801510c: 2b00 cmp r3, #0
801510e: d009 beq.n 8015124 <tcp_output+0x240>
/* segment could not be sent, for whatever reason */
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8015110: 687b ldr r3, [r7, #4]
8015112: 8b5b ldrh r3, [r3, #26]
8015114: f043 0380 orr.w r3, r3, #128 ; 0x80
8015118: b29a uxth r2, r3
801511a: 687b ldr r3, [r7, #4]
801511c: 835a strh r2, [r3, #26]
return err;
801511e: f997 300f ldrsb.w r3, [r7, #15]
8015122: e0d2 b.n 80152ca <tcp_output+0x3e6>
}
#if TCP_OVERSIZE_DBGCHECK
seg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
pcb->unsent = seg->next;
8015124: 6a7b ldr r3, [r7, #36] ; 0x24
8015126: 681a ldr r2, [r3, #0]
8015128: 687b ldr r3, [r7, #4]
801512a: 66da str r2, [r3, #108] ; 0x6c
if (pcb->state != SYN_SENT) {
801512c: 687b ldr r3, [r7, #4]
801512e: 7d1b ldrb r3, [r3, #20]
8015130: 2b02 cmp r3, #2
8015132: d006 beq.n 8015142 <tcp_output+0x25e>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015134: 687b ldr r3, [r7, #4]
8015136: 8b5b ldrh r3, [r3, #26]
8015138: f023 0303 bic.w r3, r3, #3
801513c: b29a uxth r2, r3
801513e: 687b ldr r3, [r7, #4]
8015140: 835a strh r2, [r3, #26]
}
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
8015142: 6a7b ldr r3, [r7, #36] ; 0x24
8015144: 68db ldr r3, [r3, #12]
8015146: 685b ldr r3, [r3, #4]
8015148: 4618 mov r0, r3
801514a: f7f9 feae bl 800eeaa <lwip_htonl>
801514e: 4604 mov r4, r0
8015150: 6a7b ldr r3, [r7, #36] ; 0x24
8015152: 891b ldrh r3, [r3, #8]
8015154: 461d mov r5, r3
8015156: 6a7b ldr r3, [r7, #36] ; 0x24
8015158: 68db ldr r3, [r3, #12]
801515a: 899b ldrh r3, [r3, #12]
801515c: b29b uxth r3, r3
801515e: 4618 mov r0, r3
8015160: f7f9 fe8e bl 800ee80 <lwip_htons>
8015164: 4603 mov r3, r0
8015166: b2db uxtb r3, r3
8015168: f003 0303 and.w r3, r3, #3
801516c: 2b00 cmp r3, #0
801516e: d00d beq.n 801518c <tcp_output+0x2a8>
8015170: 2301 movs r3, #1
8015172: e00c b.n 801518e <tcp_output+0x2aa>
8015174: 0801d730 .word 0x0801d730
8015178: 0801dc74 .word 0x0801dc74
801517c: 0801d784 .word 0x0801d784
8015180: 0801dc8c .word 0x0801dc8c
8015184: 2000f5d4 .word 0x2000f5d4
8015188: 0801dcb4 .word 0x0801dcb4
801518c: 2300 movs r3, #0
801518e: 442b add r3, r5
8015190: 4423 add r3, r4
8015192: 60bb str r3, [r7, #8]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
8015194: 687b ldr r3, [r7, #4]
8015196: 6d1a ldr r2, [r3, #80] ; 0x50
8015198: 68bb ldr r3, [r7, #8]
801519a: 1ad3 subs r3, r2, r3
801519c: 2b00 cmp r3, #0
801519e: da02 bge.n 80151a6 <tcp_output+0x2c2>
pcb->snd_nxt = snd_nxt;
80151a0: 687b ldr r3, [r7, #4]
80151a2: 68ba ldr r2, [r7, #8]
80151a4: 651a str r2, [r3, #80] ; 0x50
}
/* put segment on unacknowledged list if length > 0 */
if (TCP_TCPLEN(seg) > 0) {
80151a6: 6a7b ldr r3, [r7, #36] ; 0x24
80151a8: 891b ldrh r3, [r3, #8]
80151aa: 461c mov r4, r3
80151ac: 6a7b ldr r3, [r7, #36] ; 0x24
80151ae: 68db ldr r3, [r3, #12]
80151b0: 899b ldrh r3, [r3, #12]
80151b2: b29b uxth r3, r3
80151b4: 4618 mov r0, r3
80151b6: f7f9 fe63 bl 800ee80 <lwip_htons>
80151ba: 4603 mov r3, r0
80151bc: b2db uxtb r3, r3
80151be: f003 0303 and.w r3, r3, #3
80151c2: 2b00 cmp r3, #0
80151c4: d001 beq.n 80151ca <tcp_output+0x2e6>
80151c6: 2301 movs r3, #1
80151c8: e000 b.n 80151cc <tcp_output+0x2e8>
80151ca: 2300 movs r3, #0
80151cc: 4423 add r3, r4
80151ce: 2b00 cmp r3, #0
80151d0: d049 beq.n 8015266 <tcp_output+0x382>
seg->next = NULL;
80151d2: 6a7b ldr r3, [r7, #36] ; 0x24
80151d4: 2200 movs r2, #0
80151d6: 601a str r2, [r3, #0]
/* unacked list is empty? */
if (pcb->unacked == NULL) {
80151d8: 687b ldr r3, [r7, #4]
80151da: 6f1b ldr r3, [r3, #112] ; 0x70
80151dc: 2b00 cmp r3, #0
80151de: d105 bne.n 80151ec <tcp_output+0x308>
pcb->unacked = seg;
80151e0: 687b ldr r3, [r7, #4]
80151e2: 6a7a ldr r2, [r7, #36] ; 0x24
80151e4: 671a str r2, [r3, #112] ; 0x70
useg = seg;
80151e6: 6a7b ldr r3, [r7, #36] ; 0x24
80151e8: 623b str r3, [r7, #32]
80151ea: e03f b.n 801526c <tcp_output+0x388>
/* unacked list is not empty? */
} else {
/* In the case of fast retransmit, the packet should not go to the tail
* of the unacked queue, but rather somewhere before it. We need to check for
* this case. -STJ Jul 27, 2004 */
if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
80151ec: 6a7b ldr r3, [r7, #36] ; 0x24
80151ee: 68db ldr r3, [r3, #12]
80151f0: 685b ldr r3, [r3, #4]
80151f2: 4618 mov r0, r3
80151f4: f7f9 fe59 bl 800eeaa <lwip_htonl>
80151f8: 4604 mov r4, r0
80151fa: 6a3b ldr r3, [r7, #32]
80151fc: 68db ldr r3, [r3, #12]
80151fe: 685b ldr r3, [r3, #4]
8015200: 4618 mov r0, r3
8015202: f7f9 fe52 bl 800eeaa <lwip_htonl>
8015206: 4603 mov r3, r0
8015208: 1ae3 subs r3, r4, r3
801520a: 2b00 cmp r3, #0
801520c: da24 bge.n 8015258 <tcp_output+0x374>
/* add segment to before tail of unacked list, keeping the list sorted */
struct tcp_seg **cur_seg = &(pcb->unacked);
801520e: 687b ldr r3, [r7, #4]
8015210: 3370 adds r3, #112 ; 0x70
8015212: 61fb str r3, [r7, #28]
while (*cur_seg &&
8015214: e002 b.n 801521c <tcp_output+0x338>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
8015216: 69fb ldr r3, [r7, #28]
8015218: 681b ldr r3, [r3, #0]
801521a: 61fb str r3, [r7, #28]
while (*cur_seg &&
801521c: 69fb ldr r3, [r7, #28]
801521e: 681b ldr r3, [r3, #0]
8015220: 2b00 cmp r3, #0
8015222: d011 beq.n 8015248 <tcp_output+0x364>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
8015224: 69fb ldr r3, [r7, #28]
8015226: 681b ldr r3, [r3, #0]
8015228: 68db ldr r3, [r3, #12]
801522a: 685b ldr r3, [r3, #4]
801522c: 4618 mov r0, r3
801522e: f7f9 fe3c bl 800eeaa <lwip_htonl>
8015232: 4604 mov r4, r0
8015234: 6a7b ldr r3, [r7, #36] ; 0x24
8015236: 68db ldr r3, [r3, #12]
8015238: 685b ldr r3, [r3, #4]
801523a: 4618 mov r0, r3
801523c: f7f9 fe35 bl 800eeaa <lwip_htonl>
8015240: 4603 mov r3, r0
8015242: 1ae3 subs r3, r4, r3
while (*cur_seg &&
8015244: 2b00 cmp r3, #0
8015246: dbe6 blt.n 8015216 <tcp_output+0x332>
}
seg->next = (*cur_seg);
8015248: 69fb ldr r3, [r7, #28]
801524a: 681a ldr r2, [r3, #0]
801524c: 6a7b ldr r3, [r7, #36] ; 0x24
801524e: 601a str r2, [r3, #0]
(*cur_seg) = seg;
8015250: 69fb ldr r3, [r7, #28]
8015252: 6a7a ldr r2, [r7, #36] ; 0x24
8015254: 601a str r2, [r3, #0]
8015256: e009 b.n 801526c <tcp_output+0x388>
} else {
/* add segment to tail of unacked list */
useg->next = seg;
8015258: 6a3b ldr r3, [r7, #32]
801525a: 6a7a ldr r2, [r7, #36] ; 0x24
801525c: 601a str r2, [r3, #0]
useg = useg->next;
801525e: 6a3b ldr r3, [r7, #32]
8015260: 681b ldr r3, [r3, #0]
8015262: 623b str r3, [r7, #32]
8015264: e002 b.n 801526c <tcp_output+0x388>
}
}
/* do not queue empty segments on the unacked list */
} else {
tcp_seg_free(seg);
8015266: 6a78 ldr r0, [r7, #36] ; 0x24
8015268: f7fc fc42 bl 8011af0 <tcp_seg_free>
}
seg = pcb->unsent;
801526c: 687b ldr r3, [r7, #4]
801526e: 6edb ldr r3, [r3, #108] ; 0x6c
8015270: 627b str r3, [r7, #36] ; 0x24
while (seg != NULL &&
8015272: 6a7b ldr r3, [r7, #36] ; 0x24
8015274: 2b00 cmp r3, #0
8015276: d012 beq.n 801529e <tcp_output+0x3ba>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
8015278: 6a7b ldr r3, [r7, #36] ; 0x24
801527a: 68db ldr r3, [r3, #12]
801527c: 685b ldr r3, [r3, #4]
801527e: 4618 mov r0, r3
8015280: f7f9 fe13 bl 800eeaa <lwip_htonl>
8015284: 4602 mov r2, r0
8015286: 687b ldr r3, [r7, #4]
8015288: 6c5b ldr r3, [r3, #68] ; 0x44
801528a: 1ad3 subs r3, r2, r3
801528c: 6a7a ldr r2, [r7, #36] ; 0x24
801528e: 8912 ldrh r2, [r2, #8]
8015290: 4413 add r3, r2
while (seg != NULL &&
8015292: 69ba ldr r2, [r7, #24]
8015294: 429a cmp r2, r3
8015296: f4bf aeda bcs.w 801504e <tcp_output+0x16a>
801529a: e000 b.n 801529e <tcp_output+0x3ba>
break;
801529c: bf00 nop
}
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
801529e: 687b ldr r3, [r7, #4]
80152a0: 6edb ldr r3, [r3, #108] ; 0x6c
80152a2: 2b00 cmp r3, #0
80152a4: d108 bne.n 80152b8 <tcp_output+0x3d4>
/* last unsent has been removed, reset unsent_oversize */
pcb->unsent_oversize = 0;
80152a6: 687b ldr r3, [r7, #4]
80152a8: 2200 movs r2, #0
80152aa: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
80152ae: e004 b.n 80152ba <tcp_output+0x3d6>
goto output_done;
80152b0: bf00 nop
80152b2: e002 b.n 80152ba <tcp_output+0x3d6>
goto output_done;
80152b4: bf00 nop
80152b6: e000 b.n 80152ba <tcp_output+0x3d6>
}
#endif /* TCP_OVERSIZE */
output_done:
80152b8: bf00 nop
tcp_clear_flags(pcb, TF_NAGLEMEMERR);
80152ba: 687b ldr r3, [r7, #4]
80152bc: 8b5b ldrh r3, [r3, #26]
80152be: f023 0380 bic.w r3, r3, #128 ; 0x80
80152c2: b29a uxth r2, r3
80152c4: 687b ldr r3, [r7, #4]
80152c6: 835a strh r2, [r3, #26]
return ERR_OK;
80152c8: 2300 movs r3, #0
}
80152ca: 4618 mov r0, r3
80152cc: 3728 adds r7, #40 ; 0x28
80152ce: 46bd mov sp, r7
80152d0: bdb0 pop {r4, r5, r7, pc}
80152d2: bf00 nop
080152d4 <tcp_output_segment_busy>:
* @arg seg the tcp segment to check
* @return 1 if ref != 1, 0 if ref == 1
*/
static int
tcp_output_segment_busy(const struct tcp_seg *seg)
{
80152d4: b580 push {r7, lr}
80152d6: b082 sub sp, #8
80152d8: af00 add r7, sp, #0
80152da: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
80152dc: 687b ldr r3, [r7, #4]
80152de: 2b00 cmp r3, #0
80152e0: d106 bne.n 80152f0 <tcp_output_segment_busy+0x1c>
80152e2: 4b09 ldr r3, [pc, #36] ; (8015308 <tcp_output_segment_busy+0x34>)
80152e4: f240 529a movw r2, #1434 ; 0x59a
80152e8: 4908 ldr r1, [pc, #32] ; (801530c <tcp_output_segment_busy+0x38>)
80152ea: 4809 ldr r0, [pc, #36] ; (8015310 <tcp_output_segment_busy+0x3c>)
80152ec: f005 fe92 bl 801b014 <iprintf>
/* We only need to check the first pbuf here:
If a pbuf is queued for transmission, a driver calls pbuf_ref(),
which only changes the ref count of the first pbuf */
if (seg->p->ref != 1) {
80152f0: 687b ldr r3, [r7, #4]
80152f2: 685b ldr r3, [r3, #4]
80152f4: 7b9b ldrb r3, [r3, #14]
80152f6: 2b01 cmp r3, #1
80152f8: d001 beq.n 80152fe <tcp_output_segment_busy+0x2a>
/* other reference found */
return 1;
80152fa: 2301 movs r3, #1
80152fc: e000 b.n 8015300 <tcp_output_segment_busy+0x2c>
}
/* no other references found */
return 0;
80152fe: 2300 movs r3, #0
}
8015300: 4618 mov r0, r3
8015302: 3708 adds r7, #8
8015304: 46bd mov sp, r7
8015306: bd80 pop {r7, pc}
8015308: 0801d730 .word 0x0801d730
801530c: 0801dccc .word 0x0801dccc
8015310: 0801d784 .word 0x0801d784
08015314 <tcp_output_segment>:
* @param pcb the tcp_pcb for the TCP connection used to send the segment
* @param netif the netif used to send the segment
*/
static err_t
tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
{
8015314: b5b0 push {r4, r5, r7, lr}
8015316: b08c sub sp, #48 ; 0x30
8015318: af04 add r7, sp, #16
801531a: 60f8 str r0, [r7, #12]
801531c: 60b9 str r1, [r7, #8]
801531e: 607a str r2, [r7, #4]
u32_t *opts;
#if TCP_CHECKSUM_ON_COPY
int seg_chksum_was_swapped = 0;
#endif
LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
8015320: 68fb ldr r3, [r7, #12]
8015322: 2b00 cmp r3, #0
8015324: d106 bne.n 8015334 <tcp_output_segment+0x20>
8015326: 4b64 ldr r3, [pc, #400] ; (80154b8 <tcp_output_segment+0x1a4>)
8015328: f44f 62b7 mov.w r2, #1464 ; 0x5b8
801532c: 4963 ldr r1, [pc, #396] ; (80154bc <tcp_output_segment+0x1a8>)
801532e: 4864 ldr r0, [pc, #400] ; (80154c0 <tcp_output_segment+0x1ac>)
8015330: f005 fe70 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
8015334: 68bb ldr r3, [r7, #8]
8015336: 2b00 cmp r3, #0
8015338: d106 bne.n 8015348 <tcp_output_segment+0x34>
801533a: 4b5f ldr r3, [pc, #380] ; (80154b8 <tcp_output_segment+0x1a4>)
801533c: f240 52b9 movw r2, #1465 ; 0x5b9
8015340: 4960 ldr r1, [pc, #384] ; (80154c4 <tcp_output_segment+0x1b0>)
8015342: 485f ldr r0, [pc, #380] ; (80154c0 <tcp_output_segment+0x1ac>)
8015344: f005 fe66 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
8015348: 687b ldr r3, [r7, #4]
801534a: 2b00 cmp r3, #0
801534c: d106 bne.n 801535c <tcp_output_segment+0x48>
801534e: 4b5a ldr r3, [pc, #360] ; (80154b8 <tcp_output_segment+0x1a4>)
8015350: f240 52ba movw r2, #1466 ; 0x5ba
8015354: 495c ldr r1, [pc, #368] ; (80154c8 <tcp_output_segment+0x1b4>)
8015356: 485a ldr r0, [pc, #360] ; (80154c0 <tcp_output_segment+0x1ac>)
8015358: f005 fe5c bl 801b014 <iprintf>
if (tcp_output_segment_busy(seg)) {
801535c: 68f8 ldr r0, [r7, #12]
801535e: f7ff ffb9 bl 80152d4 <tcp_output_segment_busy>
8015362: 4603 mov r3, r0
8015364: 2b00 cmp r3, #0
8015366: d001 beq.n 801536c <tcp_output_segment+0x58>
/* This should not happen: rexmit functions should have checked this.
However, since this function modifies p->len, we must not continue in this case. */
LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
return ERR_OK;
8015368: 2300 movs r3, #0
801536a: e0a0 b.n 80154ae <tcp_output_segment+0x19a>
}
/* The TCP header has already been constructed, but the ackno and
wnd fields remain. */
seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
801536c: 68bb ldr r3, [r7, #8]
801536e: 6a5a ldr r2, [r3, #36] ; 0x24
8015370: 68fb ldr r3, [r7, #12]
8015372: 68dc ldr r4, [r3, #12]
8015374: 4610 mov r0, r2
8015376: f7f9 fd98 bl 800eeaa <lwip_htonl>
801537a: 4603 mov r3, r0
801537c: 60a3 str r3, [r4, #8]
the window scale option) is never scaled. */
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
} else
#endif /* LWIP_WND_SCALE */
{
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
801537e: 68bb ldr r3, [r7, #8]
8015380: 8d5a ldrh r2, [r3, #42] ; 0x2a
8015382: 68fb ldr r3, [r7, #12]
8015384: 68dc ldr r4, [r3, #12]
8015386: 4610 mov r0, r2
8015388: f7f9 fd7a bl 800ee80 <lwip_htons>
801538c: 4603 mov r3, r0
801538e: 81e3 strh r3, [r4, #14]
}
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
8015390: 68bb ldr r3, [r7, #8]
8015392: 6a5b ldr r3, [r3, #36] ; 0x24
8015394: 68ba ldr r2, [r7, #8]
8015396: 8d52 ldrh r2, [r2, #42] ; 0x2a
8015398: 441a add r2, r3
801539a: 68bb ldr r3, [r7, #8]
801539c: 62da str r2, [r3, #44] ; 0x2c
/* Add any requested options. NB MSS option is only set on SYN
packets, so ignore it here */
/* cast through void* to get rid of alignment warnings */
opts = (u32_t *)(void *)(seg->tcphdr + 1);
801539e: 68fb ldr r3, [r7, #12]
80153a0: 68db ldr r3, [r3, #12]
80153a2: 3314 adds r3, #20
80153a4: 61fb str r3, [r7, #28]
if (seg->flags & TF_SEG_OPTS_MSS) {
80153a6: 68fb ldr r3, [r7, #12]
80153a8: 7a9b ldrb r3, [r3, #10]
80153aa: f003 0301 and.w r3, r3, #1
80153ae: 2b00 cmp r3, #0
80153b0: d015 beq.n 80153de <tcp_output_segment+0xca>
u16_t mss;
#if TCP_CALCULATE_EFF_SEND_MSS
mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
80153b2: 68bb ldr r3, [r7, #8]
80153b4: 3304 adds r3, #4
80153b6: 461a mov r2, r3
80153b8: 6879 ldr r1, [r7, #4]
80153ba: f44f 7006 mov.w r0, #536 ; 0x218
80153be: f7fc fe8d bl 80120dc <tcp_eff_send_mss_netif>
80153c2: 4603 mov r3, r0
80153c4: 837b strh r3, [r7, #26]
#else /* TCP_CALCULATE_EFF_SEND_MSS */
mss = TCP_MSS;
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
*opts = TCP_BUILD_MSS_OPTION(mss);
80153c6: 8b7b ldrh r3, [r7, #26]
80153c8: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000
80153cc: 4618 mov r0, r3
80153ce: f7f9 fd6c bl 800eeaa <lwip_htonl>
80153d2: 4602 mov r2, r0
80153d4: 69fb ldr r3, [r7, #28]
80153d6: 601a str r2, [r3, #0]
opts += 1;
80153d8: 69fb ldr r3, [r7, #28]
80153da: 3304 adds r3, #4
80153dc: 61fb str r3, [r7, #28]
}
#endif
/* Set retransmission timer running if it is not currently enabled
This must be set before checking the route. */
if (pcb->rtime < 0) {
80153de: 68bb ldr r3, [r7, #8]
80153e0: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80153e4: 2b00 cmp r3, #0
80153e6: da02 bge.n 80153ee <tcp_output_segment+0xda>
pcb->rtime = 0;
80153e8: 68bb ldr r3, [r7, #8]
80153ea: 2200 movs r2, #0
80153ec: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rttest == 0) {
80153ee: 68bb ldr r3, [r7, #8]
80153f0: 6b5b ldr r3, [r3, #52] ; 0x34
80153f2: 2b00 cmp r3, #0
80153f4: d10c bne.n 8015410 <tcp_output_segment+0xfc>
pcb->rttest = tcp_ticks;
80153f6: 4b35 ldr r3, [pc, #212] ; (80154cc <tcp_output_segment+0x1b8>)
80153f8: 681a ldr r2, [r3, #0]
80153fa: 68bb ldr r3, [r7, #8]
80153fc: 635a str r2, [r3, #52] ; 0x34
pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
80153fe: 68fb ldr r3, [r7, #12]
8015400: 68db ldr r3, [r3, #12]
8015402: 685b ldr r3, [r3, #4]
8015404: 4618 mov r0, r3
8015406: f7f9 fd50 bl 800eeaa <lwip_htonl>
801540a: 4602 mov r2, r0
801540c: 68bb ldr r3, [r7, #8]
801540e: 639a str r2, [r3, #56] ; 0x38
}
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
seg->len));
len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
8015410: 68fb ldr r3, [r7, #12]
8015412: 68db ldr r3, [r3, #12]
8015414: 461a mov r2, r3
8015416: 68fb ldr r3, [r7, #12]
8015418: 685b ldr r3, [r3, #4]
801541a: 685b ldr r3, [r3, #4]
801541c: 1ad3 subs r3, r2, r3
801541e: 833b strh r3, [r7, #24]
if (len == 0) {
/** Exclude retransmitted segments from this count. */
MIB2_STATS_INC(mib2.tcpoutsegs);
}
seg->p->len -= len;
8015420: 68fb ldr r3, [r7, #12]
8015422: 685b ldr r3, [r3, #4]
8015424: 8959 ldrh r1, [r3, #10]
8015426: 68fb ldr r3, [r7, #12]
8015428: 685b ldr r3, [r3, #4]
801542a: 8b3a ldrh r2, [r7, #24]
801542c: 1a8a subs r2, r1, r2
801542e: b292 uxth r2, r2
8015430: 815a strh r2, [r3, #10]
seg->p->tot_len -= len;
8015432: 68fb ldr r3, [r7, #12]
8015434: 685b ldr r3, [r3, #4]
8015436: 8919 ldrh r1, [r3, #8]
8015438: 68fb ldr r3, [r7, #12]
801543a: 685b ldr r3, [r3, #4]
801543c: 8b3a ldrh r2, [r7, #24]
801543e: 1a8a subs r2, r1, r2
8015440: b292 uxth r2, r2
8015442: 811a strh r2, [r3, #8]
seg->p->payload = seg->tcphdr;
8015444: 68fb ldr r3, [r7, #12]
8015446: 685b ldr r3, [r3, #4]
8015448: 68fa ldr r2, [r7, #12]
801544a: 68d2 ldr r2, [r2, #12]
801544c: 605a str r2, [r3, #4]
seg->tcphdr->chksum = 0;
801544e: 68fb ldr r3, [r7, #12]
8015450: 68db ldr r3, [r3, #12]
8015452: 2200 movs r2, #0
8015454: 741a strb r2, [r3, #16]
8015456: 2200 movs r2, #0
8015458: 745a strb r2, [r3, #17]
#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
#endif
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
801545a: 68fb ldr r3, [r7, #12]
801545c: 68db ldr r3, [r3, #12]
801545e: f103 0214 add.w r2, r3, #20
8015462: 68fb ldr r3, [r7, #12]
8015464: 7a9b ldrb r3, [r3, #10]
8015466: 009b lsls r3, r3, #2
8015468: f003 0304 and.w r3, r3, #4
801546c: 4413 add r3, r2
801546e: 69fa ldr r2, [r7, #28]
8015470: 429a cmp r2, r3
8015472: d006 beq.n 8015482 <tcp_output_segment+0x16e>
8015474: 4b10 ldr r3, [pc, #64] ; (80154b8 <tcp_output_segment+0x1a4>)
8015476: f240 621c movw r2, #1564 ; 0x61c
801547a: 4915 ldr r1, [pc, #84] ; (80154d0 <tcp_output_segment+0x1bc>)
801547c: 4810 ldr r0, [pc, #64] ; (80154c0 <tcp_output_segment+0x1ac>)
801547e: f005 fdc9 bl 801b014 <iprintf>
}
#endif /* CHECKSUM_GEN_TCP */
TCP_STATS_INC(tcp.xmit);
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
8015482: 68fb ldr r3, [r7, #12]
8015484: 6858 ldr r0, [r3, #4]
8015486: 68b9 ldr r1, [r7, #8]
8015488: 68bb ldr r3, [r7, #8]
801548a: 1d1c adds r4, r3, #4
801548c: 68bb ldr r3, [r7, #8]
801548e: 7add ldrb r5, [r3, #11]
8015490: 68bb ldr r3, [r7, #8]
8015492: 7a9b ldrb r3, [r3, #10]
8015494: 687a ldr r2, [r7, #4]
8015496: 9202 str r2, [sp, #8]
8015498: 2206 movs r2, #6
801549a: 9201 str r2, [sp, #4]
801549c: 9300 str r3, [sp, #0]
801549e: 462b mov r3, r5
80154a0: 4622 mov r2, r4
80154a2: f004 fc37 bl 8019d14 <ip4_output_if>
80154a6: 4603 mov r3, r0
80154a8: 75fb strb r3, [r7, #23]
seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
seg->chksum_swapped = 1;
}
#endif
return err;
80154aa: f997 3017 ldrsb.w r3, [r7, #23]
}
80154ae: 4618 mov r0, r3
80154b0: 3720 adds r7, #32
80154b2: 46bd mov sp, r7
80154b4: bdb0 pop {r4, r5, r7, pc}
80154b6: bf00 nop
80154b8: 0801d730 .word 0x0801d730
80154bc: 0801dcf4 .word 0x0801dcf4
80154c0: 0801d784 .word 0x0801d784
80154c4: 0801dd14 .word 0x0801dd14
80154c8: 0801dd34 .word 0x0801dd34
80154cc: 2000f5c4 .word 0x2000f5c4
80154d0: 0801dd58 .word 0x0801dd58
080154d4 <tcp_rexmit_rto_prepare>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
err_t
tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
{
80154d4: b5b0 push {r4, r5, r7, lr}
80154d6: b084 sub sp, #16
80154d8: af00 add r7, sp, #0
80154da: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
80154dc: 687b ldr r3, [r7, #4]
80154de: 2b00 cmp r3, #0
80154e0: d106 bne.n 80154f0 <tcp_rexmit_rto_prepare+0x1c>
80154e2: 4b31 ldr r3, [pc, #196] ; (80155a8 <tcp_rexmit_rto_prepare+0xd4>)
80154e4: f240 6263 movw r2, #1635 ; 0x663
80154e8: 4930 ldr r1, [pc, #192] ; (80155ac <tcp_rexmit_rto_prepare+0xd8>)
80154ea: 4831 ldr r0, [pc, #196] ; (80155b0 <tcp_rexmit_rto_prepare+0xdc>)
80154ec: f005 fd92 bl 801b014 <iprintf>
if (pcb->unacked == NULL) {
80154f0: 687b ldr r3, [r7, #4]
80154f2: 6f1b ldr r3, [r3, #112] ; 0x70
80154f4: 2b00 cmp r3, #0
80154f6: d102 bne.n 80154fe <tcp_rexmit_rto_prepare+0x2a>
return ERR_VAL;
80154f8: f06f 0305 mvn.w r3, #5
80154fc: e050 b.n 80155a0 <tcp_rexmit_rto_prepare+0xcc>
/* Move all unacked segments to the head of the unsent queue.
However, give up if any of the unsent pbufs are still referenced by the
netif driver due to deferred transmission. No point loading the link further
if it is struggling to flush its buffered writes. */
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
80154fe: 687b ldr r3, [r7, #4]
8015500: 6f1b ldr r3, [r3, #112] ; 0x70
8015502: 60fb str r3, [r7, #12]
8015504: e00b b.n 801551e <tcp_rexmit_rto_prepare+0x4a>
if (tcp_output_segment_busy(seg)) {
8015506: 68f8 ldr r0, [r7, #12]
8015508: f7ff fee4 bl 80152d4 <tcp_output_segment_busy>
801550c: 4603 mov r3, r0
801550e: 2b00 cmp r3, #0
8015510: d002 beq.n 8015518 <tcp_rexmit_rto_prepare+0x44>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
8015512: f06f 0305 mvn.w r3, #5
8015516: e043 b.n 80155a0 <tcp_rexmit_rto_prepare+0xcc>
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
8015518: 68fb ldr r3, [r7, #12]
801551a: 681b ldr r3, [r3, #0]
801551c: 60fb str r3, [r7, #12]
801551e: 68fb ldr r3, [r7, #12]
8015520: 681b ldr r3, [r3, #0]
8015522: 2b00 cmp r3, #0
8015524: d1ef bne.n 8015506 <tcp_rexmit_rto_prepare+0x32>
}
}
if (tcp_output_segment_busy(seg)) {
8015526: 68f8 ldr r0, [r7, #12]
8015528: f7ff fed4 bl 80152d4 <tcp_output_segment_busy>
801552c: 4603 mov r3, r0
801552e: 2b00 cmp r3, #0
8015530: d002 beq.n 8015538 <tcp_rexmit_rto_prepare+0x64>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
8015532: f06f 0305 mvn.w r3, #5
8015536: e033 b.n 80155a0 <tcp_rexmit_rto_prepare+0xcc>
}
/* concatenate unsent queue after unacked queue */
seg->next = pcb->unsent;
8015538: 687b ldr r3, [r7, #4]
801553a: 6eda ldr r2, [r3, #108] ; 0x6c
801553c: 68fb ldr r3, [r7, #12]
801553e: 601a str r2, [r3, #0]
if (pcb->unsent == NULL) {
pcb->unsent_oversize = seg->oversize_left;
}
#endif /* TCP_OVERSIZE_DBGCHECK */
/* unsent queue is the concatenated queue (of unacked, unsent) */
pcb->unsent = pcb->unacked;
8015540: 687b ldr r3, [r7, #4]
8015542: 6f1a ldr r2, [r3, #112] ; 0x70
8015544: 687b ldr r3, [r7, #4]
8015546: 66da str r2, [r3, #108] ; 0x6c
/* unacked queue is now empty */
pcb->unacked = NULL;
8015548: 687b ldr r3, [r7, #4]
801554a: 2200 movs r2, #0
801554c: 671a str r2, [r3, #112] ; 0x70
/* Mark RTO in-progress */
tcp_set_flags(pcb, TF_RTO);
801554e: 687b ldr r3, [r7, #4]
8015550: 8b5b ldrh r3, [r3, #26]
8015552: f443 6300 orr.w r3, r3, #2048 ; 0x800
8015556: b29a uxth r2, r3
8015558: 687b ldr r3, [r7, #4]
801555a: 835a strh r2, [r3, #26]
/* Record the next byte following retransmit */
pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
801555c: 68fb ldr r3, [r7, #12]
801555e: 68db ldr r3, [r3, #12]
8015560: 685b ldr r3, [r3, #4]
8015562: 4618 mov r0, r3
8015564: f7f9 fca1 bl 800eeaa <lwip_htonl>
8015568: 4604 mov r4, r0
801556a: 68fb ldr r3, [r7, #12]
801556c: 891b ldrh r3, [r3, #8]
801556e: 461d mov r5, r3
8015570: 68fb ldr r3, [r7, #12]
8015572: 68db ldr r3, [r3, #12]
8015574: 899b ldrh r3, [r3, #12]
8015576: b29b uxth r3, r3
8015578: 4618 mov r0, r3
801557a: f7f9 fc81 bl 800ee80 <lwip_htons>
801557e: 4603 mov r3, r0
8015580: b2db uxtb r3, r3
8015582: f003 0303 and.w r3, r3, #3
8015586: 2b00 cmp r3, #0
8015588: d001 beq.n 801558e <tcp_rexmit_rto_prepare+0xba>
801558a: 2301 movs r3, #1
801558c: e000 b.n 8015590 <tcp_rexmit_rto_prepare+0xbc>
801558e: 2300 movs r3, #0
8015590: 442b add r3, r5
8015592: 18e2 adds r2, r4, r3
8015594: 687b ldr r3, [r7, #4]
8015596: 64da str r2, [r3, #76] ; 0x4c
/* Don't take any RTT measurements after retransmitting. */
pcb->rttest = 0;
8015598: 687b ldr r3, [r7, #4]
801559a: 2200 movs r2, #0
801559c: 635a str r2, [r3, #52] ; 0x34
return ERR_OK;
801559e: 2300 movs r3, #0
}
80155a0: 4618 mov r0, r3
80155a2: 3710 adds r7, #16
80155a4: 46bd mov sp, r7
80155a6: bdb0 pop {r4, r5, r7, pc}
80155a8: 0801d730 .word 0x0801d730
80155ac: 0801dd6c .word 0x0801dd6c
80155b0: 0801d784 .word 0x0801d784
080155b4 <tcp_rexmit_rto_commit>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
{
80155b4: b580 push {r7, lr}
80155b6: b082 sub sp, #8
80155b8: af00 add r7, sp, #0
80155ba: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
80155bc: 687b ldr r3, [r7, #4]
80155be: 2b00 cmp r3, #0
80155c0: d106 bne.n 80155d0 <tcp_rexmit_rto_commit+0x1c>
80155c2: 4b0d ldr r3, [pc, #52] ; (80155f8 <tcp_rexmit_rto_commit+0x44>)
80155c4: f44f 62d3 mov.w r2, #1688 ; 0x698
80155c8: 490c ldr r1, [pc, #48] ; (80155fc <tcp_rexmit_rto_commit+0x48>)
80155ca: 480d ldr r0, [pc, #52] ; (8015600 <tcp_rexmit_rto_commit+0x4c>)
80155cc: f005 fd22 bl 801b014 <iprintf>
/* increment number of retransmissions */
if (pcb->nrtx < 0xFF) {
80155d0: 687b ldr r3, [r7, #4]
80155d2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155d6: 2bff cmp r3, #255 ; 0xff
80155d8: d007 beq.n 80155ea <tcp_rexmit_rto_commit+0x36>
++pcb->nrtx;
80155da: 687b ldr r3, [r7, #4]
80155dc: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155e0: 3301 adds r3, #1
80155e2: b2da uxtb r2, r3
80155e4: 687b ldr r3, [r7, #4]
80155e6: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Do the actual retransmission */
tcp_output(pcb);
80155ea: 6878 ldr r0, [r7, #4]
80155ec: f7ff fc7a bl 8014ee4 <tcp_output>
}
80155f0: bf00 nop
80155f2: 3708 adds r7, #8
80155f4: 46bd mov sp, r7
80155f6: bd80 pop {r7, pc}
80155f8: 0801d730 .word 0x0801d730
80155fc: 0801dd90 .word 0x0801dd90
8015600: 0801d784 .word 0x0801d784
08015604 <tcp_rexmit_rto>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto(struct tcp_pcb *pcb)
{
8015604: b580 push {r7, lr}
8015606: b082 sub sp, #8
8015608: af00 add r7, sp, #0
801560a: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
801560c: 687b ldr r3, [r7, #4]
801560e: 2b00 cmp r3, #0
8015610: d106 bne.n 8015620 <tcp_rexmit_rto+0x1c>
8015612: 4b0a ldr r3, [pc, #40] ; (801563c <tcp_rexmit_rto+0x38>)
8015614: f240 62ad movw r2, #1709 ; 0x6ad
8015618: 4909 ldr r1, [pc, #36] ; (8015640 <tcp_rexmit_rto+0x3c>)
801561a: 480a ldr r0, [pc, #40] ; (8015644 <tcp_rexmit_rto+0x40>)
801561c: f005 fcfa bl 801b014 <iprintf>
if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
8015620: 6878 ldr r0, [r7, #4]
8015622: f7ff ff57 bl 80154d4 <tcp_rexmit_rto_prepare>
8015626: 4603 mov r3, r0
8015628: 2b00 cmp r3, #0
801562a: d102 bne.n 8015632 <tcp_rexmit_rto+0x2e>
tcp_rexmit_rto_commit(pcb);
801562c: 6878 ldr r0, [r7, #4]
801562e: f7ff ffc1 bl 80155b4 <tcp_rexmit_rto_commit>
}
}
8015632: bf00 nop
8015634: 3708 adds r7, #8
8015636: 46bd mov sp, r7
8015638: bd80 pop {r7, pc}
801563a: bf00 nop
801563c: 0801d730 .word 0x0801d730
8015640: 0801ddb4 .word 0x0801ddb4
8015644: 0801d784 .word 0x0801d784
08015648 <tcp_rexmit>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
err_t
tcp_rexmit(struct tcp_pcb *pcb)
{
8015648: b590 push {r4, r7, lr}
801564a: b085 sub sp, #20
801564c: af00 add r7, sp, #0
801564e: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
struct tcp_seg **cur_seg;
LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
8015650: 687b ldr r3, [r7, #4]
8015652: 2b00 cmp r3, #0
8015654: d106 bne.n 8015664 <tcp_rexmit+0x1c>
8015656: 4b2f ldr r3, [pc, #188] ; (8015714 <tcp_rexmit+0xcc>)
8015658: f240 62c1 movw r2, #1729 ; 0x6c1
801565c: 492e ldr r1, [pc, #184] ; (8015718 <tcp_rexmit+0xd0>)
801565e: 482f ldr r0, [pc, #188] ; (801571c <tcp_rexmit+0xd4>)
8015660: f005 fcd8 bl 801b014 <iprintf>
if (pcb->unacked == NULL) {
8015664: 687b ldr r3, [r7, #4]
8015666: 6f1b ldr r3, [r3, #112] ; 0x70
8015668: 2b00 cmp r3, #0
801566a: d102 bne.n 8015672 <tcp_rexmit+0x2a>
return ERR_VAL;
801566c: f06f 0305 mvn.w r3, #5
8015670: e04c b.n 801570c <tcp_rexmit+0xc4>
}
seg = pcb->unacked;
8015672: 687b ldr r3, [r7, #4]
8015674: 6f1b ldr r3, [r3, #112] ; 0x70
8015676: 60bb str r3, [r7, #8]
/* Give up if the segment is still referenced by the netif driver
due to deferred transmission. */
if (tcp_output_segment_busy(seg)) {
8015678: 68b8 ldr r0, [r7, #8]
801567a: f7ff fe2b bl 80152d4 <tcp_output_segment_busy>
801567e: 4603 mov r3, r0
8015680: 2b00 cmp r3, #0
8015682: d002 beq.n 801568a <tcp_rexmit+0x42>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
return ERR_VAL;
8015684: f06f 0305 mvn.w r3, #5
8015688: e040 b.n 801570c <tcp_rexmit+0xc4>
}
/* Move the first unacked segment to the unsent queue */
/* Keep the unsent queue sorted. */
pcb->unacked = seg->next;
801568a: 68bb ldr r3, [r7, #8]
801568c: 681a ldr r2, [r3, #0]
801568e: 687b ldr r3, [r7, #4]
8015690: 671a str r2, [r3, #112] ; 0x70
cur_seg = &(pcb->unsent);
8015692: 687b ldr r3, [r7, #4]
8015694: 336c adds r3, #108 ; 0x6c
8015696: 60fb str r3, [r7, #12]
while (*cur_seg &&
8015698: e002 b.n 80156a0 <tcp_rexmit+0x58>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
801569a: 68fb ldr r3, [r7, #12]
801569c: 681b ldr r3, [r3, #0]
801569e: 60fb str r3, [r7, #12]
while (*cur_seg &&
80156a0: 68fb ldr r3, [r7, #12]
80156a2: 681b ldr r3, [r3, #0]
80156a4: 2b00 cmp r3, #0
80156a6: d011 beq.n 80156cc <tcp_rexmit+0x84>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
80156a8: 68fb ldr r3, [r7, #12]
80156aa: 681b ldr r3, [r3, #0]
80156ac: 68db ldr r3, [r3, #12]
80156ae: 685b ldr r3, [r3, #4]
80156b0: 4618 mov r0, r3
80156b2: f7f9 fbfa bl 800eeaa <lwip_htonl>
80156b6: 4604 mov r4, r0
80156b8: 68bb ldr r3, [r7, #8]
80156ba: 68db ldr r3, [r3, #12]
80156bc: 685b ldr r3, [r3, #4]
80156be: 4618 mov r0, r3
80156c0: f7f9 fbf3 bl 800eeaa <lwip_htonl>
80156c4: 4603 mov r3, r0
80156c6: 1ae3 subs r3, r4, r3
while (*cur_seg &&
80156c8: 2b00 cmp r3, #0
80156ca: dbe6 blt.n 801569a <tcp_rexmit+0x52>
}
seg->next = *cur_seg;
80156cc: 68fb ldr r3, [r7, #12]
80156ce: 681a ldr r2, [r3, #0]
80156d0: 68bb ldr r3, [r7, #8]
80156d2: 601a str r2, [r3, #0]
*cur_seg = seg;
80156d4: 68fb ldr r3, [r7, #12]
80156d6: 68ba ldr r2, [r7, #8]
80156d8: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
if (seg->next == NULL) {
80156da: 68bb ldr r3, [r7, #8]
80156dc: 681b ldr r3, [r3, #0]
80156de: 2b00 cmp r3, #0
80156e0: d103 bne.n 80156ea <tcp_rexmit+0xa2>
/* the retransmitted segment is last in unsent, so reset unsent_oversize */
pcb->unsent_oversize = 0;
80156e2: 687b ldr r3, [r7, #4]
80156e4: 2200 movs r2, #0
80156e6: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
if (pcb->nrtx < 0xFF) {
80156ea: 687b ldr r3, [r7, #4]
80156ec: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80156f0: 2bff cmp r3, #255 ; 0xff
80156f2: d007 beq.n 8015704 <tcp_rexmit+0xbc>
++pcb->nrtx;
80156f4: 687b ldr r3, [r7, #4]
80156f6: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80156fa: 3301 adds r3, #1
80156fc: b2da uxtb r2, r3
80156fe: 687b ldr r3, [r7, #4]
8015700: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Don't take any rtt measurements after retransmitting. */
pcb->rttest = 0;
8015704: 687b ldr r3, [r7, #4]
8015706: 2200 movs r2, #0
8015708: 635a str r2, [r3, #52] ; 0x34
/* Do the actual retransmission. */
MIB2_STATS_INC(mib2.tcpretranssegs);
/* No need to call tcp_output: we are always called from tcp_input()
and thus tcp_output directly returns. */
return ERR_OK;
801570a: 2300 movs r3, #0
}
801570c: 4618 mov r0, r3
801570e: 3714 adds r7, #20
8015710: 46bd mov sp, r7
8015712: bd90 pop {r4, r7, pc}
8015714: 0801d730 .word 0x0801d730
8015718: 0801ddd0 .word 0x0801ddd0
801571c: 0801d784 .word 0x0801d784
08015720 <tcp_rexmit_fast>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
void
tcp_rexmit_fast(struct tcp_pcb *pcb)
{
8015720: b580 push {r7, lr}
8015722: b082 sub sp, #8
8015724: af00 add r7, sp, #0
8015726: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
8015728: 687b ldr r3, [r7, #4]
801572a: 2b00 cmp r3, #0
801572c: d106 bne.n 801573c <tcp_rexmit_fast+0x1c>
801572e: 4b2f ldr r3, [pc, #188] ; (80157ec <tcp_rexmit_fast+0xcc>)
8015730: f240 62f9 movw r2, #1785 ; 0x6f9
8015734: 492e ldr r1, [pc, #184] ; (80157f0 <tcp_rexmit_fast+0xd0>)
8015736: 482f ldr r0, [pc, #188] ; (80157f4 <tcp_rexmit_fast+0xd4>)
8015738: f005 fc6c bl 801b014 <iprintf>
if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
801573c: 687b ldr r3, [r7, #4]
801573e: 6f1b ldr r3, [r3, #112] ; 0x70
8015740: 2b00 cmp r3, #0
8015742: d04f beq.n 80157e4 <tcp_rexmit_fast+0xc4>
8015744: 687b ldr r3, [r7, #4]
8015746: 8b5b ldrh r3, [r3, #26]
8015748: f003 0304 and.w r3, r3, #4
801574c: 2b00 cmp r3, #0
801574e: d149 bne.n 80157e4 <tcp_rexmit_fast+0xc4>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: dupacks %"U16_F" (%"U32_F
"), fast retransmit %"U32_F"\n",
(u16_t)pcb->dupacks, pcb->lastack,
lwip_ntohl(pcb->unacked->tcphdr->seqno)));
if (tcp_rexmit(pcb) == ERR_OK) {
8015750: 6878 ldr r0, [r7, #4]
8015752: f7ff ff79 bl 8015648 <tcp_rexmit>
8015756: 4603 mov r3, r0
8015758: 2b00 cmp r3, #0
801575a: d143 bne.n 80157e4 <tcp_rexmit_fast+0xc4>
/* Set ssthresh to half of the minimum of the current
* cwnd and the advertised window */
pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
801575c: 687b ldr r3, [r7, #4]
801575e: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8015762: 687b ldr r3, [r7, #4]
8015764: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8015768: 429a cmp r2, r3
801576a: d208 bcs.n 801577e <tcp_rexmit_fast+0x5e>
801576c: 687b ldr r3, [r7, #4]
801576e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8015772: 2b00 cmp r3, #0
8015774: da00 bge.n 8015778 <tcp_rexmit_fast+0x58>
8015776: 3301 adds r3, #1
8015778: 105b asrs r3, r3, #1
801577a: b29b uxth r3, r3
801577c: e007 b.n 801578e <tcp_rexmit_fast+0x6e>
801577e: 687b ldr r3, [r7, #4]
8015780: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8015784: 2b00 cmp r3, #0
8015786: da00 bge.n 801578a <tcp_rexmit_fast+0x6a>
8015788: 3301 adds r3, #1
801578a: 105b asrs r3, r3, #1
801578c: b29b uxth r3, r3
801578e: 687a ldr r2, [r7, #4]
8015790: f8a2 304a strh.w r3, [r2, #74] ; 0x4a
/* The minimum value for ssthresh should be 2 MSS */
if (pcb->ssthresh < (2U * pcb->mss)) {
8015794: 687b ldr r3, [r7, #4]
8015796: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
801579a: 461a mov r2, r3
801579c: 687b ldr r3, [r7, #4]
801579e: 8e5b ldrh r3, [r3, #50] ; 0x32
80157a0: 005b lsls r3, r3, #1
80157a2: 429a cmp r2, r3
80157a4: d206 bcs.n 80157b4 <tcp_rexmit_fast+0x94>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
" should be min 2 mss %"U16_F"...\n",
pcb->ssthresh, (u16_t)(2 * pcb->mss)));
pcb->ssthresh = 2 * pcb->mss;
80157a6: 687b ldr r3, [r7, #4]
80157a8: 8e5b ldrh r3, [r3, #50] ; 0x32
80157aa: 005b lsls r3, r3, #1
80157ac: b29a uxth r2, r3
80157ae: 687b ldr r3, [r7, #4]
80157b0: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
80157b4: 687b ldr r3, [r7, #4]
80157b6: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
80157ba: 687b ldr r3, [r7, #4]
80157bc: 8e5b ldrh r3, [r3, #50] ; 0x32
80157be: 4619 mov r1, r3
80157c0: 0049 lsls r1, r1, #1
80157c2: 440b add r3, r1
80157c4: b29b uxth r3, r3
80157c6: 4413 add r3, r2
80157c8: b29a uxth r2, r3
80157ca: 687b ldr r3, [r7, #4]
80157cc: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
tcp_set_flags(pcb, TF_INFR);
80157d0: 687b ldr r3, [r7, #4]
80157d2: 8b5b ldrh r3, [r3, #26]
80157d4: f043 0304 orr.w r3, r3, #4
80157d8: b29a uxth r2, r3
80157da: 687b ldr r3, [r7, #4]
80157dc: 835a strh r2, [r3, #26]
/* Reset the retransmission timer to prevent immediate rto retransmissions */
pcb->rtime = 0;
80157de: 687b ldr r3, [r7, #4]
80157e0: 2200 movs r2, #0
80157e2: 861a strh r2, [r3, #48] ; 0x30
}
}
}
80157e4: bf00 nop
80157e6: 3708 adds r7, #8
80157e8: 46bd mov sp, r7
80157ea: bd80 pop {r7, pc}
80157ec: 0801d730 .word 0x0801d730
80157f0: 0801dde8 .word 0x0801dde8
80157f4: 0801d784 .word 0x0801d784
080157f8 <tcp_output_alloc_header_common>:
static struct pbuf *
tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */,
u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
{
80157f8: b580 push {r7, lr}
80157fa: b086 sub sp, #24
80157fc: af00 add r7, sp, #0
80157fe: 60f8 str r0, [r7, #12]
8015800: 607b str r3, [r7, #4]
8015802: 460b mov r3, r1
8015804: 817b strh r3, [r7, #10]
8015806: 4613 mov r3, r2
8015808: 813b strh r3, [r7, #8]
struct tcp_hdr *tcphdr;
struct pbuf *p;
p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
801580a: 897a ldrh r2, [r7, #10]
801580c: 893b ldrh r3, [r7, #8]
801580e: 4413 add r3, r2
8015810: b29b uxth r3, r3
8015812: 3314 adds r3, #20
8015814: b29b uxth r3, r3
8015816: f44f 7220 mov.w r2, #640 ; 0x280
801581a: 4619 mov r1, r3
801581c: 2022 movs r0, #34 ; 0x22
801581e: f7fa fc03 bl 8010028 <pbuf_alloc>
8015822: 6178 str r0, [r7, #20]
if (p != NULL) {
8015824: 697b ldr r3, [r7, #20]
8015826: 2b00 cmp r3, #0
8015828: d04e beq.n 80158c8 <tcp_output_alloc_header_common+0xd0>
LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
801582a: 697b ldr r3, [r7, #20]
801582c: 895b ldrh r3, [r3, #10]
801582e: 461a mov r2, r3
8015830: 897b ldrh r3, [r7, #10]
8015832: 3314 adds r3, #20
8015834: 429a cmp r2, r3
8015836: da06 bge.n 8015846 <tcp_output_alloc_header_common+0x4e>
8015838: 4b26 ldr r3, [pc, #152] ; (80158d4 <tcp_output_alloc_header_common+0xdc>)
801583a: f240 7224 movw r2, #1828 ; 0x724
801583e: 4926 ldr r1, [pc, #152] ; (80158d8 <tcp_output_alloc_header_common+0xe0>)
8015840: 4826 ldr r0, [pc, #152] ; (80158dc <tcp_output_alloc_header_common+0xe4>)
8015842: f005 fbe7 bl 801b014 <iprintf>
(p->len >= TCP_HLEN + optlen));
tcphdr = (struct tcp_hdr *)p->payload;
8015846: 697b ldr r3, [r7, #20]
8015848: 685b ldr r3, [r3, #4]
801584a: 613b str r3, [r7, #16]
tcphdr->src = lwip_htons(src_port);
801584c: 8c3b ldrh r3, [r7, #32]
801584e: 4618 mov r0, r3
8015850: f7f9 fb16 bl 800ee80 <lwip_htons>
8015854: 4603 mov r3, r0
8015856: 461a mov r2, r3
8015858: 693b ldr r3, [r7, #16]
801585a: 801a strh r2, [r3, #0]
tcphdr->dest = lwip_htons(dst_port);
801585c: 8cbb ldrh r3, [r7, #36] ; 0x24
801585e: 4618 mov r0, r3
8015860: f7f9 fb0e bl 800ee80 <lwip_htons>
8015864: 4603 mov r3, r0
8015866: 461a mov r2, r3
8015868: 693b ldr r3, [r7, #16]
801586a: 805a strh r2, [r3, #2]
tcphdr->seqno = seqno_be;
801586c: 693b ldr r3, [r7, #16]
801586e: 687a ldr r2, [r7, #4]
8015870: 605a str r2, [r3, #4]
tcphdr->ackno = lwip_htonl(ackno);
8015872: 68f8 ldr r0, [r7, #12]
8015874: f7f9 fb19 bl 800eeaa <lwip_htonl>
8015878: 4602 mov r2, r0
801587a: 693b ldr r3, [r7, #16]
801587c: 609a str r2, [r3, #8]
TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
801587e: 897b ldrh r3, [r7, #10]
8015880: 089b lsrs r3, r3, #2
8015882: b29b uxth r3, r3
8015884: 3305 adds r3, #5
8015886: b29b uxth r3, r3
8015888: 031b lsls r3, r3, #12
801588a: b29a uxth r2, r3
801588c: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
8015890: b29b uxth r3, r3
8015892: 4313 orrs r3, r2
8015894: b29b uxth r3, r3
8015896: 4618 mov r0, r3
8015898: f7f9 faf2 bl 800ee80 <lwip_htons>
801589c: 4603 mov r3, r0
801589e: 461a mov r2, r3
80158a0: 693b ldr r3, [r7, #16]
80158a2: 819a strh r2, [r3, #12]
tcphdr->wnd = lwip_htons(wnd);
80158a4: 8dbb ldrh r3, [r7, #44] ; 0x2c
80158a6: 4618 mov r0, r3
80158a8: f7f9 faea bl 800ee80 <lwip_htons>
80158ac: 4603 mov r3, r0
80158ae: 461a mov r2, r3
80158b0: 693b ldr r3, [r7, #16]
80158b2: 81da strh r2, [r3, #14]
tcphdr->chksum = 0;
80158b4: 693b ldr r3, [r7, #16]
80158b6: 2200 movs r2, #0
80158b8: 741a strb r2, [r3, #16]
80158ba: 2200 movs r2, #0
80158bc: 745a strb r2, [r3, #17]
tcphdr->urgp = 0;
80158be: 693b ldr r3, [r7, #16]
80158c0: 2200 movs r2, #0
80158c2: 749a strb r2, [r3, #18]
80158c4: 2200 movs r2, #0
80158c6: 74da strb r2, [r3, #19]
}
return p;
80158c8: 697b ldr r3, [r7, #20]
}
80158ca: 4618 mov r0, r3
80158cc: 3718 adds r7, #24
80158ce: 46bd mov sp, r7
80158d0: bd80 pop {r7, pc}
80158d2: bf00 nop
80158d4: 0801d730 .word 0x0801d730
80158d8: 0801de08 .word 0x0801de08
80158dc: 0801d784 .word 0x0801d784
080158e0 <tcp_output_alloc_header>:
* @return pbuf with p->payload being the tcp_hdr
*/
static struct pbuf *
tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */)
{
80158e0: b5b0 push {r4, r5, r7, lr}
80158e2: b08a sub sp, #40 ; 0x28
80158e4: af04 add r7, sp, #16
80158e6: 60f8 str r0, [r7, #12]
80158e8: 607b str r3, [r7, #4]
80158ea: 460b mov r3, r1
80158ec: 817b strh r3, [r7, #10]
80158ee: 4613 mov r3, r2
80158f0: 813b strh r3, [r7, #8]
struct pbuf *p;
LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
80158f2: 68fb ldr r3, [r7, #12]
80158f4: 2b00 cmp r3, #0
80158f6: d106 bne.n 8015906 <tcp_output_alloc_header+0x26>
80158f8: 4b15 ldr r3, [pc, #84] ; (8015950 <tcp_output_alloc_header+0x70>)
80158fa: f240 7242 movw r2, #1858 ; 0x742
80158fe: 4915 ldr r1, [pc, #84] ; (8015954 <tcp_output_alloc_header+0x74>)
8015900: 4815 ldr r0, [pc, #84] ; (8015958 <tcp_output_alloc_header+0x78>)
8015902: f005 fb87 bl 801b014 <iprintf>
p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
8015906: 68fb ldr r3, [r7, #12]
8015908: 6a58 ldr r0, [r3, #36] ; 0x24
801590a: 68fb ldr r3, [r7, #12]
801590c: 8adb ldrh r3, [r3, #22]
801590e: 68fa ldr r2, [r7, #12]
8015910: 8b12 ldrh r2, [r2, #24]
8015912: 68f9 ldr r1, [r7, #12]
8015914: 8d49 ldrh r1, [r1, #42] ; 0x2a
8015916: 893d ldrh r5, [r7, #8]
8015918: 897c ldrh r4, [r7, #10]
801591a: 9103 str r1, [sp, #12]
801591c: 2110 movs r1, #16
801591e: 9102 str r1, [sp, #8]
8015920: 9201 str r2, [sp, #4]
8015922: 9300 str r3, [sp, #0]
8015924: 687b ldr r3, [r7, #4]
8015926: 462a mov r2, r5
8015928: 4621 mov r1, r4
801592a: f7ff ff65 bl 80157f8 <tcp_output_alloc_header_common>
801592e: 6178 str r0, [r7, #20]
seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
if (p != NULL) {
8015930: 697b ldr r3, [r7, #20]
8015932: 2b00 cmp r3, #0
8015934: d006 beq.n 8015944 <tcp_output_alloc_header+0x64>
/* If we're sending a packet, update the announced right window edge */
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
8015936: 68fb ldr r3, [r7, #12]
8015938: 6a5b ldr r3, [r3, #36] ; 0x24
801593a: 68fa ldr r2, [r7, #12]
801593c: 8d52 ldrh r2, [r2, #42] ; 0x2a
801593e: 441a add r2, r3
8015940: 68fb ldr r3, [r7, #12]
8015942: 62da str r2, [r3, #44] ; 0x2c
}
return p;
8015944: 697b ldr r3, [r7, #20]
}
8015946: 4618 mov r0, r3
8015948: 3718 adds r7, #24
801594a: 46bd mov sp, r7
801594c: bdb0 pop {r4, r5, r7, pc}
801594e: bf00 nop
8015950: 0801d730 .word 0x0801d730
8015954: 0801de38 .word 0x0801de38
8015958: 0801d784 .word 0x0801d784
0801595c <tcp_output_fill_options>:
/* Fill in options for control segments */
static void
tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
{
801595c: b580 push {r7, lr}
801595e: b088 sub sp, #32
8015960: af00 add r7, sp, #0
8015962: 60f8 str r0, [r7, #12]
8015964: 60b9 str r1, [r7, #8]
8015966: 4611 mov r1, r2
8015968: 461a mov r2, r3
801596a: 460b mov r3, r1
801596c: 71fb strb r3, [r7, #7]
801596e: 4613 mov r3, r2
8015970: 71bb strb r3, [r7, #6]
struct tcp_hdr *tcphdr;
u32_t *opts;
u16_t sacks_len = 0;
8015972: 2300 movs r3, #0
8015974: 83fb strh r3, [r7, #30]
LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
8015976: 68bb ldr r3, [r7, #8]
8015978: 2b00 cmp r3, #0
801597a: d106 bne.n 801598a <tcp_output_fill_options+0x2e>
801597c: 4b13 ldr r3, [pc, #76] ; (80159cc <tcp_output_fill_options+0x70>)
801597e: f240 7256 movw r2, #1878 ; 0x756
8015982: 4913 ldr r1, [pc, #76] ; (80159d0 <tcp_output_fill_options+0x74>)
8015984: 4813 ldr r0, [pc, #76] ; (80159d4 <tcp_output_fill_options+0x78>)
8015986: f005 fb45 bl 801b014 <iprintf>
tcphdr = (struct tcp_hdr *)p->payload;
801598a: 68bb ldr r3, [r7, #8]
801598c: 685b ldr r3, [r3, #4]
801598e: 61bb str r3, [r7, #24]
opts = (u32_t *)(void *)(tcphdr + 1);
8015990: 69bb ldr r3, [r7, #24]
8015992: 3314 adds r3, #20
8015994: 617b str r3, [r7, #20]
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
#endif
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(sacks_len);
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
8015996: 69bb ldr r3, [r7, #24]
8015998: f103 0214 add.w r2, r3, #20
801599c: 8bfb ldrh r3, [r7, #30]
801599e: 009b lsls r3, r3, #2
80159a0: 4619 mov r1, r3
80159a2: 79fb ldrb r3, [r7, #7]
80159a4: 009b lsls r3, r3, #2
80159a6: f003 0304 and.w r3, r3, #4
80159aa: 440b add r3, r1
80159ac: 4413 add r3, r2
80159ae: 697a ldr r2, [r7, #20]
80159b0: 429a cmp r2, r3
80159b2: d006 beq.n 80159c2 <tcp_output_fill_options+0x66>
80159b4: 4b05 ldr r3, [pc, #20] ; (80159cc <tcp_output_fill_options+0x70>)
80159b6: f240 7275 movw r2, #1909 ; 0x775
80159ba: 4907 ldr r1, [pc, #28] ; (80159d8 <tcp_output_fill_options+0x7c>)
80159bc: 4805 ldr r0, [pc, #20] ; (80159d4 <tcp_output_fill_options+0x78>)
80159be: f005 fb29 bl 801b014 <iprintf>
LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
}
80159c2: bf00 nop
80159c4: 3720 adds r7, #32
80159c6: 46bd mov sp, r7
80159c8: bd80 pop {r7, pc}
80159ca: bf00 nop
80159cc: 0801d730 .word 0x0801d730
80159d0: 0801de60 .word 0x0801de60
80159d4: 0801d784 .word 0x0801d784
80159d8: 0801dd58 .word 0x0801dd58
080159dc <tcp_output_control_segment>:
* header checksum and calling ip_output_if while handling netif hints and stats.
*/
static err_t
tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
const ip_addr_t *src, const ip_addr_t *dst)
{
80159dc: b580 push {r7, lr}
80159de: b08a sub sp, #40 ; 0x28
80159e0: af04 add r7, sp, #16
80159e2: 60f8 str r0, [r7, #12]
80159e4: 60b9 str r1, [r7, #8]
80159e6: 607a str r2, [r7, #4]
80159e8: 603b str r3, [r7, #0]
err_t err;
struct netif *netif;
LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
80159ea: 68bb ldr r3, [r7, #8]
80159ec: 2b00 cmp r3, #0
80159ee: d106 bne.n 80159fe <tcp_output_control_segment+0x22>
80159f0: 4b1c ldr r3, [pc, #112] ; (8015a64 <tcp_output_control_segment+0x88>)
80159f2: f240 7287 movw r2, #1927 ; 0x787
80159f6: 491c ldr r1, [pc, #112] ; (8015a68 <tcp_output_control_segment+0x8c>)
80159f8: 481c ldr r0, [pc, #112] ; (8015a6c <tcp_output_control_segment+0x90>)
80159fa: f005 fb0b bl 801b014 <iprintf>
netif = tcp_route(pcb, src, dst);
80159fe: 683a ldr r2, [r7, #0]
8015a00: 6879 ldr r1, [r7, #4]
8015a02: 68f8 ldr r0, [r7, #12]
8015a04: f7fe ff2e bl 8014864 <tcp_route>
8015a08: 6138 str r0, [r7, #16]
if (netif == NULL) {
8015a0a: 693b ldr r3, [r7, #16]
8015a0c: 2b00 cmp r3, #0
8015a0e: d102 bne.n 8015a16 <tcp_output_control_segment+0x3a>
err = ERR_RTE;
8015a10: 23fc movs r3, #252 ; 0xfc
8015a12: 75fb strb r3, [r7, #23]
8015a14: e01c b.n 8015a50 <tcp_output_control_segment+0x74>
struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
src, dst);
}
#endif
if (pcb != NULL) {
8015a16: 68fb ldr r3, [r7, #12]
8015a18: 2b00 cmp r3, #0
8015a1a: d006 beq.n 8015a2a <tcp_output_control_segment+0x4e>
NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
ttl = pcb->ttl;
8015a1c: 68fb ldr r3, [r7, #12]
8015a1e: 7adb ldrb r3, [r3, #11]
8015a20: 75bb strb r3, [r7, #22]
tos = pcb->tos;
8015a22: 68fb ldr r3, [r7, #12]
8015a24: 7a9b ldrb r3, [r3, #10]
8015a26: 757b strb r3, [r7, #21]
8015a28: e003 b.n 8015a32 <tcp_output_control_segment+0x56>
} else {
/* Send output with hardcoded TTL/HL since we have no access to the pcb */
ttl = TCP_TTL;
8015a2a: 23ff movs r3, #255 ; 0xff
8015a2c: 75bb strb r3, [r7, #22]
tos = 0;
8015a2e: 2300 movs r3, #0
8015a30: 757b strb r3, [r7, #21]
}
TCP_STATS_INC(tcp.xmit);
err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
8015a32: 7dba ldrb r2, [r7, #22]
8015a34: 693b ldr r3, [r7, #16]
8015a36: 9302 str r3, [sp, #8]
8015a38: 2306 movs r3, #6
8015a3a: 9301 str r3, [sp, #4]
8015a3c: 7d7b ldrb r3, [r7, #21]
8015a3e: 9300 str r3, [sp, #0]
8015a40: 4613 mov r3, r2
8015a42: 683a ldr r2, [r7, #0]
8015a44: 6879 ldr r1, [r7, #4]
8015a46: 68b8 ldr r0, [r7, #8]
8015a48: f004 f964 bl 8019d14 <ip4_output_if>
8015a4c: 4603 mov r3, r0
8015a4e: 75fb strb r3, [r7, #23]
NETIF_RESET_HINTS(netif);
}
pbuf_free(p);
8015a50: 68b8 ldr r0, [r7, #8]
8015a52: f7fa fdc9 bl 80105e8 <pbuf_free>
return err;
8015a56: f997 3017 ldrsb.w r3, [r7, #23]
}
8015a5a: 4618 mov r0, r3
8015a5c: 3718 adds r7, #24
8015a5e: 46bd mov sp, r7
8015a60: bd80 pop {r7, pc}
8015a62: bf00 nop
8015a64: 0801d730 .word 0x0801d730
8015a68: 0801de88 .word 0x0801de88
8015a6c: 0801d784 .word 0x0801d784
08015a70 <tcp_rst>:
*/
void
tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
u16_t local_port, u16_t remote_port)
{
8015a70: b590 push {r4, r7, lr}
8015a72: b08b sub sp, #44 ; 0x2c
8015a74: af04 add r7, sp, #16
8015a76: 60f8 str r0, [r7, #12]
8015a78: 60b9 str r1, [r7, #8]
8015a7a: 607a str r2, [r7, #4]
8015a7c: 603b str r3, [r7, #0]
struct pbuf *p;
u16_t wnd;
u8_t optlen;
LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
8015a7e: 683b ldr r3, [r7, #0]
8015a80: 2b00 cmp r3, #0
8015a82: d106 bne.n 8015a92 <tcp_rst+0x22>
8015a84: 4b1f ldr r3, [pc, #124] ; (8015b04 <tcp_rst+0x94>)
8015a86: f240 72c4 movw r2, #1988 ; 0x7c4
8015a8a: 491f ldr r1, [pc, #124] ; (8015b08 <tcp_rst+0x98>)
8015a8c: 481f ldr r0, [pc, #124] ; (8015b0c <tcp_rst+0x9c>)
8015a8e: f005 fac1 bl 801b014 <iprintf>
LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
8015a92: 6abb ldr r3, [r7, #40] ; 0x28
8015a94: 2b00 cmp r3, #0
8015a96: d106 bne.n 8015aa6 <tcp_rst+0x36>
8015a98: 4b1a ldr r3, [pc, #104] ; (8015b04 <tcp_rst+0x94>)
8015a9a: f240 72c5 movw r2, #1989 ; 0x7c5
8015a9e: 491c ldr r1, [pc, #112] ; (8015b10 <tcp_rst+0xa0>)
8015aa0: 481a ldr r0, [pc, #104] ; (8015b0c <tcp_rst+0x9c>)
8015aa2: f005 fab7 bl 801b014 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015aa6: 2300 movs r3, #0
8015aa8: 75fb strb r3, [r7, #23]
#if LWIP_WND_SCALE
wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
#else
wnd = PP_HTONS(TCP_WND);
8015aaa: f246 0308 movw r3, #24584 ; 0x6008
8015aae: 82bb strh r3, [r7, #20]
#endif
p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
8015ab0: 7dfb ldrb r3, [r7, #23]
8015ab2: b29c uxth r4, r3
8015ab4: 68b8 ldr r0, [r7, #8]
8015ab6: f7f9 f9f8 bl 800eeaa <lwip_htonl>
8015aba: 4602 mov r2, r0
8015abc: 8abb ldrh r3, [r7, #20]
8015abe: 9303 str r3, [sp, #12]
8015ac0: 2314 movs r3, #20
8015ac2: 9302 str r3, [sp, #8]
8015ac4: 8e3b ldrh r3, [r7, #48] ; 0x30
8015ac6: 9301 str r3, [sp, #4]
8015ac8: 8dbb ldrh r3, [r7, #44] ; 0x2c
8015aca: 9300 str r3, [sp, #0]
8015acc: 4613 mov r3, r2
8015ace: 2200 movs r2, #0
8015ad0: 4621 mov r1, r4
8015ad2: 6878 ldr r0, [r7, #4]
8015ad4: f7ff fe90 bl 80157f8 <tcp_output_alloc_header_common>
8015ad8: 6138 str r0, [r7, #16]
remote_port, TCP_RST | TCP_ACK, wnd);
if (p == NULL) {
8015ada: 693b ldr r3, [r7, #16]
8015adc: 2b00 cmp r3, #0
8015ade: d00c beq.n 8015afa <tcp_rst+0x8a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
return;
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015ae0: 7dfb ldrb r3, [r7, #23]
8015ae2: 2200 movs r2, #0
8015ae4: 6939 ldr r1, [r7, #16]
8015ae6: 68f8 ldr r0, [r7, #12]
8015ae8: f7ff ff38 bl 801595c <tcp_output_fill_options>
MIB2_STATS_INC(mib2.tcpoutrsts);
tcp_output_control_segment(pcb, p, local_ip, remote_ip);
8015aec: 6abb ldr r3, [r7, #40] ; 0x28
8015aee: 683a ldr r2, [r7, #0]
8015af0: 6939 ldr r1, [r7, #16]
8015af2: 68f8 ldr r0, [r7, #12]
8015af4: f7ff ff72 bl 80159dc <tcp_output_control_segment>
8015af8: e000 b.n 8015afc <tcp_rst+0x8c>
return;
8015afa: bf00 nop
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
}
8015afc: 371c adds r7, #28
8015afe: 46bd mov sp, r7
8015b00: bd90 pop {r4, r7, pc}
8015b02: bf00 nop
8015b04: 0801d730 .word 0x0801d730
8015b08: 0801deb4 .word 0x0801deb4
8015b0c: 0801d784 .word 0x0801d784
8015b10: 0801ded0 .word 0x0801ded0
08015b14 <tcp_send_empty_ack>:
*
* @param pcb Protocol control block for the TCP connection to send the ACK
*/
err_t
tcp_send_empty_ack(struct tcp_pcb *pcb)
{
8015b14: b590 push {r4, r7, lr}
8015b16: b087 sub sp, #28
8015b18: af00 add r7, sp, #0
8015b1a: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen, optflags = 0;
8015b1c: 2300 movs r3, #0
8015b1e: 75fb strb r3, [r7, #23]
u8_t num_sacks = 0;
8015b20: 2300 movs r3, #0
8015b22: 75bb strb r3, [r7, #22]
LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
8015b24: 687b ldr r3, [r7, #4]
8015b26: 2b00 cmp r3, #0
8015b28: d106 bne.n 8015b38 <tcp_send_empty_ack+0x24>
8015b2a: 4b28 ldr r3, [pc, #160] ; (8015bcc <tcp_send_empty_ack+0xb8>)
8015b2c: f240 72ea movw r2, #2026 ; 0x7ea
8015b30: 4927 ldr r1, [pc, #156] ; (8015bd0 <tcp_send_empty_ack+0xbc>)
8015b32: 4828 ldr r0, [pc, #160] ; (8015bd4 <tcp_send_empty_ack+0xc0>)
8015b34: f005 fa6e bl 801b014 <iprintf>
#if LWIP_TCP_TIMESTAMPS
if (pcb->flags & TF_TIMESTAMP) {
optflags = TF_SEG_OPTS_TS;
}
#endif
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8015b38: 7dfb ldrb r3, [r7, #23]
8015b3a: 009b lsls r3, r3, #2
8015b3c: b2db uxtb r3, r3
8015b3e: f003 0304 and.w r3, r3, #4
8015b42: 757b strb r3, [r7, #21]
if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
}
#endif
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
8015b44: 7d7b ldrb r3, [r7, #21]
8015b46: b29c uxth r4, r3
8015b48: 687b ldr r3, [r7, #4]
8015b4a: 6d1b ldr r3, [r3, #80] ; 0x50
8015b4c: 4618 mov r0, r3
8015b4e: f7f9 f9ac bl 800eeaa <lwip_htonl>
8015b52: 4603 mov r3, r0
8015b54: 2200 movs r2, #0
8015b56: 4621 mov r1, r4
8015b58: 6878 ldr r0, [r7, #4]
8015b5a: f7ff fec1 bl 80158e0 <tcp_output_alloc_header>
8015b5e: 6138 str r0, [r7, #16]
if (p == NULL) {
8015b60: 693b ldr r3, [r7, #16]
8015b62: 2b00 cmp r3, #0
8015b64: d109 bne.n 8015b7a <tcp_send_empty_ack+0x66>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015b66: 687b ldr r3, [r7, #4]
8015b68: 8b5b ldrh r3, [r3, #26]
8015b6a: f043 0303 orr.w r3, r3, #3
8015b6e: b29a uxth r2, r3
8015b70: 687b ldr r3, [r7, #4]
8015b72: 835a strh r2, [r3, #26]
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
return ERR_BUF;
8015b74: f06f 0301 mvn.w r3, #1
8015b78: e023 b.n 8015bc2 <tcp_send_empty_ack+0xae>
}
tcp_output_fill_options(pcb, p, optflags, num_sacks);
8015b7a: 7dbb ldrb r3, [r7, #22]
8015b7c: 7dfa ldrb r2, [r7, #23]
8015b7e: 6939 ldr r1, [r7, #16]
8015b80: 6878 ldr r0, [r7, #4]
8015b82: f7ff feeb bl 801595c <tcp_output_fill_options>
pcb->ts_lastacksent = pcb->rcv_nxt;
#endif
LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015b86: 687a ldr r2, [r7, #4]
8015b88: 687b ldr r3, [r7, #4]
8015b8a: 3304 adds r3, #4
8015b8c: 6939 ldr r1, [r7, #16]
8015b8e: 6878 ldr r0, [r7, #4]
8015b90: f7ff ff24 bl 80159dc <tcp_output_control_segment>
8015b94: 4603 mov r3, r0
8015b96: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
8015b98: f997 300f ldrsb.w r3, [r7, #15]
8015b9c: 2b00 cmp r3, #0
8015b9e: d007 beq.n 8015bb0 <tcp_send_empty_ack+0x9c>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015ba0: 687b ldr r3, [r7, #4]
8015ba2: 8b5b ldrh r3, [r3, #26]
8015ba4: f043 0303 orr.w r3, r3, #3
8015ba8: b29a uxth r2, r3
8015baa: 687b ldr r3, [r7, #4]
8015bac: 835a strh r2, [r3, #26]
8015bae: e006 b.n 8015bbe <tcp_send_empty_ack+0xaa>
} else {
/* remove ACK flags from the PCB, as we sent an empty ACK now */
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015bb0: 687b ldr r3, [r7, #4]
8015bb2: 8b5b ldrh r3, [r3, #26]
8015bb4: f023 0303 bic.w r3, r3, #3
8015bb8: b29a uxth r2, r3
8015bba: 687b ldr r3, [r7, #4]
8015bbc: 835a strh r2, [r3, #26]
}
return err;
8015bbe: f997 300f ldrsb.w r3, [r7, #15]
}
8015bc2: 4618 mov r0, r3
8015bc4: 371c adds r7, #28
8015bc6: 46bd mov sp, r7
8015bc8: bd90 pop {r4, r7, pc}
8015bca: bf00 nop
8015bcc: 0801d730 .word 0x0801d730
8015bd0: 0801deec .word 0x0801deec
8015bd4: 0801d784 .word 0x0801d784
08015bd8 <tcp_keepalive>:
*
* @param pcb the tcp_pcb for which to send a keepalive packet
*/
err_t
tcp_keepalive(struct tcp_pcb *pcb)
{
8015bd8: b590 push {r4, r7, lr}
8015bda: b087 sub sp, #28
8015bdc: af00 add r7, sp, #0
8015bde: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015be0: 2300 movs r3, #0
8015be2: 75fb strb r3, [r7, #23]
LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
8015be4: 687b ldr r3, [r7, #4]
8015be6: 2b00 cmp r3, #0
8015be8: d106 bne.n 8015bf8 <tcp_keepalive+0x20>
8015bea: 4b18 ldr r3, [pc, #96] ; (8015c4c <tcp_keepalive+0x74>)
8015bec: f640 0224 movw r2, #2084 ; 0x824
8015bf0: 4917 ldr r1, [pc, #92] ; (8015c50 <tcp_keepalive+0x78>)
8015bf2: 4818 ldr r0, [pc, #96] ; (8015c54 <tcp_keepalive+0x7c>)
8015bf4: f005 fa0e bl 801b014 <iprintf>
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
8015bf8: 7dfb ldrb r3, [r7, #23]
8015bfa: b29c uxth r4, r3
8015bfc: 687b ldr r3, [r7, #4]
8015bfe: 6d1b ldr r3, [r3, #80] ; 0x50
8015c00: 3b01 subs r3, #1
8015c02: 4618 mov r0, r3
8015c04: f7f9 f951 bl 800eeaa <lwip_htonl>
8015c08: 4603 mov r3, r0
8015c0a: 2200 movs r2, #0
8015c0c: 4621 mov r1, r4
8015c0e: 6878 ldr r0, [r7, #4]
8015c10: f7ff fe66 bl 80158e0 <tcp_output_alloc_header>
8015c14: 6138 str r0, [r7, #16]
if (p == NULL) {
8015c16: 693b ldr r3, [r7, #16]
8015c18: 2b00 cmp r3, #0
8015c1a: d102 bne.n 8015c22 <tcp_keepalive+0x4a>
LWIP_DEBUGF(TCP_DEBUG,
("tcp_keepalive: could not allocate memory for pbuf\n"));
return ERR_MEM;
8015c1c: f04f 33ff mov.w r3, #4294967295
8015c20: e010 b.n 8015c44 <tcp_keepalive+0x6c>
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015c22: 7dfb ldrb r3, [r7, #23]
8015c24: 2200 movs r2, #0
8015c26: 6939 ldr r1, [r7, #16]
8015c28: 6878 ldr r0, [r7, #4]
8015c2a: f7ff fe97 bl 801595c <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015c2e: 687a ldr r2, [r7, #4]
8015c30: 687b ldr r3, [r7, #4]
8015c32: 3304 adds r3, #4
8015c34: 6939 ldr r1, [r7, #16]
8015c36: 6878 ldr r0, [r7, #4]
8015c38: f7ff fed0 bl 80159dc <tcp_output_control_segment>
8015c3c: 4603 mov r3, r0
8015c3e: 73fb strb r3, [r7, #15]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015c40: f997 300f ldrsb.w r3, [r7, #15]
}
8015c44: 4618 mov r0, r3
8015c46: 371c adds r7, #28
8015c48: 46bd mov sp, r7
8015c4a: bd90 pop {r4, r7, pc}
8015c4c: 0801d730 .word 0x0801d730
8015c50: 0801df0c .word 0x0801df0c
8015c54: 0801d784 .word 0x0801d784
08015c58 <tcp_zero_window_probe>:
*
* @param pcb the tcp_pcb for which to send a zero-window probe packet
*/
err_t
tcp_zero_window_probe(struct tcp_pcb *pcb)
{
8015c58: b590 push {r4, r7, lr}
8015c5a: b08b sub sp, #44 ; 0x2c
8015c5c: af00 add r7, sp, #0
8015c5e: 6078 str r0, [r7, #4]
struct tcp_hdr *tcphdr;
struct tcp_seg *seg;
u16_t len;
u8_t is_fin;
u32_t snd_nxt;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015c60: 2300 movs r3, #0
8015c62: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
8015c66: 687b ldr r3, [r7, #4]
8015c68: 2b00 cmp r3, #0
8015c6a: d106 bne.n 8015c7a <tcp_zero_window_probe+0x22>
8015c6c: 4b4c ldr r3, [pc, #304] ; (8015da0 <tcp_zero_window_probe+0x148>)
8015c6e: f640 024f movw r2, #2127 ; 0x84f
8015c72: 494c ldr r1, [pc, #304] ; (8015da4 <tcp_zero_window_probe+0x14c>)
8015c74: 484c ldr r0, [pc, #304] ; (8015da8 <tcp_zero_window_probe+0x150>)
8015c76: f005 f9cd bl 801b014 <iprintf>
("tcp_zero_window_probe: tcp_ticks %"U32_F
" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
/* Only consider unsent, persist timer should be off when there is data in-flight */
seg = pcb->unsent;
8015c7a: 687b ldr r3, [r7, #4]
8015c7c: 6edb ldr r3, [r3, #108] ; 0x6c
8015c7e: 623b str r3, [r7, #32]
if (seg == NULL) {
8015c80: 6a3b ldr r3, [r7, #32]
8015c82: 2b00 cmp r3, #0
8015c84: d101 bne.n 8015c8a <tcp_zero_window_probe+0x32>
/* Not expected, persist timer should be off when the send buffer is empty */
return ERR_OK;
8015c86: 2300 movs r3, #0
8015c88: e086 b.n 8015d98 <tcp_zero_window_probe+0x140>
/* increment probe count. NOTE: we record probe even if it fails
to actually transmit due to an error. This ensures memory exhaustion/
routing problem doesn't leave a zero-window pcb as an indefinite zombie.
RTO mechanism has similar behavior, see pcb->nrtx */
if (pcb->persist_probe < 0xFF) {
8015c8a: 687b ldr r3, [r7, #4]
8015c8c: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015c90: 2bff cmp r3, #255 ; 0xff
8015c92: d007 beq.n 8015ca4 <tcp_zero_window_probe+0x4c>
++pcb->persist_probe;
8015c94: 687b ldr r3, [r7, #4]
8015c96: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015c9a: 3301 adds r3, #1
8015c9c: b2da uxtb r2, r3
8015c9e: 687b ldr r3, [r7, #4]
8015ca0: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
8015ca4: 6a3b ldr r3, [r7, #32]
8015ca6: 68db ldr r3, [r3, #12]
8015ca8: 899b ldrh r3, [r3, #12]
8015caa: b29b uxth r3, r3
8015cac: 4618 mov r0, r3
8015cae: f7f9 f8e7 bl 800ee80 <lwip_htons>
8015cb2: 4603 mov r3, r0
8015cb4: b2db uxtb r3, r3
8015cb6: f003 0301 and.w r3, r3, #1
8015cba: 2b00 cmp r3, #0
8015cbc: d005 beq.n 8015cca <tcp_zero_window_probe+0x72>
8015cbe: 6a3b ldr r3, [r7, #32]
8015cc0: 891b ldrh r3, [r3, #8]
8015cc2: 2b00 cmp r3, #0
8015cc4: d101 bne.n 8015cca <tcp_zero_window_probe+0x72>
8015cc6: 2301 movs r3, #1
8015cc8: e000 b.n 8015ccc <tcp_zero_window_probe+0x74>
8015cca: 2300 movs r3, #0
8015ccc: 77fb strb r3, [r7, #31]
/* we want to send one seqno: either FIN or data (no options) */
len = is_fin ? 0 : 1;
8015cce: 7ffb ldrb r3, [r7, #31]
8015cd0: 2b00 cmp r3, #0
8015cd2: bf0c ite eq
8015cd4: 2301 moveq r3, #1
8015cd6: 2300 movne r3, #0
8015cd8: b2db uxtb r3, r3
8015cda: 83bb strh r3, [r7, #28]
p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
8015cdc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015ce0: b299 uxth r1, r3
8015ce2: 6a3b ldr r3, [r7, #32]
8015ce4: 68db ldr r3, [r3, #12]
8015ce6: 685b ldr r3, [r3, #4]
8015ce8: 8bba ldrh r2, [r7, #28]
8015cea: 6878 ldr r0, [r7, #4]
8015cec: f7ff fdf8 bl 80158e0 <tcp_output_alloc_header>
8015cf0: 61b8 str r0, [r7, #24]
if (p == NULL) {
8015cf2: 69bb ldr r3, [r7, #24]
8015cf4: 2b00 cmp r3, #0
8015cf6: d102 bne.n 8015cfe <tcp_zero_window_probe+0xa6>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
return ERR_MEM;
8015cf8: f04f 33ff mov.w r3, #4294967295
8015cfc: e04c b.n 8015d98 <tcp_zero_window_probe+0x140>
}
tcphdr = (struct tcp_hdr *)p->payload;
8015cfe: 69bb ldr r3, [r7, #24]
8015d00: 685b ldr r3, [r3, #4]
8015d02: 617b str r3, [r7, #20]
if (is_fin) {
8015d04: 7ffb ldrb r3, [r7, #31]
8015d06: 2b00 cmp r3, #0
8015d08: d011 beq.n 8015d2e <tcp_zero_window_probe+0xd6>
/* FIN segment, no data */
TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
8015d0a: 697b ldr r3, [r7, #20]
8015d0c: 899b ldrh r3, [r3, #12]
8015d0e: b29b uxth r3, r3
8015d10: b21b sxth r3, r3
8015d12: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8015d16: b21c sxth r4, r3
8015d18: 2011 movs r0, #17
8015d1a: f7f9 f8b1 bl 800ee80 <lwip_htons>
8015d1e: 4603 mov r3, r0
8015d20: b21b sxth r3, r3
8015d22: 4323 orrs r3, r4
8015d24: b21b sxth r3, r3
8015d26: b29a uxth r2, r3
8015d28: 697b ldr r3, [r7, #20]
8015d2a: 819a strh r2, [r3, #12]
8015d2c: e010 b.n 8015d50 <tcp_zero_window_probe+0xf8>
} else {
/* Data segment, copy in one byte from the head of the unacked queue */
char *d = ((char *)p->payload + TCP_HLEN);
8015d2e: 69bb ldr r3, [r7, #24]
8015d30: 685b ldr r3, [r3, #4]
8015d32: 3314 adds r3, #20
8015d34: 613b str r3, [r7, #16]
/* Depending on whether the segment has already been sent (unacked) or not
(unsent), seg->p->payload points to the IP header or TCP header.
Ensure we copy the first TCP data byte: */
pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
8015d36: 6a3b ldr r3, [r7, #32]
8015d38: 6858 ldr r0, [r3, #4]
8015d3a: 6a3b ldr r3, [r7, #32]
8015d3c: 685b ldr r3, [r3, #4]
8015d3e: 891a ldrh r2, [r3, #8]
8015d40: 6a3b ldr r3, [r7, #32]
8015d42: 891b ldrh r3, [r3, #8]
8015d44: 1ad3 subs r3, r2, r3
8015d46: b29b uxth r3, r3
8015d48: 2201 movs r2, #1
8015d4a: 6939 ldr r1, [r7, #16]
8015d4c: f7fa fe52 bl 80109f4 <pbuf_copy_partial>
}
/* The byte may be acknowledged without the window being opened. */
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
8015d50: 6a3b ldr r3, [r7, #32]
8015d52: 68db ldr r3, [r3, #12]
8015d54: 685b ldr r3, [r3, #4]
8015d56: 4618 mov r0, r3
8015d58: f7f9 f8a7 bl 800eeaa <lwip_htonl>
8015d5c: 4603 mov r3, r0
8015d5e: 3301 adds r3, #1
8015d60: 60fb str r3, [r7, #12]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
8015d62: 687b ldr r3, [r7, #4]
8015d64: 6d1a ldr r2, [r3, #80] ; 0x50
8015d66: 68fb ldr r3, [r7, #12]
8015d68: 1ad3 subs r3, r2, r3
8015d6a: 2b00 cmp r3, #0
8015d6c: da02 bge.n 8015d74 <tcp_zero_window_probe+0x11c>
pcb->snd_nxt = snd_nxt;
8015d6e: 687b ldr r3, [r7, #4]
8015d70: 68fa ldr r2, [r7, #12]
8015d72: 651a str r2, [r3, #80] ; 0x50
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015d74: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015d78: 2200 movs r2, #0
8015d7a: 69b9 ldr r1, [r7, #24]
8015d7c: 6878 ldr r0, [r7, #4]
8015d7e: f7ff fded bl 801595c <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015d82: 687a ldr r2, [r7, #4]
8015d84: 687b ldr r3, [r7, #4]
8015d86: 3304 adds r3, #4
8015d88: 69b9 ldr r1, [r7, #24]
8015d8a: 6878 ldr r0, [r7, #4]
8015d8c: f7ff fe26 bl 80159dc <tcp_output_control_segment>
8015d90: 4603 mov r3, r0
8015d92: 72fb strb r3, [r7, #11]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015d94: f997 300b ldrsb.w r3, [r7, #11]
}
8015d98: 4618 mov r0, r3
8015d9a: 372c adds r7, #44 ; 0x2c
8015d9c: 46bd mov sp, r7
8015d9e: bd90 pop {r4, r7, pc}
8015da0: 0801d730 .word 0x0801d730
8015da4: 0801df28 .word 0x0801df28
8015da8: 0801d784 .word 0x0801d784
08015dac <tcpip_tcp_timer>:
*
* @param arg unused argument
*/
static void
tcpip_tcp_timer(void *arg)
{
8015dac: b580 push {r7, lr}
8015dae: b082 sub sp, #8
8015db0: af00 add r7, sp, #0
8015db2: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
/* call TCP timer handler */
tcp_tmr();
8015db4: f7fa ff0c bl 8010bd0 <tcp_tmr>
/* timer still needed? */
if (tcp_active_pcbs || tcp_tw_pcbs) {
8015db8: 4b0a ldr r3, [pc, #40] ; (8015de4 <tcpip_tcp_timer+0x38>)
8015dba: 681b ldr r3, [r3, #0]
8015dbc: 2b00 cmp r3, #0
8015dbe: d103 bne.n 8015dc8 <tcpip_tcp_timer+0x1c>
8015dc0: 4b09 ldr r3, [pc, #36] ; (8015de8 <tcpip_tcp_timer+0x3c>)
8015dc2: 681b ldr r3, [r3, #0]
8015dc4: 2b00 cmp r3, #0
8015dc6: d005 beq.n 8015dd4 <tcpip_tcp_timer+0x28>
/* restart timer */
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015dc8: 2200 movs r2, #0
8015dca: 4908 ldr r1, [pc, #32] ; (8015dec <tcpip_tcp_timer+0x40>)
8015dcc: 20fa movs r0, #250 ; 0xfa
8015dce: f000 f8f1 bl 8015fb4 <sys_timeout>
8015dd2: e002 b.n 8015dda <tcpip_tcp_timer+0x2e>
} else {
/* disable timer */
tcpip_tcp_timer_active = 0;
8015dd4: 4b06 ldr r3, [pc, #24] ; (8015df0 <tcpip_tcp_timer+0x44>)
8015dd6: 2200 movs r2, #0
8015dd8: 601a str r2, [r3, #0]
}
}
8015dda: bf00 nop
8015ddc: 3708 adds r7, #8
8015dde: 46bd mov sp, r7
8015de0: bd80 pop {r7, pc}
8015de2: bf00 nop
8015de4: 2000f5c0 .word 0x2000f5c0
8015de8: 2000f5d0 .word 0x2000f5d0
8015dec: 08015dad .word 0x08015dad
8015df0: 20008768 .word 0x20008768
08015df4 <tcp_timer_needed>:
* the reason is to have the TCP timer only running when
* there are active (or time-wait) PCBs.
*/
void
tcp_timer_needed(void)
{
8015df4: b580 push {r7, lr}
8015df6: af00 add r7, sp, #0
LWIP_ASSERT_CORE_LOCKED();
/* timer is off but needed again? */
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
8015df8: 4b0a ldr r3, [pc, #40] ; (8015e24 <tcp_timer_needed+0x30>)
8015dfa: 681b ldr r3, [r3, #0]
8015dfc: 2b00 cmp r3, #0
8015dfe: d10f bne.n 8015e20 <tcp_timer_needed+0x2c>
8015e00: 4b09 ldr r3, [pc, #36] ; (8015e28 <tcp_timer_needed+0x34>)
8015e02: 681b ldr r3, [r3, #0]
8015e04: 2b00 cmp r3, #0
8015e06: d103 bne.n 8015e10 <tcp_timer_needed+0x1c>
8015e08: 4b08 ldr r3, [pc, #32] ; (8015e2c <tcp_timer_needed+0x38>)
8015e0a: 681b ldr r3, [r3, #0]
8015e0c: 2b00 cmp r3, #0
8015e0e: d007 beq.n 8015e20 <tcp_timer_needed+0x2c>
/* enable and start timer */
tcpip_tcp_timer_active = 1;
8015e10: 4b04 ldr r3, [pc, #16] ; (8015e24 <tcp_timer_needed+0x30>)
8015e12: 2201 movs r2, #1
8015e14: 601a str r2, [r3, #0]
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015e16: 2200 movs r2, #0
8015e18: 4905 ldr r1, [pc, #20] ; (8015e30 <tcp_timer_needed+0x3c>)
8015e1a: 20fa movs r0, #250 ; 0xfa
8015e1c: f000 f8ca bl 8015fb4 <sys_timeout>
}
}
8015e20: bf00 nop
8015e22: bd80 pop {r7, pc}
8015e24: 20008768 .word 0x20008768
8015e28: 2000f5c0 .word 0x2000f5c0
8015e2c: 2000f5d0 .word 0x2000f5d0
8015e30: 08015dad .word 0x08015dad
08015e34 <sys_timeout_abs>:
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
#endif
{
8015e34: b580 push {r7, lr}
8015e36: b086 sub sp, #24
8015e38: af00 add r7, sp, #0
8015e3a: 60f8 str r0, [r7, #12]
8015e3c: 60b9 str r1, [r7, #8]
8015e3e: 607a str r2, [r7, #4]
struct sys_timeo *timeout, *t;
timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
8015e40: 200a movs r0, #10
8015e42: f7f9 fcd3 bl 800f7ec <memp_malloc>
8015e46: 6138 str r0, [r7, #16]
if (timeout == NULL) {
8015e48: 693b ldr r3, [r7, #16]
8015e4a: 2b00 cmp r3, #0
8015e4c: d109 bne.n 8015e62 <sys_timeout_abs+0x2e>
LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
8015e4e: 693b ldr r3, [r7, #16]
8015e50: 2b00 cmp r3, #0
8015e52: d151 bne.n 8015ef8 <sys_timeout_abs+0xc4>
8015e54: 4b2a ldr r3, [pc, #168] ; (8015f00 <sys_timeout_abs+0xcc>)
8015e56: 22be movs r2, #190 ; 0xbe
8015e58: 492a ldr r1, [pc, #168] ; (8015f04 <sys_timeout_abs+0xd0>)
8015e5a: 482b ldr r0, [pc, #172] ; (8015f08 <sys_timeout_abs+0xd4>)
8015e5c: f005 f8da bl 801b014 <iprintf>
return;
8015e60: e04a b.n 8015ef8 <sys_timeout_abs+0xc4>
}
timeout->next = NULL;
8015e62: 693b ldr r3, [r7, #16]
8015e64: 2200 movs r2, #0
8015e66: 601a str r2, [r3, #0]
timeout->h = handler;
8015e68: 693b ldr r3, [r7, #16]
8015e6a: 68ba ldr r2, [r7, #8]
8015e6c: 609a str r2, [r3, #8]
timeout->arg = arg;
8015e6e: 693b ldr r3, [r7, #16]
8015e70: 687a ldr r2, [r7, #4]
8015e72: 60da str r2, [r3, #12]
timeout->time = abs_time;
8015e74: 693b ldr r3, [r7, #16]
8015e76: 68fa ldr r2, [r7, #12]
8015e78: 605a str r2, [r3, #4]
timeout->handler_name = handler_name;
LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
(void *)timeout, abs_time, handler_name, (void *)arg));
#endif /* LWIP_DEBUG_TIMERNAMES */
if (next_timeout == NULL) {
8015e7a: 4b24 ldr r3, [pc, #144] ; (8015f0c <sys_timeout_abs+0xd8>)
8015e7c: 681b ldr r3, [r3, #0]
8015e7e: 2b00 cmp r3, #0
8015e80: d103 bne.n 8015e8a <sys_timeout_abs+0x56>
next_timeout = timeout;
8015e82: 4a22 ldr r2, [pc, #136] ; (8015f0c <sys_timeout_abs+0xd8>)
8015e84: 693b ldr r3, [r7, #16]
8015e86: 6013 str r3, [r2, #0]
return;
8015e88: e037 b.n 8015efa <sys_timeout_abs+0xc6>
}
if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
8015e8a: 693b ldr r3, [r7, #16]
8015e8c: 685a ldr r2, [r3, #4]
8015e8e: 4b1f ldr r3, [pc, #124] ; (8015f0c <sys_timeout_abs+0xd8>)
8015e90: 681b ldr r3, [r3, #0]
8015e92: 685b ldr r3, [r3, #4]
8015e94: 1ad3 subs r3, r2, r3
8015e96: 0fdb lsrs r3, r3, #31
8015e98: f003 0301 and.w r3, r3, #1
8015e9c: b2db uxtb r3, r3
8015e9e: 2b00 cmp r3, #0
8015ea0: d007 beq.n 8015eb2 <sys_timeout_abs+0x7e>
timeout->next = next_timeout;
8015ea2: 4b1a ldr r3, [pc, #104] ; (8015f0c <sys_timeout_abs+0xd8>)
8015ea4: 681a ldr r2, [r3, #0]
8015ea6: 693b ldr r3, [r7, #16]
8015ea8: 601a str r2, [r3, #0]
next_timeout = timeout;
8015eaa: 4a18 ldr r2, [pc, #96] ; (8015f0c <sys_timeout_abs+0xd8>)
8015eac: 693b ldr r3, [r7, #16]
8015eae: 6013 str r3, [r2, #0]
8015eb0: e023 b.n 8015efa <sys_timeout_abs+0xc6>
} else {
for (t = next_timeout; t != NULL; t = t->next) {
8015eb2: 4b16 ldr r3, [pc, #88] ; (8015f0c <sys_timeout_abs+0xd8>)
8015eb4: 681b ldr r3, [r3, #0]
8015eb6: 617b str r3, [r7, #20]
8015eb8: e01a b.n 8015ef0 <sys_timeout_abs+0xbc>
if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
8015eba: 697b ldr r3, [r7, #20]
8015ebc: 681b ldr r3, [r3, #0]
8015ebe: 2b00 cmp r3, #0
8015ec0: d00b beq.n 8015eda <sys_timeout_abs+0xa6>
8015ec2: 693b ldr r3, [r7, #16]
8015ec4: 685a ldr r2, [r3, #4]
8015ec6: 697b ldr r3, [r7, #20]
8015ec8: 681b ldr r3, [r3, #0]
8015eca: 685b ldr r3, [r3, #4]
8015ecc: 1ad3 subs r3, r2, r3
8015ece: 0fdb lsrs r3, r3, #31
8015ed0: f003 0301 and.w r3, r3, #1
8015ed4: b2db uxtb r3, r3
8015ed6: 2b00 cmp r3, #0
8015ed8: d007 beq.n 8015eea <sys_timeout_abs+0xb6>
timeout->next = t->next;
8015eda: 697b ldr r3, [r7, #20]
8015edc: 681a ldr r2, [r3, #0]
8015ede: 693b ldr r3, [r7, #16]
8015ee0: 601a str r2, [r3, #0]
t->next = timeout;
8015ee2: 697b ldr r3, [r7, #20]
8015ee4: 693a ldr r2, [r7, #16]
8015ee6: 601a str r2, [r3, #0]
break;
8015ee8: e007 b.n 8015efa <sys_timeout_abs+0xc6>
for (t = next_timeout; t != NULL; t = t->next) {
8015eea: 697b ldr r3, [r7, #20]
8015eec: 681b ldr r3, [r3, #0]
8015eee: 617b str r3, [r7, #20]
8015ef0: 697b ldr r3, [r7, #20]
8015ef2: 2b00 cmp r3, #0
8015ef4: d1e1 bne.n 8015eba <sys_timeout_abs+0x86>
8015ef6: e000 b.n 8015efa <sys_timeout_abs+0xc6>
return;
8015ef8: bf00 nop
}
}
}
}
8015efa: 3718 adds r7, #24
8015efc: 46bd mov sp, r7
8015efe: bd80 pop {r7, pc}
8015f00: 0801df4c .word 0x0801df4c
8015f04: 0801df80 .word 0x0801df80
8015f08: 0801dfc0 .word 0x0801dfc0
8015f0c: 20008760 .word 0x20008760
08015f10 <lwip_cyclic_timer>:
#if !LWIP_TESTMODE
static
#endif
void
lwip_cyclic_timer(void *arg)
{
8015f10: b580 push {r7, lr}
8015f12: b086 sub sp, #24
8015f14: af00 add r7, sp, #0
8015f16: 6078 str r0, [r7, #4]
u32_t now;
u32_t next_timeout_time;
const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
8015f18: 687b ldr r3, [r7, #4]
8015f1a: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
#endif
cyclic->handler();
8015f1c: 697b ldr r3, [r7, #20]
8015f1e: 685b ldr r3, [r3, #4]
8015f20: 4798 blx r3
now = sys_now();
8015f22: f7f5 fc5f bl 800b7e4 <sys_now>
8015f26: 6138 str r0, [r7, #16]
next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */
8015f28: 697b ldr r3, [r7, #20]
8015f2a: 681a ldr r2, [r3, #0]
8015f2c: 4b0f ldr r3, [pc, #60] ; (8015f6c <lwip_cyclic_timer+0x5c>)
8015f2e: 681b ldr r3, [r3, #0]
8015f30: 4413 add r3, r2
8015f32: 60fb str r3, [r7, #12]
if (TIME_LESS_THAN(next_timeout_time, now)) {
8015f34: 68fa ldr r2, [r7, #12]
8015f36: 693b ldr r3, [r7, #16]
8015f38: 1ad3 subs r3, r2, r3
8015f3a: 0fdb lsrs r3, r3, #31
8015f3c: f003 0301 and.w r3, r3, #1
8015f40: b2db uxtb r3, r3
8015f42: 2b00 cmp r3, #0
8015f44: d009 beq.n 8015f5a <lwip_cyclic_timer+0x4a>
/* timer would immediately expire again -> "overload" -> restart without any correction */
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
8015f46: 697b ldr r3, [r7, #20]
8015f48: 681a ldr r2, [r3, #0]
8015f4a: 693b ldr r3, [r7, #16]
8015f4c: 4413 add r3, r2
8015f4e: 687a ldr r2, [r7, #4]
8015f50: 4907 ldr r1, [pc, #28] ; (8015f70 <lwip_cyclic_timer+0x60>)
8015f52: 4618 mov r0, r3
8015f54: f7ff ff6e bl 8015e34 <sys_timeout_abs>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
#endif
}
}
8015f58: e004 b.n 8015f64 <lwip_cyclic_timer+0x54>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
8015f5a: 687a ldr r2, [r7, #4]
8015f5c: 4904 ldr r1, [pc, #16] ; (8015f70 <lwip_cyclic_timer+0x60>)
8015f5e: 68f8 ldr r0, [r7, #12]
8015f60: f7ff ff68 bl 8015e34 <sys_timeout_abs>
}
8015f64: bf00 nop
8015f66: 3718 adds r7, #24
8015f68: 46bd mov sp, r7
8015f6a: bd80 pop {r7, pc}
8015f6c: 20008764 .word 0x20008764
8015f70: 08015f11 .word 0x08015f11
08015f74 <sys_timeouts_init>:
/** Initialize this module */
void sys_timeouts_init(void)
{
8015f74: b580 push {r7, lr}
8015f76: b082 sub sp, #8
8015f78: af00 add r7, sp, #0
size_t i;
/* tcp_tmr() at index 0 is started on demand */
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015f7a: 2301 movs r3, #1
8015f7c: 607b str r3, [r7, #4]
8015f7e: e00e b.n 8015f9e <sys_timeouts_init+0x2a>
/* we have to cast via size_t to get rid of const warning
(this is OK as cyclic_timer() casts back to const* */
sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
8015f80: 4a0a ldr r2, [pc, #40] ; (8015fac <sys_timeouts_init+0x38>)
8015f82: 687b ldr r3, [r7, #4]
8015f84: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8015f88: 687b ldr r3, [r7, #4]
8015f8a: 00db lsls r3, r3, #3
8015f8c: 4a07 ldr r2, [pc, #28] ; (8015fac <sys_timeouts_init+0x38>)
8015f8e: 4413 add r3, r2
8015f90: 461a mov r2, r3
8015f92: 4907 ldr r1, [pc, #28] ; (8015fb0 <sys_timeouts_init+0x3c>)
8015f94: f000 f80e bl 8015fb4 <sys_timeout>
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015f98: 687b ldr r3, [r7, #4]
8015f9a: 3301 adds r3, #1
8015f9c: 607b str r3, [r7, #4]
8015f9e: 687b ldr r3, [r7, #4]
8015fa0: 2b04 cmp r3, #4
8015fa2: d9ed bls.n 8015f80 <sys_timeouts_init+0xc>
}
}
8015fa4: bf00 nop
8015fa6: 3708 adds r7, #8
8015fa8: 46bd mov sp, r7
8015faa: bd80 pop {r7, pc}
8015fac: 08020e40 .word 0x08020e40
8015fb0: 08015f11 .word 0x08015f11
08015fb4 <sys_timeout>:
sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
void
sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
#endif /* LWIP_DEBUG_TIMERNAMES */
{
8015fb4: b580 push {r7, lr}
8015fb6: b086 sub sp, #24
8015fb8: af00 add r7, sp, #0
8015fba: 60f8 str r0, [r7, #12]
8015fbc: 60b9 str r1, [r7, #8]
8015fbe: 607a str r2, [r7, #4]
u32_t next_timeout_time;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
8015fc0: 68fb ldr r3, [r7, #12]
8015fc2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8015fc6: d306 bcc.n 8015fd6 <sys_timeout+0x22>
8015fc8: 4b0a ldr r3, [pc, #40] ; (8015ff4 <sys_timeout+0x40>)
8015fca: f240 1229 movw r2, #297 ; 0x129
8015fce: 490a ldr r1, [pc, #40] ; (8015ff8 <sys_timeout+0x44>)
8015fd0: 480a ldr r0, [pc, #40] ; (8015ffc <sys_timeout+0x48>)
8015fd2: f005 f81f bl 801b014 <iprintf>
next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */
8015fd6: f7f5 fc05 bl 800b7e4 <sys_now>
8015fda: 4602 mov r2, r0
8015fdc: 68fb ldr r3, [r7, #12]
8015fde: 4413 add r3, r2
8015fe0: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
#else
sys_timeout_abs(next_timeout_time, handler, arg);
8015fe2: 687a ldr r2, [r7, #4]
8015fe4: 68b9 ldr r1, [r7, #8]
8015fe6: 6978 ldr r0, [r7, #20]
8015fe8: f7ff ff24 bl 8015e34 <sys_timeout_abs>
#endif
}
8015fec: bf00 nop
8015fee: 3718 adds r7, #24
8015ff0: 46bd mov sp, r7
8015ff2: bd80 pop {r7, pc}
8015ff4: 0801df4c .word 0x0801df4c
8015ff8: 0801dfe8 .word 0x0801dfe8
8015ffc: 0801dfc0 .word 0x0801dfc0
08016000 <sys_check_timeouts>:
*
* Must be called periodically from your main loop.
*/
void
sys_check_timeouts(void)
{
8016000: b580 push {r7, lr}
8016002: b084 sub sp, #16
8016004: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
/* Process only timers expired at the start of the function. */
now = sys_now();
8016006: f7f5 fbed bl 800b7e4 <sys_now>
801600a: 60f8 str r0, [r7, #12]
sys_timeout_handler handler;
void *arg;
PBUF_CHECK_FREE_OOSEQ();
tmptimeout = next_timeout;
801600c: 4b17 ldr r3, [pc, #92] ; (801606c <sys_check_timeouts+0x6c>)
801600e: 681b ldr r3, [r3, #0]
8016010: 60bb str r3, [r7, #8]
if (tmptimeout == NULL) {
8016012: 68bb ldr r3, [r7, #8]
8016014: 2b00 cmp r3, #0
8016016: d022 beq.n 801605e <sys_check_timeouts+0x5e>
return;
}
if (TIME_LESS_THAN(now, tmptimeout->time)) {
8016018: 68bb ldr r3, [r7, #8]
801601a: 685b ldr r3, [r3, #4]
801601c: 68fa ldr r2, [r7, #12]
801601e: 1ad3 subs r3, r2, r3
8016020: 0fdb lsrs r3, r3, #31
8016022: f003 0301 and.w r3, r3, #1
8016026: b2db uxtb r3, r3
8016028: 2b00 cmp r3, #0
801602a: d11a bne.n 8016062 <sys_check_timeouts+0x62>
return;
}
/* Timeout has expired */
next_timeout = tmptimeout->next;
801602c: 68bb ldr r3, [r7, #8]
801602e: 681b ldr r3, [r3, #0]
8016030: 4a0e ldr r2, [pc, #56] ; (801606c <sys_check_timeouts+0x6c>)
8016032: 6013 str r3, [r2, #0]
handler = tmptimeout->h;
8016034: 68bb ldr r3, [r7, #8]
8016036: 689b ldr r3, [r3, #8]
8016038: 607b str r3, [r7, #4]
arg = tmptimeout->arg;
801603a: 68bb ldr r3, [r7, #8]
801603c: 68db ldr r3, [r3, #12]
801603e: 603b str r3, [r7, #0]
current_timeout_due_time = tmptimeout->time;
8016040: 68bb ldr r3, [r7, #8]
8016042: 685b ldr r3, [r3, #4]
8016044: 4a0a ldr r2, [pc, #40] ; (8016070 <sys_check_timeouts+0x70>)
8016046: 6013 str r3, [r2, #0]
if (handler != NULL) {
LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
}
#endif /* LWIP_DEBUG_TIMERNAMES */
memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
8016048: 68b9 ldr r1, [r7, #8]
801604a: 200a movs r0, #10
801604c: f7f9 fc20 bl 800f890 <memp_free>
if (handler != NULL) {
8016050: 687b ldr r3, [r7, #4]
8016052: 2b00 cmp r3, #0
8016054: d0da beq.n 801600c <sys_check_timeouts+0xc>
handler(arg);
8016056: 687b ldr r3, [r7, #4]
8016058: 6838 ldr r0, [r7, #0]
801605a: 4798 blx r3
do {
801605c: e7d6 b.n 801600c <sys_check_timeouts+0xc>
return;
801605e: bf00 nop
8016060: e000 b.n 8016064 <sys_check_timeouts+0x64>
return;
8016062: bf00 nop
}
LWIP_TCPIP_THREAD_ALIVE();
/* Repeat until all expired timers have been called */
} while (1);
}
8016064: 3710 adds r7, #16
8016066: 46bd mov sp, r7
8016068: bd80 pop {r7, pc}
801606a: bf00 nop
801606c: 20008760 .word 0x20008760
8016070: 20008764 .word 0x20008764
08016074 <sys_timeouts_sleeptime>:
/** Return the time left before the next timeout is due. If no timeouts are
* enqueued, returns 0xffffffff
*/
u32_t
sys_timeouts_sleeptime(void)
{
8016074: b580 push {r7, lr}
8016076: b082 sub sp, #8
8016078: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
if (next_timeout == NULL) {
801607a: 4b16 ldr r3, [pc, #88] ; (80160d4 <sys_timeouts_sleeptime+0x60>)
801607c: 681b ldr r3, [r3, #0]
801607e: 2b00 cmp r3, #0
8016080: d102 bne.n 8016088 <sys_timeouts_sleeptime+0x14>
return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
8016082: f04f 33ff mov.w r3, #4294967295
8016086: e020 b.n 80160ca <sys_timeouts_sleeptime+0x56>
}
now = sys_now();
8016088: f7f5 fbac bl 800b7e4 <sys_now>
801608c: 6078 str r0, [r7, #4]
if (TIME_LESS_THAN(next_timeout->time, now)) {
801608e: 4b11 ldr r3, [pc, #68] ; (80160d4 <sys_timeouts_sleeptime+0x60>)
8016090: 681b ldr r3, [r3, #0]
8016092: 685a ldr r2, [r3, #4]
8016094: 687b ldr r3, [r7, #4]
8016096: 1ad3 subs r3, r2, r3
8016098: 0fdb lsrs r3, r3, #31
801609a: f003 0301 and.w r3, r3, #1
801609e: b2db uxtb r3, r3
80160a0: 2b00 cmp r3, #0
80160a2: d001 beq.n 80160a8 <sys_timeouts_sleeptime+0x34>
return 0;
80160a4: 2300 movs r3, #0
80160a6: e010 b.n 80160ca <sys_timeouts_sleeptime+0x56>
} else {
u32_t ret = (u32_t)(next_timeout->time - now);
80160a8: 4b0a ldr r3, [pc, #40] ; (80160d4 <sys_timeouts_sleeptime+0x60>)
80160aa: 681b ldr r3, [r3, #0]
80160ac: 685a ldr r2, [r3, #4]
80160ae: 687b ldr r3, [r7, #4]
80160b0: 1ad3 subs r3, r2, r3
80160b2: 603b str r3, [r7, #0]
LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
80160b4: 683b ldr r3, [r7, #0]
80160b6: 2b00 cmp r3, #0
80160b8: da06 bge.n 80160c8 <sys_timeouts_sleeptime+0x54>
80160ba: 4b07 ldr r3, [pc, #28] ; (80160d8 <sys_timeouts_sleeptime+0x64>)
80160bc: f44f 72dc mov.w r2, #440 ; 0x1b8
80160c0: 4906 ldr r1, [pc, #24] ; (80160dc <sys_timeouts_sleeptime+0x68>)
80160c2: 4807 ldr r0, [pc, #28] ; (80160e0 <sys_timeouts_sleeptime+0x6c>)
80160c4: f004 ffa6 bl 801b014 <iprintf>
return ret;
80160c8: 683b ldr r3, [r7, #0]
}
}
80160ca: 4618 mov r0, r3
80160cc: 3708 adds r7, #8
80160ce: 46bd mov sp, r7
80160d0: bd80 pop {r7, pc}
80160d2: bf00 nop
80160d4: 20008760 .word 0x20008760
80160d8: 0801df4c .word 0x0801df4c
80160dc: 0801e020 .word 0x0801e020
80160e0: 0801dfc0 .word 0x0801dfc0
080160e4 <udp_init>:
/**
* Initialize this module.
*/
void
udp_init(void)
{
80160e4: b580 push {r7, lr}
80160e6: af00 add r7, sp, #0
#ifdef LWIP_RAND
udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
80160e8: f004 ffac bl 801b044 <rand>
80160ec: 4603 mov r3, r0
80160ee: b29b uxth r3, r3
80160f0: f3c3 030d ubfx r3, r3, #0, #14
80160f4: b29b uxth r3, r3
80160f6: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
80160fa: b29a uxth r2, r3
80160fc: 4b01 ldr r3, [pc, #4] ; (8016104 <udp_init+0x20>)
80160fe: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
8016100: bf00 nop
8016102: bd80 pop {r7, pc}
8016104: 2000007c .word 0x2000007c
08016108 <udp_new_port>:
*
* @return a new (free) local UDP port number
*/
static u16_t
udp_new_port(void)
{
8016108: b480 push {r7}
801610a: b083 sub sp, #12
801610c: af00 add r7, sp, #0
u16_t n = 0;
801610e: 2300 movs r3, #0
8016110: 80fb strh r3, [r7, #6]
struct udp_pcb *pcb;
again:
if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
8016112: 4b17 ldr r3, [pc, #92] ; (8016170 <udp_new_port+0x68>)
8016114: 881b ldrh r3, [r3, #0]
8016116: 1c5a adds r2, r3, #1
8016118: b291 uxth r1, r2
801611a: 4a15 ldr r2, [pc, #84] ; (8016170 <udp_new_port+0x68>)
801611c: 8011 strh r1, [r2, #0]
801611e: f64f 72ff movw r2, #65535 ; 0xffff
8016122: 4293 cmp r3, r2
8016124: d103 bne.n 801612e <udp_new_port+0x26>
udp_port = UDP_LOCAL_PORT_RANGE_START;
8016126: 4b12 ldr r3, [pc, #72] ; (8016170 <udp_new_port+0x68>)
8016128: f44f 4240 mov.w r2, #49152 ; 0xc000
801612c: 801a strh r2, [r3, #0]
}
/* Check all PCBs. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
801612e: 4b11 ldr r3, [pc, #68] ; (8016174 <udp_new_port+0x6c>)
8016130: 681b ldr r3, [r3, #0]
8016132: 603b str r3, [r7, #0]
8016134: e011 b.n 801615a <udp_new_port+0x52>
if (pcb->local_port == udp_port) {
8016136: 683b ldr r3, [r7, #0]
8016138: 8a5a ldrh r2, [r3, #18]
801613a: 4b0d ldr r3, [pc, #52] ; (8016170 <udp_new_port+0x68>)
801613c: 881b ldrh r3, [r3, #0]
801613e: 429a cmp r2, r3
8016140: d108 bne.n 8016154 <udp_new_port+0x4c>
if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
8016142: 88fb ldrh r3, [r7, #6]
8016144: 3301 adds r3, #1
8016146: 80fb strh r3, [r7, #6]
8016148: 88fb ldrh r3, [r7, #6]
801614a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
801614e: d3e0 bcc.n 8016112 <udp_new_port+0xa>
return 0;
8016150: 2300 movs r3, #0
8016152: e007 b.n 8016164 <udp_new_port+0x5c>
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016154: 683b ldr r3, [r7, #0]
8016156: 68db ldr r3, [r3, #12]
8016158: 603b str r3, [r7, #0]
801615a: 683b ldr r3, [r7, #0]
801615c: 2b00 cmp r3, #0
801615e: d1ea bne.n 8016136 <udp_new_port+0x2e>
}
goto again;
}
}
return udp_port;
8016160: 4b03 ldr r3, [pc, #12] ; (8016170 <udp_new_port+0x68>)
8016162: 881b ldrh r3, [r3, #0]
}
8016164: 4618 mov r0, r3
8016166: 370c adds r7, #12
8016168: 46bd mov sp, r7
801616a: f85d 7b04 ldr.w r7, [sp], #4
801616e: 4770 bx lr
8016170: 2000007c .word 0x2000007c
8016174: 2000f5d8 .word 0x2000f5d8
08016178 <udp_input_local_match>:
* @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
* @return 1 on match, 0 otherwise
*/
static u8_t
udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
{
8016178: b580 push {r7, lr}
801617a: b084 sub sp, #16
801617c: af00 add r7, sp, #0
801617e: 60f8 str r0, [r7, #12]
8016180: 60b9 str r1, [r7, #8]
8016182: 4613 mov r3, r2
8016184: 71fb strb r3, [r7, #7]
LWIP_UNUSED_ARG(inp); /* in IPv6 only case */
LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
8016186: 68fb ldr r3, [r7, #12]
8016188: 2b00 cmp r3, #0
801618a: d105 bne.n 8016198 <udp_input_local_match+0x20>
801618c: 4b27 ldr r3, [pc, #156] ; (801622c <udp_input_local_match+0xb4>)
801618e: 2287 movs r2, #135 ; 0x87
8016190: 4927 ldr r1, [pc, #156] ; (8016230 <udp_input_local_match+0xb8>)
8016192: 4828 ldr r0, [pc, #160] ; (8016234 <udp_input_local_match+0xbc>)
8016194: f004 ff3e bl 801b014 <iprintf>
LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
8016198: 68bb ldr r3, [r7, #8]
801619a: 2b00 cmp r3, #0
801619c: d105 bne.n 80161aa <udp_input_local_match+0x32>
801619e: 4b23 ldr r3, [pc, #140] ; (801622c <udp_input_local_match+0xb4>)
80161a0: 2288 movs r2, #136 ; 0x88
80161a2: 4925 ldr r1, [pc, #148] ; (8016238 <udp_input_local_match+0xc0>)
80161a4: 4823 ldr r0, [pc, #140] ; (8016234 <udp_input_local_match+0xbc>)
80161a6: f004 ff35 bl 801b014 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80161aa: 68fb ldr r3, [r7, #12]
80161ac: 7a1b ldrb r3, [r3, #8]
80161ae: 2b00 cmp r3, #0
80161b0: d00b beq.n 80161ca <udp_input_local_match+0x52>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80161b2: 68fb ldr r3, [r7, #12]
80161b4: 7a1a ldrb r2, [r3, #8]
80161b6: 4b21 ldr r3, [pc, #132] ; (801623c <udp_input_local_match+0xc4>)
80161b8: 685b ldr r3, [r3, #4]
80161ba: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80161be: 3301 adds r3, #1
80161c0: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80161c2: 429a cmp r2, r3
80161c4: d001 beq.n 80161ca <udp_input_local_match+0x52>
return 0;
80161c6: 2300 movs r3, #0
80161c8: e02b b.n 8016222 <udp_input_local_match+0xaa>
/* Only need to check PCB if incoming IP version matches PCB IP version */
if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
#if LWIP_IPV4
/* Special case: IPv4 broadcast: all or broadcasts in my subnet
* Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
if (broadcast != 0) {
80161ca: 79fb ldrb r3, [r7, #7]
80161cc: 2b00 cmp r3, #0
80161ce: d018 beq.n 8016202 <udp_input_local_match+0x8a>
#if IP_SOF_BROADCAST_RECV
if (ip_get_option(pcb, SOF_BROADCAST))
#endif /* IP_SOF_BROADCAST_RECV */
{
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80161d0: 68fb ldr r3, [r7, #12]
80161d2: 2b00 cmp r3, #0
80161d4: d013 beq.n 80161fe <udp_input_local_match+0x86>
80161d6: 68fb ldr r3, [r7, #12]
80161d8: 681b ldr r3, [r3, #0]
80161da: 2b00 cmp r3, #0
80161dc: d00f beq.n 80161fe <udp_input_local_match+0x86>
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
80161de: 4b17 ldr r3, [pc, #92] ; (801623c <udp_input_local_match+0xc4>)
80161e0: 695b ldr r3, [r3, #20]
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80161e2: f1b3 3fff cmp.w r3, #4294967295
80161e6: d00a beq.n 80161fe <udp_input_local_match+0x86>
ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
80161e8: 68fb ldr r3, [r7, #12]
80161ea: 681a ldr r2, [r3, #0]
80161ec: 4b13 ldr r3, [pc, #76] ; (801623c <udp_input_local_match+0xc4>)
80161ee: 695b ldr r3, [r3, #20]
80161f0: 405a eors r2, r3
80161f2: 68bb ldr r3, [r7, #8]
80161f4: 3308 adds r3, #8
80161f6: 681b ldr r3, [r3, #0]
80161f8: 4013 ands r3, r2
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
80161fa: 2b00 cmp r3, #0
80161fc: d110 bne.n 8016220 <udp_input_local_match+0xa8>
return 1;
80161fe: 2301 movs r3, #1
8016200: e00f b.n 8016222 <udp_input_local_match+0xaa>
}
}
} else
#endif /* LWIP_IPV4 */
/* Handle IPv4 and IPv6: all or exact match */
if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
8016202: 68fb ldr r3, [r7, #12]
8016204: 2b00 cmp r3, #0
8016206: d009 beq.n 801621c <udp_input_local_match+0xa4>
8016208: 68fb ldr r3, [r7, #12]
801620a: 681b ldr r3, [r3, #0]
801620c: 2b00 cmp r3, #0
801620e: d005 beq.n 801621c <udp_input_local_match+0xa4>
8016210: 68fb ldr r3, [r7, #12]
8016212: 681a ldr r2, [r3, #0]
8016214: 4b09 ldr r3, [pc, #36] ; (801623c <udp_input_local_match+0xc4>)
8016216: 695b ldr r3, [r3, #20]
8016218: 429a cmp r2, r3
801621a: d101 bne.n 8016220 <udp_input_local_match+0xa8>
return 1;
801621c: 2301 movs r3, #1
801621e: e000 b.n 8016222 <udp_input_local_match+0xaa>
}
}
return 0;
8016220: 2300 movs r3, #0
}
8016222: 4618 mov r0, r3
8016224: 3710 adds r7, #16
8016226: 46bd mov sp, r7
8016228: bd80 pop {r7, pc}
801622a: bf00 nop
801622c: 0801e034 .word 0x0801e034
8016230: 0801e064 .word 0x0801e064
8016234: 0801e088 .word 0x0801e088
8016238: 0801e0b0 .word 0x0801e0b0
801623c: 2000be8c .word 0x2000be8c
08016240 <udp_input>:
* @param inp network interface on which the datagram was received.
*
*/
void
udp_input(struct pbuf *p, struct netif *inp)
{
8016240: b590 push {r4, r7, lr}
8016242: b08d sub sp, #52 ; 0x34
8016244: af02 add r7, sp, #8
8016246: 6078 str r0, [r7, #4]
8016248: 6039 str r1, [r7, #0]
struct udp_hdr *udphdr;
struct udp_pcb *pcb, *prev;
struct udp_pcb *uncon_pcb;
u16_t src, dest;
u8_t broadcast;
u8_t for_us = 0;
801624a: 2300 movs r3, #0
801624c: 76fb strb r3, [r7, #27]
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
801624e: 687b ldr r3, [r7, #4]
8016250: 2b00 cmp r3, #0
8016252: d105 bne.n 8016260 <udp_input+0x20>
8016254: 4b7c ldr r3, [pc, #496] ; (8016448 <udp_input+0x208>)
8016256: 22cf movs r2, #207 ; 0xcf
8016258: 497c ldr r1, [pc, #496] ; (801644c <udp_input+0x20c>)
801625a: 487d ldr r0, [pc, #500] ; (8016450 <udp_input+0x210>)
801625c: f004 feda bl 801b014 <iprintf>
LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
8016260: 683b ldr r3, [r7, #0]
8016262: 2b00 cmp r3, #0
8016264: d105 bne.n 8016272 <udp_input+0x32>
8016266: 4b78 ldr r3, [pc, #480] ; (8016448 <udp_input+0x208>)
8016268: 22d0 movs r2, #208 ; 0xd0
801626a: 497a ldr r1, [pc, #488] ; (8016454 <udp_input+0x214>)
801626c: 4878 ldr r0, [pc, #480] ; (8016450 <udp_input+0x210>)
801626e: f004 fed1 bl 801b014 <iprintf>
PERF_START;
UDP_STATS_INC(udp.recv);
/* Check minimum length (UDP header) */
if (p->len < UDP_HLEN) {
8016272: 687b ldr r3, [r7, #4]
8016274: 895b ldrh r3, [r3, #10]
8016276: 2b07 cmp r3, #7
8016278: d803 bhi.n 8016282 <udp_input+0x42>
LWIP_DEBUGF(UDP_DEBUG,
("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
UDP_STATS_INC(udp.lenerr);
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
801627a: 6878 ldr r0, [r7, #4]
801627c: f7fa f9b4 bl 80105e8 <pbuf_free>
goto end;
8016280: e0de b.n 8016440 <udp_input+0x200>
}
udphdr = (struct udp_hdr *)p->payload;
8016282: 687b ldr r3, [r7, #4]
8016284: 685b ldr r3, [r3, #4]
8016286: 617b str r3, [r7, #20]
/* is broadcast packet ? */
broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
8016288: 4b73 ldr r3, [pc, #460] ; (8016458 <udp_input+0x218>)
801628a: 695a ldr r2, [r3, #20]
801628c: 4b72 ldr r3, [pc, #456] ; (8016458 <udp_input+0x218>)
801628e: 681b ldr r3, [r3, #0]
8016290: 4619 mov r1, r3
8016292: 4610 mov r0, r2
8016294: f003 fe16 bl 8019ec4 <ip4_addr_isbroadcast_u32>
8016298: 4603 mov r3, r0
801629a: 74fb strb r3, [r7, #19]
LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
/* convert src and dest ports to host byte order */
src = lwip_ntohs(udphdr->src);
801629c: 697b ldr r3, [r7, #20]
801629e: 881b ldrh r3, [r3, #0]
80162a0: b29b uxth r3, r3
80162a2: 4618 mov r0, r3
80162a4: f7f8 fdec bl 800ee80 <lwip_htons>
80162a8: 4603 mov r3, r0
80162aa: 823b strh r3, [r7, #16]
dest = lwip_ntohs(udphdr->dest);
80162ac: 697b ldr r3, [r7, #20]
80162ae: 885b ldrh r3, [r3, #2]
80162b0: b29b uxth r3, r3
80162b2: 4618 mov r0, r3
80162b4: f7f8 fde4 bl 800ee80 <lwip_htons>
80162b8: 4603 mov r3, r0
80162ba: 81fb strh r3, [r7, #14]
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
pcb = NULL;
80162bc: 2300 movs r3, #0
80162be: 627b str r3, [r7, #36] ; 0x24
prev = NULL;
80162c0: 2300 movs r3, #0
80162c2: 623b str r3, [r7, #32]
uncon_pcb = NULL;
80162c4: 2300 movs r3, #0
80162c6: 61fb str r3, [r7, #28]
/* Iterate through the UDP pcb list for a matching pcb.
* 'Perfect match' pcbs (connected to the remote port & ip address) are
* preferred. If no perfect match is found, the first unconnected pcb that
* matches the local port and ip address gets the datagram. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
80162c8: 4b64 ldr r3, [pc, #400] ; (801645c <udp_input+0x21c>)
80162ca: 681b ldr r3, [r3, #0]
80162cc: 627b str r3, [r7, #36] ; 0x24
80162ce: e054 b.n 801637a <udp_input+0x13a>
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
/* compare PCB local addr+port to UDP destination addr+port */
if ((pcb->local_port == dest) &&
80162d0: 6a7b ldr r3, [r7, #36] ; 0x24
80162d2: 8a5b ldrh r3, [r3, #18]
80162d4: 89fa ldrh r2, [r7, #14]
80162d6: 429a cmp r2, r3
80162d8: d14a bne.n 8016370 <udp_input+0x130>
(udp_input_local_match(pcb, inp, broadcast) != 0)) {
80162da: 7cfb ldrb r3, [r7, #19]
80162dc: 461a mov r2, r3
80162de: 6839 ldr r1, [r7, #0]
80162e0: 6a78 ldr r0, [r7, #36] ; 0x24
80162e2: f7ff ff49 bl 8016178 <udp_input_local_match>
80162e6: 4603 mov r3, r0
if ((pcb->local_port == dest) &&
80162e8: 2b00 cmp r3, #0
80162ea: d041 beq.n 8016370 <udp_input+0x130>
if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
80162ec: 6a7b ldr r3, [r7, #36] ; 0x24
80162ee: 7c1b ldrb r3, [r3, #16]
80162f0: f003 0304 and.w r3, r3, #4
80162f4: 2b00 cmp r3, #0
80162f6: d11d bne.n 8016334 <udp_input+0xf4>
if (uncon_pcb == NULL) {
80162f8: 69fb ldr r3, [r7, #28]
80162fa: 2b00 cmp r3, #0
80162fc: d102 bne.n 8016304 <udp_input+0xc4>
/* the first unconnected matching PCB */
uncon_pcb = pcb;
80162fe: 6a7b ldr r3, [r7, #36] ; 0x24
8016300: 61fb str r3, [r7, #28]
8016302: e017 b.n 8016334 <udp_input+0xf4>
#if LWIP_IPV4
} else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
8016304: 7cfb ldrb r3, [r7, #19]
8016306: 2b00 cmp r3, #0
8016308: d014 beq.n 8016334 <udp_input+0xf4>
801630a: 4b53 ldr r3, [pc, #332] ; (8016458 <udp_input+0x218>)
801630c: 695b ldr r3, [r3, #20]
801630e: f1b3 3fff cmp.w r3, #4294967295
8016312: d10f bne.n 8016334 <udp_input+0xf4>
/* global broadcast address (only valid for IPv4; match was checked before) */
if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
8016314: 69fb ldr r3, [r7, #28]
8016316: 681a ldr r2, [r3, #0]
8016318: 683b ldr r3, [r7, #0]
801631a: 3304 adds r3, #4
801631c: 681b ldr r3, [r3, #0]
801631e: 429a cmp r2, r3
8016320: d008 beq.n 8016334 <udp_input+0xf4>
/* uncon_pcb does not match the input netif, check this pcb */
if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
8016322: 6a7b ldr r3, [r7, #36] ; 0x24
8016324: 681a ldr r2, [r3, #0]
8016326: 683b ldr r3, [r7, #0]
8016328: 3304 adds r3, #4
801632a: 681b ldr r3, [r3, #0]
801632c: 429a cmp r2, r3
801632e: d101 bne.n 8016334 <udp_input+0xf4>
/* better match */
uncon_pcb = pcb;
8016330: 6a7b ldr r3, [r7, #36] ; 0x24
8016332: 61fb str r3, [r7, #28]
}
#endif /* SO_REUSE */
}
/* compare PCB remote addr+port to UDP source addr+port */
if ((pcb->remote_port == src) &&
8016334: 6a7b ldr r3, [r7, #36] ; 0x24
8016336: 8a9b ldrh r3, [r3, #20]
8016338: 8a3a ldrh r2, [r7, #16]
801633a: 429a cmp r2, r3
801633c: d118 bne.n 8016370 <udp_input+0x130>
(ip_addr_isany_val(pcb->remote_ip) ||
801633e: 6a7b ldr r3, [r7, #36] ; 0x24
8016340: 685b ldr r3, [r3, #4]
if ((pcb->remote_port == src) &&
8016342: 2b00 cmp r3, #0
8016344: d005 beq.n 8016352 <udp_input+0x112>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
8016346: 6a7b ldr r3, [r7, #36] ; 0x24
8016348: 685a ldr r2, [r3, #4]
801634a: 4b43 ldr r3, [pc, #268] ; (8016458 <udp_input+0x218>)
801634c: 691b ldr r3, [r3, #16]
(ip_addr_isany_val(pcb->remote_ip) ||
801634e: 429a cmp r2, r3
8016350: d10e bne.n 8016370 <udp_input+0x130>
/* the first fully matching PCB */
if (prev != NULL) {
8016352: 6a3b ldr r3, [r7, #32]
8016354: 2b00 cmp r3, #0
8016356: d014 beq.n 8016382 <udp_input+0x142>
/* move the pcb to the front of udp_pcbs so that is
found faster next time */
prev->next = pcb->next;
8016358: 6a7b ldr r3, [r7, #36] ; 0x24
801635a: 68da ldr r2, [r3, #12]
801635c: 6a3b ldr r3, [r7, #32]
801635e: 60da str r2, [r3, #12]
pcb->next = udp_pcbs;
8016360: 4b3e ldr r3, [pc, #248] ; (801645c <udp_input+0x21c>)
8016362: 681a ldr r2, [r3, #0]
8016364: 6a7b ldr r3, [r7, #36] ; 0x24
8016366: 60da str r2, [r3, #12]
udp_pcbs = pcb;
8016368: 4a3c ldr r2, [pc, #240] ; (801645c <udp_input+0x21c>)
801636a: 6a7b ldr r3, [r7, #36] ; 0x24
801636c: 6013 str r3, [r2, #0]
} else {
UDP_STATS_INC(udp.cachehit);
}
break;
801636e: e008 b.n 8016382 <udp_input+0x142>
}
}
prev = pcb;
8016370: 6a7b ldr r3, [r7, #36] ; 0x24
8016372: 623b str r3, [r7, #32]
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016374: 6a7b ldr r3, [r7, #36] ; 0x24
8016376: 68db ldr r3, [r3, #12]
8016378: 627b str r3, [r7, #36] ; 0x24
801637a: 6a7b ldr r3, [r7, #36] ; 0x24
801637c: 2b00 cmp r3, #0
801637e: d1a7 bne.n 80162d0 <udp_input+0x90>
8016380: e000 b.n 8016384 <udp_input+0x144>
break;
8016382: bf00 nop
}
/* no fully matching pcb found? then look for an unconnected pcb */
if (pcb == NULL) {
8016384: 6a7b ldr r3, [r7, #36] ; 0x24
8016386: 2b00 cmp r3, #0
8016388: d101 bne.n 801638e <udp_input+0x14e>
pcb = uncon_pcb;
801638a: 69fb ldr r3, [r7, #28]
801638c: 627b str r3, [r7, #36] ; 0x24
}
/* Check checksum if this is a match or if it was directed at us. */
if (pcb != NULL) {
801638e: 6a7b ldr r3, [r7, #36] ; 0x24
8016390: 2b00 cmp r3, #0
8016392: d002 beq.n 801639a <udp_input+0x15a>
for_us = 1;
8016394: 2301 movs r3, #1
8016396: 76fb strb r3, [r7, #27]
8016398: e00a b.n 80163b0 <udp_input+0x170>
for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
}
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
if (!ip_current_is_v6()) {
for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
801639a: 683b ldr r3, [r7, #0]
801639c: 3304 adds r3, #4
801639e: 681a ldr r2, [r3, #0]
80163a0: 4b2d ldr r3, [pc, #180] ; (8016458 <udp_input+0x218>)
80163a2: 695b ldr r3, [r3, #20]
80163a4: 429a cmp r2, r3
80163a6: bf0c ite eq
80163a8: 2301 moveq r3, #1
80163aa: 2300 movne r3, #0
80163ac: b2db uxtb r3, r3
80163ae: 76fb strb r3, [r7, #27]
}
#endif /* LWIP_IPV4 */
}
if (for_us) {
80163b0: 7efb ldrb r3, [r7, #27]
80163b2: 2b00 cmp r3, #0
80163b4: d041 beq.n 801643a <udp_input+0x1fa>
}
}
}
}
#endif /* CHECKSUM_CHECK_UDP */
if (pbuf_remove_header(p, UDP_HLEN)) {
80163b6: 2108 movs r1, #8
80163b8: 6878 ldr r0, [r7, #4]
80163ba: f7fa f88f bl 80104dc <pbuf_remove_header>
80163be: 4603 mov r3, r0
80163c0: 2b00 cmp r3, #0
80163c2: d00a beq.n 80163da <udp_input+0x19a>
/* Can we cope with this failing? Just assert for now */
LWIP_ASSERT("pbuf_remove_header failed\n", 0);
80163c4: 4b20 ldr r3, [pc, #128] ; (8016448 <udp_input+0x208>)
80163c6: f44f 72b8 mov.w r2, #368 ; 0x170
80163ca: 4925 ldr r1, [pc, #148] ; (8016460 <udp_input+0x220>)
80163cc: 4820 ldr r0, [pc, #128] ; (8016450 <udp_input+0x210>)
80163ce: f004 fe21 bl 801b014 <iprintf>
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
80163d2: 6878 ldr r0, [r7, #4]
80163d4: f7fa f908 bl 80105e8 <pbuf_free>
goto end;
80163d8: e032 b.n 8016440 <udp_input+0x200>
}
if (pcb != NULL) {
80163da: 6a7b ldr r3, [r7, #36] ; 0x24
80163dc: 2b00 cmp r3, #0
80163de: d012 beq.n 8016406 <udp_input+0x1c6>
}
}
}
#endif /* SO_REUSE && SO_REUSE_RXTOALL */
/* callback */
if (pcb->recv != NULL) {
80163e0: 6a7b ldr r3, [r7, #36] ; 0x24
80163e2: 699b ldr r3, [r3, #24]
80163e4: 2b00 cmp r3, #0
80163e6: d00a beq.n 80163fe <udp_input+0x1be>
/* now the recv function is responsible for freeing p */
pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
80163e8: 6a7b ldr r3, [r7, #36] ; 0x24
80163ea: 699c ldr r4, [r3, #24]
80163ec: 6a7b ldr r3, [r7, #36] ; 0x24
80163ee: 69d8 ldr r0, [r3, #28]
80163f0: 8a3b ldrh r3, [r7, #16]
80163f2: 9300 str r3, [sp, #0]
80163f4: 4b1b ldr r3, [pc, #108] ; (8016464 <udp_input+0x224>)
80163f6: 687a ldr r2, [r7, #4]
80163f8: 6a79 ldr r1, [r7, #36] ; 0x24
80163fa: 47a0 blx r4
} else {
pbuf_free(p);
}
end:
PERF_STOP("udp_input");
return;
80163fc: e021 b.n 8016442 <udp_input+0x202>
pbuf_free(p);
80163fe: 6878 ldr r0, [r7, #4]
8016400: f7fa f8f2 bl 80105e8 <pbuf_free>
goto end;
8016404: e01c b.n 8016440 <udp_input+0x200>
if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
8016406: 7cfb ldrb r3, [r7, #19]
8016408: 2b00 cmp r3, #0
801640a: d112 bne.n 8016432 <udp_input+0x1f2>
801640c: 4b12 ldr r3, [pc, #72] ; (8016458 <udp_input+0x218>)
801640e: 695b ldr r3, [r3, #20]
8016410: f003 03f0 and.w r3, r3, #240 ; 0xf0
8016414: 2be0 cmp r3, #224 ; 0xe0
8016416: d00c beq.n 8016432 <udp_input+0x1f2>
pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
8016418: 4b0f ldr r3, [pc, #60] ; (8016458 <udp_input+0x218>)
801641a: 899b ldrh r3, [r3, #12]
801641c: 3308 adds r3, #8
801641e: b29b uxth r3, r3
8016420: b21b sxth r3, r3
8016422: 4619 mov r1, r3
8016424: 6878 ldr r0, [r7, #4]
8016426: f7fa f8cc bl 80105c2 <pbuf_header_force>
icmp_port_unreach(ip_current_is_v6(), p);
801642a: 2103 movs r1, #3
801642c: 6878 ldr r0, [r7, #4]
801642e: f003 fa0d bl 801984c <icmp_dest_unreach>
pbuf_free(p);
8016432: 6878 ldr r0, [r7, #4]
8016434: f7fa f8d8 bl 80105e8 <pbuf_free>
return;
8016438: e003 b.n 8016442 <udp_input+0x202>
pbuf_free(p);
801643a: 6878 ldr r0, [r7, #4]
801643c: f7fa f8d4 bl 80105e8 <pbuf_free>
return;
8016440: bf00 nop
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
PERF_STOP("udp_input");
#endif /* CHECKSUM_CHECK_UDP */
}
8016442: 372c adds r7, #44 ; 0x2c
8016444: 46bd mov sp, r7
8016446: bd90 pop {r4, r7, pc}
8016448: 0801e034 .word 0x0801e034
801644c: 0801e0d8 .word 0x0801e0d8
8016450: 0801e088 .word 0x0801e088
8016454: 0801e0f0 .word 0x0801e0f0
8016458: 2000be8c .word 0x2000be8c
801645c: 2000f5d8 .word 0x2000f5d8
8016460: 0801e10c .word 0x0801e10c
8016464: 2000be9c .word 0x2000be9c
08016468 <udp_sendto_if>:
* @see udp_disconnect() udp_send()
*/
err_t
udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
{
8016468: b580 push {r7, lr}
801646a: b088 sub sp, #32
801646c: af02 add r7, sp, #8
801646e: 60f8 str r0, [r7, #12]
8016470: 60b9 str r1, [r7, #8]
8016472: 607a str r2, [r7, #4]
8016474: 807b strh r3, [r7, #2]
u16_t chksum)
{
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
const ip_addr_t *src_ip;
LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG);
8016476: 68fb ldr r3, [r7, #12]
8016478: 2b00 cmp r3, #0
801647a: d109 bne.n 8016490 <udp_sendto_if+0x28>
801647c: 4b2e ldr r3, [pc, #184] ; (8016538 <udp_sendto_if+0xd0>)
801647e: f44f 7220 mov.w r2, #640 ; 0x280
8016482: 492e ldr r1, [pc, #184] ; (801653c <udp_sendto_if+0xd4>)
8016484: 482e ldr r0, [pc, #184] ; (8016540 <udp_sendto_if+0xd8>)
8016486: f004 fdc5 bl 801b014 <iprintf>
801648a: f06f 030f mvn.w r3, #15
801648e: e04f b.n 8016530 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG);
8016490: 68bb ldr r3, [r7, #8]
8016492: 2b00 cmp r3, #0
8016494: d109 bne.n 80164aa <udp_sendto_if+0x42>
8016496: 4b28 ldr r3, [pc, #160] ; (8016538 <udp_sendto_if+0xd0>)
8016498: f240 2281 movw r2, #641 ; 0x281
801649c: 4929 ldr r1, [pc, #164] ; (8016544 <udp_sendto_if+0xdc>)
801649e: 4828 ldr r0, [pc, #160] ; (8016540 <udp_sendto_if+0xd8>)
80164a0: f004 fdb8 bl 801b014 <iprintf>
80164a4: f06f 030f mvn.w r3, #15
80164a8: e042 b.n 8016530 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
80164aa: 687b ldr r3, [r7, #4]
80164ac: 2b00 cmp r3, #0
80164ae: d109 bne.n 80164c4 <udp_sendto_if+0x5c>
80164b0: 4b21 ldr r3, [pc, #132] ; (8016538 <udp_sendto_if+0xd0>)
80164b2: f240 2282 movw r2, #642 ; 0x282
80164b6: 4924 ldr r1, [pc, #144] ; (8016548 <udp_sendto_if+0xe0>)
80164b8: 4821 ldr r0, [pc, #132] ; (8016540 <udp_sendto_if+0xd8>)
80164ba: f004 fdab bl 801b014 <iprintf>
80164be: f06f 030f mvn.w r3, #15
80164c2: e035 b.n 8016530 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG);
80164c4: 6a3b ldr r3, [r7, #32]
80164c6: 2b00 cmp r3, #0
80164c8: d109 bne.n 80164de <udp_sendto_if+0x76>
80164ca: 4b1b ldr r3, [pc, #108] ; (8016538 <udp_sendto_if+0xd0>)
80164cc: f240 2283 movw r2, #643 ; 0x283
80164d0: 491e ldr r1, [pc, #120] ; (801654c <udp_sendto_if+0xe4>)
80164d2: 481b ldr r0, [pc, #108] ; (8016540 <udp_sendto_if+0xd8>)
80164d4: f004 fd9e bl 801b014 <iprintf>
80164d8: f06f 030f mvn.w r3, #15
80164dc: e028 b.n 8016530 <udp_sendto_if+0xc8>
#endif /* LWIP_IPV6 */
#if LWIP_IPV4 && LWIP_IPV6
else
#endif /* LWIP_IPV4 && LWIP_IPV6 */
#if LWIP_IPV4
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80164de: 68fb ldr r3, [r7, #12]
80164e0: 2b00 cmp r3, #0
80164e2: d009 beq.n 80164f8 <udp_sendto_if+0x90>
80164e4: 68fb ldr r3, [r7, #12]
80164e6: 681b ldr r3, [r3, #0]
80164e8: 2b00 cmp r3, #0
80164ea: d005 beq.n 80164f8 <udp_sendto_if+0x90>
ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) {
80164ec: 68fb ldr r3, [r7, #12]
80164ee: 681b ldr r3, [r3, #0]
80164f0: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80164f4: 2be0 cmp r3, #224 ; 0xe0
80164f6: d103 bne.n 8016500 <udp_sendto_if+0x98>
/* if the local_ip is any or multicast
* use the outgoing network interface IP address as source address */
src_ip = netif_ip_addr4(netif);
80164f8: 6a3b ldr r3, [r7, #32]
80164fa: 3304 adds r3, #4
80164fc: 617b str r3, [r7, #20]
80164fe: e00b b.n 8016518 <udp_sendto_if+0xb0>
} else {
/* check if UDP PCB local IP address is correct
* this could be an old address if netif->ip_addr has changed */
if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) {
8016500: 68fb ldr r3, [r7, #12]
8016502: 681a ldr r2, [r3, #0]
8016504: 6a3b ldr r3, [r7, #32]
8016506: 3304 adds r3, #4
8016508: 681b ldr r3, [r3, #0]
801650a: 429a cmp r2, r3
801650c: d002 beq.n 8016514 <udp_sendto_if+0xac>
/* local_ip doesn't match, drop the packet */
return ERR_RTE;
801650e: f06f 0303 mvn.w r3, #3
8016512: e00d b.n 8016530 <udp_sendto_if+0xc8>
}
/* use UDP PCB local IP address as source address */
src_ip = &pcb->local_ip;
8016514: 68fb ldr r3, [r7, #12]
8016516: 617b str r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip);
#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip);
8016518: 887a ldrh r2, [r7, #2]
801651a: 697b ldr r3, [r7, #20]
801651c: 9301 str r3, [sp, #4]
801651e: 6a3b ldr r3, [r7, #32]
8016520: 9300 str r3, [sp, #0]
8016522: 4613 mov r3, r2
8016524: 687a ldr r2, [r7, #4]
8016526: 68b9 ldr r1, [r7, #8]
8016528: 68f8 ldr r0, [r7, #12]
801652a: f000 f811 bl 8016550 <udp_sendto_if_src>
801652e: 4603 mov r3, r0
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
}
8016530: 4618 mov r0, r3
8016532: 3718 adds r7, #24
8016534: 46bd mov sp, r7
8016536: bd80 pop {r7, pc}
8016538: 0801e034 .word 0x0801e034
801653c: 0801e1a8 .word 0x0801e1a8
8016540: 0801e088 .word 0x0801e088
8016544: 0801e1c4 .word 0x0801e1c4
8016548: 0801e1e0 .word 0x0801e1e0
801654c: 0801e200 .word 0x0801e200
08016550 <udp_sendto_if_src>:
/** @ingroup udp_raw
* Same as @ref udp_sendto_if, but with source address */
err_t
udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip)
{
8016550: b580 push {r7, lr}
8016552: b08c sub sp, #48 ; 0x30
8016554: af04 add r7, sp, #16
8016556: 60f8 str r0, [r7, #12]
8016558: 60b9 str r1, [r7, #8]
801655a: 607a str r2, [r7, #4]
801655c: 807b strh r3, [r7, #2]
u8_t ip_proto;
u8_t ttl;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG);
801655e: 68fb ldr r3, [r7, #12]
8016560: 2b00 cmp r3, #0
8016562: d109 bne.n 8016578 <udp_sendto_if_src+0x28>
8016564: 4b65 ldr r3, [pc, #404] ; (80166fc <udp_sendto_if_src+0x1ac>)
8016566: f240 22d1 movw r2, #721 ; 0x2d1
801656a: 4965 ldr r1, [pc, #404] ; (8016700 <udp_sendto_if_src+0x1b0>)
801656c: 4865 ldr r0, [pc, #404] ; (8016704 <udp_sendto_if_src+0x1b4>)
801656e: f004 fd51 bl 801b014 <iprintf>
8016572: f06f 030f mvn.w r3, #15
8016576: e0bc b.n 80166f2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG);
8016578: 68bb ldr r3, [r7, #8]
801657a: 2b00 cmp r3, #0
801657c: d109 bne.n 8016592 <udp_sendto_if_src+0x42>
801657e: 4b5f ldr r3, [pc, #380] ; (80166fc <udp_sendto_if_src+0x1ac>)
8016580: f240 22d2 movw r2, #722 ; 0x2d2
8016584: 4960 ldr r1, [pc, #384] ; (8016708 <udp_sendto_if_src+0x1b8>)
8016586: 485f ldr r0, [pc, #380] ; (8016704 <udp_sendto_if_src+0x1b4>)
8016588: f004 fd44 bl 801b014 <iprintf>
801658c: f06f 030f mvn.w r3, #15
8016590: e0af b.n 80166f2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
8016592: 687b ldr r3, [r7, #4]
8016594: 2b00 cmp r3, #0
8016596: d109 bne.n 80165ac <udp_sendto_if_src+0x5c>
8016598: 4b58 ldr r3, [pc, #352] ; (80166fc <udp_sendto_if_src+0x1ac>)
801659a: f240 22d3 movw r2, #723 ; 0x2d3
801659e: 495b ldr r1, [pc, #364] ; (801670c <udp_sendto_if_src+0x1bc>)
80165a0: 4858 ldr r0, [pc, #352] ; (8016704 <udp_sendto_if_src+0x1b4>)
80165a2: f004 fd37 bl 801b014 <iprintf>
80165a6: f06f 030f mvn.w r3, #15
80165aa: e0a2 b.n 80166f2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG);
80165ac: 6afb ldr r3, [r7, #44] ; 0x2c
80165ae: 2b00 cmp r3, #0
80165b0: d109 bne.n 80165c6 <udp_sendto_if_src+0x76>
80165b2: 4b52 ldr r3, [pc, #328] ; (80166fc <udp_sendto_if_src+0x1ac>)
80165b4: f44f 7235 mov.w r2, #724 ; 0x2d4
80165b8: 4955 ldr r1, [pc, #340] ; (8016710 <udp_sendto_if_src+0x1c0>)
80165ba: 4852 ldr r0, [pc, #328] ; (8016704 <udp_sendto_if_src+0x1b4>)
80165bc: f004 fd2a bl 801b014 <iprintf>
80165c0: f06f 030f mvn.w r3, #15
80165c4: e095 b.n 80166f2 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG);
80165c6: 6abb ldr r3, [r7, #40] ; 0x28
80165c8: 2b00 cmp r3, #0
80165ca: d109 bne.n 80165e0 <udp_sendto_if_src+0x90>
80165cc: 4b4b ldr r3, [pc, #300] ; (80166fc <udp_sendto_if_src+0x1ac>)
80165ce: f240 22d5 movw r2, #725 ; 0x2d5
80165d2: 4950 ldr r1, [pc, #320] ; (8016714 <udp_sendto_if_src+0x1c4>)
80165d4: 484b ldr r0, [pc, #300] ; (8016704 <udp_sendto_if_src+0x1b4>)
80165d6: f004 fd1d bl 801b014 <iprintf>
80165da: f06f 030f mvn.w r3, #15
80165de: e088 b.n 80166f2 <udp_sendto_if_src+0x1a2>
return ERR_VAL;
}
#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */
/* if the PCB is not yet bound to a port, bind it here */
if (pcb->local_port == 0) {
80165e0: 68fb ldr r3, [r7, #12]
80165e2: 8a5b ldrh r3, [r3, #18]
80165e4: 2b00 cmp r3, #0
80165e6: d10f bne.n 8016608 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
80165e8: 68f9 ldr r1, [r7, #12]
80165ea: 68fb ldr r3, [r7, #12]
80165ec: 8a5b ldrh r3, [r3, #18]
80165ee: 461a mov r2, r3
80165f0: 68f8 ldr r0, [r7, #12]
80165f2: f000 f893 bl 801671c <udp_bind>
80165f6: 4603 mov r3, r0
80165f8: 76fb strb r3, [r7, #27]
if (err != ERR_OK) {
80165fa: f997 301b ldrsb.w r3, [r7, #27]
80165fe: 2b00 cmp r3, #0
8016600: d002 beq.n 8016608 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
return err;
8016602: f997 301b ldrsb.w r3, [r7, #27]
8016606: e074 b.n 80166f2 <udp_sendto_if_src+0x1a2>
}
}
/* packet too large to add a UDP header without causing an overflow? */
if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) {
8016608: 68bb ldr r3, [r7, #8]
801660a: 891b ldrh r3, [r3, #8]
801660c: f64f 72f7 movw r2, #65527 ; 0xfff7
8016610: 4293 cmp r3, r2
8016612: d902 bls.n 801661a <udp_sendto_if_src+0xca>
return ERR_MEM;
8016614: f04f 33ff mov.w r3, #4294967295
8016618: e06b b.n 80166f2 <udp_sendto_if_src+0x1a2>
}
/* not enough space to add an UDP header to first pbuf in given p chain? */
if (pbuf_add_header(p, UDP_HLEN)) {
801661a: 2108 movs r1, #8
801661c: 68b8 ldr r0, [r7, #8]
801661e: f7f9 ff4d bl 80104bc <pbuf_add_header>
8016622: 4603 mov r3, r0
8016624: 2b00 cmp r3, #0
8016626: d015 beq.n 8016654 <udp_sendto_if_src+0x104>
/* allocate header in a separate new pbuf */
q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
8016628: f44f 7220 mov.w r2, #640 ; 0x280
801662c: 2108 movs r1, #8
801662e: 2022 movs r0, #34 ; 0x22
8016630: f7f9 fcfa bl 8010028 <pbuf_alloc>
8016634: 61f8 str r0, [r7, #28]
/* new header pbuf could not be allocated? */
if (q == NULL) {
8016636: 69fb ldr r3, [r7, #28]
8016638: 2b00 cmp r3, #0
801663a: d102 bne.n 8016642 <udp_sendto_if_src+0xf2>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
return ERR_MEM;
801663c: f04f 33ff mov.w r3, #4294967295
8016640: e057 b.n 80166f2 <udp_sendto_if_src+0x1a2>
}
if (p->tot_len != 0) {
8016642: 68bb ldr r3, [r7, #8]
8016644: 891b ldrh r3, [r3, #8]
8016646: 2b00 cmp r3, #0
8016648: d006 beq.n 8016658 <udp_sendto_if_src+0x108>
/* chain header q in front of given pbuf p (only if p contains data) */
pbuf_chain(q, p);
801664a: 68b9 ldr r1, [r7, #8]
801664c: 69f8 ldr r0, [r7, #28]
801664e: f7fa f8ef bl 8010830 <pbuf_chain>
8016652: e001 b.n 8016658 <udp_sendto_if_src+0x108>
LWIP_DEBUGF(UDP_DEBUG,
("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
} else {
/* adding space for header within p succeeded */
/* first pbuf q equals given pbuf */
q = p;
8016654: 68bb ldr r3, [r7, #8]
8016656: 61fb str r3, [r7, #28]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
}
LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
8016658: 69fb ldr r3, [r7, #28]
801665a: 895b ldrh r3, [r3, #10]
801665c: 2b07 cmp r3, #7
801665e: d806 bhi.n 801666e <udp_sendto_if_src+0x11e>
8016660: 4b26 ldr r3, [pc, #152] ; (80166fc <udp_sendto_if_src+0x1ac>)
8016662: f240 320e movw r2, #782 ; 0x30e
8016666: 492c ldr r1, [pc, #176] ; (8016718 <udp_sendto_if_src+0x1c8>)
8016668: 4826 ldr r0, [pc, #152] ; (8016704 <udp_sendto_if_src+0x1b4>)
801666a: f004 fcd3 bl 801b014 <iprintf>
(q->len >= sizeof(struct udp_hdr)));
/* q now represents the packet to be sent */
udphdr = (struct udp_hdr *)q->payload;
801666e: 69fb ldr r3, [r7, #28]
8016670: 685b ldr r3, [r3, #4]
8016672: 617b str r3, [r7, #20]
udphdr->src = lwip_htons(pcb->local_port);
8016674: 68fb ldr r3, [r7, #12]
8016676: 8a5b ldrh r3, [r3, #18]
8016678: 4618 mov r0, r3
801667a: f7f8 fc01 bl 800ee80 <lwip_htons>
801667e: 4603 mov r3, r0
8016680: 461a mov r2, r3
8016682: 697b ldr r3, [r7, #20]
8016684: 801a strh r2, [r3, #0]
udphdr->dest = lwip_htons(dst_port);
8016686: 887b ldrh r3, [r7, #2]
8016688: 4618 mov r0, r3
801668a: f7f8 fbf9 bl 800ee80 <lwip_htons>
801668e: 4603 mov r3, r0
8016690: 461a mov r2, r3
8016692: 697b ldr r3, [r7, #20]
8016694: 805a strh r2, [r3, #2]
/* in UDP, 0 checksum means 'no checksum' */
udphdr->chksum = 0x0000;
8016696: 697b ldr r3, [r7, #20]
8016698: 2200 movs r2, #0
801669a: 719a strb r2, [r3, #6]
801669c: 2200 movs r2, #0
801669e: 71da strb r2, [r3, #7]
ip_proto = IP_PROTO_UDPLITE;
} else
#endif /* LWIP_UDPLITE */
{ /* UDP */
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
udphdr->len = lwip_htons(q->tot_len);
80166a0: 69fb ldr r3, [r7, #28]
80166a2: 891b ldrh r3, [r3, #8]
80166a4: 4618 mov r0, r3
80166a6: f7f8 fbeb bl 800ee80 <lwip_htons>
80166aa: 4603 mov r3, r0
80166ac: 461a mov r2, r3
80166ae: 697b ldr r3, [r7, #20]
80166b0: 809a strh r2, [r3, #4]
}
udphdr->chksum = udpchksum;
}
}
#endif /* CHECKSUM_GEN_UDP */
ip_proto = IP_PROTO_UDP;
80166b2: 2311 movs r3, #17
80166b4: 74fb strb r3, [r7, #19]
/* Determine TTL to use */
#if LWIP_MULTICAST_TX_OPTIONS
ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl);
#else /* LWIP_MULTICAST_TX_OPTIONS */
ttl = pcb->ttl;
80166b6: 68fb ldr r3, [r7, #12]
80166b8: 7adb ldrb r3, [r3, #11]
80166ba: 74bb strb r3, [r7, #18]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto));
/* output to IP */
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif);
80166bc: 68fb ldr r3, [r7, #12]
80166be: 7a9b ldrb r3, [r3, #10]
80166c0: 7cb9 ldrb r1, [r7, #18]
80166c2: 6aba ldr r2, [r7, #40] ; 0x28
80166c4: 9202 str r2, [sp, #8]
80166c6: 7cfa ldrb r2, [r7, #19]
80166c8: 9201 str r2, [sp, #4]
80166ca: 9300 str r3, [sp, #0]
80166cc: 460b mov r3, r1
80166ce: 687a ldr r2, [r7, #4]
80166d0: 6af9 ldr r1, [r7, #44] ; 0x2c
80166d2: 69f8 ldr r0, [r7, #28]
80166d4: f003 fb48 bl 8019d68 <ip4_output_if_src>
80166d8: 4603 mov r3, r0
80166da: 76fb strb r3, [r7, #27]
/* @todo: must this be increased even if error occurred? */
MIB2_STATS_INC(mib2.udpoutdatagrams);
/* did we chain a separate header pbuf earlier? */
if (q != p) {
80166dc: 69fa ldr r2, [r7, #28]
80166de: 68bb ldr r3, [r7, #8]
80166e0: 429a cmp r2, r3
80166e2: d004 beq.n 80166ee <udp_sendto_if_src+0x19e>
/* free the header pbuf */
pbuf_free(q);
80166e4: 69f8 ldr r0, [r7, #28]
80166e6: f7f9 ff7f bl 80105e8 <pbuf_free>
q = NULL;
80166ea: 2300 movs r3, #0
80166ec: 61fb str r3, [r7, #28]
/* p is still referenced by the caller, and will live on */
}
UDP_STATS_INC(udp.xmit);
return err;
80166ee: f997 301b ldrsb.w r3, [r7, #27]
}
80166f2: 4618 mov r0, r3
80166f4: 3720 adds r7, #32
80166f6: 46bd mov sp, r7
80166f8: bd80 pop {r7, pc}
80166fa: bf00 nop
80166fc: 0801e034 .word 0x0801e034
8016700: 0801e220 .word 0x0801e220
8016704: 0801e088 .word 0x0801e088
8016708: 0801e240 .word 0x0801e240
801670c: 0801e260 .word 0x0801e260
8016710: 0801e284 .word 0x0801e284
8016714: 0801e2a8 .word 0x0801e2a8
8016718: 0801e2cc .word 0x0801e2cc
0801671c <udp_bind>:
*
* @see udp_disconnect()
*/
err_t
udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
801671c: b580 push {r7, lr}
801671e: b086 sub sp, #24
8016720: af00 add r7, sp, #0
8016722: 60f8 str r0, [r7, #12]
8016724: 60b9 str r1, [r7, #8]
8016726: 4613 mov r3, r2
8016728: 80fb strh r3, [r7, #6]
LWIP_ASSERT_CORE_LOCKED();
#if LWIP_IPV4
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
801672a: 68bb ldr r3, [r7, #8]
801672c: 2b00 cmp r3, #0
801672e: d101 bne.n 8016734 <udp_bind+0x18>
ipaddr = IP4_ADDR_ANY;
8016730: 4b39 ldr r3, [pc, #228] ; (8016818 <udp_bind+0xfc>)
8016732: 60bb str r3, [r7, #8]
}
#else /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
#endif /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
8016734: 68fb ldr r3, [r7, #12]
8016736: 2b00 cmp r3, #0
8016738: d109 bne.n 801674e <udp_bind+0x32>
801673a: 4b38 ldr r3, [pc, #224] ; (801681c <udp_bind+0x100>)
801673c: f240 32b7 movw r2, #951 ; 0x3b7
8016740: 4937 ldr r1, [pc, #220] ; (8016820 <udp_bind+0x104>)
8016742: 4838 ldr r0, [pc, #224] ; (8016824 <udp_bind+0x108>)
8016744: f004 fc66 bl 801b014 <iprintf>
8016748: f06f 030f mvn.w r3, #15
801674c: e060 b.n 8016810 <udp_bind+0xf4>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
rebind = 0;
801674e: 2300 movs r3, #0
8016750: 74fb strb r3, [r7, #19]
/* Check for double bind and rebind of the same pcb */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016752: 4b35 ldr r3, [pc, #212] ; (8016828 <udp_bind+0x10c>)
8016754: 681b ldr r3, [r3, #0]
8016756: 617b str r3, [r7, #20]
8016758: e009 b.n 801676e <udp_bind+0x52>
/* is this UDP PCB already on active list? */
if (pcb == ipcb) {
801675a: 68fa ldr r2, [r7, #12]
801675c: 697b ldr r3, [r7, #20]
801675e: 429a cmp r2, r3
8016760: d102 bne.n 8016768 <udp_bind+0x4c>
rebind = 1;
8016762: 2301 movs r3, #1
8016764: 74fb strb r3, [r7, #19]
break;
8016766: e005 b.n 8016774 <udp_bind+0x58>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016768: 697b ldr r3, [r7, #20]
801676a: 68db ldr r3, [r3, #12]
801676c: 617b str r3, [r7, #20]
801676e: 697b ldr r3, [r7, #20]
8016770: 2b00 cmp r3, #0
8016772: d1f2 bne.n 801675a <udp_bind+0x3e>
ipaddr = &zoned_ipaddr;
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
/* no port specified? */
if (port == 0) {
8016774: 88fb ldrh r3, [r7, #6]
8016776: 2b00 cmp r3, #0
8016778: d109 bne.n 801678e <udp_bind+0x72>
port = udp_new_port();
801677a: f7ff fcc5 bl 8016108 <udp_new_port>
801677e: 4603 mov r3, r0
8016780: 80fb strh r3, [r7, #6]
if (port == 0) {
8016782: 88fb ldrh r3, [r7, #6]
8016784: 2b00 cmp r3, #0
8016786: d12c bne.n 80167e2 <udp_bind+0xc6>
/* no more ports available in local range */
LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
return ERR_USE;
8016788: f06f 0307 mvn.w r3, #7
801678c: e040 b.n 8016810 <udp_bind+0xf4>
}
} else {
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
801678e: 4b26 ldr r3, [pc, #152] ; (8016828 <udp_bind+0x10c>)
8016790: 681b ldr r3, [r3, #0]
8016792: 617b str r3, [r7, #20]
8016794: e022 b.n 80167dc <udp_bind+0xc0>
if (pcb != ipcb) {
8016796: 68fa ldr r2, [r7, #12]
8016798: 697b ldr r3, [r7, #20]
801679a: 429a cmp r2, r3
801679c: d01b beq.n 80167d6 <udp_bind+0xba>
if (!ip_get_option(pcb, SOF_REUSEADDR) ||
!ip_get_option(ipcb, SOF_REUSEADDR))
#endif /* SO_REUSE */
{
/* port matches that of PCB in list and REUSEADDR not set -> reject */
if ((ipcb->local_port == port) &&
801679e: 697b ldr r3, [r7, #20]
80167a0: 8a5b ldrh r3, [r3, #18]
80167a2: 88fa ldrh r2, [r7, #6]
80167a4: 429a cmp r2, r3
80167a6: d116 bne.n 80167d6 <udp_bind+0xba>
/* IP address matches or any IP used? */
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167a8: 697b ldr r3, [r7, #20]
80167aa: 681a ldr r2, [r3, #0]
80167ac: 68bb ldr r3, [r7, #8]
80167ae: 681b ldr r3, [r3, #0]
if ((ipcb->local_port == port) &&
80167b0: 429a cmp r2, r3
80167b2: d00d beq.n 80167d0 <udp_bind+0xb4>
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167b4: 68bb ldr r3, [r7, #8]
80167b6: 2b00 cmp r3, #0
80167b8: d00a beq.n 80167d0 <udp_bind+0xb4>
80167ba: 68bb ldr r3, [r7, #8]
80167bc: 681b ldr r3, [r3, #0]
80167be: 2b00 cmp r3, #0
80167c0: d006 beq.n 80167d0 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
80167c2: 697b ldr r3, [r7, #20]
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167c4: 2b00 cmp r3, #0
80167c6: d003 beq.n 80167d0 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
80167c8: 697b ldr r3, [r7, #20]
80167ca: 681b ldr r3, [r3, #0]
80167cc: 2b00 cmp r3, #0
80167ce: d102 bne.n 80167d6 <udp_bind+0xba>
/* other PCB already binds to this local IP and port */
LWIP_DEBUGF(UDP_DEBUG,
("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
return ERR_USE;
80167d0: f06f 0307 mvn.w r3, #7
80167d4: e01c b.n 8016810 <udp_bind+0xf4>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80167d6: 697b ldr r3, [r7, #20]
80167d8: 68db ldr r3, [r3, #12]
80167da: 617b str r3, [r7, #20]
80167dc: 697b ldr r3, [r7, #20]
80167de: 2b00 cmp r3, #0
80167e0: d1d9 bne.n 8016796 <udp_bind+0x7a>
}
}
}
}
ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
80167e2: 68bb ldr r3, [r7, #8]
80167e4: 2b00 cmp r3, #0
80167e6: d002 beq.n 80167ee <udp_bind+0xd2>
80167e8: 68bb ldr r3, [r7, #8]
80167ea: 681b ldr r3, [r3, #0]
80167ec: e000 b.n 80167f0 <udp_bind+0xd4>
80167ee: 2300 movs r3, #0
80167f0: 68fa ldr r2, [r7, #12]
80167f2: 6013 str r3, [r2, #0]
pcb->local_port = port;
80167f4: 68fb ldr r3, [r7, #12]
80167f6: 88fa ldrh r2, [r7, #6]
80167f8: 825a strh r2, [r3, #18]
mib2_udp_bind(pcb);
/* pcb not active yet? */
if (rebind == 0) {
80167fa: 7cfb ldrb r3, [r7, #19]
80167fc: 2b00 cmp r3, #0
80167fe: d106 bne.n 801680e <udp_bind+0xf2>
/* place the PCB on the active list if not already there */
pcb->next = udp_pcbs;
8016800: 4b09 ldr r3, [pc, #36] ; (8016828 <udp_bind+0x10c>)
8016802: 681a ldr r2, [r3, #0]
8016804: 68fb ldr r3, [r7, #12]
8016806: 60da str r2, [r3, #12]
udp_pcbs = pcb;
8016808: 4a07 ldr r2, [pc, #28] ; (8016828 <udp_bind+0x10c>)
801680a: 68fb ldr r3, [r7, #12]
801680c: 6013 str r3, [r2, #0]
}
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
return ERR_OK;
801680e: 2300 movs r3, #0
}
8016810: 4618 mov r0, r3
8016812: 3718 adds r7, #24
8016814: 46bd mov sp, r7
8016816: bd80 pop {r7, pc}
8016818: 08020e68 .word 0x08020e68
801681c: 0801e034 .word 0x0801e034
8016820: 0801e2fc .word 0x0801e2fc
8016824: 0801e088 .word 0x0801e088
8016828: 2000f5d8 .word 0x2000f5d8
0801682c <udp_connect>:
*
* @see udp_disconnect()
*/
err_t
udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
801682c: b580 push {r7, lr}
801682e: b086 sub sp, #24
8016830: af00 add r7, sp, #0
8016832: 60f8 str r0, [r7, #12]
8016834: 60b9 str r1, [r7, #8]
8016836: 4613 mov r3, r2
8016838: 80fb strh r3, [r7, #6]
struct udp_pcb *ipcb;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
801683a: 68fb ldr r3, [r7, #12]
801683c: 2b00 cmp r3, #0
801683e: d109 bne.n 8016854 <udp_connect+0x28>
8016840: 4b2c ldr r3, [pc, #176] ; (80168f4 <udp_connect+0xc8>)
8016842: f240 4235 movw r2, #1077 ; 0x435
8016846: 492c ldr r1, [pc, #176] ; (80168f8 <udp_connect+0xcc>)
8016848: 482c ldr r0, [pc, #176] ; (80168fc <udp_connect+0xd0>)
801684a: f004 fbe3 bl 801b014 <iprintf>
801684e: f06f 030f mvn.w r3, #15
8016852: e04b b.n 80168ec <udp_connect+0xc0>
LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
8016854: 68bb ldr r3, [r7, #8]
8016856: 2b00 cmp r3, #0
8016858: d109 bne.n 801686e <udp_connect+0x42>
801685a: 4b26 ldr r3, [pc, #152] ; (80168f4 <udp_connect+0xc8>)
801685c: f240 4236 movw r2, #1078 ; 0x436
8016860: 4927 ldr r1, [pc, #156] ; (8016900 <udp_connect+0xd4>)
8016862: 4826 ldr r0, [pc, #152] ; (80168fc <udp_connect+0xd0>)
8016864: f004 fbd6 bl 801b014 <iprintf>
8016868: f06f 030f mvn.w r3, #15
801686c: e03e b.n 80168ec <udp_connect+0xc0>
if (pcb->local_port == 0) {
801686e: 68fb ldr r3, [r7, #12]
8016870: 8a5b ldrh r3, [r3, #18]
8016872: 2b00 cmp r3, #0
8016874: d10f bne.n 8016896 <udp_connect+0x6a>
err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
8016876: 68f9 ldr r1, [r7, #12]
8016878: 68fb ldr r3, [r7, #12]
801687a: 8a5b ldrh r3, [r3, #18]
801687c: 461a mov r2, r3
801687e: 68f8 ldr r0, [r7, #12]
8016880: f7ff ff4c bl 801671c <udp_bind>
8016884: 4603 mov r3, r0
8016886: 74fb strb r3, [r7, #19]
if (err != ERR_OK) {
8016888: f997 3013 ldrsb.w r3, [r7, #19]
801688c: 2b00 cmp r3, #0
801688e: d002 beq.n 8016896 <udp_connect+0x6a>
return err;
8016890: f997 3013 ldrsb.w r3, [r7, #19]
8016894: e02a b.n 80168ec <udp_connect+0xc0>
}
}
ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
8016896: 68bb ldr r3, [r7, #8]
8016898: 2b00 cmp r3, #0
801689a: d002 beq.n 80168a2 <udp_connect+0x76>
801689c: 68bb ldr r3, [r7, #8]
801689e: 681b ldr r3, [r3, #0]
80168a0: e000 b.n 80168a4 <udp_connect+0x78>
80168a2: 2300 movs r3, #0
80168a4: 68fa ldr r2, [r7, #12]
80168a6: 6053 str r3, [r2, #4]
ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
pcb->remote_port = port;
80168a8: 68fb ldr r3, [r7, #12]
80168aa: 88fa ldrh r2, [r7, #6]
80168ac: 829a strh r2, [r3, #20]
pcb->flags |= UDP_FLAGS_CONNECTED;
80168ae: 68fb ldr r3, [r7, #12]
80168b0: 7c1b ldrb r3, [r3, #16]
80168b2: f043 0304 orr.w r3, r3, #4
80168b6: b2da uxtb r2, r3
80168b8: 68fb ldr r3, [r7, #12]
80168ba: 741a strb r2, [r3, #16]
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
/* Insert UDP PCB into the list of active UDP PCBs. */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80168bc: 4b11 ldr r3, [pc, #68] ; (8016904 <udp_connect+0xd8>)
80168be: 681b ldr r3, [r3, #0]
80168c0: 617b str r3, [r7, #20]
80168c2: e008 b.n 80168d6 <udp_connect+0xaa>
if (pcb == ipcb) {
80168c4: 68fa ldr r2, [r7, #12]
80168c6: 697b ldr r3, [r7, #20]
80168c8: 429a cmp r2, r3
80168ca: d101 bne.n 80168d0 <udp_connect+0xa4>
/* already on the list, just return */
return ERR_OK;
80168cc: 2300 movs r3, #0
80168ce: e00d b.n 80168ec <udp_connect+0xc0>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80168d0: 697b ldr r3, [r7, #20]
80168d2: 68db ldr r3, [r3, #12]
80168d4: 617b str r3, [r7, #20]
80168d6: 697b ldr r3, [r7, #20]
80168d8: 2b00 cmp r3, #0
80168da: d1f3 bne.n 80168c4 <udp_connect+0x98>
}
}
/* PCB not yet on the list, add PCB now */
pcb->next = udp_pcbs;
80168dc: 4b09 ldr r3, [pc, #36] ; (8016904 <udp_connect+0xd8>)
80168de: 681a ldr r2, [r3, #0]
80168e0: 68fb ldr r3, [r7, #12]
80168e2: 60da str r2, [r3, #12]
udp_pcbs = pcb;
80168e4: 4a07 ldr r2, [pc, #28] ; (8016904 <udp_connect+0xd8>)
80168e6: 68fb ldr r3, [r7, #12]
80168e8: 6013 str r3, [r2, #0]
return ERR_OK;
80168ea: 2300 movs r3, #0
}
80168ec: 4618 mov r0, r3
80168ee: 3718 adds r7, #24
80168f0: 46bd mov sp, r7
80168f2: bd80 pop {r7, pc}
80168f4: 0801e034 .word 0x0801e034
80168f8: 0801e314 .word 0x0801e314
80168fc: 0801e088 .word 0x0801e088
8016900: 0801e330 .word 0x0801e330
8016904: 2000f5d8 .word 0x2000f5d8
08016908 <udp_recv>:
* @param recv function pointer of the callback function
* @param recv_arg additional argument to pass to the callback function
*/
void
udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
{
8016908: b580 push {r7, lr}
801690a: b084 sub sp, #16
801690c: af00 add r7, sp, #0
801690e: 60f8 str r0, [r7, #12]
8016910: 60b9 str r1, [r7, #8]
8016912: 607a str r2, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
8016914: 68fb ldr r3, [r7, #12]
8016916: 2b00 cmp r3, #0
8016918: d107 bne.n 801692a <udp_recv+0x22>
801691a: 4b08 ldr r3, [pc, #32] ; (801693c <udp_recv+0x34>)
801691c: f240 428a movw r2, #1162 ; 0x48a
8016920: 4907 ldr r1, [pc, #28] ; (8016940 <udp_recv+0x38>)
8016922: 4808 ldr r0, [pc, #32] ; (8016944 <udp_recv+0x3c>)
8016924: f004 fb76 bl 801b014 <iprintf>
8016928: e005 b.n 8016936 <udp_recv+0x2e>
/* remember recv() callback and user data */
pcb->recv = recv;
801692a: 68fb ldr r3, [r7, #12]
801692c: 68ba ldr r2, [r7, #8]
801692e: 619a str r2, [r3, #24]
pcb->recv_arg = recv_arg;
8016930: 68fb ldr r3, [r7, #12]
8016932: 687a ldr r2, [r7, #4]
8016934: 61da str r2, [r3, #28]
}
8016936: 3710 adds r7, #16
8016938: 46bd mov sp, r7
801693a: bd80 pop {r7, pc}
801693c: 0801e034 .word 0x0801e034
8016940: 0801e368 .word 0x0801e368
8016944: 0801e088 .word 0x0801e088
08016948 <udp_remove>:
*
* @see udp_new()
*/
void
udp_remove(struct udp_pcb *pcb)
{
8016948: b580 push {r7, lr}
801694a: b084 sub sp, #16
801694c: af00 add r7, sp, #0
801694e: 6078 str r0, [r7, #4]
struct udp_pcb *pcb2;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
8016950: 687b ldr r3, [r7, #4]
8016952: 2b00 cmp r3, #0
8016954: d107 bne.n 8016966 <udp_remove+0x1e>
8016956: 4b19 ldr r3, [pc, #100] ; (80169bc <udp_remove+0x74>)
8016958: f240 42a1 movw r2, #1185 ; 0x4a1
801695c: 4918 ldr r1, [pc, #96] ; (80169c0 <udp_remove+0x78>)
801695e: 4819 ldr r0, [pc, #100] ; (80169c4 <udp_remove+0x7c>)
8016960: f004 fb58 bl 801b014 <iprintf>
8016964: e026 b.n 80169b4 <udp_remove+0x6c>
mib2_udp_unbind(pcb);
/* pcb to be removed is first in list? */
if (udp_pcbs == pcb) {
8016966: 4b18 ldr r3, [pc, #96] ; (80169c8 <udp_remove+0x80>)
8016968: 681b ldr r3, [r3, #0]
801696a: 687a ldr r2, [r7, #4]
801696c: 429a cmp r2, r3
801696e: d105 bne.n 801697c <udp_remove+0x34>
/* make list start at 2nd pcb */
udp_pcbs = udp_pcbs->next;
8016970: 4b15 ldr r3, [pc, #84] ; (80169c8 <udp_remove+0x80>)
8016972: 681b ldr r3, [r3, #0]
8016974: 68db ldr r3, [r3, #12]
8016976: 4a14 ldr r2, [pc, #80] ; (80169c8 <udp_remove+0x80>)
8016978: 6013 str r3, [r2, #0]
801697a: e017 b.n 80169ac <udp_remove+0x64>
/* pcb not 1st in list */
} else {
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
801697c: 4b12 ldr r3, [pc, #72] ; (80169c8 <udp_remove+0x80>)
801697e: 681b ldr r3, [r3, #0]
8016980: 60fb str r3, [r7, #12]
8016982: e010 b.n 80169a6 <udp_remove+0x5e>
/* find pcb in udp_pcbs list */
if (pcb2->next != NULL && pcb2->next == pcb) {
8016984: 68fb ldr r3, [r7, #12]
8016986: 68db ldr r3, [r3, #12]
8016988: 2b00 cmp r3, #0
801698a: d009 beq.n 80169a0 <udp_remove+0x58>
801698c: 68fb ldr r3, [r7, #12]
801698e: 68db ldr r3, [r3, #12]
8016990: 687a ldr r2, [r7, #4]
8016992: 429a cmp r2, r3
8016994: d104 bne.n 80169a0 <udp_remove+0x58>
/* remove pcb from list */
pcb2->next = pcb->next;
8016996: 687b ldr r3, [r7, #4]
8016998: 68da ldr r2, [r3, #12]
801699a: 68fb ldr r3, [r7, #12]
801699c: 60da str r2, [r3, #12]
break;
801699e: e005 b.n 80169ac <udp_remove+0x64>
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
80169a0: 68fb ldr r3, [r7, #12]
80169a2: 68db ldr r3, [r3, #12]
80169a4: 60fb str r3, [r7, #12]
80169a6: 68fb ldr r3, [r7, #12]
80169a8: 2b00 cmp r3, #0
80169aa: d1eb bne.n 8016984 <udp_remove+0x3c>
}
}
}
memp_free(MEMP_UDP_PCB, pcb);
80169ac: 6879 ldr r1, [r7, #4]
80169ae: 2000 movs r0, #0
80169b0: f7f8 ff6e bl 800f890 <memp_free>
}
80169b4: 3710 adds r7, #16
80169b6: 46bd mov sp, r7
80169b8: bd80 pop {r7, pc}
80169ba: bf00 nop
80169bc: 0801e034 .word 0x0801e034
80169c0: 0801e380 .word 0x0801e380
80169c4: 0801e088 .word 0x0801e088
80169c8: 2000f5d8 .word 0x2000f5d8
080169cc <udp_new>:
*
* @see udp_remove()
*/
struct udp_pcb *
udp_new(void)
{
80169cc: b580 push {r7, lr}
80169ce: b082 sub sp, #8
80169d0: af00 add r7, sp, #0
struct udp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
80169d2: 2000 movs r0, #0
80169d4: f7f8 ff0a bl 800f7ec <memp_malloc>
80169d8: 6078 str r0, [r7, #4]
/* could allocate UDP PCB? */
if (pcb != NULL) {
80169da: 687b ldr r3, [r7, #4]
80169dc: 2b00 cmp r3, #0
80169de: d007 beq.n 80169f0 <udp_new+0x24>
/* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
* which means checksum is generated over the whole datagram per default
* (recommended as default by RFC 3828). */
/* initialize PCB to all zeroes */
memset(pcb, 0, sizeof(struct udp_pcb));
80169e0: 2220 movs r2, #32
80169e2: 2100 movs r1, #0
80169e4: 6878 ldr r0, [r7, #4]
80169e6: f004 fb0d bl 801b004 <memset>
pcb->ttl = UDP_TTL;
80169ea: 687b ldr r3, [r7, #4]
80169ec: 22ff movs r2, #255 ; 0xff
80169ee: 72da strb r2, [r3, #11]
#if LWIP_MULTICAST_TX_OPTIONS
udp_set_multicast_ttl(pcb, UDP_TTL);
#endif /* LWIP_MULTICAST_TX_OPTIONS */
}
return pcb;
80169f0: 687b ldr r3, [r7, #4]
}
80169f2: 4618 mov r0, r3
80169f4: 3708 adds r7, #8
80169f6: 46bd mov sp, r7
80169f8: bd80 pop {r7, pc}
...
080169fc <udp_netif_ip_addr_changed>:
*
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change
*/
void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
80169fc: b480 push {r7}
80169fe: b085 sub sp, #20
8016a00: af00 add r7, sp, #0
8016a02: 6078 str r0, [r7, #4]
8016a04: 6039 str r1, [r7, #0]
struct udp_pcb *upcb;
if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
8016a06: 687b ldr r3, [r7, #4]
8016a08: 2b00 cmp r3, #0
8016a0a: d01e beq.n 8016a4a <udp_netif_ip_addr_changed+0x4e>
8016a0c: 687b ldr r3, [r7, #4]
8016a0e: 681b ldr r3, [r3, #0]
8016a10: 2b00 cmp r3, #0
8016a12: d01a beq.n 8016a4a <udp_netif_ip_addr_changed+0x4e>
8016a14: 683b ldr r3, [r7, #0]
8016a16: 2b00 cmp r3, #0
8016a18: d017 beq.n 8016a4a <udp_netif_ip_addr_changed+0x4e>
8016a1a: 683b ldr r3, [r7, #0]
8016a1c: 681b ldr r3, [r3, #0]
8016a1e: 2b00 cmp r3, #0
8016a20: d013 beq.n 8016a4a <udp_netif_ip_addr_changed+0x4e>
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
8016a22: 4b0d ldr r3, [pc, #52] ; (8016a58 <udp_netif_ip_addr_changed+0x5c>)
8016a24: 681b ldr r3, [r3, #0]
8016a26: 60fb str r3, [r7, #12]
8016a28: e00c b.n 8016a44 <udp_netif_ip_addr_changed+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
8016a2a: 68fb ldr r3, [r7, #12]
8016a2c: 681a ldr r2, [r3, #0]
8016a2e: 687b ldr r3, [r7, #4]
8016a30: 681b ldr r3, [r3, #0]
8016a32: 429a cmp r2, r3
8016a34: d103 bne.n 8016a3e <udp_netif_ip_addr_changed+0x42>
/* The PCB is bound to the old ipaddr and
* is set to bound to the new one instead */
ip_addr_copy(upcb->local_ip, *new_addr);
8016a36: 683b ldr r3, [r7, #0]
8016a38: 681a ldr r2, [r3, #0]
8016a3a: 68fb ldr r3, [r7, #12]
8016a3c: 601a str r2, [r3, #0]
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
8016a3e: 68fb ldr r3, [r7, #12]
8016a40: 68db ldr r3, [r3, #12]
8016a42: 60fb str r3, [r7, #12]
8016a44: 68fb ldr r3, [r7, #12]
8016a46: 2b00 cmp r3, #0
8016a48: d1ef bne.n 8016a2a <udp_netif_ip_addr_changed+0x2e>
}
}
}
}
8016a4a: bf00 nop
8016a4c: 3714 adds r7, #20
8016a4e: 46bd mov sp, r7
8016a50: f85d 7b04 ldr.w r7, [sp], #4
8016a54: 4770 bx lr
8016a56: bf00 nop
8016a58: 2000f5d8 .word 0x2000f5d8
08016a5c <dhcp_inc_pcb_refcount>:
static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out);
/** Ensure DHCP PCB is allocated and bound */
static err_t
dhcp_inc_pcb_refcount(void)
{
8016a5c: b580 push {r7, lr}
8016a5e: af00 add r7, sp, #0
if (dhcp_pcb_refcount == 0) {
8016a60: 4b20 ldr r3, [pc, #128] ; (8016ae4 <dhcp_inc_pcb_refcount+0x88>)
8016a62: 781b ldrb r3, [r3, #0]
8016a64: 2b00 cmp r3, #0
8016a66: d133 bne.n 8016ad0 <dhcp_inc_pcb_refcount+0x74>
LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL);
8016a68: 4b1f ldr r3, [pc, #124] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016a6a: 681b ldr r3, [r3, #0]
8016a6c: 2b00 cmp r3, #0
8016a6e: d005 beq.n 8016a7c <dhcp_inc_pcb_refcount+0x20>
8016a70: 4b1e ldr r3, [pc, #120] ; (8016aec <dhcp_inc_pcb_refcount+0x90>)
8016a72: 22e5 movs r2, #229 ; 0xe5
8016a74: 491e ldr r1, [pc, #120] ; (8016af0 <dhcp_inc_pcb_refcount+0x94>)
8016a76: 481f ldr r0, [pc, #124] ; (8016af4 <dhcp_inc_pcb_refcount+0x98>)
8016a78: f004 facc bl 801b014 <iprintf>
/* allocate UDP PCB */
dhcp_pcb = udp_new();
8016a7c: f7ff ffa6 bl 80169cc <udp_new>
8016a80: 4602 mov r2, r0
8016a82: 4b19 ldr r3, [pc, #100] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016a84: 601a str r2, [r3, #0]
if (dhcp_pcb == NULL) {
8016a86: 4b18 ldr r3, [pc, #96] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016a88: 681b ldr r3, [r3, #0]
8016a8a: 2b00 cmp r3, #0
8016a8c: d102 bne.n 8016a94 <dhcp_inc_pcb_refcount+0x38>
return ERR_MEM;
8016a8e: f04f 33ff mov.w r3, #4294967295
8016a92: e024 b.n 8016ade <dhcp_inc_pcb_refcount+0x82>
}
ip_set_option(dhcp_pcb, SOF_BROADCAST);
8016a94: 4b14 ldr r3, [pc, #80] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016a96: 681b ldr r3, [r3, #0]
8016a98: 7a5a ldrb r2, [r3, #9]
8016a9a: 4b13 ldr r3, [pc, #76] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016a9c: 681b ldr r3, [r3, #0]
8016a9e: f042 0220 orr.w r2, r2, #32
8016aa2: b2d2 uxtb r2, r2
8016aa4: 725a strb r2, [r3, #9]
/* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT);
8016aa6: 4b10 ldr r3, [pc, #64] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016aa8: 681b ldr r3, [r3, #0]
8016aaa: 2244 movs r2, #68 ; 0x44
8016aac: 4912 ldr r1, [pc, #72] ; (8016af8 <dhcp_inc_pcb_refcount+0x9c>)
8016aae: 4618 mov r0, r3
8016ab0: f7ff fe34 bl 801671c <udp_bind>
udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER);
8016ab4: 4b0c ldr r3, [pc, #48] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016ab6: 681b ldr r3, [r3, #0]
8016ab8: 2243 movs r2, #67 ; 0x43
8016aba: 490f ldr r1, [pc, #60] ; (8016af8 <dhcp_inc_pcb_refcount+0x9c>)
8016abc: 4618 mov r0, r3
8016abe: f7ff feb5 bl 801682c <udp_connect>
udp_recv(dhcp_pcb, dhcp_recv, NULL);
8016ac2: 4b09 ldr r3, [pc, #36] ; (8016ae8 <dhcp_inc_pcb_refcount+0x8c>)
8016ac4: 681b ldr r3, [r3, #0]
8016ac6: 2200 movs r2, #0
8016ac8: 490c ldr r1, [pc, #48] ; (8016afc <dhcp_inc_pcb_refcount+0xa0>)
8016aca: 4618 mov r0, r3
8016acc: f7ff ff1c bl 8016908 <udp_recv>
}
dhcp_pcb_refcount++;
8016ad0: 4b04 ldr r3, [pc, #16] ; (8016ae4 <dhcp_inc_pcb_refcount+0x88>)
8016ad2: 781b ldrb r3, [r3, #0]
8016ad4: 3301 adds r3, #1
8016ad6: b2da uxtb r2, r3
8016ad8: 4b02 ldr r3, [pc, #8] ; (8016ae4 <dhcp_inc_pcb_refcount+0x88>)
8016ada: 701a strb r2, [r3, #0]
return ERR_OK;
8016adc: 2300 movs r3, #0
}
8016ade: 4618 mov r0, r3
8016ae0: bd80 pop {r7, pc}
8016ae2: bf00 nop
8016ae4: 20008770 .word 0x20008770
8016ae8: 2000876c .word 0x2000876c
8016aec: 0801e398 .word 0x0801e398
8016af0: 0801e3d0 .word 0x0801e3d0
8016af4: 0801e3f8 .word 0x0801e3f8
8016af8: 08020e68 .word 0x08020e68
8016afc: 080183b9 .word 0x080183b9
08016b00 <dhcp_dec_pcb_refcount>:
/** Free DHCP PCB if the last netif stops using it */
static void
dhcp_dec_pcb_refcount(void)
{
8016b00: b580 push {r7, lr}
8016b02: af00 add r7, sp, #0
LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0));
8016b04: 4b0e ldr r3, [pc, #56] ; (8016b40 <dhcp_dec_pcb_refcount+0x40>)
8016b06: 781b ldrb r3, [r3, #0]
8016b08: 2b00 cmp r3, #0
8016b0a: d105 bne.n 8016b18 <dhcp_dec_pcb_refcount+0x18>
8016b0c: 4b0d ldr r3, [pc, #52] ; (8016b44 <dhcp_dec_pcb_refcount+0x44>)
8016b0e: 22ff movs r2, #255 ; 0xff
8016b10: 490d ldr r1, [pc, #52] ; (8016b48 <dhcp_dec_pcb_refcount+0x48>)
8016b12: 480e ldr r0, [pc, #56] ; (8016b4c <dhcp_dec_pcb_refcount+0x4c>)
8016b14: f004 fa7e bl 801b014 <iprintf>
dhcp_pcb_refcount--;
8016b18: 4b09 ldr r3, [pc, #36] ; (8016b40 <dhcp_dec_pcb_refcount+0x40>)
8016b1a: 781b ldrb r3, [r3, #0]
8016b1c: 3b01 subs r3, #1
8016b1e: b2da uxtb r2, r3
8016b20: 4b07 ldr r3, [pc, #28] ; (8016b40 <dhcp_dec_pcb_refcount+0x40>)
8016b22: 701a strb r2, [r3, #0]
if (dhcp_pcb_refcount == 0) {
8016b24: 4b06 ldr r3, [pc, #24] ; (8016b40 <dhcp_dec_pcb_refcount+0x40>)
8016b26: 781b ldrb r3, [r3, #0]
8016b28: 2b00 cmp r3, #0
8016b2a: d107 bne.n 8016b3c <dhcp_dec_pcb_refcount+0x3c>
udp_remove(dhcp_pcb);
8016b2c: 4b08 ldr r3, [pc, #32] ; (8016b50 <dhcp_dec_pcb_refcount+0x50>)
8016b2e: 681b ldr r3, [r3, #0]
8016b30: 4618 mov r0, r3
8016b32: f7ff ff09 bl 8016948 <udp_remove>
dhcp_pcb = NULL;
8016b36: 4b06 ldr r3, [pc, #24] ; (8016b50 <dhcp_dec_pcb_refcount+0x50>)
8016b38: 2200 movs r2, #0
8016b3a: 601a str r2, [r3, #0]
}
}
8016b3c: bf00 nop
8016b3e: bd80 pop {r7, pc}
8016b40: 20008770 .word 0x20008770
8016b44: 0801e398 .word 0x0801e398
8016b48: 0801e420 .word 0x0801e420
8016b4c: 0801e3f8 .word 0x0801e3f8
8016b50: 2000876c .word 0x2000876c
08016b54 <dhcp_handle_nak>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_nak(struct netif *netif)
{
8016b54: b580 push {r7, lr}
8016b56: b084 sub sp, #16
8016b58: af00 add r7, sp, #0
8016b5a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016b5c: 687b ldr r3, [r7, #4]
8016b5e: 6a5b ldr r3, [r3, #36] ; 0x24
8016b60: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* Change to a defined state - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
8016b62: 210c movs r1, #12
8016b64: 68f8 ldr r0, [r7, #12]
8016b66: f001 f869 bl 8017c3c <dhcp_set_state>
/* remove IP address from interface (must no longer be used, as per RFC2131) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8016b6a: 4b06 ldr r3, [pc, #24] ; (8016b84 <dhcp_handle_nak+0x30>)
8016b6c: 4a05 ldr r2, [pc, #20] ; (8016b84 <dhcp_handle_nak+0x30>)
8016b6e: 4905 ldr r1, [pc, #20] ; (8016b84 <dhcp_handle_nak+0x30>)
8016b70: 6878 ldr r0, [r7, #4]
8016b72: f7f9 f82f bl 800fbd4 <netif_set_addr>
/* We can immediately restart discovery */
dhcp_discover(netif);
8016b76: 6878 ldr r0, [r7, #4]
8016b78: f000 fc5c bl 8017434 <dhcp_discover>
}
8016b7c: bf00 nop
8016b7e: 3710 adds r7, #16
8016b80: 46bd mov sp, r7
8016b82: bd80 pop {r7, pc}
8016b84: 08020e68 .word 0x08020e68
08016b88 <dhcp_check>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_check(struct netif *netif)
{
8016b88: b580 push {r7, lr}
8016b8a: b084 sub sp, #16
8016b8c: af00 add r7, sp, #0
8016b8e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016b90: 687b ldr r3, [r7, #4]
8016b92: 6a5b ldr r3, [r3, #36] ; 0x24
8016b94: 60fb str r3, [r7, #12]
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
(s16_t)netif->name[1]));
dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
8016b96: 2108 movs r1, #8
8016b98: 68f8 ldr r0, [r7, #12]
8016b9a: f001 f84f bl 8017c3c <dhcp_set_state>
/* create an ARP query for the offered IP address, expecting that no host
responds, as the IP address should not be in use. */
result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
8016b9e: 68fb ldr r3, [r7, #12]
8016ba0: 331c adds r3, #28
8016ba2: 2200 movs r2, #0
8016ba4: 4619 mov r1, r3
8016ba6: 6878 ldr r0, [r7, #4]
8016ba8: f002 fb4e bl 8019248 <etharp_query>
8016bac: 4603 mov r3, r0
8016bae: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
}
if (dhcp->tries < 255) {
8016bb0: 68fb ldr r3, [r7, #12]
8016bb2: 799b ldrb r3, [r3, #6]
8016bb4: 2bff cmp r3, #255 ; 0xff
8016bb6: d005 beq.n 8016bc4 <dhcp_check+0x3c>
dhcp->tries++;
8016bb8: 68fb ldr r3, [r7, #12]
8016bba: 799b ldrb r3, [r3, #6]
8016bbc: 3301 adds r3, #1
8016bbe: b2da uxtb r2, r3
8016bc0: 68fb ldr r3, [r7, #12]
8016bc2: 719a strb r2, [r3, #6]
}
msecs = 500;
8016bc4: f44f 73fa mov.w r3, #500 ; 0x1f4
8016bc8: 813b strh r3, [r7, #8]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016bca: 893b ldrh r3, [r7, #8]
8016bcc: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016bd0: 4a06 ldr r2, [pc, #24] ; (8016bec <dhcp_check+0x64>)
8016bd2: fb82 1203 smull r1, r2, r2, r3
8016bd6: 1152 asrs r2, r2, #5
8016bd8: 17db asrs r3, r3, #31
8016bda: 1ad3 subs r3, r2, r3
8016bdc: b29a uxth r2, r3
8016bde: 68fb ldr r3, [r7, #12]
8016be0: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
}
8016be2: bf00 nop
8016be4: 3710 adds r7, #16
8016be6: 46bd mov sp, r7
8016be8: bd80 pop {r7, pc}
8016bea: bf00 nop
8016bec: 10624dd3 .word 0x10624dd3
08016bf0 <dhcp_handle_offer>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in)
{
8016bf0: b580 push {r7, lr}
8016bf2: b084 sub sp, #16
8016bf4: af00 add r7, sp, #0
8016bf6: 6078 str r0, [r7, #4]
8016bf8: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016bfa: 687b ldr r3, [r7, #4]
8016bfc: 6a5b ldr r3, [r3, #36] ; 0x24
8016bfe: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* obtain the server address */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
8016c00: 4b0c ldr r3, [pc, #48] ; (8016c34 <dhcp_handle_offer+0x44>)
8016c02: 789b ldrb r3, [r3, #2]
8016c04: 2b00 cmp r3, #0
8016c06: d011 beq.n 8016c2c <dhcp_handle_offer+0x3c>
dhcp->request_timeout = 0; /* stop timer */
8016c08: 68fb ldr r3, [r7, #12]
8016c0a: 2200 movs r2, #0
8016c0c: 811a strh r2, [r3, #8]
ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
8016c0e: 4b0a ldr r3, [pc, #40] ; (8016c38 <dhcp_handle_offer+0x48>)
8016c10: 689b ldr r3, [r3, #8]
8016c12: 4618 mov r0, r3
8016c14: f7f8 f949 bl 800eeaa <lwip_htonl>
8016c18: 4602 mov r2, r0
8016c1a: 68fb ldr r3, [r7, #12]
8016c1c: 619a str r2, [r3, #24]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
/* remember offered address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
8016c1e: 683b ldr r3, [r7, #0]
8016c20: 691a ldr r2, [r3, #16]
8016c22: 68fb ldr r3, [r7, #12]
8016c24: 61da str r2, [r3, #28]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_select(netif);
8016c26: 6878 ldr r0, [r7, #4]
8016c28: f000 f808 bl 8016c3c <dhcp_select>
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif));
}
}
8016c2c: bf00 nop
8016c2e: 3710 adds r7, #16
8016c30: 46bd mov sp, r7
8016c32: bd80 pop {r7, pc}
8016c34: 2000f5dc .word 0x2000f5dc
8016c38: 2000f5e4 .word 0x2000f5e4
08016c3c <dhcp_select>:
* @param netif the netif under DHCP control
* @return lwIP specific error (see error.h)
*/
static err_t
dhcp_select(struct netif *netif)
{
8016c3c: b5b0 push {r4, r5, r7, lr}
8016c3e: b08a sub sp, #40 ; 0x28
8016c40: af02 add r7, sp, #8
8016c42: 6078 str r0, [r7, #4]
u16_t msecs;
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;);
8016c44: 687b ldr r3, [r7, #4]
8016c46: 2b00 cmp r3, #0
8016c48: d109 bne.n 8016c5e <dhcp_select+0x22>
8016c4a: 4b71 ldr r3, [pc, #452] ; (8016e10 <dhcp_select+0x1d4>)
8016c4c: f240 1277 movw r2, #375 ; 0x177
8016c50: 4970 ldr r1, [pc, #448] ; (8016e14 <dhcp_select+0x1d8>)
8016c52: 4871 ldr r0, [pc, #452] ; (8016e18 <dhcp_select+0x1dc>)
8016c54: f004 f9de bl 801b014 <iprintf>
8016c58: f06f 030f mvn.w r3, #15
8016c5c: e0d3 b.n 8016e06 <dhcp_select+0x1ca>
dhcp = netif_dhcp_data(netif);
8016c5e: 687b ldr r3, [r7, #4]
8016c60: 6a5b ldr r3, [r3, #36] ; 0x24
8016c62: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
8016c64: 69bb ldr r3, [r7, #24]
8016c66: 2b00 cmp r3, #0
8016c68: d109 bne.n 8016c7e <dhcp_select+0x42>
8016c6a: 4b69 ldr r3, [pc, #420] ; (8016e10 <dhcp_select+0x1d4>)
8016c6c: f240 1279 movw r2, #377 ; 0x179
8016c70: 496a ldr r1, [pc, #424] ; (8016e1c <dhcp_select+0x1e0>)
8016c72: 4869 ldr r0, [pc, #420] ; (8016e18 <dhcp_select+0x1dc>)
8016c74: f004 f9ce bl 801b014 <iprintf>
8016c78: f06f 0305 mvn.w r3, #5
8016c7c: e0c3 b.n 8016e06 <dhcp_select+0x1ca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
8016c7e: 2101 movs r1, #1
8016c80: 69b8 ldr r0, [r7, #24]
8016c82: f000 ffdb bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8016c86: f107 030c add.w r3, r7, #12
8016c8a: 2203 movs r2, #3
8016c8c: 69b9 ldr r1, [r7, #24]
8016c8e: 6878 ldr r0, [r7, #4]
8016c90: f001 fc5e bl 8018550 <dhcp_create_msg>
8016c94: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8016c96: 697b ldr r3, [r7, #20]
8016c98: 2b00 cmp r3, #0
8016c9a: f000 8085 beq.w 8016da8 <dhcp_select+0x16c>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8016c9e: 697b ldr r3, [r7, #20]
8016ca0: 685b ldr r3, [r3, #4]
8016ca2: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8016ca4: 89b8 ldrh r0, [r7, #12]
8016ca6: 693b ldr r3, [r7, #16]
8016ca8: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016cac: 2302 movs r3, #2
8016cae: 2239 movs r2, #57 ; 0x39
8016cb0: f000 ffde bl 8017c70 <dhcp_option>
8016cb4: 4603 mov r3, r0
8016cb6: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8016cb8: 89b8 ldrh r0, [r7, #12]
8016cba: 693b ldr r3, [r7, #16]
8016cbc: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016cc0: 687b ldr r3, [r7, #4]
8016cc2: 8d1b ldrh r3, [r3, #40] ; 0x28
8016cc4: 461a mov r2, r3
8016cc6: f001 f82d bl 8017d24 <dhcp_option_short>
8016cca: 4603 mov r3, r0
8016ccc: 81bb strh r3, [r7, #12]
/* MUST request the offered IP address */
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8016cce: 89b8 ldrh r0, [r7, #12]
8016cd0: 693b ldr r3, [r7, #16]
8016cd2: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016cd6: 2304 movs r3, #4
8016cd8: 2232 movs r2, #50 ; 0x32
8016cda: f000 ffc9 bl 8017c70 <dhcp_option>
8016cde: 4603 mov r3, r0
8016ce0: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
8016ce2: 89bc ldrh r4, [r7, #12]
8016ce4: 693b ldr r3, [r7, #16]
8016ce6: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016cea: 69bb ldr r3, [r7, #24]
8016cec: 69db ldr r3, [r3, #28]
8016cee: 4618 mov r0, r3
8016cf0: f7f8 f8db bl 800eeaa <lwip_htonl>
8016cf4: 4603 mov r3, r0
8016cf6: 461a mov r2, r3
8016cf8: 4629 mov r1, r5
8016cfa: 4620 mov r0, r4
8016cfc: f001 f844 bl 8017d88 <dhcp_option_long>
8016d00: 4603 mov r3, r0
8016d02: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8016d04: 89b8 ldrh r0, [r7, #12]
8016d06: 693b ldr r3, [r7, #16]
8016d08: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d0c: 2304 movs r3, #4
8016d0e: 2236 movs r2, #54 ; 0x36
8016d10: f000 ffae bl 8017c70 <dhcp_option>
8016d14: 4603 mov r3, r0
8016d16: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
8016d18: 89bc ldrh r4, [r7, #12]
8016d1a: 693b ldr r3, [r7, #16]
8016d1c: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016d20: 69bb ldr r3, [r7, #24]
8016d22: 699b ldr r3, [r3, #24]
8016d24: 4618 mov r0, r3
8016d26: f7f8 f8c0 bl 800eeaa <lwip_htonl>
8016d2a: 4603 mov r3, r0
8016d2c: 461a mov r2, r3
8016d2e: 4629 mov r1, r5
8016d30: 4620 mov r0, r4
8016d32: f001 f829 bl 8017d88 <dhcp_option_long>
8016d36: 4603 mov r3, r0
8016d38: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8016d3a: 89b8 ldrh r0, [r7, #12]
8016d3c: 693b ldr r3, [r7, #16]
8016d3e: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d42: 2303 movs r3, #3
8016d44: 2237 movs r2, #55 ; 0x37
8016d46: f000 ff93 bl 8017c70 <dhcp_option>
8016d4a: 4603 mov r3, r0
8016d4c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d4e: 2300 movs r3, #0
8016d50: 77bb strb r3, [r7, #30]
8016d52: e00e b.n 8016d72 <dhcp_select+0x136>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8016d54: 89b8 ldrh r0, [r7, #12]
8016d56: 693b ldr r3, [r7, #16]
8016d58: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d5c: 7fbb ldrb r3, [r7, #30]
8016d5e: 4a30 ldr r2, [pc, #192] ; (8016e20 <dhcp_select+0x1e4>)
8016d60: 5cd3 ldrb r3, [r2, r3]
8016d62: 461a mov r2, r3
8016d64: f000 ffb8 bl 8017cd8 <dhcp_option_byte>
8016d68: 4603 mov r3, r0
8016d6a: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d6c: 7fbb ldrb r3, [r7, #30]
8016d6e: 3301 adds r3, #1
8016d70: 77bb strb r3, [r7, #30]
8016d72: 7fbb ldrb r3, [r7, #30]
8016d74: 2b02 cmp r3, #2
8016d76: d9ed bls.n 8016d54 <dhcp_select+0x118>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8016d78: 89b8 ldrh r0, [r7, #12]
8016d7a: 693b ldr r3, [r7, #16]
8016d7c: 33f0 adds r3, #240 ; 0xf0
8016d7e: 697a ldr r2, [r7, #20]
8016d80: 4619 mov r1, r3
8016d82: f001 fcbb bl 80186fc <dhcp_option_trailer>
/* send broadcast to any DHCP server */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
8016d86: 4b27 ldr r3, [pc, #156] ; (8016e24 <dhcp_select+0x1e8>)
8016d88: 6818 ldr r0, [r3, #0]
8016d8a: 4b27 ldr r3, [pc, #156] ; (8016e28 <dhcp_select+0x1ec>)
8016d8c: 9301 str r3, [sp, #4]
8016d8e: 687b ldr r3, [r7, #4]
8016d90: 9300 str r3, [sp, #0]
8016d92: 2343 movs r3, #67 ; 0x43
8016d94: 4a25 ldr r2, [pc, #148] ; (8016e2c <dhcp_select+0x1f0>)
8016d96: 6979 ldr r1, [r7, #20]
8016d98: f7ff fbda bl 8016550 <udp_sendto_if_src>
8016d9c: 4603 mov r3, r0
8016d9e: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8016da0: 6978 ldr r0, [r7, #20]
8016da2: f7f9 fc21 bl 80105e8 <pbuf_free>
8016da6: e001 b.n 8016dac <dhcp_select+0x170>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
result = ERR_MEM;
8016da8: 23ff movs r3, #255 ; 0xff
8016daa: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8016dac: 69bb ldr r3, [r7, #24]
8016dae: 799b ldrb r3, [r3, #6]
8016db0: 2bff cmp r3, #255 ; 0xff
8016db2: d005 beq.n 8016dc0 <dhcp_select+0x184>
dhcp->tries++;
8016db4: 69bb ldr r3, [r7, #24]
8016db6: 799b ldrb r3, [r3, #6]
8016db8: 3301 adds r3, #1
8016dba: b2da uxtb r2, r3
8016dbc: 69bb ldr r3, [r7, #24]
8016dbe: 719a strb r2, [r3, #6]
}
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
8016dc0: 69bb ldr r3, [r7, #24]
8016dc2: 799b ldrb r3, [r3, #6]
8016dc4: 2b05 cmp r3, #5
8016dc6: d80d bhi.n 8016de4 <dhcp_select+0x1a8>
8016dc8: 69bb ldr r3, [r7, #24]
8016dca: 799b ldrb r3, [r3, #6]
8016dcc: 461a mov r2, r3
8016dce: 2301 movs r3, #1
8016dd0: 4093 lsls r3, r2
8016dd2: b29b uxth r3, r3
8016dd4: 461a mov r2, r3
8016dd6: 0152 lsls r2, r2, #5
8016dd8: 1ad2 subs r2, r2, r3
8016dda: 0092 lsls r2, r2, #2
8016ddc: 4413 add r3, r2
8016dde: 00db lsls r3, r3, #3
8016de0: b29b uxth r3, r3
8016de2: e001 b.n 8016de8 <dhcp_select+0x1ac>
8016de4: f64e 2360 movw r3, #60000 ; 0xea60
8016de8: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016dea: 89fb ldrh r3, [r7, #14]
8016dec: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016df0: 4a0f ldr r2, [pc, #60] ; (8016e30 <dhcp_select+0x1f4>)
8016df2: fb82 1203 smull r1, r2, r2, r3
8016df6: 1152 asrs r2, r2, #5
8016df8: 17db asrs r3, r3, #31
8016dfa: 1ad3 subs r3, r2, r3
8016dfc: b29a uxth r2, r3
8016dfe: 69bb ldr r3, [r7, #24]
8016e00: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8016e02: f997 301f ldrsb.w r3, [r7, #31]
}
8016e06: 4618 mov r0, r3
8016e08: 3720 adds r7, #32
8016e0a: 46bd mov sp, r7
8016e0c: bdb0 pop {r4, r5, r7, pc}
8016e0e: bf00 nop
8016e10: 0801e398 .word 0x0801e398
8016e14: 0801e444 .word 0x0801e444
8016e18: 0801e3f8 .word 0x0801e3f8
8016e1c: 0801e460 .word 0x0801e460
8016e20: 20000080 .word 0x20000080
8016e24: 2000876c .word 0x2000876c
8016e28: 08020e68 .word 0x08020e68
8016e2c: 08020e6c .word 0x08020e6c
8016e30: 10624dd3 .word 0x10624dd3
08016e34 <dhcp_coarse_tmr>:
* The DHCP timer that checks for lease renewal/rebind timeouts.
* Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS).
*/
void
dhcp_coarse_tmr(void)
{
8016e34: b580 push {r7, lr}
8016e36: b082 sub sp, #8
8016e38: af00 add r7, sp, #0
struct netif *netif;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
/* iterate through all network interfaces */
NETIF_FOREACH(netif) {
8016e3a: 4b27 ldr r3, [pc, #156] ; (8016ed8 <dhcp_coarse_tmr+0xa4>)
8016e3c: 681b ldr r3, [r3, #0]
8016e3e: 607b str r3, [r7, #4]
8016e40: e042 b.n 8016ec8 <dhcp_coarse_tmr+0x94>
/* only act on DHCP configured interfaces */
struct dhcp *dhcp = netif_dhcp_data(netif);
8016e42: 687b ldr r3, [r7, #4]
8016e44: 6a5b ldr r3, [r3, #36] ; 0x24
8016e46: 603b str r3, [r7, #0]
if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
8016e48: 683b ldr r3, [r7, #0]
8016e4a: 2b00 cmp r3, #0
8016e4c: d039 beq.n 8016ec2 <dhcp_coarse_tmr+0x8e>
8016e4e: 683b ldr r3, [r7, #0]
8016e50: 795b ldrb r3, [r3, #5]
8016e52: 2b00 cmp r3, #0
8016e54: d035 beq.n 8016ec2 <dhcp_coarse_tmr+0x8e>
/* compare lease time to expire timeout */
if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
8016e56: 683b ldr r3, [r7, #0]
8016e58: 8a9b ldrh r3, [r3, #20]
8016e5a: 2b00 cmp r3, #0
8016e5c: d012 beq.n 8016e84 <dhcp_coarse_tmr+0x50>
8016e5e: 683b ldr r3, [r7, #0]
8016e60: 8a5b ldrh r3, [r3, #18]
8016e62: 3301 adds r3, #1
8016e64: b29a uxth r2, r3
8016e66: 683b ldr r3, [r7, #0]
8016e68: 825a strh r2, [r3, #18]
8016e6a: 683b ldr r3, [r7, #0]
8016e6c: 8a5a ldrh r2, [r3, #18]
8016e6e: 683b ldr r3, [r7, #0]
8016e70: 8a9b ldrh r3, [r3, #20]
8016e72: 429a cmp r2, r3
8016e74: d106 bne.n 8016e84 <dhcp_coarse_tmr+0x50>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
/* this clients' lease time has expired */
dhcp_release_and_stop(netif);
8016e76: 6878 ldr r0, [r7, #4]
8016e78: f000 fe46 bl 8017b08 <dhcp_release_and_stop>
dhcp_start(netif);
8016e7c: 6878 ldr r0, [r7, #4]
8016e7e: f000 f96b bl 8017158 <dhcp_start>
8016e82: e01e b.n 8016ec2 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now? */
} else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
8016e84: 683b ldr r3, [r7, #0]
8016e86: 8a1b ldrh r3, [r3, #16]
8016e88: 2b00 cmp r3, #0
8016e8a: d00b beq.n 8016ea4 <dhcp_coarse_tmr+0x70>
8016e8c: 683b ldr r3, [r7, #0]
8016e8e: 8a1b ldrh r3, [r3, #16]
8016e90: 1e5a subs r2, r3, #1
8016e92: b291 uxth r1, r2
8016e94: 683a ldr r2, [r7, #0]
8016e96: 8211 strh r1, [r2, #16]
8016e98: 2b01 cmp r3, #1
8016e9a: d103 bne.n 8016ea4 <dhcp_coarse_tmr+0x70>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
/* this clients' rebind timeout triggered */
dhcp_t2_timeout(netif);
8016e9c: 6878 ldr r0, [r7, #4]
8016e9e: f000 f8c7 bl 8017030 <dhcp_t2_timeout>
8016ea2: e00e b.n 8016ec2 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now */
} else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
8016ea4: 683b ldr r3, [r7, #0]
8016ea6: 89db ldrh r3, [r3, #14]
8016ea8: 2b00 cmp r3, #0
8016eaa: d00a beq.n 8016ec2 <dhcp_coarse_tmr+0x8e>
8016eac: 683b ldr r3, [r7, #0]
8016eae: 89db ldrh r3, [r3, #14]
8016eb0: 1e5a subs r2, r3, #1
8016eb2: b291 uxth r1, r2
8016eb4: 683a ldr r2, [r7, #0]
8016eb6: 81d1 strh r1, [r2, #14]
8016eb8: 2b01 cmp r3, #1
8016eba: d102 bne.n 8016ec2 <dhcp_coarse_tmr+0x8e>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
/* this clients' renewal timeout triggered */
dhcp_t1_timeout(netif);
8016ebc: 6878 ldr r0, [r7, #4]
8016ebe: f000 f888 bl 8016fd2 <dhcp_t1_timeout>
NETIF_FOREACH(netif) {
8016ec2: 687b ldr r3, [r7, #4]
8016ec4: 681b ldr r3, [r3, #0]
8016ec6: 607b str r3, [r7, #4]
8016ec8: 687b ldr r3, [r7, #4]
8016eca: 2b00 cmp r3, #0
8016ecc: d1b9 bne.n 8016e42 <dhcp_coarse_tmr+0xe>
}
}
}
}
8016ece: bf00 nop
8016ed0: 3708 adds r7, #8
8016ed2: 46bd mov sp, r7
8016ed4: bd80 pop {r7, pc}
8016ed6: bf00 nop
8016ed8: 2000f5b0 .word 0x2000f5b0
08016edc <dhcp_fine_tmr>:
* A DHCP server is expected to respond within a short period of time.
* This timer checks whether an outstanding DHCP request is timed out.
*/
void
dhcp_fine_tmr(void)
{
8016edc: b580 push {r7, lr}
8016ede: b082 sub sp, #8
8016ee0: af00 add r7, sp, #0
struct netif *netif;
/* loop through netif's */
NETIF_FOREACH(netif) {
8016ee2: 4b16 ldr r3, [pc, #88] ; (8016f3c <dhcp_fine_tmr+0x60>)
8016ee4: 681b ldr r3, [r3, #0]
8016ee6: 607b str r3, [r7, #4]
8016ee8: e020 b.n 8016f2c <dhcp_fine_tmr+0x50>
struct dhcp *dhcp = netif_dhcp_data(netif);
8016eea: 687b ldr r3, [r7, #4]
8016eec: 6a5b ldr r3, [r3, #36] ; 0x24
8016eee: 603b str r3, [r7, #0]
/* only act on DHCP configured interfaces */
if (dhcp != NULL) {
8016ef0: 683b ldr r3, [r7, #0]
8016ef2: 2b00 cmp r3, #0
8016ef4: d017 beq.n 8016f26 <dhcp_fine_tmr+0x4a>
/* timer is active (non zero), and is about to trigger now */
if (dhcp->request_timeout > 1) {
8016ef6: 683b ldr r3, [r7, #0]
8016ef8: 891b ldrh r3, [r3, #8]
8016efa: 2b01 cmp r3, #1
8016efc: d906 bls.n 8016f0c <dhcp_fine_tmr+0x30>
dhcp->request_timeout--;
8016efe: 683b ldr r3, [r7, #0]
8016f00: 891b ldrh r3, [r3, #8]
8016f02: 3b01 subs r3, #1
8016f04: b29a uxth r2, r3
8016f06: 683b ldr r3, [r7, #0]
8016f08: 811a strh r2, [r3, #8]
8016f0a: e00c b.n 8016f26 <dhcp_fine_tmr+0x4a>
} else if (dhcp->request_timeout == 1) {
8016f0c: 683b ldr r3, [r7, #0]
8016f0e: 891b ldrh r3, [r3, #8]
8016f10: 2b01 cmp r3, #1
8016f12: d108 bne.n 8016f26 <dhcp_fine_tmr+0x4a>
dhcp->request_timeout--;
8016f14: 683b ldr r3, [r7, #0]
8016f16: 891b ldrh r3, [r3, #8]
8016f18: 3b01 subs r3, #1
8016f1a: b29a uxth r2, r3
8016f1c: 683b ldr r3, [r7, #0]
8016f1e: 811a strh r2, [r3, #8]
/* { dhcp->request_timeout == 0 } */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
/* this client's request timeout triggered */
dhcp_timeout(netif);
8016f20: 6878 ldr r0, [r7, #4]
8016f22: f000 f80d bl 8016f40 <dhcp_timeout>
NETIF_FOREACH(netif) {
8016f26: 687b ldr r3, [r7, #4]
8016f28: 681b ldr r3, [r3, #0]
8016f2a: 607b str r3, [r7, #4]
8016f2c: 687b ldr r3, [r7, #4]
8016f2e: 2b00 cmp r3, #0
8016f30: d1db bne.n 8016eea <dhcp_fine_tmr+0xe>
}
}
}
}
8016f32: bf00 nop
8016f34: 3708 adds r7, #8
8016f36: 46bd mov sp, r7
8016f38: bd80 pop {r7, pc}
8016f3a: bf00 nop
8016f3c: 2000f5b0 .word 0x2000f5b0
08016f40 <dhcp_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_timeout(struct netif *netif)
{
8016f40: b580 push {r7, lr}
8016f42: b084 sub sp, #16
8016f44: af00 add r7, sp, #0
8016f46: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016f48: 687b ldr r3, [r7, #4]
8016f4a: 6a5b ldr r3, [r3, #36] ; 0x24
8016f4c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
/* back-off period has passed, or server selection timed out */
if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
8016f4e: 68fb ldr r3, [r7, #12]
8016f50: 795b ldrb r3, [r3, #5]
8016f52: 2b0c cmp r3, #12
8016f54: d003 beq.n 8016f5e <dhcp_timeout+0x1e>
8016f56: 68fb ldr r3, [r7, #12]
8016f58: 795b ldrb r3, [r3, #5]
8016f5a: 2b06 cmp r3, #6
8016f5c: d103 bne.n 8016f66 <dhcp_timeout+0x26>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
dhcp_discover(netif);
8016f5e: 6878 ldr r0, [r7, #4]
8016f60: f000 fa68 bl 8017434 <dhcp_discover>
dhcp_reboot(netif);
} else {
dhcp_discover(netif);
}
}
}
8016f64: e031 b.n 8016fca <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REQUESTING) {
8016f66: 68fb ldr r3, [r7, #12]
8016f68: 795b ldrb r3, [r3, #5]
8016f6a: 2b01 cmp r3, #1
8016f6c: d10e bne.n 8016f8c <dhcp_timeout+0x4c>
if (dhcp->tries <= 5) {
8016f6e: 68fb ldr r3, [r7, #12]
8016f70: 799b ldrb r3, [r3, #6]
8016f72: 2b05 cmp r3, #5
8016f74: d803 bhi.n 8016f7e <dhcp_timeout+0x3e>
dhcp_select(netif);
8016f76: 6878 ldr r0, [r7, #4]
8016f78: f7ff fe60 bl 8016c3c <dhcp_select>
}
8016f7c: e025 b.n 8016fca <dhcp_timeout+0x8a>
dhcp_release_and_stop(netif);
8016f7e: 6878 ldr r0, [r7, #4]
8016f80: f000 fdc2 bl 8017b08 <dhcp_release_and_stop>
dhcp_start(netif);
8016f84: 6878 ldr r0, [r7, #4]
8016f86: f000 f8e7 bl 8017158 <dhcp_start>
}
8016f8a: e01e b.n 8016fca <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_CHECKING) {
8016f8c: 68fb ldr r3, [r7, #12]
8016f8e: 795b ldrb r3, [r3, #5]
8016f90: 2b08 cmp r3, #8
8016f92: d10b bne.n 8016fac <dhcp_timeout+0x6c>
if (dhcp->tries <= 1) {
8016f94: 68fb ldr r3, [r7, #12]
8016f96: 799b ldrb r3, [r3, #6]
8016f98: 2b01 cmp r3, #1
8016f9a: d803 bhi.n 8016fa4 <dhcp_timeout+0x64>
dhcp_check(netif);
8016f9c: 6878 ldr r0, [r7, #4]
8016f9e: f7ff fdf3 bl 8016b88 <dhcp_check>
}
8016fa2: e012 b.n 8016fca <dhcp_timeout+0x8a>
dhcp_bind(netif);
8016fa4: 6878 ldr r0, [r7, #4]
8016fa6: f000 fae7 bl 8017578 <dhcp_bind>
}
8016faa: e00e b.n 8016fca <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REBOOTING) {
8016fac: 68fb ldr r3, [r7, #12]
8016fae: 795b ldrb r3, [r3, #5]
8016fb0: 2b03 cmp r3, #3
8016fb2: d10a bne.n 8016fca <dhcp_timeout+0x8a>
if (dhcp->tries < REBOOT_TRIES) {
8016fb4: 68fb ldr r3, [r7, #12]
8016fb6: 799b ldrb r3, [r3, #6]
8016fb8: 2b01 cmp r3, #1
8016fba: d803 bhi.n 8016fc4 <dhcp_timeout+0x84>
dhcp_reboot(netif);
8016fbc: 6878 ldr r0, [r7, #4]
8016fbe: f000 fced bl 801799c <dhcp_reboot>
}
8016fc2: e002 b.n 8016fca <dhcp_timeout+0x8a>
dhcp_discover(netif);
8016fc4: 6878 ldr r0, [r7, #4]
8016fc6: f000 fa35 bl 8017434 <dhcp_discover>
}
8016fca: bf00 nop
8016fcc: 3710 adds r7, #16
8016fce: 46bd mov sp, r7
8016fd0: bd80 pop {r7, pc}
08016fd2 <dhcp_t1_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t1_timeout(struct netif *netif)
{
8016fd2: b580 push {r7, lr}
8016fd4: b084 sub sp, #16
8016fd6: af00 add r7, sp, #0
8016fd8: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016fda: 687b ldr r3, [r7, #4]
8016fdc: 6a5b ldr r3, [r3, #36] ; 0x24
8016fde: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016fe0: 68fb ldr r3, [r7, #12]
8016fe2: 795b ldrb r3, [r3, #5]
8016fe4: 2b01 cmp r3, #1
8016fe6: d007 beq.n 8016ff8 <dhcp_t1_timeout+0x26>
8016fe8: 68fb ldr r3, [r7, #12]
8016fea: 795b ldrb r3, [r3, #5]
8016fec: 2b0a cmp r3, #10
8016fee: d003 beq.n 8016ff8 <dhcp_t1_timeout+0x26>
(dhcp->state == DHCP_STATE_RENEWING)) {
8016ff0: 68fb ldr r3, [r7, #12]
8016ff2: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016ff4: 2b05 cmp r3, #5
8016ff6: d117 bne.n 8017028 <dhcp_t1_timeout+0x56>
* eventually time-out if renew tries fail. */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t1_timeout(): must renew\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
dhcp_renew(netif);
8016ff8: 6878 ldr r0, [r7, #4]
8016ffa: f000 fb97 bl 801772c <dhcp_renew>
/* Calculate next timeout */
if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
8016ffe: 68fb ldr r3, [r7, #12]
8017000: 899b ldrh r3, [r3, #12]
8017002: 461a mov r2, r3
8017004: 68fb ldr r3, [r7, #12]
8017006: 8a5b ldrh r3, [r3, #18]
8017008: 1ad3 subs r3, r2, r3
801700a: 2b01 cmp r3, #1
801700c: dd0c ble.n 8017028 <dhcp_t1_timeout+0x56>
dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2);
801700e: 68fb ldr r3, [r7, #12]
8017010: 899b ldrh r3, [r3, #12]
8017012: 461a mov r2, r3
8017014: 68fb ldr r3, [r7, #12]
8017016: 8a5b ldrh r3, [r3, #18]
8017018: 1ad3 subs r3, r2, r3
801701a: 2b00 cmp r3, #0
801701c: da00 bge.n 8017020 <dhcp_t1_timeout+0x4e>
801701e: 3301 adds r3, #1
8017020: 105b asrs r3, r3, #1
8017022: b29a uxth r2, r3
8017024: 68fb ldr r3, [r7, #12]
8017026: 81da strh r2, [r3, #14]
}
}
}
8017028: bf00 nop
801702a: 3710 adds r7, #16
801702c: 46bd mov sp, r7
801702e: bd80 pop {r7, pc}
08017030 <dhcp_t2_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t2_timeout(struct netif *netif)
{
8017030: b580 push {r7, lr}
8017032: b084 sub sp, #16
8017034: af00 add r7, sp, #0
8017036: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017038: 687b ldr r3, [r7, #4]
801703a: 6a5b ldr r3, [r3, #36] ; 0x24
801703c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
801703e: 68fb ldr r3, [r7, #12]
8017040: 795b ldrb r3, [r3, #5]
8017042: 2b01 cmp r3, #1
8017044: d00b beq.n 801705e <dhcp_t2_timeout+0x2e>
8017046: 68fb ldr r3, [r7, #12]
8017048: 795b ldrb r3, [r3, #5]
801704a: 2b0a cmp r3, #10
801704c: d007 beq.n 801705e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
801704e: 68fb ldr r3, [r7, #12]
8017050: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8017052: 2b05 cmp r3, #5
8017054: d003 beq.n 801705e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
8017056: 68fb ldr r3, [r7, #12]
8017058: 795b ldrb r3, [r3, #5]
801705a: 2b04 cmp r3, #4
801705c: d117 bne.n 801708e <dhcp_t2_timeout+0x5e>
/* just retry to rebind */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t2_timeout(): must rebind\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
dhcp_rebind(netif);
801705e: 6878 ldr r0, [r7, #4]
8017060: f000 fc00 bl 8017864 <dhcp_rebind>
/* Calculate next timeout */
if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
8017064: 68fb ldr r3, [r7, #12]
8017066: 8a9b ldrh r3, [r3, #20]
8017068: 461a mov r2, r3
801706a: 68fb ldr r3, [r7, #12]
801706c: 8a5b ldrh r3, [r3, #18]
801706e: 1ad3 subs r3, r2, r3
8017070: 2b01 cmp r3, #1
8017072: dd0c ble.n 801708e <dhcp_t2_timeout+0x5e>
dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2);
8017074: 68fb ldr r3, [r7, #12]
8017076: 8a9b ldrh r3, [r3, #20]
8017078: 461a mov r2, r3
801707a: 68fb ldr r3, [r7, #12]
801707c: 8a5b ldrh r3, [r3, #18]
801707e: 1ad3 subs r3, r2, r3
8017080: 2b00 cmp r3, #0
8017082: da00 bge.n 8017086 <dhcp_t2_timeout+0x56>
8017084: 3301 adds r3, #1
8017086: 105b asrs r3, r3, #1
8017088: b29a uxth r2, r3
801708a: 68fb ldr r3, [r7, #12]
801708c: 821a strh r2, [r3, #16]
}
}
}
801708e: bf00 nop
8017090: 3710 adds r7, #16
8017092: 46bd mov sp, r7
8017094: bd80 pop {r7, pc}
...
08017098 <dhcp_handle_ack>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in)
{
8017098: b580 push {r7, lr}
801709a: b084 sub sp, #16
801709c: af00 add r7, sp, #0
801709e: 6078 str r0, [r7, #4]
80170a0: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
80170a2: 687b ldr r3, [r7, #4]
80170a4: 6a5b ldr r3, [r3, #36] ; 0x24
80170a6: 60fb str r3, [r7, #12]
#if LWIP_DHCP_GET_NTP_SRV
ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
#endif
/* clear options we might not get from the ACK */
ip4_addr_set_zero(&dhcp->offered_sn_mask);
80170a8: 68fb ldr r3, [r7, #12]
80170aa: 2200 movs r2, #0
80170ac: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
80170ae: 68fb ldr r3, [r7, #12]
80170b0: 2200 movs r2, #0
80170b2: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* lease time given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
80170b4: 4b26 ldr r3, [pc, #152] ; (8017150 <dhcp_handle_ack+0xb8>)
80170b6: 78db ldrb r3, [r3, #3]
80170b8: 2b00 cmp r3, #0
80170ba: d003 beq.n 80170c4 <dhcp_handle_ack+0x2c>
/* remember offered lease time */
dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
80170bc: 4b25 ldr r3, [pc, #148] ; (8017154 <dhcp_handle_ack+0xbc>)
80170be: 68da ldr r2, [r3, #12]
80170c0: 68fb ldr r3, [r7, #12]
80170c2: 629a str r2, [r3, #40] ; 0x28
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
80170c4: 4b22 ldr r3, [pc, #136] ; (8017150 <dhcp_handle_ack+0xb8>)
80170c6: 791b ldrb r3, [r3, #4]
80170c8: 2b00 cmp r3, #0
80170ca: d004 beq.n 80170d6 <dhcp_handle_ack+0x3e>
/* remember given renewal period */
dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
80170cc: 4b21 ldr r3, [pc, #132] ; (8017154 <dhcp_handle_ack+0xbc>)
80170ce: 691a ldr r2, [r3, #16]
80170d0: 68fb ldr r3, [r7, #12]
80170d2: 62da str r2, [r3, #44] ; 0x2c
80170d4: e004 b.n 80170e0 <dhcp_handle_ack+0x48>
} else {
/* calculate safe periods for renewal */
dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
80170d6: 68fb ldr r3, [r7, #12]
80170d8: 6a9b ldr r3, [r3, #40] ; 0x28
80170da: 085a lsrs r2, r3, #1
80170dc: 68fb ldr r3, [r7, #12]
80170de: 62da str r2, [r3, #44] ; 0x2c
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
80170e0: 4b1b ldr r3, [pc, #108] ; (8017150 <dhcp_handle_ack+0xb8>)
80170e2: 795b ldrb r3, [r3, #5]
80170e4: 2b00 cmp r3, #0
80170e6: d004 beq.n 80170f2 <dhcp_handle_ack+0x5a>
/* remember given rebind period */
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
80170e8: 4b1a ldr r3, [pc, #104] ; (8017154 <dhcp_handle_ack+0xbc>)
80170ea: 695a ldr r2, [r3, #20]
80170ec: 68fb ldr r3, [r7, #12]
80170ee: 631a str r2, [r3, #48] ; 0x30
80170f0: e007 b.n 8017102 <dhcp_handle_ack+0x6a>
} else {
/* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
80170f2: 68fb ldr r3, [r7, #12]
80170f4: 6a9a ldr r2, [r3, #40] ; 0x28
80170f6: 4613 mov r3, r2
80170f8: 00db lsls r3, r3, #3
80170fa: 1a9b subs r3, r3, r2
80170fc: 08da lsrs r2, r3, #3
80170fe: 68fb ldr r3, [r7, #12]
8017100: 631a str r2, [r3, #48] ; 0x30
}
/* (y)our internet address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
8017102: 683b ldr r3, [r7, #0]
8017104: 691a ldr r2, [r3, #16]
8017106: 68fb ldr r3, [r7, #12]
8017108: 61da str r2, [r3, #28]
boot file name copied in dhcp_parse_reply if not overloaded */
ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* subnet mask given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
801710a: 4b11 ldr r3, [pc, #68] ; (8017150 <dhcp_handle_ack+0xb8>)
801710c: 799b ldrb r3, [r3, #6]
801710e: 2b00 cmp r3, #0
8017110: d00b beq.n 801712a <dhcp_handle_ack+0x92>
/* remember given subnet mask */
ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
8017112: 4b10 ldr r3, [pc, #64] ; (8017154 <dhcp_handle_ack+0xbc>)
8017114: 699b ldr r3, [r3, #24]
8017116: 4618 mov r0, r3
8017118: f7f7 fec7 bl 800eeaa <lwip_htonl>
801711c: 4602 mov r2, r0
801711e: 68fb ldr r3, [r7, #12]
8017120: 621a str r2, [r3, #32]
dhcp->subnet_mask_given = 1;
8017122: 68fb ldr r3, [r7, #12]
8017124: 2201 movs r2, #1
8017126: 71da strb r2, [r3, #7]
8017128: e002 b.n 8017130 <dhcp_handle_ack+0x98>
} else {
dhcp->subnet_mask_given = 0;
801712a: 68fb ldr r3, [r7, #12]
801712c: 2200 movs r2, #0
801712e: 71da strb r2, [r3, #7]
}
/* gateway router */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
8017130: 4b07 ldr r3, [pc, #28] ; (8017150 <dhcp_handle_ack+0xb8>)
8017132: 79db ldrb r3, [r3, #7]
8017134: 2b00 cmp r3, #0
8017136: d007 beq.n 8017148 <dhcp_handle_ack+0xb0>
ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
8017138: 4b06 ldr r3, [pc, #24] ; (8017154 <dhcp_handle_ack+0xbc>)
801713a: 69db ldr r3, [r3, #28]
801713c: 4618 mov r0, r3
801713e: f7f7 feb4 bl 800eeaa <lwip_htonl>
8017142: 4602 mov r2, r0
8017144: 68fb ldr r3, [r7, #12]
8017146: 625a str r2, [r3, #36] ; 0x24
ip_addr_t dns_addr;
ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
dns_setserver(n, &dns_addr);
}
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
}
8017148: bf00 nop
801714a: 3710 adds r7, #16
801714c: 46bd mov sp, r7
801714e: bd80 pop {r7, pc}
8017150: 2000f5dc .word 0x2000f5dc
8017154: 2000f5e4 .word 0x2000f5e4
08017158 <dhcp_start>:
* - ERR_OK - No error
* - ERR_MEM - Out of memory
*/
err_t
dhcp_start(struct netif *netif)
{
8017158: b580 push {r7, lr}
801715a: b084 sub sp, #16
801715c: af00 add r7, sp, #0
801715e: 6078 str r0, [r7, #4]
struct dhcp *dhcp;
err_t result;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
8017160: 687b ldr r3, [r7, #4]
8017162: 2b00 cmp r3, #0
8017164: d109 bne.n 801717a <dhcp_start+0x22>
8017166: 4b37 ldr r3, [pc, #220] ; (8017244 <dhcp_start+0xec>)
8017168: f240 22e7 movw r2, #743 ; 0x2e7
801716c: 4936 ldr r1, [pc, #216] ; (8017248 <dhcp_start+0xf0>)
801716e: 4837 ldr r0, [pc, #220] ; (801724c <dhcp_start+0xf4>)
8017170: f003 ff50 bl 801b014 <iprintf>
8017174: f06f 030f mvn.w r3, #15
8017178: e060 b.n 801723c <dhcp_start+0xe4>
LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
801717a: 687b ldr r3, [r7, #4]
801717c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8017180: f003 0301 and.w r3, r3, #1
8017184: 2b00 cmp r3, #0
8017186: d109 bne.n 801719c <dhcp_start+0x44>
8017188: 4b2e ldr r3, [pc, #184] ; (8017244 <dhcp_start+0xec>)
801718a: f44f 723a mov.w r2, #744 ; 0x2e8
801718e: 4930 ldr r1, [pc, #192] ; (8017250 <dhcp_start+0xf8>)
8017190: 482e ldr r0, [pc, #184] ; (801724c <dhcp_start+0xf4>)
8017192: f003 ff3f bl 801b014 <iprintf>
8017196: f06f 030f mvn.w r3, #15
801719a: e04f b.n 801723c <dhcp_start+0xe4>
dhcp = netif_dhcp_data(netif);
801719c: 687b ldr r3, [r7, #4]
801719e: 6a5b ldr r3, [r3, #36] ; 0x24
80171a0: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* check MTU of the netif */
if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
80171a2: 687b ldr r3, [r7, #4]
80171a4: 8d1b ldrh r3, [r3, #40] ; 0x28
80171a6: f5b3 7f10 cmp.w r3, #576 ; 0x240
80171aa: d202 bcs.n 80171b2 <dhcp_start+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
return ERR_MEM;
80171ac: f04f 33ff mov.w r3, #4294967295
80171b0: e044 b.n 801723c <dhcp_start+0xe4>
}
/* no DHCP client attached yet? */
if (dhcp == NULL) {
80171b2: 68fb ldr r3, [r7, #12]
80171b4: 2b00 cmp r3, #0
80171b6: d10d bne.n 80171d4 <dhcp_start+0x7c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n"));
dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
80171b8: 2034 movs r0, #52 ; 0x34
80171ba: f7f8 f995 bl 800f4e8 <mem_malloc>
80171be: 60f8 str r0, [r7, #12]
if (dhcp == NULL) {
80171c0: 68fb ldr r3, [r7, #12]
80171c2: 2b00 cmp r3, #0
80171c4: d102 bne.n 80171cc <dhcp_start+0x74>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
return ERR_MEM;
80171c6: f04f 33ff mov.w r3, #4294967295
80171ca: e037 b.n 801723c <dhcp_start+0xe4>
}
/* store this dhcp client in the netif */
netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
80171cc: 687b ldr r3, [r7, #4]
80171ce: 68fa ldr r2, [r7, #12]
80171d0: 625a str r2, [r3, #36] ; 0x24
80171d2: e005 b.n 80171e0 <dhcp_start+0x88>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
/* already has DHCP client attached */
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
if (dhcp->pcb_allocated != 0) {
80171d4: 68fb ldr r3, [r7, #12]
80171d6: 791b ldrb r3, [r3, #4]
80171d8: 2b00 cmp r3, #0
80171da: d001 beq.n 80171e0 <dhcp_start+0x88>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
80171dc: f7ff fc90 bl 8016b00 <dhcp_dec_pcb_refcount>
}
/* dhcp is cleared below, no need to reset flag*/
}
/* clear data structure */
memset(dhcp, 0, sizeof(struct dhcp));
80171e0: 2234 movs r2, #52 ; 0x34
80171e2: 2100 movs r1, #0
80171e4: 68f8 ldr r0, [r7, #12]
80171e6: f003 ff0d bl 801b004 <memset>
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
80171ea: f7ff fc37 bl 8016a5c <dhcp_inc_pcb_refcount>
80171ee: 4603 mov r3, r0
80171f0: 2b00 cmp r3, #0
80171f2: d002 beq.n 80171fa <dhcp_start+0xa2>
return ERR_MEM;
80171f4: f04f 33ff mov.w r3, #4294967295
80171f8: e020 b.n 801723c <dhcp_start+0xe4>
}
dhcp->pcb_allocated = 1;
80171fa: 68fb ldr r3, [r7, #12]
80171fc: 2201 movs r2, #1
80171fe: 711a strb r2, [r3, #4]
if (!netif_is_link_up(netif)) {
8017200: 687b ldr r3, [r7, #4]
8017202: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8017206: f003 0304 and.w r3, r3, #4
801720a: 2b00 cmp r3, #0
801720c: d105 bne.n 801721a <dhcp_start+0xc2>
/* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
dhcp_set_state(dhcp, DHCP_STATE_INIT);
801720e: 2102 movs r1, #2
8017210: 68f8 ldr r0, [r7, #12]
8017212: f000 fd13 bl 8017c3c <dhcp_set_state>
return ERR_OK;
8017216: 2300 movs r3, #0
8017218: e010 b.n 801723c <dhcp_start+0xe4>
}
/* (re)start the DHCP negotiation */
result = dhcp_discover(netif);
801721a: 6878 ldr r0, [r7, #4]
801721c: f000 f90a bl 8017434 <dhcp_discover>
8017220: 4603 mov r3, r0
8017222: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
8017224: f997 300b ldrsb.w r3, [r7, #11]
8017228: 2b00 cmp r3, #0
801722a: d005 beq.n 8017238 <dhcp_start+0xe0>
/* free resources allocated above */
dhcp_release_and_stop(netif);
801722c: 6878 ldr r0, [r7, #4]
801722e: f000 fc6b bl 8017b08 <dhcp_release_and_stop>
return ERR_MEM;
8017232: f04f 33ff mov.w r3, #4294967295
8017236: e001 b.n 801723c <dhcp_start+0xe4>
}
return result;
8017238: f997 300b ldrsb.w r3, [r7, #11]
}
801723c: 4618 mov r0, r3
801723e: 3710 adds r7, #16
8017240: 46bd mov sp, r7
8017242: bd80 pop {r7, pc}
8017244: 0801e398 .word 0x0801e398
8017248: 0801e47c .word 0x0801e47c
801724c: 0801e3f8 .word 0x0801e3f8
8017250: 0801e4c0 .word 0x0801e4c0
08017254 <dhcp_network_changed>:
* This enters the REBOOTING state to verify that the currently bound
* address is still valid.
*/
void
dhcp_network_changed(struct netif *netif)
{
8017254: b580 push {r7, lr}
8017256: b084 sub sp, #16
8017258: af00 add r7, sp, #0
801725a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801725c: 687b ldr r3, [r7, #4]
801725e: 6a5b ldr r3, [r3, #36] ; 0x24
8017260: 60fb str r3, [r7, #12]
if (!dhcp) {
8017262: 68fb ldr r3, [r7, #12]
8017264: 2b00 cmp r3, #0
8017266: d037 beq.n 80172d8 <dhcp_network_changed+0x84>
return;
}
switch (dhcp->state) {
8017268: 68fb ldr r3, [r7, #12]
801726a: 795b ldrb r3, [r3, #5]
801726c: 2b0a cmp r3, #10
801726e: d820 bhi.n 80172b2 <dhcp_network_changed+0x5e>
8017270: a201 add r2, pc, #4 ; (adr r2, 8017278 <dhcp_network_changed+0x24>)
8017272: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8017276: bf00 nop
8017278: 080172dd .word 0x080172dd
801727c: 080172b3 .word 0x080172b3
8017280: 080172b3 .word 0x080172b3
8017284: 080172a5 .word 0x080172a5
8017288: 080172a5 .word 0x080172a5
801728c: 080172a5 .word 0x080172a5
8017290: 080172b3 .word 0x080172b3
8017294: 080172b3 .word 0x080172b3
8017298: 080172b3 .word 0x080172b3
801729c: 080172b3 .word 0x080172b3
80172a0: 080172a5 .word 0x080172a5
case DHCP_STATE_REBINDING:
case DHCP_STATE_RENEWING:
case DHCP_STATE_BOUND:
case DHCP_STATE_REBOOTING:
dhcp->tries = 0;
80172a4: 68fb ldr r3, [r7, #12]
80172a6: 2200 movs r2, #0
80172a8: 719a strb r2, [r3, #6]
dhcp_reboot(netif);
80172aa: 6878 ldr r0, [r7, #4]
80172ac: f000 fb76 bl 801799c <dhcp_reboot>
break;
80172b0: e015 b.n 80172de <dhcp_network_changed+0x8a>
case DHCP_STATE_OFF:
/* stay off */
break;
default:
LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF);
80172b2: 68fb ldr r3, [r7, #12]
80172b4: 795b ldrb r3, [r3, #5]
80172b6: 2b0c cmp r3, #12
80172b8: d906 bls.n 80172c8 <dhcp_network_changed+0x74>
80172ba: 4b0a ldr r3, [pc, #40] ; (80172e4 <dhcp_network_changed+0x90>)
80172bc: f240 326d movw r2, #877 ; 0x36d
80172c0: 4909 ldr r1, [pc, #36] ; (80172e8 <dhcp_network_changed+0x94>)
80172c2: 480a ldr r0, [pc, #40] ; (80172ec <dhcp_network_changed+0x98>)
80172c4: f003 fea6 bl 801b014 <iprintf>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
/* ensure we start with short timeouts, even if already discovering */
dhcp->tries = 0;
80172c8: 68fb ldr r3, [r7, #12]
80172ca: 2200 movs r2, #0
80172cc: 719a strb r2, [r3, #6]
dhcp_discover(netif);
80172ce: 6878 ldr r0, [r7, #4]
80172d0: f000 f8b0 bl 8017434 <dhcp_discover>
break;
80172d4: bf00 nop
80172d6: e002 b.n 80172de <dhcp_network_changed+0x8a>
return;
80172d8: bf00 nop
80172da: e000 b.n 80172de <dhcp_network_changed+0x8a>
break;
80172dc: bf00 nop
}
}
80172de: 3710 adds r7, #16
80172e0: 46bd mov sp, r7
80172e2: bd80 pop {r7, pc}
80172e4: 0801e398 .word 0x0801e398
80172e8: 0801e4e4 .word 0x0801e4e4
80172ec: 0801e3f8 .word 0x0801e3f8
080172f0 <dhcp_arp_reply>:
* @param netif the network interface on which the reply was received
* @param addr The IP address we received a reply from
*/
void
dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
{
80172f0: b580 push {r7, lr}
80172f2: b084 sub sp, #16
80172f4: af00 add r7, sp, #0
80172f6: 6078 str r0, [r7, #4]
80172f8: 6039 str r1, [r7, #0]
struct dhcp *dhcp;
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
80172fa: 687b ldr r3, [r7, #4]
80172fc: 2b00 cmp r3, #0
80172fe: d107 bne.n 8017310 <dhcp_arp_reply+0x20>
8017300: 4b0e ldr r3, [pc, #56] ; (801733c <dhcp_arp_reply+0x4c>)
8017302: f240 328b movw r2, #907 ; 0x38b
8017306: 490e ldr r1, [pc, #56] ; (8017340 <dhcp_arp_reply+0x50>)
8017308: 480e ldr r0, [pc, #56] ; (8017344 <dhcp_arp_reply+0x54>)
801730a: f003 fe83 bl 801b014 <iprintf>
801730e: e012 b.n 8017336 <dhcp_arp_reply+0x46>
dhcp = netif_dhcp_data(netif);
8017310: 687b ldr r3, [r7, #4]
8017312: 6a5b ldr r3, [r3, #36] ; 0x24
8017314: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
/* is a DHCP client doing an ARP check? */
if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) {
8017316: 68fb ldr r3, [r7, #12]
8017318: 2b00 cmp r3, #0
801731a: d00c beq.n 8017336 <dhcp_arp_reply+0x46>
801731c: 68fb ldr r3, [r7, #12]
801731e: 795b ldrb r3, [r3, #5]
8017320: 2b08 cmp r3, #8
8017322: d108 bne.n 8017336 <dhcp_arp_reply+0x46>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
ip4_addr_get_u32(addr)));
/* did a host respond with the address we
were offered by the DHCP server? */
if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) {
8017324: 683b ldr r3, [r7, #0]
8017326: 681a ldr r2, [r3, #0]
8017328: 68fb ldr r3, [r7, #12]
801732a: 69db ldr r3, [r3, #28]
801732c: 429a cmp r2, r3
801732e: d102 bne.n 8017336 <dhcp_arp_reply+0x46>
/* we will not accept the offered address */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
dhcp_decline(netif);
8017330: 6878 ldr r0, [r7, #4]
8017332: f000 f809 bl 8017348 <dhcp_decline>
}
}
}
8017336: 3710 adds r7, #16
8017338: 46bd mov sp, r7
801733a: bd80 pop {r7, pc}
801733c: 0801e398 .word 0x0801e398
8017340: 0801e47c .word 0x0801e47c
8017344: 0801e3f8 .word 0x0801e3f8
08017348 <dhcp_decline>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_decline(struct netif *netif)
{
8017348: b5b0 push {r4, r5, r7, lr}
801734a: b08a sub sp, #40 ; 0x28
801734c: af02 add r7, sp, #8
801734e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017350: 687b ldr r3, [r7, #4]
8017352: 6a5b ldr r3, [r3, #36] ; 0x24
8017354: 61bb str r3, [r7, #24]
u16_t msecs;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
8017356: 210c movs r1, #12
8017358: 69b8 ldr r0, [r7, #24]
801735a: f000 fc6f bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len);
801735e: f107 030c add.w r3, r7, #12
8017362: 2204 movs r2, #4
8017364: 69b9 ldr r1, [r7, #24]
8017366: 6878 ldr r0, [r7, #4]
8017368: f001 f8f2 bl 8018550 <dhcp_create_msg>
801736c: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801736e: 697b ldr r3, [r7, #20]
8017370: 2b00 cmp r3, #0
8017372: d035 beq.n 80173e0 <dhcp_decline+0x98>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017374: 697b ldr r3, [r7, #20]
8017376: 685b ldr r3, [r3, #4]
8017378: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
801737a: 89b8 ldrh r0, [r7, #12]
801737c: 693b ldr r3, [r7, #16]
801737e: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017382: 2304 movs r3, #4
8017384: 2232 movs r2, #50 ; 0x32
8017386: f000 fc73 bl 8017c70 <dhcp_option>
801738a: 4603 mov r3, r0
801738c: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
801738e: 89bc ldrh r4, [r7, #12]
8017390: 693b ldr r3, [r7, #16]
8017392: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017396: 69bb ldr r3, [r7, #24]
8017398: 69db ldr r3, [r3, #28]
801739a: 4618 mov r0, r3
801739c: f7f7 fd85 bl 800eeaa <lwip_htonl>
80173a0: 4603 mov r3, r0
80173a2: 461a mov r2, r3
80173a4: 4629 mov r1, r5
80173a6: 4620 mov r0, r4
80173a8: f000 fcee bl 8017d88 <dhcp_option_long>
80173ac: 4603 mov r3, r0
80173ae: 81bb strh r3, [r7, #12]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80173b0: 89b8 ldrh r0, [r7, #12]
80173b2: 693b ldr r3, [r7, #16]
80173b4: 33f0 adds r3, #240 ; 0xf0
80173b6: 697a ldr r2, [r7, #20]
80173b8: 4619 mov r1, r3
80173ba: f001 f99f bl 80186fc <dhcp_option_trailer>
/* per section 4.4.4, broadcast DECLINE messages */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
80173be: 4b19 ldr r3, [pc, #100] ; (8017424 <dhcp_decline+0xdc>)
80173c0: 6818 ldr r0, [r3, #0]
80173c2: 4b19 ldr r3, [pc, #100] ; (8017428 <dhcp_decline+0xe0>)
80173c4: 9301 str r3, [sp, #4]
80173c6: 687b ldr r3, [r7, #4]
80173c8: 9300 str r3, [sp, #0]
80173ca: 2343 movs r3, #67 ; 0x43
80173cc: 4a17 ldr r2, [pc, #92] ; (801742c <dhcp_decline+0xe4>)
80173ce: 6979 ldr r1, [r7, #20]
80173d0: f7ff f8be bl 8016550 <udp_sendto_if_src>
80173d4: 4603 mov r3, r0
80173d6: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
80173d8: 6978 ldr r0, [r7, #20]
80173da: f7f9 f905 bl 80105e8 <pbuf_free>
80173de: e001 b.n 80173e4 <dhcp_decline+0x9c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_decline: could not allocate DHCP request\n"));
result = ERR_MEM;
80173e0: 23ff movs r3, #255 ; 0xff
80173e2: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
80173e4: 69bb ldr r3, [r7, #24]
80173e6: 799b ldrb r3, [r3, #6]
80173e8: 2bff cmp r3, #255 ; 0xff
80173ea: d005 beq.n 80173f8 <dhcp_decline+0xb0>
dhcp->tries++;
80173ec: 69bb ldr r3, [r7, #24]
80173ee: 799b ldrb r3, [r3, #6]
80173f0: 3301 adds r3, #1
80173f2: b2da uxtb r2, r3
80173f4: 69bb ldr r3, [r7, #24]
80173f6: 719a strb r2, [r3, #6]
}
msecs = 10 * 1000;
80173f8: f242 7310 movw r3, #10000 ; 0x2710
80173fc: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
80173fe: 89fb ldrh r3, [r7, #14]
8017400: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017404: 4a0a ldr r2, [pc, #40] ; (8017430 <dhcp_decline+0xe8>)
8017406: fb82 1203 smull r1, r2, r2, r3
801740a: 1152 asrs r2, r2, #5
801740c: 17db asrs r3, r3, #31
801740e: 1ad3 subs r3, r2, r3
8017410: b29a uxth r2, r3
8017412: 69bb ldr r3, [r7, #24]
8017414: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017416: f997 301f ldrsb.w r3, [r7, #31]
}
801741a: 4618 mov r0, r3
801741c: 3720 adds r7, #32
801741e: 46bd mov sp, r7
8017420: bdb0 pop {r4, r5, r7, pc}
8017422: bf00 nop
8017424: 2000876c .word 0x2000876c
8017428: 08020e68 .word 0x08020e68
801742c: 08020e6c .word 0x08020e6c
8017430: 10624dd3 .word 0x10624dd3
08017434 <dhcp_discover>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_discover(struct netif *netif)
{
8017434: b580 push {r7, lr}
8017436: b08a sub sp, #40 ; 0x28
8017438: af02 add r7, sp, #8
801743a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801743c: 687b ldr r3, [r7, #4]
801743e: 6a5b ldr r3, [r3, #36] ; 0x24
8017440: 61bb str r3, [r7, #24]
err_t result = ERR_OK;
8017442: 2300 movs r3, #0
8017444: 75fb strb r3, [r7, #23]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
ip4_addr_set_any(&dhcp->offered_ip_addr);
8017446: 69bb ldr r3, [r7, #24]
8017448: 2200 movs r2, #0
801744a: 61da str r2, [r3, #28]
dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
801744c: 2106 movs r1, #6
801744e: 69b8 ldr r0, [r7, #24]
8017450: f000 fbf4 bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len);
8017454: f107 0308 add.w r3, r7, #8
8017458: 2201 movs r2, #1
801745a: 69b9 ldr r1, [r7, #24]
801745c: 6878 ldr r0, [r7, #4]
801745e: f001 f877 bl 8018550 <dhcp_create_msg>
8017462: 6138 str r0, [r7, #16]
if (p_out != NULL) {
8017464: 693b ldr r3, [r7, #16]
8017466: 2b00 cmp r3, #0
8017468: d04b beq.n 8017502 <dhcp_discover+0xce>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
801746a: 693b ldr r3, [r7, #16]
801746c: 685b ldr r3, [r3, #4]
801746e: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8017470: 8938 ldrh r0, [r7, #8]
8017472: 68fb ldr r3, [r7, #12]
8017474: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017478: 2302 movs r3, #2
801747a: 2239 movs r2, #57 ; 0x39
801747c: f000 fbf8 bl 8017c70 <dhcp_option>
8017480: 4603 mov r3, r0
8017482: 813b strh r3, [r7, #8]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017484: 8938 ldrh r0, [r7, #8]
8017486: 68fb ldr r3, [r7, #12]
8017488: f103 01f0 add.w r1, r3, #240 ; 0xf0
801748c: 687b ldr r3, [r7, #4]
801748e: 8d1b ldrh r3, [r3, #40] ; 0x28
8017490: 461a mov r2, r3
8017492: f000 fc47 bl 8017d24 <dhcp_option_short>
8017496: 4603 mov r3, r0
8017498: 813b strh r3, [r7, #8]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
801749a: 8938 ldrh r0, [r7, #8]
801749c: 68fb ldr r3, [r7, #12]
801749e: f103 01f0 add.w r1, r3, #240 ; 0xf0
80174a2: 2303 movs r3, #3
80174a4: 2237 movs r2, #55 ; 0x37
80174a6: f000 fbe3 bl 8017c70 <dhcp_option>
80174aa: 4603 mov r3, r0
80174ac: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80174ae: 2300 movs r3, #0
80174b0: 77fb strb r3, [r7, #31]
80174b2: e00e b.n 80174d2 <dhcp_discover+0x9e>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80174b4: 8938 ldrh r0, [r7, #8]
80174b6: 68fb ldr r3, [r7, #12]
80174b8: f103 01f0 add.w r1, r3, #240 ; 0xf0
80174bc: 7ffb ldrb r3, [r7, #31]
80174be: 4a29 ldr r2, [pc, #164] ; (8017564 <dhcp_discover+0x130>)
80174c0: 5cd3 ldrb r3, [r2, r3]
80174c2: 461a mov r2, r3
80174c4: f000 fc08 bl 8017cd8 <dhcp_option_byte>
80174c8: 4603 mov r3, r0
80174ca: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80174cc: 7ffb ldrb r3, [r7, #31]
80174ce: 3301 adds r3, #1
80174d0: 77fb strb r3, [r7, #31]
80174d2: 7ffb ldrb r3, [r7, #31]
80174d4: 2b02 cmp r3, #2
80174d6: d9ed bls.n 80174b4 <dhcp_discover+0x80>
}
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80174d8: 8938 ldrh r0, [r7, #8]
80174da: 68fb ldr r3, [r7, #12]
80174dc: 33f0 adds r3, #240 ; 0xf0
80174de: 693a ldr r2, [r7, #16]
80174e0: 4619 mov r1, r3
80174e2: f001 f90b bl 80186fc <dhcp_option_trailer>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n"));
udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
80174e6: 4b20 ldr r3, [pc, #128] ; (8017568 <dhcp_discover+0x134>)
80174e8: 6818 ldr r0, [r3, #0]
80174ea: 4b20 ldr r3, [pc, #128] ; (801756c <dhcp_discover+0x138>)
80174ec: 9301 str r3, [sp, #4]
80174ee: 687b ldr r3, [r7, #4]
80174f0: 9300 str r3, [sp, #0]
80174f2: 2343 movs r3, #67 ; 0x43
80174f4: 4a1e ldr r2, [pc, #120] ; (8017570 <dhcp_discover+0x13c>)
80174f6: 6939 ldr r1, [r7, #16]
80174f8: f7ff f82a bl 8016550 <udp_sendto_if_src>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
pbuf_free(p_out);
80174fc: 6938 ldr r0, [r7, #16]
80174fe: f7f9 f873 bl 80105e8 <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
8017502: 69bb ldr r3, [r7, #24]
8017504: 799b ldrb r3, [r3, #6]
8017506: 2bff cmp r3, #255 ; 0xff
8017508: d005 beq.n 8017516 <dhcp_discover+0xe2>
dhcp->tries++;
801750a: 69bb ldr r3, [r7, #24]
801750c: 799b ldrb r3, [r3, #6]
801750e: 3301 adds r3, #1
8017510: b2da uxtb r2, r3
8017512: 69bb ldr r3, [r7, #24]
8017514: 719a strb r2, [r3, #6]
if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
autoip_start(netif);
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
8017516: 69bb ldr r3, [r7, #24]
8017518: 799b ldrb r3, [r3, #6]
801751a: 2b05 cmp r3, #5
801751c: d80d bhi.n 801753a <dhcp_discover+0x106>
801751e: 69bb ldr r3, [r7, #24]
8017520: 799b ldrb r3, [r3, #6]
8017522: 461a mov r2, r3
8017524: 2301 movs r3, #1
8017526: 4093 lsls r3, r2
8017528: b29b uxth r3, r3
801752a: 461a mov r2, r3
801752c: 0152 lsls r2, r2, #5
801752e: 1ad2 subs r2, r2, r3
8017530: 0092 lsls r2, r2, #2
8017532: 4413 add r3, r2
8017534: 00db lsls r3, r3, #3
8017536: b29b uxth r3, r3
8017538: e001 b.n 801753e <dhcp_discover+0x10a>
801753a: f64e 2360 movw r3, #60000 ; 0xea60
801753e: 817b strh r3, [r7, #10]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017540: 897b ldrh r3, [r7, #10]
8017542: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017546: 4a0b ldr r2, [pc, #44] ; (8017574 <dhcp_discover+0x140>)
8017548: fb82 1203 smull r1, r2, r2, r3
801754c: 1152 asrs r2, r2, #5
801754e: 17db asrs r3, r3, #31
8017550: 1ad3 subs r3, r2, r3
8017552: b29a uxth r2, r3
8017554: 69bb ldr r3, [r7, #24]
8017556: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017558: f997 3017 ldrsb.w r3, [r7, #23]
}
801755c: 4618 mov r0, r3
801755e: 3720 adds r7, #32
8017560: 46bd mov sp, r7
8017562: bd80 pop {r7, pc}
8017564: 20000080 .word 0x20000080
8017568: 2000876c .word 0x2000876c
801756c: 08020e68 .word 0x08020e68
8017570: 08020e6c .word 0x08020e6c
8017574: 10624dd3 .word 0x10624dd3
08017578 <dhcp_bind>:
*
* @param netif network interface to bind to the offered address
*/
static void
dhcp_bind(struct netif *netif)
{
8017578: b580 push {r7, lr}
801757a: b088 sub sp, #32
801757c: af00 add r7, sp, #0
801757e: 6078 str r0, [r7, #4]
u32_t timeout;
struct dhcp *dhcp;
ip4_addr_t sn_mask, gw_addr;
LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
8017580: 687b ldr r3, [r7, #4]
8017582: 2b00 cmp r3, #0
8017584: d107 bne.n 8017596 <dhcp_bind+0x1e>
8017586: 4b64 ldr r3, [pc, #400] ; (8017718 <dhcp_bind+0x1a0>)
8017588: f240 4215 movw r2, #1045 ; 0x415
801758c: 4963 ldr r1, [pc, #396] ; (801771c <dhcp_bind+0x1a4>)
801758e: 4864 ldr r0, [pc, #400] ; (8017720 <dhcp_bind+0x1a8>)
8017590: f003 fd40 bl 801b014 <iprintf>
8017594: e0bc b.n 8017710 <dhcp_bind+0x198>
dhcp = netif_dhcp_data(netif);
8017596: 687b ldr r3, [r7, #4]
8017598: 6a5b ldr r3, [r3, #36] ; 0x24
801759a: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
801759c: 69bb ldr r3, [r7, #24]
801759e: 2b00 cmp r3, #0
80175a0: d107 bne.n 80175b2 <dhcp_bind+0x3a>
80175a2: 4b5d ldr r3, [pc, #372] ; (8017718 <dhcp_bind+0x1a0>)
80175a4: f240 4217 movw r2, #1047 ; 0x417
80175a8: 495e ldr r1, [pc, #376] ; (8017724 <dhcp_bind+0x1ac>)
80175aa: 485d ldr r0, [pc, #372] ; (8017720 <dhcp_bind+0x1a8>)
80175ac: f003 fd32 bl 801b014 <iprintf>
80175b0: e0ae b.n 8017710 <dhcp_bind+0x198>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* reset time used of lease */
dhcp->lease_used = 0;
80175b2: 69bb ldr r3, [r7, #24]
80175b4: 2200 movs r2, #0
80175b6: 825a strh r2, [r3, #18]
if (dhcp->offered_t0_lease != 0xffffffffUL) {
80175b8: 69bb ldr r3, [r7, #24]
80175ba: 6a9b ldr r3, [r3, #40] ; 0x28
80175bc: f1b3 3fff cmp.w r3, #4294967295
80175c0: d019 beq.n 80175f6 <dhcp_bind+0x7e>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
80175c2: 69bb ldr r3, [r7, #24]
80175c4: 6a9b ldr r3, [r3, #40] ; 0x28
80175c6: 331e adds r3, #30
80175c8: 4a57 ldr r2, [pc, #348] ; (8017728 <dhcp_bind+0x1b0>)
80175ca: fba2 2303 umull r2, r3, r2, r3
80175ce: 095b lsrs r3, r3, #5
80175d0: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
80175d2: 69fb ldr r3, [r7, #28]
80175d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80175d8: d302 bcc.n 80175e0 <dhcp_bind+0x68>
timeout = 0xffff;
80175da: f64f 73ff movw r3, #65535 ; 0xffff
80175de: 61fb str r3, [r7, #28]
}
dhcp->t0_timeout = (u16_t)timeout;
80175e0: 69fb ldr r3, [r7, #28]
80175e2: b29a uxth r2, r3
80175e4: 69bb ldr r3, [r7, #24]
80175e6: 829a strh r2, [r3, #20]
if (dhcp->t0_timeout == 0) {
80175e8: 69bb ldr r3, [r7, #24]
80175ea: 8a9b ldrh r3, [r3, #20]
80175ec: 2b00 cmp r3, #0
80175ee: d102 bne.n 80175f6 <dhcp_bind+0x7e>
dhcp->t0_timeout = 1;
80175f0: 69bb ldr r3, [r7, #24]
80175f2: 2201 movs r2, #1
80175f4: 829a strh r2, [r3, #20]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000));
}
/* temporary DHCP lease? */
if (dhcp->offered_t1_renew != 0xffffffffUL) {
80175f6: 69bb ldr r3, [r7, #24]
80175f8: 6adb ldr r3, [r3, #44] ; 0x2c
80175fa: f1b3 3fff cmp.w r3, #4294967295
80175fe: d01d beq.n 801763c <dhcp_bind+0xc4>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
8017600: 69bb ldr r3, [r7, #24]
8017602: 6adb ldr r3, [r3, #44] ; 0x2c
8017604: 331e adds r3, #30
8017606: 4a48 ldr r2, [pc, #288] ; (8017728 <dhcp_bind+0x1b0>)
8017608: fba2 2303 umull r2, r3, r2, r3
801760c: 095b lsrs r3, r3, #5
801760e: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
8017610: 69fb ldr r3, [r7, #28]
8017612: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8017616: d302 bcc.n 801761e <dhcp_bind+0xa6>
timeout = 0xffff;
8017618: f64f 73ff movw r3, #65535 ; 0xffff
801761c: 61fb str r3, [r7, #28]
}
dhcp->t1_timeout = (u16_t)timeout;
801761e: 69fb ldr r3, [r7, #28]
8017620: b29a uxth r2, r3
8017622: 69bb ldr r3, [r7, #24]
8017624: 815a strh r2, [r3, #10]
if (dhcp->t1_timeout == 0) {
8017626: 69bb ldr r3, [r7, #24]
8017628: 895b ldrh r3, [r3, #10]
801762a: 2b00 cmp r3, #0
801762c: d102 bne.n 8017634 <dhcp_bind+0xbc>
dhcp->t1_timeout = 1;
801762e: 69bb ldr r3, [r7, #24]
8017630: 2201 movs r2, #1
8017632: 815a strh r2, [r3, #10]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000));
dhcp->t1_renew_time = dhcp->t1_timeout;
8017634: 69bb ldr r3, [r7, #24]
8017636: 895a ldrh r2, [r3, #10]
8017638: 69bb ldr r3, [r7, #24]
801763a: 81da strh r2, [r3, #14]
}
/* set renewal period timer */
if (dhcp->offered_t2_rebind != 0xffffffffUL) {
801763c: 69bb ldr r3, [r7, #24]
801763e: 6b1b ldr r3, [r3, #48] ; 0x30
8017640: f1b3 3fff cmp.w r3, #4294967295
8017644: d01d beq.n 8017682 <dhcp_bind+0x10a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
8017646: 69bb ldr r3, [r7, #24]
8017648: 6b1b ldr r3, [r3, #48] ; 0x30
801764a: 331e adds r3, #30
801764c: 4a36 ldr r2, [pc, #216] ; (8017728 <dhcp_bind+0x1b0>)
801764e: fba2 2303 umull r2, r3, r2, r3
8017652: 095b lsrs r3, r3, #5
8017654: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
8017656: 69fb ldr r3, [r7, #28]
8017658: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801765c: d302 bcc.n 8017664 <dhcp_bind+0xec>
timeout = 0xffff;
801765e: f64f 73ff movw r3, #65535 ; 0xffff
8017662: 61fb str r3, [r7, #28]
}
dhcp->t2_timeout = (u16_t)timeout;
8017664: 69fb ldr r3, [r7, #28]
8017666: b29a uxth r2, r3
8017668: 69bb ldr r3, [r7, #24]
801766a: 819a strh r2, [r3, #12]
if (dhcp->t2_timeout == 0) {
801766c: 69bb ldr r3, [r7, #24]
801766e: 899b ldrh r3, [r3, #12]
8017670: 2b00 cmp r3, #0
8017672: d102 bne.n 801767a <dhcp_bind+0x102>
dhcp->t2_timeout = 1;
8017674: 69bb ldr r3, [r7, #24]
8017676: 2201 movs r2, #1
8017678: 819a strh r2, [r3, #12]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000));
dhcp->t2_rebind_time = dhcp->t2_timeout;
801767a: 69bb ldr r3, [r7, #24]
801767c: 899a ldrh r2, [r3, #12]
801767e: 69bb ldr r3, [r7, #24]
8017680: 821a strh r2, [r3, #16]
}
/* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
8017682: 69bb ldr r3, [r7, #24]
8017684: 895a ldrh r2, [r3, #10]
8017686: 69bb ldr r3, [r7, #24]
8017688: 899b ldrh r3, [r3, #12]
801768a: 429a cmp r2, r3
801768c: d306 bcc.n 801769c <dhcp_bind+0x124>
801768e: 69bb ldr r3, [r7, #24]
8017690: 899b ldrh r3, [r3, #12]
8017692: 2b00 cmp r3, #0
8017694: d002 beq.n 801769c <dhcp_bind+0x124>
dhcp->t1_timeout = 0;
8017696: 69bb ldr r3, [r7, #24]
8017698: 2200 movs r2, #0
801769a: 815a strh r2, [r3, #10]
}
if (dhcp->subnet_mask_given) {
801769c: 69bb ldr r3, [r7, #24]
801769e: 79db ldrb r3, [r3, #7]
80176a0: 2b00 cmp r3, #0
80176a2: d003 beq.n 80176ac <dhcp_bind+0x134>
/* copy offered network mask */
ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
80176a4: 69bb ldr r3, [r7, #24]
80176a6: 6a1b ldr r3, [r3, #32]
80176a8: 613b str r3, [r7, #16]
80176aa: e014 b.n 80176d6 <dhcp_bind+0x15e>
} else {
/* subnet mask not given, choose a safe subnet mask given the network class */
u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
80176ac: 69bb ldr r3, [r7, #24]
80176ae: 331c adds r3, #28
80176b0: 781b ldrb r3, [r3, #0]
80176b2: 75fb strb r3, [r7, #23]
if (first_octet <= 127) {
80176b4: f997 3017 ldrsb.w r3, [r7, #23]
80176b8: 2b00 cmp r3, #0
80176ba: db02 blt.n 80176c2 <dhcp_bind+0x14a>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
80176bc: 23ff movs r3, #255 ; 0xff
80176be: 613b str r3, [r7, #16]
80176c0: e009 b.n 80176d6 <dhcp_bind+0x15e>
} else if (first_octet >= 192) {
80176c2: 7dfb ldrb r3, [r7, #23]
80176c4: 2bbf cmp r3, #191 ; 0xbf
80176c6: d903 bls.n 80176d0 <dhcp_bind+0x158>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
80176c8: f06f 437f mvn.w r3, #4278190080 ; 0xff000000
80176cc: 613b str r3, [r7, #16]
80176ce: e002 b.n 80176d6 <dhcp_bind+0x15e>
} else {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
80176d0: f64f 73ff movw r3, #65535 ; 0xffff
80176d4: 613b str r3, [r7, #16]
}
}
ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
80176d6: 69bb ldr r3, [r7, #24]
80176d8: 6a5b ldr r3, [r3, #36] ; 0x24
80176da: 60fb str r3, [r7, #12]
/* gateway address not given? */
if (ip4_addr_isany_val(gw_addr)) {
80176dc: 68fb ldr r3, [r7, #12]
80176de: 2b00 cmp r3, #0
80176e0: d108 bne.n 80176f4 <dhcp_bind+0x17c>
/* copy network address */
ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
80176e2: 69bb ldr r3, [r7, #24]
80176e4: 69da ldr r2, [r3, #28]
80176e6: 693b ldr r3, [r7, #16]
80176e8: 4013 ands r3, r2
80176ea: 60fb str r3, [r7, #12]
/* use first host address on network as gateway */
ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
80176ec: 68fb ldr r3, [r7, #12]
80176ee: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
80176f2: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
/* netif is now bound to DHCP leased address - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BOUND);
80176f4: 210a movs r1, #10
80176f6: 69b8 ldr r0, [r7, #24]
80176f8: f000 faa0 bl 8017c3c <dhcp_set_state>
netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
80176fc: 69bb ldr r3, [r7, #24]
80176fe: f103 011c add.w r1, r3, #28
8017702: f107 030c add.w r3, r7, #12
8017706: f107 0210 add.w r2, r7, #16
801770a: 6878 ldr r0, [r7, #4]
801770c: f7f8 fa62 bl 800fbd4 <netif_set_addr>
/* interface is used by routing now that an address is set */
}
8017710: 3720 adds r7, #32
8017712: 46bd mov sp, r7
8017714: bd80 pop {r7, pc}
8017716: bf00 nop
8017718: 0801e398 .word 0x0801e398
801771c: 0801e4f8 .word 0x0801e4f8
8017720: 0801e3f8 .word 0x0801e3f8
8017724: 0801e514 .word 0x0801e514
8017728: 88888889 .word 0x88888889
0801772c <dhcp_renew>:
*
* @param netif network interface which must renew its lease
*/
err_t
dhcp_renew(struct netif *netif)
{
801772c: b580 push {r7, lr}
801772e: b08a sub sp, #40 ; 0x28
8017730: af02 add r7, sp, #8
8017732: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017734: 687b ldr r3, [r7, #4]
8017736: 6a5b ldr r3, [r3, #36] ; 0x24
8017738: 61bb str r3, [r7, #24]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
801773a: 2105 movs r1, #5
801773c: 69b8 ldr r0, [r7, #24]
801773e: f000 fa7d bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8017742: f107 030c add.w r3, r7, #12
8017746: 2203 movs r2, #3
8017748: 69b9 ldr r1, [r7, #24]
801774a: 6878 ldr r0, [r7, #4]
801774c: f000 ff00 bl 8018550 <dhcp_create_msg>
8017750: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8017752: 697b ldr r3, [r7, #20]
8017754: 2b00 cmp r3, #0
8017756: d04e beq.n 80177f6 <dhcp_renew+0xca>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017758: 697b ldr r3, [r7, #20]
801775a: 685b ldr r3, [r3, #4]
801775c: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
801775e: 89b8 ldrh r0, [r7, #12]
8017760: 693b ldr r3, [r7, #16]
8017762: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017766: 2302 movs r3, #2
8017768: 2239 movs r2, #57 ; 0x39
801776a: f000 fa81 bl 8017c70 <dhcp_option>
801776e: 4603 mov r3, r0
8017770: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017772: 89b8 ldrh r0, [r7, #12]
8017774: 693b ldr r3, [r7, #16]
8017776: f103 01f0 add.w r1, r3, #240 ; 0xf0
801777a: 687b ldr r3, [r7, #4]
801777c: 8d1b ldrh r3, [r3, #40] ; 0x28
801777e: 461a mov r2, r3
8017780: f000 fad0 bl 8017d24 <dhcp_option_short>
8017784: 4603 mov r3, r0
8017786: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017788: 89b8 ldrh r0, [r7, #12]
801778a: 693b ldr r3, [r7, #16]
801778c: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017790: 2303 movs r3, #3
8017792: 2237 movs r2, #55 ; 0x37
8017794: f000 fa6c bl 8017c70 <dhcp_option>
8017798: 4603 mov r3, r0
801779a: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
801779c: 2300 movs r3, #0
801779e: 77bb strb r3, [r7, #30]
80177a0: e00e b.n 80177c0 <dhcp_renew+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80177a2: 89b8 ldrh r0, [r7, #12]
80177a4: 693b ldr r3, [r7, #16]
80177a6: f103 01f0 add.w r1, r3, #240 ; 0xf0
80177aa: 7fbb ldrb r3, [r7, #30]
80177ac: 4a2a ldr r2, [pc, #168] ; (8017858 <dhcp_renew+0x12c>)
80177ae: 5cd3 ldrb r3, [r2, r3]
80177b0: 461a mov r2, r3
80177b2: f000 fa91 bl 8017cd8 <dhcp_option_byte>
80177b6: 4603 mov r3, r0
80177b8: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80177ba: 7fbb ldrb r3, [r7, #30]
80177bc: 3301 adds r3, #1
80177be: 77bb strb r3, [r7, #30]
80177c0: 7fbb ldrb r3, [r7, #30]
80177c2: 2b02 cmp r3, #2
80177c4: d9ed bls.n 80177a2 <dhcp_renew+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80177c6: 89b8 ldrh r0, [r7, #12]
80177c8: 693b ldr r3, [r7, #16]
80177ca: 33f0 adds r3, #240 ; 0xf0
80177cc: 697a ldr r2, [r7, #20]
80177ce: 4619 mov r1, r3
80177d0: f000 ff94 bl 80186fc <dhcp_option_trailer>
result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
80177d4: 4b21 ldr r3, [pc, #132] ; (801785c <dhcp_renew+0x130>)
80177d6: 6818 ldr r0, [r3, #0]
80177d8: 69bb ldr r3, [r7, #24]
80177da: f103 0218 add.w r2, r3, #24
80177de: 687b ldr r3, [r7, #4]
80177e0: 9300 str r3, [sp, #0]
80177e2: 2343 movs r3, #67 ; 0x43
80177e4: 6979 ldr r1, [r7, #20]
80177e6: f7fe fe3f bl 8016468 <udp_sendto_if>
80177ea: 4603 mov r3, r0
80177ec: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
80177ee: 6978 ldr r0, [r7, #20]
80177f0: f7f8 fefa bl 80105e8 <pbuf_free>
80177f4: e001 b.n 80177fa <dhcp_renew+0xce>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
result = ERR_MEM;
80177f6: 23ff movs r3, #255 ; 0xff
80177f8: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
80177fa: 69bb ldr r3, [r7, #24]
80177fc: 799b ldrb r3, [r3, #6]
80177fe: 2bff cmp r3, #255 ; 0xff
8017800: d005 beq.n 801780e <dhcp_renew+0xe2>
dhcp->tries++;
8017802: 69bb ldr r3, [r7, #24]
8017804: 799b ldrb r3, [r3, #6]
8017806: 3301 adds r3, #1
8017808: b2da uxtb r2, r3
801780a: 69bb ldr r3, [r7, #24]
801780c: 719a strb r2, [r3, #6]
}
/* back-off on retries, but to a maximum of 20 seconds */
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000);
801780e: 69bb ldr r3, [r7, #24]
8017810: 799b ldrb r3, [r3, #6]
8017812: 2b09 cmp r3, #9
8017814: d80a bhi.n 801782c <dhcp_renew+0x100>
8017816: 69bb ldr r3, [r7, #24]
8017818: 799b ldrb r3, [r3, #6]
801781a: b29b uxth r3, r3
801781c: 461a mov r2, r3
801781e: 0152 lsls r2, r2, #5
8017820: 1ad2 subs r2, r2, r3
8017822: 0092 lsls r2, r2, #2
8017824: 4413 add r3, r2
8017826: 011b lsls r3, r3, #4
8017828: b29b uxth r3, r3
801782a: e001 b.n 8017830 <dhcp_renew+0x104>
801782c: f644 6320 movw r3, #20000 ; 0x4e20
8017830: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017832: 89fb ldrh r3, [r7, #14]
8017834: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017838: 4a09 ldr r2, [pc, #36] ; (8017860 <dhcp_renew+0x134>)
801783a: fb82 1203 smull r1, r2, r2, r3
801783e: 1152 asrs r2, r2, #5
8017840: 17db asrs r3, r3, #31
8017842: 1ad3 subs r3, r2, r3
8017844: b29a uxth r2, r3
8017846: 69bb ldr r3, [r7, #24]
8017848: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
return result;
801784a: f997 301f ldrsb.w r3, [r7, #31]
}
801784e: 4618 mov r0, r3
8017850: 3720 adds r7, #32
8017852: 46bd mov sp, r7
8017854: bd80 pop {r7, pc}
8017856: bf00 nop
8017858: 20000080 .word 0x20000080
801785c: 2000876c .word 0x2000876c
8017860: 10624dd3 .word 0x10624dd3
08017864 <dhcp_rebind>:
*
* @param netif network interface which must rebind with a DHCP server
*/
static err_t
dhcp_rebind(struct netif *netif)
{
8017864: b580 push {r7, lr}
8017866: b08a sub sp, #40 ; 0x28
8017868: af02 add r7, sp, #8
801786a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801786c: 687b ldr r3, [r7, #4]
801786e: 6a5b ldr r3, [r3, #36] ; 0x24
8017870: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
8017872: 2104 movs r1, #4
8017874: 69b8 ldr r0, [r7, #24]
8017876: f000 f9e1 bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
801787a: f107 030c add.w r3, r7, #12
801787e: 2203 movs r2, #3
8017880: 69b9 ldr r1, [r7, #24]
8017882: 6878 ldr r0, [r7, #4]
8017884: f000 fe64 bl 8018550 <dhcp_create_msg>
8017888: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801788a: 697b ldr r3, [r7, #20]
801788c: 2b00 cmp r3, #0
801788e: d04c beq.n 801792a <dhcp_rebind+0xc6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017890: 697b ldr r3, [r7, #20]
8017892: 685b ldr r3, [r3, #4]
8017894: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8017896: 89b8 ldrh r0, [r7, #12]
8017898: 693b ldr r3, [r7, #16]
801789a: f103 01f0 add.w r1, r3, #240 ; 0xf0
801789e: 2302 movs r3, #2
80178a0: 2239 movs r2, #57 ; 0x39
80178a2: f000 f9e5 bl 8017c70 <dhcp_option>
80178a6: 4603 mov r3, r0
80178a8: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
80178aa: 89b8 ldrh r0, [r7, #12]
80178ac: 693b ldr r3, [r7, #16]
80178ae: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178b2: 687b ldr r3, [r7, #4]
80178b4: 8d1b ldrh r3, [r3, #40] ; 0x28
80178b6: 461a mov r2, r3
80178b8: f000 fa34 bl 8017d24 <dhcp_option_short>
80178bc: 4603 mov r3, r0
80178be: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
80178c0: 89b8 ldrh r0, [r7, #12]
80178c2: 693b ldr r3, [r7, #16]
80178c4: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178c8: 2303 movs r3, #3
80178ca: 2237 movs r2, #55 ; 0x37
80178cc: f000 f9d0 bl 8017c70 <dhcp_option>
80178d0: 4603 mov r3, r0
80178d2: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80178d4: 2300 movs r3, #0
80178d6: 77bb strb r3, [r7, #30]
80178d8: e00e b.n 80178f8 <dhcp_rebind+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80178da: 89b8 ldrh r0, [r7, #12]
80178dc: 693b ldr r3, [r7, #16]
80178de: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178e2: 7fbb ldrb r3, [r7, #30]
80178e4: 4a29 ldr r2, [pc, #164] ; (801798c <dhcp_rebind+0x128>)
80178e6: 5cd3 ldrb r3, [r2, r3]
80178e8: 461a mov r2, r3
80178ea: f000 f9f5 bl 8017cd8 <dhcp_option_byte>
80178ee: 4603 mov r3, r0
80178f0: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80178f2: 7fbb ldrb r3, [r7, #30]
80178f4: 3301 adds r3, #1
80178f6: 77bb strb r3, [r7, #30]
80178f8: 7fbb ldrb r3, [r7, #30]
80178fa: 2b02 cmp r3, #2
80178fc: d9ed bls.n 80178da <dhcp_rebind+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80178fe: 89b8 ldrh r0, [r7, #12]
8017900: 693b ldr r3, [r7, #16]
8017902: 33f0 adds r3, #240 ; 0xf0
8017904: 697a ldr r2, [r7, #20]
8017906: 4619 mov r1, r3
8017908: f000 fef8 bl 80186fc <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
801790c: 4b20 ldr r3, [pc, #128] ; (8017990 <dhcp_rebind+0x12c>)
801790e: 6818 ldr r0, [r3, #0]
8017910: 687b ldr r3, [r7, #4]
8017912: 9300 str r3, [sp, #0]
8017914: 2343 movs r3, #67 ; 0x43
8017916: 4a1f ldr r2, [pc, #124] ; (8017994 <dhcp_rebind+0x130>)
8017918: 6979 ldr r1, [r7, #20]
801791a: f7fe fda5 bl 8016468 <udp_sendto_if>
801791e: 4603 mov r3, r0
8017920: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017922: 6978 ldr r0, [r7, #20]
8017924: f7f8 fe60 bl 80105e8 <pbuf_free>
8017928: e001 b.n 801792e <dhcp_rebind+0xca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
result = ERR_MEM;
801792a: 23ff movs r3, #255 ; 0xff
801792c: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
801792e: 69bb ldr r3, [r7, #24]
8017930: 799b ldrb r3, [r3, #6]
8017932: 2bff cmp r3, #255 ; 0xff
8017934: d005 beq.n 8017942 <dhcp_rebind+0xde>
dhcp->tries++;
8017936: 69bb ldr r3, [r7, #24]
8017938: 799b ldrb r3, [r3, #6]
801793a: 3301 adds r3, #1
801793c: b2da uxtb r2, r3
801793e: 69bb ldr r3, [r7, #24]
8017940: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
8017942: 69bb ldr r3, [r7, #24]
8017944: 799b ldrb r3, [r3, #6]
8017946: 2b09 cmp r3, #9
8017948: d80a bhi.n 8017960 <dhcp_rebind+0xfc>
801794a: 69bb ldr r3, [r7, #24]
801794c: 799b ldrb r3, [r3, #6]
801794e: b29b uxth r3, r3
8017950: 461a mov r2, r3
8017952: 0152 lsls r2, r2, #5
8017954: 1ad2 subs r2, r2, r3
8017956: 0092 lsls r2, r2, #2
8017958: 4413 add r3, r2
801795a: 00db lsls r3, r3, #3
801795c: b29b uxth r3, r3
801795e: e001 b.n 8017964 <dhcp_rebind+0x100>
8017960: f242 7310 movw r3, #10000 ; 0x2710
8017964: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017966: 89fb ldrh r3, [r7, #14]
8017968: f203 13f3 addw r3, r3, #499 ; 0x1f3
801796c: 4a0a ldr r2, [pc, #40] ; (8017998 <dhcp_rebind+0x134>)
801796e: fb82 1203 smull r1, r2, r2, r3
8017972: 1152 asrs r2, r2, #5
8017974: 17db asrs r3, r3, #31
8017976: 1ad3 subs r3, r2, r3
8017978: b29a uxth r2, r3
801797a: 69bb ldr r3, [r7, #24]
801797c: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
return result;
801797e: f997 301f ldrsb.w r3, [r7, #31]
}
8017982: 4618 mov r0, r3
8017984: 3720 adds r7, #32
8017986: 46bd mov sp, r7
8017988: bd80 pop {r7, pc}
801798a: bf00 nop
801798c: 20000080 .word 0x20000080
8017990: 2000876c .word 0x2000876c
8017994: 08020e6c .word 0x08020e6c
8017998: 10624dd3 .word 0x10624dd3
0801799c <dhcp_reboot>:
*
* @param netif network interface which must reboot
*/
static err_t
dhcp_reboot(struct netif *netif)
{
801799c: b5b0 push {r4, r5, r7, lr}
801799e: b08a sub sp, #40 ; 0x28
80179a0: af02 add r7, sp, #8
80179a2: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
80179a4: 687b ldr r3, [r7, #4]
80179a6: 6a5b ldr r3, [r3, #36] ; 0x24
80179a8: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
80179aa: 2103 movs r1, #3
80179ac: 69b8 ldr r0, [r7, #24]
80179ae: f000 f945 bl 8017c3c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
80179b2: f107 030c add.w r3, r7, #12
80179b6: 2203 movs r2, #3
80179b8: 69b9 ldr r1, [r7, #24]
80179ba: 6878 ldr r0, [r7, #4]
80179bc: f000 fdc8 bl 8018550 <dhcp_create_msg>
80179c0: 6178 str r0, [r7, #20]
if (p_out != NULL) {
80179c2: 697b ldr r3, [r7, #20]
80179c4: 2b00 cmp r3, #0
80179c6: d066 beq.n 8017a96 <dhcp_reboot+0xfa>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
80179c8: 697b ldr r3, [r7, #20]
80179ca: 685b ldr r3, [r3, #4]
80179cc: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
80179ce: 89b8 ldrh r0, [r7, #12]
80179d0: 693b ldr r3, [r7, #16]
80179d2: f103 01f0 add.w r1, r3, #240 ; 0xf0
80179d6: 2302 movs r3, #2
80179d8: 2239 movs r2, #57 ; 0x39
80179da: f000 f949 bl 8017c70 <dhcp_option>
80179de: 4603 mov r3, r0
80179e0: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED);
80179e2: 89b8 ldrh r0, [r7, #12]
80179e4: 693b ldr r3, [r7, #16]
80179e6: 33f0 adds r3, #240 ; 0xf0
80179e8: f44f 7210 mov.w r2, #576 ; 0x240
80179ec: 4619 mov r1, r3
80179ee: f000 f999 bl 8017d24 <dhcp_option_short>
80179f2: 4603 mov r3, r0
80179f4: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
80179f6: 89b8 ldrh r0, [r7, #12]
80179f8: 693b ldr r3, [r7, #16]
80179fa: f103 01f0 add.w r1, r3, #240 ; 0xf0
80179fe: 2304 movs r3, #4
8017a00: 2232 movs r2, #50 ; 0x32
8017a02: f000 f935 bl 8017c70 <dhcp_option>
8017a06: 4603 mov r3, r0
8017a08: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
8017a0a: 89bc ldrh r4, [r7, #12]
8017a0c: 693b ldr r3, [r7, #16]
8017a0e: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017a12: 69bb ldr r3, [r7, #24]
8017a14: 69db ldr r3, [r3, #28]
8017a16: 4618 mov r0, r3
8017a18: f7f7 fa47 bl 800eeaa <lwip_htonl>
8017a1c: 4603 mov r3, r0
8017a1e: 461a mov r2, r3
8017a20: 4629 mov r1, r5
8017a22: 4620 mov r0, r4
8017a24: f000 f9b0 bl 8017d88 <dhcp_option_long>
8017a28: 4603 mov r3, r0
8017a2a: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017a2c: 89b8 ldrh r0, [r7, #12]
8017a2e: 693b ldr r3, [r7, #16]
8017a30: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017a34: 2303 movs r3, #3
8017a36: 2237 movs r2, #55 ; 0x37
8017a38: f000 f91a bl 8017c70 <dhcp_option>
8017a3c: 4603 mov r3, r0
8017a3e: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017a40: 2300 movs r3, #0
8017a42: 77bb strb r3, [r7, #30]
8017a44: e00e b.n 8017a64 <dhcp_reboot+0xc8>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8017a46: 89b8 ldrh r0, [r7, #12]
8017a48: 693b ldr r3, [r7, #16]
8017a4a: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017a4e: 7fbb ldrb r3, [r7, #30]
8017a50: 4a29 ldr r2, [pc, #164] ; (8017af8 <dhcp_reboot+0x15c>)
8017a52: 5cd3 ldrb r3, [r2, r3]
8017a54: 461a mov r2, r3
8017a56: f000 f93f bl 8017cd8 <dhcp_option_byte>
8017a5a: 4603 mov r3, r0
8017a5c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017a5e: 7fbb ldrb r3, [r7, #30]
8017a60: 3301 adds r3, #1
8017a62: 77bb strb r3, [r7, #30]
8017a64: 7fbb ldrb r3, [r7, #30]
8017a66: 2b02 cmp r3, #2
8017a68: d9ed bls.n 8017a46 <dhcp_reboot+0xaa>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017a6a: 89b8 ldrh r0, [r7, #12]
8017a6c: 693b ldr r3, [r7, #16]
8017a6e: 33f0 adds r3, #240 ; 0xf0
8017a70: 697a ldr r2, [r7, #20]
8017a72: 4619 mov r1, r3
8017a74: f000 fe42 bl 80186fc <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017a78: 4b20 ldr r3, [pc, #128] ; (8017afc <dhcp_reboot+0x160>)
8017a7a: 6818 ldr r0, [r3, #0]
8017a7c: 687b ldr r3, [r7, #4]
8017a7e: 9300 str r3, [sp, #0]
8017a80: 2343 movs r3, #67 ; 0x43
8017a82: 4a1f ldr r2, [pc, #124] ; (8017b00 <dhcp_reboot+0x164>)
8017a84: 6979 ldr r1, [r7, #20]
8017a86: f7fe fcef bl 8016468 <udp_sendto_if>
8017a8a: 4603 mov r3, r0
8017a8c: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017a8e: 6978 ldr r0, [r7, #20]
8017a90: f7f8 fdaa bl 80105e8 <pbuf_free>
8017a94: e001 b.n 8017a9a <dhcp_reboot+0xfe>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
result = ERR_MEM;
8017a96: 23ff movs r3, #255 ; 0xff
8017a98: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8017a9a: 69bb ldr r3, [r7, #24]
8017a9c: 799b ldrb r3, [r3, #6]
8017a9e: 2bff cmp r3, #255 ; 0xff
8017aa0: d005 beq.n 8017aae <dhcp_reboot+0x112>
dhcp->tries++;
8017aa2: 69bb ldr r3, [r7, #24]
8017aa4: 799b ldrb r3, [r3, #6]
8017aa6: 3301 adds r3, #1
8017aa8: b2da uxtb r2, r3
8017aaa: 69bb ldr r3, [r7, #24]
8017aac: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
8017aae: 69bb ldr r3, [r7, #24]
8017ab0: 799b ldrb r3, [r3, #6]
8017ab2: 2b09 cmp r3, #9
8017ab4: d80a bhi.n 8017acc <dhcp_reboot+0x130>
8017ab6: 69bb ldr r3, [r7, #24]
8017ab8: 799b ldrb r3, [r3, #6]
8017aba: b29b uxth r3, r3
8017abc: 461a mov r2, r3
8017abe: 0152 lsls r2, r2, #5
8017ac0: 1ad2 subs r2, r2, r3
8017ac2: 0092 lsls r2, r2, #2
8017ac4: 4413 add r3, r2
8017ac6: 00db lsls r3, r3, #3
8017ac8: b29b uxth r3, r3
8017aca: e001 b.n 8017ad0 <dhcp_reboot+0x134>
8017acc: f242 7310 movw r3, #10000 ; 0x2710
8017ad0: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017ad2: 89fb ldrh r3, [r7, #14]
8017ad4: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017ad8: 4a0a ldr r2, [pc, #40] ; (8017b04 <dhcp_reboot+0x168>)
8017ada: fb82 1203 smull r1, r2, r2, r3
8017ade: 1152 asrs r2, r2, #5
8017ae0: 17db asrs r3, r3, #31
8017ae2: 1ad3 subs r3, r2, r3
8017ae4: b29a uxth r2, r3
8017ae6: 69bb ldr r3, [r7, #24]
8017ae8: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017aea: f997 301f ldrsb.w r3, [r7, #31]
}
8017aee: 4618 mov r0, r3
8017af0: 3720 adds r7, #32
8017af2: 46bd mov sp, r7
8017af4: bdb0 pop {r4, r5, r7, pc}
8017af6: bf00 nop
8017af8: 20000080 .word 0x20000080
8017afc: 2000876c .word 0x2000876c
8017b00: 08020e6c .word 0x08020e6c
8017b04: 10624dd3 .word 0x10624dd3
08017b08 <dhcp_release_and_stop>:
*
* @param netif network interface
*/
void
dhcp_release_and_stop(struct netif *netif)
{
8017b08: b5b0 push {r4, r5, r7, lr}
8017b0a: b08a sub sp, #40 ; 0x28
8017b0c: af02 add r7, sp, #8
8017b0e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017b10: 687b ldr r3, [r7, #4]
8017b12: 6a5b ldr r3, [r3, #36] ; 0x24
8017b14: 61fb str r3, [r7, #28]
ip_addr_t server_ip_addr;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n"));
if (dhcp == NULL) {
8017b16: 69fb ldr r3, [r7, #28]
8017b18: 2b00 cmp r3, #0
8017b1a: f000 8084 beq.w 8017c26 <dhcp_release_and_stop+0x11e>
return;
}
/* already off? -> nothing to do */
if (dhcp->state == DHCP_STATE_OFF) {
8017b1e: 69fb ldr r3, [r7, #28]
8017b20: 795b ldrb r3, [r3, #5]
8017b22: 2b00 cmp r3, #0
8017b24: f000 8081 beq.w 8017c2a <dhcp_release_and_stop+0x122>
return;
}
ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
8017b28: 69fb ldr r3, [r7, #28]
8017b2a: 699b ldr r3, [r3, #24]
8017b2c: 613b str r3, [r7, #16]
/* clean old DHCP offer */
ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
8017b2e: 69fb ldr r3, [r7, #28]
8017b30: 2200 movs r2, #0
8017b32: 619a str r2, [r3, #24]
ip4_addr_set_zero(&dhcp->offered_ip_addr);
8017b34: 69fb ldr r3, [r7, #28]
8017b36: 2200 movs r2, #0
8017b38: 61da str r2, [r3, #28]
ip4_addr_set_zero(&dhcp->offered_sn_mask);
8017b3a: 69fb ldr r3, [r7, #28]
8017b3c: 2200 movs r2, #0
8017b3e: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
8017b40: 69fb ldr r3, [r7, #28]
8017b42: 2200 movs r2, #0
8017b44: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
8017b46: 69fb ldr r3, [r7, #28]
8017b48: 2200 movs r2, #0
8017b4a: 631a str r2, [r3, #48] ; 0x30
8017b4c: 69fb ldr r3, [r7, #28]
8017b4e: 6b1a ldr r2, [r3, #48] ; 0x30
8017b50: 69fb ldr r3, [r7, #28]
8017b52: 62da str r2, [r3, #44] ; 0x2c
8017b54: 69fb ldr r3, [r7, #28]
8017b56: 6ada ldr r2, [r3, #44] ; 0x2c
8017b58: 69fb ldr r3, [r7, #28]
8017b5a: 629a str r2, [r3, #40] ; 0x28
dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
8017b5c: 69fb ldr r3, [r7, #28]
8017b5e: 2200 movs r2, #0
8017b60: 829a strh r2, [r3, #20]
8017b62: 69fb ldr r3, [r7, #28]
8017b64: 8a9a ldrh r2, [r3, #20]
8017b66: 69fb ldr r3, [r7, #28]
8017b68: 825a strh r2, [r3, #18]
8017b6a: 69fb ldr r3, [r7, #28]
8017b6c: 8a5a ldrh r2, [r3, #18]
8017b6e: 69fb ldr r3, [r7, #28]
8017b70: 821a strh r2, [r3, #16]
8017b72: 69fb ldr r3, [r7, #28]
8017b74: 8a1a ldrh r2, [r3, #16]
8017b76: 69fb ldr r3, [r7, #28]
8017b78: 81da strh r2, [r3, #14]
/* send release message when current IP was assigned via DHCP */
if (dhcp_supplied_address(netif)) {
8017b7a: 6878 ldr r0, [r7, #4]
8017b7c: f000 fdec bl 8018758 <dhcp_supplied_address>
8017b80: 4603 mov r3, r0
8017b82: 2b00 cmp r3, #0
8017b84: d03b beq.n 8017bfe <dhcp_release_and_stop+0xf6>
/* create and initialize the DHCP message header */
struct pbuf *p_out;
u16_t options_out_len;
p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len);
8017b86: f107 030e add.w r3, r7, #14
8017b8a: 2207 movs r2, #7
8017b8c: 69f9 ldr r1, [r7, #28]
8017b8e: 6878 ldr r0, [r7, #4]
8017b90: f000 fcde bl 8018550 <dhcp_create_msg>
8017b94: 61b8 str r0, [r7, #24]
if (p_out != NULL) {
8017b96: 69bb ldr r3, [r7, #24]
8017b98: 2b00 cmp r3, #0
8017b9a: d030 beq.n 8017bfe <dhcp_release_and_stop+0xf6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017b9c: 69bb ldr r3, [r7, #24]
8017b9e: 685b ldr r3, [r3, #4]
8017ba0: 617b str r3, [r7, #20]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8017ba2: 89f8 ldrh r0, [r7, #14]
8017ba4: 697b ldr r3, [r7, #20]
8017ba6: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017baa: 2304 movs r3, #4
8017bac: 2236 movs r2, #54 ; 0x36
8017bae: f000 f85f bl 8017c70 <dhcp_option>
8017bb2: 4603 mov r3, r0
8017bb4: 81fb strh r3, [r7, #14]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
8017bb6: 89fc ldrh r4, [r7, #14]
8017bb8: 697b ldr r3, [r7, #20]
8017bba: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017bbe: 693b ldr r3, [r7, #16]
8017bc0: 4618 mov r0, r3
8017bc2: f7f7 f972 bl 800eeaa <lwip_htonl>
8017bc6: 4603 mov r3, r0
8017bc8: 461a mov r2, r3
8017bca: 4629 mov r1, r5
8017bcc: 4620 mov r0, r4
8017bce: f000 f8db bl 8017d88 <dhcp_option_long>
8017bd2: 4603 mov r3, r0
8017bd4: 81fb strh r3, [r7, #14]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017bd6: 89f8 ldrh r0, [r7, #14]
8017bd8: 697b ldr r3, [r7, #20]
8017bda: 33f0 adds r3, #240 ; 0xf0
8017bdc: 69ba ldr r2, [r7, #24]
8017bde: 4619 mov r1, r3
8017be0: f000 fd8c bl 80186fc <dhcp_option_trailer>
udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017be4: 4b13 ldr r3, [pc, #76] ; (8017c34 <dhcp_release_and_stop+0x12c>)
8017be6: 6818 ldr r0, [r3, #0]
8017be8: f107 0210 add.w r2, r7, #16
8017bec: 687b ldr r3, [r7, #4]
8017bee: 9300 str r3, [sp, #0]
8017bf0: 2343 movs r3, #67 ; 0x43
8017bf2: 69b9 ldr r1, [r7, #24]
8017bf4: f7fe fc38 bl 8016468 <udp_sendto_if>
pbuf_free(p_out);
8017bf8: 69b8 ldr r0, [r7, #24]
8017bfa: f7f8 fcf5 bl 80105e8 <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
}
}
/* remove IP address from interface (prevents routing from selecting this interface) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8017bfe: 4b0e ldr r3, [pc, #56] ; (8017c38 <dhcp_release_and_stop+0x130>)
8017c00: 4a0d ldr r2, [pc, #52] ; (8017c38 <dhcp_release_and_stop+0x130>)
8017c02: 490d ldr r1, [pc, #52] ; (8017c38 <dhcp_release_and_stop+0x130>)
8017c04: 6878 ldr r0, [r7, #4]
8017c06: f7f7 ffe5 bl 800fbd4 <netif_set_addr>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
dhcp_set_state(dhcp, DHCP_STATE_OFF);
8017c0a: 2100 movs r1, #0
8017c0c: 69f8 ldr r0, [r7, #28]
8017c0e: f000 f815 bl 8017c3c <dhcp_set_state>
if (dhcp->pcb_allocated != 0) {
8017c12: 69fb ldr r3, [r7, #28]
8017c14: 791b ldrb r3, [r3, #4]
8017c16: 2b00 cmp r3, #0
8017c18: d008 beq.n 8017c2c <dhcp_release_and_stop+0x124>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
8017c1a: f7fe ff71 bl 8016b00 <dhcp_dec_pcb_refcount>
dhcp->pcb_allocated = 0;
8017c1e: 69fb ldr r3, [r7, #28]
8017c20: 2200 movs r2, #0
8017c22: 711a strb r2, [r3, #4]
8017c24: e002 b.n 8017c2c <dhcp_release_and_stop+0x124>
return;
8017c26: bf00 nop
8017c28: e000 b.n 8017c2c <dhcp_release_and_stop+0x124>
return;
8017c2a: bf00 nop
}
}
8017c2c: 3720 adds r7, #32
8017c2e: 46bd mov sp, r7
8017c30: bdb0 pop {r4, r5, r7, pc}
8017c32: bf00 nop
8017c34: 2000876c .word 0x2000876c
8017c38: 08020e68 .word 0x08020e68
08017c3c <dhcp_set_state>:
*
* If the state changed, reset the number of tries.
*/
static void
dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
{
8017c3c: b480 push {r7}
8017c3e: b083 sub sp, #12
8017c40: af00 add r7, sp, #0
8017c42: 6078 str r0, [r7, #4]
8017c44: 460b mov r3, r1
8017c46: 70fb strb r3, [r7, #3]
if (new_state != dhcp->state) {
8017c48: 687b ldr r3, [r7, #4]
8017c4a: 795b ldrb r3, [r3, #5]
8017c4c: 78fa ldrb r2, [r7, #3]
8017c4e: 429a cmp r2, r3
8017c50: d008 beq.n 8017c64 <dhcp_set_state+0x28>
dhcp->state = new_state;
8017c52: 687b ldr r3, [r7, #4]
8017c54: 78fa ldrb r2, [r7, #3]
8017c56: 715a strb r2, [r3, #5]
dhcp->tries = 0;
8017c58: 687b ldr r3, [r7, #4]
8017c5a: 2200 movs r2, #0
8017c5c: 719a strb r2, [r3, #6]
dhcp->request_timeout = 0;
8017c5e: 687b ldr r3, [r7, #4]
8017c60: 2200 movs r2, #0
8017c62: 811a strh r2, [r3, #8]
}
}
8017c64: bf00 nop
8017c66: 370c adds r7, #12
8017c68: 46bd mov sp, r7
8017c6a: f85d 7b04 ldr.w r7, [sp], #4
8017c6e: 4770 bx lr
08017c70 <dhcp_option>:
* DHCP message.
*
*/
static u16_t
dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len)
{
8017c70: b580 push {r7, lr}
8017c72: b082 sub sp, #8
8017c74: af00 add r7, sp, #0
8017c76: 6039 str r1, [r7, #0]
8017c78: 4611 mov r1, r2
8017c7a: 461a mov r2, r3
8017c7c: 4603 mov r3, r0
8017c7e: 80fb strh r3, [r7, #6]
8017c80: 460b mov r3, r1
8017c82: 717b strb r3, [r7, #5]
8017c84: 4613 mov r3, r2
8017c86: 713b strb r3, [r7, #4]
LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
8017c88: 88fa ldrh r2, [r7, #6]
8017c8a: 793b ldrb r3, [r7, #4]
8017c8c: 4413 add r3, r2
8017c8e: 3302 adds r3, #2
8017c90: 2b44 cmp r3, #68 ; 0x44
8017c92: d906 bls.n 8017ca2 <dhcp_option+0x32>
8017c94: 4b0d ldr r3, [pc, #52] ; (8017ccc <dhcp_option+0x5c>)
8017c96: f240 529a movw r2, #1434 ; 0x59a
8017c9a: 490d ldr r1, [pc, #52] ; (8017cd0 <dhcp_option+0x60>)
8017c9c: 480d ldr r0, [pc, #52] ; (8017cd4 <dhcp_option+0x64>)
8017c9e: f003 f9b9 bl 801b014 <iprintf>
options[options_out_len++] = option_type;
8017ca2: 88fb ldrh r3, [r7, #6]
8017ca4: 1c5a adds r2, r3, #1
8017ca6: 80fa strh r2, [r7, #6]
8017ca8: 461a mov r2, r3
8017caa: 683b ldr r3, [r7, #0]
8017cac: 4413 add r3, r2
8017cae: 797a ldrb r2, [r7, #5]
8017cb0: 701a strb r2, [r3, #0]
options[options_out_len++] = option_len;
8017cb2: 88fb ldrh r3, [r7, #6]
8017cb4: 1c5a adds r2, r3, #1
8017cb6: 80fa strh r2, [r7, #6]
8017cb8: 461a mov r2, r3
8017cba: 683b ldr r3, [r7, #0]
8017cbc: 4413 add r3, r2
8017cbe: 793a ldrb r2, [r7, #4]
8017cc0: 701a strb r2, [r3, #0]
return options_out_len;
8017cc2: 88fb ldrh r3, [r7, #6]
}
8017cc4: 4618 mov r0, r3
8017cc6: 3708 adds r7, #8
8017cc8: 46bd mov sp, r7
8017cca: bd80 pop {r7, pc}
8017ccc: 0801e398 .word 0x0801e398
8017cd0: 0801e52c .word 0x0801e52c
8017cd4: 0801e3f8 .word 0x0801e3f8
08017cd8 <dhcp_option_byte>:
* Concatenate a single byte to the outgoing DHCP message.
*
*/
static u16_t
dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value)
{
8017cd8: b580 push {r7, lr}
8017cda: b082 sub sp, #8
8017cdc: af00 add r7, sp, #0
8017cde: 4603 mov r3, r0
8017ce0: 6039 str r1, [r7, #0]
8017ce2: 80fb strh r3, [r7, #6]
8017ce4: 4613 mov r3, r2
8017ce6: 717b strb r3, [r7, #5]
LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN);
8017ce8: 88fb ldrh r3, [r7, #6]
8017cea: 2b43 cmp r3, #67 ; 0x43
8017cec: d906 bls.n 8017cfc <dhcp_option_byte+0x24>
8017cee: 4b0a ldr r3, [pc, #40] ; (8017d18 <dhcp_option_byte+0x40>)
8017cf0: f240 52a6 movw r2, #1446 ; 0x5a6
8017cf4: 4909 ldr r1, [pc, #36] ; (8017d1c <dhcp_option_byte+0x44>)
8017cf6: 480a ldr r0, [pc, #40] ; (8017d20 <dhcp_option_byte+0x48>)
8017cf8: f003 f98c bl 801b014 <iprintf>
options[options_out_len++] = value;
8017cfc: 88fb ldrh r3, [r7, #6]
8017cfe: 1c5a adds r2, r3, #1
8017d00: 80fa strh r2, [r7, #6]
8017d02: 461a mov r2, r3
8017d04: 683b ldr r3, [r7, #0]
8017d06: 4413 add r3, r2
8017d08: 797a ldrb r2, [r7, #5]
8017d0a: 701a strb r2, [r3, #0]
return options_out_len;
8017d0c: 88fb ldrh r3, [r7, #6]
}
8017d0e: 4618 mov r0, r3
8017d10: 3708 adds r7, #8
8017d12: 46bd mov sp, r7
8017d14: bd80 pop {r7, pc}
8017d16: bf00 nop
8017d18: 0801e398 .word 0x0801e398
8017d1c: 0801e570 .word 0x0801e570
8017d20: 0801e3f8 .word 0x0801e3f8
08017d24 <dhcp_option_short>:
static u16_t
dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value)
{
8017d24: b580 push {r7, lr}
8017d26: b082 sub sp, #8
8017d28: af00 add r7, sp, #0
8017d2a: 4603 mov r3, r0
8017d2c: 6039 str r1, [r7, #0]
8017d2e: 80fb strh r3, [r7, #6]
8017d30: 4613 mov r3, r2
8017d32: 80bb strh r3, [r7, #4]
LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN);
8017d34: 88fb ldrh r3, [r7, #6]
8017d36: 3302 adds r3, #2
8017d38: 2b44 cmp r3, #68 ; 0x44
8017d3a: d906 bls.n 8017d4a <dhcp_option_short+0x26>
8017d3c: 4b0f ldr r3, [pc, #60] ; (8017d7c <dhcp_option_short+0x58>)
8017d3e: f240 52ae movw r2, #1454 ; 0x5ae
8017d42: 490f ldr r1, [pc, #60] ; (8017d80 <dhcp_option_short+0x5c>)
8017d44: 480f ldr r0, [pc, #60] ; (8017d84 <dhcp_option_short+0x60>)
8017d46: f003 f965 bl 801b014 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
8017d4a: 88bb ldrh r3, [r7, #4]
8017d4c: 0a1b lsrs r3, r3, #8
8017d4e: b29a uxth r2, r3
8017d50: 88fb ldrh r3, [r7, #6]
8017d52: 1c59 adds r1, r3, #1
8017d54: 80f9 strh r1, [r7, #6]
8017d56: 4619 mov r1, r3
8017d58: 683b ldr r3, [r7, #0]
8017d5a: 440b add r3, r1
8017d5c: b2d2 uxtb r2, r2
8017d5e: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t) (value & 0x00ffU);
8017d60: 88fb ldrh r3, [r7, #6]
8017d62: 1c5a adds r2, r3, #1
8017d64: 80fa strh r2, [r7, #6]
8017d66: 461a mov r2, r3
8017d68: 683b ldr r3, [r7, #0]
8017d6a: 4413 add r3, r2
8017d6c: 88ba ldrh r2, [r7, #4]
8017d6e: b2d2 uxtb r2, r2
8017d70: 701a strb r2, [r3, #0]
return options_out_len;
8017d72: 88fb ldrh r3, [r7, #6]
}
8017d74: 4618 mov r0, r3
8017d76: 3708 adds r7, #8
8017d78: 46bd mov sp, r7
8017d7a: bd80 pop {r7, pc}
8017d7c: 0801e398 .word 0x0801e398
8017d80: 0801e5a8 .word 0x0801e5a8
8017d84: 0801e3f8 .word 0x0801e3f8
08017d88 <dhcp_option_long>:
static u16_t
dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value)
{
8017d88: b580 push {r7, lr}
8017d8a: b084 sub sp, #16
8017d8c: af00 add r7, sp, #0
8017d8e: 4603 mov r3, r0
8017d90: 60b9 str r1, [r7, #8]
8017d92: 607a str r2, [r7, #4]
8017d94: 81fb strh r3, [r7, #14]
LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN);
8017d96: 89fb ldrh r3, [r7, #14]
8017d98: 3304 adds r3, #4
8017d9a: 2b44 cmp r3, #68 ; 0x44
8017d9c: d906 bls.n 8017dac <dhcp_option_long+0x24>
8017d9e: 4b19 ldr r3, [pc, #100] ; (8017e04 <dhcp_option_long+0x7c>)
8017da0: f240 52b7 movw r2, #1463 ; 0x5b7
8017da4: 4918 ldr r1, [pc, #96] ; (8017e08 <dhcp_option_long+0x80>)
8017da6: 4819 ldr r0, [pc, #100] ; (8017e0c <dhcp_option_long+0x84>)
8017da8: f003 f934 bl 801b014 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
8017dac: 687b ldr r3, [r7, #4]
8017dae: 0e1a lsrs r2, r3, #24
8017db0: 89fb ldrh r3, [r7, #14]
8017db2: 1c59 adds r1, r3, #1
8017db4: 81f9 strh r1, [r7, #14]
8017db6: 4619 mov r1, r3
8017db8: 68bb ldr r3, [r7, #8]
8017dba: 440b add r3, r1
8017dbc: b2d2 uxtb r2, r2
8017dbe: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
8017dc0: 687b ldr r3, [r7, #4]
8017dc2: 0c1a lsrs r2, r3, #16
8017dc4: 89fb ldrh r3, [r7, #14]
8017dc6: 1c59 adds r1, r3, #1
8017dc8: 81f9 strh r1, [r7, #14]
8017dca: 4619 mov r1, r3
8017dcc: 68bb ldr r3, [r7, #8]
8017dce: 440b add r3, r1
8017dd0: b2d2 uxtb r2, r2
8017dd2: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
8017dd4: 687b ldr r3, [r7, #4]
8017dd6: 0a1a lsrs r2, r3, #8
8017dd8: 89fb ldrh r3, [r7, #14]
8017dda: 1c59 adds r1, r3, #1
8017ddc: 81f9 strh r1, [r7, #14]
8017dde: 4619 mov r1, r3
8017de0: 68bb ldr r3, [r7, #8]
8017de2: 440b add r3, r1
8017de4: b2d2 uxtb r2, r2
8017de6: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x000000ffUL));
8017de8: 89fb ldrh r3, [r7, #14]
8017dea: 1c5a adds r2, r3, #1
8017dec: 81fa strh r2, [r7, #14]
8017dee: 461a mov r2, r3
8017df0: 68bb ldr r3, [r7, #8]
8017df2: 4413 add r3, r2
8017df4: 687a ldr r2, [r7, #4]
8017df6: b2d2 uxtb r2, r2
8017df8: 701a strb r2, [r3, #0]
return options_out_len;
8017dfa: 89fb ldrh r3, [r7, #14]
}
8017dfc: 4618 mov r0, r3
8017dfe: 3710 adds r7, #16
8017e00: 46bd mov sp, r7
8017e02: bd80 pop {r7, pc}
8017e04: 0801e398 .word 0x0801e398
8017e08: 0801e5e4 .word 0x0801e5e4
8017e0c: 0801e3f8 .word 0x0801e3f8
08017e10 <dhcp_parse_reply>:
* use that further on.
*
*/
static err_t
dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp)
{
8017e10: b580 push {r7, lr}
8017e12: b090 sub sp, #64 ; 0x40
8017e14: af00 add r7, sp, #0
8017e16: 6078 str r0, [r7, #4]
8017e18: 6039 str r1, [r7, #0]
u16_t offset;
u16_t offset_max;
u16_t options_idx;
u16_t options_idx_max;
struct pbuf *q;
int parse_file_as_options = 0;
8017e1a: 2300 movs r3, #0
8017e1c: 62fb str r3, [r7, #44] ; 0x2c
int parse_sname_as_options = 0;
8017e1e: 2300 movs r3, #0
8017e20: 62bb str r3, [r7, #40] ; 0x28
#endif
LWIP_UNUSED_ARG(dhcp);
/* clear received options */
dhcp_clear_all_options(dhcp);
8017e22: 2208 movs r2, #8
8017e24: 2100 movs r1, #0
8017e26: 48be ldr r0, [pc, #760] ; (8018120 <dhcp_parse_reply+0x310>)
8017e28: f003 f8ec bl 801b004 <memset>
/* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
if (p->len < DHCP_SNAME_OFS) {
8017e2c: 687b ldr r3, [r7, #4]
8017e2e: 895b ldrh r3, [r3, #10]
8017e30: 2b2b cmp r3, #43 ; 0x2b
8017e32: d802 bhi.n 8017e3a <dhcp_parse_reply+0x2a>
return ERR_BUF;
8017e34: f06f 0301 mvn.w r3, #1
8017e38: e2a8 b.n 801838c <dhcp_parse_reply+0x57c>
}
msg_in = (struct dhcp_msg *)p->payload;
8017e3a: 687b ldr r3, [r7, #4]
8017e3c: 685b ldr r3, [r3, #4]
8017e3e: 61bb str r3, [r7, #24]
#endif /* LWIP_DHCP_BOOTP_FILE */
/* parse options */
/* start with options field */
options_idx = DHCP_OPTIONS_OFS;
8017e40: 23f0 movs r3, #240 ; 0xf0
8017e42: 86fb strh r3, [r7, #54] ; 0x36
/* parse options to the end of the received packet */
options_idx_max = p->tot_len;
8017e44: 687b ldr r3, [r7, #4]
8017e46: 891b ldrh r3, [r3, #8]
8017e48: 86bb strh r3, [r7, #52] ; 0x34
again:
q = p;
8017e4a: 687b ldr r3, [r7, #4]
8017e4c: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017e4e: e00c b.n 8017e6a <dhcp_parse_reply+0x5a>
options_idx = (u16_t)(options_idx - q->len);
8017e50: 6b3b ldr r3, [r7, #48] ; 0x30
8017e52: 895b ldrh r3, [r3, #10]
8017e54: 8efa ldrh r2, [r7, #54] ; 0x36
8017e56: 1ad3 subs r3, r2, r3
8017e58: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = (u16_t)(options_idx_max - q->len);
8017e5a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e5c: 895b ldrh r3, [r3, #10]
8017e5e: 8eba ldrh r2, [r7, #52] ; 0x34
8017e60: 1ad3 subs r3, r2, r3
8017e62: 86bb strh r3, [r7, #52] ; 0x34
q = q->next;
8017e64: 6b3b ldr r3, [r7, #48] ; 0x30
8017e66: 681b ldr r3, [r3, #0]
8017e68: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017e6a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e6c: 2b00 cmp r3, #0
8017e6e: d004 beq.n 8017e7a <dhcp_parse_reply+0x6a>
8017e70: 6b3b ldr r3, [r7, #48] ; 0x30
8017e72: 895b ldrh r3, [r3, #10]
8017e74: 8efa ldrh r2, [r7, #54] ; 0x36
8017e76: 429a cmp r2, r3
8017e78: d2ea bcs.n 8017e50 <dhcp_parse_reply+0x40>
}
if (q == NULL) {
8017e7a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e7c: 2b00 cmp r3, #0
8017e7e: d102 bne.n 8017e86 <dhcp_parse_reply+0x76>
return ERR_BUF;
8017e80: f06f 0301 mvn.w r3, #1
8017e84: e282 b.n 801838c <dhcp_parse_reply+0x57c>
}
offset = options_idx;
8017e86: 8efb ldrh r3, [r7, #54] ; 0x36
8017e88: 877b strh r3, [r7, #58] ; 0x3a
offset_max = options_idx_max;
8017e8a: 8ebb ldrh r3, [r7, #52] ; 0x34
8017e8c: 873b strh r3, [r7, #56] ; 0x38
options = (u8_t *)q->payload;
8017e8e: 6b3b ldr r3, [r7, #48] ; 0x30
8017e90: 685b ldr r3, [r3, #4]
8017e92: 63fb str r3, [r7, #60] ; 0x3c
/* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
8017e94: e23a b.n 801830c <dhcp_parse_reply+0x4fc>
u8_t op = options[offset];
8017e96: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017e98: 6bfa ldr r2, [r7, #60] ; 0x3c
8017e9a: 4413 add r3, r2
8017e9c: 781b ldrb r3, [r3, #0]
8017e9e: 75fb strb r3, [r7, #23]
u8_t len;
u8_t decode_len = 0;
8017ea0: 2300 movs r3, #0
8017ea2: f887 3026 strb.w r3, [r7, #38] ; 0x26
int decode_idx = -1;
8017ea6: f04f 33ff mov.w r3, #4294967295
8017eaa: 623b str r3, [r7, #32]
u16_t val_offset = (u16_t)(offset + 2);
8017eac: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017eae: 3302 adds r3, #2
8017eb0: 83fb strh r3, [r7, #30]
if (val_offset < offset) {
8017eb2: 8bfa ldrh r2, [r7, #30]
8017eb4: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017eb6: 429a cmp r2, r3
8017eb8: d202 bcs.n 8017ec0 <dhcp_parse_reply+0xb0>
/* overflow */
return ERR_BUF;
8017eba: f06f 0301 mvn.w r3, #1
8017ebe: e265 b.n 801838c <dhcp_parse_reply+0x57c>
}
/* len byte might be in the next pbuf */
if ((offset + 1) < q->len) {
8017ec0: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ec2: 3301 adds r3, #1
8017ec4: 6b3a ldr r2, [r7, #48] ; 0x30
8017ec6: 8952 ldrh r2, [r2, #10]
8017ec8: 4293 cmp r3, r2
8017eca: da07 bge.n 8017edc <dhcp_parse_reply+0xcc>
len = options[offset + 1];
8017ecc: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ece: 3301 adds r3, #1
8017ed0: 6bfa ldr r2, [r7, #60] ; 0x3c
8017ed2: 4413 add r3, r2
8017ed4: 781b ldrb r3, [r3, #0]
8017ed6: f887 3027 strb.w r3, [r7, #39] ; 0x27
8017eda: e00b b.n 8017ef4 <dhcp_parse_reply+0xe4>
} else {
len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0);
8017edc: 6b3b ldr r3, [r7, #48] ; 0x30
8017ede: 681b ldr r3, [r3, #0]
8017ee0: 2b00 cmp r3, #0
8017ee2: d004 beq.n 8017eee <dhcp_parse_reply+0xde>
8017ee4: 6b3b ldr r3, [r7, #48] ; 0x30
8017ee6: 681b ldr r3, [r3, #0]
8017ee8: 685b ldr r3, [r3, #4]
8017eea: 781b ldrb r3, [r3, #0]
8017eec: e000 b.n 8017ef0 <dhcp_parse_reply+0xe0>
8017eee: 2300 movs r3, #0
8017ef0: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
decode_len = len;
8017ef4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017ef8: f887 3026 strb.w r3, [r7, #38] ; 0x26
switch (op) {
8017efc: 7dfb ldrb r3, [r7, #23]
8017efe: 2b3b cmp r3, #59 ; 0x3b
8017f00: f200 812d bhi.w 801815e <dhcp_parse_reply+0x34e>
8017f04: a201 add r2, pc, #4 ; (adr r2, 8017f0c <dhcp_parse_reply+0xfc>)
8017f06: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8017f0a: bf00 nop
8017f0c: 08017ffd .word 0x08017ffd
8017f10: 0801800d .word 0x0801800d
8017f14: 0801815f .word 0x0801815f
8017f18: 0801802f .word 0x0801802f
8017f1c: 0801815f .word 0x0801815f
8017f20: 0801815f .word 0x0801815f
8017f24: 0801815f .word 0x0801815f
8017f28: 0801815f .word 0x0801815f
8017f2c: 0801815f .word 0x0801815f
8017f30: 0801815f .word 0x0801815f
8017f34: 0801815f .word 0x0801815f
8017f38: 0801815f .word 0x0801815f
8017f3c: 0801815f .word 0x0801815f
8017f40: 0801815f .word 0x0801815f
8017f44: 0801815f .word 0x0801815f
8017f48: 0801815f .word 0x0801815f
8017f4c: 0801815f .word 0x0801815f
8017f50: 0801815f .word 0x0801815f
8017f54: 0801815f .word 0x0801815f
8017f58: 0801815f .word 0x0801815f
8017f5c: 0801815f .word 0x0801815f
8017f60: 0801815f .word 0x0801815f
8017f64: 0801815f .word 0x0801815f
8017f68: 0801815f .word 0x0801815f
8017f6c: 0801815f .word 0x0801815f
8017f70: 0801815f .word 0x0801815f
8017f74: 0801815f .word 0x0801815f
8017f78: 0801815f .word 0x0801815f
8017f7c: 0801815f .word 0x0801815f
8017f80: 0801815f .word 0x0801815f
8017f84: 0801815f .word 0x0801815f
8017f88: 0801815f .word 0x0801815f
8017f8c: 0801815f .word 0x0801815f
8017f90: 0801815f .word 0x0801815f
8017f94: 0801815f .word 0x0801815f
8017f98: 0801815f .word 0x0801815f
8017f9c: 0801815f .word 0x0801815f
8017fa0: 0801815f .word 0x0801815f
8017fa4: 0801815f .word 0x0801815f
8017fa8: 0801815f .word 0x0801815f
8017fac: 0801815f .word 0x0801815f
8017fb0: 0801815f .word 0x0801815f
8017fb4: 0801815f .word 0x0801815f
8017fb8: 0801815f .word 0x0801815f
8017fbc: 0801815f .word 0x0801815f
8017fc0: 0801815f .word 0x0801815f
8017fc4: 0801815f .word 0x0801815f
8017fc8: 0801815f .word 0x0801815f
8017fcc: 0801815f .word 0x0801815f
8017fd0: 0801815f .word 0x0801815f
8017fd4: 0801815f .word 0x0801815f
8017fd8: 0801805b .word 0x0801805b
8017fdc: 0801807d .word 0x0801807d
8017fe0: 080180b9 .word 0x080180b9
8017fe4: 080180db .word 0x080180db
8017fe8: 0801815f .word 0x0801815f
8017fec: 0801815f .word 0x0801815f
8017ff0: 0801815f .word 0x0801815f
8017ff4: 080180fd .word 0x080180fd
8017ff8: 0801813d .word 0x0801813d
/* case(DHCP_OPTION_END): handled above */
case (DHCP_OPTION_PAD):
/* special option: no len encoded */
decode_len = len = 0;
8017ffc: 2300 movs r3, #0
8017ffe: f887 3027 strb.w r3, [r7, #39] ; 0x27
8018002: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018006: f887 3026 strb.w r3, [r7, #38] ; 0x26
/* will be increased below */
break;
801800a: e0ac b.n 8018166 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SUBNET_MASK):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801800c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018010: 2b04 cmp r3, #4
8018012: d009 beq.n 8018028 <dhcp_parse_reply+0x218>
8018014: 4b43 ldr r3, [pc, #268] ; (8018124 <dhcp_parse_reply+0x314>)
8018016: f240 622e movw r2, #1582 ; 0x62e
801801a: 4943 ldr r1, [pc, #268] ; (8018128 <dhcp_parse_reply+0x318>)
801801c: 4843 ldr r0, [pc, #268] ; (801812c <dhcp_parse_reply+0x31c>)
801801e: f002 fff9 bl 801b014 <iprintf>
8018022: f06f 0305 mvn.w r3, #5
8018026: e1b1 b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
8018028: 2306 movs r3, #6
801802a: 623b str r3, [r7, #32]
break;
801802c: e09b b.n 8018166 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_ROUTER):
decode_len = 4; /* only copy the first given router */
801802e: 2304 movs r3, #4
8018030: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
8018034: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
8018038: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801803c: 429a cmp r2, r3
801803e: d209 bcs.n 8018054 <dhcp_parse_reply+0x244>
8018040: 4b38 ldr r3, [pc, #224] ; (8018124 <dhcp_parse_reply+0x314>)
8018042: f240 6233 movw r2, #1587 ; 0x633
8018046: 493a ldr r1, [pc, #232] ; (8018130 <dhcp_parse_reply+0x320>)
8018048: 4838 ldr r0, [pc, #224] ; (801812c <dhcp_parse_reply+0x31c>)
801804a: f002 ffe3 bl 801b014 <iprintf>
801804e: f06f 0305 mvn.w r3, #5
8018052: e19b b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_ROUTER;
8018054: 2307 movs r3, #7
8018056: 623b str r3, [r7, #32]
break;
8018058: e085 b.n 8018166 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
break;
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
case (DHCP_OPTION_LEASE_TIME):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801805a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801805e: 2b04 cmp r3, #4
8018060: d009 beq.n 8018076 <dhcp_parse_reply+0x266>
8018062: 4b30 ldr r3, [pc, #192] ; (8018124 <dhcp_parse_reply+0x314>)
8018064: f240 6241 movw r2, #1601 ; 0x641
8018068: 492f ldr r1, [pc, #188] ; (8018128 <dhcp_parse_reply+0x318>)
801806a: 4830 ldr r0, [pc, #192] ; (801812c <dhcp_parse_reply+0x31c>)
801806c: f002 ffd2 bl 801b014 <iprintf>
8018070: f06f 0305 mvn.w r3, #5
8018074: e18a b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
8018076: 2303 movs r3, #3
8018078: 623b str r3, [r7, #32]
break;
801807a: e074 b.n 8018166 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
break;
#endif /* LWIP_DHCP_GET_NTP_SRV*/
case (DHCP_OPTION_OVERLOAD):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
801807c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018080: 2b01 cmp r3, #1
8018082: d009 beq.n 8018098 <dhcp_parse_reply+0x288>
8018084: 4b27 ldr r3, [pc, #156] ; (8018124 <dhcp_parse_reply+0x314>)
8018086: f240 624f movw r2, #1615 ; 0x64f
801808a: 492a ldr r1, [pc, #168] ; (8018134 <dhcp_parse_reply+0x324>)
801808c: 4827 ldr r0, [pc, #156] ; (801812c <dhcp_parse_reply+0x31c>)
801808e: f002 ffc1 bl 801b014 <iprintf>
8018092: f06f 0305 mvn.w r3, #5
8018096: e179 b.n 801838c <dhcp_parse_reply+0x57c>
/* decode overload only in options, not in file/sname: invalid packet */
LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;);
8018098: 8efb ldrh r3, [r7, #54] ; 0x36
801809a: 2bf0 cmp r3, #240 ; 0xf0
801809c: d009 beq.n 80180b2 <dhcp_parse_reply+0x2a2>
801809e: 4b21 ldr r3, [pc, #132] ; (8018124 <dhcp_parse_reply+0x314>)
80180a0: f240 6251 movw r2, #1617 ; 0x651
80180a4: 4924 ldr r1, [pc, #144] ; (8018138 <dhcp_parse_reply+0x328>)
80180a6: 4821 ldr r0, [pc, #132] ; (801812c <dhcp_parse_reply+0x31c>)
80180a8: f002 ffb4 bl 801b014 <iprintf>
80180ac: f06f 0305 mvn.w r3, #5
80180b0: e16c b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_OVERLOAD;
80180b2: 2300 movs r3, #0
80180b4: 623b str r3, [r7, #32]
break;
80180b6: e056 b.n 8018166 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_MESSAGE_TYPE):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
80180b8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80180bc: 2b01 cmp r3, #1
80180be: d009 beq.n 80180d4 <dhcp_parse_reply+0x2c4>
80180c0: 4b18 ldr r3, [pc, #96] ; (8018124 <dhcp_parse_reply+0x314>)
80180c2: f240 6255 movw r2, #1621 ; 0x655
80180c6: 491b ldr r1, [pc, #108] ; (8018134 <dhcp_parse_reply+0x324>)
80180c8: 4818 ldr r0, [pc, #96] ; (801812c <dhcp_parse_reply+0x31c>)
80180ca: f002 ffa3 bl 801b014 <iprintf>
80180ce: f06f 0305 mvn.w r3, #5
80180d2: e15b b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
80180d4: 2301 movs r3, #1
80180d6: 623b str r3, [r7, #32]
break;
80180d8: e045 b.n 8018166 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SERVER_ID):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
80180da: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80180de: 2b04 cmp r3, #4
80180e0: d009 beq.n 80180f6 <dhcp_parse_reply+0x2e6>
80180e2: 4b10 ldr r3, [pc, #64] ; (8018124 <dhcp_parse_reply+0x314>)
80180e4: f240 6259 movw r2, #1625 ; 0x659
80180e8: 490f ldr r1, [pc, #60] ; (8018128 <dhcp_parse_reply+0x318>)
80180ea: 4810 ldr r0, [pc, #64] ; (801812c <dhcp_parse_reply+0x31c>)
80180ec: f002 ff92 bl 801b014 <iprintf>
80180f0: f06f 0305 mvn.w r3, #5
80180f4: e14a b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SERVER_ID;
80180f6: 2302 movs r3, #2
80180f8: 623b str r3, [r7, #32]
break;
80180fa: e034 b.n 8018166 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_T1):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
80180fc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018100: 2b04 cmp r3, #4
8018102: d009 beq.n 8018118 <dhcp_parse_reply+0x308>
8018104: 4b07 ldr r3, [pc, #28] ; (8018124 <dhcp_parse_reply+0x314>)
8018106: f240 625d movw r2, #1629 ; 0x65d
801810a: 4907 ldr r1, [pc, #28] ; (8018128 <dhcp_parse_reply+0x318>)
801810c: 4807 ldr r0, [pc, #28] ; (801812c <dhcp_parse_reply+0x31c>)
801810e: f002 ff81 bl 801b014 <iprintf>
8018112: f06f 0305 mvn.w r3, #5
8018116: e139 b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T1;
8018118: 2304 movs r3, #4
801811a: 623b str r3, [r7, #32]
break;
801811c: e023 b.n 8018166 <dhcp_parse_reply+0x356>
801811e: bf00 nop
8018120: 2000f5dc .word 0x2000f5dc
8018124: 0801e398 .word 0x0801e398
8018128: 0801e620 .word 0x0801e620
801812c: 0801e3f8 .word 0x0801e3f8
8018130: 0801e62c .word 0x0801e62c
8018134: 0801e640 .word 0x0801e640
8018138: 0801e64c .word 0x0801e64c
case (DHCP_OPTION_T2):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801813c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018140: 2b04 cmp r3, #4
8018142: d009 beq.n 8018158 <dhcp_parse_reply+0x348>
8018144: 4b93 ldr r3, [pc, #588] ; (8018394 <dhcp_parse_reply+0x584>)
8018146: f240 6261 movw r2, #1633 ; 0x661
801814a: 4993 ldr r1, [pc, #588] ; (8018398 <dhcp_parse_reply+0x588>)
801814c: 4893 ldr r0, [pc, #588] ; (801839c <dhcp_parse_reply+0x58c>)
801814e: f002 ff61 bl 801b014 <iprintf>
8018152: f06f 0305 mvn.w r3, #5
8018156: e119 b.n 801838c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T2;
8018158: 2305 movs r3, #5
801815a: 623b str r3, [r7, #32]
break;
801815c: e003 b.n 8018166 <dhcp_parse_reply+0x356>
default:
decode_len = 0;
801815e: 2300 movs r3, #0
8018160: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op));
LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in,
dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0,
op, len, q, val_offset);
break;
8018164: bf00 nop
}
if (op == DHCP_OPTION_PAD) {
8018166: 7dfb ldrb r3, [r7, #23]
8018168: 2b00 cmp r3, #0
801816a: d103 bne.n 8018174 <dhcp_parse_reply+0x364>
offset++;
801816c: 8f7b ldrh r3, [r7, #58] ; 0x3a
801816e: 3301 adds r3, #1
8018170: 877b strh r3, [r7, #58] ; 0x3a
8018172: e0a1 b.n 80182b8 <dhcp_parse_reply+0x4a8>
} else {
if (offset + len + 2 > 0xFFFF) {
8018174: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018176: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801817a: 4413 add r3, r2
801817c: 3302 adds r3, #2
801817e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8018182: db02 blt.n 801818a <dhcp_parse_reply+0x37a>
/* overflow */
return ERR_BUF;
8018184: f06f 0301 mvn.w r3, #1
8018188: e100 b.n 801838c <dhcp_parse_reply+0x57c>
}
offset = (u16_t)(offset + len + 2);
801818a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801818e: b29a uxth r2, r3
8018190: 8f7b ldrh r3, [r7, #58] ; 0x3a
8018192: 4413 add r3, r2
8018194: b29b uxth r3, r3
8018196: 3302 adds r3, #2
8018198: 877b strh r3, [r7, #58] ; 0x3a
if (decode_len > 0) {
801819a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801819e: 2b00 cmp r3, #0
80181a0: f000 808a beq.w 80182b8 <dhcp_parse_reply+0x4a8>
u32_t value = 0;
80181a4: 2300 movs r3, #0
80181a6: 60bb str r3, [r7, #8]
u16_t copy_len;
decode_next:
LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
80181a8: 6a3b ldr r3, [r7, #32]
80181aa: 2b00 cmp r3, #0
80181ac: db02 blt.n 80181b4 <dhcp_parse_reply+0x3a4>
80181ae: 6a3b ldr r3, [r7, #32]
80181b0: 2b07 cmp r3, #7
80181b2: dd06 ble.n 80181c2 <dhcp_parse_reply+0x3b2>
80181b4: 4b77 ldr r3, [pc, #476] ; (8018394 <dhcp_parse_reply+0x584>)
80181b6: f44f 62cf mov.w r2, #1656 ; 0x678
80181ba: 4979 ldr r1, [pc, #484] ; (80183a0 <dhcp_parse_reply+0x590>)
80181bc: 4877 ldr r0, [pc, #476] ; (801839c <dhcp_parse_reply+0x58c>)
80181be: f002 ff29 bl 801b014 <iprintf>
if (!dhcp_option_given(dhcp, decode_idx)) {
80181c2: 4a78 ldr r2, [pc, #480] ; (80183a4 <dhcp_parse_reply+0x594>)
80181c4: 6a3b ldr r3, [r7, #32]
80181c6: 4413 add r3, r2
80181c8: 781b ldrb r3, [r3, #0]
80181ca: 2b00 cmp r3, #0
80181cc: d174 bne.n 80182b8 <dhcp_parse_reply+0x4a8>
copy_len = LWIP_MIN(decode_len, 4);
80181ce: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181d2: 2b04 cmp r3, #4
80181d4: bf28 it cs
80181d6: 2304 movcs r3, #4
80181d8: b2db uxtb r3, r3
80181da: 82bb strh r3, [r7, #20]
if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) {
80181dc: 8bfb ldrh r3, [r7, #30]
80181de: 8aba ldrh r2, [r7, #20]
80181e0: f107 0108 add.w r1, r7, #8
80181e4: 6b38 ldr r0, [r7, #48] ; 0x30
80181e6: f7f8 fc05 bl 80109f4 <pbuf_copy_partial>
80181ea: 4603 mov r3, r0
80181ec: 461a mov r2, r3
80181ee: 8abb ldrh r3, [r7, #20]
80181f0: 4293 cmp r3, r2
80181f2: d002 beq.n 80181fa <dhcp_parse_reply+0x3ea>
return ERR_BUF;
80181f4: f06f 0301 mvn.w r3, #1
80181f8: e0c8 b.n 801838c <dhcp_parse_reply+0x57c>
}
if (decode_len > 4) {
80181fa: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181fe: 2b04 cmp r3, #4
8018200: d933 bls.n 801826a <dhcp_parse_reply+0x45a>
/* decode more than one u32_t */
u16_t next_val_offset;
LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
8018202: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018206: f003 0303 and.w r3, r3, #3
801820a: b2db uxtb r3, r3
801820c: 2b00 cmp r3, #0
801820e: d009 beq.n 8018224 <dhcp_parse_reply+0x414>
8018210: 4b60 ldr r3, [pc, #384] ; (8018394 <dhcp_parse_reply+0x584>)
8018212: f240 6281 movw r2, #1665 ; 0x681
8018216: 4964 ldr r1, [pc, #400] ; (80183a8 <dhcp_parse_reply+0x598>)
8018218: 4860 ldr r0, [pc, #384] ; (801839c <dhcp_parse_reply+0x58c>)
801821a: f002 fefb bl 801b014 <iprintf>
801821e: f06f 0305 mvn.w r3, #5
8018222: e0b3 b.n 801838c <dhcp_parse_reply+0x57c>
dhcp_got_option(dhcp, decode_idx);
8018224: 4a5f ldr r2, [pc, #380] ; (80183a4 <dhcp_parse_reply+0x594>)
8018226: 6a3b ldr r3, [r7, #32]
8018228: 4413 add r3, r2
801822a: 2201 movs r2, #1
801822c: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value));
801822e: 68bb ldr r3, [r7, #8]
8018230: 4618 mov r0, r3
8018232: f7f6 fe3a bl 800eeaa <lwip_htonl>
8018236: 4601 mov r1, r0
8018238: 4a5c ldr r2, [pc, #368] ; (80183ac <dhcp_parse_reply+0x59c>)
801823a: 6a3b ldr r3, [r7, #32]
801823c: f842 1023 str.w r1, [r2, r3, lsl #2]
decode_len = (u8_t)(decode_len - 4);
8018240: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018244: 3b04 subs r3, #4
8018246: f887 3026 strb.w r3, [r7, #38] ; 0x26
next_val_offset = (u16_t)(val_offset + 4);
801824a: 8bfb ldrh r3, [r7, #30]
801824c: 3304 adds r3, #4
801824e: 827b strh r3, [r7, #18]
if (next_val_offset < val_offset) {
8018250: 8a7a ldrh r2, [r7, #18]
8018252: 8bfb ldrh r3, [r7, #30]
8018254: 429a cmp r2, r3
8018256: d202 bcs.n 801825e <dhcp_parse_reply+0x44e>
/* overflow */
return ERR_BUF;
8018258: f06f 0301 mvn.w r3, #1
801825c: e096 b.n 801838c <dhcp_parse_reply+0x57c>
}
val_offset = next_val_offset;
801825e: 8a7b ldrh r3, [r7, #18]
8018260: 83fb strh r3, [r7, #30]
decode_idx++;
8018262: 6a3b ldr r3, [r7, #32]
8018264: 3301 adds r3, #1
8018266: 623b str r3, [r7, #32]
goto decode_next;
8018268: e79e b.n 80181a8 <dhcp_parse_reply+0x398>
} else if (decode_len == 4) {
801826a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801826e: 2b04 cmp r3, #4
8018270: d106 bne.n 8018280 <dhcp_parse_reply+0x470>
value = lwip_ntohl(value);
8018272: 68bb ldr r3, [r7, #8]
8018274: 4618 mov r0, r3
8018276: f7f6 fe18 bl 800eeaa <lwip_htonl>
801827a: 4603 mov r3, r0
801827c: 60bb str r3, [r7, #8]
801827e: e011 b.n 80182a4 <dhcp_parse_reply+0x494>
} else {
LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
8018280: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018284: 2b01 cmp r3, #1
8018286: d009 beq.n 801829c <dhcp_parse_reply+0x48c>
8018288: 4b42 ldr r3, [pc, #264] ; (8018394 <dhcp_parse_reply+0x584>)
801828a: f44f 62d2 mov.w r2, #1680 ; 0x690
801828e: 4948 ldr r1, [pc, #288] ; (80183b0 <dhcp_parse_reply+0x5a0>)
8018290: 4842 ldr r0, [pc, #264] ; (801839c <dhcp_parse_reply+0x58c>)
8018292: f002 febf bl 801b014 <iprintf>
8018296: f06f 0305 mvn.w r3, #5
801829a: e077 b.n 801838c <dhcp_parse_reply+0x57c>
value = ((u8_t *)&value)[0];
801829c: f107 0308 add.w r3, r7, #8
80182a0: 781b ldrb r3, [r3, #0]
80182a2: 60bb str r3, [r7, #8]
}
dhcp_got_option(dhcp, decode_idx);
80182a4: 4a3f ldr r2, [pc, #252] ; (80183a4 <dhcp_parse_reply+0x594>)
80182a6: 6a3b ldr r3, [r7, #32]
80182a8: 4413 add r3, r2
80182aa: 2201 movs r2, #1
80182ac: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, value);
80182ae: 68ba ldr r2, [r7, #8]
80182b0: 493e ldr r1, [pc, #248] ; (80183ac <dhcp_parse_reply+0x59c>)
80182b2: 6a3b ldr r3, [r7, #32]
80182b4: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
}
if (offset >= q->len) {
80182b8: 6b3b ldr r3, [r7, #48] ; 0x30
80182ba: 895b ldrh r3, [r3, #10]
80182bc: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182be: 429a cmp r2, r3
80182c0: d324 bcc.n 801830c <dhcp_parse_reply+0x4fc>
offset = (u16_t)(offset - q->len);
80182c2: 6b3b ldr r3, [r7, #48] ; 0x30
80182c4: 895b ldrh r3, [r3, #10]
80182c6: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182c8: 1ad3 subs r3, r2, r3
80182ca: 877b strh r3, [r7, #58] ; 0x3a
offset_max = (u16_t)(offset_max - q->len);
80182cc: 6b3b ldr r3, [r7, #48] ; 0x30
80182ce: 895b ldrh r3, [r3, #10]
80182d0: 8f3a ldrh r2, [r7, #56] ; 0x38
80182d2: 1ad3 subs r3, r2, r3
80182d4: 873b strh r3, [r7, #56] ; 0x38
if (offset < offset_max) {
80182d6: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182d8: 8f3b ldrh r3, [r7, #56] ; 0x38
80182da: 429a cmp r2, r3
80182dc: d213 bcs.n 8018306 <dhcp_parse_reply+0x4f6>
q = q->next;
80182de: 6b3b ldr r3, [r7, #48] ; 0x30
80182e0: 681b ldr r3, [r3, #0]
80182e2: 633b str r3, [r7, #48] ; 0x30
LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;);
80182e4: 6b3b ldr r3, [r7, #48] ; 0x30
80182e6: 2b00 cmp r3, #0
80182e8: d109 bne.n 80182fe <dhcp_parse_reply+0x4ee>
80182ea: 4b2a ldr r3, [pc, #168] ; (8018394 <dhcp_parse_reply+0x584>)
80182ec: f240 629d movw r2, #1693 ; 0x69d
80182f0: 4930 ldr r1, [pc, #192] ; (80183b4 <dhcp_parse_reply+0x5a4>)
80182f2: 482a ldr r0, [pc, #168] ; (801839c <dhcp_parse_reply+0x58c>)
80182f4: f002 fe8e bl 801b014 <iprintf>
80182f8: f06f 0305 mvn.w r3, #5
80182fc: e046 b.n 801838c <dhcp_parse_reply+0x57c>
options = (u8_t *)q->payload;
80182fe: 6b3b ldr r3, [r7, #48] ; 0x30
8018300: 685b ldr r3, [r3, #4]
8018302: 63fb str r3, [r7, #60] ; 0x3c
8018304: e002 b.n 801830c <dhcp_parse_reply+0x4fc>
} else {
/* We've run out of bytes, probably no end marker. Don't proceed. */
return ERR_BUF;
8018306: f06f 0301 mvn.w r3, #1
801830a: e03f b.n 801838c <dhcp_parse_reply+0x57c>
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
801830c: 6b3b ldr r3, [r7, #48] ; 0x30
801830e: 2b00 cmp r3, #0
8018310: d00a beq.n 8018328 <dhcp_parse_reply+0x518>
8018312: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018314: 8f3b ldrh r3, [r7, #56] ; 0x38
8018316: 429a cmp r2, r3
8018318: d206 bcs.n 8018328 <dhcp_parse_reply+0x518>
801831a: 8f7b ldrh r3, [r7, #58] ; 0x3a
801831c: 6bfa ldr r2, [r7, #60] ; 0x3c
801831e: 4413 add r3, r2
8018320: 781b ldrb r3, [r3, #0]
8018322: 2bff cmp r3, #255 ; 0xff
8018324: f47f adb7 bne.w 8017e96 <dhcp_parse_reply+0x86>
}
}
}
/* is this an overloaded message? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
8018328: 4b1e ldr r3, [pc, #120] ; (80183a4 <dhcp_parse_reply+0x594>)
801832a: 781b ldrb r3, [r3, #0]
801832c: 2b00 cmp r3, #0
801832e: d018 beq.n 8018362 <dhcp_parse_reply+0x552>
u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
8018330: 4b1e ldr r3, [pc, #120] ; (80183ac <dhcp_parse_reply+0x59c>)
8018332: 681b ldr r3, [r3, #0]
8018334: 60fb str r3, [r7, #12]
dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
8018336: 4b1b ldr r3, [pc, #108] ; (80183a4 <dhcp_parse_reply+0x594>)
8018338: 2200 movs r2, #0
801833a: 701a strb r2, [r3, #0]
if (overload == DHCP_OVERLOAD_FILE) {
801833c: 68fb ldr r3, [r7, #12]
801833e: 2b01 cmp r3, #1
8018340: d102 bne.n 8018348 <dhcp_parse_reply+0x538>
parse_file_as_options = 1;
8018342: 2301 movs r3, #1
8018344: 62fb str r3, [r7, #44] ; 0x2c
8018346: e00c b.n 8018362 <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME) {
8018348: 68fb ldr r3, [r7, #12]
801834a: 2b02 cmp r3, #2
801834c: d102 bne.n 8018354 <dhcp_parse_reply+0x544>
parse_sname_as_options = 1;
801834e: 2301 movs r3, #1
8018350: 62bb str r3, [r7, #40] ; 0x28
8018352: e006 b.n 8018362 <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
8018354: 68fb ldr r3, [r7, #12]
8018356: 2b03 cmp r3, #3
8018358: d103 bne.n 8018362 <dhcp_parse_reply+0x552>
parse_sname_as_options = 1;
801835a: 2301 movs r3, #1
801835c: 62bb str r3, [r7, #40] ; 0x28
parse_file_as_options = 1;
801835e: 2301 movs r3, #1
8018360: 62fb str r3, [r7, #44] ; 0x2c
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
}
}
if (parse_file_as_options) {
8018362: 6afb ldr r3, [r7, #44] ; 0x2c
8018364: 2b00 cmp r3, #0
8018366: d006 beq.n 8018376 <dhcp_parse_reply+0x566>
/* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
parse_file_as_options = 0;
8018368: 2300 movs r3, #0
801836a: 62fb str r3, [r7, #44] ; 0x2c
options_idx = DHCP_FILE_OFS;
801836c: 236c movs r3, #108 ; 0x6c
801836e: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
8018370: 23ec movs r3, #236 ; 0xec
8018372: 86bb strh r3, [r7, #52] ; 0x34
#if LWIP_DHCP_BOOTP_FILE
file_overloaded = 1;
#endif
goto again;
8018374: e569 b.n 8017e4a <dhcp_parse_reply+0x3a>
} else if (parse_sname_as_options) {
8018376: 6abb ldr r3, [r7, #40] ; 0x28
8018378: 2b00 cmp r3, #0
801837a: d006 beq.n 801838a <dhcp_parse_reply+0x57a>
parse_sname_as_options = 0;
801837c: 2300 movs r3, #0
801837e: 62bb str r3, [r7, #40] ; 0x28
options_idx = DHCP_SNAME_OFS;
8018380: 232c movs r3, #44 ; 0x2c
8018382: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
8018384: 236c movs r3, #108 ; 0x6c
8018386: 86bb strh r3, [r7, #52] ; 0x34
goto again;
8018388: e55f b.n 8017e4a <dhcp_parse_reply+0x3a>
}
/* make sure the string is really NULL-terminated */
dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
}
#endif /* LWIP_DHCP_BOOTP_FILE */
return ERR_OK;
801838a: 2300 movs r3, #0
}
801838c: 4618 mov r0, r3
801838e: 3740 adds r7, #64 ; 0x40
8018390: 46bd mov sp, r7
8018392: bd80 pop {r7, pc}
8018394: 0801e398 .word 0x0801e398
8018398: 0801e620 .word 0x0801e620
801839c: 0801e3f8 .word 0x0801e3f8
80183a0: 0801e664 .word 0x0801e664
80183a4: 2000f5dc .word 0x2000f5dc
80183a8: 0801e678 .word 0x0801e678
80183ac: 2000f5e4 .word 0x2000f5e4
80183b0: 0801e690 .word 0x0801e690
80183b4: 0801e6a4 .word 0x0801e6a4
080183b8 <dhcp_recv>:
/**
* If an incoming DHCP message is in response to us, then trigger the state machine
*/
static void
dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
{
80183b8: b580 push {r7, lr}
80183ba: b08a sub sp, #40 ; 0x28
80183bc: af00 add r7, sp, #0
80183be: 60f8 str r0, [r7, #12]
80183c0: 60b9 str r1, [r7, #8]
80183c2: 607a str r2, [r7, #4]
80183c4: 603b str r3, [r7, #0]
struct netif *netif = ip_current_input_netif();
80183c6: 4b5f ldr r3, [pc, #380] ; (8018544 <dhcp_recv+0x18c>)
80183c8: 685b ldr r3, [r3, #4]
80183ca: 623b str r3, [r7, #32]
struct dhcp *dhcp = netif_dhcp_data(netif);
80183cc: 6a3b ldr r3, [r7, #32]
80183ce: 6a5b ldr r3, [r3, #36] ; 0x24
80183d0: 61fb str r3, [r7, #28]
struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
80183d2: 687b ldr r3, [r7, #4]
80183d4: 685b ldr r3, [r3, #4]
80183d6: 61bb str r3, [r7, #24]
struct dhcp_msg *msg_in;
LWIP_UNUSED_ARG(arg);
/* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */
if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) {
80183d8: 69fb ldr r3, [r7, #28]
80183da: 2b00 cmp r3, #0
80183dc: f000 809d beq.w 801851a <dhcp_recv+0x162>
80183e0: 69fb ldr r3, [r7, #28]
80183e2: 791b ldrb r3, [r3, #4]
80183e4: 2b00 cmp r3, #0
80183e6: f000 8098 beq.w 801851a <dhcp_recv+0x162>
/* prevent warnings about unused arguments */
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(addr);
LWIP_UNUSED_ARG(port);
if (p->len < DHCP_MIN_REPLY_LEN) {
80183ea: 687b ldr r3, [r7, #4]
80183ec: 895b ldrh r3, [r3, #10]
80183ee: 2b2b cmp r3, #43 ; 0x2b
80183f0: f240 8095 bls.w 801851e <dhcp_recv+0x166>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
goto free_pbuf_and_return;
}
if (reply_msg->op != DHCP_BOOTREPLY) {
80183f4: 69bb ldr r3, [r7, #24]
80183f6: 781b ldrb r3, [r3, #0]
80183f8: 2b02 cmp r3, #2
80183fa: f040 8092 bne.w 8018522 <dhcp_recv+0x16a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
goto free_pbuf_and_return;
}
/* iterate through hardware address and match against DHCP message */
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
80183fe: 2300 movs r3, #0
8018400: f887 3027 strb.w r3, [r7, #39] ; 0x27
8018404: e012 b.n 801842c <dhcp_recv+0x74>
if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
8018406: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801840a: 6a3a ldr r2, [r7, #32]
801840c: 4413 add r3, r2
801840e: f893 202a ldrb.w r2, [r3, #42] ; 0x2a
8018412: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018416: 69b9 ldr r1, [r7, #24]
8018418: 440b add r3, r1
801841a: 7f1b ldrb r3, [r3, #28]
801841c: 429a cmp r2, r3
801841e: f040 8082 bne.w 8018526 <dhcp_recv+0x16e>
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018422: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018426: 3301 adds r3, #1
8018428: f887 3027 strb.w r3, [r7, #39] ; 0x27
801842c: 6a3b ldr r3, [r7, #32]
801842e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8018432: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
8018436: 429a cmp r2, r3
8018438: d203 bcs.n 8018442 <dhcp_recv+0x8a>
801843a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801843e: 2b05 cmp r3, #5
8018440: d9e1 bls.n 8018406 <dhcp_recv+0x4e>
(u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
goto free_pbuf_and_return;
}
}
/* match transaction ID against what we expected */
if (lwip_ntohl(reply_msg->xid) != dhcp->xid) {
8018442: 69bb ldr r3, [r7, #24]
8018444: 685b ldr r3, [r3, #4]
8018446: 4618 mov r0, r3
8018448: f7f6 fd2f bl 800eeaa <lwip_htonl>
801844c: 4602 mov r2, r0
801844e: 69fb ldr r3, [r7, #28]
8018450: 681b ldr r3, [r3, #0]
8018452: 429a cmp r2, r3
8018454: d169 bne.n 801852a <dhcp_recv+0x172>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid));
goto free_pbuf_and_return;
}
/* option fields could be unfold? */
if (dhcp_parse_reply(p, dhcp) != ERR_OK) {
8018456: 69f9 ldr r1, [r7, #28]
8018458: 6878 ldr r0, [r7, #4]
801845a: f7ff fcd9 bl 8017e10 <dhcp_parse_reply>
801845e: 4603 mov r3, r0
8018460: 2b00 cmp r3, #0
8018462: d164 bne.n 801852e <dhcp_recv+0x176>
goto free_pbuf_and_return;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
/* obtain pointer to DHCP message type */
if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
8018464: 4b38 ldr r3, [pc, #224] ; (8018548 <dhcp_recv+0x190>)
8018466: 785b ldrb r3, [r3, #1]
8018468: 2b00 cmp r3, #0
801846a: d062 beq.n 8018532 <dhcp_recv+0x17a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
goto free_pbuf_and_return;
}
msg_in = (struct dhcp_msg *)p->payload;
801846c: 687b ldr r3, [r7, #4]
801846e: 685b ldr r3, [r3, #4]
8018470: 617b str r3, [r7, #20]
/* read DHCP message type */
msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
8018472: 4b36 ldr r3, [pc, #216] ; (801854c <dhcp_recv+0x194>)
8018474: 685b ldr r3, [r3, #4]
8018476: 74fb strb r3, [r7, #19]
/* message type is DHCP ACK? */
if (msg_type == DHCP_ACK) {
8018478: 7cfb ldrb r3, [r7, #19]
801847a: 2b05 cmp r3, #5
801847c: d12a bne.n 80184d4 <dhcp_recv+0x11c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
/* in requesting state? */
if (dhcp->state == DHCP_STATE_REQUESTING) {
801847e: 69fb ldr r3, [r7, #28]
8018480: 795b ldrb r3, [r3, #5]
8018482: 2b01 cmp r3, #1
8018484: d112 bne.n 80184ac <dhcp_recv+0xf4>
dhcp_handle_ack(netif, msg_in);
8018486: 6979 ldr r1, [r7, #20]
8018488: 6a38 ldr r0, [r7, #32]
801848a: f7fe fe05 bl 8017098 <dhcp_handle_ack>
#if DHCP_DOES_ARP_CHECK
if ((netif->flags & NETIF_FLAG_ETHARP) != 0) {
801848e: 6a3b ldr r3, [r7, #32]
8018490: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8018494: f003 0308 and.w r3, r3, #8
8018498: 2b00 cmp r3, #0
801849a: d003 beq.n 80184a4 <dhcp_recv+0xec>
/* check if the acknowledged lease address is already in use */
dhcp_check(netif);
801849c: 6a38 ldr r0, [r7, #32]
801849e: f7fe fb73 bl 8016b88 <dhcp_check>
80184a2: e047 b.n 8018534 <dhcp_recv+0x17c>
} else {
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
80184a4: 6a38 ldr r0, [r7, #32]
80184a6: f7ff f867 bl 8017578 <dhcp_bind>
80184aa: e043 b.n 8018534 <dhcp_recv+0x17c>
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
#endif
}
/* already bound to the given lease address? */
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
80184ac: 69fb ldr r3, [r7, #28]
80184ae: 795b ldrb r3, [r3, #5]
80184b0: 2b03 cmp r3, #3
80184b2: d007 beq.n 80184c4 <dhcp_recv+0x10c>
80184b4: 69fb ldr r3, [r7, #28]
80184b6: 795b ldrb r3, [r3, #5]
80184b8: 2b04 cmp r3, #4
80184ba: d003 beq.n 80184c4 <dhcp_recv+0x10c>
(dhcp->state == DHCP_STATE_RENEWING)) {
80184bc: 69fb ldr r3, [r7, #28]
80184be: 795b ldrb r3, [r3, #5]
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
80184c0: 2b05 cmp r3, #5
80184c2: d137 bne.n 8018534 <dhcp_recv+0x17c>
dhcp_handle_ack(netif, msg_in);
80184c4: 6979 ldr r1, [r7, #20]
80184c6: 6a38 ldr r0, [r7, #32]
80184c8: f7fe fde6 bl 8017098 <dhcp_handle_ack>
dhcp_bind(netif);
80184cc: 6a38 ldr r0, [r7, #32]
80184ce: f7ff f853 bl 8017578 <dhcp_bind>
80184d2: e02f b.n 8018534 <dhcp_recv+0x17c>
}
}
/* received a DHCP_NAK in appropriate state? */
else if ((msg_type == DHCP_NAK) &&
80184d4: 7cfb ldrb r3, [r7, #19]
80184d6: 2b06 cmp r3, #6
80184d8: d113 bne.n 8018502 <dhcp_recv+0x14a>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184da: 69fb ldr r3, [r7, #28]
80184dc: 795b ldrb r3, [r3, #5]
else if ((msg_type == DHCP_NAK) &&
80184de: 2b03 cmp r3, #3
80184e0: d00b beq.n 80184fa <dhcp_recv+0x142>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184e2: 69fb ldr r3, [r7, #28]
80184e4: 795b ldrb r3, [r3, #5]
80184e6: 2b01 cmp r3, #1
80184e8: d007 beq.n 80184fa <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
80184ea: 69fb ldr r3, [r7, #28]
80184ec: 795b ldrb r3, [r3, #5]
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184ee: 2b04 cmp r3, #4
80184f0: d003 beq.n 80184fa <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
80184f2: 69fb ldr r3, [r7, #28]
80184f4: 795b ldrb r3, [r3, #5]
80184f6: 2b05 cmp r3, #5
80184f8: d103 bne.n 8018502 <dhcp_recv+0x14a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
dhcp_handle_nak(netif);
80184fa: 6a38 ldr r0, [r7, #32]
80184fc: f7fe fb2a bl 8016b54 <dhcp_handle_nak>
8018500: e018 b.n 8018534 <dhcp_recv+0x17c>
}
/* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
8018502: 7cfb ldrb r3, [r7, #19]
8018504: 2b02 cmp r3, #2
8018506: d108 bne.n 801851a <dhcp_recv+0x162>
8018508: 69fb ldr r3, [r7, #28]
801850a: 795b ldrb r3, [r3, #5]
801850c: 2b06 cmp r3, #6
801850e: d104 bne.n 801851a <dhcp_recv+0x162>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
/* remember offered lease */
dhcp_handle_offer(netif, msg_in);
8018510: 6979 ldr r1, [r7, #20]
8018512: 6a38 ldr r0, [r7, #32]
8018514: f7fe fb6c bl 8016bf0 <dhcp_handle_offer>
8018518: e00c b.n 8018534 <dhcp_recv+0x17c>
}
free_pbuf_and_return:
801851a: bf00 nop
801851c: e00a b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801851e: bf00 nop
8018520: e008 b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018522: bf00 nop
8018524: e006 b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018526: bf00 nop
8018528: e004 b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801852a: bf00 nop
801852c: e002 b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801852e: bf00 nop
8018530: e000 b.n 8018534 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018532: bf00 nop
pbuf_free(p);
8018534: 6878 ldr r0, [r7, #4]
8018536: f7f8 f857 bl 80105e8 <pbuf_free>
}
801853a: bf00 nop
801853c: 3728 adds r7, #40 ; 0x28
801853e: 46bd mov sp, r7
8018540: bd80 pop {r7, pc}
8018542: bf00 nop
8018544: 2000be8c .word 0x2000be8c
8018548: 2000f5dc .word 0x2000f5dc
801854c: 2000f5e4 .word 0x2000f5e4
08018550 <dhcp_create_msg>:
* @param dhcp dhcp control struct
* @param message_type message type of the request
*/
static struct pbuf *
dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len)
{
8018550: b580 push {r7, lr}
8018552: b088 sub sp, #32
8018554: af00 add r7, sp, #0
8018556: 60f8 str r0, [r7, #12]
8018558: 60b9 str r1, [r7, #8]
801855a: 603b str r3, [r7, #0]
801855c: 4613 mov r3, r2
801855e: 71fb strb r3, [r7, #7]
if (!xid_initialised) {
xid = DHCP_GLOBAL_XID;
xid_initialised = !xid_initialised;
}
#endif
LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;);
8018560: 68fb ldr r3, [r7, #12]
8018562: 2b00 cmp r3, #0
8018564: d108 bne.n 8018578 <dhcp_create_msg+0x28>
8018566: 4b5f ldr r3, [pc, #380] ; (80186e4 <dhcp_create_msg+0x194>)
8018568: f240 7269 movw r2, #1897 ; 0x769
801856c: 495e ldr r1, [pc, #376] ; (80186e8 <dhcp_create_msg+0x198>)
801856e: 485f ldr r0, [pc, #380] ; (80186ec <dhcp_create_msg+0x19c>)
8018570: f002 fd50 bl 801b014 <iprintf>
8018574: 2300 movs r3, #0
8018576: e0b1 b.n 80186dc <dhcp_create_msg+0x18c>
LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;);
8018578: 68bb ldr r3, [r7, #8]
801857a: 2b00 cmp r3, #0
801857c: d108 bne.n 8018590 <dhcp_create_msg+0x40>
801857e: 4b59 ldr r3, [pc, #356] ; (80186e4 <dhcp_create_msg+0x194>)
8018580: f240 726a movw r2, #1898 ; 0x76a
8018584: 495a ldr r1, [pc, #360] ; (80186f0 <dhcp_create_msg+0x1a0>)
8018586: 4859 ldr r0, [pc, #356] ; (80186ec <dhcp_create_msg+0x19c>)
8018588: f002 fd44 bl 801b014 <iprintf>
801858c: 2300 movs r3, #0
801858e: e0a5 b.n 80186dc <dhcp_create_msg+0x18c>
p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
8018590: f44f 7220 mov.w r2, #640 ; 0x280
8018594: f44f 719a mov.w r1, #308 ; 0x134
8018598: 2036 movs r0, #54 ; 0x36
801859a: f7f7 fd45 bl 8010028 <pbuf_alloc>
801859e: 61b8 str r0, [r7, #24]
if (p_out == NULL) {
80185a0: 69bb ldr r3, [r7, #24]
80185a2: 2b00 cmp r3, #0
80185a4: d101 bne.n 80185aa <dhcp_create_msg+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_create_msg(): could not allocate pbuf\n"));
return NULL;
80185a6: 2300 movs r3, #0
80185a8: e098 b.n 80186dc <dhcp_create_msg+0x18c>
}
LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
80185aa: 69bb ldr r3, [r7, #24]
80185ac: 895b ldrh r3, [r3, #10]
80185ae: f5b3 7f9a cmp.w r3, #308 ; 0x134
80185b2: d206 bcs.n 80185c2 <dhcp_create_msg+0x72>
80185b4: 4b4b ldr r3, [pc, #300] ; (80186e4 <dhcp_create_msg+0x194>)
80185b6: f240 7272 movw r2, #1906 ; 0x772
80185ba: 494e ldr r1, [pc, #312] ; (80186f4 <dhcp_create_msg+0x1a4>)
80185bc: 484b ldr r0, [pc, #300] ; (80186ec <dhcp_create_msg+0x19c>)
80185be: f002 fd29 bl 801b014 <iprintf>
(p_out->len >= sizeof(struct dhcp_msg)));
/* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) {
80185c2: 79fb ldrb r3, [r7, #7]
80185c4: 2b03 cmp r3, #3
80185c6: d103 bne.n 80185d0 <dhcp_create_msg+0x80>
80185c8: 68bb ldr r3, [r7, #8]
80185ca: 795b ldrb r3, [r3, #5]
80185cc: 2b03 cmp r3, #3
80185ce: d10d bne.n 80185ec <dhcp_create_msg+0x9c>
/* reuse transaction identifier in retransmissions */
if (dhcp->tries == 0) {
80185d0: 68bb ldr r3, [r7, #8]
80185d2: 799b ldrb r3, [r3, #6]
80185d4: 2b00 cmp r3, #0
80185d6: d105 bne.n 80185e4 <dhcp_create_msg+0x94>
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
xid = LWIP_RAND();
80185d8: f002 fd34 bl 801b044 <rand>
80185dc: 4603 mov r3, r0
80185de: 461a mov r2, r3
80185e0: 4b45 ldr r3, [pc, #276] ; (80186f8 <dhcp_create_msg+0x1a8>)
80185e2: 601a str r2, [r3, #0]
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
xid++;
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
}
dhcp->xid = xid;
80185e4: 4b44 ldr r3, [pc, #272] ; (80186f8 <dhcp_create_msg+0x1a8>)
80185e6: 681a ldr r2, [r3, #0]
80185e8: 68bb ldr r3, [r7, #8]
80185ea: 601a str r2, [r3, #0]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
("transaction id xid(%"X32_F")\n", xid));
msg_out = (struct dhcp_msg *)p_out->payload;
80185ec: 69bb ldr r3, [r7, #24]
80185ee: 685b ldr r3, [r3, #4]
80185f0: 617b str r3, [r7, #20]
memset(msg_out, 0, sizeof(struct dhcp_msg));
80185f2: f44f 729a mov.w r2, #308 ; 0x134
80185f6: 2100 movs r1, #0
80185f8: 6978 ldr r0, [r7, #20]
80185fa: f002 fd03 bl 801b004 <memset>
msg_out->op = DHCP_BOOTREQUEST;
80185fe: 697b ldr r3, [r7, #20]
8018600: 2201 movs r2, #1
8018602: 701a strb r2, [r3, #0]
/* @todo: make link layer independent */
msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET;
8018604: 697b ldr r3, [r7, #20]
8018606: 2201 movs r2, #1
8018608: 705a strb r2, [r3, #1]
msg_out->hlen = netif->hwaddr_len;
801860a: 68fb ldr r3, [r7, #12]
801860c: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
8018610: 697b ldr r3, [r7, #20]
8018612: 709a strb r2, [r3, #2]
msg_out->xid = lwip_htonl(dhcp->xid);
8018614: 68bb ldr r3, [r7, #8]
8018616: 681b ldr r3, [r3, #0]
8018618: 4618 mov r0, r3
801861a: f7f6 fc46 bl 800eeaa <lwip_htonl>
801861e: 4602 mov r2, r0
8018620: 697b ldr r3, [r7, #20]
8018622: 605a str r2, [r3, #4]
/* we don't need the broadcast flag since we can receive unicast traffic
before being fully configured! */
/* set ciaddr to netif->ip_addr based on message_type and state */
if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
8018624: 79fb ldrb r3, [r7, #7]
8018626: 2b08 cmp r3, #8
8018628: d010 beq.n 801864c <dhcp_create_msg+0xfc>
801862a: 79fb ldrb r3, [r7, #7]
801862c: 2b04 cmp r3, #4
801862e: d00d beq.n 801864c <dhcp_create_msg+0xfc>
8018630: 79fb ldrb r3, [r7, #7]
8018632: 2b07 cmp r3, #7
8018634: d00a beq.n 801864c <dhcp_create_msg+0xfc>
8018636: 79fb ldrb r3, [r7, #7]
8018638: 2b03 cmp r3, #3
801863a: d10c bne.n 8018656 <dhcp_create_msg+0x106>
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
801863c: 68bb ldr r3, [r7, #8]
801863e: 795b ldrb r3, [r3, #5]
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
8018640: 2b05 cmp r3, #5
8018642: d003 beq.n 801864c <dhcp_create_msg+0xfc>
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
8018644: 68bb ldr r3, [r7, #8]
8018646: 795b ldrb r3, [r3, #5]
8018648: 2b04 cmp r3, #4
801864a: d104 bne.n 8018656 <dhcp_create_msg+0x106>
ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif));
801864c: 68fb ldr r3, [r7, #12]
801864e: 3304 adds r3, #4
8018650: 681a ldr r2, [r3, #0]
8018652: 697b ldr r3, [r7, #20]
8018654: 60da str r2, [r3, #12]
}
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018656: 2300 movs r3, #0
8018658: 83fb strh r3, [r7, #30]
801865a: e00c b.n 8018676 <dhcp_create_msg+0x126>
/* copy netif hardware address (padded with zeroes through memset already) */
msg_out->chaddr[i] = netif->hwaddr[i];
801865c: 8bfa ldrh r2, [r7, #30]
801865e: 8bfb ldrh r3, [r7, #30]
8018660: 68f9 ldr r1, [r7, #12]
8018662: 440a add r2, r1
8018664: f892 102a ldrb.w r1, [r2, #42] ; 0x2a
8018668: 697a ldr r2, [r7, #20]
801866a: 4413 add r3, r2
801866c: 460a mov r2, r1
801866e: 771a strb r2, [r3, #28]
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018670: 8bfb ldrh r3, [r7, #30]
8018672: 3301 adds r3, #1
8018674: 83fb strh r3, [r7, #30]
8018676: 8bfb ldrh r3, [r7, #30]
8018678: 2b05 cmp r3, #5
801867a: d9ef bls.n 801865c <dhcp_create_msg+0x10c>
}
msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
801867c: 697b ldr r3, [r7, #20]
801867e: 2200 movs r2, #0
8018680: f042 0263 orr.w r2, r2, #99 ; 0x63
8018684: f883 20ec strb.w r2, [r3, #236] ; 0xec
8018688: 2200 movs r2, #0
801868a: f062 027d orn r2, r2, #125 ; 0x7d
801868e: f883 20ed strb.w r2, [r3, #237] ; 0xed
8018692: 2200 movs r2, #0
8018694: f042 0253 orr.w r2, r2, #83 ; 0x53
8018698: f883 20ee strb.w r2, [r3, #238] ; 0xee
801869c: 2200 movs r2, #0
801869e: f042 0263 orr.w r2, r2, #99 ; 0x63
80186a2: f883 20ef strb.w r2, [r3, #239] ; 0xef
/* Add option MESSAGE_TYPE */
options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
80186a6: 697b ldr r3, [r7, #20]
80186a8: f103 01f0 add.w r1, r3, #240 ; 0xf0
80186ac: 2301 movs r3, #1
80186ae: 2235 movs r2, #53 ; 0x35
80186b0: 2000 movs r0, #0
80186b2: f7ff fadd bl 8017c70 <dhcp_option>
80186b6: 4603 mov r3, r0
80186b8: 827b strh r3, [r7, #18]
options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type);
80186ba: 697b ldr r3, [r7, #20]
80186bc: f103 01f0 add.w r1, r3, #240 ; 0xf0
80186c0: 79fa ldrb r2, [r7, #7]
80186c2: 8a7b ldrh r3, [r7, #18]
80186c4: 4618 mov r0, r3
80186c6: f7ff fb07 bl 8017cd8 <dhcp_option_byte>
80186ca: 4603 mov r3, r0
80186cc: 827b strh r3, [r7, #18]
if (options_out_len) {
80186ce: 683b ldr r3, [r7, #0]
80186d0: 2b00 cmp r3, #0
80186d2: d002 beq.n 80186da <dhcp_create_msg+0x18a>
*options_out_len = options_out_len_loc;
80186d4: 683b ldr r3, [r7, #0]
80186d6: 8a7a ldrh r2, [r7, #18]
80186d8: 801a strh r2, [r3, #0]
}
return p_out;
80186da: 69bb ldr r3, [r7, #24]
}
80186dc: 4618 mov r0, r3
80186de: 3720 adds r7, #32
80186e0: 46bd mov sp, r7
80186e2: bd80 pop {r7, pc}
80186e4: 0801e398 .word 0x0801e398
80186e8: 0801e6b8 .word 0x0801e6b8
80186ec: 0801e3f8 .word 0x0801e3f8
80186f0: 0801e6d8 .word 0x0801e6d8
80186f4: 0801e6f8 .word 0x0801e6f8
80186f8: 20008774 .word 0x20008774
080186fc <dhcp_option_trailer>:
* Adds the END option to the DHCP message, and if
* necessary, up to three padding bytes.
*/
static void
dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out)
{
80186fc: b580 push {r7, lr}
80186fe: b084 sub sp, #16
8018700: af00 add r7, sp, #0
8018702: 4603 mov r3, r0
8018704: 60b9 str r1, [r7, #8]
8018706: 607a str r2, [r7, #4]
8018708: 81fb strh r3, [r7, #14]
options[options_out_len++] = DHCP_OPTION_END;
801870a: 89fb ldrh r3, [r7, #14]
801870c: 1c5a adds r2, r3, #1
801870e: 81fa strh r2, [r7, #14]
8018710: 461a mov r2, r3
8018712: 68bb ldr r3, [r7, #8]
8018714: 4413 add r3, r2
8018716: 22ff movs r2, #255 ; 0xff
8018718: 701a strb r2, [r3, #0]
/* packet is too small, or not 4 byte aligned? */
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
801871a: e007 b.n 801872c <dhcp_option_trailer+0x30>
(options_out_len < DHCP_OPTIONS_LEN)) {
/* add a fill/padding byte */
options[options_out_len++] = 0;
801871c: 89fb ldrh r3, [r7, #14]
801871e: 1c5a adds r2, r3, #1
8018720: 81fa strh r2, [r7, #14]
8018722: 461a mov r2, r3
8018724: 68bb ldr r3, [r7, #8]
8018726: 4413 add r3, r2
8018728: 2200 movs r2, #0
801872a: 701a strb r2, [r3, #0]
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
801872c: 89fb ldrh r3, [r7, #14]
801872e: 2b43 cmp r3, #67 ; 0x43
8018730: d904 bls.n 801873c <dhcp_option_trailer+0x40>
8018732: 89fb ldrh r3, [r7, #14]
8018734: f003 0303 and.w r3, r3, #3
8018738: 2b00 cmp r3, #0
801873a: d002 beq.n 8018742 <dhcp_option_trailer+0x46>
801873c: 89fb ldrh r3, [r7, #14]
801873e: 2b43 cmp r3, #67 ; 0x43
8018740: d9ec bls.n 801871c <dhcp_option_trailer+0x20>
}
/* shrink the pbuf to the actual content length */
pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len));
8018742: 89fb ldrh r3, [r7, #14]
8018744: 33f0 adds r3, #240 ; 0xf0
8018746: b29b uxth r3, r3
8018748: 4619 mov r1, r3
801874a: 6878 ldr r0, [r7, #4]
801874c: f7f7 fdc6 bl 80102dc <pbuf_realloc>
}
8018750: bf00 nop
8018752: 3710 adds r7, #16
8018754: 46bd mov sp, r7
8018756: bd80 pop {r7, pc}
08018758 <dhcp_supplied_address>:
* @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
* 0 otherwise
*/
u8_t
dhcp_supplied_address(const struct netif *netif)
{
8018758: b480 push {r7}
801875a: b085 sub sp, #20
801875c: af00 add r7, sp, #0
801875e: 6078 str r0, [r7, #4]
if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) {
8018760: 687b ldr r3, [r7, #4]
8018762: 2b00 cmp r3, #0
8018764: d017 beq.n 8018796 <dhcp_supplied_address+0x3e>
8018766: 687b ldr r3, [r7, #4]
8018768: 6a5b ldr r3, [r3, #36] ; 0x24
801876a: 2b00 cmp r3, #0
801876c: d013 beq.n 8018796 <dhcp_supplied_address+0x3e>
struct dhcp *dhcp = netif_dhcp_data(netif);
801876e: 687b ldr r3, [r7, #4]
8018770: 6a5b ldr r3, [r3, #36] ; 0x24
8018772: 60fb str r3, [r7, #12]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018774: 68fb ldr r3, [r7, #12]
8018776: 795b ldrb r3, [r3, #5]
8018778: 2b0a cmp r3, #10
801877a: d007 beq.n 801878c <dhcp_supplied_address+0x34>
801877c: 68fb ldr r3, [r7, #12]
801877e: 795b ldrb r3, [r3, #5]
8018780: 2b05 cmp r3, #5
8018782: d003 beq.n 801878c <dhcp_supplied_address+0x34>
(dhcp->state == DHCP_STATE_REBINDING);
8018784: 68fb ldr r3, [r7, #12]
8018786: 795b ldrb r3, [r3, #5]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018788: 2b04 cmp r3, #4
801878a: d101 bne.n 8018790 <dhcp_supplied_address+0x38>
801878c: 2301 movs r3, #1
801878e: e000 b.n 8018792 <dhcp_supplied_address+0x3a>
8018790: 2300 movs r3, #0
8018792: b2db uxtb r3, r3
8018794: e000 b.n 8018798 <dhcp_supplied_address+0x40>
}
return 0;
8018796: 2300 movs r3, #0
}
8018798: 4618 mov r0, r3
801879a: 3714 adds r7, #20
801879c: 46bd mov sp, r7
801879e: f85d 7b04 ldr.w r7, [sp], #4
80187a2: 4770 bx lr
080187a4 <etharp_free_entry>:
#endif /* ARP_QUEUEING */
/** Clean up ARP table entries */
static void
etharp_free_entry(int i)
{
80187a4: b580 push {r7, lr}
80187a6: b082 sub sp, #8
80187a8: af00 add r7, sp, #0
80187aa: 6078 str r0, [r7, #4]
/* remove from SNMP ARP index tree */
mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
/* and empty packet queue */
if (arp_table[i].q != NULL) {
80187ac: 4915 ldr r1, [pc, #84] ; (8018804 <etharp_free_entry+0x60>)
80187ae: 687a ldr r2, [r7, #4]
80187b0: 4613 mov r3, r2
80187b2: 005b lsls r3, r3, #1
80187b4: 4413 add r3, r2
80187b6: 00db lsls r3, r3, #3
80187b8: 440b add r3, r1
80187ba: 681b ldr r3, [r3, #0]
80187bc: 2b00 cmp r3, #0
80187be: d013 beq.n 80187e8 <etharp_free_entry+0x44>
/* remove all queued packets */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
free_etharp_q(arp_table[i].q);
80187c0: 4910 ldr r1, [pc, #64] ; (8018804 <etharp_free_entry+0x60>)
80187c2: 687a ldr r2, [r7, #4]
80187c4: 4613 mov r3, r2
80187c6: 005b lsls r3, r3, #1
80187c8: 4413 add r3, r2
80187ca: 00db lsls r3, r3, #3
80187cc: 440b add r3, r1
80187ce: 681b ldr r3, [r3, #0]
80187d0: 4618 mov r0, r3
80187d2: f7f7 ff09 bl 80105e8 <pbuf_free>
arp_table[i].q = NULL;
80187d6: 490b ldr r1, [pc, #44] ; (8018804 <etharp_free_entry+0x60>)
80187d8: 687a ldr r2, [r7, #4]
80187da: 4613 mov r3, r2
80187dc: 005b lsls r3, r3, #1
80187de: 4413 add r3, r2
80187e0: 00db lsls r3, r3, #3
80187e2: 440b add r3, r1
80187e4: 2200 movs r2, #0
80187e6: 601a str r2, [r3, #0]
}
/* recycle entry for re-use */
arp_table[i].state = ETHARP_STATE_EMPTY;
80187e8: 4906 ldr r1, [pc, #24] ; (8018804 <etharp_free_entry+0x60>)
80187ea: 687a ldr r2, [r7, #4]
80187ec: 4613 mov r3, r2
80187ee: 005b lsls r3, r3, #1
80187f0: 4413 add r3, r2
80187f2: 00db lsls r3, r3, #3
80187f4: 440b add r3, r1
80187f6: 3314 adds r3, #20
80187f8: 2200 movs r2, #0
80187fa: 701a strb r2, [r3, #0]
arp_table[i].ctime = 0;
arp_table[i].netif = NULL;
ip4_addr_set_zero(&arp_table[i].ipaddr);
arp_table[i].ethaddr = ethzero;
#endif /* LWIP_DEBUG */
}
80187fc: bf00 nop
80187fe: 3708 adds r7, #8
8018800: 46bd mov sp, r7
8018802: bd80 pop {r7, pc}
8018804: 20008778 .word 0x20008778
08018808 <etharp_tmr>:
* This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
* in order to expire entries in the ARP table.
*/
void
etharp_tmr(void)
{
8018808: b580 push {r7, lr}
801880a: b082 sub sp, #8
801880c: af00 add r7, sp, #0
int i;
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
/* remove expired entries from the ARP table */
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
801880e: 2300 movs r3, #0
8018810: 607b str r3, [r7, #4]
8018812: e096 b.n 8018942 <etharp_tmr+0x13a>
u8_t state = arp_table[i].state;
8018814: 494f ldr r1, [pc, #316] ; (8018954 <etharp_tmr+0x14c>)
8018816: 687a ldr r2, [r7, #4]
8018818: 4613 mov r3, r2
801881a: 005b lsls r3, r3, #1
801881c: 4413 add r3, r2
801881e: 00db lsls r3, r3, #3
8018820: 440b add r3, r1
8018822: 3314 adds r3, #20
8018824: 781b ldrb r3, [r3, #0]
8018826: 70fb strb r3, [r7, #3]
if (state != ETHARP_STATE_EMPTY
8018828: 78fb ldrb r3, [r7, #3]
801882a: 2b00 cmp r3, #0
801882c: f000 8086 beq.w 801893c <etharp_tmr+0x134>
#if ETHARP_SUPPORT_STATIC_ENTRIES
&& (state != ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
) {
arp_table[i].ctime++;
8018830: 4948 ldr r1, [pc, #288] ; (8018954 <etharp_tmr+0x14c>)
8018832: 687a ldr r2, [r7, #4]
8018834: 4613 mov r3, r2
8018836: 005b lsls r3, r3, #1
8018838: 4413 add r3, r2
801883a: 00db lsls r3, r3, #3
801883c: 440b add r3, r1
801883e: 3312 adds r3, #18
8018840: 881b ldrh r3, [r3, #0]
8018842: 3301 adds r3, #1
8018844: b298 uxth r0, r3
8018846: 4943 ldr r1, [pc, #268] ; (8018954 <etharp_tmr+0x14c>)
8018848: 687a ldr r2, [r7, #4]
801884a: 4613 mov r3, r2
801884c: 005b lsls r3, r3, #1
801884e: 4413 add r3, r2
8018850: 00db lsls r3, r3, #3
8018852: 440b add r3, r1
8018854: 3312 adds r3, #18
8018856: 4602 mov r2, r0
8018858: 801a strh r2, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
801885a: 493e ldr r1, [pc, #248] ; (8018954 <etharp_tmr+0x14c>)
801885c: 687a ldr r2, [r7, #4]
801885e: 4613 mov r3, r2
8018860: 005b lsls r3, r3, #1
8018862: 4413 add r3, r2
8018864: 00db lsls r3, r3, #3
8018866: 440b add r3, r1
8018868: 3312 adds r3, #18
801886a: 881b ldrh r3, [r3, #0]
801886c: f5b3 7f96 cmp.w r3, #300 ; 0x12c
8018870: d215 bcs.n 801889e <etharp_tmr+0x96>
((arp_table[i].state == ETHARP_STATE_PENDING) &&
8018872: 4938 ldr r1, [pc, #224] ; (8018954 <etharp_tmr+0x14c>)
8018874: 687a ldr r2, [r7, #4]
8018876: 4613 mov r3, r2
8018878: 005b lsls r3, r3, #1
801887a: 4413 add r3, r2
801887c: 00db lsls r3, r3, #3
801887e: 440b add r3, r1
8018880: 3314 adds r3, #20
8018882: 781b ldrb r3, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
8018884: 2b01 cmp r3, #1
8018886: d10e bne.n 80188a6 <etharp_tmr+0x9e>
(arp_table[i].ctime >= ARP_MAXPENDING))) {
8018888: 4932 ldr r1, [pc, #200] ; (8018954 <etharp_tmr+0x14c>)
801888a: 687a ldr r2, [r7, #4]
801888c: 4613 mov r3, r2
801888e: 005b lsls r3, r3, #1
8018890: 4413 add r3, r2
8018892: 00db lsls r3, r3, #3
8018894: 440b add r3, r1
8018896: 3312 adds r3, #18
8018898: 881b ldrh r3, [r3, #0]
((arp_table[i].state == ETHARP_STATE_PENDING) &&
801889a: 2b04 cmp r3, #4
801889c: d903 bls.n 80188a6 <etharp_tmr+0x9e>
/* pending or stable entry has become old! */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
/* clean up entries that have just been expired */
etharp_free_entry(i);
801889e: 6878 ldr r0, [r7, #4]
80188a0: f7ff ff80 bl 80187a4 <etharp_free_entry>
80188a4: e04a b.n 801893c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
80188a6: 492b ldr r1, [pc, #172] ; (8018954 <etharp_tmr+0x14c>)
80188a8: 687a ldr r2, [r7, #4]
80188aa: 4613 mov r3, r2
80188ac: 005b lsls r3, r3, #1
80188ae: 4413 add r3, r2
80188b0: 00db lsls r3, r3, #3
80188b2: 440b add r3, r1
80188b4: 3314 adds r3, #20
80188b6: 781b ldrb r3, [r3, #0]
80188b8: 2b03 cmp r3, #3
80188ba: d10a bne.n 80188d2 <etharp_tmr+0xca>
/* Don't send more than one request every 2 seconds. */
arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
80188bc: 4925 ldr r1, [pc, #148] ; (8018954 <etharp_tmr+0x14c>)
80188be: 687a ldr r2, [r7, #4]
80188c0: 4613 mov r3, r2
80188c2: 005b lsls r3, r3, #1
80188c4: 4413 add r3, r2
80188c6: 00db lsls r3, r3, #3
80188c8: 440b add r3, r1
80188ca: 3314 adds r3, #20
80188cc: 2204 movs r2, #4
80188ce: 701a strb r2, [r3, #0]
80188d0: e034 b.n 801893c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
80188d2: 4920 ldr r1, [pc, #128] ; (8018954 <etharp_tmr+0x14c>)
80188d4: 687a ldr r2, [r7, #4]
80188d6: 4613 mov r3, r2
80188d8: 005b lsls r3, r3, #1
80188da: 4413 add r3, r2
80188dc: 00db lsls r3, r3, #3
80188de: 440b add r3, r1
80188e0: 3314 adds r3, #20
80188e2: 781b ldrb r3, [r3, #0]
80188e4: 2b04 cmp r3, #4
80188e6: d10a bne.n 80188fe <etharp_tmr+0xf6>
/* Reset state to stable, so that the next transmitted packet will
re-send an ARP request. */
arp_table[i].state = ETHARP_STATE_STABLE;
80188e8: 491a ldr r1, [pc, #104] ; (8018954 <etharp_tmr+0x14c>)
80188ea: 687a ldr r2, [r7, #4]
80188ec: 4613 mov r3, r2
80188ee: 005b lsls r3, r3, #1
80188f0: 4413 add r3, r2
80188f2: 00db lsls r3, r3, #3
80188f4: 440b add r3, r1
80188f6: 3314 adds r3, #20
80188f8: 2202 movs r2, #2
80188fa: 701a strb r2, [r3, #0]
80188fc: e01e b.n 801893c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
80188fe: 4915 ldr r1, [pc, #84] ; (8018954 <etharp_tmr+0x14c>)
8018900: 687a ldr r2, [r7, #4]
8018902: 4613 mov r3, r2
8018904: 005b lsls r3, r3, #1
8018906: 4413 add r3, r2
8018908: 00db lsls r3, r3, #3
801890a: 440b add r3, r1
801890c: 3314 adds r3, #20
801890e: 781b ldrb r3, [r3, #0]
8018910: 2b01 cmp r3, #1
8018912: d113 bne.n 801893c <etharp_tmr+0x134>
/* still pending, resend an ARP query */
etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
8018914: 490f ldr r1, [pc, #60] ; (8018954 <etharp_tmr+0x14c>)
8018916: 687a ldr r2, [r7, #4]
8018918: 4613 mov r3, r2
801891a: 005b lsls r3, r3, #1
801891c: 4413 add r3, r2
801891e: 00db lsls r3, r3, #3
8018920: 440b add r3, r1
8018922: 3308 adds r3, #8
8018924: 6818 ldr r0, [r3, #0]
8018926: 687a ldr r2, [r7, #4]
8018928: 4613 mov r3, r2
801892a: 005b lsls r3, r3, #1
801892c: 4413 add r3, r2
801892e: 00db lsls r3, r3, #3
8018930: 4a08 ldr r2, [pc, #32] ; (8018954 <etharp_tmr+0x14c>)
8018932: 4413 add r3, r2
8018934: 3304 adds r3, #4
8018936: 4619 mov r1, r3
8018938: f000 fe72 bl 8019620 <etharp_request>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
801893c: 687b ldr r3, [r7, #4]
801893e: 3301 adds r3, #1
8018940: 607b str r3, [r7, #4]
8018942: 687b ldr r3, [r7, #4]
8018944: 2b09 cmp r3, #9
8018946: f77f af65 ble.w 8018814 <etharp_tmr+0xc>
}
}
}
}
801894a: bf00 nop
801894c: 3708 adds r7, #8
801894e: 46bd mov sp, r7
8018950: bd80 pop {r7, pc}
8018952: bf00 nop
8018954: 20008778 .word 0x20008778
08018958 <etharp_find_entry>:
* @return The ARP entry index that matched or is created, ERR_MEM if no
* entry is found or could be recycled.
*/
static s16_t
etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
{
8018958: b580 push {r7, lr}
801895a: b08a sub sp, #40 ; 0x28
801895c: af00 add r7, sp, #0
801895e: 60f8 str r0, [r7, #12]
8018960: 460b mov r3, r1
8018962: 607a str r2, [r7, #4]
8018964: 72fb strb r3, [r7, #11]
s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
8018966: 230a movs r3, #10
8018968: 84fb strh r3, [r7, #38] ; 0x26
801896a: 230a movs r3, #10
801896c: 84bb strh r3, [r7, #36] ; 0x24
s16_t empty = ARP_TABLE_SIZE;
801896e: 230a movs r3, #10
8018970: 847b strh r3, [r7, #34] ; 0x22
s16_t i = 0;
8018972: 2300 movs r3, #0
8018974: 843b strh r3, [r7, #32]
/* oldest entry with packets on queue */
s16_t old_queue = ARP_TABLE_SIZE;
8018976: 230a movs r3, #10
8018978: 83fb strh r3, [r7, #30]
/* its age */
u16_t age_queue = 0, age_pending = 0, age_stable = 0;
801897a: 2300 movs r3, #0
801897c: 83bb strh r3, [r7, #28]
801897e: 2300 movs r3, #0
8018980: 837b strh r3, [r7, #26]
8018982: 2300 movs r3, #0
8018984: 833b strh r3, [r7, #24]
* 4) remember the oldest pending entry with queued packets (if any)
* 5) search for a matching IP entry, either pending or stable
* until 5 matches, or all entries are searched for.
*/
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018986: 2300 movs r3, #0
8018988: 843b strh r3, [r7, #32]
801898a: e0ae b.n 8018aea <etharp_find_entry+0x192>
u8_t state = arp_table[i].state;
801898c: f9b7 2020 ldrsh.w r2, [r7, #32]
8018990: 49a6 ldr r1, [pc, #664] ; (8018c2c <etharp_find_entry+0x2d4>)
8018992: 4613 mov r3, r2
8018994: 005b lsls r3, r3, #1
8018996: 4413 add r3, r2
8018998: 00db lsls r3, r3, #3
801899a: 440b add r3, r1
801899c: 3314 adds r3, #20
801899e: 781b ldrb r3, [r3, #0]
80189a0: 75fb strb r3, [r7, #23]
/* no empty entry found yet and now we do find one? */
if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
80189a2: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
80189a6: 2b0a cmp r3, #10
80189a8: d105 bne.n 80189b6 <etharp_find_entry+0x5e>
80189aa: 7dfb ldrb r3, [r7, #23]
80189ac: 2b00 cmp r3, #0
80189ae: d102 bne.n 80189b6 <etharp_find_entry+0x5e>
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
/* remember first empty entry */
empty = i;
80189b0: 8c3b ldrh r3, [r7, #32]
80189b2: 847b strh r3, [r7, #34] ; 0x22
80189b4: e095 b.n 8018ae2 <etharp_find_entry+0x18a>
} else if (state != ETHARP_STATE_EMPTY) {
80189b6: 7dfb ldrb r3, [r7, #23]
80189b8: 2b00 cmp r3, #0
80189ba: f000 8092 beq.w 8018ae2 <etharp_find_entry+0x18a>
LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
80189be: 7dfb ldrb r3, [r7, #23]
80189c0: 2b01 cmp r3, #1
80189c2: d009 beq.n 80189d8 <etharp_find_entry+0x80>
80189c4: 7dfb ldrb r3, [r7, #23]
80189c6: 2b01 cmp r3, #1
80189c8: d806 bhi.n 80189d8 <etharp_find_entry+0x80>
80189ca: 4b99 ldr r3, [pc, #612] ; (8018c30 <etharp_find_entry+0x2d8>)
80189cc: f44f 7292 mov.w r2, #292 ; 0x124
80189d0: 4998 ldr r1, [pc, #608] ; (8018c34 <etharp_find_entry+0x2dc>)
80189d2: 4899 ldr r0, [pc, #612] ; (8018c38 <etharp_find_entry+0x2e0>)
80189d4: f002 fb1e bl 801b014 <iprintf>
state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
/* if given, does IP address match IP address in ARP entry? */
if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
80189d8: 68fb ldr r3, [r7, #12]
80189da: 2b00 cmp r3, #0
80189dc: d020 beq.n 8018a20 <etharp_find_entry+0xc8>
80189de: 68fb ldr r3, [r7, #12]
80189e0: 6819 ldr r1, [r3, #0]
80189e2: f9b7 2020 ldrsh.w r2, [r7, #32]
80189e6: 4891 ldr r0, [pc, #580] ; (8018c2c <etharp_find_entry+0x2d4>)
80189e8: 4613 mov r3, r2
80189ea: 005b lsls r3, r3, #1
80189ec: 4413 add r3, r2
80189ee: 00db lsls r3, r3, #3
80189f0: 4403 add r3, r0
80189f2: 3304 adds r3, #4
80189f4: 681b ldr r3, [r3, #0]
80189f6: 4299 cmp r1, r3
80189f8: d112 bne.n 8018a20 <etharp_find_entry+0xc8>
#if ETHARP_TABLE_MATCH_NETIF
&& ((netif == NULL) || (netif == arp_table[i].netif))
80189fa: 687b ldr r3, [r7, #4]
80189fc: 2b00 cmp r3, #0
80189fe: d00c beq.n 8018a1a <etharp_find_entry+0xc2>
8018a00: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a04: 4989 ldr r1, [pc, #548] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a06: 4613 mov r3, r2
8018a08: 005b lsls r3, r3, #1
8018a0a: 4413 add r3, r2
8018a0c: 00db lsls r3, r3, #3
8018a0e: 440b add r3, r1
8018a10: 3308 adds r3, #8
8018a12: 681b ldr r3, [r3, #0]
8018a14: 687a ldr r2, [r7, #4]
8018a16: 429a cmp r2, r3
8018a18: d102 bne.n 8018a20 <etharp_find_entry+0xc8>
#endif /* ETHARP_TABLE_MATCH_NETIF */
) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
/* found exact IP address match, simply bail out */
return i;
8018a1a: f9b7 3020 ldrsh.w r3, [r7, #32]
8018a1e: e100 b.n 8018c22 <etharp_find_entry+0x2ca>
}
/* pending entry? */
if (state == ETHARP_STATE_PENDING) {
8018a20: 7dfb ldrb r3, [r7, #23]
8018a22: 2b01 cmp r3, #1
8018a24: d140 bne.n 8018aa8 <etharp_find_entry+0x150>
/* pending with queued packets? */
if (arp_table[i].q != NULL) {
8018a26: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a2a: 4980 ldr r1, [pc, #512] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a2c: 4613 mov r3, r2
8018a2e: 005b lsls r3, r3, #1
8018a30: 4413 add r3, r2
8018a32: 00db lsls r3, r3, #3
8018a34: 440b add r3, r1
8018a36: 681b ldr r3, [r3, #0]
8018a38: 2b00 cmp r3, #0
8018a3a: d01a beq.n 8018a72 <etharp_find_entry+0x11a>
if (arp_table[i].ctime >= age_queue) {
8018a3c: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a40: 497a ldr r1, [pc, #488] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a42: 4613 mov r3, r2
8018a44: 005b lsls r3, r3, #1
8018a46: 4413 add r3, r2
8018a48: 00db lsls r3, r3, #3
8018a4a: 440b add r3, r1
8018a4c: 3312 adds r3, #18
8018a4e: 881b ldrh r3, [r3, #0]
8018a50: 8bba ldrh r2, [r7, #28]
8018a52: 429a cmp r2, r3
8018a54: d845 bhi.n 8018ae2 <etharp_find_entry+0x18a>
old_queue = i;
8018a56: 8c3b ldrh r3, [r7, #32]
8018a58: 83fb strh r3, [r7, #30]
age_queue = arp_table[i].ctime;
8018a5a: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a5e: 4973 ldr r1, [pc, #460] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a60: 4613 mov r3, r2
8018a62: 005b lsls r3, r3, #1
8018a64: 4413 add r3, r2
8018a66: 00db lsls r3, r3, #3
8018a68: 440b add r3, r1
8018a6a: 3312 adds r3, #18
8018a6c: 881b ldrh r3, [r3, #0]
8018a6e: 83bb strh r3, [r7, #28]
8018a70: e037 b.n 8018ae2 <etharp_find_entry+0x18a>
}
} else
/* pending without queued packets? */
{
if (arp_table[i].ctime >= age_pending) {
8018a72: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a76: 496d ldr r1, [pc, #436] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a78: 4613 mov r3, r2
8018a7a: 005b lsls r3, r3, #1
8018a7c: 4413 add r3, r2
8018a7e: 00db lsls r3, r3, #3
8018a80: 440b add r3, r1
8018a82: 3312 adds r3, #18
8018a84: 881b ldrh r3, [r3, #0]
8018a86: 8b7a ldrh r2, [r7, #26]
8018a88: 429a cmp r2, r3
8018a8a: d82a bhi.n 8018ae2 <etharp_find_entry+0x18a>
old_pending = i;
8018a8c: 8c3b ldrh r3, [r7, #32]
8018a8e: 84fb strh r3, [r7, #38] ; 0x26
age_pending = arp_table[i].ctime;
8018a90: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a94: 4965 ldr r1, [pc, #404] ; (8018c2c <etharp_find_entry+0x2d4>)
8018a96: 4613 mov r3, r2
8018a98: 005b lsls r3, r3, #1
8018a9a: 4413 add r3, r2
8018a9c: 00db lsls r3, r3, #3
8018a9e: 440b add r3, r1
8018aa0: 3312 adds r3, #18
8018aa2: 881b ldrh r3, [r3, #0]
8018aa4: 837b strh r3, [r7, #26]
8018aa6: e01c b.n 8018ae2 <etharp_find_entry+0x18a>
}
}
/* stable entry? */
} else if (state >= ETHARP_STATE_STABLE) {
8018aa8: 7dfb ldrb r3, [r7, #23]
8018aaa: 2b01 cmp r3, #1
8018aac: d919 bls.n 8018ae2 <etharp_find_entry+0x18a>
/* don't record old_stable for static entries since they never expire */
if (state < ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* remember entry with oldest stable entry in oldest, its age in maxtime */
if (arp_table[i].ctime >= age_stable) {
8018aae: f9b7 2020 ldrsh.w r2, [r7, #32]
8018ab2: 495e ldr r1, [pc, #376] ; (8018c2c <etharp_find_entry+0x2d4>)
8018ab4: 4613 mov r3, r2
8018ab6: 005b lsls r3, r3, #1
8018ab8: 4413 add r3, r2
8018aba: 00db lsls r3, r3, #3
8018abc: 440b add r3, r1
8018abe: 3312 adds r3, #18
8018ac0: 881b ldrh r3, [r3, #0]
8018ac2: 8b3a ldrh r2, [r7, #24]
8018ac4: 429a cmp r2, r3
8018ac6: d80c bhi.n 8018ae2 <etharp_find_entry+0x18a>
old_stable = i;
8018ac8: 8c3b ldrh r3, [r7, #32]
8018aca: 84bb strh r3, [r7, #36] ; 0x24
age_stable = arp_table[i].ctime;
8018acc: f9b7 2020 ldrsh.w r2, [r7, #32]
8018ad0: 4956 ldr r1, [pc, #344] ; (8018c2c <etharp_find_entry+0x2d4>)
8018ad2: 4613 mov r3, r2
8018ad4: 005b lsls r3, r3, #1
8018ad6: 4413 add r3, r2
8018ad8: 00db lsls r3, r3, #3
8018ada: 440b add r3, r1
8018adc: 3312 adds r3, #18
8018ade: 881b ldrh r3, [r3, #0]
8018ae0: 833b strh r3, [r7, #24]
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018ae2: 8c3b ldrh r3, [r7, #32]
8018ae4: 3301 adds r3, #1
8018ae6: b29b uxth r3, r3
8018ae8: 843b strh r3, [r7, #32]
8018aea: f9b7 3020 ldrsh.w r3, [r7, #32]
8018aee: 2b09 cmp r3, #9
8018af0: f77f af4c ble.w 801898c <etharp_find_entry+0x34>
}
}
/* { we have no match } => try to create a new entry */
/* don't create new entry, only search? */
if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
8018af4: 7afb ldrb r3, [r7, #11]
8018af6: f003 0302 and.w r3, r3, #2
8018afa: 2b00 cmp r3, #0
8018afc: d108 bne.n 8018b10 <etharp_find_entry+0x1b8>
8018afe: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018b02: 2b0a cmp r3, #10
8018b04: d107 bne.n 8018b16 <etharp_find_entry+0x1be>
/* or no empty entry found and not allowed to recycle? */
((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
8018b06: 7afb ldrb r3, [r7, #11]
8018b08: f003 0301 and.w r3, r3, #1
8018b0c: 2b00 cmp r3, #0
8018b0e: d102 bne.n 8018b16 <etharp_find_entry+0x1be>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
return (s16_t)ERR_MEM;
8018b10: f04f 33ff mov.w r3, #4294967295
8018b14: e085 b.n 8018c22 <etharp_find_entry+0x2ca>
*
* { ETHARP_FLAG_TRY_HARD is set at this point }
*/
/* 1) empty entry available? */
if (empty < ARP_TABLE_SIZE) {
8018b16: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018b1a: 2b09 cmp r3, #9
8018b1c: dc02 bgt.n 8018b24 <etharp_find_entry+0x1cc>
i = empty;
8018b1e: 8c7b ldrh r3, [r7, #34] ; 0x22
8018b20: 843b strh r3, [r7, #32]
8018b22: e039 b.n 8018b98 <etharp_find_entry+0x240>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
} else {
/* 2) found recyclable stable entry? */
if (old_stable < ARP_TABLE_SIZE) {
8018b24: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24
8018b28: 2b09 cmp r3, #9
8018b2a: dc14 bgt.n 8018b56 <etharp_find_entry+0x1fe>
/* recycle oldest stable*/
i = old_stable;
8018b2c: 8cbb ldrh r3, [r7, #36] ; 0x24
8018b2e: 843b strh r3, [r7, #32]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
/* no queued packets should exist on stable entries */
LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
8018b30: f9b7 2020 ldrsh.w r2, [r7, #32]
8018b34: 493d ldr r1, [pc, #244] ; (8018c2c <etharp_find_entry+0x2d4>)
8018b36: 4613 mov r3, r2
8018b38: 005b lsls r3, r3, #1
8018b3a: 4413 add r3, r2
8018b3c: 00db lsls r3, r3, #3
8018b3e: 440b add r3, r1
8018b40: 681b ldr r3, [r3, #0]
8018b42: 2b00 cmp r3, #0
8018b44: d018 beq.n 8018b78 <etharp_find_entry+0x220>
8018b46: 4b3a ldr r3, [pc, #232] ; (8018c30 <etharp_find_entry+0x2d8>)
8018b48: f240 126d movw r2, #365 ; 0x16d
8018b4c: 493b ldr r1, [pc, #236] ; (8018c3c <etharp_find_entry+0x2e4>)
8018b4e: 483a ldr r0, [pc, #232] ; (8018c38 <etharp_find_entry+0x2e0>)
8018b50: f002 fa60 bl 801b014 <iprintf>
8018b54: e010 b.n 8018b78 <etharp_find_entry+0x220>
/* 3) found recyclable pending entry without queued packets? */
} else if (old_pending < ARP_TABLE_SIZE) {
8018b56: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26
8018b5a: 2b09 cmp r3, #9
8018b5c: dc02 bgt.n 8018b64 <etharp_find_entry+0x20c>
/* recycle oldest pending */
i = old_pending;
8018b5e: 8cfb ldrh r3, [r7, #38] ; 0x26
8018b60: 843b strh r3, [r7, #32]
8018b62: e009 b.n 8018b78 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
/* 4) found recyclable pending entry with queued packets? */
} else if (old_queue < ARP_TABLE_SIZE) {
8018b64: f9b7 301e ldrsh.w r3, [r7, #30]
8018b68: 2b09 cmp r3, #9
8018b6a: dc02 bgt.n 8018b72 <etharp_find_entry+0x21a>
/* recycle oldest pending (queued packets are free in etharp_free_entry) */
i = old_queue;
8018b6c: 8bfb ldrh r3, [r7, #30]
8018b6e: 843b strh r3, [r7, #32]
8018b70: e002 b.n 8018b78 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
/* no empty or recyclable entries found */
} else {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
return (s16_t)ERR_MEM;
8018b72: f04f 33ff mov.w r3, #4294967295
8018b76: e054 b.n 8018c22 <etharp_find_entry+0x2ca>
}
/* { empty or recyclable entry found } */
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018b78: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b7c: 2b09 cmp r3, #9
8018b7e: dd06 ble.n 8018b8e <etharp_find_entry+0x236>
8018b80: 4b2b ldr r3, [pc, #172] ; (8018c30 <etharp_find_entry+0x2d8>)
8018b82: f240 127f movw r2, #383 ; 0x17f
8018b86: 492e ldr r1, [pc, #184] ; (8018c40 <etharp_find_entry+0x2e8>)
8018b88: 482b ldr r0, [pc, #172] ; (8018c38 <etharp_find_entry+0x2e0>)
8018b8a: f002 fa43 bl 801b014 <iprintf>
etharp_free_entry(i);
8018b8e: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b92: 4618 mov r0, r3
8018b94: f7ff fe06 bl 80187a4 <etharp_free_entry>
}
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018b98: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b9c: 2b09 cmp r3, #9
8018b9e: dd06 ble.n 8018bae <etharp_find_entry+0x256>
8018ba0: 4b23 ldr r3, [pc, #140] ; (8018c30 <etharp_find_entry+0x2d8>)
8018ba2: f240 1283 movw r2, #387 ; 0x183
8018ba6: 4926 ldr r1, [pc, #152] ; (8018c40 <etharp_find_entry+0x2e8>)
8018ba8: 4823 ldr r0, [pc, #140] ; (8018c38 <etharp_find_entry+0x2e0>)
8018baa: f002 fa33 bl 801b014 <iprintf>
LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
8018bae: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bb2: 491e ldr r1, [pc, #120] ; (8018c2c <etharp_find_entry+0x2d4>)
8018bb4: 4613 mov r3, r2
8018bb6: 005b lsls r3, r3, #1
8018bb8: 4413 add r3, r2
8018bba: 00db lsls r3, r3, #3
8018bbc: 440b add r3, r1
8018bbe: 3314 adds r3, #20
8018bc0: 781b ldrb r3, [r3, #0]
8018bc2: 2b00 cmp r3, #0
8018bc4: d006 beq.n 8018bd4 <etharp_find_entry+0x27c>
8018bc6: 4b1a ldr r3, [pc, #104] ; (8018c30 <etharp_find_entry+0x2d8>)
8018bc8: f240 1285 movw r2, #389 ; 0x185
8018bcc: 491d ldr r1, [pc, #116] ; (8018c44 <etharp_find_entry+0x2ec>)
8018bce: 481a ldr r0, [pc, #104] ; (8018c38 <etharp_find_entry+0x2e0>)
8018bd0: f002 fa20 bl 801b014 <iprintf>
arp_table[i].state == ETHARP_STATE_EMPTY);
/* IP address given? */
if (ipaddr != NULL) {
8018bd4: 68fb ldr r3, [r7, #12]
8018bd6: 2b00 cmp r3, #0
8018bd8: d00b beq.n 8018bf2 <etharp_find_entry+0x29a>
/* set IP address */
ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
8018bda: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bde: 68fb ldr r3, [r7, #12]
8018be0: 6819 ldr r1, [r3, #0]
8018be2: 4812 ldr r0, [pc, #72] ; (8018c2c <etharp_find_entry+0x2d4>)
8018be4: 4613 mov r3, r2
8018be6: 005b lsls r3, r3, #1
8018be8: 4413 add r3, r2
8018bea: 00db lsls r3, r3, #3
8018bec: 4403 add r3, r0
8018bee: 3304 adds r3, #4
8018bf0: 6019 str r1, [r3, #0]
}
arp_table[i].ctime = 0;
8018bf2: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bf6: 490d ldr r1, [pc, #52] ; (8018c2c <etharp_find_entry+0x2d4>)
8018bf8: 4613 mov r3, r2
8018bfa: 005b lsls r3, r3, #1
8018bfc: 4413 add r3, r2
8018bfe: 00db lsls r3, r3, #3
8018c00: 440b add r3, r1
8018c02: 3312 adds r3, #18
8018c04: 2200 movs r2, #0
8018c06: 801a strh r2, [r3, #0]
#if ETHARP_TABLE_MATCH_NETIF
arp_table[i].netif = netif;
8018c08: f9b7 2020 ldrsh.w r2, [r7, #32]
8018c0c: 4907 ldr r1, [pc, #28] ; (8018c2c <etharp_find_entry+0x2d4>)
8018c0e: 4613 mov r3, r2
8018c10: 005b lsls r3, r3, #1
8018c12: 4413 add r3, r2
8018c14: 00db lsls r3, r3, #3
8018c16: 440b add r3, r1
8018c18: 3308 adds r3, #8
8018c1a: 687a ldr r2, [r7, #4]
8018c1c: 601a str r2, [r3, #0]
#endif /* ETHARP_TABLE_MATCH_NETIF */
return (s16_t)i;
8018c1e: f9b7 3020 ldrsh.w r3, [r7, #32]
}
8018c22: 4618 mov r0, r3
8018c24: 3728 adds r7, #40 ; 0x28
8018c26: 46bd mov sp, r7
8018c28: bd80 pop {r7, pc}
8018c2a: bf00 nop
8018c2c: 20008778 .word 0x20008778
8018c30: 0801e738 .word 0x0801e738
8018c34: 0801e770 .word 0x0801e770
8018c38: 0801e7b0 .word 0x0801e7b0
8018c3c: 0801e7d8 .word 0x0801e7d8
8018c40: 0801e7f0 .word 0x0801e7f0
8018c44: 0801e804 .word 0x0801e804
08018c48 <etharp_update_arp_entry>:
*
* @see pbuf_free()
*/
static err_t
etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
{
8018c48: b580 push {r7, lr}
8018c4a: b088 sub sp, #32
8018c4c: af02 add r7, sp, #8
8018c4e: 60f8 str r0, [r7, #12]
8018c50: 60b9 str r1, [r7, #8]
8018c52: 607a str r2, [r7, #4]
8018c54: 70fb strb r3, [r7, #3]
s16_t i;
LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
8018c56: 68fb ldr r3, [r7, #12]
8018c58: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8018c5c: 2b06 cmp r3, #6
8018c5e: d006 beq.n 8018c6e <etharp_update_arp_entry+0x26>
8018c60: 4b48 ldr r3, [pc, #288] ; (8018d84 <etharp_update_arp_entry+0x13c>)
8018c62: f240 12a9 movw r2, #425 ; 0x1a9
8018c66: 4948 ldr r1, [pc, #288] ; (8018d88 <etharp_update_arp_entry+0x140>)
8018c68: 4848 ldr r0, [pc, #288] ; (8018d8c <etharp_update_arp_entry+0x144>)
8018c6a: f002 f9d3 bl 801b014 <iprintf>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
(u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
(u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
/* non-unicast address? */
if (ip4_addr_isany(ipaddr) ||
8018c6e: 68bb ldr r3, [r7, #8]
8018c70: 2b00 cmp r3, #0
8018c72: d012 beq.n 8018c9a <etharp_update_arp_entry+0x52>
8018c74: 68bb ldr r3, [r7, #8]
8018c76: 681b ldr r3, [r3, #0]
8018c78: 2b00 cmp r3, #0
8018c7a: d00e beq.n 8018c9a <etharp_update_arp_entry+0x52>
ip4_addr_isbroadcast(ipaddr, netif) ||
8018c7c: 68bb ldr r3, [r7, #8]
8018c7e: 681b ldr r3, [r3, #0]
8018c80: 68f9 ldr r1, [r7, #12]
8018c82: 4618 mov r0, r3
8018c84: f001 f91e bl 8019ec4 <ip4_addr_isbroadcast_u32>
8018c88: 4603 mov r3, r0
if (ip4_addr_isany(ipaddr) ||
8018c8a: 2b00 cmp r3, #0
8018c8c: d105 bne.n 8018c9a <etharp_update_arp_entry+0x52>
ip4_addr_ismulticast(ipaddr)) {
8018c8e: 68bb ldr r3, [r7, #8]
8018c90: 681b ldr r3, [r3, #0]
8018c92: f003 03f0 and.w r3, r3, #240 ; 0xf0
ip4_addr_isbroadcast(ipaddr, netif) ||
8018c96: 2be0 cmp r3, #224 ; 0xe0
8018c98: d102 bne.n 8018ca0 <etharp_update_arp_entry+0x58>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
8018c9a: f06f 030f mvn.w r3, #15
8018c9e: e06c b.n 8018d7a <etharp_update_arp_entry+0x132>
}
/* find or create ARP entry */
i = etharp_find_entry(ipaddr, flags, netif);
8018ca0: 78fb ldrb r3, [r7, #3]
8018ca2: 68fa ldr r2, [r7, #12]
8018ca4: 4619 mov r1, r3
8018ca6: 68b8 ldr r0, [r7, #8]
8018ca8: f7ff fe56 bl 8018958 <etharp_find_entry>
8018cac: 4603 mov r3, r0
8018cae: 82fb strh r3, [r7, #22]
/* bail out if no entry could be found */
if (i < 0) {
8018cb0: f9b7 3016 ldrsh.w r3, [r7, #22]
8018cb4: 2b00 cmp r3, #0
8018cb6: da02 bge.n 8018cbe <etharp_update_arp_entry+0x76>
return (err_t)i;
8018cb8: 8afb ldrh r3, [r7, #22]
8018cba: b25b sxtb r3, r3
8018cbc: e05d b.n 8018d7a <etharp_update_arp_entry+0x132>
return ERR_VAL;
} else
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* mark it stable */
arp_table[i].state = ETHARP_STATE_STABLE;
8018cbe: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cc2: 4933 ldr r1, [pc, #204] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018cc4: 4613 mov r3, r2
8018cc6: 005b lsls r3, r3, #1
8018cc8: 4413 add r3, r2
8018cca: 00db lsls r3, r3, #3
8018ccc: 440b add r3, r1
8018cce: 3314 adds r3, #20
8018cd0: 2202 movs r2, #2
8018cd2: 701a strb r2, [r3, #0]
}
/* record network interface */
arp_table[i].netif = netif;
8018cd4: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cd8: 492d ldr r1, [pc, #180] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018cda: 4613 mov r3, r2
8018cdc: 005b lsls r3, r3, #1
8018cde: 4413 add r3, r2
8018ce0: 00db lsls r3, r3, #3
8018ce2: 440b add r3, r1
8018ce4: 3308 adds r3, #8
8018ce6: 68fa ldr r2, [r7, #12]
8018ce8: 601a str r2, [r3, #0]
/* insert in SNMP ARP index tree */
mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
/* update address */
SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
8018cea: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cee: 4613 mov r3, r2
8018cf0: 005b lsls r3, r3, #1
8018cf2: 4413 add r3, r2
8018cf4: 00db lsls r3, r3, #3
8018cf6: 3308 adds r3, #8
8018cf8: 4a25 ldr r2, [pc, #148] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018cfa: 4413 add r3, r2
8018cfc: 3304 adds r3, #4
8018cfe: 2206 movs r2, #6
8018d00: 6879 ldr r1, [r7, #4]
8018d02: 4618 mov r0, r3
8018d04: f002 f973 bl 801afee <memcpy>
/* reset time stamp */
arp_table[i].ctime = 0;
8018d08: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d0c: 4920 ldr r1, [pc, #128] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018d0e: 4613 mov r3, r2
8018d10: 005b lsls r3, r3, #1
8018d12: 4413 add r3, r2
8018d14: 00db lsls r3, r3, #3
8018d16: 440b add r3, r1
8018d18: 3312 adds r3, #18
8018d1a: 2200 movs r2, #0
8018d1c: 801a strh r2, [r3, #0]
/* get the packet pointer */
p = q->p;
/* now queue entry can be freed */
memp_free(MEMP_ARP_QUEUE, q);
#else /* ARP_QUEUEING */
if (arp_table[i].q != NULL) {
8018d1e: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d22: 491b ldr r1, [pc, #108] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018d24: 4613 mov r3, r2
8018d26: 005b lsls r3, r3, #1
8018d28: 4413 add r3, r2
8018d2a: 00db lsls r3, r3, #3
8018d2c: 440b add r3, r1
8018d2e: 681b ldr r3, [r3, #0]
8018d30: 2b00 cmp r3, #0
8018d32: d021 beq.n 8018d78 <etharp_update_arp_entry+0x130>
struct pbuf *p = arp_table[i].q;
8018d34: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d38: 4915 ldr r1, [pc, #84] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018d3a: 4613 mov r3, r2
8018d3c: 005b lsls r3, r3, #1
8018d3e: 4413 add r3, r2
8018d40: 00db lsls r3, r3, #3
8018d42: 440b add r3, r1
8018d44: 681b ldr r3, [r3, #0]
8018d46: 613b str r3, [r7, #16]
arp_table[i].q = NULL;
8018d48: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d4c: 4910 ldr r1, [pc, #64] ; (8018d90 <etharp_update_arp_entry+0x148>)
8018d4e: 4613 mov r3, r2
8018d50: 005b lsls r3, r3, #1
8018d52: 4413 add r3, r2
8018d54: 00db lsls r3, r3, #3
8018d56: 440b add r3, r1
8018d58: 2200 movs r2, #0
8018d5a: 601a str r2, [r3, #0]
#endif /* ARP_QUEUEING */
/* send the queued IP packet */
ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
8018d5c: 68fb ldr r3, [r7, #12]
8018d5e: f103 022a add.w r2, r3, #42 ; 0x2a
8018d62: f44f 6300 mov.w r3, #2048 ; 0x800
8018d66: 9300 str r3, [sp, #0]
8018d68: 687b ldr r3, [r7, #4]
8018d6a: 6939 ldr r1, [r7, #16]
8018d6c: 68f8 ldr r0, [r7, #12]
8018d6e: f001 ffad bl 801accc <ethernet_output>
/* free the queued IP packet */
pbuf_free(p);
8018d72: 6938 ldr r0, [r7, #16]
8018d74: f7f7 fc38 bl 80105e8 <pbuf_free>
}
return ERR_OK;
8018d78: 2300 movs r3, #0
}
8018d7a: 4618 mov r0, r3
8018d7c: 3718 adds r7, #24
8018d7e: 46bd mov sp, r7
8018d80: bd80 pop {r7, pc}
8018d82: bf00 nop
8018d84: 0801e738 .word 0x0801e738
8018d88: 0801e830 .word 0x0801e830
8018d8c: 0801e7b0 .word 0x0801e7b0
8018d90: 20008778 .word 0x20008778
08018d94 <etharp_cleanup_netif>:
*
* @param netif points to a network interface
*/
void
etharp_cleanup_netif(struct netif *netif)
{
8018d94: b580 push {r7, lr}
8018d96: b084 sub sp, #16
8018d98: af00 add r7, sp, #0
8018d9a: 6078 str r0, [r7, #4]
int i;
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018d9c: 2300 movs r3, #0
8018d9e: 60fb str r3, [r7, #12]
8018da0: e01e b.n 8018de0 <etharp_cleanup_netif+0x4c>
u8_t state = arp_table[i].state;
8018da2: 4913 ldr r1, [pc, #76] ; (8018df0 <etharp_cleanup_netif+0x5c>)
8018da4: 68fa ldr r2, [r7, #12]
8018da6: 4613 mov r3, r2
8018da8: 005b lsls r3, r3, #1
8018daa: 4413 add r3, r2
8018dac: 00db lsls r3, r3, #3
8018dae: 440b add r3, r1
8018db0: 3314 adds r3, #20
8018db2: 781b ldrb r3, [r3, #0]
8018db4: 72fb strb r3, [r7, #11]
if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
8018db6: 7afb ldrb r3, [r7, #11]
8018db8: 2b00 cmp r3, #0
8018dba: d00e beq.n 8018dda <etharp_cleanup_netif+0x46>
8018dbc: 490c ldr r1, [pc, #48] ; (8018df0 <etharp_cleanup_netif+0x5c>)
8018dbe: 68fa ldr r2, [r7, #12]
8018dc0: 4613 mov r3, r2
8018dc2: 005b lsls r3, r3, #1
8018dc4: 4413 add r3, r2
8018dc6: 00db lsls r3, r3, #3
8018dc8: 440b add r3, r1
8018dca: 3308 adds r3, #8
8018dcc: 681b ldr r3, [r3, #0]
8018dce: 687a ldr r2, [r7, #4]
8018dd0: 429a cmp r2, r3
8018dd2: d102 bne.n 8018dda <etharp_cleanup_netif+0x46>
etharp_free_entry(i);
8018dd4: 68f8 ldr r0, [r7, #12]
8018dd6: f7ff fce5 bl 80187a4 <etharp_free_entry>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018dda: 68fb ldr r3, [r7, #12]
8018ddc: 3301 adds r3, #1
8018dde: 60fb str r3, [r7, #12]
8018de0: 68fb ldr r3, [r7, #12]
8018de2: 2b09 cmp r3, #9
8018de4: dddd ble.n 8018da2 <etharp_cleanup_netif+0xe>
}
}
}
8018de6: bf00 nop
8018de8: 3710 adds r7, #16
8018dea: 46bd mov sp, r7
8018dec: bd80 pop {r7, pc}
8018dee: bf00 nop
8018df0: 20008778 .word 0x20008778
08018df4 <etharp_input>:
*
* @see pbuf_free()
*/
void
etharp_input(struct pbuf *p, struct netif *netif)
{
8018df4: b5b0 push {r4, r5, r7, lr}
8018df6: b08a sub sp, #40 ; 0x28
8018df8: af04 add r7, sp, #16
8018dfa: 6078 str r0, [r7, #4]
8018dfc: 6039 str r1, [r7, #0]
ip4_addr_t sipaddr, dipaddr;
u8_t for_us;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
8018dfe: 683b ldr r3, [r7, #0]
8018e00: 2b00 cmp r3, #0
8018e02: d107 bne.n 8018e14 <etharp_input+0x20>
8018e04: 4b3f ldr r3, [pc, #252] ; (8018f04 <etharp_input+0x110>)
8018e06: f240 228a movw r2, #650 ; 0x28a
8018e0a: 493f ldr r1, [pc, #252] ; (8018f08 <etharp_input+0x114>)
8018e0c: 483f ldr r0, [pc, #252] ; (8018f0c <etharp_input+0x118>)
8018e0e: f002 f901 bl 801b014 <iprintf>
8018e12: e074 b.n 8018efe <etharp_input+0x10a>
hdr = (struct etharp_hdr *)p->payload;
8018e14: 687b ldr r3, [r7, #4]
8018e16: 685b ldr r3, [r3, #4]
8018e18: 613b str r3, [r7, #16]
/* RFC 826 "Packet Reception": */
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018e1a: 693b ldr r3, [r7, #16]
8018e1c: 881b ldrh r3, [r3, #0]
8018e1e: b29b uxth r3, r3
8018e20: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018e24: d10c bne.n 8018e40 <etharp_input+0x4c>
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018e26: 693b ldr r3, [r7, #16]
8018e28: 791b ldrb r3, [r3, #4]
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018e2a: 2b06 cmp r3, #6
8018e2c: d108 bne.n 8018e40 <etharp_input+0x4c>
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018e2e: 693b ldr r3, [r7, #16]
8018e30: 795b ldrb r3, [r3, #5]
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018e32: 2b04 cmp r3, #4
8018e34: d104 bne.n 8018e40 <etharp_input+0x4c>
(hdr->proto != PP_HTONS(ETHTYPE_IP))) {
8018e36: 693b ldr r3, [r7, #16]
8018e38: 885b ldrh r3, [r3, #2]
8018e3a: b29b uxth r3, r3
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018e3c: 2b08 cmp r3, #8
8018e3e: d003 beq.n 8018e48 <etharp_input+0x54>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
pbuf_free(p);
8018e40: 6878 ldr r0, [r7, #4]
8018e42: f7f7 fbd1 bl 80105e8 <pbuf_free>
return;
8018e46: e05a b.n 8018efe <etharp_input+0x10a>
autoip_arp_reply(netif, hdr);
#endif /* LWIP_AUTOIP */
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing (not using structure copy which breaks strict-aliasing rules). */
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
8018e48: 693b ldr r3, [r7, #16]
8018e4a: 330e adds r3, #14
8018e4c: 681b ldr r3, [r3, #0]
8018e4e: 60fb str r3, [r7, #12]
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
8018e50: 693b ldr r3, [r7, #16]
8018e52: 3318 adds r3, #24
8018e54: 681b ldr r3, [r3, #0]
8018e56: 60bb str r3, [r7, #8]
/* this interface is not configured? */
if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8018e58: 683b ldr r3, [r7, #0]
8018e5a: 3304 adds r3, #4
8018e5c: 681b ldr r3, [r3, #0]
8018e5e: 2b00 cmp r3, #0
8018e60: d102 bne.n 8018e68 <etharp_input+0x74>
for_us = 0;
8018e62: 2300 movs r3, #0
8018e64: 75fb strb r3, [r7, #23]
8018e66: e009 b.n 8018e7c <etharp_input+0x88>
} else {
/* ARP packet directed to us? */
for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
8018e68: 68ba ldr r2, [r7, #8]
8018e6a: 683b ldr r3, [r7, #0]
8018e6c: 3304 adds r3, #4
8018e6e: 681b ldr r3, [r3, #0]
8018e70: 429a cmp r2, r3
8018e72: bf0c ite eq
8018e74: 2301 moveq r3, #1
8018e76: 2300 movne r3, #0
8018e78: b2db uxtb r3, r3
8018e7a: 75fb strb r3, [r7, #23]
/* ARP message directed to us?
-> add IP address in ARP cache; assume requester wants to talk to us,
can result in directly sending the queued packets for this host.
ARP message not directed to us?
-> update the source IP address in the cache, if present */
etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
8018e7c: 693b ldr r3, [r7, #16]
8018e7e: f103 0208 add.w r2, r3, #8
8018e82: 7dfb ldrb r3, [r7, #23]
8018e84: 2b00 cmp r3, #0
8018e86: d001 beq.n 8018e8c <etharp_input+0x98>
8018e88: 2301 movs r3, #1
8018e8a: e000 b.n 8018e8e <etharp_input+0x9a>
8018e8c: 2302 movs r3, #2
8018e8e: f107 010c add.w r1, r7, #12
8018e92: 6838 ldr r0, [r7, #0]
8018e94: f7ff fed8 bl 8018c48 <etharp_update_arp_entry>
for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
/* now act on the message itself */
switch (hdr->opcode) {
8018e98: 693b ldr r3, [r7, #16]
8018e9a: 88db ldrh r3, [r3, #6]
8018e9c: b29b uxth r3, r3
8018e9e: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018ea2: d003 beq.n 8018eac <etharp_input+0xb8>
8018ea4: f5b3 7f00 cmp.w r3, #512 ; 0x200
8018ea8: d01e beq.n 8018ee8 <etharp_input+0xf4>
#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
break;
default:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
ETHARP_STATS_INC(etharp.err);
break;
8018eaa: e025 b.n 8018ef8 <etharp_input+0x104>
if (for_us) {
8018eac: 7dfb ldrb r3, [r7, #23]
8018eae: 2b00 cmp r3, #0
8018eb0: d021 beq.n 8018ef6 <etharp_input+0x102>
(struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
8018eb2: 683b ldr r3, [r7, #0]
8018eb4: f103 002a add.w r0, r3, #42 ; 0x2a
8018eb8: 693b ldr r3, [r7, #16]
8018eba: f103 0408 add.w r4, r3, #8
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
8018ebe: 683b ldr r3, [r7, #0]
8018ec0: f103 052a add.w r5, r3, #42 ; 0x2a
8018ec4: 683b ldr r3, [r7, #0]
8018ec6: 3304 adds r3, #4
&hdr->shwaddr, &sipaddr,
8018ec8: 693a ldr r2, [r7, #16]
8018eca: 3208 adds r2, #8
etharp_raw(netif,
8018ecc: 2102 movs r1, #2
8018ece: 9103 str r1, [sp, #12]
8018ed0: f107 010c add.w r1, r7, #12
8018ed4: 9102 str r1, [sp, #8]
8018ed6: 9201 str r2, [sp, #4]
8018ed8: 9300 str r3, [sp, #0]
8018eda: 462b mov r3, r5
8018edc: 4622 mov r2, r4
8018ede: 4601 mov r1, r0
8018ee0: 6838 ldr r0, [r7, #0]
8018ee2: f000 faef bl 80194c4 <etharp_raw>
break;
8018ee6: e006 b.n 8018ef6 <etharp_input+0x102>
dhcp_arp_reply(netif, &sipaddr);
8018ee8: f107 030c add.w r3, r7, #12
8018eec: 4619 mov r1, r3
8018eee: 6838 ldr r0, [r7, #0]
8018ef0: f7fe f9fe bl 80172f0 <dhcp_arp_reply>
break;
8018ef4: e000 b.n 8018ef8 <etharp_input+0x104>
break;
8018ef6: bf00 nop
}
/* free ARP packet */
pbuf_free(p);
8018ef8: 6878 ldr r0, [r7, #4]
8018efa: f7f7 fb75 bl 80105e8 <pbuf_free>
}
8018efe: 3718 adds r7, #24
8018f00: 46bd mov sp, r7
8018f02: bdb0 pop {r4, r5, r7, pc}
8018f04: 0801e738 .word 0x0801e738
8018f08: 0801e888 .word 0x0801e888
8018f0c: 0801e7b0 .word 0x0801e7b0
08018f10 <etharp_output_to_arp_index>:
/** Just a small helper function that sends a pbuf to an ethernet address
* in the arp_table specified by the index 'arp_idx'.
*/
static err_t
etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
{
8018f10: b580 push {r7, lr}
8018f12: b086 sub sp, #24
8018f14: af02 add r7, sp, #8
8018f16: 60f8 str r0, [r7, #12]
8018f18: 60b9 str r1, [r7, #8]
8018f1a: 4613 mov r3, r2
8018f1c: 71fb strb r3, [r7, #7]
LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
8018f1e: 79fa ldrb r2, [r7, #7]
8018f20: 4944 ldr r1, [pc, #272] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018f22: 4613 mov r3, r2
8018f24: 005b lsls r3, r3, #1
8018f26: 4413 add r3, r2
8018f28: 00db lsls r3, r3, #3
8018f2a: 440b add r3, r1
8018f2c: 3314 adds r3, #20
8018f2e: 781b ldrb r3, [r3, #0]
8018f30: 2b01 cmp r3, #1
8018f32: d806 bhi.n 8018f42 <etharp_output_to_arp_index+0x32>
8018f34: 4b40 ldr r3, [pc, #256] ; (8019038 <etharp_output_to_arp_index+0x128>)
8018f36: f240 22ef movw r2, #751 ; 0x2ef
8018f3a: 4940 ldr r1, [pc, #256] ; (801903c <etharp_output_to_arp_index+0x12c>)
8018f3c: 4840 ldr r0, [pc, #256] ; (8019040 <etharp_output_to_arp_index+0x130>)
8018f3e: f002 f869 bl 801b014 <iprintf>
arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
/* if arp table entry is about to expire: re-request it,
but only if its state is ETHARP_STATE_STABLE to prevent flooding the
network with ARP requests if this address is used frequently. */
if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
8018f42: 79fa ldrb r2, [r7, #7]
8018f44: 493b ldr r1, [pc, #236] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018f46: 4613 mov r3, r2
8018f48: 005b lsls r3, r3, #1
8018f4a: 4413 add r3, r2
8018f4c: 00db lsls r3, r3, #3
8018f4e: 440b add r3, r1
8018f50: 3314 adds r3, #20
8018f52: 781b ldrb r3, [r3, #0]
8018f54: 2b02 cmp r3, #2
8018f56: d153 bne.n 8019000 <etharp_output_to_arp_index+0xf0>
if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
8018f58: 79fa ldrb r2, [r7, #7]
8018f5a: 4936 ldr r1, [pc, #216] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018f5c: 4613 mov r3, r2
8018f5e: 005b lsls r3, r3, #1
8018f60: 4413 add r3, r2
8018f62: 00db lsls r3, r3, #3
8018f64: 440b add r3, r1
8018f66: 3312 adds r3, #18
8018f68: 881b ldrh r3, [r3, #0]
8018f6a: f5b3 7f8e cmp.w r3, #284 ; 0x11c
8018f6e: d919 bls.n 8018fa4 <etharp_output_to_arp_index+0x94>
/* issue a standard request using broadcast */
if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
8018f70: 79fa ldrb r2, [r7, #7]
8018f72: 4613 mov r3, r2
8018f74: 005b lsls r3, r3, #1
8018f76: 4413 add r3, r2
8018f78: 00db lsls r3, r3, #3
8018f7a: 4a2e ldr r2, [pc, #184] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018f7c: 4413 add r3, r2
8018f7e: 3304 adds r3, #4
8018f80: 4619 mov r1, r3
8018f82: 68f8 ldr r0, [r7, #12]
8018f84: f000 fb4c bl 8019620 <etharp_request>
8018f88: 4603 mov r3, r0
8018f8a: 2b00 cmp r3, #0
8018f8c: d138 bne.n 8019000 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018f8e: 79fa ldrb r2, [r7, #7]
8018f90: 4928 ldr r1, [pc, #160] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018f92: 4613 mov r3, r2
8018f94: 005b lsls r3, r3, #1
8018f96: 4413 add r3, r2
8018f98: 00db lsls r3, r3, #3
8018f9a: 440b add r3, r1
8018f9c: 3314 adds r3, #20
8018f9e: 2203 movs r2, #3
8018fa0: 701a strb r2, [r3, #0]
8018fa2: e02d b.n 8019000 <etharp_output_to_arp_index+0xf0>
}
} else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
8018fa4: 79fa ldrb r2, [r7, #7]
8018fa6: 4923 ldr r1, [pc, #140] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018fa8: 4613 mov r3, r2
8018faa: 005b lsls r3, r3, #1
8018fac: 4413 add r3, r2
8018fae: 00db lsls r3, r3, #3
8018fb0: 440b add r3, r1
8018fb2: 3312 adds r3, #18
8018fb4: 881b ldrh r3, [r3, #0]
8018fb6: f5b3 7f87 cmp.w r3, #270 ; 0x10e
8018fba: d321 bcc.n 8019000 <etharp_output_to_arp_index+0xf0>
/* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
8018fbc: 79fa ldrb r2, [r7, #7]
8018fbe: 4613 mov r3, r2
8018fc0: 005b lsls r3, r3, #1
8018fc2: 4413 add r3, r2
8018fc4: 00db lsls r3, r3, #3
8018fc6: 4a1b ldr r2, [pc, #108] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018fc8: 4413 add r3, r2
8018fca: 1d19 adds r1, r3, #4
8018fcc: 79fa ldrb r2, [r7, #7]
8018fce: 4613 mov r3, r2
8018fd0: 005b lsls r3, r3, #1
8018fd2: 4413 add r3, r2
8018fd4: 00db lsls r3, r3, #3
8018fd6: 3308 adds r3, #8
8018fd8: 4a16 ldr r2, [pc, #88] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018fda: 4413 add r3, r2
8018fdc: 3304 adds r3, #4
8018fde: 461a mov r2, r3
8018fe0: 68f8 ldr r0, [r7, #12]
8018fe2: f000 fafb bl 80195dc <etharp_request_dst>
8018fe6: 4603 mov r3, r0
8018fe8: 2b00 cmp r3, #0
8018fea: d109 bne.n 8019000 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018fec: 79fa ldrb r2, [r7, #7]
8018fee: 4911 ldr r1, [pc, #68] ; (8019034 <etharp_output_to_arp_index+0x124>)
8018ff0: 4613 mov r3, r2
8018ff2: 005b lsls r3, r3, #1
8018ff4: 4413 add r3, r2
8018ff6: 00db lsls r3, r3, #3
8018ff8: 440b add r3, r1
8018ffa: 3314 adds r3, #20
8018ffc: 2203 movs r2, #3
8018ffe: 701a strb r2, [r3, #0]
}
}
}
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
8019000: 68fb ldr r3, [r7, #12]
8019002: f103 012a add.w r1, r3, #42 ; 0x2a
8019006: 79fa ldrb r2, [r7, #7]
8019008: 4613 mov r3, r2
801900a: 005b lsls r3, r3, #1
801900c: 4413 add r3, r2
801900e: 00db lsls r3, r3, #3
8019010: 3308 adds r3, #8
8019012: 4a08 ldr r2, [pc, #32] ; (8019034 <etharp_output_to_arp_index+0x124>)
8019014: 4413 add r3, r2
8019016: 1d1a adds r2, r3, #4
8019018: f44f 6300 mov.w r3, #2048 ; 0x800
801901c: 9300 str r3, [sp, #0]
801901e: 4613 mov r3, r2
8019020: 460a mov r2, r1
8019022: 68b9 ldr r1, [r7, #8]
8019024: 68f8 ldr r0, [r7, #12]
8019026: f001 fe51 bl 801accc <ethernet_output>
801902a: 4603 mov r3, r0
}
801902c: 4618 mov r0, r3
801902e: 3710 adds r7, #16
8019030: 46bd mov sp, r7
8019032: bd80 pop {r7, pc}
8019034: 20008778 .word 0x20008778
8019038: 0801e738 .word 0x0801e738
801903c: 0801e8a8 .word 0x0801e8a8
8019040: 0801e7b0 .word 0x0801e7b0
08019044 <etharp_output>:
* - ERR_RTE No route to destination (no gateway to external networks),
* or the return type of either etharp_query() or ethernet_output().
*/
err_t
etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
{
8019044: b580 push {r7, lr}
8019046: b08a sub sp, #40 ; 0x28
8019048: af02 add r7, sp, #8
801904a: 60f8 str r0, [r7, #12]
801904c: 60b9 str r1, [r7, #8]
801904e: 607a str r2, [r7, #4]
const struct eth_addr *dest;
struct eth_addr mcastaddr;
const ip4_addr_t *dst_addr = ipaddr;
8019050: 687b ldr r3, [r7, #4]
8019052: 61bb str r3, [r7, #24]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("netif != NULL", netif != NULL);
8019054: 68fb ldr r3, [r7, #12]
8019056: 2b00 cmp r3, #0
8019058: d106 bne.n 8019068 <etharp_output+0x24>
801905a: 4b73 ldr r3, [pc, #460] ; (8019228 <etharp_output+0x1e4>)
801905c: f240 321e movw r2, #798 ; 0x31e
8019060: 4972 ldr r1, [pc, #456] ; (801922c <etharp_output+0x1e8>)
8019062: 4873 ldr r0, [pc, #460] ; (8019230 <etharp_output+0x1ec>)
8019064: f001 ffd6 bl 801b014 <iprintf>
LWIP_ASSERT("q != NULL", q != NULL);
8019068: 68bb ldr r3, [r7, #8]
801906a: 2b00 cmp r3, #0
801906c: d106 bne.n 801907c <etharp_output+0x38>
801906e: 4b6e ldr r3, [pc, #440] ; (8019228 <etharp_output+0x1e4>)
8019070: f240 321f movw r2, #799 ; 0x31f
8019074: 496f ldr r1, [pc, #444] ; (8019234 <etharp_output+0x1f0>)
8019076: 486e ldr r0, [pc, #440] ; (8019230 <etharp_output+0x1ec>)
8019078: f001 ffcc bl 801b014 <iprintf>
LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
801907c: 687b ldr r3, [r7, #4]
801907e: 2b00 cmp r3, #0
8019080: d106 bne.n 8019090 <etharp_output+0x4c>
8019082: 4b69 ldr r3, [pc, #420] ; (8019228 <etharp_output+0x1e4>)
8019084: f44f 7248 mov.w r2, #800 ; 0x320
8019088: 496b ldr r1, [pc, #428] ; (8019238 <etharp_output+0x1f4>)
801908a: 4869 ldr r0, [pc, #420] ; (8019230 <etharp_output+0x1ec>)
801908c: f001 ffc2 bl 801b014 <iprintf>
/* Determine on destination hardware address. Broadcasts and multicasts
* are special, other IP addresses are looked up in the ARP table. */
/* broadcast destination IP address? */
if (ip4_addr_isbroadcast(ipaddr, netif)) {
8019090: 687b ldr r3, [r7, #4]
8019092: 681b ldr r3, [r3, #0]
8019094: 68f9 ldr r1, [r7, #12]
8019096: 4618 mov r0, r3
8019098: f000 ff14 bl 8019ec4 <ip4_addr_isbroadcast_u32>
801909c: 4603 mov r3, r0
801909e: 2b00 cmp r3, #0
80190a0: d002 beq.n 80190a8 <etharp_output+0x64>
/* broadcast on Ethernet also */
dest = (const struct eth_addr *)&ethbroadcast;
80190a2: 4b66 ldr r3, [pc, #408] ; (801923c <etharp_output+0x1f8>)
80190a4: 61fb str r3, [r7, #28]
80190a6: e0af b.n 8019208 <etharp_output+0x1c4>
/* multicast destination IP address? */
} else if (ip4_addr_ismulticast(ipaddr)) {
80190a8: 687b ldr r3, [r7, #4]
80190aa: 681b ldr r3, [r3, #0]
80190ac: f003 03f0 and.w r3, r3, #240 ; 0xf0
80190b0: 2be0 cmp r3, #224 ; 0xe0
80190b2: d118 bne.n 80190e6 <etharp_output+0xa2>
/* Hash IP multicast address to MAC address.*/
mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
80190b4: 2301 movs r3, #1
80190b6: 743b strb r3, [r7, #16]
mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
80190b8: 2300 movs r3, #0
80190ba: 747b strb r3, [r7, #17]
mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
80190bc: 235e movs r3, #94 ; 0x5e
80190be: 74bb strb r3, [r7, #18]
mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
80190c0: 687b ldr r3, [r7, #4]
80190c2: 3301 adds r3, #1
80190c4: 781b ldrb r3, [r3, #0]
80190c6: f003 037f and.w r3, r3, #127 ; 0x7f
80190ca: b2db uxtb r3, r3
80190cc: 74fb strb r3, [r7, #19]
mcastaddr.addr[4] = ip4_addr3(ipaddr);
80190ce: 687b ldr r3, [r7, #4]
80190d0: 3302 adds r3, #2
80190d2: 781b ldrb r3, [r3, #0]
80190d4: 753b strb r3, [r7, #20]
mcastaddr.addr[5] = ip4_addr4(ipaddr);
80190d6: 687b ldr r3, [r7, #4]
80190d8: 3303 adds r3, #3
80190da: 781b ldrb r3, [r3, #0]
80190dc: 757b strb r3, [r7, #21]
/* destination Ethernet address is multicast */
dest = &mcastaddr;
80190de: f107 0310 add.w r3, r7, #16
80190e2: 61fb str r3, [r7, #28]
80190e4: e090 b.n 8019208 <etharp_output+0x1c4>
/* unicast destination IP address? */
} else {
netif_addr_idx_t i;
/* outside local network? if so, this can neither be a global broadcast nor
a subnet broadcast. */
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
80190e6: 687b ldr r3, [r7, #4]
80190e8: 681a ldr r2, [r3, #0]
80190ea: 68fb ldr r3, [r7, #12]
80190ec: 3304 adds r3, #4
80190ee: 681b ldr r3, [r3, #0]
80190f0: 405a eors r2, r3
80190f2: 68fb ldr r3, [r7, #12]
80190f4: 3308 adds r3, #8
80190f6: 681b ldr r3, [r3, #0]
80190f8: 4013 ands r3, r2
80190fa: 2b00 cmp r3, #0
80190fc: d012 beq.n 8019124 <etharp_output+0xe0>
!ip4_addr_islinklocal(ipaddr)) {
80190fe: 687b ldr r3, [r7, #4]
8019100: 681b ldr r3, [r3, #0]
8019102: b29b uxth r3, r3
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
8019104: f64f 62a9 movw r2, #65193 ; 0xfea9
8019108: 4293 cmp r3, r2
801910a: d00b beq.n 8019124 <etharp_output+0xe0>
dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
if (dst_addr == NULL)
#endif /* LWIP_HOOK_ETHARP_GET_GW */
{
/* interface has default gateway? */
if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
801910c: 68fb ldr r3, [r7, #12]
801910e: 330c adds r3, #12
8019110: 681b ldr r3, [r3, #0]
8019112: 2b00 cmp r3, #0
8019114: d003 beq.n 801911e <etharp_output+0xda>
/* send to hardware address of default gateway IP address */
dst_addr = netif_ip4_gw(netif);
8019116: 68fb ldr r3, [r7, #12]
8019118: 330c adds r3, #12
801911a: 61bb str r3, [r7, #24]
801911c: e002 b.n 8019124 <etharp_output+0xe0>
/* no default gateway available */
} else {
/* no route to destination error (default gateway missing) */
return ERR_RTE;
801911e: f06f 0303 mvn.w r3, #3
8019122: e07d b.n 8019220 <etharp_output+0x1dc>
if (netif->hints != NULL) {
/* per-pcb cached entry was given */
netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
if (etharp_cached_entry < ARP_TABLE_SIZE) {
#endif /* LWIP_NETIF_HWADDRHINT */
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
8019124: 4b46 ldr r3, [pc, #280] ; (8019240 <etharp_output+0x1fc>)
8019126: 781b ldrb r3, [r3, #0]
8019128: 4619 mov r1, r3
801912a: 4a46 ldr r2, [pc, #280] ; (8019244 <etharp_output+0x200>)
801912c: 460b mov r3, r1
801912e: 005b lsls r3, r3, #1
8019130: 440b add r3, r1
8019132: 00db lsls r3, r3, #3
8019134: 4413 add r3, r2
8019136: 3314 adds r3, #20
8019138: 781b ldrb r3, [r3, #0]
801913a: 2b01 cmp r3, #1
801913c: d925 bls.n 801918a <etharp_output+0x146>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[etharp_cached_entry].netif == netif) &&
801913e: 4b40 ldr r3, [pc, #256] ; (8019240 <etharp_output+0x1fc>)
8019140: 781b ldrb r3, [r3, #0]
8019142: 4619 mov r1, r3
8019144: 4a3f ldr r2, [pc, #252] ; (8019244 <etharp_output+0x200>)
8019146: 460b mov r3, r1
8019148: 005b lsls r3, r3, #1
801914a: 440b add r3, r1
801914c: 00db lsls r3, r3, #3
801914e: 4413 add r3, r2
8019150: 3308 adds r3, #8
8019152: 681b ldr r3, [r3, #0]
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
8019154: 68fa ldr r2, [r7, #12]
8019156: 429a cmp r2, r3
8019158: d117 bne.n 801918a <etharp_output+0x146>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
801915a: 69bb ldr r3, [r7, #24]
801915c: 681a ldr r2, [r3, #0]
801915e: 4b38 ldr r3, [pc, #224] ; (8019240 <etharp_output+0x1fc>)
8019160: 781b ldrb r3, [r3, #0]
8019162: 4618 mov r0, r3
8019164: 4937 ldr r1, [pc, #220] ; (8019244 <etharp_output+0x200>)
8019166: 4603 mov r3, r0
8019168: 005b lsls r3, r3, #1
801916a: 4403 add r3, r0
801916c: 00db lsls r3, r3, #3
801916e: 440b add r3, r1
8019170: 3304 adds r3, #4
8019172: 681b ldr r3, [r3, #0]
(arp_table[etharp_cached_entry].netif == netif) &&
8019174: 429a cmp r2, r3
8019176: d108 bne.n 801918a <etharp_output+0x146>
/* the per-pcb-cached entry is stable and the right one! */
ETHARP_STATS_INC(etharp.cachehit);
return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
8019178: 4b31 ldr r3, [pc, #196] ; (8019240 <etharp_output+0x1fc>)
801917a: 781b ldrb r3, [r3, #0]
801917c: 461a mov r2, r3
801917e: 68b9 ldr r1, [r7, #8]
8019180: 68f8 ldr r0, [r7, #12]
8019182: f7ff fec5 bl 8018f10 <etharp_output_to_arp_index>
8019186: 4603 mov r3, r0
8019188: e04a b.n 8019220 <etharp_output+0x1dc>
}
#endif /* LWIP_NETIF_HWADDRHINT */
/* find stable entry: do this here since this is a critical path for
throughput and etharp_find_entry() is kind of slow */
for (i = 0; i < ARP_TABLE_SIZE; i++) {
801918a: 2300 movs r3, #0
801918c: 75fb strb r3, [r7, #23]
801918e: e031 b.n 80191f4 <etharp_output+0x1b0>
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
8019190: 7dfa ldrb r2, [r7, #23]
8019192: 492c ldr r1, [pc, #176] ; (8019244 <etharp_output+0x200>)
8019194: 4613 mov r3, r2
8019196: 005b lsls r3, r3, #1
8019198: 4413 add r3, r2
801919a: 00db lsls r3, r3, #3
801919c: 440b add r3, r1
801919e: 3314 adds r3, #20
80191a0: 781b ldrb r3, [r3, #0]
80191a2: 2b01 cmp r3, #1
80191a4: d923 bls.n 80191ee <etharp_output+0x1aa>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[i].netif == netif) &&
80191a6: 7dfa ldrb r2, [r7, #23]
80191a8: 4926 ldr r1, [pc, #152] ; (8019244 <etharp_output+0x200>)
80191aa: 4613 mov r3, r2
80191ac: 005b lsls r3, r3, #1
80191ae: 4413 add r3, r2
80191b0: 00db lsls r3, r3, #3
80191b2: 440b add r3, r1
80191b4: 3308 adds r3, #8
80191b6: 681b ldr r3, [r3, #0]
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
80191b8: 68fa ldr r2, [r7, #12]
80191ba: 429a cmp r2, r3
80191bc: d117 bne.n 80191ee <etharp_output+0x1aa>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
80191be: 69bb ldr r3, [r7, #24]
80191c0: 6819 ldr r1, [r3, #0]
80191c2: 7dfa ldrb r2, [r7, #23]
80191c4: 481f ldr r0, [pc, #124] ; (8019244 <etharp_output+0x200>)
80191c6: 4613 mov r3, r2
80191c8: 005b lsls r3, r3, #1
80191ca: 4413 add r3, r2
80191cc: 00db lsls r3, r3, #3
80191ce: 4403 add r3, r0
80191d0: 3304 adds r3, #4
80191d2: 681b ldr r3, [r3, #0]
(arp_table[i].netif == netif) &&
80191d4: 4299 cmp r1, r3
80191d6: d10a bne.n 80191ee <etharp_output+0x1aa>
/* found an existing, stable entry */
ETHARP_SET_ADDRHINT(netif, i);
80191d8: 4a19 ldr r2, [pc, #100] ; (8019240 <etharp_output+0x1fc>)
80191da: 7dfb ldrb r3, [r7, #23]
80191dc: 7013 strb r3, [r2, #0]
return etharp_output_to_arp_index(netif, q, i);
80191de: 7dfb ldrb r3, [r7, #23]
80191e0: 461a mov r2, r3
80191e2: 68b9 ldr r1, [r7, #8]
80191e4: 68f8 ldr r0, [r7, #12]
80191e6: f7ff fe93 bl 8018f10 <etharp_output_to_arp_index>
80191ea: 4603 mov r3, r0
80191ec: e018 b.n 8019220 <etharp_output+0x1dc>
for (i = 0; i < ARP_TABLE_SIZE; i++) {
80191ee: 7dfb ldrb r3, [r7, #23]
80191f0: 3301 adds r3, #1
80191f2: 75fb strb r3, [r7, #23]
80191f4: 7dfb ldrb r3, [r7, #23]
80191f6: 2b09 cmp r3, #9
80191f8: d9ca bls.n 8019190 <etharp_output+0x14c>
}
}
/* no stable entry found, use the (slower) query function:
queue on destination Ethernet address belonging to ipaddr */
return etharp_query(netif, dst_addr, q);
80191fa: 68ba ldr r2, [r7, #8]
80191fc: 69b9 ldr r1, [r7, #24]
80191fe: 68f8 ldr r0, [r7, #12]
8019200: f000 f822 bl 8019248 <etharp_query>
8019204: 4603 mov r3, r0
8019206: e00b b.n 8019220 <etharp_output+0x1dc>
}
/* continuation for multicast/broadcast destinations */
/* obtain source Ethernet address of the given interface */
/* send packet directly on the link */
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
8019208: 68fb ldr r3, [r7, #12]
801920a: f103 022a add.w r2, r3, #42 ; 0x2a
801920e: f44f 6300 mov.w r3, #2048 ; 0x800
8019212: 9300 str r3, [sp, #0]
8019214: 69fb ldr r3, [r7, #28]
8019216: 68b9 ldr r1, [r7, #8]
8019218: 68f8 ldr r0, [r7, #12]
801921a: f001 fd57 bl 801accc <ethernet_output>
801921e: 4603 mov r3, r0
}
8019220: 4618 mov r0, r3
8019222: 3720 adds r7, #32
8019224: 46bd mov sp, r7
8019226: bd80 pop {r7, pc}
8019228: 0801e738 .word 0x0801e738
801922c: 0801e888 .word 0x0801e888
8019230: 0801e7b0 .word 0x0801e7b0
8019234: 0801e8d8 .word 0x0801e8d8
8019238: 0801e878 .word 0x0801e878
801923c: 08020e70 .word 0x08020e70
8019240: 20008868 .word 0x20008868
8019244: 20008778 .word 0x20008778
08019248 <etharp_query>:
* - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
*
*/
err_t
etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
{
8019248: b580 push {r7, lr}
801924a: b08c sub sp, #48 ; 0x30
801924c: af02 add r7, sp, #8
801924e: 60f8 str r0, [r7, #12]
8019250: 60b9 str r1, [r7, #8]
8019252: 607a str r2, [r7, #4]
struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
8019254: 68fb ldr r3, [r7, #12]
8019256: 332a adds r3, #42 ; 0x2a
8019258: 617b str r3, [r7, #20]
err_t result = ERR_MEM;
801925a: 23ff movs r3, #255 ; 0xff
801925c: f887 3027 strb.w r3, [r7, #39] ; 0x27
int is_new_entry = 0;
8019260: 2300 movs r3, #0
8019262: 623b str r3, [r7, #32]
s16_t i_err;
netif_addr_idx_t i;
/* non-unicast address? */
if (ip4_addr_isbroadcast(ipaddr, netif) ||
8019264: 68bb ldr r3, [r7, #8]
8019266: 681b ldr r3, [r3, #0]
8019268: 68f9 ldr r1, [r7, #12]
801926a: 4618 mov r0, r3
801926c: f000 fe2a bl 8019ec4 <ip4_addr_isbroadcast_u32>
8019270: 4603 mov r3, r0
8019272: 2b00 cmp r3, #0
8019274: d10c bne.n 8019290 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019276: 68bb ldr r3, [r7, #8]
8019278: 681b ldr r3, [r3, #0]
801927a: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isbroadcast(ipaddr, netif) ||
801927e: 2be0 cmp r3, #224 ; 0xe0
8019280: d006 beq.n 8019290 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019282: 68bb ldr r3, [r7, #8]
8019284: 2b00 cmp r3, #0
8019286: d003 beq.n 8019290 <etharp_query+0x48>
ip4_addr_isany(ipaddr)) {
8019288: 68bb ldr r3, [r7, #8]
801928a: 681b ldr r3, [r3, #0]
801928c: 2b00 cmp r3, #0
801928e: d102 bne.n 8019296 <etharp_query+0x4e>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
8019290: f06f 030f mvn.w r3, #15
8019294: e102 b.n 801949c <etharp_query+0x254>
}
/* find entry in ARP cache, ask to create entry if queueing packet */
i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
8019296: 68fa ldr r2, [r7, #12]
8019298: 2101 movs r1, #1
801929a: 68b8 ldr r0, [r7, #8]
801929c: f7ff fb5c bl 8018958 <etharp_find_entry>
80192a0: 4603 mov r3, r0
80192a2: 827b strh r3, [r7, #18]
/* could not find or create entry? */
if (i_err < 0) {
80192a4: f9b7 3012 ldrsh.w r3, [r7, #18]
80192a8: 2b00 cmp r3, #0
80192aa: da02 bge.n 80192b2 <etharp_query+0x6a>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
if (q) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
ETHARP_STATS_INC(etharp.memerr);
}
return (err_t)i_err;
80192ac: 8a7b ldrh r3, [r7, #18]
80192ae: b25b sxtb r3, r3
80192b0: e0f4 b.n 801949c <etharp_query+0x254>
}
LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
80192b2: 8a7b ldrh r3, [r7, #18]
80192b4: 2b7e cmp r3, #126 ; 0x7e
80192b6: d906 bls.n 80192c6 <etharp_query+0x7e>
80192b8: 4b7a ldr r3, [pc, #488] ; (80194a4 <etharp_query+0x25c>)
80192ba: f240 32c1 movw r2, #961 ; 0x3c1
80192be: 497a ldr r1, [pc, #488] ; (80194a8 <etharp_query+0x260>)
80192c0: 487a ldr r0, [pc, #488] ; (80194ac <etharp_query+0x264>)
80192c2: f001 fea7 bl 801b014 <iprintf>
i = (netif_addr_idx_t)i_err;
80192c6: 8a7b ldrh r3, [r7, #18]
80192c8: 747b strb r3, [r7, #17]
/* mark a fresh entry as pending (we just sent a request) */
if (arp_table[i].state == ETHARP_STATE_EMPTY) {
80192ca: 7c7a ldrb r2, [r7, #17]
80192cc: 4978 ldr r1, [pc, #480] ; (80194b0 <etharp_query+0x268>)
80192ce: 4613 mov r3, r2
80192d0: 005b lsls r3, r3, #1
80192d2: 4413 add r3, r2
80192d4: 00db lsls r3, r3, #3
80192d6: 440b add r3, r1
80192d8: 3314 adds r3, #20
80192da: 781b ldrb r3, [r3, #0]
80192dc: 2b00 cmp r3, #0
80192de: d115 bne.n 801930c <etharp_query+0xc4>
is_new_entry = 1;
80192e0: 2301 movs r3, #1
80192e2: 623b str r3, [r7, #32]
arp_table[i].state = ETHARP_STATE_PENDING;
80192e4: 7c7a ldrb r2, [r7, #17]
80192e6: 4972 ldr r1, [pc, #456] ; (80194b0 <etharp_query+0x268>)
80192e8: 4613 mov r3, r2
80192ea: 005b lsls r3, r3, #1
80192ec: 4413 add r3, r2
80192ee: 00db lsls r3, r3, #3
80192f0: 440b add r3, r1
80192f2: 3314 adds r3, #20
80192f4: 2201 movs r2, #1
80192f6: 701a strb r2, [r3, #0]
/* record network interface for re-sending arp request in etharp_tmr */
arp_table[i].netif = netif;
80192f8: 7c7a ldrb r2, [r7, #17]
80192fa: 496d ldr r1, [pc, #436] ; (80194b0 <etharp_query+0x268>)
80192fc: 4613 mov r3, r2
80192fe: 005b lsls r3, r3, #1
8019300: 4413 add r3, r2
8019302: 00db lsls r3, r3, #3
8019304: 440b add r3, r1
8019306: 3308 adds r3, #8
8019308: 68fa ldr r2, [r7, #12]
801930a: 601a str r2, [r3, #0]
}
/* { i is either a STABLE or (new or existing) PENDING entry } */
LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
801930c: 7c7a ldrb r2, [r7, #17]
801930e: 4968 ldr r1, [pc, #416] ; (80194b0 <etharp_query+0x268>)
8019310: 4613 mov r3, r2
8019312: 005b lsls r3, r3, #1
8019314: 4413 add r3, r2
8019316: 00db lsls r3, r3, #3
8019318: 440b add r3, r1
801931a: 3314 adds r3, #20
801931c: 781b ldrb r3, [r3, #0]
801931e: 2b01 cmp r3, #1
8019320: d011 beq.n 8019346 <etharp_query+0xfe>
8019322: 7c7a ldrb r2, [r7, #17]
8019324: 4962 ldr r1, [pc, #392] ; (80194b0 <etharp_query+0x268>)
8019326: 4613 mov r3, r2
8019328: 005b lsls r3, r3, #1
801932a: 4413 add r3, r2
801932c: 00db lsls r3, r3, #3
801932e: 440b add r3, r1
8019330: 3314 adds r3, #20
8019332: 781b ldrb r3, [r3, #0]
8019334: 2b01 cmp r3, #1
8019336: d806 bhi.n 8019346 <etharp_query+0xfe>
8019338: 4b5a ldr r3, [pc, #360] ; (80194a4 <etharp_query+0x25c>)
801933a: f240 32cf movw r2, #975 ; 0x3cf
801933e: 495d ldr r1, [pc, #372] ; (80194b4 <etharp_query+0x26c>)
8019340: 485a ldr r0, [pc, #360] ; (80194ac <etharp_query+0x264>)
8019342: f001 fe67 bl 801b014 <iprintf>
((arp_table[i].state == ETHARP_STATE_PENDING) ||
(arp_table[i].state >= ETHARP_STATE_STABLE)));
/* do we have a new entry? or an implicit query request? */
if (is_new_entry || (q == NULL)) {
8019346: 6a3b ldr r3, [r7, #32]
8019348: 2b00 cmp r3, #0
801934a: d102 bne.n 8019352 <etharp_query+0x10a>
801934c: 687b ldr r3, [r7, #4]
801934e: 2b00 cmp r3, #0
8019350: d10c bne.n 801936c <etharp_query+0x124>
/* try to resolve it; send out ARP request */
result = etharp_request(netif, ipaddr);
8019352: 68b9 ldr r1, [r7, #8]
8019354: 68f8 ldr r0, [r7, #12]
8019356: f000 f963 bl 8019620 <etharp_request>
801935a: 4603 mov r3, r0
801935c: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* ARP request couldn't be sent */
/* We don't re-send arp request in etharp_tmr, but we still queue packets,
since this failure could be temporary, and the next packet calling
etharp_query again could lead to sending the queued packets. */
}
if (q == NULL) {
8019360: 687b ldr r3, [r7, #4]
8019362: 2b00 cmp r3, #0
8019364: d102 bne.n 801936c <etharp_query+0x124>
return result;
8019366: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
801936a: e097 b.n 801949c <etharp_query+0x254>
}
}
/* packet given? */
LWIP_ASSERT("q != NULL", q != NULL);
801936c: 687b ldr r3, [r7, #4]
801936e: 2b00 cmp r3, #0
8019370: d106 bne.n 8019380 <etharp_query+0x138>
8019372: 4b4c ldr r3, [pc, #304] ; (80194a4 <etharp_query+0x25c>)
8019374: f240 32e1 movw r2, #993 ; 0x3e1
8019378: 494f ldr r1, [pc, #316] ; (80194b8 <etharp_query+0x270>)
801937a: 484c ldr r0, [pc, #304] ; (80194ac <etharp_query+0x264>)
801937c: f001 fe4a bl 801b014 <iprintf>
/* stable entry? */
if (arp_table[i].state >= ETHARP_STATE_STABLE) {
8019380: 7c7a ldrb r2, [r7, #17]
8019382: 494b ldr r1, [pc, #300] ; (80194b0 <etharp_query+0x268>)
8019384: 4613 mov r3, r2
8019386: 005b lsls r3, r3, #1
8019388: 4413 add r3, r2
801938a: 00db lsls r3, r3, #3
801938c: 440b add r3, r1
801938e: 3314 adds r3, #20
8019390: 781b ldrb r3, [r3, #0]
8019392: 2b01 cmp r3, #1
8019394: d918 bls.n 80193c8 <etharp_query+0x180>
/* we have a valid IP->Ethernet address mapping */
ETHARP_SET_ADDRHINT(netif, i);
8019396: 4a49 ldr r2, [pc, #292] ; (80194bc <etharp_query+0x274>)
8019398: 7c7b ldrb r3, [r7, #17]
801939a: 7013 strb r3, [r2, #0]
/* send the packet */
result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
801939c: 7c7a ldrb r2, [r7, #17]
801939e: 4613 mov r3, r2
80193a0: 005b lsls r3, r3, #1
80193a2: 4413 add r3, r2
80193a4: 00db lsls r3, r3, #3
80193a6: 3308 adds r3, #8
80193a8: 4a41 ldr r2, [pc, #260] ; (80194b0 <etharp_query+0x268>)
80193aa: 4413 add r3, r2
80193ac: 1d1a adds r2, r3, #4
80193ae: f44f 6300 mov.w r3, #2048 ; 0x800
80193b2: 9300 str r3, [sp, #0]
80193b4: 4613 mov r3, r2
80193b6: 697a ldr r2, [r7, #20]
80193b8: 6879 ldr r1, [r7, #4]
80193ba: 68f8 ldr r0, [r7, #12]
80193bc: f001 fc86 bl 801accc <ethernet_output>
80193c0: 4603 mov r3, r0
80193c2: f887 3027 strb.w r3, [r7, #39] ; 0x27
80193c6: e067 b.n 8019498 <etharp_query+0x250>
/* pending entry? (either just created or already pending */
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
80193c8: 7c7a ldrb r2, [r7, #17]
80193ca: 4939 ldr r1, [pc, #228] ; (80194b0 <etharp_query+0x268>)
80193cc: 4613 mov r3, r2
80193ce: 005b lsls r3, r3, #1
80193d0: 4413 add r3, r2
80193d2: 00db lsls r3, r3, #3
80193d4: 440b add r3, r1
80193d6: 3314 adds r3, #20
80193d8: 781b ldrb r3, [r3, #0]
80193da: 2b01 cmp r3, #1
80193dc: d15c bne.n 8019498 <etharp_query+0x250>
/* entry is still pending, queue the given packet 'q' */
struct pbuf *p;
int copy_needed = 0;
80193de: 2300 movs r3, #0
80193e0: 61bb str r3, [r7, #24]
/* IF q includes a pbuf that must be copied, copy the whole chain into a
* new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
p = q;
80193e2: 687b ldr r3, [r7, #4]
80193e4: 61fb str r3, [r7, #28]
while (p) {
80193e6: e01c b.n 8019422 <etharp_query+0x1da>
LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
80193e8: 69fb ldr r3, [r7, #28]
80193ea: 895a ldrh r2, [r3, #10]
80193ec: 69fb ldr r3, [r7, #28]
80193ee: 891b ldrh r3, [r3, #8]
80193f0: 429a cmp r2, r3
80193f2: d10a bne.n 801940a <etharp_query+0x1c2>
80193f4: 69fb ldr r3, [r7, #28]
80193f6: 681b ldr r3, [r3, #0]
80193f8: 2b00 cmp r3, #0
80193fa: d006 beq.n 801940a <etharp_query+0x1c2>
80193fc: 4b29 ldr r3, [pc, #164] ; (80194a4 <etharp_query+0x25c>)
80193fe: f240 32f1 movw r2, #1009 ; 0x3f1
8019402: 492f ldr r1, [pc, #188] ; (80194c0 <etharp_query+0x278>)
8019404: 4829 ldr r0, [pc, #164] ; (80194ac <etharp_query+0x264>)
8019406: f001 fe05 bl 801b014 <iprintf>
if (PBUF_NEEDS_COPY(p)) {
801940a: 69fb ldr r3, [r7, #28]
801940c: 7b1b ldrb r3, [r3, #12]
801940e: f003 0340 and.w r3, r3, #64 ; 0x40
8019412: 2b00 cmp r3, #0
8019414: d002 beq.n 801941c <etharp_query+0x1d4>
copy_needed = 1;
8019416: 2301 movs r3, #1
8019418: 61bb str r3, [r7, #24]
break;
801941a: e005 b.n 8019428 <etharp_query+0x1e0>
}
p = p->next;
801941c: 69fb ldr r3, [r7, #28]
801941e: 681b ldr r3, [r3, #0]
8019420: 61fb str r3, [r7, #28]
while (p) {
8019422: 69fb ldr r3, [r7, #28]
8019424: 2b00 cmp r3, #0
8019426: d1df bne.n 80193e8 <etharp_query+0x1a0>
}
if (copy_needed) {
8019428: 69bb ldr r3, [r7, #24]
801942a: 2b00 cmp r3, #0
801942c: d007 beq.n 801943e <etharp_query+0x1f6>
/* copy the whole packet into new pbufs */
p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
801942e: 687a ldr r2, [r7, #4]
8019430: f44f 7120 mov.w r1, #640 ; 0x280
8019434: 200e movs r0, #14
8019436: f7f7 fb4f bl 8010ad8 <pbuf_clone>
801943a: 61f8 str r0, [r7, #28]
801943c: e004 b.n 8019448 <etharp_query+0x200>
} else {
/* referencing the old pbuf is enough */
p = q;
801943e: 687b ldr r3, [r7, #4]
8019440: 61fb str r3, [r7, #28]
pbuf_ref(p);
8019442: 69f8 ldr r0, [r7, #28]
8019444: f7f7 f976 bl 8010734 <pbuf_ref>
}
/* packet could be taken over? */
if (p != NULL) {
8019448: 69fb ldr r3, [r7, #28]
801944a: 2b00 cmp r3, #0
801944c: d021 beq.n 8019492 <etharp_query+0x24a>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
}
#else /* ARP_QUEUEING */
/* always queue one packet per ARP request only, freeing a previously queued packet */
if (arp_table[i].q != NULL) {
801944e: 7c7a ldrb r2, [r7, #17]
8019450: 4917 ldr r1, [pc, #92] ; (80194b0 <etharp_query+0x268>)
8019452: 4613 mov r3, r2
8019454: 005b lsls r3, r3, #1
8019456: 4413 add r3, r2
8019458: 00db lsls r3, r3, #3
801945a: 440b add r3, r1
801945c: 681b ldr r3, [r3, #0]
801945e: 2b00 cmp r3, #0
8019460: d00a beq.n 8019478 <etharp_query+0x230>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
pbuf_free(arp_table[i].q);
8019462: 7c7a ldrb r2, [r7, #17]
8019464: 4912 ldr r1, [pc, #72] ; (80194b0 <etharp_query+0x268>)
8019466: 4613 mov r3, r2
8019468: 005b lsls r3, r3, #1
801946a: 4413 add r3, r2
801946c: 00db lsls r3, r3, #3
801946e: 440b add r3, r1
8019470: 681b ldr r3, [r3, #0]
8019472: 4618 mov r0, r3
8019474: f7f7 f8b8 bl 80105e8 <pbuf_free>
}
arp_table[i].q = p;
8019478: 7c7a ldrb r2, [r7, #17]
801947a: 490d ldr r1, [pc, #52] ; (80194b0 <etharp_query+0x268>)
801947c: 4613 mov r3, r2
801947e: 005b lsls r3, r3, #1
8019480: 4413 add r3, r2
8019482: 00db lsls r3, r3, #3
8019484: 440b add r3, r1
8019486: 69fa ldr r2, [r7, #28]
8019488: 601a str r2, [r3, #0]
result = ERR_OK;
801948a: 2300 movs r3, #0
801948c: f887 3027 strb.w r3, [r7, #39] ; 0x27
8019490: e002 b.n 8019498 <etharp_query+0x250>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
#endif /* ARP_QUEUEING */
} else {
ETHARP_STATS_INC(etharp.memerr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
8019492: 23ff movs r3, #255 ; 0xff
8019494: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
return result;
8019498: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
801949c: 4618 mov r0, r3
801949e: 3728 adds r7, #40 ; 0x28
80194a0: 46bd mov sp, r7
80194a2: bd80 pop {r7, pc}
80194a4: 0801e738 .word 0x0801e738
80194a8: 0801e8e4 .word 0x0801e8e4
80194ac: 0801e7b0 .word 0x0801e7b0
80194b0: 20008778 .word 0x20008778
80194b4: 0801e8f4 .word 0x0801e8f4
80194b8: 0801e8d8 .word 0x0801e8d8
80194bc: 20008868 .word 0x20008868
80194c0: 0801e91c .word 0x0801e91c
080194c4 <etharp_raw>:
etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
const struct eth_addr *ethdst_addr,
const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
const u16_t opcode)
{
80194c4: b580 push {r7, lr}
80194c6: b08a sub sp, #40 ; 0x28
80194c8: af02 add r7, sp, #8
80194ca: 60f8 str r0, [r7, #12]
80194cc: 60b9 str r1, [r7, #8]
80194ce: 607a str r2, [r7, #4]
80194d0: 603b str r3, [r7, #0]
struct pbuf *p;
err_t result = ERR_OK;
80194d2: 2300 movs r3, #0
80194d4: 77fb strb r3, [r7, #31]
struct etharp_hdr *hdr;
LWIP_ASSERT("netif != NULL", netif != NULL);
80194d6: 68fb ldr r3, [r7, #12]
80194d8: 2b00 cmp r3, #0
80194da: d106 bne.n 80194ea <etharp_raw+0x26>
80194dc: 4b3a ldr r3, [pc, #232] ; (80195c8 <etharp_raw+0x104>)
80194de: f240 4257 movw r2, #1111 ; 0x457
80194e2: 493a ldr r1, [pc, #232] ; (80195cc <etharp_raw+0x108>)
80194e4: 483a ldr r0, [pc, #232] ; (80195d0 <etharp_raw+0x10c>)
80194e6: f001 fd95 bl 801b014 <iprintf>
/* allocate a pbuf for the outgoing ARP request packet */
p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
80194ea: f44f 7220 mov.w r2, #640 ; 0x280
80194ee: 211c movs r1, #28
80194f0: 200e movs r0, #14
80194f2: f7f6 fd99 bl 8010028 <pbuf_alloc>
80194f6: 61b8 str r0, [r7, #24]
/* could allocate a pbuf for an ARP request? */
if (p == NULL) {
80194f8: 69bb ldr r3, [r7, #24]
80194fa: 2b00 cmp r3, #0
80194fc: d102 bne.n 8019504 <etharp_raw+0x40>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("etharp_raw: could not allocate pbuf for ARP request.\n"));
ETHARP_STATS_INC(etharp.memerr);
return ERR_MEM;
80194fe: f04f 33ff mov.w r3, #4294967295
8019502: e05d b.n 80195c0 <etharp_raw+0xfc>
}
LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
8019504: 69bb ldr r3, [r7, #24]
8019506: 895b ldrh r3, [r3, #10]
8019508: 2b1b cmp r3, #27
801950a: d806 bhi.n 801951a <etharp_raw+0x56>
801950c: 4b2e ldr r3, [pc, #184] ; (80195c8 <etharp_raw+0x104>)
801950e: f240 4263 movw r2, #1123 ; 0x463
8019512: 4930 ldr r1, [pc, #192] ; (80195d4 <etharp_raw+0x110>)
8019514: 482e ldr r0, [pc, #184] ; (80195d0 <etharp_raw+0x10c>)
8019516: f001 fd7d bl 801b014 <iprintf>
(p->len >= SIZEOF_ETHARP_HDR));
hdr = (struct etharp_hdr *)p->payload;
801951a: 69bb ldr r3, [r7, #24]
801951c: 685b ldr r3, [r3, #4]
801951e: 617b str r3, [r7, #20]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
hdr->opcode = lwip_htons(opcode);
8019520: 8ebb ldrh r3, [r7, #52] ; 0x34
8019522: 4618 mov r0, r3
8019524: f7f5 fcac bl 800ee80 <lwip_htons>
8019528: 4603 mov r3, r0
801952a: 461a mov r2, r3
801952c: 697b ldr r3, [r7, #20]
801952e: 80da strh r2, [r3, #6]
LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
8019530: 68fb ldr r3, [r7, #12]
8019532: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8019536: 2b06 cmp r3, #6
8019538: d006 beq.n 8019548 <etharp_raw+0x84>
801953a: 4b23 ldr r3, [pc, #140] ; (80195c8 <etharp_raw+0x104>)
801953c: f240 426a movw r2, #1130 ; 0x46a
8019540: 4925 ldr r1, [pc, #148] ; (80195d8 <etharp_raw+0x114>)
8019542: 4823 ldr r0, [pc, #140] ; (80195d0 <etharp_raw+0x10c>)
8019544: f001 fd66 bl 801b014 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
/* Write the ARP MAC-Addresses */
SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
8019548: 697b ldr r3, [r7, #20]
801954a: 3308 adds r3, #8
801954c: 2206 movs r2, #6
801954e: 6839 ldr r1, [r7, #0]
8019550: 4618 mov r0, r3
8019552: f001 fd4c bl 801afee <memcpy>
SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
8019556: 697b ldr r3, [r7, #20]
8019558: 3312 adds r3, #18
801955a: 2206 movs r2, #6
801955c: 6af9 ldr r1, [r7, #44] ; 0x2c
801955e: 4618 mov r0, r3
8019560: f001 fd45 bl 801afee <memcpy>
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing. */
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
8019564: 697b ldr r3, [r7, #20]
8019566: 330e adds r3, #14
8019568: 6aba ldr r2, [r7, #40] ; 0x28
801956a: 6812 ldr r2, [r2, #0]
801956c: 601a str r2, [r3, #0]
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
801956e: 697b ldr r3, [r7, #20]
8019570: 3318 adds r3, #24
8019572: 6b3a ldr r2, [r7, #48] ; 0x30
8019574: 6812 ldr r2, [r2, #0]
8019576: 601a str r2, [r3, #0]
hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
8019578: 697b ldr r3, [r7, #20]
801957a: 2200 movs r2, #0
801957c: 701a strb r2, [r3, #0]
801957e: 2200 movs r2, #0
8019580: f042 0201 orr.w r2, r2, #1
8019584: 705a strb r2, [r3, #1]
hdr->proto = PP_HTONS(ETHTYPE_IP);
8019586: 697b ldr r3, [r7, #20]
8019588: 2200 movs r2, #0
801958a: f042 0208 orr.w r2, r2, #8
801958e: 709a strb r2, [r3, #2]
8019590: 2200 movs r2, #0
8019592: 70da strb r2, [r3, #3]
/* set hwlen and protolen */
hdr->hwlen = ETH_HWADDR_LEN;
8019594: 697b ldr r3, [r7, #20]
8019596: 2206 movs r2, #6
8019598: 711a strb r2, [r3, #4]
hdr->protolen = sizeof(ip4_addr_t);
801959a: 697b ldr r3, [r7, #20]
801959c: 2204 movs r2, #4
801959e: 715a strb r2, [r3, #5]
if (ip4_addr_islinklocal(ipsrc_addr)) {
ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
} else
#endif /* LWIP_AUTOIP */
{
ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
80195a0: f640 0306 movw r3, #2054 ; 0x806
80195a4: 9300 str r3, [sp, #0]
80195a6: 687b ldr r3, [r7, #4]
80195a8: 68ba ldr r2, [r7, #8]
80195aa: 69b9 ldr r1, [r7, #24]
80195ac: 68f8 ldr r0, [r7, #12]
80195ae: f001 fb8d bl 801accc <ethernet_output>
}
ETHARP_STATS_INC(etharp.xmit);
/* free ARP query packet */
pbuf_free(p);
80195b2: 69b8 ldr r0, [r7, #24]
80195b4: f7f7 f818 bl 80105e8 <pbuf_free>
p = NULL;
80195b8: 2300 movs r3, #0
80195ba: 61bb str r3, [r7, #24]
/* could not allocate pbuf for ARP request */
return result;
80195bc: f997 301f ldrsb.w r3, [r7, #31]
}
80195c0: 4618 mov r0, r3
80195c2: 3720 adds r7, #32
80195c4: 46bd mov sp, r7
80195c6: bd80 pop {r7, pc}
80195c8: 0801e738 .word 0x0801e738
80195cc: 0801e888 .word 0x0801e888
80195d0: 0801e7b0 .word 0x0801e7b0
80195d4: 0801e938 .word 0x0801e938
80195d8: 0801e96c .word 0x0801e96c
080195dc <etharp_request_dst>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
static err_t
etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
{
80195dc: b580 push {r7, lr}
80195de: b088 sub sp, #32
80195e0: af04 add r7, sp, #16
80195e2: 60f8 str r0, [r7, #12]
80195e4: 60b9 str r1, [r7, #8]
80195e6: 607a str r2, [r7, #4]
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
80195e8: 68fb ldr r3, [r7, #12]
80195ea: f103 012a add.w r1, r3, #42 ; 0x2a
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
80195ee: 68fb ldr r3, [r7, #12]
80195f0: f103 002a add.w r0, r3, #42 ; 0x2a
80195f4: 68fb ldr r3, [r7, #12]
80195f6: 3304 adds r3, #4
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
80195f8: 2201 movs r2, #1
80195fa: 9203 str r2, [sp, #12]
80195fc: 68ba ldr r2, [r7, #8]
80195fe: 9202 str r2, [sp, #8]
8019600: 4a06 ldr r2, [pc, #24] ; (801961c <etharp_request_dst+0x40>)
8019602: 9201 str r2, [sp, #4]
8019604: 9300 str r3, [sp, #0]
8019606: 4603 mov r3, r0
8019608: 687a ldr r2, [r7, #4]
801960a: 68f8 ldr r0, [r7, #12]
801960c: f7ff ff5a bl 80194c4 <etharp_raw>
8019610: 4603 mov r3, r0
ipaddr, ARP_REQUEST);
}
8019612: 4618 mov r0, r3
8019614: 3710 adds r7, #16
8019616: 46bd mov sp, r7
8019618: bd80 pop {r7, pc}
801961a: bf00 nop
801961c: 08020e78 .word 0x08020e78
08019620 <etharp_request>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
err_t
etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
{
8019620: b580 push {r7, lr}
8019622: b082 sub sp, #8
8019624: af00 add r7, sp, #0
8019626: 6078 str r0, [r7, #4]
8019628: 6039 str r1, [r7, #0]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
return etharp_request_dst(netif, ipaddr, &ethbroadcast);
801962a: 4a05 ldr r2, [pc, #20] ; (8019640 <etharp_request+0x20>)
801962c: 6839 ldr r1, [r7, #0]
801962e: 6878 ldr r0, [r7, #4]
8019630: f7ff ffd4 bl 80195dc <etharp_request_dst>
8019634: 4603 mov r3, r0
}
8019636: 4618 mov r0, r3
8019638: 3708 adds r7, #8
801963a: 46bd mov sp, r7
801963c: bd80 pop {r7, pc}
801963e: bf00 nop
8019640: 08020e70 .word 0x08020e70
08019644 <icmp_input>:
* @param p the icmp echo request packet, p->payload pointing to the icmp header
* @param inp the netif on which this packet was received
*/
void
icmp_input(struct pbuf *p, struct netif *inp)
{
8019644: b580 push {r7, lr}
8019646: b08e sub sp, #56 ; 0x38
8019648: af04 add r7, sp, #16
801964a: 6078 str r0, [r7, #4]
801964c: 6039 str r1, [r7, #0]
const ip4_addr_t *src;
ICMP_STATS_INC(icmp.recv);
MIB2_STATS_INC(mib2.icmpinmsgs);
iphdr_in = ip4_current_header();
801964e: 4b79 ldr r3, [pc, #484] ; (8019834 <icmp_input+0x1f0>)
8019650: 689b ldr r3, [r3, #8]
8019652: 627b str r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(iphdr_in);
8019654: 6a7b ldr r3, [r7, #36] ; 0x24
8019656: 781b ldrb r3, [r3, #0]
8019658: f003 030f and.w r3, r3, #15
801965c: b2db uxtb r3, r3
801965e: 009b lsls r3, r3, #2
8019660: b2db uxtb r3, r3
8019662: 847b strh r3, [r7, #34] ; 0x22
if (hlen < IP_HLEN) {
8019664: 8c7b ldrh r3, [r7, #34] ; 0x22
8019666: 2b13 cmp r3, #19
8019668: f240 80cd bls.w 8019806 <icmp_input+0x1c2>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
goto lenerr;
}
if (p->len < sizeof(u16_t) * 2) {
801966c: 687b ldr r3, [r7, #4]
801966e: 895b ldrh r3, [r3, #10]
8019670: 2b03 cmp r3, #3
8019672: f240 80ca bls.w 801980a <icmp_input+0x1c6>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
goto lenerr;
}
type = *((u8_t *)p->payload);
8019676: 687b ldr r3, [r7, #4]
8019678: 685b ldr r3, [r3, #4]
801967a: 781b ldrb r3, [r3, #0]
801967c: f887 3021 strb.w r3, [r7, #33] ; 0x21
#ifdef LWIP_DEBUG
code = *(((u8_t *)p->payload) + 1);
/* if debug is enabled but debug statement below is somehow disabled: */
LWIP_UNUSED_ARG(code);
#endif /* LWIP_DEBUG */
switch (type) {
8019680: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
8019684: 2b00 cmp r3, #0
8019686: f000 80b7 beq.w 80197f8 <icmp_input+0x1b4>
801968a: 2b08 cmp r3, #8
801968c: f040 80b7 bne.w 80197fe <icmp_input+0x1ba>
(as obviously, an echo request has been sent, too). */
MIB2_STATS_INC(mib2.icmpinechoreps);
break;
case ICMP_ECHO:
MIB2_STATS_INC(mib2.icmpinechos);
src = ip4_current_dest_addr();
8019690: 4b69 ldr r3, [pc, #420] ; (8019838 <icmp_input+0x1f4>)
8019692: 61fb str r3, [r7, #28]
/* multicast destination address? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019694: 4b67 ldr r3, [pc, #412] ; (8019834 <icmp_input+0x1f0>)
8019696: 695b ldr r3, [r3, #20]
8019698: f003 03f0 and.w r3, r3, #240 ; 0xf0
801969c: 2be0 cmp r3, #224 ; 0xe0
801969e: f000 80bb beq.w 8019818 <icmp_input+0x1d4>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
goto icmperr;
#endif /* LWIP_MULTICAST_PING */
}
/* broadcast destination address? */
if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
80196a2: 4b64 ldr r3, [pc, #400] ; (8019834 <icmp_input+0x1f0>)
80196a4: 695a ldr r2, [r3, #20]
80196a6: 4b63 ldr r3, [pc, #396] ; (8019834 <icmp_input+0x1f0>)
80196a8: 681b ldr r3, [r3, #0]
80196aa: 4619 mov r1, r3
80196ac: 4610 mov r0, r2
80196ae: f000 fc09 bl 8019ec4 <ip4_addr_isbroadcast_u32>
80196b2: 4603 mov r3, r0
80196b4: 2b00 cmp r3, #0
80196b6: f040 80b1 bne.w 801981c <icmp_input+0x1d8>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
goto icmperr;
#endif /* LWIP_BROADCAST_PING */
}
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
80196ba: 687b ldr r3, [r7, #4]
80196bc: 891b ldrh r3, [r3, #8]
80196be: 2b07 cmp r3, #7
80196c0: f240 80a5 bls.w 801980e <icmp_input+0x1ca>
return;
}
}
#endif
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
80196c4: 8c7b ldrh r3, [r7, #34] ; 0x22
80196c6: 330e adds r3, #14
80196c8: 4619 mov r1, r3
80196ca: 6878 ldr r0, [r7, #4]
80196cc: f7f6 fef6 bl 80104bc <pbuf_add_header>
80196d0: 4603 mov r3, r0
80196d2: 2b00 cmp r3, #0
80196d4: d04b beq.n 801976e <icmp_input+0x12a>
/* p is not big enough to contain link headers
* allocate a new one and copy p into it
*/
struct pbuf *r;
u16_t alloc_len = (u16_t)(p->tot_len + hlen);
80196d6: 687b ldr r3, [r7, #4]
80196d8: 891a ldrh r2, [r3, #8]
80196da: 8c7b ldrh r3, [r7, #34] ; 0x22
80196dc: 4413 add r3, r2
80196de: 837b strh r3, [r7, #26]
if (alloc_len < p->tot_len) {
80196e0: 687b ldr r3, [r7, #4]
80196e2: 891b ldrh r3, [r3, #8]
80196e4: 8b7a ldrh r2, [r7, #26]
80196e6: 429a cmp r2, r3
80196e8: f0c0 809a bcc.w 8019820 <icmp_input+0x1dc>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
goto icmperr;
}
/* allocate new packet buffer with space for link headers */
r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
80196ec: 8b7b ldrh r3, [r7, #26]
80196ee: f44f 7220 mov.w r2, #640 ; 0x280
80196f2: 4619 mov r1, r3
80196f4: 200e movs r0, #14
80196f6: f7f6 fc97 bl 8010028 <pbuf_alloc>
80196fa: 6178 str r0, [r7, #20]
if (r == NULL) {
80196fc: 697b ldr r3, [r7, #20]
80196fe: 2b00 cmp r3, #0
8019700: f000 8090 beq.w 8019824 <icmp_input+0x1e0>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
goto icmperr;
}
if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
8019704: 697b ldr r3, [r7, #20]
8019706: 895b ldrh r3, [r3, #10]
8019708: 461a mov r2, r3
801970a: 8c7b ldrh r3, [r7, #34] ; 0x22
801970c: 3308 adds r3, #8
801970e: 429a cmp r2, r3
8019710: d203 bcs.n 801971a <icmp_input+0xd6>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
pbuf_free(r);
8019712: 6978 ldr r0, [r7, #20]
8019714: f7f6 ff68 bl 80105e8 <pbuf_free>
goto icmperr;
8019718: e085 b.n 8019826 <icmp_input+0x1e2>
}
/* copy the ip header */
MEMCPY(r->payload, iphdr_in, hlen);
801971a: 697b ldr r3, [r7, #20]
801971c: 685b ldr r3, [r3, #4]
801971e: 8c7a ldrh r2, [r7, #34] ; 0x22
8019720: 6a79 ldr r1, [r7, #36] ; 0x24
8019722: 4618 mov r0, r3
8019724: f001 fc63 bl 801afee <memcpy>
/* switch r->payload back to icmp header (cannot fail) */
if (pbuf_remove_header(r, hlen)) {
8019728: 8c7b ldrh r3, [r7, #34] ; 0x22
801972a: 4619 mov r1, r3
801972c: 6978 ldr r0, [r7, #20]
801972e: f7f6 fed5 bl 80104dc <pbuf_remove_header>
8019732: 4603 mov r3, r0
8019734: 2b00 cmp r3, #0
8019736: d009 beq.n 801974c <icmp_input+0x108>
LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
8019738: 4b40 ldr r3, [pc, #256] ; (801983c <icmp_input+0x1f8>)
801973a: 22b6 movs r2, #182 ; 0xb6
801973c: 4940 ldr r1, [pc, #256] ; (8019840 <icmp_input+0x1fc>)
801973e: 4841 ldr r0, [pc, #260] ; (8019844 <icmp_input+0x200>)
8019740: f001 fc68 bl 801b014 <iprintf>
pbuf_free(r);
8019744: 6978 ldr r0, [r7, #20]
8019746: f7f6 ff4f bl 80105e8 <pbuf_free>
goto icmperr;
801974a: e06c b.n 8019826 <icmp_input+0x1e2>
}
/* copy the rest of the packet without ip header */
if (pbuf_copy(r, p) != ERR_OK) {
801974c: 6879 ldr r1, [r7, #4]
801974e: 6978 ldr r0, [r7, #20]
8019750: f7f7 f87e bl 8010850 <pbuf_copy>
8019754: 4603 mov r3, r0
8019756: 2b00 cmp r3, #0
8019758: d003 beq.n 8019762 <icmp_input+0x11e>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
pbuf_free(r);
801975a: 6978 ldr r0, [r7, #20]
801975c: f7f6 ff44 bl 80105e8 <pbuf_free>
goto icmperr;
8019760: e061 b.n 8019826 <icmp_input+0x1e2>
}
/* free the original p */
pbuf_free(p);
8019762: 6878 ldr r0, [r7, #4]
8019764: f7f6 ff40 bl 80105e8 <pbuf_free>
/* we now have an identical copy of p that has room for link headers */
p = r;
8019768: 697b ldr r3, [r7, #20]
801976a: 607b str r3, [r7, #4]
801976c: e00f b.n 801978e <icmp_input+0x14a>
} else {
/* restore p->payload to point to icmp header (cannot fail) */
if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
801976e: 8c7b ldrh r3, [r7, #34] ; 0x22
8019770: 330e adds r3, #14
8019772: 4619 mov r1, r3
8019774: 6878 ldr r0, [r7, #4]
8019776: f7f6 feb1 bl 80104dc <pbuf_remove_header>
801977a: 4603 mov r3, r0
801977c: 2b00 cmp r3, #0
801977e: d006 beq.n 801978e <icmp_input+0x14a>
LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
8019780: 4b2e ldr r3, [pc, #184] ; (801983c <icmp_input+0x1f8>)
8019782: 22c7 movs r2, #199 ; 0xc7
8019784: 4930 ldr r1, [pc, #192] ; (8019848 <icmp_input+0x204>)
8019786: 482f ldr r0, [pc, #188] ; (8019844 <icmp_input+0x200>)
8019788: f001 fc44 bl 801b014 <iprintf>
goto icmperr;
801978c: e04b b.n 8019826 <icmp_input+0x1e2>
}
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
/* At this point, all checks are OK. */
/* We generate an answer by switching the dest and src ip addresses,
* setting the icmp type to ECHO_RESPONSE and updating the checksum. */
iecho = (struct icmp_echo_hdr *)p->payload;
801978e: 687b ldr r3, [r7, #4]
8019790: 685b ldr r3, [r3, #4]
8019792: 613b str r3, [r7, #16]
if (pbuf_add_header(p, hlen)) {
8019794: 8c7b ldrh r3, [r7, #34] ; 0x22
8019796: 4619 mov r1, r3
8019798: 6878 ldr r0, [r7, #4]
801979a: f7f6 fe8f bl 80104bc <pbuf_add_header>
801979e: 4603 mov r3, r0
80197a0: 2b00 cmp r3, #0
80197a2: d12b bne.n 80197fc <icmp_input+0x1b8>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
} else {
err_t ret;
struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
80197a4: 687b ldr r3, [r7, #4]
80197a6: 685b ldr r3, [r3, #4]
80197a8: 60fb str r3, [r7, #12]
ip4_addr_copy(iphdr->src, *src);
80197aa: 69fb ldr r3, [r7, #28]
80197ac: 681a ldr r2, [r3, #0]
80197ae: 68fb ldr r3, [r7, #12]
80197b0: 60da str r2, [r3, #12]
ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
80197b2: 4b20 ldr r3, [pc, #128] ; (8019834 <icmp_input+0x1f0>)
80197b4: 691a ldr r2, [r3, #16]
80197b6: 68fb ldr r3, [r7, #12]
80197b8: 611a str r2, [r3, #16]
ICMPH_TYPE_SET(iecho, ICMP_ER);
80197ba: 693b ldr r3, [r7, #16]
80197bc: 2200 movs r2, #0
80197be: 701a strb r2, [r3, #0]
else {
iecho->chksum = 0;
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
#else /* CHECKSUM_GEN_ICMP */
iecho->chksum = 0;
80197c0: 693b ldr r3, [r7, #16]
80197c2: 2200 movs r2, #0
80197c4: 709a strb r2, [r3, #2]
80197c6: 2200 movs r2, #0
80197c8: 70da strb r2, [r3, #3]
#endif /* CHECKSUM_GEN_ICMP */
/* Set the correct TTL and recalculate the header checksum. */
IPH_TTL_SET(iphdr, ICMP_TTL);
80197ca: 68fb ldr r3, [r7, #12]
80197cc: 22ff movs r2, #255 ; 0xff
80197ce: 721a strb r2, [r3, #8]
IPH_CHKSUM_SET(iphdr, 0);
80197d0: 68fb ldr r3, [r7, #12]
80197d2: 2200 movs r2, #0
80197d4: 729a strb r2, [r3, #10]
80197d6: 2200 movs r2, #0
80197d8: 72da strb r2, [r3, #11]
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* increase number of echo replies attempted to send */
MIB2_STATS_INC(mib2.icmpoutechoreps);
/* send an ICMP packet */
ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
80197da: 683b ldr r3, [r7, #0]
80197dc: 9302 str r3, [sp, #8]
80197de: 2301 movs r3, #1
80197e0: 9301 str r3, [sp, #4]
80197e2: 2300 movs r3, #0
80197e4: 9300 str r3, [sp, #0]
80197e6: 23ff movs r3, #255 ; 0xff
80197e8: 2200 movs r2, #0
80197ea: 69f9 ldr r1, [r7, #28]
80197ec: 6878 ldr r0, [r7, #4]
80197ee: f000 fa91 bl 8019d14 <ip4_output_if>
80197f2: 4603 mov r3, r0
80197f4: 72fb strb r3, [r7, #11]
ICMP_TTL, 0, IP_PROTO_ICMP, inp);
if (ret != ERR_OK) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
}
}
break;
80197f6: e001 b.n 80197fc <icmp_input+0x1b8>
break;
80197f8: bf00 nop
80197fa: e000 b.n 80197fe <icmp_input+0x1ba>
break;
80197fc: bf00 nop
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
(s16_t)type, (s16_t)code));
ICMP_STATS_INC(icmp.proterr);
ICMP_STATS_INC(icmp.drop);
}
pbuf_free(p);
80197fe: 6878 ldr r0, [r7, #4]
8019800: f7f6 fef2 bl 80105e8 <pbuf_free>
return;
8019804: e013 b.n 801982e <icmp_input+0x1ea>
goto lenerr;
8019806: bf00 nop
8019808: e002 b.n 8019810 <icmp_input+0x1cc>
goto lenerr;
801980a: bf00 nop
801980c: e000 b.n 8019810 <icmp_input+0x1cc>
goto lenerr;
801980e: bf00 nop
lenerr:
pbuf_free(p);
8019810: 6878 ldr r0, [r7, #4]
8019812: f7f6 fee9 bl 80105e8 <pbuf_free>
ICMP_STATS_INC(icmp.lenerr);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
8019816: e00a b.n 801982e <icmp_input+0x1ea>
goto icmperr;
8019818: bf00 nop
801981a: e004 b.n 8019826 <icmp_input+0x1e2>
goto icmperr;
801981c: bf00 nop
801981e: e002 b.n 8019826 <icmp_input+0x1e2>
goto icmperr;
8019820: bf00 nop
8019822: e000 b.n 8019826 <icmp_input+0x1e2>
goto icmperr;
8019824: bf00 nop
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
icmperr:
pbuf_free(p);
8019826: 6878 ldr r0, [r7, #4]
8019828: f7f6 fede bl 80105e8 <pbuf_free>
ICMP_STATS_INC(icmp.err);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
801982c: bf00 nop
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
}
801982e: 3728 adds r7, #40 ; 0x28
8019830: 46bd mov sp, r7
8019832: bd80 pop {r7, pc}
8019834: 2000be8c .word 0x2000be8c
8019838: 2000bea0 .word 0x2000bea0
801983c: 0801e9b0 .word 0x0801e9b0
8019840: 0801e9e8 .word 0x0801e9e8
8019844: 0801ea20 .word 0x0801ea20
8019848: 0801ea48 .word 0x0801ea48
0801984c <icmp_dest_unreach>:
* p->payload pointing to the IP header
* @param t type of the 'unreachable' packet
*/
void
icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
{
801984c: b580 push {r7, lr}
801984e: b082 sub sp, #8
8019850: af00 add r7, sp, #0
8019852: 6078 str r0, [r7, #4]
8019854: 460b mov r3, r1
8019856: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpoutdestunreachs);
icmp_send_response(p, ICMP_DUR, t);
8019858: 78fb ldrb r3, [r7, #3]
801985a: 461a mov r2, r3
801985c: 2103 movs r1, #3
801985e: 6878 ldr r0, [r7, #4]
8019860: f000 f814 bl 801988c <icmp_send_response>
}
8019864: bf00 nop
8019866: 3708 adds r7, #8
8019868: 46bd mov sp, r7
801986a: bd80 pop {r7, pc}
0801986c <icmp_time_exceeded>:
* p->payload pointing to the IP header
* @param t type of the 'time exceeded' packet
*/
void
icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
{
801986c: b580 push {r7, lr}
801986e: b082 sub sp, #8
8019870: af00 add r7, sp, #0
8019872: 6078 str r0, [r7, #4]
8019874: 460b mov r3, r1
8019876: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpouttimeexcds);
icmp_send_response(p, ICMP_TE, t);
8019878: 78fb ldrb r3, [r7, #3]
801987a: 461a mov r2, r3
801987c: 210b movs r1, #11
801987e: 6878 ldr r0, [r7, #4]
8019880: f000 f804 bl 801988c <icmp_send_response>
}
8019884: bf00 nop
8019886: 3708 adds r7, #8
8019888: 46bd mov sp, r7
801988a: bd80 pop {r7, pc}
0801988c <icmp_send_response>:
* @param type Type of the ICMP header
* @param code Code of the ICMP header
*/
static void
icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
{
801988c: b580 push {r7, lr}
801988e: b08c sub sp, #48 ; 0x30
8019890: af04 add r7, sp, #16
8019892: 6078 str r0, [r7, #4]
8019894: 460b mov r3, r1
8019896: 70fb strb r3, [r7, #3]
8019898: 4613 mov r3, r2
801989a: 70bb strb r3, [r7, #2]
/* increase number of messages attempted to send */
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* ICMP header + IP header + 8 bytes of data */
q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
801989c: f44f 7220 mov.w r2, #640 ; 0x280
80198a0: 2124 movs r1, #36 ; 0x24
80198a2: 2022 movs r0, #34 ; 0x22
80198a4: f7f6 fbc0 bl 8010028 <pbuf_alloc>
80198a8: 61f8 str r0, [r7, #28]
PBUF_RAM);
if (q == NULL) {
80198aa: 69fb ldr r3, [r7, #28]
80198ac: 2b00 cmp r3, #0
80198ae: d04c beq.n 801994a <icmp_send_response+0xbe>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
MIB2_STATS_INC(mib2.icmpouterrors);
return;
}
LWIP_ASSERT("check that first pbuf can hold icmp message",
80198b0: 69fb ldr r3, [r7, #28]
80198b2: 895b ldrh r3, [r3, #10]
80198b4: 2b23 cmp r3, #35 ; 0x23
80198b6: d806 bhi.n 80198c6 <icmp_send_response+0x3a>
80198b8: 4b26 ldr r3, [pc, #152] ; (8019954 <icmp_send_response+0xc8>)
80198ba: f240 1269 movw r2, #361 ; 0x169
80198be: 4926 ldr r1, [pc, #152] ; (8019958 <icmp_send_response+0xcc>)
80198c0: 4826 ldr r0, [pc, #152] ; (801995c <icmp_send_response+0xd0>)
80198c2: f001 fba7 bl 801b014 <iprintf>
(q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
iphdr = (struct ip_hdr *)p->payload;
80198c6: 687b ldr r3, [r7, #4]
80198c8: 685b ldr r3, [r3, #4]
80198ca: 61bb str r3, [r7, #24]
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
LWIP_DEBUGF(ICMP_DEBUG, (" to "));
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
icmphdr = (struct icmp_echo_hdr *)q->payload;
80198cc: 69fb ldr r3, [r7, #28]
80198ce: 685b ldr r3, [r3, #4]
80198d0: 617b str r3, [r7, #20]
icmphdr->type = type;
80198d2: 697b ldr r3, [r7, #20]
80198d4: 78fa ldrb r2, [r7, #3]
80198d6: 701a strb r2, [r3, #0]
icmphdr->code = code;
80198d8: 697b ldr r3, [r7, #20]
80198da: 78ba ldrb r2, [r7, #2]
80198dc: 705a strb r2, [r3, #1]
icmphdr->id = 0;
80198de: 697b ldr r3, [r7, #20]
80198e0: 2200 movs r2, #0
80198e2: 711a strb r2, [r3, #4]
80198e4: 2200 movs r2, #0
80198e6: 715a strb r2, [r3, #5]
icmphdr->seqno = 0;
80198e8: 697b ldr r3, [r7, #20]
80198ea: 2200 movs r2, #0
80198ec: 719a strb r2, [r3, #6]
80198ee: 2200 movs r2, #0
80198f0: 71da strb r2, [r3, #7]
/* copy fields from original packet */
SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
80198f2: 69fb ldr r3, [r7, #28]
80198f4: 685b ldr r3, [r3, #4]
80198f6: f103 0008 add.w r0, r3, #8
80198fa: 687b ldr r3, [r7, #4]
80198fc: 685b ldr r3, [r3, #4]
80198fe: 221c movs r2, #28
8019900: 4619 mov r1, r3
8019902: f001 fb74 bl 801afee <memcpy>
IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
ip4_addr_copy(iphdr_src, iphdr->src);
8019906: 69bb ldr r3, [r7, #24]
8019908: 68db ldr r3, [r3, #12]
801990a: 60fb str r3, [r7, #12]
ip4_addr_t iphdr_dst;
ip4_addr_copy(iphdr_dst, iphdr->dest);
netif = ip4_route_src(&iphdr_dst, &iphdr_src);
}
#else
netif = ip4_route(&iphdr_src);
801990c: f107 030c add.w r3, r7, #12
8019910: 4618 mov r0, r3
8019912: f000 f825 bl 8019960 <ip4_route>
8019916: 6138 str r0, [r7, #16]
#endif
if (netif != NULL) {
8019918: 693b ldr r3, [r7, #16]
801991a: 2b00 cmp r3, #0
801991c: d011 beq.n 8019942 <icmp_send_response+0xb6>
/* calculate checksum */
icmphdr->chksum = 0;
801991e: 697b ldr r3, [r7, #20]
8019920: 2200 movs r2, #0
8019922: 709a strb r2, [r3, #2]
8019924: 2200 movs r2, #0
8019926: 70da strb r2, [r3, #3]
IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
icmphdr->chksum = inet_chksum(icmphdr, q->len);
}
#endif
ICMP_STATS_INC(icmp.xmit);
ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
8019928: f107 020c add.w r2, r7, #12
801992c: 693b ldr r3, [r7, #16]
801992e: 9302 str r3, [sp, #8]
8019930: 2301 movs r3, #1
8019932: 9301 str r3, [sp, #4]
8019934: 2300 movs r3, #0
8019936: 9300 str r3, [sp, #0]
8019938: 23ff movs r3, #255 ; 0xff
801993a: 2100 movs r1, #0
801993c: 69f8 ldr r0, [r7, #28]
801993e: f000 f9e9 bl 8019d14 <ip4_output_if>
}
pbuf_free(q);
8019942: 69f8 ldr r0, [r7, #28]
8019944: f7f6 fe50 bl 80105e8 <pbuf_free>
8019948: e000 b.n 801994c <icmp_send_response+0xc0>
return;
801994a: bf00 nop
}
801994c: 3720 adds r7, #32
801994e: 46bd mov sp, r7
8019950: bd80 pop {r7, pc}
8019952: bf00 nop
8019954: 0801e9b0 .word 0x0801e9b0
8019958: 0801ea7c .word 0x0801ea7c
801995c: 0801ea20 .word 0x0801ea20
08019960 <ip4_route>:
* @param dest the destination IP address for which to find the route
* @return the netif on which to send to reach dest
*/
struct netif *
ip4_route(const ip4_addr_t *dest)
{
8019960: b480 push {r7}
8019962: b085 sub sp, #20
8019964: af00 add r7, sp, #0
8019966: 6078 str r0, [r7, #4]
/* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
LWIP_UNUSED_ARG(dest);
/* iterate through netifs */
NETIF_FOREACH(netif) {
8019968: 4b33 ldr r3, [pc, #204] ; (8019a38 <ip4_route+0xd8>)
801996a: 681b ldr r3, [r3, #0]
801996c: 60fb str r3, [r7, #12]
801996e: e036 b.n 80199de <ip4_route+0x7e>
/* is the netif up, does it have a link and a valid address? */
if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8019970: 68fb ldr r3, [r7, #12]
8019972: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019976: f003 0301 and.w r3, r3, #1
801997a: b2db uxtb r3, r3
801997c: 2b00 cmp r3, #0
801997e: d02b beq.n 80199d8 <ip4_route+0x78>
8019980: 68fb ldr r3, [r7, #12]
8019982: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019986: 089b lsrs r3, r3, #2
8019988: f003 0301 and.w r3, r3, #1
801998c: b2db uxtb r3, r3
801998e: 2b00 cmp r3, #0
8019990: d022 beq.n 80199d8 <ip4_route+0x78>
8019992: 68fb ldr r3, [r7, #12]
8019994: 3304 adds r3, #4
8019996: 681b ldr r3, [r3, #0]
8019998: 2b00 cmp r3, #0
801999a: d01d beq.n 80199d8 <ip4_route+0x78>
/* network mask matches? */
if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
801999c: 687b ldr r3, [r7, #4]
801999e: 681a ldr r2, [r3, #0]
80199a0: 68fb ldr r3, [r7, #12]
80199a2: 3304 adds r3, #4
80199a4: 681b ldr r3, [r3, #0]
80199a6: 405a eors r2, r3
80199a8: 68fb ldr r3, [r7, #12]
80199aa: 3308 adds r3, #8
80199ac: 681b ldr r3, [r3, #0]
80199ae: 4013 ands r3, r2
80199b0: 2b00 cmp r3, #0
80199b2: d101 bne.n 80199b8 <ip4_route+0x58>
/* return netif on which to forward IP packet */
return netif;
80199b4: 68fb ldr r3, [r7, #12]
80199b6: e038 b.n 8019a2a <ip4_route+0xca>
}
/* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
80199b8: 68fb ldr r3, [r7, #12]
80199ba: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80199be: f003 0302 and.w r3, r3, #2
80199c2: 2b00 cmp r3, #0
80199c4: d108 bne.n 80199d8 <ip4_route+0x78>
80199c6: 687b ldr r3, [r7, #4]
80199c8: 681a ldr r2, [r3, #0]
80199ca: 68fb ldr r3, [r7, #12]
80199cc: 330c adds r3, #12
80199ce: 681b ldr r3, [r3, #0]
80199d0: 429a cmp r2, r3
80199d2: d101 bne.n 80199d8 <ip4_route+0x78>
/* return netif on which to forward IP packet */
return netif;
80199d4: 68fb ldr r3, [r7, #12]
80199d6: e028 b.n 8019a2a <ip4_route+0xca>
NETIF_FOREACH(netif) {
80199d8: 68fb ldr r3, [r7, #12]
80199da: 681b ldr r3, [r3, #0]
80199dc: 60fb str r3, [r7, #12]
80199de: 68fb ldr r3, [r7, #12]
80199e0: 2b00 cmp r3, #0
80199e2: d1c5 bne.n 8019970 <ip4_route+0x10>
return netif;
}
#endif
#endif /* !LWIP_SINGLE_NETIF */
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
80199e4: 4b15 ldr r3, [pc, #84] ; (8019a3c <ip4_route+0xdc>)
80199e6: 681b ldr r3, [r3, #0]
80199e8: 2b00 cmp r3, #0
80199ea: d01a beq.n 8019a22 <ip4_route+0xc2>
80199ec: 4b13 ldr r3, [pc, #76] ; (8019a3c <ip4_route+0xdc>)
80199ee: 681b ldr r3, [r3, #0]
80199f0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80199f4: f003 0301 and.w r3, r3, #1
80199f8: 2b00 cmp r3, #0
80199fa: d012 beq.n 8019a22 <ip4_route+0xc2>
80199fc: 4b0f ldr r3, [pc, #60] ; (8019a3c <ip4_route+0xdc>)
80199fe: 681b ldr r3, [r3, #0]
8019a00: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019a04: f003 0304 and.w r3, r3, #4
8019a08: 2b00 cmp r3, #0
8019a0a: d00a beq.n 8019a22 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
8019a0c: 4b0b ldr r3, [pc, #44] ; (8019a3c <ip4_route+0xdc>)
8019a0e: 681b ldr r3, [r3, #0]
8019a10: 3304 adds r3, #4
8019a12: 681b ldr r3, [r3, #0]
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
8019a14: 2b00 cmp r3, #0
8019a16: d004 beq.n 8019a22 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
8019a18: 687b ldr r3, [r7, #4]
8019a1a: 681b ldr r3, [r3, #0]
8019a1c: b2db uxtb r3, r3
8019a1e: 2b7f cmp r3, #127 ; 0x7f
8019a20: d101 bne.n 8019a26 <ip4_route+0xc6>
If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
IP_STATS_INC(ip.rterr);
MIB2_STATS_INC(mib2.ipoutnoroutes);
return NULL;
8019a22: 2300 movs r3, #0
8019a24: e001 b.n 8019a2a <ip4_route+0xca>
}
return netif_default;
8019a26: 4b05 ldr r3, [pc, #20] ; (8019a3c <ip4_route+0xdc>)
8019a28: 681b ldr r3, [r3, #0]
}
8019a2a: 4618 mov r0, r3
8019a2c: 3714 adds r7, #20
8019a2e: 46bd mov sp, r7
8019a30: f85d 7b04 ldr.w r7, [sp], #4
8019a34: 4770 bx lr
8019a36: bf00 nop
8019a38: 2000f5b0 .word 0x2000f5b0
8019a3c: 2000f5b4 .word 0x2000f5b4
08019a40 <ip4_input_accept>:
#endif /* IP_FORWARD */
/** Return true if the current input packet should be accepted on this netif */
static int
ip4_input_accept(struct netif *netif)
{
8019a40: b580 push {r7, lr}
8019a42: b082 sub sp, #8
8019a44: af00 add r7, sp, #0
8019a46: 6078 str r0, [r7, #4]
ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
/* interface is up and configured? */
if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
8019a48: 687b ldr r3, [r7, #4]
8019a4a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019a4e: f003 0301 and.w r3, r3, #1
8019a52: b2db uxtb r3, r3
8019a54: 2b00 cmp r3, #0
8019a56: d016 beq.n 8019a86 <ip4_input_accept+0x46>
8019a58: 687b ldr r3, [r7, #4]
8019a5a: 3304 adds r3, #4
8019a5c: 681b ldr r3, [r3, #0]
8019a5e: 2b00 cmp r3, #0
8019a60: d011 beq.n 8019a86 <ip4_input_accept+0x46>
/* unicast to this interface address? */
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a62: 4b0b ldr r3, [pc, #44] ; (8019a90 <ip4_input_accept+0x50>)
8019a64: 695a ldr r2, [r3, #20]
8019a66: 687b ldr r3, [r7, #4]
8019a68: 3304 adds r3, #4
8019a6a: 681b ldr r3, [r3, #0]
8019a6c: 429a cmp r2, r3
8019a6e: d008 beq.n 8019a82 <ip4_input_accept+0x42>
/* or broadcast on this interface network address? */
ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
8019a70: 4b07 ldr r3, [pc, #28] ; (8019a90 <ip4_input_accept+0x50>)
8019a72: 695b ldr r3, [r3, #20]
8019a74: 6879 ldr r1, [r7, #4]
8019a76: 4618 mov r0, r3
8019a78: f000 fa24 bl 8019ec4 <ip4_addr_isbroadcast_u32>
8019a7c: 4603 mov r3, r0
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a7e: 2b00 cmp r3, #0
8019a80: d001 beq.n 8019a86 <ip4_input_accept+0x46>
#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
) {
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
netif->name[0], netif->name[1]));
/* accept on this netif */
return 1;
8019a82: 2301 movs r3, #1
8019a84: e000 b.n 8019a88 <ip4_input_accept+0x48>
/* accept on this netif */
return 1;
}
#endif /* LWIP_AUTOIP */
}
return 0;
8019a86: 2300 movs r3, #0
}
8019a88: 4618 mov r0, r3
8019a8a: 3708 adds r7, #8
8019a8c: 46bd mov sp, r7
8019a8e: bd80 pop {r7, pc}
8019a90: 2000be8c .word 0x2000be8c
08019a94 <ip4_input>:
* @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
* processed, but currently always returns ERR_OK)
*/
err_t
ip4_input(struct pbuf *p, struct netif *inp)
{
8019a94: b580 push {r7, lr}
8019a96: b088 sub sp, #32
8019a98: af00 add r7, sp, #0
8019a9a: 6078 str r0, [r7, #4]
8019a9c: 6039 str r1, [r7, #0]
const struct ip_hdr *iphdr;
struct netif *netif;
u16_t iphdr_hlen;
u16_t iphdr_len;
#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP
int check_ip_src = 1;
8019a9e: 2301 movs r3, #1
8019aa0: 617b str r3, [r7, #20]
IP_STATS_INC(ip.recv);
MIB2_STATS_INC(mib2.ipinreceives);
/* identify the IP header */
iphdr = (struct ip_hdr *)p->payload;
8019aa2: 687b ldr r3, [r7, #4]
8019aa4: 685b ldr r3, [r3, #4]
8019aa6: 61fb str r3, [r7, #28]
if (IPH_V(iphdr) != 4) {
8019aa8: 69fb ldr r3, [r7, #28]
8019aaa: 781b ldrb r3, [r3, #0]
8019aac: 091b lsrs r3, r3, #4
8019aae: b2db uxtb r3, r3
8019ab0: 2b04 cmp r3, #4
8019ab2: d004 beq.n 8019abe <ip4_input+0x2a>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
ip4_debug_print(p);
pbuf_free(p);
8019ab4: 6878 ldr r0, [r7, #4]
8019ab6: f7f6 fd97 bl 80105e8 <pbuf_free>
IP_STATS_INC(ip.err);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinhdrerrors);
return ERR_OK;
8019aba: 2300 movs r3, #0
8019abc: e121 b.n 8019d02 <ip4_input+0x26e>
return ERR_OK;
}
#endif
/* obtain IP header length in bytes */
iphdr_hlen = IPH_HL_BYTES(iphdr);
8019abe: 69fb ldr r3, [r7, #28]
8019ac0: 781b ldrb r3, [r3, #0]
8019ac2: f003 030f and.w r3, r3, #15
8019ac6: b2db uxtb r3, r3
8019ac8: 009b lsls r3, r3, #2
8019aca: b2db uxtb r3, r3
8019acc: 827b strh r3, [r7, #18]
/* obtain ip length in bytes */
iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
8019ace: 69fb ldr r3, [r7, #28]
8019ad0: 885b ldrh r3, [r3, #2]
8019ad2: b29b uxth r3, r3
8019ad4: 4618 mov r0, r3
8019ad6: f7f5 f9d3 bl 800ee80 <lwip_htons>
8019ada: 4603 mov r3, r0
8019adc: 823b strh r3, [r7, #16]
/* Trim pbuf. This is especially required for packets < 60 bytes. */
if (iphdr_len < p->tot_len) {
8019ade: 687b ldr r3, [r7, #4]
8019ae0: 891b ldrh r3, [r3, #8]
8019ae2: 8a3a ldrh r2, [r7, #16]
8019ae4: 429a cmp r2, r3
8019ae6: d204 bcs.n 8019af2 <ip4_input+0x5e>
pbuf_realloc(p, iphdr_len);
8019ae8: 8a3b ldrh r3, [r7, #16]
8019aea: 4619 mov r1, r3
8019aec: 6878 ldr r0, [r7, #4]
8019aee: f7f6 fbf5 bl 80102dc <pbuf_realloc>
}
/* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
8019af2: 687b ldr r3, [r7, #4]
8019af4: 895b ldrh r3, [r3, #10]
8019af6: 8a7a ldrh r2, [r7, #18]
8019af8: 429a cmp r2, r3
8019afa: d807 bhi.n 8019b0c <ip4_input+0x78>
8019afc: 687b ldr r3, [r7, #4]
8019afe: 891b ldrh r3, [r3, #8]
8019b00: 8a3a ldrh r2, [r7, #16]
8019b02: 429a cmp r2, r3
8019b04: d802 bhi.n 8019b0c <ip4_input+0x78>
8019b06: 8a7b ldrh r3, [r7, #18]
8019b08: 2b13 cmp r3, #19
8019b0a: d804 bhi.n 8019b16 <ip4_input+0x82>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
iphdr_len, p->tot_len));
}
/* free (drop) packet pbufs */
pbuf_free(p);
8019b0c: 6878 ldr r0, [r7, #4]
8019b0e: f7f6 fd6b bl 80105e8 <pbuf_free>
IP_STATS_INC(ip.lenerr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019b12: 2300 movs r3, #0
8019b14: e0f5 b.n 8019d02 <ip4_input+0x26e>
}
}
#endif
/* copy IP addresses to aligned ip_addr_t */
ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
8019b16: 69fb ldr r3, [r7, #28]
8019b18: 691b ldr r3, [r3, #16]
8019b1a: 4a7c ldr r2, [pc, #496] ; (8019d0c <ip4_input+0x278>)
8019b1c: 6153 str r3, [r2, #20]
ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
8019b1e: 69fb ldr r3, [r7, #28]
8019b20: 68db ldr r3, [r3, #12]
8019b22: 4a7a ldr r2, [pc, #488] ; (8019d0c <ip4_input+0x278>)
8019b24: 6113 str r3, [r2, #16]
/* match packet against an interface, i.e. is this packet for us? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019b26: 4b79 ldr r3, [pc, #484] ; (8019d0c <ip4_input+0x278>)
8019b28: 695b ldr r3, [r3, #20]
8019b2a: f003 03f0 and.w r3, r3, #240 ; 0xf0
8019b2e: 2be0 cmp r3, #224 ; 0xe0
8019b30: d112 bne.n 8019b58 <ip4_input+0xc4>
netif = inp;
} else {
netif = NULL;
}
#else /* LWIP_IGMP */
if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
8019b32: 683b ldr r3, [r7, #0]
8019b34: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019b38: f003 0301 and.w r3, r3, #1
8019b3c: b2db uxtb r3, r3
8019b3e: 2b00 cmp r3, #0
8019b40: d007 beq.n 8019b52 <ip4_input+0xbe>
8019b42: 683b ldr r3, [r7, #0]
8019b44: 3304 adds r3, #4
8019b46: 681b ldr r3, [r3, #0]
8019b48: 2b00 cmp r3, #0
8019b4a: d002 beq.n 8019b52 <ip4_input+0xbe>
netif = inp;
8019b4c: 683b ldr r3, [r7, #0]
8019b4e: 61bb str r3, [r7, #24]
8019b50: e02a b.n 8019ba8 <ip4_input+0x114>
} else {
netif = NULL;
8019b52: 2300 movs r3, #0
8019b54: 61bb str r3, [r7, #24]
8019b56: e027 b.n 8019ba8 <ip4_input+0x114>
}
#endif /* LWIP_IGMP */
} else {
/* start trying with inp. if that's not acceptable, start walking the
list of configured netifs. */
if (ip4_input_accept(inp)) {
8019b58: 6838 ldr r0, [r7, #0]
8019b5a: f7ff ff71 bl 8019a40 <ip4_input_accept>
8019b5e: 4603 mov r3, r0
8019b60: 2b00 cmp r3, #0
8019b62: d002 beq.n 8019b6a <ip4_input+0xd6>
netif = inp;
8019b64: 683b ldr r3, [r7, #0]
8019b66: 61bb str r3, [r7, #24]
8019b68: e01e b.n 8019ba8 <ip4_input+0x114>
} else {
netif = NULL;
8019b6a: 2300 movs r3, #0
8019b6c: 61bb str r3, [r7, #24]
#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
/* Packets sent to the loopback address must not be accepted on an
* interface that does not have the loopback address assigned to it,
* unless a non-loopback interface is used for loopback traffic. */
if (!ip4_addr_isloopback(ip4_current_dest_addr()))
8019b6e: 4b67 ldr r3, [pc, #412] ; (8019d0c <ip4_input+0x278>)
8019b70: 695b ldr r3, [r3, #20]
8019b72: b2db uxtb r3, r3
8019b74: 2b7f cmp r3, #127 ; 0x7f
8019b76: d017 beq.n 8019ba8 <ip4_input+0x114>
#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
{
#if !LWIP_SINGLE_NETIF
NETIF_FOREACH(netif) {
8019b78: 4b65 ldr r3, [pc, #404] ; (8019d10 <ip4_input+0x27c>)
8019b7a: 681b ldr r3, [r3, #0]
8019b7c: 61bb str r3, [r7, #24]
8019b7e: e00e b.n 8019b9e <ip4_input+0x10a>
if (netif == inp) {
8019b80: 69ba ldr r2, [r7, #24]
8019b82: 683b ldr r3, [r7, #0]
8019b84: 429a cmp r2, r3
8019b86: d006 beq.n 8019b96 <ip4_input+0x102>
/* we checked that before already */
continue;
}
if (ip4_input_accept(netif)) {
8019b88: 69b8 ldr r0, [r7, #24]
8019b8a: f7ff ff59 bl 8019a40 <ip4_input_accept>
8019b8e: 4603 mov r3, r0
8019b90: 2b00 cmp r3, #0
8019b92: d108 bne.n 8019ba6 <ip4_input+0x112>
8019b94: e000 b.n 8019b98 <ip4_input+0x104>
continue;
8019b96: bf00 nop
NETIF_FOREACH(netif) {
8019b98: 69bb ldr r3, [r7, #24]
8019b9a: 681b ldr r3, [r3, #0]
8019b9c: 61bb str r3, [r7, #24]
8019b9e: 69bb ldr r3, [r7, #24]
8019ba0: 2b00 cmp r3, #0
8019ba2: d1ed bne.n 8019b80 <ip4_input+0xec>
8019ba4: e000 b.n 8019ba8 <ip4_input+0x114>
break;
8019ba6: bf00 nop
* If you want to accept private broadcast communication while a netif is down,
* define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
*
* #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
*/
if (netif == NULL) {
8019ba8: 69bb ldr r3, [r7, #24]
8019baa: 2b00 cmp r3, #0
8019bac: d111 bne.n 8019bd2 <ip4_input+0x13e>
/* remote port is DHCP server? */
if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
8019bae: 69fb ldr r3, [r7, #28]
8019bb0: 7a5b ldrb r3, [r3, #9]
8019bb2: 2b11 cmp r3, #17
8019bb4: d10d bne.n 8019bd2 <ip4_input+0x13e>
const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen);
8019bb6: 8a7b ldrh r3, [r7, #18]
8019bb8: 69fa ldr r2, [r7, #28]
8019bba: 4413 add r3, r2
8019bbc: 60fb str r3, [r7, #12]
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n",
lwip_ntohs(udphdr->dest)));
if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
8019bbe: 68fb ldr r3, [r7, #12]
8019bc0: 885b ldrh r3, [r3, #2]
8019bc2: b29b uxth r3, r3
8019bc4: f5b3 4f88 cmp.w r3, #17408 ; 0x4400
8019bc8: d103 bne.n 8019bd2 <ip4_input+0x13e>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n"));
netif = inp;
8019bca: 683b ldr r3, [r7, #0]
8019bcc: 61bb str r3, [r7, #24]
check_ip_src = 0;
8019bce: 2300 movs r3, #0
8019bd0: 617b str r3, [r7, #20]
}
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
/* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING
if (check_ip_src
8019bd2: 697b ldr r3, [r7, #20]
8019bd4: 2b00 cmp r3, #0
8019bd6: d017 beq.n 8019c08 <ip4_input+0x174>
#if IP_ACCEPT_LINK_LAYER_ADDRESSING
/* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
&& !ip4_addr_isany_val(*ip4_current_src_addr())
8019bd8: 4b4c ldr r3, [pc, #304] ; (8019d0c <ip4_input+0x278>)
8019bda: 691b ldr r3, [r3, #16]
8019bdc: 2b00 cmp r3, #0
8019bde: d013 beq.n 8019c08 <ip4_input+0x174>
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
)
#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
{
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019be0: 4b4a ldr r3, [pc, #296] ; (8019d0c <ip4_input+0x278>)
8019be2: 691b ldr r3, [r3, #16]
8019be4: 6839 ldr r1, [r7, #0]
8019be6: 4618 mov r0, r3
8019be8: f000 f96c bl 8019ec4 <ip4_addr_isbroadcast_u32>
8019bec: 4603 mov r3, r0
8019bee: 2b00 cmp r3, #0
8019bf0: d105 bne.n 8019bfe <ip4_input+0x16a>
(ip4_addr_ismulticast(ip4_current_src_addr()))) {
8019bf2: 4b46 ldr r3, [pc, #280] ; (8019d0c <ip4_input+0x278>)
8019bf4: 691b ldr r3, [r3, #16]
8019bf6: f003 03f0 and.w r3, r3, #240 ; 0xf0
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019bfa: 2be0 cmp r3, #224 ; 0xe0
8019bfc: d104 bne.n 8019c08 <ip4_input+0x174>
/* packet source is not valid */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
/* free (drop) packet pbufs */
pbuf_free(p);
8019bfe: 6878 ldr r0, [r7, #4]
8019c00: f7f6 fcf2 bl 80105e8 <pbuf_free>
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019c04: 2300 movs r3, #0
8019c06: e07c b.n 8019d02 <ip4_input+0x26e>
}
}
/* packet not for us? */
if (netif == NULL) {
8019c08: 69bb ldr r3, [r7, #24]
8019c0a: 2b00 cmp r3, #0
8019c0c: d104 bne.n 8019c18 <ip4_input+0x184>
{
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
}
pbuf_free(p);
8019c0e: 6878 ldr r0, [r7, #4]
8019c10: f7f6 fcea bl 80105e8 <pbuf_free>
return ERR_OK;
8019c14: 2300 movs r3, #0
8019c16: e074 b.n 8019d02 <ip4_input+0x26e>
}
/* packet consists of multiple fragments? */
if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
8019c18: 69fb ldr r3, [r7, #28]
8019c1a: 88db ldrh r3, [r3, #6]
8019c1c: b29b uxth r3, r3
8019c1e: 461a mov r2, r3
8019c20: f64f 733f movw r3, #65343 ; 0xff3f
8019c24: 4013 ands r3, r2
8019c26: 2b00 cmp r3, #0
8019c28: d00b beq.n 8019c42 <ip4_input+0x1ae>
#if IP_REASSEMBLY /* packet fragment reassembly code present? */
LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
/* reassemble the packet*/
p = ip4_reass(p);
8019c2a: 6878 ldr r0, [r7, #4]
8019c2c: f000 fc90 bl 801a550 <ip4_reass>
8019c30: 6078 str r0, [r7, #4]
/* packet not fully reassembled yet? */
if (p == NULL) {
8019c32: 687b ldr r3, [r7, #4]
8019c34: 2b00 cmp r3, #0
8019c36: d101 bne.n 8019c3c <ip4_input+0x1a8>
return ERR_OK;
8019c38: 2300 movs r3, #0
8019c3a: e062 b.n 8019d02 <ip4_input+0x26e>
}
iphdr = (const struct ip_hdr *)p->payload;
8019c3c: 687b ldr r3, [r7, #4]
8019c3e: 685b ldr r3, [r3, #4]
8019c40: 61fb str r3, [r7, #28]
/* send to upper layers */
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
ip4_debug_print(p);
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
ip_data.current_netif = netif;
8019c42: 4a32 ldr r2, [pc, #200] ; (8019d0c <ip4_input+0x278>)
8019c44: 69bb ldr r3, [r7, #24]
8019c46: 6013 str r3, [r2, #0]
ip_data.current_input_netif = inp;
8019c48: 4a30 ldr r2, [pc, #192] ; (8019d0c <ip4_input+0x278>)
8019c4a: 683b ldr r3, [r7, #0]
8019c4c: 6053 str r3, [r2, #4]
ip_data.current_ip4_header = iphdr;
8019c4e: 4a2f ldr r2, [pc, #188] ; (8019d0c <ip4_input+0x278>)
8019c50: 69fb ldr r3, [r7, #28]
8019c52: 6093 str r3, [r2, #8]
ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
8019c54: 69fb ldr r3, [r7, #28]
8019c56: 781b ldrb r3, [r3, #0]
8019c58: f003 030f and.w r3, r3, #15
8019c5c: b2db uxtb r3, r3
8019c5e: 009b lsls r3, r3, #2
8019c60: b2db uxtb r3, r3
8019c62: b29a uxth r2, r3
8019c64: 4b29 ldr r3, [pc, #164] ; (8019d0c <ip4_input+0x278>)
8019c66: 819a strh r2, [r3, #12]
/* raw input did not eat the packet? */
raw_status = raw_input(p, inp);
if (raw_status != RAW_INPUT_EATEN)
#endif /* LWIP_RAW */
{
pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
8019c68: 8a7b ldrh r3, [r7, #18]
8019c6a: 4619 mov r1, r3
8019c6c: 6878 ldr r0, [r7, #4]
8019c6e: f7f6 fc35 bl 80104dc <pbuf_remove_header>
switch (IPH_PROTO(iphdr)) {
8019c72: 69fb ldr r3, [r7, #28]
8019c74: 7a5b ldrb r3, [r3, #9]
8019c76: 2b06 cmp r3, #6
8019c78: d009 beq.n 8019c8e <ip4_input+0x1fa>
8019c7a: 2b11 cmp r3, #17
8019c7c: d002 beq.n 8019c84 <ip4_input+0x1f0>
8019c7e: 2b01 cmp r3, #1
8019c80: d00a beq.n 8019c98 <ip4_input+0x204>
8019c82: e00e b.n 8019ca2 <ip4_input+0x20e>
case IP_PROTO_UDP:
#if LWIP_UDPLITE
case IP_PROTO_UDPLITE:
#endif /* LWIP_UDPLITE */
MIB2_STATS_INC(mib2.ipindelivers);
udp_input(p, inp);
8019c84: 6839 ldr r1, [r7, #0]
8019c86: 6878 ldr r0, [r7, #4]
8019c88: f7fc fada bl 8016240 <udp_input>
break;
8019c8c: e026 b.n 8019cdc <ip4_input+0x248>
#endif /* LWIP_UDP */
#if LWIP_TCP
case IP_PROTO_TCP:
MIB2_STATS_INC(mib2.ipindelivers);
tcp_input(p, inp);
8019c8e: 6839 ldr r1, [r7, #0]
8019c90: 6878 ldr r0, [r7, #4]
8019c92: f7f8 fae1 bl 8012258 <tcp_input>
break;
8019c96: e021 b.n 8019cdc <ip4_input+0x248>
#endif /* LWIP_TCP */
#if LWIP_ICMP
case IP_PROTO_ICMP:
MIB2_STATS_INC(mib2.ipindelivers);
icmp_input(p, inp);
8019c98: 6839 ldr r1, [r7, #0]
8019c9a: 6878 ldr r0, [r7, #4]
8019c9c: f7ff fcd2 bl 8019644 <icmp_input>
break;
8019ca0: e01c b.n 8019cdc <ip4_input+0x248>
} else
#endif /* LWIP_RAW */
{
#if LWIP_ICMP
/* send ICMP destination protocol unreachable unless is was a broadcast */
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019ca2: 4b1a ldr r3, [pc, #104] ; (8019d0c <ip4_input+0x278>)
8019ca4: 695b ldr r3, [r3, #20]
8019ca6: 69b9 ldr r1, [r7, #24]
8019ca8: 4618 mov r0, r3
8019caa: f000 f90b bl 8019ec4 <ip4_addr_isbroadcast_u32>
8019cae: 4603 mov r3, r0
8019cb0: 2b00 cmp r3, #0
8019cb2: d10f bne.n 8019cd4 <ip4_input+0x240>
!ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019cb4: 4b15 ldr r3, [pc, #84] ; (8019d0c <ip4_input+0x278>)
8019cb6: 695b ldr r3, [r3, #20]
8019cb8: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019cbc: 2be0 cmp r3, #224 ; 0xe0
8019cbe: d009 beq.n 8019cd4 <ip4_input+0x240>
pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
8019cc0: f9b7 3012 ldrsh.w r3, [r7, #18]
8019cc4: 4619 mov r1, r3
8019cc6: 6878 ldr r0, [r7, #4]
8019cc8: f7f6 fc7b bl 80105c2 <pbuf_header_force>
icmp_dest_unreach(p, ICMP_DUR_PROTO);
8019ccc: 2102 movs r1, #2
8019cce: 6878 ldr r0, [r7, #4]
8019cd0: f7ff fdbc bl 801984c <icmp_dest_unreach>
IP_STATS_INC(ip.proterr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinunknownprotos);
}
pbuf_free(p);
8019cd4: 6878 ldr r0, [r7, #4]
8019cd6: f7f6 fc87 bl 80105e8 <pbuf_free>
break;
8019cda: bf00 nop
}
}
/* @todo: this is not really necessary... */
ip_data.current_netif = NULL;
8019cdc: 4b0b ldr r3, [pc, #44] ; (8019d0c <ip4_input+0x278>)
8019cde: 2200 movs r2, #0
8019ce0: 601a str r2, [r3, #0]
ip_data.current_input_netif = NULL;
8019ce2: 4b0a ldr r3, [pc, #40] ; (8019d0c <ip4_input+0x278>)
8019ce4: 2200 movs r2, #0
8019ce6: 605a str r2, [r3, #4]
ip_data.current_ip4_header = NULL;
8019ce8: 4b08 ldr r3, [pc, #32] ; (8019d0c <ip4_input+0x278>)
8019cea: 2200 movs r2, #0
8019cec: 609a str r2, [r3, #8]
ip_data.current_ip_header_tot_len = 0;
8019cee: 4b07 ldr r3, [pc, #28] ; (8019d0c <ip4_input+0x278>)
8019cf0: 2200 movs r2, #0
8019cf2: 819a strh r2, [r3, #12]
ip4_addr_set_any(ip4_current_src_addr());
8019cf4: 4b05 ldr r3, [pc, #20] ; (8019d0c <ip4_input+0x278>)
8019cf6: 2200 movs r2, #0
8019cf8: 611a str r2, [r3, #16]
ip4_addr_set_any(ip4_current_dest_addr());
8019cfa: 4b04 ldr r3, [pc, #16] ; (8019d0c <ip4_input+0x278>)
8019cfc: 2200 movs r2, #0
8019cfe: 615a str r2, [r3, #20]
return ERR_OK;
8019d00: 2300 movs r3, #0
}
8019d02: 4618 mov r0, r3
8019d04: 3720 adds r7, #32
8019d06: 46bd mov sp, r7
8019d08: bd80 pop {r7, pc}
8019d0a: bf00 nop
8019d0c: 2000be8c .word 0x2000be8c
8019d10: 2000f5b0 .word 0x2000f5b0
08019d14 <ip4_output_if>:
*/
err_t
ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019d14: b580 push {r7, lr}
8019d16: b08a sub sp, #40 ; 0x28
8019d18: af04 add r7, sp, #16
8019d1a: 60f8 str r0, [r7, #12]
8019d1c: 60b9 str r1, [r7, #8]
8019d1e: 607a str r2, [r7, #4]
8019d20: 70fb strb r3, [r7, #3]
ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
u16_t optlen)
{
#endif /* IP_OPTIONS_SEND */
const ip4_addr_t *src_used = src;
8019d22: 68bb ldr r3, [r7, #8]
8019d24: 617b str r3, [r7, #20]
if (dest != LWIP_IP_HDRINCL) {
8019d26: 687b ldr r3, [r7, #4]
8019d28: 2b00 cmp r3, #0
8019d2a: d009 beq.n 8019d40 <ip4_output_if+0x2c>
if (ip4_addr_isany(src)) {
8019d2c: 68bb ldr r3, [r7, #8]
8019d2e: 2b00 cmp r3, #0
8019d30: d003 beq.n 8019d3a <ip4_output_if+0x26>
8019d32: 68bb ldr r3, [r7, #8]
8019d34: 681b ldr r3, [r3, #0]
8019d36: 2b00 cmp r3, #0
8019d38: d102 bne.n 8019d40 <ip4_output_if+0x2c>
src_used = netif_ip4_addr(netif);
8019d3a: 6abb ldr r3, [r7, #40] ; 0x28
8019d3c: 3304 adds r3, #4
8019d3e: 617b str r3, [r7, #20]
#if IP_OPTIONS_SEND
return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
ip_options, optlen);
#else /* IP_OPTIONS_SEND */
return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
8019d40: 78fa ldrb r2, [r7, #3]
8019d42: 6abb ldr r3, [r7, #40] ; 0x28
8019d44: 9302 str r3, [sp, #8]
8019d46: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
8019d4a: 9301 str r3, [sp, #4]
8019d4c: f897 3020 ldrb.w r3, [r7, #32]
8019d50: 9300 str r3, [sp, #0]
8019d52: 4613 mov r3, r2
8019d54: 687a ldr r2, [r7, #4]
8019d56: 6979 ldr r1, [r7, #20]
8019d58: 68f8 ldr r0, [r7, #12]
8019d5a: f000 f805 bl 8019d68 <ip4_output_if_src>
8019d5e: 4603 mov r3, r0
#endif /* IP_OPTIONS_SEND */
}
8019d60: 4618 mov r0, r3
8019d62: 3718 adds r7, #24
8019d64: 46bd mov sp, r7
8019d66: bd80 pop {r7, pc}
08019d68 <ip4_output_if_src>:
*/
err_t
ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019d68: b580 push {r7, lr}
8019d6a: b088 sub sp, #32
8019d6c: af00 add r7, sp, #0
8019d6e: 60f8 str r0, [r7, #12]
8019d70: 60b9 str r1, [r7, #8]
8019d72: 607a str r2, [r7, #4]
8019d74: 70fb strb r3, [r7, #3]
#if CHECKSUM_GEN_IP_INLINE
u32_t chk_sum = 0;
#endif /* CHECKSUM_GEN_IP_INLINE */
LWIP_ASSERT_CORE_LOCKED();
LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
8019d76: 68fb ldr r3, [r7, #12]
8019d78: 7b9b ldrb r3, [r3, #14]
8019d7a: 2b01 cmp r3, #1
8019d7c: d006 beq.n 8019d8c <ip4_output_if_src+0x24>
8019d7e: 4b4b ldr r3, [pc, #300] ; (8019eac <ip4_output_if_src+0x144>)
8019d80: f44f 7255 mov.w r2, #852 ; 0x354
8019d84: 494a ldr r1, [pc, #296] ; (8019eb0 <ip4_output_if_src+0x148>)
8019d86: 484b ldr r0, [pc, #300] ; (8019eb4 <ip4_output_if_src+0x14c>)
8019d88: f001 f944 bl 801b014 <iprintf>
MIB2_STATS_INC(mib2.ipoutrequests);
/* Should the IP header be generated or is it already included in p? */
if (dest != LWIP_IP_HDRINCL) {
8019d8c: 687b ldr r3, [r7, #4]
8019d8e: 2b00 cmp r3, #0
8019d90: d060 beq.n 8019e54 <ip4_output_if_src+0xec>
u16_t ip_hlen = IP_HLEN;
8019d92: 2314 movs r3, #20
8019d94: 837b strh r3, [r7, #26]
}
#endif /* CHECKSUM_GEN_IP_INLINE */
}
#endif /* IP_OPTIONS_SEND */
/* generate IP header */
if (pbuf_add_header(p, IP_HLEN)) {
8019d96: 2114 movs r1, #20
8019d98: 68f8 ldr r0, [r7, #12]
8019d9a: f7f6 fb8f bl 80104bc <pbuf_add_header>
8019d9e: 4603 mov r3, r0
8019da0: 2b00 cmp r3, #0
8019da2: d002 beq.n 8019daa <ip4_output_if_src+0x42>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019da4: f06f 0301 mvn.w r3, #1
8019da8: e07c b.n 8019ea4 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019daa: 68fb ldr r3, [r7, #12]
8019dac: 685b ldr r3, [r3, #4]
8019dae: 61fb str r3, [r7, #28]
LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
8019db0: 68fb ldr r3, [r7, #12]
8019db2: 895b ldrh r3, [r3, #10]
8019db4: 2b13 cmp r3, #19
8019db6: d806 bhi.n 8019dc6 <ip4_output_if_src+0x5e>
8019db8: 4b3c ldr r3, [pc, #240] ; (8019eac <ip4_output_if_src+0x144>)
8019dba: f240 3289 movw r2, #905 ; 0x389
8019dbe: 493e ldr r1, [pc, #248] ; (8019eb8 <ip4_output_if_src+0x150>)
8019dc0: 483c ldr r0, [pc, #240] ; (8019eb4 <ip4_output_if_src+0x14c>)
8019dc2: f001 f927 bl 801b014 <iprintf>
(p->len >= sizeof(struct ip_hdr)));
IPH_TTL_SET(iphdr, ttl);
8019dc6: 69fb ldr r3, [r7, #28]
8019dc8: 78fa ldrb r2, [r7, #3]
8019dca: 721a strb r2, [r3, #8]
IPH_PROTO_SET(iphdr, proto);
8019dcc: 69fb ldr r3, [r7, #28]
8019dce: f897 202c ldrb.w r2, [r7, #44] ; 0x2c
8019dd2: 725a strb r2, [r3, #9]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(proto | (ttl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
/* dest cannot be NULL here */
ip4_addr_copy(iphdr->dest, *dest);
8019dd4: 687b ldr r3, [r7, #4]
8019dd6: 681a ldr r2, [r3, #0]
8019dd8: 69fb ldr r3, [r7, #28]
8019dda: 611a str r2, [r3, #16]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
8019ddc: 8b7b ldrh r3, [r7, #26]
8019dde: 089b lsrs r3, r3, #2
8019de0: b29b uxth r3, r3
8019de2: b2db uxtb r3, r3
8019de4: f043 0340 orr.w r3, r3, #64 ; 0x40
8019de8: b2da uxtb r2, r3
8019dea: 69fb ldr r3, [r7, #28]
8019dec: 701a strb r2, [r3, #0]
IPH_TOS_SET(iphdr, tos);
8019dee: 69fb ldr r3, [r7, #28]
8019df0: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
8019df4: 705a strb r2, [r3, #1]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
8019df6: 68fb ldr r3, [r7, #12]
8019df8: 891b ldrh r3, [r3, #8]
8019dfa: 4618 mov r0, r3
8019dfc: f7f5 f840 bl 800ee80 <lwip_htons>
8019e00: 4603 mov r3, r0
8019e02: 461a mov r2, r3
8019e04: 69fb ldr r3, [r7, #28]
8019e06: 805a strh r2, [r3, #2]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_len;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_OFFSET_SET(iphdr, 0);
8019e08: 69fb ldr r3, [r7, #28]
8019e0a: 2200 movs r2, #0
8019e0c: 719a strb r2, [r3, #6]
8019e0e: 2200 movs r2, #0
8019e10: 71da strb r2, [r3, #7]
IPH_ID_SET(iphdr, lwip_htons(ip_id));
8019e12: 4b2a ldr r3, [pc, #168] ; (8019ebc <ip4_output_if_src+0x154>)
8019e14: 881b ldrh r3, [r3, #0]
8019e16: 4618 mov r0, r3
8019e18: f7f5 f832 bl 800ee80 <lwip_htons>
8019e1c: 4603 mov r3, r0
8019e1e: 461a mov r2, r3
8019e20: 69fb ldr r3, [r7, #28]
8019e22: 809a strh r2, [r3, #4]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_id;
#endif /* CHECKSUM_GEN_IP_INLINE */
++ip_id;
8019e24: 4b25 ldr r3, [pc, #148] ; (8019ebc <ip4_output_if_src+0x154>)
8019e26: 881b ldrh r3, [r3, #0]
8019e28: 3301 adds r3, #1
8019e2a: b29a uxth r2, r3
8019e2c: 4b23 ldr r3, [pc, #140] ; (8019ebc <ip4_output_if_src+0x154>)
8019e2e: 801a strh r2, [r3, #0]
if (src == NULL) {
8019e30: 68bb ldr r3, [r7, #8]
8019e32: 2b00 cmp r3, #0
8019e34: d104 bne.n 8019e40 <ip4_output_if_src+0xd8>
ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
8019e36: 4b22 ldr r3, [pc, #136] ; (8019ec0 <ip4_output_if_src+0x158>)
8019e38: 681a ldr r2, [r3, #0]
8019e3a: 69fb ldr r3, [r7, #28]
8019e3c: 60da str r2, [r3, #12]
8019e3e: e003 b.n 8019e48 <ip4_output_if_src+0xe0>
} else {
/* src cannot be NULL here */
ip4_addr_copy(iphdr->src, *src);
8019e40: 68bb ldr r3, [r7, #8]
8019e42: 681a ldr r2, [r3, #0]
8019e44: 69fb ldr r3, [r7, #28]
8019e46: 60da str r2, [r3, #12]
else {
IPH_CHKSUM_SET(iphdr, 0);
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
#else /* CHECKSUM_GEN_IP_INLINE */
IPH_CHKSUM_SET(iphdr, 0);
8019e48: 69fb ldr r3, [r7, #28]
8019e4a: 2200 movs r2, #0
8019e4c: 729a strb r2, [r3, #10]
8019e4e: 2200 movs r2, #0
8019e50: 72da strb r2, [r3, #11]
8019e52: e00f b.n 8019e74 <ip4_output_if_src+0x10c>
}
#endif /* CHECKSUM_GEN_IP */
#endif /* CHECKSUM_GEN_IP_INLINE */
} else {
/* IP header already included in p */
if (p->len < IP_HLEN) {
8019e54: 68fb ldr r3, [r7, #12]
8019e56: 895b ldrh r3, [r3, #10]
8019e58: 2b13 cmp r3, #19
8019e5a: d802 bhi.n 8019e62 <ip4_output_if_src+0xfa>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019e5c: f06f 0301 mvn.w r3, #1
8019e60: e020 b.n 8019ea4 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019e62: 68fb ldr r3, [r7, #12]
8019e64: 685b ldr r3, [r3, #4]
8019e66: 61fb str r3, [r7, #28]
ip4_addr_copy(dest_addr, iphdr->dest);
8019e68: 69fb ldr r3, [r7, #28]
8019e6a: 691b ldr r3, [r3, #16]
8019e6c: 617b str r3, [r7, #20]
dest = &dest_addr;
8019e6e: f107 0314 add.w r3, r7, #20
8019e72: 607b str r3, [r7, #4]
}
#endif /* LWIP_MULTICAST_TX_OPTIONS */
#endif /* ENABLE_LOOPBACK */
#if IP_FRAG
/* don't fragment if interface has mtu set to 0 [loopif] */
if (netif->mtu && (p->tot_len > netif->mtu)) {
8019e74: 6b3b ldr r3, [r7, #48] ; 0x30
8019e76: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e78: 2b00 cmp r3, #0
8019e7a: d00c beq.n 8019e96 <ip4_output_if_src+0x12e>
8019e7c: 68fb ldr r3, [r7, #12]
8019e7e: 891a ldrh r2, [r3, #8]
8019e80: 6b3b ldr r3, [r7, #48] ; 0x30
8019e82: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e84: 429a cmp r2, r3
8019e86: d906 bls.n 8019e96 <ip4_output_if_src+0x12e>
return ip4_frag(p, netif, dest);
8019e88: 687a ldr r2, [r7, #4]
8019e8a: 6b39 ldr r1, [r7, #48] ; 0x30
8019e8c: 68f8 ldr r0, [r7, #12]
8019e8e: f000 fd4b bl 801a928 <ip4_frag>
8019e92: 4603 mov r3, r0
8019e94: e006 b.n 8019ea4 <ip4_output_if_src+0x13c>
}
#endif /* IP_FRAG */
LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
return netif->output(netif, p, dest);
8019e96: 6b3b ldr r3, [r7, #48] ; 0x30
8019e98: 695b ldr r3, [r3, #20]
8019e9a: 687a ldr r2, [r7, #4]
8019e9c: 68f9 ldr r1, [r7, #12]
8019e9e: 6b38 ldr r0, [r7, #48] ; 0x30
8019ea0: 4798 blx r3
8019ea2: 4603 mov r3, r0
}
8019ea4: 4618 mov r0, r3
8019ea6: 3720 adds r7, #32
8019ea8: 46bd mov sp, r7
8019eaa: bd80 pop {r7, pc}
8019eac: 0801eaa8 .word 0x0801eaa8
8019eb0: 0801eadc .word 0x0801eadc
8019eb4: 0801eae8 .word 0x0801eae8
8019eb8: 0801eb10 .word 0x0801eb10
8019ebc: 2000886a .word 0x2000886a
8019ec0: 08020e68 .word 0x08020e68
08019ec4 <ip4_addr_isbroadcast_u32>:
* @param netif the network interface against which the address is checked
* @return returns non-zero if the address is a broadcast address
*/
u8_t
ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
{
8019ec4: b480 push {r7}
8019ec6: b085 sub sp, #20
8019ec8: af00 add r7, sp, #0
8019eca: 6078 str r0, [r7, #4]
8019ecc: 6039 str r1, [r7, #0]
ip4_addr_t ipaddr;
ip4_addr_set_u32(&ipaddr, addr);
8019ece: 687b ldr r3, [r7, #4]
8019ed0: 60fb str r3, [r7, #12]
/* all ones (broadcast) or all zeroes (old skool broadcast) */
if ((~addr == IPADDR_ANY) ||
8019ed2: 687b ldr r3, [r7, #4]
8019ed4: f1b3 3fff cmp.w r3, #4294967295
8019ed8: d002 beq.n 8019ee0 <ip4_addr_isbroadcast_u32+0x1c>
8019eda: 687b ldr r3, [r7, #4]
8019edc: 2b00 cmp r3, #0
8019ede: d101 bne.n 8019ee4 <ip4_addr_isbroadcast_u32+0x20>
(addr == IPADDR_ANY)) {
return 1;
8019ee0: 2301 movs r3, #1
8019ee2: e02a b.n 8019f3a <ip4_addr_isbroadcast_u32+0x76>
/* no broadcast support on this network interface? */
} else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
8019ee4: 683b ldr r3, [r7, #0]
8019ee6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019eea: f003 0302 and.w r3, r3, #2
8019eee: 2b00 cmp r3, #0
8019ef0: d101 bne.n 8019ef6 <ip4_addr_isbroadcast_u32+0x32>
/* the given address cannot be a broadcast address
* nor can we check against any broadcast addresses */
return 0;
8019ef2: 2300 movs r3, #0
8019ef4: e021 b.n 8019f3a <ip4_addr_isbroadcast_u32+0x76>
/* address matches network interface address exactly? => no broadcast */
} else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
8019ef6: 683b ldr r3, [r7, #0]
8019ef8: 3304 adds r3, #4
8019efa: 681b ldr r3, [r3, #0]
8019efc: 687a ldr r2, [r7, #4]
8019efe: 429a cmp r2, r3
8019f00: d101 bne.n 8019f06 <ip4_addr_isbroadcast_u32+0x42>
return 0;
8019f02: 2300 movs r3, #0
8019f04: e019 b.n 8019f3a <ip4_addr_isbroadcast_u32+0x76>
/* on the same (sub) network... */
} else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
8019f06: 68fa ldr r2, [r7, #12]
8019f08: 683b ldr r3, [r7, #0]
8019f0a: 3304 adds r3, #4
8019f0c: 681b ldr r3, [r3, #0]
8019f0e: 405a eors r2, r3
8019f10: 683b ldr r3, [r7, #0]
8019f12: 3308 adds r3, #8
8019f14: 681b ldr r3, [r3, #0]
8019f16: 4013 ands r3, r2
8019f18: 2b00 cmp r3, #0
8019f1a: d10d bne.n 8019f38 <ip4_addr_isbroadcast_u32+0x74>
/* ...and host identifier bits are all ones? =>... */
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019f1c: 683b ldr r3, [r7, #0]
8019f1e: 3308 adds r3, #8
8019f20: 681b ldr r3, [r3, #0]
8019f22: 43da mvns r2, r3
8019f24: 687b ldr r3, [r7, #4]
8019f26: 401a ands r2, r3
(IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
8019f28: 683b ldr r3, [r7, #0]
8019f2a: 3308 adds r3, #8
8019f2c: 681b ldr r3, [r3, #0]
8019f2e: 43db mvns r3, r3
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019f30: 429a cmp r2, r3
8019f32: d101 bne.n 8019f38 <ip4_addr_isbroadcast_u32+0x74>
/* => network broadcast address */
return 1;
8019f34: 2301 movs r3, #1
8019f36: e000 b.n 8019f3a <ip4_addr_isbroadcast_u32+0x76>
} else {
return 0;
8019f38: 2300 movs r3, #0
}
}
8019f3a: 4618 mov r0, r3
8019f3c: 3714 adds r7, #20
8019f3e: 46bd mov sp, r7
8019f40: f85d 7b04 ldr.w r7, [sp], #4
8019f44: 4770 bx lr
...
08019f48 <ip_reass_tmr>:
*
* Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
*/
void
ip_reass_tmr(void)
{
8019f48: b580 push {r7, lr}
8019f4a: b084 sub sp, #16
8019f4c: af00 add r7, sp, #0
struct ip_reassdata *r, *prev = NULL;
8019f4e: 2300 movs r3, #0
8019f50: 60bb str r3, [r7, #8]
r = reassdatagrams;
8019f52: 4b12 ldr r3, [pc, #72] ; (8019f9c <ip_reass_tmr+0x54>)
8019f54: 681b ldr r3, [r3, #0]
8019f56: 60fb str r3, [r7, #12]
while (r != NULL) {
8019f58: e018 b.n 8019f8c <ip_reass_tmr+0x44>
/* Decrement the timer. Once it reaches 0,
* clean up the incomplete fragment assembly */
if (r->timer > 0) {
8019f5a: 68fb ldr r3, [r7, #12]
8019f5c: 7fdb ldrb r3, [r3, #31]
8019f5e: 2b00 cmp r3, #0
8019f60: d00b beq.n 8019f7a <ip_reass_tmr+0x32>
r->timer--;
8019f62: 68fb ldr r3, [r7, #12]
8019f64: 7fdb ldrb r3, [r3, #31]
8019f66: 3b01 subs r3, #1
8019f68: b2da uxtb r2, r3
8019f6a: 68fb ldr r3, [r7, #12]
8019f6c: 77da strb r2, [r3, #31]
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
prev = r;
8019f6e: 68fb ldr r3, [r7, #12]
8019f70: 60bb str r3, [r7, #8]
r = r->next;
8019f72: 68fb ldr r3, [r7, #12]
8019f74: 681b ldr r3, [r3, #0]
8019f76: 60fb str r3, [r7, #12]
8019f78: e008 b.n 8019f8c <ip_reass_tmr+0x44>
} else {
/* reassembly timed out */
struct ip_reassdata *tmp;
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
tmp = r;
8019f7a: 68fb ldr r3, [r7, #12]
8019f7c: 607b str r3, [r7, #4]
/* get the next pointer before freeing */
r = r->next;
8019f7e: 68fb ldr r3, [r7, #12]
8019f80: 681b ldr r3, [r3, #0]
8019f82: 60fb str r3, [r7, #12]
/* free the helper struct and all enqueued pbufs */
ip_reass_free_complete_datagram(tmp, prev);
8019f84: 68b9 ldr r1, [r7, #8]
8019f86: 6878 ldr r0, [r7, #4]
8019f88: f000 f80a bl 8019fa0 <ip_reass_free_complete_datagram>
while (r != NULL) {
8019f8c: 68fb ldr r3, [r7, #12]
8019f8e: 2b00 cmp r3, #0
8019f90: d1e3 bne.n 8019f5a <ip_reass_tmr+0x12>
}
}
}
8019f92: bf00 nop
8019f94: 3710 adds r7, #16
8019f96: 46bd mov sp, r7
8019f98: bd80 pop {r7, pc}
8019f9a: bf00 nop
8019f9c: 2000886c .word 0x2000886c
08019fa0 <ip_reass_free_complete_datagram>:
* @param prev the previous datagram in the linked list
* @return the number of pbufs freed
*/
static int
ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
8019fa0: b580 push {r7, lr}
8019fa2: b088 sub sp, #32
8019fa4: af00 add r7, sp, #0
8019fa6: 6078 str r0, [r7, #4]
8019fa8: 6039 str r1, [r7, #0]
u16_t pbufs_freed = 0;
8019faa: 2300 movs r3, #0
8019fac: 83fb strh r3, [r7, #30]
u16_t clen;
struct pbuf *p;
struct ip_reass_helper *iprh;
LWIP_ASSERT("prev != ipr", prev != ipr);
8019fae: 683a ldr r2, [r7, #0]
8019fb0: 687b ldr r3, [r7, #4]
8019fb2: 429a cmp r2, r3
8019fb4: d105 bne.n 8019fc2 <ip_reass_free_complete_datagram+0x22>
8019fb6: 4b45 ldr r3, [pc, #276] ; (801a0cc <ip_reass_free_complete_datagram+0x12c>)
8019fb8: 22ab movs r2, #171 ; 0xab
8019fba: 4945 ldr r1, [pc, #276] ; (801a0d0 <ip_reass_free_complete_datagram+0x130>)
8019fbc: 4845 ldr r0, [pc, #276] ; (801a0d4 <ip_reass_free_complete_datagram+0x134>)
8019fbe: f001 f829 bl 801b014 <iprintf>
if (prev != NULL) {
8019fc2: 683b ldr r3, [r7, #0]
8019fc4: 2b00 cmp r3, #0
8019fc6: d00a beq.n 8019fde <ip_reass_free_complete_datagram+0x3e>
LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
8019fc8: 683b ldr r3, [r7, #0]
8019fca: 681b ldr r3, [r3, #0]
8019fcc: 687a ldr r2, [r7, #4]
8019fce: 429a cmp r2, r3
8019fd0: d005 beq.n 8019fde <ip_reass_free_complete_datagram+0x3e>
8019fd2: 4b3e ldr r3, [pc, #248] ; (801a0cc <ip_reass_free_complete_datagram+0x12c>)
8019fd4: 22ad movs r2, #173 ; 0xad
8019fd6: 4940 ldr r1, [pc, #256] ; (801a0d8 <ip_reass_free_complete_datagram+0x138>)
8019fd8: 483e ldr r0, [pc, #248] ; (801a0d4 <ip_reass_free_complete_datagram+0x134>)
8019fda: f001 f81b bl 801b014 <iprintf>
}
MIB2_STATS_INC(mib2.ipreasmfails);
#if LWIP_ICMP
iprh = (struct ip_reass_helper *)ipr->p->payload;
8019fde: 687b ldr r3, [r7, #4]
8019fe0: 685b ldr r3, [r3, #4]
8019fe2: 685b ldr r3, [r3, #4]
8019fe4: 617b str r3, [r7, #20]
if (iprh->start == 0) {
8019fe6: 697b ldr r3, [r7, #20]
8019fe8: 889b ldrh r3, [r3, #4]
8019fea: b29b uxth r3, r3
8019fec: 2b00 cmp r3, #0
8019fee: d12a bne.n 801a046 <ip_reass_free_complete_datagram+0xa6>
/* The first fragment was received, send ICMP time exceeded. */
/* First, de-queue the first pbuf from r->p. */
p = ipr->p;
8019ff0: 687b ldr r3, [r7, #4]
8019ff2: 685b ldr r3, [r3, #4]
8019ff4: 61bb str r3, [r7, #24]
ipr->p = iprh->next_pbuf;
8019ff6: 697b ldr r3, [r7, #20]
8019ff8: 681a ldr r2, [r3, #0]
8019ffa: 687b ldr r3, [r7, #4]
8019ffc: 605a str r2, [r3, #4]
/* Then, copy the original header into it. */
SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
8019ffe: 69bb ldr r3, [r7, #24]
801a000: 6858 ldr r0, [r3, #4]
801a002: 687b ldr r3, [r7, #4]
801a004: 3308 adds r3, #8
801a006: 2214 movs r2, #20
801a008: 4619 mov r1, r3
801a00a: f000 fff0 bl 801afee <memcpy>
icmp_time_exceeded(p, ICMP_TE_FRAG);
801a00e: 2101 movs r1, #1
801a010: 69b8 ldr r0, [r7, #24]
801a012: f7ff fc2b bl 801986c <icmp_time_exceeded>
clen = pbuf_clen(p);
801a016: 69b8 ldr r0, [r7, #24]
801a018: f7f6 fb74 bl 8010704 <pbuf_clen>
801a01c: 4603 mov r3, r0
801a01e: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
801a020: 8bfa ldrh r2, [r7, #30]
801a022: 8a7b ldrh r3, [r7, #18]
801a024: 4413 add r3, r2
801a026: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801a02a: db05 blt.n 801a038 <ip_reass_free_complete_datagram+0x98>
801a02c: 4b27 ldr r3, [pc, #156] ; (801a0cc <ip_reass_free_complete_datagram+0x12c>)
801a02e: 22bc movs r2, #188 ; 0xbc
801a030: 492a ldr r1, [pc, #168] ; (801a0dc <ip_reass_free_complete_datagram+0x13c>)
801a032: 4828 ldr r0, [pc, #160] ; (801a0d4 <ip_reass_free_complete_datagram+0x134>)
801a034: f000 ffee bl 801b014 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
801a038: 8bfa ldrh r2, [r7, #30]
801a03a: 8a7b ldrh r3, [r7, #18]
801a03c: 4413 add r3, r2
801a03e: 83fb strh r3, [r7, #30]
pbuf_free(p);
801a040: 69b8 ldr r0, [r7, #24]
801a042: f7f6 fad1 bl 80105e8 <pbuf_free>
}
#endif /* LWIP_ICMP */
/* First, free all received pbufs. The individual pbufs need to be released
separately as they have not yet been chained */
p = ipr->p;
801a046: 687b ldr r3, [r7, #4]
801a048: 685b ldr r3, [r3, #4]
801a04a: 61bb str r3, [r7, #24]
while (p != NULL) {
801a04c: e01f b.n 801a08e <ip_reass_free_complete_datagram+0xee>
struct pbuf *pcur;
iprh = (struct ip_reass_helper *)p->payload;
801a04e: 69bb ldr r3, [r7, #24]
801a050: 685b ldr r3, [r3, #4]
801a052: 617b str r3, [r7, #20]
pcur = p;
801a054: 69bb ldr r3, [r7, #24]
801a056: 60fb str r3, [r7, #12]
/* get the next pointer before freeing */
p = iprh->next_pbuf;
801a058: 697b ldr r3, [r7, #20]
801a05a: 681b ldr r3, [r3, #0]
801a05c: 61bb str r3, [r7, #24]
clen = pbuf_clen(pcur);
801a05e: 68f8 ldr r0, [r7, #12]
801a060: f7f6 fb50 bl 8010704 <pbuf_clen>
801a064: 4603 mov r3, r0
801a066: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
801a068: 8bfa ldrh r2, [r7, #30]
801a06a: 8a7b ldrh r3, [r7, #18]
801a06c: 4413 add r3, r2
801a06e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801a072: db05 blt.n 801a080 <ip_reass_free_complete_datagram+0xe0>
801a074: 4b15 ldr r3, [pc, #84] ; (801a0cc <ip_reass_free_complete_datagram+0x12c>)
801a076: 22cc movs r2, #204 ; 0xcc
801a078: 4918 ldr r1, [pc, #96] ; (801a0dc <ip_reass_free_complete_datagram+0x13c>)
801a07a: 4816 ldr r0, [pc, #88] ; (801a0d4 <ip_reass_free_complete_datagram+0x134>)
801a07c: f000 ffca bl 801b014 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
801a080: 8bfa ldrh r2, [r7, #30]
801a082: 8a7b ldrh r3, [r7, #18]
801a084: 4413 add r3, r2
801a086: 83fb strh r3, [r7, #30]
pbuf_free(pcur);
801a088: 68f8 ldr r0, [r7, #12]
801a08a: f7f6 faad bl 80105e8 <pbuf_free>
while (p != NULL) {
801a08e: 69bb ldr r3, [r7, #24]
801a090: 2b00 cmp r3, #0
801a092: d1dc bne.n 801a04e <ip_reass_free_complete_datagram+0xae>
}
/* Then, unchain the struct ip_reassdata from the list and free it. */
ip_reass_dequeue_datagram(ipr, prev);
801a094: 6839 ldr r1, [r7, #0]
801a096: 6878 ldr r0, [r7, #4]
801a098: f000 f8c2 bl 801a220 <ip_reass_dequeue_datagram>
LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
801a09c: 4b10 ldr r3, [pc, #64] ; (801a0e0 <ip_reass_free_complete_datagram+0x140>)
801a09e: 881b ldrh r3, [r3, #0]
801a0a0: 8bfa ldrh r2, [r7, #30]
801a0a2: 429a cmp r2, r3
801a0a4: d905 bls.n 801a0b2 <ip_reass_free_complete_datagram+0x112>
801a0a6: 4b09 ldr r3, [pc, #36] ; (801a0cc <ip_reass_free_complete_datagram+0x12c>)
801a0a8: 22d2 movs r2, #210 ; 0xd2
801a0aa: 490e ldr r1, [pc, #56] ; (801a0e4 <ip_reass_free_complete_datagram+0x144>)
801a0ac: 4809 ldr r0, [pc, #36] ; (801a0d4 <ip_reass_free_complete_datagram+0x134>)
801a0ae: f000 ffb1 bl 801b014 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
801a0b2: 4b0b ldr r3, [pc, #44] ; (801a0e0 <ip_reass_free_complete_datagram+0x140>)
801a0b4: 881a ldrh r2, [r3, #0]
801a0b6: 8bfb ldrh r3, [r7, #30]
801a0b8: 1ad3 subs r3, r2, r3
801a0ba: b29a uxth r2, r3
801a0bc: 4b08 ldr r3, [pc, #32] ; (801a0e0 <ip_reass_free_complete_datagram+0x140>)
801a0be: 801a strh r2, [r3, #0]
return pbufs_freed;
801a0c0: 8bfb ldrh r3, [r7, #30]
}
801a0c2: 4618 mov r0, r3
801a0c4: 3720 adds r7, #32
801a0c6: 46bd mov sp, r7
801a0c8: bd80 pop {r7, pc}
801a0ca: bf00 nop
801a0cc: 0801eb40 .word 0x0801eb40
801a0d0: 0801eb7c .word 0x0801eb7c
801a0d4: 0801eb88 .word 0x0801eb88
801a0d8: 0801ebb0 .word 0x0801ebb0
801a0dc: 0801ebc4 .word 0x0801ebc4
801a0e0: 20008870 .word 0x20008870
801a0e4: 0801ebe4 .word 0x0801ebe4
0801a0e8 <ip_reass_remove_oldest_datagram>:
* (used for freeing other datagrams if not enough space)
* @return the number of pbufs freed
*/
static int
ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
{
801a0e8: b580 push {r7, lr}
801a0ea: b08a sub sp, #40 ; 0x28
801a0ec: af00 add r7, sp, #0
801a0ee: 6078 str r0, [r7, #4]
801a0f0: 6039 str r1, [r7, #0]
/* @todo Can't we simply remove the last datagram in the
* linked list behind reassdatagrams?
*/
struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
int pbufs_freed = 0, pbufs_freed_current;
801a0f2: 2300 movs r3, #0
801a0f4: 617b str r3, [r7, #20]
int other_datagrams;
/* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
* but don't free the datagram that 'fraghdr' belongs to! */
do {
oldest = NULL;
801a0f6: 2300 movs r3, #0
801a0f8: 623b str r3, [r7, #32]
prev = NULL;
801a0fa: 2300 movs r3, #0
801a0fc: 61fb str r3, [r7, #28]
oldest_prev = NULL;
801a0fe: 2300 movs r3, #0
801a100: 61bb str r3, [r7, #24]
other_datagrams = 0;
801a102: 2300 movs r3, #0
801a104: 613b str r3, [r7, #16]
r = reassdatagrams;
801a106: 4b28 ldr r3, [pc, #160] ; (801a1a8 <ip_reass_remove_oldest_datagram+0xc0>)
801a108: 681b ldr r3, [r3, #0]
801a10a: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a10c: e030 b.n 801a170 <ip_reass_remove_oldest_datagram+0x88>
if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
801a10e: 6a7b ldr r3, [r7, #36] ; 0x24
801a110: 695a ldr r2, [r3, #20]
801a112: 687b ldr r3, [r7, #4]
801a114: 68db ldr r3, [r3, #12]
801a116: 429a cmp r2, r3
801a118: d10c bne.n 801a134 <ip_reass_remove_oldest_datagram+0x4c>
801a11a: 6a7b ldr r3, [r7, #36] ; 0x24
801a11c: 699a ldr r2, [r3, #24]
801a11e: 687b ldr r3, [r7, #4]
801a120: 691b ldr r3, [r3, #16]
801a122: 429a cmp r2, r3
801a124: d106 bne.n 801a134 <ip_reass_remove_oldest_datagram+0x4c>
801a126: 6a7b ldr r3, [r7, #36] ; 0x24
801a128: 899a ldrh r2, [r3, #12]
801a12a: 687b ldr r3, [r7, #4]
801a12c: 889b ldrh r3, [r3, #4]
801a12e: b29b uxth r3, r3
801a130: 429a cmp r2, r3
801a132: d014 beq.n 801a15e <ip_reass_remove_oldest_datagram+0x76>
/* Not the same datagram as fraghdr */
other_datagrams++;
801a134: 693b ldr r3, [r7, #16]
801a136: 3301 adds r3, #1
801a138: 613b str r3, [r7, #16]
if (oldest == NULL) {
801a13a: 6a3b ldr r3, [r7, #32]
801a13c: 2b00 cmp r3, #0
801a13e: d104 bne.n 801a14a <ip_reass_remove_oldest_datagram+0x62>
oldest = r;
801a140: 6a7b ldr r3, [r7, #36] ; 0x24
801a142: 623b str r3, [r7, #32]
oldest_prev = prev;
801a144: 69fb ldr r3, [r7, #28]
801a146: 61bb str r3, [r7, #24]
801a148: e009 b.n 801a15e <ip_reass_remove_oldest_datagram+0x76>
} else if (r->timer <= oldest->timer) {
801a14a: 6a7b ldr r3, [r7, #36] ; 0x24
801a14c: 7fda ldrb r2, [r3, #31]
801a14e: 6a3b ldr r3, [r7, #32]
801a150: 7fdb ldrb r3, [r3, #31]
801a152: 429a cmp r2, r3
801a154: d803 bhi.n 801a15e <ip_reass_remove_oldest_datagram+0x76>
/* older than the previous oldest */
oldest = r;
801a156: 6a7b ldr r3, [r7, #36] ; 0x24
801a158: 623b str r3, [r7, #32]
oldest_prev = prev;
801a15a: 69fb ldr r3, [r7, #28]
801a15c: 61bb str r3, [r7, #24]
}
}
if (r->next != NULL) {
801a15e: 6a7b ldr r3, [r7, #36] ; 0x24
801a160: 681b ldr r3, [r3, #0]
801a162: 2b00 cmp r3, #0
801a164: d001 beq.n 801a16a <ip_reass_remove_oldest_datagram+0x82>
prev = r;
801a166: 6a7b ldr r3, [r7, #36] ; 0x24
801a168: 61fb str r3, [r7, #28]
}
r = r->next;
801a16a: 6a7b ldr r3, [r7, #36] ; 0x24
801a16c: 681b ldr r3, [r3, #0]
801a16e: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a170: 6a7b ldr r3, [r7, #36] ; 0x24
801a172: 2b00 cmp r3, #0
801a174: d1cb bne.n 801a10e <ip_reass_remove_oldest_datagram+0x26>
}
if (oldest != NULL) {
801a176: 6a3b ldr r3, [r7, #32]
801a178: 2b00 cmp r3, #0
801a17a: d008 beq.n 801a18e <ip_reass_remove_oldest_datagram+0xa6>
pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
801a17c: 69b9 ldr r1, [r7, #24]
801a17e: 6a38 ldr r0, [r7, #32]
801a180: f7ff ff0e bl 8019fa0 <ip_reass_free_complete_datagram>
801a184: 60f8 str r0, [r7, #12]
pbufs_freed += pbufs_freed_current;
801a186: 697a ldr r2, [r7, #20]
801a188: 68fb ldr r3, [r7, #12]
801a18a: 4413 add r3, r2
801a18c: 617b str r3, [r7, #20]
}
} while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
801a18e: 697a ldr r2, [r7, #20]
801a190: 683b ldr r3, [r7, #0]
801a192: 429a cmp r2, r3
801a194: da02 bge.n 801a19c <ip_reass_remove_oldest_datagram+0xb4>
801a196: 693b ldr r3, [r7, #16]
801a198: 2b01 cmp r3, #1
801a19a: dcac bgt.n 801a0f6 <ip_reass_remove_oldest_datagram+0xe>
return pbufs_freed;
801a19c: 697b ldr r3, [r7, #20]
}
801a19e: 4618 mov r0, r3
801a1a0: 3728 adds r7, #40 ; 0x28
801a1a2: 46bd mov sp, r7
801a1a4: bd80 pop {r7, pc}
801a1a6: bf00 nop
801a1a8: 2000886c .word 0x2000886c
0801a1ac <ip_reass_enqueue_new_datagram>:
* @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
* @return A pointer to the queue location into which the fragment was enqueued
*/
static struct ip_reassdata *
ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
{
801a1ac: b580 push {r7, lr}
801a1ae: b084 sub sp, #16
801a1b0: af00 add r7, sp, #0
801a1b2: 6078 str r0, [r7, #4]
801a1b4: 6039 str r1, [r7, #0]
#if ! IP_REASS_FREE_OLDEST
LWIP_UNUSED_ARG(clen);
#endif
/* No matching previous fragment found, allocate a new reassdata struct */
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a1b6: 2004 movs r0, #4
801a1b8: f7f5 fb18 bl 800f7ec <memp_malloc>
801a1bc: 60f8 str r0, [r7, #12]
if (ipr == NULL) {
801a1be: 68fb ldr r3, [r7, #12]
801a1c0: 2b00 cmp r3, #0
801a1c2: d110 bne.n 801a1e6 <ip_reass_enqueue_new_datagram+0x3a>
#if IP_REASS_FREE_OLDEST
if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
801a1c4: 6839 ldr r1, [r7, #0]
801a1c6: 6878 ldr r0, [r7, #4]
801a1c8: f7ff ff8e bl 801a0e8 <ip_reass_remove_oldest_datagram>
801a1cc: 4602 mov r2, r0
801a1ce: 683b ldr r3, [r7, #0]
801a1d0: 4293 cmp r3, r2
801a1d2: dc03 bgt.n 801a1dc <ip_reass_enqueue_new_datagram+0x30>
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a1d4: 2004 movs r0, #4
801a1d6: f7f5 fb09 bl 800f7ec <memp_malloc>
801a1da: 60f8 str r0, [r7, #12]
}
if (ipr == NULL)
801a1dc: 68fb ldr r3, [r7, #12]
801a1de: 2b00 cmp r3, #0
801a1e0: d101 bne.n 801a1e6 <ip_reass_enqueue_new_datagram+0x3a>
#endif /* IP_REASS_FREE_OLDEST */
{
IPFRAG_STATS_INC(ip_frag.memerr);
LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
return NULL;
801a1e2: 2300 movs r3, #0
801a1e4: e016 b.n 801a214 <ip_reass_enqueue_new_datagram+0x68>
}
}
memset(ipr, 0, sizeof(struct ip_reassdata));
801a1e6: 2220 movs r2, #32
801a1e8: 2100 movs r1, #0
801a1ea: 68f8 ldr r0, [r7, #12]
801a1ec: f000 ff0a bl 801b004 <memset>
ipr->timer = IP_REASS_MAXAGE;
801a1f0: 68fb ldr r3, [r7, #12]
801a1f2: 220f movs r2, #15
801a1f4: 77da strb r2, [r3, #31]
/* enqueue the new structure to the front of the list */
ipr->next = reassdatagrams;
801a1f6: 4b09 ldr r3, [pc, #36] ; (801a21c <ip_reass_enqueue_new_datagram+0x70>)
801a1f8: 681a ldr r2, [r3, #0]
801a1fa: 68fb ldr r3, [r7, #12]
801a1fc: 601a str r2, [r3, #0]
reassdatagrams = ipr;
801a1fe: 4a07 ldr r2, [pc, #28] ; (801a21c <ip_reass_enqueue_new_datagram+0x70>)
801a200: 68fb ldr r3, [r7, #12]
801a202: 6013 str r3, [r2, #0]
/* copy the ip header for later tests and input */
/* @todo: no ip options supported? */
SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
801a204: 68fb ldr r3, [r7, #12]
801a206: 3308 adds r3, #8
801a208: 2214 movs r2, #20
801a20a: 6879 ldr r1, [r7, #4]
801a20c: 4618 mov r0, r3
801a20e: f000 feee bl 801afee <memcpy>
return ipr;
801a212: 68fb ldr r3, [r7, #12]
}
801a214: 4618 mov r0, r3
801a216: 3710 adds r7, #16
801a218: 46bd mov sp, r7
801a21a: bd80 pop {r7, pc}
801a21c: 2000886c .word 0x2000886c
0801a220 <ip_reass_dequeue_datagram>:
* Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
* @param ipr points to the queue entry to dequeue
*/
static void
ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
801a220: b580 push {r7, lr}
801a222: b082 sub sp, #8
801a224: af00 add r7, sp, #0
801a226: 6078 str r0, [r7, #4]
801a228: 6039 str r1, [r7, #0]
/* dequeue the reass struct */
if (reassdatagrams == ipr) {
801a22a: 4b10 ldr r3, [pc, #64] ; (801a26c <ip_reass_dequeue_datagram+0x4c>)
801a22c: 681b ldr r3, [r3, #0]
801a22e: 687a ldr r2, [r7, #4]
801a230: 429a cmp r2, r3
801a232: d104 bne.n 801a23e <ip_reass_dequeue_datagram+0x1e>
/* it was the first in the list */
reassdatagrams = ipr->next;
801a234: 687b ldr r3, [r7, #4]
801a236: 681b ldr r3, [r3, #0]
801a238: 4a0c ldr r2, [pc, #48] ; (801a26c <ip_reass_dequeue_datagram+0x4c>)
801a23a: 6013 str r3, [r2, #0]
801a23c: e00d b.n 801a25a <ip_reass_dequeue_datagram+0x3a>
} else {
/* it wasn't the first, so it must have a valid 'prev' */
LWIP_ASSERT("sanity check linked list", prev != NULL);
801a23e: 683b ldr r3, [r7, #0]
801a240: 2b00 cmp r3, #0
801a242: d106 bne.n 801a252 <ip_reass_dequeue_datagram+0x32>
801a244: 4b0a ldr r3, [pc, #40] ; (801a270 <ip_reass_dequeue_datagram+0x50>)
801a246: f240 1245 movw r2, #325 ; 0x145
801a24a: 490a ldr r1, [pc, #40] ; (801a274 <ip_reass_dequeue_datagram+0x54>)
801a24c: 480a ldr r0, [pc, #40] ; (801a278 <ip_reass_dequeue_datagram+0x58>)
801a24e: f000 fee1 bl 801b014 <iprintf>
prev->next = ipr->next;
801a252: 687b ldr r3, [r7, #4]
801a254: 681a ldr r2, [r3, #0]
801a256: 683b ldr r3, [r7, #0]
801a258: 601a str r2, [r3, #0]
}
/* now we can free the ip_reassdata struct */
memp_free(MEMP_REASSDATA, ipr);
801a25a: 6879 ldr r1, [r7, #4]
801a25c: 2004 movs r0, #4
801a25e: f7f5 fb17 bl 800f890 <memp_free>
}
801a262: bf00 nop
801a264: 3708 adds r7, #8
801a266: 46bd mov sp, r7
801a268: bd80 pop {r7, pc}
801a26a: bf00 nop
801a26c: 2000886c .word 0x2000886c
801a270: 0801eb40 .word 0x0801eb40
801a274: 0801ec08 .word 0x0801ec08
801a278: 0801eb88 .word 0x0801eb88
0801a27c <ip_reass_chain_frag_into_datagram_and_validate>:
* @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
* @return see IP_REASS_VALIDATE_* defines
*/
static int
ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
{
801a27c: b580 push {r7, lr}
801a27e: b08c sub sp, #48 ; 0x30
801a280: af00 add r7, sp, #0
801a282: 60f8 str r0, [r7, #12]
801a284: 60b9 str r1, [r7, #8]
801a286: 607a str r2, [r7, #4]
struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
801a288: 2300 movs r3, #0
801a28a: 62bb str r3, [r7, #40] ; 0x28
struct pbuf *q;
u16_t offset, len;
u8_t hlen;
struct ip_hdr *fraghdr;
int valid = 1;
801a28c: 2301 movs r3, #1
801a28e: 623b str r3, [r7, #32]
/* Extract length and fragment offset from current fragment */
fraghdr = (struct ip_hdr *)new_p->payload;
801a290: 68bb ldr r3, [r7, #8]
801a292: 685b ldr r3, [r3, #4]
801a294: 61fb str r3, [r7, #28]
len = lwip_ntohs(IPH_LEN(fraghdr));
801a296: 69fb ldr r3, [r7, #28]
801a298: 885b ldrh r3, [r3, #2]
801a29a: b29b uxth r3, r3
801a29c: 4618 mov r0, r3
801a29e: f7f4 fdef bl 800ee80 <lwip_htons>
801a2a2: 4603 mov r3, r0
801a2a4: 837b strh r3, [r7, #26]
hlen = IPH_HL_BYTES(fraghdr);
801a2a6: 69fb ldr r3, [r7, #28]
801a2a8: 781b ldrb r3, [r3, #0]
801a2aa: f003 030f and.w r3, r3, #15
801a2ae: b2db uxtb r3, r3
801a2b0: 009b lsls r3, r3, #2
801a2b2: 767b strb r3, [r7, #25]
if (hlen > len) {
801a2b4: 7e7b ldrb r3, [r7, #25]
801a2b6: b29b uxth r3, r3
801a2b8: 8b7a ldrh r2, [r7, #26]
801a2ba: 429a cmp r2, r3
801a2bc: d202 bcs.n 801a2c4 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
/* invalid datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a2be: f04f 33ff mov.w r3, #4294967295
801a2c2: e135 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
len = (u16_t)(len - hlen);
801a2c4: 7e7b ldrb r3, [r7, #25]
801a2c6: b29b uxth r3, r3
801a2c8: 8b7a ldrh r2, [r7, #26]
801a2ca: 1ad3 subs r3, r2, r3
801a2cc: 837b strh r3, [r7, #26]
offset = IPH_OFFSET_BYTES(fraghdr);
801a2ce: 69fb ldr r3, [r7, #28]
801a2d0: 88db ldrh r3, [r3, #6]
801a2d2: b29b uxth r3, r3
801a2d4: 4618 mov r0, r3
801a2d6: f7f4 fdd3 bl 800ee80 <lwip_htons>
801a2da: 4603 mov r3, r0
801a2dc: f3c3 030c ubfx r3, r3, #0, #13
801a2e0: b29b uxth r3, r3
801a2e2: 00db lsls r3, r3, #3
801a2e4: 82fb strh r3, [r7, #22]
/* overwrite the fragment's ip header from the pbuf with our helper struct,
* and setup the embedded helper structure. */
/* make sure the struct ip_reass_helper fits into the IP header */
LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
sizeof(struct ip_reass_helper) <= IP_HLEN);
iprh = (struct ip_reass_helper *)new_p->payload;
801a2e6: 68bb ldr r3, [r7, #8]
801a2e8: 685b ldr r3, [r3, #4]
801a2ea: 62fb str r3, [r7, #44] ; 0x2c
iprh->next_pbuf = NULL;
801a2ec: 6afb ldr r3, [r7, #44] ; 0x2c
801a2ee: 2200 movs r2, #0
801a2f0: 701a strb r2, [r3, #0]
801a2f2: 2200 movs r2, #0
801a2f4: 705a strb r2, [r3, #1]
801a2f6: 2200 movs r2, #0
801a2f8: 709a strb r2, [r3, #2]
801a2fa: 2200 movs r2, #0
801a2fc: 70da strb r2, [r3, #3]
iprh->start = offset;
801a2fe: 6afb ldr r3, [r7, #44] ; 0x2c
801a300: 8afa ldrh r2, [r7, #22]
801a302: 809a strh r2, [r3, #4]
iprh->end = (u16_t)(offset + len);
801a304: 8afa ldrh r2, [r7, #22]
801a306: 8b7b ldrh r3, [r7, #26]
801a308: 4413 add r3, r2
801a30a: b29a uxth r2, r3
801a30c: 6afb ldr r3, [r7, #44] ; 0x2c
801a30e: 80da strh r2, [r3, #6]
if (iprh->end < offset) {
801a310: 6afb ldr r3, [r7, #44] ; 0x2c
801a312: 88db ldrh r3, [r3, #6]
801a314: b29b uxth r3, r3
801a316: 8afa ldrh r2, [r7, #22]
801a318: 429a cmp r2, r3
801a31a: d902 bls.n 801a322 <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
/* u16_t overflow, cannot handle this */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a31c: f04f 33ff mov.w r3, #4294967295
801a320: e106 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* Iterate through until we either get to the end of the list (append),
* or we find one with a larger offset (insert). */
for (q = ipr->p; q != NULL;) {
801a322: 68fb ldr r3, [r7, #12]
801a324: 685b ldr r3, [r3, #4]
801a326: 627b str r3, [r7, #36] ; 0x24
801a328: e068 b.n 801a3fc <ip_reass_chain_frag_into_datagram_and_validate+0x180>
iprh_tmp = (struct ip_reass_helper *)q->payload;
801a32a: 6a7b ldr r3, [r7, #36] ; 0x24
801a32c: 685b ldr r3, [r3, #4]
801a32e: 613b str r3, [r7, #16]
if (iprh->start < iprh_tmp->start) {
801a330: 6afb ldr r3, [r7, #44] ; 0x2c
801a332: 889b ldrh r3, [r3, #4]
801a334: b29a uxth r2, r3
801a336: 693b ldr r3, [r7, #16]
801a338: 889b ldrh r3, [r3, #4]
801a33a: b29b uxth r3, r3
801a33c: 429a cmp r2, r3
801a33e: d235 bcs.n 801a3ac <ip_reass_chain_frag_into_datagram_and_validate+0x130>
/* the new pbuf should be inserted before this */
iprh->next_pbuf = q;
801a340: 6afb ldr r3, [r7, #44] ; 0x2c
801a342: 6a7a ldr r2, [r7, #36] ; 0x24
801a344: 601a str r2, [r3, #0]
if (iprh_prev != NULL) {
801a346: 6abb ldr r3, [r7, #40] ; 0x28
801a348: 2b00 cmp r3, #0
801a34a: d020 beq.n 801a38e <ip_reass_chain_frag_into_datagram_and_validate+0x112>
/* not the fragment with the lowest offset */
#if IP_REASS_CHECK_OVERLAP
if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
801a34c: 6afb ldr r3, [r7, #44] ; 0x2c
801a34e: 889b ldrh r3, [r3, #4]
801a350: b29a uxth r2, r3
801a352: 6abb ldr r3, [r7, #40] ; 0x28
801a354: 88db ldrh r3, [r3, #6]
801a356: b29b uxth r3, r3
801a358: 429a cmp r2, r3
801a35a: d307 bcc.n 801a36c <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
801a35c: 6afb ldr r3, [r7, #44] ; 0x2c
801a35e: 88db ldrh r3, [r3, #6]
801a360: b29a uxth r2, r3
801a362: 693b ldr r3, [r7, #16]
801a364: 889b ldrh r3, [r3, #4]
801a366: b29b uxth r3, r3
801a368: 429a cmp r2, r3
801a36a: d902 bls.n 801a372 <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
/* fragment overlaps with previous or following, throw away */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a36c: f04f 33ff mov.w r3, #4294967295
801a370: e0de b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a372: 6abb ldr r3, [r7, #40] ; 0x28
801a374: 68ba ldr r2, [r7, #8]
801a376: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a378: 6abb ldr r3, [r7, #40] ; 0x28
801a37a: 88db ldrh r3, [r3, #6]
801a37c: b29a uxth r2, r3
801a37e: 6afb ldr r3, [r7, #44] ; 0x2c
801a380: 889b ldrh r3, [r3, #4]
801a382: b29b uxth r3, r3
801a384: 429a cmp r2, r3
801a386: d03d beq.n 801a404 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a388: 2300 movs r3, #0
801a38a: 623b str r3, [r7, #32]
}
#endif /* IP_REASS_CHECK_OVERLAP */
/* fragment with the lowest offset */
ipr->p = new_p;
}
break;
801a38c: e03a b.n 801a404 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
if (iprh->end > iprh_tmp->start) {
801a38e: 6afb ldr r3, [r7, #44] ; 0x2c
801a390: 88db ldrh r3, [r3, #6]
801a392: b29a uxth r2, r3
801a394: 693b ldr r3, [r7, #16]
801a396: 889b ldrh r3, [r3, #4]
801a398: b29b uxth r3, r3
801a39a: 429a cmp r2, r3
801a39c: d902 bls.n 801a3a4 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a39e: f04f 33ff mov.w r3, #4294967295
801a3a2: e0c5 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
ipr->p = new_p;
801a3a4: 68fb ldr r3, [r7, #12]
801a3a6: 68ba ldr r2, [r7, #8]
801a3a8: 605a str r2, [r3, #4]
break;
801a3aa: e02b b.n 801a404 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
} else if (iprh->start == iprh_tmp->start) {
801a3ac: 6afb ldr r3, [r7, #44] ; 0x2c
801a3ae: 889b ldrh r3, [r3, #4]
801a3b0: b29a uxth r2, r3
801a3b2: 693b ldr r3, [r7, #16]
801a3b4: 889b ldrh r3, [r3, #4]
801a3b6: b29b uxth r3, r3
801a3b8: 429a cmp r2, r3
801a3ba: d102 bne.n 801a3c2 <ip_reass_chain_frag_into_datagram_and_validate+0x146>
/* received the same datagram twice: no need to keep the datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a3bc: f04f 33ff mov.w r3, #4294967295
801a3c0: e0b6 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#if IP_REASS_CHECK_OVERLAP
} else if (iprh->start < iprh_tmp->end) {
801a3c2: 6afb ldr r3, [r7, #44] ; 0x2c
801a3c4: 889b ldrh r3, [r3, #4]
801a3c6: b29a uxth r2, r3
801a3c8: 693b ldr r3, [r7, #16]
801a3ca: 88db ldrh r3, [r3, #6]
801a3cc: b29b uxth r3, r3
801a3ce: 429a cmp r2, r3
801a3d0: d202 bcs.n 801a3d8 <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
/* overlap: no need to keep the new datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a3d2: f04f 33ff mov.w r3, #4294967295
801a3d6: e0ab b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#endif /* IP_REASS_CHECK_OVERLAP */
} else {
/* Check if the fragments received so far have no holes. */
if (iprh_prev != NULL) {
801a3d8: 6abb ldr r3, [r7, #40] ; 0x28
801a3da: 2b00 cmp r3, #0
801a3dc: d009 beq.n 801a3f2 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
if (iprh_prev->end != iprh_tmp->start) {
801a3de: 6abb ldr r3, [r7, #40] ; 0x28
801a3e0: 88db ldrh r3, [r3, #6]
801a3e2: b29a uxth r2, r3
801a3e4: 693b ldr r3, [r7, #16]
801a3e6: 889b ldrh r3, [r3, #4]
801a3e8: b29b uxth r3, r3
801a3ea: 429a cmp r2, r3
801a3ec: d001 beq.n 801a3f2 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a3ee: 2300 movs r3, #0
801a3f0: 623b str r3, [r7, #32]
}
}
}
q = iprh_tmp->next_pbuf;
801a3f2: 693b ldr r3, [r7, #16]
801a3f4: 681b ldr r3, [r3, #0]
801a3f6: 627b str r3, [r7, #36] ; 0x24
iprh_prev = iprh_tmp;
801a3f8: 693b ldr r3, [r7, #16]
801a3fa: 62bb str r3, [r7, #40] ; 0x28
for (q = ipr->p; q != NULL;) {
801a3fc: 6a7b ldr r3, [r7, #36] ; 0x24
801a3fe: 2b00 cmp r3, #0
801a400: d193 bne.n 801a32a <ip_reass_chain_frag_into_datagram_and_validate+0xae>
801a402: e000 b.n 801a406 <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
break;
801a404: bf00 nop
}
/* If q is NULL, then we made it to the end of the list. Determine what to do now */
if (q == NULL) {
801a406: 6a7b ldr r3, [r7, #36] ; 0x24
801a408: 2b00 cmp r3, #0
801a40a: d12d bne.n 801a468 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
if (iprh_prev != NULL) {
801a40c: 6abb ldr r3, [r7, #40] ; 0x28
801a40e: 2b00 cmp r3, #0
801a410: d01c beq.n 801a44c <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
/* this is (for now), the fragment with the highest offset:
* chain it to the last fragment */
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
801a412: 6abb ldr r3, [r7, #40] ; 0x28
801a414: 88db ldrh r3, [r3, #6]
801a416: b29a uxth r2, r3
801a418: 6afb ldr r3, [r7, #44] ; 0x2c
801a41a: 889b ldrh r3, [r3, #4]
801a41c: b29b uxth r3, r3
801a41e: 429a cmp r2, r3
801a420: d906 bls.n 801a430 <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
801a422: 4b45 ldr r3, [pc, #276] ; (801a538 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a424: f44f 72db mov.w r2, #438 ; 0x1b6
801a428: 4944 ldr r1, [pc, #272] ; (801a53c <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
801a42a: 4845 ldr r0, [pc, #276] ; (801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a42c: f000 fdf2 bl 801b014 <iprintf>
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a430: 6abb ldr r3, [r7, #40] ; 0x28
801a432: 68ba ldr r2, [r7, #8]
801a434: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a436: 6abb ldr r3, [r7, #40] ; 0x28
801a438: 88db ldrh r3, [r3, #6]
801a43a: b29a uxth r2, r3
801a43c: 6afb ldr r3, [r7, #44] ; 0x2c
801a43e: 889b ldrh r3, [r3, #4]
801a440: b29b uxth r3, r3
801a442: 429a cmp r2, r3
801a444: d010 beq.n 801a468 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
valid = 0;
801a446: 2300 movs r3, #0
801a448: 623b str r3, [r7, #32]
801a44a: e00d b.n 801a468 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
}
} else {
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("no previous fragment, this must be the first fragment!",
801a44c: 68fb ldr r3, [r7, #12]
801a44e: 685b ldr r3, [r3, #4]
801a450: 2b00 cmp r3, #0
801a452: d006 beq.n 801a462 <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
801a454: 4b38 ldr r3, [pc, #224] ; (801a538 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a456: f240 12bf movw r2, #447 ; 0x1bf
801a45a: 493a ldr r1, [pc, #232] ; (801a544 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
801a45c: 4838 ldr r0, [pc, #224] ; (801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a45e: f000 fdd9 bl 801b014 <iprintf>
ipr->p == NULL);
#endif /* IP_REASS_CHECK_OVERLAP */
/* this is the first fragment we ever received for this ip datagram */
ipr->p = new_p;
801a462: 68fb ldr r3, [r7, #12]
801a464: 68ba ldr r2, [r7, #8]
801a466: 605a str r2, [r3, #4]
}
}
/* At this point, the validation part begins: */
/* If we already received the last fragment */
if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
801a468: 687b ldr r3, [r7, #4]
801a46a: 2b00 cmp r3, #0
801a46c: d105 bne.n 801a47a <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
801a46e: 68fb ldr r3, [r7, #12]
801a470: 7f9b ldrb r3, [r3, #30]
801a472: f003 0301 and.w r3, r3, #1
801a476: 2b00 cmp r3, #0
801a478: d059 beq.n 801a52e <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
/* and had no holes so far */
if (valid) {
801a47a: 6a3b ldr r3, [r7, #32]
801a47c: 2b00 cmp r3, #0
801a47e: d04f beq.n 801a520 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
/* then check if the rest of the fragments is here */
/* Check if the queue starts with the first datagram */
if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
801a480: 68fb ldr r3, [r7, #12]
801a482: 685b ldr r3, [r3, #4]
801a484: 2b00 cmp r3, #0
801a486: d006 beq.n 801a496 <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
801a488: 68fb ldr r3, [r7, #12]
801a48a: 685b ldr r3, [r3, #4]
801a48c: 685b ldr r3, [r3, #4]
801a48e: 889b ldrh r3, [r3, #4]
801a490: b29b uxth r3, r3
801a492: 2b00 cmp r3, #0
801a494: d002 beq.n 801a49c <ip_reass_chain_frag_into_datagram_and_validate+0x220>
valid = 0;
801a496: 2300 movs r3, #0
801a498: 623b str r3, [r7, #32]
801a49a: e041 b.n 801a520 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
} else {
/* and check that there are no holes after this datagram */
iprh_prev = iprh;
801a49c: 6afb ldr r3, [r7, #44] ; 0x2c
801a49e: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a4a0: 6afb ldr r3, [r7, #44] ; 0x2c
801a4a2: 681b ldr r3, [r3, #0]
801a4a4: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a4a6: e012 b.n 801a4ce <ip_reass_chain_frag_into_datagram_and_validate+0x252>
iprh = (struct ip_reass_helper *)q->payload;
801a4a8: 6a7b ldr r3, [r7, #36] ; 0x24
801a4aa: 685b ldr r3, [r3, #4]
801a4ac: 62fb str r3, [r7, #44] ; 0x2c
if (iprh_prev->end != iprh->start) {
801a4ae: 6abb ldr r3, [r7, #40] ; 0x28
801a4b0: 88db ldrh r3, [r3, #6]
801a4b2: b29a uxth r2, r3
801a4b4: 6afb ldr r3, [r7, #44] ; 0x2c
801a4b6: 889b ldrh r3, [r3, #4]
801a4b8: b29b uxth r3, r3
801a4ba: 429a cmp r2, r3
801a4bc: d002 beq.n 801a4c4 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
valid = 0;
801a4be: 2300 movs r3, #0
801a4c0: 623b str r3, [r7, #32]
break;
801a4c2: e007 b.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
}
iprh_prev = iprh;
801a4c4: 6afb ldr r3, [r7, #44] ; 0x2c
801a4c6: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a4c8: 6afb ldr r3, [r7, #44] ; 0x2c
801a4ca: 681b ldr r3, [r3, #0]
801a4cc: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a4ce: 6a7b ldr r3, [r7, #36] ; 0x24
801a4d0: 2b00 cmp r3, #0
801a4d2: d1e9 bne.n 801a4a8 <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
}
/* if still valid, all fragments are received
* (because to the MF==0 already arrived */
if (valid) {
801a4d4: 6a3b ldr r3, [r7, #32]
801a4d6: 2b00 cmp r3, #0
801a4d8: d022 beq.n 801a520 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
LWIP_ASSERT("sanity check", ipr->p != NULL);
801a4da: 68fb ldr r3, [r7, #12]
801a4dc: 685b ldr r3, [r3, #4]
801a4de: 2b00 cmp r3, #0
801a4e0: d106 bne.n 801a4f0 <ip_reass_chain_frag_into_datagram_and_validate+0x274>
801a4e2: 4b15 ldr r3, [pc, #84] ; (801a538 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a4e4: f240 12df movw r2, #479 ; 0x1df
801a4e8: 4917 ldr r1, [pc, #92] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a4ea: 4815 ldr r0, [pc, #84] ; (801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a4ec: f000 fd92 bl 801b014 <iprintf>
LWIP_ASSERT("sanity check",
801a4f0: 68fb ldr r3, [r7, #12]
801a4f2: 685b ldr r3, [r3, #4]
801a4f4: 685b ldr r3, [r3, #4]
801a4f6: 6afa ldr r2, [r7, #44] ; 0x2c
801a4f8: 429a cmp r2, r3
801a4fa: d106 bne.n 801a50a <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
801a4fc: 4b0e ldr r3, [pc, #56] ; (801a538 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a4fe: f240 12e1 movw r2, #481 ; 0x1e1
801a502: 4911 ldr r1, [pc, #68] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a504: 480e ldr r0, [pc, #56] ; (801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a506: f000 fd85 bl 801b014 <iprintf>
((struct ip_reass_helper *)ipr->p->payload) != iprh);
LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
801a50a: 6afb ldr r3, [r7, #44] ; 0x2c
801a50c: 681b ldr r3, [r3, #0]
801a50e: 2b00 cmp r3, #0
801a510: d006 beq.n 801a520 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
801a512: 4b09 ldr r3, [pc, #36] ; (801a538 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a514: f240 12e3 movw r2, #483 ; 0x1e3
801a518: 490c ldr r1, [pc, #48] ; (801a54c <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
801a51a: 4809 ldr r0, [pc, #36] ; (801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a51c: f000 fd7a bl 801b014 <iprintf>
}
}
/* If valid is 0 here, there are some fragments missing in the middle
* (since MF == 0 has already arrived). Such datagrams simply time out if
* no more fragments are received... */
return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
801a520: 6a3b ldr r3, [r7, #32]
801a522: 2b00 cmp r3, #0
801a524: bf14 ite ne
801a526: 2301 movne r3, #1
801a528: 2300 moveq r3, #0
801a52a: b2db uxtb r3, r3
801a52c: e000 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* If we come here, not all fragments were received, yet! */
return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
801a52e: 2300 movs r3, #0
}
801a530: 4618 mov r0, r3
801a532: 3730 adds r7, #48 ; 0x30
801a534: 46bd mov sp, r7
801a536: bd80 pop {r7, pc}
801a538: 0801eb40 .word 0x0801eb40
801a53c: 0801ec24 .word 0x0801ec24
801a540: 0801eb88 .word 0x0801eb88
801a544: 0801ec44 .word 0x0801ec44
801a548: 0801ec7c .word 0x0801ec7c
801a54c: 0801ec8c .word 0x0801ec8c
0801a550 <ip4_reass>:
* @param p points to a pbuf chain of the fragment
* @return NULL if reassembly is incomplete, ? otherwise
*/
struct pbuf *
ip4_reass(struct pbuf *p)
{
801a550: b580 push {r7, lr}
801a552: b08e sub sp, #56 ; 0x38
801a554: af00 add r7, sp, #0
801a556: 6078 str r0, [r7, #4]
int is_last;
IPFRAG_STATS_INC(ip_frag.recv);
MIB2_STATS_INC(mib2.ipreasmreqds);
fraghdr = (struct ip_hdr *)p->payload;
801a558: 687b ldr r3, [r7, #4]
801a55a: 685b ldr r3, [r3, #4]
801a55c: 62bb str r3, [r7, #40] ; 0x28
if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
801a55e: 6abb ldr r3, [r7, #40] ; 0x28
801a560: 781b ldrb r3, [r3, #0]
801a562: f003 030f and.w r3, r3, #15
801a566: b2db uxtb r3, r3
801a568: 009b lsls r3, r3, #2
801a56a: b2db uxtb r3, r3
801a56c: 2b14 cmp r3, #20
801a56e: f040 8167 bne.w 801a840 <ip4_reass+0x2f0>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
IPFRAG_STATS_INC(ip_frag.err);
goto nullreturn;
}
offset = IPH_OFFSET_BYTES(fraghdr);
801a572: 6abb ldr r3, [r7, #40] ; 0x28
801a574: 88db ldrh r3, [r3, #6]
801a576: b29b uxth r3, r3
801a578: 4618 mov r0, r3
801a57a: f7f4 fc81 bl 800ee80 <lwip_htons>
801a57e: 4603 mov r3, r0
801a580: f3c3 030c ubfx r3, r3, #0, #13
801a584: b29b uxth r3, r3
801a586: 00db lsls r3, r3, #3
801a588: 84fb strh r3, [r7, #38] ; 0x26
len = lwip_ntohs(IPH_LEN(fraghdr));
801a58a: 6abb ldr r3, [r7, #40] ; 0x28
801a58c: 885b ldrh r3, [r3, #2]
801a58e: b29b uxth r3, r3
801a590: 4618 mov r0, r3
801a592: f7f4 fc75 bl 800ee80 <lwip_htons>
801a596: 4603 mov r3, r0
801a598: 84bb strh r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(fraghdr);
801a59a: 6abb ldr r3, [r7, #40] ; 0x28
801a59c: 781b ldrb r3, [r3, #0]
801a59e: f003 030f and.w r3, r3, #15
801a5a2: b2db uxtb r3, r3
801a5a4: 009b lsls r3, r3, #2
801a5a6: f887 3023 strb.w r3, [r7, #35] ; 0x23
if (hlen > len) {
801a5aa: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a5ae: b29b uxth r3, r3
801a5b0: 8cba ldrh r2, [r7, #36] ; 0x24
801a5b2: 429a cmp r2, r3
801a5b4: f0c0 8146 bcc.w 801a844 <ip4_reass+0x2f4>
/* invalid datagram */
goto nullreturn;
}
len = (u16_t)(len - hlen);
801a5b8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a5bc: b29b uxth r3, r3
801a5be: 8cba ldrh r2, [r7, #36] ; 0x24
801a5c0: 1ad3 subs r3, r2, r3
801a5c2: 84bb strh r3, [r7, #36] ; 0x24
/* Check if we are allowed to enqueue more datagrams. */
clen = pbuf_clen(p);
801a5c4: 6878 ldr r0, [r7, #4]
801a5c6: f7f6 f89d bl 8010704 <pbuf_clen>
801a5ca: 4603 mov r3, r0
801a5cc: 843b strh r3, [r7, #32]
if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
801a5ce: 4ba3 ldr r3, [pc, #652] ; (801a85c <ip4_reass+0x30c>)
801a5d0: 881b ldrh r3, [r3, #0]
801a5d2: 461a mov r2, r3
801a5d4: 8c3b ldrh r3, [r7, #32]
801a5d6: 4413 add r3, r2
801a5d8: 2b0a cmp r3, #10
801a5da: dd10 ble.n 801a5fe <ip4_reass+0xae>
#if IP_REASS_FREE_OLDEST
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a5dc: 8c3b ldrh r3, [r7, #32]
801a5de: 4619 mov r1, r3
801a5e0: 6ab8 ldr r0, [r7, #40] ; 0x28
801a5e2: f7ff fd81 bl 801a0e8 <ip_reass_remove_oldest_datagram>
801a5e6: 4603 mov r3, r0
801a5e8: 2b00 cmp r3, #0
801a5ea: f000 812d beq.w 801a848 <ip4_reass+0x2f8>
((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
801a5ee: 4b9b ldr r3, [pc, #620] ; (801a85c <ip4_reass+0x30c>)
801a5f0: 881b ldrh r3, [r3, #0]
801a5f2: 461a mov r2, r3
801a5f4: 8c3b ldrh r3, [r7, #32]
801a5f6: 4413 add r3, r2
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a5f8: 2b0a cmp r3, #10
801a5fa: f300 8125 bgt.w 801a848 <ip4_reass+0x2f8>
}
}
/* Look for the datagram the fragment belongs to in the current datagram queue,
* remembering the previous in the queue for later dequeueing. */
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a5fe: 4b98 ldr r3, [pc, #608] ; (801a860 <ip4_reass+0x310>)
801a600: 681b ldr r3, [r3, #0]
801a602: 633b str r3, [r7, #48] ; 0x30
801a604: e015 b.n 801a632 <ip4_reass+0xe2>
/* Check if the incoming fragment matches the one currently present
in the reassembly buffer. If so, we proceed with copying the
fragment into the buffer. */
if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
801a606: 6b3b ldr r3, [r7, #48] ; 0x30
801a608: 695a ldr r2, [r3, #20]
801a60a: 6abb ldr r3, [r7, #40] ; 0x28
801a60c: 68db ldr r3, [r3, #12]
801a60e: 429a cmp r2, r3
801a610: d10c bne.n 801a62c <ip4_reass+0xdc>
801a612: 6b3b ldr r3, [r7, #48] ; 0x30
801a614: 699a ldr r2, [r3, #24]
801a616: 6abb ldr r3, [r7, #40] ; 0x28
801a618: 691b ldr r3, [r3, #16]
801a61a: 429a cmp r2, r3
801a61c: d106 bne.n 801a62c <ip4_reass+0xdc>
801a61e: 6b3b ldr r3, [r7, #48] ; 0x30
801a620: 899a ldrh r2, [r3, #12]
801a622: 6abb ldr r3, [r7, #40] ; 0x28
801a624: 889b ldrh r3, [r3, #4]
801a626: b29b uxth r3, r3
801a628: 429a cmp r2, r3
801a62a: d006 beq.n 801a63a <ip4_reass+0xea>
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a62c: 6b3b ldr r3, [r7, #48] ; 0x30
801a62e: 681b ldr r3, [r3, #0]
801a630: 633b str r3, [r7, #48] ; 0x30
801a632: 6b3b ldr r3, [r7, #48] ; 0x30
801a634: 2b00 cmp r3, #0
801a636: d1e6 bne.n 801a606 <ip4_reass+0xb6>
801a638: e000 b.n 801a63c <ip4_reass+0xec>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
lwip_ntohs(IPH_ID(fraghdr))));
IPFRAG_STATS_INC(ip_frag.cachehit);
break;
801a63a: bf00 nop
}
}
if (ipr == NULL) {
801a63c: 6b3b ldr r3, [r7, #48] ; 0x30
801a63e: 2b00 cmp r3, #0
801a640: d109 bne.n 801a656 <ip4_reass+0x106>
/* Enqueue a new datagram into the datagram queue */
ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
801a642: 8c3b ldrh r3, [r7, #32]
801a644: 4619 mov r1, r3
801a646: 6ab8 ldr r0, [r7, #40] ; 0x28
801a648: f7ff fdb0 bl 801a1ac <ip_reass_enqueue_new_datagram>
801a64c: 6338 str r0, [r7, #48] ; 0x30
/* Bail if unable to enqueue */
if (ipr == NULL) {
801a64e: 6b3b ldr r3, [r7, #48] ; 0x30
801a650: 2b00 cmp r3, #0
801a652: d11c bne.n 801a68e <ip4_reass+0x13e>
goto nullreturn;
801a654: e0f9 b.n 801a84a <ip4_reass+0x2fa>
}
} else {
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a656: 6abb ldr r3, [r7, #40] ; 0x28
801a658: 88db ldrh r3, [r3, #6]
801a65a: b29b uxth r3, r3
801a65c: 4618 mov r0, r3
801a65e: f7f4 fc0f bl 800ee80 <lwip_htons>
801a662: 4603 mov r3, r0
801a664: f3c3 030c ubfx r3, r3, #0, #13
801a668: 2b00 cmp r3, #0
801a66a: d110 bne.n 801a68e <ip4_reass+0x13e>
((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
801a66c: 6b3b ldr r3, [r7, #48] ; 0x30
801a66e: 89db ldrh r3, [r3, #14]
801a670: 4618 mov r0, r3
801a672: f7f4 fc05 bl 800ee80 <lwip_htons>
801a676: 4603 mov r3, r0
801a678: f3c3 030c ubfx r3, r3, #0, #13
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a67c: 2b00 cmp r3, #0
801a67e: d006 beq.n 801a68e <ip4_reass+0x13e>
/* ipr->iphdr is not the header from the first fragment, but fraghdr is
* -> copy fraghdr into ipr->iphdr since we want to have the header
* of the first fragment (for ICMP time exceeded and later, for copying
* all options, if supported)*/
SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
801a680: 6b3b ldr r3, [r7, #48] ; 0x30
801a682: 3308 adds r3, #8
801a684: 2214 movs r2, #20
801a686: 6ab9 ldr r1, [r7, #40] ; 0x28
801a688: 4618 mov r0, r3
801a68a: f000 fcb0 bl 801afee <memcpy>
/* At this point, we have either created a new entry or pointing
* to an existing one */
/* check for 'no more fragments', and update queue entry*/
is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
801a68e: 6abb ldr r3, [r7, #40] ; 0x28
801a690: 88db ldrh r3, [r3, #6]
801a692: b29b uxth r3, r3
801a694: f003 0320 and.w r3, r3, #32
801a698: 2b00 cmp r3, #0
801a69a: bf0c ite eq
801a69c: 2301 moveq r3, #1
801a69e: 2300 movne r3, #0
801a6a0: b2db uxtb r3, r3
801a6a2: 61fb str r3, [r7, #28]
if (is_last) {
801a6a4: 69fb ldr r3, [r7, #28]
801a6a6: 2b00 cmp r3, #0
801a6a8: d00e beq.n 801a6c8 <ip4_reass+0x178>
u16_t datagram_len = (u16_t)(offset + len);
801a6aa: 8cfa ldrh r2, [r7, #38] ; 0x26
801a6ac: 8cbb ldrh r3, [r7, #36] ; 0x24
801a6ae: 4413 add r3, r2
801a6b0: 837b strh r3, [r7, #26]
if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
801a6b2: 8b7a ldrh r2, [r7, #26]
801a6b4: 8cfb ldrh r3, [r7, #38] ; 0x26
801a6b6: 429a cmp r2, r3
801a6b8: f0c0 80a0 bcc.w 801a7fc <ip4_reass+0x2ac>
801a6bc: 8b7b ldrh r3, [r7, #26]
801a6be: f64f 72eb movw r2, #65515 ; 0xffeb
801a6c2: 4293 cmp r3, r2
801a6c4: f200 809a bhi.w 801a7fc <ip4_reass+0x2ac>
goto nullreturn_ipr;
}
}
/* find the right place to insert this pbuf */
/* @todo: trim pbufs if fragments are overlapping */
valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
801a6c8: 69fa ldr r2, [r7, #28]
801a6ca: 6879 ldr r1, [r7, #4]
801a6cc: 6b38 ldr r0, [r7, #48] ; 0x30
801a6ce: f7ff fdd5 bl 801a27c <ip_reass_chain_frag_into_datagram_and_validate>
801a6d2: 6178 str r0, [r7, #20]
if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
801a6d4: 697b ldr r3, [r7, #20]
801a6d6: f1b3 3fff cmp.w r3, #4294967295
801a6da: f000 8091 beq.w 801a800 <ip4_reass+0x2b0>
/* if we come here, the pbuf has been enqueued */
/* Track the current number of pbufs current 'in-flight', in order to limit
the number of fragments that may be enqueued at any one time
(overflow checked by testing against IP_REASS_MAX_PBUFS) */
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
801a6de: 4b5f ldr r3, [pc, #380] ; (801a85c <ip4_reass+0x30c>)
801a6e0: 881a ldrh r2, [r3, #0]
801a6e2: 8c3b ldrh r3, [r7, #32]
801a6e4: 4413 add r3, r2
801a6e6: b29a uxth r2, r3
801a6e8: 4b5c ldr r3, [pc, #368] ; (801a85c <ip4_reass+0x30c>)
801a6ea: 801a strh r2, [r3, #0]
if (is_last) {
801a6ec: 69fb ldr r3, [r7, #28]
801a6ee: 2b00 cmp r3, #0
801a6f0: d00d beq.n 801a70e <ip4_reass+0x1be>
u16_t datagram_len = (u16_t)(offset + len);
801a6f2: 8cfa ldrh r2, [r7, #38] ; 0x26
801a6f4: 8cbb ldrh r3, [r7, #36] ; 0x24
801a6f6: 4413 add r3, r2
801a6f8: 827b strh r3, [r7, #18]
ipr->datagram_len = datagram_len;
801a6fa: 6b3b ldr r3, [r7, #48] ; 0x30
801a6fc: 8a7a ldrh r2, [r7, #18]
801a6fe: 839a strh r2, [r3, #28]
ipr->flags |= IP_REASS_FLAG_LASTFRAG;
801a700: 6b3b ldr r3, [r7, #48] ; 0x30
801a702: 7f9b ldrb r3, [r3, #30]
801a704: f043 0301 orr.w r3, r3, #1
801a708: b2da uxtb r2, r3
801a70a: 6b3b ldr r3, [r7, #48] ; 0x30
801a70c: 779a strb r2, [r3, #30]
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip4_reass: last fragment seen, total len %"S16_F"\n",
ipr->datagram_len));
}
if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
801a70e: 697b ldr r3, [r7, #20]
801a710: 2b01 cmp r3, #1
801a712: d171 bne.n 801a7f8 <ip4_reass+0x2a8>
struct ip_reassdata *ipr_prev;
/* the totally last fragment (flag more fragments = 0) was received at least
* once AND all fragments are received */
u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
801a714: 6b3b ldr r3, [r7, #48] ; 0x30
801a716: 8b9b ldrh r3, [r3, #28]
801a718: 3314 adds r3, #20
801a71a: 823b strh r3, [r7, #16]
/* save the second pbuf before copying the header over the pointer */
r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
801a71c: 6b3b ldr r3, [r7, #48] ; 0x30
801a71e: 685b ldr r3, [r3, #4]
801a720: 685b ldr r3, [r3, #4]
801a722: 681b ldr r3, [r3, #0]
801a724: 637b str r3, [r7, #52] ; 0x34
/* copy the original ip header back to the first pbuf */
fraghdr = (struct ip_hdr *)(ipr->p->payload);
801a726: 6b3b ldr r3, [r7, #48] ; 0x30
801a728: 685b ldr r3, [r3, #4]
801a72a: 685b ldr r3, [r3, #4]
801a72c: 62bb str r3, [r7, #40] ; 0x28
SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
801a72e: 6b3b ldr r3, [r7, #48] ; 0x30
801a730: 3308 adds r3, #8
801a732: 2214 movs r2, #20
801a734: 4619 mov r1, r3
801a736: 6ab8 ldr r0, [r7, #40] ; 0x28
801a738: f000 fc59 bl 801afee <memcpy>
IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
801a73c: 8a3b ldrh r3, [r7, #16]
801a73e: 4618 mov r0, r3
801a740: f7f4 fb9e bl 800ee80 <lwip_htons>
801a744: 4603 mov r3, r0
801a746: 461a mov r2, r3
801a748: 6abb ldr r3, [r7, #40] ; 0x28
801a74a: 805a strh r2, [r3, #2]
IPH_OFFSET_SET(fraghdr, 0);
801a74c: 6abb ldr r3, [r7, #40] ; 0x28
801a74e: 2200 movs r2, #0
801a750: 719a strb r2, [r3, #6]
801a752: 2200 movs r2, #0
801a754: 71da strb r2, [r3, #7]
IPH_CHKSUM_SET(fraghdr, 0);
801a756: 6abb ldr r3, [r7, #40] ; 0x28
801a758: 2200 movs r2, #0
801a75a: 729a strb r2, [r3, #10]
801a75c: 2200 movs r2, #0
801a75e: 72da strb r2, [r3, #11]
IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
}
#endif /* CHECKSUM_GEN_IP */
p = ipr->p;
801a760: 6b3b ldr r3, [r7, #48] ; 0x30
801a762: 685b ldr r3, [r3, #4]
801a764: 607b str r3, [r7, #4]
/* chain together the pbufs contained within the reass_data list. */
while (r != NULL) {
801a766: e00d b.n 801a784 <ip4_reass+0x234>
iprh = (struct ip_reass_helper *)r->payload;
801a768: 6b7b ldr r3, [r7, #52] ; 0x34
801a76a: 685b ldr r3, [r3, #4]
801a76c: 60fb str r3, [r7, #12]
/* hide the ip header for every succeeding fragment */
pbuf_remove_header(r, IP_HLEN);
801a76e: 2114 movs r1, #20
801a770: 6b78 ldr r0, [r7, #52] ; 0x34
801a772: f7f5 feb3 bl 80104dc <pbuf_remove_header>
pbuf_cat(p, r);
801a776: 6b79 ldr r1, [r7, #52] ; 0x34
801a778: 6878 ldr r0, [r7, #4]
801a77a: f7f6 f803 bl 8010784 <pbuf_cat>
r = iprh->next_pbuf;
801a77e: 68fb ldr r3, [r7, #12]
801a780: 681b ldr r3, [r3, #0]
801a782: 637b str r3, [r7, #52] ; 0x34
while (r != NULL) {
801a784: 6b7b ldr r3, [r7, #52] ; 0x34
801a786: 2b00 cmp r3, #0
801a788: d1ee bne.n 801a768 <ip4_reass+0x218>
}
/* find the previous entry in the linked list */
if (ipr == reassdatagrams) {
801a78a: 4b35 ldr r3, [pc, #212] ; (801a860 <ip4_reass+0x310>)
801a78c: 681b ldr r3, [r3, #0]
801a78e: 6b3a ldr r2, [r7, #48] ; 0x30
801a790: 429a cmp r2, r3
801a792: d102 bne.n 801a79a <ip4_reass+0x24a>
ipr_prev = NULL;
801a794: 2300 movs r3, #0
801a796: 62fb str r3, [r7, #44] ; 0x2c
801a798: e010 b.n 801a7bc <ip4_reass+0x26c>
} else {
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a79a: 4b31 ldr r3, [pc, #196] ; (801a860 <ip4_reass+0x310>)
801a79c: 681b ldr r3, [r3, #0]
801a79e: 62fb str r3, [r7, #44] ; 0x2c
801a7a0: e007 b.n 801a7b2 <ip4_reass+0x262>
if (ipr_prev->next == ipr) {
801a7a2: 6afb ldr r3, [r7, #44] ; 0x2c
801a7a4: 681b ldr r3, [r3, #0]
801a7a6: 6b3a ldr r2, [r7, #48] ; 0x30
801a7a8: 429a cmp r2, r3
801a7aa: d006 beq.n 801a7ba <ip4_reass+0x26a>
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a7ac: 6afb ldr r3, [r7, #44] ; 0x2c
801a7ae: 681b ldr r3, [r3, #0]
801a7b0: 62fb str r3, [r7, #44] ; 0x2c
801a7b2: 6afb ldr r3, [r7, #44] ; 0x2c
801a7b4: 2b00 cmp r3, #0
801a7b6: d1f4 bne.n 801a7a2 <ip4_reass+0x252>
801a7b8: e000 b.n 801a7bc <ip4_reass+0x26c>
break;
801a7ba: bf00 nop
}
}
}
/* release the sources allocate for the fragment queue entry */
ip_reass_dequeue_datagram(ipr, ipr_prev);
801a7bc: 6af9 ldr r1, [r7, #44] ; 0x2c
801a7be: 6b38 ldr r0, [r7, #48] ; 0x30
801a7c0: f7ff fd2e bl 801a220 <ip_reass_dequeue_datagram>
/* and adjust the number of pbufs currently queued for reassembly. */
clen = pbuf_clen(p);
801a7c4: 6878 ldr r0, [r7, #4]
801a7c6: f7f5 ff9d bl 8010704 <pbuf_clen>
801a7ca: 4603 mov r3, r0
801a7cc: 843b strh r3, [r7, #32]
LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
801a7ce: 4b23 ldr r3, [pc, #140] ; (801a85c <ip4_reass+0x30c>)
801a7d0: 881b ldrh r3, [r3, #0]
801a7d2: 8c3a ldrh r2, [r7, #32]
801a7d4: 429a cmp r2, r3
801a7d6: d906 bls.n 801a7e6 <ip4_reass+0x296>
801a7d8: 4b22 ldr r3, [pc, #136] ; (801a864 <ip4_reass+0x314>)
801a7da: f240 229b movw r2, #667 ; 0x29b
801a7de: 4922 ldr r1, [pc, #136] ; (801a868 <ip4_reass+0x318>)
801a7e0: 4822 ldr r0, [pc, #136] ; (801a86c <ip4_reass+0x31c>)
801a7e2: f000 fc17 bl 801b014 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
801a7e6: 4b1d ldr r3, [pc, #116] ; (801a85c <ip4_reass+0x30c>)
801a7e8: 881a ldrh r2, [r3, #0]
801a7ea: 8c3b ldrh r3, [r7, #32]
801a7ec: 1ad3 subs r3, r2, r3
801a7ee: b29a uxth r2, r3
801a7f0: 4b1a ldr r3, [pc, #104] ; (801a85c <ip4_reass+0x30c>)
801a7f2: 801a strh r2, [r3, #0]
MIB2_STATS_INC(mib2.ipreasmoks);
/* Return the pbuf chain */
return p;
801a7f4: 687b ldr r3, [r7, #4]
801a7f6: e02c b.n 801a852 <ip4_reass+0x302>
}
/* the datagram is not (yet?) reassembled completely */
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
return NULL;
801a7f8: 2300 movs r3, #0
801a7fa: e02a b.n 801a852 <ip4_reass+0x302>
nullreturn_ipr:
801a7fc: bf00 nop
801a7fe: e000 b.n 801a802 <ip4_reass+0x2b2>
goto nullreturn_ipr;
801a800: bf00 nop
LWIP_ASSERT("ipr != NULL", ipr != NULL);
801a802: 6b3b ldr r3, [r7, #48] ; 0x30
801a804: 2b00 cmp r3, #0
801a806: d106 bne.n 801a816 <ip4_reass+0x2c6>
801a808: 4b16 ldr r3, [pc, #88] ; (801a864 <ip4_reass+0x314>)
801a80a: f44f 722a mov.w r2, #680 ; 0x2a8
801a80e: 4918 ldr r1, [pc, #96] ; (801a870 <ip4_reass+0x320>)
801a810: 4816 ldr r0, [pc, #88] ; (801a86c <ip4_reass+0x31c>)
801a812: f000 fbff bl 801b014 <iprintf>
if (ipr->p == NULL) {
801a816: 6b3b ldr r3, [r7, #48] ; 0x30
801a818: 685b ldr r3, [r3, #4]
801a81a: 2b00 cmp r3, #0
801a81c: d114 bne.n 801a848 <ip4_reass+0x2f8>
/* dropped pbuf after creating a new datagram entry: remove the entry, too */
LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
801a81e: 4b10 ldr r3, [pc, #64] ; (801a860 <ip4_reass+0x310>)
801a820: 681b ldr r3, [r3, #0]
801a822: 6b3a ldr r2, [r7, #48] ; 0x30
801a824: 429a cmp r2, r3
801a826: d006 beq.n 801a836 <ip4_reass+0x2e6>
801a828: 4b0e ldr r3, [pc, #56] ; (801a864 <ip4_reass+0x314>)
801a82a: f240 22ab movw r2, #683 ; 0x2ab
801a82e: 4911 ldr r1, [pc, #68] ; (801a874 <ip4_reass+0x324>)
801a830: 480e ldr r0, [pc, #56] ; (801a86c <ip4_reass+0x31c>)
801a832: f000 fbef bl 801b014 <iprintf>
ip_reass_dequeue_datagram(ipr, NULL);
801a836: 2100 movs r1, #0
801a838: 6b38 ldr r0, [r7, #48] ; 0x30
801a83a: f7ff fcf1 bl 801a220 <ip_reass_dequeue_datagram>
801a83e: e004 b.n 801a84a <ip4_reass+0x2fa>
goto nullreturn;
801a840: bf00 nop
801a842: e002 b.n 801a84a <ip4_reass+0x2fa>
goto nullreturn;
801a844: bf00 nop
801a846: e000 b.n 801a84a <ip4_reass+0x2fa>
}
nullreturn:
801a848: bf00 nop
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
IPFRAG_STATS_INC(ip_frag.drop);
pbuf_free(p);
801a84a: 6878 ldr r0, [r7, #4]
801a84c: f7f5 fecc bl 80105e8 <pbuf_free>
return NULL;
801a850: 2300 movs r3, #0
}
801a852: 4618 mov r0, r3
801a854: 3738 adds r7, #56 ; 0x38
801a856: 46bd mov sp, r7
801a858: bd80 pop {r7, pc}
801a85a: bf00 nop
801a85c: 20008870 .word 0x20008870
801a860: 2000886c .word 0x2000886c
801a864: 0801eb40 .word 0x0801eb40
801a868: 0801ecb0 .word 0x0801ecb0
801a86c: 0801eb88 .word 0x0801eb88
801a870: 0801eccc .word 0x0801eccc
801a874: 0801ecd8 .word 0x0801ecd8
0801a878 <ip_frag_alloc_pbuf_custom_ref>:
#if IP_FRAG
#if !LWIP_NETIF_TX_SINGLE_PBUF
/** Allocate a new struct pbuf_custom_ref */
static struct pbuf_custom_ref *
ip_frag_alloc_pbuf_custom_ref(void)
{
801a878: b580 push {r7, lr}
801a87a: af00 add r7, sp, #0
return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
801a87c: 2005 movs r0, #5
801a87e: f7f4 ffb5 bl 800f7ec <memp_malloc>
801a882: 4603 mov r3, r0
}
801a884: 4618 mov r0, r3
801a886: bd80 pop {r7, pc}
0801a888 <ip_frag_free_pbuf_custom_ref>:
/** Free a struct pbuf_custom_ref */
static void
ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
{
801a888: b580 push {r7, lr}
801a88a: b082 sub sp, #8
801a88c: af00 add r7, sp, #0
801a88e: 6078 str r0, [r7, #4]
LWIP_ASSERT("p != NULL", p != NULL);
801a890: 687b ldr r3, [r7, #4]
801a892: 2b00 cmp r3, #0
801a894: d106 bne.n 801a8a4 <ip_frag_free_pbuf_custom_ref+0x1c>
801a896: 4b07 ldr r3, [pc, #28] ; (801a8b4 <ip_frag_free_pbuf_custom_ref+0x2c>)
801a898: f44f 7231 mov.w r2, #708 ; 0x2c4
801a89c: 4906 ldr r1, [pc, #24] ; (801a8b8 <ip_frag_free_pbuf_custom_ref+0x30>)
801a89e: 4807 ldr r0, [pc, #28] ; (801a8bc <ip_frag_free_pbuf_custom_ref+0x34>)
801a8a0: f000 fbb8 bl 801b014 <iprintf>
memp_free(MEMP_FRAG_PBUF, p);
801a8a4: 6879 ldr r1, [r7, #4]
801a8a6: 2005 movs r0, #5
801a8a8: f7f4 fff2 bl 800f890 <memp_free>
}
801a8ac: bf00 nop
801a8ae: 3708 adds r7, #8
801a8b0: 46bd mov sp, r7
801a8b2: bd80 pop {r7, pc}
801a8b4: 0801eb40 .word 0x0801eb40
801a8b8: 0801ecf8 .word 0x0801ecf8
801a8bc: 0801eb88 .word 0x0801eb88
0801a8c0 <ipfrag_free_pbuf_custom>:
/** Free-callback function to free a 'struct pbuf_custom_ref', called by
* pbuf_free. */
static void
ipfrag_free_pbuf_custom(struct pbuf *p)
{
801a8c0: b580 push {r7, lr}
801a8c2: b084 sub sp, #16
801a8c4: af00 add r7, sp, #0
801a8c6: 6078 str r0, [r7, #4]
struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
801a8c8: 687b ldr r3, [r7, #4]
801a8ca: 60fb str r3, [r7, #12]
LWIP_ASSERT("pcr != NULL", pcr != NULL);
801a8cc: 68fb ldr r3, [r7, #12]
801a8ce: 2b00 cmp r3, #0
801a8d0: d106 bne.n 801a8e0 <ipfrag_free_pbuf_custom+0x20>
801a8d2: 4b11 ldr r3, [pc, #68] ; (801a918 <ipfrag_free_pbuf_custom+0x58>)
801a8d4: f240 22ce movw r2, #718 ; 0x2ce
801a8d8: 4910 ldr r1, [pc, #64] ; (801a91c <ipfrag_free_pbuf_custom+0x5c>)
801a8da: 4811 ldr r0, [pc, #68] ; (801a920 <ipfrag_free_pbuf_custom+0x60>)
801a8dc: f000 fb9a bl 801b014 <iprintf>
LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
801a8e0: 68fa ldr r2, [r7, #12]
801a8e2: 687b ldr r3, [r7, #4]
801a8e4: 429a cmp r2, r3
801a8e6: d006 beq.n 801a8f6 <ipfrag_free_pbuf_custom+0x36>
801a8e8: 4b0b ldr r3, [pc, #44] ; (801a918 <ipfrag_free_pbuf_custom+0x58>)
801a8ea: f240 22cf movw r2, #719 ; 0x2cf
801a8ee: 490d ldr r1, [pc, #52] ; (801a924 <ipfrag_free_pbuf_custom+0x64>)
801a8f0: 480b ldr r0, [pc, #44] ; (801a920 <ipfrag_free_pbuf_custom+0x60>)
801a8f2: f000 fb8f bl 801b014 <iprintf>
if (pcr->original != NULL) {
801a8f6: 68fb ldr r3, [r7, #12]
801a8f8: 695b ldr r3, [r3, #20]
801a8fa: 2b00 cmp r3, #0
801a8fc: d004 beq.n 801a908 <ipfrag_free_pbuf_custom+0x48>
pbuf_free(pcr->original);
801a8fe: 68fb ldr r3, [r7, #12]
801a900: 695b ldr r3, [r3, #20]
801a902: 4618 mov r0, r3
801a904: f7f5 fe70 bl 80105e8 <pbuf_free>
}
ip_frag_free_pbuf_custom_ref(pcr);
801a908: 68f8 ldr r0, [r7, #12]
801a90a: f7ff ffbd bl 801a888 <ip_frag_free_pbuf_custom_ref>
}
801a90e: bf00 nop
801a910: 3710 adds r7, #16
801a912: 46bd mov sp, r7
801a914: bd80 pop {r7, pc}
801a916: bf00 nop
801a918: 0801eb40 .word 0x0801eb40
801a91c: 0801ed04 .word 0x0801ed04
801a920: 0801eb88 .word 0x0801eb88
801a924: 0801ed10 .word 0x0801ed10
0801a928 <ip4_frag>:
*
* @return ERR_OK if sent successfully, err_t otherwise
*/
err_t
ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
{
801a928: b580 push {r7, lr}
801a92a: b094 sub sp, #80 ; 0x50
801a92c: af02 add r7, sp, #8
801a92e: 60f8 str r0, [r7, #12]
801a930: 60b9 str r1, [r7, #8]
801a932: 607a str r2, [r7, #4]
struct pbuf *rambuf;
#if !LWIP_NETIF_TX_SINGLE_PBUF
struct pbuf *newpbuf;
u16_t newpbuflen = 0;
801a934: 2300 movs r3, #0
801a936: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
u16_t left_to_copy;
#endif
struct ip_hdr *original_iphdr;
struct ip_hdr *iphdr;
const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
801a93a: 68bb ldr r3, [r7, #8]
801a93c: 8d1b ldrh r3, [r3, #40] ; 0x28
801a93e: 3b14 subs r3, #20
801a940: 2b00 cmp r3, #0
801a942: da00 bge.n 801a946 <ip4_frag+0x1e>
801a944: 3307 adds r3, #7
801a946: 10db asrs r3, r3, #3
801a948: 877b strh r3, [r7, #58] ; 0x3a
u16_t left, fragsize;
u16_t ofo;
int last;
u16_t poff = IP_HLEN;
801a94a: 2314 movs r3, #20
801a94c: 87fb strh r3, [r7, #62] ; 0x3e
u16_t tmp;
int mf_set;
original_iphdr = (struct ip_hdr *)p->payload;
801a94e: 68fb ldr r3, [r7, #12]
801a950: 685b ldr r3, [r3, #4]
801a952: 637b str r3, [r7, #52] ; 0x34
iphdr = original_iphdr;
801a954: 6b7b ldr r3, [r7, #52] ; 0x34
801a956: 633b str r3, [r7, #48] ; 0x30
if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
801a958: 6b3b ldr r3, [r7, #48] ; 0x30
801a95a: 781b ldrb r3, [r3, #0]
801a95c: f003 030f and.w r3, r3, #15
801a960: b2db uxtb r3, r3
801a962: 009b lsls r3, r3, #2
801a964: b2db uxtb r3, r3
801a966: 2b14 cmp r3, #20
801a968: d002 beq.n 801a970 <ip4_frag+0x48>
/* ip4_frag() does not support IP options */
return ERR_VAL;
801a96a: f06f 0305 mvn.w r3, #5
801a96e: e10f b.n 801ab90 <ip4_frag+0x268>
}
LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
801a970: 68fb ldr r3, [r7, #12]
801a972: 895b ldrh r3, [r3, #10]
801a974: 2b13 cmp r3, #19
801a976: d809 bhi.n 801a98c <ip4_frag+0x64>
801a978: 4b87 ldr r3, [pc, #540] ; (801ab98 <ip4_frag+0x270>)
801a97a: f44f 723f mov.w r2, #764 ; 0x2fc
801a97e: 4987 ldr r1, [pc, #540] ; (801ab9c <ip4_frag+0x274>)
801a980: 4887 ldr r0, [pc, #540] ; (801aba0 <ip4_frag+0x278>)
801a982: f000 fb47 bl 801b014 <iprintf>
801a986: f06f 0305 mvn.w r3, #5
801a98a: e101 b.n 801ab90 <ip4_frag+0x268>
/* Save original offset */
tmp = lwip_ntohs(IPH_OFFSET(iphdr));
801a98c: 6b3b ldr r3, [r7, #48] ; 0x30
801a98e: 88db ldrh r3, [r3, #6]
801a990: b29b uxth r3, r3
801a992: 4618 mov r0, r3
801a994: f7f4 fa74 bl 800ee80 <lwip_htons>
801a998: 4603 mov r3, r0
801a99a: 87bb strh r3, [r7, #60] ; 0x3c
ofo = tmp & IP_OFFMASK;
801a99c: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a99e: f3c3 030c ubfx r3, r3, #0, #13
801a9a2: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
/* already fragmented? if so, the last fragment we create must have MF, too */
mf_set = tmp & IP_MF;
801a9a6: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a9a8: f403 5300 and.w r3, r3, #8192 ; 0x2000
801a9ac: 62fb str r3, [r7, #44] ; 0x2c
left = (u16_t)(p->tot_len - IP_HLEN);
801a9ae: 68fb ldr r3, [r7, #12]
801a9b0: 891b ldrh r3, [r3, #8]
801a9b2: 3b14 subs r3, #20
801a9b4: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
while (left) {
801a9b8: e0e0 b.n 801ab7c <ip4_frag+0x254>
/* Fill this fragment */
fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
801a9ba: 8f7b ldrh r3, [r7, #58] ; 0x3a
801a9bc: 00db lsls r3, r3, #3
801a9be: b29b uxth r3, r3
801a9c0: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801a9c4: 4293 cmp r3, r2
801a9c6: bf28 it cs
801a9c8: 4613 movcs r3, r2
801a9ca: 857b strh r3, [r7, #42] ; 0x2a
/* When not using a static buffer, create a chain of pbufs.
* The first will be a PBUF_RAM holding the link and IP header.
* The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
* but limited to the size of an mtu.
*/
rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
801a9cc: f44f 7220 mov.w r2, #640 ; 0x280
801a9d0: 2114 movs r1, #20
801a9d2: 200e movs r0, #14
801a9d4: f7f5 fb28 bl 8010028 <pbuf_alloc>
801a9d8: 6278 str r0, [r7, #36] ; 0x24
if (rambuf == NULL) {
801a9da: 6a7b ldr r3, [r7, #36] ; 0x24
801a9dc: 2b00 cmp r3, #0
801a9de: f000 80d4 beq.w 801ab8a <ip4_frag+0x262>
goto memerr;
}
LWIP_ASSERT("this needs a pbuf in one piece!",
801a9e2: 6a7b ldr r3, [r7, #36] ; 0x24
801a9e4: 895b ldrh r3, [r3, #10]
801a9e6: 2b13 cmp r3, #19
801a9e8: d806 bhi.n 801a9f8 <ip4_frag+0xd0>
801a9ea: 4b6b ldr r3, [pc, #428] ; (801ab98 <ip4_frag+0x270>)
801a9ec: f240 3225 movw r2, #805 ; 0x325
801a9f0: 496c ldr r1, [pc, #432] ; (801aba4 <ip4_frag+0x27c>)
801a9f2: 486b ldr r0, [pc, #428] ; (801aba0 <ip4_frag+0x278>)
801a9f4: f000 fb0e bl 801b014 <iprintf>
(rambuf->len >= (IP_HLEN)));
SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
801a9f8: 6a7b ldr r3, [r7, #36] ; 0x24
801a9fa: 685b ldr r3, [r3, #4]
801a9fc: 2214 movs r2, #20
801a9fe: 6b79 ldr r1, [r7, #52] ; 0x34
801aa00: 4618 mov r0, r3
801aa02: f000 faf4 bl 801afee <memcpy>
iphdr = (struct ip_hdr *)rambuf->payload;
801aa06: 6a7b ldr r3, [r7, #36] ; 0x24
801aa08: 685b ldr r3, [r3, #4]
801aa0a: 633b str r3, [r7, #48] ; 0x30
left_to_copy = fragsize;
801aa0c: 8d7b ldrh r3, [r7, #42] ; 0x2a
801aa0e: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
while (left_to_copy) {
801aa12: e064 b.n 801aade <ip4_frag+0x1b6>
struct pbuf_custom_ref *pcr;
u16_t plen = (u16_t)(p->len - poff);
801aa14: 68fb ldr r3, [r7, #12]
801aa16: 895a ldrh r2, [r3, #10]
801aa18: 8ffb ldrh r3, [r7, #62] ; 0x3e
801aa1a: 1ad3 subs r3, r2, r3
801aa1c: 83fb strh r3, [r7, #30]
LWIP_ASSERT("p->len >= poff", p->len >= poff);
801aa1e: 68fb ldr r3, [r7, #12]
801aa20: 895b ldrh r3, [r3, #10]
801aa22: 8ffa ldrh r2, [r7, #62] ; 0x3e
801aa24: 429a cmp r2, r3
801aa26: d906 bls.n 801aa36 <ip4_frag+0x10e>
801aa28: 4b5b ldr r3, [pc, #364] ; (801ab98 <ip4_frag+0x270>)
801aa2a: f240 322d movw r2, #813 ; 0x32d
801aa2e: 495e ldr r1, [pc, #376] ; (801aba8 <ip4_frag+0x280>)
801aa30: 485b ldr r0, [pc, #364] ; (801aba0 <ip4_frag+0x278>)
801aa32: f000 faef bl 801b014 <iprintf>
newpbuflen = LWIP_MIN(left_to_copy, plen);
801aa36: 8bfa ldrh r2, [r7, #30]
801aa38: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aa3c: 4293 cmp r3, r2
801aa3e: bf28 it cs
801aa40: 4613 movcs r3, r2
801aa42: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
/* Is this pbuf already empty? */
if (!newpbuflen) {
801aa46: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aa4a: 2b00 cmp r3, #0
801aa4c: d105 bne.n 801aa5a <ip4_frag+0x132>
poff = 0;
801aa4e: 2300 movs r3, #0
801aa50: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801aa52: 68fb ldr r3, [r7, #12]
801aa54: 681b ldr r3, [r3, #0]
801aa56: 60fb str r3, [r7, #12]
continue;
801aa58: e041 b.n 801aade <ip4_frag+0x1b6>
}
pcr = ip_frag_alloc_pbuf_custom_ref();
801aa5a: f7ff ff0d bl 801a878 <ip_frag_alloc_pbuf_custom_ref>
801aa5e: 61b8 str r0, [r7, #24]
if (pcr == NULL) {
801aa60: 69bb ldr r3, [r7, #24]
801aa62: 2b00 cmp r3, #0
801aa64: d103 bne.n 801aa6e <ip4_frag+0x146>
pbuf_free(rambuf);
801aa66: 6a78 ldr r0, [r7, #36] ; 0x24
801aa68: f7f5 fdbe bl 80105e8 <pbuf_free>
goto memerr;
801aa6c: e08e b.n 801ab8c <ip4_frag+0x264>
}
/* Mirror this pbuf, although we might not need all of it. */
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa6e: 69b8 ldr r0, [r7, #24]
(u8_t *)p->payload + poff, newpbuflen);
801aa70: 68fb ldr r3, [r7, #12]
801aa72: 685a ldr r2, [r3, #4]
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa74: 8ffb ldrh r3, [r7, #62] ; 0x3e
801aa76: 4413 add r3, r2
801aa78: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46
801aa7c: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
801aa80: 9201 str r2, [sp, #4]
801aa82: 9300 str r3, [sp, #0]
801aa84: 4603 mov r3, r0
801aa86: 2241 movs r2, #65 ; 0x41
801aa88: 2000 movs r0, #0
801aa8a: f7f5 fbf3 bl 8010274 <pbuf_alloced_custom>
801aa8e: 6178 str r0, [r7, #20]
if (newpbuf == NULL) {
801aa90: 697b ldr r3, [r7, #20]
801aa92: 2b00 cmp r3, #0
801aa94: d106 bne.n 801aaa4 <ip4_frag+0x17c>
ip_frag_free_pbuf_custom_ref(pcr);
801aa96: 69b8 ldr r0, [r7, #24]
801aa98: f7ff fef6 bl 801a888 <ip_frag_free_pbuf_custom_ref>
pbuf_free(rambuf);
801aa9c: 6a78 ldr r0, [r7, #36] ; 0x24
801aa9e: f7f5 fda3 bl 80105e8 <pbuf_free>
goto memerr;
801aaa2: e073 b.n 801ab8c <ip4_frag+0x264>
}
pbuf_ref(p);
801aaa4: 68f8 ldr r0, [r7, #12]
801aaa6: f7f5 fe45 bl 8010734 <pbuf_ref>
pcr->original = p;
801aaaa: 69bb ldr r3, [r7, #24]
801aaac: 68fa ldr r2, [r7, #12]
801aaae: 615a str r2, [r3, #20]
pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
801aab0: 69bb ldr r3, [r7, #24]
801aab2: 4a3e ldr r2, [pc, #248] ; (801abac <ip4_frag+0x284>)
801aab4: 611a str r2, [r3, #16]
/* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
* so that it is removed when pbuf_dechain is later called on rambuf.
*/
pbuf_cat(rambuf, newpbuf);
801aab6: 6979 ldr r1, [r7, #20]
801aab8: 6a78 ldr r0, [r7, #36] ; 0x24
801aaba: f7f5 fe63 bl 8010784 <pbuf_cat>
left_to_copy = (u16_t)(left_to_copy - newpbuflen);
801aabe: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44
801aac2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aac6: 1ad3 subs r3, r2, r3
801aac8: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if (left_to_copy) {
801aacc: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aad0: 2b00 cmp r3, #0
801aad2: d004 beq.n 801aade <ip4_frag+0x1b6>
poff = 0;
801aad4: 2300 movs r3, #0
801aad6: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801aad8: 68fb ldr r3, [r7, #12]
801aada: 681b ldr r3, [r3, #0]
801aadc: 60fb str r3, [r7, #12]
while (left_to_copy) {
801aade: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aae2: 2b00 cmp r3, #0
801aae4: d196 bne.n 801aa14 <ip4_frag+0xec>
}
}
poff = (u16_t)(poff + newpbuflen);
801aae6: 8ffa ldrh r2, [r7, #62] ; 0x3e
801aae8: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aaec: 4413 add r3, r2
801aaee: 87fb strh r3, [r7, #62] ; 0x3e
#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
/* Correct header */
last = (left <= netif->mtu - IP_HLEN);
801aaf0: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801aaf4: 68bb ldr r3, [r7, #8]
801aaf6: 8d1b ldrh r3, [r3, #40] ; 0x28
801aaf8: 3b14 subs r3, #20
801aafa: 429a cmp r2, r3
801aafc: bfd4 ite le
801aafe: 2301 movle r3, #1
801ab00: 2300 movgt r3, #0
801ab02: b2db uxtb r3, r3
801ab04: 623b str r3, [r7, #32]
/* Set new offset and MF flag */
tmp = (IP_OFFMASK & (ofo));
801ab06: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
801ab0a: f3c3 030c ubfx r3, r3, #0, #13
801ab0e: 87bb strh r3, [r7, #60] ; 0x3c
if (!last || mf_set) {
801ab10: 6a3b ldr r3, [r7, #32]
801ab12: 2b00 cmp r3, #0
801ab14: d002 beq.n 801ab1c <ip4_frag+0x1f4>
801ab16: 6afb ldr r3, [r7, #44] ; 0x2c
801ab18: 2b00 cmp r3, #0
801ab1a: d003 beq.n 801ab24 <ip4_frag+0x1fc>
/* the last fragment has MF set if the input frame had it */
tmp = tmp | IP_MF;
801ab1c: 8fbb ldrh r3, [r7, #60] ; 0x3c
801ab1e: f443 5300 orr.w r3, r3, #8192 ; 0x2000
801ab22: 87bb strh r3, [r7, #60] ; 0x3c
}
IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
801ab24: 8fbb ldrh r3, [r7, #60] ; 0x3c
801ab26: 4618 mov r0, r3
801ab28: f7f4 f9aa bl 800ee80 <lwip_htons>
801ab2c: 4603 mov r3, r0
801ab2e: 461a mov r2, r3
801ab30: 6b3b ldr r3, [r7, #48] ; 0x30
801ab32: 80da strh r2, [r3, #6]
IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
801ab34: 8d7b ldrh r3, [r7, #42] ; 0x2a
801ab36: 3314 adds r3, #20
801ab38: b29b uxth r3, r3
801ab3a: 4618 mov r0, r3
801ab3c: f7f4 f9a0 bl 800ee80 <lwip_htons>
801ab40: 4603 mov r3, r0
801ab42: 461a mov r2, r3
801ab44: 6b3b ldr r3, [r7, #48] ; 0x30
801ab46: 805a strh r2, [r3, #2]
IPH_CHKSUM_SET(iphdr, 0);
801ab48: 6b3b ldr r3, [r7, #48] ; 0x30
801ab4a: 2200 movs r2, #0
801ab4c: 729a strb r2, [r3, #10]
801ab4e: 2200 movs r2, #0
801ab50: 72da strb r2, [r3, #11]
#endif /* CHECKSUM_GEN_IP */
/* No need for separate header pbuf - we allowed room for it in rambuf
* when allocated.
*/
netif->output(netif, rambuf, dest);
801ab52: 68bb ldr r3, [r7, #8]
801ab54: 695b ldr r3, [r3, #20]
801ab56: 687a ldr r2, [r7, #4]
801ab58: 6a79 ldr r1, [r7, #36] ; 0x24
801ab5a: 68b8 ldr r0, [r7, #8]
801ab5c: 4798 blx r3
* recreate it next time round the loop. If we're lucky the hardware
* will have already sent the packet, the free will really free, and
* there will be zero memory penalty.
*/
pbuf_free(rambuf);
801ab5e: 6a78 ldr r0, [r7, #36] ; 0x24
801ab60: f7f5 fd42 bl 80105e8 <pbuf_free>
left = (u16_t)(left - fragsize);
801ab64: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801ab68: 8d7b ldrh r3, [r7, #42] ; 0x2a
801ab6a: 1ad3 subs r3, r2, r3
801ab6c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
ofo = (u16_t)(ofo + nfb);
801ab70: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40
801ab74: 8f7b ldrh r3, [r7, #58] ; 0x3a
801ab76: 4413 add r3, r2
801ab78: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
while (left) {
801ab7c: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
801ab80: 2b00 cmp r3, #0
801ab82: f47f af1a bne.w 801a9ba <ip4_frag+0x92>
}
MIB2_STATS_INC(mib2.ipfragoks);
return ERR_OK;
801ab86: 2300 movs r3, #0
801ab88: e002 b.n 801ab90 <ip4_frag+0x268>
goto memerr;
801ab8a: bf00 nop
memerr:
MIB2_STATS_INC(mib2.ipfragfails);
return ERR_MEM;
801ab8c: f04f 33ff mov.w r3, #4294967295
}
801ab90: 4618 mov r0, r3
801ab92: 3748 adds r7, #72 ; 0x48
801ab94: 46bd mov sp, r7
801ab96: bd80 pop {r7, pc}
801ab98: 0801eb40 .word 0x0801eb40
801ab9c: 0801ed1c .word 0x0801ed1c
801aba0: 0801eb88 .word 0x0801eb88
801aba4: 0801ed38 .word 0x0801ed38
801aba8: 0801ed58 .word 0x0801ed58
801abac: 0801a8c1 .word 0x0801a8c1
0801abb0 <ethernet_input>:
* @see ETHARP_SUPPORT_VLAN
* @see LWIP_HOOK_VLAN_CHECK
*/
err_t
ethernet_input(struct pbuf *p, struct netif *netif)
{
801abb0: b580 push {r7, lr}
801abb2: b086 sub sp, #24
801abb4: af00 add r7, sp, #0
801abb6: 6078 str r0, [r7, #4]
801abb8: 6039 str r1, [r7, #0]
struct eth_hdr *ethhdr;
u16_t type;
#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
u16_t next_hdr_offset = SIZEOF_ETH_HDR;
801abba: 230e movs r3, #14
801abbc: 82fb strh r3, [r7, #22]
#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
LWIP_ASSERT_CORE_LOCKED();
if (p->len <= SIZEOF_ETH_HDR) {
801abbe: 687b ldr r3, [r7, #4]
801abc0: 895b ldrh r3, [r3, #10]
801abc2: 2b0e cmp r3, #14
801abc4: d96e bls.n 801aca4 <ethernet_input+0xf4>
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinerrors);
goto free_and_return;
}
if (p->if_idx == NETIF_NO_INDEX) {
801abc6: 687b ldr r3, [r7, #4]
801abc8: 7bdb ldrb r3, [r3, #15]
801abca: 2b00 cmp r3, #0
801abcc: d106 bne.n 801abdc <ethernet_input+0x2c>
p->if_idx = netif_get_index(netif);
801abce: 683b ldr r3, [r7, #0]
801abd0: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
801abd4: 3301 adds r3, #1
801abd6: b2da uxtb r2, r3
801abd8: 687b ldr r3, [r7, #4]
801abda: 73da strb r2, [r3, #15]
}
/* points to packet payload, which starts with an Ethernet header */
ethhdr = (struct eth_hdr *)p->payload;
801abdc: 687b ldr r3, [r7, #4]
801abde: 685b ldr r3, [r3, #4]
801abe0: 613b str r3, [r7, #16]
(unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
(unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2],
(unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5],
lwip_htons(ethhdr->type)));
type = ethhdr->type;
801abe2: 693b ldr r3, [r7, #16]
801abe4: 7b1a ldrb r2, [r3, #12]
801abe6: 7b5b ldrb r3, [r3, #13]
801abe8: 021b lsls r3, r3, #8
801abea: 4313 orrs r3, r2
801abec: 81fb strh r3, [r7, #14]
#if LWIP_ARP_FILTER_NETIF
netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
#endif /* LWIP_ARP_FILTER_NETIF*/
if (ethhdr->dest.addr[0] & 1) {
801abee: 693b ldr r3, [r7, #16]
801abf0: 781b ldrb r3, [r3, #0]
801abf2: f003 0301 and.w r3, r3, #1
801abf6: 2b00 cmp r3, #0
801abf8: d023 beq.n 801ac42 <ethernet_input+0x92>
/* this might be a multicast or broadcast packet */
if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
801abfa: 693b ldr r3, [r7, #16]
801abfc: 781b ldrb r3, [r3, #0]
801abfe: 2b01 cmp r3, #1
801ac00: d10f bne.n 801ac22 <ethernet_input+0x72>
#if LWIP_IPV4
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801ac02: 693b ldr r3, [r7, #16]
801ac04: 785b ldrb r3, [r3, #1]
801ac06: 2b00 cmp r3, #0
801ac08: d11b bne.n 801ac42 <ethernet_input+0x92>
(ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
801ac0a: 693b ldr r3, [r7, #16]
801ac0c: 789b ldrb r3, [r3, #2]
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801ac0e: 2b5e cmp r3, #94 ; 0x5e
801ac10: d117 bne.n 801ac42 <ethernet_input+0x92>
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
801ac12: 687b ldr r3, [r7, #4]
801ac14: 7b5b ldrb r3, [r3, #13]
801ac16: f043 0310 orr.w r3, r3, #16
801ac1a: b2da uxtb r2, r3
801ac1c: 687b ldr r3, [r7, #4]
801ac1e: 735a strb r2, [r3, #13]
801ac20: e00f b.n 801ac42 <ethernet_input+0x92>
(ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
}
#endif /* LWIP_IPV6 */
else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
801ac22: 693b ldr r3, [r7, #16]
801ac24: 2206 movs r2, #6
801ac26: 4928 ldr r1, [pc, #160] ; (801acc8 <ethernet_input+0x118>)
801ac28: 4618 mov r0, r3
801ac2a: f000 f9d1 bl 801afd0 <memcmp>
801ac2e: 4603 mov r3, r0
801ac30: 2b00 cmp r3, #0
801ac32: d106 bne.n 801ac42 <ethernet_input+0x92>
/* mark the pbuf as link-layer broadcast */
p->flags |= PBUF_FLAG_LLBCAST;
801ac34: 687b ldr r3, [r7, #4]
801ac36: 7b5b ldrb r3, [r3, #13]
801ac38: f043 0308 orr.w r3, r3, #8
801ac3c: b2da uxtb r2, r3
801ac3e: 687b ldr r3, [r7, #4]
801ac40: 735a strb r2, [r3, #13]
}
}
switch (type) {
801ac42: 89fb ldrh r3, [r7, #14]
801ac44: 2b08 cmp r3, #8
801ac46: d003 beq.n 801ac50 <ethernet_input+0xa0>
801ac48: f5b3 6fc1 cmp.w r3, #1544 ; 0x608
801ac4c: d014 beq.n 801ac78 <ethernet_input+0xc8>
}
#endif
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
goto free_and_return;
801ac4e: e032 b.n 801acb6 <ethernet_input+0x106>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801ac50: 683b ldr r3, [r7, #0]
801ac52: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac56: f003 0308 and.w r3, r3, #8
801ac5a: 2b00 cmp r3, #0
801ac5c: d024 beq.n 801aca8 <ethernet_input+0xf8>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac5e: 8afb ldrh r3, [r7, #22]
801ac60: 4619 mov r1, r3
801ac62: 6878 ldr r0, [r7, #4]
801ac64: f7f5 fc3a bl 80104dc <pbuf_remove_header>
801ac68: 4603 mov r3, r0
801ac6a: 2b00 cmp r3, #0
801ac6c: d11e bne.n 801acac <ethernet_input+0xfc>
ip4_input(p, netif);
801ac6e: 6839 ldr r1, [r7, #0]
801ac70: 6878 ldr r0, [r7, #4]
801ac72: f7fe ff0f bl 8019a94 <ip4_input>
break;
801ac76: e013 b.n 801aca0 <ethernet_input+0xf0>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801ac78: 683b ldr r3, [r7, #0]
801ac7a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac7e: f003 0308 and.w r3, r3, #8
801ac82: 2b00 cmp r3, #0
801ac84: d014 beq.n 801acb0 <ethernet_input+0x100>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac86: 8afb ldrh r3, [r7, #22]
801ac88: 4619 mov r1, r3
801ac8a: 6878 ldr r0, [r7, #4]
801ac8c: f7f5 fc26 bl 80104dc <pbuf_remove_header>
801ac90: 4603 mov r3, r0
801ac92: 2b00 cmp r3, #0
801ac94: d10e bne.n 801acb4 <ethernet_input+0x104>
etharp_input(p, netif);
801ac96: 6839 ldr r1, [r7, #0]
801ac98: 6878 ldr r0, [r7, #4]
801ac9a: f7fe f8ab bl 8018df4 <etharp_input>
break;
801ac9e: bf00 nop
}
/* This means the pbuf is freed or consumed,
so the caller doesn't have to free it again */
return ERR_OK;
801aca0: 2300 movs r3, #0
801aca2: e00c b.n 801acbe <ethernet_input+0x10e>
goto free_and_return;
801aca4: bf00 nop
801aca6: e006 b.n 801acb6 <ethernet_input+0x106>
goto free_and_return;
801aca8: bf00 nop
801acaa: e004 b.n 801acb6 <ethernet_input+0x106>
goto free_and_return;
801acac: bf00 nop
801acae: e002 b.n 801acb6 <ethernet_input+0x106>
goto free_and_return;
801acb0: bf00 nop
801acb2: e000 b.n 801acb6 <ethernet_input+0x106>
goto free_and_return;
801acb4: bf00 nop
free_and_return:
pbuf_free(p);
801acb6: 6878 ldr r0, [r7, #4]
801acb8: f7f5 fc96 bl 80105e8 <pbuf_free>
return ERR_OK;
801acbc: 2300 movs r3, #0
}
801acbe: 4618 mov r0, r3
801acc0: 3718 adds r7, #24
801acc2: 46bd mov sp, r7
801acc4: bd80 pop {r7, pc}
801acc6: bf00 nop
801acc8: 08020e70 .word 0x08020e70
0801accc <ethernet_output>:
* @return ERR_OK if the packet was sent, any other err_t on failure
*/
err_t
ethernet_output(struct netif * netif, struct pbuf * p,
const struct eth_addr * src, const struct eth_addr * dst,
u16_t eth_type) {
801accc: b580 push {r7, lr}
801acce: b086 sub sp, #24
801acd0: af00 add r7, sp, #0
801acd2: 60f8 str r0, [r7, #12]
801acd4: 60b9 str r1, [r7, #8]
801acd6: 607a str r2, [r7, #4]
801acd8: 603b str r3, [r7, #0]
struct eth_hdr *ethhdr;
u16_t eth_type_be = lwip_htons(eth_type);
801acda: 8c3b ldrh r3, [r7, #32]
801acdc: 4618 mov r0, r3
801acde: f7f4 f8cf bl 800ee80 <lwip_htons>
801ace2: 4603 mov r3, r0
801ace4: 82fb strh r3, [r7, #22]
eth_type_be = PP_HTONS(ETHTYPE_VLAN);
} else
#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
{
if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
801ace6: 210e movs r1, #14
801ace8: 68b8 ldr r0, [r7, #8]
801acea: f7f5 fbe7 bl 80104bc <pbuf_add_header>
801acee: 4603 mov r3, r0
801acf0: 2b00 cmp r3, #0
801acf2: d125 bne.n 801ad40 <ethernet_output+0x74>
}
}
LWIP_ASSERT_CORE_LOCKED();
ethhdr = (struct eth_hdr *)p->payload;
801acf4: 68bb ldr r3, [r7, #8]
801acf6: 685b ldr r3, [r3, #4]
801acf8: 613b str r3, [r7, #16]
ethhdr->type = eth_type_be;
801acfa: 693b ldr r3, [r7, #16]
801acfc: 8afa ldrh r2, [r7, #22]
801acfe: 819a strh r2, [r3, #12]
SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
801ad00: 693b ldr r3, [r7, #16]
801ad02: 2206 movs r2, #6
801ad04: 6839 ldr r1, [r7, #0]
801ad06: 4618 mov r0, r3
801ad08: f000 f971 bl 801afee <memcpy>
SMEMCPY(&ethhdr->src, src, ETH_HWADDR_LEN);
801ad0c: 693b ldr r3, [r7, #16]
801ad0e: 3306 adds r3, #6
801ad10: 2206 movs r2, #6
801ad12: 6879 ldr r1, [r7, #4]
801ad14: 4618 mov r0, r3
801ad16: f000 f96a bl 801afee <memcpy>
LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
801ad1a: 68fb ldr r3, [r7, #12]
801ad1c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
801ad20: 2b06 cmp r3, #6
801ad22: d006 beq.n 801ad32 <ethernet_output+0x66>
801ad24: 4b0a ldr r3, [pc, #40] ; (801ad50 <ethernet_output+0x84>)
801ad26: f240 1233 movw r2, #307 ; 0x133
801ad2a: 490a ldr r1, [pc, #40] ; (801ad54 <ethernet_output+0x88>)
801ad2c: 480a ldr r0, [pc, #40] ; (801ad58 <ethernet_output+0x8c>)
801ad2e: f000 f971 bl 801b014 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
("ethernet_output: sending packet %p\n", (void *)p));
/* send the packet */
return netif->linkoutput(netif, p);
801ad32: 68fb ldr r3, [r7, #12]
801ad34: 699b ldr r3, [r3, #24]
801ad36: 68b9 ldr r1, [r7, #8]
801ad38: 68f8 ldr r0, [r7, #12]
801ad3a: 4798 blx r3
801ad3c: 4603 mov r3, r0
801ad3e: e002 b.n 801ad46 <ethernet_output+0x7a>
goto pbuf_header_failed;
801ad40: bf00 nop
pbuf_header_failed:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("ethernet_output: could not allocate room for header.\n"));
LINK_STATS_INC(link.lenerr);
return ERR_BUF;
801ad42: f06f 0301 mvn.w r3, #1
}
801ad46: 4618 mov r0, r3
801ad48: 3718 adds r7, #24
801ad4a: 46bd mov sp, r7
801ad4c: bd80 pop {r7, pc}
801ad4e: bf00 nop
801ad50: 0801ed68 .word 0x0801ed68
801ad54: 0801eda0 .word 0x0801eda0
801ad58: 0801edd4 .word 0x0801edd4
0801ad5c <sys_mbox_new>:
#endif
/*-----------------------------------------------------------------------------------*/
// Creates an empty mailbox.
err_t sys_mbox_new(sys_mbox_t *mbox, int size)
{
801ad5c: b580 push {r7, lr}
801ad5e: b086 sub sp, #24
801ad60: af00 add r7, sp, #0
801ad62: 6078 str r0, [r7, #4]
801ad64: 6039 str r1, [r7, #0]
#if (osCMSIS < 0x20000U)
osMessageQDef(QUEUE, size, void *);
801ad66: 683b ldr r3, [r7, #0]
801ad68: 60bb str r3, [r7, #8]
801ad6a: 2304 movs r3, #4
801ad6c: 60fb str r3, [r7, #12]
801ad6e: 2300 movs r3, #0
801ad70: 613b str r3, [r7, #16]
801ad72: 2300 movs r3, #0
801ad74: 617b str r3, [r7, #20]
*mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
801ad76: f107 0308 add.w r3, r7, #8
801ad7a: 2100 movs r1, #0
801ad7c: 4618 mov r0, r3
801ad7e: f7f0 fffd bl 800bd7c <osMessageCreate>
801ad82: 4602 mov r2, r0
801ad84: 687b ldr r3, [r7, #4]
801ad86: 601a str r2, [r3, #0]
if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
{
lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
}
#endif /* SYS_STATS */
if(*mbox == NULL)
801ad88: 687b ldr r3, [r7, #4]
801ad8a: 681b ldr r3, [r3, #0]
801ad8c: 2b00 cmp r3, #0
801ad8e: d102 bne.n 801ad96 <sys_mbox_new+0x3a>
return ERR_MEM;
801ad90: f04f 33ff mov.w r3, #4294967295
801ad94: e000 b.n 801ad98 <sys_mbox_new+0x3c>
return ERR_OK;
801ad96: 2300 movs r3, #0
}
801ad98: 4618 mov r0, r3
801ad9a: 3718 adds r7, #24
801ad9c: 46bd mov sp, r7
801ad9e: bd80 pop {r7, pc}
0801ada0 <sys_mbox_trypost>:
/*-----------------------------------------------------------------------------------*/
// Try to post the "msg" to the mailbox.
err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
{
801ada0: b580 push {r7, lr}
801ada2: b084 sub sp, #16
801ada4: af00 add r7, sp, #0
801ada6: 6078 str r0, [r7, #4]
801ada8: 6039 str r1, [r7, #0]
err_t result;
#if (osCMSIS < 0x20000U)
if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
801adaa: 687b ldr r3, [r7, #4]
801adac: 681b ldr r3, [r3, #0]
801adae: 6839 ldr r1, [r7, #0]
801adb0: 2200 movs r2, #0
801adb2: 4618 mov r0, r3
801adb4: f7f1 f80c bl 800bdd0 <osMessagePut>
801adb8: 4603 mov r3, r0
801adba: 2b00 cmp r3, #0
801adbc: d102 bne.n 801adc4 <sys_mbox_trypost+0x24>
#else
if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
#endif
{
result = ERR_OK;
801adbe: 2300 movs r3, #0
801adc0: 73fb strb r3, [r7, #15]
801adc2: e001 b.n 801adc8 <sys_mbox_trypost+0x28>
}
else
{
// could not post, queue must be full
result = ERR_MEM;
801adc4: 23ff movs r3, #255 ; 0xff
801adc6: 73fb strb r3, [r7, #15]
#if SYS_STATS
lwip_stats.sys.mbox.err++;
#endif /* SYS_STATS */
}
return result;
801adc8: f997 300f ldrsb.w r3, [r7, #15]
}
801adcc: 4618 mov r0, r3
801adce: 3710 adds r7, #16
801add0: 46bd mov sp, r7
801add2: bd80 pop {r7, pc}
0801add4 <sys_arch_mbox_fetch>:
Note that a function with a similar name, sys_mbox_fetch(), is
implemented by lwIP.
*/
u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
{
801add4: b580 push {r7, lr}
801add6: b08c sub sp, #48 ; 0x30
801add8: af00 add r7, sp, #0
801adda: 61f8 str r0, [r7, #28]
801addc: 61b9 str r1, [r7, #24]
801adde: 617a str r2, [r7, #20]
#if (osCMSIS < 0x20000U)
osEvent event;
uint32_t starttime = osKernelSysTick();
801ade0: f7f0 fdfb bl 800b9da <osKernelSysTick>
801ade4: 62f8 str r0, [r7, #44] ; 0x2c
#else
osStatus_t status;
uint32_t starttime = osKernelGetTickCount();
#endif
if(timeout != 0)
801ade6: 697b ldr r3, [r7, #20]
801ade8: 2b00 cmp r3, #0
801adea: d017 beq.n 801ae1c <sys_arch_mbox_fetch+0x48>
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, timeout);
801adec: 69fb ldr r3, [r7, #28]
801adee: 6819 ldr r1, [r3, #0]
801adf0: f107 0320 add.w r3, r7, #32
801adf4: 697a ldr r2, [r7, #20]
801adf6: 4618 mov r0, r3
801adf8: f7f1 f82a bl 800be50 <osMessageGet>
if(event.status == osEventMessage)
801adfc: 6a3b ldr r3, [r7, #32]
801adfe: 2b10 cmp r3, #16
801ae00: d109 bne.n 801ae16 <sys_arch_mbox_fetch+0x42>
{
*msg = (void *)event.value.v;
801ae02: 6a7b ldr r3, [r7, #36] ; 0x24
801ae04: 461a mov r2, r3
801ae06: 69bb ldr r3, [r7, #24]
801ae08: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801ae0a: f7f0 fde6 bl 800b9da <osKernelSysTick>
801ae0e: 4602 mov r2, r0
801ae10: 6afb ldr r3, [r7, #44] ; 0x2c
801ae12: 1ad3 subs r3, r2, r3
801ae14: e019 b.n 801ae4a <sys_arch_mbox_fetch+0x76>
return (osKernelGetTickCount() - starttime);
}
#endif
else
{
return SYS_ARCH_TIMEOUT;
801ae16: f04f 33ff mov.w r3, #4294967295
801ae1a: e016 b.n 801ae4a <sys_arch_mbox_fetch+0x76>
}
}
else
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, osWaitForever);
801ae1c: 69fb ldr r3, [r7, #28]
801ae1e: 6819 ldr r1, [r3, #0]
801ae20: 463b mov r3, r7
801ae22: f04f 32ff mov.w r2, #4294967295
801ae26: 4618 mov r0, r3
801ae28: f7f1 f812 bl 800be50 <osMessageGet>
801ae2c: f107 0320 add.w r3, r7, #32
801ae30: 463a mov r2, r7
801ae32: ca07 ldmia r2, {r0, r1, r2}
801ae34: e883 0007 stmia.w r3, {r0, r1, r2}
*msg = (void *)event.value.v;
801ae38: 6a7b ldr r3, [r7, #36] ; 0x24
801ae3a: 461a mov r2, r3
801ae3c: 69bb ldr r3, [r7, #24]
801ae3e: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801ae40: f7f0 fdcb bl 800b9da <osKernelSysTick>
801ae44: 4602 mov r2, r0
801ae46: 6afb ldr r3, [r7, #44] ; 0x2c
801ae48: 1ad3 subs r3, r2, r3
#else
osMessageQueueGet(*mbox, msg, 0, osWaitForever );
return (osKernelGetTickCount() - starttime);
#endif
}
}
801ae4a: 4618 mov r0, r3
801ae4c: 3730 adds r7, #48 ; 0x30
801ae4e: 46bd mov sp, r7
801ae50: bd80 pop {r7, pc}
0801ae52 <sys_mbox_valid>:
return SYS_MBOX_EMPTY;
}
}
/*----------------------------------------------------------------------------------*/
int sys_mbox_valid(sys_mbox_t *mbox)
{
801ae52: b480 push {r7}
801ae54: b083 sub sp, #12
801ae56: af00 add r7, sp, #0
801ae58: 6078 str r0, [r7, #4]
if (*mbox == SYS_MBOX_NULL)
801ae5a: 687b ldr r3, [r7, #4]
801ae5c: 681b ldr r3, [r3, #0]
801ae5e: 2b00 cmp r3, #0
801ae60: d101 bne.n 801ae66 <sys_mbox_valid+0x14>
return 0;
801ae62: 2300 movs r3, #0
801ae64: e000 b.n 801ae68 <sys_mbox_valid+0x16>
else
return 1;
801ae66: 2301 movs r3, #1
}
801ae68: 4618 mov r0, r3
801ae6a: 370c adds r7, #12
801ae6c: 46bd mov sp, r7
801ae6e: f85d 7b04 ldr.w r7, [sp], #4
801ae72: 4770 bx lr
0801ae74 <sys_init>:
#else
osMutexId_t lwip_sys_mutex;
#endif
// Initialize sys arch
void sys_init(void)
{
801ae74: b580 push {r7, lr}
801ae76: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
801ae78: 4803 ldr r0, [pc, #12] ; (801ae88 <sys_init+0x14>)
801ae7a: f7f0 fe1e bl 800baba <osMutexCreate>
801ae7e: 4602 mov r2, r0
801ae80: 4b02 ldr r3, [pc, #8] ; (801ae8c <sys_init+0x18>)
801ae82: 601a str r2, [r3, #0]
#else
lwip_sys_mutex = osMutexNew(NULL);
#endif
}
801ae84: bf00 nop
801ae86: bd80 pop {r7, pc}
801ae88: 08020e80 .word 0x08020e80
801ae8c: 2000f608 .word 0x2000f608
0801ae90 <sys_mutex_new>:
/* Mutexes*/
/*-----------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------*/
#if LWIP_COMPAT_MUTEX == 0
/* Create a new mutex*/
err_t sys_mutex_new(sys_mutex_t *mutex) {
801ae90: b580 push {r7, lr}
801ae92: b084 sub sp, #16
801ae94: af00 add r7, sp, #0
801ae96: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexDef(MUTEX);
801ae98: 2300 movs r3, #0
801ae9a: 60bb str r3, [r7, #8]
801ae9c: 2300 movs r3, #0
801ae9e: 60fb str r3, [r7, #12]
*mutex = osMutexCreate(osMutex(MUTEX));
801aea0: f107 0308 add.w r3, r7, #8
801aea4: 4618 mov r0, r3
801aea6: f7f0 fe08 bl 800baba <osMutexCreate>
801aeaa: 4602 mov r2, r0
801aeac: 687b ldr r3, [r7, #4]
801aeae: 601a str r2, [r3, #0]
#else
*mutex = osMutexNew(NULL);
#endif
if(*mutex == NULL)
801aeb0: 687b ldr r3, [r7, #4]
801aeb2: 681b ldr r3, [r3, #0]
801aeb4: 2b00 cmp r3, #0
801aeb6: d102 bne.n 801aebe <sys_mutex_new+0x2e>
{
#if SYS_STATS
++lwip_stats.sys.mutex.err;
#endif /* SYS_STATS */
return ERR_MEM;
801aeb8: f04f 33ff mov.w r3, #4294967295
801aebc: e000 b.n 801aec0 <sys_mutex_new+0x30>
++lwip_stats.sys.mutex.used;
if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
}
#endif /* SYS_STATS */
return ERR_OK;
801aebe: 2300 movs r3, #0
}
801aec0: 4618 mov r0, r3
801aec2: 3710 adds r7, #16
801aec4: 46bd mov sp, r7
801aec6: bd80 pop {r7, pc}
0801aec8 <sys_mutex_lock>:
osMutexDelete(*mutex);
}
/*-----------------------------------------------------------------------------------*/
/* Lock a mutex*/
void sys_mutex_lock(sys_mutex_t *mutex)
{
801aec8: b580 push {r7, lr}
801aeca: b082 sub sp, #8
801aecc: af00 add r7, sp, #0
801aece: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexWait(*mutex, osWaitForever);
801aed0: 687b ldr r3, [r7, #4]
801aed2: 681b ldr r3, [r3, #0]
801aed4: f04f 31ff mov.w r1, #4294967295
801aed8: 4618 mov r0, r3
801aeda: f7f0 fe07 bl 800baec <osMutexWait>
#else
osMutexAcquire(*mutex, osWaitForever);
#endif
}
801aede: bf00 nop
801aee0: 3708 adds r7, #8
801aee2: 46bd mov sp, r7
801aee4: bd80 pop {r7, pc}
0801aee6 <sys_mutex_unlock>:
/*-----------------------------------------------------------------------------------*/
/* Unlock a mutex*/
void sys_mutex_unlock(sys_mutex_t *mutex)
{
801aee6: b580 push {r7, lr}
801aee8: b082 sub sp, #8
801aeea: af00 add r7, sp, #0
801aeec: 6078 str r0, [r7, #4]
osMutexRelease(*mutex);
801aeee: 687b ldr r3, [r7, #4]
801aef0: 681b ldr r3, [r3, #0]
801aef2: 4618 mov r0, r3
801aef4: f7f0 fe48 bl 800bb88 <osMutexRelease>
}
801aef8: bf00 nop
801aefa: 3708 adds r7, #8
801aefc: 46bd mov sp, r7
801aefe: bd80 pop {r7, pc}
0801af00 <sys_thread_new>:
function "thread()". The "arg" argument will be passed as an argument to the
thread() function. The id of the new thread is returned. Both the id and
the priority are system dependent.
*/
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
{
801af00: b580 push {r7, lr}
801af02: b08c sub sp, #48 ; 0x30
801af04: af00 add r7, sp, #0
801af06: 60f8 str r0, [r7, #12]
801af08: 60b9 str r1, [r7, #8]
801af0a: 607a str r2, [r7, #4]
801af0c: 603b str r3, [r7, #0]
#if (osCMSIS < 0x20000U)
const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
801af0e: f107 0314 add.w r3, r7, #20
801af12: 2200 movs r2, #0
801af14: 601a str r2, [r3, #0]
801af16: 605a str r2, [r3, #4]
801af18: 609a str r2, [r3, #8]
801af1a: 60da str r2, [r3, #12]
801af1c: 611a str r2, [r3, #16]
801af1e: 615a str r2, [r3, #20]
801af20: 619a str r2, [r3, #24]
801af22: 68fb ldr r3, [r7, #12]
801af24: 617b str r3, [r7, #20]
801af26: 68bb ldr r3, [r7, #8]
801af28: 61bb str r3, [r7, #24]
801af2a: 6bbb ldr r3, [r7, #56] ; 0x38
801af2c: b21b sxth r3, r3
801af2e: 83bb strh r3, [r7, #28]
801af30: 683b ldr r3, [r7, #0]
801af32: 627b str r3, [r7, #36] ; 0x24
return osThreadCreate(&os_thread_def, arg);
801af34: f107 0314 add.w r3, r7, #20
801af38: 6879 ldr r1, [r7, #4]
801af3a: 4618 mov r0, r3
801af3c: f7f0 fd5d bl 800b9fa <osThreadCreate>
801af40: 4603 mov r3, r0
.stack_size = stacksize,
.priority = (osPriority_t)prio,
};
return osThreadNew(thread, arg, &attributes);
#endif
}
801af42: 4618 mov r0, r3
801af44: 3730 adds r7, #48 ; 0x30
801af46: 46bd mov sp, r7
801af48: bd80 pop {r7, pc}
...
0801af4c <sys_arch_protect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
sys_prot_t sys_arch_protect(void)
{
801af4c: b580 push {r7, lr}
801af4e: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
osMutexWait(lwip_sys_mutex, osWaitForever);
801af50: 4b04 ldr r3, [pc, #16] ; (801af64 <sys_arch_protect+0x18>)
801af52: 681b ldr r3, [r3, #0]
801af54: f04f 31ff mov.w r1, #4294967295
801af58: 4618 mov r0, r3
801af5a: f7f0 fdc7 bl 800baec <osMutexWait>
#else
osMutexAcquire(lwip_sys_mutex, osWaitForever);
#endif
return (sys_prot_t)1;
801af5e: 2301 movs r3, #1
}
801af60: 4618 mov r0, r3
801af62: bd80 pop {r7, pc}
801af64: 2000f608 .word 0x2000f608
0801af68 <sys_arch_unprotect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
void sys_arch_unprotect(sys_prot_t pval)
{
801af68: b580 push {r7, lr}
801af6a: b082 sub sp, #8
801af6c: af00 add r7, sp, #0
801af6e: 6078 str r0, [r7, #4]
( void ) pval;
osMutexRelease(lwip_sys_mutex);
801af70: 4b04 ldr r3, [pc, #16] ; (801af84 <sys_arch_unprotect+0x1c>)
801af72: 681b ldr r3, [r3, #0]
801af74: 4618 mov r0, r3
801af76: f7f0 fe07 bl 800bb88 <osMutexRelease>
}
801af7a: bf00 nop
801af7c: 3708 adds r7, #8
801af7e: 46bd mov sp, r7
801af80: bd80 pop {r7, pc}
801af82: bf00 nop
801af84: 2000f608 .word 0x2000f608
0801af88 <__libc_init_array>:
801af88: b570 push {r4, r5, r6, lr}
801af8a: 4e0d ldr r6, [pc, #52] ; (801afc0 <__libc_init_array+0x38>)
801af8c: 4c0d ldr r4, [pc, #52] ; (801afc4 <__libc_init_array+0x3c>)
801af8e: 1ba4 subs r4, r4, r6
801af90: 10a4 asrs r4, r4, #2
801af92: 2500 movs r5, #0
801af94: 42a5 cmp r5, r4
801af96: d109 bne.n 801afac <__libc_init_array+0x24>
801af98: 4e0b ldr r6, [pc, #44] ; (801afc8 <__libc_init_array+0x40>)
801af9a: 4c0c ldr r4, [pc, #48] ; (801afcc <__libc_init_array+0x44>)
801af9c: f000 ff5a bl 801be54 <_init>
801afa0: 1ba4 subs r4, r4, r6
801afa2: 10a4 asrs r4, r4, #2
801afa4: 2500 movs r5, #0
801afa6: 42a5 cmp r5, r4
801afa8: d105 bne.n 801afb6 <__libc_init_array+0x2e>
801afaa: bd70 pop {r4, r5, r6, pc}
801afac: f856 3025 ldr.w r3, [r6, r5, lsl #2]
801afb0: 4798 blx r3
801afb2: 3501 adds r5, #1
801afb4: e7ee b.n 801af94 <__libc_init_array+0xc>
801afb6: f856 3025 ldr.w r3, [r6, r5, lsl #2]
801afba: 4798 blx r3
801afbc: 3501 adds r5, #1
801afbe: e7f2 b.n 801afa6 <__libc_init_array+0x1e>
801afc0: 08020f28 .word 0x08020f28
801afc4: 08020f28 .word 0x08020f28
801afc8: 08020f28 .word 0x08020f28
801afcc: 08020f2c .word 0x08020f2c
0801afd0 <memcmp>:
801afd0: b530 push {r4, r5, lr}
801afd2: 2400 movs r4, #0
801afd4: 42a2 cmp r2, r4
801afd6: d101 bne.n 801afdc <memcmp+0xc>
801afd8: 2000 movs r0, #0
801afda: e007 b.n 801afec <memcmp+0x1c>
801afdc: 5d03 ldrb r3, [r0, r4]
801afde: 3401 adds r4, #1
801afe0: 190d adds r5, r1, r4
801afe2: f815 5c01 ldrb.w r5, [r5, #-1]
801afe6: 42ab cmp r3, r5
801afe8: d0f4 beq.n 801afd4 <memcmp+0x4>
801afea: 1b58 subs r0, r3, r5
801afec: bd30 pop {r4, r5, pc}
0801afee <memcpy>:
801afee: b510 push {r4, lr}
801aff0: 1e43 subs r3, r0, #1
801aff2: 440a add r2, r1
801aff4: 4291 cmp r1, r2
801aff6: d100 bne.n 801affa <memcpy+0xc>
801aff8: bd10 pop {r4, pc}
801affa: f811 4b01 ldrb.w r4, [r1], #1
801affe: f803 4f01 strb.w r4, [r3, #1]!
801b002: e7f7 b.n 801aff4 <memcpy+0x6>
0801b004 <memset>:
801b004: 4402 add r2, r0
801b006: 4603 mov r3, r0
801b008: 4293 cmp r3, r2
801b00a: d100 bne.n 801b00e <memset+0xa>
801b00c: 4770 bx lr
801b00e: f803 1b01 strb.w r1, [r3], #1
801b012: e7f9 b.n 801b008 <memset+0x4>
0801b014 <iprintf>:
801b014: b40f push {r0, r1, r2, r3}
801b016: 4b0a ldr r3, [pc, #40] ; (801b040 <iprintf+0x2c>)
801b018: b513 push {r0, r1, r4, lr}
801b01a: 681c ldr r4, [r3, #0]
801b01c: b124 cbz r4, 801b028 <iprintf+0x14>
801b01e: 69a3 ldr r3, [r4, #24]
801b020: b913 cbnz r3, 801b028 <iprintf+0x14>
801b022: 4620 mov r0, r4
801b024: f000 f882 bl 801b12c <__sinit>
801b028: ab05 add r3, sp, #20
801b02a: 9a04 ldr r2, [sp, #16]
801b02c: 68a1 ldr r1, [r4, #8]
801b02e: 9301 str r3, [sp, #4]
801b030: 4620 mov r0, r4
801b032: f000 f9df bl 801b3f4 <_vfiprintf_r>
801b036: b002 add sp, #8
801b038: e8bd 4010 ldmia.w sp!, {r4, lr}
801b03c: b004 add sp, #16
801b03e: 4770 bx lr
801b040: 20000084 .word 0x20000084
0801b044 <rand>:
801b044: b538 push {r3, r4, r5, lr}
801b046: 4b13 ldr r3, [pc, #76] ; (801b094 <rand+0x50>)
801b048: 681c ldr r4, [r3, #0]
801b04a: 6ba3 ldr r3, [r4, #56] ; 0x38
801b04c: b97b cbnz r3, 801b06e <rand+0x2a>
801b04e: 2018 movs r0, #24
801b050: f000 f8f6 bl 801b240 <malloc>
801b054: 4a10 ldr r2, [pc, #64] ; (801b098 <rand+0x54>)
801b056: 4b11 ldr r3, [pc, #68] ; (801b09c <rand+0x58>)
801b058: 63a0 str r0, [r4, #56] ; 0x38
801b05a: e9c0 2300 strd r2, r3, [r0]
801b05e: 4b10 ldr r3, [pc, #64] ; (801b0a0 <rand+0x5c>)
801b060: 6083 str r3, [r0, #8]
801b062: 230b movs r3, #11
801b064: 8183 strh r3, [r0, #12]
801b066: 2201 movs r2, #1
801b068: 2300 movs r3, #0
801b06a: e9c0 2304 strd r2, r3, [r0, #16]
801b06e: 6ba1 ldr r1, [r4, #56] ; 0x38
801b070: 480c ldr r0, [pc, #48] ; (801b0a4 <rand+0x60>)
801b072: 690a ldr r2, [r1, #16]
801b074: 694b ldr r3, [r1, #20]
801b076: 4c0c ldr r4, [pc, #48] ; (801b0a8 <rand+0x64>)
801b078: 4350 muls r0, r2
801b07a: fb04 0003 mla r0, r4, r3, r0
801b07e: fba2 2304 umull r2, r3, r2, r4
801b082: 4403 add r3, r0
801b084: 1c54 adds r4, r2, #1
801b086: f143 0500 adc.w r5, r3, #0
801b08a: e9c1 4504 strd r4, r5, [r1, #16]
801b08e: f025 4000 bic.w r0, r5, #2147483648 ; 0x80000000
801b092: bd38 pop {r3, r4, r5, pc}
801b094: 20000084 .word 0x20000084
801b098: abcd330e .word 0xabcd330e
801b09c: e66d1234 .word 0xe66d1234
801b0a0: 0005deec .word 0x0005deec
801b0a4: 5851f42d .word 0x5851f42d
801b0a8: 4c957f2d .word 0x4c957f2d
0801b0ac <std>:
801b0ac: 2300 movs r3, #0
801b0ae: b510 push {r4, lr}
801b0b0: 4604 mov r4, r0
801b0b2: e9c0 3300 strd r3, r3, [r0]
801b0b6: 6083 str r3, [r0, #8]
801b0b8: 8181 strh r1, [r0, #12]
801b0ba: 6643 str r3, [r0, #100] ; 0x64
801b0bc: 81c2 strh r2, [r0, #14]
801b0be: e9c0 3304 strd r3, r3, [r0, #16]
801b0c2: 6183 str r3, [r0, #24]
801b0c4: 4619 mov r1, r3
801b0c6: 2208 movs r2, #8
801b0c8: 305c adds r0, #92 ; 0x5c
801b0ca: f7ff ff9b bl 801b004 <memset>
801b0ce: 4b05 ldr r3, [pc, #20] ; (801b0e4 <std+0x38>)
801b0d0: 6263 str r3, [r4, #36] ; 0x24
801b0d2: 4b05 ldr r3, [pc, #20] ; (801b0e8 <std+0x3c>)
801b0d4: 62a3 str r3, [r4, #40] ; 0x28
801b0d6: 4b05 ldr r3, [pc, #20] ; (801b0ec <std+0x40>)
801b0d8: 62e3 str r3, [r4, #44] ; 0x2c
801b0da: 4b05 ldr r3, [pc, #20] ; (801b0f0 <std+0x44>)
801b0dc: 6224 str r4, [r4, #32]
801b0de: 6323 str r3, [r4, #48] ; 0x30
801b0e0: bd10 pop {r4, pc}
801b0e2: bf00 nop
801b0e4: 0801b951 .word 0x0801b951
801b0e8: 0801b973 .word 0x0801b973
801b0ec: 0801b9ab .word 0x0801b9ab
801b0f0: 0801b9cf .word 0x0801b9cf
0801b0f4 <_cleanup_r>:
801b0f4: 4901 ldr r1, [pc, #4] ; (801b0fc <_cleanup_r+0x8>)
801b0f6: f000 b885 b.w 801b204 <_fwalk_reent>
801b0fa: bf00 nop
801b0fc: 0801bca9 .word 0x0801bca9
0801b100 <__sfmoreglue>:
801b100: b570 push {r4, r5, r6, lr}
801b102: 1e4a subs r2, r1, #1
801b104: 2568 movs r5, #104 ; 0x68
801b106: 4355 muls r5, r2
801b108: 460e mov r6, r1
801b10a: f105 0174 add.w r1, r5, #116 ; 0x74
801b10e: f000 f8ed bl 801b2ec <_malloc_r>
801b112: 4604 mov r4, r0
801b114: b140 cbz r0, 801b128 <__sfmoreglue+0x28>
801b116: 2100 movs r1, #0
801b118: e9c0 1600 strd r1, r6, [r0]
801b11c: 300c adds r0, #12
801b11e: 60a0 str r0, [r4, #8]
801b120: f105 0268 add.w r2, r5, #104 ; 0x68
801b124: f7ff ff6e bl 801b004 <memset>
801b128: 4620 mov r0, r4
801b12a: bd70 pop {r4, r5, r6, pc}
0801b12c <__sinit>:
801b12c: 6983 ldr r3, [r0, #24]
801b12e: b510 push {r4, lr}
801b130: 4604 mov r4, r0
801b132: bb33 cbnz r3, 801b182 <__sinit+0x56>
801b134: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48
801b138: 6503 str r3, [r0, #80] ; 0x50
801b13a: 4b12 ldr r3, [pc, #72] ; (801b184 <__sinit+0x58>)
801b13c: 4a12 ldr r2, [pc, #72] ; (801b188 <__sinit+0x5c>)
801b13e: 681b ldr r3, [r3, #0]
801b140: 6282 str r2, [r0, #40] ; 0x28
801b142: 4298 cmp r0, r3
801b144: bf04 itt eq
801b146: 2301 moveq r3, #1
801b148: 6183 streq r3, [r0, #24]
801b14a: f000 f81f bl 801b18c <__sfp>
801b14e: 6060 str r0, [r4, #4]
801b150: 4620 mov r0, r4
801b152: f000 f81b bl 801b18c <__sfp>
801b156: 60a0 str r0, [r4, #8]
801b158: 4620 mov r0, r4
801b15a: f000 f817 bl 801b18c <__sfp>
801b15e: 2200 movs r2, #0
801b160: 60e0 str r0, [r4, #12]
801b162: 2104 movs r1, #4
801b164: 6860 ldr r0, [r4, #4]
801b166: f7ff ffa1 bl 801b0ac <std>
801b16a: 2201 movs r2, #1
801b16c: 2109 movs r1, #9
801b16e: 68a0 ldr r0, [r4, #8]
801b170: f7ff ff9c bl 801b0ac <std>
801b174: 2202 movs r2, #2
801b176: 2112 movs r1, #18
801b178: 68e0 ldr r0, [r4, #12]
801b17a: f7ff ff97 bl 801b0ac <std>
801b17e: 2301 movs r3, #1
801b180: 61a3 str r3, [r4, #24]
801b182: bd10 pop {r4, pc}
801b184: 08020e88 .word 0x08020e88
801b188: 0801b0f5 .word 0x0801b0f5
0801b18c <__sfp>:
801b18c: b5f8 push {r3, r4, r5, r6, r7, lr}
801b18e: 4b1b ldr r3, [pc, #108] ; (801b1fc <__sfp+0x70>)
801b190: 681e ldr r6, [r3, #0]
801b192: 69b3 ldr r3, [r6, #24]
801b194: 4607 mov r7, r0
801b196: b913 cbnz r3, 801b19e <__sfp+0x12>
801b198: 4630 mov r0, r6
801b19a: f7ff ffc7 bl 801b12c <__sinit>
801b19e: 3648 adds r6, #72 ; 0x48
801b1a0: e9d6 3401 ldrd r3, r4, [r6, #4]
801b1a4: 3b01 subs r3, #1
801b1a6: d503 bpl.n 801b1b0 <__sfp+0x24>
801b1a8: 6833 ldr r3, [r6, #0]
801b1aa: b133 cbz r3, 801b1ba <__sfp+0x2e>
801b1ac: 6836 ldr r6, [r6, #0]
801b1ae: e7f7 b.n 801b1a0 <__sfp+0x14>
801b1b0: f9b4 500c ldrsh.w r5, [r4, #12]
801b1b4: b16d cbz r5, 801b1d2 <__sfp+0x46>
801b1b6: 3468 adds r4, #104 ; 0x68
801b1b8: e7f4 b.n 801b1a4 <__sfp+0x18>
801b1ba: 2104 movs r1, #4
801b1bc: 4638 mov r0, r7
801b1be: f7ff ff9f bl 801b100 <__sfmoreglue>
801b1c2: 6030 str r0, [r6, #0]
801b1c4: 2800 cmp r0, #0
801b1c6: d1f1 bne.n 801b1ac <__sfp+0x20>
801b1c8: 230c movs r3, #12
801b1ca: 603b str r3, [r7, #0]
801b1cc: 4604 mov r4, r0
801b1ce: 4620 mov r0, r4
801b1d0: bdf8 pop {r3, r4, r5, r6, r7, pc}
801b1d2: 4b0b ldr r3, [pc, #44] ; (801b200 <__sfp+0x74>)
801b1d4: 6665 str r5, [r4, #100] ; 0x64
801b1d6: e9c4 5500 strd r5, r5, [r4]
801b1da: 60a5 str r5, [r4, #8]
801b1dc: e9c4 3503 strd r3, r5, [r4, #12]
801b1e0: e9c4 5505 strd r5, r5, [r4, #20]
801b1e4: 2208 movs r2, #8
801b1e6: 4629 mov r1, r5
801b1e8: f104 005c add.w r0, r4, #92 ; 0x5c
801b1ec: f7ff ff0a bl 801b004 <memset>
801b1f0: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
801b1f4: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
801b1f8: e7e9 b.n 801b1ce <__sfp+0x42>
801b1fa: bf00 nop
801b1fc: 08020e88 .word 0x08020e88
801b200: ffff0001 .word 0xffff0001
0801b204 <_fwalk_reent>:
801b204: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
801b208: 4680 mov r8, r0
801b20a: 4689 mov r9, r1
801b20c: f100 0448 add.w r4, r0, #72 ; 0x48
801b210: 2600 movs r6, #0
801b212: b914 cbnz r4, 801b21a <_fwalk_reent+0x16>
801b214: 4630 mov r0, r6
801b216: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
801b21a: e9d4 7501 ldrd r7, r5, [r4, #4]
801b21e: 3f01 subs r7, #1
801b220: d501 bpl.n 801b226 <_fwalk_reent+0x22>
801b222: 6824 ldr r4, [r4, #0]
801b224: e7f5 b.n 801b212 <_fwalk_reent+0xe>
801b226: 89ab ldrh r3, [r5, #12]
801b228: 2b01 cmp r3, #1
801b22a: d907 bls.n 801b23c <_fwalk_reent+0x38>
801b22c: f9b5 300e ldrsh.w r3, [r5, #14]
801b230: 3301 adds r3, #1
801b232: d003 beq.n 801b23c <_fwalk_reent+0x38>
801b234: 4629 mov r1, r5
801b236: 4640 mov r0, r8
801b238: 47c8 blx r9
801b23a: 4306 orrs r6, r0
801b23c: 3568 adds r5, #104 ; 0x68
801b23e: e7ee b.n 801b21e <_fwalk_reent+0x1a>
0801b240 <malloc>:
801b240: 4b02 ldr r3, [pc, #8] ; (801b24c <malloc+0xc>)
801b242: 4601 mov r1, r0
801b244: 6818 ldr r0, [r3, #0]
801b246: f000 b851 b.w 801b2ec <_malloc_r>
801b24a: bf00 nop
801b24c: 20000084 .word 0x20000084
0801b250 <_free_r>:
801b250: b538 push {r3, r4, r5, lr}
801b252: 4605 mov r5, r0
801b254: 2900 cmp r1, #0
801b256: d045 beq.n 801b2e4 <_free_r+0x94>
801b258: f851 3c04 ldr.w r3, [r1, #-4]
801b25c: 1f0c subs r4, r1, #4
801b25e: 2b00 cmp r3, #0
801b260: bfb8 it lt
801b262: 18e4 addlt r4, r4, r3
801b264: f000 fdc0 bl 801bde8 <__malloc_lock>
801b268: 4a1f ldr r2, [pc, #124] ; (801b2e8 <_free_r+0x98>)
801b26a: 6813 ldr r3, [r2, #0]
801b26c: 4610 mov r0, r2
801b26e: b933 cbnz r3, 801b27e <_free_r+0x2e>
801b270: 6063 str r3, [r4, #4]
801b272: 6014 str r4, [r2, #0]
801b274: 4628 mov r0, r5
801b276: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801b27a: f000 bdb6 b.w 801bdea <__malloc_unlock>
801b27e: 42a3 cmp r3, r4
801b280: d90c bls.n 801b29c <_free_r+0x4c>
801b282: 6821 ldr r1, [r4, #0]
801b284: 1862 adds r2, r4, r1
801b286: 4293 cmp r3, r2
801b288: bf04 itt eq
801b28a: 681a ldreq r2, [r3, #0]
801b28c: 685b ldreq r3, [r3, #4]
801b28e: 6063 str r3, [r4, #4]
801b290: bf04 itt eq
801b292: 1852 addeq r2, r2, r1
801b294: 6022 streq r2, [r4, #0]
801b296: 6004 str r4, [r0, #0]
801b298: e7ec b.n 801b274 <_free_r+0x24>
801b29a: 4613 mov r3, r2
801b29c: 685a ldr r2, [r3, #4]
801b29e: b10a cbz r2, 801b2a4 <_free_r+0x54>
801b2a0: 42a2 cmp r2, r4
801b2a2: d9fa bls.n 801b29a <_free_r+0x4a>
801b2a4: 6819 ldr r1, [r3, #0]
801b2a6: 1858 adds r0, r3, r1
801b2a8: 42a0 cmp r0, r4
801b2aa: d10b bne.n 801b2c4 <_free_r+0x74>
801b2ac: 6820 ldr r0, [r4, #0]
801b2ae: 4401 add r1, r0
801b2b0: 1858 adds r0, r3, r1
801b2b2: 4282 cmp r2, r0
801b2b4: 6019 str r1, [r3, #0]
801b2b6: d1dd bne.n 801b274 <_free_r+0x24>
801b2b8: 6810 ldr r0, [r2, #0]
801b2ba: 6852 ldr r2, [r2, #4]
801b2bc: 605a str r2, [r3, #4]
801b2be: 4401 add r1, r0
801b2c0: 6019 str r1, [r3, #0]
801b2c2: e7d7 b.n 801b274 <_free_r+0x24>
801b2c4: d902 bls.n 801b2cc <_free_r+0x7c>
801b2c6: 230c movs r3, #12
801b2c8: 602b str r3, [r5, #0]
801b2ca: e7d3 b.n 801b274 <_free_r+0x24>
801b2cc: 6820 ldr r0, [r4, #0]
801b2ce: 1821 adds r1, r4, r0
801b2d0: 428a cmp r2, r1
801b2d2: bf04 itt eq
801b2d4: 6811 ldreq r1, [r2, #0]
801b2d6: 6852 ldreq r2, [r2, #4]
801b2d8: 6062 str r2, [r4, #4]
801b2da: bf04 itt eq
801b2dc: 1809 addeq r1, r1, r0
801b2de: 6021 streq r1, [r4, #0]
801b2e0: 605c str r4, [r3, #4]
801b2e2: e7c7 b.n 801b274 <_free_r+0x24>
801b2e4: bd38 pop {r3, r4, r5, pc}
801b2e6: bf00 nop
801b2e8: 20008874 .word 0x20008874
0801b2ec <_malloc_r>:
801b2ec: b570 push {r4, r5, r6, lr}
801b2ee: 1ccd adds r5, r1, #3
801b2f0: f025 0503 bic.w r5, r5, #3
801b2f4: 3508 adds r5, #8
801b2f6: 2d0c cmp r5, #12
801b2f8: bf38 it cc
801b2fa: 250c movcc r5, #12
801b2fc: 2d00 cmp r5, #0
801b2fe: 4606 mov r6, r0
801b300: db01 blt.n 801b306 <_malloc_r+0x1a>
801b302: 42a9 cmp r1, r5
801b304: d903 bls.n 801b30e <_malloc_r+0x22>
801b306: 230c movs r3, #12
801b308: 6033 str r3, [r6, #0]
801b30a: 2000 movs r0, #0
801b30c: bd70 pop {r4, r5, r6, pc}
801b30e: f000 fd6b bl 801bde8 <__malloc_lock>
801b312: 4a21 ldr r2, [pc, #132] ; (801b398 <_malloc_r+0xac>)
801b314: 6814 ldr r4, [r2, #0]
801b316: 4621 mov r1, r4
801b318: b991 cbnz r1, 801b340 <_malloc_r+0x54>
801b31a: 4c20 ldr r4, [pc, #128] ; (801b39c <_malloc_r+0xb0>)
801b31c: 6823 ldr r3, [r4, #0]
801b31e: b91b cbnz r3, 801b328 <_malloc_r+0x3c>
801b320: 4630 mov r0, r6
801b322: f000 fb05 bl 801b930 <_sbrk_r>
801b326: 6020 str r0, [r4, #0]
801b328: 4629 mov r1, r5
801b32a: 4630 mov r0, r6
801b32c: f000 fb00 bl 801b930 <_sbrk_r>
801b330: 1c43 adds r3, r0, #1
801b332: d124 bne.n 801b37e <_malloc_r+0x92>
801b334: 230c movs r3, #12
801b336: 6033 str r3, [r6, #0]
801b338: 4630 mov r0, r6
801b33a: f000 fd56 bl 801bdea <__malloc_unlock>
801b33e: e7e4 b.n 801b30a <_malloc_r+0x1e>
801b340: 680b ldr r3, [r1, #0]
801b342: 1b5b subs r3, r3, r5
801b344: d418 bmi.n 801b378 <_malloc_r+0x8c>
801b346: 2b0b cmp r3, #11
801b348: d90f bls.n 801b36a <_malloc_r+0x7e>
801b34a: 600b str r3, [r1, #0]
801b34c: 50cd str r5, [r1, r3]
801b34e: 18cc adds r4, r1, r3
801b350: 4630 mov r0, r6
801b352: f000 fd4a bl 801bdea <__malloc_unlock>
801b356: f104 000b add.w r0, r4, #11
801b35a: 1d23 adds r3, r4, #4
801b35c: f020 0007 bic.w r0, r0, #7
801b360: 1ac3 subs r3, r0, r3
801b362: d0d3 beq.n 801b30c <_malloc_r+0x20>
801b364: 425a negs r2, r3
801b366: 50e2 str r2, [r4, r3]
801b368: e7d0 b.n 801b30c <_malloc_r+0x20>
801b36a: 428c cmp r4, r1
801b36c: 684b ldr r3, [r1, #4]
801b36e: bf16 itet ne
801b370: 6063 strne r3, [r4, #4]
801b372: 6013 streq r3, [r2, #0]
801b374: 460c movne r4, r1
801b376: e7eb b.n 801b350 <_malloc_r+0x64>
801b378: 460c mov r4, r1
801b37a: 6849 ldr r1, [r1, #4]
801b37c: e7cc b.n 801b318 <_malloc_r+0x2c>
801b37e: 1cc4 adds r4, r0, #3
801b380: f024 0403 bic.w r4, r4, #3
801b384: 42a0 cmp r0, r4
801b386: d005 beq.n 801b394 <_malloc_r+0xa8>
801b388: 1a21 subs r1, r4, r0
801b38a: 4630 mov r0, r6
801b38c: f000 fad0 bl 801b930 <_sbrk_r>
801b390: 3001 adds r0, #1
801b392: d0cf beq.n 801b334 <_malloc_r+0x48>
801b394: 6025 str r5, [r4, #0]
801b396: e7db b.n 801b350 <_malloc_r+0x64>
801b398: 20008874 .word 0x20008874
801b39c: 20008878 .word 0x20008878
0801b3a0 <__sfputc_r>:
801b3a0: 6893 ldr r3, [r2, #8]
801b3a2: 3b01 subs r3, #1
801b3a4: 2b00 cmp r3, #0
801b3a6: b410 push {r4}
801b3a8: 6093 str r3, [r2, #8]
801b3aa: da08 bge.n 801b3be <__sfputc_r+0x1e>
801b3ac: 6994 ldr r4, [r2, #24]
801b3ae: 42a3 cmp r3, r4
801b3b0: db01 blt.n 801b3b6 <__sfputc_r+0x16>
801b3b2: 290a cmp r1, #10
801b3b4: d103 bne.n 801b3be <__sfputc_r+0x1e>
801b3b6: f85d 4b04 ldr.w r4, [sp], #4
801b3ba: f000 bb0d b.w 801b9d8 <__swbuf_r>
801b3be: 6813 ldr r3, [r2, #0]
801b3c0: 1c58 adds r0, r3, #1
801b3c2: 6010 str r0, [r2, #0]
801b3c4: 7019 strb r1, [r3, #0]
801b3c6: 4608 mov r0, r1
801b3c8: f85d 4b04 ldr.w r4, [sp], #4
801b3cc: 4770 bx lr
0801b3ce <__sfputs_r>:
801b3ce: b5f8 push {r3, r4, r5, r6, r7, lr}
801b3d0: 4606 mov r6, r0
801b3d2: 460f mov r7, r1
801b3d4: 4614 mov r4, r2
801b3d6: 18d5 adds r5, r2, r3
801b3d8: 42ac cmp r4, r5
801b3da: d101 bne.n 801b3e0 <__sfputs_r+0x12>
801b3dc: 2000 movs r0, #0
801b3de: e007 b.n 801b3f0 <__sfputs_r+0x22>
801b3e0: 463a mov r2, r7
801b3e2: f814 1b01 ldrb.w r1, [r4], #1
801b3e6: 4630 mov r0, r6
801b3e8: f7ff ffda bl 801b3a0 <__sfputc_r>
801b3ec: 1c43 adds r3, r0, #1
801b3ee: d1f3 bne.n 801b3d8 <__sfputs_r+0xa>
801b3f0: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
0801b3f4 <_vfiprintf_r>:
801b3f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801b3f8: 460c mov r4, r1
801b3fa: b09d sub sp, #116 ; 0x74
801b3fc: 4617 mov r7, r2
801b3fe: 461d mov r5, r3
801b400: 4606 mov r6, r0
801b402: b118 cbz r0, 801b40c <_vfiprintf_r+0x18>
801b404: 6983 ldr r3, [r0, #24]
801b406: b90b cbnz r3, 801b40c <_vfiprintf_r+0x18>
801b408: f7ff fe90 bl 801b12c <__sinit>
801b40c: 4b7c ldr r3, [pc, #496] ; (801b600 <_vfiprintf_r+0x20c>)
801b40e: 429c cmp r4, r3
801b410: d158 bne.n 801b4c4 <_vfiprintf_r+0xd0>
801b412: 6874 ldr r4, [r6, #4]
801b414: 89a3 ldrh r3, [r4, #12]
801b416: 0718 lsls r0, r3, #28
801b418: d55e bpl.n 801b4d8 <_vfiprintf_r+0xe4>
801b41a: 6923 ldr r3, [r4, #16]
801b41c: 2b00 cmp r3, #0
801b41e: d05b beq.n 801b4d8 <_vfiprintf_r+0xe4>
801b420: 2300 movs r3, #0
801b422: 9309 str r3, [sp, #36] ; 0x24
801b424: 2320 movs r3, #32
801b426: f88d 3029 strb.w r3, [sp, #41] ; 0x29
801b42a: 2330 movs r3, #48 ; 0x30
801b42c: f88d 302a strb.w r3, [sp, #42] ; 0x2a
801b430: 9503 str r5, [sp, #12]
801b432: f04f 0b01 mov.w fp, #1
801b436: 46b8 mov r8, r7
801b438: 4645 mov r5, r8
801b43a: f815 3b01 ldrb.w r3, [r5], #1
801b43e: b10b cbz r3, 801b444 <_vfiprintf_r+0x50>
801b440: 2b25 cmp r3, #37 ; 0x25
801b442: d154 bne.n 801b4ee <_vfiprintf_r+0xfa>
801b444: ebb8 0a07 subs.w sl, r8, r7
801b448: d00b beq.n 801b462 <_vfiprintf_r+0x6e>
801b44a: 4653 mov r3, sl
801b44c: 463a mov r2, r7
801b44e: 4621 mov r1, r4
801b450: 4630 mov r0, r6
801b452: f7ff ffbc bl 801b3ce <__sfputs_r>
801b456: 3001 adds r0, #1
801b458: f000 80c2 beq.w 801b5e0 <_vfiprintf_r+0x1ec>
801b45c: 9b09 ldr r3, [sp, #36] ; 0x24
801b45e: 4453 add r3, sl
801b460: 9309 str r3, [sp, #36] ; 0x24
801b462: f898 3000 ldrb.w r3, [r8]
801b466: 2b00 cmp r3, #0
801b468: f000 80ba beq.w 801b5e0 <_vfiprintf_r+0x1ec>
801b46c: 2300 movs r3, #0
801b46e: f04f 32ff mov.w r2, #4294967295
801b472: e9cd 2305 strd r2, r3, [sp, #20]
801b476: 9304 str r3, [sp, #16]
801b478: 9307 str r3, [sp, #28]
801b47a: f88d 3053 strb.w r3, [sp, #83] ; 0x53
801b47e: 931a str r3, [sp, #104] ; 0x68
801b480: 46a8 mov r8, r5
801b482: 2205 movs r2, #5
801b484: f818 1b01 ldrb.w r1, [r8], #1
801b488: 485e ldr r0, [pc, #376] ; (801b604 <_vfiprintf_r+0x210>)
801b48a: f7e4 fec1 bl 8000210 <memchr>
801b48e: 9b04 ldr r3, [sp, #16]
801b490: bb78 cbnz r0, 801b4f2 <_vfiprintf_r+0xfe>
801b492: 06d9 lsls r1, r3, #27
801b494: bf44 itt mi
801b496: 2220 movmi r2, #32
801b498: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
801b49c: 071a lsls r2, r3, #28
801b49e: bf44 itt mi
801b4a0: 222b movmi r2, #43 ; 0x2b
801b4a2: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
801b4a6: 782a ldrb r2, [r5, #0]
801b4a8: 2a2a cmp r2, #42 ; 0x2a
801b4aa: d02a beq.n 801b502 <_vfiprintf_r+0x10e>
801b4ac: 9a07 ldr r2, [sp, #28]
801b4ae: 46a8 mov r8, r5
801b4b0: 2000 movs r0, #0
801b4b2: 250a movs r5, #10
801b4b4: 4641 mov r1, r8
801b4b6: f811 3b01 ldrb.w r3, [r1], #1
801b4ba: 3b30 subs r3, #48 ; 0x30
801b4bc: 2b09 cmp r3, #9
801b4be: d969 bls.n 801b594 <_vfiprintf_r+0x1a0>
801b4c0: b360 cbz r0, 801b51c <_vfiprintf_r+0x128>
801b4c2: e024 b.n 801b50e <_vfiprintf_r+0x11a>
801b4c4: 4b50 ldr r3, [pc, #320] ; (801b608 <_vfiprintf_r+0x214>)
801b4c6: 429c cmp r4, r3
801b4c8: d101 bne.n 801b4ce <_vfiprintf_r+0xda>
801b4ca: 68b4 ldr r4, [r6, #8]
801b4cc: e7a2 b.n 801b414 <_vfiprintf_r+0x20>
801b4ce: 4b4f ldr r3, [pc, #316] ; (801b60c <_vfiprintf_r+0x218>)
801b4d0: 429c cmp r4, r3
801b4d2: bf08 it eq
801b4d4: 68f4 ldreq r4, [r6, #12]
801b4d6: e79d b.n 801b414 <_vfiprintf_r+0x20>
801b4d8: 4621 mov r1, r4
801b4da: 4630 mov r0, r6
801b4dc: f000 fae0 bl 801baa0 <__swsetup_r>
801b4e0: 2800 cmp r0, #0
801b4e2: d09d beq.n 801b420 <_vfiprintf_r+0x2c>
801b4e4: f04f 30ff mov.w r0, #4294967295
801b4e8: b01d add sp, #116 ; 0x74
801b4ea: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801b4ee: 46a8 mov r8, r5
801b4f0: e7a2 b.n 801b438 <_vfiprintf_r+0x44>
801b4f2: 4a44 ldr r2, [pc, #272] ; (801b604 <_vfiprintf_r+0x210>)
801b4f4: 1a80 subs r0, r0, r2
801b4f6: fa0b f000 lsl.w r0, fp, r0
801b4fa: 4318 orrs r0, r3
801b4fc: 9004 str r0, [sp, #16]
801b4fe: 4645 mov r5, r8
801b500: e7be b.n 801b480 <_vfiprintf_r+0x8c>
801b502: 9a03 ldr r2, [sp, #12]
801b504: 1d11 adds r1, r2, #4
801b506: 6812 ldr r2, [r2, #0]
801b508: 9103 str r1, [sp, #12]
801b50a: 2a00 cmp r2, #0
801b50c: db01 blt.n 801b512 <_vfiprintf_r+0x11e>
801b50e: 9207 str r2, [sp, #28]
801b510: e004 b.n 801b51c <_vfiprintf_r+0x128>
801b512: 4252 negs r2, r2
801b514: f043 0302 orr.w r3, r3, #2
801b518: 9207 str r2, [sp, #28]
801b51a: 9304 str r3, [sp, #16]
801b51c: f898 3000 ldrb.w r3, [r8]
801b520: 2b2e cmp r3, #46 ; 0x2e
801b522: d10e bne.n 801b542 <_vfiprintf_r+0x14e>
801b524: f898 3001 ldrb.w r3, [r8, #1]
801b528: 2b2a cmp r3, #42 ; 0x2a
801b52a: d138 bne.n 801b59e <_vfiprintf_r+0x1aa>
801b52c: 9b03 ldr r3, [sp, #12]
801b52e: 1d1a adds r2, r3, #4
801b530: 681b ldr r3, [r3, #0]
801b532: 9203 str r2, [sp, #12]
801b534: 2b00 cmp r3, #0
801b536: bfb8 it lt
801b538: f04f 33ff movlt.w r3, #4294967295
801b53c: f108 0802 add.w r8, r8, #2
801b540: 9305 str r3, [sp, #20]
801b542: 4d33 ldr r5, [pc, #204] ; (801b610 <_vfiprintf_r+0x21c>)
801b544: f898 1000 ldrb.w r1, [r8]
801b548: 2203 movs r2, #3
801b54a: 4628 mov r0, r5
801b54c: f7e4 fe60 bl 8000210 <memchr>
801b550: b140 cbz r0, 801b564 <_vfiprintf_r+0x170>
801b552: 2340 movs r3, #64 ; 0x40
801b554: 1b40 subs r0, r0, r5
801b556: fa03 f000 lsl.w r0, r3, r0
801b55a: 9b04 ldr r3, [sp, #16]
801b55c: 4303 orrs r3, r0
801b55e: f108 0801 add.w r8, r8, #1
801b562: 9304 str r3, [sp, #16]
801b564: f898 1000 ldrb.w r1, [r8]
801b568: 482a ldr r0, [pc, #168] ; (801b614 <_vfiprintf_r+0x220>)
801b56a: f88d 1028 strb.w r1, [sp, #40] ; 0x28
801b56e: 2206 movs r2, #6
801b570: f108 0701 add.w r7, r8, #1
801b574: f7e4 fe4c bl 8000210 <memchr>
801b578: 2800 cmp r0, #0
801b57a: d037 beq.n 801b5ec <_vfiprintf_r+0x1f8>
801b57c: 4b26 ldr r3, [pc, #152] ; (801b618 <_vfiprintf_r+0x224>)
801b57e: bb1b cbnz r3, 801b5c8 <_vfiprintf_r+0x1d4>
801b580: 9b03 ldr r3, [sp, #12]
801b582: 3307 adds r3, #7
801b584: f023 0307 bic.w r3, r3, #7
801b588: 3308 adds r3, #8
801b58a: 9303 str r3, [sp, #12]
801b58c: 9b09 ldr r3, [sp, #36] ; 0x24
801b58e: 444b add r3, r9
801b590: 9309 str r3, [sp, #36] ; 0x24
801b592: e750 b.n 801b436 <_vfiprintf_r+0x42>
801b594: fb05 3202 mla r2, r5, r2, r3
801b598: 2001 movs r0, #1
801b59a: 4688 mov r8, r1
801b59c: e78a b.n 801b4b4 <_vfiprintf_r+0xc0>
801b59e: 2300 movs r3, #0
801b5a0: f108 0801 add.w r8, r8, #1
801b5a4: 9305 str r3, [sp, #20]
801b5a6: 4619 mov r1, r3
801b5a8: 250a movs r5, #10
801b5aa: 4640 mov r0, r8
801b5ac: f810 2b01 ldrb.w r2, [r0], #1
801b5b0: 3a30 subs r2, #48 ; 0x30
801b5b2: 2a09 cmp r2, #9
801b5b4: d903 bls.n 801b5be <_vfiprintf_r+0x1ca>
801b5b6: 2b00 cmp r3, #0
801b5b8: d0c3 beq.n 801b542 <_vfiprintf_r+0x14e>
801b5ba: 9105 str r1, [sp, #20]
801b5bc: e7c1 b.n 801b542 <_vfiprintf_r+0x14e>
801b5be: fb05 2101 mla r1, r5, r1, r2
801b5c2: 2301 movs r3, #1
801b5c4: 4680 mov r8, r0
801b5c6: e7f0 b.n 801b5aa <_vfiprintf_r+0x1b6>
801b5c8: ab03 add r3, sp, #12
801b5ca: 9300 str r3, [sp, #0]
801b5cc: 4622 mov r2, r4
801b5ce: 4b13 ldr r3, [pc, #76] ; (801b61c <_vfiprintf_r+0x228>)
801b5d0: a904 add r1, sp, #16
801b5d2: 4630 mov r0, r6
801b5d4: f3af 8000 nop.w
801b5d8: f1b0 3fff cmp.w r0, #4294967295
801b5dc: 4681 mov r9, r0
801b5de: d1d5 bne.n 801b58c <_vfiprintf_r+0x198>
801b5e0: 89a3 ldrh r3, [r4, #12]
801b5e2: 065b lsls r3, r3, #25
801b5e4: f53f af7e bmi.w 801b4e4 <_vfiprintf_r+0xf0>
801b5e8: 9809 ldr r0, [sp, #36] ; 0x24
801b5ea: e77d b.n 801b4e8 <_vfiprintf_r+0xf4>
801b5ec: ab03 add r3, sp, #12
801b5ee: 9300 str r3, [sp, #0]
801b5f0: 4622 mov r2, r4
801b5f2: 4b0a ldr r3, [pc, #40] ; (801b61c <_vfiprintf_r+0x228>)
801b5f4: a904 add r1, sp, #16
801b5f6: 4630 mov r0, r6
801b5f8: f000 f888 bl 801b70c <_printf_i>
801b5fc: e7ec b.n 801b5d8 <_vfiprintf_r+0x1e4>
801b5fe: bf00 nop
801b600: 08020eac .word 0x08020eac
801b604: 08020eec .word 0x08020eec
801b608: 08020ecc .word 0x08020ecc
801b60c: 08020e8c .word 0x08020e8c
801b610: 08020ef2 .word 0x08020ef2
801b614: 08020ef6 .word 0x08020ef6
801b618: 00000000 .word 0x00000000
801b61c: 0801b3cf .word 0x0801b3cf
0801b620 <_printf_common>:
801b620: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b624: 4691 mov r9, r2
801b626: 461f mov r7, r3
801b628: 688a ldr r2, [r1, #8]
801b62a: 690b ldr r3, [r1, #16]
801b62c: f8dd 8020 ldr.w r8, [sp, #32]
801b630: 4293 cmp r3, r2
801b632: bfb8 it lt
801b634: 4613 movlt r3, r2
801b636: f8c9 3000 str.w r3, [r9]
801b63a: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
801b63e: 4606 mov r6, r0
801b640: 460c mov r4, r1
801b642: b112 cbz r2, 801b64a <_printf_common+0x2a>
801b644: 3301 adds r3, #1
801b646: f8c9 3000 str.w r3, [r9]
801b64a: 6823 ldr r3, [r4, #0]
801b64c: 0699 lsls r1, r3, #26
801b64e: bf42 ittt mi
801b650: f8d9 3000 ldrmi.w r3, [r9]
801b654: 3302 addmi r3, #2
801b656: f8c9 3000 strmi.w r3, [r9]
801b65a: 6825 ldr r5, [r4, #0]
801b65c: f015 0506 ands.w r5, r5, #6
801b660: d107 bne.n 801b672 <_printf_common+0x52>
801b662: f104 0a19 add.w sl, r4, #25
801b666: 68e3 ldr r3, [r4, #12]
801b668: f8d9 2000 ldr.w r2, [r9]
801b66c: 1a9b subs r3, r3, r2
801b66e: 42ab cmp r3, r5
801b670: dc28 bgt.n 801b6c4 <_printf_common+0xa4>
801b672: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
801b676: 6822 ldr r2, [r4, #0]
801b678: 3300 adds r3, #0
801b67a: bf18 it ne
801b67c: 2301 movne r3, #1
801b67e: 0692 lsls r2, r2, #26
801b680: d42d bmi.n 801b6de <_printf_common+0xbe>
801b682: f104 0243 add.w r2, r4, #67 ; 0x43
801b686: 4639 mov r1, r7
801b688: 4630 mov r0, r6
801b68a: 47c0 blx r8
801b68c: 3001 adds r0, #1
801b68e: d020 beq.n 801b6d2 <_printf_common+0xb2>
801b690: 6823 ldr r3, [r4, #0]
801b692: 68e5 ldr r5, [r4, #12]
801b694: f8d9 2000 ldr.w r2, [r9]
801b698: f003 0306 and.w r3, r3, #6
801b69c: 2b04 cmp r3, #4
801b69e: bf08 it eq
801b6a0: 1aad subeq r5, r5, r2
801b6a2: 68a3 ldr r3, [r4, #8]
801b6a4: 6922 ldr r2, [r4, #16]
801b6a6: bf0c ite eq
801b6a8: ea25 75e5 biceq.w r5, r5, r5, asr #31
801b6ac: 2500 movne r5, #0
801b6ae: 4293 cmp r3, r2
801b6b0: bfc4 itt gt
801b6b2: 1a9b subgt r3, r3, r2
801b6b4: 18ed addgt r5, r5, r3
801b6b6: f04f 0900 mov.w r9, #0
801b6ba: 341a adds r4, #26
801b6bc: 454d cmp r5, r9
801b6be: d11a bne.n 801b6f6 <_printf_common+0xd6>
801b6c0: 2000 movs r0, #0
801b6c2: e008 b.n 801b6d6 <_printf_common+0xb6>
801b6c4: 2301 movs r3, #1
801b6c6: 4652 mov r2, sl
801b6c8: 4639 mov r1, r7
801b6ca: 4630 mov r0, r6
801b6cc: 47c0 blx r8
801b6ce: 3001 adds r0, #1
801b6d0: d103 bne.n 801b6da <_printf_common+0xba>
801b6d2: f04f 30ff mov.w r0, #4294967295
801b6d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b6da: 3501 adds r5, #1
801b6dc: e7c3 b.n 801b666 <_printf_common+0x46>
801b6de: 18e1 adds r1, r4, r3
801b6e0: 1c5a adds r2, r3, #1
801b6e2: 2030 movs r0, #48 ; 0x30
801b6e4: f881 0043 strb.w r0, [r1, #67] ; 0x43
801b6e8: 4422 add r2, r4
801b6ea: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
801b6ee: f882 1043 strb.w r1, [r2, #67] ; 0x43
801b6f2: 3302 adds r3, #2
801b6f4: e7c5 b.n 801b682 <_printf_common+0x62>
801b6f6: 2301 movs r3, #1
801b6f8: 4622 mov r2, r4
801b6fa: 4639 mov r1, r7
801b6fc: 4630 mov r0, r6
801b6fe: 47c0 blx r8
801b700: 3001 adds r0, #1
801b702: d0e6 beq.n 801b6d2 <_printf_common+0xb2>
801b704: f109 0901 add.w r9, r9, #1
801b708: e7d8 b.n 801b6bc <_printf_common+0x9c>
...
0801b70c <_printf_i>:
801b70c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
801b710: f101 0c43 add.w ip, r1, #67 ; 0x43
801b714: 460c mov r4, r1
801b716: 7e09 ldrb r1, [r1, #24]
801b718: b085 sub sp, #20
801b71a: 296e cmp r1, #110 ; 0x6e
801b71c: 4617 mov r7, r2
801b71e: 4606 mov r6, r0
801b720: 4698 mov r8, r3
801b722: 9a0c ldr r2, [sp, #48] ; 0x30
801b724: f000 80b3 beq.w 801b88e <_printf_i+0x182>
801b728: d822 bhi.n 801b770 <_printf_i+0x64>
801b72a: 2963 cmp r1, #99 ; 0x63
801b72c: d036 beq.n 801b79c <_printf_i+0x90>
801b72e: d80a bhi.n 801b746 <_printf_i+0x3a>
801b730: 2900 cmp r1, #0
801b732: f000 80b9 beq.w 801b8a8 <_printf_i+0x19c>
801b736: 2958 cmp r1, #88 ; 0x58
801b738: f000 8083 beq.w 801b842 <_printf_i+0x136>
801b73c: f104 0542 add.w r5, r4, #66 ; 0x42
801b740: f884 1042 strb.w r1, [r4, #66] ; 0x42
801b744: e032 b.n 801b7ac <_printf_i+0xa0>
801b746: 2964 cmp r1, #100 ; 0x64
801b748: d001 beq.n 801b74e <_printf_i+0x42>
801b74a: 2969 cmp r1, #105 ; 0x69
801b74c: d1f6 bne.n 801b73c <_printf_i+0x30>
801b74e: 6820 ldr r0, [r4, #0]
801b750: 6813 ldr r3, [r2, #0]
801b752: 0605 lsls r5, r0, #24
801b754: f103 0104 add.w r1, r3, #4
801b758: d52a bpl.n 801b7b0 <_printf_i+0xa4>
801b75a: 681b ldr r3, [r3, #0]
801b75c: 6011 str r1, [r2, #0]
801b75e: 2b00 cmp r3, #0
801b760: da03 bge.n 801b76a <_printf_i+0x5e>
801b762: 222d movs r2, #45 ; 0x2d
801b764: 425b negs r3, r3
801b766: f884 2043 strb.w r2, [r4, #67] ; 0x43
801b76a: 486f ldr r0, [pc, #444] ; (801b928 <_printf_i+0x21c>)
801b76c: 220a movs r2, #10
801b76e: e039 b.n 801b7e4 <_printf_i+0xd8>
801b770: 2973 cmp r1, #115 ; 0x73
801b772: f000 809d beq.w 801b8b0 <_printf_i+0x1a4>
801b776: d808 bhi.n 801b78a <_printf_i+0x7e>
801b778: 296f cmp r1, #111 ; 0x6f
801b77a: d020 beq.n 801b7be <_printf_i+0xb2>
801b77c: 2970 cmp r1, #112 ; 0x70
801b77e: d1dd bne.n 801b73c <_printf_i+0x30>
801b780: 6823 ldr r3, [r4, #0]
801b782: f043 0320 orr.w r3, r3, #32
801b786: 6023 str r3, [r4, #0]
801b788: e003 b.n 801b792 <_printf_i+0x86>
801b78a: 2975 cmp r1, #117 ; 0x75
801b78c: d017 beq.n 801b7be <_printf_i+0xb2>
801b78e: 2978 cmp r1, #120 ; 0x78
801b790: d1d4 bne.n 801b73c <_printf_i+0x30>
801b792: 2378 movs r3, #120 ; 0x78
801b794: f884 3045 strb.w r3, [r4, #69] ; 0x45
801b798: 4864 ldr r0, [pc, #400] ; (801b92c <_printf_i+0x220>)
801b79a: e055 b.n 801b848 <_printf_i+0x13c>
801b79c: 6813 ldr r3, [r2, #0]
801b79e: 1d19 adds r1, r3, #4
801b7a0: 681b ldr r3, [r3, #0]
801b7a2: 6011 str r1, [r2, #0]
801b7a4: f104 0542 add.w r5, r4, #66 ; 0x42
801b7a8: f884 3042 strb.w r3, [r4, #66] ; 0x42
801b7ac: 2301 movs r3, #1
801b7ae: e08c b.n 801b8ca <_printf_i+0x1be>
801b7b0: 681b ldr r3, [r3, #0]
801b7b2: 6011 str r1, [r2, #0]
801b7b4: f010 0f40 tst.w r0, #64 ; 0x40
801b7b8: bf18 it ne
801b7ba: b21b sxthne r3, r3
801b7bc: e7cf b.n 801b75e <_printf_i+0x52>
801b7be: 6813 ldr r3, [r2, #0]
801b7c0: 6825 ldr r5, [r4, #0]
801b7c2: 1d18 adds r0, r3, #4
801b7c4: 6010 str r0, [r2, #0]
801b7c6: 0628 lsls r0, r5, #24
801b7c8: d501 bpl.n 801b7ce <_printf_i+0xc2>
801b7ca: 681b ldr r3, [r3, #0]
801b7cc: e002 b.n 801b7d4 <_printf_i+0xc8>
801b7ce: 0668 lsls r0, r5, #25
801b7d0: d5fb bpl.n 801b7ca <_printf_i+0xbe>
801b7d2: 881b ldrh r3, [r3, #0]
801b7d4: 4854 ldr r0, [pc, #336] ; (801b928 <_printf_i+0x21c>)
801b7d6: 296f cmp r1, #111 ; 0x6f
801b7d8: bf14 ite ne
801b7da: 220a movne r2, #10
801b7dc: 2208 moveq r2, #8
801b7de: 2100 movs r1, #0
801b7e0: f884 1043 strb.w r1, [r4, #67] ; 0x43
801b7e4: 6865 ldr r5, [r4, #4]
801b7e6: 60a5 str r5, [r4, #8]
801b7e8: 2d00 cmp r5, #0
801b7ea: f2c0 8095 blt.w 801b918 <_printf_i+0x20c>
801b7ee: 6821 ldr r1, [r4, #0]
801b7f0: f021 0104 bic.w r1, r1, #4
801b7f4: 6021 str r1, [r4, #0]
801b7f6: 2b00 cmp r3, #0
801b7f8: d13d bne.n 801b876 <_printf_i+0x16a>
801b7fa: 2d00 cmp r5, #0
801b7fc: f040 808e bne.w 801b91c <_printf_i+0x210>
801b800: 4665 mov r5, ip
801b802: 2a08 cmp r2, #8
801b804: d10b bne.n 801b81e <_printf_i+0x112>
801b806: 6823 ldr r3, [r4, #0]
801b808: 07db lsls r3, r3, #31
801b80a: d508 bpl.n 801b81e <_printf_i+0x112>
801b80c: 6923 ldr r3, [r4, #16]
801b80e: 6862 ldr r2, [r4, #4]
801b810: 429a cmp r2, r3
801b812: bfde ittt le
801b814: 2330 movle r3, #48 ; 0x30
801b816: f805 3c01 strble.w r3, [r5, #-1]
801b81a: f105 35ff addle.w r5, r5, #4294967295
801b81e: ebac 0305 sub.w r3, ip, r5
801b822: 6123 str r3, [r4, #16]
801b824: f8cd 8000 str.w r8, [sp]
801b828: 463b mov r3, r7
801b82a: aa03 add r2, sp, #12
801b82c: 4621 mov r1, r4
801b82e: 4630 mov r0, r6
801b830: f7ff fef6 bl 801b620 <_printf_common>
801b834: 3001 adds r0, #1
801b836: d14d bne.n 801b8d4 <_printf_i+0x1c8>
801b838: f04f 30ff mov.w r0, #4294967295
801b83c: b005 add sp, #20
801b83e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
801b842: 4839 ldr r0, [pc, #228] ; (801b928 <_printf_i+0x21c>)
801b844: f884 1045 strb.w r1, [r4, #69] ; 0x45
801b848: 6813 ldr r3, [r2, #0]
801b84a: 6821 ldr r1, [r4, #0]
801b84c: 1d1d adds r5, r3, #4
801b84e: 681b ldr r3, [r3, #0]
801b850: 6015 str r5, [r2, #0]
801b852: 060a lsls r2, r1, #24
801b854: d50b bpl.n 801b86e <_printf_i+0x162>
801b856: 07ca lsls r2, r1, #31
801b858: bf44 itt mi
801b85a: f041 0120 orrmi.w r1, r1, #32
801b85e: 6021 strmi r1, [r4, #0]
801b860: b91b cbnz r3, 801b86a <_printf_i+0x15e>
801b862: 6822 ldr r2, [r4, #0]
801b864: f022 0220 bic.w r2, r2, #32
801b868: 6022 str r2, [r4, #0]
801b86a: 2210 movs r2, #16
801b86c: e7b7 b.n 801b7de <_printf_i+0xd2>
801b86e: 064d lsls r5, r1, #25
801b870: bf48 it mi
801b872: b29b uxthmi r3, r3
801b874: e7ef b.n 801b856 <_printf_i+0x14a>
801b876: 4665 mov r5, ip
801b878: fbb3 f1f2 udiv r1, r3, r2
801b87c: fb02 3311 mls r3, r2, r1, r3
801b880: 5cc3 ldrb r3, [r0, r3]
801b882: f805 3d01 strb.w r3, [r5, #-1]!
801b886: 460b mov r3, r1
801b888: 2900 cmp r1, #0
801b88a: d1f5 bne.n 801b878 <_printf_i+0x16c>
801b88c: e7b9 b.n 801b802 <_printf_i+0xf6>
801b88e: 6813 ldr r3, [r2, #0]
801b890: 6825 ldr r5, [r4, #0]
801b892: 6961 ldr r1, [r4, #20]
801b894: 1d18 adds r0, r3, #4
801b896: 6010 str r0, [r2, #0]
801b898: 0628 lsls r0, r5, #24
801b89a: 681b ldr r3, [r3, #0]
801b89c: d501 bpl.n 801b8a2 <_printf_i+0x196>
801b89e: 6019 str r1, [r3, #0]
801b8a0: e002 b.n 801b8a8 <_printf_i+0x19c>
801b8a2: 066a lsls r2, r5, #25
801b8a4: d5fb bpl.n 801b89e <_printf_i+0x192>
801b8a6: 8019 strh r1, [r3, #0]
801b8a8: 2300 movs r3, #0
801b8aa: 6123 str r3, [r4, #16]
801b8ac: 4665 mov r5, ip
801b8ae: e7b9 b.n 801b824 <_printf_i+0x118>
801b8b0: 6813 ldr r3, [r2, #0]
801b8b2: 1d19 adds r1, r3, #4
801b8b4: 6011 str r1, [r2, #0]
801b8b6: 681d ldr r5, [r3, #0]
801b8b8: 6862 ldr r2, [r4, #4]
801b8ba: 2100 movs r1, #0
801b8bc: 4628 mov r0, r5
801b8be: f7e4 fca7 bl 8000210 <memchr>
801b8c2: b108 cbz r0, 801b8c8 <_printf_i+0x1bc>
801b8c4: 1b40 subs r0, r0, r5
801b8c6: 6060 str r0, [r4, #4]
801b8c8: 6863 ldr r3, [r4, #4]
801b8ca: 6123 str r3, [r4, #16]
801b8cc: 2300 movs r3, #0
801b8ce: f884 3043 strb.w r3, [r4, #67] ; 0x43
801b8d2: e7a7 b.n 801b824 <_printf_i+0x118>
801b8d4: 6923 ldr r3, [r4, #16]
801b8d6: 462a mov r2, r5
801b8d8: 4639 mov r1, r7
801b8da: 4630 mov r0, r6
801b8dc: 47c0 blx r8
801b8de: 3001 adds r0, #1
801b8e0: d0aa beq.n 801b838 <_printf_i+0x12c>
801b8e2: 6823 ldr r3, [r4, #0]
801b8e4: 079b lsls r3, r3, #30
801b8e6: d413 bmi.n 801b910 <_printf_i+0x204>
801b8e8: 68e0 ldr r0, [r4, #12]
801b8ea: 9b03 ldr r3, [sp, #12]
801b8ec: 4298 cmp r0, r3
801b8ee: bfb8 it lt
801b8f0: 4618 movlt r0, r3
801b8f2: e7a3 b.n 801b83c <_printf_i+0x130>
801b8f4: 2301 movs r3, #1
801b8f6: 464a mov r2, r9
801b8f8: 4639 mov r1, r7
801b8fa: 4630 mov r0, r6
801b8fc: 47c0 blx r8
801b8fe: 3001 adds r0, #1
801b900: d09a beq.n 801b838 <_printf_i+0x12c>
801b902: 3501 adds r5, #1
801b904: 68e3 ldr r3, [r4, #12]
801b906: 9a03 ldr r2, [sp, #12]
801b908: 1a9b subs r3, r3, r2
801b90a: 42ab cmp r3, r5
801b90c: dcf2 bgt.n 801b8f4 <_printf_i+0x1e8>
801b90e: e7eb b.n 801b8e8 <_printf_i+0x1dc>
801b910: 2500 movs r5, #0
801b912: f104 0919 add.w r9, r4, #25
801b916: e7f5 b.n 801b904 <_printf_i+0x1f8>
801b918: 2b00 cmp r3, #0
801b91a: d1ac bne.n 801b876 <_printf_i+0x16a>
801b91c: 7803 ldrb r3, [r0, #0]
801b91e: f884 3042 strb.w r3, [r4, #66] ; 0x42
801b922: f104 0542 add.w r5, r4, #66 ; 0x42
801b926: e76c b.n 801b802 <_printf_i+0xf6>
801b928: 08020efd .word 0x08020efd
801b92c: 08020f0e .word 0x08020f0e
0801b930 <_sbrk_r>:
801b930: b538 push {r3, r4, r5, lr}
801b932: 4c06 ldr r4, [pc, #24] ; (801b94c <_sbrk_r+0x1c>)
801b934: 2300 movs r3, #0
801b936: 4605 mov r5, r0
801b938: 4608 mov r0, r1
801b93a: 6023 str r3, [r4, #0]
801b93c: f7e8 ff94 bl 8004868 <_sbrk>
801b940: 1c43 adds r3, r0, #1
801b942: d102 bne.n 801b94a <_sbrk_r+0x1a>
801b944: 6823 ldr r3, [r4, #0]
801b946: b103 cbz r3, 801b94a <_sbrk_r+0x1a>
801b948: 602b str r3, [r5, #0]
801b94a: bd38 pop {r3, r4, r5, pc}
801b94c: 2000f604 .word 0x2000f604
0801b950 <__sread>:
801b950: b510 push {r4, lr}
801b952: 460c mov r4, r1
801b954: f9b1 100e ldrsh.w r1, [r1, #14]
801b958: f000 fa48 bl 801bdec <_read_r>
801b95c: 2800 cmp r0, #0
801b95e: bfab itete ge
801b960: 6d63 ldrge r3, [r4, #84] ; 0x54
801b962: 89a3 ldrhlt r3, [r4, #12]
801b964: 181b addge r3, r3, r0
801b966: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
801b96a: bfac ite ge
801b96c: 6563 strge r3, [r4, #84] ; 0x54
801b96e: 81a3 strhlt r3, [r4, #12]
801b970: bd10 pop {r4, pc}
0801b972 <__swrite>:
801b972: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801b976: 461f mov r7, r3
801b978: 898b ldrh r3, [r1, #12]
801b97a: 05db lsls r3, r3, #23
801b97c: 4605 mov r5, r0
801b97e: 460c mov r4, r1
801b980: 4616 mov r6, r2
801b982: d505 bpl.n 801b990 <__swrite+0x1e>
801b984: 2302 movs r3, #2
801b986: 2200 movs r2, #0
801b988: f9b1 100e ldrsh.w r1, [r1, #14]
801b98c: f000 f9b6 bl 801bcfc <_lseek_r>
801b990: 89a3 ldrh r3, [r4, #12]
801b992: f9b4 100e ldrsh.w r1, [r4, #14]
801b996: f423 5380 bic.w r3, r3, #4096 ; 0x1000
801b99a: 81a3 strh r3, [r4, #12]
801b99c: 4632 mov r2, r6
801b99e: 463b mov r3, r7
801b9a0: 4628 mov r0, r5
801b9a2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
801b9a6: f000 b869 b.w 801ba7c <_write_r>
0801b9aa <__sseek>:
801b9aa: b510 push {r4, lr}
801b9ac: 460c mov r4, r1
801b9ae: f9b1 100e ldrsh.w r1, [r1, #14]
801b9b2: f000 f9a3 bl 801bcfc <_lseek_r>
801b9b6: 1c43 adds r3, r0, #1
801b9b8: 89a3 ldrh r3, [r4, #12]
801b9ba: bf15 itete ne
801b9bc: 6560 strne r0, [r4, #84] ; 0x54
801b9be: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
801b9c2: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
801b9c6: 81a3 strheq r3, [r4, #12]
801b9c8: bf18 it ne
801b9ca: 81a3 strhne r3, [r4, #12]
801b9cc: bd10 pop {r4, pc}
0801b9ce <__sclose>:
801b9ce: f9b1 100e ldrsh.w r1, [r1, #14]
801b9d2: f000 b8d3 b.w 801bb7c <_close_r>
...
0801b9d8 <__swbuf_r>:
801b9d8: b5f8 push {r3, r4, r5, r6, r7, lr}
801b9da: 460e mov r6, r1
801b9dc: 4614 mov r4, r2
801b9de: 4605 mov r5, r0
801b9e0: b118 cbz r0, 801b9ea <__swbuf_r+0x12>
801b9e2: 6983 ldr r3, [r0, #24]
801b9e4: b90b cbnz r3, 801b9ea <__swbuf_r+0x12>
801b9e6: f7ff fba1 bl 801b12c <__sinit>
801b9ea: 4b21 ldr r3, [pc, #132] ; (801ba70 <__swbuf_r+0x98>)
801b9ec: 429c cmp r4, r3
801b9ee: d12a bne.n 801ba46 <__swbuf_r+0x6e>
801b9f0: 686c ldr r4, [r5, #4]
801b9f2: 69a3 ldr r3, [r4, #24]
801b9f4: 60a3 str r3, [r4, #8]
801b9f6: 89a3 ldrh r3, [r4, #12]
801b9f8: 071a lsls r2, r3, #28
801b9fa: d52e bpl.n 801ba5a <__swbuf_r+0x82>
801b9fc: 6923 ldr r3, [r4, #16]
801b9fe: b363 cbz r3, 801ba5a <__swbuf_r+0x82>
801ba00: 6923 ldr r3, [r4, #16]
801ba02: 6820 ldr r0, [r4, #0]
801ba04: 1ac0 subs r0, r0, r3
801ba06: 6963 ldr r3, [r4, #20]
801ba08: b2f6 uxtb r6, r6
801ba0a: 4283 cmp r3, r0
801ba0c: 4637 mov r7, r6
801ba0e: dc04 bgt.n 801ba1a <__swbuf_r+0x42>
801ba10: 4621 mov r1, r4
801ba12: 4628 mov r0, r5
801ba14: f000 f948 bl 801bca8 <_fflush_r>
801ba18: bb28 cbnz r0, 801ba66 <__swbuf_r+0x8e>
801ba1a: 68a3 ldr r3, [r4, #8]
801ba1c: 3b01 subs r3, #1
801ba1e: 60a3 str r3, [r4, #8]
801ba20: 6823 ldr r3, [r4, #0]
801ba22: 1c5a adds r2, r3, #1
801ba24: 6022 str r2, [r4, #0]
801ba26: 701e strb r6, [r3, #0]
801ba28: 6963 ldr r3, [r4, #20]
801ba2a: 3001 adds r0, #1
801ba2c: 4283 cmp r3, r0
801ba2e: d004 beq.n 801ba3a <__swbuf_r+0x62>
801ba30: 89a3 ldrh r3, [r4, #12]
801ba32: 07db lsls r3, r3, #31
801ba34: d519 bpl.n 801ba6a <__swbuf_r+0x92>
801ba36: 2e0a cmp r6, #10
801ba38: d117 bne.n 801ba6a <__swbuf_r+0x92>
801ba3a: 4621 mov r1, r4
801ba3c: 4628 mov r0, r5
801ba3e: f000 f933 bl 801bca8 <_fflush_r>
801ba42: b190 cbz r0, 801ba6a <__swbuf_r+0x92>
801ba44: e00f b.n 801ba66 <__swbuf_r+0x8e>
801ba46: 4b0b ldr r3, [pc, #44] ; (801ba74 <__swbuf_r+0x9c>)
801ba48: 429c cmp r4, r3
801ba4a: d101 bne.n 801ba50 <__swbuf_r+0x78>
801ba4c: 68ac ldr r4, [r5, #8]
801ba4e: e7d0 b.n 801b9f2 <__swbuf_r+0x1a>
801ba50: 4b09 ldr r3, [pc, #36] ; (801ba78 <__swbuf_r+0xa0>)
801ba52: 429c cmp r4, r3
801ba54: bf08 it eq
801ba56: 68ec ldreq r4, [r5, #12]
801ba58: e7cb b.n 801b9f2 <__swbuf_r+0x1a>
801ba5a: 4621 mov r1, r4
801ba5c: 4628 mov r0, r5
801ba5e: f000 f81f bl 801baa0 <__swsetup_r>
801ba62: 2800 cmp r0, #0
801ba64: d0cc beq.n 801ba00 <__swbuf_r+0x28>
801ba66: f04f 37ff mov.w r7, #4294967295
801ba6a: 4638 mov r0, r7
801ba6c: bdf8 pop {r3, r4, r5, r6, r7, pc}
801ba6e: bf00 nop
801ba70: 08020eac .word 0x08020eac
801ba74: 08020ecc .word 0x08020ecc
801ba78: 08020e8c .word 0x08020e8c
0801ba7c <_write_r>:
801ba7c: b538 push {r3, r4, r5, lr}
801ba7e: 4c07 ldr r4, [pc, #28] ; (801ba9c <_write_r+0x20>)
801ba80: 4605 mov r5, r0
801ba82: 4608 mov r0, r1
801ba84: 4611 mov r1, r2
801ba86: 2200 movs r2, #0
801ba88: 6022 str r2, [r4, #0]
801ba8a: 461a mov r2, r3
801ba8c: f7e8 fe9b bl 80047c6 <_write>
801ba90: 1c43 adds r3, r0, #1
801ba92: d102 bne.n 801ba9a <_write_r+0x1e>
801ba94: 6823 ldr r3, [r4, #0]
801ba96: b103 cbz r3, 801ba9a <_write_r+0x1e>
801ba98: 602b str r3, [r5, #0]
801ba9a: bd38 pop {r3, r4, r5, pc}
801ba9c: 2000f604 .word 0x2000f604
0801baa0 <__swsetup_r>:
801baa0: 4b32 ldr r3, [pc, #200] ; (801bb6c <__swsetup_r+0xcc>)
801baa2: b570 push {r4, r5, r6, lr}
801baa4: 681d ldr r5, [r3, #0]
801baa6: 4606 mov r6, r0
801baa8: 460c mov r4, r1
801baaa: b125 cbz r5, 801bab6 <__swsetup_r+0x16>
801baac: 69ab ldr r3, [r5, #24]
801baae: b913 cbnz r3, 801bab6 <__swsetup_r+0x16>
801bab0: 4628 mov r0, r5
801bab2: f7ff fb3b bl 801b12c <__sinit>
801bab6: 4b2e ldr r3, [pc, #184] ; (801bb70 <__swsetup_r+0xd0>)
801bab8: 429c cmp r4, r3
801baba: d10f bne.n 801badc <__swsetup_r+0x3c>
801babc: 686c ldr r4, [r5, #4]
801babe: f9b4 300c ldrsh.w r3, [r4, #12]
801bac2: b29a uxth r2, r3
801bac4: 0715 lsls r5, r2, #28
801bac6: d42c bmi.n 801bb22 <__swsetup_r+0x82>
801bac8: 06d0 lsls r0, r2, #27
801baca: d411 bmi.n 801baf0 <__swsetup_r+0x50>
801bacc: 2209 movs r2, #9
801bace: 6032 str r2, [r6, #0]
801bad0: f043 0340 orr.w r3, r3, #64 ; 0x40
801bad4: 81a3 strh r3, [r4, #12]
801bad6: f04f 30ff mov.w r0, #4294967295
801bada: e03e b.n 801bb5a <__swsetup_r+0xba>
801badc: 4b25 ldr r3, [pc, #148] ; (801bb74 <__swsetup_r+0xd4>)
801bade: 429c cmp r4, r3
801bae0: d101 bne.n 801bae6 <__swsetup_r+0x46>
801bae2: 68ac ldr r4, [r5, #8]
801bae4: e7eb b.n 801babe <__swsetup_r+0x1e>
801bae6: 4b24 ldr r3, [pc, #144] ; (801bb78 <__swsetup_r+0xd8>)
801bae8: 429c cmp r4, r3
801baea: bf08 it eq
801baec: 68ec ldreq r4, [r5, #12]
801baee: e7e6 b.n 801babe <__swsetup_r+0x1e>
801baf0: 0751 lsls r1, r2, #29
801baf2: d512 bpl.n 801bb1a <__swsetup_r+0x7a>
801baf4: 6b61 ldr r1, [r4, #52] ; 0x34
801baf6: b141 cbz r1, 801bb0a <__swsetup_r+0x6a>
801baf8: f104 0344 add.w r3, r4, #68 ; 0x44
801bafc: 4299 cmp r1, r3
801bafe: d002 beq.n 801bb06 <__swsetup_r+0x66>
801bb00: 4630 mov r0, r6
801bb02: f7ff fba5 bl 801b250 <_free_r>
801bb06: 2300 movs r3, #0
801bb08: 6363 str r3, [r4, #52] ; 0x34
801bb0a: 89a3 ldrh r3, [r4, #12]
801bb0c: f023 0324 bic.w r3, r3, #36 ; 0x24
801bb10: 81a3 strh r3, [r4, #12]
801bb12: 2300 movs r3, #0
801bb14: 6063 str r3, [r4, #4]
801bb16: 6923 ldr r3, [r4, #16]
801bb18: 6023 str r3, [r4, #0]
801bb1a: 89a3 ldrh r3, [r4, #12]
801bb1c: f043 0308 orr.w r3, r3, #8
801bb20: 81a3 strh r3, [r4, #12]
801bb22: 6923 ldr r3, [r4, #16]
801bb24: b94b cbnz r3, 801bb3a <__swsetup_r+0x9a>
801bb26: 89a3 ldrh r3, [r4, #12]
801bb28: f403 7320 and.w r3, r3, #640 ; 0x280
801bb2c: f5b3 7f00 cmp.w r3, #512 ; 0x200
801bb30: d003 beq.n 801bb3a <__swsetup_r+0x9a>
801bb32: 4621 mov r1, r4
801bb34: 4630 mov r0, r6
801bb36: f000 f917 bl 801bd68 <__smakebuf_r>
801bb3a: 89a2 ldrh r2, [r4, #12]
801bb3c: f012 0301 ands.w r3, r2, #1
801bb40: d00c beq.n 801bb5c <__swsetup_r+0xbc>
801bb42: 2300 movs r3, #0
801bb44: 60a3 str r3, [r4, #8]
801bb46: 6963 ldr r3, [r4, #20]
801bb48: 425b negs r3, r3
801bb4a: 61a3 str r3, [r4, #24]
801bb4c: 6923 ldr r3, [r4, #16]
801bb4e: b953 cbnz r3, 801bb66 <__swsetup_r+0xc6>
801bb50: f9b4 300c ldrsh.w r3, [r4, #12]
801bb54: f013 0080 ands.w r0, r3, #128 ; 0x80
801bb58: d1ba bne.n 801bad0 <__swsetup_r+0x30>
801bb5a: bd70 pop {r4, r5, r6, pc}
801bb5c: 0792 lsls r2, r2, #30
801bb5e: bf58 it pl
801bb60: 6963 ldrpl r3, [r4, #20]
801bb62: 60a3 str r3, [r4, #8]
801bb64: e7f2 b.n 801bb4c <__swsetup_r+0xac>
801bb66: 2000 movs r0, #0
801bb68: e7f7 b.n 801bb5a <__swsetup_r+0xba>
801bb6a: bf00 nop
801bb6c: 20000084 .word 0x20000084
801bb70: 08020eac .word 0x08020eac
801bb74: 08020ecc .word 0x08020ecc
801bb78: 08020e8c .word 0x08020e8c
0801bb7c <_close_r>:
801bb7c: b538 push {r3, r4, r5, lr}
801bb7e: 4c06 ldr r4, [pc, #24] ; (801bb98 <_close_r+0x1c>)
801bb80: 2300 movs r3, #0
801bb82: 4605 mov r5, r0
801bb84: 4608 mov r0, r1
801bb86: 6023 str r3, [r4, #0]
801bb88: f7e8 fe39 bl 80047fe <_close>
801bb8c: 1c43 adds r3, r0, #1
801bb8e: d102 bne.n 801bb96 <_close_r+0x1a>
801bb90: 6823 ldr r3, [r4, #0]
801bb92: b103 cbz r3, 801bb96 <_close_r+0x1a>
801bb94: 602b str r3, [r5, #0]
801bb96: bd38 pop {r3, r4, r5, pc}
801bb98: 2000f604 .word 0x2000f604
0801bb9c <__sflush_r>:
801bb9c: 898a ldrh r2, [r1, #12]
801bb9e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801bba2: 4605 mov r5, r0
801bba4: 0710 lsls r0, r2, #28
801bba6: 460c mov r4, r1
801bba8: d458 bmi.n 801bc5c <__sflush_r+0xc0>
801bbaa: 684b ldr r3, [r1, #4]
801bbac: 2b00 cmp r3, #0
801bbae: dc05 bgt.n 801bbbc <__sflush_r+0x20>
801bbb0: 6c0b ldr r3, [r1, #64] ; 0x40
801bbb2: 2b00 cmp r3, #0
801bbb4: dc02 bgt.n 801bbbc <__sflush_r+0x20>
801bbb6: 2000 movs r0, #0
801bbb8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801bbbc: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bbbe: 2e00 cmp r6, #0
801bbc0: d0f9 beq.n 801bbb6 <__sflush_r+0x1a>
801bbc2: 2300 movs r3, #0
801bbc4: f412 5280 ands.w r2, r2, #4096 ; 0x1000
801bbc8: 682f ldr r7, [r5, #0]
801bbca: 6a21 ldr r1, [r4, #32]
801bbcc: 602b str r3, [r5, #0]
801bbce: d032 beq.n 801bc36 <__sflush_r+0x9a>
801bbd0: 6d60 ldr r0, [r4, #84] ; 0x54
801bbd2: 89a3 ldrh r3, [r4, #12]
801bbd4: 075a lsls r2, r3, #29
801bbd6: d505 bpl.n 801bbe4 <__sflush_r+0x48>
801bbd8: 6863 ldr r3, [r4, #4]
801bbda: 1ac0 subs r0, r0, r3
801bbdc: 6b63 ldr r3, [r4, #52] ; 0x34
801bbde: b10b cbz r3, 801bbe4 <__sflush_r+0x48>
801bbe0: 6c23 ldr r3, [r4, #64] ; 0x40
801bbe2: 1ac0 subs r0, r0, r3
801bbe4: 2300 movs r3, #0
801bbe6: 4602 mov r2, r0
801bbe8: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bbea: 6a21 ldr r1, [r4, #32]
801bbec: 4628 mov r0, r5
801bbee: 47b0 blx r6
801bbf0: 1c43 adds r3, r0, #1
801bbf2: 89a3 ldrh r3, [r4, #12]
801bbf4: d106 bne.n 801bc04 <__sflush_r+0x68>
801bbf6: 6829 ldr r1, [r5, #0]
801bbf8: 291d cmp r1, #29
801bbfa: d848 bhi.n 801bc8e <__sflush_r+0xf2>
801bbfc: 4a29 ldr r2, [pc, #164] ; (801bca4 <__sflush_r+0x108>)
801bbfe: 40ca lsrs r2, r1
801bc00: 07d6 lsls r6, r2, #31
801bc02: d544 bpl.n 801bc8e <__sflush_r+0xf2>
801bc04: 2200 movs r2, #0
801bc06: 6062 str r2, [r4, #4]
801bc08: 04d9 lsls r1, r3, #19
801bc0a: 6922 ldr r2, [r4, #16]
801bc0c: 6022 str r2, [r4, #0]
801bc0e: d504 bpl.n 801bc1a <__sflush_r+0x7e>
801bc10: 1c42 adds r2, r0, #1
801bc12: d101 bne.n 801bc18 <__sflush_r+0x7c>
801bc14: 682b ldr r3, [r5, #0]
801bc16: b903 cbnz r3, 801bc1a <__sflush_r+0x7e>
801bc18: 6560 str r0, [r4, #84] ; 0x54
801bc1a: 6b61 ldr r1, [r4, #52] ; 0x34
801bc1c: 602f str r7, [r5, #0]
801bc1e: 2900 cmp r1, #0
801bc20: d0c9 beq.n 801bbb6 <__sflush_r+0x1a>
801bc22: f104 0344 add.w r3, r4, #68 ; 0x44
801bc26: 4299 cmp r1, r3
801bc28: d002 beq.n 801bc30 <__sflush_r+0x94>
801bc2a: 4628 mov r0, r5
801bc2c: f7ff fb10 bl 801b250 <_free_r>
801bc30: 2000 movs r0, #0
801bc32: 6360 str r0, [r4, #52] ; 0x34
801bc34: e7c0 b.n 801bbb8 <__sflush_r+0x1c>
801bc36: 2301 movs r3, #1
801bc38: 4628 mov r0, r5
801bc3a: 47b0 blx r6
801bc3c: 1c41 adds r1, r0, #1
801bc3e: d1c8 bne.n 801bbd2 <__sflush_r+0x36>
801bc40: 682b ldr r3, [r5, #0]
801bc42: 2b00 cmp r3, #0
801bc44: d0c5 beq.n 801bbd2 <__sflush_r+0x36>
801bc46: 2b1d cmp r3, #29
801bc48: d001 beq.n 801bc4e <__sflush_r+0xb2>
801bc4a: 2b16 cmp r3, #22
801bc4c: d101 bne.n 801bc52 <__sflush_r+0xb6>
801bc4e: 602f str r7, [r5, #0]
801bc50: e7b1 b.n 801bbb6 <__sflush_r+0x1a>
801bc52: 89a3 ldrh r3, [r4, #12]
801bc54: f043 0340 orr.w r3, r3, #64 ; 0x40
801bc58: 81a3 strh r3, [r4, #12]
801bc5a: e7ad b.n 801bbb8 <__sflush_r+0x1c>
801bc5c: 690f ldr r7, [r1, #16]
801bc5e: 2f00 cmp r7, #0
801bc60: d0a9 beq.n 801bbb6 <__sflush_r+0x1a>
801bc62: 0793 lsls r3, r2, #30
801bc64: 680e ldr r6, [r1, #0]
801bc66: bf08 it eq
801bc68: 694b ldreq r3, [r1, #20]
801bc6a: 600f str r7, [r1, #0]
801bc6c: bf18 it ne
801bc6e: 2300 movne r3, #0
801bc70: eba6 0807 sub.w r8, r6, r7
801bc74: 608b str r3, [r1, #8]
801bc76: f1b8 0f00 cmp.w r8, #0
801bc7a: dd9c ble.n 801bbb6 <__sflush_r+0x1a>
801bc7c: 4643 mov r3, r8
801bc7e: 463a mov r2, r7
801bc80: 6a21 ldr r1, [r4, #32]
801bc82: 6aa6 ldr r6, [r4, #40] ; 0x28
801bc84: 4628 mov r0, r5
801bc86: 47b0 blx r6
801bc88: 2800 cmp r0, #0
801bc8a: dc06 bgt.n 801bc9a <__sflush_r+0xfe>
801bc8c: 89a3 ldrh r3, [r4, #12]
801bc8e: f043 0340 orr.w r3, r3, #64 ; 0x40
801bc92: 81a3 strh r3, [r4, #12]
801bc94: f04f 30ff mov.w r0, #4294967295
801bc98: e78e b.n 801bbb8 <__sflush_r+0x1c>
801bc9a: 4407 add r7, r0
801bc9c: eba8 0800 sub.w r8, r8, r0
801bca0: e7e9 b.n 801bc76 <__sflush_r+0xda>
801bca2: bf00 nop
801bca4: 20400001 .word 0x20400001
0801bca8 <_fflush_r>:
801bca8: b538 push {r3, r4, r5, lr}
801bcaa: 690b ldr r3, [r1, #16]
801bcac: 4605 mov r5, r0
801bcae: 460c mov r4, r1
801bcb0: b1db cbz r3, 801bcea <_fflush_r+0x42>
801bcb2: b118 cbz r0, 801bcbc <_fflush_r+0x14>
801bcb4: 6983 ldr r3, [r0, #24]
801bcb6: b90b cbnz r3, 801bcbc <_fflush_r+0x14>
801bcb8: f7ff fa38 bl 801b12c <__sinit>
801bcbc: 4b0c ldr r3, [pc, #48] ; (801bcf0 <_fflush_r+0x48>)
801bcbe: 429c cmp r4, r3
801bcc0: d109 bne.n 801bcd6 <_fflush_r+0x2e>
801bcc2: 686c ldr r4, [r5, #4]
801bcc4: f9b4 300c ldrsh.w r3, [r4, #12]
801bcc8: b17b cbz r3, 801bcea <_fflush_r+0x42>
801bcca: 4621 mov r1, r4
801bccc: 4628 mov r0, r5
801bcce: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801bcd2: f7ff bf63 b.w 801bb9c <__sflush_r>
801bcd6: 4b07 ldr r3, [pc, #28] ; (801bcf4 <_fflush_r+0x4c>)
801bcd8: 429c cmp r4, r3
801bcda: d101 bne.n 801bce0 <_fflush_r+0x38>
801bcdc: 68ac ldr r4, [r5, #8]
801bcde: e7f1 b.n 801bcc4 <_fflush_r+0x1c>
801bce0: 4b05 ldr r3, [pc, #20] ; (801bcf8 <_fflush_r+0x50>)
801bce2: 429c cmp r4, r3
801bce4: bf08 it eq
801bce6: 68ec ldreq r4, [r5, #12]
801bce8: e7ec b.n 801bcc4 <_fflush_r+0x1c>
801bcea: 2000 movs r0, #0
801bcec: bd38 pop {r3, r4, r5, pc}
801bcee: bf00 nop
801bcf0: 08020eac .word 0x08020eac
801bcf4: 08020ecc .word 0x08020ecc
801bcf8: 08020e8c .word 0x08020e8c
0801bcfc <_lseek_r>:
801bcfc: b538 push {r3, r4, r5, lr}
801bcfe: 4c07 ldr r4, [pc, #28] ; (801bd1c <_lseek_r+0x20>)
801bd00: 4605 mov r5, r0
801bd02: 4608 mov r0, r1
801bd04: 4611 mov r1, r2
801bd06: 2200 movs r2, #0
801bd08: 6022 str r2, [r4, #0]
801bd0a: 461a mov r2, r3
801bd0c: f7e8 fd9e bl 800484c <_lseek>
801bd10: 1c43 adds r3, r0, #1
801bd12: d102 bne.n 801bd1a <_lseek_r+0x1e>
801bd14: 6823 ldr r3, [r4, #0]
801bd16: b103 cbz r3, 801bd1a <_lseek_r+0x1e>
801bd18: 602b str r3, [r5, #0]
801bd1a: bd38 pop {r3, r4, r5, pc}
801bd1c: 2000f604 .word 0x2000f604
0801bd20 <__swhatbuf_r>:
801bd20: b570 push {r4, r5, r6, lr}
801bd22: 460e mov r6, r1
801bd24: f9b1 100e ldrsh.w r1, [r1, #14]
801bd28: 2900 cmp r1, #0
801bd2a: b096 sub sp, #88 ; 0x58
801bd2c: 4614 mov r4, r2
801bd2e: 461d mov r5, r3
801bd30: da07 bge.n 801bd42 <__swhatbuf_r+0x22>
801bd32: 2300 movs r3, #0
801bd34: 602b str r3, [r5, #0]
801bd36: 89b3 ldrh r3, [r6, #12]
801bd38: 061a lsls r2, r3, #24
801bd3a: d410 bmi.n 801bd5e <__swhatbuf_r+0x3e>
801bd3c: f44f 6380 mov.w r3, #1024 ; 0x400
801bd40: e00e b.n 801bd60 <__swhatbuf_r+0x40>
801bd42: 466a mov r2, sp
801bd44: f000 f864 bl 801be10 <_fstat_r>
801bd48: 2800 cmp r0, #0
801bd4a: dbf2 blt.n 801bd32 <__swhatbuf_r+0x12>
801bd4c: 9a01 ldr r2, [sp, #4]
801bd4e: f402 4270 and.w r2, r2, #61440 ; 0xf000
801bd52: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
801bd56: 425a negs r2, r3
801bd58: 415a adcs r2, r3
801bd5a: 602a str r2, [r5, #0]
801bd5c: e7ee b.n 801bd3c <__swhatbuf_r+0x1c>
801bd5e: 2340 movs r3, #64 ; 0x40
801bd60: 2000 movs r0, #0
801bd62: 6023 str r3, [r4, #0]
801bd64: b016 add sp, #88 ; 0x58
801bd66: bd70 pop {r4, r5, r6, pc}
0801bd68 <__smakebuf_r>:
801bd68: 898b ldrh r3, [r1, #12]
801bd6a: b573 push {r0, r1, r4, r5, r6, lr}
801bd6c: 079d lsls r5, r3, #30
801bd6e: 4606 mov r6, r0
801bd70: 460c mov r4, r1
801bd72: d507 bpl.n 801bd84 <__smakebuf_r+0x1c>
801bd74: f104 0347 add.w r3, r4, #71 ; 0x47
801bd78: 6023 str r3, [r4, #0]
801bd7a: 6123 str r3, [r4, #16]
801bd7c: 2301 movs r3, #1
801bd7e: 6163 str r3, [r4, #20]
801bd80: b002 add sp, #8
801bd82: bd70 pop {r4, r5, r6, pc}
801bd84: ab01 add r3, sp, #4
801bd86: 466a mov r2, sp
801bd88: f7ff ffca bl 801bd20 <__swhatbuf_r>
801bd8c: 9900 ldr r1, [sp, #0]
801bd8e: 4605 mov r5, r0
801bd90: 4630 mov r0, r6
801bd92: f7ff faab bl 801b2ec <_malloc_r>
801bd96: b948 cbnz r0, 801bdac <__smakebuf_r+0x44>
801bd98: f9b4 300c ldrsh.w r3, [r4, #12]
801bd9c: 059a lsls r2, r3, #22
801bd9e: d4ef bmi.n 801bd80 <__smakebuf_r+0x18>
801bda0: f023 0303 bic.w r3, r3, #3
801bda4: f043 0302 orr.w r3, r3, #2
801bda8: 81a3 strh r3, [r4, #12]
801bdaa: e7e3 b.n 801bd74 <__smakebuf_r+0xc>
801bdac: 4b0d ldr r3, [pc, #52] ; (801bde4 <__smakebuf_r+0x7c>)
801bdae: 62b3 str r3, [r6, #40] ; 0x28
801bdb0: 89a3 ldrh r3, [r4, #12]
801bdb2: 6020 str r0, [r4, #0]
801bdb4: f043 0380 orr.w r3, r3, #128 ; 0x80
801bdb8: 81a3 strh r3, [r4, #12]
801bdba: 9b00 ldr r3, [sp, #0]
801bdbc: 6163 str r3, [r4, #20]
801bdbe: 9b01 ldr r3, [sp, #4]
801bdc0: 6120 str r0, [r4, #16]
801bdc2: b15b cbz r3, 801bddc <__smakebuf_r+0x74>
801bdc4: f9b4 100e ldrsh.w r1, [r4, #14]
801bdc8: 4630 mov r0, r6
801bdca: f000 f833 bl 801be34 <_isatty_r>
801bdce: b128 cbz r0, 801bddc <__smakebuf_r+0x74>
801bdd0: 89a3 ldrh r3, [r4, #12]
801bdd2: f023 0303 bic.w r3, r3, #3
801bdd6: f043 0301 orr.w r3, r3, #1
801bdda: 81a3 strh r3, [r4, #12]
801bddc: 89a3 ldrh r3, [r4, #12]
801bdde: 431d orrs r5, r3
801bde0: 81a5 strh r5, [r4, #12]
801bde2: e7cd b.n 801bd80 <__smakebuf_r+0x18>
801bde4: 0801b0f5 .word 0x0801b0f5
0801bde8 <__malloc_lock>:
801bde8: 4770 bx lr
0801bdea <__malloc_unlock>:
801bdea: 4770 bx lr
0801bdec <_read_r>:
801bdec: b538 push {r3, r4, r5, lr}
801bdee: 4c07 ldr r4, [pc, #28] ; (801be0c <_read_r+0x20>)
801bdf0: 4605 mov r5, r0
801bdf2: 4608 mov r0, r1
801bdf4: 4611 mov r1, r2
801bdf6: 2200 movs r2, #0
801bdf8: 6022 str r2, [r4, #0]
801bdfa: 461a mov r2, r3
801bdfc: f7e8 fcc6 bl 800478c <_read>
801be00: 1c43 adds r3, r0, #1
801be02: d102 bne.n 801be0a <_read_r+0x1e>
801be04: 6823 ldr r3, [r4, #0]
801be06: b103 cbz r3, 801be0a <_read_r+0x1e>
801be08: 602b str r3, [r5, #0]
801be0a: bd38 pop {r3, r4, r5, pc}
801be0c: 2000f604 .word 0x2000f604
0801be10 <_fstat_r>:
801be10: b538 push {r3, r4, r5, lr}
801be12: 4c07 ldr r4, [pc, #28] ; (801be30 <_fstat_r+0x20>)
801be14: 2300 movs r3, #0
801be16: 4605 mov r5, r0
801be18: 4608 mov r0, r1
801be1a: 4611 mov r1, r2
801be1c: 6023 str r3, [r4, #0]
801be1e: f7e8 fcfa bl 8004816 <_fstat>
801be22: 1c43 adds r3, r0, #1
801be24: d102 bne.n 801be2c <_fstat_r+0x1c>
801be26: 6823 ldr r3, [r4, #0]
801be28: b103 cbz r3, 801be2c <_fstat_r+0x1c>
801be2a: 602b str r3, [r5, #0]
801be2c: bd38 pop {r3, r4, r5, pc}
801be2e: bf00 nop
801be30: 2000f604 .word 0x2000f604
0801be34 <_isatty_r>:
801be34: b538 push {r3, r4, r5, lr}
801be36: 4c06 ldr r4, [pc, #24] ; (801be50 <_isatty_r+0x1c>)
801be38: 2300 movs r3, #0
801be3a: 4605 mov r5, r0
801be3c: 4608 mov r0, r1
801be3e: 6023 str r3, [r4, #0]
801be40: f7e8 fcf9 bl 8004836 <_isatty>
801be44: 1c43 adds r3, r0, #1
801be46: d102 bne.n 801be4e <_isatty_r+0x1a>
801be48: 6823 ldr r3, [r4, #0]
801be4a: b103 cbz r3, 801be4e <_isatty_r+0x1a>
801be4c: 602b str r3, [r5, #0]
801be4e: bd38 pop {r3, r4, r5, pc}
801be50: 2000f604 .word 0x2000f604
0801be54 <_init>:
801be54: b5f8 push {r3, r4, r5, r6, r7, lr}
801be56: bf00 nop
801be58: bcf8 pop {r3, r4, r5, r6, r7}
801be5a: bc08 pop {r3}
801be5c: 469e mov lr, r3
801be5e: 4770 bx lr
0801be60 <_fini>:
801be60: b5f8 push {r3, r4, r5, r6, r7, lr}
801be62: bf00 nop
801be64: bcf8 pop {r3, r4, r5, r6, r7}
801be66: bc08 pop {r3}
801be68: 469e mov lr, r3
801be6a: 4770 bx lr
Reference in a new issue View git blame Copy permalink