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Space_Invaders
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Space_Invaders/Debug/Space_Invaders.list

75231 lines
2.8 MiB
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Space_Invaders.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0001bcac 080001d0 080001d0 000101d0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000050b4 0801be7c 0801be7c 0002be7c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08020f30 08020f30 000400e8 2**0
CONTENTS
4 .ARM 00000008 08020f30 08020f30 00030f30 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08020f38 08020f38 000400e8 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08020f38 08020f38 00030f38 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08020f3c 08020f3c 00030f3c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 000000e8 20000000 08020f40 00040000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000f524 200000e8 08021028 000400e8 2**2
ALLOC
10 ._user_heap_stack 00000604 2000f60c 08021028 0004f60c 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 000400e8 2**0
CONTENTS, READONLY
12 .debug_info 00050ade 00000000 00000000 00040118 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 000096fb 00000000 00000000 00090bf6 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 000030e8 00000000 00000000 0009a2f8 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00002e30 00000000 00000000 0009d3e0 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 0003bc39 00000000 00000000 000a0210 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00039110 00000000 00000000 000dbe49 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 00127a3a 00000000 00000000 00114f59 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 0023c993 2**0
CONTENTS, READONLY
20 .debug_frame 0000d120 00000000 00000000 0023ca10 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080001d0 <__do_global_dtors_aux>:
80001d0: b510 push {r4, lr}
80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
80001d4: 7823 ldrb r3, [r4, #0]
80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
80001de: f3af 8000 nop.w
80001e2: 2301 movs r3, #1
80001e4: 7023 strb r3, [r4, #0]
80001e6: bd10 pop {r4, pc}
80001e8: 200000e8 .word 0x200000e8
80001ec: 00000000 .word 0x00000000
80001f0: 0801be64 .word 0x0801be64
080001f4 <frame_dummy>:
80001f4: b508 push {r3, lr}
80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 <frame_dummy+0x10>)
80001f8: b11b cbz r3, 8000202 <frame_dummy+0xe>
80001fa: 4903 ldr r1, [pc, #12] ; (8000208 <frame_dummy+0x14>)
80001fc: 4803 ldr r0, [pc, #12] ; (800020c <frame_dummy+0x18>)
80001fe: f3af 8000 nop.w
8000202: bd08 pop {r3, pc}
8000204: 00000000 .word 0x00000000
8000208: 200000ec .word 0x200000ec
800020c: 0801be64 .word 0x0801be64
08000210 <memchr>:
8000210: f001 01ff and.w r1, r1, #255 ; 0xff
8000214: 2a10 cmp r2, #16
8000216: db2b blt.n 8000270 <memchr+0x60>
8000218: f010 0f07 tst.w r0, #7
800021c: d008 beq.n 8000230 <memchr+0x20>
800021e: f810 3b01 ldrb.w r3, [r0], #1
8000222: 3a01 subs r2, #1
8000224: 428b cmp r3, r1
8000226: d02d beq.n 8000284 <memchr+0x74>
8000228: f010 0f07 tst.w r0, #7
800022c: b342 cbz r2, 8000280 <memchr+0x70>
800022e: d1f6 bne.n 800021e <memchr+0xe>
8000230: b4f0 push {r4, r5, r6, r7}
8000232: ea41 2101 orr.w r1, r1, r1, lsl #8
8000236: ea41 4101 orr.w r1, r1, r1, lsl #16
800023a: f022 0407 bic.w r4, r2, #7
800023e: f07f 0700 mvns.w r7, #0
8000242: 2300 movs r3, #0
8000244: e8f0 5602 ldrd r5, r6, [r0], #8
8000248: 3c08 subs r4, #8
800024a: ea85 0501 eor.w r5, r5, r1
800024e: ea86 0601 eor.w r6, r6, r1
8000252: fa85 f547 uadd8 r5, r5, r7
8000256: faa3 f587 sel r5, r3, r7
800025a: fa86 f647 uadd8 r6, r6, r7
800025e: faa5 f687 sel r6, r5, r7
8000262: b98e cbnz r6, 8000288 <memchr+0x78>
8000264: d1ee bne.n 8000244 <memchr+0x34>
8000266: bcf0 pop {r4, r5, r6, r7}
8000268: f001 01ff and.w r1, r1, #255 ; 0xff
800026c: f002 0207 and.w r2, r2, #7
8000270: b132 cbz r2, 8000280 <memchr+0x70>
8000272: f810 3b01 ldrb.w r3, [r0], #1
8000276: 3a01 subs r2, #1
8000278: ea83 0301 eor.w r3, r3, r1
800027c: b113 cbz r3, 8000284 <memchr+0x74>
800027e: d1f8 bne.n 8000272 <memchr+0x62>
8000280: 2000 movs r0, #0
8000282: 4770 bx lr
8000284: 3801 subs r0, #1
8000286: 4770 bx lr
8000288: 2d00 cmp r5, #0
800028a: bf06 itte eq
800028c: 4635 moveq r5, r6
800028e: 3803 subeq r0, #3
8000290: 3807 subne r0, #7
8000292: f015 0f01 tst.w r5, #1
8000296: d107 bne.n 80002a8 <memchr+0x98>
8000298: 3001 adds r0, #1
800029a: f415 7f80 tst.w r5, #256 ; 0x100
800029e: bf02 ittt eq
80002a0: 3001 addeq r0, #1
80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
80002a6: 3001 addeq r0, #1
80002a8: bcf0 pop {r4, r5, r6, r7}
80002aa: 3801 subs r0, #1
80002ac: 4770 bx lr
80002ae: bf00 nop
080002b0 <__aeabi_uldivmod>:
80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18>
80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18>
80002b4: 2900 cmp r1, #0
80002b6: bf08 it eq
80002b8: 2800 cmpeq r0, #0
80002ba: bf1c itt ne
80002bc: f04f 31ff movne.w r1, #4294967295
80002c0: f04f 30ff movne.w r0, #4294967295
80002c4: f000 b972 b.w 80005ac <__aeabi_idiv0>
80002c8: f1ad 0c08 sub.w ip, sp, #8
80002cc: e96d ce04 strd ip, lr, [sp, #-16]!
80002d0: f000 f806 bl 80002e0 <__udivmoddi4>
80002d4: f8dd e004 ldr.w lr, [sp, #4]
80002d8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002dc: b004 add sp, #16
80002de: 4770 bx lr
080002e0 <__udivmoddi4>:
80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002e4: 9e08 ldr r6, [sp, #32]
80002e6: 4604 mov r4, r0
80002e8: 4688 mov r8, r1
80002ea: 2b00 cmp r3, #0
80002ec: d14b bne.n 8000386 <__udivmoddi4+0xa6>
80002ee: 428a cmp r2, r1
80002f0: 4615 mov r5, r2
80002f2: d967 bls.n 80003c4 <__udivmoddi4+0xe4>
80002f4: fab2 f282 clz r2, r2
80002f8: b14a cbz r2, 800030e <__udivmoddi4+0x2e>
80002fa: f1c2 0720 rsb r7, r2, #32
80002fe: fa01 f302 lsl.w r3, r1, r2
8000302: fa20 f707 lsr.w r7, r0, r7
8000306: 4095 lsls r5, r2
8000308: ea47 0803 orr.w r8, r7, r3
800030c: 4094 lsls r4, r2
800030e: ea4f 4e15 mov.w lr, r5, lsr #16
8000312: 0c23 lsrs r3, r4, #16
8000314: fbb8 f7fe udiv r7, r8, lr
8000318: fa1f fc85 uxth.w ip, r5
800031c: fb0e 8817 mls r8, lr, r7, r8
8000320: ea43 4308 orr.w r3, r3, r8, lsl #16
8000324: fb07 f10c mul.w r1, r7, ip
8000328: 4299 cmp r1, r3
800032a: d909 bls.n 8000340 <__udivmoddi4+0x60>
800032c: 18eb adds r3, r5, r3
800032e: f107 30ff add.w r0, r7, #4294967295
8000332: f080 811b bcs.w 800056c <__udivmoddi4+0x28c>
8000336: 4299 cmp r1, r3
8000338: f240 8118 bls.w 800056c <__udivmoddi4+0x28c>
800033c: 3f02 subs r7, #2
800033e: 442b add r3, r5
8000340: 1a5b subs r3, r3, r1
8000342: b2a4 uxth r4, r4
8000344: fbb3 f0fe udiv r0, r3, lr
8000348: fb0e 3310 mls r3, lr, r0, r3
800034c: ea44 4403 orr.w r4, r4, r3, lsl #16
8000350: fb00 fc0c mul.w ip, r0, ip
8000354: 45a4 cmp ip, r4
8000356: d909 bls.n 800036c <__udivmoddi4+0x8c>
8000358: 192c adds r4, r5, r4
800035a: f100 33ff add.w r3, r0, #4294967295
800035e: f080 8107 bcs.w 8000570 <__udivmoddi4+0x290>
8000362: 45a4 cmp ip, r4
8000364: f240 8104 bls.w 8000570 <__udivmoddi4+0x290>
8000368: 3802 subs r0, #2
800036a: 442c add r4, r5
800036c: ea40 4007 orr.w r0, r0, r7, lsl #16
8000370: eba4 040c sub.w r4, r4, ip
8000374: 2700 movs r7, #0
8000376: b11e cbz r6, 8000380 <__udivmoddi4+0xa0>
8000378: 40d4 lsrs r4, r2
800037a: 2300 movs r3, #0
800037c: e9c6 4300 strd r4, r3, [r6]
8000380: 4639 mov r1, r7
8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000386: 428b cmp r3, r1
8000388: d909 bls.n 800039e <__udivmoddi4+0xbe>
800038a: 2e00 cmp r6, #0
800038c: f000 80eb beq.w 8000566 <__udivmoddi4+0x286>
8000390: 2700 movs r7, #0
8000392: e9c6 0100 strd r0, r1, [r6]
8000396: 4638 mov r0, r7
8000398: 4639 mov r1, r7
800039a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800039e: fab3 f783 clz r7, r3
80003a2: 2f00 cmp r7, #0
80003a4: d147 bne.n 8000436 <__udivmoddi4+0x156>
80003a6: 428b cmp r3, r1
80003a8: d302 bcc.n 80003b0 <__udivmoddi4+0xd0>
80003aa: 4282 cmp r2, r0
80003ac: f200 80fa bhi.w 80005a4 <__udivmoddi4+0x2c4>
80003b0: 1a84 subs r4, r0, r2
80003b2: eb61 0303 sbc.w r3, r1, r3
80003b6: 2001 movs r0, #1
80003b8: 4698 mov r8, r3
80003ba: 2e00 cmp r6, #0
80003bc: d0e0 beq.n 8000380 <__udivmoddi4+0xa0>
80003be: e9c6 4800 strd r4, r8, [r6]
80003c2: e7dd b.n 8000380 <__udivmoddi4+0xa0>
80003c4: b902 cbnz r2, 80003c8 <__udivmoddi4+0xe8>
80003c6: deff udf #255 ; 0xff
80003c8: fab2 f282 clz r2, r2
80003cc: 2a00 cmp r2, #0
80003ce: f040 808f bne.w 80004f0 <__udivmoddi4+0x210>
80003d2: 1b49 subs r1, r1, r5
80003d4: ea4f 4e15 mov.w lr, r5, lsr #16
80003d8: fa1f f885 uxth.w r8, r5
80003dc: 2701 movs r7, #1
80003de: fbb1 fcfe udiv ip, r1, lr
80003e2: 0c23 lsrs r3, r4, #16
80003e4: fb0e 111c mls r1, lr, ip, r1
80003e8: ea43 4301 orr.w r3, r3, r1, lsl #16
80003ec: fb08 f10c mul.w r1, r8, ip
80003f0: 4299 cmp r1, r3
80003f2: d907 bls.n 8000404 <__udivmoddi4+0x124>
80003f4: 18eb adds r3, r5, r3
80003f6: f10c 30ff add.w r0, ip, #4294967295
80003fa: d202 bcs.n 8000402 <__udivmoddi4+0x122>
80003fc: 4299 cmp r1, r3
80003fe: f200 80cd bhi.w 800059c <__udivmoddi4+0x2bc>
8000402: 4684 mov ip, r0
8000404: 1a59 subs r1, r3, r1
8000406: b2a3 uxth r3, r4
8000408: fbb1 f0fe udiv r0, r1, lr
800040c: fb0e 1410 mls r4, lr, r0, r1
8000410: ea43 4404 orr.w r4, r3, r4, lsl #16
8000414: fb08 f800 mul.w r8, r8, r0
8000418: 45a0 cmp r8, r4
800041a: d907 bls.n 800042c <__udivmoddi4+0x14c>
800041c: 192c adds r4, r5, r4
800041e: f100 33ff add.w r3, r0, #4294967295
8000422: d202 bcs.n 800042a <__udivmoddi4+0x14a>
8000424: 45a0 cmp r8, r4
8000426: f200 80b6 bhi.w 8000596 <__udivmoddi4+0x2b6>
800042a: 4618 mov r0, r3
800042c: eba4 0408 sub.w r4, r4, r8
8000430: ea40 400c orr.w r0, r0, ip, lsl #16
8000434: e79f b.n 8000376 <__udivmoddi4+0x96>
8000436: f1c7 0c20 rsb ip, r7, #32
800043a: 40bb lsls r3, r7
800043c: fa22 fe0c lsr.w lr, r2, ip
8000440: ea4e 0e03 orr.w lr, lr, r3
8000444: fa01 f407 lsl.w r4, r1, r7
8000448: fa20 f50c lsr.w r5, r0, ip
800044c: fa21 f30c lsr.w r3, r1, ip
8000450: ea4f 481e mov.w r8, lr, lsr #16
8000454: 4325 orrs r5, r4
8000456: fbb3 f9f8 udiv r9, r3, r8
800045a: 0c2c lsrs r4, r5, #16
800045c: fb08 3319 mls r3, r8, r9, r3
8000460: fa1f fa8e uxth.w sl, lr
8000464: ea44 4303 orr.w r3, r4, r3, lsl #16
8000468: fb09 f40a mul.w r4, r9, sl
800046c: 429c cmp r4, r3
800046e: fa02 f207 lsl.w r2, r2, r7
8000472: fa00 f107 lsl.w r1, r0, r7
8000476: d90b bls.n 8000490 <__udivmoddi4+0x1b0>
8000478: eb1e 0303 adds.w r3, lr, r3
800047c: f109 30ff add.w r0, r9, #4294967295
8000480: f080 8087 bcs.w 8000592 <__udivmoddi4+0x2b2>
8000484: 429c cmp r4, r3
8000486: f240 8084 bls.w 8000592 <__udivmoddi4+0x2b2>
800048a: f1a9 0902 sub.w r9, r9, #2
800048e: 4473 add r3, lr
8000490: 1b1b subs r3, r3, r4
8000492: b2ad uxth r5, r5
8000494: fbb3 f0f8 udiv r0, r3, r8
8000498: fb08 3310 mls r3, r8, r0, r3
800049c: ea45 4403 orr.w r4, r5, r3, lsl #16
80004a0: fb00 fa0a mul.w sl, r0, sl
80004a4: 45a2 cmp sl, r4
80004a6: d908 bls.n 80004ba <__udivmoddi4+0x1da>
80004a8: eb1e 0404 adds.w r4, lr, r4
80004ac: f100 33ff add.w r3, r0, #4294967295
80004b0: d26b bcs.n 800058a <__udivmoddi4+0x2aa>
80004b2: 45a2 cmp sl, r4
80004b4: d969 bls.n 800058a <__udivmoddi4+0x2aa>
80004b6: 3802 subs r0, #2
80004b8: 4474 add r4, lr
80004ba: ea40 4009 orr.w r0, r0, r9, lsl #16
80004be: fba0 8902 umull r8, r9, r0, r2
80004c2: eba4 040a sub.w r4, r4, sl
80004c6: 454c cmp r4, r9
80004c8: 46c2 mov sl, r8
80004ca: 464b mov r3, r9
80004cc: d354 bcc.n 8000578 <__udivmoddi4+0x298>
80004ce: d051 beq.n 8000574 <__udivmoddi4+0x294>
80004d0: 2e00 cmp r6, #0
80004d2: d069 beq.n 80005a8 <__udivmoddi4+0x2c8>
80004d4: ebb1 050a subs.w r5, r1, sl
80004d8: eb64 0403 sbc.w r4, r4, r3
80004dc: fa04 fc0c lsl.w ip, r4, ip
80004e0: 40fd lsrs r5, r7
80004e2: 40fc lsrs r4, r7
80004e4: ea4c 0505 orr.w r5, ip, r5
80004e8: e9c6 5400 strd r5, r4, [r6]
80004ec: 2700 movs r7, #0
80004ee: e747 b.n 8000380 <__udivmoddi4+0xa0>
80004f0: f1c2 0320 rsb r3, r2, #32
80004f4: fa20 f703 lsr.w r7, r0, r3
80004f8: 4095 lsls r5, r2
80004fa: fa01 f002 lsl.w r0, r1, r2
80004fe: fa21 f303 lsr.w r3, r1, r3
8000502: ea4f 4e15 mov.w lr, r5, lsr #16
8000506: 4338 orrs r0, r7
8000508: 0c01 lsrs r1, r0, #16
800050a: fbb3 f7fe udiv r7, r3, lr
800050e: fa1f f885 uxth.w r8, r5
8000512: fb0e 3317 mls r3, lr, r7, r3
8000516: ea41 4103 orr.w r1, r1, r3, lsl #16
800051a: fb07 f308 mul.w r3, r7, r8
800051e: 428b cmp r3, r1
8000520: fa04 f402 lsl.w r4, r4, r2
8000524: d907 bls.n 8000536 <__udivmoddi4+0x256>
8000526: 1869 adds r1, r5, r1
8000528: f107 3cff add.w ip, r7, #4294967295
800052c: d22f bcs.n 800058e <__udivmoddi4+0x2ae>
800052e: 428b cmp r3, r1
8000530: d92d bls.n 800058e <__udivmoddi4+0x2ae>
8000532: 3f02 subs r7, #2
8000534: 4429 add r1, r5
8000536: 1acb subs r3, r1, r3
8000538: b281 uxth r1, r0
800053a: fbb3 f0fe udiv r0, r3, lr
800053e: fb0e 3310 mls r3, lr, r0, r3
8000542: ea41 4103 orr.w r1, r1, r3, lsl #16
8000546: fb00 f308 mul.w r3, r0, r8
800054a: 428b cmp r3, r1
800054c: d907 bls.n 800055e <__udivmoddi4+0x27e>
800054e: 1869 adds r1, r5, r1
8000550: f100 3cff add.w ip, r0, #4294967295
8000554: d217 bcs.n 8000586 <__udivmoddi4+0x2a6>
8000556: 428b cmp r3, r1
8000558: d915 bls.n 8000586 <__udivmoddi4+0x2a6>
800055a: 3802 subs r0, #2
800055c: 4429 add r1, r5
800055e: 1ac9 subs r1, r1, r3
8000560: ea40 4707 orr.w r7, r0, r7, lsl #16
8000564: e73b b.n 80003de <__udivmoddi4+0xfe>
8000566: 4637 mov r7, r6
8000568: 4630 mov r0, r6
800056a: e709 b.n 8000380 <__udivmoddi4+0xa0>
800056c: 4607 mov r7, r0
800056e: e6e7 b.n 8000340 <__udivmoddi4+0x60>
8000570: 4618 mov r0, r3
8000572: e6fb b.n 800036c <__udivmoddi4+0x8c>
8000574: 4541 cmp r1, r8
8000576: d2ab bcs.n 80004d0 <__udivmoddi4+0x1f0>
8000578: ebb8 0a02 subs.w sl, r8, r2
800057c: eb69 020e sbc.w r2, r9, lr
8000580: 3801 subs r0, #1
8000582: 4613 mov r3, r2
8000584: e7a4 b.n 80004d0 <__udivmoddi4+0x1f0>
8000586: 4660 mov r0, ip
8000588: e7e9 b.n 800055e <__udivmoddi4+0x27e>
800058a: 4618 mov r0, r3
800058c: e795 b.n 80004ba <__udivmoddi4+0x1da>
800058e: 4667 mov r7, ip
8000590: e7d1 b.n 8000536 <__udivmoddi4+0x256>
8000592: 4681 mov r9, r0
8000594: e77c b.n 8000490 <__udivmoddi4+0x1b0>
8000596: 3802 subs r0, #2
8000598: 442c add r4, r5
800059a: e747 b.n 800042c <__udivmoddi4+0x14c>
800059c: f1ac 0c02 sub.w ip, ip, #2
80005a0: 442b add r3, r5
80005a2: e72f b.n 8000404 <__udivmoddi4+0x124>
80005a4: 4638 mov r0, r7
80005a6: e708 b.n 80003ba <__udivmoddi4+0xda>
80005a8: 4637 mov r7, r6
80005aa: e6e9 b.n 8000380 <__udivmoddi4+0xa0>
080005ac <__aeabi_idiv0>:
80005ac: 4770 bx lr
80005ae: bf00 nop
080005b0 <vApplicationIdleHook>:
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
void vApplicationMallocFailedHook(void);
/* USER CODE BEGIN 2 */
__weak void vApplicationIdleHook( void )
{
80005b0: b480 push {r7}
80005b2: af00 add r7, sp, #0
specified, or call vTaskDelay()). If the application makes use of the
vTaskDelete() API function (as this demo application does) then it is also
important that vApplicationIdleHook() is permitted to return to its calling
function, because it is the responsibility of the idle task to clean up
memory allocated by the kernel to any task that has since been deleted. */
}
80005b4: bf00 nop
80005b6: 46bd mov sp, r7
80005b8: f85d 7b04 ldr.w r7, [sp], #4
80005bc: 4770 bx lr
080005be <vApplicationStackOverflowHook>:
/* USER CODE END 2 */
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
80005be: b480 push {r7}
80005c0: b083 sub sp, #12
80005c2: af00 add r7, sp, #0
80005c4: 6078 str r0, [r7, #4]
80005c6: 6039 str r1, [r7, #0]
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
80005c8: bf00 nop
80005ca: 370c adds r7, #12
80005cc: 46bd mov sp, r7
80005ce: f85d 7b04 ldr.w r7, [sp], #4
80005d2: 4770 bx lr
080005d4 <vApplicationMallocFailedHook>:
/* USER CODE END 4 */
/* USER CODE BEGIN 5 */
__weak void vApplicationMallocFailedHook(void)
{
80005d4: b480 push {r7}
80005d6: af00 add r7, sp, #0
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
}
80005d8: bf00 nop
80005da: 46bd mov sp, r7
80005dc: f85d 7b04 ldr.w r7, [sp], #4
80005e0: 4770 bx lr
...
080005e4 <vApplicationGetIdleTaskMemory>:
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
static StaticTask_t xIdleTaskTCBBuffer;
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
{
80005e4: b480 push {r7}
80005e6: b085 sub sp, #20
80005e8: af00 add r7, sp, #0
80005ea: 60f8 str r0, [r7, #12]
80005ec: 60b9 str r1, [r7, #8]
80005ee: 607a str r2, [r7, #4]
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
80005f0: 68fb ldr r3, [r7, #12]
80005f2: 4a07 ldr r2, [pc, #28] ; (8000610 <vApplicationGetIdleTaskMemory+0x2c>)
80005f4: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &xIdleStack[0];
80005f6: 68bb ldr r3, [r7, #8]
80005f8: 4a06 ldr r2, [pc, #24] ; (8000614 <vApplicationGetIdleTaskMemory+0x30>)
80005fa: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
80005fc: 687b ldr r3, [r7, #4]
80005fe: 2280 movs r2, #128 ; 0x80
8000600: 601a str r2, [r3, #0]
/* place for user code */
}
8000602: bf00 nop
8000604: 3714 adds r7, #20
8000606: 46bd mov sp, r7
8000608: f85d 7b04 ldr.w r7, [sp], #4
800060c: 4770 bx lr
800060e: bf00 nop
8000610: 20000104 .word 0x20000104
8000614: 2000015c .word 0x2000015c
08000618 <ft5336_Init>:
* from MCU to FT5336 : ie I2C channel initialization (if required).
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Init(uint16_t DeviceAddr)
{
8000618: b580 push {r7, lr}
800061a: b082 sub sp, #8
800061c: af00 add r7, sp, #0
800061e: 4603 mov r3, r0
8000620: 80fb strh r3, [r7, #6]
/* Wait at least 200ms after power up before accessing registers
* Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */
TS_IO_Delay(200);
8000622: 20c8 movs r0, #200 ; 0xc8
8000624: f002 f99e bl 8002964 <TS_IO_Delay>
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000628: f000 fa7a bl 8000b20 <ft5336_I2C_InitializeIfRequired>
}
800062c: bf00 nop
800062e: 3708 adds r7, #8
8000630: 46bd mov sp, r7
8000632: bd80 pop {r7, pc}
08000634 <ft5336_Reset>:
* @note : Not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Reset(uint16_t DeviceAddr)
{
8000634: b480 push {r7}
8000636: b083 sub sp, #12
8000638: af00 add r7, sp, #0
800063a: 4603 mov r3, r0
800063c: 80fb strh r3, [r7, #6]
/* Do nothing */
/* No software reset sequence available in FT5336 IC */
}
800063e: bf00 nop
8000640: 370c adds r7, #12
8000642: 46bd mov sp, r7
8000644: f85d 7b04 ldr.w r7, [sp], #4
8000648: 4770 bx lr
0800064a <ft5336_ReadID>:
* able to read the FT5336 device ID, and verify this is a FT5336.
* @param DeviceAddr: I2C FT5336 Slave address.
* @retval The Device ID (two bytes).
*/
uint16_t ft5336_ReadID(uint16_t DeviceAddr)
{
800064a: b580 push {r7, lr}
800064c: b084 sub sp, #16
800064e: af00 add r7, sp, #0
8000650: 4603 mov r3, r0
8000652: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadId = 0;
8000654: 2300 movs r3, #0
8000656: 737b strb r3, [r7, #13]
uint8_t nbReadAttempts = 0;
8000658: 2300 movs r3, #0
800065a: 73fb strb r3, [r7, #15]
uint8_t bFoundDevice = 0; /* Device not found by default */
800065c: 2300 movs r3, #0
800065e: 73bb strb r3, [r7, #14]
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
8000660: f000 fa5e bl 8000b20 <ft5336_I2C_InitializeIfRequired>
/* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000664: 2300 movs r3, #0
8000666: 73fb strb r3, [r7, #15]
8000668: e010 b.n 800068c <ft5336_ReadID+0x42>
{
/* Read register FT5336_CHIP_ID_REG as DeviceID detection */
ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG);
800066a: 88fb ldrh r3, [r7, #6]
800066c: b2db uxtb r3, r3
800066e: 21a8 movs r1, #168 ; 0xa8
8000670: 4618 mov r0, r3
8000672: f002 f959 bl 8002928 <TS_IO_Read>
8000676: 4603 mov r3, r0
8000678: 737b strb r3, [r7, #13]
/* Found the searched device ID ? */
if(ucReadId == FT5336_ID_VALUE)
800067a: 7b7b ldrb r3, [r7, #13]
800067c: b2db uxtb r3, r3
800067e: 2b51 cmp r3, #81 ; 0x51
8000680: d101 bne.n 8000686 <ft5336_ReadID+0x3c>
{
/* Set device as found */
bFoundDevice = 1;
8000682: 2301 movs r3, #1
8000684: 73bb strb r3, [r7, #14]
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000686: 7bfb ldrb r3, [r7, #15]
8000688: 3301 adds r3, #1
800068a: 73fb strb r3, [r7, #15]
800068c: 7bfb ldrb r3, [r7, #15]
800068e: 2b02 cmp r3, #2
8000690: d802 bhi.n 8000698 <ft5336_ReadID+0x4e>
8000692: 7bbb ldrb r3, [r7, #14]
8000694: 2b00 cmp r3, #0
8000696: d0e8 beq.n 800066a <ft5336_ReadID+0x20>
}
}
/* Return the device ID value */
return (ucReadId);
8000698: 7b7b ldrb r3, [r7, #13]
800069a: b2db uxtb r3, r3
800069c: b29b uxth r3, r3
}
800069e: 4618 mov r0, r3
80006a0: 3710 adds r7, #16
80006a2: 46bd mov sp, r7
80006a4: bd80 pop {r7, pc}
080006a6 <ft5336_TS_Start>:
* @brief Configures the touch Screen IC device to start detecting touches
* @param DeviceAddr: Device address on communication Bus (I2C slave address).
* @retval None.
*/
void ft5336_TS_Start(uint16_t DeviceAddr)
{
80006a6: b580 push {r7, lr}
80006a8: b082 sub sp, #8
80006aa: af00 add r7, sp, #0
80006ac: 4603 mov r3, r0
80006ae: 80fb strh r3, [r7, #6]
/* Minimum static configuration of FT5336 */
FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr));
80006b0: 88fb ldrh r3, [r7, #6]
80006b2: 4618 mov r0, r3
80006b4: f000 fa44 bl 8000b40 <ft5336_TS_Configure>
/* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */
/* Note TS_INT is active low */
ft5336_TS_DisableIT(DeviceAddr);
80006b8: 88fb ldrh r3, [r7, #6]
80006ba: 4618 mov r0, r3
80006bc: f000 f932 bl 8000924 <ft5336_TS_DisableIT>
}
80006c0: bf00 nop
80006c2: 3708 adds r7, #8
80006c4: 46bd mov sp, r7
80006c6: bd80 pop {r7, pc}
080006c8 <ft5336_TS_DetectTouch>:
* variables).
* @param DeviceAddr: Device address on communication Bus.
* @retval : Number of active touches detected (can be 0, 1 or 2).
*/
uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr)
{
80006c8: b580 push {r7, lr}
80006ca: b084 sub sp, #16
80006cc: af00 add r7, sp, #0
80006ce: 4603 mov r3, r0
80006d0: 80fb strh r3, [r7, #6]
volatile uint8_t nbTouch = 0;
80006d2: 2300 movs r3, #0
80006d4: 73fb strb r3, [r7, #15]
/* Read register FT5336_TD_STAT_REG to check number of touches detection */
nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG);
80006d6: 88fb ldrh r3, [r7, #6]
80006d8: b2db uxtb r3, r3
80006da: 2102 movs r1, #2
80006dc: 4618 mov r0, r3
80006de: f002 f923 bl 8002928 <TS_IO_Read>
80006e2: 4603 mov r3, r0
80006e4: 73fb strb r3, [r7, #15]
nbTouch &= FT5336_TD_STAT_MASK;
80006e6: 7bfb ldrb r3, [r7, #15]
80006e8: b2db uxtb r3, r3
80006ea: f003 030f and.w r3, r3, #15
80006ee: b2db uxtb r3, r3
80006f0: 73fb strb r3, [r7, #15]
if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH)
80006f2: 7bfb ldrb r3, [r7, #15]
80006f4: b2db uxtb r3, r3
80006f6: 2b05 cmp r3, #5
80006f8: d901 bls.n 80006fe <ft5336_TS_DetectTouch+0x36>
{
/* If invalid number of touch detected, set it to zero */
nbTouch = 0;
80006fa: 2300 movs r3, #0
80006fc: 73fb strb r3, [r7, #15]
}
/* Update ft5336 driver internal global : current number of active touches */
ft5336_handle.currActiveTouchNb = nbTouch;
80006fe: 7bfb ldrb r3, [r7, #15]
8000700: b2da uxtb r2, r3
8000702: 4b05 ldr r3, [pc, #20] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
8000704: 705a strb r2, [r3, #1]
/* Reset current active touch index on which to work on */
ft5336_handle.currActiveTouchIdx = 0;
8000706: 4b04 ldr r3, [pc, #16] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
8000708: 2200 movs r2, #0
800070a: 709a strb r2, [r3, #2]
return(nbTouch);
800070c: 7bfb ldrb r3, [r7, #15]
800070e: b2db uxtb r3, r3
}
8000710: 4618 mov r0, r3
8000712: 3710 adds r7, #16
8000714: 46bd mov sp, r7
8000716: bd80 pop {r7, pc}
8000718: 2000035c .word 0x2000035c
0800071c <ft5336_TS_GetXY>:
* @param X: Pointer to X position value
* @param Y: Pointer to Y position value
* @retval None.
*/
void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
{
800071c: b580 push {r7, lr}
800071e: b086 sub sp, #24
8000720: af00 add r7, sp, #0
8000722: 4603 mov r3, r0
8000724: 60b9 str r1, [r7, #8]
8000726: 607a str r2, [r7, #4]
8000728: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
800072a: 2300 movs r3, #0
800072c: 74fb strb r3, [r7, #19]
static uint16_t coord;
uint8_t regAddressXLow = 0;
800072e: 2300 movs r3, #0
8000730: 75fb strb r3, [r7, #23]
uint8_t regAddressXHigh = 0;
8000732: 2300 movs r3, #0
8000734: 75bb strb r3, [r7, #22]
uint8_t regAddressYLow = 0;
8000736: 2300 movs r3, #0
8000738: 757b strb r3, [r7, #21]
uint8_t regAddressYHigh = 0;
800073a: 2300 movs r3, #0
800073c: 753b strb r3, [r7, #20]
if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb)
800073e: 4b6d ldr r3, [pc, #436] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
8000740: 789a ldrb r2, [r3, #2]
8000742: 4b6c ldr r3, [pc, #432] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
8000744: 785b ldrb r3, [r3, #1]
8000746: 429a cmp r2, r3
8000748: f080 80cf bcs.w 80008ea <ft5336_TS_GetXY+0x1ce>
{
switch(ft5336_handle.currActiveTouchIdx)
800074c: 4b69 ldr r3, [pc, #420] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
800074e: 789b ldrb r3, [r3, #2]
8000750: 2b09 cmp r3, #9
8000752: d871 bhi.n 8000838 <ft5336_TS_GetXY+0x11c>
8000754: a201 add r2, pc, #4 ; (adr r2, 800075c <ft5336_TS_GetXY+0x40>)
8000756: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800075a: bf00 nop
800075c: 08000785 .word 0x08000785
8000760: 08000797 .word 0x08000797
8000764: 080007a9 .word 0x080007a9
8000768: 080007bb .word 0x080007bb
800076c: 080007cd .word 0x080007cd
8000770: 080007df .word 0x080007df
8000774: 080007f1 .word 0x080007f1
8000778: 08000803 .word 0x08000803
800077c: 08000815 .word 0x08000815
8000780: 08000827 .word 0x08000827
{
case 0 :
regAddressXLow = FT5336_P1_XL_REG;
8000784: 2304 movs r3, #4
8000786: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P1_XH_REG;
8000788: 2303 movs r3, #3
800078a: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P1_YL_REG;
800078c: 2306 movs r3, #6
800078e: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P1_YH_REG;
8000790: 2305 movs r3, #5
8000792: 753b strb r3, [r7, #20]
break;
8000794: e051 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 1 :
regAddressXLow = FT5336_P2_XL_REG;
8000796: 230a movs r3, #10
8000798: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P2_XH_REG;
800079a: 2309 movs r3, #9
800079c: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P2_YL_REG;
800079e: 230c movs r3, #12
80007a0: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P2_YH_REG;
80007a2: 230b movs r3, #11
80007a4: 753b strb r3, [r7, #20]
break;
80007a6: e048 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 2 :
regAddressXLow = FT5336_P3_XL_REG;
80007a8: 2310 movs r3, #16
80007aa: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P3_XH_REG;
80007ac: 230f movs r3, #15
80007ae: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P3_YL_REG;
80007b0: 2312 movs r3, #18
80007b2: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P3_YH_REG;
80007b4: 2311 movs r3, #17
80007b6: 753b strb r3, [r7, #20]
break;
80007b8: e03f b.n 800083a <ft5336_TS_GetXY+0x11e>
case 3 :
regAddressXLow = FT5336_P4_XL_REG;
80007ba: 2316 movs r3, #22
80007bc: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P4_XH_REG;
80007be: 2315 movs r3, #21
80007c0: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P4_YL_REG;
80007c2: 2318 movs r3, #24
80007c4: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P4_YH_REG;
80007c6: 2317 movs r3, #23
80007c8: 753b strb r3, [r7, #20]
break;
80007ca: e036 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 4 :
regAddressXLow = FT5336_P5_XL_REG;
80007cc: 231c movs r3, #28
80007ce: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P5_XH_REG;
80007d0: 231b movs r3, #27
80007d2: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P5_YL_REG;
80007d4: 231e movs r3, #30
80007d6: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P5_YH_REG;
80007d8: 231d movs r3, #29
80007da: 753b strb r3, [r7, #20]
break;
80007dc: e02d b.n 800083a <ft5336_TS_GetXY+0x11e>
case 5 :
regAddressXLow = FT5336_P6_XL_REG;
80007de: 2322 movs r3, #34 ; 0x22
80007e0: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P6_XH_REG;
80007e2: 2321 movs r3, #33 ; 0x21
80007e4: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P6_YL_REG;
80007e6: 2324 movs r3, #36 ; 0x24
80007e8: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P6_YH_REG;
80007ea: 2323 movs r3, #35 ; 0x23
80007ec: 753b strb r3, [r7, #20]
break;
80007ee: e024 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 6 :
regAddressXLow = FT5336_P7_XL_REG;
80007f0: 2328 movs r3, #40 ; 0x28
80007f2: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P7_XH_REG;
80007f4: 2327 movs r3, #39 ; 0x27
80007f6: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P7_YL_REG;
80007f8: 232a movs r3, #42 ; 0x2a
80007fa: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P7_YH_REG;
80007fc: 2329 movs r3, #41 ; 0x29
80007fe: 753b strb r3, [r7, #20]
break;
8000800: e01b b.n 800083a <ft5336_TS_GetXY+0x11e>
case 7 :
regAddressXLow = FT5336_P8_XL_REG;
8000802: 232e movs r3, #46 ; 0x2e
8000804: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P8_XH_REG;
8000806: 232d movs r3, #45 ; 0x2d
8000808: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P8_YL_REG;
800080a: 2330 movs r3, #48 ; 0x30
800080c: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P8_YH_REG;
800080e: 232f movs r3, #47 ; 0x2f
8000810: 753b strb r3, [r7, #20]
break;
8000812: e012 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 8 :
regAddressXLow = FT5336_P9_XL_REG;
8000814: 2334 movs r3, #52 ; 0x34
8000816: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P9_XH_REG;
8000818: 2333 movs r3, #51 ; 0x33
800081a: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P9_YL_REG;
800081c: 2336 movs r3, #54 ; 0x36
800081e: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P9_YH_REG;
8000820: 2335 movs r3, #53 ; 0x35
8000822: 753b strb r3, [r7, #20]
break;
8000824: e009 b.n 800083a <ft5336_TS_GetXY+0x11e>
case 9 :
regAddressXLow = FT5336_P10_XL_REG;
8000826: 233a movs r3, #58 ; 0x3a
8000828: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P10_XH_REG;
800082a: 2339 movs r3, #57 ; 0x39
800082c: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P10_YL_REG;
800082e: 233c movs r3, #60 ; 0x3c
8000830: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P10_YH_REG;
8000832: 233b movs r3, #59 ; 0x3b
8000834: 753b strb r3, [r7, #20]
break;
8000836: e000 b.n 800083a <ft5336_TS_GetXY+0x11e>
default :
break;
8000838: bf00 nop
} /* end switch(ft5336_handle.currActiveTouchIdx) */
/* Read low part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow);
800083a: 89fb ldrh r3, [r7, #14]
800083c: b2db uxtb r3, r3
800083e: 7dfa ldrb r2, [r7, #23]
8000840: 4611 mov r1, r2
8000842: 4618 mov r0, r3
8000844: f002 f870 bl 8002928 <TS_IO_Read>
8000848: 4603 mov r3, r0
800084a: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
800084c: 7cfb ldrb r3, [r7, #19]
800084e: b2db uxtb r3, r3
8000850: b29a uxth r2, r3
8000852: 4b29 ldr r3, [pc, #164] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000854: 801a strh r2, [r3, #0]
/* Read high part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000856: 89fb ldrh r3, [r7, #14]
8000858: b2db uxtb r3, r3
800085a: 7dba ldrb r2, [r7, #22]
800085c: 4611 mov r1, r2
800085e: 4618 mov r0, r3
8000860: f002 f862 bl 8002928 <TS_IO_Read>
8000864: 4603 mov r3, r0
8000866: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
8000868: 7cfb ldrb r3, [r7, #19]
800086a: b2db uxtb r3, r3
800086c: 021b lsls r3, r3, #8
800086e: f403 6370 and.w r3, r3, #3840 ; 0xf00
8000872: b21a sxth r2, r3
8000874: 4b20 ldr r3, [pc, #128] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000876: 881b ldrh r3, [r3, #0]
8000878: b21b sxth r3, r3
800087a: 4313 orrs r3, r2
800087c: b21b sxth r3, r3
800087e: b29a uxth r2, r3
8000880: 4b1d ldr r3, [pc, #116] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000882: 801a strh r2, [r3, #0]
/* Send back ready X position to caller */
*X = coord;
8000884: 4b1c ldr r3, [pc, #112] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
8000886: 881a ldrh r2, [r3, #0]
8000888: 68bb ldr r3, [r7, #8]
800088a: 801a strh r2, [r3, #0]
/* Read low part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow);
800088c: 89fb ldrh r3, [r7, #14]
800088e: b2db uxtb r3, r3
8000890: 7d7a ldrb r2, [r7, #21]
8000892: 4611 mov r1, r2
8000894: 4618 mov r0, r3
8000896: f002 f847 bl 8002928 <TS_IO_Read>
800089a: 4603 mov r3, r0
800089c: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
800089e: 7cfb ldrb r3, [r7, #19]
80008a0: b2db uxtb r3, r3
80008a2: b29a uxth r2, r3
80008a4: 4b14 ldr r3, [pc, #80] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008a6: 801a strh r2, [r3, #0]
/* Read high part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh);
80008a8: 89fb ldrh r3, [r7, #14]
80008aa: b2db uxtb r3, r3
80008ac: 7d3a ldrb r2, [r7, #20]
80008ae: 4611 mov r1, r2
80008b0: 4618 mov r0, r3
80008b2: f002 f839 bl 8002928 <TS_IO_Read>
80008b6: 4603 mov r3, r0
80008b8: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
80008ba: 7cfb ldrb r3, [r7, #19]
80008bc: b2db uxtb r3, r3
80008be: 021b lsls r3, r3, #8
80008c0: f403 6370 and.w r3, r3, #3840 ; 0xf00
80008c4: b21a sxth r2, r3
80008c6: 4b0c ldr r3, [pc, #48] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008c8: 881b ldrh r3, [r3, #0]
80008ca: b21b sxth r3, r3
80008cc: 4313 orrs r3, r2
80008ce: b21b sxth r3, r3
80008d0: b29a uxth r2, r3
80008d2: 4b09 ldr r3, [pc, #36] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008d4: 801a strh r2, [r3, #0]
/* Send back ready Y position to caller */
*Y = coord;
80008d6: 4b08 ldr r3, [pc, #32] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
80008d8: 881a ldrh r2, [r3, #0]
80008da: 687b ldr r3, [r7, #4]
80008dc: 801a strh r2, [r3, #0]
ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */
80008de: 4b05 ldr r3, [pc, #20] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
80008e0: 789b ldrb r3, [r3, #2]
80008e2: 3301 adds r3, #1
80008e4: b2da uxtb r2, r3
80008e6: 4b03 ldr r3, [pc, #12] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
80008e8: 709a strb r2, [r3, #2]
} /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */
}
80008ea: bf00 nop
80008ec: 3718 adds r7, #24
80008ee: 46bd mov sp, r7
80008f0: bd80 pop {r7, pc}
80008f2: bf00 nop
80008f4: 2000035c .word 0x2000035c
80008f8: 20000360 .word 0x20000360
080008fc <ft5336_TS_EnableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_EnableIT(uint16_t DeviceAddr)
{
80008fc: b580 push {r7, lr}
80008fe: b084 sub sp, #16
8000900: af00 add r7, sp, #0
8000902: 4603 mov r3, r0
8000904: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
8000906: 2300 movs r3, #0
8000908: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
800090a: 2301 movs r3, #1
800090c: 73fb strb r3, [r7, #15]
/* Set interrupt trigger mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
800090e: 88fb ldrh r3, [r7, #6]
8000910: b2db uxtb r3, r3
8000912: 7bfa ldrb r2, [r7, #15]
8000914: 21a4 movs r1, #164 ; 0xa4
8000916: 4618 mov r0, r3
8000918: f001 ffec bl 80028f4 <TS_IO_Write>
}
800091c: bf00 nop
800091e: 3710 adds r7, #16
8000920: 46bd mov sp, r7
8000922: bd80 pop {r7, pc}
08000924 <ft5336_TS_DisableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_DisableIT(uint16_t DeviceAddr)
{
8000924: b580 push {r7, lr}
8000926: b084 sub sp, #16
8000928: af00 add r7, sp, #0
800092a: 4603 mov r3, r0
800092c: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
800092e: 2300 movs r3, #0
8000930: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
8000932: 2300 movs r3, #0
8000934: 73fb strb r3, [r7, #15]
/* Set interrupt polling mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
8000936: 88fb ldrh r3, [r7, #6]
8000938: b2db uxtb r3, r3
800093a: 7bfa ldrb r2, [r7, #15]
800093c: 21a4 movs r1, #164 ; 0xa4
800093e: 4618 mov r0, r3
8000940: f001 ffd8 bl 80028f4 <TS_IO_Write>
}
8000944: bf00 nop
8000946: 3710 adds r7, #16
8000948: 46bd mov sp, r7
800094a: bd80 pop {r7, pc}
0800094c <ft5336_TS_ITStatus>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval TS interrupts status : always return 0 here
*/
uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr)
{
800094c: b480 push {r7}
800094e: b083 sub sp, #12
8000950: af00 add r7, sp, #0
8000952: 4603 mov r3, r0
8000954: 80fb strh r3, [r7, #6]
/* Always return 0 as feature not applicable to FT5336 */
return 0;
8000956: 2300 movs r3, #0
}
8000958: 4618 mov r0, r3
800095a: 370c adds r7, #12
800095c: 46bd mov sp, r7
800095e: f85d 7b04 ldr.w r7, [sp], #4
8000962: 4770 bx lr
08000964 <ft5336_TS_ClearIT>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_TS_ClearIT(uint16_t DeviceAddr)
{
8000964: b480 push {r7}
8000966: b083 sub sp, #12
8000968: af00 add r7, sp, #0
800096a: 4603 mov r3, r0
800096c: 80fb strh r3, [r7, #6]
/* Nothing to be done here for FT5336 */
}
800096e: bf00 nop
8000970: 370c adds r7, #12
8000972: 46bd mov sp, r7
8000974: f85d 7b04 ldr.w r7, [sp], #4
8000978: 4770 bx lr
0800097a <ft5336_TS_GetGestureID>:
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @param pGestureId : Pointer to get last touch gesture Identification.
* @retval None.
*/
void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
{
800097a: b580 push {r7, lr}
800097c: b084 sub sp, #16
800097e: af00 add r7, sp, #0
8000980: 4603 mov r3, r0
8000982: 6039 str r1, [r7, #0]
8000984: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadData = 0;
8000986: 2300 movs r3, #0
8000988: 73fb strb r3, [r7, #15]
ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG);
800098a: 88fb ldrh r3, [r7, #6]
800098c: b2db uxtb r3, r3
800098e: 2101 movs r1, #1
8000990: 4618 mov r0, r3
8000992: f001 ffc9 bl 8002928 <TS_IO_Read>
8000996: 4603 mov r3, r0
8000998: 73fb strb r3, [r7, #15]
* pGestureId = ucReadData;
800099a: 7bfb ldrb r3, [r7, #15]
800099c: b2db uxtb r3, r3
800099e: 461a mov r2, r3
80009a0: 683b ldr r3, [r7, #0]
80009a2: 601a str r2, [r3, #0]
}
80009a4: bf00 nop
80009a6: 3710 adds r7, #16
80009a8: 46bd mov sp, r7
80009aa: bd80 pop {r7, pc}
080009ac <ft5336_TS_GetTouchInfo>:
void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr,
uint32_t touchIdx,
uint32_t * pWeight,
uint32_t * pArea,
uint32_t * pEvent)
{
80009ac: b580 push {r7, lr}
80009ae: b086 sub sp, #24
80009b0: af00 add r7, sp, #0
80009b2: 60b9 str r1, [r7, #8]
80009b4: 607a str r2, [r7, #4]
80009b6: 603b str r3, [r7, #0]
80009b8: 4603 mov r3, r0
80009ba: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
80009bc: 2300 movs r3, #0
80009be: 753b strb r3, [r7, #20]
uint8_t regAddressXHigh = 0;
80009c0: 2300 movs r3, #0
80009c2: 75fb strb r3, [r7, #23]
uint8_t regAddressPWeight = 0;
80009c4: 2300 movs r3, #0
80009c6: 75bb strb r3, [r7, #22]
uint8_t regAddressPMisc = 0;
80009c8: 2300 movs r3, #0
80009ca: 757b strb r3, [r7, #21]
if(touchIdx < ft5336_handle.currActiveTouchNb)
80009cc: 4b4d ldr r3, [pc, #308] ; (8000b04 <ft5336_TS_GetTouchInfo+0x158>)
80009ce: 785b ldrb r3, [r3, #1]
80009d0: 461a mov r2, r3
80009d2: 68bb ldr r3, [r7, #8]
80009d4: 4293 cmp r3, r2
80009d6: f080 8090 bcs.w 8000afa <ft5336_TS_GetTouchInfo+0x14e>
{
switch(touchIdx)
80009da: 68bb ldr r3, [r7, #8]
80009dc: 2b09 cmp r3, #9
80009de: d85d bhi.n 8000a9c <ft5336_TS_GetTouchInfo+0xf0>
80009e0: a201 add r2, pc, #4 ; (adr r2, 80009e8 <ft5336_TS_GetTouchInfo+0x3c>)
80009e2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80009e6: bf00 nop
80009e8: 08000a11 .word 0x08000a11
80009ec: 08000a1f .word 0x08000a1f
80009f0: 08000a2d .word 0x08000a2d
80009f4: 08000a3b .word 0x08000a3b
80009f8: 08000a49 .word 0x08000a49
80009fc: 08000a57 .word 0x08000a57
8000a00: 08000a65 .word 0x08000a65
8000a04: 08000a73 .word 0x08000a73
8000a08: 08000a81 .word 0x08000a81
8000a0c: 08000a8f .word 0x08000a8f
{
case 0 :
regAddressXHigh = FT5336_P1_XH_REG;
8000a10: 2303 movs r3, #3
8000a12: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P1_WEIGHT_REG;
8000a14: 2307 movs r3, #7
8000a16: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P1_MISC_REG;
8000a18: 2308 movs r3, #8
8000a1a: 757b strb r3, [r7, #21]
break;
8000a1c: e03f b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 1 :
regAddressXHigh = FT5336_P2_XH_REG;
8000a1e: 2309 movs r3, #9
8000a20: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P2_WEIGHT_REG;
8000a22: 230d movs r3, #13
8000a24: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P2_MISC_REG;
8000a26: 230e movs r3, #14
8000a28: 757b strb r3, [r7, #21]
break;
8000a2a: e038 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 2 :
regAddressXHigh = FT5336_P3_XH_REG;
8000a2c: 230f movs r3, #15
8000a2e: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P3_WEIGHT_REG;
8000a30: 2313 movs r3, #19
8000a32: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P3_MISC_REG;
8000a34: 2314 movs r3, #20
8000a36: 757b strb r3, [r7, #21]
break;
8000a38: e031 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 3 :
regAddressXHigh = FT5336_P4_XH_REG;
8000a3a: 2315 movs r3, #21
8000a3c: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P4_WEIGHT_REG;
8000a3e: 2319 movs r3, #25
8000a40: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P4_MISC_REG;
8000a42: 231a movs r3, #26
8000a44: 757b strb r3, [r7, #21]
break;
8000a46: e02a b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 4 :
regAddressXHigh = FT5336_P5_XH_REG;
8000a48: 231b movs r3, #27
8000a4a: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P5_WEIGHT_REG;
8000a4c: 231f movs r3, #31
8000a4e: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P5_MISC_REG;
8000a50: 2320 movs r3, #32
8000a52: 757b strb r3, [r7, #21]
break;
8000a54: e023 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 5 :
regAddressXHigh = FT5336_P6_XH_REG;
8000a56: 2321 movs r3, #33 ; 0x21
8000a58: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P6_WEIGHT_REG;
8000a5a: 2325 movs r3, #37 ; 0x25
8000a5c: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P6_MISC_REG;
8000a5e: 2326 movs r3, #38 ; 0x26
8000a60: 757b strb r3, [r7, #21]
break;
8000a62: e01c b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 6 :
regAddressXHigh = FT5336_P7_XH_REG;
8000a64: 2327 movs r3, #39 ; 0x27
8000a66: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P7_WEIGHT_REG;
8000a68: 232b movs r3, #43 ; 0x2b
8000a6a: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P7_MISC_REG;
8000a6c: 232c movs r3, #44 ; 0x2c
8000a6e: 757b strb r3, [r7, #21]
break;
8000a70: e015 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 7 :
regAddressXHigh = FT5336_P8_XH_REG;
8000a72: 232d movs r3, #45 ; 0x2d
8000a74: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P8_WEIGHT_REG;
8000a76: 2331 movs r3, #49 ; 0x31
8000a78: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P8_MISC_REG;
8000a7a: 2332 movs r3, #50 ; 0x32
8000a7c: 757b strb r3, [r7, #21]
break;
8000a7e: e00e b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 8 :
regAddressXHigh = FT5336_P9_XH_REG;
8000a80: 2333 movs r3, #51 ; 0x33
8000a82: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P9_WEIGHT_REG;
8000a84: 2337 movs r3, #55 ; 0x37
8000a86: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P9_MISC_REG;
8000a88: 2338 movs r3, #56 ; 0x38
8000a8a: 757b strb r3, [r7, #21]
break;
8000a8c: e007 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
case 9 :
regAddressXHigh = FT5336_P10_XH_REG;
8000a8e: 2339 movs r3, #57 ; 0x39
8000a90: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P10_WEIGHT_REG;
8000a92: 233d movs r3, #61 ; 0x3d
8000a94: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P10_MISC_REG;
8000a96: 233e movs r3, #62 ; 0x3e
8000a98: 757b strb r3, [r7, #21]
break;
8000a9a: e000 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
default :
break;
8000a9c: bf00 nop
} /* end switch(touchIdx) */
/* Read Event Id of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000a9e: 89fb ldrh r3, [r7, #14]
8000aa0: b2db uxtb r3, r3
8000aa2: 7dfa ldrb r2, [r7, #23]
8000aa4: 4611 mov r1, r2
8000aa6: 4618 mov r0, r3
8000aa8: f001 ff3e bl 8002928 <TS_IO_Read>
8000aac: 4603 mov r3, r0
8000aae: 753b strb r3, [r7, #20]
* pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT;
8000ab0: 7d3b ldrb r3, [r7, #20]
8000ab2: b2db uxtb r3, r3
8000ab4: 119b asrs r3, r3, #6
8000ab6: f003 0203 and.w r2, r3, #3
8000aba: 6a3b ldr r3, [r7, #32]
8000abc: 601a str r2, [r3, #0]
/* Read weight of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight);
8000abe: 89fb ldrh r3, [r7, #14]
8000ac0: b2db uxtb r3, r3
8000ac2: 7dba ldrb r2, [r7, #22]
8000ac4: 4611 mov r1, r2
8000ac6: 4618 mov r0, r3
8000ac8: f001 ff2e bl 8002928 <TS_IO_Read>
8000acc: 4603 mov r3, r0
8000ace: 753b strb r3, [r7, #20]
* pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT;
8000ad0: 7d3b ldrb r3, [r7, #20]
8000ad2: b2db uxtb r3, r3
8000ad4: 461a mov r2, r3
8000ad6: 687b ldr r3, [r7, #4]
8000ad8: 601a str r2, [r3, #0]
/* Read area of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc);
8000ada: 89fb ldrh r3, [r7, #14]
8000adc: b2db uxtb r3, r3
8000ade: 7d7a ldrb r2, [r7, #21]
8000ae0: 4611 mov r1, r2
8000ae2: 4618 mov r0, r3
8000ae4: f001 ff20 bl 8002928 <TS_IO_Read>
8000ae8: 4603 mov r3, r0
8000aea: 753b strb r3, [r7, #20]
* pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT;
8000aec: 7d3b ldrb r3, [r7, #20]
8000aee: b2db uxtb r3, r3
8000af0: 111b asrs r3, r3, #4
8000af2: f003 0204 and.w r2, r3, #4
8000af6: 683b ldr r3, [r7, #0]
8000af8: 601a str r2, [r3, #0]
} /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */
}
8000afa: bf00 nop
8000afc: 3718 adds r7, #24
8000afe: 46bd mov sp, r7
8000b00: bd80 pop {r7, pc}
8000b02: bf00 nop
8000b04: 2000035c .word 0x2000035c
08000b08 <ft5336_Get_I2C_InitializedStatus>:
* @brief Return the status of I2C was initialized or not.
* @param None.
* @retval : I2C initialization status.
*/
static uint8_t ft5336_Get_I2C_InitializedStatus(void)
{
8000b08: b480 push {r7}
8000b0a: af00 add r7, sp, #0
return(ft5336_handle.i2cInitialized);
8000b0c: 4b03 ldr r3, [pc, #12] ; (8000b1c <ft5336_Get_I2C_InitializedStatus+0x14>)
8000b0e: 781b ldrb r3, [r3, #0]
}
8000b10: 4618 mov r0, r3
8000b12: 46bd mov sp, r7
8000b14: f85d 7b04 ldr.w r7, [sp], #4
8000b18: 4770 bx lr
8000b1a: bf00 nop
8000b1c: 2000035c .word 0x2000035c
08000b20 <ft5336_I2C_InitializeIfRequired>:
* @brief I2C initialize if needed.
* @param None.
* @retval : None.
*/
static void ft5336_I2C_InitializeIfRequired(void)
{
8000b20: b580 push {r7, lr}
8000b22: af00 add r7, sp, #0
if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED)
8000b24: f7ff fff0 bl 8000b08 <ft5336_Get_I2C_InitializedStatus>
8000b28: 4603 mov r3, r0
8000b2a: 2b00 cmp r3, #0
8000b2c: d104 bne.n 8000b38 <ft5336_I2C_InitializeIfRequired+0x18>
{
/* Initialize TS IO BUS layer (I2C) */
TS_IO_Init();
8000b2e: f001 fed7 bl 80028e0 <TS_IO_Init>
/* Set state to initialized */
ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED;
8000b32: 4b02 ldr r3, [pc, #8] ; (8000b3c <ft5336_I2C_InitializeIfRequired+0x1c>)
8000b34: 2201 movs r2, #1
8000b36: 701a strb r2, [r3, #0]
}
}
8000b38: bf00 nop
8000b3a: bd80 pop {r7, pc}
8000b3c: 2000035c .word 0x2000035c
08000b40 <ft5336_TS_Configure>:
* @brief Basic static configuration of TouchScreen
* @param DeviceAddr: FT5336 Device address for communication on I2C Bus.
* @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK.
*/
static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr)
{
8000b40: b480 push {r7}
8000b42: b085 sub sp, #20
8000b44: af00 add r7, sp, #0
8000b46: 4603 mov r3, r0
8000b48: 80fb strh r3, [r7, #6]
uint32_t status = FT5336_STATUS_OK;
8000b4a: 2300 movs r3, #0
8000b4c: 60fb str r3, [r7, #12]
/* Nothing special to be done for FT5336 */
return(status);
8000b4e: 68fb ldr r3, [r7, #12]
}
8000b50: 4618 mov r0, r3
8000b52: 3714 adds r7, #20
8000b54: 46bd mov sp, r7
8000b56: f85d 7b04 ldr.w r7, [sp], #4
8000b5a: 4770 bx lr
08000b5c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b5c: b5b0 push {r4, r5, r7, lr}
8000b5e: b0b0 sub sp, #192 ; 0xc0
8000b60: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
static TS_StateTypeDef TS_State;
ADC_ChannelConfTypeDef sConfig = {0};
8000b62: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000b66: 2200 movs r2, #0
8000b68: 601a str r2, [r3, #0]
8000b6a: 605a str r2, [r3, #4]
8000b6c: 609a str r2, [r3, #8]
8000b6e: 60da str r2, [r3, #12]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000b70: 2301 movs r3, #1
8000b72: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000b76: 2300 movs r3, #0
8000b78: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b7c: f003 feef bl 800495e <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b80: f000 f938 bl 8000df4 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b84: f000 fe46 bl 8001814 <MX_GPIO_Init>
MX_ADC3_Init();
8000b88: f000 fa2a bl 8000fe0 <MX_ADC3_Init>
MX_LTDC_Init();
8000b8c: f000 faf8 bl 8001180 <MX_LTDC_Init>
MX_SPI2_Init();
8000b90: f000 fb8c bl 80012ac <MX_SPI2_Init>
MX_TIM1_Init();
8000b94: f000 fbc8 bl 8001328 <MX_TIM1_Init>
MX_TIM2_Init();
8000b98: f000 fc1a bl 80013d0 <MX_TIM2_Init>
MX_TIM3_Init();
8000b9c: f000 fc66 bl 800146c <MX_TIM3_Init>
MX_TIM5_Init();
8000ba0: f000 fcf2 bl 8001588 <MX_TIM5_Init>
MX_TIM8_Init();
8000ba4: f000 fd3e bl 8001624 <MX_TIM8_Init>
MX_ADC1_Init();
8000ba8: f000 f9c8 bl 8000f3c <MX_ADC1_Init>
MX_DAC_Init();
8000bac: f000 fa8c bl 80010c8 <MX_DAC_Init>
MX_FMC_Init();
8000bb0: f000 fde2 bl 8001778 <MX_FMC_Init>
MX_DMA2D_Init();
8000bb4: f000 fab2 bl 800111c <MX_DMA2D_Init>
MX_CRC_Init();
8000bb8: f000 fa64 bl 8001084 <MX_CRC_Init>
MX_RNG_Init();
8000bbc: f000 fb62 bl 8001284 <MX_RNG_Init>
/* USER CODE BEGIN 2 */
BSP_LCD_Init();
8000bc0: f001 fedc bl 800297c <BSP_LCD_Init>
BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS);
8000bc4: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000
8000bc8: 2000 movs r0, #0
8000bca: f001 ff6f bl 8002aac <BSP_LCD_LayerDefaultInit>
BSP_LCD_LayerDefaultInit(1,
LCD_FB_START_ADDRESS + BSP_LCD_GetXSize() * BSP_LCD_GetYSize() * 4);
8000bce: f001 ff45 bl 8002a5c <BSP_LCD_GetXSize>
8000bd2: 4604 mov r4, r0
8000bd4: f001 ff56 bl 8002a84 <BSP_LCD_GetYSize>
8000bd8: 4603 mov r3, r0
8000bda: fb03 f304 mul.w r3, r3, r4
BSP_LCD_LayerDefaultInit(1,
8000bde: f103 5340 add.w r3, r3, #805306368 ; 0x30000000
8000be2: 009b lsls r3, r3, #2
8000be4: 4619 mov r1, r3
8000be6: 2001 movs r0, #1
8000be8: f001 ff60 bl 8002aac <BSP_LCD_LayerDefaultInit>
BSP_LCD_DisplayOn();
8000bec: f002 fba2 bl 8003334 <BSP_LCD_DisplayOn>
BSP_LCD_SelectLayer(1);
8000bf0: 2001 movs r0, #1
8000bf2: f001 ffbb bl 8002b6c <BSP_LCD_SelectLayer>
BSP_LCD_Clear(LCD_COLOR_BLACK);
8000bf6: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000bfa: f002 f813 bl 8002c24 <BSP_LCD_Clear>
BSP_LCD_SetFont(&Font12);
8000bfe: 486a ldr r0, [pc, #424] ; (8000da8 <main+0x24c>)
8000c00: f001 fff6 bl 8002bf0 <BSP_LCD_SetFont>
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8000c04: 4869 ldr r0, [pc, #420] ; (8000dac <main+0x250>)
8000c06: f001 ffc1 bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_SetBackColor(LCD_COLOR_BLACK);
8000c0a: f04f 407f mov.w r0, #4278190080 ; 0xff000000
8000c0e: f001 ffd5 bl 8002bbc <BSP_LCD_SetBackColor>
BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
8000c12: f001 ff23 bl 8002a5c <BSP_LCD_GetXSize>
8000c16: 4603 mov r3, r0
8000c18: b29c uxth r4, r3
8000c1a: f001 ff33 bl 8002a84 <BSP_LCD_GetYSize>
8000c1e: 4603 mov r3, r0
8000c20: b29b uxth r3, r3
8000c22: 4619 mov r1, r3
8000c24: 4620 mov r0, r4
8000c26: f002 fedf bl 80039e8 <BSP_TS_Init>
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* Create the queue(s) */
/* definition and creation of Queue_J */
osMessageQDef(Queue_J, 16, uint16_t);
8000c2a: 4b61 ldr r3, [pc, #388] ; (8000db0 <main+0x254>)
8000c2c: f107 04a0 add.w r4, r7, #160 ; 0xa0
8000c30: cb0f ldmia r3, {r0, r1, r2, r3}
8000c32: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
8000c36: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000c3a: 2100 movs r1, #0
8000c3c: 4618 mov r0, r3
8000c3e: f00b f8a1 bl 800bd84 <osMessageCreate>
8000c42: 4602 mov r2, r0
8000c44: 4b5b ldr r3, [pc, #364] ; (8000db4 <main+0x258>)
8000c46: 601a str r2, [r3, #0]
/* definition and creation of Queue_N */
osMessageQDef(Queue_N, 3, struct Missile);
8000c48: 4b5b ldr r3, [pc, #364] ; (8000db8 <main+0x25c>)
8000c4a: f107 0490 add.w r4, r7, #144 ; 0x90
8000c4e: cb0f ldmia r3, {r0, r1, r2, r3}
8000c50: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_NHandle = osMessageCreate(osMessageQ(Queue_N), NULL);
8000c54: f107 0390 add.w r3, r7, #144 ; 0x90
8000c58: 2100 movs r1, #0
8000c5a: 4618 mov r0, r3
8000c5c: f00b f892 bl 800bd84 <osMessageCreate>
8000c60: 4602 mov r2, r0
8000c62: 4b56 ldr r3, [pc, #344] ; (8000dbc <main+0x260>)
8000c64: 601a str r2, [r3, #0]
/* definition and creation of Queue_F */
osMessageQDef(Queue_F, 16, uint16_t);
8000c66: 4b52 ldr r3, [pc, #328] ; (8000db0 <main+0x254>)
8000c68: f107 0480 add.w r4, r7, #128 ; 0x80
8000c6c: cb0f ldmia r3, {r0, r1, r2, r3}
8000c6e: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_FHandle = osMessageCreate(osMessageQ(Queue_F), NULL);
8000c72: f107 0380 add.w r3, r7, #128 ; 0x80
8000c76: 2100 movs r1, #0
8000c78: 4618 mov r0, r3
8000c7a: f00b f883 bl 800bd84 <osMessageCreate>
8000c7e: 4602 mov r2, r0
8000c80: 4b4f ldr r3, [pc, #316] ; (8000dc0 <main+0x264>)
8000c82: 601a str r2, [r3, #0]
/* definition and creation of Queue_E */
osMessageQDef(Queue_E, 16, uint16_t);
8000c84: 4b4a ldr r3, [pc, #296] ; (8000db0 <main+0x254>)
8000c86: f107 0470 add.w r4, r7, #112 ; 0x70
8000c8a: cb0f ldmia r3, {r0, r1, r2, r3}
8000c8c: e884 000f stmia.w r4, {r0, r1, r2, r3}
Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
8000c90: f107 0370 add.w r3, r7, #112 ; 0x70
8000c94: 2100 movs r1, #0
8000c96: 4618 mov r0, r3
8000c98: f00b f874 bl 800bd84 <osMessageCreate>
8000c9c: 4602 mov r2, r0
8000c9e: 4b49 ldr r3, [pc, #292] ; (8000dc4 <main+0x268>)
8000ca0: 601a str r2, [r3, #0]
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of GameMaster */
osThreadDef(GameMaster, f_GameMaster, osPriorityNormal, 0, 128);
8000ca2: 4b49 ldr r3, [pc, #292] ; (8000dc8 <main+0x26c>)
8000ca4: f107 0454 add.w r4, r7, #84 ; 0x54
8000ca8: 461d mov r5, r3
8000caa: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cac: c40f stmia r4!, {r0, r1, r2, r3}
8000cae: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cb2: e884 0007 stmia.w r4, {r0, r1, r2}
GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
8000cb6: f107 0354 add.w r3, r7, #84 ; 0x54
8000cba: 2100 movs r1, #0
8000cbc: 4618 mov r0, r3
8000cbe: f00a fea0 bl 800ba02 <osThreadCreate>
8000cc2: 4602 mov r2, r0
8000cc4: 4b41 ldr r3, [pc, #260] ; (8000dcc <main+0x270>)
8000cc6: 601a str r2, [r3, #0]
/* definition and creation of Joueur_1 */
osThreadDef(Joueur_1, f_Joueur_1, osPriorityNormal, 0, 128);
8000cc8: 4b41 ldr r3, [pc, #260] ; (8000dd0 <main+0x274>)
8000cca: f107 0438 add.w r4, r7, #56 ; 0x38
8000cce: 461d mov r5, r3
8000cd0: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cd2: c40f stmia r4!, {r0, r1, r2, r3}
8000cd4: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cd8: e884 0007 stmia.w r4, {r0, r1, r2}
Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
8000cdc: f107 0338 add.w r3, r7, #56 ; 0x38
8000ce0: 2100 movs r1, #0
8000ce2: 4618 mov r0, r3
8000ce4: f00a fe8d bl 800ba02 <osThreadCreate>
8000ce8: 4602 mov r2, r0
8000cea: 4b3a ldr r3, [pc, #232] ; (8000dd4 <main+0x278>)
8000cec: 601a str r2, [r3, #0]
/* definition and creation of Block_Enemie */
osThreadDef(Block_Enemie, f_block_enemie, osPriorityIdle, 0, 128);
8000cee: 4b3a ldr r3, [pc, #232] ; (8000dd8 <main+0x27c>)
8000cf0: f107 041c add.w r4, r7, #28
8000cf4: 461d mov r5, r3
8000cf6: cd0f ldmia r5!, {r0, r1, r2, r3}
8000cf8: c40f stmia r4!, {r0, r1, r2, r3}
8000cfa: e895 0007 ldmia.w r5, {r0, r1, r2}
8000cfe: e884 0007 stmia.w r4, {r0, r1, r2}
Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
8000d02: f107 031c add.w r3, r7, #28
8000d06: 2100 movs r1, #0
8000d08: 4618 mov r0, r3
8000d0a: f00a fe7a bl 800ba02 <osThreadCreate>
8000d0e: 4602 mov r2, r0
8000d10: 4b32 ldr r3, [pc, #200] ; (8000ddc <main+0x280>)
8000d12: 601a str r2, [r3, #0]
/* definition and creation of Projectile */
osThreadDef(Projectile, f_projectile, osPriorityNormal, 0, 128);
8000d14: 4b32 ldr r3, [pc, #200] ; (8000de0 <main+0x284>)
8000d16: 463c mov r4, r7
8000d18: 461d mov r5, r3
8000d1a: cd0f ldmia r5!, {r0, r1, r2, r3}
8000d1c: c40f stmia r4!, {r0, r1, r2, r3}
8000d1e: e895 0007 ldmia.w r5, {r0, r1, r2}
8000d22: e884 0007 stmia.w r4, {r0, r1, r2}
ProjectileHandle = osThreadCreate(osThread(Projectile), NULL);
8000d26: 463b mov r3, r7
8000d28: 2100 movs r1, #0
8000d2a: 4618 mov r0, r3
8000d2c: f00a fe69 bl 800ba02 <osThreadCreate>
8000d30: 4602 mov r2, r0
8000d32: 4b2c ldr r3, [pc, #176] ; (8000de4 <main+0x288>)
8000d34: 601a str r2, [r3, #0]
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* Start scheduler */
osKernelStart();
8000d36: f00a fe4d bl 800b9d4 <osKernelStart>
// BSP_LCD_DisplayStringAtLine(5, (uint8_t *)text);
;
sConfig.Channel = ADC_CHANNEL_7;
8000d3a: 2307 movs r3, #7
8000d3c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d40: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d44: 4619 mov r1, r3
8000d46: 4828 ldr r0, [pc, #160] ; (8000de8 <main+0x28c>)
8000d48: f003 ffee bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d4c: 4826 ldr r0, [pc, #152] ; (8000de8 <main+0x28c>)
8000d4e: f003 fe99 bl 8004a84 <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_6;
8000d52: 2306 movs r3, #6
8000d54: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d58: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d5c: 4619 mov r1, r3
8000d5e: 4822 ldr r0, [pc, #136] ; (8000de8 <main+0x28c>)
8000d60: f003 ffe2 bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d64: 4820 ldr r0, [pc, #128] ; (8000de8 <main+0x28c>)
8000d66: f003 fe8d bl 8004a84 <HAL_ADC_Start>
sConfig.Channel = ADC_CHANNEL_8;
8000d6a: 2308 movs r3, #8
8000d6c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000d70: f107 03b0 add.w r3, r7, #176 ; 0xb0
8000d74: 4619 mov r1, r3
8000d76: 481c ldr r0, [pc, #112] ; (8000de8 <main+0x28c>)
8000d78: f003 ffd6 bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000d7c: 481a ldr r0, [pc, #104] ; (8000de8 <main+0x28c>)
8000d7e: f003 fe81 bl 8004a84 <HAL_ADC_Start>
HAL_ADC_Start(&hadc1);
8000d82: 481a ldr r0, [pc, #104] ; (8000dec <main+0x290>)
8000d84: f003 fe7e bl 8004a84 <HAL_ADC_Start>
BSP_TS_GetState(&TS_State);
8000d88: 4819 ldr r0, [pc, #100] ; (8000df0 <main+0x294>)
8000d8a: f002 fe6d bl 8003a68 <BSP_TS_GetState>
if (TS_State.touchDetected)
8000d8e: 4b18 ldr r3, [pc, #96] ; (8000df0 <main+0x294>)
8000d90: 781b ldrb r3, [r3, #0]
8000d92: 2b00 cmp r3, #0
8000d94: d0d1 beq.n 8000d3a <main+0x1de>
{
BSP_LCD_FillCircle(TS_State.touchX[0], TS_State.touchY[0], 4);
8000d96: 4b16 ldr r3, [pc, #88] ; (8000df0 <main+0x294>)
8000d98: 8858 ldrh r0, [r3, #2]
8000d9a: 4b15 ldr r3, [pc, #84] ; (8000df0 <main+0x294>)
8000d9c: 899b ldrh r3, [r3, #12]
8000d9e: 2204 movs r2, #4
8000da0: 4619 mov r1, r3
8000da2: f002 fa27 bl 80031f4 <BSP_LCD_FillCircle>
sConfig.Channel = ADC_CHANNEL_7;
8000da6: e7c8 b.n 8000d3a <main+0x1de>
8000da8: 20000058 .word 0x20000058
8000dac: ff0000ff .word 0xff0000ff
8000db0: 0801be7c .word 0x0801be7c
8000db4: 20008920 .word 0x20008920
8000db8: 0801be8c .word 0x0801be8c
8000dbc: 20008b04 .word 0x20008b04
8000dc0: 20008b08 .word 0x20008b08
8000dc4: 20008bf8 .word 0x20008bf8
8000dc8: 0801bea8 .word 0x0801bea8
8000dcc: 20008b74 .word 0x20008b74
8000dd0: 0801bed0 .word 0x0801bed0
8000dd4: 20008948 .word 0x20008948
8000dd8: 0801befc .word 0x0801befc
8000ddc: 20008c30 .word 0x20008c30
8000de0: 0801bf24 .word 0x0801bf24
8000de4: 20008b20 .word 0x20008b20
8000de8: 20008abc .word 0x20008abc
8000dec: 20008a74 .word 0x20008a74
8000df0: 20000364 .word 0x20000364
08000df4 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000df4: b580 push {r7, lr}
8000df6: b0b4 sub sp, #208 ; 0xd0
8000df8: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000dfa: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000dfe: 2230 movs r2, #48 ; 0x30
8000e00: 2100 movs r1, #0
8000e02: 4618 mov r0, r3
8000e04: f01a f906 bl 801b014 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000e08: f107 038c add.w r3, r7, #140 ; 0x8c
8000e0c: 2200 movs r2, #0
8000e0e: 601a str r2, [r3, #0]
8000e10: 605a str r2, [r3, #4]
8000e12: 609a str r2, [r3, #8]
8000e14: 60da str r2, [r3, #12]
8000e16: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000e18: f107 0308 add.w r3, r7, #8
8000e1c: 2284 movs r2, #132 ; 0x84
8000e1e: 2100 movs r1, #0
8000e20: 4618 mov r0, r3
8000e22: f01a f8f7 bl 801b014 <memset>
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000e26: f007 fcc5 bl 80087b4 <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000e2a: 4b41 ldr r3, [pc, #260] ; (8000f30 <SystemClock_Config+0x13c>)
8000e2c: 6c1b ldr r3, [r3, #64] ; 0x40
8000e2e: 4a40 ldr r2, [pc, #256] ; (8000f30 <SystemClock_Config+0x13c>)
8000e30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000e34: 6413 str r3, [r2, #64] ; 0x40
8000e36: 4b3e ldr r3, [pc, #248] ; (8000f30 <SystemClock_Config+0x13c>)
8000e38: 6c1b ldr r3, [r3, #64] ; 0x40
8000e3a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000e3e: 607b str r3, [r7, #4]
8000e40: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000e42: 4b3c ldr r3, [pc, #240] ; (8000f34 <SystemClock_Config+0x140>)
8000e44: 681b ldr r3, [r3, #0]
8000e46: 4a3b ldr r2, [pc, #236] ; (8000f34 <SystemClock_Config+0x140>)
8000e48: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8000e4c: 6013 str r3, [r2, #0]
8000e4e: 4b39 ldr r3, [pc, #228] ; (8000f34 <SystemClock_Config+0x140>)
8000e50: 681b ldr r3, [r3, #0]
8000e52: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000e56: 603b str r3, [r7, #0]
8000e58: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000e5a: 2301 movs r3, #1
8000e5c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000e60: f44f 3380 mov.w r3, #65536 ; 0x10000
8000e64: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000e68: 2302 movs r3, #2
8000e6a: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000e6e: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000e72: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLM = 25;
8000e76: 2319 movs r3, #25
8000e78: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
RCC_OscInitStruct.PLL.PLLN = 400;
8000e7c: f44f 73c8 mov.w r3, #400 ; 0x190
8000e80: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000e84: 2302 movs r3, #2
8000e86: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
RCC_OscInitStruct.PLL.PLLQ = 9;
8000e8a: 2309 movs r3, #9
8000e8c: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000e90: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000e94: 4618 mov r0, r3
8000e96: f007 fced bl 8008874 <HAL_RCC_OscConfig>
8000e9a: 4603 mov r3, r0
8000e9c: 2b00 cmp r3, #0
8000e9e: d001 beq.n 8000ea4 <SystemClock_Config+0xb0>
{
Error_Handler();
8000ea0: f001 fbc4 bl 800262c <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000ea4: f007 fc96 bl 80087d4 <HAL_PWREx_EnableOverDrive>
8000ea8: 4603 mov r3, r0
8000eaa: 2b00 cmp r3, #0
8000eac: d001 beq.n 8000eb2 <SystemClock_Config+0xbe>
{
Error_Handler();
8000eae: f001 fbbd bl 800262c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000eb2: 230f movs r3, #15
8000eb4: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000eb8: 2302 movs r3, #2
8000eba: f8c7 3090 str.w r3, [r7, #144] ; 0x90
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000ebe: 2300 movs r3, #0
8000ec0: f8c7 3094 str.w r3, [r7, #148] ; 0x94
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000ec4: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000ec8: f8c7 3098 str.w r3, [r7, #152] ; 0x98
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000ecc: f44f 5380 mov.w r3, #4096 ; 0x1000
8000ed0: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
8000ed4: f107 038c add.w r3, r7, #140 ; 0x8c
8000ed8: 2106 movs r1, #6
8000eda: 4618 mov r0, r3
8000edc: f007 ff6e bl 8008dbc <HAL_RCC_ClockConfig>
8000ee0: 4603 mov r3, r0
8000ee2: 2b00 cmp r3, #0
8000ee4: d001 beq.n 8000eea <SystemClock_Config+0xf6>
{
Error_Handler();
8000ee6: f001 fba1 bl 800262c <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_CLK48;
8000eea: 4b13 ldr r3, [pc, #76] ; (8000f38 <SystemClock_Config+0x144>)
8000eec: 60bb str r3, [r7, #8]
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
8000eee: f44f 73c0 mov.w r3, #384 ; 0x180
8000ef2: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
8000ef4: 2305 movs r3, #5
8000ef6: 627b str r3, [r7, #36] ; 0x24
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
8000ef8: 2302 movs r3, #2
8000efa: 623b str r3, [r7, #32]
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
8000efc: 2303 movs r3, #3
8000efe: 62bb str r3, [r7, #40] ; 0x28
PeriphClkInitStruct.PLLSAIDivQ = 1;
8000f00: 2301 movs r3, #1
8000f02: 633b str r3, [r7, #48] ; 0x30
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
8000f04: f44f 3300 mov.w r3, #131072 ; 0x20000
8000f08: 637b str r3, [r7, #52] ; 0x34
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
8000f0a: f04f 6300 mov.w r3, #134217728 ; 0x8000000
8000f0e: f8c7 3084 str.w r3, [r7, #132] ; 0x84
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000f12: f107 0308 add.w r3, r7, #8
8000f16: 4618 mov r0, r3
8000f18: f008 f940 bl 800919c <HAL_RCCEx_PeriphCLKConfig>
8000f1c: 4603 mov r3, r0
8000f1e: 2b00 cmp r3, #0
8000f20: d001 beq.n 8000f26 <SystemClock_Config+0x132>
{
Error_Handler();
8000f22: f001 fb83 bl 800262c <Error_Handler>
}
}
8000f26: bf00 nop
8000f28: 37d0 adds r7, #208 ; 0xd0
8000f2a: 46bd mov sp, r7
8000f2c: bd80 pop {r7, pc}
8000f2e: bf00 nop
8000f30: 40023800 .word 0x40023800
8000f34: 40007000 .word 0x40007000
8000f38: 00200008 .word 0x00200008
08000f3c <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000f3c: b580 push {r7, lr}
8000f3e: b084 sub sp, #16
8000f40: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000f42: 463b mov r3, r7
8000f44: 2200 movs r2, #0
8000f46: 601a str r2, [r3, #0]
8000f48: 605a str r2, [r3, #4]
8000f4a: 609a str r2, [r3, #8]
8000f4c: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
8000f4e: 4b21 ldr r3, [pc, #132] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f50: 4a21 ldr r2, [pc, #132] ; (8000fd8 <MX_ADC1_Init+0x9c>)
8000f52: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000f54: 4b1f ldr r3, [pc, #124] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f56: f44f 3280 mov.w r2, #65536 ; 0x10000
8000f5a: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000f5c: 4b1d ldr r3, [pc, #116] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f5e: 2200 movs r2, #0
8000f60: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000f62: 4b1c ldr r3, [pc, #112] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f64: 2200 movs r2, #0
8000f66: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000f68: 4b1a ldr r3, [pc, #104] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f6a: 2200 movs r2, #0
8000f6c: 619a str r2, [r3, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000f6e: 4b19 ldr r3, [pc, #100] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f70: 2200 movs r2, #0
8000f72: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000f76: 4b17 ldr r3, [pc, #92] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f78: 2200 movs r2, #0
8000f7a: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000f7c: 4b15 ldr r3, [pc, #84] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f7e: 4a17 ldr r2, [pc, #92] ; (8000fdc <MX_ADC1_Init+0xa0>)
8000f80: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000f82: 4b14 ldr r3, [pc, #80] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f84: 2200 movs r2, #0
8000f86: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 1;
8000f88: 4b12 ldr r3, [pc, #72] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f8a: 2201 movs r2, #1
8000f8c: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = DISABLE;
8000f8e: 4b11 ldr r3, [pc, #68] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f90: 2200 movs r2, #0
8000f92: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000f96: 4b0f ldr r3, [pc, #60] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f98: 2201 movs r2, #1
8000f9a: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000f9c: 480d ldr r0, [pc, #52] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000f9e: f003 fd2d bl 80049fc <HAL_ADC_Init>
8000fa2: 4603 mov r3, r0
8000fa4: 2b00 cmp r3, #0
8000fa6: d001 beq.n 8000fac <MX_ADC1_Init+0x70>
{
Error_Handler();
8000fa8: f001 fb40 bl 800262c <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000fac: 2300 movs r3, #0
8000fae: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000fb0: 2301 movs r3, #1
8000fb2: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000fb4: 2300 movs r3, #0
8000fb6: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000fb8: 463b mov r3, r7
8000fba: 4619 mov r1, r3
8000fbc: 4805 ldr r0, [pc, #20] ; (8000fd4 <MX_ADC1_Init+0x98>)
8000fbe: f003 feb3 bl 8004d28 <HAL_ADC_ConfigChannel>
8000fc2: 4603 mov r3, r0
8000fc4: 2b00 cmp r3, #0
8000fc6: d001 beq.n 8000fcc <MX_ADC1_Init+0x90>
{
Error_Handler();
8000fc8: f001 fb30 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000fcc: bf00 nop
8000fce: 3710 adds r7, #16
8000fd0: 46bd mov sp, r7
8000fd2: bd80 pop {r7, pc}
8000fd4: 20008a74 .word 0x20008a74
8000fd8: 40012000 .word 0x40012000
8000fdc: 0f000001 .word 0x0f000001
08000fe0 <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000fe0: b580 push {r7, lr}
8000fe2: b084 sub sp, #16
8000fe4: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000fe6: 463b mov r3, r7
8000fe8: 2200 movs r2, #0
8000fea: 601a str r2, [r3, #0]
8000fec: 605a str r2, [r3, #4]
8000fee: 609a str r2, [r3, #8]
8000ff0: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
8000ff2: 4b21 ldr r3, [pc, #132] ; (8001078 <MX_ADC3_Init+0x98>)
8000ff4: 4a21 ldr r2, [pc, #132] ; (800107c <MX_ADC3_Init+0x9c>)
8000ff6: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000ff8: 4b1f ldr r3, [pc, #124] ; (8001078 <MX_ADC3_Init+0x98>)
8000ffa: f44f 3280 mov.w r2, #65536 ; 0x10000
8000ffe: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
8001000: 4b1d ldr r3, [pc, #116] ; (8001078 <MX_ADC3_Init+0x98>)
8001002: 2200 movs r2, #0
8001004: 609a str r2, [r3, #8]
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
8001006: 4b1c ldr r3, [pc, #112] ; (8001078 <MX_ADC3_Init+0x98>)
8001008: 2200 movs r2, #0
800100a: 611a str r2, [r3, #16]
hadc3.Init.ContinuousConvMode = DISABLE;
800100c: 4b1a ldr r3, [pc, #104] ; (8001078 <MX_ADC3_Init+0x98>)
800100e: 2200 movs r2, #0
8001010: 619a str r2, [r3, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
8001012: 4b19 ldr r3, [pc, #100] ; (8001078 <MX_ADC3_Init+0x98>)
8001014: 2200 movs r2, #0
8001016: f883 2020 strb.w r2, [r3, #32]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800101a: 4b17 ldr r3, [pc, #92] ; (8001078 <MX_ADC3_Init+0x98>)
800101c: 2200 movs r2, #0
800101e: 62da str r2, [r3, #44] ; 0x2c
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001020: 4b15 ldr r3, [pc, #84] ; (8001078 <MX_ADC3_Init+0x98>)
8001022: 4a17 ldr r2, [pc, #92] ; (8001080 <MX_ADC3_Init+0xa0>)
8001024: 629a str r2, [r3, #40] ; 0x28
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001026: 4b14 ldr r3, [pc, #80] ; (8001078 <MX_ADC3_Init+0x98>)
8001028: 2200 movs r2, #0
800102a: 60da str r2, [r3, #12]
hadc3.Init.NbrOfConversion = 1;
800102c: 4b12 ldr r3, [pc, #72] ; (8001078 <MX_ADC3_Init+0x98>)
800102e: 2201 movs r2, #1
8001030: 61da str r2, [r3, #28]
hadc3.Init.DMAContinuousRequests = DISABLE;
8001032: 4b11 ldr r3, [pc, #68] ; (8001078 <MX_ADC3_Init+0x98>)
8001034: 2200 movs r2, #0
8001036: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800103a: 4b0f ldr r3, [pc, #60] ; (8001078 <MX_ADC3_Init+0x98>)
800103c: 2201 movs r2, #1
800103e: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
8001040: 480d ldr r0, [pc, #52] ; (8001078 <MX_ADC3_Init+0x98>)
8001042: f003 fcdb bl 80049fc <HAL_ADC_Init>
8001046: 4603 mov r3, r0
8001048: 2b00 cmp r3, #0
800104a: d001 beq.n 8001050 <MX_ADC3_Init+0x70>
{
Error_Handler();
800104c: f001 faee bl 800262c <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_8;
8001050: 2308 movs r3, #8
8001052: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8001054: 2301 movs r3, #1
8001056: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001058: 2300 movs r3, #0
800105a: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
800105c: 463b mov r3, r7
800105e: 4619 mov r1, r3
8001060: 4805 ldr r0, [pc, #20] ; (8001078 <MX_ADC3_Init+0x98>)
8001062: f003 fe61 bl 8004d28 <HAL_ADC_ConfigChannel>
8001066: 4603 mov r3, r0
8001068: 2b00 cmp r3, #0
800106a: d001 beq.n 8001070 <MX_ADC3_Init+0x90>
{
Error_Handler();
800106c: f001 fade bl 800262c <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
8001070: bf00 nop
8001072: 3710 adds r7, #16
8001074: 46bd mov sp, r7
8001076: bd80 pop {r7, pc}
8001078: 20008abc .word 0x20008abc
800107c: 40012200 .word 0x40012200
8001080: 0f000001 .word 0x0f000001
08001084 <MX_CRC_Init>:
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
8001084: b580 push {r7, lr}
8001086: af00 add r7, sp, #0
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
8001088: 4b0d ldr r3, [pc, #52] ; (80010c0 <MX_CRC_Init+0x3c>)
800108a: 4a0e ldr r2, [pc, #56] ; (80010c4 <MX_CRC_Init+0x40>)
800108c: 601a str r2, [r3, #0]
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
800108e: 4b0c ldr r3, [pc, #48] ; (80010c0 <MX_CRC_Init+0x3c>)
8001090: 2200 movs r2, #0
8001092: 711a strb r2, [r3, #4]
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
8001094: 4b0a ldr r3, [pc, #40] ; (80010c0 <MX_CRC_Init+0x3c>)
8001096: 2200 movs r2, #0
8001098: 715a strb r2, [r3, #5]
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
800109a: 4b09 ldr r3, [pc, #36] ; (80010c0 <MX_CRC_Init+0x3c>)
800109c: 2200 movs r2, #0
800109e: 615a str r2, [r3, #20]
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
80010a0: 4b07 ldr r3, [pc, #28] ; (80010c0 <MX_CRC_Init+0x3c>)
80010a2: 2200 movs r2, #0
80010a4: 619a str r2, [r3, #24]
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
80010a6: 4b06 ldr r3, [pc, #24] ; (80010c0 <MX_CRC_Init+0x3c>)
80010a8: 2201 movs r2, #1
80010aa: 621a str r2, [r3, #32]
if (HAL_CRC_Init(&hcrc) != HAL_OK)
80010ac: 4804 ldr r0, [pc, #16] ; (80010c0 <MX_CRC_Init+0x3c>)
80010ae: f004 f961 bl 8005374 <HAL_CRC_Init>
80010b2: 4603 mov r3, r0
80010b4: 2b00 cmp r3, #0
80010b6: d001 beq.n 80010bc <MX_CRC_Init+0x38>
{
Error_Handler();
80010b8: f001 fab8 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
80010bc: bf00 nop
80010be: bd80 pop {r7, pc}
80010c0: 20008924 .word 0x20008924
80010c4: 40023000 .word 0x40023000
080010c8 <MX_DAC_Init>:
* @brief DAC Initialization Function
* @param None
* @retval None
*/
static void MX_DAC_Init(void)
{
80010c8: b580 push {r7, lr}
80010ca: b082 sub sp, #8
80010cc: af00 add r7, sp, #0
/* USER CODE BEGIN DAC_Init 0 */
/* USER CODE END DAC_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
80010ce: 463b mov r3, r7
80010d0: 2200 movs r2, #0
80010d2: 601a str r2, [r3, #0]
80010d4: 605a str r2, [r3, #4]
/* USER CODE BEGIN DAC_Init 1 */
/* USER CODE END DAC_Init 1 */
/** DAC Initialization
*/
hdac.Instance = DAC;
80010d6: 4b0f ldr r3, [pc, #60] ; (8001114 <MX_DAC_Init+0x4c>)
80010d8: 4a0f ldr r2, [pc, #60] ; (8001118 <MX_DAC_Init+0x50>)
80010da: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac) != HAL_OK)
80010dc: 480d ldr r0, [pc, #52] ; (8001114 <MX_DAC_Init+0x4c>)
80010de: f004 fa33 bl 8005548 <HAL_DAC_Init>
80010e2: 4603 mov r3, r0
80010e4: 2b00 cmp r3, #0
80010e6: d001 beq.n 80010ec <MX_DAC_Init+0x24>
{
Error_Handler();
80010e8: f001 faa0 bl 800262c <Error_Handler>
}
/** DAC channel OUT1 config
*/
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
80010ec: 2300 movs r3, #0
80010ee: 603b str r3, [r7, #0]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
80010f0: 2300 movs r3, #0
80010f2: 607b str r3, [r7, #4]
if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
80010f4: 463b mov r3, r7
80010f6: 2200 movs r2, #0
80010f8: 4619 mov r1, r3
80010fa: 4806 ldr r0, [pc, #24] ; (8001114 <MX_DAC_Init+0x4c>)
80010fc: f004 fa9a bl 8005634 <HAL_DAC_ConfigChannel>
8001100: 4603 mov r3, r0
8001102: 2b00 cmp r3, #0
8001104: d001 beq.n 800110a <MX_DAC_Init+0x42>
{
Error_Handler();
8001106: f001 fa91 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN DAC_Init 2 */
/* USER CODE END DAC_Init 2 */
}
800110a: bf00 nop
800110c: 3708 adds r7, #8
800110e: 46bd mov sp, r7
8001110: bd80 pop {r7, pc}
8001112: bf00 nop
8001114: 20008b0c .word 0x20008b0c
8001118: 40007400 .word 0x40007400
0800111c <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
800111c: b580 push {r7, lr}
800111e: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
8001120: 4b15 ldr r3, [pc, #84] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001122: 4a16 ldr r2, [pc, #88] ; (800117c <MX_DMA2D_Init+0x60>)
8001124: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
8001126: 4b14 ldr r3, [pc, #80] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001128: 2200 movs r2, #0
800112a: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
800112c: 4b12 ldr r3, [pc, #72] ; (8001178 <MX_DMA2D_Init+0x5c>)
800112e: 2200 movs r2, #0
8001130: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
8001132: 4b11 ldr r3, [pc, #68] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001134: 2200 movs r2, #0
8001136: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
8001138: 4b0f ldr r3, [pc, #60] ; (8001178 <MX_DMA2D_Init+0x5c>)
800113a: 2200 movs r2, #0
800113c: 629a str r2, [r3, #40] ; 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
800113e: 4b0e ldr r3, [pc, #56] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001140: 2200 movs r2, #0
8001142: 62da str r2, [r3, #44] ; 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
8001144: 4b0c ldr r3, [pc, #48] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001146: 2200 movs r2, #0
8001148: 631a str r2, [r3, #48] ; 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
800114a: 4b0b ldr r3, [pc, #44] ; (8001178 <MX_DMA2D_Init+0x5c>)
800114c: 2200 movs r2, #0
800114e: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
8001150: 4809 ldr r0, [pc, #36] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001152: f004 fc83 bl 8005a5c <HAL_DMA2D_Init>
8001156: 4603 mov r3, r0
8001158: 2b00 cmp r3, #0
800115a: d001 beq.n 8001160 <MX_DMA2D_Init+0x44>
{
Error_Handler();
800115c: f001 fa66 bl 800262c <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
8001160: 2101 movs r1, #1
8001162: 4805 ldr r0, [pc, #20] ; (8001178 <MX_DMA2D_Init+0x5c>)
8001164: f004 fdd8 bl 8005d18 <HAL_DMA2D_ConfigLayer>
8001168: 4603 mov r3, r0
800116a: 2b00 cmp r3, #0
800116c: d001 beq.n 8001172 <MX_DMA2D_Init+0x56>
{
Error_Handler();
800116e: f001 fa5d bl 800262c <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
8001172: bf00 nop
8001174: bd80 pop {r7, pc}
8001176: bf00 nop
8001178: 20008b78 .word 0x20008b78
800117c: 4002b000 .word 0x4002b000
08001180 <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
8001180: b580 push {r7, lr}
8001182: b08e sub sp, #56 ; 0x38
8001184: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
8001186: 1d3b adds r3, r7, #4
8001188: 2234 movs r2, #52 ; 0x34
800118a: 2100 movs r1, #0
800118c: 4618 mov r0, r3
800118e: f019 ff41 bl 801b014 <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
8001192: 4b3a ldr r3, [pc, #232] ; (800127c <MX_LTDC_Init+0xfc>)
8001194: 4a3a ldr r2, [pc, #232] ; (8001280 <MX_LTDC_Init+0x100>)
8001196: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
8001198: 4b38 ldr r3, [pc, #224] ; (800127c <MX_LTDC_Init+0xfc>)
800119a: 2200 movs r2, #0
800119c: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
800119e: 4b37 ldr r3, [pc, #220] ; (800127c <MX_LTDC_Init+0xfc>)
80011a0: 2200 movs r2, #0
80011a2: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80011a4: 4b35 ldr r3, [pc, #212] ; (800127c <MX_LTDC_Init+0xfc>)
80011a6: 2200 movs r2, #0
80011a8: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80011aa: 4b34 ldr r3, [pc, #208] ; (800127c <MX_LTDC_Init+0xfc>)
80011ac: 2200 movs r2, #0
80011ae: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 40;
80011b0: 4b32 ldr r3, [pc, #200] ; (800127c <MX_LTDC_Init+0xfc>)
80011b2: 2228 movs r2, #40 ; 0x28
80011b4: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 9;
80011b6: 4b31 ldr r3, [pc, #196] ; (800127c <MX_LTDC_Init+0xfc>)
80011b8: 2209 movs r2, #9
80011ba: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 53;
80011bc: 4b2f ldr r3, [pc, #188] ; (800127c <MX_LTDC_Init+0xfc>)
80011be: 2235 movs r2, #53 ; 0x35
80011c0: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 11;
80011c2: 4b2e ldr r3, [pc, #184] ; (800127c <MX_LTDC_Init+0xfc>)
80011c4: 220b movs r2, #11
80011c6: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 533;
80011c8: 4b2c ldr r3, [pc, #176] ; (800127c <MX_LTDC_Init+0xfc>)
80011ca: f240 2215 movw r2, #533 ; 0x215
80011ce: 625a str r2, [r3, #36] ; 0x24
hltdc.Init.AccumulatedActiveH = 283;
80011d0: 4b2a ldr r3, [pc, #168] ; (800127c <MX_LTDC_Init+0xfc>)
80011d2: f240 121b movw r2, #283 ; 0x11b
80011d6: 629a str r2, [r3, #40] ; 0x28
hltdc.Init.TotalWidth = 565;
80011d8: 4b28 ldr r3, [pc, #160] ; (800127c <MX_LTDC_Init+0xfc>)
80011da: f240 2235 movw r2, #565 ; 0x235
80011de: 62da str r2, [r3, #44] ; 0x2c
hltdc.Init.TotalHeigh = 285;
80011e0: 4b26 ldr r3, [pc, #152] ; (800127c <MX_LTDC_Init+0xfc>)
80011e2: f240 121d movw r2, #285 ; 0x11d
80011e6: 631a str r2, [r3, #48] ; 0x30
hltdc.Init.Backcolor.Blue = 0;
80011e8: 4b24 ldr r3, [pc, #144] ; (800127c <MX_LTDC_Init+0xfc>)
80011ea: 2200 movs r2, #0
80011ec: f883 2034 strb.w r2, [r3, #52] ; 0x34
hltdc.Init.Backcolor.Green = 0;
80011f0: 4b22 ldr r3, [pc, #136] ; (800127c <MX_LTDC_Init+0xfc>)
80011f2: 2200 movs r2, #0
80011f4: f883 2035 strb.w r2, [r3, #53] ; 0x35
hltdc.Init.Backcolor.Red = 0;
80011f8: 4b20 ldr r3, [pc, #128] ; (800127c <MX_LTDC_Init+0xfc>)
80011fa: 2200 movs r2, #0
80011fc: f883 2036 strb.w r2, [r3, #54] ; 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
8001200: 481e ldr r0, [pc, #120] ; (800127c <MX_LTDC_Init+0xfc>)
8001202: f006 ff5f bl 80080c4 <HAL_LTDC_Init>
8001206: 4603 mov r3, r0
8001208: 2b00 cmp r3, #0
800120a: d001 beq.n 8001210 <MX_LTDC_Init+0x90>
{
Error_Handler();
800120c: f001 fa0e bl 800262c <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
8001210: 2300 movs r3, #0
8001212: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 480;
8001214: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001218: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
800121a: 2300 movs r3, #0
800121c: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 272;
800121e: f44f 7388 mov.w r3, #272 ; 0x110
8001222: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
8001224: 2302 movs r3, #2
8001226: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
8001228: 23ff movs r3, #255 ; 0xff
800122a: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
800122c: 2300 movs r3, #0
800122e: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8001230: f44f 63c0 mov.w r3, #1536 ; 0x600
8001234: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8001236: 2307 movs r3, #7
8001238: 627b str r3, [r7, #36] ; 0x24
pLayerCfg.FBStartAdress = 0xC0000000;
800123a: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000
800123e: 62bb str r3, [r7, #40] ; 0x28
pLayerCfg.ImageWidth = 480;
8001240: f44f 73f0 mov.w r3, #480 ; 0x1e0
8001244: 62fb str r3, [r7, #44] ; 0x2c
pLayerCfg.ImageHeight = 272;
8001246: f44f 7388 mov.w r3, #272 ; 0x110
800124a: 633b str r3, [r7, #48] ; 0x30
pLayerCfg.Backcolor.Blue = 0;
800124c: 2300 movs r3, #0
800124e: f887 3034 strb.w r3, [r7, #52] ; 0x34
pLayerCfg.Backcolor.Green = 0;
8001252: 2300 movs r3, #0
8001254: f887 3035 strb.w r3, [r7, #53] ; 0x35
pLayerCfg.Backcolor.Red = 0;
8001258: 2300 movs r3, #0
800125a: f887 3036 strb.w r3, [r7, #54] ; 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
800125e: 1d3b adds r3, r7, #4
8001260: 2200 movs r2, #0
8001262: 4619 mov r1, r3
8001264: 4805 ldr r0, [pc, #20] ; (800127c <MX_LTDC_Init+0xfc>)
8001266: f007 f8bf bl 80083e8 <HAL_LTDC_ConfigLayer>
800126a: 4603 mov r3, r0
800126c: 2b00 cmp r3, #0
800126e: d001 beq.n 8001274 <MX_LTDC_Init+0xf4>
{
Error_Handler();
8001270: f001 f9dc bl 800262c <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
8001274: bf00 nop
8001276: 3738 adds r7, #56 ; 0x38
8001278: 46bd mov sp, r7
800127a: bd80 pop {r7, pc}
800127c: 200089cc .word 0x200089cc
8001280: 40016800 .word 0x40016800
08001284 <MX_RNG_Init>:
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
8001284: b580 push {r7, lr}
8001286: af00 add r7, sp, #0
/* USER CODE END RNG_Init 0 */
/* USER CODE BEGIN RNG_Init 1 */
/* USER CODE END RNG_Init 1 */
hrng.Instance = RNG;
8001288: 4b06 ldr r3, [pc, #24] ; (80012a4 <MX_RNG_Init+0x20>)
800128a: 4a07 ldr r2, [pc, #28] ; (80012a8 <MX_RNG_Init+0x24>)
800128c: 601a str r2, [r3, #0]
if (HAL_RNG_Init(&hrng) != HAL_OK)
800128e: 4805 ldr r0, [pc, #20] ; (80012a4 <MX_RNG_Init+0x20>)
8001290: f008 fb72 bl 8009978 <HAL_RNG_Init>
8001294: 4603 mov r3, r0
8001296: 2b00 cmp r3, #0
8001298: d001 beq.n 800129e <MX_RNG_Init+0x1a>
{
Error_Handler();
800129a: f001 f9c7 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN RNG_Init 2 */
/* USER CODE END RNG_Init 2 */
}
800129e: bf00 nop
80012a0: bd80 pop {r7, pc}
80012a2: bf00 nop
80012a4: 20008b64 .word 0x20008b64
80012a8: 50060800 .word 0x50060800
080012ac <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
80012ac: b580 push {r7, lr}
80012ae: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
80012b0: 4b1b ldr r3, [pc, #108] ; (8001320 <MX_SPI2_Init+0x74>)
80012b2: 4a1c ldr r2, [pc, #112] ; (8001324 <MX_SPI2_Init+0x78>)
80012b4: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
80012b6: 4b1a ldr r3, [pc, #104] ; (8001320 <MX_SPI2_Init+0x74>)
80012b8: f44f 7282 mov.w r2, #260 ; 0x104
80012bc: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
80012be: 4b18 ldr r3, [pc, #96] ; (8001320 <MX_SPI2_Init+0x74>)
80012c0: 2200 movs r2, #0
80012c2: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
80012c4: 4b16 ldr r3, [pc, #88] ; (8001320 <MX_SPI2_Init+0x74>)
80012c6: f44f 7240 mov.w r2, #768 ; 0x300
80012ca: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
80012cc: 4b14 ldr r3, [pc, #80] ; (8001320 <MX_SPI2_Init+0x74>)
80012ce: 2200 movs r2, #0
80012d0: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
80012d2: 4b13 ldr r3, [pc, #76] ; (8001320 <MX_SPI2_Init+0x74>)
80012d4: 2200 movs r2, #0
80012d6: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
80012d8: 4b11 ldr r3, [pc, #68] ; (8001320 <MX_SPI2_Init+0x74>)
80012da: f44f 2280 mov.w r2, #262144 ; 0x40000
80012de: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80012e0: 4b0f ldr r3, [pc, #60] ; (8001320 <MX_SPI2_Init+0x74>)
80012e2: 2200 movs r2, #0
80012e4: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
80012e6: 4b0e ldr r3, [pc, #56] ; (8001320 <MX_SPI2_Init+0x74>)
80012e8: 2200 movs r2, #0
80012ea: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
80012ec: 4b0c ldr r3, [pc, #48] ; (8001320 <MX_SPI2_Init+0x74>)
80012ee: 2200 movs r2, #0
80012f0: 625a str r2, [r3, #36] ; 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80012f2: 4b0b ldr r3, [pc, #44] ; (8001320 <MX_SPI2_Init+0x74>)
80012f4: 2200 movs r2, #0
80012f6: 629a str r2, [r3, #40] ; 0x28
hspi2.Init.CRCPolynomial = 7;
80012f8: 4b09 ldr r3, [pc, #36] ; (8001320 <MX_SPI2_Init+0x74>)
80012fa: 2207 movs r2, #7
80012fc: 62da str r2, [r3, #44] ; 0x2c
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
80012fe: 4b08 ldr r3, [pc, #32] ; (8001320 <MX_SPI2_Init+0x74>)
8001300: 2200 movs r2, #0
8001302: 631a str r2, [r3, #48] ; 0x30
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
8001304: 4b06 ldr r3, [pc, #24] ; (8001320 <MX_SPI2_Init+0x74>)
8001306: 2208 movs r2, #8
8001308: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi2) != HAL_OK)
800130a: 4805 ldr r0, [pc, #20] ; (8001320 <MX_SPI2_Init+0x74>)
800130c: f008 fbdd bl 8009aca <HAL_SPI_Init>
8001310: 4603 mov r3, r0
8001312: 2b00 cmp r3, #0
8001314: d001 beq.n 800131a <MX_SPI2_Init+0x6e>
{
Error_Handler();
8001316: f001 f989 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
800131a: bf00 nop
800131c: bd80 pop {r7, pc}
800131e: bf00 nop
8001320: 2000887c .word 0x2000887c
8001324: 40003800 .word 0x40003800
08001328 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8001328: b580 push {r7, lr}
800132a: b088 sub sp, #32
800132c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800132e: f107 0310 add.w r3, r7, #16
8001332: 2200 movs r2, #0
8001334: 601a str r2, [r3, #0]
8001336: 605a str r2, [r3, #4]
8001338: 609a str r2, [r3, #8]
800133a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800133c: 1d3b adds r3, r7, #4
800133e: 2200 movs r2, #0
8001340: 601a str r2, [r3, #0]
8001342: 605a str r2, [r3, #4]
8001344: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8001346: 4b20 ldr r3, [pc, #128] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001348: 4a20 ldr r2, [pc, #128] ; (80013cc <MX_TIM1_Init+0xa4>)
800134a: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800134c: 4b1e ldr r3, [pc, #120] ; (80013c8 <MX_TIM1_Init+0xa0>)
800134e: 2200 movs r2, #0
8001350: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8001352: 4b1d ldr r3, [pc, #116] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001354: 2200 movs r2, #0
8001356: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
8001358: 4b1b ldr r3, [pc, #108] ; (80013c8 <MX_TIM1_Init+0xa0>)
800135a: f64f 72ff movw r2, #65535 ; 0xffff
800135e: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001360: 4b19 ldr r3, [pc, #100] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001362: 2200 movs r2, #0
8001364: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8001366: 4b18 ldr r3, [pc, #96] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001368: 2200 movs r2, #0
800136a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800136c: 4b16 ldr r3, [pc, #88] ; (80013c8 <MX_TIM1_Init+0xa0>)
800136e: 2200 movs r2, #0
8001370: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001372: 4815 ldr r0, [pc, #84] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001374: f008 fc3b bl 8009bee <HAL_TIM_Base_Init>
8001378: 4603 mov r3, r0
800137a: 2b00 cmp r3, #0
800137c: d001 beq.n 8001382 <MX_TIM1_Init+0x5a>
{
Error_Handler();
800137e: f001 f955 bl 800262c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001382: f44f 5380 mov.w r3, #4096 ; 0x1000
8001386: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001388: f107 0310 add.w r3, r7, #16
800138c: 4619 mov r1, r3
800138e: 480e ldr r0, [pc, #56] ; (80013c8 <MX_TIM1_Init+0xa0>)
8001390: f008 feee bl 800a170 <HAL_TIM_ConfigClockSource>
8001394: 4603 mov r3, r0
8001396: 2b00 cmp r3, #0
8001398: d001 beq.n 800139e <MX_TIM1_Init+0x76>
{
Error_Handler();
800139a: f001 f947 bl 800262c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800139e: 2300 movs r3, #0
80013a0: 607b str r3, [r7, #4]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
80013a2: 2300 movs r3, #0
80013a4: 60bb str r3, [r7, #8]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80013a6: 2300 movs r3, #0
80013a8: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
80013aa: 1d3b adds r3, r7, #4
80013ac: 4619 mov r1, r3
80013ae: 4806 ldr r0, [pc, #24] ; (80013c8 <MX_TIM1_Init+0xa0>)
80013b0: f009 fc22 bl 800abf8 <HAL_TIMEx_MasterConfigSynchronization>
80013b4: 4603 mov r3, r0
80013b6: 2b00 cmp r3, #0
80013b8: d001 beq.n 80013be <MX_TIM1_Init+0x96>
{
Error_Handler();
80013ba: f001 f937 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
80013be: bf00 nop
80013c0: 3720 adds r7, #32
80013c2: 46bd mov sp, r7
80013c4: bd80 pop {r7, pc}
80013c6: bf00 nop
80013c8: 20008b24 .word 0x20008b24
80013cc: 40010000 .word 0x40010000
080013d0 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
80013d0: b580 push {r7, lr}
80013d2: b088 sub sp, #32
80013d4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80013d6: f107 0310 add.w r3, r7, #16
80013da: 2200 movs r2, #0
80013dc: 601a str r2, [r3, #0]
80013de: 605a str r2, [r3, #4]
80013e0: 609a str r2, [r3, #8]
80013e2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80013e4: 1d3b adds r3, r7, #4
80013e6: 2200 movs r2, #0
80013e8: 601a str r2, [r3, #0]
80013ea: 605a str r2, [r3, #4]
80013ec: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
80013ee: 4b1e ldr r3, [pc, #120] ; (8001468 <MX_TIM2_Init+0x98>)
80013f0: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
80013f4: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
80013f6: 4b1c ldr r3, [pc, #112] ; (8001468 <MX_TIM2_Init+0x98>)
80013f8: 2200 movs r2, #0
80013fa: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
80013fc: 4b1a ldr r3, [pc, #104] ; (8001468 <MX_TIM2_Init+0x98>)
80013fe: 2200 movs r2, #0
8001400: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
8001402: 4b19 ldr r3, [pc, #100] ; (8001468 <MX_TIM2_Init+0x98>)
8001404: f04f 32ff mov.w r2, #4294967295
8001408: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800140a: 4b17 ldr r3, [pc, #92] ; (8001468 <MX_TIM2_Init+0x98>)
800140c: 2200 movs r2, #0
800140e: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001410: 4b15 ldr r3, [pc, #84] ; (8001468 <MX_TIM2_Init+0x98>)
8001412: 2200 movs r2, #0
8001414: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
8001416: 4814 ldr r0, [pc, #80] ; (8001468 <MX_TIM2_Init+0x98>)
8001418: f008 fbe9 bl 8009bee <HAL_TIM_Base_Init>
800141c: 4603 mov r3, r0
800141e: 2b00 cmp r3, #0
8001420: d001 beq.n 8001426 <MX_TIM2_Init+0x56>
{
Error_Handler();
8001422: f001 f903 bl 800262c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001426: f44f 5380 mov.w r3, #4096 ; 0x1000
800142a: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
800142c: f107 0310 add.w r3, r7, #16
8001430: 4619 mov r1, r3
8001432: 480d ldr r0, [pc, #52] ; (8001468 <MX_TIM2_Init+0x98>)
8001434: f008 fe9c bl 800a170 <HAL_TIM_ConfigClockSource>
8001438: 4603 mov r3, r0
800143a: 2b00 cmp r3, #0
800143c: d001 beq.n 8001442 <MX_TIM2_Init+0x72>
{
Error_Handler();
800143e: f001 f8f5 bl 800262c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001442: 2300 movs r3, #0
8001444: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001446: 2300 movs r3, #0
8001448: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
800144a: 1d3b adds r3, r7, #4
800144c: 4619 mov r1, r3
800144e: 4806 ldr r0, [pc, #24] ; (8001468 <MX_TIM2_Init+0x98>)
8001450: f009 fbd2 bl 800abf8 <HAL_TIMEx_MasterConfigSynchronization>
8001454: 4603 mov r3, r0
8001456: 2b00 cmp r3, #0
8001458: d001 beq.n 800145e <MX_TIM2_Init+0x8e>
{
Error_Handler();
800145a: f001 f8e7 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
800145e: bf00 nop
8001460: 3720 adds r7, #32
8001462: 46bd mov sp, r7
8001464: bd80 pop {r7, pc}
8001466: bf00 nop
8001468: 20008bb8 .word 0x20008bb8
0800146c <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
800146c: b580 push {r7, lr}
800146e: b094 sub sp, #80 ; 0x50
8001470: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001472: f107 0340 add.w r3, r7, #64 ; 0x40
8001476: 2200 movs r2, #0
8001478: 601a str r2, [r3, #0]
800147a: 605a str r2, [r3, #4]
800147c: 609a str r2, [r3, #8]
800147e: 60da str r2, [r3, #12]
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
8001480: f107 032c add.w r3, r7, #44 ; 0x2c
8001484: 2200 movs r2, #0
8001486: 601a str r2, [r3, #0]
8001488: 605a str r2, [r3, #4]
800148a: 609a str r2, [r3, #8]
800148c: 60da str r2, [r3, #12]
800148e: 611a str r2, [r3, #16]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001490: f107 0320 add.w r3, r7, #32
8001494: 2200 movs r2, #0
8001496: 601a str r2, [r3, #0]
8001498: 605a str r2, [r3, #4]
800149a: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
800149c: 1d3b adds r3, r7, #4
800149e: 2200 movs r2, #0
80014a0: 601a str r2, [r3, #0]
80014a2: 605a str r2, [r3, #4]
80014a4: 609a str r2, [r3, #8]
80014a6: 60da str r2, [r3, #12]
80014a8: 611a str r2, [r3, #16]
80014aa: 615a str r2, [r3, #20]
80014ac: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
80014ae: 4b34 ldr r3, [pc, #208] ; (8001580 <MX_TIM3_Init+0x114>)
80014b0: 4a34 ldr r2, [pc, #208] ; (8001584 <MX_TIM3_Init+0x118>)
80014b2: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
80014b4: 4b32 ldr r3, [pc, #200] ; (8001580 <MX_TIM3_Init+0x114>)
80014b6: 2200 movs r2, #0
80014b8: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
80014ba: 4b31 ldr r3, [pc, #196] ; (8001580 <MX_TIM3_Init+0x114>)
80014bc: 2200 movs r2, #0
80014be: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
80014c0: 4b2f ldr r3, [pc, #188] ; (8001580 <MX_TIM3_Init+0x114>)
80014c2: f64f 72ff movw r2, #65535 ; 0xffff
80014c6: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80014c8: 4b2d ldr r3, [pc, #180] ; (8001580 <MX_TIM3_Init+0x114>)
80014ca: 2200 movs r2, #0
80014cc: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80014ce: 4b2c ldr r3, [pc, #176] ; (8001580 <MX_TIM3_Init+0x114>)
80014d0: 2200 movs r2, #0
80014d2: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
80014d4: 482a ldr r0, [pc, #168] ; (8001580 <MX_TIM3_Init+0x114>)
80014d6: f008 fb8a bl 8009bee <HAL_TIM_Base_Init>
80014da: 4603 mov r3, r0
80014dc: 2b00 cmp r3, #0
80014de: d001 beq.n 80014e4 <MX_TIM3_Init+0x78>
{
Error_Handler();
80014e0: f001 f8a4 bl 800262c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80014e4: f44f 5380 mov.w r3, #4096 ; 0x1000
80014e8: 643b str r3, [r7, #64] ; 0x40
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
80014ea: f107 0340 add.w r3, r7, #64 ; 0x40
80014ee: 4619 mov r1, r3
80014f0: 4823 ldr r0, [pc, #140] ; (8001580 <MX_TIM3_Init+0x114>)
80014f2: f008 fe3d bl 800a170 <HAL_TIM_ConfigClockSource>
80014f6: 4603 mov r3, r0
80014f8: 2b00 cmp r3, #0
80014fa: d001 beq.n 8001500 <MX_TIM3_Init+0x94>
{
Error_Handler();
80014fc: f001 f896 bl 800262c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8001500: 481f ldr r0, [pc, #124] ; (8001580 <MX_TIM3_Init+0x114>)
8001502: f008 fbc9 bl 8009c98 <HAL_TIM_PWM_Init>
8001506: 4603 mov r3, r0
8001508: 2b00 cmp r3, #0
800150a: d001 beq.n 8001510 <MX_TIM3_Init+0xa4>
{
Error_Handler();
800150c: f001 f88e bl 800262c <Error_Handler>
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE;
8001510: 2300 movs r3, #0
8001512: 62fb str r3, [r7, #44] ; 0x2c
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
8001514: 2300 movs r3, #0
8001516: 633b str r3, [r7, #48] ; 0x30
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
8001518: f107 032c add.w r3, r7, #44 ; 0x2c
800151c: 4619 mov r1, r3
800151e: 4818 ldr r0, [pc, #96] ; (8001580 <MX_TIM3_Init+0x114>)
8001520: f008 fee0 bl 800a2e4 <HAL_TIM_SlaveConfigSynchro>
8001524: 4603 mov r3, r0
8001526: 2b00 cmp r3, #0
8001528: d001 beq.n 800152e <MX_TIM3_Init+0xc2>
{
Error_Handler();
800152a: f001 f87f bl 800262c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800152e: 2300 movs r3, #0
8001530: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001532: 2300 movs r3, #0
8001534: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001536: f107 0320 add.w r3, r7, #32
800153a: 4619 mov r1, r3
800153c: 4810 ldr r0, [pc, #64] ; (8001580 <MX_TIM3_Init+0x114>)
800153e: f009 fb5b bl 800abf8 <HAL_TIMEx_MasterConfigSynchronization>
8001542: 4603 mov r3, r0
8001544: 2b00 cmp r3, #0
8001546: d001 beq.n 800154c <MX_TIM3_Init+0xe0>
{
Error_Handler();
8001548: f001 f870 bl 800262c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
800154c: 2360 movs r3, #96 ; 0x60
800154e: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
8001550: 2300 movs r3, #0
8001552: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001554: 2300 movs r3, #0
8001556: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001558: 2300 movs r3, #0
800155a: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
800155c: 1d3b adds r3, r7, #4
800155e: 2200 movs r2, #0
8001560: 4619 mov r1, r3
8001562: 4807 ldr r0, [pc, #28] ; (8001580 <MX_TIM3_Init+0x114>)
8001564: f008 fcec bl 8009f40 <HAL_TIM_PWM_ConfigChannel>
8001568: 4603 mov r3, r0
800156a: 2b00 cmp r3, #0
800156c: d001 beq.n 8001572 <MX_TIM3_Init+0x106>
{
Error_Handler();
800156e: f001 f85d bl 800262c <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
8001572: 4803 ldr r0, [pc, #12] ; (8001580 <MX_TIM3_Init+0x114>)
8001574: f002 ff7e bl 8004474 <HAL_TIM_MspPostInit>
}
8001578: bf00 nop
800157a: 3750 adds r7, #80 ; 0x50
800157c: 46bd mov sp, r7
800157e: bd80 pop {r7, pc}
8001580: 2000898c .word 0x2000898c
8001584: 40000400 .word 0x40000400
08001588 <MX_TIM5_Init>:
* @brief TIM5 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM5_Init(void)
{
8001588: b580 push {r7, lr}
800158a: b088 sub sp, #32
800158c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800158e: f107 0310 add.w r3, r7, #16
8001592: 2200 movs r2, #0
8001594: 601a str r2, [r3, #0]
8001596: 605a str r2, [r3, #4]
8001598: 609a str r2, [r3, #8]
800159a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800159c: 1d3b adds r3, r7, #4
800159e: 2200 movs r2, #0
80015a0: 601a str r2, [r3, #0]
80015a2: 605a str r2, [r3, #4]
80015a4: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
80015a6: 4b1d ldr r3, [pc, #116] ; (800161c <MX_TIM5_Init+0x94>)
80015a8: 4a1d ldr r2, [pc, #116] ; (8001620 <MX_TIM5_Init+0x98>)
80015aa: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
80015ac: 4b1b ldr r3, [pc, #108] ; (800161c <MX_TIM5_Init+0x94>)
80015ae: 2200 movs r2, #0
80015b0: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
80015b2: 4b1a ldr r3, [pc, #104] ; (800161c <MX_TIM5_Init+0x94>)
80015b4: 2200 movs r2, #0
80015b6: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
80015b8: 4b18 ldr r3, [pc, #96] ; (800161c <MX_TIM5_Init+0x94>)
80015ba: f04f 32ff mov.w r2, #4294967295
80015be: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80015c0: 4b16 ldr r3, [pc, #88] ; (800161c <MX_TIM5_Init+0x94>)
80015c2: 2200 movs r2, #0
80015c4: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80015c6: 4b15 ldr r3, [pc, #84] ; (800161c <MX_TIM5_Init+0x94>)
80015c8: 2200 movs r2, #0
80015ca: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
80015cc: 4813 ldr r0, [pc, #76] ; (800161c <MX_TIM5_Init+0x94>)
80015ce: f008 fb0e bl 8009bee <HAL_TIM_Base_Init>
80015d2: 4603 mov r3, r0
80015d4: 2b00 cmp r3, #0
80015d6: d001 beq.n 80015dc <MX_TIM5_Init+0x54>
{
Error_Handler();
80015d8: f001 f828 bl 800262c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80015dc: f44f 5380 mov.w r3, #4096 ; 0x1000
80015e0: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
80015e2: f107 0310 add.w r3, r7, #16
80015e6: 4619 mov r1, r3
80015e8: 480c ldr r0, [pc, #48] ; (800161c <MX_TIM5_Init+0x94>)
80015ea: f008 fdc1 bl 800a170 <HAL_TIM_ConfigClockSource>
80015ee: 4603 mov r3, r0
80015f0: 2b00 cmp r3, #0
80015f2: d001 beq.n 80015f8 <MX_TIM5_Init+0x70>
{
Error_Handler();
80015f4: f001 f81a bl 800262c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80015f8: 2300 movs r3, #0
80015fa: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80015fc: 2300 movs r3, #0
80015fe: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
8001600: 1d3b adds r3, r7, #4
8001602: 4619 mov r1, r3
8001604: 4805 ldr r0, [pc, #20] ; (800161c <MX_TIM5_Init+0x94>)
8001606: f009 faf7 bl 800abf8 <HAL_TIMEx_MasterConfigSynchronization>
800160a: 4603 mov r3, r0
800160c: 2b00 cmp r3, #0
800160e: d001 beq.n 8001614 <MX_TIM5_Init+0x8c>
{
Error_Handler();
8001610: f001 f80c bl 800262c <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
8001614: bf00 nop
8001616: 3720 adds r7, #32
8001618: 46bd mov sp, r7
800161a: bd80 pop {r7, pc}
800161c: 2000894c .word 0x2000894c
8001620: 40000c00 .word 0x40000c00
08001624 <MX_TIM8_Init>:
* @brief TIM8 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM8_Init(void)
{
8001624: b580 push {r7, lr}
8001626: b09a sub sp, #104 ; 0x68
8001628: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_Init 0 */
/* USER CODE END TIM8_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800162a: f107 0358 add.w r3, r7, #88 ; 0x58
800162e: 2200 movs r2, #0
8001630: 601a str r2, [r3, #0]
8001632: 605a str r2, [r3, #4]
8001634: 609a str r2, [r3, #8]
8001636: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001638: f107 034c add.w r3, r7, #76 ; 0x4c
800163c: 2200 movs r2, #0
800163e: 601a str r2, [r3, #0]
8001640: 605a str r2, [r3, #4]
8001642: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8001644: f107 0330 add.w r3, r7, #48 ; 0x30
8001648: 2200 movs r2, #0
800164a: 601a str r2, [r3, #0]
800164c: 605a str r2, [r3, #4]
800164e: 609a str r2, [r3, #8]
8001650: 60da str r2, [r3, #12]
8001652: 611a str r2, [r3, #16]
8001654: 615a str r2, [r3, #20]
8001656: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8001658: 1d3b adds r3, r7, #4
800165a: 222c movs r2, #44 ; 0x2c
800165c: 2100 movs r1, #0
800165e: 4618 mov r0, r3
8001660: f019 fcd8 bl 801b014 <memset>
/* USER CODE BEGIN TIM8_Init 1 */
/* USER CODE END TIM8_Init 1 */
htim8.Instance = TIM8;
8001664: 4b42 ldr r3, [pc, #264] ; (8001770 <MX_TIM8_Init+0x14c>)
8001666: 4a43 ldr r2, [pc, #268] ; (8001774 <MX_TIM8_Init+0x150>)
8001668: 601a str r2, [r3, #0]
htim8.Init.Prescaler = 0;
800166a: 4b41 ldr r3, [pc, #260] ; (8001770 <MX_TIM8_Init+0x14c>)
800166c: 2200 movs r2, #0
800166e: 605a str r2, [r3, #4]
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
8001670: 4b3f ldr r3, [pc, #252] ; (8001770 <MX_TIM8_Init+0x14c>)
8001672: 2200 movs r2, #0
8001674: 609a str r2, [r3, #8]
htim8.Init.Period = 65535;
8001676: 4b3e ldr r3, [pc, #248] ; (8001770 <MX_TIM8_Init+0x14c>)
8001678: f64f 72ff movw r2, #65535 ; 0xffff
800167c: 60da str r2, [r3, #12]
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800167e: 4b3c ldr r3, [pc, #240] ; (8001770 <MX_TIM8_Init+0x14c>)
8001680: 2200 movs r2, #0
8001682: 611a str r2, [r3, #16]
htim8.Init.RepetitionCounter = 0;
8001684: 4b3a ldr r3, [pc, #232] ; (8001770 <MX_TIM8_Init+0x14c>)
8001686: 2200 movs r2, #0
8001688: 615a str r2, [r3, #20]
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800168a: 4b39 ldr r3, [pc, #228] ; (8001770 <MX_TIM8_Init+0x14c>)
800168c: 2200 movs r2, #0
800168e: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
8001690: 4837 ldr r0, [pc, #220] ; (8001770 <MX_TIM8_Init+0x14c>)
8001692: f008 faac bl 8009bee <HAL_TIM_Base_Init>
8001696: 4603 mov r3, r0
8001698: 2b00 cmp r3, #0
800169a: d001 beq.n 80016a0 <MX_TIM8_Init+0x7c>
{
Error_Handler();
800169c: f000 ffc6 bl 800262c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80016a0: f44f 5380 mov.w r3, #4096 ; 0x1000
80016a4: 65bb str r3, [r7, #88] ; 0x58
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
80016a6: f107 0358 add.w r3, r7, #88 ; 0x58
80016aa: 4619 mov r1, r3
80016ac: 4830 ldr r0, [pc, #192] ; (8001770 <MX_TIM8_Init+0x14c>)
80016ae: f008 fd5f bl 800a170 <HAL_TIM_ConfigClockSource>
80016b2: 4603 mov r3, r0
80016b4: 2b00 cmp r3, #0
80016b6: d001 beq.n 80016bc <MX_TIM8_Init+0x98>
{
Error_Handler();
80016b8: f000 ffb8 bl 800262c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
80016bc: 482c ldr r0, [pc, #176] ; (8001770 <MX_TIM8_Init+0x14c>)
80016be: f008 faeb bl 8009c98 <HAL_TIM_PWM_Init>
80016c2: 4603 mov r3, r0
80016c4: 2b00 cmp r3, #0
80016c6: d001 beq.n 80016cc <MX_TIM8_Init+0xa8>
{
Error_Handler();
80016c8: f000 ffb0 bl 800262c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80016cc: 2300 movs r3, #0
80016ce: 64fb str r3, [r7, #76] ; 0x4c
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
80016d0: 2300 movs r3, #0
80016d2: 653b str r3, [r7, #80] ; 0x50
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80016d4: 2300 movs r3, #0
80016d6: 657b str r3, [r7, #84] ; 0x54
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
80016d8: f107 034c add.w r3, r7, #76 ; 0x4c
80016dc: 4619 mov r1, r3
80016de: 4824 ldr r0, [pc, #144] ; (8001770 <MX_TIM8_Init+0x14c>)
80016e0: f009 fa8a bl 800abf8 <HAL_TIMEx_MasterConfigSynchronization>
80016e4: 4603 mov r3, r0
80016e6: 2b00 cmp r3, #0
80016e8: d001 beq.n 80016ee <MX_TIM8_Init+0xca>
{
Error_Handler();
80016ea: f000 ff9f bl 800262c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80016ee: 2360 movs r3, #96 ; 0x60
80016f0: 633b str r3, [r7, #48] ; 0x30
sConfigOC.Pulse = 0;
80016f2: 2300 movs r3, #0
80016f4: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80016f6: 2300 movs r3, #0
80016f8: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80016fa: 2300 movs r3, #0
80016fc: 643b str r3, [r7, #64] ; 0x40
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80016fe: 2300 movs r3, #0
8001700: 647b str r3, [r7, #68] ; 0x44
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8001702: 2300 movs r3, #0
8001704: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8001706: f107 0330 add.w r3, r7, #48 ; 0x30
800170a: 220c movs r2, #12
800170c: 4619 mov r1, r3
800170e: 4818 ldr r0, [pc, #96] ; (8001770 <MX_TIM8_Init+0x14c>)
8001710: f008 fc16 bl 8009f40 <HAL_TIM_PWM_ConfigChannel>
8001714: 4603 mov r3, r0
8001716: 2b00 cmp r3, #0
8001718: d001 beq.n 800171e <MX_TIM8_Init+0xfa>
{
Error_Handler();
800171a: f000 ff87 bl 800262c <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
800171e: 2300 movs r3, #0
8001720: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8001722: 2300 movs r3, #0
8001724: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8001726: 2300 movs r3, #0
8001728: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
800172a: 2300 movs r3, #0
800172c: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
800172e: 2300 movs r3, #0
8001730: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001732: f44f 5300 mov.w r3, #8192 ; 0x2000
8001736: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.BreakFilter = 0;
8001738: 2300 movs r3, #0
800173a: 61fb str r3, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
800173c: 2300 movs r3, #0
800173e: 623b str r3, [r7, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8001740: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8001744: 627b str r3, [r7, #36] ; 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
8001746: 2300 movs r3, #0
8001748: 62bb str r3, [r7, #40] ; 0x28
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800174a: 2300 movs r3, #0
800174c: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
800174e: 1d3b adds r3, r7, #4
8001750: 4619 mov r1, r3
8001752: 4807 ldr r0, [pc, #28] ; (8001770 <MX_TIM8_Init+0x14c>)
8001754: f009 fade bl 800ad14 <HAL_TIMEx_ConfigBreakDeadTime>
8001758: 4603 mov r3, r0
800175a: 2b00 cmp r3, #0
800175c: d001 beq.n 8001762 <MX_TIM8_Init+0x13e>
{
Error_Handler();
800175e: f000 ff65 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN TIM8_Init 2 */
/* USER CODE END TIM8_Init 2 */
HAL_TIM_MspPostInit(&htim8);
8001762: 4803 ldr r0, [pc, #12] ; (8001770 <MX_TIM8_Init+0x14c>)
8001764: f002 fe86 bl 8004474 <HAL_TIM_MspPostInit>
}
8001768: bf00 nop
800176a: 3768 adds r7, #104 ; 0x68
800176c: 46bd mov sp, r7
800176e: bd80 pop {r7, pc}
8001770: 200088e0 .word 0x200088e0
8001774: 40010400 .word 0x40010400
08001778 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8001778: b580 push {r7, lr}
800177a: b088 sub sp, #32
800177c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
800177e: 1d3b adds r3, r7, #4
8001780: 2200 movs r2, #0
8001782: 601a str r2, [r3, #0]
8001784: 605a str r2, [r3, #4]
8001786: 609a str r2, [r3, #8]
8001788: 60da str r2, [r3, #12]
800178a: 611a str r2, [r3, #16]
800178c: 615a str r2, [r3, #20]
800178e: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8001790: 4b1e ldr r3, [pc, #120] ; (800180c <MX_FMC_Init+0x94>)
8001792: 4a1f ldr r2, [pc, #124] ; (8001810 <MX_FMC_Init+0x98>)
8001794: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
8001796: 4b1d ldr r3, [pc, #116] ; (800180c <MX_FMC_Init+0x94>)
8001798: 2200 movs r2, #0
800179a: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
800179c: 4b1b ldr r3, [pc, #108] ; (800180c <MX_FMC_Init+0x94>)
800179e: 2200 movs r2, #0
80017a0: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
80017a2: 4b1a ldr r3, [pc, #104] ; (800180c <MX_FMC_Init+0x94>)
80017a4: 2204 movs r2, #4
80017a6: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
80017a8: 4b18 ldr r3, [pc, #96] ; (800180c <MX_FMC_Init+0x94>)
80017aa: 2210 movs r2, #16
80017ac: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
80017ae: 4b17 ldr r3, [pc, #92] ; (800180c <MX_FMC_Init+0x94>)
80017b0: 2240 movs r2, #64 ; 0x40
80017b2: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
80017b4: 4b15 ldr r3, [pc, #84] ; (800180c <MX_FMC_Init+0x94>)
80017b6: 2280 movs r2, #128 ; 0x80
80017b8: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
80017ba: 4b14 ldr r3, [pc, #80] ; (800180c <MX_FMC_Init+0x94>)
80017bc: 2200 movs r2, #0
80017be: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
80017c0: 4b12 ldr r3, [pc, #72] ; (800180c <MX_FMC_Init+0x94>)
80017c2: 2200 movs r2, #0
80017c4: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
80017c6: 4b11 ldr r3, [pc, #68] ; (800180c <MX_FMC_Init+0x94>)
80017c8: 2200 movs r2, #0
80017ca: 625a str r2, [r3, #36] ; 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
80017cc: 4b0f ldr r3, [pc, #60] ; (800180c <MX_FMC_Init+0x94>)
80017ce: 2200 movs r2, #0
80017d0: 629a str r2, [r3, #40] ; 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 16;
80017d2: 2310 movs r3, #16
80017d4: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 16;
80017d6: 2310 movs r3, #16
80017d8: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 16;
80017da: 2310 movs r3, #16
80017dc: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 16;
80017de: 2310 movs r3, #16
80017e0: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 16;
80017e2: 2310 movs r3, #16
80017e4: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 16;
80017e6: 2310 movs r3, #16
80017e8: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 16;
80017ea: 2310 movs r3, #16
80017ec: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
80017ee: 1d3b adds r3, r7, #4
80017f0: 4619 mov r1, r3
80017f2: 4806 ldr r0, [pc, #24] ; (800180c <MX_FMC_Init+0x94>)
80017f4: f008 f8ea bl 80099cc <HAL_SDRAM_Init>
80017f8: 4603 mov r3, r0
80017fa: 2b00 cmp r3, #0
80017fc: d001 beq.n 8001802 <MX_FMC_Init+0x8a>
{
Error_Handler( );
80017fe: f000 ff15 bl 800262c <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8001802: bf00 nop
8001804: 3720 adds r7, #32
8001806: 46bd mov sp, r7
8001808: bd80 pop {r7, pc}
800180a: bf00 nop
800180c: 20008bfc .word 0x20008bfc
8001810: a0000140 .word 0xa0000140
08001814 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001814: b580 push {r7, lr}
8001816: b090 sub sp, #64 ; 0x40
8001818: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800181a: f107 032c add.w r3, r7, #44 ; 0x2c
800181e: 2200 movs r2, #0
8001820: 601a str r2, [r3, #0]
8001822: 605a str r2, [r3, #4]
8001824: 609a str r2, [r3, #8]
8001826: 60da str r2, [r3, #12]
8001828: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
800182a: 4baf ldr r3, [pc, #700] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800182c: 6b1b ldr r3, [r3, #48] ; 0x30
800182e: 4aae ldr r2, [pc, #696] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001830: f043 0310 orr.w r3, r3, #16
8001834: 6313 str r3, [r2, #48] ; 0x30
8001836: 4bac ldr r3, [pc, #688] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001838: 6b1b ldr r3, [r3, #48] ; 0x30
800183a: f003 0310 and.w r3, r3, #16
800183e: 62bb str r3, [r7, #40] ; 0x28
8001840: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_GPIOG_CLK_ENABLE();
8001842: 4ba9 ldr r3, [pc, #676] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001844: 6b1b ldr r3, [r3, #48] ; 0x30
8001846: 4aa8 ldr r2, [pc, #672] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001848: f043 0340 orr.w r3, r3, #64 ; 0x40
800184c: 6313 str r3, [r2, #48] ; 0x30
800184e: 4ba6 ldr r3, [pc, #664] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001850: 6b1b ldr r3, [r3, #48] ; 0x30
8001852: f003 0340 and.w r3, r3, #64 ; 0x40
8001856: 627b str r3, [r7, #36] ; 0x24
8001858: 6a7b ldr r3, [r7, #36] ; 0x24
__HAL_RCC_GPIOB_CLK_ENABLE();
800185a: 4ba3 ldr r3, [pc, #652] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800185c: 6b1b ldr r3, [r3, #48] ; 0x30
800185e: 4aa2 ldr r2, [pc, #648] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001860: f043 0302 orr.w r3, r3, #2
8001864: 6313 str r3, [r2, #48] ; 0x30
8001866: 4ba0 ldr r3, [pc, #640] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001868: 6b1b ldr r3, [r3, #48] ; 0x30
800186a: f003 0302 and.w r3, r3, #2
800186e: 623b str r3, [r7, #32]
8001870: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001872: 4b9d ldr r3, [pc, #628] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001874: 6b1b ldr r3, [r3, #48] ; 0x30
8001876: 4a9c ldr r2, [pc, #624] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001878: f043 0301 orr.w r3, r3, #1
800187c: 6313 str r3, [r2, #48] ; 0x30
800187e: 4b9a ldr r3, [pc, #616] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001880: 6b1b ldr r3, [r3, #48] ; 0x30
8001882: f003 0301 and.w r3, r3, #1
8001886: 61fb str r3, [r7, #28]
8001888: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
800188a: 4b97 ldr r3, [pc, #604] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800188c: 6b1b ldr r3, [r3, #48] ; 0x30
800188e: 4a96 ldr r2, [pc, #600] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001890: f443 7300 orr.w r3, r3, #512 ; 0x200
8001894: 6313 str r3, [r2, #48] ; 0x30
8001896: 4b94 ldr r3, [pc, #592] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001898: 6b1b ldr r3, [r3, #48] ; 0x30
800189a: f403 7300 and.w r3, r3, #512 ; 0x200
800189e: 61bb str r3, [r7, #24]
80018a0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
80018a2: 4b91 ldr r3, [pc, #580] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018a4: 6b1b ldr r3, [r3, #48] ; 0x30
80018a6: 4a90 ldr r2, [pc, #576] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018a8: f043 0308 orr.w r3, r3, #8
80018ac: 6313 str r3, [r2, #48] ; 0x30
80018ae: 4b8e ldr r3, [pc, #568] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018b0: 6b1b ldr r3, [r3, #48] ; 0x30
80018b2: f003 0308 and.w r3, r3, #8
80018b6: 617b str r3, [r7, #20]
80018b8: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOI_CLK_ENABLE();
80018ba: 4b8b ldr r3, [pc, #556] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018bc: 6b1b ldr r3, [r3, #48] ; 0x30
80018be: 4a8a ldr r2, [pc, #552] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018c0: f443 7380 orr.w r3, r3, #256 ; 0x100
80018c4: 6313 str r3, [r2, #48] ; 0x30
80018c6: 4b88 ldr r3, [pc, #544] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018c8: 6b1b ldr r3, [r3, #48] ; 0x30
80018ca: f403 7380 and.w r3, r3, #256 ; 0x100
80018ce: 613b str r3, [r7, #16]
80018d0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOK_CLK_ENABLE();
80018d2: 4b85 ldr r3, [pc, #532] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018d4: 6b1b ldr r3, [r3, #48] ; 0x30
80018d6: 4a84 ldr r2, [pc, #528] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018d8: f443 6380 orr.w r3, r3, #1024 ; 0x400
80018dc: 6313 str r3, [r2, #48] ; 0x30
80018de: 4b82 ldr r3, [pc, #520] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018e0: 6b1b ldr r3, [r3, #48] ; 0x30
80018e2: f403 6380 and.w r3, r3, #1024 ; 0x400
80018e6: 60fb str r3, [r7, #12]
80018e8: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
80018ea: 4b7f ldr r3, [pc, #508] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018ec: 6b1b ldr r3, [r3, #48] ; 0x30
80018ee: 4a7e ldr r2, [pc, #504] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018f0: f043 0304 orr.w r3, r3, #4
80018f4: 6313 str r3, [r2, #48] ; 0x30
80018f6: 4b7c ldr r3, [pc, #496] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
80018f8: 6b1b ldr r3, [r3, #48] ; 0x30
80018fa: f003 0304 and.w r3, r3, #4
80018fe: 60bb str r3, [r7, #8]
8001900: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOF_CLK_ENABLE();
8001902: 4b79 ldr r3, [pc, #484] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001904: 6b1b ldr r3, [r3, #48] ; 0x30
8001906: 4a78 ldr r2, [pc, #480] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001908: f043 0320 orr.w r3, r3, #32
800190c: 6313 str r3, [r2, #48] ; 0x30
800190e: 4b76 ldr r3, [pc, #472] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001910: 6b1b ldr r3, [r3, #48] ; 0x30
8001912: f003 0320 and.w r3, r3, #32
8001916: 607b str r3, [r7, #4]
8001918: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOH_CLK_ENABLE();
800191a: 4b73 ldr r3, [pc, #460] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
800191c: 6b1b ldr r3, [r3, #48] ; 0x30
800191e: 4a72 ldr r2, [pc, #456] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001920: f043 0380 orr.w r3, r3, #128 ; 0x80
8001924: 6313 str r3, [r2, #48] ; 0x30
8001926: 4b70 ldr r3, [pc, #448] ; (8001ae8 <MX_GPIO_Init+0x2d4>)
8001928: 6b1b ldr r3, [r3, #48] ; 0x30
800192a: f003 0380 and.w r3, r3, #128 ; 0x80
800192e: 603b str r3, [r7, #0]
8001930: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET);
8001932: 2200 movs r2, #0
8001934: 2160 movs r1, #96 ; 0x60
8001936: 486d ldr r0, [pc, #436] ; (8001aec <MX_GPIO_Init+0x2d8>)
8001938: f005 fe4c bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET);
800193c: 2201 movs r2, #1
800193e: 2120 movs r1, #32
8001940: 486b ldr r0, [pc, #428] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001942: f005 fe47 bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET);
8001946: 2200 movs r2, #0
8001948: 2108 movs r1, #8
800194a: 4869 ldr r0, [pc, #420] ; (8001af0 <MX_GPIO_Init+0x2dc>)
800194c: f005 fe42 bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
8001950: 2200 movs r2, #0
8001952: 2108 movs r1, #8
8001954: 4867 ldr r0, [pc, #412] ; (8001af4 <MX_GPIO_Init+0x2e0>)
8001956: f005 fe3d bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET);
800195a: 2201 movs r2, #1
800195c: 2108 movs r1, #8
800195e: 4866 ldr r0, [pc, #408] ; (8001af8 <MX_GPIO_Init+0x2e4>)
8001960: f005 fe38 bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET);
8001964: 2201 movs r2, #1
8001966: f44f 5180 mov.w r1, #4096 ; 0x1000
800196a: 4862 ldr r0, [pc, #392] ; (8001af4 <MX_GPIO_Init+0x2e0>)
800196c: f005 fe32 bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001970: 2200 movs r2, #0
8001972: f645 6140 movw r1, #24128 ; 0x5e40
8001976: 4861 ldr r0, [pc, #388] ; (8001afc <MX_GPIO_Init+0x2e8>)
8001978: f005 fe2c bl 80075d4 <HAL_GPIO_WritePin>
|LED2_Pin|LED18_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET);
800197c: 2200 movs r2, #0
800197e: 2108 movs r1, #8
8001980: 485f ldr r0, [pc, #380] ; (8001b00 <MX_GPIO_Init+0x2ec>)
8001982: f005 fe27 bl 80075d4 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PE3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001986: 2308 movs r3, #8
8001988: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800198a: 2300 movs r3, #0
800198c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
800198e: 2300 movs r3, #0
8001990: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001992: f107 032c add.w r3, r7, #44 ; 0x2c
8001996: 4619 mov r1, r3
8001998: 4854 ldr r0, [pc, #336] ; (8001aec <MX_GPIO_Init+0x2d8>)
800199a: f005 fc71 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : ARDUINO_SCL_D15_Pin ARDUINO_SDA_D14_Pin */
GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin;
800199e: f44f 7340 mov.w r3, #768 ; 0x300
80019a2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
80019a4: 2312 movs r3, #18
80019a6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
80019a8: 2301 movs r3, #1
80019aa: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80019ac: 2300 movs r3, #0
80019ae: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
80019b0: 2304 movs r3, #4
80019b2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019b4: f107 032c add.w r3, r7, #44 ; 0x2c
80019b8: 4619 mov r1, r3
80019ba: 4852 ldr r0, [pc, #328] ; (8001b04 <MX_GPIO_Init+0x2f0>)
80019bc: f005 fc60 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin
ULPI_D1_Pin ULPI_D4_Pin */
GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin
80019c0: f643 0323 movw r3, #14371 ; 0x3823
80019c4: 62fb str r3, [r7, #44] ; 0x2c
|ULPI_D1_Pin|ULPI_D4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80019c6: 2302 movs r3, #2
80019c8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019ca: 2300 movs r3, #0
80019cc: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80019ce: 2303 movs r3, #3
80019d0: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
80019d2: 230a movs r3, #10
80019d4: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80019d6: f107 032c add.w r3, r7, #44 ; 0x2c
80019da: 4619 mov r1, r3
80019dc: 4849 ldr r0, [pc, #292] ; (8001b04 <MX_GPIO_Init+0x2f0>)
80019de: f005 fc4f bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : BP2_Pin */
GPIO_InitStruct.Pin = BP2_Pin;
80019e2: f44f 4300 mov.w r3, #32768 ; 0x8000
80019e6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80019e8: 2300 movs r3, #0
80019ea: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
80019ec: 2300 movs r3, #0
80019ee: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(BP2_GPIO_Port, &GPIO_InitStruct);
80019f0: f107 032c add.w r3, r7, #44 ; 0x2c
80019f4: 4619 mov r1, r3
80019f6: 4844 ldr r0, [pc, #272] ; (8001b08 <MX_GPIO_Init+0x2f4>)
80019f8: f005 fc42 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : LED14_Pin LED15_Pin */
GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin;
80019fc: 2360 movs r3, #96 ; 0x60
80019fe: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a00: 2301 movs r3, #1
8001a02: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a04: 2300 movs r3, #0
8001a06: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a08: 2300 movs r3, #0
8001a0a: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001a0c: f107 032c add.w r3, r7, #44 ; 0x2c
8001a10: 4619 mov r1, r3
8001a12: 4836 ldr r0, [pc, #216] ; (8001aec <MX_GPIO_Init+0x2d8>)
8001a14: f005 fc34 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_RX_Pin */
GPIO_InitStruct.Pin = VCP_RX_Pin;
8001a18: 2380 movs r3, #128 ; 0x80
8001a1a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a1c: 2302 movs r3, #2
8001a1e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a20: 2300 movs r3, #0
8001a22: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a24: 2300 movs r3, #0
8001a26: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001a28: 2307 movs r3, #7
8001a2a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
8001a2c: f107 032c add.w r3, r7, #44 ; 0x2c
8001a30: 4619 mov r1, r3
8001a32: 4834 ldr r0, [pc, #208] ; (8001b04 <MX_GPIO_Init+0x2f0>)
8001a34: f005 fc24 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_VBUS_Pin */
GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin;
8001a38: f44f 5380 mov.w r3, #4096 ; 0x1000
8001a3c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001a3e: 2300 movs r3, #0
8001a40: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a42: 2300 movs r3, #0
8001a44: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
8001a46: f107 032c add.w r3, r7, #44 ; 0x2c
8001a4a: 4619 mov r1, r3
8001a4c: 482f ldr r0, [pc, #188] ; (8001b0c <MX_GPIO_Init+0x2f8>)
8001a4e: f005 fc17 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : Audio_INT_Pin */
GPIO_InitStruct.Pin = Audio_INT_Pin;
8001a52: 2340 movs r3, #64 ; 0x40
8001a54: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001a56: 4b2e ldr r3, [pc, #184] ; (8001b10 <MX_GPIO_Init+0x2fc>)
8001a58: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a5a: 2300 movs r3, #0
8001a5c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct);
8001a5e: f107 032c add.w r3, r7, #44 ; 0x2c
8001a62: 4619 mov r1, r3
8001a64: 4822 ldr r0, [pc, #136] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001a66: f005 fc0b bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */
GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin;
8001a6a: 2328 movs r3, #40 ; 0x28
8001a6c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a6e: 2301 movs r3, #1
8001a70: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a72: 2300 movs r3, #0
8001a74: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a76: 2300 movs r3, #0
8001a78: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001a7a: f107 032c add.w r3, r7, #44 ; 0x2c
8001a7e: 4619 mov r1, r3
8001a80: 481b ldr r0, [pc, #108] ; (8001af0 <MX_GPIO_Init+0x2dc>)
8001a82: f005 fbfd bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */
GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin;
8001a86: f241 0308 movw r3, #4104 ; 0x1008
8001a8a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001a8c: 2301 movs r3, #1
8001a8e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a90: 2300 movs r3, #0
8001a92: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a94: 2300 movs r3, #0
8001a96: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001a98: f107 032c add.w r3, r7, #44 ; 0x2c
8001a9c: 4619 mov r1, r3
8001a9e: 4815 ldr r0, [pc, #84] ; (8001af4 <MX_GPIO_Init+0x2e0>)
8001aa0: f005 fbee bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : uSD_Detect_Pin */
GPIO_InitStruct.Pin = uSD_Detect_Pin;
8001aa4: f44f 5300 mov.w r3, #8192 ; 0x2000
8001aa8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001aaa: 2300 movs r3, #0
8001aac: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001aae: 2300 movs r3, #0
8001ab0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
8001ab2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ab6: 4619 mov r1, r3
8001ab8: 4816 ldr r0, [pc, #88] ; (8001b14 <MX_GPIO_Init+0x300>)
8001aba: f005 fbe1 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_CTRL_Pin */
GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
8001abe: 2308 movs r3, #8
8001ac0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001ac2: 2301 movs r3, #1
8001ac4: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ac6: 2300 movs r3, #0
8001ac8: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001aca: 2300 movs r3, #0
8001acc: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
8001ace: f107 032c add.w r3, r7, #44 ; 0x2c
8001ad2: 4619 mov r1, r3
8001ad4: 4808 ldr r0, [pc, #32] ; (8001af8 <MX_GPIO_Init+0x2e4>)
8001ad6: f005 fbd3 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OverCurrent_Pin */
GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin;
8001ada: 2310 movs r3, #16
8001adc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001ade: 2300 movs r3, #0
8001ae0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ae2: 2300 movs r3, #0
8001ae4: 637b str r3, [r7, #52] ; 0x34
8001ae6: e017 b.n 8001b18 <MX_GPIO_Init+0x304>
8001ae8: 40023800 .word 0x40023800
8001aec: 40021000 .word 0x40021000
8001af0: 40020c00 .word 0x40020c00
8001af4: 40022000 .word 0x40022000
8001af8: 40022800 .word 0x40022800
8001afc: 40021c00 .word 0x40021c00
8001b00: 40021800 .word 0x40021800
8001b04: 40020400 .word 0x40020400
8001b08: 40020000 .word 0x40020000
8001b0c: 40022400 .word 0x40022400
8001b10: 10120000 .word 0x10120000
8001b14: 40020800 .word 0x40020800
HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8001b18: f107 032c add.w r3, r7, #44 ; 0x2c
8001b1c: 4619 mov r1, r3
8001b1e: 486f ldr r0, [pc, #444] ; (8001cdc <MX_GPIO_Init+0x4c8>)
8001b20: f005 fbae bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : TP3_Pin NC2_Pin */
GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin;
8001b24: f248 0304 movw r3, #32772 ; 0x8004
8001b28: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001b2a: 2300 movs r3, #0
8001b2c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b2e: 2300 movs r3, #0
8001b30: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001b32: f107 032c add.w r3, r7, #44 ; 0x2c
8001b36: 4619 mov r1, r3
8001b38: 4869 ldr r0, [pc, #420] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001b3a: f005 fba1 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
LED2_Pin LED18_Pin */
GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001b3e: f645 6340 movw r3, #24128 ; 0x5e40
8001b42: 62fb str r3, [r7, #44] ; 0x2c
|LED2_Pin|LED18_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001b44: 2301 movs r3, #1
8001b46: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b48: 2300 movs r3, #0
8001b4a: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b4c: 2300 movs r3, #0
8001b4e: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001b50: f107 032c add.w r3, r7, #44 ; 0x2c
8001b54: 4619 mov r1, r3
8001b56: 4862 ldr r0, [pc, #392] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001b58: f005 fb92 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : VCP_TX_Pin */
GPIO_InitStruct.Pin = VCP_TX_Pin;
8001b5c: f44f 7300 mov.w r3, #512 ; 0x200
8001b60: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b62: 2302 movs r3, #2
8001b64: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b66: 2300 movs r3, #0
8001b68: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b6a: 2300 movs r3, #0
8001b6c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001b6e: 2307 movs r3, #7
8001b70: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
8001b72: f107 032c add.w r3, r7, #44 ; 0x2c
8001b76: 4619 mov r1, r3
8001b78: 485a ldr r0, [pc, #360] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001b7a: f005 fb81 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : BP_interrupt1_Pin */
GPIO_InitStruct.Pin = BP_interrupt1_Pin;
8001b7e: f44f 6300 mov.w r3, #2048 ; 0x800
8001b82: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001b84: 4b58 ldr r3, [pc, #352] ; (8001ce8 <MX_GPIO_Init+0x4d4>)
8001b86: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b88: 2300 movs r3, #0
8001b8a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(BP_interrupt1_GPIO_Port, &GPIO_InitStruct);
8001b8c: f107 032c add.w r3, r7, #44 ; 0x2c
8001b90: 4619 mov r1, r3
8001b92: 4856 ldr r0, [pc, #344] ; (8001cec <MX_GPIO_Init+0x4d8>)
8001b94: f005 fb74 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : PB_Pin */
GPIO_InitStruct.Pin = PB_Pin;
8001b98: f44f 7380 mov.w r3, #256 ; 0x100
8001b9c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
8001b9e: 4b52 ldr r3, [pc, #328] ; (8001ce8 <MX_GPIO_Init+0x4d4>)
8001ba0: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ba2: 2300 movs r3, #0
8001ba4: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(PB_GPIO_Port, &GPIO_InitStruct);
8001ba6: f107 032c add.w r3, r7, #44 ; 0x2c
8001baa: 4619 mov r1, r3
8001bac: 484d ldr r0, [pc, #308] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001bae: f005 fb67 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_INT_Pin */
GPIO_InitStruct.Pin = LCD_INT_Pin;
8001bb2: f44f 5300 mov.w r3, #8192 ; 0x2000
8001bb6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001bb8: 4b4d ldr r3, [pc, #308] ; (8001cf0 <MX_GPIO_Init+0x4dc>)
8001bba: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bbc: 2300 movs r3, #0
8001bbe: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
8001bc0: f107 032c add.w r3, r7, #44 ; 0x2c
8001bc4: 4619 mov r1, r3
8001bc6: 4849 ldr r0, [pc, #292] ; (8001cec <MX_GPIO_Init+0x4d8>)
8001bc8: f005 fb5a bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : PC7 PC6 */
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
8001bcc: 23c0 movs r3, #192 ; 0xc0
8001bce: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bd0: 2302 movs r3, #2
8001bd2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bd4: 2300 movs r3, #0
8001bd6: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bd8: 2303 movs r3, #3
8001bda: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001bdc: 2308 movs r3, #8
8001bde: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001be0: f107 032c add.w r3, r7, #44 ; 0x2c
8001be4: 4619 mov r1, r3
8001be6: 4843 ldr r0, [pc, #268] ; (8001cf4 <MX_GPIO_Init+0x4e0>)
8001be8: f005 fb4a bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : ULPI_NXT_Pin */
GPIO_InitStruct.Pin = ULPI_NXT_Pin;
8001bec: 2310 movs r3, #16
8001bee: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001bf0: 2302 movs r3, #2
8001bf2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bf4: 2300 movs r3, #0
8001bf6: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001bf8: 2303 movs r3, #3
8001bfa: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001bfc: 230a movs r3, #10
8001bfe: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct);
8001c00: f107 032c add.w r3, r7, #44 ; 0x2c
8001c04: 4619 mov r1, r3
8001c06: 4836 ldr r0, [pc, #216] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001c08: f005 fb3a bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */
GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin;
8001c0c: 2384 movs r3, #132 ; 0x84
8001c0e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001c10: 2300 movs r3, #0
8001c12: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c14: 2300 movs r3, #0
8001c16: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001c18: f107 032c add.w r3, r7, #44 ; 0x2c
8001c1c: 4619 mov r1, r3
8001c1e: 4836 ldr r0, [pc, #216] ; (8001cf8 <MX_GPIO_Init+0x4e4>)
8001c20: f005 fb2e bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : PF7 */
GPIO_InitStruct.Pin = GPIO_PIN_7;
8001c24: 2380 movs r3, #128 ; 0x80
8001c26: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c28: 2302 movs r3, #2
8001c2a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c2c: 2300 movs r3, #0
8001c2e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c30: 2303 movs r3, #3
8001c32: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
8001c34: 2308 movs r3, #8
8001c36: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8001c38: f107 032c add.w r3, r7, #44 ; 0x2c
8001c3c: 4619 mov r1, r3
8001c3e: 482f ldr r0, [pc, #188] ; (8001cfc <MX_GPIO_Init+0x4e8>)
8001c40: f005 fb1e bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */
GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin;
8001c44: 2305 movs r3, #5
8001c46: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c48: 2302 movs r3, #2
8001c4a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c4c: 2300 movs r3, #0
8001c4e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c50: 2303 movs r3, #3
8001c52: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001c54: 230a movs r3, #10
8001c56: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001c58: f107 032c add.w r3, r7, #44 ; 0x2c
8001c5c: 4619 mov r1, r3
8001c5e: 4825 ldr r0, [pc, #148] ; (8001cf4 <MX_GPIO_Init+0x4e0>)
8001c60: f005 fb0e bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pin : EXT_RST_Pin */
GPIO_InitStruct.Pin = EXT_RST_Pin;
8001c64: 2308 movs r3, #8
8001c66: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001c68: 2301 movs r3, #1
8001c6a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c6c: 2300 movs r3, #0
8001c6e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c70: 2300 movs r3, #0
8001c72: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct);
8001c74: f107 032c add.w r3, r7, #44 ; 0x2c
8001c78: 4619 mov r1, r3
8001c7a: 481f ldr r0, [pc, #124] ; (8001cf8 <MX_GPIO_Init+0x4e4>)
8001c7c: f005 fb00 bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : LCD_SCL_Pin LCD_SDA_Pin */
GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin;
8001c80: f44f 73c0 mov.w r3, #384 ; 0x180
8001c84: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8001c86: 2312 movs r3, #18
8001c88: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_PULLUP;
8001c8a: 2301 movs r3, #1
8001c8c: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c8e: 2303 movs r3, #3
8001c90: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8001c92: 2304 movs r3, #4
8001c94: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001c96: f107 032c add.w r3, r7, #44 ; 0x2c
8001c9a: 4619 mov r1, r3
8001c9c: 4810 ldr r0, [pc, #64] ; (8001ce0 <MX_GPIO_Init+0x4cc>)
8001c9e: f005 faef bl 8007280 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */
GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin;
8001ca2: 2328 movs r3, #40 ; 0x28
8001ca4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001ca6: 2302 movs r3, #2
8001ca8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001caa: 2300 movs r3, #0
8001cac: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001cae: 2303 movs r3, #3
8001cb0: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001cb2: 230a movs r3, #10
8001cb4: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001cb6: f107 032c add.w r3, r7, #44 ; 0x2c
8001cba: 4619 mov r1, r3
8001cbc: 4809 ldr r0, [pc, #36] ; (8001ce4 <MX_GPIO_Init+0x4d0>)
8001cbe: f005 fadf bl 8007280 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0);
8001cc2: 2200 movs r2, #0
8001cc4: 2105 movs r1, #5
8001cc6: 2017 movs r0, #23
8001cc8: f003 fb2a bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);
8001ccc: 2017 movs r0, #23
8001cce: f003 fb43 bl 8005358 <HAL_NVIC_EnableIRQ>
}
8001cd2: bf00 nop
8001cd4: 3740 adds r7, #64 ; 0x40
8001cd6: 46bd mov sp, r7
8001cd8: bd80 pop {r7, pc}
8001cda: bf00 nop
8001cdc: 40020c00 .word 0x40020c00
8001ce0: 40021c00 .word 0x40021c00
8001ce4: 40020000 .word 0x40020000
8001ce8: 10110000 .word 0x10110000
8001cec: 40022000 .word 0x40022000
8001cf0: 10120000 .word 0x10120000
8001cf4: 40020800 .word 0x40020800
8001cf8: 40021800 .word 0x40021800
8001cfc: 40021400 .word 0x40021400
08001d00 <HAL_GPIO_EXTI_Callback>:
/* USER CODE BEGIN 4 */
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8001d00: b580 push {r7, lr}
8001d02: b088 sub sp, #32
8001d04: af00 add r7, sp, #0
8001d06: 4603 mov r3, r0
8001d08: 80fb strh r3, [r7, #6]
/* Prevent unused argument(s) compilation warning */
BaseType_t pxHigherPriorityTaskWoken = pdTRUE;
8001d0a: 2301 movs r3, #1
8001d0c: 61fb str r3, [r7, #28]
// &pxHigherPriorityTaskWoken =
struct Missile missile = {joueur.x, joueur.y, 1, 0, 1, LCD_COLOR_LIGHTBLUE, 2, 1};
8001d0e: 4b13 ldr r3, [pc, #76] ; (8001d5c <HAL_GPIO_EXTI_Callback+0x5c>)
8001d10: 681b ldr r3, [r3, #0]
8001d12: b29b uxth r3, r3
8001d14: 81bb strh r3, [r7, #12]
8001d16: 4b11 ldr r3, [pc, #68] ; (8001d5c <HAL_GPIO_EXTI_Callback+0x5c>)
8001d18: 685b ldr r3, [r3, #4]
8001d1a: b29b uxth r3, r3
8001d1c: 81fb strh r3, [r7, #14]
8001d1e: 2301 movs r3, #1
8001d20: 743b strb r3, [r7, #16]
8001d22: 2300 movs r3, #0
8001d24: 747b strb r3, [r7, #17]
8001d26: 2301 movs r3, #1
8001d28: 74bb strb r3, [r7, #18]
8001d2a: 4b0d ldr r3, [pc, #52] ; (8001d60 <HAL_GPIO_EXTI_Callback+0x60>)
8001d2c: 617b str r3, [r7, #20]
8001d2e: 2302 movs r3, #2
8001d30: 763b strb r3, [r7, #24]
8001d32: 2301 movs r3, #1
8001d34: 767b strb r3, [r7, #25]
HAL_GPIO_TogglePin(LED13_GPIO_Port, LED13_Pin);
8001d36: f44f 4180 mov.w r1, #16384 ; 0x4000
8001d3a: 480a ldr r0, [pc, #40] ; (8001d64 <HAL_GPIO_EXTI_Callback+0x64>)
8001d3c: f005 fc63 bl 8007606 <HAL_GPIO_TogglePin>
xQueueSendFromISR(Queue_NHandle, &missile, &pxHigherPriorityTaskWoken);
8001d40: 4b09 ldr r3, [pc, #36] ; (8001d68 <HAL_GPIO_EXTI_Callback+0x68>)
8001d42: 6818 ldr r0, [r3, #0]
8001d44: f107 021c add.w r2, r7, #28
8001d48: f107 010c add.w r1, r7, #12
8001d4c: 2300 movs r3, #0
8001d4e: f00a fcaf bl 800c6b0 <xQueueGenericSendFromISR>
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
8001d52: bf00 nop
8001d54: 3720 adds r7, #32
8001d56: 46bd mov sp, r7
8001d58: bd80 pop {r7, pc}
8001d5a: bf00 nop
8001d5c: 20000028 .word 0x20000028
8001d60: ff8080ff .word 0xff8080ff
8001d64: 40021c00 .word 0x40021c00
8001d68: 20008b04 .word 0x20008b04
08001d6c <f_GameMaster>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_GameMaster */
void f_GameMaster(void const * argument)
{
8001d6c: b580 push {r7, lr}
8001d6e: b086 sub sp, #24
8001d70: af00 add r7, sp, #0
8001d72: 6078 str r0, [r7, #4]
/* init code for LWIP */
MX_LWIP_Init();
8001d74: f009 f990 bl 800b098 <MX_LWIP_Init>
/* USER CODE BEGIN 5 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8001d78: 230a movs r3, #10
8001d7a: 617b str r3, [r7, #20]
// Si la variable end est à 1, le jeu s'arrete.
uint8_t end = 0;
8001d7c: 2300 movs r3, #0
8001d7e: 73fb strb r3, [r7, #15]
/* Infinite loop */
for (;;)
{
xQueueReceive(Queue_FHandle, &end, 0);
8001d80: 4b1b ldr r3, [pc, #108] ; (8001df0 <f_GameMaster+0x84>)
8001d82: 681b ldr r3, [r3, #0]
8001d84: f107 010f add.w r1, r7, #15
8001d88: 2200 movs r2, #0
8001d8a: 4618 mov r0, r3
8001d8c: f00a fdbe bl 800c90c <xQueueReceive>
if (end == 1){
8001d90: 7bfb ldrb r3, [r7, #15]
8001d92: 2b01 cmp r3, #1
8001d94: d10e bne.n 8001db4 <f_GameMaster+0x48>
vTaskDelete(Block_EnemieHandle);
8001d96: 4b17 ldr r3, [pc, #92] ; (8001df4 <f_GameMaster+0x88>)
8001d98: 681b ldr r3, [r3, #0]
8001d9a: 4618 mov r0, r3
8001d9c: f00b faf6 bl 800d38c <vTaskDelete>
vTaskDelete(ProjectileHandle);
8001da0: 4b15 ldr r3, [pc, #84] ; (8001df8 <f_GameMaster+0x8c>)
8001da2: 681b ldr r3, [r3, #0]
8001da4: 4618 mov r0, r3
8001da6: f00b faf1 bl 800d38c <vTaskDelete>
vTaskDelete(Joueur_1Handle);
8001daa: 4b14 ldr r3, [pc, #80] ; (8001dfc <f_GameMaster+0x90>)
8001dac: 681b ldr r3, [r3, #0]
8001dae: 4618 mov r0, r3
8001db0: f00b faec bl 800d38c <vTaskDelete>
//TODO L'affichage de l'écran de fin et des scores
}
if (end == 0){
8001db4: 7bfb ldrb r3, [r7, #15]
8001db6: 2b00 cmp r3, #0
8001db8: d112 bne.n 8001de0 <f_GameMaster+0x74>
if (waves_left == 0){
8001dba: 4b11 ldr r3, [pc, #68] ; (8001e00 <f_GameMaster+0x94>)
8001dbc: 781b ldrb r3, [r3, #0]
8001dbe: 2b00 cmp r3, #0
8001dc0: d10e bne.n 8001de0 <f_GameMaster+0x74>
vTaskDelete(Block_EnemieHandle);
8001dc2: 4b0c ldr r3, [pc, #48] ; (8001df4 <f_GameMaster+0x88>)
8001dc4: 681b ldr r3, [r3, #0]
8001dc6: 4618 mov r0, r3
8001dc8: f00b fae0 bl 800d38c <vTaskDelete>
vTaskDelete(ProjectileHandle);
8001dcc: 4b0a ldr r3, [pc, #40] ; (8001df8 <f_GameMaster+0x8c>)
8001dce: 681b ldr r3, [r3, #0]
8001dd0: 4618 mov r0, r3
8001dd2: f00b fadb bl 800d38c <vTaskDelete>
vTaskDelete(Joueur_1Handle);
8001dd6: 4b09 ldr r3, [pc, #36] ; (8001dfc <f_GameMaster+0x90>)
8001dd8: 681b ldr r3, [r3, #0]
8001dda: 4618 mov r0, r3
8001ddc: f00b fad6 bl 800d38c <vTaskDelete>
}
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8001de0: f107 0310 add.w r3, r7, #16
8001de4: 6979 ldr r1, [r7, #20]
8001de6: 4618 mov r0, r3
8001de8: f00b fb60 bl 800d4ac <vTaskDelayUntil>
xQueueReceive(Queue_FHandle, &end, 0);
8001dec: e7c8 b.n 8001d80 <f_GameMaster+0x14>
8001dee: bf00 nop
8001df0: 20008b08 .word 0x20008b08
8001df4: 20008c30 .word 0x20008c30
8001df8: 20008b20 .word 0x20008b20
8001dfc: 20008948 .word 0x20008948
8001e00: 20000048 .word 0x20000048
08001e04 <f_Joueur_1>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_Joueur_1 */
void f_Joueur_1(void const * argument)
{
8001e04: b580 push {r7, lr}
8001e06: b096 sub sp, #88 ; 0x58
8001e08: af00 add r7, sp, #0
8001e0a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN f_Joueur_1 */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8001e0c: 230a movs r3, #10
8001e0e: 657b str r3, [r7, #84] ; 0x54
uint16_t Width = 20;
8001e10: 2314 movs r3, #20
8001e12: f8a7 3052 strh.w r3, [r7, #82] ; 0x52
uint16_t Height = 20;
8001e16: 2314 movs r3, #20
8001e18: f8a7 3050 strh.w r3, [r7, #80] ; 0x50
uint32_t joystick_h, joystick_v;
uint8_t stop = 1;
8001e1c: 2301 movs r3, #1
8001e1e: f887 303b strb.w r3, [r7, #59] ; 0x3b
struct Missile missile;
ADC_ChannelConfTypeDef sConfig3 = {0};
8001e22: f107 0318 add.w r3, r7, #24
8001e26: 2200 movs r2, #0
8001e28: 601a str r2, [r3, #0]
8001e2a: 605a str r2, [r3, #4]
8001e2c: 609a str r2, [r3, #8]
8001e2e: 60da str r2, [r3, #12]
sConfig3.Rank = ADC_REGULAR_RANK_1;
8001e30: 2301 movs r3, #1
8001e32: 61fb str r3, [r7, #28]
sConfig3.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001e34: 2300 movs r3, #0
8001e36: 623b str r3, [r7, #32]
sConfig3.Channel = ADC_CHANNEL_8;
8001e38: 2308 movs r3, #8
8001e3a: 61bb str r3, [r7, #24]
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8001e3c: f107 0318 add.w r3, r7, #24
8001e40: 4619 mov r1, r3
8001e42: 4872 ldr r0, [pc, #456] ; (800200c <f_Joueur_1+0x208>)
8001e44: f002 ff70 bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8001e48: 4870 ldr r0, [pc, #448] ; (800200c <f_Joueur_1+0x208>)
8001e4a: f002 fe1b bl 8004a84 <HAL_ADC_Start>
ADC_ChannelConfTypeDef sConfig1 = {0};
8001e4e: f107 0308 add.w r3, r7, #8
8001e52: 2200 movs r2, #0
8001e54: 601a str r2, [r3, #0]
8001e56: 605a str r2, [r3, #4]
8001e58: 609a str r2, [r3, #8]
8001e5a: 60da str r2, [r3, #12]
sConfig1.Rank = ADC_REGULAR_RANK_1;
8001e5c: 2301 movs r3, #1
8001e5e: 60fb str r3, [r7, #12]
sConfig1.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001e60: 2300 movs r3, #0
8001e62: 613b str r3, [r7, #16]
sConfig1.Channel = ADC_CHANNEL_0;
8001e64: 2300 movs r3, #0
8001e66: 60bb str r3, [r7, #8]
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
8001e68: f107 0308 add.w r3, r7, #8
8001e6c: 4619 mov r1, r3
8001e6e: 4868 ldr r0, [pc, #416] ; (8002010 <f_Joueur_1+0x20c>)
8001e70: f002 ff5a bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
8001e74: 4866 ldr r0, [pc, #408] ; (8002010 <f_Joueur_1+0x20c>)
8001e76: f002 fe05 bl 8004a84 <HAL_ADC_Start>
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
8001e7a: f000 fdef bl 8002a5c <BSP_LCD_GetXSize>
8001e7e: 64f8 str r0, [r7, #76] ; 0x4c
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
8001e80: f000 fe00 bl 8002a84 <BSP_LCD_GetYSize>
8001e84: 64b8 str r0, [r7, #72] ; 0x48
/* Infinite loop */
for (;;)
{
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
8001e86: 4b63 ldr r3, [pc, #396] ; (8002014 <f_Joueur_1+0x210>)
8001e88: 681b ldr r3, [r3, #0]
8001e8a: 4618 mov r0, r3
8001e8c: f000 fe7e bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
8001e90: 4b61 ldr r3, [pc, #388] ; (8002018 <f_Joueur_1+0x214>)
8001e92: 681b ldr r3, [r3, #0]
8001e94: b298 uxth r0, r3
8001e96: 4b60 ldr r3, [pc, #384] ; (8002018 <f_Joueur_1+0x214>)
8001e98: 685b ldr r3, [r3, #4]
8001e9a: b299 uxth r1, r3
8001e9c: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001ea0: f8b7 2052 ldrh.w r2, [r7, #82] ; 0x52
8001ea4: f001 f92c bl 8003100 <BSP_LCD_FillRect>
// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
HAL_ADC_ConfigChannel(&hadc3, &sConfig3);
8001ea8: f107 0318 add.w r3, r7, #24
8001eac: 4619 mov r1, r3
8001eae: 4857 ldr r0, [pc, #348] ; (800200c <f_Joueur_1+0x208>)
8001eb0: f002 ff3a bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8001eb4: 4855 ldr r0, [pc, #340] ; (800200c <f_Joueur_1+0x208>)
8001eb6: f002 fde5 bl 8004a84 <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc3, 100) != HAL_OK);
8001eba: bf00 nop
8001ebc: 2164 movs r1, #100 ; 0x64
8001ebe: 4853 ldr r0, [pc, #332] ; (800200c <f_Joueur_1+0x208>)
8001ec0: f002 fea0 bl 8004c04 <HAL_ADC_PollForConversion>
8001ec4: 4603 mov r3, r0
8001ec6: 2b00 cmp r3, #0
8001ec8: d1f8 bne.n 8001ebc <f_Joueur_1+0xb8>
joystick_h = HAL_ADC_GetValue(&hadc3);
8001eca: 4850 ldr r0, [pc, #320] ; (800200c <f_Joueur_1+0x208>)
8001ecc: f002 ff1e bl 8004d0c <HAL_ADC_GetValue>
8001ed0: 6478 str r0, [r7, #68] ; 0x44
HAL_ADC_ConfigChannel(&hadc1, &sConfig1);
8001ed2: f107 0308 add.w r3, r7, #8
8001ed6: 4619 mov r1, r3
8001ed8: 484d ldr r0, [pc, #308] ; (8002010 <f_Joueur_1+0x20c>)
8001eda: f002 ff25 bl 8004d28 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc1);
8001ede: 484c ldr r0, [pc, #304] ; (8002010 <f_Joueur_1+0x20c>)
8001ee0: f002 fdd0 bl 8004a84 <HAL_ADC_Start>
while (HAL_ADC_PollForConversion(&hadc1, 100) != HAL_OK);
8001ee4: bf00 nop
8001ee6: 2164 movs r1, #100 ; 0x64
8001ee8: 4849 ldr r0, [pc, #292] ; (8002010 <f_Joueur_1+0x20c>)
8001eea: f002 fe8b bl 8004c04 <HAL_ADC_PollForConversion>
8001eee: 4603 mov r3, r0
8001ef0: 2b00 cmp r3, #0
8001ef2: d1f8 bne.n 8001ee6 <f_Joueur_1+0xe2>
joystick_v = HAL_ADC_GetValue(&hadc1);
8001ef4: 4846 ldr r0, [pc, #280] ; (8002010 <f_Joueur_1+0x20c>)
8001ef6: f002 ff09 bl 8004d0c <HAL_ADC_GetValue>
8001efa: 6438 str r0, [r7, #64] ; 0x40
if ((joueur.y < LCD_WIDTH- Width - joueur.dy)&&(joystick_h < 1900)) joueur.y += joueur.dy;
8001efc: 4b46 ldr r3, [pc, #280] ; (8002018 <f_Joueur_1+0x214>)
8001efe: 685a ldr r2, [r3, #4]
8001f00: f8b7 3052 ldrh.w r3, [r7, #82] ; 0x52
8001f04: 6cb9 ldr r1, [r7, #72] ; 0x48
8001f06: 1acb subs r3, r1, r3
8001f08: 4943 ldr r1, [pc, #268] ; (8002018 <f_Joueur_1+0x214>)
8001f0a: 7a49 ldrb r1, [r1, #9]
8001f0c: 1a5b subs r3, r3, r1
8001f0e: 429a cmp r2, r3
8001f10: d20b bcs.n 8001f2a <f_Joueur_1+0x126>
8001f12: 6c7b ldr r3, [r7, #68] ; 0x44
8001f14: f240 726b movw r2, #1899 ; 0x76b
8001f18: 4293 cmp r3, r2
8001f1a: d806 bhi.n 8001f2a <f_Joueur_1+0x126>
8001f1c: 4b3e ldr r3, [pc, #248] ; (8002018 <f_Joueur_1+0x214>)
8001f1e: 685b ldr r3, [r3, #4]
8001f20: 4a3d ldr r2, [pc, #244] ; (8002018 <f_Joueur_1+0x214>)
8001f22: 7a52 ldrb r2, [r2, #9]
8001f24: 4413 add r3, r2
8001f26: 4a3c ldr r2, [pc, #240] ; (8002018 <f_Joueur_1+0x214>)
8001f28: 6053 str r3, [r2, #4]
if ((joueur.y > joueur.dy)&&(joystick_h > 2100)) joueur.y -= joueur.dy;
8001f2a: 4b3b ldr r3, [pc, #236] ; (8002018 <f_Joueur_1+0x214>)
8001f2c: 685b ldr r3, [r3, #4]
8001f2e: 4a3a ldr r2, [pc, #232] ; (8002018 <f_Joueur_1+0x214>)
8001f30: 7a52 ldrb r2, [r2, #9]
8001f32: 4293 cmp r3, r2
8001f34: d90b bls.n 8001f4e <f_Joueur_1+0x14a>
8001f36: 6c7b ldr r3, [r7, #68] ; 0x44
8001f38: f640 0234 movw r2, #2100 ; 0x834
8001f3c: 4293 cmp r3, r2
8001f3e: d906 bls.n 8001f4e <f_Joueur_1+0x14a>
8001f40: 4b35 ldr r3, [pc, #212] ; (8002018 <f_Joueur_1+0x214>)
8001f42: 685b ldr r3, [r3, #4]
8001f44: 4a34 ldr r2, [pc, #208] ; (8002018 <f_Joueur_1+0x214>)
8001f46: 7a52 ldrb r2, [r2, #9]
8001f48: 1a9b subs r3, r3, r2
8001f4a: 4a33 ldr r2, [pc, #204] ; (8002018 <f_Joueur_1+0x214>)
8001f4c: 6053 str r3, [r2, #4]
if ((joueur.x < LCD_HEIGHT - Height - joueur.dx)&&(joystick_v < 1900)) joueur.x += joueur.dx;
8001f4e: 4b32 ldr r3, [pc, #200] ; (8002018 <f_Joueur_1+0x214>)
8001f50: 681a ldr r2, [r3, #0]
8001f52: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001f56: 6cf9 ldr r1, [r7, #76] ; 0x4c
8001f58: 1acb subs r3, r1, r3
8001f5a: 492f ldr r1, [pc, #188] ; (8002018 <f_Joueur_1+0x214>)
8001f5c: 7a09 ldrb r1, [r1, #8]
8001f5e: 1a5b subs r3, r3, r1
8001f60: 429a cmp r2, r3
8001f62: d20b bcs.n 8001f7c <f_Joueur_1+0x178>
8001f64: 6c3b ldr r3, [r7, #64] ; 0x40
8001f66: f240 726b movw r2, #1899 ; 0x76b
8001f6a: 4293 cmp r3, r2
8001f6c: d806 bhi.n 8001f7c <f_Joueur_1+0x178>
8001f6e: 4b2a ldr r3, [pc, #168] ; (8002018 <f_Joueur_1+0x214>)
8001f70: 681b ldr r3, [r3, #0]
8001f72: 4a29 ldr r2, [pc, #164] ; (8002018 <f_Joueur_1+0x214>)
8001f74: 7a12 ldrb r2, [r2, #8]
8001f76: 4413 add r3, r2
8001f78: 4a27 ldr r2, [pc, #156] ; (8002018 <f_Joueur_1+0x214>)
8001f7a: 6013 str r3, [r2, #0]
if ((joueur.x > joueur.dx)&&(joystick_v > 2100)) joueur.x -= joueur.dx;
8001f7c: 4b26 ldr r3, [pc, #152] ; (8002018 <f_Joueur_1+0x214>)
8001f7e: 681b ldr r3, [r3, #0]
8001f80: 4a25 ldr r2, [pc, #148] ; (8002018 <f_Joueur_1+0x214>)
8001f82: 7a12 ldrb r2, [r2, #8]
8001f84: 4293 cmp r3, r2
8001f86: d90b bls.n 8001fa0 <f_Joueur_1+0x19c>
8001f88: 6c3b ldr r3, [r7, #64] ; 0x40
8001f8a: f640 0234 movw r2, #2100 ; 0x834
8001f8e: 4293 cmp r3, r2
8001f90: d906 bls.n 8001fa0 <f_Joueur_1+0x19c>
8001f92: 4b21 ldr r3, [pc, #132] ; (8002018 <f_Joueur_1+0x214>)
8001f94: 681b ldr r3, [r3, #0]
8001f96: 4a20 ldr r2, [pc, #128] ; (8002018 <f_Joueur_1+0x214>)
8001f98: 7a12 ldrb r2, [r2, #8]
8001f9a: 1a9b subs r3, r3, r2
8001f9c: 4a1e ldr r2, [pc, #120] ; (8002018 <f_Joueur_1+0x214>)
8001f9e: 6013 str r3, [r2, #0]
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8001fa0: 481e ldr r0, [pc, #120] ; (800201c <f_Joueur_1+0x218>)
8001fa2: f000 fdf3 bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
8001fa6: 4b1c ldr r3, [pc, #112] ; (8002018 <f_Joueur_1+0x214>)
8001fa8: 681b ldr r3, [r3, #0]
8001faa: b298 uxth r0, r3
8001fac: 4b1a ldr r3, [pc, #104] ; (8002018 <f_Joueur_1+0x214>)
8001fae: 685b ldr r3, [r3, #4]
8001fb0: b299 uxth r1, r3
8001fb2: f8b7 3050 ldrh.w r3, [r7, #80] ; 0x50
8001fb6: f8b7 2052 ldrh.w r2, [r7, #82] ; 0x52
8001fba: f001 f8a1 bl 8003100 <BSP_LCD_FillRect>
if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
8001fbe: 4b18 ldr r3, [pc, #96] ; (8002020 <f_Joueur_1+0x21c>)
8001fc0: 681b ldr r3, [r3, #0]
8001fc2: f107 0128 add.w r1, r7, #40 ; 0x28
8001fc6: 2200 movs r2, #0
8001fc8: 4618 mov r0, r3
8001fca: f00a fc9f bl 800c90c <xQueueReceive>
8001fce: 4603 mov r3, r0
8001fd0: 2b01 cmp r3, #1
8001fd2: d107 bne.n 8001fe4 <f_Joueur_1+0x1e0>
joueur.health = joueur.health - missile.damage;
8001fd4: 4b10 ldr r3, [pc, #64] ; (8002018 <f_Joueur_1+0x214>)
8001fd6: 7a9a ldrb r2, [r3, #10]
8001fd8: f897 3034 ldrb.w r3, [r7, #52] ; 0x34
8001fdc: 1ad3 subs r3, r2, r3
8001fde: b2da uxtb r2, r3
8001fe0: 4b0d ldr r3, [pc, #52] ; (8002018 <f_Joueur_1+0x214>)
8001fe2: 729a strb r2, [r3, #10]
// On envoie 1 si le joueur est mort et on envoie 0 si les enemis sont tous morts
if (joueur.health == 0)xQueueSend(Queue_FHandle,&stop,0);
8001fe4: 4b0c ldr r3, [pc, #48] ; (8002018 <f_Joueur_1+0x214>)
8001fe6: 7a9b ldrb r3, [r3, #10]
8001fe8: 2b00 cmp r3, #0
8001fea: d107 bne.n 8001ffc <f_Joueur_1+0x1f8>
8001fec: 4b0d ldr r3, [pc, #52] ; (8002024 <f_Joueur_1+0x220>)
8001fee: 6818 ldr r0, [r3, #0]
8001ff0: f107 013b add.w r1, r7, #59 ; 0x3b
8001ff4: 2300 movs r3, #0
8001ff6: 2200 movs r2, #0
8001ff8: f00a fa58 bl 800c4ac <xQueueGenericSend>
// TODO La condition sur une entrée analogique pour envoyer un missile
// struct Missile missile = {joueur.x, joueur.y,joueur.missile.dx, joueur.missile.dy, 1, joueur.missile.color, joueur.missile.damage};
// xQueueSend(Queue_NHandle,&missile,0);
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8001ffc: f107 033c add.w r3, r7, #60 ; 0x3c
8002000: 6d79 ldr r1, [r7, #84] ; 0x54
8002002: 4618 mov r0, r3
8002004: f00b fa52 bl 800d4ac <vTaskDelayUntil>
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
8002008: e73d b.n 8001e86 <f_Joueur_1+0x82>
800200a: bf00 nop
800200c: 20008abc .word 0x20008abc
8002010: 20008a74 .word 0x20008a74
8002014: 20000044 .word 0x20000044
8002018: 20000028 .word 0x20000028
800201c: ff0000ff .word 0xff0000ff
8002020: 20008920 .word 0x20008920
8002024: 20008b08 .word 0x20008b08
08002028 <f_block_enemie>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_block_enemie */
void f_block_enemie(void const * argument)
{
8002028: b580 push {r7, lr}
800202a: f5ad 7d7c sub.w sp, sp, #1008 ; 0x3f0
800202e: af00 add r7, sp, #0
8002030: 1d3b adds r3, r7, #4
8002032: 6018 str r0, [r3, #0]
/* USER CODE BEGIN f_block_enemie */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 10;
8002034: 230a movs r3, #10
8002036: f8c7 33e4 str.w r3, [r7, #996] ; 0x3e4
uint8_t number_monsters = 30;
800203a: 231e movs r3, #30
800203c: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
struct Monster list_monsters[30];
uint8_t end = 0;
8002040: f107 031f add.w r3, r7, #31
8002044: 2200 movs r2, #0
8002046: 701a strb r2, [r3, #0]
uint8_t deplacement = 1;
8002048: 2301 movs r3, #1
800204a: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
struct Missile missile = {0,0,0,0,0,0,0,0};
800204e: f107 030c add.w r3, r7, #12
8002052: 461a mov r2, r3
8002054: 2300 movs r3, #0
8002056: 6013 str r3, [r2, #0]
8002058: 6053 str r3, [r2, #4]
800205a: 6093 str r3, [r2, #8]
800205c: 60d3 str r3, [r2, #12]
/* Infinite loop */
for (;;)
{
xQueueReceive(Queue_EHandle, &missile, 0);
800205e: 4b52 ldr r3, [pc, #328] ; (80021a8 <f_block_enemie+0x180>)
8002060: 681b ldr r3, [r3, #0]
8002062: f107 010c add.w r1, r7, #12
8002066: 2200 movs r2, #0
8002068: 4618 mov r0, r3
800206a: f00a fc4f bl 800c90c <xQueueReceive>
if (number_monsters == 0){
800206e: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
8002072: 2b00 cmp r3, #0
8002074: d107 bne.n 8002086 <f_block_enemie+0x5e>
xQueueSend(Queue_FHandle, &end, 0);
8002076: 4b4d ldr r3, [pc, #308] ; (80021ac <f_block_enemie+0x184>)
8002078: 6818 ldr r0, [r3, #0]
800207a: f107 011f add.w r1, r7, #31
800207e: 2300 movs r3, #0
8002080: 2200 movs r2, #0
8002082: f00a fa13 bl 800c4ac <xQueueGenericSend>
}
for (int i=0;i< number_monsters;i++){
8002086: 2300 movs r3, #0
8002088: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
800208c: e07a b.n 8002184 <f_block_enemie+0x15c>
if (list_monsters[i].health > 0 ){
800208e: f107 0220 add.w r2, r7, #32
8002092: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
8002096: 015b lsls r3, r3, #5
8002098: 4413 add r3, r2
800209a: 331d adds r3, #29
800209c: 781b ldrb r3, [r3, #0]
800209e: 2b00 cmp r3, #0
80020a0: d06b beq.n 800217a <f_block_enemie+0x152>
if ((missile.x == list_monsters[i].x)&&(missile.y == list_monsters[i].y))
80020a2: f107 030c add.w r3, r7, #12
80020a6: 881b ldrh r3, [r3, #0]
80020a8: 4619 mov r1, r3
80020aa: f107 0220 add.w r2, r7, #32
80020ae: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020b2: 015b lsls r3, r3, #5
80020b4: 4413 add r3, r2
80020b6: 681b ldr r3, [r3, #0]
80020b8: 4299 cmp r1, r3
80020ba: d133 bne.n 8002124 <f_block_enemie+0xfc>
80020bc: f107 030c add.w r3, r7, #12
80020c0: 885b ldrh r3, [r3, #2]
80020c2: 4619 mov r1, r3
80020c4: f107 0220 add.w r2, r7, #32
80020c8: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020cc: 015b lsls r3, r3, #5
80020ce: 4413 add r3, r2
80020d0: 3304 adds r3, #4
80020d2: 681b ldr r3, [r3, #0]
80020d4: 4299 cmp r1, r3
80020d6: d125 bne.n 8002124 <f_block_enemie+0xfc>
{
list_monsters[i].health = list_monsters[i].health -1;
80020d8: f107 0220 add.w r2, r7, #32
80020dc: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020e0: 015b lsls r3, r3, #5
80020e2: 4413 add r3, r2
80020e4: 331d adds r3, #29
80020e6: 781b ldrb r3, [r3, #0]
80020e8: 3b01 subs r3, #1
80020ea: b2d9 uxtb r1, r3
80020ec: f107 0220 add.w r2, r7, #32
80020f0: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
80020f4: 015b lsls r3, r3, #5
80020f6: 4413 add r3, r2
80020f8: 331d adds r3, #29
80020fa: 460a mov r2, r1
80020fc: 701a strb r2, [r3, #0]
// Est ce que cette ligne va marcher sachant que je transmets l'adresse dans la queue ?
missile.valide = 0;
80020fe: f107 030c add.w r3, r7, #12
8002102: 2200 movs r2, #0
8002104: 735a strb r2, [r3, #13]
if (list_monsters[i].health == 0){
8002106: f107 0220 add.w r2, r7, #32
800210a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800210e: 015b lsls r3, r3, #5
8002110: 4413 add r3, r2
8002112: 331d adds r3, #29
8002114: 781b ldrb r3, [r3, #0]
8002116: 2b00 cmp r3, #0
8002118: d104 bne.n 8002124 <f_block_enemie+0xfc>
//TODO explosion du plaisir ?
number_monsters = number_monsters -1;
800211a: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
800211e: 3b01 subs r3, #1
8002120: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
}
}
BSP_LCD_DrawBitmap(list_monsters[i].x, list_monsters[i].y, &list_monsters[i].pbmp);
8002124: f107 0220 add.w r2, r7, #32
8002128: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800212c: 015b lsls r3, r3, #5
800212e: 4413 add r3, r2
8002130: 6818 ldr r0, [r3, #0]
8002132: f107 0220 add.w r2, r7, #32
8002136: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800213a: 015b lsls r3, r3, #5
800213c: 4413 add r3, r2
800213e: 3304 adds r3, #4
8002140: 6819 ldr r1, [r3, #0]
8002142: f107 0220 add.w r2, r7, #32
8002146: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800214a: 015b lsls r3, r3, #5
800214c: 3308 adds r3, #8
800214e: 4413 add r3, r2
8002150: 461a mov r2, r3
8002152: f000 ff25 bl 8002fa0 <BSP_LCD_DrawBitmap>
// On alterne le deplacement des méchants comme dans le vrai jeux
//TODO est ce que ca va posé un décalage entre l'affichage et la hitboxe ?
list_monsters[i].x = list_monsters[i].x + deplacement*2;
8002156: f107 0220 add.w r2, r7, #32
800215a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800215e: 015b lsls r3, r3, #5
8002160: 4413 add r3, r2
8002162: 681b ldr r3, [r3, #0]
8002164: f897 23ee ldrb.w r2, [r7, #1006] ; 0x3ee
8002168: 0052 lsls r2, r2, #1
800216a: 441a add r2, r3
800216c: f107 0120 add.w r1, r7, #32
8002170: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
8002174: 015b lsls r3, r3, #5
8002176: 440b add r3, r1
8002178: 601a str r2, [r3, #0]
for (int i=0;i< number_monsters;i++){
800217a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
800217e: 3301 adds r3, #1
8002180: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
8002184: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
8002188: f8d7 23e8 ldr.w r2, [r7, #1000] ; 0x3e8
800218c: 429a cmp r2, r3
800218e: f6ff af7e blt.w 800208e <f_block_enemie+0x66>
}
}
deplacement = -1;
8002192: 23ff movs r3, #255 ; 0xff
8002194: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
8002198: f507 7378 add.w r3, r7, #992 ; 0x3e0
800219c: f8d7 13e4 ldr.w r1, [r7, #996] ; 0x3e4
80021a0: 4618 mov r0, r3
80021a2: f00b f983 bl 800d4ac <vTaskDelayUntil>
xQueueReceive(Queue_EHandle, &missile, 0);
80021a6: e75a b.n 800205e <f_block_enemie+0x36>
80021a8: 20008bf8 .word 0x20008bf8
80021ac: 20008b08 .word 0x20008b08
080021b0 <f_projectile>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_f_projectile */
void f_projectile(void const * argument)
{
80021b0: b590 push {r4, r7, lr}
80021b2: b0dd sub sp, #372 ; 0x174
80021b4: af00 add r7, sp, #0
80021b6: 1d3b adds r3, r7, #4
80021b8: 6018 str r0, [r3, #0]
/* USER CODE BEGIN f_projectile */
TickType_t xLastWakeTime;
const TickType_t xPeriodeTache = 50000;
80021ba: f24c 3350 movw r3, #50000 ; 0xc350
80021be: f8c7 3164 str.w r3, [r7, #356] ; 0x164
/* Infinite loop */
struct Missile liste_missile[20];
struct Missile missile;
uint8_t indice = 0;
80021c2: 2300 movs r3, #0
80021c4: f887 316f strb.w r3, [r7, #367] ; 0x16f
// Paramètre de l'écran pour la reprouductibilité
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
80021c8: f000 fc48 bl 8002a5c <BSP_LCD_GetXSize>
80021cc: f8c7 0160 str.w r0, [r7, #352] ; 0x160
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
80021d0: f000 fc58 bl 8002a84 <BSP_LCD_GetYSize>
80021d4: f8c7 015c str.w r0, [r7, #348] ; 0x15c
for (;;)
{
if (xQueueReceive(Queue_NHandle, &missile, 0) == pdPASS)
80021d8: 4b82 ldr r3, [pc, #520] ; (80023e4 <f_projectile+0x234>)
80021da: 681b ldr r3, [r3, #0]
80021dc: f107 0108 add.w r1, r7, #8
80021e0: 2200 movs r2, #0
80021e2: 4618 mov r0, r3
80021e4: f00a fb92 bl 800c90c <xQueueReceive>
80021e8: 4603 mov r3, r0
80021ea: 2b01 cmp r3, #1
80021ec: d10e bne.n 800220c <f_projectile+0x5c>
{
liste_missile[indice++] = missile;
80021ee: f897 316f ldrb.w r3, [r7, #367] ; 0x16f
80021f2: 1c5a adds r2, r3, #1
80021f4: f887 216f strb.w r2, [r7, #367] ; 0x16f
80021f8: f107 0218 add.w r2, r7, #24
80021fc: 011b lsls r3, r3, #4
80021fe: 441a add r2, r3
8002200: f107 0308 add.w r3, r7, #8
8002204: 4614 mov r4, r2
8002206: cb0f ldmia r3, {r0, r1, r2, r3}
8002208: e884 000f stmia.w r4, {r0, r1, r2, r3}
}
for (int i=0;i< indice;i++)
800220c: 2300 movs r3, #0
800220e: f8c7 3168 str.w r3, [r7, #360] ; 0x168
8002212: e1e4 b.n 80025de <f_projectile+0x42e>
{
// Si le missile n'est pas sur un bord
if (liste_missile[i].valide == 1)
8002214: f107 0218 add.w r2, r7, #24
8002218: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800221c: 011b lsls r3, r3, #4
800221e: 4413 add r3, r2
8002220: 330d adds r3, #13
8002222: 781b ldrb r3, [r3, #0]
8002224: 2b01 cmp r3, #1
8002226: f040 81d5 bne.w 80025d4 <f_projectile+0x424>
{
// Si le missile appartient au joueur :
if (liste_missile[i].equipe == 1)
800222a: f107 0218 add.w r2, r7, #24
800222e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002232: 011b lsls r3, r3, #4
8002234: 4413 add r3, r2
8002236: 3306 adds r3, #6
8002238: 781b ldrb r3, [r3, #0]
800223a: 2b01 cmp r3, #1
800223c: f040 80dc bne.w 80023f8 <f_projectile+0x248>
{
if (liste_missile[i].x >= Limit_ennemis_x)
8002240: f107 0218 add.w r2, r7, #24
8002244: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002248: 011b lsls r3, r3, #4
800224a: 4413 add r3, r2
800224c: 881b ldrh r3, [r3, #0]
800224e: 461a mov r2, r3
8002250: 4b65 ldr r3, [pc, #404] ; (80023e8 <f_projectile+0x238>)
8002252: 681b ldr r3, [r3, #0]
8002254: 429a cmp r2, r3
8002256: d30f bcc.n 8002278 <f_projectile+0xc8>
{
xQueueSend(Queue_EHandle, &liste_missile+indice,0);
8002258: 4b64 ldr r3, [pc, #400] ; (80023ec <f_projectile+0x23c>)
800225a: 6818 ldr r0, [r3, #0]
800225c: f897 216f ldrb.w r2, [r7, #367] ; 0x16f
8002260: 4613 mov r3, r2
8002262: 009b lsls r3, r3, #2
8002264: 4413 add r3, r2
8002266: 019b lsls r3, r3, #6
8002268: 461a mov r2, r3
800226a: f107 0318 add.w r3, r7, #24
800226e: 1899 adds r1, r3, r2
8002270: 2300 movs r3, #0
8002272: 2200 movs r2, #0
8002274: f00a f91a bl 800c4ac <xQueueGenericSend>
// TODO Une petite animation d'explosion ?
}
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
8002278: f107 0218 add.w r2, r7, #24
800227c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002280: 011b lsls r3, r3, #4
8002282: 4413 add r3, r2
8002284: 881b ldrh r3, [r3, #0]
8002286: 2b01 cmp r3, #1
8002288: f240 808d bls.w 80023a6 <f_projectile+0x1f6>
800228c: f107 0218 add.w r2, r7, #24
8002290: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002294: 011b lsls r3, r3, #4
8002296: 4413 add r3, r2
8002298: 881b ldrh r3, [r3, #0]
800229a: 461a mov r2, r3
800229c: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
80022a0: 3b01 subs r3, #1
80022a2: 429a cmp r2, r3
80022a4: d27f bcs.n 80023a6 <f_projectile+0x1f6>
80022a6: f107 0218 add.w r2, r7, #24
80022aa: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80022ae: 011b lsls r3, r3, #4
80022b0: 4413 add r3, r2
80022b2: 3302 adds r3, #2
80022b4: 881b ldrh r3, [r3, #0]
80022b6: 461a mov r2, r3
80022b8: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
80022bc: 3b01 subs r3, #1
80022be: 429a cmp r2, r3
80022c0: d271 bcs.n 80023a6 <f_projectile+0x1f6>
80022c2: f107 0218 add.w r2, r7, #24
80022c6: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80022ca: 011b lsls r3, r3, #4
80022cc: 4413 add r3, r2
80022ce: 3302 adds r3, #2
80022d0: 881b ldrh r3, [r3, #0]
80022d2: 2b01 cmp r3, #1
80022d4: d967 bls.n 80023a6 <f_projectile+0x1f6>
{
//BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
taskENTER_CRITICAL();
80022d6: f00c f937 bl 800e548 <vPortEnterCritical>
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
80022da: 4b45 ldr r3, [pc, #276] ; (80023f0 <f_projectile+0x240>)
80022dc: 681b ldr r3, [r3, #0]
80022de: 4618 mov r0, r3
80022e0: f000 fc54 bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(joueur.x, joueur.y, 20, 20);
80022e4: 4b43 ldr r3, [pc, #268] ; (80023f4 <f_projectile+0x244>)
80022e6: 681b ldr r3, [r3, #0]
80022e8: b298 uxth r0, r3
80022ea: 4b42 ldr r3, [pc, #264] ; (80023f4 <f_projectile+0x244>)
80022ec: 685b ldr r3, [r3, #4]
80022ee: b299 uxth r1, r3
80022f0: 2314 movs r3, #20
80022f2: 2214 movs r2, #20
80022f4: f000 ff04 bl 8003100 <BSP_LCD_FillRect>
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
80022f8: f107 0218 add.w r2, r7, #24
80022fc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002300: 011b lsls r3, r3, #4
8002302: 4413 add r3, r2
8002304: 881a ldrh r2, [r3, #0]
8002306: f107 0118 add.w r1, r7, #24
800230a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800230e: 011b lsls r3, r3, #4
8002310: 440b add r3, r1
8002312: 3304 adds r3, #4
8002314: 781b ldrb r3, [r3, #0]
8002316: b29b uxth r3, r3
8002318: 4413 add r3, r2
800231a: b299 uxth r1, r3
800231c: f107 0218 add.w r2, r7, #24
8002320: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002324: 011b lsls r3, r3, #4
8002326: 4413 add r3, r2
8002328: 460a mov r2, r1
800232a: 801a strh r2, [r3, #0]
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
800232c: f107 0218 add.w r2, r7, #24
8002330: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002334: 011b lsls r3, r3, #4
8002336: 4413 add r3, r2
8002338: 3302 adds r3, #2
800233a: 881a ldrh r2, [r3, #0]
800233c: f107 0118 add.w r1, r7, #24
8002340: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002344: 011b lsls r3, r3, #4
8002346: 440b add r3, r1
8002348: 3305 adds r3, #5
800234a: 781b ldrb r3, [r3, #0]
800234c: b29b uxth r3, r3
800234e: 4413 add r3, r2
8002350: b299 uxth r1, r3
8002352: f107 0218 add.w r2, r7, #24
8002356: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800235a: 011b lsls r3, r3, #4
800235c: 4413 add r3, r2
800235e: 3302 adds r3, #2
8002360: 460a mov r2, r1
8002362: 801a strh r2, [r3, #0]
//BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
BSP_LCD_SetTextColor(liste_missile[i].color);
8002364: f107 0218 add.w r2, r7, #24
8002368: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800236c: 011b lsls r3, r3, #4
800236e: 4413 add r3, r2
8002370: 3308 adds r3, #8
8002372: 681b ldr r3, [r3, #0]
8002374: 4618 mov r0, r3
8002376: f000 fc09 bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_FillRect(liste_missile[i].x, liste_missile[i].y, 20, 20);
800237a: f107 0218 add.w r2, r7, #24
800237e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002382: 011b lsls r3, r3, #4
8002384: 4413 add r3, r2
8002386: 8818 ldrh r0, [r3, #0]
8002388: f107 0218 add.w r2, r7, #24
800238c: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002390: 011b lsls r3, r3, #4
8002392: 4413 add r3, r2
8002394: 3302 adds r3, #2
8002396: 8819 ldrh r1, [r3, #0]
8002398: 2314 movs r3, #20
800239a: 2214 movs r2, #20
800239c: f000 feb0 bl 8003100 <BSP_LCD_FillRect>
taskEXIT_CRITICAL();
80023a0: f00c f904 bl 800e5ac <vPortExitCritical>
80023a4: e116 b.n 80025d4 <f_projectile+0x424>
}
//TODO test sur tous les ennemis
else
{
liste_missile[i].valide = 0;
80023a6: f107 0218 add.w r2, r7, #24
80023aa: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023ae: 011b lsls r3, r3, #4
80023b0: 4413 add r3, r2
80023b2: 330d adds r3, #13
80023b4: 2200 movs r2, #0
80023b6: 701a strb r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80023b8: f107 0218 add.w r2, r7, #24
80023bc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023c0: 011b lsls r3, r3, #4
80023c2: 4413 add r3, r2
80023c4: 8818 ldrh r0, [r3, #0]
80023c6: f107 0218 add.w r2, r7, #24
80023ca: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80023ce: 011b lsls r3, r3, #4
80023d0: 4413 add r3, r2
80023d2: 3302 adds r3, #2
80023d4: 8819 ldrh r1, [r3, #0]
80023d6: 4b06 ldr r3, [pc, #24] ; (80023f0 <f_projectile+0x240>)
80023d8: 681b ldr r3, [r3, #0]
80023da: 461a mov r2, r3
80023dc: f000 fd98 bl 8002f10 <BSP_LCD_DrawPixel>
80023e0: e0f8 b.n 80025d4 <f_projectile+0x424>
80023e2: bf00 nop
80023e4: 20008b04 .word 0x20008b04
80023e8: 2000004c .word 0x2000004c
80023ec: 20008bf8 .word 0x20008bf8
80023f0: 20000044 .word 0x20000044
80023f4: 20000028 .word 0x20000028
}
}
// Si le missile appartient aux ennemis
else if (liste_missile[i].equipe == 0)
80023f8: f107 0218 add.w r2, r7, #24
80023fc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002400: 011b lsls r3, r3, #4
8002402: 4413 add r3, r2
8002404: 3306 adds r3, #6
8002406: 781b ldrb r3, [r3, #0]
8002408: 2b00 cmp r3, #0
800240a: f040 80e3 bne.w 80025d4 <f_projectile+0x424>
{
if ((liste_missile[i].x == joueur.x)&&(liste_missile[i].y == joueur.y))
800240e: f107 0218 add.w r2, r7, #24
8002412: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002416: 011b lsls r3, r3, #4
8002418: 4413 add r3, r2
800241a: 881b ldrh r3, [r3, #0]
800241c: 461a mov r2, r3
800241e: 4b77 ldr r3, [pc, #476] ; (80025fc <f_projectile+0x44c>)
8002420: 681b ldr r3, [r3, #0]
8002422: 429a cmp r2, r3
8002424: d125 bne.n 8002472 <f_projectile+0x2c2>
8002426: f107 0218 add.w r2, r7, #24
800242a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800242e: 011b lsls r3, r3, #4
8002430: 4413 add r3, r2
8002432: 3302 adds r3, #2
8002434: 881b ldrh r3, [r3, #0]
8002436: 461a mov r2, r3
8002438: 4b70 ldr r3, [pc, #448] ; (80025fc <f_projectile+0x44c>)
800243a: 685b ldr r3, [r3, #4]
800243c: 429a cmp r2, r3
800243e: d118 bne.n 8002472 <f_projectile+0x2c2>
{
xQueueSend(Queue_JHandle, &liste_missile+indice,0);
8002440: 4b6f ldr r3, [pc, #444] ; (8002600 <f_projectile+0x450>)
8002442: 6818 ldr r0, [r3, #0]
8002444: f897 216f ldrb.w r2, [r7, #367] ; 0x16f
8002448: 4613 mov r3, r2
800244a: 009b lsls r3, r3, #2
800244c: 4413 add r3, r2
800244e: 019b lsls r3, r3, #6
8002450: 461a mov r2, r3
8002452: f107 0318 add.w r3, r7, #24
8002456: 1899 adds r1, r3, r2
8002458: 2300 movs r3, #0
800245a: 2200 movs r2, #0
800245c: f00a f826 bl 800c4ac <xQueueGenericSend>
liste_missile[i].valide = 0;
8002460: f107 0218 add.w r2, r7, #24
8002464: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002468: 011b lsls r3, r3, #4
800246a: 4413 add r3, r2
800246c: 330d adds r3, #13
800246e: 2200 movs r2, #0
8002470: 701a strb r2, [r3, #0]
// TODO Une petite animation d'explosion ?
}
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
8002472: f107 0218 add.w r2, r7, #24
8002476: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800247a: 011b lsls r3, r3, #4
800247c: 4413 add r3, r2
800247e: 881b ldrh r3, [r3, #0]
8002480: 2b01 cmp r3, #1
8002482: f240 808a bls.w 800259a <f_projectile+0x3ea>
8002486: f107 0218 add.w r2, r7, #24
800248a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800248e: 011b lsls r3, r3, #4
8002490: 4413 add r3, r2
8002492: 881b ldrh r3, [r3, #0]
8002494: 461a mov r2, r3
8002496: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
800249a: 3b01 subs r3, #1
800249c: 429a cmp r2, r3
800249e: d27c bcs.n 800259a <f_projectile+0x3ea>
80024a0: f107 0218 add.w r2, r7, #24
80024a4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024a8: 011b lsls r3, r3, #4
80024aa: 4413 add r3, r2
80024ac: 3302 adds r3, #2
80024ae: 881b ldrh r3, [r3, #0]
80024b0: 461a mov r2, r3
80024b2: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
80024b6: 3b01 subs r3, #1
80024b8: 429a cmp r2, r3
80024ba: d26e bcs.n 800259a <f_projectile+0x3ea>
80024bc: f107 0218 add.w r2, r7, #24
80024c0: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024c4: 011b lsls r3, r3, #4
80024c6: 4413 add r3, r2
80024c8: 3302 adds r3, #2
80024ca: 881b ldrh r3, [r3, #0]
80024cc: 2b01 cmp r3, #1
80024ce: d964 bls.n 800259a <f_projectile+0x3ea>
{
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80024d0: f107 0218 add.w r2, r7, #24
80024d4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024d8: 011b lsls r3, r3, #4
80024da: 4413 add r3, r2
80024dc: 8818 ldrh r0, [r3, #0]
80024de: f107 0218 add.w r2, r7, #24
80024e2: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80024e6: 011b lsls r3, r3, #4
80024e8: 4413 add r3, r2
80024ea: 3302 adds r3, #2
80024ec: 8819 ldrh r1, [r3, #0]
80024ee: 4b45 ldr r3, [pc, #276] ; (8002604 <f_projectile+0x454>)
80024f0: 681b ldr r3, [r3, #0]
80024f2: 461a mov r2, r3
80024f4: f000 fd0c bl 8002f10 <BSP_LCD_DrawPixel>
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
80024f8: f107 0218 add.w r2, r7, #24
80024fc: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002500: 011b lsls r3, r3, #4
8002502: 4413 add r3, r2
8002504: 881a ldrh r2, [r3, #0]
8002506: f107 0118 add.w r1, r7, #24
800250a: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800250e: 011b lsls r3, r3, #4
8002510: 440b add r3, r1
8002512: 3304 adds r3, #4
8002514: 781b ldrb r3, [r3, #0]
8002516: b29b uxth r3, r3
8002518: 4413 add r3, r2
800251a: b299 uxth r1, r3
800251c: f107 0218 add.w r2, r7, #24
8002520: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002524: 011b lsls r3, r3, #4
8002526: 4413 add r3, r2
8002528: 460a mov r2, r1
800252a: 801a strh r2, [r3, #0]
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
800252c: f107 0218 add.w r2, r7, #24
8002530: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002534: 011b lsls r3, r3, #4
8002536: 4413 add r3, r2
8002538: 3302 adds r3, #2
800253a: 881a ldrh r2, [r3, #0]
800253c: f107 0118 add.w r1, r7, #24
8002540: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
8002544: 011b lsls r3, r3, #4
8002546: 440b add r3, r1
8002548: 3305 adds r3, #5
800254a: 781b ldrb r3, [r3, #0]
800254c: b29b uxth r3, r3
800254e: 4413 add r3, r2
8002550: b299 uxth r1, r3
8002552: f107 0218 add.w r2, r7, #24
8002556: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800255a: 011b lsls r3, r3, #4
800255c: 4413 add r3, r2
800255e: 3302 adds r3, #2
8002560: 460a mov r2, r1
8002562: 801a strh r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
8002564: f107 0218 add.w r2, r7, #24
8002568: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800256c: 011b lsls r3, r3, #4
800256e: 4413 add r3, r2
8002570: 8818 ldrh r0, [r3, #0]
8002572: f107 0218 add.w r2, r7, #24
8002576: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800257a: 011b lsls r3, r3, #4
800257c: 4413 add r3, r2
800257e: 3302 adds r3, #2
8002580: 8819 ldrh r1, [r3, #0]
8002582: f107 0218 add.w r2, r7, #24
8002586: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800258a: 011b lsls r3, r3, #4
800258c: 4413 add r3, r2
800258e: 3308 adds r3, #8
8002590: 681b ldr r3, [r3, #0]
8002592: 461a mov r2, r3
8002594: f000 fcbc bl 8002f10 <BSP_LCD_DrawPixel>
8002598: e01c b.n 80025d4 <f_projectile+0x424>
}
else
{
liste_missile[i].valide = 0;
800259a: f107 0218 add.w r2, r7, #24
800259e: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025a2: 011b lsls r3, r3, #4
80025a4: 4413 add r3, r2
80025a6: 330d adds r3, #13
80025a8: 2200 movs r2, #0
80025aa: 701a strb r2, [r3, #0]
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
80025ac: f107 0218 add.w r2, r7, #24
80025b0: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025b4: 011b lsls r3, r3, #4
80025b6: 4413 add r3, r2
80025b8: 8818 ldrh r0, [r3, #0]
80025ba: f107 0218 add.w r2, r7, #24
80025be: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025c2: 011b lsls r3, r3, #4
80025c4: 4413 add r3, r2
80025c6: 3302 adds r3, #2
80025c8: 8819 ldrh r1, [r3, #0]
80025ca: 4b0e ldr r3, [pc, #56] ; (8002604 <f_projectile+0x454>)
80025cc: 681b ldr r3, [r3, #0]
80025ce: 461a mov r2, r3
80025d0: f000 fc9e bl 8002f10 <BSP_LCD_DrawPixel>
for (int i=0;i< indice;i++)
80025d4: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
80025d8: 3301 adds r3, #1
80025da: f8c7 3168 str.w r3, [r7, #360] ; 0x168
80025de: f897 316f ldrb.w r3, [r7, #367] ; 0x16f
80025e2: f8d7 2168 ldr.w r2, [r7, #360] ; 0x168
80025e6: 429a cmp r2, r3
80025e8: f6ff ae14 blt.w 8002214 <f_projectile+0x64>
}
}
}
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
80025ec: f507 73ac add.w r3, r7, #344 ; 0x158
80025f0: f8d7 1164 ldr.w r1, [r7, #356] ; 0x164
80025f4: 4618 mov r0, r3
80025f6: f00a ff59 bl 800d4ac <vTaskDelayUntil>
if (xQueueReceive(Queue_NHandle, &missile, 0) == pdPASS)
80025fa: e5ed b.n 80021d8 <f_projectile+0x28>
80025fc: 20000028 .word 0x20000028
8002600: 20008920 .word 0x20008920
8002604: 20000044 .word 0x20000044
08002608 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8002608: b580 push {r7, lr}
800260a: b082 sub sp, #8
800260c: af00 add r7, sp, #0
800260e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
8002610: 687b ldr r3, [r7, #4]
8002612: 681b ldr r3, [r3, #0]
8002614: 4a04 ldr r2, [pc, #16] ; (8002628 <HAL_TIM_PeriodElapsedCallback+0x20>)
8002616: 4293 cmp r3, r2
8002618: d101 bne.n 800261e <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
800261a: f002 f9ad bl 8004978 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800261e: bf00 nop
8002620: 3708 adds r7, #8
8002622: 46bd mov sp, r7
8002624: bd80 pop {r7, pc}
8002626: bf00 nop
8002628: 40001000 .word 0x40001000
0800262c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800262c: b480 push {r7}
800262e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8002630: b672 cpsid i
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8002632: e7fe b.n 8002632 <Error_Handler+0x6>
08002634 <I2Cx_MspInit>:
* @brief Initializes I2C MSP.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
{
8002634: b580 push {r7, lr}
8002636: b08c sub sp, #48 ; 0x30
8002638: af00 add r7, sp, #0
800263a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef gpio_init_structure;
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
800263c: 687b ldr r3, [r7, #4]
800263e: 4a51 ldr r2, [pc, #324] ; (8002784 <I2Cx_MspInit+0x150>)
8002640: 4293 cmp r3, r2
8002642: d14d bne.n 80026e0 <I2Cx_MspInit+0xac>
{
/* AUDIO and LCD I2C MSP init */
/*** Configure the GPIOs ***/
/* Enable GPIO clock */
DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
8002644: 4b50 ldr r3, [pc, #320] ; (8002788 <I2Cx_MspInit+0x154>)
8002646: 6b1b ldr r3, [r3, #48] ; 0x30
8002648: 4a4f ldr r2, [pc, #316] ; (8002788 <I2Cx_MspInit+0x154>)
800264a: f043 0380 orr.w r3, r3, #128 ; 0x80
800264e: 6313 str r3, [r2, #48] ; 0x30
8002650: 4b4d ldr r3, [pc, #308] ; (8002788 <I2Cx_MspInit+0x154>)
8002652: 6b1b ldr r3, [r3, #48] ; 0x30
8002654: f003 0380 and.w r3, r3, #128 ; 0x80
8002658: 61bb str r3, [r7, #24]
800265a: 69bb ldr r3, [r7, #24]
/* Configure I2C Tx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN;
800265c: 2380 movs r3, #128 ; 0x80
800265e: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
8002660: 2312 movs r3, #18
8002662: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
8002664: 2300 movs r3, #0
8002666: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8002668: 2302 movs r3, #2
800266a: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF;
800266c: 2304 movs r3, #4
800266e: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002670: f107 031c add.w r3, r7, #28
8002674: 4619 mov r1, r3
8002676: 4845 ldr r0, [pc, #276] ; (800278c <I2Cx_MspInit+0x158>)
8002678: f004 fe02 bl 8007280 <HAL_GPIO_Init>
/* Configure I2C Rx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN;
800267c: f44f 7380 mov.w r3, #256 ; 0x100
8002680: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002682: f107 031c add.w r3, r7, #28
8002686: 4619 mov r1, r3
8002688: 4840 ldr r0, [pc, #256] ; (800278c <I2Cx_MspInit+0x158>)
800268a: f004 fdf9 bl 8007280 <HAL_GPIO_Init>
/*** Configure the I2C peripheral ***/
/* Enable I2C clock */
DISCOVERY_AUDIO_I2Cx_CLK_ENABLE();
800268e: 4b3e ldr r3, [pc, #248] ; (8002788 <I2Cx_MspInit+0x154>)
8002690: 6c1b ldr r3, [r3, #64] ; 0x40
8002692: 4a3d ldr r2, [pc, #244] ; (8002788 <I2Cx_MspInit+0x154>)
8002694: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8002698: 6413 str r3, [r2, #64] ; 0x40
800269a: 4b3b ldr r3, [pc, #236] ; (8002788 <I2Cx_MspInit+0x154>)
800269c: 6c1b ldr r3, [r3, #64] ; 0x40
800269e: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80026a2: 617b str r3, [r7, #20]
80026a4: 697b ldr r3, [r7, #20]
/* Force the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_FORCE_RESET();
80026a6: 4b38 ldr r3, [pc, #224] ; (8002788 <I2Cx_MspInit+0x154>)
80026a8: 6a1b ldr r3, [r3, #32]
80026aa: 4a37 ldr r2, [pc, #220] ; (8002788 <I2Cx_MspInit+0x154>)
80026ac: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80026b0: 6213 str r3, [r2, #32]
/* Release the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_RELEASE_RESET();
80026b2: 4b35 ldr r3, [pc, #212] ; (8002788 <I2Cx_MspInit+0x154>)
80026b4: 6a1b ldr r3, [r3, #32]
80026b6: 4a34 ldr r2, [pc, #208] ; (8002788 <I2Cx_MspInit+0x154>)
80026b8: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
80026bc: 6213 str r3, [r2, #32]
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0);
80026be: 2200 movs r2, #0
80026c0: 210f movs r1, #15
80026c2: 2048 movs r0, #72 ; 0x48
80026c4: f002 fe2c bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn);
80026c8: 2048 movs r0, #72 ; 0x48
80026ca: f002 fe45 bl 8005358 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0);
80026ce: 2200 movs r2, #0
80026d0: 210f movs r1, #15
80026d2: 2049 movs r0, #73 ; 0x49
80026d4: f002 fe24 bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn);
80026d8: 2049 movs r0, #73 ; 0x49
80026da: f002 fe3d bl 8005358 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
}
}
80026de: e04d b.n 800277c <I2Cx_MspInit+0x148>
DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
80026e0: 4b29 ldr r3, [pc, #164] ; (8002788 <I2Cx_MspInit+0x154>)
80026e2: 6b1b ldr r3, [r3, #48] ; 0x30
80026e4: 4a28 ldr r2, [pc, #160] ; (8002788 <I2Cx_MspInit+0x154>)
80026e6: f043 0302 orr.w r3, r3, #2
80026ea: 6313 str r3, [r2, #48] ; 0x30
80026ec: 4b26 ldr r3, [pc, #152] ; (8002788 <I2Cx_MspInit+0x154>)
80026ee: 6b1b ldr r3, [r3, #48] ; 0x30
80026f0: f003 0302 and.w r3, r3, #2
80026f4: 613b str r3, [r7, #16]
80026f6: 693b ldr r3, [r7, #16]
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN;
80026f8: f44f 7380 mov.w r3, #256 ; 0x100
80026fc: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
80026fe: 2312 movs r3, #18
8002700: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
8002702: 2300 movs r3, #0
8002704: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8002706: 2302 movs r3, #2
8002708: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF;
800270a: 2304 movs r3, #4
800270c: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
800270e: f107 031c add.w r3, r7, #28
8002712: 4619 mov r1, r3
8002714: 481e ldr r0, [pc, #120] ; (8002790 <I2Cx_MspInit+0x15c>)
8002716: f004 fdb3 bl 8007280 <HAL_GPIO_Init>
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN;
800271a: f44f 7300 mov.w r3, #512 ; 0x200
800271e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8002720: f107 031c add.w r3, r7, #28
8002724: 4619 mov r1, r3
8002726: 481a ldr r0, [pc, #104] ; (8002790 <I2Cx_MspInit+0x15c>)
8002728: f004 fdaa bl 8007280 <HAL_GPIO_Init>
DISCOVERY_EXT_I2Cx_CLK_ENABLE();
800272c: 4b16 ldr r3, [pc, #88] ; (8002788 <I2Cx_MspInit+0x154>)
800272e: 6c1b ldr r3, [r3, #64] ; 0x40
8002730: 4a15 ldr r2, [pc, #84] ; (8002788 <I2Cx_MspInit+0x154>)
8002732: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8002736: 6413 str r3, [r2, #64] ; 0x40
8002738: 4b13 ldr r3, [pc, #76] ; (8002788 <I2Cx_MspInit+0x154>)
800273a: 6c1b ldr r3, [r3, #64] ; 0x40
800273c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002740: 60fb str r3, [r7, #12]
8002742: 68fb ldr r3, [r7, #12]
DISCOVERY_EXT_I2Cx_FORCE_RESET();
8002744: 4b10 ldr r3, [pc, #64] ; (8002788 <I2Cx_MspInit+0x154>)
8002746: 6a1b ldr r3, [r3, #32]
8002748: 4a0f ldr r2, [pc, #60] ; (8002788 <I2Cx_MspInit+0x154>)
800274a: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
800274e: 6213 str r3, [r2, #32]
DISCOVERY_EXT_I2Cx_RELEASE_RESET();
8002750: 4b0d ldr r3, [pc, #52] ; (8002788 <I2Cx_MspInit+0x154>)
8002752: 6a1b ldr r3, [r3, #32]
8002754: 4a0c ldr r2, [pc, #48] ; (8002788 <I2Cx_MspInit+0x154>)
8002756: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
800275a: 6213 str r3, [r2, #32]
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0);
800275c: 2200 movs r2, #0
800275e: 210f movs r1, #15
8002760: 201f movs r0, #31
8002762: f002 fddd bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn);
8002766: 201f movs r0, #31
8002768: f002 fdf6 bl 8005358 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
800276c: 2200 movs r2, #0
800276e: 210f movs r1, #15
8002770: 2020 movs r0, #32
8002772: f002 fdd5 bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
8002776: 2020 movs r0, #32
8002778: f002 fdee bl 8005358 <HAL_NVIC_EnableIRQ>
}
800277c: bf00 nop
800277e: 3730 adds r7, #48 ; 0x30
8002780: 46bd mov sp, r7
8002782: bd80 pop {r7, pc}
8002784: 20000390 .word 0x20000390
8002788: 40023800 .word 0x40023800
800278c: 40021c00 .word 0x40021c00
8002790: 40020400 .word 0x40020400
08002794 <I2Cx_Init>:
* @brief Initializes I2C HAL.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
{
8002794: b580 push {r7, lr}
8002796: b082 sub sp, #8
8002798: af00 add r7, sp, #0
800279a: 6078 str r0, [r7, #4]
if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET)
800279c: 6878 ldr r0, [r7, #4]
800279e: f005 fa67 bl 8007c70 <HAL_I2C_GetState>
80027a2: 4603 mov r3, r0
80027a4: 2b00 cmp r3, #0
80027a6: d125 bne.n 80027f4 <I2Cx_Init+0x60>
{
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
80027a8: 687b ldr r3, [r7, #4]
80027aa: 4a14 ldr r2, [pc, #80] ; (80027fc <I2Cx_Init+0x68>)
80027ac: 4293 cmp r3, r2
80027ae: d103 bne.n 80027b8 <I2Cx_Init+0x24>
{
/* Audio and LCD I2C configuration */
i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx;
80027b0: 687b ldr r3, [r7, #4]
80027b2: 4a13 ldr r2, [pc, #76] ; (8002800 <I2Cx_Init+0x6c>)
80027b4: 601a str r2, [r3, #0]
80027b6: e002 b.n 80027be <I2Cx_Init+0x2a>
}
else
{
/* External, camera and Arduino connector I2C configuration */
i2c_handler->Instance = DISCOVERY_EXT_I2Cx;
80027b8: 687b ldr r3, [r7, #4]
80027ba: 4a12 ldr r2, [pc, #72] ; (8002804 <I2Cx_Init+0x70>)
80027bc: 601a str r2, [r3, #0]
}
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
80027be: 687b ldr r3, [r7, #4]
80027c0: 4a11 ldr r2, [pc, #68] ; (8002808 <I2Cx_Init+0x74>)
80027c2: 605a str r2, [r3, #4]
i2c_handler->Init.OwnAddress1 = 0;
80027c4: 687b ldr r3, [r7, #4]
80027c6: 2200 movs r2, #0
80027c8: 609a str r2, [r3, #8]
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80027ca: 687b ldr r3, [r7, #4]
80027cc: 2201 movs r2, #1
80027ce: 60da str r2, [r3, #12]
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80027d0: 687b ldr r3, [r7, #4]
80027d2: 2200 movs r2, #0
80027d4: 611a str r2, [r3, #16]
i2c_handler->Init.OwnAddress2 = 0;
80027d6: 687b ldr r3, [r7, #4]
80027d8: 2200 movs r2, #0
80027da: 615a str r2, [r3, #20]
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80027dc: 687b ldr r3, [r7, #4]
80027de: 2200 movs r2, #0
80027e0: 61da str r2, [r3, #28]
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80027e2: 687b ldr r3, [r7, #4]
80027e4: 2200 movs r2, #0
80027e6: 621a str r2, [r3, #32]
/* Init the I2C */
I2Cx_MspInit(i2c_handler);
80027e8: 6878 ldr r0, [r7, #4]
80027ea: f7ff ff23 bl 8002634 <I2Cx_MspInit>
HAL_I2C_Init(i2c_handler);
80027ee: 6878 ldr r0, [r7, #4]
80027f0: f004 ff3c bl 800766c <HAL_I2C_Init>
}
}
80027f4: bf00 nop
80027f6: 3708 adds r7, #8
80027f8: 46bd mov sp, r7
80027fa: bd80 pop {r7, pc}
80027fc: 20000390 .word 0x20000390
8002800: 40005c00 .word 0x40005c00
8002804: 40005400 .word 0x40005400
8002808: 40912732 .word 0x40912732
0800280c <I2Cx_ReadMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
800280c: b580 push {r7, lr}
800280e: b08a sub sp, #40 ; 0x28
8002810: af04 add r7, sp, #16
8002812: 60f8 str r0, [r7, #12]
8002814: 4608 mov r0, r1
8002816: 4611 mov r1, r2
8002818: 461a mov r2, r3
800281a: 4603 mov r3, r0
800281c: 72fb strb r3, [r7, #11]
800281e: 460b mov r3, r1
8002820: 813b strh r3, [r7, #8]
8002822: 4613 mov r3, r2
8002824: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
8002826: 2300 movs r3, #0
8002828: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
800282a: 7afb ldrb r3, [r7, #11]
800282c: b299 uxth r1, r3
800282e: 88f8 ldrh r0, [r7, #6]
8002830: 893a ldrh r2, [r7, #8]
8002832: f44f 737a mov.w r3, #1000 ; 0x3e8
8002836: 9302 str r3, [sp, #8]
8002838: 8cbb ldrh r3, [r7, #36] ; 0x24
800283a: 9301 str r3, [sp, #4]
800283c: 6a3b ldr r3, [r7, #32]
800283e: 9300 str r3, [sp, #0]
8002840: 4603 mov r3, r0
8002842: 68f8 ldr r0, [r7, #12]
8002844: f005 f8fa bl 8007a3c <HAL_I2C_Mem_Read>
8002848: 4603 mov r3, r0
800284a: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
800284c: 7dfb ldrb r3, [r7, #23]
800284e: 2b00 cmp r3, #0
8002850: d004 beq.n 800285c <I2Cx_ReadMultiple+0x50>
{
/* I2C error occurred */
I2Cx_Error(i2c_handler, Addr);
8002852: 7afb ldrb r3, [r7, #11]
8002854: 4619 mov r1, r3
8002856: 68f8 ldr r0, [r7, #12]
8002858: f000 f832 bl 80028c0 <I2Cx_Error>
}
return status;
800285c: 7dfb ldrb r3, [r7, #23]
}
800285e: 4618 mov r0, r3
8002860: 3718 adds r7, #24
8002862: 46bd mov sp, r7
8002864: bd80 pop {r7, pc}
08002866 <I2Cx_WriteMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
8002866: b580 push {r7, lr}
8002868: b08a sub sp, #40 ; 0x28
800286a: af04 add r7, sp, #16
800286c: 60f8 str r0, [r7, #12]
800286e: 4608 mov r0, r1
8002870: 4611 mov r1, r2
8002872: 461a mov r2, r3
8002874: 4603 mov r3, r0
8002876: 72fb strb r3, [r7, #11]
8002878: 460b mov r3, r1
800287a: 813b strh r3, [r7, #8]
800287c: 4613 mov r3, r2
800287e: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
8002880: 2300 movs r3, #0
8002882: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
8002884: 7afb ldrb r3, [r7, #11]
8002886: b299 uxth r1, r3
8002888: 88f8 ldrh r0, [r7, #6]
800288a: 893a ldrh r2, [r7, #8]
800288c: f44f 737a mov.w r3, #1000 ; 0x3e8
8002890: 9302 str r3, [sp, #8]
8002892: 8cbb ldrh r3, [r7, #36] ; 0x24
8002894: 9301 str r3, [sp, #4]
8002896: 6a3b ldr r3, [r7, #32]
8002898: 9300 str r3, [sp, #0]
800289a: 4603 mov r3, r0
800289c: 68f8 ldr r0, [r7, #12]
800289e: f004 ffb9 bl 8007814 <HAL_I2C_Mem_Write>
80028a2: 4603 mov r3, r0
80028a4: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
80028a6: 7dfb ldrb r3, [r7, #23]
80028a8: 2b00 cmp r3, #0
80028aa: d004 beq.n 80028b6 <I2Cx_WriteMultiple+0x50>
{
/* Re-Initiaize the I2C Bus */
I2Cx_Error(i2c_handler, Addr);
80028ac: 7afb ldrb r3, [r7, #11]
80028ae: 4619 mov r1, r3
80028b0: 68f8 ldr r0, [r7, #12]
80028b2: f000 f805 bl 80028c0 <I2Cx_Error>
}
return status;
80028b6: 7dfb ldrb r3, [r7, #23]
}
80028b8: 4618 mov r0, r3
80028ba: 3718 adds r7, #24
80028bc: 46bd mov sp, r7
80028be: bd80 pop {r7, pc}
080028c0 <I2Cx_Error>:
* @param i2c_handler : I2C handler
* @param Addr: I2C Address
* @retval None
*/
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
{
80028c0: b580 push {r7, lr}
80028c2: b082 sub sp, #8
80028c4: af00 add r7, sp, #0
80028c6: 6078 str r0, [r7, #4]
80028c8: 460b mov r3, r1
80028ca: 70fb strb r3, [r7, #3]
/* De-initialize the I2C communication bus */
HAL_I2C_DeInit(i2c_handler);
80028cc: 6878 ldr r0, [r7, #4]
80028ce: f004 ff5d bl 800778c <HAL_I2C_DeInit>
/* Re-Initialize the I2C communication bus */
I2Cx_Init(i2c_handler);
80028d2: 6878 ldr r0, [r7, #4]
80028d4: f7ff ff5e bl 8002794 <I2Cx_Init>
}
80028d8: bf00 nop
80028da: 3708 adds r7, #8
80028dc: 46bd mov sp, r7
80028de: bd80 pop {r7, pc}
080028e0 <TS_IO_Init>:
/**
* @brief Initializes Touchscreen low level.
* @retval None
*/
void TS_IO_Init(void)
{
80028e0: b580 push {r7, lr}
80028e2: af00 add r7, sp, #0
I2Cx_Init(&hI2cAudioHandler);
80028e4: 4802 ldr r0, [pc, #8] ; (80028f0 <TS_IO_Init+0x10>)
80028e6: f7ff ff55 bl 8002794 <I2Cx_Init>
}
80028ea: bf00 nop
80028ec: bd80 pop {r7, pc}
80028ee: bf00 nop
80028f0: 20000390 .word 0x20000390
080028f4 <TS_IO_Write>:
* @param Reg: Reg address
* @param Value: Data to be written
* @retval None
*/
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
{
80028f4: b580 push {r7, lr}
80028f6: b084 sub sp, #16
80028f8: af02 add r7, sp, #8
80028fa: 4603 mov r3, r0
80028fc: 71fb strb r3, [r7, #7]
80028fe: 460b mov r3, r1
8002900: 71bb strb r3, [r7, #6]
8002902: 4613 mov r3, r2
8002904: 717b strb r3, [r7, #5]
I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
8002906: 79bb ldrb r3, [r7, #6]
8002908: b29a uxth r2, r3
800290a: 79f9 ldrb r1, [r7, #7]
800290c: 2301 movs r3, #1
800290e: 9301 str r3, [sp, #4]
8002910: 1d7b adds r3, r7, #5
8002912: 9300 str r3, [sp, #0]
8002914: 2301 movs r3, #1
8002916: 4803 ldr r0, [pc, #12] ; (8002924 <TS_IO_Write+0x30>)
8002918: f7ff ffa5 bl 8002866 <I2Cx_WriteMultiple>
}
800291c: bf00 nop
800291e: 3708 adds r7, #8
8002920: 46bd mov sp, r7
8002922: bd80 pop {r7, pc}
8002924: 20000390 .word 0x20000390
08002928 <TS_IO_Read>:
* @param Addr: I2C address
* @param Reg: Reg address
* @retval Data to be read
*/
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
{
8002928: b580 push {r7, lr}
800292a: b086 sub sp, #24
800292c: af02 add r7, sp, #8
800292e: 4603 mov r3, r0
8002930: 460a mov r2, r1
8002932: 71fb strb r3, [r7, #7]
8002934: 4613 mov r3, r2
8002936: 71bb strb r3, [r7, #6]
uint8_t read_value = 0;
8002938: 2300 movs r3, #0
800293a: 73fb strb r3, [r7, #15]
I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
800293c: 79bb ldrb r3, [r7, #6]
800293e: b29a uxth r2, r3
8002940: 79f9 ldrb r1, [r7, #7]
8002942: 2301 movs r3, #1
8002944: 9301 str r3, [sp, #4]
8002946: f107 030f add.w r3, r7, #15
800294a: 9300 str r3, [sp, #0]
800294c: 2301 movs r3, #1
800294e: 4804 ldr r0, [pc, #16] ; (8002960 <TS_IO_Read+0x38>)
8002950: f7ff ff5c bl 800280c <I2Cx_ReadMultiple>
return read_value;
8002954: 7bfb ldrb r3, [r7, #15]
}
8002956: 4618 mov r0, r3
8002958: 3710 adds r7, #16
800295a: 46bd mov sp, r7
800295c: bd80 pop {r7, pc}
800295e: bf00 nop
8002960: 20000390 .word 0x20000390
08002964 <TS_IO_Delay>:
* @brief TS delay
* @param Delay: Delay in ms
* @retval None
*/
void TS_IO_Delay(uint32_t Delay)
{
8002964: b580 push {r7, lr}
8002966: b082 sub sp, #8
8002968: af00 add r7, sp, #0
800296a: 6078 str r0, [r7, #4]
HAL_Delay(Delay);
800296c: 6878 ldr r0, [r7, #4]
800296e: f002 f823 bl 80049b8 <HAL_Delay>
}
8002972: bf00 nop
8002974: 3708 adds r7, #8
8002976: 46bd mov sp, r7
8002978: bd80 pop {r7, pc}
...
0800297c <BSP_LCD_Init>:
/**
* @brief Initializes the LCD.
* @retval LCD state
*/
uint8_t BSP_LCD_Init(void)
{
800297c: b580 push {r7, lr}
800297e: af00 add r7, sp, #0
/* Select the used LCD */
/* The RK043FN48H LCD 480x272 is selected */
/* Timing Configuration */
hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
8002980: 4b31 ldr r3, [pc, #196] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002982: 2228 movs r2, #40 ; 0x28
8002984: 615a str r2, [r3, #20]
hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
8002986: 4b30 ldr r3, [pc, #192] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002988: 2209 movs r2, #9
800298a: 619a str r2, [r3, #24]
hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
800298c: 4b2e ldr r3, [pc, #184] ; (8002a48 <BSP_LCD_Init+0xcc>)
800298e: 2235 movs r2, #53 ; 0x35
8002990: 61da str r2, [r3, #28]
hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
8002992: 4b2d ldr r3, [pc, #180] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002994: 220b movs r2, #11
8002996: 621a str r2, [r3, #32]
hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
8002998: 4b2b ldr r3, [pc, #172] ; (8002a48 <BSP_LCD_Init+0xcc>)
800299a: f240 121b movw r2, #283 ; 0x11b
800299e: 629a str r2, [r3, #40] ; 0x28
hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
80029a0: 4b29 ldr r3, [pc, #164] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029a2: f240 2215 movw r2, #533 ; 0x215
80029a6: 625a str r2, [r3, #36] ; 0x24
hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
80029a8: 4b27 ldr r3, [pc, #156] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029aa: f240 121d movw r2, #285 ; 0x11d
80029ae: 631a str r2, [r3, #48] ; 0x30
hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
80029b0: 4b25 ldr r3, [pc, #148] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029b2: f240 2235 movw r2, #565 ; 0x235
80029b6: 62da str r2, [r3, #44] ; 0x2c
/* LCD clock configuration */
BSP_LCD_ClockConfig(&hLtdcHandler, NULL);
80029b8: 2100 movs r1, #0
80029ba: 4823 ldr r0, [pc, #140] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029bc: f000 fdb2 bl 8003524 <BSP_LCD_ClockConfig>
/* Initialize the LCD pixel width and pixel height */
hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH;
80029c0: 4b21 ldr r3, [pc, #132] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029c2: f44f 72f0 mov.w r2, #480 ; 0x1e0
80029c6: 661a str r2, [r3, #96] ; 0x60
hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;
80029c8: 4b1f ldr r3, [pc, #124] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029ca: f44f 7288 mov.w r2, #272 ; 0x110
80029ce: 665a str r2, [r3, #100] ; 0x64
/* Background value */
hLtdcHandler.Init.Backcolor.Blue = 0;
80029d0: 4b1d ldr r3, [pc, #116] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029d2: 2200 movs r2, #0
80029d4: f883 2034 strb.w r2, [r3, #52] ; 0x34
hLtdcHandler.Init.Backcolor.Green = 0;
80029d8: 4b1b ldr r3, [pc, #108] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029da: 2200 movs r2, #0
80029dc: f883 2035 strb.w r2, [r3, #53] ; 0x35
hLtdcHandler.Init.Backcolor.Red = 0;
80029e0: 4b19 ldr r3, [pc, #100] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029e2: 2200 movs r2, #0
80029e4: f883 2036 strb.w r2, [r3, #54] ; 0x36
/* Polarity */
hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL;
80029e8: 4b17 ldr r3, [pc, #92] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029ea: 2200 movs r2, #0
80029ec: 605a str r2, [r3, #4]
hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL;
80029ee: 4b16 ldr r3, [pc, #88] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029f0: 2200 movs r2, #0
80029f2: 609a str r2, [r3, #8]
hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80029f4: 4b14 ldr r3, [pc, #80] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029f6: 2200 movs r2, #0
80029f8: 60da str r2, [r3, #12]
hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80029fa: 4b13 ldr r3, [pc, #76] ; (8002a48 <BSP_LCD_Init+0xcc>)
80029fc: 2200 movs r2, #0
80029fe: 611a str r2, [r3, #16]
hLtdcHandler.Instance = LTDC;
8002a00: 4b11 ldr r3, [pc, #68] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002a02: 4a12 ldr r2, [pc, #72] ; (8002a4c <BSP_LCD_Init+0xd0>)
8002a04: 601a str r2, [r3, #0]
if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET)
8002a06: 4810 ldr r0, [pc, #64] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002a08: f005 fd2c bl 8008464 <HAL_LTDC_GetState>
8002a0c: 4603 mov r3, r0
8002a0e: 2b00 cmp r3, #0
8002a10: d103 bne.n 8002a1a <BSP_LCD_Init+0x9e>
{
/* Initialize the LCD Msp: this __weak function can be rewritten by the application */
BSP_LCD_MspInit(&hLtdcHandler, NULL);
8002a12: 2100 movs r1, #0
8002a14: 480c ldr r0, [pc, #48] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002a16: f000 fcab bl 8003370 <BSP_LCD_MspInit>
}
HAL_LTDC_Init(&hLtdcHandler);
8002a1a: 480b ldr r0, [pc, #44] ; (8002a48 <BSP_LCD_Init+0xcc>)
8002a1c: f005 fb52 bl 80080c4 <HAL_LTDC_Init>
/* Assert display enable LCD_DISP pin */
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
8002a20: 2201 movs r2, #1
8002a22: f44f 5180 mov.w r1, #4096 ; 0x1000
8002a26: 480a ldr r0, [pc, #40] ; (8002a50 <BSP_LCD_Init+0xd4>)
8002a28: f004 fdd4 bl 80075d4 <HAL_GPIO_WritePin>
/* Assert backlight LCD_BL_CTRL pin */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
8002a2c: 2201 movs r2, #1
8002a2e: 2108 movs r1, #8
8002a30: 4808 ldr r0, [pc, #32] ; (8002a54 <BSP_LCD_Init+0xd8>)
8002a32: f004 fdcf bl 80075d4 <HAL_GPIO_WritePin>
#if !defined(DATA_IN_ExtSDRAM)
/* Initialize the SDRAM */
BSP_SDRAM_Init();
8002a36: f000 fe21 bl 800367c <BSP_SDRAM_Init>
#endif
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
8002a3a: 4807 ldr r0, [pc, #28] ; (8002a58 <BSP_LCD_Init+0xdc>)
8002a3c: f000 f8d8 bl 8002bf0 <BSP_LCD_SetFont>
return LCD_OK;
8002a40: 2300 movs r3, #0
}
8002a42: 4618 mov r0, r3
8002a44: bd80 pop {r7, pc}
8002a46: bf00 nop
8002a48: 20008c34 .word 0x20008c34
8002a4c: 40016800 .word 0x40016800
8002a50: 40022000 .word 0x40022000
8002a54: 40022800 .word 0x40022800
8002a58: 20000050 .word 0x20000050
08002a5c <BSP_LCD_GetXSize>:
/**
* @brief Gets the LCD X size.
* @retval Used LCD X size
*/
uint32_t BSP_LCD_GetXSize(void)
{
8002a5c: b480 push {r7}
8002a5e: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth;
8002a60: 4b06 ldr r3, [pc, #24] ; (8002a7c <BSP_LCD_GetXSize+0x20>)
8002a62: 681b ldr r3, [r3, #0]
8002a64: 4a06 ldr r2, [pc, #24] ; (8002a80 <BSP_LCD_GetXSize+0x24>)
8002a66: 2134 movs r1, #52 ; 0x34
8002a68: fb01 f303 mul.w r3, r1, r3
8002a6c: 4413 add r3, r2
8002a6e: 3360 adds r3, #96 ; 0x60
8002a70: 681b ldr r3, [r3, #0]
}
8002a72: 4618 mov r0, r3
8002a74: 46bd mov sp, r7
8002a76: f85d 7b04 ldr.w r7, [sp], #4
8002a7a: 4770 bx lr
8002a7c: 2000041c .word 0x2000041c
8002a80: 20008c34 .word 0x20008c34
08002a84 <BSP_LCD_GetYSize>:
/**
* @brief Gets the LCD Y size.
* @retval Used LCD Y size
*/
uint32_t BSP_LCD_GetYSize(void)
{
8002a84: b480 push {r7}
8002a86: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight;
8002a88: 4b06 ldr r3, [pc, #24] ; (8002aa4 <BSP_LCD_GetYSize+0x20>)
8002a8a: 681b ldr r3, [r3, #0]
8002a8c: 4a06 ldr r2, [pc, #24] ; (8002aa8 <BSP_LCD_GetYSize+0x24>)
8002a8e: 2134 movs r1, #52 ; 0x34
8002a90: fb01 f303 mul.w r3, r1, r3
8002a94: 4413 add r3, r2
8002a96: 3364 adds r3, #100 ; 0x64
8002a98: 681b ldr r3, [r3, #0]
}
8002a9a: 4618 mov r0, r3
8002a9c: 46bd mov sp, r7
8002a9e: f85d 7b04 ldr.w r7, [sp], #4
8002aa2: 4770 bx lr
8002aa4: 2000041c .word 0x2000041c
8002aa8: 20008c34 .word 0x20008c34
08002aac <BSP_LCD_LayerDefaultInit>:
* @param LayerIndex: Layer foreground or background
* @param FB_Address: Layer frame buffer
* @retval None
*/
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
{
8002aac: b580 push {r7, lr}
8002aae: b090 sub sp, #64 ; 0x40
8002ab0: af00 add r7, sp, #0
8002ab2: 4603 mov r3, r0
8002ab4: 6039 str r1, [r7, #0]
8002ab6: 80fb strh r3, [r7, #6]
LCD_LayerCfgTypeDef layer_cfg;
/* Layer Init */
layer_cfg.WindowX0 = 0;
8002ab8: 2300 movs r3, #0
8002aba: 60fb str r3, [r7, #12]
layer_cfg.WindowX1 = BSP_LCD_GetXSize();
8002abc: f7ff ffce bl 8002a5c <BSP_LCD_GetXSize>
8002ac0: 4603 mov r3, r0
8002ac2: 613b str r3, [r7, #16]
layer_cfg.WindowY0 = 0;
8002ac4: 2300 movs r3, #0
8002ac6: 617b str r3, [r7, #20]
layer_cfg.WindowY1 = BSP_LCD_GetYSize();
8002ac8: f7ff ffdc bl 8002a84 <BSP_LCD_GetYSize>
8002acc: 4603 mov r3, r0
8002ace: 61bb str r3, [r7, #24]
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
8002ad0: 2300 movs r3, #0
8002ad2: 61fb str r3, [r7, #28]
layer_cfg.FBStartAdress = FB_Address;
8002ad4: 683b ldr r3, [r7, #0]
8002ad6: 633b str r3, [r7, #48] ; 0x30
layer_cfg.Alpha = 255;
8002ad8: 23ff movs r3, #255 ; 0xff
8002ada: 623b str r3, [r7, #32]
layer_cfg.Alpha0 = 0;
8002adc: 2300 movs r3, #0
8002ade: 627b str r3, [r7, #36] ; 0x24
layer_cfg.Backcolor.Blue = 0;
8002ae0: 2300 movs r3, #0
8002ae2: f887 303c strb.w r3, [r7, #60] ; 0x3c
layer_cfg.Backcolor.Green = 0;
8002ae6: 2300 movs r3, #0
8002ae8: f887 303d strb.w r3, [r7, #61] ; 0x3d
layer_cfg.Backcolor.Red = 0;
8002aec: 2300 movs r3, #0
8002aee: f887 303e strb.w r3, [r7, #62] ; 0x3e
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8002af2: f44f 63c0 mov.w r3, #1536 ; 0x600
8002af6: 62bb str r3, [r7, #40] ; 0x28
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8002af8: 2307 movs r3, #7
8002afa: 62fb str r3, [r7, #44] ; 0x2c
layer_cfg.ImageWidth = BSP_LCD_GetXSize();
8002afc: f7ff ffae bl 8002a5c <BSP_LCD_GetXSize>
8002b00: 4603 mov r3, r0
8002b02: 637b str r3, [r7, #52] ; 0x34
layer_cfg.ImageHeight = BSP_LCD_GetYSize();
8002b04: f7ff ffbe bl 8002a84 <BSP_LCD_GetYSize>
8002b08: 4603 mov r3, r0
8002b0a: 63bb str r3, [r7, #56] ; 0x38
HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex);
8002b0c: 88fa ldrh r2, [r7, #6]
8002b0e: f107 030c add.w r3, r7, #12
8002b12: 4619 mov r1, r3
8002b14: 4812 ldr r0, [pc, #72] ; (8002b60 <BSP_LCD_LayerDefaultInit+0xb4>)
8002b16: f005 fc67 bl 80083e8 <HAL_LTDC_ConfigLayer>
DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
8002b1a: 88fa ldrh r2, [r7, #6]
8002b1c: 4911 ldr r1, [pc, #68] ; (8002b64 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b1e: 4613 mov r3, r2
8002b20: 005b lsls r3, r3, #1
8002b22: 4413 add r3, r2
8002b24: 009b lsls r3, r3, #2
8002b26: 440b add r3, r1
8002b28: 3304 adds r3, #4
8002b2a: f04f 32ff mov.w r2, #4294967295
8002b2e: 601a str r2, [r3, #0]
DrawProp[LayerIndex].pFont = &Font24;
8002b30: 88fa ldrh r2, [r7, #6]
8002b32: 490c ldr r1, [pc, #48] ; (8002b64 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b34: 4613 mov r3, r2
8002b36: 005b lsls r3, r3, #1
8002b38: 4413 add r3, r2
8002b3a: 009b lsls r3, r3, #2
8002b3c: 440b add r3, r1
8002b3e: 3308 adds r3, #8
8002b40: 4a09 ldr r2, [pc, #36] ; (8002b68 <BSP_LCD_LayerDefaultInit+0xbc>)
8002b42: 601a str r2, [r3, #0]
DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
8002b44: 88fa ldrh r2, [r7, #6]
8002b46: 4907 ldr r1, [pc, #28] ; (8002b64 <BSP_LCD_LayerDefaultInit+0xb8>)
8002b48: 4613 mov r3, r2
8002b4a: 005b lsls r3, r3, #1
8002b4c: 4413 add r3, r2
8002b4e: 009b lsls r3, r3, #2
8002b50: 440b add r3, r1
8002b52: f04f 427f mov.w r2, #4278190080 ; 0xff000000
8002b56: 601a str r2, [r3, #0]
}
8002b58: bf00 nop
8002b5a: 3740 adds r7, #64 ; 0x40
8002b5c: 46bd mov sp, r7
8002b5e: bd80 pop {r7, pc}
8002b60: 20008c34 .word 0x20008c34
8002b64: 20000420 .word 0x20000420
8002b68: 20000050 .word 0x20000050
08002b6c <BSP_LCD_SelectLayer>:
* @brief Selects the LCD Layer.
* @param LayerIndex: Layer foreground or background
* @retval None
*/
void BSP_LCD_SelectLayer(uint32_t LayerIndex)
{
8002b6c: b480 push {r7}
8002b6e: b083 sub sp, #12
8002b70: af00 add r7, sp, #0
8002b72: 6078 str r0, [r7, #4]
ActiveLayer = LayerIndex;
8002b74: 4a04 ldr r2, [pc, #16] ; (8002b88 <BSP_LCD_SelectLayer+0x1c>)
8002b76: 687b ldr r3, [r7, #4]
8002b78: 6013 str r3, [r2, #0]
}
8002b7a: bf00 nop
8002b7c: 370c adds r7, #12
8002b7e: 46bd mov sp, r7
8002b80: f85d 7b04 ldr.w r7, [sp], #4
8002b84: 4770 bx lr
8002b86: bf00 nop
8002b88: 2000041c .word 0x2000041c
08002b8c <BSP_LCD_SetTextColor>:
* @brief Sets the LCD text color.
* @param Color: Text color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetTextColor(uint32_t Color)
{
8002b8c: b480 push {r7}
8002b8e: b083 sub sp, #12
8002b90: af00 add r7, sp, #0
8002b92: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].TextColor = Color;
8002b94: 4b07 ldr r3, [pc, #28] ; (8002bb4 <BSP_LCD_SetTextColor+0x28>)
8002b96: 681a ldr r2, [r3, #0]
8002b98: 4907 ldr r1, [pc, #28] ; (8002bb8 <BSP_LCD_SetTextColor+0x2c>)
8002b9a: 4613 mov r3, r2
8002b9c: 005b lsls r3, r3, #1
8002b9e: 4413 add r3, r2
8002ba0: 009b lsls r3, r3, #2
8002ba2: 440b add r3, r1
8002ba4: 687a ldr r2, [r7, #4]
8002ba6: 601a str r2, [r3, #0]
}
8002ba8: bf00 nop
8002baa: 370c adds r7, #12
8002bac: 46bd mov sp, r7
8002bae: f85d 7b04 ldr.w r7, [sp], #4
8002bb2: 4770 bx lr
8002bb4: 2000041c .word 0x2000041c
8002bb8: 20000420 .word 0x20000420
08002bbc <BSP_LCD_SetBackColor>:
* @brief Sets the LCD background color.
* @param Color: Layer background color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetBackColor(uint32_t Color)
{
8002bbc: b480 push {r7}
8002bbe: b083 sub sp, #12
8002bc0: af00 add r7, sp, #0
8002bc2: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].BackColor = Color;
8002bc4: 4b08 ldr r3, [pc, #32] ; (8002be8 <BSP_LCD_SetBackColor+0x2c>)
8002bc6: 681a ldr r2, [r3, #0]
8002bc8: 4908 ldr r1, [pc, #32] ; (8002bec <BSP_LCD_SetBackColor+0x30>)
8002bca: 4613 mov r3, r2
8002bcc: 005b lsls r3, r3, #1
8002bce: 4413 add r3, r2
8002bd0: 009b lsls r3, r3, #2
8002bd2: 440b add r3, r1
8002bd4: 3304 adds r3, #4
8002bd6: 687a ldr r2, [r7, #4]
8002bd8: 601a str r2, [r3, #0]
}
8002bda: bf00 nop
8002bdc: 370c adds r7, #12
8002bde: 46bd mov sp, r7
8002be0: f85d 7b04 ldr.w r7, [sp], #4
8002be4: 4770 bx lr
8002be6: bf00 nop
8002be8: 2000041c .word 0x2000041c
8002bec: 20000420 .word 0x20000420
08002bf0 <BSP_LCD_SetFont>:
* @brief Sets the LCD text font.
* @param fonts: Layer font to be used
* @retval None
*/
void BSP_LCD_SetFont(sFONT *fonts)
{
8002bf0: b480 push {r7}
8002bf2: b083 sub sp, #12
8002bf4: af00 add r7, sp, #0
8002bf6: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].pFont = fonts;
8002bf8: 4b08 ldr r3, [pc, #32] ; (8002c1c <BSP_LCD_SetFont+0x2c>)
8002bfa: 681a ldr r2, [r3, #0]
8002bfc: 4908 ldr r1, [pc, #32] ; (8002c20 <BSP_LCD_SetFont+0x30>)
8002bfe: 4613 mov r3, r2
8002c00: 005b lsls r3, r3, #1
8002c02: 4413 add r3, r2
8002c04: 009b lsls r3, r3, #2
8002c06: 440b add r3, r1
8002c08: 3308 adds r3, #8
8002c0a: 687a ldr r2, [r7, #4]
8002c0c: 601a str r2, [r3, #0]
}
8002c0e: bf00 nop
8002c10: 370c adds r7, #12
8002c12: 46bd mov sp, r7
8002c14: f85d 7b04 ldr.w r7, [sp], #4
8002c18: 4770 bx lr
8002c1a: bf00 nop
8002c1c: 2000041c .word 0x2000041c
8002c20: 20000420 .word 0x20000420
08002c24 <BSP_LCD_Clear>:
* @brief Clears the hole LCD.
* @param Color: Color of the background
* @retval None
*/
void BSP_LCD_Clear(uint32_t Color)
{
8002c24: b5f0 push {r4, r5, r6, r7, lr}
8002c26: b085 sub sp, #20
8002c28: af02 add r7, sp, #8
8002c2a: 6078 str r0, [r7, #4]
/* Clear the LCD */
LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
8002c2c: 4b0f ldr r3, [pc, #60] ; (8002c6c <BSP_LCD_Clear+0x48>)
8002c2e: 681c ldr r4, [r3, #0]
8002c30: 4b0e ldr r3, [pc, #56] ; (8002c6c <BSP_LCD_Clear+0x48>)
8002c32: 681b ldr r3, [r3, #0]
8002c34: 4a0e ldr r2, [pc, #56] ; (8002c70 <BSP_LCD_Clear+0x4c>)
8002c36: 2134 movs r1, #52 ; 0x34
8002c38: fb01 f303 mul.w r3, r1, r3
8002c3c: 4413 add r3, r2
8002c3e: 335c adds r3, #92 ; 0x5c
8002c40: 681b ldr r3, [r3, #0]
8002c42: 461d mov r5, r3
8002c44: f7ff ff0a bl 8002a5c <BSP_LCD_GetXSize>
8002c48: 4606 mov r6, r0
8002c4a: f7ff ff1b bl 8002a84 <BSP_LCD_GetYSize>
8002c4e: 4602 mov r2, r0
8002c50: 687b ldr r3, [r7, #4]
8002c52: 9301 str r3, [sp, #4]
8002c54: 2300 movs r3, #0
8002c56: 9300 str r3, [sp, #0]
8002c58: 4613 mov r3, r2
8002c5a: 4632 mov r2, r6
8002c5c: 4629 mov r1, r5
8002c5e: 4620 mov r0, r4
8002c60: f000 fc7c bl 800355c <LL_FillBuffer>
}
8002c64: bf00 nop
8002c66: 370c adds r7, #12
8002c68: 46bd mov sp, r7
8002c6a: bdf0 pop {r4, r5, r6, r7, pc}
8002c6c: 2000041c .word 0x2000041c
8002c70: 20008c34 .word 0x20008c34
08002c74 <BSP_LCD_DrawHLine>:
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
8002c74: b5b0 push {r4, r5, r7, lr}
8002c76: b086 sub sp, #24
8002c78: af02 add r7, sp, #8
8002c7a: 4603 mov r3, r0
8002c7c: 80fb strh r3, [r7, #6]
8002c7e: 460b mov r3, r1
8002c80: 80bb strh r3, [r7, #4]
8002c82: 4613 mov r3, r2
8002c84: 807b strh r3, [r7, #2]
uint32_t Xaddress = 0;
8002c86: 2300 movs r3, #0
8002c88: 60fb str r3, [r7, #12]
/* Get the line address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002c8a: 4b26 ldr r3, [pc, #152] ; (8002d24 <BSP_LCD_DrawHLine+0xb0>)
8002c8c: 681b ldr r3, [r3, #0]
8002c8e: 4a26 ldr r2, [pc, #152] ; (8002d28 <BSP_LCD_DrawHLine+0xb4>)
8002c90: 2134 movs r1, #52 ; 0x34
8002c92: fb01 f303 mul.w r3, r1, r3
8002c96: 4413 add r3, r2
8002c98: 3348 adds r3, #72 ; 0x48
8002c9a: 681b ldr r3, [r3, #0]
8002c9c: 2b02 cmp r3, #2
8002c9e: d114 bne.n 8002cca <BSP_LCD_DrawHLine+0x56>
{ /* RGB565 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002ca0: 4b20 ldr r3, [pc, #128] ; (8002d24 <BSP_LCD_DrawHLine+0xb0>)
8002ca2: 681b ldr r3, [r3, #0]
8002ca4: 4a20 ldr r2, [pc, #128] ; (8002d28 <BSP_LCD_DrawHLine+0xb4>)
8002ca6: 2134 movs r1, #52 ; 0x34
8002ca8: fb01 f303 mul.w r3, r1, r3
8002cac: 4413 add r3, r2
8002cae: 335c adds r3, #92 ; 0x5c
8002cb0: 681c ldr r4, [r3, #0]
8002cb2: f7ff fed3 bl 8002a5c <BSP_LCD_GetXSize>
8002cb6: 4602 mov r2, r0
8002cb8: 88bb ldrh r3, [r7, #4]
8002cba: fb03 f202 mul.w r2, r3, r2
8002cbe: 88fb ldrh r3, [r7, #6]
8002cc0: 4413 add r3, r2
8002cc2: 005b lsls r3, r3, #1
8002cc4: 4423 add r3, r4
8002cc6: 60fb str r3, [r7, #12]
8002cc8: e013 b.n 8002cf2 <BSP_LCD_DrawHLine+0x7e>
}
else
{ /* ARGB8888 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
8002cca: 4b16 ldr r3, [pc, #88] ; (8002d24 <BSP_LCD_DrawHLine+0xb0>)
8002ccc: 681b ldr r3, [r3, #0]
8002cce: 4a16 ldr r2, [pc, #88] ; (8002d28 <BSP_LCD_DrawHLine+0xb4>)
8002cd0: 2134 movs r1, #52 ; 0x34
8002cd2: fb01 f303 mul.w r3, r1, r3
8002cd6: 4413 add r3, r2
8002cd8: 335c adds r3, #92 ; 0x5c
8002cda: 681c ldr r4, [r3, #0]
8002cdc: f7ff febe bl 8002a5c <BSP_LCD_GetXSize>
8002ce0: 4602 mov r2, r0
8002ce2: 88bb ldrh r3, [r7, #4]
8002ce4: fb03 f202 mul.w r2, r3, r2
8002ce8: 88fb ldrh r3, [r7, #6]
8002cea: 4413 add r3, r2
8002cec: 009b lsls r3, r3, #2
8002cee: 4423 add r3, r4
8002cf0: 60fb str r3, [r7, #12]
}
/* Write line */
LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
8002cf2: 4b0c ldr r3, [pc, #48] ; (8002d24 <BSP_LCD_DrawHLine+0xb0>)
8002cf4: 6818 ldr r0, [r3, #0]
8002cf6: 68fc ldr r4, [r7, #12]
8002cf8: 887d ldrh r5, [r7, #2]
8002cfa: 4b0a ldr r3, [pc, #40] ; (8002d24 <BSP_LCD_DrawHLine+0xb0>)
8002cfc: 681a ldr r2, [r3, #0]
8002cfe: 490b ldr r1, [pc, #44] ; (8002d2c <BSP_LCD_DrawHLine+0xb8>)
8002d00: 4613 mov r3, r2
8002d02: 005b lsls r3, r3, #1
8002d04: 4413 add r3, r2
8002d06: 009b lsls r3, r3, #2
8002d08: 440b add r3, r1
8002d0a: 681b ldr r3, [r3, #0]
8002d0c: 9301 str r3, [sp, #4]
8002d0e: 2300 movs r3, #0
8002d10: 9300 str r3, [sp, #0]
8002d12: 2301 movs r3, #1
8002d14: 462a mov r2, r5
8002d16: 4621 mov r1, r4
8002d18: f000 fc20 bl 800355c <LL_FillBuffer>
}
8002d1c: bf00 nop
8002d1e: 3710 adds r7, #16
8002d20: 46bd mov sp, r7
8002d22: bdb0 pop {r4, r5, r7, pc}
8002d24: 2000041c .word 0x2000041c
8002d28: 20008c34 .word 0x20008c34
8002d2c: 20000420 .word 0x20000420
08002d30 <BSP_LCD_DrawCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
8002d30: b590 push {r4, r7, lr}
8002d32: b087 sub sp, #28
8002d34: af00 add r7, sp, #0
8002d36: 4603 mov r3, r0
8002d38: 80fb strh r3, [r7, #6]
8002d3a: 460b mov r3, r1
8002d3c: 80bb strh r3, [r7, #4]
8002d3e: 4613 mov r3, r2
8002d40: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
8002d42: 887b ldrh r3, [r7, #2]
8002d44: 005b lsls r3, r3, #1
8002d46: f1c3 0303 rsb r3, r3, #3
8002d4a: 617b str r3, [r7, #20]
current_x = 0;
8002d4c: 2300 movs r3, #0
8002d4e: 613b str r3, [r7, #16]
current_y = Radius;
8002d50: 887b ldrh r3, [r7, #2]
8002d52: 60fb str r3, [r7, #12]
while (current_x <= current_y)
8002d54: e0cf b.n 8002ef6 <BSP_LCD_DrawCircle+0x1c6>
{
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002d56: 693b ldr r3, [r7, #16]
8002d58: b29a uxth r2, r3
8002d5a: 88fb ldrh r3, [r7, #6]
8002d5c: 4413 add r3, r2
8002d5e: b298 uxth r0, r3
8002d60: 68fb ldr r3, [r7, #12]
8002d62: b29b uxth r3, r3
8002d64: 88ba ldrh r2, [r7, #4]
8002d66: 1ad3 subs r3, r2, r3
8002d68: b29c uxth r4, r3
8002d6a: 4b67 ldr r3, [pc, #412] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002d6c: 681a ldr r2, [r3, #0]
8002d6e: 4967 ldr r1, [pc, #412] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002d70: 4613 mov r3, r2
8002d72: 005b lsls r3, r3, #1
8002d74: 4413 add r3, r2
8002d76: 009b lsls r3, r3, #2
8002d78: 440b add r3, r1
8002d7a: 681b ldr r3, [r3, #0]
8002d7c: 461a mov r2, r3
8002d7e: 4621 mov r1, r4
8002d80: f000 f8c6 bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
8002d84: 693b ldr r3, [r7, #16]
8002d86: b29b uxth r3, r3
8002d88: 88fa ldrh r2, [r7, #6]
8002d8a: 1ad3 subs r3, r2, r3
8002d8c: b298 uxth r0, r3
8002d8e: 68fb ldr r3, [r7, #12]
8002d90: b29b uxth r3, r3
8002d92: 88ba ldrh r2, [r7, #4]
8002d94: 1ad3 subs r3, r2, r3
8002d96: b29c uxth r4, r3
8002d98: 4b5b ldr r3, [pc, #364] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002d9a: 681a ldr r2, [r3, #0]
8002d9c: 495b ldr r1, [pc, #364] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002d9e: 4613 mov r3, r2
8002da0: 005b lsls r3, r3, #1
8002da2: 4413 add r3, r2
8002da4: 009b lsls r3, r3, #2
8002da6: 440b add r3, r1
8002da8: 681b ldr r3, [r3, #0]
8002daa: 461a mov r2, r3
8002dac: 4621 mov r1, r4
8002dae: f000 f8af bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002db2: 68fb ldr r3, [r7, #12]
8002db4: b29a uxth r2, r3
8002db6: 88fb ldrh r3, [r7, #6]
8002db8: 4413 add r3, r2
8002dba: b298 uxth r0, r3
8002dbc: 693b ldr r3, [r7, #16]
8002dbe: b29b uxth r3, r3
8002dc0: 88ba ldrh r2, [r7, #4]
8002dc2: 1ad3 subs r3, r2, r3
8002dc4: b29c uxth r4, r3
8002dc6: 4b50 ldr r3, [pc, #320] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002dc8: 681a ldr r2, [r3, #0]
8002dca: 4950 ldr r1, [pc, #320] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002dcc: 4613 mov r3, r2
8002dce: 005b lsls r3, r3, #1
8002dd0: 4413 add r3, r2
8002dd2: 009b lsls r3, r3, #2
8002dd4: 440b add r3, r1
8002dd6: 681b ldr r3, [r3, #0]
8002dd8: 461a mov r2, r3
8002dda: 4621 mov r1, r4
8002ddc: f000 f898 bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
8002de0: 68fb ldr r3, [r7, #12]
8002de2: b29b uxth r3, r3
8002de4: 88fa ldrh r2, [r7, #6]
8002de6: 1ad3 subs r3, r2, r3
8002de8: b298 uxth r0, r3
8002dea: 693b ldr r3, [r7, #16]
8002dec: b29b uxth r3, r3
8002dee: 88ba ldrh r2, [r7, #4]
8002df0: 1ad3 subs r3, r2, r3
8002df2: b29c uxth r4, r3
8002df4: 4b44 ldr r3, [pc, #272] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002df6: 681a ldr r2, [r3, #0]
8002df8: 4944 ldr r1, [pc, #272] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002dfa: 4613 mov r3, r2
8002dfc: 005b lsls r3, r3, #1
8002dfe: 4413 add r3, r2
8002e00: 009b lsls r3, r3, #2
8002e02: 440b add r3, r1
8002e04: 681b ldr r3, [r3, #0]
8002e06: 461a mov r2, r3
8002e08: 4621 mov r1, r4
8002e0a: f000 f881 bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e0e: 693b ldr r3, [r7, #16]
8002e10: b29a uxth r2, r3
8002e12: 88fb ldrh r3, [r7, #6]
8002e14: 4413 add r3, r2
8002e16: b298 uxth r0, r3
8002e18: 68fb ldr r3, [r7, #12]
8002e1a: b29a uxth r2, r3
8002e1c: 88bb ldrh r3, [r7, #4]
8002e1e: 4413 add r3, r2
8002e20: b29c uxth r4, r3
8002e22: 4b39 ldr r3, [pc, #228] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002e24: 681a ldr r2, [r3, #0]
8002e26: 4939 ldr r1, [pc, #228] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002e28: 4613 mov r3, r2
8002e2a: 005b lsls r3, r3, #1
8002e2c: 4413 add r3, r2
8002e2e: 009b lsls r3, r3, #2
8002e30: 440b add r3, r1
8002e32: 681b ldr r3, [r3, #0]
8002e34: 461a mov r2, r3
8002e36: 4621 mov r1, r4
8002e38: f000 f86a bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002e3c: 693b ldr r3, [r7, #16]
8002e3e: b29b uxth r3, r3
8002e40: 88fa ldrh r2, [r7, #6]
8002e42: 1ad3 subs r3, r2, r3
8002e44: b298 uxth r0, r3
8002e46: 68fb ldr r3, [r7, #12]
8002e48: b29a uxth r2, r3
8002e4a: 88bb ldrh r3, [r7, #4]
8002e4c: 4413 add r3, r2
8002e4e: b29c uxth r4, r3
8002e50: 4b2d ldr r3, [pc, #180] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002e52: 681a ldr r2, [r3, #0]
8002e54: 492d ldr r1, [pc, #180] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002e56: 4613 mov r3, r2
8002e58: 005b lsls r3, r3, #1
8002e5a: 4413 add r3, r2
8002e5c: 009b lsls r3, r3, #2
8002e5e: 440b add r3, r1
8002e60: 681b ldr r3, [r3, #0]
8002e62: 461a mov r2, r3
8002e64: 4621 mov r1, r4
8002e66: f000 f853 bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002e6a: 68fb ldr r3, [r7, #12]
8002e6c: b29a uxth r2, r3
8002e6e: 88fb ldrh r3, [r7, #6]
8002e70: 4413 add r3, r2
8002e72: b298 uxth r0, r3
8002e74: 693b ldr r3, [r7, #16]
8002e76: b29a uxth r2, r3
8002e78: 88bb ldrh r3, [r7, #4]
8002e7a: 4413 add r3, r2
8002e7c: b29c uxth r4, r3
8002e7e: 4b22 ldr r3, [pc, #136] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002e80: 681a ldr r2, [r3, #0]
8002e82: 4922 ldr r1, [pc, #136] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002e84: 4613 mov r3, r2
8002e86: 005b lsls r3, r3, #1
8002e88: 4413 add r3, r2
8002e8a: 009b lsls r3, r3, #2
8002e8c: 440b add r3, r1
8002e8e: 681b ldr r3, [r3, #0]
8002e90: 461a mov r2, r3
8002e92: 4621 mov r1, r4
8002e94: f000 f83c bl 8002f10 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002e98: 68fb ldr r3, [r7, #12]
8002e9a: b29b uxth r3, r3
8002e9c: 88fa ldrh r2, [r7, #6]
8002e9e: 1ad3 subs r3, r2, r3
8002ea0: b298 uxth r0, r3
8002ea2: 693b ldr r3, [r7, #16]
8002ea4: b29a uxth r2, r3
8002ea6: 88bb ldrh r3, [r7, #4]
8002ea8: 4413 add r3, r2
8002eaa: b29c uxth r4, r3
8002eac: 4b16 ldr r3, [pc, #88] ; (8002f08 <BSP_LCD_DrawCircle+0x1d8>)
8002eae: 681a ldr r2, [r3, #0]
8002eb0: 4916 ldr r1, [pc, #88] ; (8002f0c <BSP_LCD_DrawCircle+0x1dc>)
8002eb2: 4613 mov r3, r2
8002eb4: 005b lsls r3, r3, #1
8002eb6: 4413 add r3, r2
8002eb8: 009b lsls r3, r3, #2
8002eba: 440b add r3, r1
8002ebc: 681b ldr r3, [r3, #0]
8002ebe: 461a mov r2, r3
8002ec0: 4621 mov r1, r4
8002ec2: f000 f825 bl 8002f10 <BSP_LCD_DrawPixel>
if (decision < 0)
8002ec6: 697b ldr r3, [r7, #20]
8002ec8: 2b00 cmp r3, #0
8002eca: da06 bge.n 8002eda <BSP_LCD_DrawCircle+0x1aa>
{
decision += (current_x << 2) + 6;
8002ecc: 693b ldr r3, [r7, #16]
8002ece: 009a lsls r2, r3, #2
8002ed0: 697b ldr r3, [r7, #20]
8002ed2: 4413 add r3, r2
8002ed4: 3306 adds r3, #6
8002ed6: 617b str r3, [r7, #20]
8002ed8: e00a b.n 8002ef0 <BSP_LCD_DrawCircle+0x1c0>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
8002eda: 693a ldr r2, [r7, #16]
8002edc: 68fb ldr r3, [r7, #12]
8002ede: 1ad3 subs r3, r2, r3
8002ee0: 009a lsls r2, r3, #2
8002ee2: 697b ldr r3, [r7, #20]
8002ee4: 4413 add r3, r2
8002ee6: 330a adds r3, #10
8002ee8: 617b str r3, [r7, #20]
current_y--;
8002eea: 68fb ldr r3, [r7, #12]
8002eec: 3b01 subs r3, #1
8002eee: 60fb str r3, [r7, #12]
}
current_x++;
8002ef0: 693b ldr r3, [r7, #16]
8002ef2: 3301 adds r3, #1
8002ef4: 613b str r3, [r7, #16]
while (current_x <= current_y)
8002ef6: 693a ldr r2, [r7, #16]
8002ef8: 68fb ldr r3, [r7, #12]
8002efa: 429a cmp r2, r3
8002efc: f67f af2b bls.w 8002d56 <BSP_LCD_DrawCircle+0x26>
}
}
8002f00: bf00 nop
8002f02: 371c adds r7, #28
8002f04: 46bd mov sp, r7
8002f06: bd90 pop {r4, r7, pc}
8002f08: 2000041c .word 0x2000041c
8002f0c: 20000420 .word 0x20000420
08002f10 <BSP_LCD_DrawPixel>:
* @param Ypos: Y position
* @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)
* @retval None
*/
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
{
8002f10: b5b0 push {r4, r5, r7, lr}
8002f12: b082 sub sp, #8
8002f14: af00 add r7, sp, #0
8002f16: 4603 mov r3, r0
8002f18: 603a str r2, [r7, #0]
8002f1a: 80fb strh r3, [r7, #6]
8002f1c: 460b mov r3, r1
8002f1e: 80bb strh r3, [r7, #4]
/* Write data value to all SDRAM memory */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002f20: 4b1d ldr r3, [pc, #116] ; (8002f98 <BSP_LCD_DrawPixel+0x88>)
8002f22: 681b ldr r3, [r3, #0]
8002f24: 4a1d ldr r2, [pc, #116] ; (8002f9c <BSP_LCD_DrawPixel+0x8c>)
8002f26: 2134 movs r1, #52 ; 0x34
8002f28: fb01 f303 mul.w r3, r1, r3
8002f2c: 4413 add r3, r2
8002f2e: 3348 adds r3, #72 ; 0x48
8002f30: 681b ldr r3, [r3, #0]
8002f32: 2b02 cmp r3, #2
8002f34: d116 bne.n 8002f64 <BSP_LCD_DrawPixel+0x54>
{ /* RGB565 format */
*(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code;
8002f36: 4b18 ldr r3, [pc, #96] ; (8002f98 <BSP_LCD_DrawPixel+0x88>)
8002f38: 681b ldr r3, [r3, #0]
8002f3a: 4a18 ldr r2, [pc, #96] ; (8002f9c <BSP_LCD_DrawPixel+0x8c>)
8002f3c: 2134 movs r1, #52 ; 0x34
8002f3e: fb01 f303 mul.w r3, r1, r3
8002f42: 4413 add r3, r2
8002f44: 335c adds r3, #92 ; 0x5c
8002f46: 681c ldr r4, [r3, #0]
8002f48: 88bd ldrh r5, [r7, #4]
8002f4a: f7ff fd87 bl 8002a5c <BSP_LCD_GetXSize>
8002f4e: 4603 mov r3, r0
8002f50: fb03 f205 mul.w r2, r3, r5
8002f54: 88fb ldrh r3, [r7, #6]
8002f56: 4413 add r3, r2
8002f58: 005b lsls r3, r3, #1
8002f5a: 4423 add r3, r4
8002f5c: 683a ldr r2, [r7, #0]
8002f5e: b292 uxth r2, r2
8002f60: 801a strh r2, [r3, #0]
}
else
{ /* ARGB8888 format */
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
}
}
8002f62: e015 b.n 8002f90 <BSP_LCD_DrawPixel+0x80>
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
8002f64: 4b0c ldr r3, [pc, #48] ; (8002f98 <BSP_LCD_DrawPixel+0x88>)
8002f66: 681b ldr r3, [r3, #0]
8002f68: 4a0c ldr r2, [pc, #48] ; (8002f9c <BSP_LCD_DrawPixel+0x8c>)
8002f6a: 2134 movs r1, #52 ; 0x34
8002f6c: fb01 f303 mul.w r3, r1, r3
8002f70: 4413 add r3, r2
8002f72: 335c adds r3, #92 ; 0x5c
8002f74: 681c ldr r4, [r3, #0]
8002f76: 88bd ldrh r5, [r7, #4]
8002f78: f7ff fd70 bl 8002a5c <BSP_LCD_GetXSize>
8002f7c: 4603 mov r3, r0
8002f7e: fb03 f205 mul.w r2, r3, r5
8002f82: 88fb ldrh r3, [r7, #6]
8002f84: 4413 add r3, r2
8002f86: 009b lsls r3, r3, #2
8002f88: 4423 add r3, r4
8002f8a: 461a mov r2, r3
8002f8c: 683b ldr r3, [r7, #0]
8002f8e: 6013 str r3, [r2, #0]
}
8002f90: bf00 nop
8002f92: 3708 adds r7, #8
8002f94: 46bd mov sp, r7
8002f96: bdb0 pop {r4, r5, r7, pc}
8002f98: 2000041c .word 0x2000041c
8002f9c: 20008c34 .word 0x20008c34
08002fa0 <BSP_LCD_DrawBitmap>:
* @param Ypos: Bmp Y position in the LCD
* @param pbmp: Pointer to Bmp picture address in the internal Flash
* @retval None
*/
void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
{
8002fa0: b590 push {r4, r7, lr}
8002fa2: b08b sub sp, #44 ; 0x2c
8002fa4: af00 add r7, sp, #0
8002fa6: 60f8 str r0, [r7, #12]
8002fa8: 60b9 str r1, [r7, #8]
8002faa: 607a str r2, [r7, #4]
uint32_t index = 0, width = 0, height = 0, bit_pixel = 0;
8002fac: 2300 movs r3, #0
8002fae: 627b str r3, [r7, #36] ; 0x24
8002fb0: 2300 movs r3, #0
8002fb2: 61bb str r3, [r7, #24]
8002fb4: 2300 movs r3, #0
8002fb6: 617b str r3, [r7, #20]
8002fb8: 2300 movs r3, #0
8002fba: 613b str r3, [r7, #16]
uint32_t address;
uint32_t input_color_mode = 0;
8002fbc: 2300 movs r3, #0
8002fbe: 61fb str r3, [r7, #28]
/* Get bitmap data address offset */
index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24);
8002fc0: 687b ldr r3, [r7, #4]
8002fc2: 330a adds r3, #10
8002fc4: 781b ldrb r3, [r3, #0]
8002fc6: 461a mov r2, r3
8002fc8: 687b ldr r3, [r7, #4]
8002fca: 330b adds r3, #11
8002fcc: 781b ldrb r3, [r3, #0]
8002fce: 021b lsls r3, r3, #8
8002fd0: 441a add r2, r3
8002fd2: 687b ldr r3, [r7, #4]
8002fd4: 330c adds r3, #12
8002fd6: 781b ldrb r3, [r3, #0]
8002fd8: 041b lsls r3, r3, #16
8002fda: 441a add r2, r3
8002fdc: 687b ldr r3, [r7, #4]
8002fde: 330d adds r3, #13
8002fe0: 781b ldrb r3, [r3, #0]
8002fe2: 061b lsls r3, r3, #24
8002fe4: 4413 add r3, r2
8002fe6: 627b str r3, [r7, #36] ; 0x24
/* Read bitmap width */
width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16) + (pbmp[21] << 24);
8002fe8: 687b ldr r3, [r7, #4]
8002fea: 3312 adds r3, #18
8002fec: 781b ldrb r3, [r3, #0]
8002fee: 461a mov r2, r3
8002ff0: 687b ldr r3, [r7, #4]
8002ff2: 3313 adds r3, #19
8002ff4: 781b ldrb r3, [r3, #0]
8002ff6: 021b lsls r3, r3, #8
8002ff8: 441a add r2, r3
8002ffa: 687b ldr r3, [r7, #4]
8002ffc: 3314 adds r3, #20
8002ffe: 781b ldrb r3, [r3, #0]
8003000: 041b lsls r3, r3, #16
8003002: 441a add r2, r3
8003004: 687b ldr r3, [r7, #4]
8003006: 3315 adds r3, #21
8003008: 781b ldrb r3, [r3, #0]
800300a: 061b lsls r3, r3, #24
800300c: 4413 add r3, r2
800300e: 61bb str r3, [r7, #24]
/* Read bitmap height */
height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16) + (pbmp[25] << 24);
8003010: 687b ldr r3, [r7, #4]
8003012: 3316 adds r3, #22
8003014: 781b ldrb r3, [r3, #0]
8003016: 461a mov r2, r3
8003018: 687b ldr r3, [r7, #4]
800301a: 3317 adds r3, #23
800301c: 781b ldrb r3, [r3, #0]
800301e: 021b lsls r3, r3, #8
8003020: 441a add r2, r3
8003022: 687b ldr r3, [r7, #4]
8003024: 3318 adds r3, #24
8003026: 781b ldrb r3, [r3, #0]
8003028: 041b lsls r3, r3, #16
800302a: 441a add r2, r3
800302c: 687b ldr r3, [r7, #4]
800302e: 3319 adds r3, #25
8003030: 781b ldrb r3, [r3, #0]
8003032: 061b lsls r3, r3, #24
8003034: 4413 add r3, r2
8003036: 617b str r3, [r7, #20]
/* Read bit/pixel */
bit_pixel = pbmp[28] + (pbmp[29] << 8);
8003038: 687b ldr r3, [r7, #4]
800303a: 331c adds r3, #28
800303c: 781b ldrb r3, [r3, #0]
800303e: 461a mov r2, r3
8003040: 687b ldr r3, [r7, #4]
8003042: 331d adds r3, #29
8003044: 781b ldrb r3, [r3, #0]
8003046: 021b lsls r3, r3, #8
8003048: 4413 add r3, r2
800304a: 613b str r3, [r7, #16]
/* Set the address */
address = hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4));
800304c: 4b2a ldr r3, [pc, #168] ; (80030f8 <BSP_LCD_DrawBitmap+0x158>)
800304e: 681b ldr r3, [r3, #0]
8003050: 4a2a ldr r2, [pc, #168] ; (80030fc <BSP_LCD_DrawBitmap+0x15c>)
8003052: 2134 movs r1, #52 ; 0x34
8003054: fb01 f303 mul.w r3, r1, r3
8003058: 4413 add r3, r2
800305a: 335c adds r3, #92 ; 0x5c
800305c: 681c ldr r4, [r3, #0]
800305e: f7ff fcfd bl 8002a5c <BSP_LCD_GetXSize>
8003062: 4602 mov r2, r0
8003064: 68bb ldr r3, [r7, #8]
8003066: fb03 f202 mul.w r2, r3, r2
800306a: 68fb ldr r3, [r7, #12]
800306c: 4413 add r3, r2
800306e: 009b lsls r3, r3, #2
8003070: 4423 add r3, r4
8003072: 623b str r3, [r7, #32]
/* Get the layer pixel format */
if ((bit_pixel/8) == 4)
8003074: 693b ldr r3, [r7, #16]
8003076: 3b20 subs r3, #32
8003078: 2b07 cmp r3, #7
800307a: d802 bhi.n 8003082 <BSP_LCD_DrawBitmap+0xe2>
{
input_color_mode = CM_ARGB8888;
800307c: 2300 movs r3, #0
800307e: 61fb str r3, [r7, #28]
8003080: e008 b.n 8003094 <BSP_LCD_DrawBitmap+0xf4>
}
else if ((bit_pixel/8) == 2)
8003082: 693b ldr r3, [r7, #16]
8003084: 3b10 subs r3, #16
8003086: 2b07 cmp r3, #7
8003088: d802 bhi.n 8003090 <BSP_LCD_DrawBitmap+0xf0>
{
input_color_mode = CM_RGB565;
800308a: 2302 movs r3, #2
800308c: 61fb str r3, [r7, #28]
800308e: e001 b.n 8003094 <BSP_LCD_DrawBitmap+0xf4>
}
else
{
input_color_mode = CM_RGB888;
8003090: 2301 movs r3, #1
8003092: 61fb str r3, [r7, #28]
}
/* Bypass the bitmap header */
pbmp += (index + (width * (height - 1) * (bit_pixel/8)));
8003094: 697b ldr r3, [r7, #20]
8003096: 3b01 subs r3, #1
8003098: 69ba ldr r2, [r7, #24]
800309a: fb02 f303 mul.w r3, r2, r3
800309e: 693a ldr r2, [r7, #16]
80030a0: 08d2 lsrs r2, r2, #3
80030a2: fb02 f203 mul.w r2, r2, r3
80030a6: 6a7b ldr r3, [r7, #36] ; 0x24
80030a8: 4413 add r3, r2
80030aa: 687a ldr r2, [r7, #4]
80030ac: 4413 add r3, r2
80030ae: 607b str r3, [r7, #4]
/* Convert picture to ARGB8888 pixel format */
for(index=0; index < height; index++)
80030b0: 2300 movs r3, #0
80030b2: 627b str r3, [r7, #36] ; 0x24
80030b4: e018 b.n 80030e8 <BSP_LCD_DrawBitmap+0x148>
{
/* Pixel format conversion */
LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)address, width, input_color_mode);
80030b6: 6a39 ldr r1, [r7, #32]
80030b8: 69fb ldr r3, [r7, #28]
80030ba: 69ba ldr r2, [r7, #24]
80030bc: 6878 ldr r0, [r7, #4]
80030be: f000 fa99 bl 80035f4 <LL_ConvertLineToARGB8888>
/* Increment the source and destination buffers */
address+= (BSP_LCD_GetXSize()*4);
80030c2: f7ff fccb bl 8002a5c <BSP_LCD_GetXSize>
80030c6: 4603 mov r3, r0
80030c8: 009b lsls r3, r3, #2
80030ca: 6a3a ldr r2, [r7, #32]
80030cc: 4413 add r3, r2
80030ce: 623b str r3, [r7, #32]
pbmp -= width*(bit_pixel/8);
80030d0: 693b ldr r3, [r7, #16]
80030d2: 08db lsrs r3, r3, #3
80030d4: 69ba ldr r2, [r7, #24]
80030d6: fb02 f303 mul.w r3, r2, r3
80030da: 425b negs r3, r3
80030dc: 687a ldr r2, [r7, #4]
80030de: 4413 add r3, r2
80030e0: 607b str r3, [r7, #4]
for(index=0; index < height; index++)
80030e2: 6a7b ldr r3, [r7, #36] ; 0x24
80030e4: 3301 adds r3, #1
80030e6: 627b str r3, [r7, #36] ; 0x24
80030e8: 6a7a ldr r2, [r7, #36] ; 0x24
80030ea: 697b ldr r3, [r7, #20]
80030ec: 429a cmp r2, r3
80030ee: d3e2 bcc.n 80030b6 <BSP_LCD_DrawBitmap+0x116>
}
}
80030f0: bf00 nop
80030f2: 372c adds r7, #44 ; 0x2c
80030f4: 46bd mov sp, r7
80030f6: bd90 pop {r4, r7, pc}
80030f8: 2000041c .word 0x2000041c
80030fc: 20008c34 .word 0x20008c34
08003100 <BSP_LCD_FillRect>:
* @param Width: Rectangle width
* @param Height: Rectangle height
* @retval None
*/
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
{
8003100: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8003104: b086 sub sp, #24
8003106: af02 add r7, sp, #8
8003108: 4604 mov r4, r0
800310a: 4608 mov r0, r1
800310c: 4611 mov r1, r2
800310e: 461a mov r2, r3
8003110: 4623 mov r3, r4
8003112: 80fb strh r3, [r7, #6]
8003114: 4603 mov r3, r0
8003116: 80bb strh r3, [r7, #4]
8003118: 460b mov r3, r1
800311a: 807b strh r3, [r7, #2]
800311c: 4613 mov r3, r2
800311e: 803b strh r3, [r7, #0]
uint32_t x_address = 0;
8003120: 2300 movs r3, #0
8003122: 60fb str r3, [r7, #12]
/* Set the text color */
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8003124: 4b30 ldr r3, [pc, #192] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
8003126: 681a ldr r2, [r3, #0]
8003128: 4930 ldr r1, [pc, #192] ; (80031ec <BSP_LCD_FillRect+0xec>)
800312a: 4613 mov r3, r2
800312c: 005b lsls r3, r3, #1
800312e: 4413 add r3, r2
8003130: 009b lsls r3, r3, #2
8003132: 440b add r3, r1
8003134: 681b ldr r3, [r3, #0]
8003136: 4618 mov r0, r3
8003138: f7ff fd28 bl 8002b8c <BSP_LCD_SetTextColor>
/* Get the rectangle start address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
800313c: 4b2a ldr r3, [pc, #168] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
800313e: 681b ldr r3, [r3, #0]
8003140: 4a2b ldr r2, [pc, #172] ; (80031f0 <BSP_LCD_FillRect+0xf0>)
8003142: 2134 movs r1, #52 ; 0x34
8003144: fb01 f303 mul.w r3, r1, r3
8003148: 4413 add r3, r2
800314a: 3348 adds r3, #72 ; 0x48
800314c: 681b ldr r3, [r3, #0]
800314e: 2b02 cmp r3, #2
8003150: d114 bne.n 800317c <BSP_LCD_FillRect+0x7c>
{ /* RGB565 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
8003152: 4b25 ldr r3, [pc, #148] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
8003154: 681b ldr r3, [r3, #0]
8003156: 4a26 ldr r2, [pc, #152] ; (80031f0 <BSP_LCD_FillRect+0xf0>)
8003158: 2134 movs r1, #52 ; 0x34
800315a: fb01 f303 mul.w r3, r1, r3
800315e: 4413 add r3, r2
8003160: 335c adds r3, #92 ; 0x5c
8003162: 681c ldr r4, [r3, #0]
8003164: f7ff fc7a bl 8002a5c <BSP_LCD_GetXSize>
8003168: 4602 mov r2, r0
800316a: 88bb ldrh r3, [r7, #4]
800316c: fb03 f202 mul.w r2, r3, r2
8003170: 88fb ldrh r3, [r7, #6]
8003172: 4413 add r3, r2
8003174: 005b lsls r3, r3, #1
8003176: 4423 add r3, r4
8003178: 60fb str r3, [r7, #12]
800317a: e013 b.n 80031a4 <BSP_LCD_FillRect+0xa4>
}
else
{ /* ARGB8888 format */
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
800317c: 4b1a ldr r3, [pc, #104] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
800317e: 681b ldr r3, [r3, #0]
8003180: 4a1b ldr r2, [pc, #108] ; (80031f0 <BSP_LCD_FillRect+0xf0>)
8003182: 2134 movs r1, #52 ; 0x34
8003184: fb01 f303 mul.w r3, r1, r3
8003188: 4413 add r3, r2
800318a: 335c adds r3, #92 ; 0x5c
800318c: 681c ldr r4, [r3, #0]
800318e: f7ff fc65 bl 8002a5c <BSP_LCD_GetXSize>
8003192: 4602 mov r2, r0
8003194: 88bb ldrh r3, [r7, #4]
8003196: fb03 f202 mul.w r2, r3, r2
800319a: 88fb ldrh r3, [r7, #6]
800319c: 4413 add r3, r2
800319e: 009b lsls r3, r3, #2
80031a0: 4423 add r3, r4
80031a2: 60fb str r3, [r7, #12]
}
/* Fill the rectangle */
LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);
80031a4: 4b10 ldr r3, [pc, #64] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
80031a6: 681c ldr r4, [r3, #0]
80031a8: 68fd ldr r5, [r7, #12]
80031aa: 887e ldrh r6, [r7, #2]
80031ac: f8b7 8000 ldrh.w r8, [r7]
80031b0: f7ff fc54 bl 8002a5c <BSP_LCD_GetXSize>
80031b4: 4602 mov r2, r0
80031b6: 887b ldrh r3, [r7, #2]
80031b8: 1ad1 subs r1, r2, r3
80031ba: 4b0b ldr r3, [pc, #44] ; (80031e8 <BSP_LCD_FillRect+0xe8>)
80031bc: 681a ldr r2, [r3, #0]
80031be: 480b ldr r0, [pc, #44] ; (80031ec <BSP_LCD_FillRect+0xec>)
80031c0: 4613 mov r3, r2
80031c2: 005b lsls r3, r3, #1
80031c4: 4413 add r3, r2
80031c6: 009b lsls r3, r3, #2
80031c8: 4403 add r3, r0
80031ca: 681b ldr r3, [r3, #0]
80031cc: 9301 str r3, [sp, #4]
80031ce: 9100 str r1, [sp, #0]
80031d0: 4643 mov r3, r8
80031d2: 4632 mov r2, r6
80031d4: 4629 mov r1, r5
80031d6: 4620 mov r0, r4
80031d8: f000 f9c0 bl 800355c <LL_FillBuffer>
}
80031dc: bf00 nop
80031de: 3710 adds r7, #16
80031e0: 46bd mov sp, r7
80031e2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
80031e6: bf00 nop
80031e8: 2000041c .word 0x2000041c
80031ec: 20000420 .word 0x20000420
80031f0: 20008c34 .word 0x20008c34
080031f4 <BSP_LCD_FillCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
80031f4: b580 push {r7, lr}
80031f6: b086 sub sp, #24
80031f8: af00 add r7, sp, #0
80031fa: 4603 mov r3, r0
80031fc: 80fb strh r3, [r7, #6]
80031fe: 460b mov r3, r1
8003200: 80bb strh r3, [r7, #4]
8003202: 4613 mov r3, r2
8003204: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
8003206: 887b ldrh r3, [r7, #2]
8003208: 005b lsls r3, r3, #1
800320a: f1c3 0303 rsb r3, r3, #3
800320e: 617b str r3, [r7, #20]
current_x = 0;
8003210: 2300 movs r3, #0
8003212: 613b str r3, [r7, #16]
current_y = Radius;
8003214: 887b ldrh r3, [r7, #2]
8003216: 60fb str r3, [r7, #12]
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8003218: 4b44 ldr r3, [pc, #272] ; (800332c <BSP_LCD_FillCircle+0x138>)
800321a: 681a ldr r2, [r3, #0]
800321c: 4944 ldr r1, [pc, #272] ; (8003330 <BSP_LCD_FillCircle+0x13c>)
800321e: 4613 mov r3, r2
8003220: 005b lsls r3, r3, #1
8003222: 4413 add r3, r2
8003224: 009b lsls r3, r3, #2
8003226: 440b add r3, r1
8003228: 681b ldr r3, [r3, #0]
800322a: 4618 mov r0, r3
800322c: f7ff fcae bl 8002b8c <BSP_LCD_SetTextColor>
while (current_x <= current_y)
8003230: e061 b.n 80032f6 <BSP_LCD_FillCircle+0x102>
{
if(current_y > 0)
8003232: 68fb ldr r3, [r7, #12]
8003234: 2b00 cmp r3, #0
8003236: d021 beq.n 800327c <BSP_LCD_FillCircle+0x88>
{
BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);
8003238: 68fb ldr r3, [r7, #12]
800323a: b29b uxth r3, r3
800323c: 88fa ldrh r2, [r7, #6]
800323e: 1ad3 subs r3, r2, r3
8003240: b298 uxth r0, r3
8003242: 693b ldr r3, [r7, #16]
8003244: b29a uxth r2, r3
8003246: 88bb ldrh r3, [r7, #4]
8003248: 4413 add r3, r2
800324a: b299 uxth r1, r3
800324c: 68fb ldr r3, [r7, #12]
800324e: b29b uxth r3, r3
8003250: 005b lsls r3, r3, #1
8003252: b29b uxth r3, r3
8003254: 461a mov r2, r3
8003256: f7ff fd0d bl 8002c74 <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);
800325a: 68fb ldr r3, [r7, #12]
800325c: b29b uxth r3, r3
800325e: 88fa ldrh r2, [r7, #6]
8003260: 1ad3 subs r3, r2, r3
8003262: b298 uxth r0, r3
8003264: 693b ldr r3, [r7, #16]
8003266: b29b uxth r3, r3
8003268: 88ba ldrh r2, [r7, #4]
800326a: 1ad3 subs r3, r2, r3
800326c: b299 uxth r1, r3
800326e: 68fb ldr r3, [r7, #12]
8003270: b29b uxth r3, r3
8003272: 005b lsls r3, r3, #1
8003274: b29b uxth r3, r3
8003276: 461a mov r2, r3
8003278: f7ff fcfc bl 8002c74 <BSP_LCD_DrawHLine>
}
if(current_x > 0)
800327c: 693b ldr r3, [r7, #16]
800327e: 2b00 cmp r3, #0
8003280: d021 beq.n 80032c6 <BSP_LCD_FillCircle+0xd2>
{
BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);
8003282: 693b ldr r3, [r7, #16]
8003284: b29b uxth r3, r3
8003286: 88fa ldrh r2, [r7, #6]
8003288: 1ad3 subs r3, r2, r3
800328a: b298 uxth r0, r3
800328c: 68fb ldr r3, [r7, #12]
800328e: b29b uxth r3, r3
8003290: 88ba ldrh r2, [r7, #4]
8003292: 1ad3 subs r3, r2, r3
8003294: b299 uxth r1, r3
8003296: 693b ldr r3, [r7, #16]
8003298: b29b uxth r3, r3
800329a: 005b lsls r3, r3, #1
800329c: b29b uxth r3, r3
800329e: 461a mov r2, r3
80032a0: f7ff fce8 bl 8002c74 <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);
80032a4: 693b ldr r3, [r7, #16]
80032a6: b29b uxth r3, r3
80032a8: 88fa ldrh r2, [r7, #6]
80032aa: 1ad3 subs r3, r2, r3
80032ac: b298 uxth r0, r3
80032ae: 68fb ldr r3, [r7, #12]
80032b0: b29a uxth r2, r3
80032b2: 88bb ldrh r3, [r7, #4]
80032b4: 4413 add r3, r2
80032b6: b299 uxth r1, r3
80032b8: 693b ldr r3, [r7, #16]
80032ba: b29b uxth r3, r3
80032bc: 005b lsls r3, r3, #1
80032be: b29b uxth r3, r3
80032c0: 461a mov r2, r3
80032c2: f7ff fcd7 bl 8002c74 <BSP_LCD_DrawHLine>
}
if (decision < 0)
80032c6: 697b ldr r3, [r7, #20]
80032c8: 2b00 cmp r3, #0
80032ca: da06 bge.n 80032da <BSP_LCD_FillCircle+0xe6>
{
decision += (current_x << 2) + 6;
80032cc: 693b ldr r3, [r7, #16]
80032ce: 009a lsls r2, r3, #2
80032d0: 697b ldr r3, [r7, #20]
80032d2: 4413 add r3, r2
80032d4: 3306 adds r3, #6
80032d6: 617b str r3, [r7, #20]
80032d8: e00a b.n 80032f0 <BSP_LCD_FillCircle+0xfc>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
80032da: 693a ldr r2, [r7, #16]
80032dc: 68fb ldr r3, [r7, #12]
80032de: 1ad3 subs r3, r2, r3
80032e0: 009a lsls r2, r3, #2
80032e2: 697b ldr r3, [r7, #20]
80032e4: 4413 add r3, r2
80032e6: 330a adds r3, #10
80032e8: 617b str r3, [r7, #20]
current_y--;
80032ea: 68fb ldr r3, [r7, #12]
80032ec: 3b01 subs r3, #1
80032ee: 60fb str r3, [r7, #12]
}
current_x++;
80032f0: 693b ldr r3, [r7, #16]
80032f2: 3301 adds r3, #1
80032f4: 613b str r3, [r7, #16]
while (current_x <= current_y)
80032f6: 693a ldr r2, [r7, #16]
80032f8: 68fb ldr r3, [r7, #12]
80032fa: 429a cmp r2, r3
80032fc: d999 bls.n 8003232 <BSP_LCD_FillCircle+0x3e>
}
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
80032fe: 4b0b ldr r3, [pc, #44] ; (800332c <BSP_LCD_FillCircle+0x138>)
8003300: 681a ldr r2, [r3, #0]
8003302: 490b ldr r1, [pc, #44] ; (8003330 <BSP_LCD_FillCircle+0x13c>)
8003304: 4613 mov r3, r2
8003306: 005b lsls r3, r3, #1
8003308: 4413 add r3, r2
800330a: 009b lsls r3, r3, #2
800330c: 440b add r3, r1
800330e: 681b ldr r3, [r3, #0]
8003310: 4618 mov r0, r3
8003312: f7ff fc3b bl 8002b8c <BSP_LCD_SetTextColor>
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
8003316: 887a ldrh r2, [r7, #2]
8003318: 88b9 ldrh r1, [r7, #4]
800331a: 88fb ldrh r3, [r7, #6]
800331c: 4618 mov r0, r3
800331e: f7ff fd07 bl 8002d30 <BSP_LCD_DrawCircle>
}
8003322: bf00 nop
8003324: 3718 adds r7, #24
8003326: 46bd mov sp, r7
8003328: bd80 pop {r7, pc}
800332a: bf00 nop
800332c: 2000041c .word 0x2000041c
8003330: 20000420 .word 0x20000420
08003334 <BSP_LCD_DisplayOn>:
/**
* @brief Enables the display.
* @retval None
*/
void BSP_LCD_DisplayOn(void)
{
8003334: b580 push {r7, lr}
8003336: af00 add r7, sp, #0
/* Display On */
__HAL_LTDC_ENABLE(&hLtdcHandler);
8003338: 4b0a ldr r3, [pc, #40] ; (8003364 <BSP_LCD_DisplayOn+0x30>)
800333a: 681b ldr r3, [r3, #0]
800333c: 699a ldr r2, [r3, #24]
800333e: 4b09 ldr r3, [pc, #36] ; (8003364 <BSP_LCD_DisplayOn+0x30>)
8003340: 681b ldr r3, [r3, #0]
8003342: f042 0201 orr.w r2, r2, #1
8003346: 619a str r2, [r3, #24]
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */
8003348: 2201 movs r2, #1
800334a: f44f 5180 mov.w r1, #4096 ; 0x1000
800334e: 4806 ldr r0, [pc, #24] ; (8003368 <BSP_LCD_DisplayOn+0x34>)
8003350: f004 f940 bl 80075d4 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */
8003354: 2201 movs r2, #1
8003356: 2108 movs r1, #8
8003358: 4804 ldr r0, [pc, #16] ; (800336c <BSP_LCD_DisplayOn+0x38>)
800335a: f004 f93b bl 80075d4 <HAL_GPIO_WritePin>
}
800335e: bf00 nop
8003360: bd80 pop {r7, pc}
8003362: bf00 nop
8003364: 20008c34 .word 0x20008c34
8003368: 40022000 .word 0x40022000
800336c: 40022800 .word 0x40022800
08003370 <BSP_LCD_MspInit>:
* @param hltdc: LTDC handle
* @param Params
* @retval None
*/
__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
{
8003370: b580 push {r7, lr}
8003372: b090 sub sp, #64 ; 0x40
8003374: af00 add r7, sp, #0
8003376: 6078 str r0, [r7, #4]
8003378: 6039 str r1, [r7, #0]
GPIO_InitTypeDef gpio_init_structure;
/* Enable the LTDC and DMA2D clocks */
__HAL_RCC_LTDC_CLK_ENABLE();
800337a: 4b64 ldr r3, [pc, #400] ; (800350c <BSP_LCD_MspInit+0x19c>)
800337c: 6c5b ldr r3, [r3, #68] ; 0x44
800337e: 4a63 ldr r2, [pc, #396] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003380: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8003384: 6453 str r3, [r2, #68] ; 0x44
8003386: 4b61 ldr r3, [pc, #388] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003388: 6c5b ldr r3, [r3, #68] ; 0x44
800338a: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800338e: 62bb str r3, [r7, #40] ; 0x28
8003390: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_DMA2D_CLK_ENABLE();
8003392: 4b5e ldr r3, [pc, #376] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003394: 6b1b ldr r3, [r3, #48] ; 0x30
8003396: 4a5d ldr r2, [pc, #372] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003398: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
800339c: 6313 str r3, [r2, #48] ; 0x30
800339e: 4b5b ldr r3, [pc, #364] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033a0: 6b1b ldr r3, [r3, #48] ; 0x30
80033a2: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80033a6: 627b str r3, [r7, #36] ; 0x24
80033a8: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOE_CLK_ENABLE();
80033aa: 4b58 ldr r3, [pc, #352] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033ac: 6b1b ldr r3, [r3, #48] ; 0x30
80033ae: 4a57 ldr r2, [pc, #348] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033b0: f043 0310 orr.w r3, r3, #16
80033b4: 6313 str r3, [r2, #48] ; 0x30
80033b6: 4b55 ldr r3, [pc, #340] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033b8: 6b1b ldr r3, [r3, #48] ; 0x30
80033ba: f003 0310 and.w r3, r3, #16
80033be: 623b str r3, [r7, #32]
80033c0: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOG_CLK_ENABLE();
80033c2: 4b52 ldr r3, [pc, #328] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033c4: 6b1b ldr r3, [r3, #48] ; 0x30
80033c6: 4a51 ldr r2, [pc, #324] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033c8: f043 0340 orr.w r3, r3, #64 ; 0x40
80033cc: 6313 str r3, [r2, #48] ; 0x30
80033ce: 4b4f ldr r3, [pc, #316] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033d0: 6b1b ldr r3, [r3, #48] ; 0x30
80033d2: f003 0340 and.w r3, r3, #64 ; 0x40
80033d6: 61fb str r3, [r7, #28]
80033d8: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOI_CLK_ENABLE();
80033da: 4b4c ldr r3, [pc, #304] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033dc: 6b1b ldr r3, [r3, #48] ; 0x30
80033de: 4a4b ldr r2, [pc, #300] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033e0: f443 7380 orr.w r3, r3, #256 ; 0x100
80033e4: 6313 str r3, [r2, #48] ; 0x30
80033e6: 4b49 ldr r3, [pc, #292] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033e8: 6b1b ldr r3, [r3, #48] ; 0x30
80033ea: f403 7380 and.w r3, r3, #256 ; 0x100
80033ee: 61bb str r3, [r7, #24]
80033f0: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOJ_CLK_ENABLE();
80033f2: 4b46 ldr r3, [pc, #280] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033f4: 6b1b ldr r3, [r3, #48] ; 0x30
80033f6: 4a45 ldr r2, [pc, #276] ; (800350c <BSP_LCD_MspInit+0x19c>)
80033f8: f443 7300 orr.w r3, r3, #512 ; 0x200
80033fc: 6313 str r3, [r2, #48] ; 0x30
80033fe: 4b43 ldr r3, [pc, #268] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003400: 6b1b ldr r3, [r3, #48] ; 0x30
8003402: f403 7300 and.w r3, r3, #512 ; 0x200
8003406: 617b str r3, [r7, #20]
8003408: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOK_CLK_ENABLE();
800340a: 4b40 ldr r3, [pc, #256] ; (800350c <BSP_LCD_MspInit+0x19c>)
800340c: 6b1b ldr r3, [r3, #48] ; 0x30
800340e: 4a3f ldr r2, [pc, #252] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003410: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003414: 6313 str r3, [r2, #48] ; 0x30
8003416: 4b3d ldr r3, [pc, #244] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003418: 6b1b ldr r3, [r3, #48] ; 0x30
800341a: f403 6380 and.w r3, r3, #1024 ; 0x400
800341e: 613b str r3, [r7, #16]
8003420: 693b ldr r3, [r7, #16]
LCD_DISP_GPIO_CLK_ENABLE();
8003422: 4b3a ldr r3, [pc, #232] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003424: 6b1b ldr r3, [r3, #48] ; 0x30
8003426: 4a39 ldr r2, [pc, #228] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003428: f443 7380 orr.w r3, r3, #256 ; 0x100
800342c: 6313 str r3, [r2, #48] ; 0x30
800342e: 4b37 ldr r3, [pc, #220] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003430: 6b1b ldr r3, [r3, #48] ; 0x30
8003432: f403 7380 and.w r3, r3, #256 ; 0x100
8003436: 60fb str r3, [r7, #12]
8003438: 68fb ldr r3, [r7, #12]
LCD_BL_CTRL_GPIO_CLK_ENABLE();
800343a: 4b34 ldr r3, [pc, #208] ; (800350c <BSP_LCD_MspInit+0x19c>)
800343c: 6b1b ldr r3, [r3, #48] ; 0x30
800343e: 4a33 ldr r2, [pc, #204] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003440: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003444: 6313 str r3, [r2, #48] ; 0x30
8003446: 4b31 ldr r3, [pc, #196] ; (800350c <BSP_LCD_MspInit+0x19c>)
8003448: 6b1b ldr r3, [r3, #48] ; 0x30
800344a: f403 6380 and.w r3, r3, #1024 ; 0x400
800344e: 60bb str r3, [r7, #8]
8003450: 68bb ldr r3, [r7, #8]
/*** LTDC Pins configuration ***/
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_4;
8003452: 2310 movs r3, #16
8003454: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003456: 2302 movs r3, #2
8003458: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_NOPULL;
800345a: 2300 movs r3, #0
800345c: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
800345e: 2302 movs r3, #2
8003460: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8003462: 230e movs r3, #14
8003464: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
8003466: f107 032c add.w r3, r7, #44 ; 0x2c
800346a: 4619 mov r1, r3
800346c: 4828 ldr r0, [pc, #160] ; (8003510 <BSP_LCD_MspInit+0x1a0>)
800346e: f003 ff07 bl 8007280 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_12;
8003472: f44f 5380 mov.w r3, #4096 ; 0x1000
8003476: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003478: 2302 movs r3, #2
800347a: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
800347c: 2309 movs r3, #9
800347e: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
8003480: f107 032c add.w r3, r7, #44 ; 0x2c
8003484: 4619 mov r1, r3
8003486: 4823 ldr r0, [pc, #140] ; (8003514 <BSP_LCD_MspInit+0x1a4>)
8003488: f003 fefa bl 8007280 <HAL_GPIO_Init>
/* GPIOI LTDC alternate configuration */
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
800348c: f44f 4366 mov.w r3, #58880 ; 0xe600
8003490: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8003492: 2302 movs r3, #2
8003494: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8003496: 230e movs r3, #14
8003498: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
800349a: f107 032c add.w r3, r7, #44 ; 0x2c
800349e: 4619 mov r1, r3
80034a0: 481d ldr r0, [pc, #116] ; (8003518 <BSP_LCD_MspInit+0x1a8>)
80034a2: f003 feed bl 8007280 <HAL_GPIO_Init>
/* GPIOJ configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
80034a6: f64e 73ff movw r3, #61439 ; 0xefff
80034aa: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80034ac: 2302 movs r3, #2
80034ae: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
80034b0: 230e movs r3, #14
80034b2: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
80034b4: f107 032c add.w r3, r7, #44 ; 0x2c
80034b8: 4619 mov r1, r3
80034ba: 4818 ldr r0, [pc, #96] ; (800351c <BSP_LCD_MspInit+0x1ac>)
80034bc: f003 fee0 bl 8007280 <HAL_GPIO_Init>
/* GPIOK configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
80034c0: 23f7 movs r3, #247 ; 0xf7
80034c2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80034c4: 2302 movs r3, #2
80034c6: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
80034c8: 230e movs r3, #14
80034ca: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
80034cc: f107 032c add.w r3, r7, #44 ; 0x2c
80034d0: 4619 mov r1, r3
80034d2: 4813 ldr r0, [pc, #76] ; (8003520 <BSP_LCD_MspInit+0x1b0>)
80034d4: f003 fed4 bl 8007280 <HAL_GPIO_Init>
/* LCD_DISP GPIO configuration */
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
80034d8: f44f 5380 mov.w r3, #4096 ; 0x1000
80034dc: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80034de: 2301 movs r3, #1
80034e0: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
80034e2: f107 032c add.w r3, r7, #44 ; 0x2c
80034e6: 4619 mov r1, r3
80034e8: 480b ldr r0, [pc, #44] ; (8003518 <BSP_LCD_MspInit+0x1a8>)
80034ea: f003 fec9 bl 8007280 <HAL_GPIO_Init>
/* LCD_BL_CTRL GPIO configuration */
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
80034ee: 2308 movs r3, #8
80034f0: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
80034f2: 2301 movs r3, #1
80034f4: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
80034f6: f107 032c add.w r3, r7, #44 ; 0x2c
80034fa: 4619 mov r1, r3
80034fc: 4808 ldr r0, [pc, #32] ; (8003520 <BSP_LCD_MspInit+0x1b0>)
80034fe: f003 febf bl 8007280 <HAL_GPIO_Init>
}
8003502: bf00 nop
8003504: 3740 adds r7, #64 ; 0x40
8003506: 46bd mov sp, r7
8003508: bd80 pop {r7, pc}
800350a: bf00 nop
800350c: 40023800 .word 0x40023800
8003510: 40021000 .word 0x40021000
8003514: 40021800 .word 0x40021800
8003518: 40022000 .word 0x40022000
800351c: 40022400 .word 0x40022400
8003520: 40022800 .word 0x40022800
08003524 <BSP_LCD_ClockConfig>:
* @note This API is called by BSP_LCD_Init()
* Being __weak it can be overwritten by the application
* @retval None
*/
__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)
{
8003524: b580 push {r7, lr}
8003526: b082 sub sp, #8
8003528: af00 add r7, sp, #0
800352a: 6078 str r0, [r7, #4]
800352c: 6039 str r1, [r7, #0]
/* RK043FN48H LCD clock configuration */
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
800352e: 4b0a ldr r3, [pc, #40] ; (8003558 <BSP_LCD_ClockConfig+0x34>)
8003530: 2208 movs r2, #8
8003532: 601a str r2, [r3, #0]
periph_clk_init_struct.PLLSAI.PLLSAIN = 192;
8003534: 4b08 ldr r3, [pc, #32] ; (8003558 <BSP_LCD_ClockConfig+0x34>)
8003536: 22c0 movs r2, #192 ; 0xc0
8003538: 615a str r2, [r3, #20]
periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER;
800353a: 4b07 ldr r3, [pc, #28] ; (8003558 <BSP_LCD_ClockConfig+0x34>)
800353c: 2205 movs r2, #5
800353e: 61da str r2, [r3, #28]
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
8003540: 4b05 ldr r3, [pc, #20] ; (8003558 <BSP_LCD_ClockConfig+0x34>)
8003542: f44f 3280 mov.w r2, #65536 ; 0x10000
8003546: 62da str r2, [r3, #44] ; 0x2c
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
8003548: 4803 ldr r0, [pc, #12] ; (8003558 <BSP_LCD_ClockConfig+0x34>)
800354a: f005 fe27 bl 800919c <HAL_RCCEx_PeriphCLKConfig>
}
800354e: bf00 nop
8003550: 3708 adds r7, #8
8003552: 46bd mov sp, r7
8003554: bd80 pop {r7, pc}
8003556: bf00 nop
8003558: 20000438 .word 0x20000438
0800355c <LL_FillBuffer>:
* @param OffLine: Offset
* @param ColorIndex: Color index
* @retval None
*/
static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
{
800355c: b580 push {r7, lr}
800355e: b086 sub sp, #24
8003560: af02 add r7, sp, #8
8003562: 60f8 str r0, [r7, #12]
8003564: 60b9 str r1, [r7, #8]
8003566: 607a str r2, [r7, #4]
8003568: 603b str r3, [r7, #0]
/* Register to memory mode with ARGB8888 as color Mode */
hDma2dHandler.Init.Mode = DMA2D_R2M;
800356a: 4b1e ldr r3, [pc, #120] ; (80035e4 <LL_FillBuffer+0x88>)
800356c: f44f 3240 mov.w r2, #196608 ; 0x30000
8003570: 605a str r2, [r3, #4]
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8003572: 4b1d ldr r3, [pc, #116] ; (80035e8 <LL_FillBuffer+0x8c>)
8003574: 681b ldr r3, [r3, #0]
8003576: 4a1d ldr r2, [pc, #116] ; (80035ec <LL_FillBuffer+0x90>)
8003578: 2134 movs r1, #52 ; 0x34
800357a: fb01 f303 mul.w r3, r1, r3
800357e: 4413 add r3, r2
8003580: 3348 adds r3, #72 ; 0x48
8003582: 681b ldr r3, [r3, #0]
8003584: 2b02 cmp r3, #2
8003586: d103 bne.n 8003590 <LL_FillBuffer+0x34>
{ /* RGB565 format */
hDma2dHandler.Init.ColorMode = DMA2D_RGB565;
8003588: 4b16 ldr r3, [pc, #88] ; (80035e4 <LL_FillBuffer+0x88>)
800358a: 2202 movs r2, #2
800358c: 609a str r2, [r3, #8]
800358e: e002 b.n 8003596 <LL_FillBuffer+0x3a>
}
else
{ /* ARGB8888 format */
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
8003590: 4b14 ldr r3, [pc, #80] ; (80035e4 <LL_FillBuffer+0x88>)
8003592: 2200 movs r2, #0
8003594: 609a str r2, [r3, #8]
}
hDma2dHandler.Init.OutputOffset = OffLine;
8003596: 4a13 ldr r2, [pc, #76] ; (80035e4 <LL_FillBuffer+0x88>)
8003598: 69bb ldr r3, [r7, #24]
800359a: 60d3 str r3, [r2, #12]
hDma2dHandler.Instance = DMA2D;
800359c: 4b11 ldr r3, [pc, #68] ; (80035e4 <LL_FillBuffer+0x88>)
800359e: 4a14 ldr r2, [pc, #80] ; (80035f0 <LL_FillBuffer+0x94>)
80035a0: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
80035a2: 4810 ldr r0, [pc, #64] ; (80035e4 <LL_FillBuffer+0x88>)
80035a4: f002 fa5a bl 8005a5c <HAL_DMA2D_Init>
80035a8: 4603 mov r3, r0
80035aa: 2b00 cmp r3, #0
80035ac: d115 bne.n 80035da <LL_FillBuffer+0x7e>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK)
80035ae: 68f9 ldr r1, [r7, #12]
80035b0: 480c ldr r0, [pc, #48] ; (80035e4 <LL_FillBuffer+0x88>)
80035b2: f002 fbb1 bl 8005d18 <HAL_DMA2D_ConfigLayer>
80035b6: 4603 mov r3, r0
80035b8: 2b00 cmp r3, #0
80035ba: d10e bne.n 80035da <LL_FillBuffer+0x7e>
{
if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
80035bc: 68ba ldr r2, [r7, #8]
80035be: 683b ldr r3, [r7, #0]
80035c0: 9300 str r3, [sp, #0]
80035c2: 687b ldr r3, [r7, #4]
80035c4: 69f9 ldr r1, [r7, #28]
80035c6: 4807 ldr r0, [pc, #28] ; (80035e4 <LL_FillBuffer+0x88>)
80035c8: f002 fa92 bl 8005af0 <HAL_DMA2D_Start>
80035cc: 4603 mov r3, r0
80035ce: 2b00 cmp r3, #0
80035d0: d103 bne.n 80035da <LL_FillBuffer+0x7e>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
80035d2: 210a movs r1, #10
80035d4: 4803 ldr r0, [pc, #12] ; (80035e4 <LL_FillBuffer+0x88>)
80035d6: f002 fab6 bl 8005b46 <HAL_DMA2D_PollForTransfer>
}
}
}
}
80035da: bf00 nop
80035dc: 3710 adds r7, #16
80035de: 46bd mov sp, r7
80035e0: bd80 pop {r7, pc}
80035e2: bf00 nop
80035e4: 200003dc .word 0x200003dc
80035e8: 2000041c .word 0x2000041c
80035ec: 20008c34 .word 0x20008c34
80035f0: 4002b000 .word 0x4002b000
080035f4 <LL_ConvertLineToARGB8888>:
* @param xSize: Buffer width
* @param ColorMode: Input color mode
* @retval None
*/
static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode)
{
80035f4: b580 push {r7, lr}
80035f6: b086 sub sp, #24
80035f8: af02 add r7, sp, #8
80035fa: 60f8 str r0, [r7, #12]
80035fc: 60b9 str r1, [r7, #8]
80035fe: 607a str r2, [r7, #4]
8003600: 603b str r3, [r7, #0]
/* Configure the DMA2D Mode, Color Mode and output offset */
hDma2dHandler.Init.Mode = DMA2D_M2M_PFC;
8003602: 4b1c ldr r3, [pc, #112] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003604: f44f 3280 mov.w r2, #65536 ; 0x10000
8003608: 605a str r2, [r3, #4]
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
800360a: 4b1a ldr r3, [pc, #104] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
800360c: 2200 movs r2, #0
800360e: 609a str r2, [r3, #8]
hDma2dHandler.Init.OutputOffset = 0;
8003610: 4b18 ldr r3, [pc, #96] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003612: 2200 movs r2, #0
8003614: 60da str r2, [r3, #12]
/* Foreground Configuration */
hDma2dHandler.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
8003616: 4b17 ldr r3, [pc, #92] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003618: 2200 movs r2, #0
800361a: 631a str r2, [r3, #48] ; 0x30
hDma2dHandler.LayerCfg[1].InputAlpha = 0xFF;
800361c: 4b15 ldr r3, [pc, #84] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
800361e: 22ff movs r2, #255 ; 0xff
8003620: 635a str r2, [r3, #52] ; 0x34
hDma2dHandler.LayerCfg[1].InputColorMode = ColorMode;
8003622: 4a14 ldr r2, [pc, #80] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003624: 683b ldr r3, [r7, #0]
8003626: 62d3 str r3, [r2, #44] ; 0x2c
hDma2dHandler.LayerCfg[1].InputOffset = 0;
8003628: 4b12 ldr r3, [pc, #72] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
800362a: 2200 movs r2, #0
800362c: 629a str r2, [r3, #40] ; 0x28
hDma2dHandler.Instance = DMA2D;
800362e: 4b11 ldr r3, [pc, #68] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003630: 4a11 ldr r2, [pc, #68] ; (8003678 <LL_ConvertLineToARGB8888+0x84>)
8003632: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
8003634: 480f ldr r0, [pc, #60] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003636: f002 fa11 bl 8005a5c <HAL_DMA2D_Init>
800363a: 4603 mov r3, r0
800363c: 2b00 cmp r3, #0
800363e: d115 bne.n 800366c <LL_ConvertLineToARGB8888+0x78>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, 1) == HAL_OK)
8003640: 2101 movs r1, #1
8003642: 480c ldr r0, [pc, #48] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003644: f002 fb68 bl 8005d18 <HAL_DMA2D_ConfigLayer>
8003648: 4603 mov r3, r0
800364a: 2b00 cmp r3, #0
800364c: d10e bne.n 800366c <LL_ConvertLineToARGB8888+0x78>
{
if (HAL_DMA2D_Start(&hDma2dHandler, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK)
800364e: 68f9 ldr r1, [r7, #12]
8003650: 68ba ldr r2, [r7, #8]
8003652: 2301 movs r3, #1
8003654: 9300 str r3, [sp, #0]
8003656: 687b ldr r3, [r7, #4]
8003658: 4806 ldr r0, [pc, #24] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
800365a: f002 fa49 bl 8005af0 <HAL_DMA2D_Start>
800365e: 4603 mov r3, r0
8003660: 2b00 cmp r3, #0
8003662: d103 bne.n 800366c <LL_ConvertLineToARGB8888+0x78>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
8003664: 210a movs r1, #10
8003666: 4803 ldr r0, [pc, #12] ; (8003674 <LL_ConvertLineToARGB8888+0x80>)
8003668: f002 fa6d bl 8005b46 <HAL_DMA2D_PollForTransfer>
}
}
}
}
800366c: bf00 nop
800366e: 3710 adds r7, #16
8003670: 46bd mov sp, r7
8003672: bd80 pop {r7, pc}
8003674: 200003dc .word 0x200003dc
8003678: 4002b000 .word 0x4002b000
0800367c <BSP_SDRAM_Init>:
/**
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
{
800367c: b580 push {r7, lr}
800367e: af00 add r7, sp, #0
static uint8_t sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
8003680: 4b29 ldr r3, [pc, #164] ; (8003728 <BSP_SDRAM_Init+0xac>)
8003682: 4a2a ldr r2, [pc, #168] ; (800372c <BSP_SDRAM_Init+0xb0>)
8003684: 601a str r2, [r3, #0]
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
Timing.LoadToActiveDelay = 2;
8003686: 4b2a ldr r3, [pc, #168] ; (8003730 <BSP_SDRAM_Init+0xb4>)
8003688: 2202 movs r2, #2
800368a: 601a str r2, [r3, #0]
Timing.ExitSelfRefreshDelay = 7;
800368c: 4b28 ldr r3, [pc, #160] ; (8003730 <BSP_SDRAM_Init+0xb4>)
800368e: 2207 movs r2, #7
8003690: 605a str r2, [r3, #4]
Timing.SelfRefreshTime = 4;
8003692: 4b27 ldr r3, [pc, #156] ; (8003730 <BSP_SDRAM_Init+0xb4>)
8003694: 2204 movs r2, #4
8003696: 609a str r2, [r3, #8]
Timing.RowCycleDelay = 7;
8003698: 4b25 ldr r3, [pc, #148] ; (8003730 <BSP_SDRAM_Init+0xb4>)
800369a: 2207 movs r2, #7
800369c: 60da str r2, [r3, #12]
Timing.WriteRecoveryTime = 2;
800369e: 4b24 ldr r3, [pc, #144] ; (8003730 <BSP_SDRAM_Init+0xb4>)
80036a0: 2202 movs r2, #2
80036a2: 611a str r2, [r3, #16]
Timing.RPDelay = 2;
80036a4: 4b22 ldr r3, [pc, #136] ; (8003730 <BSP_SDRAM_Init+0xb4>)
80036a6: 2202 movs r2, #2
80036a8: 615a str r2, [r3, #20]
Timing.RCDDelay = 2;
80036aa: 4b21 ldr r3, [pc, #132] ; (8003730 <BSP_SDRAM_Init+0xb4>)
80036ac: 2202 movs r2, #2
80036ae: 619a str r2, [r3, #24]
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
80036b0: 4b1d ldr r3, [pc, #116] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036b2: 2200 movs r2, #0
80036b4: 605a str r2, [r3, #4]
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
80036b6: 4b1c ldr r3, [pc, #112] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036b8: 2200 movs r2, #0
80036ba: 609a str r2, [r3, #8]
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
80036bc: 4b1a ldr r3, [pc, #104] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036be: 2204 movs r2, #4
80036c0: 60da str r2, [r3, #12]
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
80036c2: 4b19 ldr r3, [pc, #100] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036c4: 2210 movs r2, #16
80036c6: 611a str r2, [r3, #16]
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
80036c8: 4b17 ldr r3, [pc, #92] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036ca: 2240 movs r2, #64 ; 0x40
80036cc: 615a str r2, [r3, #20]
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
80036ce: 4b16 ldr r3, [pc, #88] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036d0: f44f 7280 mov.w r2, #256 ; 0x100
80036d4: 619a str r2, [r3, #24]
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
80036d6: 4b14 ldr r3, [pc, #80] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036d8: 2200 movs r2, #0
80036da: 61da str r2, [r3, #28]
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
80036dc: 4b12 ldr r3, [pc, #72] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036de: f44f 6200 mov.w r2, #2048 ; 0x800
80036e2: 621a str r2, [r3, #32]
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
80036e4: 4b10 ldr r3, [pc, #64] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036e6: f44f 5280 mov.w r2, #4096 ; 0x1000
80036ea: 625a str r2, [r3, #36] ; 0x24
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
80036ec: 4b0e ldr r3, [pc, #56] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036ee: 2200 movs r2, #0
80036f0: 629a str r2, [r3, #40] ; 0x28
/* SDRAM controller initialization */
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
80036f2: 2100 movs r1, #0
80036f4: 480c ldr r0, [pc, #48] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036f6: f000 f87f bl 80037f8 <BSP_SDRAM_MspInit>
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
80036fa: 490d ldr r1, [pc, #52] ; (8003730 <BSP_SDRAM_Init+0xb4>)
80036fc: 480a ldr r0, [pc, #40] ; (8003728 <BSP_SDRAM_Init+0xac>)
80036fe: f006 f965 bl 80099cc <HAL_SDRAM_Init>
8003702: 4603 mov r3, r0
8003704: 2b00 cmp r3, #0
8003706: d003 beq.n 8003710 <BSP_SDRAM_Init+0x94>
{
sdramstatus = SDRAM_ERROR;
8003708: 4b0a ldr r3, [pc, #40] ; (8003734 <BSP_SDRAM_Init+0xb8>)
800370a: 2201 movs r2, #1
800370c: 701a strb r2, [r3, #0]
800370e: e002 b.n 8003716 <BSP_SDRAM_Init+0x9a>
}
else
{
sdramstatus = SDRAM_OK;
8003710: 4b08 ldr r3, [pc, #32] ; (8003734 <BSP_SDRAM_Init+0xb8>)
8003712: 2200 movs r2, #0
8003714: 701a strb r2, [r3, #0]
}
/* SDRAM initialization sequence */
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
8003716: f240 6003 movw r0, #1539 ; 0x603
800371a: f000 f80d bl 8003738 <BSP_SDRAM_Initialization_sequence>
return sdramstatus;
800371e: 4b05 ldr r3, [pc, #20] ; (8003734 <BSP_SDRAM_Init+0xb8>)
8003720: 781b ldrb r3, [r3, #0]
}
8003722: 4618 mov r0, r3
8003724: bd80 pop {r7, pc}
8003726: bf00 nop
8003728: 20008cdc .word 0x20008cdc
800372c: a0000140 .word 0xa0000140
8003730: 200004bc .word 0x200004bc
8003734: 20000060 .word 0x20000060
08003738 <BSP_SDRAM_Initialization_sequence>:
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
* @retval None
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
{
8003738: b580 push {r7, lr}
800373a: b084 sub sp, #16
800373c: af00 add r7, sp, #0
800373e: 6078 str r0, [r7, #4]
__IO uint32_t tmpmrd = 0;
8003740: 2300 movs r3, #0
8003742: 60fb str r3, [r7, #12]
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
8003744: 4b2a ldr r3, [pc, #168] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003746: 2201 movs r2, #1
8003748: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
800374a: 4b29 ldr r3, [pc, #164] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
800374c: 2210 movs r2, #16
800374e: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003750: 4b27 ldr r3, [pc, #156] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003752: 2201 movs r2, #1
8003754: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003756: 4b26 ldr r3, [pc, #152] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003758: 2200 movs r2, #0
800375a: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
800375c: f64f 72ff movw r2, #65535 ; 0xffff
8003760: 4923 ldr r1, [pc, #140] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003762: 4824 ldr r0, [pc, #144] ; (80037f4 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003764: f006 f966 bl 8009a34 <HAL_SDRAM_SendCommand>
/* Step 2: Insert 100 us minimum delay */
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
HAL_Delay(1);
8003768: 2001 movs r0, #1
800376a: f001 f925 bl 80049b8 <HAL_Delay>
/* Step 3: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
800376e: 4b20 ldr r3, [pc, #128] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003770: 2202 movs r2, #2
8003772: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003774: 4b1e ldr r3, [pc, #120] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003776: 2210 movs r2, #16
8003778: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
800377a: 4b1d ldr r3, [pc, #116] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
800377c: 2201 movs r2, #1
800377e: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003780: 4b1b ldr r3, [pc, #108] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003782: 2200 movs r2, #0
8003784: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003786: f64f 72ff movw r2, #65535 ; 0xffff
800378a: 4919 ldr r1, [pc, #100] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
800378c: 4819 ldr r0, [pc, #100] ; (80037f4 <BSP_SDRAM_Initialization_sequence+0xbc>)
800378e: f006 f951 bl 8009a34 <HAL_SDRAM_SendCommand>
/* Step 4: Configure an Auto Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
8003792: 4b17 ldr r3, [pc, #92] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
8003794: 2203 movs r2, #3
8003796: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003798: 4b15 ldr r3, [pc, #84] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
800379a: 2210 movs r2, #16
800379c: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 8;
800379e: 4b14 ldr r3, [pc, #80] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037a0: 2208 movs r2, #8
80037a2: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
80037a4: 4b12 ldr r3, [pc, #72] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037a6: 2200 movs r2, #0
80037a8: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80037aa: f64f 72ff movw r2, #65535 ; 0xffff
80037ae: 4910 ldr r1, [pc, #64] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037b0: 4810 ldr r0, [pc, #64] ; (80037f4 <BSP_SDRAM_Initialization_sequence+0xbc>)
80037b2: f006 f93f bl 8009a34 <HAL_SDRAM_SendCommand>
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
80037b6: f44f 7308 mov.w r3, #544 ; 0x220
80037ba: 60fb str r3, [r7, #12]
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_2 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
80037bc: 4b0c ldr r3, [pc, #48] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037be: 2204 movs r2, #4
80037c0: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80037c2: 4b0b ldr r3, [pc, #44] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037c4: 2210 movs r2, #16
80037c6: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
80037c8: 4b09 ldr r3, [pc, #36] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037ca: 2201 movs r2, #1
80037cc: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = tmpmrd;
80037ce: 68fb ldr r3, [r7, #12]
80037d0: 4a07 ldr r2, [pc, #28] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037d2: 60d3 str r3, [r2, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
80037d4: f64f 72ff movw r2, #65535 ; 0xffff
80037d8: 4905 ldr r1, [pc, #20] ; (80037f0 <BSP_SDRAM_Initialization_sequence+0xb8>)
80037da: 4806 ldr r0, [pc, #24] ; (80037f4 <BSP_SDRAM_Initialization_sequence+0xbc>)
80037dc: f006 f92a bl 8009a34 <HAL_SDRAM_SendCommand>
/* Step 6: Set the refresh rate counter */
/* Set the device refresh rate */
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
80037e0: 6879 ldr r1, [r7, #4]
80037e2: 4804 ldr r0, [pc, #16] ; (80037f4 <BSP_SDRAM_Initialization_sequence+0xbc>)
80037e4: f006 f951 bl 8009a8a <HAL_SDRAM_ProgramRefreshRate>
}
80037e8: bf00 nop
80037ea: 3710 adds r7, #16
80037ec: 46bd mov sp, r7
80037ee: bd80 pop {r7, pc}
80037f0: 200004d8 .word 0x200004d8
80037f4: 20008cdc .word 0x20008cdc
080037f8 <BSP_SDRAM_MspInit>:
* @param hsdram: SDRAM handle
* @param Params
* @retval None
*/
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
{
80037f8: b580 push {r7, lr}
80037fa: b090 sub sp, #64 ; 0x40
80037fc: af00 add r7, sp, #0
80037fe: 6078 str r0, [r7, #4]
8003800: 6039 str r1, [r7, #0]
static DMA_HandleTypeDef dma_handle;
GPIO_InitTypeDef gpio_init_structure;
/* Enable FMC clock */
__HAL_RCC_FMC_CLK_ENABLE();
8003802: 4b70 ldr r3, [pc, #448] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003804: 6b9b ldr r3, [r3, #56] ; 0x38
8003806: 4a6f ldr r2, [pc, #444] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003808: f043 0301 orr.w r3, r3, #1
800380c: 6393 str r3, [r2, #56] ; 0x38
800380e: 4b6d ldr r3, [pc, #436] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003810: 6b9b ldr r3, [r3, #56] ; 0x38
8003812: f003 0301 and.w r3, r3, #1
8003816: 62bb str r3, [r7, #40] ; 0x28
8003818: 6abb ldr r3, [r7, #40] ; 0x28
/* Enable chosen DMAx clock */
__DMAx_CLK_ENABLE();
800381a: 4b6a ldr r3, [pc, #424] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
800381c: 6b1b ldr r3, [r3, #48] ; 0x30
800381e: 4a69 ldr r2, [pc, #420] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003820: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8003824: 6313 str r3, [r2, #48] ; 0x30
8003826: 4b67 ldr r3, [pc, #412] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003828: 6b1b ldr r3, [r3, #48] ; 0x30
800382a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800382e: 627b str r3, [r7, #36] ; 0x24
8003830: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOC_CLK_ENABLE();
8003832: 4b64 ldr r3, [pc, #400] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003834: 6b1b ldr r3, [r3, #48] ; 0x30
8003836: 4a63 ldr r2, [pc, #396] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003838: f043 0304 orr.w r3, r3, #4
800383c: 6313 str r3, [r2, #48] ; 0x30
800383e: 4b61 ldr r3, [pc, #388] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003840: 6b1b ldr r3, [r3, #48] ; 0x30
8003842: f003 0304 and.w r3, r3, #4
8003846: 623b str r3, [r7, #32]
8003848: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOD_CLK_ENABLE();
800384a: 4b5e ldr r3, [pc, #376] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
800384c: 6b1b ldr r3, [r3, #48] ; 0x30
800384e: 4a5d ldr r2, [pc, #372] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003850: f043 0308 orr.w r3, r3, #8
8003854: 6313 str r3, [r2, #48] ; 0x30
8003856: 4b5b ldr r3, [pc, #364] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003858: 6b1b ldr r3, [r3, #48] ; 0x30
800385a: f003 0308 and.w r3, r3, #8
800385e: 61fb str r3, [r7, #28]
8003860: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOE_CLK_ENABLE();
8003862: 4b58 ldr r3, [pc, #352] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003864: 6b1b ldr r3, [r3, #48] ; 0x30
8003866: 4a57 ldr r2, [pc, #348] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003868: f043 0310 orr.w r3, r3, #16
800386c: 6313 str r3, [r2, #48] ; 0x30
800386e: 4b55 ldr r3, [pc, #340] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003870: 6b1b ldr r3, [r3, #48] ; 0x30
8003872: f003 0310 and.w r3, r3, #16
8003876: 61bb str r3, [r7, #24]
8003878: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOF_CLK_ENABLE();
800387a: 4b52 ldr r3, [pc, #328] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
800387c: 6b1b ldr r3, [r3, #48] ; 0x30
800387e: 4a51 ldr r2, [pc, #324] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003880: f043 0320 orr.w r3, r3, #32
8003884: 6313 str r3, [r2, #48] ; 0x30
8003886: 4b4f ldr r3, [pc, #316] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003888: 6b1b ldr r3, [r3, #48] ; 0x30
800388a: f003 0320 and.w r3, r3, #32
800388e: 617b str r3, [r7, #20]
8003890: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8003892: 4b4c ldr r3, [pc, #304] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003894: 6b1b ldr r3, [r3, #48] ; 0x30
8003896: 4a4b ldr r2, [pc, #300] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
8003898: f043 0340 orr.w r3, r3, #64 ; 0x40
800389c: 6313 str r3, [r2, #48] ; 0x30
800389e: 4b49 ldr r3, [pc, #292] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
80038a0: 6b1b ldr r3, [r3, #48] ; 0x30
80038a2: f003 0340 and.w r3, r3, #64 ; 0x40
80038a6: 613b str r3, [r7, #16]
80038a8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80038aa: 4b46 ldr r3, [pc, #280] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
80038ac: 6b1b ldr r3, [r3, #48] ; 0x30
80038ae: 4a45 ldr r2, [pc, #276] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
80038b0: f043 0380 orr.w r3, r3, #128 ; 0x80
80038b4: 6313 str r3, [r2, #48] ; 0x30
80038b6: 4b43 ldr r3, [pc, #268] ; (80039c4 <BSP_SDRAM_MspInit+0x1cc>)
80038b8: 6b1b ldr r3, [r3, #48] ; 0x30
80038ba: f003 0380 and.w r3, r3, #128 ; 0x80
80038be: 60fb str r3, [r7, #12]
80038c0: 68fb ldr r3, [r7, #12]
/* Common GPIO configuration */
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
80038c2: 2302 movs r3, #2
80038c4: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_PULLUP;
80038c6: 2301 movs r3, #1
80038c8: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
80038ca: 2302 movs r3, #2
80038cc: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF12_FMC;
80038ce: 230c movs r3, #12
80038d0: 63fb str r3, [r7, #60] ; 0x3c
/* GPIOC configuration */
gpio_init_structure.Pin = GPIO_PIN_3;
80038d2: 2308 movs r3, #8
80038d4: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
80038d6: f107 032c add.w r3, r7, #44 ; 0x2c
80038da: 4619 mov r1, r3
80038dc: 483a ldr r0, [pc, #232] ; (80039c8 <BSP_SDRAM_MspInit+0x1d0>)
80038de: f003 fccf bl 8007280 <HAL_GPIO_Init>
/* GPIOD configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
80038e2: f24c 7303 movw r3, #50947 ; 0xc703
80038e6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
80038e8: f107 032c add.w r3, r7, #44 ; 0x2c
80038ec: 4619 mov r1, r3
80038ee: 4837 ldr r0, [pc, #220] ; (80039cc <BSP_SDRAM_MspInit+0x1d4>)
80038f0: f003 fcc6 bl 8007280 <HAL_GPIO_Init>
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
80038f4: f64f 7383 movw r3, #65411 ; 0xff83
80038f8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
80038fa: f107 032c add.w r3, r7, #44 ; 0x2c
80038fe: 4619 mov r1, r3
8003900: 4833 ldr r0, [pc, #204] ; (80039d0 <BSP_SDRAM_MspInit+0x1d8>)
8003902: f003 fcbd bl 8007280 <HAL_GPIO_Init>
/* GPIOF configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
8003906: f64f 033f movw r3, #63551 ; 0xf83f
800390a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
800390c: f107 032c add.w r3, r7, #44 ; 0x2c
8003910: 4619 mov r1, r3
8003912: 4830 ldr r0, [pc, #192] ; (80039d4 <BSP_SDRAM_MspInit+0x1dc>)
8003914: f003 fcb4 bl 8007280 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
8003918: f248 1333 movw r3, #33075 ; 0x8133
800391c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
800391e: f107 032c add.w r3, r7, #44 ; 0x2c
8003922: 4619 mov r1, r3
8003924: 482c ldr r0, [pc, #176] ; (80039d8 <BSP_SDRAM_MspInit+0x1e0>)
8003926: f003 fcab bl 8007280 <HAL_GPIO_Init>
/* GPIOH configuration */
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
800392a: 2328 movs r3, #40 ; 0x28
800392c: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
800392e: f107 032c add.w r3, r7, #44 ; 0x2c
8003932: 4619 mov r1, r3
8003934: 4829 ldr r0, [pc, #164] ; (80039dc <BSP_SDRAM_MspInit+0x1e4>)
8003936: f003 fca3 bl 8007280 <HAL_GPIO_Init>
/* Configure common DMA parameters */
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
800393a: 4b29 ldr r3, [pc, #164] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
800393c: 2200 movs r2, #0
800393e: 605a str r2, [r3, #4]
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
8003940: 4b27 ldr r3, [pc, #156] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003942: 2280 movs r2, #128 ; 0x80
8003944: 609a str r2, [r3, #8]
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
8003946: 4b26 ldr r3, [pc, #152] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003948: f44f 7200 mov.w r2, #512 ; 0x200
800394c: 60da str r2, [r3, #12]
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
800394e: 4b24 ldr r3, [pc, #144] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003950: f44f 6280 mov.w r2, #1024 ; 0x400
8003954: 611a str r2, [r3, #16]
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
8003956: 4b22 ldr r3, [pc, #136] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003958: f44f 5280 mov.w r2, #4096 ; 0x1000
800395c: 615a str r2, [r3, #20]
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
800395e: 4b20 ldr r3, [pc, #128] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003960: f44f 4280 mov.w r2, #16384 ; 0x4000
8003964: 619a str r2, [r3, #24]
dma_handle.Init.Mode = DMA_NORMAL;
8003966: 4b1e ldr r3, [pc, #120] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003968: 2200 movs r2, #0
800396a: 61da str r2, [r3, #28]
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
800396c: 4b1c ldr r3, [pc, #112] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
800396e: f44f 3200 mov.w r2, #131072 ; 0x20000
8003972: 621a str r2, [r3, #32]
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
8003974: 4b1a ldr r3, [pc, #104] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003976: 2200 movs r2, #0
8003978: 625a str r2, [r3, #36] ; 0x24
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
800397a: 4b19 ldr r3, [pc, #100] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
800397c: 2203 movs r2, #3
800397e: 629a str r2, [r3, #40] ; 0x28
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
8003980: 4b17 ldr r3, [pc, #92] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003982: 2200 movs r2, #0
8003984: 62da str r2, [r3, #44] ; 0x2c
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
8003986: 4b16 ldr r3, [pc, #88] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003988: 2200 movs r2, #0
800398a: 631a str r2, [r3, #48] ; 0x30
dma_handle.Instance = SDRAM_DMAx_STREAM;
800398c: 4b14 ldr r3, [pc, #80] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
800398e: 4a15 ldr r2, [pc, #84] ; (80039e4 <BSP_SDRAM_MspInit+0x1ec>)
8003990: 601a str r2, [r3, #0]
/* Associate the DMA handle */
__HAL_LINKDMA(hsdram, hdma, dma_handle);
8003992: 687b ldr r3, [r7, #4]
8003994: 4a12 ldr r2, [pc, #72] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
8003996: 631a str r2, [r3, #48] ; 0x30
8003998: 4a11 ldr r2, [pc, #68] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
800399a: 687b ldr r3, [r7, #4]
800399c: 6393 str r3, [r2, #56] ; 0x38
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dma_handle);
800399e: 4810 ldr r0, [pc, #64] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
80039a0: f001 ff4e bl 8005840 <HAL_DMA_DeInit>
/* Configure the DMA stream */
HAL_DMA_Init(&dma_handle);
80039a4: 480e ldr r0, [pc, #56] ; (80039e0 <BSP_SDRAM_MspInit+0x1e8>)
80039a6: f001 fe9d bl 80056e4 <HAL_DMA_Init>
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
80039aa: 2200 movs r2, #0
80039ac: 210f movs r1, #15
80039ae: 2038 movs r0, #56 ; 0x38
80039b0: f001 fcb6 bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
80039b4: 2038 movs r0, #56 ; 0x38
80039b6: f001 fccf bl 8005358 <HAL_NVIC_EnableIRQ>
}
80039ba: bf00 nop
80039bc: 3740 adds r7, #64 ; 0x40
80039be: 46bd mov sp, r7
80039c0: bd80 pop {r7, pc}
80039c2: bf00 nop
80039c4: 40023800 .word 0x40023800
80039c8: 40020800 .word 0x40020800
80039cc: 40020c00 .word 0x40020c00
80039d0: 40021000 .word 0x40021000
80039d4: 40021400 .word 0x40021400
80039d8: 40021800 .word 0x40021800
80039dc: 40021c00 .word 0x40021c00
80039e0: 200004e8 .word 0x200004e8
80039e4: 40026410 .word 0x40026410
080039e8 <BSP_TS_Init>:
* @param ts_SizeX: Maximum X size of the TS area on LCD
* @param ts_SizeY: Maximum Y size of the TS area on LCD
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
{
80039e8: b580 push {r7, lr}
80039ea: b084 sub sp, #16
80039ec: af00 add r7, sp, #0
80039ee: 4603 mov r3, r0
80039f0: 460a mov r2, r1
80039f2: 80fb strh r3, [r7, #6]
80039f4: 4613 mov r3, r2
80039f6: 80bb strh r3, [r7, #4]
uint8_t status = TS_OK;
80039f8: 2300 movs r3, #0
80039fa: 73fb strb r3, [r7, #15]
tsXBoundary = ts_SizeX;
80039fc: 4a14 ldr r2, [pc, #80] ; (8003a50 <BSP_TS_Init+0x68>)
80039fe: 88fb ldrh r3, [r7, #6]
8003a00: 8013 strh r3, [r2, #0]
tsYBoundary = ts_SizeY;
8003a02: 4a14 ldr r2, [pc, #80] ; (8003a54 <BSP_TS_Init+0x6c>)
8003a04: 88bb ldrh r3, [r7, #4]
8003a06: 8013 strh r3, [r2, #0]
/* Read ID and verify if the touch screen driver is ready */
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
8003a08: 4b13 ldr r3, [pc, #76] ; (8003a58 <BSP_TS_Init+0x70>)
8003a0a: 681b ldr r3, [r3, #0]
8003a0c: 2070 movs r0, #112 ; 0x70
8003a0e: 4798 blx r3
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
8003a10: 4b11 ldr r3, [pc, #68] ; (8003a58 <BSP_TS_Init+0x70>)
8003a12: 685b ldr r3, [r3, #4]
8003a14: 2070 movs r0, #112 ; 0x70
8003a16: 4798 blx r3
8003a18: 4603 mov r3, r0
8003a1a: 2b51 cmp r3, #81 ; 0x51
8003a1c: d111 bne.n 8003a42 <BSP_TS_Init+0x5a>
{
/* Initialize the TS driver structure */
tsDriver = &ft5336_ts_drv;
8003a1e: 4b0f ldr r3, [pc, #60] ; (8003a5c <BSP_TS_Init+0x74>)
8003a20: 4a0d ldr r2, [pc, #52] ; (8003a58 <BSP_TS_Init+0x70>)
8003a22: 601a str r2, [r3, #0]
I2cAddress = TS_I2C_ADDRESS;
8003a24: 4b0e ldr r3, [pc, #56] ; (8003a60 <BSP_TS_Init+0x78>)
8003a26: 2270 movs r2, #112 ; 0x70
8003a28: 701a strb r2, [r3, #0]
tsOrientation = TS_SWAP_XY;
8003a2a: 4b0e ldr r3, [pc, #56] ; (8003a64 <BSP_TS_Init+0x7c>)
8003a2c: 2208 movs r2, #8
8003a2e: 701a strb r2, [r3, #0]
/* Initialize the TS driver */
tsDriver->Start(I2cAddress);
8003a30: 4b0a ldr r3, [pc, #40] ; (8003a5c <BSP_TS_Init+0x74>)
8003a32: 681b ldr r3, [r3, #0]
8003a34: 68db ldr r3, [r3, #12]
8003a36: 4a0a ldr r2, [pc, #40] ; (8003a60 <BSP_TS_Init+0x78>)
8003a38: 7812 ldrb r2, [r2, #0]
8003a3a: b292 uxth r2, r2
8003a3c: 4610 mov r0, r2
8003a3e: 4798 blx r3
8003a40: e001 b.n 8003a46 <BSP_TS_Init+0x5e>
}
else
{
status = TS_DEVICE_NOT_FOUND;
8003a42: 2303 movs r3, #3
8003a44: 73fb strb r3, [r7, #15]
}
return status;
8003a46: 7bfb ldrb r3, [r7, #15]
}
8003a48: 4618 mov r0, r3
8003a4a: 3710 adds r7, #16
8003a4c: 46bd mov sp, r7
8003a4e: bd80 pop {r7, pc}
8003a50: 2000054c .word 0x2000054c
8003a54: 2000054e .word 0x2000054e
8003a58: 20000000 .word 0x20000000
8003a5c: 20000548 .word 0x20000548
8003a60: 20000551 .word 0x20000551
8003a64: 20000550 .word 0x20000550
08003a68 <BSP_TS_GetState>:
* @brief Returns status and positions of the touch screen.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
{
8003a68: b590 push {r4, r7, lr}
8003a6a: b097 sub sp, #92 ; 0x5c
8003a6c: af02 add r7, sp, #8
8003a6e: 6078 str r0, [r7, #4]
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
uint8_t ts_status = TS_OK;
8003a70: 2300 movs r3, #0
8003a72: f887 304f strb.w r3, [r7, #79] ; 0x4f
uint16_t brute_y[TS_MAX_NB_TOUCH];
uint16_t x_diff;
uint16_t y_diff;
uint32_t index;
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
uint32_t weight = 0;
8003a76: 2300 movs r3, #0
8003a78: 613b str r3, [r7, #16]
uint32_t area = 0;
8003a7a: 2300 movs r3, #0
8003a7c: 60fb str r3, [r7, #12]
uint32_t event = 0;
8003a7e: 2300 movs r3, #0
8003a80: 60bb str r3, [r7, #8]
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
/* Check and update the number of touches active detected */
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
8003a82: 4b97 ldr r3, [pc, #604] ; (8003ce0 <BSP_TS_GetState+0x278>)
8003a84: 681b ldr r3, [r3, #0]
8003a86: 691b ldr r3, [r3, #16]
8003a88: 4a96 ldr r2, [pc, #600] ; (8003ce4 <BSP_TS_GetState+0x27c>)
8003a8a: 7812 ldrb r2, [r2, #0]
8003a8c: b292 uxth r2, r2
8003a8e: 4610 mov r0, r2
8003a90: 4798 blx r3
8003a92: 4603 mov r3, r0
8003a94: 461a mov r2, r3
8003a96: 687b ldr r3, [r7, #4]
8003a98: 701a strb r2, [r3, #0]
if(TS_State->touchDetected)
8003a9a: 687b ldr r3, [r7, #4]
8003a9c: 781b ldrb r3, [r3, #0]
8003a9e: 2b00 cmp r3, #0
8003aa0: f000 81a8 beq.w 8003df4 <BSP_TS_GetState+0x38c>
{
for(index=0; index < TS_State->touchDetected; index++)
8003aa4: 2300 movs r3, #0
8003aa6: 64bb str r3, [r7, #72] ; 0x48
8003aa8: e197 b.n 8003dda <BSP_TS_GetState+0x372>
{
/* Get each touch coordinates */
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
8003aaa: 4b8d ldr r3, [pc, #564] ; (8003ce0 <BSP_TS_GetState+0x278>)
8003aac: 681b ldr r3, [r3, #0]
8003aae: 695b ldr r3, [r3, #20]
8003ab0: 4a8c ldr r2, [pc, #560] ; (8003ce4 <BSP_TS_GetState+0x27c>)
8003ab2: 7812 ldrb r2, [r2, #0]
8003ab4: b290 uxth r0, r2
8003ab6: f107 0120 add.w r1, r7, #32
8003aba: 6cba ldr r2, [r7, #72] ; 0x48
8003abc: 0052 lsls r2, r2, #1
8003abe: 188c adds r4, r1, r2
8003ac0: f107 0114 add.w r1, r7, #20
8003ac4: 6cba ldr r2, [r7, #72] ; 0x48
8003ac6: 0052 lsls r2, r2, #1
8003ac8: 440a add r2, r1
8003aca: 4621 mov r1, r4
8003acc: 4798 blx r3
if(tsOrientation == TS_SWAP_NONE)
8003ace: 4b86 ldr r3, [pc, #536] ; (8003ce8 <BSP_TS_GetState+0x280>)
8003ad0: 781b ldrb r3, [r3, #0]
8003ad2: 2b01 cmp r3, #1
8003ad4: d11b bne.n 8003b0e <BSP_TS_GetState+0xa6>
{
x[index] = brute_x[index];
8003ad6: 6cbb ldr r3, [r7, #72] ; 0x48
8003ad8: 005b lsls r3, r3, #1
8003ada: f107 0250 add.w r2, r7, #80 ; 0x50
8003ade: 4413 add r3, r2
8003ae0: f833 2c30 ldrh.w r2, [r3, #-48]
8003ae4: 6cbb ldr r3, [r7, #72] ; 0x48
8003ae6: 005b lsls r3, r3, #1
8003ae8: f107 0150 add.w r1, r7, #80 ; 0x50
8003aec: 440b add r3, r1
8003aee: f823 2c18 strh.w r2, [r3, #-24]
y[index] = brute_y[index];
8003af2: 6cbb ldr r3, [r7, #72] ; 0x48
8003af4: 005b lsls r3, r3, #1
8003af6: f107 0250 add.w r2, r7, #80 ; 0x50
8003afa: 4413 add r3, r2
8003afc: f833 2c3c ldrh.w r2, [r3, #-60]
8003b00: 6cbb ldr r3, [r7, #72] ; 0x48
8003b02: 005b lsls r3, r3, #1
8003b04: f107 0150 add.w r1, r7, #80 ; 0x50
8003b08: 440b add r3, r1
8003b0a: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_X)
8003b0e: 4b76 ldr r3, [pc, #472] ; (8003ce8 <BSP_TS_GetState+0x280>)
8003b10: 781b ldrb r3, [r3, #0]
8003b12: f003 0302 and.w r3, r3, #2
8003b16: 2b00 cmp r3, #0
8003b18: d010 beq.n 8003b3c <BSP_TS_GetState+0xd4>
{
x[index] = 4096 - brute_x[index];
8003b1a: 6cbb ldr r3, [r7, #72] ; 0x48
8003b1c: 005b lsls r3, r3, #1
8003b1e: f107 0250 add.w r2, r7, #80 ; 0x50
8003b22: 4413 add r3, r2
8003b24: f833 3c30 ldrh.w r3, [r3, #-48]
8003b28: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
8003b2c: b29a uxth r2, r3
8003b2e: 6cbb ldr r3, [r7, #72] ; 0x48
8003b30: 005b lsls r3, r3, #1
8003b32: f107 0150 add.w r1, r7, #80 ; 0x50
8003b36: 440b add r3, r1
8003b38: f823 2c18 strh.w r2, [r3, #-24]
}
if(tsOrientation & TS_SWAP_Y)
8003b3c: 4b6a ldr r3, [pc, #424] ; (8003ce8 <BSP_TS_GetState+0x280>)
8003b3e: 781b ldrb r3, [r3, #0]
8003b40: f003 0304 and.w r3, r3, #4
8003b44: 2b00 cmp r3, #0
8003b46: d010 beq.n 8003b6a <BSP_TS_GetState+0x102>
{
y[index] = 4096 - brute_y[index];
8003b48: 6cbb ldr r3, [r7, #72] ; 0x48
8003b4a: 005b lsls r3, r3, #1
8003b4c: f107 0250 add.w r2, r7, #80 ; 0x50
8003b50: 4413 add r3, r2
8003b52: f833 3c3c ldrh.w r3, [r3, #-60]
8003b56: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
8003b5a: b29a uxth r2, r3
8003b5c: 6cbb ldr r3, [r7, #72] ; 0x48
8003b5e: 005b lsls r3, r3, #1
8003b60: f107 0150 add.w r1, r7, #80 ; 0x50
8003b64: 440b add r3, r1
8003b66: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_XY)
8003b6a: 4b5f ldr r3, [pc, #380] ; (8003ce8 <BSP_TS_GetState+0x280>)
8003b6c: 781b ldrb r3, [r3, #0]
8003b6e: f003 0308 and.w r3, r3, #8
8003b72: 2b00 cmp r3, #0
8003b74: d01b beq.n 8003bae <BSP_TS_GetState+0x146>
{
y[index] = brute_x[index];
8003b76: 6cbb ldr r3, [r7, #72] ; 0x48
8003b78: 005b lsls r3, r3, #1
8003b7a: f107 0250 add.w r2, r7, #80 ; 0x50
8003b7e: 4413 add r3, r2
8003b80: f833 2c30 ldrh.w r2, [r3, #-48]
8003b84: 6cbb ldr r3, [r7, #72] ; 0x48
8003b86: 005b lsls r3, r3, #1
8003b88: f107 0150 add.w r1, r7, #80 ; 0x50
8003b8c: 440b add r3, r1
8003b8e: f823 2c24 strh.w r2, [r3, #-36]
x[index] = brute_y[index];
8003b92: 6cbb ldr r3, [r7, #72] ; 0x48
8003b94: 005b lsls r3, r3, #1
8003b96: f107 0250 add.w r2, r7, #80 ; 0x50
8003b9a: 4413 add r3, r2
8003b9c: f833 2c3c ldrh.w r2, [r3, #-60]
8003ba0: 6cbb ldr r3, [r7, #72] ; 0x48
8003ba2: 005b lsls r3, r3, #1
8003ba4: f107 0150 add.w r1, r7, #80 ; 0x50
8003ba8: 440b add r3, r1
8003baa: f823 2c18 strh.w r2, [r3, #-24]
}
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
8003bae: 6cbb ldr r3, [r7, #72] ; 0x48
8003bb0: 005b lsls r3, r3, #1
8003bb2: f107 0250 add.w r2, r7, #80 ; 0x50
8003bb6: 4413 add r3, r2
8003bb8: f833 3c18 ldrh.w r3, [r3, #-24]
8003bbc: 4619 mov r1, r3
8003bbe: 4a4b ldr r2, [pc, #300] ; (8003cec <BSP_TS_GetState+0x284>)
8003bc0: 6cbb ldr r3, [r7, #72] ; 0x48
8003bc2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003bc6: 4299 cmp r1, r3
8003bc8: d90e bls.n 8003be8 <BSP_TS_GetState+0x180>
8003bca: 6cbb ldr r3, [r7, #72] ; 0x48
8003bcc: 005b lsls r3, r3, #1
8003bce: f107 0250 add.w r2, r7, #80 ; 0x50
8003bd2: 4413 add r3, r2
8003bd4: f833 2c18 ldrh.w r2, [r3, #-24]
8003bd8: 4944 ldr r1, [pc, #272] ; (8003cec <BSP_TS_GetState+0x284>)
8003bda: 6cbb ldr r3, [r7, #72] ; 0x48
8003bdc: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003be0: b29b uxth r3, r3
8003be2: 1ad3 subs r3, r2, r3
8003be4: b29b uxth r3, r3
8003be6: e00d b.n 8003c04 <BSP_TS_GetState+0x19c>
8003be8: 4a40 ldr r2, [pc, #256] ; (8003cec <BSP_TS_GetState+0x284>)
8003bea: 6cbb ldr r3, [r7, #72] ; 0x48
8003bec: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003bf0: b29a uxth r2, r3
8003bf2: 6cbb ldr r3, [r7, #72] ; 0x48
8003bf4: 005b lsls r3, r3, #1
8003bf6: f107 0150 add.w r1, r7, #80 ; 0x50
8003bfa: 440b add r3, r1
8003bfc: f833 3c18 ldrh.w r3, [r3, #-24]
8003c00: 1ad3 subs r3, r2, r3
8003c02: b29b uxth r3, r3
8003c04: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
8003c08: 6cbb ldr r3, [r7, #72] ; 0x48
8003c0a: 005b lsls r3, r3, #1
8003c0c: f107 0250 add.w r2, r7, #80 ; 0x50
8003c10: 4413 add r3, r2
8003c12: f833 3c24 ldrh.w r3, [r3, #-36]
8003c16: 4619 mov r1, r3
8003c18: 4a35 ldr r2, [pc, #212] ; (8003cf0 <BSP_TS_GetState+0x288>)
8003c1a: 6cbb ldr r3, [r7, #72] ; 0x48
8003c1c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c20: 4299 cmp r1, r3
8003c22: d90e bls.n 8003c42 <BSP_TS_GetState+0x1da>
8003c24: 6cbb ldr r3, [r7, #72] ; 0x48
8003c26: 005b lsls r3, r3, #1
8003c28: f107 0250 add.w r2, r7, #80 ; 0x50
8003c2c: 4413 add r3, r2
8003c2e: f833 2c24 ldrh.w r2, [r3, #-36]
8003c32: 492f ldr r1, [pc, #188] ; (8003cf0 <BSP_TS_GetState+0x288>)
8003c34: 6cbb ldr r3, [r7, #72] ; 0x48
8003c36: f851 3023 ldr.w r3, [r1, r3, lsl #2]
8003c3a: b29b uxth r3, r3
8003c3c: 1ad3 subs r3, r2, r3
8003c3e: b29b uxth r3, r3
8003c40: e00d b.n 8003c5e <BSP_TS_GetState+0x1f6>
8003c42: 4a2b ldr r2, [pc, #172] ; (8003cf0 <BSP_TS_GetState+0x288>)
8003c44: 6cbb ldr r3, [r7, #72] ; 0x48
8003c46: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003c4a: b29a uxth r2, r3
8003c4c: 6cbb ldr r3, [r7, #72] ; 0x48
8003c4e: 005b lsls r3, r3, #1
8003c50: f107 0150 add.w r1, r7, #80 ; 0x50
8003c54: 440b add r3, r1
8003c56: f833 3c24 ldrh.w r3, [r3, #-36]
8003c5a: 1ad3 subs r3, r2, r3
8003c5c: b29b uxth r3, r3
8003c5e: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if ((x_diff + y_diff) > 5)
8003c62: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
8003c66: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
8003c6a: 4413 add r3, r2
8003c6c: 2b05 cmp r3, #5
8003c6e: dd17 ble.n 8003ca0 <BSP_TS_GetState+0x238>
{
_x[index] = x[index];
8003c70: 6cbb ldr r3, [r7, #72] ; 0x48
8003c72: 005b lsls r3, r3, #1
8003c74: f107 0250 add.w r2, r7, #80 ; 0x50
8003c78: 4413 add r3, r2
8003c7a: f833 3c18 ldrh.w r3, [r3, #-24]
8003c7e: 4619 mov r1, r3
8003c80: 4a1a ldr r2, [pc, #104] ; (8003cec <BSP_TS_GetState+0x284>)
8003c82: 6cbb ldr r3, [r7, #72] ; 0x48
8003c84: f842 1023 str.w r1, [r2, r3, lsl #2]
_y[index] = y[index];
8003c88: 6cbb ldr r3, [r7, #72] ; 0x48
8003c8a: 005b lsls r3, r3, #1
8003c8c: f107 0250 add.w r2, r7, #80 ; 0x50
8003c90: 4413 add r3, r2
8003c92: f833 3c24 ldrh.w r3, [r3, #-36]
8003c96: 4619 mov r1, r3
8003c98: 4a15 ldr r2, [pc, #84] ; (8003cf0 <BSP_TS_GetState+0x288>)
8003c9a: 6cbb ldr r3, [r7, #72] ; 0x48
8003c9c: f842 1023 str.w r1, [r2, r3, lsl #2]
}
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
8003ca0: 4b10 ldr r3, [pc, #64] ; (8003ce4 <BSP_TS_GetState+0x27c>)
8003ca2: 781b ldrb r3, [r3, #0]
8003ca4: 2b70 cmp r3, #112 ; 0x70
8003ca6: d125 bne.n 8003cf4 <BSP_TS_GetState+0x28c>
{
TS_State->touchX[index] = x[index];
8003ca8: 6cbb ldr r3, [r7, #72] ; 0x48
8003caa: 005b lsls r3, r3, #1
8003cac: f107 0250 add.w r2, r7, #80 ; 0x50
8003cb0: 4413 add r3, r2
8003cb2: f833 1c18 ldrh.w r1, [r3, #-24]
8003cb6: 687a ldr r2, [r7, #4]
8003cb8: 6cbb ldr r3, [r7, #72] ; 0x48
8003cba: 005b lsls r3, r3, #1
8003cbc: 4413 add r3, r2
8003cbe: 460a mov r2, r1
8003cc0: 805a strh r2, [r3, #2]
TS_State->touchY[index] = y[index];
8003cc2: 6cbb ldr r3, [r7, #72] ; 0x48
8003cc4: 005b lsls r3, r3, #1
8003cc6: f107 0250 add.w r2, r7, #80 ; 0x50
8003cca: 4413 add r3, r2
8003ccc: f833 1c24 ldrh.w r1, [r3, #-36]
8003cd0: 687a ldr r2, [r7, #4]
8003cd2: 6cbb ldr r3, [r7, #72] ; 0x48
8003cd4: 3304 adds r3, #4
8003cd6: 005b lsls r3, r3, #1
8003cd8: 4413 add r3, r2
8003cda: 460a mov r2, r1
8003cdc: 809a strh r2, [r3, #4]
8003cde: e02c b.n 8003d3a <BSP_TS_GetState+0x2d2>
8003ce0: 20000548 .word 0x20000548
8003ce4: 20000551 .word 0x20000551
8003ce8: 20000550 .word 0x20000550
8003cec: 20000554 .word 0x20000554
8003cf0: 20000568 .word 0x20000568
}
else
{
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
8003cf4: 4b42 ldr r3, [pc, #264] ; (8003e00 <BSP_TS_GetState+0x398>)
8003cf6: 881b ldrh r3, [r3, #0]
8003cf8: 4619 mov r1, r3
8003cfa: 4a42 ldr r2, [pc, #264] ; (8003e04 <BSP_TS_GetState+0x39c>)
8003cfc: 6cbb ldr r3, [r7, #72] ; 0x48
8003cfe: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003d02: fb03 f301 mul.w r3, r3, r1
8003d06: 0b1b lsrs r3, r3, #12
8003d08: b299 uxth r1, r3
8003d0a: 687a ldr r2, [r7, #4]
8003d0c: 6cbb ldr r3, [r7, #72] ; 0x48
8003d0e: 005b lsls r3, r3, #1
8003d10: 4413 add r3, r2
8003d12: 460a mov r2, r1
8003d14: 805a strh r2, [r3, #2]
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
8003d16: 4b3c ldr r3, [pc, #240] ; (8003e08 <BSP_TS_GetState+0x3a0>)
8003d18: 881b ldrh r3, [r3, #0]
8003d1a: 4619 mov r1, r3
8003d1c: 4a3b ldr r2, [pc, #236] ; (8003e0c <BSP_TS_GetState+0x3a4>)
8003d1e: 6cbb ldr r3, [r7, #72] ; 0x48
8003d20: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003d24: fb03 f301 mul.w r3, r3, r1
8003d28: 0b1b lsrs r3, r3, #12
8003d2a: b299 uxth r1, r3
8003d2c: 687a ldr r2, [r7, #4]
8003d2e: 6cbb ldr r3, [r7, #72] ; 0x48
8003d30: 3304 adds r3, #4
8003d32: 005b lsls r3, r3, #1
8003d34: 4413 add r3, r2
8003d36: 460a mov r2, r1
8003d38: 809a strh r2, [r3, #4]
}
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get touch info related to the current touch */
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
8003d3a: 4b35 ldr r3, [pc, #212] ; (8003e10 <BSP_TS_GetState+0x3a8>)
8003d3c: 781b ldrb r3, [r3, #0]
8003d3e: b298 uxth r0, r3
8003d40: f107 010c add.w r1, r7, #12
8003d44: f107 0210 add.w r2, r7, #16
8003d48: f107 0308 add.w r3, r7, #8
8003d4c: 9300 str r3, [sp, #0]
8003d4e: 460b mov r3, r1
8003d50: 6cb9 ldr r1, [r7, #72] ; 0x48
8003d52: f7fc fe2b bl 80009ac <ft5336_TS_GetTouchInfo>
/* Update TS_State structure */
TS_State->touchWeight[index] = weight;
8003d56: 693b ldr r3, [r7, #16]
8003d58: b2d9 uxtb r1, r3
8003d5a: 687a ldr r2, [r7, #4]
8003d5c: 6cbb ldr r3, [r7, #72] ; 0x48
8003d5e: 4413 add r3, r2
8003d60: 3316 adds r3, #22
8003d62: 460a mov r2, r1
8003d64: 701a strb r2, [r3, #0]
TS_State->touchArea[index] = area;
8003d66: 68fb ldr r3, [r7, #12]
8003d68: b2d9 uxtb r1, r3
8003d6a: 687a ldr r2, [r7, #4]
8003d6c: 6cbb ldr r3, [r7, #72] ; 0x48
8003d6e: 4413 add r3, r2
8003d70: 3320 adds r3, #32
8003d72: 460a mov r2, r1
8003d74: 701a strb r2, [r3, #0]
/* Remap touch event */
switch(event)
8003d76: 68bb ldr r3, [r7, #8]
8003d78: 2b03 cmp r3, #3
8003d7a: d827 bhi.n 8003dcc <BSP_TS_GetState+0x364>
8003d7c: a201 add r2, pc, #4 ; (adr r2, 8003d84 <BSP_TS_GetState+0x31c>)
8003d7e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003d82: bf00 nop
8003d84: 08003d95 .word 0x08003d95
8003d88: 08003da3 .word 0x08003da3
8003d8c: 08003db1 .word 0x08003db1
8003d90: 08003dbf .word 0x08003dbf
{
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
8003d94: 687a ldr r2, [r7, #4]
8003d96: 6cbb ldr r3, [r7, #72] ; 0x48
8003d98: 4413 add r3, r2
8003d9a: 331b adds r3, #27
8003d9c: 2201 movs r2, #1
8003d9e: 701a strb r2, [r3, #0]
break;
8003da0: e018 b.n 8003dd4 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
8003da2: 687a ldr r2, [r7, #4]
8003da4: 6cbb ldr r3, [r7, #72] ; 0x48
8003da6: 4413 add r3, r2
8003da8: 331b adds r3, #27
8003daa: 2202 movs r2, #2
8003dac: 701a strb r2, [r3, #0]
break;
8003dae: e011 b.n 8003dd4 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_CONTACT :
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
8003db0: 687a ldr r2, [r7, #4]
8003db2: 6cbb ldr r3, [r7, #72] ; 0x48
8003db4: 4413 add r3, r2
8003db6: 331b adds r3, #27
8003db8: 2203 movs r2, #3
8003dba: 701a strb r2, [r3, #0]
break;
8003dbc: e00a b.n 8003dd4 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
8003dbe: 687a ldr r2, [r7, #4]
8003dc0: 6cbb ldr r3, [r7, #72] ; 0x48
8003dc2: 4413 add r3, r2
8003dc4: 331b adds r3, #27
8003dc6: 2200 movs r2, #0
8003dc8: 701a strb r2, [r3, #0]
break;
8003dca: e003 b.n 8003dd4 <BSP_TS_GetState+0x36c>
default :
ts_status = TS_ERROR;
8003dcc: 2301 movs r3, #1
8003dce: f887 304f strb.w r3, [r7, #79] ; 0x4f
break;
8003dd2: bf00 nop
for(index=0; index < TS_State->touchDetected; index++)
8003dd4: 6cbb ldr r3, [r7, #72] ; 0x48
8003dd6: 3301 adds r3, #1
8003dd8: 64bb str r3, [r7, #72] ; 0x48
8003dda: 687b ldr r3, [r7, #4]
8003ddc: 781b ldrb r3, [r3, #0]
8003dde: 461a mov r2, r3
8003de0: 6cbb ldr r3, [r7, #72] ; 0x48
8003de2: 4293 cmp r3, r2
8003de4: f4ff ae61 bcc.w 8003aaa <BSP_TS_GetState+0x42>
} /* of for(index=0; index < TS_State->touchDetected; index++) */
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get gesture Id */
ts_status = BSP_TS_Get_GestureId(TS_State);
8003de8: 6878 ldr r0, [r7, #4]
8003dea: f000 f813 bl 8003e14 <BSP_TS_Get_GestureId>
8003dee: 4603 mov r3, r0
8003df0: f887 304f strb.w r3, [r7, #79] ; 0x4f
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
} /* end of if(TS_State->touchDetected != 0) */
return (ts_status);
8003df4: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
}
8003df8: 4618 mov r0, r3
8003dfa: 3754 adds r7, #84 ; 0x54
8003dfc: 46bd mov sp, r7
8003dfe: bd90 pop {r4, r7, pc}
8003e00: 2000054c .word 0x2000054c
8003e04: 20000554 .word 0x20000554
8003e08: 2000054e .word 0x2000054e
8003e0c: 20000568 .word 0x20000568
8003e10: 20000551 .word 0x20000551
08003e14 <BSP_TS_Get_GestureId>:
* @brief Update gesture Id following a touch detected.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
{
8003e14: b580 push {r7, lr}
8003e16: b084 sub sp, #16
8003e18: af00 add r7, sp, #0
8003e1a: 6078 str r0, [r7, #4]
uint32_t gestureId = 0;
8003e1c: 2300 movs r3, #0
8003e1e: 60bb str r3, [r7, #8]
uint8_t ts_status = TS_OK;
8003e20: 2300 movs r3, #0
8003e22: 73fb strb r3, [r7, #15]
/* Get gesture Id */
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
8003e24: 4b1f ldr r3, [pc, #124] ; (8003ea4 <BSP_TS_Get_GestureId+0x90>)
8003e26: 781b ldrb r3, [r3, #0]
8003e28: b29b uxth r3, r3
8003e2a: f107 0208 add.w r2, r7, #8
8003e2e: 4611 mov r1, r2
8003e30: 4618 mov r0, r3
8003e32: f7fc fda2 bl 800097a <ft5336_TS_GetGestureID>
/* Remap gesture Id to a TS_GestureIdTypeDef value */
switch(gestureId)
8003e36: 68bb ldr r3, [r7, #8]
8003e38: 2b18 cmp r3, #24
8003e3a: d01b beq.n 8003e74 <BSP_TS_Get_GestureId+0x60>
8003e3c: 2b18 cmp r3, #24
8003e3e: d806 bhi.n 8003e4e <BSP_TS_Get_GestureId+0x3a>
8003e40: 2b10 cmp r3, #16
8003e42: d00f beq.n 8003e64 <BSP_TS_Get_GestureId+0x50>
8003e44: 2b14 cmp r3, #20
8003e46: d011 beq.n 8003e6c <BSP_TS_Get_GestureId+0x58>
8003e48: 2b00 cmp r3, #0
8003e4a: d007 beq.n 8003e5c <BSP_TS_Get_GestureId+0x48>
8003e4c: e022 b.n 8003e94 <BSP_TS_Get_GestureId+0x80>
8003e4e: 2b40 cmp r3, #64 ; 0x40
8003e50: d018 beq.n 8003e84 <BSP_TS_Get_GestureId+0x70>
8003e52: 2b49 cmp r3, #73 ; 0x49
8003e54: d01a beq.n 8003e8c <BSP_TS_Get_GestureId+0x78>
8003e56: 2b1c cmp r3, #28
8003e58: d010 beq.n 8003e7c <BSP_TS_Get_GestureId+0x68>
8003e5a: e01b b.n 8003e94 <BSP_TS_Get_GestureId+0x80>
{
case FT5336_GEST_ID_NO_GESTURE :
TS_State->gestureId = GEST_ID_NO_GESTURE;
8003e5c: 687b ldr r3, [r7, #4]
8003e5e: 2200 movs r2, #0
8003e60: 629a str r2, [r3, #40] ; 0x28
break;
8003e62: e01a b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_UP :
TS_State->gestureId = GEST_ID_MOVE_UP;
8003e64: 687b ldr r3, [r7, #4]
8003e66: 2201 movs r2, #1
8003e68: 629a str r2, [r3, #40] ; 0x28
break;
8003e6a: e016 b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_RIGHT :
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
8003e6c: 687b ldr r3, [r7, #4]
8003e6e: 2202 movs r2, #2
8003e70: 629a str r2, [r3, #40] ; 0x28
break;
8003e72: e012 b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_DOWN :
TS_State->gestureId = GEST_ID_MOVE_DOWN;
8003e74: 687b ldr r3, [r7, #4]
8003e76: 2203 movs r2, #3
8003e78: 629a str r2, [r3, #40] ; 0x28
break;
8003e7a: e00e b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_LEFT :
TS_State->gestureId = GEST_ID_MOVE_LEFT;
8003e7c: 687b ldr r3, [r7, #4]
8003e7e: 2204 movs r2, #4
8003e80: 629a str r2, [r3, #40] ; 0x28
break;
8003e82: e00a b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_IN :
TS_State->gestureId = GEST_ID_ZOOM_IN;
8003e84: 687b ldr r3, [r7, #4]
8003e86: 2205 movs r2, #5
8003e88: 629a str r2, [r3, #40] ; 0x28
break;
8003e8a: e006 b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_OUT :
TS_State->gestureId = GEST_ID_ZOOM_OUT;
8003e8c: 687b ldr r3, [r7, #4]
8003e8e: 2206 movs r2, #6
8003e90: 629a str r2, [r3, #40] ; 0x28
break;
8003e92: e002 b.n 8003e9a <BSP_TS_Get_GestureId+0x86>
default :
ts_status = TS_ERROR;
8003e94: 2301 movs r3, #1
8003e96: 73fb strb r3, [r7, #15]
break;
8003e98: bf00 nop
} /* of switch(gestureId) */
return(ts_status);
8003e9a: 7bfb ldrb r3, [r7, #15]
}
8003e9c: 4618 mov r0, r3
8003e9e: 3710 adds r7, #16
8003ea0: 46bd mov sp, r7
8003ea2: bd80 pop {r7, pc}
8003ea4: 20000551 .word 0x20000551
08003ea8 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8003ea8: b580 push {r7, lr}
8003eaa: b082 sub sp, #8
8003eac: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
8003eae: 4b11 ldr r3, [pc, #68] ; (8003ef4 <HAL_MspInit+0x4c>)
8003eb0: 6c1b ldr r3, [r3, #64] ; 0x40
8003eb2: 4a10 ldr r2, [pc, #64] ; (8003ef4 <HAL_MspInit+0x4c>)
8003eb4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003eb8: 6413 str r3, [r2, #64] ; 0x40
8003eba: 4b0e ldr r3, [pc, #56] ; (8003ef4 <HAL_MspInit+0x4c>)
8003ebc: 6c1b ldr r3, [r3, #64] ; 0x40
8003ebe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003ec2: 607b str r3, [r7, #4]
8003ec4: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003ec6: 4b0b ldr r3, [pc, #44] ; (8003ef4 <HAL_MspInit+0x4c>)
8003ec8: 6c5b ldr r3, [r3, #68] ; 0x44
8003eca: 4a0a ldr r2, [pc, #40] ; (8003ef4 <HAL_MspInit+0x4c>)
8003ecc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8003ed0: 6453 str r3, [r2, #68] ; 0x44
8003ed2: 4b08 ldr r3, [pc, #32] ; (8003ef4 <HAL_MspInit+0x4c>)
8003ed4: 6c5b ldr r3, [r3, #68] ; 0x44
8003ed6: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003eda: 603b str r3, [r7, #0]
8003edc: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8003ede: 2200 movs r2, #0
8003ee0: 210f movs r1, #15
8003ee2: f06f 0001 mvn.w r0, #1
8003ee6: f001 fa1b bl 8005320 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8003eea: bf00 nop
8003eec: 3708 adds r7, #8
8003eee: 46bd mov sp, r7
8003ef0: bd80 pop {r7, pc}
8003ef2: bf00 nop
8003ef4: 40023800 .word 0x40023800
08003ef8 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8003ef8: b580 push {r7, lr}
8003efa: b08c sub sp, #48 ; 0x30
8003efc: af00 add r7, sp, #0
8003efe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003f00: f107 031c add.w r3, r7, #28
8003f04: 2200 movs r2, #0
8003f06: 601a str r2, [r3, #0]
8003f08: 605a str r2, [r3, #4]
8003f0a: 609a str r2, [r3, #8]
8003f0c: 60da str r2, [r3, #12]
8003f0e: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
8003f10: 687b ldr r3, [r7, #4]
8003f12: 681b ldr r3, [r3, #0]
8003f14: 4a2a ldr r2, [pc, #168] ; (8003fc0 <HAL_ADC_MspInit+0xc8>)
8003f16: 4293 cmp r3, r2
8003f18: d124 bne.n 8003f64 <HAL_ADC_MspInit+0x6c>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8003f1a: 4b2a ldr r3, [pc, #168] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f1c: 6c5b ldr r3, [r3, #68] ; 0x44
8003f1e: 4a29 ldr r2, [pc, #164] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f20: f443 7380 orr.w r3, r3, #256 ; 0x100
8003f24: 6453 str r3, [r2, #68] ; 0x44
8003f26: 4b27 ldr r3, [pc, #156] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f28: 6c5b ldr r3, [r3, #68] ; 0x44
8003f2a: f403 7380 and.w r3, r3, #256 ; 0x100
8003f2e: 61bb str r3, [r7, #24]
8003f30: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
8003f32: 4b24 ldr r3, [pc, #144] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f34: 6b1b ldr r3, [r3, #48] ; 0x30
8003f36: 4a23 ldr r2, [pc, #140] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f38: f043 0301 orr.w r3, r3, #1
8003f3c: 6313 str r3, [r2, #48] ; 0x30
8003f3e: 4b21 ldr r3, [pc, #132] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f40: 6b1b ldr r3, [r3, #48] ; 0x30
8003f42: f003 0301 and.w r3, r3, #1
8003f46: 617b str r3, [r7, #20]
8003f48: 697b ldr r3, [r7, #20]
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
8003f4a: 2301 movs r3, #1
8003f4c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003f4e: 2303 movs r3, #3
8003f50: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003f52: 2300 movs r3, #0
8003f54: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8003f56: f107 031c add.w r3, r7, #28
8003f5a: 4619 mov r1, r3
8003f5c: 481a ldr r0, [pc, #104] ; (8003fc8 <HAL_ADC_MspInit+0xd0>)
8003f5e: f003 f98f bl 8007280 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
8003f62: e029 b.n 8003fb8 <HAL_ADC_MspInit+0xc0>
else if(hadc->Instance==ADC3)
8003f64: 687b ldr r3, [r7, #4]
8003f66: 681b ldr r3, [r3, #0]
8003f68: 4a18 ldr r2, [pc, #96] ; (8003fcc <HAL_ADC_MspInit+0xd4>)
8003f6a: 4293 cmp r3, r2
8003f6c: d124 bne.n 8003fb8 <HAL_ADC_MspInit+0xc0>
__HAL_RCC_ADC3_CLK_ENABLE();
8003f6e: 4b15 ldr r3, [pc, #84] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f70: 6c5b ldr r3, [r3, #68] ; 0x44
8003f72: 4a14 ldr r2, [pc, #80] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f74: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003f78: 6453 str r3, [r2, #68] ; 0x44
8003f7a: 4b12 ldr r3, [pc, #72] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f7c: 6c5b ldr r3, [r3, #68] ; 0x44
8003f7e: f403 6380 and.w r3, r3, #1024 ; 0x400
8003f82: 613b str r3, [r7, #16]
8003f84: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003f86: 4b0f ldr r3, [pc, #60] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f88: 6b1b ldr r3, [r3, #48] ; 0x30
8003f8a: 4a0e ldr r2, [pc, #56] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f8c: f043 0320 orr.w r3, r3, #32
8003f90: 6313 str r3, [r2, #48] ; 0x30
8003f92: 4b0c ldr r3, [pc, #48] ; (8003fc4 <HAL_ADC_MspInit+0xcc>)
8003f94: 6b1b ldr r3, [r3, #48] ; 0x30
8003f96: f003 0320 and.w r3, r3, #32
8003f9a: 60fb str r3, [r7, #12]
8003f9c: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
8003f9e: f44f 63e0 mov.w r3, #1792 ; 0x700
8003fa2: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003fa4: 2303 movs r3, #3
8003fa6: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003fa8: 2300 movs r3, #0
8003faa: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8003fac: f107 031c add.w r3, r7, #28
8003fb0: 4619 mov r1, r3
8003fb2: 4807 ldr r0, [pc, #28] ; (8003fd0 <HAL_ADC_MspInit+0xd8>)
8003fb4: f003 f964 bl 8007280 <HAL_GPIO_Init>
}
8003fb8: bf00 nop
8003fba: 3730 adds r7, #48 ; 0x30
8003fbc: 46bd mov sp, r7
8003fbe: bd80 pop {r7, pc}
8003fc0: 40012000 .word 0x40012000
8003fc4: 40023800 .word 0x40023800
8003fc8: 40020000 .word 0x40020000
8003fcc: 40012200 .word 0x40012200
8003fd0: 40021400 .word 0x40021400
08003fd4 <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
8003fd4: b480 push {r7}
8003fd6: b085 sub sp, #20
8003fd8: af00 add r7, sp, #0
8003fda: 6078 str r0, [r7, #4]
if(hcrc->Instance==CRC)
8003fdc: 687b ldr r3, [r7, #4]
8003fde: 681b ldr r3, [r3, #0]
8003fe0: 4a0a ldr r2, [pc, #40] ; (800400c <HAL_CRC_MspInit+0x38>)
8003fe2: 4293 cmp r3, r2
8003fe4: d10b bne.n 8003ffe <HAL_CRC_MspInit+0x2a>
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
8003fe6: 4b0a ldr r3, [pc, #40] ; (8004010 <HAL_CRC_MspInit+0x3c>)
8003fe8: 6b1b ldr r3, [r3, #48] ; 0x30
8003fea: 4a09 ldr r2, [pc, #36] ; (8004010 <HAL_CRC_MspInit+0x3c>)
8003fec: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8003ff0: 6313 str r3, [r2, #48] ; 0x30
8003ff2: 4b07 ldr r3, [pc, #28] ; (8004010 <HAL_CRC_MspInit+0x3c>)
8003ff4: 6b1b ldr r3, [r3, #48] ; 0x30
8003ff6: f403 5380 and.w r3, r3, #4096 ; 0x1000
8003ffa: 60fb str r3, [r7, #12]
8003ffc: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
8003ffe: bf00 nop
8004000: 3714 adds r7, #20
8004002: 46bd mov sp, r7
8004004: f85d 7b04 ldr.w r7, [sp], #4
8004008: 4770 bx lr
800400a: bf00 nop
800400c: 40023000 .word 0x40023000
8004010: 40023800 .word 0x40023800
08004014 <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
8004014: b580 push {r7, lr}
8004016: b08a sub sp, #40 ; 0x28
8004018: af00 add r7, sp, #0
800401a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800401c: f107 0314 add.w r3, r7, #20
8004020: 2200 movs r2, #0
8004022: 601a str r2, [r3, #0]
8004024: 605a str r2, [r3, #4]
8004026: 609a str r2, [r3, #8]
8004028: 60da str r2, [r3, #12]
800402a: 611a str r2, [r3, #16]
if(hdac->Instance==DAC)
800402c: 687b ldr r3, [r7, #4]
800402e: 681b ldr r3, [r3, #0]
8004030: 4a19 ldr r2, [pc, #100] ; (8004098 <HAL_DAC_MspInit+0x84>)
8004032: 4293 cmp r3, r2
8004034: d12b bne.n 800408e <HAL_DAC_MspInit+0x7a>
{
/* USER CODE BEGIN DAC_MspInit 0 */
/* USER CODE END DAC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC_CLK_ENABLE();
8004036: 4b19 ldr r3, [pc, #100] ; (800409c <HAL_DAC_MspInit+0x88>)
8004038: 6c1b ldr r3, [r3, #64] ; 0x40
800403a: 4a18 ldr r2, [pc, #96] ; (800409c <HAL_DAC_MspInit+0x88>)
800403c: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8004040: 6413 str r3, [r2, #64] ; 0x40
8004042: 4b16 ldr r3, [pc, #88] ; (800409c <HAL_DAC_MspInit+0x88>)
8004044: 6c1b ldr r3, [r3, #64] ; 0x40
8004046: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800404a: 613b str r3, [r7, #16]
800404c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800404e: 4b13 ldr r3, [pc, #76] ; (800409c <HAL_DAC_MspInit+0x88>)
8004050: 6b1b ldr r3, [r3, #48] ; 0x30
8004052: 4a12 ldr r2, [pc, #72] ; (800409c <HAL_DAC_MspInit+0x88>)
8004054: f043 0301 orr.w r3, r3, #1
8004058: 6313 str r3, [r2, #48] ; 0x30
800405a: 4b10 ldr r3, [pc, #64] ; (800409c <HAL_DAC_MspInit+0x88>)
800405c: 6b1b ldr r3, [r3, #48] ; 0x30
800405e: f003 0301 and.w r3, r3, #1
8004062: 60fb str r3, [r7, #12]
8004064: 68fb ldr r3, [r7, #12]
/**DAC GPIO Configuration
PA4 ------> DAC_OUT1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
8004066: 2310 movs r3, #16
8004068: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800406a: 2303 movs r3, #3
800406c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800406e: 2300 movs r3, #0
8004070: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8004072: f107 0314 add.w r3, r7, #20
8004076: 4619 mov r1, r3
8004078: 4809 ldr r0, [pc, #36] ; (80040a0 <HAL_DAC_MspInit+0x8c>)
800407a: f003 f901 bl 8007280 <HAL_GPIO_Init>
/* DAC interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
800407e: 2200 movs r2, #0
8004080: 2100 movs r1, #0
8004082: 2036 movs r0, #54 ; 0x36
8004084: f001 f94c bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8004088: 2036 movs r0, #54 ; 0x36
800408a: f001 f965 bl 8005358 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN DAC_MspInit 1 */
/* USER CODE END DAC_MspInit 1 */
}
}
800408e: bf00 nop
8004090: 3728 adds r7, #40 ; 0x28
8004092: 46bd mov sp, r7
8004094: bd80 pop {r7, pc}
8004096: bf00 nop
8004098: 40007400 .word 0x40007400
800409c: 40023800 .word 0x40023800
80040a0: 40020000 .word 0x40020000
080040a4 <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
80040a4: b480 push {r7}
80040a6: b085 sub sp, #20
80040a8: af00 add r7, sp, #0
80040aa: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
80040ac: 687b ldr r3, [r7, #4]
80040ae: 681b ldr r3, [r3, #0]
80040b0: 4a0a ldr r2, [pc, #40] ; (80040dc <HAL_DMA2D_MspInit+0x38>)
80040b2: 4293 cmp r3, r2
80040b4: d10b bne.n 80040ce <HAL_DMA2D_MspInit+0x2a>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
80040b6: 4b0a ldr r3, [pc, #40] ; (80040e0 <HAL_DMA2D_MspInit+0x3c>)
80040b8: 6b1b ldr r3, [r3, #48] ; 0x30
80040ba: 4a09 ldr r2, [pc, #36] ; (80040e0 <HAL_DMA2D_MspInit+0x3c>)
80040bc: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
80040c0: 6313 str r3, [r2, #48] ; 0x30
80040c2: 4b07 ldr r3, [pc, #28] ; (80040e0 <HAL_DMA2D_MspInit+0x3c>)
80040c4: 6b1b ldr r3, [r3, #48] ; 0x30
80040c6: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80040ca: 60fb str r3, [r7, #12]
80040cc: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
80040ce: bf00 nop
80040d0: 3714 adds r7, #20
80040d2: 46bd mov sp, r7
80040d4: f85d 7b04 ldr.w r7, [sp], #4
80040d8: 4770 bx lr
80040da: bf00 nop
80040dc: 4002b000 .word 0x4002b000
80040e0: 40023800 .word 0x40023800
080040e4 <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
80040e4: b580 push {r7, lr}
80040e6: b08e sub sp, #56 ; 0x38
80040e8: af00 add r7, sp, #0
80040ea: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80040ec: f107 0324 add.w r3, r7, #36 ; 0x24
80040f0: 2200 movs r2, #0
80040f2: 601a str r2, [r3, #0]
80040f4: 605a str r2, [r3, #4]
80040f6: 609a str r2, [r3, #8]
80040f8: 60da str r2, [r3, #12]
80040fa: 611a str r2, [r3, #16]
if(hltdc->Instance==LTDC)
80040fc: 687b ldr r3, [r7, #4]
80040fe: 681b ldr r3, [r3, #0]
8004100: 4a55 ldr r2, [pc, #340] ; (8004258 <HAL_LTDC_MspInit+0x174>)
8004102: 4293 cmp r3, r2
8004104: f040 80a3 bne.w 800424e <HAL_LTDC_MspInit+0x16a>
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8004108: 4b54 ldr r3, [pc, #336] ; (800425c <HAL_LTDC_MspInit+0x178>)
800410a: 6c5b ldr r3, [r3, #68] ; 0x44
800410c: 4a53 ldr r2, [pc, #332] ; (800425c <HAL_LTDC_MspInit+0x178>)
800410e: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8004112: 6453 str r3, [r2, #68] ; 0x44
8004114: 4b51 ldr r3, [pc, #324] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004116: 6c5b ldr r3, [r3, #68] ; 0x44
8004118: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800411c: 623b str r3, [r7, #32]
800411e: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOE_CLK_ENABLE();
8004120: 4b4e ldr r3, [pc, #312] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004122: 6b1b ldr r3, [r3, #48] ; 0x30
8004124: 4a4d ldr r2, [pc, #308] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004126: f043 0310 orr.w r3, r3, #16
800412a: 6313 str r3, [r2, #48] ; 0x30
800412c: 4b4b ldr r3, [pc, #300] ; (800425c <HAL_LTDC_MspInit+0x178>)
800412e: 6b1b ldr r3, [r3, #48] ; 0x30
8004130: f003 0310 and.w r3, r3, #16
8004134: 61fb str r3, [r7, #28]
8004136: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8004138: 4b48 ldr r3, [pc, #288] ; (800425c <HAL_LTDC_MspInit+0x178>)
800413a: 6b1b ldr r3, [r3, #48] ; 0x30
800413c: 4a47 ldr r2, [pc, #284] ; (800425c <HAL_LTDC_MspInit+0x178>)
800413e: f443 7300 orr.w r3, r3, #512 ; 0x200
8004142: 6313 str r3, [r2, #48] ; 0x30
8004144: 4b45 ldr r3, [pc, #276] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004146: 6b1b ldr r3, [r3, #48] ; 0x30
8004148: f403 7300 and.w r3, r3, #512 ; 0x200
800414c: 61bb str r3, [r7, #24]
800414e: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOK_CLK_ENABLE();
8004150: 4b42 ldr r3, [pc, #264] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004152: 6b1b ldr r3, [r3, #48] ; 0x30
8004154: 4a41 ldr r2, [pc, #260] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004156: f443 6380 orr.w r3, r3, #1024 ; 0x400
800415a: 6313 str r3, [r2, #48] ; 0x30
800415c: 4b3f ldr r3, [pc, #252] ; (800425c <HAL_LTDC_MspInit+0x178>)
800415e: 6b1b ldr r3, [r3, #48] ; 0x30
8004160: f403 6380 and.w r3, r3, #1024 ; 0x400
8004164: 617b str r3, [r7, #20]
8004166: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8004168: 4b3c ldr r3, [pc, #240] ; (800425c <HAL_LTDC_MspInit+0x178>)
800416a: 6b1b ldr r3, [r3, #48] ; 0x30
800416c: 4a3b ldr r2, [pc, #236] ; (800425c <HAL_LTDC_MspInit+0x178>)
800416e: f043 0340 orr.w r3, r3, #64 ; 0x40
8004172: 6313 str r3, [r2, #48] ; 0x30
8004174: 4b39 ldr r3, [pc, #228] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004176: 6b1b ldr r3, [r3, #48] ; 0x30
8004178: f003 0340 and.w r3, r3, #64 ; 0x40
800417c: 613b str r3, [r7, #16]
800417e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
8004180: 4b36 ldr r3, [pc, #216] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004182: 6b1b ldr r3, [r3, #48] ; 0x30
8004184: 4a35 ldr r2, [pc, #212] ; (800425c <HAL_LTDC_MspInit+0x178>)
8004186: f443 7380 orr.w r3, r3, #256 ; 0x100
800418a: 6313 str r3, [r2, #48] ; 0x30
800418c: 4b33 ldr r3, [pc, #204] ; (800425c <HAL_LTDC_MspInit+0x178>)
800418e: 6b1b ldr r3, [r3, #48] ; 0x30
8004190: f403 7380 and.w r3, r3, #256 ; 0x100
8004194: 60fb str r3, [r7, #12]
8004196: 68fb ldr r3, [r7, #12]
PJ3 ------> LTDC_R4
PJ2 ------> LTDC_R3
PJ0 ------> LTDC_R1
PJ1 ------> LTDC_R2
*/
GPIO_InitStruct.Pin = LCD_B0_Pin;
8004198: 2310 movs r3, #16
800419a: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800419c: 2302 movs r3, #2
800419e: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041a0: 2300 movs r3, #0
80041a2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80041a4: 2300 movs r3, #0
80041a6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041a8: 230e movs r3, #14
80041aa: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct);
80041ac: f107 0324 add.w r3, r7, #36 ; 0x24
80041b0: 4619 mov r1, r3
80041b2: 482b ldr r0, [pc, #172] ; (8004260 <HAL_LTDC_MspInit+0x17c>)
80041b4: f003 f864 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin
80041b8: f64e 73ff movw r3, #61439 ; 0xefff
80041bc: 627b str r3, [r7, #36] ; 0x24
|LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin
|LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin
|LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041be: 2302 movs r3, #2
80041c0: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041c2: 2300 movs r3, #0
80041c4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80041c6: 2300 movs r3, #0
80041c8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041ca: 230e movs r3, #14
80041cc: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
80041ce: f107 0324 add.w r3, r7, #36 ; 0x24
80041d2: 4619 mov r1, r3
80041d4: 4823 ldr r0, [pc, #140] ; (8004264 <HAL_LTDC_MspInit+0x180>)
80041d6: f003 f853 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin
80041da: 23f7 movs r3, #247 ; 0xf7
80041dc: 627b str r3, [r7, #36] ; 0x24
|LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041de: 2302 movs r3, #2
80041e0: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041e2: 2300 movs r3, #0
80041e4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80041e6: 2300 movs r3, #0
80041e8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80041ea: 230e movs r3, #14
80041ec: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
80041ee: f107 0324 add.w r3, r7, #36 ; 0x24
80041f2: 4619 mov r1, r3
80041f4: 481c ldr r0, [pc, #112] ; (8004268 <HAL_LTDC_MspInit+0x184>)
80041f6: f003 f843 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B4_Pin;
80041fa: f44f 5380 mov.w r3, #4096 ; 0x1000
80041fe: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004200: 2302 movs r3, #2
8004202: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004204: 2300 movs r3, #0
8004206: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8004208: 2300 movs r3, #0
800420a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
800420c: 2309 movs r3, #9
800420e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct);
8004210: f107 0324 add.w r3, r7, #36 ; 0x24
8004214: 4619 mov r1, r3
8004216: 4815 ldr r0, [pc, #84] ; (800426c <HAL_LTDC_MspInit+0x188>)
8004218: f003 f832 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin;
800421c: f44f 4346 mov.w r3, #50688 ; 0xc600
8004220: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004222: 2302 movs r3, #2
8004224: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004226: 2300 movs r3, #0
8004228: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800422a: 2300 movs r3, #0
800422c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
800422e: 230e movs r3, #14
8004230: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8004232: f107 0324 add.w r3, r7, #36 ; 0x24
8004236: 4619 mov r1, r3
8004238: 480d ldr r0, [pc, #52] ; (8004270 <HAL_LTDC_MspInit+0x18c>)
800423a: f003 f821 bl 8007280 <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
800423e: 2200 movs r2, #0
8004240: 2105 movs r1, #5
8004242: 2058 movs r0, #88 ; 0x58
8004244: f001 f86c bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
8004248: 2058 movs r0, #88 ; 0x58
800424a: f001 f885 bl 8005358 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
800424e: bf00 nop
8004250: 3738 adds r7, #56 ; 0x38
8004252: 46bd mov sp, r7
8004254: bd80 pop {r7, pc}
8004256: bf00 nop
8004258: 40016800 .word 0x40016800
800425c: 40023800 .word 0x40023800
8004260: 40021000 .word 0x40021000
8004264: 40022400 .word 0x40022400
8004268: 40022800 .word 0x40022800
800426c: 40021800 .word 0x40021800
8004270: 40022000 .word 0x40022000
08004274 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
8004274: b480 push {r7}
8004276: b085 sub sp, #20
8004278: af00 add r7, sp, #0
800427a: 6078 str r0, [r7, #4]
if(hrng->Instance==RNG)
800427c: 687b ldr r3, [r7, #4]
800427e: 681b ldr r3, [r3, #0]
8004280: 4a0a ldr r2, [pc, #40] ; (80042ac <HAL_RNG_MspInit+0x38>)
8004282: 4293 cmp r3, r2
8004284: d10b bne.n 800429e <HAL_RNG_MspInit+0x2a>
{
/* USER CODE BEGIN RNG_MspInit 0 */
/* USER CODE END RNG_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RNG_CLK_ENABLE();
8004286: 4b0a ldr r3, [pc, #40] ; (80042b0 <HAL_RNG_MspInit+0x3c>)
8004288: 6b5b ldr r3, [r3, #52] ; 0x34
800428a: 4a09 ldr r2, [pc, #36] ; (80042b0 <HAL_RNG_MspInit+0x3c>)
800428c: f043 0340 orr.w r3, r3, #64 ; 0x40
8004290: 6353 str r3, [r2, #52] ; 0x34
8004292: 4b07 ldr r3, [pc, #28] ; (80042b0 <HAL_RNG_MspInit+0x3c>)
8004294: 6b5b ldr r3, [r3, #52] ; 0x34
8004296: f003 0340 and.w r3, r3, #64 ; 0x40
800429a: 60fb str r3, [r7, #12]
800429c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN RNG_MspInit 1 */
/* USER CODE END RNG_MspInit 1 */
}
}
800429e: bf00 nop
80042a0: 3714 adds r7, #20
80042a2: 46bd mov sp, r7
80042a4: f85d 7b04 ldr.w r7, [sp], #4
80042a8: 4770 bx lr
80042aa: bf00 nop
80042ac: 50060800 .word 0x50060800
80042b0: 40023800 .word 0x40023800
080042b4 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80042b4: b580 push {r7, lr}
80042b6: b08a sub sp, #40 ; 0x28
80042b8: af00 add r7, sp, #0
80042ba: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80042bc: f107 0314 add.w r3, r7, #20
80042c0: 2200 movs r2, #0
80042c2: 601a str r2, [r3, #0]
80042c4: 605a str r2, [r3, #4]
80042c6: 609a str r2, [r3, #8]
80042c8: 60da str r2, [r3, #12]
80042ca: 611a str r2, [r3, #16]
if(hspi->Instance==SPI2)
80042cc: 687b ldr r3, [r7, #4]
80042ce: 681b ldr r3, [r3, #0]
80042d0: 4a2d ldr r2, [pc, #180] ; (8004388 <HAL_SPI_MspInit+0xd4>)
80042d2: 4293 cmp r3, r2
80042d4: d154 bne.n 8004380 <HAL_SPI_MspInit+0xcc>
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
80042d6: 4b2d ldr r3, [pc, #180] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042d8: 6c1b ldr r3, [r3, #64] ; 0x40
80042da: 4a2c ldr r2, [pc, #176] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042dc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80042e0: 6413 str r3, [r2, #64] ; 0x40
80042e2: 4b2a ldr r3, [pc, #168] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042e4: 6c1b ldr r3, [r3, #64] ; 0x40
80042e6: f403 4380 and.w r3, r3, #16384 ; 0x4000
80042ea: 613b str r3, [r7, #16]
80042ec: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
80042ee: 4b27 ldr r3, [pc, #156] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042f0: 6b1b ldr r3, [r3, #48] ; 0x30
80042f2: 4a26 ldr r2, [pc, #152] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042f4: f443 7380 orr.w r3, r3, #256 ; 0x100
80042f8: 6313 str r3, [r2, #48] ; 0x30
80042fa: 4b24 ldr r3, [pc, #144] ; (800438c <HAL_SPI_MspInit+0xd8>)
80042fc: 6b1b ldr r3, [r3, #48] ; 0x30
80042fe: f403 7380 and.w r3, r3, #256 ; 0x100
8004302: 60fb str r3, [r7, #12]
8004304: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8004306: 4b21 ldr r3, [pc, #132] ; (800438c <HAL_SPI_MspInit+0xd8>)
8004308: 6b1b ldr r3, [r3, #48] ; 0x30
800430a: 4a20 ldr r2, [pc, #128] ; (800438c <HAL_SPI_MspInit+0xd8>)
800430c: f043 0302 orr.w r3, r3, #2
8004310: 6313 str r3, [r2, #48] ; 0x30
8004312: 4b1e ldr r3, [pc, #120] ; (800438c <HAL_SPI_MspInit+0xd8>)
8004314: 6b1b ldr r3, [r3, #48] ; 0x30
8004316: f003 0302 and.w r3, r3, #2
800431a: 60bb str r3, [r7, #8]
800431c: 68bb ldr r3, [r7, #8]
PI1 ------> SPI2_SCK
PI0 ------> SPI2_NSS
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
800431e: 2302 movs r3, #2
8004320: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004322: 2302 movs r3, #2
8004324: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004326: 2300 movs r3, #0
8004328: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800432a: 2300 movs r3, #0
800432c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
800432e: 2305 movs r3, #5
8004330: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
8004332: f107 0314 add.w r3, r7, #20
8004336: 4619 mov r1, r3
8004338: 4815 ldr r0, [pc, #84] ; (8004390 <HAL_SPI_MspInit+0xdc>)
800433a: f002 ffa1 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0;
800433e: 2301 movs r3, #1
8004340: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004342: 2302 movs r3, #2
8004344: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004346: 2300 movs r3, #0
8004348: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800434a: 2303 movs r3, #3
800434c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
800434e: 2305 movs r3, #5
8004350: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8004352: f107 0314 add.w r3, r7, #20
8004356: 4619 mov r1, r3
8004358: 480d ldr r0, [pc, #52] ; (8004390 <HAL_SPI_MspInit+0xdc>)
800435a: f002 ff91 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
800435e: f44f 4340 mov.w r3, #49152 ; 0xc000
8004362: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004364: 2302 movs r3, #2
8004366: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004368: 2300 movs r3, #0
800436a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800436c: 2303 movs r3, #3
800436e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8004370: 2305 movs r3, #5
8004372: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8004374: f107 0314 add.w r3, r7, #20
8004378: 4619 mov r1, r3
800437a: 4806 ldr r0, [pc, #24] ; (8004394 <HAL_SPI_MspInit+0xe0>)
800437c: f002 ff80 bl 8007280 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8004380: bf00 nop
8004382: 3728 adds r7, #40 ; 0x28
8004384: 46bd mov sp, r7
8004386: bd80 pop {r7, pc}
8004388: 40003800 .word 0x40003800
800438c: 40023800 .word 0x40023800
8004390: 40022000 .word 0x40022000
8004394: 40020400 .word 0x40020400
08004398 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8004398: b480 push {r7}
800439a: b089 sub sp, #36 ; 0x24
800439c: af00 add r7, sp, #0
800439e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
80043a0: 687b ldr r3, [r7, #4]
80043a2: 681b ldr r3, [r3, #0]
80043a4: 4a2e ldr r2, [pc, #184] ; (8004460 <HAL_TIM_Base_MspInit+0xc8>)
80043a6: 4293 cmp r3, r2
80043a8: d10c bne.n 80043c4 <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
80043aa: 4b2e ldr r3, [pc, #184] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043ac: 6c5b ldr r3, [r3, #68] ; 0x44
80043ae: 4a2d ldr r2, [pc, #180] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043b0: f043 0301 orr.w r3, r3, #1
80043b4: 6453 str r3, [r2, #68] ; 0x44
80043b6: 4b2b ldr r3, [pc, #172] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043b8: 6c5b ldr r3, [r3, #68] ; 0x44
80043ba: f003 0301 and.w r3, r3, #1
80043be: 61fb str r3, [r7, #28]
80043c0: 69fb ldr r3, [r7, #28]
/* USER CODE BEGIN TIM8_MspInit 1 */
/* USER CODE END TIM8_MspInit 1 */
}
}
80043c2: e046 b.n 8004452 <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM2)
80043c4: 687b ldr r3, [r7, #4]
80043c6: 681b ldr r3, [r3, #0]
80043c8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80043cc: d10c bne.n 80043e8 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
80043ce: 4b25 ldr r3, [pc, #148] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043d0: 6c1b ldr r3, [r3, #64] ; 0x40
80043d2: 4a24 ldr r2, [pc, #144] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043d4: f043 0301 orr.w r3, r3, #1
80043d8: 6413 str r3, [r2, #64] ; 0x40
80043da: 4b22 ldr r3, [pc, #136] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043dc: 6c1b ldr r3, [r3, #64] ; 0x40
80043de: f003 0301 and.w r3, r3, #1
80043e2: 61bb str r3, [r7, #24]
80043e4: 69bb ldr r3, [r7, #24]
}
80043e6: e034 b.n 8004452 <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM3)
80043e8: 687b ldr r3, [r7, #4]
80043ea: 681b ldr r3, [r3, #0]
80043ec: 4a1e ldr r2, [pc, #120] ; (8004468 <HAL_TIM_Base_MspInit+0xd0>)
80043ee: 4293 cmp r3, r2
80043f0: d10c bne.n 800440c <HAL_TIM_Base_MspInit+0x74>
__HAL_RCC_TIM3_CLK_ENABLE();
80043f2: 4b1c ldr r3, [pc, #112] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043f4: 6c1b ldr r3, [r3, #64] ; 0x40
80043f6: 4a1b ldr r2, [pc, #108] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
80043f8: f043 0302 orr.w r3, r3, #2
80043fc: 6413 str r3, [r2, #64] ; 0x40
80043fe: 4b19 ldr r3, [pc, #100] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
8004400: 6c1b ldr r3, [r3, #64] ; 0x40
8004402: f003 0302 and.w r3, r3, #2
8004406: 617b str r3, [r7, #20]
8004408: 697b ldr r3, [r7, #20]
}
800440a: e022 b.n 8004452 <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM5)
800440c: 687b ldr r3, [r7, #4]
800440e: 681b ldr r3, [r3, #0]
8004410: 4a16 ldr r2, [pc, #88] ; (800446c <HAL_TIM_Base_MspInit+0xd4>)
8004412: 4293 cmp r3, r2
8004414: d10c bne.n 8004430 <HAL_TIM_Base_MspInit+0x98>
__HAL_RCC_TIM5_CLK_ENABLE();
8004416: 4b13 ldr r3, [pc, #76] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
8004418: 6c1b ldr r3, [r3, #64] ; 0x40
800441a: 4a12 ldr r2, [pc, #72] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
800441c: f043 0308 orr.w r3, r3, #8
8004420: 6413 str r3, [r2, #64] ; 0x40
8004422: 4b10 ldr r3, [pc, #64] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
8004424: 6c1b ldr r3, [r3, #64] ; 0x40
8004426: f003 0308 and.w r3, r3, #8
800442a: 613b str r3, [r7, #16]
800442c: 693b ldr r3, [r7, #16]
}
800442e: e010 b.n 8004452 <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM8)
8004430: 687b ldr r3, [r7, #4]
8004432: 681b ldr r3, [r3, #0]
8004434: 4a0e ldr r2, [pc, #56] ; (8004470 <HAL_TIM_Base_MspInit+0xd8>)
8004436: 4293 cmp r3, r2
8004438: d10b bne.n 8004452 <HAL_TIM_Base_MspInit+0xba>
__HAL_RCC_TIM8_CLK_ENABLE();
800443a: 4b0a ldr r3, [pc, #40] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
800443c: 6c5b ldr r3, [r3, #68] ; 0x44
800443e: 4a09 ldr r2, [pc, #36] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
8004440: f043 0302 orr.w r3, r3, #2
8004444: 6453 str r3, [r2, #68] ; 0x44
8004446: 4b07 ldr r3, [pc, #28] ; (8004464 <HAL_TIM_Base_MspInit+0xcc>)
8004448: 6c5b ldr r3, [r3, #68] ; 0x44
800444a: f003 0302 and.w r3, r3, #2
800444e: 60fb str r3, [r7, #12]
8004450: 68fb ldr r3, [r7, #12]
}
8004452: bf00 nop
8004454: 3724 adds r7, #36 ; 0x24
8004456: 46bd mov sp, r7
8004458: f85d 7b04 ldr.w r7, [sp], #4
800445c: 4770 bx lr
800445e: bf00 nop
8004460: 40010000 .word 0x40010000
8004464: 40023800 .word 0x40023800
8004468: 40000400 .word 0x40000400
800446c: 40000c00 .word 0x40000c00
8004470: 40010400 .word 0x40010400
08004474 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8004474: b580 push {r7, lr}
8004476: b08a sub sp, #40 ; 0x28
8004478: af00 add r7, sp, #0
800447a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800447c: f107 0314 add.w r3, r7, #20
8004480: 2200 movs r2, #0
8004482: 601a str r2, [r3, #0]
8004484: 605a str r2, [r3, #4]
8004486: 609a str r2, [r3, #8]
8004488: 60da str r2, [r3, #12]
800448a: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
800448c: 687b ldr r3, [r7, #4]
800448e: 681b ldr r3, [r3, #0]
8004490: 4a22 ldr r2, [pc, #136] ; (800451c <HAL_TIM_MspPostInit+0xa8>)
8004492: 4293 cmp r3, r2
8004494: d11c bne.n 80044d0 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8004496: 4b22 ldr r3, [pc, #136] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
8004498: 6b1b ldr r3, [r3, #48] ; 0x30
800449a: 4a21 ldr r2, [pc, #132] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
800449c: f043 0302 orr.w r3, r3, #2
80044a0: 6313 str r3, [r2, #48] ; 0x30
80044a2: 4b1f ldr r3, [pc, #124] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
80044a4: 6b1b ldr r3, [r3, #48] ; 0x30
80044a6: f003 0302 and.w r3, r3, #2
80044aa: 613b str r3, [r7, #16]
80044ac: 693b ldr r3, [r7, #16]
/**TIM3 GPIO Configuration
PB4 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
80044ae: 2310 movs r3, #16
80044b0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80044b2: 2302 movs r3, #2
80044b4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80044b6: 2300 movs r3, #0
80044b8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80044ba: 2300 movs r3, #0
80044bc: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
80044be: 2302 movs r3, #2
80044c0: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80044c2: f107 0314 add.w r3, r7, #20
80044c6: 4619 mov r1, r3
80044c8: 4816 ldr r0, [pc, #88] ; (8004524 <HAL_TIM_MspPostInit+0xb0>)
80044ca: f002 fed9 bl 8007280 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM8_MspPostInit 1 */
/* USER CODE END TIM8_MspPostInit 1 */
}
}
80044ce: e020 b.n 8004512 <HAL_TIM_MspPostInit+0x9e>
else if(htim->Instance==TIM8)
80044d0: 687b ldr r3, [r7, #4]
80044d2: 681b ldr r3, [r3, #0]
80044d4: 4a14 ldr r2, [pc, #80] ; (8004528 <HAL_TIM_MspPostInit+0xb4>)
80044d6: 4293 cmp r3, r2
80044d8: d11b bne.n 8004512 <HAL_TIM_MspPostInit+0x9e>
__HAL_RCC_GPIOI_CLK_ENABLE();
80044da: 4b11 ldr r3, [pc, #68] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
80044dc: 6b1b ldr r3, [r3, #48] ; 0x30
80044de: 4a10 ldr r2, [pc, #64] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
80044e0: f443 7380 orr.w r3, r3, #256 ; 0x100
80044e4: 6313 str r3, [r2, #48] ; 0x30
80044e6: 4b0e ldr r3, [pc, #56] ; (8004520 <HAL_TIM_MspPostInit+0xac>)
80044e8: 6b1b ldr r3, [r3, #48] ; 0x30
80044ea: f403 7380 and.w r3, r3, #256 ; 0x100
80044ee: 60fb str r3, [r7, #12]
80044f0: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_2;
80044f2: 2304 movs r3, #4
80044f4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80044f6: 2302 movs r3, #2
80044f8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80044fa: 2300 movs r3, #0
80044fc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80044fe: 2300 movs r3, #0
8004500: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
8004502: 2303 movs r3, #3
8004504: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8004506: f107 0314 add.w r3, r7, #20
800450a: 4619 mov r1, r3
800450c: 4807 ldr r0, [pc, #28] ; (800452c <HAL_TIM_MspPostInit+0xb8>)
800450e: f002 feb7 bl 8007280 <HAL_GPIO_Init>
}
8004512: bf00 nop
8004514: 3728 adds r7, #40 ; 0x28
8004516: 46bd mov sp, r7
8004518: bd80 pop {r7, pc}
800451a: bf00 nop
800451c: 40000400 .word 0x40000400
8004520: 40023800 .word 0x40023800
8004524: 40020400 .word 0x40020400
8004528: 40010400 .word 0x40010400
800452c: 40022000 .word 0x40022000
08004530 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
8004530: b580 push {r7, lr}
8004532: b086 sub sp, #24
8004534: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
8004536: 1d3b adds r3, r7, #4
8004538: 2200 movs r2, #0
800453a: 601a str r2, [r3, #0]
800453c: 605a str r2, [r3, #4]
800453e: 609a str r2, [r3, #8]
8004540: 60da str r2, [r3, #12]
8004542: 611a str r2, [r3, #16]
if (FMC_Initialized) {
8004544: 4b3a ldr r3, [pc, #232] ; (8004630 <HAL_FMC_MspInit+0x100>)
8004546: 681b ldr r3, [r3, #0]
8004548: 2b00 cmp r3, #0
800454a: d16d bne.n 8004628 <HAL_FMC_MspInit+0xf8>
return;
}
FMC_Initialized = 1;
800454c: 4b38 ldr r3, [pc, #224] ; (8004630 <HAL_FMC_MspInit+0x100>)
800454e: 2201 movs r2, #1
8004550: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
8004552: 4b38 ldr r3, [pc, #224] ; (8004634 <HAL_FMC_MspInit+0x104>)
8004554: 6b9b ldr r3, [r3, #56] ; 0x38
8004556: 4a37 ldr r2, [pc, #220] ; (8004634 <HAL_FMC_MspInit+0x104>)
8004558: f043 0301 orr.w r3, r3, #1
800455c: 6393 str r3, [r2, #56] ; 0x38
800455e: 4b35 ldr r3, [pc, #212] ; (8004634 <HAL_FMC_MspInit+0x104>)
8004560: 6b9b ldr r3, [r3, #56] ; 0x38
8004562: f003 0301 and.w r3, r3, #1
8004566: 603b str r3, [r7, #0]
8004568: 683b ldr r3, [r7, #0]
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
800456a: f64f 7383 movw r3, #65411 ; 0xff83
800456e: 607b str r3, [r7, #4]
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004570: 2302 movs r3, #2
8004572: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004574: 2300 movs r3, #0
8004576: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004578: 2303 movs r3, #3
800457a: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
800457c: 230c movs r3, #12
800457e: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8004580: 1d3b adds r3, r7, #4
8004582: 4619 mov r1, r3
8004584: 482c ldr r0, [pc, #176] ; (8004638 <HAL_FMC_MspInit+0x108>)
8004586: f002 fe7b bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
800458a: f248 1333 movw r3, #33075 ; 0x8133
800458e: 607b str r3, [r7, #4]
|GPIO_PIN_5|GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004590: 2302 movs r3, #2
8004592: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004594: 2300 movs r3, #0
8004596: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004598: 2303 movs r3, #3
800459a: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
800459c: 230c movs r3, #12
800459e: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
80045a0: 1d3b adds r3, r7, #4
80045a2: 4619 mov r1, r3
80045a4: 4825 ldr r0, [pc, #148] ; (800463c <HAL_FMC_MspInit+0x10c>)
80045a6: f002 fe6b bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
80045aa: f24c 7303 movw r3, #50947 ; 0xc703
80045ae: 607b str r3, [r7, #4]
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045b0: 2302 movs r3, #2
80045b2: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045b4: 2300 movs r3, #0
80045b6: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045b8: 2303 movs r3, #3
80045ba: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045bc: 230c movs r3, #12
80045be: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80045c0: 1d3b adds r3, r7, #4
80045c2: 4619 mov r1, r3
80045c4: 481e ldr r0, [pc, #120] ; (8004640 <HAL_FMC_MspInit+0x110>)
80045c6: f002 fe5b bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
80045ca: f64f 033f movw r3, #63551 ; 0xf83f
80045ce: 607b str r3, [r7, #4]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045d0: 2302 movs r3, #2
80045d2: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045d4: 2300 movs r3, #0
80045d6: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045d8: 2303 movs r3, #3
80045da: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045dc: 230c movs r3, #12
80045de: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80045e0: 1d3b adds r3, r7, #4
80045e2: 4619 mov r1, r3
80045e4: 4817 ldr r0, [pc, #92] ; (8004644 <HAL_FMC_MspInit+0x114>)
80045e6: f002 fe4b bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
80045ea: 2328 movs r3, #40 ; 0x28
80045ec: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80045ee: 2302 movs r3, #2
80045f0: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80045f2: 2300 movs r3, #0
80045f4: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80045f6: 2303 movs r3, #3
80045f8: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80045fa: 230c movs r3, #12
80045fc: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
80045fe: 1d3b adds r3, r7, #4
8004600: 4619 mov r1, r3
8004602: 4811 ldr r0, [pc, #68] ; (8004648 <HAL_FMC_MspInit+0x118>)
8004604: f002 fe3c bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
8004608: 2308 movs r3, #8
800460a: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800460c: 2302 movs r3, #2
800460e: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004610: 2300 movs r3, #0
8004612: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004614: 2303 movs r3, #3
8004616: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004618: 230c movs r3, #12
800461a: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800461c: 1d3b adds r3, r7, #4
800461e: 4619 mov r1, r3
8004620: 480a ldr r0, [pc, #40] ; (800464c <HAL_FMC_MspInit+0x11c>)
8004622: f002 fe2d bl 8007280 <HAL_GPIO_Init>
8004626: e000 b.n 800462a <HAL_FMC_MspInit+0xfa>
return;
8004628: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
800462a: 3718 adds r7, #24
800462c: 46bd mov sp, r7
800462e: bd80 pop {r7, pc}
8004630: 2000057c .word 0x2000057c
8004634: 40023800 .word 0x40023800
8004638: 40021000 .word 0x40021000
800463c: 40021800 .word 0x40021800
8004640: 40020c00 .word 0x40020c00
8004644: 40021400 .word 0x40021400
8004648: 40021c00 .word 0x40021c00
800464c: 40020800 .word 0x40020800
08004650 <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
8004650: b580 push {r7, lr}
8004652: b082 sub sp, #8
8004654: af00 add r7, sp, #0
8004656: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
8004658: f7ff ff6a bl 8004530 <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
800465c: bf00 nop
800465e: 3708 adds r7, #8
8004660: 46bd mov sp, r7
8004662: bd80 pop {r7, pc}
08004664 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8004664: b580 push {r7, lr}
8004666: b08c sub sp, #48 ; 0x30
8004668: af00 add r7, sp, #0
800466a: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
800466c: 2300 movs r3, #0
800466e: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
8004670: 2300 movs r3, #0
8004672: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
8004674: 2200 movs r2, #0
8004676: 6879 ldr r1, [r7, #4]
8004678: 2036 movs r0, #54 ; 0x36
800467a: f000 fe51 bl 8005320 <HAL_NVIC_SetPriority>
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
800467e: 2036 movs r0, #54 ; 0x36
8004680: f000 fe6a bl 8005358 <HAL_NVIC_EnableIRQ>
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
8004684: 4b1f ldr r3, [pc, #124] ; (8004704 <HAL_InitTick+0xa0>)
8004686: 6c1b ldr r3, [r3, #64] ; 0x40
8004688: 4a1e ldr r2, [pc, #120] ; (8004704 <HAL_InitTick+0xa0>)
800468a: f043 0310 orr.w r3, r3, #16
800468e: 6413 str r3, [r2, #64] ; 0x40
8004690: 4b1c ldr r3, [pc, #112] ; (8004704 <HAL_InitTick+0xa0>)
8004692: 6c1b ldr r3, [r3, #64] ; 0x40
8004694: f003 0310 and.w r3, r3, #16
8004698: 60fb str r3, [r7, #12]
800469a: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
800469c: f107 0210 add.w r2, r7, #16
80046a0: f107 0314 add.w r3, r7, #20
80046a4: 4611 mov r1, r2
80046a6: 4618 mov r0, r3
80046a8: f004 fd46 bl 8009138 <HAL_RCC_GetClockConfig>
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
80046ac: f004 fd30 bl 8009110 <HAL_RCC_GetPCLK1Freq>
80046b0: 4603 mov r3, r0
80046b2: 005b lsls r3, r3, #1
80046b4: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
80046b6: 6afb ldr r3, [r7, #44] ; 0x2c
80046b8: 4a13 ldr r2, [pc, #76] ; (8004708 <HAL_InitTick+0xa4>)
80046ba: fba2 2303 umull r2, r3, r2, r3
80046be: 0c9b lsrs r3, r3, #18
80046c0: 3b01 subs r3, #1
80046c2: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
80046c4: 4b11 ldr r3, [pc, #68] ; (800470c <HAL_InitTick+0xa8>)
80046c6: 4a12 ldr r2, [pc, #72] ; (8004710 <HAL_InitTick+0xac>)
80046c8: 601a str r2, [r3, #0]
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
80046ca: 4b10 ldr r3, [pc, #64] ; (800470c <HAL_InitTick+0xa8>)
80046cc: f240 32e7 movw r2, #999 ; 0x3e7
80046d0: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
80046d2: 4a0e ldr r2, [pc, #56] ; (800470c <HAL_InitTick+0xa8>)
80046d4: 6abb ldr r3, [r7, #40] ; 0x28
80046d6: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
80046d8: 4b0c ldr r3, [pc, #48] ; (800470c <HAL_InitTick+0xa8>)
80046da: 2200 movs r2, #0
80046dc: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
80046de: 4b0b ldr r3, [pc, #44] ; (800470c <HAL_InitTick+0xa8>)
80046e0: 2200 movs r2, #0
80046e2: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
80046e4: 4809 ldr r0, [pc, #36] ; (800470c <HAL_InitTick+0xa8>)
80046e6: f005 fa82 bl 8009bee <HAL_TIM_Base_Init>
80046ea: 4603 mov r3, r0
80046ec: 2b00 cmp r3, #0
80046ee: d104 bne.n 80046fa <HAL_InitTick+0x96>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
80046f0: 4806 ldr r0, [pc, #24] ; (800470c <HAL_InitTick+0xa8>)
80046f2: f005 faa7 bl 8009c44 <HAL_TIM_Base_Start_IT>
80046f6: 4603 mov r3, r0
80046f8: e000 b.n 80046fc <HAL_InitTick+0x98>
}
/* Return function status */
return HAL_ERROR;
80046fa: 2301 movs r3, #1
}
80046fc: 4618 mov r0, r3
80046fe: 3730 adds r7, #48 ; 0x30
8004700: 46bd mov sp, r7
8004702: bd80 pop {r7, pc}
8004704: 40023800 .word 0x40023800
8004708: 431bde83 .word 0x431bde83
800470c: 20008d10 .word 0x20008d10
8004710: 40001000 .word 0x40001000
08004714 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8004714: b480 push {r7}
8004716: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8004718: e7fe b.n 8004718 <NMI_Handler+0x4>
0800471a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800471a: b480 push {r7}
800471c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800471e: e7fe b.n 800471e <HardFault_Handler+0x4>
08004720 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8004720: b480 push {r7}
8004722: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8004724: e7fe b.n 8004724 <MemManage_Handler+0x4>
08004726 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8004726: b480 push {r7}
8004728: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800472a: e7fe b.n 800472a <BusFault_Handler+0x4>
0800472c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
800472c: b480 push {r7}
800472e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8004730: e7fe b.n 8004730 <UsageFault_Handler+0x4>
08004732 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8004732: b480 push {r7}
8004734: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8004736: bf00 nop
8004738: 46bd mov sp, r7
800473a: f85d 7b04 ldr.w r7, [sp], #4
800473e: 4770 bx lr
08004740 <EXTI9_5_IRQHandler>:
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void EXTI9_5_IRQHandler(void)
{
8004740: b580 push {r7, lr}
8004742: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI9_5_IRQn 0 */
/* USER CODE END EXTI9_5_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
8004744: f44f 7080 mov.w r0, #256 ; 0x100
8004748: f002 ff78 bl 800763c <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI9_5_IRQn 1 */
/* USER CODE END EXTI9_5_IRQn 1 */
}
800474c: bf00 nop
800474e: bd80 pop {r7, pc}
08004750 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
8004750: b580 push {r7, lr}
8004752: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_DAC_IRQHandler(&hdac);
8004754: 4803 ldr r0, [pc, #12] ; (8004764 <TIM6_DAC_IRQHandler+0x14>)
8004756: f000 ff19 bl 800558c <HAL_DAC_IRQHandler>
HAL_TIM_IRQHandler(&htim6);
800475a: 4803 ldr r0, [pc, #12] ; (8004768 <TIM6_DAC_IRQHandler+0x18>)
800475c: f005 fad1 bl 8009d02 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
8004760: bf00 nop
8004762: bd80 pop {r7, pc}
8004764: 20008b0c .word 0x20008b0c
8004768: 20008d10 .word 0x20008d10
0800476c <ETH_IRQHandler>:
/**
* @brief This function handles Ethernet global interrupt.
*/
void ETH_IRQHandler(void)
{
800476c: b580 push {r7, lr}
800476e: af00 add r7, sp, #0
/* USER CODE BEGIN ETH_IRQn 0 */
/* USER CODE END ETH_IRQn 0 */
HAL_ETH_IRQHandler(&heth);
8004770: 4802 ldr r0, [pc, #8] ; (800477c <ETH_IRQHandler+0x10>)
8004772: f001 ffe3 bl 800673c <HAL_ETH_IRQHandler>
/* USER CODE BEGIN ETH_IRQn 1 */
/* USER CODE END ETH_IRQn 1 */
}
8004776: bf00 nop
8004778: bd80 pop {r7, pc}
800477a: bf00 nop
800477c: 2000a670 .word 0x2000a670
08004780 <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
8004780: b580 push {r7, lr}
8004782: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
8004784: 4802 ldr r0, [pc, #8] ; (8004790 <LTDC_IRQHandler+0x10>)
8004786: f003 fd6d bl 8008264 <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
800478a: bf00 nop
800478c: bd80 pop {r7, pc}
800478e: bf00 nop
8004790: 200089cc .word 0x200089cc
08004794 <_read>:
_kill(status, -1);
while (1) {} /* Make sure we hang here */
}
__attribute__((weak)) int _read(int file, char *ptr, int len)
{
8004794: b580 push {r7, lr}
8004796: b086 sub sp, #24
8004798: af00 add r7, sp, #0
800479a: 60f8 str r0, [r7, #12]
800479c: 60b9 str r1, [r7, #8]
800479e: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047a0: 2300 movs r3, #0
80047a2: 617b str r3, [r7, #20]
80047a4: e00a b.n 80047bc <_read+0x28>
{
*ptr++ = __io_getchar();
80047a6: f3af 8000 nop.w
80047aa: 4601 mov r1, r0
80047ac: 68bb ldr r3, [r7, #8]
80047ae: 1c5a adds r2, r3, #1
80047b0: 60ba str r2, [r7, #8]
80047b2: b2ca uxtb r2, r1
80047b4: 701a strb r2, [r3, #0]
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047b6: 697b ldr r3, [r7, #20]
80047b8: 3301 adds r3, #1
80047ba: 617b str r3, [r7, #20]
80047bc: 697a ldr r2, [r7, #20]
80047be: 687b ldr r3, [r7, #4]
80047c0: 429a cmp r2, r3
80047c2: dbf0 blt.n 80047a6 <_read+0x12>
}
return len;
80047c4: 687b ldr r3, [r7, #4]
}
80047c6: 4618 mov r0, r3
80047c8: 3718 adds r7, #24
80047ca: 46bd mov sp, r7
80047cc: bd80 pop {r7, pc}
080047ce <_write>:
__attribute__((weak)) int _write(int file, char *ptr, int len)
{
80047ce: b580 push {r7, lr}
80047d0: b086 sub sp, #24
80047d2: af00 add r7, sp, #0
80047d4: 60f8 str r0, [r7, #12]
80047d6: 60b9 str r1, [r7, #8]
80047d8: 607a str r2, [r7, #4]
int DataIdx;
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047da: 2300 movs r3, #0
80047dc: 617b str r3, [r7, #20]
80047de: e009 b.n 80047f4 <_write+0x26>
{
__io_putchar(*ptr++);
80047e0: 68bb ldr r3, [r7, #8]
80047e2: 1c5a adds r2, r3, #1
80047e4: 60ba str r2, [r7, #8]
80047e6: 781b ldrb r3, [r3, #0]
80047e8: 4618 mov r0, r3
80047ea: f3af 8000 nop.w
for (DataIdx = 0; DataIdx < len; DataIdx++)
80047ee: 697b ldr r3, [r7, #20]
80047f0: 3301 adds r3, #1
80047f2: 617b str r3, [r7, #20]
80047f4: 697a ldr r2, [r7, #20]
80047f6: 687b ldr r3, [r7, #4]
80047f8: 429a cmp r2, r3
80047fa: dbf1 blt.n 80047e0 <_write+0x12>
}
return len;
80047fc: 687b ldr r3, [r7, #4]
}
80047fe: 4618 mov r0, r3
8004800: 3718 adds r7, #24
8004802: 46bd mov sp, r7
8004804: bd80 pop {r7, pc}
08004806 <_close>:
int _close(int file)
{
8004806: b480 push {r7}
8004808: b083 sub sp, #12
800480a: af00 add r7, sp, #0
800480c: 6078 str r0, [r7, #4]
return -1;
800480e: f04f 33ff mov.w r3, #4294967295
}
8004812: 4618 mov r0, r3
8004814: 370c adds r7, #12
8004816: 46bd mov sp, r7
8004818: f85d 7b04 ldr.w r7, [sp], #4
800481c: 4770 bx lr
0800481e <_fstat>:
int _fstat(int file, struct stat *st)
{
800481e: b480 push {r7}
8004820: b083 sub sp, #12
8004822: af00 add r7, sp, #0
8004824: 6078 str r0, [r7, #4]
8004826: 6039 str r1, [r7, #0]
st->st_mode = S_IFCHR;
8004828: 683b ldr r3, [r7, #0]
800482a: f44f 5200 mov.w r2, #8192 ; 0x2000
800482e: 605a str r2, [r3, #4]
return 0;
8004830: 2300 movs r3, #0
}
8004832: 4618 mov r0, r3
8004834: 370c adds r7, #12
8004836: 46bd mov sp, r7
8004838: f85d 7b04 ldr.w r7, [sp], #4
800483c: 4770 bx lr
0800483e <_isatty>:
int _isatty(int file)
{
800483e: b480 push {r7}
8004840: b083 sub sp, #12
8004842: af00 add r7, sp, #0
8004844: 6078 str r0, [r7, #4]
return 1;
8004846: 2301 movs r3, #1
}
8004848: 4618 mov r0, r3
800484a: 370c adds r7, #12
800484c: 46bd mov sp, r7
800484e: f85d 7b04 ldr.w r7, [sp], #4
8004852: 4770 bx lr
08004854 <_lseek>:
int _lseek(int file, int ptr, int dir)
{
8004854: b480 push {r7}
8004856: b085 sub sp, #20
8004858: af00 add r7, sp, #0
800485a: 60f8 str r0, [r7, #12]
800485c: 60b9 str r1, [r7, #8]
800485e: 607a str r2, [r7, #4]
return 0;
8004860: 2300 movs r3, #0
}
8004862: 4618 mov r0, r3
8004864: 3714 adds r7, #20
8004866: 46bd mov sp, r7
8004868: f85d 7b04 ldr.w r7, [sp], #4
800486c: 4770 bx lr
...
08004870 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8004870: b480 push {r7}
8004872: b087 sub sp, #28
8004874: af00 add r7, sp, #0
8004876: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8004878: 4a14 ldr r2, [pc, #80] ; (80048cc <_sbrk+0x5c>)
800487a: 4b15 ldr r3, [pc, #84] ; (80048d0 <_sbrk+0x60>)
800487c: 1ad3 subs r3, r2, r3
800487e: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8004880: 697b ldr r3, [r7, #20]
8004882: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8004884: 4b13 ldr r3, [pc, #76] ; (80048d4 <_sbrk+0x64>)
8004886: 681b ldr r3, [r3, #0]
8004888: 2b00 cmp r3, #0
800488a: d102 bne.n 8004892 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
800488c: 4b11 ldr r3, [pc, #68] ; (80048d4 <_sbrk+0x64>)
800488e: 4a12 ldr r2, [pc, #72] ; (80048d8 <_sbrk+0x68>)
8004890: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8004892: 4b10 ldr r3, [pc, #64] ; (80048d4 <_sbrk+0x64>)
8004894: 681a ldr r2, [r3, #0]
8004896: 687b ldr r3, [r7, #4]
8004898: 4413 add r3, r2
800489a: 693a ldr r2, [r7, #16]
800489c: 429a cmp r2, r3
800489e: d205 bcs.n 80048ac <_sbrk+0x3c>
{
errno = ENOMEM;
80048a0: 4b0e ldr r3, [pc, #56] ; (80048dc <_sbrk+0x6c>)
80048a2: 220c movs r2, #12
80048a4: 601a str r2, [r3, #0]
return (void *)-1;
80048a6: f04f 33ff mov.w r3, #4294967295
80048aa: e009 b.n 80048c0 <_sbrk+0x50>
}
prev_heap_end = __sbrk_heap_end;
80048ac: 4b09 ldr r3, [pc, #36] ; (80048d4 <_sbrk+0x64>)
80048ae: 681b ldr r3, [r3, #0]
80048b0: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
80048b2: 4b08 ldr r3, [pc, #32] ; (80048d4 <_sbrk+0x64>)
80048b4: 681a ldr r2, [r3, #0]
80048b6: 687b ldr r3, [r7, #4]
80048b8: 4413 add r3, r2
80048ba: 4a06 ldr r2, [pc, #24] ; (80048d4 <_sbrk+0x64>)
80048bc: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
80048be: 68fb ldr r3, [r7, #12]
}
80048c0: 4618 mov r0, r3
80048c2: 371c adds r7, #28
80048c4: 46bd mov sp, r7
80048c6: f85d 7b04 ldr.w r7, [sp], #4
80048ca: 4770 bx lr
80048cc: 20050000 .word 0x20050000
80048d0: 00000400 .word 0x00000400
80048d4: 20000580 .word 0x20000580
80048d8: 2000f610 .word 0x2000f610
80048dc: 2000f604 .word 0x2000f604
080048e0 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
80048e0: b480 push {r7}
80048e2: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80048e4: 4b08 ldr r3, [pc, #32] ; (8004908 <SystemInit+0x28>)
80048e6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80048ea: 4a07 ldr r2, [pc, #28] ; (8004908 <SystemInit+0x28>)
80048ec: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
80048f0: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
80048f4: 4b04 ldr r3, [pc, #16] ; (8004908 <SystemInit+0x28>)
80048f6: f04f 6200 mov.w r2, #134217728 ; 0x8000000
80048fa: 609a str r2, [r3, #8]
#endif
}
80048fc: bf00 nop
80048fe: 46bd mov sp, r7
8004900: f85d 7b04 ldr.w r7, [sp], #4
8004904: 4770 bx lr
8004906: bf00 nop
8004908: e000ed00 .word 0xe000ed00
0800490c <Reset_Handler>:
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler: ldr sp, =_estack /* set stack pointer */
800490c: f8df d034 ldr.w sp, [pc, #52] ; 8004944 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8004910: 2100 movs r1, #0
b LoopCopyDataInit
8004912: e003 b.n 800491c <LoopCopyDataInit>
08004914 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8004914: 4b0c ldr r3, [pc, #48] ; (8004948 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
8004916: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8004918: 5043 str r3, [r0, r1]
adds r1, r1, #4
800491a: 3104 adds r1, #4
0800491c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
800491c: 480b ldr r0, [pc, #44] ; (800494c <LoopFillZerobss+0x1c>)
ldr r3, =_edata
800491e: 4b0c ldr r3, [pc, #48] ; (8004950 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8004920: 1842 adds r2, r0, r1
cmp r2, r3
8004922: 429a cmp r2, r3
bcc CopyDataInit
8004924: d3f6 bcc.n 8004914 <CopyDataInit>
ldr r2, =_sbss
8004926: 4a0b ldr r2, [pc, #44] ; (8004954 <LoopFillZerobss+0x24>)
b LoopFillZerobss
8004928: e002 b.n 8004930 <LoopFillZerobss>
0800492a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800492a: 2300 movs r3, #0
str r3, [r2], #4
800492c: f842 3b04 str.w r3, [r2], #4
08004930 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8004930: 4b09 ldr r3, [pc, #36] ; (8004958 <LoopFillZerobss+0x28>)
cmp r2, r3
8004932: 429a cmp r2, r3
bcc FillZerobss
8004934: d3f9 bcc.n 800492a <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8004936: f7ff ffd3 bl 80048e0 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800493a: f016 fb2d bl 801af98 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800493e: f7fc f90d bl 8000b5c <main>
bx lr
8004942: 4770 bx lr
Reset_Handler: ldr sp, =_estack /* set stack pointer */
8004944: 20050000 .word 0x20050000
ldr r3, =_sidata
8004948: 08020f40 .word 0x08020f40
ldr r0, =_sdata
800494c: 20000000 .word 0x20000000
ldr r3, =_edata
8004950: 200000e8 .word 0x200000e8
ldr r2, =_sbss
8004954: 200000e8 .word 0x200000e8
ldr r3, = _ebss
8004958: 2000f60c .word 0x2000f60c
0800495c <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
800495c: e7fe b.n 800495c <ADC_IRQHandler>
0800495e <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
800495e: b580 push {r7, lr}
8004960: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8004962: 2003 movs r0, #3
8004964: f000 fcd1 bl 800530a <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8004968: 2000 movs r0, #0
800496a: f7ff fe7b bl 8004664 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800496e: f7ff fa9b bl 8003ea8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8004972: 2300 movs r3, #0
}
8004974: 4618 mov r0, r3
8004976: bd80 pop {r7, pc}
08004978 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8004978: b480 push {r7}
800497a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800497c: 4b06 ldr r3, [pc, #24] ; (8004998 <HAL_IncTick+0x20>)
800497e: 781b ldrb r3, [r3, #0]
8004980: 461a mov r2, r3
8004982: 4b06 ldr r3, [pc, #24] ; (800499c <HAL_IncTick+0x24>)
8004984: 681b ldr r3, [r3, #0]
8004986: 4413 add r3, r2
8004988: 4a04 ldr r2, [pc, #16] ; (800499c <HAL_IncTick+0x24>)
800498a: 6013 str r3, [r2, #0]
}
800498c: bf00 nop
800498e: 46bd mov sp, r7
8004990: f85d 7b04 ldr.w r7, [sp], #4
8004994: 4770 bx lr
8004996: bf00 nop
8004998: 2000006c .word 0x2000006c
800499c: 20008d50 .word 0x20008d50
080049a0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80049a0: b480 push {r7}
80049a2: af00 add r7, sp, #0
return uwTick;
80049a4: 4b03 ldr r3, [pc, #12] ; (80049b4 <HAL_GetTick+0x14>)
80049a6: 681b ldr r3, [r3, #0]
}
80049a8: 4618 mov r0, r3
80049aa: 46bd mov sp, r7
80049ac: f85d 7b04 ldr.w r7, [sp], #4
80049b0: 4770 bx lr
80049b2: bf00 nop
80049b4: 20008d50 .word 0x20008d50
080049b8 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80049b8: b580 push {r7, lr}
80049ba: b084 sub sp, #16
80049bc: af00 add r7, sp, #0
80049be: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
80049c0: f7ff ffee bl 80049a0 <HAL_GetTick>
80049c4: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
80049c6: 687b ldr r3, [r7, #4]
80049c8: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80049ca: 68fb ldr r3, [r7, #12]
80049cc: f1b3 3fff cmp.w r3, #4294967295
80049d0: d005 beq.n 80049de <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
80049d2: 4b09 ldr r3, [pc, #36] ; (80049f8 <HAL_Delay+0x40>)
80049d4: 781b ldrb r3, [r3, #0]
80049d6: 461a mov r2, r3
80049d8: 68fb ldr r3, [r7, #12]
80049da: 4413 add r3, r2
80049dc: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
80049de: bf00 nop
80049e0: f7ff ffde bl 80049a0 <HAL_GetTick>
80049e4: 4602 mov r2, r0
80049e6: 68bb ldr r3, [r7, #8]
80049e8: 1ad3 subs r3, r2, r3
80049ea: 68fa ldr r2, [r7, #12]
80049ec: 429a cmp r2, r3
80049ee: d8f7 bhi.n 80049e0 <HAL_Delay+0x28>
{
}
}
80049f0: bf00 nop
80049f2: 3710 adds r7, #16
80049f4: 46bd mov sp, r7
80049f6: bd80 pop {r7, pc}
80049f8: 2000006c .word 0x2000006c
080049fc <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
80049fc: b580 push {r7, lr}
80049fe: b084 sub sp, #16
8004a00: af00 add r7, sp, #0
8004a02: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8004a04: 2300 movs r3, #0
8004a06: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
8004a08: 687b ldr r3, [r7, #4]
8004a0a: 2b00 cmp r3, #0
8004a0c: d101 bne.n 8004a12 <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8004a0e: 2301 movs r3, #1
8004a10: e031 b.n 8004a76 <HAL_ADC_Init+0x7a>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8004a12: 687b ldr r3, [r7, #4]
8004a14: 6c1b ldr r3, [r3, #64] ; 0x40
8004a16: 2b00 cmp r3, #0
8004a18: d109 bne.n 8004a2e <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8004a1a: 6878 ldr r0, [r7, #4]
8004a1c: f7ff fa6c bl 8003ef8 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8004a20: 687b ldr r3, [r7, #4]
8004a22: 2200 movs r2, #0
8004a24: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8004a26: 687b ldr r3, [r7, #4]
8004a28: 2200 movs r2, #0
8004a2a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8004a2e: 687b ldr r3, [r7, #4]
8004a30: 6c1b ldr r3, [r3, #64] ; 0x40
8004a32: f003 0310 and.w r3, r3, #16
8004a36: 2b00 cmp r3, #0
8004a38: d116 bne.n 8004a68 <HAL_ADC_Init+0x6c>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8004a3a: 687b ldr r3, [r7, #4]
8004a3c: 6c1a ldr r2, [r3, #64] ; 0x40
8004a3e: 4b10 ldr r3, [pc, #64] ; (8004a80 <HAL_ADC_Init+0x84>)
8004a40: 4013 ands r3, r2
8004a42: f043 0202 orr.w r2, r3, #2
8004a46: 687b ldr r3, [r7, #4]
8004a48: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
8004a4a: 6878 ldr r0, [r7, #4]
8004a4c: f000 fab6 bl 8004fbc <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8004a50: 687b ldr r3, [r7, #4]
8004a52: 2200 movs r2, #0
8004a54: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8004a56: 687b ldr r3, [r7, #4]
8004a58: 6c1b ldr r3, [r3, #64] ; 0x40
8004a5a: f023 0303 bic.w r3, r3, #3
8004a5e: f043 0201 orr.w r2, r3, #1
8004a62: 687b ldr r3, [r7, #4]
8004a64: 641a str r2, [r3, #64] ; 0x40
8004a66: e001 b.n 8004a6c <HAL_ADC_Init+0x70>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
8004a68: 2301 movs r3, #1
8004a6a: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
8004a6c: 687b ldr r3, [r7, #4]
8004a6e: 2200 movs r2, #0
8004a70: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
8004a74: 7bfb ldrb r3, [r7, #15]
}
8004a76: 4618 mov r0, r3
8004a78: 3710 adds r7, #16
8004a7a: 46bd mov sp, r7
8004a7c: bd80 pop {r7, pc}
8004a7e: bf00 nop
8004a80: ffffeefd .word 0xffffeefd
08004a84 <HAL_ADC_Start>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8004a84: b480 push {r7}
8004a86: b085 sub sp, #20
8004a88: af00 add r7, sp, #0
8004a8a: 6078 str r0, [r7, #4]
__IO uint32_t counter = 0;
8004a8c: 2300 movs r3, #0
8004a8e: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
8004a90: 687b ldr r3, [r7, #4]
8004a92: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004a96: 2b01 cmp r3, #1
8004a98: d101 bne.n 8004a9e <HAL_ADC_Start+0x1a>
8004a9a: 2302 movs r3, #2
8004a9c: e0a0 b.n 8004be0 <HAL_ADC_Start+0x15c>
8004a9e: 687b ldr r3, [r7, #4]
8004aa0: 2201 movs r2, #1
8004aa2: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
8004aa6: 687b ldr r3, [r7, #4]
8004aa8: 681b ldr r3, [r3, #0]
8004aaa: 689b ldr r3, [r3, #8]
8004aac: f003 0301 and.w r3, r3, #1
8004ab0: 2b01 cmp r3, #1
8004ab2: d018 beq.n 8004ae6 <HAL_ADC_Start+0x62>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8004ab4: 687b ldr r3, [r7, #4]
8004ab6: 681b ldr r3, [r3, #0]
8004ab8: 689a ldr r2, [r3, #8]
8004aba: 687b ldr r3, [r7, #4]
8004abc: 681b ldr r3, [r3, #0]
8004abe: f042 0201 orr.w r2, r2, #1
8004ac2: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
8004ac4: 4b49 ldr r3, [pc, #292] ; (8004bec <HAL_ADC_Start+0x168>)
8004ac6: 681b ldr r3, [r3, #0]
8004ac8: 4a49 ldr r2, [pc, #292] ; (8004bf0 <HAL_ADC_Start+0x16c>)
8004aca: fba2 2303 umull r2, r3, r2, r3
8004ace: 0c9a lsrs r2, r3, #18
8004ad0: 4613 mov r3, r2
8004ad2: 005b lsls r3, r3, #1
8004ad4: 4413 add r3, r2
8004ad6: 60fb str r3, [r7, #12]
while(counter != 0)
8004ad8: e002 b.n 8004ae0 <HAL_ADC_Start+0x5c>
{
counter--;
8004ada: 68fb ldr r3, [r7, #12]
8004adc: 3b01 subs r3, #1
8004ade: 60fb str r3, [r7, #12]
while(counter != 0)
8004ae0: 68fb ldr r3, [r7, #12]
8004ae2: 2b00 cmp r3, #0
8004ae4: d1f9 bne.n 8004ada <HAL_ADC_Start+0x56>
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
8004ae6: 687b ldr r3, [r7, #4]
8004ae8: 681b ldr r3, [r3, #0]
8004aea: 689b ldr r3, [r3, #8]
8004aec: f003 0301 and.w r3, r3, #1
8004af0: 2b01 cmp r3, #1
8004af2: d174 bne.n 8004bde <HAL_ADC_Start+0x15a>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
8004af4: 687b ldr r3, [r7, #4]
8004af6: 6c1a ldr r2, [r3, #64] ; 0x40
8004af8: 4b3e ldr r3, [pc, #248] ; (8004bf4 <HAL_ADC_Start+0x170>)
8004afa: 4013 ands r3, r2
8004afc: f443 7280 orr.w r2, r3, #256 ; 0x100
8004b00: 687b ldr r3, [r7, #4]
8004b02: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8004b04: 687b ldr r3, [r7, #4]
8004b06: 681b ldr r3, [r3, #0]
8004b08: 685b ldr r3, [r3, #4]
8004b0a: f403 6380 and.w r3, r3, #1024 ; 0x400
8004b0e: 2b00 cmp r3, #0
8004b10: d007 beq.n 8004b22 <HAL_ADC_Start+0x9e>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8004b12: 687b ldr r3, [r7, #4]
8004b14: 6c1b ldr r3, [r3, #64] ; 0x40
8004b16: f423 5340 bic.w r3, r3, #12288 ; 0x3000
8004b1a: f443 5280 orr.w r2, r3, #4096 ; 0x1000
8004b1e: 687b ldr r3, [r7, #4]
8004b20: 641a str r2, [r3, #64] ; 0x40
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004b22: 687b ldr r3, [r7, #4]
8004b24: 6c1b ldr r3, [r3, #64] ; 0x40
8004b26: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004b2a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004b2e: d106 bne.n 8004b3e <HAL_ADC_Start+0xba>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8004b30: 687b ldr r3, [r7, #4]
8004b32: 6c5b ldr r3, [r3, #68] ; 0x44
8004b34: f023 0206 bic.w r2, r3, #6
8004b38: 687b ldr r3, [r7, #4]
8004b3a: 645a str r2, [r3, #68] ; 0x44
8004b3c: e002 b.n 8004b44 <HAL_ADC_Start+0xc0>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8004b3e: 687b ldr r3, [r7, #4]
8004b40: 2200 movs r2, #0
8004b42: 645a str r2, [r3, #68] ; 0x44
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8004b44: 687b ldr r3, [r7, #4]
8004b46: 2200 movs r2, #0
8004b48: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
8004b4c: 687b ldr r3, [r7, #4]
8004b4e: 681b ldr r3, [r3, #0]
8004b50: f06f 0222 mvn.w r2, #34 ; 0x22
8004b54: 601a str r2, [r3, #0]
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
8004b56: 4b28 ldr r3, [pc, #160] ; (8004bf8 <HAL_ADC_Start+0x174>)
8004b58: 685b ldr r3, [r3, #4]
8004b5a: f003 031f and.w r3, r3, #31
8004b5e: 2b00 cmp r3, #0
8004b60: d10f bne.n 8004b82 <HAL_ADC_Start+0xfe>
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
8004b62: 687b ldr r3, [r7, #4]
8004b64: 681b ldr r3, [r3, #0]
8004b66: 689b ldr r3, [r3, #8]
8004b68: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004b6c: 2b00 cmp r3, #0
8004b6e: d136 bne.n 8004bde <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004b70: 687b ldr r3, [r7, #4]
8004b72: 681b ldr r3, [r3, #0]
8004b74: 689a ldr r2, [r3, #8]
8004b76: 687b ldr r3, [r7, #4]
8004b78: 681b ldr r3, [r3, #0]
8004b7a: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004b7e: 609a str r2, [r3, #8]
8004b80: e02d b.n 8004bde <HAL_ADC_Start+0x15a>
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8004b82: 687b ldr r3, [r7, #4]
8004b84: 681b ldr r3, [r3, #0]
8004b86: 4a1d ldr r2, [pc, #116] ; (8004bfc <HAL_ADC_Start+0x178>)
8004b88: 4293 cmp r3, r2
8004b8a: d10e bne.n 8004baa <HAL_ADC_Start+0x126>
8004b8c: 687b ldr r3, [r7, #4]
8004b8e: 681b ldr r3, [r3, #0]
8004b90: 689b ldr r3, [r3, #8]
8004b92: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004b96: 2b00 cmp r3, #0
8004b98: d107 bne.n 8004baa <HAL_ADC_Start+0x126>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004b9a: 687b ldr r3, [r7, #4]
8004b9c: 681b ldr r3, [r3, #0]
8004b9e: 689a ldr r2, [r3, #8]
8004ba0: 687b ldr r3, [r7, #4]
8004ba2: 681b ldr r3, [r3, #0]
8004ba4: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004ba8: 609a str r2, [r3, #8]
}
/* if dual mode is selected, ADC3 works independently. */
/* check if the mode selected is not triple */
if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
8004baa: 4b13 ldr r3, [pc, #76] ; (8004bf8 <HAL_ADC_Start+0x174>)
8004bac: 685b ldr r3, [r3, #4]
8004bae: f003 0310 and.w r3, r3, #16
8004bb2: 2b00 cmp r3, #0
8004bb4: d113 bne.n 8004bde <HAL_ADC_Start+0x15a>
{
/* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8004bb6: 687b ldr r3, [r7, #4]
8004bb8: 681b ldr r3, [r3, #0]
8004bba: 4a11 ldr r2, [pc, #68] ; (8004c00 <HAL_ADC_Start+0x17c>)
8004bbc: 4293 cmp r3, r2
8004bbe: d10e bne.n 8004bde <HAL_ADC_Start+0x15a>
8004bc0: 687b ldr r3, [r7, #4]
8004bc2: 681b ldr r3, [r3, #0]
8004bc4: 689b ldr r3, [r3, #8]
8004bc6: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004bca: 2b00 cmp r3, #0
8004bcc: d107 bne.n 8004bde <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
8004bce: 687b ldr r3, [r7, #4]
8004bd0: 681b ldr r3, [r3, #0]
8004bd2: 689a ldr r2, [r3, #8]
8004bd4: 687b ldr r3, [r7, #4]
8004bd6: 681b ldr r3, [r3, #0]
8004bd8: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
8004bdc: 609a str r2, [r3, #8]
}
}
}
/* Return function status */
return HAL_OK;
8004bde: 2300 movs r3, #0
}
8004be0: 4618 mov r0, r3
8004be2: 3714 adds r7, #20
8004be4: 46bd mov sp, r7
8004be6: f85d 7b04 ldr.w r7, [sp], #4
8004bea: 4770 bx lr
8004bec: 20000064 .word 0x20000064
8004bf0: 431bde83 .word 0x431bde83
8004bf4: fffff8fe .word 0xfffff8fe
8004bf8: 40012300 .word 0x40012300
8004bfc: 40012000 .word 0x40012000
8004c00: 40012200 .word 0x40012200
08004c04 <HAL_ADC_PollForConversion>:
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8004c04: b580 push {r7, lr}
8004c06: b084 sub sp, #16
8004c08: af00 add r7, sp, #0
8004c0a: 6078 str r0, [r7, #4]
8004c0c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8004c0e: 2300 movs r3, #0
8004c10: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004c12: 687b ldr r3, [r7, #4]
8004c14: 681b ldr r3, [r3, #0]
8004c16: 689b ldr r3, [r3, #8]
8004c18: f403 6380 and.w r3, r3, #1024 ; 0x400
8004c1c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8004c20: d113 bne.n 8004c4a <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
8004c22: 687b ldr r3, [r7, #4]
8004c24: 681b ldr r3, [r3, #0]
8004c26: 689b ldr r3, [r3, #8]
8004c28: f403 7380 and.w r3, r3, #256 ; 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004c2c: f5b3 7f80 cmp.w r3, #256 ; 0x100
8004c30: d10b bne.n 8004c4a <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8004c32: 687b ldr r3, [r7, #4]
8004c34: 6c1b ldr r3, [r3, #64] ; 0x40
8004c36: f043 0220 orr.w r2, r3, #32
8004c3a: 687b ldr r3, [r7, #4]
8004c3c: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004c3e: 687b ldr r3, [r7, #4]
8004c40: 2200 movs r2, #0
8004c42: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8004c46: 2301 movs r3, #1
8004c48: e05c b.n 8004d04 <HAL_ADC_PollForConversion+0x100>
}
/* Get tick */
tickstart = HAL_GetTick();
8004c4a: f7ff fea9 bl 80049a0 <HAL_GetTick>
8004c4e: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004c50: e01a b.n 8004c88 <HAL_ADC_PollForConversion+0x84>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
8004c52: 683b ldr r3, [r7, #0]
8004c54: f1b3 3fff cmp.w r3, #4294967295
8004c58: d016 beq.n 8004c88 <HAL_ADC_PollForConversion+0x84>
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
8004c5a: 683b ldr r3, [r7, #0]
8004c5c: 2b00 cmp r3, #0
8004c5e: d007 beq.n 8004c70 <HAL_ADC_PollForConversion+0x6c>
8004c60: f7ff fe9e bl 80049a0 <HAL_GetTick>
8004c64: 4602 mov r2, r0
8004c66: 68fb ldr r3, [r7, #12]
8004c68: 1ad3 subs r3, r2, r3
8004c6a: 683a ldr r2, [r7, #0]
8004c6c: 429a cmp r2, r3
8004c6e: d20b bcs.n 8004c88 <HAL_ADC_PollForConversion+0x84>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
8004c70: 687b ldr r3, [r7, #4]
8004c72: 6c1b ldr r3, [r3, #64] ; 0x40
8004c74: f043 0204 orr.w r2, r3, #4
8004c78: 687b ldr r3, [r7, #4]
8004c7a: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004c7c: 687b ldr r3, [r7, #4]
8004c7e: 2200 movs r2, #0
8004c80: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8004c84: 2303 movs r3, #3
8004c86: e03d b.n 8004d04 <HAL_ADC_PollForConversion+0x100>
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8004c88: 687b ldr r3, [r7, #4]
8004c8a: 681b ldr r3, [r3, #0]
8004c8c: 681b ldr r3, [r3, #0]
8004c8e: f003 0302 and.w r3, r3, #2
8004c92: 2b02 cmp r3, #2
8004c94: d1dd bne.n 8004c52 <HAL_ADC_PollForConversion+0x4e>
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8004c96: 687b ldr r3, [r7, #4]
8004c98: 681b ldr r3, [r3, #0]
8004c9a: f06f 0212 mvn.w r2, #18
8004c9e: 601a str r2, [r3, #0]
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8004ca0: 687b ldr r3, [r7, #4]
8004ca2: 6c1b ldr r3, [r3, #64] ; 0x40
8004ca4: f443 7200 orr.w r2, r3, #512 ; 0x200
8004ca8: 687b ldr r3, [r7, #4]
8004caa: 641a str r2, [r3, #64] ; 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004cac: 687b ldr r3, [r7, #4]
8004cae: 681b ldr r3, [r3, #0]
8004cb0: 689b ldr r3, [r3, #8]
8004cb2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004cb6: 2b00 cmp r3, #0
8004cb8: d123 bne.n 8004d02 <HAL_ADC_PollForConversion+0xfe>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 699b ldr r3, [r3, #24]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8004cbe: 2b00 cmp r3, #0
8004cc0: d11f bne.n 8004d02 <HAL_ADC_PollForConversion+0xfe>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004cc2: 687b ldr r3, [r7, #4]
8004cc4: 681b ldr r3, [r3, #0]
8004cc6: 6adb ldr r3, [r3, #44] ; 0x2c
8004cc8: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
8004ccc: 2b00 cmp r3, #0
8004cce: d006 beq.n 8004cde <HAL_ADC_PollForConversion+0xda>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
8004cd0: 687b ldr r3, [r7, #4]
8004cd2: 681b ldr r3, [r3, #0]
8004cd4: 689b ldr r3, [r3, #8]
8004cd6: f403 6380 and.w r3, r3, #1024 ; 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004cda: 2b00 cmp r3, #0
8004cdc: d111 bne.n 8004d02 <HAL_ADC_PollForConversion+0xfe>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8004cde: 687b ldr r3, [r7, #4]
8004ce0: 6c1b ldr r3, [r3, #64] ; 0x40
8004ce2: f423 7280 bic.w r2, r3, #256 ; 0x100
8004ce6: 687b ldr r3, [r7, #4]
8004ce8: 641a str r2, [r3, #64] ; 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004cea: 687b ldr r3, [r7, #4]
8004cec: 6c1b ldr r3, [r3, #64] ; 0x40
8004cee: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004cf2: 2b00 cmp r3, #0
8004cf4: d105 bne.n 8004d02 <HAL_ADC_PollForConversion+0xfe>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8004cf6: 687b ldr r3, [r7, #4]
8004cf8: 6c1b ldr r3, [r3, #64] ; 0x40
8004cfa: f043 0201 orr.w r2, r3, #1
8004cfe: 687b ldr r3, [r7, #4]
8004d00: 641a str r2, [r3, #64] ; 0x40
}
}
/* Return ADC state */
return HAL_OK;
8004d02: 2300 movs r3, #0
}
8004d04: 4618 mov r0, r3
8004d06: 3710 adds r7, #16
8004d08: 46bd mov sp, r7
8004d0a: bd80 pop {r7, pc}
08004d0c <HAL_ADC_GetValue>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
8004d0c: b480 push {r7}
8004d0e: b083 sub sp, #12
8004d10: af00 add r7, sp, #0
8004d12: 6078 str r0, [r7, #4]
/* Return the selected ADC converted value */
return hadc->Instance->DR;
8004d14: 687b ldr r3, [r7, #4]
8004d16: 681b ldr r3, [r3, #0]
8004d18: 6cdb ldr r3, [r3, #76] ; 0x4c
}
8004d1a: 4618 mov r0, r3
8004d1c: 370c adds r7, #12
8004d1e: 46bd mov sp, r7
8004d20: f85d 7b04 ldr.w r7, [sp], #4
8004d24: 4770 bx lr
...
08004d28 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8004d28: b480 push {r7}
8004d2a: b085 sub sp, #20
8004d2c: af00 add r7, sp, #0
8004d2e: 6078 str r0, [r7, #4]
8004d30: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0;
8004d32: 2300 movs r3, #0
8004d34: 60fb str r3, [r7, #12]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8004d36: 687b ldr r3, [r7, #4]
8004d38: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8004d3c: 2b01 cmp r3, #1
8004d3e: d101 bne.n 8004d44 <HAL_ADC_ConfigChannel+0x1c>
8004d40: 2302 movs r3, #2
8004d42: e12a b.n 8004f9a <HAL_ADC_ConfigChannel+0x272>
8004d44: 687b ldr r3, [r7, #4]
8004d46: 2201 movs r2, #1
8004d48: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
8004d4c: 683b ldr r3, [r7, #0]
8004d4e: 681b ldr r3, [r3, #0]
8004d50: 2b09 cmp r3, #9
8004d52: d93a bls.n 8004dca <HAL_ADC_ConfigChannel+0xa2>
8004d54: 683b ldr r3, [r7, #0]
8004d56: 681b ldr r3, [r3, #0]
8004d58: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004d5c: d035 beq.n 8004dca <HAL_ADC_ConfigChannel+0xa2>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
8004d5e: 687b ldr r3, [r7, #4]
8004d60: 681b ldr r3, [r3, #0]
8004d62: 68d9 ldr r1, [r3, #12]
8004d64: 683b ldr r3, [r7, #0]
8004d66: 681b ldr r3, [r3, #0]
8004d68: b29b uxth r3, r3
8004d6a: 461a mov r2, r3
8004d6c: 4613 mov r3, r2
8004d6e: 005b lsls r3, r3, #1
8004d70: 4413 add r3, r2
8004d72: 3b1e subs r3, #30
8004d74: 2207 movs r2, #7
8004d76: fa02 f303 lsl.w r3, r2, r3
8004d7a: 43da mvns r2, r3
8004d7c: 687b ldr r3, [r7, #4]
8004d7e: 681b ldr r3, [r3, #0]
8004d80: 400a ands r2, r1
8004d82: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004d84: 683b ldr r3, [r7, #0]
8004d86: 681b ldr r3, [r3, #0]
8004d88: 4a87 ldr r2, [pc, #540] ; (8004fa8 <HAL_ADC_ConfigChannel+0x280>)
8004d8a: 4293 cmp r3, r2
8004d8c: d10a bne.n 8004da4 <HAL_ADC_ConfigChannel+0x7c>
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
8004d8e: 687b ldr r3, [r7, #4]
8004d90: 681b ldr r3, [r3, #0]
8004d92: 68d9 ldr r1, [r3, #12]
8004d94: 683b ldr r3, [r7, #0]
8004d96: 689b ldr r3, [r3, #8]
8004d98: 061a lsls r2, r3, #24
8004d9a: 687b ldr r3, [r7, #4]
8004d9c: 681b ldr r3, [r3, #0]
8004d9e: 430a orrs r2, r1
8004da0: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004da2: e035 b.n 8004e10 <HAL_ADC_ConfigChannel+0xe8>
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
8004da4: 687b ldr r3, [r7, #4]
8004da6: 681b ldr r3, [r3, #0]
8004da8: 68d9 ldr r1, [r3, #12]
8004daa: 683b ldr r3, [r7, #0]
8004dac: 689a ldr r2, [r3, #8]
8004dae: 683b ldr r3, [r7, #0]
8004db0: 681b ldr r3, [r3, #0]
8004db2: b29b uxth r3, r3
8004db4: 4618 mov r0, r3
8004db6: 4603 mov r3, r0
8004db8: 005b lsls r3, r3, #1
8004dba: 4403 add r3, r0
8004dbc: 3b1e subs r3, #30
8004dbe: 409a lsls r2, r3
8004dc0: 687b ldr r3, [r7, #4]
8004dc2: 681b ldr r3, [r3, #0]
8004dc4: 430a orrs r2, r1
8004dc6: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004dc8: e022 b.n 8004e10 <HAL_ADC_ConfigChannel+0xe8>
}
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
8004dca: 687b ldr r3, [r7, #4]
8004dcc: 681b ldr r3, [r3, #0]
8004dce: 6919 ldr r1, [r3, #16]
8004dd0: 683b ldr r3, [r7, #0]
8004dd2: 681b ldr r3, [r3, #0]
8004dd4: b29b uxth r3, r3
8004dd6: 461a mov r2, r3
8004dd8: 4613 mov r3, r2
8004dda: 005b lsls r3, r3, #1
8004ddc: 4413 add r3, r2
8004dde: 2207 movs r2, #7
8004de0: fa02 f303 lsl.w r3, r2, r3
8004de4: 43da mvns r2, r3
8004de6: 687b ldr r3, [r7, #4]
8004de8: 681b ldr r3, [r3, #0]
8004dea: 400a ands r2, r1
8004dec: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
8004dee: 687b ldr r3, [r7, #4]
8004df0: 681b ldr r3, [r3, #0]
8004df2: 6919 ldr r1, [r3, #16]
8004df4: 683b ldr r3, [r7, #0]
8004df6: 689a ldr r2, [r3, #8]
8004df8: 683b ldr r3, [r7, #0]
8004dfa: 681b ldr r3, [r3, #0]
8004dfc: b29b uxth r3, r3
8004dfe: 4618 mov r0, r3
8004e00: 4603 mov r3, r0
8004e02: 005b lsls r3, r3, #1
8004e04: 4403 add r3, r0
8004e06: 409a lsls r2, r3
8004e08: 687b ldr r3, [r7, #4]
8004e0a: 681b ldr r3, [r3, #0]
8004e0c: 430a orrs r2, r1
8004e0e: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
8004e10: 683b ldr r3, [r7, #0]
8004e12: 685b ldr r3, [r3, #4]
8004e14: 2b06 cmp r3, #6
8004e16: d824 bhi.n 8004e62 <HAL_ADC_ConfigChannel+0x13a>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8004e18: 687b ldr r3, [r7, #4]
8004e1a: 681b ldr r3, [r3, #0]
8004e1c: 6b59 ldr r1, [r3, #52] ; 0x34
8004e1e: 683b ldr r3, [r7, #0]
8004e20: 685a ldr r2, [r3, #4]
8004e22: 4613 mov r3, r2
8004e24: 009b lsls r3, r3, #2
8004e26: 4413 add r3, r2
8004e28: 3b05 subs r3, #5
8004e2a: 221f movs r2, #31
8004e2c: fa02 f303 lsl.w r3, r2, r3
8004e30: 43da mvns r2, r3
8004e32: 687b ldr r3, [r7, #4]
8004e34: 681b ldr r3, [r3, #0]
8004e36: 400a ands r2, r1
8004e38: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
8004e3a: 687b ldr r3, [r7, #4]
8004e3c: 681b ldr r3, [r3, #0]
8004e3e: 6b59 ldr r1, [r3, #52] ; 0x34
8004e40: 683b ldr r3, [r7, #0]
8004e42: 681b ldr r3, [r3, #0]
8004e44: b29b uxth r3, r3
8004e46: 4618 mov r0, r3
8004e48: 683b ldr r3, [r7, #0]
8004e4a: 685a ldr r2, [r3, #4]
8004e4c: 4613 mov r3, r2
8004e4e: 009b lsls r3, r3, #2
8004e50: 4413 add r3, r2
8004e52: 3b05 subs r3, #5
8004e54: fa00 f203 lsl.w r2, r0, r3
8004e58: 687b ldr r3, [r7, #4]
8004e5a: 681b ldr r3, [r3, #0]
8004e5c: 430a orrs r2, r1
8004e5e: 635a str r2, [r3, #52] ; 0x34
8004e60: e04c b.n 8004efc <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
8004e62: 683b ldr r3, [r7, #0]
8004e64: 685b ldr r3, [r3, #4]
8004e66: 2b0c cmp r3, #12
8004e68: d824 bhi.n 8004eb4 <HAL_ADC_ConfigChannel+0x18c>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
8004e6a: 687b ldr r3, [r7, #4]
8004e6c: 681b ldr r3, [r3, #0]
8004e6e: 6b19 ldr r1, [r3, #48] ; 0x30
8004e70: 683b ldr r3, [r7, #0]
8004e72: 685a ldr r2, [r3, #4]
8004e74: 4613 mov r3, r2
8004e76: 009b lsls r3, r3, #2
8004e78: 4413 add r3, r2
8004e7a: 3b23 subs r3, #35 ; 0x23
8004e7c: 221f movs r2, #31
8004e7e: fa02 f303 lsl.w r3, r2, r3
8004e82: 43da mvns r2, r3
8004e84: 687b ldr r3, [r7, #4]
8004e86: 681b ldr r3, [r3, #0]
8004e88: 400a ands r2, r1
8004e8a: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
8004e8c: 687b ldr r3, [r7, #4]
8004e8e: 681b ldr r3, [r3, #0]
8004e90: 6b19 ldr r1, [r3, #48] ; 0x30
8004e92: 683b ldr r3, [r7, #0]
8004e94: 681b ldr r3, [r3, #0]
8004e96: b29b uxth r3, r3
8004e98: 4618 mov r0, r3
8004e9a: 683b ldr r3, [r7, #0]
8004e9c: 685a ldr r2, [r3, #4]
8004e9e: 4613 mov r3, r2
8004ea0: 009b lsls r3, r3, #2
8004ea2: 4413 add r3, r2
8004ea4: 3b23 subs r3, #35 ; 0x23
8004ea6: fa00 f203 lsl.w r2, r0, r3
8004eaa: 687b ldr r3, [r7, #4]
8004eac: 681b ldr r3, [r3, #0]
8004eae: 430a orrs r2, r1
8004eb0: 631a str r2, [r3, #48] ; 0x30
8004eb2: e023 b.n 8004efc <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
8004eb4: 687b ldr r3, [r7, #4]
8004eb6: 681b ldr r3, [r3, #0]
8004eb8: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004eba: 683b ldr r3, [r7, #0]
8004ebc: 685a ldr r2, [r3, #4]
8004ebe: 4613 mov r3, r2
8004ec0: 009b lsls r3, r3, #2
8004ec2: 4413 add r3, r2
8004ec4: 3b41 subs r3, #65 ; 0x41
8004ec6: 221f movs r2, #31
8004ec8: fa02 f303 lsl.w r3, r2, r3
8004ecc: 43da mvns r2, r3
8004ece: 687b ldr r3, [r7, #4]
8004ed0: 681b ldr r3, [r3, #0]
8004ed2: 400a ands r2, r1
8004ed4: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8004ed6: 687b ldr r3, [r7, #4]
8004ed8: 681b ldr r3, [r3, #0]
8004eda: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004edc: 683b ldr r3, [r7, #0]
8004ede: 681b ldr r3, [r3, #0]
8004ee0: b29b uxth r3, r3
8004ee2: 4618 mov r0, r3
8004ee4: 683b ldr r3, [r7, #0]
8004ee6: 685a ldr r2, [r3, #4]
8004ee8: 4613 mov r3, r2
8004eea: 009b lsls r3, r3, #2
8004eec: 4413 add r3, r2
8004eee: 3b41 subs r3, #65 ; 0x41
8004ef0: fa00 f203 lsl.w r2, r0, r3
8004ef4: 687b ldr r3, [r7, #4]
8004ef6: 681b ldr r3, [r3, #0]
8004ef8: 430a orrs r2, r1
8004efa: 62da str r2, [r3, #44] ; 0x2c
}
/* if no internal channel selected */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
8004efc: 687b ldr r3, [r7, #4]
8004efe: 681b ldr r3, [r3, #0]
8004f00: 4a2a ldr r2, [pc, #168] ; (8004fac <HAL_ADC_ConfigChannel+0x284>)
8004f02: 4293 cmp r3, r2
8004f04: d10a bne.n 8004f1c <HAL_ADC_ConfigChannel+0x1f4>
8004f06: 683b ldr r3, [r7, #0]
8004f08: 681b ldr r3, [r3, #0]
8004f0a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004f0e: d105 bne.n 8004f1c <HAL_ADC_ConfigChannel+0x1f4>
{
/* Disable the VBAT & TSVREFE channel*/
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
8004f10: 4b27 ldr r3, [pc, #156] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f12: 685b ldr r3, [r3, #4]
8004f14: 4a26 ldr r2, [pc, #152] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f16: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000
8004f1a: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
8004f1c: 687b ldr r3, [r7, #4]
8004f1e: 681b ldr r3, [r3, #0]
8004f20: 4a22 ldr r2, [pc, #136] ; (8004fac <HAL_ADC_ConfigChannel+0x284>)
8004f22: 4293 cmp r3, r2
8004f24: d109 bne.n 8004f3a <HAL_ADC_ConfigChannel+0x212>
8004f26: 683b ldr r3, [r7, #0]
8004f28: 681b ldr r3, [r3, #0]
8004f2a: 2b12 cmp r3, #18
8004f2c: d105 bne.n 8004f3a <HAL_ADC_ConfigChannel+0x212>
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
8004f2e: 4b20 ldr r3, [pc, #128] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f30: 685b ldr r3, [r3, #4]
8004f32: 4a1f ldr r2, [pc, #124] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f34: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8004f38: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8004f3a: 687b ldr r3, [r7, #4]
8004f3c: 681b ldr r3, [r3, #0]
8004f3e: 4a1b ldr r2, [pc, #108] ; (8004fac <HAL_ADC_ConfigChannel+0x284>)
8004f40: 4293 cmp r3, r2
8004f42: d125 bne.n 8004f90 <HAL_ADC_ConfigChannel+0x268>
8004f44: 683b ldr r3, [r7, #0]
8004f46: 681b ldr r3, [r3, #0]
8004f48: 4a17 ldr r2, [pc, #92] ; (8004fa8 <HAL_ADC_ConfigChannel+0x280>)
8004f4a: 4293 cmp r3, r2
8004f4c: d003 beq.n 8004f56 <HAL_ADC_ConfigChannel+0x22e>
8004f4e: 683b ldr r3, [r7, #0]
8004f50: 681b ldr r3, [r3, #0]
8004f52: 2b11 cmp r3, #17
8004f54: d11c bne.n 8004f90 <HAL_ADC_ConfigChannel+0x268>
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
8004f56: 4b16 ldr r3, [pc, #88] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f58: 685b ldr r3, [r3, #4]
8004f5a: 4a15 ldr r2, [pc, #84] ; (8004fb0 <HAL_ADC_ConfigChannel+0x288>)
8004f5c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8004f60: 6053 str r3, [r2, #4]
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004f62: 683b ldr r3, [r7, #0]
8004f64: 681b ldr r3, [r3, #0]
8004f66: 4a10 ldr r2, [pc, #64] ; (8004fa8 <HAL_ADC_ConfigChannel+0x280>)
8004f68: 4293 cmp r3, r2
8004f6a: d111 bne.n 8004f90 <HAL_ADC_ConfigChannel+0x268>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
8004f6c: 4b11 ldr r3, [pc, #68] ; (8004fb4 <HAL_ADC_ConfigChannel+0x28c>)
8004f6e: 681b ldr r3, [r3, #0]
8004f70: 4a11 ldr r2, [pc, #68] ; (8004fb8 <HAL_ADC_ConfigChannel+0x290>)
8004f72: fba2 2303 umull r2, r3, r2, r3
8004f76: 0c9a lsrs r2, r3, #18
8004f78: 4613 mov r3, r2
8004f7a: 009b lsls r3, r3, #2
8004f7c: 4413 add r3, r2
8004f7e: 005b lsls r3, r3, #1
8004f80: 60fb str r3, [r7, #12]
while(counter != 0)
8004f82: e002 b.n 8004f8a <HAL_ADC_ConfigChannel+0x262>
{
counter--;
8004f84: 68fb ldr r3, [r7, #12]
8004f86: 3b01 subs r3, #1
8004f88: 60fb str r3, [r7, #12]
while(counter != 0)
8004f8a: 68fb ldr r3, [r7, #12]
8004f8c: 2b00 cmp r3, #0
8004f8e: d1f9 bne.n 8004f84 <HAL_ADC_ConfigChannel+0x25c>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004f90: 687b ldr r3, [r7, #4]
8004f92: 2200 movs r2, #0
8004f94: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8004f98: 2300 movs r3, #0
}
8004f9a: 4618 mov r0, r3
8004f9c: 3714 adds r7, #20
8004f9e: 46bd mov sp, r7
8004fa0: f85d 7b04 ldr.w r7, [sp], #4
8004fa4: 4770 bx lr
8004fa6: bf00 nop
8004fa8: 10000012 .word 0x10000012
8004fac: 40012000 .word 0x40012000
8004fb0: 40012300 .word 0x40012300
8004fb4: 20000064 .word 0x20000064
8004fb8: 431bde83 .word 0x431bde83
08004fbc <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
8004fbc: b480 push {r7}
8004fbe: b083 sub sp, #12
8004fc0: af00 add r7, sp, #0
8004fc2: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
8004fc4: 4b78 ldr r3, [pc, #480] ; (80051a8 <ADC_Init+0x1ec>)
8004fc6: 685b ldr r3, [r3, #4]
8004fc8: 4a77 ldr r2, [pc, #476] ; (80051a8 <ADC_Init+0x1ec>)
8004fca: f423 3340 bic.w r3, r3, #196608 ; 0x30000
8004fce: 6053 str r3, [r2, #4]
ADC->CCR |= hadc->Init.ClockPrescaler;
8004fd0: 4b75 ldr r3, [pc, #468] ; (80051a8 <ADC_Init+0x1ec>)
8004fd2: 685a ldr r2, [r3, #4]
8004fd4: 687b ldr r3, [r7, #4]
8004fd6: 685b ldr r3, [r3, #4]
8004fd8: 4973 ldr r1, [pc, #460] ; (80051a8 <ADC_Init+0x1ec>)
8004fda: 4313 orrs r3, r2
8004fdc: 604b str r3, [r1, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
8004fde: 687b ldr r3, [r7, #4]
8004fe0: 681b ldr r3, [r3, #0]
8004fe2: 685a ldr r2, [r3, #4]
8004fe4: 687b ldr r3, [r7, #4]
8004fe6: 681b ldr r3, [r3, #0]
8004fe8: f422 7280 bic.w r2, r2, #256 ; 0x100
8004fec: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
8004fee: 687b ldr r3, [r7, #4]
8004ff0: 681b ldr r3, [r3, #0]
8004ff2: 6859 ldr r1, [r3, #4]
8004ff4: 687b ldr r3, [r7, #4]
8004ff6: 691b ldr r3, [r3, #16]
8004ff8: 021a lsls r2, r3, #8
8004ffa: 687b ldr r3, [r7, #4]
8004ffc: 681b ldr r3, [r3, #0]
8004ffe: 430a orrs r2, r1
8005000: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
8005002: 687b ldr r3, [r7, #4]
8005004: 681b ldr r3, [r3, #0]
8005006: 685a ldr r2, [r3, #4]
8005008: 687b ldr r3, [r7, #4]
800500a: 681b ldr r3, [r3, #0]
800500c: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
8005010: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
8005012: 687b ldr r3, [r7, #4]
8005014: 681b ldr r3, [r3, #0]
8005016: 6859 ldr r1, [r3, #4]
8005018: 687b ldr r3, [r7, #4]
800501a: 689a ldr r2, [r3, #8]
800501c: 687b ldr r3, [r7, #4]
800501e: 681b ldr r3, [r3, #0]
8005020: 430a orrs r2, r1
8005022: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
8005024: 687b ldr r3, [r7, #4]
8005026: 681b ldr r3, [r3, #0]
8005028: 689a ldr r2, [r3, #8]
800502a: 687b ldr r3, [r7, #4]
800502c: 681b ldr r3, [r3, #0]
800502e: f422 6200 bic.w r2, r2, #2048 ; 0x800
8005032: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
8005034: 687b ldr r3, [r7, #4]
8005036: 681b ldr r3, [r3, #0]
8005038: 6899 ldr r1, [r3, #8]
800503a: 687b ldr r3, [r7, #4]
800503c: 68da ldr r2, [r3, #12]
800503e: 687b ldr r3, [r7, #4]
8005040: 681b ldr r3, [r3, #0]
8005042: 430a orrs r2, r1
8005044: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8005046: 687b ldr r3, [r7, #4]
8005048: 6a9b ldr r3, [r3, #40] ; 0x28
800504a: 4a58 ldr r2, [pc, #352] ; (80051ac <ADC_Init+0x1f0>)
800504c: 4293 cmp r3, r2
800504e: d022 beq.n 8005096 <ADC_Init+0xda>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8005050: 687b ldr r3, [r7, #4]
8005052: 681b ldr r3, [r3, #0]
8005054: 689a ldr r2, [r3, #8]
8005056: 687b ldr r3, [r7, #4]
8005058: 681b ldr r3, [r3, #0]
800505a: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
800505e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
8005060: 687b ldr r3, [r7, #4]
8005062: 681b ldr r3, [r3, #0]
8005064: 6899 ldr r1, [r3, #8]
8005066: 687b ldr r3, [r7, #4]
8005068: 6a9a ldr r2, [r3, #40] ; 0x28
800506a: 687b ldr r3, [r7, #4]
800506c: 681b ldr r3, [r3, #0]
800506e: 430a orrs r2, r1
8005070: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8005072: 687b ldr r3, [r7, #4]
8005074: 681b ldr r3, [r3, #0]
8005076: 689a ldr r2, [r3, #8]
8005078: 687b ldr r3, [r7, #4]
800507a: 681b ldr r3, [r3, #0]
800507c: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8005080: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
8005082: 687b ldr r3, [r7, #4]
8005084: 681b ldr r3, [r3, #0]
8005086: 6899 ldr r1, [r3, #8]
8005088: 687b ldr r3, [r7, #4]
800508a: 6ada ldr r2, [r3, #44] ; 0x2c
800508c: 687b ldr r3, [r7, #4]
800508e: 681b ldr r3, [r3, #0]
8005090: 430a orrs r2, r1
8005092: 609a str r2, [r3, #8]
8005094: e00f b.n 80050b6 <ADC_Init+0xfa>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8005096: 687b ldr r3, [r7, #4]
8005098: 681b ldr r3, [r3, #0]
800509a: 689a ldr r2, [r3, #8]
800509c: 687b ldr r3, [r7, #4]
800509e: 681b ldr r3, [r3, #0]
80050a0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80050a4: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
80050a6: 687b ldr r3, [r7, #4]
80050a8: 681b ldr r3, [r3, #0]
80050aa: 689a ldr r2, [r3, #8]
80050ac: 687b ldr r3, [r7, #4]
80050ae: 681b ldr r3, [r3, #0]
80050b0: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
80050b4: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
80050b6: 687b ldr r3, [r7, #4]
80050b8: 681b ldr r3, [r3, #0]
80050ba: 689a ldr r2, [r3, #8]
80050bc: 687b ldr r3, [r7, #4]
80050be: 681b ldr r3, [r3, #0]
80050c0: f022 0202 bic.w r2, r2, #2
80050c4: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
80050c6: 687b ldr r3, [r7, #4]
80050c8: 681b ldr r3, [r3, #0]
80050ca: 6899 ldr r1, [r3, #8]
80050cc: 687b ldr r3, [r7, #4]
80050ce: 699b ldr r3, [r3, #24]
80050d0: 005a lsls r2, r3, #1
80050d2: 687b ldr r3, [r7, #4]
80050d4: 681b ldr r3, [r3, #0]
80050d6: 430a orrs r2, r1
80050d8: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
80050da: 687b ldr r3, [r7, #4]
80050dc: f893 3020 ldrb.w r3, [r3, #32]
80050e0: 2b00 cmp r3, #0
80050e2: d01b beq.n 800511c <ADC_Init+0x160>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
80050e4: 687b ldr r3, [r7, #4]
80050e6: 681b ldr r3, [r3, #0]
80050e8: 685a ldr r2, [r3, #4]
80050ea: 687b ldr r3, [r7, #4]
80050ec: 681b ldr r3, [r3, #0]
80050ee: f442 6200 orr.w r2, r2, #2048 ; 0x800
80050f2: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
80050f4: 687b ldr r3, [r7, #4]
80050f6: 681b ldr r3, [r3, #0]
80050f8: 685a ldr r2, [r3, #4]
80050fa: 687b ldr r3, [r7, #4]
80050fc: 681b ldr r3, [r3, #0]
80050fe: f422 4260 bic.w r2, r2, #57344 ; 0xe000
8005102: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
8005104: 687b ldr r3, [r7, #4]
8005106: 681b ldr r3, [r3, #0]
8005108: 6859 ldr r1, [r3, #4]
800510a: 687b ldr r3, [r7, #4]
800510c: 6a5b ldr r3, [r3, #36] ; 0x24
800510e: 3b01 subs r3, #1
8005110: 035a lsls r2, r3, #13
8005112: 687b ldr r3, [r7, #4]
8005114: 681b ldr r3, [r3, #0]
8005116: 430a orrs r2, r1
8005118: 605a str r2, [r3, #4]
800511a: e007 b.n 800512c <ADC_Init+0x170>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
800511c: 687b ldr r3, [r7, #4]
800511e: 681b ldr r3, [r3, #0]
8005120: 685a ldr r2, [r3, #4]
8005122: 687b ldr r3, [r7, #4]
8005124: 681b ldr r3, [r3, #0]
8005126: f422 6200 bic.w r2, r2, #2048 ; 0x800
800512a: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
800512c: 687b ldr r3, [r7, #4]
800512e: 681b ldr r3, [r3, #0]
8005130: 6ada ldr r2, [r3, #44] ; 0x2c
8005132: 687b ldr r3, [r7, #4]
8005134: 681b ldr r3, [r3, #0]
8005136: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
800513a: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
800513c: 687b ldr r3, [r7, #4]
800513e: 681b ldr r3, [r3, #0]
8005140: 6ad9 ldr r1, [r3, #44] ; 0x2c
8005142: 687b ldr r3, [r7, #4]
8005144: 69db ldr r3, [r3, #28]
8005146: 3b01 subs r3, #1
8005148: 051a lsls r2, r3, #20
800514a: 687b ldr r3, [r7, #4]
800514c: 681b ldr r3, [r3, #0]
800514e: 430a orrs r2, r1
8005150: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
8005152: 687b ldr r3, [r7, #4]
8005154: 681b ldr r3, [r3, #0]
8005156: 689a ldr r2, [r3, #8]
8005158: 687b ldr r3, [r7, #4]
800515a: 681b ldr r3, [r3, #0]
800515c: f422 7200 bic.w r2, r2, #512 ; 0x200
8005160: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
8005162: 687b ldr r3, [r7, #4]
8005164: 681b ldr r3, [r3, #0]
8005166: 6899 ldr r1, [r3, #8]
8005168: 687b ldr r3, [r7, #4]
800516a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
800516e: 025a lsls r2, r3, #9
8005170: 687b ldr r3, [r7, #4]
8005172: 681b ldr r3, [r3, #0]
8005174: 430a orrs r2, r1
8005176: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8005178: 687b ldr r3, [r7, #4]
800517a: 681b ldr r3, [r3, #0]
800517c: 689a ldr r2, [r3, #8]
800517e: 687b ldr r3, [r7, #4]
8005180: 681b ldr r3, [r3, #0]
8005182: f422 6280 bic.w r2, r2, #1024 ; 0x400
8005186: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8005188: 687b ldr r3, [r7, #4]
800518a: 681b ldr r3, [r3, #0]
800518c: 6899 ldr r1, [r3, #8]
800518e: 687b ldr r3, [r7, #4]
8005190: 695b ldr r3, [r3, #20]
8005192: 029a lsls r2, r3, #10
8005194: 687b ldr r3, [r7, #4]
8005196: 681b ldr r3, [r3, #0]
8005198: 430a orrs r2, r1
800519a: 609a str r2, [r3, #8]
}
800519c: bf00 nop
800519e: 370c adds r7, #12
80051a0: 46bd mov sp, r7
80051a2: f85d 7b04 ldr.w r7, [sp], #4
80051a6: 4770 bx lr
80051a8: 40012300 .word 0x40012300
80051ac: 0f000001 .word 0x0f000001
080051b0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80051b0: b480 push {r7}
80051b2: b085 sub sp, #20
80051b4: af00 add r7, sp, #0
80051b6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80051b8: 687b ldr r3, [r7, #4]
80051ba: f003 0307 and.w r3, r3, #7
80051be: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80051c0: 4b0b ldr r3, [pc, #44] ; (80051f0 <__NVIC_SetPriorityGrouping+0x40>)
80051c2: 68db ldr r3, [r3, #12]
80051c4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80051c6: 68ba ldr r2, [r7, #8]
80051c8: f64f 03ff movw r3, #63743 ; 0xf8ff
80051cc: 4013 ands r3, r2
80051ce: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80051d0: 68fb ldr r3, [r7, #12]
80051d2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80051d4: 68bb ldr r3, [r7, #8]
80051d6: 431a orrs r2, r3
reg_value = (reg_value |
80051d8: 4b06 ldr r3, [pc, #24] ; (80051f4 <__NVIC_SetPriorityGrouping+0x44>)
80051da: 4313 orrs r3, r2
80051dc: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80051de: 4a04 ldr r2, [pc, #16] ; (80051f0 <__NVIC_SetPriorityGrouping+0x40>)
80051e0: 68bb ldr r3, [r7, #8]
80051e2: 60d3 str r3, [r2, #12]
}
80051e4: bf00 nop
80051e6: 3714 adds r7, #20
80051e8: 46bd mov sp, r7
80051ea: f85d 7b04 ldr.w r7, [sp], #4
80051ee: 4770 bx lr
80051f0: e000ed00 .word 0xe000ed00
80051f4: 05fa0000 .word 0x05fa0000
080051f8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80051f8: b480 push {r7}
80051fa: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80051fc: 4b04 ldr r3, [pc, #16] ; (8005210 <__NVIC_GetPriorityGrouping+0x18>)
80051fe: 68db ldr r3, [r3, #12]
8005200: 0a1b lsrs r3, r3, #8
8005202: f003 0307 and.w r3, r3, #7
}
8005206: 4618 mov r0, r3
8005208: 46bd mov sp, r7
800520a: f85d 7b04 ldr.w r7, [sp], #4
800520e: 4770 bx lr
8005210: e000ed00 .word 0xe000ed00
08005214 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8005214: b480 push {r7}
8005216: b083 sub sp, #12
8005218: af00 add r7, sp, #0
800521a: 4603 mov r3, r0
800521c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800521e: f997 3007 ldrsb.w r3, [r7, #7]
8005222: 2b00 cmp r3, #0
8005224: db0b blt.n 800523e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8005226: 79fb ldrb r3, [r7, #7]
8005228: f003 021f and.w r2, r3, #31
800522c: 4907 ldr r1, [pc, #28] ; (800524c <__NVIC_EnableIRQ+0x38>)
800522e: f997 3007 ldrsb.w r3, [r7, #7]
8005232: 095b lsrs r3, r3, #5
8005234: 2001 movs r0, #1
8005236: fa00 f202 lsl.w r2, r0, r2
800523a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
800523e: bf00 nop
8005240: 370c adds r7, #12
8005242: 46bd mov sp, r7
8005244: f85d 7b04 ldr.w r7, [sp], #4
8005248: 4770 bx lr
800524a: bf00 nop
800524c: e000e100 .word 0xe000e100
08005250 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8005250: b480 push {r7}
8005252: b083 sub sp, #12
8005254: af00 add r7, sp, #0
8005256: 4603 mov r3, r0
8005258: 6039 str r1, [r7, #0]
800525a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800525c: f997 3007 ldrsb.w r3, [r7, #7]
8005260: 2b00 cmp r3, #0
8005262: db0a blt.n 800527a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8005264: 683b ldr r3, [r7, #0]
8005266: b2da uxtb r2, r3
8005268: 490c ldr r1, [pc, #48] ; (800529c <__NVIC_SetPriority+0x4c>)
800526a: f997 3007 ldrsb.w r3, [r7, #7]
800526e: 0112 lsls r2, r2, #4
8005270: b2d2 uxtb r2, r2
8005272: 440b add r3, r1
8005274: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8005278: e00a b.n 8005290 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800527a: 683b ldr r3, [r7, #0]
800527c: b2da uxtb r2, r3
800527e: 4908 ldr r1, [pc, #32] ; (80052a0 <__NVIC_SetPriority+0x50>)
8005280: 79fb ldrb r3, [r7, #7]
8005282: f003 030f and.w r3, r3, #15
8005286: 3b04 subs r3, #4
8005288: 0112 lsls r2, r2, #4
800528a: b2d2 uxtb r2, r2
800528c: 440b add r3, r1
800528e: 761a strb r2, [r3, #24]
}
8005290: bf00 nop
8005292: 370c adds r7, #12
8005294: 46bd mov sp, r7
8005296: f85d 7b04 ldr.w r7, [sp], #4
800529a: 4770 bx lr
800529c: e000e100 .word 0xe000e100
80052a0: e000ed00 .word 0xe000ed00
080052a4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80052a4: b480 push {r7}
80052a6: b089 sub sp, #36 ; 0x24
80052a8: af00 add r7, sp, #0
80052aa: 60f8 str r0, [r7, #12]
80052ac: 60b9 str r1, [r7, #8]
80052ae: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80052b0: 68fb ldr r3, [r7, #12]
80052b2: f003 0307 and.w r3, r3, #7
80052b6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80052b8: 69fb ldr r3, [r7, #28]
80052ba: f1c3 0307 rsb r3, r3, #7
80052be: 2b04 cmp r3, #4
80052c0: bf28 it cs
80052c2: 2304 movcs r3, #4
80052c4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80052c6: 69fb ldr r3, [r7, #28]
80052c8: 3304 adds r3, #4
80052ca: 2b06 cmp r3, #6
80052cc: d902 bls.n 80052d4 <NVIC_EncodePriority+0x30>
80052ce: 69fb ldr r3, [r7, #28]
80052d0: 3b03 subs r3, #3
80052d2: e000 b.n 80052d6 <NVIC_EncodePriority+0x32>
80052d4: 2300 movs r3, #0
80052d6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80052d8: f04f 32ff mov.w r2, #4294967295
80052dc: 69bb ldr r3, [r7, #24]
80052de: fa02 f303 lsl.w r3, r2, r3
80052e2: 43da mvns r2, r3
80052e4: 68bb ldr r3, [r7, #8]
80052e6: 401a ands r2, r3
80052e8: 697b ldr r3, [r7, #20]
80052ea: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80052ec: f04f 31ff mov.w r1, #4294967295
80052f0: 697b ldr r3, [r7, #20]
80052f2: fa01 f303 lsl.w r3, r1, r3
80052f6: 43d9 mvns r1, r3
80052f8: 687b ldr r3, [r7, #4]
80052fa: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80052fc: 4313 orrs r3, r2
);
}
80052fe: 4618 mov r0, r3
8005300: 3724 adds r7, #36 ; 0x24
8005302: 46bd mov sp, r7
8005304: f85d 7b04 ldr.w r7, [sp], #4
8005308: 4770 bx lr
0800530a <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
800530a: b580 push {r7, lr}
800530c: b082 sub sp, #8
800530e: af00 add r7, sp, #0
8005310: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8005312: 6878 ldr r0, [r7, #4]
8005314: f7ff ff4c bl 80051b0 <__NVIC_SetPriorityGrouping>
}
8005318: bf00 nop
800531a: 3708 adds r7, #8
800531c: 46bd mov sp, r7
800531e: bd80 pop {r7, pc}
08005320 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8005320: b580 push {r7, lr}
8005322: b086 sub sp, #24
8005324: af00 add r7, sp, #0
8005326: 4603 mov r3, r0
8005328: 60b9 str r1, [r7, #8]
800532a: 607a str r2, [r7, #4]
800532c: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
800532e: 2300 movs r3, #0
8005330: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8005332: f7ff ff61 bl 80051f8 <__NVIC_GetPriorityGrouping>
8005336: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8005338: 687a ldr r2, [r7, #4]
800533a: 68b9 ldr r1, [r7, #8]
800533c: 6978 ldr r0, [r7, #20]
800533e: f7ff ffb1 bl 80052a4 <NVIC_EncodePriority>
8005342: 4602 mov r2, r0
8005344: f997 300f ldrsb.w r3, [r7, #15]
8005348: 4611 mov r1, r2
800534a: 4618 mov r0, r3
800534c: f7ff ff80 bl 8005250 <__NVIC_SetPriority>
}
8005350: bf00 nop
8005352: 3718 adds r7, #24
8005354: 46bd mov sp, r7
8005356: bd80 pop {r7, pc}
08005358 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8005358: b580 push {r7, lr}
800535a: b082 sub sp, #8
800535c: af00 add r7, sp, #0
800535e: 4603 mov r3, r0
8005360: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8005362: f997 3007 ldrsb.w r3, [r7, #7]
8005366: 4618 mov r0, r3
8005368: f7ff ff54 bl 8005214 <__NVIC_EnableIRQ>
}
800536c: bf00 nop
800536e: 3708 adds r7, #8
8005370: 46bd mov sp, r7
8005372: bd80 pop {r7, pc}
08005374 <HAL_CRC_Init>:
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
8005374: b580 push {r7, lr}
8005376: b082 sub sp, #8
8005378: af00 add r7, sp, #0
800537a: 6078 str r0, [r7, #4]
/* Check the CRC handle allocation */
if (hcrc == NULL)
800537c: 687b ldr r3, [r7, #4]
800537e: 2b00 cmp r3, #0
8005380: d101 bne.n 8005386 <HAL_CRC_Init+0x12>
{
return HAL_ERROR;
8005382: 2301 movs r3, #1
8005384: e054 b.n 8005430 <HAL_CRC_Init+0xbc>
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
8005386: 687b ldr r3, [r7, #4]
8005388: 7f5b ldrb r3, [r3, #29]
800538a: b2db uxtb r3, r3
800538c: 2b00 cmp r3, #0
800538e: d105 bne.n 800539c <HAL_CRC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
8005390: 687b ldr r3, [r7, #4]
8005392: 2200 movs r2, #0
8005394: 771a strb r2, [r3, #28]
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
8005396: 6878 ldr r0, [r7, #4]
8005398: f7fe fe1c bl 8003fd4 <HAL_CRC_MspInit>
}
hcrc->State = HAL_CRC_STATE_BUSY;
800539c: 687b ldr r3, [r7, #4]
800539e: 2202 movs r2, #2
80053a0: 775a strb r2, [r3, #29]
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
80053a2: 687b ldr r3, [r7, #4]
80053a4: 791b ldrb r3, [r3, #4]
80053a6: 2b00 cmp r3, #0
80053a8: d10c bne.n 80053c4 <HAL_CRC_Init+0x50>
{
/* initialize peripheral with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
80053aa: 687b ldr r3, [r7, #4]
80053ac: 681b ldr r3, [r3, #0]
80053ae: 4a22 ldr r2, [pc, #136] ; (8005438 <HAL_CRC_Init+0xc4>)
80053b0: 615a str r2, [r3, #20]
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
80053b2: 687b ldr r3, [r7, #4]
80053b4: 681b ldr r3, [r3, #0]
80053b6: 689a ldr r2, [r3, #8]
80053b8: 687b ldr r3, [r7, #4]
80053ba: 681b ldr r3, [r3, #0]
80053bc: f022 0218 bic.w r2, r2, #24
80053c0: 609a str r2, [r3, #8]
80053c2: e00c b.n 80053de <HAL_CRC_Init+0x6a>
}
else
{
/* initialize CRC peripheral with generating polynomial defined by user */
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
80053c4: 687b ldr r3, [r7, #4]
80053c6: 6899 ldr r1, [r3, #8]
80053c8: 687b ldr r3, [r7, #4]
80053ca: 68db ldr r3, [r3, #12]
80053cc: 461a mov r2, r3
80053ce: 6878 ldr r0, [r7, #4]
80053d0: f000 f834 bl 800543c <HAL_CRCEx_Polynomial_Set>
80053d4: 4603 mov r3, r0
80053d6: 2b00 cmp r3, #0
80053d8: d001 beq.n 80053de <HAL_CRC_Init+0x6a>
{
return HAL_ERROR;
80053da: 2301 movs r3, #1
80053dc: e028 b.n 8005430 <HAL_CRC_Init+0xbc>
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
80053de: 687b ldr r3, [r7, #4]
80053e0: 795b ldrb r3, [r3, #5]
80053e2: 2b00 cmp r3, #0
80053e4: d105 bne.n 80053f2 <HAL_CRC_Init+0x7e>
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
80053e6: 687b ldr r3, [r7, #4]
80053e8: 681b ldr r3, [r3, #0]
80053ea: f04f 32ff mov.w r2, #4294967295
80053ee: 611a str r2, [r3, #16]
80053f0: e004 b.n 80053fc <HAL_CRC_Init+0x88>
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
80053f2: 687b ldr r3, [r7, #4]
80053f4: 681b ldr r3, [r3, #0]
80053f6: 687a ldr r2, [r7, #4]
80053f8: 6912 ldr r2, [r2, #16]
80053fa: 611a str r2, [r3, #16]
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
80053fc: 687b ldr r3, [r7, #4]
80053fe: 681b ldr r3, [r3, #0]
8005400: 689b ldr r3, [r3, #8]
8005402: f023 0160 bic.w r1, r3, #96 ; 0x60
8005406: 687b ldr r3, [r7, #4]
8005408: 695a ldr r2, [r3, #20]
800540a: 687b ldr r3, [r7, #4]
800540c: 681b ldr r3, [r3, #0]
800540e: 430a orrs r2, r1
8005410: 609a str r2, [r3, #8]
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
8005412: 687b ldr r3, [r7, #4]
8005414: 681b ldr r3, [r3, #0]
8005416: 689b ldr r3, [r3, #8]
8005418: f023 0180 bic.w r1, r3, #128 ; 0x80
800541c: 687b ldr r3, [r7, #4]
800541e: 699a ldr r2, [r3, #24]
8005420: 687b ldr r3, [r7, #4]
8005422: 681b ldr r3, [r3, #0]
8005424: 430a orrs r2, r1
8005426: 609a str r2, [r3, #8]
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
8005428: 687b ldr r3, [r7, #4]
800542a: 2201 movs r2, #1
800542c: 775a strb r2, [r3, #29]
/* Return function status */
return HAL_OK;
800542e: 2300 movs r3, #0
}
8005430: 4618 mov r0, r3
8005432: 3708 adds r7, #8
8005434: 46bd mov sp, r7
8005436: bd80 pop {r7, pc}
8005438: 04c11db7 .word 0x04c11db7
0800543c <HAL_CRCEx_Polynomial_Set>:
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
800543c: b480 push {r7}
800543e: b087 sub sp, #28
8005440: af00 add r7, sp, #0
8005442: 60f8 str r0, [r7, #12]
8005444: 60b9 str r1, [r7, #8]
8005446: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005448: 2300 movs r3, #0
800544a: 75fb strb r3, [r7, #23]
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
800544c: 231f movs r3, #31
800544e: 613b str r3, [r7, #16]
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
8005450: bf00 nop
8005452: 693b ldr r3, [r7, #16]
8005454: 1e5a subs r2, r3, #1
8005456: 613a str r2, [r7, #16]
8005458: 2b00 cmp r3, #0
800545a: d009 beq.n 8005470 <HAL_CRCEx_Polynomial_Set+0x34>
800545c: 693b ldr r3, [r7, #16]
800545e: f003 031f and.w r3, r3, #31
8005462: 68ba ldr r2, [r7, #8]
8005464: fa22 f303 lsr.w r3, r2, r3
8005468: f003 0301 and.w r3, r3, #1
800546c: 2b00 cmp r3, #0
800546e: d0f0 beq.n 8005452 <HAL_CRCEx_Polynomial_Set+0x16>
{
}
switch (PolyLength)
8005470: 687b ldr r3, [r7, #4]
8005472: 2b18 cmp r3, #24
8005474: d846 bhi.n 8005504 <HAL_CRCEx_Polynomial_Set+0xc8>
8005476: a201 add r2, pc, #4 ; (adr r2, 800547c <HAL_CRCEx_Polynomial_Set+0x40>)
8005478: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800547c: 0800550b .word 0x0800550b
8005480: 08005505 .word 0x08005505
8005484: 08005505 .word 0x08005505
8005488: 08005505 .word 0x08005505
800548c: 08005505 .word 0x08005505
8005490: 08005505 .word 0x08005505
8005494: 08005505 .word 0x08005505
8005498: 08005505 .word 0x08005505
800549c: 080054f9 .word 0x080054f9
80054a0: 08005505 .word 0x08005505
80054a4: 08005505 .word 0x08005505
80054a8: 08005505 .word 0x08005505
80054ac: 08005505 .word 0x08005505
80054b0: 08005505 .word 0x08005505
80054b4: 08005505 .word 0x08005505
80054b8: 08005505 .word 0x08005505
80054bc: 080054ed .word 0x080054ed
80054c0: 08005505 .word 0x08005505
80054c4: 08005505 .word 0x08005505
80054c8: 08005505 .word 0x08005505
80054cc: 08005505 .word 0x08005505
80054d0: 08005505 .word 0x08005505
80054d4: 08005505 .word 0x08005505
80054d8: 08005505 .word 0x08005505
80054dc: 080054e1 .word 0x080054e1
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
80054e0: 693b ldr r3, [r7, #16]
80054e2: 2b06 cmp r3, #6
80054e4: d913 bls.n 800550e <HAL_CRCEx_Polynomial_Set+0xd2>
{
status = HAL_ERROR;
80054e6: 2301 movs r3, #1
80054e8: 75fb strb r3, [r7, #23]
}
break;
80054ea: e010 b.n 800550e <HAL_CRCEx_Polynomial_Set+0xd2>
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
80054ec: 693b ldr r3, [r7, #16]
80054ee: 2b07 cmp r3, #7
80054f0: d90f bls.n 8005512 <HAL_CRCEx_Polynomial_Set+0xd6>
{
status = HAL_ERROR;
80054f2: 2301 movs r3, #1
80054f4: 75fb strb r3, [r7, #23]
}
break;
80054f6: e00c b.n 8005512 <HAL_CRCEx_Polynomial_Set+0xd6>
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
80054f8: 693b ldr r3, [r7, #16]
80054fa: 2b0f cmp r3, #15
80054fc: d90b bls.n 8005516 <HAL_CRCEx_Polynomial_Set+0xda>
{
status = HAL_ERROR;
80054fe: 2301 movs r3, #1
8005500: 75fb strb r3, [r7, #23]
}
break;
8005502: e008 b.n 8005516 <HAL_CRCEx_Polynomial_Set+0xda>
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
8005504: 2301 movs r3, #1
8005506: 75fb strb r3, [r7, #23]
break;
8005508: e006 b.n 8005518 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800550a: bf00 nop
800550c: e004 b.n 8005518 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
800550e: bf00 nop
8005510: e002 b.n 8005518 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005512: bf00 nop
8005514: e000 b.n 8005518 <HAL_CRCEx_Polynomial_Set+0xdc>
break;
8005516: bf00 nop
}
if (status == HAL_OK)
8005518: 7dfb ldrb r3, [r7, #23]
800551a: 2b00 cmp r3, #0
800551c: d10d bne.n 800553a <HAL_CRCEx_Polynomial_Set+0xfe>
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
800551e: 68fb ldr r3, [r7, #12]
8005520: 681b ldr r3, [r3, #0]
8005522: 68ba ldr r2, [r7, #8]
8005524: 615a str r2, [r3, #20]
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
8005526: 68fb ldr r3, [r7, #12]
8005528: 681b ldr r3, [r3, #0]
800552a: 689b ldr r3, [r3, #8]
800552c: f023 0118 bic.w r1, r3, #24
8005530: 68fb ldr r3, [r7, #12]
8005532: 681b ldr r3, [r3, #0]
8005534: 687a ldr r2, [r7, #4]
8005536: 430a orrs r2, r1
8005538: 609a str r2, [r3, #8]
}
/* Return function status */
return status;
800553a: 7dfb ldrb r3, [r7, #23]
}
800553c: 4618 mov r0, r3
800553e: 371c adds r7, #28
8005540: 46bd mov sp, r7
8005542: f85d 7b04 ldr.w r7, [sp], #4
8005546: 4770 bx lr
08005548 <HAL_DAC_Init>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
{
8005548: b580 push {r7, lr}
800554a: b082 sub sp, #8
800554c: af00 add r7, sp, #0
800554e: 6078 str r0, [r7, #4]
/* Check DAC handle */
if(hdac == NULL)
8005550: 687b ldr r3, [r7, #4]
8005552: 2b00 cmp r3, #0
8005554: d101 bne.n 800555a <HAL_DAC_Init+0x12>
{
return HAL_ERROR;
8005556: 2301 movs r3, #1
8005558: e014 b.n 8005584 <HAL_DAC_Init+0x3c>
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if(hdac->State == HAL_DAC_STATE_RESET)
800555a: 687b ldr r3, [r7, #4]
800555c: 791b ldrb r3, [r3, #4]
800555e: b2db uxtb r3, r3
8005560: 2b00 cmp r3, #0
8005562: d105 bne.n 8005570 <HAL_DAC_Init+0x28>
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
8005564: 687b ldr r3, [r7, #4]
8005566: 2200 movs r2, #0
8005568: 715a strb r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
800556a: 6878 ldr r0, [r7, #4]
800556c: f7fe fd52 bl 8004014 <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
8005570: 687b ldr r3, [r7, #4]
8005572: 2202 movs r2, #2
8005574: 711a strb r2, [r3, #4]
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
8005576: 687b ldr r3, [r7, #4]
8005578: 2200 movs r2, #0
800557a: 611a str r2, [r3, #16]
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
800557c: 687b ldr r3, [r7, #4]
800557e: 2201 movs r2, #1
8005580: 711a strb r2, [r3, #4]
/* Return function status */
return HAL_OK;
8005582: 2300 movs r3, #0
}
8005584: 4618 mov r0, r3
8005586: 3708 adds r7, #8
8005588: 46bd mov sp, r7
800558a: bd80 pop {r7, pc}
0800558c <HAL_DAC_IRQHandler>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
800558c: b580 push {r7, lr}
800558e: b082 sub sp, #8
8005590: af00 add r7, sp, #0
8005592: 6078 str r0, [r7, #4]
/* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
8005594: 687b ldr r3, [r7, #4]
8005596: 681b ldr r3, [r3, #0]
8005598: 6b5b ldr r3, [r3, #52] ; 0x34
800559a: f403 5300 and.w r3, r3, #8192 ; 0x2000
800559e: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80055a2: d118 bne.n 80055d6 <HAL_DAC_IRQHandler+0x4a>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
80055a4: 687b ldr r3, [r7, #4]
80055a6: 2204 movs r2, #4
80055a8: 711a strb r2, [r3, #4]
/* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
80055aa: 687b ldr r3, [r7, #4]
80055ac: 691b ldr r3, [r3, #16]
80055ae: f043 0201 orr.w r2, r3, #1
80055b2: 687b ldr r3, [r7, #4]
80055b4: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
80055b6: 687b ldr r3, [r7, #4]
80055b8: 681b ldr r3, [r3, #0]
80055ba: f44f 5200 mov.w r2, #8192 ; 0x2000
80055be: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
80055c0: 687b ldr r3, [r7, #4]
80055c2: 681b ldr r3, [r3, #0]
80055c4: 681a ldr r2, [r3, #0]
80055c6: 687b ldr r3, [r7, #4]
80055c8: 681b ldr r3, [r3, #0]
80055ca: f422 5280 bic.w r2, r2, #4096 ; 0x1000
80055ce: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
80055d0: 6878 ldr r0, [r7, #4]
80055d2: f000 f825 bl 8005620 <HAL_DAC_DMAUnderrunCallbackCh1>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
80055d6: 687b ldr r3, [r7, #4]
80055d8: 681b ldr r3, [r3, #0]
80055da: 6b5b ldr r3, [r3, #52] ; 0x34
80055dc: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80055e0: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
80055e4: d118 bne.n 8005618 <HAL_DAC_IRQHandler+0x8c>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
80055e6: 687b ldr r3, [r7, #4]
80055e8: 2204 movs r2, #4
80055ea: 711a strb r2, [r3, #4]
/* Set DAC error code to channel2 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
80055ec: 687b ldr r3, [r7, #4]
80055ee: 691b ldr r3, [r3, #16]
80055f0: f043 0202 orr.w r2, r3, #2
80055f4: 687b ldr r3, [r7, #4]
80055f6: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
80055f8: 687b ldr r3, [r7, #4]
80055fa: 681b ldr r3, [r3, #0]
80055fc: f04f 5200 mov.w r2, #536870912 ; 0x20000000
8005600: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
8005602: 687b ldr r3, [r7, #4]
8005604: 681b ldr r3, [r3, #0]
8005606: 681a ldr r2, [r3, #0]
8005608: 687b ldr r3, [r7, #4]
800560a: 681b ldr r3, [r3, #0]
800560c: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
8005610: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
8005612: 6878 ldr r0, [r7, #4]
8005614: f000 f85b bl 80056ce <HAL_DACEx_DMAUnderrunCallbackCh2>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
8005618: bf00 nop
800561a: 3708 adds r7, #8
800561c: 46bd mov sp, r7
800561e: bd80 pop {r7, pc}
08005620 <HAL_DAC_DMAUnderrunCallbackCh1>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
8005620: b480 push {r7}
8005622: b083 sub sp, #12
8005624: af00 add r7, sp, #0
8005626: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
8005628: bf00 nop
800562a: 370c adds r7, #12
800562c: 46bd mov sp, r7
800562e: f85d 7b04 ldr.w r7, [sp], #4
8005632: 4770 bx lr
08005634 <HAL_DAC_ConfigChannel>:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
8005634: b480 push {r7}
8005636: b087 sub sp, #28
8005638: af00 add r7, sp, #0
800563a: 60f8 str r0, [r7, #12]
800563c: 60b9 str r1, [r7, #8]
800563e: 607a str r2, [r7, #4]
uint32_t tmpreg1 = 0, tmpreg2 = 0;
8005640: 2300 movs r3, #0
8005642: 617b str r3, [r7, #20]
8005644: 2300 movs r3, #0
8005646: 613b str r3, [r7, #16]
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
8005648: 68fb ldr r3, [r7, #12]
800564a: 795b ldrb r3, [r3, #5]
800564c: 2b01 cmp r3, #1
800564e: d101 bne.n 8005654 <HAL_DAC_ConfigChannel+0x20>
8005650: 2302 movs r3, #2
8005652: e036 b.n 80056c2 <HAL_DAC_ConfigChannel+0x8e>
8005654: 68fb ldr r3, [r7, #12]
8005656: 2201 movs r2, #1
8005658: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
800565a: 68fb ldr r3, [r7, #12]
800565c: 2202 movs r2, #2
800565e: 711a strb r2, [r3, #4]
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
8005660: 68fb ldr r3, [r7, #12]
8005662: 681b ldr r3, [r3, #0]
8005664: 681b ldr r3, [r3, #0]
8005666: 617b str r3, [r7, #20]
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
8005668: f640 72fe movw r2, #4094 ; 0xffe
800566c: 687b ldr r3, [r7, #4]
800566e: fa02 f303 lsl.w r3, r2, r3
8005672: 43db mvns r3, r3
8005674: 697a ldr r2, [r7, #20]
8005676: 4013 ands r3, r2
8005678: 617b str r3, [r7, #20]
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
800567a: 68bb ldr r3, [r7, #8]
800567c: 681a ldr r2, [r3, #0]
800567e: 68bb ldr r3, [r7, #8]
8005680: 685b ldr r3, [r3, #4]
8005682: 4313 orrs r3, r2
8005684: 613b str r3, [r7, #16]
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
8005686: 693a ldr r2, [r7, #16]
8005688: 687b ldr r3, [r7, #4]
800568a: fa02 f303 lsl.w r3, r2, r3
800568e: 697a ldr r2, [r7, #20]
8005690: 4313 orrs r3, r2
8005692: 617b str r3, [r7, #20]
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
8005694: 68fb ldr r3, [r7, #12]
8005696: 681b ldr r3, [r3, #0]
8005698: 697a ldr r2, [r7, #20]
800569a: 601a str r2, [r3, #0]
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
800569c: 68fb ldr r3, [r7, #12]
800569e: 681b ldr r3, [r3, #0]
80056a0: 6819 ldr r1, [r3, #0]
80056a2: 22c0 movs r2, #192 ; 0xc0
80056a4: 687b ldr r3, [r7, #4]
80056a6: fa02 f303 lsl.w r3, r2, r3
80056aa: 43da mvns r2, r3
80056ac: 68fb ldr r3, [r7, #12]
80056ae: 681b ldr r3, [r3, #0]
80056b0: 400a ands r2, r1
80056b2: 601a str r2, [r3, #0]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
80056b4: 68fb ldr r3, [r7, #12]
80056b6: 2201 movs r2, #1
80056b8: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
80056ba: 68fb ldr r3, [r7, #12]
80056bc: 2200 movs r2, #0
80056be: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
80056c0: 2300 movs r3, #0
}
80056c2: 4618 mov r0, r3
80056c4: 371c adds r7, #28
80056c6: 46bd mov sp, r7
80056c8: f85d 7b04 ldr.w r7, [sp], #4
80056cc: 4770 bx lr
080056ce <HAL_DACEx_DMAUnderrunCallbackCh2>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
80056ce: b480 push {r7}
80056d0: b083 sub sp, #12
80056d2: af00 add r7, sp, #0
80056d4: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
80056d6: bf00 nop
80056d8: 370c adds r7, #12
80056da: 46bd mov sp, r7
80056dc: f85d 7b04 ldr.w r7, [sp], #4
80056e0: 4770 bx lr
...
080056e4 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
80056e4: b580 push {r7, lr}
80056e6: b086 sub sp, #24
80056e8: af00 add r7, sp, #0
80056ea: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
80056ec: 2300 movs r3, #0
80056ee: 617b str r3, [r7, #20]
uint32_t tickstart = HAL_GetTick();
80056f0: f7ff f956 bl 80049a0 <HAL_GetTick>
80056f4: 6138 str r0, [r7, #16]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
80056f6: 687b ldr r3, [r7, #4]
80056f8: 2b00 cmp r3, #0
80056fa: d101 bne.n 8005700 <HAL_DMA_Init+0x1c>
{
return HAL_ERROR;
80056fc: 2301 movs r3, #1
80056fe: e099 b.n 8005834 <HAL_DMA_Init+0x150>
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
8005700: 687b ldr r3, [r7, #4]
8005702: 2200 movs r2, #0
8005704: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8005708: 687b ldr r3, [r7, #4]
800570a: 2202 movs r2, #2
800570c: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8005710: 687b ldr r3, [r7, #4]
8005712: 681b ldr r3, [r3, #0]
8005714: 681a ldr r2, [r3, #0]
8005716: 687b ldr r3, [r7, #4]
8005718: 681b ldr r3, [r3, #0]
800571a: f022 0201 bic.w r2, r2, #1
800571e: 601a str r2, [r3, #0]
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
8005720: e00f b.n 8005742 <HAL_DMA_Init+0x5e>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
8005722: f7ff f93d bl 80049a0 <HAL_GetTick>
8005726: 4602 mov r2, r0
8005728: 693b ldr r3, [r7, #16]
800572a: 1ad3 subs r3, r2, r3
800572c: 2b05 cmp r3, #5
800572e: d908 bls.n 8005742 <HAL_DMA_Init+0x5e>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
8005730: 687b ldr r3, [r7, #4]
8005732: 2220 movs r2, #32
8005734: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
8005736: 687b ldr r3, [r7, #4]
8005738: 2203 movs r2, #3
800573a: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_TIMEOUT;
800573e: 2303 movs r3, #3
8005740: e078 b.n 8005834 <HAL_DMA_Init+0x150>
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
8005742: 687b ldr r3, [r7, #4]
8005744: 681b ldr r3, [r3, #0]
8005746: 681b ldr r3, [r3, #0]
8005748: f003 0301 and.w r3, r3, #1
800574c: 2b00 cmp r3, #0
800574e: d1e8 bne.n 8005722 <HAL_DMA_Init+0x3e>
}
}
/* Get the CR register value */
tmp = hdma->Instance->CR;
8005750: 687b ldr r3, [r7, #4]
8005752: 681b ldr r3, [r3, #0]
8005754: 681b ldr r3, [r3, #0]
8005756: 617b str r3, [r7, #20]
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
8005758: 697a ldr r2, [r7, #20]
800575a: 4b38 ldr r3, [pc, #224] ; (800583c <HAL_DMA_Init+0x158>)
800575c: 4013 ands r3, r2
800575e: 617b str r3, [r7, #20]
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
8005760: 687b ldr r3, [r7, #4]
8005762: 685a ldr r2, [r3, #4]
8005764: 687b ldr r3, [r7, #4]
8005766: 689b ldr r3, [r3, #8]
8005768: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
800576a: 687b ldr r3, [r7, #4]
800576c: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Channel | hdma->Init.Direction |
800576e: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8005770: 687b ldr r3, [r7, #4]
8005772: 691b ldr r3, [r3, #16]
8005774: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005776: 687b ldr r3, [r7, #4]
8005778: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
800577a: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800577c: 687b ldr r3, [r7, #4]
800577e: 699b ldr r3, [r3, #24]
8005780: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005782: 687b ldr r3, [r7, #4]
8005784: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005786: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005788: 687b ldr r3, [r7, #4]
800578a: 6a1b ldr r3, [r3, #32]
800578c: 4313 orrs r3, r2
tmp |= hdma->Init.Channel | hdma->Init.Direction |
800578e: 697a ldr r2, [r7, #20]
8005790: 4313 orrs r3, r2
8005792: 617b str r3, [r7, #20]
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
8005794: 687b ldr r3, [r7, #4]
8005796: 6a5b ldr r3, [r3, #36] ; 0x24
8005798: 2b04 cmp r3, #4
800579a: d107 bne.n 80057ac <HAL_DMA_Init+0xc8>
{
/* Get memory burst and peripheral burst */
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
800579c: 687b ldr r3, [r7, #4]
800579e: 6ada ldr r2, [r3, #44] ; 0x2c
80057a0: 687b ldr r3, [r7, #4]
80057a2: 6b1b ldr r3, [r3, #48] ; 0x30
80057a4: 4313 orrs r3, r2
80057a6: 697a ldr r2, [r7, #20]
80057a8: 4313 orrs r3, r2
80057aa: 617b str r3, [r7, #20]
}
/* Write to DMA Stream CR register */
hdma->Instance->CR = tmp;
80057ac: 687b ldr r3, [r7, #4]
80057ae: 681b ldr r3, [r3, #0]
80057b0: 697a ldr r2, [r7, #20]
80057b2: 601a str r2, [r3, #0]
/* Get the FCR register value */
tmp = hdma->Instance->FCR;
80057b4: 687b ldr r3, [r7, #4]
80057b6: 681b ldr r3, [r3, #0]
80057b8: 695b ldr r3, [r3, #20]
80057ba: 617b str r3, [r7, #20]
/* Clear Direct mode and FIFO threshold bits */
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
80057bc: 697b ldr r3, [r7, #20]
80057be: f023 0307 bic.w r3, r3, #7
80057c2: 617b str r3, [r7, #20]
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
80057c4: 687b ldr r3, [r7, #4]
80057c6: 6a5b ldr r3, [r3, #36] ; 0x24
80057c8: 697a ldr r2, [r7, #20]
80057ca: 4313 orrs r3, r2
80057cc: 617b str r3, [r7, #20]
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
80057ce: 687b ldr r3, [r7, #4]
80057d0: 6a5b ldr r3, [r3, #36] ; 0x24
80057d2: 2b04 cmp r3, #4
80057d4: d117 bne.n 8005806 <HAL_DMA_Init+0x122>
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
80057d6: 687b ldr r3, [r7, #4]
80057d8: 6a9b ldr r3, [r3, #40] ; 0x28
80057da: 697a ldr r2, [r7, #20]
80057dc: 4313 orrs r3, r2
80057de: 617b str r3, [r7, #20]
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
80057e0: 687b ldr r3, [r7, #4]
80057e2: 6adb ldr r3, [r3, #44] ; 0x2c
80057e4: 2b00 cmp r3, #0
80057e6: d00e beq.n 8005806 <HAL_DMA_Init+0x122>
{
if (DMA_CheckFifoParam(hdma) != HAL_OK)
80057e8: 6878 ldr r0, [r7, #4]
80057ea: f000 f8bd bl 8005968 <DMA_CheckFifoParam>
80057ee: 4603 mov r3, r0
80057f0: 2b00 cmp r3, #0
80057f2: d008 beq.n 8005806 <HAL_DMA_Init+0x122>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
80057f4: 687b ldr r3, [r7, #4]
80057f6: 2240 movs r2, #64 ; 0x40
80057f8: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80057fa: 687b ldr r3, [r7, #4]
80057fc: 2201 movs r2, #1
80057fe: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_ERROR;
8005802: 2301 movs r3, #1
8005804: e016 b.n 8005834 <HAL_DMA_Init+0x150>
}
}
}
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
8005806: 687b ldr r3, [r7, #4]
8005808: 681b ldr r3, [r3, #0]
800580a: 697a ldr r2, [r7, #20]
800580c: 615a str r2, [r3, #20]
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
800580e: 6878 ldr r0, [r7, #4]
8005810: f000 f874 bl 80058fc <DMA_CalcBaseAndBitshift>
8005814: 4603 mov r3, r0
8005816: 60fb str r3, [r7, #12]
/* Clear all interrupt flags */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8005818: 687b ldr r3, [r7, #4]
800581a: 6ddb ldr r3, [r3, #92] ; 0x5c
800581c: 223f movs r2, #63 ; 0x3f
800581e: 409a lsls r2, r3
8005820: 68fb ldr r3, [r7, #12]
8005822: 609a str r2, [r3, #8]
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8005824: 687b ldr r3, [r7, #4]
8005826: 2200 movs r2, #0
8005828: 655a str r2, [r3, #84] ; 0x54
/* Initialize the DMA state */
hdma->State = HAL_DMA_STATE_READY;
800582a: 687b ldr r3, [r7, #4]
800582c: 2201 movs r2, #1
800582e: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_OK;
8005832: 2300 movs r3, #0
}
8005834: 4618 mov r0, r3
8005836: 3718 adds r7, #24
8005838: 46bd mov sp, r7
800583a: bd80 pop {r7, pc}
800583c: f010803f .word 0xf010803f
08005840 <HAL_DMA_DeInit>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
8005840: b580 push {r7, lr}
8005842: b084 sub sp, #16
8005844: af00 add r7, sp, #0
8005846: 6078 str r0, [r7, #4]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
8005848: 687b ldr r3, [r7, #4]
800584a: 2b00 cmp r3, #0
800584c: d101 bne.n 8005852 <HAL_DMA_DeInit+0x12>
{
return HAL_ERROR;
800584e: 2301 movs r3, #1
8005850: e050 b.n 80058f4 <HAL_DMA_DeInit+0xb4>
}
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
8005852: 687b ldr r3, [r7, #4]
8005854: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8005858: b2db uxtb r3, r3
800585a: 2b02 cmp r3, #2
800585c: d101 bne.n 8005862 <HAL_DMA_DeInit+0x22>
{
/* Return error status */
return HAL_BUSY;
800585e: 2302 movs r3, #2
8005860: e048 b.n 80058f4 <HAL_DMA_DeInit+0xb4>
/* Check the parameters */
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
8005862: 687b ldr r3, [r7, #4]
8005864: 681b ldr r3, [r3, #0]
8005866: 681a ldr r2, [r3, #0]
8005868: 687b ldr r3, [r7, #4]
800586a: 681b ldr r3, [r3, #0]
800586c: f022 0201 bic.w r2, r2, #1
8005870: 601a str r2, [r3, #0]
/* Reset DMA Streamx control register */
hdma->Instance->CR = 0U;
8005872: 687b ldr r3, [r7, #4]
8005874: 681b ldr r3, [r3, #0]
8005876: 2200 movs r2, #0
8005878: 601a str r2, [r3, #0]
/* Reset DMA Streamx number of data to transfer register */
hdma->Instance->NDTR = 0U;
800587a: 687b ldr r3, [r7, #4]
800587c: 681b ldr r3, [r3, #0]
800587e: 2200 movs r2, #0
8005880: 605a str r2, [r3, #4]
/* Reset DMA Streamx peripheral address register */
hdma->Instance->PAR = 0U;
8005882: 687b ldr r3, [r7, #4]
8005884: 681b ldr r3, [r3, #0]
8005886: 2200 movs r2, #0
8005888: 609a str r2, [r3, #8]
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0U;
800588a: 687b ldr r3, [r7, #4]
800588c: 681b ldr r3, [r3, #0]
800588e: 2200 movs r2, #0
8005890: 60da str r2, [r3, #12]
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0U;
8005892: 687b ldr r3, [r7, #4]
8005894: 681b ldr r3, [r3, #0]
8005896: 2200 movs r2, #0
8005898: 611a str r2, [r3, #16]
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
800589a: 687b ldr r3, [r7, #4]
800589c: 681b ldr r3, [r3, #0]
800589e: 2221 movs r2, #33 ; 0x21
80058a0: 615a str r2, [r3, #20]
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
80058a2: 6878 ldr r0, [r7, #4]
80058a4: f000 f82a bl 80058fc <DMA_CalcBaseAndBitshift>
80058a8: 4603 mov r3, r0
80058aa: 60fb str r3, [r7, #12]
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
80058ac: 687b ldr r3, [r7, #4]
80058ae: 6ddb ldr r3, [r3, #92] ; 0x5c
80058b0: 223f movs r2, #63 ; 0x3f
80058b2: 409a lsls r2, r3
80058b4: 68fb ldr r3, [r7, #12]
80058b6: 609a str r2, [r3, #8]
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
80058b8: 687b ldr r3, [r7, #4]
80058ba: 2200 movs r2, #0
80058bc: 63da str r2, [r3, #60] ; 0x3c
hdma->XferHalfCpltCallback = NULL;
80058be: 687b ldr r3, [r7, #4]
80058c0: 2200 movs r2, #0
80058c2: 641a str r2, [r3, #64] ; 0x40
hdma->XferM1CpltCallback = NULL;
80058c4: 687b ldr r3, [r7, #4]
80058c6: 2200 movs r2, #0
80058c8: 645a str r2, [r3, #68] ; 0x44
hdma->XferM1HalfCpltCallback = NULL;
80058ca: 687b ldr r3, [r7, #4]
80058cc: 2200 movs r2, #0
80058ce: 649a str r2, [r3, #72] ; 0x48
hdma->XferErrorCallback = NULL;
80058d0: 687b ldr r3, [r7, #4]
80058d2: 2200 movs r2, #0
80058d4: 64da str r2, [r3, #76] ; 0x4c
hdma->XferAbortCallback = NULL;
80058d6: 687b ldr r3, [r7, #4]
80058d8: 2200 movs r2, #0
80058da: 651a str r2, [r3, #80] ; 0x50
/* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80058dc: 687b ldr r3, [r7, #4]
80058de: 2200 movs r2, #0
80058e0: 655a str r2, [r3, #84] ; 0x54
/* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
80058e2: 687b ldr r3, [r7, #4]
80058e4: 2200 movs r2, #0
80058e6: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Release Lock */
__HAL_UNLOCK(hdma);
80058ea: 687b ldr r3, [r7, #4]
80058ec: 2200 movs r2, #0
80058ee: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_OK;
80058f2: 2300 movs r3, #0
}
80058f4: 4618 mov r0, r3
80058f6: 3710 adds r7, #16
80058f8: 46bd mov sp, r7
80058fa: bd80 pop {r7, pc}
080058fc <DMA_CalcBaseAndBitshift>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
80058fc: b480 push {r7}
80058fe: b085 sub sp, #20
8005900: af00 add r7, sp, #0
8005902: 6078 str r0, [r7, #4]
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
8005904: 687b ldr r3, [r7, #4]
8005906: 681b ldr r3, [r3, #0]
8005908: b2db uxtb r3, r3
800590a: 3b10 subs r3, #16
800590c: 4a13 ldr r2, [pc, #76] ; (800595c <DMA_CalcBaseAndBitshift+0x60>)
800590e: fba2 2303 umull r2, r3, r2, r3
8005912: 091b lsrs r3, r3, #4
8005914: 60fb str r3, [r7, #12]
/* lookup table for necessary bitshift of flags within status registers */
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
hdma->StreamIndex = flagBitshiftOffset[stream_number];
8005916: 4a12 ldr r2, [pc, #72] ; (8005960 <DMA_CalcBaseAndBitshift+0x64>)
8005918: 68fb ldr r3, [r7, #12]
800591a: 4413 add r3, r2
800591c: 781b ldrb r3, [r3, #0]
800591e: 461a mov r2, r3
8005920: 687b ldr r3, [r7, #4]
8005922: 65da str r2, [r3, #92] ; 0x5c
if (stream_number > 3U)
8005924: 68fb ldr r3, [r7, #12]
8005926: 2b03 cmp r3, #3
8005928: d908 bls.n 800593c <DMA_CalcBaseAndBitshift+0x40>
{
/* return pointer to HISR and HIFCR */
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
800592a: 687b ldr r3, [r7, #4]
800592c: 681b ldr r3, [r3, #0]
800592e: 461a mov r2, r3
8005930: 4b0c ldr r3, [pc, #48] ; (8005964 <DMA_CalcBaseAndBitshift+0x68>)
8005932: 4013 ands r3, r2
8005934: 1d1a adds r2, r3, #4
8005936: 687b ldr r3, [r7, #4]
8005938: 659a str r2, [r3, #88] ; 0x58
800593a: e006 b.n 800594a <DMA_CalcBaseAndBitshift+0x4e>
}
else
{
/* return pointer to LISR and LIFCR */
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
800593c: 687b ldr r3, [r7, #4]
800593e: 681b ldr r3, [r3, #0]
8005940: 461a mov r2, r3
8005942: 4b08 ldr r3, [pc, #32] ; (8005964 <DMA_CalcBaseAndBitshift+0x68>)
8005944: 4013 ands r3, r2
8005946: 687a ldr r2, [r7, #4]
8005948: 6593 str r3, [r2, #88] ; 0x58
}
return hdma->StreamBaseAddress;
800594a: 687b ldr r3, [r7, #4]
800594c: 6d9b ldr r3, [r3, #88] ; 0x58
}
800594e: 4618 mov r0, r3
8005950: 3714 adds r7, #20
8005952: 46bd mov sp, r7
8005954: f85d 7b04 ldr.w r7, [sp], #4
8005958: 4770 bx lr
800595a: bf00 nop
800595c: aaaaaaab .word 0xaaaaaaab
8005960: 08020d50 .word 0x08020d50
8005964: fffffc00 .word 0xfffffc00
08005968 <DMA_CheckFifoParam>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
8005968: b480 push {r7}
800596a: b085 sub sp, #20
800596c: af00 add r7, sp, #0
800596e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8005970: 2300 movs r3, #0
8005972: 73fb strb r3, [r7, #15]
uint32_t tmp = hdma->Init.FIFOThreshold;
8005974: 687b ldr r3, [r7, #4]
8005976: 6a9b ldr r3, [r3, #40] ; 0x28
8005978: 60bb str r3, [r7, #8]
/* Memory Data size equal to Byte */
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
800597a: 687b ldr r3, [r7, #4]
800597c: 699b ldr r3, [r3, #24]
800597e: 2b00 cmp r3, #0
8005980: d11f bne.n 80059c2 <DMA_CheckFifoParam+0x5a>
{
switch (tmp)
8005982: 68bb ldr r3, [r7, #8]
8005984: 2b03 cmp r3, #3
8005986: d855 bhi.n 8005a34 <DMA_CheckFifoParam+0xcc>
8005988: a201 add r2, pc, #4 ; (adr r2, 8005990 <DMA_CheckFifoParam+0x28>)
800598a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800598e: bf00 nop
8005990: 080059a1 .word 0x080059a1
8005994: 080059b3 .word 0x080059b3
8005998: 080059a1 .word 0x080059a1
800599c: 08005a35 .word 0x08005a35
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
80059a0: 687b ldr r3, [r7, #4]
80059a2: 6adb ldr r3, [r3, #44] ; 0x2c
80059a4: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80059a8: 2b00 cmp r3, #0
80059aa: d045 beq.n 8005a38 <DMA_CheckFifoParam+0xd0>
{
status = HAL_ERROR;
80059ac: 2301 movs r3, #1
80059ae: 73fb strb r3, [r7, #15]
}
break;
80059b0: e042 b.n 8005a38 <DMA_CheckFifoParam+0xd0>
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
80059b2: 687b ldr r3, [r7, #4]
80059b4: 6adb ldr r3, [r3, #44] ; 0x2c
80059b6: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
80059ba: d13f bne.n 8005a3c <DMA_CheckFifoParam+0xd4>
{
status = HAL_ERROR;
80059bc: 2301 movs r3, #1
80059be: 73fb strb r3, [r7, #15]
}
break;
80059c0: e03c b.n 8005a3c <DMA_CheckFifoParam+0xd4>
break;
}
}
/* Memory Data size equal to Half-Word */
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
80059c2: 687b ldr r3, [r7, #4]
80059c4: 699b ldr r3, [r3, #24]
80059c6: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80059ca: d121 bne.n 8005a10 <DMA_CheckFifoParam+0xa8>
{
switch (tmp)
80059cc: 68bb ldr r3, [r7, #8]
80059ce: 2b03 cmp r3, #3
80059d0: d836 bhi.n 8005a40 <DMA_CheckFifoParam+0xd8>
80059d2: a201 add r2, pc, #4 ; (adr r2, 80059d8 <DMA_CheckFifoParam+0x70>)
80059d4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80059d8: 080059e9 .word 0x080059e9
80059dc: 080059ef .word 0x080059ef
80059e0: 080059e9 .word 0x080059e9
80059e4: 08005a01 .word 0x08005a01
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
80059e8: 2301 movs r3, #1
80059ea: 73fb strb r3, [r7, #15]
break;
80059ec: e02f b.n 8005a4e <DMA_CheckFifoParam+0xe6>
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
80059ee: 687b ldr r3, [r7, #4]
80059f0: 6adb ldr r3, [r3, #44] ; 0x2c
80059f2: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80059f6: 2b00 cmp r3, #0
80059f8: d024 beq.n 8005a44 <DMA_CheckFifoParam+0xdc>
{
status = HAL_ERROR;
80059fa: 2301 movs r3, #1
80059fc: 73fb strb r3, [r7, #15]
}
break;
80059fe: e021 b.n 8005a44 <DMA_CheckFifoParam+0xdc>
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
8005a00: 687b ldr r3, [r7, #4]
8005a02: 6adb ldr r3, [r3, #44] ; 0x2c
8005a04: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
8005a08: d11e bne.n 8005a48 <DMA_CheckFifoParam+0xe0>
{
status = HAL_ERROR;
8005a0a: 2301 movs r3, #1
8005a0c: 73fb strb r3, [r7, #15]
}
break;
8005a0e: e01b b.n 8005a48 <DMA_CheckFifoParam+0xe0>
}
/* Memory Data size equal to Word */
else
{
switch (tmp)
8005a10: 68bb ldr r3, [r7, #8]
8005a12: 2b02 cmp r3, #2
8005a14: d902 bls.n 8005a1c <DMA_CheckFifoParam+0xb4>
8005a16: 2b03 cmp r3, #3
8005a18: d003 beq.n 8005a22 <DMA_CheckFifoParam+0xba>
{
status = HAL_ERROR;
}
break;
default:
break;
8005a1a: e018 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
status = HAL_ERROR;
8005a1c: 2301 movs r3, #1
8005a1e: 73fb strb r3, [r7, #15]
break;
8005a20: e015 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
8005a22: 687b ldr r3, [r7, #4]
8005a24: 6adb ldr r3, [r3, #44] ; 0x2c
8005a26: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005a2a: 2b00 cmp r3, #0
8005a2c: d00e beq.n 8005a4c <DMA_CheckFifoParam+0xe4>
status = HAL_ERROR;
8005a2e: 2301 movs r3, #1
8005a30: 73fb strb r3, [r7, #15]
break;
8005a32: e00b b.n 8005a4c <DMA_CheckFifoParam+0xe4>
break;
8005a34: bf00 nop
8005a36: e00a b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a38: bf00 nop
8005a3a: e008 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a3c: bf00 nop
8005a3e: e006 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a40: bf00 nop
8005a42: e004 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a44: bf00 nop
8005a46: e002 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a48: bf00 nop
8005a4a: e000 b.n 8005a4e <DMA_CheckFifoParam+0xe6>
break;
8005a4c: bf00 nop
}
}
return status;
8005a4e: 7bfb ldrb r3, [r7, #15]
}
8005a50: 4618 mov r0, r3
8005a52: 3714 adds r7, #20
8005a54: 46bd mov sp, r7
8005a56: f85d 7b04 ldr.w r7, [sp], #4
8005a5a: 4770 bx lr
08005a5c <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
8005a5c: b580 push {r7, lr}
8005a5e: b082 sub sp, #8
8005a60: af00 add r7, sp, #0
8005a62: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if(hdma2d == NULL)
8005a64: 687b ldr r3, [r7, #4]
8005a66: 2b00 cmp r3, #0
8005a68: d101 bne.n 8005a6e <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
8005a6a: 2301 movs r3, #1
8005a6c: e039 b.n 8005ae2 <HAL_DMA2D_Init+0x86>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
8005a6e: 687b ldr r3, [r7, #4]
8005a70: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
8005a74: b2db uxtb r3, r3
8005a76: 2b00 cmp r3, #0
8005a78: d106 bne.n 8005a88 <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
8005a7a: 687b ldr r3, [r7, #4]
8005a7c: 2200 movs r2, #0
8005a7e: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
8005a82: 6878 ldr r0, [r7, #4]
8005a84: f7fe fb0e bl 80040a4 <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005a88: 687b ldr r3, [r7, #4]
8005a8a: 2202 movs r2, #2
8005a8c: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
8005a90: 687b ldr r3, [r7, #4]
8005a92: 681b ldr r3, [r3, #0]
8005a94: 681b ldr r3, [r3, #0]
8005a96: f423 3140 bic.w r1, r3, #196608 ; 0x30000
8005a9a: 687b ldr r3, [r7, #4]
8005a9c: 685a ldr r2, [r3, #4]
8005a9e: 687b ldr r3, [r7, #4]
8005aa0: 681b ldr r3, [r3, #0]
8005aa2: 430a orrs r2, r1
8005aa4: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
8005aa6: 687b ldr r3, [r7, #4]
8005aa8: 681b ldr r3, [r3, #0]
8005aaa: 6b5b ldr r3, [r3, #52] ; 0x34
8005aac: f023 0107 bic.w r1, r3, #7
8005ab0: 687b ldr r3, [r7, #4]
8005ab2: 689a ldr r2, [r3, #8]
8005ab4: 687b ldr r3, [r7, #4]
8005ab6: 681b ldr r3, [r3, #0]
8005ab8: 430a orrs r2, r1
8005aba: 635a str r2, [r3, #52] ; 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
8005abc: 687b ldr r3, [r7, #4]
8005abe: 681b ldr r3, [r3, #0]
8005ac0: 6c1a ldr r2, [r3, #64] ; 0x40
8005ac2: 4b0a ldr r3, [pc, #40] ; (8005aec <HAL_DMA2D_Init+0x90>)
8005ac4: 4013 ands r3, r2
8005ac6: 687a ldr r2, [r7, #4]
8005ac8: 68d1 ldr r1, [r2, #12]
8005aca: 687a ldr r2, [r7, #4]
8005acc: 6812 ldr r2, [r2, #0]
8005ace: 430b orrs r3, r1
8005ad0: 6413 str r3, [r2, #64] ; 0x40
MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
8005ad2: 687b ldr r3, [r7, #4]
8005ad4: 2200 movs r2, #0
8005ad6: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005ad8: 687b ldr r3, [r7, #4]
8005ada: 2201 movs r2, #1
8005adc: f883 2039 strb.w r2, [r3, #57] ; 0x39
return HAL_OK;
8005ae0: 2300 movs r3, #0
}
8005ae2: 4618 mov r0, r3
8005ae4: 3708 adds r7, #8
8005ae6: 46bd mov sp, r7
8005ae8: bd80 pop {r7, pc}
8005aea: bf00 nop
8005aec: ffffc000 .word 0xffffc000
08005af0 <HAL_DMA2D_Start>:
* @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
8005af0: b580 push {r7, lr}
8005af2: b086 sub sp, #24
8005af4: af02 add r7, sp, #8
8005af6: 60f8 str r0, [r7, #12]
8005af8: 60b9 str r1, [r7, #8]
8005afa: 607a str r2, [r7, #4]
8005afc: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
8005afe: 68fb ldr r3, [r7, #12]
8005b00: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005b04: 2b01 cmp r3, #1
8005b06: d101 bne.n 8005b0c <HAL_DMA2D_Start+0x1c>
8005b08: 2302 movs r3, #2
8005b0a: e018 b.n 8005b3e <HAL_DMA2D_Start+0x4e>
8005b0c: 68fb ldr r3, [r7, #12]
8005b0e: 2201 movs r2, #1
8005b10: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005b14: 68fb ldr r3, [r7, #12]
8005b16: 2202 movs r2, #2
8005b18: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
8005b1c: 69bb ldr r3, [r7, #24]
8005b1e: 9300 str r3, [sp, #0]
8005b20: 683b ldr r3, [r7, #0]
8005b22: 687a ldr r2, [r7, #4]
8005b24: 68b9 ldr r1, [r7, #8]
8005b26: 68f8 ldr r0, [r7, #12]
8005b28: f000 f988 bl 8005e3c <DMA2D_SetConfig>
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
8005b2c: 68fb ldr r3, [r7, #12]
8005b2e: 681b ldr r3, [r3, #0]
8005b30: 681a ldr r2, [r3, #0]
8005b32: 68fb ldr r3, [r7, #12]
8005b34: 681b ldr r3, [r3, #0]
8005b36: f042 0201 orr.w r2, r2, #1
8005b3a: 601a str r2, [r3, #0]
return HAL_OK;
8005b3c: 2300 movs r3, #0
}
8005b3e: 4618 mov r0, r3
8005b40: 3710 adds r7, #16
8005b42: 46bd mov sp, r7
8005b44: bd80 pop {r7, pc}
08005b46 <HAL_DMA2D_PollForTransfer>:
* the configuration information for the DMA2D.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
8005b46: b580 push {r7, lr}
8005b48: b086 sub sp, #24
8005b4a: af00 add r7, sp, #0
8005b4c: 6078 str r0, [r7, #4]
8005b4e: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
8005b50: 2300 movs r3, #0
8005b52: 60fb str r3, [r7, #12]
/* Polling for DMA2D transfer */
if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
8005b54: 687b ldr r3, [r7, #4]
8005b56: 681b ldr r3, [r3, #0]
8005b58: 681b ldr r3, [r3, #0]
8005b5a: f003 0301 and.w r3, r3, #1
8005b5e: 2b00 cmp r3, #0
8005b60: d056 beq.n 8005c10 <HAL_DMA2D_PollForTransfer+0xca>
{
/* Get tick */
tickstart = HAL_GetTick();
8005b62: f7fe ff1d bl 80049a0 <HAL_GetTick>
8005b66: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
8005b68: e04b b.n 8005c02 <HAL_DMA2D_PollForTransfer+0xbc>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
8005b6a: 687b ldr r3, [r7, #4]
8005b6c: 681b ldr r3, [r3, #0]
8005b6e: 685b ldr r3, [r3, #4]
8005b70: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
8005b72: 68fb ldr r3, [r7, #12]
8005b74: f003 0321 and.w r3, r3, #33 ; 0x21
8005b78: 2b00 cmp r3, #0
8005b7a: d023 beq.n 8005bc4 <HAL_DMA2D_PollForTransfer+0x7e>
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005b7c: 68fb ldr r3, [r7, #12]
8005b7e: f003 0320 and.w r3, r3, #32
8005b82: 2b00 cmp r3, #0
8005b84: d005 beq.n 8005b92 <HAL_DMA2D_PollForTransfer+0x4c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005b86: 687b ldr r3, [r7, #4]
8005b88: 6bdb ldr r3, [r3, #60] ; 0x3c
8005b8a: f043 0202 orr.w r2, r3, #2
8005b8e: 687b ldr r3, [r7, #4]
8005b90: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005b92: 68fb ldr r3, [r7, #12]
8005b94: f003 0301 and.w r3, r3, #1
8005b98: 2b00 cmp r3, #0
8005b9a: d005 beq.n 8005ba8 <HAL_DMA2D_PollForTransfer+0x62>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 6bdb ldr r3, [r3, #60] ; 0x3c
8005ba0: f043 0201 orr.w r2, r3, #1
8005ba4: 687b ldr r3, [r7, #4]
8005ba6: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the transfer and configuration error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005ba8: 687b ldr r3, [r7, #4]
8005baa: 681b ldr r3, [r3, #0]
8005bac: 2221 movs r2, #33 ; 0x21
8005bae: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8005bb0: 687b ldr r3, [r7, #4]
8005bb2: 2204 movs r2, #4
8005bb4: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005bb8: 687b ldr r3, [r7, #4]
8005bba: 2200 movs r2, #0
8005bbc: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005bc0: 2301 movs r3, #1
8005bc2: e0a5 b.n 8005d10 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005bc4: 683b ldr r3, [r7, #0]
8005bc6: f1b3 3fff cmp.w r3, #4294967295
8005bca: d01a beq.n 8005c02 <HAL_DMA2D_PollForTransfer+0xbc>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
8005bcc: f7fe fee8 bl 80049a0 <HAL_GetTick>
8005bd0: 4602 mov r2, r0
8005bd2: 697b ldr r3, [r7, #20]
8005bd4: 1ad3 subs r3, r2, r3
8005bd6: 683a ldr r2, [r7, #0]
8005bd8: 429a cmp r2, r3
8005bda: d302 bcc.n 8005be2 <HAL_DMA2D_PollForTransfer+0x9c>
8005bdc: 683b ldr r3, [r7, #0]
8005bde: 2b00 cmp r3, #0
8005be0: d10f bne.n 8005c02 <HAL_DMA2D_PollForTransfer+0xbc>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005be2: 687b ldr r3, [r7, #4]
8005be4: 6bdb ldr r3, [r3, #60] ; 0x3c
8005be6: f043 0220 orr.w r2, r3, #32
8005bea: 687b ldr r3, [r7, #4]
8005bec: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
8005bee: 687b ldr r3, [r7, #4]
8005bf0: 2203 movs r2, #3
8005bf2: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005bf6: 687b ldr r3, [r7, #4]
8005bf8: 2200 movs r2, #0
8005bfa: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005bfe: 2303 movs r3, #3
8005c00: e086 b.n 8005d10 <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
8005c02: 687b ldr r3, [r7, #4]
8005c04: 681b ldr r3, [r3, #0]
8005c06: 685b ldr r3, [r3, #4]
8005c08: f003 0302 and.w r3, r3, #2
8005c0c: 2b00 cmp r3, #0
8005c0e: d0ac beq.n 8005b6a <HAL_DMA2D_PollForTransfer+0x24>
}
}
}
}
/* Polling for CLUT loading (foreground or background) */
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
8005c10: 687b ldr r3, [r7, #4]
8005c12: 681b ldr r3, [r3, #0]
8005c14: 69db ldr r3, [r3, #28]
8005c16: f003 0320 and.w r3, r3, #32
8005c1a: 613b str r3, [r7, #16]
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
8005c1c: 687b ldr r3, [r7, #4]
8005c1e: 681b ldr r3, [r3, #0]
8005c20: 6a5b ldr r3, [r3, #36] ; 0x24
8005c22: f003 0320 and.w r3, r3, #32
8005c26: 693a ldr r2, [r7, #16]
8005c28: 4313 orrs r3, r2
8005c2a: 613b str r3, [r7, #16]
if (layer_start != 0U)
8005c2c: 693b ldr r3, [r7, #16]
8005c2e: 2b00 cmp r3, #0
8005c30: d061 beq.n 8005cf6 <HAL_DMA2D_PollForTransfer+0x1b0>
{
/* Get tick */
tickstart = HAL_GetTick();
8005c32: f7fe feb5 bl 80049a0 <HAL_GetTick>
8005c36: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005c38: e056 b.n 8005ce8 <HAL_DMA2D_PollForTransfer+0x1a2>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
8005c3a: 687b ldr r3, [r7, #4]
8005c3c: 681b ldr r3, [r3, #0]
8005c3e: 685b ldr r3, [r3, #4]
8005c40: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
8005c42: 68fb ldr r3, [r7, #12]
8005c44: f003 0329 and.w r3, r3, #41 ; 0x29
8005c48: 2b00 cmp r3, #0
8005c4a: d02e beq.n 8005caa <HAL_DMA2D_PollForTransfer+0x164>
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
8005c4c: 68fb ldr r3, [r7, #12]
8005c4e: f003 0308 and.w r3, r3, #8
8005c52: 2b00 cmp r3, #0
8005c54: d005 beq.n 8005c62 <HAL_DMA2D_PollForTransfer+0x11c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
8005c56: 687b ldr r3, [r7, #4]
8005c58: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c5a: f043 0204 orr.w r2, r3, #4
8005c5e: 687b ldr r3, [r7, #4]
8005c60: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8005c62: 68fb ldr r3, [r7, #12]
8005c64: f003 0320 and.w r3, r3, #32
8005c68: 2b00 cmp r3, #0
8005c6a: d005 beq.n 8005c78 <HAL_DMA2D_PollForTransfer+0x132>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005c6c: 687b ldr r3, [r7, #4]
8005c6e: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c70: f043 0202 orr.w r2, r3, #2
8005c74: 687b ldr r3, [r7, #4]
8005c76: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8005c78: 68fb ldr r3, [r7, #12]
8005c7a: f003 0301 and.w r3, r3, #1
8005c7e: 2b00 cmp r3, #0
8005c80: d005 beq.n 8005c8e <HAL_DMA2D_PollForTransfer+0x148>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005c82: 687b ldr r3, [r7, #4]
8005c84: 6bdb ldr r3, [r3, #60] ; 0x3c
8005c86: f043 0201 orr.w r2, r3, #1
8005c8a: 687b ldr r3, [r7, #4]
8005c8c: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005c8e: 687b ldr r3, [r7, #4]
8005c90: 681b ldr r3, [r3, #0]
8005c92: 2229 movs r2, #41 ; 0x29
8005c94: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_ERROR;
8005c96: 687b ldr r3, [r7, #4]
8005c98: 2204 movs r2, #4
8005c9a: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005c9e: 687b ldr r3, [r7, #4]
8005ca0: 2200 movs r2, #0
8005ca2: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005ca6: 2301 movs r3, #1
8005ca8: e032 b.n 8005d10 <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005caa: 683b ldr r3, [r7, #0]
8005cac: f1b3 3fff cmp.w r3, #4294967295
8005cb0: d01a beq.n 8005ce8 <HAL_DMA2D_PollForTransfer+0x1a2>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
8005cb2: f7fe fe75 bl 80049a0 <HAL_GetTick>
8005cb6: 4602 mov r2, r0
8005cb8: 697b ldr r3, [r7, #20]
8005cba: 1ad3 subs r3, r2, r3
8005cbc: 683a ldr r2, [r7, #0]
8005cbe: 429a cmp r2, r3
8005cc0: d302 bcc.n 8005cc8 <HAL_DMA2D_PollForTransfer+0x182>
8005cc2: 683b ldr r3, [r7, #0]
8005cc4: 2b00 cmp r3, #0
8005cc6: d10f bne.n 8005ce8 <HAL_DMA2D_PollForTransfer+0x1a2>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005cc8: 687b ldr r3, [r7, #4]
8005cca: 6bdb ldr r3, [r3, #60] ; 0x3c
8005ccc: f043 0220 orr.w r2, r3, #32
8005cd0: 687b ldr r3, [r7, #4]
8005cd2: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
8005cd4: 687b ldr r3, [r7, #4]
8005cd6: 2203 movs r2, #3
8005cd8: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005cdc: 687b ldr r3, [r7, #4]
8005cde: 2200 movs r2, #0
8005ce0: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005ce4: 2303 movs r3, #3
8005ce6: e013 b.n 8005d10 <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005ce8: 687b ldr r3, [r7, #4]
8005cea: 681b ldr r3, [r3, #0]
8005cec: 685b ldr r3, [r3, #4]
8005cee: f003 0310 and.w r3, r3, #16
8005cf2: 2b00 cmp r3, #0
8005cf4: d0a1 beq.n 8005c3a <HAL_DMA2D_PollForTransfer+0xf4>
}
}
}
/* Clear the transfer complete and CLUT loading flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
8005cf6: 687b ldr r3, [r7, #4]
8005cf8: 681b ldr r3, [r3, #0]
8005cfa: 2212 movs r2, #18
8005cfc: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8005cfe: 687b ldr r3, [r7, #4]
8005d00: 2201 movs r2, #1
8005d02: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005d06: 687b ldr r3, [r7, #4]
8005d08: 2200 movs r2, #0
8005d0a: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005d0e: 2300 movs r3, #0
}
8005d10: 4618 mov r0, r3
8005d12: 3718 adds r7, #24
8005d14: 46bd mov sp, r7
8005d16: bd80 pop {r7, pc}
08005d18 <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8005d18: b480 push {r7}
8005d1a: b087 sub sp, #28
8005d1c: af00 add r7, sp, #0
8005d1e: 6078 str r0, [r7, #4]
8005d20: 6039 str r1, [r7, #0]
uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
8005d22: 687b ldr r3, [r7, #4]
8005d24: 685b ldr r3, [r3, #4]
8005d26: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Process locked */
__HAL_LOCK(hdma2d);
8005d2a: 687b ldr r3, [r7, #4]
8005d2c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005d30: 2b01 cmp r3, #1
8005d32: d101 bne.n 8005d38 <HAL_DMA2D_ConfigLayer+0x20>
8005d34: 2302 movs r3, #2
8005d36: e079 b.n 8005e2c <HAL_DMA2D_ConfigLayer+0x114>
8005d38: 687b ldr r3, [r7, #4]
8005d3a: 2201 movs r2, #1
8005d3c: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005d40: 687b ldr r3, [r7, #4]
8005d42: 2202 movs r2, #2
8005d44: f883 2039 strb.w r2, [r3, #57] ; 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
8005d48: 683b ldr r3, [r7, #0]
8005d4a: 011b lsls r3, r3, #4
8005d4c: 3318 adds r3, #24
8005d4e: 687a ldr r2, [r7, #4]
8005d50: 4413 add r3, r2
8005d52: 613b str r3, [r7, #16]
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
#else
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
8005d54: 693b ldr r3, [r7, #16]
8005d56: 685a ldr r2, [r3, #4]
8005d58: 693b ldr r3, [r7, #16]
8005d5a: 689b ldr r3, [r3, #8]
8005d5c: 041b lsls r3, r3, #16
8005d5e: 4313 orrs r3, r2
8005d60: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
8005d62: 4b35 ldr r3, [pc, #212] ; (8005e38 <HAL_DMA2D_ConfigLayer+0x120>)
8005d64: 60fb str r3, [r7, #12]
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005d66: 693b ldr r3, [r7, #16]
8005d68: 685b ldr r3, [r3, #4]
8005d6a: 2b0a cmp r3, #10
8005d6c: d003 beq.n 8005d76 <HAL_DMA2D_ConfigLayer+0x5e>
8005d6e: 693b ldr r3, [r7, #16]
8005d70: 685b ldr r3, [r3, #4]
8005d72: 2b09 cmp r3, #9
8005d74: d107 bne.n 8005d86 <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
8005d76: 693b ldr r3, [r7, #16]
8005d78: 68db ldr r3, [r3, #12]
8005d7a: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005d7e: 697a ldr r2, [r7, #20]
8005d80: 4313 orrs r3, r2
8005d82: 617b str r3, [r7, #20]
8005d84: e005 b.n 8005d92 <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8005d86: 693b ldr r3, [r7, #16]
8005d88: 68db ldr r3, [r3, #12]
8005d8a: 061b lsls r3, r3, #24
8005d8c: 697a ldr r2, [r7, #20]
8005d8e: 4313 orrs r3, r2
8005d90: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
8005d92: 683b ldr r3, [r7, #0]
8005d94: 2b00 cmp r3, #0
8005d96: d120 bne.n 8005dda <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8005d98: 687b ldr r3, [r7, #4]
8005d9a: 681b ldr r3, [r3, #0]
8005d9c: 6a5a ldr r2, [r3, #36] ; 0x24
8005d9e: 68fb ldr r3, [r7, #12]
8005da0: 43db mvns r3, r3
8005da2: ea02 0103 and.w r1, r2, r3
8005da6: 687b ldr r3, [r7, #4]
8005da8: 681b ldr r3, [r3, #0]
8005daa: 697a ldr r2, [r7, #20]
8005dac: 430a orrs r2, r1
8005dae: 625a str r2, [r3, #36] ; 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
8005db0: 687b ldr r3, [r7, #4]
8005db2: 681b ldr r3, [r3, #0]
8005db4: 693a ldr r2, [r7, #16]
8005db6: 6812 ldr r2, [r2, #0]
8005db8: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005dba: 693b ldr r3, [r7, #16]
8005dbc: 685b ldr r3, [r3, #4]
8005dbe: 2b0a cmp r3, #10
8005dc0: d003 beq.n 8005dca <HAL_DMA2D_ConfigLayer+0xb2>
8005dc2: 693b ldr r3, [r7, #16]
8005dc4: 685b ldr r3, [r3, #4]
8005dc6: 2b09 cmp r3, #9
8005dc8: d127 bne.n 8005e1a <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
8005dca: 693b ldr r3, [r7, #16]
8005dcc: 68da ldr r2, [r3, #12]
8005dce: 687b ldr r3, [r7, #4]
8005dd0: 681b ldr r3, [r3, #0]
8005dd2: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005dd6: 629a str r2, [r3, #40] ; 0x28
8005dd8: e01f b.n 8005e1a <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8005dda: 687b ldr r3, [r7, #4]
8005ddc: 681b ldr r3, [r3, #0]
8005dde: 69da ldr r2, [r3, #28]
8005de0: 68fb ldr r3, [r7, #12]
8005de2: 43db mvns r3, r3
8005de4: ea02 0103 and.w r1, r2, r3
8005de8: 687b ldr r3, [r7, #4]
8005dea: 681b ldr r3, [r3, #0]
8005dec: 697a ldr r2, [r7, #20]
8005dee: 430a orrs r2, r1
8005df0: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
8005df2: 687b ldr r3, [r7, #4]
8005df4: 681b ldr r3, [r3, #0]
8005df6: 693a ldr r2, [r7, #16]
8005df8: 6812 ldr r2, [r2, #0]
8005dfa: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005dfc: 693b ldr r3, [r7, #16]
8005dfe: 685b ldr r3, [r3, #4]
8005e00: 2b0a cmp r3, #10
8005e02: d003 beq.n 8005e0c <HAL_DMA2D_ConfigLayer+0xf4>
8005e04: 693b ldr r3, [r7, #16]
8005e06: 685b ldr r3, [r3, #4]
8005e08: 2b09 cmp r3, #9
8005e0a: d106 bne.n 8005e1a <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
8005e0c: 693b ldr r3, [r7, #16]
8005e0e: 68da ldr r2, [r3, #12]
8005e10: 687b ldr r3, [r7, #4]
8005e12: 681b ldr r3, [r3, #0]
8005e14: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005e18: 621a str r2, [r3, #32]
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005e1a: 687b ldr r3, [r7, #4]
8005e1c: 2201 movs r2, #1
8005e1e: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005e22: 687b ldr r3, [r7, #4]
8005e24: 2200 movs r2, #0
8005e26: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8005e2a: 2300 movs r3, #0
}
8005e2c: 4618 mov r0, r3
8005e2e: 371c adds r7, #28
8005e30: 46bd mov sp, r7
8005e32: f85d 7b04 ldr.w r7, [sp], #4
8005e36: 4770 bx lr
8005e38: ff03000f .word 0xff03000f
08005e3c <DMA2D_SetConfig>:
* @param Width The width of data to be transferred from source to destination.
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
8005e3c: b480 push {r7}
8005e3e: b08b sub sp, #44 ; 0x2c
8005e40: af00 add r7, sp, #0
8005e42: 60f8 str r0, [r7, #12]
8005e44: 60b9 str r1, [r7, #8]
8005e46: 607a str r2, [r7, #4]
8005e48: 603b str r3, [r7, #0]
uint32_t tmp2;
uint32_t tmp3;
uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
8005e4a: 68fb ldr r3, [r7, #12]
8005e4c: 681b ldr r3, [r3, #0]
8005e4e: 6c5b ldr r3, [r3, #68] ; 0x44
8005e50: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
8005e54: 683b ldr r3, [r7, #0]
8005e56: 041a lsls r2, r3, #16
8005e58: 6b3b ldr r3, [r7, #48] ; 0x30
8005e5a: 431a orrs r2, r3
8005e5c: 68fb ldr r3, [r7, #12]
8005e5e: 681b ldr r3, [r3, #0]
8005e60: 430a orrs r2, r1
8005e62: 645a str r2, [r3, #68] ; 0x44
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
8005e64: 68fb ldr r3, [r7, #12]
8005e66: 681b ldr r3, [r3, #0]
8005e68: 687a ldr r2, [r7, #4]
8005e6a: 63da str r2, [r3, #60] ; 0x3c
/* Register to memory DMA2D mode selected */
if (hdma2d->Init.Mode == DMA2D_R2M)
8005e6c: 68fb ldr r3, [r7, #12]
8005e6e: 685b ldr r3, [r3, #4]
8005e70: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
8005e74: d174 bne.n 8005f60 <DMA2D_SetConfig+0x124>
{
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
8005e76: 68bb ldr r3, [r7, #8]
8005e78: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8005e7c: 623b str r3, [r7, #32]
tmp2 = pdata & DMA2D_OCOLR_RED_1;
8005e7e: 68bb ldr r3, [r7, #8]
8005e80: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8005e84: 61fb str r3, [r7, #28]
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
8005e86: 68bb ldr r3, [r7, #8]
8005e88: f403 437f and.w r3, r3, #65280 ; 0xff00
8005e8c: 61bb str r3, [r7, #24]
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
8005e8e: 68bb ldr r3, [r7, #8]
8005e90: b2db uxtb r3, r3
8005e92: 617b str r3, [r7, #20]
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
8005e94: 68fb ldr r3, [r7, #12]
8005e96: 689b ldr r3, [r3, #8]
8005e98: 2b00 cmp r3, #0
8005e9a: d108 bne.n 8005eae <DMA2D_SetConfig+0x72>
{
tmp = (tmp3 | tmp2 | tmp1| tmp4);
8005e9c: 69ba ldr r2, [r7, #24]
8005e9e: 69fb ldr r3, [r7, #28]
8005ea0: 431a orrs r2, r3
8005ea2: 6a3b ldr r3, [r7, #32]
8005ea4: 4313 orrs r3, r2
8005ea6: 697a ldr r2, [r7, #20]
8005ea8: 4313 orrs r3, r2
8005eaa: 627b str r3, [r7, #36] ; 0x24
8005eac: e053 b.n 8005f56 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
8005eae: 68fb ldr r3, [r7, #12]
8005eb0: 689b ldr r3, [r3, #8]
8005eb2: 2b01 cmp r3, #1
8005eb4: d106 bne.n 8005ec4 <DMA2D_SetConfig+0x88>
{
tmp = (tmp3 | tmp2 | tmp4);
8005eb6: 69ba ldr r2, [r7, #24]
8005eb8: 69fb ldr r3, [r7, #28]
8005eba: 4313 orrs r3, r2
8005ebc: 697a ldr r2, [r7, #20]
8005ebe: 4313 orrs r3, r2
8005ec0: 627b str r3, [r7, #36] ; 0x24
8005ec2: e048 b.n 8005f56 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
8005ec4: 68fb ldr r3, [r7, #12]
8005ec6: 689b ldr r3, [r3, #8]
8005ec8: 2b02 cmp r3, #2
8005eca: d111 bne.n 8005ef0 <DMA2D_SetConfig+0xb4>
{
tmp2 = (tmp2 >> 19U);
8005ecc: 69fb ldr r3, [r7, #28]
8005ece: 0cdb lsrs r3, r3, #19
8005ed0: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 10U);
8005ed2: 69bb ldr r3, [r7, #24]
8005ed4: 0a9b lsrs r3, r3, #10
8005ed6: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005ed8: 697b ldr r3, [r7, #20]
8005eda: 08db lsrs r3, r3, #3
8005edc: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
8005ede: 69bb ldr r3, [r7, #24]
8005ee0: 015a lsls r2, r3, #5
8005ee2: 69fb ldr r3, [r7, #28]
8005ee4: 02db lsls r3, r3, #11
8005ee6: 4313 orrs r3, r2
8005ee8: 697a ldr r2, [r7, #20]
8005eea: 4313 orrs r3, r2
8005eec: 627b str r3, [r7, #36] ; 0x24
8005eee: e032 b.n 8005f56 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
8005ef0: 68fb ldr r3, [r7, #12]
8005ef2: 689b ldr r3, [r3, #8]
8005ef4: 2b03 cmp r3, #3
8005ef6: d117 bne.n 8005f28 <DMA2D_SetConfig+0xec>
{
tmp1 = (tmp1 >> 31U);
8005ef8: 6a3b ldr r3, [r7, #32]
8005efa: 0fdb lsrs r3, r3, #31
8005efc: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 19U);
8005efe: 69fb ldr r3, [r7, #28]
8005f00: 0cdb lsrs r3, r3, #19
8005f02: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 11U);
8005f04: 69bb ldr r3, [r7, #24]
8005f06: 0adb lsrs r3, r3, #11
8005f08: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005f0a: 697b ldr r3, [r7, #20]
8005f0c: 08db lsrs r3, r3, #3
8005f0e: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
8005f10: 69bb ldr r3, [r7, #24]
8005f12: 015a lsls r2, r3, #5
8005f14: 69fb ldr r3, [r7, #28]
8005f16: 029b lsls r3, r3, #10
8005f18: 431a orrs r2, r3
8005f1a: 6a3b ldr r3, [r7, #32]
8005f1c: 03db lsls r3, r3, #15
8005f1e: 4313 orrs r3, r2
8005f20: 697a ldr r2, [r7, #20]
8005f22: 4313 orrs r3, r2
8005f24: 627b str r3, [r7, #36] ; 0x24
8005f26: e016 b.n 8005f56 <DMA2D_SetConfig+0x11a>
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
tmp1 = (tmp1 >> 28U);
8005f28: 6a3b ldr r3, [r7, #32]
8005f2a: 0f1b lsrs r3, r3, #28
8005f2c: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 20U);
8005f2e: 69fb ldr r3, [r7, #28]
8005f30: 0d1b lsrs r3, r3, #20
8005f32: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 12U);
8005f34: 69bb ldr r3, [r7, #24]
8005f36: 0b1b lsrs r3, r3, #12
8005f38: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 4U );
8005f3a: 697b ldr r3, [r7, #20]
8005f3c: 091b lsrs r3, r3, #4
8005f3e: 617b str r3, [r7, #20]
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
8005f40: 69bb ldr r3, [r7, #24]
8005f42: 011a lsls r2, r3, #4
8005f44: 69fb ldr r3, [r7, #28]
8005f46: 021b lsls r3, r3, #8
8005f48: 431a orrs r2, r3
8005f4a: 6a3b ldr r3, [r7, #32]
8005f4c: 031b lsls r3, r3, #12
8005f4e: 4313 orrs r3, r2
8005f50: 697a ldr r2, [r7, #20]
8005f52: 4313 orrs r3, r2
8005f54: 627b str r3, [r7, #36] ; 0x24
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
8005f56: 68fb ldr r3, [r7, #12]
8005f58: 681b ldr r3, [r3, #0]
8005f5a: 6a7a ldr r2, [r7, #36] ; 0x24
8005f5c: 639a str r2, [r3, #56] ; 0x38
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
}
}
8005f5e: e003 b.n 8005f68 <DMA2D_SetConfig+0x12c>
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
8005f60: 68fb ldr r3, [r7, #12]
8005f62: 681b ldr r3, [r3, #0]
8005f64: 68ba ldr r2, [r7, #8]
8005f66: 60da str r2, [r3, #12]
}
8005f68: bf00 nop
8005f6a: 372c adds r7, #44 ; 0x2c
8005f6c: 46bd mov sp, r7
8005f6e: f85d 7b04 ldr.w r7, [sp], #4
8005f72: 4770 bx lr
08005f74 <HAL_ETH_Init>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
8005f74: b580 push {r7, lr}
8005f76: b088 sub sp, #32
8005f78: af00 add r7, sp, #0
8005f7a: 6078 str r0, [r7, #4]
uint32_t tempreg = 0, phyreg = 0;
8005f7c: 2300 movs r3, #0
8005f7e: 61fb str r3, [r7, #28]
8005f80: 2300 movs r3, #0
8005f82: 60fb str r3, [r7, #12]
uint32_t hclk = 60000000;
8005f84: 4ba9 ldr r3, [pc, #676] ; (800622c <HAL_ETH_Init+0x2b8>)
8005f86: 61bb str r3, [r7, #24]
uint32_t tickstart = 0;
8005f88: 2300 movs r3, #0
8005f8a: 617b str r3, [r7, #20]
uint32_t err = ETH_SUCCESS;
8005f8c: 2300 movs r3, #0
8005f8e: 613b str r3, [r7, #16]
/* Check the ETH peripheral state */
if(heth == NULL)
8005f90: 687b ldr r3, [r7, #4]
8005f92: 2b00 cmp r3, #0
8005f94: d101 bne.n 8005f9a <HAL_ETH_Init+0x26>
{
return HAL_ERROR;
8005f96: 2301 movs r3, #1
8005f98: e183 b.n 80062a2 <HAL_ETH_Init+0x32e>
assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
if(heth->State == HAL_ETH_STATE_RESET)
8005f9a: 687b ldr r3, [r7, #4]
8005f9c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8005fa0: b2db uxtb r3, r3
8005fa2: 2b00 cmp r3, #0
8005fa4: d106 bne.n 8005fb4 <HAL_ETH_Init+0x40>
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
8005fa6: 687b ldr r3, [r7, #4]
8005fa8: 2200 movs r2, #0
8005faa: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
heth->MspInitCallback(heth);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
8005fae: 6878 ldr r0, [r7, #4]
8005fb0: f005 f8e2 bl 800b178 <HAL_ETH_MspInit>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8005fb4: 4b9e ldr r3, [pc, #632] ; (8006230 <HAL_ETH_Init+0x2bc>)
8005fb6: 6c5b ldr r3, [r3, #68] ; 0x44
8005fb8: 4a9d ldr r2, [pc, #628] ; (8006230 <HAL_ETH_Init+0x2bc>)
8005fba: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8005fbe: 6453 str r3, [r2, #68] ; 0x44
8005fc0: 4b9b ldr r3, [pc, #620] ; (8006230 <HAL_ETH_Init+0x2bc>)
8005fc2: 6c5b ldr r3, [r3, #68] ; 0x44
8005fc4: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005fc8: 60bb str r3, [r7, #8]
8005fca: 68bb ldr r3, [r7, #8]
/* Select MII or RMII Mode*/
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
8005fcc: 4b99 ldr r3, [pc, #612] ; (8006234 <HAL_ETH_Init+0x2c0>)
8005fce: 685b ldr r3, [r3, #4]
8005fd0: 4a98 ldr r2, [pc, #608] ; (8006234 <HAL_ETH_Init+0x2c0>)
8005fd2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8005fd6: 6053 str r3, [r2, #4]
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
8005fd8: 4b96 ldr r3, [pc, #600] ; (8006234 <HAL_ETH_Init+0x2c0>)
8005fda: 685a ldr r2, [r3, #4]
8005fdc: 687b ldr r3, [r7, #4]
8005fde: 6a1b ldr r3, [r3, #32]
8005fe0: 4994 ldr r1, [pc, #592] ; (8006234 <HAL_ETH_Init+0x2c0>)
8005fe2: 4313 orrs r3, r2
8005fe4: 604b str r3, [r1, #4]
/* Ethernet Software reset */
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
8005fe6: 687b ldr r3, [r7, #4]
8005fe8: 681b ldr r3, [r3, #0]
8005fea: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005fee: 681a ldr r2, [r3, #0]
8005ff0: 687b ldr r3, [r7, #4]
8005ff2: 681b ldr r3, [r3, #0]
8005ff4: f042 0201 orr.w r2, r2, #1
8005ff8: f503 5380 add.w r3, r3, #4096 ; 0x1000
8005ffc: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8005ffe: f7fe fccf bl 80049a0 <HAL_GetTick>
8006002: 6178 str r0, [r7, #20]
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
8006004: e011 b.n 800602a <HAL_ETH_Init+0xb6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
8006006: f7fe fccb bl 80049a0 <HAL_GetTick>
800600a: 4602 mov r2, r0
800600c: 697b ldr r3, [r7, #20]
800600e: 1ad3 subs r3, r2, r3
8006010: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
8006014: d909 bls.n 800602a <HAL_ETH_Init+0xb6>
{
heth->State= HAL_ETH_STATE_TIMEOUT;
8006016: 687b ldr r3, [r7, #4]
8006018: 2203 movs r2, #3
800601a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800601e: 687b ldr r3, [r7, #4]
8006020: 2200 movs r2, #0
8006022: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
not available, please check your external PHY or the IO configuration */
return HAL_TIMEOUT;
8006026: 2303 movs r3, #3
8006028: e13b b.n 80062a2 <HAL_ETH_Init+0x32e>
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
800602a: 687b ldr r3, [r7, #4]
800602c: 681b ldr r3, [r3, #0]
800602e: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006032: 681b ldr r3, [r3, #0]
8006034: f003 0301 and.w r3, r3, #1
8006038: 2b00 cmp r3, #0
800603a: d1e4 bne.n 8006006 <HAL_ETH_Init+0x92>
}
}
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
tempreg = (heth->Instance)->MACMIIAR;
800603c: 687b ldr r3, [r7, #4]
800603e: 681b ldr r3, [r3, #0]
8006040: 691b ldr r3, [r3, #16]
8006042: 61fb str r3, [r7, #28]
/* Clear CSR Clock Range CR[2:0] bits */
tempreg &= ETH_MACMIIAR_CR_MASK;
8006044: 69fb ldr r3, [r7, #28]
8006046: f023 031c bic.w r3, r3, #28
800604a: 61fb str r3, [r7, #28]
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
800604c: f003 f854 bl 80090f8 <HAL_RCC_GetHCLKFreq>
8006050: 61b8 str r0, [r7, #24]
/* Set CR bits depending on hclk value */
if((hclk >= 20000000)&&(hclk < 35000000))
8006052: 69bb ldr r3, [r7, #24]
8006054: 4a78 ldr r2, [pc, #480] ; (8006238 <HAL_ETH_Init+0x2c4>)
8006056: 4293 cmp r3, r2
8006058: d908 bls.n 800606c <HAL_ETH_Init+0xf8>
800605a: 69bb ldr r3, [r7, #24]
800605c: 4a77 ldr r2, [pc, #476] ; (800623c <HAL_ETH_Init+0x2c8>)
800605e: 4293 cmp r3, r2
8006060: d804 bhi.n 800606c <HAL_ETH_Init+0xf8>
{
/* CSR Clock Range between 20-35 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
8006062: 69fb ldr r3, [r7, #28]
8006064: f043 0308 orr.w r3, r3, #8
8006068: 61fb str r3, [r7, #28]
800606a: e027 b.n 80060bc <HAL_ETH_Init+0x148>
}
else if((hclk >= 35000000)&&(hclk < 60000000))
800606c: 69bb ldr r3, [r7, #24]
800606e: 4a73 ldr r2, [pc, #460] ; (800623c <HAL_ETH_Init+0x2c8>)
8006070: 4293 cmp r3, r2
8006072: d908 bls.n 8006086 <HAL_ETH_Init+0x112>
8006074: 69bb ldr r3, [r7, #24]
8006076: 4a72 ldr r2, [pc, #456] ; (8006240 <HAL_ETH_Init+0x2cc>)
8006078: 4293 cmp r3, r2
800607a: d804 bhi.n 8006086 <HAL_ETH_Init+0x112>
{
/* CSR Clock Range between 35-60 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
800607c: 69fb ldr r3, [r7, #28]
800607e: f043 030c orr.w r3, r3, #12
8006082: 61fb str r3, [r7, #28]
8006084: e01a b.n 80060bc <HAL_ETH_Init+0x148>
}
else if((hclk >= 60000000)&&(hclk < 100000000))
8006086: 69bb ldr r3, [r7, #24]
8006088: 4a6d ldr r2, [pc, #436] ; (8006240 <HAL_ETH_Init+0x2cc>)
800608a: 4293 cmp r3, r2
800608c: d903 bls.n 8006096 <HAL_ETH_Init+0x122>
800608e: 69bb ldr r3, [r7, #24]
8006090: 4a6c ldr r2, [pc, #432] ; (8006244 <HAL_ETH_Init+0x2d0>)
8006092: 4293 cmp r3, r2
8006094: d911 bls.n 80060ba <HAL_ETH_Init+0x146>
{
/* CSR Clock Range between 60-100 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
}
else if((hclk >= 100000000)&&(hclk < 150000000))
8006096: 69bb ldr r3, [r7, #24]
8006098: 4a6a ldr r2, [pc, #424] ; (8006244 <HAL_ETH_Init+0x2d0>)
800609a: 4293 cmp r3, r2
800609c: d908 bls.n 80060b0 <HAL_ETH_Init+0x13c>
800609e: 69bb ldr r3, [r7, #24]
80060a0: 4a69 ldr r2, [pc, #420] ; (8006248 <HAL_ETH_Init+0x2d4>)
80060a2: 4293 cmp r3, r2
80060a4: d804 bhi.n 80060b0 <HAL_ETH_Init+0x13c>
{
/* CSR Clock Range between 100-150 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
80060a6: 69fb ldr r3, [r7, #28]
80060a8: f043 0304 orr.w r3, r3, #4
80060ac: 61fb str r3, [r7, #28]
80060ae: e005 b.n 80060bc <HAL_ETH_Init+0x148>
}
else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
{
/* CSR Clock Range between 150-216 MHz */
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
80060b0: 69fb ldr r3, [r7, #28]
80060b2: f043 0310 orr.w r3, r3, #16
80060b6: 61fb str r3, [r7, #28]
80060b8: e000 b.n 80060bc <HAL_ETH_Init+0x148>
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
80060ba: bf00 nop
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
(heth->Instance)->MACMIIAR = (uint32_t)tempreg;
80060bc: 687b ldr r3, [r7, #4]
80060be: 681b ldr r3, [r3, #0]
80060c0: 69fa ldr r2, [r7, #28]
80060c2: 611a str r2, [r3, #16]
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
80060c4: f44f 4200 mov.w r2, #32768 ; 0x8000
80060c8: 2100 movs r1, #0
80060ca: 6878 ldr r0, [r7, #4]
80060cc: f000 fc19 bl 8006902 <HAL_ETH_WritePHYRegister>
80060d0: 4603 mov r3, r0
80060d2: 2b00 cmp r3, #0
80060d4: d00b beq.n 80060ee <HAL_ETH_Init+0x17a>
{
/* In case of write timeout */
err = ETH_ERROR;
80060d6: 2301 movs r3, #1
80060d8: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80060da: 6939 ldr r1, [r7, #16]
80060dc: 6878 ldr r0, [r7, #4]
80060de: f000 fdcf bl 8006c80 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
80060e2: 687b ldr r3, [r7, #4]
80060e4: 2201 movs r2, #1
80060e6: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
80060ea: 2301 movs r3, #1
80060ec: e0d9 b.n 80062a2 <HAL_ETH_Init+0x32e>
}
/* Delay to assure PHY reset */
HAL_Delay(PHY_RESET_DELAY);
80060ee: 20ff movs r0, #255 ; 0xff
80060f0: f7fe fc62 bl 80049b8 <HAL_Delay>
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
80060f4: 687b ldr r3, [r7, #4]
80060f6: 685b ldr r3, [r3, #4]
80060f8: 2b00 cmp r3, #0
80060fa: f000 80a7 beq.w 800624c <HAL_ETH_Init+0x2d8>
{
/* Get tick */
tickstart = HAL_GetTick();
80060fe: f7fe fc4f bl 80049a0 <HAL_GetTick>
8006102: 6178 str r0, [r7, #20]
/* We wait for linked status */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
8006104: f107 030c add.w r3, r7, #12
8006108: 461a mov r2, r3
800610a: 2101 movs r1, #1
800610c: 6878 ldr r0, [r7, #4]
800610e: f000 fb90 bl 8006832 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
8006112: f7fe fc45 bl 80049a0 <HAL_GetTick>
8006116: 4602 mov r2, r0
8006118: 697b ldr r3, [r7, #20]
800611a: 1ad3 subs r3, r2, r3
800611c: f241 3288 movw r2, #5000 ; 0x1388
8006120: 4293 cmp r3, r2
8006122: d90f bls.n 8006144 <HAL_ETH_Init+0x1d0>
{
/* In case of write timeout */
err = ETH_ERROR;
8006124: 2301 movs r3, #1
8006126: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006128: 6939 ldr r1, [r7, #16]
800612a: 6878 ldr r0, [r7, #4]
800612c: f000 fda8 bl 8006c80 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
8006130: 687b ldr r3, [r7, #4]
8006132: 2201 movs r2, #1
8006134: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006138: 687b ldr r3, [r7, #4]
800613a: 2200 movs r2, #0
800613c: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
8006140: 2303 movs r3, #3
8006142: e0ae b.n 80062a2 <HAL_ETH_Init+0x32e>
}
} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
8006144: 68fb ldr r3, [r7, #12]
8006146: f003 0304 and.w r3, r3, #4
800614a: 2b00 cmp r3, #0
800614c: d0da beq.n 8006104 <HAL_ETH_Init+0x190>
/* Enable Auto-Negotiation */
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
800614e: f44f 5280 mov.w r2, #4096 ; 0x1000
8006152: 2100 movs r1, #0
8006154: 6878 ldr r0, [r7, #4]
8006156: f000 fbd4 bl 8006902 <HAL_ETH_WritePHYRegister>
800615a: 4603 mov r3, r0
800615c: 2b00 cmp r3, #0
800615e: d00b beq.n 8006178 <HAL_ETH_Init+0x204>
{
/* In case of write timeout */
err = ETH_ERROR;
8006160: 2301 movs r3, #1
8006162: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006164: 6939 ldr r1, [r7, #16]
8006166: 6878 ldr r0, [r7, #4]
8006168: f000 fd8a bl 8006c80 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
800616c: 687b ldr r3, [r7, #4]
800616e: 2201 movs r2, #1
8006170: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8006174: 2301 movs r3, #1
8006176: e094 b.n 80062a2 <HAL_ETH_Init+0x32e>
}
/* Get tick */
tickstart = HAL_GetTick();
8006178: f7fe fc12 bl 80049a0 <HAL_GetTick>
800617c: 6178 str r0, [r7, #20]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
800617e: f107 030c add.w r3, r7, #12
8006182: 461a mov r2, r3
8006184: 2101 movs r1, #1
8006186: 6878 ldr r0, [r7, #4]
8006188: f000 fb53 bl 8006832 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
800618c: f7fe fc08 bl 80049a0 <HAL_GetTick>
8006190: 4602 mov r2, r0
8006192: 697b ldr r3, [r7, #20]
8006194: 1ad3 subs r3, r2, r3
8006196: f241 3288 movw r2, #5000 ; 0x1388
800619a: 4293 cmp r3, r2
800619c: d90f bls.n 80061be <HAL_ETH_Init+0x24a>
{
/* In case of write timeout */
err = ETH_ERROR;
800619e: 2301 movs r3, #1
80061a0: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80061a2: 6939 ldr r1, [r7, #16]
80061a4: 6878 ldr r0, [r7, #4]
80061a6: f000 fd6b bl 8006c80 <ETH_MACDMAConfig>
heth->State= HAL_ETH_STATE_READY;
80061aa: 687b ldr r3, [r7, #4]
80061ac: 2201 movs r2, #1
80061ae: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80061b2: 687b ldr r3, [r7, #4]
80061b4: 2200 movs r2, #0
80061b6: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
80061ba: 2303 movs r3, #3
80061bc: e071 b.n 80062a2 <HAL_ETH_Init+0x32e>
}
} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
80061be: 68fb ldr r3, [r7, #12]
80061c0: f003 0320 and.w r3, r3, #32
80061c4: 2b00 cmp r3, #0
80061c6: d0da beq.n 800617e <HAL_ETH_Init+0x20a>
/* Read the result of the auto-negotiation */
if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
80061c8: f107 030c add.w r3, r7, #12
80061cc: 461a mov r2, r3
80061ce: 211f movs r1, #31
80061d0: 6878 ldr r0, [r7, #4]
80061d2: f000 fb2e bl 8006832 <HAL_ETH_ReadPHYRegister>
80061d6: 4603 mov r3, r0
80061d8: 2b00 cmp r3, #0
80061da: d00b beq.n 80061f4 <HAL_ETH_Init+0x280>
{
/* In case of write timeout */
err = ETH_ERROR;
80061dc: 2301 movs r3, #1
80061de: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
80061e0: 6939 ldr r1, [r7, #16]
80061e2: 6878 ldr r0, [r7, #4]
80061e4: f000 fd4c bl 8006c80 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
80061e8: 687b ldr r3, [r7, #4]
80061ea: 2201 movs r2, #1
80061ec: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
80061f0: 2301 movs r3, #1
80061f2: e056 b.n 80062a2 <HAL_ETH_Init+0x32e>
}
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
80061f4: 68fb ldr r3, [r7, #12]
80061f6: f003 0310 and.w r3, r3, #16
80061fa: 2b00 cmp r3, #0
80061fc: d004 beq.n 8006208 <HAL_ETH_Init+0x294>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
80061fe: 687b ldr r3, [r7, #4]
8006200: f44f 6200 mov.w r2, #2048 ; 0x800
8006204: 60da str r2, [r3, #12]
8006206: e002 b.n 800620e <HAL_ETH_Init+0x29a>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
8006208: 687b ldr r3, [r7, #4]
800620a: 2200 movs r2, #0
800620c: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
800620e: 68fb ldr r3, [r7, #12]
8006210: f003 0304 and.w r3, r3, #4
8006214: 2b00 cmp r3, #0
8006216: d003 beq.n 8006220 <HAL_ETH_Init+0x2ac>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_10M;
8006218: 687b ldr r3, [r7, #4]
800621a: 2200 movs r2, #0
800621c: 609a str r2, [r3, #8]
800621e: e037 b.n 8006290 <HAL_ETH_Init+0x31c>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
(heth->Init).Speed = ETH_SPEED_100M;
8006220: 687b ldr r3, [r7, #4]
8006222: f44f 4280 mov.w r2, #16384 ; 0x4000
8006226: 609a str r2, [r3, #8]
8006228: e032 b.n 8006290 <HAL_ETH_Init+0x31c>
800622a: bf00 nop
800622c: 03938700 .word 0x03938700
8006230: 40023800 .word 0x40023800
8006234: 40013800 .word 0x40013800
8006238: 01312cff .word 0x01312cff
800623c: 02160ebf .word 0x02160ebf
8006240: 039386ff .word 0x039386ff
8006244: 05f5e0ff .word 0x05f5e0ff
8006248: 08f0d17f .word 0x08f0d17f
/* Check parameters */
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
800624c: 687b ldr r3, [r7, #4]
800624e: 68db ldr r3, [r3, #12]
8006250: 08db lsrs r3, r3, #3
8006252: b29a uxth r2, r3
(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
8006254: 687b ldr r3, [r7, #4]
8006256: 689b ldr r3, [r3, #8]
8006258: 085b lsrs r3, r3, #1
800625a: b29b uxth r3, r3
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
800625c: 4313 orrs r3, r2
800625e: b29b uxth r3, r3
8006260: 461a mov r2, r3
8006262: 2100 movs r1, #0
8006264: 6878 ldr r0, [r7, #4]
8006266: f000 fb4c bl 8006902 <HAL_ETH_WritePHYRegister>
800626a: 4603 mov r3, r0
800626c: 2b00 cmp r3, #0
800626e: d00b beq.n 8006288 <HAL_ETH_Init+0x314>
{
/* In case of write timeout */
err = ETH_ERROR;
8006270: 2301 movs r3, #1
8006272: 613b str r3, [r7, #16]
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006274: 6939 ldr r1, [r7, #16]
8006276: 6878 ldr r0, [r7, #4]
8006278: f000 fd02 bl 8006c80 <ETH_MACDMAConfig>
/* Set the ETH peripheral state to READY */
heth->State = HAL_ETH_STATE_READY;
800627c: 687b ldr r3, [r7, #4]
800627e: 2201 movs r2, #1
8006280: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return HAL_ERROR */
return HAL_ERROR;
8006284: 2301 movs r3, #1
8006286: e00c b.n 80062a2 <HAL_ETH_Init+0x32e>
}
/* Delay to assure PHY configuration */
HAL_Delay(PHY_CONFIG_DELAY);
8006288: f640 70ff movw r0, #4095 ; 0xfff
800628c: f7fe fb94 bl 80049b8 <HAL_Delay>
}
/* Config MAC and DMA */
ETH_MACDMAConfig(heth, err);
8006290: 6939 ldr r1, [r7, #16]
8006292: 6878 ldr r0, [r7, #4]
8006294: f000 fcf4 bl 8006c80 <ETH_MACDMAConfig>
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006298: 687b ldr r3, [r7, #4]
800629a: 2201 movs r2, #1
800629c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
80062a0: 2300 movs r3, #0
}
80062a2: 4618 mov r0, r3
80062a4: 3720 adds r7, #32
80062a6: 46bd mov sp, r7
80062a8: bd80 pop {r7, pc}
80062aa: bf00 nop
080062ac <HAL_ETH_DMATxDescListInit>:
* @param TxBuff Pointer to the first TxBuffer list
* @param TxBuffCount Number of the used Tx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
{
80062ac: b480 push {r7}
80062ae: b087 sub sp, #28
80062b0: af00 add r7, sp, #0
80062b2: 60f8 str r0, [r7, #12]
80062b4: 60b9 str r1, [r7, #8]
80062b6: 607a str r2, [r7, #4]
80062b8: 603b str r3, [r7, #0]
uint32_t i = 0;
80062ba: 2300 movs r3, #0
80062bc: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *dmatxdesc;
/* Process Locked */
__HAL_LOCK(heth);
80062be: 68fb ldr r3, [r7, #12]
80062c0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80062c4: 2b01 cmp r3, #1
80062c6: d101 bne.n 80062cc <HAL_ETH_DMATxDescListInit+0x20>
80062c8: 2302 movs r3, #2
80062ca: e052 b.n 8006372 <HAL_ETH_DMATxDescListInit+0xc6>
80062cc: 68fb ldr r3, [r7, #12]
80062ce: 2201 movs r2, #1
80062d0: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80062d4: 68fb ldr r3, [r7, #12]
80062d6: 2202 movs r2, #2
80062d8: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
heth->TxDesc = DMATxDescTab;
80062dc: 68fb ldr r3, [r7, #12]
80062de: 68ba ldr r2, [r7, #8]
80062e0: 62da str r2, [r3, #44] ; 0x2c
/* Fill each DMATxDesc descriptor with the right values */
for(i=0; i < TxBuffCount; i++)
80062e2: 2300 movs r3, #0
80062e4: 617b str r3, [r7, #20]
80062e6: e030 b.n 800634a <HAL_ETH_DMATxDescListInit+0x9e>
{
/* Get the pointer on the ith member of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
80062e8: 697b ldr r3, [r7, #20]
80062ea: 015b lsls r3, r3, #5
80062ec: 68ba ldr r2, [r7, #8]
80062ee: 4413 add r3, r2
80062f0: 613b str r3, [r7, #16]
/* Set Second Address Chained bit */
dmatxdesc->Status = ETH_DMATXDESC_TCH;
80062f2: 693b ldr r3, [r7, #16]
80062f4: f44f 1280 mov.w r2, #1048576 ; 0x100000
80062f8: 601a str r2, [r3, #0]
/* Set Buffer1 address pointer */
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
80062fa: 697b ldr r3, [r7, #20]
80062fc: f240 52f4 movw r2, #1524 ; 0x5f4
8006300: fb02 f303 mul.w r3, r2, r3
8006304: 687a ldr r2, [r7, #4]
8006306: 4413 add r3, r2
8006308: 461a mov r2, r3
800630a: 693b ldr r3, [r7, #16]
800630c: 609a str r2, [r3, #8]
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
800630e: 68fb ldr r3, [r7, #12]
8006310: 69db ldr r3, [r3, #28]
8006312: 2b00 cmp r3, #0
8006314: d105 bne.n 8006322 <HAL_ETH_DMATxDescListInit+0x76>
{
/* Set the DMA Tx descriptors checksum insertion */
dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
8006316: 693b ldr r3, [r7, #16]
8006318: 681b ldr r3, [r3, #0]
800631a: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000
800631e: 693b ldr r3, [r7, #16]
8006320: 601a str r2, [r3, #0]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (TxBuffCount-1))
8006322: 683b ldr r3, [r7, #0]
8006324: 3b01 subs r3, #1
8006326: 697a ldr r2, [r7, #20]
8006328: 429a cmp r2, r3
800632a: d208 bcs.n 800633e <HAL_ETH_DMATxDescListInit+0x92>
{
/* Set next descriptor address register with next descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
800632c: 697b ldr r3, [r7, #20]
800632e: 3301 adds r3, #1
8006330: 015b lsls r3, r3, #5
8006332: 68ba ldr r2, [r7, #8]
8006334: 4413 add r3, r2
8006336: 461a mov r2, r3
8006338: 693b ldr r3, [r7, #16]
800633a: 60da str r2, [r3, #12]
800633c: e002 b.n 8006344 <HAL_ETH_DMATxDescListInit+0x98>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
800633e: 68ba ldr r2, [r7, #8]
8006340: 693b ldr r3, [r7, #16]
8006342: 60da str r2, [r3, #12]
for(i=0; i < TxBuffCount; i++)
8006344: 697b ldr r3, [r7, #20]
8006346: 3301 adds r3, #1
8006348: 617b str r3, [r7, #20]
800634a: 697a ldr r2, [r7, #20]
800634c: 683b ldr r3, [r7, #0]
800634e: 429a cmp r2, r3
8006350: d3ca bcc.n 80062e8 <HAL_ETH_DMATxDescListInit+0x3c>
}
}
/* Set Transmit Descriptor List Address Register */
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
8006352: 68fb ldr r3, [r7, #12]
8006354: 6819 ldr r1, [r3, #0]
8006356: 68ba ldr r2, [r7, #8]
8006358: f241 0310 movw r3, #4112 ; 0x1010
800635c: 440b add r3, r1
800635e: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
8006360: 68fb ldr r3, [r7, #12]
8006362: 2201 movs r2, #1
8006364: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006368: 68fb ldr r3, [r7, #12]
800636a: 2200 movs r2, #0
800636c: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006370: 2300 movs r3, #0
}
8006372: 4618 mov r0, r3
8006374: 371c adds r7, #28
8006376: 46bd mov sp, r7
8006378: f85d 7b04 ldr.w r7, [sp], #4
800637c: 4770 bx lr
0800637e <HAL_ETH_DMARxDescListInit>:
* @param RxBuff Pointer to the first RxBuffer list
* @param RxBuffCount Number of the used Rx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
{
800637e: b480 push {r7}
8006380: b087 sub sp, #28
8006382: af00 add r7, sp, #0
8006384: 60f8 str r0, [r7, #12]
8006386: 60b9 str r1, [r7, #8]
8006388: 607a str r2, [r7, #4]
800638a: 603b str r3, [r7, #0]
uint32_t i = 0;
800638c: 2300 movs r3, #0
800638e: 617b str r3, [r7, #20]
ETH_DMADescTypeDef *DMARxDesc;
/* Process Locked */
__HAL_LOCK(heth);
8006390: 68fb ldr r3, [r7, #12]
8006392: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006396: 2b01 cmp r3, #1
8006398: d101 bne.n 800639e <HAL_ETH_DMARxDescListInit+0x20>
800639a: 2302 movs r3, #2
800639c: e056 b.n 800644c <HAL_ETH_DMARxDescListInit+0xce>
800639e: 68fb ldr r3, [r7, #12]
80063a0: 2201 movs r2, #1
80063a2: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80063a6: 68fb ldr r3, [r7, #12]
80063a8: 2202 movs r2, #2
80063aa: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
heth->RxDesc = DMARxDescTab;
80063ae: 68fb ldr r3, [r7, #12]
80063b0: 68ba ldr r2, [r7, #8]
80063b2: 629a str r2, [r3, #40] ; 0x28
/* Fill each DMARxDesc descriptor with the right values */
for(i=0; i < RxBuffCount; i++)
80063b4: 2300 movs r3, #0
80063b6: 617b str r3, [r7, #20]
80063b8: e034 b.n 8006424 <HAL_ETH_DMARxDescListInit+0xa6>
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
80063ba: 697b ldr r3, [r7, #20]
80063bc: 015b lsls r3, r3, #5
80063be: 68ba ldr r2, [r7, #8]
80063c0: 4413 add r3, r2
80063c2: 613b str r3, [r7, #16]
/* Set Own bit of the Rx descriptor Status */
DMARxDesc->Status = ETH_DMARXDESC_OWN;
80063c4: 693b ldr r3, [r7, #16]
80063c6: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
80063ca: 601a str r2, [r3, #0]
/* Set Buffer1 size and Second Address Chained bit */
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
80063cc: 693b ldr r3, [r7, #16]
80063ce: f244 52f4 movw r2, #17908 ; 0x45f4
80063d2: 605a str r2, [r3, #4]
/* Set Buffer1 address pointer */
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
80063d4: 697b ldr r3, [r7, #20]
80063d6: f240 52f4 movw r2, #1524 ; 0x5f4
80063da: fb02 f303 mul.w r3, r2, r3
80063de: 687a ldr r2, [r7, #4]
80063e0: 4413 add r3, r2
80063e2: 461a mov r2, r3
80063e4: 693b ldr r3, [r7, #16]
80063e6: 609a str r2, [r3, #8]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
80063e8: 68fb ldr r3, [r7, #12]
80063ea: 699b ldr r3, [r3, #24]
80063ec: 2b01 cmp r3, #1
80063ee: d105 bne.n 80063fc <HAL_ETH_DMARxDescListInit+0x7e>
{
/* Enable Ethernet DMA Rx Descriptor interrupt */
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
80063f0: 693b ldr r3, [r7, #16]
80063f2: 685b ldr r3, [r3, #4]
80063f4: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
80063f8: 693b ldr r3, [r7, #16]
80063fa: 605a str r2, [r3, #4]
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
if(i < (RxBuffCount-1))
80063fc: 683b ldr r3, [r7, #0]
80063fe: 3b01 subs r3, #1
8006400: 697a ldr r2, [r7, #20]
8006402: 429a cmp r2, r3
8006404: d208 bcs.n 8006418 <HAL_ETH_DMARxDescListInit+0x9a>
{
/* Set next descriptor address register with next descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
8006406: 697b ldr r3, [r7, #20]
8006408: 3301 adds r3, #1
800640a: 015b lsls r3, r3, #5
800640c: 68ba ldr r2, [r7, #8]
800640e: 4413 add r3, r2
8006410: 461a mov r2, r3
8006412: 693b ldr r3, [r7, #16]
8006414: 60da str r2, [r3, #12]
8006416: e002 b.n 800641e <HAL_ETH_DMARxDescListInit+0xa0>
}
else
{
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
8006418: 68ba ldr r2, [r7, #8]
800641a: 693b ldr r3, [r7, #16]
800641c: 60da str r2, [r3, #12]
for(i=0; i < RxBuffCount; i++)
800641e: 697b ldr r3, [r7, #20]
8006420: 3301 adds r3, #1
8006422: 617b str r3, [r7, #20]
8006424: 697a ldr r2, [r7, #20]
8006426: 683b ldr r3, [r7, #0]
8006428: 429a cmp r2, r3
800642a: d3c6 bcc.n 80063ba <HAL_ETH_DMARxDescListInit+0x3c>
}
}
/* Set Receive Descriptor List Address Register */
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
800642c: 68fb ldr r3, [r7, #12]
800642e: 6819 ldr r1, [r3, #0]
8006430: 68ba ldr r2, [r7, #8]
8006432: f241 030c movw r3, #4108 ; 0x100c
8006436: 440b add r3, r1
8006438: 601a str r2, [r3, #0]
/* Set ETH HAL State to Ready */
heth->State= HAL_ETH_STATE_READY;
800643a: 68fb ldr r3, [r7, #12]
800643c: 2201 movs r2, #1
800643e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006442: 68fb ldr r3, [r7, #12]
8006444: 2200 movs r2, #0
8006446: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
800644a: 2300 movs r3, #0
}
800644c: 4618 mov r0, r3
800644e: 371c adds r7, #28
8006450: 46bd mov sp, r7
8006452: f85d 7b04 ldr.w r7, [sp], #4
8006456: 4770 bx lr
08006458 <HAL_ETH_TransmitFrame>:
* the configuration information for ETHERNET module
* @param FrameLength Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
8006458: b480 push {r7}
800645a: b087 sub sp, #28
800645c: af00 add r7, sp, #0
800645e: 6078 str r0, [r7, #4]
8006460: 6039 str r1, [r7, #0]
uint32_t bufcount = 0, size = 0, i = 0;
8006462: 2300 movs r3, #0
8006464: 617b str r3, [r7, #20]
8006466: 2300 movs r3, #0
8006468: 60fb str r3, [r7, #12]
800646a: 2300 movs r3, #0
800646c: 613b str r3, [r7, #16]
/* Process Locked */
__HAL_LOCK(heth);
800646e: 687b ldr r3, [r7, #4]
8006470: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006474: 2b01 cmp r3, #1
8006476: d101 bne.n 800647c <HAL_ETH_TransmitFrame+0x24>
8006478: 2302 movs r3, #2
800647a: e0cd b.n 8006618 <HAL_ETH_TransmitFrame+0x1c0>
800647c: 687b ldr r3, [r7, #4]
800647e: 2201 movs r2, #1
8006480: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006484: 687b ldr r3, [r7, #4]
8006486: 2202 movs r2, #2
8006488: f883 2044 strb.w r2, [r3, #68] ; 0x44
if (FrameLength == 0)
800648c: 683b ldr r3, [r7, #0]
800648e: 2b00 cmp r3, #0
8006490: d109 bne.n 80064a6 <HAL_ETH_TransmitFrame+0x4e>
{
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
8006492: 687b ldr r3, [r7, #4]
8006494: 2201 movs r2, #1
8006496: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800649a: 687b ldr r3, [r7, #4]
800649c: 2200 movs r2, #0
800649e: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
80064a2: 2301 movs r3, #1
80064a4: e0b8 b.n 8006618 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
80064a6: 687b ldr r3, [r7, #4]
80064a8: 6adb ldr r3, [r3, #44] ; 0x2c
80064aa: 681b ldr r3, [r3, #0]
80064ac: 2b00 cmp r3, #0
80064ae: da09 bge.n 80064c4 <HAL_ETH_TransmitFrame+0x6c>
{
/* OWN bit set */
heth->State = HAL_ETH_STATE_BUSY_TX;
80064b0: 687b ldr r3, [r7, #4]
80064b2: 2212 movs r2, #18
80064b4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80064b8: 687b ldr r3, [r7, #4]
80064ba: 2200 movs r2, #0
80064bc: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_ERROR;
80064c0: 2301 movs r3, #1
80064c2: e0a9 b.n 8006618 <HAL_ETH_TransmitFrame+0x1c0>
}
/* Get the number of needed Tx buffers for the current frame */
if (FrameLength > ETH_TX_BUF_SIZE)
80064c4: 683b ldr r3, [r7, #0]
80064c6: f240 52f4 movw r2, #1524 ; 0x5f4
80064ca: 4293 cmp r3, r2
80064cc: d915 bls.n 80064fa <HAL_ETH_TransmitFrame+0xa2>
{
bufcount = FrameLength/ETH_TX_BUF_SIZE;
80064ce: 683b ldr r3, [r7, #0]
80064d0: 4a54 ldr r2, [pc, #336] ; (8006624 <HAL_ETH_TransmitFrame+0x1cc>)
80064d2: fba2 2303 umull r2, r3, r2, r3
80064d6: 0a9b lsrs r3, r3, #10
80064d8: 617b str r3, [r7, #20]
if (FrameLength % ETH_TX_BUF_SIZE)
80064da: 683a ldr r2, [r7, #0]
80064dc: 4b51 ldr r3, [pc, #324] ; (8006624 <HAL_ETH_TransmitFrame+0x1cc>)
80064de: fba3 1302 umull r1, r3, r3, r2
80064e2: 0a9b lsrs r3, r3, #10
80064e4: f240 51f4 movw r1, #1524 ; 0x5f4
80064e8: fb01 f303 mul.w r3, r1, r3
80064ec: 1ad3 subs r3, r2, r3
80064ee: 2b00 cmp r3, #0
80064f0: d005 beq.n 80064fe <HAL_ETH_TransmitFrame+0xa6>
{
bufcount++;
80064f2: 697b ldr r3, [r7, #20]
80064f4: 3301 adds r3, #1
80064f6: 617b str r3, [r7, #20]
80064f8: e001 b.n 80064fe <HAL_ETH_TransmitFrame+0xa6>
}
}
else
{
bufcount = 1;
80064fa: 2301 movs r3, #1
80064fc: 617b str r3, [r7, #20]
}
if (bufcount == 1)
80064fe: 697b ldr r3, [r7, #20]
8006500: 2b01 cmp r3, #1
8006502: d11c bne.n 800653e <HAL_ETH_TransmitFrame+0xe6>
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
8006504: 687b ldr r3, [r7, #4]
8006506: 6adb ldr r3, [r3, #44] ; 0x2c
8006508: 681a ldr r2, [r3, #0]
800650a: 687b ldr r3, [r7, #4]
800650c: 6adb ldr r3, [r3, #44] ; 0x2c
800650e: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
8006512: 601a str r2, [r3, #0]
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
8006514: 687b ldr r3, [r7, #4]
8006516: 6adb ldr r3, [r3, #44] ; 0x2c
8006518: 683a ldr r2, [r7, #0]
800651a: f3c2 020c ubfx r2, r2, #0, #13
800651e: 605a str r2, [r3, #4]
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
8006520: 687b ldr r3, [r7, #4]
8006522: 6adb ldr r3, [r3, #44] ; 0x2c
8006524: 681a ldr r2, [r3, #0]
8006526: 687b ldr r3, [r7, #4]
8006528: 6adb ldr r3, [r3, #44] ; 0x2c
800652a: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
800652e: 601a str r2, [r3, #0]
/* Point to next descriptor */
heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
8006530: 687b ldr r3, [r7, #4]
8006532: 6adb ldr r3, [r3, #44] ; 0x2c
8006534: 68db ldr r3, [r3, #12]
8006536: 461a mov r2, r3
8006538: 687b ldr r3, [r7, #4]
800653a: 62da str r2, [r3, #44] ; 0x2c
800653c: e04b b.n 80065d6 <HAL_ETH_TransmitFrame+0x17e>
}
else
{
for (i=0; i< bufcount; i++)
800653e: 2300 movs r3, #0
8006540: 613b str r3, [r7, #16]
8006542: e044 b.n 80065ce <HAL_ETH_TransmitFrame+0x176>
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
8006544: 687b ldr r3, [r7, #4]
8006546: 6adb ldr r3, [r3, #44] ; 0x2c
8006548: 681a ldr r2, [r3, #0]
800654a: 687b ldr r3, [r7, #4]
800654c: 6adb ldr r3, [r3, #44] ; 0x2c
800654e: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8006552: 601a str r2, [r3, #0]
if (i == 0)
8006554: 693b ldr r3, [r7, #16]
8006556: 2b00 cmp r3, #0
8006558: d107 bne.n 800656a <HAL_ETH_TransmitFrame+0x112>
{
/* Setting the first segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
800655a: 687b ldr r3, [r7, #4]
800655c: 6adb ldr r3, [r3, #44] ; 0x2c
800655e: 681a ldr r2, [r3, #0]
8006560: 687b ldr r3, [r7, #4]
8006562: 6adb ldr r3, [r3, #44] ; 0x2c
8006564: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
8006568: 601a str r2, [r3, #0]
}
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
800656a: 687b ldr r3, [r7, #4]
800656c: 6adb ldr r3, [r3, #44] ; 0x2c
800656e: f240 52f4 movw r2, #1524 ; 0x5f4
8006572: 605a str r2, [r3, #4]
if (i == (bufcount-1))
8006574: 697b ldr r3, [r7, #20]
8006576: 3b01 subs r3, #1
8006578: 693a ldr r2, [r7, #16]
800657a: 429a cmp r2, r3
800657c: d116 bne.n 80065ac <HAL_ETH_TransmitFrame+0x154>
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
800657e: 687b ldr r3, [r7, #4]
8006580: 6adb ldr r3, [r3, #44] ; 0x2c
8006582: 681a ldr r2, [r3, #0]
8006584: 687b ldr r3, [r7, #4]
8006586: 6adb ldr r3, [r3, #44] ; 0x2c
8006588: f042 5200 orr.w r2, r2, #536870912 ; 0x20000000
800658c: 601a str r2, [r3, #0]
size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
800658e: 697b ldr r3, [r7, #20]
8006590: 4a25 ldr r2, [pc, #148] ; (8006628 <HAL_ETH_TransmitFrame+0x1d0>)
8006592: fb02 f203 mul.w r2, r2, r3
8006596: 683b ldr r3, [r7, #0]
8006598: 4413 add r3, r2
800659a: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800659e: 60fb str r3, [r7, #12]
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
80065a0: 687b ldr r3, [r7, #4]
80065a2: 6adb ldr r3, [r3, #44] ; 0x2c
80065a4: 68fa ldr r2, [r7, #12]
80065a6: f3c2 020c ubfx r2, r2, #0, #13
80065aa: 605a str r2, [r3, #4]
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
80065ac: 687b ldr r3, [r7, #4]
80065ae: 6adb ldr r3, [r3, #44] ; 0x2c
80065b0: 681a ldr r2, [r3, #0]
80065b2: 687b ldr r3, [r7, #4]
80065b4: 6adb ldr r3, [r3, #44] ; 0x2c
80065b6: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
80065ba: 601a str r2, [r3, #0]
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
80065bc: 687b ldr r3, [r7, #4]
80065be: 6adb ldr r3, [r3, #44] ; 0x2c
80065c0: 68db ldr r3, [r3, #12]
80065c2: 461a mov r2, r3
80065c4: 687b ldr r3, [r7, #4]
80065c6: 62da str r2, [r3, #44] ; 0x2c
for (i=0; i< bufcount; i++)
80065c8: 693b ldr r3, [r7, #16]
80065ca: 3301 adds r3, #1
80065cc: 613b str r3, [r7, #16]
80065ce: 693a ldr r2, [r7, #16]
80065d0: 697b ldr r3, [r7, #20]
80065d2: 429a cmp r2, r3
80065d4: d3b6 bcc.n 8006544 <HAL_ETH_TransmitFrame+0xec>
}
}
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
80065d6: 687b ldr r3, [r7, #4]
80065d8: 681a ldr r2, [r3, #0]
80065da: f241 0314 movw r3, #4116 ; 0x1014
80065de: 4413 add r3, r2
80065e0: 681b ldr r3, [r3, #0]
80065e2: f003 0304 and.w r3, r3, #4
80065e6: 2b00 cmp r3, #0
80065e8: d00d beq.n 8006606 <HAL_ETH_TransmitFrame+0x1ae>
{
/* Clear TBUS ETHERNET DMA flag */
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
80065ea: 687b ldr r3, [r7, #4]
80065ec: 681a ldr r2, [r3, #0]
80065ee: f241 0314 movw r3, #4116 ; 0x1014
80065f2: 4413 add r3, r2
80065f4: 2204 movs r2, #4
80065f6: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
(heth->Instance)->DMATPDR = 0;
80065f8: 687b ldr r3, [r7, #4]
80065fa: 681a ldr r2, [r3, #0]
80065fc: f241 0304 movw r3, #4100 ; 0x1004
8006600: 4413 add r3, r2
8006602: 2200 movs r2, #0
8006604: 601a str r2, [r3, #0]
}
/* Set ETH HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
8006606: 687b ldr r3, [r7, #4]
8006608: 2201 movs r2, #1
800660a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800660e: 687b ldr r3, [r7, #4]
8006610: 2200 movs r2, #0
8006612: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006616: 2300 movs r3, #0
}
8006618: 4618 mov r0, r3
800661a: 371c adds r7, #28
800661c: 46bd mov sp, r7
800661e: f85d 7b04 ldr.w r7, [sp], #4
8006622: 4770 bx lr
8006624: ac02b00b .word 0xac02b00b
8006628: fffffa0c .word 0xfffffa0c
0800662c <HAL_ETH_GetReceivedFrame_IT>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
800662c: b480 push {r7}
800662e: b085 sub sp, #20
8006630: af00 add r7, sp, #0
8006632: 6078 str r0, [r7, #4]
uint32_t descriptorscancounter = 0;
8006634: 2300 movs r3, #0
8006636: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
8006638: 687b ldr r3, [r7, #4]
800663a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800663e: 2b01 cmp r3, #1
8006640: d101 bne.n 8006646 <HAL_ETH_GetReceivedFrame_IT+0x1a>
8006642: 2302 movs r3, #2
8006644: e074 b.n 8006730 <HAL_ETH_GetReceivedFrame_IT+0x104>
8006646: 687b ldr r3, [r7, #4]
8006648: 2201 movs r2, #1
800664a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set ETH HAL State to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
800664e: 687b ldr r3, [r7, #4]
8006650: 2202 movs r2, #2
8006652: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Scan descriptors owned by CPU */
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
8006656: e05a b.n 800670e <HAL_ETH_GetReceivedFrame_IT+0xe2>
{
/* Just for security */
descriptorscancounter++;
8006658: 68fb ldr r3, [r7, #12]
800665a: 3301 adds r3, #1
800665c: 60fb str r3, [r7, #12]
/* Check if first segment in frame */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
800665e: 687b ldr r3, [r7, #4]
8006660: 6a9b ldr r3, [r3, #40] ; 0x28
8006662: 681b ldr r3, [r3, #0]
8006664: f403 7340 and.w r3, r3, #768 ; 0x300
8006668: f5b3 7f00 cmp.w r3, #512 ; 0x200
800666c: d10d bne.n 800668a <HAL_ETH_GetReceivedFrame_IT+0x5e>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
800666e: 687b ldr r3, [r7, #4]
8006670: 6a9a ldr r2, [r3, #40] ; 0x28
8006672: 687b ldr r3, [r7, #4]
8006674: 631a str r2, [r3, #48] ; 0x30
heth->RxFrameInfos.SegCount = 1;
8006676: 687b ldr r3, [r7, #4]
8006678: 2201 movs r2, #1
800667a: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
800667c: 687b ldr r3, [r7, #4]
800667e: 6a9b ldr r3, [r3, #40] ; 0x28
8006680: 68db ldr r3, [r3, #12]
8006682: 461a mov r2, r3
8006684: 687b ldr r3, [r7, #4]
8006686: 629a str r2, [r3, #40] ; 0x28
8006688: e041 b.n 800670e <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Check if intermediate segment */
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
800668a: 687b ldr r3, [r7, #4]
800668c: 6a9b ldr r3, [r3, #40] ; 0x28
800668e: 681b ldr r3, [r3, #0]
8006690: f403 7340 and.w r3, r3, #768 ; 0x300
8006694: 2b00 cmp r3, #0
8006696: d10b bne.n 80066b0 <HAL_ETH_GetReceivedFrame_IT+0x84>
{
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
8006698: 687b ldr r3, [r7, #4]
800669a: 6b9b ldr r3, [r3, #56] ; 0x38
800669c: 1c5a adds r2, r3, #1
800669e: 687b ldr r3, [r7, #4]
80066a0: 639a str r2, [r3, #56] ; 0x38
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
80066a2: 687b ldr r3, [r7, #4]
80066a4: 6a9b ldr r3, [r3, #40] ; 0x28
80066a6: 68db ldr r3, [r3, #12]
80066a8: 461a mov r2, r3
80066aa: 687b ldr r3, [r7, #4]
80066ac: 629a str r2, [r3, #40] ; 0x28
80066ae: e02e b.n 800670e <HAL_ETH_GetReceivedFrame_IT+0xe2>
}
/* Should be last segment */
else
{
/* Last segment */
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
80066b0: 687b ldr r3, [r7, #4]
80066b2: 6a9a ldr r2, [r3, #40] ; 0x28
80066b4: 687b ldr r3, [r7, #4]
80066b6: 635a str r2, [r3, #52] ; 0x34
/* Increment segment count */
(heth->RxFrameInfos.SegCount)++;
80066b8: 687b ldr r3, [r7, #4]
80066ba: 6b9b ldr r3, [r3, #56] ; 0x38
80066bc: 1c5a adds r2, r3, #1
80066be: 687b ldr r3, [r7, #4]
80066c0: 639a str r2, [r3, #56] ; 0x38
/* Check if last segment is first segment: one segment contains the frame */
if ((heth->RxFrameInfos.SegCount) == 1)
80066c2: 687b ldr r3, [r7, #4]
80066c4: 6b9b ldr r3, [r3, #56] ; 0x38
80066c6: 2b01 cmp r3, #1
80066c8: d103 bne.n 80066d2 <HAL_ETH_GetReceivedFrame_IT+0xa6>
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
80066ca: 687b ldr r3, [r7, #4]
80066cc: 6a9a ldr r2, [r3, #40] ; 0x28
80066ce: 687b ldr r3, [r7, #4]
80066d0: 631a str r2, [r3, #48] ; 0x30
}
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
80066d2: 687b ldr r3, [r7, #4]
80066d4: 6a9b ldr r3, [r3, #40] ; 0x28
80066d6: 681b ldr r3, [r3, #0]
80066d8: 0c1b lsrs r3, r3, #16
80066da: f3c3 030d ubfx r3, r3, #0, #14
80066de: 1f1a subs r2, r3, #4
80066e0: 687b ldr r3, [r7, #4]
80066e2: 63da str r2, [r3, #60] ; 0x3c
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
80066e4: 687b ldr r3, [r7, #4]
80066e6: 6b1b ldr r3, [r3, #48] ; 0x30
80066e8: 689a ldr r2, [r3, #8]
80066ea: 687b ldr r3, [r7, #4]
80066ec: 641a str r2, [r3, #64] ; 0x40
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
80066ee: 687b ldr r3, [r7, #4]
80066f0: 6a9b ldr r3, [r3, #40] ; 0x28
80066f2: 68db ldr r3, [r3, #12]
80066f4: 461a mov r2, r3
80066f6: 687b ldr r3, [r7, #4]
80066f8: 629a str r2, [r3, #40] ; 0x28
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80066fa: 687b ldr r3, [r7, #4]
80066fc: 2201 movs r2, #1
80066fe: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006702: 687b ldr r3, [r7, #4]
8006704: 2200 movs r2, #0
8006706: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
800670a: 2300 movs r3, #0
800670c: e010 b.n 8006730 <HAL_ETH_GetReceivedFrame_IT+0x104>
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
800670e: 687b ldr r3, [r7, #4]
8006710: 6a9b ldr r3, [r3, #40] ; 0x28
8006712: 681b ldr r3, [r3, #0]
8006714: 2b00 cmp r3, #0
8006716: db02 blt.n 800671e <HAL_ETH_GetReceivedFrame_IT+0xf2>
8006718: 68fb ldr r3, [r7, #12]
800671a: 2b03 cmp r3, #3
800671c: d99c bls.n 8006658 <HAL_ETH_GetReceivedFrame_IT+0x2c>
}
}
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
800671e: 687b ldr r3, [r7, #4]
8006720: 2201 movs r2, #1
8006722: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006726: 687b ldr r3, [r7, #4]
8006728: 2200 movs r2, #0
800672a: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_ERROR;
800672e: 2301 movs r3, #1
}
8006730: 4618 mov r0, r3
8006732: 3714 adds r7, #20
8006734: 46bd mov sp, r7
8006736: f85d 7b04 ldr.w r7, [sp], #4
800673a: 4770 bx lr
0800673c <HAL_ETH_IRQHandler>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
800673c: b580 push {r7, lr}
800673e: b082 sub sp, #8
8006740: af00 add r7, sp, #0
8006742: 6078 str r0, [r7, #4]
/* Frame received */
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
8006744: 687b ldr r3, [r7, #4]
8006746: 681a ldr r2, [r3, #0]
8006748: f241 0314 movw r3, #4116 ; 0x1014
800674c: 4413 add r3, r2
800674e: 681b ldr r3, [r3, #0]
8006750: f003 0340 and.w r3, r3, #64 ; 0x40
8006754: 2b40 cmp r3, #64 ; 0x40
8006756: d112 bne.n 800677e <HAL_ETH_IRQHandler+0x42>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
8006758: 6878 ldr r0, [r7, #4]
800675a: f004 fdaf bl 800b2bc <HAL_ETH_RxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
800675e: 687b ldr r3, [r7, #4]
8006760: 681a ldr r2, [r3, #0]
8006762: f241 0314 movw r3, #4116 ; 0x1014
8006766: 4413 add r3, r2
8006768: 2240 movs r2, #64 ; 0x40
800676a: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
800676c: 687b ldr r3, [r7, #4]
800676e: 2201 movs r2, #1
8006770: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006774: 687b ldr r3, [r7, #4]
8006776: 2200 movs r2, #0
8006778: f883 2045 strb.w r2, [r3, #69] ; 0x45
800677c: e01b b.n 80067b6 <HAL_ETH_IRQHandler+0x7a>
}
/* Frame transmitted */
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
800677e: 687b ldr r3, [r7, #4]
8006780: 681a ldr r2, [r3, #0]
8006782: f241 0314 movw r3, #4116 ; 0x1014
8006786: 4413 add r3, r2
8006788: 681b ldr r3, [r3, #0]
800678a: f003 0301 and.w r3, r3, #1
800678e: 2b01 cmp r3, #1
8006790: d111 bne.n 80067b6 <HAL_ETH_IRQHandler+0x7a>
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call resgistered Transfer complete callback*/
heth->TxCpltCallback(heth);
#else
/* Transfer complete callback */
HAL_ETH_TxCpltCallback(heth);
8006792: 6878 ldr r0, [r7, #4]
8006794: f000 f839 bl 800680a <HAL_ETH_TxCpltCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the Eth DMA Tx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
8006798: 687b ldr r3, [r7, #4]
800679a: 681a ldr r2, [r3, #0]
800679c: f241 0314 movw r3, #4116 ; 0x1014
80067a0: 4413 add r3, r2
80067a2: 2201 movs r2, #1
80067a4: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80067a6: 687b ldr r3, [r7, #4]
80067a8: 2201 movs r2, #1
80067aa: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80067ae: 687b ldr r3, [r7, #4]
80067b0: 2200 movs r2, #0
80067b2: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
80067b6: 687b ldr r3, [r7, #4]
80067b8: 681a ldr r2, [r3, #0]
80067ba: f241 0314 movw r3, #4116 ; 0x1014
80067be: 4413 add r3, r2
80067c0: f44f 3280 mov.w r2, #65536 ; 0x10000
80067c4: 601a str r2, [r3, #0]
/* ETH DMA Error */
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
80067c6: 687b ldr r3, [r7, #4]
80067c8: 681a ldr r2, [r3, #0]
80067ca: f241 0314 movw r3, #4116 ; 0x1014
80067ce: 4413 add r3, r2
80067d0: 681b ldr r3, [r3, #0]
80067d2: f403 4300 and.w r3, r3, #32768 ; 0x8000
80067d6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80067da: d112 bne.n 8006802 <HAL_ETH_IRQHandler+0xc6>
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
heth->DMAErrorCallback(heth);
#else
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
80067dc: 6878 ldr r0, [r7, #4]
80067de: f000 f81e bl 800681e <HAL_ETH_ErrorCallback>
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/* Clear the interrupt flags */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
80067e2: 687b ldr r3, [r7, #4]
80067e4: 681a ldr r2, [r3, #0]
80067e6: f241 0314 movw r3, #4116 ; 0x1014
80067ea: 4413 add r3, r2
80067ec: f44f 4200 mov.w r2, #32768 ; 0x8000
80067f0: 601a str r2, [r3, #0]
/* Set HAL State to Ready */
heth->State = HAL_ETH_STATE_READY;
80067f2: 687b ldr r3, [r7, #4]
80067f4: 2201 movs r2, #1
80067f6: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80067fa: 687b ldr r3, [r7, #4]
80067fc: 2200 movs r2, #0
80067fe: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
}
8006802: bf00 nop
8006804: 3708 adds r7, #8
8006806: 46bd mov sp, r7
8006808: bd80 pop {r7, pc}
0800680a <HAL_ETH_TxCpltCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
{
800680a: b480 push {r7}
800680c: b083 sub sp, #12
800680e: af00 add r7, sp, #0
8006810: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_TxCpltCallback could be implemented in the user file
*/
}
8006812: bf00 nop
8006814: 370c adds r7, #12
8006816: 46bd mov sp, r7
8006818: f85d 7b04 ldr.w r7, [sp], #4
800681c: 4770 bx lr
0800681e <HAL_ETH_ErrorCallback>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
{
800681e: b480 push {r7}
8006820: b083 sub sp, #12
8006822: af00 add r7, sp, #0
8006824: 6078 str r0, [r7, #4]
UNUSED(heth);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ETH_ErrorCallback could be implemented in the user file
*/
}
8006826: bf00 nop
8006828: 370c adds r7, #12
800682a: 46bd mov sp, r7
800682c: f85d 7b04 ldr.w r7, [sp], #4
8006830: 4770 bx lr
08006832 <HAL_ETH_ReadPHYRegister>:
* More PHY register could be read depending on the used PHY
* @param RegValue PHY register value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
8006832: b580 push {r7, lr}
8006834: b086 sub sp, #24
8006836: af00 add r7, sp, #0
8006838: 60f8 str r0, [r7, #12]
800683a: 460b mov r3, r1
800683c: 607a str r2, [r7, #4]
800683e: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
8006840: 2300 movs r3, #0
8006842: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
8006844: 2300 movs r3, #0
8006846: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_RD)
8006848: 68fb ldr r3, [r7, #12]
800684a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800684e: b2db uxtb r3, r3
8006850: 2b82 cmp r3, #130 ; 0x82
8006852: d101 bne.n 8006858 <HAL_ETH_ReadPHYRegister+0x26>
{
return HAL_BUSY;
8006854: 2302 movs r3, #2
8006856: e050 b.n 80068fa <HAL_ETH_ReadPHYRegister+0xc8>
}
/* Set ETH HAL State to BUSY_RD */
heth->State = HAL_ETH_STATE_BUSY_RD;
8006858: 68fb ldr r3, [r7, #12]
800685a: 2282 movs r2, #130 ; 0x82
800685c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
8006860: 68fb ldr r3, [r7, #12]
8006862: 681b ldr r3, [r3, #0]
8006864: 691b ldr r3, [r3, #16]
8006866: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
8006868: 697b ldr r3, [r7, #20]
800686a: f003 031c and.w r3, r3, #28
800686e: 617b str r3, [r7, #20]
/* Prepare the MII address register value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
8006870: 68fb ldr r3, [r7, #12]
8006872: 8a1b ldrh r3, [r3, #16]
8006874: 02db lsls r3, r3, #11
8006876: b29b uxth r3, r3
8006878: 697a ldr r2, [r7, #20]
800687a: 4313 orrs r3, r2
800687c: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
800687e: 897b ldrh r3, [r7, #10]
8006880: 019b lsls r3, r3, #6
8006882: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
8006886: 697a ldr r2, [r7, #20]
8006888: 4313 orrs r3, r2
800688a: 617b str r3, [r7, #20]
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
800688c: 697b ldr r3, [r7, #20]
800688e: f023 0302 bic.w r3, r3, #2
8006892: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
8006894: 697b ldr r3, [r7, #20]
8006896: f043 0301 orr.w r3, r3, #1
800689a: 617b str r3, [r7, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
800689c: 68fb ldr r3, [r7, #12]
800689e: 681b ldr r3, [r3, #0]
80068a0: 697a ldr r2, [r7, #20]
80068a2: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
80068a4: f7fe f87c bl 80049a0 <HAL_GetTick>
80068a8: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80068aa: e015 b.n 80068d8 <HAL_ETH_ReadPHYRegister+0xa6>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
80068ac: f7fe f878 bl 80049a0 <HAL_GetTick>
80068b0: 4602 mov r2, r0
80068b2: 693b ldr r3, [r7, #16]
80068b4: 1ad3 subs r3, r2, r3
80068b6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80068ba: d309 bcc.n 80068d0 <HAL_ETH_ReadPHYRegister+0x9e>
{
heth->State= HAL_ETH_STATE_READY;
80068bc: 68fb ldr r3, [r7, #12]
80068be: 2201 movs r2, #1
80068c0: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
80068c4: 68fb ldr r3, [r7, #12]
80068c6: 2200 movs r2, #0
80068c8: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
80068cc: 2303 movs r3, #3
80068ce: e014 b.n 80068fa <HAL_ETH_ReadPHYRegister+0xc8>
}
tmpreg = heth->Instance->MACMIIAR;
80068d0: 68fb ldr r3, [r7, #12]
80068d2: 681b ldr r3, [r3, #0]
80068d4: 691b ldr r3, [r3, #16]
80068d6: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80068d8: 697b ldr r3, [r7, #20]
80068da: f003 0301 and.w r3, r3, #1
80068de: 2b00 cmp r3, #0
80068e0: d1e4 bne.n 80068ac <HAL_ETH_ReadPHYRegister+0x7a>
}
/* Get MACMIIDR value */
*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
80068e2: 68fb ldr r3, [r7, #12]
80068e4: 681b ldr r3, [r3, #0]
80068e6: 695b ldr r3, [r3, #20]
80068e8: b29b uxth r3, r3
80068ea: 461a mov r2, r3
80068ec: 687b ldr r3, [r7, #4]
80068ee: 601a str r2, [r3, #0]
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
80068f0: 68fb ldr r3, [r7, #12]
80068f2: 2201 movs r2, #1
80068f4: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
80068f8: 2300 movs r3, #0
}
80068fa: 4618 mov r0, r3
80068fc: 3718 adds r7, #24
80068fe: 46bd mov sp, r7
8006900: bd80 pop {r7, pc}
08006902 <HAL_ETH_WritePHYRegister>:
* More PHY register could be written depending on the used PHY
* @param RegValue the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
8006902: b580 push {r7, lr}
8006904: b086 sub sp, #24
8006906: af00 add r7, sp, #0
8006908: 60f8 str r0, [r7, #12]
800690a: 460b mov r3, r1
800690c: 607a str r2, [r7, #4]
800690e: 817b strh r3, [r7, #10]
uint32_t tmpreg = 0;
8006910: 2300 movs r3, #0
8006912: 617b str r3, [r7, #20]
uint32_t tickstart = 0;
8006914: 2300 movs r3, #0
8006916: 613b str r3, [r7, #16]
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
/* Check the ETH peripheral state */
if(heth->State == HAL_ETH_STATE_BUSY_WR)
8006918: 68fb ldr r3, [r7, #12]
800691a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800691e: b2db uxtb r3, r3
8006920: 2b42 cmp r3, #66 ; 0x42
8006922: d101 bne.n 8006928 <HAL_ETH_WritePHYRegister+0x26>
{
return HAL_BUSY;
8006924: 2302 movs r3, #2
8006926: e04e b.n 80069c6 <HAL_ETH_WritePHYRegister+0xc4>
}
/* Set ETH HAL State to BUSY_WR */
heth->State = HAL_ETH_STATE_BUSY_WR;
8006928: 68fb ldr r3, [r7, #12]
800692a: 2242 movs r2, #66 ; 0x42
800692c: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Get the ETHERNET MACMIIAR value */
tmpreg = heth->Instance->MACMIIAR;
8006930: 68fb ldr r3, [r7, #12]
8006932: 681b ldr r3, [r3, #0]
8006934: 691b ldr r3, [r3, #16]
8006936: 617b str r3, [r7, #20]
/* Keep only the CSR Clock Range CR[2:0] bits value */
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
8006938: 697b ldr r3, [r7, #20]
800693a: f003 031c and.w r3, r3, #28
800693e: 617b str r3, [r7, #20]
/* Prepare the MII register address value */
tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
8006940: 68fb ldr r3, [r7, #12]
8006942: 8a1b ldrh r3, [r3, #16]
8006944: 02db lsls r3, r3, #11
8006946: b29b uxth r3, r3
8006948: 697a ldr r2, [r7, #20]
800694a: 4313 orrs r3, r2
800694c: 617b str r3, [r7, #20]
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
800694e: 897b ldrh r3, [r7, #10]
8006950: 019b lsls r3, r3, #6
8006952: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
8006956: 697a ldr r2, [r7, #20]
8006958: 4313 orrs r3, r2
800695a: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
800695c: 697b ldr r3, [r7, #20]
800695e: f043 0302 orr.w r3, r3, #2
8006962: 617b str r3, [r7, #20]
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
8006964: 697b ldr r3, [r7, #20]
8006966: f043 0301 orr.w r3, r3, #1
800696a: 617b str r3, [r7, #20]
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
800696c: 687b ldr r3, [r7, #4]
800696e: b29a uxth r2, r3
8006970: 68fb ldr r3, [r7, #12]
8006972: 681b ldr r3, [r3, #0]
8006974: 615a str r2, [r3, #20]
/* Write the result value into the MII Address register */
heth->Instance->MACMIIAR = tmpreg;
8006976: 68fb ldr r3, [r7, #12]
8006978: 681b ldr r3, [r3, #0]
800697a: 697a ldr r2, [r7, #20]
800697c: 611a str r2, [r3, #16]
/* Get tick */
tickstart = HAL_GetTick();
800697e: f7fe f80f bl 80049a0 <HAL_GetTick>
8006982: 6138 str r0, [r7, #16]
/* Check for the Busy flag */
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
8006984: e015 b.n 80069b2 <HAL_ETH_WritePHYRegister+0xb0>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
8006986: f7fe f80b bl 80049a0 <HAL_GetTick>
800698a: 4602 mov r2, r0
800698c: 693b ldr r3, [r7, #16]
800698e: 1ad3 subs r3, r2, r3
8006990: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8006994: d309 bcc.n 80069aa <HAL_ETH_WritePHYRegister+0xa8>
{
heth->State= HAL_ETH_STATE_READY;
8006996: 68fb ldr r3, [r7, #12]
8006998: 2201 movs r2, #1
800699a: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
800699e: 68fb ldr r3, [r7, #12]
80069a0: 2200 movs r2, #0
80069a2: f883 2045 strb.w r2, [r3, #69] ; 0x45
return HAL_TIMEOUT;
80069a6: 2303 movs r3, #3
80069a8: e00d b.n 80069c6 <HAL_ETH_WritePHYRegister+0xc4>
}
tmpreg = heth->Instance->MACMIIAR;
80069aa: 68fb ldr r3, [r7, #12]
80069ac: 681b ldr r3, [r3, #0]
80069ae: 691b ldr r3, [r3, #16]
80069b0: 617b str r3, [r7, #20]
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
80069b2: 697b ldr r3, [r7, #20]
80069b4: f003 0301 and.w r3, r3, #1
80069b8: 2b00 cmp r3, #0
80069ba: d1e4 bne.n 8006986 <HAL_ETH_WritePHYRegister+0x84>
}
/* Set ETH HAL State to READY */
heth->State = HAL_ETH_STATE_READY;
80069bc: 68fb ldr r3, [r7, #12]
80069be: 2201 movs r2, #1
80069c0: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Return function status */
return HAL_OK;
80069c4: 2300 movs r3, #0
}
80069c6: 4618 mov r0, r3
80069c8: 3718 adds r7, #24
80069ca: 46bd mov sp, r7
80069cc: bd80 pop {r7, pc}
080069ce <HAL_ETH_Start>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
{
80069ce: b580 push {r7, lr}
80069d0: b082 sub sp, #8
80069d2: af00 add r7, sp, #0
80069d4: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
80069d6: 687b ldr r3, [r7, #4]
80069d8: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80069dc: 2b01 cmp r3, #1
80069de: d101 bne.n 80069e4 <HAL_ETH_Start+0x16>
80069e0: 2302 movs r3, #2
80069e2: e01f b.n 8006a24 <HAL_ETH_Start+0x56>
80069e4: 687b ldr r3, [r7, #4]
80069e6: 2201 movs r2, #1
80069e8: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
80069ec: 687b ldr r3, [r7, #4]
80069ee: 2202 movs r2, #2
80069f0: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Enable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionEnable(heth);
80069f4: 6878 ldr r0, [r7, #4]
80069f6: f000 fb45 bl 8007084 <ETH_MACTransmissionEnable>
/* Enable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionEnable(heth);
80069fa: 6878 ldr r0, [r7, #4]
80069fc: f000 fb7c bl 80070f8 <ETH_MACReceptionEnable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
8006a00: 6878 ldr r0, [r7, #4]
8006a02: f000 fc13 bl 800722c <ETH_FlushTransmitFIFO>
/* Start DMA transmission */
ETH_DMATransmissionEnable(heth);
8006a06: 6878 ldr r0, [r7, #4]
8006a08: f000 fbb0 bl 800716c <ETH_DMATransmissionEnable>
/* Start DMA reception */
ETH_DMAReceptionEnable(heth);
8006a0c: 6878 ldr r0, [r7, #4]
8006a0e: f000 fbdd bl 80071cc <ETH_DMAReceptionEnable>
/* Set the ETH state to READY*/
heth->State= HAL_ETH_STATE_READY;
8006a12: 687b ldr r3, [r7, #4]
8006a14: 2201 movs r2, #1
8006a16: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006a1a: 687b ldr r3, [r7, #4]
8006a1c: 2200 movs r2, #0
8006a1e: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006a22: 2300 movs r3, #0
}
8006a24: 4618 mov r0, r3
8006a26: 3708 adds r7, #8
8006a28: 46bd mov sp, r7
8006a2a: bd80 pop {r7, pc}
08006a2c <HAL_ETH_Stop>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
{
8006a2c: b580 push {r7, lr}
8006a2e: b082 sub sp, #8
8006a30: af00 add r7, sp, #0
8006a32: 6078 str r0, [r7, #4]
/* Process Locked */
__HAL_LOCK(heth);
8006a34: 687b ldr r3, [r7, #4]
8006a36: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006a3a: 2b01 cmp r3, #1
8006a3c: d101 bne.n 8006a42 <HAL_ETH_Stop+0x16>
8006a3e: 2302 movs r3, #2
8006a40: e01f b.n 8006a82 <HAL_ETH_Stop+0x56>
8006a42: 687b ldr r3, [r7, #4]
8006a44: 2201 movs r2, #1
8006a46: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
8006a4a: 687b ldr r3, [r7, #4]
8006a4c: 2202 movs r2, #2
8006a4e: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Stop DMA transmission */
ETH_DMATransmissionDisable(heth);
8006a52: 6878 ldr r0, [r7, #4]
8006a54: f000 fba2 bl 800719c <ETH_DMATransmissionDisable>
/* Stop DMA reception */
ETH_DMAReceptionDisable(heth);
8006a58: 6878 ldr r0, [r7, #4]
8006a5a: f000 fbcf bl 80071fc <ETH_DMAReceptionDisable>
/* Disable receive state machine of the MAC for reception from the MII */
ETH_MACReceptionDisable(heth);
8006a5e: 6878 ldr r0, [r7, #4]
8006a60: f000 fb67 bl 8007132 <ETH_MACReceptionDisable>
/* Flush Transmit FIFO */
ETH_FlushTransmitFIFO(heth);
8006a64: 6878 ldr r0, [r7, #4]
8006a66: f000 fbe1 bl 800722c <ETH_FlushTransmitFIFO>
/* Disable transmit state machine of the MAC for transmission on the MII */
ETH_MACTransmissionDisable(heth);
8006a6a: 6878 ldr r0, [r7, #4]
8006a6c: f000 fb27 bl 80070be <ETH_MACTransmissionDisable>
/* Set the ETH state*/
heth->State = HAL_ETH_STATE_READY;
8006a70: 687b ldr r3, [r7, #4]
8006a72: 2201 movs r2, #1
8006a74: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006a78: 687b ldr r3, [r7, #4]
8006a7a: 2200 movs r2, #0
8006a7c: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006a80: 2300 movs r3, #0
}
8006a82: 4618 mov r0, r3
8006a84: 3708 adds r7, #8
8006a86: 46bd mov sp, r7
8006a88: bd80 pop {r7, pc}
...
08006a8c <HAL_ETH_ConfigMAC>:
* the configuration information for ETHERNET module
* @param macconf MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
8006a8c: b580 push {r7, lr}
8006a8e: b084 sub sp, #16
8006a90: af00 add r7, sp, #0
8006a92: 6078 str r0, [r7, #4]
8006a94: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
8006a96: 2300 movs r3, #0
8006a98: 60fb str r3, [r7, #12]
/* Process Locked */
__HAL_LOCK(heth);
8006a9a: 687b ldr r3, [r7, #4]
8006a9c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8006aa0: 2b01 cmp r3, #1
8006aa2: d101 bne.n 8006aa8 <HAL_ETH_ConfigMAC+0x1c>
8006aa4: 2302 movs r3, #2
8006aa6: e0e4 b.n 8006c72 <HAL_ETH_ConfigMAC+0x1e6>
8006aa8: 687b ldr r3, [r7, #4]
8006aaa: 2201 movs r2, #1
8006aac: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Set the ETH peripheral state to BUSY */
heth->State= HAL_ETH_STATE_BUSY;
8006ab0: 687b ldr r3, [r7, #4]
8006ab2: 2202 movs r2, #2
8006ab4: f883 2044 strb.w r2, [r3, #68] ; 0x44
assert_param(IS_ETH_SPEED(heth->Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
if (macconf != NULL)
8006ab8: 683b ldr r3, [r7, #0]
8006aba: 2b00 cmp r3, #0
8006abc: f000 80b1 beq.w 8006c22 <HAL_ETH_ConfigMAC+0x196>
assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006ac0: 687b ldr r3, [r7, #4]
8006ac2: 681b ldr r3, [r3, #0]
8006ac4: 681b ldr r3, [r3, #0]
8006ac6: 60fb str r3, [r7, #12]
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006ac8: 68fa ldr r2, [r7, #12]
8006aca: 4b6c ldr r3, [pc, #432] ; (8006c7c <HAL_ETH_ConfigMAC+0x1f0>)
8006acc: 4013 ands r3, r2
8006ace: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006ad0: 683b ldr r3, [r7, #0]
8006ad2: 681a ldr r2, [r3, #0]
macconf->Jabber |
8006ad4: 683b ldr r3, [r7, #0]
8006ad6: 685b ldr r3, [r3, #4]
tmpreg |= (uint32_t)(macconf->Watchdog |
8006ad8: 431a orrs r2, r3
macconf->InterFrameGap |
8006ada: 683b ldr r3, [r7, #0]
8006adc: 689b ldr r3, [r3, #8]
macconf->Jabber |
8006ade: 431a orrs r2, r3
macconf->CarrierSense |
8006ae0: 683b ldr r3, [r7, #0]
8006ae2: 68db ldr r3, [r3, #12]
macconf->InterFrameGap |
8006ae4: 431a orrs r2, r3
(heth->Init).Speed |
8006ae6: 687b ldr r3, [r7, #4]
8006ae8: 689b ldr r3, [r3, #8]
macconf->CarrierSense |
8006aea: 431a orrs r2, r3
macconf->ReceiveOwn |
8006aec: 683b ldr r3, [r7, #0]
8006aee: 691b ldr r3, [r3, #16]
(heth->Init).Speed |
8006af0: 431a orrs r2, r3
macconf->LoopbackMode |
8006af2: 683b ldr r3, [r7, #0]
8006af4: 695b ldr r3, [r3, #20]
macconf->ReceiveOwn |
8006af6: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006af8: 687b ldr r3, [r7, #4]
8006afa: 68db ldr r3, [r3, #12]
macconf->LoopbackMode |
8006afc: 431a orrs r2, r3
macconf->ChecksumOffload |
8006afe: 683b ldr r3, [r7, #0]
8006b00: 699b ldr r3, [r3, #24]
(heth->Init).DuplexMode |
8006b02: 431a orrs r2, r3
macconf->RetryTransmission |
8006b04: 683b ldr r3, [r7, #0]
8006b06: 69db ldr r3, [r3, #28]
macconf->ChecksumOffload |
8006b08: 431a orrs r2, r3
macconf->AutomaticPadCRCStrip |
8006b0a: 683b ldr r3, [r7, #0]
8006b0c: 6a1b ldr r3, [r3, #32]
macconf->RetryTransmission |
8006b0e: 431a orrs r2, r3
macconf->BackOffLimit |
8006b10: 683b ldr r3, [r7, #0]
8006b12: 6a5b ldr r3, [r3, #36] ; 0x24
macconf->AutomaticPadCRCStrip |
8006b14: 431a orrs r2, r3
macconf->DeferralCheck);
8006b16: 683b ldr r3, [r7, #0]
8006b18: 6a9b ldr r3, [r3, #40] ; 0x28
macconf->BackOffLimit |
8006b1a: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macconf->Watchdog |
8006b1c: 68fa ldr r2, [r7, #12]
8006b1e: 4313 orrs r3, r2
8006b20: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006b22: 687b ldr r3, [r7, #4]
8006b24: 681b ldr r3, [r3, #0]
8006b26: 68fa ldr r2, [r7, #12]
8006b28: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006b2a: 687b ldr r3, [r7, #4]
8006b2c: 681b ldr r3, [r3, #0]
8006b2e: 681b ldr r3, [r3, #0]
8006b30: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006b32: 2001 movs r0, #1
8006b34: f7fd ff40 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006b38: 687b ldr r3, [r7, #4]
8006b3a: 681b ldr r3, [r3, #0]
8006b3c: 68fa ldr r2, [r7, #12]
8006b3e: 601a str r2, [r3, #0]
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b40: 683b ldr r3, [r7, #0]
8006b42: 6ada ldr r2, [r3, #44] ; 0x2c
macconf->SourceAddrFilter |
8006b44: 683b ldr r3, [r7, #0]
8006b46: 6b1b ldr r3, [r3, #48] ; 0x30
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b48: 431a orrs r2, r3
macconf->PassControlFrames |
8006b4a: 683b ldr r3, [r7, #0]
8006b4c: 6b5b ldr r3, [r3, #52] ; 0x34
macconf->SourceAddrFilter |
8006b4e: 431a orrs r2, r3
macconf->BroadcastFramesReception |
8006b50: 683b ldr r3, [r7, #0]
8006b52: 6b9b ldr r3, [r3, #56] ; 0x38
macconf->PassControlFrames |
8006b54: 431a orrs r2, r3
macconf->DestinationAddrFilter |
8006b56: 683b ldr r3, [r7, #0]
8006b58: 6bdb ldr r3, [r3, #60] ; 0x3c
macconf->BroadcastFramesReception |
8006b5a: 431a orrs r2, r3
macconf->PromiscuousMode |
8006b5c: 683b ldr r3, [r7, #0]
8006b5e: 6c1b ldr r3, [r3, #64] ; 0x40
macconf->DestinationAddrFilter |
8006b60: 431a orrs r2, r3
macconf->MulticastFramesFilter |
8006b62: 683b ldr r3, [r7, #0]
8006b64: 6c5b ldr r3, [r3, #68] ; 0x44
macconf->PromiscuousMode |
8006b66: ea42 0103 orr.w r1, r2, r3
macconf->UnicastFramesFilter);
8006b6a: 683b ldr r3, [r7, #0]
8006b6c: 6c9a ldr r2, [r3, #72] ; 0x48
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b6e: 687b ldr r3, [r7, #4]
8006b70: 681b ldr r3, [r3, #0]
macconf->MulticastFramesFilter |
8006b72: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
8006b74: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
8006b76: 687b ldr r3, [r7, #4]
8006b78: 681b ldr r3, [r3, #0]
8006b7a: 685b ldr r3, [r3, #4]
8006b7c: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006b7e: 2001 movs r0, #1
8006b80: f7fd ff1a bl 80049b8 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006b84: 687b ldr r3, [r7, #4]
8006b86: 681b ldr r3, [r3, #0]
8006b88: 68fa ldr r2, [r7, #12]
8006b8a: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
8006b8c: 687b ldr r3, [r7, #4]
8006b8e: 681b ldr r3, [r3, #0]
8006b90: 683a ldr r2, [r7, #0]
8006b92: 6cd2 ldr r2, [r2, #76] ; 0x4c
8006b94: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
8006b96: 687b ldr r3, [r7, #4]
8006b98: 681b ldr r3, [r3, #0]
8006b9a: 683a ldr r2, [r7, #0]
8006b9c: 6d12 ldr r2, [r2, #80] ; 0x50
8006b9e: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006ba0: 687b ldr r3, [r7, #4]
8006ba2: 681b ldr r3, [r3, #0]
8006ba4: 699b ldr r3, [r3, #24]
8006ba6: 60fb str r3, [r7, #12]
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006ba8: 68fa ldr r2, [r7, #12]
8006baa: f64f 7341 movw r3, #65345 ; 0xff41
8006bae: 4013 ands r3, r2
8006bb0: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006bb2: 683b ldr r3, [r7, #0]
8006bb4: 6d5b ldr r3, [r3, #84] ; 0x54
8006bb6: 041a lsls r2, r3, #16
macconf->ZeroQuantaPause |
8006bb8: 683b ldr r3, [r7, #0]
8006bba: 6d9b ldr r3, [r3, #88] ; 0x58
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006bbc: 431a orrs r2, r3
macconf->PauseLowThreshold |
8006bbe: 683b ldr r3, [r7, #0]
8006bc0: 6ddb ldr r3, [r3, #92] ; 0x5c
macconf->ZeroQuantaPause |
8006bc2: 431a orrs r2, r3
macconf->UnicastPauseFrameDetect |
8006bc4: 683b ldr r3, [r7, #0]
8006bc6: 6e1b ldr r3, [r3, #96] ; 0x60
macconf->PauseLowThreshold |
8006bc8: 431a orrs r2, r3
macconf->ReceiveFlowControl |
8006bca: 683b ldr r3, [r7, #0]
8006bcc: 6e5b ldr r3, [r3, #100] ; 0x64
macconf->UnicastPauseFrameDetect |
8006bce: 431a orrs r2, r3
macconf->TransmitFlowControl);
8006bd0: 683b ldr r3, [r7, #0]
8006bd2: 6e9b ldr r3, [r3, #104] ; 0x68
macconf->ReceiveFlowControl |
8006bd4: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
8006bd6: 68fa ldr r2, [r7, #12]
8006bd8: 4313 orrs r3, r2
8006bda: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006bdc: 687b ldr r3, [r7, #4]
8006bde: 681b ldr r3, [r3, #0]
8006be0: 68fa ldr r2, [r7, #12]
8006be2: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006be4: 687b ldr r3, [r7, #4]
8006be6: 681b ldr r3, [r3, #0]
8006be8: 699b ldr r3, [r3, #24]
8006bea: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006bec: 2001 movs r0, #1
8006bee: f7fd fee3 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006bf2: 687b ldr r3, [r7, #4]
8006bf4: 681b ldr r3, [r3, #0]
8006bf6: 68fa ldr r2, [r7, #12]
8006bf8: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006bfa: 683b ldr r3, [r7, #0]
8006bfc: 6ed9 ldr r1, [r3, #108] ; 0x6c
macconf->VLANTagIdentifier);
8006bfe: 683b ldr r3, [r7, #0]
8006c00: 6f1a ldr r2, [r3, #112] ; 0x70
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
8006c02: 687b ldr r3, [r7, #4]
8006c04: 681b ldr r3, [r3, #0]
8006c06: 430a orrs r2, r1
8006c08: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006c0a: 687b ldr r3, [r7, #4]
8006c0c: 681b ldr r3, [r3, #0]
8006c0e: 69db ldr r3, [r3, #28]
8006c10: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c12: 2001 movs r0, #1
8006c14: f7fd fed0 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006c18: 687b ldr r3, [r7, #4]
8006c1a: 681b ldr r3, [r3, #0]
8006c1c: 68fa ldr r2, [r7, #12]
8006c1e: 61da str r2, [r3, #28]
8006c20: e01e b.n 8006c60 <HAL_ETH_ConfigMAC+0x1d4>
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006c22: 687b ldr r3, [r7, #4]
8006c24: 681b ldr r3, [r3, #0]
8006c26: 681b ldr r3, [r3, #0]
8006c28: 60fb str r3, [r7, #12]
/* Clear FES and DM bits */
tmpreg &= ~((uint32_t)0x00004800);
8006c2a: 68fb ldr r3, [r7, #12]
8006c2c: f423 4390 bic.w r3, r3, #18432 ; 0x4800
8006c30: 60fb str r3, [r7, #12]
tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
8006c32: 687b ldr r3, [r7, #4]
8006c34: 689a ldr r2, [r3, #8]
8006c36: 687b ldr r3, [r7, #4]
8006c38: 68db ldr r3, [r3, #12]
8006c3a: 4313 orrs r3, r2
8006c3c: 68fa ldr r2, [r7, #12]
8006c3e: 4313 orrs r3, r2
8006c40: 60fb str r3, [r7, #12]
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006c42: 687b ldr r3, [r7, #4]
8006c44: 681b ldr r3, [r3, #0]
8006c46: 68fa ldr r2, [r7, #12]
8006c48: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006c4a: 687b ldr r3, [r7, #4]
8006c4c: 681b ldr r3, [r3, #0]
8006c4e: 681b ldr r3, [r3, #0]
8006c50: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8006c52: 2001 movs r0, #1
8006c54: f7fd feb0 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006c58: 687b ldr r3, [r7, #4]
8006c5a: 681b ldr r3, [r3, #0]
8006c5c: 68fa ldr r2, [r7, #12]
8006c5e: 601a str r2, [r3, #0]
}
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
8006c60: 687b ldr r3, [r7, #4]
8006c62: 2201 movs r2, #1
8006c64: f883 2044 strb.w r2, [r3, #68] ; 0x44
/* Process Unlocked */
__HAL_UNLOCK(heth);
8006c68: 687b ldr r3, [r7, #4]
8006c6a: 2200 movs r2, #0
8006c6c: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Return function status */
return HAL_OK;
8006c70: 2300 movs r3, #0
}
8006c72: 4618 mov r0, r3
8006c74: 3710 adds r7, #16
8006c76: 46bd mov sp, r7
8006c78: bd80 pop {r7, pc}
8006c7a: bf00 nop
8006c7c: ff20810f .word 0xff20810f
08006c80 <ETH_MACDMAConfig>:
* the configuration information for ETHERNET module
* @param err Ethernet Init error
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
{
8006c80: b580 push {r7, lr}
8006c82: b0b0 sub sp, #192 ; 0xc0
8006c84: af00 add r7, sp, #0
8006c86: 6078 str r0, [r7, #4]
8006c88: 6039 str r1, [r7, #0]
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
uint32_t tmpreg = 0;
8006c8a: 2300 movs r3, #0
8006c8c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
8006c90: 683b ldr r3, [r7, #0]
8006c92: 2b00 cmp r3, #0
8006c94: d007 beq.n 8006ca6 <ETH_MACDMAConfig+0x26>
{
/* Set Ethernet duplex mode to Full-duplex */
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
8006c96: 687b ldr r3, [r7, #4]
8006c98: f44f 6200 mov.w r2, #2048 ; 0x800
8006c9c: 60da str r2, [r3, #12]
/* Set Ethernet speed to 100M */
(heth->Init).Speed = ETH_SPEED_100M;
8006c9e: 687b ldr r3, [r7, #4]
8006ca0: f44f 4280 mov.w r2, #16384 ; 0x4000
8006ca4: 609a str r2, [r3, #8]
}
/* Ethernet MAC default initialization **************************************/
macinit.Watchdog = ETH_WATCHDOG_ENABLE;
8006ca6: 2300 movs r3, #0
8006ca8: 64bb str r3, [r7, #72] ; 0x48
macinit.Jabber = ETH_JABBER_ENABLE;
8006caa: 2300 movs r3, #0
8006cac: 64fb str r3, [r7, #76] ; 0x4c
macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
8006cae: 2300 movs r3, #0
8006cb0: 653b str r3, [r7, #80] ; 0x50
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
8006cb2: 2300 movs r3, #0
8006cb4: 657b str r3, [r7, #84] ; 0x54
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
8006cb6: 2300 movs r3, #0
8006cb8: 65bb str r3, [r7, #88] ; 0x58
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
8006cba: 2300 movs r3, #0
8006cbc: 65fb str r3, [r7, #92] ; 0x5c
if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
8006cbe: 687b ldr r3, [r7, #4]
8006cc0: 69db ldr r3, [r3, #28]
8006cc2: 2b00 cmp r3, #0
8006cc4: d103 bne.n 8006cce <ETH_MACDMAConfig+0x4e>
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
8006cc6: f44f 6380 mov.w r3, #1024 ; 0x400
8006cca: 663b str r3, [r7, #96] ; 0x60
8006ccc: e001 b.n 8006cd2 <ETH_MACDMAConfig+0x52>
}
else
{
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
8006cce: 2300 movs r3, #0
8006cd0: 663b str r3, [r7, #96] ; 0x60
}
macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
8006cd2: f44f 7300 mov.w r3, #512 ; 0x200
8006cd6: 667b str r3, [r7, #100] ; 0x64
macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
8006cd8: 2300 movs r3, #0
8006cda: 66bb str r3, [r7, #104] ; 0x68
macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
8006cdc: 2300 movs r3, #0
8006cde: 66fb str r3, [r7, #108] ; 0x6c
macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
8006ce0: 2300 movs r3, #0
8006ce2: 673b str r3, [r7, #112] ; 0x70
macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
8006ce4: 2300 movs r3, #0
8006ce6: 677b str r3, [r7, #116] ; 0x74
macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
8006ce8: 2300 movs r3, #0
8006cea: 67bb str r3, [r7, #120] ; 0x78
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
8006cec: 2340 movs r3, #64 ; 0x40
8006cee: 67fb str r3, [r7, #124] ; 0x7c
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
8006cf0: 2300 movs r3, #0
8006cf2: f8c7 3080 str.w r3, [r7, #128] ; 0x80
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
8006cf6: 2300 movs r3, #0
8006cf8: f8c7 3084 str.w r3, [r7, #132] ; 0x84
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
8006cfc: 2300 movs r3, #0
8006cfe: f8c7 3088 str.w r3, [r7, #136] ; 0x88
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
8006d02: 2300 movs r3, #0
8006d04: f8c7 308c str.w r3, [r7, #140] ; 0x8c
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
8006d08: 2300 movs r3, #0
8006d0a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
macinit.HashTableHigh = 0x0;
8006d0e: 2300 movs r3, #0
8006d10: f8c7 3094 str.w r3, [r7, #148] ; 0x94
macinit.HashTableLow = 0x0;
8006d14: 2300 movs r3, #0
8006d16: f8c7 3098 str.w r3, [r7, #152] ; 0x98
macinit.PauseTime = 0x0;
8006d1a: 2300 movs r3, #0
8006d1c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
8006d20: 2380 movs r3, #128 ; 0x80
8006d22: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
8006d26: 2300 movs r3, #0
8006d28: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
8006d2c: 2300 movs r3, #0
8006d2e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
8006d32: 2300 movs r3, #0
8006d34: f8c7 30ac str.w r3, [r7, #172] ; 0xac
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
8006d38: 2300 movs r3, #0
8006d3a: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
8006d3e: 2300 movs r3, #0
8006d40: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier = 0x0;
8006d44: 2300 movs r3, #0
8006d46: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
tmpreg = (heth->Instance)->MACCR;
8006d4a: 687b ldr r3, [r7, #4]
8006d4c: 681b ldr r3, [r3, #0]
8006d4e: 681b ldr r3, [r3, #0]
8006d50: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear WD, PCE, PS, TE and RE bits */
tmpreg &= ETH_MACCR_CLEAR_MASK;
8006d54: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d58: 4bab ldr r3, [pc, #684] ; (8007008 <ETH_MACDMAConfig+0x388>)
8006d5a: 4013 ands r3, r2
8006d5c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the IPCO bit according to ETH ChecksumOffload value */
/* Set the DR bit according to ETH RetryTransmission value */
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d60: 6cba ldr r2, [r7, #72] ; 0x48
macinit.Jabber |
8006d62: 6cfb ldr r3, [r7, #76] ; 0x4c
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d64: 431a orrs r2, r3
macinit.InterFrameGap |
8006d66: 6d3b ldr r3, [r7, #80] ; 0x50
macinit.Jabber |
8006d68: 431a orrs r2, r3
macinit.CarrierSense |
8006d6a: 6d7b ldr r3, [r7, #84] ; 0x54
macinit.InterFrameGap |
8006d6c: 431a orrs r2, r3
(heth->Init).Speed |
8006d6e: 687b ldr r3, [r7, #4]
8006d70: 689b ldr r3, [r3, #8]
macinit.CarrierSense |
8006d72: 431a orrs r2, r3
macinit.ReceiveOwn |
8006d74: 6dbb ldr r3, [r7, #88] ; 0x58
(heth->Init).Speed |
8006d76: 431a orrs r2, r3
macinit.LoopbackMode |
8006d78: 6dfb ldr r3, [r7, #92] ; 0x5c
macinit.ReceiveOwn |
8006d7a: 431a orrs r2, r3
(heth->Init).DuplexMode |
8006d7c: 687b ldr r3, [r7, #4]
8006d7e: 68db ldr r3, [r3, #12]
macinit.LoopbackMode |
8006d80: 431a orrs r2, r3
macinit.ChecksumOffload |
8006d82: 6e3b ldr r3, [r7, #96] ; 0x60
(heth->Init).DuplexMode |
8006d84: 431a orrs r2, r3
macinit.RetryTransmission |
8006d86: 6e7b ldr r3, [r7, #100] ; 0x64
macinit.ChecksumOffload |
8006d88: 431a orrs r2, r3
macinit.AutomaticPadCRCStrip |
8006d8a: 6ebb ldr r3, [r7, #104] ; 0x68
macinit.RetryTransmission |
8006d8c: 431a orrs r2, r3
macinit.BackOffLimit |
8006d8e: 6efb ldr r3, [r7, #108] ; 0x6c
macinit.AutomaticPadCRCStrip |
8006d90: 431a orrs r2, r3
macinit.DeferralCheck);
8006d92: 6f3b ldr r3, [r7, #112] ; 0x70
macinit.BackOffLimit |
8006d94: 4313 orrs r3, r2
tmpreg |= (uint32_t)(macinit.Watchdog |
8006d96: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006d9a: 4313 orrs r3, r2
8006d9c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACCR */
(heth->Instance)->MACCR = (uint32_t)tmpreg;
8006da0: 687b ldr r3, [r7, #4]
8006da2: 681b ldr r3, [r3, #0]
8006da4: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006da8: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8006daa: 687b ldr r3, [r7, #4]
8006dac: 681b ldr r3, [r3, #0]
8006dae: 681b ldr r3, [r3, #0]
8006db0: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006db4: 2001 movs r0, #1
8006db6: f7fd fdff bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8006dba: 687b ldr r3, [r7, #4]
8006dbc: 681b ldr r3, [r3, #0]
8006dbe: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006dc2: 601a str r2, [r3, #0]
/* Set the DAIF bit according to ETH DestinationAddrFilter value */
/* Set the PR bit according to ETH PromiscuousMode value */
/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
/* Write to ETHERNET MACFFR */
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dc4: 6f7a ldr r2, [r7, #116] ; 0x74
macinit.SourceAddrFilter |
8006dc6: 6fbb ldr r3, [r7, #120] ; 0x78
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dc8: 431a orrs r2, r3
macinit.PassControlFrames |
8006dca: 6ffb ldr r3, [r7, #124] ; 0x7c
macinit.SourceAddrFilter |
8006dcc: 431a orrs r2, r3
macinit.BroadcastFramesReception |
8006dce: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
macinit.PassControlFrames |
8006dd2: 431a orrs r2, r3
macinit.DestinationAddrFilter |
8006dd4: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
macinit.BroadcastFramesReception |
8006dd8: 431a orrs r2, r3
macinit.PromiscuousMode |
8006dda: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
macinit.DestinationAddrFilter |
8006dde: 431a orrs r2, r3
macinit.MulticastFramesFilter |
8006de0: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
macinit.PromiscuousMode |
8006de4: ea42 0103 orr.w r1, r2, r3
macinit.UnicastFramesFilter);
8006de8: f8d7 2090 ldr.w r2, [r7, #144] ; 0x90
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006dec: 687b ldr r3, [r7, #4]
8006dee: 681b ldr r3, [r3, #0]
macinit.MulticastFramesFilter |
8006df0: 430a orrs r2, r1
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
8006df2: 605a str r2, [r3, #4]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFFR;
8006df4: 687b ldr r3, [r7, #4]
8006df6: 681b ldr r3, [r3, #0]
8006df8: 685b ldr r3, [r3, #4]
8006dfa: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006dfe: 2001 movs r0, #1
8006e00: f7fd fdda bl 80049b8 <HAL_Delay>
(heth->Instance)->MACFFR = tmpreg;
8006e04: 687b ldr r3, [r7, #4]
8006e06: 681b ldr r3, [r3, #0]
8006e08: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e0c: 605a str r2, [r3, #4]
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
8006e0e: 687b ldr r3, [r7, #4]
8006e10: 681b ldr r3, [r3, #0]
8006e12: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
8006e16: 609a str r2, [r3, #8]
/* Write to ETHERNET MACHTLR */
(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
8006e18: 687b ldr r3, [r7, #4]
8006e1a: 681b ldr r3, [r3, #0]
8006e1c: f8d7 2098 ldr.w r2, [r7, #152] ; 0x98
8006e20: 60da str r2, [r3, #12]
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
tmpreg = (heth->Instance)->MACFCR;
8006e22: 687b ldr r3, [r7, #4]
8006e24: 681b ldr r3, [r3, #0]
8006e26: 699b ldr r3, [r3, #24]
8006e28: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_MACFCR_CLEAR_MASK;
8006e2c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e30: f64f 7341 movw r3, #65345 ; 0xff41
8006e34: 4013 ands r3, r2
8006e36: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
/* Set the PLT bit according to ETH PauseLowThreshold value */
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e3a: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8006e3e: 041a lsls r2, r3, #16
macinit.ZeroQuantaPause |
8006e40: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e44: 431a orrs r2, r3
macinit.PauseLowThreshold |
8006e46: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
macinit.ZeroQuantaPause |
8006e4a: 431a orrs r2, r3
macinit.UnicastPauseFrameDetect |
8006e4c: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
macinit.PauseLowThreshold |
8006e50: 431a orrs r2, r3
macinit.ReceiveFlowControl |
8006e52: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
macinit.UnicastPauseFrameDetect |
8006e56: 431a orrs r2, r3
macinit.TransmitFlowControl);
8006e58: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
macinit.ReceiveFlowControl |
8006e5c: 4313 orrs r3, r2
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
8006e5e: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e62: 4313 orrs r3, r2
8006e64: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET MACFCR */
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
8006e68: 687b ldr r3, [r7, #4]
8006e6a: 681b ldr r3, [r3, #0]
8006e6c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e70: 619a str r2, [r3, #24]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACFCR;
8006e72: 687b ldr r3, [r7, #4]
8006e74: 681b ldr r3, [r3, #0]
8006e76: 699b ldr r3, [r3, #24]
8006e78: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006e7c: 2001 movs r0, #1
8006e7e: f7fd fd9b bl 80049b8 <HAL_Delay>
(heth->Instance)->MACFCR = tmpreg;
8006e82: 687b ldr r3, [r7, #4]
8006e84: 681b ldr r3, [r3, #0]
8006e86: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006e8a: 619a str r2, [r3, #24]
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
/* Set the VL bit according to ETH VLANTagIdentifier value */
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006e8c: f8d7 10b4 ldr.w r1, [r7, #180] ; 0xb4
macinit.VLANTagIdentifier);
8006e90: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
8006e94: 687b ldr r3, [r7, #4]
8006e96: 681b ldr r3, [r3, #0]
8006e98: 430a orrs r2, r1
8006e9a: 61da str r2, [r3, #28]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACVLANTR;
8006e9c: 687b ldr r3, [r7, #4]
8006e9e: 681b ldr r3, [r3, #0]
8006ea0: 69db ldr r3, [r3, #28]
8006ea2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006ea6: 2001 movs r0, #1
8006ea8: f7fd fd86 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACVLANTR = tmpreg;
8006eac: 687b ldr r3, [r7, #4]
8006eae: 681b ldr r3, [r3, #0]
8006eb0: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006eb4: 61da str r2, [r3, #28]
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
8006eb6: 2300 movs r3, #0
8006eb8: 60bb str r3, [r7, #8]
dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
8006eba: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006ebe: 60fb str r3, [r7, #12]
dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
8006ec0: 2300 movs r3, #0
8006ec2: 613b str r3, [r7, #16]
dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
8006ec4: f44f 1300 mov.w r3, #2097152 ; 0x200000
8006ec8: 617b str r3, [r7, #20]
dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
8006eca: 2300 movs r3, #0
8006ecc: 61bb str r3, [r7, #24]
dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
8006ece: 2300 movs r3, #0
8006ed0: 61fb str r3, [r7, #28]
dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
8006ed2: 2300 movs r3, #0
8006ed4: 623b str r3, [r7, #32]
dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
8006ed6: 2300 movs r3, #0
8006ed8: 627b str r3, [r7, #36] ; 0x24
dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
8006eda: 2304 movs r3, #4
8006edc: 62bb str r3, [r7, #40] ; 0x28
dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
8006ede: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006ee2: 62fb str r3, [r7, #44] ; 0x2c
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
8006ee4: f44f 3380 mov.w r3, #65536 ; 0x10000
8006ee8: 633b str r3, [r7, #48] ; 0x30
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
8006eea: f44f 0380 mov.w r3, #4194304 ; 0x400000
8006eee: 637b str r3, [r7, #52] ; 0x34
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
8006ef0: f44f 5300 mov.w r3, #8192 ; 0x2000
8006ef4: 63bb str r3, [r7, #56] ; 0x38
dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
8006ef6: 2380 movs r3, #128 ; 0x80
8006ef8: 63fb str r3, [r7, #60] ; 0x3c
dmainit.DescriptorSkipLength = 0x0;
8006efa: 2300 movs r3, #0
8006efc: 643b str r3, [r7, #64] ; 0x40
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
8006efe: 2300 movs r3, #0
8006f00: 647b str r3, [r7, #68] ; 0x44
/* Get the ETHERNET DMAOMR value */
tmpreg = (heth->Instance)->DMAOMR;
8006f02: 687b ldr r3, [r7, #4]
8006f04: 681a ldr r2, [r3, #0]
8006f06: f241 0318 movw r3, #4120 ; 0x1018
8006f0a: 4413 add r3, r2
8006f0c: 681b ldr r3, [r3, #0]
8006f0e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Clear xx bits */
tmpreg &= ETH_DMAOMR_CLEAR_MASK;
8006f12: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f16: 4b3d ldr r3, [pc, #244] ; (800700c <ETH_MACDMAConfig+0x38c>)
8006f18: 4013 ands r3, r2
8006f1a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Set the TTC bit according to ETH TransmitThresholdControl value */
/* Set the FEF bit according to ETH ForwardErrorFrames value */
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f1e: 68ba ldr r2, [r7, #8]
dmainit.ReceiveStoreForward |
8006f20: 68fb ldr r3, [r7, #12]
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f22: 431a orrs r2, r3
dmainit.FlushReceivedFrame |
8006f24: 693b ldr r3, [r7, #16]
dmainit.ReceiveStoreForward |
8006f26: 431a orrs r2, r3
dmainit.TransmitStoreForward |
8006f28: 697b ldr r3, [r7, #20]
dmainit.FlushReceivedFrame |
8006f2a: 431a orrs r2, r3
dmainit.TransmitThresholdControl |
8006f2c: 69bb ldr r3, [r7, #24]
dmainit.TransmitStoreForward |
8006f2e: 431a orrs r2, r3
dmainit.ForwardErrorFrames |
8006f30: 69fb ldr r3, [r7, #28]
dmainit.TransmitThresholdControl |
8006f32: 431a orrs r2, r3
dmainit.ForwardUndersizedGoodFrames |
8006f34: 6a3b ldr r3, [r7, #32]
dmainit.ForwardErrorFrames |
8006f36: 431a orrs r2, r3
dmainit.ReceiveThresholdControl |
8006f38: 6a7b ldr r3, [r7, #36] ; 0x24
dmainit.ForwardUndersizedGoodFrames |
8006f3a: 431a orrs r2, r3
dmainit.SecondFrameOperate);
8006f3c: 6abb ldr r3, [r7, #40] ; 0x28
dmainit.ReceiveThresholdControl |
8006f3e: 4313 orrs r3, r2
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
8006f40: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f44: 4313 orrs r3, r2
8006f46: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
/* Write to ETHERNET DMAOMR */
(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
8006f4a: 687b ldr r3, [r7, #4]
8006f4c: 681a ldr r2, [r3, #0]
8006f4e: f241 0318 movw r3, #4120 ; 0x1018
8006f52: 4413 add r3, r2
8006f54: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f58: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
8006f5a: 687b ldr r3, [r7, #4]
8006f5c: 681a ldr r2, [r3, #0]
8006f5e: f241 0318 movw r3, #4120 ; 0x1018
8006f62: 4413 add r3, r2
8006f64: 681b ldr r3, [r3, #0]
8006f66: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006f6a: 2001 movs r0, #1
8006f6c: f7fd fd24 bl 80049b8 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
8006f70: 687b ldr r3, [r7, #4]
8006f72: 681a ldr r2, [r3, #0]
8006f74: f241 0318 movw r3, #4120 ; 0x1018
8006f78: 4413 add r3, r2
8006f7a: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006f7e: 601a str r2, [r3, #0]
/* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
/* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
/* Set the DSL bit according to ETH DesciptorSkipLength value */
/* Set the PR and DA bits according to ETH DMAArbitration value */
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f80: 6afa ldr r2, [r7, #44] ; 0x2c
dmainit.FixedBurst |
8006f82: 6b3b ldr r3, [r7, #48] ; 0x30
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f84: 431a orrs r2, r3
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006f86: 6b7b ldr r3, [r7, #52] ; 0x34
dmainit.FixedBurst |
8006f88: 431a orrs r2, r3
dmainit.TxDMABurstLength |
8006f8a: 6bbb ldr r3, [r7, #56] ; 0x38
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
8006f8c: 431a orrs r2, r3
dmainit.EnhancedDescriptorFormat |
8006f8e: 6bfb ldr r3, [r7, #60] ; 0x3c
dmainit.TxDMABurstLength |
8006f90: 431a orrs r2, r3
(dmainit.DescriptorSkipLength << 2) |
8006f92: 6c3b ldr r3, [r7, #64] ; 0x40
8006f94: 009b lsls r3, r3, #2
dmainit.EnhancedDescriptorFormat |
8006f96: 431a orrs r2, r3
dmainit.DMAArbitration |
8006f98: 6c7b ldr r3, [r7, #68] ; 0x44
(dmainit.DescriptorSkipLength << 2) |
8006f9a: 431a orrs r2, r3
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
8006f9c: 687b ldr r3, [r7, #4]
8006f9e: 681b ldr r3, [r3, #0]
8006fa0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000
8006fa4: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006fa8: 601a str r2, [r3, #0]
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMABMR;
8006faa: 687b ldr r3, [r7, #4]
8006fac: 681b ldr r3, [r3, #0]
8006fae: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006fb2: 681b ldr r3, [r3, #0]
8006fb4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
HAL_Delay(ETH_REG_WRITE_DELAY);
8006fb8: 2001 movs r0, #1
8006fba: f7fd fcfd bl 80049b8 <HAL_Delay>
(heth->Instance)->DMABMR = tmpreg;
8006fbe: 687b ldr r3, [r7, #4]
8006fc0: 681b ldr r3, [r3, #0]
8006fc2: f503 5380 add.w r3, r3, #4096 ; 0x1000
8006fc6: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
8006fca: 601a str r2, [r3, #0]
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
8006fcc: 687b ldr r3, [r7, #4]
8006fce: 699b ldr r3, [r3, #24]
8006fd0: 2b01 cmp r3, #1
8006fd2: d10d bne.n 8006ff0 <ETH_MACDMAConfig+0x370>
{
/* Enable the Ethernet Rx Interrupt */
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
8006fd4: 687b ldr r3, [r7, #4]
8006fd6: 681a ldr r2, [r3, #0]
8006fd8: f241 031c movw r3, #4124 ; 0x101c
8006fdc: 4413 add r3, r2
8006fde: 681b ldr r3, [r3, #0]
8006fe0: 687a ldr r2, [r7, #4]
8006fe2: 6811 ldr r1, [r2, #0]
8006fe4: 4a0a ldr r2, [pc, #40] ; (8007010 <ETH_MACDMAConfig+0x390>)
8006fe6: 431a orrs r2, r3
8006fe8: f241 031c movw r3, #4124 ; 0x101c
8006fec: 440b add r3, r1
8006fee: 601a str r2, [r3, #0]
}
/* Initialize MAC address in ethernet MAC */
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
8006ff0: 687b ldr r3, [r7, #4]
8006ff2: 695b ldr r3, [r3, #20]
8006ff4: 461a mov r2, r3
8006ff6: 2100 movs r1, #0
8006ff8: 6878 ldr r0, [r7, #4]
8006ffa: f000 f80b bl 8007014 <ETH_MACAddressConfig>
}
8006ffe: bf00 nop
8007000: 37c0 adds r7, #192 ; 0xc0
8007002: 46bd mov sp, r7
8007004: bd80 pop {r7, pc}
8007006: bf00 nop
8007008: ff20810f .word 0xff20810f
800700c: f8de3f23 .word 0xf8de3f23
8007010: 00010040 .word 0x00010040
08007014 <ETH_MACAddressConfig>:
* @arg ETH_MAC_Address3: MAC Address3
* @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
8007014: b480 push {r7}
8007016: b087 sub sp, #28
8007018: af00 add r7, sp, #0
800701a: 60f8 str r0, [r7, #12]
800701c: 60b9 str r1, [r7, #8]
800701e: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
8007020: 687b ldr r3, [r7, #4]
8007022: 3305 adds r3, #5
8007024: 781b ldrb r3, [r3, #0]
8007026: 021b lsls r3, r3, #8
8007028: 687a ldr r2, [r7, #4]
800702a: 3204 adds r2, #4
800702c: 7812 ldrb r2, [r2, #0]
800702e: 4313 orrs r3, r2
8007030: 617b str r3, [r7, #20]
/* Load the selected MAC address high register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
8007032: 68ba ldr r2, [r7, #8]
8007034: 4b11 ldr r3, [pc, #68] ; (800707c <ETH_MACAddressConfig+0x68>)
8007036: 4413 add r3, r2
8007038: 461a mov r2, r3
800703a: 697b ldr r3, [r7, #20]
800703c: 6013 str r3, [r2, #0]
/* Calculate the selected MAC address low register */
tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
800703e: 687b ldr r3, [r7, #4]
8007040: 3303 adds r3, #3
8007042: 781b ldrb r3, [r3, #0]
8007044: 061a lsls r2, r3, #24
8007046: 687b ldr r3, [r7, #4]
8007048: 3302 adds r3, #2
800704a: 781b ldrb r3, [r3, #0]
800704c: 041b lsls r3, r3, #16
800704e: 431a orrs r2, r3
8007050: 687b ldr r3, [r7, #4]
8007052: 3301 adds r3, #1
8007054: 781b ldrb r3, [r3, #0]
8007056: 021b lsls r3, r3, #8
8007058: 4313 orrs r3, r2
800705a: 687a ldr r2, [r7, #4]
800705c: 7812 ldrb r2, [r2, #0]
800705e: 4313 orrs r3, r2
8007060: 617b str r3, [r7, #20]
/* Load the selected MAC address low register */
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
8007062: 68ba ldr r2, [r7, #8]
8007064: 4b06 ldr r3, [pc, #24] ; (8007080 <ETH_MACAddressConfig+0x6c>)
8007066: 4413 add r3, r2
8007068: 461a mov r2, r3
800706a: 697b ldr r3, [r7, #20]
800706c: 6013 str r3, [r2, #0]
}
800706e: bf00 nop
8007070: 371c adds r7, #28
8007072: 46bd mov sp, r7
8007074: f85d 7b04 ldr.w r7, [sp], #4
8007078: 4770 bx lr
800707a: bf00 nop
800707c: 40028040 .word 0x40028040
8007080: 40028044 .word 0x40028044
08007084 <ETH_MACTransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
8007084: b580 push {r7, lr}
8007086: b084 sub sp, #16
8007088: af00 add r7, sp, #0
800708a: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
800708c: 2300 movs r3, #0
800708e: 60fb str r3, [r7, #12]
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
8007090: 687b ldr r3, [r7, #4]
8007092: 681b ldr r3, [r3, #0]
8007094: 681a ldr r2, [r3, #0]
8007096: 687b ldr r3, [r7, #4]
8007098: 681b ldr r3, [r3, #0]
800709a: f042 0208 orr.w r2, r2, #8
800709e: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
80070a0: 687b ldr r3, [r7, #4]
80070a2: 681b ldr r3, [r3, #0]
80070a4: 681b ldr r3, [r3, #0]
80070a6: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80070a8: 2001 movs r0, #1
80070aa: f7fd fc85 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
80070ae: 687b ldr r3, [r7, #4]
80070b0: 681b ldr r3, [r3, #0]
80070b2: 68fa ldr r2, [r7, #12]
80070b4: 601a str r2, [r3, #0]
}
80070b6: bf00 nop
80070b8: 3710 adds r7, #16
80070ba: 46bd mov sp, r7
80070bc: bd80 pop {r7, pc}
080070be <ETH_MACTransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
80070be: b580 push {r7, lr}
80070c0: b084 sub sp, #16
80070c2: af00 add r7, sp, #0
80070c4: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
80070c6: 2300 movs r3, #0
80070c8: 60fb str r3, [r7, #12]
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
80070ca: 687b ldr r3, [r7, #4]
80070cc: 681b ldr r3, [r3, #0]
80070ce: 681a ldr r2, [r3, #0]
80070d0: 687b ldr r3, [r7, #4]
80070d2: 681b ldr r3, [r3, #0]
80070d4: f022 0208 bic.w r2, r2, #8
80070d8: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
80070da: 687b ldr r3, [r7, #4]
80070dc: 681b ldr r3, [r3, #0]
80070de: 681b ldr r3, [r3, #0]
80070e0: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
80070e2: 2001 movs r0, #1
80070e4: f7fd fc68 bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
80070e8: 687b ldr r3, [r7, #4]
80070ea: 681b ldr r3, [r3, #0]
80070ec: 68fa ldr r2, [r7, #12]
80070ee: 601a str r2, [r3, #0]
}
80070f0: bf00 nop
80070f2: 3710 adds r7, #16
80070f4: 46bd mov sp, r7
80070f6: bd80 pop {r7, pc}
080070f8 <ETH_MACReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
80070f8: b580 push {r7, lr}
80070fa: b084 sub sp, #16
80070fc: af00 add r7, sp, #0
80070fe: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8007100: 2300 movs r3, #0
8007102: 60fb str r3, [r7, #12]
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
8007104: 687b ldr r3, [r7, #4]
8007106: 681b ldr r3, [r3, #0]
8007108: 681a ldr r2, [r3, #0]
800710a: 687b ldr r3, [r7, #4]
800710c: 681b ldr r3, [r3, #0]
800710e: f042 0204 orr.w r2, r2, #4
8007112: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
8007114: 687b ldr r3, [r7, #4]
8007116: 681b ldr r3, [r3, #0]
8007118: 681b ldr r3, [r3, #0]
800711a: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
800711c: 2001 movs r0, #1
800711e: f7fd fc4b bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
8007122: 687b ldr r3, [r7, #4]
8007124: 681b ldr r3, [r3, #0]
8007126: 68fa ldr r2, [r7, #12]
8007128: 601a str r2, [r3, #0]
}
800712a: bf00 nop
800712c: 3710 adds r7, #16
800712e: 46bd mov sp, r7
8007130: bd80 pop {r7, pc}
08007132 <ETH_MACReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
8007132: b580 push {r7, lr}
8007134: b084 sub sp, #16
8007136: af00 add r7, sp, #0
8007138: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
800713a: 2300 movs r3, #0
800713c: 60fb str r3, [r7, #12]
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
800713e: 687b ldr r3, [r7, #4]
8007140: 681b ldr r3, [r3, #0]
8007142: 681a ldr r2, [r3, #0]
8007144: 687b ldr r3, [r7, #4]
8007146: 681b ldr r3, [r3, #0]
8007148: f022 0204 bic.w r2, r2, #4
800714c: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->MACCR;
800714e: 687b ldr r3, [r7, #4]
8007150: 681b ldr r3, [r3, #0]
8007152: 681b ldr r3, [r3, #0]
8007154: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8007156: 2001 movs r0, #1
8007158: f7fd fc2e bl 80049b8 <HAL_Delay>
(heth->Instance)->MACCR = tmpreg;
800715c: 687b ldr r3, [r7, #4]
800715e: 681b ldr r3, [r3, #0]
8007160: 68fa ldr r2, [r7, #12]
8007162: 601a str r2, [r3, #0]
}
8007164: bf00 nop
8007166: 3710 adds r7, #16
8007168: 46bd mov sp, r7
800716a: bd80 pop {r7, pc}
0800716c <ETH_DMATransmissionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
{
800716c: b480 push {r7}
800716e: b083 sub sp, #12
8007170: af00 add r7, sp, #0
8007172: 6078 str r0, [r7, #4]
/* Enable the DMA transmission */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
8007174: 687b ldr r3, [r7, #4]
8007176: 681a ldr r2, [r3, #0]
8007178: f241 0318 movw r3, #4120 ; 0x1018
800717c: 4413 add r3, r2
800717e: 681b ldr r3, [r3, #0]
8007180: 687a ldr r2, [r7, #4]
8007182: 6811 ldr r1, [r2, #0]
8007184: f443 5200 orr.w r2, r3, #8192 ; 0x2000
8007188: f241 0318 movw r3, #4120 ; 0x1018
800718c: 440b add r3, r1
800718e: 601a str r2, [r3, #0]
}
8007190: bf00 nop
8007192: 370c adds r7, #12
8007194: 46bd mov sp, r7
8007196: f85d 7b04 ldr.w r7, [sp], #4
800719a: 4770 bx lr
0800719c <ETH_DMATransmissionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
{
800719c: b480 push {r7}
800719e: b083 sub sp, #12
80071a0: af00 add r7, sp, #0
80071a2: 6078 str r0, [r7, #4]
/* Disable the DMA transmission */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
80071a4: 687b ldr r3, [r7, #4]
80071a6: 681a ldr r2, [r3, #0]
80071a8: f241 0318 movw r3, #4120 ; 0x1018
80071ac: 4413 add r3, r2
80071ae: 681b ldr r3, [r3, #0]
80071b0: 687a ldr r2, [r7, #4]
80071b2: 6811 ldr r1, [r2, #0]
80071b4: f423 5200 bic.w r2, r3, #8192 ; 0x2000
80071b8: f241 0318 movw r3, #4120 ; 0x1018
80071bc: 440b add r3, r1
80071be: 601a str r2, [r3, #0]
}
80071c0: bf00 nop
80071c2: 370c adds r7, #12
80071c4: 46bd mov sp, r7
80071c6: f85d 7b04 ldr.w r7, [sp], #4
80071ca: 4770 bx lr
080071cc <ETH_DMAReceptionEnable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
{
80071cc: b480 push {r7}
80071ce: b083 sub sp, #12
80071d0: af00 add r7, sp, #0
80071d2: 6078 str r0, [r7, #4]
/* Enable the DMA reception */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
80071d4: 687b ldr r3, [r7, #4]
80071d6: 681a ldr r2, [r3, #0]
80071d8: f241 0318 movw r3, #4120 ; 0x1018
80071dc: 4413 add r3, r2
80071de: 681b ldr r3, [r3, #0]
80071e0: 687a ldr r2, [r7, #4]
80071e2: 6811 ldr r1, [r2, #0]
80071e4: f043 0202 orr.w r2, r3, #2
80071e8: f241 0318 movw r3, #4120 ; 0x1018
80071ec: 440b add r3, r1
80071ee: 601a str r2, [r3, #0]
}
80071f0: bf00 nop
80071f2: 370c adds r7, #12
80071f4: 46bd mov sp, r7
80071f6: f85d 7b04 ldr.w r7, [sp], #4
80071fa: 4770 bx lr
080071fc <ETH_DMAReceptionDisable>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
{
80071fc: b480 push {r7}
80071fe: b083 sub sp, #12
8007200: af00 add r7, sp, #0
8007202: 6078 str r0, [r7, #4]
/* Disable the DMA reception */
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
8007204: 687b ldr r3, [r7, #4]
8007206: 681a ldr r2, [r3, #0]
8007208: f241 0318 movw r3, #4120 ; 0x1018
800720c: 4413 add r3, r2
800720e: 681b ldr r3, [r3, #0]
8007210: 687a ldr r2, [r7, #4]
8007212: 6811 ldr r1, [r2, #0]
8007214: f023 0202 bic.w r2, r3, #2
8007218: f241 0318 movw r3, #4120 ; 0x1018
800721c: 440b add r3, r1
800721e: 601a str r2, [r3, #0]
}
8007220: bf00 nop
8007222: 370c adds r7, #12
8007224: 46bd mov sp, r7
8007226: f85d 7b04 ldr.w r7, [sp], #4
800722a: 4770 bx lr
0800722c <ETH_FlushTransmitFIFO>:
* @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
800722c: b580 push {r7, lr}
800722e: b084 sub sp, #16
8007230: af00 add r7, sp, #0
8007232: 6078 str r0, [r7, #4]
__IO uint32_t tmpreg = 0;
8007234: 2300 movs r3, #0
8007236: 60fb str r3, [r7, #12]
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
8007238: 687b ldr r3, [r7, #4]
800723a: 681a ldr r2, [r3, #0]
800723c: f241 0318 movw r3, #4120 ; 0x1018
8007240: 4413 add r3, r2
8007242: 681b ldr r3, [r3, #0]
8007244: 687a ldr r2, [r7, #4]
8007246: 6811 ldr r1, [r2, #0]
8007248: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
800724c: f241 0318 movw r3, #4120 ; 0x1018
8007250: 440b add r3, r1
8007252: 601a str r2, [r3, #0]
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
tmpreg = (heth->Instance)->DMAOMR;
8007254: 687b ldr r3, [r7, #4]
8007256: 681a ldr r2, [r3, #0]
8007258: f241 0318 movw r3, #4120 ; 0x1018
800725c: 4413 add r3, r2
800725e: 681b ldr r3, [r3, #0]
8007260: 60fb str r3, [r7, #12]
HAL_Delay(ETH_REG_WRITE_DELAY);
8007262: 2001 movs r0, #1
8007264: f7fd fba8 bl 80049b8 <HAL_Delay>
(heth->Instance)->DMAOMR = tmpreg;
8007268: 687b ldr r3, [r7, #4]
800726a: 6819 ldr r1, [r3, #0]
800726c: 68fa ldr r2, [r7, #12]
800726e: f241 0318 movw r3, #4120 ; 0x1018
8007272: 440b add r3, r1
8007274: 601a str r2, [r3, #0]
}
8007276: bf00 nop
8007278: 3710 adds r7, #16
800727a: 46bd mov sp, r7
800727c: bd80 pop {r7, pc}
...
08007280 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8007280: b480 push {r7}
8007282: b089 sub sp, #36 ; 0x24
8007284: af00 add r7, sp, #0
8007286: 6078 str r0, [r7, #4]
8007288: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
800728a: 2300 movs r3, #0
800728c: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
800728e: 2300 movs r3, #0
8007290: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8007292: 2300 movs r3, #0
8007294: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
8007296: 2300 movs r3, #0
8007298: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
800729a: 2300 movs r3, #0
800729c: 61fb str r3, [r7, #28]
800729e: e175 b.n 800758c <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
80072a0: 2201 movs r2, #1
80072a2: 69fb ldr r3, [r7, #28]
80072a4: fa02 f303 lsl.w r3, r2, r3
80072a8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80072aa: 683b ldr r3, [r7, #0]
80072ac: 681b ldr r3, [r3, #0]
80072ae: 697a ldr r2, [r7, #20]
80072b0: 4013 ands r3, r2
80072b2: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80072b4: 693a ldr r2, [r7, #16]
80072b6: 697b ldr r3, [r7, #20]
80072b8: 429a cmp r2, r3
80072ba: f040 8164 bne.w 8007586 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
80072be: 683b ldr r3, [r7, #0]
80072c0: 685b ldr r3, [r3, #4]
80072c2: 2b01 cmp r3, #1
80072c4: d00b beq.n 80072de <HAL_GPIO_Init+0x5e>
80072c6: 683b ldr r3, [r7, #0]
80072c8: 685b ldr r3, [r3, #4]
80072ca: 2b02 cmp r3, #2
80072cc: d007 beq.n 80072de <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80072ce: 683b ldr r3, [r7, #0]
80072d0: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
80072d2: 2b11 cmp r3, #17
80072d4: d003 beq.n 80072de <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80072d6: 683b ldr r3, [r7, #0]
80072d8: 685b ldr r3, [r3, #4]
80072da: 2b12 cmp r3, #18
80072dc: d130 bne.n 8007340 <HAL_GPIO_Init+0xc0>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80072de: 687b ldr r3, [r7, #4]
80072e0: 689b ldr r3, [r3, #8]
80072e2: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
80072e4: 69fb ldr r3, [r7, #28]
80072e6: 005b lsls r3, r3, #1
80072e8: 2203 movs r2, #3
80072ea: fa02 f303 lsl.w r3, r2, r3
80072ee: 43db mvns r3, r3
80072f0: 69ba ldr r2, [r7, #24]
80072f2: 4013 ands r3, r2
80072f4: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
80072f6: 683b ldr r3, [r7, #0]
80072f8: 68da ldr r2, [r3, #12]
80072fa: 69fb ldr r3, [r7, #28]
80072fc: 005b lsls r3, r3, #1
80072fe: fa02 f303 lsl.w r3, r2, r3
8007302: 69ba ldr r2, [r7, #24]
8007304: 4313 orrs r3, r2
8007306: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8007308: 687b ldr r3, [r7, #4]
800730a: 69ba ldr r2, [r7, #24]
800730c: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800730e: 687b ldr r3, [r7, #4]
8007310: 685b ldr r3, [r3, #4]
8007312: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8007314: 2201 movs r2, #1
8007316: 69fb ldr r3, [r7, #28]
8007318: fa02 f303 lsl.w r3, r2, r3
800731c: 43db mvns r3, r3
800731e: 69ba ldr r2, [r7, #24]
8007320: 4013 ands r3, r2
8007322: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
8007324: 683b ldr r3, [r7, #0]
8007326: 685b ldr r3, [r3, #4]
8007328: 091b lsrs r3, r3, #4
800732a: f003 0201 and.w r2, r3, #1
800732e: 69fb ldr r3, [r7, #28]
8007330: fa02 f303 lsl.w r3, r2, r3
8007334: 69ba ldr r2, [r7, #24]
8007336: 4313 orrs r3, r2
8007338: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
800733a: 687b ldr r3, [r7, #4]
800733c: 69ba ldr r2, [r7, #24]
800733e: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8007340: 687b ldr r3, [r7, #4]
8007342: 68db ldr r3, [r3, #12]
8007344: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
8007346: 69fb ldr r3, [r7, #28]
8007348: 005b lsls r3, r3, #1
800734a: 2203 movs r2, #3
800734c: fa02 f303 lsl.w r3, r2, r3
8007350: 43db mvns r3, r3
8007352: 69ba ldr r2, [r7, #24]
8007354: 4013 ands r3, r2
8007356: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
8007358: 683b ldr r3, [r7, #0]
800735a: 689a ldr r2, [r3, #8]
800735c: 69fb ldr r3, [r7, #28]
800735e: 005b lsls r3, r3, #1
8007360: fa02 f303 lsl.w r3, r2, r3
8007364: 69ba ldr r2, [r7, #24]
8007366: 4313 orrs r3, r2
8007368: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800736a: 687b ldr r3, [r7, #4]
800736c: 69ba ldr r2, [r7, #24]
800736e: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8007370: 683b ldr r3, [r7, #0]
8007372: 685b ldr r3, [r3, #4]
8007374: 2b02 cmp r3, #2
8007376: d003 beq.n 8007380 <HAL_GPIO_Init+0x100>
8007378: 683b ldr r3, [r7, #0]
800737a: 685b ldr r3, [r3, #4]
800737c: 2b12 cmp r3, #18
800737e: d123 bne.n 80073c8 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
8007380: 69fb ldr r3, [r7, #28]
8007382: 08da lsrs r2, r3, #3
8007384: 687b ldr r3, [r7, #4]
8007386: 3208 adds r2, #8
8007388: f853 3022 ldr.w r3, [r3, r2, lsl #2]
800738c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
800738e: 69fb ldr r3, [r7, #28]
8007390: f003 0307 and.w r3, r3, #7
8007394: 009b lsls r3, r3, #2
8007396: 220f movs r2, #15
8007398: fa02 f303 lsl.w r3, r2, r3
800739c: 43db mvns r3, r3
800739e: 69ba ldr r2, [r7, #24]
80073a0: 4013 ands r3, r2
80073a2: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
80073a4: 683b ldr r3, [r7, #0]
80073a6: 691a ldr r2, [r3, #16]
80073a8: 69fb ldr r3, [r7, #28]
80073aa: f003 0307 and.w r3, r3, #7
80073ae: 009b lsls r3, r3, #2
80073b0: fa02 f303 lsl.w r3, r2, r3
80073b4: 69ba ldr r2, [r7, #24]
80073b6: 4313 orrs r3, r2
80073b8: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
80073ba: 69fb ldr r3, [r7, #28]
80073bc: 08da lsrs r2, r3, #3
80073be: 687b ldr r3, [r7, #4]
80073c0: 3208 adds r2, #8
80073c2: 69b9 ldr r1, [r7, #24]
80073c4: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80073c8: 687b ldr r3, [r7, #4]
80073ca: 681b ldr r3, [r3, #0]
80073cc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
80073ce: 69fb ldr r3, [r7, #28]
80073d0: 005b lsls r3, r3, #1
80073d2: 2203 movs r2, #3
80073d4: fa02 f303 lsl.w r3, r2, r3
80073d8: 43db mvns r3, r3
80073da: 69ba ldr r2, [r7, #24]
80073dc: 4013 ands r3, r2
80073de: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
80073e0: 683b ldr r3, [r7, #0]
80073e2: 685b ldr r3, [r3, #4]
80073e4: f003 0203 and.w r2, r3, #3
80073e8: 69fb ldr r3, [r7, #28]
80073ea: 005b lsls r3, r3, #1
80073ec: fa02 f303 lsl.w r3, r2, r3
80073f0: 69ba ldr r2, [r7, #24]
80073f2: 4313 orrs r3, r2
80073f4: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
80073f6: 687b ldr r3, [r7, #4]
80073f8: 69ba ldr r2, [r7, #24]
80073fa: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
80073fc: 683b ldr r3, [r7, #0]
80073fe: 685b ldr r3, [r3, #4]
8007400: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8007404: 2b00 cmp r3, #0
8007406: f000 80be beq.w 8007586 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800740a: 4b65 ldr r3, [pc, #404] ; (80075a0 <HAL_GPIO_Init+0x320>)
800740c: 6c5b ldr r3, [r3, #68] ; 0x44
800740e: 4a64 ldr r2, [pc, #400] ; (80075a0 <HAL_GPIO_Init+0x320>)
8007410: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8007414: 6453 str r3, [r2, #68] ; 0x44
8007416: 4b62 ldr r3, [pc, #392] ; (80075a0 <HAL_GPIO_Init+0x320>)
8007418: 6c5b ldr r3, [r3, #68] ; 0x44
800741a: f403 4380 and.w r3, r3, #16384 ; 0x4000
800741e: 60fb str r3, [r7, #12]
8007420: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
8007422: 4a60 ldr r2, [pc, #384] ; (80075a4 <HAL_GPIO_Init+0x324>)
8007424: 69fb ldr r3, [r7, #28]
8007426: 089b lsrs r3, r3, #2
8007428: 3302 adds r3, #2
800742a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800742e: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8007430: 69fb ldr r3, [r7, #28]
8007432: f003 0303 and.w r3, r3, #3
8007436: 009b lsls r3, r3, #2
8007438: 220f movs r2, #15
800743a: fa02 f303 lsl.w r3, r2, r3
800743e: 43db mvns r3, r3
8007440: 69ba ldr r2, [r7, #24]
8007442: 4013 ands r3, r2
8007444: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8007446: 687b ldr r3, [r7, #4]
8007448: 4a57 ldr r2, [pc, #348] ; (80075a8 <HAL_GPIO_Init+0x328>)
800744a: 4293 cmp r3, r2
800744c: d037 beq.n 80074be <HAL_GPIO_Init+0x23e>
800744e: 687b ldr r3, [r7, #4]
8007450: 4a56 ldr r2, [pc, #344] ; (80075ac <HAL_GPIO_Init+0x32c>)
8007452: 4293 cmp r3, r2
8007454: d031 beq.n 80074ba <HAL_GPIO_Init+0x23a>
8007456: 687b ldr r3, [r7, #4]
8007458: 4a55 ldr r2, [pc, #340] ; (80075b0 <HAL_GPIO_Init+0x330>)
800745a: 4293 cmp r3, r2
800745c: d02b beq.n 80074b6 <HAL_GPIO_Init+0x236>
800745e: 687b ldr r3, [r7, #4]
8007460: 4a54 ldr r2, [pc, #336] ; (80075b4 <HAL_GPIO_Init+0x334>)
8007462: 4293 cmp r3, r2
8007464: d025 beq.n 80074b2 <HAL_GPIO_Init+0x232>
8007466: 687b ldr r3, [r7, #4]
8007468: 4a53 ldr r2, [pc, #332] ; (80075b8 <HAL_GPIO_Init+0x338>)
800746a: 4293 cmp r3, r2
800746c: d01f beq.n 80074ae <HAL_GPIO_Init+0x22e>
800746e: 687b ldr r3, [r7, #4]
8007470: 4a52 ldr r2, [pc, #328] ; (80075bc <HAL_GPIO_Init+0x33c>)
8007472: 4293 cmp r3, r2
8007474: d019 beq.n 80074aa <HAL_GPIO_Init+0x22a>
8007476: 687b ldr r3, [r7, #4]
8007478: 4a51 ldr r2, [pc, #324] ; (80075c0 <HAL_GPIO_Init+0x340>)
800747a: 4293 cmp r3, r2
800747c: d013 beq.n 80074a6 <HAL_GPIO_Init+0x226>
800747e: 687b ldr r3, [r7, #4]
8007480: 4a50 ldr r2, [pc, #320] ; (80075c4 <HAL_GPIO_Init+0x344>)
8007482: 4293 cmp r3, r2
8007484: d00d beq.n 80074a2 <HAL_GPIO_Init+0x222>
8007486: 687b ldr r3, [r7, #4]
8007488: 4a4f ldr r2, [pc, #316] ; (80075c8 <HAL_GPIO_Init+0x348>)
800748a: 4293 cmp r3, r2
800748c: d007 beq.n 800749e <HAL_GPIO_Init+0x21e>
800748e: 687b ldr r3, [r7, #4]
8007490: 4a4e ldr r2, [pc, #312] ; (80075cc <HAL_GPIO_Init+0x34c>)
8007492: 4293 cmp r3, r2
8007494: d101 bne.n 800749a <HAL_GPIO_Init+0x21a>
8007496: 2309 movs r3, #9
8007498: e012 b.n 80074c0 <HAL_GPIO_Init+0x240>
800749a: 230a movs r3, #10
800749c: e010 b.n 80074c0 <HAL_GPIO_Init+0x240>
800749e: 2308 movs r3, #8
80074a0: e00e b.n 80074c0 <HAL_GPIO_Init+0x240>
80074a2: 2307 movs r3, #7
80074a4: e00c b.n 80074c0 <HAL_GPIO_Init+0x240>
80074a6: 2306 movs r3, #6
80074a8: e00a b.n 80074c0 <HAL_GPIO_Init+0x240>
80074aa: 2305 movs r3, #5
80074ac: e008 b.n 80074c0 <HAL_GPIO_Init+0x240>
80074ae: 2304 movs r3, #4
80074b0: e006 b.n 80074c0 <HAL_GPIO_Init+0x240>
80074b2: 2303 movs r3, #3
80074b4: e004 b.n 80074c0 <HAL_GPIO_Init+0x240>
80074b6: 2302 movs r3, #2
80074b8: e002 b.n 80074c0 <HAL_GPIO_Init+0x240>
80074ba: 2301 movs r3, #1
80074bc: e000 b.n 80074c0 <HAL_GPIO_Init+0x240>
80074be: 2300 movs r3, #0
80074c0: 69fa ldr r2, [r7, #28]
80074c2: f002 0203 and.w r2, r2, #3
80074c6: 0092 lsls r2, r2, #2
80074c8: 4093 lsls r3, r2
80074ca: 69ba ldr r2, [r7, #24]
80074cc: 4313 orrs r3, r2
80074ce: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
80074d0: 4934 ldr r1, [pc, #208] ; (80075a4 <HAL_GPIO_Init+0x324>)
80074d2: 69fb ldr r3, [r7, #28]
80074d4: 089b lsrs r3, r3, #2
80074d6: 3302 adds r3, #2
80074d8: 69ba ldr r2, [r7, #24]
80074da: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80074de: 4b3c ldr r3, [pc, #240] ; (80075d0 <HAL_GPIO_Init+0x350>)
80074e0: 681b ldr r3, [r3, #0]
80074e2: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80074e4: 693b ldr r3, [r7, #16]
80074e6: 43db mvns r3, r3
80074e8: 69ba ldr r2, [r7, #24]
80074ea: 4013 ands r3, r2
80074ec: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80074ee: 683b ldr r3, [r7, #0]
80074f0: 685b ldr r3, [r3, #4]
80074f2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80074f6: 2b00 cmp r3, #0
80074f8: d003 beq.n 8007502 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
80074fa: 69ba ldr r2, [r7, #24]
80074fc: 693b ldr r3, [r7, #16]
80074fe: 4313 orrs r3, r2
8007500: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8007502: 4a33 ldr r2, [pc, #204] ; (80075d0 <HAL_GPIO_Init+0x350>)
8007504: 69bb ldr r3, [r7, #24]
8007506: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8007508: 4b31 ldr r3, [pc, #196] ; (80075d0 <HAL_GPIO_Init+0x350>)
800750a: 685b ldr r3, [r3, #4]
800750c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800750e: 693b ldr r3, [r7, #16]
8007510: 43db mvns r3, r3
8007512: 69ba ldr r2, [r7, #24]
8007514: 4013 ands r3, r2
8007516: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8007518: 683b ldr r3, [r7, #0]
800751a: 685b ldr r3, [r3, #4]
800751c: f403 3300 and.w r3, r3, #131072 ; 0x20000
8007520: 2b00 cmp r3, #0
8007522: d003 beq.n 800752c <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8007524: 69ba ldr r2, [r7, #24]
8007526: 693b ldr r3, [r7, #16]
8007528: 4313 orrs r3, r2
800752a: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
800752c: 4a28 ldr r2, [pc, #160] ; (80075d0 <HAL_GPIO_Init+0x350>)
800752e: 69bb ldr r3, [r7, #24]
8007530: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8007532: 4b27 ldr r3, [pc, #156] ; (80075d0 <HAL_GPIO_Init+0x350>)
8007534: 689b ldr r3, [r3, #8]
8007536: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8007538: 693b ldr r3, [r7, #16]
800753a: 43db mvns r3, r3
800753c: 69ba ldr r2, [r7, #24]
800753e: 4013 ands r3, r2
8007540: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8007542: 683b ldr r3, [r7, #0]
8007544: 685b ldr r3, [r3, #4]
8007546: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800754a: 2b00 cmp r3, #0
800754c: d003 beq.n 8007556 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
800754e: 69ba ldr r2, [r7, #24]
8007550: 693b ldr r3, [r7, #16]
8007552: 4313 orrs r3, r2
8007554: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8007556: 4a1e ldr r2, [pc, #120] ; (80075d0 <HAL_GPIO_Init+0x350>)
8007558: 69bb ldr r3, [r7, #24]
800755a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800755c: 4b1c ldr r3, [pc, #112] ; (80075d0 <HAL_GPIO_Init+0x350>)
800755e: 68db ldr r3, [r3, #12]
8007560: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8007562: 693b ldr r3, [r7, #16]
8007564: 43db mvns r3, r3
8007566: 69ba ldr r2, [r7, #24]
8007568: 4013 ands r3, r2
800756a: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
800756c: 683b ldr r3, [r7, #0]
800756e: 685b ldr r3, [r3, #4]
8007570: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8007574: 2b00 cmp r3, #0
8007576: d003 beq.n 8007580 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8007578: 69ba ldr r2, [r7, #24]
800757a: 693b ldr r3, [r7, #16]
800757c: 4313 orrs r3, r2
800757e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8007580: 4a13 ldr r2, [pc, #76] ; (80075d0 <HAL_GPIO_Init+0x350>)
8007582: 69bb ldr r3, [r7, #24]
8007584: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
8007586: 69fb ldr r3, [r7, #28]
8007588: 3301 adds r3, #1
800758a: 61fb str r3, [r7, #28]
800758c: 69fb ldr r3, [r7, #28]
800758e: 2b0f cmp r3, #15
8007590: f67f ae86 bls.w 80072a0 <HAL_GPIO_Init+0x20>
}
}
}
}
8007594: bf00 nop
8007596: 3724 adds r7, #36 ; 0x24
8007598: 46bd mov sp, r7
800759a: f85d 7b04 ldr.w r7, [sp], #4
800759e: 4770 bx lr
80075a0: 40023800 .word 0x40023800
80075a4: 40013800 .word 0x40013800
80075a8: 40020000 .word 0x40020000
80075ac: 40020400 .word 0x40020400
80075b0: 40020800 .word 0x40020800
80075b4: 40020c00 .word 0x40020c00
80075b8: 40021000 .word 0x40021000
80075bc: 40021400 .word 0x40021400
80075c0: 40021800 .word 0x40021800
80075c4: 40021c00 .word 0x40021c00
80075c8: 40022000 .word 0x40022000
80075cc: 40022400 .word 0x40022400
80075d0: 40013c00 .word 0x40013c00
080075d4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80075d4: b480 push {r7}
80075d6: b083 sub sp, #12
80075d8: af00 add r7, sp, #0
80075da: 6078 str r0, [r7, #4]
80075dc: 460b mov r3, r1
80075de: 807b strh r3, [r7, #2]
80075e0: 4613 mov r3, r2
80075e2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80075e4: 787b ldrb r3, [r7, #1]
80075e6: 2b00 cmp r3, #0
80075e8: d003 beq.n 80075f2 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80075ea: 887a ldrh r2, [r7, #2]
80075ec: 687b ldr r3, [r7, #4]
80075ee: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
80075f0: e003 b.n 80075fa <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
80075f2: 887b ldrh r3, [r7, #2]
80075f4: 041a lsls r2, r3, #16
80075f6: 687b ldr r3, [r7, #4]
80075f8: 619a str r2, [r3, #24]
}
80075fa: bf00 nop
80075fc: 370c adds r7, #12
80075fe: 46bd mov sp, r7
8007600: f85d 7b04 ldr.w r7, [sp], #4
8007604: 4770 bx lr
08007606 <HAL_GPIO_TogglePin>:
* @param GPIOx Where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8007606: b480 push {r7}
8007608: b083 sub sp, #12
800760a: af00 add r7, sp, #0
800760c: 6078 str r0, [r7, #4]
800760e: 460b mov r3, r1
8007610: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
8007612: 687b ldr r3, [r7, #4]
8007614: 695a ldr r2, [r3, #20]
8007616: 887b ldrh r3, [r7, #2]
8007618: 4013 ands r3, r2
800761a: 2b00 cmp r3, #0
800761c: d004 beq.n 8007628 <HAL_GPIO_TogglePin+0x22>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
800761e: 887b ldrh r3, [r7, #2]
8007620: 041a lsls r2, r3, #16
8007622: 687b ldr r3, [r7, #4]
8007624: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
8007626: e002 b.n 800762e <HAL_GPIO_TogglePin+0x28>
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8007628: 887a ldrh r2, [r7, #2]
800762a: 687b ldr r3, [r7, #4]
800762c: 619a str r2, [r3, #24]
}
800762e: bf00 nop
8007630: 370c adds r7, #12
8007632: 46bd mov sp, r7
8007634: f85d 7b04 ldr.w r7, [sp], #4
8007638: 4770 bx lr
...
0800763c <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
800763c: b580 push {r7, lr}
800763e: b082 sub sp, #8
8007640: af00 add r7, sp, #0
8007642: 4603 mov r3, r0
8007644: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
8007646: 4b08 ldr r3, [pc, #32] ; (8007668 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8007648: 695a ldr r2, [r3, #20]
800764a: 88fb ldrh r3, [r7, #6]
800764c: 4013 ands r3, r2
800764e: 2b00 cmp r3, #0
8007650: d006 beq.n 8007660 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8007652: 4a05 ldr r2, [pc, #20] ; (8007668 <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8007654: 88fb ldrh r3, [r7, #6]
8007656: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8007658: 88fb ldrh r3, [r7, #6]
800765a: 4618 mov r0, r3
800765c: f7fa fb50 bl 8001d00 <HAL_GPIO_EXTI_Callback>
}
}
8007660: bf00 nop
8007662: 3708 adds r7, #8
8007664: 46bd mov sp, r7
8007666: bd80 pop {r7, pc}
8007668: 40013c00 .word 0x40013c00
0800766c <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
800766c: b580 push {r7, lr}
800766e: b082 sub sp, #8
8007670: af00 add r7, sp, #0
8007672: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8007674: 687b ldr r3, [r7, #4]
8007676: 2b00 cmp r3, #0
8007678: d101 bne.n 800767e <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800767a: 2301 movs r3, #1
800767c: e07f b.n 800777e <HAL_I2C_Init+0x112>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
800767e: 687b ldr r3, [r7, #4]
8007680: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007684: b2db uxtb r3, r3
8007686: 2b00 cmp r3, #0
8007688: d106 bne.n 8007698 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
800768a: 687b ldr r3, [r7, #4]
800768c: 2200 movs r2, #0
800768e: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8007692: 6878 ldr r0, [r7, #4]
8007694: f000 f8a9 bl 80077ea <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8007698: 687b ldr r3, [r7, #4]
800769a: 2224 movs r2, #36 ; 0x24
800769c: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80076a0: 687b ldr r3, [r7, #4]
80076a2: 681b ldr r3, [r3, #0]
80076a4: 681a ldr r2, [r3, #0]
80076a6: 687b ldr r3, [r7, #4]
80076a8: 681b ldr r3, [r3, #0]
80076aa: f022 0201 bic.w r2, r2, #1
80076ae: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
80076b0: 687b ldr r3, [r7, #4]
80076b2: 685a ldr r2, [r3, #4]
80076b4: 687b ldr r3, [r7, #4]
80076b6: 681b ldr r3, [r3, #0]
80076b8: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80076bc: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
80076be: 687b ldr r3, [r7, #4]
80076c0: 681b ldr r3, [r3, #0]
80076c2: 689a ldr r2, [r3, #8]
80076c4: 687b ldr r3, [r7, #4]
80076c6: 681b ldr r3, [r3, #0]
80076c8: f422 4200 bic.w r2, r2, #32768 ; 0x8000
80076cc: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80076ce: 687b ldr r3, [r7, #4]
80076d0: 68db ldr r3, [r3, #12]
80076d2: 2b01 cmp r3, #1
80076d4: d107 bne.n 80076e6 <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80076d6: 687b ldr r3, [r7, #4]
80076d8: 689a ldr r2, [r3, #8]
80076da: 687b ldr r3, [r7, #4]
80076dc: 681b ldr r3, [r3, #0]
80076de: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80076e2: 609a str r2, [r3, #8]
80076e4: e006 b.n 80076f4 <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
80076e6: 687b ldr r3, [r7, #4]
80076e8: 689a ldr r2, [r3, #8]
80076ea: 687b ldr r3, [r7, #4]
80076ec: 681b ldr r3, [r3, #0]
80076ee: f442 4204 orr.w r2, r2, #33792 ; 0x8400
80076f2: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
80076f4: 687b ldr r3, [r7, #4]
80076f6: 68db ldr r3, [r3, #12]
80076f8: 2b02 cmp r3, #2
80076fa: d104 bne.n 8007706 <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
80076fc: 687b ldr r3, [r7, #4]
80076fe: 681b ldr r3, [r3, #0]
8007700: f44f 6200 mov.w r2, #2048 ; 0x800
8007704: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8007706: 687b ldr r3, [r7, #4]
8007708: 681b ldr r3, [r3, #0]
800770a: 6859 ldr r1, [r3, #4]
800770c: 687b ldr r3, [r7, #4]
800770e: 681a ldr r2, [r3, #0]
8007710: 4b1d ldr r3, [pc, #116] ; (8007788 <HAL_I2C_Init+0x11c>)
8007712: 430b orrs r3, r1
8007714: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8007716: 687b ldr r3, [r7, #4]
8007718: 681b ldr r3, [r3, #0]
800771a: 68da ldr r2, [r3, #12]
800771c: 687b ldr r3, [r7, #4]
800771e: 681b ldr r3, [r3, #0]
8007720: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8007724: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
8007726: 687b ldr r3, [r7, #4]
8007728: 691a ldr r2, [r3, #16]
800772a: 687b ldr r3, [r7, #4]
800772c: 695b ldr r3, [r3, #20]
800772e: ea42 0103 orr.w r1, r2, r3
8007732: 687b ldr r3, [r7, #4]
8007734: 699b ldr r3, [r3, #24]
8007736: 021a lsls r2, r3, #8
8007738: 687b ldr r3, [r7, #4]
800773a: 681b ldr r3, [r3, #0]
800773c: 430a orrs r2, r1
800773e: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8007740: 687b ldr r3, [r7, #4]
8007742: 69d9 ldr r1, [r3, #28]
8007744: 687b ldr r3, [r7, #4]
8007746: 6a1a ldr r2, [r3, #32]
8007748: 687b ldr r3, [r7, #4]
800774a: 681b ldr r3, [r3, #0]
800774c: 430a orrs r2, r1
800774e: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8007750: 687b ldr r3, [r7, #4]
8007752: 681b ldr r3, [r3, #0]
8007754: 681a ldr r2, [r3, #0]
8007756: 687b ldr r3, [r7, #4]
8007758: 681b ldr r3, [r3, #0]
800775a: f042 0201 orr.w r2, r2, #1
800775e: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007760: 687b ldr r3, [r7, #4]
8007762: 2200 movs r2, #0
8007764: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007766: 687b ldr r3, [r7, #4]
8007768: 2220 movs r2, #32
800776a: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800776e: 687b ldr r3, [r7, #4]
8007770: 2200 movs r2, #0
8007772: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8007774: 687b ldr r3, [r7, #4]
8007776: 2200 movs r2, #0
8007778: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
800777c: 2300 movs r3, #0
}
800777e: 4618 mov r0, r3
8007780: 3708 adds r7, #8
8007782: 46bd mov sp, r7
8007784: bd80 pop {r7, pc}
8007786: bf00 nop
8007788: 02008000 .word 0x02008000
0800778c <HAL_I2C_DeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
800778c: b580 push {r7, lr}
800778e: b082 sub sp, #8
8007790: af00 add r7, sp, #0
8007792: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8007794: 687b ldr r3, [r7, #4]
8007796: 2b00 cmp r3, #0
8007798: d101 bne.n 800779e <HAL_I2C_DeInit+0x12>
{
return HAL_ERROR;
800779a: 2301 movs r3, #1
800779c: e021 b.n 80077e2 <HAL_I2C_DeInit+0x56>
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
hi2c->State = HAL_I2C_STATE_BUSY;
800779e: 687b ldr r3, [r7, #4]
80077a0: 2224 movs r2, #36 ; 0x24
80077a2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
80077a6: 687b ldr r3, [r7, #4]
80077a8: 681b ldr r3, [r3, #0]
80077aa: 681a ldr r2, [r3, #0]
80077ac: 687b ldr r3, [r7, #4]
80077ae: 681b ldr r3, [r3, #0]
80077b0: f022 0201 bic.w r2, r2, #1
80077b4: 601a str r2, [r3, #0]
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hi2c->MspDeInitCallback(hi2c);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
80077b6: 6878 ldr r0, [r7, #4]
80077b8: f000 f821 bl 80077fe <HAL_I2C_MspDeInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80077bc: 687b ldr r3, [r7, #4]
80077be: 2200 movs r2, #0
80077c0: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_RESET;
80077c2: 687b ldr r3, [r7, #4]
80077c4: 2200 movs r2, #0
80077c6: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
80077ca: 687b ldr r3, [r7, #4]
80077cc: 2200 movs r2, #0
80077ce: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80077d0: 687b ldr r3, [r7, #4]
80077d2: 2200 movs r2, #0
80077d4: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Release Lock */
__HAL_UNLOCK(hi2c);
80077d8: 687b ldr r3, [r7, #4]
80077da: 2200 movs r2, #0
80077dc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
80077e0: 2300 movs r3, #0
}
80077e2: 4618 mov r0, r3
80077e4: 3708 adds r7, #8
80077e6: 46bd mov sp, r7
80077e8: bd80 pop {r7, pc}
080077ea <HAL_I2C_MspInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
80077ea: b480 push {r7}
80077ec: b083 sub sp, #12
80077ee: af00 add r7, sp, #0
80077f0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
80077f2: bf00 nop
80077f4: 370c adds r7, #12
80077f6: 46bd mov sp, r7
80077f8: f85d 7b04 ldr.w r7, [sp], #4
80077fc: 4770 bx lr
080077fe <HAL_I2C_MspDeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
80077fe: b480 push {r7}
8007800: b083 sub sp, #12
8007802: af00 add r7, sp, #0
8007804: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
8007806: bf00 nop
8007808: 370c adds r7, #12
800780a: 46bd mov sp, r7
800780c: f85d 7b04 ldr.w r7, [sp], #4
8007810: 4770 bx lr
...
08007814 <HAL_I2C_Mem_Write>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8007814: b580 push {r7, lr}
8007816: b088 sub sp, #32
8007818: af02 add r7, sp, #8
800781a: 60f8 str r0, [r7, #12]
800781c: 4608 mov r0, r1
800781e: 4611 mov r1, r2
8007820: 461a mov r2, r3
8007822: 4603 mov r3, r0
8007824: 817b strh r3, [r7, #10]
8007826: 460b mov r3, r1
8007828: 813b strh r3, [r7, #8]
800782a: 4613 mov r3, r2
800782c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
800782e: 68fb ldr r3, [r7, #12]
8007830: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007834: b2db uxtb r3, r3
8007836: 2b20 cmp r3, #32
8007838: f040 80f9 bne.w 8007a2e <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
800783c: 6a3b ldr r3, [r7, #32]
800783e: 2b00 cmp r3, #0
8007840: d002 beq.n 8007848 <HAL_I2C_Mem_Write+0x34>
8007842: 8cbb ldrh r3, [r7, #36] ; 0x24
8007844: 2b00 cmp r3, #0
8007846: d105 bne.n 8007854 <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007848: 68fb ldr r3, [r7, #12]
800784a: f44f 7200 mov.w r2, #512 ; 0x200
800784e: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007850: 2301 movs r3, #1
8007852: e0ed b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8007854: 68fb ldr r3, [r7, #12]
8007856: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800785a: 2b01 cmp r3, #1
800785c: d101 bne.n 8007862 <HAL_I2C_Mem_Write+0x4e>
800785e: 2302 movs r3, #2
8007860: e0e6 b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
8007862: 68fb ldr r3, [r7, #12]
8007864: 2201 movs r2, #1
8007866: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
800786a: f7fd f899 bl 80049a0 <HAL_GetTick>
800786e: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8007870: 697b ldr r3, [r7, #20]
8007872: 9300 str r3, [sp, #0]
8007874: 2319 movs r3, #25
8007876: 2201 movs r2, #1
8007878: f44f 4100 mov.w r1, #32768 ; 0x8000
800787c: 68f8 ldr r0, [r7, #12]
800787e: f000 fad1 bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007882: 4603 mov r3, r0
8007884: 2b00 cmp r3, #0
8007886: d001 beq.n 800788c <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
8007888: 2301 movs r3, #1
800788a: e0d1 b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
800788c: 68fb ldr r3, [r7, #12]
800788e: 2221 movs r2, #33 ; 0x21
8007890: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
8007894: 68fb ldr r3, [r7, #12]
8007896: 2240 movs r2, #64 ; 0x40
8007898: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800789c: 68fb ldr r3, [r7, #12]
800789e: 2200 movs r2, #0
80078a0: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80078a2: 68fb ldr r3, [r7, #12]
80078a4: 6a3a ldr r2, [r7, #32]
80078a6: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80078a8: 68fb ldr r3, [r7, #12]
80078aa: 8cba ldrh r2, [r7, #36] ; 0x24
80078ac: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80078ae: 68fb ldr r3, [r7, #12]
80078b0: 2200 movs r2, #0
80078b2: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80078b4: 88f8 ldrh r0, [r7, #6]
80078b6: 893a ldrh r2, [r7, #8]
80078b8: 8979 ldrh r1, [r7, #10]
80078ba: 697b ldr r3, [r7, #20]
80078bc: 9301 str r3, [sp, #4]
80078be: 6abb ldr r3, [r7, #40] ; 0x28
80078c0: 9300 str r3, [sp, #0]
80078c2: 4603 mov r3, r0
80078c4: 68f8 ldr r0, [r7, #12]
80078c6: f000 f9e1 bl 8007c8c <I2C_RequestMemoryWrite>
80078ca: 4603 mov r3, r0
80078cc: 2b00 cmp r3, #0
80078ce: d005 beq.n 80078dc <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80078d0: 68fb ldr r3, [r7, #12]
80078d2: 2200 movs r2, #0
80078d4: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
80078d8: 2301 movs r3, #1
80078da: e0a9 b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80078dc: 68fb ldr r3, [r7, #12]
80078de: 8d5b ldrh r3, [r3, #42] ; 0x2a
80078e0: b29b uxth r3, r3
80078e2: 2bff cmp r3, #255 ; 0xff
80078e4: d90e bls.n 8007904 <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80078e6: 68fb ldr r3, [r7, #12]
80078e8: 22ff movs r2, #255 ; 0xff
80078ea: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80078ec: 68fb ldr r3, [r7, #12]
80078ee: 8d1b ldrh r3, [r3, #40] ; 0x28
80078f0: b2da uxtb r2, r3
80078f2: 8979 ldrh r1, [r7, #10]
80078f4: 2300 movs r3, #0
80078f6: 9300 str r3, [sp, #0]
80078f8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80078fc: 68f8 ldr r0, [r7, #12]
80078fe: f000 fbb3 bl 8008068 <I2C_TransferConfig>
8007902: e00f b.n 8007924 <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007904: 68fb ldr r3, [r7, #12]
8007906: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007908: b29a uxth r2, r3
800790a: 68fb ldr r3, [r7, #12]
800790c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
800790e: 68fb ldr r3, [r7, #12]
8007910: 8d1b ldrh r3, [r3, #40] ; 0x28
8007912: b2da uxtb r2, r3
8007914: 8979 ldrh r1, [r7, #10]
8007916: 2300 movs r3, #0
8007918: 9300 str r3, [sp, #0]
800791a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800791e: 68f8 ldr r0, [r7, #12]
8007920: f000 fba2 bl 8008068 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007924: 697a ldr r2, [r7, #20]
8007926: 6ab9 ldr r1, [r7, #40] ; 0x28
8007928: 68f8 ldr r0, [r7, #12]
800792a: f000 fabb bl 8007ea4 <I2C_WaitOnTXISFlagUntilTimeout>
800792e: 4603 mov r3, r0
8007930: 2b00 cmp r3, #0
8007932: d001 beq.n 8007938 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
8007934: 2301 movs r3, #1
8007936: e07b b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8007938: 68fb ldr r3, [r7, #12]
800793a: 6a5b ldr r3, [r3, #36] ; 0x24
800793c: 781a ldrb r2, [r3, #0]
800793e: 68fb ldr r3, [r7, #12]
8007940: 681b ldr r3, [r3, #0]
8007942: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007944: 68fb ldr r3, [r7, #12]
8007946: 6a5b ldr r3, [r3, #36] ; 0x24
8007948: 1c5a adds r2, r3, #1
800794a: 68fb ldr r3, [r7, #12]
800794c: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
800794e: 68fb ldr r3, [r7, #12]
8007950: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007952: b29b uxth r3, r3
8007954: 3b01 subs r3, #1
8007956: b29a uxth r2, r3
8007958: 68fb ldr r3, [r7, #12]
800795a: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
800795c: 68fb ldr r3, [r7, #12]
800795e: 8d1b ldrh r3, [r3, #40] ; 0x28
8007960: 3b01 subs r3, #1
8007962: b29a uxth r2, r3
8007964: 68fb ldr r3, [r7, #12]
8007966: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8007968: 68fb ldr r3, [r7, #12]
800796a: 8d5b ldrh r3, [r3, #42] ; 0x2a
800796c: b29b uxth r3, r3
800796e: 2b00 cmp r3, #0
8007970: d034 beq.n 80079dc <HAL_I2C_Mem_Write+0x1c8>
8007972: 68fb ldr r3, [r7, #12]
8007974: 8d1b ldrh r3, [r3, #40] ; 0x28
8007976: 2b00 cmp r3, #0
8007978: d130 bne.n 80079dc <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
800797a: 697b ldr r3, [r7, #20]
800797c: 9300 str r3, [sp, #0]
800797e: 6abb ldr r3, [r7, #40] ; 0x28
8007980: 2200 movs r2, #0
8007982: 2180 movs r1, #128 ; 0x80
8007984: 68f8 ldr r0, [r7, #12]
8007986: f000 fa4d bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
800798a: 4603 mov r3, r0
800798c: 2b00 cmp r3, #0
800798e: d001 beq.n 8007994 <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
8007990: 2301 movs r3, #1
8007992: e04d b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007994: 68fb ldr r3, [r7, #12]
8007996: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007998: b29b uxth r3, r3
800799a: 2bff cmp r3, #255 ; 0xff
800799c: d90e bls.n 80079bc <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800799e: 68fb ldr r3, [r7, #12]
80079a0: 22ff movs r2, #255 ; 0xff
80079a2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80079a4: 68fb ldr r3, [r7, #12]
80079a6: 8d1b ldrh r3, [r3, #40] ; 0x28
80079a8: b2da uxtb r2, r3
80079aa: 8979 ldrh r1, [r7, #10]
80079ac: 2300 movs r3, #0
80079ae: 9300 str r3, [sp, #0]
80079b0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80079b4: 68f8 ldr r0, [r7, #12]
80079b6: f000 fb57 bl 8008068 <I2C_TransferConfig>
80079ba: e00f b.n 80079dc <HAL_I2C_Mem_Write+0x1c8>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80079bc: 68fb ldr r3, [r7, #12]
80079be: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079c0: b29a uxth r2, r3
80079c2: 68fb ldr r3, [r7, #12]
80079c4: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
80079c6: 68fb ldr r3, [r7, #12]
80079c8: 8d1b ldrh r3, [r3, #40] ; 0x28
80079ca: b2da uxtb r2, r3
80079cc: 8979 ldrh r1, [r7, #10]
80079ce: 2300 movs r3, #0
80079d0: 9300 str r3, [sp, #0]
80079d2: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80079d6: 68f8 ldr r0, [r7, #12]
80079d8: f000 fb46 bl 8008068 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
80079dc: 68fb ldr r3, [r7, #12]
80079de: 8d5b ldrh r3, [r3, #42] ; 0x2a
80079e0: b29b uxth r3, r3
80079e2: 2b00 cmp r3, #0
80079e4: d19e bne.n 8007924 <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
80079e6: 697a ldr r2, [r7, #20]
80079e8: 6ab9 ldr r1, [r7, #40] ; 0x28
80079ea: 68f8 ldr r0, [r7, #12]
80079ec: f000 fa9a bl 8007f24 <I2C_WaitOnSTOPFlagUntilTimeout>
80079f0: 4603 mov r3, r0
80079f2: 2b00 cmp r3, #0
80079f4: d001 beq.n 80079fa <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
80079f6: 2301 movs r3, #1
80079f8: e01a b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80079fa: 68fb ldr r3, [r7, #12]
80079fc: 681b ldr r3, [r3, #0]
80079fe: 2220 movs r2, #32
8007a00: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007a02: 68fb ldr r3, [r7, #12]
8007a04: 681b ldr r3, [r3, #0]
8007a06: 6859 ldr r1, [r3, #4]
8007a08: 68fb ldr r3, [r7, #12]
8007a0a: 681a ldr r2, [r3, #0]
8007a0c: 4b0a ldr r3, [pc, #40] ; (8007a38 <HAL_I2C_Mem_Write+0x224>)
8007a0e: 400b ands r3, r1
8007a10: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007a12: 68fb ldr r3, [r7, #12]
8007a14: 2220 movs r2, #32
8007a16: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007a1a: 68fb ldr r3, [r7, #12]
8007a1c: 2200 movs r2, #0
8007a1e: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007a22: 68fb ldr r3, [r7, #12]
8007a24: 2200 movs r2, #0
8007a26: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007a2a: 2300 movs r3, #0
8007a2c: e000 b.n 8007a30 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
8007a2e: 2302 movs r3, #2
}
}
8007a30: 4618 mov r0, r3
8007a32: 3718 adds r7, #24
8007a34: 46bd mov sp, r7
8007a36: bd80 pop {r7, pc}
8007a38: fe00e800 .word 0xfe00e800
08007a3c <HAL_I2C_Mem_Read>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8007a3c: b580 push {r7, lr}
8007a3e: b088 sub sp, #32
8007a40: af02 add r7, sp, #8
8007a42: 60f8 str r0, [r7, #12]
8007a44: 4608 mov r0, r1
8007a46: 4611 mov r1, r2
8007a48: 461a mov r2, r3
8007a4a: 4603 mov r3, r0
8007a4c: 817b strh r3, [r7, #10]
8007a4e: 460b mov r3, r1
8007a50: 813b strh r3, [r7, #8]
8007a52: 4613 mov r3, r2
8007a54: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8007a56: 68fb ldr r3, [r7, #12]
8007a58: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007a5c: b2db uxtb r3, r3
8007a5e: 2b20 cmp r3, #32
8007a60: f040 80fd bne.w 8007c5e <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
8007a64: 6a3b ldr r3, [r7, #32]
8007a66: 2b00 cmp r3, #0
8007a68: d002 beq.n 8007a70 <HAL_I2C_Mem_Read+0x34>
8007a6a: 8cbb ldrh r3, [r7, #36] ; 0x24
8007a6c: 2b00 cmp r3, #0
8007a6e: d105 bne.n 8007a7c <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8007a70: 68fb ldr r3, [r7, #12]
8007a72: f44f 7200 mov.w r2, #512 ; 0x200
8007a76: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8007a78: 2301 movs r3, #1
8007a7a: e0f1 b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
8007a7c: 68fb ldr r3, [r7, #12]
8007a7e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8007a82: 2b01 cmp r3, #1
8007a84: d101 bne.n 8007a8a <HAL_I2C_Mem_Read+0x4e>
8007a86: 2302 movs r3, #2
8007a88: e0ea b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
8007a8a: 68fb ldr r3, [r7, #12]
8007a8c: 2201 movs r2, #1
8007a8e: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8007a92: f7fc ff85 bl 80049a0 <HAL_GetTick>
8007a96: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8007a98: 697b ldr r3, [r7, #20]
8007a9a: 9300 str r3, [sp, #0]
8007a9c: 2319 movs r3, #25
8007a9e: 2201 movs r2, #1
8007aa0: f44f 4100 mov.w r1, #32768 ; 0x8000
8007aa4: 68f8 ldr r0, [r7, #12]
8007aa6: f000 f9bd bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007aaa: 4603 mov r3, r0
8007aac: 2b00 cmp r3, #0
8007aae: d001 beq.n 8007ab4 <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
8007ab0: 2301 movs r3, #1
8007ab2: e0d5 b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
8007ab4: 68fb ldr r3, [r7, #12]
8007ab6: 2222 movs r2, #34 ; 0x22
8007ab8: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
8007abc: 68fb ldr r3, [r7, #12]
8007abe: 2240 movs r2, #64 ; 0x40
8007ac0: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8007ac4: 68fb ldr r3, [r7, #12]
8007ac6: 2200 movs r2, #0
8007ac8: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8007aca: 68fb ldr r3, [r7, #12]
8007acc: 6a3a ldr r2, [r7, #32]
8007ace: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
8007ad0: 68fb ldr r3, [r7, #12]
8007ad2: 8cba ldrh r2, [r7, #36] ; 0x24
8007ad4: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
8007ad6: 68fb ldr r3, [r7, #12]
8007ad8: 2200 movs r2, #0
8007ada: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
8007adc: 88f8 ldrh r0, [r7, #6]
8007ade: 893a ldrh r2, [r7, #8]
8007ae0: 8979 ldrh r1, [r7, #10]
8007ae2: 697b ldr r3, [r7, #20]
8007ae4: 9301 str r3, [sp, #4]
8007ae6: 6abb ldr r3, [r7, #40] ; 0x28
8007ae8: 9300 str r3, [sp, #0]
8007aea: 4603 mov r3, r0
8007aec: 68f8 ldr r0, [r7, #12]
8007aee: f000 f921 bl 8007d34 <I2C_RequestMemoryRead>
8007af2: 4603 mov r3, r0
8007af4: 2b00 cmp r3, #0
8007af6: d005 beq.n 8007b04 <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007af8: 68fb ldr r3, [r7, #12]
8007afa: 2200 movs r2, #0
8007afc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007b00: 2301 movs r3, #1
8007b02: e0ad b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007b04: 68fb ldr r3, [r7, #12]
8007b06: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b08: b29b uxth r3, r3
8007b0a: 2bff cmp r3, #255 ; 0xff
8007b0c: d90e bls.n 8007b2c <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007b0e: 68fb ldr r3, [r7, #12]
8007b10: 22ff movs r2, #255 ; 0xff
8007b12: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
8007b14: 68fb ldr r3, [r7, #12]
8007b16: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b18: b2da uxtb r2, r3
8007b1a: 8979 ldrh r1, [r7, #10]
8007b1c: 4b52 ldr r3, [pc, #328] ; (8007c68 <HAL_I2C_Mem_Read+0x22c>)
8007b1e: 9300 str r3, [sp, #0]
8007b20: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007b24: 68f8 ldr r0, [r7, #12]
8007b26: f000 fa9f bl 8008068 <I2C_TransferConfig>
8007b2a: e00f b.n 8007b4c <HAL_I2C_Mem_Read+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007b2c: 68fb ldr r3, [r7, #12]
8007b2e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b30: b29a uxth r2, r3
8007b32: 68fb ldr r3, [r7, #12]
8007b34: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
8007b36: 68fb ldr r3, [r7, #12]
8007b38: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b3a: b2da uxtb r2, r3
8007b3c: 8979 ldrh r1, [r7, #10]
8007b3e: 4b4a ldr r3, [pc, #296] ; (8007c68 <HAL_I2C_Mem_Read+0x22c>)
8007b40: 9300 str r3, [sp, #0]
8007b42: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007b46: 68f8 ldr r0, [r7, #12]
8007b48: f000 fa8e bl 8008068 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
8007b4c: 697b ldr r3, [r7, #20]
8007b4e: 9300 str r3, [sp, #0]
8007b50: 6abb ldr r3, [r7, #40] ; 0x28
8007b52: 2200 movs r2, #0
8007b54: 2104 movs r1, #4
8007b56: 68f8 ldr r0, [r7, #12]
8007b58: f000 f964 bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007b5c: 4603 mov r3, r0
8007b5e: 2b00 cmp r3, #0
8007b60: d001 beq.n 8007b66 <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
8007b62: 2301 movs r3, #1
8007b64: e07c b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8007b66: 68fb ldr r3, [r7, #12]
8007b68: 681b ldr r3, [r3, #0]
8007b6a: 6a5a ldr r2, [r3, #36] ; 0x24
8007b6c: 68fb ldr r3, [r7, #12]
8007b6e: 6a5b ldr r3, [r3, #36] ; 0x24
8007b70: b2d2 uxtb r2, r2
8007b72: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8007b74: 68fb ldr r3, [r7, #12]
8007b76: 6a5b ldr r3, [r3, #36] ; 0x24
8007b78: 1c5a adds r2, r3, #1
8007b7a: 68fb ldr r3, [r7, #12]
8007b7c: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
8007b7e: 68fb ldr r3, [r7, #12]
8007b80: 8d1b ldrh r3, [r3, #40] ; 0x28
8007b82: 3b01 subs r3, #1
8007b84: b29a uxth r2, r3
8007b86: 68fb ldr r3, [r7, #12]
8007b88: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
8007b8a: 68fb ldr r3, [r7, #12]
8007b8c: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b8e: b29b uxth r3, r3
8007b90: 3b01 subs r3, #1
8007b92: b29a uxth r2, r3
8007b94: 68fb ldr r3, [r7, #12]
8007b96: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8007b98: 68fb ldr r3, [r7, #12]
8007b9a: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007b9c: b29b uxth r3, r3
8007b9e: 2b00 cmp r3, #0
8007ba0: d034 beq.n 8007c0c <HAL_I2C_Mem_Read+0x1d0>
8007ba2: 68fb ldr r3, [r7, #12]
8007ba4: 8d1b ldrh r3, [r3, #40] ; 0x28
8007ba6: 2b00 cmp r3, #0
8007ba8: d130 bne.n 8007c0c <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
8007baa: 697b ldr r3, [r7, #20]
8007bac: 9300 str r3, [sp, #0]
8007bae: 6abb ldr r3, [r7, #40] ; 0x28
8007bb0: 2200 movs r2, #0
8007bb2: 2180 movs r1, #128 ; 0x80
8007bb4: 68f8 ldr r0, [r7, #12]
8007bb6: f000 f935 bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007bba: 4603 mov r3, r0
8007bbc: 2b00 cmp r3, #0
8007bbe: d001 beq.n 8007bc4 <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
8007bc0: 2301 movs r3, #1
8007bc2: e04d b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8007bc4: 68fb ldr r3, [r7, #12]
8007bc6: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007bc8: b29b uxth r3, r3
8007bca: 2bff cmp r3, #255 ; 0xff
8007bcc: d90e bls.n 8007bec <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8007bce: 68fb ldr r3, [r7, #12]
8007bd0: 22ff movs r2, #255 ; 0xff
8007bd2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
8007bd4: 68fb ldr r3, [r7, #12]
8007bd6: 8d1b ldrh r3, [r3, #40] ; 0x28
8007bd8: b2da uxtb r2, r3
8007bda: 8979 ldrh r1, [r7, #10]
8007bdc: 2300 movs r3, #0
8007bde: 9300 str r3, [sp, #0]
8007be0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007be4: 68f8 ldr r0, [r7, #12]
8007be6: f000 fa3f bl 8008068 <I2C_TransferConfig>
8007bea: e00f b.n 8007c0c <HAL_I2C_Mem_Read+0x1d0>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8007bec: 68fb ldr r3, [r7, #12]
8007bee: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007bf0: b29a uxth r2, r3
8007bf2: 68fb ldr r3, [r7, #12]
8007bf4: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8007bf6: 68fb ldr r3, [r7, #12]
8007bf8: 8d1b ldrh r3, [r3, #40] ; 0x28
8007bfa: b2da uxtb r2, r3
8007bfc: 8979 ldrh r1, [r7, #10]
8007bfe: 2300 movs r3, #0
8007c00: 9300 str r3, [sp, #0]
8007c02: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8007c06: 68f8 ldr r0, [r7, #12]
8007c08: f000 fa2e bl 8008068 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
8007c0c: 68fb ldr r3, [r7, #12]
8007c0e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8007c10: b29b uxth r3, r3
8007c12: 2b00 cmp r3, #0
8007c14: d19a bne.n 8007b4c <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
8007c16: 697a ldr r2, [r7, #20]
8007c18: 6ab9 ldr r1, [r7, #40] ; 0x28
8007c1a: 68f8 ldr r0, [r7, #12]
8007c1c: f000 f982 bl 8007f24 <I2C_WaitOnSTOPFlagUntilTimeout>
8007c20: 4603 mov r3, r0
8007c22: 2b00 cmp r3, #0
8007c24: d001 beq.n 8007c2a <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
8007c26: 2301 movs r3, #1
8007c28: e01a b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8007c2a: 68fb ldr r3, [r7, #12]
8007c2c: 681b ldr r3, [r3, #0]
8007c2e: 2220 movs r2, #32
8007c30: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8007c32: 68fb ldr r3, [r7, #12]
8007c34: 681b ldr r3, [r3, #0]
8007c36: 6859 ldr r1, [r3, #4]
8007c38: 68fb ldr r3, [r7, #12]
8007c3a: 681a ldr r2, [r3, #0]
8007c3c: 4b0b ldr r3, [pc, #44] ; (8007c6c <HAL_I2C_Mem_Read+0x230>)
8007c3e: 400b ands r3, r1
8007c40: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
8007c42: 68fb ldr r3, [r7, #12]
8007c44: 2220 movs r2, #32
8007c46: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007c4a: 68fb ldr r3, [r7, #12]
8007c4c: 2200 movs r2, #0
8007c4e: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007c52: 68fb ldr r3, [r7, #12]
8007c54: 2200 movs r2, #0
8007c56: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8007c5a: 2300 movs r3, #0
8007c5c: e000 b.n 8007c60 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8007c5e: 2302 movs r3, #2
}
}
8007c60: 4618 mov r0, r3
8007c62: 3718 adds r7, #24
8007c64: 46bd mov sp, r7
8007c66: bd80 pop {r7, pc}
8007c68: 80002400 .word 0x80002400
8007c6c: fe00e800 .word 0xfe00e800
08007c70 <HAL_I2C_GetState>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
8007c70: b480 push {r7}
8007c72: b083 sub sp, #12
8007c74: af00 add r7, sp, #0
8007c76: 6078 str r0, [r7, #4]
/* Return I2C handle state */
return hi2c->State;
8007c78: 687b ldr r3, [r7, #4]
8007c7a: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8007c7e: b2db uxtb r3, r3
}
8007c80: 4618 mov r0, r3
8007c82: 370c adds r7, #12
8007c84: 46bd mov sp, r7
8007c86: f85d 7b04 ldr.w r7, [sp], #4
8007c8a: 4770 bx lr
08007c8c <I2C_RequestMemoryWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007c8c: b580 push {r7, lr}
8007c8e: b086 sub sp, #24
8007c90: af02 add r7, sp, #8
8007c92: 60f8 str r0, [r7, #12]
8007c94: 4608 mov r0, r1
8007c96: 4611 mov r1, r2
8007c98: 461a mov r2, r3
8007c9a: 4603 mov r3, r0
8007c9c: 817b strh r3, [r7, #10]
8007c9e: 460b mov r3, r1
8007ca0: 813b strh r3, [r7, #8]
8007ca2: 4613 mov r3, r2
8007ca4: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
8007ca6: 88fb ldrh r3, [r7, #6]
8007ca8: b2da uxtb r2, r3
8007caa: 8979 ldrh r1, [r7, #10]
8007cac: 4b20 ldr r3, [pc, #128] ; (8007d30 <I2C_RequestMemoryWrite+0xa4>)
8007cae: 9300 str r3, [sp, #0]
8007cb0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8007cb4: 68f8 ldr r0, [r7, #12]
8007cb6: f000 f9d7 bl 8008068 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007cba: 69fa ldr r2, [r7, #28]
8007cbc: 69b9 ldr r1, [r7, #24]
8007cbe: 68f8 ldr r0, [r7, #12]
8007cc0: f000 f8f0 bl 8007ea4 <I2C_WaitOnTXISFlagUntilTimeout>
8007cc4: 4603 mov r3, r0
8007cc6: 2b00 cmp r3, #0
8007cc8: d001 beq.n 8007cce <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
8007cca: 2301 movs r3, #1
8007ccc: e02c b.n 8007d28 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007cce: 88fb ldrh r3, [r7, #6]
8007cd0: 2b01 cmp r3, #1
8007cd2: d105 bne.n 8007ce0 <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007cd4: 893b ldrh r3, [r7, #8]
8007cd6: b2da uxtb r2, r3
8007cd8: 68fb ldr r3, [r7, #12]
8007cda: 681b ldr r3, [r3, #0]
8007cdc: 629a str r2, [r3, #40] ; 0x28
8007cde: e015 b.n 8007d0c <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007ce0: 893b ldrh r3, [r7, #8]
8007ce2: 0a1b lsrs r3, r3, #8
8007ce4: b29b uxth r3, r3
8007ce6: b2da uxtb r2, r3
8007ce8: 68fb ldr r3, [r7, #12]
8007cea: 681b ldr r3, [r3, #0]
8007cec: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007cee: 69fa ldr r2, [r7, #28]
8007cf0: 69b9 ldr r1, [r7, #24]
8007cf2: 68f8 ldr r0, [r7, #12]
8007cf4: f000 f8d6 bl 8007ea4 <I2C_WaitOnTXISFlagUntilTimeout>
8007cf8: 4603 mov r3, r0
8007cfa: 2b00 cmp r3, #0
8007cfc: d001 beq.n 8007d02 <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
8007cfe: 2301 movs r3, #1
8007d00: e012 b.n 8007d28 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007d02: 893b ldrh r3, [r7, #8]
8007d04: b2da uxtb r2, r3
8007d06: 68fb ldr r3, [r7, #12]
8007d08: 681b ldr r3, [r3, #0]
8007d0a: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8007d0c: 69fb ldr r3, [r7, #28]
8007d0e: 9300 str r3, [sp, #0]
8007d10: 69bb ldr r3, [r7, #24]
8007d12: 2200 movs r2, #0
8007d14: 2180 movs r1, #128 ; 0x80
8007d16: 68f8 ldr r0, [r7, #12]
8007d18: f000 f884 bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007d1c: 4603 mov r3, r0
8007d1e: 2b00 cmp r3, #0
8007d20: d001 beq.n 8007d26 <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
8007d22: 2301 movs r3, #1
8007d24: e000 b.n 8007d28 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
8007d26: 2300 movs r3, #0
}
8007d28: 4618 mov r0, r3
8007d2a: 3710 adds r7, #16
8007d2c: 46bd mov sp, r7
8007d2e: bd80 pop {r7, pc}
8007d30: 80002000 .word 0x80002000
08007d34 <I2C_RequestMemoryRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
8007d34: b580 push {r7, lr}
8007d36: b086 sub sp, #24
8007d38: af02 add r7, sp, #8
8007d3a: 60f8 str r0, [r7, #12]
8007d3c: 4608 mov r0, r1
8007d3e: 4611 mov r1, r2
8007d40: 461a mov r2, r3
8007d42: 4603 mov r3, r0
8007d44: 817b strh r3, [r7, #10]
8007d46: 460b mov r3, r1
8007d48: 813b strh r3, [r7, #8]
8007d4a: 4613 mov r3, r2
8007d4c: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
8007d4e: 88fb ldrh r3, [r7, #6]
8007d50: b2da uxtb r2, r3
8007d52: 8979 ldrh r1, [r7, #10]
8007d54: 4b20 ldr r3, [pc, #128] ; (8007dd8 <I2C_RequestMemoryRead+0xa4>)
8007d56: 9300 str r3, [sp, #0]
8007d58: 2300 movs r3, #0
8007d5a: 68f8 ldr r0, [r7, #12]
8007d5c: f000 f984 bl 8008068 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007d60: 69fa ldr r2, [r7, #28]
8007d62: 69b9 ldr r1, [r7, #24]
8007d64: 68f8 ldr r0, [r7, #12]
8007d66: f000 f89d bl 8007ea4 <I2C_WaitOnTXISFlagUntilTimeout>
8007d6a: 4603 mov r3, r0
8007d6c: 2b00 cmp r3, #0
8007d6e: d001 beq.n 8007d74 <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
8007d70: 2301 movs r3, #1
8007d72: e02c b.n 8007dce <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
8007d74: 88fb ldrh r3, [r7, #6]
8007d76: 2b01 cmp r3, #1
8007d78: d105 bne.n 8007d86 <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007d7a: 893b ldrh r3, [r7, #8]
8007d7c: b2da uxtb r2, r3
8007d7e: 68fb ldr r3, [r7, #12]
8007d80: 681b ldr r3, [r3, #0]
8007d82: 629a str r2, [r3, #40] ; 0x28
8007d84: e015 b.n 8007db2 <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8007d86: 893b ldrh r3, [r7, #8]
8007d88: 0a1b lsrs r3, r3, #8
8007d8a: b29b uxth r3, r3
8007d8c: b2da uxtb r2, r3
8007d8e: 68fb ldr r3, [r7, #12]
8007d90: 681b ldr r3, [r3, #0]
8007d92: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8007d94: 69fa ldr r2, [r7, #28]
8007d96: 69b9 ldr r1, [r7, #24]
8007d98: 68f8 ldr r0, [r7, #12]
8007d9a: f000 f883 bl 8007ea4 <I2C_WaitOnTXISFlagUntilTimeout>
8007d9e: 4603 mov r3, r0
8007da0: 2b00 cmp r3, #0
8007da2: d001 beq.n 8007da8 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
8007da4: 2301 movs r3, #1
8007da6: e012 b.n 8007dce <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
8007da8: 893b ldrh r3, [r7, #8]
8007daa: b2da uxtb r2, r3
8007dac: 68fb ldr r3, [r7, #12]
8007dae: 681b ldr r3, [r3, #0]
8007db0: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
8007db2: 69fb ldr r3, [r7, #28]
8007db4: 9300 str r3, [sp, #0]
8007db6: 69bb ldr r3, [r7, #24]
8007db8: 2200 movs r2, #0
8007dba: 2140 movs r1, #64 ; 0x40
8007dbc: 68f8 ldr r0, [r7, #12]
8007dbe: f000 f831 bl 8007e24 <I2C_WaitOnFlagUntilTimeout>
8007dc2: 4603 mov r3, r0
8007dc4: 2b00 cmp r3, #0
8007dc6: d001 beq.n 8007dcc <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
8007dc8: 2301 movs r3, #1
8007dca: e000 b.n 8007dce <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
8007dcc: 2300 movs r3, #0
}
8007dce: 4618 mov r0, r3
8007dd0: 3710 adds r7, #16
8007dd2: 46bd mov sp, r7
8007dd4: bd80 pop {r7, pc}
8007dd6: bf00 nop
8007dd8: 80002000 .word 0x80002000
08007ddc <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8007ddc: b480 push {r7}
8007dde: b083 sub sp, #12
8007de0: af00 add r7, sp, #0
8007de2: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8007de4: 687b ldr r3, [r7, #4]
8007de6: 681b ldr r3, [r3, #0]
8007de8: 699b ldr r3, [r3, #24]
8007dea: f003 0302 and.w r3, r3, #2
8007dee: 2b02 cmp r3, #2
8007df0: d103 bne.n 8007dfa <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8007df2: 687b ldr r3, [r7, #4]
8007df4: 681b ldr r3, [r3, #0]
8007df6: 2200 movs r2, #0
8007df8: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8007dfa: 687b ldr r3, [r7, #4]
8007dfc: 681b ldr r3, [r3, #0]
8007dfe: 699b ldr r3, [r3, #24]
8007e00: f003 0301 and.w r3, r3, #1
8007e04: 2b01 cmp r3, #1
8007e06: d007 beq.n 8007e18 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8007e08: 687b ldr r3, [r7, #4]
8007e0a: 681b ldr r3, [r3, #0]
8007e0c: 699a ldr r2, [r3, #24]
8007e0e: 687b ldr r3, [r7, #4]
8007e10: 681b ldr r3, [r3, #0]
8007e12: f042 0201 orr.w r2, r2, #1
8007e16: 619a str r2, [r3, #24]
}
}
8007e18: bf00 nop
8007e1a: 370c adds r7, #12
8007e1c: 46bd mov sp, r7
8007e1e: f85d 7b04 ldr.w r7, [sp], #4
8007e22: 4770 bx lr
08007e24 <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
8007e24: b580 push {r7, lr}
8007e26: b084 sub sp, #16
8007e28: af00 add r7, sp, #0
8007e2a: 60f8 str r0, [r7, #12]
8007e2c: 60b9 str r1, [r7, #8]
8007e2e: 603b str r3, [r7, #0]
8007e30: 4613 mov r3, r2
8007e32: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007e34: e022 b.n 8007e7c <I2C_WaitOnFlagUntilTimeout+0x58>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007e36: 683b ldr r3, [r7, #0]
8007e38: f1b3 3fff cmp.w r3, #4294967295
8007e3c: d01e beq.n 8007e7c <I2C_WaitOnFlagUntilTimeout+0x58>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007e3e: f7fc fdaf bl 80049a0 <HAL_GetTick>
8007e42: 4602 mov r2, r0
8007e44: 69bb ldr r3, [r7, #24]
8007e46: 1ad3 subs r3, r2, r3
8007e48: 683a ldr r2, [r7, #0]
8007e4a: 429a cmp r2, r3
8007e4c: d302 bcc.n 8007e54 <I2C_WaitOnFlagUntilTimeout+0x30>
8007e4e: 683b ldr r3, [r7, #0]
8007e50: 2b00 cmp r3, #0
8007e52: d113 bne.n 8007e7c <I2C_WaitOnFlagUntilTimeout+0x58>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007e54: 68fb ldr r3, [r7, #12]
8007e56: 6c5b ldr r3, [r3, #68] ; 0x44
8007e58: f043 0220 orr.w r2, r3, #32
8007e5c: 68fb ldr r3, [r7, #12]
8007e5e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007e60: 68fb ldr r3, [r7, #12]
8007e62: 2220 movs r2, #32
8007e64: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007e68: 68fb ldr r3, [r7, #12]
8007e6a: 2200 movs r2, #0
8007e6c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007e70: 68fb ldr r3, [r7, #12]
8007e72: 2200 movs r2, #0
8007e74: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007e78: 2301 movs r3, #1
8007e7a: e00f b.n 8007e9c <I2C_WaitOnFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
8007e7c: 68fb ldr r3, [r7, #12]
8007e7e: 681b ldr r3, [r3, #0]
8007e80: 699a ldr r2, [r3, #24]
8007e82: 68bb ldr r3, [r7, #8]
8007e84: 4013 ands r3, r2
8007e86: 68ba ldr r2, [r7, #8]
8007e88: 429a cmp r2, r3
8007e8a: bf0c ite eq
8007e8c: 2301 moveq r3, #1
8007e8e: 2300 movne r3, #0
8007e90: b2db uxtb r3, r3
8007e92: 461a mov r2, r3
8007e94: 79fb ldrb r3, [r7, #7]
8007e96: 429a cmp r2, r3
8007e98: d0cd beq.n 8007e36 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8007e9a: 2300 movs r3, #0
}
8007e9c: 4618 mov r0, r3
8007e9e: 3710 adds r7, #16
8007ea0: 46bd mov sp, r7
8007ea2: bd80 pop {r7, pc}
08007ea4 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007ea4: b580 push {r7, lr}
8007ea6: b084 sub sp, #16
8007ea8: af00 add r7, sp, #0
8007eaa: 60f8 str r0, [r7, #12]
8007eac: 60b9 str r1, [r7, #8]
8007eae: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007eb0: e02c b.n 8007f0c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007eb2: 687a ldr r2, [r7, #4]
8007eb4: 68b9 ldr r1, [r7, #8]
8007eb6: 68f8 ldr r0, [r7, #12]
8007eb8: f000 f870 bl 8007f9c <I2C_IsAcknowledgeFailed>
8007ebc: 4603 mov r3, r0
8007ebe: 2b00 cmp r3, #0
8007ec0: d001 beq.n 8007ec6 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007ec2: 2301 movs r3, #1
8007ec4: e02a b.n 8007f1c <I2C_WaitOnTXISFlagUntilTimeout+0x78>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007ec6: 68bb ldr r3, [r7, #8]
8007ec8: f1b3 3fff cmp.w r3, #4294967295
8007ecc: d01e beq.n 8007f0c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007ece: f7fc fd67 bl 80049a0 <HAL_GetTick>
8007ed2: 4602 mov r2, r0
8007ed4: 687b ldr r3, [r7, #4]
8007ed6: 1ad3 subs r3, r2, r3
8007ed8: 68ba ldr r2, [r7, #8]
8007eda: 429a cmp r2, r3
8007edc: d302 bcc.n 8007ee4 <I2C_WaitOnTXISFlagUntilTimeout+0x40>
8007ede: 68bb ldr r3, [r7, #8]
8007ee0: 2b00 cmp r3, #0
8007ee2: d113 bne.n 8007f0c <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007ee4: 68fb ldr r3, [r7, #12]
8007ee6: 6c5b ldr r3, [r3, #68] ; 0x44
8007ee8: f043 0220 orr.w r2, r3, #32
8007eec: 68fb ldr r3, [r7, #12]
8007eee: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007ef0: 68fb ldr r3, [r7, #12]
8007ef2: 2220 movs r2, #32
8007ef4: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007ef8: 68fb ldr r3, [r7, #12]
8007efa: 2200 movs r2, #0
8007efc: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007f00: 68fb ldr r3, [r7, #12]
8007f02: 2200 movs r2, #0
8007f04: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007f08: 2301 movs r3, #1
8007f0a: e007 b.n 8007f1c <I2C_WaitOnTXISFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8007f0c: 68fb ldr r3, [r7, #12]
8007f0e: 681b ldr r3, [r3, #0]
8007f10: 699b ldr r3, [r3, #24]
8007f12: f003 0302 and.w r3, r3, #2
8007f16: 2b02 cmp r3, #2
8007f18: d1cb bne.n 8007eb2 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8007f1a: 2300 movs r3, #0
}
8007f1c: 4618 mov r0, r3
8007f1e: 3710 adds r7, #16
8007f20: 46bd mov sp, r7
8007f22: bd80 pop {r7, pc}
08007f24 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007f24: b580 push {r7, lr}
8007f26: b084 sub sp, #16
8007f28: af00 add r7, sp, #0
8007f2a: 60f8 str r0, [r7, #12]
8007f2c: 60b9 str r1, [r7, #8]
8007f2e: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007f30: e028 b.n 8007f84 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
8007f32: 687a ldr r2, [r7, #4]
8007f34: 68b9 ldr r1, [r7, #8]
8007f36: 68f8 ldr r0, [r7, #12]
8007f38: f000 f830 bl 8007f9c <I2C_IsAcknowledgeFailed>
8007f3c: 4603 mov r3, r0
8007f3e: 2b00 cmp r3, #0
8007f40: d001 beq.n 8007f46 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
8007f42: 2301 movs r3, #1
8007f44: e026 b.n 8007f94 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007f46: f7fc fd2b bl 80049a0 <HAL_GetTick>
8007f4a: 4602 mov r2, r0
8007f4c: 687b ldr r3, [r7, #4]
8007f4e: 1ad3 subs r3, r2, r3
8007f50: 68ba ldr r2, [r7, #8]
8007f52: 429a cmp r2, r3
8007f54: d302 bcc.n 8007f5c <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
8007f56: 68bb ldr r3, [r7, #8]
8007f58: 2b00 cmp r3, #0
8007f5a: d113 bne.n 8007f84 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007f5c: 68fb ldr r3, [r7, #12]
8007f5e: 6c5b ldr r3, [r3, #68] ; 0x44
8007f60: f043 0220 orr.w r2, r3, #32
8007f64: 68fb ldr r3, [r7, #12]
8007f66: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007f68: 68fb ldr r3, [r7, #12]
8007f6a: 2220 movs r2, #32
8007f6c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007f70: 68fb ldr r3, [r7, #12]
8007f72: 2200 movs r2, #0
8007f74: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007f78: 68fb ldr r3, [r7, #12]
8007f7a: 2200 movs r2, #0
8007f7c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007f80: 2301 movs r3, #1
8007f82: e007 b.n 8007f94 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007f84: 68fb ldr r3, [r7, #12]
8007f86: 681b ldr r3, [r3, #0]
8007f88: 699b ldr r3, [r3, #24]
8007f8a: f003 0320 and.w r3, r3, #32
8007f8e: 2b20 cmp r3, #32
8007f90: d1cf bne.n 8007f32 <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
8007f92: 2300 movs r3, #0
}
8007f94: 4618 mov r0, r3
8007f96: 3710 adds r7, #16
8007f98: 46bd mov sp, r7
8007f9a: bd80 pop {r7, pc}
08007f9c <I2C_IsAcknowledgeFailed>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
8007f9c: b580 push {r7, lr}
8007f9e: b084 sub sp, #16
8007fa0: af00 add r7, sp, #0
8007fa2: 60f8 str r0, [r7, #12]
8007fa4: 60b9 str r1, [r7, #8]
8007fa6: 607a str r2, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8007fa8: 68fb ldr r3, [r7, #12]
8007faa: 681b ldr r3, [r3, #0]
8007fac: 699b ldr r3, [r3, #24]
8007fae: f003 0310 and.w r3, r3, #16
8007fb2: 2b10 cmp r3, #16
8007fb4: d151 bne.n 800805a <I2C_IsAcknowledgeFailed+0xbe>
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007fb6: e022 b.n 8007ffe <I2C_IsAcknowledgeFailed+0x62>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8007fb8: 68bb ldr r3, [r7, #8]
8007fba: f1b3 3fff cmp.w r3, #4294967295
8007fbe: d01e beq.n 8007ffe <I2C_IsAcknowledgeFailed+0x62>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8007fc0: f7fc fcee bl 80049a0 <HAL_GetTick>
8007fc4: 4602 mov r2, r0
8007fc6: 687b ldr r3, [r7, #4]
8007fc8: 1ad3 subs r3, r2, r3
8007fca: 68ba ldr r2, [r7, #8]
8007fcc: 429a cmp r2, r3
8007fce: d302 bcc.n 8007fd6 <I2C_IsAcknowledgeFailed+0x3a>
8007fd0: 68bb ldr r3, [r7, #8]
8007fd2: 2b00 cmp r3, #0
8007fd4: d113 bne.n 8007ffe <I2C_IsAcknowledgeFailed+0x62>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8007fd6: 68fb ldr r3, [r7, #12]
8007fd8: 6c5b ldr r3, [r3, #68] ; 0x44
8007fda: f043 0220 orr.w r2, r3, #32
8007fde: 68fb ldr r3, [r7, #12]
8007fe0: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8007fe2: 68fb ldr r3, [r7, #12]
8007fe4: 2220 movs r2, #32
8007fe6: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8007fea: 68fb ldr r3, [r7, #12]
8007fec: 2200 movs r2, #0
8007fee: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8007ff2: 68fb ldr r3, [r7, #12]
8007ff4: 2200 movs r2, #0
8007ff6: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8007ffa: 2301 movs r3, #1
8007ffc: e02e b.n 800805c <I2C_IsAcknowledgeFailed+0xc0>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8007ffe: 68fb ldr r3, [r7, #12]
8008000: 681b ldr r3, [r3, #0]
8008002: 699b ldr r3, [r3, #24]
8008004: f003 0320 and.w r3, r3, #32
8008008: 2b20 cmp r3, #32
800800a: d1d5 bne.n 8007fb8 <I2C_IsAcknowledgeFailed+0x1c>
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800800c: 68fb ldr r3, [r7, #12]
800800e: 681b ldr r3, [r3, #0]
8008010: 2210 movs r2, #16
8008012: 61da str r2, [r3, #28]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8008014: 68fb ldr r3, [r7, #12]
8008016: 681b ldr r3, [r3, #0]
8008018: 2220 movs r2, #32
800801a: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
800801c: 68f8 ldr r0, [r7, #12]
800801e: f7ff fedd bl 8007ddc <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8008022: 68fb ldr r3, [r7, #12]
8008024: 681b ldr r3, [r3, #0]
8008026: 6859 ldr r1, [r3, #4]
8008028: 68fb ldr r3, [r7, #12]
800802a: 681a ldr r2, [r3, #0]
800802c: 4b0d ldr r3, [pc, #52] ; (8008064 <I2C_IsAcknowledgeFailed+0xc8>)
800802e: 400b ands r3, r1
8008030: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8008032: 68fb ldr r3, [r7, #12]
8008034: 6c5b ldr r3, [r3, #68] ; 0x44
8008036: f043 0204 orr.w r2, r3, #4
800803a: 68fb ldr r3, [r7, #12]
800803c: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
800803e: 68fb ldr r3, [r7, #12]
8008040: 2220 movs r2, #32
8008042: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8008046: 68fb ldr r3, [r7, #12]
8008048: 2200 movs r2, #0
800804a: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800804e: 68fb ldr r3, [r7, #12]
8008050: 2200 movs r2, #0
8008052: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8008056: 2301 movs r3, #1
8008058: e000 b.n 800805c <I2C_IsAcknowledgeFailed+0xc0>
}
return HAL_OK;
800805a: 2300 movs r3, #0
}
800805c: 4618 mov r0, r3
800805e: 3710 adds r7, #16
8008060: 46bd mov sp, r7
8008062: bd80 pop {r7, pc}
8008064: fe00e800 .word 0xfe00e800
08008068 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
8008068: b480 push {r7}
800806a: b085 sub sp, #20
800806c: af00 add r7, sp, #0
800806e: 60f8 str r0, [r7, #12]
8008070: 607b str r3, [r7, #4]
8008072: 460b mov r3, r1
8008074: 817b strh r3, [r7, #10]
8008076: 4613 mov r3, r2
8008078: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
800807a: 68fb ldr r3, [r7, #12]
800807c: 681b ldr r3, [r3, #0]
800807e: 685a ldr r2, [r3, #4]
8008080: 69bb ldr r3, [r7, #24]
8008082: 0d5b lsrs r3, r3, #21
8008084: f403 6180 and.w r1, r3, #1024 ; 0x400
8008088: 4b0d ldr r3, [pc, #52] ; (80080c0 <I2C_TransferConfig+0x58>)
800808a: 430b orrs r3, r1
800808c: 43db mvns r3, r3
800808e: ea02 0103 and.w r1, r2, r3
8008092: 897b ldrh r3, [r7, #10]
8008094: f3c3 0209 ubfx r2, r3, #0, #10
8008098: 7a7b ldrb r3, [r7, #9]
800809a: 041b lsls r3, r3, #16
800809c: f403 037f and.w r3, r3, #16711680 ; 0xff0000
80080a0: 431a orrs r2, r3
80080a2: 687b ldr r3, [r7, #4]
80080a4: 431a orrs r2, r3
80080a6: 69bb ldr r3, [r7, #24]
80080a8: 431a orrs r2, r3
80080aa: 68fb ldr r3, [r7, #12]
80080ac: 681b ldr r3, [r3, #0]
80080ae: 430a orrs r2, r1
80080b0: 605a str r2, [r3, #4]
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
80080b2: bf00 nop
80080b4: 3714 adds r7, #20
80080b6: 46bd mov sp, r7
80080b8: f85d 7b04 ldr.w r7, [sp], #4
80080bc: 4770 bx lr
80080be: bf00 nop
80080c0: 03ff63ff .word 0x03ff63ff
080080c4 <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
80080c4: b580 push {r7, lr}
80080c6: b084 sub sp, #16
80080c8: af00 add r7, sp, #0
80080ca: 6078 str r0, [r7, #4]
uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
80080cc: 687b ldr r3, [r7, #4]
80080ce: 2b00 cmp r3, #0
80080d0: d101 bne.n 80080d6 <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
80080d2: 2301 movs r3, #1
80080d4: e0bf b.n 8008256 <HAL_LTDC_Init+0x192>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
80080d6: 687b ldr r3, [r7, #4]
80080d8: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
80080dc: b2db uxtb r3, r3
80080de: 2b00 cmp r3, #0
80080e0: d106 bne.n 80080f0 <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
80080e2: 687b ldr r3, [r7, #4]
80080e4: 2200 movs r2, #0
80080e6: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
80080ea: 6878 ldr r0, [r7, #4]
80080ec: f7fb fffa bl 80040e4 <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
80080f0: 687b ldr r3, [r7, #4]
80080f2: 2202 movs r2, #2
80080f4: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
80080f8: 687b ldr r3, [r7, #4]
80080fa: 681b ldr r3, [r3, #0]
80080fc: 699a ldr r2, [r3, #24]
80080fe: 687b ldr r3, [r7, #4]
8008100: 681b ldr r3, [r3, #0]
8008102: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
8008106: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8008108: 687b ldr r3, [r7, #4]
800810a: 681b ldr r3, [r3, #0]
800810c: 6999 ldr r1, [r3, #24]
800810e: 687b ldr r3, [r7, #4]
8008110: 685a ldr r2, [r3, #4]
8008112: 687b ldr r3, [r7, #4]
8008114: 689b ldr r3, [r3, #8]
8008116: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8008118: 687b ldr r3, [r7, #4]
800811a: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
800811c: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
800811e: 687b ldr r3, [r7, #4]
8008120: 691b ldr r3, [r3, #16]
8008122: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8008124: 687b ldr r3, [r7, #4]
8008126: 681b ldr r3, [r3, #0]
8008128: 430a orrs r2, r1
800812a: 619a str r2, [r3, #24]
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
800812c: 687b ldr r3, [r7, #4]
800812e: 681b ldr r3, [r3, #0]
8008130: 6899 ldr r1, [r3, #8]
8008132: 687b ldr r3, [r7, #4]
8008134: 681a ldr r2, [r3, #0]
8008136: 4b4a ldr r3, [pc, #296] ; (8008260 <HAL_LTDC_Init+0x19c>)
8008138: 400b ands r3, r1
800813a: 6093 str r3, [r2, #8]
tmp = (hltdc->Init.HorizontalSync << 16U);
800813c: 687b ldr r3, [r7, #4]
800813e: 695b ldr r3, [r3, #20]
8008140: 041b lsls r3, r3, #16
8008142: 60fb str r3, [r7, #12]
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
8008144: 687b ldr r3, [r7, #4]
8008146: 681b ldr r3, [r3, #0]
8008148: 6899 ldr r1, [r3, #8]
800814a: 687b ldr r3, [r7, #4]
800814c: 699a ldr r2, [r3, #24]
800814e: 68fb ldr r3, [r7, #12]
8008150: 431a orrs r2, r3
8008152: 687b ldr r3, [r7, #4]
8008154: 681b ldr r3, [r3, #0]
8008156: 430a orrs r2, r1
8008158: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
800815a: 687b ldr r3, [r7, #4]
800815c: 681b ldr r3, [r3, #0]
800815e: 68d9 ldr r1, [r3, #12]
8008160: 687b ldr r3, [r7, #4]
8008162: 681a ldr r2, [r3, #0]
8008164: 4b3e ldr r3, [pc, #248] ; (8008260 <HAL_LTDC_Init+0x19c>)
8008166: 400b ands r3, r1
8008168: 60d3 str r3, [r2, #12]
tmp = (hltdc->Init.AccumulatedHBP << 16U);
800816a: 687b ldr r3, [r7, #4]
800816c: 69db ldr r3, [r3, #28]
800816e: 041b lsls r3, r3, #16
8008170: 60fb str r3, [r7, #12]
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
8008172: 687b ldr r3, [r7, #4]
8008174: 681b ldr r3, [r3, #0]
8008176: 68d9 ldr r1, [r3, #12]
8008178: 687b ldr r3, [r7, #4]
800817a: 6a1a ldr r2, [r3, #32]
800817c: 68fb ldr r3, [r7, #12]
800817e: 431a orrs r2, r3
8008180: 687b ldr r3, [r7, #4]
8008182: 681b ldr r3, [r3, #0]
8008184: 430a orrs r2, r1
8008186: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
8008188: 687b ldr r3, [r7, #4]
800818a: 681b ldr r3, [r3, #0]
800818c: 6919 ldr r1, [r3, #16]
800818e: 687b ldr r3, [r7, #4]
8008190: 681a ldr r2, [r3, #0]
8008192: 4b33 ldr r3, [pc, #204] ; (8008260 <HAL_LTDC_Init+0x19c>)
8008194: 400b ands r3, r1
8008196: 6113 str r3, [r2, #16]
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
8008198: 687b ldr r3, [r7, #4]
800819a: 6a5b ldr r3, [r3, #36] ; 0x24
800819c: 041b lsls r3, r3, #16
800819e: 60fb str r3, [r7, #12]
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
80081a0: 687b ldr r3, [r7, #4]
80081a2: 681b ldr r3, [r3, #0]
80081a4: 6919 ldr r1, [r3, #16]
80081a6: 687b ldr r3, [r7, #4]
80081a8: 6a9a ldr r2, [r3, #40] ; 0x28
80081aa: 68fb ldr r3, [r7, #12]
80081ac: 431a orrs r2, r3
80081ae: 687b ldr r3, [r7, #4]
80081b0: 681b ldr r3, [r3, #0]
80081b2: 430a orrs r2, r1
80081b4: 611a str r2, [r3, #16]
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
80081b6: 687b ldr r3, [r7, #4]
80081b8: 681b ldr r3, [r3, #0]
80081ba: 6959 ldr r1, [r3, #20]
80081bc: 687b ldr r3, [r7, #4]
80081be: 681a ldr r2, [r3, #0]
80081c0: 4b27 ldr r3, [pc, #156] ; (8008260 <HAL_LTDC_Init+0x19c>)
80081c2: 400b ands r3, r1
80081c4: 6153 str r3, [r2, #20]
tmp = (hltdc->Init.TotalWidth << 16U);
80081c6: 687b ldr r3, [r7, #4]
80081c8: 6adb ldr r3, [r3, #44] ; 0x2c
80081ca: 041b lsls r3, r3, #16
80081cc: 60fb str r3, [r7, #12]
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
80081ce: 687b ldr r3, [r7, #4]
80081d0: 681b ldr r3, [r3, #0]
80081d2: 6959 ldr r1, [r3, #20]
80081d4: 687b ldr r3, [r7, #4]
80081d6: 6b1a ldr r2, [r3, #48] ; 0x30
80081d8: 68fb ldr r3, [r7, #12]
80081da: 431a orrs r2, r3
80081dc: 687b ldr r3, [r7, #4]
80081de: 681b ldr r3, [r3, #0]
80081e0: 430a orrs r2, r1
80081e2: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
80081e4: 687b ldr r3, [r7, #4]
80081e6: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
80081ea: 021b lsls r3, r3, #8
80081ec: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
80081ee: 687b ldr r3, [r7, #4]
80081f0: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
80081f4: 041b lsls r3, r3, #16
80081f6: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
80081f8: 687b ldr r3, [r7, #4]
80081fa: 681b ldr r3, [r3, #0]
80081fc: 6ada ldr r2, [r3, #44] ; 0x2c
80081fe: 687b ldr r3, [r7, #4]
8008200: 681b ldr r3, [r3, #0]
8008202: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
8008206: 62da str r2, [r3, #44] ; 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8008208: 687b ldr r3, [r7, #4]
800820a: 681b ldr r3, [r3, #0]
800820c: 6ad9 ldr r1, [r3, #44] ; 0x2c
800820e: 68ba ldr r2, [r7, #8]
8008210: 68fb ldr r3, [r7, #12]
8008212: 4313 orrs r3, r2
8008214: 687a ldr r2, [r7, #4]
8008216: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
800821a: 431a orrs r2, r3
800821c: 687b ldr r3, [r7, #4]
800821e: 681b ldr r3, [r3, #0]
8008220: 430a orrs r2, r1
8008222: 62da str r2, [r3, #44] ; 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
8008224: 687b ldr r3, [r7, #4]
8008226: 681b ldr r3, [r3, #0]
8008228: 6b5a ldr r2, [r3, #52] ; 0x34
800822a: 687b ldr r3, [r7, #4]
800822c: 681b ldr r3, [r3, #0]
800822e: f042 0206 orr.w r2, r2, #6
8008232: 635a str r2, [r3, #52] ; 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
8008234: 687b ldr r3, [r7, #4]
8008236: 681b ldr r3, [r3, #0]
8008238: 699a ldr r2, [r3, #24]
800823a: 687b ldr r3, [r7, #4]
800823c: 681b ldr r3, [r3, #0]
800823e: f042 0201 orr.w r2, r2, #1
8008242: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
8008244: 687b ldr r3, [r7, #4]
8008246: 2200 movs r2, #0
8008248: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
800824c: 687b ldr r3, [r7, #4]
800824e: 2201 movs r2, #1
8008250: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
return HAL_OK;
8008254: 2300 movs r3, #0
}
8008256: 4618 mov r0, r3
8008258: 3710 adds r7, #16
800825a: 46bd mov sp, r7
800825c: bd80 pop {r7, pc}
800825e: bf00 nop
8008260: f000f800 .word 0xf000f800
08008264 <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
8008264: b580 push {r7, lr}
8008266: b084 sub sp, #16
8008268: af00 add r7, sp, #0
800826a: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
800826c: 687b ldr r3, [r7, #4]
800826e: 681b ldr r3, [r3, #0]
8008270: 6b9b ldr r3, [r3, #56] ; 0x38
8008272: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
8008274: 687b ldr r3, [r7, #4]
8008276: 681b ldr r3, [r3, #0]
8008278: 6b5b ldr r3, [r3, #52] ; 0x34
800827a: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
800827c: 68fb ldr r3, [r7, #12]
800827e: f003 0304 and.w r3, r3, #4
8008282: 2b00 cmp r3, #0
8008284: d023 beq.n 80082ce <HAL_LTDC_IRQHandler+0x6a>
8008286: 68bb ldr r3, [r7, #8]
8008288: f003 0304 and.w r3, r3, #4
800828c: 2b00 cmp r3, #0
800828e: d01e beq.n 80082ce <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
8008290: 687b ldr r3, [r7, #4]
8008292: 681b ldr r3, [r3, #0]
8008294: 6b5a ldr r2, [r3, #52] ; 0x34
8008296: 687b ldr r3, [r7, #4]
8008298: 681b ldr r3, [r3, #0]
800829a: f022 0204 bic.w r2, r2, #4
800829e: 635a str r2, [r3, #52] ; 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
80082a0: 687b ldr r3, [r7, #4]
80082a2: 681b ldr r3, [r3, #0]
80082a4: 2204 movs r2, #4
80082a6: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
80082a8: 687b ldr r3, [r7, #4]
80082aa: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
80082ae: f043 0201 orr.w r2, r3, #1
80082b2: 687b ldr r3, [r7, #4]
80082b4: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
80082b8: 687b ldr r3, [r7, #4]
80082ba: 2204 movs r2, #4
80082bc: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80082c0: 687b ldr r3, [r7, #4]
80082c2: 2200 movs r2, #0
80082c4: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
80082c8: 6878 ldr r0, [r7, #4]
80082ca: f000 f86f bl 80083ac <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
80082ce: 68fb ldr r3, [r7, #12]
80082d0: f003 0302 and.w r3, r3, #2
80082d4: 2b00 cmp r3, #0
80082d6: d023 beq.n 8008320 <HAL_LTDC_IRQHandler+0xbc>
80082d8: 68bb ldr r3, [r7, #8]
80082da: f003 0302 and.w r3, r3, #2
80082de: 2b00 cmp r3, #0
80082e0: d01e beq.n 8008320 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
80082e2: 687b ldr r3, [r7, #4]
80082e4: 681b ldr r3, [r3, #0]
80082e6: 6b5a ldr r2, [r3, #52] ; 0x34
80082e8: 687b ldr r3, [r7, #4]
80082ea: 681b ldr r3, [r3, #0]
80082ec: f022 0202 bic.w r2, r2, #2
80082f0: 635a str r2, [r3, #52] ; 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
80082f2: 687b ldr r3, [r7, #4]
80082f4: 681b ldr r3, [r3, #0]
80082f6: 2202 movs r2, #2
80082f8: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
80082fa: 687b ldr r3, [r7, #4]
80082fc: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
8008300: f043 0202 orr.w r2, r3, #2
8008304: 687b ldr r3, [r7, #4]
8008306: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
800830a: 687b ldr r3, [r7, #4]
800830c: 2204 movs r2, #4
800830e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008312: 687b ldr r3, [r7, #4]
8008314: 2200 movs r2, #0
8008316: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
800831a: 6878 ldr r0, [r7, #4]
800831c: f000 f846 bl 80083ac <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
8008320: 68fb ldr r3, [r7, #12]
8008322: f003 0301 and.w r3, r3, #1
8008326: 2b00 cmp r3, #0
8008328: d01b beq.n 8008362 <HAL_LTDC_IRQHandler+0xfe>
800832a: 68bb ldr r3, [r7, #8]
800832c: f003 0301 and.w r3, r3, #1
8008330: 2b00 cmp r3, #0
8008332: d016 beq.n 8008362 <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
8008334: 687b ldr r3, [r7, #4]
8008336: 681b ldr r3, [r3, #0]
8008338: 6b5a ldr r2, [r3, #52] ; 0x34
800833a: 687b ldr r3, [r7, #4]
800833c: 681b ldr r3, [r3, #0]
800833e: f022 0201 bic.w r2, r2, #1
8008342: 635a str r2, [r3, #52] ; 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
8008344: 687b ldr r3, [r7, #4]
8008346: 681b ldr r3, [r3, #0]
8008348: 2201 movs r2, #1
800834a: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
800834c: 687b ldr r3, [r7, #4]
800834e: 2201 movs r2, #1
8008350: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008354: 687b ldr r3, [r7, #4]
8008356: 2200 movs r2, #0
8008358: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
800835c: 6878 ldr r0, [r7, #4]
800835e: f000 f82f bl 80083c0 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
8008362: 68fb ldr r3, [r7, #12]
8008364: f003 0308 and.w r3, r3, #8
8008368: 2b00 cmp r3, #0
800836a: d01b beq.n 80083a4 <HAL_LTDC_IRQHandler+0x140>
800836c: 68bb ldr r3, [r7, #8]
800836e: f003 0308 and.w r3, r3, #8
8008372: 2b00 cmp r3, #0
8008374: d016 beq.n 80083a4 <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
8008376: 687b ldr r3, [r7, #4]
8008378: 681b ldr r3, [r3, #0]
800837a: 6b5a ldr r2, [r3, #52] ; 0x34
800837c: 687b ldr r3, [r7, #4]
800837e: 681b ldr r3, [r3, #0]
8008380: f022 0208 bic.w r2, r2, #8
8008384: 635a str r2, [r3, #52] ; 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
8008386: 687b ldr r3, [r7, #4]
8008388: 681b ldr r3, [r3, #0]
800838a: 2208 movs r2, #8
800838c: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
800838e: 687b ldr r3, [r7, #4]
8008390: 2201 movs r2, #1
8008392: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008396: 687b ldr r3, [r7, #4]
8008398: 2200 movs r2, #0
800839a: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
800839e: 6878 ldr r0, [r7, #4]
80083a0: f000 f818 bl 80083d4 <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
80083a4: bf00 nop
80083a6: 3710 adds r7, #16
80083a8: 46bd mov sp, r7
80083aa: bd80 pop {r7, pc}
080083ac <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
80083ac: b480 push {r7}
80083ae: b083 sub sp, #12
80083b0: af00 add r7, sp, #0
80083b2: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
80083b4: bf00 nop
80083b6: 370c adds r7, #12
80083b8: 46bd mov sp, r7
80083ba: f85d 7b04 ldr.w r7, [sp], #4
80083be: 4770 bx lr
080083c0 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
80083c0: b480 push {r7}
80083c2: b083 sub sp, #12
80083c4: af00 add r7, sp, #0
80083c6: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
80083c8: bf00 nop
80083ca: 370c adds r7, #12
80083cc: 46bd mov sp, r7
80083ce: f85d 7b04 ldr.w r7, [sp], #4
80083d2: 4770 bx lr
080083d4 <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
80083d4: b480 push {r7}
80083d6: b083 sub sp, #12
80083d8: af00 add r7, sp, #0
80083da: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
80083dc: bf00 nop
80083de: 370c adds r7, #12
80083e0: 46bd mov sp, r7
80083e2: f85d 7b04 ldr.w r7, [sp], #4
80083e6: 4770 bx lr
080083e8 <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
80083e8: b5b0 push {r4, r5, r7, lr}
80083ea: b084 sub sp, #16
80083ec: af00 add r7, sp, #0
80083ee: 60f8 str r0, [r7, #12]
80083f0: 60b9 str r1, [r7, #8]
80083f2: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
80083f4: 68fb ldr r3, [r7, #12]
80083f6: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
80083fa: 2b01 cmp r3, #1
80083fc: d101 bne.n 8008402 <HAL_LTDC_ConfigLayer+0x1a>
80083fe: 2302 movs r3, #2
8008400: e02c b.n 800845c <HAL_LTDC_ConfigLayer+0x74>
8008402: 68fb ldr r3, [r7, #12]
8008404: 2201 movs r2, #1
8008406: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
800840a: 68fb ldr r3, [r7, #12]
800840c: 2202 movs r2, #2
800840e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
8008412: 68fa ldr r2, [r7, #12]
8008414: 687b ldr r3, [r7, #4]
8008416: 2134 movs r1, #52 ; 0x34
8008418: fb01 f303 mul.w r3, r1, r3
800841c: 4413 add r3, r2
800841e: f103 0238 add.w r2, r3, #56 ; 0x38
8008422: 68bb ldr r3, [r7, #8]
8008424: 4614 mov r4, r2
8008426: 461d mov r5, r3
8008428: cd0f ldmia r5!, {r0, r1, r2, r3}
800842a: c40f stmia r4!, {r0, r1, r2, r3}
800842c: cd0f ldmia r5!, {r0, r1, r2, r3}
800842e: c40f stmia r4!, {r0, r1, r2, r3}
8008430: cd0f ldmia r5!, {r0, r1, r2, r3}
8008432: c40f stmia r4!, {r0, r1, r2, r3}
8008434: 682b ldr r3, [r5, #0]
8008436: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
8008438: 687a ldr r2, [r7, #4]
800843a: 68b9 ldr r1, [r7, #8]
800843c: 68f8 ldr r0, [r7, #12]
800843e: f000 f81f bl 8008480 <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
8008442: 68fb ldr r3, [r7, #12]
8008444: 681b ldr r3, [r3, #0]
8008446: 2201 movs r2, #1
8008448: 625a str r2, [r3, #36] ; 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
800844a: 68fb ldr r3, [r7, #12]
800844c: 2201 movs r2, #1
800844e: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8008452: 68fb ldr r3, [r7, #12]
8008454: 2200 movs r2, #0
8008456: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
return HAL_OK;
800845a: 2300 movs r3, #0
}
800845c: 4618 mov r0, r3
800845e: 3710 adds r7, #16
8008460: 46bd mov sp, r7
8008462: bdb0 pop {r4, r5, r7, pc}
08008464 <HAL_LTDC_GetState>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
{
8008464: b480 push {r7}
8008466: b083 sub sp, #12
8008468: af00 add r7, sp, #0
800846a: 6078 str r0, [r7, #4]
return hltdc->State;
800846c: 687b ldr r3, [r7, #4]
800846e: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8008472: b2db uxtb r3, r3
}
8008474: 4618 mov r0, r3
8008476: 370c adds r7, #12
8008478: 46bd mov sp, r7
800847a: f85d 7b04 ldr.w r7, [sp], #4
800847e: 4770 bx lr
08008480 <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8008480: b480 push {r7}
8008482: b089 sub sp, #36 ; 0x24
8008484: af00 add r7, sp, #0
8008486: 60f8 str r0, [r7, #12]
8008488: 60b9 str r1, [r7, #8]
800848a: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
800848c: 68bb ldr r3, [r7, #8]
800848e: 685a ldr r2, [r3, #4]
8008490: 68fb ldr r3, [r7, #12]
8008492: 681b ldr r3, [r3, #0]
8008494: 68db ldr r3, [r3, #12]
8008496: 0c1b lsrs r3, r3, #16
8008498: f3c3 030b ubfx r3, r3, #0, #12
800849c: 4413 add r3, r2
800849e: 041b lsls r3, r3, #16
80084a0: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
80084a2: 68fb ldr r3, [r7, #12]
80084a4: 681b ldr r3, [r3, #0]
80084a6: 461a mov r2, r3
80084a8: 687b ldr r3, [r7, #4]
80084aa: 01db lsls r3, r3, #7
80084ac: 4413 add r3, r2
80084ae: 3384 adds r3, #132 ; 0x84
80084b0: 685b ldr r3, [r3, #4]
80084b2: 68fa ldr r2, [r7, #12]
80084b4: 6812 ldr r2, [r2, #0]
80084b6: 4611 mov r1, r2
80084b8: 687a ldr r2, [r7, #4]
80084ba: 01d2 lsls r2, r2, #7
80084bc: 440a add r2, r1
80084be: 3284 adds r2, #132 ; 0x84
80084c0: f403 4370 and.w r3, r3, #61440 ; 0xf000
80084c4: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
80084c6: 68bb ldr r3, [r7, #8]
80084c8: 681a ldr r2, [r3, #0]
80084ca: 68fb ldr r3, [r7, #12]
80084cc: 681b ldr r3, [r3, #0]
80084ce: 68db ldr r3, [r3, #12]
80084d0: 0c1b lsrs r3, r3, #16
80084d2: f3c3 030b ubfx r3, r3, #0, #12
80084d6: 4413 add r3, r2
80084d8: 1c5a adds r2, r3, #1
80084da: 68fb ldr r3, [r7, #12]
80084dc: 681b ldr r3, [r3, #0]
80084de: 4619 mov r1, r3
80084e0: 687b ldr r3, [r7, #4]
80084e2: 01db lsls r3, r3, #7
80084e4: 440b add r3, r1
80084e6: 3384 adds r3, #132 ; 0x84
80084e8: 4619 mov r1, r3
80084ea: 69fb ldr r3, [r7, #28]
80084ec: 4313 orrs r3, r2
80084ee: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
80084f0: 68bb ldr r3, [r7, #8]
80084f2: 68da ldr r2, [r3, #12]
80084f4: 68fb ldr r3, [r7, #12]
80084f6: 681b ldr r3, [r3, #0]
80084f8: 68db ldr r3, [r3, #12]
80084fa: f3c3 030a ubfx r3, r3, #0, #11
80084fe: 4413 add r3, r2
8008500: 041b lsls r3, r3, #16
8008502: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
8008504: 68fb ldr r3, [r7, #12]
8008506: 681b ldr r3, [r3, #0]
8008508: 461a mov r2, r3
800850a: 687b ldr r3, [r7, #4]
800850c: 01db lsls r3, r3, #7
800850e: 4413 add r3, r2
8008510: 3384 adds r3, #132 ; 0x84
8008512: 689b ldr r3, [r3, #8]
8008514: 68fa ldr r2, [r7, #12]
8008516: 6812 ldr r2, [r2, #0]
8008518: 4611 mov r1, r2
800851a: 687a ldr r2, [r7, #4]
800851c: 01d2 lsls r2, r2, #7
800851e: 440a add r2, r1
8008520: 3284 adds r2, #132 ; 0x84
8008522: f403 4370 and.w r3, r3, #61440 ; 0xf000
8008526: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
8008528: 68bb ldr r3, [r7, #8]
800852a: 689a ldr r2, [r3, #8]
800852c: 68fb ldr r3, [r7, #12]
800852e: 681b ldr r3, [r3, #0]
8008530: 68db ldr r3, [r3, #12]
8008532: f3c3 030a ubfx r3, r3, #0, #11
8008536: 4413 add r3, r2
8008538: 1c5a adds r2, r3, #1
800853a: 68fb ldr r3, [r7, #12]
800853c: 681b ldr r3, [r3, #0]
800853e: 4619 mov r1, r3
8008540: 687b ldr r3, [r7, #4]
8008542: 01db lsls r3, r3, #7
8008544: 440b add r3, r1
8008546: 3384 adds r3, #132 ; 0x84
8008548: 4619 mov r1, r3
800854a: 69fb ldr r3, [r7, #28]
800854c: 4313 orrs r3, r2
800854e: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
8008550: 68fb ldr r3, [r7, #12]
8008552: 681b ldr r3, [r3, #0]
8008554: 461a mov r2, r3
8008556: 687b ldr r3, [r7, #4]
8008558: 01db lsls r3, r3, #7
800855a: 4413 add r3, r2
800855c: 3384 adds r3, #132 ; 0x84
800855e: 691b ldr r3, [r3, #16]
8008560: 68fa ldr r2, [r7, #12]
8008562: 6812 ldr r2, [r2, #0]
8008564: 4611 mov r1, r2
8008566: 687a ldr r2, [r7, #4]
8008568: 01d2 lsls r2, r2, #7
800856a: 440a add r2, r1
800856c: 3284 adds r2, #132 ; 0x84
800856e: f023 0307 bic.w r3, r3, #7
8008572: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
8008574: 68fb ldr r3, [r7, #12]
8008576: 681b ldr r3, [r3, #0]
8008578: 461a mov r2, r3
800857a: 687b ldr r3, [r7, #4]
800857c: 01db lsls r3, r3, #7
800857e: 4413 add r3, r2
8008580: 3384 adds r3, #132 ; 0x84
8008582: 461a mov r2, r3
8008584: 68bb ldr r3, [r7, #8]
8008586: 691b ldr r3, [r3, #16]
8008588: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
800858a: 68bb ldr r3, [r7, #8]
800858c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8008590: 021b lsls r3, r3, #8
8008592: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
8008594: 68bb ldr r3, [r7, #8]
8008596: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
800859a: 041b lsls r3, r3, #16
800859c: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
800859e: 68bb ldr r3, [r7, #8]
80085a0: 699b ldr r3, [r3, #24]
80085a2: 061b lsls r3, r3, #24
80085a4: 617b str r3, [r7, #20]
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
80085a6: 68fb ldr r3, [r7, #12]
80085a8: 681b ldr r3, [r3, #0]
80085aa: 461a mov r2, r3
80085ac: 687b ldr r3, [r7, #4]
80085ae: 01db lsls r3, r3, #7
80085b0: 4413 add r3, r2
80085b2: 3384 adds r3, #132 ; 0x84
80085b4: 699b ldr r3, [r3, #24]
80085b6: 68fb ldr r3, [r7, #12]
80085b8: 681b ldr r3, [r3, #0]
80085ba: 461a mov r2, r3
80085bc: 687b ldr r3, [r7, #4]
80085be: 01db lsls r3, r3, #7
80085c0: 4413 add r3, r2
80085c2: 3384 adds r3, #132 ; 0x84
80085c4: 461a mov r2, r3
80085c6: 2300 movs r3, #0
80085c8: 6193 str r3, [r2, #24]
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
80085ca: 68bb ldr r3, [r7, #8]
80085cc: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80085d0: 461a mov r2, r3
80085d2: 69fb ldr r3, [r7, #28]
80085d4: 431a orrs r2, r3
80085d6: 69bb ldr r3, [r7, #24]
80085d8: 431a orrs r2, r3
80085da: 68fb ldr r3, [r7, #12]
80085dc: 681b ldr r3, [r3, #0]
80085de: 4619 mov r1, r3
80085e0: 687b ldr r3, [r7, #4]
80085e2: 01db lsls r3, r3, #7
80085e4: 440b add r3, r1
80085e6: 3384 adds r3, #132 ; 0x84
80085e8: 4619 mov r1, r3
80085ea: 697b ldr r3, [r7, #20]
80085ec: 4313 orrs r3, r2
80085ee: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
80085f0: 68fb ldr r3, [r7, #12]
80085f2: 681b ldr r3, [r3, #0]
80085f4: 461a mov r2, r3
80085f6: 687b ldr r3, [r7, #4]
80085f8: 01db lsls r3, r3, #7
80085fa: 4413 add r3, r2
80085fc: 3384 adds r3, #132 ; 0x84
80085fe: 695b ldr r3, [r3, #20]
8008600: 68fa ldr r2, [r7, #12]
8008602: 6812 ldr r2, [r2, #0]
8008604: 4611 mov r1, r2
8008606: 687a ldr r2, [r7, #4]
8008608: 01d2 lsls r2, r2, #7
800860a: 440a add r2, r1
800860c: 3284 adds r2, #132 ; 0x84
800860e: f023 03ff bic.w r3, r3, #255 ; 0xff
8008612: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
8008614: 68fb ldr r3, [r7, #12]
8008616: 681b ldr r3, [r3, #0]
8008618: 461a mov r2, r3
800861a: 687b ldr r3, [r7, #4]
800861c: 01db lsls r3, r3, #7
800861e: 4413 add r3, r2
8008620: 3384 adds r3, #132 ; 0x84
8008622: 461a mov r2, r3
8008624: 68bb ldr r3, [r7, #8]
8008626: 695b ldr r3, [r3, #20]
8008628: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
800862a: 68fb ldr r3, [r7, #12]
800862c: 681b ldr r3, [r3, #0]
800862e: 461a mov r2, r3
8008630: 687b ldr r3, [r7, #4]
8008632: 01db lsls r3, r3, #7
8008634: 4413 add r3, r2
8008636: 3384 adds r3, #132 ; 0x84
8008638: 69da ldr r2, [r3, #28]
800863a: 68fb ldr r3, [r7, #12]
800863c: 681b ldr r3, [r3, #0]
800863e: 4619 mov r1, r3
8008640: 687b ldr r3, [r7, #4]
8008642: 01db lsls r3, r3, #7
8008644: 440b add r3, r1
8008646: 3384 adds r3, #132 ; 0x84
8008648: 4619 mov r1, r3
800864a: 4b58 ldr r3, [pc, #352] ; (80087ac <LTDC_SetConfig+0x32c>)
800864c: 4013 ands r3, r2
800864e: 61cb str r3, [r1, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
8008650: 68bb ldr r3, [r7, #8]
8008652: 69da ldr r2, [r3, #28]
8008654: 68bb ldr r3, [r7, #8]
8008656: 6a1b ldr r3, [r3, #32]
8008658: 68f9 ldr r1, [r7, #12]
800865a: 6809 ldr r1, [r1, #0]
800865c: 4608 mov r0, r1
800865e: 6879 ldr r1, [r7, #4]
8008660: 01c9 lsls r1, r1, #7
8008662: 4401 add r1, r0
8008664: 3184 adds r1, #132 ; 0x84
8008666: 4313 orrs r3, r2
8008668: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
800866a: 68fb ldr r3, [r7, #12]
800866c: 681b ldr r3, [r3, #0]
800866e: 461a mov r2, r3
8008670: 687b ldr r3, [r7, #4]
8008672: 01db lsls r3, r3, #7
8008674: 4413 add r3, r2
8008676: 3384 adds r3, #132 ; 0x84
8008678: 6a9b ldr r3, [r3, #40] ; 0x28
800867a: 68fb ldr r3, [r7, #12]
800867c: 681b ldr r3, [r3, #0]
800867e: 461a mov r2, r3
8008680: 687b ldr r3, [r7, #4]
8008682: 01db lsls r3, r3, #7
8008684: 4413 add r3, r2
8008686: 3384 adds r3, #132 ; 0x84
8008688: 461a mov r2, r3
800868a: 2300 movs r3, #0
800868c: 6293 str r3, [r2, #40] ; 0x28
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
800868e: 68fb ldr r3, [r7, #12]
8008690: 681b ldr r3, [r3, #0]
8008692: 461a mov r2, r3
8008694: 687b ldr r3, [r7, #4]
8008696: 01db lsls r3, r3, #7
8008698: 4413 add r3, r2
800869a: 3384 adds r3, #132 ; 0x84
800869c: 461a mov r2, r3
800869e: 68bb ldr r3, [r7, #8]
80086a0: 6a5b ldr r3, [r3, #36] ; 0x24
80086a2: 6293 str r3, [r2, #40] ; 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
80086a4: 68bb ldr r3, [r7, #8]
80086a6: 691b ldr r3, [r3, #16]
80086a8: 2b00 cmp r3, #0
80086aa: d102 bne.n 80086b2 <LTDC_SetConfig+0x232>
{
tmp = 4U;
80086ac: 2304 movs r3, #4
80086ae: 61fb str r3, [r7, #28]
80086b0: e01b b.n 80086ea <LTDC_SetConfig+0x26a>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
80086b2: 68bb ldr r3, [r7, #8]
80086b4: 691b ldr r3, [r3, #16]
80086b6: 2b01 cmp r3, #1
80086b8: d102 bne.n 80086c0 <LTDC_SetConfig+0x240>
{
tmp = 3U;
80086ba: 2303 movs r3, #3
80086bc: 61fb str r3, [r7, #28]
80086be: e014 b.n 80086ea <LTDC_SetConfig+0x26a>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80086c0: 68bb ldr r3, [r7, #8]
80086c2: 691b ldr r3, [r3, #16]
80086c4: 2b04 cmp r3, #4
80086c6: d00b beq.n 80086e0 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80086c8: 68bb ldr r3, [r7, #8]
80086ca: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80086cc: 2b02 cmp r3, #2
80086ce: d007 beq.n 80086e0 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80086d0: 68bb ldr r3, [r7, #8]
80086d2: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80086d4: 2b03 cmp r3, #3
80086d6: d003 beq.n 80086e0 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
80086d8: 68bb ldr r3, [r7, #8]
80086da: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80086dc: 2b07 cmp r3, #7
80086de: d102 bne.n 80086e6 <LTDC_SetConfig+0x266>
{
tmp = 2U;
80086e0: 2302 movs r3, #2
80086e2: 61fb str r3, [r7, #28]
80086e4: e001 b.n 80086ea <LTDC_SetConfig+0x26a>
}
else
{
tmp = 1U;
80086e6: 2301 movs r3, #1
80086e8: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
80086ea: 68fb ldr r3, [r7, #12]
80086ec: 681b ldr r3, [r3, #0]
80086ee: 461a mov r2, r3
80086f0: 687b ldr r3, [r7, #4]
80086f2: 01db lsls r3, r3, #7
80086f4: 4413 add r3, r2
80086f6: 3384 adds r3, #132 ; 0x84
80086f8: 6adb ldr r3, [r3, #44] ; 0x2c
80086fa: 68fa ldr r2, [r7, #12]
80086fc: 6812 ldr r2, [r2, #0]
80086fe: 4611 mov r1, r2
8008700: 687a ldr r2, [r7, #4]
8008702: 01d2 lsls r2, r2, #7
8008704: 440a add r2, r1
8008706: 3284 adds r2, #132 ; 0x84
8008708: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
800870c: 62d3 str r3, [r2, #44] ; 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
800870e: 68bb ldr r3, [r7, #8]
8008710: 6a9b ldr r3, [r3, #40] ; 0x28
8008712: 69fa ldr r2, [r7, #28]
8008714: fb02 f303 mul.w r3, r2, r3
8008718: 041a lsls r2, r3, #16
800871a: 68bb ldr r3, [r7, #8]
800871c: 6859 ldr r1, [r3, #4]
800871e: 68bb ldr r3, [r7, #8]
8008720: 681b ldr r3, [r3, #0]
8008722: 1acb subs r3, r1, r3
8008724: 69f9 ldr r1, [r7, #28]
8008726: fb01 f303 mul.w r3, r1, r3
800872a: 3303 adds r3, #3
800872c: 68f9 ldr r1, [r7, #12]
800872e: 6809 ldr r1, [r1, #0]
8008730: 4608 mov r0, r1
8008732: 6879 ldr r1, [r7, #4]
8008734: 01c9 lsls r1, r1, #7
8008736: 4401 add r1, r0
8008738: 3184 adds r1, #132 ; 0x84
800873a: 4313 orrs r3, r2
800873c: 62cb str r3, [r1, #44] ; 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
800873e: 68fb ldr r3, [r7, #12]
8008740: 681b ldr r3, [r3, #0]
8008742: 461a mov r2, r3
8008744: 687b ldr r3, [r7, #4]
8008746: 01db lsls r3, r3, #7
8008748: 4413 add r3, r2
800874a: 3384 adds r3, #132 ; 0x84
800874c: 6b1a ldr r2, [r3, #48] ; 0x30
800874e: 68fb ldr r3, [r7, #12]
8008750: 681b ldr r3, [r3, #0]
8008752: 4619 mov r1, r3
8008754: 687b ldr r3, [r7, #4]
8008756: 01db lsls r3, r3, #7
8008758: 440b add r3, r1
800875a: 3384 adds r3, #132 ; 0x84
800875c: 4619 mov r1, r3
800875e: 4b14 ldr r3, [pc, #80] ; (80087b0 <LTDC_SetConfig+0x330>)
8008760: 4013 ands r3, r2
8008762: 630b str r3, [r1, #48] ; 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
8008764: 68fb ldr r3, [r7, #12]
8008766: 681b ldr r3, [r3, #0]
8008768: 461a mov r2, r3
800876a: 687b ldr r3, [r7, #4]
800876c: 01db lsls r3, r3, #7
800876e: 4413 add r3, r2
8008770: 3384 adds r3, #132 ; 0x84
8008772: 461a mov r2, r3
8008774: 68bb ldr r3, [r7, #8]
8008776: 6adb ldr r3, [r3, #44] ; 0x2c
8008778: 6313 str r3, [r2, #48] ; 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
800877a: 68fb ldr r3, [r7, #12]
800877c: 681b ldr r3, [r3, #0]
800877e: 461a mov r2, r3
8008780: 687b ldr r3, [r7, #4]
8008782: 01db lsls r3, r3, #7
8008784: 4413 add r3, r2
8008786: 3384 adds r3, #132 ; 0x84
8008788: 681b ldr r3, [r3, #0]
800878a: 68fa ldr r2, [r7, #12]
800878c: 6812 ldr r2, [r2, #0]
800878e: 4611 mov r1, r2
8008790: 687a ldr r2, [r7, #4]
8008792: 01d2 lsls r2, r2, #7
8008794: 440a add r2, r1
8008796: 3284 adds r2, #132 ; 0x84
8008798: f043 0301 orr.w r3, r3, #1
800879c: 6013 str r3, [r2, #0]
}
800879e: bf00 nop
80087a0: 3724 adds r7, #36 ; 0x24
80087a2: 46bd mov sp, r7
80087a4: f85d 7b04 ldr.w r7, [sp], #4
80087a8: 4770 bx lr
80087aa: bf00 nop
80087ac: fffff8f8 .word 0xfffff8f8
80087b0: fffff800 .word 0xfffff800
080087b4 <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
80087b4: b480 push {r7}
80087b6: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80087b8: 4b05 ldr r3, [pc, #20] ; (80087d0 <HAL_PWR_EnableBkUpAccess+0x1c>)
80087ba: 681b ldr r3, [r3, #0]
80087bc: 4a04 ldr r2, [pc, #16] ; (80087d0 <HAL_PWR_EnableBkUpAccess+0x1c>)
80087be: f443 7380 orr.w r3, r3, #256 ; 0x100
80087c2: 6013 str r3, [r2, #0]
}
80087c4: bf00 nop
80087c6: 46bd mov sp, r7
80087c8: f85d 7b04 ldr.w r7, [sp], #4
80087cc: 4770 bx lr
80087ce: bf00 nop
80087d0: 40007000 .word 0x40007000
080087d4 <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
80087d4: b580 push {r7, lr}
80087d6: b082 sub sp, #8
80087d8: af00 add r7, sp, #0
uint32_t tickstart = 0;
80087da: 2300 movs r3, #0
80087dc: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80087de: 4b23 ldr r3, [pc, #140] ; (800886c <HAL_PWREx_EnableOverDrive+0x98>)
80087e0: 6c1b ldr r3, [r3, #64] ; 0x40
80087e2: 4a22 ldr r2, [pc, #136] ; (800886c <HAL_PWREx_EnableOverDrive+0x98>)
80087e4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80087e8: 6413 str r3, [r2, #64] ; 0x40
80087ea: 4b20 ldr r3, [pc, #128] ; (800886c <HAL_PWREx_EnableOverDrive+0x98>)
80087ec: 6c1b ldr r3, [r3, #64] ; 0x40
80087ee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80087f2: 603b str r3, [r7, #0]
80087f4: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
80087f6: 4b1e ldr r3, [pc, #120] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
80087f8: 681b ldr r3, [r3, #0]
80087fa: 4a1d ldr r2, [pc, #116] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
80087fc: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8008800: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8008802: f7fc f8cd bl 80049a0 <HAL_GetTick>
8008806: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8008808: e009 b.n 800881e <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
800880a: f7fc f8c9 bl 80049a0 <HAL_GetTick>
800880e: 4602 mov r2, r0
8008810: 687b ldr r3, [r7, #4]
8008812: 1ad3 subs r3, r2, r3
8008814: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008818: d901 bls.n 800881e <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
800881a: 2303 movs r3, #3
800881c: e022 b.n 8008864 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
800881e: 4b14 ldr r3, [pc, #80] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
8008820: 685b ldr r3, [r3, #4]
8008822: f403 3380 and.w r3, r3, #65536 ; 0x10000
8008826: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800882a: d1ee bne.n 800880a <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
800882c: 4b10 ldr r3, [pc, #64] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
800882e: 681b ldr r3, [r3, #0]
8008830: 4a0f ldr r2, [pc, #60] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
8008832: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8008836: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8008838: f7fc f8b2 bl 80049a0 <HAL_GetTick>
800883c: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
800883e: e009 b.n 8008854 <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8008840: f7fc f8ae bl 80049a0 <HAL_GetTick>
8008844: 4602 mov r2, r0
8008846: 687b ldr r3, [r7, #4]
8008848: 1ad3 subs r3, r2, r3
800884a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800884e: d901 bls.n 8008854 <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
8008850: 2303 movs r3, #3
8008852: e007 b.n 8008864 <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8008854: 4b06 ldr r3, [pc, #24] ; (8008870 <HAL_PWREx_EnableOverDrive+0x9c>)
8008856: 685b ldr r3, [r3, #4]
8008858: f403 3300 and.w r3, r3, #131072 ; 0x20000
800885c: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
8008860: d1ee bne.n 8008840 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
8008862: 2300 movs r3, #0
}
8008864: 4618 mov r0, r3
8008866: 3708 adds r7, #8
8008868: 46bd mov sp, r7
800886a: bd80 pop {r7, pc}
800886c: 40023800 .word 0x40023800
8008870: 40007000 .word 0x40007000
08008874 <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8008874: b580 push {r7, lr}
8008876: b086 sub sp, #24
8008878: af00 add r7, sp, #0
800887a: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
800887c: 2300 movs r3, #0
800887e: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8008880: 687b ldr r3, [r7, #4]
8008882: 2b00 cmp r3, #0
8008884: d101 bne.n 800888a <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
8008886: 2301 movs r3, #1
8008888: e291 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800888a: 687b ldr r3, [r7, #4]
800888c: 681b ldr r3, [r3, #0]
800888e: f003 0301 and.w r3, r3, #1
8008892: 2b00 cmp r3, #0
8008894: f000 8087 beq.w 80089a6 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8008898: 4b96 ldr r3, [pc, #600] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
800889a: 689b ldr r3, [r3, #8]
800889c: f003 030c and.w r3, r3, #12
80088a0: 2b04 cmp r3, #4
80088a2: d00c beq.n 80088be <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80088a4: 4b93 ldr r3, [pc, #588] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088a6: 689b ldr r3, [r3, #8]
80088a8: f003 030c and.w r3, r3, #12
80088ac: 2b08 cmp r3, #8
80088ae: d112 bne.n 80088d6 <HAL_RCC_OscConfig+0x62>
80088b0: 4b90 ldr r3, [pc, #576] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088b2: 685b ldr r3, [r3, #4]
80088b4: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80088b8: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80088bc: d10b bne.n 80088d6 <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80088be: 4b8d ldr r3, [pc, #564] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088c0: 681b ldr r3, [r3, #0]
80088c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80088c6: 2b00 cmp r3, #0
80088c8: d06c beq.n 80089a4 <HAL_RCC_OscConfig+0x130>
80088ca: 687b ldr r3, [r7, #4]
80088cc: 685b ldr r3, [r3, #4]
80088ce: 2b00 cmp r3, #0
80088d0: d168 bne.n 80089a4 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
80088d2: 2301 movs r3, #1
80088d4: e26b b.n 8008dae <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80088d6: 687b ldr r3, [r7, #4]
80088d8: 685b ldr r3, [r3, #4]
80088da: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80088de: d106 bne.n 80088ee <HAL_RCC_OscConfig+0x7a>
80088e0: 4b84 ldr r3, [pc, #528] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088e2: 681b ldr r3, [r3, #0]
80088e4: 4a83 ldr r2, [pc, #524] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088e6: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80088ea: 6013 str r3, [r2, #0]
80088ec: e02e b.n 800894c <HAL_RCC_OscConfig+0xd8>
80088ee: 687b ldr r3, [r7, #4]
80088f0: 685b ldr r3, [r3, #4]
80088f2: 2b00 cmp r3, #0
80088f4: d10c bne.n 8008910 <HAL_RCC_OscConfig+0x9c>
80088f6: 4b7f ldr r3, [pc, #508] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088f8: 681b ldr r3, [r3, #0]
80088fa: 4a7e ldr r2, [pc, #504] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80088fc: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8008900: 6013 str r3, [r2, #0]
8008902: 4b7c ldr r3, [pc, #496] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008904: 681b ldr r3, [r3, #0]
8008906: 4a7b ldr r2, [pc, #492] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008908: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800890c: 6013 str r3, [r2, #0]
800890e: e01d b.n 800894c <HAL_RCC_OscConfig+0xd8>
8008910: 687b ldr r3, [r7, #4]
8008912: 685b ldr r3, [r3, #4]
8008914: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8008918: d10c bne.n 8008934 <HAL_RCC_OscConfig+0xc0>
800891a: 4b76 ldr r3, [pc, #472] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
800891c: 681b ldr r3, [r3, #0]
800891e: 4a75 ldr r2, [pc, #468] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008920: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8008924: 6013 str r3, [r2, #0]
8008926: 4b73 ldr r3, [pc, #460] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008928: 681b ldr r3, [r3, #0]
800892a: 4a72 ldr r2, [pc, #456] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
800892c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8008930: 6013 str r3, [r2, #0]
8008932: e00b b.n 800894c <HAL_RCC_OscConfig+0xd8>
8008934: 4b6f ldr r3, [pc, #444] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008936: 681b ldr r3, [r3, #0]
8008938: 4a6e ldr r2, [pc, #440] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
800893a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800893e: 6013 str r3, [r2, #0]
8008940: 4b6c ldr r3, [pc, #432] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008942: 681b ldr r3, [r3, #0]
8008944: 4a6b ldr r2, [pc, #428] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008946: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800894a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
800894c: 687b ldr r3, [r7, #4]
800894e: 685b ldr r3, [r3, #4]
8008950: 2b00 cmp r3, #0
8008952: d013 beq.n 800897c <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008954: f7fc f824 bl 80049a0 <HAL_GetTick>
8008958: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800895a: e008 b.n 800896e <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800895c: f7fc f820 bl 80049a0 <HAL_GetTick>
8008960: 4602 mov r2, r0
8008962: 693b ldr r3, [r7, #16]
8008964: 1ad3 subs r3, r2, r3
8008966: 2b64 cmp r3, #100 ; 0x64
8008968: d901 bls.n 800896e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800896a: 2303 movs r3, #3
800896c: e21f b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800896e: 4b61 ldr r3, [pc, #388] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008970: 681b ldr r3, [r3, #0]
8008972: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008976: 2b00 cmp r3, #0
8008978: d0f0 beq.n 800895c <HAL_RCC_OscConfig+0xe8>
800897a: e014 b.n 80089a6 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800897c: f7fc f810 bl 80049a0 <HAL_GetTick>
8008980: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8008982: e008 b.n 8008996 <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8008984: f7fc f80c bl 80049a0 <HAL_GetTick>
8008988: 4602 mov r2, r0
800898a: 693b ldr r3, [r7, #16]
800898c: 1ad3 subs r3, r2, r3
800898e: 2b64 cmp r3, #100 ; 0x64
8008990: d901 bls.n 8008996 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
8008992: 2303 movs r3, #3
8008994: e20b b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8008996: 4b57 ldr r3, [pc, #348] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008998: 681b ldr r3, [r3, #0]
800899a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800899e: 2b00 cmp r3, #0
80089a0: d1f0 bne.n 8008984 <HAL_RCC_OscConfig+0x110>
80089a2: e000 b.n 80089a6 <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80089a4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80089a6: 687b ldr r3, [r7, #4]
80089a8: 681b ldr r3, [r3, #0]
80089aa: f003 0302 and.w r3, r3, #2
80089ae: 2b00 cmp r3, #0
80089b0: d069 beq.n 8008a86 <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
80089b2: 4b50 ldr r3, [pc, #320] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089b4: 689b ldr r3, [r3, #8]
80089b6: f003 030c and.w r3, r3, #12
80089ba: 2b00 cmp r3, #0
80089bc: d00b beq.n 80089d6 <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80089be: 4b4d ldr r3, [pc, #308] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089c0: 689b ldr r3, [r3, #8]
80089c2: f003 030c and.w r3, r3, #12
80089c6: 2b08 cmp r3, #8
80089c8: d11c bne.n 8008a04 <HAL_RCC_OscConfig+0x190>
80089ca: 4b4a ldr r3, [pc, #296] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089cc: 685b ldr r3, [r3, #4]
80089ce: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80089d2: 2b00 cmp r3, #0
80089d4: d116 bne.n 8008a04 <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80089d6: 4b47 ldr r3, [pc, #284] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089d8: 681b ldr r3, [r3, #0]
80089da: f003 0302 and.w r3, r3, #2
80089de: 2b00 cmp r3, #0
80089e0: d005 beq.n 80089ee <HAL_RCC_OscConfig+0x17a>
80089e2: 687b ldr r3, [r7, #4]
80089e4: 68db ldr r3, [r3, #12]
80089e6: 2b01 cmp r3, #1
80089e8: d001 beq.n 80089ee <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
80089ea: 2301 movs r3, #1
80089ec: e1df b.n 8008dae <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80089ee: 4b41 ldr r3, [pc, #260] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089f0: 681b ldr r3, [r3, #0]
80089f2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80089f6: 687b ldr r3, [r7, #4]
80089f8: 691b ldr r3, [r3, #16]
80089fa: 00db lsls r3, r3, #3
80089fc: 493d ldr r1, [pc, #244] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
80089fe: 4313 orrs r3, r2
8008a00: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8008a02: e040 b.n 8008a86 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8008a04: 687b ldr r3, [r7, #4]
8008a06: 68db ldr r3, [r3, #12]
8008a08: 2b00 cmp r3, #0
8008a0a: d023 beq.n 8008a54 <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8008a0c: 4b39 ldr r3, [pc, #228] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a0e: 681b ldr r3, [r3, #0]
8008a10: 4a38 ldr r2, [pc, #224] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a12: f043 0301 orr.w r3, r3, #1
8008a16: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a18: f7fb ffc2 bl 80049a0 <HAL_GetTick>
8008a1c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008a1e: e008 b.n 8008a32 <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008a20: f7fb ffbe bl 80049a0 <HAL_GetTick>
8008a24: 4602 mov r2, r0
8008a26: 693b ldr r3, [r7, #16]
8008a28: 1ad3 subs r3, r2, r3
8008a2a: 2b02 cmp r3, #2
8008a2c: d901 bls.n 8008a32 <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8008a2e: 2303 movs r3, #3
8008a30: e1bd b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008a32: 4b30 ldr r3, [pc, #192] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a34: 681b ldr r3, [r3, #0]
8008a36: f003 0302 and.w r3, r3, #2
8008a3a: 2b00 cmp r3, #0
8008a3c: d0f0 beq.n 8008a20 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8008a3e: 4b2d ldr r3, [pc, #180] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a40: 681b ldr r3, [r3, #0]
8008a42: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8008a46: 687b ldr r3, [r7, #4]
8008a48: 691b ldr r3, [r3, #16]
8008a4a: 00db lsls r3, r3, #3
8008a4c: 4929 ldr r1, [pc, #164] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a4e: 4313 orrs r3, r2
8008a50: 600b str r3, [r1, #0]
8008a52: e018 b.n 8008a86 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8008a54: 4b27 ldr r3, [pc, #156] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a56: 681b ldr r3, [r3, #0]
8008a58: 4a26 ldr r2, [pc, #152] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a5a: f023 0301 bic.w r3, r3, #1
8008a5e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008a60: f7fb ff9e bl 80049a0 <HAL_GetTick>
8008a64: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8008a66: e008 b.n 8008a7a <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8008a68: f7fb ff9a bl 80049a0 <HAL_GetTick>
8008a6c: 4602 mov r2, r0
8008a6e: 693b ldr r3, [r7, #16]
8008a70: 1ad3 subs r3, r2, r3
8008a72: 2b02 cmp r3, #2
8008a74: d901 bls.n 8008a7a <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8008a76: 2303 movs r3, #3
8008a78: e199 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8008a7a: 4b1e ldr r3, [pc, #120] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a7c: 681b ldr r3, [r3, #0]
8008a7e: f003 0302 and.w r3, r3, #2
8008a82: 2b00 cmp r3, #0
8008a84: d1f0 bne.n 8008a68 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8008a86: 687b ldr r3, [r7, #4]
8008a88: 681b ldr r3, [r3, #0]
8008a8a: f003 0308 and.w r3, r3, #8
8008a8e: 2b00 cmp r3, #0
8008a90: d038 beq.n 8008b04 <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
8008a92: 687b ldr r3, [r7, #4]
8008a94: 695b ldr r3, [r3, #20]
8008a96: 2b00 cmp r3, #0
8008a98: d019 beq.n 8008ace <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8008a9a: 4b16 ldr r3, [pc, #88] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008a9c: 6f5b ldr r3, [r3, #116] ; 0x74
8008a9e: 4a15 ldr r2, [pc, #84] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008aa0: f043 0301 orr.w r3, r3, #1
8008aa4: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008aa6: f7fb ff7b bl 80049a0 <HAL_GetTick>
8008aaa: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8008aac: e008 b.n 8008ac0 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8008aae: f7fb ff77 bl 80049a0 <HAL_GetTick>
8008ab2: 4602 mov r2, r0
8008ab4: 693b ldr r3, [r7, #16]
8008ab6: 1ad3 subs r3, r2, r3
8008ab8: 2b02 cmp r3, #2
8008aba: d901 bls.n 8008ac0 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8008abc: 2303 movs r3, #3
8008abe: e176 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8008ac0: 4b0c ldr r3, [pc, #48] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008ac2: 6f5b ldr r3, [r3, #116] ; 0x74
8008ac4: f003 0302 and.w r3, r3, #2
8008ac8: 2b00 cmp r3, #0
8008aca: d0f0 beq.n 8008aae <HAL_RCC_OscConfig+0x23a>
8008acc: e01a b.n 8008b04 <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8008ace: 4b09 ldr r3, [pc, #36] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008ad0: 6f5b ldr r3, [r3, #116] ; 0x74
8008ad2: 4a08 ldr r2, [pc, #32] ; (8008af4 <HAL_RCC_OscConfig+0x280>)
8008ad4: f023 0301 bic.w r3, r3, #1
8008ad8: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008ada: f7fb ff61 bl 80049a0 <HAL_GetTick>
8008ade: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008ae0: e00a b.n 8008af8 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8008ae2: f7fb ff5d bl 80049a0 <HAL_GetTick>
8008ae6: 4602 mov r2, r0
8008ae8: 693b ldr r3, [r7, #16]
8008aea: 1ad3 subs r3, r2, r3
8008aec: 2b02 cmp r3, #2
8008aee: d903 bls.n 8008af8 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8008af0: 2303 movs r3, #3
8008af2: e15c b.n 8008dae <HAL_RCC_OscConfig+0x53a>
8008af4: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8008af8: 4b91 ldr r3, [pc, #580] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008afa: 6f5b ldr r3, [r3, #116] ; 0x74
8008afc: f003 0302 and.w r3, r3, #2
8008b00: 2b00 cmp r3, #0
8008b02: d1ee bne.n 8008ae2 <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8008b04: 687b ldr r3, [r7, #4]
8008b06: 681b ldr r3, [r3, #0]
8008b08: f003 0304 and.w r3, r3, #4
8008b0c: 2b00 cmp r3, #0
8008b0e: f000 80a4 beq.w 8008c5a <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8008b12: 4b8b ldr r3, [pc, #556] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b14: 6c1b ldr r3, [r3, #64] ; 0x40
8008b16: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008b1a: 2b00 cmp r3, #0
8008b1c: d10d bne.n 8008b3a <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8008b1e: 4b88 ldr r3, [pc, #544] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b20: 6c1b ldr r3, [r3, #64] ; 0x40
8008b22: 4a87 ldr r2, [pc, #540] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b24: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8008b28: 6413 str r3, [r2, #64] ; 0x40
8008b2a: 4b85 ldr r3, [pc, #532] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b2c: 6c1b ldr r3, [r3, #64] ; 0x40
8008b2e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8008b32: 60bb str r3, [r7, #8]
8008b34: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8008b36: 2301 movs r3, #1
8008b38: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b3a: 4b82 ldr r3, [pc, #520] ; (8008d44 <HAL_RCC_OscConfig+0x4d0>)
8008b3c: 681b ldr r3, [r3, #0]
8008b3e: f403 7380 and.w r3, r3, #256 ; 0x100
8008b42: 2b00 cmp r3, #0
8008b44: d118 bne.n 8008b78 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8008b46: 4b7f ldr r3, [pc, #508] ; (8008d44 <HAL_RCC_OscConfig+0x4d0>)
8008b48: 681b ldr r3, [r3, #0]
8008b4a: 4a7e ldr r2, [pc, #504] ; (8008d44 <HAL_RCC_OscConfig+0x4d0>)
8008b4c: f443 7380 orr.w r3, r3, #256 ; 0x100
8008b50: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8008b52: f7fb ff25 bl 80049a0 <HAL_GetTick>
8008b56: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b58: e008 b.n 8008b6c <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8008b5a: f7fb ff21 bl 80049a0 <HAL_GetTick>
8008b5e: 4602 mov r2, r0
8008b60: 693b ldr r3, [r7, #16]
8008b62: 1ad3 subs r3, r2, r3
8008b64: 2b64 cmp r3, #100 ; 0x64
8008b66: d901 bls.n 8008b6c <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
8008b68: 2303 movs r3, #3
8008b6a: e120 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8008b6c: 4b75 ldr r3, [pc, #468] ; (8008d44 <HAL_RCC_OscConfig+0x4d0>)
8008b6e: 681b ldr r3, [r3, #0]
8008b70: f403 7380 and.w r3, r3, #256 ; 0x100
8008b74: 2b00 cmp r3, #0
8008b76: d0f0 beq.n 8008b5a <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8008b78: 687b ldr r3, [r7, #4]
8008b7a: 689b ldr r3, [r3, #8]
8008b7c: 2b01 cmp r3, #1
8008b7e: d106 bne.n 8008b8e <HAL_RCC_OscConfig+0x31a>
8008b80: 4b6f ldr r3, [pc, #444] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b82: 6f1b ldr r3, [r3, #112] ; 0x70
8008b84: 4a6e ldr r2, [pc, #440] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b86: f043 0301 orr.w r3, r3, #1
8008b8a: 6713 str r3, [r2, #112] ; 0x70
8008b8c: e02d b.n 8008bea <HAL_RCC_OscConfig+0x376>
8008b8e: 687b ldr r3, [r7, #4]
8008b90: 689b ldr r3, [r3, #8]
8008b92: 2b00 cmp r3, #0
8008b94: d10c bne.n 8008bb0 <HAL_RCC_OscConfig+0x33c>
8008b96: 4b6a ldr r3, [pc, #424] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b98: 6f1b ldr r3, [r3, #112] ; 0x70
8008b9a: 4a69 ldr r2, [pc, #420] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008b9c: f023 0301 bic.w r3, r3, #1
8008ba0: 6713 str r3, [r2, #112] ; 0x70
8008ba2: 4b67 ldr r3, [pc, #412] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008ba4: 6f1b ldr r3, [r3, #112] ; 0x70
8008ba6: 4a66 ldr r2, [pc, #408] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008ba8: f023 0304 bic.w r3, r3, #4
8008bac: 6713 str r3, [r2, #112] ; 0x70
8008bae: e01c b.n 8008bea <HAL_RCC_OscConfig+0x376>
8008bb0: 687b ldr r3, [r7, #4]
8008bb2: 689b ldr r3, [r3, #8]
8008bb4: 2b05 cmp r3, #5
8008bb6: d10c bne.n 8008bd2 <HAL_RCC_OscConfig+0x35e>
8008bb8: 4b61 ldr r3, [pc, #388] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bba: 6f1b ldr r3, [r3, #112] ; 0x70
8008bbc: 4a60 ldr r2, [pc, #384] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bbe: f043 0304 orr.w r3, r3, #4
8008bc2: 6713 str r3, [r2, #112] ; 0x70
8008bc4: 4b5e ldr r3, [pc, #376] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bc6: 6f1b ldr r3, [r3, #112] ; 0x70
8008bc8: 4a5d ldr r2, [pc, #372] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bca: f043 0301 orr.w r3, r3, #1
8008bce: 6713 str r3, [r2, #112] ; 0x70
8008bd0: e00b b.n 8008bea <HAL_RCC_OscConfig+0x376>
8008bd2: 4b5b ldr r3, [pc, #364] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bd4: 6f1b ldr r3, [r3, #112] ; 0x70
8008bd6: 4a5a ldr r2, [pc, #360] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008bd8: f023 0301 bic.w r3, r3, #1
8008bdc: 6713 str r3, [r2, #112] ; 0x70
8008bde: 4b58 ldr r3, [pc, #352] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008be0: 6f1b ldr r3, [r3, #112] ; 0x70
8008be2: 4a57 ldr r2, [pc, #348] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008be4: f023 0304 bic.w r3, r3, #4
8008be8: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8008bea: 687b ldr r3, [r7, #4]
8008bec: 689b ldr r3, [r3, #8]
8008bee: 2b00 cmp r3, #0
8008bf0: d015 beq.n 8008c1e <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008bf2: f7fb fed5 bl 80049a0 <HAL_GetTick>
8008bf6: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008bf8: e00a b.n 8008c10 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008bfa: f7fb fed1 bl 80049a0 <HAL_GetTick>
8008bfe: 4602 mov r2, r0
8008c00: 693b ldr r3, [r7, #16]
8008c02: 1ad3 subs r3, r2, r3
8008c04: f241 3288 movw r2, #5000 ; 0x1388
8008c08: 4293 cmp r3, r2
8008c0a: d901 bls.n 8008c10 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8008c0c: 2303 movs r3, #3
8008c0e: e0ce b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8008c10: 4b4b ldr r3, [pc, #300] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c12: 6f1b ldr r3, [r3, #112] ; 0x70
8008c14: f003 0302 and.w r3, r3, #2
8008c18: 2b00 cmp r3, #0
8008c1a: d0ee beq.n 8008bfa <HAL_RCC_OscConfig+0x386>
8008c1c: e014 b.n 8008c48 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008c1e: f7fb febf bl 80049a0 <HAL_GetTick>
8008c22: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008c24: e00a b.n 8008c3c <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8008c26: f7fb febb bl 80049a0 <HAL_GetTick>
8008c2a: 4602 mov r2, r0
8008c2c: 693b ldr r3, [r7, #16]
8008c2e: 1ad3 subs r3, r2, r3
8008c30: f241 3288 movw r2, #5000 ; 0x1388
8008c34: 4293 cmp r3, r2
8008c36: d901 bls.n 8008c3c <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8008c38: 2303 movs r3, #3
8008c3a: e0b8 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8008c3c: 4b40 ldr r3, [pc, #256] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c3e: 6f1b ldr r3, [r3, #112] ; 0x70
8008c40: f003 0302 and.w r3, r3, #2
8008c44: 2b00 cmp r3, #0
8008c46: d1ee bne.n 8008c26 <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8008c48: 7dfb ldrb r3, [r7, #23]
8008c4a: 2b01 cmp r3, #1
8008c4c: d105 bne.n 8008c5a <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
8008c4e: 4b3c ldr r3, [pc, #240] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c50: 6c1b ldr r3, [r3, #64] ; 0x40
8008c52: 4a3b ldr r2, [pc, #236] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c54: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8008c58: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8008c5a: 687b ldr r3, [r7, #4]
8008c5c: 699b ldr r3, [r3, #24]
8008c5e: 2b00 cmp r3, #0
8008c60: f000 80a4 beq.w 8008dac <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8008c64: 4b36 ldr r3, [pc, #216] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c66: 689b ldr r3, [r3, #8]
8008c68: f003 030c and.w r3, r3, #12
8008c6c: 2b08 cmp r3, #8
8008c6e: d06b beq.n 8008d48 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8008c70: 687b ldr r3, [r7, #4]
8008c72: 699b ldr r3, [r3, #24]
8008c74: 2b02 cmp r3, #2
8008c76: d149 bne.n 8008d0c <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008c78: 4b31 ldr r3, [pc, #196] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c7a: 681b ldr r3, [r3, #0]
8008c7c: 4a30 ldr r2, [pc, #192] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008c7e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008c82: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008c84: f7fb fe8c bl 80049a0 <HAL_GetTick>
8008c88: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008c8a: e008 b.n 8008c9e <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008c8c: f7fb fe88 bl 80049a0 <HAL_GetTick>
8008c90: 4602 mov r2, r0
8008c92: 693b ldr r3, [r7, #16]
8008c94: 1ad3 subs r3, r2, r3
8008c96: 2b02 cmp r3, #2
8008c98: d901 bls.n 8008c9e <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8008c9a: 2303 movs r3, #3
8008c9c: e087 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008c9e: 4b28 ldr r3, [pc, #160] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008ca0: 681b ldr r3, [r3, #0]
8008ca2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008ca6: 2b00 cmp r3, #0
8008ca8: d1f0 bne.n 8008c8c <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8008caa: 687b ldr r3, [r7, #4]
8008cac: 69da ldr r2, [r3, #28]
8008cae: 687b ldr r3, [r7, #4]
8008cb0: 6a1b ldr r3, [r3, #32]
8008cb2: 431a orrs r2, r3
8008cb4: 687b ldr r3, [r7, #4]
8008cb6: 6a5b ldr r3, [r3, #36] ; 0x24
8008cb8: 019b lsls r3, r3, #6
8008cba: 431a orrs r2, r3
8008cbc: 687b ldr r3, [r7, #4]
8008cbe: 6a9b ldr r3, [r3, #40] ; 0x28
8008cc0: 085b lsrs r3, r3, #1
8008cc2: 3b01 subs r3, #1
8008cc4: 041b lsls r3, r3, #16
8008cc6: 431a orrs r2, r3
8008cc8: 687b ldr r3, [r7, #4]
8008cca: 6adb ldr r3, [r3, #44] ; 0x2c
8008ccc: 061b lsls r3, r3, #24
8008cce: 4313 orrs r3, r2
8008cd0: 4a1b ldr r2, [pc, #108] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008cd2: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
8008cd6: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8008cd8: 4b19 ldr r3, [pc, #100] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008cda: 681b ldr r3, [r3, #0]
8008cdc: 4a18 ldr r2, [pc, #96] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008cde: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8008ce2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008ce4: f7fb fe5c bl 80049a0 <HAL_GetTick>
8008ce8: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008cea: e008 b.n 8008cfe <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008cec: f7fb fe58 bl 80049a0 <HAL_GetTick>
8008cf0: 4602 mov r2, r0
8008cf2: 693b ldr r3, [r7, #16]
8008cf4: 1ad3 subs r3, r2, r3
8008cf6: 2b02 cmp r3, #2
8008cf8: d901 bls.n 8008cfe <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8008cfa: 2303 movs r3, #3
8008cfc: e057 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008cfe: 4b10 ldr r3, [pc, #64] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008d00: 681b ldr r3, [r3, #0]
8008d02: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008d06: 2b00 cmp r3, #0
8008d08: d0f0 beq.n 8008cec <HAL_RCC_OscConfig+0x478>
8008d0a: e04f b.n 8008dac <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8008d0c: 4b0c ldr r3, [pc, #48] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008d0e: 681b ldr r3, [r3, #0]
8008d10: 4a0b ldr r2, [pc, #44] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008d12: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8008d16: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008d18: f7fb fe42 bl 80049a0 <HAL_GetTick>
8008d1c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008d1e: e008 b.n 8008d32 <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8008d20: f7fb fe3e bl 80049a0 <HAL_GetTick>
8008d24: 4602 mov r2, r0
8008d26: 693b ldr r3, [r7, #16]
8008d28: 1ad3 subs r3, r2, r3
8008d2a: 2b02 cmp r3, #2
8008d2c: d901 bls.n 8008d32 <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8008d2e: 2303 movs r3, #3
8008d30: e03d b.n 8008dae <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8008d32: 4b03 ldr r3, [pc, #12] ; (8008d40 <HAL_RCC_OscConfig+0x4cc>)
8008d34: 681b ldr r3, [r3, #0]
8008d36: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008d3a: 2b00 cmp r3, #0
8008d3c: d1f0 bne.n 8008d20 <HAL_RCC_OscConfig+0x4ac>
8008d3e: e035 b.n 8008dac <HAL_RCC_OscConfig+0x538>
8008d40: 40023800 .word 0x40023800
8008d44: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8008d48: 4b1b ldr r3, [pc, #108] ; (8008db8 <HAL_RCC_OscConfig+0x544>)
8008d4a: 685b ldr r3, [r3, #4]
8008d4c: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008d4e: 687b ldr r3, [r7, #4]
8008d50: 699b ldr r3, [r3, #24]
8008d52: 2b01 cmp r3, #1
8008d54: d028 beq.n 8008da8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008d56: 68fb ldr r3, [r7, #12]
8008d58: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8008d5c: 687b ldr r3, [r7, #4]
8008d5e: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8008d60: 429a cmp r2, r3
8008d62: d121 bne.n 8008da8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008d64: 68fb ldr r3, [r7, #12]
8008d66: f003 023f and.w r2, r3, #63 ; 0x3f
8008d6a: 687b ldr r3, [r7, #4]
8008d6c: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8008d6e: 429a cmp r2, r3
8008d70: d11a bne.n 8008da8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008d72: 68fa ldr r2, [r7, #12]
8008d74: f647 73c0 movw r3, #32704 ; 0x7fc0
8008d78: 4013 ands r3, r2
8008d7a: 687a ldr r2, [r7, #4]
8008d7c: 6a52 ldr r2, [r2, #36] ; 0x24
8008d7e: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8008d80: 4293 cmp r3, r2
8008d82: d111 bne.n 8008da8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008d84: 68fb ldr r3, [r7, #12]
8008d86: f403 3240 and.w r2, r3, #196608 ; 0x30000
8008d8a: 687b ldr r3, [r7, #4]
8008d8c: 6a9b ldr r3, [r3, #40] ; 0x28
8008d8e: 085b lsrs r3, r3, #1
8008d90: 3b01 subs r3, #1
8008d92: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
8008d94: 429a cmp r2, r3
8008d96: d107 bne.n 8008da8 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8008d98: 68fb ldr r3, [r7, #12]
8008d9a: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8008d9e: 687b ldr r3, [r7, #4]
8008da0: 6adb ldr r3, [r3, #44] ; 0x2c
8008da2: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
8008da4: 429a cmp r2, r3
8008da6: d001 beq.n 8008dac <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8008da8: 2301 movs r3, #1
8008daa: e000 b.n 8008dae <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8008dac: 2300 movs r3, #0
}
8008dae: 4618 mov r0, r3
8008db0: 3718 adds r7, #24
8008db2: 46bd mov sp, r7
8008db4: bd80 pop {r7, pc}
8008db6: bf00 nop
8008db8: 40023800 .word 0x40023800
08008dbc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8008dbc: b580 push {r7, lr}
8008dbe: b084 sub sp, #16
8008dc0: af00 add r7, sp, #0
8008dc2: 6078 str r0, [r7, #4]
8008dc4: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
8008dc6: 2300 movs r3, #0
8008dc8: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8008dca: 687b ldr r3, [r7, #4]
8008dcc: 2b00 cmp r3, #0
8008dce: d101 bne.n 8008dd4 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8008dd0: 2301 movs r3, #1
8008dd2: e0d0 b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8008dd4: 4b6a ldr r3, [pc, #424] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008dd6: 681b ldr r3, [r3, #0]
8008dd8: f003 030f and.w r3, r3, #15
8008ddc: 683a ldr r2, [r7, #0]
8008dde: 429a cmp r2, r3
8008de0: d910 bls.n 8008e04 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008de2: 4b67 ldr r3, [pc, #412] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008de4: 681b ldr r3, [r3, #0]
8008de6: f023 020f bic.w r2, r3, #15
8008dea: 4965 ldr r1, [pc, #404] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008dec: 683b ldr r3, [r7, #0]
8008dee: 4313 orrs r3, r2
8008df0: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008df2: 4b63 ldr r3, [pc, #396] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008df4: 681b ldr r3, [r3, #0]
8008df6: f003 030f and.w r3, r3, #15
8008dfa: 683a ldr r2, [r7, #0]
8008dfc: 429a cmp r2, r3
8008dfe: d001 beq.n 8008e04 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8008e00: 2301 movs r3, #1
8008e02: e0b8 b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8008e04: 687b ldr r3, [r7, #4]
8008e06: 681b ldr r3, [r3, #0]
8008e08: f003 0302 and.w r3, r3, #2
8008e0c: 2b00 cmp r3, #0
8008e0e: d020 beq.n 8008e52 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008e10: 687b ldr r3, [r7, #4]
8008e12: 681b ldr r3, [r3, #0]
8008e14: f003 0304 and.w r3, r3, #4
8008e18: 2b00 cmp r3, #0
8008e1a: d005 beq.n 8008e28 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8008e1c: 4b59 ldr r3, [pc, #356] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e1e: 689b ldr r3, [r3, #8]
8008e20: 4a58 ldr r2, [pc, #352] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e22: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8008e26: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008e28: 687b ldr r3, [r7, #4]
8008e2a: 681b ldr r3, [r3, #0]
8008e2c: f003 0308 and.w r3, r3, #8
8008e30: 2b00 cmp r3, #0
8008e32: d005 beq.n 8008e40 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8008e34: 4b53 ldr r3, [pc, #332] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e36: 689b ldr r3, [r3, #8]
8008e38: 4a52 ldr r2, [pc, #328] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e3a: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8008e3e: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8008e40: 4b50 ldr r3, [pc, #320] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e42: 689b ldr r3, [r3, #8]
8008e44: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8008e48: 687b ldr r3, [r7, #4]
8008e4a: 689b ldr r3, [r3, #8]
8008e4c: 494d ldr r1, [pc, #308] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e4e: 4313 orrs r3, r2
8008e50: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8008e52: 687b ldr r3, [r7, #4]
8008e54: 681b ldr r3, [r3, #0]
8008e56: f003 0301 and.w r3, r3, #1
8008e5a: 2b00 cmp r3, #0
8008e5c: d040 beq.n 8008ee0 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8008e5e: 687b ldr r3, [r7, #4]
8008e60: 685b ldr r3, [r3, #4]
8008e62: 2b01 cmp r3, #1
8008e64: d107 bne.n 8008e76 <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8008e66: 4b47 ldr r3, [pc, #284] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e68: 681b ldr r3, [r3, #0]
8008e6a: f403 3300 and.w r3, r3, #131072 ; 0x20000
8008e6e: 2b00 cmp r3, #0
8008e70: d115 bne.n 8008e9e <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e72: 2301 movs r3, #1
8008e74: e07f b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8008e76: 687b ldr r3, [r7, #4]
8008e78: 685b ldr r3, [r3, #4]
8008e7a: 2b02 cmp r3, #2
8008e7c: d107 bne.n 8008e8e <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8008e7e: 4b41 ldr r3, [pc, #260] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e80: 681b ldr r3, [r3, #0]
8008e82: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8008e86: 2b00 cmp r3, #0
8008e88: d109 bne.n 8008e9e <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e8a: 2301 movs r3, #1
8008e8c: e073 b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8008e8e: 4b3d ldr r3, [pc, #244] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008e90: 681b ldr r3, [r3, #0]
8008e92: f003 0302 and.w r3, r3, #2
8008e96: 2b00 cmp r3, #0
8008e98: d101 bne.n 8008e9e <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
8008e9a: 2301 movs r3, #1
8008e9c: e06b b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8008e9e: 4b39 ldr r3, [pc, #228] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008ea0: 689b ldr r3, [r3, #8]
8008ea2: f023 0203 bic.w r2, r3, #3
8008ea6: 687b ldr r3, [r7, #4]
8008ea8: 685b ldr r3, [r3, #4]
8008eaa: 4936 ldr r1, [pc, #216] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008eac: 4313 orrs r3, r2
8008eae: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008eb0: f7fb fd76 bl 80049a0 <HAL_GetTick>
8008eb4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008eb6: e00a b.n 8008ece <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8008eb8: f7fb fd72 bl 80049a0 <HAL_GetTick>
8008ebc: 4602 mov r2, r0
8008ebe: 68fb ldr r3, [r7, #12]
8008ec0: 1ad3 subs r3, r2, r3
8008ec2: f241 3288 movw r2, #5000 ; 0x1388
8008ec6: 4293 cmp r3, r2
8008ec8: d901 bls.n 8008ece <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8008eca: 2303 movs r3, #3
8008ecc: e053 b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8008ece: 4b2d ldr r3, [pc, #180] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008ed0: 689b ldr r3, [r3, #8]
8008ed2: f003 020c and.w r2, r3, #12
8008ed6: 687b ldr r3, [r7, #4]
8008ed8: 685b ldr r3, [r3, #4]
8008eda: 009b lsls r3, r3, #2
8008edc: 429a cmp r2, r3
8008ede: d1eb bne.n 8008eb8 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8008ee0: 4b27 ldr r3, [pc, #156] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008ee2: 681b ldr r3, [r3, #0]
8008ee4: f003 030f and.w r3, r3, #15
8008ee8: 683a ldr r2, [r7, #0]
8008eea: 429a cmp r2, r3
8008eec: d210 bcs.n 8008f10 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8008eee: 4b24 ldr r3, [pc, #144] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008ef0: 681b ldr r3, [r3, #0]
8008ef2: f023 020f bic.w r2, r3, #15
8008ef6: 4922 ldr r1, [pc, #136] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008ef8: 683b ldr r3, [r7, #0]
8008efa: 4313 orrs r3, r2
8008efc: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8008efe: 4b20 ldr r3, [pc, #128] ; (8008f80 <HAL_RCC_ClockConfig+0x1c4>)
8008f00: 681b ldr r3, [r3, #0]
8008f02: f003 030f and.w r3, r3, #15
8008f06: 683a ldr r2, [r7, #0]
8008f08: 429a cmp r2, r3
8008f0a: d001 beq.n 8008f10 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8008f0c: 2301 movs r3, #1
8008f0e: e032 b.n 8008f76 <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8008f10: 687b ldr r3, [r7, #4]
8008f12: 681b ldr r3, [r3, #0]
8008f14: f003 0304 and.w r3, r3, #4
8008f18: 2b00 cmp r3, #0
8008f1a: d008 beq.n 8008f2e <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8008f1c: 4b19 ldr r3, [pc, #100] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008f1e: 689b ldr r3, [r3, #8]
8008f20: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8008f24: 687b ldr r3, [r7, #4]
8008f26: 68db ldr r3, [r3, #12]
8008f28: 4916 ldr r1, [pc, #88] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008f2a: 4313 orrs r3, r2
8008f2c: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8008f2e: 687b ldr r3, [r7, #4]
8008f30: 681b ldr r3, [r3, #0]
8008f32: f003 0308 and.w r3, r3, #8
8008f36: 2b00 cmp r3, #0
8008f38: d009 beq.n 8008f4e <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8008f3a: 4b12 ldr r3, [pc, #72] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008f3c: 689b ldr r3, [r3, #8]
8008f3e: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8008f42: 687b ldr r3, [r7, #4]
8008f44: 691b ldr r3, [r3, #16]
8008f46: 00db lsls r3, r3, #3
8008f48: 490e ldr r1, [pc, #56] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008f4a: 4313 orrs r3, r2
8008f4c: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8008f4e: f000 f821 bl 8008f94 <HAL_RCC_GetSysClockFreq>
8008f52: 4601 mov r1, r0
8008f54: 4b0b ldr r3, [pc, #44] ; (8008f84 <HAL_RCC_ClockConfig+0x1c8>)
8008f56: 689b ldr r3, [r3, #8]
8008f58: 091b lsrs r3, r3, #4
8008f5a: f003 030f and.w r3, r3, #15
8008f5e: 4a0a ldr r2, [pc, #40] ; (8008f88 <HAL_RCC_ClockConfig+0x1cc>)
8008f60: 5cd3 ldrb r3, [r2, r3]
8008f62: fa21 f303 lsr.w r3, r1, r3
8008f66: 4a09 ldr r2, [pc, #36] ; (8008f8c <HAL_RCC_ClockConfig+0x1d0>)
8008f68: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
8008f6a: 4b09 ldr r3, [pc, #36] ; (8008f90 <HAL_RCC_ClockConfig+0x1d4>)
8008f6c: 681b ldr r3, [r3, #0]
8008f6e: 4618 mov r0, r3
8008f70: f7fb fb78 bl 8004664 <HAL_InitTick>
return HAL_OK;
8008f74: 2300 movs r3, #0
}
8008f76: 4618 mov r0, r3
8008f78: 3710 adds r7, #16
8008f7a: 46bd mov sp, r7
8008f7c: bd80 pop {r7, pc}
8008f7e: bf00 nop
8008f80: 40023c00 .word 0x40023c00
8008f84: 40023800 .word 0x40023800
8008f88: 08020d38 .word 0x08020d38
8008f8c: 20000064 .word 0x20000064
8008f90: 20000068 .word 0x20000068
08008f94 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8008f94: b5f0 push {r4, r5, r6, r7, lr}
8008f96: b085 sub sp, #20
8008f98: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
8008f9a: 2300 movs r3, #0
8008f9c: 607b str r3, [r7, #4]
8008f9e: 2300 movs r3, #0
8008fa0: 60fb str r3, [r7, #12]
8008fa2: 2300 movs r3, #0
8008fa4: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
8008fa6: 2300 movs r3, #0
8008fa8: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8008faa: 4b50 ldr r3, [pc, #320] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
8008fac: 689b ldr r3, [r3, #8]
8008fae: f003 030c and.w r3, r3, #12
8008fb2: 2b04 cmp r3, #4
8008fb4: d007 beq.n 8008fc6 <HAL_RCC_GetSysClockFreq+0x32>
8008fb6: 2b08 cmp r3, #8
8008fb8: d008 beq.n 8008fcc <HAL_RCC_GetSysClockFreq+0x38>
8008fba: 2b00 cmp r3, #0
8008fbc: f040 808d bne.w 80090da <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8008fc0: 4b4b ldr r3, [pc, #300] ; (80090f0 <HAL_RCC_GetSysClockFreq+0x15c>)
8008fc2: 60bb str r3, [r7, #8]
break;
8008fc4: e08c b.n 80090e0 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8008fc6: 4b4b ldr r3, [pc, #300] ; (80090f4 <HAL_RCC_GetSysClockFreq+0x160>)
8008fc8: 60bb str r3, [r7, #8]
break;
8008fca: e089 b.n 80090e0 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8008fcc: 4b47 ldr r3, [pc, #284] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
8008fce: 685b ldr r3, [r3, #4]
8008fd0: f003 033f and.w r3, r3, #63 ; 0x3f
8008fd4: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
8008fd6: 4b45 ldr r3, [pc, #276] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
8008fd8: 685b ldr r3, [r3, #4]
8008fda: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8008fde: 2b00 cmp r3, #0
8008fe0: d023 beq.n 800902a <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8008fe2: 4b42 ldr r3, [pc, #264] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
8008fe4: 685b ldr r3, [r3, #4]
8008fe6: 099b lsrs r3, r3, #6
8008fe8: f04f 0400 mov.w r4, #0
8008fec: f240 11ff movw r1, #511 ; 0x1ff
8008ff0: f04f 0200 mov.w r2, #0
8008ff4: ea03 0501 and.w r5, r3, r1
8008ff8: ea04 0602 and.w r6, r4, r2
8008ffc: 4a3d ldr r2, [pc, #244] ; (80090f4 <HAL_RCC_GetSysClockFreq+0x160>)
8008ffe: fb02 f106 mul.w r1, r2, r6
8009002: 2200 movs r2, #0
8009004: fb02 f205 mul.w r2, r2, r5
8009008: 440a add r2, r1
800900a: 493a ldr r1, [pc, #232] ; (80090f4 <HAL_RCC_GetSysClockFreq+0x160>)
800900c: fba5 0101 umull r0, r1, r5, r1
8009010: 1853 adds r3, r2, r1
8009012: 4619 mov r1, r3
8009014: 687b ldr r3, [r7, #4]
8009016: f04f 0400 mov.w r4, #0
800901a: 461a mov r2, r3
800901c: 4623 mov r3, r4
800901e: f7f7 f947 bl 80002b0 <__aeabi_uldivmod>
8009022: 4603 mov r3, r0
8009024: 460c mov r4, r1
8009026: 60fb str r3, [r7, #12]
8009028: e049 b.n 80090be <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800902a: 4b30 ldr r3, [pc, #192] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
800902c: 685b ldr r3, [r3, #4]
800902e: 099b lsrs r3, r3, #6
8009030: f04f 0400 mov.w r4, #0
8009034: f240 11ff movw r1, #511 ; 0x1ff
8009038: f04f 0200 mov.w r2, #0
800903c: ea03 0501 and.w r5, r3, r1
8009040: ea04 0602 and.w r6, r4, r2
8009044: 4629 mov r1, r5
8009046: 4632 mov r2, r6
8009048: f04f 0300 mov.w r3, #0
800904c: f04f 0400 mov.w r4, #0
8009050: 0154 lsls r4, r2, #5
8009052: ea44 64d1 orr.w r4, r4, r1, lsr #27
8009056: 014b lsls r3, r1, #5
8009058: 4619 mov r1, r3
800905a: 4622 mov r2, r4
800905c: 1b49 subs r1, r1, r5
800905e: eb62 0206 sbc.w r2, r2, r6
8009062: f04f 0300 mov.w r3, #0
8009066: f04f 0400 mov.w r4, #0
800906a: 0194 lsls r4, r2, #6
800906c: ea44 6491 orr.w r4, r4, r1, lsr #26
8009070: 018b lsls r3, r1, #6
8009072: 1a5b subs r3, r3, r1
8009074: eb64 0402 sbc.w r4, r4, r2
8009078: f04f 0100 mov.w r1, #0
800907c: f04f 0200 mov.w r2, #0
8009080: 00e2 lsls r2, r4, #3
8009082: ea42 7253 orr.w r2, r2, r3, lsr #29
8009086: 00d9 lsls r1, r3, #3
8009088: 460b mov r3, r1
800908a: 4614 mov r4, r2
800908c: 195b adds r3, r3, r5
800908e: eb44 0406 adc.w r4, r4, r6
8009092: f04f 0100 mov.w r1, #0
8009096: f04f 0200 mov.w r2, #0
800909a: 02a2 lsls r2, r4, #10
800909c: ea42 5293 orr.w r2, r2, r3, lsr #22
80090a0: 0299 lsls r1, r3, #10
80090a2: 460b mov r3, r1
80090a4: 4614 mov r4, r2
80090a6: 4618 mov r0, r3
80090a8: 4621 mov r1, r4
80090aa: 687b ldr r3, [r7, #4]
80090ac: f04f 0400 mov.w r4, #0
80090b0: 461a mov r2, r3
80090b2: 4623 mov r3, r4
80090b4: f7f7 f8fc bl 80002b0 <__aeabi_uldivmod>
80090b8: 4603 mov r3, r0
80090ba: 460c mov r4, r1
80090bc: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
80090be: 4b0b ldr r3, [pc, #44] ; (80090ec <HAL_RCC_GetSysClockFreq+0x158>)
80090c0: 685b ldr r3, [r3, #4]
80090c2: 0c1b lsrs r3, r3, #16
80090c4: f003 0303 and.w r3, r3, #3
80090c8: 3301 adds r3, #1
80090ca: 005b lsls r3, r3, #1
80090cc: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllp;
80090ce: 68fa ldr r2, [r7, #12]
80090d0: 683b ldr r3, [r7, #0]
80090d2: fbb2 f3f3 udiv r3, r2, r3
80090d6: 60bb str r3, [r7, #8]
break;
80090d8: e002 b.n 80090e0 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
80090da: 4b05 ldr r3, [pc, #20] ; (80090f0 <HAL_RCC_GetSysClockFreq+0x15c>)
80090dc: 60bb str r3, [r7, #8]
break;
80090de: bf00 nop
}
}
return sysclockfreq;
80090e0: 68bb ldr r3, [r7, #8]
}
80090e2: 4618 mov r0, r3
80090e4: 3714 adds r7, #20
80090e6: 46bd mov sp, r7
80090e8: bdf0 pop {r4, r5, r6, r7, pc}
80090ea: bf00 nop
80090ec: 40023800 .word 0x40023800
80090f0: 00f42400 .word 0x00f42400
80090f4: 017d7840 .word 0x017d7840
080090f8 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80090f8: b480 push {r7}
80090fa: af00 add r7, sp, #0
return SystemCoreClock;
80090fc: 4b03 ldr r3, [pc, #12] ; (800910c <HAL_RCC_GetHCLKFreq+0x14>)
80090fe: 681b ldr r3, [r3, #0]
}
8009100: 4618 mov r0, r3
8009102: 46bd mov sp, r7
8009104: f85d 7b04 ldr.w r7, [sp], #4
8009108: 4770 bx lr
800910a: bf00 nop
800910c: 20000064 .word 0x20000064
08009110 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8009110: b580 push {r7, lr}
8009112: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8009114: f7ff fff0 bl 80090f8 <HAL_RCC_GetHCLKFreq>
8009118: 4601 mov r1, r0
800911a: 4b05 ldr r3, [pc, #20] ; (8009130 <HAL_RCC_GetPCLK1Freq+0x20>)
800911c: 689b ldr r3, [r3, #8]
800911e: 0a9b lsrs r3, r3, #10
8009120: f003 0307 and.w r3, r3, #7
8009124: 4a03 ldr r2, [pc, #12] ; (8009134 <HAL_RCC_GetPCLK1Freq+0x24>)
8009126: 5cd3 ldrb r3, [r2, r3]
8009128: fa21 f303 lsr.w r3, r1, r3
}
800912c: 4618 mov r0, r3
800912e: bd80 pop {r7, pc}
8009130: 40023800 .word 0x40023800
8009134: 08020d48 .word 0x08020d48
08009138 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8009138: b480 push {r7}
800913a: b083 sub sp, #12
800913c: af00 add r7, sp, #0
800913e: 6078 str r0, [r7, #4]
8009140: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8009142: 687b ldr r3, [r7, #4]
8009144: 220f movs r2, #15
8009146: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8009148: 4b12 ldr r3, [pc, #72] ; (8009194 <HAL_RCC_GetClockConfig+0x5c>)
800914a: 689b ldr r3, [r3, #8]
800914c: f003 0203 and.w r2, r3, #3
8009150: 687b ldr r3, [r7, #4]
8009152: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8009154: 4b0f ldr r3, [pc, #60] ; (8009194 <HAL_RCC_GetClockConfig+0x5c>)
8009156: 689b ldr r3, [r3, #8]
8009158: f003 02f0 and.w r2, r3, #240 ; 0xf0
800915c: 687b ldr r3, [r7, #4]
800915e: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8009160: 4b0c ldr r3, [pc, #48] ; (8009194 <HAL_RCC_GetClockConfig+0x5c>)
8009162: 689b ldr r3, [r3, #8]
8009164: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8009168: 687b ldr r3, [r7, #4]
800916a: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
800916c: 4b09 ldr r3, [pc, #36] ; (8009194 <HAL_RCC_GetClockConfig+0x5c>)
800916e: 689b ldr r3, [r3, #8]
8009170: 08db lsrs r3, r3, #3
8009172: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8009176: 687b ldr r3, [r7, #4]
8009178: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
800917a: 4b07 ldr r3, [pc, #28] ; (8009198 <HAL_RCC_GetClockConfig+0x60>)
800917c: 681b ldr r3, [r3, #0]
800917e: f003 020f and.w r2, r3, #15
8009182: 683b ldr r3, [r7, #0]
8009184: 601a str r2, [r3, #0]
}
8009186: bf00 nop
8009188: 370c adds r7, #12
800918a: 46bd mov sp, r7
800918c: f85d 7b04 ldr.w r7, [sp], #4
8009190: 4770 bx lr
8009192: bf00 nop
8009194: 40023800 .word 0x40023800
8009198: 40023c00 .word 0x40023c00
0800919c <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
800919c: b580 push {r7, lr}
800919e: b088 sub sp, #32
80091a0: af00 add r7, sp, #0
80091a2: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
80091a4: 2300 movs r3, #0
80091a6: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
80091a8: 2300 movs r3, #0
80091aa: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
80091ac: 2300 movs r3, #0
80091ae: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
80091b0: 2300 movs r3, #0
80091b2: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
80091b4: 2300 movs r3, #0
80091b6: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
80091b8: 687b ldr r3, [r7, #4]
80091ba: 681b ldr r3, [r3, #0]
80091bc: f003 0301 and.w r3, r3, #1
80091c0: 2b00 cmp r3, #0
80091c2: d012 beq.n 80091ea <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80091c4: 4b69 ldr r3, [pc, #420] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091c6: 689b ldr r3, [r3, #8]
80091c8: 4a68 ldr r2, [pc, #416] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091ca: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
80091ce: 6093 str r3, [r2, #8]
80091d0: 4b66 ldr r3, [pc, #408] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091d2: 689a ldr r2, [r3, #8]
80091d4: 687b ldr r3, [r7, #4]
80091d6: 6b5b ldr r3, [r3, #52] ; 0x34
80091d8: 4964 ldr r1, [pc, #400] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091da: 4313 orrs r3, r2
80091dc: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
80091de: 687b ldr r3, [r7, #4]
80091e0: 6b5b ldr r3, [r3, #52] ; 0x34
80091e2: 2b00 cmp r3, #0
80091e4: d101 bne.n 80091ea <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
80091e6: 2301 movs r3, #1
80091e8: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
80091ea: 687b ldr r3, [r7, #4]
80091ec: 681b ldr r3, [r3, #0]
80091ee: f403 2300 and.w r3, r3, #524288 ; 0x80000
80091f2: 2b00 cmp r3, #0
80091f4: d017 beq.n 8009226 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
80091f6: 4b5d ldr r3, [pc, #372] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80091f8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80091fc: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8009200: 687b ldr r3, [r7, #4]
8009202: 6bdb ldr r3, [r3, #60] ; 0x3c
8009204: 4959 ldr r1, [pc, #356] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009206: 4313 orrs r3, r2
8009208: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
800920c: 687b ldr r3, [r7, #4]
800920e: 6bdb ldr r3, [r3, #60] ; 0x3c
8009210: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8009214: d101 bne.n 800921a <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
8009216: 2301 movs r3, #1
8009218: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
800921a: 687b ldr r3, [r7, #4]
800921c: 6bdb ldr r3, [r3, #60] ; 0x3c
800921e: 2b00 cmp r3, #0
8009220: d101 bne.n 8009226 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
8009222: 2301 movs r3, #1
8009224: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
8009226: 687b ldr r3, [r7, #4]
8009228: 681b ldr r3, [r3, #0]
800922a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800922e: 2b00 cmp r3, #0
8009230: d017 beq.n 8009262 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8009232: 4b4e ldr r3, [pc, #312] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009234: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009238: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
800923c: 687b ldr r3, [r7, #4]
800923e: 6c1b ldr r3, [r3, #64] ; 0x40
8009240: 494a ldr r1, [pc, #296] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009242: 4313 orrs r3, r2
8009244: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
8009248: 687b ldr r3, [r7, #4]
800924a: 6c1b ldr r3, [r3, #64] ; 0x40
800924c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8009250: d101 bne.n 8009256 <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
8009252: 2301 movs r3, #1
8009254: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
8009256: 687b ldr r3, [r7, #4]
8009258: 6c1b ldr r3, [r3, #64] ; 0x40
800925a: 2b00 cmp r3, #0
800925c: d101 bne.n 8009262 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
800925e: 2301 movs r3, #1
8009260: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8009262: 687b ldr r3, [r7, #4]
8009264: 681b ldr r3, [r3, #0]
8009266: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
800926a: 2b00 cmp r3, #0
800926c: d001 beq.n 8009272 <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
800926e: 2301 movs r3, #1
8009270: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8009272: 687b ldr r3, [r7, #4]
8009274: 681b ldr r3, [r3, #0]
8009276: f003 0320 and.w r3, r3, #32
800927a: 2b00 cmp r3, #0
800927c: f000 808b beq.w 8009396 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8009280: 4b3a ldr r3, [pc, #232] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009282: 6c1b ldr r3, [r3, #64] ; 0x40
8009284: 4a39 ldr r2, [pc, #228] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009286: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800928a: 6413 str r3, [r2, #64] ; 0x40
800928c: 4b37 ldr r3, [pc, #220] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800928e: 6c1b ldr r3, [r3, #64] ; 0x40
8009290: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8009294: 60bb str r3, [r7, #8]
8009296: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8009298: 4b35 ldr r3, [pc, #212] ; (8009370 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
800929a: 681b ldr r3, [r3, #0]
800929c: 4a34 ldr r2, [pc, #208] ; (8009370 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
800929e: f443 7380 orr.w r3, r3, #256 ; 0x100
80092a2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80092a4: f7fb fb7c bl 80049a0 <HAL_GetTick>
80092a8: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80092aa: e008 b.n 80092be <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80092ac: f7fb fb78 bl 80049a0 <HAL_GetTick>
80092b0: 4602 mov r2, r0
80092b2: 697b ldr r3, [r7, #20]
80092b4: 1ad3 subs r3, r2, r3
80092b6: 2b64 cmp r3, #100 ; 0x64
80092b8: d901 bls.n 80092be <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
80092ba: 2303 movs r3, #3
80092bc: e355 b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
80092be: 4b2c ldr r3, [pc, #176] ; (8009370 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
80092c0: 681b ldr r3, [r3, #0]
80092c2: f403 7380 and.w r3, r3, #256 ; 0x100
80092c6: 2b00 cmp r3, #0
80092c8: d0f0 beq.n 80092ac <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
80092ca: 4b28 ldr r3, [pc, #160] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092cc: 6f1b ldr r3, [r3, #112] ; 0x70
80092ce: f403 7340 and.w r3, r3, #768 ; 0x300
80092d2: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
80092d4: 693b ldr r3, [r7, #16]
80092d6: 2b00 cmp r3, #0
80092d8: d035 beq.n 8009346 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
80092da: 687b ldr r3, [r7, #4]
80092dc: 6b1b ldr r3, [r3, #48] ; 0x30
80092de: f403 7340 and.w r3, r3, #768 ; 0x300
80092e2: 693a ldr r2, [r7, #16]
80092e4: 429a cmp r2, r3
80092e6: d02e beq.n 8009346 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80092e8: 4b20 ldr r3, [pc, #128] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092ea: 6f1b ldr r3, [r3, #112] ; 0x70
80092ec: f423 7340 bic.w r3, r3, #768 ; 0x300
80092f0: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80092f2: 4b1e ldr r3, [pc, #120] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092f4: 6f1b ldr r3, [r3, #112] ; 0x70
80092f6: 4a1d ldr r2, [pc, #116] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
80092f8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80092fc: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
80092fe: 4b1b ldr r3, [pc, #108] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009300: 6f1b ldr r3, [r3, #112] ; 0x70
8009302: 4a1a ldr r2, [pc, #104] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009304: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8009308: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
800930a: 4a18 ldr r2, [pc, #96] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800930c: 693b ldr r3, [r7, #16]
800930e: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8009310: 4b16 ldr r3, [pc, #88] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009312: 6f1b ldr r3, [r3, #112] ; 0x70
8009314: f003 0301 and.w r3, r3, #1
8009318: 2b01 cmp r3, #1
800931a: d114 bne.n 8009346 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800931c: f7fb fb40 bl 80049a0 <HAL_GetTick>
8009320: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8009322: e00a b.n 800933a <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8009324: f7fb fb3c bl 80049a0 <HAL_GetTick>
8009328: 4602 mov r2, r0
800932a: 697b ldr r3, [r7, #20]
800932c: 1ad3 subs r3, r2, r3
800932e: f241 3288 movw r2, #5000 ; 0x1388
8009332: 4293 cmp r3, r2
8009334: d901 bls.n 800933a <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
8009336: 2303 movs r3, #3
8009338: e317 b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800933a: 4b0c ldr r3, [pc, #48] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
800933c: 6f1b ldr r3, [r3, #112] ; 0x70
800933e: f003 0302 and.w r3, r3, #2
8009342: 2b00 cmp r3, #0
8009344: d0ee beq.n 8009324 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8009346: 687b ldr r3, [r7, #4]
8009348: 6b1b ldr r3, [r3, #48] ; 0x30
800934a: f403 7340 and.w r3, r3, #768 ; 0x300
800934e: f5b3 7f40 cmp.w r3, #768 ; 0x300
8009352: d111 bne.n 8009378 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
8009354: 4b05 ldr r3, [pc, #20] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009356: 689b ldr r3, [r3, #8]
8009358: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
800935c: 687b ldr r3, [r7, #4]
800935e: 6b19 ldr r1, [r3, #48] ; 0x30
8009360: 4b04 ldr r3, [pc, #16] ; (8009374 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
8009362: 400b ands r3, r1
8009364: 4901 ldr r1, [pc, #4] ; (800936c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8009366: 4313 orrs r3, r2
8009368: 608b str r3, [r1, #8]
800936a: e00b b.n 8009384 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
800936c: 40023800 .word 0x40023800
8009370: 40007000 .word 0x40007000
8009374: 0ffffcff .word 0x0ffffcff
8009378: 4bb0 ldr r3, [pc, #704] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800937a: 689b ldr r3, [r3, #8]
800937c: 4aaf ldr r2, [pc, #700] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800937e: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
8009382: 6093 str r3, [r2, #8]
8009384: 4bad ldr r3, [pc, #692] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009386: 6f1a ldr r2, [r3, #112] ; 0x70
8009388: 687b ldr r3, [r7, #4]
800938a: 6b1b ldr r3, [r3, #48] ; 0x30
800938c: f3c3 030b ubfx r3, r3, #0, #12
8009390: 49aa ldr r1, [pc, #680] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009392: 4313 orrs r3, r2
8009394: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8009396: 687b ldr r3, [r7, #4]
8009398: 681b ldr r3, [r3, #0]
800939a: f003 0310 and.w r3, r3, #16
800939e: 2b00 cmp r3, #0
80093a0: d010 beq.n 80093c4 <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
80093a2: 4ba6 ldr r3, [pc, #664] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093a4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80093a8: 4aa4 ldr r2, [pc, #656] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093aa: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80093ae: f8c2 308c str.w r3, [r2, #140] ; 0x8c
80093b2: 4ba2 ldr r3, [pc, #648] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093b4: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
80093b8: 687b ldr r3, [r7, #4]
80093ba: 6b9b ldr r3, [r3, #56] ; 0x38
80093bc: 499f ldr r1, [pc, #636] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093be: 4313 orrs r3, r2
80093c0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
80093c4: 687b ldr r3, [r7, #4]
80093c6: 681b ldr r3, [r3, #0]
80093c8: f403 4380 and.w r3, r3, #16384 ; 0x4000
80093cc: 2b00 cmp r3, #0
80093ce: d00a beq.n 80093e6 <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
80093d0: 4b9a ldr r3, [pc, #616] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093d2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093d6: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80093da: 687b ldr r3, [r7, #4]
80093dc: 6e5b ldr r3, [r3, #100] ; 0x64
80093de: 4997 ldr r1, [pc, #604] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093e0: 4313 orrs r3, r2
80093e2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80093e6: 687b ldr r3, [r7, #4]
80093e8: 681b ldr r3, [r3, #0]
80093ea: f403 4300 and.w r3, r3, #32768 ; 0x8000
80093ee: 2b00 cmp r3, #0
80093f0: d00a beq.n 8009408 <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80093f2: 4b92 ldr r3, [pc, #584] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80093f4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80093f8: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
80093fc: 687b ldr r3, [r7, #4]
80093fe: 6e9b ldr r3, [r3, #104] ; 0x68
8009400: 498e ldr r1, [pc, #568] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009402: 4313 orrs r3, r2
8009404: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8009408: 687b ldr r3, [r7, #4]
800940a: 681b ldr r3, [r3, #0]
800940c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8009410: 2b00 cmp r3, #0
8009412: d00a beq.n 800942a <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8009414: 4b89 ldr r3, [pc, #548] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009416: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800941a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
800941e: 687b ldr r3, [r7, #4]
8009420: 6edb ldr r3, [r3, #108] ; 0x6c
8009422: 4986 ldr r1, [pc, #536] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009424: 4313 orrs r3, r2
8009426: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
800942a: 687b ldr r3, [r7, #4]
800942c: 681b ldr r3, [r3, #0]
800942e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8009432: 2b00 cmp r3, #0
8009434: d00a beq.n 800944c <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8009436: 4b81 ldr r3, [pc, #516] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009438: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800943c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8009440: 687b ldr r3, [r7, #4]
8009442: 6f1b ldr r3, [r3, #112] ; 0x70
8009444: 497d ldr r1, [pc, #500] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009446: 4313 orrs r3, r2
8009448: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800944c: 687b ldr r3, [r7, #4]
800944e: 681b ldr r3, [r3, #0]
8009450: f003 0340 and.w r3, r3, #64 ; 0x40
8009454: 2b00 cmp r3, #0
8009456: d00a beq.n 800946e <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8009458: 4b78 ldr r3, [pc, #480] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800945a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800945e: f023 0203 bic.w r2, r3, #3
8009462: 687b ldr r3, [r7, #4]
8009464: 6c5b ldr r3, [r3, #68] ; 0x44
8009466: 4975 ldr r1, [pc, #468] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009468: 4313 orrs r3, r2
800946a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
800946e: 687b ldr r3, [r7, #4]
8009470: 681b ldr r3, [r3, #0]
8009472: f003 0380 and.w r3, r3, #128 ; 0x80
8009476: 2b00 cmp r3, #0
8009478: d00a beq.n 8009490 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
800947a: 4b70 ldr r3, [pc, #448] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800947c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009480: f023 020c bic.w r2, r3, #12
8009484: 687b ldr r3, [r7, #4]
8009486: 6c9b ldr r3, [r3, #72] ; 0x48
8009488: 496c ldr r1, [pc, #432] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800948a: 4313 orrs r3, r2
800948c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8009490: 687b ldr r3, [r7, #4]
8009492: 681b ldr r3, [r3, #0]
8009494: f403 7380 and.w r3, r3, #256 ; 0x100
8009498: 2b00 cmp r3, #0
800949a: d00a beq.n 80094b2 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
800949c: 4b67 ldr r3, [pc, #412] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800949e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80094a2: f023 0230 bic.w r2, r3, #48 ; 0x30
80094a6: 687b ldr r3, [r7, #4]
80094a8: 6cdb ldr r3, [r3, #76] ; 0x4c
80094aa: 4964 ldr r1, [pc, #400] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094ac: 4313 orrs r3, r2
80094ae: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80094b2: 687b ldr r3, [r7, #4]
80094b4: 681b ldr r3, [r3, #0]
80094b6: f403 7300 and.w r3, r3, #512 ; 0x200
80094ba: 2b00 cmp r3, #0
80094bc: d00a beq.n 80094d4 <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80094be: 4b5f ldr r3, [pc, #380] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094c0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80094c4: f023 02c0 bic.w r2, r3, #192 ; 0xc0
80094c8: 687b ldr r3, [r7, #4]
80094ca: 6d1b ldr r3, [r3, #80] ; 0x50
80094cc: 495b ldr r1, [pc, #364] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094ce: 4313 orrs r3, r2
80094d0: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
80094d4: 687b ldr r3, [r7, #4]
80094d6: 681b ldr r3, [r3, #0]
80094d8: f403 6380 and.w r3, r3, #1024 ; 0x400
80094dc: 2b00 cmp r3, #0
80094de: d00a beq.n 80094f6 <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
80094e0: 4b56 ldr r3, [pc, #344] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094e2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80094e6: f423 7240 bic.w r2, r3, #768 ; 0x300
80094ea: 687b ldr r3, [r7, #4]
80094ec: 6d5b ldr r3, [r3, #84] ; 0x54
80094ee: 4953 ldr r1, [pc, #332] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80094f0: 4313 orrs r3, r2
80094f2: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
80094f6: 687b ldr r3, [r7, #4]
80094f8: 681b ldr r3, [r3, #0]
80094fa: f403 6300 and.w r3, r3, #2048 ; 0x800
80094fe: 2b00 cmp r3, #0
8009500: d00a beq.n 8009518 <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8009502: 4b4e ldr r3, [pc, #312] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009504: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009508: f423 6240 bic.w r2, r3, #3072 ; 0xc00
800950c: 687b ldr r3, [r7, #4]
800950e: 6d9b ldr r3, [r3, #88] ; 0x58
8009510: 494a ldr r1, [pc, #296] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009512: 4313 orrs r3, r2
8009514: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8009518: 687b ldr r3, [r7, #4]
800951a: 681b ldr r3, [r3, #0]
800951c: f403 5380 and.w r3, r3, #4096 ; 0x1000
8009520: 2b00 cmp r3, #0
8009522: d00a beq.n 800953a <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8009524: 4b45 ldr r3, [pc, #276] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009526: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800952a: f423 5240 bic.w r2, r3, #12288 ; 0x3000
800952e: 687b ldr r3, [r7, #4]
8009530: 6ddb ldr r3, [r3, #92] ; 0x5c
8009532: 4942 ldr r1, [pc, #264] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009534: 4313 orrs r3, r2
8009536: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
800953a: 687b ldr r3, [r7, #4]
800953c: 681b ldr r3, [r3, #0]
800953e: f403 5300 and.w r3, r3, #8192 ; 0x2000
8009542: 2b00 cmp r3, #0
8009544: d00a beq.n 800955c <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8009546: 4b3d ldr r3, [pc, #244] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009548: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800954c: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8009550: 687b ldr r3, [r7, #4]
8009552: 6e1b ldr r3, [r3, #96] ; 0x60
8009554: 4939 ldr r1, [pc, #228] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009556: 4313 orrs r3, r2
8009558: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
800955c: 687b ldr r3, [r7, #4]
800955e: 681b ldr r3, [r3, #0]
8009560: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8009564: 2b00 cmp r3, #0
8009566: d00a beq.n 800957e <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8009568: 4b34 ldr r3, [pc, #208] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800956a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800956e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
8009572: 687b ldr r3, [r7, #4]
8009574: 6f9b ldr r3, [r3, #120] ; 0x78
8009576: 4931 ldr r1, [pc, #196] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009578: 4313 orrs r3, r2
800957a: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
800957e: 687b ldr r3, [r7, #4]
8009580: 681b ldr r3, [r3, #0]
8009582: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8009586: 2b00 cmp r3, #0
8009588: d011 beq.n 80095ae <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
800958a: 4b2c ldr r3, [pc, #176] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800958c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8009590: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
8009594: 687b ldr r3, [r7, #4]
8009596: 6fdb ldr r3, [r3, #124] ; 0x7c
8009598: 4928 ldr r1, [pc, #160] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800959a: 4313 orrs r3, r2
800959c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
80095a0: 687b ldr r3, [r7, #4]
80095a2: 6fdb ldr r3, [r3, #124] ; 0x7c
80095a4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
80095a8: d101 bne.n 80095ae <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
80095aa: 2301 movs r3, #1
80095ac: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
80095ae: 687b ldr r3, [r7, #4]
80095b0: 681b ldr r3, [r3, #0]
80095b2: f003 0308 and.w r3, r3, #8
80095b6: 2b00 cmp r3, #0
80095b8: d001 beq.n 80095be <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
80095ba: 2301 movs r3, #1
80095bc: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80095be: 687b ldr r3, [r7, #4]
80095c0: 681b ldr r3, [r3, #0]
80095c2: f403 2380 and.w r3, r3, #262144 ; 0x40000
80095c6: 2b00 cmp r3, #0
80095c8: d00a beq.n 80095e0 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80095ca: 4b1c ldr r3, [pc, #112] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095cc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80095d0: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
80095d4: 687b ldr r3, [r7, #4]
80095d6: 6f5b ldr r3, [r3, #116] ; 0x74
80095d8: 4918 ldr r1, [pc, #96] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095da: 4313 orrs r3, r2
80095dc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
80095e0: 687b ldr r3, [r7, #4]
80095e2: 681b ldr r3, [r3, #0]
80095e4: f403 0300 and.w r3, r3, #8388608 ; 0x800000
80095e8: 2b00 cmp r3, #0
80095ea: d00b beq.n 8009604 <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
80095ec: 4b13 ldr r3, [pc, #76] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80095f2: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
80095f6: 687b ldr r3, [r7, #4]
80095f8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80095fc: 490f ldr r1, [pc, #60] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
80095fe: 4313 orrs r3, r2
8009600: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
8009604: 69fb ldr r3, [r7, #28]
8009606: 2b01 cmp r3, #1
8009608: d005 beq.n 8009616 <HAL_RCCEx_PeriphCLKConfig+0x47a>
800960a: 687b ldr r3, [r7, #4]
800960c: 681b ldr r3, [r3, #0]
800960e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
8009612: f040 80d8 bne.w 80097c6 <HAL_RCCEx_PeriphCLKConfig+0x62a>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8009616: 4b09 ldr r3, [pc, #36] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8009618: 681b ldr r3, [r3, #0]
800961a: 4a08 ldr r2, [pc, #32] ; (800963c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
800961c: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
8009620: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009622: f7fb f9bd bl 80049a0 <HAL_GetTick>
8009626: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8009628: e00a b.n 8009640 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
800962a: f7fb f9b9 bl 80049a0 <HAL_GetTick>
800962e: 4602 mov r2, r0
8009630: 697b ldr r3, [r7, #20]
8009632: 1ad3 subs r3, r2, r3
8009634: 2b64 cmp r3, #100 ; 0x64
8009636: d903 bls.n 8009640 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8009638: 2303 movs r3, #3
800963a: e196 b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
800963c: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8009640: 4b6c ldr r3, [pc, #432] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009642: 681b ldr r3, [r3, #0]
8009644: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8009648: 2b00 cmp r3, #0
800964a: d1ee bne.n 800962a <HAL_RCCEx_PeriphCLKConfig+0x48e>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
800964c: 687b ldr r3, [r7, #4]
800964e: 681b ldr r3, [r3, #0]
8009650: f003 0301 and.w r3, r3, #1
8009654: 2b00 cmp r3, #0
8009656: d021 beq.n 800969c <HAL_RCCEx_PeriphCLKConfig+0x500>
8009658: 687b ldr r3, [r7, #4]
800965a: 6b5b ldr r3, [r3, #52] ; 0x34
800965c: 2b00 cmp r3, #0
800965e: d11d bne.n 800969c <HAL_RCCEx_PeriphCLKConfig+0x500>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8009660: 4b64 ldr r3, [pc, #400] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009662: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009666: 0c1b lsrs r3, r3, #16
8009668: f003 0303 and.w r3, r3, #3
800966c: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
800966e: 4b61 ldr r3, [pc, #388] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009670: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8009674: 0e1b lsrs r3, r3, #24
8009676: f003 030f and.w r3, r3, #15
800967a: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
800967c: 687b ldr r3, [r7, #4]
800967e: 685b ldr r3, [r3, #4]
8009680: 019a lsls r2, r3, #6
8009682: 693b ldr r3, [r7, #16]
8009684: 041b lsls r3, r3, #16
8009686: 431a orrs r2, r3
8009688: 68fb ldr r3, [r7, #12]
800968a: 061b lsls r3, r3, #24
800968c: 431a orrs r2, r3
800968e: 687b ldr r3, [r7, #4]
8009690: 689b ldr r3, [r3, #8]
8009692: 071b lsls r3, r3, #28
8009694: 4957 ldr r1, [pc, #348] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009696: 4313 orrs r3, r2
8009698: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
800969c: 687b ldr r3, [r7, #4]
800969e: 681b ldr r3, [r3, #0]
80096a0: f403 2300 and.w r3, r3, #524288 ; 0x80000
80096a4: 2b00 cmp r3, #0
80096a6: d004 beq.n 80096b2 <HAL_RCCEx_PeriphCLKConfig+0x516>
80096a8: 687b ldr r3, [r7, #4]
80096aa: 6bdb ldr r3, [r3, #60] ; 0x3c
80096ac: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
80096b0: d00a beq.n 80096c8 <HAL_RCCEx_PeriphCLKConfig+0x52c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80096b2: 687b ldr r3, [r7, #4]
80096b4: 681b ldr r3, [r3, #0]
80096b6: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
80096ba: 2b00 cmp r3, #0
80096bc: d02e beq.n 800971c <HAL_RCCEx_PeriphCLKConfig+0x580>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
80096be: 687b ldr r3, [r7, #4]
80096c0: 6c1b ldr r3, [r3, #64] ; 0x40
80096c2: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80096c6: d129 bne.n 800971c <HAL_RCCEx_PeriphCLKConfig+0x580>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
80096c8: 4b4a ldr r3, [pc, #296] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096ca: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80096ce: 0c1b lsrs r3, r3, #16
80096d0: f003 0303 and.w r3, r3, #3
80096d4: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
80096d6: 4b47 ldr r3, [pc, #284] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096d8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80096dc: 0f1b lsrs r3, r3, #28
80096de: f003 0307 and.w r3, r3, #7
80096e2: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
80096e4: 687b ldr r3, [r7, #4]
80096e6: 685b ldr r3, [r3, #4]
80096e8: 019a lsls r2, r3, #6
80096ea: 693b ldr r3, [r7, #16]
80096ec: 041b lsls r3, r3, #16
80096ee: 431a orrs r2, r3
80096f0: 687b ldr r3, [r7, #4]
80096f2: 68db ldr r3, [r3, #12]
80096f4: 061b lsls r3, r3, #24
80096f6: 431a orrs r2, r3
80096f8: 68fb ldr r3, [r7, #12]
80096fa: 071b lsls r3, r3, #28
80096fc: 493d ldr r1, [pc, #244] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80096fe: 4313 orrs r3, r2
8009700: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8009704: 4b3b ldr r3, [pc, #236] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009706: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
800970a: f023 021f bic.w r2, r3, #31
800970e: 687b ldr r3, [r7, #4]
8009710: 6a5b ldr r3, [r3, #36] ; 0x24
8009712: 3b01 subs r3, #1
8009714: 4937 ldr r1, [pc, #220] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009716: 4313 orrs r3, r2
8009718: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
800971c: 687b ldr r3, [r7, #4]
800971e: 681b ldr r3, [r3, #0]
8009720: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8009724: 2b00 cmp r3, #0
8009726: d01d beq.n 8009764 <HAL_RCCEx_PeriphCLKConfig+0x5c8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8009728: 4b32 ldr r3, [pc, #200] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800972a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800972e: 0e1b lsrs r3, r3, #24
8009730: f003 030f and.w r3, r3, #15
8009734: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8009736: 4b2f ldr r3, [pc, #188] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009738: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800973c: 0f1b lsrs r3, r3, #28
800973e: f003 0307 and.w r3, r3, #7
8009742: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
8009744: 687b ldr r3, [r7, #4]
8009746: 685b ldr r3, [r3, #4]
8009748: 019a lsls r2, r3, #6
800974a: 687b ldr r3, [r7, #4]
800974c: 691b ldr r3, [r3, #16]
800974e: 041b lsls r3, r3, #16
8009750: 431a orrs r2, r3
8009752: 693b ldr r3, [r7, #16]
8009754: 061b lsls r3, r3, #24
8009756: 431a orrs r2, r3
8009758: 68fb ldr r3, [r7, #12]
800975a: 071b lsls r3, r3, #28
800975c: 4925 ldr r1, [pc, #148] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800975e: 4313 orrs r3, r2
8009760: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8009764: 687b ldr r3, [r7, #4]
8009766: 681b ldr r3, [r3, #0]
8009768: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800976c: 2b00 cmp r3, #0
800976e: d011 beq.n 8009794 <HAL_RCCEx_PeriphCLKConfig+0x5f8>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
8009770: 687b ldr r3, [r7, #4]
8009772: 685b ldr r3, [r3, #4]
8009774: 019a lsls r2, r3, #6
8009776: 687b ldr r3, [r7, #4]
8009778: 691b ldr r3, [r3, #16]
800977a: 041b lsls r3, r3, #16
800977c: 431a orrs r2, r3
800977e: 687b ldr r3, [r7, #4]
8009780: 68db ldr r3, [r3, #12]
8009782: 061b lsls r3, r3, #24
8009784: 431a orrs r2, r3
8009786: 687b ldr r3, [r7, #4]
8009788: 689b ldr r3, [r3, #8]
800978a: 071b lsls r3, r3, #28
800978c: 4919 ldr r1, [pc, #100] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800978e: 4313 orrs r3, r2
8009790: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8009794: 4b17 ldr r3, [pc, #92] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8009796: 681b ldr r3, [r3, #0]
8009798: 4a16 ldr r2, [pc, #88] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800979a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800979e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80097a0: f7fb f8fe bl 80049a0 <HAL_GetTick>
80097a4: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80097a6: e008 b.n 80097ba <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
80097a8: f7fb f8fa bl 80049a0 <HAL_GetTick>
80097ac: 4602 mov r2, r0
80097ae: 697b ldr r3, [r7, #20]
80097b0: 1ad3 subs r3, r2, r3
80097b2: 2b64 cmp r3, #100 ; 0x64
80097b4: d901 bls.n 80097ba <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80097b6: 2303 movs r3, #3
80097b8: e0d7 b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
80097ba: 4b0e ldr r3, [pc, #56] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097bc: 681b ldr r3, [r3, #0]
80097be: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
80097c2: 2b00 cmp r3, #0
80097c4: d0f0 beq.n 80097a8 <HAL_RCCEx_PeriphCLKConfig+0x60c>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
80097c6: 69bb ldr r3, [r7, #24]
80097c8: 2b01 cmp r3, #1
80097ca: f040 80cd bne.w 8009968 <HAL_RCCEx_PeriphCLKConfig+0x7cc>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
80097ce: 4b09 ldr r3, [pc, #36] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097d0: 681b ldr r3, [r3, #0]
80097d2: 4a08 ldr r2, [pc, #32] ; (80097f4 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80097d4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80097d8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80097da: f7fb f8e1 bl 80049a0 <HAL_GetTick>
80097de: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80097e0: e00a b.n 80097f8 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80097e2: f7fb f8dd bl 80049a0 <HAL_GetTick>
80097e6: 4602 mov r2, r0
80097e8: 697b ldr r3, [r7, #20]
80097ea: 1ad3 subs r3, r2, r3
80097ec: 2b64 cmp r3, #100 ; 0x64
80097ee: d903 bls.n 80097f8 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80097f0: 2303 movs r3, #3
80097f2: e0ba b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
80097f4: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
80097f8: 4b5e ldr r3, [pc, #376] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80097fa: 681b ldr r3, [r3, #0]
80097fc: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8009800: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8009804: d0ed beq.n 80097e2 <HAL_RCCEx_PeriphCLKConfig+0x646>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8009806: 687b ldr r3, [r7, #4]
8009808: 681b ldr r3, [r3, #0]
800980a: f403 2300 and.w r3, r3, #524288 ; 0x80000
800980e: 2b00 cmp r3, #0
8009810: d003 beq.n 800981a <HAL_RCCEx_PeriphCLKConfig+0x67e>
8009812: 687b ldr r3, [r7, #4]
8009814: 6bdb ldr r3, [r3, #60] ; 0x3c
8009816: 2b00 cmp r3, #0
8009818: d009 beq.n 800982e <HAL_RCCEx_PeriphCLKConfig+0x692>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
800981a: 687b ldr r3, [r7, #4]
800981c: 681b ldr r3, [r3, #0]
800981e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8009822: 2b00 cmp r3, #0
8009824: d02e beq.n 8009884 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
8009826: 687b ldr r3, [r7, #4]
8009828: 6c1b ldr r3, [r3, #64] ; 0x40
800982a: 2b00 cmp r3, #0
800982c: d12a bne.n 8009884 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
800982e: 4b51 ldr r3, [pc, #324] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009830: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009834: 0c1b lsrs r3, r3, #16
8009836: f003 0303 and.w r3, r3, #3
800983a: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
800983c: 4b4d ldr r3, [pc, #308] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800983e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8009842: 0f1b lsrs r3, r3, #28
8009844: f003 0307 and.w r3, r3, #7
8009848: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
800984a: 687b ldr r3, [r7, #4]
800984c: 695b ldr r3, [r3, #20]
800984e: 019a lsls r2, r3, #6
8009850: 693b ldr r3, [r7, #16]
8009852: 041b lsls r3, r3, #16
8009854: 431a orrs r2, r3
8009856: 687b ldr r3, [r7, #4]
8009858: 699b ldr r3, [r3, #24]
800985a: 061b lsls r3, r3, #24
800985c: 431a orrs r2, r3
800985e: 68fb ldr r3, [r7, #12]
8009860: 071b lsls r3, r3, #28
8009862: 4944 ldr r1, [pc, #272] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009864: 4313 orrs r3, r2
8009866: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
800986a: 4b42 ldr r3, [pc, #264] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800986c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009870: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
8009874: 687b ldr r3, [r7, #4]
8009876: 6a9b ldr r3, [r3, #40] ; 0x28
8009878: 3b01 subs r3, #1
800987a: 021b lsls r3, r3, #8
800987c: 493d ldr r1, [pc, #244] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800987e: 4313 orrs r3, r2
8009880: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8009884: 687b ldr r3, [r7, #4]
8009886: 681b ldr r3, [r3, #0]
8009888: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800988c: 2b00 cmp r3, #0
800988e: d022 beq.n 80098d6 <HAL_RCCEx_PeriphCLKConfig+0x73a>
8009890: 687b ldr r3, [r7, #4]
8009892: 6fdb ldr r3, [r3, #124] ; 0x7c
8009894: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
8009898: d11d bne.n 80098d6 <HAL_RCCEx_PeriphCLKConfig+0x73a>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
800989a: 4b36 ldr r3, [pc, #216] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800989c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098a0: 0e1b lsrs r3, r3, #24
80098a2: f003 030f and.w r3, r3, #15
80098a6: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
80098a8: 4b32 ldr r3, [pc, #200] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098aa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098ae: 0f1b lsrs r3, r3, #28
80098b0: f003 0307 and.w r3, r3, #7
80098b4: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
80098b6: 687b ldr r3, [r7, #4]
80098b8: 695b ldr r3, [r3, #20]
80098ba: 019a lsls r2, r3, #6
80098bc: 687b ldr r3, [r7, #4]
80098be: 6a1b ldr r3, [r3, #32]
80098c0: 041b lsls r3, r3, #16
80098c2: 431a orrs r2, r3
80098c4: 693b ldr r3, [r7, #16]
80098c6: 061b lsls r3, r3, #24
80098c8: 431a orrs r2, r3
80098ca: 68fb ldr r3, [r7, #12]
80098cc: 071b lsls r3, r3, #28
80098ce: 4929 ldr r1, [pc, #164] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098d0: 4313 orrs r3, r2
80098d2: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
80098d6: 687b ldr r3, [r7, #4]
80098d8: 681b ldr r3, [r3, #0]
80098da: f003 0308 and.w r3, r3, #8
80098de: 2b00 cmp r3, #0
80098e0: d028 beq.n 8009934 <HAL_RCCEx_PeriphCLKConfig+0x798>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
80098e2: 4b24 ldr r3, [pc, #144] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098e4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098e8: 0e1b lsrs r3, r3, #24
80098ea: f003 030f and.w r3, r3, #15
80098ee: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
80098f0: 4b20 ldr r3, [pc, #128] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80098f2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80098f6: 0c1b lsrs r3, r3, #16
80098f8: f003 0303 and.w r3, r3, #3
80098fc: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
80098fe: 687b ldr r3, [r7, #4]
8009900: 695b ldr r3, [r3, #20]
8009902: 019a lsls r2, r3, #6
8009904: 68fb ldr r3, [r7, #12]
8009906: 041b lsls r3, r3, #16
8009908: 431a orrs r2, r3
800990a: 693b ldr r3, [r7, #16]
800990c: 061b lsls r3, r3, #24
800990e: 431a orrs r2, r3
8009910: 687b ldr r3, [r7, #4]
8009912: 69db ldr r3, [r3, #28]
8009914: 071b lsls r3, r3, #28
8009916: 4917 ldr r1, [pc, #92] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009918: 4313 orrs r3, r2
800991a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
800991e: 4b15 ldr r3, [pc, #84] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009920: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8009924: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8009928: 687b ldr r3, [r7, #4]
800992a: 6adb ldr r3, [r3, #44] ; 0x2c
800992c: 4911 ldr r1, [pc, #68] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800992e: 4313 orrs r3, r2
8009930: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8009934: 4b0f ldr r3, [pc, #60] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8009936: 681b ldr r3, [r3, #0]
8009938: 4a0e ldr r2, [pc, #56] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800993a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800993e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8009940: f7fb f82e bl 80049a0 <HAL_GetTick>
8009944: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8009946: e008 b.n 800995a <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8009948: f7fb f82a bl 80049a0 <HAL_GetTick>
800994c: 4602 mov r2, r0
800994e: 697b ldr r3, [r7, #20]
8009950: 1ad3 subs r3, r2, r3
8009952: 2b64 cmp r3, #100 ; 0x64
8009954: d901 bls.n 800995a <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8009956: 2303 movs r3, #3
8009958: e007 b.n 800996a <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
800995a: 4b06 ldr r3, [pc, #24] ; (8009974 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800995c: 681b ldr r3, [r3, #0]
800995e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8009962: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8009966: d1ef bne.n 8009948 <HAL_RCCEx_PeriphCLKConfig+0x7ac>
}
}
}
return HAL_OK;
8009968: 2300 movs r3, #0
}
800996a: 4618 mov r0, r3
800996c: 3720 adds r7, #32
800996e: 46bd mov sp, r7
8009970: bd80 pop {r7, pc}
8009972: bf00 nop
8009974: 40023800 .word 0x40023800
08009978 <HAL_RNG_Init>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
8009978: b580 push {r7, lr}
800997a: b082 sub sp, #8
800997c: af00 add r7, sp, #0
800997e: 6078 str r0, [r7, #4]
/* Check the RNG handle allocation */
if (hrng == NULL)
8009980: 687b ldr r3, [r7, #4]
8009982: 2b00 cmp r3, #0
8009984: d101 bne.n 800998a <HAL_RNG_Init+0x12>
{
return HAL_ERROR;
8009986: 2301 movs r3, #1
8009988: e01c b.n 80099c4 <HAL_RNG_Init+0x4c>
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
800998a: 687b ldr r3, [r7, #4]
800998c: 795b ldrb r3, [r3, #5]
800998e: b2db uxtb r3, r3
8009990: 2b00 cmp r3, #0
8009992: d105 bne.n 80099a0 <HAL_RNG_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
8009994: 687b ldr r3, [r7, #4]
8009996: 2200 movs r2, #0
8009998: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
800999a: 6878 ldr r0, [r7, #4]
800999c: f7fa fc6a bl 8004274 <HAL_RNG_MspInit>
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
80099a0: 687b ldr r3, [r7, #4]
80099a2: 2202 movs r2, #2
80099a4: 715a strb r2, [r3, #5]
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
80099a6: 687b ldr r3, [r7, #4]
80099a8: 681b ldr r3, [r3, #0]
80099aa: 681a ldr r2, [r3, #0]
80099ac: 687b ldr r3, [r7, #4]
80099ae: 681b ldr r3, [r3, #0]
80099b0: f042 0204 orr.w r2, r2, #4
80099b4: 601a str r2, [r3, #0]
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
80099b6: 687b ldr r3, [r7, #4]
80099b8: 2201 movs r2, #1
80099ba: 715a strb r2, [r3, #5]
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
80099bc: 687b ldr r3, [r7, #4]
80099be: 2200 movs r2, #0
80099c0: 609a str r2, [r3, #8]
/* Return function status */
return HAL_OK;
80099c2: 2300 movs r3, #0
}
80099c4: 4618 mov r0, r3
80099c6: 3708 adds r7, #8
80099c8: 46bd mov sp, r7
80099ca: bd80 pop {r7, pc}
080099cc <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
80099cc: b580 push {r7, lr}
80099ce: b082 sub sp, #8
80099d0: af00 add r7, sp, #0
80099d2: 6078 str r0, [r7, #4]
80099d4: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
80099d6: 687b ldr r3, [r7, #4]
80099d8: 2b00 cmp r3, #0
80099da: d101 bne.n 80099e0 <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
80099dc: 2301 movs r3, #1
80099de: e025 b.n 8009a2c <HAL_SDRAM_Init+0x60>
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
80099e0: 687b ldr r3, [r7, #4]
80099e2: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
80099e6: b2db uxtb r3, r3
80099e8: 2b00 cmp r3, #0
80099ea: d106 bne.n 80099fa <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
80099ec: 687b ldr r3, [r7, #4]
80099ee: 2200 movs r2, #0
80099f0: f883 202d strb.w r2, [r3, #45] ; 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
80099f4: 6878 ldr r0, [r7, #4]
80099f6: f7fa fe2b bl 8004650 <HAL_SDRAM_MspInit>
#endif
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
80099fa: 687b ldr r3, [r7, #4]
80099fc: 2202 movs r2, #2
80099fe: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
8009a02: 687b ldr r3, [r7, #4]
8009a04: 681a ldr r2, [r3, #0]
8009a06: 687b ldr r3, [r7, #4]
8009a08: 3304 adds r3, #4
8009a0a: 4619 mov r1, r3
8009a0c: 4610 mov r0, r2
8009a0e: f001 fa1d bl 800ae4c <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
8009a12: 687b ldr r3, [r7, #4]
8009a14: 6818 ldr r0, [r3, #0]
8009a16: 687b ldr r3, [r7, #4]
8009a18: 685b ldr r3, [r3, #4]
8009a1a: 461a mov r2, r3
8009a1c: 6839 ldr r1, [r7, #0]
8009a1e: f001 fa87 bl 800af30 <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
8009a22: 687b ldr r3, [r7, #4]
8009a24: 2201 movs r2, #1
8009a26: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8009a2a: 2300 movs r3, #0
}
8009a2c: 4618 mov r0, r3
8009a2e: 3708 adds r7, #8
8009a30: 46bd mov sp, r7
8009a32: bd80 pop {r7, pc}
08009a34 <HAL_SDRAM_SendCommand>:
* @param Command SDRAM command structure
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
8009a34: b580 push {r7, lr}
8009a36: b084 sub sp, #16
8009a38: af00 add r7, sp, #0
8009a3a: 60f8 str r0, [r7, #12]
8009a3c: 60b9 str r1, [r7, #8]
8009a3e: 607a str r2, [r7, #4]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8009a40: 68fb ldr r3, [r7, #12]
8009a42: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009a46: b2db uxtb r3, r3
8009a48: 2b02 cmp r3, #2
8009a4a: d101 bne.n 8009a50 <HAL_SDRAM_SendCommand+0x1c>
{
return HAL_BUSY;
8009a4c: 2302 movs r3, #2
8009a4e: e018 b.n 8009a82 <HAL_SDRAM_SendCommand+0x4e>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8009a50: 68fb ldr r3, [r7, #12]
8009a52: 2202 movs r2, #2
8009a54: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
8009a58: 68fb ldr r3, [r7, #12]
8009a5a: 681b ldr r3, [r3, #0]
8009a5c: 687a ldr r2, [r7, #4]
8009a5e: 68b9 ldr r1, [r7, #8]
8009a60: 4618 mov r0, r3
8009a62: f001 fae5 bl 800b030 <FMC_SDRAM_SendCommand>
/* Update the SDRAM controller state state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
8009a66: 68bb ldr r3, [r7, #8]
8009a68: 681b ldr r3, [r3, #0]
8009a6a: 2b02 cmp r3, #2
8009a6c: d104 bne.n 8009a78 <HAL_SDRAM_SendCommand+0x44>
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
8009a6e: 68fb ldr r3, [r7, #12]
8009a70: 2205 movs r2, #5
8009a72: f883 202c strb.w r2, [r3, #44] ; 0x2c
8009a76: e003 b.n 8009a80 <HAL_SDRAM_SendCommand+0x4c>
}
else
{
hsdram->State = HAL_SDRAM_STATE_READY;
8009a78: 68fb ldr r3, [r7, #12]
8009a7a: 2201 movs r2, #1
8009a7c: f883 202c strb.w r2, [r3, #44] ; 0x2c
}
return HAL_OK;
8009a80: 2300 movs r3, #0
}
8009a82: 4618 mov r0, r3
8009a84: 3710 adds r7, #16
8009a86: 46bd mov sp, r7
8009a88: bd80 pop {r7, pc}
08009a8a <HAL_SDRAM_ProgramRefreshRate>:
* the configuration information for SDRAM module.
* @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
8009a8a: b580 push {r7, lr}
8009a8c: b082 sub sp, #8
8009a8e: af00 add r7, sp, #0
8009a90: 6078 str r0, [r7, #4]
8009a92: 6039 str r1, [r7, #0]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8009a94: 687b ldr r3, [r7, #4]
8009a96: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8009a9a: b2db uxtb r3, r3
8009a9c: 2b02 cmp r3, #2
8009a9e: d101 bne.n 8009aa4 <HAL_SDRAM_ProgramRefreshRate+0x1a>
{
return HAL_BUSY;
8009aa0: 2302 movs r3, #2
8009aa2: e00e b.n 8009ac2 <HAL_SDRAM_ProgramRefreshRate+0x38>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8009aa4: 687b ldr r3, [r7, #4]
8009aa6: 2202 movs r2, #2
8009aa8: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Program the refresh rate */
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
8009aac: 687b ldr r3, [r7, #4]
8009aae: 681b ldr r3, [r3, #0]
8009ab0: 6839 ldr r1, [r7, #0]
8009ab2: 4618 mov r0, r3
8009ab4: f001 fadd bl 800b072 <FMC_SDRAM_ProgramRefreshRate>
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
8009ab8: 687b ldr r3, [r7, #4]
8009aba: 2201 movs r2, #1
8009abc: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8009ac0: 2300 movs r3, #0
}
8009ac2: 4618 mov r0, r3
8009ac4: 3708 adds r7, #8
8009ac6: 46bd mov sp, r7
8009ac8: bd80 pop {r7, pc}
08009aca <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8009aca: b580 push {r7, lr}
8009acc: b084 sub sp, #16
8009ace: af00 add r7, sp, #0
8009ad0: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8009ad2: 687b ldr r3, [r7, #4]
8009ad4: 2b00 cmp r3, #0
8009ad6: d101 bne.n 8009adc <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8009ad8: 2301 movs r3, #1
8009ada: e084 b.n 8009be6 <HAL_SPI_Init+0x11c>
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8009adc: 687b ldr r3, [r7, #4]
8009ade: 2200 movs r2, #0
8009ae0: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8009ae2: 687b ldr r3, [r7, #4]
8009ae4: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
8009ae8: b2db uxtb r3, r3
8009aea: 2b00 cmp r3, #0
8009aec: d106 bne.n 8009afc <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8009aee: 687b ldr r3, [r7, #4]
8009af0: 2200 movs r2, #0
8009af2: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8009af6: 6878 ldr r0, [r7, #4]
8009af8: f7fa fbdc bl 80042b4 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8009afc: 687b ldr r3, [r7, #4]
8009afe: 2202 movs r2, #2
8009b00: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8009b04: 687b ldr r3, [r7, #4]
8009b06: 681b ldr r3, [r3, #0]
8009b08: 681a ldr r2, [r3, #0]
8009b0a: 687b ldr r3, [r7, #4]
8009b0c: 681b ldr r3, [r3, #0]
8009b0e: f022 0240 bic.w r2, r2, #64 ; 0x40
8009b12: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8009b14: 687b ldr r3, [r7, #4]
8009b16: 68db ldr r3, [r3, #12]
8009b18: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b1c: d902 bls.n 8009b24 <HAL_SPI_Init+0x5a>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8009b1e: 2300 movs r3, #0
8009b20: 60fb str r3, [r7, #12]
8009b22: e002 b.n 8009b2a <HAL_SPI_Init+0x60>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8009b24: f44f 5380 mov.w r3, #4096 ; 0x1000
8009b28: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8009b2a: 687b ldr r3, [r7, #4]
8009b2c: 68db ldr r3, [r3, #12]
8009b2e: f5b3 6f70 cmp.w r3, #3840 ; 0xf00
8009b32: d007 beq.n 8009b44 <HAL_SPI_Init+0x7a>
8009b34: 687b ldr r3, [r7, #4]
8009b36: 68db ldr r3, [r3, #12]
8009b38: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b3c: d002 beq.n 8009b44 <HAL_SPI_Init+0x7a>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8009b3e: 687b ldr r3, [r7, #4]
8009b40: 2200 movs r2, #0
8009b42: 629a str r2, [r3, #40] ; 0x28
}
/* Align the CRC Length on the data size */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
8009b44: 687b ldr r3, [r7, #4]
8009b46: 6b1b ldr r3, [r3, #48] ; 0x30
8009b48: 2b00 cmp r3, #0
8009b4a: d10b bne.n 8009b64 <HAL_SPI_Init+0x9a>
{
/* CRC Length aligned on the data size : value set by default */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8009b4c: 687b ldr r3, [r7, #4]
8009b4e: 68db ldr r3, [r3, #12]
8009b50: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8009b54: d903 bls.n 8009b5e <HAL_SPI_Init+0x94>
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
8009b56: 687b ldr r3, [r7, #4]
8009b58: 2202 movs r2, #2
8009b5a: 631a str r2, [r3, #48] ; 0x30
8009b5c: e002 b.n 8009b64 <HAL_SPI_Init+0x9a>
}
else
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
8009b5e: 687b ldr r3, [r7, #4]
8009b60: 2201 movs r2, #1
8009b62: 631a str r2, [r3, #48] ; 0x30
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
8009b64: 687b ldr r3, [r7, #4]
8009b66: 685a ldr r2, [r3, #4]
8009b68: 687b ldr r3, [r7, #4]
8009b6a: 689b ldr r3, [r3, #8]
8009b6c: 431a orrs r2, r3
8009b6e: 687b ldr r3, [r7, #4]
8009b70: 691b ldr r3, [r3, #16]
8009b72: 431a orrs r2, r3
8009b74: 687b ldr r3, [r7, #4]
8009b76: 695b ldr r3, [r3, #20]
8009b78: 431a orrs r2, r3
8009b7a: 687b ldr r3, [r7, #4]
8009b7c: 699b ldr r3, [r3, #24]
8009b7e: f403 7300 and.w r3, r3, #512 ; 0x200
8009b82: 431a orrs r2, r3
8009b84: 687b ldr r3, [r7, #4]
8009b86: 69db ldr r3, [r3, #28]
8009b88: 431a orrs r2, r3
8009b8a: 687b ldr r3, [r7, #4]
8009b8c: 6a1b ldr r3, [r3, #32]
8009b8e: ea42 0103 orr.w r1, r2, r3
8009b92: 687b ldr r3, [r7, #4]
8009b94: 6a9a ldr r2, [r3, #40] ; 0x28
8009b96: 687b ldr r3, [r7, #4]
8009b98: 681b ldr r3, [r3, #0]
8009b9a: 430a orrs r2, r1
8009b9c: 601a str r2, [r3, #0]
hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
8009b9e: 687b ldr r3, [r7, #4]
8009ba0: 699b ldr r3, [r3, #24]
8009ba2: 0c1b lsrs r3, r3, #16
8009ba4: f003 0204 and.w r2, r3, #4
8009ba8: 687b ldr r3, [r7, #4]
8009baa: 6a5b ldr r3, [r3, #36] ; 0x24
8009bac: 431a orrs r2, r3
8009bae: 687b ldr r3, [r7, #4]
8009bb0: 6b5b ldr r3, [r3, #52] ; 0x34
8009bb2: 431a orrs r2, r3
8009bb4: 687b ldr r3, [r7, #4]
8009bb6: 68db ldr r3, [r3, #12]
8009bb8: ea42 0103 orr.w r1, r2, r3
8009bbc: 687b ldr r3, [r7, #4]
8009bbe: 681b ldr r3, [r3, #0]
8009bc0: 68fa ldr r2, [r7, #12]
8009bc2: 430a orrs r2, r1
8009bc4: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8009bc6: 687b ldr r3, [r7, #4]
8009bc8: 681b ldr r3, [r3, #0]
8009bca: 69da ldr r2, [r3, #28]
8009bcc: 687b ldr r3, [r7, #4]
8009bce: 681b ldr r3, [r3, #0]
8009bd0: f422 6200 bic.w r2, r2, #2048 ; 0x800
8009bd4: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8009bd6: 687b ldr r3, [r7, #4]
8009bd8: 2200 movs r2, #0
8009bda: 661a str r2, [r3, #96] ; 0x60
hspi->State = HAL_SPI_STATE_READY;
8009bdc: 687b ldr r3, [r7, #4]
8009bde: 2201 movs r2, #1
8009be0: f883 205d strb.w r2, [r3, #93] ; 0x5d
return HAL_OK;
8009be4: 2300 movs r3, #0
}
8009be6: 4618 mov r0, r3
8009be8: 3710 adds r7, #16
8009bea: 46bd mov sp, r7
8009bec: bd80 pop {r7, pc}
08009bee <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8009bee: b580 push {r7, lr}
8009bf0: b082 sub sp, #8
8009bf2: af00 add r7, sp, #0
8009bf4: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8009bf6: 687b ldr r3, [r7, #4]
8009bf8: 2b00 cmp r3, #0
8009bfa: d101 bne.n 8009c00 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8009bfc: 2301 movs r3, #1
8009bfe: e01d b.n 8009c3c <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8009c00: 687b ldr r3, [r7, #4]
8009c02: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009c06: b2db uxtb r3, r3
8009c08: 2b00 cmp r3, #0
8009c0a: d106 bne.n 8009c1a <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8009c0c: 687b ldr r3, [r7, #4]
8009c0e: 2200 movs r2, #0
8009c10: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8009c14: 6878 ldr r0, [r7, #4]
8009c16: f7fa fbbf bl 8004398 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009c1a: 687b ldr r3, [r7, #4]
8009c1c: 2202 movs r2, #2
8009c1e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8009c22: 687b ldr r3, [r7, #4]
8009c24: 681a ldr r2, [r3, #0]
8009c26: 687b ldr r3, [r7, #4]
8009c28: 3304 adds r3, #4
8009c2a: 4619 mov r1, r3
8009c2c: 4610 mov r0, r2
8009c2e: f000 fbc3 bl 800a3b8 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009c32: 687b ldr r3, [r7, #4]
8009c34: 2201 movs r2, #1
8009c36: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009c3a: 2300 movs r3, #0
}
8009c3c: 4618 mov r0, r3
8009c3e: 3708 adds r7, #8
8009c40: 46bd mov sp, r7
8009c42: bd80 pop {r7, pc}
08009c44 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8009c44: b480 push {r7}
8009c46: b085 sub sp, #20
8009c48: af00 add r7, sp, #0
8009c4a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8009c4c: 687b ldr r3, [r7, #4]
8009c4e: 681b ldr r3, [r3, #0]
8009c50: 68da ldr r2, [r3, #12]
8009c52: 687b ldr r3, [r7, #4]
8009c54: 681b ldr r3, [r3, #0]
8009c56: f042 0201 orr.w r2, r2, #1
8009c5a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8009c5c: 687b ldr r3, [r7, #4]
8009c5e: 681b ldr r3, [r3, #0]
8009c60: 689a ldr r2, [r3, #8]
8009c62: 4b0c ldr r3, [pc, #48] ; (8009c94 <HAL_TIM_Base_Start_IT+0x50>)
8009c64: 4013 ands r3, r2
8009c66: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8009c68: 68fb ldr r3, [r7, #12]
8009c6a: 2b06 cmp r3, #6
8009c6c: d00b beq.n 8009c86 <HAL_TIM_Base_Start_IT+0x42>
8009c6e: 68fb ldr r3, [r7, #12]
8009c70: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8009c74: d007 beq.n 8009c86 <HAL_TIM_Base_Start_IT+0x42>
{
__HAL_TIM_ENABLE(htim);
8009c76: 687b ldr r3, [r7, #4]
8009c78: 681b ldr r3, [r3, #0]
8009c7a: 681a ldr r2, [r3, #0]
8009c7c: 687b ldr r3, [r7, #4]
8009c7e: 681b ldr r3, [r3, #0]
8009c80: f042 0201 orr.w r2, r2, #1
8009c84: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8009c86: 2300 movs r3, #0
}
8009c88: 4618 mov r0, r3
8009c8a: 3714 adds r7, #20
8009c8c: 46bd mov sp, r7
8009c8e: f85d 7b04 ldr.w r7, [sp], #4
8009c92: 4770 bx lr
8009c94: 00010007 .word 0x00010007
08009c98 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8009c98: b580 push {r7, lr}
8009c9a: b082 sub sp, #8
8009c9c: af00 add r7, sp, #0
8009c9e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8009ca0: 687b ldr r3, [r7, #4]
8009ca2: 2b00 cmp r3, #0
8009ca4: d101 bne.n 8009caa <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8009ca6: 2301 movs r3, #1
8009ca8: e01d b.n 8009ce6 <HAL_TIM_PWM_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8009caa: 687b ldr r3, [r7, #4]
8009cac: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8009cb0: b2db uxtb r3, r3
8009cb2: 2b00 cmp r3, #0
8009cb4: d106 bne.n 8009cc4 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8009cb6: 687b ldr r3, [r7, #4]
8009cb8: 2200 movs r2, #0
8009cba: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8009cbe: 6878 ldr r0, [r7, #4]
8009cc0: f000 f815 bl 8009cee <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8009cc4: 687b ldr r3, [r7, #4]
8009cc6: 2202 movs r2, #2
8009cc8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8009ccc: 687b ldr r3, [r7, #4]
8009cce: 681a ldr r2, [r3, #0]
8009cd0: 687b ldr r3, [r7, #4]
8009cd2: 3304 adds r3, #4
8009cd4: 4619 mov r1, r3
8009cd6: 4610 mov r0, r2
8009cd8: f000 fb6e bl 800a3b8 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8009cdc: 687b ldr r3, [r7, #4]
8009cde: 2201 movs r2, #1
8009ce0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8009ce4: 2300 movs r3, #0
}
8009ce6: 4618 mov r0, r3
8009ce8: 3708 adds r7, #8
8009cea: 46bd mov sp, r7
8009cec: bd80 pop {r7, pc}
08009cee <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8009cee: b480 push {r7}
8009cf0: b083 sub sp, #12
8009cf2: af00 add r7, sp, #0
8009cf4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8009cf6: bf00 nop
8009cf8: 370c adds r7, #12
8009cfa: 46bd mov sp, r7
8009cfc: f85d 7b04 ldr.w r7, [sp], #4
8009d00: 4770 bx lr
08009d02 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8009d02: b580 push {r7, lr}
8009d04: b082 sub sp, #8
8009d06: af00 add r7, sp, #0
8009d08: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8009d0a: 687b ldr r3, [r7, #4]
8009d0c: 681b ldr r3, [r3, #0]
8009d0e: 691b ldr r3, [r3, #16]
8009d10: f003 0302 and.w r3, r3, #2
8009d14: 2b02 cmp r3, #2
8009d16: d122 bne.n 8009d5e <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8009d18: 687b ldr r3, [r7, #4]
8009d1a: 681b ldr r3, [r3, #0]
8009d1c: 68db ldr r3, [r3, #12]
8009d1e: f003 0302 and.w r3, r3, #2
8009d22: 2b02 cmp r3, #2
8009d24: d11b bne.n 8009d5e <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8009d26: 687b ldr r3, [r7, #4]
8009d28: 681b ldr r3, [r3, #0]
8009d2a: f06f 0202 mvn.w r2, #2
8009d2e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8009d30: 687b ldr r3, [r7, #4]
8009d32: 2201 movs r2, #1
8009d34: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8009d36: 687b ldr r3, [r7, #4]
8009d38: 681b ldr r3, [r3, #0]
8009d3a: 699b ldr r3, [r3, #24]
8009d3c: f003 0303 and.w r3, r3, #3
8009d40: 2b00 cmp r3, #0
8009d42: d003 beq.n 8009d4c <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009d44: 6878 ldr r0, [r7, #4]
8009d46: f000 fb19 bl 800a37c <HAL_TIM_IC_CaptureCallback>
8009d4a: e005 b.n 8009d58 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009d4c: 6878 ldr r0, [r7, #4]
8009d4e: f000 fb0b bl 800a368 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009d52: 6878 ldr r0, [r7, #4]
8009d54: f000 fb1c bl 800a390 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009d58: 687b ldr r3, [r7, #4]
8009d5a: 2200 movs r2, #0
8009d5c: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8009d5e: 687b ldr r3, [r7, #4]
8009d60: 681b ldr r3, [r3, #0]
8009d62: 691b ldr r3, [r3, #16]
8009d64: f003 0304 and.w r3, r3, #4
8009d68: 2b04 cmp r3, #4
8009d6a: d122 bne.n 8009db2 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8009d6c: 687b ldr r3, [r7, #4]
8009d6e: 681b ldr r3, [r3, #0]
8009d70: 68db ldr r3, [r3, #12]
8009d72: f003 0304 and.w r3, r3, #4
8009d76: 2b04 cmp r3, #4
8009d78: d11b bne.n 8009db2 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8009d7a: 687b ldr r3, [r7, #4]
8009d7c: 681b ldr r3, [r3, #0]
8009d7e: f06f 0204 mvn.w r2, #4
8009d82: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8009d84: 687b ldr r3, [r7, #4]
8009d86: 2202 movs r2, #2
8009d88: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8009d8a: 687b ldr r3, [r7, #4]
8009d8c: 681b ldr r3, [r3, #0]
8009d8e: 699b ldr r3, [r3, #24]
8009d90: f403 7340 and.w r3, r3, #768 ; 0x300
8009d94: 2b00 cmp r3, #0
8009d96: d003 beq.n 8009da0 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009d98: 6878 ldr r0, [r7, #4]
8009d9a: f000 faef bl 800a37c <HAL_TIM_IC_CaptureCallback>
8009d9e: e005 b.n 8009dac <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009da0: 6878 ldr r0, [r7, #4]
8009da2: f000 fae1 bl 800a368 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009da6: 6878 ldr r0, [r7, #4]
8009da8: f000 faf2 bl 800a390 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009dac: 687b ldr r3, [r7, #4]
8009dae: 2200 movs r2, #0
8009db0: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8009db2: 687b ldr r3, [r7, #4]
8009db4: 681b ldr r3, [r3, #0]
8009db6: 691b ldr r3, [r3, #16]
8009db8: f003 0308 and.w r3, r3, #8
8009dbc: 2b08 cmp r3, #8
8009dbe: d122 bne.n 8009e06 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8009dc0: 687b ldr r3, [r7, #4]
8009dc2: 681b ldr r3, [r3, #0]
8009dc4: 68db ldr r3, [r3, #12]
8009dc6: f003 0308 and.w r3, r3, #8
8009dca: 2b08 cmp r3, #8
8009dcc: d11b bne.n 8009e06 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8009dce: 687b ldr r3, [r7, #4]
8009dd0: 681b ldr r3, [r3, #0]
8009dd2: f06f 0208 mvn.w r2, #8
8009dd6: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8009dd8: 687b ldr r3, [r7, #4]
8009dda: 2204 movs r2, #4
8009ddc: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8009dde: 687b ldr r3, [r7, #4]
8009de0: 681b ldr r3, [r3, #0]
8009de2: 69db ldr r3, [r3, #28]
8009de4: f003 0303 and.w r3, r3, #3
8009de8: 2b00 cmp r3, #0
8009dea: d003 beq.n 8009df4 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009dec: 6878 ldr r0, [r7, #4]
8009dee: f000 fac5 bl 800a37c <HAL_TIM_IC_CaptureCallback>
8009df2: e005 b.n 8009e00 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009df4: 6878 ldr r0, [r7, #4]
8009df6: f000 fab7 bl 800a368 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009dfa: 6878 ldr r0, [r7, #4]
8009dfc: f000 fac8 bl 800a390 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009e00: 687b ldr r3, [r7, #4]
8009e02: 2200 movs r2, #0
8009e04: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8009e06: 687b ldr r3, [r7, #4]
8009e08: 681b ldr r3, [r3, #0]
8009e0a: 691b ldr r3, [r3, #16]
8009e0c: f003 0310 and.w r3, r3, #16
8009e10: 2b10 cmp r3, #16
8009e12: d122 bne.n 8009e5a <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8009e14: 687b ldr r3, [r7, #4]
8009e16: 681b ldr r3, [r3, #0]
8009e18: 68db ldr r3, [r3, #12]
8009e1a: f003 0310 and.w r3, r3, #16
8009e1e: 2b10 cmp r3, #16
8009e20: d11b bne.n 8009e5a <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8009e22: 687b ldr r3, [r7, #4]
8009e24: 681b ldr r3, [r3, #0]
8009e26: f06f 0210 mvn.w r2, #16
8009e2a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8009e2c: 687b ldr r3, [r7, #4]
8009e2e: 2208 movs r2, #8
8009e30: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8009e32: 687b ldr r3, [r7, #4]
8009e34: 681b ldr r3, [r3, #0]
8009e36: 69db ldr r3, [r3, #28]
8009e38: f403 7340 and.w r3, r3, #768 ; 0x300
8009e3c: 2b00 cmp r3, #0
8009e3e: d003 beq.n 8009e48 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8009e40: 6878 ldr r0, [r7, #4]
8009e42: f000 fa9b bl 800a37c <HAL_TIM_IC_CaptureCallback>
8009e46: e005 b.n 8009e54 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8009e48: 6878 ldr r0, [r7, #4]
8009e4a: f000 fa8d bl 800a368 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8009e4e: 6878 ldr r0, [r7, #4]
8009e50: f000 fa9e bl 800a390 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8009e54: 687b ldr r3, [r7, #4]
8009e56: 2200 movs r2, #0
8009e58: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8009e5a: 687b ldr r3, [r7, #4]
8009e5c: 681b ldr r3, [r3, #0]
8009e5e: 691b ldr r3, [r3, #16]
8009e60: f003 0301 and.w r3, r3, #1
8009e64: 2b01 cmp r3, #1
8009e66: d10e bne.n 8009e86 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8009e68: 687b ldr r3, [r7, #4]
8009e6a: 681b ldr r3, [r3, #0]
8009e6c: 68db ldr r3, [r3, #12]
8009e6e: f003 0301 and.w r3, r3, #1
8009e72: 2b01 cmp r3, #1
8009e74: d107 bne.n 8009e86 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8009e76: 687b ldr r3, [r7, #4]
8009e78: 681b ldr r3, [r3, #0]
8009e7a: f06f 0201 mvn.w r2, #1
8009e7e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8009e80: 6878 ldr r0, [r7, #4]
8009e82: f7f8 fbc1 bl 8002608 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8009e86: 687b ldr r3, [r7, #4]
8009e88: 681b ldr r3, [r3, #0]
8009e8a: 691b ldr r3, [r3, #16]
8009e8c: f003 0380 and.w r3, r3, #128 ; 0x80
8009e90: 2b80 cmp r3, #128 ; 0x80
8009e92: d10e bne.n 8009eb2 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009e94: 687b ldr r3, [r7, #4]
8009e96: 681b ldr r3, [r3, #0]
8009e98: 68db ldr r3, [r3, #12]
8009e9a: f003 0380 and.w r3, r3, #128 ; 0x80
8009e9e: 2b80 cmp r3, #128 ; 0x80
8009ea0: d107 bne.n 8009eb2 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8009ea2: 687b ldr r3, [r7, #4]
8009ea4: 681b ldr r3, [r3, #0]
8009ea6: f06f 0280 mvn.w r2, #128 ; 0x80
8009eaa: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8009eac: 6878 ldr r0, [r7, #4]
8009eae: f000 ffb9 bl 800ae24 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8009eb2: 687b ldr r3, [r7, #4]
8009eb4: 681b ldr r3, [r3, #0]
8009eb6: 691b ldr r3, [r3, #16]
8009eb8: f403 7380 and.w r3, r3, #256 ; 0x100
8009ebc: f5b3 7f80 cmp.w r3, #256 ; 0x100
8009ec0: d10e bne.n 8009ee0 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8009ec2: 687b ldr r3, [r7, #4]
8009ec4: 681b ldr r3, [r3, #0]
8009ec6: 68db ldr r3, [r3, #12]
8009ec8: f003 0380 and.w r3, r3, #128 ; 0x80
8009ecc: 2b80 cmp r3, #128 ; 0x80
8009ece: d107 bne.n 8009ee0 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8009ed0: 687b ldr r3, [r7, #4]
8009ed2: 681b ldr r3, [r3, #0]
8009ed4: f46f 7280 mvn.w r2, #256 ; 0x100
8009ed8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8009eda: 6878 ldr r0, [r7, #4]
8009edc: f000 ffac bl 800ae38 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8009ee0: 687b ldr r3, [r7, #4]
8009ee2: 681b ldr r3, [r3, #0]
8009ee4: 691b ldr r3, [r3, #16]
8009ee6: f003 0340 and.w r3, r3, #64 ; 0x40
8009eea: 2b40 cmp r3, #64 ; 0x40
8009eec: d10e bne.n 8009f0c <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8009eee: 687b ldr r3, [r7, #4]
8009ef0: 681b ldr r3, [r3, #0]
8009ef2: 68db ldr r3, [r3, #12]
8009ef4: f003 0340 and.w r3, r3, #64 ; 0x40
8009ef8: 2b40 cmp r3, #64 ; 0x40
8009efa: d107 bne.n 8009f0c <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8009efc: 687b ldr r3, [r7, #4]
8009efe: 681b ldr r3, [r3, #0]
8009f00: f06f 0240 mvn.w r2, #64 ; 0x40
8009f04: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8009f06: 6878 ldr r0, [r7, #4]
8009f08: f000 fa4c bl 800a3a4 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8009f0c: 687b ldr r3, [r7, #4]
8009f0e: 681b ldr r3, [r3, #0]
8009f10: 691b ldr r3, [r3, #16]
8009f12: f003 0320 and.w r3, r3, #32
8009f16: 2b20 cmp r3, #32
8009f18: d10e bne.n 8009f38 <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8009f1a: 687b ldr r3, [r7, #4]
8009f1c: 681b ldr r3, [r3, #0]
8009f1e: 68db ldr r3, [r3, #12]
8009f20: f003 0320 and.w r3, r3, #32
8009f24: 2b20 cmp r3, #32
8009f26: d107 bne.n 8009f38 <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8009f28: 687b ldr r3, [r7, #4]
8009f2a: 681b ldr r3, [r3, #0]
8009f2c: f06f 0220 mvn.w r2, #32
8009f30: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8009f32: 6878 ldr r0, [r7, #4]
8009f34: f000 ff6c bl 800ae10 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8009f38: bf00 nop
8009f3a: 3708 adds r7, #8
8009f3c: 46bd mov sp, r7
8009f3e: bd80 pop {r7, pc}
08009f40 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8009f40: b580 push {r7, lr}
8009f42: b084 sub sp, #16
8009f44: af00 add r7, sp, #0
8009f46: 60f8 str r0, [r7, #12]
8009f48: 60b9 str r1, [r7, #8]
8009f4a: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8009f4c: 68fb ldr r3, [r7, #12]
8009f4e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009f52: 2b01 cmp r3, #1
8009f54: d101 bne.n 8009f5a <HAL_TIM_PWM_ConfigChannel+0x1a>
8009f56: 2302 movs r3, #2
8009f58: e105 b.n 800a166 <HAL_TIM_PWM_ConfigChannel+0x226>
8009f5a: 68fb ldr r3, [r7, #12]
8009f5c: 2201 movs r2, #1
8009f5e: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8009f62: 68fb ldr r3, [r7, #12]
8009f64: 2202 movs r2, #2
8009f66: f883 203d strb.w r2, [r3, #61] ; 0x3d
switch (Channel)
8009f6a: 687b ldr r3, [r7, #4]
8009f6c: 2b14 cmp r3, #20
8009f6e: f200 80f0 bhi.w 800a152 <HAL_TIM_PWM_ConfigChannel+0x212>
8009f72: a201 add r2, pc, #4 ; (adr r2, 8009f78 <HAL_TIM_PWM_ConfigChannel+0x38>)
8009f74: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009f78: 08009fcd .word 0x08009fcd
8009f7c: 0800a153 .word 0x0800a153
8009f80: 0800a153 .word 0x0800a153
8009f84: 0800a153 .word 0x0800a153
8009f88: 0800a00d .word 0x0800a00d
8009f8c: 0800a153 .word 0x0800a153
8009f90: 0800a153 .word 0x0800a153
8009f94: 0800a153 .word 0x0800a153
8009f98: 0800a04f .word 0x0800a04f
8009f9c: 0800a153 .word 0x0800a153
8009fa0: 0800a153 .word 0x0800a153
8009fa4: 0800a153 .word 0x0800a153
8009fa8: 0800a08f .word 0x0800a08f
8009fac: 0800a153 .word 0x0800a153
8009fb0: 0800a153 .word 0x0800a153
8009fb4: 0800a153 .word 0x0800a153
8009fb8: 0800a0d1 .word 0x0800a0d1
8009fbc: 0800a153 .word 0x0800a153
8009fc0: 0800a153 .word 0x0800a153
8009fc4: 0800a153 .word 0x0800a153
8009fc8: 0800a111 .word 0x0800a111
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8009fcc: 68fb ldr r3, [r7, #12]
8009fce: 681b ldr r3, [r3, #0]
8009fd0: 68b9 ldr r1, [r7, #8]
8009fd2: 4618 mov r0, r3
8009fd4: f000 fa90 bl 800a4f8 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8009fd8: 68fb ldr r3, [r7, #12]
8009fda: 681b ldr r3, [r3, #0]
8009fdc: 699a ldr r2, [r3, #24]
8009fde: 68fb ldr r3, [r7, #12]
8009fe0: 681b ldr r3, [r3, #0]
8009fe2: f042 0208 orr.w r2, r2, #8
8009fe6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8009fe8: 68fb ldr r3, [r7, #12]
8009fea: 681b ldr r3, [r3, #0]
8009fec: 699a ldr r2, [r3, #24]
8009fee: 68fb ldr r3, [r7, #12]
8009ff0: 681b ldr r3, [r3, #0]
8009ff2: f022 0204 bic.w r2, r2, #4
8009ff6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8009ff8: 68fb ldr r3, [r7, #12]
8009ffa: 681b ldr r3, [r3, #0]
8009ffc: 6999 ldr r1, [r3, #24]
8009ffe: 68bb ldr r3, [r7, #8]
800a000: 691a ldr r2, [r3, #16]
800a002: 68fb ldr r3, [r7, #12]
800a004: 681b ldr r3, [r3, #0]
800a006: 430a orrs r2, r1
800a008: 619a str r2, [r3, #24]
break;
800a00a: e0a3 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
800a00c: 68fb ldr r3, [r7, #12]
800a00e: 681b ldr r3, [r3, #0]
800a010: 68b9 ldr r1, [r7, #8]
800a012: 4618 mov r0, r3
800a014: f000 fae2 bl 800a5dc <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
800a018: 68fb ldr r3, [r7, #12]
800a01a: 681b ldr r3, [r3, #0]
800a01c: 699a ldr r2, [r3, #24]
800a01e: 68fb ldr r3, [r7, #12]
800a020: 681b ldr r3, [r3, #0]
800a022: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a026: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
800a028: 68fb ldr r3, [r7, #12]
800a02a: 681b ldr r3, [r3, #0]
800a02c: 699a ldr r2, [r3, #24]
800a02e: 68fb ldr r3, [r7, #12]
800a030: 681b ldr r3, [r3, #0]
800a032: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a036: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
800a038: 68fb ldr r3, [r7, #12]
800a03a: 681b ldr r3, [r3, #0]
800a03c: 6999 ldr r1, [r3, #24]
800a03e: 68bb ldr r3, [r7, #8]
800a040: 691b ldr r3, [r3, #16]
800a042: 021a lsls r2, r3, #8
800a044: 68fb ldr r3, [r7, #12]
800a046: 681b ldr r3, [r3, #0]
800a048: 430a orrs r2, r1
800a04a: 619a str r2, [r3, #24]
break;
800a04c: e082 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
800a04e: 68fb ldr r3, [r7, #12]
800a050: 681b ldr r3, [r3, #0]
800a052: 68b9 ldr r1, [r7, #8]
800a054: 4618 mov r0, r3
800a056: f000 fb39 bl 800a6cc <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800a05a: 68fb ldr r3, [r7, #12]
800a05c: 681b ldr r3, [r3, #0]
800a05e: 69da ldr r2, [r3, #28]
800a060: 68fb ldr r3, [r7, #12]
800a062: 681b ldr r3, [r3, #0]
800a064: f042 0208 orr.w r2, r2, #8
800a068: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800a06a: 68fb ldr r3, [r7, #12]
800a06c: 681b ldr r3, [r3, #0]
800a06e: 69da ldr r2, [r3, #28]
800a070: 68fb ldr r3, [r7, #12]
800a072: 681b ldr r3, [r3, #0]
800a074: f022 0204 bic.w r2, r2, #4
800a078: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800a07a: 68fb ldr r3, [r7, #12]
800a07c: 681b ldr r3, [r3, #0]
800a07e: 69d9 ldr r1, [r3, #28]
800a080: 68bb ldr r3, [r7, #8]
800a082: 691a ldr r2, [r3, #16]
800a084: 68fb ldr r3, [r7, #12]
800a086: 681b ldr r3, [r3, #0]
800a088: 430a orrs r2, r1
800a08a: 61da str r2, [r3, #28]
break;
800a08c: e062 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800a08e: 68fb ldr r3, [r7, #12]
800a090: 681b ldr r3, [r3, #0]
800a092: 68b9 ldr r1, [r7, #8]
800a094: 4618 mov r0, r3
800a096: f000 fb8f bl 800a7b8 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800a09a: 68fb ldr r3, [r7, #12]
800a09c: 681b ldr r3, [r3, #0]
800a09e: 69da ldr r2, [r3, #28]
800a0a0: 68fb ldr r3, [r7, #12]
800a0a2: 681b ldr r3, [r3, #0]
800a0a4: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a0a8: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800a0aa: 68fb ldr r3, [r7, #12]
800a0ac: 681b ldr r3, [r3, #0]
800a0ae: 69da ldr r2, [r3, #28]
800a0b0: 68fb ldr r3, [r7, #12]
800a0b2: 681b ldr r3, [r3, #0]
800a0b4: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a0b8: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800a0ba: 68fb ldr r3, [r7, #12]
800a0bc: 681b ldr r3, [r3, #0]
800a0be: 69d9 ldr r1, [r3, #28]
800a0c0: 68bb ldr r3, [r7, #8]
800a0c2: 691b ldr r3, [r3, #16]
800a0c4: 021a lsls r2, r3, #8
800a0c6: 68fb ldr r3, [r7, #12]
800a0c8: 681b ldr r3, [r3, #0]
800a0ca: 430a orrs r2, r1
800a0cc: 61da str r2, [r3, #28]
break;
800a0ce: e041 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
800a0d0: 68fb ldr r3, [r7, #12]
800a0d2: 681b ldr r3, [r3, #0]
800a0d4: 68b9 ldr r1, [r7, #8]
800a0d6: 4618 mov r0, r3
800a0d8: f000 fbc6 bl 800a868 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
800a0dc: 68fb ldr r3, [r7, #12]
800a0de: 681b ldr r3, [r3, #0]
800a0e0: 6d5a ldr r2, [r3, #84] ; 0x54
800a0e2: 68fb ldr r3, [r7, #12]
800a0e4: 681b ldr r3, [r3, #0]
800a0e6: f042 0208 orr.w r2, r2, #8
800a0ea: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
800a0ec: 68fb ldr r3, [r7, #12]
800a0ee: 681b ldr r3, [r3, #0]
800a0f0: 6d5a ldr r2, [r3, #84] ; 0x54
800a0f2: 68fb ldr r3, [r7, #12]
800a0f4: 681b ldr r3, [r3, #0]
800a0f6: f022 0204 bic.w r2, r2, #4
800a0fa: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
800a0fc: 68fb ldr r3, [r7, #12]
800a0fe: 681b ldr r3, [r3, #0]
800a100: 6d59 ldr r1, [r3, #84] ; 0x54
800a102: 68bb ldr r3, [r7, #8]
800a104: 691a ldr r2, [r3, #16]
800a106: 68fb ldr r3, [r7, #12]
800a108: 681b ldr r3, [r3, #0]
800a10a: 430a orrs r2, r1
800a10c: 655a str r2, [r3, #84] ; 0x54
break;
800a10e: e021 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
800a110: 68fb ldr r3, [r7, #12]
800a112: 681b ldr r3, [r3, #0]
800a114: 68b9 ldr r1, [r7, #8]
800a116: 4618 mov r0, r3
800a118: f000 fbf8 bl 800a90c <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
800a11c: 68fb ldr r3, [r7, #12]
800a11e: 681b ldr r3, [r3, #0]
800a120: 6d5a ldr r2, [r3, #84] ; 0x54
800a122: 68fb ldr r3, [r7, #12]
800a124: 681b ldr r3, [r3, #0]
800a126: f442 6200 orr.w r2, r2, #2048 ; 0x800
800a12a: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800a12c: 68fb ldr r3, [r7, #12]
800a12e: 681b ldr r3, [r3, #0]
800a130: 6d5a ldr r2, [r3, #84] ; 0x54
800a132: 68fb ldr r3, [r7, #12]
800a134: 681b ldr r3, [r3, #0]
800a136: f422 6280 bic.w r2, r2, #1024 ; 0x400
800a13a: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
800a13c: 68fb ldr r3, [r7, #12]
800a13e: 681b ldr r3, [r3, #0]
800a140: 6d59 ldr r1, [r3, #84] ; 0x54
800a142: 68bb ldr r3, [r7, #8]
800a144: 691b ldr r3, [r3, #16]
800a146: 021a lsls r2, r3, #8
800a148: 68fb ldr r3, [r7, #12]
800a14a: 681b ldr r3, [r3, #0]
800a14c: 430a orrs r2, r1
800a14e: 655a str r2, [r3, #84] ; 0x54
break;
800a150: e000 b.n 800a154 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
break;
800a152: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800a154: 68fb ldr r3, [r7, #12]
800a156: 2201 movs r2, #1
800a158: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a15c: 68fb ldr r3, [r7, #12]
800a15e: 2200 movs r2, #0
800a160: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a164: 2300 movs r3, #0
}
800a166: 4618 mov r0, r3
800a168: 3710 adds r7, #16
800a16a: 46bd mov sp, r7
800a16c: bd80 pop {r7, pc}
800a16e: bf00 nop
0800a170 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800a170: b580 push {r7, lr}
800a172: b084 sub sp, #16
800a174: af00 add r7, sp, #0
800a176: 6078 str r0, [r7, #4]
800a178: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800a17a: 687b ldr r3, [r7, #4]
800a17c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a180: 2b01 cmp r3, #1
800a182: d101 bne.n 800a188 <HAL_TIM_ConfigClockSource+0x18>
800a184: 2302 movs r3, #2
800a186: e0a6 b.n 800a2d6 <HAL_TIM_ConfigClockSource+0x166>
800a188: 687b ldr r3, [r7, #4]
800a18a: 2201 movs r2, #1
800a18c: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a190: 687b ldr r3, [r7, #4]
800a192: 2202 movs r2, #2
800a194: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
800a198: 687b ldr r3, [r7, #4]
800a19a: 681b ldr r3, [r3, #0]
800a19c: 689b ldr r3, [r3, #8]
800a19e: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
800a1a0: 68fa ldr r2, [r7, #12]
800a1a2: 4b4f ldr r3, [pc, #316] ; (800a2e0 <HAL_TIM_ConfigClockSource+0x170>)
800a1a4: 4013 ands r3, r2
800a1a6: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800a1a8: 68fb ldr r3, [r7, #12]
800a1aa: f423 437f bic.w r3, r3, #65280 ; 0xff00
800a1ae: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a1b0: 687b ldr r3, [r7, #4]
800a1b2: 681b ldr r3, [r3, #0]
800a1b4: 68fa ldr r2, [r7, #12]
800a1b6: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
800a1b8: 683b ldr r3, [r7, #0]
800a1ba: 681b ldr r3, [r3, #0]
800a1bc: 2b40 cmp r3, #64 ; 0x40
800a1be: d067 beq.n 800a290 <HAL_TIM_ConfigClockSource+0x120>
800a1c0: 2b40 cmp r3, #64 ; 0x40
800a1c2: d80b bhi.n 800a1dc <HAL_TIM_ConfigClockSource+0x6c>
800a1c4: 2b10 cmp r3, #16
800a1c6: d073 beq.n 800a2b0 <HAL_TIM_ConfigClockSource+0x140>
800a1c8: 2b10 cmp r3, #16
800a1ca: d802 bhi.n 800a1d2 <HAL_TIM_ConfigClockSource+0x62>
800a1cc: 2b00 cmp r3, #0
800a1ce: d06f beq.n 800a2b0 <HAL_TIM_ConfigClockSource+0x140>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
800a1d0: e078 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1d2: 2b20 cmp r3, #32
800a1d4: d06c beq.n 800a2b0 <HAL_TIM_ConfigClockSource+0x140>
800a1d6: 2b30 cmp r3, #48 ; 0x30
800a1d8: d06a beq.n 800a2b0 <HAL_TIM_ConfigClockSource+0x140>
break;
800a1da: e073 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1dc: 2b70 cmp r3, #112 ; 0x70
800a1de: d00d beq.n 800a1fc <HAL_TIM_ConfigClockSource+0x8c>
800a1e0: 2b70 cmp r3, #112 ; 0x70
800a1e2: d804 bhi.n 800a1ee <HAL_TIM_ConfigClockSource+0x7e>
800a1e4: 2b50 cmp r3, #80 ; 0x50
800a1e6: d033 beq.n 800a250 <HAL_TIM_ConfigClockSource+0xe0>
800a1e8: 2b60 cmp r3, #96 ; 0x60
800a1ea: d041 beq.n 800a270 <HAL_TIM_ConfigClockSource+0x100>
break;
800a1ec: e06a b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800a1ee: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a1f2: d066 beq.n 800a2c2 <HAL_TIM_ConfigClockSource+0x152>
800a1f4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800a1f8: d017 beq.n 800a22a <HAL_TIM_ConfigClockSource+0xba>
break;
800a1fa: e063 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
800a1fc: 687b ldr r3, [r7, #4]
800a1fe: 6818 ldr r0, [r3, #0]
800a200: 683b ldr r3, [r7, #0]
800a202: 6899 ldr r1, [r3, #8]
800a204: 683b ldr r3, [r7, #0]
800a206: 685a ldr r2, [r3, #4]
800a208: 683b ldr r3, [r7, #0]
800a20a: 68db ldr r3, [r3, #12]
800a20c: f000 fcd4 bl 800abb8 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
800a210: 687b ldr r3, [r7, #4]
800a212: 681b ldr r3, [r3, #0]
800a214: 689b ldr r3, [r3, #8]
800a216: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
800a218: 68fb ldr r3, [r7, #12]
800a21a: f043 0377 orr.w r3, r3, #119 ; 0x77
800a21e: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
800a220: 687b ldr r3, [r7, #4]
800a222: 681b ldr r3, [r3, #0]
800a224: 68fa ldr r2, [r7, #12]
800a226: 609a str r2, [r3, #8]
break;
800a228: e04c b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
800a22a: 687b ldr r3, [r7, #4]
800a22c: 6818 ldr r0, [r3, #0]
800a22e: 683b ldr r3, [r7, #0]
800a230: 6899 ldr r1, [r3, #8]
800a232: 683b ldr r3, [r7, #0]
800a234: 685a ldr r2, [r3, #4]
800a236: 683b ldr r3, [r7, #0]
800a238: 68db ldr r3, [r3, #12]
800a23a: f000 fcbd bl 800abb8 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
800a23e: 687b ldr r3, [r7, #4]
800a240: 681b ldr r3, [r3, #0]
800a242: 689a ldr r2, [r3, #8]
800a244: 687b ldr r3, [r7, #4]
800a246: 681b ldr r3, [r3, #0]
800a248: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800a24c: 609a str r2, [r3, #8]
break;
800a24e: e039 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
800a250: 687b ldr r3, [r7, #4]
800a252: 6818 ldr r0, [r3, #0]
800a254: 683b ldr r3, [r7, #0]
800a256: 6859 ldr r1, [r3, #4]
800a258: 683b ldr r3, [r7, #0]
800a25a: 68db ldr r3, [r3, #12]
800a25c: 461a mov r2, r3
800a25e: f000 fc31 bl 800aac4 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
800a262: 687b ldr r3, [r7, #4]
800a264: 681b ldr r3, [r3, #0]
800a266: 2150 movs r1, #80 ; 0x50
800a268: 4618 mov r0, r3
800a26a: f000 fc8a bl 800ab82 <TIM_ITRx_SetConfig>
break;
800a26e: e029 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI2_ConfigInputStage(htim->Instance,
800a270: 687b ldr r3, [r7, #4]
800a272: 6818 ldr r0, [r3, #0]
800a274: 683b ldr r3, [r7, #0]
800a276: 6859 ldr r1, [r3, #4]
800a278: 683b ldr r3, [r7, #0]
800a27a: 68db ldr r3, [r3, #12]
800a27c: 461a mov r2, r3
800a27e: f000 fc50 bl 800ab22 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
800a282: 687b ldr r3, [r7, #4]
800a284: 681b ldr r3, [r3, #0]
800a286: 2160 movs r1, #96 ; 0x60
800a288: 4618 mov r0, r3
800a28a: f000 fc7a bl 800ab82 <TIM_ITRx_SetConfig>
break;
800a28e: e019 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
800a290: 687b ldr r3, [r7, #4]
800a292: 6818 ldr r0, [r3, #0]
800a294: 683b ldr r3, [r7, #0]
800a296: 6859 ldr r1, [r3, #4]
800a298: 683b ldr r3, [r7, #0]
800a29a: 68db ldr r3, [r3, #12]
800a29c: 461a mov r2, r3
800a29e: f000 fc11 bl 800aac4 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
800a2a2: 687b ldr r3, [r7, #4]
800a2a4: 681b ldr r3, [r3, #0]
800a2a6: 2140 movs r1, #64 ; 0x40
800a2a8: 4618 mov r0, r3
800a2aa: f000 fc6a bl 800ab82 <TIM_ITRx_SetConfig>
break;
800a2ae: e009 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
800a2b0: 687b ldr r3, [r7, #4]
800a2b2: 681a ldr r2, [r3, #0]
800a2b4: 683b ldr r3, [r7, #0]
800a2b6: 681b ldr r3, [r3, #0]
800a2b8: 4619 mov r1, r3
800a2ba: 4610 mov r0, r2
800a2bc: f000 fc61 bl 800ab82 <TIM_ITRx_SetConfig>
break;
800a2c0: e000 b.n 800a2c4 <HAL_TIM_ConfigClockSource+0x154>
break;
800a2c2: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
800a2c4: 687b ldr r3, [r7, #4]
800a2c6: 2201 movs r2, #1
800a2c8: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a2cc: 687b ldr r3, [r7, #4]
800a2ce: 2200 movs r2, #0
800a2d0: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a2d4: 2300 movs r3, #0
}
800a2d6: 4618 mov r0, r3
800a2d8: 3710 adds r7, #16
800a2da: 46bd mov sp, r7
800a2dc: bd80 pop {r7, pc}
800a2de: bf00 nop
800a2e0: fffeff88 .word 0xfffeff88
0800a2e4 <HAL_TIM_SlaveConfigSynchro>:
* timer input or external trigger input) and the Slave mode
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a2e4: b580 push {r7, lr}
800a2e6: b082 sub sp, #8
800a2e8: af00 add r7, sp, #0
800a2ea: 6078 str r0, [r7, #4]
800a2ec: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
__HAL_LOCK(htim);
800a2ee: 687b ldr r3, [r7, #4]
800a2f0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800a2f4: 2b01 cmp r3, #1
800a2f6: d101 bne.n 800a2fc <HAL_TIM_SlaveConfigSynchro+0x18>
800a2f8: 2302 movs r3, #2
800a2fa: e031 b.n 800a360 <HAL_TIM_SlaveConfigSynchro+0x7c>
800a2fc: 687b ldr r3, [r7, #4]
800a2fe: 2201 movs r2, #1
800a300: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
800a304: 687b ldr r3, [r7, #4]
800a306: 2202 movs r2, #2
800a308: f883 203d strb.w r2, [r3, #61] ; 0x3d
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
800a30c: 6839 ldr r1, [r7, #0]
800a30e: 6878 ldr r0, [r7, #4]
800a310: f000 fb50 bl 800a9b4 <TIM_SlaveTimer_SetConfig>
800a314: 4603 mov r3, r0
800a316: 2b00 cmp r3, #0
800a318: d009 beq.n 800a32e <HAL_TIM_SlaveConfigSynchro+0x4a>
{
htim->State = HAL_TIM_STATE_READY;
800a31a: 687b ldr r3, [r7, #4]
800a31c: 2201 movs r2, #1
800a31e: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a322: 687b ldr r3, [r7, #4]
800a324: 2200 movs r2, #0
800a326: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
800a32a: 2301 movs r3, #1
800a32c: e018 b.n 800a360 <HAL_TIM_SlaveConfigSynchro+0x7c>
}
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
800a32e: 687b ldr r3, [r7, #4]
800a330: 681b ldr r3, [r3, #0]
800a332: 68da ldr r2, [r3, #12]
800a334: 687b ldr r3, [r7, #4]
800a336: 681b ldr r3, [r3, #0]
800a338: f022 0240 bic.w r2, r2, #64 ; 0x40
800a33c: 60da str r2, [r3, #12]
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
800a33e: 687b ldr r3, [r7, #4]
800a340: 681b ldr r3, [r3, #0]
800a342: 68da ldr r2, [r3, #12]
800a344: 687b ldr r3, [r7, #4]
800a346: 681b ldr r3, [r3, #0]
800a348: f422 4280 bic.w r2, r2, #16384 ; 0x4000
800a34c: 60da str r2, [r3, #12]
htim->State = HAL_TIM_STATE_READY;
800a34e: 687b ldr r3, [r7, #4]
800a350: 2201 movs r2, #1
800a352: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800a356: 687b ldr r3, [r7, #4]
800a358: 2200 movs r2, #0
800a35a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800a35e: 2300 movs r3, #0
}
800a360: 4618 mov r0, r3
800a362: 3708 adds r7, #8
800a364: 46bd mov sp, r7
800a366: bd80 pop {r7, pc}
0800a368 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800a368: b480 push {r7}
800a36a: b083 sub sp, #12
800a36c: af00 add r7, sp, #0
800a36e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800a370: bf00 nop
800a372: 370c adds r7, #12
800a374: 46bd mov sp, r7
800a376: f85d 7b04 ldr.w r7, [sp], #4
800a37a: 4770 bx lr
0800a37c <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800a37c: b480 push {r7}
800a37e: b083 sub sp, #12
800a380: af00 add r7, sp, #0
800a382: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
800a384: bf00 nop
800a386: 370c adds r7, #12
800a388: 46bd mov sp, r7
800a38a: f85d 7b04 ldr.w r7, [sp], #4
800a38e: 4770 bx lr
0800a390 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800a390: b480 push {r7}
800a392: b083 sub sp, #12
800a394: af00 add r7, sp, #0
800a396: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
800a398: bf00 nop
800a39a: 370c adds r7, #12
800a39c: 46bd mov sp, r7
800a39e: f85d 7b04 ldr.w r7, [sp], #4
800a3a2: 4770 bx lr
0800a3a4 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
800a3a4: b480 push {r7}
800a3a6: b083 sub sp, #12
800a3a8: af00 add r7, sp, #0
800a3aa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800a3ac: bf00 nop
800a3ae: 370c adds r7, #12
800a3b0: 46bd mov sp, r7
800a3b2: f85d 7b04 ldr.w r7, [sp], #4
800a3b6: 4770 bx lr
0800a3b8 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
800a3b8: b480 push {r7}
800a3ba: b085 sub sp, #20
800a3bc: af00 add r7, sp, #0
800a3be: 6078 str r0, [r7, #4]
800a3c0: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
800a3c2: 687b ldr r3, [r7, #4]
800a3c4: 681b ldr r3, [r3, #0]
800a3c6: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
800a3c8: 687b ldr r3, [r7, #4]
800a3ca: 4a40 ldr r2, [pc, #256] ; (800a4cc <TIM_Base_SetConfig+0x114>)
800a3cc: 4293 cmp r3, r2
800a3ce: d013 beq.n 800a3f8 <TIM_Base_SetConfig+0x40>
800a3d0: 687b ldr r3, [r7, #4]
800a3d2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a3d6: d00f beq.n 800a3f8 <TIM_Base_SetConfig+0x40>
800a3d8: 687b ldr r3, [r7, #4]
800a3da: 4a3d ldr r2, [pc, #244] ; (800a4d0 <TIM_Base_SetConfig+0x118>)
800a3dc: 4293 cmp r3, r2
800a3de: d00b beq.n 800a3f8 <TIM_Base_SetConfig+0x40>
800a3e0: 687b ldr r3, [r7, #4]
800a3e2: 4a3c ldr r2, [pc, #240] ; (800a4d4 <TIM_Base_SetConfig+0x11c>)
800a3e4: 4293 cmp r3, r2
800a3e6: d007 beq.n 800a3f8 <TIM_Base_SetConfig+0x40>
800a3e8: 687b ldr r3, [r7, #4]
800a3ea: 4a3b ldr r2, [pc, #236] ; (800a4d8 <TIM_Base_SetConfig+0x120>)
800a3ec: 4293 cmp r3, r2
800a3ee: d003 beq.n 800a3f8 <TIM_Base_SetConfig+0x40>
800a3f0: 687b ldr r3, [r7, #4]
800a3f2: 4a3a ldr r2, [pc, #232] ; (800a4dc <TIM_Base_SetConfig+0x124>)
800a3f4: 4293 cmp r3, r2
800a3f6: d108 bne.n 800a40a <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800a3f8: 68fb ldr r3, [r7, #12]
800a3fa: f023 0370 bic.w r3, r3, #112 ; 0x70
800a3fe: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
800a400: 683b ldr r3, [r7, #0]
800a402: 685b ldr r3, [r3, #4]
800a404: 68fa ldr r2, [r7, #12]
800a406: 4313 orrs r3, r2
800a408: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800a40a: 687b ldr r3, [r7, #4]
800a40c: 4a2f ldr r2, [pc, #188] ; (800a4cc <TIM_Base_SetConfig+0x114>)
800a40e: 4293 cmp r3, r2
800a410: d02b beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a412: 687b ldr r3, [r7, #4]
800a414: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800a418: d027 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a41a: 687b ldr r3, [r7, #4]
800a41c: 4a2c ldr r2, [pc, #176] ; (800a4d0 <TIM_Base_SetConfig+0x118>)
800a41e: 4293 cmp r3, r2
800a420: d023 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a422: 687b ldr r3, [r7, #4]
800a424: 4a2b ldr r2, [pc, #172] ; (800a4d4 <TIM_Base_SetConfig+0x11c>)
800a426: 4293 cmp r3, r2
800a428: d01f beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a42a: 687b ldr r3, [r7, #4]
800a42c: 4a2a ldr r2, [pc, #168] ; (800a4d8 <TIM_Base_SetConfig+0x120>)
800a42e: 4293 cmp r3, r2
800a430: d01b beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a432: 687b ldr r3, [r7, #4]
800a434: 4a29 ldr r2, [pc, #164] ; (800a4dc <TIM_Base_SetConfig+0x124>)
800a436: 4293 cmp r3, r2
800a438: d017 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a43a: 687b ldr r3, [r7, #4]
800a43c: 4a28 ldr r2, [pc, #160] ; (800a4e0 <TIM_Base_SetConfig+0x128>)
800a43e: 4293 cmp r3, r2
800a440: d013 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a442: 687b ldr r3, [r7, #4]
800a444: 4a27 ldr r2, [pc, #156] ; (800a4e4 <TIM_Base_SetConfig+0x12c>)
800a446: 4293 cmp r3, r2
800a448: d00f beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a44a: 687b ldr r3, [r7, #4]
800a44c: 4a26 ldr r2, [pc, #152] ; (800a4e8 <TIM_Base_SetConfig+0x130>)
800a44e: 4293 cmp r3, r2
800a450: d00b beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a452: 687b ldr r3, [r7, #4]
800a454: 4a25 ldr r2, [pc, #148] ; (800a4ec <TIM_Base_SetConfig+0x134>)
800a456: 4293 cmp r3, r2
800a458: d007 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a45a: 687b ldr r3, [r7, #4]
800a45c: 4a24 ldr r2, [pc, #144] ; (800a4f0 <TIM_Base_SetConfig+0x138>)
800a45e: 4293 cmp r3, r2
800a460: d003 beq.n 800a46a <TIM_Base_SetConfig+0xb2>
800a462: 687b ldr r3, [r7, #4]
800a464: 4a23 ldr r2, [pc, #140] ; (800a4f4 <TIM_Base_SetConfig+0x13c>)
800a466: 4293 cmp r3, r2
800a468: d108 bne.n 800a47c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800a46a: 68fb ldr r3, [r7, #12]
800a46c: f423 7340 bic.w r3, r3, #768 ; 0x300
800a470: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
800a472: 683b ldr r3, [r7, #0]
800a474: 68db ldr r3, [r3, #12]
800a476: 68fa ldr r2, [r7, #12]
800a478: 4313 orrs r3, r2
800a47a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800a47c: 68fb ldr r3, [r7, #12]
800a47e: f023 0280 bic.w r2, r3, #128 ; 0x80
800a482: 683b ldr r3, [r7, #0]
800a484: 695b ldr r3, [r3, #20]
800a486: 4313 orrs r3, r2
800a488: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800a48a: 687b ldr r3, [r7, #4]
800a48c: 68fa ldr r2, [r7, #12]
800a48e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
800a490: 683b ldr r3, [r7, #0]
800a492: 689a ldr r2, [r3, #8]
800a494: 687b ldr r3, [r7, #4]
800a496: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
800a498: 683b ldr r3, [r7, #0]
800a49a: 681a ldr r2, [r3, #0]
800a49c: 687b ldr r3, [r7, #4]
800a49e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
800a4a0: 687b ldr r3, [r7, #4]
800a4a2: 4a0a ldr r2, [pc, #40] ; (800a4cc <TIM_Base_SetConfig+0x114>)
800a4a4: 4293 cmp r3, r2
800a4a6: d003 beq.n 800a4b0 <TIM_Base_SetConfig+0xf8>
800a4a8: 687b ldr r3, [r7, #4]
800a4aa: 4a0c ldr r2, [pc, #48] ; (800a4dc <TIM_Base_SetConfig+0x124>)
800a4ac: 4293 cmp r3, r2
800a4ae: d103 bne.n 800a4b8 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
800a4b0: 683b ldr r3, [r7, #0]
800a4b2: 691a ldr r2, [r3, #16]
800a4b4: 687b ldr r3, [r7, #4]
800a4b6: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
800a4b8: 687b ldr r3, [r7, #4]
800a4ba: 2201 movs r2, #1
800a4bc: 615a str r2, [r3, #20]
}
800a4be: bf00 nop
800a4c0: 3714 adds r7, #20
800a4c2: 46bd mov sp, r7
800a4c4: f85d 7b04 ldr.w r7, [sp], #4
800a4c8: 4770 bx lr
800a4ca: bf00 nop
800a4cc: 40010000 .word 0x40010000
800a4d0: 40000400 .word 0x40000400
800a4d4: 40000800 .word 0x40000800
800a4d8: 40000c00 .word 0x40000c00
800a4dc: 40010400 .word 0x40010400
800a4e0: 40014000 .word 0x40014000
800a4e4: 40014400 .word 0x40014400
800a4e8: 40014800 .word 0x40014800
800a4ec: 40001800 .word 0x40001800
800a4f0: 40001c00 .word 0x40001c00
800a4f4: 40002000 .word 0x40002000
0800a4f8 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a4f8: b480 push {r7}
800a4fa: b087 sub sp, #28
800a4fc: af00 add r7, sp, #0
800a4fe: 6078 str r0, [r7, #4]
800a500: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
800a502: 687b ldr r3, [r7, #4]
800a504: 6a1b ldr r3, [r3, #32]
800a506: f023 0201 bic.w r2, r3, #1
800a50a: 687b ldr r3, [r7, #4]
800a50c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a50e: 687b ldr r3, [r7, #4]
800a510: 6a1b ldr r3, [r3, #32]
800a512: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a514: 687b ldr r3, [r7, #4]
800a516: 685b ldr r3, [r3, #4]
800a518: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a51a: 687b ldr r3, [r7, #4]
800a51c: 699b ldr r3, [r3, #24]
800a51e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
800a520: 68fa ldr r2, [r7, #12]
800a522: 4b2b ldr r3, [pc, #172] ; (800a5d0 <TIM_OC1_SetConfig+0xd8>)
800a524: 4013 ands r3, r2
800a526: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
800a528: 68fb ldr r3, [r7, #12]
800a52a: f023 0303 bic.w r3, r3, #3
800a52e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a530: 683b ldr r3, [r7, #0]
800a532: 681b ldr r3, [r3, #0]
800a534: 68fa ldr r2, [r7, #12]
800a536: 4313 orrs r3, r2
800a538: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
800a53a: 697b ldr r3, [r7, #20]
800a53c: f023 0302 bic.w r3, r3, #2
800a540: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800a542: 683b ldr r3, [r7, #0]
800a544: 689b ldr r3, [r3, #8]
800a546: 697a ldr r2, [r7, #20]
800a548: 4313 orrs r3, r2
800a54a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
800a54c: 687b ldr r3, [r7, #4]
800a54e: 4a21 ldr r2, [pc, #132] ; (800a5d4 <TIM_OC1_SetConfig+0xdc>)
800a550: 4293 cmp r3, r2
800a552: d003 beq.n 800a55c <TIM_OC1_SetConfig+0x64>
800a554: 687b ldr r3, [r7, #4]
800a556: 4a20 ldr r2, [pc, #128] ; (800a5d8 <TIM_OC1_SetConfig+0xe0>)
800a558: 4293 cmp r3, r2
800a55a: d10c bne.n 800a576 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800a55c: 697b ldr r3, [r7, #20]
800a55e: f023 0308 bic.w r3, r3, #8
800a562: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800a564: 683b ldr r3, [r7, #0]
800a566: 68db ldr r3, [r3, #12]
800a568: 697a ldr r2, [r7, #20]
800a56a: 4313 orrs r3, r2
800a56c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800a56e: 697b ldr r3, [r7, #20]
800a570: f023 0304 bic.w r3, r3, #4
800a574: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a576: 687b ldr r3, [r7, #4]
800a578: 4a16 ldr r2, [pc, #88] ; (800a5d4 <TIM_OC1_SetConfig+0xdc>)
800a57a: 4293 cmp r3, r2
800a57c: d003 beq.n 800a586 <TIM_OC1_SetConfig+0x8e>
800a57e: 687b ldr r3, [r7, #4]
800a580: 4a15 ldr r2, [pc, #84] ; (800a5d8 <TIM_OC1_SetConfig+0xe0>)
800a582: 4293 cmp r3, r2
800a584: d111 bne.n 800a5aa <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800a586: 693b ldr r3, [r7, #16]
800a588: f423 7380 bic.w r3, r3, #256 ; 0x100
800a58c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800a58e: 693b ldr r3, [r7, #16]
800a590: f423 7300 bic.w r3, r3, #512 ; 0x200
800a594: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
800a596: 683b ldr r3, [r7, #0]
800a598: 695b ldr r3, [r3, #20]
800a59a: 693a ldr r2, [r7, #16]
800a59c: 4313 orrs r3, r2
800a59e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
800a5a0: 683b ldr r3, [r7, #0]
800a5a2: 699b ldr r3, [r3, #24]
800a5a4: 693a ldr r2, [r7, #16]
800a5a6: 4313 orrs r3, r2
800a5a8: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a5aa: 687b ldr r3, [r7, #4]
800a5ac: 693a ldr r2, [r7, #16]
800a5ae: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a5b0: 687b ldr r3, [r7, #4]
800a5b2: 68fa ldr r2, [r7, #12]
800a5b4: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
800a5b6: 683b ldr r3, [r7, #0]
800a5b8: 685a ldr r2, [r3, #4]
800a5ba: 687b ldr r3, [r7, #4]
800a5bc: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a5be: 687b ldr r3, [r7, #4]
800a5c0: 697a ldr r2, [r7, #20]
800a5c2: 621a str r2, [r3, #32]
}
800a5c4: bf00 nop
800a5c6: 371c adds r7, #28
800a5c8: 46bd mov sp, r7
800a5ca: f85d 7b04 ldr.w r7, [sp], #4
800a5ce: 4770 bx lr
800a5d0: fffeff8f .word 0xfffeff8f
800a5d4: 40010000 .word 0x40010000
800a5d8: 40010400 .word 0x40010400
0800a5dc <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a5dc: b480 push {r7}
800a5de: b087 sub sp, #28
800a5e0: af00 add r7, sp, #0
800a5e2: 6078 str r0, [r7, #4]
800a5e4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800a5e6: 687b ldr r3, [r7, #4]
800a5e8: 6a1b ldr r3, [r3, #32]
800a5ea: f023 0210 bic.w r2, r3, #16
800a5ee: 687b ldr r3, [r7, #4]
800a5f0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a5f2: 687b ldr r3, [r7, #4]
800a5f4: 6a1b ldr r3, [r3, #32]
800a5f6: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a5f8: 687b ldr r3, [r7, #4]
800a5fa: 685b ldr r3, [r3, #4]
800a5fc: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
800a5fe: 687b ldr r3, [r7, #4]
800a600: 699b ldr r3, [r3, #24]
800a602: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
800a604: 68fa ldr r2, [r7, #12]
800a606: 4b2e ldr r3, [pc, #184] ; (800a6c0 <TIM_OC2_SetConfig+0xe4>)
800a608: 4013 ands r3, r2
800a60a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
800a60c: 68fb ldr r3, [r7, #12]
800a60e: f423 7340 bic.w r3, r3, #768 ; 0x300
800a612: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a614: 683b ldr r3, [r7, #0]
800a616: 681b ldr r3, [r3, #0]
800a618: 021b lsls r3, r3, #8
800a61a: 68fa ldr r2, [r7, #12]
800a61c: 4313 orrs r3, r2
800a61e: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
800a620: 697b ldr r3, [r7, #20]
800a622: f023 0320 bic.w r3, r3, #32
800a626: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
800a628: 683b ldr r3, [r7, #0]
800a62a: 689b ldr r3, [r3, #8]
800a62c: 011b lsls r3, r3, #4
800a62e: 697a ldr r2, [r7, #20]
800a630: 4313 orrs r3, r2
800a632: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800a634: 687b ldr r3, [r7, #4]
800a636: 4a23 ldr r2, [pc, #140] ; (800a6c4 <TIM_OC2_SetConfig+0xe8>)
800a638: 4293 cmp r3, r2
800a63a: d003 beq.n 800a644 <TIM_OC2_SetConfig+0x68>
800a63c: 687b ldr r3, [r7, #4]
800a63e: 4a22 ldr r2, [pc, #136] ; (800a6c8 <TIM_OC2_SetConfig+0xec>)
800a640: 4293 cmp r3, r2
800a642: d10d bne.n 800a660 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
800a644: 697b ldr r3, [r7, #20]
800a646: f023 0380 bic.w r3, r3, #128 ; 0x80
800a64a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800a64c: 683b ldr r3, [r7, #0]
800a64e: 68db ldr r3, [r3, #12]
800a650: 011b lsls r3, r3, #4
800a652: 697a ldr r2, [r7, #20]
800a654: 4313 orrs r3, r2
800a656: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
800a658: 697b ldr r3, [r7, #20]
800a65a: f023 0340 bic.w r3, r3, #64 ; 0x40
800a65e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a660: 687b ldr r3, [r7, #4]
800a662: 4a18 ldr r2, [pc, #96] ; (800a6c4 <TIM_OC2_SetConfig+0xe8>)
800a664: 4293 cmp r3, r2
800a666: d003 beq.n 800a670 <TIM_OC2_SetConfig+0x94>
800a668: 687b ldr r3, [r7, #4]
800a66a: 4a17 ldr r2, [pc, #92] ; (800a6c8 <TIM_OC2_SetConfig+0xec>)
800a66c: 4293 cmp r3, r2
800a66e: d113 bne.n 800a698 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
800a670: 693b ldr r3, [r7, #16]
800a672: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a676: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
800a678: 693b ldr r3, [r7, #16]
800a67a: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a67e: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
800a680: 683b ldr r3, [r7, #0]
800a682: 695b ldr r3, [r3, #20]
800a684: 009b lsls r3, r3, #2
800a686: 693a ldr r2, [r7, #16]
800a688: 4313 orrs r3, r2
800a68a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800a68c: 683b ldr r3, [r7, #0]
800a68e: 699b ldr r3, [r3, #24]
800a690: 009b lsls r3, r3, #2
800a692: 693a ldr r2, [r7, #16]
800a694: 4313 orrs r3, r2
800a696: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a698: 687b ldr r3, [r7, #4]
800a69a: 693a ldr r2, [r7, #16]
800a69c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800a69e: 687b ldr r3, [r7, #4]
800a6a0: 68fa ldr r2, [r7, #12]
800a6a2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
800a6a4: 683b ldr r3, [r7, #0]
800a6a6: 685a ldr r2, [r3, #4]
800a6a8: 687b ldr r3, [r7, #4]
800a6aa: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a6ac: 687b ldr r3, [r7, #4]
800a6ae: 697a ldr r2, [r7, #20]
800a6b0: 621a str r2, [r3, #32]
}
800a6b2: bf00 nop
800a6b4: 371c adds r7, #28
800a6b6: 46bd mov sp, r7
800a6b8: f85d 7b04 ldr.w r7, [sp], #4
800a6bc: 4770 bx lr
800a6be: bf00 nop
800a6c0: feff8fff .word 0xfeff8fff
800a6c4: 40010000 .word 0x40010000
800a6c8: 40010400 .word 0x40010400
0800a6cc <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a6cc: b480 push {r7}
800a6ce: b087 sub sp, #28
800a6d0: af00 add r7, sp, #0
800a6d2: 6078 str r0, [r7, #4]
800a6d4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800a6d6: 687b ldr r3, [r7, #4]
800a6d8: 6a1b ldr r3, [r3, #32]
800a6da: f423 7280 bic.w r2, r3, #256 ; 0x100
800a6de: 687b ldr r3, [r7, #4]
800a6e0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a6e2: 687b ldr r3, [r7, #4]
800a6e4: 6a1b ldr r3, [r3, #32]
800a6e6: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a6e8: 687b ldr r3, [r7, #4]
800a6ea: 685b ldr r3, [r3, #4]
800a6ec: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a6ee: 687b ldr r3, [r7, #4]
800a6f0: 69db ldr r3, [r3, #28]
800a6f2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
800a6f4: 68fa ldr r2, [r7, #12]
800a6f6: 4b2d ldr r3, [pc, #180] ; (800a7ac <TIM_OC3_SetConfig+0xe0>)
800a6f8: 4013 ands r3, r2
800a6fa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800a6fc: 68fb ldr r3, [r7, #12]
800a6fe: f023 0303 bic.w r3, r3, #3
800a702: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a704: 683b ldr r3, [r7, #0]
800a706: 681b ldr r3, [r3, #0]
800a708: 68fa ldr r2, [r7, #12]
800a70a: 4313 orrs r3, r2
800a70c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800a70e: 697b ldr r3, [r7, #20]
800a710: f423 7300 bic.w r3, r3, #512 ; 0x200
800a714: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
800a716: 683b ldr r3, [r7, #0]
800a718: 689b ldr r3, [r3, #8]
800a71a: 021b lsls r3, r3, #8
800a71c: 697a ldr r2, [r7, #20]
800a71e: 4313 orrs r3, r2
800a720: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800a722: 687b ldr r3, [r7, #4]
800a724: 4a22 ldr r2, [pc, #136] ; (800a7b0 <TIM_OC3_SetConfig+0xe4>)
800a726: 4293 cmp r3, r2
800a728: d003 beq.n 800a732 <TIM_OC3_SetConfig+0x66>
800a72a: 687b ldr r3, [r7, #4]
800a72c: 4a21 ldr r2, [pc, #132] ; (800a7b4 <TIM_OC3_SetConfig+0xe8>)
800a72e: 4293 cmp r3, r2
800a730: d10d bne.n 800a74e <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800a732: 697b ldr r3, [r7, #20]
800a734: f423 6300 bic.w r3, r3, #2048 ; 0x800
800a738: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
800a73a: 683b ldr r3, [r7, #0]
800a73c: 68db ldr r3, [r3, #12]
800a73e: 021b lsls r3, r3, #8
800a740: 697a ldr r2, [r7, #20]
800a742: 4313 orrs r3, r2
800a744: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800a746: 697b ldr r3, [r7, #20]
800a748: f423 6380 bic.w r3, r3, #1024 ; 0x400
800a74c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a74e: 687b ldr r3, [r7, #4]
800a750: 4a17 ldr r2, [pc, #92] ; (800a7b0 <TIM_OC3_SetConfig+0xe4>)
800a752: 4293 cmp r3, r2
800a754: d003 beq.n 800a75e <TIM_OC3_SetConfig+0x92>
800a756: 687b ldr r3, [r7, #4]
800a758: 4a16 ldr r2, [pc, #88] ; (800a7b4 <TIM_OC3_SetConfig+0xe8>)
800a75a: 4293 cmp r3, r2
800a75c: d113 bne.n 800a786 <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800a75e: 693b ldr r3, [r7, #16]
800a760: f423 5380 bic.w r3, r3, #4096 ; 0x1000
800a764: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800a766: 693b ldr r3, [r7, #16]
800a768: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a76c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800a76e: 683b ldr r3, [r7, #0]
800a770: 695b ldr r3, [r3, #20]
800a772: 011b lsls r3, r3, #4
800a774: 693a ldr r2, [r7, #16]
800a776: 4313 orrs r3, r2
800a778: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800a77a: 683b ldr r3, [r7, #0]
800a77c: 699b ldr r3, [r3, #24]
800a77e: 011b lsls r3, r3, #4
800a780: 693a ldr r2, [r7, #16]
800a782: 4313 orrs r3, r2
800a784: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a786: 687b ldr r3, [r7, #4]
800a788: 693a ldr r2, [r7, #16]
800a78a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a78c: 687b ldr r3, [r7, #4]
800a78e: 68fa ldr r2, [r7, #12]
800a790: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800a792: 683b ldr r3, [r7, #0]
800a794: 685a ldr r2, [r3, #4]
800a796: 687b ldr r3, [r7, #4]
800a798: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a79a: 687b ldr r3, [r7, #4]
800a79c: 697a ldr r2, [r7, #20]
800a79e: 621a str r2, [r3, #32]
}
800a7a0: bf00 nop
800a7a2: 371c adds r7, #28
800a7a4: 46bd mov sp, r7
800a7a6: f85d 7b04 ldr.w r7, [sp], #4
800a7aa: 4770 bx lr
800a7ac: fffeff8f .word 0xfffeff8f
800a7b0: 40010000 .word 0x40010000
800a7b4: 40010400 .word 0x40010400
0800a7b8 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800a7b8: b480 push {r7}
800a7ba: b087 sub sp, #28
800a7bc: af00 add r7, sp, #0
800a7be: 6078 str r0, [r7, #4]
800a7c0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800a7c2: 687b ldr r3, [r7, #4]
800a7c4: 6a1b ldr r3, [r3, #32]
800a7c6: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800a7ca: 687b ldr r3, [r7, #4]
800a7cc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a7ce: 687b ldr r3, [r7, #4]
800a7d0: 6a1b ldr r3, [r3, #32]
800a7d2: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a7d4: 687b ldr r3, [r7, #4]
800a7d6: 685b ldr r3, [r3, #4]
800a7d8: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800a7da: 687b ldr r3, [r7, #4]
800a7dc: 69db ldr r3, [r3, #28]
800a7de: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
800a7e0: 68fa ldr r2, [r7, #12]
800a7e2: 4b1e ldr r3, [pc, #120] ; (800a85c <TIM_OC4_SetConfig+0xa4>)
800a7e4: 4013 ands r3, r2
800a7e6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
800a7e8: 68fb ldr r3, [r7, #12]
800a7ea: f423 7340 bic.w r3, r3, #768 ; 0x300
800a7ee: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a7f0: 683b ldr r3, [r7, #0]
800a7f2: 681b ldr r3, [r3, #0]
800a7f4: 021b lsls r3, r3, #8
800a7f6: 68fa ldr r2, [r7, #12]
800a7f8: 4313 orrs r3, r2
800a7fa: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
800a7fc: 693b ldr r3, [r7, #16]
800a7fe: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800a802: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800a804: 683b ldr r3, [r7, #0]
800a806: 689b ldr r3, [r3, #8]
800a808: 031b lsls r3, r3, #12
800a80a: 693a ldr r2, [r7, #16]
800a80c: 4313 orrs r3, r2
800a80e: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a810: 687b ldr r3, [r7, #4]
800a812: 4a13 ldr r2, [pc, #76] ; (800a860 <TIM_OC4_SetConfig+0xa8>)
800a814: 4293 cmp r3, r2
800a816: d003 beq.n 800a820 <TIM_OC4_SetConfig+0x68>
800a818: 687b ldr r3, [r7, #4]
800a81a: 4a12 ldr r2, [pc, #72] ; (800a864 <TIM_OC4_SetConfig+0xac>)
800a81c: 4293 cmp r3, r2
800a81e: d109 bne.n 800a834 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800a820: 697b ldr r3, [r7, #20]
800a822: f423 4380 bic.w r3, r3, #16384 ; 0x4000
800a826: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800a828: 683b ldr r3, [r7, #0]
800a82a: 695b ldr r3, [r3, #20]
800a82c: 019b lsls r3, r3, #6
800a82e: 697a ldr r2, [r7, #20]
800a830: 4313 orrs r3, r2
800a832: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a834: 687b ldr r3, [r7, #4]
800a836: 697a ldr r2, [r7, #20]
800a838: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800a83a: 687b ldr r3, [r7, #4]
800a83c: 68fa ldr r2, [r7, #12]
800a83e: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
800a840: 683b ldr r3, [r7, #0]
800a842: 685a ldr r2, [r3, #4]
800a844: 687b ldr r3, [r7, #4]
800a846: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a848: 687b ldr r3, [r7, #4]
800a84a: 693a ldr r2, [r7, #16]
800a84c: 621a str r2, [r3, #32]
}
800a84e: bf00 nop
800a850: 371c adds r7, #28
800a852: 46bd mov sp, r7
800a854: f85d 7b04 ldr.w r7, [sp], #4
800a858: 4770 bx lr
800a85a: bf00 nop
800a85c: feff8fff .word 0xfeff8fff
800a860: 40010000 .word 0x40010000
800a864: 40010400 .word 0x40010400
0800a868 <TIM_OC5_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a868: b480 push {r7}
800a86a: b087 sub sp, #28
800a86c: af00 add r7, sp, #0
800a86e: 6078 str r0, [r7, #4]
800a870: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
800a872: 687b ldr r3, [r7, #4]
800a874: 6a1b ldr r3, [r3, #32]
800a876: f423 3280 bic.w r2, r3, #65536 ; 0x10000
800a87a: 687b ldr r3, [r7, #4]
800a87c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a87e: 687b ldr r3, [r7, #4]
800a880: 6a1b ldr r3, [r3, #32]
800a882: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a884: 687b ldr r3, [r7, #4]
800a886: 685b ldr r3, [r3, #4]
800a888: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a88a: 687b ldr r3, [r7, #4]
800a88c: 6d5b ldr r3, [r3, #84] ; 0x54
800a88e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800a890: 68fa ldr r2, [r7, #12]
800a892: 4b1b ldr r3, [pc, #108] ; (800a900 <TIM_OC5_SetConfig+0x98>)
800a894: 4013 ands r3, r2
800a896: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800a898: 683b ldr r3, [r7, #0]
800a89a: 681b ldr r3, [r3, #0]
800a89c: 68fa ldr r2, [r7, #12]
800a89e: 4313 orrs r3, r2
800a8a0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
800a8a2: 693b ldr r3, [r7, #16]
800a8a4: f423 3300 bic.w r3, r3, #131072 ; 0x20000
800a8a8: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800a8aa: 683b ldr r3, [r7, #0]
800a8ac: 689b ldr r3, [r3, #8]
800a8ae: 041b lsls r3, r3, #16
800a8b0: 693a ldr r2, [r7, #16]
800a8b2: 4313 orrs r3, r2
800a8b4: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a8b6: 687b ldr r3, [r7, #4]
800a8b8: 4a12 ldr r2, [pc, #72] ; (800a904 <TIM_OC5_SetConfig+0x9c>)
800a8ba: 4293 cmp r3, r2
800a8bc: d003 beq.n 800a8c6 <TIM_OC5_SetConfig+0x5e>
800a8be: 687b ldr r3, [r7, #4]
800a8c0: 4a11 ldr r2, [pc, #68] ; (800a908 <TIM_OC5_SetConfig+0xa0>)
800a8c2: 4293 cmp r3, r2
800a8c4: d109 bne.n 800a8da <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
800a8c6: 697b ldr r3, [r7, #20]
800a8c8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800a8cc: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800a8ce: 683b ldr r3, [r7, #0]
800a8d0: 695b ldr r3, [r3, #20]
800a8d2: 021b lsls r3, r3, #8
800a8d4: 697a ldr r2, [r7, #20]
800a8d6: 4313 orrs r3, r2
800a8d8: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a8da: 687b ldr r3, [r7, #4]
800a8dc: 697a ldr r2, [r7, #20]
800a8de: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a8e0: 687b ldr r3, [r7, #4]
800a8e2: 68fa ldr r2, [r7, #12]
800a8e4: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
800a8e6: 683b ldr r3, [r7, #0]
800a8e8: 685a ldr r2, [r3, #4]
800a8ea: 687b ldr r3, [r7, #4]
800a8ec: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a8ee: 687b ldr r3, [r7, #4]
800a8f0: 693a ldr r2, [r7, #16]
800a8f2: 621a str r2, [r3, #32]
}
800a8f4: bf00 nop
800a8f6: 371c adds r7, #28
800a8f8: 46bd mov sp, r7
800a8fa: f85d 7b04 ldr.w r7, [sp], #4
800a8fe: 4770 bx lr
800a900: fffeff8f .word 0xfffeff8f
800a904: 40010000 .word 0x40010000
800a908: 40010400 .word 0x40010400
0800a90c <TIM_OC6_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
800a90c: b480 push {r7}
800a90e: b087 sub sp, #28
800a910: af00 add r7, sp, #0
800a912: 6078 str r0, [r7, #4]
800a914: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
800a916: 687b ldr r3, [r7, #4]
800a918: 6a1b ldr r3, [r3, #32]
800a91a: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
800a91e: 687b ldr r3, [r7, #4]
800a920: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800a922: 687b ldr r3, [r7, #4]
800a924: 6a1b ldr r3, [r3, #32]
800a926: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800a928: 687b ldr r3, [r7, #4]
800a92a: 685b ldr r3, [r3, #4]
800a92c: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800a92e: 687b ldr r3, [r7, #4]
800a930: 6d5b ldr r3, [r3, #84] ; 0x54
800a932: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
800a934: 68fa ldr r2, [r7, #12]
800a936: 4b1c ldr r3, [pc, #112] ; (800a9a8 <TIM_OC6_SetConfig+0x9c>)
800a938: 4013 ands r3, r2
800a93a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800a93c: 683b ldr r3, [r7, #0]
800a93e: 681b ldr r3, [r3, #0]
800a940: 021b lsls r3, r3, #8
800a942: 68fa ldr r2, [r7, #12]
800a944: 4313 orrs r3, r2
800a946: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
800a948: 693b ldr r3, [r7, #16]
800a94a: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
800a94e: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
800a950: 683b ldr r3, [r7, #0]
800a952: 689b ldr r3, [r3, #8]
800a954: 051b lsls r3, r3, #20
800a956: 693a ldr r2, [r7, #16]
800a958: 4313 orrs r3, r2
800a95a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800a95c: 687b ldr r3, [r7, #4]
800a95e: 4a13 ldr r2, [pc, #76] ; (800a9ac <TIM_OC6_SetConfig+0xa0>)
800a960: 4293 cmp r3, r2
800a962: d003 beq.n 800a96c <TIM_OC6_SetConfig+0x60>
800a964: 687b ldr r3, [r7, #4]
800a966: 4a12 ldr r2, [pc, #72] ; (800a9b0 <TIM_OC6_SetConfig+0xa4>)
800a968: 4293 cmp r3, r2
800a96a: d109 bne.n 800a980 <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
800a96c: 697b ldr r3, [r7, #20]
800a96e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800a972: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
800a974: 683b ldr r3, [r7, #0]
800a976: 695b ldr r3, [r3, #20]
800a978: 029b lsls r3, r3, #10
800a97a: 697a ldr r2, [r7, #20]
800a97c: 4313 orrs r3, r2
800a97e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800a980: 687b ldr r3, [r7, #4]
800a982: 697a ldr r2, [r7, #20]
800a984: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
800a986: 687b ldr r3, [r7, #4]
800a988: 68fa ldr r2, [r7, #12]
800a98a: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
800a98c: 683b ldr r3, [r7, #0]
800a98e: 685a ldr r2, [r3, #4]
800a990: 687b ldr r3, [r7, #4]
800a992: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800a994: 687b ldr r3, [r7, #4]
800a996: 693a ldr r2, [r7, #16]
800a998: 621a str r2, [r3, #32]
}
800a99a: bf00 nop
800a99c: 371c adds r7, #28
800a99e: 46bd mov sp, r7
800a9a0: f85d 7b04 ldr.w r7, [sp], #4
800a9a4: 4770 bx lr
800a9a6: bf00 nop
800a9a8: feff8fff .word 0xfeff8fff
800a9ac: 40010000 .word 0x40010000
800a9b0: 40010400 .word 0x40010400
0800a9b4 <TIM_SlaveTimer_SetConfig>:
* @param sSlaveConfig Slave timer configuration
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
800a9b4: b580 push {r7, lr}
800a9b6: b086 sub sp, #24
800a9b8: af00 add r7, sp, #0
800a9ba: 6078 str r0, [r7, #4]
800a9bc: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800a9be: 687b ldr r3, [r7, #4]
800a9c0: 681b ldr r3, [r3, #0]
800a9c2: 689b ldr r3, [r3, #8]
800a9c4: 617b str r3, [r7, #20]
/* Reset the Trigger Selection Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800a9c6: 697b ldr r3, [r7, #20]
800a9c8: f023 0370 bic.w r3, r3, #112 ; 0x70
800a9cc: 617b str r3, [r7, #20]
/* Set the Input Trigger source */
tmpsmcr |= sSlaveConfig->InputTrigger;
800a9ce: 683b ldr r3, [r7, #0]
800a9d0: 685b ldr r3, [r3, #4]
800a9d2: 697a ldr r2, [r7, #20]
800a9d4: 4313 orrs r3, r2
800a9d6: 617b str r3, [r7, #20]
/* Reset the slave mode Bits */
tmpsmcr &= ~TIM_SMCR_SMS;
800a9d8: 697a ldr r2, [r7, #20]
800a9da: 4b39 ldr r3, [pc, #228] ; (800aac0 <TIM_SlaveTimer_SetConfig+0x10c>)
800a9dc: 4013 ands r3, r2
800a9de: 617b str r3, [r7, #20]
/* Set the slave mode */
tmpsmcr |= sSlaveConfig->SlaveMode;
800a9e0: 683b ldr r3, [r7, #0]
800a9e2: 681b ldr r3, [r3, #0]
800a9e4: 697a ldr r2, [r7, #20]
800a9e6: 4313 orrs r3, r2
800a9e8: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800a9ea: 687b ldr r3, [r7, #4]
800a9ec: 681b ldr r3, [r3, #0]
800a9ee: 697a ldr r2, [r7, #20]
800a9f0: 609a str r2, [r3, #8]
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
800a9f2: 683b ldr r3, [r7, #0]
800a9f4: 685b ldr r3, [r3, #4]
800a9f6: 2b30 cmp r3, #48 ; 0x30
800a9f8: d05c beq.n 800aab4 <TIM_SlaveTimer_SetConfig+0x100>
800a9fa: 2b30 cmp r3, #48 ; 0x30
800a9fc: d806 bhi.n 800aa0c <TIM_SlaveTimer_SetConfig+0x58>
800a9fe: 2b10 cmp r3, #16
800aa00: d058 beq.n 800aab4 <TIM_SlaveTimer_SetConfig+0x100>
800aa02: 2b20 cmp r3, #32
800aa04: d056 beq.n 800aab4 <TIM_SlaveTimer_SetConfig+0x100>
800aa06: 2b00 cmp r3, #0
800aa08: d054 beq.n 800aab4 <TIM_SlaveTimer_SetConfig+0x100>
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
break;
}
default:
break;
800aa0a: e054 b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
800aa0c: 2b50 cmp r3, #80 ; 0x50
800aa0e: d03d beq.n 800aa8c <TIM_SlaveTimer_SetConfig+0xd8>
800aa10: 2b50 cmp r3, #80 ; 0x50
800aa12: d802 bhi.n 800aa1a <TIM_SlaveTimer_SetConfig+0x66>
800aa14: 2b40 cmp r3, #64 ; 0x40
800aa16: d010 beq.n 800aa3a <TIM_SlaveTimer_SetConfig+0x86>
break;
800aa18: e04d b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
800aa1a: 2b60 cmp r3, #96 ; 0x60
800aa1c: d040 beq.n 800aaa0 <TIM_SlaveTimer_SetConfig+0xec>
800aa1e: 2b70 cmp r3, #112 ; 0x70
800aa20: d000 beq.n 800aa24 <TIM_SlaveTimer_SetConfig+0x70>
break;
800aa22: e048 b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
TIM_ETR_SetConfig(htim->Instance,
800aa24: 687b ldr r3, [r7, #4]
800aa26: 6818 ldr r0, [r3, #0]
800aa28: 683b ldr r3, [r7, #0]
800aa2a: 68d9 ldr r1, [r3, #12]
800aa2c: 683b ldr r3, [r7, #0]
800aa2e: 689a ldr r2, [r3, #8]
800aa30: 683b ldr r3, [r7, #0]
800aa32: 691b ldr r3, [r3, #16]
800aa34: f000 f8c0 bl 800abb8 <TIM_ETR_SetConfig>
break;
800aa38: e03d b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
800aa3a: 683b ldr r3, [r7, #0]
800aa3c: 681b ldr r3, [r3, #0]
800aa3e: 2b05 cmp r3, #5
800aa40: d101 bne.n 800aa46 <TIM_SlaveTimer_SetConfig+0x92>
return HAL_ERROR;
800aa42: 2301 movs r3, #1
800aa44: e038 b.n 800aab8 <TIM_SlaveTimer_SetConfig+0x104>
tmpccer = htim->Instance->CCER;
800aa46: 687b ldr r3, [r7, #4]
800aa48: 681b ldr r3, [r3, #0]
800aa4a: 6a1b ldr r3, [r3, #32]
800aa4c: 613b str r3, [r7, #16]
htim->Instance->CCER &= ~TIM_CCER_CC1E;
800aa4e: 687b ldr r3, [r7, #4]
800aa50: 681b ldr r3, [r3, #0]
800aa52: 6a1a ldr r2, [r3, #32]
800aa54: 687b ldr r3, [r7, #4]
800aa56: 681b ldr r3, [r3, #0]
800aa58: f022 0201 bic.w r2, r2, #1
800aa5c: 621a str r2, [r3, #32]
tmpccmr1 = htim->Instance->CCMR1;
800aa5e: 687b ldr r3, [r7, #4]
800aa60: 681b ldr r3, [r3, #0]
800aa62: 699b ldr r3, [r3, #24]
800aa64: 60fb str r3, [r7, #12]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800aa66: 68fb ldr r3, [r7, #12]
800aa68: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800aa6c: 60fb str r3, [r7, #12]
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
800aa6e: 683b ldr r3, [r7, #0]
800aa70: 691b ldr r3, [r3, #16]
800aa72: 011b lsls r3, r3, #4
800aa74: 68fa ldr r2, [r7, #12]
800aa76: 4313 orrs r3, r2
800aa78: 60fb str r3, [r7, #12]
htim->Instance->CCMR1 = tmpccmr1;
800aa7a: 687b ldr r3, [r7, #4]
800aa7c: 681b ldr r3, [r3, #0]
800aa7e: 68fa ldr r2, [r7, #12]
800aa80: 619a str r2, [r3, #24]
htim->Instance->CCER = tmpccer;
800aa82: 687b ldr r3, [r7, #4]
800aa84: 681b ldr r3, [r3, #0]
800aa86: 693a ldr r2, [r7, #16]
800aa88: 621a str r2, [r3, #32]
break;
800aa8a: e014 b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI1_ConfigInputStage(htim->Instance,
800aa8c: 687b ldr r3, [r7, #4]
800aa8e: 6818 ldr r0, [r3, #0]
800aa90: 683b ldr r3, [r7, #0]
800aa92: 6899 ldr r1, [r3, #8]
800aa94: 683b ldr r3, [r7, #0]
800aa96: 691b ldr r3, [r3, #16]
800aa98: 461a mov r2, r3
800aa9a: f000 f813 bl 800aac4 <TIM_TI1_ConfigInputStage>
break;
800aa9e: e00a b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI2_ConfigInputStage(htim->Instance,
800aaa0: 687b ldr r3, [r7, #4]
800aaa2: 6818 ldr r0, [r3, #0]
800aaa4: 683b ldr r3, [r7, #0]
800aaa6: 6899 ldr r1, [r3, #8]
800aaa8: 683b ldr r3, [r7, #0]
800aaaa: 691b ldr r3, [r3, #16]
800aaac: 461a mov r2, r3
800aaae: f000 f838 bl 800ab22 <TIM_TI2_ConfigInputStage>
break;
800aab2: e000 b.n 800aab6 <TIM_SlaveTimer_SetConfig+0x102>
break;
800aab4: bf00 nop
}
return HAL_OK;
800aab6: 2300 movs r3, #0
}
800aab8: 4618 mov r0, r3
800aaba: 3718 adds r7, #24
800aabc: 46bd mov sp, r7
800aabe: bd80 pop {r7, pc}
800aac0: fffefff8 .word 0xfffefff8
0800aac4 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800aac4: b480 push {r7}
800aac6: b087 sub sp, #28
800aac8: af00 add r7, sp, #0
800aaca: 60f8 str r0, [r7, #12]
800aacc: 60b9 str r1, [r7, #8]
800aace: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
800aad0: 68fb ldr r3, [r7, #12]
800aad2: 6a1b ldr r3, [r3, #32]
800aad4: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800aad6: 68fb ldr r3, [r7, #12]
800aad8: 6a1b ldr r3, [r3, #32]
800aada: f023 0201 bic.w r2, r3, #1
800aade: 68fb ldr r3, [r7, #12]
800aae0: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800aae2: 68fb ldr r3, [r7, #12]
800aae4: 699b ldr r3, [r3, #24]
800aae6: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800aae8: 693b ldr r3, [r7, #16]
800aaea: f023 03f0 bic.w r3, r3, #240 ; 0xf0
800aaee: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
800aaf0: 687b ldr r3, [r7, #4]
800aaf2: 011b lsls r3, r3, #4
800aaf4: 693a ldr r2, [r7, #16]
800aaf6: 4313 orrs r3, r2
800aaf8: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800aafa: 697b ldr r3, [r7, #20]
800aafc: f023 030a bic.w r3, r3, #10
800ab00: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800ab02: 697a ldr r2, [r7, #20]
800ab04: 68bb ldr r3, [r7, #8]
800ab06: 4313 orrs r3, r2
800ab08: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800ab0a: 68fb ldr r3, [r7, #12]
800ab0c: 693a ldr r2, [r7, #16]
800ab0e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800ab10: 68fb ldr r3, [r7, #12]
800ab12: 697a ldr r2, [r7, #20]
800ab14: 621a str r2, [r3, #32]
}
800ab16: bf00 nop
800ab18: 371c adds r7, #28
800ab1a: 46bd mov sp, r7
800ab1c: f85d 7b04 ldr.w r7, [sp], #4
800ab20: 4770 bx lr
0800ab22 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800ab22: b480 push {r7}
800ab24: b087 sub sp, #28
800ab26: af00 add r7, sp, #0
800ab28: 60f8 str r0, [r7, #12]
800ab2a: 60b9 str r1, [r7, #8]
800ab2c: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
800ab2e: 68fb ldr r3, [r7, #12]
800ab30: 6a1b ldr r3, [r3, #32]
800ab32: f023 0210 bic.w r2, r3, #16
800ab36: 68fb ldr r3, [r7, #12]
800ab38: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800ab3a: 68fb ldr r3, [r7, #12]
800ab3c: 699b ldr r3, [r3, #24]
800ab3e: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
800ab40: 68fb ldr r3, [r7, #12]
800ab42: 6a1b ldr r3, [r3, #32]
800ab44: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800ab46: 697b ldr r3, [r7, #20]
800ab48: f423 4370 bic.w r3, r3, #61440 ; 0xf000
800ab4c: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
800ab4e: 687b ldr r3, [r7, #4]
800ab50: 031b lsls r3, r3, #12
800ab52: 697a ldr r2, [r7, #20]
800ab54: 4313 orrs r3, r2
800ab56: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800ab58: 693b ldr r3, [r7, #16]
800ab5a: f023 03a0 bic.w r3, r3, #160 ; 0xa0
800ab5e: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
800ab60: 68bb ldr r3, [r7, #8]
800ab62: 011b lsls r3, r3, #4
800ab64: 693a ldr r2, [r7, #16]
800ab66: 4313 orrs r3, r2
800ab68: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800ab6a: 68fb ldr r3, [r7, #12]
800ab6c: 697a ldr r2, [r7, #20]
800ab6e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800ab70: 68fb ldr r3, [r7, #12]
800ab72: 693a ldr r2, [r7, #16]
800ab74: 621a str r2, [r3, #32]
}
800ab76: bf00 nop
800ab78: 371c adds r7, #28
800ab7a: 46bd mov sp, r7
800ab7c: f85d 7b04 ldr.w r7, [sp], #4
800ab80: 4770 bx lr
0800ab82 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
800ab82: b480 push {r7}
800ab84: b085 sub sp, #20
800ab86: af00 add r7, sp, #0
800ab88: 6078 str r0, [r7, #4]
800ab8a: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
800ab8c: 687b ldr r3, [r7, #4]
800ab8e: 689b ldr r3, [r3, #8]
800ab90: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
800ab92: 68fb ldr r3, [r7, #12]
800ab94: f023 0370 bic.w r3, r3, #112 ; 0x70
800ab98: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800ab9a: 683a ldr r2, [r7, #0]
800ab9c: 68fb ldr r3, [r7, #12]
800ab9e: 4313 orrs r3, r2
800aba0: f043 0307 orr.w r3, r3, #7
800aba4: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800aba6: 687b ldr r3, [r7, #4]
800aba8: 68fa ldr r2, [r7, #12]
800abaa: 609a str r2, [r3, #8]
}
800abac: bf00 nop
800abae: 3714 adds r7, #20
800abb0: 46bd mov sp, r7
800abb2: f85d 7b04 ldr.w r7, [sp], #4
800abb6: 4770 bx lr
0800abb8 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800abb8: b480 push {r7}
800abba: b087 sub sp, #28
800abbc: af00 add r7, sp, #0
800abbe: 60f8 str r0, [r7, #12]
800abc0: 60b9 str r1, [r7, #8]
800abc2: 607a str r2, [r7, #4]
800abc4: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800abc6: 68fb ldr r3, [r7, #12]
800abc8: 689b ldr r3, [r3, #8]
800abca: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800abcc: 697b ldr r3, [r7, #20]
800abce: f423 437f bic.w r3, r3, #65280 ; 0xff00
800abd2: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
800abd4: 683b ldr r3, [r7, #0]
800abd6: 021a lsls r2, r3, #8
800abd8: 687b ldr r3, [r7, #4]
800abda: 431a orrs r2, r3
800abdc: 68bb ldr r3, [r7, #8]
800abde: 4313 orrs r3, r2
800abe0: 697a ldr r2, [r7, #20]
800abe2: 4313 orrs r3, r2
800abe4: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800abe6: 68fb ldr r3, [r7, #12]
800abe8: 697a ldr r2, [r7, #20]
800abea: 609a str r2, [r3, #8]
}
800abec: bf00 nop
800abee: 371c adds r7, #28
800abf0: 46bd mov sp, r7
800abf2: f85d 7b04 ldr.w r7, [sp], #4
800abf6: 4770 bx lr
0800abf8 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
800abf8: b480 push {r7}
800abfa: b085 sub sp, #20
800abfc: af00 add r7, sp, #0
800abfe: 6078 str r0, [r7, #4]
800ac00: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
800ac02: 687b ldr r3, [r7, #4]
800ac04: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ac08: 2b01 cmp r3, #1
800ac0a: d101 bne.n 800ac10 <HAL_TIMEx_MasterConfigSynchronization+0x18>
800ac0c: 2302 movs r3, #2
800ac0e: e06d b.n 800acec <HAL_TIMEx_MasterConfigSynchronization+0xf4>
800ac10: 687b ldr r3, [r7, #4]
800ac12: 2201 movs r2, #1
800ac14: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800ac18: 687b ldr r3, [r7, #4]
800ac1a: 2202 movs r2, #2
800ac1c: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
800ac20: 687b ldr r3, [r7, #4]
800ac22: 681b ldr r3, [r3, #0]
800ac24: 685b ldr r3, [r3, #4]
800ac26: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800ac28: 687b ldr r3, [r7, #4]
800ac2a: 681b ldr r3, [r3, #0]
800ac2c: 689b ldr r3, [r3, #8]
800ac2e: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
800ac30: 687b ldr r3, [r7, #4]
800ac32: 681b ldr r3, [r3, #0]
800ac34: 4a30 ldr r2, [pc, #192] ; (800acf8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ac36: 4293 cmp r3, r2
800ac38: d004 beq.n 800ac44 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
800ac3a: 687b ldr r3, [r7, #4]
800ac3c: 681b ldr r3, [r3, #0]
800ac3e: 4a2f ldr r2, [pc, #188] ; (800acfc <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800ac40: 4293 cmp r3, r2
800ac42: d108 bne.n 800ac56 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
800ac44: 68fb ldr r3, [r7, #12]
800ac46: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
800ac4a: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
800ac4c: 683b ldr r3, [r7, #0]
800ac4e: 685b ldr r3, [r3, #4]
800ac50: 68fa ldr r2, [r7, #12]
800ac52: 4313 orrs r3, r2
800ac54: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800ac56: 68fb ldr r3, [r7, #12]
800ac58: f023 0370 bic.w r3, r3, #112 ; 0x70
800ac5c: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
800ac5e: 683b ldr r3, [r7, #0]
800ac60: 681b ldr r3, [r3, #0]
800ac62: 68fa ldr r2, [r7, #12]
800ac64: 4313 orrs r3, r2
800ac66: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
800ac68: 687b ldr r3, [r7, #4]
800ac6a: 681b ldr r3, [r3, #0]
800ac6c: 68fa ldr r2, [r7, #12]
800ac6e: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800ac70: 687b ldr r3, [r7, #4]
800ac72: 681b ldr r3, [r3, #0]
800ac74: 4a20 ldr r2, [pc, #128] ; (800acf8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
800ac76: 4293 cmp r3, r2
800ac78: d022 beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac7a: 687b ldr r3, [r7, #4]
800ac7c: 681b ldr r3, [r3, #0]
800ac7e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
800ac82: d01d beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac84: 687b ldr r3, [r7, #4]
800ac86: 681b ldr r3, [r3, #0]
800ac88: 4a1d ldr r2, [pc, #116] ; (800ad00 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
800ac8a: 4293 cmp r3, r2
800ac8c: d018 beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac8e: 687b ldr r3, [r7, #4]
800ac90: 681b ldr r3, [r3, #0]
800ac92: 4a1c ldr r2, [pc, #112] ; (800ad04 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
800ac94: 4293 cmp r3, r2
800ac96: d013 beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800ac98: 687b ldr r3, [r7, #4]
800ac9a: 681b ldr r3, [r3, #0]
800ac9c: 4a1a ldr r2, [pc, #104] ; (800ad08 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
800ac9e: 4293 cmp r3, r2
800aca0: d00e beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800aca2: 687b ldr r3, [r7, #4]
800aca4: 681b ldr r3, [r3, #0]
800aca6: 4a15 ldr r2, [pc, #84] ; (800acfc <HAL_TIMEx_MasterConfigSynchronization+0x104>)
800aca8: 4293 cmp r3, r2
800acaa: d009 beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800acac: 687b ldr r3, [r7, #4]
800acae: 681b ldr r3, [r3, #0]
800acb0: 4a16 ldr r2, [pc, #88] ; (800ad0c <HAL_TIMEx_MasterConfigSynchronization+0x114>)
800acb2: 4293 cmp r3, r2
800acb4: d004 beq.n 800acc0 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
800acb6: 687b ldr r3, [r7, #4]
800acb8: 681b ldr r3, [r3, #0]
800acba: 4a15 ldr r2, [pc, #84] ; (800ad10 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
800acbc: 4293 cmp r3, r2
800acbe: d10c bne.n 800acda <HAL_TIMEx_MasterConfigSynchronization+0xe2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800acc0: 68bb ldr r3, [r7, #8]
800acc2: f023 0380 bic.w r3, r3, #128 ; 0x80
800acc6: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
800acc8: 683b ldr r3, [r7, #0]
800acca: 689b ldr r3, [r3, #8]
800accc: 68ba ldr r2, [r7, #8]
800acce: 4313 orrs r3, r2
800acd0: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800acd2: 687b ldr r3, [r7, #4]
800acd4: 681b ldr r3, [r3, #0]
800acd6: 68ba ldr r2, [r7, #8]
800acd8: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
800acda: 687b ldr r3, [r7, #4]
800acdc: 2201 movs r2, #1
800acde: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800ace2: 687b ldr r3, [r7, #4]
800ace4: 2200 movs r2, #0
800ace6: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800acea: 2300 movs r3, #0
}
800acec: 4618 mov r0, r3
800acee: 3714 adds r7, #20
800acf0: 46bd mov sp, r7
800acf2: f85d 7b04 ldr.w r7, [sp], #4
800acf6: 4770 bx lr
800acf8: 40010000 .word 0x40010000
800acfc: 40010400 .word 0x40010400
800ad00: 40000400 .word 0x40000400
800ad04: 40000800 .word 0x40000800
800ad08: 40000c00 .word 0x40000c00
800ad0c: 40014000 .word 0x40014000
800ad10: 40001800 .word 0x40001800
0800ad14 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
800ad14: b480 push {r7}
800ad16: b085 sub sp, #20
800ad18: af00 add r7, sp, #0
800ad1a: 6078 str r0, [r7, #4]
800ad1c: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800ad1e: 2300 movs r3, #0
800ad20: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
800ad22: 687b ldr r3, [r7, #4]
800ad24: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800ad28: 2b01 cmp r3, #1
800ad2a: d101 bne.n 800ad30 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
800ad2c: 2302 movs r3, #2
800ad2e: e065 b.n 800adfc <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
800ad30: 687b ldr r3, [r7, #4]
800ad32: 2201 movs r2, #1
800ad34: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
800ad38: 68fb ldr r3, [r7, #12]
800ad3a: f023 02ff bic.w r2, r3, #255 ; 0xff
800ad3e: 683b ldr r3, [r7, #0]
800ad40: 68db ldr r3, [r3, #12]
800ad42: 4313 orrs r3, r2
800ad44: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
800ad46: 68fb ldr r3, [r7, #12]
800ad48: f423 7240 bic.w r2, r3, #768 ; 0x300
800ad4c: 683b ldr r3, [r7, #0]
800ad4e: 689b ldr r3, [r3, #8]
800ad50: 4313 orrs r3, r2
800ad52: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
800ad54: 68fb ldr r3, [r7, #12]
800ad56: f423 6280 bic.w r2, r3, #1024 ; 0x400
800ad5a: 683b ldr r3, [r7, #0]
800ad5c: 685b ldr r3, [r3, #4]
800ad5e: 4313 orrs r3, r2
800ad60: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
800ad62: 68fb ldr r3, [r7, #12]
800ad64: f423 6200 bic.w r2, r3, #2048 ; 0x800
800ad68: 683b ldr r3, [r7, #0]
800ad6a: 681b ldr r3, [r3, #0]
800ad6c: 4313 orrs r3, r2
800ad6e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
800ad70: 68fb ldr r3, [r7, #12]
800ad72: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800ad76: 683b ldr r3, [r7, #0]
800ad78: 691b ldr r3, [r3, #16]
800ad7a: 4313 orrs r3, r2
800ad7c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
800ad7e: 68fb ldr r3, [r7, #12]
800ad80: f423 5200 bic.w r2, r3, #8192 ; 0x2000
800ad84: 683b ldr r3, [r7, #0]
800ad86: 695b ldr r3, [r3, #20]
800ad88: 4313 orrs r3, r2
800ad8a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
800ad8c: 68fb ldr r3, [r7, #12]
800ad8e: f423 4280 bic.w r2, r3, #16384 ; 0x4000
800ad92: 683b ldr r3, [r7, #0]
800ad94: 6a9b ldr r3, [r3, #40] ; 0x28
800ad96: 4313 orrs r3, r2
800ad98: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
800ad9a: 68fb ldr r3, [r7, #12]
800ad9c: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
800ada0: 683b ldr r3, [r7, #0]
800ada2: 699b ldr r3, [r3, #24]
800ada4: 041b lsls r3, r3, #16
800ada6: 4313 orrs r3, r2
800ada8: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
800adaa: 687b ldr r3, [r7, #4]
800adac: 681b ldr r3, [r3, #0]
800adae: 4a16 ldr r2, [pc, #88] ; (800ae08 <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
800adb0: 4293 cmp r3, r2
800adb2: d004 beq.n 800adbe <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
800adb4: 687b ldr r3, [r7, #4]
800adb6: 681b ldr r3, [r3, #0]
800adb8: 4a14 ldr r2, [pc, #80] ; (800ae0c <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
800adba: 4293 cmp r3, r2
800adbc: d115 bne.n 800adea <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
800adbe: 68fb ldr r3, [r7, #12]
800adc0: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
800adc4: 683b ldr r3, [r7, #0]
800adc6: 6a5b ldr r3, [r3, #36] ; 0x24
800adc8: 051b lsls r3, r3, #20
800adca: 4313 orrs r3, r2
800adcc: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
800adce: 68fb ldr r3, [r7, #12]
800add0: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
800add4: 683b ldr r3, [r7, #0]
800add6: 69db ldr r3, [r3, #28]
800add8: 4313 orrs r3, r2
800adda: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
800addc: 68fb ldr r3, [r7, #12]
800adde: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
800ade2: 683b ldr r3, [r7, #0]
800ade4: 6a1b ldr r3, [r3, #32]
800ade6: 4313 orrs r3, r2
800ade8: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
800adea: 687b ldr r3, [r7, #4]
800adec: 681b ldr r3, [r3, #0]
800adee: 68fa ldr r2, [r7, #12]
800adf0: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
800adf2: 687b ldr r3, [r7, #4]
800adf4: 2200 movs r2, #0
800adf6: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800adfa: 2300 movs r3, #0
}
800adfc: 4618 mov r0, r3
800adfe: 3714 adds r7, #20
800ae00: 46bd mov sp, r7
800ae02: f85d 7b04 ldr.w r7, [sp], #4
800ae06: 4770 bx lr
800ae08: 40010000 .word 0x40010000
800ae0c: 40010400 .word 0x40010400
0800ae10 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800ae10: b480 push {r7}
800ae12: b083 sub sp, #12
800ae14: af00 add r7, sp, #0
800ae16: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
800ae18: bf00 nop
800ae1a: 370c adds r7, #12
800ae1c: 46bd mov sp, r7
800ae1e: f85d 7b04 ldr.w r7, [sp], #4
800ae22: 4770 bx lr
0800ae24 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800ae24: b480 push {r7}
800ae26: b083 sub sp, #12
800ae28: af00 add r7, sp, #0
800ae2a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
800ae2c: bf00 nop
800ae2e: 370c adds r7, #12
800ae30: 46bd mov sp, r7
800ae32: f85d 7b04 ldr.w r7, [sp], #4
800ae36: 4770 bx lr
0800ae38 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
800ae38: b480 push {r7}
800ae3a: b083 sub sp, #12
800ae3c: af00 add r7, sp, #0
800ae3e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
800ae40: bf00 nop
800ae42: 370c adds r7, #12
800ae44: 46bd mov sp, r7
800ae46: f85d 7b04 ldr.w r7, [sp], #4
800ae4a: 4770 bx lr
0800ae4c <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
800ae4c: b480 push {r7}
800ae4e: b085 sub sp, #20
800ae50: af00 add r7, sp, #0
800ae52: 6078 str r0, [r7, #4]
800ae54: 6039 str r1, [r7, #0]
uint32_t tmpr1 = 0;
800ae56: 2300 movs r3, #0
800ae58: 60fb str r3, [r7, #12]
uint32_t tmpr2 = 0;
800ae5a: 2300 movs r3, #0
800ae5c: 60bb str r3, [r7, #8]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
800ae5e: 683b ldr r3, [r7, #0]
800ae60: 681b ldr r3, [r3, #0]
800ae62: 2b01 cmp r3, #1
800ae64: d027 beq.n 800aeb6 <FMC_SDRAM_Init+0x6a>
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800ae66: 687b ldr r3, [r7, #4]
800ae68: 681b ldr r3, [r3, #0]
800ae6a: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800ae6c: 68fa ldr r2, [r7, #12]
800ae6e: 4b2f ldr r3, [pc, #188] ; (800af2c <FMC_SDRAM_Init+0xe0>)
800ae70: 4013 ands r3, r2
800ae72: 60fb str r3, [r7, #12]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ae74: 683b ldr r3, [r7, #0]
800ae76: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800ae78: 683b ldr r3, [r7, #0]
800ae7a: 689b ldr r3, [r3, #8]
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800ae7c: 431a orrs r2, r3
Init->MemoryDataWidth |\
800ae7e: 683b ldr r3, [r7, #0]
800ae80: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800ae82: 431a orrs r2, r3
Init->InternalBankNumber |\
800ae84: 683b ldr r3, [r7, #0]
800ae86: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800ae88: 431a orrs r2, r3
Init->CASLatency |\
800ae8a: 683b ldr r3, [r7, #0]
800ae8c: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800ae8e: 431a orrs r2, r3
Init->WriteProtection |\
800ae90: 683b ldr r3, [r7, #0]
800ae92: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800ae94: 431a orrs r2, r3
Init->SDClockPeriod |\
800ae96: 683b ldr r3, [r7, #0]
800ae98: 69db ldr r3, [r3, #28]
Init->WriteProtection |\
800ae9a: 431a orrs r2, r3
Init->ReadBurst |\
800ae9c: 683b ldr r3, [r7, #0]
800ae9e: 6a1b ldr r3, [r3, #32]
Init->SDClockPeriod |\
800aea0: 431a orrs r2, r3
Init->ReadPipeDelay
800aea2: 683b ldr r3, [r7, #0]
800aea4: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800aea6: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800aea8: 68fa ldr r2, [r7, #12]
800aeaa: 4313 orrs r3, r2
800aeac: 60fb str r3, [r7, #12]
);
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800aeae: 687b ldr r3, [r7, #4]
800aeb0: 68fa ldr r2, [r7, #12]
800aeb2: 601a str r2, [r3, #0]
800aeb4: e032 b.n 800af1c <FMC_SDRAM_Init+0xd0>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800aeb6: 687b ldr r3, [r7, #4]
800aeb8: 681b ldr r3, [r3, #0]
800aeba: 60fb str r3, [r7, #12]
/* Clear SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
800aebc: 68fb ldr r3, [r7, #12]
800aebe: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
800aec2: 60fb str r3, [r7, #12]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aec4: 683b ldr r3, [r7, #0]
800aec6: 69da ldr r2, [r3, #28]
Init->ReadBurst |\
800aec8: 683b ldr r3, [r7, #0]
800aeca: 6a1b ldr r3, [r3, #32]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aecc: 431a orrs r2, r3
Init->ReadPipeDelay);
800aece: 683b ldr r3, [r7, #0]
800aed0: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800aed2: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800aed4: 68fa ldr r2, [r7, #12]
800aed6: 4313 orrs r3, r2
800aed8: 60fb str r3, [r7, #12]
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
800aeda: 687b ldr r3, [r7, #4]
800aedc: 685b ldr r3, [r3, #4]
800aede: 60bb str r3, [r7, #8]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800aee0: 68ba ldr r2, [r7, #8]
800aee2: 4b12 ldr r3, [pc, #72] ; (800af2c <FMC_SDRAM_Init+0xe0>)
800aee4: 4013 ands r3, r2
800aee6: 60bb str r3, [r7, #8]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800aee8: 683b ldr r3, [r7, #0]
800aeea: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800aeec: 683b ldr r3, [r7, #0]
800aeee: 689b ldr r3, [r3, #8]
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800aef0: 431a orrs r2, r3
Init->MemoryDataWidth |\
800aef2: 683b ldr r3, [r7, #0]
800aef4: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800aef6: 431a orrs r2, r3
Init->InternalBankNumber |\
800aef8: 683b ldr r3, [r7, #0]
800aefa: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800aefc: 431a orrs r2, r3
Init->CASLatency |\
800aefe: 683b ldr r3, [r7, #0]
800af00: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800af02: 431a orrs r2, r3
Init->WriteProtection);
800af04: 683b ldr r3, [r7, #0]
800af06: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800af08: 4313 orrs r3, r2
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800af0a: 68ba ldr r2, [r7, #8]
800af0c: 4313 orrs r3, r2
800af0e: 60bb str r3, [r7, #8]
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800af10: 687b ldr r3, [r7, #4]
800af12: 68fa ldr r2, [r7, #12]
800af14: 601a str r2, [r3, #0]
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
800af16: 687b ldr r3, [r7, #4]
800af18: 68ba ldr r2, [r7, #8]
800af1a: 605a str r2, [r3, #4]
}
return HAL_OK;
800af1c: 2300 movs r3, #0
}
800af1e: 4618 mov r0, r3
800af20: 3714 adds r7, #20
800af22: 46bd mov sp, r7
800af24: f85d 7b04 ldr.w r7, [sp], #4
800af28: 4770 bx lr
800af2a: bf00 nop
800af2c: ffff8000 .word 0xffff8000
0800af30 <FMC_SDRAM_Timing_Init>:
* @param Timing Pointer to SDRAM Timing structure
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
800af30: b480 push {r7}
800af32: b087 sub sp, #28
800af34: af00 add r7, sp, #0
800af36: 60f8 str r0, [r7, #12]
800af38: 60b9 str r1, [r7, #8]
800af3a: 607a str r2, [r7, #4]
uint32_t tmpr1 = 0;
800af3c: 2300 movs r3, #0
800af3e: 617b str r3, [r7, #20]
uint32_t tmpr2 = 0;
800af40: 2300 movs r3, #0
800af42: 613b str r3, [r7, #16]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
800af44: 687b ldr r3, [r7, #4]
800af46: 2b01 cmp r3, #1
800af48: d02e beq.n 800afa8 <FMC_SDRAM_Timing_Init+0x78>
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800af4a: 68fb ldr r3, [r7, #12]
800af4c: 689b ldr r3, [r3, #8]
800af4e: 617b str r3, [r7, #20]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800af50: 697b ldr r3, [r7, #20]
800af52: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800af56: 617b str r3, [r7, #20]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af58: 68bb ldr r3, [r7, #8]
800af5a: 681b ldr r3, [r3, #0]
800af5c: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800af5e: 68bb ldr r3, [r7, #8]
800af60: 685b ldr r3, [r3, #4]
800af62: 3b01 subs r3, #1
800af64: 011b lsls r3, r3, #4
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af66: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800af68: 68bb ldr r3, [r7, #8]
800af6a: 689b ldr r3, [r3, #8]
800af6c: 3b01 subs r3, #1
800af6e: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800af70: 431a orrs r2, r3
(((Timing->RowCycleDelay)-1) << 12) |\
800af72: 68bb ldr r3, [r7, #8]
800af74: 68db ldr r3, [r3, #12]
800af76: 3b01 subs r3, #1
800af78: 031b lsls r3, r3, #12
(((Timing->SelfRefreshTime)-1) << 8) |\
800af7a: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800af7c: 68bb ldr r3, [r7, #8]
800af7e: 691b ldr r3, [r3, #16]
800af80: 3b01 subs r3, #1
800af82: 041b lsls r3, r3, #16
(((Timing->RowCycleDelay)-1) << 12) |\
800af84: 431a orrs r2, r3
(((Timing->RPDelay)-1) << 20) |\
800af86: 68bb ldr r3, [r7, #8]
800af88: 695b ldr r3, [r3, #20]
800af8a: 3b01 subs r3, #1
800af8c: 051b lsls r3, r3, #20
(((Timing->WriteRecoveryTime)-1) <<16) |\
800af8e: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800af90: 68bb ldr r3, [r7, #8]
800af92: 699b ldr r3, [r3, #24]
800af94: 3b01 subs r3, #1
800af96: 061b lsls r3, r3, #24
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800af98: 4313 orrs r3, r2
800af9a: 697a ldr r2, [r7, #20]
800af9c: 4313 orrs r3, r2
800af9e: 617b str r3, [r7, #20]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800afa0: 68fb ldr r3, [r7, #12]
800afa2: 697a ldr r2, [r7, #20]
800afa4: 609a str r2, [r3, #8]
800afa6: e039 b.n 800b01c <FMC_SDRAM_Timing_Init+0xec>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800afa8: 68fb ldr r3, [r7, #12]
800afaa: 689b ldr r3, [r3, #8]
800afac: 617b str r3, [r7, #20]
/* Clear TRC and TRP bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
800afae: 697a ldr r2, [r7, #20]
800afb0: 4b1e ldr r3, [pc, #120] ; (800b02c <FMC_SDRAM_Timing_Init+0xfc>)
800afb2: 4013 ands r3, r2
800afb4: 617b str r3, [r7, #20]
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800afb6: 68bb ldr r3, [r7, #8]
800afb8: 68db ldr r3, [r3, #12]
800afba: 3b01 subs r3, #1
800afbc: 031a lsls r2, r3, #12
(((Timing->RPDelay)-1) << 20));
800afbe: 68bb ldr r3, [r7, #8]
800afc0: 695b ldr r3, [r3, #20]
800afc2: 3b01 subs r3, #1
800afc4: 051b lsls r3, r3, #20
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800afc6: 4313 orrs r3, r2
800afc8: 697a ldr r2, [r7, #20]
800afca: 4313 orrs r3, r2
800afcc: 617b str r3, [r7, #20]
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
800afce: 68fb ldr r3, [r7, #12]
800afd0: 68db ldr r3, [r3, #12]
800afd2: 613b str r3, [r7, #16]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800afd4: 693b ldr r3, [r7, #16]
800afd6: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800afda: 613b str r3, [r7, #16]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800afdc: 68bb ldr r3, [r7, #8]
800afde: 681b ldr r3, [r3, #0]
800afe0: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800afe2: 68bb ldr r3, [r7, #8]
800afe4: 685b ldr r3, [r3, #4]
800afe6: 3b01 subs r3, #1
800afe8: 011b lsls r3, r3, #4
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800afea: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800afec: 68bb ldr r3, [r7, #8]
800afee: 689b ldr r3, [r3, #8]
800aff0: 3b01 subs r3, #1
800aff2: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800aff4: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800aff6: 68bb ldr r3, [r7, #8]
800aff8: 691b ldr r3, [r3, #16]
800affa: 3b01 subs r3, #1
800affc: 041b lsls r3, r3, #16
(((Timing->SelfRefreshTime)-1) << 8) |\
800affe: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800b000: 68bb ldr r3, [r7, #8]
800b002: 699b ldr r3, [r3, #24]
800b004: 3b01 subs r3, #1
800b006: 061b lsls r3, r3, #24
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800b008: 4313 orrs r3, r2
800b00a: 693a ldr r2, [r7, #16]
800b00c: 4313 orrs r3, r2
800b00e: 613b str r3, [r7, #16]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800b010: 68fb ldr r3, [r7, #12]
800b012: 697a ldr r2, [r7, #20]
800b014: 609a str r2, [r3, #8]
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
800b016: 68fb ldr r3, [r7, #12]
800b018: 693a ldr r2, [r7, #16]
800b01a: 60da str r2, [r3, #12]
}
return HAL_OK;
800b01c: 2300 movs r3, #0
}
800b01e: 4618 mov r0, r3
800b020: 371c adds r7, #28
800b022: 46bd mov sp, r7
800b024: f85d 7b04 ldr.w r7, [sp], #4
800b028: 4770 bx lr
800b02a: bf00 nop
800b02c: ff0f0fff .word 0xff0f0fff
0800b030 <FMC_SDRAM_SendCommand>:
* @param Timing Pointer to SDRAM Timing structure
* @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
800b030: b480 push {r7}
800b032: b087 sub sp, #28
800b034: af00 add r7, sp, #0
800b036: 60f8 str r0, [r7, #12]
800b038: 60b9 str r1, [r7, #8]
800b03a: 607a str r2, [r7, #4]
__IO uint32_t tmpr = 0;
800b03c: 2300 movs r3, #0
800b03e: 617b str r3, [r7, #20]
assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
tmpr = (uint32_t)((Command->CommandMode) |\
800b040: 68bb ldr r3, [r7, #8]
800b042: 681a ldr r2, [r3, #0]
(Command->CommandTarget) |\
800b044: 68bb ldr r3, [r7, #8]
800b046: 685b ldr r3, [r3, #4]
tmpr = (uint32_t)((Command->CommandMode) |\
800b048: 431a orrs r2, r3
(((Command->AutoRefreshNumber)-1) << 5) |\
800b04a: 68bb ldr r3, [r7, #8]
800b04c: 689b ldr r3, [r3, #8]
800b04e: 3b01 subs r3, #1
800b050: 015b lsls r3, r3, #5
(Command->CommandTarget) |\
800b052: 431a orrs r2, r3
((Command->ModeRegisterDefinition) << 9)
800b054: 68bb ldr r3, [r7, #8]
800b056: 68db ldr r3, [r3, #12]
800b058: 025b lsls r3, r3, #9
tmpr = (uint32_t)((Command->CommandMode) |\
800b05a: 4313 orrs r3, r2
800b05c: 617b str r3, [r7, #20]
);
Device->SDCMR = tmpr;
800b05e: 697a ldr r2, [r7, #20]
800b060: 68fb ldr r3, [r7, #12]
800b062: 611a str r2, [r3, #16]
return HAL_OK;
800b064: 2300 movs r3, #0
}
800b066: 4618 mov r0, r3
800b068: 371c adds r7, #28
800b06a: 46bd mov sp, r7
800b06c: f85d 7b04 ldr.w r7, [sp], #4
800b070: 4770 bx lr
0800b072 <FMC_SDRAM_ProgramRefreshRate>:
* @param Device Pointer to SDRAM device instance
* @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
{
800b072: b480 push {r7}
800b074: b083 sub sp, #12
800b076: af00 add r7, sp, #0
800b078: 6078 str r0, [r7, #4]
800b07a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
/* Set the refresh rate in command register */
Device->SDRTR |= (RefreshRate<<1);
800b07c: 687b ldr r3, [r7, #4]
800b07e: 695a ldr r2, [r3, #20]
800b080: 683b ldr r3, [r7, #0]
800b082: 005b lsls r3, r3, #1
800b084: 431a orrs r2, r3
800b086: 687b ldr r3, [r7, #4]
800b088: 615a str r2, [r3, #20]
return HAL_OK;
800b08a: 2300 movs r3, #0
}
800b08c: 4618 mov r0, r3
800b08e: 370c adds r7, #12
800b090: 46bd mov sp, r7
800b092: f85d 7b04 ldr.w r7, [sp], #4
800b096: 4770 bx lr
0800b098 <MX_LWIP_Init>:
/**
* LwIP initialization function
*/
void MX_LWIP_Init(void)
{
800b098: b5b0 push {r4, r5, r7, lr}
800b09a: b08e sub sp, #56 ; 0x38
800b09c: af04 add r7, sp, #16
/* Initilialize the LwIP stack with RTOS */
tcpip_init( NULL, NULL );
800b09e: 2100 movs r1, #0
800b0a0: 2000 movs r0, #0
800b0a2: f003 feab bl 800edfc <tcpip_init>
/* IP addresses initialization with DHCP (IPv4) */
ipaddr.addr = 0;
800b0a6: 4b2a ldr r3, [pc, #168] ; (800b150 <MX_LWIP_Init+0xb8>)
800b0a8: 2200 movs r2, #0
800b0aa: 601a str r2, [r3, #0]
netmask.addr = 0;
800b0ac: 4b29 ldr r3, [pc, #164] ; (800b154 <MX_LWIP_Init+0xbc>)
800b0ae: 2200 movs r2, #0
800b0b0: 601a str r2, [r3, #0]
gw.addr = 0;
800b0b2: 4b29 ldr r3, [pc, #164] ; (800b158 <MX_LWIP_Init+0xc0>)
800b0b4: 2200 movs r2, #0
800b0b6: 601a str r2, [r3, #0]
/* add the network interface (IPv4/IPv6) with RTOS */
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, &ethernetif_init, &tcpip_input);
800b0b8: 4b28 ldr r3, [pc, #160] ; (800b15c <MX_LWIP_Init+0xc4>)
800b0ba: 9302 str r3, [sp, #8]
800b0bc: 4b28 ldr r3, [pc, #160] ; (800b160 <MX_LWIP_Init+0xc8>)
800b0be: 9301 str r3, [sp, #4]
800b0c0: 2300 movs r3, #0
800b0c2: 9300 str r3, [sp, #0]
800b0c4: 4b24 ldr r3, [pc, #144] ; (800b158 <MX_LWIP_Init+0xc0>)
800b0c6: 4a23 ldr r2, [pc, #140] ; (800b154 <MX_LWIP_Init+0xbc>)
800b0c8: 4921 ldr r1, [pc, #132] ; (800b150 <MX_LWIP_Init+0xb8>)
800b0ca: 4826 ldr r0, [pc, #152] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0cc: f004 fc1a bl 800f904 <netif_add>
/* Registers the default network interface */
netif_set_default(&gnetif);
800b0d0: 4824 ldr r0, [pc, #144] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0d2: f004 fdd1 bl 800fc78 <netif_set_default>
if (netif_is_link_up(&gnetif))
800b0d6: 4b23 ldr r3, [pc, #140] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0d8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b0dc: 089b lsrs r3, r3, #2
800b0de: f003 0301 and.w r3, r3, #1
800b0e2: b2db uxtb r3, r3
800b0e4: 2b00 cmp r3, #0
800b0e6: d003 beq.n 800b0f0 <MX_LWIP_Init+0x58>
{
/* When the netif is fully configured this function must be called */
netif_set_up(&gnetif);
800b0e8: 481e ldr r0, [pc, #120] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0ea: f004 fdd5 bl 800fc98 <netif_set_up>
800b0ee: e002 b.n 800b0f6 <MX_LWIP_Init+0x5e>
}
else
{
/* When the netif link is down this function must be called */
netif_set_down(&gnetif);
800b0f0: 481c ldr r0, [pc, #112] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0f2: f004 fe3d bl 800fd70 <netif_set_down>
}
/* Set the link callback function, this function is called on change of link status*/
netif_set_link_callback(&gnetif, ethernetif_update_config);
800b0f6: 491c ldr r1, [pc, #112] ; (800b168 <MX_LWIP_Init+0xd0>)
800b0f8: 481a ldr r0, [pc, #104] ; (800b164 <MX_LWIP_Init+0xcc>)
800b0fa: f004 fed3 bl 800fea4 <netif_set_link_callback>
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(Netif_SEM);
800b0fe: 2300 movs r3, #0
800b100: 623b str r3, [r7, #32]
800b102: 2300 movs r3, #0
800b104: 627b str r3, [r7, #36] ; 0x24
Netif_LinkSemaphore = osSemaphoreCreate(osSemaphore(Netif_SEM) , 1 );
800b106: f107 0320 add.w r3, r7, #32
800b10a: 2101 movs r1, #1
800b10c: 4618 mov r0, r3
800b10e: f000 fd75 bl 800bbfc <osSemaphoreCreate>
800b112: 4602 mov r2, r0
800b114: 4b15 ldr r3, [pc, #84] ; (800b16c <MX_LWIP_Init+0xd4>)
800b116: 601a str r2, [r3, #0]
link_arg.netif = &gnetif;
800b118: 4b15 ldr r3, [pc, #84] ; (800b170 <MX_LWIP_Init+0xd8>)
800b11a: 4a12 ldr r2, [pc, #72] ; (800b164 <MX_LWIP_Init+0xcc>)
800b11c: 601a str r2, [r3, #0]
link_arg.semaphore = Netif_LinkSemaphore;
800b11e: 4b13 ldr r3, [pc, #76] ; (800b16c <MX_LWIP_Init+0xd4>)
800b120: 681b ldr r3, [r3, #0]
800b122: 4a13 ldr r2, [pc, #76] ; (800b170 <MX_LWIP_Init+0xd8>)
800b124: 6053 str r3, [r2, #4]
/* Create the Ethernet link handler thread */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(LinkThr, ethernetif_set_link, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE * 2);
800b126: 4b13 ldr r3, [pc, #76] ; (800b174 <MX_LWIP_Init+0xdc>)
800b128: 1d3c adds r4, r7, #4
800b12a: 461d mov r5, r3
800b12c: cd0f ldmia r5!, {r0, r1, r2, r3}
800b12e: c40f stmia r4!, {r0, r1, r2, r3}
800b130: e895 0007 ldmia.w r5, {r0, r1, r2}
800b134: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(LinkThr), &link_arg);
800b138: 1d3b adds r3, r7, #4
800b13a: 490d ldr r1, [pc, #52] ; (800b170 <MX_LWIP_Init+0xd8>)
800b13c: 4618 mov r0, r3
800b13e: f000 fc60 bl 800ba02 <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Start DHCP negotiation for a network interface (IPv4) */
dhcp_start(&gnetif);
800b142: 4808 ldr r0, [pc, #32] ; (800b164 <MX_LWIP_Init+0xcc>)
800b144: f00c f810 bl 8017168 <dhcp_start>
/* USER CODE BEGIN 3 */
/* USER CODE END 3 */
}
800b148: bf00 nop
800b14a: 3728 adds r7, #40 ; 0x28
800b14c: 46bd mov sp, r7
800b14e: bdb0 pop {r4, r5, r7, pc}
800b150: 20008d94 .word 0x20008d94
800b154: 20008d98 .word 0x20008d98
800b158: 20008d9c .word 0x20008d9c
800b15c: 0800ed39 .word 0x0800ed39
800b160: 0800b791 .word 0x0800b791
800b164: 20008d5c .word 0x20008d5c
800b168: 0800b875 .word 0x0800b875
800b16c: 20000584 .word 0x20000584
800b170: 20008d54 .word 0x20008d54
800b174: 0801bf48 .word 0x0801bf48
0800b178 <HAL_ETH_MspInit>:
/* USER CODE END 3 */
/* Private functions ---------------------------------------------------------*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
{
800b178: b580 push {r7, lr}
800b17a: b08e sub sp, #56 ; 0x38
800b17c: af00 add r7, sp, #0
800b17e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800b180: f107 0324 add.w r3, r7, #36 ; 0x24
800b184: 2200 movs r2, #0
800b186: 601a str r2, [r3, #0]
800b188: 605a str r2, [r3, #4]
800b18a: 609a str r2, [r3, #8]
800b18c: 60da str r2, [r3, #12]
800b18e: 611a str r2, [r3, #16]
if(ethHandle->Instance==ETH)
800b190: 687b ldr r3, [r7, #4]
800b192: 681b ldr r3, [r3, #0]
800b194: 4a44 ldr r2, [pc, #272] ; (800b2a8 <HAL_ETH_MspInit+0x130>)
800b196: 4293 cmp r3, r2
800b198: f040 8081 bne.w 800b29e <HAL_ETH_MspInit+0x126>
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Enable Peripheral clock */
__HAL_RCC_ETH_CLK_ENABLE();
800b19c: 4b43 ldr r3, [pc, #268] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b19e: 6b1b ldr r3, [r3, #48] ; 0x30
800b1a0: 4a42 ldr r2, [pc, #264] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1a2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800b1a6: 6313 str r3, [r2, #48] ; 0x30
800b1a8: 4b40 ldr r3, [pc, #256] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1aa: 6b1b ldr r3, [r3, #48] ; 0x30
800b1ac: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800b1b0: 623b str r3, [r7, #32]
800b1b2: 6a3b ldr r3, [r7, #32]
800b1b4: 4b3d ldr r3, [pc, #244] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1b6: 6b1b ldr r3, [r3, #48] ; 0x30
800b1b8: 4a3c ldr r2, [pc, #240] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1ba: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800b1be: 6313 str r3, [r2, #48] ; 0x30
800b1c0: 4b3a ldr r3, [pc, #232] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1c2: 6b1b ldr r3, [r3, #48] ; 0x30
800b1c4: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800b1c8: 61fb str r3, [r7, #28]
800b1ca: 69fb ldr r3, [r7, #28]
800b1cc: 4b37 ldr r3, [pc, #220] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1ce: 6b1b ldr r3, [r3, #48] ; 0x30
800b1d0: 4a36 ldr r2, [pc, #216] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1d2: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
800b1d6: 6313 str r3, [r2, #48] ; 0x30
800b1d8: 4b34 ldr r3, [pc, #208] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1da: 6b1b ldr r3, [r3, #48] ; 0x30
800b1dc: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
800b1e0: 61bb str r3, [r7, #24]
800b1e2: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOG_CLK_ENABLE();
800b1e4: 4b31 ldr r3, [pc, #196] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1e6: 6b1b ldr r3, [r3, #48] ; 0x30
800b1e8: 4a30 ldr r2, [pc, #192] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1ea: f043 0340 orr.w r3, r3, #64 ; 0x40
800b1ee: 6313 str r3, [r2, #48] ; 0x30
800b1f0: 4b2e ldr r3, [pc, #184] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1f2: 6b1b ldr r3, [r3, #48] ; 0x30
800b1f4: f003 0340 and.w r3, r3, #64 ; 0x40
800b1f8: 617b str r3, [r7, #20]
800b1fa: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
800b1fc: 4b2b ldr r3, [pc, #172] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b1fe: 6b1b ldr r3, [r3, #48] ; 0x30
800b200: 4a2a ldr r2, [pc, #168] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b202: f043 0304 orr.w r3, r3, #4
800b206: 6313 str r3, [r2, #48] ; 0x30
800b208: 4b28 ldr r3, [pc, #160] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b20a: 6b1b ldr r3, [r3, #48] ; 0x30
800b20c: f003 0304 and.w r3, r3, #4
800b210: 613b str r3, [r7, #16]
800b212: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800b214: 4b25 ldr r3, [pc, #148] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b216: 6b1b ldr r3, [r3, #48] ; 0x30
800b218: 4a24 ldr r2, [pc, #144] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b21a: f043 0301 orr.w r3, r3, #1
800b21e: 6313 str r3, [r2, #48] ; 0x30
800b220: 4b22 ldr r3, [pc, #136] ; (800b2ac <HAL_ETH_MspInit+0x134>)
800b222: 6b1b ldr r3, [r3, #48] ; 0x30
800b224: f003 0301 and.w r3, r3, #1
800b228: 60fb str r3, [r7, #12]
800b22a: 68fb ldr r3, [r7, #12]
PC4 ------> ETH_RXD0
PA2 ------> ETH_MDIO
PC5 ------> ETH_RXD1
PA7 ------> ETH_CRS_DV
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11;
800b22c: f44f 43d0 mov.w r3, #26624 ; 0x6800
800b230: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b232: 2302 movs r3, #2
800b234: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b236: 2300 movs r3, #0
800b238: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b23a: 2303 movs r3, #3
800b23c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b23e: 230b movs r3, #11
800b240: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800b242: f107 0324 add.w r3, r7, #36 ; 0x24
800b246: 4619 mov r1, r3
800b248: 4819 ldr r0, [pc, #100] ; (800b2b0 <HAL_ETH_MspInit+0x138>)
800b24a: f7fc f819 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
800b24e: 2332 movs r3, #50 ; 0x32
800b250: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b252: 2302 movs r3, #2
800b254: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b256: 2300 movs r3, #0
800b258: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b25a: 2303 movs r3, #3
800b25c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b25e: 230b movs r3, #11
800b260: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800b262: f107 0324 add.w r3, r7, #36 ; 0x24
800b266: 4619 mov r1, r3
800b268: 4812 ldr r0, [pc, #72] ; (800b2b4 <HAL_ETH_MspInit+0x13c>)
800b26a: f7fc f809 bl 8007280 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
800b26e: 2386 movs r3, #134 ; 0x86
800b270: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800b272: 2302 movs r3, #2
800b274: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800b276: 2300 movs r3, #0
800b278: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800b27a: 2303 movs r3, #3
800b27c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
800b27e: 230b movs r3, #11
800b280: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800b282: f107 0324 add.w r3, r7, #36 ; 0x24
800b286: 4619 mov r1, r3
800b288: 480b ldr r0, [pc, #44] ; (800b2b8 <HAL_ETH_MspInit+0x140>)
800b28a: f7fb fff9 bl 8007280 <HAL_GPIO_Init>
/* Peripheral interrupt init */
HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
800b28e: 2200 movs r2, #0
800b290: 2105 movs r1, #5
800b292: 203d movs r0, #61 ; 0x3d
800b294: f7fa f844 bl 8005320 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ETH_IRQn);
800b298: 203d movs r0, #61 ; 0x3d
800b29a: f7fa f85d bl 8005358 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
800b29e: bf00 nop
800b2a0: 3738 adds r7, #56 ; 0x38
800b2a2: 46bd mov sp, r7
800b2a4: bd80 pop {r7, pc}
800b2a6: bf00 nop
800b2a8: 40028000 .word 0x40028000
800b2ac: 40023800 .word 0x40023800
800b2b0: 40021800 .word 0x40021800
800b2b4: 40020800 .word 0x40020800
800b2b8: 40020000 .word 0x40020000
0800b2bc <HAL_ETH_RxCpltCallback>:
* @brief Ethernet Rx Transfer completed callback
* @param heth: ETH handle
* @retval None
*/
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
800b2bc: b580 push {r7, lr}
800b2be: b082 sub sp, #8
800b2c0: af00 add r7, sp, #0
800b2c2: 6078 str r0, [r7, #4]
osSemaphoreRelease(s_xSemaphore);
800b2c4: 4b04 ldr r3, [pc, #16] ; (800b2d8 <HAL_ETH_RxCpltCallback+0x1c>)
800b2c6: 681b ldr r3, [r3, #0]
800b2c8: 4618 mov r0, r3
800b2ca: f000 fd25 bl 800bd18 <osSemaphoreRelease>
}
800b2ce: bf00 nop
800b2d0: 3708 adds r7, #8
800b2d2: 46bd mov sp, r7
800b2d4: bd80 pop {r7, pc}
800b2d6: bf00 nop
800b2d8: 20000588 .word 0x20000588
0800b2dc <low_level_init>:
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
800b2dc: b5b0 push {r4, r5, r7, lr}
800b2de: b090 sub sp, #64 ; 0x40
800b2e0: af00 add r7, sp, #0
800b2e2: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b2e4: 2300 movs r3, #0
800b2e6: 63bb str r3, [r7, #56] ; 0x38
HAL_StatusTypeDef hal_eth_init_status;
/* Init ETH */
uint8_t MACAddr[6] ;
heth.Instance = ETH;
800b2e8: 4b60 ldr r3, [pc, #384] ; (800b46c <low_level_init+0x190>)
800b2ea: 4a61 ldr r2, [pc, #388] ; (800b470 <low_level_init+0x194>)
800b2ec: 601a str r2, [r3, #0]
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
800b2ee: 4b5f ldr r3, [pc, #380] ; (800b46c <low_level_init+0x190>)
800b2f0: 2201 movs r2, #1
800b2f2: 605a str r2, [r3, #4]
heth.Init.Speed = ETH_SPEED_100M;
800b2f4: 4b5d ldr r3, [pc, #372] ; (800b46c <low_level_init+0x190>)
800b2f6: f44f 4280 mov.w r2, #16384 ; 0x4000
800b2fa: 609a str r2, [r3, #8]
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b2fc: 4b5b ldr r3, [pc, #364] ; (800b46c <low_level_init+0x190>)
800b2fe: f44f 6200 mov.w r2, #2048 ; 0x800
800b302: 60da str r2, [r3, #12]
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
800b304: 4b59 ldr r3, [pc, #356] ; (800b46c <low_level_init+0x190>)
800b306: 2201 movs r2, #1
800b308: 821a strh r2, [r3, #16]
MACAddr[0] = 0x00;
800b30a: 2300 movs r3, #0
800b30c: f887 3030 strb.w r3, [r7, #48] ; 0x30
MACAddr[1] = 0x80;
800b310: 2380 movs r3, #128 ; 0x80
800b312: f887 3031 strb.w r3, [r7, #49] ; 0x31
MACAddr[2] = 0xE1;
800b316: 23e1 movs r3, #225 ; 0xe1
800b318: f887 3032 strb.w r3, [r7, #50] ; 0x32
MACAddr[3] = 0x00;
800b31c: 2300 movs r3, #0
800b31e: f887 3033 strb.w r3, [r7, #51] ; 0x33
MACAddr[4] = 0x00;
800b322: 2300 movs r3, #0
800b324: f887 3034 strb.w r3, [r7, #52] ; 0x34
MACAddr[5] = 0x00;
800b328: 2300 movs r3, #0
800b32a: f887 3035 strb.w r3, [r7, #53] ; 0x35
heth.Init.MACAddr = &MACAddr[0];
800b32e: 4a4f ldr r2, [pc, #316] ; (800b46c <low_level_init+0x190>)
800b330: f107 0330 add.w r3, r7, #48 ; 0x30
800b334: 6153 str r3, [r2, #20]
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
800b336: 4b4d ldr r3, [pc, #308] ; (800b46c <low_level_init+0x190>)
800b338: 2201 movs r2, #1
800b33a: 619a str r2, [r3, #24]
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
800b33c: 4b4b ldr r3, [pc, #300] ; (800b46c <low_level_init+0x190>)
800b33e: 2200 movs r2, #0
800b340: 61da str r2, [r3, #28]
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
800b342: 4b4a ldr r3, [pc, #296] ; (800b46c <low_level_init+0x190>)
800b344: f44f 0200 mov.w r2, #8388608 ; 0x800000
800b348: 621a str r2, [r3, #32]
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
hal_eth_init_status = HAL_ETH_Init(&heth);
800b34a: 4848 ldr r0, [pc, #288] ; (800b46c <low_level_init+0x190>)
800b34c: f7fa fe12 bl 8005f74 <HAL_ETH_Init>
800b350: 4603 mov r3, r0
800b352: f887 303f strb.w r3, [r7, #63] ; 0x3f
if (hal_eth_init_status == HAL_OK)
800b356: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
800b35a: 2b00 cmp r3, #0
800b35c: d108 bne.n 800b370 <low_level_init+0x94>
{
/* Set netif link flag */
netif->flags |= NETIF_FLAG_LINK_UP;
800b35e: 687b ldr r3, [r7, #4]
800b360: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b364: f043 0304 orr.w r3, r3, #4
800b368: b2da uxtb r2, r3
800b36a: 687b ldr r3, [r7, #4]
800b36c: f883 2031 strb.w r2, [r3, #49] ; 0x31
}
/* Initialize Tx Descriptors list: Chain Mode */
HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
800b370: 2304 movs r3, #4
800b372: 4a40 ldr r2, [pc, #256] ; (800b474 <low_level_init+0x198>)
800b374: 4940 ldr r1, [pc, #256] ; (800b478 <low_level_init+0x19c>)
800b376: 483d ldr r0, [pc, #244] ; (800b46c <low_level_init+0x190>)
800b378: f7fa ff98 bl 80062ac <HAL_ETH_DMATxDescListInit>
/* Initialize Rx Descriptors list: Chain Mode */
HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
800b37c: 2304 movs r3, #4
800b37e: 4a3f ldr r2, [pc, #252] ; (800b47c <low_level_init+0x1a0>)
800b380: 493f ldr r1, [pc, #252] ; (800b480 <low_level_init+0x1a4>)
800b382: 483a ldr r0, [pc, #232] ; (800b46c <low_level_init+0x190>)
800b384: f7fa fffb bl 800637e <HAL_ETH_DMARxDescListInit>
#if LWIP_ARP || LWIP_ETHERNET
/* set MAC hardware address length */
netif->hwaddr_len = ETH_HWADDR_LEN;
800b388: 687b ldr r3, [r7, #4]
800b38a: 2206 movs r2, #6
800b38c: f883 2030 strb.w r2, [r3, #48] ; 0x30
/* set MAC hardware address */
netif->hwaddr[0] = heth.Init.MACAddr[0];
800b390: 4b36 ldr r3, [pc, #216] ; (800b46c <low_level_init+0x190>)
800b392: 695b ldr r3, [r3, #20]
800b394: 781a ldrb r2, [r3, #0]
800b396: 687b ldr r3, [r7, #4]
800b398: f883 202a strb.w r2, [r3, #42] ; 0x2a
netif->hwaddr[1] = heth.Init.MACAddr[1];
800b39c: 4b33 ldr r3, [pc, #204] ; (800b46c <low_level_init+0x190>)
800b39e: 695b ldr r3, [r3, #20]
800b3a0: 785a ldrb r2, [r3, #1]
800b3a2: 687b ldr r3, [r7, #4]
800b3a4: f883 202b strb.w r2, [r3, #43] ; 0x2b
netif->hwaddr[2] = heth.Init.MACAddr[2];
800b3a8: 4b30 ldr r3, [pc, #192] ; (800b46c <low_level_init+0x190>)
800b3aa: 695b ldr r3, [r3, #20]
800b3ac: 789a ldrb r2, [r3, #2]
800b3ae: 687b ldr r3, [r7, #4]
800b3b0: f883 202c strb.w r2, [r3, #44] ; 0x2c
netif->hwaddr[3] = heth.Init.MACAddr[3];
800b3b4: 4b2d ldr r3, [pc, #180] ; (800b46c <low_level_init+0x190>)
800b3b6: 695b ldr r3, [r3, #20]
800b3b8: 78da ldrb r2, [r3, #3]
800b3ba: 687b ldr r3, [r7, #4]
800b3bc: f883 202d strb.w r2, [r3, #45] ; 0x2d
netif->hwaddr[4] = heth.Init.MACAddr[4];
800b3c0: 4b2a ldr r3, [pc, #168] ; (800b46c <low_level_init+0x190>)
800b3c2: 695b ldr r3, [r3, #20]
800b3c4: 791a ldrb r2, [r3, #4]
800b3c6: 687b ldr r3, [r7, #4]
800b3c8: f883 202e strb.w r2, [r3, #46] ; 0x2e
netif->hwaddr[5] = heth.Init.MACAddr[5];
800b3cc: 4b27 ldr r3, [pc, #156] ; (800b46c <low_level_init+0x190>)
800b3ce: 695b ldr r3, [r3, #20]
800b3d0: 795a ldrb r2, [r3, #5]
800b3d2: 687b ldr r3, [r7, #4]
800b3d4: f883 202f strb.w r2, [r3, #47] ; 0x2f
/* maximum transfer unit */
netif->mtu = 1500;
800b3d8: 687b ldr r3, [r7, #4]
800b3da: f240 52dc movw r2, #1500 ; 0x5dc
800b3de: 851a strh r2, [r3, #40] ; 0x28
/* Accept broadcast address and ARP traffic */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
#if LWIP_ARP
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
800b3e0: 687b ldr r3, [r7, #4]
800b3e2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b3e6: f043 030a orr.w r3, r3, #10
800b3ea: b2da uxtb r2, r3
800b3ec: 687b ldr r3, [r7, #4]
800b3ee: f883 2031 strb.w r2, [r3, #49] ; 0x31
#else
netif->flags |= NETIF_FLAG_BROADCAST;
#endif /* LWIP_ARP */
/* create a binary semaphore used for informing ethernetif of frame reception */
osSemaphoreDef(SEM);
800b3f2: 2300 movs r3, #0
800b3f4: 62bb str r3, [r7, #40] ; 0x28
800b3f6: 2300 movs r3, #0
800b3f8: 62fb str r3, [r7, #44] ; 0x2c
s_xSemaphore = osSemaphoreCreate(osSemaphore(SEM), 1);
800b3fa: f107 0328 add.w r3, r7, #40 ; 0x28
800b3fe: 2101 movs r1, #1
800b400: 4618 mov r0, r3
800b402: f000 fbfb bl 800bbfc <osSemaphoreCreate>
800b406: 4602 mov r2, r0
800b408: 4b1e ldr r3, [pc, #120] ; (800b484 <low_level_init+0x1a8>)
800b40a: 601a str r2, [r3, #0]
/* create the task that handles the ETH_MAC */
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
800b40c: 4b1e ldr r3, [pc, #120] ; (800b488 <low_level_init+0x1ac>)
800b40e: f107 040c add.w r4, r7, #12
800b412: 461d mov r5, r3
800b414: cd0f ldmia r5!, {r0, r1, r2, r3}
800b416: c40f stmia r4!, {r0, r1, r2, r3}
800b418: e895 0007 ldmia.w r5, {r0, r1, r2}
800b41c: e884 0007 stmia.w r4, {r0, r1, r2}
osThreadCreate (osThread(EthIf), netif);
800b420: f107 030c add.w r3, r7, #12
800b424: 6879 ldr r1, [r7, #4]
800b426: 4618 mov r0, r3
800b428: f000 faeb bl 800ba02 <osThreadCreate>
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
/* Enable MAC and DMA transmission and reception */
HAL_ETH_Start(&heth);
800b42c: 480f ldr r0, [pc, #60] ; (800b46c <low_level_init+0x190>)
800b42e: f7fb face bl 80069ce <HAL_ETH_Start>
/* USER CODE BEGIN PHY_PRE_CONFIG */
/* USER CODE END PHY_PRE_CONFIG */
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR, &regvalue);
800b432: f107 0338 add.w r3, r7, #56 ; 0x38
800b436: 461a mov r2, r3
800b438: 211d movs r1, #29
800b43a: 480c ldr r0, [pc, #48] ; (800b46c <low_level_init+0x190>)
800b43c: f7fb f9f9 bl 8006832 <HAL_ETH_ReadPHYRegister>
regvalue |= (PHY_ISFR_INT4);
800b440: 6bbb ldr r3, [r7, #56] ; 0x38
800b442: f043 030b orr.w r3, r3, #11
800b446: 63bb str r3, [r7, #56] ; 0x38
/* Enable Interrupt on change of link status */
HAL_ETH_WritePHYRegister(&heth, PHY_ISFR , regvalue );
800b448: 6bbb ldr r3, [r7, #56] ; 0x38
800b44a: 461a mov r2, r3
800b44c: 211d movs r1, #29
800b44e: 4807 ldr r0, [pc, #28] ; (800b46c <low_level_init+0x190>)
800b450: f7fb fa57 bl 8006902 <HAL_ETH_WritePHYRegister>
/* Read Register Configuration */
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , &regvalue);
800b454: f107 0338 add.w r3, r7, #56 ; 0x38
800b458: 461a mov r2, r3
800b45a: 211d movs r1, #29
800b45c: 4803 ldr r0, [pc, #12] ; (800b46c <low_level_init+0x190>)
800b45e: f7fb f9e8 bl 8006832 <HAL_ETH_ReadPHYRegister>
#endif /* LWIP_ARP || LWIP_ETHERNET */
/* USER CODE BEGIN LOW_LEVEL_INIT */
/* USER CODE END LOW_LEVEL_INIT */
}
800b462: bf00 nop
800b464: 3740 adds r7, #64 ; 0x40
800b466: 46bd mov sp, r7
800b468: bdb0 pop {r4, r5, r7, pc}
800b46a: bf00 nop
800b46c: 2000a670 .word 0x2000a670
800b470: 40028000 .word 0x40028000
800b474: 2000a6b8 .word 0x2000a6b8
800b478: 20008da0 .word 0x20008da0
800b47c: 20008e20 .word 0x20008e20
800b480: 2000a5f0 .word 0x2000a5f0
800b484: 20000588 .word 0x20000588
800b488: 0801bf6c .word 0x0801bf6c
0800b48c <low_level_output>:
* to become availale since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
800b48c: b580 push {r7, lr}
800b48e: b08a sub sp, #40 ; 0x28
800b490: af00 add r7, sp, #0
800b492: 6078 str r0, [r7, #4]
800b494: 6039 str r1, [r7, #0]
err_t errval;
struct pbuf *q;
uint8_t *buffer = (uint8_t *)(heth.TxDesc->Buffer1Addr);
800b496: 4b4b ldr r3, [pc, #300] ; (800b5c4 <low_level_output+0x138>)
800b498: 6adb ldr r3, [r3, #44] ; 0x2c
800b49a: 689b ldr r3, [r3, #8]
800b49c: 61fb str r3, [r7, #28]
__IO ETH_DMADescTypeDef *DmaTxDesc;
uint32_t framelength = 0;
800b49e: 2300 movs r3, #0
800b4a0: 617b str r3, [r7, #20]
uint32_t bufferoffset = 0;
800b4a2: 2300 movs r3, #0
800b4a4: 613b str r3, [r7, #16]
uint32_t byteslefttocopy = 0;
800b4a6: 2300 movs r3, #0
800b4a8: 60fb str r3, [r7, #12]
uint32_t payloadoffset = 0;
800b4aa: 2300 movs r3, #0
800b4ac: 60bb str r3, [r7, #8]
DmaTxDesc = heth.TxDesc;
800b4ae: 4b45 ldr r3, [pc, #276] ; (800b5c4 <low_level_output+0x138>)
800b4b0: 6adb ldr r3, [r3, #44] ; 0x2c
800b4b2: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b4b4: 2300 movs r3, #0
800b4b6: 613b str r3, [r7, #16]
/* copy frame from pbufs to driver buffers */
for(q = p; q != NULL; q = q->next)
800b4b8: 683b ldr r3, [r7, #0]
800b4ba: 623b str r3, [r7, #32]
800b4bc: e05a b.n 800b574 <low_level_output+0xe8>
{
/* Is this buffer available? If not, goto error */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b4be: 69bb ldr r3, [r7, #24]
800b4c0: 681b ldr r3, [r3, #0]
800b4c2: 2b00 cmp r3, #0
800b4c4: da03 bge.n 800b4ce <low_level_output+0x42>
{
errval = ERR_USE;
800b4c6: 23f8 movs r3, #248 ; 0xf8
800b4c8: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b4cc: e05c b.n 800b588 <low_level_output+0xfc>
}
/* Get bytes in current lwIP buffer */
byteslefttocopy = q->len;
800b4ce: 6a3b ldr r3, [r7, #32]
800b4d0: 895b ldrh r3, [r3, #10]
800b4d2: 60fb str r3, [r7, #12]
payloadoffset = 0;
800b4d4: 2300 movs r3, #0
800b4d6: 60bb str r3, [r7, #8]
/* Check if the length of data to copy is bigger than Tx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b4d8: e02f b.n 800b53a <low_level_output+0xae>
{
/* Copy data to Tx buffer*/
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
800b4da: 69fa ldr r2, [r7, #28]
800b4dc: 693b ldr r3, [r7, #16]
800b4de: 18d0 adds r0, r2, r3
800b4e0: 6a3b ldr r3, [r7, #32]
800b4e2: 685a ldr r2, [r3, #4]
800b4e4: 68bb ldr r3, [r7, #8]
800b4e6: 18d1 adds r1, r2, r3
800b4e8: 693a ldr r2, [r7, #16]
800b4ea: f240 53f4 movw r3, #1524 ; 0x5f4
800b4ee: 1a9b subs r3, r3, r2
800b4f0: 461a mov r2, r3
800b4f2: f00f fd84 bl 801affe <memcpy>
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
800b4f6: 69bb ldr r3, [r7, #24]
800b4f8: 68db ldr r3, [r3, #12]
800b4fa: 61bb str r3, [r7, #24]
/* Check if the buffer is available */
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
800b4fc: 69bb ldr r3, [r7, #24]
800b4fe: 681b ldr r3, [r3, #0]
800b500: 2b00 cmp r3, #0
800b502: da03 bge.n 800b50c <low_level_output+0x80>
{
errval = ERR_USE;
800b504: 23f8 movs r3, #248 ; 0xf8
800b506: f887 3027 strb.w r3, [r7, #39] ; 0x27
goto error;
800b50a: e03d b.n 800b588 <low_level_output+0xfc>
}
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
800b50c: 69bb ldr r3, [r7, #24]
800b50e: 689b ldr r3, [r3, #8]
800b510: 61fb str r3, [r7, #28]
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
800b512: 693a ldr r2, [r7, #16]
800b514: 68fb ldr r3, [r7, #12]
800b516: 4413 add r3, r2
800b518: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b51c: 60fb str r3, [r7, #12]
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
800b51e: 68ba ldr r2, [r7, #8]
800b520: 693b ldr r3, [r7, #16]
800b522: 1ad3 subs r3, r2, r3
800b524: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b528: 60bb str r3, [r7, #8]
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
800b52a: 697a ldr r2, [r7, #20]
800b52c: 693b ldr r3, [r7, #16]
800b52e: 1ad3 subs r3, r2, r3
800b530: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b534: 617b str r3, [r7, #20]
bufferoffset = 0;
800b536: 2300 movs r3, #0
800b538: 613b str r3, [r7, #16]
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
800b53a: 68fa ldr r2, [r7, #12]
800b53c: 693b ldr r3, [r7, #16]
800b53e: 4413 add r3, r2
800b540: f240 52f4 movw r2, #1524 ; 0x5f4
800b544: 4293 cmp r3, r2
800b546: d8c8 bhi.n 800b4da <low_level_output+0x4e>
}
/* Copy the remaining bytes */
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
800b548: 69fa ldr r2, [r7, #28]
800b54a: 693b ldr r3, [r7, #16]
800b54c: 18d0 adds r0, r2, r3
800b54e: 6a3b ldr r3, [r7, #32]
800b550: 685a ldr r2, [r3, #4]
800b552: 68bb ldr r3, [r7, #8]
800b554: 4413 add r3, r2
800b556: 68fa ldr r2, [r7, #12]
800b558: 4619 mov r1, r3
800b55a: f00f fd50 bl 801affe <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b55e: 693a ldr r2, [r7, #16]
800b560: 68fb ldr r3, [r7, #12]
800b562: 4413 add r3, r2
800b564: 613b str r3, [r7, #16]
framelength = framelength + byteslefttocopy;
800b566: 697a ldr r2, [r7, #20]
800b568: 68fb ldr r3, [r7, #12]
800b56a: 4413 add r3, r2
800b56c: 617b str r3, [r7, #20]
for(q = p; q != NULL; q = q->next)
800b56e: 6a3b ldr r3, [r7, #32]
800b570: 681b ldr r3, [r3, #0]
800b572: 623b str r3, [r7, #32]
800b574: 6a3b ldr r3, [r7, #32]
800b576: 2b00 cmp r3, #0
800b578: d1a1 bne.n 800b4be <low_level_output+0x32>
}
/* Prepare transmit descriptors to give to DMA */
HAL_ETH_TransmitFrame(&heth, framelength);
800b57a: 6979 ldr r1, [r7, #20]
800b57c: 4811 ldr r0, [pc, #68] ; (800b5c4 <low_level_output+0x138>)
800b57e: f7fa ff6b bl 8006458 <HAL_ETH_TransmitFrame>
errval = ERR_OK;
800b582: 2300 movs r3, #0
800b584: f887 3027 strb.w r3, [r7, #39] ; 0x27
error:
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
800b588: 4b0e ldr r3, [pc, #56] ; (800b5c4 <low_level_output+0x138>)
800b58a: 681a ldr r2, [r3, #0]
800b58c: f241 0314 movw r3, #4116 ; 0x1014
800b590: 4413 add r3, r2
800b592: 681b ldr r3, [r3, #0]
800b594: f003 0320 and.w r3, r3, #32
800b598: 2b00 cmp r3, #0
800b59a: d00d beq.n 800b5b8 <low_level_output+0x12c>
{
/* Clear TUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_TUS;
800b59c: 4b09 ldr r3, [pc, #36] ; (800b5c4 <low_level_output+0x138>)
800b59e: 681a ldr r2, [r3, #0]
800b5a0: f241 0314 movw r3, #4116 ; 0x1014
800b5a4: 4413 add r3, r2
800b5a6: 2220 movs r2, #32
800b5a8: 601a str r2, [r3, #0]
/* Resume DMA transmission*/
heth.Instance->DMATPDR = 0;
800b5aa: 4b06 ldr r3, [pc, #24] ; (800b5c4 <low_level_output+0x138>)
800b5ac: 681a ldr r2, [r3, #0]
800b5ae: f241 0304 movw r3, #4100 ; 0x1004
800b5b2: 4413 add r3, r2
800b5b4: 2200 movs r2, #0
800b5b6: 601a str r2, [r3, #0]
}
return errval;
800b5b8: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
800b5bc: 4618 mov r0, r3
800b5be: 3728 adds r7, #40 ; 0x28
800b5c0: 46bd mov sp, r7
800b5c2: bd80 pop {r7, pc}
800b5c4: 2000a670 .word 0x2000a670
0800b5c8 <low_level_input>:
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf * low_level_input(struct netif *netif)
{
800b5c8: b580 push {r7, lr}
800b5ca: b08c sub sp, #48 ; 0x30
800b5cc: af00 add r7, sp, #0
800b5ce: 6078 str r0, [r7, #4]
struct pbuf *p = NULL;
800b5d0: 2300 movs r3, #0
800b5d2: 62fb str r3, [r7, #44] ; 0x2c
struct pbuf *q = NULL;
800b5d4: 2300 movs r3, #0
800b5d6: 62bb str r3, [r7, #40] ; 0x28
uint16_t len = 0;
800b5d8: 2300 movs r3, #0
800b5da: 81fb strh r3, [r7, #14]
uint8_t *buffer;
__IO ETH_DMADescTypeDef *dmarxdesc;
uint32_t bufferoffset = 0;
800b5dc: 2300 movs r3, #0
800b5de: 61fb str r3, [r7, #28]
uint32_t payloadoffset = 0;
800b5e0: 2300 movs r3, #0
800b5e2: 61bb str r3, [r7, #24]
uint32_t byteslefttocopy = 0;
800b5e4: 2300 movs r3, #0
800b5e6: 617b str r3, [r7, #20]
uint32_t i=0;
800b5e8: 2300 movs r3, #0
800b5ea: 613b str r3, [r7, #16]
/* get received frame */
if (HAL_ETH_GetReceivedFrame_IT(&heth) != HAL_OK)
800b5ec: 484f ldr r0, [pc, #316] ; (800b72c <low_level_input+0x164>)
800b5ee: f7fb f81d bl 800662c <HAL_ETH_GetReceivedFrame_IT>
800b5f2: 4603 mov r3, r0
800b5f4: 2b00 cmp r3, #0
800b5f6: d001 beq.n 800b5fc <low_level_input+0x34>
return NULL;
800b5f8: 2300 movs r3, #0
800b5fa: e092 b.n 800b722 <low_level_input+0x15a>
/* Obtain the size of the packet and put it into the "len" variable. */
len = heth.RxFrameInfos.length;
800b5fc: 4b4b ldr r3, [pc, #300] ; (800b72c <low_level_input+0x164>)
800b5fe: 6bdb ldr r3, [r3, #60] ; 0x3c
800b600: 81fb strh r3, [r7, #14]
buffer = (uint8_t *)heth.RxFrameInfos.buffer;
800b602: 4b4a ldr r3, [pc, #296] ; (800b72c <low_level_input+0x164>)
800b604: 6c1b ldr r3, [r3, #64] ; 0x40
800b606: 627b str r3, [r7, #36] ; 0x24
if (len > 0)
800b608: 89fb ldrh r3, [r7, #14]
800b60a: 2b00 cmp r3, #0
800b60c: d007 beq.n 800b61e <low_level_input+0x56>
{
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
800b60e: 89fb ldrh r3, [r7, #14]
800b610: f44f 72c1 mov.w r2, #386 ; 0x182
800b614: 4619 mov r1, r3
800b616: 2000 movs r0, #0
800b618: f004 fd0e bl 8010038 <pbuf_alloc>
800b61c: 62f8 str r0, [r7, #44] ; 0x2c
}
if (p != NULL)
800b61e: 6afb ldr r3, [r7, #44] ; 0x2c
800b620: 2b00 cmp r3, #0
800b622: d04b beq.n 800b6bc <low_level_input+0xf4>
{
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b624: 4b41 ldr r3, [pc, #260] ; (800b72c <low_level_input+0x164>)
800b626: 6b1b ldr r3, [r3, #48] ; 0x30
800b628: 623b str r3, [r7, #32]
bufferoffset = 0;
800b62a: 2300 movs r3, #0
800b62c: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b62e: 6afb ldr r3, [r7, #44] ; 0x2c
800b630: 62bb str r3, [r7, #40] ; 0x28
800b632: e040 b.n 800b6b6 <low_level_input+0xee>
{
byteslefttocopy = q->len;
800b634: 6abb ldr r3, [r7, #40] ; 0x28
800b636: 895b ldrh r3, [r3, #10]
800b638: 617b str r3, [r7, #20]
payloadoffset = 0;
800b63a: 2300 movs r3, #0
800b63c: 61bb str r3, [r7, #24]
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b63e: e021 b.n 800b684 <low_level_input+0xbc>
{
/* Copy data to pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
800b640: 6abb ldr r3, [r7, #40] ; 0x28
800b642: 685a ldr r2, [r3, #4]
800b644: 69bb ldr r3, [r7, #24]
800b646: 18d0 adds r0, r2, r3
800b648: 6a7a ldr r2, [r7, #36] ; 0x24
800b64a: 69fb ldr r3, [r7, #28]
800b64c: 18d1 adds r1, r2, r3
800b64e: 69fa ldr r2, [r7, #28]
800b650: f240 53f4 movw r3, #1524 ; 0x5f4
800b654: 1a9b subs r3, r3, r2
800b656: 461a mov r2, r3
800b658: f00f fcd1 bl 801affe <memcpy>
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b65c: 6a3b ldr r3, [r7, #32]
800b65e: 68db ldr r3, [r3, #12]
800b660: 623b str r3, [r7, #32]
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
800b662: 6a3b ldr r3, [r7, #32]
800b664: 689b ldr r3, [r3, #8]
800b666: 627b str r3, [r7, #36] ; 0x24
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
800b668: 69fa ldr r2, [r7, #28]
800b66a: 697b ldr r3, [r7, #20]
800b66c: 4413 add r3, r2
800b66e: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
800b672: 617b str r3, [r7, #20]
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
800b674: 69ba ldr r2, [r7, #24]
800b676: 69fb ldr r3, [r7, #28]
800b678: 1ad3 subs r3, r2, r3
800b67a: f203 53f4 addw r3, r3, #1524 ; 0x5f4
800b67e: 61bb str r3, [r7, #24]
bufferoffset = 0;
800b680: 2300 movs r3, #0
800b682: 61fb str r3, [r7, #28]
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
800b684: 697a ldr r2, [r7, #20]
800b686: 69fb ldr r3, [r7, #28]
800b688: 4413 add r3, r2
800b68a: f240 52f4 movw r2, #1524 ; 0x5f4
800b68e: 4293 cmp r3, r2
800b690: d8d6 bhi.n 800b640 <low_level_input+0x78>
}
/* Copy remaining data in pbuf */
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
800b692: 6abb ldr r3, [r7, #40] ; 0x28
800b694: 685a ldr r2, [r3, #4]
800b696: 69bb ldr r3, [r7, #24]
800b698: 18d0 adds r0, r2, r3
800b69a: 6a7a ldr r2, [r7, #36] ; 0x24
800b69c: 69fb ldr r3, [r7, #28]
800b69e: 4413 add r3, r2
800b6a0: 697a ldr r2, [r7, #20]
800b6a2: 4619 mov r1, r3
800b6a4: f00f fcab bl 801affe <memcpy>
bufferoffset = bufferoffset + byteslefttocopy;
800b6a8: 69fa ldr r2, [r7, #28]
800b6aa: 697b ldr r3, [r7, #20]
800b6ac: 4413 add r3, r2
800b6ae: 61fb str r3, [r7, #28]
for(q = p; q != NULL; q = q->next)
800b6b0: 6abb ldr r3, [r7, #40] ; 0x28
800b6b2: 681b ldr r3, [r3, #0]
800b6b4: 62bb str r3, [r7, #40] ; 0x28
800b6b6: 6abb ldr r3, [r7, #40] ; 0x28
800b6b8: 2b00 cmp r3, #0
800b6ba: d1bb bne.n 800b634 <low_level_input+0x6c>
}
}
/* Release descriptors to DMA */
/* Point to first descriptor */
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
800b6bc: 4b1b ldr r3, [pc, #108] ; (800b72c <low_level_input+0x164>)
800b6be: 6b1b ldr r3, [r3, #48] ; 0x30
800b6c0: 623b str r3, [r7, #32]
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b6c2: 2300 movs r3, #0
800b6c4: 613b str r3, [r7, #16]
800b6c6: e00b b.n 800b6e0 <low_level_input+0x118>
{
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
800b6c8: 6a3b ldr r3, [r7, #32]
800b6ca: 681b ldr r3, [r3, #0]
800b6cc: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
800b6d0: 6a3b ldr r3, [r7, #32]
800b6d2: 601a str r2, [r3, #0]
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
800b6d4: 6a3b ldr r3, [r7, #32]
800b6d6: 68db ldr r3, [r3, #12]
800b6d8: 623b str r3, [r7, #32]
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
800b6da: 693b ldr r3, [r7, #16]
800b6dc: 3301 adds r3, #1
800b6de: 613b str r3, [r7, #16]
800b6e0: 4b12 ldr r3, [pc, #72] ; (800b72c <low_level_input+0x164>)
800b6e2: 6b9b ldr r3, [r3, #56] ; 0x38
800b6e4: 693a ldr r2, [r7, #16]
800b6e6: 429a cmp r2, r3
800b6e8: d3ee bcc.n 800b6c8 <low_level_input+0x100>
}
/* Clear Segment_Count */
heth.RxFrameInfos.SegCount =0;
800b6ea: 4b10 ldr r3, [pc, #64] ; (800b72c <low_level_input+0x164>)
800b6ec: 2200 movs r2, #0
800b6ee: 639a str r2, [r3, #56] ; 0x38
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
800b6f0: 4b0e ldr r3, [pc, #56] ; (800b72c <low_level_input+0x164>)
800b6f2: 681a ldr r2, [r3, #0]
800b6f4: f241 0314 movw r3, #4116 ; 0x1014
800b6f8: 4413 add r3, r2
800b6fa: 681b ldr r3, [r3, #0]
800b6fc: f003 0380 and.w r3, r3, #128 ; 0x80
800b700: 2b00 cmp r3, #0
800b702: d00d beq.n 800b720 <low_level_input+0x158>
{
/* Clear RBUS ETHERNET DMA flag */
heth.Instance->DMASR = ETH_DMASR_RBUS;
800b704: 4b09 ldr r3, [pc, #36] ; (800b72c <low_level_input+0x164>)
800b706: 681a ldr r2, [r3, #0]
800b708: f241 0314 movw r3, #4116 ; 0x1014
800b70c: 4413 add r3, r2
800b70e: 2280 movs r2, #128 ; 0x80
800b710: 601a str r2, [r3, #0]
/* Resume DMA reception */
heth.Instance->DMARPDR = 0;
800b712: 4b06 ldr r3, [pc, #24] ; (800b72c <low_level_input+0x164>)
800b714: 681a ldr r2, [r3, #0]
800b716: f241 0308 movw r3, #4104 ; 0x1008
800b71a: 4413 add r3, r2
800b71c: 2200 movs r2, #0
800b71e: 601a str r2, [r3, #0]
}
return p;
800b720: 6afb ldr r3, [r7, #44] ; 0x2c
}
800b722: 4618 mov r0, r3
800b724: 3730 adds r7, #48 ; 0x30
800b726: 46bd mov sp, r7
800b728: bd80 pop {r7, pc}
800b72a: bf00 nop
800b72c: 2000a670 .word 0x2000a670
0800b730 <ethernetif_input>:
* the appropriate input function is called.
*
* @param netif the lwip network interface structure for this ethernetif
*/
void ethernetif_input(void const * argument)
{
800b730: b580 push {r7, lr}
800b732: b084 sub sp, #16
800b734: af00 add r7, sp, #0
800b736: 6078 str r0, [r7, #4]
struct pbuf *p;
struct netif *netif = (struct netif *) argument;
800b738: 687b ldr r3, [r7, #4]
800b73a: 60fb str r3, [r7, #12]
for( ;; )
{
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b73c: 4b12 ldr r3, [pc, #72] ; (800b788 <ethernetif_input+0x58>)
800b73e: 681b ldr r3, [r3, #0]
800b740: f04f 31ff mov.w r1, #4294967295
800b744: 4618 mov r0, r3
800b746: f000 fa99 bl 800bc7c <osSemaphoreWait>
800b74a: 4603 mov r3, r0
800b74c: 2b00 cmp r3, #0
800b74e: d1f5 bne.n 800b73c <ethernetif_input+0xc>
{
do
{
LOCK_TCPIP_CORE();
800b750: 480e ldr r0, [pc, #56] ; (800b78c <ethernetif_input+0x5c>)
800b752: f00f fbc1 bl 801aed8 <sys_mutex_lock>
p = low_level_input( netif );
800b756: 68f8 ldr r0, [r7, #12]
800b758: f7ff ff36 bl 800b5c8 <low_level_input>
800b75c: 60b8 str r0, [r7, #8]
if (p != NULL)
800b75e: 68bb ldr r3, [r7, #8]
800b760: 2b00 cmp r3, #0
800b762: d00a beq.n 800b77a <ethernetif_input+0x4a>
{
if (netif->input( p, netif) != ERR_OK )
800b764: 68fb ldr r3, [r7, #12]
800b766: 691b ldr r3, [r3, #16]
800b768: 68f9 ldr r1, [r7, #12]
800b76a: 68b8 ldr r0, [r7, #8]
800b76c: 4798 blx r3
800b76e: 4603 mov r3, r0
800b770: 2b00 cmp r3, #0
800b772: d002 beq.n 800b77a <ethernetif_input+0x4a>
{
pbuf_free(p);
800b774: 68b8 ldr r0, [r7, #8]
800b776: f004 ff3f bl 80105f8 <pbuf_free>
}
}
UNLOCK_TCPIP_CORE();
800b77a: 4804 ldr r0, [pc, #16] ; (800b78c <ethernetif_input+0x5c>)
800b77c: f00f fbbb bl 801aef6 <sys_mutex_unlock>
} while(p!=NULL);
800b780: 68bb ldr r3, [r7, #8]
800b782: 2b00 cmp r3, #0
800b784: d1e4 bne.n 800b750 <ethernetif_input+0x20>
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
800b786: e7d9 b.n 800b73c <ethernetif_input+0xc>
800b788: 20000588 .word 0x20000588
800b78c: 2000be88 .word 0x2000be88
0800b790 <ethernetif_init>:
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t ethernetif_init(struct netif *netif)
{
800b790: b580 push {r7, lr}
800b792: b082 sub sp, #8
800b794: af00 add r7, sp, #0
800b796: 6078 str r0, [r7, #4]
LWIP_ASSERT("netif != NULL", (netif != NULL));
800b798: 687b ldr r3, [r7, #4]
800b79a: 2b00 cmp r3, #0
800b79c: d106 bne.n 800b7ac <ethernetif_init+0x1c>
800b79e: 4b0e ldr r3, [pc, #56] ; (800b7d8 <ethernetif_init+0x48>)
800b7a0: f240 222b movw r2, #555 ; 0x22b
800b7a4: 490d ldr r1, [pc, #52] ; (800b7dc <ethernetif_init+0x4c>)
800b7a6: 480e ldr r0, [pc, #56] ; (800b7e0 <ethernetif_init+0x50>)
800b7a8: f00f fc3c bl 801b024 <iprintf>
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = "lwip";
#endif /* LWIP_NETIF_HOSTNAME */
netif->name[0] = IFNAME0;
800b7ac: 687b ldr r3, [r7, #4]
800b7ae: 2273 movs r2, #115 ; 0x73
800b7b0: f883 2032 strb.w r2, [r3, #50] ; 0x32
netif->name[1] = IFNAME1;
800b7b4: 687b ldr r3, [r7, #4]
800b7b6: 2274 movs r2, #116 ; 0x74
800b7b8: f883 2033 strb.w r2, [r3, #51] ; 0x33
* is available...) */
#if LWIP_IPV4
#if LWIP_ARP || LWIP_ETHERNET
#if LWIP_ARP
netif->output = etharp_output;
800b7bc: 687b ldr r3, [r7, #4]
800b7be: 4a09 ldr r2, [pc, #36] ; (800b7e4 <ethernetif_init+0x54>)
800b7c0: 615a str r2, [r3, #20]
#if LWIP_IPV6
netif->output_ip6 = ethip6_output;
#endif /* LWIP_IPV6 */
netif->linkoutput = low_level_output;
800b7c2: 687b ldr r3, [r7, #4]
800b7c4: 4a08 ldr r2, [pc, #32] ; (800b7e8 <ethernetif_init+0x58>)
800b7c6: 619a str r2, [r3, #24]
/* initialize the hardware */
low_level_init(netif);
800b7c8: 6878 ldr r0, [r7, #4]
800b7ca: f7ff fd87 bl 800b2dc <low_level_init>
return ERR_OK;
800b7ce: 2300 movs r3, #0
}
800b7d0: 4618 mov r0, r3
800b7d2: 3708 adds r7, #8
800b7d4: 46bd mov sp, r7
800b7d6: bd80 pop {r7, pc}
800b7d8: 0801bf88 .word 0x0801bf88
800b7dc: 0801bfa4 .word 0x0801bfa4
800b7e0: 0801bfb4 .word 0x0801bfb4
800b7e4: 08019055 .word 0x08019055
800b7e8: 0800b48d .word 0x0800b48d
0800b7ec <sys_now>:
* when LWIP_TIMERS == 1 and NO_SYS == 1
* @param None
* @retval Time
*/
u32_t sys_now(void)
{
800b7ec: b580 push {r7, lr}
800b7ee: af00 add r7, sp, #0
return HAL_GetTick();
800b7f0: f7f9 f8d6 bl 80049a0 <HAL_GetTick>
800b7f4: 4603 mov r3, r0
}
800b7f6: 4618 mov r0, r3
800b7f8: bd80 pop {r7, pc}
...
0800b7fc <ethernetif_set_link>:
* @param netif: the network interface
* @retval None
*/
void ethernetif_set_link(void const *argument)
{
800b7fc: b580 push {r7, lr}
800b7fe: b084 sub sp, #16
800b800: af00 add r7, sp, #0
800b802: 6078 str r0, [r7, #4]
uint32_t regvalue = 0;
800b804: 2300 movs r3, #0
800b806: 60bb str r3, [r7, #8]
struct link_str *link_arg = (struct link_str *)argument;
800b808: 687b ldr r3, [r7, #4]
800b80a: 60fb str r3, [r7, #12]
for(;;)
{
/* Read PHY_BSR*/
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b80c: f107 0308 add.w r3, r7, #8
800b810: 461a mov r2, r3
800b812: 2101 movs r1, #1
800b814: 4816 ldr r0, [pc, #88] ; (800b870 <ethernetif_set_link+0x74>)
800b816: f7fb f80c bl 8006832 <HAL_ETH_ReadPHYRegister>
regvalue &= PHY_LINKED_STATUS;
800b81a: 68bb ldr r3, [r7, #8]
800b81c: f003 0304 and.w r3, r3, #4
800b820: 60bb str r3, [r7, #8]
/* Check whether the netif link down and the PHY link is up */
if(!netif_is_link_up(link_arg->netif) && (regvalue))
800b822: 68fb ldr r3, [r7, #12]
800b824: 681b ldr r3, [r3, #0]
800b826: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b82a: f003 0304 and.w r3, r3, #4
800b82e: 2b00 cmp r3, #0
800b830: d108 bne.n 800b844 <ethernetif_set_link+0x48>
800b832: 68bb ldr r3, [r7, #8]
800b834: 2b00 cmp r3, #0
800b836: d005 beq.n 800b844 <ethernetif_set_link+0x48>
{
/* network cable is connected */
netif_set_link_up(link_arg->netif);
800b838: 68fb ldr r3, [r7, #12]
800b83a: 681b ldr r3, [r3, #0]
800b83c: 4618 mov r0, r3
800b83e: f004 fac9 bl 800fdd4 <netif_set_link_up>
800b842: e011 b.n 800b868 <ethernetif_set_link+0x6c>
}
else if(netif_is_link_up(link_arg->netif) && (!regvalue))
800b844: 68fb ldr r3, [r7, #12]
800b846: 681b ldr r3, [r3, #0]
800b848: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b84c: 089b lsrs r3, r3, #2
800b84e: f003 0301 and.w r3, r3, #1
800b852: b2db uxtb r3, r3
800b854: 2b00 cmp r3, #0
800b856: d007 beq.n 800b868 <ethernetif_set_link+0x6c>
800b858: 68bb ldr r3, [r7, #8]
800b85a: 2b00 cmp r3, #0
800b85c: d104 bne.n 800b868 <ethernetif_set_link+0x6c>
{
/* network cable is dis-connected */
netif_set_link_down(link_arg->netif);
800b85e: 68fb ldr r3, [r7, #12]
800b860: 681b ldr r3, [r3, #0]
800b862: 4618 mov r0, r3
800b864: f004 faee bl 800fe44 <netif_set_link_down>
}
/* Suspend thread for 200 ms */
osDelay(200);
800b868: 20c8 movs r0, #200 ; 0xc8
800b86a: f000 f916 bl 800ba9a <osDelay>
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b86e: e7cd b.n 800b80c <ethernetif_set_link+0x10>
800b870: 2000a670 .word 0x2000a670
0800b874 <ethernetif_update_config>:
* to update low level driver configuration.
* @param netif: The network interface
* @retval None
*/
void ethernetif_update_config(struct netif *netif)
{
800b874: b580 push {r7, lr}
800b876: b084 sub sp, #16
800b878: af00 add r7, sp, #0
800b87a: 6078 str r0, [r7, #4]
__IO uint32_t tickstart = 0;
800b87c: 2300 movs r3, #0
800b87e: 60fb str r3, [r7, #12]
uint32_t regvalue = 0;
800b880: 2300 movs r3, #0
800b882: 60bb str r3, [r7, #8]
if(netif_is_link_up(netif))
800b884: 687b ldr r3, [r7, #4]
800b886: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800b88a: 089b lsrs r3, r3, #2
800b88c: f003 0301 and.w r3, r3, #1
800b890: b2db uxtb r3, r3
800b892: 2b00 cmp r3, #0
800b894: d05d beq.n 800b952 <ethernetif_update_config+0xde>
{
/* Restart the auto-negotiation */
if(heth.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
800b896: 4b34 ldr r3, [pc, #208] ; (800b968 <ethernetif_update_config+0xf4>)
800b898: 685b ldr r3, [r3, #4]
800b89a: 2b00 cmp r3, #0
800b89c: d03f beq.n 800b91e <ethernetif_update_config+0xaa>
{
/* Enable Auto-Negotiation */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, PHY_AUTONEGOTIATION);
800b89e: f44f 5280 mov.w r2, #4096 ; 0x1000
800b8a2: 2100 movs r1, #0
800b8a4: 4830 ldr r0, [pc, #192] ; (800b968 <ethernetif_update_config+0xf4>)
800b8a6: f7fb f82c bl 8006902 <HAL_ETH_WritePHYRegister>
/* Get tick */
tickstart = HAL_GetTick();
800b8aa: f7f9 f879 bl 80049a0 <HAL_GetTick>
800b8ae: 4603 mov r3, r0
800b8b0: 60fb str r3, [r7, #12]
/* Wait until the auto-negotiation will be completed */
do
{
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, &regvalue);
800b8b2: f107 0308 add.w r3, r7, #8
800b8b6: 461a mov r2, r3
800b8b8: 2101 movs r1, #1
800b8ba: 482b ldr r0, [pc, #172] ; (800b968 <ethernetif_update_config+0xf4>)
800b8bc: f7fa ffb9 bl 8006832 <HAL_ETH_ReadPHYRegister>
/* Check for the Timeout ( 1s ) */
if((HAL_GetTick() - tickstart ) > 1000)
800b8c0: f7f9 f86e bl 80049a0 <HAL_GetTick>
800b8c4: 4602 mov r2, r0
800b8c6: 68fb ldr r3, [r7, #12]
800b8c8: 1ad3 subs r3, r2, r3
800b8ca: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800b8ce: d828 bhi.n 800b922 <ethernetif_update_config+0xae>
{
/* In case of timeout */
goto error;
}
} while (((regvalue & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
800b8d0: 68bb ldr r3, [r7, #8]
800b8d2: f003 0320 and.w r3, r3, #32
800b8d6: 2b00 cmp r3, #0
800b8d8: d0eb beq.n 800b8b2 <ethernetif_update_config+0x3e>
/* Read the result of the auto-negotiation */
HAL_ETH_ReadPHYRegister(&heth, PHY_SR, &regvalue);
800b8da: f107 0308 add.w r3, r7, #8
800b8de: 461a mov r2, r3
800b8e0: 211f movs r1, #31
800b8e2: 4821 ldr r0, [pc, #132] ; (800b968 <ethernetif_update_config+0xf4>)
800b8e4: f7fa ffa5 bl 8006832 <HAL_ETH_ReadPHYRegister>
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
if((regvalue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
800b8e8: 68bb ldr r3, [r7, #8]
800b8ea: f003 0310 and.w r3, r3, #16
800b8ee: 2b00 cmp r3, #0
800b8f0: d004 beq.n 800b8fc <ethernetif_update_config+0x88>
{
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
800b8f2: 4b1d ldr r3, [pc, #116] ; (800b968 <ethernetif_update_config+0xf4>)
800b8f4: f44f 6200 mov.w r2, #2048 ; 0x800
800b8f8: 60da str r2, [r3, #12]
800b8fa: e002 b.n 800b902 <ethernetif_update_config+0x8e>
}
else
{
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
heth.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
800b8fc: 4b1a ldr r3, [pc, #104] ; (800b968 <ethernetif_update_config+0xf4>)
800b8fe: 2200 movs r2, #0
800b900: 60da str r2, [r3, #12]
}
/* Configure the MAC with the speed fixed by the auto-negotiation process */
if(regvalue & PHY_SPEED_STATUS)
800b902: 68bb ldr r3, [r7, #8]
800b904: f003 0304 and.w r3, r3, #4
800b908: 2b00 cmp r3, #0
800b90a: d003 beq.n 800b914 <ethernetif_update_config+0xa0>
{
/* Set Ethernet speed to 10M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_10M;
800b90c: 4b16 ldr r3, [pc, #88] ; (800b968 <ethernetif_update_config+0xf4>)
800b90e: 2200 movs r2, #0
800b910: 609a str r2, [r3, #8]
800b912: e016 b.n 800b942 <ethernetif_update_config+0xce>
}
else
{
/* Set Ethernet speed to 100M following the auto-negotiation */
heth.Init.Speed = ETH_SPEED_100M;
800b914: 4b14 ldr r3, [pc, #80] ; (800b968 <ethernetif_update_config+0xf4>)
800b916: f44f 4280 mov.w r2, #16384 ; 0x4000
800b91a: 609a str r2, [r3, #8]
800b91c: e011 b.n 800b942 <ethernetif_update_config+0xce>
}
}
else /* AutoNegotiation Disable */
{
error :
800b91e: bf00 nop
800b920: e000 b.n 800b924 <ethernetif_update_config+0xb0>
goto error;
800b922: bf00 nop
/* Check parameters */
assert_param(IS_ETH_SPEED(heth.Init.Speed));
assert_param(IS_ETH_DUPLEX_MODE(heth.Init.DuplexMode));
/* Set MAC Speed and Duplex Mode to PHY */
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b924: 4b10 ldr r3, [pc, #64] ; (800b968 <ethernetif_update_config+0xf4>)
800b926: 68db ldr r3, [r3, #12]
800b928: 08db lsrs r3, r3, #3
800b92a: b29a uxth r2, r3
(uint16_t)(heth.Init.Speed >> 1)));
800b92c: 4b0e ldr r3, [pc, #56] ; (800b968 <ethernetif_update_config+0xf4>)
800b92e: 689b ldr r3, [r3, #8]
800b930: 085b lsrs r3, r3, #1
800b932: b29b uxth r3, r3
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
800b934: 4313 orrs r3, r2
800b936: b29b uxth r3, r3
800b938: 461a mov r2, r3
800b93a: 2100 movs r1, #0
800b93c: 480a ldr r0, [pc, #40] ; (800b968 <ethernetif_update_config+0xf4>)
800b93e: f7fa ffe0 bl 8006902 <HAL_ETH_WritePHYRegister>
}
/* ETHERNET MAC Re-Configuration */
HAL_ETH_ConfigMAC(&heth, (ETH_MACInitTypeDef *) NULL);
800b942: 2100 movs r1, #0
800b944: 4808 ldr r0, [pc, #32] ; (800b968 <ethernetif_update_config+0xf4>)
800b946: f7fb f8a1 bl 8006a8c <HAL_ETH_ConfigMAC>
/* Restart MAC interface */
HAL_ETH_Start(&heth);
800b94a: 4807 ldr r0, [pc, #28] ; (800b968 <ethernetif_update_config+0xf4>)
800b94c: f7fb f83f bl 80069ce <HAL_ETH_Start>
800b950: e002 b.n 800b958 <ethernetif_update_config+0xe4>
}
else
{
/* Stop MAC interface */
HAL_ETH_Stop(&heth);
800b952: 4805 ldr r0, [pc, #20] ; (800b968 <ethernetif_update_config+0xf4>)
800b954: f7fb f86a bl 8006a2c <HAL_ETH_Stop>
}
ethernetif_notify_conn_changed(netif);
800b958: 6878 ldr r0, [r7, #4]
800b95a: f000 f807 bl 800b96c <ethernetif_notify_conn_changed>
}
800b95e: bf00 nop
800b960: 3710 adds r7, #16
800b962: 46bd mov sp, r7
800b964: bd80 pop {r7, pc}
800b966: bf00 nop
800b968: 2000a670 .word 0x2000a670
0800b96c <ethernetif_notify_conn_changed>:
* @brief This function notify user about link status changement.
* @param netif: the network interface
* @retval None
*/
__weak void ethernetif_notify_conn_changed(struct netif *netif)
{
800b96c: b480 push {r7}
800b96e: b083 sub sp, #12
800b970: af00 add r7, sp, #0
800b972: 6078 str r0, [r7, #4]
/* NOTE : This is function could be implemented in user file
when the callback is needed,
*/
}
800b974: bf00 nop
800b976: 370c adds r7, #12
800b978: 46bd mov sp, r7
800b97a: f85d 7b04 ldr.w r7, [sp], #4
800b97e: 4770 bx lr
0800b980 <makeFreeRtosPriority>:
extern void xPortSysTickHandler(void);
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
{
800b980: b480 push {r7}
800b982: b085 sub sp, #20
800b984: af00 add r7, sp, #0
800b986: 4603 mov r3, r0
800b988: 80fb strh r3, [r7, #6]
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
800b98a: 2300 movs r3, #0
800b98c: 60fb str r3, [r7, #12]
if (priority != osPriorityError) {
800b98e: f9b7 3006 ldrsh.w r3, [r7, #6]
800b992: 2b84 cmp r3, #132 ; 0x84
800b994: d005 beq.n 800b9a2 <makeFreeRtosPriority+0x22>
fpriority += (priority - osPriorityIdle);
800b996: f9b7 2006 ldrsh.w r2, [r7, #6]
800b99a: 68fb ldr r3, [r7, #12]
800b99c: 4413 add r3, r2
800b99e: 3303 adds r3, #3
800b9a0: 60fb str r3, [r7, #12]
}
return fpriority;
800b9a2: 68fb ldr r3, [r7, #12]
}
800b9a4: 4618 mov r0, r3
800b9a6: 3714 adds r7, #20
800b9a8: 46bd mov sp, r7
800b9aa: f85d 7b04 ldr.w r7, [sp], #4
800b9ae: 4770 bx lr
0800b9b0 <inHandlerMode>:
#endif
/* Determine whether we are in thread mode or handler mode. */
static int inHandlerMode (void)
{
800b9b0: b480 push {r7}
800b9b2: b083 sub sp, #12
800b9b4: af00 add r7, sp, #0
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
800b9b6: f3ef 8305 mrs r3, IPSR
800b9ba: 607b str r3, [r7, #4]
return(result);
800b9bc: 687b ldr r3, [r7, #4]
return __get_IPSR() != 0;
800b9be: 2b00 cmp r3, #0
800b9c0: bf14 ite ne
800b9c2: 2301 movne r3, #1
800b9c4: 2300 moveq r3, #0
800b9c6: b2db uxtb r3, r3
}
800b9c8: 4618 mov r0, r3
800b9ca: 370c adds r7, #12
800b9cc: 46bd mov sp, r7
800b9ce: f85d 7b04 ldr.w r7, [sp], #4
800b9d2: 4770 bx lr
0800b9d4 <osKernelStart>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval status code that indicates the execution status of the function
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
*/
osStatus osKernelStart (void)
{
800b9d4: b580 push {r7, lr}
800b9d6: af00 add r7, sp, #0
vTaskStartScheduler();
800b9d8: f001 fe1e bl 800d618 <vTaskStartScheduler>
return osOK;
800b9dc: 2300 movs r3, #0
}
800b9de: 4618 mov r0, r3
800b9e0: bd80 pop {r7, pc}
0800b9e2 <osKernelSysTick>:
* @param None
* @retval None
* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
*/
uint32_t osKernelSysTick(void)
{
800b9e2: b580 push {r7, lr}
800b9e4: af00 add r7, sp, #0
if (inHandlerMode()) {
800b9e6: f7ff ffe3 bl 800b9b0 <inHandlerMode>
800b9ea: 4603 mov r3, r0
800b9ec: 2b00 cmp r3, #0
800b9ee: d003 beq.n 800b9f8 <osKernelSysTick+0x16>
return xTaskGetTickCountFromISR();
800b9f0: f001 ff30 bl 800d854 <xTaskGetTickCountFromISR>
800b9f4: 4603 mov r3, r0
800b9f6: e002 b.n 800b9fe <osKernelSysTick+0x1c>
}
else {
return xTaskGetTickCount();
800b9f8: f001 ff1c bl 800d834 <xTaskGetTickCount>
800b9fc: 4603 mov r3, r0
}
}
800b9fe: 4618 mov r0, r3
800ba00: bd80 pop {r7, pc}
0800ba02 <osThreadCreate>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval thread ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
*/
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
{
800ba02: b5f0 push {r4, r5, r6, r7, lr}
800ba04: b089 sub sp, #36 ; 0x24
800ba06: af04 add r7, sp, #16
800ba08: 6078 str r0, [r7, #4]
800ba0a: 6039 str r1, [r7, #0]
TaskHandle_t handle;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
800ba0c: 687b ldr r3, [r7, #4]
800ba0e: 695b ldr r3, [r3, #20]
800ba10: 2b00 cmp r3, #0
800ba12: d020 beq.n 800ba56 <osThreadCreate+0x54>
800ba14: 687b ldr r3, [r7, #4]
800ba16: 699b ldr r3, [r3, #24]
800ba18: 2b00 cmp r3, #0
800ba1a: d01c beq.n 800ba56 <osThreadCreate+0x54>
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba1c: 687b ldr r3, [r7, #4]
800ba1e: 685c ldr r4, [r3, #4]
800ba20: 687b ldr r3, [r7, #4]
800ba22: 681d ldr r5, [r3, #0]
800ba24: 687b ldr r3, [r7, #4]
800ba26: 691e ldr r6, [r3, #16]
800ba28: 687b ldr r3, [r7, #4]
800ba2a: f9b3 3008 ldrsh.w r3, [r3, #8]
800ba2e: 4618 mov r0, r3
800ba30: f7ff ffa6 bl 800b980 <makeFreeRtosPriority>
800ba34: 4601 mov r1, r0
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
thread_def->buffer, thread_def->controlblock);
800ba36: 687b ldr r3, [r7, #4]
800ba38: 695b ldr r3, [r3, #20]
800ba3a: 687a ldr r2, [r7, #4]
800ba3c: 6992 ldr r2, [r2, #24]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba3e: 9202 str r2, [sp, #8]
800ba40: 9301 str r3, [sp, #4]
800ba42: 9100 str r1, [sp, #0]
800ba44: 683b ldr r3, [r7, #0]
800ba46: 4632 mov r2, r6
800ba48: 4629 mov r1, r5
800ba4a: 4620 mov r0, r4
800ba4c: f001 fafb bl 800d046 <xTaskCreateStatic>
800ba50: 4603 mov r3, r0
800ba52: 60fb str r3, [r7, #12]
800ba54: e01c b.n 800ba90 <osThreadCreate+0x8e>
}
else {
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba56: 687b ldr r3, [r7, #4]
800ba58: 685c ldr r4, [r3, #4]
800ba5a: 687b ldr r3, [r7, #4]
800ba5c: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
800ba5e: 687b ldr r3, [r7, #4]
800ba60: 691b ldr r3, [r3, #16]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800ba62: b29e uxth r6, r3
800ba64: 687b ldr r3, [r7, #4]
800ba66: f9b3 3008 ldrsh.w r3, [r3, #8]
800ba6a: 4618 mov r0, r3
800ba6c: f7ff ff88 bl 800b980 <makeFreeRtosPriority>
800ba70: 4602 mov r2, r0
800ba72: f107 030c add.w r3, r7, #12
800ba76: 9301 str r3, [sp, #4]
800ba78: 9200 str r2, [sp, #0]
800ba7a: 683b ldr r3, [r7, #0]
800ba7c: 4632 mov r2, r6
800ba7e: 4629 mov r1, r5
800ba80: 4620 mov r0, r4
800ba82: f001 fb40 bl 800d106 <xTaskCreate>
800ba86: 4603 mov r3, r0
800ba88: 2b01 cmp r3, #1
800ba8a: d001 beq.n 800ba90 <osThreadCreate+0x8e>
&handle) != pdPASS) {
return NULL;
800ba8c: 2300 movs r3, #0
800ba8e: e000 b.n 800ba92 <osThreadCreate+0x90>
&handle) != pdPASS) {
return NULL;
}
#endif
return handle;
800ba90: 68fb ldr r3, [r7, #12]
}
800ba92: 4618 mov r0, r3
800ba94: 3714 adds r7, #20
800ba96: 46bd mov sp, r7
800ba98: bdf0 pop {r4, r5, r6, r7, pc}
0800ba9a <osDelay>:
* @brief Wait for Timeout (Time Delay)
* @param millisec time delay value
* @retval status code that indicates the execution status of the function.
*/
osStatus osDelay (uint32_t millisec)
{
800ba9a: b580 push {r7, lr}
800ba9c: b084 sub sp, #16
800ba9e: af00 add r7, sp, #0
800baa0: 6078 str r0, [r7, #4]
#if INCLUDE_vTaskDelay
TickType_t ticks = millisec / portTICK_PERIOD_MS;
800baa2: 687b ldr r3, [r7, #4]
800baa4: 60fb str r3, [r7, #12]
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
800baa6: 68fb ldr r3, [r7, #12]
800baa8: 2b00 cmp r3, #0
800baaa: d001 beq.n 800bab0 <osDelay+0x16>
800baac: 68fb ldr r3, [r7, #12]
800baae: e000 b.n 800bab2 <osDelay+0x18>
800bab0: 2301 movs r3, #1
800bab2: 4618 mov r0, r3
800bab4: f001 fd7a bl 800d5ac <vTaskDelay>
return osOK;
800bab8: 2300 movs r3, #0
#else
(void) millisec;
return osErrorResource;
#endif
}
800baba: 4618 mov r0, r3
800babc: 3710 adds r7, #16
800babe: 46bd mov sp, r7
800bac0: bd80 pop {r7, pc}
0800bac2 <osMutexCreate>:
* @param mutex_def mutex definition referenced with \ref osMutex.
* @retval mutex ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
*/
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
{
800bac2: b580 push {r7, lr}
800bac4: b082 sub sp, #8
800bac6: af00 add r7, sp, #0
800bac8: 6078 str r0, [r7, #4]
#if ( configUSE_MUTEXES == 1)
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if (mutex_def->controlblock != NULL) {
800baca: 687b ldr r3, [r7, #4]
800bacc: 685b ldr r3, [r3, #4]
800bace: 2b00 cmp r3, #0
800bad0: d007 beq.n 800bae2 <osMutexCreate+0x20>
return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
800bad2: 687b ldr r3, [r7, #4]
800bad4: 685b ldr r3, [r3, #4]
800bad6: 4619 mov r1, r3
800bad8: 2001 movs r0, #1
800bada: f000 fc5e bl 800c39a <xQueueCreateMutexStatic>
800bade: 4603 mov r3, r0
800bae0: e003 b.n 800baea <osMutexCreate+0x28>
}
else {
return xSemaphoreCreateMutex();
800bae2: 2001 movs r0, #1
800bae4: f000 fc41 bl 800c36a <xQueueCreateMutex>
800bae8: 4603 mov r3, r0
return xSemaphoreCreateMutex();
#endif
#else
return NULL;
#endif
}
800baea: 4618 mov r0, r3
800baec: 3708 adds r7, #8
800baee: 46bd mov sp, r7
800baf0: bd80 pop {r7, pc}
...
0800baf4 <osMutexWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
{
800baf4: b580 push {r7, lr}
800baf6: b084 sub sp, #16
800baf8: af00 add r7, sp, #0
800bafa: 6078 str r0, [r7, #4]
800bafc: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800bafe: 2300 movs r3, #0
800bb00: 60bb str r3, [r7, #8]
if (mutex_id == NULL) {
800bb02: 687b ldr r3, [r7, #4]
800bb04: 2b00 cmp r3, #0
800bb06: d101 bne.n 800bb0c <osMutexWait+0x18>
return osErrorParameter;
800bb08: 2380 movs r3, #128 ; 0x80
800bb0a: e03a b.n 800bb82 <osMutexWait+0x8e>
}
ticks = 0;
800bb0c: 2300 movs r3, #0
800bb0e: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800bb10: 683b ldr r3, [r7, #0]
800bb12: f1b3 3fff cmp.w r3, #4294967295
800bb16: d103 bne.n 800bb20 <osMutexWait+0x2c>
ticks = portMAX_DELAY;
800bb18: f04f 33ff mov.w r3, #4294967295
800bb1c: 60fb str r3, [r7, #12]
800bb1e: e009 b.n 800bb34 <osMutexWait+0x40>
}
else if (millisec != 0) {
800bb20: 683b ldr r3, [r7, #0]
800bb22: 2b00 cmp r3, #0
800bb24: d006 beq.n 800bb34 <osMutexWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800bb26: 683b ldr r3, [r7, #0]
800bb28: 60fb str r3, [r7, #12]
if (ticks == 0) {
800bb2a: 68fb ldr r3, [r7, #12]
800bb2c: 2b00 cmp r3, #0
800bb2e: d101 bne.n 800bb34 <osMutexWait+0x40>
ticks = 1;
800bb30: 2301 movs r3, #1
800bb32: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800bb34: f7ff ff3c bl 800b9b0 <inHandlerMode>
800bb38: 4603 mov r3, r0
800bb3a: 2b00 cmp r3, #0
800bb3c: d017 beq.n 800bb6e <osMutexWait+0x7a>
if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
800bb3e: f107 0308 add.w r3, r7, #8
800bb42: 461a mov r2, r3
800bb44: 2100 movs r1, #0
800bb46: 6878 ldr r0, [r7, #4]
800bb48: f001 f8d2 bl 800ccf0 <xQueueReceiveFromISR>
800bb4c: 4603 mov r3, r0
800bb4e: 2b01 cmp r3, #1
800bb50: d001 beq.n 800bb56 <osMutexWait+0x62>
return osErrorOS;
800bb52: 23ff movs r3, #255 ; 0xff
800bb54: e015 b.n 800bb82 <osMutexWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800bb56: 68bb ldr r3, [r7, #8]
800bb58: 2b00 cmp r3, #0
800bb5a: d011 beq.n 800bb80 <osMutexWait+0x8c>
800bb5c: 4b0b ldr r3, [pc, #44] ; (800bb8c <osMutexWait+0x98>)
800bb5e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bb62: 601a str r2, [r3, #0]
800bb64: f3bf 8f4f dsb sy
800bb68: f3bf 8f6f isb sy
800bb6c: e008 b.n 800bb80 <osMutexWait+0x8c>
}
else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
800bb6e: 68f9 ldr r1, [r7, #12]
800bb70: 6878 ldr r0, [r7, #4]
800bb72: f000 ffad bl 800cad0 <xQueueSemaphoreTake>
800bb76: 4603 mov r3, r0
800bb78: 2b01 cmp r3, #1
800bb7a: d001 beq.n 800bb80 <osMutexWait+0x8c>
return osErrorOS;
800bb7c: 23ff movs r3, #255 ; 0xff
800bb7e: e000 b.n 800bb82 <osMutexWait+0x8e>
}
return osOK;
800bb80: 2300 movs r3, #0
}
800bb82: 4618 mov r0, r3
800bb84: 3710 adds r7, #16
800bb86: 46bd mov sp, r7
800bb88: bd80 pop {r7, pc}
800bb8a: bf00 nop
800bb8c: e000ed04 .word 0xe000ed04
0800bb90 <osMutexRelease>:
* @param mutex_id mutex ID obtained by \ref osMutexCreate.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osMutexRelease (osMutexId mutex_id)
{
800bb90: b580 push {r7, lr}
800bb92: b084 sub sp, #16
800bb94: af00 add r7, sp, #0
800bb96: 6078 str r0, [r7, #4]
osStatus result = osOK;
800bb98: 2300 movs r3, #0
800bb9a: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bb9c: 2300 movs r3, #0
800bb9e: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bba0: f7ff ff06 bl 800b9b0 <inHandlerMode>
800bba4: 4603 mov r3, r0
800bba6: 2b00 cmp r3, #0
800bba8: d016 beq.n 800bbd8 <osMutexRelease+0x48>
if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
800bbaa: f107 0308 add.w r3, r7, #8
800bbae: 4619 mov r1, r3
800bbb0: 6878 ldr r0, [r7, #4]
800bbb2: f000 fe19 bl 800c7e8 <xQueueGiveFromISR>
800bbb6: 4603 mov r3, r0
800bbb8: 2b01 cmp r3, #1
800bbba: d001 beq.n 800bbc0 <osMutexRelease+0x30>
return osErrorOS;
800bbbc: 23ff movs r3, #255 ; 0xff
800bbbe: e017 b.n 800bbf0 <osMutexRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bbc0: 68bb ldr r3, [r7, #8]
800bbc2: 2b00 cmp r3, #0
800bbc4: d013 beq.n 800bbee <osMutexRelease+0x5e>
800bbc6: 4b0c ldr r3, [pc, #48] ; (800bbf8 <osMutexRelease+0x68>)
800bbc8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bbcc: 601a str r2, [r3, #0]
800bbce: f3bf 8f4f dsb sy
800bbd2: f3bf 8f6f isb sy
800bbd6: e00a b.n 800bbee <osMutexRelease+0x5e>
}
else if (xSemaphoreGive(mutex_id) != pdTRUE)
800bbd8: 2300 movs r3, #0
800bbda: 2200 movs r2, #0
800bbdc: 2100 movs r1, #0
800bbde: 6878 ldr r0, [r7, #4]
800bbe0: f000 fc64 bl 800c4ac <xQueueGenericSend>
800bbe4: 4603 mov r3, r0
800bbe6: 2b01 cmp r3, #1
800bbe8: d001 beq.n 800bbee <osMutexRelease+0x5e>
{
result = osErrorOS;
800bbea: 23ff movs r3, #255 ; 0xff
800bbec: 60fb str r3, [r7, #12]
}
return result;
800bbee: 68fb ldr r3, [r7, #12]
}
800bbf0: 4618 mov r0, r3
800bbf2: 3710 adds r7, #16
800bbf4: 46bd mov sp, r7
800bbf6: bd80 pop {r7, pc}
800bbf8: e000ed04 .word 0xe000ed04
0800bbfc <osSemaphoreCreate>:
* @param count number of available resources.
* @retval semaphore ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
*/
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
{
800bbfc: b580 push {r7, lr}
800bbfe: b086 sub sp, #24
800bc00: af02 add r7, sp, #8
800bc02: 6078 str r0, [r7, #4]
800bc04: 6039 str r1, [r7, #0]
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
osSemaphoreId sema;
if (semaphore_def->controlblock != NULL){
800bc06: 687b ldr r3, [r7, #4]
800bc08: 685b ldr r3, [r3, #4]
800bc0a: 2b00 cmp r3, #0
800bc0c: d017 beq.n 800bc3e <osSemaphoreCreate+0x42>
if (count == 1) {
800bc0e: 683b ldr r3, [r7, #0]
800bc10: 2b01 cmp r3, #1
800bc12: d10b bne.n 800bc2c <osSemaphoreCreate+0x30>
return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
800bc14: 687b ldr r3, [r7, #4]
800bc16: 685a ldr r2, [r3, #4]
800bc18: 2303 movs r3, #3
800bc1a: 9300 str r3, [sp, #0]
800bc1c: 4613 mov r3, r2
800bc1e: 2200 movs r2, #0
800bc20: 2100 movs r1, #0
800bc22: 2001 movs r0, #1
800bc24: f000 faaa bl 800c17c <xQueueGenericCreateStatic>
800bc28: 4603 mov r3, r0
800bc2a: e023 b.n 800bc74 <osSemaphoreCreate+0x78>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
800bc2c: 6838 ldr r0, [r7, #0]
800bc2e: 6839 ldr r1, [r7, #0]
800bc30: 687b ldr r3, [r7, #4]
800bc32: 685b ldr r3, [r3, #4]
800bc34: 461a mov r2, r3
800bc36: f000 fbcb bl 800c3d0 <xQueueCreateCountingSemaphoreStatic>
800bc3a: 4603 mov r3, r0
800bc3c: e01a b.n 800bc74 <osSemaphoreCreate+0x78>
return NULL;
#endif
}
}
else {
if (count == 1) {
800bc3e: 683b ldr r3, [r7, #0]
800bc40: 2b01 cmp r3, #1
800bc42: d110 bne.n 800bc66 <osSemaphoreCreate+0x6a>
vSemaphoreCreateBinary(sema);
800bc44: 2203 movs r2, #3
800bc46: 2100 movs r1, #0
800bc48: 2001 movs r0, #1
800bc4a: f000 fb14 bl 800c276 <xQueueGenericCreate>
800bc4e: 60f8 str r0, [r7, #12]
800bc50: 68fb ldr r3, [r7, #12]
800bc52: 2b00 cmp r3, #0
800bc54: d005 beq.n 800bc62 <osSemaphoreCreate+0x66>
800bc56: 2300 movs r3, #0
800bc58: 2200 movs r2, #0
800bc5a: 2100 movs r1, #0
800bc5c: 68f8 ldr r0, [r7, #12]
800bc5e: f000 fc25 bl 800c4ac <xQueueGenericSend>
return sema;
800bc62: 68fb ldr r3, [r7, #12]
800bc64: e006 b.n 800bc74 <osSemaphoreCreate+0x78>
}
else {
#if (configUSE_COUNTING_SEMAPHORES == 1 )
return xSemaphoreCreateCounting(count, count);
800bc66: 683b ldr r3, [r7, #0]
800bc68: 683a ldr r2, [r7, #0]
800bc6a: 4611 mov r1, r2
800bc6c: 4618 mov r0, r3
800bc6e: f000 fbe8 bl 800c442 <xQueueCreateCountingSemaphore>
800bc72: 4603 mov r3, r0
#else
return NULL;
#endif
}
#endif
}
800bc74: 4618 mov r0, r3
800bc76: 3710 adds r7, #16
800bc78: 46bd mov sp, r7
800bc7a: bd80 pop {r7, pc}
0800bc7c <osSemaphoreWait>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval number of available tokens, or -1 in case of incorrect parameters.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
*/
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
{
800bc7c: b580 push {r7, lr}
800bc7e: b084 sub sp, #16
800bc80: af00 add r7, sp, #0
800bc82: 6078 str r0, [r7, #4]
800bc84: 6039 str r1, [r7, #0]
TickType_t ticks;
portBASE_TYPE taskWoken = pdFALSE;
800bc86: 2300 movs r3, #0
800bc88: 60bb str r3, [r7, #8]
if (semaphore_id == NULL) {
800bc8a: 687b ldr r3, [r7, #4]
800bc8c: 2b00 cmp r3, #0
800bc8e: d101 bne.n 800bc94 <osSemaphoreWait+0x18>
return osErrorParameter;
800bc90: 2380 movs r3, #128 ; 0x80
800bc92: e03a b.n 800bd0a <osSemaphoreWait+0x8e>
}
ticks = 0;
800bc94: 2300 movs r3, #0
800bc96: 60fb str r3, [r7, #12]
if (millisec == osWaitForever) {
800bc98: 683b ldr r3, [r7, #0]
800bc9a: f1b3 3fff cmp.w r3, #4294967295
800bc9e: d103 bne.n 800bca8 <osSemaphoreWait+0x2c>
ticks = portMAX_DELAY;
800bca0: f04f 33ff mov.w r3, #4294967295
800bca4: 60fb str r3, [r7, #12]
800bca6: e009 b.n 800bcbc <osSemaphoreWait+0x40>
}
else if (millisec != 0) {
800bca8: 683b ldr r3, [r7, #0]
800bcaa: 2b00 cmp r3, #0
800bcac: d006 beq.n 800bcbc <osSemaphoreWait+0x40>
ticks = millisec / portTICK_PERIOD_MS;
800bcae: 683b ldr r3, [r7, #0]
800bcb0: 60fb str r3, [r7, #12]
if (ticks == 0) {
800bcb2: 68fb ldr r3, [r7, #12]
800bcb4: 2b00 cmp r3, #0
800bcb6: d101 bne.n 800bcbc <osSemaphoreWait+0x40>
ticks = 1;
800bcb8: 2301 movs r3, #1
800bcba: 60fb str r3, [r7, #12]
}
}
if (inHandlerMode()) {
800bcbc: f7ff fe78 bl 800b9b0 <inHandlerMode>
800bcc0: 4603 mov r3, r0
800bcc2: 2b00 cmp r3, #0
800bcc4: d017 beq.n 800bcf6 <osSemaphoreWait+0x7a>
if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bcc6: f107 0308 add.w r3, r7, #8
800bcca: 461a mov r2, r3
800bccc: 2100 movs r1, #0
800bcce: 6878 ldr r0, [r7, #4]
800bcd0: f001 f80e bl 800ccf0 <xQueueReceiveFromISR>
800bcd4: 4603 mov r3, r0
800bcd6: 2b01 cmp r3, #1
800bcd8: d001 beq.n 800bcde <osSemaphoreWait+0x62>
return osErrorOS;
800bcda: 23ff movs r3, #255 ; 0xff
800bcdc: e015 b.n 800bd0a <osSemaphoreWait+0x8e>
}
portEND_SWITCHING_ISR(taskWoken);
800bcde: 68bb ldr r3, [r7, #8]
800bce0: 2b00 cmp r3, #0
800bce2: d011 beq.n 800bd08 <osSemaphoreWait+0x8c>
800bce4: 4b0b ldr r3, [pc, #44] ; (800bd14 <osSemaphoreWait+0x98>)
800bce6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bcea: 601a str r2, [r3, #0]
800bcec: f3bf 8f4f dsb sy
800bcf0: f3bf 8f6f isb sy
800bcf4: e008 b.n 800bd08 <osSemaphoreWait+0x8c>
}
else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
800bcf6: 68f9 ldr r1, [r7, #12]
800bcf8: 6878 ldr r0, [r7, #4]
800bcfa: f000 fee9 bl 800cad0 <xQueueSemaphoreTake>
800bcfe: 4603 mov r3, r0
800bd00: 2b01 cmp r3, #1
800bd02: d001 beq.n 800bd08 <osSemaphoreWait+0x8c>
return osErrorOS;
800bd04: 23ff movs r3, #255 ; 0xff
800bd06: e000 b.n 800bd0a <osSemaphoreWait+0x8e>
}
return osOK;
800bd08: 2300 movs r3, #0
}
800bd0a: 4618 mov r0, r3
800bd0c: 3710 adds r7, #16
800bd0e: 46bd mov sp, r7
800bd10: bd80 pop {r7, pc}
800bd12: bf00 nop
800bd14: e000ed04 .word 0xe000ed04
0800bd18 <osSemaphoreRelease>:
* @param semaphore_id semaphore object referenced with \ref osSemaphore.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
*/
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
{
800bd18: b580 push {r7, lr}
800bd1a: b084 sub sp, #16
800bd1c: af00 add r7, sp, #0
800bd1e: 6078 str r0, [r7, #4]
osStatus result = osOK;
800bd20: 2300 movs r3, #0
800bd22: 60fb str r3, [r7, #12]
portBASE_TYPE taskWoken = pdFALSE;
800bd24: 2300 movs r3, #0
800bd26: 60bb str r3, [r7, #8]
if (inHandlerMode()) {
800bd28: f7ff fe42 bl 800b9b0 <inHandlerMode>
800bd2c: 4603 mov r3, r0
800bd2e: 2b00 cmp r3, #0
800bd30: d016 beq.n 800bd60 <osSemaphoreRelease+0x48>
if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
800bd32: f107 0308 add.w r3, r7, #8
800bd36: 4619 mov r1, r3
800bd38: 6878 ldr r0, [r7, #4]
800bd3a: f000 fd55 bl 800c7e8 <xQueueGiveFromISR>
800bd3e: 4603 mov r3, r0
800bd40: 2b01 cmp r3, #1
800bd42: d001 beq.n 800bd48 <osSemaphoreRelease+0x30>
return osErrorOS;
800bd44: 23ff movs r3, #255 ; 0xff
800bd46: e017 b.n 800bd78 <osSemaphoreRelease+0x60>
}
portEND_SWITCHING_ISR(taskWoken);
800bd48: 68bb ldr r3, [r7, #8]
800bd4a: 2b00 cmp r3, #0
800bd4c: d013 beq.n 800bd76 <osSemaphoreRelease+0x5e>
800bd4e: 4b0c ldr r3, [pc, #48] ; (800bd80 <osSemaphoreRelease+0x68>)
800bd50: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800bd54: 601a str r2, [r3, #0]
800bd56: f3bf 8f4f dsb sy
800bd5a: f3bf 8f6f isb sy
800bd5e: e00a b.n 800bd76 <osSemaphoreRelease+0x5e>
}
else {
if (xSemaphoreGive(semaphore_id) != pdTRUE) {
800bd60: 2300 movs r3, #0
800bd62: 2200 movs r2, #0
800bd64: 2100 movs r1, #0
800bd66: 6878 ldr r0, [r7, #4]
800bd68: f000 fba0 bl 800c4ac <xQueueGenericSend>
800bd6c: 4603 mov r3, r0
800bd6e: 2b01 cmp r3, #1
800bd70: d001 beq.n 800bd76 <osSemaphoreRelease+0x5e>
result = osErrorOS;
800bd72: 23ff movs r3, #255 ; 0xff
800bd74: 60fb str r3, [r7, #12]
}
}
return result;
800bd76: 68fb ldr r3, [r7, #12]
}
800bd78: 4618 mov r0, r3
800bd7a: 3710 adds r7, #16
800bd7c: 46bd mov sp, r7
800bd7e: bd80 pop {r7, pc}
800bd80: e000ed04 .word 0xe000ed04
0800bd84 <osMessageCreate>:
* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
* @retval message queue ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
*/
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
{
800bd84: b590 push {r4, r7, lr}
800bd86: b085 sub sp, #20
800bd88: af02 add r7, sp, #8
800bd8a: 6078 str r0, [r7, #4]
800bd8c: 6039 str r1, [r7, #0]
(void) thread_id;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
800bd8e: 687b ldr r3, [r7, #4]
800bd90: 689b ldr r3, [r3, #8]
800bd92: 2b00 cmp r3, #0
800bd94: d012 beq.n 800bdbc <osMessageCreate+0x38>
800bd96: 687b ldr r3, [r7, #4]
800bd98: 68db ldr r3, [r3, #12]
800bd9a: 2b00 cmp r3, #0
800bd9c: d00e beq.n 800bdbc <osMessageCreate+0x38>
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
800bd9e: 687b ldr r3, [r7, #4]
800bda0: 6818 ldr r0, [r3, #0]
800bda2: 687b ldr r3, [r7, #4]
800bda4: 6859 ldr r1, [r3, #4]
800bda6: 687b ldr r3, [r7, #4]
800bda8: 689a ldr r2, [r3, #8]
800bdaa: 687b ldr r3, [r7, #4]
800bdac: 68dc ldr r4, [r3, #12]
800bdae: 2300 movs r3, #0
800bdb0: 9300 str r3, [sp, #0]
800bdb2: 4623 mov r3, r4
800bdb4: f000 f9e2 bl 800c17c <xQueueGenericCreateStatic>
800bdb8: 4603 mov r3, r0
800bdba: e008 b.n 800bdce <osMessageCreate+0x4a>
}
else {
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
800bdbc: 687b ldr r3, [r7, #4]
800bdbe: 6818 ldr r0, [r3, #0]
800bdc0: 687b ldr r3, [r7, #4]
800bdc2: 685b ldr r3, [r3, #4]
800bdc4: 2200 movs r2, #0
800bdc6: 4619 mov r1, r3
800bdc8: f000 fa55 bl 800c276 <xQueueGenericCreate>
800bdcc: 4603 mov r3, r0
#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
#else
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
#endif
}
800bdce: 4618 mov r0, r3
800bdd0: 370c adds r7, #12
800bdd2: 46bd mov sp, r7
800bdd4: bd90 pop {r4, r7, pc}
...
0800bdd8 <osMessagePut>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
*/
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
{
800bdd8: b580 push {r7, lr}
800bdda: b086 sub sp, #24
800bddc: af00 add r7, sp, #0
800bdde: 60f8 str r0, [r7, #12]
800bde0: 60b9 str r1, [r7, #8]
800bde2: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken = pdFALSE;
800bde4: 2300 movs r3, #0
800bde6: 613b str r3, [r7, #16]
TickType_t ticks;
ticks = millisec / portTICK_PERIOD_MS;
800bde8: 687b ldr r3, [r7, #4]
800bdea: 617b str r3, [r7, #20]
if (ticks == 0) {
800bdec: 697b ldr r3, [r7, #20]
800bdee: 2b00 cmp r3, #0
800bdf0: d101 bne.n 800bdf6 <osMessagePut+0x1e>
ticks = 1;
800bdf2: 2301 movs r3, #1
800bdf4: 617b str r3, [r7, #20]
}
if (inHandlerMode()) {
800bdf6: f7ff fddb bl 800b9b0 <inHandlerMode>
800bdfa: 4603 mov r3, r0
800bdfc: 2b00 cmp r3, #0
800bdfe: d018 beq.n 800be32 <osMessagePut+0x5a>
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
800be00: f107 0210 add.w r2, r7, #16
800be04: f107 0108 add.w r1, r7, #8
800be08: 2300 movs r3, #0
800be0a: 68f8 ldr r0, [r7, #12]
800be0c: f000 fc50 bl 800c6b0 <xQueueGenericSendFromISR>
800be10: 4603 mov r3, r0
800be12: 2b01 cmp r3, #1
800be14: d001 beq.n 800be1a <osMessagePut+0x42>
return osErrorOS;
800be16: 23ff movs r3, #255 ; 0xff
800be18: e018 b.n 800be4c <osMessagePut+0x74>
}
portEND_SWITCHING_ISR(taskWoken);
800be1a: 693b ldr r3, [r7, #16]
800be1c: 2b00 cmp r3, #0
800be1e: d014 beq.n 800be4a <osMessagePut+0x72>
800be20: 4b0c ldr r3, [pc, #48] ; (800be54 <osMessagePut+0x7c>)
800be22: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800be26: 601a str r2, [r3, #0]
800be28: f3bf 8f4f dsb sy
800be2c: f3bf 8f6f isb sy
800be30: e00b b.n 800be4a <osMessagePut+0x72>
}
else {
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
800be32: f107 0108 add.w r1, r7, #8
800be36: 2300 movs r3, #0
800be38: 697a ldr r2, [r7, #20]
800be3a: 68f8 ldr r0, [r7, #12]
800be3c: f000 fb36 bl 800c4ac <xQueueGenericSend>
800be40: 4603 mov r3, r0
800be42: 2b01 cmp r3, #1
800be44: d001 beq.n 800be4a <osMessagePut+0x72>
return osErrorOS;
800be46: 23ff movs r3, #255 ; 0xff
800be48: e000 b.n 800be4c <osMessagePut+0x74>
}
}
return osOK;
800be4a: 2300 movs r3, #0
}
800be4c: 4618 mov r0, r3
800be4e: 3718 adds r7, #24
800be50: 46bd mov sp, r7
800be52: bd80 pop {r7, pc}
800be54: e000ed04 .word 0xe000ed04
0800be58 <osMessageGet>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval event information that includes status code.
* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
*/
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
{
800be58: b590 push {r4, r7, lr}
800be5a: b08b sub sp, #44 ; 0x2c
800be5c: af00 add r7, sp, #0
800be5e: 60f8 str r0, [r7, #12]
800be60: 60b9 str r1, [r7, #8]
800be62: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken;
TickType_t ticks;
osEvent event;
event.def.message_id = queue_id;
800be64: 68bb ldr r3, [r7, #8]
800be66: 61fb str r3, [r7, #28]
event.value.v = 0;
800be68: 2300 movs r3, #0
800be6a: 61bb str r3, [r7, #24]
if (queue_id == NULL) {
800be6c: 68bb ldr r3, [r7, #8]
800be6e: 2b00 cmp r3, #0
800be70: d10a bne.n 800be88 <osMessageGet+0x30>
event.status = osErrorParameter;
800be72: 2380 movs r3, #128 ; 0x80
800be74: 617b str r3, [r7, #20]
return event;
800be76: 68fb ldr r3, [r7, #12]
800be78: 461c mov r4, r3
800be7a: f107 0314 add.w r3, r7, #20
800be7e: e893 0007 ldmia.w r3, {r0, r1, r2}
800be82: e884 0007 stmia.w r4, {r0, r1, r2}
800be86: e054 b.n 800bf32 <osMessageGet+0xda>
}
taskWoken = pdFALSE;
800be88: 2300 movs r3, #0
800be8a: 623b str r3, [r7, #32]
ticks = 0;
800be8c: 2300 movs r3, #0
800be8e: 627b str r3, [r7, #36] ; 0x24
if (millisec == osWaitForever) {
800be90: 687b ldr r3, [r7, #4]
800be92: f1b3 3fff cmp.w r3, #4294967295
800be96: d103 bne.n 800bea0 <osMessageGet+0x48>
ticks = portMAX_DELAY;
800be98: f04f 33ff mov.w r3, #4294967295
800be9c: 627b str r3, [r7, #36] ; 0x24
800be9e: e009 b.n 800beb4 <osMessageGet+0x5c>
}
else if (millisec != 0) {
800bea0: 687b ldr r3, [r7, #4]
800bea2: 2b00 cmp r3, #0
800bea4: d006 beq.n 800beb4 <osMessageGet+0x5c>
ticks = millisec / portTICK_PERIOD_MS;
800bea6: 687b ldr r3, [r7, #4]
800bea8: 627b str r3, [r7, #36] ; 0x24
if (ticks == 0) {
800beaa: 6a7b ldr r3, [r7, #36] ; 0x24
800beac: 2b00 cmp r3, #0
800beae: d101 bne.n 800beb4 <osMessageGet+0x5c>
ticks = 1;
800beb0: 2301 movs r3, #1
800beb2: 627b str r3, [r7, #36] ; 0x24
}
}
if (inHandlerMode()) {
800beb4: f7ff fd7c bl 800b9b0 <inHandlerMode>
800beb8: 4603 mov r3, r0
800beba: 2b00 cmp r3, #0
800bebc: d01c beq.n 800bef8 <osMessageGet+0xa0>
if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
800bebe: f107 0220 add.w r2, r7, #32
800bec2: f107 0314 add.w r3, r7, #20
800bec6: 3304 adds r3, #4
800bec8: 4619 mov r1, r3
800beca: 68b8 ldr r0, [r7, #8]
800becc: f000 ff10 bl 800ccf0 <xQueueReceiveFromISR>
800bed0: 4603 mov r3, r0
800bed2: 2b01 cmp r3, #1
800bed4: d102 bne.n 800bedc <osMessageGet+0x84>
/* We have mail */
event.status = osEventMessage;
800bed6: 2310 movs r3, #16
800bed8: 617b str r3, [r7, #20]
800beda: e001 b.n 800bee0 <osMessageGet+0x88>
}
else {
event.status = osOK;
800bedc: 2300 movs r3, #0
800bede: 617b str r3, [r7, #20]
}
portEND_SWITCHING_ISR(taskWoken);
800bee0: 6a3b ldr r3, [r7, #32]
800bee2: 2b00 cmp r3, #0
800bee4: d01d beq.n 800bf22 <osMessageGet+0xca>
800bee6: 4b15 ldr r3, [pc, #84] ; (800bf3c <osMessageGet+0xe4>)
800bee8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800beec: 601a str r2, [r3, #0]
800beee: f3bf 8f4f dsb sy
800bef2: f3bf 8f6f isb sy
800bef6: e014 b.n 800bf22 <osMessageGet+0xca>
}
else {
if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
800bef8: f107 0314 add.w r3, r7, #20
800befc: 3304 adds r3, #4
800befe: 6a7a ldr r2, [r7, #36] ; 0x24
800bf00: 4619 mov r1, r3
800bf02: 68b8 ldr r0, [r7, #8]
800bf04: f000 fd02 bl 800c90c <xQueueReceive>
800bf08: 4603 mov r3, r0
800bf0a: 2b01 cmp r3, #1
800bf0c: d102 bne.n 800bf14 <osMessageGet+0xbc>
/* We have mail */
event.status = osEventMessage;
800bf0e: 2310 movs r3, #16
800bf10: 617b str r3, [r7, #20]
800bf12: e006 b.n 800bf22 <osMessageGet+0xca>
}
else {
event.status = (ticks == 0) ? osOK : osEventTimeout;
800bf14: 6a7b ldr r3, [r7, #36] ; 0x24
800bf16: 2b00 cmp r3, #0
800bf18: d101 bne.n 800bf1e <osMessageGet+0xc6>
800bf1a: 2300 movs r3, #0
800bf1c: e000 b.n 800bf20 <osMessageGet+0xc8>
800bf1e: 2340 movs r3, #64 ; 0x40
800bf20: 617b str r3, [r7, #20]
}
}
return event;
800bf22: 68fb ldr r3, [r7, #12]
800bf24: 461c mov r4, r3
800bf26: f107 0314 add.w r3, r7, #20
800bf2a: e893 0007 ldmia.w r3, {r0, r1, r2}
800bf2e: e884 0007 stmia.w r4, {r0, r1, r2}
}
800bf32: 68f8 ldr r0, [r7, #12]
800bf34: 372c adds r7, #44 ; 0x2c
800bf36: 46bd mov sp, r7
800bf38: bd90 pop {r4, r7, pc}
800bf3a: bf00 nop
800bf3c: e000ed04 .word 0xe000ed04
0800bf40 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
800bf40: b480 push {r7}
800bf42: b083 sub sp, #12
800bf44: af00 add r7, sp, #0
800bf46: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf48: 687b ldr r3, [r7, #4]
800bf4a: f103 0208 add.w r2, r3, #8
800bf4e: 687b ldr r3, [r7, #4]
800bf50: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
800bf52: 687b ldr r3, [r7, #4]
800bf54: f04f 32ff mov.w r2, #4294967295
800bf58: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf5a: 687b ldr r3, [r7, #4]
800bf5c: f103 0208 add.w r2, r3, #8
800bf60: 687b ldr r3, [r7, #4]
800bf62: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800bf64: 687b ldr r3, [r7, #4]
800bf66: f103 0208 add.w r2, r3, #8
800bf6a: 687b ldr r3, [r7, #4]
800bf6c: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
800bf6e: 687b ldr r3, [r7, #4]
800bf70: 2200 movs r2, #0
800bf72: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
800bf74: bf00 nop
800bf76: 370c adds r7, #12
800bf78: 46bd mov sp, r7
800bf7a: f85d 7b04 ldr.w r7, [sp], #4
800bf7e: 4770 bx lr
0800bf80 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
800bf80: b480 push {r7}
800bf82: b083 sub sp, #12
800bf84: af00 add r7, sp, #0
800bf86: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
800bf88: 687b ldr r3, [r7, #4]
800bf8a: 2200 movs r2, #0
800bf8c: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
800bf8e: bf00 nop
800bf90: 370c adds r7, #12
800bf92: 46bd mov sp, r7
800bf94: f85d 7b04 ldr.w r7, [sp], #4
800bf98: 4770 bx lr
0800bf9a <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800bf9a: b480 push {r7}
800bf9c: b085 sub sp, #20
800bf9e: af00 add r7, sp, #0
800bfa0: 6078 str r0, [r7, #4]
800bfa2: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
800bfa4: 687b ldr r3, [r7, #4]
800bfa6: 685b ldr r3, [r3, #4]
800bfa8: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
800bfaa: 683b ldr r3, [r7, #0]
800bfac: 68fa ldr r2, [r7, #12]
800bfae: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
800bfb0: 68fb ldr r3, [r7, #12]
800bfb2: 689a ldr r2, [r3, #8]
800bfb4: 683b ldr r3, [r7, #0]
800bfb6: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
800bfb8: 68fb ldr r3, [r7, #12]
800bfba: 689b ldr r3, [r3, #8]
800bfbc: 683a ldr r2, [r7, #0]
800bfbe: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
800bfc0: 68fb ldr r3, [r7, #12]
800bfc2: 683a ldr r2, [r7, #0]
800bfc4: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
800bfc6: 683b ldr r3, [r7, #0]
800bfc8: 687a ldr r2, [r7, #4]
800bfca: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800bfcc: 687b ldr r3, [r7, #4]
800bfce: 681b ldr r3, [r3, #0]
800bfd0: 1c5a adds r2, r3, #1
800bfd2: 687b ldr r3, [r7, #4]
800bfd4: 601a str r2, [r3, #0]
}
800bfd6: bf00 nop
800bfd8: 3714 adds r7, #20
800bfda: 46bd mov sp, r7
800bfdc: f85d 7b04 ldr.w r7, [sp], #4
800bfe0: 4770 bx lr
0800bfe2 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800bfe2: b480 push {r7}
800bfe4: b085 sub sp, #20
800bfe6: af00 add r7, sp, #0
800bfe8: 6078 str r0, [r7, #4]
800bfea: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
800bfec: 683b ldr r3, [r7, #0]
800bfee: 681b ldr r3, [r3, #0]
800bff0: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
800bff2: 68bb ldr r3, [r7, #8]
800bff4: f1b3 3fff cmp.w r3, #4294967295
800bff8: d103 bne.n 800c002 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
800bffa: 687b ldr r3, [r7, #4]
800bffc: 691b ldr r3, [r3, #16]
800bffe: 60fb str r3, [r7, #12]
800c000: e00c b.n 800c01c <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
800c002: 687b ldr r3, [r7, #4]
800c004: 3308 adds r3, #8
800c006: 60fb str r3, [r7, #12]
800c008: e002 b.n 800c010 <vListInsert+0x2e>
800c00a: 68fb ldr r3, [r7, #12]
800c00c: 685b ldr r3, [r3, #4]
800c00e: 60fb str r3, [r7, #12]
800c010: 68fb ldr r3, [r7, #12]
800c012: 685b ldr r3, [r3, #4]
800c014: 681b ldr r3, [r3, #0]
800c016: 68ba ldr r2, [r7, #8]
800c018: 429a cmp r2, r3
800c01a: d2f6 bcs.n 800c00a <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
800c01c: 68fb ldr r3, [r7, #12]
800c01e: 685a ldr r2, [r3, #4]
800c020: 683b ldr r3, [r7, #0]
800c022: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
800c024: 683b ldr r3, [r7, #0]
800c026: 685b ldr r3, [r3, #4]
800c028: 683a ldr r2, [r7, #0]
800c02a: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
800c02c: 683b ldr r3, [r7, #0]
800c02e: 68fa ldr r2, [r7, #12]
800c030: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
800c032: 68fb ldr r3, [r7, #12]
800c034: 683a ldr r2, [r7, #0]
800c036: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
800c038: 683b ldr r3, [r7, #0]
800c03a: 687a ldr r2, [r7, #4]
800c03c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800c03e: 687b ldr r3, [r7, #4]
800c040: 681b ldr r3, [r3, #0]
800c042: 1c5a adds r2, r3, #1
800c044: 687b ldr r3, [r7, #4]
800c046: 601a str r2, [r3, #0]
}
800c048: bf00 nop
800c04a: 3714 adds r7, #20
800c04c: 46bd mov sp, r7
800c04e: f85d 7b04 ldr.w r7, [sp], #4
800c052: 4770 bx lr
0800c054 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
800c054: b480 push {r7}
800c056: b085 sub sp, #20
800c058: af00 add r7, sp, #0
800c05a: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
800c05c: 687b ldr r3, [r7, #4]
800c05e: 691b ldr r3, [r3, #16]
800c060: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
800c062: 687b ldr r3, [r7, #4]
800c064: 685b ldr r3, [r3, #4]
800c066: 687a ldr r2, [r7, #4]
800c068: 6892 ldr r2, [r2, #8]
800c06a: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
800c06c: 687b ldr r3, [r7, #4]
800c06e: 689b ldr r3, [r3, #8]
800c070: 687a ldr r2, [r7, #4]
800c072: 6852 ldr r2, [r2, #4]
800c074: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
800c076: 68fb ldr r3, [r7, #12]
800c078: 685b ldr r3, [r3, #4]
800c07a: 687a ldr r2, [r7, #4]
800c07c: 429a cmp r2, r3
800c07e: d103 bne.n 800c088 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
800c080: 687b ldr r3, [r7, #4]
800c082: 689a ldr r2, [r3, #8]
800c084: 68fb ldr r3, [r7, #12]
800c086: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
800c088: 687b ldr r3, [r7, #4]
800c08a: 2200 movs r2, #0
800c08c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
800c08e: 68fb ldr r3, [r7, #12]
800c090: 681b ldr r3, [r3, #0]
800c092: 1e5a subs r2, r3, #1
800c094: 68fb ldr r3, [r7, #12]
800c096: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
800c098: 68fb ldr r3, [r7, #12]
800c09a: 681b ldr r3, [r3, #0]
}
800c09c: 4618 mov r0, r3
800c09e: 3714 adds r7, #20
800c0a0: 46bd mov sp, r7
800c0a2: f85d 7b04 ldr.w r7, [sp], #4
800c0a6: 4770 bx lr
0800c0a8 <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
800c0a8: b580 push {r7, lr}
800c0aa: b084 sub sp, #16
800c0ac: af00 add r7, sp, #0
800c0ae: 6078 str r0, [r7, #4]
800c0b0: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
800c0b2: 687b ldr r3, [r7, #4]
800c0b4: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
800c0b6: 68fb ldr r3, [r7, #12]
800c0b8: 2b00 cmp r3, #0
800c0ba: d10b bne.n 800c0d4 <xQueueGenericReset+0x2c>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
800c0bc: f04f 0350 mov.w r3, #80 ; 0x50
800c0c0: b672 cpsid i
800c0c2: f383 8811 msr BASEPRI, r3
800c0c6: f3bf 8f6f isb sy
800c0ca: f3bf 8f4f dsb sy
800c0ce: b662 cpsie i
800c0d0: 60bb str r3, [r7, #8]
800c0d2: e7fe b.n 800c0d2 <xQueueGenericReset+0x2a>
taskENTER_CRITICAL();
800c0d4: f002 fa38 bl 800e548 <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c0d8: 68fb ldr r3, [r7, #12]
800c0da: 681a ldr r2, [r3, #0]
800c0dc: 68fb ldr r3, [r7, #12]
800c0de: 6bdb ldr r3, [r3, #60] ; 0x3c
800c0e0: 68f9 ldr r1, [r7, #12]
800c0e2: 6c09 ldr r1, [r1, #64] ; 0x40
800c0e4: fb01 f303 mul.w r3, r1, r3
800c0e8: 441a add r2, r3
800c0ea: 68fb ldr r3, [r7, #12]
800c0ec: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
800c0ee: 68fb ldr r3, [r7, #12]
800c0f0: 2200 movs r2, #0
800c0f2: 639a str r2, [r3, #56] ; 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
800c0f4: 68fb ldr r3, [r7, #12]
800c0f6: 681a ldr r2, [r3, #0]
800c0f8: 68fb ldr r3, [r7, #12]
800c0fa: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c0fc: 68fb ldr r3, [r7, #12]
800c0fe: 681a ldr r2, [r3, #0]
800c100: 68fb ldr r3, [r7, #12]
800c102: 6bdb ldr r3, [r3, #60] ; 0x3c
800c104: 3b01 subs r3, #1
800c106: 68f9 ldr r1, [r7, #12]
800c108: 6c09 ldr r1, [r1, #64] ; 0x40
800c10a: fb01 f303 mul.w r3, r1, r3
800c10e: 441a add r2, r3
800c110: 68fb ldr r3, [r7, #12]
800c112: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
800c114: 68fb ldr r3, [r7, #12]
800c116: 22ff movs r2, #255 ; 0xff
800c118: f883 2044 strb.w r2, [r3, #68] ; 0x44
pxQueue->cTxLock = queueUNLOCKED;
800c11c: 68fb ldr r3, [r7, #12]
800c11e: 22ff movs r2, #255 ; 0xff
800c120: f883 2045 strb.w r2, [r3, #69] ; 0x45
if( xNewQueue == pdFALSE )
800c124: 683b ldr r3, [r7, #0]
800c126: 2b00 cmp r3, #0
800c128: d114 bne.n 800c154 <xQueueGenericReset+0xac>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c12a: 68fb ldr r3, [r7, #12]
800c12c: 691b ldr r3, [r3, #16]
800c12e: 2b00 cmp r3, #0
800c130: d01a beq.n 800c168 <xQueueGenericReset+0xc0>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c132: 68fb ldr r3, [r7, #12]
800c134: 3310 adds r3, #16
800c136: 4618 mov r0, r3
800c138: f001 fd00 bl 800db3c <xTaskRemoveFromEventList>
800c13c: 4603 mov r3, r0
800c13e: 2b00 cmp r3, #0
800c140: d012 beq.n 800c168 <xQueueGenericReset+0xc0>
{
queueYIELD_IF_USING_PREEMPTION();
800c142: 4b0d ldr r3, [pc, #52] ; (800c178 <xQueueGenericReset+0xd0>)
800c144: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c148: 601a str r2, [r3, #0]
800c14a: f3bf 8f4f dsb sy
800c14e: f3bf 8f6f isb sy
800c152: e009 b.n 800c168 <xQueueGenericReset+0xc0>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
800c154: 68fb ldr r3, [r7, #12]
800c156: 3310 adds r3, #16
800c158: 4618 mov r0, r3
800c15a: f7ff fef1 bl 800bf40 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
800c15e: 68fb ldr r3, [r7, #12]
800c160: 3324 adds r3, #36 ; 0x24
800c162: 4618 mov r0, r3
800c164: f7ff feec bl 800bf40 <vListInitialise>
}
}
taskEXIT_CRITICAL();
800c168: f002 fa20 bl 800e5ac <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
800c16c: 2301 movs r3, #1
}
800c16e: 4618 mov r0, r3
800c170: 3710 adds r7, #16
800c172: 46bd mov sp, r7
800c174: bd80 pop {r7, pc}
800c176: bf00 nop
800c178: e000ed04 .word 0xe000ed04
0800c17c <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
800c17c: b580 push {r7, lr}
800c17e: b08e sub sp, #56 ; 0x38
800c180: af02 add r7, sp, #8
800c182: 60f8 str r0, [r7, #12]
800c184: 60b9 str r1, [r7, #8]
800c186: 607a str r2, [r7, #4]
800c188: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c18a: 68fb ldr r3, [r7, #12]
800c18c: 2b00 cmp r3, #0
800c18e: d10b bne.n 800c1a8 <xQueueGenericCreateStatic+0x2c>
800c190: f04f 0350 mov.w r3, #80 ; 0x50
800c194: b672 cpsid i
800c196: f383 8811 msr BASEPRI, r3
800c19a: f3bf 8f6f isb sy
800c19e: f3bf 8f4f dsb sy
800c1a2: b662 cpsie i
800c1a4: 62bb str r3, [r7, #40] ; 0x28
800c1a6: e7fe b.n 800c1a6 <xQueueGenericCreateStatic+0x2a>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
800c1a8: 683b ldr r3, [r7, #0]
800c1aa: 2b00 cmp r3, #0
800c1ac: d10b bne.n 800c1c6 <xQueueGenericCreateStatic+0x4a>
800c1ae: f04f 0350 mov.w r3, #80 ; 0x50
800c1b2: b672 cpsid i
800c1b4: f383 8811 msr BASEPRI, r3
800c1b8: f3bf 8f6f isb sy
800c1bc: f3bf 8f4f dsb sy
800c1c0: b662 cpsie i
800c1c2: 627b str r3, [r7, #36] ; 0x24
800c1c4: e7fe b.n 800c1c4 <xQueueGenericCreateStatic+0x48>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
800c1c6: 687b ldr r3, [r7, #4]
800c1c8: 2b00 cmp r3, #0
800c1ca: d002 beq.n 800c1d2 <xQueueGenericCreateStatic+0x56>
800c1cc: 68bb ldr r3, [r7, #8]
800c1ce: 2b00 cmp r3, #0
800c1d0: d001 beq.n 800c1d6 <xQueueGenericCreateStatic+0x5a>
800c1d2: 2301 movs r3, #1
800c1d4: e000 b.n 800c1d8 <xQueueGenericCreateStatic+0x5c>
800c1d6: 2300 movs r3, #0
800c1d8: 2b00 cmp r3, #0
800c1da: d10b bne.n 800c1f4 <xQueueGenericCreateStatic+0x78>
800c1dc: f04f 0350 mov.w r3, #80 ; 0x50
800c1e0: b672 cpsid i
800c1e2: f383 8811 msr BASEPRI, r3
800c1e6: f3bf 8f6f isb sy
800c1ea: f3bf 8f4f dsb sy
800c1ee: b662 cpsie i
800c1f0: 623b str r3, [r7, #32]
800c1f2: e7fe b.n 800c1f2 <xQueueGenericCreateStatic+0x76>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
800c1f4: 687b ldr r3, [r7, #4]
800c1f6: 2b00 cmp r3, #0
800c1f8: d102 bne.n 800c200 <xQueueGenericCreateStatic+0x84>
800c1fa: 68bb ldr r3, [r7, #8]
800c1fc: 2b00 cmp r3, #0
800c1fe: d101 bne.n 800c204 <xQueueGenericCreateStatic+0x88>
800c200: 2301 movs r3, #1
800c202: e000 b.n 800c206 <xQueueGenericCreateStatic+0x8a>
800c204: 2300 movs r3, #0
800c206: 2b00 cmp r3, #0
800c208: d10b bne.n 800c222 <xQueueGenericCreateStatic+0xa6>
800c20a: f04f 0350 mov.w r3, #80 ; 0x50
800c20e: b672 cpsid i
800c210: f383 8811 msr BASEPRI, r3
800c214: f3bf 8f6f isb sy
800c218: f3bf 8f4f dsb sy
800c21c: b662 cpsie i
800c21e: 61fb str r3, [r7, #28]
800c220: e7fe b.n 800c220 <xQueueGenericCreateStatic+0xa4>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
800c222: 2348 movs r3, #72 ; 0x48
800c224: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
800c226: 697b ldr r3, [r7, #20]
800c228: 2b48 cmp r3, #72 ; 0x48
800c22a: d00b beq.n 800c244 <xQueueGenericCreateStatic+0xc8>
800c22c: f04f 0350 mov.w r3, #80 ; 0x50
800c230: b672 cpsid i
800c232: f383 8811 msr BASEPRI, r3
800c236: f3bf 8f6f isb sy
800c23a: f3bf 8f4f dsb sy
800c23e: b662 cpsie i
800c240: 61bb str r3, [r7, #24]
800c242: e7fe b.n 800c242 <xQueueGenericCreateStatic+0xc6>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
800c244: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800c246: 683b ldr r3, [r7, #0]
800c248: 62fb str r3, [r7, #44] ; 0x2c
if( pxNewQueue != NULL )
800c24a: 6afb ldr r3, [r7, #44] ; 0x2c
800c24c: 2b00 cmp r3, #0
800c24e: d00d beq.n 800c26c <xQueueGenericCreateStatic+0xf0>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
800c250: 6afb ldr r3, [r7, #44] ; 0x2c
800c252: 2201 movs r2, #1
800c254: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c258: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
800c25c: 6afb ldr r3, [r7, #44] ; 0x2c
800c25e: 9300 str r3, [sp, #0]
800c260: 4613 mov r3, r2
800c262: 687a ldr r2, [r7, #4]
800c264: 68b9 ldr r1, [r7, #8]
800c266: 68f8 ldr r0, [r7, #12]
800c268: f000 f846 bl 800c2f8 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c26c: 6afb ldr r3, [r7, #44] ; 0x2c
}
800c26e: 4618 mov r0, r3
800c270: 3730 adds r7, #48 ; 0x30
800c272: 46bd mov sp, r7
800c274: bd80 pop {r7, pc}
0800c276 <xQueueGenericCreate>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
{
800c276: b580 push {r7, lr}
800c278: b08a sub sp, #40 ; 0x28
800c27a: af02 add r7, sp, #8
800c27c: 60f8 str r0, [r7, #12]
800c27e: 60b9 str r1, [r7, #8]
800c280: 4613 mov r3, r2
800c282: 71fb strb r3, [r7, #7]
Queue_t *pxNewQueue;
size_t xQueueSizeInBytes;
uint8_t *pucQueueStorage;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
800c284: 68fb ldr r3, [r7, #12]
800c286: 2b00 cmp r3, #0
800c288: d10b bne.n 800c2a2 <xQueueGenericCreate+0x2c>
800c28a: f04f 0350 mov.w r3, #80 ; 0x50
800c28e: b672 cpsid i
800c290: f383 8811 msr BASEPRI, r3
800c294: f3bf 8f6f isb sy
800c298: f3bf 8f4f dsb sy
800c29c: b662 cpsie i
800c29e: 613b str r3, [r7, #16]
800c2a0: e7fe b.n 800c2a0 <xQueueGenericCreate+0x2a>
if( uxItemSize == ( UBaseType_t ) 0 )
800c2a2: 68bb ldr r3, [r7, #8]
800c2a4: 2b00 cmp r3, #0
800c2a6: d102 bne.n 800c2ae <xQueueGenericCreate+0x38>
{
/* There is not going to be a queue storage area. */
xQueueSizeInBytes = ( size_t ) 0;
800c2a8: 2300 movs r3, #0
800c2aa: 61fb str r3, [r7, #28]
800c2ac: e004 b.n 800c2b8 <xQueueGenericCreate+0x42>
}
else
{
/* Allocate enough space to hold the maximum number of items that
can be in the queue at any time. */
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800c2ae: 68fb ldr r3, [r7, #12]
800c2b0: 68ba ldr r2, [r7, #8]
800c2b2: fb02 f303 mul.w r3, r2, r3
800c2b6: 61fb str r3, [r7, #28]
alignment requirements of the Queue_t structure - which in this case
is an int8_t *. Therefore, whenever the stack alignment requirements
are greater than or equal to the pointer to char requirements the cast
is safe. In other cases alignment requirements are not strict (one or
two bytes). */
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
800c2b8: 69fb ldr r3, [r7, #28]
800c2ba: 3348 adds r3, #72 ; 0x48
800c2bc: 4618 mov r0, r3
800c2be: f002 fa65 bl 800e78c <pvPortMalloc>
800c2c2: 61b8 str r0, [r7, #24]
if( pxNewQueue != NULL )
800c2c4: 69bb ldr r3, [r7, #24]
800c2c6: 2b00 cmp r3, #0
800c2c8: d011 beq.n 800c2ee <xQueueGenericCreate+0x78>
{
/* Jump past the queue structure to find the location of the queue
storage area. */
pucQueueStorage = ( uint8_t * ) pxNewQueue;
800c2ca: 69bb ldr r3, [r7, #24]
800c2cc: 617b str r3, [r7, #20]
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
800c2ce: 697b ldr r3, [r7, #20]
800c2d0: 3348 adds r3, #72 ; 0x48
800c2d2: 617b str r3, [r7, #20]
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
/* Queues can be created either statically or dynamically, so
note this task was created dynamically in case it is later
deleted. */
pxNewQueue->ucStaticallyAllocated = pdFALSE;
800c2d4: 69bb ldr r3, [r7, #24]
800c2d6: 2200 movs r2, #0
800c2d8: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
800c2dc: 79fa ldrb r2, [r7, #7]
800c2de: 69bb ldr r3, [r7, #24]
800c2e0: 9300 str r3, [sp, #0]
800c2e2: 4613 mov r3, r2
800c2e4: 697a ldr r2, [r7, #20]
800c2e6: 68b9 ldr r1, [r7, #8]
800c2e8: 68f8 ldr r0, [r7, #12]
800c2ea: f000 f805 bl 800c2f8 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
800c2ee: 69bb ldr r3, [r7, #24]
}
800c2f0: 4618 mov r0, r3
800c2f2: 3720 adds r7, #32
800c2f4: 46bd mov sp, r7
800c2f6: bd80 pop {r7, pc}
0800c2f8 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
800c2f8: b580 push {r7, lr}
800c2fa: b084 sub sp, #16
800c2fc: af00 add r7, sp, #0
800c2fe: 60f8 str r0, [r7, #12]
800c300: 60b9 str r1, [r7, #8]
800c302: 607a str r2, [r7, #4]
800c304: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
800c306: 68bb ldr r3, [r7, #8]
800c308: 2b00 cmp r3, #0
800c30a: d103 bne.n 800c314 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
800c30c: 69bb ldr r3, [r7, #24]
800c30e: 69ba ldr r2, [r7, #24]
800c310: 601a str r2, [r3, #0]
800c312: e002 b.n 800c31a <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
800c314: 69bb ldr r3, [r7, #24]
800c316: 687a ldr r2, [r7, #4]
800c318: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
800c31a: 69bb ldr r3, [r7, #24]
800c31c: 68fa ldr r2, [r7, #12]
800c31e: 63da str r2, [r3, #60] ; 0x3c
pxNewQueue->uxItemSize = uxItemSize;
800c320: 69bb ldr r3, [r7, #24]
800c322: 68ba ldr r2, [r7, #8]
800c324: 641a str r2, [r3, #64] ; 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
800c326: 2101 movs r1, #1
800c328: 69b8 ldr r0, [r7, #24]
800c32a: f7ff febd bl 800c0a8 <xQueueGenericReset>
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
800c32e: bf00 nop
800c330: 3710 adds r7, #16
800c332: 46bd mov sp, r7
800c334: bd80 pop {r7, pc}
0800c336 <prvInitialiseMutex>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static void prvInitialiseMutex( Queue_t *pxNewQueue )
{
800c336: b580 push {r7, lr}
800c338: b082 sub sp, #8
800c33a: af00 add r7, sp, #0
800c33c: 6078 str r0, [r7, #4]
if( pxNewQueue != NULL )
800c33e: 687b ldr r3, [r7, #4]
800c340: 2b00 cmp r3, #0
800c342: d00e beq.n 800c362 <prvInitialiseMutex+0x2c>
{
/* The queue create function will set all the queue structure members
correctly for a generic queue, but this function is creating a
mutex. Overwrite those members that need to be set differently -
in particular the information required for priority inheritance. */
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
800c344: 687b ldr r3, [r7, #4]
800c346: 2200 movs r2, #0
800c348: 609a str r2, [r3, #8]
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
800c34a: 687b ldr r3, [r7, #4]
800c34c: 2200 movs r2, #0
800c34e: 601a str r2, [r3, #0]
/* In case this is a recursive mutex. */
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
800c350: 687b ldr r3, [r7, #4]
800c352: 2200 movs r2, #0
800c354: 60da str r2, [r3, #12]
traceCREATE_MUTEX( pxNewQueue );
/* Start with the semaphore in the expected state. */
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
800c356: 2300 movs r3, #0
800c358: 2200 movs r2, #0
800c35a: 2100 movs r1, #0
800c35c: 6878 ldr r0, [r7, #4]
800c35e: f000 f8a5 bl 800c4ac <xQueueGenericSend>
}
else
{
traceCREATE_MUTEX_FAILED();
}
}
800c362: bf00 nop
800c364: 3708 adds r7, #8
800c366: 46bd mov sp, r7
800c368: bd80 pop {r7, pc}
0800c36a <xQueueCreateMutex>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
{
800c36a: b580 push {r7, lr}
800c36c: b086 sub sp, #24
800c36e: af00 add r7, sp, #0
800c370: 4603 mov r3, r0
800c372: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c374: 2301 movs r3, #1
800c376: 617b str r3, [r7, #20]
800c378: 2300 movs r3, #0
800c37a: 613b str r3, [r7, #16]
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
800c37c: 79fb ldrb r3, [r7, #7]
800c37e: 461a mov r2, r3
800c380: 6939 ldr r1, [r7, #16]
800c382: 6978 ldr r0, [r7, #20]
800c384: f7ff ff77 bl 800c276 <xQueueGenericCreate>
800c388: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c38a: 68f8 ldr r0, [r7, #12]
800c38c: f7ff ffd3 bl 800c336 <prvInitialiseMutex>
return xNewQueue;
800c390: 68fb ldr r3, [r7, #12]
}
800c392: 4618 mov r0, r3
800c394: 3718 adds r7, #24
800c396: 46bd mov sp, r7
800c398: bd80 pop {r7, pc}
0800c39a <xQueueCreateMutexStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
{
800c39a: b580 push {r7, lr}
800c39c: b088 sub sp, #32
800c39e: af02 add r7, sp, #8
800c3a0: 4603 mov r3, r0
800c3a2: 6039 str r1, [r7, #0]
800c3a4: 71fb strb r3, [r7, #7]
QueueHandle_t xNewQueue;
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
800c3a6: 2301 movs r3, #1
800c3a8: 617b str r3, [r7, #20]
800c3aa: 2300 movs r3, #0
800c3ac: 613b str r3, [r7, #16]
/* Prevent compiler warnings about unused parameters if
configUSE_TRACE_FACILITY does not equal 1. */
( void ) ucQueueType;
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
800c3ae: 79fb ldrb r3, [r7, #7]
800c3b0: 9300 str r3, [sp, #0]
800c3b2: 683b ldr r3, [r7, #0]
800c3b4: 2200 movs r2, #0
800c3b6: 6939 ldr r1, [r7, #16]
800c3b8: 6978 ldr r0, [r7, #20]
800c3ba: f7ff fedf bl 800c17c <xQueueGenericCreateStatic>
800c3be: 60f8 str r0, [r7, #12]
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
800c3c0: 68f8 ldr r0, [r7, #12]
800c3c2: f7ff ffb8 bl 800c336 <prvInitialiseMutex>
return xNewQueue;
800c3c6: 68fb ldr r3, [r7, #12]
}
800c3c8: 4618 mov r0, r3
800c3ca: 3718 adds r7, #24
800c3cc: 46bd mov sp, r7
800c3ce: bd80 pop {r7, pc}
0800c3d0 <xQueueCreateCountingSemaphoreStatic>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
{
800c3d0: b580 push {r7, lr}
800c3d2: b08a sub sp, #40 ; 0x28
800c3d4: af02 add r7, sp, #8
800c3d6: 60f8 str r0, [r7, #12]
800c3d8: 60b9 str r1, [r7, #8]
800c3da: 607a str r2, [r7, #4]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c3dc: 68fb ldr r3, [r7, #12]
800c3de: 2b00 cmp r3, #0
800c3e0: d10b bne.n 800c3fa <xQueueCreateCountingSemaphoreStatic+0x2a>
800c3e2: f04f 0350 mov.w r3, #80 ; 0x50
800c3e6: b672 cpsid i
800c3e8: f383 8811 msr BASEPRI, r3
800c3ec: f3bf 8f6f isb sy
800c3f0: f3bf 8f4f dsb sy
800c3f4: b662 cpsie i
800c3f6: 61bb str r3, [r7, #24]
800c3f8: e7fe b.n 800c3f8 <xQueueCreateCountingSemaphoreStatic+0x28>
configASSERT( uxInitialCount <= uxMaxCount );
800c3fa: 68ba ldr r2, [r7, #8]
800c3fc: 68fb ldr r3, [r7, #12]
800c3fe: 429a cmp r2, r3
800c400: d90b bls.n 800c41a <xQueueCreateCountingSemaphoreStatic+0x4a>
800c402: f04f 0350 mov.w r3, #80 ; 0x50
800c406: b672 cpsid i
800c408: f383 8811 msr BASEPRI, r3
800c40c: f3bf 8f6f isb sy
800c410: f3bf 8f4f dsb sy
800c414: b662 cpsie i
800c416: 617b str r3, [r7, #20]
800c418: e7fe b.n 800c418 <xQueueCreateCountingSemaphoreStatic+0x48>
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c41a: 2302 movs r3, #2
800c41c: 9300 str r3, [sp, #0]
800c41e: 687b ldr r3, [r7, #4]
800c420: 2200 movs r2, #0
800c422: 2100 movs r1, #0
800c424: 68f8 ldr r0, [r7, #12]
800c426: f7ff fea9 bl 800c17c <xQueueGenericCreateStatic>
800c42a: 61f8 str r0, [r7, #28]
if( xHandle != NULL )
800c42c: 69fb ldr r3, [r7, #28]
800c42e: 2b00 cmp r3, #0
800c430: d002 beq.n 800c438 <xQueueCreateCountingSemaphoreStatic+0x68>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c432: 69fb ldr r3, [r7, #28]
800c434: 68ba ldr r2, [r7, #8]
800c436: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c438: 69fb ldr r3, [r7, #28]
}
800c43a: 4618 mov r0, r3
800c43c: 3720 adds r7, #32
800c43e: 46bd mov sp, r7
800c440: bd80 pop {r7, pc}
0800c442 <xQueueCreateCountingSemaphore>:
/*-----------------------------------------------------------*/
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
{
800c442: b580 push {r7, lr}
800c444: b086 sub sp, #24
800c446: af00 add r7, sp, #0
800c448: 6078 str r0, [r7, #4]
800c44a: 6039 str r1, [r7, #0]
QueueHandle_t xHandle;
configASSERT( uxMaxCount != 0 );
800c44c: 687b ldr r3, [r7, #4]
800c44e: 2b00 cmp r3, #0
800c450: d10b bne.n 800c46a <xQueueCreateCountingSemaphore+0x28>
800c452: f04f 0350 mov.w r3, #80 ; 0x50
800c456: b672 cpsid i
800c458: f383 8811 msr BASEPRI, r3
800c45c: f3bf 8f6f isb sy
800c460: f3bf 8f4f dsb sy
800c464: b662 cpsie i
800c466: 613b str r3, [r7, #16]
800c468: e7fe b.n 800c468 <xQueueCreateCountingSemaphore+0x26>
configASSERT( uxInitialCount <= uxMaxCount );
800c46a: 683a ldr r2, [r7, #0]
800c46c: 687b ldr r3, [r7, #4]
800c46e: 429a cmp r2, r3
800c470: d90b bls.n 800c48a <xQueueCreateCountingSemaphore+0x48>
800c472: f04f 0350 mov.w r3, #80 ; 0x50
800c476: b672 cpsid i
800c478: f383 8811 msr BASEPRI, r3
800c47c: f3bf 8f6f isb sy
800c480: f3bf 8f4f dsb sy
800c484: b662 cpsie i
800c486: 60fb str r3, [r7, #12]
800c488: e7fe b.n 800c488 <xQueueCreateCountingSemaphore+0x46>
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
800c48a: 2202 movs r2, #2
800c48c: 2100 movs r1, #0
800c48e: 6878 ldr r0, [r7, #4]
800c490: f7ff fef1 bl 800c276 <xQueueGenericCreate>
800c494: 6178 str r0, [r7, #20]
if( xHandle != NULL )
800c496: 697b ldr r3, [r7, #20]
800c498: 2b00 cmp r3, #0
800c49a: d002 beq.n 800c4a2 <xQueueCreateCountingSemaphore+0x60>
{
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
800c49c: 697b ldr r3, [r7, #20]
800c49e: 683a ldr r2, [r7, #0]
800c4a0: 639a str r2, [r3, #56] ; 0x38
else
{
traceCREATE_COUNTING_SEMAPHORE_FAILED();
}
return xHandle;
800c4a2: 697b ldr r3, [r7, #20]
}
800c4a4: 4618 mov r0, r3
800c4a6: 3718 adds r7, #24
800c4a8: 46bd mov sp, r7
800c4aa: bd80 pop {r7, pc}
0800c4ac <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
800c4ac: b580 push {r7, lr}
800c4ae: b08e sub sp, #56 ; 0x38
800c4b0: af00 add r7, sp, #0
800c4b2: 60f8 str r0, [r7, #12]
800c4b4: 60b9 str r1, [r7, #8]
800c4b6: 607a str r2, [r7, #4]
800c4b8: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
800c4ba: 2300 movs r3, #0
800c4bc: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c4be: 68fb ldr r3, [r7, #12]
800c4c0: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c4c2: 6b3b ldr r3, [r7, #48] ; 0x30
800c4c4: 2b00 cmp r3, #0
800c4c6: d10b bne.n 800c4e0 <xQueueGenericSend+0x34>
800c4c8: f04f 0350 mov.w r3, #80 ; 0x50
800c4cc: b672 cpsid i
800c4ce: f383 8811 msr BASEPRI, r3
800c4d2: f3bf 8f6f isb sy
800c4d6: f3bf 8f4f dsb sy
800c4da: b662 cpsie i
800c4dc: 62bb str r3, [r7, #40] ; 0x28
800c4de: e7fe b.n 800c4de <xQueueGenericSend+0x32>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c4e0: 68bb ldr r3, [r7, #8]
800c4e2: 2b00 cmp r3, #0
800c4e4: d103 bne.n 800c4ee <xQueueGenericSend+0x42>
800c4e6: 6b3b ldr r3, [r7, #48] ; 0x30
800c4e8: 6c1b ldr r3, [r3, #64] ; 0x40
800c4ea: 2b00 cmp r3, #0
800c4ec: d101 bne.n 800c4f2 <xQueueGenericSend+0x46>
800c4ee: 2301 movs r3, #1
800c4f0: e000 b.n 800c4f4 <xQueueGenericSend+0x48>
800c4f2: 2300 movs r3, #0
800c4f4: 2b00 cmp r3, #0
800c4f6: d10b bne.n 800c510 <xQueueGenericSend+0x64>
800c4f8: f04f 0350 mov.w r3, #80 ; 0x50
800c4fc: b672 cpsid i
800c4fe: f383 8811 msr BASEPRI, r3
800c502: f3bf 8f6f isb sy
800c506: f3bf 8f4f dsb sy
800c50a: b662 cpsie i
800c50c: 627b str r3, [r7, #36] ; 0x24
800c50e: e7fe b.n 800c50e <xQueueGenericSend+0x62>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c510: 683b ldr r3, [r7, #0]
800c512: 2b02 cmp r3, #2
800c514: d103 bne.n 800c51e <xQueueGenericSend+0x72>
800c516: 6b3b ldr r3, [r7, #48] ; 0x30
800c518: 6bdb ldr r3, [r3, #60] ; 0x3c
800c51a: 2b01 cmp r3, #1
800c51c: d101 bne.n 800c522 <xQueueGenericSend+0x76>
800c51e: 2301 movs r3, #1
800c520: e000 b.n 800c524 <xQueueGenericSend+0x78>
800c522: 2300 movs r3, #0
800c524: 2b00 cmp r3, #0
800c526: d10b bne.n 800c540 <xQueueGenericSend+0x94>
800c528: f04f 0350 mov.w r3, #80 ; 0x50
800c52c: b672 cpsid i
800c52e: f383 8811 msr BASEPRI, r3
800c532: f3bf 8f6f isb sy
800c536: f3bf 8f4f dsb sy
800c53a: b662 cpsie i
800c53c: 623b str r3, [r7, #32]
800c53e: e7fe b.n 800c53e <xQueueGenericSend+0x92>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c540: f001 fcbc bl 800debc <xTaskGetSchedulerState>
800c544: 4603 mov r3, r0
800c546: 2b00 cmp r3, #0
800c548: d102 bne.n 800c550 <xQueueGenericSend+0xa4>
800c54a: 687b ldr r3, [r7, #4]
800c54c: 2b00 cmp r3, #0
800c54e: d101 bne.n 800c554 <xQueueGenericSend+0xa8>
800c550: 2301 movs r3, #1
800c552: e000 b.n 800c556 <xQueueGenericSend+0xaa>
800c554: 2300 movs r3, #0
800c556: 2b00 cmp r3, #0
800c558: d10b bne.n 800c572 <xQueueGenericSend+0xc6>
800c55a: f04f 0350 mov.w r3, #80 ; 0x50
800c55e: b672 cpsid i
800c560: f383 8811 msr BASEPRI, r3
800c564: f3bf 8f6f isb sy
800c568: f3bf 8f4f dsb sy
800c56c: b662 cpsie i
800c56e: 61fb str r3, [r7, #28]
800c570: e7fe b.n 800c570 <xQueueGenericSend+0xc4>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c572: f001 ffe9 bl 800e548 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c576: 6b3b ldr r3, [r7, #48] ; 0x30
800c578: 6b9a ldr r2, [r3, #56] ; 0x38
800c57a: 6b3b ldr r3, [r7, #48] ; 0x30
800c57c: 6bdb ldr r3, [r3, #60] ; 0x3c
800c57e: 429a cmp r2, r3
800c580: d302 bcc.n 800c588 <xQueueGenericSend+0xdc>
800c582: 683b ldr r3, [r7, #0]
800c584: 2b02 cmp r3, #2
800c586: d129 bne.n 800c5dc <xQueueGenericSend+0x130>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c588: 683a ldr r2, [r7, #0]
800c58a: 68b9 ldr r1, [r7, #8]
800c58c: 6b38 ldr r0, [r7, #48] ; 0x30
800c58e: f000 fc4a bl 800ce26 <prvCopyDataToQueue>
800c592: 62f8 str r0, [r7, #44] ; 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c594: 6b3b ldr r3, [r7, #48] ; 0x30
800c596: 6a5b ldr r3, [r3, #36] ; 0x24
800c598: 2b00 cmp r3, #0
800c59a: d010 beq.n 800c5be <xQueueGenericSend+0x112>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c59c: 6b3b ldr r3, [r7, #48] ; 0x30
800c59e: 3324 adds r3, #36 ; 0x24
800c5a0: 4618 mov r0, r3
800c5a2: f001 facb bl 800db3c <xTaskRemoveFromEventList>
800c5a6: 4603 mov r3, r0
800c5a8: 2b00 cmp r3, #0
800c5aa: d013 beq.n 800c5d4 <xQueueGenericSend+0x128>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
800c5ac: 4b3f ldr r3, [pc, #252] ; (800c6ac <xQueueGenericSend+0x200>)
800c5ae: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c5b2: 601a str r2, [r3, #0]
800c5b4: f3bf 8f4f dsb sy
800c5b8: f3bf 8f6f isb sy
800c5bc: e00a b.n 800c5d4 <xQueueGenericSend+0x128>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800c5be: 6afb ldr r3, [r7, #44] ; 0x2c
800c5c0: 2b00 cmp r3, #0
800c5c2: d007 beq.n 800c5d4 <xQueueGenericSend+0x128>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
800c5c4: 4b39 ldr r3, [pc, #228] ; (800c6ac <xQueueGenericSend+0x200>)
800c5c6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c5ca: 601a str r2, [r3, #0]
800c5cc: f3bf 8f4f dsb sy
800c5d0: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
800c5d4: f001 ffea bl 800e5ac <vPortExitCritical>
return pdPASS;
800c5d8: 2301 movs r3, #1
800c5da: e063 b.n 800c6a4 <xQueueGenericSend+0x1f8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c5dc: 687b ldr r3, [r7, #4]
800c5de: 2b00 cmp r3, #0
800c5e0: d103 bne.n 800c5ea <xQueueGenericSend+0x13e>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c5e2: f001 ffe3 bl 800e5ac <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c5e6: 2300 movs r3, #0
800c5e8: e05c b.n 800c6a4 <xQueueGenericSend+0x1f8>
}
else if( xEntryTimeSet == pdFALSE )
800c5ea: 6b7b ldr r3, [r7, #52] ; 0x34
800c5ec: 2b00 cmp r3, #0
800c5ee: d106 bne.n 800c5fe <xQueueGenericSend+0x152>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800c5f0: f107 0314 add.w r3, r7, #20
800c5f4: 4618 mov r0, r3
800c5f6: f001 fb05 bl 800dc04 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800c5fa: 2301 movs r3, #1
800c5fc: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800c5fe: f001 ffd5 bl 800e5ac <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800c602: f001 f86b bl 800d6dc <vTaskSuspendAll>
prvLockQueue( pxQueue );
800c606: f001 ff9f bl 800e548 <vPortEnterCritical>
800c60a: 6b3b ldr r3, [r7, #48] ; 0x30
800c60c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800c610: b25b sxtb r3, r3
800c612: f1b3 3fff cmp.w r3, #4294967295
800c616: d103 bne.n 800c620 <xQueueGenericSend+0x174>
800c618: 6b3b ldr r3, [r7, #48] ; 0x30
800c61a: 2200 movs r2, #0
800c61c: f883 2044 strb.w r2, [r3, #68] ; 0x44
800c620: 6b3b ldr r3, [r7, #48] ; 0x30
800c622: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c626: b25b sxtb r3, r3
800c628: f1b3 3fff cmp.w r3, #4294967295
800c62c: d103 bne.n 800c636 <xQueueGenericSend+0x18a>
800c62e: 6b3b ldr r3, [r7, #48] ; 0x30
800c630: 2200 movs r2, #0
800c632: f883 2045 strb.w r2, [r3, #69] ; 0x45
800c636: f001 ffb9 bl 800e5ac <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800c63a: 1d3a adds r2, r7, #4
800c63c: f107 0314 add.w r3, r7, #20
800c640: 4611 mov r1, r2
800c642: 4618 mov r0, r3
800c644: f001 faf4 bl 800dc30 <xTaskCheckForTimeOut>
800c648: 4603 mov r3, r0
800c64a: 2b00 cmp r3, #0
800c64c: d124 bne.n 800c698 <xQueueGenericSend+0x1ec>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
800c64e: 6b38 ldr r0, [r7, #48] ; 0x30
800c650: f000 fce1 bl 800d016 <prvIsQueueFull>
800c654: 4603 mov r3, r0
800c656: 2b00 cmp r3, #0
800c658: d018 beq.n 800c68c <xQueueGenericSend+0x1e0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
800c65a: 6b3b ldr r3, [r7, #48] ; 0x30
800c65c: 3310 adds r3, #16
800c65e: 687a ldr r2, [r7, #4]
800c660: 4611 mov r1, r2
800c662: 4618 mov r0, r3
800c664: f001 fa44 bl 800daf0 <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
800c668: 6b38 ldr r0, [r7, #48] ; 0x30
800c66a: f000 fc6c bl 800cf46 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
800c66e: f001 f843 bl 800d6f8 <xTaskResumeAll>
800c672: 4603 mov r3, r0
800c674: 2b00 cmp r3, #0
800c676: f47f af7c bne.w 800c572 <xQueueGenericSend+0xc6>
{
portYIELD_WITHIN_API();
800c67a: 4b0c ldr r3, [pc, #48] ; (800c6ac <xQueueGenericSend+0x200>)
800c67c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c680: 601a str r2, [r3, #0]
800c682: f3bf 8f4f dsb sy
800c686: f3bf 8f6f isb sy
800c68a: e772 b.n 800c572 <xQueueGenericSend+0xc6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
800c68c: 6b38 ldr r0, [r7, #48] ; 0x30
800c68e: f000 fc5a bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c692: f001 f831 bl 800d6f8 <xTaskResumeAll>
800c696: e76c b.n 800c572 <xQueueGenericSend+0xc6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
800c698: 6b38 ldr r0, [r7, #48] ; 0x30
800c69a: f000 fc54 bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800c69e: f001 f82b bl 800d6f8 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800c6a2: 2300 movs r3, #0
}
} /*lint -restore */
}
800c6a4: 4618 mov r0, r3
800c6a6: 3738 adds r7, #56 ; 0x38
800c6a8: 46bd mov sp, r7
800c6aa: bd80 pop {r7, pc}
800c6ac: e000ed04 .word 0xe000ed04
0800c6b0 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
800c6b0: b580 push {r7, lr}
800c6b2: b08e sub sp, #56 ; 0x38
800c6b4: af00 add r7, sp, #0
800c6b6: 60f8 str r0, [r7, #12]
800c6b8: 60b9 str r1, [r7, #8]
800c6ba: 607a str r2, [r7, #4]
800c6bc: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c6be: 68fb ldr r3, [r7, #12]
800c6c0: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800c6c2: 6b3b ldr r3, [r7, #48] ; 0x30
800c6c4: 2b00 cmp r3, #0
800c6c6: d10b bne.n 800c6e0 <xQueueGenericSendFromISR+0x30>
800c6c8: f04f 0350 mov.w r3, #80 ; 0x50
800c6cc: b672 cpsid i
800c6ce: f383 8811 msr BASEPRI, r3
800c6d2: f3bf 8f6f isb sy
800c6d6: f3bf 8f4f dsb sy
800c6da: b662 cpsie i
800c6dc: 627b str r3, [r7, #36] ; 0x24
800c6de: e7fe b.n 800c6de <xQueueGenericSendFromISR+0x2e>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c6e0: 68bb ldr r3, [r7, #8]
800c6e2: 2b00 cmp r3, #0
800c6e4: d103 bne.n 800c6ee <xQueueGenericSendFromISR+0x3e>
800c6e6: 6b3b ldr r3, [r7, #48] ; 0x30
800c6e8: 6c1b ldr r3, [r3, #64] ; 0x40
800c6ea: 2b00 cmp r3, #0
800c6ec: d101 bne.n 800c6f2 <xQueueGenericSendFromISR+0x42>
800c6ee: 2301 movs r3, #1
800c6f0: e000 b.n 800c6f4 <xQueueGenericSendFromISR+0x44>
800c6f2: 2300 movs r3, #0
800c6f4: 2b00 cmp r3, #0
800c6f6: d10b bne.n 800c710 <xQueueGenericSendFromISR+0x60>
800c6f8: f04f 0350 mov.w r3, #80 ; 0x50
800c6fc: b672 cpsid i
800c6fe: f383 8811 msr BASEPRI, r3
800c702: f3bf 8f6f isb sy
800c706: f3bf 8f4f dsb sy
800c70a: b662 cpsie i
800c70c: 623b str r3, [r7, #32]
800c70e: e7fe b.n 800c70e <xQueueGenericSendFromISR+0x5e>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800c710: 683b ldr r3, [r7, #0]
800c712: 2b02 cmp r3, #2
800c714: d103 bne.n 800c71e <xQueueGenericSendFromISR+0x6e>
800c716: 6b3b ldr r3, [r7, #48] ; 0x30
800c718: 6bdb ldr r3, [r3, #60] ; 0x3c
800c71a: 2b01 cmp r3, #1
800c71c: d101 bne.n 800c722 <xQueueGenericSendFromISR+0x72>
800c71e: 2301 movs r3, #1
800c720: e000 b.n 800c724 <xQueueGenericSendFromISR+0x74>
800c722: 2300 movs r3, #0
800c724: 2b00 cmp r3, #0
800c726: d10b bne.n 800c740 <xQueueGenericSendFromISR+0x90>
800c728: f04f 0350 mov.w r3, #80 ; 0x50
800c72c: b672 cpsid i
800c72e: f383 8811 msr BASEPRI, r3
800c732: f3bf 8f6f isb sy
800c736: f3bf 8f4f dsb sy
800c73a: b662 cpsie i
800c73c: 61fb str r3, [r7, #28]
800c73e: e7fe b.n 800c73e <xQueueGenericSendFromISR+0x8e>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c740: f001 ffe2 bl 800e708 <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
800c744: f3ef 8211 mrs r2, BASEPRI
800c748: f04f 0350 mov.w r3, #80 ; 0x50
800c74c: b672 cpsid i
800c74e: f383 8811 msr BASEPRI, r3
800c752: f3bf 8f6f isb sy
800c756: f3bf 8f4f dsb sy
800c75a: b662 cpsie i
800c75c: 61ba str r2, [r7, #24]
800c75e: 617b str r3, [r7, #20]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
800c760: 69bb ldr r3, [r7, #24]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c762: 62fb str r3, [r7, #44] ; 0x2c
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800c764: 6b3b ldr r3, [r7, #48] ; 0x30
800c766: 6b9a ldr r2, [r3, #56] ; 0x38
800c768: 6b3b ldr r3, [r7, #48] ; 0x30
800c76a: 6bdb ldr r3, [r3, #60] ; 0x3c
800c76c: 429a cmp r2, r3
800c76e: d302 bcc.n 800c776 <xQueueGenericSendFromISR+0xc6>
800c770: 683b ldr r3, [r7, #0]
800c772: 2b02 cmp r3, #2
800c774: d12c bne.n 800c7d0 <xQueueGenericSendFromISR+0x120>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c776: 6b3b ldr r3, [r7, #48] ; 0x30
800c778: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c77c: f887 302b strb.w r3, [r7, #43] ; 0x2b
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800c780: 683a ldr r2, [r7, #0]
800c782: 68b9 ldr r1, [r7, #8]
800c784: 6b38 ldr r0, [r7, #48] ; 0x30
800c786: f000 fb4e bl 800ce26 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c78a: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b
800c78e: f1b3 3fff cmp.w r3, #4294967295
800c792: d112 bne.n 800c7ba <xQueueGenericSendFromISR+0x10a>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c794: 6b3b ldr r3, [r7, #48] ; 0x30
800c796: 6a5b ldr r3, [r3, #36] ; 0x24
800c798: 2b00 cmp r3, #0
800c79a: d016 beq.n 800c7ca <xQueueGenericSendFromISR+0x11a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c79c: 6b3b ldr r3, [r7, #48] ; 0x30
800c79e: 3324 adds r3, #36 ; 0x24
800c7a0: 4618 mov r0, r3
800c7a2: f001 f9cb bl 800db3c <xTaskRemoveFromEventList>
800c7a6: 4603 mov r3, r0
800c7a8: 2b00 cmp r3, #0
800c7aa: d00e beq.n 800c7ca <xQueueGenericSendFromISR+0x11a>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c7ac: 687b ldr r3, [r7, #4]
800c7ae: 2b00 cmp r3, #0
800c7b0: d00b beq.n 800c7ca <xQueueGenericSendFromISR+0x11a>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c7b2: 687b ldr r3, [r7, #4]
800c7b4: 2201 movs r2, #1
800c7b6: 601a str r2, [r3, #0]
800c7b8: e007 b.n 800c7ca <xQueueGenericSendFromISR+0x11a>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c7ba: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
800c7be: 3301 adds r3, #1
800c7c0: b2db uxtb r3, r3
800c7c2: b25a sxtb r2, r3
800c7c4: 6b3b ldr r3, [r7, #48] ; 0x30
800c7c6: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c7ca: 2301 movs r3, #1
800c7cc: 637b str r3, [r7, #52] ; 0x34
{
800c7ce: e001 b.n 800c7d4 <xQueueGenericSendFromISR+0x124>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c7d0: 2300 movs r3, #0
800c7d2: 637b str r3, [r7, #52] ; 0x34
800c7d4: 6afb ldr r3, [r7, #44] ; 0x2c
800c7d6: 613b str r3, [r7, #16]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
800c7d8: 693b ldr r3, [r7, #16]
800c7da: f383 8811 msr BASEPRI, r3
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c7de: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c7e0: 4618 mov r0, r3
800c7e2: 3738 adds r7, #56 ; 0x38
800c7e4: 46bd mov sp, r7
800c7e6: bd80 pop {r7, pc}
0800c7e8 <xQueueGiveFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
{
800c7e8: b580 push {r7, lr}
800c7ea: b08e sub sp, #56 ; 0x38
800c7ec: af00 add r7, sp, #0
800c7ee: 6078 str r0, [r7, #4]
800c7f0: 6039 str r1, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800c7f2: 687b ldr r3, [r7, #4]
800c7f4: 633b str r3, [r7, #48] ; 0x30
item size is 0. Don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
configASSERT( pxQueue );
800c7f6: 6b3b ldr r3, [r7, #48] ; 0x30
800c7f8: 2b00 cmp r3, #0
800c7fa: d10b bne.n 800c814 <xQueueGiveFromISR+0x2c>
__asm volatile
800c7fc: f04f 0350 mov.w r3, #80 ; 0x50
800c800: b672 cpsid i
800c802: f383 8811 msr BASEPRI, r3
800c806: f3bf 8f6f isb sy
800c80a: f3bf 8f4f dsb sy
800c80e: b662 cpsie i
800c810: 623b str r3, [r7, #32]
800c812: e7fe b.n 800c812 <xQueueGiveFromISR+0x2a>
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
if the item size is not 0. */
configASSERT( pxQueue->uxItemSize == 0 );
800c814: 6b3b ldr r3, [r7, #48] ; 0x30
800c816: 6c1b ldr r3, [r3, #64] ; 0x40
800c818: 2b00 cmp r3, #0
800c81a: d00b beq.n 800c834 <xQueueGiveFromISR+0x4c>
800c81c: f04f 0350 mov.w r3, #80 ; 0x50
800c820: b672 cpsid i
800c822: f383 8811 msr BASEPRI, r3
800c826: f3bf 8f6f isb sy
800c82a: f3bf 8f4f dsb sy
800c82e: b662 cpsie i
800c830: 61fb str r3, [r7, #28]
800c832: e7fe b.n 800c832 <xQueueGiveFromISR+0x4a>
/* Normally a mutex would not be given from an interrupt, especially if
there is a mutex holder, as priority inheritance makes no sense for an
interrupts, only tasks. */
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
800c834: 6b3b ldr r3, [r7, #48] ; 0x30
800c836: 681b ldr r3, [r3, #0]
800c838: 2b00 cmp r3, #0
800c83a: d103 bne.n 800c844 <xQueueGiveFromISR+0x5c>
800c83c: 6b3b ldr r3, [r7, #48] ; 0x30
800c83e: 689b ldr r3, [r3, #8]
800c840: 2b00 cmp r3, #0
800c842: d101 bne.n 800c848 <xQueueGiveFromISR+0x60>
800c844: 2301 movs r3, #1
800c846: e000 b.n 800c84a <xQueueGiveFromISR+0x62>
800c848: 2300 movs r3, #0
800c84a: 2b00 cmp r3, #0
800c84c: d10b bne.n 800c866 <xQueueGiveFromISR+0x7e>
800c84e: f04f 0350 mov.w r3, #80 ; 0x50
800c852: b672 cpsid i
800c854: f383 8811 msr BASEPRI, r3
800c858: f3bf 8f6f isb sy
800c85c: f3bf 8f4f dsb sy
800c860: b662 cpsie i
800c862: 61bb str r3, [r7, #24]
800c864: e7fe b.n 800c864 <xQueueGiveFromISR+0x7c>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800c866: f001 ff4f bl 800e708 <vPortValidateInterruptPriority>
__asm volatile
800c86a: f3ef 8211 mrs r2, BASEPRI
800c86e: f04f 0350 mov.w r3, #80 ; 0x50
800c872: b672 cpsid i
800c874: f383 8811 msr BASEPRI, r3
800c878: f3bf 8f6f isb sy
800c87c: f3bf 8f4f dsb sy
800c880: b662 cpsie i
800c882: 617a str r2, [r7, #20]
800c884: 613b str r3, [r7, #16]
return ulOriginalBASEPRI;
800c886: 697b ldr r3, [r7, #20]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800c888: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c88a: 6b3b ldr r3, [r7, #48] ; 0x30
800c88c: 6b9b ldr r3, [r3, #56] ; 0x38
800c88e: 62bb str r3, [r7, #40] ; 0x28
/* When the queue is used to implement a semaphore no data is ever
moved through the queue but it is still valid to see if the queue 'has
space'. */
if( uxMessagesWaiting < pxQueue->uxLength )
800c890: 6b3b ldr r3, [r7, #48] ; 0x30
800c892: 6bdb ldr r3, [r3, #60] ; 0x3c
800c894: 6aba ldr r2, [r7, #40] ; 0x28
800c896: 429a cmp r2, r3
800c898: d22b bcs.n 800c8f2 <xQueueGiveFromISR+0x10a>
{
const int8_t cTxLock = pxQueue->cTxLock;
800c89a: 6b3b ldr r3, [r7, #48] ; 0x30
800c89c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800c8a0: f887 3027 strb.w r3, [r7, #39] ; 0x27
holder - and if there is a mutex holder then the mutex cannot be
given from an ISR. As this is the ISR version of the function it
can be assumed there is no mutex holder and no need to determine if
priority disinheritance is needed. Simply increase the count of
messages (semaphores) available. */
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800c8a4: 6abb ldr r3, [r7, #40] ; 0x28
800c8a6: 1c5a adds r2, r3, #1
800c8a8: 6b3b ldr r3, [r7, #48] ; 0x30
800c8aa: 639a str r2, [r3, #56] ; 0x38
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
800c8ac: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800c8b0: f1b3 3fff cmp.w r3, #4294967295
800c8b4: d112 bne.n 800c8dc <xQueueGiveFromISR+0xf4>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800c8b6: 6b3b ldr r3, [r7, #48] ; 0x30
800c8b8: 6a5b ldr r3, [r3, #36] ; 0x24
800c8ba: 2b00 cmp r3, #0
800c8bc: d016 beq.n 800c8ec <xQueueGiveFromISR+0x104>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800c8be: 6b3b ldr r3, [r7, #48] ; 0x30
800c8c0: 3324 adds r3, #36 ; 0x24
800c8c2: 4618 mov r0, r3
800c8c4: f001 f93a bl 800db3c <xTaskRemoveFromEventList>
800c8c8: 4603 mov r3, r0
800c8ca: 2b00 cmp r3, #0
800c8cc: d00e beq.n 800c8ec <xQueueGiveFromISR+0x104>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800c8ce: 683b ldr r3, [r7, #0]
800c8d0: 2b00 cmp r3, #0
800c8d2: d00b beq.n 800c8ec <xQueueGiveFromISR+0x104>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800c8d4: 683b ldr r3, [r7, #0]
800c8d6: 2201 movs r2, #1
800c8d8: 601a str r2, [r3, #0]
800c8da: e007 b.n 800c8ec <xQueueGiveFromISR+0x104>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
800c8dc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800c8e0: 3301 adds r3, #1
800c8e2: b2db uxtb r3, r3
800c8e4: b25a sxtb r2, r3
800c8e6: 6b3b ldr r3, [r7, #48] ; 0x30
800c8e8: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
800c8ec: 2301 movs r3, #1
800c8ee: 637b str r3, [r7, #52] ; 0x34
800c8f0: e001 b.n 800c8f6 <xQueueGiveFromISR+0x10e>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800c8f2: 2300 movs r3, #0
800c8f4: 637b str r3, [r7, #52] ; 0x34
800c8f6: 6afb ldr r3, [r7, #44] ; 0x2c
800c8f8: 60fb str r3, [r7, #12]
__asm volatile
800c8fa: 68fb ldr r3, [r7, #12]
800c8fc: f383 8811 msr BASEPRI, r3
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800c900: 6b7b ldr r3, [r7, #52] ; 0x34
}
800c902: 4618 mov r0, r3
800c904: 3738 adds r7, #56 ; 0x38
800c906: 46bd mov sp, r7
800c908: bd80 pop {r7, pc}
...
0800c90c <xQueueReceive>:
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
800c90c: b580 push {r7, lr}
800c90e: b08c sub sp, #48 ; 0x30
800c910: af00 add r7, sp, #0
800c912: 60f8 str r0, [r7, #12]
800c914: 60b9 str r1, [r7, #8]
800c916: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
800c918: 2300 movs r3, #0
800c91a: 62fb str r3, [r7, #44] ; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800c91c: 68fb ldr r3, [r7, #12]
800c91e: 62bb str r3, [r7, #40] ; 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
800c920: 6abb ldr r3, [r7, #40] ; 0x28
800c922: 2b00 cmp r3, #0
800c924: d10b bne.n 800c93e <xQueueReceive+0x32>
__asm volatile
800c926: f04f 0350 mov.w r3, #80 ; 0x50
800c92a: b672 cpsid i
800c92c: f383 8811 msr BASEPRI, r3
800c930: f3bf 8f6f isb sy
800c934: f3bf 8f4f dsb sy
800c938: b662 cpsie i
800c93a: 623b str r3, [r7, #32]
800c93c: e7fe b.n 800c93c <xQueueReceive+0x30>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
800c93e: 68bb ldr r3, [r7, #8]
800c940: 2b00 cmp r3, #0
800c942: d103 bne.n 800c94c <xQueueReceive+0x40>
800c944: 6abb ldr r3, [r7, #40] ; 0x28
800c946: 6c1b ldr r3, [r3, #64] ; 0x40
800c948: 2b00 cmp r3, #0
800c94a: d101 bne.n 800c950 <xQueueReceive+0x44>
800c94c: 2301 movs r3, #1
800c94e: e000 b.n 800c952 <xQueueReceive+0x46>
800c950: 2300 movs r3, #0
800c952: 2b00 cmp r3, #0
800c954: d10b bne.n 800c96e <xQueueReceive+0x62>
800c956: f04f 0350 mov.w r3, #80 ; 0x50
800c95a: b672 cpsid i
800c95c: f383 8811 msr BASEPRI, r3
800c960: f3bf 8f6f isb sy
800c964: f3bf 8f4f dsb sy
800c968: b662 cpsie i
800c96a: 61fb str r3, [r7, #28]
800c96c: e7fe b.n 800c96c <xQueueReceive+0x60>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800c96e: f001 faa5 bl 800debc <xTaskGetSchedulerState>
800c972: 4603 mov r3, r0
800c974: 2b00 cmp r3, #0
800c976: d102 bne.n 800c97e <xQueueReceive+0x72>
800c978: 687b ldr r3, [r7, #4]
800c97a: 2b00 cmp r3, #0
800c97c: d101 bne.n 800c982 <xQueueReceive+0x76>
800c97e: 2301 movs r3, #1
800c980: e000 b.n 800c984 <xQueueReceive+0x78>
800c982: 2300 movs r3, #0
800c984: 2b00 cmp r3, #0
800c986: d10b bne.n 800c9a0 <xQueueReceive+0x94>
800c988: f04f 0350 mov.w r3, #80 ; 0x50
800c98c: b672 cpsid i
800c98e: f383 8811 msr BASEPRI, r3
800c992: f3bf 8f6f isb sy
800c996: f3bf 8f4f dsb sy
800c99a: b662 cpsie i
800c99c: 61bb str r3, [r7, #24]
800c99e: e7fe b.n 800c99e <xQueueReceive+0x92>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800c9a0: f001 fdd2 bl 800e548 <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800c9a4: 6abb ldr r3, [r7, #40] ; 0x28
800c9a6: 6b9b ldr r3, [r3, #56] ; 0x38
800c9a8: 627b str r3, [r7, #36] ; 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800c9aa: 6a7b ldr r3, [r7, #36] ; 0x24
800c9ac: 2b00 cmp r3, #0
800c9ae: d01f beq.n 800c9f0 <xQueueReceive+0xe4>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
800c9b0: 68b9 ldr r1, [r7, #8]
800c9b2: 6ab8 ldr r0, [r7, #40] ; 0x28
800c9b4: f000 faa1 bl 800cefa <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800c9b8: 6a7b ldr r3, [r7, #36] ; 0x24
800c9ba: 1e5a subs r2, r3, #1
800c9bc: 6abb ldr r3, [r7, #40] ; 0x28
800c9be: 639a str r2, [r3, #56] ; 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800c9c0: 6abb ldr r3, [r7, #40] ; 0x28
800c9c2: 691b ldr r3, [r3, #16]
800c9c4: 2b00 cmp r3, #0
800c9c6: d00f beq.n 800c9e8 <xQueueReceive+0xdc>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800c9c8: 6abb ldr r3, [r7, #40] ; 0x28
800c9ca: 3310 adds r3, #16
800c9cc: 4618 mov r0, r3
800c9ce: f001 f8b5 bl 800db3c <xTaskRemoveFromEventList>
800c9d2: 4603 mov r3, r0
800c9d4: 2b00 cmp r3, #0
800c9d6: d007 beq.n 800c9e8 <xQueueReceive+0xdc>
{
queueYIELD_IF_USING_PREEMPTION();
800c9d8: 4b3c ldr r3, [pc, #240] ; (800cacc <xQueueReceive+0x1c0>)
800c9da: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800c9de: 601a str r2, [r3, #0]
800c9e0: f3bf 8f4f dsb sy
800c9e4: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800c9e8: f001 fde0 bl 800e5ac <vPortExitCritical>
return pdPASS;
800c9ec: 2301 movs r3, #1
800c9ee: e069 b.n 800cac4 <xQueueReceive+0x1b8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800c9f0: 687b ldr r3, [r7, #4]
800c9f2: 2b00 cmp r3, #0
800c9f4: d103 bne.n 800c9fe <xQueueReceive+0xf2>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800c9f6: f001 fdd9 bl 800e5ac <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800c9fa: 2300 movs r3, #0
800c9fc: e062 b.n 800cac4 <xQueueReceive+0x1b8>
}
else if( xEntryTimeSet == pdFALSE )
800c9fe: 6afb ldr r3, [r7, #44] ; 0x2c
800ca00: 2b00 cmp r3, #0
800ca02: d106 bne.n 800ca12 <xQueueReceive+0x106>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800ca04: f107 0310 add.w r3, r7, #16
800ca08: 4618 mov r0, r3
800ca0a: f001 f8fb bl 800dc04 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800ca0e: 2301 movs r3, #1
800ca10: 62fb str r3, [r7, #44] ; 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800ca12: f001 fdcb bl 800e5ac <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800ca16: f000 fe61 bl 800d6dc <vTaskSuspendAll>
prvLockQueue( pxQueue );
800ca1a: f001 fd95 bl 800e548 <vPortEnterCritical>
800ca1e: 6abb ldr r3, [r7, #40] ; 0x28
800ca20: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800ca24: b25b sxtb r3, r3
800ca26: f1b3 3fff cmp.w r3, #4294967295
800ca2a: d103 bne.n 800ca34 <xQueueReceive+0x128>
800ca2c: 6abb ldr r3, [r7, #40] ; 0x28
800ca2e: 2200 movs r2, #0
800ca30: f883 2044 strb.w r2, [r3, #68] ; 0x44
800ca34: 6abb ldr r3, [r7, #40] ; 0x28
800ca36: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800ca3a: b25b sxtb r3, r3
800ca3c: f1b3 3fff cmp.w r3, #4294967295
800ca40: d103 bne.n 800ca4a <xQueueReceive+0x13e>
800ca42: 6abb ldr r3, [r7, #40] ; 0x28
800ca44: 2200 movs r2, #0
800ca46: f883 2045 strb.w r2, [r3, #69] ; 0x45
800ca4a: f001 fdaf bl 800e5ac <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800ca4e: 1d3a adds r2, r7, #4
800ca50: f107 0310 add.w r3, r7, #16
800ca54: 4611 mov r1, r2
800ca56: 4618 mov r0, r3
800ca58: f001 f8ea bl 800dc30 <xTaskCheckForTimeOut>
800ca5c: 4603 mov r3, r0
800ca5e: 2b00 cmp r3, #0
800ca60: d123 bne.n 800caaa <xQueueReceive+0x19e>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800ca62: 6ab8 ldr r0, [r7, #40] ; 0x28
800ca64: f000 fac1 bl 800cfea <prvIsQueueEmpty>
800ca68: 4603 mov r3, r0
800ca6a: 2b00 cmp r3, #0
800ca6c: d017 beq.n 800ca9e <xQueueReceive+0x192>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800ca6e: 6abb ldr r3, [r7, #40] ; 0x28
800ca70: 3324 adds r3, #36 ; 0x24
800ca72: 687a ldr r2, [r7, #4]
800ca74: 4611 mov r1, r2
800ca76: 4618 mov r0, r3
800ca78: f001 f83a bl 800daf0 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800ca7c: 6ab8 ldr r0, [r7, #40] ; 0x28
800ca7e: f000 fa62 bl 800cf46 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800ca82: f000 fe39 bl 800d6f8 <xTaskResumeAll>
800ca86: 4603 mov r3, r0
800ca88: 2b00 cmp r3, #0
800ca8a: d189 bne.n 800c9a0 <xQueueReceive+0x94>
{
portYIELD_WITHIN_API();
800ca8c: 4b0f ldr r3, [pc, #60] ; (800cacc <xQueueReceive+0x1c0>)
800ca8e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800ca92: 601a str r2, [r3, #0]
800ca94: f3bf 8f4f dsb sy
800ca98: f3bf 8f6f isb sy
800ca9c: e780 b.n 800c9a0 <xQueueReceive+0x94>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
800ca9e: 6ab8 ldr r0, [r7, #40] ; 0x28
800caa0: f000 fa51 bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800caa4: f000 fe28 bl 800d6f8 <xTaskResumeAll>
800caa8: e77a b.n 800c9a0 <xQueueReceive+0x94>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
800caaa: 6ab8 ldr r0, [r7, #40] ; 0x28
800caac: f000 fa4b bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800cab0: f000 fe22 bl 800d6f8 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cab4: 6ab8 ldr r0, [r7, #40] ; 0x28
800cab6: f000 fa98 bl 800cfea <prvIsQueueEmpty>
800caba: 4603 mov r3, r0
800cabc: 2b00 cmp r3, #0
800cabe: f43f af6f beq.w 800c9a0 <xQueueReceive+0x94>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cac2: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800cac4: 4618 mov r0, r3
800cac6: 3730 adds r7, #48 ; 0x30
800cac8: 46bd mov sp, r7
800caca: bd80 pop {r7, pc}
800cacc: e000ed04 .word 0xe000ed04
0800cad0 <xQueueSemaphoreTake>:
/*-----------------------------------------------------------*/
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
{
800cad0: b580 push {r7, lr}
800cad2: b08e sub sp, #56 ; 0x38
800cad4: af00 add r7, sp, #0
800cad6: 6078 str r0, [r7, #4]
800cad8: 6039 str r1, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE;
800cada: 2300 movs r3, #0
800cadc: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
800cade: 687b ldr r3, [r7, #4]
800cae0: 62fb str r3, [r7, #44] ; 0x2c
#if( configUSE_MUTEXES == 1 )
BaseType_t xInheritanceOccurred = pdFALSE;
800cae2: 2300 movs r3, #0
800cae4: 633b str r3, [r7, #48] ; 0x30
#endif
/* Check the queue pointer is not NULL. */
configASSERT( ( pxQueue ) );
800cae6: 6afb ldr r3, [r7, #44] ; 0x2c
800cae8: 2b00 cmp r3, #0
800caea: d10b bne.n 800cb04 <xQueueSemaphoreTake+0x34>
800caec: f04f 0350 mov.w r3, #80 ; 0x50
800caf0: b672 cpsid i
800caf2: f383 8811 msr BASEPRI, r3
800caf6: f3bf 8f6f isb sy
800cafa: f3bf 8f4f dsb sy
800cafe: b662 cpsie i
800cb00: 623b str r3, [r7, #32]
800cb02: e7fe b.n 800cb02 <xQueueSemaphoreTake+0x32>
/* Check this really is a semaphore, in which case the item size will be
0. */
configASSERT( pxQueue->uxItemSize == 0 );
800cb04: 6afb ldr r3, [r7, #44] ; 0x2c
800cb06: 6c1b ldr r3, [r3, #64] ; 0x40
800cb08: 2b00 cmp r3, #0
800cb0a: d00b beq.n 800cb24 <xQueueSemaphoreTake+0x54>
800cb0c: f04f 0350 mov.w r3, #80 ; 0x50
800cb10: b672 cpsid i
800cb12: f383 8811 msr BASEPRI, r3
800cb16: f3bf 8f6f isb sy
800cb1a: f3bf 8f4f dsb sy
800cb1e: b662 cpsie i
800cb20: 61fb str r3, [r7, #28]
800cb22: e7fe b.n 800cb22 <xQueueSemaphoreTake+0x52>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
800cb24: f001 f9ca bl 800debc <xTaskGetSchedulerState>
800cb28: 4603 mov r3, r0
800cb2a: 2b00 cmp r3, #0
800cb2c: d102 bne.n 800cb34 <xQueueSemaphoreTake+0x64>
800cb2e: 683b ldr r3, [r7, #0]
800cb30: 2b00 cmp r3, #0
800cb32: d101 bne.n 800cb38 <xQueueSemaphoreTake+0x68>
800cb34: 2301 movs r3, #1
800cb36: e000 b.n 800cb3a <xQueueSemaphoreTake+0x6a>
800cb38: 2300 movs r3, #0
800cb3a: 2b00 cmp r3, #0
800cb3c: d10b bne.n 800cb56 <xQueueSemaphoreTake+0x86>
800cb3e: f04f 0350 mov.w r3, #80 ; 0x50
800cb42: b672 cpsid i
800cb44: f383 8811 msr BASEPRI, r3
800cb48: f3bf 8f6f isb sy
800cb4c: f3bf 8f4f dsb sy
800cb50: b662 cpsie i
800cb52: 61bb str r3, [r7, #24]
800cb54: e7fe b.n 800cb54 <xQueueSemaphoreTake+0x84>
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
statements within the function itself. This is done in the interest
of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
800cb56: f001 fcf7 bl 800e548 <vPortEnterCritical>
{
/* Semaphores are queues with an item size of 0, and where the
number of messages in the queue is the semaphore's count value. */
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
800cb5a: 6afb ldr r3, [r7, #44] ; 0x2c
800cb5c: 6b9b ldr r3, [r3, #56] ; 0x38
800cb5e: 62bb str r3, [r7, #40] ; 0x28
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
800cb60: 6abb ldr r3, [r7, #40] ; 0x28
800cb62: 2b00 cmp r3, #0
800cb64: d024 beq.n 800cbb0 <xQueueSemaphoreTake+0xe0>
{
traceQUEUE_RECEIVE( pxQueue );
/* Semaphores are queues with a data size of zero and where the
messages waiting is the semaphore's count. Reduce the count. */
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
800cb66: 6abb ldr r3, [r7, #40] ; 0x28
800cb68: 1e5a subs r2, r3, #1
800cb6a: 6afb ldr r3, [r7, #44] ; 0x2c
800cb6c: 639a str r2, [r3, #56] ; 0x38
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cb6e: 6afb ldr r3, [r7, #44] ; 0x2c
800cb70: 681b ldr r3, [r3, #0]
800cb72: 2b00 cmp r3, #0
800cb74: d104 bne.n 800cb80 <xQueueSemaphoreTake+0xb0>
{
/* Record the information required to implement
priority inheritance should it become necessary. */
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
800cb76: f001 fb63 bl 800e240 <pvTaskIncrementMutexHeldCount>
800cb7a: 4602 mov r2, r0
800cb7c: 6afb ldr r3, [r7, #44] ; 0x2c
800cb7e: 609a str r2, [r3, #8]
}
#endif /* configUSE_MUTEXES */
/* Check to see if other tasks are blocked waiting to give the
semaphore, and if so, unblock the highest priority such task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cb80: 6afb ldr r3, [r7, #44] ; 0x2c
800cb82: 691b ldr r3, [r3, #16]
800cb84: 2b00 cmp r3, #0
800cb86: d00f beq.n 800cba8 <xQueueSemaphoreTake+0xd8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cb88: 6afb ldr r3, [r7, #44] ; 0x2c
800cb8a: 3310 adds r3, #16
800cb8c: 4618 mov r0, r3
800cb8e: f000 ffd5 bl 800db3c <xTaskRemoveFromEventList>
800cb92: 4603 mov r3, r0
800cb94: 2b00 cmp r3, #0
800cb96: d007 beq.n 800cba8 <xQueueSemaphoreTake+0xd8>
{
queueYIELD_IF_USING_PREEMPTION();
800cb98: 4b54 ldr r3, [pc, #336] ; (800ccec <xQueueSemaphoreTake+0x21c>)
800cb9a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cb9e: 601a str r2, [r3, #0]
800cba0: f3bf 8f4f dsb sy
800cba4: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800cba8: f001 fd00 bl 800e5ac <vPortExitCritical>
return pdPASS;
800cbac: 2301 movs r3, #1
800cbae: e098 b.n 800cce2 <xQueueSemaphoreTake+0x212>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800cbb0: 683b ldr r3, [r7, #0]
800cbb2: 2b00 cmp r3, #0
800cbb4: d112 bne.n 800cbdc <xQueueSemaphoreTake+0x10c>
/* For inheritance to have occurred there must have been an
initial timeout, and an adjusted timeout cannot become 0, as
if it were 0 the function would have exited. */
#if( configUSE_MUTEXES == 1 )
{
configASSERT( xInheritanceOccurred == pdFALSE );
800cbb6: 6b3b ldr r3, [r7, #48] ; 0x30
800cbb8: 2b00 cmp r3, #0
800cbba: d00b beq.n 800cbd4 <xQueueSemaphoreTake+0x104>
800cbbc: f04f 0350 mov.w r3, #80 ; 0x50
800cbc0: b672 cpsid i
800cbc2: f383 8811 msr BASEPRI, r3
800cbc6: f3bf 8f6f isb sy
800cbca: f3bf 8f4f dsb sy
800cbce: b662 cpsie i
800cbd0: 617b str r3, [r7, #20]
800cbd2: e7fe b.n 800cbd2 <xQueueSemaphoreTake+0x102>
}
#endif /* configUSE_MUTEXES */
/* The semaphore count was 0 and no block time is specified
(or the block time has expired) so exit now. */
taskEXIT_CRITICAL();
800cbd4: f001 fcea bl 800e5ac <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cbd8: 2300 movs r3, #0
800cbda: e082 b.n 800cce2 <xQueueSemaphoreTake+0x212>
}
else if( xEntryTimeSet == pdFALSE )
800cbdc: 6b7b ldr r3, [r7, #52] ; 0x34
800cbde: 2b00 cmp r3, #0
800cbe0: d106 bne.n 800cbf0 <xQueueSemaphoreTake+0x120>
{
/* The semaphore count was 0 and a block time was specified
so configure the timeout structure ready to block. */
vTaskInternalSetTimeOutState( &xTimeOut );
800cbe2: f107 030c add.w r3, r7, #12
800cbe6: 4618 mov r0, r3
800cbe8: f001 f80c bl 800dc04 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800cbec: 2301 movs r3, #1
800cbee: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800cbf0: f001 fcdc bl 800e5ac <vPortExitCritical>
/* Interrupts and other tasks can give to and take from the semaphore
now the critical section has been exited. */
vTaskSuspendAll();
800cbf4: f000 fd72 bl 800d6dc <vTaskSuspendAll>
prvLockQueue( pxQueue );
800cbf8: f001 fca6 bl 800e548 <vPortEnterCritical>
800cbfc: 6afb ldr r3, [r7, #44] ; 0x2c
800cbfe: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cc02: b25b sxtb r3, r3
800cc04: f1b3 3fff cmp.w r3, #4294967295
800cc08: d103 bne.n 800cc12 <xQueueSemaphoreTake+0x142>
800cc0a: 6afb ldr r3, [r7, #44] ; 0x2c
800cc0c: 2200 movs r2, #0
800cc0e: f883 2044 strb.w r2, [r3, #68] ; 0x44
800cc12: 6afb ldr r3, [r7, #44] ; 0x2c
800cc14: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800cc18: b25b sxtb r3, r3
800cc1a: f1b3 3fff cmp.w r3, #4294967295
800cc1e: d103 bne.n 800cc28 <xQueueSemaphoreTake+0x158>
800cc20: 6afb ldr r3, [r7, #44] ; 0x2c
800cc22: 2200 movs r2, #0
800cc24: f883 2045 strb.w r2, [r3, #69] ; 0x45
800cc28: f001 fcc0 bl 800e5ac <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800cc2c: 463a mov r2, r7
800cc2e: f107 030c add.w r3, r7, #12
800cc32: 4611 mov r1, r2
800cc34: 4618 mov r0, r3
800cc36: f000 fffb bl 800dc30 <xTaskCheckForTimeOut>
800cc3a: 4603 mov r3, r0
800cc3c: 2b00 cmp r3, #0
800cc3e: d132 bne.n 800cca6 <xQueueSemaphoreTake+0x1d6>
{
/* A block time is specified and not expired. If the semaphore
count is 0 then enter the Blocked state to wait for a semaphore to
become available. As semaphores are implemented with queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800cc40: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc42: f000 f9d2 bl 800cfea <prvIsQueueEmpty>
800cc46: 4603 mov r3, r0
800cc48: 2b00 cmp r3, #0
800cc4a: d026 beq.n 800cc9a <xQueueSemaphoreTake+0x1ca>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800cc4c: 6afb ldr r3, [r7, #44] ; 0x2c
800cc4e: 681b ldr r3, [r3, #0]
800cc50: 2b00 cmp r3, #0
800cc52: d109 bne.n 800cc68 <xQueueSemaphoreTake+0x198>
{
taskENTER_CRITICAL();
800cc54: f001 fc78 bl 800e548 <vPortEnterCritical>
{
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
800cc58: 6afb ldr r3, [r7, #44] ; 0x2c
800cc5a: 689b ldr r3, [r3, #8]
800cc5c: 4618 mov r0, r3
800cc5e: f001 f94b bl 800def8 <xTaskPriorityInherit>
800cc62: 6338 str r0, [r7, #48] ; 0x30
}
taskEXIT_CRITICAL();
800cc64: f001 fca2 bl 800e5ac <vPortExitCritical>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
800cc68: 6afb ldr r3, [r7, #44] ; 0x2c
800cc6a: 3324 adds r3, #36 ; 0x24
800cc6c: 683a ldr r2, [r7, #0]
800cc6e: 4611 mov r1, r2
800cc70: 4618 mov r0, r3
800cc72: f000 ff3d bl 800daf0 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
800cc76: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc78: f000 f965 bl 800cf46 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
800cc7c: f000 fd3c bl 800d6f8 <xTaskResumeAll>
800cc80: 4603 mov r3, r0
800cc82: 2b00 cmp r3, #0
800cc84: f47f af67 bne.w 800cb56 <xQueueSemaphoreTake+0x86>
{
portYIELD_WITHIN_API();
800cc88: 4b18 ldr r3, [pc, #96] ; (800ccec <xQueueSemaphoreTake+0x21c>)
800cc8a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800cc8e: 601a str r2, [r3, #0]
800cc90: f3bf 8f4f dsb sy
800cc94: f3bf 8f6f isb sy
800cc98: e75d b.n 800cb56 <xQueueSemaphoreTake+0x86>
}
else
{
/* There was no timeout and the semaphore count was not 0, so
attempt to take the semaphore again. */
prvUnlockQueue( pxQueue );
800cc9a: 6af8 ldr r0, [r7, #44] ; 0x2c
800cc9c: f000 f953 bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800cca0: f000 fd2a bl 800d6f8 <xTaskResumeAll>
800cca4: e757 b.n 800cb56 <xQueueSemaphoreTake+0x86>
}
}
else
{
/* Timed out. */
prvUnlockQueue( pxQueue );
800cca6: 6af8 ldr r0, [r7, #44] ; 0x2c
800cca8: f000 f94d bl 800cf46 <prvUnlockQueue>
( void ) xTaskResumeAll();
800ccac: f000 fd24 bl 800d6f8 <xTaskResumeAll>
/* If the semaphore count is 0 exit now as the timeout has
expired. Otherwise return to attempt to take the semaphore that is
known to be available. As semaphores are implemented by queues the
queue being empty is equivalent to the semaphore count being 0. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
800ccb0: 6af8 ldr r0, [r7, #44] ; 0x2c
800ccb2: f000 f99a bl 800cfea <prvIsQueueEmpty>
800ccb6: 4603 mov r3, r0
800ccb8: 2b00 cmp r3, #0
800ccba: f43f af4c beq.w 800cb56 <xQueueSemaphoreTake+0x86>
#if ( configUSE_MUTEXES == 1 )
{
/* xInheritanceOccurred could only have be set if
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
test the mutex type again to check it is actually a mutex. */
if( xInheritanceOccurred != pdFALSE )
800ccbe: 6b3b ldr r3, [r7, #48] ; 0x30
800ccc0: 2b00 cmp r3, #0
800ccc2: d00d beq.n 800cce0 <xQueueSemaphoreTake+0x210>
{
taskENTER_CRITICAL();
800ccc4: f001 fc40 bl 800e548 <vPortEnterCritical>
/* This task blocking on the mutex caused another
task to inherit this task's priority. Now this task
has timed out the priority should be disinherited
again, but only as low as the next highest priority
task that is waiting for the same mutex. */
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
800ccc8: 6af8 ldr r0, [r7, #44] ; 0x2c
800ccca: f000 f894 bl 800cdf6 <prvGetDisinheritPriorityAfterTimeout>
800ccce: 6278 str r0, [r7, #36] ; 0x24
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
800ccd0: 6afb ldr r3, [r7, #44] ; 0x2c
800ccd2: 689b ldr r3, [r3, #8]
800ccd4: 6a79 ldr r1, [r7, #36] ; 0x24
800ccd6: 4618 mov r0, r3
800ccd8: f001 fa16 bl 800e108 <vTaskPriorityDisinheritAfterTimeout>
}
taskEXIT_CRITICAL();
800ccdc: f001 fc66 bl 800e5ac <vPortExitCritical>
}
}
#endif /* configUSE_MUTEXES */
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800cce0: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
800cce2: 4618 mov r0, r3
800cce4: 3738 adds r7, #56 ; 0x38
800cce6: 46bd mov sp, r7
800cce8: bd80 pop {r7, pc}
800ccea: bf00 nop
800ccec: e000ed04 .word 0xe000ed04
0800ccf0 <xQueueReceiveFromISR>:
} /*lint -restore */
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
{
800ccf0: b580 push {r7, lr}
800ccf2: b08e sub sp, #56 ; 0x38
800ccf4: af00 add r7, sp, #0
800ccf6: 60f8 str r0, [r7, #12]
800ccf8: 60b9 str r1, [r7, #8]
800ccfa: 607a str r2, [r7, #4]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800ccfc: 68fb ldr r3, [r7, #12]
800ccfe: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
800cd00: 6b3b ldr r3, [r7, #48] ; 0x30
800cd02: 2b00 cmp r3, #0
800cd04: d10b bne.n 800cd1e <xQueueReceiveFromISR+0x2e>
800cd06: f04f 0350 mov.w r3, #80 ; 0x50
800cd0a: b672 cpsid i
800cd0c: f383 8811 msr BASEPRI, r3
800cd10: f3bf 8f6f isb sy
800cd14: f3bf 8f4f dsb sy
800cd18: b662 cpsie i
800cd1a: 623b str r3, [r7, #32]
800cd1c: e7fe b.n 800cd1c <xQueueReceiveFromISR+0x2c>
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800cd1e: 68bb ldr r3, [r7, #8]
800cd20: 2b00 cmp r3, #0
800cd22: d103 bne.n 800cd2c <xQueueReceiveFromISR+0x3c>
800cd24: 6b3b ldr r3, [r7, #48] ; 0x30
800cd26: 6c1b ldr r3, [r3, #64] ; 0x40
800cd28: 2b00 cmp r3, #0
800cd2a: d101 bne.n 800cd30 <xQueueReceiveFromISR+0x40>
800cd2c: 2301 movs r3, #1
800cd2e: e000 b.n 800cd32 <xQueueReceiveFromISR+0x42>
800cd30: 2300 movs r3, #0
800cd32: 2b00 cmp r3, #0
800cd34: d10b bne.n 800cd4e <xQueueReceiveFromISR+0x5e>
800cd36: f04f 0350 mov.w r3, #80 ; 0x50
800cd3a: b672 cpsid i
800cd3c: f383 8811 msr BASEPRI, r3
800cd40: f3bf 8f6f isb sy
800cd44: f3bf 8f4f dsb sy
800cd48: b662 cpsie i
800cd4a: 61fb str r3, [r7, #28]
800cd4c: e7fe b.n 800cd4c <xQueueReceiveFromISR+0x5c>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800cd4e: f001 fcdb bl 800e708 <vPortValidateInterruptPriority>
__asm volatile
800cd52: f3ef 8211 mrs r2, BASEPRI
800cd56: f04f 0350 mov.w r3, #80 ; 0x50
800cd5a: b672 cpsid i
800cd5c: f383 8811 msr BASEPRI, r3
800cd60: f3bf 8f6f isb sy
800cd64: f3bf 8f4f dsb sy
800cd68: b662 cpsie i
800cd6a: 61ba str r2, [r7, #24]
800cd6c: 617b str r3, [r7, #20]
return ulOriginalBASEPRI;
800cd6e: 69bb ldr r3, [r7, #24]
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800cd70: 62fb str r3, [r7, #44] ; 0x2c
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800cd72: 6b3b ldr r3, [r7, #48] ; 0x30
800cd74: 6b9b ldr r3, [r3, #56] ; 0x38
800cd76: 62bb str r3, [r7, #40] ; 0x28
/* Cannot block in an ISR, so check there is data available. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800cd78: 6abb ldr r3, [r7, #40] ; 0x28
800cd7a: 2b00 cmp r3, #0
800cd7c: d02f beq.n 800cdde <xQueueReceiveFromISR+0xee>
{
const int8_t cRxLock = pxQueue->cRxLock;
800cd7e: 6b3b ldr r3, [r7, #48] ; 0x30
800cd80: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cd84: f887 3027 strb.w r3, [r7, #39] ; 0x27
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
prvCopyDataFromQueue( pxQueue, pvBuffer );
800cd88: 68b9 ldr r1, [r7, #8]
800cd8a: 6b38 ldr r0, [r7, #48] ; 0x30
800cd8c: f000 f8b5 bl 800cefa <prvCopyDataFromQueue>
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800cd90: 6abb ldr r3, [r7, #40] ; 0x28
800cd92: 1e5a subs r2, r3, #1
800cd94: 6b3b ldr r3, [r7, #48] ; 0x30
800cd96: 639a str r2, [r3, #56] ; 0x38
/* If the queue is locked the event list will not be modified.
Instead update the lock count so the task that unlocks the queue
will know that an ISR has removed data while the queue was
locked. */
if( cRxLock == queueUNLOCKED )
800cd98: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
800cd9c: f1b3 3fff cmp.w r3, #4294967295
800cda0: d112 bne.n 800cdc8 <xQueueReceiveFromISR+0xd8>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cda2: 6b3b ldr r3, [r7, #48] ; 0x30
800cda4: 691b ldr r3, [r3, #16]
800cda6: 2b00 cmp r3, #0
800cda8: d016 beq.n 800cdd8 <xQueueReceiveFromISR+0xe8>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cdaa: 6b3b ldr r3, [r7, #48] ; 0x30
800cdac: 3310 adds r3, #16
800cdae: 4618 mov r0, r3
800cdb0: f000 fec4 bl 800db3c <xTaskRemoveFromEventList>
800cdb4: 4603 mov r3, r0
800cdb6: 2b00 cmp r3, #0
800cdb8: d00e beq.n 800cdd8 <xQueueReceiveFromISR+0xe8>
{
/* The task waiting has a higher priority than us so
force a context switch. */
if( pxHigherPriorityTaskWoken != NULL )
800cdba: 687b ldr r3, [r7, #4]
800cdbc: 2b00 cmp r3, #0
800cdbe: d00b beq.n 800cdd8 <xQueueReceiveFromISR+0xe8>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800cdc0: 687b ldr r3, [r7, #4]
800cdc2: 2201 movs r2, #1
800cdc4: 601a str r2, [r3, #0]
800cdc6: e007 b.n 800cdd8 <xQueueReceiveFromISR+0xe8>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was removed while it was locked. */
pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
800cdc8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
800cdcc: 3301 adds r3, #1
800cdce: b2db uxtb r3, r3
800cdd0: b25a sxtb r2, r3
800cdd2: 6b3b ldr r3, [r7, #48] ; 0x30
800cdd4: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
xReturn = pdPASS;
800cdd8: 2301 movs r3, #1
800cdda: 637b str r3, [r7, #52] ; 0x34
800cddc: e001 b.n 800cde2 <xQueueReceiveFromISR+0xf2>
}
else
{
xReturn = pdFAIL;
800cdde: 2300 movs r3, #0
800cde0: 637b str r3, [r7, #52] ; 0x34
800cde2: 6afb ldr r3, [r7, #44] ; 0x2c
800cde4: 613b str r3, [r7, #16]
__asm volatile
800cde6: 693b ldr r3, [r7, #16]
800cde8: f383 8811 msr BASEPRI, r3
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800cdec: 6b7b ldr r3, [r7, #52] ; 0x34
}
800cdee: 4618 mov r0, r3
800cdf0: 3738 adds r7, #56 ; 0x38
800cdf2: 46bd mov sp, r7
800cdf4: bd80 pop {r7, pc}
0800cdf6 <prvGetDisinheritPriorityAfterTimeout>:
/*-----------------------------------------------------------*/
#if( configUSE_MUTEXES == 1 )
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
{
800cdf6: b480 push {r7}
800cdf8: b085 sub sp, #20
800cdfa: af00 add r7, sp, #0
800cdfc: 6078 str r0, [r7, #4]
priority, but the waiting task times out, then the holder should
disinherit the priority - but only down to the highest priority of any
other tasks that are waiting for the same mutex. For this purpose,
return the priority of the highest priority task that is waiting for the
mutex. */
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
800cdfe: 687b ldr r3, [r7, #4]
800ce00: 6a5b ldr r3, [r3, #36] ; 0x24
800ce02: 2b00 cmp r3, #0
800ce04: d006 beq.n 800ce14 <prvGetDisinheritPriorityAfterTimeout+0x1e>
{
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
800ce06: 687b ldr r3, [r7, #4]
800ce08: 6b1b ldr r3, [r3, #48] ; 0x30
800ce0a: 681b ldr r3, [r3, #0]
800ce0c: f1c3 0307 rsb r3, r3, #7
800ce10: 60fb str r3, [r7, #12]
800ce12: e001 b.n 800ce18 <prvGetDisinheritPriorityAfterTimeout+0x22>
}
else
{
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
800ce14: 2300 movs r3, #0
800ce16: 60fb str r3, [r7, #12]
}
return uxHighestPriorityOfWaitingTasks;
800ce18: 68fb ldr r3, [r7, #12]
}
800ce1a: 4618 mov r0, r3
800ce1c: 3714 adds r7, #20
800ce1e: 46bd mov sp, r7
800ce20: f85d 7b04 ldr.w r7, [sp], #4
800ce24: 4770 bx lr
0800ce26 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
800ce26: b580 push {r7, lr}
800ce28: b086 sub sp, #24
800ce2a: af00 add r7, sp, #0
800ce2c: 60f8 str r0, [r7, #12]
800ce2e: 60b9 str r1, [r7, #8]
800ce30: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
800ce32: 2300 movs r3, #0
800ce34: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
800ce36: 68fb ldr r3, [r7, #12]
800ce38: 6b9b ldr r3, [r3, #56] ; 0x38
800ce3a: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800ce3c: 68fb ldr r3, [r7, #12]
800ce3e: 6c1b ldr r3, [r3, #64] ; 0x40
800ce40: 2b00 cmp r3, #0
800ce42: d10d bne.n 800ce60 <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
800ce44: 68fb ldr r3, [r7, #12]
800ce46: 681b ldr r3, [r3, #0]
800ce48: 2b00 cmp r3, #0
800ce4a: d14d bne.n 800cee8 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800ce4c: 68fb ldr r3, [r7, #12]
800ce4e: 689b ldr r3, [r3, #8]
800ce50: 4618 mov r0, r3
800ce52: f001 f8d1 bl 800dff8 <xTaskPriorityDisinherit>
800ce56: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
800ce58: 68fb ldr r3, [r7, #12]
800ce5a: 2200 movs r2, #0
800ce5c: 609a str r2, [r3, #8]
800ce5e: e043 b.n 800cee8 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
800ce60: 687b ldr r3, [r7, #4]
800ce62: 2b00 cmp r3, #0
800ce64: d119 bne.n 800ce9a <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800ce66: 68fb ldr r3, [r7, #12]
800ce68: 6858 ldr r0, [r3, #4]
800ce6a: 68fb ldr r3, [r7, #12]
800ce6c: 6c1b ldr r3, [r3, #64] ; 0x40
800ce6e: 461a mov r2, r3
800ce70: 68b9 ldr r1, [r7, #8]
800ce72: f00e f8c4 bl 801affe <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800ce76: 68fb ldr r3, [r7, #12]
800ce78: 685a ldr r2, [r3, #4]
800ce7a: 68fb ldr r3, [r7, #12]
800ce7c: 6c1b ldr r3, [r3, #64] ; 0x40
800ce7e: 441a add r2, r3
800ce80: 68fb ldr r3, [r7, #12]
800ce82: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800ce84: 68fb ldr r3, [r7, #12]
800ce86: 685a ldr r2, [r3, #4]
800ce88: 68fb ldr r3, [r7, #12]
800ce8a: 689b ldr r3, [r3, #8]
800ce8c: 429a cmp r2, r3
800ce8e: d32b bcc.n 800cee8 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
800ce90: 68fb ldr r3, [r7, #12]
800ce92: 681a ldr r2, [r3, #0]
800ce94: 68fb ldr r3, [r7, #12]
800ce96: 605a str r2, [r3, #4]
800ce98: e026 b.n 800cee8 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
800ce9a: 68fb ldr r3, [r7, #12]
800ce9c: 68d8 ldr r0, [r3, #12]
800ce9e: 68fb ldr r3, [r7, #12]
800cea0: 6c1b ldr r3, [r3, #64] ; 0x40
800cea2: 461a mov r2, r3
800cea4: 68b9 ldr r1, [r7, #8]
800cea6: f00e f8aa bl 801affe <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
800ceaa: 68fb ldr r3, [r7, #12]
800ceac: 68da ldr r2, [r3, #12]
800ceae: 68fb ldr r3, [r7, #12]
800ceb0: 6c1b ldr r3, [r3, #64] ; 0x40
800ceb2: 425b negs r3, r3
800ceb4: 441a add r2, r3
800ceb6: 68fb ldr r3, [r7, #12]
800ceb8: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800ceba: 68fb ldr r3, [r7, #12]
800cebc: 68da ldr r2, [r3, #12]
800cebe: 68fb ldr r3, [r7, #12]
800cec0: 681b ldr r3, [r3, #0]
800cec2: 429a cmp r2, r3
800cec4: d207 bcs.n 800ced6 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
800cec6: 68fb ldr r3, [r7, #12]
800cec8: 689a ldr r2, [r3, #8]
800ceca: 68fb ldr r3, [r7, #12]
800cecc: 6c1b ldr r3, [r3, #64] ; 0x40
800cece: 425b negs r3, r3
800ced0: 441a add r2, r3
800ced2: 68fb ldr r3, [r7, #12]
800ced4: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
800ced6: 687b ldr r3, [r7, #4]
800ced8: 2b02 cmp r3, #2
800ceda: d105 bne.n 800cee8 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
800cedc: 693b ldr r3, [r7, #16]
800cede: 2b00 cmp r3, #0
800cee0: d002 beq.n 800cee8 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
800cee2: 693b ldr r3, [r7, #16]
800cee4: 3b01 subs r3, #1
800cee6: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
800cee8: 693b ldr r3, [r7, #16]
800ceea: 1c5a adds r2, r3, #1
800ceec: 68fb ldr r3, [r7, #12]
800ceee: 639a str r2, [r3, #56] ; 0x38
return xReturn;
800cef0: 697b ldr r3, [r7, #20]
}
800cef2: 4618 mov r0, r3
800cef4: 3718 adds r7, #24
800cef6: 46bd mov sp, r7
800cef8: bd80 pop {r7, pc}
0800cefa <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
800cefa: b580 push {r7, lr}
800cefc: b082 sub sp, #8
800cefe: af00 add r7, sp, #0
800cf00: 6078 str r0, [r7, #4]
800cf02: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
800cf04: 687b ldr r3, [r7, #4]
800cf06: 6c1b ldr r3, [r3, #64] ; 0x40
800cf08: 2b00 cmp r3, #0
800cf0a: d018 beq.n 800cf3e <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800cf0c: 687b ldr r3, [r7, #4]
800cf0e: 68da ldr r2, [r3, #12]
800cf10: 687b ldr r3, [r7, #4]
800cf12: 6c1b ldr r3, [r3, #64] ; 0x40
800cf14: 441a add r2, r3
800cf16: 687b ldr r3, [r7, #4]
800cf18: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
800cf1a: 687b ldr r3, [r7, #4]
800cf1c: 68da ldr r2, [r3, #12]
800cf1e: 687b ldr r3, [r7, #4]
800cf20: 689b ldr r3, [r3, #8]
800cf22: 429a cmp r2, r3
800cf24: d303 bcc.n 800cf2e <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
800cf26: 687b ldr r3, [r7, #4]
800cf28: 681a ldr r2, [r3, #0]
800cf2a: 687b ldr r3, [r7, #4]
800cf2c: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800cf2e: 687b ldr r3, [r7, #4]
800cf30: 68d9 ldr r1, [r3, #12]
800cf32: 687b ldr r3, [r7, #4]
800cf34: 6c1b ldr r3, [r3, #64] ; 0x40
800cf36: 461a mov r2, r3
800cf38: 6838 ldr r0, [r7, #0]
800cf3a: f00e f860 bl 801affe <memcpy>
}
}
800cf3e: bf00 nop
800cf40: 3708 adds r7, #8
800cf42: 46bd mov sp, r7
800cf44: bd80 pop {r7, pc}
0800cf46 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
800cf46: b580 push {r7, lr}
800cf48: b084 sub sp, #16
800cf4a: af00 add r7, sp, #0
800cf4c: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
800cf4e: f001 fafb bl 800e548 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
800cf52: 687b ldr r3, [r7, #4]
800cf54: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800cf58: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
800cf5a: e011 b.n 800cf80 <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800cf5c: 687b ldr r3, [r7, #4]
800cf5e: 6a5b ldr r3, [r3, #36] ; 0x24
800cf60: 2b00 cmp r3, #0
800cf62: d012 beq.n 800cf8a <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800cf64: 687b ldr r3, [r7, #4]
800cf66: 3324 adds r3, #36 ; 0x24
800cf68: 4618 mov r0, r3
800cf6a: f000 fde7 bl 800db3c <xTaskRemoveFromEventList>
800cf6e: 4603 mov r3, r0
800cf70: 2b00 cmp r3, #0
800cf72: d001 beq.n 800cf78 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
800cf74: f000 fec0 bl 800dcf8 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
800cf78: 7bfb ldrb r3, [r7, #15]
800cf7a: 3b01 subs r3, #1
800cf7c: b2db uxtb r3, r3
800cf7e: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
800cf80: f997 300f ldrsb.w r3, [r7, #15]
800cf84: 2b00 cmp r3, #0
800cf86: dce9 bgt.n 800cf5c <prvUnlockQueue+0x16>
800cf88: e000 b.n 800cf8c <prvUnlockQueue+0x46>
break;
800cf8a: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800cf8c: 687b ldr r3, [r7, #4]
800cf8e: 22ff movs r2, #255 ; 0xff
800cf90: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
taskEXIT_CRITICAL();
800cf94: f001 fb0a bl 800e5ac <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
800cf98: f001 fad6 bl 800e548 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800cf9c: 687b ldr r3, [r7, #4]
800cf9e: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800cfa2: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cfa4: e011 b.n 800cfca <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
800cfa6: 687b ldr r3, [r7, #4]
800cfa8: 691b ldr r3, [r3, #16]
800cfaa: 2b00 cmp r3, #0
800cfac: d012 beq.n 800cfd4 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800cfae: 687b ldr r3, [r7, #4]
800cfb0: 3310 adds r3, #16
800cfb2: 4618 mov r0, r3
800cfb4: f000 fdc2 bl 800db3c <xTaskRemoveFromEventList>
800cfb8: 4603 mov r3, r0
800cfba: 2b00 cmp r3, #0
800cfbc: d001 beq.n 800cfc2 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
800cfbe: f000 fe9b bl 800dcf8 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
800cfc2: 7bbb ldrb r3, [r7, #14]
800cfc4: 3b01 subs r3, #1
800cfc6: b2db uxtb r3, r3
800cfc8: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800cfca: f997 300e ldrsb.w r3, [r7, #14]
800cfce: 2b00 cmp r3, #0
800cfd0: dce9 bgt.n 800cfa6 <prvUnlockQueue+0x60>
800cfd2: e000 b.n 800cfd6 <prvUnlockQueue+0x90>
}
else
{
break;
800cfd4: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
800cfd6: 687b ldr r3, [r7, #4]
800cfd8: 22ff movs r2, #255 ; 0xff
800cfda: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
taskEXIT_CRITICAL();
800cfde: f001 fae5 bl 800e5ac <vPortExitCritical>
}
800cfe2: bf00 nop
800cfe4: 3710 adds r7, #16
800cfe6: 46bd mov sp, r7
800cfe8: bd80 pop {r7, pc}
0800cfea <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
800cfea: b580 push {r7, lr}
800cfec: b084 sub sp, #16
800cfee: af00 add r7, sp, #0
800cff0: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800cff2: f001 faa9 bl 800e548 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
800cff6: 687b ldr r3, [r7, #4]
800cff8: 6b9b ldr r3, [r3, #56] ; 0x38
800cffa: 2b00 cmp r3, #0
800cffc: d102 bne.n 800d004 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
800cffe: 2301 movs r3, #1
800d000: 60fb str r3, [r7, #12]
800d002: e001 b.n 800d008 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
800d004: 2300 movs r3, #0
800d006: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800d008: f001 fad0 bl 800e5ac <vPortExitCritical>
return xReturn;
800d00c: 68fb ldr r3, [r7, #12]
}
800d00e: 4618 mov r0, r3
800d010: 3710 adds r7, #16
800d012: 46bd mov sp, r7
800d014: bd80 pop {r7, pc}
0800d016 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
800d016: b580 push {r7, lr}
800d018: b084 sub sp, #16
800d01a: af00 add r7, sp, #0
800d01c: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800d01e: f001 fa93 bl 800e548 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
800d022: 687b ldr r3, [r7, #4]
800d024: 6b9a ldr r2, [r3, #56] ; 0x38
800d026: 687b ldr r3, [r7, #4]
800d028: 6bdb ldr r3, [r3, #60] ; 0x3c
800d02a: 429a cmp r2, r3
800d02c: d102 bne.n 800d034 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
800d02e: 2301 movs r3, #1
800d030: 60fb str r3, [r7, #12]
800d032: e001 b.n 800d038 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
800d034: 2300 movs r3, #0
800d036: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800d038: f001 fab8 bl 800e5ac <vPortExitCritical>
return xReturn;
800d03c: 68fb ldr r3, [r7, #12]
}
800d03e: 4618 mov r0, r3
800d040: 3710 adds r7, #16
800d042: 46bd mov sp, r7
800d044: bd80 pop {r7, pc}
0800d046 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
800d046: b580 push {r7, lr}
800d048: b08e sub sp, #56 ; 0x38
800d04a: af04 add r7, sp, #16
800d04c: 60f8 str r0, [r7, #12]
800d04e: 60b9 str r1, [r7, #8]
800d050: 607a str r2, [r7, #4]
800d052: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800d054: 6b7b ldr r3, [r7, #52] ; 0x34
800d056: 2b00 cmp r3, #0
800d058: d10b bne.n 800d072 <xTaskCreateStatic+0x2c>
__asm volatile
800d05a: f04f 0350 mov.w r3, #80 ; 0x50
800d05e: b672 cpsid i
800d060: f383 8811 msr BASEPRI, r3
800d064: f3bf 8f6f isb sy
800d068: f3bf 8f4f dsb sy
800d06c: b662 cpsie i
800d06e: 623b str r3, [r7, #32]
800d070: e7fe b.n 800d070 <xTaskCreateStatic+0x2a>
configASSERT( pxTaskBuffer != NULL );
800d072: 6bbb ldr r3, [r7, #56] ; 0x38
800d074: 2b00 cmp r3, #0
800d076: d10b bne.n 800d090 <xTaskCreateStatic+0x4a>
800d078: f04f 0350 mov.w r3, #80 ; 0x50
800d07c: b672 cpsid i
800d07e: f383 8811 msr BASEPRI, r3
800d082: f3bf 8f6f isb sy
800d086: f3bf 8f4f dsb sy
800d08a: b662 cpsie i
800d08c: 61fb str r3, [r7, #28]
800d08e: e7fe b.n 800d08e <xTaskCreateStatic+0x48>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
800d090: 2358 movs r3, #88 ; 0x58
800d092: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800d094: 693b ldr r3, [r7, #16]
800d096: 2b58 cmp r3, #88 ; 0x58
800d098: d00b beq.n 800d0b2 <xTaskCreateStatic+0x6c>
800d09a: f04f 0350 mov.w r3, #80 ; 0x50
800d09e: b672 cpsid i
800d0a0: f383 8811 msr BASEPRI, r3
800d0a4: f3bf 8f6f isb sy
800d0a8: f3bf 8f4f dsb sy
800d0ac: b662 cpsie i
800d0ae: 61bb str r3, [r7, #24]
800d0b0: e7fe b.n 800d0b0 <xTaskCreateStatic+0x6a>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800d0b2: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800d0b4: 6bbb ldr r3, [r7, #56] ; 0x38
800d0b6: 2b00 cmp r3, #0
800d0b8: d01e beq.n 800d0f8 <xTaskCreateStatic+0xb2>
800d0ba: 6b7b ldr r3, [r7, #52] ; 0x34
800d0bc: 2b00 cmp r3, #0
800d0be: d01b beq.n 800d0f8 <xTaskCreateStatic+0xb2>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800d0c0: 6bbb ldr r3, [r7, #56] ; 0x38
800d0c2: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800d0c4: 6a7b ldr r3, [r7, #36] ; 0x24
800d0c6: 6b7a ldr r2, [r7, #52] ; 0x34
800d0c8: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
800d0ca: 6a7b ldr r3, [r7, #36] ; 0x24
800d0cc: 2202 movs r2, #2
800d0ce: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800d0d2: 2300 movs r3, #0
800d0d4: 9303 str r3, [sp, #12]
800d0d6: 6a7b ldr r3, [r7, #36] ; 0x24
800d0d8: 9302 str r3, [sp, #8]
800d0da: f107 0314 add.w r3, r7, #20
800d0de: 9301 str r3, [sp, #4]
800d0e0: 6b3b ldr r3, [r7, #48] ; 0x30
800d0e2: 9300 str r3, [sp, #0]
800d0e4: 683b ldr r3, [r7, #0]
800d0e6: 687a ldr r2, [r7, #4]
800d0e8: 68b9 ldr r1, [r7, #8]
800d0ea: 68f8 ldr r0, [r7, #12]
800d0ec: f000 f850 bl 800d190 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d0f0: 6a78 ldr r0, [r7, #36] ; 0x24
800d0f2: f000 f8e1 bl 800d2b8 <prvAddNewTaskToReadyList>
800d0f6: e001 b.n 800d0fc <xTaskCreateStatic+0xb6>
}
else
{
xReturn = NULL;
800d0f8: 2300 movs r3, #0
800d0fa: 617b str r3, [r7, #20]
}
return xReturn;
800d0fc: 697b ldr r3, [r7, #20]
}
800d0fe: 4618 mov r0, r3
800d100: 3728 adds r7, #40 ; 0x28
800d102: 46bd mov sp, r7
800d104: bd80 pop {r7, pc}
0800d106 <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
800d106: b580 push {r7, lr}
800d108: b08c sub sp, #48 ; 0x30
800d10a: af04 add r7, sp, #16
800d10c: 60f8 str r0, [r7, #12]
800d10e: 60b9 str r1, [r7, #8]
800d110: 603b str r3, [r7, #0]
800d112: 4613 mov r3, r2
800d114: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
800d116: 88fb ldrh r3, [r7, #6]
800d118: 009b lsls r3, r3, #2
800d11a: 4618 mov r0, r3
800d11c: f001 fb36 bl 800e78c <pvPortMalloc>
800d120: 6178 str r0, [r7, #20]
if( pxStack != NULL )
800d122: 697b ldr r3, [r7, #20]
800d124: 2b00 cmp r3, #0
800d126: d00e beq.n 800d146 <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
800d128: 2058 movs r0, #88 ; 0x58
800d12a: f001 fb2f bl 800e78c <pvPortMalloc>
800d12e: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
800d130: 69fb ldr r3, [r7, #28]
800d132: 2b00 cmp r3, #0
800d134: d003 beq.n 800d13e <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
800d136: 69fb ldr r3, [r7, #28]
800d138: 697a ldr r2, [r7, #20]
800d13a: 631a str r2, [r3, #48] ; 0x30
800d13c: e005 b.n 800d14a <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
800d13e: 6978 ldr r0, [r7, #20]
800d140: f001 fbf0 bl 800e924 <vPortFree>
800d144: e001 b.n 800d14a <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
800d146: 2300 movs r3, #0
800d148: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
800d14a: 69fb ldr r3, [r7, #28]
800d14c: 2b00 cmp r3, #0
800d14e: d017 beq.n 800d180 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
800d150: 69fb ldr r3, [r7, #28]
800d152: 2200 movs r2, #0
800d154: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
800d158: 88fa ldrh r2, [r7, #6]
800d15a: 2300 movs r3, #0
800d15c: 9303 str r3, [sp, #12]
800d15e: 69fb ldr r3, [r7, #28]
800d160: 9302 str r3, [sp, #8]
800d162: 6afb ldr r3, [r7, #44] ; 0x2c
800d164: 9301 str r3, [sp, #4]
800d166: 6abb ldr r3, [r7, #40] ; 0x28
800d168: 9300 str r3, [sp, #0]
800d16a: 683b ldr r3, [r7, #0]
800d16c: 68b9 ldr r1, [r7, #8]
800d16e: 68f8 ldr r0, [r7, #12]
800d170: f000 f80e bl 800d190 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800d174: 69f8 ldr r0, [r7, #28]
800d176: f000 f89f bl 800d2b8 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
800d17a: 2301 movs r3, #1
800d17c: 61bb str r3, [r7, #24]
800d17e: e002 b.n 800d186 <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
800d180: f04f 33ff mov.w r3, #4294967295
800d184: 61bb str r3, [r7, #24]
}
return xReturn;
800d186: 69bb ldr r3, [r7, #24]
}
800d188: 4618 mov r0, r3
800d18a: 3720 adds r7, #32
800d18c: 46bd mov sp, r7
800d18e: bd80 pop {r7, pc}
0800d190 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
800d190: b580 push {r7, lr}
800d192: b088 sub sp, #32
800d194: af00 add r7, sp, #0
800d196: 60f8 str r0, [r7, #12]
800d198: 60b9 str r1, [r7, #8]
800d19a: 607a str r2, [r7, #4]
800d19c: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
800d19e: 6b3b ldr r3, [r7, #48] ; 0x30
800d1a0: 6b18 ldr r0, [r3, #48] ; 0x30
800d1a2: 687b ldr r3, [r7, #4]
800d1a4: 009b lsls r3, r3, #2
800d1a6: 461a mov r2, r3
800d1a8: 21a5 movs r1, #165 ; 0xa5
800d1aa: f00d ff33 bl 801b014 <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
800d1ae: 6b3b ldr r3, [r7, #48] ; 0x30
800d1b0: 6b1a ldr r2, [r3, #48] ; 0x30
800d1b2: 6879 ldr r1, [r7, #4]
800d1b4: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000
800d1b8: 440b add r3, r1
800d1ba: 009b lsls r3, r3, #2
800d1bc: 4413 add r3, r2
800d1be: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
800d1c0: 69bb ldr r3, [r7, #24]
800d1c2: f023 0307 bic.w r3, r3, #7
800d1c6: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
800d1c8: 69bb ldr r3, [r7, #24]
800d1ca: f003 0307 and.w r3, r3, #7
800d1ce: 2b00 cmp r3, #0
800d1d0: d00b beq.n 800d1ea <prvInitialiseNewTask+0x5a>
800d1d2: f04f 0350 mov.w r3, #80 ; 0x50
800d1d6: b672 cpsid i
800d1d8: f383 8811 msr BASEPRI, r3
800d1dc: f3bf 8f6f isb sy
800d1e0: f3bf 8f4f dsb sy
800d1e4: b662 cpsie i
800d1e6: 617b str r3, [r7, #20]
800d1e8: e7fe b.n 800d1e8 <prvInitialiseNewTask+0x58>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
800d1ea: 68bb ldr r3, [r7, #8]
800d1ec: 2b00 cmp r3, #0
800d1ee: d01f beq.n 800d230 <prvInitialiseNewTask+0xa0>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d1f0: 2300 movs r3, #0
800d1f2: 61fb str r3, [r7, #28]
800d1f4: e012 b.n 800d21c <prvInitialiseNewTask+0x8c>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
800d1f6: 68ba ldr r2, [r7, #8]
800d1f8: 69fb ldr r3, [r7, #28]
800d1fa: 4413 add r3, r2
800d1fc: 7819 ldrb r1, [r3, #0]
800d1fe: 6b3a ldr r2, [r7, #48] ; 0x30
800d200: 69fb ldr r3, [r7, #28]
800d202: 4413 add r3, r2
800d204: 3334 adds r3, #52 ; 0x34
800d206: 460a mov r2, r1
800d208: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
800d20a: 68ba ldr r2, [r7, #8]
800d20c: 69fb ldr r3, [r7, #28]
800d20e: 4413 add r3, r2
800d210: 781b ldrb r3, [r3, #0]
800d212: 2b00 cmp r3, #0
800d214: d006 beq.n 800d224 <prvInitialiseNewTask+0x94>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800d216: 69fb ldr r3, [r7, #28]
800d218: 3301 adds r3, #1
800d21a: 61fb str r3, [r7, #28]
800d21c: 69fb ldr r3, [r7, #28]
800d21e: 2b0f cmp r3, #15
800d220: d9e9 bls.n 800d1f6 <prvInitialiseNewTask+0x66>
800d222: e000 b.n 800d226 <prvInitialiseNewTask+0x96>
{
break;
800d224: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
800d226: 6b3b ldr r3, [r7, #48] ; 0x30
800d228: 2200 movs r2, #0
800d22a: f883 2043 strb.w r2, [r3, #67] ; 0x43
800d22e: e003 b.n 800d238 <prvInitialiseNewTask+0xa8>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
800d230: 6b3b ldr r3, [r7, #48] ; 0x30
800d232: 2200 movs r2, #0
800d234: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
800d238: 6abb ldr r3, [r7, #40] ; 0x28
800d23a: 2b06 cmp r3, #6
800d23c: d901 bls.n 800d242 <prvInitialiseNewTask+0xb2>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
800d23e: 2306 movs r3, #6
800d240: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
800d242: 6b3b ldr r3, [r7, #48] ; 0x30
800d244: 6aba ldr r2, [r7, #40] ; 0x28
800d246: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
800d248: 6b3b ldr r3, [r7, #48] ; 0x30
800d24a: 6aba ldr r2, [r7, #40] ; 0x28
800d24c: 645a str r2, [r3, #68] ; 0x44
pxNewTCB->uxMutexesHeld = 0;
800d24e: 6b3b ldr r3, [r7, #48] ; 0x30
800d250: 2200 movs r2, #0
800d252: 649a str r2, [r3, #72] ; 0x48
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
800d254: 6b3b ldr r3, [r7, #48] ; 0x30
800d256: 3304 adds r3, #4
800d258: 4618 mov r0, r3
800d25a: f7fe fe91 bl 800bf80 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
800d25e: 6b3b ldr r3, [r7, #48] ; 0x30
800d260: 3318 adds r3, #24
800d262: 4618 mov r0, r3
800d264: f7fe fe8c bl 800bf80 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
800d268: 6b3b ldr r3, [r7, #48] ; 0x30
800d26a: 6b3a ldr r2, [r7, #48] ; 0x30
800d26c: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d26e: 6abb ldr r3, [r7, #40] ; 0x28
800d270: f1c3 0207 rsb r2, r3, #7
800d274: 6b3b ldr r3, [r7, #48] ; 0x30
800d276: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800d278: 6b3b ldr r3, [r7, #48] ; 0x30
800d27a: 6b3a ldr r2, [r7, #48] ; 0x30
800d27c: 625a str r2, [r3, #36] ; 0x24
}
#endif /* portCRITICAL_NESTING_IN_TCB */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
{
pxNewTCB->pxTaskTag = NULL;
800d27e: 6b3b ldr r3, [r7, #48] ; 0x30
800d280: 2200 movs r2, #0
800d282: 64da str r2, [r3, #76] ; 0x4c
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
800d284: 6b3b ldr r3, [r7, #48] ; 0x30
800d286: 2200 movs r2, #0
800d288: 651a str r2, [r3, #80] ; 0x50
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
800d28a: 6b3b ldr r3, [r7, #48] ; 0x30
800d28c: 2200 movs r2, #0
800d28e: f883 2054 strb.w r2, [r3, #84] ; 0x54
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
800d292: 683a ldr r2, [r7, #0]
800d294: 68f9 ldr r1, [r7, #12]
800d296: 69b8 ldr r0, [r7, #24]
800d298: f001 f84c bl 800e334 <pxPortInitialiseStack>
800d29c: 4602 mov r2, r0
800d29e: 6b3b ldr r3, [r7, #48] ; 0x30
800d2a0: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
800d2a2: 6afb ldr r3, [r7, #44] ; 0x2c
800d2a4: 2b00 cmp r3, #0
800d2a6: d002 beq.n 800d2ae <prvInitialiseNewTask+0x11e>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
800d2a8: 6afb ldr r3, [r7, #44] ; 0x2c
800d2aa: 6b3a ldr r2, [r7, #48] ; 0x30
800d2ac: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d2ae: bf00 nop
800d2b0: 3720 adds r7, #32
800d2b2: 46bd mov sp, r7
800d2b4: bd80 pop {r7, pc}
...
0800d2b8 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
800d2b8: b580 push {r7, lr}
800d2ba: b082 sub sp, #8
800d2bc: af00 add r7, sp, #0
800d2be: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
800d2c0: f001 f942 bl 800e548 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
800d2c4: 4b2a ldr r3, [pc, #168] ; (800d370 <prvAddNewTaskToReadyList+0xb8>)
800d2c6: 681b ldr r3, [r3, #0]
800d2c8: 3301 adds r3, #1
800d2ca: 4a29 ldr r2, [pc, #164] ; (800d370 <prvAddNewTaskToReadyList+0xb8>)
800d2cc: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
800d2ce: 4b29 ldr r3, [pc, #164] ; (800d374 <prvAddNewTaskToReadyList+0xbc>)
800d2d0: 681b ldr r3, [r3, #0]
800d2d2: 2b00 cmp r3, #0
800d2d4: d109 bne.n 800d2ea <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
800d2d6: 4a27 ldr r2, [pc, #156] ; (800d374 <prvAddNewTaskToReadyList+0xbc>)
800d2d8: 687b ldr r3, [r7, #4]
800d2da: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
800d2dc: 4b24 ldr r3, [pc, #144] ; (800d370 <prvAddNewTaskToReadyList+0xb8>)
800d2de: 681b ldr r3, [r3, #0]
800d2e0: 2b01 cmp r3, #1
800d2e2: d110 bne.n 800d306 <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
800d2e4: f000 fd2e bl 800dd44 <prvInitialiseTaskLists>
800d2e8: e00d b.n 800d306 <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
800d2ea: 4b23 ldr r3, [pc, #140] ; (800d378 <prvAddNewTaskToReadyList+0xc0>)
800d2ec: 681b ldr r3, [r3, #0]
800d2ee: 2b00 cmp r3, #0
800d2f0: d109 bne.n 800d306 <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
800d2f2: 4b20 ldr r3, [pc, #128] ; (800d374 <prvAddNewTaskToReadyList+0xbc>)
800d2f4: 681b ldr r3, [r3, #0]
800d2f6: 6ada ldr r2, [r3, #44] ; 0x2c
800d2f8: 687b ldr r3, [r7, #4]
800d2fa: 6adb ldr r3, [r3, #44] ; 0x2c
800d2fc: 429a cmp r2, r3
800d2fe: d802 bhi.n 800d306 <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
800d300: 4a1c ldr r2, [pc, #112] ; (800d374 <prvAddNewTaskToReadyList+0xbc>)
800d302: 687b ldr r3, [r7, #4]
800d304: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
800d306: 4b1d ldr r3, [pc, #116] ; (800d37c <prvAddNewTaskToReadyList+0xc4>)
800d308: 681b ldr r3, [r3, #0]
800d30a: 3301 adds r3, #1
800d30c: 4a1b ldr r2, [pc, #108] ; (800d37c <prvAddNewTaskToReadyList+0xc4>)
800d30e: 6013 str r3, [r2, #0]
pxNewTCB->uxTCBNumber = uxTaskNumber;
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
800d310: 687b ldr r3, [r7, #4]
800d312: 6adb ldr r3, [r3, #44] ; 0x2c
800d314: 2201 movs r2, #1
800d316: 409a lsls r2, r3
800d318: 4b19 ldr r3, [pc, #100] ; (800d380 <prvAddNewTaskToReadyList+0xc8>)
800d31a: 681b ldr r3, [r3, #0]
800d31c: 4313 orrs r3, r2
800d31e: 4a18 ldr r2, [pc, #96] ; (800d380 <prvAddNewTaskToReadyList+0xc8>)
800d320: 6013 str r3, [r2, #0]
800d322: 687b ldr r3, [r7, #4]
800d324: 6ada ldr r2, [r3, #44] ; 0x2c
800d326: 4613 mov r3, r2
800d328: 009b lsls r3, r3, #2
800d32a: 4413 add r3, r2
800d32c: 009b lsls r3, r3, #2
800d32e: 4a15 ldr r2, [pc, #84] ; (800d384 <prvAddNewTaskToReadyList+0xcc>)
800d330: 441a add r2, r3
800d332: 687b ldr r3, [r7, #4]
800d334: 3304 adds r3, #4
800d336: 4619 mov r1, r3
800d338: 4610 mov r0, r2
800d33a: f7fe fe2e bl 800bf9a <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
800d33e: f001 f935 bl 800e5ac <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
800d342: 4b0d ldr r3, [pc, #52] ; (800d378 <prvAddNewTaskToReadyList+0xc0>)
800d344: 681b ldr r3, [r3, #0]
800d346: 2b00 cmp r3, #0
800d348: d00e beq.n 800d368 <prvAddNewTaskToReadyList+0xb0>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
800d34a: 4b0a ldr r3, [pc, #40] ; (800d374 <prvAddNewTaskToReadyList+0xbc>)
800d34c: 681b ldr r3, [r3, #0]
800d34e: 6ada ldr r2, [r3, #44] ; 0x2c
800d350: 687b ldr r3, [r7, #4]
800d352: 6adb ldr r3, [r3, #44] ; 0x2c
800d354: 429a cmp r2, r3
800d356: d207 bcs.n 800d368 <prvAddNewTaskToReadyList+0xb0>
{
taskYIELD_IF_USING_PREEMPTION();
800d358: 4b0b ldr r3, [pc, #44] ; (800d388 <prvAddNewTaskToReadyList+0xd0>)
800d35a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d35e: 601a str r2, [r3, #0]
800d360: f3bf 8f4f dsb sy
800d364: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d368: bf00 nop
800d36a: 3708 adds r7, #8
800d36c: 46bd mov sp, r7
800d36e: bd80 pop {r7, pc}
800d370: 2000068c .word 0x2000068c
800d374: 2000058c .word 0x2000058c
800d378: 20000698 .word 0x20000698
800d37c: 200006a8 .word 0x200006a8
800d380: 20000694 .word 0x20000694
800d384: 20000590 .word 0x20000590
800d388: e000ed04 .word 0xe000ed04
0800d38c <vTaskDelete>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
void vTaskDelete( TaskHandle_t xTaskToDelete )
{
800d38c: b580 push {r7, lr}
800d38e: b084 sub sp, #16
800d390: af00 add r7, sp, #0
800d392: 6078 str r0, [r7, #4]
TCB_t *pxTCB;
taskENTER_CRITICAL();
800d394: f001 f8d8 bl 800e548 <vPortEnterCritical>
{
/* If null is passed in here then it is the calling task that is
being deleted. */
pxTCB = prvGetTCBFromHandle( xTaskToDelete );
800d398: 687b ldr r3, [r7, #4]
800d39a: 2b00 cmp r3, #0
800d39c: d102 bne.n 800d3a4 <vTaskDelete+0x18>
800d39e: 4b39 ldr r3, [pc, #228] ; (800d484 <vTaskDelete+0xf8>)
800d3a0: 681b ldr r3, [r3, #0]
800d3a2: e000 b.n 800d3a6 <vTaskDelete+0x1a>
800d3a4: 687b ldr r3, [r7, #4]
800d3a6: 60fb str r3, [r7, #12]
/* Remove task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800d3a8: 68fb ldr r3, [r7, #12]
800d3aa: 3304 adds r3, #4
800d3ac: 4618 mov r0, r3
800d3ae: f7fe fe51 bl 800c054 <uxListRemove>
800d3b2: 4603 mov r3, r0
800d3b4: 2b00 cmp r3, #0
800d3b6: d115 bne.n 800d3e4 <vTaskDelete+0x58>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800d3b8: 68fb ldr r3, [r7, #12]
800d3ba: 6ada ldr r2, [r3, #44] ; 0x2c
800d3bc: 4932 ldr r1, [pc, #200] ; (800d488 <vTaskDelete+0xfc>)
800d3be: 4613 mov r3, r2
800d3c0: 009b lsls r3, r3, #2
800d3c2: 4413 add r3, r2
800d3c4: 009b lsls r3, r3, #2
800d3c6: 440b add r3, r1
800d3c8: 681b ldr r3, [r3, #0]
800d3ca: 2b00 cmp r3, #0
800d3cc: d10a bne.n 800d3e4 <vTaskDelete+0x58>
800d3ce: 68fb ldr r3, [r7, #12]
800d3d0: 6adb ldr r3, [r3, #44] ; 0x2c
800d3d2: 2201 movs r2, #1
800d3d4: fa02 f303 lsl.w r3, r2, r3
800d3d8: 43da mvns r2, r3
800d3da: 4b2c ldr r3, [pc, #176] ; (800d48c <vTaskDelete+0x100>)
800d3dc: 681b ldr r3, [r3, #0]
800d3de: 4013 ands r3, r2
800d3e0: 4a2a ldr r2, [pc, #168] ; (800d48c <vTaskDelete+0x100>)
800d3e2: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Is the task waiting on an event also? */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d3e4: 68fb ldr r3, [r7, #12]
800d3e6: 6a9b ldr r3, [r3, #40] ; 0x28
800d3e8: 2b00 cmp r3, #0
800d3ea: d004 beq.n 800d3f6 <vTaskDelete+0x6a>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d3ec: 68fb ldr r3, [r7, #12]
800d3ee: 3318 adds r3, #24
800d3f0: 4618 mov r0, r3
800d3f2: f7fe fe2f bl 800c054 <uxListRemove>
/* Increment the uxTaskNumber also so kernel aware debuggers can
detect that the task lists need re-generating. This is done before
portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
not return. */
uxTaskNumber++;
800d3f6: 4b26 ldr r3, [pc, #152] ; (800d490 <vTaskDelete+0x104>)
800d3f8: 681b ldr r3, [r3, #0]
800d3fa: 3301 adds r3, #1
800d3fc: 4a24 ldr r2, [pc, #144] ; (800d490 <vTaskDelete+0x104>)
800d3fe: 6013 str r3, [r2, #0]
if( pxTCB == pxCurrentTCB )
800d400: 4b20 ldr r3, [pc, #128] ; (800d484 <vTaskDelete+0xf8>)
800d402: 681b ldr r3, [r3, #0]
800d404: 68fa ldr r2, [r7, #12]
800d406: 429a cmp r2, r3
800d408: d10b bne.n 800d422 <vTaskDelete+0x96>
/* A task is deleting itself. This cannot complete within the
task itself, as a context switch to another task is required.
Place the task in the termination list. The idle task will
check the termination list and free up any memory allocated by
the scheduler for the TCB and stack of the deleted task. */
vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
800d40a: 68fb ldr r3, [r7, #12]
800d40c: 3304 adds r3, #4
800d40e: 4619 mov r1, r3
800d410: 4820 ldr r0, [pc, #128] ; (800d494 <vTaskDelete+0x108>)
800d412: f7fe fdc2 bl 800bf9a <vListInsertEnd>
/* Increment the ucTasksDeleted variable so the idle task knows
there is a task that has been deleted and that it should therefore
check the xTasksWaitingTermination list. */
++uxDeletedTasksWaitingCleanUp;
800d416: 4b20 ldr r3, [pc, #128] ; (800d498 <vTaskDelete+0x10c>)
800d418: 681b ldr r3, [r3, #0]
800d41a: 3301 adds r3, #1
800d41c: 4a1e ldr r2, [pc, #120] ; (800d498 <vTaskDelete+0x10c>)
800d41e: 6013 str r3, [r2, #0]
800d420: e009 b.n 800d436 <vTaskDelete+0xaa>
required. */
portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
}
else
{
--uxCurrentNumberOfTasks;
800d422: 4b1e ldr r3, [pc, #120] ; (800d49c <vTaskDelete+0x110>)
800d424: 681b ldr r3, [r3, #0]
800d426: 3b01 subs r3, #1
800d428: 4a1c ldr r2, [pc, #112] ; (800d49c <vTaskDelete+0x110>)
800d42a: 6013 str r3, [r2, #0]
prvDeleteTCB( pxTCB );
800d42c: 68f8 ldr r0, [r7, #12]
800d42e: f000 fcf5 bl 800de1c <prvDeleteTCB>
/* Reset the next expected unblock time in case it referred to
the task that has just been deleted. */
prvResetNextTaskUnblockTime();
800d432: f000 fd23 bl 800de7c <prvResetNextTaskUnblockTime>
}
traceTASK_DELETE( pxTCB );
}
taskEXIT_CRITICAL();
800d436: f001 f8b9 bl 800e5ac <vPortExitCritical>
/* Force a reschedule if it is the currently running task that has just
been deleted. */
if( xSchedulerRunning != pdFALSE )
800d43a: 4b19 ldr r3, [pc, #100] ; (800d4a0 <vTaskDelete+0x114>)
800d43c: 681b ldr r3, [r3, #0]
800d43e: 2b00 cmp r3, #0
800d440: d01c beq.n 800d47c <vTaskDelete+0xf0>
{
if( pxTCB == pxCurrentTCB )
800d442: 4b10 ldr r3, [pc, #64] ; (800d484 <vTaskDelete+0xf8>)
800d444: 681b ldr r3, [r3, #0]
800d446: 68fa ldr r2, [r7, #12]
800d448: 429a cmp r2, r3
800d44a: d117 bne.n 800d47c <vTaskDelete+0xf0>
{
configASSERT( uxSchedulerSuspended == 0 );
800d44c: 4b15 ldr r3, [pc, #84] ; (800d4a4 <vTaskDelete+0x118>)
800d44e: 681b ldr r3, [r3, #0]
800d450: 2b00 cmp r3, #0
800d452: d00b beq.n 800d46c <vTaskDelete+0xe0>
800d454: f04f 0350 mov.w r3, #80 ; 0x50
800d458: b672 cpsid i
800d45a: f383 8811 msr BASEPRI, r3
800d45e: f3bf 8f6f isb sy
800d462: f3bf 8f4f dsb sy
800d466: b662 cpsie i
800d468: 60bb str r3, [r7, #8]
800d46a: e7fe b.n 800d46a <vTaskDelete+0xde>
portYIELD_WITHIN_API();
800d46c: 4b0e ldr r3, [pc, #56] ; (800d4a8 <vTaskDelete+0x11c>)
800d46e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d472: 601a str r2, [r3, #0]
800d474: f3bf 8f4f dsb sy
800d478: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800d47c: bf00 nop
800d47e: 3710 adds r7, #16
800d480: 46bd mov sp, r7
800d482: bd80 pop {r7, pc}
800d484: 2000058c .word 0x2000058c
800d488: 20000590 .word 0x20000590
800d48c: 20000694 .word 0x20000694
800d490: 200006a8 .word 0x200006a8
800d494: 20000660 .word 0x20000660
800d498: 20000674 .word 0x20000674
800d49c: 2000068c .word 0x2000068c
800d4a0: 20000698 .word 0x20000698
800d4a4: 200006b4 .word 0x200006b4
800d4a8: e000ed04 .word 0xe000ed04
0800d4ac <vTaskDelayUntil>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelayUntil == 1 )
void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
{
800d4ac: b580 push {r7, lr}
800d4ae: b08a sub sp, #40 ; 0x28
800d4b0: af00 add r7, sp, #0
800d4b2: 6078 str r0, [r7, #4]
800d4b4: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
800d4b6: 2300 movs r3, #0
800d4b8: 627b str r3, [r7, #36] ; 0x24
configASSERT( pxPreviousWakeTime );
800d4ba: 687b ldr r3, [r7, #4]
800d4bc: 2b00 cmp r3, #0
800d4be: d10b bne.n 800d4d8 <vTaskDelayUntil+0x2c>
800d4c0: f04f 0350 mov.w r3, #80 ; 0x50
800d4c4: b672 cpsid i
800d4c6: f383 8811 msr BASEPRI, r3
800d4ca: f3bf 8f6f isb sy
800d4ce: f3bf 8f4f dsb sy
800d4d2: b662 cpsie i
800d4d4: 617b str r3, [r7, #20]
800d4d6: e7fe b.n 800d4d6 <vTaskDelayUntil+0x2a>
configASSERT( ( xTimeIncrement > 0U ) );
800d4d8: 683b ldr r3, [r7, #0]
800d4da: 2b00 cmp r3, #0
800d4dc: d10b bne.n 800d4f6 <vTaskDelayUntil+0x4a>
800d4de: f04f 0350 mov.w r3, #80 ; 0x50
800d4e2: b672 cpsid i
800d4e4: f383 8811 msr BASEPRI, r3
800d4e8: f3bf 8f6f isb sy
800d4ec: f3bf 8f4f dsb sy
800d4f0: b662 cpsie i
800d4f2: 613b str r3, [r7, #16]
800d4f4: e7fe b.n 800d4f4 <vTaskDelayUntil+0x48>
configASSERT( uxSchedulerSuspended == 0 );
800d4f6: 4b2a ldr r3, [pc, #168] ; (800d5a0 <vTaskDelayUntil+0xf4>)
800d4f8: 681b ldr r3, [r3, #0]
800d4fa: 2b00 cmp r3, #0
800d4fc: d00b beq.n 800d516 <vTaskDelayUntil+0x6a>
800d4fe: f04f 0350 mov.w r3, #80 ; 0x50
800d502: b672 cpsid i
800d504: f383 8811 msr BASEPRI, r3
800d508: f3bf 8f6f isb sy
800d50c: f3bf 8f4f dsb sy
800d510: b662 cpsie i
800d512: 60fb str r3, [r7, #12]
800d514: e7fe b.n 800d514 <vTaskDelayUntil+0x68>
vTaskSuspendAll();
800d516: f000 f8e1 bl 800d6dc <vTaskSuspendAll>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount;
800d51a: 4b22 ldr r3, [pc, #136] ; (800d5a4 <vTaskDelayUntil+0xf8>)
800d51c: 681b ldr r3, [r3, #0]
800d51e: 623b str r3, [r7, #32]
/* Generate the tick time at which the task wants to wake. */
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
800d520: 687b ldr r3, [r7, #4]
800d522: 681b ldr r3, [r3, #0]
800d524: 683a ldr r2, [r7, #0]
800d526: 4413 add r3, r2
800d528: 61fb str r3, [r7, #28]
if( xConstTickCount < *pxPreviousWakeTime )
800d52a: 687b ldr r3, [r7, #4]
800d52c: 681b ldr r3, [r3, #0]
800d52e: 6a3a ldr r2, [r7, #32]
800d530: 429a cmp r2, r3
800d532: d20b bcs.n 800d54c <vTaskDelayUntil+0xa0>
/* The tick count has overflowed since this function was
lasted called. In this case the only time we should ever
actually delay is if the wake time has also overflowed,
and the wake time is greater than the tick time. When this
is the case it is as if neither time had overflowed. */
if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
800d534: 687b ldr r3, [r7, #4]
800d536: 681b ldr r3, [r3, #0]
800d538: 69fa ldr r2, [r7, #28]
800d53a: 429a cmp r2, r3
800d53c: d211 bcs.n 800d562 <vTaskDelayUntil+0xb6>
800d53e: 69fa ldr r2, [r7, #28]
800d540: 6a3b ldr r3, [r7, #32]
800d542: 429a cmp r2, r3
800d544: d90d bls.n 800d562 <vTaskDelayUntil+0xb6>
{
xShouldDelay = pdTRUE;
800d546: 2301 movs r3, #1
800d548: 627b str r3, [r7, #36] ; 0x24
800d54a: e00a b.n 800d562 <vTaskDelayUntil+0xb6>
else
{
/* The tick time has not overflowed. In this case we will
delay if either the wake time has overflowed, and/or the
tick time is less than the wake time. */
if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
800d54c: 687b ldr r3, [r7, #4]
800d54e: 681b ldr r3, [r3, #0]
800d550: 69fa ldr r2, [r7, #28]
800d552: 429a cmp r2, r3
800d554: d303 bcc.n 800d55e <vTaskDelayUntil+0xb2>
800d556: 69fa ldr r2, [r7, #28]
800d558: 6a3b ldr r3, [r7, #32]
800d55a: 429a cmp r2, r3
800d55c: d901 bls.n 800d562 <vTaskDelayUntil+0xb6>
{
xShouldDelay = pdTRUE;
800d55e: 2301 movs r3, #1
800d560: 627b str r3, [r7, #36] ; 0x24
mtCOVERAGE_TEST_MARKER();
}
}
/* Update the wake time ready for the next call. */
*pxPreviousWakeTime = xTimeToWake;
800d562: 687b ldr r3, [r7, #4]
800d564: 69fa ldr r2, [r7, #28]
800d566: 601a str r2, [r3, #0]
if( xShouldDelay != pdFALSE )
800d568: 6a7b ldr r3, [r7, #36] ; 0x24
800d56a: 2b00 cmp r3, #0
800d56c: d006 beq.n 800d57c <vTaskDelayUntil+0xd0>
{
traceTASK_DELAY_UNTIL( xTimeToWake );
/* prvAddCurrentTaskToDelayedList() needs the block time, not
the time to wake, so subtract the current tick count. */
prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
800d56e: 69fa ldr r2, [r7, #28]
800d570: 6a3b ldr r3, [r7, #32]
800d572: 1ad3 subs r3, r2, r3
800d574: 2100 movs r1, #0
800d576: 4618 mov r0, r3
800d578: f000 fe76 bl 800e268 <prvAddCurrentTaskToDelayedList>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
xAlreadyYielded = xTaskResumeAll();
800d57c: f000 f8bc bl 800d6f8 <xTaskResumeAll>
800d580: 61b8 str r0, [r7, #24]
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d582: 69bb ldr r3, [r7, #24]
800d584: 2b00 cmp r3, #0
800d586: d107 bne.n 800d598 <vTaskDelayUntil+0xec>
{
portYIELD_WITHIN_API();
800d588: 4b07 ldr r3, [pc, #28] ; (800d5a8 <vTaskDelayUntil+0xfc>)
800d58a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d58e: 601a str r2, [r3, #0]
800d590: f3bf 8f4f dsb sy
800d594: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d598: bf00 nop
800d59a: 3728 adds r7, #40 ; 0x28
800d59c: 46bd mov sp, r7
800d59e: bd80 pop {r7, pc}
800d5a0: 200006b4 .word 0x200006b4
800d5a4: 20000690 .word 0x20000690
800d5a8: e000ed04 .word 0xe000ed04
0800d5ac <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
800d5ac: b580 push {r7, lr}
800d5ae: b084 sub sp, #16
800d5b0: af00 add r7, sp, #0
800d5b2: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
800d5b4: 2300 movs r3, #0
800d5b6: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
800d5b8: 687b ldr r3, [r7, #4]
800d5ba: 2b00 cmp r3, #0
800d5bc: d018 beq.n 800d5f0 <vTaskDelay+0x44>
{
configASSERT( uxSchedulerSuspended == 0 );
800d5be: 4b14 ldr r3, [pc, #80] ; (800d610 <vTaskDelay+0x64>)
800d5c0: 681b ldr r3, [r3, #0]
800d5c2: 2b00 cmp r3, #0
800d5c4: d00b beq.n 800d5de <vTaskDelay+0x32>
800d5c6: f04f 0350 mov.w r3, #80 ; 0x50
800d5ca: b672 cpsid i
800d5cc: f383 8811 msr BASEPRI, r3
800d5d0: f3bf 8f6f isb sy
800d5d4: f3bf 8f4f dsb sy
800d5d8: b662 cpsie i
800d5da: 60bb str r3, [r7, #8]
800d5dc: e7fe b.n 800d5dc <vTaskDelay+0x30>
vTaskSuspendAll();
800d5de: f000 f87d bl 800d6dc <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
800d5e2: 2100 movs r1, #0
800d5e4: 6878 ldr r0, [r7, #4]
800d5e6: f000 fe3f bl 800e268 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
800d5ea: f000 f885 bl 800d6f8 <xTaskResumeAll>
800d5ee: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800d5f0: 68fb ldr r3, [r7, #12]
800d5f2: 2b00 cmp r3, #0
800d5f4: d107 bne.n 800d606 <vTaskDelay+0x5a>
{
portYIELD_WITHIN_API();
800d5f6: 4b07 ldr r3, [pc, #28] ; (800d614 <vTaskDelay+0x68>)
800d5f8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d5fc: 601a str r2, [r3, #0]
800d5fe: f3bf 8f4f dsb sy
800d602: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800d606: bf00 nop
800d608: 3710 adds r7, #16
800d60a: 46bd mov sp, r7
800d60c: bd80 pop {r7, pc}
800d60e: bf00 nop
800d610: 200006b4 .word 0x200006b4
800d614: e000ed04 .word 0xe000ed04
0800d618 <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
800d618: b580 push {r7, lr}
800d61a: b08a sub sp, #40 ; 0x28
800d61c: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
800d61e: 2300 movs r3, #0
800d620: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
800d622: 2300 movs r3, #0
800d624: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
800d626: 463a mov r2, r7
800d628: 1d39 adds r1, r7, #4
800d62a: f107 0308 add.w r3, r7, #8
800d62e: 4618 mov r0, r3
800d630: f7f2 ffd8 bl 80005e4 <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
800d634: 6839 ldr r1, [r7, #0]
800d636: 687b ldr r3, [r7, #4]
800d638: 68ba ldr r2, [r7, #8]
800d63a: 9202 str r2, [sp, #8]
800d63c: 9301 str r3, [sp, #4]
800d63e: 2300 movs r3, #0
800d640: 9300 str r3, [sp, #0]
800d642: 2300 movs r3, #0
800d644: 460a mov r2, r1
800d646: 491f ldr r1, [pc, #124] ; (800d6c4 <vTaskStartScheduler+0xac>)
800d648: 481f ldr r0, [pc, #124] ; (800d6c8 <vTaskStartScheduler+0xb0>)
800d64a: f7ff fcfc bl 800d046 <xTaskCreateStatic>
800d64e: 4602 mov r2, r0
800d650: 4b1e ldr r3, [pc, #120] ; (800d6cc <vTaskStartScheduler+0xb4>)
800d652: 601a str r2, [r3, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
800d654: 4b1d ldr r3, [pc, #116] ; (800d6cc <vTaskStartScheduler+0xb4>)
800d656: 681b ldr r3, [r3, #0]
800d658: 2b00 cmp r3, #0
800d65a: d002 beq.n 800d662 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
800d65c: 2301 movs r3, #1
800d65e: 617b str r3, [r7, #20]
800d660: e001 b.n 800d666 <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
800d662: 2300 movs r3, #0
800d664: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
800d666: 697b ldr r3, [r7, #20]
800d668: 2b01 cmp r3, #1
800d66a: d117 bne.n 800d69c <vTaskStartScheduler+0x84>
800d66c: f04f 0350 mov.w r3, #80 ; 0x50
800d670: b672 cpsid i
800d672: f383 8811 msr BASEPRI, r3
800d676: f3bf 8f6f isb sy
800d67a: f3bf 8f4f dsb sy
800d67e: b662 cpsie i
800d680: 613b str r3, [r7, #16]
structure specific to the task that will run first. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
800d682: 4b13 ldr r3, [pc, #76] ; (800d6d0 <vTaskStartScheduler+0xb8>)
800d684: f04f 32ff mov.w r2, #4294967295
800d688: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
800d68a: 4b12 ldr r3, [pc, #72] ; (800d6d4 <vTaskStartScheduler+0xbc>)
800d68c: 2201 movs r2, #1
800d68e: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
800d690: 4b11 ldr r3, [pc, #68] ; (800d6d8 <vTaskStartScheduler+0xc0>)
800d692: 2200 movs r2, #0
800d694: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
800d696: f000 fedb bl 800e450 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
800d69a: e00f b.n 800d6bc <vTaskStartScheduler+0xa4>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
800d69c: 697b ldr r3, [r7, #20]
800d69e: f1b3 3fff cmp.w r3, #4294967295
800d6a2: d10b bne.n 800d6bc <vTaskStartScheduler+0xa4>
800d6a4: f04f 0350 mov.w r3, #80 ; 0x50
800d6a8: b672 cpsid i
800d6aa: f383 8811 msr BASEPRI, r3
800d6ae: f3bf 8f6f isb sy
800d6b2: f3bf 8f4f dsb sy
800d6b6: b662 cpsie i
800d6b8: 60fb str r3, [r7, #12]
800d6ba: e7fe b.n 800d6ba <vTaskStartScheduler+0xa2>
}
800d6bc: bf00 nop
800d6be: 3718 adds r7, #24
800d6c0: 46bd mov sp, r7
800d6c2: bd80 pop {r7, pc}
800d6c4: 0801bfdc .word 0x0801bfdc
800d6c8: 0800dd11 .word 0x0800dd11
800d6cc: 200006b0 .word 0x200006b0
800d6d0: 200006ac .word 0x200006ac
800d6d4: 20000698 .word 0x20000698
800d6d8: 20000690 .word 0x20000690
0800d6dc <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
800d6dc: b480 push {r7}
800d6de: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
800d6e0: 4b04 ldr r3, [pc, #16] ; (800d6f4 <vTaskSuspendAll+0x18>)
800d6e2: 681b ldr r3, [r3, #0]
800d6e4: 3301 adds r3, #1
800d6e6: 4a03 ldr r2, [pc, #12] ; (800d6f4 <vTaskSuspendAll+0x18>)
800d6e8: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
800d6ea: bf00 nop
800d6ec: 46bd mov sp, r7
800d6ee: f85d 7b04 ldr.w r7, [sp], #4
800d6f2: 4770 bx lr
800d6f4: 200006b4 .word 0x200006b4
0800d6f8 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
800d6f8: b580 push {r7, lr}
800d6fa: b084 sub sp, #16
800d6fc: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
800d6fe: 2300 movs r3, #0
800d700: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
800d702: 2300 movs r3, #0
800d704: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
800d706: 4b42 ldr r3, [pc, #264] ; (800d810 <xTaskResumeAll+0x118>)
800d708: 681b ldr r3, [r3, #0]
800d70a: 2b00 cmp r3, #0
800d70c: d10b bne.n 800d726 <xTaskResumeAll+0x2e>
800d70e: f04f 0350 mov.w r3, #80 ; 0x50
800d712: b672 cpsid i
800d714: f383 8811 msr BASEPRI, r3
800d718: f3bf 8f6f isb sy
800d71c: f3bf 8f4f dsb sy
800d720: b662 cpsie i
800d722: 603b str r3, [r7, #0]
800d724: e7fe b.n 800d724 <xTaskResumeAll+0x2c>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
800d726: f000 ff0f bl 800e548 <vPortEnterCritical>
{
--uxSchedulerSuspended;
800d72a: 4b39 ldr r3, [pc, #228] ; (800d810 <xTaskResumeAll+0x118>)
800d72c: 681b ldr r3, [r3, #0]
800d72e: 3b01 subs r3, #1
800d730: 4a37 ldr r2, [pc, #220] ; (800d810 <xTaskResumeAll+0x118>)
800d732: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d734: 4b36 ldr r3, [pc, #216] ; (800d810 <xTaskResumeAll+0x118>)
800d736: 681b ldr r3, [r3, #0]
800d738: 2b00 cmp r3, #0
800d73a: d161 bne.n 800d800 <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
800d73c: 4b35 ldr r3, [pc, #212] ; (800d814 <xTaskResumeAll+0x11c>)
800d73e: 681b ldr r3, [r3, #0]
800d740: 2b00 cmp r3, #0
800d742: d05d beq.n 800d800 <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d744: e02e b.n 800d7a4 <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d746: 4b34 ldr r3, [pc, #208] ; (800d818 <xTaskResumeAll+0x120>)
800d748: 68db ldr r3, [r3, #12]
800d74a: 68db ldr r3, [r3, #12]
800d74c: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d74e: 68fb ldr r3, [r7, #12]
800d750: 3318 adds r3, #24
800d752: 4618 mov r0, r3
800d754: f7fe fc7e bl 800c054 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d758: 68fb ldr r3, [r7, #12]
800d75a: 3304 adds r3, #4
800d75c: 4618 mov r0, r3
800d75e: f7fe fc79 bl 800c054 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
800d762: 68fb ldr r3, [r7, #12]
800d764: 6adb ldr r3, [r3, #44] ; 0x2c
800d766: 2201 movs r2, #1
800d768: 409a lsls r2, r3
800d76a: 4b2c ldr r3, [pc, #176] ; (800d81c <xTaskResumeAll+0x124>)
800d76c: 681b ldr r3, [r3, #0]
800d76e: 4313 orrs r3, r2
800d770: 4a2a ldr r2, [pc, #168] ; (800d81c <xTaskResumeAll+0x124>)
800d772: 6013 str r3, [r2, #0]
800d774: 68fb ldr r3, [r7, #12]
800d776: 6ada ldr r2, [r3, #44] ; 0x2c
800d778: 4613 mov r3, r2
800d77a: 009b lsls r3, r3, #2
800d77c: 4413 add r3, r2
800d77e: 009b lsls r3, r3, #2
800d780: 4a27 ldr r2, [pc, #156] ; (800d820 <xTaskResumeAll+0x128>)
800d782: 441a add r2, r3
800d784: 68fb ldr r3, [r7, #12]
800d786: 3304 adds r3, #4
800d788: 4619 mov r1, r3
800d78a: 4610 mov r0, r2
800d78c: f7fe fc05 bl 800bf9a <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d790: 68fb ldr r3, [r7, #12]
800d792: 6ada ldr r2, [r3, #44] ; 0x2c
800d794: 4b23 ldr r3, [pc, #140] ; (800d824 <xTaskResumeAll+0x12c>)
800d796: 681b ldr r3, [r3, #0]
800d798: 6adb ldr r3, [r3, #44] ; 0x2c
800d79a: 429a cmp r2, r3
800d79c: d302 bcc.n 800d7a4 <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
800d79e: 4b22 ldr r3, [pc, #136] ; (800d828 <xTaskResumeAll+0x130>)
800d7a0: 2201 movs r2, #1
800d7a2: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800d7a4: 4b1c ldr r3, [pc, #112] ; (800d818 <xTaskResumeAll+0x120>)
800d7a6: 681b ldr r3, [r3, #0]
800d7a8: 2b00 cmp r3, #0
800d7aa: d1cc bne.n 800d746 <xTaskResumeAll+0x4e>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
800d7ac: 68fb ldr r3, [r7, #12]
800d7ae: 2b00 cmp r3, #0
800d7b0: d001 beq.n 800d7b6 <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
800d7b2: f000 fb63 bl 800de7c <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
800d7b6: 4b1d ldr r3, [pc, #116] ; (800d82c <xTaskResumeAll+0x134>)
800d7b8: 681b ldr r3, [r3, #0]
800d7ba: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
800d7bc: 687b ldr r3, [r7, #4]
800d7be: 2b00 cmp r3, #0
800d7c0: d010 beq.n 800d7e4 <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
800d7c2: f000 f859 bl 800d878 <xTaskIncrementTick>
800d7c6: 4603 mov r3, r0
800d7c8: 2b00 cmp r3, #0
800d7ca: d002 beq.n 800d7d2 <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
800d7cc: 4b16 ldr r3, [pc, #88] ; (800d828 <xTaskResumeAll+0x130>)
800d7ce: 2201 movs r2, #1
800d7d0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
800d7d2: 687b ldr r3, [r7, #4]
800d7d4: 3b01 subs r3, #1
800d7d6: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
800d7d8: 687b ldr r3, [r7, #4]
800d7da: 2b00 cmp r3, #0
800d7dc: d1f1 bne.n 800d7c2 <xTaskResumeAll+0xca>
uxPendedTicks = 0;
800d7de: 4b13 ldr r3, [pc, #76] ; (800d82c <xTaskResumeAll+0x134>)
800d7e0: 2200 movs r2, #0
800d7e2: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
800d7e4: 4b10 ldr r3, [pc, #64] ; (800d828 <xTaskResumeAll+0x130>)
800d7e6: 681b ldr r3, [r3, #0]
800d7e8: 2b00 cmp r3, #0
800d7ea: d009 beq.n 800d800 <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
800d7ec: 2301 movs r3, #1
800d7ee: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
800d7f0: 4b0f ldr r3, [pc, #60] ; (800d830 <xTaskResumeAll+0x138>)
800d7f2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800d7f6: 601a str r2, [r3, #0]
800d7f8: f3bf 8f4f dsb sy
800d7fc: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
800d800: f000 fed4 bl 800e5ac <vPortExitCritical>
return xAlreadyYielded;
800d804: 68bb ldr r3, [r7, #8]
}
800d806: 4618 mov r0, r3
800d808: 3710 adds r7, #16
800d80a: 46bd mov sp, r7
800d80c: bd80 pop {r7, pc}
800d80e: bf00 nop
800d810: 200006b4 .word 0x200006b4
800d814: 2000068c .word 0x2000068c
800d818: 2000064c .word 0x2000064c
800d81c: 20000694 .word 0x20000694
800d820: 20000590 .word 0x20000590
800d824: 2000058c .word 0x2000058c
800d828: 200006a0 .word 0x200006a0
800d82c: 2000069c .word 0x2000069c
800d830: e000ed04 .word 0xe000ed04
0800d834 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
800d834: b480 push {r7}
800d836: b083 sub sp, #12
800d838: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
800d83a: 4b05 ldr r3, [pc, #20] ; (800d850 <xTaskGetTickCount+0x1c>)
800d83c: 681b ldr r3, [r3, #0]
800d83e: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
800d840: 687b ldr r3, [r7, #4]
}
800d842: 4618 mov r0, r3
800d844: 370c adds r7, #12
800d846: 46bd mov sp, r7
800d848: f85d 7b04 ldr.w r7, [sp], #4
800d84c: 4770 bx lr
800d84e: bf00 nop
800d850: 20000690 .word 0x20000690
0800d854 <xTaskGetTickCountFromISR>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCountFromISR( void )
{
800d854: b580 push {r7, lr}
800d856: b082 sub sp, #8
800d858: af00 add r7, sp, #0
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800d85a: f000 ff55 bl 800e708 <vPortValidateInterruptPriority>
uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
800d85e: 2300 movs r3, #0
800d860: 607b str r3, [r7, #4]
{
xReturn = xTickCount;
800d862: 4b04 ldr r3, [pc, #16] ; (800d874 <xTaskGetTickCountFromISR+0x20>)
800d864: 681b ldr r3, [r3, #0]
800d866: 603b str r3, [r7, #0]
}
portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800d868: 683b ldr r3, [r7, #0]
}
800d86a: 4618 mov r0, r3
800d86c: 3708 adds r7, #8
800d86e: 46bd mov sp, r7
800d870: bd80 pop {r7, pc}
800d872: bf00 nop
800d874: 20000690 .word 0x20000690
0800d878 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
800d878: b580 push {r7, lr}
800d87a: b086 sub sp, #24
800d87c: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
800d87e: 2300 movs r3, #0
800d880: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800d882: 4b4f ldr r3, [pc, #316] ; (800d9c0 <xTaskIncrementTick+0x148>)
800d884: 681b ldr r3, [r3, #0]
800d886: 2b00 cmp r3, #0
800d888: f040 8089 bne.w 800d99e <xTaskIncrementTick+0x126>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
800d88c: 4b4d ldr r3, [pc, #308] ; (800d9c4 <xTaskIncrementTick+0x14c>)
800d88e: 681b ldr r3, [r3, #0]
800d890: 3301 adds r3, #1
800d892: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
800d894: 4a4b ldr r2, [pc, #300] ; (800d9c4 <xTaskIncrementTick+0x14c>)
800d896: 693b ldr r3, [r7, #16]
800d898: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
800d89a: 693b ldr r3, [r7, #16]
800d89c: 2b00 cmp r3, #0
800d89e: d121 bne.n 800d8e4 <xTaskIncrementTick+0x6c>
{
taskSWITCH_DELAYED_LISTS();
800d8a0: 4b49 ldr r3, [pc, #292] ; (800d9c8 <xTaskIncrementTick+0x150>)
800d8a2: 681b ldr r3, [r3, #0]
800d8a4: 681b ldr r3, [r3, #0]
800d8a6: 2b00 cmp r3, #0
800d8a8: d00b beq.n 800d8c2 <xTaskIncrementTick+0x4a>
800d8aa: f04f 0350 mov.w r3, #80 ; 0x50
800d8ae: b672 cpsid i
800d8b0: f383 8811 msr BASEPRI, r3
800d8b4: f3bf 8f6f isb sy
800d8b8: f3bf 8f4f dsb sy
800d8bc: b662 cpsie i
800d8be: 603b str r3, [r7, #0]
800d8c0: e7fe b.n 800d8c0 <xTaskIncrementTick+0x48>
800d8c2: 4b41 ldr r3, [pc, #260] ; (800d9c8 <xTaskIncrementTick+0x150>)
800d8c4: 681b ldr r3, [r3, #0]
800d8c6: 60fb str r3, [r7, #12]
800d8c8: 4b40 ldr r3, [pc, #256] ; (800d9cc <xTaskIncrementTick+0x154>)
800d8ca: 681b ldr r3, [r3, #0]
800d8cc: 4a3e ldr r2, [pc, #248] ; (800d9c8 <xTaskIncrementTick+0x150>)
800d8ce: 6013 str r3, [r2, #0]
800d8d0: 4a3e ldr r2, [pc, #248] ; (800d9cc <xTaskIncrementTick+0x154>)
800d8d2: 68fb ldr r3, [r7, #12]
800d8d4: 6013 str r3, [r2, #0]
800d8d6: 4b3e ldr r3, [pc, #248] ; (800d9d0 <xTaskIncrementTick+0x158>)
800d8d8: 681b ldr r3, [r3, #0]
800d8da: 3301 adds r3, #1
800d8dc: 4a3c ldr r2, [pc, #240] ; (800d9d0 <xTaskIncrementTick+0x158>)
800d8de: 6013 str r3, [r2, #0]
800d8e0: f000 facc bl 800de7c <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
800d8e4: 4b3b ldr r3, [pc, #236] ; (800d9d4 <xTaskIncrementTick+0x15c>)
800d8e6: 681b ldr r3, [r3, #0]
800d8e8: 693a ldr r2, [r7, #16]
800d8ea: 429a cmp r2, r3
800d8ec: d348 bcc.n 800d980 <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d8ee: 4b36 ldr r3, [pc, #216] ; (800d9c8 <xTaskIncrementTick+0x150>)
800d8f0: 681b ldr r3, [r3, #0]
800d8f2: 681b ldr r3, [r3, #0]
800d8f4: 2b00 cmp r3, #0
800d8f6: d104 bne.n 800d902 <xTaskIncrementTick+0x8a>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800d8f8: 4b36 ldr r3, [pc, #216] ; (800d9d4 <xTaskIncrementTick+0x15c>)
800d8fa: f04f 32ff mov.w r2, #4294967295
800d8fe: 601a str r2, [r3, #0]
break;
800d900: e03e b.n 800d980 <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800d902: 4b31 ldr r3, [pc, #196] ; (800d9c8 <xTaskIncrementTick+0x150>)
800d904: 681b ldr r3, [r3, #0]
800d906: 68db ldr r3, [r3, #12]
800d908: 68db ldr r3, [r3, #12]
800d90a: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
800d90c: 68bb ldr r3, [r7, #8]
800d90e: 685b ldr r3, [r3, #4]
800d910: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800d912: 693a ldr r2, [r7, #16]
800d914: 687b ldr r3, [r7, #4]
800d916: 429a cmp r2, r3
800d918: d203 bcs.n 800d922 <xTaskIncrementTick+0xaa>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
800d91a: 4a2e ldr r2, [pc, #184] ; (800d9d4 <xTaskIncrementTick+0x15c>)
800d91c: 687b ldr r3, [r7, #4]
800d91e: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
800d920: e02e b.n 800d980 <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800d922: 68bb ldr r3, [r7, #8]
800d924: 3304 adds r3, #4
800d926: 4618 mov r0, r3
800d928: f7fe fb94 bl 800c054 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800d92c: 68bb ldr r3, [r7, #8]
800d92e: 6a9b ldr r3, [r3, #40] ; 0x28
800d930: 2b00 cmp r3, #0
800d932: d004 beq.n 800d93e <xTaskIncrementTick+0xc6>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800d934: 68bb ldr r3, [r7, #8]
800d936: 3318 adds r3, #24
800d938: 4618 mov r0, r3
800d93a: f7fe fb8b bl 800c054 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800d93e: 68bb ldr r3, [r7, #8]
800d940: 6adb ldr r3, [r3, #44] ; 0x2c
800d942: 2201 movs r2, #1
800d944: 409a lsls r2, r3
800d946: 4b24 ldr r3, [pc, #144] ; (800d9d8 <xTaskIncrementTick+0x160>)
800d948: 681b ldr r3, [r3, #0]
800d94a: 4313 orrs r3, r2
800d94c: 4a22 ldr r2, [pc, #136] ; (800d9d8 <xTaskIncrementTick+0x160>)
800d94e: 6013 str r3, [r2, #0]
800d950: 68bb ldr r3, [r7, #8]
800d952: 6ada ldr r2, [r3, #44] ; 0x2c
800d954: 4613 mov r3, r2
800d956: 009b lsls r3, r3, #2
800d958: 4413 add r3, r2
800d95a: 009b lsls r3, r3, #2
800d95c: 4a1f ldr r2, [pc, #124] ; (800d9dc <xTaskIncrementTick+0x164>)
800d95e: 441a add r2, r3
800d960: 68bb ldr r3, [r7, #8]
800d962: 3304 adds r3, #4
800d964: 4619 mov r1, r3
800d966: 4610 mov r0, r2
800d968: f7fe fb17 bl 800bf9a <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800d96c: 68bb ldr r3, [r7, #8]
800d96e: 6ada ldr r2, [r3, #44] ; 0x2c
800d970: 4b1b ldr r3, [pc, #108] ; (800d9e0 <xTaskIncrementTick+0x168>)
800d972: 681b ldr r3, [r3, #0]
800d974: 6adb ldr r3, [r3, #44] ; 0x2c
800d976: 429a cmp r2, r3
800d978: d3b9 bcc.n 800d8ee <xTaskIncrementTick+0x76>
{
xSwitchRequired = pdTRUE;
800d97a: 2301 movs r3, #1
800d97c: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800d97e: e7b6 b.n 800d8ee <xTaskIncrementTick+0x76>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800d980: 4b17 ldr r3, [pc, #92] ; (800d9e0 <xTaskIncrementTick+0x168>)
800d982: 681b ldr r3, [r3, #0]
800d984: 6ada ldr r2, [r3, #44] ; 0x2c
800d986: 4915 ldr r1, [pc, #84] ; (800d9dc <xTaskIncrementTick+0x164>)
800d988: 4613 mov r3, r2
800d98a: 009b lsls r3, r3, #2
800d98c: 4413 add r3, r2
800d98e: 009b lsls r3, r3, #2
800d990: 440b add r3, r1
800d992: 681b ldr r3, [r3, #0]
800d994: 2b01 cmp r3, #1
800d996: d907 bls.n 800d9a8 <xTaskIncrementTick+0x130>
{
xSwitchRequired = pdTRUE;
800d998: 2301 movs r3, #1
800d99a: 617b str r3, [r7, #20]
800d99c: e004 b.n 800d9a8 <xTaskIncrementTick+0x130>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
800d99e: 4b11 ldr r3, [pc, #68] ; (800d9e4 <xTaskIncrementTick+0x16c>)
800d9a0: 681b ldr r3, [r3, #0]
800d9a2: 3301 adds r3, #1
800d9a4: 4a0f ldr r2, [pc, #60] ; (800d9e4 <xTaskIncrementTick+0x16c>)
800d9a6: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
800d9a8: 4b0f ldr r3, [pc, #60] ; (800d9e8 <xTaskIncrementTick+0x170>)
800d9aa: 681b ldr r3, [r3, #0]
800d9ac: 2b00 cmp r3, #0
800d9ae: d001 beq.n 800d9b4 <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
800d9b0: 2301 movs r3, #1
800d9b2: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
800d9b4: 697b ldr r3, [r7, #20]
}
800d9b6: 4618 mov r0, r3
800d9b8: 3718 adds r7, #24
800d9ba: 46bd mov sp, r7
800d9bc: bd80 pop {r7, pc}
800d9be: bf00 nop
800d9c0: 200006b4 .word 0x200006b4
800d9c4: 20000690 .word 0x20000690
800d9c8: 20000644 .word 0x20000644
800d9cc: 20000648 .word 0x20000648
800d9d0: 200006a4 .word 0x200006a4
800d9d4: 200006ac .word 0x200006ac
800d9d8: 20000694 .word 0x20000694
800d9dc: 20000590 .word 0x20000590
800d9e0: 2000058c .word 0x2000058c
800d9e4: 2000069c .word 0x2000069c
800d9e8: 200006a0 .word 0x200006a0
0800d9ec <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
800d9ec: b580 push {r7, lr}
800d9ee: b088 sub sp, #32
800d9f0: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
800d9f2: 4b3a ldr r3, [pc, #232] ; (800dadc <vTaskSwitchContext+0xf0>)
800d9f4: 681b ldr r3, [r3, #0]
800d9f6: 2b00 cmp r3, #0
800d9f8: d003 beq.n 800da02 <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
800d9fa: 4b39 ldr r3, [pc, #228] ; (800dae0 <vTaskSwitchContext+0xf4>)
800d9fc: 2201 movs r2, #1
800d9fe: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
800da00: e067 b.n 800dad2 <vTaskSwitchContext+0xe6>
xYieldPending = pdFALSE;
800da02: 4b37 ldr r3, [pc, #220] ; (800dae0 <vTaskSwitchContext+0xf4>)
800da04: 2200 movs r2, #0
800da06: 601a str r2, [r3, #0]
taskCHECK_FOR_STACK_OVERFLOW();
800da08: 4b36 ldr r3, [pc, #216] ; (800dae4 <vTaskSwitchContext+0xf8>)
800da0a: 681b ldr r3, [r3, #0]
800da0c: 6b1b ldr r3, [r3, #48] ; 0x30
800da0e: 61fb str r3, [r7, #28]
800da10: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5
800da14: 61bb str r3, [r7, #24]
800da16: 69fb ldr r3, [r7, #28]
800da18: 681b ldr r3, [r3, #0]
800da1a: 69ba ldr r2, [r7, #24]
800da1c: 429a cmp r2, r3
800da1e: d111 bne.n 800da44 <vTaskSwitchContext+0x58>
800da20: 69fb ldr r3, [r7, #28]
800da22: 3304 adds r3, #4
800da24: 681b ldr r3, [r3, #0]
800da26: 69ba ldr r2, [r7, #24]
800da28: 429a cmp r2, r3
800da2a: d10b bne.n 800da44 <vTaskSwitchContext+0x58>
800da2c: 69fb ldr r3, [r7, #28]
800da2e: 3308 adds r3, #8
800da30: 681b ldr r3, [r3, #0]
800da32: 69ba ldr r2, [r7, #24]
800da34: 429a cmp r2, r3
800da36: d105 bne.n 800da44 <vTaskSwitchContext+0x58>
800da38: 69fb ldr r3, [r7, #28]
800da3a: 330c adds r3, #12
800da3c: 681b ldr r3, [r3, #0]
800da3e: 69ba ldr r2, [r7, #24]
800da40: 429a cmp r2, r3
800da42: d008 beq.n 800da56 <vTaskSwitchContext+0x6a>
800da44: 4b27 ldr r3, [pc, #156] ; (800dae4 <vTaskSwitchContext+0xf8>)
800da46: 681a ldr r2, [r3, #0]
800da48: 4b26 ldr r3, [pc, #152] ; (800dae4 <vTaskSwitchContext+0xf8>)
800da4a: 681b ldr r3, [r3, #0]
800da4c: 3334 adds r3, #52 ; 0x34
800da4e: 4619 mov r1, r3
800da50: 4610 mov r0, r2
800da52: f7f2 fdb4 bl 80005be <vApplicationStackOverflowHook>
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800da56: 4b24 ldr r3, [pc, #144] ; (800dae8 <vTaskSwitchContext+0xfc>)
800da58: 681b ldr r3, [r3, #0]
800da5a: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
800da5c: 68fb ldr r3, [r7, #12]
800da5e: fab3 f383 clz r3, r3
800da62: 72fb strb r3, [r7, #11]
return ucReturn;
800da64: 7afb ldrb r3, [r7, #11]
800da66: f1c3 031f rsb r3, r3, #31
800da6a: 617b str r3, [r7, #20]
800da6c: 491f ldr r1, [pc, #124] ; (800daec <vTaskSwitchContext+0x100>)
800da6e: 697a ldr r2, [r7, #20]
800da70: 4613 mov r3, r2
800da72: 009b lsls r3, r3, #2
800da74: 4413 add r3, r2
800da76: 009b lsls r3, r3, #2
800da78: 440b add r3, r1
800da7a: 681b ldr r3, [r3, #0]
800da7c: 2b00 cmp r3, #0
800da7e: d10b bne.n 800da98 <vTaskSwitchContext+0xac>
__asm volatile
800da80: f04f 0350 mov.w r3, #80 ; 0x50
800da84: b672 cpsid i
800da86: f383 8811 msr BASEPRI, r3
800da8a: f3bf 8f6f isb sy
800da8e: f3bf 8f4f dsb sy
800da92: b662 cpsie i
800da94: 607b str r3, [r7, #4]
800da96: e7fe b.n 800da96 <vTaskSwitchContext+0xaa>
800da98: 697a ldr r2, [r7, #20]
800da9a: 4613 mov r3, r2
800da9c: 009b lsls r3, r3, #2
800da9e: 4413 add r3, r2
800daa0: 009b lsls r3, r3, #2
800daa2: 4a12 ldr r2, [pc, #72] ; (800daec <vTaskSwitchContext+0x100>)
800daa4: 4413 add r3, r2
800daa6: 613b str r3, [r7, #16]
800daa8: 693b ldr r3, [r7, #16]
800daaa: 685b ldr r3, [r3, #4]
800daac: 685a ldr r2, [r3, #4]
800daae: 693b ldr r3, [r7, #16]
800dab0: 605a str r2, [r3, #4]
800dab2: 693b ldr r3, [r7, #16]
800dab4: 685a ldr r2, [r3, #4]
800dab6: 693b ldr r3, [r7, #16]
800dab8: 3308 adds r3, #8
800daba: 429a cmp r2, r3
800dabc: d104 bne.n 800dac8 <vTaskSwitchContext+0xdc>
800dabe: 693b ldr r3, [r7, #16]
800dac0: 685b ldr r3, [r3, #4]
800dac2: 685a ldr r2, [r3, #4]
800dac4: 693b ldr r3, [r7, #16]
800dac6: 605a str r2, [r3, #4]
800dac8: 693b ldr r3, [r7, #16]
800daca: 685b ldr r3, [r3, #4]
800dacc: 68db ldr r3, [r3, #12]
800dace: 4a05 ldr r2, [pc, #20] ; (800dae4 <vTaskSwitchContext+0xf8>)
800dad0: 6013 str r3, [r2, #0]
}
800dad2: bf00 nop
800dad4: 3720 adds r7, #32
800dad6: 46bd mov sp, r7
800dad8: bd80 pop {r7, pc}
800dada: bf00 nop
800dadc: 200006b4 .word 0x200006b4
800dae0: 200006a0 .word 0x200006a0
800dae4: 2000058c .word 0x2000058c
800dae8: 20000694 .word 0x20000694
800daec: 20000590 .word 0x20000590
0800daf0 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
800daf0: b580 push {r7, lr}
800daf2: b084 sub sp, #16
800daf4: af00 add r7, sp, #0
800daf6: 6078 str r0, [r7, #4]
800daf8: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
800dafa: 687b ldr r3, [r7, #4]
800dafc: 2b00 cmp r3, #0
800dafe: d10b bne.n 800db18 <vTaskPlaceOnEventList+0x28>
800db00: f04f 0350 mov.w r3, #80 ; 0x50
800db04: b672 cpsid i
800db06: f383 8811 msr BASEPRI, r3
800db0a: f3bf 8f6f isb sy
800db0e: f3bf 8f4f dsb sy
800db12: b662 cpsie i
800db14: 60fb str r3, [r7, #12]
800db16: e7fe b.n 800db16 <vTaskPlaceOnEventList+0x26>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
800db18: 4b07 ldr r3, [pc, #28] ; (800db38 <vTaskPlaceOnEventList+0x48>)
800db1a: 681b ldr r3, [r3, #0]
800db1c: 3318 adds r3, #24
800db1e: 4619 mov r1, r3
800db20: 6878 ldr r0, [r7, #4]
800db22: f7fe fa5e bl 800bfe2 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
800db26: 2101 movs r1, #1
800db28: 6838 ldr r0, [r7, #0]
800db2a: f000 fb9d bl 800e268 <prvAddCurrentTaskToDelayedList>
}
800db2e: bf00 nop
800db30: 3710 adds r7, #16
800db32: 46bd mov sp, r7
800db34: bd80 pop {r7, pc}
800db36: bf00 nop
800db38: 2000058c .word 0x2000058c
0800db3c <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
800db3c: b580 push {r7, lr}
800db3e: b086 sub sp, #24
800db40: af00 add r7, sp, #0
800db42: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800db44: 687b ldr r3, [r7, #4]
800db46: 68db ldr r3, [r3, #12]
800db48: 68db ldr r3, [r3, #12]
800db4a: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
800db4c: 693b ldr r3, [r7, #16]
800db4e: 2b00 cmp r3, #0
800db50: d10b bne.n 800db6a <xTaskRemoveFromEventList+0x2e>
800db52: f04f 0350 mov.w r3, #80 ; 0x50
800db56: b672 cpsid i
800db58: f383 8811 msr BASEPRI, r3
800db5c: f3bf 8f6f isb sy
800db60: f3bf 8f4f dsb sy
800db64: b662 cpsie i
800db66: 60fb str r3, [r7, #12]
800db68: e7fe b.n 800db68 <xTaskRemoveFromEventList+0x2c>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
800db6a: 693b ldr r3, [r7, #16]
800db6c: 3318 adds r3, #24
800db6e: 4618 mov r0, r3
800db70: f7fe fa70 bl 800c054 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800db74: 4b1d ldr r3, [pc, #116] ; (800dbec <xTaskRemoveFromEventList+0xb0>)
800db76: 681b ldr r3, [r3, #0]
800db78: 2b00 cmp r3, #0
800db7a: d11c bne.n 800dbb6 <xTaskRemoveFromEventList+0x7a>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
800db7c: 693b ldr r3, [r7, #16]
800db7e: 3304 adds r3, #4
800db80: 4618 mov r0, r3
800db82: f7fe fa67 bl 800c054 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
800db86: 693b ldr r3, [r7, #16]
800db88: 6adb ldr r3, [r3, #44] ; 0x2c
800db8a: 2201 movs r2, #1
800db8c: 409a lsls r2, r3
800db8e: 4b18 ldr r3, [pc, #96] ; (800dbf0 <xTaskRemoveFromEventList+0xb4>)
800db90: 681b ldr r3, [r3, #0]
800db92: 4313 orrs r3, r2
800db94: 4a16 ldr r2, [pc, #88] ; (800dbf0 <xTaskRemoveFromEventList+0xb4>)
800db96: 6013 str r3, [r2, #0]
800db98: 693b ldr r3, [r7, #16]
800db9a: 6ada ldr r2, [r3, #44] ; 0x2c
800db9c: 4613 mov r3, r2
800db9e: 009b lsls r3, r3, #2
800dba0: 4413 add r3, r2
800dba2: 009b lsls r3, r3, #2
800dba4: 4a13 ldr r2, [pc, #76] ; (800dbf4 <xTaskRemoveFromEventList+0xb8>)
800dba6: 441a add r2, r3
800dba8: 693b ldr r3, [r7, #16]
800dbaa: 3304 adds r3, #4
800dbac: 4619 mov r1, r3
800dbae: 4610 mov r0, r2
800dbb0: f7fe f9f3 bl 800bf9a <vListInsertEnd>
800dbb4: e005 b.n 800dbc2 <xTaskRemoveFromEventList+0x86>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
800dbb6: 693b ldr r3, [r7, #16]
800dbb8: 3318 adds r3, #24
800dbba: 4619 mov r1, r3
800dbbc: 480e ldr r0, [pc, #56] ; (800dbf8 <xTaskRemoveFromEventList+0xbc>)
800dbbe: f7fe f9ec bl 800bf9a <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
800dbc2: 693b ldr r3, [r7, #16]
800dbc4: 6ada ldr r2, [r3, #44] ; 0x2c
800dbc6: 4b0d ldr r3, [pc, #52] ; (800dbfc <xTaskRemoveFromEventList+0xc0>)
800dbc8: 681b ldr r3, [r3, #0]
800dbca: 6adb ldr r3, [r3, #44] ; 0x2c
800dbcc: 429a cmp r2, r3
800dbce: d905 bls.n 800dbdc <xTaskRemoveFromEventList+0xa0>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
800dbd0: 2301 movs r3, #1
800dbd2: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
800dbd4: 4b0a ldr r3, [pc, #40] ; (800dc00 <xTaskRemoveFromEventList+0xc4>)
800dbd6: 2201 movs r2, #1
800dbd8: 601a str r2, [r3, #0]
800dbda: e001 b.n 800dbe0 <xTaskRemoveFromEventList+0xa4>
}
else
{
xReturn = pdFALSE;
800dbdc: 2300 movs r3, #0
800dbde: 617b str r3, [r7, #20]
}
return xReturn;
800dbe0: 697b ldr r3, [r7, #20]
}
800dbe2: 4618 mov r0, r3
800dbe4: 3718 adds r7, #24
800dbe6: 46bd mov sp, r7
800dbe8: bd80 pop {r7, pc}
800dbea: bf00 nop
800dbec: 200006b4 .word 0x200006b4
800dbf0: 20000694 .word 0x20000694
800dbf4: 20000590 .word 0x20000590
800dbf8: 2000064c .word 0x2000064c
800dbfc: 2000058c .word 0x2000058c
800dc00: 200006a0 .word 0x200006a0
0800dc04 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
800dc04: b480 push {r7}
800dc06: b083 sub sp, #12
800dc08: af00 add r7, sp, #0
800dc0a: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
800dc0c: 4b06 ldr r3, [pc, #24] ; (800dc28 <vTaskInternalSetTimeOutState+0x24>)
800dc0e: 681a ldr r2, [r3, #0]
800dc10: 687b ldr r3, [r7, #4]
800dc12: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
800dc14: 4b05 ldr r3, [pc, #20] ; (800dc2c <vTaskInternalSetTimeOutState+0x28>)
800dc16: 681a ldr r2, [r3, #0]
800dc18: 687b ldr r3, [r7, #4]
800dc1a: 605a str r2, [r3, #4]
}
800dc1c: bf00 nop
800dc1e: 370c adds r7, #12
800dc20: 46bd mov sp, r7
800dc22: f85d 7b04 ldr.w r7, [sp], #4
800dc26: 4770 bx lr
800dc28: 200006a4 .word 0x200006a4
800dc2c: 20000690 .word 0x20000690
0800dc30 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
800dc30: b580 push {r7, lr}
800dc32: b088 sub sp, #32
800dc34: af00 add r7, sp, #0
800dc36: 6078 str r0, [r7, #4]
800dc38: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
800dc3a: 687b ldr r3, [r7, #4]
800dc3c: 2b00 cmp r3, #0
800dc3e: d10b bne.n 800dc58 <xTaskCheckForTimeOut+0x28>
800dc40: f04f 0350 mov.w r3, #80 ; 0x50
800dc44: b672 cpsid i
800dc46: f383 8811 msr BASEPRI, r3
800dc4a: f3bf 8f6f isb sy
800dc4e: f3bf 8f4f dsb sy
800dc52: b662 cpsie i
800dc54: 613b str r3, [r7, #16]
800dc56: e7fe b.n 800dc56 <xTaskCheckForTimeOut+0x26>
configASSERT( pxTicksToWait );
800dc58: 683b ldr r3, [r7, #0]
800dc5a: 2b00 cmp r3, #0
800dc5c: d10b bne.n 800dc76 <xTaskCheckForTimeOut+0x46>
800dc5e: f04f 0350 mov.w r3, #80 ; 0x50
800dc62: b672 cpsid i
800dc64: f383 8811 msr BASEPRI, r3
800dc68: f3bf 8f6f isb sy
800dc6c: f3bf 8f4f dsb sy
800dc70: b662 cpsie i
800dc72: 60fb str r3, [r7, #12]
800dc74: e7fe b.n 800dc74 <xTaskCheckForTimeOut+0x44>
taskENTER_CRITICAL();
800dc76: f000 fc67 bl 800e548 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
800dc7a: 4b1d ldr r3, [pc, #116] ; (800dcf0 <xTaskCheckForTimeOut+0xc0>)
800dc7c: 681b ldr r3, [r3, #0]
800dc7e: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800dc80: 687b ldr r3, [r7, #4]
800dc82: 685b ldr r3, [r3, #4]
800dc84: 69ba ldr r2, [r7, #24]
800dc86: 1ad3 subs r3, r2, r3
800dc88: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
800dc8a: 683b ldr r3, [r7, #0]
800dc8c: 681b ldr r3, [r3, #0]
800dc8e: f1b3 3fff cmp.w r3, #4294967295
800dc92: d102 bne.n 800dc9a <xTaskCheckForTimeOut+0x6a>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
800dc94: 2300 movs r3, #0
800dc96: 61fb str r3, [r7, #28]
800dc98: e023 b.n 800dce2 <xTaskCheckForTimeOut+0xb2>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
800dc9a: 687b ldr r3, [r7, #4]
800dc9c: 681a ldr r2, [r3, #0]
800dc9e: 4b15 ldr r3, [pc, #84] ; (800dcf4 <xTaskCheckForTimeOut+0xc4>)
800dca0: 681b ldr r3, [r3, #0]
800dca2: 429a cmp r2, r3
800dca4: d007 beq.n 800dcb6 <xTaskCheckForTimeOut+0x86>
800dca6: 687b ldr r3, [r7, #4]
800dca8: 685b ldr r3, [r3, #4]
800dcaa: 69ba ldr r2, [r7, #24]
800dcac: 429a cmp r2, r3
800dcae: d302 bcc.n 800dcb6 <xTaskCheckForTimeOut+0x86>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
800dcb0: 2301 movs r3, #1
800dcb2: 61fb str r3, [r7, #28]
800dcb4: e015 b.n 800dce2 <xTaskCheckForTimeOut+0xb2>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
800dcb6: 683b ldr r3, [r7, #0]
800dcb8: 681b ldr r3, [r3, #0]
800dcba: 697a ldr r2, [r7, #20]
800dcbc: 429a cmp r2, r3
800dcbe: d20b bcs.n 800dcd8 <xTaskCheckForTimeOut+0xa8>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
800dcc0: 683b ldr r3, [r7, #0]
800dcc2: 681a ldr r2, [r3, #0]
800dcc4: 697b ldr r3, [r7, #20]
800dcc6: 1ad2 subs r2, r2, r3
800dcc8: 683b ldr r3, [r7, #0]
800dcca: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
800dccc: 6878 ldr r0, [r7, #4]
800dcce: f7ff ff99 bl 800dc04 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
800dcd2: 2300 movs r3, #0
800dcd4: 61fb str r3, [r7, #28]
800dcd6: e004 b.n 800dce2 <xTaskCheckForTimeOut+0xb2>
}
else
{
*pxTicksToWait = 0;
800dcd8: 683b ldr r3, [r7, #0]
800dcda: 2200 movs r2, #0
800dcdc: 601a str r2, [r3, #0]
xReturn = pdTRUE;
800dcde: 2301 movs r3, #1
800dce0: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
800dce2: f000 fc63 bl 800e5ac <vPortExitCritical>
return xReturn;
800dce6: 69fb ldr r3, [r7, #28]
}
800dce8: 4618 mov r0, r3
800dcea: 3720 adds r7, #32
800dcec: 46bd mov sp, r7
800dcee: bd80 pop {r7, pc}
800dcf0: 20000690 .word 0x20000690
800dcf4: 200006a4 .word 0x200006a4
0800dcf8 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
800dcf8: b480 push {r7}
800dcfa: af00 add r7, sp, #0
xYieldPending = pdTRUE;
800dcfc: 4b03 ldr r3, [pc, #12] ; (800dd0c <vTaskMissedYield+0x14>)
800dcfe: 2201 movs r2, #1
800dd00: 601a str r2, [r3, #0]
}
800dd02: bf00 nop
800dd04: 46bd mov sp, r7
800dd06: f85d 7b04 ldr.w r7, [sp], #4
800dd0a: 4770 bx lr
800dd0c: 200006a0 .word 0x200006a0
0800dd10 <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
800dd10: b580 push {r7, lr}
800dd12: b082 sub sp, #8
800dd14: af00 add r7, sp, #0
800dd16: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
800dd18: f000 f854 bl 800ddc4 <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
800dd1c: 4b07 ldr r3, [pc, #28] ; (800dd3c <prvIdleTask+0x2c>)
800dd1e: 681b ldr r3, [r3, #0]
800dd20: 2b01 cmp r3, #1
800dd22: d907 bls.n 800dd34 <prvIdleTask+0x24>
{
taskYIELD();
800dd24: 4b06 ldr r3, [pc, #24] ; (800dd40 <prvIdleTask+0x30>)
800dd26: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800dd2a: 601a str r2, [r3, #0]
800dd2c: f3bf 8f4f dsb sy
800dd30: f3bf 8f6f isb sy
/* Call the user defined function from within the idle task. This
allows the application designer to add background functionality
without the overhead of a separate task.
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
CALL A FUNCTION THAT MIGHT BLOCK. */
vApplicationIdleHook();
800dd34: f7f2 fc3c bl 80005b0 <vApplicationIdleHook>
prvCheckTasksWaitingTermination();
800dd38: e7ee b.n 800dd18 <prvIdleTask+0x8>
800dd3a: bf00 nop
800dd3c: 20000590 .word 0x20000590
800dd40: e000ed04 .word 0xe000ed04
0800dd44 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800dd44: b580 push {r7, lr}
800dd46: b082 sub sp, #8
800dd48: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dd4a: 2300 movs r3, #0
800dd4c: 607b str r3, [r7, #4]
800dd4e: e00c b.n 800dd6a <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
800dd50: 687a ldr r2, [r7, #4]
800dd52: 4613 mov r3, r2
800dd54: 009b lsls r3, r3, #2
800dd56: 4413 add r3, r2
800dd58: 009b lsls r3, r3, #2
800dd5a: 4a12 ldr r2, [pc, #72] ; (800dda4 <prvInitialiseTaskLists+0x60>)
800dd5c: 4413 add r3, r2
800dd5e: 4618 mov r0, r3
800dd60: f7fe f8ee bl 800bf40 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800dd64: 687b ldr r3, [r7, #4]
800dd66: 3301 adds r3, #1
800dd68: 607b str r3, [r7, #4]
800dd6a: 687b ldr r3, [r7, #4]
800dd6c: 2b06 cmp r3, #6
800dd6e: d9ef bls.n 800dd50 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
800dd70: 480d ldr r0, [pc, #52] ; (800dda8 <prvInitialiseTaskLists+0x64>)
800dd72: f7fe f8e5 bl 800bf40 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800dd76: 480d ldr r0, [pc, #52] ; (800ddac <prvInitialiseTaskLists+0x68>)
800dd78: f7fe f8e2 bl 800bf40 <vListInitialise>
vListInitialise( &xPendingReadyList );
800dd7c: 480c ldr r0, [pc, #48] ; (800ddb0 <prvInitialiseTaskLists+0x6c>)
800dd7e: f7fe f8df bl 800bf40 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800dd82: 480c ldr r0, [pc, #48] ; (800ddb4 <prvInitialiseTaskLists+0x70>)
800dd84: f7fe f8dc bl 800bf40 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
800dd88: 480b ldr r0, [pc, #44] ; (800ddb8 <prvInitialiseTaskLists+0x74>)
800dd8a: f7fe f8d9 bl 800bf40 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
800dd8e: 4b0b ldr r3, [pc, #44] ; (800ddbc <prvInitialiseTaskLists+0x78>)
800dd90: 4a05 ldr r2, [pc, #20] ; (800dda8 <prvInitialiseTaskLists+0x64>)
800dd92: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800dd94: 4b0a ldr r3, [pc, #40] ; (800ddc0 <prvInitialiseTaskLists+0x7c>)
800dd96: 4a05 ldr r2, [pc, #20] ; (800ddac <prvInitialiseTaskLists+0x68>)
800dd98: 601a str r2, [r3, #0]
}
800dd9a: bf00 nop
800dd9c: 3708 adds r7, #8
800dd9e: 46bd mov sp, r7
800dda0: bd80 pop {r7, pc}
800dda2: bf00 nop
800dda4: 20000590 .word 0x20000590
800dda8: 2000061c .word 0x2000061c
800ddac: 20000630 .word 0x20000630
800ddb0: 2000064c .word 0x2000064c
800ddb4: 20000660 .word 0x20000660
800ddb8: 20000678 .word 0x20000678
800ddbc: 20000644 .word 0x20000644
800ddc0: 20000648 .word 0x20000648
0800ddc4 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
800ddc4: b580 push {r7, lr}
800ddc6: b082 sub sp, #8
800ddc8: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800ddca: e019 b.n 800de00 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
800ddcc: f000 fbbc bl 800e548 <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800ddd0: 4b0f ldr r3, [pc, #60] ; (800de10 <prvCheckTasksWaitingTermination+0x4c>)
800ddd2: 68db ldr r3, [r3, #12]
800ddd4: 68db ldr r3, [r3, #12]
800ddd6: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800ddd8: 687b ldr r3, [r7, #4]
800ddda: 3304 adds r3, #4
800dddc: 4618 mov r0, r3
800ddde: f7fe f939 bl 800c054 <uxListRemove>
--uxCurrentNumberOfTasks;
800dde2: 4b0c ldr r3, [pc, #48] ; (800de14 <prvCheckTasksWaitingTermination+0x50>)
800dde4: 681b ldr r3, [r3, #0]
800dde6: 3b01 subs r3, #1
800dde8: 4a0a ldr r2, [pc, #40] ; (800de14 <prvCheckTasksWaitingTermination+0x50>)
800ddea: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
800ddec: 4b0a ldr r3, [pc, #40] ; (800de18 <prvCheckTasksWaitingTermination+0x54>)
800ddee: 681b ldr r3, [r3, #0]
800ddf0: 3b01 subs r3, #1
800ddf2: 4a09 ldr r2, [pc, #36] ; (800de18 <prvCheckTasksWaitingTermination+0x54>)
800ddf4: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
800ddf6: f000 fbd9 bl 800e5ac <vPortExitCritical>
prvDeleteTCB( pxTCB );
800ddfa: 6878 ldr r0, [r7, #4]
800ddfc: f000 f80e bl 800de1c <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
800de00: 4b05 ldr r3, [pc, #20] ; (800de18 <prvCheckTasksWaitingTermination+0x54>)
800de02: 681b ldr r3, [r3, #0]
800de04: 2b00 cmp r3, #0
800de06: d1e1 bne.n 800ddcc <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
800de08: bf00 nop
800de0a: 3708 adds r7, #8
800de0c: 46bd mov sp, r7
800de0e: bd80 pop {r7, pc}
800de10: 20000660 .word 0x20000660
800de14: 2000068c .word 0x2000068c
800de18: 20000674 .word 0x20000674
0800de1c <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
800de1c: b580 push {r7, lr}
800de1e: b084 sub sp, #16
800de20: af00 add r7, sp, #0
800de22: 6078 str r0, [r7, #4]
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
800de24: 687b ldr r3, [r7, #4]
800de26: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de2a: 2b00 cmp r3, #0
800de2c: d108 bne.n 800de40 <prvDeleteTCB+0x24>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
800de2e: 687b ldr r3, [r7, #4]
800de30: 6b1b ldr r3, [r3, #48] ; 0x30
800de32: 4618 mov r0, r3
800de34: f000 fd76 bl 800e924 <vPortFree>
vPortFree( pxTCB );
800de38: 6878 ldr r0, [r7, #4]
800de3a: f000 fd73 bl 800e924 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
800de3e: e019 b.n 800de74 <prvDeleteTCB+0x58>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
800de40: 687b ldr r3, [r7, #4]
800de42: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de46: 2b01 cmp r3, #1
800de48: d103 bne.n 800de52 <prvDeleteTCB+0x36>
vPortFree( pxTCB );
800de4a: 6878 ldr r0, [r7, #4]
800de4c: f000 fd6a bl 800e924 <vPortFree>
}
800de50: e010 b.n 800de74 <prvDeleteTCB+0x58>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
800de52: 687b ldr r3, [r7, #4]
800de54: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
800de58: 2b02 cmp r3, #2
800de5a: d00b beq.n 800de74 <prvDeleteTCB+0x58>
800de5c: f04f 0350 mov.w r3, #80 ; 0x50
800de60: b672 cpsid i
800de62: f383 8811 msr BASEPRI, r3
800de66: f3bf 8f6f isb sy
800de6a: f3bf 8f4f dsb sy
800de6e: b662 cpsie i
800de70: 60fb str r3, [r7, #12]
800de72: e7fe b.n 800de72 <prvDeleteTCB+0x56>
}
800de74: bf00 nop
800de76: 3710 adds r7, #16
800de78: 46bd mov sp, r7
800de7a: bd80 pop {r7, pc}
0800de7c <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
800de7c: b480 push {r7}
800de7e: b083 sub sp, #12
800de80: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800de82: 4b0c ldr r3, [pc, #48] ; (800deb4 <prvResetNextTaskUnblockTime+0x38>)
800de84: 681b ldr r3, [r3, #0]
800de86: 681b ldr r3, [r3, #0]
800de88: 2b00 cmp r3, #0
800de8a: d104 bne.n 800de96 <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
800de8c: 4b0a ldr r3, [pc, #40] ; (800deb8 <prvResetNextTaskUnblockTime+0x3c>)
800de8e: f04f 32ff mov.w r2, #4294967295
800de92: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
800de94: e008 b.n 800dea8 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800de96: 4b07 ldr r3, [pc, #28] ; (800deb4 <prvResetNextTaskUnblockTime+0x38>)
800de98: 681b ldr r3, [r3, #0]
800de9a: 68db ldr r3, [r3, #12]
800de9c: 68db ldr r3, [r3, #12]
800de9e: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
800dea0: 687b ldr r3, [r7, #4]
800dea2: 685b ldr r3, [r3, #4]
800dea4: 4a04 ldr r2, [pc, #16] ; (800deb8 <prvResetNextTaskUnblockTime+0x3c>)
800dea6: 6013 str r3, [r2, #0]
}
800dea8: bf00 nop
800deaa: 370c adds r7, #12
800deac: 46bd mov sp, r7
800deae: f85d 7b04 ldr.w r7, [sp], #4
800deb2: 4770 bx lr
800deb4: 20000644 .word 0x20000644
800deb8: 200006ac .word 0x200006ac
0800debc <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
800debc: b480 push {r7}
800debe: b083 sub sp, #12
800dec0: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
800dec2: 4b0b ldr r3, [pc, #44] ; (800def0 <xTaskGetSchedulerState+0x34>)
800dec4: 681b ldr r3, [r3, #0]
800dec6: 2b00 cmp r3, #0
800dec8: d102 bne.n 800ded0 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800deca: 2301 movs r3, #1
800decc: 607b str r3, [r7, #4]
800dece: e008 b.n 800dee2 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800ded0: 4b08 ldr r3, [pc, #32] ; (800def4 <xTaskGetSchedulerState+0x38>)
800ded2: 681b ldr r3, [r3, #0]
800ded4: 2b00 cmp r3, #0
800ded6: d102 bne.n 800dede <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
800ded8: 2302 movs r3, #2
800deda: 607b str r3, [r7, #4]
800dedc: e001 b.n 800dee2 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
800dede: 2300 movs r3, #0
800dee0: 607b str r3, [r7, #4]
}
}
return xReturn;
800dee2: 687b ldr r3, [r7, #4]
}
800dee4: 4618 mov r0, r3
800dee6: 370c adds r7, #12
800dee8: 46bd mov sp, r7
800deea: f85d 7b04 ldr.w r7, [sp], #4
800deee: 4770 bx lr
800def0: 20000698 .word 0x20000698
800def4: 200006b4 .word 0x200006b4
0800def8 <xTaskPriorityInherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
{
800def8: b580 push {r7, lr}
800defa: b084 sub sp, #16
800defc: af00 add r7, sp, #0
800defe: 6078 str r0, [r7, #4]
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
800df00: 687b ldr r3, [r7, #4]
800df02: 60bb str r3, [r7, #8]
BaseType_t xReturn = pdFALSE;
800df04: 2300 movs r3, #0
800df06: 60fb str r3, [r7, #12]
/* If the mutex was given back by an interrupt while the queue was
locked then the mutex holder might now be NULL. _RB_ Is this still
needed as interrupts can no longer use mutexes? */
if( pxMutexHolder != NULL )
800df08: 687b ldr r3, [r7, #4]
800df0a: 2b00 cmp r3, #0
800df0c: d069 beq.n 800dfe2 <xTaskPriorityInherit+0xea>
{
/* If the holder of the mutex has a priority below the priority of
the task attempting to obtain the mutex then it will temporarily
inherit the priority of the task attempting to obtain the mutex. */
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
800df0e: 68bb ldr r3, [r7, #8]
800df10: 6ada ldr r2, [r3, #44] ; 0x2c
800df12: 4b36 ldr r3, [pc, #216] ; (800dfec <xTaskPriorityInherit+0xf4>)
800df14: 681b ldr r3, [r3, #0]
800df16: 6adb ldr r3, [r3, #44] ; 0x2c
800df18: 429a cmp r2, r3
800df1a: d259 bcs.n 800dfd0 <xTaskPriorityInherit+0xd8>
{
/* Adjust the mutex holder state to account for its new
priority. Only reset the event list item value if the value is
not being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800df1c: 68bb ldr r3, [r7, #8]
800df1e: 699b ldr r3, [r3, #24]
800df20: 2b00 cmp r3, #0
800df22: db06 blt.n 800df32 <xTaskPriorityInherit+0x3a>
{
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800df24: 4b31 ldr r3, [pc, #196] ; (800dfec <xTaskPriorityInherit+0xf4>)
800df26: 681b ldr r3, [r3, #0]
800df28: 6adb ldr r3, [r3, #44] ; 0x2c
800df2a: f1c3 0207 rsb r2, r3, #7
800df2e: 68bb ldr r3, [r7, #8]
800df30: 619a str r2, [r3, #24]
mtCOVERAGE_TEST_MARKER();
}
/* If the task being modified is in the ready state it will need
to be moved into a new list. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
800df32: 68bb ldr r3, [r7, #8]
800df34: 6959 ldr r1, [r3, #20]
800df36: 68bb ldr r3, [r7, #8]
800df38: 6ada ldr r2, [r3, #44] ; 0x2c
800df3a: 4613 mov r3, r2
800df3c: 009b lsls r3, r3, #2
800df3e: 4413 add r3, r2
800df40: 009b lsls r3, r3, #2
800df42: 4a2b ldr r2, [pc, #172] ; (800dff0 <xTaskPriorityInherit+0xf8>)
800df44: 4413 add r3, r2
800df46: 4299 cmp r1, r3
800df48: d13a bne.n 800dfc0 <xTaskPriorityInherit+0xc8>
{
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800df4a: 68bb ldr r3, [r7, #8]
800df4c: 3304 adds r3, #4
800df4e: 4618 mov r0, r3
800df50: f7fe f880 bl 800c054 <uxListRemove>
800df54: 4603 mov r3, r0
800df56: 2b00 cmp r3, #0
800df58: d115 bne.n 800df86 <xTaskPriorityInherit+0x8e>
{
taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
800df5a: 68bb ldr r3, [r7, #8]
800df5c: 6ada ldr r2, [r3, #44] ; 0x2c
800df5e: 4924 ldr r1, [pc, #144] ; (800dff0 <xTaskPriorityInherit+0xf8>)
800df60: 4613 mov r3, r2
800df62: 009b lsls r3, r3, #2
800df64: 4413 add r3, r2
800df66: 009b lsls r3, r3, #2
800df68: 440b add r3, r1
800df6a: 681b ldr r3, [r3, #0]
800df6c: 2b00 cmp r3, #0
800df6e: d10a bne.n 800df86 <xTaskPriorityInherit+0x8e>
800df70: 68bb ldr r3, [r7, #8]
800df72: 6adb ldr r3, [r3, #44] ; 0x2c
800df74: 2201 movs r2, #1
800df76: fa02 f303 lsl.w r3, r2, r3
800df7a: 43da mvns r2, r3
800df7c: 4b1d ldr r3, [pc, #116] ; (800dff4 <xTaskPriorityInherit+0xfc>)
800df7e: 681b ldr r3, [r3, #0]
800df80: 4013 ands r3, r2
800df82: 4a1c ldr r2, [pc, #112] ; (800dff4 <xTaskPriorityInherit+0xfc>)
800df84: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
/* Inherit the priority before being moved into the new list. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800df86: 4b19 ldr r3, [pc, #100] ; (800dfec <xTaskPriorityInherit+0xf4>)
800df88: 681b ldr r3, [r3, #0]
800df8a: 6ada ldr r2, [r3, #44] ; 0x2c
800df8c: 68bb ldr r3, [r7, #8]
800df8e: 62da str r2, [r3, #44] ; 0x2c
prvAddTaskToReadyList( pxMutexHolderTCB );
800df90: 68bb ldr r3, [r7, #8]
800df92: 6adb ldr r3, [r3, #44] ; 0x2c
800df94: 2201 movs r2, #1
800df96: 409a lsls r2, r3
800df98: 4b16 ldr r3, [pc, #88] ; (800dff4 <xTaskPriorityInherit+0xfc>)
800df9a: 681b ldr r3, [r3, #0]
800df9c: 4313 orrs r3, r2
800df9e: 4a15 ldr r2, [pc, #84] ; (800dff4 <xTaskPriorityInherit+0xfc>)
800dfa0: 6013 str r3, [r2, #0]
800dfa2: 68bb ldr r3, [r7, #8]
800dfa4: 6ada ldr r2, [r3, #44] ; 0x2c
800dfa6: 4613 mov r3, r2
800dfa8: 009b lsls r3, r3, #2
800dfaa: 4413 add r3, r2
800dfac: 009b lsls r3, r3, #2
800dfae: 4a10 ldr r2, [pc, #64] ; (800dff0 <xTaskPriorityInherit+0xf8>)
800dfb0: 441a add r2, r3
800dfb2: 68bb ldr r3, [r7, #8]
800dfb4: 3304 adds r3, #4
800dfb6: 4619 mov r1, r3
800dfb8: 4610 mov r0, r2
800dfba: f7fd ffee bl 800bf9a <vListInsertEnd>
800dfbe: e004 b.n 800dfca <xTaskPriorityInherit+0xd2>
}
else
{
/* Just inherit the priority. */
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
800dfc0: 4b0a ldr r3, [pc, #40] ; (800dfec <xTaskPriorityInherit+0xf4>)
800dfc2: 681b ldr r3, [r3, #0]
800dfc4: 6ada ldr r2, [r3, #44] ; 0x2c
800dfc6: 68bb ldr r3, [r7, #8]
800dfc8: 62da str r2, [r3, #44] ; 0x2c
}
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
/* Inheritance occurred. */
xReturn = pdTRUE;
800dfca: 2301 movs r3, #1
800dfcc: 60fb str r3, [r7, #12]
800dfce: e008 b.n 800dfe2 <xTaskPriorityInherit+0xea>
}
else
{
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
800dfd0: 68bb ldr r3, [r7, #8]
800dfd2: 6c5a ldr r2, [r3, #68] ; 0x44
800dfd4: 4b05 ldr r3, [pc, #20] ; (800dfec <xTaskPriorityInherit+0xf4>)
800dfd6: 681b ldr r3, [r3, #0]
800dfd8: 6adb ldr r3, [r3, #44] ; 0x2c
800dfda: 429a cmp r2, r3
800dfdc: d201 bcs.n 800dfe2 <xTaskPriorityInherit+0xea>
current priority of the mutex holder is not lower than the
priority of the task attempting to take the mutex.
Therefore the mutex holder must have already inherited a
priority, but inheritance would have occurred if that had
not been the case. */
xReturn = pdTRUE;
800dfde: 2301 movs r3, #1
800dfe0: 60fb str r3, [r7, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800dfe2: 68fb ldr r3, [r7, #12]
}
800dfe4: 4618 mov r0, r3
800dfe6: 3710 adds r7, #16
800dfe8: 46bd mov sp, r7
800dfea: bd80 pop {r7, pc}
800dfec: 2000058c .word 0x2000058c
800dff0: 20000590 .word 0x20000590
800dff4: 20000694 .word 0x20000694
0800dff8 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
800dff8: b580 push {r7, lr}
800dffa: b086 sub sp, #24
800dffc: af00 add r7, sp, #0
800dffe: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
800e000: 687b ldr r3, [r7, #4]
800e002: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
800e004: 2300 movs r3, #0
800e006: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800e008: 687b ldr r3, [r7, #4]
800e00a: 2b00 cmp r3, #0
800e00c: d070 beq.n 800e0f0 <xTaskPriorityDisinherit+0xf8>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
800e00e: 4b3b ldr r3, [pc, #236] ; (800e0fc <xTaskPriorityDisinherit+0x104>)
800e010: 681b ldr r3, [r3, #0]
800e012: 693a ldr r2, [r7, #16]
800e014: 429a cmp r2, r3
800e016: d00b beq.n 800e030 <xTaskPriorityDisinherit+0x38>
800e018: f04f 0350 mov.w r3, #80 ; 0x50
800e01c: b672 cpsid i
800e01e: f383 8811 msr BASEPRI, r3
800e022: f3bf 8f6f isb sy
800e026: f3bf 8f4f dsb sy
800e02a: b662 cpsie i
800e02c: 60fb str r3, [r7, #12]
800e02e: e7fe b.n 800e02e <xTaskPriorityDisinherit+0x36>
configASSERT( pxTCB->uxMutexesHeld );
800e030: 693b ldr r3, [r7, #16]
800e032: 6c9b ldr r3, [r3, #72] ; 0x48
800e034: 2b00 cmp r3, #0
800e036: d10b bne.n 800e050 <xTaskPriorityDisinherit+0x58>
800e038: f04f 0350 mov.w r3, #80 ; 0x50
800e03c: b672 cpsid i
800e03e: f383 8811 msr BASEPRI, r3
800e042: f3bf 8f6f isb sy
800e046: f3bf 8f4f dsb sy
800e04a: b662 cpsie i
800e04c: 60bb str r3, [r7, #8]
800e04e: e7fe b.n 800e04e <xTaskPriorityDisinherit+0x56>
( pxTCB->uxMutexesHeld )--;
800e050: 693b ldr r3, [r7, #16]
800e052: 6c9b ldr r3, [r3, #72] ; 0x48
800e054: 1e5a subs r2, r3, #1
800e056: 693b ldr r3, [r7, #16]
800e058: 649a str r2, [r3, #72] ; 0x48
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
800e05a: 693b ldr r3, [r7, #16]
800e05c: 6ada ldr r2, [r3, #44] ; 0x2c
800e05e: 693b ldr r3, [r7, #16]
800e060: 6c5b ldr r3, [r3, #68] ; 0x44
800e062: 429a cmp r2, r3
800e064: d044 beq.n 800e0f0 <xTaskPriorityDisinherit+0xf8>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
800e066: 693b ldr r3, [r7, #16]
800e068: 6c9b ldr r3, [r3, #72] ; 0x48
800e06a: 2b00 cmp r3, #0
800e06c: d140 bne.n 800e0f0 <xTaskPriorityDisinherit+0xf8>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e06e: 693b ldr r3, [r7, #16]
800e070: 3304 adds r3, #4
800e072: 4618 mov r0, r3
800e074: f7fd ffee bl 800c054 <uxListRemove>
800e078: 4603 mov r3, r0
800e07a: 2b00 cmp r3, #0
800e07c: d115 bne.n 800e0aa <xTaskPriorityDisinherit+0xb2>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800e07e: 693b ldr r3, [r7, #16]
800e080: 6ada ldr r2, [r3, #44] ; 0x2c
800e082: 491f ldr r1, [pc, #124] ; (800e100 <xTaskPriorityDisinherit+0x108>)
800e084: 4613 mov r3, r2
800e086: 009b lsls r3, r3, #2
800e088: 4413 add r3, r2
800e08a: 009b lsls r3, r3, #2
800e08c: 440b add r3, r1
800e08e: 681b ldr r3, [r3, #0]
800e090: 2b00 cmp r3, #0
800e092: d10a bne.n 800e0aa <xTaskPriorityDisinherit+0xb2>
800e094: 693b ldr r3, [r7, #16]
800e096: 6adb ldr r3, [r3, #44] ; 0x2c
800e098: 2201 movs r2, #1
800e09a: fa02 f303 lsl.w r3, r2, r3
800e09e: 43da mvns r2, r3
800e0a0: 4b18 ldr r3, [pc, #96] ; (800e104 <xTaskPriorityDisinherit+0x10c>)
800e0a2: 681b ldr r3, [r3, #0]
800e0a4: 4013 ands r3, r2
800e0a6: 4a17 ldr r2, [pc, #92] ; (800e104 <xTaskPriorityDisinherit+0x10c>)
800e0a8: 6013 str r3, [r2, #0]
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
800e0aa: 693b ldr r3, [r7, #16]
800e0ac: 6c5a ldr r2, [r3, #68] ; 0x44
800e0ae: 693b ldr r3, [r7, #16]
800e0b0: 62da str r2, [r3, #44] ; 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e0b2: 693b ldr r3, [r7, #16]
800e0b4: 6adb ldr r3, [r3, #44] ; 0x2c
800e0b6: f1c3 0207 rsb r2, r3, #7
800e0ba: 693b ldr r3, [r7, #16]
800e0bc: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
800e0be: 693b ldr r3, [r7, #16]
800e0c0: 6adb ldr r3, [r3, #44] ; 0x2c
800e0c2: 2201 movs r2, #1
800e0c4: 409a lsls r2, r3
800e0c6: 4b0f ldr r3, [pc, #60] ; (800e104 <xTaskPriorityDisinherit+0x10c>)
800e0c8: 681b ldr r3, [r3, #0]
800e0ca: 4313 orrs r3, r2
800e0cc: 4a0d ldr r2, [pc, #52] ; (800e104 <xTaskPriorityDisinherit+0x10c>)
800e0ce: 6013 str r3, [r2, #0]
800e0d0: 693b ldr r3, [r7, #16]
800e0d2: 6ada ldr r2, [r3, #44] ; 0x2c
800e0d4: 4613 mov r3, r2
800e0d6: 009b lsls r3, r3, #2
800e0d8: 4413 add r3, r2
800e0da: 009b lsls r3, r3, #2
800e0dc: 4a08 ldr r2, [pc, #32] ; (800e100 <xTaskPriorityDisinherit+0x108>)
800e0de: 441a add r2, r3
800e0e0: 693b ldr r3, [r7, #16]
800e0e2: 3304 adds r3, #4
800e0e4: 4619 mov r1, r3
800e0e6: 4610 mov r0, r2
800e0e8: f7fd ff57 bl 800bf9a <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
800e0ec: 2301 movs r3, #1
800e0ee: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800e0f0: 697b ldr r3, [r7, #20]
}
800e0f2: 4618 mov r0, r3
800e0f4: 3718 adds r7, #24
800e0f6: 46bd mov sp, r7
800e0f8: bd80 pop {r7, pc}
800e0fa: bf00 nop
800e0fc: 2000058c .word 0x2000058c
800e100: 20000590 .word 0x20000590
800e104: 20000694 .word 0x20000694
0800e108 <vTaskPriorityDisinheritAfterTimeout>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
{
800e108: b580 push {r7, lr}
800e10a: b088 sub sp, #32
800e10c: af00 add r7, sp, #0
800e10e: 6078 str r0, [r7, #4]
800e110: 6039 str r1, [r7, #0]
TCB_t * const pxTCB = pxMutexHolder;
800e112: 687b ldr r3, [r7, #4]
800e114: 61bb str r3, [r7, #24]
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
800e116: 2301 movs r3, #1
800e118: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
800e11a: 687b ldr r3, [r7, #4]
800e11c: 2b00 cmp r3, #0
800e11e: f000 8085 beq.w 800e22c <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* If pxMutexHolder is not NULL then the holder must hold at least
one mutex. */
configASSERT( pxTCB->uxMutexesHeld );
800e122: 69bb ldr r3, [r7, #24]
800e124: 6c9b ldr r3, [r3, #72] ; 0x48
800e126: 2b00 cmp r3, #0
800e128: d10b bne.n 800e142 <vTaskPriorityDisinheritAfterTimeout+0x3a>
800e12a: f04f 0350 mov.w r3, #80 ; 0x50
800e12e: b672 cpsid i
800e130: f383 8811 msr BASEPRI, r3
800e134: f3bf 8f6f isb sy
800e138: f3bf 8f4f dsb sy
800e13c: b662 cpsie i
800e13e: 60fb str r3, [r7, #12]
800e140: e7fe b.n 800e140 <vTaskPriorityDisinheritAfterTimeout+0x38>
/* Determine the priority to which the priority of the task that
holds the mutex should be set. This will be the greater of the
holding task's base priority and the priority of the highest
priority task that is waiting to obtain the mutex. */
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
800e142: 69bb ldr r3, [r7, #24]
800e144: 6c5b ldr r3, [r3, #68] ; 0x44
800e146: 683a ldr r2, [r7, #0]
800e148: 429a cmp r2, r3
800e14a: d902 bls.n 800e152 <vTaskPriorityDisinheritAfterTimeout+0x4a>
{
uxPriorityToUse = uxHighestPriorityWaitingTask;
800e14c: 683b ldr r3, [r7, #0]
800e14e: 61fb str r3, [r7, #28]
800e150: e002 b.n 800e158 <vTaskPriorityDisinheritAfterTimeout+0x50>
}
else
{
uxPriorityToUse = pxTCB->uxBasePriority;
800e152: 69bb ldr r3, [r7, #24]
800e154: 6c5b ldr r3, [r3, #68] ; 0x44
800e156: 61fb str r3, [r7, #28]
}
/* Does the priority need to change? */
if( pxTCB->uxPriority != uxPriorityToUse )
800e158: 69bb ldr r3, [r7, #24]
800e15a: 6adb ldr r3, [r3, #44] ; 0x2c
800e15c: 69fa ldr r2, [r7, #28]
800e15e: 429a cmp r2, r3
800e160: d064 beq.n 800e22c <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* Only disinherit if no other mutexes are held. This is a
simplification in the priority inheritance implementation. If
the task that holds the mutex is also holding other mutexes then
the other mutexes may have caused the priority inheritance. */
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
800e162: 69bb ldr r3, [r7, #24]
800e164: 6c9b ldr r3, [r3, #72] ; 0x48
800e166: 697a ldr r2, [r7, #20]
800e168: 429a cmp r2, r3
800e16a: d15f bne.n 800e22c <vTaskPriorityDisinheritAfterTimeout+0x124>
{
/* If a task has timed out because it already holds the
mutex it was trying to obtain then it cannot of inherited
its own priority. */
configASSERT( pxTCB != pxCurrentTCB );
800e16c: 4b31 ldr r3, [pc, #196] ; (800e234 <vTaskPriorityDisinheritAfterTimeout+0x12c>)
800e16e: 681b ldr r3, [r3, #0]
800e170: 69ba ldr r2, [r7, #24]
800e172: 429a cmp r2, r3
800e174: d10b bne.n 800e18e <vTaskPriorityDisinheritAfterTimeout+0x86>
800e176: f04f 0350 mov.w r3, #80 ; 0x50
800e17a: b672 cpsid i
800e17c: f383 8811 msr BASEPRI, r3
800e180: f3bf 8f6f isb sy
800e184: f3bf 8f4f dsb sy
800e188: b662 cpsie i
800e18a: 60bb str r3, [r7, #8]
800e18c: e7fe b.n 800e18c <vTaskPriorityDisinheritAfterTimeout+0x84>
/* Disinherit the priority, remembering the previous
priority to facilitate determining the subject task's
state. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
uxPriorityUsedOnEntry = pxTCB->uxPriority;
800e18e: 69bb ldr r3, [r7, #24]
800e190: 6adb ldr r3, [r3, #44] ; 0x2c
800e192: 613b str r3, [r7, #16]
pxTCB->uxPriority = uxPriorityToUse;
800e194: 69bb ldr r3, [r7, #24]
800e196: 69fa ldr r2, [r7, #28]
800e198: 62da str r2, [r3, #44] ; 0x2c
/* Only reset the event list item value if the value is not
being used for anything else. */
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
800e19a: 69bb ldr r3, [r7, #24]
800e19c: 699b ldr r3, [r3, #24]
800e19e: 2b00 cmp r3, #0
800e1a0: db04 blt.n 800e1ac <vTaskPriorityDisinheritAfterTimeout+0xa4>
{
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800e1a2: 69fb ldr r3, [r7, #28]
800e1a4: f1c3 0207 rsb r2, r3, #7
800e1a8: 69bb ldr r3, [r7, #24]
800e1aa: 619a str r2, [r3, #24]
then the task that holds the mutex could be in either the
Ready, Blocked or Suspended states. Only remove the task
from its current state list if it is in the Ready state as
the task's priority is going to change and there is one
Ready list per priority. */
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
800e1ac: 69bb ldr r3, [r7, #24]
800e1ae: 6959 ldr r1, [r3, #20]
800e1b0: 693a ldr r2, [r7, #16]
800e1b2: 4613 mov r3, r2
800e1b4: 009b lsls r3, r3, #2
800e1b6: 4413 add r3, r2
800e1b8: 009b lsls r3, r3, #2
800e1ba: 4a1f ldr r2, [pc, #124] ; (800e238 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e1bc: 4413 add r3, r2
800e1be: 4299 cmp r1, r3
800e1c0: d134 bne.n 800e22c <vTaskPriorityDisinheritAfterTimeout+0x124>
{
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e1c2: 69bb ldr r3, [r7, #24]
800e1c4: 3304 adds r3, #4
800e1c6: 4618 mov r0, r3
800e1c8: f7fd ff44 bl 800c054 <uxListRemove>
800e1cc: 4603 mov r3, r0
800e1ce: 2b00 cmp r3, #0
800e1d0: d115 bne.n 800e1fe <vTaskPriorityDisinheritAfterTimeout+0xf6>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
800e1d2: 69bb ldr r3, [r7, #24]
800e1d4: 6ada ldr r2, [r3, #44] ; 0x2c
800e1d6: 4918 ldr r1, [pc, #96] ; (800e238 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e1d8: 4613 mov r3, r2
800e1da: 009b lsls r3, r3, #2
800e1dc: 4413 add r3, r2
800e1de: 009b lsls r3, r3, #2
800e1e0: 440b add r3, r1
800e1e2: 681b ldr r3, [r3, #0]
800e1e4: 2b00 cmp r3, #0
800e1e6: d10a bne.n 800e1fe <vTaskPriorityDisinheritAfterTimeout+0xf6>
800e1e8: 69bb ldr r3, [r7, #24]
800e1ea: 6adb ldr r3, [r3, #44] ; 0x2c
800e1ec: 2201 movs r2, #1
800e1ee: fa02 f303 lsl.w r3, r2, r3
800e1f2: 43da mvns r2, r3
800e1f4: 4b11 ldr r3, [pc, #68] ; (800e23c <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e1f6: 681b ldr r3, [r3, #0]
800e1f8: 4013 ands r3, r2
800e1fa: 4a10 ldr r2, [pc, #64] ; (800e23c <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e1fc: 6013 str r3, [r2, #0]
else
{
mtCOVERAGE_TEST_MARKER();
}
prvAddTaskToReadyList( pxTCB );
800e1fe: 69bb ldr r3, [r7, #24]
800e200: 6adb ldr r3, [r3, #44] ; 0x2c
800e202: 2201 movs r2, #1
800e204: 409a lsls r2, r3
800e206: 4b0d ldr r3, [pc, #52] ; (800e23c <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e208: 681b ldr r3, [r3, #0]
800e20a: 4313 orrs r3, r2
800e20c: 4a0b ldr r2, [pc, #44] ; (800e23c <vTaskPriorityDisinheritAfterTimeout+0x134>)
800e20e: 6013 str r3, [r2, #0]
800e210: 69bb ldr r3, [r7, #24]
800e212: 6ada ldr r2, [r3, #44] ; 0x2c
800e214: 4613 mov r3, r2
800e216: 009b lsls r3, r3, #2
800e218: 4413 add r3, r2
800e21a: 009b lsls r3, r3, #2
800e21c: 4a06 ldr r2, [pc, #24] ; (800e238 <vTaskPriorityDisinheritAfterTimeout+0x130>)
800e21e: 441a add r2, r3
800e220: 69bb ldr r3, [r7, #24]
800e222: 3304 adds r3, #4
800e224: 4619 mov r1, r3
800e226: 4610 mov r0, r2
800e228: f7fd feb7 bl 800bf9a <vListInsertEnd>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800e22c: bf00 nop
800e22e: 3720 adds r7, #32
800e230: 46bd mov sp, r7
800e232: bd80 pop {r7, pc}
800e234: 2000058c .word 0x2000058c
800e238: 20000590 .word 0x20000590
800e23c: 20000694 .word 0x20000694
0800e240 <pvTaskIncrementMutexHeldCount>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
{
800e240: b480 push {r7}
800e242: af00 add r7, sp, #0
/* If xSemaphoreCreateMutex() is called before any tasks have been created
then pxCurrentTCB will be NULL. */
if( pxCurrentTCB != NULL )
800e244: 4b07 ldr r3, [pc, #28] ; (800e264 <pvTaskIncrementMutexHeldCount+0x24>)
800e246: 681b ldr r3, [r3, #0]
800e248: 2b00 cmp r3, #0
800e24a: d004 beq.n 800e256 <pvTaskIncrementMutexHeldCount+0x16>
{
( pxCurrentTCB->uxMutexesHeld )++;
800e24c: 4b05 ldr r3, [pc, #20] ; (800e264 <pvTaskIncrementMutexHeldCount+0x24>)
800e24e: 681b ldr r3, [r3, #0]
800e250: 6c9a ldr r2, [r3, #72] ; 0x48
800e252: 3201 adds r2, #1
800e254: 649a str r2, [r3, #72] ; 0x48
}
return pxCurrentTCB;
800e256: 4b03 ldr r3, [pc, #12] ; (800e264 <pvTaskIncrementMutexHeldCount+0x24>)
800e258: 681b ldr r3, [r3, #0]
}
800e25a: 4618 mov r0, r3
800e25c: 46bd mov sp, r7
800e25e: f85d 7b04 ldr.w r7, [sp], #4
800e262: 4770 bx lr
800e264: 2000058c .word 0x2000058c
0800e268 <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
800e268: b580 push {r7, lr}
800e26a: b084 sub sp, #16
800e26c: af00 add r7, sp, #0
800e26e: 6078 str r0, [r7, #4]
800e270: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
800e272: 4b29 ldr r3, [pc, #164] ; (800e318 <prvAddCurrentTaskToDelayedList+0xb0>)
800e274: 681b ldr r3, [r3, #0]
800e276: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800e278: 4b28 ldr r3, [pc, #160] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e27a: 681b ldr r3, [r3, #0]
800e27c: 3304 adds r3, #4
800e27e: 4618 mov r0, r3
800e280: f7fd fee8 bl 800c054 <uxListRemove>
800e284: 4603 mov r3, r0
800e286: 2b00 cmp r3, #0
800e288: d10b bne.n 800e2a2 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
800e28a: 4b24 ldr r3, [pc, #144] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e28c: 681b ldr r3, [r3, #0]
800e28e: 6adb ldr r3, [r3, #44] ; 0x2c
800e290: 2201 movs r2, #1
800e292: fa02 f303 lsl.w r3, r2, r3
800e296: 43da mvns r2, r3
800e298: 4b21 ldr r3, [pc, #132] ; (800e320 <prvAddCurrentTaskToDelayedList+0xb8>)
800e29a: 681b ldr r3, [r3, #0]
800e29c: 4013 ands r3, r2
800e29e: 4a20 ldr r2, [pc, #128] ; (800e320 <prvAddCurrentTaskToDelayedList+0xb8>)
800e2a0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
800e2a2: 687b ldr r3, [r7, #4]
800e2a4: f1b3 3fff cmp.w r3, #4294967295
800e2a8: d10a bne.n 800e2c0 <prvAddCurrentTaskToDelayedList+0x58>
800e2aa: 683b ldr r3, [r7, #0]
800e2ac: 2b00 cmp r3, #0
800e2ae: d007 beq.n 800e2c0 <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2b0: 4b1a ldr r3, [pc, #104] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e2b2: 681b ldr r3, [r3, #0]
800e2b4: 3304 adds r3, #4
800e2b6: 4619 mov r1, r3
800e2b8: 481a ldr r0, [pc, #104] ; (800e324 <prvAddCurrentTaskToDelayedList+0xbc>)
800e2ba: f7fd fe6e bl 800bf9a <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
800e2be: e026 b.n 800e30e <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
800e2c0: 68fa ldr r2, [r7, #12]
800e2c2: 687b ldr r3, [r7, #4]
800e2c4: 4413 add r3, r2
800e2c6: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
800e2c8: 4b14 ldr r3, [pc, #80] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e2ca: 681b ldr r3, [r3, #0]
800e2cc: 68ba ldr r2, [r7, #8]
800e2ce: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
800e2d0: 68ba ldr r2, [r7, #8]
800e2d2: 68fb ldr r3, [r7, #12]
800e2d4: 429a cmp r2, r3
800e2d6: d209 bcs.n 800e2ec <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2d8: 4b13 ldr r3, [pc, #76] ; (800e328 <prvAddCurrentTaskToDelayedList+0xc0>)
800e2da: 681a ldr r2, [r3, #0]
800e2dc: 4b0f ldr r3, [pc, #60] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e2de: 681b ldr r3, [r3, #0]
800e2e0: 3304 adds r3, #4
800e2e2: 4619 mov r1, r3
800e2e4: 4610 mov r0, r2
800e2e6: f7fd fe7c bl 800bfe2 <vListInsert>
}
800e2ea: e010 b.n 800e30e <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800e2ec: 4b0f ldr r3, [pc, #60] ; (800e32c <prvAddCurrentTaskToDelayedList+0xc4>)
800e2ee: 681a ldr r2, [r3, #0]
800e2f0: 4b0a ldr r3, [pc, #40] ; (800e31c <prvAddCurrentTaskToDelayedList+0xb4>)
800e2f2: 681b ldr r3, [r3, #0]
800e2f4: 3304 adds r3, #4
800e2f6: 4619 mov r1, r3
800e2f8: 4610 mov r0, r2
800e2fa: f7fd fe72 bl 800bfe2 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
800e2fe: 4b0c ldr r3, [pc, #48] ; (800e330 <prvAddCurrentTaskToDelayedList+0xc8>)
800e300: 681b ldr r3, [r3, #0]
800e302: 68ba ldr r2, [r7, #8]
800e304: 429a cmp r2, r3
800e306: d202 bcs.n 800e30e <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
800e308: 4a09 ldr r2, [pc, #36] ; (800e330 <prvAddCurrentTaskToDelayedList+0xc8>)
800e30a: 68bb ldr r3, [r7, #8]
800e30c: 6013 str r3, [r2, #0]
}
800e30e: bf00 nop
800e310: 3710 adds r7, #16
800e312: 46bd mov sp, r7
800e314: bd80 pop {r7, pc}
800e316: bf00 nop
800e318: 20000690 .word 0x20000690
800e31c: 2000058c .word 0x2000058c
800e320: 20000694 .word 0x20000694
800e324: 20000678 .word 0x20000678
800e328: 20000648 .word 0x20000648
800e32c: 20000644 .word 0x20000644
800e330: 200006ac .word 0x200006ac
0800e334 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
800e334: b480 push {r7}
800e336: b085 sub sp, #20
800e338: af00 add r7, sp, #0
800e33a: 60f8 str r0, [r7, #12]
800e33c: 60b9 str r1, [r7, #8]
800e33e: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
800e340: 68fb ldr r3, [r7, #12]
800e342: 3b04 subs r3, #4
800e344: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
800e346: 68fb ldr r3, [r7, #12]
800e348: f04f 7280 mov.w r2, #16777216 ; 0x1000000
800e34c: 601a str r2, [r3, #0]
pxTopOfStack--;
800e34e: 68fb ldr r3, [r7, #12]
800e350: 3b04 subs r3, #4
800e352: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
800e354: 68bb ldr r3, [r7, #8]
800e356: f023 0201 bic.w r2, r3, #1
800e35a: 68fb ldr r3, [r7, #12]
800e35c: 601a str r2, [r3, #0]
pxTopOfStack--;
800e35e: 68fb ldr r3, [r7, #12]
800e360: 3b04 subs r3, #4
800e362: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
800e364: 4a0c ldr r2, [pc, #48] ; (800e398 <pxPortInitialiseStack+0x64>)
800e366: 68fb ldr r3, [r7, #12]
800e368: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
800e36a: 68fb ldr r3, [r7, #12]
800e36c: 3b14 subs r3, #20
800e36e: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
800e370: 687a ldr r2, [r7, #4]
800e372: 68fb ldr r3, [r7, #12]
800e374: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
800e376: 68fb ldr r3, [r7, #12]
800e378: 3b04 subs r3, #4
800e37a: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
800e37c: 68fb ldr r3, [r7, #12]
800e37e: f06f 0202 mvn.w r2, #2
800e382: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
800e384: 68fb ldr r3, [r7, #12]
800e386: 3b20 subs r3, #32
800e388: 60fb str r3, [r7, #12]
return pxTopOfStack;
800e38a: 68fb ldr r3, [r7, #12]
}
800e38c: 4618 mov r0, r3
800e38e: 3714 adds r7, #20
800e390: 46bd mov sp, r7
800e392: f85d 7b04 ldr.w r7, [sp], #4
800e396: 4770 bx lr
800e398: 0800e39d .word 0x0800e39d
0800e39c <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
800e39c: b480 push {r7}
800e39e: b085 sub sp, #20
800e3a0: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
800e3a2: 2300 movs r3, #0
800e3a4: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
800e3a6: 4b13 ldr r3, [pc, #76] ; (800e3f4 <prvTaskExitError+0x58>)
800e3a8: 681b ldr r3, [r3, #0]
800e3aa: f1b3 3fff cmp.w r3, #4294967295
800e3ae: d00b beq.n 800e3c8 <prvTaskExitError+0x2c>
800e3b0: f04f 0350 mov.w r3, #80 ; 0x50
800e3b4: b672 cpsid i
800e3b6: f383 8811 msr BASEPRI, r3
800e3ba: f3bf 8f6f isb sy
800e3be: f3bf 8f4f dsb sy
800e3c2: b662 cpsie i
800e3c4: 60fb str r3, [r7, #12]
800e3c6: e7fe b.n 800e3c6 <prvTaskExitError+0x2a>
800e3c8: f04f 0350 mov.w r3, #80 ; 0x50
800e3cc: b672 cpsid i
800e3ce: f383 8811 msr BASEPRI, r3
800e3d2: f3bf 8f6f isb sy
800e3d6: f3bf 8f4f dsb sy
800e3da: b662 cpsie i
800e3dc: 60bb str r3, [r7, #8]
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
800e3de: bf00 nop
800e3e0: 687b ldr r3, [r7, #4]
800e3e2: 2b00 cmp r3, #0
800e3e4: d0fc beq.n 800e3e0 <prvTaskExitError+0x44>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
800e3e6: bf00 nop
800e3e8: 3714 adds r7, #20
800e3ea: 46bd mov sp, r7
800e3ec: f85d 7b04 ldr.w r7, [sp], #4
800e3f0: 4770 bx lr
800e3f2: bf00 nop
800e3f4: 20000070 .word 0x20000070
...
0800e400 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
800e400: 4b07 ldr r3, [pc, #28] ; (800e420 <pxCurrentTCBConst2>)
800e402: 6819 ldr r1, [r3, #0]
800e404: 6808 ldr r0, [r1, #0]
800e406: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e40a: f380 8809 msr PSP, r0
800e40e: f3bf 8f6f isb sy
800e412: f04f 0000 mov.w r0, #0
800e416: f380 8811 msr BASEPRI, r0
800e41a: 4770 bx lr
800e41c: f3af 8000 nop.w
0800e420 <pxCurrentTCBConst2>:
800e420: 2000058c .word 0x2000058c
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
800e424: bf00 nop
800e426: bf00 nop
0800e428 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
800e428: 4808 ldr r0, [pc, #32] ; (800e44c <prvPortStartFirstTask+0x24>)
800e42a: 6800 ldr r0, [r0, #0]
800e42c: 6800 ldr r0, [r0, #0]
800e42e: f380 8808 msr MSP, r0
800e432: f04f 0000 mov.w r0, #0
800e436: f380 8814 msr CONTROL, r0
800e43a: b662 cpsie i
800e43c: b661 cpsie f
800e43e: f3bf 8f4f dsb sy
800e442: f3bf 8f6f isb sy
800e446: df00 svc 0
800e448: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
800e44a: bf00 nop
800e44c: e000ed08 .word 0xe000ed08
0800e450 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
800e450: b580 push {r7, lr}
800e452: b084 sub sp, #16
800e454: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
800e456: 4b36 ldr r3, [pc, #216] ; (800e530 <xPortStartScheduler+0xe0>)
800e458: 60fb str r3, [r7, #12]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
800e45a: 68fb ldr r3, [r7, #12]
800e45c: 781b ldrb r3, [r3, #0]
800e45e: b2db uxtb r3, r3
800e460: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
800e462: 68fb ldr r3, [r7, #12]
800e464: 22ff movs r2, #255 ; 0xff
800e466: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
800e468: 68fb ldr r3, [r7, #12]
800e46a: 781b ldrb r3, [r3, #0]
800e46c: b2db uxtb r3, r3
800e46e: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
800e470: 78fb ldrb r3, [r7, #3]
800e472: b2db uxtb r3, r3
800e474: f003 0350 and.w r3, r3, #80 ; 0x50
800e478: b2da uxtb r2, r3
800e47a: 4b2e ldr r3, [pc, #184] ; (800e534 <xPortStartScheduler+0xe4>)
800e47c: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
800e47e: 4b2e ldr r3, [pc, #184] ; (800e538 <xPortStartScheduler+0xe8>)
800e480: 2207 movs r2, #7
800e482: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e484: e009 b.n 800e49a <xPortStartScheduler+0x4a>
{
ulMaxPRIGROUPValue--;
800e486: 4b2c ldr r3, [pc, #176] ; (800e538 <xPortStartScheduler+0xe8>)
800e488: 681b ldr r3, [r3, #0]
800e48a: 3b01 subs r3, #1
800e48c: 4a2a ldr r2, [pc, #168] ; (800e538 <xPortStartScheduler+0xe8>)
800e48e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
800e490: 78fb ldrb r3, [r7, #3]
800e492: b2db uxtb r3, r3
800e494: 005b lsls r3, r3, #1
800e496: b2db uxtb r3, r3
800e498: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
800e49a: 78fb ldrb r3, [r7, #3]
800e49c: b2db uxtb r3, r3
800e49e: f003 0380 and.w r3, r3, #128 ; 0x80
800e4a2: 2b80 cmp r3, #128 ; 0x80
800e4a4: d0ef beq.n 800e486 <xPortStartScheduler+0x36>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
800e4a6: 4b24 ldr r3, [pc, #144] ; (800e538 <xPortStartScheduler+0xe8>)
800e4a8: 681b ldr r3, [r3, #0]
800e4aa: f1c3 0307 rsb r3, r3, #7
800e4ae: 2b04 cmp r3, #4
800e4b0: d00b beq.n 800e4ca <xPortStartScheduler+0x7a>
800e4b2: f04f 0350 mov.w r3, #80 ; 0x50
800e4b6: b672 cpsid i
800e4b8: f383 8811 msr BASEPRI, r3
800e4bc: f3bf 8f6f isb sy
800e4c0: f3bf 8f4f dsb sy
800e4c4: b662 cpsie i
800e4c6: 60bb str r3, [r7, #8]
800e4c8: e7fe b.n 800e4c8 <xPortStartScheduler+0x78>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
800e4ca: 4b1b ldr r3, [pc, #108] ; (800e538 <xPortStartScheduler+0xe8>)
800e4cc: 681b ldr r3, [r3, #0]
800e4ce: 021b lsls r3, r3, #8
800e4d0: 4a19 ldr r2, [pc, #100] ; (800e538 <xPortStartScheduler+0xe8>)
800e4d2: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
800e4d4: 4b18 ldr r3, [pc, #96] ; (800e538 <xPortStartScheduler+0xe8>)
800e4d6: 681b ldr r3, [r3, #0]
800e4d8: f403 63e0 and.w r3, r3, #1792 ; 0x700
800e4dc: 4a16 ldr r2, [pc, #88] ; (800e538 <xPortStartScheduler+0xe8>)
800e4de: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
800e4e0: 687b ldr r3, [r7, #4]
800e4e2: b2da uxtb r2, r3
800e4e4: 68fb ldr r3, [r7, #12]
800e4e6: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
800e4e8: 4b14 ldr r3, [pc, #80] ; (800e53c <xPortStartScheduler+0xec>)
800e4ea: 681b ldr r3, [r3, #0]
800e4ec: 4a13 ldr r2, [pc, #76] ; (800e53c <xPortStartScheduler+0xec>)
800e4ee: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
800e4f2: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
800e4f4: 4b11 ldr r3, [pc, #68] ; (800e53c <xPortStartScheduler+0xec>)
800e4f6: 681b ldr r3, [r3, #0]
800e4f8: 4a10 ldr r2, [pc, #64] ; (800e53c <xPortStartScheduler+0xec>)
800e4fa: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
800e4fe: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
800e500: f000 f8d4 bl 800e6ac <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
800e504: 4b0e ldr r3, [pc, #56] ; (800e540 <xPortStartScheduler+0xf0>)
800e506: 2200 movs r2, #0
800e508: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
800e50a: f000 f8f3 bl 800e6f4 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
800e50e: 4b0d ldr r3, [pc, #52] ; (800e544 <xPortStartScheduler+0xf4>)
800e510: 681b ldr r3, [r3, #0]
800e512: 4a0c ldr r2, [pc, #48] ; (800e544 <xPortStartScheduler+0xf4>)
800e514: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
800e518: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
800e51a: f7ff ff85 bl 800e428 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
800e51e: f7ff fa65 bl 800d9ec <vTaskSwitchContext>
prvTaskExitError();
800e522: f7ff ff3b bl 800e39c <prvTaskExitError>
/* Should not get here! */
return 0;
800e526: 2300 movs r3, #0
}
800e528: 4618 mov r0, r3
800e52a: 3710 adds r7, #16
800e52c: 46bd mov sp, r7
800e52e: bd80 pop {r7, pc}
800e530: e000e400 .word 0xe000e400
800e534: 200006b8 .word 0x200006b8
800e538: 200006bc .word 0x200006bc
800e53c: e000ed20 .word 0xe000ed20
800e540: 20000070 .word 0x20000070
800e544: e000ef34 .word 0xe000ef34
0800e548 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
800e548: b480 push {r7}
800e54a: b083 sub sp, #12
800e54c: af00 add r7, sp, #0
800e54e: f04f 0350 mov.w r3, #80 ; 0x50
800e552: b672 cpsid i
800e554: f383 8811 msr BASEPRI, r3
800e558: f3bf 8f6f isb sy
800e55c: f3bf 8f4f dsb sy
800e560: b662 cpsie i
800e562: 607b str r3, [r7, #4]
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
800e564: 4b0f ldr r3, [pc, #60] ; (800e5a4 <vPortEnterCritical+0x5c>)
800e566: 681b ldr r3, [r3, #0]
800e568: 3301 adds r3, #1
800e56a: 4a0e ldr r2, [pc, #56] ; (800e5a4 <vPortEnterCritical+0x5c>)
800e56c: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
800e56e: 4b0d ldr r3, [pc, #52] ; (800e5a4 <vPortEnterCritical+0x5c>)
800e570: 681b ldr r3, [r3, #0]
800e572: 2b01 cmp r3, #1
800e574: d110 bne.n 800e598 <vPortEnterCritical+0x50>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
800e576: 4b0c ldr r3, [pc, #48] ; (800e5a8 <vPortEnterCritical+0x60>)
800e578: 681b ldr r3, [r3, #0]
800e57a: b2db uxtb r3, r3
800e57c: 2b00 cmp r3, #0
800e57e: d00b beq.n 800e598 <vPortEnterCritical+0x50>
800e580: f04f 0350 mov.w r3, #80 ; 0x50
800e584: b672 cpsid i
800e586: f383 8811 msr BASEPRI, r3
800e58a: f3bf 8f6f isb sy
800e58e: f3bf 8f4f dsb sy
800e592: b662 cpsie i
800e594: 603b str r3, [r7, #0]
800e596: e7fe b.n 800e596 <vPortEnterCritical+0x4e>
}
}
800e598: bf00 nop
800e59a: 370c adds r7, #12
800e59c: 46bd mov sp, r7
800e59e: f85d 7b04 ldr.w r7, [sp], #4
800e5a2: 4770 bx lr
800e5a4: 20000070 .word 0x20000070
800e5a8: e000ed04 .word 0xe000ed04
0800e5ac <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
800e5ac: b480 push {r7}
800e5ae: b083 sub sp, #12
800e5b0: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800e5b2: 4b12 ldr r3, [pc, #72] ; (800e5fc <vPortExitCritical+0x50>)
800e5b4: 681b ldr r3, [r3, #0]
800e5b6: 2b00 cmp r3, #0
800e5b8: d10b bne.n 800e5d2 <vPortExitCritical+0x26>
800e5ba: f04f 0350 mov.w r3, #80 ; 0x50
800e5be: b672 cpsid i
800e5c0: f383 8811 msr BASEPRI, r3
800e5c4: f3bf 8f6f isb sy
800e5c8: f3bf 8f4f dsb sy
800e5cc: b662 cpsie i
800e5ce: 607b str r3, [r7, #4]
800e5d0: e7fe b.n 800e5d0 <vPortExitCritical+0x24>
uxCriticalNesting--;
800e5d2: 4b0a ldr r3, [pc, #40] ; (800e5fc <vPortExitCritical+0x50>)
800e5d4: 681b ldr r3, [r3, #0]
800e5d6: 3b01 subs r3, #1
800e5d8: 4a08 ldr r2, [pc, #32] ; (800e5fc <vPortExitCritical+0x50>)
800e5da: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
800e5dc: 4b07 ldr r3, [pc, #28] ; (800e5fc <vPortExitCritical+0x50>)
800e5de: 681b ldr r3, [r3, #0]
800e5e0: 2b00 cmp r3, #0
800e5e2: d104 bne.n 800e5ee <vPortExitCritical+0x42>
800e5e4: 2300 movs r3, #0
800e5e6: 603b str r3, [r7, #0]
__asm volatile
800e5e8: 683b ldr r3, [r7, #0]
800e5ea: f383 8811 msr BASEPRI, r3
{
portENABLE_INTERRUPTS();
}
}
800e5ee: bf00 nop
800e5f0: 370c adds r7, #12
800e5f2: 46bd mov sp, r7
800e5f4: f85d 7b04 ldr.w r7, [sp], #4
800e5f8: 4770 bx lr
800e5fa: bf00 nop
800e5fc: 20000070 .word 0x20000070
0800e600 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
800e600: f3ef 8009 mrs r0, PSP
800e604: f3bf 8f6f isb sy
800e608: 4b15 ldr r3, [pc, #84] ; (800e660 <pxCurrentTCBConst>)
800e60a: 681a ldr r2, [r3, #0]
800e60c: f01e 0f10 tst.w lr, #16
800e610: bf08 it eq
800e612: ed20 8a10 vstmdbeq r0!, {s16-s31}
800e616: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e61a: 6010 str r0, [r2, #0]
800e61c: e92d 0009 stmdb sp!, {r0, r3}
800e620: f04f 0050 mov.w r0, #80 ; 0x50
800e624: b672 cpsid i
800e626: f380 8811 msr BASEPRI, r0
800e62a: f3bf 8f4f dsb sy
800e62e: f3bf 8f6f isb sy
800e632: b662 cpsie i
800e634: f7ff f9da bl 800d9ec <vTaskSwitchContext>
800e638: f04f 0000 mov.w r0, #0
800e63c: f380 8811 msr BASEPRI, r0
800e640: bc09 pop {r0, r3}
800e642: 6819 ldr r1, [r3, #0]
800e644: 6808 ldr r0, [r1, #0]
800e646: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800e64a: f01e 0f10 tst.w lr, #16
800e64e: bf08 it eq
800e650: ecb0 8a10 vldmiaeq r0!, {s16-s31}
800e654: f380 8809 msr PSP, r0
800e658: f3bf 8f6f isb sy
800e65c: 4770 bx lr
800e65e: bf00 nop
0800e660 <pxCurrentTCBConst>:
800e660: 2000058c .word 0x2000058c
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
800e664: bf00 nop
800e666: bf00 nop
0800e668 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
800e668: b580 push {r7, lr}
800e66a: b082 sub sp, #8
800e66c: af00 add r7, sp, #0
__asm volatile
800e66e: f04f 0350 mov.w r3, #80 ; 0x50
800e672: b672 cpsid i
800e674: f383 8811 msr BASEPRI, r3
800e678: f3bf 8f6f isb sy
800e67c: f3bf 8f4f dsb sy
800e680: b662 cpsie i
800e682: 607b str r3, [r7, #4]
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
800e684: f7ff f8f8 bl 800d878 <xTaskIncrementTick>
800e688: 4603 mov r3, r0
800e68a: 2b00 cmp r3, #0
800e68c: d003 beq.n 800e696 <SysTick_Handler+0x2e>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
800e68e: 4b06 ldr r3, [pc, #24] ; (800e6a8 <SysTick_Handler+0x40>)
800e690: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800e694: 601a str r2, [r3, #0]
800e696: 2300 movs r3, #0
800e698: 603b str r3, [r7, #0]
__asm volatile
800e69a: 683b ldr r3, [r7, #0]
800e69c: f383 8811 msr BASEPRI, r3
}
}
portENABLE_INTERRUPTS();
}
800e6a0: bf00 nop
800e6a2: 3708 adds r7, #8
800e6a4: 46bd mov sp, r7
800e6a6: bd80 pop {r7, pc}
800e6a8: e000ed04 .word 0xe000ed04
0800e6ac <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
800e6ac: b480 push {r7}
800e6ae: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
800e6b0: 4b0b ldr r3, [pc, #44] ; (800e6e0 <vPortSetupTimerInterrupt+0x34>)
800e6b2: 2200 movs r2, #0
800e6b4: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
800e6b6: 4b0b ldr r3, [pc, #44] ; (800e6e4 <vPortSetupTimerInterrupt+0x38>)
800e6b8: 2200 movs r2, #0
800e6ba: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
800e6bc: 4b0a ldr r3, [pc, #40] ; (800e6e8 <vPortSetupTimerInterrupt+0x3c>)
800e6be: 681b ldr r3, [r3, #0]
800e6c0: 4a0a ldr r2, [pc, #40] ; (800e6ec <vPortSetupTimerInterrupt+0x40>)
800e6c2: fba2 2303 umull r2, r3, r2, r3
800e6c6: 099b lsrs r3, r3, #6
800e6c8: 4a09 ldr r2, [pc, #36] ; (800e6f0 <vPortSetupTimerInterrupt+0x44>)
800e6ca: 3b01 subs r3, #1
800e6cc: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
800e6ce: 4b04 ldr r3, [pc, #16] ; (800e6e0 <vPortSetupTimerInterrupt+0x34>)
800e6d0: 2207 movs r2, #7
800e6d2: 601a str r2, [r3, #0]
}
800e6d4: bf00 nop
800e6d6: 46bd mov sp, r7
800e6d8: f85d 7b04 ldr.w r7, [sp], #4
800e6dc: 4770 bx lr
800e6de: bf00 nop
800e6e0: e000e010 .word 0xe000e010
800e6e4: e000e018 .word 0xe000e018
800e6e8: 20000064 .word 0x20000064
800e6ec: 10624dd3 .word 0x10624dd3
800e6f0: e000e014 .word 0xe000e014
0800e6f4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
800e6f4: f8df 000c ldr.w r0, [pc, #12] ; 800e704 <vPortEnableVFP+0x10>
800e6f8: 6801 ldr r1, [r0, #0]
800e6fa: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
800e6fe: 6001 str r1, [r0, #0]
800e700: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
800e702: bf00 nop
800e704: e000ed88 .word 0xe000ed88
0800e708 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
800e708: b480 push {r7}
800e70a: b085 sub sp, #20
800e70c: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
800e70e: f3ef 8305 mrs r3, IPSR
800e712: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
800e714: 68fb ldr r3, [r7, #12]
800e716: 2b0f cmp r3, #15
800e718: d915 bls.n 800e746 <vPortValidateInterruptPriority+0x3e>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
800e71a: 4a18 ldr r2, [pc, #96] ; (800e77c <vPortValidateInterruptPriority+0x74>)
800e71c: 68fb ldr r3, [r7, #12]
800e71e: 4413 add r3, r2
800e720: 781b ldrb r3, [r3, #0]
800e722: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
800e724: 4b16 ldr r3, [pc, #88] ; (800e780 <vPortValidateInterruptPriority+0x78>)
800e726: 781b ldrb r3, [r3, #0]
800e728: 7afa ldrb r2, [r7, #11]
800e72a: 429a cmp r2, r3
800e72c: d20b bcs.n 800e746 <vPortValidateInterruptPriority+0x3e>
__asm volatile
800e72e: f04f 0350 mov.w r3, #80 ; 0x50
800e732: b672 cpsid i
800e734: f383 8811 msr BASEPRI, r3
800e738: f3bf 8f6f isb sy
800e73c: f3bf 8f4f dsb sy
800e740: b662 cpsie i
800e742: 607b str r3, [r7, #4]
800e744: e7fe b.n 800e744 <vPortValidateInterruptPriority+0x3c>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
800e746: 4b0f ldr r3, [pc, #60] ; (800e784 <vPortValidateInterruptPriority+0x7c>)
800e748: 681b ldr r3, [r3, #0]
800e74a: f403 62e0 and.w r2, r3, #1792 ; 0x700
800e74e: 4b0e ldr r3, [pc, #56] ; (800e788 <vPortValidateInterruptPriority+0x80>)
800e750: 681b ldr r3, [r3, #0]
800e752: 429a cmp r2, r3
800e754: d90b bls.n 800e76e <vPortValidateInterruptPriority+0x66>
800e756: f04f 0350 mov.w r3, #80 ; 0x50
800e75a: b672 cpsid i
800e75c: f383 8811 msr BASEPRI, r3
800e760: f3bf 8f6f isb sy
800e764: f3bf 8f4f dsb sy
800e768: b662 cpsie i
800e76a: 603b str r3, [r7, #0]
800e76c: e7fe b.n 800e76c <vPortValidateInterruptPriority+0x64>
}
800e76e: bf00 nop
800e770: 3714 adds r7, #20
800e772: 46bd mov sp, r7
800e774: f85d 7b04 ldr.w r7, [sp], #4
800e778: 4770 bx lr
800e77a: bf00 nop
800e77c: e000e3f0 .word 0xe000e3f0
800e780: 200006b8 .word 0x200006b8
800e784: e000ed0c .word 0xe000ed0c
800e788: 200006bc .word 0x200006bc
0800e78c <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
800e78c: b580 push {r7, lr}
800e78e: b08a sub sp, #40 ; 0x28
800e790: af00 add r7, sp, #0
800e792: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
800e794: 2300 movs r3, #0
800e796: 61fb str r3, [r7, #28]
vTaskSuspendAll();
800e798: f7fe ffa0 bl 800d6dc <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
800e79c: 4b5c ldr r3, [pc, #368] ; (800e910 <pvPortMalloc+0x184>)
800e79e: 681b ldr r3, [r3, #0]
800e7a0: 2b00 cmp r3, #0
800e7a2: d101 bne.n 800e7a8 <pvPortMalloc+0x1c>
{
prvHeapInit();
800e7a4: f000 f91a bl 800e9dc <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
800e7a8: 4b5a ldr r3, [pc, #360] ; (800e914 <pvPortMalloc+0x188>)
800e7aa: 681a ldr r2, [r3, #0]
800e7ac: 687b ldr r3, [r7, #4]
800e7ae: 4013 ands r3, r2
800e7b0: 2b00 cmp r3, #0
800e7b2: f040 8090 bne.w 800e8d6 <pvPortMalloc+0x14a>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
800e7b6: 687b ldr r3, [r7, #4]
800e7b8: 2b00 cmp r3, #0
800e7ba: d01e beq.n 800e7fa <pvPortMalloc+0x6e>
{
xWantedSize += xHeapStructSize;
800e7bc: 2208 movs r2, #8
800e7be: 687b ldr r3, [r7, #4]
800e7c0: 4413 add r3, r2
800e7c2: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
800e7c4: 687b ldr r3, [r7, #4]
800e7c6: f003 0307 and.w r3, r3, #7
800e7ca: 2b00 cmp r3, #0
800e7cc: d015 beq.n 800e7fa <pvPortMalloc+0x6e>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800e7ce: 687b ldr r3, [r7, #4]
800e7d0: f023 0307 bic.w r3, r3, #7
800e7d4: 3308 adds r3, #8
800e7d6: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
800e7d8: 687b ldr r3, [r7, #4]
800e7da: f003 0307 and.w r3, r3, #7
800e7de: 2b00 cmp r3, #0
800e7e0: d00b beq.n 800e7fa <pvPortMalloc+0x6e>
800e7e2: f04f 0350 mov.w r3, #80 ; 0x50
800e7e6: b672 cpsid i
800e7e8: f383 8811 msr BASEPRI, r3
800e7ec: f3bf 8f6f isb sy
800e7f0: f3bf 8f4f dsb sy
800e7f4: b662 cpsie i
800e7f6: 617b str r3, [r7, #20]
800e7f8: e7fe b.n 800e7f8 <pvPortMalloc+0x6c>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800e7fa: 687b ldr r3, [r7, #4]
800e7fc: 2b00 cmp r3, #0
800e7fe: d06a beq.n 800e8d6 <pvPortMalloc+0x14a>
800e800: 4b45 ldr r3, [pc, #276] ; (800e918 <pvPortMalloc+0x18c>)
800e802: 681b ldr r3, [r3, #0]
800e804: 687a ldr r2, [r7, #4]
800e806: 429a cmp r2, r3
800e808: d865 bhi.n 800e8d6 <pvPortMalloc+0x14a>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800e80a: 4b44 ldr r3, [pc, #272] ; (800e91c <pvPortMalloc+0x190>)
800e80c: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
800e80e: 4b43 ldr r3, [pc, #268] ; (800e91c <pvPortMalloc+0x190>)
800e810: 681b ldr r3, [r3, #0]
800e812: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e814: e004 b.n 800e820 <pvPortMalloc+0x94>
{
pxPreviousBlock = pxBlock;
800e816: 6a7b ldr r3, [r7, #36] ; 0x24
800e818: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
800e81a: 6a7b ldr r3, [r7, #36] ; 0x24
800e81c: 681b ldr r3, [r3, #0]
800e81e: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800e820: 6a7b ldr r3, [r7, #36] ; 0x24
800e822: 685b ldr r3, [r3, #4]
800e824: 687a ldr r2, [r7, #4]
800e826: 429a cmp r2, r3
800e828: d903 bls.n 800e832 <pvPortMalloc+0xa6>
800e82a: 6a7b ldr r3, [r7, #36] ; 0x24
800e82c: 681b ldr r3, [r3, #0]
800e82e: 2b00 cmp r3, #0
800e830: d1f1 bne.n 800e816 <pvPortMalloc+0x8a>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800e832: 4b37 ldr r3, [pc, #220] ; (800e910 <pvPortMalloc+0x184>)
800e834: 681b ldr r3, [r3, #0]
800e836: 6a7a ldr r2, [r7, #36] ; 0x24
800e838: 429a cmp r2, r3
800e83a: d04c beq.n 800e8d6 <pvPortMalloc+0x14a>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
800e83c: 6a3b ldr r3, [r7, #32]
800e83e: 681b ldr r3, [r3, #0]
800e840: 2208 movs r2, #8
800e842: 4413 add r3, r2
800e844: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
800e846: 6a7b ldr r3, [r7, #36] ; 0x24
800e848: 681a ldr r2, [r3, #0]
800e84a: 6a3b ldr r3, [r7, #32]
800e84c: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
800e84e: 6a7b ldr r3, [r7, #36] ; 0x24
800e850: 685a ldr r2, [r3, #4]
800e852: 687b ldr r3, [r7, #4]
800e854: 1ad2 subs r2, r2, r3
800e856: 2308 movs r3, #8
800e858: 005b lsls r3, r3, #1
800e85a: 429a cmp r2, r3
800e85c: d920 bls.n 800e8a0 <pvPortMalloc+0x114>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
800e85e: 6a7a ldr r2, [r7, #36] ; 0x24
800e860: 687b ldr r3, [r7, #4]
800e862: 4413 add r3, r2
800e864: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
800e866: 69bb ldr r3, [r7, #24]
800e868: f003 0307 and.w r3, r3, #7
800e86c: 2b00 cmp r3, #0
800e86e: d00b beq.n 800e888 <pvPortMalloc+0xfc>
800e870: f04f 0350 mov.w r3, #80 ; 0x50
800e874: b672 cpsid i
800e876: f383 8811 msr BASEPRI, r3
800e87a: f3bf 8f6f isb sy
800e87e: f3bf 8f4f dsb sy
800e882: b662 cpsie i
800e884: 613b str r3, [r7, #16]
800e886: e7fe b.n 800e886 <pvPortMalloc+0xfa>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
800e888: 6a7b ldr r3, [r7, #36] ; 0x24
800e88a: 685a ldr r2, [r3, #4]
800e88c: 687b ldr r3, [r7, #4]
800e88e: 1ad2 subs r2, r2, r3
800e890: 69bb ldr r3, [r7, #24]
800e892: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800e894: 6a7b ldr r3, [r7, #36] ; 0x24
800e896: 687a ldr r2, [r7, #4]
800e898: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
800e89a: 69b8 ldr r0, [r7, #24]
800e89c: f000 f900 bl 800eaa0 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
800e8a0: 4b1d ldr r3, [pc, #116] ; (800e918 <pvPortMalloc+0x18c>)
800e8a2: 681a ldr r2, [r3, #0]
800e8a4: 6a7b ldr r3, [r7, #36] ; 0x24
800e8a6: 685b ldr r3, [r3, #4]
800e8a8: 1ad3 subs r3, r2, r3
800e8aa: 4a1b ldr r2, [pc, #108] ; (800e918 <pvPortMalloc+0x18c>)
800e8ac: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
800e8ae: 4b1a ldr r3, [pc, #104] ; (800e918 <pvPortMalloc+0x18c>)
800e8b0: 681a ldr r2, [r3, #0]
800e8b2: 4b1b ldr r3, [pc, #108] ; (800e920 <pvPortMalloc+0x194>)
800e8b4: 681b ldr r3, [r3, #0]
800e8b6: 429a cmp r2, r3
800e8b8: d203 bcs.n 800e8c2 <pvPortMalloc+0x136>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
800e8ba: 4b17 ldr r3, [pc, #92] ; (800e918 <pvPortMalloc+0x18c>)
800e8bc: 681b ldr r3, [r3, #0]
800e8be: 4a18 ldr r2, [pc, #96] ; (800e920 <pvPortMalloc+0x194>)
800e8c0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800e8c2: 6a7b ldr r3, [r7, #36] ; 0x24
800e8c4: 685a ldr r2, [r3, #4]
800e8c6: 4b13 ldr r3, [pc, #76] ; (800e914 <pvPortMalloc+0x188>)
800e8c8: 681b ldr r3, [r3, #0]
800e8ca: 431a orrs r2, r3
800e8cc: 6a7b ldr r3, [r7, #36] ; 0x24
800e8ce: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
800e8d0: 6a7b ldr r3, [r7, #36] ; 0x24
800e8d2: 2200 movs r2, #0
800e8d4: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800e8d6: f7fe ff0f bl 800d6f8 <xTaskResumeAll>
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
{
if( pvReturn == NULL )
800e8da: 69fb ldr r3, [r7, #28]
800e8dc: 2b00 cmp r3, #0
800e8de: d101 bne.n 800e8e4 <pvPortMalloc+0x158>
{
extern void vApplicationMallocFailedHook( void );
vApplicationMallocFailedHook();
800e8e0: f7f1 fe78 bl 80005d4 <vApplicationMallocFailedHook>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
800e8e4: 69fb ldr r3, [r7, #28]
800e8e6: f003 0307 and.w r3, r3, #7
800e8ea: 2b00 cmp r3, #0
800e8ec: d00b beq.n 800e906 <pvPortMalloc+0x17a>
800e8ee: f04f 0350 mov.w r3, #80 ; 0x50
800e8f2: b672 cpsid i
800e8f4: f383 8811 msr BASEPRI, r3
800e8f8: f3bf 8f6f isb sy
800e8fc: f3bf 8f4f dsb sy
800e900: b662 cpsie i
800e902: 60fb str r3, [r7, #12]
800e904: e7fe b.n 800e904 <pvPortMalloc+0x178>
return pvReturn;
800e906: 69fb ldr r3, [r7, #28]
}
800e908: 4618 mov r0, r3
800e90a: 3728 adds r7, #40 ; 0x28
800e90c: 46bd mov sp, r7
800e90e: bd80 pop {r7, pc}
800e910: 200086c8 .word 0x200086c8
800e914: 200086d4 .word 0x200086d4
800e918: 200086cc .word 0x200086cc
800e91c: 200086c0 .word 0x200086c0
800e920: 200086d0 .word 0x200086d0
0800e924 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
800e924: b580 push {r7, lr}
800e926: b086 sub sp, #24
800e928: af00 add r7, sp, #0
800e92a: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
800e92c: 687b ldr r3, [r7, #4]
800e92e: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800e930: 687b ldr r3, [r7, #4]
800e932: 2b00 cmp r3, #0
800e934: d04a beq.n 800e9cc <vPortFree+0xa8>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
800e936: 2308 movs r3, #8
800e938: 425b negs r3, r3
800e93a: 697a ldr r2, [r7, #20]
800e93c: 4413 add r3, r2
800e93e: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800e940: 697b ldr r3, [r7, #20]
800e942: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
800e944: 693b ldr r3, [r7, #16]
800e946: 685a ldr r2, [r3, #4]
800e948: 4b22 ldr r3, [pc, #136] ; (800e9d4 <vPortFree+0xb0>)
800e94a: 681b ldr r3, [r3, #0]
800e94c: 4013 ands r3, r2
800e94e: 2b00 cmp r3, #0
800e950: d10b bne.n 800e96a <vPortFree+0x46>
800e952: f04f 0350 mov.w r3, #80 ; 0x50
800e956: b672 cpsid i
800e958: f383 8811 msr BASEPRI, r3
800e95c: f3bf 8f6f isb sy
800e960: f3bf 8f4f dsb sy
800e964: b662 cpsie i
800e966: 60fb str r3, [r7, #12]
800e968: e7fe b.n 800e968 <vPortFree+0x44>
configASSERT( pxLink->pxNextFreeBlock == NULL );
800e96a: 693b ldr r3, [r7, #16]
800e96c: 681b ldr r3, [r3, #0]
800e96e: 2b00 cmp r3, #0
800e970: d00b beq.n 800e98a <vPortFree+0x66>
800e972: f04f 0350 mov.w r3, #80 ; 0x50
800e976: b672 cpsid i
800e978: f383 8811 msr BASEPRI, r3
800e97c: f3bf 8f6f isb sy
800e980: f3bf 8f4f dsb sy
800e984: b662 cpsie i
800e986: 60bb str r3, [r7, #8]
800e988: e7fe b.n 800e988 <vPortFree+0x64>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
800e98a: 693b ldr r3, [r7, #16]
800e98c: 685a ldr r2, [r3, #4]
800e98e: 4b11 ldr r3, [pc, #68] ; (800e9d4 <vPortFree+0xb0>)
800e990: 681b ldr r3, [r3, #0]
800e992: 4013 ands r3, r2
800e994: 2b00 cmp r3, #0
800e996: d019 beq.n 800e9cc <vPortFree+0xa8>
{
if( pxLink->pxNextFreeBlock == NULL )
800e998: 693b ldr r3, [r7, #16]
800e99a: 681b ldr r3, [r3, #0]
800e99c: 2b00 cmp r3, #0
800e99e: d115 bne.n 800e9cc <vPortFree+0xa8>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
800e9a0: 693b ldr r3, [r7, #16]
800e9a2: 685a ldr r2, [r3, #4]
800e9a4: 4b0b ldr r3, [pc, #44] ; (800e9d4 <vPortFree+0xb0>)
800e9a6: 681b ldr r3, [r3, #0]
800e9a8: 43db mvns r3, r3
800e9aa: 401a ands r2, r3
800e9ac: 693b ldr r3, [r7, #16]
800e9ae: 605a str r2, [r3, #4]
vTaskSuspendAll();
800e9b0: f7fe fe94 bl 800d6dc <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800e9b4: 693b ldr r3, [r7, #16]
800e9b6: 685a ldr r2, [r3, #4]
800e9b8: 4b07 ldr r3, [pc, #28] ; (800e9d8 <vPortFree+0xb4>)
800e9ba: 681b ldr r3, [r3, #0]
800e9bc: 4413 add r3, r2
800e9be: 4a06 ldr r2, [pc, #24] ; (800e9d8 <vPortFree+0xb4>)
800e9c0: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800e9c2: 6938 ldr r0, [r7, #16]
800e9c4: f000 f86c bl 800eaa0 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
800e9c8: f7fe fe96 bl 800d6f8 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800e9cc: bf00 nop
800e9ce: 3718 adds r7, #24
800e9d0: 46bd mov sp, r7
800e9d2: bd80 pop {r7, pc}
800e9d4: 200086d4 .word 0x200086d4
800e9d8: 200086cc .word 0x200086cc
0800e9dc <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
800e9dc: b480 push {r7}
800e9de: b085 sub sp, #20
800e9e0: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
800e9e2: f44f 4300 mov.w r3, #32768 ; 0x8000
800e9e6: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
800e9e8: 4b27 ldr r3, [pc, #156] ; (800ea88 <prvHeapInit+0xac>)
800e9ea: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
800e9ec: 68fb ldr r3, [r7, #12]
800e9ee: f003 0307 and.w r3, r3, #7
800e9f2: 2b00 cmp r3, #0
800e9f4: d00c beq.n 800ea10 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800e9f6: 68fb ldr r3, [r7, #12]
800e9f8: 3307 adds r3, #7
800e9fa: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800e9fc: 68fb ldr r3, [r7, #12]
800e9fe: f023 0307 bic.w r3, r3, #7
800ea02: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800ea04: 68ba ldr r2, [r7, #8]
800ea06: 68fb ldr r3, [r7, #12]
800ea08: 1ad3 subs r3, r2, r3
800ea0a: 4a1f ldr r2, [pc, #124] ; (800ea88 <prvHeapInit+0xac>)
800ea0c: 4413 add r3, r2
800ea0e: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
800ea10: 68fb ldr r3, [r7, #12]
800ea12: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
800ea14: 4a1d ldr r2, [pc, #116] ; (800ea8c <prvHeapInit+0xb0>)
800ea16: 687b ldr r3, [r7, #4]
800ea18: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
800ea1a: 4b1c ldr r3, [pc, #112] ; (800ea8c <prvHeapInit+0xb0>)
800ea1c: 2200 movs r2, #0
800ea1e: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
800ea20: 687b ldr r3, [r7, #4]
800ea22: 68ba ldr r2, [r7, #8]
800ea24: 4413 add r3, r2
800ea26: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
800ea28: 2208 movs r2, #8
800ea2a: 68fb ldr r3, [r7, #12]
800ea2c: 1a9b subs r3, r3, r2
800ea2e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800ea30: 68fb ldr r3, [r7, #12]
800ea32: f023 0307 bic.w r3, r3, #7
800ea36: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
800ea38: 68fb ldr r3, [r7, #12]
800ea3a: 4a15 ldr r2, [pc, #84] ; (800ea90 <prvHeapInit+0xb4>)
800ea3c: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
800ea3e: 4b14 ldr r3, [pc, #80] ; (800ea90 <prvHeapInit+0xb4>)
800ea40: 681b ldr r3, [r3, #0]
800ea42: 2200 movs r2, #0
800ea44: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800ea46: 4b12 ldr r3, [pc, #72] ; (800ea90 <prvHeapInit+0xb4>)
800ea48: 681b ldr r3, [r3, #0]
800ea4a: 2200 movs r2, #0
800ea4c: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
800ea4e: 687b ldr r3, [r7, #4]
800ea50: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800ea52: 683b ldr r3, [r7, #0]
800ea54: 68fa ldr r2, [r7, #12]
800ea56: 1ad2 subs r2, r2, r3
800ea58: 683b ldr r3, [r7, #0]
800ea5a: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
800ea5c: 4b0c ldr r3, [pc, #48] ; (800ea90 <prvHeapInit+0xb4>)
800ea5e: 681a ldr r2, [r3, #0]
800ea60: 683b ldr r3, [r7, #0]
800ea62: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea64: 683b ldr r3, [r7, #0]
800ea66: 685b ldr r3, [r3, #4]
800ea68: 4a0a ldr r2, [pc, #40] ; (800ea94 <prvHeapInit+0xb8>)
800ea6a: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ea6c: 683b ldr r3, [r7, #0]
800ea6e: 685b ldr r3, [r3, #4]
800ea70: 4a09 ldr r2, [pc, #36] ; (800ea98 <prvHeapInit+0xbc>)
800ea72: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800ea74: 4b09 ldr r3, [pc, #36] ; (800ea9c <prvHeapInit+0xc0>)
800ea76: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
800ea7a: 601a str r2, [r3, #0]
}
800ea7c: bf00 nop
800ea7e: 3714 adds r7, #20
800ea80: 46bd mov sp, r7
800ea82: f85d 7b04 ldr.w r7, [sp], #4
800ea86: 4770 bx lr
800ea88: 200006c0 .word 0x200006c0
800ea8c: 200086c0 .word 0x200086c0
800ea90: 200086c8 .word 0x200086c8
800ea94: 200086d0 .word 0x200086d0
800ea98: 200086cc .word 0x200086cc
800ea9c: 200086d4 .word 0x200086d4
0800eaa0 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
800eaa0: b480 push {r7}
800eaa2: b085 sub sp, #20
800eaa4: af00 add r7, sp, #0
800eaa6: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
800eaa8: 4b28 ldr r3, [pc, #160] ; (800eb4c <prvInsertBlockIntoFreeList+0xac>)
800eaaa: 60fb str r3, [r7, #12]
800eaac: e002 b.n 800eab4 <prvInsertBlockIntoFreeList+0x14>
800eaae: 68fb ldr r3, [r7, #12]
800eab0: 681b ldr r3, [r3, #0]
800eab2: 60fb str r3, [r7, #12]
800eab4: 68fb ldr r3, [r7, #12]
800eab6: 681b ldr r3, [r3, #0]
800eab8: 687a ldr r2, [r7, #4]
800eaba: 429a cmp r2, r3
800eabc: d8f7 bhi.n 800eaae <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
800eabe: 68fb ldr r3, [r7, #12]
800eac0: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
800eac2: 68fb ldr r3, [r7, #12]
800eac4: 685b ldr r3, [r3, #4]
800eac6: 68ba ldr r2, [r7, #8]
800eac8: 4413 add r3, r2
800eaca: 687a ldr r2, [r7, #4]
800eacc: 429a cmp r2, r3
800eace: d108 bne.n 800eae2 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
800ead0: 68fb ldr r3, [r7, #12]
800ead2: 685a ldr r2, [r3, #4]
800ead4: 687b ldr r3, [r7, #4]
800ead6: 685b ldr r3, [r3, #4]
800ead8: 441a add r2, r3
800eada: 68fb ldr r3, [r7, #12]
800eadc: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
800eade: 68fb ldr r3, [r7, #12]
800eae0: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
800eae2: 687b ldr r3, [r7, #4]
800eae4: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800eae6: 687b ldr r3, [r7, #4]
800eae8: 685b ldr r3, [r3, #4]
800eaea: 68ba ldr r2, [r7, #8]
800eaec: 441a add r2, r3
800eaee: 68fb ldr r3, [r7, #12]
800eaf0: 681b ldr r3, [r3, #0]
800eaf2: 429a cmp r2, r3
800eaf4: d118 bne.n 800eb28 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800eaf6: 68fb ldr r3, [r7, #12]
800eaf8: 681a ldr r2, [r3, #0]
800eafa: 4b15 ldr r3, [pc, #84] ; (800eb50 <prvInsertBlockIntoFreeList+0xb0>)
800eafc: 681b ldr r3, [r3, #0]
800eafe: 429a cmp r2, r3
800eb00: d00d beq.n 800eb1e <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800eb02: 687b ldr r3, [r7, #4]
800eb04: 685a ldr r2, [r3, #4]
800eb06: 68fb ldr r3, [r7, #12]
800eb08: 681b ldr r3, [r3, #0]
800eb0a: 685b ldr r3, [r3, #4]
800eb0c: 441a add r2, r3
800eb0e: 687b ldr r3, [r7, #4]
800eb10: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
800eb12: 68fb ldr r3, [r7, #12]
800eb14: 681b ldr r3, [r3, #0]
800eb16: 681a ldr r2, [r3, #0]
800eb18: 687b ldr r3, [r7, #4]
800eb1a: 601a str r2, [r3, #0]
800eb1c: e008 b.n 800eb30 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
800eb1e: 4b0c ldr r3, [pc, #48] ; (800eb50 <prvInsertBlockIntoFreeList+0xb0>)
800eb20: 681a ldr r2, [r3, #0]
800eb22: 687b ldr r3, [r7, #4]
800eb24: 601a str r2, [r3, #0]
800eb26: e003 b.n 800eb30 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
800eb28: 68fb ldr r3, [r7, #12]
800eb2a: 681a ldr r2, [r3, #0]
800eb2c: 687b ldr r3, [r7, #4]
800eb2e: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
800eb30: 68fa ldr r2, [r7, #12]
800eb32: 687b ldr r3, [r7, #4]
800eb34: 429a cmp r2, r3
800eb36: d002 beq.n 800eb3e <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
800eb38: 68fb ldr r3, [r7, #12]
800eb3a: 687a ldr r2, [r7, #4]
800eb3c: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800eb3e: bf00 nop
800eb40: 3714 adds r7, #20
800eb42: 46bd mov sp, r7
800eb44: f85d 7b04 ldr.w r7, [sp], #4
800eb48: 4770 bx lr
800eb4a: bf00 nop
800eb4c: 200086c0 .word 0x200086c0
800eb50: 200086c8 .word 0x200086c8
0800eb54 <tcpip_timeouts_mbox_fetch>:
* @param mbox the mbox to fetch the message from
* @param msg the place to store the message
*/
static void
tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
{
800eb54: b580 push {r7, lr}
800eb56: b084 sub sp, #16
800eb58: af00 add r7, sp, #0
800eb5a: 6078 str r0, [r7, #4]
800eb5c: 6039 str r1, [r7, #0]
u32_t sleeptime, res;
again:
LWIP_ASSERT_CORE_LOCKED();
sleeptime = sys_timeouts_sleeptime();
800eb5e: f007 fa91 bl 8016084 <sys_timeouts_sleeptime>
800eb62: 60f8 str r0, [r7, #12]
if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
800eb64: 68fb ldr r3, [r7, #12]
800eb66: f1b3 3fff cmp.w r3, #4294967295
800eb6a: d10b bne.n 800eb84 <tcpip_timeouts_mbox_fetch+0x30>
UNLOCK_TCPIP_CORE();
800eb6c: 4813 ldr r0, [pc, #76] ; (800ebbc <tcpip_timeouts_mbox_fetch+0x68>)
800eb6e: f00c f9c2 bl 801aef6 <sys_mutex_unlock>
sys_arch_mbox_fetch(mbox, msg, 0);
800eb72: 2200 movs r2, #0
800eb74: 6839 ldr r1, [r7, #0]
800eb76: 6878 ldr r0, [r7, #4]
800eb78: f00c f934 bl 801ade4 <sys_arch_mbox_fetch>
LOCK_TCPIP_CORE();
800eb7c: 480f ldr r0, [pc, #60] ; (800ebbc <tcpip_timeouts_mbox_fetch+0x68>)
800eb7e: f00c f9ab bl 801aed8 <sys_mutex_lock>
return;
800eb82: e018 b.n 800ebb6 <tcpip_timeouts_mbox_fetch+0x62>
} else if (sleeptime == 0) {
800eb84: 68fb ldr r3, [r7, #12]
800eb86: 2b00 cmp r3, #0
800eb88: d102 bne.n 800eb90 <tcpip_timeouts_mbox_fetch+0x3c>
sys_check_timeouts();
800eb8a: f007 fa41 bl 8016010 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800eb8e: e7e6 b.n 800eb5e <tcpip_timeouts_mbox_fetch+0xa>
}
UNLOCK_TCPIP_CORE();
800eb90: 480a ldr r0, [pc, #40] ; (800ebbc <tcpip_timeouts_mbox_fetch+0x68>)
800eb92: f00c f9b0 bl 801aef6 <sys_mutex_unlock>
res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
800eb96: 68fa ldr r2, [r7, #12]
800eb98: 6839 ldr r1, [r7, #0]
800eb9a: 6878 ldr r0, [r7, #4]
800eb9c: f00c f922 bl 801ade4 <sys_arch_mbox_fetch>
800eba0: 60b8 str r0, [r7, #8]
LOCK_TCPIP_CORE();
800eba2: 4806 ldr r0, [pc, #24] ; (800ebbc <tcpip_timeouts_mbox_fetch+0x68>)
800eba4: f00c f998 bl 801aed8 <sys_mutex_lock>
if (res == SYS_ARCH_TIMEOUT) {
800eba8: 68bb ldr r3, [r7, #8]
800ebaa: f1b3 3fff cmp.w r3, #4294967295
800ebae: d102 bne.n 800ebb6 <tcpip_timeouts_mbox_fetch+0x62>
/* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
before a message could be fetched. */
sys_check_timeouts();
800ebb0: f007 fa2e bl 8016010 <sys_check_timeouts>
/* We try again to fetch a message from the mbox. */
goto again;
800ebb4: e7d3 b.n 800eb5e <tcpip_timeouts_mbox_fetch+0xa>
}
}
800ebb6: 3710 adds r7, #16
800ebb8: 46bd mov sp, r7
800ebba: bd80 pop {r7, pc}
800ebbc: 2000be88 .word 0x2000be88
0800ebc0 <tcpip_thread>:
*
* @param arg unused argument
*/
static void
tcpip_thread(void *arg)
{
800ebc0: b580 push {r7, lr}
800ebc2: b084 sub sp, #16
800ebc4: af00 add r7, sp, #0
800ebc6: 6078 str r0, [r7, #4]
struct tcpip_msg *msg;
LWIP_UNUSED_ARG(arg);
LWIP_MARK_TCPIP_THREAD();
LOCK_TCPIP_CORE();
800ebc8: 4810 ldr r0, [pc, #64] ; (800ec0c <tcpip_thread+0x4c>)
800ebca: f00c f985 bl 801aed8 <sys_mutex_lock>
if (tcpip_init_done != NULL) {
800ebce: 4b10 ldr r3, [pc, #64] ; (800ec10 <tcpip_thread+0x50>)
800ebd0: 681b ldr r3, [r3, #0]
800ebd2: 2b00 cmp r3, #0
800ebd4: d005 beq.n 800ebe2 <tcpip_thread+0x22>
tcpip_init_done(tcpip_init_done_arg);
800ebd6: 4b0e ldr r3, [pc, #56] ; (800ec10 <tcpip_thread+0x50>)
800ebd8: 681b ldr r3, [r3, #0]
800ebda: 4a0e ldr r2, [pc, #56] ; (800ec14 <tcpip_thread+0x54>)
800ebdc: 6812 ldr r2, [r2, #0]
800ebde: 4610 mov r0, r2
800ebe0: 4798 blx r3
}
while (1) { /* MAIN Loop */
LWIP_TCPIP_THREAD_ALIVE();
/* wait for a message, timeouts are processed while waiting */
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800ebe2: f107 030c add.w r3, r7, #12
800ebe6: 4619 mov r1, r3
800ebe8: 480b ldr r0, [pc, #44] ; (800ec18 <tcpip_thread+0x58>)
800ebea: f7ff ffb3 bl 800eb54 <tcpip_timeouts_mbox_fetch>
if (msg == NULL) {
800ebee: 68fb ldr r3, [r7, #12]
800ebf0: 2b00 cmp r3, #0
800ebf2: d106 bne.n 800ec02 <tcpip_thread+0x42>
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800ebf4: 4b09 ldr r3, [pc, #36] ; (800ec1c <tcpip_thread+0x5c>)
800ebf6: 2291 movs r2, #145 ; 0x91
800ebf8: 4909 ldr r1, [pc, #36] ; (800ec20 <tcpip_thread+0x60>)
800ebfa: 480a ldr r0, [pc, #40] ; (800ec24 <tcpip_thread+0x64>)
800ebfc: f00c fa12 bl 801b024 <iprintf>
continue;
800ec00: e003 b.n 800ec0a <tcpip_thread+0x4a>
}
tcpip_thread_handle_msg(msg);
800ec02: 68fb ldr r3, [r7, #12]
800ec04: 4618 mov r0, r3
800ec06: f000 f80f bl 800ec28 <tcpip_thread_handle_msg>
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
800ec0a: e7ea b.n 800ebe2 <tcpip_thread+0x22>
800ec0c: 2000be88 .word 0x2000be88
800ec10: 200086d8 .word 0x200086d8
800ec14: 200086dc .word 0x200086dc
800ec18: 200086e0 .word 0x200086e0
800ec1c: 0801bfe4 .word 0x0801bfe4
800ec20: 0801c014 .word 0x0801c014
800ec24: 0801c034 .word 0x0801c034
0800ec28 <tcpip_thread_handle_msg>:
/* Handle a single tcpip_msg
* This is in its own function for access by tests only.
*/
static void
tcpip_thread_handle_msg(struct tcpip_msg *msg)
{
800ec28: b580 push {r7, lr}
800ec2a: b082 sub sp, #8
800ec2c: af00 add r7, sp, #0
800ec2e: 6078 str r0, [r7, #4]
switch (msg->type) {
800ec30: 687b ldr r3, [r7, #4]
800ec32: 781b ldrb r3, [r3, #0]
800ec34: 2b01 cmp r3, #1
800ec36: d018 beq.n 800ec6a <tcpip_thread_handle_msg+0x42>
800ec38: 2b02 cmp r3, #2
800ec3a: d021 beq.n 800ec80 <tcpip_thread_handle_msg+0x58>
800ec3c: 2b00 cmp r3, #0
800ec3e: d126 bne.n 800ec8e <tcpip_thread_handle_msg+0x66>
#endif /* !LWIP_TCPIP_CORE_LOCKING */
#if !LWIP_TCPIP_CORE_LOCKING_INPUT
case TCPIP_MSG_INPKT:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
800ec40: 687b ldr r3, [r7, #4]
800ec42: 68db ldr r3, [r3, #12]
800ec44: 687a ldr r2, [r7, #4]
800ec46: 6850 ldr r0, [r2, #4]
800ec48: 687a ldr r2, [r7, #4]
800ec4a: 6892 ldr r2, [r2, #8]
800ec4c: 4611 mov r1, r2
800ec4e: 4798 blx r3
800ec50: 4603 mov r3, r0
800ec52: 2b00 cmp r3, #0
800ec54: d004 beq.n 800ec60 <tcpip_thread_handle_msg+0x38>
pbuf_free(msg->msg.inp.p);
800ec56: 687b ldr r3, [r7, #4]
800ec58: 685b ldr r3, [r3, #4]
800ec5a: 4618 mov r0, r3
800ec5c: f001 fccc bl 80105f8 <pbuf_free>
}
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ec60: 6879 ldr r1, [r7, #4]
800ec62: 2009 movs r0, #9
800ec64: f000 fe1c bl 800f8a0 <memp_free>
break;
800ec68: e018 b.n 800ec9c <tcpip_thread_handle_msg+0x74>
break;
#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
case TCPIP_MSG_CALLBACK:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec6a: 687b ldr r3, [r7, #4]
800ec6c: 685b ldr r3, [r3, #4]
800ec6e: 687a ldr r2, [r7, #4]
800ec70: 6892 ldr r2, [r2, #8]
800ec72: 4610 mov r0, r2
800ec74: 4798 blx r3
memp_free(MEMP_TCPIP_MSG_API, msg);
800ec76: 6879 ldr r1, [r7, #4]
800ec78: 2008 movs r0, #8
800ec7a: f000 fe11 bl 800f8a0 <memp_free>
break;
800ec7e: e00d b.n 800ec9c <tcpip_thread_handle_msg+0x74>
case TCPIP_MSG_CALLBACK_STATIC:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
msg->msg.cb.function(msg->msg.cb.ctx);
800ec80: 687b ldr r3, [r7, #4]
800ec82: 685b ldr r3, [r3, #4]
800ec84: 687a ldr r2, [r7, #4]
800ec86: 6892 ldr r2, [r2, #8]
800ec88: 4610 mov r0, r2
800ec8a: 4798 blx r3
break;
800ec8c: e006 b.n 800ec9c <tcpip_thread_handle_msg+0x74>
default:
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
LWIP_ASSERT("tcpip_thread: invalid message", 0);
800ec8e: 4b05 ldr r3, [pc, #20] ; (800eca4 <tcpip_thread_handle_msg+0x7c>)
800ec90: 22cf movs r2, #207 ; 0xcf
800ec92: 4905 ldr r1, [pc, #20] ; (800eca8 <tcpip_thread_handle_msg+0x80>)
800ec94: 4805 ldr r0, [pc, #20] ; (800ecac <tcpip_thread_handle_msg+0x84>)
800ec96: f00c f9c5 bl 801b024 <iprintf>
break;
800ec9a: bf00 nop
}
}
800ec9c: bf00 nop
800ec9e: 3708 adds r7, #8
800eca0: 46bd mov sp, r7
800eca2: bd80 pop {r7, pc}
800eca4: 0801bfe4 .word 0x0801bfe4
800eca8: 0801c014 .word 0x0801c014
800ecac: 0801c034 .word 0x0801c034
0800ecb0 <tcpip_inpkt>:
* @param inp the network interface on which the packet was received
* @param input_fn input function to call
*/
err_t
tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
{
800ecb0: b580 push {r7, lr}
800ecb2: b086 sub sp, #24
800ecb4: af00 add r7, sp, #0
800ecb6: 60f8 str r0, [r7, #12]
800ecb8: 60b9 str r1, [r7, #8]
800ecba: 607a str r2, [r7, #4]
UNLOCK_TCPIP_CORE();
return ret;
#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ecbc: 481a ldr r0, [pc, #104] ; (800ed28 <tcpip_inpkt+0x78>)
800ecbe: f00c f8d0 bl 801ae62 <sys_mbox_valid>
800ecc2: 4603 mov r3, r0
800ecc4: 2b00 cmp r3, #0
800ecc6: d105 bne.n 800ecd4 <tcpip_inpkt+0x24>
800ecc8: 4b18 ldr r3, [pc, #96] ; (800ed2c <tcpip_inpkt+0x7c>)
800ecca: 22fc movs r2, #252 ; 0xfc
800eccc: 4918 ldr r1, [pc, #96] ; (800ed30 <tcpip_inpkt+0x80>)
800ecce: 4819 ldr r0, [pc, #100] ; (800ed34 <tcpip_inpkt+0x84>)
800ecd0: f00c f9a8 bl 801b024 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
800ecd4: 2009 movs r0, #9
800ecd6: f000 fd91 bl 800f7fc <memp_malloc>
800ecda: 6178 str r0, [r7, #20]
if (msg == NULL) {
800ecdc: 697b ldr r3, [r7, #20]
800ecde: 2b00 cmp r3, #0
800ece0: d102 bne.n 800ece8 <tcpip_inpkt+0x38>
return ERR_MEM;
800ece2: f04f 33ff mov.w r3, #4294967295
800ece6: e01a b.n 800ed1e <tcpip_inpkt+0x6e>
}
msg->type = TCPIP_MSG_INPKT;
800ece8: 697b ldr r3, [r7, #20]
800ecea: 2200 movs r2, #0
800ecec: 701a strb r2, [r3, #0]
msg->msg.inp.p = p;
800ecee: 697b ldr r3, [r7, #20]
800ecf0: 68fa ldr r2, [r7, #12]
800ecf2: 605a str r2, [r3, #4]
msg->msg.inp.netif = inp;
800ecf4: 697b ldr r3, [r7, #20]
800ecf6: 68ba ldr r2, [r7, #8]
800ecf8: 609a str r2, [r3, #8]
msg->msg.inp.input_fn = input_fn;
800ecfa: 697b ldr r3, [r7, #20]
800ecfc: 687a ldr r2, [r7, #4]
800ecfe: 60da str r2, [r3, #12]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800ed00: 6979 ldr r1, [r7, #20]
800ed02: 4809 ldr r0, [pc, #36] ; (800ed28 <tcpip_inpkt+0x78>)
800ed04: f00c f854 bl 801adb0 <sys_mbox_trypost>
800ed08: 4603 mov r3, r0
800ed0a: 2b00 cmp r3, #0
800ed0c: d006 beq.n 800ed1c <tcpip_inpkt+0x6c>
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
800ed0e: 6979 ldr r1, [r7, #20]
800ed10: 2009 movs r0, #9
800ed12: f000 fdc5 bl 800f8a0 <memp_free>
return ERR_MEM;
800ed16: f04f 33ff mov.w r3, #4294967295
800ed1a: e000 b.n 800ed1e <tcpip_inpkt+0x6e>
}
return ERR_OK;
800ed1c: 2300 movs r3, #0
#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
}
800ed1e: 4618 mov r0, r3
800ed20: 3718 adds r7, #24
800ed22: 46bd mov sp, r7
800ed24: bd80 pop {r7, pc}
800ed26: bf00 nop
800ed28: 200086e0 .word 0x200086e0
800ed2c: 0801bfe4 .word 0x0801bfe4
800ed30: 0801c05c .word 0x0801c05c
800ed34: 0801c034 .word 0x0801c034
0800ed38 <tcpip_input>:
* NETIF_FLAG_ETHERNET flags)
* @param inp the network interface on which the packet was received
*/
err_t
tcpip_input(struct pbuf *p, struct netif *inp)
{
800ed38: b580 push {r7, lr}
800ed3a: b082 sub sp, #8
800ed3c: af00 add r7, sp, #0
800ed3e: 6078 str r0, [r7, #4]
800ed40: 6039 str r1, [r7, #0]
#if LWIP_ETHERNET
if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
800ed42: 683b ldr r3, [r7, #0]
800ed44: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800ed48: f003 0318 and.w r3, r3, #24
800ed4c: 2b00 cmp r3, #0
800ed4e: d006 beq.n 800ed5e <tcpip_input+0x26>
return tcpip_inpkt(p, inp, ethernet_input);
800ed50: 4a08 ldr r2, [pc, #32] ; (800ed74 <tcpip_input+0x3c>)
800ed52: 6839 ldr r1, [r7, #0]
800ed54: 6878 ldr r0, [r7, #4]
800ed56: f7ff ffab bl 800ecb0 <tcpip_inpkt>
800ed5a: 4603 mov r3, r0
800ed5c: e005 b.n 800ed6a <tcpip_input+0x32>
} else
#endif /* LWIP_ETHERNET */
return tcpip_inpkt(p, inp, ip_input);
800ed5e: 4a06 ldr r2, [pc, #24] ; (800ed78 <tcpip_input+0x40>)
800ed60: 6839 ldr r1, [r7, #0]
800ed62: 6878 ldr r0, [r7, #4]
800ed64: f7ff ffa4 bl 800ecb0 <tcpip_inpkt>
800ed68: 4603 mov r3, r0
}
800ed6a: 4618 mov r0, r3
800ed6c: 3708 adds r7, #8
800ed6e: 46bd mov sp, r7
800ed70: bd80 pop {r7, pc}
800ed72: bf00 nop
800ed74: 0801abc1 .word 0x0801abc1
800ed78: 08019aa5 .word 0x08019aa5
0800ed7c <tcpip_try_callback>:
*
* @see tcpip_callback
*/
err_t
tcpip_try_callback(tcpip_callback_fn function, void *ctx)
{
800ed7c: b580 push {r7, lr}
800ed7e: b084 sub sp, #16
800ed80: af00 add r7, sp, #0
800ed82: 6078 str r0, [r7, #4]
800ed84: 6039 str r1, [r7, #0]
struct tcpip_msg *msg;
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
800ed86: 4819 ldr r0, [pc, #100] ; (800edec <tcpip_try_callback+0x70>)
800ed88: f00c f86b bl 801ae62 <sys_mbox_valid>
800ed8c: 4603 mov r3, r0
800ed8e: 2b00 cmp r3, #0
800ed90: d106 bne.n 800eda0 <tcpip_try_callback+0x24>
800ed92: 4b17 ldr r3, [pc, #92] ; (800edf0 <tcpip_try_callback+0x74>)
800ed94: f240 125d movw r2, #349 ; 0x15d
800ed98: 4916 ldr r1, [pc, #88] ; (800edf4 <tcpip_try_callback+0x78>)
800ed9a: 4817 ldr r0, [pc, #92] ; (800edf8 <tcpip_try_callback+0x7c>)
800ed9c: f00c f942 bl 801b024 <iprintf>
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
800eda0: 2008 movs r0, #8
800eda2: f000 fd2b bl 800f7fc <memp_malloc>
800eda6: 60f8 str r0, [r7, #12]
if (msg == NULL) {
800eda8: 68fb ldr r3, [r7, #12]
800edaa: 2b00 cmp r3, #0
800edac: d102 bne.n 800edb4 <tcpip_try_callback+0x38>
return ERR_MEM;
800edae: f04f 33ff mov.w r3, #4294967295
800edb2: e017 b.n 800ede4 <tcpip_try_callback+0x68>
}
msg->type = TCPIP_MSG_CALLBACK;
800edb4: 68fb ldr r3, [r7, #12]
800edb6: 2201 movs r2, #1
800edb8: 701a strb r2, [r3, #0]
msg->msg.cb.function = function;
800edba: 68fb ldr r3, [r7, #12]
800edbc: 687a ldr r2, [r7, #4]
800edbe: 605a str r2, [r3, #4]
msg->msg.cb.ctx = ctx;
800edc0: 68fb ldr r3, [r7, #12]
800edc2: 683a ldr r2, [r7, #0]
800edc4: 609a str r2, [r3, #8]
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
800edc6: 68f9 ldr r1, [r7, #12]
800edc8: 4808 ldr r0, [pc, #32] ; (800edec <tcpip_try_callback+0x70>)
800edca: f00b fff1 bl 801adb0 <sys_mbox_trypost>
800edce: 4603 mov r3, r0
800edd0: 2b00 cmp r3, #0
800edd2: d006 beq.n 800ede2 <tcpip_try_callback+0x66>
memp_free(MEMP_TCPIP_MSG_API, msg);
800edd4: 68f9 ldr r1, [r7, #12]
800edd6: 2008 movs r0, #8
800edd8: f000 fd62 bl 800f8a0 <memp_free>
return ERR_MEM;
800eddc: f04f 33ff mov.w r3, #4294967295
800ede0: e000 b.n 800ede4 <tcpip_try_callback+0x68>
}
return ERR_OK;
800ede2: 2300 movs r3, #0
}
800ede4: 4618 mov r0, r3
800ede6: 3710 adds r7, #16
800ede8: 46bd mov sp, r7
800edea: bd80 pop {r7, pc}
800edec: 200086e0 .word 0x200086e0
800edf0: 0801bfe4 .word 0x0801bfe4
800edf4: 0801c05c .word 0x0801c05c
800edf8: 0801c034 .word 0x0801c034
0800edfc <tcpip_init>:
* @param initfunc a function to call when tcpip_thread is running and finished initializing
* @param arg argument to pass to initfunc
*/
void
tcpip_init(tcpip_init_done_fn initfunc, void *arg)
{
800edfc: b580 push {r7, lr}
800edfe: b084 sub sp, #16
800ee00: af02 add r7, sp, #8
800ee02: 6078 str r0, [r7, #4]
800ee04: 6039 str r1, [r7, #0]
lwip_init();
800ee06: f000 f871 bl 800eeec <lwip_init>
tcpip_init_done = initfunc;
800ee0a: 4a17 ldr r2, [pc, #92] ; (800ee68 <tcpip_init+0x6c>)
800ee0c: 687b ldr r3, [r7, #4]
800ee0e: 6013 str r3, [r2, #0]
tcpip_init_done_arg = arg;
800ee10: 4a16 ldr r2, [pc, #88] ; (800ee6c <tcpip_init+0x70>)
800ee12: 683b ldr r3, [r7, #0]
800ee14: 6013 str r3, [r2, #0]
if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
800ee16: 2106 movs r1, #6
800ee18: 4815 ldr r0, [pc, #84] ; (800ee70 <tcpip_init+0x74>)
800ee1a: f00b ffa7 bl 801ad6c <sys_mbox_new>
800ee1e: 4603 mov r3, r0
800ee20: 2b00 cmp r3, #0
800ee22: d006 beq.n 800ee32 <tcpip_init+0x36>
LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
800ee24: 4b13 ldr r3, [pc, #76] ; (800ee74 <tcpip_init+0x78>)
800ee26: f240 2261 movw r2, #609 ; 0x261
800ee2a: 4913 ldr r1, [pc, #76] ; (800ee78 <tcpip_init+0x7c>)
800ee2c: 4813 ldr r0, [pc, #76] ; (800ee7c <tcpip_init+0x80>)
800ee2e: f00c f8f9 bl 801b024 <iprintf>
}
#if LWIP_TCPIP_CORE_LOCKING
if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
800ee32: 4813 ldr r0, [pc, #76] ; (800ee80 <tcpip_init+0x84>)
800ee34: f00c f834 bl 801aea0 <sys_mutex_new>
800ee38: 4603 mov r3, r0
800ee3a: 2b00 cmp r3, #0
800ee3c: d006 beq.n 800ee4c <tcpip_init+0x50>
LWIP_ASSERT("failed to create lock_tcpip_core", 0);
800ee3e: 4b0d ldr r3, [pc, #52] ; (800ee74 <tcpip_init+0x78>)
800ee40: f240 2265 movw r2, #613 ; 0x265
800ee44: 490f ldr r1, [pc, #60] ; (800ee84 <tcpip_init+0x88>)
800ee46: 480d ldr r0, [pc, #52] ; (800ee7c <tcpip_init+0x80>)
800ee48: f00c f8ec bl 801b024 <iprintf>
}
#endif /* LWIP_TCPIP_CORE_LOCKING */
sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
800ee4c: 2300 movs r3, #0
800ee4e: 9300 str r3, [sp, #0]
800ee50: f44f 6380 mov.w r3, #1024 ; 0x400
800ee54: 2200 movs r2, #0
800ee56: 490c ldr r1, [pc, #48] ; (800ee88 <tcpip_init+0x8c>)
800ee58: 480c ldr r0, [pc, #48] ; (800ee8c <tcpip_init+0x90>)
800ee5a: f00c f859 bl 801af10 <sys_thread_new>
}
800ee5e: bf00 nop
800ee60: 3708 adds r7, #8
800ee62: 46bd mov sp, r7
800ee64: bd80 pop {r7, pc}
800ee66: bf00 nop
800ee68: 200086d8 .word 0x200086d8
800ee6c: 200086dc .word 0x200086dc
800ee70: 200086e0 .word 0x200086e0
800ee74: 0801bfe4 .word 0x0801bfe4
800ee78: 0801c06c .word 0x0801c06c
800ee7c: 0801c034 .word 0x0801c034
800ee80: 2000be88 .word 0x2000be88
800ee84: 0801c090 .word 0x0801c090
800ee88: 0800ebc1 .word 0x0800ebc1
800ee8c: 0801c0b4 .word 0x0801c0b4
0800ee90 <lwip_htons>:
* @param n u16_t in host byte order
* @return n in network byte order
*/
u16_t
lwip_htons(u16_t n)
{
800ee90: b480 push {r7}
800ee92: b083 sub sp, #12
800ee94: af00 add r7, sp, #0
800ee96: 4603 mov r3, r0
800ee98: 80fb strh r3, [r7, #6]
return PP_HTONS(n);
800ee9a: 88fb ldrh r3, [r7, #6]
800ee9c: 021b lsls r3, r3, #8
800ee9e: b21a sxth r2, r3
800eea0: 88fb ldrh r3, [r7, #6]
800eea2: 0a1b lsrs r3, r3, #8
800eea4: b29b uxth r3, r3
800eea6: b21b sxth r3, r3
800eea8: 4313 orrs r3, r2
800eeaa: b21b sxth r3, r3
800eeac: b29b uxth r3, r3
}
800eeae: 4618 mov r0, r3
800eeb0: 370c adds r7, #12
800eeb2: 46bd mov sp, r7
800eeb4: f85d 7b04 ldr.w r7, [sp], #4
800eeb8: 4770 bx lr
0800eeba <lwip_htonl>:
* @param n u32_t in host byte order
* @return n in network byte order
*/
u32_t
lwip_htonl(u32_t n)
{
800eeba: b480 push {r7}
800eebc: b083 sub sp, #12
800eebe: af00 add r7, sp, #0
800eec0: 6078 str r0, [r7, #4]
return PP_HTONL(n);
800eec2: 687b ldr r3, [r7, #4]
800eec4: 061a lsls r2, r3, #24
800eec6: 687b ldr r3, [r7, #4]
800eec8: 021b lsls r3, r3, #8
800eeca: f403 037f and.w r3, r3, #16711680 ; 0xff0000
800eece: 431a orrs r2, r3
800eed0: 687b ldr r3, [r7, #4]
800eed2: 0a1b lsrs r3, r3, #8
800eed4: f403 437f and.w r3, r3, #65280 ; 0xff00
800eed8: 431a orrs r2, r3
800eeda: 687b ldr r3, [r7, #4]
800eedc: 0e1b lsrs r3, r3, #24
800eede: 4313 orrs r3, r2
}
800eee0: 4618 mov r0, r3
800eee2: 370c adds r7, #12
800eee4: 46bd mov sp, r7
800eee6: f85d 7b04 ldr.w r7, [sp], #4
800eeea: 4770 bx lr
0800eeec <lwip_init>:
* Initialize all modules.
* Use this in NO_SYS mode. Use tcpip_init() otherwise.
*/
void
lwip_init(void)
{
800eeec: b580 push {r7, lr}
800eeee: b082 sub sp, #8
800eef0: af00 add r7, sp, #0
#ifndef LWIP_SKIP_CONST_CHECK
int a = 0;
800eef2: 2300 movs r3, #0
800eef4: 607b str r3, [r7, #4]
#endif
/* Modules initialization */
stats_init();
#if !NO_SYS
sys_init();
800eef6: f00b ffc5 bl 801ae84 <sys_init>
#endif /* !NO_SYS */
mem_init();
800eefa: f000 f8d5 bl 800f0a8 <mem_init>
memp_init();
800eefe: f000 fc31 bl 800f764 <memp_init>
pbuf_init();
netif_init();
800ef02: f000 fcf7 bl 800f8f4 <netif_init>
#endif /* LWIP_IPV4 */
#if LWIP_RAW
raw_init();
#endif /* LWIP_RAW */
#if LWIP_UDP
udp_init();
800ef06: f007 f8f5 bl 80160f4 <udp_init>
#endif /* LWIP_UDP */
#if LWIP_TCP
tcp_init();
800ef0a: f001 fe1f bl 8010b4c <tcp_init>
#if PPP_SUPPORT
ppp_init();
#endif
#if LWIP_TIMERS
sys_timeouts_init();
800ef0e: f007 f839 bl 8015f84 <sys_timeouts_init>
#endif /* LWIP_TIMERS */
}
800ef12: bf00 nop
800ef14: 3708 adds r7, #8
800ef16: 46bd mov sp, r7
800ef18: bd80 pop {r7, pc}
...
0800ef1c <ptr_to_mem>:
#define mem_overflow_check_element(mem)
#endif /* MEM_OVERFLOW_CHECK */
static struct mem *
ptr_to_mem(mem_size_t ptr)
{
800ef1c: b480 push {r7}
800ef1e: b083 sub sp, #12
800ef20: af00 add r7, sp, #0
800ef22: 4603 mov r3, r0
800ef24: 80fb strh r3, [r7, #6]
return (struct mem *)(void *)&ram[ptr];
800ef26: 4b05 ldr r3, [pc, #20] ; (800ef3c <ptr_to_mem+0x20>)
800ef28: 681a ldr r2, [r3, #0]
800ef2a: 88fb ldrh r3, [r7, #6]
800ef2c: 4413 add r3, r2
}
800ef2e: 4618 mov r0, r3
800ef30: 370c adds r7, #12
800ef32: 46bd mov sp, r7
800ef34: f85d 7b04 ldr.w r7, [sp], #4
800ef38: 4770 bx lr
800ef3a: bf00 nop
800ef3c: 200086e4 .word 0x200086e4
0800ef40 <mem_to_ptr>:
static mem_size_t
mem_to_ptr(void *mem)
{
800ef40: b480 push {r7}
800ef42: b083 sub sp, #12
800ef44: af00 add r7, sp, #0
800ef46: 6078 str r0, [r7, #4]
return (mem_size_t)((u8_t *)mem - ram);
800ef48: 687b ldr r3, [r7, #4]
800ef4a: 4a05 ldr r2, [pc, #20] ; (800ef60 <mem_to_ptr+0x20>)
800ef4c: 6812 ldr r2, [r2, #0]
800ef4e: 1a9b subs r3, r3, r2
800ef50: b29b uxth r3, r3
}
800ef52: 4618 mov r0, r3
800ef54: 370c adds r7, #12
800ef56: 46bd mov sp, r7
800ef58: f85d 7b04 ldr.w r7, [sp], #4
800ef5c: 4770 bx lr
800ef5e: bf00 nop
800ef60: 200086e4 .word 0x200086e4
0800ef64 <plug_holes>:
* This assumes access to the heap is protected by the calling function
* already.
*/
static void
plug_holes(struct mem *mem)
{
800ef64: b590 push {r4, r7, lr}
800ef66: b085 sub sp, #20
800ef68: af00 add r7, sp, #0
800ef6a: 6078 str r0, [r7, #4]
struct mem *nmem;
struct mem *pmem;
LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
800ef6c: 4b45 ldr r3, [pc, #276] ; (800f084 <plug_holes+0x120>)
800ef6e: 681b ldr r3, [r3, #0]
800ef70: 687a ldr r2, [r7, #4]
800ef72: 429a cmp r2, r3
800ef74: d206 bcs.n 800ef84 <plug_holes+0x20>
800ef76: 4b44 ldr r3, [pc, #272] ; (800f088 <plug_holes+0x124>)
800ef78: f240 12df movw r2, #479 ; 0x1df
800ef7c: 4943 ldr r1, [pc, #268] ; (800f08c <plug_holes+0x128>)
800ef7e: 4844 ldr r0, [pc, #272] ; (800f090 <plug_holes+0x12c>)
800ef80: f00c f850 bl 801b024 <iprintf>
LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
800ef84: 4b43 ldr r3, [pc, #268] ; (800f094 <plug_holes+0x130>)
800ef86: 681b ldr r3, [r3, #0]
800ef88: 687a ldr r2, [r7, #4]
800ef8a: 429a cmp r2, r3
800ef8c: d306 bcc.n 800ef9c <plug_holes+0x38>
800ef8e: 4b3e ldr r3, [pc, #248] ; (800f088 <plug_holes+0x124>)
800ef90: f44f 72f0 mov.w r2, #480 ; 0x1e0
800ef94: 4940 ldr r1, [pc, #256] ; (800f098 <plug_holes+0x134>)
800ef96: 483e ldr r0, [pc, #248] ; (800f090 <plug_holes+0x12c>)
800ef98: f00c f844 bl 801b024 <iprintf>
LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
800ef9c: 687b ldr r3, [r7, #4]
800ef9e: 791b ldrb r3, [r3, #4]
800efa0: 2b00 cmp r3, #0
800efa2: d006 beq.n 800efb2 <plug_holes+0x4e>
800efa4: 4b38 ldr r3, [pc, #224] ; (800f088 <plug_holes+0x124>)
800efa6: f240 12e1 movw r2, #481 ; 0x1e1
800efaa: 493c ldr r1, [pc, #240] ; (800f09c <plug_holes+0x138>)
800efac: 4838 ldr r0, [pc, #224] ; (800f090 <plug_holes+0x12c>)
800efae: f00c f839 bl 801b024 <iprintf>
/* plug hole forward */
LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
800efb2: 687b ldr r3, [r7, #4]
800efb4: 881b ldrh r3, [r3, #0]
800efb6: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800efba: d906 bls.n 800efca <plug_holes+0x66>
800efbc: 4b32 ldr r3, [pc, #200] ; (800f088 <plug_holes+0x124>)
800efbe: f44f 72f2 mov.w r2, #484 ; 0x1e4
800efc2: 4937 ldr r1, [pc, #220] ; (800f0a0 <plug_holes+0x13c>)
800efc4: 4832 ldr r0, [pc, #200] ; (800f090 <plug_holes+0x12c>)
800efc6: f00c f82d bl 801b024 <iprintf>
nmem = ptr_to_mem(mem->next);
800efca: 687b ldr r3, [r7, #4]
800efcc: 881b ldrh r3, [r3, #0]
800efce: 4618 mov r0, r3
800efd0: f7ff ffa4 bl 800ef1c <ptr_to_mem>
800efd4: 60f8 str r0, [r7, #12]
if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
800efd6: 687a ldr r2, [r7, #4]
800efd8: 68fb ldr r3, [r7, #12]
800efda: 429a cmp r2, r3
800efdc: d024 beq.n 800f028 <plug_holes+0xc4>
800efde: 68fb ldr r3, [r7, #12]
800efe0: 791b ldrb r3, [r3, #4]
800efe2: 2b00 cmp r3, #0
800efe4: d120 bne.n 800f028 <plug_holes+0xc4>
800efe6: 4b2b ldr r3, [pc, #172] ; (800f094 <plug_holes+0x130>)
800efe8: 681b ldr r3, [r3, #0]
800efea: 68fa ldr r2, [r7, #12]
800efec: 429a cmp r2, r3
800efee: d01b beq.n 800f028 <plug_holes+0xc4>
/* if mem->next is unused and not end of ram, combine mem and mem->next */
if (lfree == nmem) {
800eff0: 4b2c ldr r3, [pc, #176] ; (800f0a4 <plug_holes+0x140>)
800eff2: 681b ldr r3, [r3, #0]
800eff4: 68fa ldr r2, [r7, #12]
800eff6: 429a cmp r2, r3
800eff8: d102 bne.n 800f000 <plug_holes+0x9c>
lfree = mem;
800effa: 4a2a ldr r2, [pc, #168] ; (800f0a4 <plug_holes+0x140>)
800effc: 687b ldr r3, [r7, #4]
800effe: 6013 str r3, [r2, #0]
}
mem->next = nmem->next;
800f000: 68fb ldr r3, [r7, #12]
800f002: 881a ldrh r2, [r3, #0]
800f004: 687b ldr r3, [r7, #4]
800f006: 801a strh r2, [r3, #0]
if (nmem->next != MEM_SIZE_ALIGNED) {
800f008: 68fb ldr r3, [r7, #12]
800f00a: 881b ldrh r3, [r3, #0]
800f00c: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f010: d00a beq.n 800f028 <plug_holes+0xc4>
ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
800f012: 68fb ldr r3, [r7, #12]
800f014: 881b ldrh r3, [r3, #0]
800f016: 4618 mov r0, r3
800f018: f7ff ff80 bl 800ef1c <ptr_to_mem>
800f01c: 4604 mov r4, r0
800f01e: 6878 ldr r0, [r7, #4]
800f020: f7ff ff8e bl 800ef40 <mem_to_ptr>
800f024: 4603 mov r3, r0
800f026: 8063 strh r3, [r4, #2]
}
}
/* plug hole backward */
pmem = ptr_to_mem(mem->prev);
800f028: 687b ldr r3, [r7, #4]
800f02a: 885b ldrh r3, [r3, #2]
800f02c: 4618 mov r0, r3
800f02e: f7ff ff75 bl 800ef1c <ptr_to_mem>
800f032: 60b8 str r0, [r7, #8]
if (pmem != mem && pmem->used == 0) {
800f034: 68ba ldr r2, [r7, #8]
800f036: 687b ldr r3, [r7, #4]
800f038: 429a cmp r2, r3
800f03a: d01f beq.n 800f07c <plug_holes+0x118>
800f03c: 68bb ldr r3, [r7, #8]
800f03e: 791b ldrb r3, [r3, #4]
800f040: 2b00 cmp r3, #0
800f042: d11b bne.n 800f07c <plug_holes+0x118>
/* if mem->prev is unused, combine mem and mem->prev */
if (lfree == mem) {
800f044: 4b17 ldr r3, [pc, #92] ; (800f0a4 <plug_holes+0x140>)
800f046: 681b ldr r3, [r3, #0]
800f048: 687a ldr r2, [r7, #4]
800f04a: 429a cmp r2, r3
800f04c: d102 bne.n 800f054 <plug_holes+0xf0>
lfree = pmem;
800f04e: 4a15 ldr r2, [pc, #84] ; (800f0a4 <plug_holes+0x140>)
800f050: 68bb ldr r3, [r7, #8]
800f052: 6013 str r3, [r2, #0]
}
pmem->next = mem->next;
800f054: 687b ldr r3, [r7, #4]
800f056: 881a ldrh r2, [r3, #0]
800f058: 68bb ldr r3, [r7, #8]
800f05a: 801a strh r2, [r3, #0]
if (mem->next != MEM_SIZE_ALIGNED) {
800f05c: 687b ldr r3, [r7, #4]
800f05e: 881b ldrh r3, [r3, #0]
800f060: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f064: d00a beq.n 800f07c <plug_holes+0x118>
ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
800f066: 687b ldr r3, [r7, #4]
800f068: 881b ldrh r3, [r3, #0]
800f06a: 4618 mov r0, r3
800f06c: f7ff ff56 bl 800ef1c <ptr_to_mem>
800f070: 4604 mov r4, r0
800f072: 68b8 ldr r0, [r7, #8]
800f074: f7ff ff64 bl 800ef40 <mem_to_ptr>
800f078: 4603 mov r3, r0
800f07a: 8063 strh r3, [r4, #2]
}
}
}
800f07c: bf00 nop
800f07e: 3714 adds r7, #20
800f080: 46bd mov sp, r7
800f082: bd90 pop {r4, r7, pc}
800f084: 200086e4 .word 0x200086e4
800f088: 0801c0c4 .word 0x0801c0c4
800f08c: 0801c0f4 .word 0x0801c0f4
800f090: 0801c10c .word 0x0801c10c
800f094: 200086e8 .word 0x200086e8
800f098: 0801c134 .word 0x0801c134
800f09c: 0801c150 .word 0x0801c150
800f0a0: 0801c16c .word 0x0801c16c
800f0a4: 200086f0 .word 0x200086f0
0800f0a8 <mem_init>:
/**
* Zero the heap and initialize start, end and lowest-free
*/
void
mem_init(void)
{
800f0a8: b580 push {r7, lr}
800f0aa: b082 sub sp, #8
800f0ac: af00 add r7, sp, #0
LWIP_ASSERT("Sanity check alignment",
(SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
/* align the heap */
ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
800f0ae: 4b1f ldr r3, [pc, #124] ; (800f12c <mem_init+0x84>)
800f0b0: 3303 adds r3, #3
800f0b2: f023 0303 bic.w r3, r3, #3
800f0b6: 461a mov r2, r3
800f0b8: 4b1d ldr r3, [pc, #116] ; (800f130 <mem_init+0x88>)
800f0ba: 601a str r2, [r3, #0]
/* initialize the start of the heap */
mem = (struct mem *)(void *)ram;
800f0bc: 4b1c ldr r3, [pc, #112] ; (800f130 <mem_init+0x88>)
800f0be: 681b ldr r3, [r3, #0]
800f0c0: 607b str r3, [r7, #4]
mem->next = MEM_SIZE_ALIGNED;
800f0c2: 687b ldr r3, [r7, #4]
800f0c4: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0c8: 801a strh r2, [r3, #0]
mem->prev = 0;
800f0ca: 687b ldr r3, [r7, #4]
800f0cc: 2200 movs r2, #0
800f0ce: 805a strh r2, [r3, #2]
mem->used = 0;
800f0d0: 687b ldr r3, [r7, #4]
800f0d2: 2200 movs r2, #0
800f0d4: 711a strb r2, [r3, #4]
/* initialize the end of the heap */
ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
800f0d6: f44f 60c8 mov.w r0, #1600 ; 0x640
800f0da: f7ff ff1f bl 800ef1c <ptr_to_mem>
800f0de: 4602 mov r2, r0
800f0e0: 4b14 ldr r3, [pc, #80] ; (800f134 <mem_init+0x8c>)
800f0e2: 601a str r2, [r3, #0]
ram_end->used = 1;
800f0e4: 4b13 ldr r3, [pc, #76] ; (800f134 <mem_init+0x8c>)
800f0e6: 681b ldr r3, [r3, #0]
800f0e8: 2201 movs r2, #1
800f0ea: 711a strb r2, [r3, #4]
ram_end->next = MEM_SIZE_ALIGNED;
800f0ec: 4b11 ldr r3, [pc, #68] ; (800f134 <mem_init+0x8c>)
800f0ee: 681b ldr r3, [r3, #0]
800f0f0: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0f4: 801a strh r2, [r3, #0]
ram_end->prev = MEM_SIZE_ALIGNED;
800f0f6: 4b0f ldr r3, [pc, #60] ; (800f134 <mem_init+0x8c>)
800f0f8: 681b ldr r3, [r3, #0]
800f0fa: f44f 62c8 mov.w r2, #1600 ; 0x640
800f0fe: 805a strh r2, [r3, #2]
MEM_SANITY();
/* initialize the lowest-free pointer to the start of the heap */
lfree = (struct mem *)(void *)ram;
800f100: 4b0b ldr r3, [pc, #44] ; (800f130 <mem_init+0x88>)
800f102: 681b ldr r3, [r3, #0]
800f104: 4a0c ldr r2, [pc, #48] ; (800f138 <mem_init+0x90>)
800f106: 6013 str r3, [r2, #0]
MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
if (sys_mutex_new(&mem_mutex) != ERR_OK) {
800f108: 480c ldr r0, [pc, #48] ; (800f13c <mem_init+0x94>)
800f10a: f00b fec9 bl 801aea0 <sys_mutex_new>
800f10e: 4603 mov r3, r0
800f110: 2b00 cmp r3, #0
800f112: d006 beq.n 800f122 <mem_init+0x7a>
LWIP_ASSERT("failed to create mem_mutex", 0);
800f114: 4b0a ldr r3, [pc, #40] ; (800f140 <mem_init+0x98>)
800f116: f240 221f movw r2, #543 ; 0x21f
800f11a: 490a ldr r1, [pc, #40] ; (800f144 <mem_init+0x9c>)
800f11c: 480a ldr r0, [pc, #40] ; (800f148 <mem_init+0xa0>)
800f11e: f00b ff81 bl 801b024 <iprintf>
}
}
800f122: bf00 nop
800f124: 3708 adds r7, #8
800f126: 46bd mov sp, r7
800f128: bd80 pop {r7, pc}
800f12a: bf00 nop
800f12c: 2000bea4 .word 0x2000bea4
800f130: 200086e4 .word 0x200086e4
800f134: 200086e8 .word 0x200086e8
800f138: 200086f0 .word 0x200086f0
800f13c: 200086ec .word 0x200086ec
800f140: 0801c0c4 .word 0x0801c0c4
800f144: 0801c198 .word 0x0801c198
800f148: 0801c10c .word 0x0801c10c
0800f14c <mem_link_valid>:
/* Check if a struct mem is correctly linked.
* If not, double-free is a possible reason.
*/
static int
mem_link_valid(struct mem *mem)
{
800f14c: b580 push {r7, lr}
800f14e: b086 sub sp, #24
800f150: af00 add r7, sp, #0
800f152: 6078 str r0, [r7, #4]
struct mem *nmem, *pmem;
mem_size_t rmem_idx;
rmem_idx = mem_to_ptr(mem);
800f154: 6878 ldr r0, [r7, #4]
800f156: f7ff fef3 bl 800ef40 <mem_to_ptr>
800f15a: 4603 mov r3, r0
800f15c: 82fb strh r3, [r7, #22]
nmem = ptr_to_mem(mem->next);
800f15e: 687b ldr r3, [r7, #4]
800f160: 881b ldrh r3, [r3, #0]
800f162: 4618 mov r0, r3
800f164: f7ff feda bl 800ef1c <ptr_to_mem>
800f168: 6138 str r0, [r7, #16]
pmem = ptr_to_mem(mem->prev);
800f16a: 687b ldr r3, [r7, #4]
800f16c: 885b ldrh r3, [r3, #2]
800f16e: 4618 mov r0, r3
800f170: f7ff fed4 bl 800ef1c <ptr_to_mem>
800f174: 60f8 str r0, [r7, #12]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f176: 687b ldr r3, [r7, #4]
800f178: 881b ldrh r3, [r3, #0]
800f17a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f17e: d818 bhi.n 800f1b2 <mem_link_valid+0x66>
800f180: 687b ldr r3, [r7, #4]
800f182: 885b ldrh r3, [r3, #2]
800f184: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f188: d813 bhi.n 800f1b2 <mem_link_valid+0x66>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f18a: 687b ldr r3, [r7, #4]
800f18c: 885b ldrh r3, [r3, #2]
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
800f18e: 8afa ldrh r2, [r7, #22]
800f190: 429a cmp r2, r3
800f192: d004 beq.n 800f19e <mem_link_valid+0x52>
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f194: 68fb ldr r3, [r7, #12]
800f196: 881b ldrh r3, [r3, #0]
800f198: 8afa ldrh r2, [r7, #22]
800f19a: 429a cmp r2, r3
800f19c: d109 bne.n 800f1b2 <mem_link_valid+0x66>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f19e: 4b08 ldr r3, [pc, #32] ; (800f1c0 <mem_link_valid+0x74>)
800f1a0: 681b ldr r3, [r3, #0]
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
800f1a2: 693a ldr r2, [r7, #16]
800f1a4: 429a cmp r2, r3
800f1a6: d006 beq.n 800f1b6 <mem_link_valid+0x6a>
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
800f1a8: 693b ldr r3, [r7, #16]
800f1aa: 885b ldrh r3, [r3, #2]
800f1ac: 8afa ldrh r2, [r7, #22]
800f1ae: 429a cmp r2, r3
800f1b0: d001 beq.n 800f1b6 <mem_link_valid+0x6a>
return 0;
800f1b2: 2300 movs r3, #0
800f1b4: e000 b.n 800f1b8 <mem_link_valid+0x6c>
}
return 1;
800f1b6: 2301 movs r3, #1
}
800f1b8: 4618 mov r0, r3
800f1ba: 3718 adds r7, #24
800f1bc: 46bd mov sp, r7
800f1be: bd80 pop {r7, pc}
800f1c0: 200086e8 .word 0x200086e8
0800f1c4 <mem_free>:
* @param rmem is the data portion of a struct mem as returned by a previous
* call to mem_malloc()
*/
void
mem_free(void *rmem)
{
800f1c4: b580 push {r7, lr}
800f1c6: b088 sub sp, #32
800f1c8: af00 add r7, sp, #0
800f1ca: 6078 str r0, [r7, #4]
struct mem *mem;
LWIP_MEM_FREE_DECL_PROTECT();
if (rmem == NULL) {
800f1cc: 687b ldr r3, [r7, #4]
800f1ce: 2b00 cmp r3, #0
800f1d0: d070 beq.n 800f2b4 <mem_free+0xf0>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
return;
}
if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
800f1d2: 687b ldr r3, [r7, #4]
800f1d4: f003 0303 and.w r3, r3, #3
800f1d8: 2b00 cmp r3, #0
800f1da: d00d beq.n 800f1f8 <mem_free+0x34>
LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
800f1dc: 4b37 ldr r3, [pc, #220] ; (800f2bc <mem_free+0xf8>)
800f1de: f240 2273 movw r2, #627 ; 0x273
800f1e2: 4937 ldr r1, [pc, #220] ; (800f2c0 <mem_free+0xfc>)
800f1e4: 4837 ldr r0, [pc, #220] ; (800f2c4 <mem_free+0x100>)
800f1e6: f00b ff1d bl 801b024 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f1ea: f00b feb7 bl 801af5c <sys_arch_protect>
800f1ee: 60f8 str r0, [r7, #12]
800f1f0: 68f8 ldr r0, [r7, #12]
800f1f2: f00b fec1 bl 801af78 <sys_arch_unprotect>
return;
800f1f6: e05e b.n 800f2b6 <mem_free+0xf2>
}
/* Get the corresponding struct mem: */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f1f8: 687b ldr r3, [r7, #4]
800f1fa: 3b08 subs r3, #8
800f1fc: 61fb str r3, [r7, #28]
if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
800f1fe: 4b32 ldr r3, [pc, #200] ; (800f2c8 <mem_free+0x104>)
800f200: 681b ldr r3, [r3, #0]
800f202: 69fa ldr r2, [r7, #28]
800f204: 429a cmp r2, r3
800f206: d306 bcc.n 800f216 <mem_free+0x52>
800f208: 687b ldr r3, [r7, #4]
800f20a: f103 020c add.w r2, r3, #12
800f20e: 4b2f ldr r3, [pc, #188] ; (800f2cc <mem_free+0x108>)
800f210: 681b ldr r3, [r3, #0]
800f212: 429a cmp r2, r3
800f214: d90d bls.n 800f232 <mem_free+0x6e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
800f216: 4b29 ldr r3, [pc, #164] ; (800f2bc <mem_free+0xf8>)
800f218: f240 227f movw r2, #639 ; 0x27f
800f21c: 492c ldr r1, [pc, #176] ; (800f2d0 <mem_free+0x10c>)
800f21e: 4829 ldr r0, [pc, #164] ; (800f2c4 <mem_free+0x100>)
800f220: f00b ff00 bl 801b024 <iprintf>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f224: f00b fe9a bl 801af5c <sys_arch_protect>
800f228: 6138 str r0, [r7, #16]
800f22a: 6938 ldr r0, [r7, #16]
800f22c: f00b fea4 bl 801af78 <sys_arch_unprotect>
return;
800f230: e041 b.n 800f2b6 <mem_free+0xf2>
}
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f232: 4828 ldr r0, [pc, #160] ; (800f2d4 <mem_free+0x110>)
800f234: f00b fe50 bl 801aed8 <sys_mutex_lock>
/* mem has to be in a used state */
if (!mem->used) {
800f238: 69fb ldr r3, [r7, #28]
800f23a: 791b ldrb r3, [r3, #4]
800f23c: 2b00 cmp r3, #0
800f23e: d110 bne.n 800f262 <mem_free+0x9e>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
800f240: 4b1e ldr r3, [pc, #120] ; (800f2bc <mem_free+0xf8>)
800f242: f44f 7223 mov.w r2, #652 ; 0x28c
800f246: 4924 ldr r1, [pc, #144] ; (800f2d8 <mem_free+0x114>)
800f248: 481e ldr r0, [pc, #120] ; (800f2c4 <mem_free+0x100>)
800f24a: f00b feeb bl 801b024 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f24e: 4821 ldr r0, [pc, #132] ; (800f2d4 <mem_free+0x110>)
800f250: f00b fe51 bl 801aef6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f254: f00b fe82 bl 801af5c <sys_arch_protect>
800f258: 6178 str r0, [r7, #20]
800f25a: 6978 ldr r0, [r7, #20]
800f25c: f00b fe8c bl 801af78 <sys_arch_unprotect>
return;
800f260: e029 b.n 800f2b6 <mem_free+0xf2>
}
if (!mem_link_valid(mem)) {
800f262: 69f8 ldr r0, [r7, #28]
800f264: f7ff ff72 bl 800f14c <mem_link_valid>
800f268: 4603 mov r3, r0
800f26a: 2b00 cmp r3, #0
800f26c: d110 bne.n 800f290 <mem_free+0xcc>
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
800f26e: 4b13 ldr r3, [pc, #76] ; (800f2bc <mem_free+0xf8>)
800f270: f240 2295 movw r2, #661 ; 0x295
800f274: 4919 ldr r1, [pc, #100] ; (800f2dc <mem_free+0x118>)
800f276: 4813 ldr r0, [pc, #76] ; (800f2c4 <mem_free+0x100>)
800f278: f00b fed4 bl 801b024 <iprintf>
LWIP_MEM_FREE_UNPROTECT();
800f27c: 4815 ldr r0, [pc, #84] ; (800f2d4 <mem_free+0x110>)
800f27e: f00b fe3a bl 801aef6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f282: f00b fe6b bl 801af5c <sys_arch_protect>
800f286: 61b8 str r0, [r7, #24]
800f288: 69b8 ldr r0, [r7, #24]
800f28a: f00b fe75 bl 801af78 <sys_arch_unprotect>
return;
800f28e: e012 b.n 800f2b6 <mem_free+0xf2>
}
/* mem is now unused. */
mem->used = 0;
800f290: 69fb ldr r3, [r7, #28]
800f292: 2200 movs r2, #0
800f294: 711a strb r2, [r3, #4]
if (mem < lfree) {
800f296: 4b12 ldr r3, [pc, #72] ; (800f2e0 <mem_free+0x11c>)
800f298: 681b ldr r3, [r3, #0]
800f29a: 69fa ldr r2, [r7, #28]
800f29c: 429a cmp r2, r3
800f29e: d202 bcs.n 800f2a6 <mem_free+0xe2>
/* the newly freed struct is now the lowest */
lfree = mem;
800f2a0: 4a0f ldr r2, [pc, #60] ; (800f2e0 <mem_free+0x11c>)
800f2a2: 69fb ldr r3, [r7, #28]
800f2a4: 6013 str r3, [r2, #0]
}
MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
/* finally, see if prev or next are free also */
plug_holes(mem);
800f2a6: 69f8 ldr r0, [r7, #28]
800f2a8: f7ff fe5c bl 800ef64 <plug_holes>
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f2ac: 4809 ldr r0, [pc, #36] ; (800f2d4 <mem_free+0x110>)
800f2ae: f00b fe22 bl 801aef6 <sys_mutex_unlock>
800f2b2: e000 b.n 800f2b6 <mem_free+0xf2>
return;
800f2b4: bf00 nop
}
800f2b6: 3720 adds r7, #32
800f2b8: 46bd mov sp, r7
800f2ba: bd80 pop {r7, pc}
800f2bc: 0801c0c4 .word 0x0801c0c4
800f2c0: 0801c1b4 .word 0x0801c1b4
800f2c4: 0801c10c .word 0x0801c10c
800f2c8: 200086e4 .word 0x200086e4
800f2cc: 200086e8 .word 0x200086e8
800f2d0: 0801c1d8 .word 0x0801c1d8
800f2d4: 200086ec .word 0x200086ec
800f2d8: 0801c1f4 .word 0x0801c1f4
800f2dc: 0801c21c .word 0x0801c21c
800f2e0: 200086f0 .word 0x200086f0
0800f2e4 <mem_trim>:
* or NULL if newsize is > old size, in which case rmem is NOT touched
* or freed!
*/
void *
mem_trim(void *rmem, mem_size_t new_size)
{
800f2e4: b580 push {r7, lr}
800f2e6: b088 sub sp, #32
800f2e8: af00 add r7, sp, #0
800f2ea: 6078 str r0, [r7, #4]
800f2ec: 460b mov r3, r1
800f2ee: 807b strh r3, [r7, #2]
/* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
LWIP_MEM_FREE_DECL_PROTECT();
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
800f2f0: 887b ldrh r3, [r7, #2]
800f2f2: 3303 adds r3, #3
800f2f4: b29b uxth r3, r3
800f2f6: f023 0303 bic.w r3, r3, #3
800f2fa: 83fb strh r3, [r7, #30]
if (newsize < MIN_SIZE_ALIGNED) {
800f2fc: 8bfb ldrh r3, [r7, #30]
800f2fe: 2b0b cmp r3, #11
800f300: d801 bhi.n 800f306 <mem_trim+0x22>
/* every data block must be at least MIN_SIZE_ALIGNED long */
newsize = MIN_SIZE_ALIGNED;
800f302: 230c movs r3, #12
800f304: 83fb strh r3, [r7, #30]
}
#if MEM_OVERFLOW_CHECK
newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
800f306: 8bfb ldrh r3, [r7, #30]
800f308: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f30c: d803 bhi.n 800f316 <mem_trim+0x32>
800f30e: 8bfa ldrh r2, [r7, #30]
800f310: 887b ldrh r3, [r7, #2]
800f312: 429a cmp r2, r3
800f314: d201 bcs.n 800f31a <mem_trim+0x36>
return NULL;
800f316: 2300 movs r3, #0
800f318: e0d8 b.n 800f4cc <mem_trim+0x1e8>
}
LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
800f31a: 4b6e ldr r3, [pc, #440] ; (800f4d4 <mem_trim+0x1f0>)
800f31c: 681b ldr r3, [r3, #0]
800f31e: 687a ldr r2, [r7, #4]
800f320: 429a cmp r2, r3
800f322: d304 bcc.n 800f32e <mem_trim+0x4a>
800f324: 4b6c ldr r3, [pc, #432] ; (800f4d8 <mem_trim+0x1f4>)
800f326: 681b ldr r3, [r3, #0]
800f328: 687a ldr r2, [r7, #4]
800f32a: 429a cmp r2, r3
800f32c: d306 bcc.n 800f33c <mem_trim+0x58>
800f32e: 4b6b ldr r3, [pc, #428] ; (800f4dc <mem_trim+0x1f8>)
800f330: f240 22d2 movw r2, #722 ; 0x2d2
800f334: 496a ldr r1, [pc, #424] ; (800f4e0 <mem_trim+0x1fc>)
800f336: 486b ldr r0, [pc, #428] ; (800f4e4 <mem_trim+0x200>)
800f338: f00b fe74 bl 801b024 <iprintf>
(u8_t *)rmem < (u8_t *)ram_end);
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
800f33c: 4b65 ldr r3, [pc, #404] ; (800f4d4 <mem_trim+0x1f0>)
800f33e: 681b ldr r3, [r3, #0]
800f340: 687a ldr r2, [r7, #4]
800f342: 429a cmp r2, r3
800f344: d304 bcc.n 800f350 <mem_trim+0x6c>
800f346: 4b64 ldr r3, [pc, #400] ; (800f4d8 <mem_trim+0x1f4>)
800f348: 681b ldr r3, [r3, #0]
800f34a: 687a ldr r2, [r7, #4]
800f34c: 429a cmp r2, r3
800f34e: d307 bcc.n 800f360 <mem_trim+0x7c>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
/* protect mem stats from concurrent access */
MEM_STATS_INC_LOCKED(illegal);
800f350: f00b fe04 bl 801af5c <sys_arch_protect>
800f354: 60b8 str r0, [r7, #8]
800f356: 68b8 ldr r0, [r7, #8]
800f358: f00b fe0e bl 801af78 <sys_arch_unprotect>
return rmem;
800f35c: 687b ldr r3, [r7, #4]
800f35e: e0b5 b.n 800f4cc <mem_trim+0x1e8>
}
/* Get the corresponding struct mem ... */
/* cast through void* to get rid of alignment warnings */
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
800f360: 687b ldr r3, [r7, #4]
800f362: 3b08 subs r3, #8
800f364: 61bb str r3, [r7, #24]
#if MEM_OVERFLOW_CHECK
mem_overflow_check_element(mem);
#endif
/* ... and its offset pointer */
ptr = mem_to_ptr(mem);
800f366: 69b8 ldr r0, [r7, #24]
800f368: f7ff fdea bl 800ef40 <mem_to_ptr>
800f36c: 4603 mov r3, r0
800f36e: 82fb strh r3, [r7, #22]
size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
800f370: 69bb ldr r3, [r7, #24]
800f372: 881a ldrh r2, [r3, #0]
800f374: 8afb ldrh r3, [r7, #22]
800f376: 1ad3 subs r3, r2, r3
800f378: b29b uxth r3, r3
800f37a: 3b08 subs r3, #8
800f37c: 82bb strh r3, [r7, #20]
LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
800f37e: 8bfa ldrh r2, [r7, #30]
800f380: 8abb ldrh r3, [r7, #20]
800f382: 429a cmp r2, r3
800f384: d906 bls.n 800f394 <mem_trim+0xb0>
800f386: 4b55 ldr r3, [pc, #340] ; (800f4dc <mem_trim+0x1f8>)
800f388: f44f 7239 mov.w r2, #740 ; 0x2e4
800f38c: 4956 ldr r1, [pc, #344] ; (800f4e8 <mem_trim+0x204>)
800f38e: 4855 ldr r0, [pc, #340] ; (800f4e4 <mem_trim+0x200>)
800f390: f00b fe48 bl 801b024 <iprintf>
if (newsize > size) {
800f394: 8bfa ldrh r2, [r7, #30]
800f396: 8abb ldrh r3, [r7, #20]
800f398: 429a cmp r2, r3
800f39a: d901 bls.n 800f3a0 <mem_trim+0xbc>
/* not supported */
return NULL;
800f39c: 2300 movs r3, #0
800f39e: e095 b.n 800f4cc <mem_trim+0x1e8>
}
if (newsize == size) {
800f3a0: 8bfa ldrh r2, [r7, #30]
800f3a2: 8abb ldrh r3, [r7, #20]
800f3a4: 429a cmp r2, r3
800f3a6: d101 bne.n 800f3ac <mem_trim+0xc8>
/* No change in size, simply return */
return rmem;
800f3a8: 687b ldr r3, [r7, #4]
800f3aa: e08f b.n 800f4cc <mem_trim+0x1e8>
}
/* protect the heap from concurrent access */
LWIP_MEM_FREE_PROTECT();
800f3ac: 484f ldr r0, [pc, #316] ; (800f4ec <mem_trim+0x208>)
800f3ae: f00b fd93 bl 801aed8 <sys_mutex_lock>
mem2 = ptr_to_mem(mem->next);
800f3b2: 69bb ldr r3, [r7, #24]
800f3b4: 881b ldrh r3, [r3, #0]
800f3b6: 4618 mov r0, r3
800f3b8: f7ff fdb0 bl 800ef1c <ptr_to_mem>
800f3bc: 6138 str r0, [r7, #16]
if (mem2->used == 0) {
800f3be: 693b ldr r3, [r7, #16]
800f3c0: 791b ldrb r3, [r3, #4]
800f3c2: 2b00 cmp r3, #0
800f3c4: d13f bne.n 800f446 <mem_trim+0x162>
/* The next struct is unused, we can simply move it at little */
mem_size_t next;
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f3c6: 69bb ldr r3, [r7, #24]
800f3c8: 881b ldrh r3, [r3, #0]
800f3ca: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f3ce: d106 bne.n 800f3de <mem_trim+0xfa>
800f3d0: 4b42 ldr r3, [pc, #264] ; (800f4dc <mem_trim+0x1f8>)
800f3d2: f240 22f5 movw r2, #757 ; 0x2f5
800f3d6: 4946 ldr r1, [pc, #280] ; (800f4f0 <mem_trim+0x20c>)
800f3d8: 4842 ldr r0, [pc, #264] ; (800f4e4 <mem_trim+0x200>)
800f3da: f00b fe23 bl 801b024 <iprintf>
/* remember the old next pointer */
next = mem2->next;
800f3de: 693b ldr r3, [r7, #16]
800f3e0: 881b ldrh r3, [r3, #0]
800f3e2: 81bb strh r3, [r7, #12]
/* create new struct mem which is moved directly after the shrinked mem */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f3e4: 8afa ldrh r2, [r7, #22]
800f3e6: 8bfb ldrh r3, [r7, #30]
800f3e8: 4413 add r3, r2
800f3ea: b29b uxth r3, r3
800f3ec: 3308 adds r3, #8
800f3ee: 81fb strh r3, [r7, #14]
if (lfree == mem2) {
800f3f0: 4b40 ldr r3, [pc, #256] ; (800f4f4 <mem_trim+0x210>)
800f3f2: 681b ldr r3, [r3, #0]
800f3f4: 693a ldr r2, [r7, #16]
800f3f6: 429a cmp r2, r3
800f3f8: d106 bne.n 800f408 <mem_trim+0x124>
lfree = ptr_to_mem(ptr2);
800f3fa: 89fb ldrh r3, [r7, #14]
800f3fc: 4618 mov r0, r3
800f3fe: f7ff fd8d bl 800ef1c <ptr_to_mem>
800f402: 4602 mov r2, r0
800f404: 4b3b ldr r3, [pc, #236] ; (800f4f4 <mem_trim+0x210>)
800f406: 601a str r2, [r3, #0]
}
mem2 = ptr_to_mem(ptr2);
800f408: 89fb ldrh r3, [r7, #14]
800f40a: 4618 mov r0, r3
800f40c: f7ff fd86 bl 800ef1c <ptr_to_mem>
800f410: 6138 str r0, [r7, #16]
mem2->used = 0;
800f412: 693b ldr r3, [r7, #16]
800f414: 2200 movs r2, #0
800f416: 711a strb r2, [r3, #4]
/* restore the next pointer */
mem2->next = next;
800f418: 693b ldr r3, [r7, #16]
800f41a: 89ba ldrh r2, [r7, #12]
800f41c: 801a strh r2, [r3, #0]
/* link it back to mem */
mem2->prev = ptr;
800f41e: 693b ldr r3, [r7, #16]
800f420: 8afa ldrh r2, [r7, #22]
800f422: 805a strh r2, [r3, #2]
/* link mem to it */
mem->next = ptr2;
800f424: 69bb ldr r3, [r7, #24]
800f426: 89fa ldrh r2, [r7, #14]
800f428: 801a strh r2, [r3, #0]
/* last thing to restore linked list: as we have moved mem2,
* let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
* the end of the heap */
if (mem2->next != MEM_SIZE_ALIGNED) {
800f42a: 693b ldr r3, [r7, #16]
800f42c: 881b ldrh r3, [r3, #0]
800f42e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f432: d047 beq.n 800f4c4 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f434: 693b ldr r3, [r7, #16]
800f436: 881b ldrh r3, [r3, #0]
800f438: 4618 mov r0, r3
800f43a: f7ff fd6f bl 800ef1c <ptr_to_mem>
800f43e: 4602 mov r2, r0
800f440: 89fb ldrh r3, [r7, #14]
800f442: 8053 strh r3, [r2, #2]
800f444: e03e b.n 800f4c4 <mem_trim+0x1e0>
}
MEM_STATS_DEC_USED(used, (size - newsize));
/* no need to plug holes, we've already done that */
} else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
800f446: 8bfb ldrh r3, [r7, #30]
800f448: f103 0214 add.w r2, r3, #20
800f44c: 8abb ldrh r3, [r7, #20]
800f44e: 429a cmp r2, r3
800f450: d838 bhi.n 800f4c4 <mem_trim+0x1e0>
* Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
* ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory */
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
800f452: 8afa ldrh r2, [r7, #22]
800f454: 8bfb ldrh r3, [r7, #30]
800f456: 4413 add r3, r2
800f458: b29b uxth r3, r3
800f45a: 3308 adds r3, #8
800f45c: 81fb strh r3, [r7, #14]
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
800f45e: 69bb ldr r3, [r7, #24]
800f460: 881b ldrh r3, [r3, #0]
800f462: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f466: d106 bne.n 800f476 <mem_trim+0x192>
800f468: 4b1c ldr r3, [pc, #112] ; (800f4dc <mem_trim+0x1f8>)
800f46a: f240 3216 movw r2, #790 ; 0x316
800f46e: 4920 ldr r1, [pc, #128] ; (800f4f0 <mem_trim+0x20c>)
800f470: 481c ldr r0, [pc, #112] ; (800f4e4 <mem_trim+0x200>)
800f472: f00b fdd7 bl 801b024 <iprintf>
mem2 = ptr_to_mem(ptr2);
800f476: 89fb ldrh r3, [r7, #14]
800f478: 4618 mov r0, r3
800f47a: f7ff fd4f bl 800ef1c <ptr_to_mem>
800f47e: 6138 str r0, [r7, #16]
if (mem2 < lfree) {
800f480: 4b1c ldr r3, [pc, #112] ; (800f4f4 <mem_trim+0x210>)
800f482: 681b ldr r3, [r3, #0]
800f484: 693a ldr r2, [r7, #16]
800f486: 429a cmp r2, r3
800f488: d202 bcs.n 800f490 <mem_trim+0x1ac>
lfree = mem2;
800f48a: 4a1a ldr r2, [pc, #104] ; (800f4f4 <mem_trim+0x210>)
800f48c: 693b ldr r3, [r7, #16]
800f48e: 6013 str r3, [r2, #0]
}
mem2->used = 0;
800f490: 693b ldr r3, [r7, #16]
800f492: 2200 movs r2, #0
800f494: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f496: 69bb ldr r3, [r7, #24]
800f498: 881a ldrh r2, [r3, #0]
800f49a: 693b ldr r3, [r7, #16]
800f49c: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f49e: 693b ldr r3, [r7, #16]
800f4a0: 8afa ldrh r2, [r7, #22]
800f4a2: 805a strh r2, [r3, #2]
mem->next = ptr2;
800f4a4: 69bb ldr r3, [r7, #24]
800f4a6: 89fa ldrh r2, [r7, #14]
800f4a8: 801a strh r2, [r3, #0]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f4aa: 693b ldr r3, [r7, #16]
800f4ac: 881b ldrh r3, [r3, #0]
800f4ae: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f4b2: d007 beq.n 800f4c4 <mem_trim+0x1e0>
ptr_to_mem(mem2->next)->prev = ptr2;
800f4b4: 693b ldr r3, [r7, #16]
800f4b6: 881b ldrh r3, [r3, #0]
800f4b8: 4618 mov r0, r3
800f4ba: f7ff fd2f bl 800ef1c <ptr_to_mem>
800f4be: 4602 mov r2, r0
800f4c0: 89fb ldrh r3, [r7, #14]
800f4c2: 8053 strh r3, [r2, #2]
#endif
MEM_SANITY();
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_free_count = 1;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_FREE_UNPROTECT();
800f4c4: 4809 ldr r0, [pc, #36] ; (800f4ec <mem_trim+0x208>)
800f4c6: f00b fd16 bl 801aef6 <sys_mutex_unlock>
return rmem;
800f4ca: 687b ldr r3, [r7, #4]
}
800f4cc: 4618 mov r0, r3
800f4ce: 3720 adds r7, #32
800f4d0: 46bd mov sp, r7
800f4d2: bd80 pop {r7, pc}
800f4d4: 200086e4 .word 0x200086e4
800f4d8: 200086e8 .word 0x200086e8
800f4dc: 0801c0c4 .word 0x0801c0c4
800f4e0: 0801c250 .word 0x0801c250
800f4e4: 0801c10c .word 0x0801c10c
800f4e8: 0801c268 .word 0x0801c268
800f4ec: 200086ec .word 0x200086ec
800f4f0: 0801c288 .word 0x0801c288
800f4f4: 200086f0 .word 0x200086f0
0800f4f8 <mem_malloc>:
*
* Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
*/
void *
mem_malloc(mem_size_t size_in)
{
800f4f8: b580 push {r7, lr}
800f4fa: b088 sub sp, #32
800f4fc: af00 add r7, sp, #0
800f4fe: 4603 mov r3, r0
800f500: 80fb strh r3, [r7, #6]
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
u8_t local_mem_free_count = 0;
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
LWIP_MEM_ALLOC_DECL_PROTECT();
if (size_in == 0) {
800f502: 88fb ldrh r3, [r7, #6]
800f504: 2b00 cmp r3, #0
800f506: d101 bne.n 800f50c <mem_malloc+0x14>
return NULL;
800f508: 2300 movs r3, #0
800f50a: e0e2 b.n 800f6d2 <mem_malloc+0x1da>
}
/* Expand the size of the allocated memory region so that we can
adjust for alignment. */
size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
800f50c: 88fb ldrh r3, [r7, #6]
800f50e: 3303 adds r3, #3
800f510: b29b uxth r3, r3
800f512: f023 0303 bic.w r3, r3, #3
800f516: 83bb strh r3, [r7, #28]
if (size < MIN_SIZE_ALIGNED) {
800f518: 8bbb ldrh r3, [r7, #28]
800f51a: 2b0b cmp r3, #11
800f51c: d801 bhi.n 800f522 <mem_malloc+0x2a>
/* every data block must be at least MIN_SIZE_ALIGNED long */
size = MIN_SIZE_ALIGNED;
800f51e: 230c movs r3, #12
800f520: 83bb strh r3, [r7, #28]
}
#if MEM_OVERFLOW_CHECK
size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
#endif
if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
800f522: 8bbb ldrh r3, [r7, #28]
800f524: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f528: d803 bhi.n 800f532 <mem_malloc+0x3a>
800f52a: 8bba ldrh r2, [r7, #28]
800f52c: 88fb ldrh r3, [r7, #6]
800f52e: 429a cmp r2, r3
800f530: d201 bcs.n 800f536 <mem_malloc+0x3e>
return NULL;
800f532: 2300 movs r3, #0
800f534: e0cd b.n 800f6d2 <mem_malloc+0x1da>
}
/* protect the heap from concurrent access */
sys_mutex_lock(&mem_mutex);
800f536: 4869 ldr r0, [pc, #420] ; (800f6dc <mem_malloc+0x1e4>)
800f538: f00b fcce bl 801aed8 <sys_mutex_lock>
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
/* Scan through the heap searching for a free block that is big enough,
* beginning with the lowest free block.
*/
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f53c: 4b68 ldr r3, [pc, #416] ; (800f6e0 <mem_malloc+0x1e8>)
800f53e: 681b ldr r3, [r3, #0]
800f540: 4618 mov r0, r3
800f542: f7ff fcfd bl 800ef40 <mem_to_ptr>
800f546: 4603 mov r3, r0
800f548: 83fb strh r3, [r7, #30]
800f54a: e0b7 b.n 800f6bc <mem_malloc+0x1c4>
ptr = ptr_to_mem(ptr)->next) {
mem = ptr_to_mem(ptr);
800f54c: 8bfb ldrh r3, [r7, #30]
800f54e: 4618 mov r0, r3
800f550: f7ff fce4 bl 800ef1c <ptr_to_mem>
800f554: 6178 str r0, [r7, #20]
local_mem_free_count = 1;
break;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if ((!mem->used) &&
800f556: 697b ldr r3, [r7, #20]
800f558: 791b ldrb r3, [r3, #4]
800f55a: 2b00 cmp r3, #0
800f55c: f040 80a7 bne.w 800f6ae <mem_malloc+0x1b6>
(mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
800f560: 697b ldr r3, [r7, #20]
800f562: 881b ldrh r3, [r3, #0]
800f564: 461a mov r2, r3
800f566: 8bfb ldrh r3, [r7, #30]
800f568: 1ad3 subs r3, r2, r3
800f56a: f1a3 0208 sub.w r2, r3, #8
800f56e: 8bbb ldrh r3, [r7, #28]
if ((!mem->used) &&
800f570: 429a cmp r2, r3
800f572: f0c0 809c bcc.w 800f6ae <mem_malloc+0x1b6>
/* mem is not used and at least perfect fit is possible:
* mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
800f576: 697b ldr r3, [r7, #20]
800f578: 881b ldrh r3, [r3, #0]
800f57a: 461a mov r2, r3
800f57c: 8bfb ldrh r3, [r7, #30]
800f57e: 1ad3 subs r3, r2, r3
800f580: f1a3 0208 sub.w r2, r3, #8
800f584: 8bbb ldrh r3, [r7, #28]
800f586: 3314 adds r3, #20
800f588: 429a cmp r2, r3
800f58a: d333 bcc.n 800f5f4 <mem_malloc+0xfc>
* struct mem would fit in but no data between mem2 and mem2->next
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
* region that couldn't hold data, but when mem->next gets freed,
* the 2 regions would be combined, resulting in more free memory
*/
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
800f58c: 8bfa ldrh r2, [r7, #30]
800f58e: 8bbb ldrh r3, [r7, #28]
800f590: 4413 add r3, r2
800f592: b29b uxth r3, r3
800f594: 3308 adds r3, #8
800f596: 827b strh r3, [r7, #18]
LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
800f598: 8a7b ldrh r3, [r7, #18]
800f59a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f59e: d106 bne.n 800f5ae <mem_malloc+0xb6>
800f5a0: 4b50 ldr r3, [pc, #320] ; (800f6e4 <mem_malloc+0x1ec>)
800f5a2: f240 3287 movw r2, #903 ; 0x387
800f5a6: 4950 ldr r1, [pc, #320] ; (800f6e8 <mem_malloc+0x1f0>)
800f5a8: 4850 ldr r0, [pc, #320] ; (800f6ec <mem_malloc+0x1f4>)
800f5aa: f00b fd3b bl 801b024 <iprintf>
/* create mem2 struct */
mem2 = ptr_to_mem(ptr2);
800f5ae: 8a7b ldrh r3, [r7, #18]
800f5b0: 4618 mov r0, r3
800f5b2: f7ff fcb3 bl 800ef1c <ptr_to_mem>
800f5b6: 60f8 str r0, [r7, #12]
mem2->used = 0;
800f5b8: 68fb ldr r3, [r7, #12]
800f5ba: 2200 movs r2, #0
800f5bc: 711a strb r2, [r3, #4]
mem2->next = mem->next;
800f5be: 697b ldr r3, [r7, #20]
800f5c0: 881a ldrh r2, [r3, #0]
800f5c2: 68fb ldr r3, [r7, #12]
800f5c4: 801a strh r2, [r3, #0]
mem2->prev = ptr;
800f5c6: 68fb ldr r3, [r7, #12]
800f5c8: 8bfa ldrh r2, [r7, #30]
800f5ca: 805a strh r2, [r3, #2]
/* and insert it between mem and mem->next */
mem->next = ptr2;
800f5cc: 697b ldr r3, [r7, #20]
800f5ce: 8a7a ldrh r2, [r7, #18]
800f5d0: 801a strh r2, [r3, #0]
mem->used = 1;
800f5d2: 697b ldr r3, [r7, #20]
800f5d4: 2201 movs r2, #1
800f5d6: 711a strb r2, [r3, #4]
if (mem2->next != MEM_SIZE_ALIGNED) {
800f5d8: 68fb ldr r3, [r7, #12]
800f5da: 881b ldrh r3, [r3, #0]
800f5dc: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
800f5e0: d00b beq.n 800f5fa <mem_malloc+0x102>
ptr_to_mem(mem2->next)->prev = ptr2;
800f5e2: 68fb ldr r3, [r7, #12]
800f5e4: 881b ldrh r3, [r3, #0]
800f5e6: 4618 mov r0, r3
800f5e8: f7ff fc98 bl 800ef1c <ptr_to_mem>
800f5ec: 4602 mov r2, r0
800f5ee: 8a7b ldrh r3, [r7, #18]
800f5f0: 8053 strh r3, [r2, #2]
800f5f2: e002 b.n 800f5fa <mem_malloc+0x102>
* take care of this).
* -> near fit or exact fit: do not split, no mem2 creation
* also can't move mem->next directly behind mem, since mem->next
* will always be used at this point!
*/
mem->used = 1;
800f5f4: 697b ldr r3, [r7, #20]
800f5f6: 2201 movs r2, #1
800f5f8: 711a strb r2, [r3, #4]
MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
}
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
mem_malloc_adjust_lfree:
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
if (mem == lfree) {
800f5fa: 4b39 ldr r3, [pc, #228] ; (800f6e0 <mem_malloc+0x1e8>)
800f5fc: 681b ldr r3, [r3, #0]
800f5fe: 697a ldr r2, [r7, #20]
800f600: 429a cmp r2, r3
800f602: d127 bne.n 800f654 <mem_malloc+0x15c>
struct mem *cur = lfree;
800f604: 4b36 ldr r3, [pc, #216] ; (800f6e0 <mem_malloc+0x1e8>)
800f606: 681b ldr r3, [r3, #0]
800f608: 61bb str r3, [r7, #24]
/* Find next free block after mem and update lowest free pointer */
while (cur->used && cur != ram_end) {
800f60a: e005 b.n 800f618 <mem_malloc+0x120>
/* If mem_free or mem_trim have run, we have to restart since they
could have altered our current struct mem or lfree. */
goto mem_malloc_adjust_lfree;
}
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
cur = ptr_to_mem(cur->next);
800f60c: 69bb ldr r3, [r7, #24]
800f60e: 881b ldrh r3, [r3, #0]
800f610: 4618 mov r0, r3
800f612: f7ff fc83 bl 800ef1c <ptr_to_mem>
800f616: 61b8 str r0, [r7, #24]
while (cur->used && cur != ram_end) {
800f618: 69bb ldr r3, [r7, #24]
800f61a: 791b ldrb r3, [r3, #4]
800f61c: 2b00 cmp r3, #0
800f61e: d004 beq.n 800f62a <mem_malloc+0x132>
800f620: 4b33 ldr r3, [pc, #204] ; (800f6f0 <mem_malloc+0x1f8>)
800f622: 681b ldr r3, [r3, #0]
800f624: 69ba ldr r2, [r7, #24]
800f626: 429a cmp r2, r3
800f628: d1f0 bne.n 800f60c <mem_malloc+0x114>
}
lfree = cur;
800f62a: 4a2d ldr r2, [pc, #180] ; (800f6e0 <mem_malloc+0x1e8>)
800f62c: 69bb ldr r3, [r7, #24]
800f62e: 6013 str r3, [r2, #0]
LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
800f630: 4b2b ldr r3, [pc, #172] ; (800f6e0 <mem_malloc+0x1e8>)
800f632: 681a ldr r2, [r3, #0]
800f634: 4b2e ldr r3, [pc, #184] ; (800f6f0 <mem_malloc+0x1f8>)
800f636: 681b ldr r3, [r3, #0]
800f638: 429a cmp r2, r3
800f63a: d00b beq.n 800f654 <mem_malloc+0x15c>
800f63c: 4b28 ldr r3, [pc, #160] ; (800f6e0 <mem_malloc+0x1e8>)
800f63e: 681b ldr r3, [r3, #0]
800f640: 791b ldrb r3, [r3, #4]
800f642: 2b00 cmp r3, #0
800f644: d006 beq.n 800f654 <mem_malloc+0x15c>
800f646: 4b27 ldr r3, [pc, #156] ; (800f6e4 <mem_malloc+0x1ec>)
800f648: f240 32b5 movw r2, #949 ; 0x3b5
800f64c: 4929 ldr r1, [pc, #164] ; (800f6f4 <mem_malloc+0x1fc>)
800f64e: 4827 ldr r0, [pc, #156] ; (800f6ec <mem_malloc+0x1f4>)
800f650: f00b fce8 bl 801b024 <iprintf>
}
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f654: 4821 ldr r0, [pc, #132] ; (800f6dc <mem_malloc+0x1e4>)
800f656: f00b fc4e bl 801aef6 <sys_mutex_unlock>
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
800f65a: 8bba ldrh r2, [r7, #28]
800f65c: 697b ldr r3, [r7, #20]
800f65e: 4413 add r3, r2
800f660: 3308 adds r3, #8
800f662: 4a23 ldr r2, [pc, #140] ; (800f6f0 <mem_malloc+0x1f8>)
800f664: 6812 ldr r2, [r2, #0]
800f666: 4293 cmp r3, r2
800f668: d906 bls.n 800f678 <mem_malloc+0x180>
800f66a: 4b1e ldr r3, [pc, #120] ; (800f6e4 <mem_malloc+0x1ec>)
800f66c: f240 32ba movw r2, #954 ; 0x3ba
800f670: 4921 ldr r1, [pc, #132] ; (800f6f8 <mem_malloc+0x200>)
800f672: 481e ldr r0, [pc, #120] ; (800f6ec <mem_malloc+0x1f4>)
800f674: f00b fcd6 bl 801b024 <iprintf>
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
800f678: 697b ldr r3, [r7, #20]
800f67a: f003 0303 and.w r3, r3, #3
800f67e: 2b00 cmp r3, #0
800f680: d006 beq.n 800f690 <mem_malloc+0x198>
800f682: 4b18 ldr r3, [pc, #96] ; (800f6e4 <mem_malloc+0x1ec>)
800f684: f44f 726f mov.w r2, #956 ; 0x3bc
800f688: 491c ldr r1, [pc, #112] ; (800f6fc <mem_malloc+0x204>)
800f68a: 4818 ldr r0, [pc, #96] ; (800f6ec <mem_malloc+0x1f4>)
800f68c: f00b fcca bl 801b024 <iprintf>
((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
LWIP_ASSERT("mem_malloc: sanity check alignment",
800f690: 697b ldr r3, [r7, #20]
800f692: f003 0303 and.w r3, r3, #3
800f696: 2b00 cmp r3, #0
800f698: d006 beq.n 800f6a8 <mem_malloc+0x1b0>
800f69a: 4b12 ldr r3, [pc, #72] ; (800f6e4 <mem_malloc+0x1ec>)
800f69c: f240 32be movw r2, #958 ; 0x3be
800f6a0: 4917 ldr r1, [pc, #92] ; (800f700 <mem_malloc+0x208>)
800f6a2: 4812 ldr r0, [pc, #72] ; (800f6ec <mem_malloc+0x1f4>)
800f6a4: f00b fcbe bl 801b024 <iprintf>
#if MEM_OVERFLOW_CHECK
mem_overflow_init_element(mem, size_in);
#endif
MEM_SANITY();
return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
800f6a8: 697b ldr r3, [r7, #20]
800f6aa: 3308 adds r3, #8
800f6ac: e011 b.n 800f6d2 <mem_malloc+0x1da>
ptr = ptr_to_mem(ptr)->next) {
800f6ae: 8bfb ldrh r3, [r7, #30]
800f6b0: 4618 mov r0, r3
800f6b2: f7ff fc33 bl 800ef1c <ptr_to_mem>
800f6b6: 4603 mov r3, r0
800f6b8: 881b ldrh r3, [r3, #0]
800f6ba: 83fb strh r3, [r7, #30]
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
800f6bc: 8bfa ldrh r2, [r7, #30]
800f6be: 8bbb ldrh r3, [r7, #28]
800f6c0: f5c3 63c8 rsb r3, r3, #1600 ; 0x640
800f6c4: 429a cmp r2, r3
800f6c6: f4ff af41 bcc.w 800f54c <mem_malloc+0x54>
/* if we got interrupted by a mem_free, try again */
} while (local_mem_free_count != 0);
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
MEM_STATS_INC(err);
LWIP_MEM_ALLOC_UNPROTECT();
sys_mutex_unlock(&mem_mutex);
800f6ca: 4804 ldr r0, [pc, #16] ; (800f6dc <mem_malloc+0x1e4>)
800f6cc: f00b fc13 bl 801aef6 <sys_mutex_unlock>
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
return NULL;
800f6d0: 2300 movs r3, #0
}
800f6d2: 4618 mov r0, r3
800f6d4: 3720 adds r7, #32
800f6d6: 46bd mov sp, r7
800f6d8: bd80 pop {r7, pc}
800f6da: bf00 nop
800f6dc: 200086ec .word 0x200086ec
800f6e0: 200086f0 .word 0x200086f0
800f6e4: 0801c0c4 .word 0x0801c0c4
800f6e8: 0801c288 .word 0x0801c288
800f6ec: 0801c10c .word 0x0801c10c
800f6f0: 200086e8 .word 0x200086e8
800f6f4: 0801c29c .word 0x0801c29c
800f6f8: 0801c2b8 .word 0x0801c2b8
800f6fc: 0801c2e8 .word 0x0801c2e8
800f700: 0801c318 .word 0x0801c318
0800f704 <memp_init_pool>:
*
* @param desc pool to initialize
*/
void
memp_init_pool(const struct memp_desc *desc)
{
800f704: b480 push {r7}
800f706: b085 sub sp, #20
800f708: af00 add r7, sp, #0
800f70a: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(desc);
#else
int i;
struct memp *memp;
*desc->tab = NULL;
800f70c: 687b ldr r3, [r7, #4]
800f70e: 689b ldr r3, [r3, #8]
800f710: 2200 movs r2, #0
800f712: 601a str r2, [r3, #0]
memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
800f714: 687b ldr r3, [r7, #4]
800f716: 685b ldr r3, [r3, #4]
800f718: 3303 adds r3, #3
800f71a: f023 0303 bic.w r3, r3, #3
800f71e: 60bb str r3, [r7, #8]
+ MEM_SANITY_REGION_AFTER_ALIGNED
#endif
));
#endif
/* create a linked list of memp elements */
for (i = 0; i < desc->num; ++i) {
800f720: 2300 movs r3, #0
800f722: 60fb str r3, [r7, #12]
800f724: e011 b.n 800f74a <memp_init_pool+0x46>
memp->next = *desc->tab;
800f726: 687b ldr r3, [r7, #4]
800f728: 689b ldr r3, [r3, #8]
800f72a: 681a ldr r2, [r3, #0]
800f72c: 68bb ldr r3, [r7, #8]
800f72e: 601a str r2, [r3, #0]
*desc->tab = memp;
800f730: 687b ldr r3, [r7, #4]
800f732: 689b ldr r3, [r3, #8]
800f734: 68ba ldr r2, [r7, #8]
800f736: 601a str r2, [r3, #0]
#if MEMP_OVERFLOW_CHECK
memp_overflow_init_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
800f738: 687b ldr r3, [r7, #4]
800f73a: 881b ldrh r3, [r3, #0]
800f73c: 461a mov r2, r3
800f73e: 68bb ldr r3, [r7, #8]
800f740: 4413 add r3, r2
800f742: 60bb str r3, [r7, #8]
for (i = 0; i < desc->num; ++i) {
800f744: 68fb ldr r3, [r7, #12]
800f746: 3301 adds r3, #1
800f748: 60fb str r3, [r7, #12]
800f74a: 687b ldr r3, [r7, #4]
800f74c: 885b ldrh r3, [r3, #2]
800f74e: 461a mov r2, r3
800f750: 68fb ldr r3, [r7, #12]
800f752: 4293 cmp r3, r2
800f754: dbe7 blt.n 800f726 <memp_init_pool+0x22>
#endif /* !MEMP_MEM_MALLOC */
#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
desc->stats->name = desc->desc;
#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
}
800f756: bf00 nop
800f758: 3714 adds r7, #20
800f75a: 46bd mov sp, r7
800f75c: f85d 7b04 ldr.w r7, [sp], #4
800f760: 4770 bx lr
...
0800f764 <memp_init>:
*
* Carves out memp_memory into linked lists for each pool-type.
*/
void
memp_init(void)
{
800f764: b580 push {r7, lr}
800f766: b082 sub sp, #8
800f768: af00 add r7, sp, #0
u16_t i;
/* for every pool: */
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f76a: 2300 movs r3, #0
800f76c: 80fb strh r3, [r7, #6]
800f76e: e009 b.n 800f784 <memp_init+0x20>
memp_init_pool(memp_pools[i]);
800f770: 88fb ldrh r3, [r7, #6]
800f772: 4a08 ldr r2, [pc, #32] ; (800f794 <memp_init+0x30>)
800f774: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f778: 4618 mov r0, r3
800f77a: f7ff ffc3 bl 800f704 <memp_init_pool>
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
800f77e: 88fb ldrh r3, [r7, #6]
800f780: 3301 adds r3, #1
800f782: 80fb strh r3, [r7, #6]
800f784: 88fb ldrh r3, [r7, #6]
800f786: 2b0c cmp r3, #12
800f788: d9f2 bls.n 800f770 <memp_init+0xc>
#if MEMP_OVERFLOW_CHECK >= 2
/* check everything a first time to see if it worked */
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
}
800f78a: bf00 nop
800f78c: 3708 adds r7, #8
800f78e: 46bd mov sp, r7
800f790: bd80 pop {r7, pc}
800f792: bf00 nop
800f794: 08020df4 .word 0x08020df4
0800f798 <do_memp_malloc_pool>:
#if !MEMP_OVERFLOW_CHECK
do_memp_malloc_pool(const struct memp_desc *desc)
#else
do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
#endif
{
800f798: b580 push {r7, lr}
800f79a: b084 sub sp, #16
800f79c: af00 add r7, sp, #0
800f79e: 6078 str r0, [r7, #4]
#if MEMP_MEM_MALLOC
memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
SYS_ARCH_PROTECT(old_level);
#else /* MEMP_MEM_MALLOC */
SYS_ARCH_PROTECT(old_level);
800f7a0: f00b fbdc bl 801af5c <sys_arch_protect>
800f7a4: 60f8 str r0, [r7, #12]
memp = *desc->tab;
800f7a6: 687b ldr r3, [r7, #4]
800f7a8: 689b ldr r3, [r3, #8]
800f7aa: 681b ldr r3, [r3, #0]
800f7ac: 60bb str r3, [r7, #8]
#endif /* MEMP_MEM_MALLOC */
if (memp != NULL) {
800f7ae: 68bb ldr r3, [r7, #8]
800f7b0: 2b00 cmp r3, #0
800f7b2: d015 beq.n 800f7e0 <do_memp_malloc_pool+0x48>
#if !MEMP_MEM_MALLOC
#if MEMP_OVERFLOW_CHECK == 1
memp_overflow_check_element(memp, desc);
#endif /* MEMP_OVERFLOW_CHECK */
*desc->tab = memp->next;
800f7b4: 687b ldr r3, [r7, #4]
800f7b6: 689b ldr r3, [r3, #8]
800f7b8: 68ba ldr r2, [r7, #8]
800f7ba: 6812 ldr r2, [r2, #0]
800f7bc: 601a str r2, [r3, #0]
memp->line = line;
#if MEMP_MEM_MALLOC
memp_overflow_init_element(memp, desc);
#endif /* MEMP_MEM_MALLOC */
#endif /* MEMP_OVERFLOW_CHECK */
LWIP_ASSERT("memp_malloc: memp properly aligned",
800f7be: 68bb ldr r3, [r7, #8]
800f7c0: f003 0303 and.w r3, r3, #3
800f7c4: 2b00 cmp r3, #0
800f7c6: d006 beq.n 800f7d6 <do_memp_malloc_pool+0x3e>
800f7c8: 4b09 ldr r3, [pc, #36] ; (800f7f0 <do_memp_malloc_pool+0x58>)
800f7ca: f240 1219 movw r2, #281 ; 0x119
800f7ce: 4909 ldr r1, [pc, #36] ; (800f7f4 <do_memp_malloc_pool+0x5c>)
800f7d0: 4809 ldr r0, [pc, #36] ; (800f7f8 <do_memp_malloc_pool+0x60>)
800f7d2: f00b fc27 bl 801b024 <iprintf>
desc->stats->used++;
if (desc->stats->used > desc->stats->max) {
desc->stats->max = desc->stats->used;
}
#endif
SYS_ARCH_UNPROTECT(old_level);
800f7d6: 68f8 ldr r0, [r7, #12]
800f7d8: f00b fbce bl 801af78 <sys_arch_unprotect>
/* cast through u8_t* to get rid of alignment warnings */
return ((u8_t *)memp + MEMP_SIZE);
800f7dc: 68bb ldr r3, [r7, #8]
800f7de: e003 b.n 800f7e8 <do_memp_malloc_pool+0x50>
} else {
#if MEMP_STATS
desc->stats->err++;
#endif
SYS_ARCH_UNPROTECT(old_level);
800f7e0: 68f8 ldr r0, [r7, #12]
800f7e2: f00b fbc9 bl 801af78 <sys_arch_unprotect>
LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
}
return NULL;
800f7e6: 2300 movs r3, #0
}
800f7e8: 4618 mov r0, r3
800f7ea: 3710 adds r7, #16
800f7ec: 46bd mov sp, r7
800f7ee: bd80 pop {r7, pc}
800f7f0: 0801c33c .word 0x0801c33c
800f7f4: 0801c36c .word 0x0801c36c
800f7f8: 0801c390 .word 0x0801c390
0800f7fc <memp_malloc>:
#if !MEMP_OVERFLOW_CHECK
memp_malloc(memp_t type)
#else
memp_malloc_fn(memp_t type, const char *file, const int line)
#endif
{
800f7fc: b580 push {r7, lr}
800f7fe: b084 sub sp, #16
800f800: af00 add r7, sp, #0
800f802: 4603 mov r3, r0
800f804: 71fb strb r3, [r7, #7]
void *memp;
LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
800f806: 79fb ldrb r3, [r7, #7]
800f808: 2b0c cmp r3, #12
800f80a: d908 bls.n 800f81e <memp_malloc+0x22>
800f80c: 4b0a ldr r3, [pc, #40] ; (800f838 <memp_malloc+0x3c>)
800f80e: f240 1257 movw r2, #343 ; 0x157
800f812: 490a ldr r1, [pc, #40] ; (800f83c <memp_malloc+0x40>)
800f814: 480a ldr r0, [pc, #40] ; (800f840 <memp_malloc+0x44>)
800f816: f00b fc05 bl 801b024 <iprintf>
800f81a: 2300 movs r3, #0
800f81c: e008 b.n 800f830 <memp_malloc+0x34>
#if MEMP_OVERFLOW_CHECK >= 2
memp_overflow_check_all();
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
#if !MEMP_OVERFLOW_CHECK
memp = do_memp_malloc_pool(memp_pools[type]);
800f81e: 79fb ldrb r3, [r7, #7]
800f820: 4a08 ldr r2, [pc, #32] ; (800f844 <memp_malloc+0x48>)
800f822: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f826: 4618 mov r0, r3
800f828: f7ff ffb6 bl 800f798 <do_memp_malloc_pool>
800f82c: 60f8 str r0, [r7, #12]
#else
memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
#endif
return memp;
800f82e: 68fb ldr r3, [r7, #12]
}
800f830: 4618 mov r0, r3
800f832: 3710 adds r7, #16
800f834: 46bd mov sp, r7
800f836: bd80 pop {r7, pc}
800f838: 0801c33c .word 0x0801c33c
800f83c: 0801c3cc .word 0x0801c3cc
800f840: 0801c390 .word 0x0801c390
800f844: 08020df4 .word 0x08020df4
0800f848 <do_memp_free_pool>:
static void
do_memp_free_pool(const struct memp_desc *desc, void *mem)
{
800f848: b580 push {r7, lr}
800f84a: b084 sub sp, #16
800f84c: af00 add r7, sp, #0
800f84e: 6078 str r0, [r7, #4]
800f850: 6039 str r1, [r7, #0]
struct memp *memp;
SYS_ARCH_DECL_PROTECT(old_level);
LWIP_ASSERT("memp_free: mem properly aligned",
800f852: 683b ldr r3, [r7, #0]
800f854: f003 0303 and.w r3, r3, #3
800f858: 2b00 cmp r3, #0
800f85a: d006 beq.n 800f86a <do_memp_free_pool+0x22>
800f85c: 4b0d ldr r3, [pc, #52] ; (800f894 <do_memp_free_pool+0x4c>)
800f85e: f240 126d movw r2, #365 ; 0x16d
800f862: 490d ldr r1, [pc, #52] ; (800f898 <do_memp_free_pool+0x50>)
800f864: 480d ldr r0, [pc, #52] ; (800f89c <do_memp_free_pool+0x54>)
800f866: f00b fbdd bl 801b024 <iprintf>
((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
/* cast through void* to get rid of alignment warnings */
memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
800f86a: 683b ldr r3, [r7, #0]
800f86c: 60fb str r3, [r7, #12]
SYS_ARCH_PROTECT(old_level);
800f86e: f00b fb75 bl 801af5c <sys_arch_protect>
800f872: 60b8 str r0, [r7, #8]
#if MEMP_MEM_MALLOC
LWIP_UNUSED_ARG(desc);
SYS_ARCH_UNPROTECT(old_level);
mem_free(memp);
#else /* MEMP_MEM_MALLOC */
memp->next = *desc->tab;
800f874: 687b ldr r3, [r7, #4]
800f876: 689b ldr r3, [r3, #8]
800f878: 681a ldr r2, [r3, #0]
800f87a: 68fb ldr r3, [r7, #12]
800f87c: 601a str r2, [r3, #0]
*desc->tab = memp;
800f87e: 687b ldr r3, [r7, #4]
800f880: 689b ldr r3, [r3, #8]
800f882: 68fa ldr r2, [r7, #12]
800f884: 601a str r2, [r3, #0]
#if MEMP_SANITY_CHECK
LWIP_ASSERT("memp sanity", memp_sanity(desc));
#endif /* MEMP_SANITY_CHECK */
SYS_ARCH_UNPROTECT(old_level);
800f886: 68b8 ldr r0, [r7, #8]
800f888: f00b fb76 bl 801af78 <sys_arch_unprotect>
#endif /* !MEMP_MEM_MALLOC */
}
800f88c: bf00 nop
800f88e: 3710 adds r7, #16
800f890: 46bd mov sp, r7
800f892: bd80 pop {r7, pc}
800f894: 0801c33c .word 0x0801c33c
800f898: 0801c3ec .word 0x0801c3ec
800f89c: 0801c390 .word 0x0801c390
0800f8a0 <memp_free>:
* @param type the pool where to put mem
* @param mem the memp element to free
*/
void
memp_free(memp_t type, void *mem)
{
800f8a0: b580 push {r7, lr}
800f8a2: b082 sub sp, #8
800f8a4: af00 add r7, sp, #0
800f8a6: 4603 mov r3, r0
800f8a8: 6039 str r1, [r7, #0]
800f8aa: 71fb strb r3, [r7, #7]
#ifdef LWIP_HOOK_MEMP_AVAILABLE
struct memp *old_first;
#endif
LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
800f8ac: 79fb ldrb r3, [r7, #7]
800f8ae: 2b0c cmp r3, #12
800f8b0: d907 bls.n 800f8c2 <memp_free+0x22>
800f8b2: 4b0c ldr r3, [pc, #48] ; (800f8e4 <memp_free+0x44>)
800f8b4: f44f 72d5 mov.w r2, #426 ; 0x1aa
800f8b8: 490b ldr r1, [pc, #44] ; (800f8e8 <memp_free+0x48>)
800f8ba: 480c ldr r0, [pc, #48] ; (800f8ec <memp_free+0x4c>)
800f8bc: f00b fbb2 bl 801b024 <iprintf>
800f8c0: e00c b.n 800f8dc <memp_free+0x3c>
if (mem == NULL) {
800f8c2: 683b ldr r3, [r7, #0]
800f8c4: 2b00 cmp r3, #0
800f8c6: d008 beq.n 800f8da <memp_free+0x3a>
#ifdef LWIP_HOOK_MEMP_AVAILABLE
old_first = *memp_pools[type]->tab;
#endif
do_memp_free_pool(memp_pools[type], mem);
800f8c8: 79fb ldrb r3, [r7, #7]
800f8ca: 4a09 ldr r2, [pc, #36] ; (800f8f0 <memp_free+0x50>)
800f8cc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800f8d0: 6839 ldr r1, [r7, #0]
800f8d2: 4618 mov r0, r3
800f8d4: f7ff ffb8 bl 800f848 <do_memp_free_pool>
800f8d8: e000 b.n 800f8dc <memp_free+0x3c>
return;
800f8da: bf00 nop
#ifdef LWIP_HOOK_MEMP_AVAILABLE
if (old_first == NULL) {
LWIP_HOOK_MEMP_AVAILABLE(type);
}
#endif
}
800f8dc: 3708 adds r7, #8
800f8de: 46bd mov sp, r7
800f8e0: bd80 pop {r7, pc}
800f8e2: bf00 nop
800f8e4: 0801c33c .word 0x0801c33c
800f8e8: 0801c40c .word 0x0801c40c
800f8ec: 0801c390 .word 0x0801c390
800f8f0: 08020df4 .word 0x08020df4
0800f8f4 <netif_init>:
}
#endif /* LWIP_HAVE_LOOPIF */
void
netif_init(void)
{
800f8f4: b480 push {r7}
800f8f6: af00 add r7, sp, #0
netif_set_link_up(&loop_netif);
netif_set_up(&loop_netif);
#endif /* LWIP_HAVE_LOOPIF */
}
800f8f8: bf00 nop
800f8fa: 46bd mov sp, r7
800f8fc: f85d 7b04 ldr.w r7, [sp], #4
800f900: 4770 bx lr
...
0800f904 <netif_add>:
netif_add(struct netif *netif,
#if LWIP_IPV4
const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
#endif /* LWIP_IPV4 */
void *state, netif_init_fn init, netif_input_fn input)
{
800f904: b580 push {r7, lr}
800f906: b086 sub sp, #24
800f908: af00 add r7, sp, #0
800f90a: 60f8 str r0, [r7, #12]
800f90c: 60b9 str r1, [r7, #8]
800f90e: 607a str r2, [r7, #4]
800f910: 603b str r3, [r7, #0]
LWIP_ASSERT("single netif already set", 0);
return NULL;
}
#endif
LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
800f912: 68fb ldr r3, [r7, #12]
800f914: 2b00 cmp r3, #0
800f916: d108 bne.n 800f92a <netif_add+0x26>
800f918: 4b5b ldr r3, [pc, #364] ; (800fa88 <netif_add+0x184>)
800f91a: f240 1227 movw r2, #295 ; 0x127
800f91e: 495b ldr r1, [pc, #364] ; (800fa8c <netif_add+0x188>)
800f920: 485b ldr r0, [pc, #364] ; (800fa90 <netif_add+0x18c>)
800f922: f00b fb7f bl 801b024 <iprintf>
800f926: 2300 movs r3, #0
800f928: e0a9 b.n 800fa7e <netif_add+0x17a>
LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
800f92a: 6a7b ldr r3, [r7, #36] ; 0x24
800f92c: 2b00 cmp r3, #0
800f92e: d108 bne.n 800f942 <netif_add+0x3e>
800f930: 4b55 ldr r3, [pc, #340] ; (800fa88 <netif_add+0x184>)
800f932: f44f 7294 mov.w r2, #296 ; 0x128
800f936: 4957 ldr r1, [pc, #348] ; (800fa94 <netif_add+0x190>)
800f938: 4855 ldr r0, [pc, #340] ; (800fa90 <netif_add+0x18c>)
800f93a: f00b fb73 bl 801b024 <iprintf>
800f93e: 2300 movs r3, #0
800f940: e09d b.n 800fa7e <netif_add+0x17a>
#if LWIP_IPV4
if (ipaddr == NULL) {
800f942: 68bb ldr r3, [r7, #8]
800f944: 2b00 cmp r3, #0
800f946: d101 bne.n 800f94c <netif_add+0x48>
ipaddr = ip_2_ip4(IP4_ADDR_ANY);
800f948: 4b53 ldr r3, [pc, #332] ; (800fa98 <netif_add+0x194>)
800f94a: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800f94c: 687b ldr r3, [r7, #4]
800f94e: 2b00 cmp r3, #0
800f950: d101 bne.n 800f956 <netif_add+0x52>
netmask = ip_2_ip4(IP4_ADDR_ANY);
800f952: 4b51 ldr r3, [pc, #324] ; (800fa98 <netif_add+0x194>)
800f954: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800f956: 683b ldr r3, [r7, #0]
800f958: 2b00 cmp r3, #0
800f95a: d101 bne.n 800f960 <netif_add+0x5c>
gw = ip_2_ip4(IP4_ADDR_ANY);
800f95c: 4b4e ldr r3, [pc, #312] ; (800fa98 <netif_add+0x194>)
800f95e: 603b str r3, [r7, #0]
}
/* reset new interface configuration state */
ip_addr_set_zero_ip4(&netif->ip_addr);
800f960: 68fb ldr r3, [r7, #12]
800f962: 2200 movs r2, #0
800f964: 605a str r2, [r3, #4]
ip_addr_set_zero_ip4(&netif->netmask);
800f966: 68fb ldr r3, [r7, #12]
800f968: 2200 movs r2, #0
800f96a: 609a str r2, [r3, #8]
ip_addr_set_zero_ip4(&netif->gw);
800f96c: 68fb ldr r3, [r7, #12]
800f96e: 2200 movs r2, #0
800f970: 60da str r2, [r3, #12]
netif->output = netif_null_output_ip4;
800f972: 68fb ldr r3, [r7, #12]
800f974: 4a49 ldr r2, [pc, #292] ; (800fa9c <netif_add+0x198>)
800f976: 615a str r2, [r3, #20]
#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
}
netif->output_ip6 = netif_null_output_ip6;
#endif /* LWIP_IPV6 */
NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
netif->mtu = 0;
800f978: 68fb ldr r3, [r7, #12]
800f97a: 2200 movs r2, #0
800f97c: 851a strh r2, [r3, #40] ; 0x28
netif->flags = 0;
800f97e: 68fb ldr r3, [r7, #12]
800f980: 2200 movs r2, #0
800f982: f883 2031 strb.w r2, [r3, #49] ; 0x31
#ifdef netif_get_client_data
memset(netif->client_data, 0, sizeof(netif->client_data));
800f986: 68fb ldr r3, [r7, #12]
800f988: 3324 adds r3, #36 ; 0x24
800f98a: 2204 movs r2, #4
800f98c: 2100 movs r1, #0
800f98e: 4618 mov r0, r3
800f990: f00b fb40 bl 801b014 <memset>
#endif /* LWIP_IPV6 */
#if LWIP_NETIF_STATUS_CALLBACK
netif->status_callback = NULL;
#endif /* LWIP_NETIF_STATUS_CALLBACK */
#if LWIP_NETIF_LINK_CALLBACK
netif->link_callback = NULL;
800f994: 68fb ldr r3, [r7, #12]
800f996: 2200 movs r2, #0
800f998: 61da str r2, [r3, #28]
netif->loop_first = NULL;
netif->loop_last = NULL;
#endif /* ENABLE_LOOPBACK */
/* remember netif specific state information data */
netif->state = state;
800f99a: 68fb ldr r3, [r7, #12]
800f99c: 6a3a ldr r2, [r7, #32]
800f99e: 621a str r2, [r3, #32]
netif->num = netif_num;
800f9a0: 4b3f ldr r3, [pc, #252] ; (800faa0 <netif_add+0x19c>)
800f9a2: 781a ldrb r2, [r3, #0]
800f9a4: 68fb ldr r3, [r7, #12]
800f9a6: f883 2034 strb.w r2, [r3, #52] ; 0x34
netif->input = input;
800f9aa: 68fb ldr r3, [r7, #12]
800f9ac: 6aba ldr r2, [r7, #40] ; 0x28
800f9ae: 611a str r2, [r3, #16]
#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
netif->loop_cnt_current = 0;
#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
#if LWIP_IPV4
netif_set_addr(netif, ipaddr, netmask, gw);
800f9b0: 683b ldr r3, [r7, #0]
800f9b2: 687a ldr r2, [r7, #4]
800f9b4: 68b9 ldr r1, [r7, #8]
800f9b6: 68f8 ldr r0, [r7, #12]
800f9b8: f000 f914 bl 800fbe4 <netif_set_addr>
#endif /* LWIP_IPV4 */
/* call user specified initialization function for netif */
if (init(netif) != ERR_OK) {
800f9bc: 6a7b ldr r3, [r7, #36] ; 0x24
800f9be: 68f8 ldr r0, [r7, #12]
800f9c0: 4798 blx r3
800f9c2: 4603 mov r3, r0
800f9c4: 2b00 cmp r3, #0
800f9c6: d001 beq.n 800f9cc <netif_add+0xc8>
return NULL;
800f9c8: 2300 movs r3, #0
800f9ca: e058 b.n 800fa7e <netif_add+0x17a>
*/
{
struct netif *netif2;
int num_netifs;
do {
if (netif->num == 255) {
800f9cc: 68fb ldr r3, [r7, #12]
800f9ce: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800f9d2: 2bff cmp r3, #255 ; 0xff
800f9d4: d103 bne.n 800f9de <netif_add+0xda>
netif->num = 0;
800f9d6: 68fb ldr r3, [r7, #12]
800f9d8: 2200 movs r2, #0
800f9da: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
num_netifs = 0;
800f9de: 2300 movs r3, #0
800f9e0: 613b str r3, [r7, #16]
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800f9e2: 4b30 ldr r3, [pc, #192] ; (800faa4 <netif_add+0x1a0>)
800f9e4: 681b ldr r3, [r3, #0]
800f9e6: 617b str r3, [r7, #20]
800f9e8: e02b b.n 800fa42 <netif_add+0x13e>
LWIP_ASSERT("netif already added", netif2 != netif);
800f9ea: 697a ldr r2, [r7, #20]
800f9ec: 68fb ldr r3, [r7, #12]
800f9ee: 429a cmp r2, r3
800f9f0: d106 bne.n 800fa00 <netif_add+0xfc>
800f9f2: 4b25 ldr r3, [pc, #148] ; (800fa88 <netif_add+0x184>)
800f9f4: f240 128b movw r2, #395 ; 0x18b
800f9f8: 492b ldr r1, [pc, #172] ; (800faa8 <netif_add+0x1a4>)
800f9fa: 4825 ldr r0, [pc, #148] ; (800fa90 <netif_add+0x18c>)
800f9fc: f00b fb12 bl 801b024 <iprintf>
num_netifs++;
800fa00: 693b ldr r3, [r7, #16]
800fa02: 3301 adds r3, #1
800fa04: 613b str r3, [r7, #16]
LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
800fa06: 693b ldr r3, [r7, #16]
800fa08: 2bff cmp r3, #255 ; 0xff
800fa0a: dd06 ble.n 800fa1a <netif_add+0x116>
800fa0c: 4b1e ldr r3, [pc, #120] ; (800fa88 <netif_add+0x184>)
800fa0e: f240 128d movw r2, #397 ; 0x18d
800fa12: 4926 ldr r1, [pc, #152] ; (800faac <netif_add+0x1a8>)
800fa14: 481e ldr r0, [pc, #120] ; (800fa90 <netif_add+0x18c>)
800fa16: f00b fb05 bl 801b024 <iprintf>
if (netif2->num == netif->num) {
800fa1a: 697b ldr r3, [r7, #20]
800fa1c: f893 2034 ldrb.w r2, [r3, #52] ; 0x34
800fa20: 68fb ldr r3, [r7, #12]
800fa22: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa26: 429a cmp r2, r3
800fa28: d108 bne.n 800fa3c <netif_add+0x138>
netif->num++;
800fa2a: 68fb ldr r3, [r7, #12]
800fa2c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa30: 3301 adds r3, #1
800fa32: b2da uxtb r2, r3
800fa34: 68fb ldr r3, [r7, #12]
800fa36: f883 2034 strb.w r2, [r3, #52] ; 0x34
break;
800fa3a: e005 b.n 800fa48 <netif_add+0x144>
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
800fa3c: 697b ldr r3, [r7, #20]
800fa3e: 681b ldr r3, [r3, #0]
800fa40: 617b str r3, [r7, #20]
800fa42: 697b ldr r3, [r7, #20]
800fa44: 2b00 cmp r3, #0
800fa46: d1d0 bne.n 800f9ea <netif_add+0xe6>
}
}
} while (netif2 != NULL);
800fa48: 697b ldr r3, [r7, #20]
800fa4a: 2b00 cmp r3, #0
800fa4c: d1be bne.n 800f9cc <netif_add+0xc8>
}
if (netif->num == 254) {
800fa4e: 68fb ldr r3, [r7, #12]
800fa50: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa54: 2bfe cmp r3, #254 ; 0xfe
800fa56: d103 bne.n 800fa60 <netif_add+0x15c>
netif_num = 0;
800fa58: 4b11 ldr r3, [pc, #68] ; (800faa0 <netif_add+0x19c>)
800fa5a: 2200 movs r2, #0
800fa5c: 701a strb r2, [r3, #0]
800fa5e: e006 b.n 800fa6e <netif_add+0x16a>
} else {
netif_num = (u8_t)(netif->num + 1);
800fa60: 68fb ldr r3, [r7, #12]
800fa62: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800fa66: 3301 adds r3, #1
800fa68: b2da uxtb r2, r3
800fa6a: 4b0d ldr r3, [pc, #52] ; (800faa0 <netif_add+0x19c>)
800fa6c: 701a strb r2, [r3, #0]
}
/* add this netif to the list */
netif->next = netif_list;
800fa6e: 4b0d ldr r3, [pc, #52] ; (800faa4 <netif_add+0x1a0>)
800fa70: 681a ldr r2, [r3, #0]
800fa72: 68fb ldr r3, [r7, #12]
800fa74: 601a str r2, [r3, #0]
netif_list = netif;
800fa76: 4a0b ldr r2, [pc, #44] ; (800faa4 <netif_add+0x1a0>)
800fa78: 68fb ldr r3, [r7, #12]
800fa7a: 6013 str r3, [r2, #0]
#endif /* LWIP_IPV4 */
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
return netif;
800fa7c: 68fb ldr r3, [r7, #12]
}
800fa7e: 4618 mov r0, r3
800fa80: 3718 adds r7, #24
800fa82: 46bd mov sp, r7
800fa84: bd80 pop {r7, pc}
800fa86: bf00 nop
800fa88: 0801c428 .word 0x0801c428
800fa8c: 0801c4bc .word 0x0801c4bc
800fa90: 0801c478 .word 0x0801c478
800fa94: 0801c4d8 .word 0x0801c4d8
800fa98: 08020e78 .word 0x08020e78
800fa9c: 0800fec7 .word 0x0800fec7
800faa0: 20008728 .word 0x20008728
800faa4: 2000f5b0 .word 0x2000f5b0
800faa8: 0801c4fc .word 0x0801c4fc
800faac: 0801c510 .word 0x0801c510
0800fab0 <netif_do_ip_addr_changed>:
static void
netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
800fab0: b580 push {r7, lr}
800fab2: b082 sub sp, #8
800fab4: af00 add r7, sp, #0
800fab6: 6078 str r0, [r7, #4]
800fab8: 6039 str r1, [r7, #0]
#if LWIP_TCP
tcp_netif_ip_addr_changed(old_addr, new_addr);
800faba: 6839 ldr r1, [r7, #0]
800fabc: 6878 ldr r0, [r7, #4]
800fabe: f002 fb81 bl 80121c4 <tcp_netif_ip_addr_changed>
#endif /* LWIP_TCP */
#if LWIP_UDP
udp_netif_ip_addr_changed(old_addr, new_addr);
800fac2: 6839 ldr r1, [r7, #0]
800fac4: 6878 ldr r0, [r7, #4]
800fac6: f006 ffa1 bl 8016a0c <udp_netif_ip_addr_changed>
#endif /* LWIP_UDP */
#if LWIP_RAW
raw_netif_ip_addr_changed(old_addr, new_addr);
#endif /* LWIP_RAW */
}
800faca: bf00 nop
800facc: 3708 adds r7, #8
800face: 46bd mov sp, r7
800fad0: bd80 pop {r7, pc}
...
0800fad4 <netif_do_set_ipaddr>:
#if LWIP_IPV4
static int
netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
{
800fad4: b580 push {r7, lr}
800fad6: b086 sub sp, #24
800fad8: af00 add r7, sp, #0
800fada: 60f8 str r0, [r7, #12]
800fadc: 60b9 str r1, [r7, #8]
800fade: 607a str r2, [r7, #4]
LWIP_ASSERT("invalid pointer", ipaddr != NULL);
800fae0: 68bb ldr r3, [r7, #8]
800fae2: 2b00 cmp r3, #0
800fae4: d106 bne.n 800faf4 <netif_do_set_ipaddr+0x20>
800fae6: 4b1d ldr r3, [pc, #116] ; (800fb5c <netif_do_set_ipaddr+0x88>)
800fae8: f240 12cb movw r2, #459 ; 0x1cb
800faec: 491c ldr r1, [pc, #112] ; (800fb60 <netif_do_set_ipaddr+0x8c>)
800faee: 481d ldr r0, [pc, #116] ; (800fb64 <netif_do_set_ipaddr+0x90>)
800faf0: f00b fa98 bl 801b024 <iprintf>
LWIP_ASSERT("invalid pointer", old_addr != NULL);
800faf4: 687b ldr r3, [r7, #4]
800faf6: 2b00 cmp r3, #0
800faf8: d106 bne.n 800fb08 <netif_do_set_ipaddr+0x34>
800fafa: 4b18 ldr r3, [pc, #96] ; (800fb5c <netif_do_set_ipaddr+0x88>)
800fafc: f44f 72e6 mov.w r2, #460 ; 0x1cc
800fb00: 4917 ldr r1, [pc, #92] ; (800fb60 <netif_do_set_ipaddr+0x8c>)
800fb02: 4818 ldr r0, [pc, #96] ; (800fb64 <netif_do_set_ipaddr+0x90>)
800fb04: f00b fa8e bl 801b024 <iprintf>
/* address is actually being changed? */
if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
800fb08: 68bb ldr r3, [r7, #8]
800fb0a: 681a ldr r2, [r3, #0]
800fb0c: 68fb ldr r3, [r7, #12]
800fb0e: 3304 adds r3, #4
800fb10: 681b ldr r3, [r3, #0]
800fb12: 429a cmp r2, r3
800fb14: d01c beq.n 800fb50 <netif_do_set_ipaddr+0x7c>
ip_addr_t new_addr;
*ip_2_ip4(&new_addr) = *ipaddr;
800fb16: 68bb ldr r3, [r7, #8]
800fb18: 681b ldr r3, [r3, #0]
800fb1a: 617b str r3, [r7, #20]
IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
800fb1c: 68fb ldr r3, [r7, #12]
800fb1e: 3304 adds r3, #4
800fb20: 681a ldr r2, [r3, #0]
800fb22: 687b ldr r3, [r7, #4]
800fb24: 601a str r2, [r3, #0]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
netif_do_ip_addr_changed(old_addr, &new_addr);
800fb26: f107 0314 add.w r3, r7, #20
800fb2a: 4619 mov r1, r3
800fb2c: 6878 ldr r0, [r7, #4]
800fb2e: f7ff ffbf bl 800fab0 <netif_do_ip_addr_changed>
mib2_remove_ip4(netif);
mib2_remove_route_ip4(0, netif);
/* set new IP address to netif */
ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
800fb32: 68bb ldr r3, [r7, #8]
800fb34: 2b00 cmp r3, #0
800fb36: d002 beq.n 800fb3e <netif_do_set_ipaddr+0x6a>
800fb38: 68bb ldr r3, [r7, #8]
800fb3a: 681b ldr r3, [r3, #0]
800fb3c: e000 b.n 800fb40 <netif_do_set_ipaddr+0x6c>
800fb3e: 2300 movs r3, #0
800fb40: 68fa ldr r2, [r7, #12]
800fb42: 6053 str r3, [r2, #4]
IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
mib2_add_ip4(netif);
mib2_add_route_ip4(0, netif);
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
800fb44: 2101 movs r1, #1
800fb46: 68f8 ldr r0, [r7, #12]
800fb48: f000 f8d2 bl 800fcf0 <netif_issue_reports>
NETIF_STATUS_CALLBACK(netif);
return 1; /* address changed */
800fb4c: 2301 movs r3, #1
800fb4e: e000 b.n 800fb52 <netif_do_set_ipaddr+0x7e>
}
return 0; /* address unchanged */
800fb50: 2300 movs r3, #0
}
800fb52: 4618 mov r0, r3
800fb54: 3718 adds r7, #24
800fb56: 46bd mov sp, r7
800fb58: bd80 pop {r7, pc}
800fb5a: bf00 nop
800fb5c: 0801c428 .word 0x0801c428
800fb60: 0801c540 .word 0x0801c540
800fb64: 0801c478 .word 0x0801c478
0800fb68 <netif_do_set_netmask>:
}
}
static int
netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
{
800fb68: b480 push {r7}
800fb6a: b085 sub sp, #20
800fb6c: af00 add r7, sp, #0
800fb6e: 60f8 str r0, [r7, #12]
800fb70: 60b9 str r1, [r7, #8]
800fb72: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
800fb74: 68bb ldr r3, [r7, #8]
800fb76: 681a ldr r2, [r3, #0]
800fb78: 68fb ldr r3, [r7, #12]
800fb7a: 3308 adds r3, #8
800fb7c: 681b ldr r3, [r3, #0]
800fb7e: 429a cmp r2, r3
800fb80: d00a beq.n 800fb98 <netif_do_set_netmask+0x30>
#else
LWIP_UNUSED_ARG(old_nm);
#endif
mib2_remove_route_ip4(0, netif);
/* set new netmask to netif */
ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
800fb82: 68bb ldr r3, [r7, #8]
800fb84: 2b00 cmp r3, #0
800fb86: d002 beq.n 800fb8e <netif_do_set_netmask+0x26>
800fb88: 68bb ldr r3, [r7, #8]
800fb8a: 681b ldr r3, [r3, #0]
800fb8c: e000 b.n 800fb90 <netif_do_set_netmask+0x28>
800fb8e: 2300 movs r3, #0
800fb90: 68fa ldr r2, [r7, #12]
800fb92: 6093 str r3, [r2, #8]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_netmask(netif)),
ip4_addr2_16(netif_ip4_netmask(netif)),
ip4_addr3_16(netif_ip4_netmask(netif)),
ip4_addr4_16(netif_ip4_netmask(netif))));
return 1; /* netmask changed */
800fb94: 2301 movs r3, #1
800fb96: e000 b.n 800fb9a <netif_do_set_netmask+0x32>
}
return 0; /* netmask unchanged */
800fb98: 2300 movs r3, #0
}
800fb9a: 4618 mov r0, r3
800fb9c: 3714 adds r7, #20
800fb9e: 46bd mov sp, r7
800fba0: f85d 7b04 ldr.w r7, [sp], #4
800fba4: 4770 bx lr
0800fba6 <netif_do_set_gw>:
}
}
static int
netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
{
800fba6: b480 push {r7}
800fba8: b085 sub sp, #20
800fbaa: af00 add r7, sp, #0
800fbac: 60f8 str r0, [r7, #12]
800fbae: 60b9 str r1, [r7, #8]
800fbb0: 607a str r2, [r7, #4]
/* address is actually being changed? */
if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
800fbb2: 68bb ldr r3, [r7, #8]
800fbb4: 681a ldr r2, [r3, #0]
800fbb6: 68fb ldr r3, [r7, #12]
800fbb8: 330c adds r3, #12
800fbba: 681b ldr r3, [r3, #0]
800fbbc: 429a cmp r2, r3
800fbbe: d00a beq.n 800fbd6 <netif_do_set_gw+0x30>
ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
#else
LWIP_UNUSED_ARG(old_gw);
#endif
ip4_addr_set(ip_2_ip4(&netif->gw), gw);
800fbc0: 68bb ldr r3, [r7, #8]
800fbc2: 2b00 cmp r3, #0
800fbc4: d002 beq.n 800fbcc <netif_do_set_gw+0x26>
800fbc6: 68bb ldr r3, [r7, #8]
800fbc8: 681b ldr r3, [r3, #0]
800fbca: e000 b.n 800fbce <netif_do_set_gw+0x28>
800fbcc: 2300 movs r3, #0
800fbce: 68fa ldr r2, [r7, #12]
800fbd0: 60d3 str r3, [r2, #12]
netif->name[0], netif->name[1],
ip4_addr1_16(netif_ip4_gw(netif)),
ip4_addr2_16(netif_ip4_gw(netif)),
ip4_addr3_16(netif_ip4_gw(netif)),
ip4_addr4_16(netif_ip4_gw(netif))));
return 1; /* gateway changed */
800fbd2: 2301 movs r3, #1
800fbd4: e000 b.n 800fbd8 <netif_do_set_gw+0x32>
}
return 0; /* gateway unchanged */
800fbd6: 2300 movs r3, #0
}
800fbd8: 4618 mov r0, r3
800fbda: 3714 adds r7, #20
800fbdc: 46bd mov sp, r7
800fbde: f85d 7b04 ldr.w r7, [sp], #4
800fbe2: 4770 bx lr
0800fbe4 <netif_set_addr>:
* @param gw the new default gateway
*/
void
netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
const ip4_addr_t *gw)
{
800fbe4: b580 push {r7, lr}
800fbe6: b088 sub sp, #32
800fbe8: af00 add r7, sp, #0
800fbea: 60f8 str r0, [r7, #12]
800fbec: 60b9 str r1, [r7, #8]
800fbee: 607a str r2, [r7, #4]
800fbf0: 603b str r3, [r7, #0]
ip_addr_t old_nm_val;
ip_addr_t old_gw_val;
ip_addr_t *old_nm = &old_nm_val;
ip_addr_t *old_gw = &old_gw_val;
#else
ip_addr_t *old_nm = NULL;
800fbf2: 2300 movs r3, #0
800fbf4: 61fb str r3, [r7, #28]
ip_addr_t *old_gw = NULL;
800fbf6: 2300 movs r3, #0
800fbf8: 61bb str r3, [r7, #24]
int remove;
LWIP_ASSERT_CORE_LOCKED();
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
800fbfa: 68bb ldr r3, [r7, #8]
800fbfc: 2b00 cmp r3, #0
800fbfe: d101 bne.n 800fc04 <netif_set_addr+0x20>
ipaddr = IP4_ADDR_ANY4;
800fc00: 4b1c ldr r3, [pc, #112] ; (800fc74 <netif_set_addr+0x90>)
800fc02: 60bb str r3, [r7, #8]
}
if (netmask == NULL) {
800fc04: 687b ldr r3, [r7, #4]
800fc06: 2b00 cmp r3, #0
800fc08: d101 bne.n 800fc0e <netif_set_addr+0x2a>
netmask = IP4_ADDR_ANY4;
800fc0a: 4b1a ldr r3, [pc, #104] ; (800fc74 <netif_set_addr+0x90>)
800fc0c: 607b str r3, [r7, #4]
}
if (gw == NULL) {
800fc0e: 683b ldr r3, [r7, #0]
800fc10: 2b00 cmp r3, #0
800fc12: d101 bne.n 800fc18 <netif_set_addr+0x34>
gw = IP4_ADDR_ANY4;
800fc14: 4b17 ldr r3, [pc, #92] ; (800fc74 <netif_set_addr+0x90>)
800fc16: 603b str r3, [r7, #0]
}
remove = ip4_addr_isany(ipaddr);
800fc18: 68bb ldr r3, [r7, #8]
800fc1a: 2b00 cmp r3, #0
800fc1c: d003 beq.n 800fc26 <netif_set_addr+0x42>
800fc1e: 68bb ldr r3, [r7, #8]
800fc20: 681b ldr r3, [r3, #0]
800fc22: 2b00 cmp r3, #0
800fc24: d101 bne.n 800fc2a <netif_set_addr+0x46>
800fc26: 2301 movs r3, #1
800fc28: e000 b.n 800fc2c <netif_set_addr+0x48>
800fc2a: 2300 movs r3, #0
800fc2c: 617b str r3, [r7, #20]
if (remove) {
800fc2e: 697b ldr r3, [r7, #20]
800fc30: 2b00 cmp r3, #0
800fc32: d006 beq.n 800fc42 <netif_set_addr+0x5e>
/* when removing an address, we have to remove it *before* changing netmask/gw
to ensure that tcp RST segment can be sent correctly */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fc34: f107 0310 add.w r3, r7, #16
800fc38: 461a mov r2, r3
800fc3a: 68b9 ldr r1, [r7, #8]
800fc3c: 68f8 ldr r0, [r7, #12]
800fc3e: f7ff ff49 bl 800fad4 <netif_do_set_ipaddr>
change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
cb_args.ipv4_changed.old_address = &old_addr;
#endif
}
}
if (netif_do_set_netmask(netif, netmask, old_nm)) {
800fc42: 69fa ldr r2, [r7, #28]
800fc44: 6879 ldr r1, [r7, #4]
800fc46: 68f8 ldr r0, [r7, #12]
800fc48: f7ff ff8e bl 800fb68 <netif_do_set_netmask>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
cb_args.ipv4_changed.old_netmask = old_nm;
#endif
}
if (netif_do_set_gw(netif, gw, old_gw)) {
800fc4c: 69ba ldr r2, [r7, #24]
800fc4e: 6839 ldr r1, [r7, #0]
800fc50: 68f8 ldr r0, [r7, #12]
800fc52: f7ff ffa8 bl 800fba6 <netif_do_set_gw>
#if LWIP_NETIF_EXT_STATUS_CALLBACK
change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
cb_args.ipv4_changed.old_gw = old_gw;
#endif
}
if (!remove) {
800fc56: 697b ldr r3, [r7, #20]
800fc58: 2b00 cmp r3, #0
800fc5a: d106 bne.n 800fc6a <netif_set_addr+0x86>
/* set ipaddr last to ensure netmask/gw have been set when status callback is called */
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
800fc5c: f107 0310 add.w r3, r7, #16
800fc60: 461a mov r2, r3
800fc62: 68b9 ldr r1, [r7, #8]
800fc64: 68f8 ldr r0, [r7, #12]
800fc66: f7ff ff35 bl 800fad4 <netif_do_set_ipaddr>
if (change_reason != LWIP_NSC_NONE) {
change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
netif_invoke_ext_callback(netif, change_reason, &cb_args);
}
#endif
}
800fc6a: bf00 nop
800fc6c: 3720 adds r7, #32
800fc6e: 46bd mov sp, r7
800fc70: bd80 pop {r7, pc}
800fc72: bf00 nop
800fc74: 08020e78 .word 0x08020e78
0800fc78 <netif_set_default>:
*
* @param netif the default network interface
*/
void
netif_set_default(struct netif *netif)
{
800fc78: b480 push {r7}
800fc7a: b083 sub sp, #12
800fc7c: af00 add r7, sp, #0
800fc7e: 6078 str r0, [r7, #4]
mib2_remove_route_ip4(1, netif);
} else {
/* install default route */
mib2_add_route_ip4(1, netif);
}
netif_default = netif;
800fc80: 4a04 ldr r2, [pc, #16] ; (800fc94 <netif_set_default+0x1c>)
800fc82: 687b ldr r3, [r7, #4]
800fc84: 6013 str r3, [r2, #0]
LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
}
800fc86: bf00 nop
800fc88: 370c adds r7, #12
800fc8a: 46bd mov sp, r7
800fc8c: f85d 7b04 ldr.w r7, [sp], #4
800fc90: 4770 bx lr
800fc92: bf00 nop
800fc94: 2000f5b4 .word 0x2000f5b4
0800fc98 <netif_set_up>:
* Bring an interface up, available for processing
* traffic.
*/
void
netif_set_up(struct netif *netif)
{
800fc98: b580 push {r7, lr}
800fc9a: b082 sub sp, #8
800fc9c: af00 add r7, sp, #0
800fc9e: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
800fca0: 687b ldr r3, [r7, #4]
800fca2: 2b00 cmp r3, #0
800fca4: d107 bne.n 800fcb6 <netif_set_up+0x1e>
800fca6: 4b0f ldr r3, [pc, #60] ; (800fce4 <netif_set_up+0x4c>)
800fca8: f44f 7254 mov.w r2, #848 ; 0x350
800fcac: 490e ldr r1, [pc, #56] ; (800fce8 <netif_set_up+0x50>)
800fcae: 480f ldr r0, [pc, #60] ; (800fcec <netif_set_up+0x54>)
800fcb0: f00b f9b8 bl 801b024 <iprintf>
800fcb4: e013 b.n 800fcde <netif_set_up+0x46>
if (!(netif->flags & NETIF_FLAG_UP)) {
800fcb6: 687b ldr r3, [r7, #4]
800fcb8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcbc: f003 0301 and.w r3, r3, #1
800fcc0: 2b00 cmp r3, #0
800fcc2: d10c bne.n 800fcde <netif_set_up+0x46>
netif_set_flags(netif, NETIF_FLAG_UP);
800fcc4: 687b ldr r3, [r7, #4]
800fcc6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fcca: f043 0301 orr.w r3, r3, #1
800fcce: b2da uxtb r2, r3
800fcd0: 687b ldr r3, [r7, #4]
800fcd2: f883 2031 strb.w r2, [r3, #49] ; 0x31
args.status_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fcd6: 2103 movs r1, #3
800fcd8: 6878 ldr r0, [r7, #4]
800fcda: f000 f809 bl 800fcf0 <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
}
}
800fcde: 3708 adds r7, #8
800fce0: 46bd mov sp, r7
800fce2: bd80 pop {r7, pc}
800fce4: 0801c428 .word 0x0801c428
800fce8: 0801c5b0 .word 0x0801c5b0
800fcec: 0801c478 .word 0x0801c478
0800fcf0 <netif_issue_reports>:
/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
*/
static void
netif_issue_reports(struct netif *netif, u8_t report_type)
{
800fcf0: b580 push {r7, lr}
800fcf2: b082 sub sp, #8
800fcf4: af00 add r7, sp, #0
800fcf6: 6078 str r0, [r7, #4]
800fcf8: 460b mov r3, r1
800fcfa: 70fb strb r3, [r7, #3]
LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
800fcfc: 687b ldr r3, [r7, #4]
800fcfe: 2b00 cmp r3, #0
800fd00: d106 bne.n 800fd10 <netif_issue_reports+0x20>
800fd02: 4b18 ldr r3, [pc, #96] ; (800fd64 <netif_issue_reports+0x74>)
800fd04: f240 326d movw r2, #877 ; 0x36d
800fd08: 4917 ldr r1, [pc, #92] ; (800fd68 <netif_issue_reports+0x78>)
800fd0a: 4818 ldr r0, [pc, #96] ; (800fd6c <netif_issue_reports+0x7c>)
800fd0c: f00b f98a bl 801b024 <iprintf>
/* Only send reports when both link and admin states are up */
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fd10: 687b ldr r3, [r7, #4]
800fd12: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd16: f003 0304 and.w r3, r3, #4
800fd1a: 2b00 cmp r3, #0
800fd1c: d01e beq.n 800fd5c <netif_issue_reports+0x6c>
!(netif->flags & NETIF_FLAG_UP)) {
800fd1e: 687b ldr r3, [r7, #4]
800fd20: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd24: f003 0301 and.w r3, r3, #1
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
800fd28: 2b00 cmp r3, #0
800fd2a: d017 beq.n 800fd5c <netif_issue_reports+0x6c>
return;
}
#if LWIP_IPV4
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fd2c: 78fb ldrb r3, [r7, #3]
800fd2e: f003 0301 and.w r3, r3, #1
800fd32: 2b00 cmp r3, #0
800fd34: d013 beq.n 800fd5e <netif_issue_reports+0x6e>
!ip4_addr_isany_val(*netif_ip4_addr(netif))) {
800fd36: 687b ldr r3, [r7, #4]
800fd38: 3304 adds r3, #4
800fd3a: 681b ldr r3, [r3, #0]
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
800fd3c: 2b00 cmp r3, #0
800fd3e: d00e beq.n 800fd5e <netif_issue_reports+0x6e>
#if LWIP_ARP
/* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
if (netif->flags & (NETIF_FLAG_ETHARP)) {
800fd40: 687b ldr r3, [r7, #4]
800fd42: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd46: f003 0308 and.w r3, r3, #8
800fd4a: 2b00 cmp r3, #0
800fd4c: d007 beq.n 800fd5e <netif_issue_reports+0x6e>
etharp_gratuitous(netif);
800fd4e: 687b ldr r3, [r7, #4]
800fd50: 3304 adds r3, #4
800fd52: 4619 mov r1, r3
800fd54: 6878 ldr r0, [r7, #4]
800fd56: f009 fc6b bl 8019630 <etharp_request>
800fd5a: e000 b.n 800fd5e <netif_issue_reports+0x6e>
return;
800fd5c: bf00 nop
/* send mld memberships */
mld6_report_groups(netif);
#endif /* LWIP_IPV6_MLD */
}
#endif /* LWIP_IPV6 */
}
800fd5e: 3708 adds r7, #8
800fd60: 46bd mov sp, r7
800fd62: bd80 pop {r7, pc}
800fd64: 0801c428 .word 0x0801c428
800fd68: 0801c5cc .word 0x0801c5cc
800fd6c: 0801c478 .word 0x0801c478
0800fd70 <netif_set_down>:
* @ingroup netif
* Bring an interface down, disabling any traffic processing.
*/
void
netif_set_down(struct netif *netif)
{
800fd70: b580 push {r7, lr}
800fd72: b082 sub sp, #8
800fd74: af00 add r7, sp, #0
800fd76: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
800fd78: 687b ldr r3, [r7, #4]
800fd7a: 2b00 cmp r3, #0
800fd7c: d107 bne.n 800fd8e <netif_set_down+0x1e>
800fd7e: 4b12 ldr r3, [pc, #72] ; (800fdc8 <netif_set_down+0x58>)
800fd80: f240 329b movw r2, #923 ; 0x39b
800fd84: 4911 ldr r1, [pc, #68] ; (800fdcc <netif_set_down+0x5c>)
800fd86: 4812 ldr r0, [pc, #72] ; (800fdd0 <netif_set_down+0x60>)
800fd88: f00b f94c bl 801b024 <iprintf>
800fd8c: e019 b.n 800fdc2 <netif_set_down+0x52>
if (netif->flags & NETIF_FLAG_UP) {
800fd8e: 687b ldr r3, [r7, #4]
800fd90: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fd94: f003 0301 and.w r3, r3, #1
800fd98: 2b00 cmp r3, #0
800fd9a: d012 beq.n 800fdc2 <netif_set_down+0x52>
args.status_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
}
#endif
netif_clear_flags(netif, NETIF_FLAG_UP);
800fd9c: 687b ldr r3, [r7, #4]
800fd9e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fda2: f023 0301 bic.w r3, r3, #1
800fda6: b2da uxtb r2, r3
800fda8: 687b ldr r3, [r7, #4]
800fdaa: f883 2031 strb.w r2, [r3, #49] ; 0x31
MIB2_COPY_SYSUPTIME_TO(&netif->ts);
#if LWIP_IPV4 && LWIP_ARP
if (netif->flags & NETIF_FLAG_ETHARP) {
800fdae: 687b ldr r3, [r7, #4]
800fdb0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fdb4: f003 0308 and.w r3, r3, #8
800fdb8: 2b00 cmp r3, #0
800fdba: d002 beq.n 800fdc2 <netif_set_down+0x52>
etharp_cleanup_netif(netif);
800fdbc: 6878 ldr r0, [r7, #4]
800fdbe: f008 fff1 bl 8018da4 <etharp_cleanup_netif>
nd6_cleanup_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_STATUS_CALLBACK(netif);
}
}
800fdc2: 3708 adds r7, #8
800fdc4: 46bd mov sp, r7
800fdc6: bd80 pop {r7, pc}
800fdc8: 0801c428 .word 0x0801c428
800fdcc: 0801c5f0 .word 0x0801c5f0
800fdd0: 0801c478 .word 0x0801c478
0800fdd4 <netif_set_link_up>:
* @ingroup netif
* Called by a driver when its link goes up
*/
void
netif_set_link_up(struct netif *netif)
{
800fdd4: b580 push {r7, lr}
800fdd6: b082 sub sp, #8
800fdd8: af00 add r7, sp, #0
800fdda: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
800fddc: 687b ldr r3, [r7, #4]
800fdde: 2b00 cmp r3, #0
800fde0: d107 bne.n 800fdf2 <netif_set_link_up+0x1e>
800fde2: 4b15 ldr r3, [pc, #84] ; (800fe38 <netif_set_link_up+0x64>)
800fde4: f44f 7278 mov.w r2, #992 ; 0x3e0
800fde8: 4914 ldr r1, [pc, #80] ; (800fe3c <netif_set_link_up+0x68>)
800fdea: 4815 ldr r0, [pc, #84] ; (800fe40 <netif_set_link_up+0x6c>)
800fdec: f00b f91a bl 801b024 <iprintf>
800fdf0: e01e b.n 800fe30 <netif_set_link_up+0x5c>
if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
800fdf2: 687b ldr r3, [r7, #4]
800fdf4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fdf8: f003 0304 and.w r3, r3, #4
800fdfc: 2b00 cmp r3, #0
800fdfe: d117 bne.n 800fe30 <netif_set_link_up+0x5c>
netif_set_flags(netif, NETIF_FLAG_LINK_UP);
800fe00: 687b ldr r3, [r7, #4]
800fe02: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe06: f043 0304 orr.w r3, r3, #4
800fe0a: b2da uxtb r2, r3
800fe0c: 687b ldr r3, [r7, #4]
800fe0e: f883 2031 strb.w r2, [r3, #49] ; 0x31
#if LWIP_DHCP
dhcp_network_changed(netif);
800fe12: 6878 ldr r0, [r7, #4]
800fe14: f007 fa26 bl 8017264 <dhcp_network_changed>
#if LWIP_AUTOIP
autoip_network_changed(netif);
#endif /* LWIP_AUTOIP */
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
800fe18: 2103 movs r1, #3
800fe1a: 6878 ldr r0, [r7, #4]
800fe1c: f7ff ff68 bl 800fcf0 <netif_issue_reports>
#if LWIP_IPV6
nd6_restart_netif(netif);
#endif /* LWIP_IPV6 */
NETIF_LINK_CALLBACK(netif);
800fe20: 687b ldr r3, [r7, #4]
800fe22: 69db ldr r3, [r3, #28]
800fe24: 2b00 cmp r3, #0
800fe26: d003 beq.n 800fe30 <netif_set_link_up+0x5c>
800fe28: 687b ldr r3, [r7, #4]
800fe2a: 69db ldr r3, [r3, #28]
800fe2c: 6878 ldr r0, [r7, #4]
800fe2e: 4798 blx r3
args.link_changed.state = 1;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fe30: 3708 adds r7, #8
800fe32: 46bd mov sp, r7
800fe34: bd80 pop {r7, pc}
800fe36: bf00 nop
800fe38: 0801c428 .word 0x0801c428
800fe3c: 0801c610 .word 0x0801c610
800fe40: 0801c478 .word 0x0801c478
0800fe44 <netif_set_link_down>:
* @ingroup netif
* Called by a driver when its link goes down
*/
void
netif_set_link_down(struct netif *netif)
{
800fe44: b580 push {r7, lr}
800fe46: b082 sub sp, #8
800fe48: af00 add r7, sp, #0
800fe4a: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
800fe4c: 687b ldr r3, [r7, #4]
800fe4e: 2b00 cmp r3, #0
800fe50: d107 bne.n 800fe62 <netif_set_link_down+0x1e>
800fe52: 4b11 ldr r3, [pc, #68] ; (800fe98 <netif_set_link_down+0x54>)
800fe54: f240 4206 movw r2, #1030 ; 0x406
800fe58: 4910 ldr r1, [pc, #64] ; (800fe9c <netif_set_link_down+0x58>)
800fe5a: 4811 ldr r0, [pc, #68] ; (800fea0 <netif_set_link_down+0x5c>)
800fe5c: f00b f8e2 bl 801b024 <iprintf>
800fe60: e017 b.n 800fe92 <netif_set_link_down+0x4e>
if (netif->flags & NETIF_FLAG_LINK_UP) {
800fe62: 687b ldr r3, [r7, #4]
800fe64: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe68: f003 0304 and.w r3, r3, #4
800fe6c: 2b00 cmp r3, #0
800fe6e: d010 beq.n 800fe92 <netif_set_link_down+0x4e>
netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
800fe70: 687b ldr r3, [r7, #4]
800fe72: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
800fe76: f023 0304 bic.w r3, r3, #4
800fe7a: b2da uxtb r2, r3
800fe7c: 687b ldr r3, [r7, #4]
800fe7e: f883 2031 strb.w r2, [r3, #49] ; 0x31
NETIF_LINK_CALLBACK(netif);
800fe82: 687b ldr r3, [r7, #4]
800fe84: 69db ldr r3, [r3, #28]
800fe86: 2b00 cmp r3, #0
800fe88: d003 beq.n 800fe92 <netif_set_link_down+0x4e>
800fe8a: 687b ldr r3, [r7, #4]
800fe8c: 69db ldr r3, [r3, #28]
800fe8e: 6878 ldr r0, [r7, #4]
800fe90: 4798 blx r3
args.link_changed.state = 0;
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
}
#endif
}
}
800fe92: 3708 adds r7, #8
800fe94: 46bd mov sp, r7
800fe96: bd80 pop {r7, pc}
800fe98: 0801c428 .word 0x0801c428
800fe9c: 0801c634 .word 0x0801c634
800fea0: 0801c478 .word 0x0801c478
0800fea4 <netif_set_link_callback>:
* @ingroup netif
* Set callback to be called when link is brought up/down
*/
void
netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
{
800fea4: b480 push {r7}
800fea6: b083 sub sp, #12
800fea8: af00 add r7, sp, #0
800feaa: 6078 str r0, [r7, #4]
800feac: 6039 str r1, [r7, #0]
LWIP_ASSERT_CORE_LOCKED();
if (netif) {
800feae: 687b ldr r3, [r7, #4]
800feb0: 2b00 cmp r3, #0
800feb2: d002 beq.n 800feba <netif_set_link_callback+0x16>
netif->link_callback = link_callback;
800feb4: 687b ldr r3, [r7, #4]
800feb6: 683a ldr r2, [r7, #0]
800feb8: 61da str r2, [r3, #28]
}
}
800feba: bf00 nop
800febc: 370c adds r7, #12
800febe: 46bd mov sp, r7
800fec0: f85d 7b04 ldr.w r7, [sp], #4
800fec4: 4770 bx lr
0800fec6 <netif_null_output_ip4>:
#if LWIP_IPV4
/** Dummy IPv4 output function for netifs not supporting IPv4
*/
static err_t
netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
{
800fec6: b480 push {r7}
800fec8: b085 sub sp, #20
800feca: af00 add r7, sp, #0
800fecc: 60f8 str r0, [r7, #12]
800fece: 60b9 str r1, [r7, #8]
800fed0: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(netif);
LWIP_UNUSED_ARG(p);
LWIP_UNUSED_ARG(ipaddr);
return ERR_IF;
800fed2: f06f 030b mvn.w r3, #11
}
800fed6: 4618 mov r0, r3
800fed8: 3714 adds r7, #20
800feda: 46bd mov sp, r7
800fedc: f85d 7b04 ldr.w r7, [sp], #4
800fee0: 4770 bx lr
...
0800fee4 <netif_get_by_index>:
*
* @param idx index of netif to find
*/
struct netif *
netif_get_by_index(u8_t idx)
{
800fee4: b480 push {r7}
800fee6: b085 sub sp, #20
800fee8: af00 add r7, sp, #0
800feea: 4603 mov r3, r0
800feec: 71fb strb r3, [r7, #7]
struct netif *netif;
LWIP_ASSERT_CORE_LOCKED();
if (idx != NETIF_NO_INDEX) {
800feee: 79fb ldrb r3, [r7, #7]
800fef0: 2b00 cmp r3, #0
800fef2: d013 beq.n 800ff1c <netif_get_by_index+0x38>
NETIF_FOREACH(netif) {
800fef4: 4b0d ldr r3, [pc, #52] ; (800ff2c <netif_get_by_index+0x48>)
800fef6: 681b ldr r3, [r3, #0]
800fef8: 60fb str r3, [r7, #12]
800fefa: e00c b.n 800ff16 <netif_get_by_index+0x32>
if (idx == netif_get_index(netif)) {
800fefc: 68fb ldr r3, [r7, #12]
800fefe: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800ff02: 3301 adds r3, #1
800ff04: b2db uxtb r3, r3
800ff06: 79fa ldrb r2, [r7, #7]
800ff08: 429a cmp r2, r3
800ff0a: d101 bne.n 800ff10 <netif_get_by_index+0x2c>
return netif; /* found! */
800ff0c: 68fb ldr r3, [r7, #12]
800ff0e: e006 b.n 800ff1e <netif_get_by_index+0x3a>
NETIF_FOREACH(netif) {
800ff10: 68fb ldr r3, [r7, #12]
800ff12: 681b ldr r3, [r3, #0]
800ff14: 60fb str r3, [r7, #12]
800ff16: 68fb ldr r3, [r7, #12]
800ff18: 2b00 cmp r3, #0
800ff1a: d1ef bne.n 800fefc <netif_get_by_index+0x18>
}
}
}
return NULL;
800ff1c: 2300 movs r3, #0
}
800ff1e: 4618 mov r0, r3
800ff20: 3714 adds r7, #20
800ff22: 46bd mov sp, r7
800ff24: f85d 7b04 ldr.w r7, [sp], #4
800ff28: 4770 bx lr
800ff2a: bf00 nop
800ff2c: 2000f5b0 .word 0x2000f5b0
0800ff30 <pbuf_free_ooseq>:
#if !NO_SYS
static
#endif /* !NO_SYS */
void
pbuf_free_ooseq(void)
{
800ff30: b580 push {r7, lr}
800ff32: b082 sub sp, #8
800ff34: af00 add r7, sp, #0
struct tcp_pcb *pcb;
SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
800ff36: f00b f811 bl 801af5c <sys_arch_protect>
800ff3a: 6038 str r0, [r7, #0]
800ff3c: 4b0d ldr r3, [pc, #52] ; (800ff74 <pbuf_free_ooseq+0x44>)
800ff3e: 2200 movs r2, #0
800ff40: 701a strb r2, [r3, #0]
800ff42: 6838 ldr r0, [r7, #0]
800ff44: f00b f818 bl 801af78 <sys_arch_unprotect>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800ff48: 4b0b ldr r3, [pc, #44] ; (800ff78 <pbuf_free_ooseq+0x48>)
800ff4a: 681b ldr r3, [r3, #0]
800ff4c: 607b str r3, [r7, #4]
800ff4e: e00a b.n 800ff66 <pbuf_free_ooseq+0x36>
if (pcb->ooseq != NULL) {
800ff50: 687b ldr r3, [r7, #4]
800ff52: 6f5b ldr r3, [r3, #116] ; 0x74
800ff54: 2b00 cmp r3, #0
800ff56: d003 beq.n 800ff60 <pbuf_free_ooseq+0x30>
/** Free the ooseq pbufs of one PCB only */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
tcp_free_ooseq(pcb);
800ff58: 6878 ldr r0, [r7, #4]
800ff5a: f002 f971 bl 8012240 <tcp_free_ooseq>
return;
800ff5e: e005 b.n 800ff6c <pbuf_free_ooseq+0x3c>
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
800ff60: 687b ldr r3, [r7, #4]
800ff62: 68db ldr r3, [r3, #12]
800ff64: 607b str r3, [r7, #4]
800ff66: 687b ldr r3, [r7, #4]
800ff68: 2b00 cmp r3, #0
800ff6a: d1f1 bne.n 800ff50 <pbuf_free_ooseq+0x20>
}
}
}
800ff6c: 3708 adds r7, #8
800ff6e: 46bd mov sp, r7
800ff70: bd80 pop {r7, pc}
800ff72: bf00 nop
800ff74: 2000f5b8 .word 0x2000f5b8
800ff78: 2000f5c0 .word 0x2000f5c0
0800ff7c <pbuf_free_ooseq_callback>:
/**
* Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
*/
static void
pbuf_free_ooseq_callback(void *arg)
{
800ff7c: b580 push {r7, lr}
800ff7e: b082 sub sp, #8
800ff80: af00 add r7, sp, #0
800ff82: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
pbuf_free_ooseq();
800ff84: f7ff ffd4 bl 800ff30 <pbuf_free_ooseq>
}
800ff88: bf00 nop
800ff8a: 3708 adds r7, #8
800ff8c: 46bd mov sp, r7
800ff8e: bd80 pop {r7, pc}
0800ff90 <pbuf_pool_is_empty>:
#endif /* !NO_SYS */
/** Queue a call to pbuf_free_ooseq if not already queued. */
static void
pbuf_pool_is_empty(void)
{
800ff90: b580 push {r7, lr}
800ff92: b082 sub sp, #8
800ff94: af00 add r7, sp, #0
#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
u8_t queued;
SYS_ARCH_DECL_PROTECT(old_level);
SYS_ARCH_PROTECT(old_level);
800ff96: f00a ffe1 bl 801af5c <sys_arch_protect>
800ff9a: 6078 str r0, [r7, #4]
queued = pbuf_free_ooseq_pending;
800ff9c: 4b0f ldr r3, [pc, #60] ; (800ffdc <pbuf_pool_is_empty+0x4c>)
800ff9e: 781b ldrb r3, [r3, #0]
800ffa0: 70fb strb r3, [r7, #3]
pbuf_free_ooseq_pending = 1;
800ffa2: 4b0e ldr r3, [pc, #56] ; (800ffdc <pbuf_pool_is_empty+0x4c>)
800ffa4: 2201 movs r2, #1
800ffa6: 701a strb r2, [r3, #0]
SYS_ARCH_UNPROTECT(old_level);
800ffa8: 6878 ldr r0, [r7, #4]
800ffaa: f00a ffe5 bl 801af78 <sys_arch_unprotect>
if (!queued) {
800ffae: 78fb ldrb r3, [r7, #3]
800ffb0: 2b00 cmp r3, #0
800ffb2: d10f bne.n 800ffd4 <pbuf_pool_is_empty+0x44>
/* queue a call to pbuf_free_ooseq if not already queued */
PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
800ffb4: 2100 movs r1, #0
800ffb6: 480a ldr r0, [pc, #40] ; (800ffe0 <pbuf_pool_is_empty+0x50>)
800ffb8: f7fe fee0 bl 800ed7c <tcpip_try_callback>
800ffbc: 4603 mov r3, r0
800ffbe: 2b00 cmp r3, #0
800ffc0: d008 beq.n 800ffd4 <pbuf_pool_is_empty+0x44>
800ffc2: f00a ffcb bl 801af5c <sys_arch_protect>
800ffc6: 6078 str r0, [r7, #4]
800ffc8: 4b04 ldr r3, [pc, #16] ; (800ffdc <pbuf_pool_is_empty+0x4c>)
800ffca: 2200 movs r2, #0
800ffcc: 701a strb r2, [r3, #0]
800ffce: 6878 ldr r0, [r7, #4]
800ffd0: f00a ffd2 bl 801af78 <sys_arch_unprotect>
}
#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
}
800ffd4: bf00 nop
800ffd6: 3708 adds r7, #8
800ffd8: 46bd mov sp, r7
800ffda: bd80 pop {r7, pc}
800ffdc: 2000f5b8 .word 0x2000f5b8
800ffe0: 0800ff7d .word 0x0800ff7d
0800ffe4 <pbuf_init_alloced_pbuf>:
#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
/* Initialize members of struct pbuf after allocation */
static void
pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
{
800ffe4: b480 push {r7}
800ffe6: b085 sub sp, #20
800ffe8: af00 add r7, sp, #0
800ffea: 60f8 str r0, [r7, #12]
800ffec: 60b9 str r1, [r7, #8]
800ffee: 4611 mov r1, r2
800fff0: 461a mov r2, r3
800fff2: 460b mov r3, r1
800fff4: 80fb strh r3, [r7, #6]
800fff6: 4613 mov r3, r2
800fff8: 80bb strh r3, [r7, #4]
p->next = NULL;
800fffa: 68fb ldr r3, [r7, #12]
800fffc: 2200 movs r2, #0
800fffe: 601a str r2, [r3, #0]
p->payload = payload;
8010000: 68fb ldr r3, [r7, #12]
8010002: 68ba ldr r2, [r7, #8]
8010004: 605a str r2, [r3, #4]
p->tot_len = tot_len;
8010006: 68fb ldr r3, [r7, #12]
8010008: 88fa ldrh r2, [r7, #6]
801000a: 811a strh r2, [r3, #8]
p->len = len;
801000c: 68fb ldr r3, [r7, #12]
801000e: 88ba ldrh r2, [r7, #4]
8010010: 815a strh r2, [r3, #10]
p->type_internal = (u8_t)type;
8010012: 8b3b ldrh r3, [r7, #24]
8010014: b2da uxtb r2, r3
8010016: 68fb ldr r3, [r7, #12]
8010018: 731a strb r2, [r3, #12]
p->flags = flags;
801001a: 68fb ldr r3, [r7, #12]
801001c: 7f3a ldrb r2, [r7, #28]
801001e: 735a strb r2, [r3, #13]
p->ref = 1;
8010020: 68fb ldr r3, [r7, #12]
8010022: 2201 movs r2, #1
8010024: 739a strb r2, [r3, #14]
p->if_idx = NETIF_NO_INDEX;
8010026: 68fb ldr r3, [r7, #12]
8010028: 2200 movs r2, #0
801002a: 73da strb r2, [r3, #15]
}
801002c: bf00 nop
801002e: 3714 adds r7, #20
8010030: 46bd mov sp, r7
8010032: f85d 7b04 ldr.w r7, [sp], #4
8010036: 4770 bx lr
08010038 <pbuf_alloc>:
* @return the allocated pbuf. If multiple pbufs where allocated, this
* is the first pbuf of a pbuf chain.
*/
struct pbuf *
pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
{
8010038: b580 push {r7, lr}
801003a: b08c sub sp, #48 ; 0x30
801003c: af02 add r7, sp, #8
801003e: 4603 mov r3, r0
8010040: 71fb strb r3, [r7, #7]
8010042: 460b mov r3, r1
8010044: 80bb strh r3, [r7, #4]
8010046: 4613 mov r3, r2
8010048: 807b strh r3, [r7, #2]
struct pbuf *p;
u16_t offset = (u16_t)layer;
801004a: 79fb ldrb r3, [r7, #7]
801004c: 847b strh r3, [r7, #34] ; 0x22
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
switch (type) {
801004e: 887b ldrh r3, [r7, #2]
8010050: 2b41 cmp r3, #65 ; 0x41
8010052: d00b beq.n 801006c <pbuf_alloc+0x34>
8010054: 2b41 cmp r3, #65 ; 0x41
8010056: dc02 bgt.n 801005e <pbuf_alloc+0x26>
8010058: 2b01 cmp r3, #1
801005a: d007 beq.n 801006c <pbuf_alloc+0x34>
801005c: e0c2 b.n 80101e4 <pbuf_alloc+0x1ac>
801005e: f5b3 7fc1 cmp.w r3, #386 ; 0x182
8010062: d00b beq.n 801007c <pbuf_alloc+0x44>
8010064: f5b3 7f20 cmp.w r3, #640 ; 0x280
8010068: d070 beq.n 801014c <pbuf_alloc+0x114>
801006a: e0bb b.n 80101e4 <pbuf_alloc+0x1ac>
case PBUF_REF: /* fall through */
case PBUF_ROM:
p = pbuf_alloc_reference(NULL, length, type);
801006c: 887a ldrh r2, [r7, #2]
801006e: 88bb ldrh r3, [r7, #4]
8010070: 4619 mov r1, r3
8010072: 2000 movs r0, #0
8010074: f000 f8d2 bl 801021c <pbuf_alloc_reference>
8010078: 6278 str r0, [r7, #36] ; 0x24
break;
801007a: e0bd b.n 80101f8 <pbuf_alloc+0x1c0>
case PBUF_POOL: {
struct pbuf *q, *last;
u16_t rem_len; /* remaining length */
p = NULL;
801007c: 2300 movs r3, #0
801007e: 627b str r3, [r7, #36] ; 0x24
last = NULL;
8010080: 2300 movs r3, #0
8010082: 61fb str r3, [r7, #28]
rem_len = length;
8010084: 88bb ldrh r3, [r7, #4]
8010086: 837b strh r3, [r7, #26]
do {
u16_t qlen;
q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
8010088: 200c movs r0, #12
801008a: f7ff fbb7 bl 800f7fc <memp_malloc>
801008e: 6138 str r0, [r7, #16]
if (q == NULL) {
8010090: 693b ldr r3, [r7, #16]
8010092: 2b00 cmp r3, #0
8010094: d109 bne.n 80100aa <pbuf_alloc+0x72>
PBUF_POOL_IS_EMPTY();
8010096: f7ff ff7b bl 800ff90 <pbuf_pool_is_empty>
/* free chain so far allocated */
if (p) {
801009a: 6a7b ldr r3, [r7, #36] ; 0x24
801009c: 2b00 cmp r3, #0
801009e: d002 beq.n 80100a6 <pbuf_alloc+0x6e>
pbuf_free(p);
80100a0: 6a78 ldr r0, [r7, #36] ; 0x24
80100a2: f000 faa9 bl 80105f8 <pbuf_free>
}
/* bail out unsuccessfully */
return NULL;
80100a6: 2300 movs r3, #0
80100a8: e0a7 b.n 80101fa <pbuf_alloc+0x1c2>
}
qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
80100aa: 8c7b ldrh r3, [r7, #34] ; 0x22
80100ac: 3303 adds r3, #3
80100ae: b29b uxth r3, r3
80100b0: f023 0303 bic.w r3, r3, #3
80100b4: b29b uxth r3, r3
80100b6: f5c3 7314 rsb r3, r3, #592 ; 0x250
80100ba: b29b uxth r3, r3
80100bc: 8b7a ldrh r2, [r7, #26]
80100be: 4293 cmp r3, r2
80100c0: bf28 it cs
80100c2: 4613 movcs r3, r2
80100c4: 81fb strh r3, [r7, #14]
pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
80100c6: 8c7b ldrh r3, [r7, #34] ; 0x22
80100c8: 3310 adds r3, #16
80100ca: 693a ldr r2, [r7, #16]
80100cc: 4413 add r3, r2
80100ce: 3303 adds r3, #3
80100d0: f023 0303 bic.w r3, r3, #3
80100d4: 4618 mov r0, r3
80100d6: 89f9 ldrh r1, [r7, #14]
80100d8: 8b7a ldrh r2, [r7, #26]
80100da: 2300 movs r3, #0
80100dc: 9301 str r3, [sp, #4]
80100de: 887b ldrh r3, [r7, #2]
80100e0: 9300 str r3, [sp, #0]
80100e2: 460b mov r3, r1
80100e4: 4601 mov r1, r0
80100e6: 6938 ldr r0, [r7, #16]
80100e8: f7ff ff7c bl 800ffe4 <pbuf_init_alloced_pbuf>
rem_len, qlen, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
80100ec: 693b ldr r3, [r7, #16]
80100ee: 685b ldr r3, [r3, #4]
80100f0: f003 0303 and.w r3, r3, #3
80100f4: 2b00 cmp r3, #0
80100f6: d006 beq.n 8010106 <pbuf_alloc+0xce>
80100f8: 4b42 ldr r3, [pc, #264] ; (8010204 <pbuf_alloc+0x1cc>)
80100fa: f240 1201 movw r2, #257 ; 0x101
80100fe: 4942 ldr r1, [pc, #264] ; (8010208 <pbuf_alloc+0x1d0>)
8010100: 4842 ldr r0, [pc, #264] ; (801020c <pbuf_alloc+0x1d4>)
8010102: f00a ff8f bl 801b024 <iprintf>
((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
8010106: 8c7b ldrh r3, [r7, #34] ; 0x22
8010108: 3303 adds r3, #3
801010a: f023 0303 bic.w r3, r3, #3
801010e: f5b3 7f14 cmp.w r3, #592 ; 0x250
8010112: d106 bne.n 8010122 <pbuf_alloc+0xea>
8010114: 4b3b ldr r3, [pc, #236] ; (8010204 <pbuf_alloc+0x1cc>)
8010116: f240 1203 movw r2, #259 ; 0x103
801011a: 493d ldr r1, [pc, #244] ; (8010210 <pbuf_alloc+0x1d8>)
801011c: 483b ldr r0, [pc, #236] ; (801020c <pbuf_alloc+0x1d4>)
801011e: f00a ff81 bl 801b024 <iprintf>
(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
if (p == NULL) {
8010122: 6a7b ldr r3, [r7, #36] ; 0x24
8010124: 2b00 cmp r3, #0
8010126: d102 bne.n 801012e <pbuf_alloc+0xf6>
/* allocated head of pbuf chain (into p) */
p = q;
8010128: 693b ldr r3, [r7, #16]
801012a: 627b str r3, [r7, #36] ; 0x24
801012c: e002 b.n 8010134 <pbuf_alloc+0xfc>
} else {
/* make previous pbuf point to this pbuf */
last->next = q;
801012e: 69fb ldr r3, [r7, #28]
8010130: 693a ldr r2, [r7, #16]
8010132: 601a str r2, [r3, #0]
}
last = q;
8010134: 693b ldr r3, [r7, #16]
8010136: 61fb str r3, [r7, #28]
rem_len = (u16_t)(rem_len - qlen);
8010138: 8b7a ldrh r2, [r7, #26]
801013a: 89fb ldrh r3, [r7, #14]
801013c: 1ad3 subs r3, r2, r3
801013e: 837b strh r3, [r7, #26]
offset = 0;
8010140: 2300 movs r3, #0
8010142: 847b strh r3, [r7, #34] ; 0x22
} while (rem_len > 0);
8010144: 8b7b ldrh r3, [r7, #26]
8010146: 2b00 cmp r3, #0
8010148: d19e bne.n 8010088 <pbuf_alloc+0x50>
break;
801014a: e055 b.n 80101f8 <pbuf_alloc+0x1c0>
}
case PBUF_RAM: {
u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
801014c: 8c7b ldrh r3, [r7, #34] ; 0x22
801014e: 3303 adds r3, #3
8010150: b29b uxth r3, r3
8010152: f023 0303 bic.w r3, r3, #3
8010156: b29a uxth r2, r3
8010158: 88bb ldrh r3, [r7, #4]
801015a: 3303 adds r3, #3
801015c: b29b uxth r3, r3
801015e: f023 0303 bic.w r3, r3, #3
8010162: b29b uxth r3, r3
8010164: 4413 add r3, r2
8010166: 833b strh r3, [r7, #24]
mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
8010168: 8b3b ldrh r3, [r7, #24]
801016a: 3310 adds r3, #16
801016c: 82fb strh r3, [r7, #22]
/* bug #50040: Check for integer overflow when calculating alloc_len */
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
801016e: 8b3a ldrh r2, [r7, #24]
8010170: 88bb ldrh r3, [r7, #4]
8010172: 3303 adds r3, #3
8010174: f023 0303 bic.w r3, r3, #3
8010178: 429a cmp r2, r3
801017a: d306 bcc.n 801018a <pbuf_alloc+0x152>
(alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
801017c: 8afa ldrh r2, [r7, #22]
801017e: 88bb ldrh r3, [r7, #4]
8010180: 3303 adds r3, #3
8010182: f023 0303 bic.w r3, r3, #3
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
8010186: 429a cmp r2, r3
8010188: d201 bcs.n 801018e <pbuf_alloc+0x156>
return NULL;
801018a: 2300 movs r3, #0
801018c: e035 b.n 80101fa <pbuf_alloc+0x1c2>
}
/* If pbuf is to be allocated in RAM, allocate memory for it. */
p = (struct pbuf *)mem_malloc(alloc_len);
801018e: 8afb ldrh r3, [r7, #22]
8010190: 4618 mov r0, r3
8010192: f7ff f9b1 bl 800f4f8 <mem_malloc>
8010196: 6278 str r0, [r7, #36] ; 0x24
if (p == NULL) {
8010198: 6a7b ldr r3, [r7, #36] ; 0x24
801019a: 2b00 cmp r3, #0
801019c: d101 bne.n 80101a2 <pbuf_alloc+0x16a>
return NULL;
801019e: 2300 movs r3, #0
80101a0: e02b b.n 80101fa <pbuf_alloc+0x1c2>
}
pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
80101a2: 8c7b ldrh r3, [r7, #34] ; 0x22
80101a4: 3310 adds r3, #16
80101a6: 6a7a ldr r2, [r7, #36] ; 0x24
80101a8: 4413 add r3, r2
80101aa: 3303 adds r3, #3
80101ac: f023 0303 bic.w r3, r3, #3
80101b0: 4618 mov r0, r3
80101b2: 88b9 ldrh r1, [r7, #4]
80101b4: 88ba ldrh r2, [r7, #4]
80101b6: 2300 movs r3, #0
80101b8: 9301 str r3, [sp, #4]
80101ba: 887b ldrh r3, [r7, #2]
80101bc: 9300 str r3, [sp, #0]
80101be: 460b mov r3, r1
80101c0: 4601 mov r1, r0
80101c2: 6a78 ldr r0, [r7, #36] ; 0x24
80101c4: f7ff ff0e bl 800ffe4 <pbuf_init_alloced_pbuf>
length, length, type, 0);
LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
80101c8: 6a7b ldr r3, [r7, #36] ; 0x24
80101ca: 685b ldr r3, [r3, #4]
80101cc: f003 0303 and.w r3, r3, #3
80101d0: 2b00 cmp r3, #0
80101d2: d010 beq.n 80101f6 <pbuf_alloc+0x1be>
80101d4: 4b0b ldr r3, [pc, #44] ; (8010204 <pbuf_alloc+0x1cc>)
80101d6: f240 1223 movw r2, #291 ; 0x123
80101da: 490e ldr r1, [pc, #56] ; (8010214 <pbuf_alloc+0x1dc>)
80101dc: 480b ldr r0, [pc, #44] ; (801020c <pbuf_alloc+0x1d4>)
80101de: f00a ff21 bl 801b024 <iprintf>
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
break;
80101e2: e008 b.n 80101f6 <pbuf_alloc+0x1be>
}
default:
LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
80101e4: 4b07 ldr r3, [pc, #28] ; (8010204 <pbuf_alloc+0x1cc>)
80101e6: f240 1227 movw r2, #295 ; 0x127
80101ea: 490b ldr r1, [pc, #44] ; (8010218 <pbuf_alloc+0x1e0>)
80101ec: 4807 ldr r0, [pc, #28] ; (801020c <pbuf_alloc+0x1d4>)
80101ee: f00a ff19 bl 801b024 <iprintf>
return NULL;
80101f2: 2300 movs r3, #0
80101f4: e001 b.n 80101fa <pbuf_alloc+0x1c2>
break;
80101f6: bf00 nop
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
return p;
80101f8: 6a7b ldr r3, [r7, #36] ; 0x24
}
80101fa: 4618 mov r0, r3
80101fc: 3728 adds r7, #40 ; 0x28
80101fe: 46bd mov sp, r7
8010200: bd80 pop {r7, pc}
8010202: bf00 nop
8010204: 0801c658 .word 0x0801c658
8010208: 0801c688 .word 0x0801c688
801020c: 0801c6b8 .word 0x0801c6b8
8010210: 0801c6e0 .word 0x0801c6e0
8010214: 0801c714 .word 0x0801c714
8010218: 0801c740 .word 0x0801c740
0801021c <pbuf_alloc_reference>:
*
* @return the allocated pbuf.
*/
struct pbuf *
pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
{
801021c: b580 push {r7, lr}
801021e: b086 sub sp, #24
8010220: af02 add r7, sp, #8
8010222: 6078 str r0, [r7, #4]
8010224: 460b mov r3, r1
8010226: 807b strh r3, [r7, #2]
8010228: 4613 mov r3, r2
801022a: 803b strh r3, [r7, #0]
struct pbuf *p;
LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
801022c: 883b ldrh r3, [r7, #0]
801022e: 2b41 cmp r3, #65 ; 0x41
8010230: d009 beq.n 8010246 <pbuf_alloc_reference+0x2a>
8010232: 883b ldrh r3, [r7, #0]
8010234: 2b01 cmp r3, #1
8010236: d006 beq.n 8010246 <pbuf_alloc_reference+0x2a>
8010238: 4b0f ldr r3, [pc, #60] ; (8010278 <pbuf_alloc_reference+0x5c>)
801023a: f44f 72a5 mov.w r2, #330 ; 0x14a
801023e: 490f ldr r1, [pc, #60] ; (801027c <pbuf_alloc_reference+0x60>)
8010240: 480f ldr r0, [pc, #60] ; (8010280 <pbuf_alloc_reference+0x64>)
8010242: f00a feef bl 801b024 <iprintf>
/* only allocate memory for the pbuf structure */
p = (struct pbuf *)memp_malloc(MEMP_PBUF);
8010246: 200b movs r0, #11
8010248: f7ff fad8 bl 800f7fc <memp_malloc>
801024c: 60f8 str r0, [r7, #12]
if (p == NULL) {
801024e: 68fb ldr r3, [r7, #12]
8010250: 2b00 cmp r3, #0
8010252: d101 bne.n 8010258 <pbuf_alloc_reference+0x3c>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
(type == PBUF_ROM) ? "ROM" : "REF"));
return NULL;
8010254: 2300 movs r3, #0
8010256: e00b b.n 8010270 <pbuf_alloc_reference+0x54>
}
pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
8010258: 8879 ldrh r1, [r7, #2]
801025a: 887a ldrh r2, [r7, #2]
801025c: 2300 movs r3, #0
801025e: 9301 str r3, [sp, #4]
8010260: 883b ldrh r3, [r7, #0]
8010262: 9300 str r3, [sp, #0]
8010264: 460b mov r3, r1
8010266: 6879 ldr r1, [r7, #4]
8010268: 68f8 ldr r0, [r7, #12]
801026a: f7ff febb bl 800ffe4 <pbuf_init_alloced_pbuf>
return p;
801026e: 68fb ldr r3, [r7, #12]
}
8010270: 4618 mov r0, r3
8010272: 3710 adds r7, #16
8010274: 46bd mov sp, r7
8010276: bd80 pop {r7, pc}
8010278: 0801c658 .word 0x0801c658
801027c: 0801c75c .word 0x0801c75c
8010280: 0801c6b8 .word 0x0801c6b8
08010284 <pbuf_alloced_custom>:
* big enough to hold 'length' plus the header size
*/
struct pbuf *
pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
void *payload_mem, u16_t payload_mem_len)
{
8010284: b580 push {r7, lr}
8010286: b088 sub sp, #32
8010288: af02 add r7, sp, #8
801028a: 607b str r3, [r7, #4]
801028c: 4603 mov r3, r0
801028e: 73fb strb r3, [r7, #15]
8010290: 460b mov r3, r1
8010292: 81bb strh r3, [r7, #12]
8010294: 4613 mov r3, r2
8010296: 817b strh r3, [r7, #10]
u16_t offset = (u16_t)l;
8010298: 7bfb ldrb r3, [r7, #15]
801029a: 827b strh r3, [r7, #18]
void *payload;
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
801029c: 8a7b ldrh r3, [r7, #18]
801029e: 3303 adds r3, #3
80102a0: f023 0203 bic.w r2, r3, #3
80102a4: 89bb ldrh r3, [r7, #12]
80102a6: 441a add r2, r3
80102a8: 8cbb ldrh r3, [r7, #36] ; 0x24
80102aa: 429a cmp r2, r3
80102ac: d901 bls.n 80102b2 <pbuf_alloced_custom+0x2e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
return NULL;
80102ae: 2300 movs r3, #0
80102b0: e018 b.n 80102e4 <pbuf_alloced_custom+0x60>
}
if (payload_mem != NULL) {
80102b2: 6a3b ldr r3, [r7, #32]
80102b4: 2b00 cmp r3, #0
80102b6: d007 beq.n 80102c8 <pbuf_alloced_custom+0x44>
payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
80102b8: 8a7b ldrh r3, [r7, #18]
80102ba: 3303 adds r3, #3
80102bc: f023 0303 bic.w r3, r3, #3
80102c0: 6a3a ldr r2, [r7, #32]
80102c2: 4413 add r3, r2
80102c4: 617b str r3, [r7, #20]
80102c6: e001 b.n 80102cc <pbuf_alloced_custom+0x48>
} else {
payload = NULL;
80102c8: 2300 movs r3, #0
80102ca: 617b str r3, [r7, #20]
}
pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
80102cc: 6878 ldr r0, [r7, #4]
80102ce: 89b9 ldrh r1, [r7, #12]
80102d0: 89ba ldrh r2, [r7, #12]
80102d2: 2302 movs r3, #2
80102d4: 9301 str r3, [sp, #4]
80102d6: 897b ldrh r3, [r7, #10]
80102d8: 9300 str r3, [sp, #0]
80102da: 460b mov r3, r1
80102dc: 6979 ldr r1, [r7, #20]
80102de: f7ff fe81 bl 800ffe4 <pbuf_init_alloced_pbuf>
return &p->pbuf;
80102e2: 687b ldr r3, [r7, #4]
}
80102e4: 4618 mov r0, r3
80102e6: 3718 adds r7, #24
80102e8: 46bd mov sp, r7
80102ea: bd80 pop {r7, pc}
080102ec <pbuf_realloc>:
*
* @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
*/
void
pbuf_realloc(struct pbuf *p, u16_t new_len)
{
80102ec: b580 push {r7, lr}
80102ee: b084 sub sp, #16
80102f0: af00 add r7, sp, #0
80102f2: 6078 str r0, [r7, #4]
80102f4: 460b mov r3, r1
80102f6: 807b strh r3, [r7, #2]
struct pbuf *q;
u16_t rem_len; /* remaining length */
u16_t shrink;
LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
80102f8: 687b ldr r3, [r7, #4]
80102fa: 2b00 cmp r3, #0
80102fc: d106 bne.n 801030c <pbuf_realloc+0x20>
80102fe: 4b3a ldr r3, [pc, #232] ; (80103e8 <pbuf_realloc+0xfc>)
8010300: f44f 72cc mov.w r2, #408 ; 0x198
8010304: 4939 ldr r1, [pc, #228] ; (80103ec <pbuf_realloc+0x100>)
8010306: 483a ldr r0, [pc, #232] ; (80103f0 <pbuf_realloc+0x104>)
8010308: f00a fe8c bl 801b024 <iprintf>
/* desired length larger than current length? */
if (new_len >= p->tot_len) {
801030c: 687b ldr r3, [r7, #4]
801030e: 891b ldrh r3, [r3, #8]
8010310: 887a ldrh r2, [r7, #2]
8010312: 429a cmp r2, r3
8010314: d264 bcs.n 80103e0 <pbuf_realloc+0xf4>
return;
}
/* the pbuf chain grows by (new_len - p->tot_len) bytes
* (which may be negative in case of shrinking) */
shrink = (u16_t)(p->tot_len - new_len);
8010316: 687b ldr r3, [r7, #4]
8010318: 891a ldrh r2, [r3, #8]
801031a: 887b ldrh r3, [r7, #2]
801031c: 1ad3 subs r3, r2, r3
801031e: 813b strh r3, [r7, #8]
/* first, step over any pbufs that should remain in the chain */
rem_len = new_len;
8010320: 887b ldrh r3, [r7, #2]
8010322: 817b strh r3, [r7, #10]
q = p;
8010324: 687b ldr r3, [r7, #4]
8010326: 60fb str r3, [r7, #12]
/* should this pbuf be kept? */
while (rem_len > q->len) {
8010328: e018 b.n 801035c <pbuf_realloc+0x70>
/* decrease remaining length by pbuf length */
rem_len = (u16_t)(rem_len - q->len);
801032a: 68fb ldr r3, [r7, #12]
801032c: 895b ldrh r3, [r3, #10]
801032e: 897a ldrh r2, [r7, #10]
8010330: 1ad3 subs r3, r2, r3
8010332: 817b strh r3, [r7, #10]
/* decrease total length indicator */
q->tot_len = (u16_t)(q->tot_len - shrink);
8010334: 68fb ldr r3, [r7, #12]
8010336: 891a ldrh r2, [r3, #8]
8010338: 893b ldrh r3, [r7, #8]
801033a: 1ad3 subs r3, r2, r3
801033c: b29a uxth r2, r3
801033e: 68fb ldr r3, [r7, #12]
8010340: 811a strh r2, [r3, #8]
/* proceed to next pbuf in chain */
q = q->next;
8010342: 68fb ldr r3, [r7, #12]
8010344: 681b ldr r3, [r3, #0]
8010346: 60fb str r3, [r7, #12]
LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
8010348: 68fb ldr r3, [r7, #12]
801034a: 2b00 cmp r3, #0
801034c: d106 bne.n 801035c <pbuf_realloc+0x70>
801034e: 4b26 ldr r3, [pc, #152] ; (80103e8 <pbuf_realloc+0xfc>)
8010350: f240 12af movw r2, #431 ; 0x1af
8010354: 4927 ldr r1, [pc, #156] ; (80103f4 <pbuf_realloc+0x108>)
8010356: 4826 ldr r0, [pc, #152] ; (80103f0 <pbuf_realloc+0x104>)
8010358: f00a fe64 bl 801b024 <iprintf>
while (rem_len > q->len) {
801035c: 68fb ldr r3, [r7, #12]
801035e: 895b ldrh r3, [r3, #10]
8010360: 897a ldrh r2, [r7, #10]
8010362: 429a cmp r2, r3
8010364: d8e1 bhi.n 801032a <pbuf_realloc+0x3e>
/* we have now reached the new last pbuf (in q) */
/* rem_len == desired length for pbuf q */
/* shrink allocated memory for PBUF_RAM */
/* (other types merely adjust their length fields */
if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
8010366: 68fb ldr r3, [r7, #12]
8010368: 7b1b ldrb r3, [r3, #12]
801036a: f003 030f and.w r3, r3, #15
801036e: 2b00 cmp r3, #0
8010370: d122 bne.n 80103b8 <pbuf_realloc+0xcc>
8010372: 68fb ldr r3, [r7, #12]
8010374: 895b ldrh r3, [r3, #10]
8010376: 897a ldrh r2, [r7, #10]
8010378: 429a cmp r2, r3
801037a: d01d beq.n 80103b8 <pbuf_realloc+0xcc>
#if LWIP_SUPPORT_CUSTOM_PBUF
&& ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
801037c: 68fb ldr r3, [r7, #12]
801037e: 7b5b ldrb r3, [r3, #13]
8010380: f003 0302 and.w r3, r3, #2
8010384: 2b00 cmp r3, #0
8010386: d117 bne.n 80103b8 <pbuf_realloc+0xcc>
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
) {
/* reallocate and adjust the length of the pbuf that will be split */
q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
8010388: 68fb ldr r3, [r7, #12]
801038a: 685b ldr r3, [r3, #4]
801038c: 461a mov r2, r3
801038e: 68fb ldr r3, [r7, #12]
8010390: 1ad3 subs r3, r2, r3
8010392: b29a uxth r2, r3
8010394: 897b ldrh r3, [r7, #10]
8010396: 4413 add r3, r2
8010398: b29b uxth r3, r3
801039a: 4619 mov r1, r3
801039c: 68f8 ldr r0, [r7, #12]
801039e: f7fe ffa1 bl 800f2e4 <mem_trim>
80103a2: 60f8 str r0, [r7, #12]
LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
80103a4: 68fb ldr r3, [r7, #12]
80103a6: 2b00 cmp r3, #0
80103a8: d106 bne.n 80103b8 <pbuf_realloc+0xcc>
80103aa: 4b0f ldr r3, [pc, #60] ; (80103e8 <pbuf_realloc+0xfc>)
80103ac: f240 12bd movw r2, #445 ; 0x1bd
80103b0: 4911 ldr r1, [pc, #68] ; (80103f8 <pbuf_realloc+0x10c>)
80103b2: 480f ldr r0, [pc, #60] ; (80103f0 <pbuf_realloc+0x104>)
80103b4: f00a fe36 bl 801b024 <iprintf>
}
/* adjust length fields for new last pbuf */
q->len = rem_len;
80103b8: 68fb ldr r3, [r7, #12]
80103ba: 897a ldrh r2, [r7, #10]
80103bc: 815a strh r2, [r3, #10]
q->tot_len = q->len;
80103be: 68fb ldr r3, [r7, #12]
80103c0: 895a ldrh r2, [r3, #10]
80103c2: 68fb ldr r3, [r7, #12]
80103c4: 811a strh r2, [r3, #8]
/* any remaining pbufs in chain? */
if (q->next != NULL) {
80103c6: 68fb ldr r3, [r7, #12]
80103c8: 681b ldr r3, [r3, #0]
80103ca: 2b00 cmp r3, #0
80103cc: d004 beq.n 80103d8 <pbuf_realloc+0xec>
/* free remaining pbufs in chain */
pbuf_free(q->next);
80103ce: 68fb ldr r3, [r7, #12]
80103d0: 681b ldr r3, [r3, #0]
80103d2: 4618 mov r0, r3
80103d4: f000 f910 bl 80105f8 <pbuf_free>
}
/* q is last packet in chain */
q->next = NULL;
80103d8: 68fb ldr r3, [r7, #12]
80103da: 2200 movs r2, #0
80103dc: 601a str r2, [r3, #0]
80103de: e000 b.n 80103e2 <pbuf_realloc+0xf6>
return;
80103e0: bf00 nop
}
80103e2: 3710 adds r7, #16
80103e4: 46bd mov sp, r7
80103e6: bd80 pop {r7, pc}
80103e8: 0801c658 .word 0x0801c658
80103ec: 0801c770 .word 0x0801c770
80103f0: 0801c6b8 .word 0x0801c6b8
80103f4: 0801c788 .word 0x0801c788
80103f8: 0801c7a0 .word 0x0801c7a0
080103fc <pbuf_add_header_impl>:
* @return non-zero on failure, zero on success.
*
*/
static u8_t
pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
{
80103fc: b580 push {r7, lr}
80103fe: b086 sub sp, #24
8010400: af00 add r7, sp, #0
8010402: 60f8 str r0, [r7, #12]
8010404: 60b9 str r1, [r7, #8]
8010406: 4613 mov r3, r2
8010408: 71fb strb r3, [r7, #7]
u16_t type_internal;
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
801040a: 68fb ldr r3, [r7, #12]
801040c: 2b00 cmp r3, #0
801040e: d106 bne.n 801041e <pbuf_add_header_impl+0x22>
8010410: 4b2b ldr r3, [pc, #172] ; (80104c0 <pbuf_add_header_impl+0xc4>)
8010412: f240 12df movw r2, #479 ; 0x1df
8010416: 492b ldr r1, [pc, #172] ; (80104c4 <pbuf_add_header_impl+0xc8>)
8010418: 482b ldr r0, [pc, #172] ; (80104c8 <pbuf_add_header_impl+0xcc>)
801041a: f00a fe03 bl 801b024 <iprintf>
if ((p == NULL) || (header_size_increment > 0xFFFF)) {
801041e: 68fb ldr r3, [r7, #12]
8010420: 2b00 cmp r3, #0
8010422: d003 beq.n 801042c <pbuf_add_header_impl+0x30>
8010424: 68bb ldr r3, [r7, #8]
8010426: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801042a: d301 bcc.n 8010430 <pbuf_add_header_impl+0x34>
return 1;
801042c: 2301 movs r3, #1
801042e: e043 b.n 80104b8 <pbuf_add_header_impl+0xbc>
}
if (header_size_increment == 0) {
8010430: 68bb ldr r3, [r7, #8]
8010432: 2b00 cmp r3, #0
8010434: d101 bne.n 801043a <pbuf_add_header_impl+0x3e>
return 0;
8010436: 2300 movs r3, #0
8010438: e03e b.n 80104b8 <pbuf_add_header_impl+0xbc>
}
increment_magnitude = (u16_t)header_size_increment;
801043a: 68bb ldr r3, [r7, #8]
801043c: 827b strh r3, [r7, #18]
/* Do not allow tot_len to wrap as a result. */
if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
801043e: 68fb ldr r3, [r7, #12]
8010440: 891a ldrh r2, [r3, #8]
8010442: 8a7b ldrh r3, [r7, #18]
8010444: 4413 add r3, r2
8010446: b29b uxth r3, r3
8010448: 8a7a ldrh r2, [r7, #18]
801044a: 429a cmp r2, r3
801044c: d901 bls.n 8010452 <pbuf_add_header_impl+0x56>
return 1;
801044e: 2301 movs r3, #1
8010450: e032 b.n 80104b8 <pbuf_add_header_impl+0xbc>
}
type_internal = p->type_internal;
8010452: 68fb ldr r3, [r7, #12]
8010454: 7b1b ldrb r3, [r3, #12]
8010456: 823b strh r3, [r7, #16]
/* pbuf types containing payloads? */
if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
8010458: 8a3b ldrh r3, [r7, #16]
801045a: f003 0380 and.w r3, r3, #128 ; 0x80
801045e: 2b00 cmp r3, #0
8010460: d00c beq.n 801047c <pbuf_add_header_impl+0x80>
/* set new payload pointer */
payload = (u8_t *)p->payload - header_size_increment;
8010462: 68fb ldr r3, [r7, #12]
8010464: 685a ldr r2, [r3, #4]
8010466: 68bb ldr r3, [r7, #8]
8010468: 425b negs r3, r3
801046a: 4413 add r3, r2
801046c: 617b str r3, [r7, #20]
/* boundary check fails? */
if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
801046e: 68fb ldr r3, [r7, #12]
8010470: 3310 adds r3, #16
8010472: 697a ldr r2, [r7, #20]
8010474: 429a cmp r2, r3
8010476: d20d bcs.n 8010494 <pbuf_add_header_impl+0x98>
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
(void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
/* bail out unsuccessfully */
return 1;
8010478: 2301 movs r3, #1
801047a: e01d b.n 80104b8 <pbuf_add_header_impl+0xbc>
}
/* pbuf types referring to external payloads? */
} else {
/* hide a header in the payload? */
if (force) {
801047c: 79fb ldrb r3, [r7, #7]
801047e: 2b00 cmp r3, #0
8010480: d006 beq.n 8010490 <pbuf_add_header_impl+0x94>
payload = (u8_t *)p->payload - header_size_increment;
8010482: 68fb ldr r3, [r7, #12]
8010484: 685a ldr r2, [r3, #4]
8010486: 68bb ldr r3, [r7, #8]
8010488: 425b negs r3, r3
801048a: 4413 add r3, r2
801048c: 617b str r3, [r7, #20]
801048e: e001 b.n 8010494 <pbuf_add_header_impl+0x98>
} else {
/* cannot expand payload to front (yet!)
* bail out unsuccessfully */
return 1;
8010490: 2301 movs r3, #1
8010492: e011 b.n 80104b8 <pbuf_add_header_impl+0xbc>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
(void *)p->payload, (void *)payload, increment_magnitude));
/* modify pbuf fields */
p->payload = payload;
8010494: 68fb ldr r3, [r7, #12]
8010496: 697a ldr r2, [r7, #20]
8010498: 605a str r2, [r3, #4]
p->len = (u16_t)(p->len + increment_magnitude);
801049a: 68fb ldr r3, [r7, #12]
801049c: 895a ldrh r2, [r3, #10]
801049e: 8a7b ldrh r3, [r7, #18]
80104a0: 4413 add r3, r2
80104a2: b29a uxth r2, r3
80104a4: 68fb ldr r3, [r7, #12]
80104a6: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
80104a8: 68fb ldr r3, [r7, #12]
80104aa: 891a ldrh r2, [r3, #8]
80104ac: 8a7b ldrh r3, [r7, #18]
80104ae: 4413 add r3, r2
80104b0: b29a uxth r2, r3
80104b2: 68fb ldr r3, [r7, #12]
80104b4: 811a strh r2, [r3, #8]
return 0;
80104b6: 2300 movs r3, #0
}
80104b8: 4618 mov r0, r3
80104ba: 3718 adds r7, #24
80104bc: 46bd mov sp, r7
80104be: bd80 pop {r7, pc}
80104c0: 0801c658 .word 0x0801c658
80104c4: 0801c7bc .word 0x0801c7bc
80104c8: 0801c6b8 .word 0x0801c6b8
080104cc <pbuf_add_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_add_header(struct pbuf *p, size_t header_size_increment)
{
80104cc: b580 push {r7, lr}
80104ce: b082 sub sp, #8
80104d0: af00 add r7, sp, #0
80104d2: 6078 str r0, [r7, #4]
80104d4: 6039 str r1, [r7, #0]
return pbuf_add_header_impl(p, header_size_increment, 0);
80104d6: 2200 movs r2, #0
80104d8: 6839 ldr r1, [r7, #0]
80104da: 6878 ldr r0, [r7, #4]
80104dc: f7ff ff8e bl 80103fc <pbuf_add_header_impl>
80104e0: 4603 mov r3, r0
}
80104e2: 4618 mov r0, r3
80104e4: 3708 adds r7, #8
80104e6: 46bd mov sp, r7
80104e8: bd80 pop {r7, pc}
...
080104ec <pbuf_remove_header>:
* @return non-zero on failure, zero on success.
*
*/
u8_t
pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
{
80104ec: b580 push {r7, lr}
80104ee: b084 sub sp, #16
80104f0: af00 add r7, sp, #0
80104f2: 6078 str r0, [r7, #4]
80104f4: 6039 str r1, [r7, #0]
void *payload;
u16_t increment_magnitude;
LWIP_ASSERT("p != NULL", p != NULL);
80104f6: 687b ldr r3, [r7, #4]
80104f8: 2b00 cmp r3, #0
80104fa: d106 bne.n 801050a <pbuf_remove_header+0x1e>
80104fc: 4b20 ldr r3, [pc, #128] ; (8010580 <pbuf_remove_header+0x94>)
80104fe: f240 224b movw r2, #587 ; 0x24b
8010502: 4920 ldr r1, [pc, #128] ; (8010584 <pbuf_remove_header+0x98>)
8010504: 4820 ldr r0, [pc, #128] ; (8010588 <pbuf_remove_header+0x9c>)
8010506: f00a fd8d bl 801b024 <iprintf>
if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
801050a: 687b ldr r3, [r7, #4]
801050c: 2b00 cmp r3, #0
801050e: d003 beq.n 8010518 <pbuf_remove_header+0x2c>
8010510: 683b ldr r3, [r7, #0]
8010512: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8010516: d301 bcc.n 801051c <pbuf_remove_header+0x30>
return 1;
8010518: 2301 movs r3, #1
801051a: e02c b.n 8010576 <pbuf_remove_header+0x8a>
}
if (header_size_decrement == 0) {
801051c: 683b ldr r3, [r7, #0]
801051e: 2b00 cmp r3, #0
8010520: d101 bne.n 8010526 <pbuf_remove_header+0x3a>
return 0;
8010522: 2300 movs r3, #0
8010524: e027 b.n 8010576 <pbuf_remove_header+0x8a>
}
increment_magnitude = (u16_t)header_size_decrement;
8010526: 683b ldr r3, [r7, #0]
8010528: 81fb strh r3, [r7, #14]
/* Check that we aren't going to move off the end of the pbuf */
LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
801052a: 687b ldr r3, [r7, #4]
801052c: 895b ldrh r3, [r3, #10]
801052e: 89fa ldrh r2, [r7, #14]
8010530: 429a cmp r2, r3
8010532: d908 bls.n 8010546 <pbuf_remove_header+0x5a>
8010534: 4b12 ldr r3, [pc, #72] ; (8010580 <pbuf_remove_header+0x94>)
8010536: f240 2255 movw r2, #597 ; 0x255
801053a: 4914 ldr r1, [pc, #80] ; (801058c <pbuf_remove_header+0xa0>)
801053c: 4812 ldr r0, [pc, #72] ; (8010588 <pbuf_remove_header+0x9c>)
801053e: f00a fd71 bl 801b024 <iprintf>
8010542: 2301 movs r3, #1
8010544: e017 b.n 8010576 <pbuf_remove_header+0x8a>
/* remember current payload pointer */
payload = p->payload;
8010546: 687b ldr r3, [r7, #4]
8010548: 685b ldr r3, [r3, #4]
801054a: 60bb str r3, [r7, #8]
LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
/* increase payload pointer (guarded by length check above) */
p->payload = (u8_t *)p->payload + header_size_decrement;
801054c: 687b ldr r3, [r7, #4]
801054e: 685a ldr r2, [r3, #4]
8010550: 683b ldr r3, [r7, #0]
8010552: 441a add r2, r3
8010554: 687b ldr r3, [r7, #4]
8010556: 605a str r2, [r3, #4]
/* modify pbuf length fields */
p->len = (u16_t)(p->len - increment_magnitude);
8010558: 687b ldr r3, [r7, #4]
801055a: 895a ldrh r2, [r3, #10]
801055c: 89fb ldrh r3, [r7, #14]
801055e: 1ad3 subs r3, r2, r3
8010560: b29a uxth r2, r3
8010562: 687b ldr r3, [r7, #4]
8010564: 815a strh r2, [r3, #10]
p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
8010566: 687b ldr r3, [r7, #4]
8010568: 891a ldrh r2, [r3, #8]
801056a: 89fb ldrh r3, [r7, #14]
801056c: 1ad3 subs r3, r2, r3
801056e: b29a uxth r2, r3
8010570: 687b ldr r3, [r7, #4]
8010572: 811a strh r2, [r3, #8]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
(void *)payload, (void *)p->payload, increment_magnitude));
return 0;
8010574: 2300 movs r3, #0
}
8010576: 4618 mov r0, r3
8010578: 3710 adds r7, #16
801057a: 46bd mov sp, r7
801057c: bd80 pop {r7, pc}
801057e: bf00 nop
8010580: 0801c658 .word 0x0801c658
8010584: 0801c7bc .word 0x0801c7bc
8010588: 0801c6b8 .word 0x0801c6b8
801058c: 0801c7c8 .word 0x0801c7c8
08010590 <pbuf_header_impl>:
static u8_t
pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
{
8010590: b580 push {r7, lr}
8010592: b082 sub sp, #8
8010594: af00 add r7, sp, #0
8010596: 6078 str r0, [r7, #4]
8010598: 460b mov r3, r1
801059a: 807b strh r3, [r7, #2]
801059c: 4613 mov r3, r2
801059e: 707b strb r3, [r7, #1]
if (header_size_increment < 0) {
80105a0: f9b7 3002 ldrsh.w r3, [r7, #2]
80105a4: 2b00 cmp r3, #0
80105a6: da08 bge.n 80105ba <pbuf_header_impl+0x2a>
return pbuf_remove_header(p, (size_t) - header_size_increment);
80105a8: f9b7 3002 ldrsh.w r3, [r7, #2]
80105ac: 425b negs r3, r3
80105ae: 4619 mov r1, r3
80105b0: 6878 ldr r0, [r7, #4]
80105b2: f7ff ff9b bl 80104ec <pbuf_remove_header>
80105b6: 4603 mov r3, r0
80105b8: e007 b.n 80105ca <pbuf_header_impl+0x3a>
} else {
return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
80105ba: f9b7 3002 ldrsh.w r3, [r7, #2]
80105be: 787a ldrb r2, [r7, #1]
80105c0: 4619 mov r1, r3
80105c2: 6878 ldr r0, [r7, #4]
80105c4: f7ff ff1a bl 80103fc <pbuf_add_header_impl>
80105c8: 4603 mov r3, r0
}
}
80105ca: 4618 mov r0, r3
80105cc: 3708 adds r7, #8
80105ce: 46bd mov sp, r7
80105d0: bd80 pop {r7, pc}
080105d2 <pbuf_header_force>:
* Same as pbuf_header but does not check if 'header_size > 0' is allowed.
* This is used internally only, to allow PBUF_REF for RX.
*/
u8_t
pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
{
80105d2: b580 push {r7, lr}
80105d4: b082 sub sp, #8
80105d6: af00 add r7, sp, #0
80105d8: 6078 str r0, [r7, #4]
80105da: 460b mov r3, r1
80105dc: 807b strh r3, [r7, #2]
return pbuf_header_impl(p, header_size_increment, 1);
80105de: f9b7 3002 ldrsh.w r3, [r7, #2]
80105e2: 2201 movs r2, #1
80105e4: 4619 mov r1, r3
80105e6: 6878 ldr r0, [r7, #4]
80105e8: f7ff ffd2 bl 8010590 <pbuf_header_impl>
80105ec: 4603 mov r3, r0
}
80105ee: 4618 mov r0, r3
80105f0: 3708 adds r7, #8
80105f2: 46bd mov sp, r7
80105f4: bd80 pop {r7, pc}
...
080105f8 <pbuf_free>:
* 1->1->1 becomes .......
*
*/
u8_t
pbuf_free(struct pbuf *p)
{
80105f8: b580 push {r7, lr}
80105fa: b088 sub sp, #32
80105fc: af00 add r7, sp, #0
80105fe: 6078 str r0, [r7, #4]
u8_t alloc_src;
struct pbuf *q;
u8_t count;
if (p == NULL) {
8010600: 687b ldr r3, [r7, #4]
8010602: 2b00 cmp r3, #0
8010604: d10b bne.n 801061e <pbuf_free+0x26>
LWIP_ASSERT("p != NULL", p != NULL);
8010606: 687b ldr r3, [r7, #4]
8010608: 2b00 cmp r3, #0
801060a: d106 bne.n 801061a <pbuf_free+0x22>
801060c: 4b3b ldr r3, [pc, #236] ; (80106fc <pbuf_free+0x104>)
801060e: f44f 7237 mov.w r2, #732 ; 0x2dc
8010612: 493b ldr r1, [pc, #236] ; (8010700 <pbuf_free+0x108>)
8010614: 483b ldr r0, [pc, #236] ; (8010704 <pbuf_free+0x10c>)
8010616: f00a fd05 bl 801b024 <iprintf>
/* if assertions are disabled, proceed with debug output */
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("pbuf_free(p == NULL) was called.\n"));
return 0;
801061a: 2300 movs r3, #0
801061c: e069 b.n 80106f2 <pbuf_free+0xfa>
}
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
PERF_START;
count = 0;
801061e: 2300 movs r3, #0
8010620: 77fb strb r3, [r7, #31]
/* de-allocate all consecutive pbufs from the head of the chain that
* obtain a zero reference count after decrementing*/
while (p != NULL) {
8010622: e062 b.n 80106ea <pbuf_free+0xf2>
LWIP_PBUF_REF_T ref;
SYS_ARCH_DECL_PROTECT(old_level);
/* Since decrementing ref cannot be guaranteed to be a single machine operation
* we must protect it. We put the new ref into a local variable to prevent
* further protection. */
SYS_ARCH_PROTECT(old_level);
8010624: f00a fc9a bl 801af5c <sys_arch_protect>
8010628: 61b8 str r0, [r7, #24]
/* all pbufs in a chain are referenced at least once */
LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
801062a: 687b ldr r3, [r7, #4]
801062c: 7b9b ldrb r3, [r3, #14]
801062e: 2b00 cmp r3, #0
8010630: d106 bne.n 8010640 <pbuf_free+0x48>
8010632: 4b32 ldr r3, [pc, #200] ; (80106fc <pbuf_free+0x104>)
8010634: f240 22f1 movw r2, #753 ; 0x2f1
8010638: 4933 ldr r1, [pc, #204] ; (8010708 <pbuf_free+0x110>)
801063a: 4832 ldr r0, [pc, #200] ; (8010704 <pbuf_free+0x10c>)
801063c: f00a fcf2 bl 801b024 <iprintf>
/* decrease reference count (number of pointers to pbuf) */
ref = --(p->ref);
8010640: 687b ldr r3, [r7, #4]
8010642: 7b9b ldrb r3, [r3, #14]
8010644: 3b01 subs r3, #1
8010646: b2da uxtb r2, r3
8010648: 687b ldr r3, [r7, #4]
801064a: 739a strb r2, [r3, #14]
801064c: 687b ldr r3, [r7, #4]
801064e: 7b9b ldrb r3, [r3, #14]
8010650: 75fb strb r3, [r7, #23]
SYS_ARCH_UNPROTECT(old_level);
8010652: 69b8 ldr r0, [r7, #24]
8010654: f00a fc90 bl 801af78 <sys_arch_unprotect>
/* this pbuf is no longer referenced to? */
if (ref == 0) {
8010658: 7dfb ldrb r3, [r7, #23]
801065a: 2b00 cmp r3, #0
801065c: d143 bne.n 80106e6 <pbuf_free+0xee>
/* remember next pbuf in chain for next iteration */
q = p->next;
801065e: 687b ldr r3, [r7, #4]
8010660: 681b ldr r3, [r3, #0]
8010662: 613b str r3, [r7, #16]
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
alloc_src = pbuf_get_allocsrc(p);
8010664: 687b ldr r3, [r7, #4]
8010666: 7b1b ldrb r3, [r3, #12]
8010668: f003 030f and.w r3, r3, #15
801066c: 73fb strb r3, [r7, #15]
#if LWIP_SUPPORT_CUSTOM_PBUF
/* is this a custom pbuf? */
if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
801066e: 687b ldr r3, [r7, #4]
8010670: 7b5b ldrb r3, [r3, #13]
8010672: f003 0302 and.w r3, r3, #2
8010676: 2b00 cmp r3, #0
8010678: d011 beq.n 801069e <pbuf_free+0xa6>
struct pbuf_custom *pc = (struct pbuf_custom *)p;
801067a: 687b ldr r3, [r7, #4]
801067c: 60bb str r3, [r7, #8]
LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
801067e: 68bb ldr r3, [r7, #8]
8010680: 691b ldr r3, [r3, #16]
8010682: 2b00 cmp r3, #0
8010684: d106 bne.n 8010694 <pbuf_free+0x9c>
8010686: 4b1d ldr r3, [pc, #116] ; (80106fc <pbuf_free+0x104>)
8010688: f240 22ff movw r2, #767 ; 0x2ff
801068c: 491f ldr r1, [pc, #124] ; (801070c <pbuf_free+0x114>)
801068e: 481d ldr r0, [pc, #116] ; (8010704 <pbuf_free+0x10c>)
8010690: f00a fcc8 bl 801b024 <iprintf>
pc->custom_free_function(p);
8010694: 68bb ldr r3, [r7, #8]
8010696: 691b ldr r3, [r3, #16]
8010698: 6878 ldr r0, [r7, #4]
801069a: 4798 blx r3
801069c: e01d b.n 80106da <pbuf_free+0xe2>
} else
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
{
/* is this a pbuf from the pool? */
if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
801069e: 7bfb ldrb r3, [r7, #15]
80106a0: 2b02 cmp r3, #2
80106a2: d104 bne.n 80106ae <pbuf_free+0xb6>
memp_free(MEMP_PBUF_POOL, p);
80106a4: 6879 ldr r1, [r7, #4]
80106a6: 200c movs r0, #12
80106a8: f7ff f8fa bl 800f8a0 <memp_free>
80106ac: e015 b.n 80106da <pbuf_free+0xe2>
/* is this a ROM or RAM referencing pbuf? */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
80106ae: 7bfb ldrb r3, [r7, #15]
80106b0: 2b01 cmp r3, #1
80106b2: d104 bne.n 80106be <pbuf_free+0xc6>
memp_free(MEMP_PBUF, p);
80106b4: 6879 ldr r1, [r7, #4]
80106b6: 200b movs r0, #11
80106b8: f7ff f8f2 bl 800f8a0 <memp_free>
80106bc: e00d b.n 80106da <pbuf_free+0xe2>
/* type == PBUF_RAM */
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
80106be: 7bfb ldrb r3, [r7, #15]
80106c0: 2b00 cmp r3, #0
80106c2: d103 bne.n 80106cc <pbuf_free+0xd4>
mem_free(p);
80106c4: 6878 ldr r0, [r7, #4]
80106c6: f7fe fd7d bl 800f1c4 <mem_free>
80106ca: e006 b.n 80106da <pbuf_free+0xe2>
} else {
/* @todo: support freeing other types */
LWIP_ASSERT("invalid pbuf type", 0);
80106cc: 4b0b ldr r3, [pc, #44] ; (80106fc <pbuf_free+0x104>)
80106ce: f240 320f movw r2, #783 ; 0x30f
80106d2: 490f ldr r1, [pc, #60] ; (8010710 <pbuf_free+0x118>)
80106d4: 480b ldr r0, [pc, #44] ; (8010704 <pbuf_free+0x10c>)
80106d6: f00a fca5 bl 801b024 <iprintf>
}
}
count++;
80106da: 7ffb ldrb r3, [r7, #31]
80106dc: 3301 adds r3, #1
80106de: 77fb strb r3, [r7, #31]
/* proceed to next pbuf */
p = q;
80106e0: 693b ldr r3, [r7, #16]
80106e2: 607b str r3, [r7, #4]
80106e4: e001 b.n 80106ea <pbuf_free+0xf2>
/* p->ref > 0, this pbuf is still referenced to */
/* (and so the remaining pbufs in chain as well) */
} else {
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
/* stop walking through the chain */
p = NULL;
80106e6: 2300 movs r3, #0
80106e8: 607b str r3, [r7, #4]
while (p != NULL) {
80106ea: 687b ldr r3, [r7, #4]
80106ec: 2b00 cmp r3, #0
80106ee: d199 bne.n 8010624 <pbuf_free+0x2c>
}
}
PERF_STOP("pbuf_free");
/* return number of de-allocated pbufs */
return count;
80106f0: 7ffb ldrb r3, [r7, #31]
}
80106f2: 4618 mov r0, r3
80106f4: 3720 adds r7, #32
80106f6: 46bd mov sp, r7
80106f8: bd80 pop {r7, pc}
80106fa: bf00 nop
80106fc: 0801c658 .word 0x0801c658
8010700: 0801c7bc .word 0x0801c7bc
8010704: 0801c6b8 .word 0x0801c6b8
8010708: 0801c7e8 .word 0x0801c7e8
801070c: 0801c800 .word 0x0801c800
8010710: 0801c824 .word 0x0801c824
08010714 <pbuf_clen>:
* @param p first pbuf of chain
* @return the number of pbufs in a chain
*/
u16_t
pbuf_clen(const struct pbuf *p)
{
8010714: b480 push {r7}
8010716: b085 sub sp, #20
8010718: af00 add r7, sp, #0
801071a: 6078 str r0, [r7, #4]
u16_t len;
len = 0;
801071c: 2300 movs r3, #0
801071e: 81fb strh r3, [r7, #14]
while (p != NULL) {
8010720: e005 b.n 801072e <pbuf_clen+0x1a>
++len;
8010722: 89fb ldrh r3, [r7, #14]
8010724: 3301 adds r3, #1
8010726: 81fb strh r3, [r7, #14]
p = p->next;
8010728: 687b ldr r3, [r7, #4]
801072a: 681b ldr r3, [r3, #0]
801072c: 607b str r3, [r7, #4]
while (p != NULL) {
801072e: 687b ldr r3, [r7, #4]
8010730: 2b00 cmp r3, #0
8010732: d1f6 bne.n 8010722 <pbuf_clen+0xe>
}
return len;
8010734: 89fb ldrh r3, [r7, #14]
}
8010736: 4618 mov r0, r3
8010738: 3714 adds r7, #20
801073a: 46bd mov sp, r7
801073c: f85d 7b04 ldr.w r7, [sp], #4
8010740: 4770 bx lr
...
08010744 <pbuf_ref>:
* @param p pbuf to increase reference counter of
*
*/
void
pbuf_ref(struct pbuf *p)
{
8010744: b580 push {r7, lr}
8010746: b084 sub sp, #16
8010748: af00 add r7, sp, #0
801074a: 6078 str r0, [r7, #4]
/* pbuf given? */
if (p != NULL) {
801074c: 687b ldr r3, [r7, #4]
801074e: 2b00 cmp r3, #0
8010750: d016 beq.n 8010780 <pbuf_ref+0x3c>
SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
8010752: f00a fc03 bl 801af5c <sys_arch_protect>
8010756: 60f8 str r0, [r7, #12]
8010758: 687b ldr r3, [r7, #4]
801075a: 7b9b ldrb r3, [r3, #14]
801075c: 3301 adds r3, #1
801075e: b2da uxtb r2, r3
8010760: 687b ldr r3, [r7, #4]
8010762: 739a strb r2, [r3, #14]
8010764: 68f8 ldr r0, [r7, #12]
8010766: f00a fc07 bl 801af78 <sys_arch_unprotect>
LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
801076a: 687b ldr r3, [r7, #4]
801076c: 7b9b ldrb r3, [r3, #14]
801076e: 2b00 cmp r3, #0
8010770: d106 bne.n 8010780 <pbuf_ref+0x3c>
8010772: 4b05 ldr r3, [pc, #20] ; (8010788 <pbuf_ref+0x44>)
8010774: f240 3242 movw r2, #834 ; 0x342
8010778: 4904 ldr r1, [pc, #16] ; (801078c <pbuf_ref+0x48>)
801077a: 4805 ldr r0, [pc, #20] ; (8010790 <pbuf_ref+0x4c>)
801077c: f00a fc52 bl 801b024 <iprintf>
}
}
8010780: bf00 nop
8010782: 3710 adds r7, #16
8010784: 46bd mov sp, r7
8010786: bd80 pop {r7, pc}
8010788: 0801c658 .word 0x0801c658
801078c: 0801c838 .word 0x0801c838
8010790: 0801c6b8 .word 0x0801c6b8
08010794 <pbuf_cat>:
*
* @see pbuf_chain()
*/
void
pbuf_cat(struct pbuf *h, struct pbuf *t)
{
8010794: b580 push {r7, lr}
8010796: b084 sub sp, #16
8010798: af00 add r7, sp, #0
801079a: 6078 str r0, [r7, #4]
801079c: 6039 str r1, [r7, #0]
struct pbuf *p;
LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
801079e: 687b ldr r3, [r7, #4]
80107a0: 2b00 cmp r3, #0
80107a2: d002 beq.n 80107aa <pbuf_cat+0x16>
80107a4: 683b ldr r3, [r7, #0]
80107a6: 2b00 cmp r3, #0
80107a8: d107 bne.n 80107ba <pbuf_cat+0x26>
80107aa: 4b20 ldr r3, [pc, #128] ; (801082c <pbuf_cat+0x98>)
80107ac: f240 325a movw r2, #858 ; 0x35a
80107b0: 491f ldr r1, [pc, #124] ; (8010830 <pbuf_cat+0x9c>)
80107b2: 4820 ldr r0, [pc, #128] ; (8010834 <pbuf_cat+0xa0>)
80107b4: f00a fc36 bl 801b024 <iprintf>
80107b8: e034 b.n 8010824 <pbuf_cat+0x90>
((h != NULL) && (t != NULL)), return;);
/* proceed to last pbuf of chain */
for (p = h; p->next != NULL; p = p->next) {
80107ba: 687b ldr r3, [r7, #4]
80107bc: 60fb str r3, [r7, #12]
80107be: e00a b.n 80107d6 <pbuf_cat+0x42>
/* add total length of second chain to all totals of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
80107c0: 68fb ldr r3, [r7, #12]
80107c2: 891a ldrh r2, [r3, #8]
80107c4: 683b ldr r3, [r7, #0]
80107c6: 891b ldrh r3, [r3, #8]
80107c8: 4413 add r3, r2
80107ca: b29a uxth r2, r3
80107cc: 68fb ldr r3, [r7, #12]
80107ce: 811a strh r2, [r3, #8]
for (p = h; p->next != NULL; p = p->next) {
80107d0: 68fb ldr r3, [r7, #12]
80107d2: 681b ldr r3, [r3, #0]
80107d4: 60fb str r3, [r7, #12]
80107d6: 68fb ldr r3, [r7, #12]
80107d8: 681b ldr r3, [r3, #0]
80107da: 2b00 cmp r3, #0
80107dc: d1f0 bne.n 80107c0 <pbuf_cat+0x2c>
}
/* { p is last pbuf of first h chain, p->next == NULL } */
LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
80107de: 68fb ldr r3, [r7, #12]
80107e0: 891a ldrh r2, [r3, #8]
80107e2: 68fb ldr r3, [r7, #12]
80107e4: 895b ldrh r3, [r3, #10]
80107e6: 429a cmp r2, r3
80107e8: d006 beq.n 80107f8 <pbuf_cat+0x64>
80107ea: 4b10 ldr r3, [pc, #64] ; (801082c <pbuf_cat+0x98>)
80107ec: f240 3262 movw r2, #866 ; 0x362
80107f0: 4911 ldr r1, [pc, #68] ; (8010838 <pbuf_cat+0xa4>)
80107f2: 4810 ldr r0, [pc, #64] ; (8010834 <pbuf_cat+0xa0>)
80107f4: f00a fc16 bl 801b024 <iprintf>
LWIP_ASSERT("p->next == NULL", p->next == NULL);
80107f8: 68fb ldr r3, [r7, #12]
80107fa: 681b ldr r3, [r3, #0]
80107fc: 2b00 cmp r3, #0
80107fe: d006 beq.n 801080e <pbuf_cat+0x7a>
8010800: 4b0a ldr r3, [pc, #40] ; (801082c <pbuf_cat+0x98>)
8010802: f240 3263 movw r2, #867 ; 0x363
8010806: 490d ldr r1, [pc, #52] ; (801083c <pbuf_cat+0xa8>)
8010808: 480a ldr r0, [pc, #40] ; (8010834 <pbuf_cat+0xa0>)
801080a: f00a fc0b bl 801b024 <iprintf>
/* add total length of second chain to last pbuf total of first chain */
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
801080e: 68fb ldr r3, [r7, #12]
8010810: 891a ldrh r2, [r3, #8]
8010812: 683b ldr r3, [r7, #0]
8010814: 891b ldrh r3, [r3, #8]
8010816: 4413 add r3, r2
8010818: b29a uxth r2, r3
801081a: 68fb ldr r3, [r7, #12]
801081c: 811a strh r2, [r3, #8]
/* chain last pbuf of head (p) with first of tail (t) */
p->next = t;
801081e: 68fb ldr r3, [r7, #12]
8010820: 683a ldr r2, [r7, #0]
8010822: 601a str r2, [r3, #0]
/* p->next now references t, but the caller will drop its reference to t,
* so netto there is no change to the reference count of t.
*/
}
8010824: 3710 adds r7, #16
8010826: 46bd mov sp, r7
8010828: bd80 pop {r7, pc}
801082a: bf00 nop
801082c: 0801c658 .word 0x0801c658
8010830: 0801c84c .word 0x0801c84c
8010834: 0801c6b8 .word 0x0801c6b8
8010838: 0801c884 .word 0x0801c884
801083c: 0801c8b4 .word 0x0801c8b4
08010840 <pbuf_chain>:
* The ->ref field of the first pbuf of the tail chain is adjusted.
*
*/
void
pbuf_chain(struct pbuf *h, struct pbuf *t)
{
8010840: b580 push {r7, lr}
8010842: b082 sub sp, #8
8010844: af00 add r7, sp, #0
8010846: 6078 str r0, [r7, #4]
8010848: 6039 str r1, [r7, #0]
pbuf_cat(h, t);
801084a: 6839 ldr r1, [r7, #0]
801084c: 6878 ldr r0, [r7, #4]
801084e: f7ff ffa1 bl 8010794 <pbuf_cat>
/* t is now referenced by h */
pbuf_ref(t);
8010852: 6838 ldr r0, [r7, #0]
8010854: f7ff ff76 bl 8010744 <pbuf_ref>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
}
8010858: bf00 nop
801085a: 3708 adds r7, #8
801085c: 46bd mov sp, r7
801085e: bd80 pop {r7, pc}
08010860 <pbuf_copy>:
* ERR_ARG if one of the pbufs is NULL or p_to is not big
* enough to hold p_from
*/
err_t
pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
{
8010860: b580 push {r7, lr}
8010862: b086 sub sp, #24
8010864: af00 add r7, sp, #0
8010866: 6078 str r0, [r7, #4]
8010868: 6039 str r1, [r7, #0]
size_t offset_to = 0, offset_from = 0, len;
801086a: 2300 movs r3, #0
801086c: 617b str r3, [r7, #20]
801086e: 2300 movs r3, #0
8010870: 613b str r3, [r7, #16]
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
(const void *)p_to, (const void *)p_from));
/* is the target big enough to hold the source? */
LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
8010872: 687b ldr r3, [r7, #4]
8010874: 2b00 cmp r3, #0
8010876: d008 beq.n 801088a <pbuf_copy+0x2a>
8010878: 683b ldr r3, [r7, #0]
801087a: 2b00 cmp r3, #0
801087c: d005 beq.n 801088a <pbuf_copy+0x2a>
801087e: 687b ldr r3, [r7, #4]
8010880: 891a ldrh r2, [r3, #8]
8010882: 683b ldr r3, [r7, #0]
8010884: 891b ldrh r3, [r3, #8]
8010886: 429a cmp r2, r3
8010888: d209 bcs.n 801089e <pbuf_copy+0x3e>
801088a: 4b57 ldr r3, [pc, #348] ; (80109e8 <pbuf_copy+0x188>)
801088c: f240 32ca movw r2, #970 ; 0x3ca
8010890: 4956 ldr r1, [pc, #344] ; (80109ec <pbuf_copy+0x18c>)
8010892: 4857 ldr r0, [pc, #348] ; (80109f0 <pbuf_copy+0x190>)
8010894: f00a fbc6 bl 801b024 <iprintf>
8010898: f06f 030f mvn.w r3, #15
801089c: e09f b.n 80109de <pbuf_copy+0x17e>
(p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
/* iterate through pbuf chain */
do {
/* copy one part of the original chain */
if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
801089e: 687b ldr r3, [r7, #4]
80108a0: 895b ldrh r3, [r3, #10]
80108a2: 461a mov r2, r3
80108a4: 697b ldr r3, [r7, #20]
80108a6: 1ad2 subs r2, r2, r3
80108a8: 683b ldr r3, [r7, #0]
80108aa: 895b ldrh r3, [r3, #10]
80108ac: 4619 mov r1, r3
80108ae: 693b ldr r3, [r7, #16]
80108b0: 1acb subs r3, r1, r3
80108b2: 429a cmp r2, r3
80108b4: d306 bcc.n 80108c4 <pbuf_copy+0x64>
/* complete current p_from fits into current p_to */
len = p_from->len - offset_from;
80108b6: 683b ldr r3, [r7, #0]
80108b8: 895b ldrh r3, [r3, #10]
80108ba: 461a mov r2, r3
80108bc: 693b ldr r3, [r7, #16]
80108be: 1ad3 subs r3, r2, r3
80108c0: 60fb str r3, [r7, #12]
80108c2: e005 b.n 80108d0 <pbuf_copy+0x70>
} else {
/* current p_from does not fit into current p_to */
len = p_to->len - offset_to;
80108c4: 687b ldr r3, [r7, #4]
80108c6: 895b ldrh r3, [r3, #10]
80108c8: 461a mov r2, r3
80108ca: 697b ldr r3, [r7, #20]
80108cc: 1ad3 subs r3, r2, r3
80108ce: 60fb str r3, [r7, #12]
}
MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
80108d0: 687b ldr r3, [r7, #4]
80108d2: 685a ldr r2, [r3, #4]
80108d4: 697b ldr r3, [r7, #20]
80108d6: 18d0 adds r0, r2, r3
80108d8: 683b ldr r3, [r7, #0]
80108da: 685a ldr r2, [r3, #4]
80108dc: 693b ldr r3, [r7, #16]
80108de: 4413 add r3, r2
80108e0: 68fa ldr r2, [r7, #12]
80108e2: 4619 mov r1, r3
80108e4: f00a fb8b bl 801affe <memcpy>
offset_to += len;
80108e8: 697a ldr r2, [r7, #20]
80108ea: 68fb ldr r3, [r7, #12]
80108ec: 4413 add r3, r2
80108ee: 617b str r3, [r7, #20]
offset_from += len;
80108f0: 693a ldr r2, [r7, #16]
80108f2: 68fb ldr r3, [r7, #12]
80108f4: 4413 add r3, r2
80108f6: 613b str r3, [r7, #16]
LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
80108f8: 687b ldr r3, [r7, #4]
80108fa: 895b ldrh r3, [r3, #10]
80108fc: 461a mov r2, r3
80108fe: 697b ldr r3, [r7, #20]
8010900: 4293 cmp r3, r2
8010902: d906 bls.n 8010912 <pbuf_copy+0xb2>
8010904: 4b38 ldr r3, [pc, #224] ; (80109e8 <pbuf_copy+0x188>)
8010906: f240 32d9 movw r2, #985 ; 0x3d9
801090a: 493a ldr r1, [pc, #232] ; (80109f4 <pbuf_copy+0x194>)
801090c: 4838 ldr r0, [pc, #224] ; (80109f0 <pbuf_copy+0x190>)
801090e: f00a fb89 bl 801b024 <iprintf>
LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
8010912: 683b ldr r3, [r7, #0]
8010914: 895b ldrh r3, [r3, #10]
8010916: 461a mov r2, r3
8010918: 693b ldr r3, [r7, #16]
801091a: 4293 cmp r3, r2
801091c: d906 bls.n 801092c <pbuf_copy+0xcc>
801091e: 4b32 ldr r3, [pc, #200] ; (80109e8 <pbuf_copy+0x188>)
8010920: f240 32da movw r2, #986 ; 0x3da
8010924: 4934 ldr r1, [pc, #208] ; (80109f8 <pbuf_copy+0x198>)
8010926: 4832 ldr r0, [pc, #200] ; (80109f0 <pbuf_copy+0x190>)
8010928: f00a fb7c bl 801b024 <iprintf>
if (offset_from >= p_from->len) {
801092c: 683b ldr r3, [r7, #0]
801092e: 895b ldrh r3, [r3, #10]
8010930: 461a mov r2, r3
8010932: 693b ldr r3, [r7, #16]
8010934: 4293 cmp r3, r2
8010936: d304 bcc.n 8010942 <pbuf_copy+0xe2>
/* on to next p_from (if any) */
offset_from = 0;
8010938: 2300 movs r3, #0
801093a: 613b str r3, [r7, #16]
p_from = p_from->next;
801093c: 683b ldr r3, [r7, #0]
801093e: 681b ldr r3, [r3, #0]
8010940: 603b str r3, [r7, #0]
}
if (offset_to == p_to->len) {
8010942: 687b ldr r3, [r7, #4]
8010944: 895b ldrh r3, [r3, #10]
8010946: 461a mov r2, r3
8010948: 697b ldr r3, [r7, #20]
801094a: 4293 cmp r3, r2
801094c: d114 bne.n 8010978 <pbuf_copy+0x118>
/* on to next p_to (if any) */
offset_to = 0;
801094e: 2300 movs r3, #0
8010950: 617b str r3, [r7, #20]
p_to = p_to->next;
8010952: 687b ldr r3, [r7, #4]
8010954: 681b ldr r3, [r3, #0]
8010956: 607b str r3, [r7, #4]
LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
8010958: 687b ldr r3, [r7, #4]
801095a: 2b00 cmp r3, #0
801095c: d10c bne.n 8010978 <pbuf_copy+0x118>
801095e: 683b ldr r3, [r7, #0]
8010960: 2b00 cmp r3, #0
8010962: d009 beq.n 8010978 <pbuf_copy+0x118>
8010964: 4b20 ldr r3, [pc, #128] ; (80109e8 <pbuf_copy+0x188>)
8010966: f44f 7279 mov.w r2, #996 ; 0x3e4
801096a: 4924 ldr r1, [pc, #144] ; (80109fc <pbuf_copy+0x19c>)
801096c: 4820 ldr r0, [pc, #128] ; (80109f0 <pbuf_copy+0x190>)
801096e: f00a fb59 bl 801b024 <iprintf>
8010972: f06f 030f mvn.w r3, #15
8010976: e032 b.n 80109de <pbuf_copy+0x17e>
}
if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
8010978: 683b ldr r3, [r7, #0]
801097a: 2b00 cmp r3, #0
801097c: d013 beq.n 80109a6 <pbuf_copy+0x146>
801097e: 683b ldr r3, [r7, #0]
8010980: 895a ldrh r2, [r3, #10]
8010982: 683b ldr r3, [r7, #0]
8010984: 891b ldrh r3, [r3, #8]
8010986: 429a cmp r2, r3
8010988: d10d bne.n 80109a6 <pbuf_copy+0x146>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
801098a: 683b ldr r3, [r7, #0]
801098c: 681b ldr r3, [r3, #0]
801098e: 2b00 cmp r3, #0
8010990: d009 beq.n 80109a6 <pbuf_copy+0x146>
8010992: 4b15 ldr r3, [pc, #84] ; (80109e8 <pbuf_copy+0x188>)
8010994: f240 32ea movw r2, #1002 ; 0x3ea
8010998: 4919 ldr r1, [pc, #100] ; (8010a00 <pbuf_copy+0x1a0>)
801099a: 4815 ldr r0, [pc, #84] ; (80109f0 <pbuf_copy+0x190>)
801099c: f00a fb42 bl 801b024 <iprintf>
80109a0: f06f 0305 mvn.w r3, #5
80109a4: e01b b.n 80109de <pbuf_copy+0x17e>
(p_from->next == NULL), return ERR_VAL;);
}
if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
80109a6: 687b ldr r3, [r7, #4]
80109a8: 2b00 cmp r3, #0
80109aa: d013 beq.n 80109d4 <pbuf_copy+0x174>
80109ac: 687b ldr r3, [r7, #4]
80109ae: 895a ldrh r2, [r3, #10]
80109b0: 687b ldr r3, [r7, #4]
80109b2: 891b ldrh r3, [r3, #8]
80109b4: 429a cmp r2, r3
80109b6: d10d bne.n 80109d4 <pbuf_copy+0x174>
/* don't copy more than one packet! */
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
80109b8: 687b ldr r3, [r7, #4]
80109ba: 681b ldr r3, [r3, #0]
80109bc: 2b00 cmp r3, #0
80109be: d009 beq.n 80109d4 <pbuf_copy+0x174>
80109c0: 4b09 ldr r3, [pc, #36] ; (80109e8 <pbuf_copy+0x188>)
80109c2: f240 32ef movw r2, #1007 ; 0x3ef
80109c6: 490e ldr r1, [pc, #56] ; (8010a00 <pbuf_copy+0x1a0>)
80109c8: 4809 ldr r0, [pc, #36] ; (80109f0 <pbuf_copy+0x190>)
80109ca: f00a fb2b bl 801b024 <iprintf>
80109ce: f06f 0305 mvn.w r3, #5
80109d2: e004 b.n 80109de <pbuf_copy+0x17e>
(p_to->next == NULL), return ERR_VAL;);
}
} while (p_from);
80109d4: 683b ldr r3, [r7, #0]
80109d6: 2b00 cmp r3, #0
80109d8: f47f af61 bne.w 801089e <pbuf_copy+0x3e>
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
return ERR_OK;
80109dc: 2300 movs r3, #0
}
80109de: 4618 mov r0, r3
80109e0: 3718 adds r7, #24
80109e2: 46bd mov sp, r7
80109e4: bd80 pop {r7, pc}
80109e6: bf00 nop
80109e8: 0801c658 .word 0x0801c658
80109ec: 0801c900 .word 0x0801c900
80109f0: 0801c6b8 .word 0x0801c6b8
80109f4: 0801c930 .word 0x0801c930
80109f8: 0801c948 .word 0x0801c948
80109fc: 0801c964 .word 0x0801c964
8010a00: 0801c974 .word 0x0801c974
08010a04 <pbuf_copy_partial>:
* @param offset offset into the packet buffer from where to begin copying len bytes
* @return the number of bytes copied, or 0 on failure
*/
u16_t
pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
{
8010a04: b580 push {r7, lr}
8010a06: b088 sub sp, #32
8010a08: af00 add r7, sp, #0
8010a0a: 60f8 str r0, [r7, #12]
8010a0c: 60b9 str r1, [r7, #8]
8010a0e: 4611 mov r1, r2
8010a10: 461a mov r2, r3
8010a12: 460b mov r3, r1
8010a14: 80fb strh r3, [r7, #6]
8010a16: 4613 mov r3, r2
8010a18: 80bb strh r3, [r7, #4]
const struct pbuf *p;
u16_t left = 0;
8010a1a: 2300 movs r3, #0
8010a1c: 837b strh r3, [r7, #26]
u16_t buf_copy_len;
u16_t copied_total = 0;
8010a1e: 2300 movs r3, #0
8010a20: 82fb strh r3, [r7, #22]
LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
8010a22: 68fb ldr r3, [r7, #12]
8010a24: 2b00 cmp r3, #0
8010a26: d108 bne.n 8010a3a <pbuf_copy_partial+0x36>
8010a28: 4b2b ldr r3, [pc, #172] ; (8010ad8 <pbuf_copy_partial+0xd4>)
8010a2a: f240 420a movw r2, #1034 ; 0x40a
8010a2e: 492b ldr r1, [pc, #172] ; (8010adc <pbuf_copy_partial+0xd8>)
8010a30: 482b ldr r0, [pc, #172] ; (8010ae0 <pbuf_copy_partial+0xdc>)
8010a32: f00a faf7 bl 801b024 <iprintf>
8010a36: 2300 movs r3, #0
8010a38: e04a b.n 8010ad0 <pbuf_copy_partial+0xcc>
LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
8010a3a: 68bb ldr r3, [r7, #8]
8010a3c: 2b00 cmp r3, #0
8010a3e: d108 bne.n 8010a52 <pbuf_copy_partial+0x4e>
8010a40: 4b25 ldr r3, [pc, #148] ; (8010ad8 <pbuf_copy_partial+0xd4>)
8010a42: f240 420b movw r2, #1035 ; 0x40b
8010a46: 4927 ldr r1, [pc, #156] ; (8010ae4 <pbuf_copy_partial+0xe0>)
8010a48: 4825 ldr r0, [pc, #148] ; (8010ae0 <pbuf_copy_partial+0xdc>)
8010a4a: f00a faeb bl 801b024 <iprintf>
8010a4e: 2300 movs r3, #0
8010a50: e03e b.n 8010ad0 <pbuf_copy_partial+0xcc>
/* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010a52: 68fb ldr r3, [r7, #12]
8010a54: 61fb str r3, [r7, #28]
8010a56: e034 b.n 8010ac2 <pbuf_copy_partial+0xbe>
if ((offset != 0) && (offset >= p->len)) {
8010a58: 88bb ldrh r3, [r7, #4]
8010a5a: 2b00 cmp r3, #0
8010a5c: d00a beq.n 8010a74 <pbuf_copy_partial+0x70>
8010a5e: 69fb ldr r3, [r7, #28]
8010a60: 895b ldrh r3, [r3, #10]
8010a62: 88ba ldrh r2, [r7, #4]
8010a64: 429a cmp r2, r3
8010a66: d305 bcc.n 8010a74 <pbuf_copy_partial+0x70>
/* don't copy from this buffer -> on to the next */
offset = (u16_t)(offset - p->len);
8010a68: 69fb ldr r3, [r7, #28]
8010a6a: 895b ldrh r3, [r3, #10]
8010a6c: 88ba ldrh r2, [r7, #4]
8010a6e: 1ad3 subs r3, r2, r3
8010a70: 80bb strh r3, [r7, #4]
8010a72: e023 b.n 8010abc <pbuf_copy_partial+0xb8>
} else {
/* copy from this buffer. maybe only partially. */
buf_copy_len = (u16_t)(p->len - offset);
8010a74: 69fb ldr r3, [r7, #28]
8010a76: 895a ldrh r2, [r3, #10]
8010a78: 88bb ldrh r3, [r7, #4]
8010a7a: 1ad3 subs r3, r2, r3
8010a7c: 833b strh r3, [r7, #24]
if (buf_copy_len > len) {
8010a7e: 8b3a ldrh r2, [r7, #24]
8010a80: 88fb ldrh r3, [r7, #6]
8010a82: 429a cmp r2, r3
8010a84: d901 bls.n 8010a8a <pbuf_copy_partial+0x86>
buf_copy_len = len;
8010a86: 88fb ldrh r3, [r7, #6]
8010a88: 833b strh r3, [r7, #24]
}
/* copy the necessary parts of the buffer */
MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
8010a8a: 8b7b ldrh r3, [r7, #26]
8010a8c: 68ba ldr r2, [r7, #8]
8010a8e: 18d0 adds r0, r2, r3
8010a90: 69fb ldr r3, [r7, #28]
8010a92: 685a ldr r2, [r3, #4]
8010a94: 88bb ldrh r3, [r7, #4]
8010a96: 4413 add r3, r2
8010a98: 8b3a ldrh r2, [r7, #24]
8010a9a: 4619 mov r1, r3
8010a9c: f00a faaf bl 801affe <memcpy>
copied_total = (u16_t)(copied_total + buf_copy_len);
8010aa0: 8afa ldrh r2, [r7, #22]
8010aa2: 8b3b ldrh r3, [r7, #24]
8010aa4: 4413 add r3, r2
8010aa6: 82fb strh r3, [r7, #22]
left = (u16_t)(left + buf_copy_len);
8010aa8: 8b7a ldrh r2, [r7, #26]
8010aaa: 8b3b ldrh r3, [r7, #24]
8010aac: 4413 add r3, r2
8010aae: 837b strh r3, [r7, #26]
len = (u16_t)(len - buf_copy_len);
8010ab0: 88fa ldrh r2, [r7, #6]
8010ab2: 8b3b ldrh r3, [r7, #24]
8010ab4: 1ad3 subs r3, r2, r3
8010ab6: 80fb strh r3, [r7, #6]
offset = 0;
8010ab8: 2300 movs r3, #0
8010aba: 80bb strh r3, [r7, #4]
for (p = buf; len != 0 && p != NULL; p = p->next) {
8010abc: 69fb ldr r3, [r7, #28]
8010abe: 681b ldr r3, [r3, #0]
8010ac0: 61fb str r3, [r7, #28]
8010ac2: 88fb ldrh r3, [r7, #6]
8010ac4: 2b00 cmp r3, #0
8010ac6: d002 beq.n 8010ace <pbuf_copy_partial+0xca>
8010ac8: 69fb ldr r3, [r7, #28]
8010aca: 2b00 cmp r3, #0
8010acc: d1c4 bne.n 8010a58 <pbuf_copy_partial+0x54>
}
}
return copied_total;
8010ace: 8afb ldrh r3, [r7, #22]
}
8010ad0: 4618 mov r0, r3
8010ad2: 3720 adds r7, #32
8010ad4: 46bd mov sp, r7
8010ad6: bd80 pop {r7, pc}
8010ad8: 0801c658 .word 0x0801c658
8010adc: 0801c9a0 .word 0x0801c9a0
8010ae0: 0801c6b8 .word 0x0801c6b8
8010ae4: 0801c9c0 .word 0x0801c9c0
08010ae8 <pbuf_clone>:
*
* @return a new pbuf or NULL if allocation fails
*/
struct pbuf *
pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
{
8010ae8: b580 push {r7, lr}
8010aea: b084 sub sp, #16
8010aec: af00 add r7, sp, #0
8010aee: 4603 mov r3, r0
8010af0: 603a str r2, [r7, #0]
8010af2: 71fb strb r3, [r7, #7]
8010af4: 460b mov r3, r1
8010af6: 80bb strh r3, [r7, #4]
struct pbuf *q;
err_t err;
q = pbuf_alloc(layer, p->tot_len, type);
8010af8: 683b ldr r3, [r7, #0]
8010afa: 8919 ldrh r1, [r3, #8]
8010afc: 88ba ldrh r2, [r7, #4]
8010afe: 79fb ldrb r3, [r7, #7]
8010b00: 4618 mov r0, r3
8010b02: f7ff fa99 bl 8010038 <pbuf_alloc>
8010b06: 60f8 str r0, [r7, #12]
if (q == NULL) {
8010b08: 68fb ldr r3, [r7, #12]
8010b0a: 2b00 cmp r3, #0
8010b0c: d101 bne.n 8010b12 <pbuf_clone+0x2a>
return NULL;
8010b0e: 2300 movs r3, #0
8010b10: e011 b.n 8010b36 <pbuf_clone+0x4e>
}
err = pbuf_copy(q, p);
8010b12: 6839 ldr r1, [r7, #0]
8010b14: 68f8 ldr r0, [r7, #12]
8010b16: f7ff fea3 bl 8010860 <pbuf_copy>
8010b1a: 4603 mov r3, r0
8010b1c: 72fb strb r3, [r7, #11]
LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
8010b1e: f997 300b ldrsb.w r3, [r7, #11]
8010b22: 2b00 cmp r3, #0
8010b24: d006 beq.n 8010b34 <pbuf_clone+0x4c>
8010b26: 4b06 ldr r3, [pc, #24] ; (8010b40 <pbuf_clone+0x58>)
8010b28: f240 5224 movw r2, #1316 ; 0x524
8010b2c: 4905 ldr r1, [pc, #20] ; (8010b44 <pbuf_clone+0x5c>)
8010b2e: 4806 ldr r0, [pc, #24] ; (8010b48 <pbuf_clone+0x60>)
8010b30: f00a fa78 bl 801b024 <iprintf>
return q;
8010b34: 68fb ldr r3, [r7, #12]
}
8010b36: 4618 mov r0, r3
8010b38: 3710 adds r7, #16
8010b3a: 46bd mov sp, r7
8010b3c: bd80 pop {r7, pc}
8010b3e: bf00 nop
8010b40: 0801c658 .word 0x0801c658
8010b44: 0801cacc .word 0x0801cacc
8010b48: 0801c6b8 .word 0x0801c6b8
08010b4c <tcp_init>:
/**
* Initialize this module.
*/
void
tcp_init(void)
{
8010b4c: b580 push {r7, lr}
8010b4e: af00 add r7, sp, #0
#ifdef LWIP_RAND
tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
8010b50: f00a fa80 bl 801b054 <rand>
8010b54: 4603 mov r3, r0
8010b56: b29b uxth r3, r3
8010b58: f3c3 030d ubfx r3, r3, #0, #14
8010b5c: b29b uxth r3, r3
8010b5e: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
8010b62: b29a uxth r2, r3
8010b64: 4b01 ldr r3, [pc, #4] ; (8010b6c <tcp_init+0x20>)
8010b66: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
8010b68: bf00 nop
8010b6a: bd80 pop {r7, pc}
8010b6c: 20000074 .word 0x20000074
08010b70 <tcp_free>:
/** Free a tcp pcb */
void
tcp_free(struct tcp_pcb *pcb)
{
8010b70: b580 push {r7, lr}
8010b72: b082 sub sp, #8
8010b74: af00 add r7, sp, #0
8010b76: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
8010b78: 687b ldr r3, [r7, #4]
8010b7a: 7d1b ldrb r3, [r3, #20]
8010b7c: 2b01 cmp r3, #1
8010b7e: d105 bne.n 8010b8c <tcp_free+0x1c>
8010b80: 4b06 ldr r3, [pc, #24] ; (8010b9c <tcp_free+0x2c>)
8010b82: 22d4 movs r2, #212 ; 0xd4
8010b84: 4906 ldr r1, [pc, #24] ; (8010ba0 <tcp_free+0x30>)
8010b86: 4807 ldr r0, [pc, #28] ; (8010ba4 <tcp_free+0x34>)
8010b88: f00a fa4c bl 801b024 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB, pcb);
8010b8c: 6879 ldr r1, [r7, #4]
8010b8e: 2001 movs r0, #1
8010b90: f7fe fe86 bl 800f8a0 <memp_free>
}
8010b94: bf00 nop
8010b96: 3708 adds r7, #8
8010b98: 46bd mov sp, r7
8010b9a: bd80 pop {r7, pc}
8010b9c: 0801cb58 .word 0x0801cb58
8010ba0: 0801cb88 .word 0x0801cb88
8010ba4: 0801cb9c .word 0x0801cb9c
08010ba8 <tcp_free_listen>:
/** Free a tcp listen pcb */
static void
tcp_free_listen(struct tcp_pcb *pcb)
{
8010ba8: b580 push {r7, lr}
8010baa: b082 sub sp, #8
8010bac: af00 add r7, sp, #0
8010bae: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
8010bb0: 687b ldr r3, [r7, #4]
8010bb2: 7d1b ldrb r3, [r3, #20]
8010bb4: 2b01 cmp r3, #1
8010bb6: d105 bne.n 8010bc4 <tcp_free_listen+0x1c>
8010bb8: 4b06 ldr r3, [pc, #24] ; (8010bd4 <tcp_free_listen+0x2c>)
8010bba: 22df movs r2, #223 ; 0xdf
8010bbc: 4906 ldr r1, [pc, #24] ; (8010bd8 <tcp_free_listen+0x30>)
8010bbe: 4807 ldr r0, [pc, #28] ; (8010bdc <tcp_free_listen+0x34>)
8010bc0: f00a fa30 bl 801b024 <iprintf>
#if LWIP_TCP_PCB_NUM_EXT_ARGS
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
#endif
memp_free(MEMP_TCP_PCB_LISTEN, pcb);
8010bc4: 6879 ldr r1, [r7, #4]
8010bc6: 2002 movs r0, #2
8010bc8: f7fe fe6a bl 800f8a0 <memp_free>
}
8010bcc: bf00 nop
8010bce: 3708 adds r7, #8
8010bd0: 46bd mov sp, r7
8010bd2: bd80 pop {r7, pc}
8010bd4: 0801cb58 .word 0x0801cb58
8010bd8: 0801cbc4 .word 0x0801cbc4
8010bdc: 0801cb9c .word 0x0801cb9c
08010be0 <tcp_tmr>:
/**
* Called periodically to dispatch TCP timers.
*/
void
tcp_tmr(void)
{
8010be0: b580 push {r7, lr}
8010be2: af00 add r7, sp, #0
/* Call tcp_fasttmr() every 250 ms */
tcp_fasttmr();
8010be4: f000 fe98 bl 8011918 <tcp_fasttmr>
if (++tcp_timer & 1) {
8010be8: 4b07 ldr r3, [pc, #28] ; (8010c08 <tcp_tmr+0x28>)
8010bea: 781b ldrb r3, [r3, #0]
8010bec: 3301 adds r3, #1
8010bee: b2da uxtb r2, r3
8010bf0: 4b05 ldr r3, [pc, #20] ; (8010c08 <tcp_tmr+0x28>)
8010bf2: 701a strb r2, [r3, #0]
8010bf4: 4b04 ldr r3, [pc, #16] ; (8010c08 <tcp_tmr+0x28>)
8010bf6: 781b ldrb r3, [r3, #0]
8010bf8: f003 0301 and.w r3, r3, #1
8010bfc: 2b00 cmp r3, #0
8010bfe: d001 beq.n 8010c04 <tcp_tmr+0x24>
/* Call tcp_slowtmr() every 500 ms, i.e., every other timer
tcp_tmr() is called. */
tcp_slowtmr();
8010c00: f000 fb4c bl 801129c <tcp_slowtmr>
}
}
8010c04: bf00 nop
8010c06: bd80 pop {r7, pc}
8010c08: 20008729 .word 0x20008729
08010c0c <tcp_remove_listener>:
/** Called when a listen pcb is closed. Iterates one pcb list and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
{
8010c0c: b580 push {r7, lr}
8010c0e: b084 sub sp, #16
8010c10: af00 add r7, sp, #0
8010c12: 6078 str r0, [r7, #4]
8010c14: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
8010c16: 683b ldr r3, [r7, #0]
8010c18: 2b00 cmp r3, #0
8010c1a: d105 bne.n 8010c28 <tcp_remove_listener+0x1c>
8010c1c: 4b0d ldr r3, [pc, #52] ; (8010c54 <tcp_remove_listener+0x48>)
8010c1e: 22ff movs r2, #255 ; 0xff
8010c20: 490d ldr r1, [pc, #52] ; (8010c58 <tcp_remove_listener+0x4c>)
8010c22: 480e ldr r0, [pc, #56] ; (8010c5c <tcp_remove_listener+0x50>)
8010c24: f00a f9fe bl 801b024 <iprintf>
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010c28: 687b ldr r3, [r7, #4]
8010c2a: 60fb str r3, [r7, #12]
8010c2c: e00a b.n 8010c44 <tcp_remove_listener+0x38>
if (pcb->listener == lpcb) {
8010c2e: 68fb ldr r3, [r7, #12]
8010c30: 6fdb ldr r3, [r3, #124] ; 0x7c
8010c32: 683a ldr r2, [r7, #0]
8010c34: 429a cmp r2, r3
8010c36: d102 bne.n 8010c3e <tcp_remove_listener+0x32>
pcb->listener = NULL;
8010c38: 68fb ldr r3, [r7, #12]
8010c3a: 2200 movs r2, #0
8010c3c: 67da str r2, [r3, #124] ; 0x7c
for (pcb = list; pcb != NULL; pcb = pcb->next) {
8010c3e: 68fb ldr r3, [r7, #12]
8010c40: 68db ldr r3, [r3, #12]
8010c42: 60fb str r3, [r7, #12]
8010c44: 68fb ldr r3, [r7, #12]
8010c46: 2b00 cmp r3, #0
8010c48: d1f1 bne.n 8010c2e <tcp_remove_listener+0x22>
}
}
}
8010c4a: bf00 nop
8010c4c: 3710 adds r7, #16
8010c4e: 46bd mov sp, r7
8010c50: bd80 pop {r7, pc}
8010c52: bf00 nop
8010c54: 0801cb58 .word 0x0801cb58
8010c58: 0801cbe0 .word 0x0801cbe0
8010c5c: 0801cb9c .word 0x0801cb9c
08010c60 <tcp_listen_closed>:
/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
* closed listener pcb from pcb->listener if matching.
*/
static void
tcp_listen_closed(struct tcp_pcb *pcb)
{
8010c60: b580 push {r7, lr}
8010c62: b084 sub sp, #16
8010c64: af00 add r7, sp, #0
8010c66: 6078 str r0, [r7, #4]
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
size_t i;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010c68: 687b ldr r3, [r7, #4]
8010c6a: 2b00 cmp r3, #0
8010c6c: d106 bne.n 8010c7c <tcp_listen_closed+0x1c>
8010c6e: 4b14 ldr r3, [pc, #80] ; (8010cc0 <tcp_listen_closed+0x60>)
8010c70: f240 1211 movw r2, #273 ; 0x111
8010c74: 4913 ldr r1, [pc, #76] ; (8010cc4 <tcp_listen_closed+0x64>)
8010c76: 4814 ldr r0, [pc, #80] ; (8010cc8 <tcp_listen_closed+0x68>)
8010c78: f00a f9d4 bl 801b024 <iprintf>
LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
8010c7c: 687b ldr r3, [r7, #4]
8010c7e: 7d1b ldrb r3, [r3, #20]
8010c80: 2b01 cmp r3, #1
8010c82: d006 beq.n 8010c92 <tcp_listen_closed+0x32>
8010c84: 4b0e ldr r3, [pc, #56] ; (8010cc0 <tcp_listen_closed+0x60>)
8010c86: f44f 7289 mov.w r2, #274 ; 0x112
8010c8a: 4910 ldr r1, [pc, #64] ; (8010ccc <tcp_listen_closed+0x6c>)
8010c8c: 480e ldr r0, [pc, #56] ; (8010cc8 <tcp_listen_closed+0x68>)
8010c8e: f00a f9c9 bl 801b024 <iprintf>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010c92: 2301 movs r3, #1
8010c94: 60fb str r3, [r7, #12]
8010c96: e00b b.n 8010cb0 <tcp_listen_closed+0x50>
tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
8010c98: 4a0d ldr r2, [pc, #52] ; (8010cd0 <tcp_listen_closed+0x70>)
8010c9a: 68fb ldr r3, [r7, #12]
8010c9c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8010ca0: 681b ldr r3, [r3, #0]
8010ca2: 6879 ldr r1, [r7, #4]
8010ca4: 4618 mov r0, r3
8010ca6: f7ff ffb1 bl 8010c0c <tcp_remove_listener>
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
8010caa: 68fb ldr r3, [r7, #12]
8010cac: 3301 adds r3, #1
8010cae: 60fb str r3, [r7, #12]
8010cb0: 68fb ldr r3, [r7, #12]
8010cb2: 2b03 cmp r3, #3
8010cb4: d9f0 bls.n 8010c98 <tcp_listen_closed+0x38>
}
#endif
LWIP_UNUSED_ARG(pcb);
}
8010cb6: bf00 nop
8010cb8: 3710 adds r7, #16
8010cba: 46bd mov sp, r7
8010cbc: bd80 pop {r7, pc}
8010cbe: bf00 nop
8010cc0: 0801cb58 .word 0x0801cb58
8010cc4: 0801cc08 .word 0x0801cc08
8010cc8: 0801cb9c .word 0x0801cb9c
8010ccc: 0801cc14 .word 0x0801cc14
8010cd0: 08020e40 .word 0x08020e40
08010cd4 <tcp_close_shutdown>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
static err_t
tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
{
8010cd4: b5b0 push {r4, r5, r7, lr}
8010cd6: b088 sub sp, #32
8010cd8: af04 add r7, sp, #16
8010cda: 6078 str r0, [r7, #4]
8010cdc: 460b mov r3, r1
8010cde: 70fb strb r3, [r7, #3]
LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
8010ce0: 687b ldr r3, [r7, #4]
8010ce2: 2b00 cmp r3, #0
8010ce4: d106 bne.n 8010cf4 <tcp_close_shutdown+0x20>
8010ce6: 4b61 ldr r3, [pc, #388] ; (8010e6c <tcp_close_shutdown+0x198>)
8010ce8: f44f 72af mov.w r2, #350 ; 0x15e
8010cec: 4960 ldr r1, [pc, #384] ; (8010e70 <tcp_close_shutdown+0x19c>)
8010cee: 4861 ldr r0, [pc, #388] ; (8010e74 <tcp_close_shutdown+0x1a0>)
8010cf0: f00a f998 bl 801b024 <iprintf>
if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
8010cf4: 78fb ldrb r3, [r7, #3]
8010cf6: 2b00 cmp r3, #0
8010cf8: d066 beq.n 8010dc8 <tcp_close_shutdown+0xf4>
8010cfa: 687b ldr r3, [r7, #4]
8010cfc: 7d1b ldrb r3, [r3, #20]
8010cfe: 2b04 cmp r3, #4
8010d00: d003 beq.n 8010d0a <tcp_close_shutdown+0x36>
8010d02: 687b ldr r3, [r7, #4]
8010d04: 7d1b ldrb r3, [r3, #20]
8010d06: 2b07 cmp r3, #7
8010d08: d15e bne.n 8010dc8 <tcp_close_shutdown+0xf4>
if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
8010d0a: 687b ldr r3, [r7, #4]
8010d0c: 6f9b ldr r3, [r3, #120] ; 0x78
8010d0e: 2b00 cmp r3, #0
8010d10: d104 bne.n 8010d1c <tcp_close_shutdown+0x48>
8010d12: 687b ldr r3, [r7, #4]
8010d14: 8d1b ldrh r3, [r3, #40] ; 0x28
8010d16: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8010d1a: d055 beq.n 8010dc8 <tcp_close_shutdown+0xf4>
/* Not all data received by application, send RST to tell the remote
side about this. */
LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
8010d1c: 687b ldr r3, [r7, #4]
8010d1e: 8b5b ldrh r3, [r3, #26]
8010d20: f003 0310 and.w r3, r3, #16
8010d24: 2b00 cmp r3, #0
8010d26: d106 bne.n 8010d36 <tcp_close_shutdown+0x62>
8010d28: 4b50 ldr r3, [pc, #320] ; (8010e6c <tcp_close_shutdown+0x198>)
8010d2a: f44f 72b2 mov.w r2, #356 ; 0x164
8010d2e: 4952 ldr r1, [pc, #328] ; (8010e78 <tcp_close_shutdown+0x1a4>)
8010d30: 4850 ldr r0, [pc, #320] ; (8010e74 <tcp_close_shutdown+0x1a0>)
8010d32: f00a f977 bl 801b024 <iprintf>
/* don't call tcp_abort here: we must not deallocate the pcb since
that might not be expected when calling tcp_close */
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
8010d36: 687b ldr r3, [r7, #4]
8010d38: 6d18 ldr r0, [r3, #80] ; 0x50
8010d3a: 687b ldr r3, [r7, #4]
8010d3c: 6a5c ldr r4, [r3, #36] ; 0x24
8010d3e: 687d ldr r5, [r7, #4]
8010d40: 687b ldr r3, [r7, #4]
8010d42: 3304 adds r3, #4
8010d44: 687a ldr r2, [r7, #4]
8010d46: 8ad2 ldrh r2, [r2, #22]
8010d48: 6879 ldr r1, [r7, #4]
8010d4a: 8b09 ldrh r1, [r1, #24]
8010d4c: 9102 str r1, [sp, #8]
8010d4e: 9201 str r2, [sp, #4]
8010d50: 9300 str r3, [sp, #0]
8010d52: 462b mov r3, r5
8010d54: 4622 mov r2, r4
8010d56: 4601 mov r1, r0
8010d58: 6878 ldr r0, [r7, #4]
8010d5a: f004 fe91 bl 8015a80 <tcp_rst>
pcb->local_port, pcb->remote_port);
tcp_pcb_purge(pcb);
8010d5e: 6878 ldr r0, [r7, #4]
8010d60: f001 f8ba bl 8011ed8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8010d64: 4b45 ldr r3, [pc, #276] ; (8010e7c <tcp_close_shutdown+0x1a8>)
8010d66: 681b ldr r3, [r3, #0]
8010d68: 687a ldr r2, [r7, #4]
8010d6a: 429a cmp r2, r3
8010d6c: d105 bne.n 8010d7a <tcp_close_shutdown+0xa6>
8010d6e: 4b43 ldr r3, [pc, #268] ; (8010e7c <tcp_close_shutdown+0x1a8>)
8010d70: 681b ldr r3, [r3, #0]
8010d72: 68db ldr r3, [r3, #12]
8010d74: 4a41 ldr r2, [pc, #260] ; (8010e7c <tcp_close_shutdown+0x1a8>)
8010d76: 6013 str r3, [r2, #0]
8010d78: e013 b.n 8010da2 <tcp_close_shutdown+0xce>
8010d7a: 4b40 ldr r3, [pc, #256] ; (8010e7c <tcp_close_shutdown+0x1a8>)
8010d7c: 681b ldr r3, [r3, #0]
8010d7e: 60fb str r3, [r7, #12]
8010d80: e00c b.n 8010d9c <tcp_close_shutdown+0xc8>
8010d82: 68fb ldr r3, [r7, #12]
8010d84: 68db ldr r3, [r3, #12]
8010d86: 687a ldr r2, [r7, #4]
8010d88: 429a cmp r2, r3
8010d8a: d104 bne.n 8010d96 <tcp_close_shutdown+0xc2>
8010d8c: 687b ldr r3, [r7, #4]
8010d8e: 68da ldr r2, [r3, #12]
8010d90: 68fb ldr r3, [r7, #12]
8010d92: 60da str r2, [r3, #12]
8010d94: e005 b.n 8010da2 <tcp_close_shutdown+0xce>
8010d96: 68fb ldr r3, [r7, #12]
8010d98: 68db ldr r3, [r3, #12]
8010d9a: 60fb str r3, [r7, #12]
8010d9c: 68fb ldr r3, [r7, #12]
8010d9e: 2b00 cmp r3, #0
8010da0: d1ef bne.n 8010d82 <tcp_close_shutdown+0xae>
8010da2: 687b ldr r3, [r7, #4]
8010da4: 2200 movs r2, #0
8010da6: 60da str r2, [r3, #12]
8010da8: 4b35 ldr r3, [pc, #212] ; (8010e80 <tcp_close_shutdown+0x1ac>)
8010daa: 2201 movs r2, #1
8010dac: 701a strb r2, [r3, #0]
/* Deallocate the pcb since we already sent a RST for it */
if (tcp_input_pcb == pcb) {
8010dae: 4b35 ldr r3, [pc, #212] ; (8010e84 <tcp_close_shutdown+0x1b0>)
8010db0: 681b ldr r3, [r3, #0]
8010db2: 687a ldr r2, [r7, #4]
8010db4: 429a cmp r2, r3
8010db6: d102 bne.n 8010dbe <tcp_close_shutdown+0xea>
/* prevent using a deallocated pcb: free it from tcp_input later */
tcp_trigger_input_pcb_close();
8010db8: f003 fd4c bl 8014854 <tcp_trigger_input_pcb_close>
8010dbc: e002 b.n 8010dc4 <tcp_close_shutdown+0xf0>
} else {
tcp_free(pcb);
8010dbe: 6878 ldr r0, [r7, #4]
8010dc0: f7ff fed6 bl 8010b70 <tcp_free>
}
return ERR_OK;
8010dc4: 2300 movs r3, #0
8010dc6: e04d b.n 8010e64 <tcp_close_shutdown+0x190>
}
}
/* - states which free the pcb are handled here,
- states which send FIN and change state are handled in tcp_close_shutdown_fin() */
switch (pcb->state) {
8010dc8: 687b ldr r3, [r7, #4]
8010dca: 7d1b ldrb r3, [r3, #20]
8010dcc: 2b01 cmp r3, #1
8010dce: d02d beq.n 8010e2c <tcp_close_shutdown+0x158>
8010dd0: 2b02 cmp r3, #2
8010dd2: d036 beq.n 8010e42 <tcp_close_shutdown+0x16e>
8010dd4: 2b00 cmp r3, #0
8010dd6: d13f bne.n 8010e58 <tcp_close_shutdown+0x184>
* and the user needs some way to free it should the need arise.
* Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
* or for a pcb that has been used and then entered the CLOSED state
* is erroneous, but this should never happen as the pcb has in those cases
* been freed, and so any remaining handles are bogus. */
if (pcb->local_port != 0) {
8010dd8: 687b ldr r3, [r7, #4]
8010dda: 8adb ldrh r3, [r3, #22]
8010ddc: 2b00 cmp r3, #0
8010dde: d021 beq.n 8010e24 <tcp_close_shutdown+0x150>
TCP_RMV(&tcp_bound_pcbs, pcb);
8010de0: 4b29 ldr r3, [pc, #164] ; (8010e88 <tcp_close_shutdown+0x1b4>)
8010de2: 681b ldr r3, [r3, #0]
8010de4: 687a ldr r2, [r7, #4]
8010de6: 429a cmp r2, r3
8010de8: d105 bne.n 8010df6 <tcp_close_shutdown+0x122>
8010dea: 4b27 ldr r3, [pc, #156] ; (8010e88 <tcp_close_shutdown+0x1b4>)
8010dec: 681b ldr r3, [r3, #0]
8010dee: 68db ldr r3, [r3, #12]
8010df0: 4a25 ldr r2, [pc, #148] ; (8010e88 <tcp_close_shutdown+0x1b4>)
8010df2: 6013 str r3, [r2, #0]
8010df4: e013 b.n 8010e1e <tcp_close_shutdown+0x14a>
8010df6: 4b24 ldr r3, [pc, #144] ; (8010e88 <tcp_close_shutdown+0x1b4>)
8010df8: 681b ldr r3, [r3, #0]
8010dfa: 60bb str r3, [r7, #8]
8010dfc: e00c b.n 8010e18 <tcp_close_shutdown+0x144>
8010dfe: 68bb ldr r3, [r7, #8]
8010e00: 68db ldr r3, [r3, #12]
8010e02: 687a ldr r2, [r7, #4]
8010e04: 429a cmp r2, r3
8010e06: d104 bne.n 8010e12 <tcp_close_shutdown+0x13e>
8010e08: 687b ldr r3, [r7, #4]
8010e0a: 68da ldr r2, [r3, #12]
8010e0c: 68bb ldr r3, [r7, #8]
8010e0e: 60da str r2, [r3, #12]
8010e10: e005 b.n 8010e1e <tcp_close_shutdown+0x14a>
8010e12: 68bb ldr r3, [r7, #8]
8010e14: 68db ldr r3, [r3, #12]
8010e16: 60bb str r3, [r7, #8]
8010e18: 68bb ldr r3, [r7, #8]
8010e1a: 2b00 cmp r3, #0
8010e1c: d1ef bne.n 8010dfe <tcp_close_shutdown+0x12a>
8010e1e: 687b ldr r3, [r7, #4]
8010e20: 2200 movs r2, #0
8010e22: 60da str r2, [r3, #12]
}
tcp_free(pcb);
8010e24: 6878 ldr r0, [r7, #4]
8010e26: f7ff fea3 bl 8010b70 <tcp_free>
break;
8010e2a: e01a b.n 8010e62 <tcp_close_shutdown+0x18e>
case LISTEN:
tcp_listen_closed(pcb);
8010e2c: 6878 ldr r0, [r7, #4]
8010e2e: f7ff ff17 bl 8010c60 <tcp_listen_closed>
tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
8010e32: 6879 ldr r1, [r7, #4]
8010e34: 4815 ldr r0, [pc, #84] ; (8010e8c <tcp_close_shutdown+0x1b8>)
8010e36: f001 f89f bl 8011f78 <tcp_pcb_remove>
tcp_free_listen(pcb);
8010e3a: 6878 ldr r0, [r7, #4]
8010e3c: f7ff feb4 bl 8010ba8 <tcp_free_listen>
break;
8010e40: e00f b.n 8010e62 <tcp_close_shutdown+0x18e>
case SYN_SENT:
TCP_PCB_REMOVE_ACTIVE(pcb);
8010e42: 6879 ldr r1, [r7, #4]
8010e44: 480d ldr r0, [pc, #52] ; (8010e7c <tcp_close_shutdown+0x1a8>)
8010e46: f001 f897 bl 8011f78 <tcp_pcb_remove>
8010e4a: 4b0d ldr r3, [pc, #52] ; (8010e80 <tcp_close_shutdown+0x1ac>)
8010e4c: 2201 movs r2, #1
8010e4e: 701a strb r2, [r3, #0]
tcp_free(pcb);
8010e50: 6878 ldr r0, [r7, #4]
8010e52: f7ff fe8d bl 8010b70 <tcp_free>
MIB2_STATS_INC(mib2.tcpattemptfails);
break;
8010e56: e004 b.n 8010e62 <tcp_close_shutdown+0x18e>
default:
return tcp_close_shutdown_fin(pcb);
8010e58: 6878 ldr r0, [r7, #4]
8010e5a: f000 f819 bl 8010e90 <tcp_close_shutdown_fin>
8010e5e: 4603 mov r3, r0
8010e60: e000 b.n 8010e64 <tcp_close_shutdown+0x190>
}
return ERR_OK;
8010e62: 2300 movs r3, #0
}
8010e64: 4618 mov r0, r3
8010e66: 3710 adds r7, #16
8010e68: 46bd mov sp, r7
8010e6a: bdb0 pop {r4, r5, r7, pc}
8010e6c: 0801cb58 .word 0x0801cb58
8010e70: 0801cc2c .word 0x0801cc2c
8010e74: 0801cb9c .word 0x0801cb9c
8010e78: 0801cc4c .word 0x0801cc4c
8010e7c: 2000f5c0 .word 0x2000f5c0
8010e80: 2000f5bc .word 0x2000f5bc
8010e84: 2000f5d4 .word 0x2000f5d4
8010e88: 2000f5cc .word 0x2000f5cc
8010e8c: 2000f5c8 .word 0x2000f5c8
08010e90 <tcp_close_shutdown_fin>:
static err_t
tcp_close_shutdown_fin(struct tcp_pcb *pcb)
{
8010e90: b580 push {r7, lr}
8010e92: b084 sub sp, #16
8010e94: af00 add r7, sp, #0
8010e96: 6078 str r0, [r7, #4]
err_t err;
LWIP_ASSERT("pcb != NULL", pcb != NULL);
8010e98: 687b ldr r3, [r7, #4]
8010e9a: 2b00 cmp r3, #0
8010e9c: d106 bne.n 8010eac <tcp_close_shutdown_fin+0x1c>
8010e9e: 4b2c ldr r3, [pc, #176] ; (8010f50 <tcp_close_shutdown_fin+0xc0>)
8010ea0: f44f 72ce mov.w r2, #412 ; 0x19c
8010ea4: 492b ldr r1, [pc, #172] ; (8010f54 <tcp_close_shutdown_fin+0xc4>)
8010ea6: 482c ldr r0, [pc, #176] ; (8010f58 <tcp_close_shutdown_fin+0xc8>)
8010ea8: f00a f8bc bl 801b024 <iprintf>
switch (pcb->state) {
8010eac: 687b ldr r3, [r7, #4]
8010eae: 7d1b ldrb r3, [r3, #20]
8010eb0: 2b04 cmp r3, #4
8010eb2: d010 beq.n 8010ed6 <tcp_close_shutdown_fin+0x46>
8010eb4: 2b07 cmp r3, #7
8010eb6: d01b beq.n 8010ef0 <tcp_close_shutdown_fin+0x60>
8010eb8: 2b03 cmp r3, #3
8010eba: d126 bne.n 8010f0a <tcp_close_shutdown_fin+0x7a>
case SYN_RCVD:
err = tcp_send_fin(pcb);
8010ebc: 6878 ldr r0, [r7, #4]
8010ebe: f003 fedb bl 8014c78 <tcp_send_fin>
8010ec2: 4603 mov r3, r0
8010ec4: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010ec6: f997 300f ldrsb.w r3, [r7, #15]
8010eca: 2b00 cmp r3, #0
8010ecc: d11f bne.n 8010f0e <tcp_close_shutdown_fin+0x7e>
tcp_backlog_accepted(pcb);
MIB2_STATS_INC(mib2.tcpattemptfails);
pcb->state = FIN_WAIT_1;
8010ece: 687b ldr r3, [r7, #4]
8010ed0: 2205 movs r2, #5
8010ed2: 751a strb r2, [r3, #20]
}
break;
8010ed4: e01b b.n 8010f0e <tcp_close_shutdown_fin+0x7e>
case ESTABLISHED:
err = tcp_send_fin(pcb);
8010ed6: 6878 ldr r0, [r7, #4]
8010ed8: f003 fece bl 8014c78 <tcp_send_fin>
8010edc: 4603 mov r3, r0
8010ede: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010ee0: f997 300f ldrsb.w r3, [r7, #15]
8010ee4: 2b00 cmp r3, #0
8010ee6: d114 bne.n 8010f12 <tcp_close_shutdown_fin+0x82>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = FIN_WAIT_1;
8010ee8: 687b ldr r3, [r7, #4]
8010eea: 2205 movs r2, #5
8010eec: 751a strb r2, [r3, #20]
}
break;
8010eee: e010 b.n 8010f12 <tcp_close_shutdown_fin+0x82>
case CLOSE_WAIT:
err = tcp_send_fin(pcb);
8010ef0: 6878 ldr r0, [r7, #4]
8010ef2: f003 fec1 bl 8014c78 <tcp_send_fin>
8010ef6: 4603 mov r3, r0
8010ef8: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8010efa: f997 300f ldrsb.w r3, [r7, #15]
8010efe: 2b00 cmp r3, #0
8010f00: d109 bne.n 8010f16 <tcp_close_shutdown_fin+0x86>
MIB2_STATS_INC(mib2.tcpestabresets);
pcb->state = LAST_ACK;
8010f02: 687b ldr r3, [r7, #4]
8010f04: 2209 movs r2, #9
8010f06: 751a strb r2, [r3, #20]
}
break;
8010f08: e005 b.n 8010f16 <tcp_close_shutdown_fin+0x86>
default:
/* Has already been closed, do nothing. */
return ERR_OK;
8010f0a: 2300 movs r3, #0
8010f0c: e01c b.n 8010f48 <tcp_close_shutdown_fin+0xb8>
break;
8010f0e: bf00 nop
8010f10: e002 b.n 8010f18 <tcp_close_shutdown_fin+0x88>
break;
8010f12: bf00 nop
8010f14: e000 b.n 8010f18 <tcp_close_shutdown_fin+0x88>
break;
8010f16: bf00 nop
}
if (err == ERR_OK) {
8010f18: f997 300f ldrsb.w r3, [r7, #15]
8010f1c: 2b00 cmp r3, #0
8010f1e: d103 bne.n 8010f28 <tcp_close_shutdown_fin+0x98>
/* To ensure all data has been sent when tcp_close returns, we have
to make sure tcp_output doesn't fail.
Since we don't really have to ensure all data has been sent when tcp_close
returns (unsent data is sent from tcp timer functions, also), we don't care
for the return value of tcp_output for now. */
tcp_output(pcb);
8010f20: 6878 ldr r0, [r7, #4]
8010f22: f003 ffe7 bl 8014ef4 <tcp_output>
8010f26: e00d b.n 8010f44 <tcp_close_shutdown_fin+0xb4>
} else if (err == ERR_MEM) {
8010f28: f997 300f ldrsb.w r3, [r7, #15]
8010f2c: f1b3 3fff cmp.w r3, #4294967295
8010f30: d108 bne.n 8010f44 <tcp_close_shutdown_fin+0xb4>
/* Mark this pcb for closing. Closing is retried from tcp_tmr. */
tcp_set_flags(pcb, TF_CLOSEPEND);
8010f32: 687b ldr r3, [r7, #4]
8010f34: 8b5b ldrh r3, [r3, #26]
8010f36: f043 0308 orr.w r3, r3, #8
8010f3a: b29a uxth r2, r3
8010f3c: 687b ldr r3, [r7, #4]
8010f3e: 835a strh r2, [r3, #26]
/* We have to return ERR_OK from here to indicate to the callers that this
pcb should not be used any more as it will be freed soon via tcp_tmr.
This is OK here since sending FIN does not guarantee a time frime for
actually freeing the pcb, either (it is left in closure states for
remote ACK or timeout) */
return ERR_OK;
8010f40: 2300 movs r3, #0
8010f42: e001 b.n 8010f48 <tcp_close_shutdown_fin+0xb8>
}
return err;
8010f44: f997 300f ldrsb.w r3, [r7, #15]
}
8010f48: 4618 mov r0, r3
8010f4a: 3710 adds r7, #16
8010f4c: 46bd mov sp, r7
8010f4e: bd80 pop {r7, pc}
8010f50: 0801cb58 .word 0x0801cb58
8010f54: 0801cc08 .word 0x0801cc08
8010f58: 0801cb9c .word 0x0801cb9c
08010f5c <tcp_close>:
* @return ERR_OK if connection has been closed
* another err_t if closing failed and pcb is not freed
*/
err_t
tcp_close(struct tcp_pcb *pcb)
{
8010f5c: b580 push {r7, lr}
8010f5e: b082 sub sp, #8
8010f60: af00 add r7, sp, #0
8010f62: 6078 str r0, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
8010f64: 687b ldr r3, [r7, #4]
8010f66: 2b00 cmp r3, #0
8010f68: d109 bne.n 8010f7e <tcp_close+0x22>
8010f6a: 4b0f ldr r3, [pc, #60] ; (8010fa8 <tcp_close+0x4c>)
8010f6c: f44f 72f4 mov.w r2, #488 ; 0x1e8
8010f70: 490e ldr r1, [pc, #56] ; (8010fac <tcp_close+0x50>)
8010f72: 480f ldr r0, [pc, #60] ; (8010fb0 <tcp_close+0x54>)
8010f74: f00a f856 bl 801b024 <iprintf>
8010f78: f06f 030f mvn.w r3, #15
8010f7c: e00f b.n 8010f9e <tcp_close+0x42>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
tcp_debug_print_state(pcb->state);
if (pcb->state != LISTEN) {
8010f7e: 687b ldr r3, [r7, #4]
8010f80: 7d1b ldrb r3, [r3, #20]
8010f82: 2b01 cmp r3, #1
8010f84: d006 beq.n 8010f94 <tcp_close+0x38>
/* Set a flag not to receive any more data... */
tcp_set_flags(pcb, TF_RXCLOSED);
8010f86: 687b ldr r3, [r7, #4]
8010f88: 8b5b ldrh r3, [r3, #26]
8010f8a: f043 0310 orr.w r3, r3, #16
8010f8e: b29a uxth r2, r3
8010f90: 687b ldr r3, [r7, #4]
8010f92: 835a strh r2, [r3, #26]
}
/* ... and close */
return tcp_close_shutdown(pcb, 1);
8010f94: 2101 movs r1, #1
8010f96: 6878 ldr r0, [r7, #4]
8010f98: f7ff fe9c bl 8010cd4 <tcp_close_shutdown>
8010f9c: 4603 mov r3, r0
}
8010f9e: 4618 mov r0, r3
8010fa0: 3708 adds r7, #8
8010fa2: 46bd mov sp, r7
8010fa4: bd80 pop {r7, pc}
8010fa6: bf00 nop
8010fa8: 0801cb58 .word 0x0801cb58
8010fac: 0801cc68 .word 0x0801cc68
8010fb0: 0801cb9c .word 0x0801cb9c
08010fb4 <tcp_abandon>:
* @param pcb the tcp_pcb to abort
* @param reset boolean to indicate whether a reset should be sent
*/
void
tcp_abandon(struct tcp_pcb *pcb, int reset)
{
8010fb4: b580 push {r7, lr}
8010fb6: b08e sub sp, #56 ; 0x38
8010fb8: af04 add r7, sp, #16
8010fba: 6078 str r0, [r7, #4]
8010fbc: 6039 str r1, [r7, #0]
#endif /* LWIP_CALLBACK_API */
void *errf_arg;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
8010fbe: 687b ldr r3, [r7, #4]
8010fc0: 2b00 cmp r3, #0
8010fc2: d107 bne.n 8010fd4 <tcp_abandon+0x20>
8010fc4: 4b52 ldr r3, [pc, #328] ; (8011110 <tcp_abandon+0x15c>)
8010fc6: f240 223d movw r2, #573 ; 0x23d
8010fca: 4952 ldr r1, [pc, #328] ; (8011114 <tcp_abandon+0x160>)
8010fcc: 4852 ldr r0, [pc, #328] ; (8011118 <tcp_abandon+0x164>)
8010fce: f00a f829 bl 801b024 <iprintf>
8010fd2: e099 b.n 8011108 <tcp_abandon+0x154>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
8010fd4: 687b ldr r3, [r7, #4]
8010fd6: 7d1b ldrb r3, [r3, #20]
8010fd8: 2b01 cmp r3, #1
8010fda: d106 bne.n 8010fea <tcp_abandon+0x36>
8010fdc: 4b4c ldr r3, [pc, #304] ; (8011110 <tcp_abandon+0x15c>)
8010fde: f240 2241 movw r2, #577 ; 0x241
8010fe2: 494e ldr r1, [pc, #312] ; (801111c <tcp_abandon+0x168>)
8010fe4: 484c ldr r0, [pc, #304] ; (8011118 <tcp_abandon+0x164>)
8010fe6: f00a f81d bl 801b024 <iprintf>
pcb->state != LISTEN);
/* Figure out on which TCP PCB list we are, and remove us. If we
are in an active state, call the receive function associated with
the PCB with a NULL argument, and send an RST to the remote end. */
if (pcb->state == TIME_WAIT) {
8010fea: 687b ldr r3, [r7, #4]
8010fec: 7d1b ldrb r3, [r3, #20]
8010fee: 2b0a cmp r3, #10
8010ff0: d107 bne.n 8011002 <tcp_abandon+0x4e>
tcp_pcb_remove(&tcp_tw_pcbs, pcb);
8010ff2: 6879 ldr r1, [r7, #4]
8010ff4: 484a ldr r0, [pc, #296] ; (8011120 <tcp_abandon+0x16c>)
8010ff6: f000 ffbf bl 8011f78 <tcp_pcb_remove>
tcp_free(pcb);
8010ffa: 6878 ldr r0, [r7, #4]
8010ffc: f7ff fdb8 bl 8010b70 <tcp_free>
8011000: e082 b.n 8011108 <tcp_abandon+0x154>
} else {
int send_rst = 0;
8011002: 2300 movs r3, #0
8011004: 627b str r3, [r7, #36] ; 0x24
u16_t local_port = 0;
8011006: 2300 movs r3, #0
8011008: 847b strh r3, [r7, #34] ; 0x22
enum tcp_state last_state;
seqno = pcb->snd_nxt;
801100a: 687b ldr r3, [r7, #4]
801100c: 6d1b ldr r3, [r3, #80] ; 0x50
801100e: 61bb str r3, [r7, #24]
ackno = pcb->rcv_nxt;
8011010: 687b ldr r3, [r7, #4]
8011012: 6a5b ldr r3, [r3, #36] ; 0x24
8011014: 617b str r3, [r7, #20]
#if LWIP_CALLBACK_API
errf = pcb->errf;
8011016: 687b ldr r3, [r7, #4]
8011018: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
801101c: 613b str r3, [r7, #16]
#endif /* LWIP_CALLBACK_API */
errf_arg = pcb->callback_arg;
801101e: 687b ldr r3, [r7, #4]
8011020: 691b ldr r3, [r3, #16]
8011022: 60fb str r3, [r7, #12]
if (pcb->state == CLOSED) {
8011024: 687b ldr r3, [r7, #4]
8011026: 7d1b ldrb r3, [r3, #20]
8011028: 2b00 cmp r3, #0
801102a: d126 bne.n 801107a <tcp_abandon+0xc6>
if (pcb->local_port != 0) {
801102c: 687b ldr r3, [r7, #4]
801102e: 8adb ldrh r3, [r3, #22]
8011030: 2b00 cmp r3, #0
8011032: d02e beq.n 8011092 <tcp_abandon+0xde>
/* bound, not yet opened */
TCP_RMV(&tcp_bound_pcbs, pcb);
8011034: 4b3b ldr r3, [pc, #236] ; (8011124 <tcp_abandon+0x170>)
8011036: 681b ldr r3, [r3, #0]
8011038: 687a ldr r2, [r7, #4]
801103a: 429a cmp r2, r3
801103c: d105 bne.n 801104a <tcp_abandon+0x96>
801103e: 4b39 ldr r3, [pc, #228] ; (8011124 <tcp_abandon+0x170>)
8011040: 681b ldr r3, [r3, #0]
8011042: 68db ldr r3, [r3, #12]
8011044: 4a37 ldr r2, [pc, #220] ; (8011124 <tcp_abandon+0x170>)
8011046: 6013 str r3, [r2, #0]
8011048: e013 b.n 8011072 <tcp_abandon+0xbe>
801104a: 4b36 ldr r3, [pc, #216] ; (8011124 <tcp_abandon+0x170>)
801104c: 681b ldr r3, [r3, #0]
801104e: 61fb str r3, [r7, #28]
8011050: e00c b.n 801106c <tcp_abandon+0xb8>
8011052: 69fb ldr r3, [r7, #28]
8011054: 68db ldr r3, [r3, #12]
8011056: 687a ldr r2, [r7, #4]
8011058: 429a cmp r2, r3
801105a: d104 bne.n 8011066 <tcp_abandon+0xb2>
801105c: 687b ldr r3, [r7, #4]
801105e: 68da ldr r2, [r3, #12]
8011060: 69fb ldr r3, [r7, #28]
8011062: 60da str r2, [r3, #12]
8011064: e005 b.n 8011072 <tcp_abandon+0xbe>
8011066: 69fb ldr r3, [r7, #28]
8011068: 68db ldr r3, [r3, #12]
801106a: 61fb str r3, [r7, #28]
801106c: 69fb ldr r3, [r7, #28]
801106e: 2b00 cmp r3, #0
8011070: d1ef bne.n 8011052 <tcp_abandon+0x9e>
8011072: 687b ldr r3, [r7, #4]
8011074: 2200 movs r2, #0
8011076: 60da str r2, [r3, #12]
8011078: e00b b.n 8011092 <tcp_abandon+0xde>
}
} else {
send_rst = reset;
801107a: 683b ldr r3, [r7, #0]
801107c: 627b str r3, [r7, #36] ; 0x24
local_port = pcb->local_port;
801107e: 687b ldr r3, [r7, #4]
8011080: 8adb ldrh r3, [r3, #22]
8011082: 847b strh r3, [r7, #34] ; 0x22
TCP_PCB_REMOVE_ACTIVE(pcb);
8011084: 6879 ldr r1, [r7, #4]
8011086: 4828 ldr r0, [pc, #160] ; (8011128 <tcp_abandon+0x174>)
8011088: f000 ff76 bl 8011f78 <tcp_pcb_remove>
801108c: 4b27 ldr r3, [pc, #156] ; (801112c <tcp_abandon+0x178>)
801108e: 2201 movs r2, #1
8011090: 701a strb r2, [r3, #0]
}
if (pcb->unacked != NULL) {
8011092: 687b ldr r3, [r7, #4]
8011094: 6f1b ldr r3, [r3, #112] ; 0x70
8011096: 2b00 cmp r3, #0
8011098: d004 beq.n 80110a4 <tcp_abandon+0xf0>
tcp_segs_free(pcb->unacked);
801109a: 687b ldr r3, [r7, #4]
801109c: 6f1b ldr r3, [r3, #112] ; 0x70
801109e: 4618 mov r0, r3
80110a0: f000 fd1a bl 8011ad8 <tcp_segs_free>
}
if (pcb->unsent != NULL) {
80110a4: 687b ldr r3, [r7, #4]
80110a6: 6edb ldr r3, [r3, #108] ; 0x6c
80110a8: 2b00 cmp r3, #0
80110aa: d004 beq.n 80110b6 <tcp_abandon+0x102>
tcp_segs_free(pcb->unsent);
80110ac: 687b ldr r3, [r7, #4]
80110ae: 6edb ldr r3, [r3, #108] ; 0x6c
80110b0: 4618 mov r0, r3
80110b2: f000 fd11 bl 8011ad8 <tcp_segs_free>
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
80110b6: 687b ldr r3, [r7, #4]
80110b8: 6f5b ldr r3, [r3, #116] ; 0x74
80110ba: 2b00 cmp r3, #0
80110bc: d004 beq.n 80110c8 <tcp_abandon+0x114>
tcp_segs_free(pcb->ooseq);
80110be: 687b ldr r3, [r7, #4]
80110c0: 6f5b ldr r3, [r3, #116] ; 0x74
80110c2: 4618 mov r0, r3
80110c4: f000 fd08 bl 8011ad8 <tcp_segs_free>
}
#endif /* TCP_QUEUE_OOSEQ */
tcp_backlog_accepted(pcb);
if (send_rst) {
80110c8: 6a7b ldr r3, [r7, #36] ; 0x24
80110ca: 2b00 cmp r3, #0
80110cc: d00e beq.n 80110ec <tcp_abandon+0x138>
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
80110ce: 6879 ldr r1, [r7, #4]
80110d0: 687b ldr r3, [r7, #4]
80110d2: 3304 adds r3, #4
80110d4: 687a ldr r2, [r7, #4]
80110d6: 8b12 ldrh r2, [r2, #24]
80110d8: 9202 str r2, [sp, #8]
80110da: 8c7a ldrh r2, [r7, #34] ; 0x22
80110dc: 9201 str r2, [sp, #4]
80110de: 9300 str r3, [sp, #0]
80110e0: 460b mov r3, r1
80110e2: 697a ldr r2, [r7, #20]
80110e4: 69b9 ldr r1, [r7, #24]
80110e6: 6878 ldr r0, [r7, #4]
80110e8: f004 fcca bl 8015a80 <tcp_rst>
}
last_state = pcb->state;
80110ec: 687b ldr r3, [r7, #4]
80110ee: 7d1b ldrb r3, [r3, #20]
80110f0: 72fb strb r3, [r7, #11]
tcp_free(pcb);
80110f2: 6878 ldr r0, [r7, #4]
80110f4: f7ff fd3c bl 8010b70 <tcp_free>
TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
80110f8: 693b ldr r3, [r7, #16]
80110fa: 2b00 cmp r3, #0
80110fc: d004 beq.n 8011108 <tcp_abandon+0x154>
80110fe: 693b ldr r3, [r7, #16]
8011100: f06f 010c mvn.w r1, #12
8011104: 68f8 ldr r0, [r7, #12]
8011106: 4798 blx r3
}
}
8011108: 3728 adds r7, #40 ; 0x28
801110a: 46bd mov sp, r7
801110c: bd80 pop {r7, pc}
801110e: bf00 nop
8011110: 0801cb58 .word 0x0801cb58
8011114: 0801cc9c .word 0x0801cc9c
8011118: 0801cb9c .word 0x0801cb9c
801111c: 0801ccb8 .word 0x0801ccb8
8011120: 2000f5d0 .word 0x2000f5d0
8011124: 2000f5cc .word 0x2000f5cc
8011128: 2000f5c0 .word 0x2000f5c0
801112c: 2000f5bc .word 0x2000f5bc
08011130 <tcp_abort>:
*
* @param pcb the tcp pcb to abort
*/
void
tcp_abort(struct tcp_pcb *pcb)
{
8011130: b580 push {r7, lr}
8011132: b082 sub sp, #8
8011134: af00 add r7, sp, #0
8011136: 6078 str r0, [r7, #4]
tcp_abandon(pcb, 1);
8011138: 2101 movs r1, #1
801113a: 6878 ldr r0, [r7, #4]
801113c: f7ff ff3a bl 8010fb4 <tcp_abandon>
}
8011140: bf00 nop
8011142: 3708 adds r7, #8
8011144: 46bd mov sp, r7
8011146: bd80 pop {r7, pc}
08011148 <tcp_update_rcv_ann_wnd>:
* Returns how much extra window would be advertised if we sent an
* update now.
*/
u32_t
tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
{
8011148: b580 push {r7, lr}
801114a: b084 sub sp, #16
801114c: af00 add r7, sp, #0
801114e: 6078 str r0, [r7, #4]
u32_t new_right_edge;
LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
8011150: 687b ldr r3, [r7, #4]
8011152: 2b00 cmp r3, #0
8011154: d106 bne.n 8011164 <tcp_update_rcv_ann_wnd+0x1c>
8011156: 4b25 ldr r3, [pc, #148] ; (80111ec <tcp_update_rcv_ann_wnd+0xa4>)
8011158: f240 32a6 movw r2, #934 ; 0x3a6
801115c: 4924 ldr r1, [pc, #144] ; (80111f0 <tcp_update_rcv_ann_wnd+0xa8>)
801115e: 4825 ldr r0, [pc, #148] ; (80111f4 <tcp_update_rcv_ann_wnd+0xac>)
8011160: f009 ff60 bl 801b024 <iprintf>
new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
8011164: 687b ldr r3, [r7, #4]
8011166: 6a5b ldr r3, [r3, #36] ; 0x24
8011168: 687a ldr r2, [r7, #4]
801116a: 8d12 ldrh r2, [r2, #40] ; 0x28
801116c: 4413 add r3, r2
801116e: 60fb str r3, [r7, #12]
if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
8011170: 687b ldr r3, [r7, #4]
8011172: 6adb ldr r3, [r3, #44] ; 0x2c
8011174: 687a ldr r2, [r7, #4]
8011176: 8e52 ldrh r2, [r2, #50] ; 0x32
8011178: f5b2 6f86 cmp.w r2, #1072 ; 0x430
801117c: bf28 it cs
801117e: f44f 6286 movcs.w r2, #1072 ; 0x430
8011182: b292 uxth r2, r2
8011184: 4413 add r3, r2
8011186: 68fa ldr r2, [r7, #12]
8011188: 1ad3 subs r3, r2, r3
801118a: 2b00 cmp r3, #0
801118c: db08 blt.n 80111a0 <tcp_update_rcv_ann_wnd+0x58>
/* we can advertise more window */
pcb->rcv_ann_wnd = pcb->rcv_wnd;
801118e: 687b ldr r3, [r7, #4]
8011190: 8d1a ldrh r2, [r3, #40] ; 0x28
8011192: 687b ldr r3, [r7, #4]
8011194: 855a strh r2, [r3, #42] ; 0x2a
return new_right_edge - pcb->rcv_ann_right_edge;
8011196: 687b ldr r3, [r7, #4]
8011198: 6adb ldr r3, [r3, #44] ; 0x2c
801119a: 68fa ldr r2, [r7, #12]
801119c: 1ad3 subs r3, r2, r3
801119e: e020 b.n 80111e2 <tcp_update_rcv_ann_wnd+0x9a>
} else {
if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
80111a0: 687b ldr r3, [r7, #4]
80111a2: 6a5a ldr r2, [r3, #36] ; 0x24
80111a4: 687b ldr r3, [r7, #4]
80111a6: 6adb ldr r3, [r3, #44] ; 0x2c
80111a8: 1ad3 subs r3, r2, r3
80111aa: 2b00 cmp r3, #0
80111ac: dd03 ble.n 80111b6 <tcp_update_rcv_ann_wnd+0x6e>
/* Can happen due to other end sending out of advertised window,
* but within actual available (but not yet advertised) window */
pcb->rcv_ann_wnd = 0;
80111ae: 687b ldr r3, [r7, #4]
80111b0: 2200 movs r2, #0
80111b2: 855a strh r2, [r3, #42] ; 0x2a
80111b4: e014 b.n 80111e0 <tcp_update_rcv_ann_wnd+0x98>
} else {
/* keep the right edge of window constant */
u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
80111b6: 687b ldr r3, [r7, #4]
80111b8: 6ada ldr r2, [r3, #44] ; 0x2c
80111ba: 687b ldr r3, [r7, #4]
80111bc: 6a5b ldr r3, [r3, #36] ; 0x24
80111be: 1ad3 subs r3, r2, r3
80111c0: 60bb str r3, [r7, #8]
#if !LWIP_WND_SCALE
LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
80111c2: 68bb ldr r3, [r7, #8]
80111c4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80111c8: d306 bcc.n 80111d8 <tcp_update_rcv_ann_wnd+0x90>
80111ca: 4b08 ldr r3, [pc, #32] ; (80111ec <tcp_update_rcv_ann_wnd+0xa4>)
80111cc: f240 32b6 movw r2, #950 ; 0x3b6
80111d0: 4909 ldr r1, [pc, #36] ; (80111f8 <tcp_update_rcv_ann_wnd+0xb0>)
80111d2: 4808 ldr r0, [pc, #32] ; (80111f4 <tcp_update_rcv_ann_wnd+0xac>)
80111d4: f009 ff26 bl 801b024 <iprintf>
#endif
pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
80111d8: 68bb ldr r3, [r7, #8]
80111da: b29a uxth r2, r3
80111dc: 687b ldr r3, [r7, #4]
80111de: 855a strh r2, [r3, #42] ; 0x2a
}
return 0;
80111e0: 2300 movs r3, #0
}
}
80111e2: 4618 mov r0, r3
80111e4: 3710 adds r7, #16
80111e6: 46bd mov sp, r7
80111e8: bd80 pop {r7, pc}
80111ea: bf00 nop
80111ec: 0801cb58 .word 0x0801cb58
80111f0: 0801cdb4 .word 0x0801cdb4
80111f4: 0801cb9c .word 0x0801cb9c
80111f8: 0801cdd8 .word 0x0801cdd8
080111fc <tcp_recved>:
* @param pcb the tcp_pcb for which data is read
* @param len the amount of bytes that have been read by the application
*/
void
tcp_recved(struct tcp_pcb *pcb, u16_t len)
{
80111fc: b580 push {r7, lr}
80111fe: b084 sub sp, #16
8011200: af00 add r7, sp, #0
8011202: 6078 str r0, [r7, #4]
8011204: 460b mov r3, r1
8011206: 807b strh r3, [r7, #2]
u32_t wnd_inflation;
tcpwnd_size_t rcv_wnd;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
8011208: 687b ldr r3, [r7, #4]
801120a: 2b00 cmp r3, #0
801120c: d107 bne.n 801121e <tcp_recved+0x22>
801120e: 4b1f ldr r3, [pc, #124] ; (801128c <tcp_recved+0x90>)
8011210: f240 32cf movw r2, #975 ; 0x3cf
8011214: 491e ldr r1, [pc, #120] ; (8011290 <tcp_recved+0x94>)
8011216: 481f ldr r0, [pc, #124] ; (8011294 <tcp_recved+0x98>)
8011218: f009 ff04 bl 801b024 <iprintf>
801121c: e032 b.n 8011284 <tcp_recved+0x88>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
801121e: 687b ldr r3, [r7, #4]
8011220: 7d1b ldrb r3, [r3, #20]
8011222: 2b01 cmp r3, #1
8011224: d106 bne.n 8011234 <tcp_recved+0x38>
8011226: 4b19 ldr r3, [pc, #100] ; (801128c <tcp_recved+0x90>)
8011228: f240 32d3 movw r2, #979 ; 0x3d3
801122c: 491a ldr r1, [pc, #104] ; (8011298 <tcp_recved+0x9c>)
801122e: 4819 ldr r0, [pc, #100] ; (8011294 <tcp_recved+0x98>)
8011230: f009 fef8 bl 801b024 <iprintf>
pcb->state != LISTEN);
rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
8011234: 687b ldr r3, [r7, #4]
8011236: 8d1a ldrh r2, [r3, #40] ; 0x28
8011238: 887b ldrh r3, [r7, #2]
801123a: 4413 add r3, r2
801123c: 81fb strh r3, [r7, #14]
if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
801123e: 89fb ldrh r3, [r7, #14]
8011240: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011244: d804 bhi.n 8011250 <tcp_recved+0x54>
8011246: 687b ldr r3, [r7, #4]
8011248: 8d1b ldrh r3, [r3, #40] ; 0x28
801124a: 89fa ldrh r2, [r7, #14]
801124c: 429a cmp r2, r3
801124e: d204 bcs.n 801125a <tcp_recved+0x5e>
/* window got too big or tcpwnd_size_t overflow */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
pcb->rcv_wnd = TCP_WND_MAX(pcb);
8011250: 687b ldr r3, [r7, #4]
8011252: f44f 6206 mov.w r2, #2144 ; 0x860
8011256: 851a strh r2, [r3, #40] ; 0x28
8011258: e002 b.n 8011260 <tcp_recved+0x64>
} else {
pcb->rcv_wnd = rcv_wnd;
801125a: 687b ldr r3, [r7, #4]
801125c: 89fa ldrh r2, [r7, #14]
801125e: 851a strh r2, [r3, #40] ; 0x28
}
wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
8011260: 6878 ldr r0, [r7, #4]
8011262: f7ff ff71 bl 8011148 <tcp_update_rcv_ann_wnd>
8011266: 60b8 str r0, [r7, #8]
/* If the change in the right edge of window is significant (default
* watermark is TCP_WND/4), then send an explicit update now.
* Otherwise wait for a packet to be sent in the normal course of
* events (or more window to be available later) */
if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
8011268: 68bb ldr r3, [r7, #8]
801126a: f5b3 7f06 cmp.w r3, #536 ; 0x218
801126e: d309 bcc.n 8011284 <tcp_recved+0x88>
tcp_ack_now(pcb);
8011270: 687b ldr r3, [r7, #4]
8011272: 8b5b ldrh r3, [r3, #26]
8011274: f043 0302 orr.w r3, r3, #2
8011278: b29a uxth r2, r3
801127a: 687b ldr r3, [r7, #4]
801127c: 835a strh r2, [r3, #26]
tcp_output(pcb);
801127e: 6878 ldr r0, [r7, #4]
8011280: f003 fe38 bl 8014ef4 <tcp_output>
}
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
}
8011284: 3710 adds r7, #16
8011286: 46bd mov sp, r7
8011288: bd80 pop {r7, pc}
801128a: bf00 nop
801128c: 0801cb58 .word 0x0801cb58
8011290: 0801cdf4 .word 0x0801cdf4
8011294: 0801cb9c .word 0x0801cb9c
8011298: 0801ce0c .word 0x0801ce0c
0801129c <tcp_slowtmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_slowtmr(void)
{
801129c: b5b0 push {r4, r5, r7, lr}
801129e: b090 sub sp, #64 ; 0x40
80112a0: af04 add r7, sp, #16
tcpwnd_size_t eff_wnd;
u8_t pcb_remove; /* flag if a PCB should be removed */
u8_t pcb_reset; /* flag if a RST should be sent when removing */
err_t err;
err = ERR_OK;
80112a2: 2300 movs r3, #0
80112a4: f887 3025 strb.w r3, [r7, #37] ; 0x25
++tcp_ticks;
80112a8: 4b94 ldr r3, [pc, #592] ; (80114fc <tcp_slowtmr+0x260>)
80112aa: 681b ldr r3, [r3, #0]
80112ac: 3301 adds r3, #1
80112ae: 4a93 ldr r2, [pc, #588] ; (80114fc <tcp_slowtmr+0x260>)
80112b0: 6013 str r3, [r2, #0]
++tcp_timer_ctr;
80112b2: 4b93 ldr r3, [pc, #588] ; (8011500 <tcp_slowtmr+0x264>)
80112b4: 781b ldrb r3, [r3, #0]
80112b6: 3301 adds r3, #1
80112b8: b2da uxtb r2, r3
80112ba: 4b91 ldr r3, [pc, #580] ; (8011500 <tcp_slowtmr+0x264>)
80112bc: 701a strb r2, [r3, #0]
tcp_slowtmr_start:
/* Steps through all of the active PCBs. */
prev = NULL;
80112be: 2300 movs r3, #0
80112c0: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_active_pcbs;
80112c2: 4b90 ldr r3, [pc, #576] ; (8011504 <tcp_slowtmr+0x268>)
80112c4: 681b ldr r3, [r3, #0]
80112c6: 62fb str r3, [r7, #44] ; 0x2c
if (pcb == NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
}
while (pcb != NULL) {
80112c8: e29d b.n 8011806 <tcp_slowtmr+0x56a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
80112ca: 6afb ldr r3, [r7, #44] ; 0x2c
80112cc: 7d1b ldrb r3, [r3, #20]
80112ce: 2b00 cmp r3, #0
80112d0: d106 bne.n 80112e0 <tcp_slowtmr+0x44>
80112d2: 4b8d ldr r3, [pc, #564] ; (8011508 <tcp_slowtmr+0x26c>)
80112d4: f240 42be movw r2, #1214 ; 0x4be
80112d8: 498c ldr r1, [pc, #560] ; (801150c <tcp_slowtmr+0x270>)
80112da: 488d ldr r0, [pc, #564] ; (8011510 <tcp_slowtmr+0x274>)
80112dc: f009 fea2 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
80112e0: 6afb ldr r3, [r7, #44] ; 0x2c
80112e2: 7d1b ldrb r3, [r3, #20]
80112e4: 2b01 cmp r3, #1
80112e6: d106 bne.n 80112f6 <tcp_slowtmr+0x5a>
80112e8: 4b87 ldr r3, [pc, #540] ; (8011508 <tcp_slowtmr+0x26c>)
80112ea: f240 42bf movw r2, #1215 ; 0x4bf
80112ee: 4989 ldr r1, [pc, #548] ; (8011514 <tcp_slowtmr+0x278>)
80112f0: 4887 ldr r0, [pc, #540] ; (8011510 <tcp_slowtmr+0x274>)
80112f2: f009 fe97 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
80112f6: 6afb ldr r3, [r7, #44] ; 0x2c
80112f8: 7d1b ldrb r3, [r3, #20]
80112fa: 2b0a cmp r3, #10
80112fc: d106 bne.n 801130c <tcp_slowtmr+0x70>
80112fe: 4b82 ldr r3, [pc, #520] ; (8011508 <tcp_slowtmr+0x26c>)
8011300: f44f 6298 mov.w r2, #1216 ; 0x4c0
8011304: 4984 ldr r1, [pc, #528] ; (8011518 <tcp_slowtmr+0x27c>)
8011306: 4882 ldr r0, [pc, #520] ; (8011510 <tcp_slowtmr+0x274>)
8011308: f009 fe8c bl 801b024 <iprintf>
if (pcb->last_timer == tcp_timer_ctr) {
801130c: 6afb ldr r3, [r7, #44] ; 0x2c
801130e: 7f9a ldrb r2, [r3, #30]
8011310: 4b7b ldr r3, [pc, #492] ; (8011500 <tcp_slowtmr+0x264>)
8011312: 781b ldrb r3, [r3, #0]
8011314: 429a cmp r2, r3
8011316: d105 bne.n 8011324 <tcp_slowtmr+0x88>
/* skip this pcb, we have already processed it */
prev = pcb;
8011318: 6afb ldr r3, [r7, #44] ; 0x2c
801131a: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
801131c: 6afb ldr r3, [r7, #44] ; 0x2c
801131e: 68db ldr r3, [r3, #12]
8011320: 62fb str r3, [r7, #44] ; 0x2c
continue;
8011322: e270 b.n 8011806 <tcp_slowtmr+0x56a>
}
pcb->last_timer = tcp_timer_ctr;
8011324: 4b76 ldr r3, [pc, #472] ; (8011500 <tcp_slowtmr+0x264>)
8011326: 781a ldrb r2, [r3, #0]
8011328: 6afb ldr r3, [r7, #44] ; 0x2c
801132a: 779a strb r2, [r3, #30]
pcb_remove = 0;
801132c: 2300 movs r3, #0
801132e: f887 3027 strb.w r3, [r7, #39] ; 0x27
pcb_reset = 0;
8011332: 2300 movs r3, #0
8011334: f887 3026 strb.w r3, [r7, #38] ; 0x26
if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
8011338: 6afb ldr r3, [r7, #44] ; 0x2c
801133a: 7d1b ldrb r3, [r3, #20]
801133c: 2b02 cmp r3, #2
801133e: d10a bne.n 8011356 <tcp_slowtmr+0xba>
8011340: 6afb ldr r3, [r7, #44] ; 0x2c
8011342: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8011346: 2b05 cmp r3, #5
8011348: d905 bls.n 8011356 <tcp_slowtmr+0xba>
++pcb_remove;
801134a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801134e: 3301 adds r3, #1
8011350: f887 3027 strb.w r3, [r7, #39] ; 0x27
8011354: e11e b.n 8011594 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
} else if (pcb->nrtx >= TCP_MAXRTX) {
8011356: 6afb ldr r3, [r7, #44] ; 0x2c
8011358: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801135c: 2b0b cmp r3, #11
801135e: d905 bls.n 801136c <tcp_slowtmr+0xd0>
++pcb_remove;
8011360: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011364: 3301 adds r3, #1
8011366: f887 3027 strb.w r3, [r7, #39] ; 0x27
801136a: e113 b.n 8011594 <tcp_slowtmr+0x2f8>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
} else {
if (pcb->persist_backoff > 0) {
801136c: 6afb ldr r3, [r7, #44] ; 0x2c
801136e: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011372: 2b00 cmp r3, #0
8011374: d075 beq.n 8011462 <tcp_slowtmr+0x1c6>
LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
8011376: 6afb ldr r3, [r7, #44] ; 0x2c
8011378: 6f1b ldr r3, [r3, #112] ; 0x70
801137a: 2b00 cmp r3, #0
801137c: d006 beq.n 801138c <tcp_slowtmr+0xf0>
801137e: 4b62 ldr r3, [pc, #392] ; (8011508 <tcp_slowtmr+0x26c>)
8011380: f240 42d4 movw r2, #1236 ; 0x4d4
8011384: 4965 ldr r1, [pc, #404] ; (801151c <tcp_slowtmr+0x280>)
8011386: 4862 ldr r0, [pc, #392] ; (8011510 <tcp_slowtmr+0x274>)
8011388: f009 fe4c bl 801b024 <iprintf>
LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
801138c: 6afb ldr r3, [r7, #44] ; 0x2c
801138e: 6edb ldr r3, [r3, #108] ; 0x6c
8011390: 2b00 cmp r3, #0
8011392: d106 bne.n 80113a2 <tcp_slowtmr+0x106>
8011394: 4b5c ldr r3, [pc, #368] ; (8011508 <tcp_slowtmr+0x26c>)
8011396: f240 42d5 movw r2, #1237 ; 0x4d5
801139a: 4961 ldr r1, [pc, #388] ; (8011520 <tcp_slowtmr+0x284>)
801139c: 485c ldr r0, [pc, #368] ; (8011510 <tcp_slowtmr+0x274>)
801139e: f009 fe41 bl 801b024 <iprintf>
if (pcb->persist_probe >= TCP_MAXRTX) {
80113a2: 6afb ldr r3, [r7, #44] ; 0x2c
80113a4: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
80113a8: 2b0b cmp r3, #11
80113aa: d905 bls.n 80113b8 <tcp_slowtmr+0x11c>
++pcb_remove; /* max probes reached */
80113ac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80113b0: 3301 adds r3, #1
80113b2: f887 3027 strb.w r3, [r7, #39] ; 0x27
80113b6: e0ed b.n 8011594 <tcp_slowtmr+0x2f8>
} else {
u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
80113b8: 6afb ldr r3, [r7, #44] ; 0x2c
80113ba: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
80113be: 3b01 subs r3, #1
80113c0: 4a58 ldr r2, [pc, #352] ; (8011524 <tcp_slowtmr+0x288>)
80113c2: 5cd3 ldrb r3, [r2, r3]
80113c4: 747b strb r3, [r7, #17]
if (pcb->persist_cnt < backoff_cnt) {
80113c6: 6afb ldr r3, [r7, #44] ; 0x2c
80113c8: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113cc: 7c7a ldrb r2, [r7, #17]
80113ce: 429a cmp r2, r3
80113d0: d907 bls.n 80113e2 <tcp_slowtmr+0x146>
pcb->persist_cnt++;
80113d2: 6afb ldr r3, [r7, #44] ; 0x2c
80113d4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113d8: 3301 adds r3, #1
80113da: b2da uxtb r2, r3
80113dc: 6afb ldr r3, [r7, #44] ; 0x2c
80113de: f883 2098 strb.w r2, [r3, #152] ; 0x98
}
if (pcb->persist_cnt >= backoff_cnt) {
80113e2: 6afb ldr r3, [r7, #44] ; 0x2c
80113e4: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
80113e8: 7c7a ldrb r2, [r7, #17]
80113ea: 429a cmp r2, r3
80113ec: f200 80d2 bhi.w 8011594 <tcp_slowtmr+0x2f8>
int next_slot = 1; /* increment timer to next slot */
80113f0: 2301 movs r3, #1
80113f2: 623b str r3, [r7, #32]
/* If snd_wnd is zero, send 1 byte probes */
if (pcb->snd_wnd == 0) {
80113f4: 6afb ldr r3, [r7, #44] ; 0x2c
80113f6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
80113fa: 2b00 cmp r3, #0
80113fc: d108 bne.n 8011410 <tcp_slowtmr+0x174>
if (tcp_zero_window_probe(pcb) != ERR_OK) {
80113fe: 6af8 ldr r0, [r7, #44] ; 0x2c
8011400: f004 fc32 bl 8015c68 <tcp_zero_window_probe>
8011404: 4603 mov r3, r0
8011406: 2b00 cmp r3, #0
8011408: d014 beq.n 8011434 <tcp_slowtmr+0x198>
next_slot = 0; /* try probe again with current slot */
801140a: 2300 movs r3, #0
801140c: 623b str r3, [r7, #32]
801140e: e011 b.n 8011434 <tcp_slowtmr+0x198>
}
/* snd_wnd not fully closed, split unsent head and fill window */
} else {
if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
8011410: 6afb ldr r3, [r7, #44] ; 0x2c
8011412: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8011416: 4619 mov r1, r3
8011418: 6af8 ldr r0, [r7, #44] ; 0x2c
801141a: f003 fae5 bl 80149e8 <tcp_split_unsent_seg>
801141e: 4603 mov r3, r0
8011420: 2b00 cmp r3, #0
8011422: d107 bne.n 8011434 <tcp_slowtmr+0x198>
if (tcp_output(pcb) == ERR_OK) {
8011424: 6af8 ldr r0, [r7, #44] ; 0x2c
8011426: f003 fd65 bl 8014ef4 <tcp_output>
801142a: 4603 mov r3, r0
801142c: 2b00 cmp r3, #0
801142e: d101 bne.n 8011434 <tcp_slowtmr+0x198>
/* sending will cancel persist timer, else retry with current slot */
next_slot = 0;
8011430: 2300 movs r3, #0
8011432: 623b str r3, [r7, #32]
}
}
}
if (next_slot) {
8011434: 6a3b ldr r3, [r7, #32]
8011436: 2b00 cmp r3, #0
8011438: f000 80ac beq.w 8011594 <tcp_slowtmr+0x2f8>
pcb->persist_cnt = 0;
801143c: 6afb ldr r3, [r7, #44] ; 0x2c
801143e: 2200 movs r2, #0
8011440: f883 2098 strb.w r2, [r3, #152] ; 0x98
if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
8011444: 6afb ldr r3, [r7, #44] ; 0x2c
8011446: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
801144a: 2b06 cmp r3, #6
801144c: f200 80a2 bhi.w 8011594 <tcp_slowtmr+0x2f8>
pcb->persist_backoff++;
8011450: 6afb ldr r3, [r7, #44] ; 0x2c
8011452: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8011456: 3301 adds r3, #1
8011458: b2da uxtb r2, r3
801145a: 6afb ldr r3, [r7, #44] ; 0x2c
801145c: f883 2099 strb.w r2, [r3, #153] ; 0x99
8011460: e098 b.n 8011594 <tcp_slowtmr+0x2f8>
}
}
}
} else {
/* Increase the retransmission timer if it is running */
if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
8011462: 6afb ldr r3, [r7, #44] ; 0x2c
8011464: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011468: 2b00 cmp r3, #0
801146a: db0f blt.n 801148c <tcp_slowtmr+0x1f0>
801146c: 6afb ldr r3, [r7, #44] ; 0x2c
801146e: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011472: f647 72ff movw r2, #32767 ; 0x7fff
8011476: 4293 cmp r3, r2
8011478: d008 beq.n 801148c <tcp_slowtmr+0x1f0>
++pcb->rtime;
801147a: 6afb ldr r3, [r7, #44] ; 0x2c
801147c: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
8011480: b29b uxth r3, r3
8011482: 3301 adds r3, #1
8011484: b29b uxth r3, r3
8011486: b21a sxth r2, r3
8011488: 6afb ldr r3, [r7, #44] ; 0x2c
801148a: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rtime >= pcb->rto) {
801148c: 6afb ldr r3, [r7, #44] ; 0x2c
801148e: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30
8011492: 6afb ldr r3, [r7, #44] ; 0x2c
8011494: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
8011498: 429a cmp r2, r3
801149a: db7b blt.n 8011594 <tcp_slowtmr+0x2f8>
" pcb->rto %"S16_F"\n",
pcb->rtime, pcb->rto));
/* If prepare phase fails but we have unsent data but no unacked data,
still execute the backoff calculations below, as this means we somehow
failed to send segment. */
if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
801149c: 6af8 ldr r0, [r7, #44] ; 0x2c
801149e: f004 f821 bl 80154e4 <tcp_rexmit_rto_prepare>
80114a2: 4603 mov r3, r0
80114a4: 2b00 cmp r3, #0
80114a6: d007 beq.n 80114b8 <tcp_slowtmr+0x21c>
80114a8: 6afb ldr r3, [r7, #44] ; 0x2c
80114aa: 6f1b ldr r3, [r3, #112] ; 0x70
80114ac: 2b00 cmp r3, #0
80114ae: d171 bne.n 8011594 <tcp_slowtmr+0x2f8>
80114b0: 6afb ldr r3, [r7, #44] ; 0x2c
80114b2: 6edb ldr r3, [r3, #108] ; 0x6c
80114b4: 2b00 cmp r3, #0
80114b6: d06d beq.n 8011594 <tcp_slowtmr+0x2f8>
/* Double retransmission time-out unless we are trying to
* connect to somebody (i.e., we are in SYN_SENT). */
if (pcb->state != SYN_SENT) {
80114b8: 6afb ldr r3, [r7, #44] ; 0x2c
80114ba: 7d1b ldrb r3, [r3, #20]
80114bc: 2b02 cmp r3, #2
80114be: d03a beq.n 8011536 <tcp_slowtmr+0x29a>
u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
80114c0: 6afb ldr r3, [r7, #44] ; 0x2c
80114c2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80114c6: 2b0c cmp r3, #12
80114c8: bf28 it cs
80114ca: 230c movcs r3, #12
80114cc: 76fb strb r3, [r7, #27]
int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
80114ce: 6afb ldr r3, [r7, #44] ; 0x2c
80114d0: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
80114d4: 10db asrs r3, r3, #3
80114d6: b21b sxth r3, r3
80114d8: 461a mov r2, r3
80114da: 6afb ldr r3, [r7, #44] ; 0x2c
80114dc: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
80114e0: 4413 add r3, r2
80114e2: 7efa ldrb r2, [r7, #27]
80114e4: 4910 ldr r1, [pc, #64] ; (8011528 <tcp_slowtmr+0x28c>)
80114e6: 5c8a ldrb r2, [r1, r2]
80114e8: 4093 lsls r3, r2
80114ea: 617b str r3, [r7, #20]
pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
80114ec: 697b ldr r3, [r7, #20]
80114ee: f647 72fe movw r2, #32766 ; 0x7ffe
80114f2: 4293 cmp r3, r2
80114f4: dc1a bgt.n 801152c <tcp_slowtmr+0x290>
80114f6: 697b ldr r3, [r7, #20]
80114f8: b21a sxth r2, r3
80114fa: e019 b.n 8011530 <tcp_slowtmr+0x294>
80114fc: 2000f5c4 .word 0x2000f5c4
8011500: 2000872a .word 0x2000872a
8011504: 2000f5c0 .word 0x2000f5c0
8011508: 0801cb58 .word 0x0801cb58
801150c: 0801ce9c .word 0x0801ce9c
8011510: 0801cb9c .word 0x0801cb9c
8011514: 0801cec8 .word 0x0801cec8
8011518: 0801cef4 .word 0x0801cef4
801151c: 0801cf24 .word 0x0801cf24
8011520: 0801cf58 .word 0x0801cf58
8011524: 08020e38 .word 0x08020e38
8011528: 08020e28 .word 0x08020e28
801152c: f647 72ff movw r2, #32767 ; 0x7fff
8011530: 6afb ldr r3, [r7, #44] ; 0x2c
8011532: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
}
/* Reset the retransmission timer. */
pcb->rtime = 0;
8011536: 6afb ldr r3, [r7, #44] ; 0x2c
8011538: 2200 movs r2, #0
801153a: 861a strh r2, [r3, #48] ; 0x30
/* Reduce congestion window and ssthresh. */
eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
801153c: 6afb ldr r3, [r7, #44] ; 0x2c
801153e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8011542: 6afb ldr r3, [r7, #44] ; 0x2c
8011544: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8011548: 4293 cmp r3, r2
801154a: bf28 it cs
801154c: 4613 movcs r3, r2
801154e: 827b strh r3, [r7, #18]
pcb->ssthresh = eff_wnd >> 1;
8011550: 8a7b ldrh r3, [r7, #18]
8011552: 085b lsrs r3, r3, #1
8011554: b29a uxth r2, r3
8011556: 6afb ldr r3, [r7, #44] ; 0x2c
8011558: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
801155c: 6afb ldr r3, [r7, #44] ; 0x2c
801155e: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
8011562: 6afb ldr r3, [r7, #44] ; 0x2c
8011564: 8e5b ldrh r3, [r3, #50] ; 0x32
8011566: 005b lsls r3, r3, #1
8011568: b29b uxth r3, r3
801156a: 429a cmp r2, r3
801156c: d206 bcs.n 801157c <tcp_slowtmr+0x2e0>
pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
801156e: 6afb ldr r3, [r7, #44] ; 0x2c
8011570: 8e5b ldrh r3, [r3, #50] ; 0x32
8011572: 005b lsls r3, r3, #1
8011574: b29a uxth r2, r3
8011576: 6afb ldr r3, [r7, #44] ; 0x2c
8011578: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->mss;
801157c: 6afb ldr r3, [r7, #44] ; 0x2c
801157e: 8e5a ldrh r2, [r3, #50] ; 0x32
8011580: 6afb ldr r3, [r7, #44] ; 0x2c
8011582: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
pcb->bytes_acked = 0;
8011586: 6afb ldr r3, [r7, #44] ; 0x2c
8011588: 2200 movs r2, #0
801158a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
/* The following needs to be called AFTER cwnd is set to one
mss - STJ */
tcp_rexmit_rto_commit(pcb);
801158e: 6af8 ldr r0, [r7, #44] ; 0x2c
8011590: f004 f818 bl 80155c4 <tcp_rexmit_rto_commit>
}
}
}
}
/* Check if this PCB has stayed too long in FIN-WAIT-2 */
if (pcb->state == FIN_WAIT_2) {
8011594: 6afb ldr r3, [r7, #44] ; 0x2c
8011596: 7d1b ldrb r3, [r3, #20]
8011598: 2b06 cmp r3, #6
801159a: d111 bne.n 80115c0 <tcp_slowtmr+0x324>
/* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
if (pcb->flags & TF_RXCLOSED) {
801159c: 6afb ldr r3, [r7, #44] ; 0x2c
801159e: 8b5b ldrh r3, [r3, #26]
80115a0: f003 0310 and.w r3, r3, #16
80115a4: 2b00 cmp r3, #0
80115a6: d00b beq.n 80115c0 <tcp_slowtmr+0x324>
/* PCB was fully closed (either through close() or SHUT_RDWR):
normal FIN-WAIT timeout handling. */
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115a8: 4b9c ldr r3, [pc, #624] ; (801181c <tcp_slowtmr+0x580>)
80115aa: 681a ldr r2, [r3, #0]
80115ac: 6afb ldr r3, [r7, #44] ; 0x2c
80115ae: 6a1b ldr r3, [r3, #32]
80115b0: 1ad3 subs r3, r2, r3
80115b2: 2b28 cmp r3, #40 ; 0x28
80115b4: d904 bls.n 80115c0 <tcp_slowtmr+0x324>
TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
80115b6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80115ba: 3301 adds r3, #1
80115bc: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
}
/* Check if KEEPALIVE should be sent */
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
80115c0: 6afb ldr r3, [r7, #44] ; 0x2c
80115c2: 7a5b ldrb r3, [r3, #9]
80115c4: f003 0308 and.w r3, r3, #8
80115c8: 2b00 cmp r3, #0
80115ca: d04a beq.n 8011662 <tcp_slowtmr+0x3c6>
((pcb->state == ESTABLISHED) ||
80115cc: 6afb ldr r3, [r7, #44] ; 0x2c
80115ce: 7d1b ldrb r3, [r3, #20]
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
80115d0: 2b04 cmp r3, #4
80115d2: d003 beq.n 80115dc <tcp_slowtmr+0x340>
(pcb->state == CLOSE_WAIT))) {
80115d4: 6afb ldr r3, [r7, #44] ; 0x2c
80115d6: 7d1b ldrb r3, [r3, #20]
((pcb->state == ESTABLISHED) ||
80115d8: 2b07 cmp r3, #7
80115da: d142 bne.n 8011662 <tcp_slowtmr+0x3c6>
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115dc: 4b8f ldr r3, [pc, #572] ; (801181c <tcp_slowtmr+0x580>)
80115de: 681a ldr r2, [r3, #0]
80115e0: 6afb ldr r3, [r7, #44] ; 0x2c
80115e2: 6a1b ldr r3, [r3, #32]
80115e4: 1ad2 subs r2, r2, r3
(pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
80115e6: 6afb ldr r3, [r7, #44] ; 0x2c
80115e8: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
80115ec: 4b8c ldr r3, [pc, #560] ; (8011820 <tcp_slowtmr+0x584>)
80115ee: 440b add r3, r1
80115f0: 498c ldr r1, [pc, #560] ; (8011824 <tcp_slowtmr+0x588>)
80115f2: fba1 1303 umull r1, r3, r1, r3
80115f6: 095b lsrs r3, r3, #5
if ((u32_t)(tcp_ticks - pcb->tmr) >
80115f8: 429a cmp r2, r3
80115fa: d90a bls.n 8011612 <tcp_slowtmr+0x376>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
++pcb_remove;
80115fc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011600: 3301 adds r3, #1
8011602: f887 3027 strb.w r3, [r7, #39] ; 0x27
++pcb_reset;
8011606: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801160a: 3301 adds r3, #1
801160c: f887 3026 strb.w r3, [r7, #38] ; 0x26
8011610: e027 b.n 8011662 <tcp_slowtmr+0x3c6>
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
8011612: 4b82 ldr r3, [pc, #520] ; (801181c <tcp_slowtmr+0x580>)
8011614: 681a ldr r2, [r3, #0]
8011616: 6afb ldr r3, [r7, #44] ; 0x2c
8011618: 6a1b ldr r3, [r3, #32]
801161a: 1ad2 subs r2, r2, r3
(pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
801161c: 6afb ldr r3, [r7, #44] ; 0x2c
801161e: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
8011622: 6afb ldr r3, [r7, #44] ; 0x2c
8011624: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
8011628: 4618 mov r0, r3
801162a: 4b7f ldr r3, [pc, #508] ; (8011828 <tcp_slowtmr+0x58c>)
801162c: fb03 f300 mul.w r3, r3, r0
8011630: 440b add r3, r1
/ TCP_SLOW_INTERVAL) {
8011632: 497c ldr r1, [pc, #496] ; (8011824 <tcp_slowtmr+0x588>)
8011634: fba1 1303 umull r1, r3, r1, r3
8011638: 095b lsrs r3, r3, #5
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
801163a: 429a cmp r2, r3
801163c: d911 bls.n 8011662 <tcp_slowtmr+0x3c6>
err = tcp_keepalive(pcb);
801163e: 6af8 ldr r0, [r7, #44] ; 0x2c
8011640: f004 fad2 bl 8015be8 <tcp_keepalive>
8011644: 4603 mov r3, r0
8011646: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (err == ERR_OK) {
801164a: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
801164e: 2b00 cmp r3, #0
8011650: d107 bne.n 8011662 <tcp_slowtmr+0x3c6>
pcb->keep_cnt_sent++;
8011652: 6afb ldr r3, [r7, #44] ; 0x2c
8011654: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
8011658: 3301 adds r3, #1
801165a: b2da uxtb r2, r3
801165c: 6afb ldr r3, [r7, #44] ; 0x2c
801165e: f883 209b strb.w r2, [r3, #155] ; 0x9b
/* If this PCB has queued out of sequence data, but has been
inactive for too long, will drop the data (it will eventually
be retransmitted). */
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL &&
8011662: 6afb ldr r3, [r7, #44] ; 0x2c
8011664: 6f5b ldr r3, [r3, #116] ; 0x74
8011666: 2b00 cmp r3, #0
8011668: d011 beq.n 801168e <tcp_slowtmr+0x3f2>
(tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
801166a: 4b6c ldr r3, [pc, #432] ; (801181c <tcp_slowtmr+0x580>)
801166c: 681a ldr r2, [r3, #0]
801166e: 6afb ldr r3, [r7, #44] ; 0x2c
8011670: 6a1b ldr r3, [r3, #32]
8011672: 1ad2 subs r2, r2, r3
8011674: 6afb ldr r3, [r7, #44] ; 0x2c
8011676: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
801167a: 4619 mov r1, r3
801167c: 460b mov r3, r1
801167e: 005b lsls r3, r3, #1
8011680: 440b add r3, r1
8011682: 005b lsls r3, r3, #1
if (pcb->ooseq != NULL &&
8011684: 429a cmp r2, r3
8011686: d302 bcc.n 801168e <tcp_slowtmr+0x3f2>
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
tcp_free_ooseq(pcb);
8011688: 6af8 ldr r0, [r7, #44] ; 0x2c
801168a: f000 fdd9 bl 8012240 <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Check if this PCB has stayed too long in SYN-RCVD */
if (pcb->state == SYN_RCVD) {
801168e: 6afb ldr r3, [r7, #44] ; 0x2c
8011690: 7d1b ldrb r3, [r3, #20]
8011692: 2b03 cmp r3, #3
8011694: d10b bne.n 80116ae <tcp_slowtmr+0x412>
if ((u32_t)(tcp_ticks - pcb->tmr) >
8011696: 4b61 ldr r3, [pc, #388] ; (801181c <tcp_slowtmr+0x580>)
8011698: 681a ldr r2, [r3, #0]
801169a: 6afb ldr r3, [r7, #44] ; 0x2c
801169c: 6a1b ldr r3, [r3, #32]
801169e: 1ad3 subs r3, r2, r3
80116a0: 2b28 cmp r3, #40 ; 0x28
80116a2: d904 bls.n 80116ae <tcp_slowtmr+0x412>
TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
++pcb_remove;
80116a4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80116a8: 3301 adds r3, #1
80116aa: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
}
}
/* Check if this PCB has stayed too long in LAST-ACK */
if (pcb->state == LAST_ACK) {
80116ae: 6afb ldr r3, [r7, #44] ; 0x2c
80116b0: 7d1b ldrb r3, [r3, #20]
80116b2: 2b09 cmp r3, #9
80116b4: d10b bne.n 80116ce <tcp_slowtmr+0x432>
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
80116b6: 4b59 ldr r3, [pc, #356] ; (801181c <tcp_slowtmr+0x580>)
80116b8: 681a ldr r2, [r3, #0]
80116ba: 6afb ldr r3, [r7, #44] ; 0x2c
80116bc: 6a1b ldr r3, [r3, #32]
80116be: 1ad3 subs r3, r2, r3
80116c0: 2bf0 cmp r3, #240 ; 0xf0
80116c2: d904 bls.n 80116ce <tcp_slowtmr+0x432>
++pcb_remove;
80116c4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80116c8: 3301 adds r3, #1
80116ca: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
}
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
80116ce: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80116d2: 2b00 cmp r3, #0
80116d4: d060 beq.n 8011798 <tcp_slowtmr+0x4fc>
struct tcp_pcb *pcb2;
#if LWIP_CALLBACK_API
tcp_err_fn err_fn = pcb->errf;
80116d6: 6afb ldr r3, [r7, #44] ; 0x2c
80116d8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80116dc: 60fb str r3, [r7, #12]
#endif /* LWIP_CALLBACK_API */
void *err_arg;
enum tcp_state last_state;
tcp_pcb_purge(pcb);
80116de: 6af8 ldr r0, [r7, #44] ; 0x2c
80116e0: f000 fbfa bl 8011ed8 <tcp_pcb_purge>
/* Remove PCB from tcp_active_pcbs list. */
if (prev != NULL) {
80116e4: 6abb ldr r3, [r7, #40] ; 0x28
80116e6: 2b00 cmp r3, #0
80116e8: d010 beq.n 801170c <tcp_slowtmr+0x470>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
80116ea: 4b50 ldr r3, [pc, #320] ; (801182c <tcp_slowtmr+0x590>)
80116ec: 681b ldr r3, [r3, #0]
80116ee: 6afa ldr r2, [r7, #44] ; 0x2c
80116f0: 429a cmp r2, r3
80116f2: d106 bne.n 8011702 <tcp_slowtmr+0x466>
80116f4: 4b4e ldr r3, [pc, #312] ; (8011830 <tcp_slowtmr+0x594>)
80116f6: f240 526d movw r2, #1389 ; 0x56d
80116fa: 494e ldr r1, [pc, #312] ; (8011834 <tcp_slowtmr+0x598>)
80116fc: 484e ldr r0, [pc, #312] ; (8011838 <tcp_slowtmr+0x59c>)
80116fe: f009 fc91 bl 801b024 <iprintf>
prev->next = pcb->next;
8011702: 6afb ldr r3, [r7, #44] ; 0x2c
8011704: 68da ldr r2, [r3, #12]
8011706: 6abb ldr r3, [r7, #40] ; 0x28
8011708: 60da str r2, [r3, #12]
801170a: e00f b.n 801172c <tcp_slowtmr+0x490>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
801170c: 4b47 ldr r3, [pc, #284] ; (801182c <tcp_slowtmr+0x590>)
801170e: 681b ldr r3, [r3, #0]
8011710: 6afa ldr r2, [r7, #44] ; 0x2c
8011712: 429a cmp r2, r3
8011714: d006 beq.n 8011724 <tcp_slowtmr+0x488>
8011716: 4b46 ldr r3, [pc, #280] ; (8011830 <tcp_slowtmr+0x594>)
8011718: f240 5271 movw r2, #1393 ; 0x571
801171c: 4947 ldr r1, [pc, #284] ; (801183c <tcp_slowtmr+0x5a0>)
801171e: 4846 ldr r0, [pc, #280] ; (8011838 <tcp_slowtmr+0x59c>)
8011720: f009 fc80 bl 801b024 <iprintf>
tcp_active_pcbs = pcb->next;
8011724: 6afb ldr r3, [r7, #44] ; 0x2c
8011726: 68db ldr r3, [r3, #12]
8011728: 4a40 ldr r2, [pc, #256] ; (801182c <tcp_slowtmr+0x590>)
801172a: 6013 str r3, [r2, #0]
}
if (pcb_reset) {
801172c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8011730: 2b00 cmp r3, #0
8011732: d013 beq.n 801175c <tcp_slowtmr+0x4c0>
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
8011734: 6afb ldr r3, [r7, #44] ; 0x2c
8011736: 6d18 ldr r0, [r3, #80] ; 0x50
8011738: 6afb ldr r3, [r7, #44] ; 0x2c
801173a: 6a5c ldr r4, [r3, #36] ; 0x24
801173c: 6afd ldr r5, [r7, #44] ; 0x2c
801173e: 6afb ldr r3, [r7, #44] ; 0x2c
8011740: 3304 adds r3, #4
8011742: 6afa ldr r2, [r7, #44] ; 0x2c
8011744: 8ad2 ldrh r2, [r2, #22]
8011746: 6af9 ldr r1, [r7, #44] ; 0x2c
8011748: 8b09 ldrh r1, [r1, #24]
801174a: 9102 str r1, [sp, #8]
801174c: 9201 str r2, [sp, #4]
801174e: 9300 str r3, [sp, #0]
8011750: 462b mov r3, r5
8011752: 4622 mov r2, r4
8011754: 4601 mov r1, r0
8011756: 6af8 ldr r0, [r7, #44] ; 0x2c
8011758: f004 f992 bl 8015a80 <tcp_rst>
pcb->local_port, pcb->remote_port);
}
err_arg = pcb->callback_arg;
801175c: 6afb ldr r3, [r7, #44] ; 0x2c
801175e: 691b ldr r3, [r3, #16]
8011760: 60bb str r3, [r7, #8]
last_state = pcb->state;
8011762: 6afb ldr r3, [r7, #44] ; 0x2c
8011764: 7d1b ldrb r3, [r3, #20]
8011766: 71fb strb r3, [r7, #7]
pcb2 = pcb;
8011768: 6afb ldr r3, [r7, #44] ; 0x2c
801176a: 603b str r3, [r7, #0]
pcb = pcb->next;
801176c: 6afb ldr r3, [r7, #44] ; 0x2c
801176e: 68db ldr r3, [r3, #12]
8011770: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
8011772: 6838 ldr r0, [r7, #0]
8011774: f7ff f9fc bl 8010b70 <tcp_free>
tcp_active_pcbs_changed = 0;
8011778: 4b31 ldr r3, [pc, #196] ; (8011840 <tcp_slowtmr+0x5a4>)
801177a: 2200 movs r2, #0
801177c: 701a strb r2, [r3, #0]
TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
801177e: 68fb ldr r3, [r7, #12]
8011780: 2b00 cmp r3, #0
8011782: d004 beq.n 801178e <tcp_slowtmr+0x4f2>
8011784: 68fb ldr r3, [r7, #12]
8011786: f06f 010c mvn.w r1, #12
801178a: 68b8 ldr r0, [r7, #8]
801178c: 4798 blx r3
if (tcp_active_pcbs_changed) {
801178e: 4b2c ldr r3, [pc, #176] ; (8011840 <tcp_slowtmr+0x5a4>)
8011790: 781b ldrb r3, [r3, #0]
8011792: 2b00 cmp r3, #0
8011794: d037 beq.n 8011806 <tcp_slowtmr+0x56a>
goto tcp_slowtmr_start;
8011796: e592 b.n 80112be <tcp_slowtmr+0x22>
}
} else {
/* get the 'next' element now and work with 'prev' below (in case of abort) */
prev = pcb;
8011798: 6afb ldr r3, [r7, #44] ; 0x2c
801179a: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
801179c: 6afb ldr r3, [r7, #44] ; 0x2c
801179e: 68db ldr r3, [r3, #12]
80117a0: 62fb str r3, [r7, #44] ; 0x2c
/* We check if we should poll the connection. */
++prev->polltmr;
80117a2: 6abb ldr r3, [r7, #40] ; 0x28
80117a4: 7f1b ldrb r3, [r3, #28]
80117a6: 3301 adds r3, #1
80117a8: b2da uxtb r2, r3
80117aa: 6abb ldr r3, [r7, #40] ; 0x28
80117ac: 771a strb r2, [r3, #28]
if (prev->polltmr >= prev->pollinterval) {
80117ae: 6abb ldr r3, [r7, #40] ; 0x28
80117b0: 7f1a ldrb r2, [r3, #28]
80117b2: 6abb ldr r3, [r7, #40] ; 0x28
80117b4: 7f5b ldrb r3, [r3, #29]
80117b6: 429a cmp r2, r3
80117b8: d325 bcc.n 8011806 <tcp_slowtmr+0x56a>
prev->polltmr = 0;
80117ba: 6abb ldr r3, [r7, #40] ; 0x28
80117bc: 2200 movs r2, #0
80117be: 771a strb r2, [r3, #28]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
tcp_active_pcbs_changed = 0;
80117c0: 4b1f ldr r3, [pc, #124] ; (8011840 <tcp_slowtmr+0x5a4>)
80117c2: 2200 movs r2, #0
80117c4: 701a strb r2, [r3, #0]
TCP_EVENT_POLL(prev, err);
80117c6: 6abb ldr r3, [r7, #40] ; 0x28
80117c8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80117cc: 2b00 cmp r3, #0
80117ce: d00b beq.n 80117e8 <tcp_slowtmr+0x54c>
80117d0: 6abb ldr r3, [r7, #40] ; 0x28
80117d2: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80117d6: 6aba ldr r2, [r7, #40] ; 0x28
80117d8: 6912 ldr r2, [r2, #16]
80117da: 6ab9 ldr r1, [r7, #40] ; 0x28
80117dc: 4610 mov r0, r2
80117de: 4798 blx r3
80117e0: 4603 mov r3, r0
80117e2: f887 3025 strb.w r3, [r7, #37] ; 0x25
80117e6: e002 b.n 80117ee <tcp_slowtmr+0x552>
80117e8: 2300 movs r3, #0
80117ea: f887 3025 strb.w r3, [r7, #37] ; 0x25
if (tcp_active_pcbs_changed) {
80117ee: 4b14 ldr r3, [pc, #80] ; (8011840 <tcp_slowtmr+0x5a4>)
80117f0: 781b ldrb r3, [r3, #0]
80117f2: 2b00 cmp r3, #0
80117f4: d000 beq.n 80117f8 <tcp_slowtmr+0x55c>
goto tcp_slowtmr_start;
80117f6: e562 b.n 80112be <tcp_slowtmr+0x22>
}
/* if err == ERR_ABRT, 'prev' is already deallocated */
if (err == ERR_OK) {
80117f8: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
80117fc: 2b00 cmp r3, #0
80117fe: d102 bne.n 8011806 <tcp_slowtmr+0x56a>
tcp_output(prev);
8011800: 6ab8 ldr r0, [r7, #40] ; 0x28
8011802: f003 fb77 bl 8014ef4 <tcp_output>
while (pcb != NULL) {
8011806: 6afb ldr r3, [r7, #44] ; 0x2c
8011808: 2b00 cmp r3, #0
801180a: f47f ad5e bne.w 80112ca <tcp_slowtmr+0x2e>
}
}
/* Steps through all of the TIME-WAIT PCBs. */
prev = NULL;
801180e: 2300 movs r3, #0
8011810: 62bb str r3, [r7, #40] ; 0x28
pcb = tcp_tw_pcbs;
8011812: 4b0c ldr r3, [pc, #48] ; (8011844 <tcp_slowtmr+0x5a8>)
8011814: 681b ldr r3, [r3, #0]
8011816: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
8011818: e069 b.n 80118ee <tcp_slowtmr+0x652>
801181a: bf00 nop
801181c: 2000f5c4 .word 0x2000f5c4
8011820: 000a4cb8 .word 0x000a4cb8
8011824: 10624dd3 .word 0x10624dd3
8011828: 000124f8 .word 0x000124f8
801182c: 2000f5c0 .word 0x2000f5c0
8011830: 0801cb58 .word 0x0801cb58
8011834: 0801cf90 .word 0x0801cf90
8011838: 0801cb9c .word 0x0801cb9c
801183c: 0801cfbc .word 0x0801cfbc
8011840: 2000f5bc .word 0x2000f5bc
8011844: 2000f5d0 .word 0x2000f5d0
LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
8011848: 6afb ldr r3, [r7, #44] ; 0x2c
801184a: 7d1b ldrb r3, [r3, #20]
801184c: 2b0a cmp r3, #10
801184e: d006 beq.n 801185e <tcp_slowtmr+0x5c2>
8011850: 4b2a ldr r3, [pc, #168] ; (80118fc <tcp_slowtmr+0x660>)
8011852: f240 52a1 movw r2, #1441 ; 0x5a1
8011856: 492a ldr r1, [pc, #168] ; (8011900 <tcp_slowtmr+0x664>)
8011858: 482a ldr r0, [pc, #168] ; (8011904 <tcp_slowtmr+0x668>)
801185a: f009 fbe3 bl 801b024 <iprintf>
pcb_remove = 0;
801185e: 2300 movs r3, #0
8011860: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* Check if this PCB has stayed long enough in TIME-WAIT */
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
8011864: 4b28 ldr r3, [pc, #160] ; (8011908 <tcp_slowtmr+0x66c>)
8011866: 681a ldr r2, [r3, #0]
8011868: 6afb ldr r3, [r7, #44] ; 0x2c
801186a: 6a1b ldr r3, [r3, #32]
801186c: 1ad3 subs r3, r2, r3
801186e: 2bf0 cmp r3, #240 ; 0xf0
8011870: d904 bls.n 801187c <tcp_slowtmr+0x5e0>
++pcb_remove;
8011872: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011876: 3301 adds r3, #1
8011878: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* If the PCB should be removed, do it. */
if (pcb_remove) {
801187c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8011880: 2b00 cmp r3, #0
8011882: d02f beq.n 80118e4 <tcp_slowtmr+0x648>
struct tcp_pcb *pcb2;
tcp_pcb_purge(pcb);
8011884: 6af8 ldr r0, [r7, #44] ; 0x2c
8011886: f000 fb27 bl 8011ed8 <tcp_pcb_purge>
/* Remove PCB from tcp_tw_pcbs list. */
if (prev != NULL) {
801188a: 6abb ldr r3, [r7, #40] ; 0x28
801188c: 2b00 cmp r3, #0
801188e: d010 beq.n 80118b2 <tcp_slowtmr+0x616>
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
8011890: 4b1e ldr r3, [pc, #120] ; (801190c <tcp_slowtmr+0x670>)
8011892: 681b ldr r3, [r3, #0]
8011894: 6afa ldr r2, [r7, #44] ; 0x2c
8011896: 429a cmp r2, r3
8011898: d106 bne.n 80118a8 <tcp_slowtmr+0x60c>
801189a: 4b18 ldr r3, [pc, #96] ; (80118fc <tcp_slowtmr+0x660>)
801189c: f240 52af movw r2, #1455 ; 0x5af
80118a0: 491b ldr r1, [pc, #108] ; (8011910 <tcp_slowtmr+0x674>)
80118a2: 4818 ldr r0, [pc, #96] ; (8011904 <tcp_slowtmr+0x668>)
80118a4: f009 fbbe bl 801b024 <iprintf>
prev->next = pcb->next;
80118a8: 6afb ldr r3, [r7, #44] ; 0x2c
80118aa: 68da ldr r2, [r3, #12]
80118ac: 6abb ldr r3, [r7, #40] ; 0x28
80118ae: 60da str r2, [r3, #12]
80118b0: e00f b.n 80118d2 <tcp_slowtmr+0x636>
} else {
/* This PCB was the first. */
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
80118b2: 4b16 ldr r3, [pc, #88] ; (801190c <tcp_slowtmr+0x670>)
80118b4: 681b ldr r3, [r3, #0]
80118b6: 6afa ldr r2, [r7, #44] ; 0x2c
80118b8: 429a cmp r2, r3
80118ba: d006 beq.n 80118ca <tcp_slowtmr+0x62e>
80118bc: 4b0f ldr r3, [pc, #60] ; (80118fc <tcp_slowtmr+0x660>)
80118be: f240 52b3 movw r2, #1459 ; 0x5b3
80118c2: 4914 ldr r1, [pc, #80] ; (8011914 <tcp_slowtmr+0x678>)
80118c4: 480f ldr r0, [pc, #60] ; (8011904 <tcp_slowtmr+0x668>)
80118c6: f009 fbad bl 801b024 <iprintf>
tcp_tw_pcbs = pcb->next;
80118ca: 6afb ldr r3, [r7, #44] ; 0x2c
80118cc: 68db ldr r3, [r3, #12]
80118ce: 4a0f ldr r2, [pc, #60] ; (801190c <tcp_slowtmr+0x670>)
80118d0: 6013 str r3, [r2, #0]
}
pcb2 = pcb;
80118d2: 6afb ldr r3, [r7, #44] ; 0x2c
80118d4: 61fb str r3, [r7, #28]
pcb = pcb->next;
80118d6: 6afb ldr r3, [r7, #44] ; 0x2c
80118d8: 68db ldr r3, [r3, #12]
80118da: 62fb str r3, [r7, #44] ; 0x2c
tcp_free(pcb2);
80118dc: 69f8 ldr r0, [r7, #28]
80118de: f7ff f947 bl 8010b70 <tcp_free>
80118e2: e004 b.n 80118ee <tcp_slowtmr+0x652>
} else {
prev = pcb;
80118e4: 6afb ldr r3, [r7, #44] ; 0x2c
80118e6: 62bb str r3, [r7, #40] ; 0x28
pcb = pcb->next;
80118e8: 6afb ldr r3, [r7, #44] ; 0x2c
80118ea: 68db ldr r3, [r3, #12]
80118ec: 62fb str r3, [r7, #44] ; 0x2c
while (pcb != NULL) {
80118ee: 6afb ldr r3, [r7, #44] ; 0x2c
80118f0: 2b00 cmp r3, #0
80118f2: d1a9 bne.n 8011848 <tcp_slowtmr+0x5ac>
}
}
}
80118f4: bf00 nop
80118f6: 3730 adds r7, #48 ; 0x30
80118f8: 46bd mov sp, r7
80118fa: bdb0 pop {r4, r5, r7, pc}
80118fc: 0801cb58 .word 0x0801cb58
8011900: 0801cfe8 .word 0x0801cfe8
8011904: 0801cb9c .word 0x0801cb9c
8011908: 2000f5c4 .word 0x2000f5c4
801190c: 2000f5d0 .word 0x2000f5d0
8011910: 0801d018 .word 0x0801d018
8011914: 0801d040 .word 0x0801d040
08011918 <tcp_fasttmr>:
*
* Automatically called from tcp_tmr().
*/
void
tcp_fasttmr(void)
{
8011918: b580 push {r7, lr}
801191a: b082 sub sp, #8
801191c: af00 add r7, sp, #0
struct tcp_pcb *pcb;
++tcp_timer_ctr;
801191e: 4b2d ldr r3, [pc, #180] ; (80119d4 <tcp_fasttmr+0xbc>)
8011920: 781b ldrb r3, [r3, #0]
8011922: 3301 adds r3, #1
8011924: b2da uxtb r2, r3
8011926: 4b2b ldr r3, [pc, #172] ; (80119d4 <tcp_fasttmr+0xbc>)
8011928: 701a strb r2, [r3, #0]
tcp_fasttmr_start:
pcb = tcp_active_pcbs;
801192a: 4b2b ldr r3, [pc, #172] ; (80119d8 <tcp_fasttmr+0xc0>)
801192c: 681b ldr r3, [r3, #0]
801192e: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011930: e048 b.n 80119c4 <tcp_fasttmr+0xac>
if (pcb->last_timer != tcp_timer_ctr) {
8011932: 687b ldr r3, [r7, #4]
8011934: 7f9a ldrb r2, [r3, #30]
8011936: 4b27 ldr r3, [pc, #156] ; (80119d4 <tcp_fasttmr+0xbc>)
8011938: 781b ldrb r3, [r3, #0]
801193a: 429a cmp r2, r3
801193c: d03f beq.n 80119be <tcp_fasttmr+0xa6>
struct tcp_pcb *next;
pcb->last_timer = tcp_timer_ctr;
801193e: 4b25 ldr r3, [pc, #148] ; (80119d4 <tcp_fasttmr+0xbc>)
8011940: 781a ldrb r2, [r3, #0]
8011942: 687b ldr r3, [r7, #4]
8011944: 779a strb r2, [r3, #30]
/* send delayed ACKs */
if (pcb->flags & TF_ACK_DELAY) {
8011946: 687b ldr r3, [r7, #4]
8011948: 8b5b ldrh r3, [r3, #26]
801194a: f003 0301 and.w r3, r3, #1
801194e: 2b00 cmp r3, #0
8011950: d010 beq.n 8011974 <tcp_fasttmr+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
tcp_ack_now(pcb);
8011952: 687b ldr r3, [r7, #4]
8011954: 8b5b ldrh r3, [r3, #26]
8011956: f043 0302 orr.w r3, r3, #2
801195a: b29a uxth r2, r3
801195c: 687b ldr r3, [r7, #4]
801195e: 835a strh r2, [r3, #26]
tcp_output(pcb);
8011960: 6878 ldr r0, [r7, #4]
8011962: f003 fac7 bl 8014ef4 <tcp_output>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8011966: 687b ldr r3, [r7, #4]
8011968: 8b5b ldrh r3, [r3, #26]
801196a: f023 0303 bic.w r3, r3, #3
801196e: b29a uxth r2, r3
8011970: 687b ldr r3, [r7, #4]
8011972: 835a strh r2, [r3, #26]
}
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
8011974: 687b ldr r3, [r7, #4]
8011976: 8b5b ldrh r3, [r3, #26]
8011978: f003 0308 and.w r3, r3, #8
801197c: 2b00 cmp r3, #0
801197e: d009 beq.n 8011994 <tcp_fasttmr+0x7c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011980: 687b ldr r3, [r7, #4]
8011982: 8b5b ldrh r3, [r3, #26]
8011984: f023 0308 bic.w r3, r3, #8
8011988: b29a uxth r2, r3
801198a: 687b ldr r3, [r7, #4]
801198c: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
801198e: 6878 ldr r0, [r7, #4]
8011990: f7ff fa7e bl 8010e90 <tcp_close_shutdown_fin>
}
next = pcb->next;
8011994: 687b ldr r3, [r7, #4]
8011996: 68db ldr r3, [r3, #12]
8011998: 603b str r3, [r7, #0]
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
801199a: 687b ldr r3, [r7, #4]
801199c: 6f9b ldr r3, [r3, #120] ; 0x78
801199e: 2b00 cmp r3, #0
80119a0: d00a beq.n 80119b8 <tcp_fasttmr+0xa0>
tcp_active_pcbs_changed = 0;
80119a2: 4b0e ldr r3, [pc, #56] ; (80119dc <tcp_fasttmr+0xc4>)
80119a4: 2200 movs r2, #0
80119a6: 701a strb r2, [r3, #0]
tcp_process_refused_data(pcb);
80119a8: 6878 ldr r0, [r7, #4]
80119aa: f000 f819 bl 80119e0 <tcp_process_refused_data>
if (tcp_active_pcbs_changed) {
80119ae: 4b0b ldr r3, [pc, #44] ; (80119dc <tcp_fasttmr+0xc4>)
80119b0: 781b ldrb r3, [r3, #0]
80119b2: 2b00 cmp r3, #0
80119b4: d000 beq.n 80119b8 <tcp_fasttmr+0xa0>
/* application callback has changed the pcb list: restart the loop */
goto tcp_fasttmr_start;
80119b6: e7b8 b.n 801192a <tcp_fasttmr+0x12>
}
}
pcb = next;
80119b8: 683b ldr r3, [r7, #0]
80119ba: 607b str r3, [r7, #4]
80119bc: e002 b.n 80119c4 <tcp_fasttmr+0xac>
} else {
pcb = pcb->next;
80119be: 687b ldr r3, [r7, #4]
80119c0: 68db ldr r3, [r3, #12]
80119c2: 607b str r3, [r7, #4]
while (pcb != NULL) {
80119c4: 687b ldr r3, [r7, #4]
80119c6: 2b00 cmp r3, #0
80119c8: d1b3 bne.n 8011932 <tcp_fasttmr+0x1a>
}
}
}
80119ca: bf00 nop
80119cc: 3708 adds r7, #8
80119ce: 46bd mov sp, r7
80119d0: bd80 pop {r7, pc}
80119d2: bf00 nop
80119d4: 2000872a .word 0x2000872a
80119d8: 2000f5c0 .word 0x2000f5c0
80119dc: 2000f5bc .word 0x2000f5bc
080119e0 <tcp_process_refused_data>:
}
/** Pass pcb->refused_data to the recv callback */
err_t
tcp_process_refused_data(struct tcp_pcb *pcb)
{
80119e0: b590 push {r4, r7, lr}
80119e2: b085 sub sp, #20
80119e4: af00 add r7, sp, #0
80119e6: 6078 str r0, [r7, #4]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
struct pbuf *rest;
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
80119e8: 687b ldr r3, [r7, #4]
80119ea: 2b00 cmp r3, #0
80119ec: d109 bne.n 8011a02 <tcp_process_refused_data+0x22>
80119ee: 4b37 ldr r3, [pc, #220] ; (8011acc <tcp_process_refused_data+0xec>)
80119f0: f240 6209 movw r2, #1545 ; 0x609
80119f4: 4936 ldr r1, [pc, #216] ; (8011ad0 <tcp_process_refused_data+0xf0>)
80119f6: 4837 ldr r0, [pc, #220] ; (8011ad4 <tcp_process_refused_data+0xf4>)
80119f8: f009 fb14 bl 801b024 <iprintf>
80119fc: f06f 030f mvn.w r3, #15
8011a00: e060 b.n 8011ac4 <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (pcb->refused_data != NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
{
err_t err;
u8_t refused_flags = pcb->refused_data->flags;
8011a02: 687b ldr r3, [r7, #4]
8011a04: 6f9b ldr r3, [r3, #120] ; 0x78
8011a06: 7b5b ldrb r3, [r3, #13]
8011a08: 73bb strb r3, [r7, #14]
/* set pcb->refused_data to NULL in case the callback frees it and then
closes the pcb */
struct pbuf *refused_data = pcb->refused_data;
8011a0a: 687b ldr r3, [r7, #4]
8011a0c: 6f9b ldr r3, [r3, #120] ; 0x78
8011a0e: 60bb str r3, [r7, #8]
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
pbuf_split_64k(refused_data, &rest);
pcb->refused_data = rest;
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = NULL;
8011a10: 687b ldr r3, [r7, #4]
8011a12: 2200 movs r2, #0
8011a14: 679a str r2, [r3, #120] ; 0x78
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
/* Notify again application with data previously received. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
8011a16: 687b ldr r3, [r7, #4]
8011a18: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8011a1c: 2b00 cmp r3, #0
8011a1e: d00b beq.n 8011a38 <tcp_process_refused_data+0x58>
8011a20: 687b ldr r3, [r7, #4]
8011a22: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8011a26: 687b ldr r3, [r7, #4]
8011a28: 6918 ldr r0, [r3, #16]
8011a2a: 2300 movs r3, #0
8011a2c: 68ba ldr r2, [r7, #8]
8011a2e: 6879 ldr r1, [r7, #4]
8011a30: 47a0 blx r4
8011a32: 4603 mov r3, r0
8011a34: 73fb strb r3, [r7, #15]
8011a36: e007 b.n 8011a48 <tcp_process_refused_data+0x68>
8011a38: 2300 movs r3, #0
8011a3a: 68ba ldr r2, [r7, #8]
8011a3c: 6879 ldr r1, [r7, #4]
8011a3e: 2000 movs r0, #0
8011a40: f000 f8a2 bl 8011b88 <tcp_recv_null>
8011a44: 4603 mov r3, r0
8011a46: 73fb strb r3, [r7, #15]
if (err == ERR_OK) {
8011a48: f997 300f ldrsb.w r3, [r7, #15]
8011a4c: 2b00 cmp r3, #0
8011a4e: d12a bne.n 8011aa6 <tcp_process_refused_data+0xc6>
/* did refused_data include a FIN? */
if ((refused_flags & PBUF_FLAG_TCP_FIN)
8011a50: 7bbb ldrb r3, [r7, #14]
8011a52: f003 0320 and.w r3, r3, #32
8011a56: 2b00 cmp r3, #0
8011a58: d033 beq.n 8011ac2 <tcp_process_refused_data+0xe2>
&& (rest == NULL)
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
) {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
8011a5a: 687b ldr r3, [r7, #4]
8011a5c: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a5e: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8011a62: d005 beq.n 8011a70 <tcp_process_refused_data+0x90>
pcb->rcv_wnd++;
8011a64: 687b ldr r3, [r7, #4]
8011a66: 8d1b ldrh r3, [r3, #40] ; 0x28
8011a68: 3301 adds r3, #1
8011a6a: b29a uxth r2, r3
8011a6c: 687b ldr r3, [r7, #4]
8011a6e: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
8011a70: 687b ldr r3, [r7, #4]
8011a72: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8011a76: 2b00 cmp r3, #0
8011a78: d00b beq.n 8011a92 <tcp_process_refused_data+0xb2>
8011a7a: 687b ldr r3, [r7, #4]
8011a7c: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8011a80: 687b ldr r3, [r7, #4]
8011a82: 6918 ldr r0, [r3, #16]
8011a84: 2300 movs r3, #0
8011a86: 2200 movs r2, #0
8011a88: 6879 ldr r1, [r7, #4]
8011a8a: 47a0 blx r4
8011a8c: 4603 mov r3, r0
8011a8e: 73fb strb r3, [r7, #15]
8011a90: e001 b.n 8011a96 <tcp_process_refused_data+0xb6>
8011a92: 2300 movs r3, #0
8011a94: 73fb strb r3, [r7, #15]
if (err == ERR_ABRT) {
8011a96: f997 300f ldrsb.w r3, [r7, #15]
8011a9a: f113 0f0d cmn.w r3, #13
8011a9e: d110 bne.n 8011ac2 <tcp_process_refused_data+0xe2>
return ERR_ABRT;
8011aa0: f06f 030c mvn.w r3, #12
8011aa4: e00e b.n 8011ac4 <tcp_process_refused_data+0xe4>
}
}
} else if (err == ERR_ABRT) {
8011aa6: f997 300f ldrsb.w r3, [r7, #15]
8011aaa: f113 0f0d cmn.w r3, #13
8011aae: d102 bne.n 8011ab6 <tcp_process_refused_data+0xd6>
/* if err == ERR_ABRT, 'pcb' is already deallocated */
/* Drop incoming packets because pcb is "full" (only if the incoming
segment contains data). */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
return ERR_ABRT;
8011ab0: f06f 030c mvn.w r3, #12
8011ab4: e006 b.n 8011ac4 <tcp_process_refused_data+0xe4>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(refused_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = refused_data;
8011ab6: 687b ldr r3, [r7, #4]
8011ab8: 68ba ldr r2, [r7, #8]
8011aba: 679a str r2, [r3, #120] ; 0x78
return ERR_INPROGRESS;
8011abc: f06f 0304 mvn.w r3, #4
8011ac0: e000 b.n 8011ac4 <tcp_process_refused_data+0xe4>
}
}
return ERR_OK;
8011ac2: 2300 movs r3, #0
}
8011ac4: 4618 mov r0, r3
8011ac6: 3714 adds r7, #20
8011ac8: 46bd mov sp, r7
8011aca: bd90 pop {r4, r7, pc}
8011acc: 0801cb58 .word 0x0801cb58
8011ad0: 0801d068 .word 0x0801d068
8011ad4: 0801cb9c .word 0x0801cb9c
08011ad8 <tcp_segs_free>:
*
* @param seg tcp_seg list of TCP segments to free
*/
void
tcp_segs_free(struct tcp_seg *seg)
{
8011ad8: b580 push {r7, lr}
8011ada: b084 sub sp, #16
8011adc: af00 add r7, sp, #0
8011ade: 6078 str r0, [r7, #4]
while (seg != NULL) {
8011ae0: e007 b.n 8011af2 <tcp_segs_free+0x1a>
struct tcp_seg *next = seg->next;
8011ae2: 687b ldr r3, [r7, #4]
8011ae4: 681b ldr r3, [r3, #0]
8011ae6: 60fb str r3, [r7, #12]
tcp_seg_free(seg);
8011ae8: 6878 ldr r0, [r7, #4]
8011aea: f000 f809 bl 8011b00 <tcp_seg_free>
seg = next;
8011aee: 68fb ldr r3, [r7, #12]
8011af0: 607b str r3, [r7, #4]
while (seg != NULL) {
8011af2: 687b ldr r3, [r7, #4]
8011af4: 2b00 cmp r3, #0
8011af6: d1f4 bne.n 8011ae2 <tcp_segs_free+0xa>
}
}
8011af8: bf00 nop
8011afa: 3710 adds r7, #16
8011afc: 46bd mov sp, r7
8011afe: bd80 pop {r7, pc}
08011b00 <tcp_seg_free>:
*
* @param seg single tcp_seg to free
*/
void
tcp_seg_free(struct tcp_seg *seg)
{
8011b00: b580 push {r7, lr}
8011b02: b082 sub sp, #8
8011b04: af00 add r7, sp, #0
8011b06: 6078 str r0, [r7, #4]
if (seg != NULL) {
8011b08: 687b ldr r3, [r7, #4]
8011b0a: 2b00 cmp r3, #0
8011b0c: d00c beq.n 8011b28 <tcp_seg_free+0x28>
if (seg->p != NULL) {
8011b0e: 687b ldr r3, [r7, #4]
8011b10: 685b ldr r3, [r3, #4]
8011b12: 2b00 cmp r3, #0
8011b14: d004 beq.n 8011b20 <tcp_seg_free+0x20>
pbuf_free(seg->p);
8011b16: 687b ldr r3, [r7, #4]
8011b18: 685b ldr r3, [r3, #4]
8011b1a: 4618 mov r0, r3
8011b1c: f7fe fd6c bl 80105f8 <pbuf_free>
#if TCP_DEBUG
seg->p = NULL;
#endif /* TCP_DEBUG */
}
memp_free(MEMP_TCP_SEG, seg);
8011b20: 6879 ldr r1, [r7, #4]
8011b22: 2003 movs r0, #3
8011b24: f7fd febc bl 800f8a0 <memp_free>
}
}
8011b28: bf00 nop
8011b2a: 3708 adds r7, #8
8011b2c: 46bd mov sp, r7
8011b2e: bd80 pop {r7, pc}
08011b30 <tcp_seg_copy>:
* @param seg the old tcp_seg
* @return a copy of seg
*/
struct tcp_seg *
tcp_seg_copy(struct tcp_seg *seg)
{
8011b30: b580 push {r7, lr}
8011b32: b084 sub sp, #16
8011b34: af00 add r7, sp, #0
8011b36: 6078 str r0, [r7, #4]
struct tcp_seg *cseg;
LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
8011b38: 687b ldr r3, [r7, #4]
8011b3a: 2b00 cmp r3, #0
8011b3c: d106 bne.n 8011b4c <tcp_seg_copy+0x1c>
8011b3e: 4b0f ldr r3, [pc, #60] ; (8011b7c <tcp_seg_copy+0x4c>)
8011b40: f240 6282 movw r2, #1666 ; 0x682
8011b44: 490e ldr r1, [pc, #56] ; (8011b80 <tcp_seg_copy+0x50>)
8011b46: 480f ldr r0, [pc, #60] ; (8011b84 <tcp_seg_copy+0x54>)
8011b48: f009 fa6c bl 801b024 <iprintf>
cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
8011b4c: 2003 movs r0, #3
8011b4e: f7fd fe55 bl 800f7fc <memp_malloc>
8011b52: 60f8 str r0, [r7, #12]
if (cseg == NULL) {
8011b54: 68fb ldr r3, [r7, #12]
8011b56: 2b00 cmp r3, #0
8011b58: d101 bne.n 8011b5e <tcp_seg_copy+0x2e>
return NULL;
8011b5a: 2300 movs r3, #0
8011b5c: e00a b.n 8011b74 <tcp_seg_copy+0x44>
}
SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
8011b5e: 2210 movs r2, #16
8011b60: 6879 ldr r1, [r7, #4]
8011b62: 68f8 ldr r0, [r7, #12]
8011b64: f009 fa4b bl 801affe <memcpy>
pbuf_ref(cseg->p);
8011b68: 68fb ldr r3, [r7, #12]
8011b6a: 685b ldr r3, [r3, #4]
8011b6c: 4618 mov r0, r3
8011b6e: f7fe fde9 bl 8010744 <pbuf_ref>
return cseg;
8011b72: 68fb ldr r3, [r7, #12]
}
8011b74: 4618 mov r0, r3
8011b76: 3710 adds r7, #16
8011b78: 46bd mov sp, r7
8011b7a: bd80 pop {r7, pc}
8011b7c: 0801cb58 .word 0x0801cb58
8011b80: 0801d0ac .word 0x0801d0ac
8011b84: 0801cb9c .word 0x0801cb9c
08011b88 <tcp_recv_null>:
* Default receive callback that is called if the user didn't register
* a recv callback for the pcb.
*/
err_t
tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
{
8011b88: b580 push {r7, lr}
8011b8a: b084 sub sp, #16
8011b8c: af00 add r7, sp, #0
8011b8e: 60f8 str r0, [r7, #12]
8011b90: 60b9 str r1, [r7, #8]
8011b92: 607a str r2, [r7, #4]
8011b94: 70fb strb r3, [r7, #3]
LWIP_UNUSED_ARG(arg);
LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
8011b96: 68bb ldr r3, [r7, #8]
8011b98: 2b00 cmp r3, #0
8011b9a: d109 bne.n 8011bb0 <tcp_recv_null+0x28>
8011b9c: 4b12 ldr r3, [pc, #72] ; (8011be8 <tcp_recv_null+0x60>)
8011b9e: f44f 62d3 mov.w r2, #1688 ; 0x698
8011ba2: 4912 ldr r1, [pc, #72] ; (8011bec <tcp_recv_null+0x64>)
8011ba4: 4812 ldr r0, [pc, #72] ; (8011bf0 <tcp_recv_null+0x68>)
8011ba6: f009 fa3d bl 801b024 <iprintf>
8011baa: f06f 030f mvn.w r3, #15
8011bae: e016 b.n 8011bde <tcp_recv_null+0x56>
if (p != NULL) {
8011bb0: 687b ldr r3, [r7, #4]
8011bb2: 2b00 cmp r3, #0
8011bb4: d009 beq.n 8011bca <tcp_recv_null+0x42>
tcp_recved(pcb, p->tot_len);
8011bb6: 687b ldr r3, [r7, #4]
8011bb8: 891b ldrh r3, [r3, #8]
8011bba: 4619 mov r1, r3
8011bbc: 68b8 ldr r0, [r7, #8]
8011bbe: f7ff fb1d bl 80111fc <tcp_recved>
pbuf_free(p);
8011bc2: 6878 ldr r0, [r7, #4]
8011bc4: f7fe fd18 bl 80105f8 <pbuf_free>
8011bc8: e008 b.n 8011bdc <tcp_recv_null+0x54>
} else if (err == ERR_OK) {
8011bca: f997 3003 ldrsb.w r3, [r7, #3]
8011bce: 2b00 cmp r3, #0
8011bd0: d104 bne.n 8011bdc <tcp_recv_null+0x54>
return tcp_close(pcb);
8011bd2: 68b8 ldr r0, [r7, #8]
8011bd4: f7ff f9c2 bl 8010f5c <tcp_close>
8011bd8: 4603 mov r3, r0
8011bda: e000 b.n 8011bde <tcp_recv_null+0x56>
}
return ERR_OK;
8011bdc: 2300 movs r3, #0
}
8011bde: 4618 mov r0, r3
8011be0: 3710 adds r7, #16
8011be2: 46bd mov sp, r7
8011be4: bd80 pop {r7, pc}
8011be6: bf00 nop
8011be8: 0801cb58 .word 0x0801cb58
8011bec: 0801d0c8 .word 0x0801d0c8
8011bf0: 0801cb9c .word 0x0801cb9c
08011bf4 <tcp_kill_prio>:
*
* @param prio minimum priority
*/
static void
tcp_kill_prio(u8_t prio)
{
8011bf4: b580 push {r7, lr}
8011bf6: b086 sub sp, #24
8011bf8: af00 add r7, sp, #0
8011bfa: 4603 mov r3, r0
8011bfc: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
u8_t mprio;
mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
8011bfe: f997 3007 ldrsb.w r3, [r7, #7]
8011c02: 2b00 cmp r3, #0
8011c04: db01 blt.n 8011c0a <tcp_kill_prio+0x16>
8011c06: 79fb ldrb r3, [r7, #7]
8011c08: e000 b.n 8011c0c <tcp_kill_prio+0x18>
8011c0a: 237f movs r3, #127 ; 0x7f
8011c0c: 72fb strb r3, [r7, #11]
/* We want to kill connections with a lower prio, so bail out if
* supplied prio is 0 - there can never be a lower prio
*/
if (mprio == 0) {
8011c0e: 7afb ldrb r3, [r7, #11]
8011c10: 2b00 cmp r3, #0
8011c12: d034 beq.n 8011c7e <tcp_kill_prio+0x8a>
/* We only want kill connections with a lower prio, so decrement prio by one
* and start searching for oldest connection with same or lower priority than mprio.
* We want to find the connections with the lowest possible prio, and among
* these the one with the longest inactivity time.
*/
mprio--;
8011c14: 7afb ldrb r3, [r7, #11]
8011c16: 3b01 subs r3, #1
8011c18: 72fb strb r3, [r7, #11]
inactivity = 0;
8011c1a: 2300 movs r3, #0
8011c1c: 60fb str r3, [r7, #12]
inactive = NULL;
8011c1e: 2300 movs r3, #0
8011c20: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c22: 4b19 ldr r3, [pc, #100] ; (8011c88 <tcp_kill_prio+0x94>)
8011c24: 681b ldr r3, [r3, #0]
8011c26: 617b str r3, [r7, #20]
8011c28: e01f b.n 8011c6a <tcp_kill_prio+0x76>
/* lower prio is always a kill candidate */
if ((pcb->prio < mprio) ||
8011c2a: 697b ldr r3, [r7, #20]
8011c2c: 7d5b ldrb r3, [r3, #21]
8011c2e: 7afa ldrb r2, [r7, #11]
8011c30: 429a cmp r2, r3
8011c32: d80c bhi.n 8011c4e <tcp_kill_prio+0x5a>
/* longer inactivity is also a kill candidate */
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c34: 697b ldr r3, [r7, #20]
8011c36: 7d5b ldrb r3, [r3, #21]
if ((pcb->prio < mprio) ||
8011c38: 7afa ldrb r2, [r7, #11]
8011c3a: 429a cmp r2, r3
8011c3c: d112 bne.n 8011c64 <tcp_kill_prio+0x70>
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
8011c3e: 4b13 ldr r3, [pc, #76] ; (8011c8c <tcp_kill_prio+0x98>)
8011c40: 681a ldr r2, [r3, #0]
8011c42: 697b ldr r3, [r7, #20]
8011c44: 6a1b ldr r3, [r3, #32]
8011c46: 1ad3 subs r3, r2, r3
8011c48: 68fa ldr r2, [r7, #12]
8011c4a: 429a cmp r2, r3
8011c4c: d80a bhi.n 8011c64 <tcp_kill_prio+0x70>
inactivity = tcp_ticks - pcb->tmr;
8011c4e: 4b0f ldr r3, [pc, #60] ; (8011c8c <tcp_kill_prio+0x98>)
8011c50: 681a ldr r2, [r3, #0]
8011c52: 697b ldr r3, [r7, #20]
8011c54: 6a1b ldr r3, [r3, #32]
8011c56: 1ad3 subs r3, r2, r3
8011c58: 60fb str r3, [r7, #12]
inactive = pcb;
8011c5a: 697b ldr r3, [r7, #20]
8011c5c: 613b str r3, [r7, #16]
mprio = pcb->prio;
8011c5e: 697b ldr r3, [r7, #20]
8011c60: 7d5b ldrb r3, [r3, #21]
8011c62: 72fb strb r3, [r7, #11]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011c64: 697b ldr r3, [r7, #20]
8011c66: 68db ldr r3, [r3, #12]
8011c68: 617b str r3, [r7, #20]
8011c6a: 697b ldr r3, [r7, #20]
8011c6c: 2b00 cmp r3, #0
8011c6e: d1dc bne.n 8011c2a <tcp_kill_prio+0x36>
}
}
if (inactive != NULL) {
8011c70: 693b ldr r3, [r7, #16]
8011c72: 2b00 cmp r3, #0
8011c74: d004 beq.n 8011c80 <tcp_kill_prio+0x8c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011c76: 6938 ldr r0, [r7, #16]
8011c78: f7ff fa5a bl 8011130 <tcp_abort>
8011c7c: e000 b.n 8011c80 <tcp_kill_prio+0x8c>
return;
8011c7e: bf00 nop
}
}
8011c80: 3718 adds r7, #24
8011c82: 46bd mov sp, r7
8011c84: bd80 pop {r7, pc}
8011c86: bf00 nop
8011c88: 2000f5c0 .word 0x2000f5c0
8011c8c: 2000f5c4 .word 0x2000f5c4
08011c90 <tcp_kill_state>:
* Kills the oldest connection that is in specific state.
* Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
*/
static void
tcp_kill_state(enum tcp_state state)
{
8011c90: b580 push {r7, lr}
8011c92: b086 sub sp, #24
8011c94: af00 add r7, sp, #0
8011c96: 4603 mov r3, r0
8011c98: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
8011c9a: 79fb ldrb r3, [r7, #7]
8011c9c: 2b08 cmp r3, #8
8011c9e: d009 beq.n 8011cb4 <tcp_kill_state+0x24>
8011ca0: 79fb ldrb r3, [r7, #7]
8011ca2: 2b09 cmp r3, #9
8011ca4: d006 beq.n 8011cb4 <tcp_kill_state+0x24>
8011ca6: 4b1a ldr r3, [pc, #104] ; (8011d10 <tcp_kill_state+0x80>)
8011ca8: f240 62dd movw r2, #1757 ; 0x6dd
8011cac: 4919 ldr r1, [pc, #100] ; (8011d14 <tcp_kill_state+0x84>)
8011cae: 481a ldr r0, [pc, #104] ; (8011d18 <tcp_kill_state+0x88>)
8011cb0: f009 f9b8 bl 801b024 <iprintf>
inactivity = 0;
8011cb4: 2300 movs r3, #0
8011cb6: 60fb str r3, [r7, #12]
inactive = NULL;
8011cb8: 2300 movs r3, #0
8011cba: 613b str r3, [r7, #16]
/* Go through the list of active pcbs and get the oldest pcb that is in state
CLOSING/LAST_ACK. */
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011cbc: 4b17 ldr r3, [pc, #92] ; (8011d1c <tcp_kill_state+0x8c>)
8011cbe: 681b ldr r3, [r3, #0]
8011cc0: 617b str r3, [r7, #20]
8011cc2: e017 b.n 8011cf4 <tcp_kill_state+0x64>
if (pcb->state == state) {
8011cc4: 697b ldr r3, [r7, #20]
8011cc6: 7d1b ldrb r3, [r3, #20]
8011cc8: 79fa ldrb r2, [r7, #7]
8011cca: 429a cmp r2, r3
8011ccc: d10f bne.n 8011cee <tcp_kill_state+0x5e>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011cce: 4b14 ldr r3, [pc, #80] ; (8011d20 <tcp_kill_state+0x90>)
8011cd0: 681a ldr r2, [r3, #0]
8011cd2: 697b ldr r3, [r7, #20]
8011cd4: 6a1b ldr r3, [r3, #32]
8011cd6: 1ad3 subs r3, r2, r3
8011cd8: 68fa ldr r2, [r7, #12]
8011cda: 429a cmp r2, r3
8011cdc: d807 bhi.n 8011cee <tcp_kill_state+0x5e>
inactivity = tcp_ticks - pcb->tmr;
8011cde: 4b10 ldr r3, [pc, #64] ; (8011d20 <tcp_kill_state+0x90>)
8011ce0: 681a ldr r2, [r3, #0]
8011ce2: 697b ldr r3, [r7, #20]
8011ce4: 6a1b ldr r3, [r3, #32]
8011ce6: 1ad3 subs r3, r2, r3
8011ce8: 60fb str r3, [r7, #12]
inactive = pcb;
8011cea: 697b ldr r3, [r7, #20]
8011cec: 613b str r3, [r7, #16]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8011cee: 697b ldr r3, [r7, #20]
8011cf0: 68db ldr r3, [r3, #12]
8011cf2: 617b str r3, [r7, #20]
8011cf4: 697b ldr r3, [r7, #20]
8011cf6: 2b00 cmp r3, #0
8011cf8: d1e4 bne.n 8011cc4 <tcp_kill_state+0x34>
}
}
}
if (inactive != NULL) {
8011cfa: 693b ldr r3, [r7, #16]
8011cfc: 2b00 cmp r3, #0
8011cfe: d003 beq.n 8011d08 <tcp_kill_state+0x78>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
tcp_state_str[state], (void *)inactive, inactivity));
/* Don't send a RST, since no data is lost. */
tcp_abandon(inactive, 0);
8011d00: 2100 movs r1, #0
8011d02: 6938 ldr r0, [r7, #16]
8011d04: f7ff f956 bl 8010fb4 <tcp_abandon>
}
}
8011d08: bf00 nop
8011d0a: 3718 adds r7, #24
8011d0c: 46bd mov sp, r7
8011d0e: bd80 pop {r7, pc}
8011d10: 0801cb58 .word 0x0801cb58
8011d14: 0801d0e4 .word 0x0801d0e4
8011d18: 0801cb9c .word 0x0801cb9c
8011d1c: 2000f5c0 .word 0x2000f5c0
8011d20: 2000f5c4 .word 0x2000f5c4
08011d24 <tcp_kill_timewait>:
* Kills the oldest connection that is in TIME_WAIT state.
* Called from tcp_alloc() if no more connections are available.
*/
static void
tcp_kill_timewait(void)
{
8011d24: b580 push {r7, lr}
8011d26: b084 sub sp, #16
8011d28: af00 add r7, sp, #0
struct tcp_pcb *pcb, *inactive;
u32_t inactivity;
inactivity = 0;
8011d2a: 2300 movs r3, #0
8011d2c: 607b str r3, [r7, #4]
inactive = NULL;
8011d2e: 2300 movs r3, #0
8011d30: 60bb str r3, [r7, #8]
/* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011d32: 4b12 ldr r3, [pc, #72] ; (8011d7c <tcp_kill_timewait+0x58>)
8011d34: 681b ldr r3, [r3, #0]
8011d36: 60fb str r3, [r7, #12]
8011d38: e012 b.n 8011d60 <tcp_kill_timewait+0x3c>
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
8011d3a: 4b11 ldr r3, [pc, #68] ; (8011d80 <tcp_kill_timewait+0x5c>)
8011d3c: 681a ldr r2, [r3, #0]
8011d3e: 68fb ldr r3, [r7, #12]
8011d40: 6a1b ldr r3, [r3, #32]
8011d42: 1ad3 subs r3, r2, r3
8011d44: 687a ldr r2, [r7, #4]
8011d46: 429a cmp r2, r3
8011d48: d807 bhi.n 8011d5a <tcp_kill_timewait+0x36>
inactivity = tcp_ticks - pcb->tmr;
8011d4a: 4b0d ldr r3, [pc, #52] ; (8011d80 <tcp_kill_timewait+0x5c>)
8011d4c: 681a ldr r2, [r3, #0]
8011d4e: 68fb ldr r3, [r7, #12]
8011d50: 6a1b ldr r3, [r3, #32]
8011d52: 1ad3 subs r3, r2, r3
8011d54: 607b str r3, [r7, #4]
inactive = pcb;
8011d56: 68fb ldr r3, [r7, #12]
8011d58: 60bb str r3, [r7, #8]
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
8011d5a: 68fb ldr r3, [r7, #12]
8011d5c: 68db ldr r3, [r3, #12]
8011d5e: 60fb str r3, [r7, #12]
8011d60: 68fb ldr r3, [r7, #12]
8011d62: 2b00 cmp r3, #0
8011d64: d1e9 bne.n 8011d3a <tcp_kill_timewait+0x16>
}
}
if (inactive != NULL) {
8011d66: 68bb ldr r3, [r7, #8]
8011d68: 2b00 cmp r3, #0
8011d6a: d002 beq.n 8011d72 <tcp_kill_timewait+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
(void *)inactive, inactivity));
tcp_abort(inactive);
8011d6c: 68b8 ldr r0, [r7, #8]
8011d6e: f7ff f9df bl 8011130 <tcp_abort>
}
}
8011d72: bf00 nop
8011d74: 3710 adds r7, #16
8011d76: 46bd mov sp, r7
8011d78: bd80 pop {r7, pc}
8011d7a: bf00 nop
8011d7c: 2000f5d0 .word 0x2000f5d0
8011d80: 2000f5c4 .word 0x2000f5c4
08011d84 <tcp_handle_closepend>:
* now send the FIN (which failed before), the pcb might be in a state that is
* OK for us to now free it.
*/
static void
tcp_handle_closepend(void)
{
8011d84: b580 push {r7, lr}
8011d86: b082 sub sp, #8
8011d88: af00 add r7, sp, #0
struct tcp_pcb *pcb = tcp_active_pcbs;
8011d8a: 4b10 ldr r3, [pc, #64] ; (8011dcc <tcp_handle_closepend+0x48>)
8011d8c: 681b ldr r3, [r3, #0]
8011d8e: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011d90: e014 b.n 8011dbc <tcp_handle_closepend+0x38>
struct tcp_pcb *next = pcb->next;
8011d92: 687b ldr r3, [r7, #4]
8011d94: 68db ldr r3, [r3, #12]
8011d96: 603b str r3, [r7, #0]
/* send pending FIN */
if (pcb->flags & TF_CLOSEPEND) {
8011d98: 687b ldr r3, [r7, #4]
8011d9a: 8b5b ldrh r3, [r3, #26]
8011d9c: f003 0308 and.w r3, r3, #8
8011da0: 2b00 cmp r3, #0
8011da2: d009 beq.n 8011db8 <tcp_handle_closepend+0x34>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
tcp_clear_flags(pcb, TF_CLOSEPEND);
8011da4: 687b ldr r3, [r7, #4]
8011da6: 8b5b ldrh r3, [r3, #26]
8011da8: f023 0308 bic.w r3, r3, #8
8011dac: b29a uxth r2, r3
8011dae: 687b ldr r3, [r7, #4]
8011db0: 835a strh r2, [r3, #26]
tcp_close_shutdown_fin(pcb);
8011db2: 6878 ldr r0, [r7, #4]
8011db4: f7ff f86c bl 8010e90 <tcp_close_shutdown_fin>
}
pcb = next;
8011db8: 683b ldr r3, [r7, #0]
8011dba: 607b str r3, [r7, #4]
while (pcb != NULL) {
8011dbc: 687b ldr r3, [r7, #4]
8011dbe: 2b00 cmp r3, #0
8011dc0: d1e7 bne.n 8011d92 <tcp_handle_closepend+0xe>
}
}
8011dc2: bf00 nop
8011dc4: 3708 adds r7, #8
8011dc6: 46bd mov sp, r7
8011dc8: bd80 pop {r7, pc}
8011dca: bf00 nop
8011dcc: 2000f5c0 .word 0x2000f5c0
08011dd0 <tcp_alloc>:
* @param prio priority for the new pcb
* @return a new tcp_pcb that initially is in state CLOSED
*/
struct tcp_pcb *
tcp_alloc(u8_t prio)
{
8011dd0: b580 push {r7, lr}
8011dd2: b084 sub sp, #16
8011dd4: af00 add r7, sp, #0
8011dd6: 4603 mov r3, r0
8011dd8: 71fb strb r3, [r7, #7]
struct tcp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011dda: 2001 movs r0, #1
8011ddc: f7fd fd0e bl 800f7fc <memp_malloc>
8011de0: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011de2: 68fb ldr r3, [r7, #12]
8011de4: 2b00 cmp r3, #0
8011de6: d126 bne.n 8011e36 <tcp_alloc+0x66>
/* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
tcp_handle_closepend();
8011de8: f7ff ffcc bl 8011d84 <tcp_handle_closepend>
/* Try killing oldest connection in TIME-WAIT. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
tcp_kill_timewait();
8011dec: f7ff ff9a bl 8011d24 <tcp_kill_timewait>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011df0: 2001 movs r0, #1
8011df2: f7fd fd03 bl 800f7fc <memp_malloc>
8011df6: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011df8: 68fb ldr r3, [r7, #12]
8011dfa: 2b00 cmp r3, #0
8011dfc: d11b bne.n 8011e36 <tcp_alloc+0x66>
/* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
tcp_kill_state(LAST_ACK);
8011dfe: 2009 movs r0, #9
8011e00: f7ff ff46 bl 8011c90 <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011e04: 2001 movs r0, #1
8011e06: f7fd fcf9 bl 800f7fc <memp_malloc>
8011e0a: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011e0c: 68fb ldr r3, [r7, #12]
8011e0e: 2b00 cmp r3, #0
8011e10: d111 bne.n 8011e36 <tcp_alloc+0x66>
/* Try killing oldest connection in CLOSING. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
tcp_kill_state(CLOSING);
8011e12: 2008 movs r0, #8
8011e14: f7ff ff3c bl 8011c90 <tcp_kill_state>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011e18: 2001 movs r0, #1
8011e1a: f7fd fcef bl 800f7fc <memp_malloc>
8011e1e: 60f8 str r0, [r7, #12]
if (pcb == NULL) {
8011e20: 68fb ldr r3, [r7, #12]
8011e22: 2b00 cmp r3, #0
8011e24: d107 bne.n 8011e36 <tcp_alloc+0x66>
/* Try killing oldest active connection with lower priority than the new one. */
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
tcp_kill_prio(prio);
8011e26: 79fb ldrb r3, [r7, #7]
8011e28: 4618 mov r0, r3
8011e2a: f7ff fee3 bl 8011bf4 <tcp_kill_prio>
/* Try to allocate a tcp_pcb again. */
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
8011e2e: 2001 movs r0, #1
8011e30: f7fd fce4 bl 800f7fc <memp_malloc>
8011e34: 60f8 str r0, [r7, #12]
if (pcb != NULL) {
/* adjust err stats: memp_malloc failed above */
MEMP_STATS_DEC(err, MEMP_TCP_PCB);
}
}
if (pcb != NULL) {
8011e36: 68fb ldr r3, [r7, #12]
8011e38: 2b00 cmp r3, #0
8011e3a: d03f beq.n 8011ebc <tcp_alloc+0xec>
/* zero out the whole pcb, so there is no need to initialize members to zero */
memset(pcb, 0, sizeof(struct tcp_pcb));
8011e3c: 229c movs r2, #156 ; 0x9c
8011e3e: 2100 movs r1, #0
8011e40: 68f8 ldr r0, [r7, #12]
8011e42: f009 f8e7 bl 801b014 <memset>
pcb->prio = prio;
8011e46: 68fb ldr r3, [r7, #12]
8011e48: 79fa ldrb r2, [r7, #7]
8011e4a: 755a strb r2, [r3, #21]
pcb->snd_buf = TCP_SND_BUF;
8011e4c: 68fb ldr r3, [r7, #12]
8011e4e: f44f 6286 mov.w r2, #1072 ; 0x430
8011e52: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* Start with a window that does not need scaling. When window scaling is
enabled and used, the window is enlarged when both sides agree on scaling. */
pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
8011e56: 68fb ldr r3, [r7, #12]
8011e58: f44f 6206 mov.w r2, #2144 ; 0x860
8011e5c: 855a strh r2, [r3, #42] ; 0x2a
8011e5e: 68fb ldr r3, [r7, #12]
8011e60: 8d5a ldrh r2, [r3, #42] ; 0x2a
8011e62: 68fb ldr r3, [r7, #12]
8011e64: 851a strh r2, [r3, #40] ; 0x28
pcb->ttl = TCP_TTL;
8011e66: 68fb ldr r3, [r7, #12]
8011e68: 22ff movs r2, #255 ; 0xff
8011e6a: 72da strb r2, [r3, #11]
/* As initial send MSS, we use TCP_MSS but limit it to 536.
The send MSS is updated when an MSS option is received. */
pcb->mss = INITIAL_MSS;
8011e6c: 68fb ldr r3, [r7, #12]
8011e6e: f44f 7206 mov.w r2, #536 ; 0x218
8011e72: 865a strh r2, [r3, #50] ; 0x32
pcb->rto = 3000 / TCP_SLOW_INTERVAL;
8011e74: 68fb ldr r3, [r7, #12]
8011e76: 2206 movs r2, #6
8011e78: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
pcb->sv = 3000 / TCP_SLOW_INTERVAL;
8011e7c: 68fb ldr r3, [r7, #12]
8011e7e: 2206 movs r2, #6
8011e80: 87da strh r2, [r3, #62] ; 0x3e
pcb->rtime = -1;
8011e82: 68fb ldr r3, [r7, #12]
8011e84: f64f 72ff movw r2, #65535 ; 0xffff
8011e88: 861a strh r2, [r3, #48] ; 0x30
pcb->cwnd = 1;
8011e8a: 68fb ldr r3, [r7, #12]
8011e8c: 2201 movs r2, #1
8011e8e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->tmr = tcp_ticks;
8011e92: 4b0d ldr r3, [pc, #52] ; (8011ec8 <tcp_alloc+0xf8>)
8011e94: 681a ldr r2, [r3, #0]
8011e96: 68fb ldr r3, [r7, #12]
8011e98: 621a str r2, [r3, #32]
pcb->last_timer = tcp_timer_ctr;
8011e9a: 4b0c ldr r3, [pc, #48] ; (8011ecc <tcp_alloc+0xfc>)
8011e9c: 781a ldrb r2, [r3, #0]
8011e9e: 68fb ldr r3, [r7, #12]
8011ea0: 779a strb r2, [r3, #30]
of using the largest advertised receive window. We've seen complications with
receiving TCPs that use window scaling and/or window auto-tuning where the
initial advertised window is very small and then grows rapidly once the
connection is established. To avoid these complications, we set ssthresh to the
largest effective cwnd (amount of in-flight data) that the sender can have. */
pcb->ssthresh = TCP_SND_BUF;
8011ea2: 68fb ldr r3, [r7, #12]
8011ea4: f44f 6286 mov.w r2, #1072 ; 0x430
8011ea8: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
#if LWIP_CALLBACK_API
pcb->recv = tcp_recv_null;
8011eac: 68fb ldr r3, [r7, #12]
8011eae: 4a08 ldr r2, [pc, #32] ; (8011ed0 <tcp_alloc+0x100>)
8011eb0: f8c3 2084 str.w r2, [r3, #132] ; 0x84
#endif /* LWIP_CALLBACK_API */
/* Init KEEPALIVE timer */
pcb->keep_idle = TCP_KEEPIDLE_DEFAULT;
8011eb4: 68fb ldr r3, [r7, #12]
8011eb6: 4a07 ldr r2, [pc, #28] ; (8011ed4 <tcp_alloc+0x104>)
8011eb8: f8c3 2094 str.w r2, [r3, #148] ; 0x94
#if LWIP_TCP_KEEPALIVE
pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
pcb->keep_cnt = TCP_KEEPCNT_DEFAULT;
#endif /* LWIP_TCP_KEEPALIVE */
}
return pcb;
8011ebc: 68fb ldr r3, [r7, #12]
}
8011ebe: 4618 mov r0, r3
8011ec0: 3710 adds r7, #16
8011ec2: 46bd mov sp, r7
8011ec4: bd80 pop {r7, pc}
8011ec6: bf00 nop
8011ec8: 2000f5c4 .word 0x2000f5c4
8011ecc: 2000872a .word 0x2000872a
8011ed0: 08011b89 .word 0x08011b89
8011ed4: 006ddd00 .word 0x006ddd00
08011ed8 <tcp_pcb_purge>:
*
* @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
*/
void
tcp_pcb_purge(struct tcp_pcb *pcb)
{
8011ed8: b580 push {r7, lr}
8011eda: b082 sub sp, #8
8011edc: af00 add r7, sp, #0
8011ede: 6078 str r0, [r7, #4]
LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
8011ee0: 687b ldr r3, [r7, #4]
8011ee2: 2b00 cmp r3, #0
8011ee4: d107 bne.n 8011ef6 <tcp_pcb_purge+0x1e>
8011ee6: 4b21 ldr r3, [pc, #132] ; (8011f6c <tcp_pcb_purge+0x94>)
8011ee8: f640 0251 movw r2, #2129 ; 0x851
8011eec: 4920 ldr r1, [pc, #128] ; (8011f70 <tcp_pcb_purge+0x98>)
8011eee: 4821 ldr r0, [pc, #132] ; (8011f74 <tcp_pcb_purge+0x9c>)
8011ef0: f009 f898 bl 801b024 <iprintf>
8011ef4: e037 b.n 8011f66 <tcp_pcb_purge+0x8e>
if (pcb->state != CLOSED &&
8011ef6: 687b ldr r3, [r7, #4]
8011ef8: 7d1b ldrb r3, [r3, #20]
8011efa: 2b00 cmp r3, #0
8011efc: d033 beq.n 8011f66 <tcp_pcb_purge+0x8e>
pcb->state != TIME_WAIT &&
8011efe: 687b ldr r3, [r7, #4]
8011f00: 7d1b ldrb r3, [r3, #20]
if (pcb->state != CLOSED &&
8011f02: 2b0a cmp r3, #10
8011f04: d02f beq.n 8011f66 <tcp_pcb_purge+0x8e>
pcb->state != LISTEN) {
8011f06: 687b ldr r3, [r7, #4]
8011f08: 7d1b ldrb r3, [r3, #20]
pcb->state != TIME_WAIT &&
8011f0a: 2b01 cmp r3, #1
8011f0c: d02b beq.n 8011f66 <tcp_pcb_purge+0x8e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
tcp_backlog_accepted(pcb);
if (pcb->refused_data != NULL) {
8011f0e: 687b ldr r3, [r7, #4]
8011f10: 6f9b ldr r3, [r3, #120] ; 0x78
8011f12: 2b00 cmp r3, #0
8011f14: d007 beq.n 8011f26 <tcp_pcb_purge+0x4e>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
pbuf_free(pcb->refused_data);
8011f16: 687b ldr r3, [r7, #4]
8011f18: 6f9b ldr r3, [r3, #120] ; 0x78
8011f1a: 4618 mov r0, r3
8011f1c: f7fe fb6c bl 80105f8 <pbuf_free>
pcb->refused_data = NULL;
8011f20: 687b ldr r3, [r7, #4]
8011f22: 2200 movs r2, #0
8011f24: 679a str r2, [r3, #120] ; 0x78
}
if (pcb->unacked != NULL) {
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
}
#if TCP_QUEUE_OOSEQ
if (pcb->ooseq != NULL) {
8011f26: 687b ldr r3, [r7, #4]
8011f28: 6f5b ldr r3, [r3, #116] ; 0x74
8011f2a: 2b00 cmp r3, #0
8011f2c: d002 beq.n 8011f34 <tcp_pcb_purge+0x5c>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
tcp_free_ooseq(pcb);
8011f2e: 6878 ldr r0, [r7, #4]
8011f30: f000 f986 bl 8012240 <tcp_free_ooseq>
}
#endif /* TCP_QUEUE_OOSEQ */
/* Stop the retransmission timer as it will expect data on unacked
queue if it fires */
pcb->rtime = -1;
8011f34: 687b ldr r3, [r7, #4]
8011f36: f64f 72ff movw r2, #65535 ; 0xffff
8011f3a: 861a strh r2, [r3, #48] ; 0x30
tcp_segs_free(pcb->unsent);
8011f3c: 687b ldr r3, [r7, #4]
8011f3e: 6edb ldr r3, [r3, #108] ; 0x6c
8011f40: 4618 mov r0, r3
8011f42: f7ff fdc9 bl 8011ad8 <tcp_segs_free>
tcp_segs_free(pcb->unacked);
8011f46: 687b ldr r3, [r7, #4]
8011f48: 6f1b ldr r3, [r3, #112] ; 0x70
8011f4a: 4618 mov r0, r3
8011f4c: f7ff fdc4 bl 8011ad8 <tcp_segs_free>
pcb->unacked = pcb->unsent = NULL;
8011f50: 687b ldr r3, [r7, #4]
8011f52: 2200 movs r2, #0
8011f54: 66da str r2, [r3, #108] ; 0x6c
8011f56: 687b ldr r3, [r7, #4]
8011f58: 6eda ldr r2, [r3, #108] ; 0x6c
8011f5a: 687b ldr r3, [r7, #4]
8011f5c: 671a str r2, [r3, #112] ; 0x70
#if TCP_OVERSIZE
pcb->unsent_oversize = 0;
8011f5e: 687b ldr r3, [r7, #4]
8011f60: 2200 movs r2, #0
8011f62: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
}
}
8011f66: 3708 adds r7, #8
8011f68: 46bd mov sp, r7
8011f6a: bd80 pop {r7, pc}
8011f6c: 0801cb58 .word 0x0801cb58
8011f70: 0801d1a4 .word 0x0801d1a4
8011f74: 0801cb9c .word 0x0801cb9c
08011f78 <tcp_pcb_remove>:
* @param pcblist PCB list to purge.
* @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
*/
void
tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
{
8011f78: b580 push {r7, lr}
8011f7a: b084 sub sp, #16
8011f7c: af00 add r7, sp, #0
8011f7e: 6078 str r0, [r7, #4]
8011f80: 6039 str r1, [r7, #0]
LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
8011f82: 683b ldr r3, [r7, #0]
8011f84: 2b00 cmp r3, #0
8011f86: d106 bne.n 8011f96 <tcp_pcb_remove+0x1e>
8011f88: 4b3e ldr r3, [pc, #248] ; (8012084 <tcp_pcb_remove+0x10c>)
8011f8a: f640 0283 movw r2, #2179 ; 0x883
8011f8e: 493e ldr r1, [pc, #248] ; (8012088 <tcp_pcb_remove+0x110>)
8011f90: 483e ldr r0, [pc, #248] ; (801208c <tcp_pcb_remove+0x114>)
8011f92: f009 f847 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
8011f96: 687b ldr r3, [r7, #4]
8011f98: 2b00 cmp r3, #0
8011f9a: d106 bne.n 8011faa <tcp_pcb_remove+0x32>
8011f9c: 4b39 ldr r3, [pc, #228] ; (8012084 <tcp_pcb_remove+0x10c>)
8011f9e: f640 0284 movw r2, #2180 ; 0x884
8011fa2: 493b ldr r1, [pc, #236] ; (8012090 <tcp_pcb_remove+0x118>)
8011fa4: 4839 ldr r0, [pc, #228] ; (801208c <tcp_pcb_remove+0x114>)
8011fa6: f009 f83d bl 801b024 <iprintf>
TCP_RMV(pcblist, pcb);
8011faa: 687b ldr r3, [r7, #4]
8011fac: 681b ldr r3, [r3, #0]
8011fae: 683a ldr r2, [r7, #0]
8011fb0: 429a cmp r2, r3
8011fb2: d105 bne.n 8011fc0 <tcp_pcb_remove+0x48>
8011fb4: 687b ldr r3, [r7, #4]
8011fb6: 681b ldr r3, [r3, #0]
8011fb8: 68da ldr r2, [r3, #12]
8011fba: 687b ldr r3, [r7, #4]
8011fbc: 601a str r2, [r3, #0]
8011fbe: e013 b.n 8011fe8 <tcp_pcb_remove+0x70>
8011fc0: 687b ldr r3, [r7, #4]
8011fc2: 681b ldr r3, [r3, #0]
8011fc4: 60fb str r3, [r7, #12]
8011fc6: e00c b.n 8011fe2 <tcp_pcb_remove+0x6a>
8011fc8: 68fb ldr r3, [r7, #12]
8011fca: 68db ldr r3, [r3, #12]
8011fcc: 683a ldr r2, [r7, #0]
8011fce: 429a cmp r2, r3
8011fd0: d104 bne.n 8011fdc <tcp_pcb_remove+0x64>
8011fd2: 683b ldr r3, [r7, #0]
8011fd4: 68da ldr r2, [r3, #12]
8011fd6: 68fb ldr r3, [r7, #12]
8011fd8: 60da str r2, [r3, #12]
8011fda: e005 b.n 8011fe8 <tcp_pcb_remove+0x70>
8011fdc: 68fb ldr r3, [r7, #12]
8011fde: 68db ldr r3, [r3, #12]
8011fe0: 60fb str r3, [r7, #12]
8011fe2: 68fb ldr r3, [r7, #12]
8011fe4: 2b00 cmp r3, #0
8011fe6: d1ef bne.n 8011fc8 <tcp_pcb_remove+0x50>
8011fe8: 683b ldr r3, [r7, #0]
8011fea: 2200 movs r2, #0
8011fec: 60da str r2, [r3, #12]
tcp_pcb_purge(pcb);
8011fee: 6838 ldr r0, [r7, #0]
8011ff0: f7ff ff72 bl 8011ed8 <tcp_pcb_purge>
/* if there is an outstanding delayed ACKs, send it */
if ((pcb->state != TIME_WAIT) &&
8011ff4: 683b ldr r3, [r7, #0]
8011ff6: 7d1b ldrb r3, [r3, #20]
8011ff8: 2b0a cmp r3, #10
8011ffa: d013 beq.n 8012024 <tcp_pcb_remove+0xac>
(pcb->state != LISTEN) &&
8011ffc: 683b ldr r3, [r7, #0]
8011ffe: 7d1b ldrb r3, [r3, #20]
if ((pcb->state != TIME_WAIT) &&
8012000: 2b01 cmp r3, #1
8012002: d00f beq.n 8012024 <tcp_pcb_remove+0xac>
(pcb->flags & TF_ACK_DELAY)) {
8012004: 683b ldr r3, [r7, #0]
8012006: 8b5b ldrh r3, [r3, #26]
8012008: f003 0301 and.w r3, r3, #1
(pcb->state != LISTEN) &&
801200c: 2b00 cmp r3, #0
801200e: d009 beq.n 8012024 <tcp_pcb_remove+0xac>
tcp_ack_now(pcb);
8012010: 683b ldr r3, [r7, #0]
8012012: 8b5b ldrh r3, [r3, #26]
8012014: f043 0302 orr.w r3, r3, #2
8012018: b29a uxth r2, r3
801201a: 683b ldr r3, [r7, #0]
801201c: 835a strh r2, [r3, #26]
tcp_output(pcb);
801201e: 6838 ldr r0, [r7, #0]
8012020: f002 ff68 bl 8014ef4 <tcp_output>
}
if (pcb->state != LISTEN) {
8012024: 683b ldr r3, [r7, #0]
8012026: 7d1b ldrb r3, [r3, #20]
8012028: 2b01 cmp r3, #1
801202a: d020 beq.n 801206e <tcp_pcb_remove+0xf6>
LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
801202c: 683b ldr r3, [r7, #0]
801202e: 6edb ldr r3, [r3, #108] ; 0x6c
8012030: 2b00 cmp r3, #0
8012032: d006 beq.n 8012042 <tcp_pcb_remove+0xca>
8012034: 4b13 ldr r3, [pc, #76] ; (8012084 <tcp_pcb_remove+0x10c>)
8012036: f640 0293 movw r2, #2195 ; 0x893
801203a: 4916 ldr r1, [pc, #88] ; (8012094 <tcp_pcb_remove+0x11c>)
801203c: 4813 ldr r0, [pc, #76] ; (801208c <tcp_pcb_remove+0x114>)
801203e: f008 fff1 bl 801b024 <iprintf>
LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
8012042: 683b ldr r3, [r7, #0]
8012044: 6f1b ldr r3, [r3, #112] ; 0x70
8012046: 2b00 cmp r3, #0
8012048: d006 beq.n 8012058 <tcp_pcb_remove+0xe0>
801204a: 4b0e ldr r3, [pc, #56] ; (8012084 <tcp_pcb_remove+0x10c>)
801204c: f640 0294 movw r2, #2196 ; 0x894
8012050: 4911 ldr r1, [pc, #68] ; (8012098 <tcp_pcb_remove+0x120>)
8012052: 480e ldr r0, [pc, #56] ; (801208c <tcp_pcb_remove+0x114>)
8012054: f008 ffe6 bl 801b024 <iprintf>
#if TCP_QUEUE_OOSEQ
LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
8012058: 683b ldr r3, [r7, #0]
801205a: 6f5b ldr r3, [r3, #116] ; 0x74
801205c: 2b00 cmp r3, #0
801205e: d006 beq.n 801206e <tcp_pcb_remove+0xf6>
8012060: 4b08 ldr r3, [pc, #32] ; (8012084 <tcp_pcb_remove+0x10c>)
8012062: f640 0296 movw r2, #2198 ; 0x896
8012066: 490d ldr r1, [pc, #52] ; (801209c <tcp_pcb_remove+0x124>)
8012068: 4808 ldr r0, [pc, #32] ; (801208c <tcp_pcb_remove+0x114>)
801206a: f008 ffdb bl 801b024 <iprintf>
#endif /* TCP_QUEUE_OOSEQ */
}
pcb->state = CLOSED;
801206e: 683b ldr r3, [r7, #0]
8012070: 2200 movs r2, #0
8012072: 751a strb r2, [r3, #20]
/* reset the local port to prevent the pcb from being 'bound' */
pcb->local_port = 0;
8012074: 683b ldr r3, [r7, #0]
8012076: 2200 movs r2, #0
8012078: 82da strh r2, [r3, #22]
LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
}
801207a: bf00 nop
801207c: 3710 adds r7, #16
801207e: 46bd mov sp, r7
8012080: bd80 pop {r7, pc}
8012082: bf00 nop
8012084: 0801cb58 .word 0x0801cb58
8012088: 0801d1c0 .word 0x0801d1c0
801208c: 0801cb9c .word 0x0801cb9c
8012090: 0801d1dc .word 0x0801d1dc
8012094: 0801d1fc .word 0x0801d1fc
8012098: 0801d214 .word 0x0801d214
801209c: 0801d230 .word 0x0801d230
080120a0 <tcp_next_iss>:
*
* @return u32_t pseudo random sequence number
*/
u32_t
tcp_next_iss(struct tcp_pcb *pcb)
{
80120a0: b580 push {r7, lr}
80120a2: b082 sub sp, #8
80120a4: af00 add r7, sp, #0
80120a6: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
#else /* LWIP_HOOK_TCP_ISN */
static u32_t iss = 6510;
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
80120a8: 687b ldr r3, [r7, #4]
80120aa: 2b00 cmp r3, #0
80120ac: d106 bne.n 80120bc <tcp_next_iss+0x1c>
80120ae: 4b0a ldr r3, [pc, #40] ; (80120d8 <tcp_next_iss+0x38>)
80120b0: f640 02af movw r2, #2223 ; 0x8af
80120b4: 4909 ldr r1, [pc, #36] ; (80120dc <tcp_next_iss+0x3c>)
80120b6: 480a ldr r0, [pc, #40] ; (80120e0 <tcp_next_iss+0x40>)
80120b8: f008 ffb4 bl 801b024 <iprintf>
LWIP_UNUSED_ARG(pcb);
iss += tcp_ticks; /* XXX */
80120bc: 4b09 ldr r3, [pc, #36] ; (80120e4 <tcp_next_iss+0x44>)
80120be: 681a ldr r2, [r3, #0]
80120c0: 4b09 ldr r3, [pc, #36] ; (80120e8 <tcp_next_iss+0x48>)
80120c2: 681b ldr r3, [r3, #0]
80120c4: 4413 add r3, r2
80120c6: 4a07 ldr r2, [pc, #28] ; (80120e4 <tcp_next_iss+0x44>)
80120c8: 6013 str r3, [r2, #0]
return iss;
80120ca: 4b06 ldr r3, [pc, #24] ; (80120e4 <tcp_next_iss+0x44>)
80120cc: 681b ldr r3, [r3, #0]
#endif /* LWIP_HOOK_TCP_ISN */
}
80120ce: 4618 mov r0, r3
80120d0: 3708 adds r7, #8
80120d2: 46bd mov sp, r7
80120d4: bd80 pop {r7, pc}
80120d6: bf00 nop
80120d8: 0801cb58 .word 0x0801cb58
80120dc: 0801d248 .word 0x0801d248
80120e0: 0801cb9c .word 0x0801cb9c
80120e4: 20000078 .word 0x20000078
80120e8: 2000f5c4 .word 0x2000f5c4
080120ec <tcp_eff_send_mss_netif>:
* by calculating the minimum of TCP_MSS and the mtu (if set) of the target
* netif (if not NULL).
*/
u16_t
tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
{
80120ec: b580 push {r7, lr}
80120ee: b086 sub sp, #24
80120f0: af00 add r7, sp, #0
80120f2: 4603 mov r3, r0
80120f4: 60b9 str r1, [r7, #8]
80120f6: 607a str r2, [r7, #4]
80120f8: 81fb strh r3, [r7, #14]
u16_t mss_s;
u16_t mtu;
LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
80120fa: 687b ldr r3, [r7, #4]
80120fc: 2b00 cmp r3, #0
80120fe: d106 bne.n 801210e <tcp_eff_send_mss_netif+0x22>
8012100: 4b14 ldr r3, [pc, #80] ; (8012154 <tcp_eff_send_mss_netif+0x68>)
8012102: f640 02c5 movw r2, #2245 ; 0x8c5
8012106: 4914 ldr r1, [pc, #80] ; (8012158 <tcp_eff_send_mss_netif+0x6c>)
8012108: 4814 ldr r0, [pc, #80] ; (801215c <tcp_eff_send_mss_netif+0x70>)
801210a: f008 ff8b bl 801b024 <iprintf>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
if (outif == NULL) {
801210e: 68bb ldr r3, [r7, #8]
8012110: 2b00 cmp r3, #0
8012112: d101 bne.n 8012118 <tcp_eff_send_mss_netif+0x2c>
return sendmss;
8012114: 89fb ldrh r3, [r7, #14]
8012116: e019 b.n 801214c <tcp_eff_send_mss_netif+0x60>
}
mtu = outif->mtu;
8012118: 68bb ldr r3, [r7, #8]
801211a: 8d1b ldrh r3, [r3, #40] ; 0x28
801211c: 82fb strh r3, [r7, #22]
}
#endif /* LWIP_IPV4 */
if (mtu != 0) {
801211e: 8afb ldrh r3, [r7, #22]
8012120: 2b00 cmp r3, #0
8012122: d012 beq.n 801214a <tcp_eff_send_mss_netif+0x5e>
else
#endif /* LWIP_IPV4 */
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
{
offset = IP_HLEN + TCP_HLEN;
8012124: 2328 movs r3, #40 ; 0x28
8012126: 82bb strh r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
8012128: 8afa ldrh r2, [r7, #22]
801212a: 8abb ldrh r3, [r7, #20]
801212c: 429a cmp r2, r3
801212e: d904 bls.n 801213a <tcp_eff_send_mss_netif+0x4e>
8012130: 8afa ldrh r2, [r7, #22]
8012132: 8abb ldrh r3, [r7, #20]
8012134: 1ad3 subs r3, r2, r3
8012136: b29b uxth r3, r3
8012138: e000 b.n 801213c <tcp_eff_send_mss_netif+0x50>
801213a: 2300 movs r3, #0
801213c: 827b strh r3, [r7, #18]
/* RFC 1122, chap 4.2.2.6:
* Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
* We correct for TCP options in tcp_write(), and don't support IP options.
*/
sendmss = LWIP_MIN(sendmss, mss_s);
801213e: 8a7a ldrh r2, [r7, #18]
8012140: 89fb ldrh r3, [r7, #14]
8012142: 4293 cmp r3, r2
8012144: bf28 it cs
8012146: 4613 movcs r3, r2
8012148: 81fb strh r3, [r7, #14]
}
return sendmss;
801214a: 89fb ldrh r3, [r7, #14]
}
801214c: 4618 mov r0, r3
801214e: 3718 adds r7, #24
8012150: 46bd mov sp, r7
8012152: bd80 pop {r7, pc}
8012154: 0801cb58 .word 0x0801cb58
8012158: 0801d264 .word 0x0801d264
801215c: 0801cb9c .word 0x0801cb9c
08012160 <tcp_netif_ip_addr_changed_pcblist>:
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
static void
tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
{
8012160: b580 push {r7, lr}
8012162: b084 sub sp, #16
8012164: af00 add r7, sp, #0
8012166: 6078 str r0, [r7, #4]
8012168: 6039 str r1, [r7, #0]
struct tcp_pcb *pcb;
pcb = pcb_list;
801216a: 683b ldr r3, [r7, #0]
801216c: 60fb str r3, [r7, #12]
LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
801216e: 687b ldr r3, [r7, #4]
8012170: 2b00 cmp r3, #0
8012172: d119 bne.n 80121a8 <tcp_netif_ip_addr_changed_pcblist+0x48>
8012174: 4b10 ldr r3, [pc, #64] ; (80121b8 <tcp_netif_ip_addr_changed_pcblist+0x58>)
8012176: f44f 6210 mov.w r2, #2304 ; 0x900
801217a: 4910 ldr r1, [pc, #64] ; (80121bc <tcp_netif_ip_addr_changed_pcblist+0x5c>)
801217c: 4810 ldr r0, [pc, #64] ; (80121c0 <tcp_netif_ip_addr_changed_pcblist+0x60>)
801217e: f008 ff51 bl 801b024 <iprintf>
while (pcb != NULL) {
8012182: e011 b.n 80121a8 <tcp_netif_ip_addr_changed_pcblist+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&pcb->local_ip, old_addr)
8012184: 68fb ldr r3, [r7, #12]
8012186: 681a ldr r2, [r3, #0]
8012188: 687b ldr r3, [r7, #4]
801218a: 681b ldr r3, [r3, #0]
801218c: 429a cmp r2, r3
801218e: d108 bne.n 80121a2 <tcp_netif_ip_addr_changed_pcblist+0x42>
/* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
&& (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
#endif /* LWIP_AUTOIP */
) {
/* this connection must be aborted */
struct tcp_pcb *next = pcb->next;
8012190: 68fb ldr r3, [r7, #12]
8012192: 68db ldr r3, [r3, #12]
8012194: 60bb str r3, [r7, #8]
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
tcp_abort(pcb);
8012196: 68f8 ldr r0, [r7, #12]
8012198: f7fe ffca bl 8011130 <tcp_abort>
pcb = next;
801219c: 68bb ldr r3, [r7, #8]
801219e: 60fb str r3, [r7, #12]
80121a0: e002 b.n 80121a8 <tcp_netif_ip_addr_changed_pcblist+0x48>
} else {
pcb = pcb->next;
80121a2: 68fb ldr r3, [r7, #12]
80121a4: 68db ldr r3, [r3, #12]
80121a6: 60fb str r3, [r7, #12]
while (pcb != NULL) {
80121a8: 68fb ldr r3, [r7, #12]
80121aa: 2b00 cmp r3, #0
80121ac: d1ea bne.n 8012184 <tcp_netif_ip_addr_changed_pcblist+0x24>
}
}
}
80121ae: bf00 nop
80121b0: 3710 adds r7, #16
80121b2: 46bd mov sp, r7
80121b4: bd80 pop {r7, pc}
80121b6: bf00 nop
80121b8: 0801cb58 .word 0x0801cb58
80121bc: 0801d28c .word 0x0801d28c
80121c0: 0801cb9c .word 0x0801cb9c
080121c4 <tcp_netif_ip_addr_changed>:
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change or NULL if netif has been removed
*/
void
tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
80121c4: b580 push {r7, lr}
80121c6: b084 sub sp, #16
80121c8: af00 add r7, sp, #0
80121ca: 6078 str r0, [r7, #4]
80121cc: 6039 str r1, [r7, #0]
struct tcp_pcb_listen *lpcb;
if (!ip_addr_isany(old_addr)) {
80121ce: 687b ldr r3, [r7, #4]
80121d0: 2b00 cmp r3, #0
80121d2: d02a beq.n 801222a <tcp_netif_ip_addr_changed+0x66>
80121d4: 687b ldr r3, [r7, #4]
80121d6: 681b ldr r3, [r3, #0]
80121d8: 2b00 cmp r3, #0
80121da: d026 beq.n 801222a <tcp_netif_ip_addr_changed+0x66>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
80121dc: 4b15 ldr r3, [pc, #84] ; (8012234 <tcp_netif_ip_addr_changed+0x70>)
80121de: 681b ldr r3, [r3, #0]
80121e0: 4619 mov r1, r3
80121e2: 6878 ldr r0, [r7, #4]
80121e4: f7ff ffbc bl 8012160 <tcp_netif_ip_addr_changed_pcblist>
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
80121e8: 4b13 ldr r3, [pc, #76] ; (8012238 <tcp_netif_ip_addr_changed+0x74>)
80121ea: 681b ldr r3, [r3, #0]
80121ec: 4619 mov r1, r3
80121ee: 6878 ldr r0, [r7, #4]
80121f0: f7ff ffb6 bl 8012160 <tcp_netif_ip_addr_changed_pcblist>
if (!ip_addr_isany(new_addr)) {
80121f4: 683b ldr r3, [r7, #0]
80121f6: 2b00 cmp r3, #0
80121f8: d017 beq.n 801222a <tcp_netif_ip_addr_changed+0x66>
80121fa: 683b ldr r3, [r7, #0]
80121fc: 681b ldr r3, [r3, #0]
80121fe: 2b00 cmp r3, #0
8012200: d013 beq.n 801222a <tcp_netif_ip_addr_changed+0x66>
/* PCB bound to current local interface address? */
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
8012202: 4b0e ldr r3, [pc, #56] ; (801223c <tcp_netif_ip_addr_changed+0x78>)
8012204: 681b ldr r3, [r3, #0]
8012206: 60fb str r3, [r7, #12]
8012208: e00c b.n 8012224 <tcp_netif_ip_addr_changed+0x60>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
801220a: 68fb ldr r3, [r7, #12]
801220c: 681a ldr r2, [r3, #0]
801220e: 687b ldr r3, [r7, #4]
8012210: 681b ldr r3, [r3, #0]
8012212: 429a cmp r2, r3
8012214: d103 bne.n 801221e <tcp_netif_ip_addr_changed+0x5a>
/* The PCB is listening to the old ipaddr and
* is set to listen to the new one instead */
ip_addr_copy(lpcb->local_ip, *new_addr);
8012216: 683b ldr r3, [r7, #0]
8012218: 681a ldr r2, [r3, #0]
801221a: 68fb ldr r3, [r7, #12]
801221c: 601a str r2, [r3, #0]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
801221e: 68fb ldr r3, [r7, #12]
8012220: 68db ldr r3, [r3, #12]
8012222: 60fb str r3, [r7, #12]
8012224: 68fb ldr r3, [r7, #12]
8012226: 2b00 cmp r3, #0
8012228: d1ef bne.n 801220a <tcp_netif_ip_addr_changed+0x46>
}
}
}
}
}
801222a: bf00 nop
801222c: 3710 adds r7, #16
801222e: 46bd mov sp, r7
8012230: bd80 pop {r7, pc}
8012232: bf00 nop
8012234: 2000f5c0 .word 0x2000f5c0
8012238: 2000f5cc .word 0x2000f5cc
801223c: 2000f5c8 .word 0x2000f5c8
08012240 <tcp_free_ooseq>:
#if TCP_QUEUE_OOSEQ
/* Free all ooseq pbufs (and possibly reset SACK state) */
void
tcp_free_ooseq(struct tcp_pcb *pcb)
{
8012240: b580 push {r7, lr}
8012242: b082 sub sp, #8
8012244: af00 add r7, sp, #0
8012246: 6078 str r0, [r7, #4]
if (pcb->ooseq) {
8012248: 687b ldr r3, [r7, #4]
801224a: 6f5b ldr r3, [r3, #116] ; 0x74
801224c: 2b00 cmp r3, #0
801224e: d007 beq.n 8012260 <tcp_free_ooseq+0x20>
tcp_segs_free(pcb->ooseq);
8012250: 687b ldr r3, [r7, #4]
8012252: 6f5b ldr r3, [r3, #116] ; 0x74
8012254: 4618 mov r0, r3
8012256: f7ff fc3f bl 8011ad8 <tcp_segs_free>
pcb->ooseq = NULL;
801225a: 687b ldr r3, [r7, #4]
801225c: 2200 movs r2, #0
801225e: 675a str r2, [r3, #116] ; 0x74
#if LWIP_TCP_SACK_OUT
memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
#endif /* LWIP_TCP_SACK_OUT */
}
}
8012260: bf00 nop
8012262: 3708 adds r7, #8
8012264: 46bd mov sp, r7
8012266: bd80 pop {r7, pc}
08012268 <tcp_input>:
* @param p received TCP segment to process (p->payload pointing to the TCP header)
* @param inp network interface on which this segment was received
*/
void
tcp_input(struct pbuf *p, struct netif *inp)
{
8012268: b590 push {r4, r7, lr}
801226a: b08d sub sp, #52 ; 0x34
801226c: af04 add r7, sp, #16
801226e: 6078 str r0, [r7, #4]
8012270: 6039 str r1, [r7, #0]
u8_t hdrlen_bytes;
err_t err;
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
8012272: 687b ldr r3, [r7, #4]
8012274: 2b00 cmp r3, #0
8012276: d105 bne.n 8012284 <tcp_input+0x1c>
8012278: 4b9b ldr r3, [pc, #620] ; (80124e8 <tcp_input+0x280>)
801227a: 2283 movs r2, #131 ; 0x83
801227c: 499b ldr r1, [pc, #620] ; (80124ec <tcp_input+0x284>)
801227e: 489c ldr r0, [pc, #624] ; (80124f0 <tcp_input+0x288>)
8012280: f008 fed0 bl 801b024 <iprintf>
PERF_START;
TCP_STATS_INC(tcp.recv);
MIB2_STATS_INC(mib2.tcpinsegs);
tcphdr = (struct tcp_hdr *)p->payload;
8012284: 687b ldr r3, [r7, #4]
8012286: 685b ldr r3, [r3, #4]
8012288: 4a9a ldr r2, [pc, #616] ; (80124f4 <tcp_input+0x28c>)
801228a: 6013 str r3, [r2, #0]
#if TCP_INPUT_DEBUG
tcp_debug_print(tcphdr);
#endif
/* Check that TCP header fits in payload */
if (p->len < TCP_HLEN) {
801228c: 687b ldr r3, [r7, #4]
801228e: 895b ldrh r3, [r3, #10]
8012290: 2b13 cmp r3, #19
8012292: f240 83c4 bls.w 8012a1e <tcp_input+0x7b6>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* Don't even process incoming broadcasts/multicasts. */
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
8012296: 4b98 ldr r3, [pc, #608] ; (80124f8 <tcp_input+0x290>)
8012298: 695a ldr r2, [r3, #20]
801229a: 4b97 ldr r3, [pc, #604] ; (80124f8 <tcp_input+0x290>)
801229c: 681b ldr r3, [r3, #0]
801229e: 4619 mov r1, r3
80122a0: 4610 mov r0, r2
80122a2: f007 fe17 bl 8019ed4 <ip4_addr_isbroadcast_u32>
80122a6: 4603 mov r3, r0
80122a8: 2b00 cmp r3, #0
80122aa: f040 83ba bne.w 8012a22 <tcp_input+0x7ba>
ip_addr_ismulticast(ip_current_dest_addr())) {
80122ae: 4b92 ldr r3, [pc, #584] ; (80124f8 <tcp_input+0x290>)
80122b0: 695b ldr r3, [r3, #20]
80122b2: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
80122b6: 2be0 cmp r3, #224 ; 0xe0
80122b8: f000 83b3 beq.w 8012a22 <tcp_input+0x7ba>
}
}
#endif /* CHECKSUM_CHECK_TCP */
/* sanity-check header length */
hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
80122bc: 4b8d ldr r3, [pc, #564] ; (80124f4 <tcp_input+0x28c>)
80122be: 681b ldr r3, [r3, #0]
80122c0: 899b ldrh r3, [r3, #12]
80122c2: b29b uxth r3, r3
80122c4: 4618 mov r0, r3
80122c6: f7fc fde3 bl 800ee90 <lwip_htons>
80122ca: 4603 mov r3, r0
80122cc: 0b1b lsrs r3, r3, #12
80122ce: b29b uxth r3, r3
80122d0: b2db uxtb r3, r3
80122d2: 009b lsls r3, r3, #2
80122d4: 74bb strb r3, [r7, #18]
if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
80122d6: 7cbb ldrb r3, [r7, #18]
80122d8: 2b13 cmp r3, #19
80122da: f240 83a2 bls.w 8012a22 <tcp_input+0x7ba>
80122de: 7cbb ldrb r3, [r7, #18]
80122e0: b29a uxth r2, r3
80122e2: 687b ldr r3, [r7, #4]
80122e4: 891b ldrh r3, [r3, #8]
80122e6: 429a cmp r2, r3
80122e8: f200 839b bhi.w 8012a22 <tcp_input+0x7ba>
goto dropped;
}
/* Move the payload pointer in the pbuf so that it points to the
TCP data instead of the TCP header. */
tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
80122ec: 7cbb ldrb r3, [r7, #18]
80122ee: b29b uxth r3, r3
80122f0: 3b14 subs r3, #20
80122f2: b29a uxth r2, r3
80122f4: 4b81 ldr r3, [pc, #516] ; (80124fc <tcp_input+0x294>)
80122f6: 801a strh r2, [r3, #0]
tcphdr_opt2 = NULL;
80122f8: 4b81 ldr r3, [pc, #516] ; (8012500 <tcp_input+0x298>)
80122fa: 2200 movs r2, #0
80122fc: 601a str r2, [r3, #0]
if (p->len >= hdrlen_bytes) {
80122fe: 687b ldr r3, [r7, #4]
8012300: 895a ldrh r2, [r3, #10]
8012302: 7cbb ldrb r3, [r7, #18]
8012304: b29b uxth r3, r3
8012306: 429a cmp r2, r3
8012308: d309 bcc.n 801231e <tcp_input+0xb6>
/* all options are in the first pbuf */
tcphdr_opt1len = tcphdr_optlen;
801230a: 4b7c ldr r3, [pc, #496] ; (80124fc <tcp_input+0x294>)
801230c: 881a ldrh r2, [r3, #0]
801230e: 4b7d ldr r3, [pc, #500] ; (8012504 <tcp_input+0x29c>)
8012310: 801a strh r2, [r3, #0]
pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
8012312: 7cbb ldrb r3, [r7, #18]
8012314: 4619 mov r1, r3
8012316: 6878 ldr r0, [r7, #4]
8012318: f7fe f8e8 bl 80104ec <pbuf_remove_header>
801231c: e04e b.n 80123bc <tcp_input+0x154>
} else {
u16_t opt2len;
/* TCP header fits into first pbuf, options don't - data is in the next pbuf */
/* there must be a next pbuf, due to hdrlen_bytes sanity check above */
LWIP_ASSERT("p->next != NULL", p->next != NULL);
801231e: 687b ldr r3, [r7, #4]
8012320: 681b ldr r3, [r3, #0]
8012322: 2b00 cmp r3, #0
8012324: d105 bne.n 8012332 <tcp_input+0xca>
8012326: 4b70 ldr r3, [pc, #448] ; (80124e8 <tcp_input+0x280>)
8012328: 22c2 movs r2, #194 ; 0xc2
801232a: 4977 ldr r1, [pc, #476] ; (8012508 <tcp_input+0x2a0>)
801232c: 4870 ldr r0, [pc, #448] ; (80124f0 <tcp_input+0x288>)
801232e: f008 fe79 bl 801b024 <iprintf>
/* advance over the TCP header (cannot fail) */
pbuf_remove_header(p, TCP_HLEN);
8012332: 2114 movs r1, #20
8012334: 6878 ldr r0, [r7, #4]
8012336: f7fe f8d9 bl 80104ec <pbuf_remove_header>
/* determine how long the first and second parts of the options are */
tcphdr_opt1len = p->len;
801233a: 687b ldr r3, [r7, #4]
801233c: 895a ldrh r2, [r3, #10]
801233e: 4b71 ldr r3, [pc, #452] ; (8012504 <tcp_input+0x29c>)
8012340: 801a strh r2, [r3, #0]
opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
8012342: 4b6e ldr r3, [pc, #440] ; (80124fc <tcp_input+0x294>)
8012344: 881a ldrh r2, [r3, #0]
8012346: 4b6f ldr r3, [pc, #444] ; (8012504 <tcp_input+0x29c>)
8012348: 881b ldrh r3, [r3, #0]
801234a: 1ad3 subs r3, r2, r3
801234c: 823b strh r3, [r7, #16]
/* options continue in the next pbuf: set p to zero length and hide the
options in the next pbuf (adjusting p->tot_len) */
pbuf_remove_header(p, tcphdr_opt1len);
801234e: 4b6d ldr r3, [pc, #436] ; (8012504 <tcp_input+0x29c>)
8012350: 881b ldrh r3, [r3, #0]
8012352: 4619 mov r1, r3
8012354: 6878 ldr r0, [r7, #4]
8012356: f7fe f8c9 bl 80104ec <pbuf_remove_header>
/* check that the options fit in the second pbuf */
if (opt2len > p->next->len) {
801235a: 687b ldr r3, [r7, #4]
801235c: 681b ldr r3, [r3, #0]
801235e: 895b ldrh r3, [r3, #10]
8012360: 8a3a ldrh r2, [r7, #16]
8012362: 429a cmp r2, r3
8012364: f200 835f bhi.w 8012a26 <tcp_input+0x7be>
TCP_STATS_INC(tcp.lenerr);
goto dropped;
}
/* remember the pointer to the second part of the options */
tcphdr_opt2 = (u8_t *)p->next->payload;
8012368: 687b ldr r3, [r7, #4]
801236a: 681b ldr r3, [r3, #0]
801236c: 685b ldr r3, [r3, #4]
801236e: 4a64 ldr r2, [pc, #400] ; (8012500 <tcp_input+0x298>)
8012370: 6013 str r3, [r2, #0]
/* advance p->next to point after the options, and manually
adjust p->tot_len to keep it consistent with the changed p->next */
pbuf_remove_header(p->next, opt2len);
8012372: 687b ldr r3, [r7, #4]
8012374: 681b ldr r3, [r3, #0]
8012376: 8a3a ldrh r2, [r7, #16]
8012378: 4611 mov r1, r2
801237a: 4618 mov r0, r3
801237c: f7fe f8b6 bl 80104ec <pbuf_remove_header>
p->tot_len = (u16_t)(p->tot_len - opt2len);
8012380: 687b ldr r3, [r7, #4]
8012382: 891a ldrh r2, [r3, #8]
8012384: 8a3b ldrh r3, [r7, #16]
8012386: 1ad3 subs r3, r2, r3
8012388: b29a uxth r2, r3
801238a: 687b ldr r3, [r7, #4]
801238c: 811a strh r2, [r3, #8]
LWIP_ASSERT("p->len == 0", p->len == 0);
801238e: 687b ldr r3, [r7, #4]
8012390: 895b ldrh r3, [r3, #10]
8012392: 2b00 cmp r3, #0
8012394: d005 beq.n 80123a2 <tcp_input+0x13a>
8012396: 4b54 ldr r3, [pc, #336] ; (80124e8 <tcp_input+0x280>)
8012398: 22df movs r2, #223 ; 0xdf
801239a: 495c ldr r1, [pc, #368] ; (801250c <tcp_input+0x2a4>)
801239c: 4854 ldr r0, [pc, #336] ; (80124f0 <tcp_input+0x288>)
801239e: f008 fe41 bl 801b024 <iprintf>
LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
80123a2: 687b ldr r3, [r7, #4]
80123a4: 891a ldrh r2, [r3, #8]
80123a6: 687b ldr r3, [r7, #4]
80123a8: 681b ldr r3, [r3, #0]
80123aa: 891b ldrh r3, [r3, #8]
80123ac: 429a cmp r2, r3
80123ae: d005 beq.n 80123bc <tcp_input+0x154>
80123b0: 4b4d ldr r3, [pc, #308] ; (80124e8 <tcp_input+0x280>)
80123b2: 22e0 movs r2, #224 ; 0xe0
80123b4: 4956 ldr r1, [pc, #344] ; (8012510 <tcp_input+0x2a8>)
80123b6: 484e ldr r0, [pc, #312] ; (80124f0 <tcp_input+0x288>)
80123b8: f008 fe34 bl 801b024 <iprintf>
}
/* Convert fields in TCP header to host byte order. */
tcphdr->src = lwip_ntohs(tcphdr->src);
80123bc: 4b4d ldr r3, [pc, #308] ; (80124f4 <tcp_input+0x28c>)
80123be: 681b ldr r3, [r3, #0]
80123c0: 881b ldrh r3, [r3, #0]
80123c2: b29a uxth r2, r3
80123c4: 4b4b ldr r3, [pc, #300] ; (80124f4 <tcp_input+0x28c>)
80123c6: 681c ldr r4, [r3, #0]
80123c8: 4610 mov r0, r2
80123ca: f7fc fd61 bl 800ee90 <lwip_htons>
80123ce: 4603 mov r3, r0
80123d0: 8023 strh r3, [r4, #0]
tcphdr->dest = lwip_ntohs(tcphdr->dest);
80123d2: 4b48 ldr r3, [pc, #288] ; (80124f4 <tcp_input+0x28c>)
80123d4: 681b ldr r3, [r3, #0]
80123d6: 885b ldrh r3, [r3, #2]
80123d8: b29a uxth r2, r3
80123da: 4b46 ldr r3, [pc, #280] ; (80124f4 <tcp_input+0x28c>)
80123dc: 681c ldr r4, [r3, #0]
80123de: 4610 mov r0, r2
80123e0: f7fc fd56 bl 800ee90 <lwip_htons>
80123e4: 4603 mov r3, r0
80123e6: 8063 strh r3, [r4, #2]
seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
80123e8: 4b42 ldr r3, [pc, #264] ; (80124f4 <tcp_input+0x28c>)
80123ea: 681b ldr r3, [r3, #0]
80123ec: 685a ldr r2, [r3, #4]
80123ee: 4b41 ldr r3, [pc, #260] ; (80124f4 <tcp_input+0x28c>)
80123f0: 681c ldr r4, [r3, #0]
80123f2: 4610 mov r0, r2
80123f4: f7fc fd61 bl 800eeba <lwip_htonl>
80123f8: 4603 mov r3, r0
80123fa: 6063 str r3, [r4, #4]
80123fc: 6863 ldr r3, [r4, #4]
80123fe: 4a45 ldr r2, [pc, #276] ; (8012514 <tcp_input+0x2ac>)
8012400: 6013 str r3, [r2, #0]
ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
8012402: 4b3c ldr r3, [pc, #240] ; (80124f4 <tcp_input+0x28c>)
8012404: 681b ldr r3, [r3, #0]
8012406: 689a ldr r2, [r3, #8]
8012408: 4b3a ldr r3, [pc, #232] ; (80124f4 <tcp_input+0x28c>)
801240a: 681c ldr r4, [r3, #0]
801240c: 4610 mov r0, r2
801240e: f7fc fd54 bl 800eeba <lwip_htonl>
8012412: 4603 mov r3, r0
8012414: 60a3 str r3, [r4, #8]
8012416: 68a3 ldr r3, [r4, #8]
8012418: 4a3f ldr r2, [pc, #252] ; (8012518 <tcp_input+0x2b0>)
801241a: 6013 str r3, [r2, #0]
tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
801241c: 4b35 ldr r3, [pc, #212] ; (80124f4 <tcp_input+0x28c>)
801241e: 681b ldr r3, [r3, #0]
8012420: 89db ldrh r3, [r3, #14]
8012422: b29a uxth r2, r3
8012424: 4b33 ldr r3, [pc, #204] ; (80124f4 <tcp_input+0x28c>)
8012426: 681c ldr r4, [r3, #0]
8012428: 4610 mov r0, r2
801242a: f7fc fd31 bl 800ee90 <lwip_htons>
801242e: 4603 mov r3, r0
8012430: 81e3 strh r3, [r4, #14]
flags = TCPH_FLAGS(tcphdr);
8012432: 4b30 ldr r3, [pc, #192] ; (80124f4 <tcp_input+0x28c>)
8012434: 681b ldr r3, [r3, #0]
8012436: 899b ldrh r3, [r3, #12]
8012438: b29b uxth r3, r3
801243a: 4618 mov r0, r3
801243c: f7fc fd28 bl 800ee90 <lwip_htons>
8012440: 4603 mov r3, r0
8012442: b2db uxtb r3, r3
8012444: f003 033f and.w r3, r3, #63 ; 0x3f
8012448: b2da uxtb r2, r3
801244a: 4b34 ldr r3, [pc, #208] ; (801251c <tcp_input+0x2b4>)
801244c: 701a strb r2, [r3, #0]
tcplen = p->tot_len;
801244e: 687b ldr r3, [r7, #4]
8012450: 891a ldrh r2, [r3, #8]
8012452: 4b33 ldr r3, [pc, #204] ; (8012520 <tcp_input+0x2b8>)
8012454: 801a strh r2, [r3, #0]
if (flags & (TCP_FIN | TCP_SYN)) {
8012456: 4b31 ldr r3, [pc, #196] ; (801251c <tcp_input+0x2b4>)
8012458: 781b ldrb r3, [r3, #0]
801245a: f003 0303 and.w r3, r3, #3
801245e: 2b00 cmp r3, #0
8012460: d00c beq.n 801247c <tcp_input+0x214>
tcplen++;
8012462: 4b2f ldr r3, [pc, #188] ; (8012520 <tcp_input+0x2b8>)
8012464: 881b ldrh r3, [r3, #0]
8012466: 3301 adds r3, #1
8012468: b29a uxth r2, r3
801246a: 4b2d ldr r3, [pc, #180] ; (8012520 <tcp_input+0x2b8>)
801246c: 801a strh r2, [r3, #0]
if (tcplen < p->tot_len) {
801246e: 687b ldr r3, [r7, #4]
8012470: 891a ldrh r2, [r3, #8]
8012472: 4b2b ldr r3, [pc, #172] ; (8012520 <tcp_input+0x2b8>)
8012474: 881b ldrh r3, [r3, #0]
8012476: 429a cmp r2, r3
8012478: f200 82d7 bhi.w 8012a2a <tcp_input+0x7c2>
}
}
/* Demultiplex an incoming segment. First, we check if it is destined
for an active connection. */
prev = NULL;
801247c: 2300 movs r3, #0
801247e: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
8012480: 4b28 ldr r3, [pc, #160] ; (8012524 <tcp_input+0x2bc>)
8012482: 681b ldr r3, [r3, #0]
8012484: 61fb str r3, [r7, #28]
8012486: e09d b.n 80125c4 <tcp_input+0x35c>
LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
8012488: 69fb ldr r3, [r7, #28]
801248a: 7d1b ldrb r3, [r3, #20]
801248c: 2b00 cmp r3, #0
801248e: d105 bne.n 801249c <tcp_input+0x234>
8012490: 4b15 ldr r3, [pc, #84] ; (80124e8 <tcp_input+0x280>)
8012492: 22fb movs r2, #251 ; 0xfb
8012494: 4924 ldr r1, [pc, #144] ; (8012528 <tcp_input+0x2c0>)
8012496: 4816 ldr r0, [pc, #88] ; (80124f0 <tcp_input+0x288>)
8012498: f008 fdc4 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
801249c: 69fb ldr r3, [r7, #28]
801249e: 7d1b ldrb r3, [r3, #20]
80124a0: 2b0a cmp r3, #10
80124a2: d105 bne.n 80124b0 <tcp_input+0x248>
80124a4: 4b10 ldr r3, [pc, #64] ; (80124e8 <tcp_input+0x280>)
80124a6: 22fc movs r2, #252 ; 0xfc
80124a8: 4920 ldr r1, [pc, #128] ; (801252c <tcp_input+0x2c4>)
80124aa: 4811 ldr r0, [pc, #68] ; (80124f0 <tcp_input+0x288>)
80124ac: f008 fdba bl 801b024 <iprintf>
LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
80124b0: 69fb ldr r3, [r7, #28]
80124b2: 7d1b ldrb r3, [r3, #20]
80124b4: 2b01 cmp r3, #1
80124b6: d105 bne.n 80124c4 <tcp_input+0x25c>
80124b8: 4b0b ldr r3, [pc, #44] ; (80124e8 <tcp_input+0x280>)
80124ba: 22fd movs r2, #253 ; 0xfd
80124bc: 491c ldr r1, [pc, #112] ; (8012530 <tcp_input+0x2c8>)
80124be: 480c ldr r0, [pc, #48] ; (80124f0 <tcp_input+0x288>)
80124c0: f008 fdb0 bl 801b024 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80124c4: 69fb ldr r3, [r7, #28]
80124c6: 7a1b ldrb r3, [r3, #8]
80124c8: 2b00 cmp r3, #0
80124ca: d033 beq.n 8012534 <tcp_input+0x2cc>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80124cc: 69fb ldr r3, [r7, #28]
80124ce: 7a1a ldrb r2, [r3, #8]
80124d0: 4b09 ldr r3, [pc, #36] ; (80124f8 <tcp_input+0x290>)
80124d2: 685b ldr r3, [r3, #4]
80124d4: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80124d8: 3301 adds r3, #1
80124da: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80124dc: 429a cmp r2, r3
80124de: d029 beq.n 8012534 <tcp_input+0x2cc>
prev = pcb;
80124e0: 69fb ldr r3, [r7, #28]
80124e2: 61bb str r3, [r7, #24]
continue;
80124e4: e06b b.n 80125be <tcp_input+0x356>
80124e6: bf00 nop
80124e8: 0801d2c0 .word 0x0801d2c0
80124ec: 0801d2f4 .word 0x0801d2f4
80124f0: 0801d30c .word 0x0801d30c
80124f4: 2000873c .word 0x2000873c
80124f8: 2000be8c .word 0x2000be8c
80124fc: 20008740 .word 0x20008740
8012500: 20008744 .word 0x20008744
8012504: 20008742 .word 0x20008742
8012508: 0801d334 .word 0x0801d334
801250c: 0801d344 .word 0x0801d344
8012510: 0801d350 .word 0x0801d350
8012514: 2000874c .word 0x2000874c
8012518: 20008750 .word 0x20008750
801251c: 20008758 .word 0x20008758
8012520: 20008756 .word 0x20008756
8012524: 2000f5c0 .word 0x2000f5c0
8012528: 0801d370 .word 0x0801d370
801252c: 0801d398 .word 0x0801d398
8012530: 0801d3c4 .word 0x0801d3c4
}
if (pcb->remote_port == tcphdr->src &&
8012534: 69fb ldr r3, [r7, #28]
8012536: 8b1a ldrh r2, [r3, #24]
8012538: 4b94 ldr r3, [pc, #592] ; (801278c <tcp_input+0x524>)
801253a: 681b ldr r3, [r3, #0]
801253c: 881b ldrh r3, [r3, #0]
801253e: b29b uxth r3, r3
8012540: 429a cmp r2, r3
8012542: d13a bne.n 80125ba <tcp_input+0x352>
pcb->local_port == tcphdr->dest &&
8012544: 69fb ldr r3, [r7, #28]
8012546: 8ada ldrh r2, [r3, #22]
8012548: 4b90 ldr r3, [pc, #576] ; (801278c <tcp_input+0x524>)
801254a: 681b ldr r3, [r3, #0]
801254c: 885b ldrh r3, [r3, #2]
801254e: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
8012550: 429a cmp r2, r3
8012552: d132 bne.n 80125ba <tcp_input+0x352>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012554: 69fb ldr r3, [r7, #28]
8012556: 685a ldr r2, [r3, #4]
8012558: 4b8d ldr r3, [pc, #564] ; (8012790 <tcp_input+0x528>)
801255a: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
801255c: 429a cmp r2, r3
801255e: d12c bne.n 80125ba <tcp_input+0x352>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
8012560: 69fb ldr r3, [r7, #28]
8012562: 681a ldr r2, [r3, #0]
8012564: 4b8a ldr r3, [pc, #552] ; (8012790 <tcp_input+0x528>)
8012566: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012568: 429a cmp r2, r3
801256a: d126 bne.n 80125ba <tcp_input+0x352>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
801256c: 69fb ldr r3, [r7, #28]
801256e: 68db ldr r3, [r3, #12]
8012570: 69fa ldr r2, [r7, #28]
8012572: 429a cmp r2, r3
8012574: d106 bne.n 8012584 <tcp_input+0x31c>
8012576: 4b87 ldr r3, [pc, #540] ; (8012794 <tcp_input+0x52c>)
8012578: f240 120d movw r2, #269 ; 0x10d
801257c: 4986 ldr r1, [pc, #536] ; (8012798 <tcp_input+0x530>)
801257e: 4887 ldr r0, [pc, #540] ; (801279c <tcp_input+0x534>)
8012580: f008 fd50 bl 801b024 <iprintf>
if (prev != NULL) {
8012584: 69bb ldr r3, [r7, #24]
8012586: 2b00 cmp r3, #0
8012588: d00a beq.n 80125a0 <tcp_input+0x338>
prev->next = pcb->next;
801258a: 69fb ldr r3, [r7, #28]
801258c: 68da ldr r2, [r3, #12]
801258e: 69bb ldr r3, [r7, #24]
8012590: 60da str r2, [r3, #12]
pcb->next = tcp_active_pcbs;
8012592: 4b83 ldr r3, [pc, #524] ; (80127a0 <tcp_input+0x538>)
8012594: 681a ldr r2, [r3, #0]
8012596: 69fb ldr r3, [r7, #28]
8012598: 60da str r2, [r3, #12]
tcp_active_pcbs = pcb;
801259a: 4a81 ldr r2, [pc, #516] ; (80127a0 <tcp_input+0x538>)
801259c: 69fb ldr r3, [r7, #28]
801259e: 6013 str r3, [r2, #0]
} else {
TCP_STATS_INC(tcp.cachehit);
}
LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
80125a0: 69fb ldr r3, [r7, #28]
80125a2: 68db ldr r3, [r3, #12]
80125a4: 69fa ldr r2, [r7, #28]
80125a6: 429a cmp r2, r3
80125a8: d111 bne.n 80125ce <tcp_input+0x366>
80125aa: 4b7a ldr r3, [pc, #488] ; (8012794 <tcp_input+0x52c>)
80125ac: f240 1215 movw r2, #277 ; 0x115
80125b0: 497c ldr r1, [pc, #496] ; (80127a4 <tcp_input+0x53c>)
80125b2: 487a ldr r0, [pc, #488] ; (801279c <tcp_input+0x534>)
80125b4: f008 fd36 bl 801b024 <iprintf>
break;
80125b8: e009 b.n 80125ce <tcp_input+0x366>
}
prev = pcb;
80125ba: 69fb ldr r3, [r7, #28]
80125bc: 61bb str r3, [r7, #24]
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
80125be: 69fb ldr r3, [r7, #28]
80125c0: 68db ldr r3, [r3, #12]
80125c2: 61fb str r3, [r7, #28]
80125c4: 69fb ldr r3, [r7, #28]
80125c6: 2b00 cmp r3, #0
80125c8: f47f af5e bne.w 8012488 <tcp_input+0x220>
80125cc: e000 b.n 80125d0 <tcp_input+0x368>
break;
80125ce: bf00 nop
}
if (pcb == NULL) {
80125d0: 69fb ldr r3, [r7, #28]
80125d2: 2b00 cmp r3, #0
80125d4: f040 8095 bne.w 8012702 <tcp_input+0x49a>
/* If it did not go to an active connection, we check the connections
in the TIME-WAIT state. */
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
80125d8: 4b73 ldr r3, [pc, #460] ; (80127a8 <tcp_input+0x540>)
80125da: 681b ldr r3, [r3, #0]
80125dc: 61fb str r3, [r7, #28]
80125de: e03f b.n 8012660 <tcp_input+0x3f8>
LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
80125e0: 69fb ldr r3, [r7, #28]
80125e2: 7d1b ldrb r3, [r3, #20]
80125e4: 2b0a cmp r3, #10
80125e6: d006 beq.n 80125f6 <tcp_input+0x38e>
80125e8: 4b6a ldr r3, [pc, #424] ; (8012794 <tcp_input+0x52c>)
80125ea: f240 121f movw r2, #287 ; 0x11f
80125ee: 496f ldr r1, [pc, #444] ; (80127ac <tcp_input+0x544>)
80125f0: 486a ldr r0, [pc, #424] ; (801279c <tcp_input+0x534>)
80125f2: f008 fd17 bl 801b024 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80125f6: 69fb ldr r3, [r7, #28]
80125f8: 7a1b ldrb r3, [r3, #8]
80125fa: 2b00 cmp r3, #0
80125fc: d009 beq.n 8012612 <tcp_input+0x3aa>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80125fe: 69fb ldr r3, [r7, #28]
8012600: 7a1a ldrb r2, [r3, #8]
8012602: 4b63 ldr r3, [pc, #396] ; (8012790 <tcp_input+0x528>)
8012604: 685b ldr r3, [r3, #4]
8012606: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
801260a: 3301 adds r3, #1
801260c: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
801260e: 429a cmp r2, r3
8012610: d122 bne.n 8012658 <tcp_input+0x3f0>
continue;
}
if (pcb->remote_port == tcphdr->src &&
8012612: 69fb ldr r3, [r7, #28]
8012614: 8b1a ldrh r2, [r3, #24]
8012616: 4b5d ldr r3, [pc, #372] ; (801278c <tcp_input+0x524>)
8012618: 681b ldr r3, [r3, #0]
801261a: 881b ldrh r3, [r3, #0]
801261c: b29b uxth r3, r3
801261e: 429a cmp r2, r3
8012620: d11b bne.n 801265a <tcp_input+0x3f2>
pcb->local_port == tcphdr->dest &&
8012622: 69fb ldr r3, [r7, #28]
8012624: 8ada ldrh r2, [r3, #22]
8012626: 4b59 ldr r3, [pc, #356] ; (801278c <tcp_input+0x524>)
8012628: 681b ldr r3, [r3, #0]
801262a: 885b ldrh r3, [r3, #2]
801262c: b29b uxth r3, r3
if (pcb->remote_port == tcphdr->src &&
801262e: 429a cmp r2, r3
8012630: d113 bne.n 801265a <tcp_input+0x3f2>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012632: 69fb ldr r3, [r7, #28]
8012634: 685a ldr r2, [r3, #4]
8012636: 4b56 ldr r3, [pc, #344] ; (8012790 <tcp_input+0x528>)
8012638: 691b ldr r3, [r3, #16]
pcb->local_port == tcphdr->dest &&
801263a: 429a cmp r2, r3
801263c: d10d bne.n 801265a <tcp_input+0x3f2>
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
801263e: 69fb ldr r3, [r7, #28]
8012640: 681a ldr r2, [r3, #0]
8012642: 4b53 ldr r3, [pc, #332] ; (8012790 <tcp_input+0x528>)
8012644: 695b ldr r3, [r3, #20]
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
8012646: 429a cmp r2, r3
8012648: d107 bne.n 801265a <tcp_input+0x3f2>
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_timewait_input(pcb);
801264a: 69f8 ldr r0, [r7, #28]
801264c: f000 fb52 bl 8012cf4 <tcp_timewait_input>
}
pbuf_free(p);
8012650: 6878 ldr r0, [r7, #4]
8012652: f7fd ffd1 bl 80105f8 <pbuf_free>
return;
8012656: e1ee b.n 8012a36 <tcp_input+0x7ce>
continue;
8012658: bf00 nop
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
801265a: 69fb ldr r3, [r7, #28]
801265c: 68db ldr r3, [r3, #12]
801265e: 61fb str r3, [r7, #28]
8012660: 69fb ldr r3, [r7, #28]
8012662: 2b00 cmp r3, #0
8012664: d1bc bne.n 80125e0 <tcp_input+0x378>
}
}
/* Finally, if we still did not get a match, we check all PCBs that
are LISTENing for incoming connections. */
prev = NULL;
8012666: 2300 movs r3, #0
8012668: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
801266a: 4b51 ldr r3, [pc, #324] ; (80127b0 <tcp_input+0x548>)
801266c: 681b ldr r3, [r3, #0]
801266e: 617b str r3, [r7, #20]
8012670: e02a b.n 80126c8 <tcp_input+0x460>
/* check if PCB is bound to specific netif */
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
8012672: 697b ldr r3, [r7, #20]
8012674: 7a1b ldrb r3, [r3, #8]
8012676: 2b00 cmp r3, #0
8012678: d00c beq.n 8012694 <tcp_input+0x42c>
(lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
801267a: 697b ldr r3, [r7, #20]
801267c: 7a1a ldrb r2, [r3, #8]
801267e: 4b44 ldr r3, [pc, #272] ; (8012790 <tcp_input+0x528>)
8012680: 685b ldr r3, [r3, #4]
8012682: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
8012686: 3301 adds r3, #1
8012688: b2db uxtb r3, r3
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
801268a: 429a cmp r2, r3
801268c: d002 beq.n 8012694 <tcp_input+0x42c>
prev = (struct tcp_pcb *)lpcb;
801268e: 697b ldr r3, [r7, #20]
8012690: 61bb str r3, [r7, #24]
continue;
8012692: e016 b.n 80126c2 <tcp_input+0x45a>
}
if (lpcb->local_port == tcphdr->dest) {
8012694: 697b ldr r3, [r7, #20]
8012696: 8ada ldrh r2, [r3, #22]
8012698: 4b3c ldr r3, [pc, #240] ; (801278c <tcp_input+0x524>)
801269a: 681b ldr r3, [r3, #0]
801269c: 885b ldrh r3, [r3, #2]
801269e: b29b uxth r3, r3
80126a0: 429a cmp r2, r3
80126a2: d10c bne.n 80126be <tcp_input+0x456>
lpcb_prev = prev;
#else /* SO_REUSE */
break;
#endif /* SO_REUSE */
} else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
80126a4: 697b ldr r3, [r7, #20]
80126a6: 681a ldr r2, [r3, #0]
80126a8: 4b39 ldr r3, [pc, #228] ; (8012790 <tcp_input+0x528>)
80126aa: 695b ldr r3, [r3, #20]
80126ac: 429a cmp r2, r3
80126ae: d00f beq.n 80126d0 <tcp_input+0x468>
/* found an exact match */
break;
} else if (ip_addr_isany(&lpcb->local_ip)) {
80126b0: 697b ldr r3, [r7, #20]
80126b2: 2b00 cmp r3, #0
80126b4: d00d beq.n 80126d2 <tcp_input+0x46a>
80126b6: 697b ldr r3, [r7, #20]
80126b8: 681b ldr r3, [r3, #0]
80126ba: 2b00 cmp r3, #0
80126bc: d009 beq.n 80126d2 <tcp_input+0x46a>
break;
#endif /* SO_REUSE */
}
}
}
prev = (struct tcp_pcb *)lpcb;
80126be: 697b ldr r3, [r7, #20]
80126c0: 61bb str r3, [r7, #24]
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
80126c2: 697b ldr r3, [r7, #20]
80126c4: 68db ldr r3, [r3, #12]
80126c6: 617b str r3, [r7, #20]
80126c8: 697b ldr r3, [r7, #20]
80126ca: 2b00 cmp r3, #0
80126cc: d1d1 bne.n 8012672 <tcp_input+0x40a>
80126ce: e000 b.n 80126d2 <tcp_input+0x46a>
break;
80126d0: bf00 nop
/* only pass to ANY if no specific local IP has been found */
lpcb = lpcb_any;
prev = lpcb_prev;
}
#endif /* SO_REUSE */
if (lpcb != NULL) {
80126d2: 697b ldr r3, [r7, #20]
80126d4: 2b00 cmp r3, #0
80126d6: d014 beq.n 8012702 <tcp_input+0x49a>
/* Move this PCB to the front of the list so that subsequent
lookups will be faster (we exploit locality in TCP segment
arrivals). */
if (prev != NULL) {
80126d8: 69bb ldr r3, [r7, #24]
80126da: 2b00 cmp r3, #0
80126dc: d00a beq.n 80126f4 <tcp_input+0x48c>
((struct tcp_pcb_listen *)prev)->next = lpcb->next;
80126de: 697b ldr r3, [r7, #20]
80126e0: 68da ldr r2, [r3, #12]
80126e2: 69bb ldr r3, [r7, #24]
80126e4: 60da str r2, [r3, #12]
/* our successor is the remainder of the listening list */
lpcb->next = tcp_listen_pcbs.listen_pcbs;
80126e6: 4b32 ldr r3, [pc, #200] ; (80127b0 <tcp_input+0x548>)
80126e8: 681a ldr r2, [r3, #0]
80126ea: 697b ldr r3, [r7, #20]
80126ec: 60da str r2, [r3, #12]
/* put this listening pcb at the head of the listening list */
tcp_listen_pcbs.listen_pcbs = lpcb;
80126ee: 4a30 ldr r2, [pc, #192] ; (80127b0 <tcp_input+0x548>)
80126f0: 697b ldr r3, [r7, #20]
80126f2: 6013 str r3, [r2, #0]
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
#endif
{
tcp_listen_input(lpcb);
80126f4: 6978 ldr r0, [r7, #20]
80126f6: f000 f9ff bl 8012af8 <tcp_listen_input>
}
pbuf_free(p);
80126fa: 6878 ldr r0, [r7, #4]
80126fc: f7fd ff7c bl 80105f8 <pbuf_free>
return;
8012700: e199 b.n 8012a36 <tcp_input+0x7ce>
tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
pbuf_free(p);
return;
}
#endif
if (pcb != NULL) {
8012702: 69fb ldr r3, [r7, #28]
8012704: 2b00 cmp r3, #0
8012706: f000 8160 beq.w 80129ca <tcp_input+0x762>
#if TCP_INPUT_DEBUG
tcp_debug_print_state(pcb->state);
#endif /* TCP_INPUT_DEBUG */
/* Set up a tcp_seg structure. */
inseg.next = NULL;
801270a: 4b2a ldr r3, [pc, #168] ; (80127b4 <tcp_input+0x54c>)
801270c: 2200 movs r2, #0
801270e: 601a str r2, [r3, #0]
inseg.len = p->tot_len;
8012710: 687b ldr r3, [r7, #4]
8012712: 891a ldrh r2, [r3, #8]
8012714: 4b27 ldr r3, [pc, #156] ; (80127b4 <tcp_input+0x54c>)
8012716: 811a strh r2, [r3, #8]
inseg.p = p;
8012718: 4a26 ldr r2, [pc, #152] ; (80127b4 <tcp_input+0x54c>)
801271a: 687b ldr r3, [r7, #4]
801271c: 6053 str r3, [r2, #4]
inseg.tcphdr = tcphdr;
801271e: 4b1b ldr r3, [pc, #108] ; (801278c <tcp_input+0x524>)
8012720: 681b ldr r3, [r3, #0]
8012722: 4a24 ldr r2, [pc, #144] ; (80127b4 <tcp_input+0x54c>)
8012724: 60d3 str r3, [r2, #12]
recv_data = NULL;
8012726: 4b24 ldr r3, [pc, #144] ; (80127b8 <tcp_input+0x550>)
8012728: 2200 movs r2, #0
801272a: 601a str r2, [r3, #0]
recv_flags = 0;
801272c: 4b23 ldr r3, [pc, #140] ; (80127bc <tcp_input+0x554>)
801272e: 2200 movs r2, #0
8012730: 701a strb r2, [r3, #0]
recv_acked = 0;
8012732: 4b23 ldr r3, [pc, #140] ; (80127c0 <tcp_input+0x558>)
8012734: 2200 movs r2, #0
8012736: 801a strh r2, [r3, #0]
if (flags & TCP_PSH) {
8012738: 4b22 ldr r3, [pc, #136] ; (80127c4 <tcp_input+0x55c>)
801273a: 781b ldrb r3, [r3, #0]
801273c: f003 0308 and.w r3, r3, #8
8012740: 2b00 cmp r3, #0
8012742: d006 beq.n 8012752 <tcp_input+0x4ea>
p->flags |= PBUF_FLAG_PUSH;
8012744: 687b ldr r3, [r7, #4]
8012746: 7b5b ldrb r3, [r3, #13]
8012748: f043 0301 orr.w r3, r3, #1
801274c: b2da uxtb r2, r3
801274e: 687b ldr r3, [r7, #4]
8012750: 735a strb r2, [r3, #13]
}
/* If there is data which was previously "refused" by upper layer */
if (pcb->refused_data != NULL) {
8012752: 69fb ldr r3, [r7, #28]
8012754: 6f9b ldr r3, [r3, #120] ; 0x78
8012756: 2b00 cmp r3, #0
8012758: d038 beq.n 80127cc <tcp_input+0x564>
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
801275a: 69f8 ldr r0, [r7, #28]
801275c: f7ff f940 bl 80119e0 <tcp_process_refused_data>
8012760: 4603 mov r3, r0
8012762: f113 0f0d cmn.w r3, #13
8012766: d007 beq.n 8012778 <tcp_input+0x510>
((pcb->refused_data != NULL) && (tcplen > 0))) {
8012768: 69fb ldr r3, [r7, #28]
801276a: 6f9b ldr r3, [r3, #120] ; 0x78
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
801276c: 2b00 cmp r3, #0
801276e: d02d beq.n 80127cc <tcp_input+0x564>
((pcb->refused_data != NULL) && (tcplen > 0))) {
8012770: 4b15 ldr r3, [pc, #84] ; (80127c8 <tcp_input+0x560>)
8012772: 881b ldrh r3, [r3, #0]
8012774: 2b00 cmp r3, #0
8012776: d029 beq.n 80127cc <tcp_input+0x564>
/* pcb has been aborted or refused data is still refused and the new
segment contains data */
if (pcb->rcv_ann_wnd == 0) {
8012778: 69fb ldr r3, [r7, #28]
801277a: 8d5b ldrh r3, [r3, #42] ; 0x2a
801277c: 2b00 cmp r3, #0
801277e: f040 8104 bne.w 801298a <tcp_input+0x722>
/* this is a zero-window probe, we respond to it with current RCV.NXT
and drop the data segment */
tcp_send_empty_ack(pcb);
8012782: 69f8 ldr r0, [r7, #28]
8012784: f003 f9ce bl 8015b24 <tcp_send_empty_ack>
}
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
goto aborted;
8012788: e0ff b.n 801298a <tcp_input+0x722>
801278a: bf00 nop
801278c: 2000873c .word 0x2000873c
8012790: 2000be8c .word 0x2000be8c
8012794: 0801d2c0 .word 0x0801d2c0
8012798: 0801d3ec .word 0x0801d3ec
801279c: 0801d30c .word 0x0801d30c
80127a0: 2000f5c0 .word 0x2000f5c0
80127a4: 0801d418 .word 0x0801d418
80127a8: 2000f5d0 .word 0x2000f5d0
80127ac: 0801d444 .word 0x0801d444
80127b0: 2000f5c8 .word 0x2000f5c8
80127b4: 2000872c .word 0x2000872c
80127b8: 2000875c .word 0x2000875c
80127bc: 20008759 .word 0x20008759
80127c0: 20008754 .word 0x20008754
80127c4: 20008758 .word 0x20008758
80127c8: 20008756 .word 0x20008756
}
}
tcp_input_pcb = pcb;
80127cc: 4a9b ldr r2, [pc, #620] ; (8012a3c <tcp_input+0x7d4>)
80127ce: 69fb ldr r3, [r7, #28]
80127d0: 6013 str r3, [r2, #0]
err = tcp_process(pcb);
80127d2: 69f8 ldr r0, [r7, #28]
80127d4: f000 fb0a bl 8012dec <tcp_process>
80127d8: 4603 mov r3, r0
80127da: 74fb strb r3, [r7, #19]
/* A return value of ERR_ABRT means that tcp_abort() was called
and that the pcb has been freed. If so, we don't do anything. */
if (err != ERR_ABRT) {
80127dc: f997 3013 ldrsb.w r3, [r7, #19]
80127e0: f113 0f0d cmn.w r3, #13
80127e4: f000 80d3 beq.w 801298e <tcp_input+0x726>
if (recv_flags & TF_RESET) {
80127e8: 4b95 ldr r3, [pc, #596] ; (8012a40 <tcp_input+0x7d8>)
80127ea: 781b ldrb r3, [r3, #0]
80127ec: f003 0308 and.w r3, r3, #8
80127f0: 2b00 cmp r3, #0
80127f2: d015 beq.n 8012820 <tcp_input+0x5b8>
/* TF_RESET means that the connection was reset by the other
end. We then call the error callback to inform the
application that the connection is dead before we
deallocate the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
80127f4: 69fb ldr r3, [r7, #28]
80127f6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
80127fa: 2b00 cmp r3, #0
80127fc: d008 beq.n 8012810 <tcp_input+0x5a8>
80127fe: 69fb ldr r3, [r7, #28]
8012800: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012804: 69fa ldr r2, [r7, #28]
8012806: 6912 ldr r2, [r2, #16]
8012808: f06f 010d mvn.w r1, #13
801280c: 4610 mov r0, r2
801280e: 4798 blx r3
tcp_pcb_remove(&tcp_active_pcbs, pcb);
8012810: 69f9 ldr r1, [r7, #28]
8012812: 488c ldr r0, [pc, #560] ; (8012a44 <tcp_input+0x7dc>)
8012814: f7ff fbb0 bl 8011f78 <tcp_pcb_remove>
tcp_free(pcb);
8012818: 69f8 ldr r0, [r7, #28]
801281a: f7fe f9a9 bl 8010b70 <tcp_free>
801281e: e0c1 b.n 80129a4 <tcp_input+0x73c>
} else {
err = ERR_OK;
8012820: 2300 movs r3, #0
8012822: 74fb strb r3, [r7, #19]
/* If the application has registered a "sent" function to be
called when new send buffer space is available, we call it
now. */
if (recv_acked > 0) {
8012824: 4b88 ldr r3, [pc, #544] ; (8012a48 <tcp_input+0x7e0>)
8012826: 881b ldrh r3, [r3, #0]
8012828: 2b00 cmp r3, #0
801282a: d01d beq.n 8012868 <tcp_input+0x600>
while (acked > 0) {
acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
acked -= acked16;
#else
{
acked16 = recv_acked;
801282c: 4b86 ldr r3, [pc, #536] ; (8012a48 <tcp_input+0x7e0>)
801282e: 881b ldrh r3, [r3, #0]
8012830: 81fb strh r3, [r7, #14]
#endif
TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
8012832: 69fb ldr r3, [r7, #28]
8012834: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8012838: 2b00 cmp r3, #0
801283a: d00a beq.n 8012852 <tcp_input+0x5ea>
801283c: 69fb ldr r3, [r7, #28]
801283e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8012842: 69fa ldr r2, [r7, #28]
8012844: 6910 ldr r0, [r2, #16]
8012846: 89fa ldrh r2, [r7, #14]
8012848: 69f9 ldr r1, [r7, #28]
801284a: 4798 blx r3
801284c: 4603 mov r3, r0
801284e: 74fb strb r3, [r7, #19]
8012850: e001 b.n 8012856 <tcp_input+0x5ee>
8012852: 2300 movs r3, #0
8012854: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012856: f997 3013 ldrsb.w r3, [r7, #19]
801285a: f113 0f0d cmn.w r3, #13
801285e: f000 8098 beq.w 8012992 <tcp_input+0x72a>
goto aborted;
}
}
recv_acked = 0;
8012862: 4b79 ldr r3, [pc, #484] ; (8012a48 <tcp_input+0x7e0>)
8012864: 2200 movs r2, #0
8012866: 801a strh r2, [r3, #0]
}
if (tcp_input_delayed_close(pcb)) {
8012868: 69f8 ldr r0, [r7, #28]
801286a: f000 f905 bl 8012a78 <tcp_input_delayed_close>
801286e: 4603 mov r3, r0
8012870: 2b00 cmp r3, #0
8012872: f040 8090 bne.w 8012996 <tcp_input+0x72e>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
while (recv_data != NULL) {
struct pbuf *rest = NULL;
pbuf_split_64k(recv_data, &rest);
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
if (recv_data != NULL) {
8012876: 4b75 ldr r3, [pc, #468] ; (8012a4c <tcp_input+0x7e4>)
8012878: 681b ldr r3, [r3, #0]
801287a: 2b00 cmp r3, #0
801287c: d041 beq.n 8012902 <tcp_input+0x69a>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
801287e: 69fb ldr r3, [r7, #28]
8012880: 6f9b ldr r3, [r3, #120] ; 0x78
8012882: 2b00 cmp r3, #0
8012884: d006 beq.n 8012894 <tcp_input+0x62c>
8012886: 4b72 ldr r3, [pc, #456] ; (8012a50 <tcp_input+0x7e8>)
8012888: f44f 72f3 mov.w r2, #486 ; 0x1e6
801288c: 4971 ldr r1, [pc, #452] ; (8012a54 <tcp_input+0x7ec>)
801288e: 4872 ldr r0, [pc, #456] ; (8012a58 <tcp_input+0x7f0>)
8012890: f008 fbc8 bl 801b024 <iprintf>
if (pcb->flags & TF_RXCLOSED) {
8012894: 69fb ldr r3, [r7, #28]
8012896: 8b5b ldrh r3, [r3, #26]
8012898: f003 0310 and.w r3, r3, #16
801289c: 2b00 cmp r3, #0
801289e: d008 beq.n 80128b2 <tcp_input+0x64a>
/* received data although already closed -> abort (send RST) to
notify the remote host that not all data has been processed */
pbuf_free(recv_data);
80128a0: 4b6a ldr r3, [pc, #424] ; (8012a4c <tcp_input+0x7e4>)
80128a2: 681b ldr r3, [r3, #0]
80128a4: 4618 mov r0, r3
80128a6: f7fd fea7 bl 80105f8 <pbuf_free>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_free(rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
tcp_abort(pcb);
80128aa: 69f8 ldr r0, [r7, #28]
80128ac: f7fe fc40 bl 8011130 <tcp_abort>
goto aborted;
80128b0: e078 b.n 80129a4 <tcp_input+0x73c>
}
/* Notify application that data has been received. */
TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
80128b2: 69fb ldr r3, [r7, #28]
80128b4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80128b8: 2b00 cmp r3, #0
80128ba: d00c beq.n 80128d6 <tcp_input+0x66e>
80128bc: 69fb ldr r3, [r7, #28]
80128be: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
80128c2: 69fb ldr r3, [r7, #28]
80128c4: 6918 ldr r0, [r3, #16]
80128c6: 4b61 ldr r3, [pc, #388] ; (8012a4c <tcp_input+0x7e4>)
80128c8: 681a ldr r2, [r3, #0]
80128ca: 2300 movs r3, #0
80128cc: 69f9 ldr r1, [r7, #28]
80128ce: 47a0 blx r4
80128d0: 4603 mov r3, r0
80128d2: 74fb strb r3, [r7, #19]
80128d4: e008 b.n 80128e8 <tcp_input+0x680>
80128d6: 4b5d ldr r3, [pc, #372] ; (8012a4c <tcp_input+0x7e4>)
80128d8: 681a ldr r2, [r3, #0]
80128da: 2300 movs r3, #0
80128dc: 69f9 ldr r1, [r7, #28]
80128de: 2000 movs r0, #0
80128e0: f7ff f952 bl 8011b88 <tcp_recv_null>
80128e4: 4603 mov r3, r0
80128e6: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
80128e8: f997 3013 ldrsb.w r3, [r7, #19]
80128ec: f113 0f0d cmn.w r3, #13
80128f0: d053 beq.n 801299a <tcp_input+0x732>
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
goto aborted;
}
/* If the upper layer can't receive this data, store it */
if (err != ERR_OK) {
80128f2: f997 3013 ldrsb.w r3, [r7, #19]
80128f6: 2b00 cmp r3, #0
80128f8: d003 beq.n 8012902 <tcp_input+0x69a>
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
if (rest != NULL) {
pbuf_cat(recv_data, rest);
}
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
pcb->refused_data = recv_data;
80128fa: 4b54 ldr r3, [pc, #336] ; (8012a4c <tcp_input+0x7e4>)
80128fc: 681a ldr r2, [r3, #0]
80128fe: 69fb ldr r3, [r7, #28]
8012900: 679a str r2, [r3, #120] ; 0x78
}
}
/* If a FIN segment was received, we call the callback
function with a NULL buffer to indicate EOF. */
if (recv_flags & TF_GOT_FIN) {
8012902: 4b4f ldr r3, [pc, #316] ; (8012a40 <tcp_input+0x7d8>)
8012904: 781b ldrb r3, [r3, #0]
8012906: f003 0320 and.w r3, r3, #32
801290a: 2b00 cmp r3, #0
801290c: d030 beq.n 8012970 <tcp_input+0x708>
if (pcb->refused_data != NULL) {
801290e: 69fb ldr r3, [r7, #28]
8012910: 6f9b ldr r3, [r3, #120] ; 0x78
8012912: 2b00 cmp r3, #0
8012914: d009 beq.n 801292a <tcp_input+0x6c2>
/* Delay this if we have refused data. */
pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
8012916: 69fb ldr r3, [r7, #28]
8012918: 6f9b ldr r3, [r3, #120] ; 0x78
801291a: 7b5a ldrb r2, [r3, #13]
801291c: 69fb ldr r3, [r7, #28]
801291e: 6f9b ldr r3, [r3, #120] ; 0x78
8012920: f042 0220 orr.w r2, r2, #32
8012924: b2d2 uxtb r2, r2
8012926: 735a strb r2, [r3, #13]
8012928: e022 b.n 8012970 <tcp_input+0x708>
} else {
/* correct rcv_wnd as the application won't call tcp_recved()
for the FIN's seqno */
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
801292a: 69fb ldr r3, [r7, #28]
801292c: 8d1b ldrh r3, [r3, #40] ; 0x28
801292e: f5b3 6f06 cmp.w r3, #2144 ; 0x860
8012932: d005 beq.n 8012940 <tcp_input+0x6d8>
pcb->rcv_wnd++;
8012934: 69fb ldr r3, [r7, #28]
8012936: 8d1b ldrh r3, [r3, #40] ; 0x28
8012938: 3301 adds r3, #1
801293a: b29a uxth r2, r3
801293c: 69fb ldr r3, [r7, #28]
801293e: 851a strh r2, [r3, #40] ; 0x28
}
TCP_EVENT_CLOSED(pcb, err);
8012940: 69fb ldr r3, [r7, #28]
8012942: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8012946: 2b00 cmp r3, #0
8012948: d00b beq.n 8012962 <tcp_input+0x6fa>
801294a: 69fb ldr r3, [r7, #28]
801294c: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
8012950: 69fb ldr r3, [r7, #28]
8012952: 6918 ldr r0, [r3, #16]
8012954: 2300 movs r3, #0
8012956: 2200 movs r2, #0
8012958: 69f9 ldr r1, [r7, #28]
801295a: 47a0 blx r4
801295c: 4603 mov r3, r0
801295e: 74fb strb r3, [r7, #19]
8012960: e001 b.n 8012966 <tcp_input+0x6fe>
8012962: 2300 movs r3, #0
8012964: 74fb strb r3, [r7, #19]
if (err == ERR_ABRT) {
8012966: f997 3013 ldrsb.w r3, [r7, #19]
801296a: f113 0f0d cmn.w r3, #13
801296e: d016 beq.n 801299e <tcp_input+0x736>
goto aborted;
}
}
}
tcp_input_pcb = NULL;
8012970: 4b32 ldr r3, [pc, #200] ; (8012a3c <tcp_input+0x7d4>)
8012972: 2200 movs r2, #0
8012974: 601a str r2, [r3, #0]
if (tcp_input_delayed_close(pcb)) {
8012976: 69f8 ldr r0, [r7, #28]
8012978: f000 f87e bl 8012a78 <tcp_input_delayed_close>
801297c: 4603 mov r3, r0
801297e: 2b00 cmp r3, #0
8012980: d10f bne.n 80129a2 <tcp_input+0x73a>
goto aborted;
}
/* Try to send something out. */
tcp_output(pcb);
8012982: 69f8 ldr r0, [r7, #28]
8012984: f002 fab6 bl 8014ef4 <tcp_output>
8012988: e00c b.n 80129a4 <tcp_input+0x73c>
goto aborted;
801298a: bf00 nop
801298c: e00a b.n 80129a4 <tcp_input+0x73c>
#endif /* TCP_INPUT_DEBUG */
}
}
/* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
Below this line, 'pcb' may not be dereferenced! */
aborted:
801298e: bf00 nop
8012990: e008 b.n 80129a4 <tcp_input+0x73c>
goto aborted;
8012992: bf00 nop
8012994: e006 b.n 80129a4 <tcp_input+0x73c>
goto aborted;
8012996: bf00 nop
8012998: e004 b.n 80129a4 <tcp_input+0x73c>
goto aborted;
801299a: bf00 nop
801299c: e002 b.n 80129a4 <tcp_input+0x73c>
goto aborted;
801299e: bf00 nop
80129a0: e000 b.n 80129a4 <tcp_input+0x73c>
goto aborted;
80129a2: bf00 nop
tcp_input_pcb = NULL;
80129a4: 4b25 ldr r3, [pc, #148] ; (8012a3c <tcp_input+0x7d4>)
80129a6: 2200 movs r2, #0
80129a8: 601a str r2, [r3, #0]
recv_data = NULL;
80129aa: 4b28 ldr r3, [pc, #160] ; (8012a4c <tcp_input+0x7e4>)
80129ac: 2200 movs r2, #0
80129ae: 601a str r2, [r3, #0]
/* give up our reference to inseg.p */
if (inseg.p != NULL) {
80129b0: 4b2a ldr r3, [pc, #168] ; (8012a5c <tcp_input+0x7f4>)
80129b2: 685b ldr r3, [r3, #4]
80129b4: 2b00 cmp r3, #0
80129b6: d03d beq.n 8012a34 <tcp_input+0x7cc>
pbuf_free(inseg.p);
80129b8: 4b28 ldr r3, [pc, #160] ; (8012a5c <tcp_input+0x7f4>)
80129ba: 685b ldr r3, [r3, #4]
80129bc: 4618 mov r0, r3
80129be: f7fd fe1b bl 80105f8 <pbuf_free>
inseg.p = NULL;
80129c2: 4b26 ldr r3, [pc, #152] ; (8012a5c <tcp_input+0x7f4>)
80129c4: 2200 movs r2, #0
80129c6: 605a str r2, [r3, #4]
pbuf_free(p);
}
LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
PERF_STOP("tcp_input");
return;
80129c8: e034 b.n 8012a34 <tcp_input+0x7cc>
if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
80129ca: 4b25 ldr r3, [pc, #148] ; (8012a60 <tcp_input+0x7f8>)
80129cc: 681b ldr r3, [r3, #0]
80129ce: 899b ldrh r3, [r3, #12]
80129d0: b29b uxth r3, r3
80129d2: 4618 mov r0, r3
80129d4: f7fc fa5c bl 800ee90 <lwip_htons>
80129d8: 4603 mov r3, r0
80129da: b2db uxtb r3, r3
80129dc: f003 0304 and.w r3, r3, #4
80129e0: 2b00 cmp r3, #0
80129e2: d118 bne.n 8012a16 <tcp_input+0x7ae>
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129e4: 4b1f ldr r3, [pc, #124] ; (8012a64 <tcp_input+0x7fc>)
80129e6: 6819 ldr r1, [r3, #0]
80129e8: 4b1f ldr r3, [pc, #124] ; (8012a68 <tcp_input+0x800>)
80129ea: 881b ldrh r3, [r3, #0]
80129ec: 461a mov r2, r3
80129ee: 4b1f ldr r3, [pc, #124] ; (8012a6c <tcp_input+0x804>)
80129f0: 681b ldr r3, [r3, #0]
80129f2: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129f4: 4b1a ldr r3, [pc, #104] ; (8012a60 <tcp_input+0x7f8>)
80129f6: 681b ldr r3, [r3, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
80129f8: 885b ldrh r3, [r3, #2]
80129fa: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80129fc: 4a18 ldr r2, [pc, #96] ; (8012a60 <tcp_input+0x7f8>)
80129fe: 6812 ldr r2, [r2, #0]
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
8012a00: 8812 ldrh r2, [r2, #0]
8012a02: b292 uxth r2, r2
8012a04: 9202 str r2, [sp, #8]
8012a06: 9301 str r3, [sp, #4]
8012a08: 4b19 ldr r3, [pc, #100] ; (8012a70 <tcp_input+0x808>)
8012a0a: 9300 str r3, [sp, #0]
8012a0c: 4b19 ldr r3, [pc, #100] ; (8012a74 <tcp_input+0x80c>)
8012a0e: 4602 mov r2, r0
8012a10: 2000 movs r0, #0
8012a12: f003 f835 bl 8015a80 <tcp_rst>
pbuf_free(p);
8012a16: 6878 ldr r0, [r7, #4]
8012a18: f7fd fdee bl 80105f8 <pbuf_free>
return;
8012a1c: e00a b.n 8012a34 <tcp_input+0x7cc>
goto dropped;
8012a1e: bf00 nop
8012a20: e004 b.n 8012a2c <tcp_input+0x7c4>
dropped:
8012a22: bf00 nop
8012a24: e002 b.n 8012a2c <tcp_input+0x7c4>
goto dropped;
8012a26: bf00 nop
8012a28: e000 b.n 8012a2c <tcp_input+0x7c4>
goto dropped;
8012a2a: bf00 nop
TCP_STATS_INC(tcp.drop);
MIB2_STATS_INC(mib2.tcpinerrs);
pbuf_free(p);
8012a2c: 6878 ldr r0, [r7, #4]
8012a2e: f7fd fde3 bl 80105f8 <pbuf_free>
8012a32: e000 b.n 8012a36 <tcp_input+0x7ce>
return;
8012a34: bf00 nop
}
8012a36: 3724 adds r7, #36 ; 0x24
8012a38: 46bd mov sp, r7
8012a3a: bd90 pop {r4, r7, pc}
8012a3c: 2000f5d4 .word 0x2000f5d4
8012a40: 20008759 .word 0x20008759
8012a44: 2000f5c0 .word 0x2000f5c0
8012a48: 20008754 .word 0x20008754
8012a4c: 2000875c .word 0x2000875c
8012a50: 0801d2c0 .word 0x0801d2c0
8012a54: 0801d474 .word 0x0801d474
8012a58: 0801d30c .word 0x0801d30c
8012a5c: 2000872c .word 0x2000872c
8012a60: 2000873c .word 0x2000873c
8012a64: 20008750 .word 0x20008750
8012a68: 20008756 .word 0x20008756
8012a6c: 2000874c .word 0x2000874c
8012a70: 2000be9c .word 0x2000be9c
8012a74: 2000bea0 .word 0x2000bea0
08012a78 <tcp_input_delayed_close>:
* any more.
* @returns 1 if the pcb has been closed and deallocated, 0 otherwise
*/
static int
tcp_input_delayed_close(struct tcp_pcb *pcb)
{
8012a78: b580 push {r7, lr}
8012a7a: b082 sub sp, #8
8012a7c: af00 add r7, sp, #0
8012a7e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
8012a80: 687b ldr r3, [r7, #4]
8012a82: 2b00 cmp r3, #0
8012a84: d106 bne.n 8012a94 <tcp_input_delayed_close+0x1c>
8012a86: 4b17 ldr r3, [pc, #92] ; (8012ae4 <tcp_input_delayed_close+0x6c>)
8012a88: f240 225a movw r2, #602 ; 0x25a
8012a8c: 4916 ldr r1, [pc, #88] ; (8012ae8 <tcp_input_delayed_close+0x70>)
8012a8e: 4817 ldr r0, [pc, #92] ; (8012aec <tcp_input_delayed_close+0x74>)
8012a90: f008 fac8 bl 801b024 <iprintf>
if (recv_flags & TF_CLOSED) {
8012a94: 4b16 ldr r3, [pc, #88] ; (8012af0 <tcp_input_delayed_close+0x78>)
8012a96: 781b ldrb r3, [r3, #0]
8012a98: f003 0310 and.w r3, r3, #16
8012a9c: 2b00 cmp r3, #0
8012a9e: d01c beq.n 8012ada <tcp_input_delayed_close+0x62>
/* The connection has been closed and we will deallocate the
PCB. */
if (!(pcb->flags & TF_RXCLOSED)) {
8012aa0: 687b ldr r3, [r7, #4]
8012aa2: 8b5b ldrh r3, [r3, #26]
8012aa4: f003 0310 and.w r3, r3, #16
8012aa8: 2b00 cmp r3, #0
8012aaa: d10d bne.n 8012ac8 <tcp_input_delayed_close+0x50>
/* Connection closed although the application has only shut down the
tx side: call the PCB's err callback and indicate the closure to
ensure the application doesn't continue using the PCB. */
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
8012aac: 687b ldr r3, [r7, #4]
8012aae: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012ab2: 2b00 cmp r3, #0
8012ab4: d008 beq.n 8012ac8 <tcp_input_delayed_close+0x50>
8012ab6: 687b ldr r3, [r7, #4]
8012ab8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8012abc: 687a ldr r2, [r7, #4]
8012abe: 6912 ldr r2, [r2, #16]
8012ac0: f06f 010e mvn.w r1, #14
8012ac4: 4610 mov r0, r2
8012ac6: 4798 blx r3
}
tcp_pcb_remove(&tcp_active_pcbs, pcb);
8012ac8: 6879 ldr r1, [r7, #4]
8012aca: 480a ldr r0, [pc, #40] ; (8012af4 <tcp_input_delayed_close+0x7c>)
8012acc: f7ff fa54 bl 8011f78 <tcp_pcb_remove>
tcp_free(pcb);
8012ad0: 6878 ldr r0, [r7, #4]
8012ad2: f7fe f84d bl 8010b70 <tcp_free>
return 1;
8012ad6: 2301 movs r3, #1
8012ad8: e000 b.n 8012adc <tcp_input_delayed_close+0x64>
}
return 0;
8012ada: 2300 movs r3, #0
}
8012adc: 4618 mov r0, r3
8012ade: 3708 adds r7, #8
8012ae0: 46bd mov sp, r7
8012ae2: bd80 pop {r7, pc}
8012ae4: 0801d2c0 .word 0x0801d2c0
8012ae8: 0801d490 .word 0x0801d490
8012aec: 0801d30c .word 0x0801d30c
8012af0: 20008759 .word 0x20008759
8012af4: 2000f5c0 .word 0x2000f5c0
08012af8 <tcp_listen_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_listen_input(struct tcp_pcb_listen *pcb)
{
8012af8: b590 push {r4, r7, lr}
8012afa: b08b sub sp, #44 ; 0x2c
8012afc: af04 add r7, sp, #16
8012afe: 6078 str r0, [r7, #4]
struct tcp_pcb *npcb;
u32_t iss;
err_t rc;
if (flags & TCP_RST) {
8012b00: 4b6f ldr r3, [pc, #444] ; (8012cc0 <tcp_listen_input+0x1c8>)
8012b02: 781b ldrb r3, [r3, #0]
8012b04: f003 0304 and.w r3, r3, #4
8012b08: 2b00 cmp r3, #0
8012b0a: f040 80d3 bne.w 8012cb4 <tcp_listen_input+0x1bc>
/* An incoming RST should be ignored. Return. */
return;
}
LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
8012b0e: 687b ldr r3, [r7, #4]
8012b10: 2b00 cmp r3, #0
8012b12: d106 bne.n 8012b22 <tcp_listen_input+0x2a>
8012b14: 4b6b ldr r3, [pc, #428] ; (8012cc4 <tcp_listen_input+0x1cc>)
8012b16: f240 2281 movw r2, #641 ; 0x281
8012b1a: 496b ldr r1, [pc, #428] ; (8012cc8 <tcp_listen_input+0x1d0>)
8012b1c: 486b ldr r0, [pc, #428] ; (8012ccc <tcp_listen_input+0x1d4>)
8012b1e: f008 fa81 bl 801b024 <iprintf>
/* In the LISTEN state, we check for incoming SYN segments,
creates a new PCB, and responds with a SYN|ACK. */
if (flags & TCP_ACK) {
8012b22: 4b67 ldr r3, [pc, #412] ; (8012cc0 <tcp_listen_input+0x1c8>)
8012b24: 781b ldrb r3, [r3, #0]
8012b26: f003 0310 and.w r3, r3, #16
8012b2a: 2b00 cmp r3, #0
8012b2c: d019 beq.n 8012b62 <tcp_listen_input+0x6a>
/* For incoming segments with the ACK flag set, respond with a
RST. */
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b2e: 4b68 ldr r3, [pc, #416] ; (8012cd0 <tcp_listen_input+0x1d8>)
8012b30: 6819 ldr r1, [r3, #0]
8012b32: 4b68 ldr r3, [pc, #416] ; (8012cd4 <tcp_listen_input+0x1dc>)
8012b34: 881b ldrh r3, [r3, #0]
8012b36: 461a mov r2, r3
8012b38: 4b67 ldr r3, [pc, #412] ; (8012cd8 <tcp_listen_input+0x1e0>)
8012b3a: 681b ldr r3, [r3, #0]
8012b3c: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b3e: 4b67 ldr r3, [pc, #412] ; (8012cdc <tcp_listen_input+0x1e4>)
8012b40: 681b ldr r3, [r3, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b42: 885b ldrh r3, [r3, #2]
8012b44: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012b46: 4a65 ldr r2, [pc, #404] ; (8012cdc <tcp_listen_input+0x1e4>)
8012b48: 6812 ldr r2, [r2, #0]
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012b4a: 8812 ldrh r2, [r2, #0]
8012b4c: b292 uxth r2, r2
8012b4e: 9202 str r2, [sp, #8]
8012b50: 9301 str r3, [sp, #4]
8012b52: 4b63 ldr r3, [pc, #396] ; (8012ce0 <tcp_listen_input+0x1e8>)
8012b54: 9300 str r3, [sp, #0]
8012b56: 4b63 ldr r3, [pc, #396] ; (8012ce4 <tcp_listen_input+0x1ec>)
8012b58: 4602 mov r2, r0
8012b5a: 6878 ldr r0, [r7, #4]
8012b5c: f002 ff90 bl 8015a80 <tcp_rst>
tcp_abandon(npcb, 0);
return;
}
tcp_output(npcb);
}
return;
8012b60: e0aa b.n 8012cb8 <tcp_listen_input+0x1c0>
} else if (flags & TCP_SYN) {
8012b62: 4b57 ldr r3, [pc, #348] ; (8012cc0 <tcp_listen_input+0x1c8>)
8012b64: 781b ldrb r3, [r3, #0]
8012b66: f003 0302 and.w r3, r3, #2
8012b6a: 2b00 cmp r3, #0
8012b6c: f000 80a4 beq.w 8012cb8 <tcp_listen_input+0x1c0>
npcb = tcp_alloc(pcb->prio);
8012b70: 687b ldr r3, [r7, #4]
8012b72: 7d5b ldrb r3, [r3, #21]
8012b74: 4618 mov r0, r3
8012b76: f7ff f92b bl 8011dd0 <tcp_alloc>
8012b7a: 6178 str r0, [r7, #20]
if (npcb == NULL) {
8012b7c: 697b ldr r3, [r7, #20]
8012b7e: 2b00 cmp r3, #0
8012b80: d111 bne.n 8012ba6 <tcp_listen_input+0xae>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012b82: 687b ldr r3, [r7, #4]
8012b84: 699b ldr r3, [r3, #24]
8012b86: 2b00 cmp r3, #0
8012b88: d00a beq.n 8012ba0 <tcp_listen_input+0xa8>
8012b8a: 687b ldr r3, [r7, #4]
8012b8c: 699b ldr r3, [r3, #24]
8012b8e: 687a ldr r2, [r7, #4]
8012b90: 6910 ldr r0, [r2, #16]
8012b92: f04f 32ff mov.w r2, #4294967295
8012b96: 2100 movs r1, #0
8012b98: 4798 blx r3
8012b9a: 4603 mov r3, r0
8012b9c: 73bb strb r3, [r7, #14]
return;
8012b9e: e08c b.n 8012cba <tcp_listen_input+0x1c2>
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
8012ba0: 23f0 movs r3, #240 ; 0xf0
8012ba2: 73bb strb r3, [r7, #14]
return;
8012ba4: e089 b.n 8012cba <tcp_listen_input+0x1c2>
ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
8012ba6: 4b50 ldr r3, [pc, #320] ; (8012ce8 <tcp_listen_input+0x1f0>)
8012ba8: 695a ldr r2, [r3, #20]
8012baa: 697b ldr r3, [r7, #20]
8012bac: 601a str r2, [r3, #0]
ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
8012bae: 4b4e ldr r3, [pc, #312] ; (8012ce8 <tcp_listen_input+0x1f0>)
8012bb0: 691a ldr r2, [r3, #16]
8012bb2: 697b ldr r3, [r7, #20]
8012bb4: 605a str r2, [r3, #4]
npcb->local_port = pcb->local_port;
8012bb6: 687b ldr r3, [r7, #4]
8012bb8: 8ada ldrh r2, [r3, #22]
8012bba: 697b ldr r3, [r7, #20]
8012bbc: 82da strh r2, [r3, #22]
npcb->remote_port = tcphdr->src;
8012bbe: 4b47 ldr r3, [pc, #284] ; (8012cdc <tcp_listen_input+0x1e4>)
8012bc0: 681b ldr r3, [r3, #0]
8012bc2: 881b ldrh r3, [r3, #0]
8012bc4: b29a uxth r2, r3
8012bc6: 697b ldr r3, [r7, #20]
8012bc8: 831a strh r2, [r3, #24]
npcb->state = SYN_RCVD;
8012bca: 697b ldr r3, [r7, #20]
8012bcc: 2203 movs r2, #3
8012bce: 751a strb r2, [r3, #20]
npcb->rcv_nxt = seqno + 1;
8012bd0: 4b41 ldr r3, [pc, #260] ; (8012cd8 <tcp_listen_input+0x1e0>)
8012bd2: 681b ldr r3, [r3, #0]
8012bd4: 1c5a adds r2, r3, #1
8012bd6: 697b ldr r3, [r7, #20]
8012bd8: 625a str r2, [r3, #36] ; 0x24
npcb->rcv_ann_right_edge = npcb->rcv_nxt;
8012bda: 697b ldr r3, [r7, #20]
8012bdc: 6a5a ldr r2, [r3, #36] ; 0x24
8012bde: 697b ldr r3, [r7, #20]
8012be0: 62da str r2, [r3, #44] ; 0x2c
iss = tcp_next_iss(npcb);
8012be2: 6978 ldr r0, [r7, #20]
8012be4: f7ff fa5c bl 80120a0 <tcp_next_iss>
8012be8: 6138 str r0, [r7, #16]
npcb->snd_wl2 = iss;
8012bea: 697b ldr r3, [r7, #20]
8012bec: 693a ldr r2, [r7, #16]
8012bee: 659a str r2, [r3, #88] ; 0x58
npcb->snd_nxt = iss;
8012bf0: 697b ldr r3, [r7, #20]
8012bf2: 693a ldr r2, [r7, #16]
8012bf4: 651a str r2, [r3, #80] ; 0x50
npcb->lastack = iss;
8012bf6: 697b ldr r3, [r7, #20]
8012bf8: 693a ldr r2, [r7, #16]
8012bfa: 645a str r2, [r3, #68] ; 0x44
npcb->snd_lbb = iss;
8012bfc: 697b ldr r3, [r7, #20]
8012bfe: 693a ldr r2, [r7, #16]
8012c00: 65da str r2, [r3, #92] ; 0x5c
npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
8012c02: 4b35 ldr r3, [pc, #212] ; (8012cd8 <tcp_listen_input+0x1e0>)
8012c04: 681b ldr r3, [r3, #0]
8012c06: 1e5a subs r2, r3, #1
8012c08: 697b ldr r3, [r7, #20]
8012c0a: 655a str r2, [r3, #84] ; 0x54
npcb->callback_arg = pcb->callback_arg;
8012c0c: 687b ldr r3, [r7, #4]
8012c0e: 691a ldr r2, [r3, #16]
8012c10: 697b ldr r3, [r7, #20]
8012c12: 611a str r2, [r3, #16]
npcb->listener = pcb;
8012c14: 697b ldr r3, [r7, #20]
8012c16: 687a ldr r2, [r7, #4]
8012c18: 67da str r2, [r3, #124] ; 0x7c
npcb->so_options = pcb->so_options & SOF_INHERITED;
8012c1a: 687b ldr r3, [r7, #4]
8012c1c: 7a5b ldrb r3, [r3, #9]
8012c1e: f003 030c and.w r3, r3, #12
8012c22: b2da uxtb r2, r3
8012c24: 697b ldr r3, [r7, #20]
8012c26: 725a strb r2, [r3, #9]
npcb->netif_idx = pcb->netif_idx;
8012c28: 687b ldr r3, [r7, #4]
8012c2a: 7a1a ldrb r2, [r3, #8]
8012c2c: 697b ldr r3, [r7, #20]
8012c2e: 721a strb r2, [r3, #8]
TCP_REG_ACTIVE(npcb);
8012c30: 4b2e ldr r3, [pc, #184] ; (8012cec <tcp_listen_input+0x1f4>)
8012c32: 681a ldr r2, [r3, #0]
8012c34: 697b ldr r3, [r7, #20]
8012c36: 60da str r2, [r3, #12]
8012c38: 4a2c ldr r2, [pc, #176] ; (8012cec <tcp_listen_input+0x1f4>)
8012c3a: 697b ldr r3, [r7, #20]
8012c3c: 6013 str r3, [r2, #0]
8012c3e: f003 f8e1 bl 8015e04 <tcp_timer_needed>
8012c42: 4b2b ldr r3, [pc, #172] ; (8012cf0 <tcp_listen_input+0x1f8>)
8012c44: 2201 movs r2, #1
8012c46: 701a strb r2, [r3, #0]
tcp_parseopt(npcb);
8012c48: 6978 ldr r0, [r7, #20]
8012c4a: f001 fd8f bl 801476c <tcp_parseopt>
npcb->snd_wnd = tcphdr->wnd;
8012c4e: 4b23 ldr r3, [pc, #140] ; (8012cdc <tcp_listen_input+0x1e4>)
8012c50: 681b ldr r3, [r3, #0]
8012c52: 89db ldrh r3, [r3, #14]
8012c54: b29a uxth r2, r3
8012c56: 697b ldr r3, [r7, #20]
8012c58: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
npcb->snd_wnd_max = npcb->snd_wnd;
8012c5c: 697b ldr r3, [r7, #20]
8012c5e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012c62: 697b ldr r3, [r7, #20]
8012c64: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
8012c68: 697b ldr r3, [r7, #20]
8012c6a: 8e5c ldrh r4, [r3, #50] ; 0x32
8012c6c: 697b ldr r3, [r7, #20]
8012c6e: 3304 adds r3, #4
8012c70: 4618 mov r0, r3
8012c72: f006 fe7d bl 8019970 <ip4_route>
8012c76: 4601 mov r1, r0
8012c78: 697b ldr r3, [r7, #20]
8012c7a: 3304 adds r3, #4
8012c7c: 461a mov r2, r3
8012c7e: 4620 mov r0, r4
8012c80: f7ff fa34 bl 80120ec <tcp_eff_send_mss_netif>
8012c84: 4603 mov r3, r0
8012c86: 461a mov r2, r3
8012c88: 697b ldr r3, [r7, #20]
8012c8a: 865a strh r2, [r3, #50] ; 0x32
rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
8012c8c: 2112 movs r1, #18
8012c8e: 6978 ldr r0, [r7, #20]
8012c90: f002 f842 bl 8014d18 <tcp_enqueue_flags>
8012c94: 4603 mov r3, r0
8012c96: 73fb strb r3, [r7, #15]
if (rc != ERR_OK) {
8012c98: f997 300f ldrsb.w r3, [r7, #15]
8012c9c: 2b00 cmp r3, #0
8012c9e: d004 beq.n 8012caa <tcp_listen_input+0x1b2>
tcp_abandon(npcb, 0);
8012ca0: 2100 movs r1, #0
8012ca2: 6978 ldr r0, [r7, #20]
8012ca4: f7fe f986 bl 8010fb4 <tcp_abandon>
return;
8012ca8: e007 b.n 8012cba <tcp_listen_input+0x1c2>
tcp_output(npcb);
8012caa: 6978 ldr r0, [r7, #20]
8012cac: f002 f922 bl 8014ef4 <tcp_output>
return;
8012cb0: bf00 nop
8012cb2: e001 b.n 8012cb8 <tcp_listen_input+0x1c0>
return;
8012cb4: bf00 nop
8012cb6: e000 b.n 8012cba <tcp_listen_input+0x1c2>
return;
8012cb8: bf00 nop
}
8012cba: 371c adds r7, #28
8012cbc: 46bd mov sp, r7
8012cbe: bd90 pop {r4, r7, pc}
8012cc0: 20008758 .word 0x20008758
8012cc4: 0801d2c0 .word 0x0801d2c0
8012cc8: 0801d4b8 .word 0x0801d4b8
8012ccc: 0801d30c .word 0x0801d30c
8012cd0: 20008750 .word 0x20008750
8012cd4: 20008756 .word 0x20008756
8012cd8: 2000874c .word 0x2000874c
8012cdc: 2000873c .word 0x2000873c
8012ce0: 2000be9c .word 0x2000be9c
8012ce4: 2000bea0 .word 0x2000bea0
8012ce8: 2000be8c .word 0x2000be8c
8012cec: 2000f5c0 .word 0x2000f5c0
8012cf0: 2000f5bc .word 0x2000f5bc
08012cf4 <tcp_timewait_input>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static void
tcp_timewait_input(struct tcp_pcb *pcb)
{
8012cf4: b580 push {r7, lr}
8012cf6: b086 sub sp, #24
8012cf8: af04 add r7, sp, #16
8012cfa: 6078 str r0, [r7, #4]
/* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
/* RFC 793 3.9 Event Processing - Segment Arrives:
* - first check sequence number - we skip that one in TIME_WAIT (always
* acceptable since we only send ACKs)
* - second check the RST bit (... return) */
if (flags & TCP_RST) {
8012cfc: 4b30 ldr r3, [pc, #192] ; (8012dc0 <tcp_timewait_input+0xcc>)
8012cfe: 781b ldrb r3, [r3, #0]
8012d00: f003 0304 and.w r3, r3, #4
8012d04: 2b00 cmp r3, #0
8012d06: d154 bne.n 8012db2 <tcp_timewait_input+0xbe>
return;
}
LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
8012d08: 687b ldr r3, [r7, #4]
8012d0a: 2b00 cmp r3, #0
8012d0c: d106 bne.n 8012d1c <tcp_timewait_input+0x28>
8012d0e: 4b2d ldr r3, [pc, #180] ; (8012dc4 <tcp_timewait_input+0xd0>)
8012d10: f240 22ee movw r2, #750 ; 0x2ee
8012d14: 492c ldr r1, [pc, #176] ; (8012dc8 <tcp_timewait_input+0xd4>)
8012d16: 482d ldr r0, [pc, #180] ; (8012dcc <tcp_timewait_input+0xd8>)
8012d18: f008 f984 bl 801b024 <iprintf>
/* - fourth, check the SYN bit, */
if (flags & TCP_SYN) {
8012d1c: 4b28 ldr r3, [pc, #160] ; (8012dc0 <tcp_timewait_input+0xcc>)
8012d1e: 781b ldrb r3, [r3, #0]
8012d20: f003 0302 and.w r3, r3, #2
8012d24: 2b00 cmp r3, #0
8012d26: d02a beq.n 8012d7e <tcp_timewait_input+0x8a>
/* If an incoming segment is not acceptable, an acknowledgment
should be sent in reply */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
8012d28: 4b29 ldr r3, [pc, #164] ; (8012dd0 <tcp_timewait_input+0xdc>)
8012d2a: 681a ldr r2, [r3, #0]
8012d2c: 687b ldr r3, [r7, #4]
8012d2e: 6a5b ldr r3, [r3, #36] ; 0x24
8012d30: 1ad3 subs r3, r2, r3
8012d32: 2b00 cmp r3, #0
8012d34: db2d blt.n 8012d92 <tcp_timewait_input+0x9e>
8012d36: 4b26 ldr r3, [pc, #152] ; (8012dd0 <tcp_timewait_input+0xdc>)
8012d38: 681a ldr r2, [r3, #0]
8012d3a: 687b ldr r3, [r7, #4]
8012d3c: 6a5b ldr r3, [r3, #36] ; 0x24
8012d3e: 6879 ldr r1, [r7, #4]
8012d40: 8d09 ldrh r1, [r1, #40] ; 0x28
8012d42: 440b add r3, r1
8012d44: 1ad3 subs r3, r2, r3
8012d46: 2b00 cmp r3, #0
8012d48: dc23 bgt.n 8012d92 <tcp_timewait_input+0x9e>
/* If the SYN is in the window it is an error, send a reset */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d4a: 4b22 ldr r3, [pc, #136] ; (8012dd4 <tcp_timewait_input+0xe0>)
8012d4c: 6819 ldr r1, [r3, #0]
8012d4e: 4b22 ldr r3, [pc, #136] ; (8012dd8 <tcp_timewait_input+0xe4>)
8012d50: 881b ldrh r3, [r3, #0]
8012d52: 461a mov r2, r3
8012d54: 4b1e ldr r3, [pc, #120] ; (8012dd0 <tcp_timewait_input+0xdc>)
8012d56: 681b ldr r3, [r3, #0]
8012d58: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d5a: 4b20 ldr r3, [pc, #128] ; (8012ddc <tcp_timewait_input+0xe8>)
8012d5c: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d5e: 885b ldrh r3, [r3, #2]
8012d60: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8012d62: 4a1e ldr r2, [pc, #120] ; (8012ddc <tcp_timewait_input+0xe8>)
8012d64: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8012d66: 8812 ldrh r2, [r2, #0]
8012d68: b292 uxth r2, r2
8012d6a: 9202 str r2, [sp, #8]
8012d6c: 9301 str r3, [sp, #4]
8012d6e: 4b1c ldr r3, [pc, #112] ; (8012de0 <tcp_timewait_input+0xec>)
8012d70: 9300 str r3, [sp, #0]
8012d72: 4b1c ldr r3, [pc, #112] ; (8012de4 <tcp_timewait_input+0xf0>)
8012d74: 4602 mov r2, r0
8012d76: 6878 ldr r0, [r7, #4]
8012d78: f002 fe82 bl 8015a80 <tcp_rst>
return;
8012d7c: e01c b.n 8012db8 <tcp_timewait_input+0xc4>
}
} else if (flags & TCP_FIN) {
8012d7e: 4b10 ldr r3, [pc, #64] ; (8012dc0 <tcp_timewait_input+0xcc>)
8012d80: 781b ldrb r3, [r3, #0]
8012d82: f003 0301 and.w r3, r3, #1
8012d86: 2b00 cmp r3, #0
8012d88: d003 beq.n 8012d92 <tcp_timewait_input+0x9e>
/* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
Restart the 2 MSL time-wait timeout.*/
pcb->tmr = tcp_ticks;
8012d8a: 4b17 ldr r3, [pc, #92] ; (8012de8 <tcp_timewait_input+0xf4>)
8012d8c: 681a ldr r2, [r3, #0]
8012d8e: 687b ldr r3, [r7, #4]
8012d90: 621a str r2, [r3, #32]
}
if ((tcplen > 0)) {
8012d92: 4b11 ldr r3, [pc, #68] ; (8012dd8 <tcp_timewait_input+0xe4>)
8012d94: 881b ldrh r3, [r3, #0]
8012d96: 2b00 cmp r3, #0
8012d98: d00d beq.n 8012db6 <tcp_timewait_input+0xc2>
/* Acknowledge data, FIN or out-of-window SYN */
tcp_ack_now(pcb);
8012d9a: 687b ldr r3, [r7, #4]
8012d9c: 8b5b ldrh r3, [r3, #26]
8012d9e: f043 0302 orr.w r3, r3, #2
8012da2: b29a uxth r2, r3
8012da4: 687b ldr r3, [r7, #4]
8012da6: 835a strh r2, [r3, #26]
tcp_output(pcb);
8012da8: 6878 ldr r0, [r7, #4]
8012daa: f002 f8a3 bl 8014ef4 <tcp_output>
}
return;
8012dae: bf00 nop
8012db0: e001 b.n 8012db6 <tcp_timewait_input+0xc2>
return;
8012db2: bf00 nop
8012db4: e000 b.n 8012db8 <tcp_timewait_input+0xc4>
return;
8012db6: bf00 nop
}
8012db8: 3708 adds r7, #8
8012dba: 46bd mov sp, r7
8012dbc: bd80 pop {r7, pc}
8012dbe: bf00 nop
8012dc0: 20008758 .word 0x20008758
8012dc4: 0801d2c0 .word 0x0801d2c0
8012dc8: 0801d4d8 .word 0x0801d4d8
8012dcc: 0801d30c .word 0x0801d30c
8012dd0: 2000874c .word 0x2000874c
8012dd4: 20008750 .word 0x20008750
8012dd8: 20008756 .word 0x20008756
8012ddc: 2000873c .word 0x2000873c
8012de0: 2000be9c .word 0x2000be9c
8012de4: 2000bea0 .word 0x2000bea0
8012de8: 2000f5c4 .word 0x2000f5c4
08012dec <tcp_process>:
* @note the segment which arrived is saved in global variables, therefore only the pcb
* involved is passed as a parameter to this function
*/
static err_t
tcp_process(struct tcp_pcb *pcb)
{
8012dec: b590 push {r4, r7, lr}
8012dee: b08d sub sp, #52 ; 0x34
8012df0: af04 add r7, sp, #16
8012df2: 6078 str r0, [r7, #4]
struct tcp_seg *rseg;
u8_t acceptable = 0;
8012df4: 2300 movs r3, #0
8012df6: 76fb strb r3, [r7, #27]
err_t err;
err = ERR_OK;
8012df8: 2300 movs r3, #0
8012dfa: 76bb strb r3, [r7, #26]
LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
8012dfc: 687b ldr r3, [r7, #4]
8012dfe: 2b00 cmp r3, #0
8012e00: d106 bne.n 8012e10 <tcp_process+0x24>
8012e02: 4ba5 ldr r3, [pc, #660] ; (8013098 <tcp_process+0x2ac>)
8012e04: f44f 7247 mov.w r2, #796 ; 0x31c
8012e08: 49a4 ldr r1, [pc, #656] ; (801309c <tcp_process+0x2b0>)
8012e0a: 48a5 ldr r0, [pc, #660] ; (80130a0 <tcp_process+0x2b4>)
8012e0c: f008 f90a bl 801b024 <iprintf>
/* Process incoming RST segments. */
if (flags & TCP_RST) {
8012e10: 4ba4 ldr r3, [pc, #656] ; (80130a4 <tcp_process+0x2b8>)
8012e12: 781b ldrb r3, [r3, #0]
8012e14: f003 0304 and.w r3, r3, #4
8012e18: 2b00 cmp r3, #0
8012e1a: d04e beq.n 8012eba <tcp_process+0xce>
/* First, determine if the reset is acceptable. */
if (pcb->state == SYN_SENT) {
8012e1c: 687b ldr r3, [r7, #4]
8012e1e: 7d1b ldrb r3, [r3, #20]
8012e20: 2b02 cmp r3, #2
8012e22: d108 bne.n 8012e36 <tcp_process+0x4a>
/* "In the SYN-SENT state (a RST received in response to an initial SYN),
the RST is acceptable if the ACK field acknowledges the SYN." */
if (ackno == pcb->snd_nxt) {
8012e24: 687b ldr r3, [r7, #4]
8012e26: 6d1a ldr r2, [r3, #80] ; 0x50
8012e28: 4b9f ldr r3, [pc, #636] ; (80130a8 <tcp_process+0x2bc>)
8012e2a: 681b ldr r3, [r3, #0]
8012e2c: 429a cmp r2, r3
8012e2e: d123 bne.n 8012e78 <tcp_process+0x8c>
acceptable = 1;
8012e30: 2301 movs r3, #1
8012e32: 76fb strb r3, [r7, #27]
8012e34: e020 b.n 8012e78 <tcp_process+0x8c>
}
} else {
/* "In all states except SYN-SENT, all reset (RST) segments are validated
by checking their SEQ-fields." */
if (seqno == pcb->rcv_nxt) {
8012e36: 687b ldr r3, [r7, #4]
8012e38: 6a5a ldr r2, [r3, #36] ; 0x24
8012e3a: 4b9c ldr r3, [pc, #624] ; (80130ac <tcp_process+0x2c0>)
8012e3c: 681b ldr r3, [r3, #0]
8012e3e: 429a cmp r2, r3
8012e40: d102 bne.n 8012e48 <tcp_process+0x5c>
acceptable = 1;
8012e42: 2301 movs r3, #1
8012e44: 76fb strb r3, [r7, #27]
8012e46: e017 b.n 8012e78 <tcp_process+0x8c>
} else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8012e48: 4b98 ldr r3, [pc, #608] ; (80130ac <tcp_process+0x2c0>)
8012e4a: 681a ldr r2, [r3, #0]
8012e4c: 687b ldr r3, [r7, #4]
8012e4e: 6a5b ldr r3, [r3, #36] ; 0x24
8012e50: 1ad3 subs r3, r2, r3
8012e52: 2b00 cmp r3, #0
8012e54: db10 blt.n 8012e78 <tcp_process+0x8c>
8012e56: 4b95 ldr r3, [pc, #596] ; (80130ac <tcp_process+0x2c0>)
8012e58: 681a ldr r2, [r3, #0]
8012e5a: 687b ldr r3, [r7, #4]
8012e5c: 6a5b ldr r3, [r3, #36] ; 0x24
8012e5e: 6879 ldr r1, [r7, #4]
8012e60: 8d09 ldrh r1, [r1, #40] ; 0x28
8012e62: 440b add r3, r1
8012e64: 1ad3 subs r3, r2, r3
8012e66: 2b00 cmp r3, #0
8012e68: dc06 bgt.n 8012e78 <tcp_process+0x8c>
pcb->rcv_nxt + pcb->rcv_wnd)) {
/* If the sequence number is inside the window, we send a challenge ACK
and wait for a re-send with matching sequence number.
This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
(RST spoofing attack), which is present in RFC 793 RST handling. */
tcp_ack_now(pcb);
8012e6a: 687b ldr r3, [r7, #4]
8012e6c: 8b5b ldrh r3, [r3, #26]
8012e6e: f043 0302 orr.w r3, r3, #2
8012e72: b29a uxth r2, r3
8012e74: 687b ldr r3, [r7, #4]
8012e76: 835a strh r2, [r3, #26]
}
}
if (acceptable) {
8012e78: 7efb ldrb r3, [r7, #27]
8012e7a: 2b00 cmp r3, #0
8012e7c: d01b beq.n 8012eb6 <tcp_process+0xca>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
8012e7e: 687b ldr r3, [r7, #4]
8012e80: 7d1b ldrb r3, [r3, #20]
8012e82: 2b00 cmp r3, #0
8012e84: d106 bne.n 8012e94 <tcp_process+0xa8>
8012e86: 4b84 ldr r3, [pc, #528] ; (8013098 <tcp_process+0x2ac>)
8012e88: f44f 724e mov.w r2, #824 ; 0x338
8012e8c: 4988 ldr r1, [pc, #544] ; (80130b0 <tcp_process+0x2c4>)
8012e8e: 4884 ldr r0, [pc, #528] ; (80130a0 <tcp_process+0x2b4>)
8012e90: f008 f8c8 bl 801b024 <iprintf>
recv_flags |= TF_RESET;
8012e94: 4b87 ldr r3, [pc, #540] ; (80130b4 <tcp_process+0x2c8>)
8012e96: 781b ldrb r3, [r3, #0]
8012e98: f043 0308 orr.w r3, r3, #8
8012e9c: b2da uxtb r2, r3
8012e9e: 4b85 ldr r3, [pc, #532] ; (80130b4 <tcp_process+0x2c8>)
8012ea0: 701a strb r2, [r3, #0]
tcp_clear_flags(pcb, TF_ACK_DELAY);
8012ea2: 687b ldr r3, [r7, #4]
8012ea4: 8b5b ldrh r3, [r3, #26]
8012ea6: f023 0301 bic.w r3, r3, #1
8012eaa: b29a uxth r2, r3
8012eac: 687b ldr r3, [r7, #4]
8012eae: 835a strh r2, [r3, #26]
return ERR_RST;
8012eb0: f06f 030d mvn.w r3, #13
8012eb4: e37a b.n 80135ac <tcp_process+0x7c0>
} else {
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
seqno, pcb->rcv_nxt));
return ERR_OK;
8012eb6: 2300 movs r3, #0
8012eb8: e378 b.n 80135ac <tcp_process+0x7c0>
}
}
if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
8012eba: 4b7a ldr r3, [pc, #488] ; (80130a4 <tcp_process+0x2b8>)
8012ebc: 781b ldrb r3, [r3, #0]
8012ebe: f003 0302 and.w r3, r3, #2
8012ec2: 2b00 cmp r3, #0
8012ec4: d010 beq.n 8012ee8 <tcp_process+0xfc>
8012ec6: 687b ldr r3, [r7, #4]
8012ec8: 7d1b ldrb r3, [r3, #20]
8012eca: 2b02 cmp r3, #2
8012ecc: d00c beq.n 8012ee8 <tcp_process+0xfc>
8012ece: 687b ldr r3, [r7, #4]
8012ed0: 7d1b ldrb r3, [r3, #20]
8012ed2: 2b03 cmp r3, #3
8012ed4: d008 beq.n 8012ee8 <tcp_process+0xfc>
/* Cope with new connection attempt after remote end crashed */
tcp_ack_now(pcb);
8012ed6: 687b ldr r3, [r7, #4]
8012ed8: 8b5b ldrh r3, [r3, #26]
8012eda: f043 0302 orr.w r3, r3, #2
8012ede: b29a uxth r2, r3
8012ee0: 687b ldr r3, [r7, #4]
8012ee2: 835a strh r2, [r3, #26]
return ERR_OK;
8012ee4: 2300 movs r3, #0
8012ee6: e361 b.n 80135ac <tcp_process+0x7c0>
}
if ((pcb->flags & TF_RXCLOSED) == 0) {
8012ee8: 687b ldr r3, [r7, #4]
8012eea: 8b5b ldrh r3, [r3, #26]
8012eec: f003 0310 and.w r3, r3, #16
8012ef0: 2b00 cmp r3, #0
8012ef2: d103 bne.n 8012efc <tcp_process+0x110>
/* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
pcb->tmr = tcp_ticks;
8012ef4: 4b70 ldr r3, [pc, #448] ; (80130b8 <tcp_process+0x2cc>)
8012ef6: 681a ldr r2, [r3, #0]
8012ef8: 687b ldr r3, [r7, #4]
8012efa: 621a str r2, [r3, #32]
}
pcb->keep_cnt_sent = 0;
8012efc: 687b ldr r3, [r7, #4]
8012efe: 2200 movs r2, #0
8012f00: f883 209b strb.w r2, [r3, #155] ; 0x9b
pcb->persist_probe = 0;
8012f04: 687b ldr r3, [r7, #4]
8012f06: 2200 movs r2, #0
8012f08: f883 209a strb.w r2, [r3, #154] ; 0x9a
tcp_parseopt(pcb);
8012f0c: 6878 ldr r0, [r7, #4]
8012f0e: f001 fc2d bl 801476c <tcp_parseopt>
/* Do different things depending on the TCP state. */
switch (pcb->state) {
8012f12: 687b ldr r3, [r7, #4]
8012f14: 7d1b ldrb r3, [r3, #20]
8012f16: 3b02 subs r3, #2
8012f18: 2b07 cmp r3, #7
8012f1a: f200 8337 bhi.w 801358c <tcp_process+0x7a0>
8012f1e: a201 add r2, pc, #4 ; (adr r2, 8012f24 <tcp_process+0x138>)
8012f20: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8012f24: 08012f45 .word 0x08012f45
8012f28: 08013175 .word 0x08013175
8012f2c: 080132ed .word 0x080132ed
8012f30: 08013317 .word 0x08013317
8012f34: 0801343b .word 0x0801343b
8012f38: 080132ed .word 0x080132ed
8012f3c: 080134c7 .word 0x080134c7
8012f40: 08013557 .word 0x08013557
case SYN_SENT:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
/* received SYN ACK with expected sequence number? */
if ((flags & TCP_ACK) && (flags & TCP_SYN)
8012f44: 4b57 ldr r3, [pc, #348] ; (80130a4 <tcp_process+0x2b8>)
8012f46: 781b ldrb r3, [r3, #0]
8012f48: f003 0310 and.w r3, r3, #16
8012f4c: 2b00 cmp r3, #0
8012f4e: f000 80e4 beq.w 801311a <tcp_process+0x32e>
8012f52: 4b54 ldr r3, [pc, #336] ; (80130a4 <tcp_process+0x2b8>)
8012f54: 781b ldrb r3, [r3, #0]
8012f56: f003 0302 and.w r3, r3, #2
8012f5a: 2b00 cmp r3, #0
8012f5c: f000 80dd beq.w 801311a <tcp_process+0x32e>
&& (ackno == pcb->lastack + 1)) {
8012f60: 687b ldr r3, [r7, #4]
8012f62: 6c5b ldr r3, [r3, #68] ; 0x44
8012f64: 1c5a adds r2, r3, #1
8012f66: 4b50 ldr r3, [pc, #320] ; (80130a8 <tcp_process+0x2bc>)
8012f68: 681b ldr r3, [r3, #0]
8012f6a: 429a cmp r2, r3
8012f6c: f040 80d5 bne.w 801311a <tcp_process+0x32e>
pcb->rcv_nxt = seqno + 1;
8012f70: 4b4e ldr r3, [pc, #312] ; (80130ac <tcp_process+0x2c0>)
8012f72: 681b ldr r3, [r3, #0]
8012f74: 1c5a adds r2, r3, #1
8012f76: 687b ldr r3, [r7, #4]
8012f78: 625a str r2, [r3, #36] ; 0x24
pcb->rcv_ann_right_edge = pcb->rcv_nxt;
8012f7a: 687b ldr r3, [r7, #4]
8012f7c: 6a5a ldr r2, [r3, #36] ; 0x24
8012f7e: 687b ldr r3, [r7, #4]
8012f80: 62da str r2, [r3, #44] ; 0x2c
pcb->lastack = ackno;
8012f82: 4b49 ldr r3, [pc, #292] ; (80130a8 <tcp_process+0x2bc>)
8012f84: 681a ldr r2, [r3, #0]
8012f86: 687b ldr r3, [r7, #4]
8012f88: 645a str r2, [r3, #68] ; 0x44
pcb->snd_wnd = tcphdr->wnd;
8012f8a: 4b4c ldr r3, [pc, #304] ; (80130bc <tcp_process+0x2d0>)
8012f8c: 681b ldr r3, [r3, #0]
8012f8e: 89db ldrh r3, [r3, #14]
8012f90: b29a uxth r2, r3
8012f92: 687b ldr r3, [r7, #4]
8012f94: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
pcb->snd_wnd_max = pcb->snd_wnd;
8012f98: 687b ldr r3, [r7, #4]
8012f9a: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8012f9e: 687b ldr r3, [r7, #4]
8012fa0: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
8012fa4: 4b41 ldr r3, [pc, #260] ; (80130ac <tcp_process+0x2c0>)
8012fa6: 681b ldr r3, [r3, #0]
8012fa8: 1e5a subs r2, r3, #1
8012faa: 687b ldr r3, [r7, #4]
8012fac: 655a str r2, [r3, #84] ; 0x54
pcb->state = ESTABLISHED;
8012fae: 687b ldr r3, [r7, #4]
8012fb0: 2204 movs r2, #4
8012fb2: 751a strb r2, [r3, #20]
#if TCP_CALCULATE_EFF_SEND_MSS
pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
8012fb4: 687b ldr r3, [r7, #4]
8012fb6: 8e5c ldrh r4, [r3, #50] ; 0x32
8012fb8: 687b ldr r3, [r7, #4]
8012fba: 3304 adds r3, #4
8012fbc: 4618 mov r0, r3
8012fbe: f006 fcd7 bl 8019970 <ip4_route>
8012fc2: 4601 mov r1, r0
8012fc4: 687b ldr r3, [r7, #4]
8012fc6: 3304 adds r3, #4
8012fc8: 461a mov r2, r3
8012fca: 4620 mov r0, r4
8012fcc: f7ff f88e bl 80120ec <tcp_eff_send_mss_netif>
8012fd0: 4603 mov r3, r0
8012fd2: 461a mov r2, r3
8012fd4: 687b ldr r3, [r7, #4]
8012fd6: 865a strh r2, [r3, #50] ; 0x32
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
8012fd8: 687b ldr r3, [r7, #4]
8012fda: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fdc: 009a lsls r2, r3, #2
8012fde: 687b ldr r3, [r7, #4]
8012fe0: 8e5b ldrh r3, [r3, #50] ; 0x32
8012fe2: 005b lsls r3, r3, #1
8012fe4: f241 111c movw r1, #4380 ; 0x111c
8012fe8: 428b cmp r3, r1
8012fea: bf38 it cc
8012fec: 460b movcc r3, r1
8012fee: 429a cmp r2, r3
8012ff0: d204 bcs.n 8012ffc <tcp_process+0x210>
8012ff2: 687b ldr r3, [r7, #4]
8012ff4: 8e5b ldrh r3, [r3, #50] ; 0x32
8012ff6: 009b lsls r3, r3, #2
8012ff8: b29b uxth r3, r3
8012ffa: e00d b.n 8013018 <tcp_process+0x22c>
8012ffc: 687b ldr r3, [r7, #4]
8012ffe: 8e5b ldrh r3, [r3, #50] ; 0x32
8013000: 005b lsls r3, r3, #1
8013002: f241 121c movw r2, #4380 ; 0x111c
8013006: 4293 cmp r3, r2
8013008: d904 bls.n 8013014 <tcp_process+0x228>
801300a: 687b ldr r3, [r7, #4]
801300c: 8e5b ldrh r3, [r3, #50] ; 0x32
801300e: 005b lsls r3, r3, #1
8013010: b29b uxth r3, r3
8013012: e001 b.n 8013018 <tcp_process+0x22c>
8013014: f241 131c movw r3, #4380 ; 0x111c
8013018: 687a ldr r2, [r7, #4]
801301a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
801301e: 687b ldr r3, [r7, #4]
8013020: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8013024: 2b00 cmp r3, #0
8013026: d106 bne.n 8013036 <tcp_process+0x24a>
8013028: 4b1b ldr r3, [pc, #108] ; (8013098 <tcp_process+0x2ac>)
801302a: f44f 725b mov.w r2, #876 ; 0x36c
801302e: 4924 ldr r1, [pc, #144] ; (80130c0 <tcp_process+0x2d4>)
8013030: 481b ldr r0, [pc, #108] ; (80130a0 <tcp_process+0x2b4>)
8013032: f007 fff7 bl 801b024 <iprintf>
--pcb->snd_queuelen;
8013036: 687b ldr r3, [r7, #4]
8013038: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
801303c: 3b01 subs r3, #1
801303e: b29a uxth r2, r3
8013040: 687b ldr r3, [r7, #4]
8013042: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
rseg = pcb->unacked;
8013046: 687b ldr r3, [r7, #4]
8013048: 6f1b ldr r3, [r3, #112] ; 0x70
801304a: 61fb str r3, [r7, #28]
if (rseg == NULL) {
801304c: 69fb ldr r3, [r7, #28]
801304e: 2b00 cmp r3, #0
8013050: d111 bne.n 8013076 <tcp_process+0x28a>
/* might happen if tcp_output fails in tcp_rexmit_rto()
in which case the segment is on the unsent list */
rseg = pcb->unsent;
8013052: 687b ldr r3, [r7, #4]
8013054: 6edb ldr r3, [r3, #108] ; 0x6c
8013056: 61fb str r3, [r7, #28]
LWIP_ASSERT("no segment to free", rseg != NULL);
8013058: 69fb ldr r3, [r7, #28]
801305a: 2b00 cmp r3, #0
801305c: d106 bne.n 801306c <tcp_process+0x280>
801305e: 4b0e ldr r3, [pc, #56] ; (8013098 <tcp_process+0x2ac>)
8013060: f44f 725d mov.w r2, #884 ; 0x374
8013064: 4917 ldr r1, [pc, #92] ; (80130c4 <tcp_process+0x2d8>)
8013066: 480e ldr r0, [pc, #56] ; (80130a0 <tcp_process+0x2b4>)
8013068: f007 ffdc bl 801b024 <iprintf>
pcb->unsent = rseg->next;
801306c: 69fb ldr r3, [r7, #28]
801306e: 681a ldr r2, [r3, #0]
8013070: 687b ldr r3, [r7, #4]
8013072: 66da str r2, [r3, #108] ; 0x6c
8013074: e003 b.n 801307e <tcp_process+0x292>
} else {
pcb->unacked = rseg->next;
8013076: 69fb ldr r3, [r7, #28]
8013078: 681a ldr r2, [r3, #0]
801307a: 687b ldr r3, [r7, #4]
801307c: 671a str r2, [r3, #112] ; 0x70
}
tcp_seg_free(rseg);
801307e: 69f8 ldr r0, [r7, #28]
8013080: f7fe fd3e bl 8011b00 <tcp_seg_free>
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013084: 687b ldr r3, [r7, #4]
8013086: 6f1b ldr r3, [r3, #112] ; 0x70
8013088: 2b00 cmp r3, #0
801308a: d11d bne.n 80130c8 <tcp_process+0x2dc>
pcb->rtime = -1;
801308c: 687b ldr r3, [r7, #4]
801308e: f64f 72ff movw r2, #65535 ; 0xffff
8013092: 861a strh r2, [r3, #48] ; 0x30
8013094: e01f b.n 80130d6 <tcp_process+0x2ea>
8013096: bf00 nop
8013098: 0801d2c0 .word 0x0801d2c0
801309c: 0801d4f8 .word 0x0801d4f8
80130a0: 0801d30c .word 0x0801d30c
80130a4: 20008758 .word 0x20008758
80130a8: 20008750 .word 0x20008750
80130ac: 2000874c .word 0x2000874c
80130b0: 0801d514 .word 0x0801d514
80130b4: 20008759 .word 0x20008759
80130b8: 2000f5c4 .word 0x2000f5c4
80130bc: 2000873c .word 0x2000873c
80130c0: 0801d534 .word 0x0801d534
80130c4: 0801d54c .word 0x0801d54c
} else {
pcb->rtime = 0;
80130c8: 687b ldr r3, [r7, #4]
80130ca: 2200 movs r2, #0
80130cc: 861a strh r2, [r3, #48] ; 0x30
pcb->nrtx = 0;
80130ce: 687b ldr r3, [r7, #4]
80130d0: 2200 movs r2, #0
80130d2: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Call the user specified function to call when successfully
* connected. */
TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
80130d6: 687b ldr r3, [r7, #4]
80130d8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130dc: 2b00 cmp r3, #0
80130de: d00a beq.n 80130f6 <tcp_process+0x30a>
80130e0: 687b ldr r3, [r7, #4]
80130e2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80130e6: 687a ldr r2, [r7, #4]
80130e8: 6910 ldr r0, [r2, #16]
80130ea: 2200 movs r2, #0
80130ec: 6879 ldr r1, [r7, #4]
80130ee: 4798 blx r3
80130f0: 4603 mov r3, r0
80130f2: 76bb strb r3, [r7, #26]
80130f4: e001 b.n 80130fa <tcp_process+0x30e>
80130f6: 2300 movs r3, #0
80130f8: 76bb strb r3, [r7, #26]
if (err == ERR_ABRT) {
80130fa: f997 301a ldrsb.w r3, [r7, #26]
80130fe: f113 0f0d cmn.w r3, #13
8013102: d102 bne.n 801310a <tcp_process+0x31e>
return ERR_ABRT;
8013104: f06f 030c mvn.w r3, #12
8013108: e250 b.n 80135ac <tcp_process+0x7c0>
}
tcp_ack_now(pcb);
801310a: 687b ldr r3, [r7, #4]
801310c: 8b5b ldrh r3, [r3, #26]
801310e: f043 0302 orr.w r3, r3, #2
8013112: b29a uxth r2, r3
8013114: 687b ldr r3, [r7, #4]
8013116: 835a strh r2, [r3, #26]
if (pcb->nrtx < TCP_SYNMAXRTX) {
pcb->rtime = 0;
tcp_rexmit_rto(pcb);
}
}
break;
8013118: e23a b.n 8013590 <tcp_process+0x7a4>
else if (flags & TCP_ACK) {
801311a: 4b9d ldr r3, [pc, #628] ; (8013390 <tcp_process+0x5a4>)
801311c: 781b ldrb r3, [r3, #0]
801311e: f003 0310 and.w r3, r3, #16
8013122: 2b00 cmp r3, #0
8013124: f000 8234 beq.w 8013590 <tcp_process+0x7a4>
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013128: 4b9a ldr r3, [pc, #616] ; (8013394 <tcp_process+0x5a8>)
801312a: 6819 ldr r1, [r3, #0]
801312c: 4b9a ldr r3, [pc, #616] ; (8013398 <tcp_process+0x5ac>)
801312e: 881b ldrh r3, [r3, #0]
8013130: 461a mov r2, r3
8013132: 4b9a ldr r3, [pc, #616] ; (801339c <tcp_process+0x5b0>)
8013134: 681b ldr r3, [r3, #0]
8013136: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013138: 4b99 ldr r3, [pc, #612] ; (80133a0 <tcp_process+0x5b4>)
801313a: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
801313c: 885b ldrh r3, [r3, #2]
801313e: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
8013140: 4a97 ldr r2, [pc, #604] ; (80133a0 <tcp_process+0x5b4>)
8013142: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013144: 8812 ldrh r2, [r2, #0]
8013146: b292 uxth r2, r2
8013148: 9202 str r2, [sp, #8]
801314a: 9301 str r3, [sp, #4]
801314c: 4b95 ldr r3, [pc, #596] ; (80133a4 <tcp_process+0x5b8>)
801314e: 9300 str r3, [sp, #0]
8013150: 4b95 ldr r3, [pc, #596] ; (80133a8 <tcp_process+0x5bc>)
8013152: 4602 mov r2, r0
8013154: 6878 ldr r0, [r7, #4]
8013156: f002 fc93 bl 8015a80 <tcp_rst>
if (pcb->nrtx < TCP_SYNMAXRTX) {
801315a: 687b ldr r3, [r7, #4]
801315c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8013160: 2b05 cmp r3, #5
8013162: f200 8215 bhi.w 8013590 <tcp_process+0x7a4>
pcb->rtime = 0;
8013166: 687b ldr r3, [r7, #4]
8013168: 2200 movs r2, #0
801316a: 861a strh r2, [r3, #48] ; 0x30
tcp_rexmit_rto(pcb);
801316c: 6878 ldr r0, [r7, #4]
801316e: f002 fa51 bl 8015614 <tcp_rexmit_rto>
break;
8013172: e20d b.n 8013590 <tcp_process+0x7a4>
case SYN_RCVD:
if (flags & TCP_ACK) {
8013174: 4b86 ldr r3, [pc, #536] ; (8013390 <tcp_process+0x5a4>)
8013176: 781b ldrb r3, [r3, #0]
8013178: f003 0310 and.w r3, r3, #16
801317c: 2b00 cmp r3, #0
801317e: f000 80a1 beq.w 80132c4 <tcp_process+0x4d8>
/* expected ACK number? */
if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013182: 4b84 ldr r3, [pc, #528] ; (8013394 <tcp_process+0x5a8>)
8013184: 681a ldr r2, [r3, #0]
8013186: 687b ldr r3, [r7, #4]
8013188: 6c5b ldr r3, [r3, #68] ; 0x44
801318a: 1ad3 subs r3, r2, r3
801318c: 3b01 subs r3, #1
801318e: 2b00 cmp r3, #0
8013190: db7e blt.n 8013290 <tcp_process+0x4a4>
8013192: 4b80 ldr r3, [pc, #512] ; (8013394 <tcp_process+0x5a8>)
8013194: 681a ldr r2, [r3, #0]
8013196: 687b ldr r3, [r7, #4]
8013198: 6d1b ldr r3, [r3, #80] ; 0x50
801319a: 1ad3 subs r3, r2, r3
801319c: 2b00 cmp r3, #0
801319e: dc77 bgt.n 8013290 <tcp_process+0x4a4>
pcb->state = ESTABLISHED;
80131a0: 687b ldr r3, [r7, #4]
80131a2: 2204 movs r2, #4
80131a4: 751a strb r2, [r3, #20]
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
if (pcb->listener == NULL) {
80131a6: 687b ldr r3, [r7, #4]
80131a8: 6fdb ldr r3, [r3, #124] ; 0x7c
80131aa: 2b00 cmp r3, #0
80131ac: d102 bne.n 80131b4 <tcp_process+0x3c8>
/* listen pcb might be closed by now */
err = ERR_VAL;
80131ae: 23fa movs r3, #250 ; 0xfa
80131b0: 76bb strb r3, [r7, #26]
80131b2: e01d b.n 80131f0 <tcp_process+0x404>
} else
#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
{
#if LWIP_CALLBACK_API
LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
80131b4: 687b ldr r3, [r7, #4]
80131b6: 6fdb ldr r3, [r3, #124] ; 0x7c
80131b8: 699b ldr r3, [r3, #24]
80131ba: 2b00 cmp r3, #0
80131bc: d106 bne.n 80131cc <tcp_process+0x3e0>
80131be: 4b7b ldr r3, [pc, #492] ; (80133ac <tcp_process+0x5c0>)
80131c0: f44f 726a mov.w r2, #936 ; 0x3a8
80131c4: 497a ldr r1, [pc, #488] ; (80133b0 <tcp_process+0x5c4>)
80131c6: 487b ldr r0, [pc, #492] ; (80133b4 <tcp_process+0x5c8>)
80131c8: f007 ff2c bl 801b024 <iprintf>
#endif
tcp_backlog_accepted(pcb);
/* Call the accept function. */
TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
80131cc: 687b ldr r3, [r7, #4]
80131ce: 6fdb ldr r3, [r3, #124] ; 0x7c
80131d0: 699b ldr r3, [r3, #24]
80131d2: 2b00 cmp r3, #0
80131d4: d00a beq.n 80131ec <tcp_process+0x400>
80131d6: 687b ldr r3, [r7, #4]
80131d8: 6fdb ldr r3, [r3, #124] ; 0x7c
80131da: 699b ldr r3, [r3, #24]
80131dc: 687a ldr r2, [r7, #4]
80131de: 6910 ldr r0, [r2, #16]
80131e0: 2200 movs r2, #0
80131e2: 6879 ldr r1, [r7, #4]
80131e4: 4798 blx r3
80131e6: 4603 mov r3, r0
80131e8: 76bb strb r3, [r7, #26]
80131ea: e001 b.n 80131f0 <tcp_process+0x404>
80131ec: 23f0 movs r3, #240 ; 0xf0
80131ee: 76bb strb r3, [r7, #26]
}
if (err != ERR_OK) {
80131f0: f997 301a ldrsb.w r3, [r7, #26]
80131f4: 2b00 cmp r3, #0
80131f6: d00a beq.n 801320e <tcp_process+0x422>
/* If the accept function returns with an error, we abort
* the connection. */
/* Already aborted? */
if (err != ERR_ABRT) {
80131f8: f997 301a ldrsb.w r3, [r7, #26]
80131fc: f113 0f0d cmn.w r3, #13
8013200: d002 beq.n 8013208 <tcp_process+0x41c>
tcp_abort(pcb);
8013202: 6878 ldr r0, [r7, #4]
8013204: f7fd ff94 bl 8011130 <tcp_abort>
}
return ERR_ABRT;
8013208: f06f 030c mvn.w r3, #12
801320c: e1ce b.n 80135ac <tcp_process+0x7c0>
}
/* If there was any data contained within this ACK,
* we'd better pass it on to the application as well. */
tcp_receive(pcb);
801320e: 6878 ldr r0, [r7, #4]
8013210: f000 fae0 bl 80137d4 <tcp_receive>
/* Prevent ACK for SYN to generate a sent event */
if (recv_acked != 0) {
8013214: 4b68 ldr r3, [pc, #416] ; (80133b8 <tcp_process+0x5cc>)
8013216: 881b ldrh r3, [r3, #0]
8013218: 2b00 cmp r3, #0
801321a: d005 beq.n 8013228 <tcp_process+0x43c>
recv_acked--;
801321c: 4b66 ldr r3, [pc, #408] ; (80133b8 <tcp_process+0x5cc>)
801321e: 881b ldrh r3, [r3, #0]
8013220: 3b01 subs r3, #1
8013222: b29a uxth r2, r3
8013224: 4b64 ldr r3, [pc, #400] ; (80133b8 <tcp_process+0x5cc>)
8013226: 801a strh r2, [r3, #0]
}
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
8013228: 687b ldr r3, [r7, #4]
801322a: 8e5b ldrh r3, [r3, #50] ; 0x32
801322c: 009a lsls r2, r3, #2
801322e: 687b ldr r3, [r7, #4]
8013230: 8e5b ldrh r3, [r3, #50] ; 0x32
8013232: 005b lsls r3, r3, #1
8013234: f241 111c movw r1, #4380 ; 0x111c
8013238: 428b cmp r3, r1
801323a: bf38 it cc
801323c: 460b movcc r3, r1
801323e: 429a cmp r2, r3
8013240: d204 bcs.n 801324c <tcp_process+0x460>
8013242: 687b ldr r3, [r7, #4]
8013244: 8e5b ldrh r3, [r3, #50] ; 0x32
8013246: 009b lsls r3, r3, #2
8013248: b29b uxth r3, r3
801324a: e00d b.n 8013268 <tcp_process+0x47c>
801324c: 687b ldr r3, [r7, #4]
801324e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013250: 005b lsls r3, r3, #1
8013252: f241 121c movw r2, #4380 ; 0x111c
8013256: 4293 cmp r3, r2
8013258: d904 bls.n 8013264 <tcp_process+0x478>
801325a: 687b ldr r3, [r7, #4]
801325c: 8e5b ldrh r3, [r3, #50] ; 0x32
801325e: 005b lsls r3, r3, #1
8013260: b29b uxth r3, r3
8013262: e001 b.n 8013268 <tcp_process+0x47c>
8013264: f241 131c movw r3, #4380 ; 0x111c
8013268: 687a ldr r2, [r7, #4]
801326a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
" ssthresh %"TCPWNDSIZE_F"\n",
pcb->cwnd, pcb->ssthresh));
if (recv_flags & TF_GOT_FIN) {
801326e: 4b53 ldr r3, [pc, #332] ; (80133bc <tcp_process+0x5d0>)
8013270: 781b ldrb r3, [r3, #0]
8013272: f003 0320 and.w r3, r3, #32
8013276: 2b00 cmp r3, #0
8013278: d037 beq.n 80132ea <tcp_process+0x4fe>
tcp_ack_now(pcb);
801327a: 687b ldr r3, [r7, #4]
801327c: 8b5b ldrh r3, [r3, #26]
801327e: f043 0302 orr.w r3, r3, #2
8013282: b29a uxth r2, r3
8013284: 687b ldr r3, [r7, #4]
8013286: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
8013288: 687b ldr r3, [r7, #4]
801328a: 2207 movs r2, #7
801328c: 751a strb r2, [r3, #20]
if (recv_flags & TF_GOT_FIN) {
801328e: e02c b.n 80132ea <tcp_process+0x4fe>
}
} else {
/* incorrect ACK number, send RST */
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
8013290: 4b40 ldr r3, [pc, #256] ; (8013394 <tcp_process+0x5a8>)
8013292: 6819 ldr r1, [r3, #0]
8013294: 4b40 ldr r3, [pc, #256] ; (8013398 <tcp_process+0x5ac>)
8013296: 881b ldrh r3, [r3, #0]
8013298: 461a mov r2, r3
801329a: 4b40 ldr r3, [pc, #256] ; (801339c <tcp_process+0x5b0>)
801329c: 681b ldr r3, [r3, #0]
801329e: 18d0 adds r0, r2, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80132a0: 4b3f ldr r3, [pc, #252] ; (80133a0 <tcp_process+0x5b4>)
80132a2: 681b ldr r3, [r3, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
80132a4: 885b ldrh r3, [r3, #2]
80132a6: b29b uxth r3, r3
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
80132a8: 4a3d ldr r2, [pc, #244] ; (80133a0 <tcp_process+0x5b4>)
80132aa: 6812 ldr r2, [r2, #0]
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
80132ac: 8812 ldrh r2, [r2, #0]
80132ae: b292 uxth r2, r2
80132b0: 9202 str r2, [sp, #8]
80132b2: 9301 str r3, [sp, #4]
80132b4: 4b3b ldr r3, [pc, #236] ; (80133a4 <tcp_process+0x5b8>)
80132b6: 9300 str r3, [sp, #0]
80132b8: 4b3b ldr r3, [pc, #236] ; (80133a8 <tcp_process+0x5bc>)
80132ba: 4602 mov r2, r0
80132bc: 6878 ldr r0, [r7, #4]
80132be: f002 fbdf bl 8015a80 <tcp_rst>
}
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
/* Looks like another copy of the SYN - retransmit our SYN-ACK */
tcp_rexmit(pcb);
}
break;
80132c2: e167 b.n 8013594 <tcp_process+0x7a8>
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
80132c4: 4b32 ldr r3, [pc, #200] ; (8013390 <tcp_process+0x5a4>)
80132c6: 781b ldrb r3, [r3, #0]
80132c8: f003 0302 and.w r3, r3, #2
80132cc: 2b00 cmp r3, #0
80132ce: f000 8161 beq.w 8013594 <tcp_process+0x7a8>
80132d2: 687b ldr r3, [r7, #4]
80132d4: 6a5b ldr r3, [r3, #36] ; 0x24
80132d6: 1e5a subs r2, r3, #1
80132d8: 4b30 ldr r3, [pc, #192] ; (801339c <tcp_process+0x5b0>)
80132da: 681b ldr r3, [r3, #0]
80132dc: 429a cmp r2, r3
80132de: f040 8159 bne.w 8013594 <tcp_process+0x7a8>
tcp_rexmit(pcb);
80132e2: 6878 ldr r0, [r7, #4]
80132e4: f002 f9b8 bl 8015658 <tcp_rexmit>
break;
80132e8: e154 b.n 8013594 <tcp_process+0x7a8>
80132ea: e153 b.n 8013594 <tcp_process+0x7a8>
case CLOSE_WAIT:
/* FALLTHROUGH */
case ESTABLISHED:
tcp_receive(pcb);
80132ec: 6878 ldr r0, [r7, #4]
80132ee: f000 fa71 bl 80137d4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) { /* passive close */
80132f2: 4b32 ldr r3, [pc, #200] ; (80133bc <tcp_process+0x5d0>)
80132f4: 781b ldrb r3, [r3, #0]
80132f6: f003 0320 and.w r3, r3, #32
80132fa: 2b00 cmp r3, #0
80132fc: f000 814c beq.w 8013598 <tcp_process+0x7ac>
tcp_ack_now(pcb);
8013300: 687b ldr r3, [r7, #4]
8013302: 8b5b ldrh r3, [r3, #26]
8013304: f043 0302 orr.w r3, r3, #2
8013308: b29a uxth r2, r3
801330a: 687b ldr r3, [r7, #4]
801330c: 835a strh r2, [r3, #26]
pcb->state = CLOSE_WAIT;
801330e: 687b ldr r3, [r7, #4]
8013310: 2207 movs r2, #7
8013312: 751a strb r2, [r3, #20]
}
break;
8013314: e140 b.n 8013598 <tcp_process+0x7ac>
case FIN_WAIT_1:
tcp_receive(pcb);
8013316: 6878 ldr r0, [r7, #4]
8013318: f000 fa5c bl 80137d4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
801331c: 4b27 ldr r3, [pc, #156] ; (80133bc <tcp_process+0x5d0>)
801331e: 781b ldrb r3, [r3, #0]
8013320: f003 0320 and.w r3, r3, #32
8013324: 2b00 cmp r3, #0
8013326: d071 beq.n 801340c <tcp_process+0x620>
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
8013328: 4b19 ldr r3, [pc, #100] ; (8013390 <tcp_process+0x5a4>)
801332a: 781b ldrb r3, [r3, #0]
801332c: f003 0310 and.w r3, r3, #16
8013330: 2b00 cmp r3, #0
8013332: d060 beq.n 80133f6 <tcp_process+0x60a>
8013334: 687b ldr r3, [r7, #4]
8013336: 6d1a ldr r2, [r3, #80] ; 0x50
8013338: 4b16 ldr r3, [pc, #88] ; (8013394 <tcp_process+0x5a8>)
801333a: 681b ldr r3, [r3, #0]
801333c: 429a cmp r2, r3
801333e: d15a bne.n 80133f6 <tcp_process+0x60a>
pcb->unsent == NULL) {
8013340: 687b ldr r3, [r7, #4]
8013342: 6edb ldr r3, [r3, #108] ; 0x6c
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
8013344: 2b00 cmp r3, #0
8013346: d156 bne.n 80133f6 <tcp_process+0x60a>
LWIP_DEBUGF(TCP_DEBUG,
("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
8013348: 687b ldr r3, [r7, #4]
801334a: 8b5b ldrh r3, [r3, #26]
801334c: f043 0302 orr.w r3, r3, #2
8013350: b29a uxth r2, r3
8013352: 687b ldr r3, [r7, #4]
8013354: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
8013356: 6878 ldr r0, [r7, #4]
8013358: f7fe fdbe bl 8011ed8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
801335c: 4b18 ldr r3, [pc, #96] ; (80133c0 <tcp_process+0x5d4>)
801335e: 681b ldr r3, [r3, #0]
8013360: 687a ldr r2, [r7, #4]
8013362: 429a cmp r2, r3
8013364: d105 bne.n 8013372 <tcp_process+0x586>
8013366: 4b16 ldr r3, [pc, #88] ; (80133c0 <tcp_process+0x5d4>)
8013368: 681b ldr r3, [r3, #0]
801336a: 68db ldr r3, [r3, #12]
801336c: 4a14 ldr r2, [pc, #80] ; (80133c0 <tcp_process+0x5d4>)
801336e: 6013 str r3, [r2, #0]
8013370: e02e b.n 80133d0 <tcp_process+0x5e4>
8013372: 4b13 ldr r3, [pc, #76] ; (80133c0 <tcp_process+0x5d4>)
8013374: 681b ldr r3, [r3, #0]
8013376: 617b str r3, [r7, #20]
8013378: e027 b.n 80133ca <tcp_process+0x5de>
801337a: 697b ldr r3, [r7, #20]
801337c: 68db ldr r3, [r3, #12]
801337e: 687a ldr r2, [r7, #4]
8013380: 429a cmp r2, r3
8013382: d11f bne.n 80133c4 <tcp_process+0x5d8>
8013384: 687b ldr r3, [r7, #4]
8013386: 68da ldr r2, [r3, #12]
8013388: 697b ldr r3, [r7, #20]
801338a: 60da str r2, [r3, #12]
801338c: e020 b.n 80133d0 <tcp_process+0x5e4>
801338e: bf00 nop
8013390: 20008758 .word 0x20008758
8013394: 20008750 .word 0x20008750
8013398: 20008756 .word 0x20008756
801339c: 2000874c .word 0x2000874c
80133a0: 2000873c .word 0x2000873c
80133a4: 2000be9c .word 0x2000be9c
80133a8: 2000bea0 .word 0x2000bea0
80133ac: 0801d2c0 .word 0x0801d2c0
80133b0: 0801d560 .word 0x0801d560
80133b4: 0801d30c .word 0x0801d30c
80133b8: 20008754 .word 0x20008754
80133bc: 20008759 .word 0x20008759
80133c0: 2000f5c0 .word 0x2000f5c0
80133c4: 697b ldr r3, [r7, #20]
80133c6: 68db ldr r3, [r3, #12]
80133c8: 617b str r3, [r7, #20]
80133ca: 697b ldr r3, [r7, #20]
80133cc: 2b00 cmp r3, #0
80133ce: d1d4 bne.n 801337a <tcp_process+0x58e>
80133d0: 687b ldr r3, [r7, #4]
80133d2: 2200 movs r2, #0
80133d4: 60da str r2, [r3, #12]
80133d6: 4b77 ldr r3, [pc, #476] ; (80135b4 <tcp_process+0x7c8>)
80133d8: 2201 movs r2, #1
80133da: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
80133dc: 687b ldr r3, [r7, #4]
80133de: 220a movs r2, #10
80133e0: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
80133e2: 4b75 ldr r3, [pc, #468] ; (80135b8 <tcp_process+0x7cc>)
80133e4: 681a ldr r2, [r3, #0]
80133e6: 687b ldr r3, [r7, #4]
80133e8: 60da str r2, [r3, #12]
80133ea: 4a73 ldr r2, [pc, #460] ; (80135b8 <tcp_process+0x7cc>)
80133ec: 687b ldr r3, [r7, #4]
80133ee: 6013 str r3, [r2, #0]
80133f0: f002 fd08 bl 8015e04 <tcp_timer_needed>
}
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
pcb->unsent == NULL) {
pcb->state = FIN_WAIT_2;
}
break;
80133f4: e0d2 b.n 801359c <tcp_process+0x7b0>
tcp_ack_now(pcb);
80133f6: 687b ldr r3, [r7, #4]
80133f8: 8b5b ldrh r3, [r3, #26]
80133fa: f043 0302 orr.w r3, r3, #2
80133fe: b29a uxth r2, r3
8013400: 687b ldr r3, [r7, #4]
8013402: 835a strh r2, [r3, #26]
pcb->state = CLOSING;
8013404: 687b ldr r3, [r7, #4]
8013406: 2208 movs r2, #8
8013408: 751a strb r2, [r3, #20]
break;
801340a: e0c7 b.n 801359c <tcp_process+0x7b0>
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
801340c: 4b6b ldr r3, [pc, #428] ; (80135bc <tcp_process+0x7d0>)
801340e: 781b ldrb r3, [r3, #0]
8013410: f003 0310 and.w r3, r3, #16
8013414: 2b00 cmp r3, #0
8013416: f000 80c1 beq.w 801359c <tcp_process+0x7b0>
801341a: 687b ldr r3, [r7, #4]
801341c: 6d1a ldr r2, [r3, #80] ; 0x50
801341e: 4b68 ldr r3, [pc, #416] ; (80135c0 <tcp_process+0x7d4>)
8013420: 681b ldr r3, [r3, #0]
8013422: 429a cmp r2, r3
8013424: f040 80ba bne.w 801359c <tcp_process+0x7b0>
pcb->unsent == NULL) {
8013428: 687b ldr r3, [r7, #4]
801342a: 6edb ldr r3, [r3, #108] ; 0x6c
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
801342c: 2b00 cmp r3, #0
801342e: f040 80b5 bne.w 801359c <tcp_process+0x7b0>
pcb->state = FIN_WAIT_2;
8013432: 687b ldr r3, [r7, #4]
8013434: 2206 movs r2, #6
8013436: 751a strb r2, [r3, #20]
break;
8013438: e0b0 b.n 801359c <tcp_process+0x7b0>
case FIN_WAIT_2:
tcp_receive(pcb);
801343a: 6878 ldr r0, [r7, #4]
801343c: f000 f9ca bl 80137d4 <tcp_receive>
if (recv_flags & TF_GOT_FIN) {
8013440: 4b60 ldr r3, [pc, #384] ; (80135c4 <tcp_process+0x7d8>)
8013442: 781b ldrb r3, [r3, #0]
8013444: f003 0320 and.w r3, r3, #32
8013448: 2b00 cmp r3, #0
801344a: f000 80a9 beq.w 80135a0 <tcp_process+0x7b4>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_ack_now(pcb);
801344e: 687b ldr r3, [r7, #4]
8013450: 8b5b ldrh r3, [r3, #26]
8013452: f043 0302 orr.w r3, r3, #2
8013456: b29a uxth r2, r3
8013458: 687b ldr r3, [r7, #4]
801345a: 835a strh r2, [r3, #26]
tcp_pcb_purge(pcb);
801345c: 6878 ldr r0, [r7, #4]
801345e: f7fe fd3b bl 8011ed8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
8013462: 4b59 ldr r3, [pc, #356] ; (80135c8 <tcp_process+0x7dc>)
8013464: 681b ldr r3, [r3, #0]
8013466: 687a ldr r2, [r7, #4]
8013468: 429a cmp r2, r3
801346a: d105 bne.n 8013478 <tcp_process+0x68c>
801346c: 4b56 ldr r3, [pc, #344] ; (80135c8 <tcp_process+0x7dc>)
801346e: 681b ldr r3, [r3, #0]
8013470: 68db ldr r3, [r3, #12]
8013472: 4a55 ldr r2, [pc, #340] ; (80135c8 <tcp_process+0x7dc>)
8013474: 6013 str r3, [r2, #0]
8013476: e013 b.n 80134a0 <tcp_process+0x6b4>
8013478: 4b53 ldr r3, [pc, #332] ; (80135c8 <tcp_process+0x7dc>)
801347a: 681b ldr r3, [r3, #0]
801347c: 613b str r3, [r7, #16]
801347e: e00c b.n 801349a <tcp_process+0x6ae>
8013480: 693b ldr r3, [r7, #16]
8013482: 68db ldr r3, [r3, #12]
8013484: 687a ldr r2, [r7, #4]
8013486: 429a cmp r2, r3
8013488: d104 bne.n 8013494 <tcp_process+0x6a8>
801348a: 687b ldr r3, [r7, #4]
801348c: 68da ldr r2, [r3, #12]
801348e: 693b ldr r3, [r7, #16]
8013490: 60da str r2, [r3, #12]
8013492: e005 b.n 80134a0 <tcp_process+0x6b4>
8013494: 693b ldr r3, [r7, #16]
8013496: 68db ldr r3, [r3, #12]
8013498: 613b str r3, [r7, #16]
801349a: 693b ldr r3, [r7, #16]
801349c: 2b00 cmp r3, #0
801349e: d1ef bne.n 8013480 <tcp_process+0x694>
80134a0: 687b ldr r3, [r7, #4]
80134a2: 2200 movs r2, #0
80134a4: 60da str r2, [r3, #12]
80134a6: 4b43 ldr r3, [pc, #268] ; (80135b4 <tcp_process+0x7c8>)
80134a8: 2201 movs r2, #1
80134aa: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
80134ac: 687b ldr r3, [r7, #4]
80134ae: 220a movs r2, #10
80134b0: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
80134b2: 4b41 ldr r3, [pc, #260] ; (80135b8 <tcp_process+0x7cc>)
80134b4: 681a ldr r2, [r3, #0]
80134b6: 687b ldr r3, [r7, #4]
80134b8: 60da str r2, [r3, #12]
80134ba: 4a3f ldr r2, [pc, #252] ; (80135b8 <tcp_process+0x7cc>)
80134bc: 687b ldr r3, [r7, #4]
80134be: 6013 str r3, [r2, #0]
80134c0: f002 fca0 bl 8015e04 <tcp_timer_needed>
}
break;
80134c4: e06c b.n 80135a0 <tcp_process+0x7b4>
case CLOSING:
tcp_receive(pcb);
80134c6: 6878 ldr r0, [r7, #4]
80134c8: f000 f984 bl 80137d4 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
80134cc: 4b3b ldr r3, [pc, #236] ; (80135bc <tcp_process+0x7d0>)
80134ce: 781b ldrb r3, [r3, #0]
80134d0: f003 0310 and.w r3, r3, #16
80134d4: 2b00 cmp r3, #0
80134d6: d065 beq.n 80135a4 <tcp_process+0x7b8>
80134d8: 687b ldr r3, [r7, #4]
80134da: 6d1a ldr r2, [r3, #80] ; 0x50
80134dc: 4b38 ldr r3, [pc, #224] ; (80135c0 <tcp_process+0x7d4>)
80134de: 681b ldr r3, [r3, #0]
80134e0: 429a cmp r2, r3
80134e2: d15f bne.n 80135a4 <tcp_process+0x7b8>
80134e4: 687b ldr r3, [r7, #4]
80134e6: 6edb ldr r3, [r3, #108] ; 0x6c
80134e8: 2b00 cmp r3, #0
80134ea: d15b bne.n 80135a4 <tcp_process+0x7b8>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
tcp_pcb_purge(pcb);
80134ec: 6878 ldr r0, [r7, #4]
80134ee: f7fe fcf3 bl 8011ed8 <tcp_pcb_purge>
TCP_RMV_ACTIVE(pcb);
80134f2: 4b35 ldr r3, [pc, #212] ; (80135c8 <tcp_process+0x7dc>)
80134f4: 681b ldr r3, [r3, #0]
80134f6: 687a ldr r2, [r7, #4]
80134f8: 429a cmp r2, r3
80134fa: d105 bne.n 8013508 <tcp_process+0x71c>
80134fc: 4b32 ldr r3, [pc, #200] ; (80135c8 <tcp_process+0x7dc>)
80134fe: 681b ldr r3, [r3, #0]
8013500: 68db ldr r3, [r3, #12]
8013502: 4a31 ldr r2, [pc, #196] ; (80135c8 <tcp_process+0x7dc>)
8013504: 6013 str r3, [r2, #0]
8013506: e013 b.n 8013530 <tcp_process+0x744>
8013508: 4b2f ldr r3, [pc, #188] ; (80135c8 <tcp_process+0x7dc>)
801350a: 681b ldr r3, [r3, #0]
801350c: 60fb str r3, [r7, #12]
801350e: e00c b.n 801352a <tcp_process+0x73e>
8013510: 68fb ldr r3, [r7, #12]
8013512: 68db ldr r3, [r3, #12]
8013514: 687a ldr r2, [r7, #4]
8013516: 429a cmp r2, r3
8013518: d104 bne.n 8013524 <tcp_process+0x738>
801351a: 687b ldr r3, [r7, #4]
801351c: 68da ldr r2, [r3, #12]
801351e: 68fb ldr r3, [r7, #12]
8013520: 60da str r2, [r3, #12]
8013522: e005 b.n 8013530 <tcp_process+0x744>
8013524: 68fb ldr r3, [r7, #12]
8013526: 68db ldr r3, [r3, #12]
8013528: 60fb str r3, [r7, #12]
801352a: 68fb ldr r3, [r7, #12]
801352c: 2b00 cmp r3, #0
801352e: d1ef bne.n 8013510 <tcp_process+0x724>
8013530: 687b ldr r3, [r7, #4]
8013532: 2200 movs r2, #0
8013534: 60da str r2, [r3, #12]
8013536: 4b1f ldr r3, [pc, #124] ; (80135b4 <tcp_process+0x7c8>)
8013538: 2201 movs r2, #1
801353a: 701a strb r2, [r3, #0]
pcb->state = TIME_WAIT;
801353c: 687b ldr r3, [r7, #4]
801353e: 220a movs r2, #10
8013540: 751a strb r2, [r3, #20]
TCP_REG(&tcp_tw_pcbs, pcb);
8013542: 4b1d ldr r3, [pc, #116] ; (80135b8 <tcp_process+0x7cc>)
8013544: 681a ldr r2, [r3, #0]
8013546: 687b ldr r3, [r7, #4]
8013548: 60da str r2, [r3, #12]
801354a: 4a1b ldr r2, [pc, #108] ; (80135b8 <tcp_process+0x7cc>)
801354c: 687b ldr r3, [r7, #4]
801354e: 6013 str r3, [r2, #0]
8013550: f002 fc58 bl 8015e04 <tcp_timer_needed>
}
break;
8013554: e026 b.n 80135a4 <tcp_process+0x7b8>
case LAST_ACK:
tcp_receive(pcb);
8013556: 6878 ldr r0, [r7, #4]
8013558: f000 f93c bl 80137d4 <tcp_receive>
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
801355c: 4b17 ldr r3, [pc, #92] ; (80135bc <tcp_process+0x7d0>)
801355e: 781b ldrb r3, [r3, #0]
8013560: f003 0310 and.w r3, r3, #16
8013564: 2b00 cmp r3, #0
8013566: d01f beq.n 80135a8 <tcp_process+0x7bc>
8013568: 687b ldr r3, [r7, #4]
801356a: 6d1a ldr r2, [r3, #80] ; 0x50
801356c: 4b14 ldr r3, [pc, #80] ; (80135c0 <tcp_process+0x7d4>)
801356e: 681b ldr r3, [r3, #0]
8013570: 429a cmp r2, r3
8013572: d119 bne.n 80135a8 <tcp_process+0x7bc>
8013574: 687b ldr r3, [r7, #4]
8013576: 6edb ldr r3, [r3, #108] ; 0x6c
8013578: 2b00 cmp r3, #0
801357a: d115 bne.n 80135a8 <tcp_process+0x7bc>
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
/* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
recv_flags |= TF_CLOSED;
801357c: 4b11 ldr r3, [pc, #68] ; (80135c4 <tcp_process+0x7d8>)
801357e: 781b ldrb r3, [r3, #0]
8013580: f043 0310 orr.w r3, r3, #16
8013584: b2da uxtb r2, r3
8013586: 4b0f ldr r3, [pc, #60] ; (80135c4 <tcp_process+0x7d8>)
8013588: 701a strb r2, [r3, #0]
}
break;
801358a: e00d b.n 80135a8 <tcp_process+0x7bc>
default:
break;
801358c: bf00 nop
801358e: e00c b.n 80135aa <tcp_process+0x7be>
break;
8013590: bf00 nop
8013592: e00a b.n 80135aa <tcp_process+0x7be>
break;
8013594: bf00 nop
8013596: e008 b.n 80135aa <tcp_process+0x7be>
break;
8013598: bf00 nop
801359a: e006 b.n 80135aa <tcp_process+0x7be>
break;
801359c: bf00 nop
801359e: e004 b.n 80135aa <tcp_process+0x7be>
break;
80135a0: bf00 nop
80135a2: e002 b.n 80135aa <tcp_process+0x7be>
break;
80135a4: bf00 nop
80135a6: e000 b.n 80135aa <tcp_process+0x7be>
break;
80135a8: bf00 nop
}
return ERR_OK;
80135aa: 2300 movs r3, #0
}
80135ac: 4618 mov r0, r3
80135ae: 3724 adds r7, #36 ; 0x24
80135b0: 46bd mov sp, r7
80135b2: bd90 pop {r4, r7, pc}
80135b4: 2000f5bc .word 0x2000f5bc
80135b8: 2000f5d0 .word 0x2000f5d0
80135bc: 20008758 .word 0x20008758
80135c0: 20008750 .word 0x20008750
80135c4: 20008759 .word 0x20008759
80135c8: 2000f5c0 .word 0x2000f5c0
080135cc <tcp_oos_insert_segment>:
*
* Called from tcp_receive()
*/
static void
tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
{
80135cc: b590 push {r4, r7, lr}
80135ce: b085 sub sp, #20
80135d0: af00 add r7, sp, #0
80135d2: 6078 str r0, [r7, #4]
80135d4: 6039 str r1, [r7, #0]
struct tcp_seg *old_seg;
LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
80135d6: 687b ldr r3, [r7, #4]
80135d8: 2b00 cmp r3, #0
80135da: d106 bne.n 80135ea <tcp_oos_insert_segment+0x1e>
80135dc: 4b3b ldr r3, [pc, #236] ; (80136cc <tcp_oos_insert_segment+0x100>)
80135de: f240 421f movw r2, #1055 ; 0x41f
80135e2: 493b ldr r1, [pc, #236] ; (80136d0 <tcp_oos_insert_segment+0x104>)
80135e4: 483b ldr r0, [pc, #236] ; (80136d4 <tcp_oos_insert_segment+0x108>)
80135e6: f007 fd1d bl 801b024 <iprintf>
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
80135ea: 687b ldr r3, [r7, #4]
80135ec: 68db ldr r3, [r3, #12]
80135ee: 899b ldrh r3, [r3, #12]
80135f0: b29b uxth r3, r3
80135f2: 4618 mov r0, r3
80135f4: f7fb fc4c bl 800ee90 <lwip_htons>
80135f8: 4603 mov r3, r0
80135fa: b2db uxtb r3, r3
80135fc: f003 0301 and.w r3, r3, #1
8013600: 2b00 cmp r3, #0
8013602: d028 beq.n 8013656 <tcp_oos_insert_segment+0x8a>
/* received segment overlaps all following segments */
tcp_segs_free(next);
8013604: 6838 ldr r0, [r7, #0]
8013606: f7fe fa67 bl 8011ad8 <tcp_segs_free>
next = NULL;
801360a: 2300 movs r3, #0
801360c: 603b str r3, [r7, #0]
801360e: e056 b.n 80136be <tcp_oos_insert_segment+0xf2>
oos queue may have segments with FIN flag */
while (next &&
TCP_SEQ_GEQ((seqno + cseg->len),
(next->tcphdr->seqno + next->len))) {
/* cseg with FIN already processed */
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
8013610: 683b ldr r3, [r7, #0]
8013612: 68db ldr r3, [r3, #12]
8013614: 899b ldrh r3, [r3, #12]
8013616: b29b uxth r3, r3
8013618: 4618 mov r0, r3
801361a: f7fb fc39 bl 800ee90 <lwip_htons>
801361e: 4603 mov r3, r0
8013620: b2db uxtb r3, r3
8013622: f003 0301 and.w r3, r3, #1
8013626: 2b00 cmp r3, #0
8013628: d00d beq.n 8013646 <tcp_oos_insert_segment+0x7a>
TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
801362a: 687b ldr r3, [r7, #4]
801362c: 68db ldr r3, [r3, #12]
801362e: 899b ldrh r3, [r3, #12]
8013630: b29c uxth r4, r3
8013632: 2001 movs r0, #1
8013634: f7fb fc2c bl 800ee90 <lwip_htons>
8013638: 4603 mov r3, r0
801363a: 461a mov r2, r3
801363c: 687b ldr r3, [r7, #4]
801363e: 68db ldr r3, [r3, #12]
8013640: 4322 orrs r2, r4
8013642: b292 uxth r2, r2
8013644: 819a strh r2, [r3, #12]
}
old_seg = next;
8013646: 683b ldr r3, [r7, #0]
8013648: 60fb str r3, [r7, #12]
next = next->next;
801364a: 683b ldr r3, [r7, #0]
801364c: 681b ldr r3, [r3, #0]
801364e: 603b str r3, [r7, #0]
tcp_seg_free(old_seg);
8013650: 68f8 ldr r0, [r7, #12]
8013652: f7fe fa55 bl 8011b00 <tcp_seg_free>
while (next &&
8013656: 683b ldr r3, [r7, #0]
8013658: 2b00 cmp r3, #0
801365a: d00e beq.n 801367a <tcp_oos_insert_segment+0xae>
TCP_SEQ_GEQ((seqno + cseg->len),
801365c: 687b ldr r3, [r7, #4]
801365e: 891b ldrh r3, [r3, #8]
8013660: 461a mov r2, r3
8013662: 4b1d ldr r3, [pc, #116] ; (80136d8 <tcp_oos_insert_segment+0x10c>)
8013664: 681b ldr r3, [r3, #0]
8013666: 441a add r2, r3
8013668: 683b ldr r3, [r7, #0]
801366a: 68db ldr r3, [r3, #12]
801366c: 685b ldr r3, [r3, #4]
801366e: 6839 ldr r1, [r7, #0]
8013670: 8909 ldrh r1, [r1, #8]
8013672: 440b add r3, r1
8013674: 1ad3 subs r3, r2, r3
while (next &&
8013676: 2b00 cmp r3, #0
8013678: daca bge.n 8013610 <tcp_oos_insert_segment+0x44>
}
if (next &&
801367a: 683b ldr r3, [r7, #0]
801367c: 2b00 cmp r3, #0
801367e: d01e beq.n 80136be <tcp_oos_insert_segment+0xf2>
TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
8013680: 687b ldr r3, [r7, #4]
8013682: 891b ldrh r3, [r3, #8]
8013684: 461a mov r2, r3
8013686: 4b14 ldr r3, [pc, #80] ; (80136d8 <tcp_oos_insert_segment+0x10c>)
8013688: 681b ldr r3, [r3, #0]
801368a: 441a add r2, r3
801368c: 683b ldr r3, [r7, #0]
801368e: 68db ldr r3, [r3, #12]
8013690: 685b ldr r3, [r3, #4]
8013692: 1ad3 subs r3, r2, r3
if (next &&
8013694: 2b00 cmp r3, #0
8013696: dd12 ble.n 80136be <tcp_oos_insert_segment+0xf2>
/* We need to trim the incoming segment. */
cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
8013698: 683b ldr r3, [r7, #0]
801369a: 68db ldr r3, [r3, #12]
801369c: 685b ldr r3, [r3, #4]
801369e: b29a uxth r2, r3
80136a0: 4b0d ldr r3, [pc, #52] ; (80136d8 <tcp_oos_insert_segment+0x10c>)
80136a2: 681b ldr r3, [r3, #0]
80136a4: b29b uxth r3, r3
80136a6: 1ad3 subs r3, r2, r3
80136a8: b29a uxth r2, r3
80136aa: 687b ldr r3, [r7, #4]
80136ac: 811a strh r2, [r3, #8]
pbuf_realloc(cseg->p, cseg->len);
80136ae: 687b ldr r3, [r7, #4]
80136b0: 685a ldr r2, [r3, #4]
80136b2: 687b ldr r3, [r7, #4]
80136b4: 891b ldrh r3, [r3, #8]
80136b6: 4619 mov r1, r3
80136b8: 4610 mov r0, r2
80136ba: f7fc fe17 bl 80102ec <pbuf_realloc>
}
}
cseg->next = next;
80136be: 687b ldr r3, [r7, #4]
80136c0: 683a ldr r2, [r7, #0]
80136c2: 601a str r2, [r3, #0]
}
80136c4: bf00 nop
80136c6: 3714 adds r7, #20
80136c8: 46bd mov sp, r7
80136ca: bd90 pop {r4, r7, pc}
80136cc: 0801d2c0 .word 0x0801d2c0
80136d0: 0801d580 .word 0x0801d580
80136d4: 0801d30c .word 0x0801d30c
80136d8: 2000874c .word 0x2000874c
080136dc <tcp_free_acked_segments>:
/** Remove segments from a list if the incoming ACK acknowledges them */
static struct tcp_seg *
tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
struct tcp_seg *dbg_other_seg_list)
{
80136dc: b5b0 push {r4, r5, r7, lr}
80136de: b086 sub sp, #24
80136e0: af00 add r7, sp, #0
80136e2: 60f8 str r0, [r7, #12]
80136e4: 60b9 str r1, [r7, #8]
80136e6: 607a str r2, [r7, #4]
80136e8: 603b str r3, [r7, #0]
u16_t clen;
LWIP_UNUSED_ARG(dbg_list_name);
LWIP_UNUSED_ARG(dbg_other_seg_list);
while (seg_list != NULL &&
80136ea: e03e b.n 801376a <tcp_free_acked_segments+0x8e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
lwip_ntohl(seg_list->tcphdr->seqno),
lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
dbg_list_name));
next = seg_list;
80136ec: 68bb ldr r3, [r7, #8]
80136ee: 617b str r3, [r7, #20]
seg_list = seg_list->next;
80136f0: 68bb ldr r3, [r7, #8]
80136f2: 681b ldr r3, [r3, #0]
80136f4: 60bb str r3, [r7, #8]
clen = pbuf_clen(next->p);
80136f6: 697b ldr r3, [r7, #20]
80136f8: 685b ldr r3, [r3, #4]
80136fa: 4618 mov r0, r3
80136fc: f7fd f80a bl 8010714 <pbuf_clen>
8013700: 4603 mov r3, r0
8013702: 827b strh r3, [r7, #18]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
(tcpwnd_size_t)pcb->snd_queuelen));
LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
8013704: 68fb ldr r3, [r7, #12]
8013706: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
801370a: 8a7a ldrh r2, [r7, #18]
801370c: 429a cmp r2, r3
801370e: d906 bls.n 801371e <tcp_free_acked_segments+0x42>
8013710: 4b2a ldr r3, [pc, #168] ; (80137bc <tcp_free_acked_segments+0xe0>)
8013712: f240 4257 movw r2, #1111 ; 0x457
8013716: 492a ldr r1, [pc, #168] ; (80137c0 <tcp_free_acked_segments+0xe4>)
8013718: 482a ldr r0, [pc, #168] ; (80137c4 <tcp_free_acked_segments+0xe8>)
801371a: f007 fc83 bl 801b024 <iprintf>
pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
801371e: 68fb ldr r3, [r7, #12]
8013720: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66
8013724: 8a7b ldrh r3, [r7, #18]
8013726: 1ad3 subs r3, r2, r3
8013728: b29a uxth r2, r3
801372a: 68fb ldr r3, [r7, #12]
801372c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
8013730: 697b ldr r3, [r7, #20]
8013732: 891a ldrh r2, [r3, #8]
8013734: 4b24 ldr r3, [pc, #144] ; (80137c8 <tcp_free_acked_segments+0xec>)
8013736: 881b ldrh r3, [r3, #0]
8013738: 4413 add r3, r2
801373a: b29a uxth r2, r3
801373c: 4b22 ldr r3, [pc, #136] ; (80137c8 <tcp_free_acked_segments+0xec>)
801373e: 801a strh r2, [r3, #0]
tcp_seg_free(next);
8013740: 6978 ldr r0, [r7, #20]
8013742: f7fe f9dd bl 8011b00 <tcp_seg_free>
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
(tcpwnd_size_t)pcb->snd_queuelen,
dbg_list_name));
if (pcb->snd_queuelen != 0) {
8013746: 68fb ldr r3, [r7, #12]
8013748: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
801374c: 2b00 cmp r3, #0
801374e: d00c beq.n 801376a <tcp_free_acked_segments+0x8e>
LWIP_ASSERT("tcp_receive: valid queue length",
8013750: 68bb ldr r3, [r7, #8]
8013752: 2b00 cmp r3, #0
8013754: d109 bne.n 801376a <tcp_free_acked_segments+0x8e>
8013756: 683b ldr r3, [r7, #0]
8013758: 2b00 cmp r3, #0
801375a: d106 bne.n 801376a <tcp_free_acked_segments+0x8e>
801375c: 4b17 ldr r3, [pc, #92] ; (80137bc <tcp_free_acked_segments+0xe0>)
801375e: f240 4262 movw r2, #1122 ; 0x462
8013762: 491a ldr r1, [pc, #104] ; (80137cc <tcp_free_acked_segments+0xf0>)
8013764: 4817 ldr r0, [pc, #92] ; (80137c4 <tcp_free_acked_segments+0xe8>)
8013766: f007 fc5d bl 801b024 <iprintf>
while (seg_list != NULL &&
801376a: 68bb ldr r3, [r7, #8]
801376c: 2b00 cmp r3, #0
801376e: d020 beq.n 80137b2 <tcp_free_acked_segments+0xd6>
TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
8013770: 68bb ldr r3, [r7, #8]
8013772: 68db ldr r3, [r3, #12]
8013774: 685b ldr r3, [r3, #4]
8013776: 4618 mov r0, r3
8013778: f7fb fb9f bl 800eeba <lwip_htonl>
801377c: 4604 mov r4, r0
801377e: 68bb ldr r3, [r7, #8]
8013780: 891b ldrh r3, [r3, #8]
8013782: 461d mov r5, r3
8013784: 68bb ldr r3, [r7, #8]
8013786: 68db ldr r3, [r3, #12]
8013788: 899b ldrh r3, [r3, #12]
801378a: b29b uxth r3, r3
801378c: 4618 mov r0, r3
801378e: f7fb fb7f bl 800ee90 <lwip_htons>
8013792: 4603 mov r3, r0
8013794: b2db uxtb r3, r3
8013796: f003 0303 and.w r3, r3, #3
801379a: 2b00 cmp r3, #0
801379c: d001 beq.n 80137a2 <tcp_free_acked_segments+0xc6>
801379e: 2301 movs r3, #1
80137a0: e000 b.n 80137a4 <tcp_free_acked_segments+0xc8>
80137a2: 2300 movs r3, #0
80137a4: 442b add r3, r5
80137a6: 18e2 adds r2, r4, r3
80137a8: 4b09 ldr r3, [pc, #36] ; (80137d0 <tcp_free_acked_segments+0xf4>)
80137aa: 681b ldr r3, [r3, #0]
80137ac: 1ad3 subs r3, r2, r3
while (seg_list != NULL &&
80137ae: 2b00 cmp r3, #0
80137b0: dd9c ble.n 80136ec <tcp_free_acked_segments+0x10>
seg_list != NULL || dbg_other_seg_list != NULL);
}
}
return seg_list;
80137b2: 68bb ldr r3, [r7, #8]
}
80137b4: 4618 mov r0, r3
80137b6: 3718 adds r7, #24
80137b8: 46bd mov sp, r7
80137ba: bdb0 pop {r4, r5, r7, pc}
80137bc: 0801d2c0 .word 0x0801d2c0
80137c0: 0801d5a8 .word 0x0801d5a8
80137c4: 0801d30c .word 0x0801d30c
80137c8: 20008754 .word 0x20008754
80137cc: 0801d5d0 .word 0x0801d5d0
80137d0: 20008750 .word 0x20008750
080137d4 <tcp_receive>:
*
* Called from tcp_process().
*/
static void
tcp_receive(struct tcp_pcb *pcb)
{
80137d4: b5b0 push {r4, r5, r7, lr}
80137d6: b094 sub sp, #80 ; 0x50
80137d8: af00 add r7, sp, #0
80137da: 6078 str r0, [r7, #4]
s16_t m;
u32_t right_wnd_edge;
int found_dupack = 0;
80137dc: 2300 movs r3, #0
80137de: 64bb str r3, [r7, #72] ; 0x48
LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
80137e0: 687b ldr r3, [r7, #4]
80137e2: 2b00 cmp r3, #0
80137e4: d106 bne.n 80137f4 <tcp_receive+0x20>
80137e6: 4ba6 ldr r3, [pc, #664] ; (8013a80 <tcp_receive+0x2ac>)
80137e8: f240 427b movw r2, #1147 ; 0x47b
80137ec: 49a5 ldr r1, [pc, #660] ; (8013a84 <tcp_receive+0x2b0>)
80137ee: 48a6 ldr r0, [pc, #664] ; (8013a88 <tcp_receive+0x2b4>)
80137f0: f007 fc18 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
80137f4: 687b ldr r3, [r7, #4]
80137f6: 7d1b ldrb r3, [r3, #20]
80137f8: 2b03 cmp r3, #3
80137fa: d806 bhi.n 801380a <tcp_receive+0x36>
80137fc: 4ba0 ldr r3, [pc, #640] ; (8013a80 <tcp_receive+0x2ac>)
80137fe: f240 427c movw r2, #1148 ; 0x47c
8013802: 49a2 ldr r1, [pc, #648] ; (8013a8c <tcp_receive+0x2b8>)
8013804: 48a0 ldr r0, [pc, #640] ; (8013a88 <tcp_receive+0x2b4>)
8013806: f007 fc0d bl 801b024 <iprintf>
if (flags & TCP_ACK) {
801380a: 4ba1 ldr r3, [pc, #644] ; (8013a90 <tcp_receive+0x2bc>)
801380c: 781b ldrb r3, [r3, #0]
801380e: f003 0310 and.w r3, r3, #16
8013812: 2b00 cmp r3, #0
8013814: f000 8263 beq.w 8013cde <tcp_receive+0x50a>
right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
8013818: 687b ldr r3, [r7, #4]
801381a: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
801381e: 461a mov r2, r3
8013820: 687b ldr r3, [r7, #4]
8013822: 6d9b ldr r3, [r3, #88] ; 0x58
8013824: 4413 add r3, r2
8013826: 633b str r3, [r7, #48] ; 0x30
/* Update window. */
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
8013828: 687b ldr r3, [r7, #4]
801382a: 6d5a ldr r2, [r3, #84] ; 0x54
801382c: 4b99 ldr r3, [pc, #612] ; (8013a94 <tcp_receive+0x2c0>)
801382e: 681b ldr r3, [r3, #0]
8013830: 1ad3 subs r3, r2, r3
8013832: 2b00 cmp r3, #0
8013834: db1b blt.n 801386e <tcp_receive+0x9a>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013836: 687b ldr r3, [r7, #4]
8013838: 6d5a ldr r2, [r3, #84] ; 0x54
801383a: 4b96 ldr r3, [pc, #600] ; (8013a94 <tcp_receive+0x2c0>)
801383c: 681b ldr r3, [r3, #0]
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
801383e: 429a cmp r2, r3
8013840: d106 bne.n 8013850 <tcp_receive+0x7c>
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013842: 687b ldr r3, [r7, #4]
8013844: 6d9a ldr r2, [r3, #88] ; 0x58
8013846: 4b94 ldr r3, [pc, #592] ; (8013a98 <tcp_receive+0x2c4>)
8013848: 681b ldr r3, [r3, #0]
801384a: 1ad3 subs r3, r2, r3
801384c: 2b00 cmp r3, #0
801384e: db0e blt.n 801386e <tcp_receive+0x9a>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
8013850: 687b ldr r3, [r7, #4]
8013852: 6d9a ldr r2, [r3, #88] ; 0x58
8013854: 4b90 ldr r3, [pc, #576] ; (8013a98 <tcp_receive+0x2c4>)
8013856: 681b ldr r3, [r3, #0]
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
8013858: 429a cmp r2, r3
801385a: d125 bne.n 80138a8 <tcp_receive+0xd4>
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
801385c: 4b8f ldr r3, [pc, #572] ; (8013a9c <tcp_receive+0x2c8>)
801385e: 681b ldr r3, [r3, #0]
8013860: 89db ldrh r3, [r3, #14]
8013862: b29a uxth r2, r3
8013864: 687b ldr r3, [r7, #4]
8013866: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
801386a: 429a cmp r2, r3
801386c: d91c bls.n 80138a8 <tcp_receive+0xd4>
pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
801386e: 4b8b ldr r3, [pc, #556] ; (8013a9c <tcp_receive+0x2c8>)
8013870: 681b ldr r3, [r3, #0]
8013872: 89db ldrh r3, [r3, #14]
8013874: b29a uxth r2, r3
8013876: 687b ldr r3, [r7, #4]
8013878: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
/* keep track of the biggest window announced by the remote host to calculate
the maximum segment size */
if (pcb->snd_wnd_max < pcb->snd_wnd) {
801387c: 687b ldr r3, [r7, #4]
801387e: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62
8013882: 687b ldr r3, [r7, #4]
8013884: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8013888: 429a cmp r2, r3
801388a: d205 bcs.n 8013898 <tcp_receive+0xc4>
pcb->snd_wnd_max = pcb->snd_wnd;
801388c: 687b ldr r3, [r7, #4]
801388e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8013892: 687b ldr r3, [r7, #4]
8013894: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
}
pcb->snd_wl1 = seqno;
8013898: 4b7e ldr r3, [pc, #504] ; (8013a94 <tcp_receive+0x2c0>)
801389a: 681a ldr r2, [r3, #0]
801389c: 687b ldr r3, [r7, #4]
801389e: 655a str r2, [r3, #84] ; 0x54
pcb->snd_wl2 = ackno;
80138a0: 4b7d ldr r3, [pc, #500] ; (8013a98 <tcp_receive+0x2c4>)
80138a2: 681a ldr r2, [r3, #0]
80138a4: 687b ldr r3, [r7, #4]
80138a6: 659a str r2, [r3, #88] ; 0x58
* If it only passes 1, should reset dupack counter
*
*/
/* Clause 1 */
if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
80138a8: 4b7b ldr r3, [pc, #492] ; (8013a98 <tcp_receive+0x2c4>)
80138aa: 681a ldr r2, [r3, #0]
80138ac: 687b ldr r3, [r7, #4]
80138ae: 6c5b ldr r3, [r3, #68] ; 0x44
80138b0: 1ad3 subs r3, r2, r3
80138b2: 2b00 cmp r3, #0
80138b4: dc58 bgt.n 8013968 <tcp_receive+0x194>
/* Clause 2 */
if (tcplen == 0) {
80138b6: 4b7a ldr r3, [pc, #488] ; (8013aa0 <tcp_receive+0x2cc>)
80138b8: 881b ldrh r3, [r3, #0]
80138ba: 2b00 cmp r3, #0
80138bc: d14b bne.n 8013956 <tcp_receive+0x182>
/* Clause 3 */
if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
80138be: 687b ldr r3, [r7, #4]
80138c0: 6d9b ldr r3, [r3, #88] ; 0x58
80138c2: 687a ldr r2, [r7, #4]
80138c4: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60
80138c8: 4413 add r3, r2
80138ca: 6b3a ldr r2, [r7, #48] ; 0x30
80138cc: 429a cmp r2, r3
80138ce: d142 bne.n 8013956 <tcp_receive+0x182>
/* Clause 4 */
if (pcb->rtime >= 0) {
80138d0: 687b ldr r3, [r7, #4]
80138d2: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80138d6: 2b00 cmp r3, #0
80138d8: db3d blt.n 8013956 <tcp_receive+0x182>
/* Clause 5 */
if (pcb->lastack == ackno) {
80138da: 687b ldr r3, [r7, #4]
80138dc: 6c5a ldr r2, [r3, #68] ; 0x44
80138de: 4b6e ldr r3, [pc, #440] ; (8013a98 <tcp_receive+0x2c4>)
80138e0: 681b ldr r3, [r3, #0]
80138e2: 429a cmp r2, r3
80138e4: d137 bne.n 8013956 <tcp_receive+0x182>
found_dupack = 1;
80138e6: 2301 movs r3, #1
80138e8: 64bb str r3, [r7, #72] ; 0x48
if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
80138ea: 687b ldr r3, [r7, #4]
80138ec: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138f0: 2bff cmp r3, #255 ; 0xff
80138f2: d007 beq.n 8013904 <tcp_receive+0x130>
++pcb->dupacks;
80138f4: 687b ldr r3, [r7, #4]
80138f6: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
80138fa: 3301 adds r3, #1
80138fc: b2da uxtb r2, r3
80138fe: 687b ldr r3, [r7, #4]
8013900: f883 2043 strb.w r2, [r3, #67] ; 0x43
}
if (pcb->dupacks > 3) {
8013904: 687b ldr r3, [r7, #4]
8013906: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
801390a: 2b03 cmp r3, #3
801390c: d91b bls.n 8013946 <tcp_receive+0x172>
/* Inflate the congestion window */
TCP_WND_INC(pcb->cwnd, pcb->mss);
801390e: 687b ldr r3, [r7, #4]
8013910: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013914: 687b ldr r3, [r7, #4]
8013916: 8e5b ldrh r3, [r3, #50] ; 0x32
8013918: 4413 add r3, r2
801391a: b29a uxth r2, r3
801391c: 687b ldr r3, [r7, #4]
801391e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013922: 429a cmp r2, r3
8013924: d30a bcc.n 801393c <tcp_receive+0x168>
8013926: 687b ldr r3, [r7, #4]
8013928: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
801392c: 687b ldr r3, [r7, #4]
801392e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013930: 4413 add r3, r2
8013932: b29a uxth r2, r3
8013934: 687b ldr r3, [r7, #4]
8013936: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
801393a: e004 b.n 8013946 <tcp_receive+0x172>
801393c: 687b ldr r3, [r7, #4]
801393e: f64f 72ff movw r2, #65535 ; 0xffff
8013942: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
}
if (pcb->dupacks >= 3) {
8013946: 687b ldr r3, [r7, #4]
8013948: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
801394c: 2b02 cmp r3, #2
801394e: d902 bls.n 8013956 <tcp_receive+0x182>
/* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
tcp_rexmit_fast(pcb);
8013950: 6878 ldr r0, [r7, #4]
8013952: f001 feed bl 8015730 <tcp_rexmit_fast>
}
}
}
/* If Clause (1) or more is true, but not a duplicate ack, reset
* count of consecutive duplicate acks */
if (!found_dupack) {
8013956: 6cbb ldr r3, [r7, #72] ; 0x48
8013958: 2b00 cmp r3, #0
801395a: f040 8160 bne.w 8013c1e <tcp_receive+0x44a>
pcb->dupacks = 0;
801395e: 687b ldr r3, [r7, #4]
8013960: 2200 movs r2, #0
8013962: f883 2043 strb.w r2, [r3, #67] ; 0x43
8013966: e15a b.n 8013c1e <tcp_receive+0x44a>
}
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013968: 4b4b ldr r3, [pc, #300] ; (8013a98 <tcp_receive+0x2c4>)
801396a: 681a ldr r2, [r3, #0]
801396c: 687b ldr r3, [r7, #4]
801396e: 6c5b ldr r3, [r3, #68] ; 0x44
8013970: 1ad3 subs r3, r2, r3
8013972: 3b01 subs r3, #1
8013974: 2b00 cmp r3, #0
8013976: f2c0 814d blt.w 8013c14 <tcp_receive+0x440>
801397a: 4b47 ldr r3, [pc, #284] ; (8013a98 <tcp_receive+0x2c4>)
801397c: 681a ldr r2, [r3, #0]
801397e: 687b ldr r3, [r7, #4]
8013980: 6d1b ldr r3, [r3, #80] ; 0x50
8013982: 1ad3 subs r3, r2, r3
8013984: 2b00 cmp r3, #0
8013986: f300 8145 bgt.w 8013c14 <tcp_receive+0x440>
tcpwnd_size_t acked;
/* Reset the "IN Fast Retransmit" flag, since we are no longer
in fast retransmit. Also reset the congestion window to the
slow start threshold. */
if (pcb->flags & TF_INFR) {
801398a: 687b ldr r3, [r7, #4]
801398c: 8b5b ldrh r3, [r3, #26]
801398e: f003 0304 and.w r3, r3, #4
8013992: 2b00 cmp r3, #0
8013994: d010 beq.n 80139b8 <tcp_receive+0x1e4>
tcp_clear_flags(pcb, TF_INFR);
8013996: 687b ldr r3, [r7, #4]
8013998: 8b5b ldrh r3, [r3, #26]
801399a: f023 0304 bic.w r3, r3, #4
801399e: b29a uxth r2, r3
80139a0: 687b ldr r3, [r7, #4]
80139a2: 835a strh r2, [r3, #26]
pcb->cwnd = pcb->ssthresh;
80139a4: 687b ldr r3, [r7, #4]
80139a6: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
80139aa: 687b ldr r3, [r7, #4]
80139ac: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->bytes_acked = 0;
80139b0: 687b ldr r3, [r7, #4]
80139b2: 2200 movs r2, #0
80139b4: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
}
/* Reset the number of retransmissions. */
pcb->nrtx = 0;
80139b8: 687b ldr r3, [r7, #4]
80139ba: 2200 movs r2, #0
80139bc: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Reset the retransmission time-out. */
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
80139c0: 687b ldr r3, [r7, #4]
80139c2: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
80139c6: 10db asrs r3, r3, #3
80139c8: b21b sxth r3, r3
80139ca: b29a uxth r2, r3
80139cc: 687b ldr r3, [r7, #4]
80139ce: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
80139d2: b29b uxth r3, r3
80139d4: 4413 add r3, r2
80139d6: b29b uxth r3, r3
80139d8: b21a sxth r2, r3
80139da: 687b ldr r3, [r7, #4]
80139dc: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
/* Record how much data this ACK acks */
acked = (tcpwnd_size_t)(ackno - pcb->lastack);
80139e0: 4b2d ldr r3, [pc, #180] ; (8013a98 <tcp_receive+0x2c4>)
80139e2: 681b ldr r3, [r3, #0]
80139e4: b29a uxth r2, r3
80139e6: 687b ldr r3, [r7, #4]
80139e8: 6c5b ldr r3, [r3, #68] ; 0x44
80139ea: b29b uxth r3, r3
80139ec: 1ad3 subs r3, r2, r3
80139ee: 85fb strh r3, [r7, #46] ; 0x2e
/* Reset the fast retransmit variables. */
pcb->dupacks = 0;
80139f0: 687b ldr r3, [r7, #4]
80139f2: 2200 movs r2, #0
80139f4: f883 2043 strb.w r2, [r3, #67] ; 0x43
pcb->lastack = ackno;
80139f8: 4b27 ldr r3, [pc, #156] ; (8013a98 <tcp_receive+0x2c4>)
80139fa: 681a ldr r2, [r3, #0]
80139fc: 687b ldr r3, [r7, #4]
80139fe: 645a str r2, [r3, #68] ; 0x44
/* Update the congestion control variables (cwnd and
ssthresh). */
if (pcb->state >= ESTABLISHED) {
8013a00: 687b ldr r3, [r7, #4]
8013a02: 7d1b ldrb r3, [r3, #20]
8013a04: 2b03 cmp r3, #3
8013a06: f240 8096 bls.w 8013b36 <tcp_receive+0x362>
if (pcb->cwnd < pcb->ssthresh) {
8013a0a: 687b ldr r3, [r7, #4]
8013a0c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a10: 687b ldr r3, [r7, #4]
8013a12: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
8013a16: 429a cmp r2, r3
8013a18: d244 bcs.n 8013aa4 <tcp_receive+0x2d0>
tcpwnd_size_t increase;
/* limit to 1 SMSS segment during period following RTO */
u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
8013a1a: 687b ldr r3, [r7, #4]
8013a1c: 8b5b ldrh r3, [r3, #26]
8013a1e: f403 6300 and.w r3, r3, #2048 ; 0x800
8013a22: 2b00 cmp r3, #0
8013a24: d001 beq.n 8013a2a <tcp_receive+0x256>
8013a26: 2301 movs r3, #1
8013a28: e000 b.n 8013a2c <tcp_receive+0x258>
8013a2a: 2302 movs r3, #2
8013a2c: f887 302d strb.w r3, [r7, #45] ; 0x2d
/* RFC 3465, section 2.2 Slow Start */
increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
8013a30: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
8013a34: b29a uxth r2, r3
8013a36: 687b ldr r3, [r7, #4]
8013a38: 8e5b ldrh r3, [r3, #50] ; 0x32
8013a3a: fb12 f303 smulbb r3, r2, r3
8013a3e: b29b uxth r3, r3
8013a40: 8dfa ldrh r2, [r7, #46] ; 0x2e
8013a42: 4293 cmp r3, r2
8013a44: bf28 it cs
8013a46: 4613 movcs r3, r2
8013a48: 857b strh r3, [r7, #42] ; 0x2a
TCP_WND_INC(pcb->cwnd, increase);
8013a4a: 687b ldr r3, [r7, #4]
8013a4c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a50: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a52: 4413 add r3, r2
8013a54: b29a uxth r2, r3
8013a56: 687b ldr r3, [r7, #4]
8013a58: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013a5c: 429a cmp r2, r3
8013a5e: d309 bcc.n 8013a74 <tcp_receive+0x2a0>
8013a60: 687b ldr r3, [r7, #4]
8013a62: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013a66: 8d7b ldrh r3, [r7, #42] ; 0x2a
8013a68: 4413 add r3, r2
8013a6a: b29a uxth r2, r3
8013a6c: 687b ldr r3, [r7, #4]
8013a6e: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a72: e060 b.n 8013b36 <tcp_receive+0x362>
8013a74: 687b ldr r3, [r7, #4]
8013a76: f64f 72ff movw r2, #65535 ; 0xffff
8013a7a: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013a7e: e05a b.n 8013b36 <tcp_receive+0x362>
8013a80: 0801d2c0 .word 0x0801d2c0
8013a84: 0801d5f0 .word 0x0801d5f0
8013a88: 0801d30c .word 0x0801d30c
8013a8c: 0801d60c .word 0x0801d60c
8013a90: 20008758 .word 0x20008758
8013a94: 2000874c .word 0x2000874c
8013a98: 20008750 .word 0x20008750
8013a9c: 2000873c .word 0x2000873c
8013aa0: 20008756 .word 0x20008756
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
} else {
/* RFC 3465, section 2.1 Congestion Avoidance */
TCP_WND_INC(pcb->bytes_acked, acked);
8013aa4: 687b ldr r3, [r7, #4]
8013aa6: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013aaa: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013aac: 4413 add r3, r2
8013aae: b29a uxth r2, r3
8013ab0: 687b ldr r3, [r7, #4]
8013ab2: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a
8013ab6: 429a cmp r2, r3
8013ab8: d309 bcc.n 8013ace <tcp_receive+0x2fa>
8013aba: 687b ldr r3, [r7, #4]
8013abc: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013ac0: 8dfb ldrh r3, [r7, #46] ; 0x2e
8013ac2: 4413 add r3, r2
8013ac4: b29a uxth r2, r3
8013ac6: 687b ldr r3, [r7, #4]
8013ac8: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
8013acc: e004 b.n 8013ad8 <tcp_receive+0x304>
8013ace: 687b ldr r3, [r7, #4]
8013ad0: f64f 72ff movw r2, #65535 ; 0xffff
8013ad4: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
if (pcb->bytes_acked >= pcb->cwnd) {
8013ad8: 687b ldr r3, [r7, #4]
8013ada: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013ade: 687b ldr r3, [r7, #4]
8013ae0: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013ae4: 429a cmp r2, r3
8013ae6: d326 bcc.n 8013b36 <tcp_receive+0x362>
pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
8013ae8: 687b ldr r3, [r7, #4]
8013aea: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
8013aee: 687b ldr r3, [r7, #4]
8013af0: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013af4: 1ad3 subs r3, r2, r3
8013af6: b29a uxth r2, r3
8013af8: 687b ldr r3, [r7, #4]
8013afa: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
TCP_WND_INC(pcb->cwnd, pcb->mss);
8013afe: 687b ldr r3, [r7, #4]
8013b00: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013b04: 687b ldr r3, [r7, #4]
8013b06: 8e5b ldrh r3, [r3, #50] ; 0x32
8013b08: 4413 add r3, r2
8013b0a: b29a uxth r2, r3
8013b0c: 687b ldr r3, [r7, #4]
8013b0e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8013b12: 429a cmp r2, r3
8013b14: d30a bcc.n 8013b2c <tcp_receive+0x358>
8013b16: 687b ldr r3, [r7, #4]
8013b18: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8013b1c: 687b ldr r3, [r7, #4]
8013b1e: 8e5b ldrh r3, [r3, #50] ; 0x32
8013b20: 4413 add r3, r2
8013b22: b29a uxth r2, r3
8013b24: 687b ldr r3, [r7, #4]
8013b26: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
8013b2a: e004 b.n 8013b36 <tcp_receive+0x362>
8013b2c: 687b ldr r3, [r7, #4]
8013b2e: f64f 72ff movw r2, #65535 ; 0xffff
8013b32: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
pcb->unacked != NULL ?
lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
/* Remove segment from the unacknowledged list if the incoming
ACK acknowledges them. */
pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
8013b36: 687b ldr r3, [r7, #4]
8013b38: 6f19 ldr r1, [r3, #112] ; 0x70
8013b3a: 687b ldr r3, [r7, #4]
8013b3c: 6edb ldr r3, [r3, #108] ; 0x6c
8013b3e: 4a98 ldr r2, [pc, #608] ; (8013da0 <tcp_receive+0x5cc>)
8013b40: 6878 ldr r0, [r7, #4]
8013b42: f7ff fdcb bl 80136dc <tcp_free_acked_segments>
8013b46: 4602 mov r2, r0
8013b48: 687b ldr r3, [r7, #4]
8013b4a: 671a str r2, [r3, #112] ; 0x70
on the list are acknowledged by the ACK. This may seem
strange since an "unsent" segment shouldn't be acked. The
rationale is that lwIP puts all outstanding segments on the
->unsent list after a retransmission, so these segments may
in fact have been sent once. */
pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
8013b4c: 687b ldr r3, [r7, #4]
8013b4e: 6ed9 ldr r1, [r3, #108] ; 0x6c
8013b50: 687b ldr r3, [r7, #4]
8013b52: 6f1b ldr r3, [r3, #112] ; 0x70
8013b54: 4a93 ldr r2, [pc, #588] ; (8013da4 <tcp_receive+0x5d0>)
8013b56: 6878 ldr r0, [r7, #4]
8013b58: f7ff fdc0 bl 80136dc <tcp_free_acked_segments>
8013b5c: 4602 mov r2, r0
8013b5e: 687b ldr r3, [r7, #4]
8013b60: 66da str r2, [r3, #108] ; 0x6c
/* If there's nothing left to acknowledge, stop the retransmit
timer, otherwise reset it to start again */
if (pcb->unacked == NULL) {
8013b62: 687b ldr r3, [r7, #4]
8013b64: 6f1b ldr r3, [r3, #112] ; 0x70
8013b66: 2b00 cmp r3, #0
8013b68: d104 bne.n 8013b74 <tcp_receive+0x3a0>
pcb->rtime = -1;
8013b6a: 687b ldr r3, [r7, #4]
8013b6c: f64f 72ff movw r2, #65535 ; 0xffff
8013b70: 861a strh r2, [r3, #48] ; 0x30
8013b72: e002 b.n 8013b7a <tcp_receive+0x3a6>
} else {
pcb->rtime = 0;
8013b74: 687b ldr r3, [r7, #4]
8013b76: 2200 movs r2, #0
8013b78: 861a strh r2, [r3, #48] ; 0x30
}
pcb->polltmr = 0;
8013b7a: 687b ldr r3, [r7, #4]
8013b7c: 2200 movs r2, #0
8013b7e: 771a strb r2, [r3, #28]
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
8013b80: 687b ldr r3, [r7, #4]
8013b82: 6edb ldr r3, [r3, #108] ; 0x6c
8013b84: 2b00 cmp r3, #0
8013b86: d103 bne.n 8013b90 <tcp_receive+0x3bc>
pcb->unsent_oversize = 0;
8013b88: 687b ldr r3, [r7, #4]
8013b8a: 2200 movs r2, #0
8013b8c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
/* Inform neighbor reachability of forward progress. */
nd6_reachability_hint(ip6_current_src_addr());
}
#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
8013b90: 687b ldr r3, [r7, #4]
8013b92: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64
8013b96: 4b84 ldr r3, [pc, #528] ; (8013da8 <tcp_receive+0x5d4>)
8013b98: 881b ldrh r3, [r3, #0]
8013b9a: 4413 add r3, r2
8013b9c: b29a uxth r2, r3
8013b9e: 687b ldr r3, [r7, #4]
8013ba0: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
/* check if this ACK ends our retransmission of in-flight data */
if (pcb->flags & TF_RTO) {
8013ba4: 687b ldr r3, [r7, #4]
8013ba6: 8b5b ldrh r3, [r3, #26]
8013ba8: f403 6300 and.w r3, r3, #2048 ; 0x800
8013bac: 2b00 cmp r3, #0
8013bae: d035 beq.n 8013c1c <tcp_receive+0x448>
/* RTO is done if
1) both queues are empty or
2) unacked is empty and unsent head contains data not part of RTO or
3) unacked head contains data not part of RTO */
if (pcb->unacked == NULL) {
8013bb0: 687b ldr r3, [r7, #4]
8013bb2: 6f1b ldr r3, [r3, #112] ; 0x70
8013bb4: 2b00 cmp r3, #0
8013bb6: d118 bne.n 8013bea <tcp_receive+0x416>
if ((pcb->unsent == NULL) ||
8013bb8: 687b ldr r3, [r7, #4]
8013bba: 6edb ldr r3, [r3, #108] ; 0x6c
8013bbc: 2b00 cmp r3, #0
8013bbe: d00c beq.n 8013bda <tcp_receive+0x406>
(TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
8013bc0: 687b ldr r3, [r7, #4]
8013bc2: 6cdc ldr r4, [r3, #76] ; 0x4c
8013bc4: 687b ldr r3, [r7, #4]
8013bc6: 6edb ldr r3, [r3, #108] ; 0x6c
8013bc8: 68db ldr r3, [r3, #12]
8013bca: 685b ldr r3, [r3, #4]
8013bcc: 4618 mov r0, r3
8013bce: f7fb f974 bl 800eeba <lwip_htonl>
8013bd2: 4603 mov r3, r0
8013bd4: 1ae3 subs r3, r4, r3
if ((pcb->unsent == NULL) ||
8013bd6: 2b00 cmp r3, #0
8013bd8: dc20 bgt.n 8013c1c <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013bda: 687b ldr r3, [r7, #4]
8013bdc: 8b5b ldrh r3, [r3, #26]
8013bde: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013be2: b29a uxth r2, r3
8013be4: 687b ldr r3, [r7, #4]
8013be6: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013be8: e018 b.n 8013c1c <tcp_receive+0x448>
}
} else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
8013bea: 687b ldr r3, [r7, #4]
8013bec: 6cdc ldr r4, [r3, #76] ; 0x4c
8013bee: 687b ldr r3, [r7, #4]
8013bf0: 6f1b ldr r3, [r3, #112] ; 0x70
8013bf2: 68db ldr r3, [r3, #12]
8013bf4: 685b ldr r3, [r3, #4]
8013bf6: 4618 mov r0, r3
8013bf8: f7fb f95f bl 800eeba <lwip_htonl>
8013bfc: 4603 mov r3, r0
8013bfe: 1ae3 subs r3, r4, r3
8013c00: 2b00 cmp r3, #0
8013c02: dc0b bgt.n 8013c1c <tcp_receive+0x448>
tcp_clear_flags(pcb, TF_RTO);
8013c04: 687b ldr r3, [r7, #4]
8013c06: 8b5b ldrh r3, [r3, #26]
8013c08: f423 6300 bic.w r3, r3, #2048 ; 0x800
8013c0c: b29a uxth r2, r3
8013c0e: 687b ldr r3, [r7, #4]
8013c10: 835a strh r2, [r3, #26]
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013c12: e003 b.n 8013c1c <tcp_receive+0x448>
}
}
/* End of ACK for new data processing. */
} else {
/* Out of sequence ACK, didn't really ack anything */
tcp_send_empty_ack(pcb);
8013c14: 6878 ldr r0, [r7, #4]
8013c16: f001 ff85 bl 8015b24 <tcp_send_empty_ack>
8013c1a: e000 b.n 8013c1e <tcp_receive+0x44a>
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
8013c1c: bf00 nop
pcb->rttest, pcb->rtseq, ackno));
/* RTT estimation calculations. This is done by checking if the
incoming segment acknowledges the segment we use to take a
round-trip time measurement. */
if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
8013c1e: 687b ldr r3, [r7, #4]
8013c20: 6b5b ldr r3, [r3, #52] ; 0x34
8013c22: 2b00 cmp r3, #0
8013c24: d05b beq.n 8013cde <tcp_receive+0x50a>
8013c26: 687b ldr r3, [r7, #4]
8013c28: 6b9a ldr r2, [r3, #56] ; 0x38
8013c2a: 4b60 ldr r3, [pc, #384] ; (8013dac <tcp_receive+0x5d8>)
8013c2c: 681b ldr r3, [r3, #0]
8013c2e: 1ad3 subs r3, r2, r3
8013c30: 2b00 cmp r3, #0
8013c32: da54 bge.n 8013cde <tcp_receive+0x50a>
/* diff between this shouldn't exceed 32K since this are tcp timer ticks
and a round-trip shouldn't be that long... */
m = (s16_t)(tcp_ticks - pcb->rttest);
8013c34: 4b5e ldr r3, [pc, #376] ; (8013db0 <tcp_receive+0x5dc>)
8013c36: 681b ldr r3, [r3, #0]
8013c38: b29a uxth r2, r3
8013c3a: 687b ldr r3, [r7, #4]
8013c3c: 6b5b ldr r3, [r3, #52] ; 0x34
8013c3e: b29b uxth r3, r3
8013c40: 1ad3 subs r3, r2, r3
8013c42: b29b uxth r3, r3
8013c44: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
m, (u16_t)(m * TCP_SLOW_INTERVAL)));
/* This is taken directly from VJs original code in his paper */
m = (s16_t)(m - (pcb->sa >> 3));
8013c48: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c4c: 687b ldr r3, [r7, #4]
8013c4e: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c52: 10db asrs r3, r3, #3
8013c54: b21b sxth r3, r3
8013c56: b29b uxth r3, r3
8013c58: 1ad3 subs r3, r2, r3
8013c5a: b29b uxth r3, r3
8013c5c: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sa = (s16_t)(pcb->sa + m);
8013c60: 687b ldr r3, [r7, #4]
8013c62: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013c66: b29a uxth r2, r3
8013c68: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c6c: 4413 add r3, r2
8013c6e: b29b uxth r3, r3
8013c70: b21a sxth r2, r3
8013c72: 687b ldr r3, [r7, #4]
8013c74: 879a strh r2, [r3, #60] ; 0x3c
if (m < 0) {
8013c76: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e
8013c7a: 2b00 cmp r3, #0
8013c7c: da05 bge.n 8013c8a <tcp_receive+0x4b6>
m = (s16_t) - m;
8013c7e: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013c82: 425b negs r3, r3
8013c84: b29b uxth r3, r3
8013c86: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
}
m = (s16_t)(m - (pcb->sv >> 2));
8013c8a: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
8013c8e: 687b ldr r3, [r7, #4]
8013c90: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013c94: 109b asrs r3, r3, #2
8013c96: b21b sxth r3, r3
8013c98: b29b uxth r3, r3
8013c9a: 1ad3 subs r3, r2, r3
8013c9c: b29b uxth r3, r3
8013c9e: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
pcb->sv = (s16_t)(pcb->sv + m);
8013ca2: 687b ldr r3, [r7, #4]
8013ca4: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013ca8: b29a uxth r2, r3
8013caa: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
8013cae: 4413 add r3, r2
8013cb0: b29b uxth r3, r3
8013cb2: b21a sxth r2, r3
8013cb4: 687b ldr r3, [r7, #4]
8013cb6: 87da strh r2, [r3, #62] ; 0x3e
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
8013cb8: 687b ldr r3, [r7, #4]
8013cba: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
8013cbe: 10db asrs r3, r3, #3
8013cc0: b21b sxth r3, r3
8013cc2: b29a uxth r2, r3
8013cc4: 687b ldr r3, [r7, #4]
8013cc6: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
8013cca: b29b uxth r3, r3
8013ccc: 4413 add r3, r2
8013cce: b29b uxth r3, r3
8013cd0: b21a sxth r2, r3
8013cd2: 687b ldr r3, [r7, #4]
8013cd4: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
pcb->rttest = 0;
8013cd8: 687b ldr r3, [r7, #4]
8013cda: 2200 movs r2, #0
8013cdc: 635a str r2, [r3, #52] ; 0x34
/* If the incoming segment contains data, we must process it
further unless the pcb already received a FIN.
(RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
8013cde: 4b35 ldr r3, [pc, #212] ; (8013db4 <tcp_receive+0x5e0>)
8013ce0: 881b ldrh r3, [r3, #0]
8013ce2: 2b00 cmp r3, #0
8013ce4: f000 84e1 beq.w 80146aa <tcp_receive+0xed6>
8013ce8: 687b ldr r3, [r7, #4]
8013cea: 7d1b ldrb r3, [r3, #20]
8013cec: 2b06 cmp r3, #6
8013cee: f200 84dc bhi.w 80146aa <tcp_receive+0xed6>
this if the sequence number of the incoming segment is less
than rcv_nxt, and the sequence number plus the length of the
segment is larger than rcv_nxt. */
/* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013cf2: 687b ldr r3, [r7, #4]
8013cf4: 6a5a ldr r2, [r3, #36] ; 0x24
8013cf6: 4b30 ldr r3, [pc, #192] ; (8013db8 <tcp_receive+0x5e4>)
8013cf8: 681b ldr r3, [r3, #0]
8013cfa: 1ad3 subs r3, r2, r3
8013cfc: 3b01 subs r3, #1
8013cfe: 2b00 cmp r3, #0
8013d00: f2c0 808e blt.w 8013e20 <tcp_receive+0x64c>
8013d04: 687b ldr r3, [r7, #4]
8013d06: 6a5a ldr r2, [r3, #36] ; 0x24
8013d08: 4b2a ldr r3, [pc, #168] ; (8013db4 <tcp_receive+0x5e0>)
8013d0a: 881b ldrh r3, [r3, #0]
8013d0c: 4619 mov r1, r3
8013d0e: 4b2a ldr r3, [pc, #168] ; (8013db8 <tcp_receive+0x5e4>)
8013d10: 681b ldr r3, [r3, #0]
8013d12: 440b add r3, r1
8013d14: 1ad3 subs r3, r2, r3
8013d16: 3301 adds r3, #1
8013d18: 2b00 cmp r3, #0
8013d1a: f300 8081 bgt.w 8013e20 <tcp_receive+0x64c>
After we are done with adjusting the pbuf pointers we must
adjust the ->data pointer in the seg and the segment
length.*/
struct pbuf *p = inseg.p;
8013d1e: 4b27 ldr r3, [pc, #156] ; (8013dbc <tcp_receive+0x5e8>)
8013d20: 685b ldr r3, [r3, #4]
8013d22: 647b str r3, [r7, #68] ; 0x44
u32_t off32 = pcb->rcv_nxt - seqno;
8013d24: 687b ldr r3, [r7, #4]
8013d26: 6a5a ldr r2, [r3, #36] ; 0x24
8013d28: 4b23 ldr r3, [pc, #140] ; (8013db8 <tcp_receive+0x5e4>)
8013d2a: 681b ldr r3, [r3, #0]
8013d2c: 1ad3 subs r3, r2, r3
8013d2e: 627b str r3, [r7, #36] ; 0x24
u16_t new_tot_len, off;
LWIP_ASSERT("inseg.p != NULL", inseg.p);
8013d30: 4b22 ldr r3, [pc, #136] ; (8013dbc <tcp_receive+0x5e8>)
8013d32: 685b ldr r3, [r3, #4]
8013d34: 2b00 cmp r3, #0
8013d36: d106 bne.n 8013d46 <tcp_receive+0x572>
8013d38: 4b21 ldr r3, [pc, #132] ; (8013dc0 <tcp_receive+0x5ec>)
8013d3a: f240 5294 movw r2, #1428 ; 0x594
8013d3e: 4921 ldr r1, [pc, #132] ; (8013dc4 <tcp_receive+0x5f0>)
8013d40: 4821 ldr r0, [pc, #132] ; (8013dc8 <tcp_receive+0x5f4>)
8013d42: f007 f96f bl 801b024 <iprintf>
LWIP_ASSERT("insane offset!", (off32 < 0xffff));
8013d46: 6a7b ldr r3, [r7, #36] ; 0x24
8013d48: f64f 72fe movw r2, #65534 ; 0xfffe
8013d4c: 4293 cmp r3, r2
8013d4e: d906 bls.n 8013d5e <tcp_receive+0x58a>
8013d50: 4b1b ldr r3, [pc, #108] ; (8013dc0 <tcp_receive+0x5ec>)
8013d52: f240 5295 movw r2, #1429 ; 0x595
8013d56: 491d ldr r1, [pc, #116] ; (8013dcc <tcp_receive+0x5f8>)
8013d58: 481b ldr r0, [pc, #108] ; (8013dc8 <tcp_receive+0x5f4>)
8013d5a: f007 f963 bl 801b024 <iprintf>
off = (u16_t)off32;
8013d5e: 6a7b ldr r3, [r7, #36] ; 0x24
8013d60: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
8013d64: 4b15 ldr r3, [pc, #84] ; (8013dbc <tcp_receive+0x5e8>)
8013d66: 685b ldr r3, [r3, #4]
8013d68: 891b ldrh r3, [r3, #8]
8013d6a: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013d6e: 429a cmp r2, r3
8013d70: d906 bls.n 8013d80 <tcp_receive+0x5ac>
8013d72: 4b13 ldr r3, [pc, #76] ; (8013dc0 <tcp_receive+0x5ec>)
8013d74: f240 5297 movw r2, #1431 ; 0x597
8013d78: 4915 ldr r1, [pc, #84] ; (8013dd0 <tcp_receive+0x5fc>)
8013d7a: 4813 ldr r0, [pc, #76] ; (8013dc8 <tcp_receive+0x5f4>)
8013d7c: f007 f952 bl 801b024 <iprintf>
inseg.len -= off;
8013d80: 4b0e ldr r3, [pc, #56] ; (8013dbc <tcp_receive+0x5e8>)
8013d82: 891a ldrh r2, [r3, #8]
8013d84: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d88: 1ad3 subs r3, r2, r3
8013d8a: b29a uxth r2, r3
8013d8c: 4b0b ldr r3, [pc, #44] ; (8013dbc <tcp_receive+0x5e8>)
8013d8e: 811a strh r2, [r3, #8]
new_tot_len = (u16_t)(inseg.p->tot_len - off);
8013d90: 4b0a ldr r3, [pc, #40] ; (8013dbc <tcp_receive+0x5e8>)
8013d92: 685b ldr r3, [r3, #4]
8013d94: 891a ldrh r2, [r3, #8]
8013d96: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013d9a: 1ad3 subs r3, r2, r3
8013d9c: 847b strh r3, [r7, #34] ; 0x22
while (p->len < off) {
8013d9e: e029 b.n 8013df4 <tcp_receive+0x620>
8013da0: 0801d628 .word 0x0801d628
8013da4: 0801d630 .word 0x0801d630
8013da8: 20008754 .word 0x20008754
8013dac: 20008750 .word 0x20008750
8013db0: 2000f5c4 .word 0x2000f5c4
8013db4: 20008756 .word 0x20008756
8013db8: 2000874c .word 0x2000874c
8013dbc: 2000872c .word 0x2000872c
8013dc0: 0801d2c0 .word 0x0801d2c0
8013dc4: 0801d638 .word 0x0801d638
8013dc8: 0801d30c .word 0x0801d30c
8013dcc: 0801d648 .word 0x0801d648
8013dd0: 0801d658 .word 0x0801d658
off -= p->len;
8013dd4: 6c7b ldr r3, [r7, #68] ; 0x44
8013dd6: 895b ldrh r3, [r3, #10]
8013dd8: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013ddc: 1ad3 subs r3, r2, r3
8013dde: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
/* all pbufs up to and including this one have len==0, so tot_len is equal */
p->tot_len = new_tot_len;
8013de2: 6c7b ldr r3, [r7, #68] ; 0x44
8013de4: 8c7a ldrh r2, [r7, #34] ; 0x22
8013de6: 811a strh r2, [r3, #8]
p->len = 0;
8013de8: 6c7b ldr r3, [r7, #68] ; 0x44
8013dea: 2200 movs r2, #0
8013dec: 815a strh r2, [r3, #10]
p = p->next;
8013dee: 6c7b ldr r3, [r7, #68] ; 0x44
8013df0: 681b ldr r3, [r3, #0]
8013df2: 647b str r3, [r7, #68] ; 0x44
while (p->len < off) {
8013df4: 6c7b ldr r3, [r7, #68] ; 0x44
8013df6: 895b ldrh r3, [r3, #10]
8013df8: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
8013dfc: 429a cmp r2, r3
8013dfe: d8e9 bhi.n 8013dd4 <tcp_receive+0x600>
}
/* cannot fail... */
pbuf_remove_header(p, off);
8013e00: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
8013e04: 4619 mov r1, r3
8013e06: 6c78 ldr r0, [r7, #68] ; 0x44
8013e08: f7fc fb70 bl 80104ec <pbuf_remove_header>
inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
8013e0c: 687b ldr r3, [r7, #4]
8013e0e: 6a5b ldr r3, [r3, #36] ; 0x24
8013e10: 4a91 ldr r2, [pc, #580] ; (8014058 <tcp_receive+0x884>)
8013e12: 6013 str r3, [r2, #0]
8013e14: 4b91 ldr r3, [pc, #580] ; (801405c <tcp_receive+0x888>)
8013e16: 68db ldr r3, [r3, #12]
8013e18: 4a8f ldr r2, [pc, #572] ; (8014058 <tcp_receive+0x884>)
8013e1a: 6812 ldr r2, [r2, #0]
8013e1c: 605a str r2, [r3, #4]
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
8013e1e: e00d b.n 8013e3c <tcp_receive+0x668>
} else {
if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
8013e20: 4b8d ldr r3, [pc, #564] ; (8014058 <tcp_receive+0x884>)
8013e22: 681a ldr r2, [r3, #0]
8013e24: 687b ldr r3, [r7, #4]
8013e26: 6a5b ldr r3, [r3, #36] ; 0x24
8013e28: 1ad3 subs r3, r2, r3
8013e2a: 2b00 cmp r3, #0
8013e2c: da06 bge.n 8013e3c <tcp_receive+0x668>
/* the whole segment is < rcv_nxt */
/* must be a duplicate of a packet that has already been correctly handled */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
tcp_ack_now(pcb);
8013e2e: 687b ldr r3, [r7, #4]
8013e30: 8b5b ldrh r3, [r3, #26]
8013e32: f043 0302 orr.w r3, r3, #2
8013e36: b29a uxth r2, r3
8013e38: 687b ldr r3, [r7, #4]
8013e3a: 835a strh r2, [r3, #26]
}
/* The sequence number must be within the window (above rcv_nxt
and below rcv_nxt + rcv_wnd) in order to be further
processed. */
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
8013e3c: 4b86 ldr r3, [pc, #536] ; (8014058 <tcp_receive+0x884>)
8013e3e: 681a ldr r2, [r3, #0]
8013e40: 687b ldr r3, [r7, #4]
8013e42: 6a5b ldr r3, [r3, #36] ; 0x24
8013e44: 1ad3 subs r3, r2, r3
8013e46: 2b00 cmp r3, #0
8013e48: f2c0 842a blt.w 80146a0 <tcp_receive+0xecc>
8013e4c: 4b82 ldr r3, [pc, #520] ; (8014058 <tcp_receive+0x884>)
8013e4e: 681a ldr r2, [r3, #0]
8013e50: 687b ldr r3, [r7, #4]
8013e52: 6a5b ldr r3, [r3, #36] ; 0x24
8013e54: 6879 ldr r1, [r7, #4]
8013e56: 8d09 ldrh r1, [r1, #40] ; 0x28
8013e58: 440b add r3, r1
8013e5a: 1ad3 subs r3, r2, r3
8013e5c: 3301 adds r3, #1
8013e5e: 2b00 cmp r3, #0
8013e60: f300 841e bgt.w 80146a0 <tcp_receive+0xecc>
pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
if (pcb->rcv_nxt == seqno) {
8013e64: 687b ldr r3, [r7, #4]
8013e66: 6a5a ldr r2, [r3, #36] ; 0x24
8013e68: 4b7b ldr r3, [pc, #492] ; (8014058 <tcp_receive+0x884>)
8013e6a: 681b ldr r3, [r3, #0]
8013e6c: 429a cmp r2, r3
8013e6e: f040 829a bne.w 80143a6 <tcp_receive+0xbd2>
/* The incoming segment is the next in sequence. We check if
we have to trim the end of the segment and update rcv_nxt
and pass the data to the application. */
tcplen = TCP_TCPLEN(&inseg);
8013e72: 4b7a ldr r3, [pc, #488] ; (801405c <tcp_receive+0x888>)
8013e74: 891c ldrh r4, [r3, #8]
8013e76: 4b79 ldr r3, [pc, #484] ; (801405c <tcp_receive+0x888>)
8013e78: 68db ldr r3, [r3, #12]
8013e7a: 899b ldrh r3, [r3, #12]
8013e7c: b29b uxth r3, r3
8013e7e: 4618 mov r0, r3
8013e80: f7fb f806 bl 800ee90 <lwip_htons>
8013e84: 4603 mov r3, r0
8013e86: b2db uxtb r3, r3
8013e88: f003 0303 and.w r3, r3, #3
8013e8c: 2b00 cmp r3, #0
8013e8e: d001 beq.n 8013e94 <tcp_receive+0x6c0>
8013e90: 2301 movs r3, #1
8013e92: e000 b.n 8013e96 <tcp_receive+0x6c2>
8013e94: 2300 movs r3, #0
8013e96: 4423 add r3, r4
8013e98: b29a uxth r2, r3
8013e9a: 4b71 ldr r3, [pc, #452] ; (8014060 <tcp_receive+0x88c>)
8013e9c: 801a strh r2, [r3, #0]
if (tcplen > pcb->rcv_wnd) {
8013e9e: 687b ldr r3, [r7, #4]
8013ea0: 8d1a ldrh r2, [r3, #40] ; 0x28
8013ea2: 4b6f ldr r3, [pc, #444] ; (8014060 <tcp_receive+0x88c>)
8013ea4: 881b ldrh r3, [r3, #0]
8013ea6: 429a cmp r2, r3
8013ea8: d275 bcs.n 8013f96 <tcp_receive+0x7c2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013eaa: 4b6c ldr r3, [pc, #432] ; (801405c <tcp_receive+0x888>)
8013eac: 68db ldr r3, [r3, #12]
8013eae: 899b ldrh r3, [r3, #12]
8013eb0: b29b uxth r3, r3
8013eb2: 4618 mov r0, r3
8013eb4: f7fa ffec bl 800ee90 <lwip_htons>
8013eb8: 4603 mov r3, r0
8013eba: b2db uxtb r3, r3
8013ebc: f003 0301 and.w r3, r3, #1
8013ec0: 2b00 cmp r3, #0
8013ec2: d01f beq.n 8013f04 <tcp_receive+0x730>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
8013ec4: 4b65 ldr r3, [pc, #404] ; (801405c <tcp_receive+0x888>)
8013ec6: 68db ldr r3, [r3, #12]
8013ec8: 899b ldrh r3, [r3, #12]
8013eca: b29b uxth r3, r3
8013ecc: b21b sxth r3, r3
8013ece: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8013ed2: b21c sxth r4, r3
8013ed4: 4b61 ldr r3, [pc, #388] ; (801405c <tcp_receive+0x888>)
8013ed6: 68db ldr r3, [r3, #12]
8013ed8: 899b ldrh r3, [r3, #12]
8013eda: b29b uxth r3, r3
8013edc: 4618 mov r0, r3
8013ede: f7fa ffd7 bl 800ee90 <lwip_htons>
8013ee2: 4603 mov r3, r0
8013ee4: b2db uxtb r3, r3
8013ee6: b29b uxth r3, r3
8013ee8: f003 033e and.w r3, r3, #62 ; 0x3e
8013eec: b29b uxth r3, r3
8013eee: 4618 mov r0, r3
8013ef0: f7fa ffce bl 800ee90 <lwip_htons>
8013ef4: 4603 mov r3, r0
8013ef6: b21b sxth r3, r3
8013ef8: 4323 orrs r3, r4
8013efa: b21a sxth r2, r3
8013efc: 4b57 ldr r3, [pc, #348] ; (801405c <tcp_receive+0x888>)
8013efe: 68db ldr r3, [r3, #12]
8013f00: b292 uxth r2, r2
8013f02: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
TCPWND_CHECK16(pcb->rcv_wnd);
inseg.len = (u16_t)pcb->rcv_wnd;
8013f04: 687b ldr r3, [r7, #4]
8013f06: 8d1a ldrh r2, [r3, #40] ; 0x28
8013f08: 4b54 ldr r3, [pc, #336] ; (801405c <tcp_receive+0x888>)
8013f0a: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
8013f0c: 4b53 ldr r3, [pc, #332] ; (801405c <tcp_receive+0x888>)
8013f0e: 68db ldr r3, [r3, #12]
8013f10: 899b ldrh r3, [r3, #12]
8013f12: b29b uxth r3, r3
8013f14: 4618 mov r0, r3
8013f16: f7fa ffbb bl 800ee90 <lwip_htons>
8013f1a: 4603 mov r3, r0
8013f1c: b2db uxtb r3, r3
8013f1e: f003 0302 and.w r3, r3, #2
8013f22: 2b00 cmp r3, #0
8013f24: d005 beq.n 8013f32 <tcp_receive+0x75e>
inseg.len -= 1;
8013f26: 4b4d ldr r3, [pc, #308] ; (801405c <tcp_receive+0x888>)
8013f28: 891b ldrh r3, [r3, #8]
8013f2a: 3b01 subs r3, #1
8013f2c: b29a uxth r2, r3
8013f2e: 4b4b ldr r3, [pc, #300] ; (801405c <tcp_receive+0x888>)
8013f30: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
8013f32: 4b4a ldr r3, [pc, #296] ; (801405c <tcp_receive+0x888>)
8013f34: 685a ldr r2, [r3, #4]
8013f36: 4b49 ldr r3, [pc, #292] ; (801405c <tcp_receive+0x888>)
8013f38: 891b ldrh r3, [r3, #8]
8013f3a: 4619 mov r1, r3
8013f3c: 4610 mov r0, r2
8013f3e: f7fc f9d5 bl 80102ec <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
8013f42: 4b46 ldr r3, [pc, #280] ; (801405c <tcp_receive+0x888>)
8013f44: 891c ldrh r4, [r3, #8]
8013f46: 4b45 ldr r3, [pc, #276] ; (801405c <tcp_receive+0x888>)
8013f48: 68db ldr r3, [r3, #12]
8013f4a: 899b ldrh r3, [r3, #12]
8013f4c: b29b uxth r3, r3
8013f4e: 4618 mov r0, r3
8013f50: f7fa ff9e bl 800ee90 <lwip_htons>
8013f54: 4603 mov r3, r0
8013f56: b2db uxtb r3, r3
8013f58: f003 0303 and.w r3, r3, #3
8013f5c: 2b00 cmp r3, #0
8013f5e: d001 beq.n 8013f64 <tcp_receive+0x790>
8013f60: 2301 movs r3, #1
8013f62: e000 b.n 8013f66 <tcp_receive+0x792>
8013f64: 2300 movs r3, #0
8013f66: 4423 add r3, r4
8013f68: b29a uxth r2, r3
8013f6a: 4b3d ldr r3, [pc, #244] ; (8014060 <tcp_receive+0x88c>)
8013f6c: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8013f6e: 4b3c ldr r3, [pc, #240] ; (8014060 <tcp_receive+0x88c>)
8013f70: 881b ldrh r3, [r3, #0]
8013f72: 461a mov r2, r3
8013f74: 4b38 ldr r3, [pc, #224] ; (8014058 <tcp_receive+0x884>)
8013f76: 681b ldr r3, [r3, #0]
8013f78: 441a add r2, r3
8013f7a: 687b ldr r3, [r7, #4]
8013f7c: 6a5b ldr r3, [r3, #36] ; 0x24
8013f7e: 6879 ldr r1, [r7, #4]
8013f80: 8d09 ldrh r1, [r1, #40] ; 0x28
8013f82: 440b add r3, r1
8013f84: 429a cmp r2, r3
8013f86: d006 beq.n 8013f96 <tcp_receive+0x7c2>
8013f88: 4b36 ldr r3, [pc, #216] ; (8014064 <tcp_receive+0x890>)
8013f8a: f240 52cc movw r2, #1484 ; 0x5cc
8013f8e: 4936 ldr r1, [pc, #216] ; (8014068 <tcp_receive+0x894>)
8013f90: 4836 ldr r0, [pc, #216] ; (801406c <tcp_receive+0x898>)
8013f92: f007 f847 bl 801b024 <iprintf>
}
#if TCP_QUEUE_OOSEQ
/* Received in-sequence data, adjust ooseq data if:
- FIN has been received or
- inseq overlaps with ooseq */
if (pcb->ooseq != NULL) {
8013f96: 687b ldr r3, [r7, #4]
8013f98: 6f5b ldr r3, [r3, #116] ; 0x74
8013f9a: 2b00 cmp r3, #0
8013f9c: f000 80e7 beq.w 801416e <tcp_receive+0x99a>
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
8013fa0: 4b2e ldr r3, [pc, #184] ; (801405c <tcp_receive+0x888>)
8013fa2: 68db ldr r3, [r3, #12]
8013fa4: 899b ldrh r3, [r3, #12]
8013fa6: b29b uxth r3, r3
8013fa8: 4618 mov r0, r3
8013faa: f7fa ff71 bl 800ee90 <lwip_htons>
8013fae: 4603 mov r3, r0
8013fb0: b2db uxtb r3, r3
8013fb2: f003 0301 and.w r3, r3, #1
8013fb6: 2b00 cmp r3, #0
8013fb8: d010 beq.n 8013fdc <tcp_receive+0x808>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: received in-order FIN, binning ooseq queue\n"));
/* Received in-order FIN means anything that was received
* out of order must now have been received in-order, so
* bin the ooseq queue */
while (pcb->ooseq != NULL) {
8013fba: e00a b.n 8013fd2 <tcp_receive+0x7fe>
struct tcp_seg *old_ooseq = pcb->ooseq;
8013fbc: 687b ldr r3, [r7, #4]
8013fbe: 6f5b ldr r3, [r3, #116] ; 0x74
8013fc0: 60fb str r3, [r7, #12]
pcb->ooseq = pcb->ooseq->next;
8013fc2: 687b ldr r3, [r7, #4]
8013fc4: 6f5b ldr r3, [r3, #116] ; 0x74
8013fc6: 681a ldr r2, [r3, #0]
8013fc8: 687b ldr r3, [r7, #4]
8013fca: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(old_ooseq);
8013fcc: 68f8 ldr r0, [r7, #12]
8013fce: f7fd fd97 bl 8011b00 <tcp_seg_free>
while (pcb->ooseq != NULL) {
8013fd2: 687b ldr r3, [r7, #4]
8013fd4: 6f5b ldr r3, [r3, #116] ; 0x74
8013fd6: 2b00 cmp r3, #0
8013fd8: d1f0 bne.n 8013fbc <tcp_receive+0x7e8>
8013fda: e0c8 b.n 801416e <tcp_receive+0x99a>
}
} else {
struct tcp_seg *next = pcb->ooseq;
8013fdc: 687b ldr r3, [r7, #4]
8013fde: 6f5b ldr r3, [r3, #116] ; 0x74
8013fe0: 63fb str r3, [r7, #60] ; 0x3c
/* Remove all segments on ooseq that are covered by inseg already.
* FIN is copied from ooseq to inseg if present. */
while (next &&
8013fe2: e052 b.n 801408a <tcp_receive+0x8b6>
TCP_SEQ_GEQ(seqno + tcplen,
next->tcphdr->seqno + next->len)) {
struct tcp_seg *tmp;
/* inseg cannot have FIN here (already processed above) */
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8013fe4: 6bfb ldr r3, [r7, #60] ; 0x3c
8013fe6: 68db ldr r3, [r3, #12]
8013fe8: 899b ldrh r3, [r3, #12]
8013fea: b29b uxth r3, r3
8013fec: 4618 mov r0, r3
8013fee: f7fa ff4f bl 800ee90 <lwip_htons>
8013ff2: 4603 mov r3, r0
8013ff4: b2db uxtb r3, r3
8013ff6: f003 0301 and.w r3, r3, #1
8013ffa: 2b00 cmp r3, #0
8013ffc: d03d beq.n 801407a <tcp_receive+0x8a6>
(TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
8013ffe: 4b17 ldr r3, [pc, #92] ; (801405c <tcp_receive+0x888>)
8014000: 68db ldr r3, [r3, #12]
8014002: 899b ldrh r3, [r3, #12]
8014004: b29b uxth r3, r3
8014006: 4618 mov r0, r3
8014008: f7fa ff42 bl 800ee90 <lwip_htons>
801400c: 4603 mov r3, r0
801400e: b2db uxtb r3, r3
8014010: f003 0302 and.w r3, r3, #2
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
8014014: 2b00 cmp r3, #0
8014016: d130 bne.n 801407a <tcp_receive+0x8a6>
TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
8014018: 4b10 ldr r3, [pc, #64] ; (801405c <tcp_receive+0x888>)
801401a: 68db ldr r3, [r3, #12]
801401c: 899b ldrh r3, [r3, #12]
801401e: b29c uxth r4, r3
8014020: 2001 movs r0, #1
8014022: f7fa ff35 bl 800ee90 <lwip_htons>
8014026: 4603 mov r3, r0
8014028: 461a mov r2, r3
801402a: 4b0c ldr r3, [pc, #48] ; (801405c <tcp_receive+0x888>)
801402c: 68db ldr r3, [r3, #12]
801402e: 4322 orrs r2, r4
8014030: b292 uxth r2, r2
8014032: 819a strh r2, [r3, #12]
tcplen = TCP_TCPLEN(&inseg);
8014034: 4b09 ldr r3, [pc, #36] ; (801405c <tcp_receive+0x888>)
8014036: 891c ldrh r4, [r3, #8]
8014038: 4b08 ldr r3, [pc, #32] ; (801405c <tcp_receive+0x888>)
801403a: 68db ldr r3, [r3, #12]
801403c: 899b ldrh r3, [r3, #12]
801403e: b29b uxth r3, r3
8014040: 4618 mov r0, r3
8014042: f7fa ff25 bl 800ee90 <lwip_htons>
8014046: 4603 mov r3, r0
8014048: b2db uxtb r3, r3
801404a: f003 0303 and.w r3, r3, #3
801404e: 2b00 cmp r3, #0
8014050: d00e beq.n 8014070 <tcp_receive+0x89c>
8014052: 2301 movs r3, #1
8014054: e00d b.n 8014072 <tcp_receive+0x89e>
8014056: bf00 nop
8014058: 2000874c .word 0x2000874c
801405c: 2000872c .word 0x2000872c
8014060: 20008756 .word 0x20008756
8014064: 0801d2c0 .word 0x0801d2c0
8014068: 0801d668 .word 0x0801d668
801406c: 0801d30c .word 0x0801d30c
8014070: 2300 movs r3, #0
8014072: 4423 add r3, r4
8014074: b29a uxth r2, r3
8014076: 4b98 ldr r3, [pc, #608] ; (80142d8 <tcp_receive+0xb04>)
8014078: 801a strh r2, [r3, #0]
}
tmp = next;
801407a: 6bfb ldr r3, [r7, #60] ; 0x3c
801407c: 613b str r3, [r7, #16]
next = next->next;
801407e: 6bfb ldr r3, [r7, #60] ; 0x3c
8014080: 681b ldr r3, [r3, #0]
8014082: 63fb str r3, [r7, #60] ; 0x3c
tcp_seg_free(tmp);
8014084: 6938 ldr r0, [r7, #16]
8014086: f7fd fd3b bl 8011b00 <tcp_seg_free>
while (next &&
801408a: 6bfb ldr r3, [r7, #60] ; 0x3c
801408c: 2b00 cmp r3, #0
801408e: d00e beq.n 80140ae <tcp_receive+0x8da>
TCP_SEQ_GEQ(seqno + tcplen,
8014090: 4b91 ldr r3, [pc, #580] ; (80142d8 <tcp_receive+0xb04>)
8014092: 881b ldrh r3, [r3, #0]
8014094: 461a mov r2, r3
8014096: 4b91 ldr r3, [pc, #580] ; (80142dc <tcp_receive+0xb08>)
8014098: 681b ldr r3, [r3, #0]
801409a: 441a add r2, r3
801409c: 6bfb ldr r3, [r7, #60] ; 0x3c
801409e: 68db ldr r3, [r3, #12]
80140a0: 685b ldr r3, [r3, #4]
80140a2: 6bf9 ldr r1, [r7, #60] ; 0x3c
80140a4: 8909 ldrh r1, [r1, #8]
80140a6: 440b add r3, r1
80140a8: 1ad3 subs r3, r2, r3
while (next &&
80140aa: 2b00 cmp r3, #0
80140ac: da9a bge.n 8013fe4 <tcp_receive+0x810>
}
/* Now trim right side of inseg if it overlaps with the first
* segment on ooseq */
if (next &&
80140ae: 6bfb ldr r3, [r7, #60] ; 0x3c
80140b0: 2b00 cmp r3, #0
80140b2: d059 beq.n 8014168 <tcp_receive+0x994>
TCP_SEQ_GT(seqno + tcplen,
80140b4: 4b88 ldr r3, [pc, #544] ; (80142d8 <tcp_receive+0xb04>)
80140b6: 881b ldrh r3, [r3, #0]
80140b8: 461a mov r2, r3
80140ba: 4b88 ldr r3, [pc, #544] ; (80142dc <tcp_receive+0xb08>)
80140bc: 681b ldr r3, [r3, #0]
80140be: 441a add r2, r3
80140c0: 6bfb ldr r3, [r7, #60] ; 0x3c
80140c2: 68db ldr r3, [r3, #12]
80140c4: 685b ldr r3, [r3, #4]
80140c6: 1ad3 subs r3, r2, r3
if (next &&
80140c8: 2b00 cmp r3, #0
80140ca: dd4d ble.n 8014168 <tcp_receive+0x994>
next->tcphdr->seqno)) {
/* inseg cannot have FIN here (already processed above) */
inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
80140cc: 6bfb ldr r3, [r7, #60] ; 0x3c
80140ce: 68db ldr r3, [r3, #12]
80140d0: 685b ldr r3, [r3, #4]
80140d2: b29a uxth r2, r3
80140d4: 4b81 ldr r3, [pc, #516] ; (80142dc <tcp_receive+0xb08>)
80140d6: 681b ldr r3, [r3, #0]
80140d8: b29b uxth r3, r3
80140da: 1ad3 subs r3, r2, r3
80140dc: b29a uxth r2, r3
80140de: 4b80 ldr r3, [pc, #512] ; (80142e0 <tcp_receive+0xb0c>)
80140e0: 811a strh r2, [r3, #8]
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
80140e2: 4b7f ldr r3, [pc, #508] ; (80142e0 <tcp_receive+0xb0c>)
80140e4: 68db ldr r3, [r3, #12]
80140e6: 899b ldrh r3, [r3, #12]
80140e8: b29b uxth r3, r3
80140ea: 4618 mov r0, r3
80140ec: f7fa fed0 bl 800ee90 <lwip_htons>
80140f0: 4603 mov r3, r0
80140f2: b2db uxtb r3, r3
80140f4: f003 0302 and.w r3, r3, #2
80140f8: 2b00 cmp r3, #0
80140fa: d005 beq.n 8014108 <tcp_receive+0x934>
inseg.len -= 1;
80140fc: 4b78 ldr r3, [pc, #480] ; (80142e0 <tcp_receive+0xb0c>)
80140fe: 891b ldrh r3, [r3, #8]
8014100: 3b01 subs r3, #1
8014102: b29a uxth r2, r3
8014104: 4b76 ldr r3, [pc, #472] ; (80142e0 <tcp_receive+0xb0c>)
8014106: 811a strh r2, [r3, #8]
}
pbuf_realloc(inseg.p, inseg.len);
8014108: 4b75 ldr r3, [pc, #468] ; (80142e0 <tcp_receive+0xb0c>)
801410a: 685a ldr r2, [r3, #4]
801410c: 4b74 ldr r3, [pc, #464] ; (80142e0 <tcp_receive+0xb0c>)
801410e: 891b ldrh r3, [r3, #8]
8014110: 4619 mov r1, r3
8014112: 4610 mov r0, r2
8014114: f7fc f8ea bl 80102ec <pbuf_realloc>
tcplen = TCP_TCPLEN(&inseg);
8014118: 4b71 ldr r3, [pc, #452] ; (80142e0 <tcp_receive+0xb0c>)
801411a: 891c ldrh r4, [r3, #8]
801411c: 4b70 ldr r3, [pc, #448] ; (80142e0 <tcp_receive+0xb0c>)
801411e: 68db ldr r3, [r3, #12]
8014120: 899b ldrh r3, [r3, #12]
8014122: b29b uxth r3, r3
8014124: 4618 mov r0, r3
8014126: f7fa feb3 bl 800ee90 <lwip_htons>
801412a: 4603 mov r3, r0
801412c: b2db uxtb r3, r3
801412e: f003 0303 and.w r3, r3, #3
8014132: 2b00 cmp r3, #0
8014134: d001 beq.n 801413a <tcp_receive+0x966>
8014136: 2301 movs r3, #1
8014138: e000 b.n 801413c <tcp_receive+0x968>
801413a: 2300 movs r3, #0
801413c: 4423 add r3, r4
801413e: b29a uxth r2, r3
8014140: 4b65 ldr r3, [pc, #404] ; (80142d8 <tcp_receive+0xb04>)
8014142: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
8014144: 4b64 ldr r3, [pc, #400] ; (80142d8 <tcp_receive+0xb04>)
8014146: 881b ldrh r3, [r3, #0]
8014148: 461a mov r2, r3
801414a: 4b64 ldr r3, [pc, #400] ; (80142dc <tcp_receive+0xb08>)
801414c: 681b ldr r3, [r3, #0]
801414e: 441a add r2, r3
8014150: 6bfb ldr r3, [r7, #60] ; 0x3c
8014152: 68db ldr r3, [r3, #12]
8014154: 685b ldr r3, [r3, #4]
8014156: 429a cmp r2, r3
8014158: d006 beq.n 8014168 <tcp_receive+0x994>
801415a: 4b62 ldr r3, [pc, #392] ; (80142e4 <tcp_receive+0xb10>)
801415c: f240 52fd movw r2, #1533 ; 0x5fd
8014160: 4961 ldr r1, [pc, #388] ; (80142e8 <tcp_receive+0xb14>)
8014162: 4862 ldr r0, [pc, #392] ; (80142ec <tcp_receive+0xb18>)
8014164: f006 ff5e bl 801b024 <iprintf>
(seqno + tcplen) == next->tcphdr->seqno);
}
pcb->ooseq = next;
8014168: 687b ldr r3, [r7, #4]
801416a: 6bfa ldr r2, [r7, #60] ; 0x3c
801416c: 675a str r2, [r3, #116] ; 0x74
}
}
#endif /* TCP_QUEUE_OOSEQ */
pcb->rcv_nxt = seqno + tcplen;
801416e: 4b5a ldr r3, [pc, #360] ; (80142d8 <tcp_receive+0xb04>)
8014170: 881b ldrh r3, [r3, #0]
8014172: 461a mov r2, r3
8014174: 4b59 ldr r3, [pc, #356] ; (80142dc <tcp_receive+0xb08>)
8014176: 681b ldr r3, [r3, #0]
8014178: 441a add r2, r3
801417a: 687b ldr r3, [r7, #4]
801417c: 625a str r2, [r3, #36] ; 0x24
/* Update the receiver's (our) window. */
LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
801417e: 687b ldr r3, [r7, #4]
8014180: 8d1a ldrh r2, [r3, #40] ; 0x28
8014182: 4b55 ldr r3, [pc, #340] ; (80142d8 <tcp_receive+0xb04>)
8014184: 881b ldrh r3, [r3, #0]
8014186: 429a cmp r2, r3
8014188: d206 bcs.n 8014198 <tcp_receive+0x9c4>
801418a: 4b56 ldr r3, [pc, #344] ; (80142e4 <tcp_receive+0xb10>)
801418c: f240 6207 movw r2, #1543 ; 0x607
8014190: 4957 ldr r1, [pc, #348] ; (80142f0 <tcp_receive+0xb1c>)
8014192: 4856 ldr r0, [pc, #344] ; (80142ec <tcp_receive+0xb18>)
8014194: f006 ff46 bl 801b024 <iprintf>
pcb->rcv_wnd -= tcplen;
8014198: 687b ldr r3, [r7, #4]
801419a: 8d1a ldrh r2, [r3, #40] ; 0x28
801419c: 4b4e ldr r3, [pc, #312] ; (80142d8 <tcp_receive+0xb04>)
801419e: 881b ldrh r3, [r3, #0]
80141a0: 1ad3 subs r3, r2, r3
80141a2: b29a uxth r2, r3
80141a4: 687b ldr r3, [r7, #4]
80141a6: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
80141a8: 6878 ldr r0, [r7, #4]
80141aa: f7fc ffcd bl 8011148 <tcp_update_rcv_ann_wnd>
chains its data on this pbuf as well.
If the segment was a FIN, we set the TF_GOT_FIN flag that will
be used to indicate to the application that the remote side has
closed its end of the connection. */
if (inseg.p->tot_len > 0) {
80141ae: 4b4c ldr r3, [pc, #304] ; (80142e0 <tcp_receive+0xb0c>)
80141b0: 685b ldr r3, [r3, #4]
80141b2: 891b ldrh r3, [r3, #8]
80141b4: 2b00 cmp r3, #0
80141b6: d006 beq.n 80141c6 <tcp_receive+0x9f2>
recv_data = inseg.p;
80141b8: 4b49 ldr r3, [pc, #292] ; (80142e0 <tcp_receive+0xb0c>)
80141ba: 685b ldr r3, [r3, #4]
80141bc: 4a4d ldr r2, [pc, #308] ; (80142f4 <tcp_receive+0xb20>)
80141be: 6013 str r3, [r2, #0]
/* Since this pbuf now is the responsibility of the
application, we delete our reference to it so that we won't
(mistakingly) deallocate it. */
inseg.p = NULL;
80141c0: 4b47 ldr r3, [pc, #284] ; (80142e0 <tcp_receive+0xb0c>)
80141c2: 2200 movs r2, #0
80141c4: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
80141c6: 4b46 ldr r3, [pc, #280] ; (80142e0 <tcp_receive+0xb0c>)
80141c8: 68db ldr r3, [r3, #12]
80141ca: 899b ldrh r3, [r3, #12]
80141cc: b29b uxth r3, r3
80141ce: 4618 mov r0, r3
80141d0: f7fa fe5e bl 800ee90 <lwip_htons>
80141d4: 4603 mov r3, r0
80141d6: b2db uxtb r3, r3
80141d8: f003 0301 and.w r3, r3, #1
80141dc: 2b00 cmp r3, #0
80141de: f000 80b8 beq.w 8014352 <tcp_receive+0xb7e>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
recv_flags |= TF_GOT_FIN;
80141e2: 4b45 ldr r3, [pc, #276] ; (80142f8 <tcp_receive+0xb24>)
80141e4: 781b ldrb r3, [r3, #0]
80141e6: f043 0320 orr.w r3, r3, #32
80141ea: b2da uxtb r2, r3
80141ec: 4b42 ldr r3, [pc, #264] ; (80142f8 <tcp_receive+0xb24>)
80141ee: 701a strb r2, [r3, #0]
}
#if TCP_QUEUE_OOSEQ
/* We now check if we have segments on the ->ooseq queue that
are now in sequence. */
while (pcb->ooseq != NULL &&
80141f0: e0af b.n 8014352 <tcp_receive+0xb7e>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
struct tcp_seg *cseg = pcb->ooseq;
80141f2: 687b ldr r3, [r7, #4]
80141f4: 6f5b ldr r3, [r3, #116] ; 0x74
80141f6: 60bb str r3, [r7, #8]
seqno = pcb->ooseq->tcphdr->seqno;
80141f8: 687b ldr r3, [r7, #4]
80141fa: 6f5b ldr r3, [r3, #116] ; 0x74
80141fc: 68db ldr r3, [r3, #12]
80141fe: 685b ldr r3, [r3, #4]
8014200: 4a36 ldr r2, [pc, #216] ; (80142dc <tcp_receive+0xb08>)
8014202: 6013 str r3, [r2, #0]
pcb->rcv_nxt += TCP_TCPLEN(cseg);
8014204: 68bb ldr r3, [r7, #8]
8014206: 891b ldrh r3, [r3, #8]
8014208: 461c mov r4, r3
801420a: 68bb ldr r3, [r7, #8]
801420c: 68db ldr r3, [r3, #12]
801420e: 899b ldrh r3, [r3, #12]
8014210: b29b uxth r3, r3
8014212: 4618 mov r0, r3
8014214: f7fa fe3c bl 800ee90 <lwip_htons>
8014218: 4603 mov r3, r0
801421a: b2db uxtb r3, r3
801421c: f003 0303 and.w r3, r3, #3
8014220: 2b00 cmp r3, #0
8014222: d001 beq.n 8014228 <tcp_receive+0xa54>
8014224: 2301 movs r3, #1
8014226: e000 b.n 801422a <tcp_receive+0xa56>
8014228: 2300 movs r3, #0
801422a: 191a adds r2, r3, r4
801422c: 687b ldr r3, [r7, #4]
801422e: 6a5b ldr r3, [r3, #36] ; 0x24
8014230: 441a add r2, r3
8014232: 687b ldr r3, [r7, #4]
8014234: 625a str r2, [r3, #36] ; 0x24
LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
8014236: 687b ldr r3, [r7, #4]
8014238: 8d1b ldrh r3, [r3, #40] ; 0x28
801423a: 461c mov r4, r3
801423c: 68bb ldr r3, [r7, #8]
801423e: 891b ldrh r3, [r3, #8]
8014240: 461d mov r5, r3
8014242: 68bb ldr r3, [r7, #8]
8014244: 68db ldr r3, [r3, #12]
8014246: 899b ldrh r3, [r3, #12]
8014248: b29b uxth r3, r3
801424a: 4618 mov r0, r3
801424c: f7fa fe20 bl 800ee90 <lwip_htons>
8014250: 4603 mov r3, r0
8014252: b2db uxtb r3, r3
8014254: f003 0303 and.w r3, r3, #3
8014258: 2b00 cmp r3, #0
801425a: d001 beq.n 8014260 <tcp_receive+0xa8c>
801425c: 2301 movs r3, #1
801425e: e000 b.n 8014262 <tcp_receive+0xa8e>
8014260: 2300 movs r3, #0
8014262: 442b add r3, r5
8014264: 429c cmp r4, r3
8014266: d206 bcs.n 8014276 <tcp_receive+0xaa2>
8014268: 4b1e ldr r3, [pc, #120] ; (80142e4 <tcp_receive+0xb10>)
801426a: f240 622c movw r2, #1580 ; 0x62c
801426e: 4923 ldr r1, [pc, #140] ; (80142fc <tcp_receive+0xb28>)
8014270: 481e ldr r0, [pc, #120] ; (80142ec <tcp_receive+0xb18>)
8014272: f006 fed7 bl 801b024 <iprintf>
pcb->rcv_wnd >= TCP_TCPLEN(cseg));
pcb->rcv_wnd -= TCP_TCPLEN(cseg);
8014276: 68bb ldr r3, [r7, #8]
8014278: 891b ldrh r3, [r3, #8]
801427a: 461c mov r4, r3
801427c: 68bb ldr r3, [r7, #8]
801427e: 68db ldr r3, [r3, #12]
8014280: 899b ldrh r3, [r3, #12]
8014282: b29b uxth r3, r3
8014284: 4618 mov r0, r3
8014286: f7fa fe03 bl 800ee90 <lwip_htons>
801428a: 4603 mov r3, r0
801428c: b2db uxtb r3, r3
801428e: f003 0303 and.w r3, r3, #3
8014292: 2b00 cmp r3, #0
8014294: d001 beq.n 801429a <tcp_receive+0xac6>
8014296: 2301 movs r3, #1
8014298: e000 b.n 801429c <tcp_receive+0xac8>
801429a: 2300 movs r3, #0
801429c: 1919 adds r1, r3, r4
801429e: 687b ldr r3, [r7, #4]
80142a0: 8d1a ldrh r2, [r3, #40] ; 0x28
80142a2: b28b uxth r3, r1
80142a4: 1ad3 subs r3, r2, r3
80142a6: b29a uxth r2, r3
80142a8: 687b ldr r3, [r7, #4]
80142aa: 851a strh r2, [r3, #40] ; 0x28
tcp_update_rcv_ann_wnd(pcb);
80142ac: 6878 ldr r0, [r7, #4]
80142ae: f7fc ff4b bl 8011148 <tcp_update_rcv_ann_wnd>
if (cseg->p->tot_len > 0) {
80142b2: 68bb ldr r3, [r7, #8]
80142b4: 685b ldr r3, [r3, #4]
80142b6: 891b ldrh r3, [r3, #8]
80142b8: 2b00 cmp r3, #0
80142ba: d028 beq.n 801430e <tcp_receive+0xb3a>
/* Chain this pbuf onto the pbuf that we will pass to
the application. */
/* With window scaling, this can overflow recv_data->tot_len, but
that's not a problem since we explicitly fix that before passing
recv_data to the application. */
if (recv_data) {
80142bc: 4b0d ldr r3, [pc, #52] ; (80142f4 <tcp_receive+0xb20>)
80142be: 681b ldr r3, [r3, #0]
80142c0: 2b00 cmp r3, #0
80142c2: d01d beq.n 8014300 <tcp_receive+0xb2c>
pbuf_cat(recv_data, cseg->p);
80142c4: 4b0b ldr r3, [pc, #44] ; (80142f4 <tcp_receive+0xb20>)
80142c6: 681a ldr r2, [r3, #0]
80142c8: 68bb ldr r3, [r7, #8]
80142ca: 685b ldr r3, [r3, #4]
80142cc: 4619 mov r1, r3
80142ce: 4610 mov r0, r2
80142d0: f7fc fa60 bl 8010794 <pbuf_cat>
80142d4: e018 b.n 8014308 <tcp_receive+0xb34>
80142d6: bf00 nop
80142d8: 20008756 .word 0x20008756
80142dc: 2000874c .word 0x2000874c
80142e0: 2000872c .word 0x2000872c
80142e4: 0801d2c0 .word 0x0801d2c0
80142e8: 0801d6a0 .word 0x0801d6a0
80142ec: 0801d30c .word 0x0801d30c
80142f0: 0801d6dc .word 0x0801d6dc
80142f4: 2000875c .word 0x2000875c
80142f8: 20008759 .word 0x20008759
80142fc: 0801d6fc .word 0x0801d6fc
} else {
recv_data = cseg->p;
8014300: 68bb ldr r3, [r7, #8]
8014302: 685b ldr r3, [r3, #4]
8014304: 4a70 ldr r2, [pc, #448] ; (80144c8 <tcp_receive+0xcf4>)
8014306: 6013 str r3, [r2, #0]
}
cseg->p = NULL;
8014308: 68bb ldr r3, [r7, #8]
801430a: 2200 movs r2, #0
801430c: 605a str r2, [r3, #4]
}
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
801430e: 68bb ldr r3, [r7, #8]
8014310: 68db ldr r3, [r3, #12]
8014312: 899b ldrh r3, [r3, #12]
8014314: b29b uxth r3, r3
8014316: 4618 mov r0, r3
8014318: f7fa fdba bl 800ee90 <lwip_htons>
801431c: 4603 mov r3, r0
801431e: b2db uxtb r3, r3
8014320: f003 0301 and.w r3, r3, #1
8014324: 2b00 cmp r3, #0
8014326: d00d beq.n 8014344 <tcp_receive+0xb70>
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
recv_flags |= TF_GOT_FIN;
8014328: 4b68 ldr r3, [pc, #416] ; (80144cc <tcp_receive+0xcf8>)
801432a: 781b ldrb r3, [r3, #0]
801432c: f043 0320 orr.w r3, r3, #32
8014330: b2da uxtb r2, r3
8014332: 4b66 ldr r3, [pc, #408] ; (80144cc <tcp_receive+0xcf8>)
8014334: 701a strb r2, [r3, #0]
if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
8014336: 687b ldr r3, [r7, #4]
8014338: 7d1b ldrb r3, [r3, #20]
801433a: 2b04 cmp r3, #4
801433c: d102 bne.n 8014344 <tcp_receive+0xb70>
pcb->state = CLOSE_WAIT;
801433e: 687b ldr r3, [r7, #4]
8014340: 2207 movs r2, #7
8014342: 751a strb r2, [r3, #20]
}
}
pcb->ooseq = cseg->next;
8014344: 68bb ldr r3, [r7, #8]
8014346: 681a ldr r2, [r3, #0]
8014348: 687b ldr r3, [r7, #4]
801434a: 675a str r2, [r3, #116] ; 0x74
tcp_seg_free(cseg);
801434c: 68b8 ldr r0, [r7, #8]
801434e: f7fd fbd7 bl 8011b00 <tcp_seg_free>
while (pcb->ooseq != NULL &&
8014352: 687b ldr r3, [r7, #4]
8014354: 6f5b ldr r3, [r3, #116] ; 0x74
8014356: 2b00 cmp r3, #0
8014358: d008 beq.n 801436c <tcp_receive+0xb98>
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
801435a: 687b ldr r3, [r7, #4]
801435c: 6f5b ldr r3, [r3, #116] ; 0x74
801435e: 68db ldr r3, [r3, #12]
8014360: 685a ldr r2, [r3, #4]
8014362: 687b ldr r3, [r7, #4]
8014364: 6a5b ldr r3, [r3, #36] ; 0x24
while (pcb->ooseq != NULL &&
8014366: 429a cmp r2, r3
8014368: f43f af43 beq.w 80141f2 <tcp_receive+0xa1e>
#endif /* LWIP_TCP_SACK_OUT */
#endif /* TCP_QUEUE_OOSEQ */
/* Acknowledge the segment(s). */
tcp_ack(pcb);
801436c: 687b ldr r3, [r7, #4]
801436e: 8b5b ldrh r3, [r3, #26]
8014370: f003 0301 and.w r3, r3, #1
8014374: 2b00 cmp r3, #0
8014376: d00e beq.n 8014396 <tcp_receive+0xbc2>
8014378: 687b ldr r3, [r7, #4]
801437a: 8b5b ldrh r3, [r3, #26]
801437c: f023 0301 bic.w r3, r3, #1
8014380: b29a uxth r2, r3
8014382: 687b ldr r3, [r7, #4]
8014384: 835a strh r2, [r3, #26]
8014386: 687b ldr r3, [r7, #4]
8014388: 8b5b ldrh r3, [r3, #26]
801438a: f043 0302 orr.w r3, r3, #2
801438e: b29a uxth r2, r3
8014390: 687b ldr r3, [r7, #4]
8014392: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
8014394: e188 b.n 80146a8 <tcp_receive+0xed4>
tcp_ack(pcb);
8014396: 687b ldr r3, [r7, #4]
8014398: 8b5b ldrh r3, [r3, #26]
801439a: f043 0301 orr.w r3, r3, #1
801439e: b29a uxth r2, r3
80143a0: 687b ldr r3, [r7, #4]
80143a2: 835a strh r2, [r3, #26]
if (pcb->rcv_nxt == seqno) {
80143a4: e180 b.n 80146a8 <tcp_receive+0xed4>
} else {
/* We get here if the incoming segment is out-of-sequence. */
#if TCP_QUEUE_OOSEQ
/* We queue the segment on the ->ooseq queue. */
if (pcb->ooseq == NULL) {
80143a6: 687b ldr r3, [r7, #4]
80143a8: 6f5b ldr r3, [r3, #116] ; 0x74
80143aa: 2b00 cmp r3, #0
80143ac: d106 bne.n 80143bc <tcp_receive+0xbe8>
pcb->ooseq = tcp_seg_copy(&inseg);
80143ae: 4848 ldr r0, [pc, #288] ; (80144d0 <tcp_receive+0xcfc>)
80143b0: f7fd fbbe bl 8011b30 <tcp_seg_copy>
80143b4: 4602 mov r2, r0
80143b6: 687b ldr r3, [r7, #4]
80143b8: 675a str r2, [r3, #116] ; 0x74
80143ba: e16d b.n 8014698 <tcp_receive+0xec4>
#if LWIP_TCP_SACK_OUT
/* This is the left edge of the lowest possible SACK range.
It may start before the newly received segment (possibly adjusted below). */
u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
#endif /* LWIP_TCP_SACK_OUT */
struct tcp_seg *next, *prev = NULL;
80143bc: 2300 movs r3, #0
80143be: 637b str r3, [r7, #52] ; 0x34
for (next = pcb->ooseq; next != NULL; next = next->next) {
80143c0: 687b ldr r3, [r7, #4]
80143c2: 6f5b ldr r3, [r3, #116] ; 0x74
80143c4: 63bb str r3, [r7, #56] ; 0x38
80143c6: e157 b.n 8014678 <tcp_receive+0xea4>
if (seqno == next->tcphdr->seqno) {
80143c8: 6bbb ldr r3, [r7, #56] ; 0x38
80143ca: 68db ldr r3, [r3, #12]
80143cc: 685a ldr r2, [r3, #4]
80143ce: 4b41 ldr r3, [pc, #260] ; (80144d4 <tcp_receive+0xd00>)
80143d0: 681b ldr r3, [r3, #0]
80143d2: 429a cmp r2, r3
80143d4: d11d bne.n 8014412 <tcp_receive+0xc3e>
/* The sequence number of the incoming segment is the
same as the sequence number of the segment on
->ooseq. We check the lengths to see which one to
discard. */
if (inseg.len > next->len) {
80143d6: 4b3e ldr r3, [pc, #248] ; (80144d0 <tcp_receive+0xcfc>)
80143d8: 891a ldrh r2, [r3, #8]
80143da: 6bbb ldr r3, [r7, #56] ; 0x38
80143dc: 891b ldrh r3, [r3, #8]
80143de: 429a cmp r2, r3
80143e0: f240 814f bls.w 8014682 <tcp_receive+0xeae>
/* The incoming segment is larger than the old
segment. We replace some segments with the new
one. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
80143e4: 483a ldr r0, [pc, #232] ; (80144d0 <tcp_receive+0xcfc>)
80143e6: f7fd fba3 bl 8011b30 <tcp_seg_copy>
80143ea: 6178 str r0, [r7, #20]
if (cseg != NULL) {
80143ec: 697b ldr r3, [r7, #20]
80143ee: 2b00 cmp r3, #0
80143f0: f000 8149 beq.w 8014686 <tcp_receive+0xeb2>
if (prev != NULL) {
80143f4: 6b7b ldr r3, [r7, #52] ; 0x34
80143f6: 2b00 cmp r3, #0
80143f8: d003 beq.n 8014402 <tcp_receive+0xc2e>
prev->next = cseg;
80143fa: 6b7b ldr r3, [r7, #52] ; 0x34
80143fc: 697a ldr r2, [r7, #20]
80143fe: 601a str r2, [r3, #0]
8014400: e002 b.n 8014408 <tcp_receive+0xc34>
} else {
pcb->ooseq = cseg;
8014402: 687b ldr r3, [r7, #4]
8014404: 697a ldr r2, [r7, #20]
8014406: 675a str r2, [r3, #116] ; 0x74
}
tcp_oos_insert_segment(cseg, next);
8014408: 6bb9 ldr r1, [r7, #56] ; 0x38
801440a: 6978 ldr r0, [r7, #20]
801440c: f7ff f8de bl 80135cc <tcp_oos_insert_segment>
}
break;
8014410: e139 b.n 8014686 <tcp_receive+0xeb2>
segment was smaller than the old one; in either
case, we ditch the incoming segment. */
break;
}
} else {
if (prev == NULL) {
8014412: 6b7b ldr r3, [r7, #52] ; 0x34
8014414: 2b00 cmp r3, #0
8014416: d117 bne.n 8014448 <tcp_receive+0xc74>
if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
8014418: 4b2e ldr r3, [pc, #184] ; (80144d4 <tcp_receive+0xd00>)
801441a: 681a ldr r2, [r3, #0]
801441c: 6bbb ldr r3, [r7, #56] ; 0x38
801441e: 68db ldr r3, [r3, #12]
8014420: 685b ldr r3, [r3, #4]
8014422: 1ad3 subs r3, r2, r3
8014424: 2b00 cmp r3, #0
8014426: da57 bge.n 80144d8 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is lower
than the sequence number of the first segment on the
queue. We put the incoming segment first on the
queue. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
8014428: 4829 ldr r0, [pc, #164] ; (80144d0 <tcp_receive+0xcfc>)
801442a: f7fd fb81 bl 8011b30 <tcp_seg_copy>
801442e: 61b8 str r0, [r7, #24]
if (cseg != NULL) {
8014430: 69bb ldr r3, [r7, #24]
8014432: 2b00 cmp r3, #0
8014434: f000 8129 beq.w 801468a <tcp_receive+0xeb6>
pcb->ooseq = cseg;
8014438: 687b ldr r3, [r7, #4]
801443a: 69ba ldr r2, [r7, #24]
801443c: 675a str r2, [r3, #116] ; 0x74
tcp_oos_insert_segment(cseg, next);
801443e: 6bb9 ldr r1, [r7, #56] ; 0x38
8014440: 69b8 ldr r0, [r7, #24]
8014442: f7ff f8c3 bl 80135cc <tcp_oos_insert_segment>
}
break;
8014446: e120 b.n 801468a <tcp_receive+0xeb6>
}
} else {
/*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
8014448: 4b22 ldr r3, [pc, #136] ; (80144d4 <tcp_receive+0xd00>)
801444a: 681a ldr r2, [r3, #0]
801444c: 6b7b ldr r3, [r7, #52] ; 0x34
801444e: 68db ldr r3, [r3, #12]
8014450: 685b ldr r3, [r3, #4]
8014452: 1ad3 subs r3, r2, r3
8014454: 3b01 subs r3, #1
8014456: 2b00 cmp r3, #0
8014458: db3e blt.n 80144d8 <tcp_receive+0xd04>
801445a: 4b1e ldr r3, [pc, #120] ; (80144d4 <tcp_receive+0xd00>)
801445c: 681a ldr r2, [r3, #0]
801445e: 6bbb ldr r3, [r7, #56] ; 0x38
8014460: 68db ldr r3, [r3, #12]
8014462: 685b ldr r3, [r3, #4]
8014464: 1ad3 subs r3, r2, r3
8014466: 3301 adds r3, #1
8014468: 2b00 cmp r3, #0
801446a: dc35 bgt.n 80144d8 <tcp_receive+0xd04>
/* The sequence number of the incoming segment is in
between the sequence numbers of the previous and
the next segment on ->ooseq. We trim trim the previous
segment, delete next segments that included in received segment
and trim received, if needed. */
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
801446c: 4818 ldr r0, [pc, #96] ; (80144d0 <tcp_receive+0xcfc>)
801446e: f7fd fb5f bl 8011b30 <tcp_seg_copy>
8014472: 61f8 str r0, [r7, #28]
if (cseg != NULL) {
8014474: 69fb ldr r3, [r7, #28]
8014476: 2b00 cmp r3, #0
8014478: f000 8109 beq.w 801468e <tcp_receive+0xeba>
if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
801447c: 6b7b ldr r3, [r7, #52] ; 0x34
801447e: 68db ldr r3, [r3, #12]
8014480: 685b ldr r3, [r3, #4]
8014482: 6b7a ldr r2, [r7, #52] ; 0x34
8014484: 8912 ldrh r2, [r2, #8]
8014486: 441a add r2, r3
8014488: 4b12 ldr r3, [pc, #72] ; (80144d4 <tcp_receive+0xd00>)
801448a: 681b ldr r3, [r3, #0]
801448c: 1ad3 subs r3, r2, r3
801448e: 2b00 cmp r3, #0
8014490: dd12 ble.n 80144b8 <tcp_receive+0xce4>
/* We need to trim the prev segment. */
prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
8014492: 4b10 ldr r3, [pc, #64] ; (80144d4 <tcp_receive+0xd00>)
8014494: 681b ldr r3, [r3, #0]
8014496: b29a uxth r2, r3
8014498: 6b7b ldr r3, [r7, #52] ; 0x34
801449a: 68db ldr r3, [r3, #12]
801449c: 685b ldr r3, [r3, #4]
801449e: b29b uxth r3, r3
80144a0: 1ad3 subs r3, r2, r3
80144a2: b29a uxth r2, r3
80144a4: 6b7b ldr r3, [r7, #52] ; 0x34
80144a6: 811a strh r2, [r3, #8]
pbuf_realloc(prev->p, prev->len);
80144a8: 6b7b ldr r3, [r7, #52] ; 0x34
80144aa: 685a ldr r2, [r3, #4]
80144ac: 6b7b ldr r3, [r7, #52] ; 0x34
80144ae: 891b ldrh r3, [r3, #8]
80144b0: 4619 mov r1, r3
80144b2: 4610 mov r0, r2
80144b4: f7fb ff1a bl 80102ec <pbuf_realloc>
}
prev->next = cseg;
80144b8: 6b7b ldr r3, [r7, #52] ; 0x34
80144ba: 69fa ldr r2, [r7, #28]
80144bc: 601a str r2, [r3, #0]
tcp_oos_insert_segment(cseg, next);
80144be: 6bb9 ldr r1, [r7, #56] ; 0x38
80144c0: 69f8 ldr r0, [r7, #28]
80144c2: f7ff f883 bl 80135cc <tcp_oos_insert_segment>
}
break;
80144c6: e0e2 b.n 801468e <tcp_receive+0xeba>
80144c8: 2000875c .word 0x2000875c
80144cc: 20008759 .word 0x20008759
80144d0: 2000872c .word 0x2000872c
80144d4: 2000874c .word 0x2000874c
#endif /* LWIP_TCP_SACK_OUT */
/* We don't use 'prev' below, so let's set it to current 'next'.
This way even if we break the loop below, 'prev' will be pointing
at the segment right in front of the newly added one. */
prev = next;
80144d8: 6bbb ldr r3, [r7, #56] ; 0x38
80144da: 637b str r3, [r7, #52] ; 0x34
/* If the "next" segment is the last segment on the
ooseq queue, we add the incoming segment to the end
of the list. */
if (next->next == NULL &&
80144dc: 6bbb ldr r3, [r7, #56] ; 0x38
80144de: 681b ldr r3, [r3, #0]
80144e0: 2b00 cmp r3, #0
80144e2: f040 80c6 bne.w 8014672 <tcp_receive+0xe9e>
TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
80144e6: 4b80 ldr r3, [pc, #512] ; (80146e8 <tcp_receive+0xf14>)
80144e8: 681a ldr r2, [r3, #0]
80144ea: 6bbb ldr r3, [r7, #56] ; 0x38
80144ec: 68db ldr r3, [r3, #12]
80144ee: 685b ldr r3, [r3, #4]
80144f0: 1ad3 subs r3, r2, r3
if (next->next == NULL &&
80144f2: 2b00 cmp r3, #0
80144f4: f340 80bd ble.w 8014672 <tcp_receive+0xe9e>
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
80144f8: 6bbb ldr r3, [r7, #56] ; 0x38
80144fa: 68db ldr r3, [r3, #12]
80144fc: 899b ldrh r3, [r3, #12]
80144fe: b29b uxth r3, r3
8014500: 4618 mov r0, r3
8014502: f7fa fcc5 bl 800ee90 <lwip_htons>
8014506: 4603 mov r3, r0
8014508: b2db uxtb r3, r3
801450a: f003 0301 and.w r3, r3, #1
801450e: 2b00 cmp r3, #0
8014510: f040 80bf bne.w 8014692 <tcp_receive+0xebe>
/* segment "next" already contains all data */
break;
}
next->next = tcp_seg_copy(&inseg);
8014514: 4875 ldr r0, [pc, #468] ; (80146ec <tcp_receive+0xf18>)
8014516: f7fd fb0b bl 8011b30 <tcp_seg_copy>
801451a: 4602 mov r2, r0
801451c: 6bbb ldr r3, [r7, #56] ; 0x38
801451e: 601a str r2, [r3, #0]
if (next->next != NULL) {
8014520: 6bbb ldr r3, [r7, #56] ; 0x38
8014522: 681b ldr r3, [r3, #0]
8014524: 2b00 cmp r3, #0
8014526: f000 80b6 beq.w 8014696 <tcp_receive+0xec2>
if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
801452a: 6bbb ldr r3, [r7, #56] ; 0x38
801452c: 68db ldr r3, [r3, #12]
801452e: 685b ldr r3, [r3, #4]
8014530: 6bba ldr r2, [r7, #56] ; 0x38
8014532: 8912 ldrh r2, [r2, #8]
8014534: 441a add r2, r3
8014536: 4b6c ldr r3, [pc, #432] ; (80146e8 <tcp_receive+0xf14>)
8014538: 681b ldr r3, [r3, #0]
801453a: 1ad3 subs r3, r2, r3
801453c: 2b00 cmp r3, #0
801453e: dd12 ble.n 8014566 <tcp_receive+0xd92>
/* We need to trim the last segment. */
next->len = (u16_t)(seqno - next->tcphdr->seqno);
8014540: 4b69 ldr r3, [pc, #420] ; (80146e8 <tcp_receive+0xf14>)
8014542: 681b ldr r3, [r3, #0]
8014544: b29a uxth r2, r3
8014546: 6bbb ldr r3, [r7, #56] ; 0x38
8014548: 68db ldr r3, [r3, #12]
801454a: 685b ldr r3, [r3, #4]
801454c: b29b uxth r3, r3
801454e: 1ad3 subs r3, r2, r3
8014550: b29a uxth r2, r3
8014552: 6bbb ldr r3, [r7, #56] ; 0x38
8014554: 811a strh r2, [r3, #8]
pbuf_realloc(next->p, next->len);
8014556: 6bbb ldr r3, [r7, #56] ; 0x38
8014558: 685a ldr r2, [r3, #4]
801455a: 6bbb ldr r3, [r7, #56] ; 0x38
801455c: 891b ldrh r3, [r3, #8]
801455e: 4619 mov r1, r3
8014560: 4610 mov r0, r2
8014562: f7fb fec3 bl 80102ec <pbuf_realloc>
}
/* check if the remote side overruns our receive window */
if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
8014566: 4b62 ldr r3, [pc, #392] ; (80146f0 <tcp_receive+0xf1c>)
8014568: 881b ldrh r3, [r3, #0]
801456a: 461a mov r2, r3
801456c: 4b5e ldr r3, [pc, #376] ; (80146e8 <tcp_receive+0xf14>)
801456e: 681b ldr r3, [r3, #0]
8014570: 441a add r2, r3
8014572: 687b ldr r3, [r7, #4]
8014574: 6a5b ldr r3, [r3, #36] ; 0x24
8014576: 6879 ldr r1, [r7, #4]
8014578: 8d09 ldrh r1, [r1, #40] ; 0x28
801457a: 440b add r3, r1
801457c: 1ad3 subs r3, r2, r3
801457e: 2b00 cmp r3, #0
8014580: f340 8089 ble.w 8014696 <tcp_receive+0xec2>
LWIP_DEBUGF(TCP_INPUT_DEBUG,
("tcp_receive: other end overran receive window"
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
8014584: 6bbb ldr r3, [r7, #56] ; 0x38
8014586: 681b ldr r3, [r3, #0]
8014588: 68db ldr r3, [r3, #12]
801458a: 899b ldrh r3, [r3, #12]
801458c: b29b uxth r3, r3
801458e: 4618 mov r0, r3
8014590: f7fa fc7e bl 800ee90 <lwip_htons>
8014594: 4603 mov r3, r0
8014596: b2db uxtb r3, r3
8014598: f003 0301 and.w r3, r3, #1
801459c: 2b00 cmp r3, #0
801459e: d022 beq.n 80145e6 <tcp_receive+0xe12>
/* Must remove the FIN from the header as we're trimming
* that byte of sequence-space from the packet */
TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
80145a0: 6bbb ldr r3, [r7, #56] ; 0x38
80145a2: 681b ldr r3, [r3, #0]
80145a4: 68db ldr r3, [r3, #12]
80145a6: 899b ldrh r3, [r3, #12]
80145a8: b29b uxth r3, r3
80145aa: b21b sxth r3, r3
80145ac: f423 537c bic.w r3, r3, #16128 ; 0x3f00
80145b0: b21c sxth r4, r3
80145b2: 6bbb ldr r3, [r7, #56] ; 0x38
80145b4: 681b ldr r3, [r3, #0]
80145b6: 68db ldr r3, [r3, #12]
80145b8: 899b ldrh r3, [r3, #12]
80145ba: b29b uxth r3, r3
80145bc: 4618 mov r0, r3
80145be: f7fa fc67 bl 800ee90 <lwip_htons>
80145c2: 4603 mov r3, r0
80145c4: b2db uxtb r3, r3
80145c6: b29b uxth r3, r3
80145c8: f003 033e and.w r3, r3, #62 ; 0x3e
80145cc: b29b uxth r3, r3
80145ce: 4618 mov r0, r3
80145d0: f7fa fc5e bl 800ee90 <lwip_htons>
80145d4: 4603 mov r3, r0
80145d6: b21b sxth r3, r3
80145d8: 4323 orrs r3, r4
80145da: b21a sxth r2, r3
80145dc: 6bbb ldr r3, [r7, #56] ; 0x38
80145de: 681b ldr r3, [r3, #0]
80145e0: 68db ldr r3, [r3, #12]
80145e2: b292 uxth r2, r2
80145e4: 819a strh r2, [r3, #12]
}
/* Adjust length of segment to fit in the window. */
next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
80145e6: 687b ldr r3, [r7, #4]
80145e8: 6a5b ldr r3, [r3, #36] ; 0x24
80145ea: b29a uxth r2, r3
80145ec: 687b ldr r3, [r7, #4]
80145ee: 8d1b ldrh r3, [r3, #40] ; 0x28
80145f0: 4413 add r3, r2
80145f2: b299 uxth r1, r3
80145f4: 4b3c ldr r3, [pc, #240] ; (80146e8 <tcp_receive+0xf14>)
80145f6: 681b ldr r3, [r3, #0]
80145f8: b29a uxth r2, r3
80145fa: 6bbb ldr r3, [r7, #56] ; 0x38
80145fc: 681b ldr r3, [r3, #0]
80145fe: 1a8a subs r2, r1, r2
8014600: b292 uxth r2, r2
8014602: 811a strh r2, [r3, #8]
pbuf_realloc(next->next->p, next->next->len);
8014604: 6bbb ldr r3, [r7, #56] ; 0x38
8014606: 681b ldr r3, [r3, #0]
8014608: 685a ldr r2, [r3, #4]
801460a: 6bbb ldr r3, [r7, #56] ; 0x38
801460c: 681b ldr r3, [r3, #0]
801460e: 891b ldrh r3, [r3, #8]
8014610: 4619 mov r1, r3
8014612: 4610 mov r0, r2
8014614: f7fb fe6a bl 80102ec <pbuf_realloc>
tcplen = TCP_TCPLEN(next->next);
8014618: 6bbb ldr r3, [r7, #56] ; 0x38
801461a: 681b ldr r3, [r3, #0]
801461c: 891c ldrh r4, [r3, #8]
801461e: 6bbb ldr r3, [r7, #56] ; 0x38
8014620: 681b ldr r3, [r3, #0]
8014622: 68db ldr r3, [r3, #12]
8014624: 899b ldrh r3, [r3, #12]
8014626: b29b uxth r3, r3
8014628: 4618 mov r0, r3
801462a: f7fa fc31 bl 800ee90 <lwip_htons>
801462e: 4603 mov r3, r0
8014630: b2db uxtb r3, r3
8014632: f003 0303 and.w r3, r3, #3
8014636: 2b00 cmp r3, #0
8014638: d001 beq.n 801463e <tcp_receive+0xe6a>
801463a: 2301 movs r3, #1
801463c: e000 b.n 8014640 <tcp_receive+0xe6c>
801463e: 2300 movs r3, #0
8014640: 4423 add r3, r4
8014642: b29a uxth r2, r3
8014644: 4b2a ldr r3, [pc, #168] ; (80146f0 <tcp_receive+0xf1c>)
8014646: 801a strh r2, [r3, #0]
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
8014648: 4b29 ldr r3, [pc, #164] ; (80146f0 <tcp_receive+0xf1c>)
801464a: 881b ldrh r3, [r3, #0]
801464c: 461a mov r2, r3
801464e: 4b26 ldr r3, [pc, #152] ; (80146e8 <tcp_receive+0xf14>)
8014650: 681b ldr r3, [r3, #0]
8014652: 441a add r2, r3
8014654: 687b ldr r3, [r7, #4]
8014656: 6a5b ldr r3, [r3, #36] ; 0x24
8014658: 6879 ldr r1, [r7, #4]
801465a: 8d09 ldrh r1, [r1, #40] ; 0x28
801465c: 440b add r3, r1
801465e: 429a cmp r2, r3
8014660: d019 beq.n 8014696 <tcp_receive+0xec2>
8014662: 4b24 ldr r3, [pc, #144] ; (80146f4 <tcp_receive+0xf20>)
8014664: f240 62f9 movw r2, #1785 ; 0x6f9
8014668: 4923 ldr r1, [pc, #140] ; (80146f8 <tcp_receive+0xf24>)
801466a: 4824 ldr r0, [pc, #144] ; (80146fc <tcp_receive+0xf28>)
801466c: f006 fcda bl 801b024 <iprintf>
(seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
}
}
break;
8014670: e011 b.n 8014696 <tcp_receive+0xec2>
for (next = pcb->ooseq; next != NULL; next = next->next) {
8014672: 6bbb ldr r3, [r7, #56] ; 0x38
8014674: 681b ldr r3, [r3, #0]
8014676: 63bb str r3, [r7, #56] ; 0x38
8014678: 6bbb ldr r3, [r7, #56] ; 0x38
801467a: 2b00 cmp r3, #0
801467c: f47f aea4 bne.w 80143c8 <tcp_receive+0xbf4>
8014680: e00a b.n 8014698 <tcp_receive+0xec4>
break;
8014682: bf00 nop
8014684: e008 b.n 8014698 <tcp_receive+0xec4>
break;
8014686: bf00 nop
8014688: e006 b.n 8014698 <tcp_receive+0xec4>
break;
801468a: bf00 nop
801468c: e004 b.n 8014698 <tcp_receive+0xec4>
break;
801468e: bf00 nop
8014690: e002 b.n 8014698 <tcp_receive+0xec4>
break;
8014692: bf00 nop
8014694: e000 b.n 8014698 <tcp_receive+0xec4>
break;
8014696: bf00 nop
#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
#endif /* TCP_QUEUE_OOSEQ */
/* We send the ACK packet after we've (potentially) dealt with SACKs,
so they can be included in the acknowledgment. */
tcp_send_empty_ack(pcb);
8014698: 6878 ldr r0, [r7, #4]
801469a: f001 fa43 bl 8015b24 <tcp_send_empty_ack>
if (pcb->rcv_nxt == seqno) {
801469e: e003 b.n 80146a8 <tcp_receive+0xed4>
}
} else {
/* The incoming segment is not within the window. */
tcp_send_empty_ack(pcb);
80146a0: 6878 ldr r0, [r7, #4]
80146a2: f001 fa3f bl 8015b24 <tcp_send_empty_ack>
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
80146a6: e01a b.n 80146de <tcp_receive+0xf0a>
80146a8: e019 b.n 80146de <tcp_receive+0xf0a>
}
} else {
/* Segments with length 0 is taken care of here. Segments that
fall out of the window are ACKed. */
if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
80146aa: 4b0f ldr r3, [pc, #60] ; (80146e8 <tcp_receive+0xf14>)
80146ac: 681a ldr r2, [r3, #0]
80146ae: 687b ldr r3, [r7, #4]
80146b0: 6a5b ldr r3, [r3, #36] ; 0x24
80146b2: 1ad3 subs r3, r2, r3
80146b4: 2b00 cmp r3, #0
80146b6: db0a blt.n 80146ce <tcp_receive+0xefa>
80146b8: 4b0b ldr r3, [pc, #44] ; (80146e8 <tcp_receive+0xf14>)
80146ba: 681a ldr r2, [r3, #0]
80146bc: 687b ldr r3, [r7, #4]
80146be: 6a5b ldr r3, [r3, #36] ; 0x24
80146c0: 6879 ldr r1, [r7, #4]
80146c2: 8d09 ldrh r1, [r1, #40] ; 0x28
80146c4: 440b add r3, r1
80146c6: 1ad3 subs r3, r2, r3
80146c8: 3301 adds r3, #1
80146ca: 2b00 cmp r3, #0
80146cc: dd07 ble.n 80146de <tcp_receive+0xf0a>
tcp_ack_now(pcb);
80146ce: 687b ldr r3, [r7, #4]
80146d0: 8b5b ldrh r3, [r3, #26]
80146d2: f043 0302 orr.w r3, r3, #2
80146d6: b29a uxth r2, r3
80146d8: 687b ldr r3, [r7, #4]
80146da: 835a strh r2, [r3, #26]
}
}
}
80146dc: e7ff b.n 80146de <tcp_receive+0xf0a>
80146de: bf00 nop
80146e0: 3750 adds r7, #80 ; 0x50
80146e2: 46bd mov sp, r7
80146e4: bdb0 pop {r4, r5, r7, pc}
80146e6: bf00 nop
80146e8: 2000874c .word 0x2000874c
80146ec: 2000872c .word 0x2000872c
80146f0: 20008756 .word 0x20008756
80146f4: 0801d2c0 .word 0x0801d2c0
80146f8: 0801d668 .word 0x0801d668
80146fc: 0801d30c .word 0x0801d30c
08014700 <tcp_get_next_optbyte>:
static u8_t
tcp_get_next_optbyte(void)
{
8014700: b480 push {r7}
8014702: b083 sub sp, #12
8014704: af00 add r7, sp, #0
u16_t optidx = tcp_optidx++;
8014706: 4b15 ldr r3, [pc, #84] ; (801475c <tcp_get_next_optbyte+0x5c>)
8014708: 881b ldrh r3, [r3, #0]
801470a: 1c5a adds r2, r3, #1
801470c: b291 uxth r1, r2
801470e: 4a13 ldr r2, [pc, #76] ; (801475c <tcp_get_next_optbyte+0x5c>)
8014710: 8011 strh r1, [r2, #0]
8014712: 80fb strh r3, [r7, #6]
if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
8014714: 4b12 ldr r3, [pc, #72] ; (8014760 <tcp_get_next_optbyte+0x60>)
8014716: 681b ldr r3, [r3, #0]
8014718: 2b00 cmp r3, #0
801471a: d004 beq.n 8014726 <tcp_get_next_optbyte+0x26>
801471c: 4b11 ldr r3, [pc, #68] ; (8014764 <tcp_get_next_optbyte+0x64>)
801471e: 881b ldrh r3, [r3, #0]
8014720: 88fa ldrh r2, [r7, #6]
8014722: 429a cmp r2, r3
8014724: d208 bcs.n 8014738 <tcp_get_next_optbyte+0x38>
u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
8014726: 4b10 ldr r3, [pc, #64] ; (8014768 <tcp_get_next_optbyte+0x68>)
8014728: 681b ldr r3, [r3, #0]
801472a: 3314 adds r3, #20
801472c: 603b str r3, [r7, #0]
return opts[optidx];
801472e: 88fb ldrh r3, [r7, #6]
8014730: 683a ldr r2, [r7, #0]
8014732: 4413 add r3, r2
8014734: 781b ldrb r3, [r3, #0]
8014736: e00b b.n 8014750 <tcp_get_next_optbyte+0x50>
} else {
u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
8014738: 88fb ldrh r3, [r7, #6]
801473a: b2da uxtb r2, r3
801473c: 4b09 ldr r3, [pc, #36] ; (8014764 <tcp_get_next_optbyte+0x64>)
801473e: 881b ldrh r3, [r3, #0]
8014740: b2db uxtb r3, r3
8014742: 1ad3 subs r3, r2, r3
8014744: 717b strb r3, [r7, #5]
return tcphdr_opt2[idx];
8014746: 4b06 ldr r3, [pc, #24] ; (8014760 <tcp_get_next_optbyte+0x60>)
8014748: 681a ldr r2, [r3, #0]
801474a: 797b ldrb r3, [r7, #5]
801474c: 4413 add r3, r2
801474e: 781b ldrb r3, [r3, #0]
}
}
8014750: 4618 mov r0, r3
8014752: 370c adds r7, #12
8014754: 46bd mov sp, r7
8014756: f85d 7b04 ldr.w r7, [sp], #4
801475a: 4770 bx lr
801475c: 20008748 .word 0x20008748
8014760: 20008744 .word 0x20008744
8014764: 20008742 .word 0x20008742
8014768: 2000873c .word 0x2000873c
0801476c <tcp_parseopt>:
*
* @param pcb the tcp_pcb for which a segment arrived
*/
static void
tcp_parseopt(struct tcp_pcb *pcb)
{
801476c: b580 push {r7, lr}
801476e: b084 sub sp, #16
8014770: af00 add r7, sp, #0
8014772: 6078 str r0, [r7, #4]
u16_t mss;
#if LWIP_TCP_TIMESTAMPS
u32_t tsval;
#endif
LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
8014774: 687b ldr r3, [r7, #4]
8014776: 2b00 cmp r3, #0
8014778: d106 bne.n 8014788 <tcp_parseopt+0x1c>
801477a: 4b31 ldr r3, [pc, #196] ; (8014840 <tcp_parseopt+0xd4>)
801477c: f240 727d movw r2, #1917 ; 0x77d
8014780: 4930 ldr r1, [pc, #192] ; (8014844 <tcp_parseopt+0xd8>)
8014782: 4831 ldr r0, [pc, #196] ; (8014848 <tcp_parseopt+0xdc>)
8014784: f006 fc4e bl 801b024 <iprintf>
/* Parse the TCP MSS option, if present. */
if (tcphdr_optlen != 0) {
8014788: 4b30 ldr r3, [pc, #192] ; (801484c <tcp_parseopt+0xe0>)
801478a: 881b ldrh r3, [r3, #0]
801478c: 2b00 cmp r3, #0
801478e: d053 beq.n 8014838 <tcp_parseopt+0xcc>
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
8014790: 4b2f ldr r3, [pc, #188] ; (8014850 <tcp_parseopt+0xe4>)
8014792: 2200 movs r2, #0
8014794: 801a strh r2, [r3, #0]
8014796: e043 b.n 8014820 <tcp_parseopt+0xb4>
u8_t opt = tcp_get_next_optbyte();
8014798: f7ff ffb2 bl 8014700 <tcp_get_next_optbyte>
801479c: 4603 mov r3, r0
801479e: 73fb strb r3, [r7, #15]
switch (opt) {
80147a0: 7bfb ldrb r3, [r7, #15]
80147a2: 2b01 cmp r3, #1
80147a4: d03c beq.n 8014820 <tcp_parseopt+0xb4>
80147a6: 2b02 cmp r3, #2
80147a8: d002 beq.n 80147b0 <tcp_parseopt+0x44>
80147aa: 2b00 cmp r3, #0
80147ac: d03f beq.n 801482e <tcp_parseopt+0xc2>
80147ae: e026 b.n 80147fe <tcp_parseopt+0x92>
/* NOP option. */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
break;
case LWIP_TCP_OPT_MSS:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
80147b0: f7ff ffa6 bl 8014700 <tcp_get_next_optbyte>
80147b4: 4603 mov r3, r0
80147b6: 2b04 cmp r3, #4
80147b8: d13b bne.n 8014832 <tcp_parseopt+0xc6>
80147ba: 4b25 ldr r3, [pc, #148] ; (8014850 <tcp_parseopt+0xe4>)
80147bc: 881b ldrh r3, [r3, #0]
80147be: 3302 adds r3, #2
80147c0: 4a22 ldr r2, [pc, #136] ; (801484c <tcp_parseopt+0xe0>)
80147c2: 8812 ldrh r2, [r2, #0]
80147c4: 4293 cmp r3, r2
80147c6: dc34 bgt.n 8014832 <tcp_parseopt+0xc6>
/* Bad length */
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
return;
}
/* An MSS option with the right option length. */
mss = (u16_t)(tcp_get_next_optbyte() << 8);
80147c8: f7ff ff9a bl 8014700 <tcp_get_next_optbyte>
80147cc: 4603 mov r3, r0
80147ce: b29b uxth r3, r3
80147d0: 021b lsls r3, r3, #8
80147d2: 81bb strh r3, [r7, #12]
mss |= tcp_get_next_optbyte();
80147d4: f7ff ff94 bl 8014700 <tcp_get_next_optbyte>
80147d8: 4603 mov r3, r0
80147da: b29a uxth r2, r3
80147dc: 89bb ldrh r3, [r7, #12]
80147de: 4313 orrs r3, r2
80147e0: 81bb strh r3, [r7, #12]
/* Limit the mss to the configured TCP_MSS and prevent division by zero */
pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
80147e2: 89bb ldrh r3, [r7, #12]
80147e4: f5b3 7f06 cmp.w r3, #536 ; 0x218
80147e8: d804 bhi.n 80147f4 <tcp_parseopt+0x88>
80147ea: 89bb ldrh r3, [r7, #12]
80147ec: 2b00 cmp r3, #0
80147ee: d001 beq.n 80147f4 <tcp_parseopt+0x88>
80147f0: 89ba ldrh r2, [r7, #12]
80147f2: e001 b.n 80147f8 <tcp_parseopt+0x8c>
80147f4: f44f 7206 mov.w r2, #536 ; 0x218
80147f8: 687b ldr r3, [r7, #4]
80147fa: 865a strh r2, [r3, #50] ; 0x32
break;
80147fc: e010 b.n 8014820 <tcp_parseopt+0xb4>
}
break;
#endif /* LWIP_TCP_SACK_OUT */
default:
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
data = tcp_get_next_optbyte();
80147fe: f7ff ff7f bl 8014700 <tcp_get_next_optbyte>
8014802: 4603 mov r3, r0
8014804: 72fb strb r3, [r7, #11]
if (data < 2) {
8014806: 7afb ldrb r3, [r7, #11]
8014808: 2b01 cmp r3, #1
801480a: d914 bls.n 8014836 <tcp_parseopt+0xca>
and we don't process them further. */
return;
}
/* All other options have a length field, so that we easily
can skip past them. */
tcp_optidx += data - 2;
801480c: 7afb ldrb r3, [r7, #11]
801480e: b29a uxth r2, r3
8014810: 4b0f ldr r3, [pc, #60] ; (8014850 <tcp_parseopt+0xe4>)
8014812: 881b ldrh r3, [r3, #0]
8014814: 4413 add r3, r2
8014816: b29b uxth r3, r3
8014818: 3b02 subs r3, #2
801481a: b29a uxth r2, r3
801481c: 4b0c ldr r3, [pc, #48] ; (8014850 <tcp_parseopt+0xe4>)
801481e: 801a strh r2, [r3, #0]
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
8014820: 4b0b ldr r3, [pc, #44] ; (8014850 <tcp_parseopt+0xe4>)
8014822: 881a ldrh r2, [r3, #0]
8014824: 4b09 ldr r3, [pc, #36] ; (801484c <tcp_parseopt+0xe0>)
8014826: 881b ldrh r3, [r3, #0]
8014828: 429a cmp r2, r3
801482a: d3b5 bcc.n 8014798 <tcp_parseopt+0x2c>
801482c: e004 b.n 8014838 <tcp_parseopt+0xcc>
return;
801482e: bf00 nop
8014830: e002 b.n 8014838 <tcp_parseopt+0xcc>
return;
8014832: bf00 nop
8014834: e000 b.n 8014838 <tcp_parseopt+0xcc>
return;
8014836: bf00 nop
}
}
}
}
8014838: 3710 adds r7, #16
801483a: 46bd mov sp, r7
801483c: bd80 pop {r7, pc}
801483e: bf00 nop
8014840: 0801d2c0 .word 0x0801d2c0
8014844: 0801d724 .word 0x0801d724
8014848: 0801d30c .word 0x0801d30c
801484c: 20008740 .word 0x20008740
8014850: 20008748 .word 0x20008748
08014854 <tcp_trigger_input_pcb_close>:
void
tcp_trigger_input_pcb_close(void)
{
8014854: b480 push {r7}
8014856: af00 add r7, sp, #0
recv_flags |= TF_CLOSED;
8014858: 4b05 ldr r3, [pc, #20] ; (8014870 <tcp_trigger_input_pcb_close+0x1c>)
801485a: 781b ldrb r3, [r3, #0]
801485c: f043 0310 orr.w r3, r3, #16
8014860: b2da uxtb r2, r3
8014862: 4b03 ldr r3, [pc, #12] ; (8014870 <tcp_trigger_input_pcb_close+0x1c>)
8014864: 701a strb r2, [r3, #0]
}
8014866: bf00 nop
8014868: 46bd mov sp, r7
801486a: f85d 7b04 ldr.w r7, [sp], #4
801486e: 4770 bx lr
8014870: 20008759 .word 0x20008759
08014874 <tcp_route>:
static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
static struct netif *
tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
{
8014874: b580 push {r7, lr}
8014876: b084 sub sp, #16
8014878: af00 add r7, sp, #0
801487a: 60f8 str r0, [r7, #12]
801487c: 60b9 str r1, [r7, #8]
801487e: 607a str r2, [r7, #4]
LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
8014880: 68fb ldr r3, [r7, #12]
8014882: 2b00 cmp r3, #0
8014884: d00a beq.n 801489c <tcp_route+0x28>
8014886: 68fb ldr r3, [r7, #12]
8014888: 7a1b ldrb r3, [r3, #8]
801488a: 2b00 cmp r3, #0
801488c: d006 beq.n 801489c <tcp_route+0x28>
return netif_get_by_index(pcb->netif_idx);
801488e: 68fb ldr r3, [r7, #12]
8014890: 7a1b ldrb r3, [r3, #8]
8014892: 4618 mov r0, r3
8014894: f7fb fb26 bl 800fee4 <netif_get_by_index>
8014898: 4603 mov r3, r0
801489a: e003 b.n 80148a4 <tcp_route+0x30>
} else {
return ip_route(src, dst);
801489c: 6878 ldr r0, [r7, #4]
801489e: f005 f867 bl 8019970 <ip4_route>
80148a2: 4603 mov r3, r0
}
}
80148a4: 4618 mov r0, r3
80148a6: 3710 adds r7, #16
80148a8: 46bd mov sp, r7
80148aa: bd80 pop {r7, pc}
080148ac <tcp_create_segment>:
* The TCP header is filled in except ackno and wnd.
* p is freed on failure.
*/
static struct tcp_seg *
tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
{
80148ac: b590 push {r4, r7, lr}
80148ae: b087 sub sp, #28
80148b0: af00 add r7, sp, #0
80148b2: 60f8 str r0, [r7, #12]
80148b4: 60b9 str r1, [r7, #8]
80148b6: 603b str r3, [r7, #0]
80148b8: 4613 mov r3, r2
80148ba: 71fb strb r3, [r7, #7]
struct tcp_seg *seg;
u8_t optlen;
LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
80148bc: 68fb ldr r3, [r7, #12]
80148be: 2b00 cmp r3, #0
80148c0: d105 bne.n 80148ce <tcp_create_segment+0x22>
80148c2: 4b44 ldr r3, [pc, #272] ; (80149d4 <tcp_create_segment+0x128>)
80148c4: 22a3 movs r2, #163 ; 0xa3
80148c6: 4944 ldr r1, [pc, #272] ; (80149d8 <tcp_create_segment+0x12c>)
80148c8: 4844 ldr r0, [pc, #272] ; (80149dc <tcp_create_segment+0x130>)
80148ca: f006 fbab bl 801b024 <iprintf>
LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
80148ce: 68bb ldr r3, [r7, #8]
80148d0: 2b00 cmp r3, #0
80148d2: d105 bne.n 80148e0 <tcp_create_segment+0x34>
80148d4: 4b3f ldr r3, [pc, #252] ; (80149d4 <tcp_create_segment+0x128>)
80148d6: 22a4 movs r2, #164 ; 0xa4
80148d8: 4941 ldr r1, [pc, #260] ; (80149e0 <tcp_create_segment+0x134>)
80148da: 4840 ldr r0, [pc, #256] ; (80149dc <tcp_create_segment+0x130>)
80148dc: f006 fba2 bl 801b024 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
80148e0: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
80148e4: 009b lsls r3, r3, #2
80148e6: b2db uxtb r3, r3
80148e8: f003 0304 and.w r3, r3, #4
80148ec: 75fb strb r3, [r7, #23]
if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
80148ee: 2003 movs r0, #3
80148f0: f7fa ff84 bl 800f7fc <memp_malloc>
80148f4: 6138 str r0, [r7, #16]
80148f6: 693b ldr r3, [r7, #16]
80148f8: 2b00 cmp r3, #0
80148fa: d104 bne.n 8014906 <tcp_create_segment+0x5a>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
pbuf_free(p);
80148fc: 68b8 ldr r0, [r7, #8]
80148fe: f7fb fe7b bl 80105f8 <pbuf_free>
return NULL;
8014902: 2300 movs r3, #0
8014904: e061 b.n 80149ca <tcp_create_segment+0x11e>
}
seg->flags = optflags;
8014906: 693b ldr r3, [r7, #16]
8014908: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
801490c: 729a strb r2, [r3, #10]
seg->next = NULL;
801490e: 693b ldr r3, [r7, #16]
8014910: 2200 movs r2, #0
8014912: 601a str r2, [r3, #0]
seg->p = p;
8014914: 693b ldr r3, [r7, #16]
8014916: 68ba ldr r2, [r7, #8]
8014918: 605a str r2, [r3, #4]
LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
801491a: 68bb ldr r3, [r7, #8]
801491c: 891a ldrh r2, [r3, #8]
801491e: 7dfb ldrb r3, [r7, #23]
8014920: b29b uxth r3, r3
8014922: 429a cmp r2, r3
8014924: d205 bcs.n 8014932 <tcp_create_segment+0x86>
8014926: 4b2b ldr r3, [pc, #172] ; (80149d4 <tcp_create_segment+0x128>)
8014928: 22b0 movs r2, #176 ; 0xb0
801492a: 492e ldr r1, [pc, #184] ; (80149e4 <tcp_create_segment+0x138>)
801492c: 482b ldr r0, [pc, #172] ; (80149dc <tcp_create_segment+0x130>)
801492e: f006 fb79 bl 801b024 <iprintf>
seg->len = p->tot_len - optlen;
8014932: 68bb ldr r3, [r7, #8]
8014934: 891a ldrh r2, [r3, #8]
8014936: 7dfb ldrb r3, [r7, #23]
8014938: b29b uxth r3, r3
801493a: 1ad3 subs r3, r2, r3
801493c: b29a uxth r2, r3
801493e: 693b ldr r3, [r7, #16]
8014940: 811a strh r2, [r3, #8]
LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
(optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
#endif /* TCP_CHECKSUM_ON_COPY */
/* build TCP header */
if (pbuf_add_header(p, TCP_HLEN)) {
8014942: 2114 movs r1, #20
8014944: 68b8 ldr r0, [r7, #8]
8014946: f7fb fdc1 bl 80104cc <pbuf_add_header>
801494a: 4603 mov r3, r0
801494c: 2b00 cmp r3, #0
801494e: d004 beq.n 801495a <tcp_create_segment+0xae>
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
TCP_STATS_INC(tcp.err);
tcp_seg_free(seg);
8014950: 6938 ldr r0, [r7, #16]
8014952: f7fd f8d5 bl 8011b00 <tcp_seg_free>
return NULL;
8014956: 2300 movs r3, #0
8014958: e037 b.n 80149ca <tcp_create_segment+0x11e>
}
seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
801495a: 693b ldr r3, [r7, #16]
801495c: 685b ldr r3, [r3, #4]
801495e: 685a ldr r2, [r3, #4]
8014960: 693b ldr r3, [r7, #16]
8014962: 60da str r2, [r3, #12]
seg->tcphdr->src = lwip_htons(pcb->local_port);
8014964: 68fb ldr r3, [r7, #12]
8014966: 8ada ldrh r2, [r3, #22]
8014968: 693b ldr r3, [r7, #16]
801496a: 68dc ldr r4, [r3, #12]
801496c: 4610 mov r0, r2
801496e: f7fa fa8f bl 800ee90 <lwip_htons>
8014972: 4603 mov r3, r0
8014974: 8023 strh r3, [r4, #0]
seg->tcphdr->dest = lwip_htons(pcb->remote_port);
8014976: 68fb ldr r3, [r7, #12]
8014978: 8b1a ldrh r2, [r3, #24]
801497a: 693b ldr r3, [r7, #16]
801497c: 68dc ldr r4, [r3, #12]
801497e: 4610 mov r0, r2
8014980: f7fa fa86 bl 800ee90 <lwip_htons>
8014984: 4603 mov r3, r0
8014986: 8063 strh r3, [r4, #2]
seg->tcphdr->seqno = lwip_htonl(seqno);
8014988: 693b ldr r3, [r7, #16]
801498a: 68dc ldr r4, [r3, #12]
801498c: 6838 ldr r0, [r7, #0]
801498e: f7fa fa94 bl 800eeba <lwip_htonl>
8014992: 4603 mov r3, r0
8014994: 6063 str r3, [r4, #4]
/* ackno is set in tcp_output */
TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
8014996: 7dfb ldrb r3, [r7, #23]
8014998: 089b lsrs r3, r3, #2
801499a: b2db uxtb r3, r3
801499c: b29b uxth r3, r3
801499e: 3305 adds r3, #5
80149a0: b29b uxth r3, r3
80149a2: 031b lsls r3, r3, #12
80149a4: b29a uxth r2, r3
80149a6: 79fb ldrb r3, [r7, #7]
80149a8: b29b uxth r3, r3
80149aa: 4313 orrs r3, r2
80149ac: b29a uxth r2, r3
80149ae: 693b ldr r3, [r7, #16]
80149b0: 68dc ldr r4, [r3, #12]
80149b2: 4610 mov r0, r2
80149b4: f7fa fa6c bl 800ee90 <lwip_htons>
80149b8: 4603 mov r3, r0
80149ba: 81a3 strh r3, [r4, #12]
/* wnd and chksum are set in tcp_output */
seg->tcphdr->urgp = 0;
80149bc: 693b ldr r3, [r7, #16]
80149be: 68db ldr r3, [r3, #12]
80149c0: 2200 movs r2, #0
80149c2: 749a strb r2, [r3, #18]
80149c4: 2200 movs r2, #0
80149c6: 74da strb r2, [r3, #19]
return seg;
80149c8: 693b ldr r3, [r7, #16]
}
80149ca: 4618 mov r0, r3
80149cc: 371c adds r7, #28
80149ce: 46bd mov sp, r7
80149d0: bd90 pop {r4, r7, pc}
80149d2: bf00 nop
80149d4: 0801d740 .word 0x0801d740
80149d8: 0801d774 .word 0x0801d774
80149dc: 0801d794 .word 0x0801d794
80149e0: 0801d7bc .word 0x0801d7bc
80149e4: 0801d7e0 .word 0x0801d7e0
080149e8 <tcp_split_unsent_seg>:
* @param pcb the tcp_pcb for which to split the unsent head
* @param split the amount of payload to remain in the head
*/
err_t
tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
{
80149e8: b590 push {r4, r7, lr}
80149ea: b08b sub sp, #44 ; 0x2c
80149ec: af02 add r7, sp, #8
80149ee: 6078 str r0, [r7, #4]
80149f0: 460b mov r3, r1
80149f2: 807b strh r3, [r7, #2]
struct tcp_seg *seg = NULL, *useg = NULL;
80149f4: 2300 movs r3, #0
80149f6: 61fb str r3, [r7, #28]
80149f8: 2300 movs r3, #0
80149fa: 617b str r3, [r7, #20]
struct pbuf *p = NULL;
80149fc: 2300 movs r3, #0
80149fe: 613b str r3, [r7, #16]
u16_t chksum = 0;
u8_t chksum_swapped = 0;
struct pbuf *q;
#endif /* TCP_CHECKSUM_ON_COPY */
LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
8014a00: 687b ldr r3, [r7, #4]
8014a02: 2b00 cmp r3, #0
8014a04: d106 bne.n 8014a14 <tcp_split_unsent_seg+0x2c>
8014a06: 4b95 ldr r3, [pc, #596] ; (8014c5c <tcp_split_unsent_seg+0x274>)
8014a08: f240 324b movw r2, #843 ; 0x34b
8014a0c: 4994 ldr r1, [pc, #592] ; (8014c60 <tcp_split_unsent_seg+0x278>)
8014a0e: 4895 ldr r0, [pc, #596] ; (8014c64 <tcp_split_unsent_seg+0x27c>)
8014a10: f006 fb08 bl 801b024 <iprintf>
useg = pcb->unsent;
8014a14: 687b ldr r3, [r7, #4]
8014a16: 6edb ldr r3, [r3, #108] ; 0x6c
8014a18: 617b str r3, [r7, #20]
if (useg == NULL) {
8014a1a: 697b ldr r3, [r7, #20]
8014a1c: 2b00 cmp r3, #0
8014a1e: d102 bne.n 8014a26 <tcp_split_unsent_seg+0x3e>
return ERR_MEM;
8014a20: f04f 33ff mov.w r3, #4294967295
8014a24: e116 b.n 8014c54 <tcp_split_unsent_seg+0x26c>
}
if (split == 0) {
8014a26: 887b ldrh r3, [r7, #2]
8014a28: 2b00 cmp r3, #0
8014a2a: d109 bne.n 8014a40 <tcp_split_unsent_seg+0x58>
LWIP_ASSERT("Can't split segment into length 0", 0);
8014a2c: 4b8b ldr r3, [pc, #556] ; (8014c5c <tcp_split_unsent_seg+0x274>)
8014a2e: f240 3253 movw r2, #851 ; 0x353
8014a32: 498d ldr r1, [pc, #564] ; (8014c68 <tcp_split_unsent_seg+0x280>)
8014a34: 488b ldr r0, [pc, #556] ; (8014c64 <tcp_split_unsent_seg+0x27c>)
8014a36: f006 faf5 bl 801b024 <iprintf>
return ERR_VAL;
8014a3a: f06f 0305 mvn.w r3, #5
8014a3e: e109 b.n 8014c54 <tcp_split_unsent_seg+0x26c>
}
if (useg->len <= split) {
8014a40: 697b ldr r3, [r7, #20]
8014a42: 891b ldrh r3, [r3, #8]
8014a44: 887a ldrh r2, [r7, #2]
8014a46: 429a cmp r2, r3
8014a48: d301 bcc.n 8014a4e <tcp_split_unsent_seg+0x66>
return ERR_OK;
8014a4a: 2300 movs r3, #0
8014a4c: e102 b.n 8014c54 <tcp_split_unsent_seg+0x26c>
}
LWIP_ASSERT("split <= mss", split <= pcb->mss);
8014a4e: 687b ldr r3, [r7, #4]
8014a50: 8e5b ldrh r3, [r3, #50] ; 0x32
8014a52: 887a ldrh r2, [r7, #2]
8014a54: 429a cmp r2, r3
8014a56: d906 bls.n 8014a66 <tcp_split_unsent_seg+0x7e>
8014a58: 4b80 ldr r3, [pc, #512] ; (8014c5c <tcp_split_unsent_seg+0x274>)
8014a5a: f240 325b movw r2, #859 ; 0x35b
8014a5e: 4983 ldr r1, [pc, #524] ; (8014c6c <tcp_split_unsent_seg+0x284>)
8014a60: 4880 ldr r0, [pc, #512] ; (8014c64 <tcp_split_unsent_seg+0x27c>)
8014a62: f006 fadf bl 801b024 <iprintf>
LWIP_ASSERT("useg->len > 0", useg->len > 0);
8014a66: 697b ldr r3, [r7, #20]
8014a68: 891b ldrh r3, [r3, #8]
8014a6a: 2b00 cmp r3, #0
8014a6c: d106 bne.n 8014a7c <tcp_split_unsent_seg+0x94>
8014a6e: 4b7b ldr r3, [pc, #492] ; (8014c5c <tcp_split_unsent_seg+0x274>)
8014a70: f44f 7257 mov.w r2, #860 ; 0x35c
8014a74: 497e ldr r1, [pc, #504] ; (8014c70 <tcp_split_unsent_seg+0x288>)
8014a76: 487b ldr r0, [pc, #492] ; (8014c64 <tcp_split_unsent_seg+0x27c>)
8014a78: f006 fad4 bl 801b024 <iprintf>
* to split this packet so we may actually exceed the max value by
* one!
*/
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
optflags = useg->flags;
8014a7c: 697b ldr r3, [r7, #20]
8014a7e: 7a9b ldrb r3, [r3, #10]
8014a80: 73fb strb r3, [r7, #15]
#if TCP_CHECKSUM_ON_COPY
/* Remove since checksum is not stored until after tcp_create_segment() */
optflags &= ~TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
optlen = LWIP_TCP_OPT_LENGTH(optflags);
8014a82: 7bfb ldrb r3, [r7, #15]
8014a84: 009b lsls r3, r3, #2
8014a86: b2db uxtb r3, r3
8014a88: f003 0304 and.w r3, r3, #4
8014a8c: 73bb strb r3, [r7, #14]
remainder = useg->len - split;
8014a8e: 697b ldr r3, [r7, #20]
8014a90: 891a ldrh r2, [r3, #8]
8014a92: 887b ldrh r3, [r7, #2]
8014a94: 1ad3 subs r3, r2, r3
8014a96: 81bb strh r3, [r7, #12]
/* Create new pbuf for the remainder of the split */
p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
8014a98: 7bbb ldrb r3, [r7, #14]
8014a9a: b29a uxth r2, r3
8014a9c: 89bb ldrh r3, [r7, #12]
8014a9e: 4413 add r3, r2
8014aa0: b29b uxth r3, r3
8014aa2: f44f 7220 mov.w r2, #640 ; 0x280
8014aa6: 4619 mov r1, r3
8014aa8: 2036 movs r0, #54 ; 0x36
8014aaa: f7fb fac5 bl 8010038 <pbuf_alloc>
8014aae: 6138 str r0, [r7, #16]
if (p == NULL) {
8014ab0: 693b ldr r3, [r7, #16]
8014ab2: 2b00 cmp r3, #0
8014ab4: f000 80b7 beq.w 8014c26 <tcp_split_unsent_seg+0x23e>
("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
goto memerr;
}
/* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
offset = useg->p->tot_len - useg->len + split;
8014ab8: 697b ldr r3, [r7, #20]
8014aba: 685b ldr r3, [r3, #4]
8014abc: 891a ldrh r2, [r3, #8]
8014abe: 697b ldr r3, [r7, #20]
8014ac0: 891b ldrh r3, [r3, #8]
8014ac2: 1ad3 subs r3, r2, r3
8014ac4: b29a uxth r2, r3
8014ac6: 887b ldrh r3, [r7, #2]
8014ac8: 4413 add r3, r2
8014aca: 817b strh r3, [r7, #10]
/* Copy remainder into new pbuf, headers and options will not be filled out */
if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
8014acc: 697b ldr r3, [r7, #20]
8014ace: 6858 ldr r0, [r3, #4]
8014ad0: 693b ldr r3, [r7, #16]
8014ad2: 685a ldr r2, [r3, #4]
8014ad4: 7bbb ldrb r3, [r7, #14]
8014ad6: 18d1 adds r1, r2, r3
8014ad8: 897b ldrh r3, [r7, #10]
8014ada: 89ba ldrh r2, [r7, #12]
8014adc: f7fb ff92 bl 8010a04 <pbuf_copy_partial>
8014ae0: 4603 mov r3, r0
8014ae2: 461a mov r2, r3
8014ae4: 89bb ldrh r3, [r7, #12]
8014ae6: 4293 cmp r3, r2
8014ae8: f040 809f bne.w 8014c2a <tcp_split_unsent_seg+0x242>
#endif /* TCP_CHECKSUM_ON_COPY */
/* Options are created when calling tcp_output() */
/* Migrate flags from original segment */
split_flags = TCPH_FLAGS(useg->tcphdr);
8014aec: 697b ldr r3, [r7, #20]
8014aee: 68db ldr r3, [r3, #12]
8014af0: 899b ldrh r3, [r3, #12]
8014af2: b29b uxth r3, r3
8014af4: 4618 mov r0, r3
8014af6: f7fa f9cb bl 800ee90 <lwip_htons>
8014afa: 4603 mov r3, r0
8014afc: b2db uxtb r3, r3
8014afe: f003 033f and.w r3, r3, #63 ; 0x3f
8014b02: 76fb strb r3, [r7, #27]
remainder_flags = 0; /* ACK added in tcp_output() */
8014b04: 2300 movs r3, #0
8014b06: 76bb strb r3, [r7, #26]
if (split_flags & TCP_PSH) {
8014b08: 7efb ldrb r3, [r7, #27]
8014b0a: f003 0308 and.w r3, r3, #8
8014b0e: 2b00 cmp r3, #0
8014b10: d007 beq.n 8014b22 <tcp_split_unsent_seg+0x13a>
split_flags &= ~TCP_PSH;
8014b12: 7efb ldrb r3, [r7, #27]
8014b14: f023 0308 bic.w r3, r3, #8
8014b18: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_PSH;
8014b1a: 7ebb ldrb r3, [r7, #26]
8014b1c: f043 0308 orr.w r3, r3, #8
8014b20: 76bb strb r3, [r7, #26]
}
if (split_flags & TCP_FIN) {
8014b22: 7efb ldrb r3, [r7, #27]
8014b24: f003 0301 and.w r3, r3, #1
8014b28: 2b00 cmp r3, #0
8014b2a: d007 beq.n 8014b3c <tcp_split_unsent_seg+0x154>
split_flags &= ~TCP_FIN;
8014b2c: 7efb ldrb r3, [r7, #27]
8014b2e: f023 0301 bic.w r3, r3, #1
8014b32: 76fb strb r3, [r7, #27]
remainder_flags |= TCP_FIN;
8014b34: 7ebb ldrb r3, [r7, #26]
8014b36: f043 0301 orr.w r3, r3, #1
8014b3a: 76bb strb r3, [r7, #26]
}
/* SYN should be left on split, RST should not be present with data */
seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
8014b3c: 697b ldr r3, [r7, #20]
8014b3e: 68db ldr r3, [r3, #12]
8014b40: 685b ldr r3, [r3, #4]
8014b42: 4618 mov r0, r3
8014b44: f7fa f9b9 bl 800eeba <lwip_htonl>
8014b48: 4602 mov r2, r0
8014b4a: 887b ldrh r3, [r7, #2]
8014b4c: 18d1 adds r1, r2, r3
8014b4e: 7eba ldrb r2, [r7, #26]
8014b50: 7bfb ldrb r3, [r7, #15]
8014b52: 9300 str r3, [sp, #0]
8014b54: 460b mov r3, r1
8014b56: 6939 ldr r1, [r7, #16]
8014b58: 6878 ldr r0, [r7, #4]
8014b5a: f7ff fea7 bl 80148ac <tcp_create_segment>
8014b5e: 61f8 str r0, [r7, #28]
if (seg == NULL) {
8014b60: 69fb ldr r3, [r7, #28]
8014b62: 2b00 cmp r3, #0
8014b64: d063 beq.n 8014c2e <tcp_split_unsent_seg+0x246>
seg->chksum_swapped = chksum_swapped;
seg->flags |= TF_SEG_DATA_CHECKSUMMED;
#endif /* TCP_CHECKSUM_ON_COPY */
/* Remove this segment from the queue since trimming it may free pbufs */
pcb->snd_queuelen -= pbuf_clen(useg->p);
8014b66: 697b ldr r3, [r7, #20]
8014b68: 685b ldr r3, [r3, #4]
8014b6a: 4618 mov r0, r3
8014b6c: f7fb fdd2 bl 8010714 <pbuf_clen>
8014b70: 4603 mov r3, r0
8014b72: 461a mov r2, r3
8014b74: 687b ldr r3, [r7, #4]
8014b76: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014b7a: 1a9b subs r3, r3, r2
8014b7c: b29a uxth r2, r3
8014b7e: 687b ldr r3, [r7, #4]
8014b80: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Trim the original pbuf into our split size. At this point our remainder segment must be setup
successfully because we are modifying the original segment */
pbuf_realloc(useg->p, useg->p->tot_len - remainder);
8014b84: 697b ldr r3, [r7, #20]
8014b86: 6858 ldr r0, [r3, #4]
8014b88: 697b ldr r3, [r7, #20]
8014b8a: 685b ldr r3, [r3, #4]
8014b8c: 891a ldrh r2, [r3, #8]
8014b8e: 89bb ldrh r3, [r7, #12]
8014b90: 1ad3 subs r3, r2, r3
8014b92: b29b uxth r3, r3
8014b94: 4619 mov r1, r3
8014b96: f7fb fba9 bl 80102ec <pbuf_realloc>
useg->len -= remainder;
8014b9a: 697b ldr r3, [r7, #20]
8014b9c: 891a ldrh r2, [r3, #8]
8014b9e: 89bb ldrh r3, [r7, #12]
8014ba0: 1ad3 subs r3, r2, r3
8014ba2: b29a uxth r2, r3
8014ba4: 697b ldr r3, [r7, #20]
8014ba6: 811a strh r2, [r3, #8]
TCPH_SET_FLAG(useg->tcphdr, split_flags);
8014ba8: 697b ldr r3, [r7, #20]
8014baa: 68db ldr r3, [r3, #12]
8014bac: 899b ldrh r3, [r3, #12]
8014bae: b29c uxth r4, r3
8014bb0: 7efb ldrb r3, [r7, #27]
8014bb2: b29b uxth r3, r3
8014bb4: 4618 mov r0, r3
8014bb6: f7fa f96b bl 800ee90 <lwip_htons>
8014bba: 4603 mov r3, r0
8014bbc: 461a mov r2, r3
8014bbe: 697b ldr r3, [r7, #20]
8014bc0: 68db ldr r3, [r3, #12]
8014bc2: 4322 orrs r2, r4
8014bc4: b292 uxth r2, r2
8014bc6: 819a strh r2, [r3, #12]
/* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
useg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
/* Add back to the queue with new trimmed pbuf */
pcb->snd_queuelen += pbuf_clen(useg->p);
8014bc8: 697b ldr r3, [r7, #20]
8014bca: 685b ldr r3, [r3, #4]
8014bcc: 4618 mov r0, r3
8014bce: f7fb fda1 bl 8010714 <pbuf_clen>
8014bd2: 4603 mov r3, r0
8014bd4: 461a mov r2, r3
8014bd6: 687b ldr r3, [r7, #4]
8014bd8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bdc: 4413 add r3, r2
8014bde: b29a uxth r2, r3
8014be0: 687b ldr r3, [r7, #4]
8014be2: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
#endif /* TCP_CHECKSUM_ON_COPY */
/* Update number of segments on the queues. Note that length now may
* exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
* because the total amount of data is constant when packet is split */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014be6: 69fb ldr r3, [r7, #28]
8014be8: 685b ldr r3, [r3, #4]
8014bea: 4618 mov r0, r3
8014bec: f7fb fd92 bl 8010714 <pbuf_clen>
8014bf0: 4603 mov r3, r0
8014bf2: 461a mov r2, r3
8014bf4: 687b ldr r3, [r7, #4]
8014bf6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014bfa: 4413 add r3, r2
8014bfc: b29a uxth r2, r3
8014bfe: 687b ldr r3, [r7, #4]
8014c00: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
/* Finally insert remainder into queue after split (which stays head) */
seg->next = useg->next;
8014c04: 697b ldr r3, [r7, #20]
8014c06: 681a ldr r2, [r3, #0]
8014c08: 69fb ldr r3, [r7, #28]
8014c0a: 601a str r2, [r3, #0]
useg->next = seg;
8014c0c: 697b ldr r3, [r7, #20]
8014c0e: 69fa ldr r2, [r7, #28]
8014c10: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
/* If remainder is last segment on the unsent, ensure we clear the oversize amount
* because the remainder is always sized to the exact remaining amount */
if (seg->next == NULL) {
8014c12: 69fb ldr r3, [r7, #28]
8014c14: 681b ldr r3, [r3, #0]
8014c16: 2b00 cmp r3, #0
8014c18: d103 bne.n 8014c22 <tcp_split_unsent_seg+0x23a>
pcb->unsent_oversize = 0;
8014c1a: 687b ldr r3, [r7, #4]
8014c1c: 2200 movs r2, #0
8014c1e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
return ERR_OK;
8014c22: 2300 movs r3, #0
8014c24: e016 b.n 8014c54 <tcp_split_unsent_seg+0x26c>
goto memerr;
8014c26: bf00 nop
8014c28: e002 b.n 8014c30 <tcp_split_unsent_seg+0x248>
goto memerr;
8014c2a: bf00 nop
8014c2c: e000 b.n 8014c30 <tcp_split_unsent_seg+0x248>
goto memerr;
8014c2e: bf00 nop
memerr:
TCP_STATS_INC(tcp.memerr);
LWIP_ASSERT("seg == NULL", seg == NULL);
8014c30: 69fb ldr r3, [r7, #28]
8014c32: 2b00 cmp r3, #0
8014c34: d006 beq.n 8014c44 <tcp_split_unsent_seg+0x25c>
8014c36: 4b09 ldr r3, [pc, #36] ; (8014c5c <tcp_split_unsent_seg+0x274>)
8014c38: f44f 7276 mov.w r2, #984 ; 0x3d8
8014c3c: 490d ldr r1, [pc, #52] ; (8014c74 <tcp_split_unsent_seg+0x28c>)
8014c3e: 4809 ldr r0, [pc, #36] ; (8014c64 <tcp_split_unsent_seg+0x27c>)
8014c40: f006 f9f0 bl 801b024 <iprintf>
if (p != NULL) {
8014c44: 693b ldr r3, [r7, #16]
8014c46: 2b00 cmp r3, #0
8014c48: d002 beq.n 8014c50 <tcp_split_unsent_seg+0x268>
pbuf_free(p);
8014c4a: 6938 ldr r0, [r7, #16]
8014c4c: f7fb fcd4 bl 80105f8 <pbuf_free>
}
return ERR_MEM;
8014c50: f04f 33ff mov.w r3, #4294967295
}
8014c54: 4618 mov r0, r3
8014c56: 3724 adds r7, #36 ; 0x24
8014c58: 46bd mov sp, r7
8014c5a: bd90 pop {r4, r7, pc}
8014c5c: 0801d740 .word 0x0801d740
8014c60: 0801dad4 .word 0x0801dad4
8014c64: 0801d794 .word 0x0801d794
8014c68: 0801daf8 .word 0x0801daf8
8014c6c: 0801db1c .word 0x0801db1c
8014c70: 0801db2c .word 0x0801db2c
8014c74: 0801db3c .word 0x0801db3c
08014c78 <tcp_send_fin>:
* @param pcb the tcp_pcb over which to send a segment
* @return ERR_OK if sent, another err_t otherwise
*/
err_t
tcp_send_fin(struct tcp_pcb *pcb)
{
8014c78: b590 push {r4, r7, lr}
8014c7a: b085 sub sp, #20
8014c7c: af00 add r7, sp, #0
8014c7e: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
8014c80: 687b ldr r3, [r7, #4]
8014c82: 2b00 cmp r3, #0
8014c84: d106 bne.n 8014c94 <tcp_send_fin+0x1c>
8014c86: 4b21 ldr r3, [pc, #132] ; (8014d0c <tcp_send_fin+0x94>)
8014c88: f240 32eb movw r2, #1003 ; 0x3eb
8014c8c: 4920 ldr r1, [pc, #128] ; (8014d10 <tcp_send_fin+0x98>)
8014c8e: 4821 ldr r0, [pc, #132] ; (8014d14 <tcp_send_fin+0x9c>)
8014c90: f006 f9c8 bl 801b024 <iprintf>
/* first, try to add the fin to the last unsent segment */
if (pcb->unsent != NULL) {
8014c94: 687b ldr r3, [r7, #4]
8014c96: 6edb ldr r3, [r3, #108] ; 0x6c
8014c98: 2b00 cmp r3, #0
8014c9a: d02e beq.n 8014cfa <tcp_send_fin+0x82>
struct tcp_seg *last_unsent;
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014c9c: 687b ldr r3, [r7, #4]
8014c9e: 6edb ldr r3, [r3, #108] ; 0x6c
8014ca0: 60fb str r3, [r7, #12]
8014ca2: e002 b.n 8014caa <tcp_send_fin+0x32>
last_unsent = last_unsent->next);
8014ca4: 68fb ldr r3, [r7, #12]
8014ca6: 681b ldr r3, [r3, #0]
8014ca8: 60fb str r3, [r7, #12]
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
8014caa: 68fb ldr r3, [r7, #12]
8014cac: 681b ldr r3, [r3, #0]
8014cae: 2b00 cmp r3, #0
8014cb0: d1f8 bne.n 8014ca4 <tcp_send_fin+0x2c>
if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
8014cb2: 68fb ldr r3, [r7, #12]
8014cb4: 68db ldr r3, [r3, #12]
8014cb6: 899b ldrh r3, [r3, #12]
8014cb8: b29b uxth r3, r3
8014cba: 4618 mov r0, r3
8014cbc: f7fa f8e8 bl 800ee90 <lwip_htons>
8014cc0: 4603 mov r3, r0
8014cc2: b2db uxtb r3, r3
8014cc4: f003 0307 and.w r3, r3, #7
8014cc8: 2b00 cmp r3, #0
8014cca: d116 bne.n 8014cfa <tcp_send_fin+0x82>
/* no SYN/FIN/RST flag in the header, we can add the FIN flag */
TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
8014ccc: 68fb ldr r3, [r7, #12]
8014cce: 68db ldr r3, [r3, #12]
8014cd0: 899b ldrh r3, [r3, #12]
8014cd2: b29c uxth r4, r3
8014cd4: 2001 movs r0, #1
8014cd6: f7fa f8db bl 800ee90 <lwip_htons>
8014cda: 4603 mov r3, r0
8014cdc: 461a mov r2, r3
8014cde: 68fb ldr r3, [r7, #12]
8014ce0: 68db ldr r3, [r3, #12]
8014ce2: 4322 orrs r2, r4
8014ce4: b292 uxth r2, r2
8014ce6: 819a strh r2, [r3, #12]
tcp_set_flags(pcb, TF_FIN);
8014ce8: 687b ldr r3, [r7, #4]
8014cea: 8b5b ldrh r3, [r3, #26]
8014cec: f043 0320 orr.w r3, r3, #32
8014cf0: b29a uxth r2, r3
8014cf2: 687b ldr r3, [r7, #4]
8014cf4: 835a strh r2, [r3, #26]
return ERR_OK;
8014cf6: 2300 movs r3, #0
8014cf8: e004 b.n 8014d04 <tcp_send_fin+0x8c>
}
}
/* no data, no length, flags, copy=1, no optdata */
return tcp_enqueue_flags(pcb, TCP_FIN);
8014cfa: 2101 movs r1, #1
8014cfc: 6878 ldr r0, [r7, #4]
8014cfe: f000 f80b bl 8014d18 <tcp_enqueue_flags>
8014d02: 4603 mov r3, r0
}
8014d04: 4618 mov r0, r3
8014d06: 3714 adds r7, #20
8014d08: 46bd mov sp, r7
8014d0a: bd90 pop {r4, r7, pc}
8014d0c: 0801d740 .word 0x0801d740
8014d10: 0801db48 .word 0x0801db48
8014d14: 0801d794 .word 0x0801d794
08014d18 <tcp_enqueue_flags>:
* @param pcb Protocol control block for the TCP connection.
* @param flags TCP header flags to set in the outgoing segment.
*/
err_t
tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
{
8014d18: b580 push {r7, lr}
8014d1a: b08a sub sp, #40 ; 0x28
8014d1c: af02 add r7, sp, #8
8014d1e: 6078 str r0, [r7, #4]
8014d20: 460b mov r3, r1
8014d22: 70fb strb r3, [r7, #3]
struct pbuf *p;
struct tcp_seg *seg;
u8_t optflags = 0;
8014d24: 2300 movs r3, #0
8014d26: 77fb strb r3, [r7, #31]
u8_t optlen = 0;
8014d28: 2300 movs r3, #0
8014d2a: 75fb strb r3, [r7, #23]
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
8014d2c: 78fb ldrb r3, [r7, #3]
8014d2e: f003 0303 and.w r3, r3, #3
8014d32: 2b00 cmp r3, #0
8014d34: d106 bne.n 8014d44 <tcp_enqueue_flags+0x2c>
8014d36: 4b67 ldr r3, [pc, #412] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014d38: f240 4212 movw r2, #1042 ; 0x412
8014d3c: 4966 ldr r1, [pc, #408] ; (8014ed8 <tcp_enqueue_flags+0x1c0>)
8014d3e: 4867 ldr r0, [pc, #412] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014d40: f006 f970 bl 801b024 <iprintf>
(flags & (TCP_SYN | TCP_FIN)) != 0);
LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
8014d44: 687b ldr r3, [r7, #4]
8014d46: 2b00 cmp r3, #0
8014d48: d106 bne.n 8014d58 <tcp_enqueue_flags+0x40>
8014d4a: 4b62 ldr r3, [pc, #392] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014d4c: f240 4213 movw r2, #1043 ; 0x413
8014d50: 4963 ldr r1, [pc, #396] ; (8014ee0 <tcp_enqueue_flags+0x1c8>)
8014d52: 4862 ldr r0, [pc, #392] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014d54: f006 f966 bl 801b024 <iprintf>
/* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
/* Get options for this segment. This is a special case since this is the
only place where a SYN can be sent. */
if (flags & TCP_SYN) {
8014d58: 78fb ldrb r3, [r7, #3]
8014d5a: f003 0302 and.w r3, r3, #2
8014d5e: 2b00 cmp r3, #0
8014d60: d001 beq.n 8014d66 <tcp_enqueue_flags+0x4e>
optflags = TF_SEG_OPTS_MSS;
8014d62: 2301 movs r3, #1
8014d64: 77fb strb r3, [r7, #31]
/* Make sure the timestamp option is only included in data segments if we
agreed about it with the remote host (and in active open SYN segments). */
optflags |= TF_SEG_OPTS_TS;
}
#endif /* LWIP_TCP_TIMESTAMPS */
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8014d66: 7ffb ldrb r3, [r7, #31]
8014d68: 009b lsls r3, r3, #2
8014d6a: b2db uxtb r3, r3
8014d6c: f003 0304 and.w r3, r3, #4
8014d70: 75fb strb r3, [r7, #23]
/* Allocate pbuf with room for TCP header + options */
if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
8014d72: 7dfb ldrb r3, [r7, #23]
8014d74: b29b uxth r3, r3
8014d76: f44f 7220 mov.w r2, #640 ; 0x280
8014d7a: 4619 mov r1, r3
8014d7c: 2036 movs r0, #54 ; 0x36
8014d7e: f7fb f95b bl 8010038 <pbuf_alloc>
8014d82: 6138 str r0, [r7, #16]
8014d84: 693b ldr r3, [r7, #16]
8014d86: 2b00 cmp r3, #0
8014d88: d109 bne.n 8014d9e <tcp_enqueue_flags+0x86>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014d8a: 687b ldr r3, [r7, #4]
8014d8c: 8b5b ldrh r3, [r3, #26]
8014d8e: f043 0380 orr.w r3, r3, #128 ; 0x80
8014d92: b29a uxth r2, r3
8014d94: 687b ldr r3, [r7, #4]
8014d96: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014d98: f04f 33ff mov.w r3, #4294967295
8014d9c: e095 b.n 8014eca <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
8014d9e: 693b ldr r3, [r7, #16]
8014da0: 895a ldrh r2, [r3, #10]
8014da2: 7dfb ldrb r3, [r7, #23]
8014da4: b29b uxth r3, r3
8014da6: 429a cmp r2, r3
8014da8: d206 bcs.n 8014db8 <tcp_enqueue_flags+0xa0>
8014daa: 4b4a ldr r3, [pc, #296] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014dac: f240 423a movw r2, #1082 ; 0x43a
8014db0: 494c ldr r1, [pc, #304] ; (8014ee4 <tcp_enqueue_flags+0x1cc>)
8014db2: 484a ldr r0, [pc, #296] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014db4: f006 f936 bl 801b024 <iprintf>
(p->len >= optlen));
/* Allocate memory for tcp_seg, and fill in fields. */
if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
8014db8: 687b ldr r3, [r7, #4]
8014dba: 6dd9 ldr r1, [r3, #92] ; 0x5c
8014dbc: 78fa ldrb r2, [r7, #3]
8014dbe: 7ffb ldrb r3, [r7, #31]
8014dc0: 9300 str r3, [sp, #0]
8014dc2: 460b mov r3, r1
8014dc4: 6939 ldr r1, [r7, #16]
8014dc6: 6878 ldr r0, [r7, #4]
8014dc8: f7ff fd70 bl 80148ac <tcp_create_segment>
8014dcc: 60f8 str r0, [r7, #12]
8014dce: 68fb ldr r3, [r7, #12]
8014dd0: 2b00 cmp r3, #0
8014dd2: d109 bne.n 8014de8 <tcp_enqueue_flags+0xd0>
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8014dd4: 687b ldr r3, [r7, #4]
8014dd6: 8b5b ldrh r3, [r3, #26]
8014dd8: f043 0380 orr.w r3, r3, #128 ; 0x80
8014ddc: b29a uxth r2, r3
8014dde: 687b ldr r3, [r7, #4]
8014de0: 835a strh r2, [r3, #26]
TCP_STATS_INC(tcp.memerr);
return ERR_MEM;
8014de2: f04f 33ff mov.w r3, #4294967295
8014de6: e070 b.n 8014eca <tcp_enqueue_flags+0x1b2>
}
LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
8014de8: 68fb ldr r3, [r7, #12]
8014dea: 68db ldr r3, [r3, #12]
8014dec: f003 0303 and.w r3, r3, #3
8014df0: 2b00 cmp r3, #0
8014df2: d006 beq.n 8014e02 <tcp_enqueue_flags+0xea>
8014df4: 4b37 ldr r3, [pc, #220] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014df6: f240 4242 movw r2, #1090 ; 0x442
8014dfa: 493b ldr r1, [pc, #236] ; (8014ee8 <tcp_enqueue_flags+0x1d0>)
8014dfc: 4837 ldr r0, [pc, #220] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014dfe: f006 f911 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
8014e02: 68fb ldr r3, [r7, #12]
8014e04: 891b ldrh r3, [r3, #8]
8014e06: 2b00 cmp r3, #0
8014e08: d006 beq.n 8014e18 <tcp_enqueue_flags+0x100>
8014e0a: 4b32 ldr r3, [pc, #200] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014e0c: f240 4243 movw r2, #1091 ; 0x443
8014e10: 4936 ldr r1, [pc, #216] ; (8014eec <tcp_enqueue_flags+0x1d4>)
8014e12: 4832 ldr r0, [pc, #200] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014e14: f006 f906 bl 801b024 <iprintf>
lwip_ntohl(seg->tcphdr->seqno),
lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
(u16_t)flags));
/* Now append seg to pcb->unsent queue */
if (pcb->unsent == NULL) {
8014e18: 687b ldr r3, [r7, #4]
8014e1a: 6edb ldr r3, [r3, #108] ; 0x6c
8014e1c: 2b00 cmp r3, #0
8014e1e: d103 bne.n 8014e28 <tcp_enqueue_flags+0x110>
pcb->unsent = seg;
8014e20: 687b ldr r3, [r7, #4]
8014e22: 68fa ldr r2, [r7, #12]
8014e24: 66da str r2, [r3, #108] ; 0x6c
8014e26: e00d b.n 8014e44 <tcp_enqueue_flags+0x12c>
} else {
struct tcp_seg *useg;
for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
8014e28: 687b ldr r3, [r7, #4]
8014e2a: 6edb ldr r3, [r3, #108] ; 0x6c
8014e2c: 61bb str r3, [r7, #24]
8014e2e: e002 b.n 8014e36 <tcp_enqueue_flags+0x11e>
8014e30: 69bb ldr r3, [r7, #24]
8014e32: 681b ldr r3, [r3, #0]
8014e34: 61bb str r3, [r7, #24]
8014e36: 69bb ldr r3, [r7, #24]
8014e38: 681b ldr r3, [r3, #0]
8014e3a: 2b00 cmp r3, #0
8014e3c: d1f8 bne.n 8014e30 <tcp_enqueue_flags+0x118>
useg->next = seg;
8014e3e: 69bb ldr r3, [r7, #24]
8014e40: 68fa ldr r2, [r7, #12]
8014e42: 601a str r2, [r3, #0]
}
#if TCP_OVERSIZE
/* The new unsent tail has no space */
pcb->unsent_oversize = 0;
8014e44: 687b ldr r3, [r7, #4]
8014e46: 2200 movs r2, #0
8014e48: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
#endif /* TCP_OVERSIZE */
/* SYN and FIN bump the sequence number */
if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
8014e4c: 78fb ldrb r3, [r7, #3]
8014e4e: f003 0302 and.w r3, r3, #2
8014e52: 2b00 cmp r3, #0
8014e54: d104 bne.n 8014e60 <tcp_enqueue_flags+0x148>
8014e56: 78fb ldrb r3, [r7, #3]
8014e58: f003 0301 and.w r3, r3, #1
8014e5c: 2b00 cmp r3, #0
8014e5e: d004 beq.n 8014e6a <tcp_enqueue_flags+0x152>
pcb->snd_lbb++;
8014e60: 687b ldr r3, [r7, #4]
8014e62: 6ddb ldr r3, [r3, #92] ; 0x5c
8014e64: 1c5a adds r2, r3, #1
8014e66: 687b ldr r3, [r7, #4]
8014e68: 65da str r2, [r3, #92] ; 0x5c
/* optlen does not influence snd_buf */
}
if (flags & TCP_FIN) {
8014e6a: 78fb ldrb r3, [r7, #3]
8014e6c: f003 0301 and.w r3, r3, #1
8014e70: 2b00 cmp r3, #0
8014e72: d006 beq.n 8014e82 <tcp_enqueue_flags+0x16a>
tcp_set_flags(pcb, TF_FIN);
8014e74: 687b ldr r3, [r7, #4]
8014e76: 8b5b ldrh r3, [r3, #26]
8014e78: f043 0320 orr.w r3, r3, #32
8014e7c: b29a uxth r2, r3
8014e7e: 687b ldr r3, [r7, #4]
8014e80: 835a strh r2, [r3, #26]
}
/* update number of segments on the queues */
pcb->snd_queuelen += pbuf_clen(seg->p);
8014e82: 68fb ldr r3, [r7, #12]
8014e84: 685b ldr r3, [r3, #4]
8014e86: 4618 mov r0, r3
8014e88: f7fb fc44 bl 8010714 <pbuf_clen>
8014e8c: 4603 mov r3, r0
8014e8e: 461a mov r2, r3
8014e90: 687b ldr r3, [r7, #4]
8014e92: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014e96: 4413 add r3, r2
8014e98: b29a uxth r2, r3
8014e9a: 687b ldr r3, [r7, #4]
8014e9c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
if (pcb->snd_queuelen != 0) {
8014ea0: 687b ldr r3, [r7, #4]
8014ea2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
8014ea6: 2b00 cmp r3, #0
8014ea8: d00e beq.n 8014ec8 <tcp_enqueue_flags+0x1b0>
LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
8014eaa: 687b ldr r3, [r7, #4]
8014eac: 6f1b ldr r3, [r3, #112] ; 0x70
8014eae: 2b00 cmp r3, #0
8014eb0: d10a bne.n 8014ec8 <tcp_enqueue_flags+0x1b0>
8014eb2: 687b ldr r3, [r7, #4]
8014eb4: 6edb ldr r3, [r3, #108] ; 0x6c
8014eb6: 2b00 cmp r3, #0
8014eb8: d106 bne.n 8014ec8 <tcp_enqueue_flags+0x1b0>
8014eba: 4b06 ldr r3, [pc, #24] ; (8014ed4 <tcp_enqueue_flags+0x1bc>)
8014ebc: f240 4266 movw r2, #1126 ; 0x466
8014ec0: 490b ldr r1, [pc, #44] ; (8014ef0 <tcp_enqueue_flags+0x1d8>)
8014ec2: 4806 ldr r0, [pc, #24] ; (8014edc <tcp_enqueue_flags+0x1c4>)
8014ec4: f006 f8ae bl 801b024 <iprintf>
pcb->unacked != NULL || pcb->unsent != NULL);
}
return ERR_OK;
8014ec8: 2300 movs r3, #0
}
8014eca: 4618 mov r0, r3
8014ecc: 3720 adds r7, #32
8014ece: 46bd mov sp, r7
8014ed0: bd80 pop {r7, pc}
8014ed2: bf00 nop
8014ed4: 0801d740 .word 0x0801d740
8014ed8: 0801db64 .word 0x0801db64
8014edc: 0801d794 .word 0x0801d794
8014ee0: 0801dbbc .word 0x0801dbbc
8014ee4: 0801dbdc .word 0x0801dbdc
8014ee8: 0801dc18 .word 0x0801dc18
8014eec: 0801dc30 .word 0x0801dc30
8014ef0: 0801dc5c .word 0x0801dc5c
08014ef4 <tcp_output>:
* @return ERR_OK if data has been sent or nothing to send
* another err_t on error
*/
err_t
tcp_output(struct tcp_pcb *pcb)
{
8014ef4: b5b0 push {r4, r5, r7, lr}
8014ef6: b08a sub sp, #40 ; 0x28
8014ef8: af00 add r7, sp, #0
8014efa: 6078 str r0, [r7, #4]
s16_t i = 0;
#endif /* TCP_CWND_DEBUG */
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
8014efc: 687b ldr r3, [r7, #4]
8014efe: 2b00 cmp r3, #0
8014f00: d106 bne.n 8014f10 <tcp_output+0x1c>
8014f02: 4ba0 ldr r3, [pc, #640] ; (8015184 <tcp_output+0x290>)
8014f04: f240 42e1 movw r2, #1249 ; 0x4e1
8014f08: 499f ldr r1, [pc, #636] ; (8015188 <tcp_output+0x294>)
8014f0a: 48a0 ldr r0, [pc, #640] ; (801518c <tcp_output+0x298>)
8014f0c: f006 f88a bl 801b024 <iprintf>
/* pcb->state LISTEN not allowed here */
LWIP_ASSERT("don't call tcp_output for listen-pcbs",
8014f10: 687b ldr r3, [r7, #4]
8014f12: 7d1b ldrb r3, [r3, #20]
8014f14: 2b01 cmp r3, #1
8014f16: d106 bne.n 8014f26 <tcp_output+0x32>
8014f18: 4b9a ldr r3, [pc, #616] ; (8015184 <tcp_output+0x290>)
8014f1a: f240 42e4 movw r2, #1252 ; 0x4e4
8014f1e: 499c ldr r1, [pc, #624] ; (8015190 <tcp_output+0x29c>)
8014f20: 489a ldr r0, [pc, #616] ; (801518c <tcp_output+0x298>)
8014f22: f006 f87f bl 801b024 <iprintf>
/* First, check if we are invoked by the TCP input processing
code. If so, we do not output anything. Instead, we rely on the
input processing code to call us when input processing is done
with. */
if (tcp_input_pcb == pcb) {
8014f26: 4b9b ldr r3, [pc, #620] ; (8015194 <tcp_output+0x2a0>)
8014f28: 681b ldr r3, [r3, #0]
8014f2a: 687a ldr r2, [r7, #4]
8014f2c: 429a cmp r2, r3
8014f2e: d101 bne.n 8014f34 <tcp_output+0x40>
return ERR_OK;
8014f30: 2300 movs r3, #0
8014f32: e1d2 b.n 80152da <tcp_output+0x3e6>
}
wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
8014f34: 687b ldr r3, [r7, #4]
8014f36: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
8014f3a: 687b ldr r3, [r7, #4]
8014f3c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8014f40: 429a cmp r2, r3
8014f42: d203 bcs.n 8014f4c <tcp_output+0x58>
8014f44: 687b ldr r3, [r7, #4]
8014f46: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014f4a: e002 b.n 8014f52 <tcp_output+0x5e>
8014f4c: 687b ldr r3, [r7, #4]
8014f4e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8014f52: 61bb str r3, [r7, #24]
seg = pcb->unsent;
8014f54: 687b ldr r3, [r7, #4]
8014f56: 6edb ldr r3, [r3, #108] ; 0x6c
8014f58: 627b str r3, [r7, #36] ; 0x24
if (seg == NULL) {
8014f5a: 6a7b ldr r3, [r7, #36] ; 0x24
8014f5c: 2b00 cmp r3, #0
8014f5e: d10b bne.n 8014f78 <tcp_output+0x84>
", seg == NULL, ack %"U32_F"\n",
pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
/* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
* an empty ACK segment and send it. */
if (pcb->flags & TF_ACK_NOW) {
8014f60: 687b ldr r3, [r7, #4]
8014f62: 8b5b ldrh r3, [r3, #26]
8014f64: f003 0302 and.w r3, r3, #2
8014f68: 2b00 cmp r3, #0
8014f6a: f000 81a9 beq.w 80152c0 <tcp_output+0x3cc>
return tcp_send_empty_ack(pcb);
8014f6e: 6878 ldr r0, [r7, #4]
8014f70: f000 fdd8 bl 8015b24 <tcp_send_empty_ack>
8014f74: 4603 mov r3, r0
8014f76: e1b0 b.n 80152da <tcp_output+0x3e6>
pcb->snd_wnd, pcb->cwnd, wnd,
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
}
netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
8014f78: 6879 ldr r1, [r7, #4]
8014f7a: 687b ldr r3, [r7, #4]
8014f7c: 3304 adds r3, #4
8014f7e: 461a mov r2, r3
8014f80: 6878 ldr r0, [r7, #4]
8014f82: f7ff fc77 bl 8014874 <tcp_route>
8014f86: 6178 str r0, [r7, #20]
if (netif == NULL) {
8014f88: 697b ldr r3, [r7, #20]
8014f8a: 2b00 cmp r3, #0
8014f8c: d102 bne.n 8014f94 <tcp_output+0xa0>
return ERR_RTE;
8014f8e: f06f 0303 mvn.w r3, #3
8014f92: e1a2 b.n 80152da <tcp_output+0x3e6>
}
/* If we don't have a local IP address, we get one from netif */
if (ip_addr_isany(&pcb->local_ip)) {
8014f94: 687b ldr r3, [r7, #4]
8014f96: 2b00 cmp r3, #0
8014f98: d003 beq.n 8014fa2 <tcp_output+0xae>
8014f9a: 687b ldr r3, [r7, #4]
8014f9c: 681b ldr r3, [r3, #0]
8014f9e: 2b00 cmp r3, #0
8014fa0: d111 bne.n 8014fc6 <tcp_output+0xd2>
const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
8014fa2: 697b ldr r3, [r7, #20]
8014fa4: 2b00 cmp r3, #0
8014fa6: d002 beq.n 8014fae <tcp_output+0xba>
8014fa8: 697b ldr r3, [r7, #20]
8014faa: 3304 adds r3, #4
8014fac: e000 b.n 8014fb0 <tcp_output+0xbc>
8014fae: 2300 movs r3, #0
8014fb0: 613b str r3, [r7, #16]
if (local_ip == NULL) {
8014fb2: 693b ldr r3, [r7, #16]
8014fb4: 2b00 cmp r3, #0
8014fb6: d102 bne.n 8014fbe <tcp_output+0xca>
return ERR_RTE;
8014fb8: f06f 0303 mvn.w r3, #3
8014fbc: e18d b.n 80152da <tcp_output+0x3e6>
}
ip_addr_copy(pcb->local_ip, *local_ip);
8014fbe: 693b ldr r3, [r7, #16]
8014fc0: 681a ldr r2, [r3, #0]
8014fc2: 687b ldr r3, [r7, #4]
8014fc4: 601a str r2, [r3, #0]
}
/* Handle the current segment not fitting within the window */
if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
8014fc6: 6a7b ldr r3, [r7, #36] ; 0x24
8014fc8: 68db ldr r3, [r3, #12]
8014fca: 685b ldr r3, [r3, #4]
8014fcc: 4618 mov r0, r3
8014fce: f7f9 ff74 bl 800eeba <lwip_htonl>
8014fd2: 4602 mov r2, r0
8014fd4: 687b ldr r3, [r7, #4]
8014fd6: 6c5b ldr r3, [r3, #68] ; 0x44
8014fd8: 1ad3 subs r3, r2, r3
8014fda: 6a7a ldr r2, [r7, #36] ; 0x24
8014fdc: 8912 ldrh r2, [r2, #8]
8014fde: 4413 add r3, r2
8014fe0: 69ba ldr r2, [r7, #24]
8014fe2: 429a cmp r2, r3
8014fe4: d227 bcs.n 8015036 <tcp_output+0x142>
* within the remaining (could be 0) send window and RTO timer is not running (we
* have no in-flight data). If window is still too small after persist timer fires,
* then we split the segment. We don't consider the congestion window since a cwnd
* smaller than 1 SMSS implies in-flight data
*/
if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
8014fe6: 687b ldr r3, [r7, #4]
8014fe8: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8014fec: 461a mov r2, r3
8014fee: 69bb ldr r3, [r7, #24]
8014ff0: 4293 cmp r3, r2
8014ff2: d114 bne.n 801501e <tcp_output+0x12a>
8014ff4: 687b ldr r3, [r7, #4]
8014ff6: 6f1b ldr r3, [r3, #112] ; 0x70
8014ff8: 2b00 cmp r3, #0
8014ffa: d110 bne.n 801501e <tcp_output+0x12a>
8014ffc: 687b ldr r3, [r7, #4]
8014ffe: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
8015002: 2b00 cmp r3, #0
8015004: d10b bne.n 801501e <tcp_output+0x12a>
pcb->persist_cnt = 0;
8015006: 687b ldr r3, [r7, #4]
8015008: 2200 movs r2, #0
801500a: f883 2098 strb.w r2, [r3, #152] ; 0x98
pcb->persist_backoff = 1;
801500e: 687b ldr r3, [r7, #4]
8015010: 2201 movs r2, #1
8015012: f883 2099 strb.w r2, [r3, #153] ; 0x99
pcb->persist_probe = 0;
8015016: 687b ldr r3, [r7, #4]
8015018: 2200 movs r2, #0
801501a: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
/* We need an ACK, but can't send data now, so send an empty ACK */
if (pcb->flags & TF_ACK_NOW) {
801501e: 687b ldr r3, [r7, #4]
8015020: 8b5b ldrh r3, [r3, #26]
8015022: f003 0302 and.w r3, r3, #2
8015026: 2b00 cmp r3, #0
8015028: f000 814c beq.w 80152c4 <tcp_output+0x3d0>
return tcp_send_empty_ack(pcb);
801502c: 6878 ldr r0, [r7, #4]
801502e: f000 fd79 bl 8015b24 <tcp_send_empty_ack>
8015032: 4603 mov r3, r0
8015034: e151 b.n 80152da <tcp_output+0x3e6>
}
goto output_done;
}
/* Stop persist timer, above conditions are not active */
pcb->persist_backoff = 0;
8015036: 687b ldr r3, [r7, #4]
8015038: 2200 movs r2, #0
801503a: f883 2099 strb.w r2, [r3, #153] ; 0x99
/* useg should point to last segment on unacked queue */
useg = pcb->unacked;
801503e: 687b ldr r3, [r7, #4]
8015040: 6f1b ldr r3, [r3, #112] ; 0x70
8015042: 623b str r3, [r7, #32]
if (useg != NULL) {
8015044: 6a3b ldr r3, [r7, #32]
8015046: 2b00 cmp r3, #0
8015048: f000 811b beq.w 8015282 <tcp_output+0x38e>
for (; useg->next != NULL; useg = useg->next);
801504c: e002 b.n 8015054 <tcp_output+0x160>
801504e: 6a3b ldr r3, [r7, #32]
8015050: 681b ldr r3, [r3, #0]
8015052: 623b str r3, [r7, #32]
8015054: 6a3b ldr r3, [r7, #32]
8015056: 681b ldr r3, [r3, #0]
8015058: 2b00 cmp r3, #0
801505a: d1f8 bne.n 801504e <tcp_output+0x15a>
}
/* data available and window allows it to be sent? */
while (seg != NULL &&
801505c: e111 b.n 8015282 <tcp_output+0x38e>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
LWIP_ASSERT("RST not expected here!",
801505e: 6a7b ldr r3, [r7, #36] ; 0x24
8015060: 68db ldr r3, [r3, #12]
8015062: 899b ldrh r3, [r3, #12]
8015064: b29b uxth r3, r3
8015066: 4618 mov r0, r3
8015068: f7f9 ff12 bl 800ee90 <lwip_htons>
801506c: 4603 mov r3, r0
801506e: b2db uxtb r3, r3
8015070: f003 0304 and.w r3, r3, #4
8015074: 2b00 cmp r3, #0
8015076: d006 beq.n 8015086 <tcp_output+0x192>
8015078: 4b42 ldr r3, [pc, #264] ; (8015184 <tcp_output+0x290>)
801507a: f240 5237 movw r2, #1335 ; 0x537
801507e: 4946 ldr r1, [pc, #280] ; (8015198 <tcp_output+0x2a4>)
8015080: 4842 ldr r0, [pc, #264] ; (801518c <tcp_output+0x298>)
8015082: f005 ffcf bl 801b024 <iprintf>
* - if tcp_write had a memory error before (prevent delayed ACK timeout) or
* - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
* either seg->next != NULL or pcb->unacked == NULL;
* RST is no sent using tcp_write/tcp_output.
*/
if ((tcp_do_output_nagle(pcb) == 0) &&
8015086: 687b ldr r3, [r7, #4]
8015088: 6f1b ldr r3, [r3, #112] ; 0x70
801508a: 2b00 cmp r3, #0
801508c: d01f beq.n 80150ce <tcp_output+0x1da>
801508e: 687b ldr r3, [r7, #4]
8015090: 8b5b ldrh r3, [r3, #26]
8015092: f003 0344 and.w r3, r3, #68 ; 0x44
8015096: 2b00 cmp r3, #0
8015098: d119 bne.n 80150ce <tcp_output+0x1da>
801509a: 687b ldr r3, [r7, #4]
801509c: 6edb ldr r3, [r3, #108] ; 0x6c
801509e: 2b00 cmp r3, #0
80150a0: d00b beq.n 80150ba <tcp_output+0x1c6>
80150a2: 687b ldr r3, [r7, #4]
80150a4: 6edb ldr r3, [r3, #108] ; 0x6c
80150a6: 681b ldr r3, [r3, #0]
80150a8: 2b00 cmp r3, #0
80150aa: d110 bne.n 80150ce <tcp_output+0x1da>
80150ac: 687b ldr r3, [r7, #4]
80150ae: 6edb ldr r3, [r3, #108] ; 0x6c
80150b0: 891a ldrh r2, [r3, #8]
80150b2: 687b ldr r3, [r7, #4]
80150b4: 8e5b ldrh r3, [r3, #50] ; 0x32
80150b6: 429a cmp r2, r3
80150b8: d209 bcs.n 80150ce <tcp_output+0x1da>
80150ba: 687b ldr r3, [r7, #4]
80150bc: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64
80150c0: 2b00 cmp r3, #0
80150c2: d004 beq.n 80150ce <tcp_output+0x1da>
80150c4: 687b ldr r3, [r7, #4]
80150c6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
80150ca: 2b08 cmp r3, #8
80150cc: d901 bls.n 80150d2 <tcp_output+0x1de>
80150ce: 2301 movs r3, #1
80150d0: e000 b.n 80150d4 <tcp_output+0x1e0>
80150d2: 2300 movs r3, #0
80150d4: 2b00 cmp r3, #0
80150d6: d106 bne.n 80150e6 <tcp_output+0x1f2>
((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
80150d8: 687b ldr r3, [r7, #4]
80150da: 8b5b ldrh r3, [r3, #26]
80150dc: f003 03a0 and.w r3, r3, #160 ; 0xa0
if ((tcp_do_output_nagle(pcb) == 0) &&
80150e0: 2b00 cmp r3, #0
80150e2: f000 80e3 beq.w 80152ac <tcp_output+0x3b8>
pcb->lastack,
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
++i;
#endif /* TCP_CWND_DEBUG */
if (pcb->state != SYN_SENT) {
80150e6: 687b ldr r3, [r7, #4]
80150e8: 7d1b ldrb r3, [r3, #20]
80150ea: 2b02 cmp r3, #2
80150ec: d00d beq.n 801510a <tcp_output+0x216>
TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
80150ee: 6a7b ldr r3, [r7, #36] ; 0x24
80150f0: 68db ldr r3, [r3, #12]
80150f2: 899b ldrh r3, [r3, #12]
80150f4: b29c uxth r4, r3
80150f6: 2010 movs r0, #16
80150f8: f7f9 feca bl 800ee90 <lwip_htons>
80150fc: 4603 mov r3, r0
80150fe: 461a mov r2, r3
8015100: 6a7b ldr r3, [r7, #36] ; 0x24
8015102: 68db ldr r3, [r3, #12]
8015104: 4322 orrs r2, r4
8015106: b292 uxth r2, r2
8015108: 819a strh r2, [r3, #12]
}
err = tcp_output_segment(seg, pcb, netif);
801510a: 697a ldr r2, [r7, #20]
801510c: 6879 ldr r1, [r7, #4]
801510e: 6a78 ldr r0, [r7, #36] ; 0x24
8015110: f000 f908 bl 8015324 <tcp_output_segment>
8015114: 4603 mov r3, r0
8015116: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
8015118: f997 300f ldrsb.w r3, [r7, #15]
801511c: 2b00 cmp r3, #0
801511e: d009 beq.n 8015134 <tcp_output+0x240>
/* segment could not be sent, for whatever reason */
tcp_set_flags(pcb, TF_NAGLEMEMERR);
8015120: 687b ldr r3, [r7, #4]
8015122: 8b5b ldrh r3, [r3, #26]
8015124: f043 0380 orr.w r3, r3, #128 ; 0x80
8015128: b29a uxth r2, r3
801512a: 687b ldr r3, [r7, #4]
801512c: 835a strh r2, [r3, #26]
return err;
801512e: f997 300f ldrsb.w r3, [r7, #15]
8015132: e0d2 b.n 80152da <tcp_output+0x3e6>
}
#if TCP_OVERSIZE_DBGCHECK
seg->oversize_left = 0;
#endif /* TCP_OVERSIZE_DBGCHECK */
pcb->unsent = seg->next;
8015134: 6a7b ldr r3, [r7, #36] ; 0x24
8015136: 681a ldr r2, [r3, #0]
8015138: 687b ldr r3, [r7, #4]
801513a: 66da str r2, [r3, #108] ; 0x6c
if (pcb->state != SYN_SENT) {
801513c: 687b ldr r3, [r7, #4]
801513e: 7d1b ldrb r3, [r3, #20]
8015140: 2b02 cmp r3, #2
8015142: d006 beq.n 8015152 <tcp_output+0x25e>
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015144: 687b ldr r3, [r7, #4]
8015146: 8b5b ldrh r3, [r3, #26]
8015148: f023 0303 bic.w r3, r3, #3
801514c: b29a uxth r2, r3
801514e: 687b ldr r3, [r7, #4]
8015150: 835a strh r2, [r3, #26]
}
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
8015152: 6a7b ldr r3, [r7, #36] ; 0x24
8015154: 68db ldr r3, [r3, #12]
8015156: 685b ldr r3, [r3, #4]
8015158: 4618 mov r0, r3
801515a: f7f9 feae bl 800eeba <lwip_htonl>
801515e: 4604 mov r4, r0
8015160: 6a7b ldr r3, [r7, #36] ; 0x24
8015162: 891b ldrh r3, [r3, #8]
8015164: 461d mov r5, r3
8015166: 6a7b ldr r3, [r7, #36] ; 0x24
8015168: 68db ldr r3, [r3, #12]
801516a: 899b ldrh r3, [r3, #12]
801516c: b29b uxth r3, r3
801516e: 4618 mov r0, r3
8015170: f7f9 fe8e bl 800ee90 <lwip_htons>
8015174: 4603 mov r3, r0
8015176: b2db uxtb r3, r3
8015178: f003 0303 and.w r3, r3, #3
801517c: 2b00 cmp r3, #0
801517e: d00d beq.n 801519c <tcp_output+0x2a8>
8015180: 2301 movs r3, #1
8015182: e00c b.n 801519e <tcp_output+0x2aa>
8015184: 0801d740 .word 0x0801d740
8015188: 0801dc84 .word 0x0801dc84
801518c: 0801d794 .word 0x0801d794
8015190: 0801dc9c .word 0x0801dc9c
8015194: 2000f5d4 .word 0x2000f5d4
8015198: 0801dcc4 .word 0x0801dcc4
801519c: 2300 movs r3, #0
801519e: 442b add r3, r5
80151a0: 4423 add r3, r4
80151a2: 60bb str r3, [r7, #8]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
80151a4: 687b ldr r3, [r7, #4]
80151a6: 6d1a ldr r2, [r3, #80] ; 0x50
80151a8: 68bb ldr r3, [r7, #8]
80151aa: 1ad3 subs r3, r2, r3
80151ac: 2b00 cmp r3, #0
80151ae: da02 bge.n 80151b6 <tcp_output+0x2c2>
pcb->snd_nxt = snd_nxt;
80151b0: 687b ldr r3, [r7, #4]
80151b2: 68ba ldr r2, [r7, #8]
80151b4: 651a str r2, [r3, #80] ; 0x50
}
/* put segment on unacknowledged list if length > 0 */
if (TCP_TCPLEN(seg) > 0) {
80151b6: 6a7b ldr r3, [r7, #36] ; 0x24
80151b8: 891b ldrh r3, [r3, #8]
80151ba: 461c mov r4, r3
80151bc: 6a7b ldr r3, [r7, #36] ; 0x24
80151be: 68db ldr r3, [r3, #12]
80151c0: 899b ldrh r3, [r3, #12]
80151c2: b29b uxth r3, r3
80151c4: 4618 mov r0, r3
80151c6: f7f9 fe63 bl 800ee90 <lwip_htons>
80151ca: 4603 mov r3, r0
80151cc: b2db uxtb r3, r3
80151ce: f003 0303 and.w r3, r3, #3
80151d2: 2b00 cmp r3, #0
80151d4: d001 beq.n 80151da <tcp_output+0x2e6>
80151d6: 2301 movs r3, #1
80151d8: e000 b.n 80151dc <tcp_output+0x2e8>
80151da: 2300 movs r3, #0
80151dc: 4423 add r3, r4
80151de: 2b00 cmp r3, #0
80151e0: d049 beq.n 8015276 <tcp_output+0x382>
seg->next = NULL;
80151e2: 6a7b ldr r3, [r7, #36] ; 0x24
80151e4: 2200 movs r2, #0
80151e6: 601a str r2, [r3, #0]
/* unacked list is empty? */
if (pcb->unacked == NULL) {
80151e8: 687b ldr r3, [r7, #4]
80151ea: 6f1b ldr r3, [r3, #112] ; 0x70
80151ec: 2b00 cmp r3, #0
80151ee: d105 bne.n 80151fc <tcp_output+0x308>
pcb->unacked = seg;
80151f0: 687b ldr r3, [r7, #4]
80151f2: 6a7a ldr r2, [r7, #36] ; 0x24
80151f4: 671a str r2, [r3, #112] ; 0x70
useg = seg;
80151f6: 6a7b ldr r3, [r7, #36] ; 0x24
80151f8: 623b str r3, [r7, #32]
80151fa: e03f b.n 801527c <tcp_output+0x388>
/* unacked list is not empty? */
} else {
/* In the case of fast retransmit, the packet should not go to the tail
* of the unacked queue, but rather somewhere before it. We need to check for
* this case. -STJ Jul 27, 2004 */
if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
80151fc: 6a7b ldr r3, [r7, #36] ; 0x24
80151fe: 68db ldr r3, [r3, #12]
8015200: 685b ldr r3, [r3, #4]
8015202: 4618 mov r0, r3
8015204: f7f9 fe59 bl 800eeba <lwip_htonl>
8015208: 4604 mov r4, r0
801520a: 6a3b ldr r3, [r7, #32]
801520c: 68db ldr r3, [r3, #12]
801520e: 685b ldr r3, [r3, #4]
8015210: 4618 mov r0, r3
8015212: f7f9 fe52 bl 800eeba <lwip_htonl>
8015216: 4603 mov r3, r0
8015218: 1ae3 subs r3, r4, r3
801521a: 2b00 cmp r3, #0
801521c: da24 bge.n 8015268 <tcp_output+0x374>
/* add segment to before tail of unacked list, keeping the list sorted */
struct tcp_seg **cur_seg = &(pcb->unacked);
801521e: 687b ldr r3, [r7, #4]
8015220: 3370 adds r3, #112 ; 0x70
8015222: 61fb str r3, [r7, #28]
while (*cur_seg &&
8015224: e002 b.n 801522c <tcp_output+0x338>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
8015226: 69fb ldr r3, [r7, #28]
8015228: 681b ldr r3, [r3, #0]
801522a: 61fb str r3, [r7, #28]
while (*cur_seg &&
801522c: 69fb ldr r3, [r7, #28]
801522e: 681b ldr r3, [r3, #0]
8015230: 2b00 cmp r3, #0
8015232: d011 beq.n 8015258 <tcp_output+0x364>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
8015234: 69fb ldr r3, [r7, #28]
8015236: 681b ldr r3, [r3, #0]
8015238: 68db ldr r3, [r3, #12]
801523a: 685b ldr r3, [r3, #4]
801523c: 4618 mov r0, r3
801523e: f7f9 fe3c bl 800eeba <lwip_htonl>
8015242: 4604 mov r4, r0
8015244: 6a7b ldr r3, [r7, #36] ; 0x24
8015246: 68db ldr r3, [r3, #12]
8015248: 685b ldr r3, [r3, #4]
801524a: 4618 mov r0, r3
801524c: f7f9 fe35 bl 800eeba <lwip_htonl>
8015250: 4603 mov r3, r0
8015252: 1ae3 subs r3, r4, r3
while (*cur_seg &&
8015254: 2b00 cmp r3, #0
8015256: dbe6 blt.n 8015226 <tcp_output+0x332>
}
seg->next = (*cur_seg);
8015258: 69fb ldr r3, [r7, #28]
801525a: 681a ldr r2, [r3, #0]
801525c: 6a7b ldr r3, [r7, #36] ; 0x24
801525e: 601a str r2, [r3, #0]
(*cur_seg) = seg;
8015260: 69fb ldr r3, [r7, #28]
8015262: 6a7a ldr r2, [r7, #36] ; 0x24
8015264: 601a str r2, [r3, #0]
8015266: e009 b.n 801527c <tcp_output+0x388>
} else {
/* add segment to tail of unacked list */
useg->next = seg;
8015268: 6a3b ldr r3, [r7, #32]
801526a: 6a7a ldr r2, [r7, #36] ; 0x24
801526c: 601a str r2, [r3, #0]
useg = useg->next;
801526e: 6a3b ldr r3, [r7, #32]
8015270: 681b ldr r3, [r3, #0]
8015272: 623b str r3, [r7, #32]
8015274: e002 b.n 801527c <tcp_output+0x388>
}
}
/* do not queue empty segments on the unacked list */
} else {
tcp_seg_free(seg);
8015276: 6a78 ldr r0, [r7, #36] ; 0x24
8015278: f7fc fc42 bl 8011b00 <tcp_seg_free>
}
seg = pcb->unsent;
801527c: 687b ldr r3, [r7, #4]
801527e: 6edb ldr r3, [r3, #108] ; 0x6c
8015280: 627b str r3, [r7, #36] ; 0x24
while (seg != NULL &&
8015282: 6a7b ldr r3, [r7, #36] ; 0x24
8015284: 2b00 cmp r3, #0
8015286: d012 beq.n 80152ae <tcp_output+0x3ba>
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
8015288: 6a7b ldr r3, [r7, #36] ; 0x24
801528a: 68db ldr r3, [r3, #12]
801528c: 685b ldr r3, [r3, #4]
801528e: 4618 mov r0, r3
8015290: f7f9 fe13 bl 800eeba <lwip_htonl>
8015294: 4602 mov r2, r0
8015296: 687b ldr r3, [r7, #4]
8015298: 6c5b ldr r3, [r3, #68] ; 0x44
801529a: 1ad3 subs r3, r2, r3
801529c: 6a7a ldr r2, [r7, #36] ; 0x24
801529e: 8912 ldrh r2, [r2, #8]
80152a0: 4413 add r3, r2
while (seg != NULL &&
80152a2: 69ba ldr r2, [r7, #24]
80152a4: 429a cmp r2, r3
80152a6: f4bf aeda bcs.w 801505e <tcp_output+0x16a>
80152aa: e000 b.n 80152ae <tcp_output+0x3ba>
break;
80152ac: bf00 nop
}
#if TCP_OVERSIZE
if (pcb->unsent == NULL) {
80152ae: 687b ldr r3, [r7, #4]
80152b0: 6edb ldr r3, [r3, #108] ; 0x6c
80152b2: 2b00 cmp r3, #0
80152b4: d108 bne.n 80152c8 <tcp_output+0x3d4>
/* last unsent has been removed, reset unsent_oversize */
pcb->unsent_oversize = 0;
80152b6: 687b ldr r3, [r7, #4]
80152b8: 2200 movs r2, #0
80152ba: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
80152be: e004 b.n 80152ca <tcp_output+0x3d6>
goto output_done;
80152c0: bf00 nop
80152c2: e002 b.n 80152ca <tcp_output+0x3d6>
goto output_done;
80152c4: bf00 nop
80152c6: e000 b.n 80152ca <tcp_output+0x3d6>
}
#endif /* TCP_OVERSIZE */
output_done:
80152c8: bf00 nop
tcp_clear_flags(pcb, TF_NAGLEMEMERR);
80152ca: 687b ldr r3, [r7, #4]
80152cc: 8b5b ldrh r3, [r3, #26]
80152ce: f023 0380 bic.w r3, r3, #128 ; 0x80
80152d2: b29a uxth r2, r3
80152d4: 687b ldr r3, [r7, #4]
80152d6: 835a strh r2, [r3, #26]
return ERR_OK;
80152d8: 2300 movs r3, #0
}
80152da: 4618 mov r0, r3
80152dc: 3728 adds r7, #40 ; 0x28
80152de: 46bd mov sp, r7
80152e0: bdb0 pop {r4, r5, r7, pc}
80152e2: bf00 nop
080152e4 <tcp_output_segment_busy>:
* @arg seg the tcp segment to check
* @return 1 if ref != 1, 0 if ref == 1
*/
static int
tcp_output_segment_busy(const struct tcp_seg *seg)
{
80152e4: b580 push {r7, lr}
80152e6: b082 sub sp, #8
80152e8: af00 add r7, sp, #0
80152ea: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
80152ec: 687b ldr r3, [r7, #4]
80152ee: 2b00 cmp r3, #0
80152f0: d106 bne.n 8015300 <tcp_output_segment_busy+0x1c>
80152f2: 4b09 ldr r3, [pc, #36] ; (8015318 <tcp_output_segment_busy+0x34>)
80152f4: f240 529a movw r2, #1434 ; 0x59a
80152f8: 4908 ldr r1, [pc, #32] ; (801531c <tcp_output_segment_busy+0x38>)
80152fa: 4809 ldr r0, [pc, #36] ; (8015320 <tcp_output_segment_busy+0x3c>)
80152fc: f005 fe92 bl 801b024 <iprintf>
/* We only need to check the first pbuf here:
If a pbuf is queued for transmission, a driver calls pbuf_ref(),
which only changes the ref count of the first pbuf */
if (seg->p->ref != 1) {
8015300: 687b ldr r3, [r7, #4]
8015302: 685b ldr r3, [r3, #4]
8015304: 7b9b ldrb r3, [r3, #14]
8015306: 2b01 cmp r3, #1
8015308: d001 beq.n 801530e <tcp_output_segment_busy+0x2a>
/* other reference found */
return 1;
801530a: 2301 movs r3, #1
801530c: e000 b.n 8015310 <tcp_output_segment_busy+0x2c>
}
/* no other references found */
return 0;
801530e: 2300 movs r3, #0
}
8015310: 4618 mov r0, r3
8015312: 3708 adds r7, #8
8015314: 46bd mov sp, r7
8015316: bd80 pop {r7, pc}
8015318: 0801d740 .word 0x0801d740
801531c: 0801dcdc .word 0x0801dcdc
8015320: 0801d794 .word 0x0801d794
08015324 <tcp_output_segment>:
* @param pcb the tcp_pcb for the TCP connection used to send the segment
* @param netif the netif used to send the segment
*/
static err_t
tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
{
8015324: b5b0 push {r4, r5, r7, lr}
8015326: b08c sub sp, #48 ; 0x30
8015328: af04 add r7, sp, #16
801532a: 60f8 str r0, [r7, #12]
801532c: 60b9 str r1, [r7, #8]
801532e: 607a str r2, [r7, #4]
u32_t *opts;
#if TCP_CHECKSUM_ON_COPY
int seg_chksum_was_swapped = 0;
#endif
LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
8015330: 68fb ldr r3, [r7, #12]
8015332: 2b00 cmp r3, #0
8015334: d106 bne.n 8015344 <tcp_output_segment+0x20>
8015336: 4b64 ldr r3, [pc, #400] ; (80154c8 <tcp_output_segment+0x1a4>)
8015338: f44f 62b7 mov.w r2, #1464 ; 0x5b8
801533c: 4963 ldr r1, [pc, #396] ; (80154cc <tcp_output_segment+0x1a8>)
801533e: 4864 ldr r0, [pc, #400] ; (80154d0 <tcp_output_segment+0x1ac>)
8015340: f005 fe70 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
8015344: 68bb ldr r3, [r7, #8]
8015346: 2b00 cmp r3, #0
8015348: d106 bne.n 8015358 <tcp_output_segment+0x34>
801534a: 4b5f ldr r3, [pc, #380] ; (80154c8 <tcp_output_segment+0x1a4>)
801534c: f240 52b9 movw r2, #1465 ; 0x5b9
8015350: 4960 ldr r1, [pc, #384] ; (80154d4 <tcp_output_segment+0x1b0>)
8015352: 485f ldr r0, [pc, #380] ; (80154d0 <tcp_output_segment+0x1ac>)
8015354: f005 fe66 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
8015358: 687b ldr r3, [r7, #4]
801535a: 2b00 cmp r3, #0
801535c: d106 bne.n 801536c <tcp_output_segment+0x48>
801535e: 4b5a ldr r3, [pc, #360] ; (80154c8 <tcp_output_segment+0x1a4>)
8015360: f240 52ba movw r2, #1466 ; 0x5ba
8015364: 495c ldr r1, [pc, #368] ; (80154d8 <tcp_output_segment+0x1b4>)
8015366: 485a ldr r0, [pc, #360] ; (80154d0 <tcp_output_segment+0x1ac>)
8015368: f005 fe5c bl 801b024 <iprintf>
if (tcp_output_segment_busy(seg)) {
801536c: 68f8 ldr r0, [r7, #12]
801536e: f7ff ffb9 bl 80152e4 <tcp_output_segment_busy>
8015372: 4603 mov r3, r0
8015374: 2b00 cmp r3, #0
8015376: d001 beq.n 801537c <tcp_output_segment+0x58>
/* This should not happen: rexmit functions should have checked this.
However, since this function modifies p->len, we must not continue in this case. */
LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
return ERR_OK;
8015378: 2300 movs r3, #0
801537a: e0a0 b.n 80154be <tcp_output_segment+0x19a>
}
/* The TCP header has already been constructed, but the ackno and
wnd fields remain. */
seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
801537c: 68bb ldr r3, [r7, #8]
801537e: 6a5a ldr r2, [r3, #36] ; 0x24
8015380: 68fb ldr r3, [r7, #12]
8015382: 68dc ldr r4, [r3, #12]
8015384: 4610 mov r0, r2
8015386: f7f9 fd98 bl 800eeba <lwip_htonl>
801538a: 4603 mov r3, r0
801538c: 60a3 str r3, [r4, #8]
the window scale option) is never scaled. */
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
} else
#endif /* LWIP_WND_SCALE */
{
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
801538e: 68bb ldr r3, [r7, #8]
8015390: 8d5a ldrh r2, [r3, #42] ; 0x2a
8015392: 68fb ldr r3, [r7, #12]
8015394: 68dc ldr r4, [r3, #12]
8015396: 4610 mov r0, r2
8015398: f7f9 fd7a bl 800ee90 <lwip_htons>
801539c: 4603 mov r3, r0
801539e: 81e3 strh r3, [r4, #14]
}
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
80153a0: 68bb ldr r3, [r7, #8]
80153a2: 6a5b ldr r3, [r3, #36] ; 0x24
80153a4: 68ba ldr r2, [r7, #8]
80153a6: 8d52 ldrh r2, [r2, #42] ; 0x2a
80153a8: 441a add r2, r3
80153aa: 68bb ldr r3, [r7, #8]
80153ac: 62da str r2, [r3, #44] ; 0x2c
/* Add any requested options. NB MSS option is only set on SYN
packets, so ignore it here */
/* cast through void* to get rid of alignment warnings */
opts = (u32_t *)(void *)(seg->tcphdr + 1);
80153ae: 68fb ldr r3, [r7, #12]
80153b0: 68db ldr r3, [r3, #12]
80153b2: 3314 adds r3, #20
80153b4: 61fb str r3, [r7, #28]
if (seg->flags & TF_SEG_OPTS_MSS) {
80153b6: 68fb ldr r3, [r7, #12]
80153b8: 7a9b ldrb r3, [r3, #10]
80153ba: f003 0301 and.w r3, r3, #1
80153be: 2b00 cmp r3, #0
80153c0: d015 beq.n 80153ee <tcp_output_segment+0xca>
u16_t mss;
#if TCP_CALCULATE_EFF_SEND_MSS
mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
80153c2: 68bb ldr r3, [r7, #8]
80153c4: 3304 adds r3, #4
80153c6: 461a mov r2, r3
80153c8: 6879 ldr r1, [r7, #4]
80153ca: f44f 7006 mov.w r0, #536 ; 0x218
80153ce: f7fc fe8d bl 80120ec <tcp_eff_send_mss_netif>
80153d2: 4603 mov r3, r0
80153d4: 837b strh r3, [r7, #26]
#else /* TCP_CALCULATE_EFF_SEND_MSS */
mss = TCP_MSS;
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
*opts = TCP_BUILD_MSS_OPTION(mss);
80153d6: 8b7b ldrh r3, [r7, #26]
80153d8: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000
80153dc: 4618 mov r0, r3
80153de: f7f9 fd6c bl 800eeba <lwip_htonl>
80153e2: 4602 mov r2, r0
80153e4: 69fb ldr r3, [r7, #28]
80153e6: 601a str r2, [r3, #0]
opts += 1;
80153e8: 69fb ldr r3, [r7, #28]
80153ea: 3304 adds r3, #4
80153ec: 61fb str r3, [r7, #28]
}
#endif
/* Set retransmission timer running if it is not currently enabled
This must be set before checking the route. */
if (pcb->rtime < 0) {
80153ee: 68bb ldr r3, [r7, #8]
80153f0: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
80153f4: 2b00 cmp r3, #0
80153f6: da02 bge.n 80153fe <tcp_output_segment+0xda>
pcb->rtime = 0;
80153f8: 68bb ldr r3, [r7, #8]
80153fa: 2200 movs r2, #0
80153fc: 861a strh r2, [r3, #48] ; 0x30
}
if (pcb->rttest == 0) {
80153fe: 68bb ldr r3, [r7, #8]
8015400: 6b5b ldr r3, [r3, #52] ; 0x34
8015402: 2b00 cmp r3, #0
8015404: d10c bne.n 8015420 <tcp_output_segment+0xfc>
pcb->rttest = tcp_ticks;
8015406: 4b35 ldr r3, [pc, #212] ; (80154dc <tcp_output_segment+0x1b8>)
8015408: 681a ldr r2, [r3, #0]
801540a: 68bb ldr r3, [r7, #8]
801540c: 635a str r2, [r3, #52] ; 0x34
pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
801540e: 68fb ldr r3, [r7, #12]
8015410: 68db ldr r3, [r3, #12]
8015412: 685b ldr r3, [r3, #4]
8015414: 4618 mov r0, r3
8015416: f7f9 fd50 bl 800eeba <lwip_htonl>
801541a: 4602 mov r2, r0
801541c: 68bb ldr r3, [r7, #8]
801541e: 639a str r2, [r3, #56] ; 0x38
}
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
seg->len));
len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
8015420: 68fb ldr r3, [r7, #12]
8015422: 68db ldr r3, [r3, #12]
8015424: 461a mov r2, r3
8015426: 68fb ldr r3, [r7, #12]
8015428: 685b ldr r3, [r3, #4]
801542a: 685b ldr r3, [r3, #4]
801542c: 1ad3 subs r3, r2, r3
801542e: 833b strh r3, [r7, #24]
if (len == 0) {
/** Exclude retransmitted segments from this count. */
MIB2_STATS_INC(mib2.tcpoutsegs);
}
seg->p->len -= len;
8015430: 68fb ldr r3, [r7, #12]
8015432: 685b ldr r3, [r3, #4]
8015434: 8959 ldrh r1, [r3, #10]
8015436: 68fb ldr r3, [r7, #12]
8015438: 685b ldr r3, [r3, #4]
801543a: 8b3a ldrh r2, [r7, #24]
801543c: 1a8a subs r2, r1, r2
801543e: b292 uxth r2, r2
8015440: 815a strh r2, [r3, #10]
seg->p->tot_len -= len;
8015442: 68fb ldr r3, [r7, #12]
8015444: 685b ldr r3, [r3, #4]
8015446: 8919 ldrh r1, [r3, #8]
8015448: 68fb ldr r3, [r7, #12]
801544a: 685b ldr r3, [r3, #4]
801544c: 8b3a ldrh r2, [r7, #24]
801544e: 1a8a subs r2, r1, r2
8015450: b292 uxth r2, r2
8015452: 811a strh r2, [r3, #8]
seg->p->payload = seg->tcphdr;
8015454: 68fb ldr r3, [r7, #12]
8015456: 685b ldr r3, [r3, #4]
8015458: 68fa ldr r2, [r7, #12]
801545a: 68d2 ldr r2, [r2, #12]
801545c: 605a str r2, [r3, #4]
seg->tcphdr->chksum = 0;
801545e: 68fb ldr r3, [r7, #12]
8015460: 68db ldr r3, [r3, #12]
8015462: 2200 movs r2, #0
8015464: 741a strb r2, [r3, #16]
8015466: 2200 movs r2, #0
8015468: 745a strb r2, [r3, #17]
#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
#endif
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
801546a: 68fb ldr r3, [r7, #12]
801546c: 68db ldr r3, [r3, #12]
801546e: f103 0214 add.w r2, r3, #20
8015472: 68fb ldr r3, [r7, #12]
8015474: 7a9b ldrb r3, [r3, #10]
8015476: 009b lsls r3, r3, #2
8015478: f003 0304 and.w r3, r3, #4
801547c: 4413 add r3, r2
801547e: 69fa ldr r2, [r7, #28]
8015480: 429a cmp r2, r3
8015482: d006 beq.n 8015492 <tcp_output_segment+0x16e>
8015484: 4b10 ldr r3, [pc, #64] ; (80154c8 <tcp_output_segment+0x1a4>)
8015486: f240 621c movw r2, #1564 ; 0x61c
801548a: 4915 ldr r1, [pc, #84] ; (80154e0 <tcp_output_segment+0x1bc>)
801548c: 4810 ldr r0, [pc, #64] ; (80154d0 <tcp_output_segment+0x1ac>)
801548e: f005 fdc9 bl 801b024 <iprintf>
}
#endif /* CHECKSUM_GEN_TCP */
TCP_STATS_INC(tcp.xmit);
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
8015492: 68fb ldr r3, [r7, #12]
8015494: 6858 ldr r0, [r3, #4]
8015496: 68b9 ldr r1, [r7, #8]
8015498: 68bb ldr r3, [r7, #8]
801549a: 1d1c adds r4, r3, #4
801549c: 68bb ldr r3, [r7, #8]
801549e: 7add ldrb r5, [r3, #11]
80154a0: 68bb ldr r3, [r7, #8]
80154a2: 7a9b ldrb r3, [r3, #10]
80154a4: 687a ldr r2, [r7, #4]
80154a6: 9202 str r2, [sp, #8]
80154a8: 2206 movs r2, #6
80154aa: 9201 str r2, [sp, #4]
80154ac: 9300 str r3, [sp, #0]
80154ae: 462b mov r3, r5
80154b0: 4622 mov r2, r4
80154b2: f004 fc37 bl 8019d24 <ip4_output_if>
80154b6: 4603 mov r3, r0
80154b8: 75fb strb r3, [r7, #23]
seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
seg->chksum_swapped = 1;
}
#endif
return err;
80154ba: f997 3017 ldrsb.w r3, [r7, #23]
}
80154be: 4618 mov r0, r3
80154c0: 3720 adds r7, #32
80154c2: 46bd mov sp, r7
80154c4: bdb0 pop {r4, r5, r7, pc}
80154c6: bf00 nop
80154c8: 0801d740 .word 0x0801d740
80154cc: 0801dd04 .word 0x0801dd04
80154d0: 0801d794 .word 0x0801d794
80154d4: 0801dd24 .word 0x0801dd24
80154d8: 0801dd44 .word 0x0801dd44
80154dc: 2000f5c4 .word 0x2000f5c4
80154e0: 0801dd68 .word 0x0801dd68
080154e4 <tcp_rexmit_rto_prepare>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
err_t
tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
{
80154e4: b5b0 push {r4, r5, r7, lr}
80154e6: b084 sub sp, #16
80154e8: af00 add r7, sp, #0
80154ea: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
80154ec: 687b ldr r3, [r7, #4]
80154ee: 2b00 cmp r3, #0
80154f0: d106 bne.n 8015500 <tcp_rexmit_rto_prepare+0x1c>
80154f2: 4b31 ldr r3, [pc, #196] ; (80155b8 <tcp_rexmit_rto_prepare+0xd4>)
80154f4: f240 6263 movw r2, #1635 ; 0x663
80154f8: 4930 ldr r1, [pc, #192] ; (80155bc <tcp_rexmit_rto_prepare+0xd8>)
80154fa: 4831 ldr r0, [pc, #196] ; (80155c0 <tcp_rexmit_rto_prepare+0xdc>)
80154fc: f005 fd92 bl 801b024 <iprintf>
if (pcb->unacked == NULL) {
8015500: 687b ldr r3, [r7, #4]
8015502: 6f1b ldr r3, [r3, #112] ; 0x70
8015504: 2b00 cmp r3, #0
8015506: d102 bne.n 801550e <tcp_rexmit_rto_prepare+0x2a>
return ERR_VAL;
8015508: f06f 0305 mvn.w r3, #5
801550c: e050 b.n 80155b0 <tcp_rexmit_rto_prepare+0xcc>
/* Move all unacked segments to the head of the unsent queue.
However, give up if any of the unsent pbufs are still referenced by the
netif driver due to deferred transmission. No point loading the link further
if it is struggling to flush its buffered writes. */
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
801550e: 687b ldr r3, [r7, #4]
8015510: 6f1b ldr r3, [r3, #112] ; 0x70
8015512: 60fb str r3, [r7, #12]
8015514: e00b b.n 801552e <tcp_rexmit_rto_prepare+0x4a>
if (tcp_output_segment_busy(seg)) {
8015516: 68f8 ldr r0, [r7, #12]
8015518: f7ff fee4 bl 80152e4 <tcp_output_segment_busy>
801551c: 4603 mov r3, r0
801551e: 2b00 cmp r3, #0
8015520: d002 beq.n 8015528 <tcp_rexmit_rto_prepare+0x44>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
8015522: f06f 0305 mvn.w r3, #5
8015526: e043 b.n 80155b0 <tcp_rexmit_rto_prepare+0xcc>
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
8015528: 68fb ldr r3, [r7, #12]
801552a: 681b ldr r3, [r3, #0]
801552c: 60fb str r3, [r7, #12]
801552e: 68fb ldr r3, [r7, #12]
8015530: 681b ldr r3, [r3, #0]
8015532: 2b00 cmp r3, #0
8015534: d1ef bne.n 8015516 <tcp_rexmit_rto_prepare+0x32>
}
}
if (tcp_output_segment_busy(seg)) {
8015536: 68f8 ldr r0, [r7, #12]
8015538: f7ff fed4 bl 80152e4 <tcp_output_segment_busy>
801553c: 4603 mov r3, r0
801553e: 2b00 cmp r3, #0
8015540: d002 beq.n 8015548 <tcp_rexmit_rto_prepare+0x64>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
return ERR_VAL;
8015542: f06f 0305 mvn.w r3, #5
8015546: e033 b.n 80155b0 <tcp_rexmit_rto_prepare+0xcc>
}
/* concatenate unsent queue after unacked queue */
seg->next = pcb->unsent;
8015548: 687b ldr r3, [r7, #4]
801554a: 6eda ldr r2, [r3, #108] ; 0x6c
801554c: 68fb ldr r3, [r7, #12]
801554e: 601a str r2, [r3, #0]
if (pcb->unsent == NULL) {
pcb->unsent_oversize = seg->oversize_left;
}
#endif /* TCP_OVERSIZE_DBGCHECK */
/* unsent queue is the concatenated queue (of unacked, unsent) */
pcb->unsent = pcb->unacked;
8015550: 687b ldr r3, [r7, #4]
8015552: 6f1a ldr r2, [r3, #112] ; 0x70
8015554: 687b ldr r3, [r7, #4]
8015556: 66da str r2, [r3, #108] ; 0x6c
/* unacked queue is now empty */
pcb->unacked = NULL;
8015558: 687b ldr r3, [r7, #4]
801555a: 2200 movs r2, #0
801555c: 671a str r2, [r3, #112] ; 0x70
/* Mark RTO in-progress */
tcp_set_flags(pcb, TF_RTO);
801555e: 687b ldr r3, [r7, #4]
8015560: 8b5b ldrh r3, [r3, #26]
8015562: f443 6300 orr.w r3, r3, #2048 ; 0x800
8015566: b29a uxth r2, r3
8015568: 687b ldr r3, [r7, #4]
801556a: 835a strh r2, [r3, #26]
/* Record the next byte following retransmit */
pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
801556c: 68fb ldr r3, [r7, #12]
801556e: 68db ldr r3, [r3, #12]
8015570: 685b ldr r3, [r3, #4]
8015572: 4618 mov r0, r3
8015574: f7f9 fca1 bl 800eeba <lwip_htonl>
8015578: 4604 mov r4, r0
801557a: 68fb ldr r3, [r7, #12]
801557c: 891b ldrh r3, [r3, #8]
801557e: 461d mov r5, r3
8015580: 68fb ldr r3, [r7, #12]
8015582: 68db ldr r3, [r3, #12]
8015584: 899b ldrh r3, [r3, #12]
8015586: b29b uxth r3, r3
8015588: 4618 mov r0, r3
801558a: f7f9 fc81 bl 800ee90 <lwip_htons>
801558e: 4603 mov r3, r0
8015590: b2db uxtb r3, r3
8015592: f003 0303 and.w r3, r3, #3
8015596: 2b00 cmp r3, #0
8015598: d001 beq.n 801559e <tcp_rexmit_rto_prepare+0xba>
801559a: 2301 movs r3, #1
801559c: e000 b.n 80155a0 <tcp_rexmit_rto_prepare+0xbc>
801559e: 2300 movs r3, #0
80155a0: 442b add r3, r5
80155a2: 18e2 adds r2, r4, r3
80155a4: 687b ldr r3, [r7, #4]
80155a6: 64da str r2, [r3, #76] ; 0x4c
/* Don't take any RTT measurements after retransmitting. */
pcb->rttest = 0;
80155a8: 687b ldr r3, [r7, #4]
80155aa: 2200 movs r2, #0
80155ac: 635a str r2, [r3, #52] ; 0x34
return ERR_OK;
80155ae: 2300 movs r3, #0
}
80155b0: 4618 mov r0, r3
80155b2: 3710 adds r7, #16
80155b4: 46bd mov sp, r7
80155b6: bdb0 pop {r4, r5, r7, pc}
80155b8: 0801d740 .word 0x0801d740
80155bc: 0801dd7c .word 0x0801dd7c
80155c0: 0801d794 .word 0x0801d794
080155c4 <tcp_rexmit_rto_commit>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
{
80155c4: b580 push {r7, lr}
80155c6: b082 sub sp, #8
80155c8: af00 add r7, sp, #0
80155ca: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
80155cc: 687b ldr r3, [r7, #4]
80155ce: 2b00 cmp r3, #0
80155d0: d106 bne.n 80155e0 <tcp_rexmit_rto_commit+0x1c>
80155d2: 4b0d ldr r3, [pc, #52] ; (8015608 <tcp_rexmit_rto_commit+0x44>)
80155d4: f44f 62d3 mov.w r2, #1688 ; 0x698
80155d8: 490c ldr r1, [pc, #48] ; (801560c <tcp_rexmit_rto_commit+0x48>)
80155da: 480d ldr r0, [pc, #52] ; (8015610 <tcp_rexmit_rto_commit+0x4c>)
80155dc: f005 fd22 bl 801b024 <iprintf>
/* increment number of retransmissions */
if (pcb->nrtx < 0xFF) {
80155e0: 687b ldr r3, [r7, #4]
80155e2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155e6: 2bff cmp r3, #255 ; 0xff
80155e8: d007 beq.n 80155fa <tcp_rexmit_rto_commit+0x36>
++pcb->nrtx;
80155ea: 687b ldr r3, [r7, #4]
80155ec: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
80155f0: 3301 adds r3, #1
80155f2: b2da uxtb r2, r3
80155f4: 687b ldr r3, [r7, #4]
80155f6: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Do the actual retransmission */
tcp_output(pcb);
80155fa: 6878 ldr r0, [r7, #4]
80155fc: f7ff fc7a bl 8014ef4 <tcp_output>
}
8015600: bf00 nop
8015602: 3708 adds r7, #8
8015604: 46bd mov sp, r7
8015606: bd80 pop {r7, pc}
8015608: 0801d740 .word 0x0801d740
801560c: 0801dda0 .word 0x0801dda0
8015610: 0801d794 .word 0x0801d794
08015614 <tcp_rexmit_rto>:
*
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
*/
void
tcp_rexmit_rto(struct tcp_pcb *pcb)
{
8015614: b580 push {r7, lr}
8015616: b082 sub sp, #8
8015618: af00 add r7, sp, #0
801561a: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
801561c: 687b ldr r3, [r7, #4]
801561e: 2b00 cmp r3, #0
8015620: d106 bne.n 8015630 <tcp_rexmit_rto+0x1c>
8015622: 4b0a ldr r3, [pc, #40] ; (801564c <tcp_rexmit_rto+0x38>)
8015624: f240 62ad movw r2, #1709 ; 0x6ad
8015628: 4909 ldr r1, [pc, #36] ; (8015650 <tcp_rexmit_rto+0x3c>)
801562a: 480a ldr r0, [pc, #40] ; (8015654 <tcp_rexmit_rto+0x40>)
801562c: f005 fcfa bl 801b024 <iprintf>
if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
8015630: 6878 ldr r0, [r7, #4]
8015632: f7ff ff57 bl 80154e4 <tcp_rexmit_rto_prepare>
8015636: 4603 mov r3, r0
8015638: 2b00 cmp r3, #0
801563a: d102 bne.n 8015642 <tcp_rexmit_rto+0x2e>
tcp_rexmit_rto_commit(pcb);
801563c: 6878 ldr r0, [r7, #4]
801563e: f7ff ffc1 bl 80155c4 <tcp_rexmit_rto_commit>
}
}
8015642: bf00 nop
8015644: 3708 adds r7, #8
8015646: 46bd mov sp, r7
8015648: bd80 pop {r7, pc}
801564a: bf00 nop
801564c: 0801d740 .word 0x0801d740
8015650: 0801ddc4 .word 0x0801ddc4
8015654: 0801d794 .word 0x0801d794
08015658 <tcp_rexmit>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
err_t
tcp_rexmit(struct tcp_pcb *pcb)
{
8015658: b590 push {r4, r7, lr}
801565a: b085 sub sp, #20
801565c: af00 add r7, sp, #0
801565e: 6078 str r0, [r7, #4]
struct tcp_seg *seg;
struct tcp_seg **cur_seg;
LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
8015660: 687b ldr r3, [r7, #4]
8015662: 2b00 cmp r3, #0
8015664: d106 bne.n 8015674 <tcp_rexmit+0x1c>
8015666: 4b2f ldr r3, [pc, #188] ; (8015724 <tcp_rexmit+0xcc>)
8015668: f240 62c1 movw r2, #1729 ; 0x6c1
801566c: 492e ldr r1, [pc, #184] ; (8015728 <tcp_rexmit+0xd0>)
801566e: 482f ldr r0, [pc, #188] ; (801572c <tcp_rexmit+0xd4>)
8015670: f005 fcd8 bl 801b024 <iprintf>
if (pcb->unacked == NULL) {
8015674: 687b ldr r3, [r7, #4]
8015676: 6f1b ldr r3, [r3, #112] ; 0x70
8015678: 2b00 cmp r3, #0
801567a: d102 bne.n 8015682 <tcp_rexmit+0x2a>
return ERR_VAL;
801567c: f06f 0305 mvn.w r3, #5
8015680: e04c b.n 801571c <tcp_rexmit+0xc4>
}
seg = pcb->unacked;
8015682: 687b ldr r3, [r7, #4]
8015684: 6f1b ldr r3, [r3, #112] ; 0x70
8015686: 60bb str r3, [r7, #8]
/* Give up if the segment is still referenced by the netif driver
due to deferred transmission. */
if (tcp_output_segment_busy(seg)) {
8015688: 68b8 ldr r0, [r7, #8]
801568a: f7ff fe2b bl 80152e4 <tcp_output_segment_busy>
801568e: 4603 mov r3, r0
8015690: 2b00 cmp r3, #0
8015692: d002 beq.n 801569a <tcp_rexmit+0x42>
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
return ERR_VAL;
8015694: f06f 0305 mvn.w r3, #5
8015698: e040 b.n 801571c <tcp_rexmit+0xc4>
}
/* Move the first unacked segment to the unsent queue */
/* Keep the unsent queue sorted. */
pcb->unacked = seg->next;
801569a: 68bb ldr r3, [r7, #8]
801569c: 681a ldr r2, [r3, #0]
801569e: 687b ldr r3, [r7, #4]
80156a0: 671a str r2, [r3, #112] ; 0x70
cur_seg = &(pcb->unsent);
80156a2: 687b ldr r3, [r7, #4]
80156a4: 336c adds r3, #108 ; 0x6c
80156a6: 60fb str r3, [r7, #12]
while (*cur_seg &&
80156a8: e002 b.n 80156b0 <tcp_rexmit+0x58>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
cur_seg = &((*cur_seg)->next );
80156aa: 68fb ldr r3, [r7, #12]
80156ac: 681b ldr r3, [r3, #0]
80156ae: 60fb str r3, [r7, #12]
while (*cur_seg &&
80156b0: 68fb ldr r3, [r7, #12]
80156b2: 681b ldr r3, [r3, #0]
80156b4: 2b00 cmp r3, #0
80156b6: d011 beq.n 80156dc <tcp_rexmit+0x84>
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
80156b8: 68fb ldr r3, [r7, #12]
80156ba: 681b ldr r3, [r3, #0]
80156bc: 68db ldr r3, [r3, #12]
80156be: 685b ldr r3, [r3, #4]
80156c0: 4618 mov r0, r3
80156c2: f7f9 fbfa bl 800eeba <lwip_htonl>
80156c6: 4604 mov r4, r0
80156c8: 68bb ldr r3, [r7, #8]
80156ca: 68db ldr r3, [r3, #12]
80156cc: 685b ldr r3, [r3, #4]
80156ce: 4618 mov r0, r3
80156d0: f7f9 fbf3 bl 800eeba <lwip_htonl>
80156d4: 4603 mov r3, r0
80156d6: 1ae3 subs r3, r4, r3
while (*cur_seg &&
80156d8: 2b00 cmp r3, #0
80156da: dbe6 blt.n 80156aa <tcp_rexmit+0x52>
}
seg->next = *cur_seg;
80156dc: 68fb ldr r3, [r7, #12]
80156de: 681a ldr r2, [r3, #0]
80156e0: 68bb ldr r3, [r7, #8]
80156e2: 601a str r2, [r3, #0]
*cur_seg = seg;
80156e4: 68fb ldr r3, [r7, #12]
80156e6: 68ba ldr r2, [r7, #8]
80156e8: 601a str r2, [r3, #0]
#if TCP_OVERSIZE
if (seg->next == NULL) {
80156ea: 68bb ldr r3, [r7, #8]
80156ec: 681b ldr r3, [r3, #0]
80156ee: 2b00 cmp r3, #0
80156f0: d103 bne.n 80156fa <tcp_rexmit+0xa2>
/* the retransmitted segment is last in unsent, so reset unsent_oversize */
pcb->unsent_oversize = 0;
80156f2: 687b ldr r3, [r7, #4]
80156f4: 2200 movs r2, #0
80156f6: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
}
#endif /* TCP_OVERSIZE */
if (pcb->nrtx < 0xFF) {
80156fa: 687b ldr r3, [r7, #4]
80156fc: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
8015700: 2bff cmp r3, #255 ; 0xff
8015702: d007 beq.n 8015714 <tcp_rexmit+0xbc>
++pcb->nrtx;
8015704: 687b ldr r3, [r7, #4]
8015706: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
801570a: 3301 adds r3, #1
801570c: b2da uxtb r2, r3
801570e: 687b ldr r3, [r7, #4]
8015710: f883 2042 strb.w r2, [r3, #66] ; 0x42
}
/* Don't take any rtt measurements after retransmitting. */
pcb->rttest = 0;
8015714: 687b ldr r3, [r7, #4]
8015716: 2200 movs r2, #0
8015718: 635a str r2, [r3, #52] ; 0x34
/* Do the actual retransmission. */
MIB2_STATS_INC(mib2.tcpretranssegs);
/* No need to call tcp_output: we are always called from tcp_input()
and thus tcp_output directly returns. */
return ERR_OK;
801571a: 2300 movs r3, #0
}
801571c: 4618 mov r0, r3
801571e: 3714 adds r7, #20
8015720: 46bd mov sp, r7
8015722: bd90 pop {r4, r7, pc}
8015724: 0801d740 .word 0x0801d740
8015728: 0801dde0 .word 0x0801dde0
801572c: 0801d794 .word 0x0801d794
08015730 <tcp_rexmit_fast>:
*
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
*/
void
tcp_rexmit_fast(struct tcp_pcb *pcb)
{
8015730: b580 push {r7, lr}
8015732: b082 sub sp, #8
8015734: af00 add r7, sp, #0
8015736: 6078 str r0, [r7, #4]
LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
8015738: 687b ldr r3, [r7, #4]
801573a: 2b00 cmp r3, #0
801573c: d106 bne.n 801574c <tcp_rexmit_fast+0x1c>
801573e: 4b2f ldr r3, [pc, #188] ; (80157fc <tcp_rexmit_fast+0xcc>)
8015740: f240 62f9 movw r2, #1785 ; 0x6f9
8015744: 492e ldr r1, [pc, #184] ; (8015800 <tcp_rexmit_fast+0xd0>)
8015746: 482f ldr r0, [pc, #188] ; (8015804 <tcp_rexmit_fast+0xd4>)
8015748: f005 fc6c bl 801b024 <iprintf>
if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
801574c: 687b ldr r3, [r7, #4]
801574e: 6f1b ldr r3, [r3, #112] ; 0x70
8015750: 2b00 cmp r3, #0
8015752: d04f beq.n 80157f4 <tcp_rexmit_fast+0xc4>
8015754: 687b ldr r3, [r7, #4]
8015756: 8b5b ldrh r3, [r3, #26]
8015758: f003 0304 and.w r3, r3, #4
801575c: 2b00 cmp r3, #0
801575e: d149 bne.n 80157f4 <tcp_rexmit_fast+0xc4>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: dupacks %"U16_F" (%"U32_F
"), fast retransmit %"U32_F"\n",
(u16_t)pcb->dupacks, pcb->lastack,
lwip_ntohl(pcb->unacked->tcphdr->seqno)));
if (tcp_rexmit(pcb) == ERR_OK) {
8015760: 6878 ldr r0, [r7, #4]
8015762: f7ff ff79 bl 8015658 <tcp_rexmit>
8015766: 4603 mov r3, r0
8015768: 2b00 cmp r3, #0
801576a: d143 bne.n 80157f4 <tcp_rexmit_fast+0xc4>
/* Set ssthresh to half of the minimum of the current
* cwnd and the advertised window */
pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
801576c: 687b ldr r3, [r7, #4]
801576e: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
8015772: 687b ldr r3, [r7, #4]
8015774: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8015778: 429a cmp r2, r3
801577a: d208 bcs.n 801578e <tcp_rexmit_fast+0x5e>
801577c: 687b ldr r3, [r7, #4]
801577e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
8015782: 2b00 cmp r3, #0
8015784: da00 bge.n 8015788 <tcp_rexmit_fast+0x58>
8015786: 3301 adds r3, #1
8015788: 105b asrs r3, r3, #1
801578a: b29b uxth r3, r3
801578c: e007 b.n 801579e <tcp_rexmit_fast+0x6e>
801578e: 687b ldr r3, [r7, #4]
8015790: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
8015794: 2b00 cmp r3, #0
8015796: da00 bge.n 801579a <tcp_rexmit_fast+0x6a>
8015798: 3301 adds r3, #1
801579a: 105b asrs r3, r3, #1
801579c: b29b uxth r3, r3
801579e: 687a ldr r2, [r7, #4]
80157a0: f8a2 304a strh.w r3, [r2, #74] ; 0x4a
/* The minimum value for ssthresh should be 2 MSS */
if (pcb->ssthresh < (2U * pcb->mss)) {
80157a4: 687b ldr r3, [r7, #4]
80157a6: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
80157aa: 461a mov r2, r3
80157ac: 687b ldr r3, [r7, #4]
80157ae: 8e5b ldrh r3, [r3, #50] ; 0x32
80157b0: 005b lsls r3, r3, #1
80157b2: 429a cmp r2, r3
80157b4: d206 bcs.n 80157c4 <tcp_rexmit_fast+0x94>
LWIP_DEBUGF(TCP_FR_DEBUG,
("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
" should be min 2 mss %"U16_F"...\n",
pcb->ssthresh, (u16_t)(2 * pcb->mss)));
pcb->ssthresh = 2 * pcb->mss;
80157b6: 687b ldr r3, [r7, #4]
80157b8: 8e5b ldrh r3, [r3, #50] ; 0x32
80157ba: 005b lsls r3, r3, #1
80157bc: b29a uxth r2, r3
80157be: 687b ldr r3, [r7, #4]
80157c0: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
}
pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
80157c4: 687b ldr r3, [r7, #4]
80157c6: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
80157ca: 687b ldr r3, [r7, #4]
80157cc: 8e5b ldrh r3, [r3, #50] ; 0x32
80157ce: 4619 mov r1, r3
80157d0: 0049 lsls r1, r1, #1
80157d2: 440b add r3, r1
80157d4: b29b uxth r3, r3
80157d6: 4413 add r3, r2
80157d8: b29a uxth r2, r3
80157da: 687b ldr r3, [r7, #4]
80157dc: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
tcp_set_flags(pcb, TF_INFR);
80157e0: 687b ldr r3, [r7, #4]
80157e2: 8b5b ldrh r3, [r3, #26]
80157e4: f043 0304 orr.w r3, r3, #4
80157e8: b29a uxth r2, r3
80157ea: 687b ldr r3, [r7, #4]
80157ec: 835a strh r2, [r3, #26]
/* Reset the retransmission timer to prevent immediate rto retransmissions */
pcb->rtime = 0;
80157ee: 687b ldr r3, [r7, #4]
80157f0: 2200 movs r2, #0
80157f2: 861a strh r2, [r3, #48] ; 0x30
}
}
}
80157f4: bf00 nop
80157f6: 3708 adds r7, #8
80157f8: 46bd mov sp, r7
80157fa: bd80 pop {r7, pc}
80157fc: 0801d740 .word 0x0801d740
8015800: 0801ddf8 .word 0x0801ddf8
8015804: 0801d794 .word 0x0801d794
08015808 <tcp_output_alloc_header_common>:
static struct pbuf *
tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */,
u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
{
8015808: b580 push {r7, lr}
801580a: b086 sub sp, #24
801580c: af00 add r7, sp, #0
801580e: 60f8 str r0, [r7, #12]
8015810: 607b str r3, [r7, #4]
8015812: 460b mov r3, r1
8015814: 817b strh r3, [r7, #10]
8015816: 4613 mov r3, r2
8015818: 813b strh r3, [r7, #8]
struct tcp_hdr *tcphdr;
struct pbuf *p;
p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
801581a: 897a ldrh r2, [r7, #10]
801581c: 893b ldrh r3, [r7, #8]
801581e: 4413 add r3, r2
8015820: b29b uxth r3, r3
8015822: 3314 adds r3, #20
8015824: b29b uxth r3, r3
8015826: f44f 7220 mov.w r2, #640 ; 0x280
801582a: 4619 mov r1, r3
801582c: 2022 movs r0, #34 ; 0x22
801582e: f7fa fc03 bl 8010038 <pbuf_alloc>
8015832: 6178 str r0, [r7, #20]
if (p != NULL) {
8015834: 697b ldr r3, [r7, #20]
8015836: 2b00 cmp r3, #0
8015838: d04e beq.n 80158d8 <tcp_output_alloc_header_common+0xd0>
LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
801583a: 697b ldr r3, [r7, #20]
801583c: 895b ldrh r3, [r3, #10]
801583e: 461a mov r2, r3
8015840: 897b ldrh r3, [r7, #10]
8015842: 3314 adds r3, #20
8015844: 429a cmp r2, r3
8015846: da06 bge.n 8015856 <tcp_output_alloc_header_common+0x4e>
8015848: 4b26 ldr r3, [pc, #152] ; (80158e4 <tcp_output_alloc_header_common+0xdc>)
801584a: f240 7224 movw r2, #1828 ; 0x724
801584e: 4926 ldr r1, [pc, #152] ; (80158e8 <tcp_output_alloc_header_common+0xe0>)
8015850: 4826 ldr r0, [pc, #152] ; (80158ec <tcp_output_alloc_header_common+0xe4>)
8015852: f005 fbe7 bl 801b024 <iprintf>
(p->len >= TCP_HLEN + optlen));
tcphdr = (struct tcp_hdr *)p->payload;
8015856: 697b ldr r3, [r7, #20]
8015858: 685b ldr r3, [r3, #4]
801585a: 613b str r3, [r7, #16]
tcphdr->src = lwip_htons(src_port);
801585c: 8c3b ldrh r3, [r7, #32]
801585e: 4618 mov r0, r3
8015860: f7f9 fb16 bl 800ee90 <lwip_htons>
8015864: 4603 mov r3, r0
8015866: 461a mov r2, r3
8015868: 693b ldr r3, [r7, #16]
801586a: 801a strh r2, [r3, #0]
tcphdr->dest = lwip_htons(dst_port);
801586c: 8cbb ldrh r3, [r7, #36] ; 0x24
801586e: 4618 mov r0, r3
8015870: f7f9 fb0e bl 800ee90 <lwip_htons>
8015874: 4603 mov r3, r0
8015876: 461a mov r2, r3
8015878: 693b ldr r3, [r7, #16]
801587a: 805a strh r2, [r3, #2]
tcphdr->seqno = seqno_be;
801587c: 693b ldr r3, [r7, #16]
801587e: 687a ldr r2, [r7, #4]
8015880: 605a str r2, [r3, #4]
tcphdr->ackno = lwip_htonl(ackno);
8015882: 68f8 ldr r0, [r7, #12]
8015884: f7f9 fb19 bl 800eeba <lwip_htonl>
8015888: 4602 mov r2, r0
801588a: 693b ldr r3, [r7, #16]
801588c: 609a str r2, [r3, #8]
TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
801588e: 897b ldrh r3, [r7, #10]
8015890: 089b lsrs r3, r3, #2
8015892: b29b uxth r3, r3
8015894: 3305 adds r3, #5
8015896: b29b uxth r3, r3
8015898: 031b lsls r3, r3, #12
801589a: b29a uxth r2, r3
801589c: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
80158a0: b29b uxth r3, r3
80158a2: 4313 orrs r3, r2
80158a4: b29b uxth r3, r3
80158a6: 4618 mov r0, r3
80158a8: f7f9 faf2 bl 800ee90 <lwip_htons>
80158ac: 4603 mov r3, r0
80158ae: 461a mov r2, r3
80158b0: 693b ldr r3, [r7, #16]
80158b2: 819a strh r2, [r3, #12]
tcphdr->wnd = lwip_htons(wnd);
80158b4: 8dbb ldrh r3, [r7, #44] ; 0x2c
80158b6: 4618 mov r0, r3
80158b8: f7f9 faea bl 800ee90 <lwip_htons>
80158bc: 4603 mov r3, r0
80158be: 461a mov r2, r3
80158c0: 693b ldr r3, [r7, #16]
80158c2: 81da strh r2, [r3, #14]
tcphdr->chksum = 0;
80158c4: 693b ldr r3, [r7, #16]
80158c6: 2200 movs r2, #0
80158c8: 741a strb r2, [r3, #16]
80158ca: 2200 movs r2, #0
80158cc: 745a strb r2, [r3, #17]
tcphdr->urgp = 0;
80158ce: 693b ldr r3, [r7, #16]
80158d0: 2200 movs r2, #0
80158d2: 749a strb r2, [r3, #18]
80158d4: 2200 movs r2, #0
80158d6: 74da strb r2, [r3, #19]
}
return p;
80158d8: 697b ldr r3, [r7, #20]
}
80158da: 4618 mov r0, r3
80158dc: 3718 adds r7, #24
80158de: 46bd mov sp, r7
80158e0: bd80 pop {r7, pc}
80158e2: bf00 nop
80158e4: 0801d740 .word 0x0801d740
80158e8: 0801de18 .word 0x0801de18
80158ec: 0801d794 .word 0x0801d794
080158f0 <tcp_output_alloc_header>:
* @return pbuf with p->payload being the tcp_hdr
*/
static struct pbuf *
tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
u32_t seqno_be /* already in network byte order */)
{
80158f0: b5b0 push {r4, r5, r7, lr}
80158f2: b08a sub sp, #40 ; 0x28
80158f4: af04 add r7, sp, #16
80158f6: 60f8 str r0, [r7, #12]
80158f8: 607b str r3, [r7, #4]
80158fa: 460b mov r3, r1
80158fc: 817b strh r3, [r7, #10]
80158fe: 4613 mov r3, r2
8015900: 813b strh r3, [r7, #8]
struct pbuf *p;
LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
8015902: 68fb ldr r3, [r7, #12]
8015904: 2b00 cmp r3, #0
8015906: d106 bne.n 8015916 <tcp_output_alloc_header+0x26>
8015908: 4b15 ldr r3, [pc, #84] ; (8015960 <tcp_output_alloc_header+0x70>)
801590a: f240 7242 movw r2, #1858 ; 0x742
801590e: 4915 ldr r1, [pc, #84] ; (8015964 <tcp_output_alloc_header+0x74>)
8015910: 4815 ldr r0, [pc, #84] ; (8015968 <tcp_output_alloc_header+0x78>)
8015912: f005 fb87 bl 801b024 <iprintf>
p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
8015916: 68fb ldr r3, [r7, #12]
8015918: 6a58 ldr r0, [r3, #36] ; 0x24
801591a: 68fb ldr r3, [r7, #12]
801591c: 8adb ldrh r3, [r3, #22]
801591e: 68fa ldr r2, [r7, #12]
8015920: 8b12 ldrh r2, [r2, #24]
8015922: 68f9 ldr r1, [r7, #12]
8015924: 8d49 ldrh r1, [r1, #42] ; 0x2a
8015926: 893d ldrh r5, [r7, #8]
8015928: 897c ldrh r4, [r7, #10]
801592a: 9103 str r1, [sp, #12]
801592c: 2110 movs r1, #16
801592e: 9102 str r1, [sp, #8]
8015930: 9201 str r2, [sp, #4]
8015932: 9300 str r3, [sp, #0]
8015934: 687b ldr r3, [r7, #4]
8015936: 462a mov r2, r5
8015938: 4621 mov r1, r4
801593a: f7ff ff65 bl 8015808 <tcp_output_alloc_header_common>
801593e: 6178 str r0, [r7, #20]
seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
if (p != NULL) {
8015940: 697b ldr r3, [r7, #20]
8015942: 2b00 cmp r3, #0
8015944: d006 beq.n 8015954 <tcp_output_alloc_header+0x64>
/* If we're sending a packet, update the announced right window edge */
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
8015946: 68fb ldr r3, [r7, #12]
8015948: 6a5b ldr r3, [r3, #36] ; 0x24
801594a: 68fa ldr r2, [r7, #12]
801594c: 8d52 ldrh r2, [r2, #42] ; 0x2a
801594e: 441a add r2, r3
8015950: 68fb ldr r3, [r7, #12]
8015952: 62da str r2, [r3, #44] ; 0x2c
}
return p;
8015954: 697b ldr r3, [r7, #20]
}
8015956: 4618 mov r0, r3
8015958: 3718 adds r7, #24
801595a: 46bd mov sp, r7
801595c: bdb0 pop {r4, r5, r7, pc}
801595e: bf00 nop
8015960: 0801d740 .word 0x0801d740
8015964: 0801de48 .word 0x0801de48
8015968: 0801d794 .word 0x0801d794
0801596c <tcp_output_fill_options>:
/* Fill in options for control segments */
static void
tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
{
801596c: b580 push {r7, lr}
801596e: b088 sub sp, #32
8015970: af00 add r7, sp, #0
8015972: 60f8 str r0, [r7, #12]
8015974: 60b9 str r1, [r7, #8]
8015976: 4611 mov r1, r2
8015978: 461a mov r2, r3
801597a: 460b mov r3, r1
801597c: 71fb strb r3, [r7, #7]
801597e: 4613 mov r3, r2
8015980: 71bb strb r3, [r7, #6]
struct tcp_hdr *tcphdr;
u32_t *opts;
u16_t sacks_len = 0;
8015982: 2300 movs r3, #0
8015984: 83fb strh r3, [r7, #30]
LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
8015986: 68bb ldr r3, [r7, #8]
8015988: 2b00 cmp r3, #0
801598a: d106 bne.n 801599a <tcp_output_fill_options+0x2e>
801598c: 4b13 ldr r3, [pc, #76] ; (80159dc <tcp_output_fill_options+0x70>)
801598e: f240 7256 movw r2, #1878 ; 0x756
8015992: 4913 ldr r1, [pc, #76] ; (80159e0 <tcp_output_fill_options+0x74>)
8015994: 4813 ldr r0, [pc, #76] ; (80159e4 <tcp_output_fill_options+0x78>)
8015996: f005 fb45 bl 801b024 <iprintf>
tcphdr = (struct tcp_hdr *)p->payload;
801599a: 68bb ldr r3, [r7, #8]
801599c: 685b ldr r3, [r3, #4]
801599e: 61bb str r3, [r7, #24]
opts = (u32_t *)(void *)(tcphdr + 1);
80159a0: 69bb ldr r3, [r7, #24]
80159a2: 3314 adds r3, #20
80159a4: 617b str r3, [r7, #20]
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
#endif
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(sacks_len);
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
80159a6: 69bb ldr r3, [r7, #24]
80159a8: f103 0214 add.w r2, r3, #20
80159ac: 8bfb ldrh r3, [r7, #30]
80159ae: 009b lsls r3, r3, #2
80159b0: 4619 mov r1, r3
80159b2: 79fb ldrb r3, [r7, #7]
80159b4: 009b lsls r3, r3, #2
80159b6: f003 0304 and.w r3, r3, #4
80159ba: 440b add r3, r1
80159bc: 4413 add r3, r2
80159be: 697a ldr r2, [r7, #20]
80159c0: 429a cmp r2, r3
80159c2: d006 beq.n 80159d2 <tcp_output_fill_options+0x66>
80159c4: 4b05 ldr r3, [pc, #20] ; (80159dc <tcp_output_fill_options+0x70>)
80159c6: f240 7275 movw r2, #1909 ; 0x775
80159ca: 4907 ldr r1, [pc, #28] ; (80159e8 <tcp_output_fill_options+0x7c>)
80159cc: 4805 ldr r0, [pc, #20] ; (80159e4 <tcp_output_fill_options+0x78>)
80159ce: f005 fb29 bl 801b024 <iprintf>
LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
}
80159d2: bf00 nop
80159d4: 3720 adds r7, #32
80159d6: 46bd mov sp, r7
80159d8: bd80 pop {r7, pc}
80159da: bf00 nop
80159dc: 0801d740 .word 0x0801d740
80159e0: 0801de70 .word 0x0801de70
80159e4: 0801d794 .word 0x0801d794
80159e8: 0801dd68 .word 0x0801dd68
080159ec <tcp_output_control_segment>:
* header checksum and calling ip_output_if while handling netif hints and stats.
*/
static err_t
tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
const ip_addr_t *src, const ip_addr_t *dst)
{
80159ec: b580 push {r7, lr}
80159ee: b08a sub sp, #40 ; 0x28
80159f0: af04 add r7, sp, #16
80159f2: 60f8 str r0, [r7, #12]
80159f4: 60b9 str r1, [r7, #8]
80159f6: 607a str r2, [r7, #4]
80159f8: 603b str r3, [r7, #0]
err_t err;
struct netif *netif;
LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
80159fa: 68bb ldr r3, [r7, #8]
80159fc: 2b00 cmp r3, #0
80159fe: d106 bne.n 8015a0e <tcp_output_control_segment+0x22>
8015a00: 4b1c ldr r3, [pc, #112] ; (8015a74 <tcp_output_control_segment+0x88>)
8015a02: f240 7287 movw r2, #1927 ; 0x787
8015a06: 491c ldr r1, [pc, #112] ; (8015a78 <tcp_output_control_segment+0x8c>)
8015a08: 481c ldr r0, [pc, #112] ; (8015a7c <tcp_output_control_segment+0x90>)
8015a0a: f005 fb0b bl 801b024 <iprintf>
netif = tcp_route(pcb, src, dst);
8015a0e: 683a ldr r2, [r7, #0]
8015a10: 6879 ldr r1, [r7, #4]
8015a12: 68f8 ldr r0, [r7, #12]
8015a14: f7fe ff2e bl 8014874 <tcp_route>
8015a18: 6138 str r0, [r7, #16]
if (netif == NULL) {
8015a1a: 693b ldr r3, [r7, #16]
8015a1c: 2b00 cmp r3, #0
8015a1e: d102 bne.n 8015a26 <tcp_output_control_segment+0x3a>
err = ERR_RTE;
8015a20: 23fc movs r3, #252 ; 0xfc
8015a22: 75fb strb r3, [r7, #23]
8015a24: e01c b.n 8015a60 <tcp_output_control_segment+0x74>
struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
src, dst);
}
#endif
if (pcb != NULL) {
8015a26: 68fb ldr r3, [r7, #12]
8015a28: 2b00 cmp r3, #0
8015a2a: d006 beq.n 8015a3a <tcp_output_control_segment+0x4e>
NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
ttl = pcb->ttl;
8015a2c: 68fb ldr r3, [r7, #12]
8015a2e: 7adb ldrb r3, [r3, #11]
8015a30: 75bb strb r3, [r7, #22]
tos = pcb->tos;
8015a32: 68fb ldr r3, [r7, #12]
8015a34: 7a9b ldrb r3, [r3, #10]
8015a36: 757b strb r3, [r7, #21]
8015a38: e003 b.n 8015a42 <tcp_output_control_segment+0x56>
} else {
/* Send output with hardcoded TTL/HL since we have no access to the pcb */
ttl = TCP_TTL;
8015a3a: 23ff movs r3, #255 ; 0xff
8015a3c: 75bb strb r3, [r7, #22]
tos = 0;
8015a3e: 2300 movs r3, #0
8015a40: 757b strb r3, [r7, #21]
}
TCP_STATS_INC(tcp.xmit);
err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
8015a42: 7dba ldrb r2, [r7, #22]
8015a44: 693b ldr r3, [r7, #16]
8015a46: 9302 str r3, [sp, #8]
8015a48: 2306 movs r3, #6
8015a4a: 9301 str r3, [sp, #4]
8015a4c: 7d7b ldrb r3, [r7, #21]
8015a4e: 9300 str r3, [sp, #0]
8015a50: 4613 mov r3, r2
8015a52: 683a ldr r2, [r7, #0]
8015a54: 6879 ldr r1, [r7, #4]
8015a56: 68b8 ldr r0, [r7, #8]
8015a58: f004 f964 bl 8019d24 <ip4_output_if>
8015a5c: 4603 mov r3, r0
8015a5e: 75fb strb r3, [r7, #23]
NETIF_RESET_HINTS(netif);
}
pbuf_free(p);
8015a60: 68b8 ldr r0, [r7, #8]
8015a62: f7fa fdc9 bl 80105f8 <pbuf_free>
return err;
8015a66: f997 3017 ldrsb.w r3, [r7, #23]
}
8015a6a: 4618 mov r0, r3
8015a6c: 3718 adds r7, #24
8015a6e: 46bd mov sp, r7
8015a70: bd80 pop {r7, pc}
8015a72: bf00 nop
8015a74: 0801d740 .word 0x0801d740
8015a78: 0801de98 .word 0x0801de98
8015a7c: 0801d794 .word 0x0801d794
08015a80 <tcp_rst>:
*/
void
tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
u16_t local_port, u16_t remote_port)
{
8015a80: b590 push {r4, r7, lr}
8015a82: b08b sub sp, #44 ; 0x2c
8015a84: af04 add r7, sp, #16
8015a86: 60f8 str r0, [r7, #12]
8015a88: 60b9 str r1, [r7, #8]
8015a8a: 607a str r2, [r7, #4]
8015a8c: 603b str r3, [r7, #0]
struct pbuf *p;
u16_t wnd;
u8_t optlen;
LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
8015a8e: 683b ldr r3, [r7, #0]
8015a90: 2b00 cmp r3, #0
8015a92: d106 bne.n 8015aa2 <tcp_rst+0x22>
8015a94: 4b1f ldr r3, [pc, #124] ; (8015b14 <tcp_rst+0x94>)
8015a96: f240 72c4 movw r2, #1988 ; 0x7c4
8015a9a: 491f ldr r1, [pc, #124] ; (8015b18 <tcp_rst+0x98>)
8015a9c: 481f ldr r0, [pc, #124] ; (8015b1c <tcp_rst+0x9c>)
8015a9e: f005 fac1 bl 801b024 <iprintf>
LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
8015aa2: 6abb ldr r3, [r7, #40] ; 0x28
8015aa4: 2b00 cmp r3, #0
8015aa6: d106 bne.n 8015ab6 <tcp_rst+0x36>
8015aa8: 4b1a ldr r3, [pc, #104] ; (8015b14 <tcp_rst+0x94>)
8015aaa: f240 72c5 movw r2, #1989 ; 0x7c5
8015aae: 491c ldr r1, [pc, #112] ; (8015b20 <tcp_rst+0xa0>)
8015ab0: 481a ldr r0, [pc, #104] ; (8015b1c <tcp_rst+0x9c>)
8015ab2: f005 fab7 bl 801b024 <iprintf>
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015ab6: 2300 movs r3, #0
8015ab8: 75fb strb r3, [r7, #23]
#if LWIP_WND_SCALE
wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
#else
wnd = PP_HTONS(TCP_WND);
8015aba: f246 0308 movw r3, #24584 ; 0x6008
8015abe: 82bb strh r3, [r7, #20]
#endif
p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
8015ac0: 7dfb ldrb r3, [r7, #23]
8015ac2: b29c uxth r4, r3
8015ac4: 68b8 ldr r0, [r7, #8]
8015ac6: f7f9 f9f8 bl 800eeba <lwip_htonl>
8015aca: 4602 mov r2, r0
8015acc: 8abb ldrh r3, [r7, #20]
8015ace: 9303 str r3, [sp, #12]
8015ad0: 2314 movs r3, #20
8015ad2: 9302 str r3, [sp, #8]
8015ad4: 8e3b ldrh r3, [r7, #48] ; 0x30
8015ad6: 9301 str r3, [sp, #4]
8015ad8: 8dbb ldrh r3, [r7, #44] ; 0x2c
8015ada: 9300 str r3, [sp, #0]
8015adc: 4613 mov r3, r2
8015ade: 2200 movs r2, #0
8015ae0: 4621 mov r1, r4
8015ae2: 6878 ldr r0, [r7, #4]
8015ae4: f7ff fe90 bl 8015808 <tcp_output_alloc_header_common>
8015ae8: 6138 str r0, [r7, #16]
remote_port, TCP_RST | TCP_ACK, wnd);
if (p == NULL) {
8015aea: 693b ldr r3, [r7, #16]
8015aec: 2b00 cmp r3, #0
8015aee: d00c beq.n 8015b0a <tcp_rst+0x8a>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
return;
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015af0: 7dfb ldrb r3, [r7, #23]
8015af2: 2200 movs r2, #0
8015af4: 6939 ldr r1, [r7, #16]
8015af6: 68f8 ldr r0, [r7, #12]
8015af8: f7ff ff38 bl 801596c <tcp_output_fill_options>
MIB2_STATS_INC(mib2.tcpoutrsts);
tcp_output_control_segment(pcb, p, local_ip, remote_ip);
8015afc: 6abb ldr r3, [r7, #40] ; 0x28
8015afe: 683a ldr r2, [r7, #0]
8015b00: 6939 ldr r1, [r7, #16]
8015b02: 68f8 ldr r0, [r7, #12]
8015b04: f7ff ff72 bl 80159ec <tcp_output_control_segment>
8015b08: e000 b.n 8015b0c <tcp_rst+0x8c>
return;
8015b0a: bf00 nop
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
}
8015b0c: 371c adds r7, #28
8015b0e: 46bd mov sp, r7
8015b10: bd90 pop {r4, r7, pc}
8015b12: bf00 nop
8015b14: 0801d740 .word 0x0801d740
8015b18: 0801dec4 .word 0x0801dec4
8015b1c: 0801d794 .word 0x0801d794
8015b20: 0801dee0 .word 0x0801dee0
08015b24 <tcp_send_empty_ack>:
*
* @param pcb Protocol control block for the TCP connection to send the ACK
*/
err_t
tcp_send_empty_ack(struct tcp_pcb *pcb)
{
8015b24: b590 push {r4, r7, lr}
8015b26: b087 sub sp, #28
8015b28: af00 add r7, sp, #0
8015b2a: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen, optflags = 0;
8015b2c: 2300 movs r3, #0
8015b2e: 75fb strb r3, [r7, #23]
u8_t num_sacks = 0;
8015b30: 2300 movs r3, #0
8015b32: 75bb strb r3, [r7, #22]
LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
8015b34: 687b ldr r3, [r7, #4]
8015b36: 2b00 cmp r3, #0
8015b38: d106 bne.n 8015b48 <tcp_send_empty_ack+0x24>
8015b3a: 4b28 ldr r3, [pc, #160] ; (8015bdc <tcp_send_empty_ack+0xb8>)
8015b3c: f240 72ea movw r2, #2026 ; 0x7ea
8015b40: 4927 ldr r1, [pc, #156] ; (8015be0 <tcp_send_empty_ack+0xbc>)
8015b42: 4828 ldr r0, [pc, #160] ; (8015be4 <tcp_send_empty_ack+0xc0>)
8015b44: f005 fa6e bl 801b024 <iprintf>
#if LWIP_TCP_TIMESTAMPS
if (pcb->flags & TF_TIMESTAMP) {
optflags = TF_SEG_OPTS_TS;
}
#endif
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
8015b48: 7dfb ldrb r3, [r7, #23]
8015b4a: 009b lsls r3, r3, #2
8015b4c: b2db uxtb r3, r3
8015b4e: f003 0304 and.w r3, r3, #4
8015b52: 757b strb r3, [r7, #21]
if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
}
#endif
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
8015b54: 7d7b ldrb r3, [r7, #21]
8015b56: b29c uxth r4, r3
8015b58: 687b ldr r3, [r7, #4]
8015b5a: 6d1b ldr r3, [r3, #80] ; 0x50
8015b5c: 4618 mov r0, r3
8015b5e: f7f9 f9ac bl 800eeba <lwip_htonl>
8015b62: 4603 mov r3, r0
8015b64: 2200 movs r2, #0
8015b66: 4621 mov r1, r4
8015b68: 6878 ldr r0, [r7, #4]
8015b6a: f7ff fec1 bl 80158f0 <tcp_output_alloc_header>
8015b6e: 6138 str r0, [r7, #16]
if (p == NULL) {
8015b70: 693b ldr r3, [r7, #16]
8015b72: 2b00 cmp r3, #0
8015b74: d109 bne.n 8015b8a <tcp_send_empty_ack+0x66>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015b76: 687b ldr r3, [r7, #4]
8015b78: 8b5b ldrh r3, [r3, #26]
8015b7a: f043 0303 orr.w r3, r3, #3
8015b7e: b29a uxth r2, r3
8015b80: 687b ldr r3, [r7, #4]
8015b82: 835a strh r2, [r3, #26]
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
return ERR_BUF;
8015b84: f06f 0301 mvn.w r3, #1
8015b88: e023 b.n 8015bd2 <tcp_send_empty_ack+0xae>
}
tcp_output_fill_options(pcb, p, optflags, num_sacks);
8015b8a: 7dbb ldrb r3, [r7, #22]
8015b8c: 7dfa ldrb r2, [r7, #23]
8015b8e: 6939 ldr r1, [r7, #16]
8015b90: 6878 ldr r0, [r7, #4]
8015b92: f7ff feeb bl 801596c <tcp_output_fill_options>
pcb->ts_lastacksent = pcb->rcv_nxt;
#endif
LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015b96: 687a ldr r2, [r7, #4]
8015b98: 687b ldr r3, [r7, #4]
8015b9a: 3304 adds r3, #4
8015b9c: 6939 ldr r1, [r7, #16]
8015b9e: 6878 ldr r0, [r7, #4]
8015ba0: f7ff ff24 bl 80159ec <tcp_output_control_segment>
8015ba4: 4603 mov r3, r0
8015ba6: 73fb strb r3, [r7, #15]
if (err != ERR_OK) {
8015ba8: f997 300f ldrsb.w r3, [r7, #15]
8015bac: 2b00 cmp r3, #0
8015bae: d007 beq.n 8015bc0 <tcp_send_empty_ack+0x9c>
/* let tcp_fasttmr retry sending this ACK */
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015bb0: 687b ldr r3, [r7, #4]
8015bb2: 8b5b ldrh r3, [r3, #26]
8015bb4: f043 0303 orr.w r3, r3, #3
8015bb8: b29a uxth r2, r3
8015bba: 687b ldr r3, [r7, #4]
8015bbc: 835a strh r2, [r3, #26]
8015bbe: e006 b.n 8015bce <tcp_send_empty_ack+0xaa>
} else {
/* remove ACK flags from the PCB, as we sent an empty ACK now */
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
8015bc0: 687b ldr r3, [r7, #4]
8015bc2: 8b5b ldrh r3, [r3, #26]
8015bc4: f023 0303 bic.w r3, r3, #3
8015bc8: b29a uxth r2, r3
8015bca: 687b ldr r3, [r7, #4]
8015bcc: 835a strh r2, [r3, #26]
}
return err;
8015bce: f997 300f ldrsb.w r3, [r7, #15]
}
8015bd2: 4618 mov r0, r3
8015bd4: 371c adds r7, #28
8015bd6: 46bd mov sp, r7
8015bd8: bd90 pop {r4, r7, pc}
8015bda: bf00 nop
8015bdc: 0801d740 .word 0x0801d740
8015be0: 0801defc .word 0x0801defc
8015be4: 0801d794 .word 0x0801d794
08015be8 <tcp_keepalive>:
*
* @param pcb the tcp_pcb for which to send a keepalive packet
*/
err_t
tcp_keepalive(struct tcp_pcb *pcb)
{
8015be8: b590 push {r4, r7, lr}
8015bea: b087 sub sp, #28
8015bec: af00 add r7, sp, #0
8015bee: 6078 str r0, [r7, #4]
err_t err;
struct pbuf *p;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015bf0: 2300 movs r3, #0
8015bf2: 75fb strb r3, [r7, #23]
LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
8015bf4: 687b ldr r3, [r7, #4]
8015bf6: 2b00 cmp r3, #0
8015bf8: d106 bne.n 8015c08 <tcp_keepalive+0x20>
8015bfa: 4b18 ldr r3, [pc, #96] ; (8015c5c <tcp_keepalive+0x74>)
8015bfc: f640 0224 movw r2, #2084 ; 0x824
8015c00: 4917 ldr r1, [pc, #92] ; (8015c60 <tcp_keepalive+0x78>)
8015c02: 4818 ldr r0, [pc, #96] ; (8015c64 <tcp_keepalive+0x7c>)
8015c04: f005 fa0e bl 801b024 <iprintf>
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
8015c08: 7dfb ldrb r3, [r7, #23]
8015c0a: b29c uxth r4, r3
8015c0c: 687b ldr r3, [r7, #4]
8015c0e: 6d1b ldr r3, [r3, #80] ; 0x50
8015c10: 3b01 subs r3, #1
8015c12: 4618 mov r0, r3
8015c14: f7f9 f951 bl 800eeba <lwip_htonl>
8015c18: 4603 mov r3, r0
8015c1a: 2200 movs r2, #0
8015c1c: 4621 mov r1, r4
8015c1e: 6878 ldr r0, [r7, #4]
8015c20: f7ff fe66 bl 80158f0 <tcp_output_alloc_header>
8015c24: 6138 str r0, [r7, #16]
if (p == NULL) {
8015c26: 693b ldr r3, [r7, #16]
8015c28: 2b00 cmp r3, #0
8015c2a: d102 bne.n 8015c32 <tcp_keepalive+0x4a>
LWIP_DEBUGF(TCP_DEBUG,
("tcp_keepalive: could not allocate memory for pbuf\n"));
return ERR_MEM;
8015c2c: f04f 33ff mov.w r3, #4294967295
8015c30: e010 b.n 8015c54 <tcp_keepalive+0x6c>
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015c32: 7dfb ldrb r3, [r7, #23]
8015c34: 2200 movs r2, #0
8015c36: 6939 ldr r1, [r7, #16]
8015c38: 6878 ldr r0, [r7, #4]
8015c3a: f7ff fe97 bl 801596c <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015c3e: 687a ldr r2, [r7, #4]
8015c40: 687b ldr r3, [r7, #4]
8015c42: 3304 adds r3, #4
8015c44: 6939 ldr r1, [r7, #16]
8015c46: 6878 ldr r0, [r7, #4]
8015c48: f7ff fed0 bl 80159ec <tcp_output_control_segment>
8015c4c: 4603 mov r3, r0
8015c4e: 73fb strb r3, [r7, #15]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015c50: f997 300f ldrsb.w r3, [r7, #15]
}
8015c54: 4618 mov r0, r3
8015c56: 371c adds r7, #28
8015c58: 46bd mov sp, r7
8015c5a: bd90 pop {r4, r7, pc}
8015c5c: 0801d740 .word 0x0801d740
8015c60: 0801df1c .word 0x0801df1c
8015c64: 0801d794 .word 0x0801d794
08015c68 <tcp_zero_window_probe>:
*
* @param pcb the tcp_pcb for which to send a zero-window probe packet
*/
err_t
tcp_zero_window_probe(struct tcp_pcb *pcb)
{
8015c68: b590 push {r4, r7, lr}
8015c6a: b08b sub sp, #44 ; 0x2c
8015c6c: af00 add r7, sp, #0
8015c6e: 6078 str r0, [r7, #4]
struct tcp_hdr *tcphdr;
struct tcp_seg *seg;
u16_t len;
u8_t is_fin;
u32_t snd_nxt;
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
8015c70: 2300 movs r3, #0
8015c72: f887 3027 strb.w r3, [r7, #39] ; 0x27
LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
8015c76: 687b ldr r3, [r7, #4]
8015c78: 2b00 cmp r3, #0
8015c7a: d106 bne.n 8015c8a <tcp_zero_window_probe+0x22>
8015c7c: 4b4c ldr r3, [pc, #304] ; (8015db0 <tcp_zero_window_probe+0x148>)
8015c7e: f640 024f movw r2, #2127 ; 0x84f
8015c82: 494c ldr r1, [pc, #304] ; (8015db4 <tcp_zero_window_probe+0x14c>)
8015c84: 484c ldr r0, [pc, #304] ; (8015db8 <tcp_zero_window_probe+0x150>)
8015c86: f005 f9cd bl 801b024 <iprintf>
("tcp_zero_window_probe: tcp_ticks %"U32_F
" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
/* Only consider unsent, persist timer should be off when there is data in-flight */
seg = pcb->unsent;
8015c8a: 687b ldr r3, [r7, #4]
8015c8c: 6edb ldr r3, [r3, #108] ; 0x6c
8015c8e: 623b str r3, [r7, #32]
if (seg == NULL) {
8015c90: 6a3b ldr r3, [r7, #32]
8015c92: 2b00 cmp r3, #0
8015c94: d101 bne.n 8015c9a <tcp_zero_window_probe+0x32>
/* Not expected, persist timer should be off when the send buffer is empty */
return ERR_OK;
8015c96: 2300 movs r3, #0
8015c98: e086 b.n 8015da8 <tcp_zero_window_probe+0x140>
/* increment probe count. NOTE: we record probe even if it fails
to actually transmit due to an error. This ensures memory exhaustion/
routing problem doesn't leave a zero-window pcb as an indefinite zombie.
RTO mechanism has similar behavior, see pcb->nrtx */
if (pcb->persist_probe < 0xFF) {
8015c9a: 687b ldr r3, [r7, #4]
8015c9c: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015ca0: 2bff cmp r3, #255 ; 0xff
8015ca2: d007 beq.n 8015cb4 <tcp_zero_window_probe+0x4c>
++pcb->persist_probe;
8015ca4: 687b ldr r3, [r7, #4]
8015ca6: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
8015caa: 3301 adds r3, #1
8015cac: b2da uxtb r2, r3
8015cae: 687b ldr r3, [r7, #4]
8015cb0: f883 209a strb.w r2, [r3, #154] ; 0x9a
}
is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
8015cb4: 6a3b ldr r3, [r7, #32]
8015cb6: 68db ldr r3, [r3, #12]
8015cb8: 899b ldrh r3, [r3, #12]
8015cba: b29b uxth r3, r3
8015cbc: 4618 mov r0, r3
8015cbe: f7f9 f8e7 bl 800ee90 <lwip_htons>
8015cc2: 4603 mov r3, r0
8015cc4: b2db uxtb r3, r3
8015cc6: f003 0301 and.w r3, r3, #1
8015cca: 2b00 cmp r3, #0
8015ccc: d005 beq.n 8015cda <tcp_zero_window_probe+0x72>
8015cce: 6a3b ldr r3, [r7, #32]
8015cd0: 891b ldrh r3, [r3, #8]
8015cd2: 2b00 cmp r3, #0
8015cd4: d101 bne.n 8015cda <tcp_zero_window_probe+0x72>
8015cd6: 2301 movs r3, #1
8015cd8: e000 b.n 8015cdc <tcp_zero_window_probe+0x74>
8015cda: 2300 movs r3, #0
8015cdc: 77fb strb r3, [r7, #31]
/* we want to send one seqno: either FIN or data (no options) */
len = is_fin ? 0 : 1;
8015cde: 7ffb ldrb r3, [r7, #31]
8015ce0: 2b00 cmp r3, #0
8015ce2: bf0c ite eq
8015ce4: 2301 moveq r3, #1
8015ce6: 2300 movne r3, #0
8015ce8: b2db uxtb r3, r3
8015cea: 83bb strh r3, [r7, #28]
p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
8015cec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015cf0: b299 uxth r1, r3
8015cf2: 6a3b ldr r3, [r7, #32]
8015cf4: 68db ldr r3, [r3, #12]
8015cf6: 685b ldr r3, [r3, #4]
8015cf8: 8bba ldrh r2, [r7, #28]
8015cfa: 6878 ldr r0, [r7, #4]
8015cfc: f7ff fdf8 bl 80158f0 <tcp_output_alloc_header>
8015d00: 61b8 str r0, [r7, #24]
if (p == NULL) {
8015d02: 69bb ldr r3, [r7, #24]
8015d04: 2b00 cmp r3, #0
8015d06: d102 bne.n 8015d0e <tcp_zero_window_probe+0xa6>
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
return ERR_MEM;
8015d08: f04f 33ff mov.w r3, #4294967295
8015d0c: e04c b.n 8015da8 <tcp_zero_window_probe+0x140>
}
tcphdr = (struct tcp_hdr *)p->payload;
8015d0e: 69bb ldr r3, [r7, #24]
8015d10: 685b ldr r3, [r3, #4]
8015d12: 617b str r3, [r7, #20]
if (is_fin) {
8015d14: 7ffb ldrb r3, [r7, #31]
8015d16: 2b00 cmp r3, #0
8015d18: d011 beq.n 8015d3e <tcp_zero_window_probe+0xd6>
/* FIN segment, no data */
TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
8015d1a: 697b ldr r3, [r7, #20]
8015d1c: 899b ldrh r3, [r3, #12]
8015d1e: b29b uxth r3, r3
8015d20: b21b sxth r3, r3
8015d22: f423 537c bic.w r3, r3, #16128 ; 0x3f00
8015d26: b21c sxth r4, r3
8015d28: 2011 movs r0, #17
8015d2a: f7f9 f8b1 bl 800ee90 <lwip_htons>
8015d2e: 4603 mov r3, r0
8015d30: b21b sxth r3, r3
8015d32: 4323 orrs r3, r4
8015d34: b21b sxth r3, r3
8015d36: b29a uxth r2, r3
8015d38: 697b ldr r3, [r7, #20]
8015d3a: 819a strh r2, [r3, #12]
8015d3c: e010 b.n 8015d60 <tcp_zero_window_probe+0xf8>
} else {
/* Data segment, copy in one byte from the head of the unacked queue */
char *d = ((char *)p->payload + TCP_HLEN);
8015d3e: 69bb ldr r3, [r7, #24]
8015d40: 685b ldr r3, [r3, #4]
8015d42: 3314 adds r3, #20
8015d44: 613b str r3, [r7, #16]
/* Depending on whether the segment has already been sent (unacked) or not
(unsent), seg->p->payload points to the IP header or TCP header.
Ensure we copy the first TCP data byte: */
pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
8015d46: 6a3b ldr r3, [r7, #32]
8015d48: 6858 ldr r0, [r3, #4]
8015d4a: 6a3b ldr r3, [r7, #32]
8015d4c: 685b ldr r3, [r3, #4]
8015d4e: 891a ldrh r2, [r3, #8]
8015d50: 6a3b ldr r3, [r7, #32]
8015d52: 891b ldrh r3, [r3, #8]
8015d54: 1ad3 subs r3, r2, r3
8015d56: b29b uxth r3, r3
8015d58: 2201 movs r2, #1
8015d5a: 6939 ldr r1, [r7, #16]
8015d5c: f7fa fe52 bl 8010a04 <pbuf_copy_partial>
}
/* The byte may be acknowledged without the window being opened. */
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
8015d60: 6a3b ldr r3, [r7, #32]
8015d62: 68db ldr r3, [r3, #12]
8015d64: 685b ldr r3, [r3, #4]
8015d66: 4618 mov r0, r3
8015d68: f7f9 f8a7 bl 800eeba <lwip_htonl>
8015d6c: 4603 mov r3, r0
8015d6e: 3301 adds r3, #1
8015d70: 60fb str r3, [r7, #12]
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
8015d72: 687b ldr r3, [r7, #4]
8015d74: 6d1a ldr r2, [r3, #80] ; 0x50
8015d76: 68fb ldr r3, [r7, #12]
8015d78: 1ad3 subs r3, r2, r3
8015d7a: 2b00 cmp r3, #0
8015d7c: da02 bge.n 8015d84 <tcp_zero_window_probe+0x11c>
pcb->snd_nxt = snd_nxt;
8015d7e: 687b ldr r3, [r7, #4]
8015d80: 68fa ldr r2, [r7, #12]
8015d82: 651a str r2, [r3, #80] ; 0x50
}
tcp_output_fill_options(pcb, p, 0, optlen);
8015d84: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8015d88: 2200 movs r2, #0
8015d8a: 69b9 ldr r1, [r7, #24]
8015d8c: 6878 ldr r0, [r7, #4]
8015d8e: f7ff fded bl 801596c <tcp_output_fill_options>
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
8015d92: 687a ldr r2, [r7, #4]
8015d94: 687b ldr r3, [r7, #4]
8015d96: 3304 adds r3, #4
8015d98: 69b9 ldr r1, [r7, #24]
8015d9a: 6878 ldr r0, [r7, #4]
8015d9c: f7ff fe26 bl 80159ec <tcp_output_control_segment>
8015da0: 4603 mov r3, r0
8015da2: 72fb strb r3, [r7, #11]
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
" ackno %"U32_F" err %d.\n",
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
return err;
8015da4: f997 300b ldrsb.w r3, [r7, #11]
}
8015da8: 4618 mov r0, r3
8015daa: 372c adds r7, #44 ; 0x2c
8015dac: 46bd mov sp, r7
8015dae: bd90 pop {r4, r7, pc}
8015db0: 0801d740 .word 0x0801d740
8015db4: 0801df38 .word 0x0801df38
8015db8: 0801d794 .word 0x0801d794
08015dbc <tcpip_tcp_timer>:
*
* @param arg unused argument
*/
static void
tcpip_tcp_timer(void *arg)
{
8015dbc: b580 push {r7, lr}
8015dbe: b082 sub sp, #8
8015dc0: af00 add r7, sp, #0
8015dc2: 6078 str r0, [r7, #4]
LWIP_UNUSED_ARG(arg);
/* call TCP timer handler */
tcp_tmr();
8015dc4: f7fa ff0c bl 8010be0 <tcp_tmr>
/* timer still needed? */
if (tcp_active_pcbs || tcp_tw_pcbs) {
8015dc8: 4b0a ldr r3, [pc, #40] ; (8015df4 <tcpip_tcp_timer+0x38>)
8015dca: 681b ldr r3, [r3, #0]
8015dcc: 2b00 cmp r3, #0
8015dce: d103 bne.n 8015dd8 <tcpip_tcp_timer+0x1c>
8015dd0: 4b09 ldr r3, [pc, #36] ; (8015df8 <tcpip_tcp_timer+0x3c>)
8015dd2: 681b ldr r3, [r3, #0]
8015dd4: 2b00 cmp r3, #0
8015dd6: d005 beq.n 8015de4 <tcpip_tcp_timer+0x28>
/* restart timer */
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015dd8: 2200 movs r2, #0
8015dda: 4908 ldr r1, [pc, #32] ; (8015dfc <tcpip_tcp_timer+0x40>)
8015ddc: 20fa movs r0, #250 ; 0xfa
8015dde: f000 f8f1 bl 8015fc4 <sys_timeout>
8015de2: e002 b.n 8015dea <tcpip_tcp_timer+0x2e>
} else {
/* disable timer */
tcpip_tcp_timer_active = 0;
8015de4: 4b06 ldr r3, [pc, #24] ; (8015e00 <tcpip_tcp_timer+0x44>)
8015de6: 2200 movs r2, #0
8015de8: 601a str r2, [r3, #0]
}
}
8015dea: bf00 nop
8015dec: 3708 adds r7, #8
8015dee: 46bd mov sp, r7
8015df0: bd80 pop {r7, pc}
8015df2: bf00 nop
8015df4: 2000f5c0 .word 0x2000f5c0
8015df8: 2000f5d0 .word 0x2000f5d0
8015dfc: 08015dbd .word 0x08015dbd
8015e00: 20008768 .word 0x20008768
08015e04 <tcp_timer_needed>:
* the reason is to have the TCP timer only running when
* there are active (or time-wait) PCBs.
*/
void
tcp_timer_needed(void)
{
8015e04: b580 push {r7, lr}
8015e06: af00 add r7, sp, #0
LWIP_ASSERT_CORE_LOCKED();
/* timer is off but needed again? */
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
8015e08: 4b0a ldr r3, [pc, #40] ; (8015e34 <tcp_timer_needed+0x30>)
8015e0a: 681b ldr r3, [r3, #0]
8015e0c: 2b00 cmp r3, #0
8015e0e: d10f bne.n 8015e30 <tcp_timer_needed+0x2c>
8015e10: 4b09 ldr r3, [pc, #36] ; (8015e38 <tcp_timer_needed+0x34>)
8015e12: 681b ldr r3, [r3, #0]
8015e14: 2b00 cmp r3, #0
8015e16: d103 bne.n 8015e20 <tcp_timer_needed+0x1c>
8015e18: 4b08 ldr r3, [pc, #32] ; (8015e3c <tcp_timer_needed+0x38>)
8015e1a: 681b ldr r3, [r3, #0]
8015e1c: 2b00 cmp r3, #0
8015e1e: d007 beq.n 8015e30 <tcp_timer_needed+0x2c>
/* enable and start timer */
tcpip_tcp_timer_active = 1;
8015e20: 4b04 ldr r3, [pc, #16] ; (8015e34 <tcp_timer_needed+0x30>)
8015e22: 2201 movs r2, #1
8015e24: 601a str r2, [r3, #0]
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
8015e26: 2200 movs r2, #0
8015e28: 4905 ldr r1, [pc, #20] ; (8015e40 <tcp_timer_needed+0x3c>)
8015e2a: 20fa movs r0, #250 ; 0xfa
8015e2c: f000 f8ca bl 8015fc4 <sys_timeout>
}
}
8015e30: bf00 nop
8015e32: bd80 pop {r7, pc}
8015e34: 20008768 .word 0x20008768
8015e38: 2000f5c0 .word 0x2000f5c0
8015e3c: 2000f5d0 .word 0x2000f5d0
8015e40: 08015dbd .word 0x08015dbd
08015e44 <sys_timeout_abs>:
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
#endif
{
8015e44: b580 push {r7, lr}
8015e46: b086 sub sp, #24
8015e48: af00 add r7, sp, #0
8015e4a: 60f8 str r0, [r7, #12]
8015e4c: 60b9 str r1, [r7, #8]
8015e4e: 607a str r2, [r7, #4]
struct sys_timeo *timeout, *t;
timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
8015e50: 200a movs r0, #10
8015e52: f7f9 fcd3 bl 800f7fc <memp_malloc>
8015e56: 6138 str r0, [r7, #16]
if (timeout == NULL) {
8015e58: 693b ldr r3, [r7, #16]
8015e5a: 2b00 cmp r3, #0
8015e5c: d109 bne.n 8015e72 <sys_timeout_abs+0x2e>
LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
8015e5e: 693b ldr r3, [r7, #16]
8015e60: 2b00 cmp r3, #0
8015e62: d151 bne.n 8015f08 <sys_timeout_abs+0xc4>
8015e64: 4b2a ldr r3, [pc, #168] ; (8015f10 <sys_timeout_abs+0xcc>)
8015e66: 22be movs r2, #190 ; 0xbe
8015e68: 492a ldr r1, [pc, #168] ; (8015f14 <sys_timeout_abs+0xd0>)
8015e6a: 482b ldr r0, [pc, #172] ; (8015f18 <sys_timeout_abs+0xd4>)
8015e6c: f005 f8da bl 801b024 <iprintf>
return;
8015e70: e04a b.n 8015f08 <sys_timeout_abs+0xc4>
}
timeout->next = NULL;
8015e72: 693b ldr r3, [r7, #16]
8015e74: 2200 movs r2, #0
8015e76: 601a str r2, [r3, #0]
timeout->h = handler;
8015e78: 693b ldr r3, [r7, #16]
8015e7a: 68ba ldr r2, [r7, #8]
8015e7c: 609a str r2, [r3, #8]
timeout->arg = arg;
8015e7e: 693b ldr r3, [r7, #16]
8015e80: 687a ldr r2, [r7, #4]
8015e82: 60da str r2, [r3, #12]
timeout->time = abs_time;
8015e84: 693b ldr r3, [r7, #16]
8015e86: 68fa ldr r2, [r7, #12]
8015e88: 605a str r2, [r3, #4]
timeout->handler_name = handler_name;
LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
(void *)timeout, abs_time, handler_name, (void *)arg));
#endif /* LWIP_DEBUG_TIMERNAMES */
if (next_timeout == NULL) {
8015e8a: 4b24 ldr r3, [pc, #144] ; (8015f1c <sys_timeout_abs+0xd8>)
8015e8c: 681b ldr r3, [r3, #0]
8015e8e: 2b00 cmp r3, #0
8015e90: d103 bne.n 8015e9a <sys_timeout_abs+0x56>
next_timeout = timeout;
8015e92: 4a22 ldr r2, [pc, #136] ; (8015f1c <sys_timeout_abs+0xd8>)
8015e94: 693b ldr r3, [r7, #16]
8015e96: 6013 str r3, [r2, #0]
return;
8015e98: e037 b.n 8015f0a <sys_timeout_abs+0xc6>
}
if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
8015e9a: 693b ldr r3, [r7, #16]
8015e9c: 685a ldr r2, [r3, #4]
8015e9e: 4b1f ldr r3, [pc, #124] ; (8015f1c <sys_timeout_abs+0xd8>)
8015ea0: 681b ldr r3, [r3, #0]
8015ea2: 685b ldr r3, [r3, #4]
8015ea4: 1ad3 subs r3, r2, r3
8015ea6: 0fdb lsrs r3, r3, #31
8015ea8: f003 0301 and.w r3, r3, #1
8015eac: b2db uxtb r3, r3
8015eae: 2b00 cmp r3, #0
8015eb0: d007 beq.n 8015ec2 <sys_timeout_abs+0x7e>
timeout->next = next_timeout;
8015eb2: 4b1a ldr r3, [pc, #104] ; (8015f1c <sys_timeout_abs+0xd8>)
8015eb4: 681a ldr r2, [r3, #0]
8015eb6: 693b ldr r3, [r7, #16]
8015eb8: 601a str r2, [r3, #0]
next_timeout = timeout;
8015eba: 4a18 ldr r2, [pc, #96] ; (8015f1c <sys_timeout_abs+0xd8>)
8015ebc: 693b ldr r3, [r7, #16]
8015ebe: 6013 str r3, [r2, #0]
8015ec0: e023 b.n 8015f0a <sys_timeout_abs+0xc6>
} else {
for (t = next_timeout; t != NULL; t = t->next) {
8015ec2: 4b16 ldr r3, [pc, #88] ; (8015f1c <sys_timeout_abs+0xd8>)
8015ec4: 681b ldr r3, [r3, #0]
8015ec6: 617b str r3, [r7, #20]
8015ec8: e01a b.n 8015f00 <sys_timeout_abs+0xbc>
if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
8015eca: 697b ldr r3, [r7, #20]
8015ecc: 681b ldr r3, [r3, #0]
8015ece: 2b00 cmp r3, #0
8015ed0: d00b beq.n 8015eea <sys_timeout_abs+0xa6>
8015ed2: 693b ldr r3, [r7, #16]
8015ed4: 685a ldr r2, [r3, #4]
8015ed6: 697b ldr r3, [r7, #20]
8015ed8: 681b ldr r3, [r3, #0]
8015eda: 685b ldr r3, [r3, #4]
8015edc: 1ad3 subs r3, r2, r3
8015ede: 0fdb lsrs r3, r3, #31
8015ee0: f003 0301 and.w r3, r3, #1
8015ee4: b2db uxtb r3, r3
8015ee6: 2b00 cmp r3, #0
8015ee8: d007 beq.n 8015efa <sys_timeout_abs+0xb6>
timeout->next = t->next;
8015eea: 697b ldr r3, [r7, #20]
8015eec: 681a ldr r2, [r3, #0]
8015eee: 693b ldr r3, [r7, #16]
8015ef0: 601a str r2, [r3, #0]
t->next = timeout;
8015ef2: 697b ldr r3, [r7, #20]
8015ef4: 693a ldr r2, [r7, #16]
8015ef6: 601a str r2, [r3, #0]
break;
8015ef8: e007 b.n 8015f0a <sys_timeout_abs+0xc6>
for (t = next_timeout; t != NULL; t = t->next) {
8015efa: 697b ldr r3, [r7, #20]
8015efc: 681b ldr r3, [r3, #0]
8015efe: 617b str r3, [r7, #20]
8015f00: 697b ldr r3, [r7, #20]
8015f02: 2b00 cmp r3, #0
8015f04: d1e1 bne.n 8015eca <sys_timeout_abs+0x86>
8015f06: e000 b.n 8015f0a <sys_timeout_abs+0xc6>
return;
8015f08: bf00 nop
}
}
}
}
8015f0a: 3718 adds r7, #24
8015f0c: 46bd mov sp, r7
8015f0e: bd80 pop {r7, pc}
8015f10: 0801df5c .word 0x0801df5c
8015f14: 0801df90 .word 0x0801df90
8015f18: 0801dfd0 .word 0x0801dfd0
8015f1c: 20008760 .word 0x20008760
08015f20 <lwip_cyclic_timer>:
#if !LWIP_TESTMODE
static
#endif
void
lwip_cyclic_timer(void *arg)
{
8015f20: b580 push {r7, lr}
8015f22: b086 sub sp, #24
8015f24: af00 add r7, sp, #0
8015f26: 6078 str r0, [r7, #4]
u32_t now;
u32_t next_timeout_time;
const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
8015f28: 687b ldr r3, [r7, #4]
8015f2a: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
#endif
cyclic->handler();
8015f2c: 697b ldr r3, [r7, #20]
8015f2e: 685b ldr r3, [r3, #4]
8015f30: 4798 blx r3
now = sys_now();
8015f32: f7f5 fc5b bl 800b7ec <sys_now>
8015f36: 6138 str r0, [r7, #16]
next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */
8015f38: 697b ldr r3, [r7, #20]
8015f3a: 681a ldr r2, [r3, #0]
8015f3c: 4b0f ldr r3, [pc, #60] ; (8015f7c <lwip_cyclic_timer+0x5c>)
8015f3e: 681b ldr r3, [r3, #0]
8015f40: 4413 add r3, r2
8015f42: 60fb str r3, [r7, #12]
if (TIME_LESS_THAN(next_timeout_time, now)) {
8015f44: 68fa ldr r2, [r7, #12]
8015f46: 693b ldr r3, [r7, #16]
8015f48: 1ad3 subs r3, r2, r3
8015f4a: 0fdb lsrs r3, r3, #31
8015f4c: f003 0301 and.w r3, r3, #1
8015f50: b2db uxtb r3, r3
8015f52: 2b00 cmp r3, #0
8015f54: d009 beq.n 8015f6a <lwip_cyclic_timer+0x4a>
/* timer would immediately expire again -> "overload" -> restart without any correction */
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
8015f56: 697b ldr r3, [r7, #20]
8015f58: 681a ldr r2, [r3, #0]
8015f5a: 693b ldr r3, [r7, #16]
8015f5c: 4413 add r3, r2
8015f5e: 687a ldr r2, [r7, #4]
8015f60: 4907 ldr r1, [pc, #28] ; (8015f80 <lwip_cyclic_timer+0x60>)
8015f62: 4618 mov r0, r3
8015f64: f7ff ff6e bl 8015e44 <sys_timeout_abs>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
#else
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
#endif
}
}
8015f68: e004 b.n 8015f74 <lwip_cyclic_timer+0x54>
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
8015f6a: 687a ldr r2, [r7, #4]
8015f6c: 4904 ldr r1, [pc, #16] ; (8015f80 <lwip_cyclic_timer+0x60>)
8015f6e: 68f8 ldr r0, [r7, #12]
8015f70: f7ff ff68 bl 8015e44 <sys_timeout_abs>
}
8015f74: bf00 nop
8015f76: 3718 adds r7, #24
8015f78: 46bd mov sp, r7
8015f7a: bd80 pop {r7, pc}
8015f7c: 20008764 .word 0x20008764
8015f80: 08015f21 .word 0x08015f21
08015f84 <sys_timeouts_init>:
/** Initialize this module */
void sys_timeouts_init(void)
{
8015f84: b580 push {r7, lr}
8015f86: b082 sub sp, #8
8015f88: af00 add r7, sp, #0
size_t i;
/* tcp_tmr() at index 0 is started on demand */
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015f8a: 2301 movs r3, #1
8015f8c: 607b str r3, [r7, #4]
8015f8e: e00e b.n 8015fae <sys_timeouts_init+0x2a>
/* we have to cast via size_t to get rid of const warning
(this is OK as cyclic_timer() casts back to const* */
sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
8015f90: 4a0a ldr r2, [pc, #40] ; (8015fbc <sys_timeouts_init+0x38>)
8015f92: 687b ldr r3, [r7, #4]
8015f94: f852 0033 ldr.w r0, [r2, r3, lsl #3]
8015f98: 687b ldr r3, [r7, #4]
8015f9a: 00db lsls r3, r3, #3
8015f9c: 4a07 ldr r2, [pc, #28] ; (8015fbc <sys_timeouts_init+0x38>)
8015f9e: 4413 add r3, r2
8015fa0: 461a mov r2, r3
8015fa2: 4907 ldr r1, [pc, #28] ; (8015fc0 <sys_timeouts_init+0x3c>)
8015fa4: f000 f80e bl 8015fc4 <sys_timeout>
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
8015fa8: 687b ldr r3, [r7, #4]
8015faa: 3301 adds r3, #1
8015fac: 607b str r3, [r7, #4]
8015fae: 687b ldr r3, [r7, #4]
8015fb0: 2b04 cmp r3, #4
8015fb2: d9ed bls.n 8015f90 <sys_timeouts_init+0xc>
}
}
8015fb4: bf00 nop
8015fb6: 3708 adds r7, #8
8015fb8: 46bd mov sp, r7
8015fba: bd80 pop {r7, pc}
8015fbc: 08020e50 .word 0x08020e50
8015fc0: 08015f21 .word 0x08015f21
08015fc4 <sys_timeout>:
sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
#else /* LWIP_DEBUG_TIMERNAMES */
void
sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
#endif /* LWIP_DEBUG_TIMERNAMES */
{
8015fc4: b580 push {r7, lr}
8015fc6: b086 sub sp, #24
8015fc8: af00 add r7, sp, #0
8015fca: 60f8 str r0, [r7, #12]
8015fcc: 60b9 str r1, [r7, #8]
8015fce: 607a str r2, [r7, #4]
u32_t next_timeout_time;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
8015fd0: 68fb ldr r3, [r7, #12]
8015fd2: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8015fd6: d306 bcc.n 8015fe6 <sys_timeout+0x22>
8015fd8: 4b0a ldr r3, [pc, #40] ; (8016004 <sys_timeout+0x40>)
8015fda: f240 1229 movw r2, #297 ; 0x129
8015fde: 490a ldr r1, [pc, #40] ; (8016008 <sys_timeout+0x44>)
8015fe0: 480a ldr r0, [pc, #40] ; (801600c <sys_timeout+0x48>)
8015fe2: f005 f81f bl 801b024 <iprintf>
next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */
8015fe6: f7f5 fc01 bl 800b7ec <sys_now>
8015fea: 4602 mov r2, r0
8015fec: 68fb ldr r3, [r7, #12]
8015fee: 4413 add r3, r2
8015ff0: 617b str r3, [r7, #20]
#if LWIP_DEBUG_TIMERNAMES
sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
#else
sys_timeout_abs(next_timeout_time, handler, arg);
8015ff2: 687a ldr r2, [r7, #4]
8015ff4: 68b9 ldr r1, [r7, #8]
8015ff6: 6978 ldr r0, [r7, #20]
8015ff8: f7ff ff24 bl 8015e44 <sys_timeout_abs>
#endif
}
8015ffc: bf00 nop
8015ffe: 3718 adds r7, #24
8016000: 46bd mov sp, r7
8016002: bd80 pop {r7, pc}
8016004: 0801df5c .word 0x0801df5c
8016008: 0801dff8 .word 0x0801dff8
801600c: 0801dfd0 .word 0x0801dfd0
08016010 <sys_check_timeouts>:
*
* Must be called periodically from your main loop.
*/
void
sys_check_timeouts(void)
{
8016010: b580 push {r7, lr}
8016012: b084 sub sp, #16
8016014: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
/* Process only timers expired at the start of the function. */
now = sys_now();
8016016: f7f5 fbe9 bl 800b7ec <sys_now>
801601a: 60f8 str r0, [r7, #12]
sys_timeout_handler handler;
void *arg;
PBUF_CHECK_FREE_OOSEQ();
tmptimeout = next_timeout;
801601c: 4b17 ldr r3, [pc, #92] ; (801607c <sys_check_timeouts+0x6c>)
801601e: 681b ldr r3, [r3, #0]
8016020: 60bb str r3, [r7, #8]
if (tmptimeout == NULL) {
8016022: 68bb ldr r3, [r7, #8]
8016024: 2b00 cmp r3, #0
8016026: d022 beq.n 801606e <sys_check_timeouts+0x5e>
return;
}
if (TIME_LESS_THAN(now, tmptimeout->time)) {
8016028: 68bb ldr r3, [r7, #8]
801602a: 685b ldr r3, [r3, #4]
801602c: 68fa ldr r2, [r7, #12]
801602e: 1ad3 subs r3, r2, r3
8016030: 0fdb lsrs r3, r3, #31
8016032: f003 0301 and.w r3, r3, #1
8016036: b2db uxtb r3, r3
8016038: 2b00 cmp r3, #0
801603a: d11a bne.n 8016072 <sys_check_timeouts+0x62>
return;
}
/* Timeout has expired */
next_timeout = tmptimeout->next;
801603c: 68bb ldr r3, [r7, #8]
801603e: 681b ldr r3, [r3, #0]
8016040: 4a0e ldr r2, [pc, #56] ; (801607c <sys_check_timeouts+0x6c>)
8016042: 6013 str r3, [r2, #0]
handler = tmptimeout->h;
8016044: 68bb ldr r3, [r7, #8]
8016046: 689b ldr r3, [r3, #8]
8016048: 607b str r3, [r7, #4]
arg = tmptimeout->arg;
801604a: 68bb ldr r3, [r7, #8]
801604c: 68db ldr r3, [r3, #12]
801604e: 603b str r3, [r7, #0]
current_timeout_due_time = tmptimeout->time;
8016050: 68bb ldr r3, [r7, #8]
8016052: 685b ldr r3, [r3, #4]
8016054: 4a0a ldr r2, [pc, #40] ; (8016080 <sys_check_timeouts+0x70>)
8016056: 6013 str r3, [r2, #0]
if (handler != NULL) {
LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
}
#endif /* LWIP_DEBUG_TIMERNAMES */
memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
8016058: 68b9 ldr r1, [r7, #8]
801605a: 200a movs r0, #10
801605c: f7f9 fc20 bl 800f8a0 <memp_free>
if (handler != NULL) {
8016060: 687b ldr r3, [r7, #4]
8016062: 2b00 cmp r3, #0
8016064: d0da beq.n 801601c <sys_check_timeouts+0xc>
handler(arg);
8016066: 687b ldr r3, [r7, #4]
8016068: 6838 ldr r0, [r7, #0]
801606a: 4798 blx r3
do {
801606c: e7d6 b.n 801601c <sys_check_timeouts+0xc>
return;
801606e: bf00 nop
8016070: e000 b.n 8016074 <sys_check_timeouts+0x64>
return;
8016072: bf00 nop
}
LWIP_TCPIP_THREAD_ALIVE();
/* Repeat until all expired timers have been called */
} while (1);
}
8016074: 3710 adds r7, #16
8016076: 46bd mov sp, r7
8016078: bd80 pop {r7, pc}
801607a: bf00 nop
801607c: 20008760 .word 0x20008760
8016080: 20008764 .word 0x20008764
08016084 <sys_timeouts_sleeptime>:
/** Return the time left before the next timeout is due. If no timeouts are
* enqueued, returns 0xffffffff
*/
u32_t
sys_timeouts_sleeptime(void)
{
8016084: b580 push {r7, lr}
8016086: b082 sub sp, #8
8016088: af00 add r7, sp, #0
u32_t now;
LWIP_ASSERT_CORE_LOCKED();
if (next_timeout == NULL) {
801608a: 4b16 ldr r3, [pc, #88] ; (80160e4 <sys_timeouts_sleeptime+0x60>)
801608c: 681b ldr r3, [r3, #0]
801608e: 2b00 cmp r3, #0
8016090: d102 bne.n 8016098 <sys_timeouts_sleeptime+0x14>
return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
8016092: f04f 33ff mov.w r3, #4294967295
8016096: e020 b.n 80160da <sys_timeouts_sleeptime+0x56>
}
now = sys_now();
8016098: f7f5 fba8 bl 800b7ec <sys_now>
801609c: 6078 str r0, [r7, #4]
if (TIME_LESS_THAN(next_timeout->time, now)) {
801609e: 4b11 ldr r3, [pc, #68] ; (80160e4 <sys_timeouts_sleeptime+0x60>)
80160a0: 681b ldr r3, [r3, #0]
80160a2: 685a ldr r2, [r3, #4]
80160a4: 687b ldr r3, [r7, #4]
80160a6: 1ad3 subs r3, r2, r3
80160a8: 0fdb lsrs r3, r3, #31
80160aa: f003 0301 and.w r3, r3, #1
80160ae: b2db uxtb r3, r3
80160b0: 2b00 cmp r3, #0
80160b2: d001 beq.n 80160b8 <sys_timeouts_sleeptime+0x34>
return 0;
80160b4: 2300 movs r3, #0
80160b6: e010 b.n 80160da <sys_timeouts_sleeptime+0x56>
} else {
u32_t ret = (u32_t)(next_timeout->time - now);
80160b8: 4b0a ldr r3, [pc, #40] ; (80160e4 <sys_timeouts_sleeptime+0x60>)
80160ba: 681b ldr r3, [r3, #0]
80160bc: 685a ldr r2, [r3, #4]
80160be: 687b ldr r3, [r7, #4]
80160c0: 1ad3 subs r3, r2, r3
80160c2: 603b str r3, [r7, #0]
LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
80160c4: 683b ldr r3, [r7, #0]
80160c6: 2b00 cmp r3, #0
80160c8: da06 bge.n 80160d8 <sys_timeouts_sleeptime+0x54>
80160ca: 4b07 ldr r3, [pc, #28] ; (80160e8 <sys_timeouts_sleeptime+0x64>)
80160cc: f44f 72dc mov.w r2, #440 ; 0x1b8
80160d0: 4906 ldr r1, [pc, #24] ; (80160ec <sys_timeouts_sleeptime+0x68>)
80160d2: 4807 ldr r0, [pc, #28] ; (80160f0 <sys_timeouts_sleeptime+0x6c>)
80160d4: f004 ffa6 bl 801b024 <iprintf>
return ret;
80160d8: 683b ldr r3, [r7, #0]
}
}
80160da: 4618 mov r0, r3
80160dc: 3708 adds r7, #8
80160de: 46bd mov sp, r7
80160e0: bd80 pop {r7, pc}
80160e2: bf00 nop
80160e4: 20008760 .word 0x20008760
80160e8: 0801df5c .word 0x0801df5c
80160ec: 0801e030 .word 0x0801e030
80160f0: 0801dfd0 .word 0x0801dfd0
080160f4 <udp_init>:
/**
* Initialize this module.
*/
void
udp_init(void)
{
80160f4: b580 push {r7, lr}
80160f6: af00 add r7, sp, #0
#ifdef LWIP_RAND
udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
80160f8: f004 ffac bl 801b054 <rand>
80160fc: 4603 mov r3, r0
80160fe: b29b uxth r3, r3
8016100: f3c3 030d ubfx r3, r3, #0, #14
8016104: b29b uxth r3, r3
8016106: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
801610a: b29a uxth r2, r3
801610c: 4b01 ldr r3, [pc, #4] ; (8016114 <udp_init+0x20>)
801610e: 801a strh r2, [r3, #0]
#endif /* LWIP_RAND */
}
8016110: bf00 nop
8016112: bd80 pop {r7, pc}
8016114: 2000007c .word 0x2000007c
08016118 <udp_new_port>:
*
* @return a new (free) local UDP port number
*/
static u16_t
udp_new_port(void)
{
8016118: b480 push {r7}
801611a: b083 sub sp, #12
801611c: af00 add r7, sp, #0
u16_t n = 0;
801611e: 2300 movs r3, #0
8016120: 80fb strh r3, [r7, #6]
struct udp_pcb *pcb;
again:
if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
8016122: 4b17 ldr r3, [pc, #92] ; (8016180 <udp_new_port+0x68>)
8016124: 881b ldrh r3, [r3, #0]
8016126: 1c5a adds r2, r3, #1
8016128: b291 uxth r1, r2
801612a: 4a15 ldr r2, [pc, #84] ; (8016180 <udp_new_port+0x68>)
801612c: 8011 strh r1, [r2, #0]
801612e: f64f 72ff movw r2, #65535 ; 0xffff
8016132: 4293 cmp r3, r2
8016134: d103 bne.n 801613e <udp_new_port+0x26>
udp_port = UDP_LOCAL_PORT_RANGE_START;
8016136: 4b12 ldr r3, [pc, #72] ; (8016180 <udp_new_port+0x68>)
8016138: f44f 4240 mov.w r2, #49152 ; 0xc000
801613c: 801a strh r2, [r3, #0]
}
/* Check all PCBs. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
801613e: 4b11 ldr r3, [pc, #68] ; (8016184 <udp_new_port+0x6c>)
8016140: 681b ldr r3, [r3, #0]
8016142: 603b str r3, [r7, #0]
8016144: e011 b.n 801616a <udp_new_port+0x52>
if (pcb->local_port == udp_port) {
8016146: 683b ldr r3, [r7, #0]
8016148: 8a5a ldrh r2, [r3, #18]
801614a: 4b0d ldr r3, [pc, #52] ; (8016180 <udp_new_port+0x68>)
801614c: 881b ldrh r3, [r3, #0]
801614e: 429a cmp r2, r3
8016150: d108 bne.n 8016164 <udp_new_port+0x4c>
if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
8016152: 88fb ldrh r3, [r7, #6]
8016154: 3301 adds r3, #1
8016156: 80fb strh r3, [r7, #6]
8016158: 88fb ldrh r3, [r7, #6]
801615a: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
801615e: d3e0 bcc.n 8016122 <udp_new_port+0xa>
return 0;
8016160: 2300 movs r3, #0
8016162: e007 b.n 8016174 <udp_new_port+0x5c>
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016164: 683b ldr r3, [r7, #0]
8016166: 68db ldr r3, [r3, #12]
8016168: 603b str r3, [r7, #0]
801616a: 683b ldr r3, [r7, #0]
801616c: 2b00 cmp r3, #0
801616e: d1ea bne.n 8016146 <udp_new_port+0x2e>
}
goto again;
}
}
return udp_port;
8016170: 4b03 ldr r3, [pc, #12] ; (8016180 <udp_new_port+0x68>)
8016172: 881b ldrh r3, [r3, #0]
}
8016174: 4618 mov r0, r3
8016176: 370c adds r7, #12
8016178: 46bd mov sp, r7
801617a: f85d 7b04 ldr.w r7, [sp], #4
801617e: 4770 bx lr
8016180: 2000007c .word 0x2000007c
8016184: 2000f5d8 .word 0x2000f5d8
08016188 <udp_input_local_match>:
* @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
* @return 1 on match, 0 otherwise
*/
static u8_t
udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
{
8016188: b580 push {r7, lr}
801618a: b084 sub sp, #16
801618c: af00 add r7, sp, #0
801618e: 60f8 str r0, [r7, #12]
8016190: 60b9 str r1, [r7, #8]
8016192: 4613 mov r3, r2
8016194: 71fb strb r3, [r7, #7]
LWIP_UNUSED_ARG(inp); /* in IPv6 only case */
LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
8016196: 68fb ldr r3, [r7, #12]
8016198: 2b00 cmp r3, #0
801619a: d105 bne.n 80161a8 <udp_input_local_match+0x20>
801619c: 4b27 ldr r3, [pc, #156] ; (801623c <udp_input_local_match+0xb4>)
801619e: 2287 movs r2, #135 ; 0x87
80161a0: 4927 ldr r1, [pc, #156] ; (8016240 <udp_input_local_match+0xb8>)
80161a2: 4828 ldr r0, [pc, #160] ; (8016244 <udp_input_local_match+0xbc>)
80161a4: f004 ff3e bl 801b024 <iprintf>
LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
80161a8: 68bb ldr r3, [r7, #8]
80161aa: 2b00 cmp r3, #0
80161ac: d105 bne.n 80161ba <udp_input_local_match+0x32>
80161ae: 4b23 ldr r3, [pc, #140] ; (801623c <udp_input_local_match+0xb4>)
80161b0: 2288 movs r2, #136 ; 0x88
80161b2: 4925 ldr r1, [pc, #148] ; (8016248 <udp_input_local_match+0xc0>)
80161b4: 4823 ldr r0, [pc, #140] ; (8016244 <udp_input_local_match+0xbc>)
80161b6: f004 ff35 bl 801b024 <iprintf>
/* check if PCB is bound to specific netif */
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80161ba: 68fb ldr r3, [r7, #12]
80161bc: 7a1b ldrb r3, [r3, #8]
80161be: 2b00 cmp r3, #0
80161c0: d00b beq.n 80161da <udp_input_local_match+0x52>
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
80161c2: 68fb ldr r3, [r7, #12]
80161c4: 7a1a ldrb r2, [r3, #8]
80161c6: 4b21 ldr r3, [pc, #132] ; (801624c <udp_input_local_match+0xc4>)
80161c8: 685b ldr r3, [r3, #4]
80161ca: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80161ce: 3301 adds r3, #1
80161d0: b2db uxtb r3, r3
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
80161d2: 429a cmp r2, r3
80161d4: d001 beq.n 80161da <udp_input_local_match+0x52>
return 0;
80161d6: 2300 movs r3, #0
80161d8: e02b b.n 8016232 <udp_input_local_match+0xaa>
/* Only need to check PCB if incoming IP version matches PCB IP version */
if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
#if LWIP_IPV4
/* Special case: IPv4 broadcast: all or broadcasts in my subnet
* Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
if (broadcast != 0) {
80161da: 79fb ldrb r3, [r7, #7]
80161dc: 2b00 cmp r3, #0
80161de: d018 beq.n 8016212 <udp_input_local_match+0x8a>
#if IP_SOF_BROADCAST_RECV
if (ip_get_option(pcb, SOF_BROADCAST))
#endif /* IP_SOF_BROADCAST_RECV */
{
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80161e0: 68fb ldr r3, [r7, #12]
80161e2: 2b00 cmp r3, #0
80161e4: d013 beq.n 801620e <udp_input_local_match+0x86>
80161e6: 68fb ldr r3, [r7, #12]
80161e8: 681b ldr r3, [r3, #0]
80161ea: 2b00 cmp r3, #0
80161ec: d00f beq.n 801620e <udp_input_local_match+0x86>
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
80161ee: 4b17 ldr r3, [pc, #92] ; (801624c <udp_input_local_match+0xc4>)
80161f0: 695b ldr r3, [r3, #20]
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80161f2: f1b3 3fff cmp.w r3, #4294967295
80161f6: d00a beq.n 801620e <udp_input_local_match+0x86>
ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
80161f8: 68fb ldr r3, [r7, #12]
80161fa: 681a ldr r2, [r3, #0]
80161fc: 4b13 ldr r3, [pc, #76] ; (801624c <udp_input_local_match+0xc4>)
80161fe: 695b ldr r3, [r3, #20]
8016200: 405a eors r2, r3
8016202: 68bb ldr r3, [r7, #8]
8016204: 3308 adds r3, #8
8016206: 681b ldr r3, [r3, #0]
8016208: 4013 ands r3, r2
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
801620a: 2b00 cmp r3, #0
801620c: d110 bne.n 8016230 <udp_input_local_match+0xa8>
return 1;
801620e: 2301 movs r3, #1
8016210: e00f b.n 8016232 <udp_input_local_match+0xaa>
}
}
} else
#endif /* LWIP_IPV4 */
/* Handle IPv4 and IPv6: all or exact match */
if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
8016212: 68fb ldr r3, [r7, #12]
8016214: 2b00 cmp r3, #0
8016216: d009 beq.n 801622c <udp_input_local_match+0xa4>
8016218: 68fb ldr r3, [r7, #12]
801621a: 681b ldr r3, [r3, #0]
801621c: 2b00 cmp r3, #0
801621e: d005 beq.n 801622c <udp_input_local_match+0xa4>
8016220: 68fb ldr r3, [r7, #12]
8016222: 681a ldr r2, [r3, #0]
8016224: 4b09 ldr r3, [pc, #36] ; (801624c <udp_input_local_match+0xc4>)
8016226: 695b ldr r3, [r3, #20]
8016228: 429a cmp r2, r3
801622a: d101 bne.n 8016230 <udp_input_local_match+0xa8>
return 1;
801622c: 2301 movs r3, #1
801622e: e000 b.n 8016232 <udp_input_local_match+0xaa>
}
}
return 0;
8016230: 2300 movs r3, #0
}
8016232: 4618 mov r0, r3
8016234: 3710 adds r7, #16
8016236: 46bd mov sp, r7
8016238: bd80 pop {r7, pc}
801623a: bf00 nop
801623c: 0801e044 .word 0x0801e044
8016240: 0801e074 .word 0x0801e074
8016244: 0801e098 .word 0x0801e098
8016248: 0801e0c0 .word 0x0801e0c0
801624c: 2000be8c .word 0x2000be8c
08016250 <udp_input>:
* @param inp network interface on which the datagram was received.
*
*/
void
udp_input(struct pbuf *p, struct netif *inp)
{
8016250: b590 push {r4, r7, lr}
8016252: b08d sub sp, #52 ; 0x34
8016254: af02 add r7, sp, #8
8016256: 6078 str r0, [r7, #4]
8016258: 6039 str r1, [r7, #0]
struct udp_hdr *udphdr;
struct udp_pcb *pcb, *prev;
struct udp_pcb *uncon_pcb;
u16_t src, dest;
u8_t broadcast;
u8_t for_us = 0;
801625a: 2300 movs r3, #0
801625c: 76fb strb r3, [r7, #27]
LWIP_UNUSED_ARG(inp);
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
801625e: 687b ldr r3, [r7, #4]
8016260: 2b00 cmp r3, #0
8016262: d105 bne.n 8016270 <udp_input+0x20>
8016264: 4b7c ldr r3, [pc, #496] ; (8016458 <udp_input+0x208>)
8016266: 22cf movs r2, #207 ; 0xcf
8016268: 497c ldr r1, [pc, #496] ; (801645c <udp_input+0x20c>)
801626a: 487d ldr r0, [pc, #500] ; (8016460 <udp_input+0x210>)
801626c: f004 feda bl 801b024 <iprintf>
LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
8016270: 683b ldr r3, [r7, #0]
8016272: 2b00 cmp r3, #0
8016274: d105 bne.n 8016282 <udp_input+0x32>
8016276: 4b78 ldr r3, [pc, #480] ; (8016458 <udp_input+0x208>)
8016278: 22d0 movs r2, #208 ; 0xd0
801627a: 497a ldr r1, [pc, #488] ; (8016464 <udp_input+0x214>)
801627c: 4878 ldr r0, [pc, #480] ; (8016460 <udp_input+0x210>)
801627e: f004 fed1 bl 801b024 <iprintf>
PERF_START;
UDP_STATS_INC(udp.recv);
/* Check minimum length (UDP header) */
if (p->len < UDP_HLEN) {
8016282: 687b ldr r3, [r7, #4]
8016284: 895b ldrh r3, [r3, #10]
8016286: 2b07 cmp r3, #7
8016288: d803 bhi.n 8016292 <udp_input+0x42>
LWIP_DEBUGF(UDP_DEBUG,
("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
UDP_STATS_INC(udp.lenerr);
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
801628a: 6878 ldr r0, [r7, #4]
801628c: f7fa f9b4 bl 80105f8 <pbuf_free>
goto end;
8016290: e0de b.n 8016450 <udp_input+0x200>
}
udphdr = (struct udp_hdr *)p->payload;
8016292: 687b ldr r3, [r7, #4]
8016294: 685b ldr r3, [r3, #4]
8016296: 617b str r3, [r7, #20]
/* is broadcast packet ? */
broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
8016298: 4b73 ldr r3, [pc, #460] ; (8016468 <udp_input+0x218>)
801629a: 695a ldr r2, [r3, #20]
801629c: 4b72 ldr r3, [pc, #456] ; (8016468 <udp_input+0x218>)
801629e: 681b ldr r3, [r3, #0]
80162a0: 4619 mov r1, r3
80162a2: 4610 mov r0, r2
80162a4: f003 fe16 bl 8019ed4 <ip4_addr_isbroadcast_u32>
80162a8: 4603 mov r3, r0
80162aa: 74fb strb r3, [r7, #19]
LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
/* convert src and dest ports to host byte order */
src = lwip_ntohs(udphdr->src);
80162ac: 697b ldr r3, [r7, #20]
80162ae: 881b ldrh r3, [r3, #0]
80162b0: b29b uxth r3, r3
80162b2: 4618 mov r0, r3
80162b4: f7f8 fdec bl 800ee90 <lwip_htons>
80162b8: 4603 mov r3, r0
80162ba: 823b strh r3, [r7, #16]
dest = lwip_ntohs(udphdr->dest);
80162bc: 697b ldr r3, [r7, #20]
80162be: 885b ldrh r3, [r3, #2]
80162c0: b29b uxth r3, r3
80162c2: 4618 mov r0, r3
80162c4: f7f8 fde4 bl 800ee90 <lwip_htons>
80162c8: 4603 mov r3, r0
80162ca: 81fb strh r3, [r7, #14]
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
pcb = NULL;
80162cc: 2300 movs r3, #0
80162ce: 627b str r3, [r7, #36] ; 0x24
prev = NULL;
80162d0: 2300 movs r3, #0
80162d2: 623b str r3, [r7, #32]
uncon_pcb = NULL;
80162d4: 2300 movs r3, #0
80162d6: 61fb str r3, [r7, #28]
/* Iterate through the UDP pcb list for a matching pcb.
* 'Perfect match' pcbs (connected to the remote port & ip address) are
* preferred. If no perfect match is found, the first unconnected pcb that
* matches the local port and ip address gets the datagram. */
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
80162d8: 4b64 ldr r3, [pc, #400] ; (801646c <udp_input+0x21c>)
80162da: 681b ldr r3, [r3, #0]
80162dc: 627b str r3, [r7, #36] ; 0x24
80162de: e054 b.n 801638a <udp_input+0x13a>
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
/* compare PCB local addr+port to UDP destination addr+port */
if ((pcb->local_port == dest) &&
80162e0: 6a7b ldr r3, [r7, #36] ; 0x24
80162e2: 8a5b ldrh r3, [r3, #18]
80162e4: 89fa ldrh r2, [r7, #14]
80162e6: 429a cmp r2, r3
80162e8: d14a bne.n 8016380 <udp_input+0x130>
(udp_input_local_match(pcb, inp, broadcast) != 0)) {
80162ea: 7cfb ldrb r3, [r7, #19]
80162ec: 461a mov r2, r3
80162ee: 6839 ldr r1, [r7, #0]
80162f0: 6a78 ldr r0, [r7, #36] ; 0x24
80162f2: f7ff ff49 bl 8016188 <udp_input_local_match>
80162f6: 4603 mov r3, r0
if ((pcb->local_port == dest) &&
80162f8: 2b00 cmp r3, #0
80162fa: d041 beq.n 8016380 <udp_input+0x130>
if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
80162fc: 6a7b ldr r3, [r7, #36] ; 0x24
80162fe: 7c1b ldrb r3, [r3, #16]
8016300: f003 0304 and.w r3, r3, #4
8016304: 2b00 cmp r3, #0
8016306: d11d bne.n 8016344 <udp_input+0xf4>
if (uncon_pcb == NULL) {
8016308: 69fb ldr r3, [r7, #28]
801630a: 2b00 cmp r3, #0
801630c: d102 bne.n 8016314 <udp_input+0xc4>
/* the first unconnected matching PCB */
uncon_pcb = pcb;
801630e: 6a7b ldr r3, [r7, #36] ; 0x24
8016310: 61fb str r3, [r7, #28]
8016312: e017 b.n 8016344 <udp_input+0xf4>
#if LWIP_IPV4
} else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
8016314: 7cfb ldrb r3, [r7, #19]
8016316: 2b00 cmp r3, #0
8016318: d014 beq.n 8016344 <udp_input+0xf4>
801631a: 4b53 ldr r3, [pc, #332] ; (8016468 <udp_input+0x218>)
801631c: 695b ldr r3, [r3, #20]
801631e: f1b3 3fff cmp.w r3, #4294967295
8016322: d10f bne.n 8016344 <udp_input+0xf4>
/* global broadcast address (only valid for IPv4; match was checked before) */
if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
8016324: 69fb ldr r3, [r7, #28]
8016326: 681a ldr r2, [r3, #0]
8016328: 683b ldr r3, [r7, #0]
801632a: 3304 adds r3, #4
801632c: 681b ldr r3, [r3, #0]
801632e: 429a cmp r2, r3
8016330: d008 beq.n 8016344 <udp_input+0xf4>
/* uncon_pcb does not match the input netif, check this pcb */
if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
8016332: 6a7b ldr r3, [r7, #36] ; 0x24
8016334: 681a ldr r2, [r3, #0]
8016336: 683b ldr r3, [r7, #0]
8016338: 3304 adds r3, #4
801633a: 681b ldr r3, [r3, #0]
801633c: 429a cmp r2, r3
801633e: d101 bne.n 8016344 <udp_input+0xf4>
/* better match */
uncon_pcb = pcb;
8016340: 6a7b ldr r3, [r7, #36] ; 0x24
8016342: 61fb str r3, [r7, #28]
}
#endif /* SO_REUSE */
}
/* compare PCB remote addr+port to UDP source addr+port */
if ((pcb->remote_port == src) &&
8016344: 6a7b ldr r3, [r7, #36] ; 0x24
8016346: 8a9b ldrh r3, [r3, #20]
8016348: 8a3a ldrh r2, [r7, #16]
801634a: 429a cmp r2, r3
801634c: d118 bne.n 8016380 <udp_input+0x130>
(ip_addr_isany_val(pcb->remote_ip) ||
801634e: 6a7b ldr r3, [r7, #36] ; 0x24
8016350: 685b ldr r3, [r3, #4]
if ((pcb->remote_port == src) &&
8016352: 2b00 cmp r3, #0
8016354: d005 beq.n 8016362 <udp_input+0x112>
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
8016356: 6a7b ldr r3, [r7, #36] ; 0x24
8016358: 685a ldr r2, [r3, #4]
801635a: 4b43 ldr r3, [pc, #268] ; (8016468 <udp_input+0x218>)
801635c: 691b ldr r3, [r3, #16]
(ip_addr_isany_val(pcb->remote_ip) ||
801635e: 429a cmp r2, r3
8016360: d10e bne.n 8016380 <udp_input+0x130>
/* the first fully matching PCB */
if (prev != NULL) {
8016362: 6a3b ldr r3, [r7, #32]
8016364: 2b00 cmp r3, #0
8016366: d014 beq.n 8016392 <udp_input+0x142>
/* move the pcb to the front of udp_pcbs so that is
found faster next time */
prev->next = pcb->next;
8016368: 6a7b ldr r3, [r7, #36] ; 0x24
801636a: 68da ldr r2, [r3, #12]
801636c: 6a3b ldr r3, [r7, #32]
801636e: 60da str r2, [r3, #12]
pcb->next = udp_pcbs;
8016370: 4b3e ldr r3, [pc, #248] ; (801646c <udp_input+0x21c>)
8016372: 681a ldr r2, [r3, #0]
8016374: 6a7b ldr r3, [r7, #36] ; 0x24
8016376: 60da str r2, [r3, #12]
udp_pcbs = pcb;
8016378: 4a3c ldr r2, [pc, #240] ; (801646c <udp_input+0x21c>)
801637a: 6a7b ldr r3, [r7, #36] ; 0x24
801637c: 6013 str r3, [r2, #0]
} else {
UDP_STATS_INC(udp.cachehit);
}
break;
801637e: e008 b.n 8016392 <udp_input+0x142>
}
}
prev = pcb;
8016380: 6a7b ldr r3, [r7, #36] ; 0x24
8016382: 623b str r3, [r7, #32]
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
8016384: 6a7b ldr r3, [r7, #36] ; 0x24
8016386: 68db ldr r3, [r3, #12]
8016388: 627b str r3, [r7, #36] ; 0x24
801638a: 6a7b ldr r3, [r7, #36] ; 0x24
801638c: 2b00 cmp r3, #0
801638e: d1a7 bne.n 80162e0 <udp_input+0x90>
8016390: e000 b.n 8016394 <udp_input+0x144>
break;
8016392: bf00 nop
}
/* no fully matching pcb found? then look for an unconnected pcb */
if (pcb == NULL) {
8016394: 6a7b ldr r3, [r7, #36] ; 0x24
8016396: 2b00 cmp r3, #0
8016398: d101 bne.n 801639e <udp_input+0x14e>
pcb = uncon_pcb;
801639a: 69fb ldr r3, [r7, #28]
801639c: 627b str r3, [r7, #36] ; 0x24
}
/* Check checksum if this is a match or if it was directed at us. */
if (pcb != NULL) {
801639e: 6a7b ldr r3, [r7, #36] ; 0x24
80163a0: 2b00 cmp r3, #0
80163a2: d002 beq.n 80163aa <udp_input+0x15a>
for_us = 1;
80163a4: 2301 movs r3, #1
80163a6: 76fb strb r3, [r7, #27]
80163a8: e00a b.n 80163c0 <udp_input+0x170>
for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
}
#endif /* LWIP_IPV6 */
#if LWIP_IPV4
if (!ip_current_is_v6()) {
for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
80163aa: 683b ldr r3, [r7, #0]
80163ac: 3304 adds r3, #4
80163ae: 681a ldr r2, [r3, #0]
80163b0: 4b2d ldr r3, [pc, #180] ; (8016468 <udp_input+0x218>)
80163b2: 695b ldr r3, [r3, #20]
80163b4: 429a cmp r2, r3
80163b6: bf0c ite eq
80163b8: 2301 moveq r3, #1
80163ba: 2300 movne r3, #0
80163bc: b2db uxtb r3, r3
80163be: 76fb strb r3, [r7, #27]
}
#endif /* LWIP_IPV4 */
}
if (for_us) {
80163c0: 7efb ldrb r3, [r7, #27]
80163c2: 2b00 cmp r3, #0
80163c4: d041 beq.n 801644a <udp_input+0x1fa>
}
}
}
}
#endif /* CHECKSUM_CHECK_UDP */
if (pbuf_remove_header(p, UDP_HLEN)) {
80163c6: 2108 movs r1, #8
80163c8: 6878 ldr r0, [r7, #4]
80163ca: f7fa f88f bl 80104ec <pbuf_remove_header>
80163ce: 4603 mov r3, r0
80163d0: 2b00 cmp r3, #0
80163d2: d00a beq.n 80163ea <udp_input+0x19a>
/* Can we cope with this failing? Just assert for now */
LWIP_ASSERT("pbuf_remove_header failed\n", 0);
80163d4: 4b20 ldr r3, [pc, #128] ; (8016458 <udp_input+0x208>)
80163d6: f44f 72b8 mov.w r2, #368 ; 0x170
80163da: 4925 ldr r1, [pc, #148] ; (8016470 <udp_input+0x220>)
80163dc: 4820 ldr r0, [pc, #128] ; (8016460 <udp_input+0x210>)
80163de: f004 fe21 bl 801b024 <iprintf>
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
80163e2: 6878 ldr r0, [r7, #4]
80163e4: f7fa f908 bl 80105f8 <pbuf_free>
goto end;
80163e8: e032 b.n 8016450 <udp_input+0x200>
}
if (pcb != NULL) {
80163ea: 6a7b ldr r3, [r7, #36] ; 0x24
80163ec: 2b00 cmp r3, #0
80163ee: d012 beq.n 8016416 <udp_input+0x1c6>
}
}
}
#endif /* SO_REUSE && SO_REUSE_RXTOALL */
/* callback */
if (pcb->recv != NULL) {
80163f0: 6a7b ldr r3, [r7, #36] ; 0x24
80163f2: 699b ldr r3, [r3, #24]
80163f4: 2b00 cmp r3, #0
80163f6: d00a beq.n 801640e <udp_input+0x1be>
/* now the recv function is responsible for freeing p */
pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
80163f8: 6a7b ldr r3, [r7, #36] ; 0x24
80163fa: 699c ldr r4, [r3, #24]
80163fc: 6a7b ldr r3, [r7, #36] ; 0x24
80163fe: 69d8 ldr r0, [r3, #28]
8016400: 8a3b ldrh r3, [r7, #16]
8016402: 9300 str r3, [sp, #0]
8016404: 4b1b ldr r3, [pc, #108] ; (8016474 <udp_input+0x224>)
8016406: 687a ldr r2, [r7, #4]
8016408: 6a79 ldr r1, [r7, #36] ; 0x24
801640a: 47a0 blx r4
} else {
pbuf_free(p);
}
end:
PERF_STOP("udp_input");
return;
801640c: e021 b.n 8016452 <udp_input+0x202>
pbuf_free(p);
801640e: 6878 ldr r0, [r7, #4]
8016410: f7fa f8f2 bl 80105f8 <pbuf_free>
goto end;
8016414: e01c b.n 8016450 <udp_input+0x200>
if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
8016416: 7cfb ldrb r3, [r7, #19]
8016418: 2b00 cmp r3, #0
801641a: d112 bne.n 8016442 <udp_input+0x1f2>
801641c: 4b12 ldr r3, [pc, #72] ; (8016468 <udp_input+0x218>)
801641e: 695b ldr r3, [r3, #20]
8016420: f003 03f0 and.w r3, r3, #240 ; 0xf0
8016424: 2be0 cmp r3, #224 ; 0xe0
8016426: d00c beq.n 8016442 <udp_input+0x1f2>
pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
8016428: 4b0f ldr r3, [pc, #60] ; (8016468 <udp_input+0x218>)
801642a: 899b ldrh r3, [r3, #12]
801642c: 3308 adds r3, #8
801642e: b29b uxth r3, r3
8016430: b21b sxth r3, r3
8016432: 4619 mov r1, r3
8016434: 6878 ldr r0, [r7, #4]
8016436: f7fa f8cc bl 80105d2 <pbuf_header_force>
icmp_port_unreach(ip_current_is_v6(), p);
801643a: 2103 movs r1, #3
801643c: 6878 ldr r0, [r7, #4]
801643e: f003 fa0d bl 801985c <icmp_dest_unreach>
pbuf_free(p);
8016442: 6878 ldr r0, [r7, #4]
8016444: f7fa f8d8 bl 80105f8 <pbuf_free>
return;
8016448: e003 b.n 8016452 <udp_input+0x202>
pbuf_free(p);
801644a: 6878 ldr r0, [r7, #4]
801644c: f7fa f8d4 bl 80105f8 <pbuf_free>
return;
8016450: bf00 nop
UDP_STATS_INC(udp.drop);
MIB2_STATS_INC(mib2.udpinerrors);
pbuf_free(p);
PERF_STOP("udp_input");
#endif /* CHECKSUM_CHECK_UDP */
}
8016452: 372c adds r7, #44 ; 0x2c
8016454: 46bd mov sp, r7
8016456: bd90 pop {r4, r7, pc}
8016458: 0801e044 .word 0x0801e044
801645c: 0801e0e8 .word 0x0801e0e8
8016460: 0801e098 .word 0x0801e098
8016464: 0801e100 .word 0x0801e100
8016468: 2000be8c .word 0x2000be8c
801646c: 2000f5d8 .word 0x2000f5d8
8016470: 0801e11c .word 0x0801e11c
8016474: 2000be9c .word 0x2000be9c
08016478 <udp_sendto_if>:
* @see udp_disconnect() udp_send()
*/
err_t
udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
{
8016478: b580 push {r7, lr}
801647a: b088 sub sp, #32
801647c: af02 add r7, sp, #8
801647e: 60f8 str r0, [r7, #12]
8016480: 60b9 str r1, [r7, #8]
8016482: 607a str r2, [r7, #4]
8016484: 807b strh r3, [r7, #2]
u16_t chksum)
{
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
const ip_addr_t *src_ip;
LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG);
8016486: 68fb ldr r3, [r7, #12]
8016488: 2b00 cmp r3, #0
801648a: d109 bne.n 80164a0 <udp_sendto_if+0x28>
801648c: 4b2e ldr r3, [pc, #184] ; (8016548 <udp_sendto_if+0xd0>)
801648e: f44f 7220 mov.w r2, #640 ; 0x280
8016492: 492e ldr r1, [pc, #184] ; (801654c <udp_sendto_if+0xd4>)
8016494: 482e ldr r0, [pc, #184] ; (8016550 <udp_sendto_if+0xd8>)
8016496: f004 fdc5 bl 801b024 <iprintf>
801649a: f06f 030f mvn.w r3, #15
801649e: e04f b.n 8016540 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG);
80164a0: 68bb ldr r3, [r7, #8]
80164a2: 2b00 cmp r3, #0
80164a4: d109 bne.n 80164ba <udp_sendto_if+0x42>
80164a6: 4b28 ldr r3, [pc, #160] ; (8016548 <udp_sendto_if+0xd0>)
80164a8: f240 2281 movw r2, #641 ; 0x281
80164ac: 4929 ldr r1, [pc, #164] ; (8016554 <udp_sendto_if+0xdc>)
80164ae: 4828 ldr r0, [pc, #160] ; (8016550 <udp_sendto_if+0xd8>)
80164b0: f004 fdb8 bl 801b024 <iprintf>
80164b4: f06f 030f mvn.w r3, #15
80164b8: e042 b.n 8016540 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
80164ba: 687b ldr r3, [r7, #4]
80164bc: 2b00 cmp r3, #0
80164be: d109 bne.n 80164d4 <udp_sendto_if+0x5c>
80164c0: 4b21 ldr r3, [pc, #132] ; (8016548 <udp_sendto_if+0xd0>)
80164c2: f240 2282 movw r2, #642 ; 0x282
80164c6: 4924 ldr r1, [pc, #144] ; (8016558 <udp_sendto_if+0xe0>)
80164c8: 4821 ldr r0, [pc, #132] ; (8016550 <udp_sendto_if+0xd8>)
80164ca: f004 fdab bl 801b024 <iprintf>
80164ce: f06f 030f mvn.w r3, #15
80164d2: e035 b.n 8016540 <udp_sendto_if+0xc8>
LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG);
80164d4: 6a3b ldr r3, [r7, #32]
80164d6: 2b00 cmp r3, #0
80164d8: d109 bne.n 80164ee <udp_sendto_if+0x76>
80164da: 4b1b ldr r3, [pc, #108] ; (8016548 <udp_sendto_if+0xd0>)
80164dc: f240 2283 movw r2, #643 ; 0x283
80164e0: 491e ldr r1, [pc, #120] ; (801655c <udp_sendto_if+0xe4>)
80164e2: 481b ldr r0, [pc, #108] ; (8016550 <udp_sendto_if+0xd8>)
80164e4: f004 fd9e bl 801b024 <iprintf>
80164e8: f06f 030f mvn.w r3, #15
80164ec: e028 b.n 8016540 <udp_sendto_if+0xc8>
#endif /* LWIP_IPV6 */
#if LWIP_IPV4 && LWIP_IPV6
else
#endif /* LWIP_IPV4 && LWIP_IPV6 */
#if LWIP_IPV4
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
80164ee: 68fb ldr r3, [r7, #12]
80164f0: 2b00 cmp r3, #0
80164f2: d009 beq.n 8016508 <udp_sendto_if+0x90>
80164f4: 68fb ldr r3, [r7, #12]
80164f6: 681b ldr r3, [r3, #0]
80164f8: 2b00 cmp r3, #0
80164fa: d005 beq.n 8016508 <udp_sendto_if+0x90>
ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) {
80164fc: 68fb ldr r3, [r7, #12]
80164fe: 681b ldr r3, [r3, #0]
8016500: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
8016504: 2be0 cmp r3, #224 ; 0xe0
8016506: d103 bne.n 8016510 <udp_sendto_if+0x98>
/* if the local_ip is any or multicast
* use the outgoing network interface IP address as source address */
src_ip = netif_ip_addr4(netif);
8016508: 6a3b ldr r3, [r7, #32]
801650a: 3304 adds r3, #4
801650c: 617b str r3, [r7, #20]
801650e: e00b b.n 8016528 <udp_sendto_if+0xb0>
} else {
/* check if UDP PCB local IP address is correct
* this could be an old address if netif->ip_addr has changed */
if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) {
8016510: 68fb ldr r3, [r7, #12]
8016512: 681a ldr r2, [r3, #0]
8016514: 6a3b ldr r3, [r7, #32]
8016516: 3304 adds r3, #4
8016518: 681b ldr r3, [r3, #0]
801651a: 429a cmp r2, r3
801651c: d002 beq.n 8016524 <udp_sendto_if+0xac>
/* local_ip doesn't match, drop the packet */
return ERR_RTE;
801651e: f06f 0303 mvn.w r3, #3
8016522: e00d b.n 8016540 <udp_sendto_if+0xc8>
}
/* use UDP PCB local IP address as source address */
src_ip = &pcb->local_ip;
8016524: 68fb ldr r3, [r7, #12]
8016526: 617b str r3, [r7, #20]
}
#endif /* LWIP_IPV4 */
#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip);
#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip);
8016528: 887a ldrh r2, [r7, #2]
801652a: 697b ldr r3, [r7, #20]
801652c: 9301 str r3, [sp, #4]
801652e: 6a3b ldr r3, [r7, #32]
8016530: 9300 str r3, [sp, #0]
8016532: 4613 mov r3, r2
8016534: 687a ldr r2, [r7, #4]
8016536: 68b9 ldr r1, [r7, #8]
8016538: 68f8 ldr r0, [r7, #12]
801653a: f000 f811 bl 8016560 <udp_sendto_if_src>
801653e: 4603 mov r3, r0
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
}
8016540: 4618 mov r0, r3
8016542: 3718 adds r7, #24
8016544: 46bd mov sp, r7
8016546: bd80 pop {r7, pc}
8016548: 0801e044 .word 0x0801e044
801654c: 0801e1b8 .word 0x0801e1b8
8016550: 0801e098 .word 0x0801e098
8016554: 0801e1d4 .word 0x0801e1d4
8016558: 0801e1f0 .word 0x0801e1f0
801655c: 0801e210 .word 0x0801e210
08016560 <udp_sendto_if_src>:
/** @ingroup udp_raw
* Same as @ref udp_sendto_if, but with source address */
err_t
udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip)
{
8016560: b580 push {r7, lr}
8016562: b08c sub sp, #48 ; 0x30
8016564: af04 add r7, sp, #16
8016566: 60f8 str r0, [r7, #12]
8016568: 60b9 str r1, [r7, #8]
801656a: 607a str r2, [r7, #4]
801656c: 807b strh r3, [r7, #2]
u8_t ip_proto;
u8_t ttl;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG);
801656e: 68fb ldr r3, [r7, #12]
8016570: 2b00 cmp r3, #0
8016572: d109 bne.n 8016588 <udp_sendto_if_src+0x28>
8016574: 4b65 ldr r3, [pc, #404] ; (801670c <udp_sendto_if_src+0x1ac>)
8016576: f240 22d1 movw r2, #721 ; 0x2d1
801657a: 4965 ldr r1, [pc, #404] ; (8016710 <udp_sendto_if_src+0x1b0>)
801657c: 4865 ldr r0, [pc, #404] ; (8016714 <udp_sendto_if_src+0x1b4>)
801657e: f004 fd51 bl 801b024 <iprintf>
8016582: f06f 030f mvn.w r3, #15
8016586: e0bc b.n 8016702 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG);
8016588: 68bb ldr r3, [r7, #8]
801658a: 2b00 cmp r3, #0
801658c: d109 bne.n 80165a2 <udp_sendto_if_src+0x42>
801658e: 4b5f ldr r3, [pc, #380] ; (801670c <udp_sendto_if_src+0x1ac>)
8016590: f240 22d2 movw r2, #722 ; 0x2d2
8016594: 4960 ldr r1, [pc, #384] ; (8016718 <udp_sendto_if_src+0x1b8>)
8016596: 485f ldr r0, [pc, #380] ; (8016714 <udp_sendto_if_src+0x1b4>)
8016598: f004 fd44 bl 801b024 <iprintf>
801659c: f06f 030f mvn.w r3, #15
80165a0: e0af b.n 8016702 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
80165a2: 687b ldr r3, [r7, #4]
80165a4: 2b00 cmp r3, #0
80165a6: d109 bne.n 80165bc <udp_sendto_if_src+0x5c>
80165a8: 4b58 ldr r3, [pc, #352] ; (801670c <udp_sendto_if_src+0x1ac>)
80165aa: f240 22d3 movw r2, #723 ; 0x2d3
80165ae: 495b ldr r1, [pc, #364] ; (801671c <udp_sendto_if_src+0x1bc>)
80165b0: 4858 ldr r0, [pc, #352] ; (8016714 <udp_sendto_if_src+0x1b4>)
80165b2: f004 fd37 bl 801b024 <iprintf>
80165b6: f06f 030f mvn.w r3, #15
80165ba: e0a2 b.n 8016702 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG);
80165bc: 6afb ldr r3, [r7, #44] ; 0x2c
80165be: 2b00 cmp r3, #0
80165c0: d109 bne.n 80165d6 <udp_sendto_if_src+0x76>
80165c2: 4b52 ldr r3, [pc, #328] ; (801670c <udp_sendto_if_src+0x1ac>)
80165c4: f44f 7235 mov.w r2, #724 ; 0x2d4
80165c8: 4955 ldr r1, [pc, #340] ; (8016720 <udp_sendto_if_src+0x1c0>)
80165ca: 4852 ldr r0, [pc, #328] ; (8016714 <udp_sendto_if_src+0x1b4>)
80165cc: f004 fd2a bl 801b024 <iprintf>
80165d0: f06f 030f mvn.w r3, #15
80165d4: e095 b.n 8016702 <udp_sendto_if_src+0x1a2>
LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG);
80165d6: 6abb ldr r3, [r7, #40] ; 0x28
80165d8: 2b00 cmp r3, #0
80165da: d109 bne.n 80165f0 <udp_sendto_if_src+0x90>
80165dc: 4b4b ldr r3, [pc, #300] ; (801670c <udp_sendto_if_src+0x1ac>)
80165de: f240 22d5 movw r2, #725 ; 0x2d5
80165e2: 4950 ldr r1, [pc, #320] ; (8016724 <udp_sendto_if_src+0x1c4>)
80165e4: 484b ldr r0, [pc, #300] ; (8016714 <udp_sendto_if_src+0x1b4>)
80165e6: f004 fd1d bl 801b024 <iprintf>
80165ea: f06f 030f mvn.w r3, #15
80165ee: e088 b.n 8016702 <udp_sendto_if_src+0x1a2>
return ERR_VAL;
}
#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */
/* if the PCB is not yet bound to a port, bind it here */
if (pcb->local_port == 0) {
80165f0: 68fb ldr r3, [r7, #12]
80165f2: 8a5b ldrh r3, [r3, #18]
80165f4: 2b00 cmp r3, #0
80165f6: d10f bne.n 8016618 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
80165f8: 68f9 ldr r1, [r7, #12]
80165fa: 68fb ldr r3, [r7, #12]
80165fc: 8a5b ldrh r3, [r3, #18]
80165fe: 461a mov r2, r3
8016600: 68f8 ldr r0, [r7, #12]
8016602: f000 f893 bl 801672c <udp_bind>
8016606: 4603 mov r3, r0
8016608: 76fb strb r3, [r7, #27]
if (err != ERR_OK) {
801660a: f997 301b ldrsb.w r3, [r7, #27]
801660e: 2b00 cmp r3, #0
8016610: d002 beq.n 8016618 <udp_sendto_if_src+0xb8>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
return err;
8016612: f997 301b ldrsb.w r3, [r7, #27]
8016616: e074 b.n 8016702 <udp_sendto_if_src+0x1a2>
}
}
/* packet too large to add a UDP header without causing an overflow? */
if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) {
8016618: 68bb ldr r3, [r7, #8]
801661a: 891b ldrh r3, [r3, #8]
801661c: f64f 72f7 movw r2, #65527 ; 0xfff7
8016620: 4293 cmp r3, r2
8016622: d902 bls.n 801662a <udp_sendto_if_src+0xca>
return ERR_MEM;
8016624: f04f 33ff mov.w r3, #4294967295
8016628: e06b b.n 8016702 <udp_sendto_if_src+0x1a2>
}
/* not enough space to add an UDP header to first pbuf in given p chain? */
if (pbuf_add_header(p, UDP_HLEN)) {
801662a: 2108 movs r1, #8
801662c: 68b8 ldr r0, [r7, #8]
801662e: f7f9 ff4d bl 80104cc <pbuf_add_header>
8016632: 4603 mov r3, r0
8016634: 2b00 cmp r3, #0
8016636: d015 beq.n 8016664 <udp_sendto_if_src+0x104>
/* allocate header in a separate new pbuf */
q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
8016638: f44f 7220 mov.w r2, #640 ; 0x280
801663c: 2108 movs r1, #8
801663e: 2022 movs r0, #34 ; 0x22
8016640: f7f9 fcfa bl 8010038 <pbuf_alloc>
8016644: 61f8 str r0, [r7, #28]
/* new header pbuf could not be allocated? */
if (q == NULL) {
8016646: 69fb ldr r3, [r7, #28]
8016648: 2b00 cmp r3, #0
801664a: d102 bne.n 8016652 <udp_sendto_if_src+0xf2>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
return ERR_MEM;
801664c: f04f 33ff mov.w r3, #4294967295
8016650: e057 b.n 8016702 <udp_sendto_if_src+0x1a2>
}
if (p->tot_len != 0) {
8016652: 68bb ldr r3, [r7, #8]
8016654: 891b ldrh r3, [r3, #8]
8016656: 2b00 cmp r3, #0
8016658: d006 beq.n 8016668 <udp_sendto_if_src+0x108>
/* chain header q in front of given pbuf p (only if p contains data) */
pbuf_chain(q, p);
801665a: 68b9 ldr r1, [r7, #8]
801665c: 69f8 ldr r0, [r7, #28]
801665e: f7fa f8ef bl 8010840 <pbuf_chain>
8016662: e001 b.n 8016668 <udp_sendto_if_src+0x108>
LWIP_DEBUGF(UDP_DEBUG,
("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
} else {
/* adding space for header within p succeeded */
/* first pbuf q equals given pbuf */
q = p;
8016664: 68bb ldr r3, [r7, #8]
8016666: 61fb str r3, [r7, #28]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
}
LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
8016668: 69fb ldr r3, [r7, #28]
801666a: 895b ldrh r3, [r3, #10]
801666c: 2b07 cmp r3, #7
801666e: d806 bhi.n 801667e <udp_sendto_if_src+0x11e>
8016670: 4b26 ldr r3, [pc, #152] ; (801670c <udp_sendto_if_src+0x1ac>)
8016672: f240 320e movw r2, #782 ; 0x30e
8016676: 492c ldr r1, [pc, #176] ; (8016728 <udp_sendto_if_src+0x1c8>)
8016678: 4826 ldr r0, [pc, #152] ; (8016714 <udp_sendto_if_src+0x1b4>)
801667a: f004 fcd3 bl 801b024 <iprintf>
(q->len >= sizeof(struct udp_hdr)));
/* q now represents the packet to be sent */
udphdr = (struct udp_hdr *)q->payload;
801667e: 69fb ldr r3, [r7, #28]
8016680: 685b ldr r3, [r3, #4]
8016682: 617b str r3, [r7, #20]
udphdr->src = lwip_htons(pcb->local_port);
8016684: 68fb ldr r3, [r7, #12]
8016686: 8a5b ldrh r3, [r3, #18]
8016688: 4618 mov r0, r3
801668a: f7f8 fc01 bl 800ee90 <lwip_htons>
801668e: 4603 mov r3, r0
8016690: 461a mov r2, r3
8016692: 697b ldr r3, [r7, #20]
8016694: 801a strh r2, [r3, #0]
udphdr->dest = lwip_htons(dst_port);
8016696: 887b ldrh r3, [r7, #2]
8016698: 4618 mov r0, r3
801669a: f7f8 fbf9 bl 800ee90 <lwip_htons>
801669e: 4603 mov r3, r0
80166a0: 461a mov r2, r3
80166a2: 697b ldr r3, [r7, #20]
80166a4: 805a strh r2, [r3, #2]
/* in UDP, 0 checksum means 'no checksum' */
udphdr->chksum = 0x0000;
80166a6: 697b ldr r3, [r7, #20]
80166a8: 2200 movs r2, #0
80166aa: 719a strb r2, [r3, #6]
80166ac: 2200 movs r2, #0
80166ae: 71da strb r2, [r3, #7]
ip_proto = IP_PROTO_UDPLITE;
} else
#endif /* LWIP_UDPLITE */
{ /* UDP */
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
udphdr->len = lwip_htons(q->tot_len);
80166b0: 69fb ldr r3, [r7, #28]
80166b2: 891b ldrh r3, [r3, #8]
80166b4: 4618 mov r0, r3
80166b6: f7f8 fbeb bl 800ee90 <lwip_htons>
80166ba: 4603 mov r3, r0
80166bc: 461a mov r2, r3
80166be: 697b ldr r3, [r7, #20]
80166c0: 809a strh r2, [r3, #4]
}
udphdr->chksum = udpchksum;
}
}
#endif /* CHECKSUM_GEN_UDP */
ip_proto = IP_PROTO_UDP;
80166c2: 2311 movs r3, #17
80166c4: 74fb strb r3, [r7, #19]
/* Determine TTL to use */
#if LWIP_MULTICAST_TX_OPTIONS
ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl);
#else /* LWIP_MULTICAST_TX_OPTIONS */
ttl = pcb->ttl;
80166c6: 68fb ldr r3, [r7, #12]
80166c8: 7adb ldrb r3, [r3, #11]
80166ca: 74bb strb r3, [r7, #18]
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto));
/* output to IP */
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif);
80166cc: 68fb ldr r3, [r7, #12]
80166ce: 7a9b ldrb r3, [r3, #10]
80166d0: 7cb9 ldrb r1, [r7, #18]
80166d2: 6aba ldr r2, [r7, #40] ; 0x28
80166d4: 9202 str r2, [sp, #8]
80166d6: 7cfa ldrb r2, [r7, #19]
80166d8: 9201 str r2, [sp, #4]
80166da: 9300 str r3, [sp, #0]
80166dc: 460b mov r3, r1
80166de: 687a ldr r2, [r7, #4]
80166e0: 6af9 ldr r1, [r7, #44] ; 0x2c
80166e2: 69f8 ldr r0, [r7, #28]
80166e4: f003 fb48 bl 8019d78 <ip4_output_if_src>
80166e8: 4603 mov r3, r0
80166ea: 76fb strb r3, [r7, #27]
/* @todo: must this be increased even if error occurred? */
MIB2_STATS_INC(mib2.udpoutdatagrams);
/* did we chain a separate header pbuf earlier? */
if (q != p) {
80166ec: 69fa ldr r2, [r7, #28]
80166ee: 68bb ldr r3, [r7, #8]
80166f0: 429a cmp r2, r3
80166f2: d004 beq.n 80166fe <udp_sendto_if_src+0x19e>
/* free the header pbuf */
pbuf_free(q);
80166f4: 69f8 ldr r0, [r7, #28]
80166f6: f7f9 ff7f bl 80105f8 <pbuf_free>
q = NULL;
80166fa: 2300 movs r3, #0
80166fc: 61fb str r3, [r7, #28]
/* p is still referenced by the caller, and will live on */
}
UDP_STATS_INC(udp.xmit);
return err;
80166fe: f997 301b ldrsb.w r3, [r7, #27]
}
8016702: 4618 mov r0, r3
8016704: 3720 adds r7, #32
8016706: 46bd mov sp, r7
8016708: bd80 pop {r7, pc}
801670a: bf00 nop
801670c: 0801e044 .word 0x0801e044
8016710: 0801e230 .word 0x0801e230
8016714: 0801e098 .word 0x0801e098
8016718: 0801e250 .word 0x0801e250
801671c: 0801e270 .word 0x0801e270
8016720: 0801e294 .word 0x0801e294
8016724: 0801e2b8 .word 0x0801e2b8
8016728: 0801e2dc .word 0x0801e2dc
0801672c <udp_bind>:
*
* @see udp_disconnect()
*/
err_t
udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
801672c: b580 push {r7, lr}
801672e: b086 sub sp, #24
8016730: af00 add r7, sp, #0
8016732: 60f8 str r0, [r7, #12]
8016734: 60b9 str r1, [r7, #8]
8016736: 4613 mov r3, r2
8016738: 80fb strh r3, [r7, #6]
LWIP_ASSERT_CORE_LOCKED();
#if LWIP_IPV4
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
if (ipaddr == NULL) {
801673a: 68bb ldr r3, [r7, #8]
801673c: 2b00 cmp r3, #0
801673e: d101 bne.n 8016744 <udp_bind+0x18>
ipaddr = IP4_ADDR_ANY;
8016740: 4b39 ldr r3, [pc, #228] ; (8016828 <udp_bind+0xfc>)
8016742: 60bb str r3, [r7, #8]
}
#else /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
#endif /* LWIP_IPV4 */
LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
8016744: 68fb ldr r3, [r7, #12]
8016746: 2b00 cmp r3, #0
8016748: d109 bne.n 801675e <udp_bind+0x32>
801674a: 4b38 ldr r3, [pc, #224] ; (801682c <udp_bind+0x100>)
801674c: f240 32b7 movw r2, #951 ; 0x3b7
8016750: 4937 ldr r1, [pc, #220] ; (8016830 <udp_bind+0x104>)
8016752: 4838 ldr r0, [pc, #224] ; (8016834 <udp_bind+0x108>)
8016754: f004 fc66 bl 801b024 <iprintf>
8016758: f06f 030f mvn.w r3, #15
801675c: e060 b.n 8016820 <udp_bind+0xf4>
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
rebind = 0;
801675e: 2300 movs r3, #0
8016760: 74fb strb r3, [r7, #19]
/* Check for double bind and rebind of the same pcb */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016762: 4b35 ldr r3, [pc, #212] ; (8016838 <udp_bind+0x10c>)
8016764: 681b ldr r3, [r3, #0]
8016766: 617b str r3, [r7, #20]
8016768: e009 b.n 801677e <udp_bind+0x52>
/* is this UDP PCB already on active list? */
if (pcb == ipcb) {
801676a: 68fa ldr r2, [r7, #12]
801676c: 697b ldr r3, [r7, #20]
801676e: 429a cmp r2, r3
8016770: d102 bne.n 8016778 <udp_bind+0x4c>
rebind = 1;
8016772: 2301 movs r3, #1
8016774: 74fb strb r3, [r7, #19]
break;
8016776: e005 b.n 8016784 <udp_bind+0x58>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
8016778: 697b ldr r3, [r7, #20]
801677a: 68db ldr r3, [r3, #12]
801677c: 617b str r3, [r7, #20]
801677e: 697b ldr r3, [r7, #20]
8016780: 2b00 cmp r3, #0
8016782: d1f2 bne.n 801676a <udp_bind+0x3e>
ipaddr = &zoned_ipaddr;
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
/* no port specified? */
if (port == 0) {
8016784: 88fb ldrh r3, [r7, #6]
8016786: 2b00 cmp r3, #0
8016788: d109 bne.n 801679e <udp_bind+0x72>
port = udp_new_port();
801678a: f7ff fcc5 bl 8016118 <udp_new_port>
801678e: 4603 mov r3, r0
8016790: 80fb strh r3, [r7, #6]
if (port == 0) {
8016792: 88fb ldrh r3, [r7, #6]
8016794: 2b00 cmp r3, #0
8016796: d12c bne.n 80167f2 <udp_bind+0xc6>
/* no more ports available in local range */
LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
return ERR_USE;
8016798: f06f 0307 mvn.w r3, #7
801679c: e040 b.n 8016820 <udp_bind+0xf4>
}
} else {
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
801679e: 4b26 ldr r3, [pc, #152] ; (8016838 <udp_bind+0x10c>)
80167a0: 681b ldr r3, [r3, #0]
80167a2: 617b str r3, [r7, #20]
80167a4: e022 b.n 80167ec <udp_bind+0xc0>
if (pcb != ipcb) {
80167a6: 68fa ldr r2, [r7, #12]
80167a8: 697b ldr r3, [r7, #20]
80167aa: 429a cmp r2, r3
80167ac: d01b beq.n 80167e6 <udp_bind+0xba>
if (!ip_get_option(pcb, SOF_REUSEADDR) ||
!ip_get_option(ipcb, SOF_REUSEADDR))
#endif /* SO_REUSE */
{
/* port matches that of PCB in list and REUSEADDR not set -> reject */
if ((ipcb->local_port == port) &&
80167ae: 697b ldr r3, [r7, #20]
80167b0: 8a5b ldrh r3, [r3, #18]
80167b2: 88fa ldrh r2, [r7, #6]
80167b4: 429a cmp r2, r3
80167b6: d116 bne.n 80167e6 <udp_bind+0xba>
/* IP address matches or any IP used? */
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167b8: 697b ldr r3, [r7, #20]
80167ba: 681a ldr r2, [r3, #0]
80167bc: 68bb ldr r3, [r7, #8]
80167be: 681b ldr r3, [r3, #0]
if ((ipcb->local_port == port) &&
80167c0: 429a cmp r2, r3
80167c2: d00d beq.n 80167e0 <udp_bind+0xb4>
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167c4: 68bb ldr r3, [r7, #8]
80167c6: 2b00 cmp r3, #0
80167c8: d00a beq.n 80167e0 <udp_bind+0xb4>
80167ca: 68bb ldr r3, [r7, #8]
80167cc: 681b ldr r3, [r3, #0]
80167ce: 2b00 cmp r3, #0
80167d0: d006 beq.n 80167e0 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
80167d2: 697b ldr r3, [r7, #20]
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
80167d4: 2b00 cmp r3, #0
80167d6: d003 beq.n 80167e0 <udp_bind+0xb4>
ip_addr_isany(&ipcb->local_ip))) {
80167d8: 697b ldr r3, [r7, #20]
80167da: 681b ldr r3, [r3, #0]
80167dc: 2b00 cmp r3, #0
80167de: d102 bne.n 80167e6 <udp_bind+0xba>
/* other PCB already binds to this local IP and port */
LWIP_DEBUGF(UDP_DEBUG,
("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
return ERR_USE;
80167e0: f06f 0307 mvn.w r3, #7
80167e4: e01c b.n 8016820 <udp_bind+0xf4>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80167e6: 697b ldr r3, [r7, #20]
80167e8: 68db ldr r3, [r3, #12]
80167ea: 617b str r3, [r7, #20]
80167ec: 697b ldr r3, [r7, #20]
80167ee: 2b00 cmp r3, #0
80167f0: d1d9 bne.n 80167a6 <udp_bind+0x7a>
}
}
}
}
ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
80167f2: 68bb ldr r3, [r7, #8]
80167f4: 2b00 cmp r3, #0
80167f6: d002 beq.n 80167fe <udp_bind+0xd2>
80167f8: 68bb ldr r3, [r7, #8]
80167fa: 681b ldr r3, [r3, #0]
80167fc: e000 b.n 8016800 <udp_bind+0xd4>
80167fe: 2300 movs r3, #0
8016800: 68fa ldr r2, [r7, #12]
8016802: 6013 str r3, [r2, #0]
pcb->local_port = port;
8016804: 68fb ldr r3, [r7, #12]
8016806: 88fa ldrh r2, [r7, #6]
8016808: 825a strh r2, [r3, #18]
mib2_udp_bind(pcb);
/* pcb not active yet? */
if (rebind == 0) {
801680a: 7cfb ldrb r3, [r7, #19]
801680c: 2b00 cmp r3, #0
801680e: d106 bne.n 801681e <udp_bind+0xf2>
/* place the PCB on the active list if not already there */
pcb->next = udp_pcbs;
8016810: 4b09 ldr r3, [pc, #36] ; (8016838 <udp_bind+0x10c>)
8016812: 681a ldr r2, [r3, #0]
8016814: 68fb ldr r3, [r7, #12]
8016816: 60da str r2, [r3, #12]
udp_pcbs = pcb;
8016818: 4a07 ldr r2, [pc, #28] ; (8016838 <udp_bind+0x10c>)
801681a: 68fb ldr r3, [r7, #12]
801681c: 6013 str r3, [r2, #0]
}
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
return ERR_OK;
801681e: 2300 movs r3, #0
}
8016820: 4618 mov r0, r3
8016822: 3718 adds r7, #24
8016824: 46bd mov sp, r7
8016826: bd80 pop {r7, pc}
8016828: 08020e78 .word 0x08020e78
801682c: 0801e044 .word 0x0801e044
8016830: 0801e30c .word 0x0801e30c
8016834: 0801e098 .word 0x0801e098
8016838: 2000f5d8 .word 0x2000f5d8
0801683c <udp_connect>:
*
* @see udp_disconnect()
*/
err_t
udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
{
801683c: b580 push {r7, lr}
801683e: b086 sub sp, #24
8016840: af00 add r7, sp, #0
8016842: 60f8 str r0, [r7, #12]
8016844: 60b9 str r1, [r7, #8]
8016846: 4613 mov r3, r2
8016848: 80fb strh r3, [r7, #6]
struct udp_pcb *ipcb;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
801684a: 68fb ldr r3, [r7, #12]
801684c: 2b00 cmp r3, #0
801684e: d109 bne.n 8016864 <udp_connect+0x28>
8016850: 4b2c ldr r3, [pc, #176] ; (8016904 <udp_connect+0xc8>)
8016852: f240 4235 movw r2, #1077 ; 0x435
8016856: 492c ldr r1, [pc, #176] ; (8016908 <udp_connect+0xcc>)
8016858: 482c ldr r0, [pc, #176] ; (801690c <udp_connect+0xd0>)
801685a: f004 fbe3 bl 801b024 <iprintf>
801685e: f06f 030f mvn.w r3, #15
8016862: e04b b.n 80168fc <udp_connect+0xc0>
LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
8016864: 68bb ldr r3, [r7, #8]
8016866: 2b00 cmp r3, #0
8016868: d109 bne.n 801687e <udp_connect+0x42>
801686a: 4b26 ldr r3, [pc, #152] ; (8016904 <udp_connect+0xc8>)
801686c: f240 4236 movw r2, #1078 ; 0x436
8016870: 4927 ldr r1, [pc, #156] ; (8016910 <udp_connect+0xd4>)
8016872: 4826 ldr r0, [pc, #152] ; (801690c <udp_connect+0xd0>)
8016874: f004 fbd6 bl 801b024 <iprintf>
8016878: f06f 030f mvn.w r3, #15
801687c: e03e b.n 80168fc <udp_connect+0xc0>
if (pcb->local_port == 0) {
801687e: 68fb ldr r3, [r7, #12]
8016880: 8a5b ldrh r3, [r3, #18]
8016882: 2b00 cmp r3, #0
8016884: d10f bne.n 80168a6 <udp_connect+0x6a>
err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
8016886: 68f9 ldr r1, [r7, #12]
8016888: 68fb ldr r3, [r7, #12]
801688a: 8a5b ldrh r3, [r3, #18]
801688c: 461a mov r2, r3
801688e: 68f8 ldr r0, [r7, #12]
8016890: f7ff ff4c bl 801672c <udp_bind>
8016894: 4603 mov r3, r0
8016896: 74fb strb r3, [r7, #19]
if (err != ERR_OK) {
8016898: f997 3013 ldrsb.w r3, [r7, #19]
801689c: 2b00 cmp r3, #0
801689e: d002 beq.n 80168a6 <udp_connect+0x6a>
return err;
80168a0: f997 3013 ldrsb.w r3, [r7, #19]
80168a4: e02a b.n 80168fc <udp_connect+0xc0>
}
}
ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
80168a6: 68bb ldr r3, [r7, #8]
80168a8: 2b00 cmp r3, #0
80168aa: d002 beq.n 80168b2 <udp_connect+0x76>
80168ac: 68bb ldr r3, [r7, #8]
80168ae: 681b ldr r3, [r3, #0]
80168b0: e000 b.n 80168b4 <udp_connect+0x78>
80168b2: 2300 movs r3, #0
80168b4: 68fa ldr r2, [r7, #12]
80168b6: 6053 str r3, [r2, #4]
ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
}
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
pcb->remote_port = port;
80168b8: 68fb ldr r3, [r7, #12]
80168ba: 88fa ldrh r2, [r7, #6]
80168bc: 829a strh r2, [r3, #20]
pcb->flags |= UDP_FLAGS_CONNECTED;
80168be: 68fb ldr r3, [r7, #12]
80168c0: 7c1b ldrb r3, [r3, #16]
80168c2: f043 0304 orr.w r3, r3, #4
80168c6: b2da uxtb r2, r3
80168c8: 68fb ldr r3, [r7, #12]
80168ca: 741a strb r2, [r3, #16]
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
pcb->remote_ip);
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
/* Insert UDP PCB into the list of active UDP PCBs. */
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80168cc: 4b11 ldr r3, [pc, #68] ; (8016914 <udp_connect+0xd8>)
80168ce: 681b ldr r3, [r3, #0]
80168d0: 617b str r3, [r7, #20]
80168d2: e008 b.n 80168e6 <udp_connect+0xaa>
if (pcb == ipcb) {
80168d4: 68fa ldr r2, [r7, #12]
80168d6: 697b ldr r3, [r7, #20]
80168d8: 429a cmp r2, r3
80168da: d101 bne.n 80168e0 <udp_connect+0xa4>
/* already on the list, just return */
return ERR_OK;
80168dc: 2300 movs r3, #0
80168de: e00d b.n 80168fc <udp_connect+0xc0>
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
80168e0: 697b ldr r3, [r7, #20]
80168e2: 68db ldr r3, [r3, #12]
80168e4: 617b str r3, [r7, #20]
80168e6: 697b ldr r3, [r7, #20]
80168e8: 2b00 cmp r3, #0
80168ea: d1f3 bne.n 80168d4 <udp_connect+0x98>
}
}
/* PCB not yet on the list, add PCB now */
pcb->next = udp_pcbs;
80168ec: 4b09 ldr r3, [pc, #36] ; (8016914 <udp_connect+0xd8>)
80168ee: 681a ldr r2, [r3, #0]
80168f0: 68fb ldr r3, [r7, #12]
80168f2: 60da str r2, [r3, #12]
udp_pcbs = pcb;
80168f4: 4a07 ldr r2, [pc, #28] ; (8016914 <udp_connect+0xd8>)
80168f6: 68fb ldr r3, [r7, #12]
80168f8: 6013 str r3, [r2, #0]
return ERR_OK;
80168fa: 2300 movs r3, #0
}
80168fc: 4618 mov r0, r3
80168fe: 3718 adds r7, #24
8016900: 46bd mov sp, r7
8016902: bd80 pop {r7, pc}
8016904: 0801e044 .word 0x0801e044
8016908: 0801e324 .word 0x0801e324
801690c: 0801e098 .word 0x0801e098
8016910: 0801e340 .word 0x0801e340
8016914: 2000f5d8 .word 0x2000f5d8
08016918 <udp_recv>:
* @param recv function pointer of the callback function
* @param recv_arg additional argument to pass to the callback function
*/
void
udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
{
8016918: b580 push {r7, lr}
801691a: b084 sub sp, #16
801691c: af00 add r7, sp, #0
801691e: 60f8 str r0, [r7, #12]
8016920: 60b9 str r1, [r7, #8]
8016922: 607a str r2, [r7, #4]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
8016924: 68fb ldr r3, [r7, #12]
8016926: 2b00 cmp r3, #0
8016928: d107 bne.n 801693a <udp_recv+0x22>
801692a: 4b08 ldr r3, [pc, #32] ; (801694c <udp_recv+0x34>)
801692c: f240 428a movw r2, #1162 ; 0x48a
8016930: 4907 ldr r1, [pc, #28] ; (8016950 <udp_recv+0x38>)
8016932: 4808 ldr r0, [pc, #32] ; (8016954 <udp_recv+0x3c>)
8016934: f004 fb76 bl 801b024 <iprintf>
8016938: e005 b.n 8016946 <udp_recv+0x2e>
/* remember recv() callback and user data */
pcb->recv = recv;
801693a: 68fb ldr r3, [r7, #12]
801693c: 68ba ldr r2, [r7, #8]
801693e: 619a str r2, [r3, #24]
pcb->recv_arg = recv_arg;
8016940: 68fb ldr r3, [r7, #12]
8016942: 687a ldr r2, [r7, #4]
8016944: 61da str r2, [r3, #28]
}
8016946: 3710 adds r7, #16
8016948: 46bd mov sp, r7
801694a: bd80 pop {r7, pc}
801694c: 0801e044 .word 0x0801e044
8016950: 0801e378 .word 0x0801e378
8016954: 0801e098 .word 0x0801e098
08016958 <udp_remove>:
*
* @see udp_new()
*/
void
udp_remove(struct udp_pcb *pcb)
{
8016958: b580 push {r7, lr}
801695a: b084 sub sp, #16
801695c: af00 add r7, sp, #0
801695e: 6078 str r0, [r7, #4]
struct udp_pcb *pcb2;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
8016960: 687b ldr r3, [r7, #4]
8016962: 2b00 cmp r3, #0
8016964: d107 bne.n 8016976 <udp_remove+0x1e>
8016966: 4b19 ldr r3, [pc, #100] ; (80169cc <udp_remove+0x74>)
8016968: f240 42a1 movw r2, #1185 ; 0x4a1
801696c: 4918 ldr r1, [pc, #96] ; (80169d0 <udp_remove+0x78>)
801696e: 4819 ldr r0, [pc, #100] ; (80169d4 <udp_remove+0x7c>)
8016970: f004 fb58 bl 801b024 <iprintf>
8016974: e026 b.n 80169c4 <udp_remove+0x6c>
mib2_udp_unbind(pcb);
/* pcb to be removed is first in list? */
if (udp_pcbs == pcb) {
8016976: 4b18 ldr r3, [pc, #96] ; (80169d8 <udp_remove+0x80>)
8016978: 681b ldr r3, [r3, #0]
801697a: 687a ldr r2, [r7, #4]
801697c: 429a cmp r2, r3
801697e: d105 bne.n 801698c <udp_remove+0x34>
/* make list start at 2nd pcb */
udp_pcbs = udp_pcbs->next;
8016980: 4b15 ldr r3, [pc, #84] ; (80169d8 <udp_remove+0x80>)
8016982: 681b ldr r3, [r3, #0]
8016984: 68db ldr r3, [r3, #12]
8016986: 4a14 ldr r2, [pc, #80] ; (80169d8 <udp_remove+0x80>)
8016988: 6013 str r3, [r2, #0]
801698a: e017 b.n 80169bc <udp_remove+0x64>
/* pcb not 1st in list */
} else {
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
801698c: 4b12 ldr r3, [pc, #72] ; (80169d8 <udp_remove+0x80>)
801698e: 681b ldr r3, [r3, #0]
8016990: 60fb str r3, [r7, #12]
8016992: e010 b.n 80169b6 <udp_remove+0x5e>
/* find pcb in udp_pcbs list */
if (pcb2->next != NULL && pcb2->next == pcb) {
8016994: 68fb ldr r3, [r7, #12]
8016996: 68db ldr r3, [r3, #12]
8016998: 2b00 cmp r3, #0
801699a: d009 beq.n 80169b0 <udp_remove+0x58>
801699c: 68fb ldr r3, [r7, #12]
801699e: 68db ldr r3, [r3, #12]
80169a0: 687a ldr r2, [r7, #4]
80169a2: 429a cmp r2, r3
80169a4: d104 bne.n 80169b0 <udp_remove+0x58>
/* remove pcb from list */
pcb2->next = pcb->next;
80169a6: 687b ldr r3, [r7, #4]
80169a8: 68da ldr r2, [r3, #12]
80169aa: 68fb ldr r3, [r7, #12]
80169ac: 60da str r2, [r3, #12]
break;
80169ae: e005 b.n 80169bc <udp_remove+0x64>
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
80169b0: 68fb ldr r3, [r7, #12]
80169b2: 68db ldr r3, [r3, #12]
80169b4: 60fb str r3, [r7, #12]
80169b6: 68fb ldr r3, [r7, #12]
80169b8: 2b00 cmp r3, #0
80169ba: d1eb bne.n 8016994 <udp_remove+0x3c>
}
}
}
memp_free(MEMP_UDP_PCB, pcb);
80169bc: 6879 ldr r1, [r7, #4]
80169be: 2000 movs r0, #0
80169c0: f7f8 ff6e bl 800f8a0 <memp_free>
}
80169c4: 3710 adds r7, #16
80169c6: 46bd mov sp, r7
80169c8: bd80 pop {r7, pc}
80169ca: bf00 nop
80169cc: 0801e044 .word 0x0801e044
80169d0: 0801e390 .word 0x0801e390
80169d4: 0801e098 .word 0x0801e098
80169d8: 2000f5d8 .word 0x2000f5d8
080169dc <udp_new>:
*
* @see udp_remove()
*/
struct udp_pcb *
udp_new(void)
{
80169dc: b580 push {r7, lr}
80169de: b082 sub sp, #8
80169e0: af00 add r7, sp, #0
struct udp_pcb *pcb;
LWIP_ASSERT_CORE_LOCKED();
pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
80169e2: 2000 movs r0, #0
80169e4: f7f8 ff0a bl 800f7fc <memp_malloc>
80169e8: 6078 str r0, [r7, #4]
/* could allocate UDP PCB? */
if (pcb != NULL) {
80169ea: 687b ldr r3, [r7, #4]
80169ec: 2b00 cmp r3, #0
80169ee: d007 beq.n 8016a00 <udp_new+0x24>
/* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
* which means checksum is generated over the whole datagram per default
* (recommended as default by RFC 3828). */
/* initialize PCB to all zeroes */
memset(pcb, 0, sizeof(struct udp_pcb));
80169f0: 2220 movs r2, #32
80169f2: 2100 movs r1, #0
80169f4: 6878 ldr r0, [r7, #4]
80169f6: f004 fb0d bl 801b014 <memset>
pcb->ttl = UDP_TTL;
80169fa: 687b ldr r3, [r7, #4]
80169fc: 22ff movs r2, #255 ; 0xff
80169fe: 72da strb r2, [r3, #11]
#if LWIP_MULTICAST_TX_OPTIONS
udp_set_multicast_ttl(pcb, UDP_TTL);
#endif /* LWIP_MULTICAST_TX_OPTIONS */
}
return pcb;
8016a00: 687b ldr r3, [r7, #4]
}
8016a02: 4618 mov r0, r3
8016a04: 3708 adds r7, #8
8016a06: 46bd mov sp, r7
8016a08: bd80 pop {r7, pc}
...
08016a0c <udp_netif_ip_addr_changed>:
*
* @param old_addr IP address of the netif before change
* @param new_addr IP address of the netif after change
*/
void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
{
8016a0c: b480 push {r7}
8016a0e: b085 sub sp, #20
8016a10: af00 add r7, sp, #0
8016a12: 6078 str r0, [r7, #4]
8016a14: 6039 str r1, [r7, #0]
struct udp_pcb *upcb;
if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
8016a16: 687b ldr r3, [r7, #4]
8016a18: 2b00 cmp r3, #0
8016a1a: d01e beq.n 8016a5a <udp_netif_ip_addr_changed+0x4e>
8016a1c: 687b ldr r3, [r7, #4]
8016a1e: 681b ldr r3, [r3, #0]
8016a20: 2b00 cmp r3, #0
8016a22: d01a beq.n 8016a5a <udp_netif_ip_addr_changed+0x4e>
8016a24: 683b ldr r3, [r7, #0]
8016a26: 2b00 cmp r3, #0
8016a28: d017 beq.n 8016a5a <udp_netif_ip_addr_changed+0x4e>
8016a2a: 683b ldr r3, [r7, #0]
8016a2c: 681b ldr r3, [r3, #0]
8016a2e: 2b00 cmp r3, #0
8016a30: d013 beq.n 8016a5a <udp_netif_ip_addr_changed+0x4e>
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
8016a32: 4b0d ldr r3, [pc, #52] ; (8016a68 <udp_netif_ip_addr_changed+0x5c>)
8016a34: 681b ldr r3, [r3, #0]
8016a36: 60fb str r3, [r7, #12]
8016a38: e00c b.n 8016a54 <udp_netif_ip_addr_changed+0x48>
/* PCB bound to current local interface address? */
if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
8016a3a: 68fb ldr r3, [r7, #12]
8016a3c: 681a ldr r2, [r3, #0]
8016a3e: 687b ldr r3, [r7, #4]
8016a40: 681b ldr r3, [r3, #0]
8016a42: 429a cmp r2, r3
8016a44: d103 bne.n 8016a4e <udp_netif_ip_addr_changed+0x42>
/* The PCB is bound to the old ipaddr and
* is set to bound to the new one instead */
ip_addr_copy(upcb->local_ip, *new_addr);
8016a46: 683b ldr r3, [r7, #0]
8016a48: 681a ldr r2, [r3, #0]
8016a4a: 68fb ldr r3, [r7, #12]
8016a4c: 601a str r2, [r3, #0]
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
8016a4e: 68fb ldr r3, [r7, #12]
8016a50: 68db ldr r3, [r3, #12]
8016a52: 60fb str r3, [r7, #12]
8016a54: 68fb ldr r3, [r7, #12]
8016a56: 2b00 cmp r3, #0
8016a58: d1ef bne.n 8016a3a <udp_netif_ip_addr_changed+0x2e>
}
}
}
}
8016a5a: bf00 nop
8016a5c: 3714 adds r7, #20
8016a5e: 46bd mov sp, r7
8016a60: f85d 7b04 ldr.w r7, [sp], #4
8016a64: 4770 bx lr
8016a66: bf00 nop
8016a68: 2000f5d8 .word 0x2000f5d8
08016a6c <dhcp_inc_pcb_refcount>:
static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out);
/** Ensure DHCP PCB is allocated and bound */
static err_t
dhcp_inc_pcb_refcount(void)
{
8016a6c: b580 push {r7, lr}
8016a6e: af00 add r7, sp, #0
if (dhcp_pcb_refcount == 0) {
8016a70: 4b20 ldr r3, [pc, #128] ; (8016af4 <dhcp_inc_pcb_refcount+0x88>)
8016a72: 781b ldrb r3, [r3, #0]
8016a74: 2b00 cmp r3, #0
8016a76: d133 bne.n 8016ae0 <dhcp_inc_pcb_refcount+0x74>
LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL);
8016a78: 4b1f ldr r3, [pc, #124] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016a7a: 681b ldr r3, [r3, #0]
8016a7c: 2b00 cmp r3, #0
8016a7e: d005 beq.n 8016a8c <dhcp_inc_pcb_refcount+0x20>
8016a80: 4b1e ldr r3, [pc, #120] ; (8016afc <dhcp_inc_pcb_refcount+0x90>)
8016a82: 22e5 movs r2, #229 ; 0xe5
8016a84: 491e ldr r1, [pc, #120] ; (8016b00 <dhcp_inc_pcb_refcount+0x94>)
8016a86: 481f ldr r0, [pc, #124] ; (8016b04 <dhcp_inc_pcb_refcount+0x98>)
8016a88: f004 facc bl 801b024 <iprintf>
/* allocate UDP PCB */
dhcp_pcb = udp_new();
8016a8c: f7ff ffa6 bl 80169dc <udp_new>
8016a90: 4602 mov r2, r0
8016a92: 4b19 ldr r3, [pc, #100] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016a94: 601a str r2, [r3, #0]
if (dhcp_pcb == NULL) {
8016a96: 4b18 ldr r3, [pc, #96] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016a98: 681b ldr r3, [r3, #0]
8016a9a: 2b00 cmp r3, #0
8016a9c: d102 bne.n 8016aa4 <dhcp_inc_pcb_refcount+0x38>
return ERR_MEM;
8016a9e: f04f 33ff mov.w r3, #4294967295
8016aa2: e024 b.n 8016aee <dhcp_inc_pcb_refcount+0x82>
}
ip_set_option(dhcp_pcb, SOF_BROADCAST);
8016aa4: 4b14 ldr r3, [pc, #80] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016aa6: 681b ldr r3, [r3, #0]
8016aa8: 7a5a ldrb r2, [r3, #9]
8016aaa: 4b13 ldr r3, [pc, #76] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016aac: 681b ldr r3, [r3, #0]
8016aae: f042 0220 orr.w r2, r2, #32
8016ab2: b2d2 uxtb r2, r2
8016ab4: 725a strb r2, [r3, #9]
/* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT);
8016ab6: 4b10 ldr r3, [pc, #64] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016ab8: 681b ldr r3, [r3, #0]
8016aba: 2244 movs r2, #68 ; 0x44
8016abc: 4912 ldr r1, [pc, #72] ; (8016b08 <dhcp_inc_pcb_refcount+0x9c>)
8016abe: 4618 mov r0, r3
8016ac0: f7ff fe34 bl 801672c <udp_bind>
udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER);
8016ac4: 4b0c ldr r3, [pc, #48] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016ac6: 681b ldr r3, [r3, #0]
8016ac8: 2243 movs r2, #67 ; 0x43
8016aca: 490f ldr r1, [pc, #60] ; (8016b08 <dhcp_inc_pcb_refcount+0x9c>)
8016acc: 4618 mov r0, r3
8016ace: f7ff feb5 bl 801683c <udp_connect>
udp_recv(dhcp_pcb, dhcp_recv, NULL);
8016ad2: 4b09 ldr r3, [pc, #36] ; (8016af8 <dhcp_inc_pcb_refcount+0x8c>)
8016ad4: 681b ldr r3, [r3, #0]
8016ad6: 2200 movs r2, #0
8016ad8: 490c ldr r1, [pc, #48] ; (8016b0c <dhcp_inc_pcb_refcount+0xa0>)
8016ada: 4618 mov r0, r3
8016adc: f7ff ff1c bl 8016918 <udp_recv>
}
dhcp_pcb_refcount++;
8016ae0: 4b04 ldr r3, [pc, #16] ; (8016af4 <dhcp_inc_pcb_refcount+0x88>)
8016ae2: 781b ldrb r3, [r3, #0]
8016ae4: 3301 adds r3, #1
8016ae6: b2da uxtb r2, r3
8016ae8: 4b02 ldr r3, [pc, #8] ; (8016af4 <dhcp_inc_pcb_refcount+0x88>)
8016aea: 701a strb r2, [r3, #0]
return ERR_OK;
8016aec: 2300 movs r3, #0
}
8016aee: 4618 mov r0, r3
8016af0: bd80 pop {r7, pc}
8016af2: bf00 nop
8016af4: 20008770 .word 0x20008770
8016af8: 2000876c .word 0x2000876c
8016afc: 0801e3a8 .word 0x0801e3a8
8016b00: 0801e3e0 .word 0x0801e3e0
8016b04: 0801e408 .word 0x0801e408
8016b08: 08020e78 .word 0x08020e78
8016b0c: 080183c9 .word 0x080183c9
08016b10 <dhcp_dec_pcb_refcount>:
/** Free DHCP PCB if the last netif stops using it */
static void
dhcp_dec_pcb_refcount(void)
{
8016b10: b580 push {r7, lr}
8016b12: af00 add r7, sp, #0
LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0));
8016b14: 4b0e ldr r3, [pc, #56] ; (8016b50 <dhcp_dec_pcb_refcount+0x40>)
8016b16: 781b ldrb r3, [r3, #0]
8016b18: 2b00 cmp r3, #0
8016b1a: d105 bne.n 8016b28 <dhcp_dec_pcb_refcount+0x18>
8016b1c: 4b0d ldr r3, [pc, #52] ; (8016b54 <dhcp_dec_pcb_refcount+0x44>)
8016b1e: 22ff movs r2, #255 ; 0xff
8016b20: 490d ldr r1, [pc, #52] ; (8016b58 <dhcp_dec_pcb_refcount+0x48>)
8016b22: 480e ldr r0, [pc, #56] ; (8016b5c <dhcp_dec_pcb_refcount+0x4c>)
8016b24: f004 fa7e bl 801b024 <iprintf>
dhcp_pcb_refcount--;
8016b28: 4b09 ldr r3, [pc, #36] ; (8016b50 <dhcp_dec_pcb_refcount+0x40>)
8016b2a: 781b ldrb r3, [r3, #0]
8016b2c: 3b01 subs r3, #1
8016b2e: b2da uxtb r2, r3
8016b30: 4b07 ldr r3, [pc, #28] ; (8016b50 <dhcp_dec_pcb_refcount+0x40>)
8016b32: 701a strb r2, [r3, #0]
if (dhcp_pcb_refcount == 0) {
8016b34: 4b06 ldr r3, [pc, #24] ; (8016b50 <dhcp_dec_pcb_refcount+0x40>)
8016b36: 781b ldrb r3, [r3, #0]
8016b38: 2b00 cmp r3, #0
8016b3a: d107 bne.n 8016b4c <dhcp_dec_pcb_refcount+0x3c>
udp_remove(dhcp_pcb);
8016b3c: 4b08 ldr r3, [pc, #32] ; (8016b60 <dhcp_dec_pcb_refcount+0x50>)
8016b3e: 681b ldr r3, [r3, #0]
8016b40: 4618 mov r0, r3
8016b42: f7ff ff09 bl 8016958 <udp_remove>
dhcp_pcb = NULL;
8016b46: 4b06 ldr r3, [pc, #24] ; (8016b60 <dhcp_dec_pcb_refcount+0x50>)
8016b48: 2200 movs r2, #0
8016b4a: 601a str r2, [r3, #0]
}
}
8016b4c: bf00 nop
8016b4e: bd80 pop {r7, pc}
8016b50: 20008770 .word 0x20008770
8016b54: 0801e3a8 .word 0x0801e3a8
8016b58: 0801e430 .word 0x0801e430
8016b5c: 0801e408 .word 0x0801e408
8016b60: 2000876c .word 0x2000876c
08016b64 <dhcp_handle_nak>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_nak(struct netif *netif)
{
8016b64: b580 push {r7, lr}
8016b66: b084 sub sp, #16
8016b68: af00 add r7, sp, #0
8016b6a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016b6c: 687b ldr r3, [r7, #4]
8016b6e: 6a5b ldr r3, [r3, #36] ; 0x24
8016b70: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* Change to a defined state - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
8016b72: 210c movs r1, #12
8016b74: 68f8 ldr r0, [r7, #12]
8016b76: f001 f869 bl 8017c4c <dhcp_set_state>
/* remove IP address from interface (must no longer be used, as per RFC2131) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8016b7a: 4b06 ldr r3, [pc, #24] ; (8016b94 <dhcp_handle_nak+0x30>)
8016b7c: 4a05 ldr r2, [pc, #20] ; (8016b94 <dhcp_handle_nak+0x30>)
8016b7e: 4905 ldr r1, [pc, #20] ; (8016b94 <dhcp_handle_nak+0x30>)
8016b80: 6878 ldr r0, [r7, #4]
8016b82: f7f9 f82f bl 800fbe4 <netif_set_addr>
/* We can immediately restart discovery */
dhcp_discover(netif);
8016b86: 6878 ldr r0, [r7, #4]
8016b88: f000 fc5c bl 8017444 <dhcp_discover>
}
8016b8c: bf00 nop
8016b8e: 3710 adds r7, #16
8016b90: 46bd mov sp, r7
8016b92: bd80 pop {r7, pc}
8016b94: 08020e78 .word 0x08020e78
08016b98 <dhcp_check>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_check(struct netif *netif)
{
8016b98: b580 push {r7, lr}
8016b9a: b084 sub sp, #16
8016b9c: af00 add r7, sp, #0
8016b9e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016ba0: 687b ldr r3, [r7, #4]
8016ba2: 6a5b ldr r3, [r3, #36] ; 0x24
8016ba4: 60fb str r3, [r7, #12]
err_t result;
u16_t msecs;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
(s16_t)netif->name[1]));
dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
8016ba6: 2108 movs r1, #8
8016ba8: 68f8 ldr r0, [r7, #12]
8016baa: f001 f84f bl 8017c4c <dhcp_set_state>
/* create an ARP query for the offered IP address, expecting that no host
responds, as the IP address should not be in use. */
result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
8016bae: 68fb ldr r3, [r7, #12]
8016bb0: 331c adds r3, #28
8016bb2: 2200 movs r2, #0
8016bb4: 4619 mov r1, r3
8016bb6: 6878 ldr r0, [r7, #4]
8016bb8: f002 fb4e bl 8019258 <etharp_query>
8016bbc: 4603 mov r3, r0
8016bbe: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
}
if (dhcp->tries < 255) {
8016bc0: 68fb ldr r3, [r7, #12]
8016bc2: 799b ldrb r3, [r3, #6]
8016bc4: 2bff cmp r3, #255 ; 0xff
8016bc6: d005 beq.n 8016bd4 <dhcp_check+0x3c>
dhcp->tries++;
8016bc8: 68fb ldr r3, [r7, #12]
8016bca: 799b ldrb r3, [r3, #6]
8016bcc: 3301 adds r3, #1
8016bce: b2da uxtb r2, r3
8016bd0: 68fb ldr r3, [r7, #12]
8016bd2: 719a strb r2, [r3, #6]
}
msecs = 500;
8016bd4: f44f 73fa mov.w r3, #500 ; 0x1f4
8016bd8: 813b strh r3, [r7, #8]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016bda: 893b ldrh r3, [r7, #8]
8016bdc: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016be0: 4a06 ldr r2, [pc, #24] ; (8016bfc <dhcp_check+0x64>)
8016be2: fb82 1203 smull r1, r2, r2, r3
8016be6: 1152 asrs r2, r2, #5
8016be8: 17db asrs r3, r3, #31
8016bea: 1ad3 subs r3, r2, r3
8016bec: b29a uxth r2, r3
8016bee: 68fb ldr r3, [r7, #12]
8016bf0: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
}
8016bf2: bf00 nop
8016bf4: 3710 adds r7, #16
8016bf6: 46bd mov sp, r7
8016bf8: bd80 pop {r7, pc}
8016bfa: bf00 nop
8016bfc: 10624dd3 .word 0x10624dd3
08016c00 <dhcp_handle_offer>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in)
{
8016c00: b580 push {r7, lr}
8016c02: b084 sub sp, #16
8016c04: af00 add r7, sp, #0
8016c06: 6078 str r0, [r7, #4]
8016c08: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016c0a: 687b ldr r3, [r7, #4]
8016c0c: 6a5b ldr r3, [r3, #36] ; 0x24
8016c0e: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* obtain the server address */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
8016c10: 4b0c ldr r3, [pc, #48] ; (8016c44 <dhcp_handle_offer+0x44>)
8016c12: 789b ldrb r3, [r3, #2]
8016c14: 2b00 cmp r3, #0
8016c16: d011 beq.n 8016c3c <dhcp_handle_offer+0x3c>
dhcp->request_timeout = 0; /* stop timer */
8016c18: 68fb ldr r3, [r7, #12]
8016c1a: 2200 movs r2, #0
8016c1c: 811a strh r2, [r3, #8]
ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
8016c1e: 4b0a ldr r3, [pc, #40] ; (8016c48 <dhcp_handle_offer+0x48>)
8016c20: 689b ldr r3, [r3, #8]
8016c22: 4618 mov r0, r3
8016c24: f7f8 f949 bl 800eeba <lwip_htonl>
8016c28: 4602 mov r2, r0
8016c2a: 68fb ldr r3, [r7, #12]
8016c2c: 619a str r2, [r3, #24]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
/* remember offered address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
8016c2e: 683b ldr r3, [r7, #0]
8016c30: 691a ldr r2, [r3, #16]
8016c32: 68fb ldr r3, [r7, #12]
8016c34: 61da str r2, [r3, #28]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr)));
dhcp_select(netif);
8016c36: 6878 ldr r0, [r7, #4]
8016c38: f000 f808 bl 8016c4c <dhcp_select>
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif));
}
}
8016c3c: bf00 nop
8016c3e: 3710 adds r7, #16
8016c40: 46bd mov sp, r7
8016c42: bd80 pop {r7, pc}
8016c44: 2000f5dc .word 0x2000f5dc
8016c48: 2000f5e4 .word 0x2000f5e4
08016c4c <dhcp_select>:
* @param netif the netif under DHCP control
* @return lwIP specific error (see error.h)
*/
static err_t
dhcp_select(struct netif *netif)
{
8016c4c: b5b0 push {r4, r5, r7, lr}
8016c4e: b08a sub sp, #40 ; 0x28
8016c50: af02 add r7, sp, #8
8016c52: 6078 str r0, [r7, #4]
u16_t msecs;
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;);
8016c54: 687b ldr r3, [r7, #4]
8016c56: 2b00 cmp r3, #0
8016c58: d109 bne.n 8016c6e <dhcp_select+0x22>
8016c5a: 4b71 ldr r3, [pc, #452] ; (8016e20 <dhcp_select+0x1d4>)
8016c5c: f240 1277 movw r2, #375 ; 0x177
8016c60: 4970 ldr r1, [pc, #448] ; (8016e24 <dhcp_select+0x1d8>)
8016c62: 4871 ldr r0, [pc, #452] ; (8016e28 <dhcp_select+0x1dc>)
8016c64: f004 f9de bl 801b024 <iprintf>
8016c68: f06f 030f mvn.w r3, #15
8016c6c: e0d3 b.n 8016e16 <dhcp_select+0x1ca>
dhcp = netif_dhcp_data(netif);
8016c6e: 687b ldr r3, [r7, #4]
8016c70: 6a5b ldr r3, [r3, #36] ; 0x24
8016c72: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
8016c74: 69bb ldr r3, [r7, #24]
8016c76: 2b00 cmp r3, #0
8016c78: d109 bne.n 8016c8e <dhcp_select+0x42>
8016c7a: 4b69 ldr r3, [pc, #420] ; (8016e20 <dhcp_select+0x1d4>)
8016c7c: f240 1279 movw r2, #377 ; 0x179
8016c80: 496a ldr r1, [pc, #424] ; (8016e2c <dhcp_select+0x1e0>)
8016c82: 4869 ldr r0, [pc, #420] ; (8016e28 <dhcp_select+0x1dc>)
8016c84: f004 f9ce bl 801b024 <iprintf>
8016c88: f06f 0305 mvn.w r3, #5
8016c8c: e0c3 b.n 8016e16 <dhcp_select+0x1ca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
8016c8e: 2101 movs r1, #1
8016c90: 69b8 ldr r0, [r7, #24]
8016c92: f000 ffdb bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8016c96: f107 030c add.w r3, r7, #12
8016c9a: 2203 movs r2, #3
8016c9c: 69b9 ldr r1, [r7, #24]
8016c9e: 6878 ldr r0, [r7, #4]
8016ca0: f001 fc5e bl 8018560 <dhcp_create_msg>
8016ca4: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8016ca6: 697b ldr r3, [r7, #20]
8016ca8: 2b00 cmp r3, #0
8016caa: f000 8085 beq.w 8016db8 <dhcp_select+0x16c>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8016cae: 697b ldr r3, [r7, #20]
8016cb0: 685b ldr r3, [r3, #4]
8016cb2: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8016cb4: 89b8 ldrh r0, [r7, #12]
8016cb6: 693b ldr r3, [r7, #16]
8016cb8: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016cbc: 2302 movs r3, #2
8016cbe: 2239 movs r2, #57 ; 0x39
8016cc0: f000 ffde bl 8017c80 <dhcp_option>
8016cc4: 4603 mov r3, r0
8016cc6: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8016cc8: 89b8 ldrh r0, [r7, #12]
8016cca: 693b ldr r3, [r7, #16]
8016ccc: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016cd0: 687b ldr r3, [r7, #4]
8016cd2: 8d1b ldrh r3, [r3, #40] ; 0x28
8016cd4: 461a mov r2, r3
8016cd6: f001 f82d bl 8017d34 <dhcp_option_short>
8016cda: 4603 mov r3, r0
8016cdc: 81bb strh r3, [r7, #12]
/* MUST request the offered IP address */
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8016cde: 89b8 ldrh r0, [r7, #12]
8016ce0: 693b ldr r3, [r7, #16]
8016ce2: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016ce6: 2304 movs r3, #4
8016ce8: 2232 movs r2, #50 ; 0x32
8016cea: f000 ffc9 bl 8017c80 <dhcp_option>
8016cee: 4603 mov r3, r0
8016cf0: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
8016cf2: 89bc ldrh r4, [r7, #12]
8016cf4: 693b ldr r3, [r7, #16]
8016cf6: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016cfa: 69bb ldr r3, [r7, #24]
8016cfc: 69db ldr r3, [r3, #28]
8016cfe: 4618 mov r0, r3
8016d00: f7f8 f8db bl 800eeba <lwip_htonl>
8016d04: 4603 mov r3, r0
8016d06: 461a mov r2, r3
8016d08: 4629 mov r1, r5
8016d0a: 4620 mov r0, r4
8016d0c: f001 f844 bl 8017d98 <dhcp_option_long>
8016d10: 4603 mov r3, r0
8016d12: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8016d14: 89b8 ldrh r0, [r7, #12]
8016d16: 693b ldr r3, [r7, #16]
8016d18: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d1c: 2304 movs r3, #4
8016d1e: 2236 movs r2, #54 ; 0x36
8016d20: f000 ffae bl 8017c80 <dhcp_option>
8016d24: 4603 mov r3, r0
8016d26: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
8016d28: 89bc ldrh r4, [r7, #12]
8016d2a: 693b ldr r3, [r7, #16]
8016d2c: f103 05f0 add.w r5, r3, #240 ; 0xf0
8016d30: 69bb ldr r3, [r7, #24]
8016d32: 699b ldr r3, [r3, #24]
8016d34: 4618 mov r0, r3
8016d36: f7f8 f8c0 bl 800eeba <lwip_htonl>
8016d3a: 4603 mov r3, r0
8016d3c: 461a mov r2, r3
8016d3e: 4629 mov r1, r5
8016d40: 4620 mov r0, r4
8016d42: f001 f829 bl 8017d98 <dhcp_option_long>
8016d46: 4603 mov r3, r0
8016d48: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8016d4a: 89b8 ldrh r0, [r7, #12]
8016d4c: 693b ldr r3, [r7, #16]
8016d4e: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d52: 2303 movs r3, #3
8016d54: 2237 movs r2, #55 ; 0x37
8016d56: f000 ff93 bl 8017c80 <dhcp_option>
8016d5a: 4603 mov r3, r0
8016d5c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d5e: 2300 movs r3, #0
8016d60: 77bb strb r3, [r7, #30]
8016d62: e00e b.n 8016d82 <dhcp_select+0x136>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8016d64: 89b8 ldrh r0, [r7, #12]
8016d66: 693b ldr r3, [r7, #16]
8016d68: f103 01f0 add.w r1, r3, #240 ; 0xf0
8016d6c: 7fbb ldrb r3, [r7, #30]
8016d6e: 4a30 ldr r2, [pc, #192] ; (8016e30 <dhcp_select+0x1e4>)
8016d70: 5cd3 ldrb r3, [r2, r3]
8016d72: 461a mov r2, r3
8016d74: f000 ffb8 bl 8017ce8 <dhcp_option_byte>
8016d78: 4603 mov r3, r0
8016d7a: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8016d7c: 7fbb ldrb r3, [r7, #30]
8016d7e: 3301 adds r3, #1
8016d80: 77bb strb r3, [r7, #30]
8016d82: 7fbb ldrb r3, [r7, #30]
8016d84: 2b02 cmp r3, #2
8016d86: d9ed bls.n 8016d64 <dhcp_select+0x118>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8016d88: 89b8 ldrh r0, [r7, #12]
8016d8a: 693b ldr r3, [r7, #16]
8016d8c: 33f0 adds r3, #240 ; 0xf0
8016d8e: 697a ldr r2, [r7, #20]
8016d90: 4619 mov r1, r3
8016d92: f001 fcbb bl 801870c <dhcp_option_trailer>
/* send broadcast to any DHCP server */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
8016d96: 4b27 ldr r3, [pc, #156] ; (8016e34 <dhcp_select+0x1e8>)
8016d98: 6818 ldr r0, [r3, #0]
8016d9a: 4b27 ldr r3, [pc, #156] ; (8016e38 <dhcp_select+0x1ec>)
8016d9c: 9301 str r3, [sp, #4]
8016d9e: 687b ldr r3, [r7, #4]
8016da0: 9300 str r3, [sp, #0]
8016da2: 2343 movs r3, #67 ; 0x43
8016da4: 4a25 ldr r2, [pc, #148] ; (8016e3c <dhcp_select+0x1f0>)
8016da6: 6979 ldr r1, [r7, #20]
8016da8: f7ff fbda bl 8016560 <udp_sendto_if_src>
8016dac: 4603 mov r3, r0
8016dae: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8016db0: 6978 ldr r0, [r7, #20]
8016db2: f7f9 fc21 bl 80105f8 <pbuf_free>
8016db6: e001 b.n 8016dbc <dhcp_select+0x170>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
result = ERR_MEM;
8016db8: 23ff movs r3, #255 ; 0xff
8016dba: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8016dbc: 69bb ldr r3, [r7, #24]
8016dbe: 799b ldrb r3, [r3, #6]
8016dc0: 2bff cmp r3, #255 ; 0xff
8016dc2: d005 beq.n 8016dd0 <dhcp_select+0x184>
dhcp->tries++;
8016dc4: 69bb ldr r3, [r7, #24]
8016dc6: 799b ldrb r3, [r3, #6]
8016dc8: 3301 adds r3, #1
8016dca: b2da uxtb r2, r3
8016dcc: 69bb ldr r3, [r7, #24]
8016dce: 719a strb r2, [r3, #6]
}
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
8016dd0: 69bb ldr r3, [r7, #24]
8016dd2: 799b ldrb r3, [r3, #6]
8016dd4: 2b05 cmp r3, #5
8016dd6: d80d bhi.n 8016df4 <dhcp_select+0x1a8>
8016dd8: 69bb ldr r3, [r7, #24]
8016dda: 799b ldrb r3, [r3, #6]
8016ddc: 461a mov r2, r3
8016dde: 2301 movs r3, #1
8016de0: 4093 lsls r3, r2
8016de2: b29b uxth r3, r3
8016de4: 461a mov r2, r3
8016de6: 0152 lsls r2, r2, #5
8016de8: 1ad2 subs r2, r2, r3
8016dea: 0092 lsls r2, r2, #2
8016dec: 4413 add r3, r2
8016dee: 00db lsls r3, r3, #3
8016df0: b29b uxth r3, r3
8016df2: e001 b.n 8016df8 <dhcp_select+0x1ac>
8016df4: f64e 2360 movw r3, #60000 ; 0xea60
8016df8: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8016dfa: 89fb ldrh r3, [r7, #14]
8016dfc: f203 13f3 addw r3, r3, #499 ; 0x1f3
8016e00: 4a0f ldr r2, [pc, #60] ; (8016e40 <dhcp_select+0x1f4>)
8016e02: fb82 1203 smull r1, r2, r2, r3
8016e06: 1152 asrs r2, r2, #5
8016e08: 17db asrs r3, r3, #31
8016e0a: 1ad3 subs r3, r2, r3
8016e0c: b29a uxth r2, r3
8016e0e: 69bb ldr r3, [r7, #24]
8016e10: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8016e12: f997 301f ldrsb.w r3, [r7, #31]
}
8016e16: 4618 mov r0, r3
8016e18: 3720 adds r7, #32
8016e1a: 46bd mov sp, r7
8016e1c: bdb0 pop {r4, r5, r7, pc}
8016e1e: bf00 nop
8016e20: 0801e3a8 .word 0x0801e3a8
8016e24: 0801e454 .word 0x0801e454
8016e28: 0801e408 .word 0x0801e408
8016e2c: 0801e470 .word 0x0801e470
8016e30: 20000080 .word 0x20000080
8016e34: 2000876c .word 0x2000876c
8016e38: 08020e78 .word 0x08020e78
8016e3c: 08020e7c .word 0x08020e7c
8016e40: 10624dd3 .word 0x10624dd3
08016e44 <dhcp_coarse_tmr>:
* The DHCP timer that checks for lease renewal/rebind timeouts.
* Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS).
*/
void
dhcp_coarse_tmr(void)
{
8016e44: b580 push {r7, lr}
8016e46: b082 sub sp, #8
8016e48: af00 add r7, sp, #0
struct netif *netif;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
/* iterate through all network interfaces */
NETIF_FOREACH(netif) {
8016e4a: 4b27 ldr r3, [pc, #156] ; (8016ee8 <dhcp_coarse_tmr+0xa4>)
8016e4c: 681b ldr r3, [r3, #0]
8016e4e: 607b str r3, [r7, #4]
8016e50: e042 b.n 8016ed8 <dhcp_coarse_tmr+0x94>
/* only act on DHCP configured interfaces */
struct dhcp *dhcp = netif_dhcp_data(netif);
8016e52: 687b ldr r3, [r7, #4]
8016e54: 6a5b ldr r3, [r3, #36] ; 0x24
8016e56: 603b str r3, [r7, #0]
if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
8016e58: 683b ldr r3, [r7, #0]
8016e5a: 2b00 cmp r3, #0
8016e5c: d039 beq.n 8016ed2 <dhcp_coarse_tmr+0x8e>
8016e5e: 683b ldr r3, [r7, #0]
8016e60: 795b ldrb r3, [r3, #5]
8016e62: 2b00 cmp r3, #0
8016e64: d035 beq.n 8016ed2 <dhcp_coarse_tmr+0x8e>
/* compare lease time to expire timeout */
if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
8016e66: 683b ldr r3, [r7, #0]
8016e68: 8a9b ldrh r3, [r3, #20]
8016e6a: 2b00 cmp r3, #0
8016e6c: d012 beq.n 8016e94 <dhcp_coarse_tmr+0x50>
8016e6e: 683b ldr r3, [r7, #0]
8016e70: 8a5b ldrh r3, [r3, #18]
8016e72: 3301 adds r3, #1
8016e74: b29a uxth r2, r3
8016e76: 683b ldr r3, [r7, #0]
8016e78: 825a strh r2, [r3, #18]
8016e7a: 683b ldr r3, [r7, #0]
8016e7c: 8a5a ldrh r2, [r3, #18]
8016e7e: 683b ldr r3, [r7, #0]
8016e80: 8a9b ldrh r3, [r3, #20]
8016e82: 429a cmp r2, r3
8016e84: d106 bne.n 8016e94 <dhcp_coarse_tmr+0x50>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
/* this clients' lease time has expired */
dhcp_release_and_stop(netif);
8016e86: 6878 ldr r0, [r7, #4]
8016e88: f000 fe46 bl 8017b18 <dhcp_release_and_stop>
dhcp_start(netif);
8016e8c: 6878 ldr r0, [r7, #4]
8016e8e: f000 f96b bl 8017168 <dhcp_start>
8016e92: e01e b.n 8016ed2 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now? */
} else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
8016e94: 683b ldr r3, [r7, #0]
8016e96: 8a1b ldrh r3, [r3, #16]
8016e98: 2b00 cmp r3, #0
8016e9a: d00b beq.n 8016eb4 <dhcp_coarse_tmr+0x70>
8016e9c: 683b ldr r3, [r7, #0]
8016e9e: 8a1b ldrh r3, [r3, #16]
8016ea0: 1e5a subs r2, r3, #1
8016ea2: b291 uxth r1, r2
8016ea4: 683a ldr r2, [r7, #0]
8016ea6: 8211 strh r1, [r2, #16]
8016ea8: 2b01 cmp r3, #1
8016eaa: d103 bne.n 8016eb4 <dhcp_coarse_tmr+0x70>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
/* this clients' rebind timeout triggered */
dhcp_t2_timeout(netif);
8016eac: 6878 ldr r0, [r7, #4]
8016eae: f000 f8c7 bl 8017040 <dhcp_t2_timeout>
8016eb2: e00e b.n 8016ed2 <dhcp_coarse_tmr+0x8e>
/* timer is active (non zero), and triggers (zeroes) now */
} else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
8016eb4: 683b ldr r3, [r7, #0]
8016eb6: 89db ldrh r3, [r3, #14]
8016eb8: 2b00 cmp r3, #0
8016eba: d00a beq.n 8016ed2 <dhcp_coarse_tmr+0x8e>
8016ebc: 683b ldr r3, [r7, #0]
8016ebe: 89db ldrh r3, [r3, #14]
8016ec0: 1e5a subs r2, r3, #1
8016ec2: b291 uxth r1, r2
8016ec4: 683a ldr r2, [r7, #0]
8016ec6: 81d1 strh r1, [r2, #14]
8016ec8: 2b01 cmp r3, #1
8016eca: d102 bne.n 8016ed2 <dhcp_coarse_tmr+0x8e>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
/* this clients' renewal timeout triggered */
dhcp_t1_timeout(netif);
8016ecc: 6878 ldr r0, [r7, #4]
8016ece: f000 f888 bl 8016fe2 <dhcp_t1_timeout>
NETIF_FOREACH(netif) {
8016ed2: 687b ldr r3, [r7, #4]
8016ed4: 681b ldr r3, [r3, #0]
8016ed6: 607b str r3, [r7, #4]
8016ed8: 687b ldr r3, [r7, #4]
8016eda: 2b00 cmp r3, #0
8016edc: d1b9 bne.n 8016e52 <dhcp_coarse_tmr+0xe>
}
}
}
}
8016ede: bf00 nop
8016ee0: 3708 adds r7, #8
8016ee2: 46bd mov sp, r7
8016ee4: bd80 pop {r7, pc}
8016ee6: bf00 nop
8016ee8: 2000f5b0 .word 0x2000f5b0
08016eec <dhcp_fine_tmr>:
* A DHCP server is expected to respond within a short period of time.
* This timer checks whether an outstanding DHCP request is timed out.
*/
void
dhcp_fine_tmr(void)
{
8016eec: b580 push {r7, lr}
8016eee: b082 sub sp, #8
8016ef0: af00 add r7, sp, #0
struct netif *netif;
/* loop through netif's */
NETIF_FOREACH(netif) {
8016ef2: 4b16 ldr r3, [pc, #88] ; (8016f4c <dhcp_fine_tmr+0x60>)
8016ef4: 681b ldr r3, [r3, #0]
8016ef6: 607b str r3, [r7, #4]
8016ef8: e020 b.n 8016f3c <dhcp_fine_tmr+0x50>
struct dhcp *dhcp = netif_dhcp_data(netif);
8016efa: 687b ldr r3, [r7, #4]
8016efc: 6a5b ldr r3, [r3, #36] ; 0x24
8016efe: 603b str r3, [r7, #0]
/* only act on DHCP configured interfaces */
if (dhcp != NULL) {
8016f00: 683b ldr r3, [r7, #0]
8016f02: 2b00 cmp r3, #0
8016f04: d017 beq.n 8016f36 <dhcp_fine_tmr+0x4a>
/* timer is active (non zero), and is about to trigger now */
if (dhcp->request_timeout > 1) {
8016f06: 683b ldr r3, [r7, #0]
8016f08: 891b ldrh r3, [r3, #8]
8016f0a: 2b01 cmp r3, #1
8016f0c: d906 bls.n 8016f1c <dhcp_fine_tmr+0x30>
dhcp->request_timeout--;
8016f0e: 683b ldr r3, [r7, #0]
8016f10: 891b ldrh r3, [r3, #8]
8016f12: 3b01 subs r3, #1
8016f14: b29a uxth r2, r3
8016f16: 683b ldr r3, [r7, #0]
8016f18: 811a strh r2, [r3, #8]
8016f1a: e00c b.n 8016f36 <dhcp_fine_tmr+0x4a>
} else if (dhcp->request_timeout == 1) {
8016f1c: 683b ldr r3, [r7, #0]
8016f1e: 891b ldrh r3, [r3, #8]
8016f20: 2b01 cmp r3, #1
8016f22: d108 bne.n 8016f36 <dhcp_fine_tmr+0x4a>
dhcp->request_timeout--;
8016f24: 683b ldr r3, [r7, #0]
8016f26: 891b ldrh r3, [r3, #8]
8016f28: 3b01 subs r3, #1
8016f2a: b29a uxth r2, r3
8016f2c: 683b ldr r3, [r7, #0]
8016f2e: 811a strh r2, [r3, #8]
/* { dhcp->request_timeout == 0 } */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
/* this client's request timeout triggered */
dhcp_timeout(netif);
8016f30: 6878 ldr r0, [r7, #4]
8016f32: f000 f80d bl 8016f50 <dhcp_timeout>
NETIF_FOREACH(netif) {
8016f36: 687b ldr r3, [r7, #4]
8016f38: 681b ldr r3, [r3, #0]
8016f3a: 607b str r3, [r7, #4]
8016f3c: 687b ldr r3, [r7, #4]
8016f3e: 2b00 cmp r3, #0
8016f40: d1db bne.n 8016efa <dhcp_fine_tmr+0xe>
}
}
}
}
8016f42: bf00 nop
8016f44: 3708 adds r7, #8
8016f46: 46bd mov sp, r7
8016f48: bd80 pop {r7, pc}
8016f4a: bf00 nop
8016f4c: 2000f5b0 .word 0x2000f5b0
08016f50 <dhcp_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_timeout(struct netif *netif)
{
8016f50: b580 push {r7, lr}
8016f52: b084 sub sp, #16
8016f54: af00 add r7, sp, #0
8016f56: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016f58: 687b ldr r3, [r7, #4]
8016f5a: 6a5b ldr r3, [r3, #36] ; 0x24
8016f5c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
/* back-off period has passed, or server selection timed out */
if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
8016f5e: 68fb ldr r3, [r7, #12]
8016f60: 795b ldrb r3, [r3, #5]
8016f62: 2b0c cmp r3, #12
8016f64: d003 beq.n 8016f6e <dhcp_timeout+0x1e>
8016f66: 68fb ldr r3, [r7, #12]
8016f68: 795b ldrb r3, [r3, #5]
8016f6a: 2b06 cmp r3, #6
8016f6c: d103 bne.n 8016f76 <dhcp_timeout+0x26>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
dhcp_discover(netif);
8016f6e: 6878 ldr r0, [r7, #4]
8016f70: f000 fa68 bl 8017444 <dhcp_discover>
dhcp_reboot(netif);
} else {
dhcp_discover(netif);
}
}
}
8016f74: e031 b.n 8016fda <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REQUESTING) {
8016f76: 68fb ldr r3, [r7, #12]
8016f78: 795b ldrb r3, [r3, #5]
8016f7a: 2b01 cmp r3, #1
8016f7c: d10e bne.n 8016f9c <dhcp_timeout+0x4c>
if (dhcp->tries <= 5) {
8016f7e: 68fb ldr r3, [r7, #12]
8016f80: 799b ldrb r3, [r3, #6]
8016f82: 2b05 cmp r3, #5
8016f84: d803 bhi.n 8016f8e <dhcp_timeout+0x3e>
dhcp_select(netif);
8016f86: 6878 ldr r0, [r7, #4]
8016f88: f7ff fe60 bl 8016c4c <dhcp_select>
}
8016f8c: e025 b.n 8016fda <dhcp_timeout+0x8a>
dhcp_release_and_stop(netif);
8016f8e: 6878 ldr r0, [r7, #4]
8016f90: f000 fdc2 bl 8017b18 <dhcp_release_and_stop>
dhcp_start(netif);
8016f94: 6878 ldr r0, [r7, #4]
8016f96: f000 f8e7 bl 8017168 <dhcp_start>
}
8016f9a: e01e b.n 8016fda <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_CHECKING) {
8016f9c: 68fb ldr r3, [r7, #12]
8016f9e: 795b ldrb r3, [r3, #5]
8016fa0: 2b08 cmp r3, #8
8016fa2: d10b bne.n 8016fbc <dhcp_timeout+0x6c>
if (dhcp->tries <= 1) {
8016fa4: 68fb ldr r3, [r7, #12]
8016fa6: 799b ldrb r3, [r3, #6]
8016fa8: 2b01 cmp r3, #1
8016faa: d803 bhi.n 8016fb4 <dhcp_timeout+0x64>
dhcp_check(netif);
8016fac: 6878 ldr r0, [r7, #4]
8016fae: f7ff fdf3 bl 8016b98 <dhcp_check>
}
8016fb2: e012 b.n 8016fda <dhcp_timeout+0x8a>
dhcp_bind(netif);
8016fb4: 6878 ldr r0, [r7, #4]
8016fb6: f000 fae7 bl 8017588 <dhcp_bind>
}
8016fba: e00e b.n 8016fda <dhcp_timeout+0x8a>
} else if (dhcp->state == DHCP_STATE_REBOOTING) {
8016fbc: 68fb ldr r3, [r7, #12]
8016fbe: 795b ldrb r3, [r3, #5]
8016fc0: 2b03 cmp r3, #3
8016fc2: d10a bne.n 8016fda <dhcp_timeout+0x8a>
if (dhcp->tries < REBOOT_TRIES) {
8016fc4: 68fb ldr r3, [r7, #12]
8016fc6: 799b ldrb r3, [r3, #6]
8016fc8: 2b01 cmp r3, #1
8016fca: d803 bhi.n 8016fd4 <dhcp_timeout+0x84>
dhcp_reboot(netif);
8016fcc: 6878 ldr r0, [r7, #4]
8016fce: f000 fced bl 80179ac <dhcp_reboot>
}
8016fd2: e002 b.n 8016fda <dhcp_timeout+0x8a>
dhcp_discover(netif);
8016fd4: 6878 ldr r0, [r7, #4]
8016fd6: f000 fa35 bl 8017444 <dhcp_discover>
}
8016fda: bf00 nop
8016fdc: 3710 adds r7, #16
8016fde: 46bd mov sp, r7
8016fe0: bd80 pop {r7, pc}
08016fe2 <dhcp_t1_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t1_timeout(struct netif *netif)
{
8016fe2: b580 push {r7, lr}
8016fe4: b084 sub sp, #16
8016fe6: af00 add r7, sp, #0
8016fe8: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8016fea: 687b ldr r3, [r7, #4]
8016fec: 6a5b ldr r3, [r3, #36] ; 0x24
8016fee: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8016ff0: 68fb ldr r3, [r7, #12]
8016ff2: 795b ldrb r3, [r3, #5]
8016ff4: 2b01 cmp r3, #1
8016ff6: d007 beq.n 8017008 <dhcp_t1_timeout+0x26>
8016ff8: 68fb ldr r3, [r7, #12]
8016ffa: 795b ldrb r3, [r3, #5]
8016ffc: 2b0a cmp r3, #10
8016ffe: d003 beq.n 8017008 <dhcp_t1_timeout+0x26>
(dhcp->state == DHCP_STATE_RENEWING)) {
8017000: 68fb ldr r3, [r7, #12]
8017002: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8017004: 2b05 cmp r3, #5
8017006: d117 bne.n 8017038 <dhcp_t1_timeout+0x56>
* eventually time-out if renew tries fail. */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t1_timeout(): must renew\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
dhcp_renew(netif);
8017008: 6878 ldr r0, [r7, #4]
801700a: f000 fb97 bl 801773c <dhcp_renew>
/* Calculate next timeout */
if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
801700e: 68fb ldr r3, [r7, #12]
8017010: 899b ldrh r3, [r3, #12]
8017012: 461a mov r2, r3
8017014: 68fb ldr r3, [r7, #12]
8017016: 8a5b ldrh r3, [r3, #18]
8017018: 1ad3 subs r3, r2, r3
801701a: 2b01 cmp r3, #1
801701c: dd0c ble.n 8017038 <dhcp_t1_timeout+0x56>
dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2);
801701e: 68fb ldr r3, [r7, #12]
8017020: 899b ldrh r3, [r3, #12]
8017022: 461a mov r2, r3
8017024: 68fb ldr r3, [r7, #12]
8017026: 8a5b ldrh r3, [r3, #18]
8017028: 1ad3 subs r3, r2, r3
801702a: 2b00 cmp r3, #0
801702c: da00 bge.n 8017030 <dhcp_t1_timeout+0x4e>
801702e: 3301 adds r3, #1
8017030: 105b asrs r3, r3, #1
8017032: b29a uxth r2, r3
8017034: 68fb ldr r3, [r7, #12]
8017036: 81da strh r2, [r3, #14]
}
}
}
8017038: bf00 nop
801703a: 3710 adds r7, #16
801703c: 46bd mov sp, r7
801703e: bd80 pop {r7, pc}
08017040 <dhcp_t2_timeout>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_t2_timeout(struct netif *netif)
{
8017040: b580 push {r7, lr}
8017042: b084 sub sp, #16
8017044: af00 add r7, sp, #0
8017046: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017048: 687b ldr r3, [r7, #4]
801704a: 6a5b ldr r3, [r3, #36] ; 0x24
801704c: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
801704e: 68fb ldr r3, [r7, #12]
8017050: 795b ldrb r3, [r3, #5]
8017052: 2b01 cmp r3, #1
8017054: d00b beq.n 801706e <dhcp_t2_timeout+0x2e>
8017056: 68fb ldr r3, [r7, #12]
8017058: 795b ldrb r3, [r3, #5]
801705a: 2b0a cmp r3, #10
801705c: d007 beq.n 801706e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
801705e: 68fb ldr r3, [r7, #12]
8017060: 795b ldrb r3, [r3, #5]
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
8017062: 2b05 cmp r3, #5
8017064: d003 beq.n 801706e <dhcp_t2_timeout+0x2e>
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
8017066: 68fb ldr r3, [r7, #12]
8017068: 795b ldrb r3, [r3, #5]
801706a: 2b04 cmp r3, #4
801706c: d117 bne.n 801709e <dhcp_t2_timeout+0x5e>
/* just retry to rebind */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
("dhcp_t2_timeout(): must rebind\n"));
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
dhcp_rebind(netif);
801706e: 6878 ldr r0, [r7, #4]
8017070: f000 fc00 bl 8017874 <dhcp_rebind>
/* Calculate next timeout */
if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
8017074: 68fb ldr r3, [r7, #12]
8017076: 8a9b ldrh r3, [r3, #20]
8017078: 461a mov r2, r3
801707a: 68fb ldr r3, [r7, #12]
801707c: 8a5b ldrh r3, [r3, #18]
801707e: 1ad3 subs r3, r2, r3
8017080: 2b01 cmp r3, #1
8017082: dd0c ble.n 801709e <dhcp_t2_timeout+0x5e>
dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2);
8017084: 68fb ldr r3, [r7, #12]
8017086: 8a9b ldrh r3, [r3, #20]
8017088: 461a mov r2, r3
801708a: 68fb ldr r3, [r7, #12]
801708c: 8a5b ldrh r3, [r3, #18]
801708e: 1ad3 subs r3, r2, r3
8017090: 2b00 cmp r3, #0
8017092: da00 bge.n 8017096 <dhcp_t2_timeout+0x56>
8017094: 3301 adds r3, #1
8017096: 105b asrs r3, r3, #1
8017098: b29a uxth r2, r3
801709a: 68fb ldr r3, [r7, #12]
801709c: 821a strh r2, [r3, #16]
}
}
}
801709e: bf00 nop
80170a0: 3710 adds r7, #16
80170a2: 46bd mov sp, r7
80170a4: bd80 pop {r7, pc}
...
080170a8 <dhcp_handle_ack>:
*
* @param netif the netif under DHCP control
*/
static void
dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in)
{
80170a8: b580 push {r7, lr}
80170aa: b084 sub sp, #16
80170ac: af00 add r7, sp, #0
80170ae: 6078 str r0, [r7, #4]
80170b0: 6039 str r1, [r7, #0]
struct dhcp *dhcp = netif_dhcp_data(netif);
80170b2: 687b ldr r3, [r7, #4]
80170b4: 6a5b ldr r3, [r3, #36] ; 0x24
80170b6: 60fb str r3, [r7, #12]
#if LWIP_DHCP_GET_NTP_SRV
ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
#endif
/* clear options we might not get from the ACK */
ip4_addr_set_zero(&dhcp->offered_sn_mask);
80170b8: 68fb ldr r3, [r7, #12]
80170ba: 2200 movs r2, #0
80170bc: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
80170be: 68fb ldr r3, [r7, #12]
80170c0: 2200 movs r2, #0
80170c2: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* lease time given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
80170c4: 4b26 ldr r3, [pc, #152] ; (8017160 <dhcp_handle_ack+0xb8>)
80170c6: 78db ldrb r3, [r3, #3]
80170c8: 2b00 cmp r3, #0
80170ca: d003 beq.n 80170d4 <dhcp_handle_ack+0x2c>
/* remember offered lease time */
dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
80170cc: 4b25 ldr r3, [pc, #148] ; (8017164 <dhcp_handle_ack+0xbc>)
80170ce: 68da ldr r2, [r3, #12]
80170d0: 68fb ldr r3, [r7, #12]
80170d2: 629a str r2, [r3, #40] ; 0x28
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
80170d4: 4b22 ldr r3, [pc, #136] ; (8017160 <dhcp_handle_ack+0xb8>)
80170d6: 791b ldrb r3, [r3, #4]
80170d8: 2b00 cmp r3, #0
80170da: d004 beq.n 80170e6 <dhcp_handle_ack+0x3e>
/* remember given renewal period */
dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
80170dc: 4b21 ldr r3, [pc, #132] ; (8017164 <dhcp_handle_ack+0xbc>)
80170de: 691a ldr r2, [r3, #16]
80170e0: 68fb ldr r3, [r7, #12]
80170e2: 62da str r2, [r3, #44] ; 0x2c
80170e4: e004 b.n 80170f0 <dhcp_handle_ack+0x48>
} else {
/* calculate safe periods for renewal */
dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
80170e6: 68fb ldr r3, [r7, #12]
80170e8: 6a9b ldr r3, [r3, #40] ; 0x28
80170ea: 085a lsrs r2, r3, #1
80170ec: 68fb ldr r3, [r7, #12]
80170ee: 62da str r2, [r3, #44] ; 0x2c
}
/* renewal period given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
80170f0: 4b1b ldr r3, [pc, #108] ; (8017160 <dhcp_handle_ack+0xb8>)
80170f2: 795b ldrb r3, [r3, #5]
80170f4: 2b00 cmp r3, #0
80170f6: d004 beq.n 8017102 <dhcp_handle_ack+0x5a>
/* remember given rebind period */
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
80170f8: 4b1a ldr r3, [pc, #104] ; (8017164 <dhcp_handle_ack+0xbc>)
80170fa: 695a ldr r2, [r3, #20]
80170fc: 68fb ldr r3, [r7, #12]
80170fe: 631a str r2, [r3, #48] ; 0x30
8017100: e007 b.n 8017112 <dhcp_handle_ack+0x6a>
} else {
/* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
8017102: 68fb ldr r3, [r7, #12]
8017104: 6a9a ldr r2, [r3, #40] ; 0x28
8017106: 4613 mov r3, r2
8017108: 00db lsls r3, r3, #3
801710a: 1a9b subs r3, r3, r2
801710c: 08da lsrs r2, r3, #3
801710e: 68fb ldr r3, [r7, #12]
8017110: 631a str r2, [r3, #48] ; 0x30
}
/* (y)our internet address */
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
8017112: 683b ldr r3, [r7, #0]
8017114: 691a ldr r2, [r3, #16]
8017116: 68fb ldr r3, [r7, #12]
8017118: 61da str r2, [r3, #28]
boot file name copied in dhcp_parse_reply if not overloaded */
ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr);
#endif /* LWIP_DHCP_BOOTP_FILE */
/* subnet mask given? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
801711a: 4b11 ldr r3, [pc, #68] ; (8017160 <dhcp_handle_ack+0xb8>)
801711c: 799b ldrb r3, [r3, #6]
801711e: 2b00 cmp r3, #0
8017120: d00b beq.n 801713a <dhcp_handle_ack+0x92>
/* remember given subnet mask */
ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
8017122: 4b10 ldr r3, [pc, #64] ; (8017164 <dhcp_handle_ack+0xbc>)
8017124: 699b ldr r3, [r3, #24]
8017126: 4618 mov r0, r3
8017128: f7f7 fec7 bl 800eeba <lwip_htonl>
801712c: 4602 mov r2, r0
801712e: 68fb ldr r3, [r7, #12]
8017130: 621a str r2, [r3, #32]
dhcp->subnet_mask_given = 1;
8017132: 68fb ldr r3, [r7, #12]
8017134: 2201 movs r2, #1
8017136: 71da strb r2, [r3, #7]
8017138: e002 b.n 8017140 <dhcp_handle_ack+0x98>
} else {
dhcp->subnet_mask_given = 0;
801713a: 68fb ldr r3, [r7, #12]
801713c: 2200 movs r2, #0
801713e: 71da strb r2, [r3, #7]
}
/* gateway router */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
8017140: 4b07 ldr r3, [pc, #28] ; (8017160 <dhcp_handle_ack+0xb8>)
8017142: 79db ldrb r3, [r3, #7]
8017144: 2b00 cmp r3, #0
8017146: d007 beq.n 8017158 <dhcp_handle_ack+0xb0>
ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
8017148: 4b06 ldr r3, [pc, #24] ; (8017164 <dhcp_handle_ack+0xbc>)
801714a: 69db ldr r3, [r3, #28]
801714c: 4618 mov r0, r3
801714e: f7f7 feb4 bl 800eeba <lwip_htonl>
8017152: 4602 mov r2, r0
8017154: 68fb ldr r3, [r7, #12]
8017156: 625a str r2, [r3, #36] ; 0x24
ip_addr_t dns_addr;
ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
dns_setserver(n, &dns_addr);
}
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
}
8017158: bf00 nop
801715a: 3710 adds r7, #16
801715c: 46bd mov sp, r7
801715e: bd80 pop {r7, pc}
8017160: 2000f5dc .word 0x2000f5dc
8017164: 2000f5e4 .word 0x2000f5e4
08017168 <dhcp_start>:
* - ERR_OK - No error
* - ERR_MEM - Out of memory
*/
err_t
dhcp_start(struct netif *netif)
{
8017168: b580 push {r7, lr}
801716a: b084 sub sp, #16
801716c: af00 add r7, sp, #0
801716e: 6078 str r0, [r7, #4]
struct dhcp *dhcp;
err_t result;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
8017170: 687b ldr r3, [r7, #4]
8017172: 2b00 cmp r3, #0
8017174: d109 bne.n 801718a <dhcp_start+0x22>
8017176: 4b37 ldr r3, [pc, #220] ; (8017254 <dhcp_start+0xec>)
8017178: f240 22e7 movw r2, #743 ; 0x2e7
801717c: 4936 ldr r1, [pc, #216] ; (8017258 <dhcp_start+0xf0>)
801717e: 4837 ldr r0, [pc, #220] ; (801725c <dhcp_start+0xf4>)
8017180: f003 ff50 bl 801b024 <iprintf>
8017184: f06f 030f mvn.w r3, #15
8017188: e060 b.n 801724c <dhcp_start+0xe4>
LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
801718a: 687b ldr r3, [r7, #4]
801718c: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8017190: f003 0301 and.w r3, r3, #1
8017194: 2b00 cmp r3, #0
8017196: d109 bne.n 80171ac <dhcp_start+0x44>
8017198: 4b2e ldr r3, [pc, #184] ; (8017254 <dhcp_start+0xec>)
801719a: f44f 723a mov.w r2, #744 ; 0x2e8
801719e: 4930 ldr r1, [pc, #192] ; (8017260 <dhcp_start+0xf8>)
80171a0: 482e ldr r0, [pc, #184] ; (801725c <dhcp_start+0xf4>)
80171a2: f003 ff3f bl 801b024 <iprintf>
80171a6: f06f 030f mvn.w r3, #15
80171aa: e04f b.n 801724c <dhcp_start+0xe4>
dhcp = netif_dhcp_data(netif);
80171ac: 687b ldr r3, [r7, #4]
80171ae: 6a5b ldr r3, [r3, #36] ; 0x24
80171b0: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* check MTU of the netif */
if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
80171b2: 687b ldr r3, [r7, #4]
80171b4: 8d1b ldrh r3, [r3, #40] ; 0x28
80171b6: f5b3 7f10 cmp.w r3, #576 ; 0x240
80171ba: d202 bcs.n 80171c2 <dhcp_start+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
return ERR_MEM;
80171bc: f04f 33ff mov.w r3, #4294967295
80171c0: e044 b.n 801724c <dhcp_start+0xe4>
}
/* no DHCP client attached yet? */
if (dhcp == NULL) {
80171c2: 68fb ldr r3, [r7, #12]
80171c4: 2b00 cmp r3, #0
80171c6: d10d bne.n 80171e4 <dhcp_start+0x7c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n"));
dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
80171c8: 2034 movs r0, #52 ; 0x34
80171ca: f7f8 f995 bl 800f4f8 <mem_malloc>
80171ce: 60f8 str r0, [r7, #12]
if (dhcp == NULL) {
80171d0: 68fb ldr r3, [r7, #12]
80171d2: 2b00 cmp r3, #0
80171d4: d102 bne.n 80171dc <dhcp_start+0x74>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
return ERR_MEM;
80171d6: f04f 33ff mov.w r3, #4294967295
80171da: e037 b.n 801724c <dhcp_start+0xe4>
}
/* store this dhcp client in the netif */
netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
80171dc: 687b ldr r3, [r7, #4]
80171de: 68fa ldr r2, [r7, #12]
80171e0: 625a str r2, [r3, #36] ; 0x24
80171e2: e005 b.n 80171f0 <dhcp_start+0x88>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
/* already has DHCP client attached */
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
if (dhcp->pcb_allocated != 0) {
80171e4: 68fb ldr r3, [r7, #12]
80171e6: 791b ldrb r3, [r3, #4]
80171e8: 2b00 cmp r3, #0
80171ea: d001 beq.n 80171f0 <dhcp_start+0x88>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
80171ec: f7ff fc90 bl 8016b10 <dhcp_dec_pcb_refcount>
}
/* dhcp is cleared below, no need to reset flag*/
}
/* clear data structure */
memset(dhcp, 0, sizeof(struct dhcp));
80171f0: 2234 movs r2, #52 ; 0x34
80171f2: 2100 movs r1, #0
80171f4: 68f8 ldr r0, [r7, #12]
80171f6: f003 ff0d bl 801b014 <memset>
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
80171fa: f7ff fc37 bl 8016a6c <dhcp_inc_pcb_refcount>
80171fe: 4603 mov r3, r0
8017200: 2b00 cmp r3, #0
8017202: d002 beq.n 801720a <dhcp_start+0xa2>
return ERR_MEM;
8017204: f04f 33ff mov.w r3, #4294967295
8017208: e020 b.n 801724c <dhcp_start+0xe4>
}
dhcp->pcb_allocated = 1;
801720a: 68fb ldr r3, [r7, #12]
801720c: 2201 movs r2, #1
801720e: 711a strb r2, [r3, #4]
if (!netif_is_link_up(netif)) {
8017210: 687b ldr r3, [r7, #4]
8017212: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8017216: f003 0304 and.w r3, r3, #4
801721a: 2b00 cmp r3, #0
801721c: d105 bne.n 801722a <dhcp_start+0xc2>
/* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
dhcp_set_state(dhcp, DHCP_STATE_INIT);
801721e: 2102 movs r1, #2
8017220: 68f8 ldr r0, [r7, #12]
8017222: f000 fd13 bl 8017c4c <dhcp_set_state>
return ERR_OK;
8017226: 2300 movs r3, #0
8017228: e010 b.n 801724c <dhcp_start+0xe4>
}
/* (re)start the DHCP negotiation */
result = dhcp_discover(netif);
801722a: 6878 ldr r0, [r7, #4]
801722c: f000 f90a bl 8017444 <dhcp_discover>
8017230: 4603 mov r3, r0
8017232: 72fb strb r3, [r7, #11]
if (result != ERR_OK) {
8017234: f997 300b ldrsb.w r3, [r7, #11]
8017238: 2b00 cmp r3, #0
801723a: d005 beq.n 8017248 <dhcp_start+0xe0>
/* free resources allocated above */
dhcp_release_and_stop(netif);
801723c: 6878 ldr r0, [r7, #4]
801723e: f000 fc6b bl 8017b18 <dhcp_release_and_stop>
return ERR_MEM;
8017242: f04f 33ff mov.w r3, #4294967295
8017246: e001 b.n 801724c <dhcp_start+0xe4>
}
return result;
8017248: f997 300b ldrsb.w r3, [r7, #11]
}
801724c: 4618 mov r0, r3
801724e: 3710 adds r7, #16
8017250: 46bd mov sp, r7
8017252: bd80 pop {r7, pc}
8017254: 0801e3a8 .word 0x0801e3a8
8017258: 0801e48c .word 0x0801e48c
801725c: 0801e408 .word 0x0801e408
8017260: 0801e4d0 .word 0x0801e4d0
08017264 <dhcp_network_changed>:
* This enters the REBOOTING state to verify that the currently bound
* address is still valid.
*/
void
dhcp_network_changed(struct netif *netif)
{
8017264: b580 push {r7, lr}
8017266: b084 sub sp, #16
8017268: af00 add r7, sp, #0
801726a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801726c: 687b ldr r3, [r7, #4]
801726e: 6a5b ldr r3, [r3, #36] ; 0x24
8017270: 60fb str r3, [r7, #12]
if (!dhcp) {
8017272: 68fb ldr r3, [r7, #12]
8017274: 2b00 cmp r3, #0
8017276: d037 beq.n 80172e8 <dhcp_network_changed+0x84>
return;
}
switch (dhcp->state) {
8017278: 68fb ldr r3, [r7, #12]
801727a: 795b ldrb r3, [r3, #5]
801727c: 2b0a cmp r3, #10
801727e: d820 bhi.n 80172c2 <dhcp_network_changed+0x5e>
8017280: a201 add r2, pc, #4 ; (adr r2, 8017288 <dhcp_network_changed+0x24>)
8017282: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8017286: bf00 nop
8017288: 080172ed .word 0x080172ed
801728c: 080172c3 .word 0x080172c3
8017290: 080172c3 .word 0x080172c3
8017294: 080172b5 .word 0x080172b5
8017298: 080172b5 .word 0x080172b5
801729c: 080172b5 .word 0x080172b5
80172a0: 080172c3 .word 0x080172c3
80172a4: 080172c3 .word 0x080172c3
80172a8: 080172c3 .word 0x080172c3
80172ac: 080172c3 .word 0x080172c3
80172b0: 080172b5 .word 0x080172b5
case DHCP_STATE_REBINDING:
case DHCP_STATE_RENEWING:
case DHCP_STATE_BOUND:
case DHCP_STATE_REBOOTING:
dhcp->tries = 0;
80172b4: 68fb ldr r3, [r7, #12]
80172b6: 2200 movs r2, #0
80172b8: 719a strb r2, [r3, #6]
dhcp_reboot(netif);
80172ba: 6878 ldr r0, [r7, #4]
80172bc: f000 fb76 bl 80179ac <dhcp_reboot>
break;
80172c0: e015 b.n 80172ee <dhcp_network_changed+0x8a>
case DHCP_STATE_OFF:
/* stay off */
break;
default:
LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF);
80172c2: 68fb ldr r3, [r7, #12]
80172c4: 795b ldrb r3, [r3, #5]
80172c6: 2b0c cmp r3, #12
80172c8: d906 bls.n 80172d8 <dhcp_network_changed+0x74>
80172ca: 4b0a ldr r3, [pc, #40] ; (80172f4 <dhcp_network_changed+0x90>)
80172cc: f240 326d movw r2, #877 ; 0x36d
80172d0: 4909 ldr r1, [pc, #36] ; (80172f8 <dhcp_network_changed+0x94>)
80172d2: 480a ldr r0, [pc, #40] ; (80172fc <dhcp_network_changed+0x98>)
80172d4: f003 fea6 bl 801b024 <iprintf>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
/* ensure we start with short timeouts, even if already discovering */
dhcp->tries = 0;
80172d8: 68fb ldr r3, [r7, #12]
80172da: 2200 movs r2, #0
80172dc: 719a strb r2, [r3, #6]
dhcp_discover(netif);
80172de: 6878 ldr r0, [r7, #4]
80172e0: f000 f8b0 bl 8017444 <dhcp_discover>
break;
80172e4: bf00 nop
80172e6: e002 b.n 80172ee <dhcp_network_changed+0x8a>
return;
80172e8: bf00 nop
80172ea: e000 b.n 80172ee <dhcp_network_changed+0x8a>
break;
80172ec: bf00 nop
}
}
80172ee: 3710 adds r7, #16
80172f0: 46bd mov sp, r7
80172f2: bd80 pop {r7, pc}
80172f4: 0801e3a8 .word 0x0801e3a8
80172f8: 0801e4f4 .word 0x0801e4f4
80172fc: 0801e408 .word 0x0801e408
08017300 <dhcp_arp_reply>:
* @param netif the network interface on which the reply was received
* @param addr The IP address we received a reply from
*/
void
dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
{
8017300: b580 push {r7, lr}
8017302: b084 sub sp, #16
8017304: af00 add r7, sp, #0
8017306: 6078 str r0, [r7, #4]
8017308: 6039 str r1, [r7, #0]
struct dhcp *dhcp;
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
801730a: 687b ldr r3, [r7, #4]
801730c: 2b00 cmp r3, #0
801730e: d107 bne.n 8017320 <dhcp_arp_reply+0x20>
8017310: 4b0e ldr r3, [pc, #56] ; (801734c <dhcp_arp_reply+0x4c>)
8017312: f240 328b movw r2, #907 ; 0x38b
8017316: 490e ldr r1, [pc, #56] ; (8017350 <dhcp_arp_reply+0x50>)
8017318: 480e ldr r0, [pc, #56] ; (8017354 <dhcp_arp_reply+0x54>)
801731a: f003 fe83 bl 801b024 <iprintf>
801731e: e012 b.n 8017346 <dhcp_arp_reply+0x46>
dhcp = netif_dhcp_data(netif);
8017320: 687b ldr r3, [r7, #4]
8017322: 6a5b ldr r3, [r3, #36] ; 0x24
8017324: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
/* is a DHCP client doing an ARP check? */
if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) {
8017326: 68fb ldr r3, [r7, #12]
8017328: 2b00 cmp r3, #0
801732a: d00c beq.n 8017346 <dhcp_arp_reply+0x46>
801732c: 68fb ldr r3, [r7, #12]
801732e: 795b ldrb r3, [r3, #5]
8017330: 2b08 cmp r3, #8
8017332: d108 bne.n 8017346 <dhcp_arp_reply+0x46>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
ip4_addr_get_u32(addr)));
/* did a host respond with the address we
were offered by the DHCP server? */
if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) {
8017334: 683b ldr r3, [r7, #0]
8017336: 681a ldr r2, [r3, #0]
8017338: 68fb ldr r3, [r7, #12]
801733a: 69db ldr r3, [r3, #28]
801733c: 429a cmp r2, r3
801733e: d102 bne.n 8017346 <dhcp_arp_reply+0x46>
/* we will not accept the offered address */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
dhcp_decline(netif);
8017340: 6878 ldr r0, [r7, #4]
8017342: f000 f809 bl 8017358 <dhcp_decline>
}
}
}
8017346: 3710 adds r7, #16
8017348: 46bd mov sp, r7
801734a: bd80 pop {r7, pc}
801734c: 0801e3a8 .word 0x0801e3a8
8017350: 0801e48c .word 0x0801e48c
8017354: 0801e408 .word 0x0801e408
08017358 <dhcp_decline>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_decline(struct netif *netif)
{
8017358: b5b0 push {r4, r5, r7, lr}
801735a: b08a sub sp, #40 ; 0x28
801735c: af02 add r7, sp, #8
801735e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017360: 687b ldr r3, [r7, #4]
8017362: 6a5b ldr r3, [r3, #36] ; 0x24
8017364: 61bb str r3, [r7, #24]
u16_t msecs;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
8017366: 210c movs r1, #12
8017368: 69b8 ldr r0, [r7, #24]
801736a: f000 fc6f bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len);
801736e: f107 030c add.w r3, r7, #12
8017372: 2204 movs r2, #4
8017374: 69b9 ldr r1, [r7, #24]
8017376: 6878 ldr r0, [r7, #4]
8017378: f001 f8f2 bl 8018560 <dhcp_create_msg>
801737c: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801737e: 697b ldr r3, [r7, #20]
8017380: 2b00 cmp r3, #0
8017382: d035 beq.n 80173f0 <dhcp_decline+0x98>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017384: 697b ldr r3, [r7, #20]
8017386: 685b ldr r3, [r3, #4]
8017388: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
801738a: 89b8 ldrh r0, [r7, #12]
801738c: 693b ldr r3, [r7, #16]
801738e: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017392: 2304 movs r3, #4
8017394: 2232 movs r2, #50 ; 0x32
8017396: f000 fc73 bl 8017c80 <dhcp_option>
801739a: 4603 mov r3, r0
801739c: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
801739e: 89bc ldrh r4, [r7, #12]
80173a0: 693b ldr r3, [r7, #16]
80173a2: f103 05f0 add.w r5, r3, #240 ; 0xf0
80173a6: 69bb ldr r3, [r7, #24]
80173a8: 69db ldr r3, [r3, #28]
80173aa: 4618 mov r0, r3
80173ac: f7f7 fd85 bl 800eeba <lwip_htonl>
80173b0: 4603 mov r3, r0
80173b2: 461a mov r2, r3
80173b4: 4629 mov r1, r5
80173b6: 4620 mov r0, r4
80173b8: f000 fcee bl 8017d98 <dhcp_option_long>
80173bc: 4603 mov r3, r0
80173be: 81bb strh r3, [r7, #12]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80173c0: 89b8 ldrh r0, [r7, #12]
80173c2: 693b ldr r3, [r7, #16]
80173c4: 33f0 adds r3, #240 ; 0xf0
80173c6: 697a ldr r2, [r7, #20]
80173c8: 4619 mov r1, r3
80173ca: f001 f99f bl 801870c <dhcp_option_trailer>
/* per section 4.4.4, broadcast DECLINE messages */
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
80173ce: 4b19 ldr r3, [pc, #100] ; (8017434 <dhcp_decline+0xdc>)
80173d0: 6818 ldr r0, [r3, #0]
80173d2: 4b19 ldr r3, [pc, #100] ; (8017438 <dhcp_decline+0xe0>)
80173d4: 9301 str r3, [sp, #4]
80173d6: 687b ldr r3, [r7, #4]
80173d8: 9300 str r3, [sp, #0]
80173da: 2343 movs r3, #67 ; 0x43
80173dc: 4a17 ldr r2, [pc, #92] ; (801743c <dhcp_decline+0xe4>)
80173de: 6979 ldr r1, [r7, #20]
80173e0: f7ff f8be bl 8016560 <udp_sendto_if_src>
80173e4: 4603 mov r3, r0
80173e6: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
80173e8: 6978 ldr r0, [r7, #20]
80173ea: f7f9 f905 bl 80105f8 <pbuf_free>
80173ee: e001 b.n 80173f4 <dhcp_decline+0x9c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_decline: could not allocate DHCP request\n"));
result = ERR_MEM;
80173f0: 23ff movs r3, #255 ; 0xff
80173f2: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
80173f4: 69bb ldr r3, [r7, #24]
80173f6: 799b ldrb r3, [r3, #6]
80173f8: 2bff cmp r3, #255 ; 0xff
80173fa: d005 beq.n 8017408 <dhcp_decline+0xb0>
dhcp->tries++;
80173fc: 69bb ldr r3, [r7, #24]
80173fe: 799b ldrb r3, [r3, #6]
8017400: 3301 adds r3, #1
8017402: b2da uxtb r2, r3
8017404: 69bb ldr r3, [r7, #24]
8017406: 719a strb r2, [r3, #6]
}
msecs = 10 * 1000;
8017408: f242 7310 movw r3, #10000 ; 0x2710
801740c: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
801740e: 89fb ldrh r3, [r7, #14]
8017410: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017414: 4a0a ldr r2, [pc, #40] ; (8017440 <dhcp_decline+0xe8>)
8017416: fb82 1203 smull r1, r2, r2, r3
801741a: 1152 asrs r2, r2, #5
801741c: 17db asrs r3, r3, #31
801741e: 1ad3 subs r3, r2, r3
8017420: b29a uxth r2, r3
8017422: 69bb ldr r3, [r7, #24]
8017424: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017426: f997 301f ldrsb.w r3, [r7, #31]
}
801742a: 4618 mov r0, r3
801742c: 3720 adds r7, #32
801742e: 46bd mov sp, r7
8017430: bdb0 pop {r4, r5, r7, pc}
8017432: bf00 nop
8017434: 2000876c .word 0x2000876c
8017438: 08020e78 .word 0x08020e78
801743c: 08020e7c .word 0x08020e7c
8017440: 10624dd3 .word 0x10624dd3
08017444 <dhcp_discover>:
*
* @param netif the netif under DHCP control
*/
static err_t
dhcp_discover(struct netif *netif)
{
8017444: b580 push {r7, lr}
8017446: b08a sub sp, #40 ; 0x28
8017448: af02 add r7, sp, #8
801744a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801744c: 687b ldr r3, [r7, #4]
801744e: 6a5b ldr r3, [r3, #36] ; 0x24
8017450: 61bb str r3, [r7, #24]
err_t result = ERR_OK;
8017452: 2300 movs r3, #0
8017454: 75fb strb r3, [r7, #23]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
ip4_addr_set_any(&dhcp->offered_ip_addr);
8017456: 69bb ldr r3, [r7, #24]
8017458: 2200 movs r2, #0
801745a: 61da str r2, [r3, #28]
dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
801745c: 2106 movs r1, #6
801745e: 69b8 ldr r0, [r7, #24]
8017460: f000 fbf4 bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len);
8017464: f107 0308 add.w r3, r7, #8
8017468: 2201 movs r2, #1
801746a: 69b9 ldr r1, [r7, #24]
801746c: 6878 ldr r0, [r7, #4]
801746e: f001 f877 bl 8018560 <dhcp_create_msg>
8017472: 6138 str r0, [r7, #16]
if (p_out != NULL) {
8017474: 693b ldr r3, [r7, #16]
8017476: 2b00 cmp r3, #0
8017478: d04b beq.n 8017512 <dhcp_discover+0xce>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
801747a: 693b ldr r3, [r7, #16]
801747c: 685b ldr r3, [r3, #4]
801747e: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
8017480: 8938 ldrh r0, [r7, #8]
8017482: 68fb ldr r3, [r7, #12]
8017484: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017488: 2302 movs r3, #2
801748a: 2239 movs r2, #57 ; 0x39
801748c: f000 fbf8 bl 8017c80 <dhcp_option>
8017490: 4603 mov r3, r0
8017492: 813b strh r3, [r7, #8]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017494: 8938 ldrh r0, [r7, #8]
8017496: 68fb ldr r3, [r7, #12]
8017498: f103 01f0 add.w r1, r3, #240 ; 0xf0
801749c: 687b ldr r3, [r7, #4]
801749e: 8d1b ldrh r3, [r3, #40] ; 0x28
80174a0: 461a mov r2, r3
80174a2: f000 fc47 bl 8017d34 <dhcp_option_short>
80174a6: 4603 mov r3, r0
80174a8: 813b strh r3, [r7, #8]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
80174aa: 8938 ldrh r0, [r7, #8]
80174ac: 68fb ldr r3, [r7, #12]
80174ae: f103 01f0 add.w r1, r3, #240 ; 0xf0
80174b2: 2303 movs r3, #3
80174b4: 2237 movs r2, #55 ; 0x37
80174b6: f000 fbe3 bl 8017c80 <dhcp_option>
80174ba: 4603 mov r3, r0
80174bc: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80174be: 2300 movs r3, #0
80174c0: 77fb strb r3, [r7, #31]
80174c2: e00e b.n 80174e2 <dhcp_discover+0x9e>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80174c4: 8938 ldrh r0, [r7, #8]
80174c6: 68fb ldr r3, [r7, #12]
80174c8: f103 01f0 add.w r1, r3, #240 ; 0xf0
80174cc: 7ffb ldrb r3, [r7, #31]
80174ce: 4a29 ldr r2, [pc, #164] ; (8017574 <dhcp_discover+0x130>)
80174d0: 5cd3 ldrb r3, [r2, r3]
80174d2: 461a mov r2, r3
80174d4: f000 fc08 bl 8017ce8 <dhcp_option_byte>
80174d8: 4603 mov r3, r0
80174da: 813b strh r3, [r7, #8]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80174dc: 7ffb ldrb r3, [r7, #31]
80174de: 3301 adds r3, #1
80174e0: 77fb strb r3, [r7, #31]
80174e2: 7ffb ldrb r3, [r7, #31]
80174e4: 2b02 cmp r3, #2
80174e6: d9ed bls.n 80174c4 <dhcp_discover+0x80>
}
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80174e8: 8938 ldrh r0, [r7, #8]
80174ea: 68fb ldr r3, [r7, #12]
80174ec: 33f0 adds r3, #240 ; 0xf0
80174ee: 693a ldr r2, [r7, #16]
80174f0: 4619 mov r1, r3
80174f2: f001 f90b bl 801870c <dhcp_option_trailer>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n"));
udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
80174f6: 4b20 ldr r3, [pc, #128] ; (8017578 <dhcp_discover+0x134>)
80174f8: 6818 ldr r0, [r3, #0]
80174fa: 4b20 ldr r3, [pc, #128] ; (801757c <dhcp_discover+0x138>)
80174fc: 9301 str r3, [sp, #4]
80174fe: 687b ldr r3, [r7, #4]
8017500: 9300 str r3, [sp, #0]
8017502: 2343 movs r3, #67 ; 0x43
8017504: 4a1e ldr r2, [pc, #120] ; (8017580 <dhcp_discover+0x13c>)
8017506: 6939 ldr r1, [r7, #16]
8017508: f7ff f82a bl 8016560 <udp_sendto_if_src>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
pbuf_free(p_out);
801750c: 6938 ldr r0, [r7, #16]
801750e: f7f9 f873 bl 80105f8 <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
}
if (dhcp->tries < 255) {
8017512: 69bb ldr r3, [r7, #24]
8017514: 799b ldrb r3, [r3, #6]
8017516: 2bff cmp r3, #255 ; 0xff
8017518: d005 beq.n 8017526 <dhcp_discover+0xe2>
dhcp->tries++;
801751a: 69bb ldr r3, [r7, #24]
801751c: 799b ldrb r3, [r3, #6]
801751e: 3301 adds r3, #1
8017520: b2da uxtb r2, r3
8017522: 69bb ldr r3, [r7, #24]
8017524: 719a strb r2, [r3, #6]
if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
autoip_start(netif);
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
8017526: 69bb ldr r3, [r7, #24]
8017528: 799b ldrb r3, [r3, #6]
801752a: 2b05 cmp r3, #5
801752c: d80d bhi.n 801754a <dhcp_discover+0x106>
801752e: 69bb ldr r3, [r7, #24]
8017530: 799b ldrb r3, [r3, #6]
8017532: 461a mov r2, r3
8017534: 2301 movs r3, #1
8017536: 4093 lsls r3, r2
8017538: b29b uxth r3, r3
801753a: 461a mov r2, r3
801753c: 0152 lsls r2, r2, #5
801753e: 1ad2 subs r2, r2, r3
8017540: 0092 lsls r2, r2, #2
8017542: 4413 add r3, r2
8017544: 00db lsls r3, r3, #3
8017546: b29b uxth r3, r3
8017548: e001 b.n 801754e <dhcp_discover+0x10a>
801754a: f64e 2360 movw r3, #60000 ; 0xea60
801754e: 817b strh r3, [r7, #10]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017550: 897b ldrh r3, [r7, #10]
8017552: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017556: 4a0b ldr r2, [pc, #44] ; (8017584 <dhcp_discover+0x140>)
8017558: fb82 1203 smull r1, r2, r2, r3
801755c: 1152 asrs r2, r2, #5
801755e: 17db asrs r3, r3, #31
8017560: 1ad3 subs r3, r2, r3
8017562: b29a uxth r2, r3
8017564: 69bb ldr r3, [r7, #24]
8017566: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017568: f997 3017 ldrsb.w r3, [r7, #23]
}
801756c: 4618 mov r0, r3
801756e: 3720 adds r7, #32
8017570: 46bd mov sp, r7
8017572: bd80 pop {r7, pc}
8017574: 20000080 .word 0x20000080
8017578: 2000876c .word 0x2000876c
801757c: 08020e78 .word 0x08020e78
8017580: 08020e7c .word 0x08020e7c
8017584: 10624dd3 .word 0x10624dd3
08017588 <dhcp_bind>:
*
* @param netif network interface to bind to the offered address
*/
static void
dhcp_bind(struct netif *netif)
{
8017588: b580 push {r7, lr}
801758a: b088 sub sp, #32
801758c: af00 add r7, sp, #0
801758e: 6078 str r0, [r7, #4]
u32_t timeout;
struct dhcp *dhcp;
ip4_addr_t sn_mask, gw_addr;
LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
8017590: 687b ldr r3, [r7, #4]
8017592: 2b00 cmp r3, #0
8017594: d107 bne.n 80175a6 <dhcp_bind+0x1e>
8017596: 4b64 ldr r3, [pc, #400] ; (8017728 <dhcp_bind+0x1a0>)
8017598: f240 4215 movw r2, #1045 ; 0x415
801759c: 4963 ldr r1, [pc, #396] ; (801772c <dhcp_bind+0x1a4>)
801759e: 4864 ldr r0, [pc, #400] ; (8017730 <dhcp_bind+0x1a8>)
80175a0: f003 fd40 bl 801b024 <iprintf>
80175a4: e0bc b.n 8017720 <dhcp_bind+0x198>
dhcp = netif_dhcp_data(netif);
80175a6: 687b ldr r3, [r7, #4]
80175a8: 6a5b ldr r3, [r3, #36] ; 0x24
80175aa: 61bb str r3, [r7, #24]
LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
80175ac: 69bb ldr r3, [r7, #24]
80175ae: 2b00 cmp r3, #0
80175b0: d107 bne.n 80175c2 <dhcp_bind+0x3a>
80175b2: 4b5d ldr r3, [pc, #372] ; (8017728 <dhcp_bind+0x1a0>)
80175b4: f240 4217 movw r2, #1047 ; 0x417
80175b8: 495e ldr r1, [pc, #376] ; (8017734 <dhcp_bind+0x1ac>)
80175ba: 485d ldr r0, [pc, #372] ; (8017730 <dhcp_bind+0x1a8>)
80175bc: f003 fd32 bl 801b024 <iprintf>
80175c0: e0ae b.n 8017720 <dhcp_bind+0x198>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
/* reset time used of lease */
dhcp->lease_used = 0;
80175c2: 69bb ldr r3, [r7, #24]
80175c4: 2200 movs r2, #0
80175c6: 825a strh r2, [r3, #18]
if (dhcp->offered_t0_lease != 0xffffffffUL) {
80175c8: 69bb ldr r3, [r7, #24]
80175ca: 6a9b ldr r3, [r3, #40] ; 0x28
80175cc: f1b3 3fff cmp.w r3, #4294967295
80175d0: d019 beq.n 8017606 <dhcp_bind+0x7e>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
80175d2: 69bb ldr r3, [r7, #24]
80175d4: 6a9b ldr r3, [r3, #40] ; 0x28
80175d6: 331e adds r3, #30
80175d8: 4a57 ldr r2, [pc, #348] ; (8017738 <dhcp_bind+0x1b0>)
80175da: fba2 2303 umull r2, r3, r2, r3
80175de: 095b lsrs r3, r3, #5
80175e0: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
80175e2: 69fb ldr r3, [r7, #28]
80175e4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80175e8: d302 bcc.n 80175f0 <dhcp_bind+0x68>
timeout = 0xffff;
80175ea: f64f 73ff movw r3, #65535 ; 0xffff
80175ee: 61fb str r3, [r7, #28]
}
dhcp->t0_timeout = (u16_t)timeout;
80175f0: 69fb ldr r3, [r7, #28]
80175f2: b29a uxth r2, r3
80175f4: 69bb ldr r3, [r7, #24]
80175f6: 829a strh r2, [r3, #20]
if (dhcp->t0_timeout == 0) {
80175f8: 69bb ldr r3, [r7, #24]
80175fa: 8a9b ldrh r3, [r3, #20]
80175fc: 2b00 cmp r3, #0
80175fe: d102 bne.n 8017606 <dhcp_bind+0x7e>
dhcp->t0_timeout = 1;
8017600: 69bb ldr r3, [r7, #24]
8017602: 2201 movs r2, #1
8017604: 829a strh r2, [r3, #20]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000));
}
/* temporary DHCP lease? */
if (dhcp->offered_t1_renew != 0xffffffffUL) {
8017606: 69bb ldr r3, [r7, #24]
8017608: 6adb ldr r3, [r3, #44] ; 0x2c
801760a: f1b3 3fff cmp.w r3, #4294967295
801760e: d01d beq.n 801764c <dhcp_bind+0xc4>
/* set renewal period timer */
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
8017610: 69bb ldr r3, [r7, #24]
8017612: 6adb ldr r3, [r3, #44] ; 0x2c
8017614: 331e adds r3, #30
8017616: 4a48 ldr r2, [pc, #288] ; (8017738 <dhcp_bind+0x1b0>)
8017618: fba2 2303 umull r2, r3, r2, r3
801761c: 095b lsrs r3, r3, #5
801761e: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
8017620: 69fb ldr r3, [r7, #28]
8017622: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8017626: d302 bcc.n 801762e <dhcp_bind+0xa6>
timeout = 0xffff;
8017628: f64f 73ff movw r3, #65535 ; 0xffff
801762c: 61fb str r3, [r7, #28]
}
dhcp->t1_timeout = (u16_t)timeout;
801762e: 69fb ldr r3, [r7, #28]
8017630: b29a uxth r2, r3
8017632: 69bb ldr r3, [r7, #24]
8017634: 815a strh r2, [r3, #10]
if (dhcp->t1_timeout == 0) {
8017636: 69bb ldr r3, [r7, #24]
8017638: 895b ldrh r3, [r3, #10]
801763a: 2b00 cmp r3, #0
801763c: d102 bne.n 8017644 <dhcp_bind+0xbc>
dhcp->t1_timeout = 1;
801763e: 69bb ldr r3, [r7, #24]
8017640: 2201 movs r2, #1
8017642: 815a strh r2, [r3, #10]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000));
dhcp->t1_renew_time = dhcp->t1_timeout;
8017644: 69bb ldr r3, [r7, #24]
8017646: 895a ldrh r2, [r3, #10]
8017648: 69bb ldr r3, [r7, #24]
801764a: 81da strh r2, [r3, #14]
}
/* set renewal period timer */
if (dhcp->offered_t2_rebind != 0xffffffffUL) {
801764c: 69bb ldr r3, [r7, #24]
801764e: 6b1b ldr r3, [r3, #48] ; 0x30
8017650: f1b3 3fff cmp.w r3, #4294967295
8017654: d01d beq.n 8017692 <dhcp_bind+0x10a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
8017656: 69bb ldr r3, [r7, #24]
8017658: 6b1b ldr r3, [r3, #48] ; 0x30
801765a: 331e adds r3, #30
801765c: 4a36 ldr r2, [pc, #216] ; (8017738 <dhcp_bind+0x1b0>)
801765e: fba2 2303 umull r2, r3, r2, r3
8017662: 095b lsrs r3, r3, #5
8017664: 61fb str r3, [r7, #28]
if (timeout > 0xffff) {
8017666: 69fb ldr r3, [r7, #28]
8017668: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801766c: d302 bcc.n 8017674 <dhcp_bind+0xec>
timeout = 0xffff;
801766e: f64f 73ff movw r3, #65535 ; 0xffff
8017672: 61fb str r3, [r7, #28]
}
dhcp->t2_timeout = (u16_t)timeout;
8017674: 69fb ldr r3, [r7, #28]
8017676: b29a uxth r2, r3
8017678: 69bb ldr r3, [r7, #24]
801767a: 819a strh r2, [r3, #12]
if (dhcp->t2_timeout == 0) {
801767c: 69bb ldr r3, [r7, #24]
801767e: 899b ldrh r3, [r3, #12]
8017680: 2b00 cmp r3, #0
8017682: d102 bne.n 801768a <dhcp_bind+0x102>
dhcp->t2_timeout = 1;
8017684: 69bb ldr r3, [r7, #24]
8017686: 2201 movs r2, #1
8017688: 819a strh r2, [r3, #12]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000));
dhcp->t2_rebind_time = dhcp->t2_timeout;
801768a: 69bb ldr r3, [r7, #24]
801768c: 899a ldrh r2, [r3, #12]
801768e: 69bb ldr r3, [r7, #24]
8017690: 821a strh r2, [r3, #16]
}
/* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
8017692: 69bb ldr r3, [r7, #24]
8017694: 895a ldrh r2, [r3, #10]
8017696: 69bb ldr r3, [r7, #24]
8017698: 899b ldrh r3, [r3, #12]
801769a: 429a cmp r2, r3
801769c: d306 bcc.n 80176ac <dhcp_bind+0x124>
801769e: 69bb ldr r3, [r7, #24]
80176a0: 899b ldrh r3, [r3, #12]
80176a2: 2b00 cmp r3, #0
80176a4: d002 beq.n 80176ac <dhcp_bind+0x124>
dhcp->t1_timeout = 0;
80176a6: 69bb ldr r3, [r7, #24]
80176a8: 2200 movs r2, #0
80176aa: 815a strh r2, [r3, #10]
}
if (dhcp->subnet_mask_given) {
80176ac: 69bb ldr r3, [r7, #24]
80176ae: 79db ldrb r3, [r3, #7]
80176b0: 2b00 cmp r3, #0
80176b2: d003 beq.n 80176bc <dhcp_bind+0x134>
/* copy offered network mask */
ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
80176b4: 69bb ldr r3, [r7, #24]
80176b6: 6a1b ldr r3, [r3, #32]
80176b8: 613b str r3, [r7, #16]
80176ba: e014 b.n 80176e6 <dhcp_bind+0x15e>
} else {
/* subnet mask not given, choose a safe subnet mask given the network class */
u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
80176bc: 69bb ldr r3, [r7, #24]
80176be: 331c adds r3, #28
80176c0: 781b ldrb r3, [r3, #0]
80176c2: 75fb strb r3, [r7, #23]
if (first_octet <= 127) {
80176c4: f997 3017 ldrsb.w r3, [r7, #23]
80176c8: 2b00 cmp r3, #0
80176ca: db02 blt.n 80176d2 <dhcp_bind+0x14a>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
80176cc: 23ff movs r3, #255 ; 0xff
80176ce: 613b str r3, [r7, #16]
80176d0: e009 b.n 80176e6 <dhcp_bind+0x15e>
} else if (first_octet >= 192) {
80176d2: 7dfb ldrb r3, [r7, #23]
80176d4: 2bbf cmp r3, #191 ; 0xbf
80176d6: d903 bls.n 80176e0 <dhcp_bind+0x158>
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
80176d8: f06f 437f mvn.w r3, #4278190080 ; 0xff000000
80176dc: 613b str r3, [r7, #16]
80176de: e002 b.n 80176e6 <dhcp_bind+0x15e>
} else {
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
80176e0: f64f 73ff movw r3, #65535 ; 0xffff
80176e4: 613b str r3, [r7, #16]
}
}
ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
80176e6: 69bb ldr r3, [r7, #24]
80176e8: 6a5b ldr r3, [r3, #36] ; 0x24
80176ea: 60fb str r3, [r7, #12]
/* gateway address not given? */
if (ip4_addr_isany_val(gw_addr)) {
80176ec: 68fb ldr r3, [r7, #12]
80176ee: 2b00 cmp r3, #0
80176f0: d108 bne.n 8017704 <dhcp_bind+0x17c>
/* copy network address */
ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
80176f2: 69bb ldr r3, [r7, #24]
80176f4: 69da ldr r2, [r3, #28]
80176f6: 693b ldr r3, [r7, #16]
80176f8: 4013 ands r3, r2
80176fa: 60fb str r3, [r7, #12]
/* use first host address on network as gateway */
ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
80176fc: 68fb ldr r3, [r7, #12]
80176fe: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
8017702: 60fb str r3, [r7, #12]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
/* netif is now bound to DHCP leased address - set this before assigning the address
to ensure the callback can use dhcp_supplied_address() */
dhcp_set_state(dhcp, DHCP_STATE_BOUND);
8017704: 210a movs r1, #10
8017706: 69b8 ldr r0, [r7, #24]
8017708: f000 faa0 bl 8017c4c <dhcp_set_state>
netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
801770c: 69bb ldr r3, [r7, #24]
801770e: f103 011c add.w r1, r3, #28
8017712: f107 030c add.w r3, r7, #12
8017716: f107 0210 add.w r2, r7, #16
801771a: 6878 ldr r0, [r7, #4]
801771c: f7f8 fa62 bl 800fbe4 <netif_set_addr>
/* interface is used by routing now that an address is set */
}
8017720: 3720 adds r7, #32
8017722: 46bd mov sp, r7
8017724: bd80 pop {r7, pc}
8017726: bf00 nop
8017728: 0801e3a8 .word 0x0801e3a8
801772c: 0801e508 .word 0x0801e508
8017730: 0801e408 .word 0x0801e408
8017734: 0801e524 .word 0x0801e524
8017738: 88888889 .word 0x88888889
0801773c <dhcp_renew>:
*
* @param netif network interface which must renew its lease
*/
err_t
dhcp_renew(struct netif *netif)
{
801773c: b580 push {r7, lr}
801773e: b08a sub sp, #40 ; 0x28
8017740: af02 add r7, sp, #8
8017742: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017744: 687b ldr r3, [r7, #4]
8017746: 6a5b ldr r3, [r3, #36] ; 0x24
8017748: 61bb str r3, [r7, #24]
struct pbuf *p_out;
u16_t options_out_len;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
801774a: 2105 movs r1, #5
801774c: 69b8 ldr r0, [r7, #24]
801774e: f000 fa7d bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
8017752: f107 030c add.w r3, r7, #12
8017756: 2203 movs r2, #3
8017758: 69b9 ldr r1, [r7, #24]
801775a: 6878 ldr r0, [r7, #4]
801775c: f000 ff00 bl 8018560 <dhcp_create_msg>
8017760: 6178 str r0, [r7, #20]
if (p_out != NULL) {
8017762: 697b ldr r3, [r7, #20]
8017764: 2b00 cmp r3, #0
8017766: d04e beq.n 8017806 <dhcp_renew+0xca>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017768: 697b ldr r3, [r7, #20]
801776a: 685b ldr r3, [r3, #4]
801776c: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
801776e: 89b8 ldrh r0, [r7, #12]
8017770: 693b ldr r3, [r7, #16]
8017772: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017776: 2302 movs r3, #2
8017778: 2239 movs r2, #57 ; 0x39
801777a: f000 fa81 bl 8017c80 <dhcp_option>
801777e: 4603 mov r3, r0
8017780: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
8017782: 89b8 ldrh r0, [r7, #12]
8017784: 693b ldr r3, [r7, #16]
8017786: f103 01f0 add.w r1, r3, #240 ; 0xf0
801778a: 687b ldr r3, [r7, #4]
801778c: 8d1b ldrh r3, [r3, #40] ; 0x28
801778e: 461a mov r2, r3
8017790: f000 fad0 bl 8017d34 <dhcp_option_short>
8017794: 4603 mov r3, r0
8017796: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017798: 89b8 ldrh r0, [r7, #12]
801779a: 693b ldr r3, [r7, #16]
801779c: f103 01f0 add.w r1, r3, #240 ; 0xf0
80177a0: 2303 movs r3, #3
80177a2: 2237 movs r2, #55 ; 0x37
80177a4: f000 fa6c bl 8017c80 <dhcp_option>
80177a8: 4603 mov r3, r0
80177aa: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80177ac: 2300 movs r3, #0
80177ae: 77bb strb r3, [r7, #30]
80177b0: e00e b.n 80177d0 <dhcp_renew+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80177b2: 89b8 ldrh r0, [r7, #12]
80177b4: 693b ldr r3, [r7, #16]
80177b6: f103 01f0 add.w r1, r3, #240 ; 0xf0
80177ba: 7fbb ldrb r3, [r7, #30]
80177bc: 4a2a ldr r2, [pc, #168] ; (8017868 <dhcp_renew+0x12c>)
80177be: 5cd3 ldrb r3, [r2, r3]
80177c0: 461a mov r2, r3
80177c2: f000 fa91 bl 8017ce8 <dhcp_option_byte>
80177c6: 4603 mov r3, r0
80177c8: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80177ca: 7fbb ldrb r3, [r7, #30]
80177cc: 3301 adds r3, #1
80177ce: 77bb strb r3, [r7, #30]
80177d0: 7fbb ldrb r3, [r7, #30]
80177d2: 2b02 cmp r3, #2
80177d4: d9ed bls.n 80177b2 <dhcp_renew+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
80177d6: 89b8 ldrh r0, [r7, #12]
80177d8: 693b ldr r3, [r7, #16]
80177da: 33f0 adds r3, #240 ; 0xf0
80177dc: 697a ldr r2, [r7, #20]
80177de: 4619 mov r1, r3
80177e0: f000 ff94 bl 801870c <dhcp_option_trailer>
result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
80177e4: 4b21 ldr r3, [pc, #132] ; (801786c <dhcp_renew+0x130>)
80177e6: 6818 ldr r0, [r3, #0]
80177e8: 69bb ldr r3, [r7, #24]
80177ea: f103 0218 add.w r2, r3, #24
80177ee: 687b ldr r3, [r7, #4]
80177f0: 9300 str r3, [sp, #0]
80177f2: 2343 movs r3, #67 ; 0x43
80177f4: 6979 ldr r1, [r7, #20]
80177f6: f7fe fe3f bl 8016478 <udp_sendto_if>
80177fa: 4603 mov r3, r0
80177fc: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
80177fe: 6978 ldr r0, [r7, #20]
8017800: f7f8 fefa bl 80105f8 <pbuf_free>
8017804: e001 b.n 801780a <dhcp_renew+0xce>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
result = ERR_MEM;
8017806: 23ff movs r3, #255 ; 0xff
8017808: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
801780a: 69bb ldr r3, [r7, #24]
801780c: 799b ldrb r3, [r3, #6]
801780e: 2bff cmp r3, #255 ; 0xff
8017810: d005 beq.n 801781e <dhcp_renew+0xe2>
dhcp->tries++;
8017812: 69bb ldr r3, [r7, #24]
8017814: 799b ldrb r3, [r3, #6]
8017816: 3301 adds r3, #1
8017818: b2da uxtb r2, r3
801781a: 69bb ldr r3, [r7, #24]
801781c: 719a strb r2, [r3, #6]
}
/* back-off on retries, but to a maximum of 20 seconds */
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000);
801781e: 69bb ldr r3, [r7, #24]
8017820: 799b ldrb r3, [r3, #6]
8017822: 2b09 cmp r3, #9
8017824: d80a bhi.n 801783c <dhcp_renew+0x100>
8017826: 69bb ldr r3, [r7, #24]
8017828: 799b ldrb r3, [r3, #6]
801782a: b29b uxth r3, r3
801782c: 461a mov r2, r3
801782e: 0152 lsls r2, r2, #5
8017830: 1ad2 subs r2, r2, r3
8017832: 0092 lsls r2, r2, #2
8017834: 4413 add r3, r2
8017836: 011b lsls r3, r3, #4
8017838: b29b uxth r3, r3
801783a: e001 b.n 8017840 <dhcp_renew+0x104>
801783c: f644 6320 movw r3, #20000 ; 0x4e20
8017840: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017842: 89fb ldrh r3, [r7, #14]
8017844: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017848: 4a09 ldr r2, [pc, #36] ; (8017870 <dhcp_renew+0x134>)
801784a: fb82 1203 smull r1, r2, r2, r3
801784e: 1152 asrs r2, r2, #5
8017850: 17db asrs r3, r3, #31
8017852: 1ad3 subs r3, r2, r3
8017854: b29a uxth r2, r3
8017856: 69bb ldr r3, [r7, #24]
8017858: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
return result;
801785a: f997 301f ldrsb.w r3, [r7, #31]
}
801785e: 4618 mov r0, r3
8017860: 3720 adds r7, #32
8017862: 46bd mov sp, r7
8017864: bd80 pop {r7, pc}
8017866: bf00 nop
8017868: 20000080 .word 0x20000080
801786c: 2000876c .word 0x2000876c
8017870: 10624dd3 .word 0x10624dd3
08017874 <dhcp_rebind>:
*
* @param netif network interface which must rebind with a DHCP server
*/
static err_t
dhcp_rebind(struct netif *netif)
{
8017874: b580 push {r7, lr}
8017876: b08a sub sp, #40 ; 0x28
8017878: af02 add r7, sp, #8
801787a: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
801787c: 687b ldr r3, [r7, #4]
801787e: 6a5b ldr r3, [r3, #36] ; 0x24
8017880: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
8017882: 2104 movs r1, #4
8017884: 69b8 ldr r0, [r7, #24]
8017886: f000 f9e1 bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
801788a: f107 030c add.w r3, r7, #12
801788e: 2203 movs r2, #3
8017890: 69b9 ldr r1, [r7, #24]
8017892: 6878 ldr r0, [r7, #4]
8017894: f000 fe64 bl 8018560 <dhcp_create_msg>
8017898: 6178 str r0, [r7, #20]
if (p_out != NULL) {
801789a: 697b ldr r3, [r7, #20]
801789c: 2b00 cmp r3, #0
801789e: d04c beq.n 801793a <dhcp_rebind+0xc6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
80178a0: 697b ldr r3, [r7, #20]
80178a2: 685b ldr r3, [r3, #4]
80178a4: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
80178a6: 89b8 ldrh r0, [r7, #12]
80178a8: 693b ldr r3, [r7, #16]
80178aa: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178ae: 2302 movs r3, #2
80178b0: 2239 movs r2, #57 ; 0x39
80178b2: f000 f9e5 bl 8017c80 <dhcp_option>
80178b6: 4603 mov r3, r0
80178b8: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
80178ba: 89b8 ldrh r0, [r7, #12]
80178bc: 693b ldr r3, [r7, #16]
80178be: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178c2: 687b ldr r3, [r7, #4]
80178c4: 8d1b ldrh r3, [r3, #40] ; 0x28
80178c6: 461a mov r2, r3
80178c8: f000 fa34 bl 8017d34 <dhcp_option_short>
80178cc: 4603 mov r3, r0
80178ce: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
80178d0: 89b8 ldrh r0, [r7, #12]
80178d2: 693b ldr r3, [r7, #16]
80178d4: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178d8: 2303 movs r3, #3
80178da: 2237 movs r2, #55 ; 0x37
80178dc: f000 f9d0 bl 8017c80 <dhcp_option>
80178e0: 4603 mov r3, r0
80178e2: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
80178e4: 2300 movs r3, #0
80178e6: 77bb strb r3, [r7, #30]
80178e8: e00e b.n 8017908 <dhcp_rebind+0x94>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
80178ea: 89b8 ldrh r0, [r7, #12]
80178ec: 693b ldr r3, [r7, #16]
80178ee: f103 01f0 add.w r1, r3, #240 ; 0xf0
80178f2: 7fbb ldrb r3, [r7, #30]
80178f4: 4a29 ldr r2, [pc, #164] ; (801799c <dhcp_rebind+0x128>)
80178f6: 5cd3 ldrb r3, [r2, r3]
80178f8: 461a mov r2, r3
80178fa: f000 f9f5 bl 8017ce8 <dhcp_option_byte>
80178fe: 4603 mov r3, r0
8017900: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017902: 7fbb ldrb r3, [r7, #30]
8017904: 3301 adds r3, #1
8017906: 77bb strb r3, [r7, #30]
8017908: 7fbb ldrb r3, [r7, #30]
801790a: 2b02 cmp r3, #2
801790c: d9ed bls.n 80178ea <dhcp_rebind+0x76>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
801790e: 89b8 ldrh r0, [r7, #12]
8017910: 693b ldr r3, [r7, #16]
8017912: 33f0 adds r3, #240 ; 0xf0
8017914: 697a ldr r2, [r7, #20]
8017916: 4619 mov r1, r3
8017918: f000 fef8 bl 801870c <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
801791c: 4b20 ldr r3, [pc, #128] ; (80179a0 <dhcp_rebind+0x12c>)
801791e: 6818 ldr r0, [r3, #0]
8017920: 687b ldr r3, [r7, #4]
8017922: 9300 str r3, [sp, #0]
8017924: 2343 movs r3, #67 ; 0x43
8017926: 4a1f ldr r2, [pc, #124] ; (80179a4 <dhcp_rebind+0x130>)
8017928: 6979 ldr r1, [r7, #20]
801792a: f7fe fda5 bl 8016478 <udp_sendto_if>
801792e: 4603 mov r3, r0
8017930: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017932: 6978 ldr r0, [r7, #20]
8017934: f7f8 fe60 bl 80105f8 <pbuf_free>
8017938: e001 b.n 801793e <dhcp_rebind+0xca>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
result = ERR_MEM;
801793a: 23ff movs r3, #255 ; 0xff
801793c: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
801793e: 69bb ldr r3, [r7, #24]
8017940: 799b ldrb r3, [r3, #6]
8017942: 2bff cmp r3, #255 ; 0xff
8017944: d005 beq.n 8017952 <dhcp_rebind+0xde>
dhcp->tries++;
8017946: 69bb ldr r3, [r7, #24]
8017948: 799b ldrb r3, [r3, #6]
801794a: 3301 adds r3, #1
801794c: b2da uxtb r2, r3
801794e: 69bb ldr r3, [r7, #24]
8017950: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
8017952: 69bb ldr r3, [r7, #24]
8017954: 799b ldrb r3, [r3, #6]
8017956: 2b09 cmp r3, #9
8017958: d80a bhi.n 8017970 <dhcp_rebind+0xfc>
801795a: 69bb ldr r3, [r7, #24]
801795c: 799b ldrb r3, [r3, #6]
801795e: b29b uxth r3, r3
8017960: 461a mov r2, r3
8017962: 0152 lsls r2, r2, #5
8017964: 1ad2 subs r2, r2, r3
8017966: 0092 lsls r2, r2, #2
8017968: 4413 add r3, r2
801796a: 00db lsls r3, r3, #3
801796c: b29b uxth r3, r3
801796e: e001 b.n 8017974 <dhcp_rebind+0x100>
8017970: f242 7310 movw r3, #10000 ; 0x2710
8017974: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017976: 89fb ldrh r3, [r7, #14]
8017978: f203 13f3 addw r3, r3, #499 ; 0x1f3
801797c: 4a0a ldr r2, [pc, #40] ; (80179a8 <dhcp_rebind+0x134>)
801797e: fb82 1203 smull r1, r2, r2, r3
8017982: 1152 asrs r2, r2, #5
8017984: 17db asrs r3, r3, #31
8017986: 1ad3 subs r3, r2, r3
8017988: b29a uxth r2, r3
801798a: 69bb ldr r3, [r7, #24]
801798c: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
return result;
801798e: f997 301f ldrsb.w r3, [r7, #31]
}
8017992: 4618 mov r0, r3
8017994: 3720 adds r7, #32
8017996: 46bd mov sp, r7
8017998: bd80 pop {r7, pc}
801799a: bf00 nop
801799c: 20000080 .word 0x20000080
80179a0: 2000876c .word 0x2000876c
80179a4: 08020e7c .word 0x08020e7c
80179a8: 10624dd3 .word 0x10624dd3
080179ac <dhcp_reboot>:
*
* @param netif network interface which must reboot
*/
static err_t
dhcp_reboot(struct netif *netif)
{
80179ac: b5b0 push {r4, r5, r7, lr}
80179ae: b08a sub sp, #40 ; 0x28
80179b0: af02 add r7, sp, #8
80179b2: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
80179b4: 687b ldr r3, [r7, #4]
80179b6: 6a5b ldr r3, [r3, #36] ; 0x24
80179b8: 61bb str r3, [r7, #24]
u8_t i;
struct pbuf *p_out;
u16_t options_out_len;
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
80179ba: 2103 movs r1, #3
80179bc: 69b8 ldr r0, [r7, #24]
80179be: f000 f945 bl 8017c4c <dhcp_set_state>
/* create and initialize the DHCP message header */
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
80179c2: f107 030c add.w r3, r7, #12
80179c6: 2203 movs r2, #3
80179c8: 69b9 ldr r1, [r7, #24]
80179ca: 6878 ldr r0, [r7, #4]
80179cc: f000 fdc8 bl 8018560 <dhcp_create_msg>
80179d0: 6178 str r0, [r7, #20]
if (p_out != NULL) {
80179d2: 697b ldr r3, [r7, #20]
80179d4: 2b00 cmp r3, #0
80179d6: d066 beq.n 8017aa6 <dhcp_reboot+0xfa>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
80179d8: 697b ldr r3, [r7, #20]
80179da: 685b ldr r3, [r3, #4]
80179dc: 613b str r3, [r7, #16]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
80179de: 89b8 ldrh r0, [r7, #12]
80179e0: 693b ldr r3, [r7, #16]
80179e2: f103 01f0 add.w r1, r3, #240 ; 0xf0
80179e6: 2302 movs r3, #2
80179e8: 2239 movs r2, #57 ; 0x39
80179ea: f000 f949 bl 8017c80 <dhcp_option>
80179ee: 4603 mov r3, r0
80179f0: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED);
80179f2: 89b8 ldrh r0, [r7, #12]
80179f4: 693b ldr r3, [r7, #16]
80179f6: 33f0 adds r3, #240 ; 0xf0
80179f8: f44f 7210 mov.w r2, #576 ; 0x240
80179fc: 4619 mov r1, r3
80179fe: f000 f999 bl 8017d34 <dhcp_option_short>
8017a02: 4603 mov r3, r0
8017a04: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
8017a06: 89b8 ldrh r0, [r7, #12]
8017a08: 693b ldr r3, [r7, #16]
8017a0a: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017a0e: 2304 movs r3, #4
8017a10: 2232 movs r2, #50 ; 0x32
8017a12: f000 f935 bl 8017c80 <dhcp_option>
8017a16: 4603 mov r3, r0
8017a18: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
8017a1a: 89bc ldrh r4, [r7, #12]
8017a1c: 693b ldr r3, [r7, #16]
8017a1e: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017a22: 69bb ldr r3, [r7, #24]
8017a24: 69db ldr r3, [r3, #28]
8017a26: 4618 mov r0, r3
8017a28: f7f7 fa47 bl 800eeba <lwip_htonl>
8017a2c: 4603 mov r3, r0
8017a2e: 461a mov r2, r3
8017a30: 4629 mov r1, r5
8017a32: 4620 mov r0, r4
8017a34: f000 f9b0 bl 8017d98 <dhcp_option_long>
8017a38: 4603 mov r3, r0
8017a3a: 81bb strh r3, [r7, #12]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
8017a3c: 89b8 ldrh r0, [r7, #12]
8017a3e: 693b ldr r3, [r7, #16]
8017a40: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017a44: 2303 movs r3, #3
8017a46: 2237 movs r2, #55 ; 0x37
8017a48: f000 f91a bl 8017c80 <dhcp_option>
8017a4c: 4603 mov r3, r0
8017a4e: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017a50: 2300 movs r3, #0
8017a52: 77bb strb r3, [r7, #30]
8017a54: e00e b.n 8017a74 <dhcp_reboot+0xc8>
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
8017a56: 89b8 ldrh r0, [r7, #12]
8017a58: 693b ldr r3, [r7, #16]
8017a5a: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017a5e: 7fbb ldrb r3, [r7, #30]
8017a60: 4a29 ldr r2, [pc, #164] ; (8017b08 <dhcp_reboot+0x15c>)
8017a62: 5cd3 ldrb r3, [r2, r3]
8017a64: 461a mov r2, r3
8017a66: f000 f93f bl 8017ce8 <dhcp_option_byte>
8017a6a: 4603 mov r3, r0
8017a6c: 81bb strh r3, [r7, #12]
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
8017a6e: 7fbb ldrb r3, [r7, #30]
8017a70: 3301 adds r3, #1
8017a72: 77bb strb r3, [r7, #30]
8017a74: 7fbb ldrb r3, [r7, #30]
8017a76: 2b02 cmp r3, #2
8017a78: d9ed bls.n 8017a56 <dhcp_reboot+0xaa>
#if LWIP_NETIF_HOSTNAME
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
#endif /* LWIP_NETIF_HOSTNAME */
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017a7a: 89b8 ldrh r0, [r7, #12]
8017a7c: 693b ldr r3, [r7, #16]
8017a7e: 33f0 adds r3, #240 ; 0xf0
8017a80: 697a ldr r2, [r7, #20]
8017a82: 4619 mov r1, r3
8017a84: f000 fe42 bl 801870c <dhcp_option_trailer>
/* broadcast to server */
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017a88: 4b20 ldr r3, [pc, #128] ; (8017b0c <dhcp_reboot+0x160>)
8017a8a: 6818 ldr r0, [r3, #0]
8017a8c: 687b ldr r3, [r7, #4]
8017a8e: 9300 str r3, [sp, #0]
8017a90: 2343 movs r3, #67 ; 0x43
8017a92: 4a1f ldr r2, [pc, #124] ; (8017b10 <dhcp_reboot+0x164>)
8017a94: 6979 ldr r1, [r7, #20]
8017a96: f7fe fcef bl 8016478 <udp_sendto_if>
8017a9a: 4603 mov r3, r0
8017a9c: 77fb strb r3, [r7, #31]
pbuf_free(p_out);
8017a9e: 6978 ldr r0, [r7, #20]
8017aa0: f7f8 fdaa bl 80105f8 <pbuf_free>
8017aa4: e001 b.n 8017aaa <dhcp_reboot+0xfe>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
result = ERR_MEM;
8017aa6: 23ff movs r3, #255 ; 0xff
8017aa8: 77fb strb r3, [r7, #31]
}
if (dhcp->tries < 255) {
8017aaa: 69bb ldr r3, [r7, #24]
8017aac: 799b ldrb r3, [r3, #6]
8017aae: 2bff cmp r3, #255 ; 0xff
8017ab0: d005 beq.n 8017abe <dhcp_reboot+0x112>
dhcp->tries++;
8017ab2: 69bb ldr r3, [r7, #24]
8017ab4: 799b ldrb r3, [r3, #6]
8017ab6: 3301 adds r3, #1
8017ab8: b2da uxtb r2, r3
8017aba: 69bb ldr r3, [r7, #24]
8017abc: 719a strb r2, [r3, #6]
}
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
8017abe: 69bb ldr r3, [r7, #24]
8017ac0: 799b ldrb r3, [r3, #6]
8017ac2: 2b09 cmp r3, #9
8017ac4: d80a bhi.n 8017adc <dhcp_reboot+0x130>
8017ac6: 69bb ldr r3, [r7, #24]
8017ac8: 799b ldrb r3, [r3, #6]
8017aca: b29b uxth r3, r3
8017acc: 461a mov r2, r3
8017ace: 0152 lsls r2, r2, #5
8017ad0: 1ad2 subs r2, r2, r3
8017ad2: 0092 lsls r2, r2, #2
8017ad4: 4413 add r3, r2
8017ad6: 00db lsls r3, r3, #3
8017ad8: b29b uxth r3, r3
8017ada: e001 b.n 8017ae0 <dhcp_reboot+0x134>
8017adc: f242 7310 movw r3, #10000 ; 0x2710
8017ae0: 81fb strh r3, [r7, #14]
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
8017ae2: 89fb ldrh r3, [r7, #14]
8017ae4: f203 13f3 addw r3, r3, #499 ; 0x1f3
8017ae8: 4a0a ldr r2, [pc, #40] ; (8017b14 <dhcp_reboot+0x168>)
8017aea: fb82 1203 smull r1, r2, r2, r3
8017aee: 1152 asrs r2, r2, #5
8017af0: 17db asrs r3, r3, #31
8017af2: 1ad3 subs r3, r2, r3
8017af4: b29a uxth r2, r3
8017af6: 69bb ldr r3, [r7, #24]
8017af8: 811a strh r2, [r3, #8]
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
return result;
8017afa: f997 301f ldrsb.w r3, [r7, #31]
}
8017afe: 4618 mov r0, r3
8017b00: 3720 adds r7, #32
8017b02: 46bd mov sp, r7
8017b04: bdb0 pop {r4, r5, r7, pc}
8017b06: bf00 nop
8017b08: 20000080 .word 0x20000080
8017b0c: 2000876c .word 0x2000876c
8017b10: 08020e7c .word 0x08020e7c
8017b14: 10624dd3 .word 0x10624dd3
08017b18 <dhcp_release_and_stop>:
*
* @param netif network interface
*/
void
dhcp_release_and_stop(struct netif *netif)
{
8017b18: b5b0 push {r4, r5, r7, lr}
8017b1a: b08a sub sp, #40 ; 0x28
8017b1c: af02 add r7, sp, #8
8017b1e: 6078 str r0, [r7, #4]
struct dhcp *dhcp = netif_dhcp_data(netif);
8017b20: 687b ldr r3, [r7, #4]
8017b22: 6a5b ldr r3, [r3, #36] ; 0x24
8017b24: 61fb str r3, [r7, #28]
ip_addr_t server_ip_addr;
LWIP_ASSERT_CORE_LOCKED();
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n"));
if (dhcp == NULL) {
8017b26: 69fb ldr r3, [r7, #28]
8017b28: 2b00 cmp r3, #0
8017b2a: f000 8084 beq.w 8017c36 <dhcp_release_and_stop+0x11e>
return;
}
/* already off? -> nothing to do */
if (dhcp->state == DHCP_STATE_OFF) {
8017b2e: 69fb ldr r3, [r7, #28]
8017b30: 795b ldrb r3, [r3, #5]
8017b32: 2b00 cmp r3, #0
8017b34: f000 8081 beq.w 8017c3a <dhcp_release_and_stop+0x122>
return;
}
ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
8017b38: 69fb ldr r3, [r7, #28]
8017b3a: 699b ldr r3, [r3, #24]
8017b3c: 613b str r3, [r7, #16]
/* clean old DHCP offer */
ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
8017b3e: 69fb ldr r3, [r7, #28]
8017b40: 2200 movs r2, #0
8017b42: 619a str r2, [r3, #24]
ip4_addr_set_zero(&dhcp->offered_ip_addr);
8017b44: 69fb ldr r3, [r7, #28]
8017b46: 2200 movs r2, #0
8017b48: 61da str r2, [r3, #28]
ip4_addr_set_zero(&dhcp->offered_sn_mask);
8017b4a: 69fb ldr r3, [r7, #28]
8017b4c: 2200 movs r2, #0
8017b4e: 621a str r2, [r3, #32]
ip4_addr_set_zero(&dhcp->offered_gw_addr);
8017b50: 69fb ldr r3, [r7, #28]
8017b52: 2200 movs r2, #0
8017b54: 625a str r2, [r3, #36] ; 0x24
#if LWIP_DHCP_BOOTP_FILE
ip4_addr_set_zero(&dhcp->offered_si_addr);
#endif /* LWIP_DHCP_BOOTP_FILE */
dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
8017b56: 69fb ldr r3, [r7, #28]
8017b58: 2200 movs r2, #0
8017b5a: 631a str r2, [r3, #48] ; 0x30
8017b5c: 69fb ldr r3, [r7, #28]
8017b5e: 6b1a ldr r2, [r3, #48] ; 0x30
8017b60: 69fb ldr r3, [r7, #28]
8017b62: 62da str r2, [r3, #44] ; 0x2c
8017b64: 69fb ldr r3, [r7, #28]
8017b66: 6ada ldr r2, [r3, #44] ; 0x2c
8017b68: 69fb ldr r3, [r7, #28]
8017b6a: 629a str r2, [r3, #40] ; 0x28
dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
8017b6c: 69fb ldr r3, [r7, #28]
8017b6e: 2200 movs r2, #0
8017b70: 829a strh r2, [r3, #20]
8017b72: 69fb ldr r3, [r7, #28]
8017b74: 8a9a ldrh r2, [r3, #20]
8017b76: 69fb ldr r3, [r7, #28]
8017b78: 825a strh r2, [r3, #18]
8017b7a: 69fb ldr r3, [r7, #28]
8017b7c: 8a5a ldrh r2, [r3, #18]
8017b7e: 69fb ldr r3, [r7, #28]
8017b80: 821a strh r2, [r3, #16]
8017b82: 69fb ldr r3, [r7, #28]
8017b84: 8a1a ldrh r2, [r3, #16]
8017b86: 69fb ldr r3, [r7, #28]
8017b88: 81da strh r2, [r3, #14]
/* send release message when current IP was assigned via DHCP */
if (dhcp_supplied_address(netif)) {
8017b8a: 6878 ldr r0, [r7, #4]
8017b8c: f000 fdec bl 8018768 <dhcp_supplied_address>
8017b90: 4603 mov r3, r0
8017b92: 2b00 cmp r3, #0
8017b94: d03b beq.n 8017c0e <dhcp_release_and_stop+0xf6>
/* create and initialize the DHCP message header */
struct pbuf *p_out;
u16_t options_out_len;
p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len);
8017b96: f107 030e add.w r3, r7, #14
8017b9a: 2207 movs r2, #7
8017b9c: 69f9 ldr r1, [r7, #28]
8017b9e: 6878 ldr r0, [r7, #4]
8017ba0: f000 fcde bl 8018560 <dhcp_create_msg>
8017ba4: 61b8 str r0, [r7, #24]
if (p_out != NULL) {
8017ba6: 69bb ldr r3, [r7, #24]
8017ba8: 2b00 cmp r3, #0
8017baa: d030 beq.n 8017c0e <dhcp_release_and_stop+0xf6>
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
8017bac: 69bb ldr r3, [r7, #24]
8017bae: 685b ldr r3, [r3, #4]
8017bb0: 617b str r3, [r7, #20]
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
8017bb2: 89f8 ldrh r0, [r7, #14]
8017bb4: 697b ldr r3, [r7, #20]
8017bb6: f103 01f0 add.w r1, r3, #240 ; 0xf0
8017bba: 2304 movs r3, #4
8017bbc: 2236 movs r2, #54 ; 0x36
8017bbe: f000 f85f bl 8017c80 <dhcp_option>
8017bc2: 4603 mov r3, r0
8017bc4: 81fb strh r3, [r7, #14]
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
8017bc6: 89fc ldrh r4, [r7, #14]
8017bc8: 697b ldr r3, [r7, #20]
8017bca: f103 05f0 add.w r5, r3, #240 ; 0xf0
8017bce: 693b ldr r3, [r7, #16]
8017bd0: 4618 mov r0, r3
8017bd2: f7f7 f972 bl 800eeba <lwip_htonl>
8017bd6: 4603 mov r3, r0
8017bd8: 461a mov r2, r3
8017bda: 4629 mov r1, r5
8017bdc: 4620 mov r0, r4
8017bde: f000 f8db bl 8017d98 <dhcp_option_long>
8017be2: 4603 mov r3, r0
8017be4: 81fb strh r3, [r7, #14]
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len);
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
8017be6: 89f8 ldrh r0, [r7, #14]
8017be8: 697b ldr r3, [r7, #20]
8017bea: 33f0 adds r3, #240 ; 0xf0
8017bec: 69ba ldr r2, [r7, #24]
8017bee: 4619 mov r1, r3
8017bf0: f000 fd8c bl 801870c <dhcp_option_trailer>
udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
8017bf4: 4b13 ldr r3, [pc, #76] ; (8017c44 <dhcp_release_and_stop+0x12c>)
8017bf6: 6818 ldr r0, [r3, #0]
8017bf8: f107 0210 add.w r2, r7, #16
8017bfc: 687b ldr r3, [r7, #4]
8017bfe: 9300 str r3, [sp, #0]
8017c00: 2343 movs r3, #67 ; 0x43
8017c02: 69b9 ldr r1, [r7, #24]
8017c04: f7fe fc38 bl 8016478 <udp_sendto_if>
pbuf_free(p_out);
8017c08: 69b8 ldr r0, [r7, #24]
8017c0a: f7f8 fcf5 bl 80105f8 <pbuf_free>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
}
}
/* remove IP address from interface (prevents routing from selecting this interface) */
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
8017c0e: 4b0e ldr r3, [pc, #56] ; (8017c48 <dhcp_release_and_stop+0x130>)
8017c10: 4a0d ldr r2, [pc, #52] ; (8017c48 <dhcp_release_and_stop+0x130>)
8017c12: 490d ldr r1, [pc, #52] ; (8017c48 <dhcp_release_and_stop+0x130>)
8017c14: 6878 ldr r0, [r7, #4]
8017c16: f7f7 ffe5 bl 800fbe4 <netif_set_addr>
autoip_stop(netif);
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
}
#endif /* LWIP_DHCP_AUTOIP_COOP */
dhcp_set_state(dhcp, DHCP_STATE_OFF);
8017c1a: 2100 movs r1, #0
8017c1c: 69f8 ldr r0, [r7, #28]
8017c1e: f000 f815 bl 8017c4c <dhcp_set_state>
if (dhcp->pcb_allocated != 0) {
8017c22: 69fb ldr r3, [r7, #28]
8017c24: 791b ldrb r3, [r3, #4]
8017c26: 2b00 cmp r3, #0
8017c28: d008 beq.n 8017c3c <dhcp_release_and_stop+0x124>
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
8017c2a: f7fe ff71 bl 8016b10 <dhcp_dec_pcb_refcount>
dhcp->pcb_allocated = 0;
8017c2e: 69fb ldr r3, [r7, #28]
8017c30: 2200 movs r2, #0
8017c32: 711a strb r2, [r3, #4]
8017c34: e002 b.n 8017c3c <dhcp_release_and_stop+0x124>
return;
8017c36: bf00 nop
8017c38: e000 b.n 8017c3c <dhcp_release_and_stop+0x124>
return;
8017c3a: bf00 nop
}
}
8017c3c: 3720 adds r7, #32
8017c3e: 46bd mov sp, r7
8017c40: bdb0 pop {r4, r5, r7, pc}
8017c42: bf00 nop
8017c44: 2000876c .word 0x2000876c
8017c48: 08020e78 .word 0x08020e78
08017c4c <dhcp_set_state>:
*
* If the state changed, reset the number of tries.
*/
static void
dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
{
8017c4c: b480 push {r7}
8017c4e: b083 sub sp, #12
8017c50: af00 add r7, sp, #0
8017c52: 6078 str r0, [r7, #4]
8017c54: 460b mov r3, r1
8017c56: 70fb strb r3, [r7, #3]
if (new_state != dhcp->state) {
8017c58: 687b ldr r3, [r7, #4]
8017c5a: 795b ldrb r3, [r3, #5]
8017c5c: 78fa ldrb r2, [r7, #3]
8017c5e: 429a cmp r2, r3
8017c60: d008 beq.n 8017c74 <dhcp_set_state+0x28>
dhcp->state = new_state;
8017c62: 687b ldr r3, [r7, #4]
8017c64: 78fa ldrb r2, [r7, #3]
8017c66: 715a strb r2, [r3, #5]
dhcp->tries = 0;
8017c68: 687b ldr r3, [r7, #4]
8017c6a: 2200 movs r2, #0
8017c6c: 719a strb r2, [r3, #6]
dhcp->request_timeout = 0;
8017c6e: 687b ldr r3, [r7, #4]
8017c70: 2200 movs r2, #0
8017c72: 811a strh r2, [r3, #8]
}
}
8017c74: bf00 nop
8017c76: 370c adds r7, #12
8017c78: 46bd mov sp, r7
8017c7a: f85d 7b04 ldr.w r7, [sp], #4
8017c7e: 4770 bx lr
08017c80 <dhcp_option>:
* DHCP message.
*
*/
static u16_t
dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len)
{
8017c80: b580 push {r7, lr}
8017c82: b082 sub sp, #8
8017c84: af00 add r7, sp, #0
8017c86: 6039 str r1, [r7, #0]
8017c88: 4611 mov r1, r2
8017c8a: 461a mov r2, r3
8017c8c: 4603 mov r3, r0
8017c8e: 80fb strh r3, [r7, #6]
8017c90: 460b mov r3, r1
8017c92: 717b strb r3, [r7, #5]
8017c94: 4613 mov r3, r2
8017c96: 713b strb r3, [r7, #4]
LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
8017c98: 88fa ldrh r2, [r7, #6]
8017c9a: 793b ldrb r3, [r7, #4]
8017c9c: 4413 add r3, r2
8017c9e: 3302 adds r3, #2
8017ca0: 2b44 cmp r3, #68 ; 0x44
8017ca2: d906 bls.n 8017cb2 <dhcp_option+0x32>
8017ca4: 4b0d ldr r3, [pc, #52] ; (8017cdc <dhcp_option+0x5c>)
8017ca6: f240 529a movw r2, #1434 ; 0x59a
8017caa: 490d ldr r1, [pc, #52] ; (8017ce0 <dhcp_option+0x60>)
8017cac: 480d ldr r0, [pc, #52] ; (8017ce4 <dhcp_option+0x64>)
8017cae: f003 f9b9 bl 801b024 <iprintf>
options[options_out_len++] = option_type;
8017cb2: 88fb ldrh r3, [r7, #6]
8017cb4: 1c5a adds r2, r3, #1
8017cb6: 80fa strh r2, [r7, #6]
8017cb8: 461a mov r2, r3
8017cba: 683b ldr r3, [r7, #0]
8017cbc: 4413 add r3, r2
8017cbe: 797a ldrb r2, [r7, #5]
8017cc0: 701a strb r2, [r3, #0]
options[options_out_len++] = option_len;
8017cc2: 88fb ldrh r3, [r7, #6]
8017cc4: 1c5a adds r2, r3, #1
8017cc6: 80fa strh r2, [r7, #6]
8017cc8: 461a mov r2, r3
8017cca: 683b ldr r3, [r7, #0]
8017ccc: 4413 add r3, r2
8017cce: 793a ldrb r2, [r7, #4]
8017cd0: 701a strb r2, [r3, #0]
return options_out_len;
8017cd2: 88fb ldrh r3, [r7, #6]
}
8017cd4: 4618 mov r0, r3
8017cd6: 3708 adds r7, #8
8017cd8: 46bd mov sp, r7
8017cda: bd80 pop {r7, pc}
8017cdc: 0801e3a8 .word 0x0801e3a8
8017ce0: 0801e53c .word 0x0801e53c
8017ce4: 0801e408 .word 0x0801e408
08017ce8 <dhcp_option_byte>:
* Concatenate a single byte to the outgoing DHCP message.
*
*/
static u16_t
dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value)
{
8017ce8: b580 push {r7, lr}
8017cea: b082 sub sp, #8
8017cec: af00 add r7, sp, #0
8017cee: 4603 mov r3, r0
8017cf0: 6039 str r1, [r7, #0]
8017cf2: 80fb strh r3, [r7, #6]
8017cf4: 4613 mov r3, r2
8017cf6: 717b strb r3, [r7, #5]
LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN);
8017cf8: 88fb ldrh r3, [r7, #6]
8017cfa: 2b43 cmp r3, #67 ; 0x43
8017cfc: d906 bls.n 8017d0c <dhcp_option_byte+0x24>
8017cfe: 4b0a ldr r3, [pc, #40] ; (8017d28 <dhcp_option_byte+0x40>)
8017d00: f240 52a6 movw r2, #1446 ; 0x5a6
8017d04: 4909 ldr r1, [pc, #36] ; (8017d2c <dhcp_option_byte+0x44>)
8017d06: 480a ldr r0, [pc, #40] ; (8017d30 <dhcp_option_byte+0x48>)
8017d08: f003 f98c bl 801b024 <iprintf>
options[options_out_len++] = value;
8017d0c: 88fb ldrh r3, [r7, #6]
8017d0e: 1c5a adds r2, r3, #1
8017d10: 80fa strh r2, [r7, #6]
8017d12: 461a mov r2, r3
8017d14: 683b ldr r3, [r7, #0]
8017d16: 4413 add r3, r2
8017d18: 797a ldrb r2, [r7, #5]
8017d1a: 701a strb r2, [r3, #0]
return options_out_len;
8017d1c: 88fb ldrh r3, [r7, #6]
}
8017d1e: 4618 mov r0, r3
8017d20: 3708 adds r7, #8
8017d22: 46bd mov sp, r7
8017d24: bd80 pop {r7, pc}
8017d26: bf00 nop
8017d28: 0801e3a8 .word 0x0801e3a8
8017d2c: 0801e580 .word 0x0801e580
8017d30: 0801e408 .word 0x0801e408
08017d34 <dhcp_option_short>:
static u16_t
dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value)
{
8017d34: b580 push {r7, lr}
8017d36: b082 sub sp, #8
8017d38: af00 add r7, sp, #0
8017d3a: 4603 mov r3, r0
8017d3c: 6039 str r1, [r7, #0]
8017d3e: 80fb strh r3, [r7, #6]
8017d40: 4613 mov r3, r2
8017d42: 80bb strh r3, [r7, #4]
LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN);
8017d44: 88fb ldrh r3, [r7, #6]
8017d46: 3302 adds r3, #2
8017d48: 2b44 cmp r3, #68 ; 0x44
8017d4a: d906 bls.n 8017d5a <dhcp_option_short+0x26>
8017d4c: 4b0f ldr r3, [pc, #60] ; (8017d8c <dhcp_option_short+0x58>)
8017d4e: f240 52ae movw r2, #1454 ; 0x5ae
8017d52: 490f ldr r1, [pc, #60] ; (8017d90 <dhcp_option_short+0x5c>)
8017d54: 480f ldr r0, [pc, #60] ; (8017d94 <dhcp_option_short+0x60>)
8017d56: f003 f965 bl 801b024 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
8017d5a: 88bb ldrh r3, [r7, #4]
8017d5c: 0a1b lsrs r3, r3, #8
8017d5e: b29a uxth r2, r3
8017d60: 88fb ldrh r3, [r7, #6]
8017d62: 1c59 adds r1, r3, #1
8017d64: 80f9 strh r1, [r7, #6]
8017d66: 4619 mov r1, r3
8017d68: 683b ldr r3, [r7, #0]
8017d6a: 440b add r3, r1
8017d6c: b2d2 uxtb r2, r2
8017d6e: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t) (value & 0x00ffU);
8017d70: 88fb ldrh r3, [r7, #6]
8017d72: 1c5a adds r2, r3, #1
8017d74: 80fa strh r2, [r7, #6]
8017d76: 461a mov r2, r3
8017d78: 683b ldr r3, [r7, #0]
8017d7a: 4413 add r3, r2
8017d7c: 88ba ldrh r2, [r7, #4]
8017d7e: b2d2 uxtb r2, r2
8017d80: 701a strb r2, [r3, #0]
return options_out_len;
8017d82: 88fb ldrh r3, [r7, #6]
}
8017d84: 4618 mov r0, r3
8017d86: 3708 adds r7, #8
8017d88: 46bd mov sp, r7
8017d8a: bd80 pop {r7, pc}
8017d8c: 0801e3a8 .word 0x0801e3a8
8017d90: 0801e5b8 .word 0x0801e5b8
8017d94: 0801e408 .word 0x0801e408
08017d98 <dhcp_option_long>:
static u16_t
dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value)
{
8017d98: b580 push {r7, lr}
8017d9a: b084 sub sp, #16
8017d9c: af00 add r7, sp, #0
8017d9e: 4603 mov r3, r0
8017da0: 60b9 str r1, [r7, #8]
8017da2: 607a str r2, [r7, #4]
8017da4: 81fb strh r3, [r7, #14]
LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN);
8017da6: 89fb ldrh r3, [r7, #14]
8017da8: 3304 adds r3, #4
8017daa: 2b44 cmp r3, #68 ; 0x44
8017dac: d906 bls.n 8017dbc <dhcp_option_long+0x24>
8017dae: 4b19 ldr r3, [pc, #100] ; (8017e14 <dhcp_option_long+0x7c>)
8017db0: f240 52b7 movw r2, #1463 ; 0x5b7
8017db4: 4918 ldr r1, [pc, #96] ; (8017e18 <dhcp_option_long+0x80>)
8017db6: 4819 ldr r0, [pc, #100] ; (8017e1c <dhcp_option_long+0x84>)
8017db8: f003 f934 bl 801b024 <iprintf>
options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
8017dbc: 687b ldr r3, [r7, #4]
8017dbe: 0e1a lsrs r2, r3, #24
8017dc0: 89fb ldrh r3, [r7, #14]
8017dc2: 1c59 adds r1, r3, #1
8017dc4: 81f9 strh r1, [r7, #14]
8017dc6: 4619 mov r1, r3
8017dc8: 68bb ldr r3, [r7, #8]
8017dca: 440b add r3, r1
8017dcc: b2d2 uxtb r2, r2
8017dce: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
8017dd0: 687b ldr r3, [r7, #4]
8017dd2: 0c1a lsrs r2, r3, #16
8017dd4: 89fb ldrh r3, [r7, #14]
8017dd6: 1c59 adds r1, r3, #1
8017dd8: 81f9 strh r1, [r7, #14]
8017dda: 4619 mov r1, r3
8017ddc: 68bb ldr r3, [r7, #8]
8017dde: 440b add r3, r1
8017de0: b2d2 uxtb r2, r2
8017de2: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
8017de4: 687b ldr r3, [r7, #4]
8017de6: 0a1a lsrs r2, r3, #8
8017de8: 89fb ldrh r3, [r7, #14]
8017dea: 1c59 adds r1, r3, #1
8017dec: 81f9 strh r1, [r7, #14]
8017dee: 4619 mov r1, r3
8017df0: 68bb ldr r3, [r7, #8]
8017df2: 440b add r3, r1
8017df4: b2d2 uxtb r2, r2
8017df6: 701a strb r2, [r3, #0]
options[options_out_len++] = (u8_t)((value & 0x000000ffUL));
8017df8: 89fb ldrh r3, [r7, #14]
8017dfa: 1c5a adds r2, r3, #1
8017dfc: 81fa strh r2, [r7, #14]
8017dfe: 461a mov r2, r3
8017e00: 68bb ldr r3, [r7, #8]
8017e02: 4413 add r3, r2
8017e04: 687a ldr r2, [r7, #4]
8017e06: b2d2 uxtb r2, r2
8017e08: 701a strb r2, [r3, #0]
return options_out_len;
8017e0a: 89fb ldrh r3, [r7, #14]
}
8017e0c: 4618 mov r0, r3
8017e0e: 3710 adds r7, #16
8017e10: 46bd mov sp, r7
8017e12: bd80 pop {r7, pc}
8017e14: 0801e3a8 .word 0x0801e3a8
8017e18: 0801e5f4 .word 0x0801e5f4
8017e1c: 0801e408 .word 0x0801e408
08017e20 <dhcp_parse_reply>:
* use that further on.
*
*/
static err_t
dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp)
{
8017e20: b580 push {r7, lr}
8017e22: b090 sub sp, #64 ; 0x40
8017e24: af00 add r7, sp, #0
8017e26: 6078 str r0, [r7, #4]
8017e28: 6039 str r1, [r7, #0]
u16_t offset;
u16_t offset_max;
u16_t options_idx;
u16_t options_idx_max;
struct pbuf *q;
int parse_file_as_options = 0;
8017e2a: 2300 movs r3, #0
8017e2c: 62fb str r3, [r7, #44] ; 0x2c
int parse_sname_as_options = 0;
8017e2e: 2300 movs r3, #0
8017e30: 62bb str r3, [r7, #40] ; 0x28
#endif
LWIP_UNUSED_ARG(dhcp);
/* clear received options */
dhcp_clear_all_options(dhcp);
8017e32: 2208 movs r2, #8
8017e34: 2100 movs r1, #0
8017e36: 48be ldr r0, [pc, #760] ; (8018130 <dhcp_parse_reply+0x310>)
8017e38: f003 f8ec bl 801b014 <memset>
/* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
if (p->len < DHCP_SNAME_OFS) {
8017e3c: 687b ldr r3, [r7, #4]
8017e3e: 895b ldrh r3, [r3, #10]
8017e40: 2b2b cmp r3, #43 ; 0x2b
8017e42: d802 bhi.n 8017e4a <dhcp_parse_reply+0x2a>
return ERR_BUF;
8017e44: f06f 0301 mvn.w r3, #1
8017e48: e2a8 b.n 801839c <dhcp_parse_reply+0x57c>
}
msg_in = (struct dhcp_msg *)p->payload;
8017e4a: 687b ldr r3, [r7, #4]
8017e4c: 685b ldr r3, [r3, #4]
8017e4e: 61bb str r3, [r7, #24]
#endif /* LWIP_DHCP_BOOTP_FILE */
/* parse options */
/* start with options field */
options_idx = DHCP_OPTIONS_OFS;
8017e50: 23f0 movs r3, #240 ; 0xf0
8017e52: 86fb strh r3, [r7, #54] ; 0x36
/* parse options to the end of the received packet */
options_idx_max = p->tot_len;
8017e54: 687b ldr r3, [r7, #4]
8017e56: 891b ldrh r3, [r3, #8]
8017e58: 86bb strh r3, [r7, #52] ; 0x34
again:
q = p;
8017e5a: 687b ldr r3, [r7, #4]
8017e5c: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017e5e: e00c b.n 8017e7a <dhcp_parse_reply+0x5a>
options_idx = (u16_t)(options_idx - q->len);
8017e60: 6b3b ldr r3, [r7, #48] ; 0x30
8017e62: 895b ldrh r3, [r3, #10]
8017e64: 8efa ldrh r2, [r7, #54] ; 0x36
8017e66: 1ad3 subs r3, r2, r3
8017e68: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = (u16_t)(options_idx_max - q->len);
8017e6a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e6c: 895b ldrh r3, [r3, #10]
8017e6e: 8eba ldrh r2, [r7, #52] ; 0x34
8017e70: 1ad3 subs r3, r2, r3
8017e72: 86bb strh r3, [r7, #52] ; 0x34
q = q->next;
8017e74: 6b3b ldr r3, [r7, #48] ; 0x30
8017e76: 681b ldr r3, [r3, #0]
8017e78: 633b str r3, [r7, #48] ; 0x30
while ((q != NULL) && (options_idx >= q->len)) {
8017e7a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e7c: 2b00 cmp r3, #0
8017e7e: d004 beq.n 8017e8a <dhcp_parse_reply+0x6a>
8017e80: 6b3b ldr r3, [r7, #48] ; 0x30
8017e82: 895b ldrh r3, [r3, #10]
8017e84: 8efa ldrh r2, [r7, #54] ; 0x36
8017e86: 429a cmp r2, r3
8017e88: d2ea bcs.n 8017e60 <dhcp_parse_reply+0x40>
}
if (q == NULL) {
8017e8a: 6b3b ldr r3, [r7, #48] ; 0x30
8017e8c: 2b00 cmp r3, #0
8017e8e: d102 bne.n 8017e96 <dhcp_parse_reply+0x76>
return ERR_BUF;
8017e90: f06f 0301 mvn.w r3, #1
8017e94: e282 b.n 801839c <dhcp_parse_reply+0x57c>
}
offset = options_idx;
8017e96: 8efb ldrh r3, [r7, #54] ; 0x36
8017e98: 877b strh r3, [r7, #58] ; 0x3a
offset_max = options_idx_max;
8017e9a: 8ebb ldrh r3, [r7, #52] ; 0x34
8017e9c: 873b strh r3, [r7, #56] ; 0x38
options = (u8_t *)q->payload;
8017e9e: 6b3b ldr r3, [r7, #48] ; 0x30
8017ea0: 685b ldr r3, [r3, #4]
8017ea2: 63fb str r3, [r7, #60] ; 0x3c
/* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
8017ea4: e23a b.n 801831c <dhcp_parse_reply+0x4fc>
u8_t op = options[offset];
8017ea6: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ea8: 6bfa ldr r2, [r7, #60] ; 0x3c
8017eaa: 4413 add r3, r2
8017eac: 781b ldrb r3, [r3, #0]
8017eae: 75fb strb r3, [r7, #23]
u8_t len;
u8_t decode_len = 0;
8017eb0: 2300 movs r3, #0
8017eb2: f887 3026 strb.w r3, [r7, #38] ; 0x26
int decode_idx = -1;
8017eb6: f04f 33ff mov.w r3, #4294967295
8017eba: 623b str r3, [r7, #32]
u16_t val_offset = (u16_t)(offset + 2);
8017ebc: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ebe: 3302 adds r3, #2
8017ec0: 83fb strh r3, [r7, #30]
if (val_offset < offset) {
8017ec2: 8bfa ldrh r2, [r7, #30]
8017ec4: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ec6: 429a cmp r2, r3
8017ec8: d202 bcs.n 8017ed0 <dhcp_parse_reply+0xb0>
/* overflow */
return ERR_BUF;
8017eca: f06f 0301 mvn.w r3, #1
8017ece: e265 b.n 801839c <dhcp_parse_reply+0x57c>
}
/* len byte might be in the next pbuf */
if ((offset + 1) < q->len) {
8017ed0: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ed2: 3301 adds r3, #1
8017ed4: 6b3a ldr r2, [r7, #48] ; 0x30
8017ed6: 8952 ldrh r2, [r2, #10]
8017ed8: 4293 cmp r3, r2
8017eda: da07 bge.n 8017eec <dhcp_parse_reply+0xcc>
len = options[offset + 1];
8017edc: 8f7b ldrh r3, [r7, #58] ; 0x3a
8017ede: 3301 adds r3, #1
8017ee0: 6bfa ldr r2, [r7, #60] ; 0x3c
8017ee2: 4413 add r3, r2
8017ee4: 781b ldrb r3, [r3, #0]
8017ee6: f887 3027 strb.w r3, [r7, #39] ; 0x27
8017eea: e00b b.n 8017f04 <dhcp_parse_reply+0xe4>
} else {
len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0);
8017eec: 6b3b ldr r3, [r7, #48] ; 0x30
8017eee: 681b ldr r3, [r3, #0]
8017ef0: 2b00 cmp r3, #0
8017ef2: d004 beq.n 8017efe <dhcp_parse_reply+0xde>
8017ef4: 6b3b ldr r3, [r7, #48] ; 0x30
8017ef6: 681b ldr r3, [r3, #0]
8017ef8: 685b ldr r3, [r3, #4]
8017efa: 781b ldrb r3, [r3, #0]
8017efc: e000 b.n 8017f00 <dhcp_parse_reply+0xe0>
8017efe: 2300 movs r3, #0
8017f00: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
decode_len = len;
8017f04: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8017f08: f887 3026 strb.w r3, [r7, #38] ; 0x26
switch (op) {
8017f0c: 7dfb ldrb r3, [r7, #23]
8017f0e: 2b3b cmp r3, #59 ; 0x3b
8017f10: f200 812d bhi.w 801816e <dhcp_parse_reply+0x34e>
8017f14: a201 add r2, pc, #4 ; (adr r2, 8017f1c <dhcp_parse_reply+0xfc>)
8017f16: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8017f1a: bf00 nop
8017f1c: 0801800d .word 0x0801800d
8017f20: 0801801d .word 0x0801801d
8017f24: 0801816f .word 0x0801816f
8017f28: 0801803f .word 0x0801803f
8017f2c: 0801816f .word 0x0801816f
8017f30: 0801816f .word 0x0801816f
8017f34: 0801816f .word 0x0801816f
8017f38: 0801816f .word 0x0801816f
8017f3c: 0801816f .word 0x0801816f
8017f40: 0801816f .word 0x0801816f
8017f44: 0801816f .word 0x0801816f
8017f48: 0801816f .word 0x0801816f
8017f4c: 0801816f .word 0x0801816f
8017f50: 0801816f .word 0x0801816f
8017f54: 0801816f .word 0x0801816f
8017f58: 0801816f .word 0x0801816f
8017f5c: 0801816f .word 0x0801816f
8017f60: 0801816f .word 0x0801816f
8017f64: 0801816f .word 0x0801816f
8017f68: 0801816f .word 0x0801816f
8017f6c: 0801816f .word 0x0801816f
8017f70: 0801816f .word 0x0801816f
8017f74: 0801816f .word 0x0801816f
8017f78: 0801816f .word 0x0801816f
8017f7c: 0801816f .word 0x0801816f
8017f80: 0801816f .word 0x0801816f
8017f84: 0801816f .word 0x0801816f
8017f88: 0801816f .word 0x0801816f
8017f8c: 0801816f .word 0x0801816f
8017f90: 0801816f .word 0x0801816f
8017f94: 0801816f .word 0x0801816f
8017f98: 0801816f .word 0x0801816f
8017f9c: 0801816f .word 0x0801816f
8017fa0: 0801816f .word 0x0801816f
8017fa4: 0801816f .word 0x0801816f
8017fa8: 0801816f .word 0x0801816f
8017fac: 0801816f .word 0x0801816f
8017fb0: 0801816f .word 0x0801816f
8017fb4: 0801816f .word 0x0801816f
8017fb8: 0801816f .word 0x0801816f
8017fbc: 0801816f .word 0x0801816f
8017fc0: 0801816f .word 0x0801816f
8017fc4: 0801816f .word 0x0801816f
8017fc8: 0801816f .word 0x0801816f
8017fcc: 0801816f .word 0x0801816f
8017fd0: 0801816f .word 0x0801816f
8017fd4: 0801816f .word 0x0801816f
8017fd8: 0801816f .word 0x0801816f
8017fdc: 0801816f .word 0x0801816f
8017fe0: 0801816f .word 0x0801816f
8017fe4: 0801816f .word 0x0801816f
8017fe8: 0801806b .word 0x0801806b
8017fec: 0801808d .word 0x0801808d
8017ff0: 080180c9 .word 0x080180c9
8017ff4: 080180eb .word 0x080180eb
8017ff8: 0801816f .word 0x0801816f
8017ffc: 0801816f .word 0x0801816f
8018000: 0801816f .word 0x0801816f
8018004: 0801810d .word 0x0801810d
8018008: 0801814d .word 0x0801814d
/* case(DHCP_OPTION_END): handled above */
case (DHCP_OPTION_PAD):
/* special option: no len encoded */
decode_len = len = 0;
801800c: 2300 movs r3, #0
801800e: f887 3027 strb.w r3, [r7, #39] ; 0x27
8018012: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018016: f887 3026 strb.w r3, [r7, #38] ; 0x26
/* will be increased below */
break;
801801a: e0ac b.n 8018176 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SUBNET_MASK):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801801c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018020: 2b04 cmp r3, #4
8018022: d009 beq.n 8018038 <dhcp_parse_reply+0x218>
8018024: 4b43 ldr r3, [pc, #268] ; (8018134 <dhcp_parse_reply+0x314>)
8018026: f240 622e movw r2, #1582 ; 0x62e
801802a: 4943 ldr r1, [pc, #268] ; (8018138 <dhcp_parse_reply+0x318>)
801802c: 4843 ldr r0, [pc, #268] ; (801813c <dhcp_parse_reply+0x31c>)
801802e: f002 fff9 bl 801b024 <iprintf>
8018032: f06f 0305 mvn.w r3, #5
8018036: e1b1 b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
8018038: 2306 movs r3, #6
801803a: 623b str r3, [r7, #32]
break;
801803c: e09b b.n 8018176 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_ROUTER):
decode_len = 4; /* only copy the first given router */
801803e: 2304 movs r3, #4
8018040: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
8018044: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
8018048: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801804c: 429a cmp r2, r3
801804e: d209 bcs.n 8018064 <dhcp_parse_reply+0x244>
8018050: 4b38 ldr r3, [pc, #224] ; (8018134 <dhcp_parse_reply+0x314>)
8018052: f240 6233 movw r2, #1587 ; 0x633
8018056: 493a ldr r1, [pc, #232] ; (8018140 <dhcp_parse_reply+0x320>)
8018058: 4838 ldr r0, [pc, #224] ; (801813c <dhcp_parse_reply+0x31c>)
801805a: f002 ffe3 bl 801b024 <iprintf>
801805e: f06f 0305 mvn.w r3, #5
8018062: e19b b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_ROUTER;
8018064: 2307 movs r3, #7
8018066: 623b str r3, [r7, #32]
break;
8018068: e085 b.n 8018176 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
break;
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
case (DHCP_OPTION_LEASE_TIME):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801806a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801806e: 2b04 cmp r3, #4
8018070: d009 beq.n 8018086 <dhcp_parse_reply+0x266>
8018072: 4b30 ldr r3, [pc, #192] ; (8018134 <dhcp_parse_reply+0x314>)
8018074: f240 6241 movw r2, #1601 ; 0x641
8018078: 492f ldr r1, [pc, #188] ; (8018138 <dhcp_parse_reply+0x318>)
801807a: 4830 ldr r0, [pc, #192] ; (801813c <dhcp_parse_reply+0x31c>)
801807c: f002 ffd2 bl 801b024 <iprintf>
8018080: f06f 0305 mvn.w r3, #5
8018084: e18a b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
8018086: 2303 movs r3, #3
8018088: 623b str r3, [r7, #32]
break;
801808a: e074 b.n 8018176 <dhcp_parse_reply+0x356>
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
break;
#endif /* LWIP_DHCP_GET_NTP_SRV*/
case (DHCP_OPTION_OVERLOAD):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
801808c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018090: 2b01 cmp r3, #1
8018092: d009 beq.n 80180a8 <dhcp_parse_reply+0x288>
8018094: 4b27 ldr r3, [pc, #156] ; (8018134 <dhcp_parse_reply+0x314>)
8018096: f240 624f movw r2, #1615 ; 0x64f
801809a: 492a ldr r1, [pc, #168] ; (8018144 <dhcp_parse_reply+0x324>)
801809c: 4827 ldr r0, [pc, #156] ; (801813c <dhcp_parse_reply+0x31c>)
801809e: f002 ffc1 bl 801b024 <iprintf>
80180a2: f06f 0305 mvn.w r3, #5
80180a6: e179 b.n 801839c <dhcp_parse_reply+0x57c>
/* decode overload only in options, not in file/sname: invalid packet */
LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;);
80180a8: 8efb ldrh r3, [r7, #54] ; 0x36
80180aa: 2bf0 cmp r3, #240 ; 0xf0
80180ac: d009 beq.n 80180c2 <dhcp_parse_reply+0x2a2>
80180ae: 4b21 ldr r3, [pc, #132] ; (8018134 <dhcp_parse_reply+0x314>)
80180b0: f240 6251 movw r2, #1617 ; 0x651
80180b4: 4924 ldr r1, [pc, #144] ; (8018148 <dhcp_parse_reply+0x328>)
80180b6: 4821 ldr r0, [pc, #132] ; (801813c <dhcp_parse_reply+0x31c>)
80180b8: f002 ffb4 bl 801b024 <iprintf>
80180bc: f06f 0305 mvn.w r3, #5
80180c0: e16c b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_OVERLOAD;
80180c2: 2300 movs r3, #0
80180c4: 623b str r3, [r7, #32]
break;
80180c6: e056 b.n 8018176 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_MESSAGE_TYPE):
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
80180c8: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80180cc: 2b01 cmp r3, #1
80180ce: d009 beq.n 80180e4 <dhcp_parse_reply+0x2c4>
80180d0: 4b18 ldr r3, [pc, #96] ; (8018134 <dhcp_parse_reply+0x314>)
80180d2: f240 6255 movw r2, #1621 ; 0x655
80180d6: 491b ldr r1, [pc, #108] ; (8018144 <dhcp_parse_reply+0x324>)
80180d8: 4818 ldr r0, [pc, #96] ; (801813c <dhcp_parse_reply+0x31c>)
80180da: f002 ffa3 bl 801b024 <iprintf>
80180de: f06f 0305 mvn.w r3, #5
80180e2: e15b b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
80180e4: 2301 movs r3, #1
80180e6: 623b str r3, [r7, #32]
break;
80180e8: e045 b.n 8018176 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_SERVER_ID):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
80180ea: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80180ee: 2b04 cmp r3, #4
80180f0: d009 beq.n 8018106 <dhcp_parse_reply+0x2e6>
80180f2: 4b10 ldr r3, [pc, #64] ; (8018134 <dhcp_parse_reply+0x314>)
80180f4: f240 6259 movw r2, #1625 ; 0x659
80180f8: 490f ldr r1, [pc, #60] ; (8018138 <dhcp_parse_reply+0x318>)
80180fa: 4810 ldr r0, [pc, #64] ; (801813c <dhcp_parse_reply+0x31c>)
80180fc: f002 ff92 bl 801b024 <iprintf>
8018100: f06f 0305 mvn.w r3, #5
8018104: e14a b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_SERVER_ID;
8018106: 2302 movs r3, #2
8018108: 623b str r3, [r7, #32]
break;
801810a: e034 b.n 8018176 <dhcp_parse_reply+0x356>
case (DHCP_OPTION_T1):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801810c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018110: 2b04 cmp r3, #4
8018112: d009 beq.n 8018128 <dhcp_parse_reply+0x308>
8018114: 4b07 ldr r3, [pc, #28] ; (8018134 <dhcp_parse_reply+0x314>)
8018116: f240 625d movw r2, #1629 ; 0x65d
801811a: 4907 ldr r1, [pc, #28] ; (8018138 <dhcp_parse_reply+0x318>)
801811c: 4807 ldr r0, [pc, #28] ; (801813c <dhcp_parse_reply+0x31c>)
801811e: f002 ff81 bl 801b024 <iprintf>
8018122: f06f 0305 mvn.w r3, #5
8018126: e139 b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T1;
8018128: 2304 movs r3, #4
801812a: 623b str r3, [r7, #32]
break;
801812c: e023 b.n 8018176 <dhcp_parse_reply+0x356>
801812e: bf00 nop
8018130: 2000f5dc .word 0x2000f5dc
8018134: 0801e3a8 .word 0x0801e3a8
8018138: 0801e630 .word 0x0801e630
801813c: 0801e408 .word 0x0801e408
8018140: 0801e63c .word 0x0801e63c
8018144: 0801e650 .word 0x0801e650
8018148: 0801e65c .word 0x0801e65c
case (DHCP_OPTION_T2):
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
801814c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018150: 2b04 cmp r3, #4
8018152: d009 beq.n 8018168 <dhcp_parse_reply+0x348>
8018154: 4b93 ldr r3, [pc, #588] ; (80183a4 <dhcp_parse_reply+0x584>)
8018156: f240 6261 movw r2, #1633 ; 0x661
801815a: 4993 ldr r1, [pc, #588] ; (80183a8 <dhcp_parse_reply+0x588>)
801815c: 4893 ldr r0, [pc, #588] ; (80183ac <dhcp_parse_reply+0x58c>)
801815e: f002 ff61 bl 801b024 <iprintf>
8018162: f06f 0305 mvn.w r3, #5
8018166: e119 b.n 801839c <dhcp_parse_reply+0x57c>
decode_idx = DHCP_OPTION_IDX_T2;
8018168: 2305 movs r3, #5
801816a: 623b str r3, [r7, #32]
break;
801816c: e003 b.n 8018176 <dhcp_parse_reply+0x356>
default:
decode_len = 0;
801816e: 2300 movs r3, #0
8018170: f887 3026 strb.w r3, [r7, #38] ; 0x26
LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op));
LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in,
dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0,
op, len, q, val_offset);
break;
8018174: bf00 nop
}
if (op == DHCP_OPTION_PAD) {
8018176: 7dfb ldrb r3, [r7, #23]
8018178: 2b00 cmp r3, #0
801817a: d103 bne.n 8018184 <dhcp_parse_reply+0x364>
offset++;
801817c: 8f7b ldrh r3, [r7, #58] ; 0x3a
801817e: 3301 adds r3, #1
8018180: 877b strh r3, [r7, #58] ; 0x3a
8018182: e0a1 b.n 80182c8 <dhcp_parse_reply+0x4a8>
} else {
if (offset + len + 2 > 0xFFFF) {
8018184: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018186: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801818a: 4413 add r3, r2
801818c: 3302 adds r3, #2
801818e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8018192: db02 blt.n 801819a <dhcp_parse_reply+0x37a>
/* overflow */
return ERR_BUF;
8018194: f06f 0301 mvn.w r3, #1
8018198: e100 b.n 801839c <dhcp_parse_reply+0x57c>
}
offset = (u16_t)(offset + len + 2);
801819a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801819e: b29a uxth r2, r3
80181a0: 8f7b ldrh r3, [r7, #58] ; 0x3a
80181a2: 4413 add r3, r2
80181a4: b29b uxth r3, r3
80181a6: 3302 adds r3, #2
80181a8: 877b strh r3, [r7, #58] ; 0x3a
if (decode_len > 0) {
80181aa: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181ae: 2b00 cmp r3, #0
80181b0: f000 808a beq.w 80182c8 <dhcp_parse_reply+0x4a8>
u32_t value = 0;
80181b4: 2300 movs r3, #0
80181b6: 60bb str r3, [r7, #8]
u16_t copy_len;
decode_next:
LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
80181b8: 6a3b ldr r3, [r7, #32]
80181ba: 2b00 cmp r3, #0
80181bc: db02 blt.n 80181c4 <dhcp_parse_reply+0x3a4>
80181be: 6a3b ldr r3, [r7, #32]
80181c0: 2b07 cmp r3, #7
80181c2: dd06 ble.n 80181d2 <dhcp_parse_reply+0x3b2>
80181c4: 4b77 ldr r3, [pc, #476] ; (80183a4 <dhcp_parse_reply+0x584>)
80181c6: f44f 62cf mov.w r2, #1656 ; 0x678
80181ca: 4979 ldr r1, [pc, #484] ; (80183b0 <dhcp_parse_reply+0x590>)
80181cc: 4877 ldr r0, [pc, #476] ; (80183ac <dhcp_parse_reply+0x58c>)
80181ce: f002 ff29 bl 801b024 <iprintf>
if (!dhcp_option_given(dhcp, decode_idx)) {
80181d2: 4a78 ldr r2, [pc, #480] ; (80183b4 <dhcp_parse_reply+0x594>)
80181d4: 6a3b ldr r3, [r7, #32]
80181d6: 4413 add r3, r2
80181d8: 781b ldrb r3, [r3, #0]
80181da: 2b00 cmp r3, #0
80181dc: d174 bne.n 80182c8 <dhcp_parse_reply+0x4a8>
copy_len = LWIP_MIN(decode_len, 4);
80181de: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
80181e2: 2b04 cmp r3, #4
80181e4: bf28 it cs
80181e6: 2304 movcs r3, #4
80181e8: b2db uxtb r3, r3
80181ea: 82bb strh r3, [r7, #20]
if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) {
80181ec: 8bfb ldrh r3, [r7, #30]
80181ee: 8aba ldrh r2, [r7, #20]
80181f0: f107 0108 add.w r1, r7, #8
80181f4: 6b38 ldr r0, [r7, #48] ; 0x30
80181f6: f7f8 fc05 bl 8010a04 <pbuf_copy_partial>
80181fa: 4603 mov r3, r0
80181fc: 461a mov r2, r3
80181fe: 8abb ldrh r3, [r7, #20]
8018200: 4293 cmp r3, r2
8018202: d002 beq.n 801820a <dhcp_parse_reply+0x3ea>
return ERR_BUF;
8018204: f06f 0301 mvn.w r3, #1
8018208: e0c8 b.n 801839c <dhcp_parse_reply+0x57c>
}
if (decode_len > 4) {
801820a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801820e: 2b04 cmp r3, #4
8018210: d933 bls.n 801827a <dhcp_parse_reply+0x45a>
/* decode more than one u32_t */
u16_t next_val_offset;
LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
8018212: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018216: f003 0303 and.w r3, r3, #3
801821a: b2db uxtb r3, r3
801821c: 2b00 cmp r3, #0
801821e: d009 beq.n 8018234 <dhcp_parse_reply+0x414>
8018220: 4b60 ldr r3, [pc, #384] ; (80183a4 <dhcp_parse_reply+0x584>)
8018222: f240 6281 movw r2, #1665 ; 0x681
8018226: 4964 ldr r1, [pc, #400] ; (80183b8 <dhcp_parse_reply+0x598>)
8018228: 4860 ldr r0, [pc, #384] ; (80183ac <dhcp_parse_reply+0x58c>)
801822a: f002 fefb bl 801b024 <iprintf>
801822e: f06f 0305 mvn.w r3, #5
8018232: e0b3 b.n 801839c <dhcp_parse_reply+0x57c>
dhcp_got_option(dhcp, decode_idx);
8018234: 4a5f ldr r2, [pc, #380] ; (80183b4 <dhcp_parse_reply+0x594>)
8018236: 6a3b ldr r3, [r7, #32]
8018238: 4413 add r3, r2
801823a: 2201 movs r2, #1
801823c: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value));
801823e: 68bb ldr r3, [r7, #8]
8018240: 4618 mov r0, r3
8018242: f7f6 fe3a bl 800eeba <lwip_htonl>
8018246: 4601 mov r1, r0
8018248: 4a5c ldr r2, [pc, #368] ; (80183bc <dhcp_parse_reply+0x59c>)
801824a: 6a3b ldr r3, [r7, #32]
801824c: f842 1023 str.w r1, [r2, r3, lsl #2]
decode_len = (u8_t)(decode_len - 4);
8018250: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018254: 3b04 subs r3, #4
8018256: f887 3026 strb.w r3, [r7, #38] ; 0x26
next_val_offset = (u16_t)(val_offset + 4);
801825a: 8bfb ldrh r3, [r7, #30]
801825c: 3304 adds r3, #4
801825e: 827b strh r3, [r7, #18]
if (next_val_offset < val_offset) {
8018260: 8a7a ldrh r2, [r7, #18]
8018262: 8bfb ldrh r3, [r7, #30]
8018264: 429a cmp r2, r3
8018266: d202 bcs.n 801826e <dhcp_parse_reply+0x44e>
/* overflow */
return ERR_BUF;
8018268: f06f 0301 mvn.w r3, #1
801826c: e096 b.n 801839c <dhcp_parse_reply+0x57c>
}
val_offset = next_val_offset;
801826e: 8a7b ldrh r3, [r7, #18]
8018270: 83fb strh r3, [r7, #30]
decode_idx++;
8018272: 6a3b ldr r3, [r7, #32]
8018274: 3301 adds r3, #1
8018276: 623b str r3, [r7, #32]
goto decode_next;
8018278: e79e b.n 80181b8 <dhcp_parse_reply+0x398>
} else if (decode_len == 4) {
801827a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
801827e: 2b04 cmp r3, #4
8018280: d106 bne.n 8018290 <dhcp_parse_reply+0x470>
value = lwip_ntohl(value);
8018282: 68bb ldr r3, [r7, #8]
8018284: 4618 mov r0, r3
8018286: f7f6 fe18 bl 800eeba <lwip_htonl>
801828a: 4603 mov r3, r0
801828c: 60bb str r3, [r7, #8]
801828e: e011 b.n 80182b4 <dhcp_parse_reply+0x494>
} else {
LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
8018290: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
8018294: 2b01 cmp r3, #1
8018296: d009 beq.n 80182ac <dhcp_parse_reply+0x48c>
8018298: 4b42 ldr r3, [pc, #264] ; (80183a4 <dhcp_parse_reply+0x584>)
801829a: f44f 62d2 mov.w r2, #1680 ; 0x690
801829e: 4948 ldr r1, [pc, #288] ; (80183c0 <dhcp_parse_reply+0x5a0>)
80182a0: 4842 ldr r0, [pc, #264] ; (80183ac <dhcp_parse_reply+0x58c>)
80182a2: f002 febf bl 801b024 <iprintf>
80182a6: f06f 0305 mvn.w r3, #5
80182aa: e077 b.n 801839c <dhcp_parse_reply+0x57c>
value = ((u8_t *)&value)[0];
80182ac: f107 0308 add.w r3, r7, #8
80182b0: 781b ldrb r3, [r3, #0]
80182b2: 60bb str r3, [r7, #8]
}
dhcp_got_option(dhcp, decode_idx);
80182b4: 4a3f ldr r2, [pc, #252] ; (80183b4 <dhcp_parse_reply+0x594>)
80182b6: 6a3b ldr r3, [r7, #32]
80182b8: 4413 add r3, r2
80182ba: 2201 movs r2, #1
80182bc: 701a strb r2, [r3, #0]
dhcp_set_option_value(dhcp, decode_idx, value);
80182be: 68ba ldr r2, [r7, #8]
80182c0: 493e ldr r1, [pc, #248] ; (80183bc <dhcp_parse_reply+0x59c>)
80182c2: 6a3b ldr r3, [r7, #32]
80182c4: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
}
if (offset >= q->len) {
80182c8: 6b3b ldr r3, [r7, #48] ; 0x30
80182ca: 895b ldrh r3, [r3, #10]
80182cc: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182ce: 429a cmp r2, r3
80182d0: d324 bcc.n 801831c <dhcp_parse_reply+0x4fc>
offset = (u16_t)(offset - q->len);
80182d2: 6b3b ldr r3, [r7, #48] ; 0x30
80182d4: 895b ldrh r3, [r3, #10]
80182d6: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182d8: 1ad3 subs r3, r2, r3
80182da: 877b strh r3, [r7, #58] ; 0x3a
offset_max = (u16_t)(offset_max - q->len);
80182dc: 6b3b ldr r3, [r7, #48] ; 0x30
80182de: 895b ldrh r3, [r3, #10]
80182e0: 8f3a ldrh r2, [r7, #56] ; 0x38
80182e2: 1ad3 subs r3, r2, r3
80182e4: 873b strh r3, [r7, #56] ; 0x38
if (offset < offset_max) {
80182e6: 8f7a ldrh r2, [r7, #58] ; 0x3a
80182e8: 8f3b ldrh r3, [r7, #56] ; 0x38
80182ea: 429a cmp r2, r3
80182ec: d213 bcs.n 8018316 <dhcp_parse_reply+0x4f6>
q = q->next;
80182ee: 6b3b ldr r3, [r7, #48] ; 0x30
80182f0: 681b ldr r3, [r3, #0]
80182f2: 633b str r3, [r7, #48] ; 0x30
LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;);
80182f4: 6b3b ldr r3, [r7, #48] ; 0x30
80182f6: 2b00 cmp r3, #0
80182f8: d109 bne.n 801830e <dhcp_parse_reply+0x4ee>
80182fa: 4b2a ldr r3, [pc, #168] ; (80183a4 <dhcp_parse_reply+0x584>)
80182fc: f240 629d movw r2, #1693 ; 0x69d
8018300: 4930 ldr r1, [pc, #192] ; (80183c4 <dhcp_parse_reply+0x5a4>)
8018302: 482a ldr r0, [pc, #168] ; (80183ac <dhcp_parse_reply+0x58c>)
8018304: f002 fe8e bl 801b024 <iprintf>
8018308: f06f 0305 mvn.w r3, #5
801830c: e046 b.n 801839c <dhcp_parse_reply+0x57c>
options = (u8_t *)q->payload;
801830e: 6b3b ldr r3, [r7, #48] ; 0x30
8018310: 685b ldr r3, [r3, #4]
8018312: 63fb str r3, [r7, #60] ; 0x3c
8018314: e002 b.n 801831c <dhcp_parse_reply+0x4fc>
} else {
/* We've run out of bytes, probably no end marker. Don't proceed. */
return ERR_BUF;
8018316: f06f 0301 mvn.w r3, #1
801831a: e03f b.n 801839c <dhcp_parse_reply+0x57c>
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
801831c: 6b3b ldr r3, [r7, #48] ; 0x30
801831e: 2b00 cmp r3, #0
8018320: d00a beq.n 8018338 <dhcp_parse_reply+0x518>
8018322: 8f7a ldrh r2, [r7, #58] ; 0x3a
8018324: 8f3b ldrh r3, [r7, #56] ; 0x38
8018326: 429a cmp r2, r3
8018328: d206 bcs.n 8018338 <dhcp_parse_reply+0x518>
801832a: 8f7b ldrh r3, [r7, #58] ; 0x3a
801832c: 6bfa ldr r2, [r7, #60] ; 0x3c
801832e: 4413 add r3, r2
8018330: 781b ldrb r3, [r3, #0]
8018332: 2bff cmp r3, #255 ; 0xff
8018334: f47f adb7 bne.w 8017ea6 <dhcp_parse_reply+0x86>
}
}
}
/* is this an overloaded message? */
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
8018338: 4b1e ldr r3, [pc, #120] ; (80183b4 <dhcp_parse_reply+0x594>)
801833a: 781b ldrb r3, [r3, #0]
801833c: 2b00 cmp r3, #0
801833e: d018 beq.n 8018372 <dhcp_parse_reply+0x552>
u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
8018340: 4b1e ldr r3, [pc, #120] ; (80183bc <dhcp_parse_reply+0x59c>)
8018342: 681b ldr r3, [r3, #0]
8018344: 60fb str r3, [r7, #12]
dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
8018346: 4b1b ldr r3, [pc, #108] ; (80183b4 <dhcp_parse_reply+0x594>)
8018348: 2200 movs r2, #0
801834a: 701a strb r2, [r3, #0]
if (overload == DHCP_OVERLOAD_FILE) {
801834c: 68fb ldr r3, [r7, #12]
801834e: 2b01 cmp r3, #1
8018350: d102 bne.n 8018358 <dhcp_parse_reply+0x538>
parse_file_as_options = 1;
8018352: 2301 movs r3, #1
8018354: 62fb str r3, [r7, #44] ; 0x2c
8018356: e00c b.n 8018372 <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME) {
8018358: 68fb ldr r3, [r7, #12]
801835a: 2b02 cmp r3, #2
801835c: d102 bne.n 8018364 <dhcp_parse_reply+0x544>
parse_sname_as_options = 1;
801835e: 2301 movs r3, #1
8018360: 62bb str r3, [r7, #40] ; 0x28
8018362: e006 b.n 8018372 <dhcp_parse_reply+0x552>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
} else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
8018364: 68fb ldr r3, [r7, #12]
8018366: 2b03 cmp r3, #3
8018368: d103 bne.n 8018372 <dhcp_parse_reply+0x552>
parse_sname_as_options = 1;
801836a: 2301 movs r3, #1
801836c: 62bb str r3, [r7, #40] ; 0x28
parse_file_as_options = 1;
801836e: 2301 movs r3, #1
8018370: 62fb str r3, [r7, #44] ; 0x2c
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
} else {
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
}
}
if (parse_file_as_options) {
8018372: 6afb ldr r3, [r7, #44] ; 0x2c
8018374: 2b00 cmp r3, #0
8018376: d006 beq.n 8018386 <dhcp_parse_reply+0x566>
/* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
parse_file_as_options = 0;
8018378: 2300 movs r3, #0
801837a: 62fb str r3, [r7, #44] ; 0x2c
options_idx = DHCP_FILE_OFS;
801837c: 236c movs r3, #108 ; 0x6c
801837e: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
8018380: 23ec movs r3, #236 ; 0xec
8018382: 86bb strh r3, [r7, #52] ; 0x34
#if LWIP_DHCP_BOOTP_FILE
file_overloaded = 1;
#endif
goto again;
8018384: e569 b.n 8017e5a <dhcp_parse_reply+0x3a>
} else if (parse_sname_as_options) {
8018386: 6abb ldr r3, [r7, #40] ; 0x28
8018388: 2b00 cmp r3, #0
801838a: d006 beq.n 801839a <dhcp_parse_reply+0x57a>
parse_sname_as_options = 0;
801838c: 2300 movs r3, #0
801838e: 62bb str r3, [r7, #40] ; 0x28
options_idx = DHCP_SNAME_OFS;
8018390: 232c movs r3, #44 ; 0x2c
8018392: 86fb strh r3, [r7, #54] ; 0x36
options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
8018394: 236c movs r3, #108 ; 0x6c
8018396: 86bb strh r3, [r7, #52] ; 0x34
goto again;
8018398: e55f b.n 8017e5a <dhcp_parse_reply+0x3a>
}
/* make sure the string is really NULL-terminated */
dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
}
#endif /* LWIP_DHCP_BOOTP_FILE */
return ERR_OK;
801839a: 2300 movs r3, #0
}
801839c: 4618 mov r0, r3
801839e: 3740 adds r7, #64 ; 0x40
80183a0: 46bd mov sp, r7
80183a2: bd80 pop {r7, pc}
80183a4: 0801e3a8 .word 0x0801e3a8
80183a8: 0801e630 .word 0x0801e630
80183ac: 0801e408 .word 0x0801e408
80183b0: 0801e674 .word 0x0801e674
80183b4: 2000f5dc .word 0x2000f5dc
80183b8: 0801e688 .word 0x0801e688
80183bc: 2000f5e4 .word 0x2000f5e4
80183c0: 0801e6a0 .word 0x0801e6a0
80183c4: 0801e6b4 .word 0x0801e6b4
080183c8 <dhcp_recv>:
/**
* If an incoming DHCP message is in response to us, then trigger the state machine
*/
static void
dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
{
80183c8: b580 push {r7, lr}
80183ca: b08a sub sp, #40 ; 0x28
80183cc: af00 add r7, sp, #0
80183ce: 60f8 str r0, [r7, #12]
80183d0: 60b9 str r1, [r7, #8]
80183d2: 607a str r2, [r7, #4]
80183d4: 603b str r3, [r7, #0]
struct netif *netif = ip_current_input_netif();
80183d6: 4b5f ldr r3, [pc, #380] ; (8018554 <dhcp_recv+0x18c>)
80183d8: 685b ldr r3, [r3, #4]
80183da: 623b str r3, [r7, #32]
struct dhcp *dhcp = netif_dhcp_data(netif);
80183dc: 6a3b ldr r3, [r7, #32]
80183de: 6a5b ldr r3, [r3, #36] ; 0x24
80183e0: 61fb str r3, [r7, #28]
struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
80183e2: 687b ldr r3, [r7, #4]
80183e4: 685b ldr r3, [r3, #4]
80183e6: 61bb str r3, [r7, #24]
struct dhcp_msg *msg_in;
LWIP_UNUSED_ARG(arg);
/* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */
if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) {
80183e8: 69fb ldr r3, [r7, #28]
80183ea: 2b00 cmp r3, #0
80183ec: f000 809d beq.w 801852a <dhcp_recv+0x162>
80183f0: 69fb ldr r3, [r7, #28]
80183f2: 791b ldrb r3, [r3, #4]
80183f4: 2b00 cmp r3, #0
80183f6: f000 8098 beq.w 801852a <dhcp_recv+0x162>
/* prevent warnings about unused arguments */
LWIP_UNUSED_ARG(pcb);
LWIP_UNUSED_ARG(addr);
LWIP_UNUSED_ARG(port);
if (p->len < DHCP_MIN_REPLY_LEN) {
80183fa: 687b ldr r3, [r7, #4]
80183fc: 895b ldrh r3, [r3, #10]
80183fe: 2b2b cmp r3, #43 ; 0x2b
8018400: f240 8095 bls.w 801852e <dhcp_recv+0x166>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
goto free_pbuf_and_return;
}
if (reply_msg->op != DHCP_BOOTREPLY) {
8018404: 69bb ldr r3, [r7, #24]
8018406: 781b ldrb r3, [r3, #0]
8018408: 2b02 cmp r3, #2
801840a: f040 8092 bne.w 8018532 <dhcp_recv+0x16a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
goto free_pbuf_and_return;
}
/* iterate through hardware address and match against DHCP message */
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
801840e: 2300 movs r3, #0
8018410: f887 3027 strb.w r3, [r7, #39] ; 0x27
8018414: e012 b.n 801843c <dhcp_recv+0x74>
if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
8018416: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801841a: 6a3a ldr r2, [r7, #32]
801841c: 4413 add r3, r2
801841e: f893 202a ldrb.w r2, [r3, #42] ; 0x2a
8018422: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018426: 69b9 ldr r1, [r7, #24]
8018428: 440b add r3, r1
801842a: 7f1b ldrb r3, [r3, #28]
801842c: 429a cmp r2, r3
801842e: f040 8082 bne.w 8018536 <dhcp_recv+0x16e>
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018432: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
8018436: 3301 adds r3, #1
8018438: f887 3027 strb.w r3, [r7, #39] ; 0x27
801843c: 6a3b ldr r3, [r7, #32]
801843e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8018442: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
8018446: 429a cmp r2, r3
8018448: d203 bcs.n 8018452 <dhcp_recv+0x8a>
801844a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
801844e: 2b05 cmp r3, #5
8018450: d9e1 bls.n 8018416 <dhcp_recv+0x4e>
(u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
goto free_pbuf_and_return;
}
}
/* match transaction ID against what we expected */
if (lwip_ntohl(reply_msg->xid) != dhcp->xid) {
8018452: 69bb ldr r3, [r7, #24]
8018454: 685b ldr r3, [r3, #4]
8018456: 4618 mov r0, r3
8018458: f7f6 fd2f bl 800eeba <lwip_htonl>
801845c: 4602 mov r2, r0
801845e: 69fb ldr r3, [r7, #28]
8018460: 681b ldr r3, [r3, #0]
8018462: 429a cmp r2, r3
8018464: d169 bne.n 801853a <dhcp_recv+0x172>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid));
goto free_pbuf_and_return;
}
/* option fields could be unfold? */
if (dhcp_parse_reply(p, dhcp) != ERR_OK) {
8018466: 69f9 ldr r1, [r7, #28]
8018468: 6878 ldr r0, [r7, #4]
801846a: f7ff fcd9 bl 8017e20 <dhcp_parse_reply>
801846e: 4603 mov r3, r0
8018470: 2b00 cmp r3, #0
8018472: d164 bne.n 801853e <dhcp_recv+0x176>
goto free_pbuf_and_return;
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
/* obtain pointer to DHCP message type */
if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
8018474: 4b38 ldr r3, [pc, #224] ; (8018558 <dhcp_recv+0x190>)
8018476: 785b ldrb r3, [r3, #1]
8018478: 2b00 cmp r3, #0
801847a: d062 beq.n 8018542 <dhcp_recv+0x17a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
goto free_pbuf_and_return;
}
msg_in = (struct dhcp_msg *)p->payload;
801847c: 687b ldr r3, [r7, #4]
801847e: 685b ldr r3, [r3, #4]
8018480: 617b str r3, [r7, #20]
/* read DHCP message type */
msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
8018482: 4b36 ldr r3, [pc, #216] ; (801855c <dhcp_recv+0x194>)
8018484: 685b ldr r3, [r3, #4]
8018486: 74fb strb r3, [r7, #19]
/* message type is DHCP ACK? */
if (msg_type == DHCP_ACK) {
8018488: 7cfb ldrb r3, [r7, #19]
801848a: 2b05 cmp r3, #5
801848c: d12a bne.n 80184e4 <dhcp_recv+0x11c>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
/* in requesting state? */
if (dhcp->state == DHCP_STATE_REQUESTING) {
801848e: 69fb ldr r3, [r7, #28]
8018490: 795b ldrb r3, [r3, #5]
8018492: 2b01 cmp r3, #1
8018494: d112 bne.n 80184bc <dhcp_recv+0xf4>
dhcp_handle_ack(netif, msg_in);
8018496: 6979 ldr r1, [r7, #20]
8018498: 6a38 ldr r0, [r7, #32]
801849a: f7fe fe05 bl 80170a8 <dhcp_handle_ack>
#if DHCP_DOES_ARP_CHECK
if ((netif->flags & NETIF_FLAG_ETHARP) != 0) {
801849e: 6a3b ldr r3, [r7, #32]
80184a0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80184a4: f003 0308 and.w r3, r3, #8
80184a8: 2b00 cmp r3, #0
80184aa: d003 beq.n 80184b4 <dhcp_recv+0xec>
/* check if the acknowledged lease address is already in use */
dhcp_check(netif);
80184ac: 6a38 ldr r0, [r7, #32]
80184ae: f7fe fb73 bl 8016b98 <dhcp_check>
80184b2: e047 b.n 8018544 <dhcp_recv+0x17c>
} else {
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
80184b4: 6a38 ldr r0, [r7, #32]
80184b6: f7ff f867 bl 8017588 <dhcp_bind>
80184ba: e043 b.n 8018544 <dhcp_recv+0x17c>
/* bind interface to the acknowledged lease address */
dhcp_bind(netif);
#endif
}
/* already bound to the given lease address? */
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
80184bc: 69fb ldr r3, [r7, #28]
80184be: 795b ldrb r3, [r3, #5]
80184c0: 2b03 cmp r3, #3
80184c2: d007 beq.n 80184d4 <dhcp_recv+0x10c>
80184c4: 69fb ldr r3, [r7, #28]
80184c6: 795b ldrb r3, [r3, #5]
80184c8: 2b04 cmp r3, #4
80184ca: d003 beq.n 80184d4 <dhcp_recv+0x10c>
(dhcp->state == DHCP_STATE_RENEWING)) {
80184cc: 69fb ldr r3, [r7, #28]
80184ce: 795b ldrb r3, [r3, #5]
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
80184d0: 2b05 cmp r3, #5
80184d2: d137 bne.n 8018544 <dhcp_recv+0x17c>
dhcp_handle_ack(netif, msg_in);
80184d4: 6979 ldr r1, [r7, #20]
80184d6: 6a38 ldr r0, [r7, #32]
80184d8: f7fe fde6 bl 80170a8 <dhcp_handle_ack>
dhcp_bind(netif);
80184dc: 6a38 ldr r0, [r7, #32]
80184de: f7ff f853 bl 8017588 <dhcp_bind>
80184e2: e02f b.n 8018544 <dhcp_recv+0x17c>
}
}
/* received a DHCP_NAK in appropriate state? */
else if ((msg_type == DHCP_NAK) &&
80184e4: 7cfb ldrb r3, [r7, #19]
80184e6: 2b06 cmp r3, #6
80184e8: d113 bne.n 8018512 <dhcp_recv+0x14a>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184ea: 69fb ldr r3, [r7, #28]
80184ec: 795b ldrb r3, [r3, #5]
else if ((msg_type == DHCP_NAK) &&
80184ee: 2b03 cmp r3, #3
80184f0: d00b beq.n 801850a <dhcp_recv+0x142>
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184f2: 69fb ldr r3, [r7, #28]
80184f4: 795b ldrb r3, [r3, #5]
80184f6: 2b01 cmp r3, #1
80184f8: d007 beq.n 801850a <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
80184fa: 69fb ldr r3, [r7, #28]
80184fc: 795b ldrb r3, [r3, #5]
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
80184fe: 2b04 cmp r3, #4
8018500: d003 beq.n 801850a <dhcp_recv+0x142>
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
8018502: 69fb ldr r3, [r7, #28]
8018504: 795b ldrb r3, [r3, #5]
8018506: 2b05 cmp r3, #5
8018508: d103 bne.n 8018512 <dhcp_recv+0x14a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
dhcp_handle_nak(netif);
801850a: 6a38 ldr r0, [r7, #32]
801850c: f7fe fb2a bl 8016b64 <dhcp_handle_nak>
8018510: e018 b.n 8018544 <dhcp_recv+0x17c>
}
/* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
8018512: 7cfb ldrb r3, [r7, #19]
8018514: 2b02 cmp r3, #2
8018516: d108 bne.n 801852a <dhcp_recv+0x162>
8018518: 69fb ldr r3, [r7, #28]
801851a: 795b ldrb r3, [r3, #5]
801851c: 2b06 cmp r3, #6
801851e: d104 bne.n 801852a <dhcp_recv+0x162>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
/* remember offered lease */
dhcp_handle_offer(netif, msg_in);
8018520: 6979 ldr r1, [r7, #20]
8018522: 6a38 ldr r0, [r7, #32]
8018524: f7fe fb6c bl 8016c00 <dhcp_handle_offer>
8018528: e00c b.n 8018544 <dhcp_recv+0x17c>
}
free_pbuf_and_return:
801852a: bf00 nop
801852c: e00a b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801852e: bf00 nop
8018530: e008 b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018532: bf00 nop
8018534: e006 b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018536: bf00 nop
8018538: e004 b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801853a: bf00 nop
801853c: e002 b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
801853e: bf00 nop
8018540: e000 b.n 8018544 <dhcp_recv+0x17c>
goto free_pbuf_and_return;
8018542: bf00 nop
pbuf_free(p);
8018544: 6878 ldr r0, [r7, #4]
8018546: f7f8 f857 bl 80105f8 <pbuf_free>
}
801854a: bf00 nop
801854c: 3728 adds r7, #40 ; 0x28
801854e: 46bd mov sp, r7
8018550: bd80 pop {r7, pc}
8018552: bf00 nop
8018554: 2000be8c .word 0x2000be8c
8018558: 2000f5dc .word 0x2000f5dc
801855c: 2000f5e4 .word 0x2000f5e4
08018560 <dhcp_create_msg>:
* @param dhcp dhcp control struct
* @param message_type message type of the request
*/
static struct pbuf *
dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len)
{
8018560: b580 push {r7, lr}
8018562: b088 sub sp, #32
8018564: af00 add r7, sp, #0
8018566: 60f8 str r0, [r7, #12]
8018568: 60b9 str r1, [r7, #8]
801856a: 603b str r3, [r7, #0]
801856c: 4613 mov r3, r2
801856e: 71fb strb r3, [r7, #7]
if (!xid_initialised) {
xid = DHCP_GLOBAL_XID;
xid_initialised = !xid_initialised;
}
#endif
LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;);
8018570: 68fb ldr r3, [r7, #12]
8018572: 2b00 cmp r3, #0
8018574: d108 bne.n 8018588 <dhcp_create_msg+0x28>
8018576: 4b5f ldr r3, [pc, #380] ; (80186f4 <dhcp_create_msg+0x194>)
8018578: f240 7269 movw r2, #1897 ; 0x769
801857c: 495e ldr r1, [pc, #376] ; (80186f8 <dhcp_create_msg+0x198>)
801857e: 485f ldr r0, [pc, #380] ; (80186fc <dhcp_create_msg+0x19c>)
8018580: f002 fd50 bl 801b024 <iprintf>
8018584: 2300 movs r3, #0
8018586: e0b1 b.n 80186ec <dhcp_create_msg+0x18c>
LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;);
8018588: 68bb ldr r3, [r7, #8]
801858a: 2b00 cmp r3, #0
801858c: d108 bne.n 80185a0 <dhcp_create_msg+0x40>
801858e: 4b59 ldr r3, [pc, #356] ; (80186f4 <dhcp_create_msg+0x194>)
8018590: f240 726a movw r2, #1898 ; 0x76a
8018594: 495a ldr r1, [pc, #360] ; (8018700 <dhcp_create_msg+0x1a0>)
8018596: 4859 ldr r0, [pc, #356] ; (80186fc <dhcp_create_msg+0x19c>)
8018598: f002 fd44 bl 801b024 <iprintf>
801859c: 2300 movs r3, #0
801859e: e0a5 b.n 80186ec <dhcp_create_msg+0x18c>
p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
80185a0: f44f 7220 mov.w r2, #640 ; 0x280
80185a4: f44f 719a mov.w r1, #308 ; 0x134
80185a8: 2036 movs r0, #54 ; 0x36
80185aa: f7f7 fd45 bl 8010038 <pbuf_alloc>
80185ae: 61b8 str r0, [r7, #24]
if (p_out == NULL) {
80185b0: 69bb ldr r3, [r7, #24]
80185b2: 2b00 cmp r3, #0
80185b4: d101 bne.n 80185ba <dhcp_create_msg+0x5a>
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("dhcp_create_msg(): could not allocate pbuf\n"));
return NULL;
80185b6: 2300 movs r3, #0
80185b8: e098 b.n 80186ec <dhcp_create_msg+0x18c>
}
LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
80185ba: 69bb ldr r3, [r7, #24]
80185bc: 895b ldrh r3, [r3, #10]
80185be: f5b3 7f9a cmp.w r3, #308 ; 0x134
80185c2: d206 bcs.n 80185d2 <dhcp_create_msg+0x72>
80185c4: 4b4b ldr r3, [pc, #300] ; (80186f4 <dhcp_create_msg+0x194>)
80185c6: f240 7272 movw r2, #1906 ; 0x772
80185ca: 494e ldr r1, [pc, #312] ; (8018704 <dhcp_create_msg+0x1a4>)
80185cc: 484b ldr r0, [pc, #300] ; (80186fc <dhcp_create_msg+0x19c>)
80185ce: f002 fd29 bl 801b024 <iprintf>
(p_out->len >= sizeof(struct dhcp_msg)));
/* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) {
80185d2: 79fb ldrb r3, [r7, #7]
80185d4: 2b03 cmp r3, #3
80185d6: d103 bne.n 80185e0 <dhcp_create_msg+0x80>
80185d8: 68bb ldr r3, [r7, #8]
80185da: 795b ldrb r3, [r3, #5]
80185dc: 2b03 cmp r3, #3
80185de: d10d bne.n 80185fc <dhcp_create_msg+0x9c>
/* reuse transaction identifier in retransmissions */
if (dhcp->tries == 0) {
80185e0: 68bb ldr r3, [r7, #8]
80185e2: 799b ldrb r3, [r3, #6]
80185e4: 2b00 cmp r3, #0
80185e6: d105 bne.n 80185f4 <dhcp_create_msg+0x94>
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
xid = LWIP_RAND();
80185e8: f002 fd34 bl 801b054 <rand>
80185ec: 4603 mov r3, r0
80185ee: 461a mov r2, r3
80185f0: 4b45 ldr r3, [pc, #276] ; (8018708 <dhcp_create_msg+0x1a8>)
80185f2: 601a str r2, [r3, #0]
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
xid++;
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
}
dhcp->xid = xid;
80185f4: 4b44 ldr r3, [pc, #272] ; (8018708 <dhcp_create_msg+0x1a8>)
80185f6: 681a ldr r2, [r3, #0]
80185f8: 68bb ldr r3, [r7, #8]
80185fa: 601a str r2, [r3, #0]
}
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
("transaction id xid(%"X32_F")\n", xid));
msg_out = (struct dhcp_msg *)p_out->payload;
80185fc: 69bb ldr r3, [r7, #24]
80185fe: 685b ldr r3, [r3, #4]
8018600: 617b str r3, [r7, #20]
memset(msg_out, 0, sizeof(struct dhcp_msg));
8018602: f44f 729a mov.w r2, #308 ; 0x134
8018606: 2100 movs r1, #0
8018608: 6978 ldr r0, [r7, #20]
801860a: f002 fd03 bl 801b014 <memset>
msg_out->op = DHCP_BOOTREQUEST;
801860e: 697b ldr r3, [r7, #20]
8018610: 2201 movs r2, #1
8018612: 701a strb r2, [r3, #0]
/* @todo: make link layer independent */
msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET;
8018614: 697b ldr r3, [r7, #20]
8018616: 2201 movs r2, #1
8018618: 705a strb r2, [r3, #1]
msg_out->hlen = netif->hwaddr_len;
801861a: 68fb ldr r3, [r7, #12]
801861c: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
8018620: 697b ldr r3, [r7, #20]
8018622: 709a strb r2, [r3, #2]
msg_out->xid = lwip_htonl(dhcp->xid);
8018624: 68bb ldr r3, [r7, #8]
8018626: 681b ldr r3, [r3, #0]
8018628: 4618 mov r0, r3
801862a: f7f6 fc46 bl 800eeba <lwip_htonl>
801862e: 4602 mov r2, r0
8018630: 697b ldr r3, [r7, #20]
8018632: 605a str r2, [r3, #4]
/* we don't need the broadcast flag since we can receive unicast traffic
before being fully configured! */
/* set ciaddr to netif->ip_addr based on message_type and state */
if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
8018634: 79fb ldrb r3, [r7, #7]
8018636: 2b08 cmp r3, #8
8018638: d010 beq.n 801865c <dhcp_create_msg+0xfc>
801863a: 79fb ldrb r3, [r7, #7]
801863c: 2b04 cmp r3, #4
801863e: d00d beq.n 801865c <dhcp_create_msg+0xfc>
8018640: 79fb ldrb r3, [r7, #7]
8018642: 2b07 cmp r3, #7
8018644: d00a beq.n 801865c <dhcp_create_msg+0xfc>
8018646: 79fb ldrb r3, [r7, #7]
8018648: 2b03 cmp r3, #3
801864a: d10c bne.n 8018666 <dhcp_create_msg+0x106>
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
801864c: 68bb ldr r3, [r7, #8]
801864e: 795b ldrb r3, [r3, #5]
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
8018650: 2b05 cmp r3, #5
8018652: d003 beq.n 801865c <dhcp_create_msg+0xfc>
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
8018654: 68bb ldr r3, [r7, #8]
8018656: 795b ldrb r3, [r3, #5]
8018658: 2b04 cmp r3, #4
801865a: d104 bne.n 8018666 <dhcp_create_msg+0x106>
ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif));
801865c: 68fb ldr r3, [r7, #12]
801865e: 3304 adds r3, #4
8018660: 681a ldr r2, [r3, #0]
8018662: 697b ldr r3, [r7, #20]
8018664: 60da str r2, [r3, #12]
}
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018666: 2300 movs r3, #0
8018668: 83fb strh r3, [r7, #30]
801866a: e00c b.n 8018686 <dhcp_create_msg+0x126>
/* copy netif hardware address (padded with zeroes through memset already) */
msg_out->chaddr[i] = netif->hwaddr[i];
801866c: 8bfa ldrh r2, [r7, #30]
801866e: 8bfb ldrh r3, [r7, #30]
8018670: 68f9 ldr r1, [r7, #12]
8018672: 440a add r2, r1
8018674: f892 102a ldrb.w r1, [r2, #42] ; 0x2a
8018678: 697a ldr r2, [r7, #20]
801867a: 4413 add r3, r2
801867c: 460a mov r2, r1
801867e: 771a strb r2, [r3, #28]
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
8018680: 8bfb ldrh r3, [r7, #30]
8018682: 3301 adds r3, #1
8018684: 83fb strh r3, [r7, #30]
8018686: 8bfb ldrh r3, [r7, #30]
8018688: 2b05 cmp r3, #5
801868a: d9ef bls.n 801866c <dhcp_create_msg+0x10c>
}
msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
801868c: 697b ldr r3, [r7, #20]
801868e: 2200 movs r2, #0
8018690: f042 0263 orr.w r2, r2, #99 ; 0x63
8018694: f883 20ec strb.w r2, [r3, #236] ; 0xec
8018698: 2200 movs r2, #0
801869a: f062 027d orn r2, r2, #125 ; 0x7d
801869e: f883 20ed strb.w r2, [r3, #237] ; 0xed
80186a2: 2200 movs r2, #0
80186a4: f042 0253 orr.w r2, r2, #83 ; 0x53
80186a8: f883 20ee strb.w r2, [r3, #238] ; 0xee
80186ac: 2200 movs r2, #0
80186ae: f042 0263 orr.w r2, r2, #99 ; 0x63
80186b2: f883 20ef strb.w r2, [r3, #239] ; 0xef
/* Add option MESSAGE_TYPE */
options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
80186b6: 697b ldr r3, [r7, #20]
80186b8: f103 01f0 add.w r1, r3, #240 ; 0xf0
80186bc: 2301 movs r3, #1
80186be: 2235 movs r2, #53 ; 0x35
80186c0: 2000 movs r0, #0
80186c2: f7ff fadd bl 8017c80 <dhcp_option>
80186c6: 4603 mov r3, r0
80186c8: 827b strh r3, [r7, #18]
options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type);
80186ca: 697b ldr r3, [r7, #20]
80186cc: f103 01f0 add.w r1, r3, #240 ; 0xf0
80186d0: 79fa ldrb r2, [r7, #7]
80186d2: 8a7b ldrh r3, [r7, #18]
80186d4: 4618 mov r0, r3
80186d6: f7ff fb07 bl 8017ce8 <dhcp_option_byte>
80186da: 4603 mov r3, r0
80186dc: 827b strh r3, [r7, #18]
if (options_out_len) {
80186de: 683b ldr r3, [r7, #0]
80186e0: 2b00 cmp r3, #0
80186e2: d002 beq.n 80186ea <dhcp_create_msg+0x18a>
*options_out_len = options_out_len_loc;
80186e4: 683b ldr r3, [r7, #0]
80186e6: 8a7a ldrh r2, [r7, #18]
80186e8: 801a strh r2, [r3, #0]
}
return p_out;
80186ea: 69bb ldr r3, [r7, #24]
}
80186ec: 4618 mov r0, r3
80186ee: 3720 adds r7, #32
80186f0: 46bd mov sp, r7
80186f2: bd80 pop {r7, pc}
80186f4: 0801e3a8 .word 0x0801e3a8
80186f8: 0801e6c8 .word 0x0801e6c8
80186fc: 0801e408 .word 0x0801e408
8018700: 0801e6e8 .word 0x0801e6e8
8018704: 0801e708 .word 0x0801e708
8018708: 20008774 .word 0x20008774
0801870c <dhcp_option_trailer>:
* Adds the END option to the DHCP message, and if
* necessary, up to three padding bytes.
*/
static void
dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out)
{
801870c: b580 push {r7, lr}
801870e: b084 sub sp, #16
8018710: af00 add r7, sp, #0
8018712: 4603 mov r3, r0
8018714: 60b9 str r1, [r7, #8]
8018716: 607a str r2, [r7, #4]
8018718: 81fb strh r3, [r7, #14]
options[options_out_len++] = DHCP_OPTION_END;
801871a: 89fb ldrh r3, [r7, #14]
801871c: 1c5a adds r2, r3, #1
801871e: 81fa strh r2, [r7, #14]
8018720: 461a mov r2, r3
8018722: 68bb ldr r3, [r7, #8]
8018724: 4413 add r3, r2
8018726: 22ff movs r2, #255 ; 0xff
8018728: 701a strb r2, [r3, #0]
/* packet is too small, or not 4 byte aligned? */
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
801872a: e007 b.n 801873c <dhcp_option_trailer+0x30>
(options_out_len < DHCP_OPTIONS_LEN)) {
/* add a fill/padding byte */
options[options_out_len++] = 0;
801872c: 89fb ldrh r3, [r7, #14]
801872e: 1c5a adds r2, r3, #1
8018730: 81fa strh r2, [r7, #14]
8018732: 461a mov r2, r3
8018734: 68bb ldr r3, [r7, #8]
8018736: 4413 add r3, r2
8018738: 2200 movs r2, #0
801873a: 701a strb r2, [r3, #0]
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
801873c: 89fb ldrh r3, [r7, #14]
801873e: 2b43 cmp r3, #67 ; 0x43
8018740: d904 bls.n 801874c <dhcp_option_trailer+0x40>
8018742: 89fb ldrh r3, [r7, #14]
8018744: f003 0303 and.w r3, r3, #3
8018748: 2b00 cmp r3, #0
801874a: d002 beq.n 8018752 <dhcp_option_trailer+0x46>
801874c: 89fb ldrh r3, [r7, #14]
801874e: 2b43 cmp r3, #67 ; 0x43
8018750: d9ec bls.n 801872c <dhcp_option_trailer+0x20>
}
/* shrink the pbuf to the actual content length */
pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len));
8018752: 89fb ldrh r3, [r7, #14]
8018754: 33f0 adds r3, #240 ; 0xf0
8018756: b29b uxth r3, r3
8018758: 4619 mov r1, r3
801875a: 6878 ldr r0, [r7, #4]
801875c: f7f7 fdc6 bl 80102ec <pbuf_realloc>
}
8018760: bf00 nop
8018762: 3710 adds r7, #16
8018764: 46bd mov sp, r7
8018766: bd80 pop {r7, pc}
08018768 <dhcp_supplied_address>:
* @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
* 0 otherwise
*/
u8_t
dhcp_supplied_address(const struct netif *netif)
{
8018768: b480 push {r7}
801876a: b085 sub sp, #20
801876c: af00 add r7, sp, #0
801876e: 6078 str r0, [r7, #4]
if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) {
8018770: 687b ldr r3, [r7, #4]
8018772: 2b00 cmp r3, #0
8018774: d017 beq.n 80187a6 <dhcp_supplied_address+0x3e>
8018776: 687b ldr r3, [r7, #4]
8018778: 6a5b ldr r3, [r3, #36] ; 0x24
801877a: 2b00 cmp r3, #0
801877c: d013 beq.n 80187a6 <dhcp_supplied_address+0x3e>
struct dhcp *dhcp = netif_dhcp_data(netif);
801877e: 687b ldr r3, [r7, #4]
8018780: 6a5b ldr r3, [r3, #36] ; 0x24
8018782: 60fb str r3, [r7, #12]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018784: 68fb ldr r3, [r7, #12]
8018786: 795b ldrb r3, [r3, #5]
8018788: 2b0a cmp r3, #10
801878a: d007 beq.n 801879c <dhcp_supplied_address+0x34>
801878c: 68fb ldr r3, [r7, #12]
801878e: 795b ldrb r3, [r3, #5]
8018790: 2b05 cmp r3, #5
8018792: d003 beq.n 801879c <dhcp_supplied_address+0x34>
(dhcp->state == DHCP_STATE_REBINDING);
8018794: 68fb ldr r3, [r7, #12]
8018796: 795b ldrb r3, [r3, #5]
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
8018798: 2b04 cmp r3, #4
801879a: d101 bne.n 80187a0 <dhcp_supplied_address+0x38>
801879c: 2301 movs r3, #1
801879e: e000 b.n 80187a2 <dhcp_supplied_address+0x3a>
80187a0: 2300 movs r3, #0
80187a2: b2db uxtb r3, r3
80187a4: e000 b.n 80187a8 <dhcp_supplied_address+0x40>
}
return 0;
80187a6: 2300 movs r3, #0
}
80187a8: 4618 mov r0, r3
80187aa: 3714 adds r7, #20
80187ac: 46bd mov sp, r7
80187ae: f85d 7b04 ldr.w r7, [sp], #4
80187b2: 4770 bx lr
080187b4 <etharp_free_entry>:
#endif /* ARP_QUEUEING */
/** Clean up ARP table entries */
static void
etharp_free_entry(int i)
{
80187b4: b580 push {r7, lr}
80187b6: b082 sub sp, #8
80187b8: af00 add r7, sp, #0
80187ba: 6078 str r0, [r7, #4]
/* remove from SNMP ARP index tree */
mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
/* and empty packet queue */
if (arp_table[i].q != NULL) {
80187bc: 4915 ldr r1, [pc, #84] ; (8018814 <etharp_free_entry+0x60>)
80187be: 687a ldr r2, [r7, #4]
80187c0: 4613 mov r3, r2
80187c2: 005b lsls r3, r3, #1
80187c4: 4413 add r3, r2
80187c6: 00db lsls r3, r3, #3
80187c8: 440b add r3, r1
80187ca: 681b ldr r3, [r3, #0]
80187cc: 2b00 cmp r3, #0
80187ce: d013 beq.n 80187f8 <etharp_free_entry+0x44>
/* remove all queued packets */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
free_etharp_q(arp_table[i].q);
80187d0: 4910 ldr r1, [pc, #64] ; (8018814 <etharp_free_entry+0x60>)
80187d2: 687a ldr r2, [r7, #4]
80187d4: 4613 mov r3, r2
80187d6: 005b lsls r3, r3, #1
80187d8: 4413 add r3, r2
80187da: 00db lsls r3, r3, #3
80187dc: 440b add r3, r1
80187de: 681b ldr r3, [r3, #0]
80187e0: 4618 mov r0, r3
80187e2: f7f7 ff09 bl 80105f8 <pbuf_free>
arp_table[i].q = NULL;
80187e6: 490b ldr r1, [pc, #44] ; (8018814 <etharp_free_entry+0x60>)
80187e8: 687a ldr r2, [r7, #4]
80187ea: 4613 mov r3, r2
80187ec: 005b lsls r3, r3, #1
80187ee: 4413 add r3, r2
80187f0: 00db lsls r3, r3, #3
80187f2: 440b add r3, r1
80187f4: 2200 movs r2, #0
80187f6: 601a str r2, [r3, #0]
}
/* recycle entry for re-use */
arp_table[i].state = ETHARP_STATE_EMPTY;
80187f8: 4906 ldr r1, [pc, #24] ; (8018814 <etharp_free_entry+0x60>)
80187fa: 687a ldr r2, [r7, #4]
80187fc: 4613 mov r3, r2
80187fe: 005b lsls r3, r3, #1
8018800: 4413 add r3, r2
8018802: 00db lsls r3, r3, #3
8018804: 440b add r3, r1
8018806: 3314 adds r3, #20
8018808: 2200 movs r2, #0
801880a: 701a strb r2, [r3, #0]
arp_table[i].ctime = 0;
arp_table[i].netif = NULL;
ip4_addr_set_zero(&arp_table[i].ipaddr);
arp_table[i].ethaddr = ethzero;
#endif /* LWIP_DEBUG */
}
801880c: bf00 nop
801880e: 3708 adds r7, #8
8018810: 46bd mov sp, r7
8018812: bd80 pop {r7, pc}
8018814: 20008778 .word 0x20008778
08018818 <etharp_tmr>:
* This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
* in order to expire entries in the ARP table.
*/
void
etharp_tmr(void)
{
8018818: b580 push {r7, lr}
801881a: b082 sub sp, #8
801881c: af00 add r7, sp, #0
int i;
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
/* remove expired entries from the ARP table */
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
801881e: 2300 movs r3, #0
8018820: 607b str r3, [r7, #4]
8018822: e096 b.n 8018952 <etharp_tmr+0x13a>
u8_t state = arp_table[i].state;
8018824: 494f ldr r1, [pc, #316] ; (8018964 <etharp_tmr+0x14c>)
8018826: 687a ldr r2, [r7, #4]
8018828: 4613 mov r3, r2
801882a: 005b lsls r3, r3, #1
801882c: 4413 add r3, r2
801882e: 00db lsls r3, r3, #3
8018830: 440b add r3, r1
8018832: 3314 adds r3, #20
8018834: 781b ldrb r3, [r3, #0]
8018836: 70fb strb r3, [r7, #3]
if (state != ETHARP_STATE_EMPTY
8018838: 78fb ldrb r3, [r7, #3]
801883a: 2b00 cmp r3, #0
801883c: f000 8086 beq.w 801894c <etharp_tmr+0x134>
#if ETHARP_SUPPORT_STATIC_ENTRIES
&& (state != ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
) {
arp_table[i].ctime++;
8018840: 4948 ldr r1, [pc, #288] ; (8018964 <etharp_tmr+0x14c>)
8018842: 687a ldr r2, [r7, #4]
8018844: 4613 mov r3, r2
8018846: 005b lsls r3, r3, #1
8018848: 4413 add r3, r2
801884a: 00db lsls r3, r3, #3
801884c: 440b add r3, r1
801884e: 3312 adds r3, #18
8018850: 881b ldrh r3, [r3, #0]
8018852: 3301 adds r3, #1
8018854: b298 uxth r0, r3
8018856: 4943 ldr r1, [pc, #268] ; (8018964 <etharp_tmr+0x14c>)
8018858: 687a ldr r2, [r7, #4]
801885a: 4613 mov r3, r2
801885c: 005b lsls r3, r3, #1
801885e: 4413 add r3, r2
8018860: 00db lsls r3, r3, #3
8018862: 440b add r3, r1
8018864: 3312 adds r3, #18
8018866: 4602 mov r2, r0
8018868: 801a strh r2, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
801886a: 493e ldr r1, [pc, #248] ; (8018964 <etharp_tmr+0x14c>)
801886c: 687a ldr r2, [r7, #4]
801886e: 4613 mov r3, r2
8018870: 005b lsls r3, r3, #1
8018872: 4413 add r3, r2
8018874: 00db lsls r3, r3, #3
8018876: 440b add r3, r1
8018878: 3312 adds r3, #18
801887a: 881b ldrh r3, [r3, #0]
801887c: f5b3 7f96 cmp.w r3, #300 ; 0x12c
8018880: d215 bcs.n 80188ae <etharp_tmr+0x96>
((arp_table[i].state == ETHARP_STATE_PENDING) &&
8018882: 4938 ldr r1, [pc, #224] ; (8018964 <etharp_tmr+0x14c>)
8018884: 687a ldr r2, [r7, #4]
8018886: 4613 mov r3, r2
8018888: 005b lsls r3, r3, #1
801888a: 4413 add r3, r2
801888c: 00db lsls r3, r3, #3
801888e: 440b add r3, r1
8018890: 3314 adds r3, #20
8018892: 781b ldrb r3, [r3, #0]
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
8018894: 2b01 cmp r3, #1
8018896: d10e bne.n 80188b6 <etharp_tmr+0x9e>
(arp_table[i].ctime >= ARP_MAXPENDING))) {
8018898: 4932 ldr r1, [pc, #200] ; (8018964 <etharp_tmr+0x14c>)
801889a: 687a ldr r2, [r7, #4]
801889c: 4613 mov r3, r2
801889e: 005b lsls r3, r3, #1
80188a0: 4413 add r3, r2
80188a2: 00db lsls r3, r3, #3
80188a4: 440b add r3, r1
80188a6: 3312 adds r3, #18
80188a8: 881b ldrh r3, [r3, #0]
((arp_table[i].state == ETHARP_STATE_PENDING) &&
80188aa: 2b04 cmp r3, #4
80188ac: d903 bls.n 80188b6 <etharp_tmr+0x9e>
/* pending or stable entry has become old! */
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
/* clean up entries that have just been expired */
etharp_free_entry(i);
80188ae: 6878 ldr r0, [r7, #4]
80188b0: f7ff ff80 bl 80187b4 <etharp_free_entry>
80188b4: e04a b.n 801894c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
80188b6: 492b ldr r1, [pc, #172] ; (8018964 <etharp_tmr+0x14c>)
80188b8: 687a ldr r2, [r7, #4]
80188ba: 4613 mov r3, r2
80188bc: 005b lsls r3, r3, #1
80188be: 4413 add r3, r2
80188c0: 00db lsls r3, r3, #3
80188c2: 440b add r3, r1
80188c4: 3314 adds r3, #20
80188c6: 781b ldrb r3, [r3, #0]
80188c8: 2b03 cmp r3, #3
80188ca: d10a bne.n 80188e2 <etharp_tmr+0xca>
/* Don't send more than one request every 2 seconds. */
arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
80188cc: 4925 ldr r1, [pc, #148] ; (8018964 <etharp_tmr+0x14c>)
80188ce: 687a ldr r2, [r7, #4]
80188d0: 4613 mov r3, r2
80188d2: 005b lsls r3, r3, #1
80188d4: 4413 add r3, r2
80188d6: 00db lsls r3, r3, #3
80188d8: 440b add r3, r1
80188da: 3314 adds r3, #20
80188dc: 2204 movs r2, #4
80188de: 701a strb r2, [r3, #0]
80188e0: e034 b.n 801894c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
80188e2: 4920 ldr r1, [pc, #128] ; (8018964 <etharp_tmr+0x14c>)
80188e4: 687a ldr r2, [r7, #4]
80188e6: 4613 mov r3, r2
80188e8: 005b lsls r3, r3, #1
80188ea: 4413 add r3, r2
80188ec: 00db lsls r3, r3, #3
80188ee: 440b add r3, r1
80188f0: 3314 adds r3, #20
80188f2: 781b ldrb r3, [r3, #0]
80188f4: 2b04 cmp r3, #4
80188f6: d10a bne.n 801890e <etharp_tmr+0xf6>
/* Reset state to stable, so that the next transmitted packet will
re-send an ARP request. */
arp_table[i].state = ETHARP_STATE_STABLE;
80188f8: 491a ldr r1, [pc, #104] ; (8018964 <etharp_tmr+0x14c>)
80188fa: 687a ldr r2, [r7, #4]
80188fc: 4613 mov r3, r2
80188fe: 005b lsls r3, r3, #1
8018900: 4413 add r3, r2
8018902: 00db lsls r3, r3, #3
8018904: 440b add r3, r1
8018906: 3314 adds r3, #20
8018908: 2202 movs r2, #2
801890a: 701a strb r2, [r3, #0]
801890c: e01e b.n 801894c <etharp_tmr+0x134>
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
801890e: 4915 ldr r1, [pc, #84] ; (8018964 <etharp_tmr+0x14c>)
8018910: 687a ldr r2, [r7, #4]
8018912: 4613 mov r3, r2
8018914: 005b lsls r3, r3, #1
8018916: 4413 add r3, r2
8018918: 00db lsls r3, r3, #3
801891a: 440b add r3, r1
801891c: 3314 adds r3, #20
801891e: 781b ldrb r3, [r3, #0]
8018920: 2b01 cmp r3, #1
8018922: d113 bne.n 801894c <etharp_tmr+0x134>
/* still pending, resend an ARP query */
etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
8018924: 490f ldr r1, [pc, #60] ; (8018964 <etharp_tmr+0x14c>)
8018926: 687a ldr r2, [r7, #4]
8018928: 4613 mov r3, r2
801892a: 005b lsls r3, r3, #1
801892c: 4413 add r3, r2
801892e: 00db lsls r3, r3, #3
8018930: 440b add r3, r1
8018932: 3308 adds r3, #8
8018934: 6818 ldr r0, [r3, #0]
8018936: 687a ldr r2, [r7, #4]
8018938: 4613 mov r3, r2
801893a: 005b lsls r3, r3, #1
801893c: 4413 add r3, r2
801893e: 00db lsls r3, r3, #3
8018940: 4a08 ldr r2, [pc, #32] ; (8018964 <etharp_tmr+0x14c>)
8018942: 4413 add r3, r2
8018944: 3304 adds r3, #4
8018946: 4619 mov r1, r3
8018948: f000 fe72 bl 8019630 <etharp_request>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
801894c: 687b ldr r3, [r7, #4]
801894e: 3301 adds r3, #1
8018950: 607b str r3, [r7, #4]
8018952: 687b ldr r3, [r7, #4]
8018954: 2b09 cmp r3, #9
8018956: f77f af65 ble.w 8018824 <etharp_tmr+0xc>
}
}
}
}
801895a: bf00 nop
801895c: 3708 adds r7, #8
801895e: 46bd mov sp, r7
8018960: bd80 pop {r7, pc}
8018962: bf00 nop
8018964: 20008778 .word 0x20008778
08018968 <etharp_find_entry>:
* @return The ARP entry index that matched or is created, ERR_MEM if no
* entry is found or could be recycled.
*/
static s16_t
etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
{
8018968: b580 push {r7, lr}
801896a: b08a sub sp, #40 ; 0x28
801896c: af00 add r7, sp, #0
801896e: 60f8 str r0, [r7, #12]
8018970: 460b mov r3, r1
8018972: 607a str r2, [r7, #4]
8018974: 72fb strb r3, [r7, #11]
s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
8018976: 230a movs r3, #10
8018978: 84fb strh r3, [r7, #38] ; 0x26
801897a: 230a movs r3, #10
801897c: 84bb strh r3, [r7, #36] ; 0x24
s16_t empty = ARP_TABLE_SIZE;
801897e: 230a movs r3, #10
8018980: 847b strh r3, [r7, #34] ; 0x22
s16_t i = 0;
8018982: 2300 movs r3, #0
8018984: 843b strh r3, [r7, #32]
/* oldest entry with packets on queue */
s16_t old_queue = ARP_TABLE_SIZE;
8018986: 230a movs r3, #10
8018988: 83fb strh r3, [r7, #30]
/* its age */
u16_t age_queue = 0, age_pending = 0, age_stable = 0;
801898a: 2300 movs r3, #0
801898c: 83bb strh r3, [r7, #28]
801898e: 2300 movs r3, #0
8018990: 837b strh r3, [r7, #26]
8018992: 2300 movs r3, #0
8018994: 833b strh r3, [r7, #24]
* 4) remember the oldest pending entry with queued packets (if any)
* 5) search for a matching IP entry, either pending or stable
* until 5 matches, or all entries are searched for.
*/
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018996: 2300 movs r3, #0
8018998: 843b strh r3, [r7, #32]
801899a: e0ae b.n 8018afa <etharp_find_entry+0x192>
u8_t state = arp_table[i].state;
801899c: f9b7 2020 ldrsh.w r2, [r7, #32]
80189a0: 49a6 ldr r1, [pc, #664] ; (8018c3c <etharp_find_entry+0x2d4>)
80189a2: 4613 mov r3, r2
80189a4: 005b lsls r3, r3, #1
80189a6: 4413 add r3, r2
80189a8: 00db lsls r3, r3, #3
80189aa: 440b add r3, r1
80189ac: 3314 adds r3, #20
80189ae: 781b ldrb r3, [r3, #0]
80189b0: 75fb strb r3, [r7, #23]
/* no empty entry found yet and now we do find one? */
if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
80189b2: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
80189b6: 2b0a cmp r3, #10
80189b8: d105 bne.n 80189c6 <etharp_find_entry+0x5e>
80189ba: 7dfb ldrb r3, [r7, #23]
80189bc: 2b00 cmp r3, #0
80189be: d102 bne.n 80189c6 <etharp_find_entry+0x5e>
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
/* remember first empty entry */
empty = i;
80189c0: 8c3b ldrh r3, [r7, #32]
80189c2: 847b strh r3, [r7, #34] ; 0x22
80189c4: e095 b.n 8018af2 <etharp_find_entry+0x18a>
} else if (state != ETHARP_STATE_EMPTY) {
80189c6: 7dfb ldrb r3, [r7, #23]
80189c8: 2b00 cmp r3, #0
80189ca: f000 8092 beq.w 8018af2 <etharp_find_entry+0x18a>
LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
80189ce: 7dfb ldrb r3, [r7, #23]
80189d0: 2b01 cmp r3, #1
80189d2: d009 beq.n 80189e8 <etharp_find_entry+0x80>
80189d4: 7dfb ldrb r3, [r7, #23]
80189d6: 2b01 cmp r3, #1
80189d8: d806 bhi.n 80189e8 <etharp_find_entry+0x80>
80189da: 4b99 ldr r3, [pc, #612] ; (8018c40 <etharp_find_entry+0x2d8>)
80189dc: f44f 7292 mov.w r2, #292 ; 0x124
80189e0: 4998 ldr r1, [pc, #608] ; (8018c44 <etharp_find_entry+0x2dc>)
80189e2: 4899 ldr r0, [pc, #612] ; (8018c48 <etharp_find_entry+0x2e0>)
80189e4: f002 fb1e bl 801b024 <iprintf>
state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
/* if given, does IP address match IP address in ARP entry? */
if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
80189e8: 68fb ldr r3, [r7, #12]
80189ea: 2b00 cmp r3, #0
80189ec: d020 beq.n 8018a30 <etharp_find_entry+0xc8>
80189ee: 68fb ldr r3, [r7, #12]
80189f0: 6819 ldr r1, [r3, #0]
80189f2: f9b7 2020 ldrsh.w r2, [r7, #32]
80189f6: 4891 ldr r0, [pc, #580] ; (8018c3c <etharp_find_entry+0x2d4>)
80189f8: 4613 mov r3, r2
80189fa: 005b lsls r3, r3, #1
80189fc: 4413 add r3, r2
80189fe: 00db lsls r3, r3, #3
8018a00: 4403 add r3, r0
8018a02: 3304 adds r3, #4
8018a04: 681b ldr r3, [r3, #0]
8018a06: 4299 cmp r1, r3
8018a08: d112 bne.n 8018a30 <etharp_find_entry+0xc8>
#if ETHARP_TABLE_MATCH_NETIF
&& ((netif == NULL) || (netif == arp_table[i].netif))
8018a0a: 687b ldr r3, [r7, #4]
8018a0c: 2b00 cmp r3, #0
8018a0e: d00c beq.n 8018a2a <etharp_find_entry+0xc2>
8018a10: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a14: 4989 ldr r1, [pc, #548] ; (8018c3c <etharp_find_entry+0x2d4>)
8018a16: 4613 mov r3, r2
8018a18: 005b lsls r3, r3, #1
8018a1a: 4413 add r3, r2
8018a1c: 00db lsls r3, r3, #3
8018a1e: 440b add r3, r1
8018a20: 3308 adds r3, #8
8018a22: 681b ldr r3, [r3, #0]
8018a24: 687a ldr r2, [r7, #4]
8018a26: 429a cmp r2, r3
8018a28: d102 bne.n 8018a30 <etharp_find_entry+0xc8>
#endif /* ETHARP_TABLE_MATCH_NETIF */
) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
/* found exact IP address match, simply bail out */
return i;
8018a2a: f9b7 3020 ldrsh.w r3, [r7, #32]
8018a2e: e100 b.n 8018c32 <etharp_find_entry+0x2ca>
}
/* pending entry? */
if (state == ETHARP_STATE_PENDING) {
8018a30: 7dfb ldrb r3, [r7, #23]
8018a32: 2b01 cmp r3, #1
8018a34: d140 bne.n 8018ab8 <etharp_find_entry+0x150>
/* pending with queued packets? */
if (arp_table[i].q != NULL) {
8018a36: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a3a: 4980 ldr r1, [pc, #512] ; (8018c3c <etharp_find_entry+0x2d4>)
8018a3c: 4613 mov r3, r2
8018a3e: 005b lsls r3, r3, #1
8018a40: 4413 add r3, r2
8018a42: 00db lsls r3, r3, #3
8018a44: 440b add r3, r1
8018a46: 681b ldr r3, [r3, #0]
8018a48: 2b00 cmp r3, #0
8018a4a: d01a beq.n 8018a82 <etharp_find_entry+0x11a>
if (arp_table[i].ctime >= age_queue) {
8018a4c: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a50: 497a ldr r1, [pc, #488] ; (8018c3c <etharp_find_entry+0x2d4>)
8018a52: 4613 mov r3, r2
8018a54: 005b lsls r3, r3, #1
8018a56: 4413 add r3, r2
8018a58: 00db lsls r3, r3, #3
8018a5a: 440b add r3, r1
8018a5c: 3312 adds r3, #18
8018a5e: 881b ldrh r3, [r3, #0]
8018a60: 8bba ldrh r2, [r7, #28]
8018a62: 429a cmp r2, r3
8018a64: d845 bhi.n 8018af2 <etharp_find_entry+0x18a>
old_queue = i;
8018a66: 8c3b ldrh r3, [r7, #32]
8018a68: 83fb strh r3, [r7, #30]
age_queue = arp_table[i].ctime;
8018a6a: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a6e: 4973 ldr r1, [pc, #460] ; (8018c3c <etharp_find_entry+0x2d4>)
8018a70: 4613 mov r3, r2
8018a72: 005b lsls r3, r3, #1
8018a74: 4413 add r3, r2
8018a76: 00db lsls r3, r3, #3
8018a78: 440b add r3, r1
8018a7a: 3312 adds r3, #18
8018a7c: 881b ldrh r3, [r3, #0]
8018a7e: 83bb strh r3, [r7, #28]
8018a80: e037 b.n 8018af2 <etharp_find_entry+0x18a>
}
} else
/* pending without queued packets? */
{
if (arp_table[i].ctime >= age_pending) {
8018a82: f9b7 2020 ldrsh.w r2, [r7, #32]
8018a86: 496d ldr r1, [pc, #436] ; (8018c3c <etharp_find_entry+0x2d4>)
8018a88: 4613 mov r3, r2
8018a8a: 005b lsls r3, r3, #1
8018a8c: 4413 add r3, r2
8018a8e: 00db lsls r3, r3, #3
8018a90: 440b add r3, r1
8018a92: 3312 adds r3, #18
8018a94: 881b ldrh r3, [r3, #0]
8018a96: 8b7a ldrh r2, [r7, #26]
8018a98: 429a cmp r2, r3
8018a9a: d82a bhi.n 8018af2 <etharp_find_entry+0x18a>
old_pending = i;
8018a9c: 8c3b ldrh r3, [r7, #32]
8018a9e: 84fb strh r3, [r7, #38] ; 0x26
age_pending = arp_table[i].ctime;
8018aa0: f9b7 2020 ldrsh.w r2, [r7, #32]
8018aa4: 4965 ldr r1, [pc, #404] ; (8018c3c <etharp_find_entry+0x2d4>)
8018aa6: 4613 mov r3, r2
8018aa8: 005b lsls r3, r3, #1
8018aaa: 4413 add r3, r2
8018aac: 00db lsls r3, r3, #3
8018aae: 440b add r3, r1
8018ab0: 3312 adds r3, #18
8018ab2: 881b ldrh r3, [r3, #0]
8018ab4: 837b strh r3, [r7, #26]
8018ab6: e01c b.n 8018af2 <etharp_find_entry+0x18a>
}
}
/* stable entry? */
} else if (state >= ETHARP_STATE_STABLE) {
8018ab8: 7dfb ldrb r3, [r7, #23]
8018aba: 2b01 cmp r3, #1
8018abc: d919 bls.n 8018af2 <etharp_find_entry+0x18a>
/* don't record old_stable for static entries since they never expire */
if (state < ETHARP_STATE_STATIC)
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* remember entry with oldest stable entry in oldest, its age in maxtime */
if (arp_table[i].ctime >= age_stable) {
8018abe: f9b7 2020 ldrsh.w r2, [r7, #32]
8018ac2: 495e ldr r1, [pc, #376] ; (8018c3c <etharp_find_entry+0x2d4>)
8018ac4: 4613 mov r3, r2
8018ac6: 005b lsls r3, r3, #1
8018ac8: 4413 add r3, r2
8018aca: 00db lsls r3, r3, #3
8018acc: 440b add r3, r1
8018ace: 3312 adds r3, #18
8018ad0: 881b ldrh r3, [r3, #0]
8018ad2: 8b3a ldrh r2, [r7, #24]
8018ad4: 429a cmp r2, r3
8018ad6: d80c bhi.n 8018af2 <etharp_find_entry+0x18a>
old_stable = i;
8018ad8: 8c3b ldrh r3, [r7, #32]
8018ada: 84bb strh r3, [r7, #36] ; 0x24
age_stable = arp_table[i].ctime;
8018adc: f9b7 2020 ldrsh.w r2, [r7, #32]
8018ae0: 4956 ldr r1, [pc, #344] ; (8018c3c <etharp_find_entry+0x2d4>)
8018ae2: 4613 mov r3, r2
8018ae4: 005b lsls r3, r3, #1
8018ae6: 4413 add r3, r2
8018ae8: 00db lsls r3, r3, #3
8018aea: 440b add r3, r1
8018aec: 3312 adds r3, #18
8018aee: 881b ldrh r3, [r3, #0]
8018af0: 833b strh r3, [r7, #24]
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018af2: 8c3b ldrh r3, [r7, #32]
8018af4: 3301 adds r3, #1
8018af6: b29b uxth r3, r3
8018af8: 843b strh r3, [r7, #32]
8018afa: f9b7 3020 ldrsh.w r3, [r7, #32]
8018afe: 2b09 cmp r3, #9
8018b00: f77f af4c ble.w 801899c <etharp_find_entry+0x34>
}
}
/* { we have no match } => try to create a new entry */
/* don't create new entry, only search? */
if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
8018b04: 7afb ldrb r3, [r7, #11]
8018b06: f003 0302 and.w r3, r3, #2
8018b0a: 2b00 cmp r3, #0
8018b0c: d108 bne.n 8018b20 <etharp_find_entry+0x1b8>
8018b0e: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018b12: 2b0a cmp r3, #10
8018b14: d107 bne.n 8018b26 <etharp_find_entry+0x1be>
/* or no empty entry found and not allowed to recycle? */
((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
8018b16: 7afb ldrb r3, [r7, #11]
8018b18: f003 0301 and.w r3, r3, #1
8018b1c: 2b00 cmp r3, #0
8018b1e: d102 bne.n 8018b26 <etharp_find_entry+0x1be>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
return (s16_t)ERR_MEM;
8018b20: f04f 33ff mov.w r3, #4294967295
8018b24: e085 b.n 8018c32 <etharp_find_entry+0x2ca>
*
* { ETHARP_FLAG_TRY_HARD is set at this point }
*/
/* 1) empty entry available? */
if (empty < ARP_TABLE_SIZE) {
8018b26: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
8018b2a: 2b09 cmp r3, #9
8018b2c: dc02 bgt.n 8018b34 <etharp_find_entry+0x1cc>
i = empty;
8018b2e: 8c7b ldrh r3, [r7, #34] ; 0x22
8018b30: 843b strh r3, [r7, #32]
8018b32: e039 b.n 8018ba8 <etharp_find_entry+0x240>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
} else {
/* 2) found recyclable stable entry? */
if (old_stable < ARP_TABLE_SIZE) {
8018b34: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24
8018b38: 2b09 cmp r3, #9
8018b3a: dc14 bgt.n 8018b66 <etharp_find_entry+0x1fe>
/* recycle oldest stable*/
i = old_stable;
8018b3c: 8cbb ldrh r3, [r7, #36] ; 0x24
8018b3e: 843b strh r3, [r7, #32]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
/* no queued packets should exist on stable entries */
LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
8018b40: f9b7 2020 ldrsh.w r2, [r7, #32]
8018b44: 493d ldr r1, [pc, #244] ; (8018c3c <etharp_find_entry+0x2d4>)
8018b46: 4613 mov r3, r2
8018b48: 005b lsls r3, r3, #1
8018b4a: 4413 add r3, r2
8018b4c: 00db lsls r3, r3, #3
8018b4e: 440b add r3, r1
8018b50: 681b ldr r3, [r3, #0]
8018b52: 2b00 cmp r3, #0
8018b54: d018 beq.n 8018b88 <etharp_find_entry+0x220>
8018b56: 4b3a ldr r3, [pc, #232] ; (8018c40 <etharp_find_entry+0x2d8>)
8018b58: f240 126d movw r2, #365 ; 0x16d
8018b5c: 493b ldr r1, [pc, #236] ; (8018c4c <etharp_find_entry+0x2e4>)
8018b5e: 483a ldr r0, [pc, #232] ; (8018c48 <etharp_find_entry+0x2e0>)
8018b60: f002 fa60 bl 801b024 <iprintf>
8018b64: e010 b.n 8018b88 <etharp_find_entry+0x220>
/* 3) found recyclable pending entry without queued packets? */
} else if (old_pending < ARP_TABLE_SIZE) {
8018b66: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26
8018b6a: 2b09 cmp r3, #9
8018b6c: dc02 bgt.n 8018b74 <etharp_find_entry+0x20c>
/* recycle oldest pending */
i = old_pending;
8018b6e: 8cfb ldrh r3, [r7, #38] ; 0x26
8018b70: 843b strh r3, [r7, #32]
8018b72: e009 b.n 8018b88 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
/* 4) found recyclable pending entry with queued packets? */
} else if (old_queue < ARP_TABLE_SIZE) {
8018b74: f9b7 301e ldrsh.w r3, [r7, #30]
8018b78: 2b09 cmp r3, #9
8018b7a: dc02 bgt.n 8018b82 <etharp_find_entry+0x21a>
/* recycle oldest pending (queued packets are free in etharp_free_entry) */
i = old_queue;
8018b7c: 8bfb ldrh r3, [r7, #30]
8018b7e: 843b strh r3, [r7, #32]
8018b80: e002 b.n 8018b88 <etharp_find_entry+0x220>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
/* no empty or recyclable entries found */
} else {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
return (s16_t)ERR_MEM;
8018b82: f04f 33ff mov.w r3, #4294967295
8018b86: e054 b.n 8018c32 <etharp_find_entry+0x2ca>
}
/* { empty or recyclable entry found } */
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018b88: f9b7 3020 ldrsh.w r3, [r7, #32]
8018b8c: 2b09 cmp r3, #9
8018b8e: dd06 ble.n 8018b9e <etharp_find_entry+0x236>
8018b90: 4b2b ldr r3, [pc, #172] ; (8018c40 <etharp_find_entry+0x2d8>)
8018b92: f240 127f movw r2, #383 ; 0x17f
8018b96: 492e ldr r1, [pc, #184] ; (8018c50 <etharp_find_entry+0x2e8>)
8018b98: 482b ldr r0, [pc, #172] ; (8018c48 <etharp_find_entry+0x2e0>)
8018b9a: f002 fa43 bl 801b024 <iprintf>
etharp_free_entry(i);
8018b9e: f9b7 3020 ldrsh.w r3, [r7, #32]
8018ba2: 4618 mov r0, r3
8018ba4: f7ff fe06 bl 80187b4 <etharp_free_entry>
}
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
8018ba8: f9b7 3020 ldrsh.w r3, [r7, #32]
8018bac: 2b09 cmp r3, #9
8018bae: dd06 ble.n 8018bbe <etharp_find_entry+0x256>
8018bb0: 4b23 ldr r3, [pc, #140] ; (8018c40 <etharp_find_entry+0x2d8>)
8018bb2: f240 1283 movw r2, #387 ; 0x183
8018bb6: 4926 ldr r1, [pc, #152] ; (8018c50 <etharp_find_entry+0x2e8>)
8018bb8: 4823 ldr r0, [pc, #140] ; (8018c48 <etharp_find_entry+0x2e0>)
8018bba: f002 fa33 bl 801b024 <iprintf>
LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
8018bbe: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bc2: 491e ldr r1, [pc, #120] ; (8018c3c <etharp_find_entry+0x2d4>)
8018bc4: 4613 mov r3, r2
8018bc6: 005b lsls r3, r3, #1
8018bc8: 4413 add r3, r2
8018bca: 00db lsls r3, r3, #3
8018bcc: 440b add r3, r1
8018bce: 3314 adds r3, #20
8018bd0: 781b ldrb r3, [r3, #0]
8018bd2: 2b00 cmp r3, #0
8018bd4: d006 beq.n 8018be4 <etharp_find_entry+0x27c>
8018bd6: 4b1a ldr r3, [pc, #104] ; (8018c40 <etharp_find_entry+0x2d8>)
8018bd8: f240 1285 movw r2, #389 ; 0x185
8018bdc: 491d ldr r1, [pc, #116] ; (8018c54 <etharp_find_entry+0x2ec>)
8018bde: 481a ldr r0, [pc, #104] ; (8018c48 <etharp_find_entry+0x2e0>)
8018be0: f002 fa20 bl 801b024 <iprintf>
arp_table[i].state == ETHARP_STATE_EMPTY);
/* IP address given? */
if (ipaddr != NULL) {
8018be4: 68fb ldr r3, [r7, #12]
8018be6: 2b00 cmp r3, #0
8018be8: d00b beq.n 8018c02 <etharp_find_entry+0x29a>
/* set IP address */
ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
8018bea: f9b7 2020 ldrsh.w r2, [r7, #32]
8018bee: 68fb ldr r3, [r7, #12]
8018bf0: 6819 ldr r1, [r3, #0]
8018bf2: 4812 ldr r0, [pc, #72] ; (8018c3c <etharp_find_entry+0x2d4>)
8018bf4: 4613 mov r3, r2
8018bf6: 005b lsls r3, r3, #1
8018bf8: 4413 add r3, r2
8018bfa: 00db lsls r3, r3, #3
8018bfc: 4403 add r3, r0
8018bfe: 3304 adds r3, #4
8018c00: 6019 str r1, [r3, #0]
}
arp_table[i].ctime = 0;
8018c02: f9b7 2020 ldrsh.w r2, [r7, #32]
8018c06: 490d ldr r1, [pc, #52] ; (8018c3c <etharp_find_entry+0x2d4>)
8018c08: 4613 mov r3, r2
8018c0a: 005b lsls r3, r3, #1
8018c0c: 4413 add r3, r2
8018c0e: 00db lsls r3, r3, #3
8018c10: 440b add r3, r1
8018c12: 3312 adds r3, #18
8018c14: 2200 movs r2, #0
8018c16: 801a strh r2, [r3, #0]
#if ETHARP_TABLE_MATCH_NETIF
arp_table[i].netif = netif;
8018c18: f9b7 2020 ldrsh.w r2, [r7, #32]
8018c1c: 4907 ldr r1, [pc, #28] ; (8018c3c <etharp_find_entry+0x2d4>)
8018c1e: 4613 mov r3, r2
8018c20: 005b lsls r3, r3, #1
8018c22: 4413 add r3, r2
8018c24: 00db lsls r3, r3, #3
8018c26: 440b add r3, r1
8018c28: 3308 adds r3, #8
8018c2a: 687a ldr r2, [r7, #4]
8018c2c: 601a str r2, [r3, #0]
#endif /* ETHARP_TABLE_MATCH_NETIF */
return (s16_t)i;
8018c2e: f9b7 3020 ldrsh.w r3, [r7, #32]
}
8018c32: 4618 mov r0, r3
8018c34: 3728 adds r7, #40 ; 0x28
8018c36: 46bd mov sp, r7
8018c38: bd80 pop {r7, pc}
8018c3a: bf00 nop
8018c3c: 20008778 .word 0x20008778
8018c40: 0801e748 .word 0x0801e748
8018c44: 0801e780 .word 0x0801e780
8018c48: 0801e7c0 .word 0x0801e7c0
8018c4c: 0801e7e8 .word 0x0801e7e8
8018c50: 0801e800 .word 0x0801e800
8018c54: 0801e814 .word 0x0801e814
08018c58 <etharp_update_arp_entry>:
*
* @see pbuf_free()
*/
static err_t
etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
{
8018c58: b580 push {r7, lr}
8018c5a: b088 sub sp, #32
8018c5c: af02 add r7, sp, #8
8018c5e: 60f8 str r0, [r7, #12]
8018c60: 60b9 str r1, [r7, #8]
8018c62: 607a str r2, [r7, #4]
8018c64: 70fb strb r3, [r7, #3]
s16_t i;
LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
8018c66: 68fb ldr r3, [r7, #12]
8018c68: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8018c6c: 2b06 cmp r3, #6
8018c6e: d006 beq.n 8018c7e <etharp_update_arp_entry+0x26>
8018c70: 4b48 ldr r3, [pc, #288] ; (8018d94 <etharp_update_arp_entry+0x13c>)
8018c72: f240 12a9 movw r2, #425 ; 0x1a9
8018c76: 4948 ldr r1, [pc, #288] ; (8018d98 <etharp_update_arp_entry+0x140>)
8018c78: 4848 ldr r0, [pc, #288] ; (8018d9c <etharp_update_arp_entry+0x144>)
8018c7a: f002 f9d3 bl 801b024 <iprintf>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
(u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
(u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
/* non-unicast address? */
if (ip4_addr_isany(ipaddr) ||
8018c7e: 68bb ldr r3, [r7, #8]
8018c80: 2b00 cmp r3, #0
8018c82: d012 beq.n 8018caa <etharp_update_arp_entry+0x52>
8018c84: 68bb ldr r3, [r7, #8]
8018c86: 681b ldr r3, [r3, #0]
8018c88: 2b00 cmp r3, #0
8018c8a: d00e beq.n 8018caa <etharp_update_arp_entry+0x52>
ip4_addr_isbroadcast(ipaddr, netif) ||
8018c8c: 68bb ldr r3, [r7, #8]
8018c8e: 681b ldr r3, [r3, #0]
8018c90: 68f9 ldr r1, [r7, #12]
8018c92: 4618 mov r0, r3
8018c94: f001 f91e bl 8019ed4 <ip4_addr_isbroadcast_u32>
8018c98: 4603 mov r3, r0
if (ip4_addr_isany(ipaddr) ||
8018c9a: 2b00 cmp r3, #0
8018c9c: d105 bne.n 8018caa <etharp_update_arp_entry+0x52>
ip4_addr_ismulticast(ipaddr)) {
8018c9e: 68bb ldr r3, [r7, #8]
8018ca0: 681b ldr r3, [r3, #0]
8018ca2: f003 03f0 and.w r3, r3, #240 ; 0xf0
ip4_addr_isbroadcast(ipaddr, netif) ||
8018ca6: 2be0 cmp r3, #224 ; 0xe0
8018ca8: d102 bne.n 8018cb0 <etharp_update_arp_entry+0x58>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
8018caa: f06f 030f mvn.w r3, #15
8018cae: e06c b.n 8018d8a <etharp_update_arp_entry+0x132>
}
/* find or create ARP entry */
i = etharp_find_entry(ipaddr, flags, netif);
8018cb0: 78fb ldrb r3, [r7, #3]
8018cb2: 68fa ldr r2, [r7, #12]
8018cb4: 4619 mov r1, r3
8018cb6: 68b8 ldr r0, [r7, #8]
8018cb8: f7ff fe56 bl 8018968 <etharp_find_entry>
8018cbc: 4603 mov r3, r0
8018cbe: 82fb strh r3, [r7, #22]
/* bail out if no entry could be found */
if (i < 0) {
8018cc0: f9b7 3016 ldrsh.w r3, [r7, #22]
8018cc4: 2b00 cmp r3, #0
8018cc6: da02 bge.n 8018cce <etharp_update_arp_entry+0x76>
return (err_t)i;
8018cc8: 8afb ldrh r3, [r7, #22]
8018cca: b25b sxtb r3, r3
8018ccc: e05d b.n 8018d8a <etharp_update_arp_entry+0x132>
return ERR_VAL;
} else
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
{
/* mark it stable */
arp_table[i].state = ETHARP_STATE_STABLE;
8018cce: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cd2: 4933 ldr r1, [pc, #204] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018cd4: 4613 mov r3, r2
8018cd6: 005b lsls r3, r3, #1
8018cd8: 4413 add r3, r2
8018cda: 00db lsls r3, r3, #3
8018cdc: 440b add r3, r1
8018cde: 3314 adds r3, #20
8018ce0: 2202 movs r2, #2
8018ce2: 701a strb r2, [r3, #0]
}
/* record network interface */
arp_table[i].netif = netif;
8018ce4: f9b7 2016 ldrsh.w r2, [r7, #22]
8018ce8: 492d ldr r1, [pc, #180] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018cea: 4613 mov r3, r2
8018cec: 005b lsls r3, r3, #1
8018cee: 4413 add r3, r2
8018cf0: 00db lsls r3, r3, #3
8018cf2: 440b add r3, r1
8018cf4: 3308 adds r3, #8
8018cf6: 68fa ldr r2, [r7, #12]
8018cf8: 601a str r2, [r3, #0]
/* insert in SNMP ARP index tree */
mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
/* update address */
SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
8018cfa: f9b7 2016 ldrsh.w r2, [r7, #22]
8018cfe: 4613 mov r3, r2
8018d00: 005b lsls r3, r3, #1
8018d02: 4413 add r3, r2
8018d04: 00db lsls r3, r3, #3
8018d06: 3308 adds r3, #8
8018d08: 4a25 ldr r2, [pc, #148] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018d0a: 4413 add r3, r2
8018d0c: 3304 adds r3, #4
8018d0e: 2206 movs r2, #6
8018d10: 6879 ldr r1, [r7, #4]
8018d12: 4618 mov r0, r3
8018d14: f002 f973 bl 801affe <memcpy>
/* reset time stamp */
arp_table[i].ctime = 0;
8018d18: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d1c: 4920 ldr r1, [pc, #128] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018d1e: 4613 mov r3, r2
8018d20: 005b lsls r3, r3, #1
8018d22: 4413 add r3, r2
8018d24: 00db lsls r3, r3, #3
8018d26: 440b add r3, r1
8018d28: 3312 adds r3, #18
8018d2a: 2200 movs r2, #0
8018d2c: 801a strh r2, [r3, #0]
/* get the packet pointer */
p = q->p;
/* now queue entry can be freed */
memp_free(MEMP_ARP_QUEUE, q);
#else /* ARP_QUEUEING */
if (arp_table[i].q != NULL) {
8018d2e: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d32: 491b ldr r1, [pc, #108] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018d34: 4613 mov r3, r2
8018d36: 005b lsls r3, r3, #1
8018d38: 4413 add r3, r2
8018d3a: 00db lsls r3, r3, #3
8018d3c: 440b add r3, r1
8018d3e: 681b ldr r3, [r3, #0]
8018d40: 2b00 cmp r3, #0
8018d42: d021 beq.n 8018d88 <etharp_update_arp_entry+0x130>
struct pbuf *p = arp_table[i].q;
8018d44: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d48: 4915 ldr r1, [pc, #84] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018d4a: 4613 mov r3, r2
8018d4c: 005b lsls r3, r3, #1
8018d4e: 4413 add r3, r2
8018d50: 00db lsls r3, r3, #3
8018d52: 440b add r3, r1
8018d54: 681b ldr r3, [r3, #0]
8018d56: 613b str r3, [r7, #16]
arp_table[i].q = NULL;
8018d58: f9b7 2016 ldrsh.w r2, [r7, #22]
8018d5c: 4910 ldr r1, [pc, #64] ; (8018da0 <etharp_update_arp_entry+0x148>)
8018d5e: 4613 mov r3, r2
8018d60: 005b lsls r3, r3, #1
8018d62: 4413 add r3, r2
8018d64: 00db lsls r3, r3, #3
8018d66: 440b add r3, r1
8018d68: 2200 movs r2, #0
8018d6a: 601a str r2, [r3, #0]
#endif /* ARP_QUEUEING */
/* send the queued IP packet */
ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
8018d6c: 68fb ldr r3, [r7, #12]
8018d6e: f103 022a add.w r2, r3, #42 ; 0x2a
8018d72: f44f 6300 mov.w r3, #2048 ; 0x800
8018d76: 9300 str r3, [sp, #0]
8018d78: 687b ldr r3, [r7, #4]
8018d7a: 6939 ldr r1, [r7, #16]
8018d7c: 68f8 ldr r0, [r7, #12]
8018d7e: f001 ffad bl 801acdc <ethernet_output>
/* free the queued IP packet */
pbuf_free(p);
8018d82: 6938 ldr r0, [r7, #16]
8018d84: f7f7 fc38 bl 80105f8 <pbuf_free>
}
return ERR_OK;
8018d88: 2300 movs r3, #0
}
8018d8a: 4618 mov r0, r3
8018d8c: 3718 adds r7, #24
8018d8e: 46bd mov sp, r7
8018d90: bd80 pop {r7, pc}
8018d92: bf00 nop
8018d94: 0801e748 .word 0x0801e748
8018d98: 0801e840 .word 0x0801e840
8018d9c: 0801e7c0 .word 0x0801e7c0
8018da0: 20008778 .word 0x20008778
08018da4 <etharp_cleanup_netif>:
*
* @param netif points to a network interface
*/
void
etharp_cleanup_netif(struct netif *netif)
{
8018da4: b580 push {r7, lr}
8018da6: b084 sub sp, #16
8018da8: af00 add r7, sp, #0
8018daa: 6078 str r0, [r7, #4]
int i;
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018dac: 2300 movs r3, #0
8018dae: 60fb str r3, [r7, #12]
8018db0: e01e b.n 8018df0 <etharp_cleanup_netif+0x4c>
u8_t state = arp_table[i].state;
8018db2: 4913 ldr r1, [pc, #76] ; (8018e00 <etharp_cleanup_netif+0x5c>)
8018db4: 68fa ldr r2, [r7, #12]
8018db6: 4613 mov r3, r2
8018db8: 005b lsls r3, r3, #1
8018dba: 4413 add r3, r2
8018dbc: 00db lsls r3, r3, #3
8018dbe: 440b add r3, r1
8018dc0: 3314 adds r3, #20
8018dc2: 781b ldrb r3, [r3, #0]
8018dc4: 72fb strb r3, [r7, #11]
if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
8018dc6: 7afb ldrb r3, [r7, #11]
8018dc8: 2b00 cmp r3, #0
8018dca: d00e beq.n 8018dea <etharp_cleanup_netif+0x46>
8018dcc: 490c ldr r1, [pc, #48] ; (8018e00 <etharp_cleanup_netif+0x5c>)
8018dce: 68fa ldr r2, [r7, #12]
8018dd0: 4613 mov r3, r2
8018dd2: 005b lsls r3, r3, #1
8018dd4: 4413 add r3, r2
8018dd6: 00db lsls r3, r3, #3
8018dd8: 440b add r3, r1
8018dda: 3308 adds r3, #8
8018ddc: 681b ldr r3, [r3, #0]
8018dde: 687a ldr r2, [r7, #4]
8018de0: 429a cmp r2, r3
8018de2: d102 bne.n 8018dea <etharp_cleanup_netif+0x46>
etharp_free_entry(i);
8018de4: 68f8 ldr r0, [r7, #12]
8018de6: f7ff fce5 bl 80187b4 <etharp_free_entry>
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
8018dea: 68fb ldr r3, [r7, #12]
8018dec: 3301 adds r3, #1
8018dee: 60fb str r3, [r7, #12]
8018df0: 68fb ldr r3, [r7, #12]
8018df2: 2b09 cmp r3, #9
8018df4: dddd ble.n 8018db2 <etharp_cleanup_netif+0xe>
}
}
}
8018df6: bf00 nop
8018df8: 3710 adds r7, #16
8018dfa: 46bd mov sp, r7
8018dfc: bd80 pop {r7, pc}
8018dfe: bf00 nop
8018e00: 20008778 .word 0x20008778
08018e04 <etharp_input>:
*
* @see pbuf_free()
*/
void
etharp_input(struct pbuf *p, struct netif *netif)
{
8018e04: b5b0 push {r4, r5, r7, lr}
8018e06: b08a sub sp, #40 ; 0x28
8018e08: af04 add r7, sp, #16
8018e0a: 6078 str r0, [r7, #4]
8018e0c: 6039 str r1, [r7, #0]
ip4_addr_t sipaddr, dipaddr;
u8_t for_us;
LWIP_ASSERT_CORE_LOCKED();
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
8018e0e: 683b ldr r3, [r7, #0]
8018e10: 2b00 cmp r3, #0
8018e12: d107 bne.n 8018e24 <etharp_input+0x20>
8018e14: 4b3f ldr r3, [pc, #252] ; (8018f14 <etharp_input+0x110>)
8018e16: f240 228a movw r2, #650 ; 0x28a
8018e1a: 493f ldr r1, [pc, #252] ; (8018f18 <etharp_input+0x114>)
8018e1c: 483f ldr r0, [pc, #252] ; (8018f1c <etharp_input+0x118>)
8018e1e: f002 f901 bl 801b024 <iprintf>
8018e22: e074 b.n 8018f0e <etharp_input+0x10a>
hdr = (struct etharp_hdr *)p->payload;
8018e24: 687b ldr r3, [r7, #4]
8018e26: 685b ldr r3, [r3, #4]
8018e28: 613b str r3, [r7, #16]
/* RFC 826 "Packet Reception": */
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018e2a: 693b ldr r3, [r7, #16]
8018e2c: 881b ldrh r3, [r3, #0]
8018e2e: b29b uxth r3, r3
8018e30: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018e34: d10c bne.n 8018e50 <etharp_input+0x4c>
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018e36: 693b ldr r3, [r7, #16]
8018e38: 791b ldrb r3, [r3, #4]
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
8018e3a: 2b06 cmp r3, #6
8018e3c: d108 bne.n 8018e50 <etharp_input+0x4c>
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018e3e: 693b ldr r3, [r7, #16]
8018e40: 795b ldrb r3, [r3, #5]
(hdr->hwlen != ETH_HWADDR_LEN) ||
8018e42: 2b04 cmp r3, #4
8018e44: d104 bne.n 8018e50 <etharp_input+0x4c>
(hdr->proto != PP_HTONS(ETHTYPE_IP))) {
8018e46: 693b ldr r3, [r7, #16]
8018e48: 885b ldrh r3, [r3, #2]
8018e4a: b29b uxth r3, r3
(hdr->protolen != sizeof(ip4_addr_t)) ||
8018e4c: 2b08 cmp r3, #8
8018e4e: d003 beq.n 8018e58 <etharp_input+0x54>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
pbuf_free(p);
8018e50: 6878 ldr r0, [r7, #4]
8018e52: f7f7 fbd1 bl 80105f8 <pbuf_free>
return;
8018e56: e05a b.n 8018f0e <etharp_input+0x10a>
autoip_arp_reply(netif, hdr);
#endif /* LWIP_AUTOIP */
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing (not using structure copy which breaks strict-aliasing rules). */
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
8018e58: 693b ldr r3, [r7, #16]
8018e5a: 330e adds r3, #14
8018e5c: 681b ldr r3, [r3, #0]
8018e5e: 60fb str r3, [r7, #12]
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
8018e60: 693b ldr r3, [r7, #16]
8018e62: 3318 adds r3, #24
8018e64: 681b ldr r3, [r3, #0]
8018e66: 60bb str r3, [r7, #8]
/* this interface is not configured? */
if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8018e68: 683b ldr r3, [r7, #0]
8018e6a: 3304 adds r3, #4
8018e6c: 681b ldr r3, [r3, #0]
8018e6e: 2b00 cmp r3, #0
8018e70: d102 bne.n 8018e78 <etharp_input+0x74>
for_us = 0;
8018e72: 2300 movs r3, #0
8018e74: 75fb strb r3, [r7, #23]
8018e76: e009 b.n 8018e8c <etharp_input+0x88>
} else {
/* ARP packet directed to us? */
for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
8018e78: 68ba ldr r2, [r7, #8]
8018e7a: 683b ldr r3, [r7, #0]
8018e7c: 3304 adds r3, #4
8018e7e: 681b ldr r3, [r3, #0]
8018e80: 429a cmp r2, r3
8018e82: bf0c ite eq
8018e84: 2301 moveq r3, #1
8018e86: 2300 movne r3, #0
8018e88: b2db uxtb r3, r3
8018e8a: 75fb strb r3, [r7, #23]
/* ARP message directed to us?
-> add IP address in ARP cache; assume requester wants to talk to us,
can result in directly sending the queued packets for this host.
ARP message not directed to us?
-> update the source IP address in the cache, if present */
etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
8018e8c: 693b ldr r3, [r7, #16]
8018e8e: f103 0208 add.w r2, r3, #8
8018e92: 7dfb ldrb r3, [r7, #23]
8018e94: 2b00 cmp r3, #0
8018e96: d001 beq.n 8018e9c <etharp_input+0x98>
8018e98: 2301 movs r3, #1
8018e9a: e000 b.n 8018e9e <etharp_input+0x9a>
8018e9c: 2302 movs r3, #2
8018e9e: f107 010c add.w r1, r7, #12
8018ea2: 6838 ldr r0, [r7, #0]
8018ea4: f7ff fed8 bl 8018c58 <etharp_update_arp_entry>
for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
/* now act on the message itself */
switch (hdr->opcode) {
8018ea8: 693b ldr r3, [r7, #16]
8018eaa: 88db ldrh r3, [r3, #6]
8018eac: b29b uxth r3, r3
8018eae: f5b3 7f80 cmp.w r3, #256 ; 0x100
8018eb2: d003 beq.n 8018ebc <etharp_input+0xb8>
8018eb4: f5b3 7f00 cmp.w r3, #512 ; 0x200
8018eb8: d01e beq.n 8018ef8 <etharp_input+0xf4>
#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
break;
default:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
ETHARP_STATS_INC(etharp.err);
break;
8018eba: e025 b.n 8018f08 <etharp_input+0x104>
if (for_us) {
8018ebc: 7dfb ldrb r3, [r7, #23]
8018ebe: 2b00 cmp r3, #0
8018ec0: d021 beq.n 8018f06 <etharp_input+0x102>
(struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
8018ec2: 683b ldr r3, [r7, #0]
8018ec4: f103 002a add.w r0, r3, #42 ; 0x2a
8018ec8: 693b ldr r3, [r7, #16]
8018eca: f103 0408 add.w r4, r3, #8
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
8018ece: 683b ldr r3, [r7, #0]
8018ed0: f103 052a add.w r5, r3, #42 ; 0x2a
8018ed4: 683b ldr r3, [r7, #0]
8018ed6: 3304 adds r3, #4
&hdr->shwaddr, &sipaddr,
8018ed8: 693a ldr r2, [r7, #16]
8018eda: 3208 adds r2, #8
etharp_raw(netif,
8018edc: 2102 movs r1, #2
8018ede: 9103 str r1, [sp, #12]
8018ee0: f107 010c add.w r1, r7, #12
8018ee4: 9102 str r1, [sp, #8]
8018ee6: 9201 str r2, [sp, #4]
8018ee8: 9300 str r3, [sp, #0]
8018eea: 462b mov r3, r5
8018eec: 4622 mov r2, r4
8018eee: 4601 mov r1, r0
8018ef0: 6838 ldr r0, [r7, #0]
8018ef2: f000 faef bl 80194d4 <etharp_raw>
break;
8018ef6: e006 b.n 8018f06 <etharp_input+0x102>
dhcp_arp_reply(netif, &sipaddr);
8018ef8: f107 030c add.w r3, r7, #12
8018efc: 4619 mov r1, r3
8018efe: 6838 ldr r0, [r7, #0]
8018f00: f7fe f9fe bl 8017300 <dhcp_arp_reply>
break;
8018f04: e000 b.n 8018f08 <etharp_input+0x104>
break;
8018f06: bf00 nop
}
/* free ARP packet */
pbuf_free(p);
8018f08: 6878 ldr r0, [r7, #4]
8018f0a: f7f7 fb75 bl 80105f8 <pbuf_free>
}
8018f0e: 3718 adds r7, #24
8018f10: 46bd mov sp, r7
8018f12: bdb0 pop {r4, r5, r7, pc}
8018f14: 0801e748 .word 0x0801e748
8018f18: 0801e898 .word 0x0801e898
8018f1c: 0801e7c0 .word 0x0801e7c0
08018f20 <etharp_output_to_arp_index>:
/** Just a small helper function that sends a pbuf to an ethernet address
* in the arp_table specified by the index 'arp_idx'.
*/
static err_t
etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
{
8018f20: b580 push {r7, lr}
8018f22: b086 sub sp, #24
8018f24: af02 add r7, sp, #8
8018f26: 60f8 str r0, [r7, #12]
8018f28: 60b9 str r1, [r7, #8]
8018f2a: 4613 mov r3, r2
8018f2c: 71fb strb r3, [r7, #7]
LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
8018f2e: 79fa ldrb r2, [r7, #7]
8018f30: 4944 ldr r1, [pc, #272] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018f32: 4613 mov r3, r2
8018f34: 005b lsls r3, r3, #1
8018f36: 4413 add r3, r2
8018f38: 00db lsls r3, r3, #3
8018f3a: 440b add r3, r1
8018f3c: 3314 adds r3, #20
8018f3e: 781b ldrb r3, [r3, #0]
8018f40: 2b01 cmp r3, #1
8018f42: d806 bhi.n 8018f52 <etharp_output_to_arp_index+0x32>
8018f44: 4b40 ldr r3, [pc, #256] ; (8019048 <etharp_output_to_arp_index+0x128>)
8018f46: f240 22ef movw r2, #751 ; 0x2ef
8018f4a: 4940 ldr r1, [pc, #256] ; (801904c <etharp_output_to_arp_index+0x12c>)
8018f4c: 4840 ldr r0, [pc, #256] ; (8019050 <etharp_output_to_arp_index+0x130>)
8018f4e: f002 f869 bl 801b024 <iprintf>
arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
/* if arp table entry is about to expire: re-request it,
but only if its state is ETHARP_STATE_STABLE to prevent flooding the
network with ARP requests if this address is used frequently. */
if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
8018f52: 79fa ldrb r2, [r7, #7]
8018f54: 493b ldr r1, [pc, #236] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018f56: 4613 mov r3, r2
8018f58: 005b lsls r3, r3, #1
8018f5a: 4413 add r3, r2
8018f5c: 00db lsls r3, r3, #3
8018f5e: 440b add r3, r1
8018f60: 3314 adds r3, #20
8018f62: 781b ldrb r3, [r3, #0]
8018f64: 2b02 cmp r3, #2
8018f66: d153 bne.n 8019010 <etharp_output_to_arp_index+0xf0>
if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
8018f68: 79fa ldrb r2, [r7, #7]
8018f6a: 4936 ldr r1, [pc, #216] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018f6c: 4613 mov r3, r2
8018f6e: 005b lsls r3, r3, #1
8018f70: 4413 add r3, r2
8018f72: 00db lsls r3, r3, #3
8018f74: 440b add r3, r1
8018f76: 3312 adds r3, #18
8018f78: 881b ldrh r3, [r3, #0]
8018f7a: f5b3 7f8e cmp.w r3, #284 ; 0x11c
8018f7e: d919 bls.n 8018fb4 <etharp_output_to_arp_index+0x94>
/* issue a standard request using broadcast */
if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
8018f80: 79fa ldrb r2, [r7, #7]
8018f82: 4613 mov r3, r2
8018f84: 005b lsls r3, r3, #1
8018f86: 4413 add r3, r2
8018f88: 00db lsls r3, r3, #3
8018f8a: 4a2e ldr r2, [pc, #184] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018f8c: 4413 add r3, r2
8018f8e: 3304 adds r3, #4
8018f90: 4619 mov r1, r3
8018f92: 68f8 ldr r0, [r7, #12]
8018f94: f000 fb4c bl 8019630 <etharp_request>
8018f98: 4603 mov r3, r0
8018f9a: 2b00 cmp r3, #0
8018f9c: d138 bne.n 8019010 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018f9e: 79fa ldrb r2, [r7, #7]
8018fa0: 4928 ldr r1, [pc, #160] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018fa2: 4613 mov r3, r2
8018fa4: 005b lsls r3, r3, #1
8018fa6: 4413 add r3, r2
8018fa8: 00db lsls r3, r3, #3
8018faa: 440b add r3, r1
8018fac: 3314 adds r3, #20
8018fae: 2203 movs r2, #3
8018fb0: 701a strb r2, [r3, #0]
8018fb2: e02d b.n 8019010 <etharp_output_to_arp_index+0xf0>
}
} else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
8018fb4: 79fa ldrb r2, [r7, #7]
8018fb6: 4923 ldr r1, [pc, #140] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018fb8: 4613 mov r3, r2
8018fba: 005b lsls r3, r3, #1
8018fbc: 4413 add r3, r2
8018fbe: 00db lsls r3, r3, #3
8018fc0: 440b add r3, r1
8018fc2: 3312 adds r3, #18
8018fc4: 881b ldrh r3, [r3, #0]
8018fc6: f5b3 7f87 cmp.w r3, #270 ; 0x10e
8018fca: d321 bcc.n 8019010 <etharp_output_to_arp_index+0xf0>
/* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
8018fcc: 79fa ldrb r2, [r7, #7]
8018fce: 4613 mov r3, r2
8018fd0: 005b lsls r3, r3, #1
8018fd2: 4413 add r3, r2
8018fd4: 00db lsls r3, r3, #3
8018fd6: 4a1b ldr r2, [pc, #108] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018fd8: 4413 add r3, r2
8018fda: 1d19 adds r1, r3, #4
8018fdc: 79fa ldrb r2, [r7, #7]
8018fde: 4613 mov r3, r2
8018fe0: 005b lsls r3, r3, #1
8018fe2: 4413 add r3, r2
8018fe4: 00db lsls r3, r3, #3
8018fe6: 3308 adds r3, #8
8018fe8: 4a16 ldr r2, [pc, #88] ; (8019044 <etharp_output_to_arp_index+0x124>)
8018fea: 4413 add r3, r2
8018fec: 3304 adds r3, #4
8018fee: 461a mov r2, r3
8018ff0: 68f8 ldr r0, [r7, #12]
8018ff2: f000 fafb bl 80195ec <etharp_request_dst>
8018ff6: 4603 mov r3, r0
8018ff8: 2b00 cmp r3, #0
8018ffa: d109 bne.n 8019010 <etharp_output_to_arp_index+0xf0>
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
8018ffc: 79fa ldrb r2, [r7, #7]
8018ffe: 4911 ldr r1, [pc, #68] ; (8019044 <etharp_output_to_arp_index+0x124>)
8019000: 4613 mov r3, r2
8019002: 005b lsls r3, r3, #1
8019004: 4413 add r3, r2
8019006: 00db lsls r3, r3, #3
8019008: 440b add r3, r1
801900a: 3314 adds r3, #20
801900c: 2203 movs r2, #3
801900e: 701a strb r2, [r3, #0]
}
}
}
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
8019010: 68fb ldr r3, [r7, #12]
8019012: f103 012a add.w r1, r3, #42 ; 0x2a
8019016: 79fa ldrb r2, [r7, #7]
8019018: 4613 mov r3, r2
801901a: 005b lsls r3, r3, #1
801901c: 4413 add r3, r2
801901e: 00db lsls r3, r3, #3
8019020: 3308 adds r3, #8
8019022: 4a08 ldr r2, [pc, #32] ; (8019044 <etharp_output_to_arp_index+0x124>)
8019024: 4413 add r3, r2
8019026: 1d1a adds r2, r3, #4
8019028: f44f 6300 mov.w r3, #2048 ; 0x800
801902c: 9300 str r3, [sp, #0]
801902e: 4613 mov r3, r2
8019030: 460a mov r2, r1
8019032: 68b9 ldr r1, [r7, #8]
8019034: 68f8 ldr r0, [r7, #12]
8019036: f001 fe51 bl 801acdc <ethernet_output>
801903a: 4603 mov r3, r0
}
801903c: 4618 mov r0, r3
801903e: 3710 adds r7, #16
8019040: 46bd mov sp, r7
8019042: bd80 pop {r7, pc}
8019044: 20008778 .word 0x20008778
8019048: 0801e748 .word 0x0801e748
801904c: 0801e8b8 .word 0x0801e8b8
8019050: 0801e7c0 .word 0x0801e7c0
08019054 <etharp_output>:
* - ERR_RTE No route to destination (no gateway to external networks),
* or the return type of either etharp_query() or ethernet_output().
*/
err_t
etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
{
8019054: b580 push {r7, lr}
8019056: b08a sub sp, #40 ; 0x28
8019058: af02 add r7, sp, #8
801905a: 60f8 str r0, [r7, #12]
801905c: 60b9 str r1, [r7, #8]
801905e: 607a str r2, [r7, #4]
const struct eth_addr *dest;
struct eth_addr mcastaddr;
const ip4_addr_t *dst_addr = ipaddr;
8019060: 687b ldr r3, [r7, #4]
8019062: 61bb str r3, [r7, #24]
LWIP_ASSERT_CORE_LOCKED();
LWIP_ASSERT("netif != NULL", netif != NULL);
8019064: 68fb ldr r3, [r7, #12]
8019066: 2b00 cmp r3, #0
8019068: d106 bne.n 8019078 <etharp_output+0x24>
801906a: 4b73 ldr r3, [pc, #460] ; (8019238 <etharp_output+0x1e4>)
801906c: f240 321e movw r2, #798 ; 0x31e
8019070: 4972 ldr r1, [pc, #456] ; (801923c <etharp_output+0x1e8>)
8019072: 4873 ldr r0, [pc, #460] ; (8019240 <etharp_output+0x1ec>)
8019074: f001 ffd6 bl 801b024 <iprintf>
LWIP_ASSERT("q != NULL", q != NULL);
8019078: 68bb ldr r3, [r7, #8]
801907a: 2b00 cmp r3, #0
801907c: d106 bne.n 801908c <etharp_output+0x38>
801907e: 4b6e ldr r3, [pc, #440] ; (8019238 <etharp_output+0x1e4>)
8019080: f240 321f movw r2, #799 ; 0x31f
8019084: 496f ldr r1, [pc, #444] ; (8019244 <etharp_output+0x1f0>)
8019086: 486e ldr r0, [pc, #440] ; (8019240 <etharp_output+0x1ec>)
8019088: f001 ffcc bl 801b024 <iprintf>
LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
801908c: 687b ldr r3, [r7, #4]
801908e: 2b00 cmp r3, #0
8019090: d106 bne.n 80190a0 <etharp_output+0x4c>
8019092: 4b69 ldr r3, [pc, #420] ; (8019238 <etharp_output+0x1e4>)
8019094: f44f 7248 mov.w r2, #800 ; 0x320
8019098: 496b ldr r1, [pc, #428] ; (8019248 <etharp_output+0x1f4>)
801909a: 4869 ldr r0, [pc, #420] ; (8019240 <etharp_output+0x1ec>)
801909c: f001 ffc2 bl 801b024 <iprintf>
/* Determine on destination hardware address. Broadcasts and multicasts
* are special, other IP addresses are looked up in the ARP table. */
/* broadcast destination IP address? */
if (ip4_addr_isbroadcast(ipaddr, netif)) {
80190a0: 687b ldr r3, [r7, #4]
80190a2: 681b ldr r3, [r3, #0]
80190a4: 68f9 ldr r1, [r7, #12]
80190a6: 4618 mov r0, r3
80190a8: f000 ff14 bl 8019ed4 <ip4_addr_isbroadcast_u32>
80190ac: 4603 mov r3, r0
80190ae: 2b00 cmp r3, #0
80190b0: d002 beq.n 80190b8 <etharp_output+0x64>
/* broadcast on Ethernet also */
dest = (const struct eth_addr *)&ethbroadcast;
80190b2: 4b66 ldr r3, [pc, #408] ; (801924c <etharp_output+0x1f8>)
80190b4: 61fb str r3, [r7, #28]
80190b6: e0af b.n 8019218 <etharp_output+0x1c4>
/* multicast destination IP address? */
} else if (ip4_addr_ismulticast(ipaddr)) {
80190b8: 687b ldr r3, [r7, #4]
80190ba: 681b ldr r3, [r3, #0]
80190bc: f003 03f0 and.w r3, r3, #240 ; 0xf0
80190c0: 2be0 cmp r3, #224 ; 0xe0
80190c2: d118 bne.n 80190f6 <etharp_output+0xa2>
/* Hash IP multicast address to MAC address.*/
mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
80190c4: 2301 movs r3, #1
80190c6: 743b strb r3, [r7, #16]
mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
80190c8: 2300 movs r3, #0
80190ca: 747b strb r3, [r7, #17]
mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
80190cc: 235e movs r3, #94 ; 0x5e
80190ce: 74bb strb r3, [r7, #18]
mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
80190d0: 687b ldr r3, [r7, #4]
80190d2: 3301 adds r3, #1
80190d4: 781b ldrb r3, [r3, #0]
80190d6: f003 037f and.w r3, r3, #127 ; 0x7f
80190da: b2db uxtb r3, r3
80190dc: 74fb strb r3, [r7, #19]
mcastaddr.addr[4] = ip4_addr3(ipaddr);
80190de: 687b ldr r3, [r7, #4]
80190e0: 3302 adds r3, #2
80190e2: 781b ldrb r3, [r3, #0]
80190e4: 753b strb r3, [r7, #20]
mcastaddr.addr[5] = ip4_addr4(ipaddr);
80190e6: 687b ldr r3, [r7, #4]
80190e8: 3303 adds r3, #3
80190ea: 781b ldrb r3, [r3, #0]
80190ec: 757b strb r3, [r7, #21]
/* destination Ethernet address is multicast */
dest = &mcastaddr;
80190ee: f107 0310 add.w r3, r7, #16
80190f2: 61fb str r3, [r7, #28]
80190f4: e090 b.n 8019218 <etharp_output+0x1c4>
/* unicast destination IP address? */
} else {
netif_addr_idx_t i;
/* outside local network? if so, this can neither be a global broadcast nor
a subnet broadcast. */
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
80190f6: 687b ldr r3, [r7, #4]
80190f8: 681a ldr r2, [r3, #0]
80190fa: 68fb ldr r3, [r7, #12]
80190fc: 3304 adds r3, #4
80190fe: 681b ldr r3, [r3, #0]
8019100: 405a eors r2, r3
8019102: 68fb ldr r3, [r7, #12]
8019104: 3308 adds r3, #8
8019106: 681b ldr r3, [r3, #0]
8019108: 4013 ands r3, r2
801910a: 2b00 cmp r3, #0
801910c: d012 beq.n 8019134 <etharp_output+0xe0>
!ip4_addr_islinklocal(ipaddr)) {
801910e: 687b ldr r3, [r7, #4]
8019110: 681b ldr r3, [r3, #0]
8019112: b29b uxth r3, r3
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
8019114: f64f 62a9 movw r2, #65193 ; 0xfea9
8019118: 4293 cmp r3, r2
801911a: d00b beq.n 8019134 <etharp_output+0xe0>
dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
if (dst_addr == NULL)
#endif /* LWIP_HOOK_ETHARP_GET_GW */
{
/* interface has default gateway? */
if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
801911c: 68fb ldr r3, [r7, #12]
801911e: 330c adds r3, #12
8019120: 681b ldr r3, [r3, #0]
8019122: 2b00 cmp r3, #0
8019124: d003 beq.n 801912e <etharp_output+0xda>
/* send to hardware address of default gateway IP address */
dst_addr = netif_ip4_gw(netif);
8019126: 68fb ldr r3, [r7, #12]
8019128: 330c adds r3, #12
801912a: 61bb str r3, [r7, #24]
801912c: e002 b.n 8019134 <etharp_output+0xe0>
/* no default gateway available */
} else {
/* no route to destination error (default gateway missing) */
return ERR_RTE;
801912e: f06f 0303 mvn.w r3, #3
8019132: e07d b.n 8019230 <etharp_output+0x1dc>
if (netif->hints != NULL) {
/* per-pcb cached entry was given */
netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
if (etharp_cached_entry < ARP_TABLE_SIZE) {
#endif /* LWIP_NETIF_HWADDRHINT */
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
8019134: 4b46 ldr r3, [pc, #280] ; (8019250 <etharp_output+0x1fc>)
8019136: 781b ldrb r3, [r3, #0]
8019138: 4619 mov r1, r3
801913a: 4a46 ldr r2, [pc, #280] ; (8019254 <etharp_output+0x200>)
801913c: 460b mov r3, r1
801913e: 005b lsls r3, r3, #1
8019140: 440b add r3, r1
8019142: 00db lsls r3, r3, #3
8019144: 4413 add r3, r2
8019146: 3314 adds r3, #20
8019148: 781b ldrb r3, [r3, #0]
801914a: 2b01 cmp r3, #1
801914c: d925 bls.n 801919a <etharp_output+0x146>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[etharp_cached_entry].netif == netif) &&
801914e: 4b40 ldr r3, [pc, #256] ; (8019250 <etharp_output+0x1fc>)
8019150: 781b ldrb r3, [r3, #0]
8019152: 4619 mov r1, r3
8019154: 4a3f ldr r2, [pc, #252] ; (8019254 <etharp_output+0x200>)
8019156: 460b mov r3, r1
8019158: 005b lsls r3, r3, #1
801915a: 440b add r3, r1
801915c: 00db lsls r3, r3, #3
801915e: 4413 add r3, r2
8019160: 3308 adds r3, #8
8019162: 681b ldr r3, [r3, #0]
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
8019164: 68fa ldr r2, [r7, #12]
8019166: 429a cmp r2, r3
8019168: d117 bne.n 801919a <etharp_output+0x146>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
801916a: 69bb ldr r3, [r7, #24]
801916c: 681a ldr r2, [r3, #0]
801916e: 4b38 ldr r3, [pc, #224] ; (8019250 <etharp_output+0x1fc>)
8019170: 781b ldrb r3, [r3, #0]
8019172: 4618 mov r0, r3
8019174: 4937 ldr r1, [pc, #220] ; (8019254 <etharp_output+0x200>)
8019176: 4603 mov r3, r0
8019178: 005b lsls r3, r3, #1
801917a: 4403 add r3, r0
801917c: 00db lsls r3, r3, #3
801917e: 440b add r3, r1
8019180: 3304 adds r3, #4
8019182: 681b ldr r3, [r3, #0]
(arp_table[etharp_cached_entry].netif == netif) &&
8019184: 429a cmp r2, r3
8019186: d108 bne.n 801919a <etharp_output+0x146>
/* the per-pcb-cached entry is stable and the right one! */
ETHARP_STATS_INC(etharp.cachehit);
return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
8019188: 4b31 ldr r3, [pc, #196] ; (8019250 <etharp_output+0x1fc>)
801918a: 781b ldrb r3, [r3, #0]
801918c: 461a mov r2, r3
801918e: 68b9 ldr r1, [r7, #8]
8019190: 68f8 ldr r0, [r7, #12]
8019192: f7ff fec5 bl 8018f20 <etharp_output_to_arp_index>
8019196: 4603 mov r3, r0
8019198: e04a b.n 8019230 <etharp_output+0x1dc>
}
#endif /* LWIP_NETIF_HWADDRHINT */
/* find stable entry: do this here since this is a critical path for
throughput and etharp_find_entry() is kind of slow */
for (i = 0; i < ARP_TABLE_SIZE; i++) {
801919a: 2300 movs r3, #0
801919c: 75fb strb r3, [r7, #23]
801919e: e031 b.n 8019204 <etharp_output+0x1b0>
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
80191a0: 7dfa ldrb r2, [r7, #23]
80191a2: 492c ldr r1, [pc, #176] ; (8019254 <etharp_output+0x200>)
80191a4: 4613 mov r3, r2
80191a6: 005b lsls r3, r3, #1
80191a8: 4413 add r3, r2
80191aa: 00db lsls r3, r3, #3
80191ac: 440b add r3, r1
80191ae: 3314 adds r3, #20
80191b0: 781b ldrb r3, [r3, #0]
80191b2: 2b01 cmp r3, #1
80191b4: d923 bls.n 80191fe <etharp_output+0x1aa>
#if ETHARP_TABLE_MATCH_NETIF
(arp_table[i].netif == netif) &&
80191b6: 7dfa ldrb r2, [r7, #23]
80191b8: 4926 ldr r1, [pc, #152] ; (8019254 <etharp_output+0x200>)
80191ba: 4613 mov r3, r2
80191bc: 005b lsls r3, r3, #1
80191be: 4413 add r3, r2
80191c0: 00db lsls r3, r3, #3
80191c2: 440b add r3, r1
80191c4: 3308 adds r3, #8
80191c6: 681b ldr r3, [r3, #0]
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
80191c8: 68fa ldr r2, [r7, #12]
80191ca: 429a cmp r2, r3
80191cc: d117 bne.n 80191fe <etharp_output+0x1aa>
#endif
(ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
80191ce: 69bb ldr r3, [r7, #24]
80191d0: 6819 ldr r1, [r3, #0]
80191d2: 7dfa ldrb r2, [r7, #23]
80191d4: 481f ldr r0, [pc, #124] ; (8019254 <etharp_output+0x200>)
80191d6: 4613 mov r3, r2
80191d8: 005b lsls r3, r3, #1
80191da: 4413 add r3, r2
80191dc: 00db lsls r3, r3, #3
80191de: 4403 add r3, r0
80191e0: 3304 adds r3, #4
80191e2: 681b ldr r3, [r3, #0]
(arp_table[i].netif == netif) &&
80191e4: 4299 cmp r1, r3
80191e6: d10a bne.n 80191fe <etharp_output+0x1aa>
/* found an existing, stable entry */
ETHARP_SET_ADDRHINT(netif, i);
80191e8: 4a19 ldr r2, [pc, #100] ; (8019250 <etharp_output+0x1fc>)
80191ea: 7dfb ldrb r3, [r7, #23]
80191ec: 7013 strb r3, [r2, #0]
return etharp_output_to_arp_index(netif, q, i);
80191ee: 7dfb ldrb r3, [r7, #23]
80191f0: 461a mov r2, r3
80191f2: 68b9 ldr r1, [r7, #8]
80191f4: 68f8 ldr r0, [r7, #12]
80191f6: f7ff fe93 bl 8018f20 <etharp_output_to_arp_index>
80191fa: 4603 mov r3, r0
80191fc: e018 b.n 8019230 <etharp_output+0x1dc>
for (i = 0; i < ARP_TABLE_SIZE; i++) {
80191fe: 7dfb ldrb r3, [r7, #23]
8019200: 3301 adds r3, #1
8019202: 75fb strb r3, [r7, #23]
8019204: 7dfb ldrb r3, [r7, #23]
8019206: 2b09 cmp r3, #9
8019208: d9ca bls.n 80191a0 <etharp_output+0x14c>
}
}
/* no stable entry found, use the (slower) query function:
queue on destination Ethernet address belonging to ipaddr */
return etharp_query(netif, dst_addr, q);
801920a: 68ba ldr r2, [r7, #8]
801920c: 69b9 ldr r1, [r7, #24]
801920e: 68f8 ldr r0, [r7, #12]
8019210: f000 f822 bl 8019258 <etharp_query>
8019214: 4603 mov r3, r0
8019216: e00b b.n 8019230 <etharp_output+0x1dc>
}
/* continuation for multicast/broadcast destinations */
/* obtain source Ethernet address of the given interface */
/* send packet directly on the link */
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
8019218: 68fb ldr r3, [r7, #12]
801921a: f103 022a add.w r2, r3, #42 ; 0x2a
801921e: f44f 6300 mov.w r3, #2048 ; 0x800
8019222: 9300 str r3, [sp, #0]
8019224: 69fb ldr r3, [r7, #28]
8019226: 68b9 ldr r1, [r7, #8]
8019228: 68f8 ldr r0, [r7, #12]
801922a: f001 fd57 bl 801acdc <ethernet_output>
801922e: 4603 mov r3, r0
}
8019230: 4618 mov r0, r3
8019232: 3720 adds r7, #32
8019234: 46bd mov sp, r7
8019236: bd80 pop {r7, pc}
8019238: 0801e748 .word 0x0801e748
801923c: 0801e898 .word 0x0801e898
8019240: 0801e7c0 .word 0x0801e7c0
8019244: 0801e8e8 .word 0x0801e8e8
8019248: 0801e888 .word 0x0801e888
801924c: 08020e80 .word 0x08020e80
8019250: 20008868 .word 0x20008868
8019254: 20008778 .word 0x20008778
08019258 <etharp_query>:
* - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
*
*/
err_t
etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
{
8019258: b580 push {r7, lr}
801925a: b08c sub sp, #48 ; 0x30
801925c: af02 add r7, sp, #8
801925e: 60f8 str r0, [r7, #12]
8019260: 60b9 str r1, [r7, #8]
8019262: 607a str r2, [r7, #4]
struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
8019264: 68fb ldr r3, [r7, #12]
8019266: 332a adds r3, #42 ; 0x2a
8019268: 617b str r3, [r7, #20]
err_t result = ERR_MEM;
801926a: 23ff movs r3, #255 ; 0xff
801926c: f887 3027 strb.w r3, [r7, #39] ; 0x27
int is_new_entry = 0;
8019270: 2300 movs r3, #0
8019272: 623b str r3, [r7, #32]
s16_t i_err;
netif_addr_idx_t i;
/* non-unicast address? */
if (ip4_addr_isbroadcast(ipaddr, netif) ||
8019274: 68bb ldr r3, [r7, #8]
8019276: 681b ldr r3, [r3, #0]
8019278: 68f9 ldr r1, [r7, #12]
801927a: 4618 mov r0, r3
801927c: f000 fe2a bl 8019ed4 <ip4_addr_isbroadcast_u32>
8019280: 4603 mov r3, r0
8019282: 2b00 cmp r3, #0
8019284: d10c bne.n 80192a0 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019286: 68bb ldr r3, [r7, #8]
8019288: 681b ldr r3, [r3, #0]
801928a: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (ip4_addr_isbroadcast(ipaddr, netif) ||
801928e: 2be0 cmp r3, #224 ; 0xe0
8019290: d006 beq.n 80192a0 <etharp_query+0x48>
ip4_addr_ismulticast(ipaddr) ||
8019292: 68bb ldr r3, [r7, #8]
8019294: 2b00 cmp r3, #0
8019296: d003 beq.n 80192a0 <etharp_query+0x48>
ip4_addr_isany(ipaddr)) {
8019298: 68bb ldr r3, [r7, #8]
801929a: 681b ldr r3, [r3, #0]
801929c: 2b00 cmp r3, #0
801929e: d102 bne.n 80192a6 <etharp_query+0x4e>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
return ERR_ARG;
80192a0: f06f 030f mvn.w r3, #15
80192a4: e102 b.n 80194ac <etharp_query+0x254>
}
/* find entry in ARP cache, ask to create entry if queueing packet */
i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
80192a6: 68fa ldr r2, [r7, #12]
80192a8: 2101 movs r1, #1
80192aa: 68b8 ldr r0, [r7, #8]
80192ac: f7ff fb5c bl 8018968 <etharp_find_entry>
80192b0: 4603 mov r3, r0
80192b2: 827b strh r3, [r7, #18]
/* could not find or create entry? */
if (i_err < 0) {
80192b4: f9b7 3012 ldrsh.w r3, [r7, #18]
80192b8: 2b00 cmp r3, #0
80192ba: da02 bge.n 80192c2 <etharp_query+0x6a>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
if (q) {
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
ETHARP_STATS_INC(etharp.memerr);
}
return (err_t)i_err;
80192bc: 8a7b ldrh r3, [r7, #18]
80192be: b25b sxtb r3, r3
80192c0: e0f4 b.n 80194ac <etharp_query+0x254>
}
LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
80192c2: 8a7b ldrh r3, [r7, #18]
80192c4: 2b7e cmp r3, #126 ; 0x7e
80192c6: d906 bls.n 80192d6 <etharp_query+0x7e>
80192c8: 4b7a ldr r3, [pc, #488] ; (80194b4 <etharp_query+0x25c>)
80192ca: f240 32c1 movw r2, #961 ; 0x3c1
80192ce: 497a ldr r1, [pc, #488] ; (80194b8 <etharp_query+0x260>)
80192d0: 487a ldr r0, [pc, #488] ; (80194bc <etharp_query+0x264>)
80192d2: f001 fea7 bl 801b024 <iprintf>
i = (netif_addr_idx_t)i_err;
80192d6: 8a7b ldrh r3, [r7, #18]
80192d8: 747b strb r3, [r7, #17]
/* mark a fresh entry as pending (we just sent a request) */
if (arp_table[i].state == ETHARP_STATE_EMPTY) {
80192da: 7c7a ldrb r2, [r7, #17]
80192dc: 4978 ldr r1, [pc, #480] ; (80194c0 <etharp_query+0x268>)
80192de: 4613 mov r3, r2
80192e0: 005b lsls r3, r3, #1
80192e2: 4413 add r3, r2
80192e4: 00db lsls r3, r3, #3
80192e6: 440b add r3, r1
80192e8: 3314 adds r3, #20
80192ea: 781b ldrb r3, [r3, #0]
80192ec: 2b00 cmp r3, #0
80192ee: d115 bne.n 801931c <etharp_query+0xc4>
is_new_entry = 1;
80192f0: 2301 movs r3, #1
80192f2: 623b str r3, [r7, #32]
arp_table[i].state = ETHARP_STATE_PENDING;
80192f4: 7c7a ldrb r2, [r7, #17]
80192f6: 4972 ldr r1, [pc, #456] ; (80194c0 <etharp_query+0x268>)
80192f8: 4613 mov r3, r2
80192fa: 005b lsls r3, r3, #1
80192fc: 4413 add r3, r2
80192fe: 00db lsls r3, r3, #3
8019300: 440b add r3, r1
8019302: 3314 adds r3, #20
8019304: 2201 movs r2, #1
8019306: 701a strb r2, [r3, #0]
/* record network interface for re-sending arp request in etharp_tmr */
arp_table[i].netif = netif;
8019308: 7c7a ldrb r2, [r7, #17]
801930a: 496d ldr r1, [pc, #436] ; (80194c0 <etharp_query+0x268>)
801930c: 4613 mov r3, r2
801930e: 005b lsls r3, r3, #1
8019310: 4413 add r3, r2
8019312: 00db lsls r3, r3, #3
8019314: 440b add r3, r1
8019316: 3308 adds r3, #8
8019318: 68fa ldr r2, [r7, #12]
801931a: 601a str r2, [r3, #0]
}
/* { i is either a STABLE or (new or existing) PENDING entry } */
LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
801931c: 7c7a ldrb r2, [r7, #17]
801931e: 4968 ldr r1, [pc, #416] ; (80194c0 <etharp_query+0x268>)
8019320: 4613 mov r3, r2
8019322: 005b lsls r3, r3, #1
8019324: 4413 add r3, r2
8019326: 00db lsls r3, r3, #3
8019328: 440b add r3, r1
801932a: 3314 adds r3, #20
801932c: 781b ldrb r3, [r3, #0]
801932e: 2b01 cmp r3, #1
8019330: d011 beq.n 8019356 <etharp_query+0xfe>
8019332: 7c7a ldrb r2, [r7, #17]
8019334: 4962 ldr r1, [pc, #392] ; (80194c0 <etharp_query+0x268>)
8019336: 4613 mov r3, r2
8019338: 005b lsls r3, r3, #1
801933a: 4413 add r3, r2
801933c: 00db lsls r3, r3, #3
801933e: 440b add r3, r1
8019340: 3314 adds r3, #20
8019342: 781b ldrb r3, [r3, #0]
8019344: 2b01 cmp r3, #1
8019346: d806 bhi.n 8019356 <etharp_query+0xfe>
8019348: 4b5a ldr r3, [pc, #360] ; (80194b4 <etharp_query+0x25c>)
801934a: f240 32cf movw r2, #975 ; 0x3cf
801934e: 495d ldr r1, [pc, #372] ; (80194c4 <etharp_query+0x26c>)
8019350: 485a ldr r0, [pc, #360] ; (80194bc <etharp_query+0x264>)
8019352: f001 fe67 bl 801b024 <iprintf>
((arp_table[i].state == ETHARP_STATE_PENDING) ||
(arp_table[i].state >= ETHARP_STATE_STABLE)));
/* do we have a new entry? or an implicit query request? */
if (is_new_entry || (q == NULL)) {
8019356: 6a3b ldr r3, [r7, #32]
8019358: 2b00 cmp r3, #0
801935a: d102 bne.n 8019362 <etharp_query+0x10a>
801935c: 687b ldr r3, [r7, #4]
801935e: 2b00 cmp r3, #0
8019360: d10c bne.n 801937c <etharp_query+0x124>
/* try to resolve it; send out ARP request */
result = etharp_request(netif, ipaddr);
8019362: 68b9 ldr r1, [r7, #8]
8019364: 68f8 ldr r0, [r7, #12]
8019366: f000 f963 bl 8019630 <etharp_request>
801936a: 4603 mov r3, r0
801936c: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* ARP request couldn't be sent */
/* We don't re-send arp request in etharp_tmr, but we still queue packets,
since this failure could be temporary, and the next packet calling
etharp_query again could lead to sending the queued packets. */
}
if (q == NULL) {
8019370: 687b ldr r3, [r7, #4]
8019372: 2b00 cmp r3, #0
8019374: d102 bne.n 801937c <etharp_query+0x124>
return result;
8019376: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
801937a: e097 b.n 80194ac <etharp_query+0x254>
}
}
/* packet given? */
LWIP_ASSERT("q != NULL", q != NULL);
801937c: 687b ldr r3, [r7, #4]
801937e: 2b00 cmp r3, #0
8019380: d106 bne.n 8019390 <etharp_query+0x138>
8019382: 4b4c ldr r3, [pc, #304] ; (80194b4 <etharp_query+0x25c>)
8019384: f240 32e1 movw r2, #993 ; 0x3e1
8019388: 494f ldr r1, [pc, #316] ; (80194c8 <etharp_query+0x270>)
801938a: 484c ldr r0, [pc, #304] ; (80194bc <etharp_query+0x264>)
801938c: f001 fe4a bl 801b024 <iprintf>
/* stable entry? */
if (arp_table[i].state >= ETHARP_STATE_STABLE) {
8019390: 7c7a ldrb r2, [r7, #17]
8019392: 494b ldr r1, [pc, #300] ; (80194c0 <etharp_query+0x268>)
8019394: 4613 mov r3, r2
8019396: 005b lsls r3, r3, #1
8019398: 4413 add r3, r2
801939a: 00db lsls r3, r3, #3
801939c: 440b add r3, r1
801939e: 3314 adds r3, #20
80193a0: 781b ldrb r3, [r3, #0]
80193a2: 2b01 cmp r3, #1
80193a4: d918 bls.n 80193d8 <etharp_query+0x180>
/* we have a valid IP->Ethernet address mapping */
ETHARP_SET_ADDRHINT(netif, i);
80193a6: 4a49 ldr r2, [pc, #292] ; (80194cc <etharp_query+0x274>)
80193a8: 7c7b ldrb r3, [r7, #17]
80193aa: 7013 strb r3, [r2, #0]
/* send the packet */
result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
80193ac: 7c7a ldrb r2, [r7, #17]
80193ae: 4613 mov r3, r2
80193b0: 005b lsls r3, r3, #1
80193b2: 4413 add r3, r2
80193b4: 00db lsls r3, r3, #3
80193b6: 3308 adds r3, #8
80193b8: 4a41 ldr r2, [pc, #260] ; (80194c0 <etharp_query+0x268>)
80193ba: 4413 add r3, r2
80193bc: 1d1a adds r2, r3, #4
80193be: f44f 6300 mov.w r3, #2048 ; 0x800
80193c2: 9300 str r3, [sp, #0]
80193c4: 4613 mov r3, r2
80193c6: 697a ldr r2, [r7, #20]
80193c8: 6879 ldr r1, [r7, #4]
80193ca: 68f8 ldr r0, [r7, #12]
80193cc: f001 fc86 bl 801acdc <ethernet_output>
80193d0: 4603 mov r3, r0
80193d2: f887 3027 strb.w r3, [r7, #39] ; 0x27
80193d6: e067 b.n 80194a8 <etharp_query+0x250>
/* pending entry? (either just created or already pending */
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
80193d8: 7c7a ldrb r2, [r7, #17]
80193da: 4939 ldr r1, [pc, #228] ; (80194c0 <etharp_query+0x268>)
80193dc: 4613 mov r3, r2
80193de: 005b lsls r3, r3, #1
80193e0: 4413 add r3, r2
80193e2: 00db lsls r3, r3, #3
80193e4: 440b add r3, r1
80193e6: 3314 adds r3, #20
80193e8: 781b ldrb r3, [r3, #0]
80193ea: 2b01 cmp r3, #1
80193ec: d15c bne.n 80194a8 <etharp_query+0x250>
/* entry is still pending, queue the given packet 'q' */
struct pbuf *p;
int copy_needed = 0;
80193ee: 2300 movs r3, #0
80193f0: 61bb str r3, [r7, #24]
/* IF q includes a pbuf that must be copied, copy the whole chain into a
* new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
p = q;
80193f2: 687b ldr r3, [r7, #4]
80193f4: 61fb str r3, [r7, #28]
while (p) {
80193f6: e01c b.n 8019432 <etharp_query+0x1da>
LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
80193f8: 69fb ldr r3, [r7, #28]
80193fa: 895a ldrh r2, [r3, #10]
80193fc: 69fb ldr r3, [r7, #28]
80193fe: 891b ldrh r3, [r3, #8]
8019400: 429a cmp r2, r3
8019402: d10a bne.n 801941a <etharp_query+0x1c2>
8019404: 69fb ldr r3, [r7, #28]
8019406: 681b ldr r3, [r3, #0]
8019408: 2b00 cmp r3, #0
801940a: d006 beq.n 801941a <etharp_query+0x1c2>
801940c: 4b29 ldr r3, [pc, #164] ; (80194b4 <etharp_query+0x25c>)
801940e: f240 32f1 movw r2, #1009 ; 0x3f1
8019412: 492f ldr r1, [pc, #188] ; (80194d0 <etharp_query+0x278>)
8019414: 4829 ldr r0, [pc, #164] ; (80194bc <etharp_query+0x264>)
8019416: f001 fe05 bl 801b024 <iprintf>
if (PBUF_NEEDS_COPY(p)) {
801941a: 69fb ldr r3, [r7, #28]
801941c: 7b1b ldrb r3, [r3, #12]
801941e: f003 0340 and.w r3, r3, #64 ; 0x40
8019422: 2b00 cmp r3, #0
8019424: d002 beq.n 801942c <etharp_query+0x1d4>
copy_needed = 1;
8019426: 2301 movs r3, #1
8019428: 61bb str r3, [r7, #24]
break;
801942a: e005 b.n 8019438 <etharp_query+0x1e0>
}
p = p->next;
801942c: 69fb ldr r3, [r7, #28]
801942e: 681b ldr r3, [r3, #0]
8019430: 61fb str r3, [r7, #28]
while (p) {
8019432: 69fb ldr r3, [r7, #28]
8019434: 2b00 cmp r3, #0
8019436: d1df bne.n 80193f8 <etharp_query+0x1a0>
}
if (copy_needed) {
8019438: 69bb ldr r3, [r7, #24]
801943a: 2b00 cmp r3, #0
801943c: d007 beq.n 801944e <etharp_query+0x1f6>
/* copy the whole packet into new pbufs */
p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
801943e: 687a ldr r2, [r7, #4]
8019440: f44f 7120 mov.w r1, #640 ; 0x280
8019444: 200e movs r0, #14
8019446: f7f7 fb4f bl 8010ae8 <pbuf_clone>
801944a: 61f8 str r0, [r7, #28]
801944c: e004 b.n 8019458 <etharp_query+0x200>
} else {
/* referencing the old pbuf is enough */
p = q;
801944e: 687b ldr r3, [r7, #4]
8019450: 61fb str r3, [r7, #28]
pbuf_ref(p);
8019452: 69f8 ldr r0, [r7, #28]
8019454: f7f7 f976 bl 8010744 <pbuf_ref>
}
/* packet could be taken over? */
if (p != NULL) {
8019458: 69fb ldr r3, [r7, #28]
801945a: 2b00 cmp r3, #0
801945c: d021 beq.n 80194a2 <etharp_query+0x24a>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
}
#else /* ARP_QUEUEING */
/* always queue one packet per ARP request only, freeing a previously queued packet */
if (arp_table[i].q != NULL) {
801945e: 7c7a ldrb r2, [r7, #17]
8019460: 4917 ldr r1, [pc, #92] ; (80194c0 <etharp_query+0x268>)
8019462: 4613 mov r3, r2
8019464: 005b lsls r3, r3, #1
8019466: 4413 add r3, r2
8019468: 00db lsls r3, r3, #3
801946a: 440b add r3, r1
801946c: 681b ldr r3, [r3, #0]
801946e: 2b00 cmp r3, #0
8019470: d00a beq.n 8019488 <etharp_query+0x230>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
pbuf_free(arp_table[i].q);
8019472: 7c7a ldrb r2, [r7, #17]
8019474: 4912 ldr r1, [pc, #72] ; (80194c0 <etharp_query+0x268>)
8019476: 4613 mov r3, r2
8019478: 005b lsls r3, r3, #1
801947a: 4413 add r3, r2
801947c: 00db lsls r3, r3, #3
801947e: 440b add r3, r1
8019480: 681b ldr r3, [r3, #0]
8019482: 4618 mov r0, r3
8019484: f7f7 f8b8 bl 80105f8 <pbuf_free>
}
arp_table[i].q = p;
8019488: 7c7a ldrb r2, [r7, #17]
801948a: 490d ldr r1, [pc, #52] ; (80194c0 <etharp_query+0x268>)
801948c: 4613 mov r3, r2
801948e: 005b lsls r3, r3, #1
8019490: 4413 add r3, r2
8019492: 00db lsls r3, r3, #3
8019494: 440b add r3, r1
8019496: 69fa ldr r2, [r7, #28]
8019498: 601a str r2, [r3, #0]
result = ERR_OK;
801949a: 2300 movs r3, #0
801949c: f887 3027 strb.w r3, [r7, #39] ; 0x27
80194a0: e002 b.n 80194a8 <etharp_query+0x250>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
#endif /* ARP_QUEUEING */
} else {
ETHARP_STATS_INC(etharp.memerr);
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
result = ERR_MEM;
80194a2: 23ff movs r3, #255 ; 0xff
80194a4: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
}
return result;
80194a8: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
}
80194ac: 4618 mov r0, r3
80194ae: 3728 adds r7, #40 ; 0x28
80194b0: 46bd mov sp, r7
80194b2: bd80 pop {r7, pc}
80194b4: 0801e748 .word 0x0801e748
80194b8: 0801e8f4 .word 0x0801e8f4
80194bc: 0801e7c0 .word 0x0801e7c0
80194c0: 20008778 .word 0x20008778
80194c4: 0801e904 .word 0x0801e904
80194c8: 0801e8e8 .word 0x0801e8e8
80194cc: 20008868 .word 0x20008868
80194d0: 0801e92c .word 0x0801e92c
080194d4 <etharp_raw>:
etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
const struct eth_addr *ethdst_addr,
const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
const u16_t opcode)
{
80194d4: b580 push {r7, lr}
80194d6: b08a sub sp, #40 ; 0x28
80194d8: af02 add r7, sp, #8
80194da: 60f8 str r0, [r7, #12]
80194dc: 60b9 str r1, [r7, #8]
80194de: 607a str r2, [r7, #4]
80194e0: 603b str r3, [r7, #0]
struct pbuf *p;
err_t result = ERR_OK;
80194e2: 2300 movs r3, #0
80194e4: 77fb strb r3, [r7, #31]
struct etharp_hdr *hdr;
LWIP_ASSERT("netif != NULL", netif != NULL);
80194e6: 68fb ldr r3, [r7, #12]
80194e8: 2b00 cmp r3, #0
80194ea: d106 bne.n 80194fa <etharp_raw+0x26>
80194ec: 4b3a ldr r3, [pc, #232] ; (80195d8 <etharp_raw+0x104>)
80194ee: f240 4257 movw r2, #1111 ; 0x457
80194f2: 493a ldr r1, [pc, #232] ; (80195dc <etharp_raw+0x108>)
80194f4: 483a ldr r0, [pc, #232] ; (80195e0 <etharp_raw+0x10c>)
80194f6: f001 fd95 bl 801b024 <iprintf>
/* allocate a pbuf for the outgoing ARP request packet */
p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
80194fa: f44f 7220 mov.w r2, #640 ; 0x280
80194fe: 211c movs r1, #28
8019500: 200e movs r0, #14
8019502: f7f6 fd99 bl 8010038 <pbuf_alloc>
8019506: 61b8 str r0, [r7, #24]
/* could allocate a pbuf for an ARP request? */
if (p == NULL) {
8019508: 69bb ldr r3, [r7, #24]
801950a: 2b00 cmp r3, #0
801950c: d102 bne.n 8019514 <etharp_raw+0x40>
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("etharp_raw: could not allocate pbuf for ARP request.\n"));
ETHARP_STATS_INC(etharp.memerr);
return ERR_MEM;
801950e: f04f 33ff mov.w r3, #4294967295
8019512: e05d b.n 80195d0 <etharp_raw+0xfc>
}
LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
8019514: 69bb ldr r3, [r7, #24]
8019516: 895b ldrh r3, [r3, #10]
8019518: 2b1b cmp r3, #27
801951a: d806 bhi.n 801952a <etharp_raw+0x56>
801951c: 4b2e ldr r3, [pc, #184] ; (80195d8 <etharp_raw+0x104>)
801951e: f240 4263 movw r2, #1123 ; 0x463
8019522: 4930 ldr r1, [pc, #192] ; (80195e4 <etharp_raw+0x110>)
8019524: 482e ldr r0, [pc, #184] ; (80195e0 <etharp_raw+0x10c>)
8019526: f001 fd7d bl 801b024 <iprintf>
(p->len >= SIZEOF_ETHARP_HDR));
hdr = (struct etharp_hdr *)p->payload;
801952a: 69bb ldr r3, [r7, #24]
801952c: 685b ldr r3, [r3, #4]
801952e: 617b str r3, [r7, #20]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
hdr->opcode = lwip_htons(opcode);
8019530: 8ebb ldrh r3, [r7, #52] ; 0x34
8019532: 4618 mov r0, r3
8019534: f7f5 fcac bl 800ee90 <lwip_htons>
8019538: 4603 mov r3, r0
801953a: 461a mov r2, r3
801953c: 697b ldr r3, [r7, #20]
801953e: 80da strh r2, [r3, #6]
LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
8019540: 68fb ldr r3, [r7, #12]
8019542: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8019546: 2b06 cmp r3, #6
8019548: d006 beq.n 8019558 <etharp_raw+0x84>
801954a: 4b23 ldr r3, [pc, #140] ; (80195d8 <etharp_raw+0x104>)
801954c: f240 426a movw r2, #1130 ; 0x46a
8019550: 4925 ldr r1, [pc, #148] ; (80195e8 <etharp_raw+0x114>)
8019552: 4823 ldr r0, [pc, #140] ; (80195e0 <etharp_raw+0x10c>)
8019554: f001 fd66 bl 801b024 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
/* Write the ARP MAC-Addresses */
SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
8019558: 697b ldr r3, [r7, #20]
801955a: 3308 adds r3, #8
801955c: 2206 movs r2, #6
801955e: 6839 ldr r1, [r7, #0]
8019560: 4618 mov r0, r3
8019562: f001 fd4c bl 801affe <memcpy>
SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
8019566: 697b ldr r3, [r7, #20]
8019568: 3312 adds r3, #18
801956a: 2206 movs r2, #6
801956c: 6af9 ldr r1, [r7, #44] ; 0x2c
801956e: 4618 mov r0, r3
8019570: f001 fd45 bl 801affe <memcpy>
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
* structure packing. */
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
8019574: 697b ldr r3, [r7, #20]
8019576: 330e adds r3, #14
8019578: 6aba ldr r2, [r7, #40] ; 0x28
801957a: 6812 ldr r2, [r2, #0]
801957c: 601a str r2, [r3, #0]
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
801957e: 697b ldr r3, [r7, #20]
8019580: 3318 adds r3, #24
8019582: 6b3a ldr r2, [r7, #48] ; 0x30
8019584: 6812 ldr r2, [r2, #0]
8019586: 601a str r2, [r3, #0]
hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
8019588: 697b ldr r3, [r7, #20]
801958a: 2200 movs r2, #0
801958c: 701a strb r2, [r3, #0]
801958e: 2200 movs r2, #0
8019590: f042 0201 orr.w r2, r2, #1
8019594: 705a strb r2, [r3, #1]
hdr->proto = PP_HTONS(ETHTYPE_IP);
8019596: 697b ldr r3, [r7, #20]
8019598: 2200 movs r2, #0
801959a: f042 0208 orr.w r2, r2, #8
801959e: 709a strb r2, [r3, #2]
80195a0: 2200 movs r2, #0
80195a2: 70da strb r2, [r3, #3]
/* set hwlen and protolen */
hdr->hwlen = ETH_HWADDR_LEN;
80195a4: 697b ldr r3, [r7, #20]
80195a6: 2206 movs r2, #6
80195a8: 711a strb r2, [r3, #4]
hdr->protolen = sizeof(ip4_addr_t);
80195aa: 697b ldr r3, [r7, #20]
80195ac: 2204 movs r2, #4
80195ae: 715a strb r2, [r3, #5]
if (ip4_addr_islinklocal(ipsrc_addr)) {
ethernet_output(netif, p, ethsrc_addr, &ethbroadcast, ETHTYPE_ARP);
} else
#endif /* LWIP_AUTOIP */
{
ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
80195b0: f640 0306 movw r3, #2054 ; 0x806
80195b4: 9300 str r3, [sp, #0]
80195b6: 687b ldr r3, [r7, #4]
80195b8: 68ba ldr r2, [r7, #8]
80195ba: 69b9 ldr r1, [r7, #24]
80195bc: 68f8 ldr r0, [r7, #12]
80195be: f001 fb8d bl 801acdc <ethernet_output>
}
ETHARP_STATS_INC(etharp.xmit);
/* free ARP query packet */
pbuf_free(p);
80195c2: 69b8 ldr r0, [r7, #24]
80195c4: f7f7 f818 bl 80105f8 <pbuf_free>
p = NULL;
80195c8: 2300 movs r3, #0
80195ca: 61bb str r3, [r7, #24]
/* could not allocate pbuf for ARP request */
return result;
80195cc: f997 301f ldrsb.w r3, [r7, #31]
}
80195d0: 4618 mov r0, r3
80195d2: 3720 adds r7, #32
80195d4: 46bd mov sp, r7
80195d6: bd80 pop {r7, pc}
80195d8: 0801e748 .word 0x0801e748
80195dc: 0801e898 .word 0x0801e898
80195e0: 0801e7c0 .word 0x0801e7c0
80195e4: 0801e948 .word 0x0801e948
80195e8: 0801e97c .word 0x0801e97c
080195ec <etharp_request_dst>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
static err_t
etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
{
80195ec: b580 push {r7, lr}
80195ee: b088 sub sp, #32
80195f0: af04 add r7, sp, #16
80195f2: 60f8 str r0, [r7, #12]
80195f4: 60b9 str r1, [r7, #8]
80195f6: 607a str r2, [r7, #4]
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
80195f8: 68fb ldr r3, [r7, #12]
80195fa: f103 012a add.w r1, r3, #42 ; 0x2a
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), &ethzero,
80195fe: 68fb ldr r3, [r7, #12]
8019600: f103 002a add.w r0, r3, #42 ; 0x2a
8019604: 68fb ldr r3, [r7, #12]
8019606: 3304 adds r3, #4
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
8019608: 2201 movs r2, #1
801960a: 9203 str r2, [sp, #12]
801960c: 68ba ldr r2, [r7, #8]
801960e: 9202 str r2, [sp, #8]
8019610: 4a06 ldr r2, [pc, #24] ; (801962c <etharp_request_dst+0x40>)
8019612: 9201 str r2, [sp, #4]
8019614: 9300 str r3, [sp, #0]
8019616: 4603 mov r3, r0
8019618: 687a ldr r2, [r7, #4]
801961a: 68f8 ldr r0, [r7, #12]
801961c: f7ff ff5a bl 80194d4 <etharp_raw>
8019620: 4603 mov r3, r0
ipaddr, ARP_REQUEST);
}
8019622: 4618 mov r0, r3
8019624: 3710 adds r7, #16
8019626: 46bd mov sp, r7
8019628: bd80 pop {r7, pc}
801962a: bf00 nop
801962c: 08020e88 .word 0x08020e88
08019630 <etharp_request>:
* ERR_MEM if the ARP packet couldn't be allocated
* any other err_t on failure
*/
err_t
etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
{
8019630: b580 push {r7, lr}
8019632: b082 sub sp, #8
8019634: af00 add r7, sp, #0
8019636: 6078 str r0, [r7, #4]
8019638: 6039 str r1, [r7, #0]
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
return etharp_request_dst(netif, ipaddr, &ethbroadcast);
801963a: 4a05 ldr r2, [pc, #20] ; (8019650 <etharp_request+0x20>)
801963c: 6839 ldr r1, [r7, #0]
801963e: 6878 ldr r0, [r7, #4]
8019640: f7ff ffd4 bl 80195ec <etharp_request_dst>
8019644: 4603 mov r3, r0
}
8019646: 4618 mov r0, r3
8019648: 3708 adds r7, #8
801964a: 46bd mov sp, r7
801964c: bd80 pop {r7, pc}
801964e: bf00 nop
8019650: 08020e80 .word 0x08020e80
08019654 <icmp_input>:
* @param p the icmp echo request packet, p->payload pointing to the icmp header
* @param inp the netif on which this packet was received
*/
void
icmp_input(struct pbuf *p, struct netif *inp)
{
8019654: b580 push {r7, lr}
8019656: b08e sub sp, #56 ; 0x38
8019658: af04 add r7, sp, #16
801965a: 6078 str r0, [r7, #4]
801965c: 6039 str r1, [r7, #0]
const ip4_addr_t *src;
ICMP_STATS_INC(icmp.recv);
MIB2_STATS_INC(mib2.icmpinmsgs);
iphdr_in = ip4_current_header();
801965e: 4b79 ldr r3, [pc, #484] ; (8019844 <icmp_input+0x1f0>)
8019660: 689b ldr r3, [r3, #8]
8019662: 627b str r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(iphdr_in);
8019664: 6a7b ldr r3, [r7, #36] ; 0x24
8019666: 781b ldrb r3, [r3, #0]
8019668: f003 030f and.w r3, r3, #15
801966c: b2db uxtb r3, r3
801966e: 009b lsls r3, r3, #2
8019670: b2db uxtb r3, r3
8019672: 847b strh r3, [r7, #34] ; 0x22
if (hlen < IP_HLEN) {
8019674: 8c7b ldrh r3, [r7, #34] ; 0x22
8019676: 2b13 cmp r3, #19
8019678: f240 80cd bls.w 8019816 <icmp_input+0x1c2>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
goto lenerr;
}
if (p->len < sizeof(u16_t) * 2) {
801967c: 687b ldr r3, [r7, #4]
801967e: 895b ldrh r3, [r3, #10]
8019680: 2b03 cmp r3, #3
8019682: f240 80ca bls.w 801981a <icmp_input+0x1c6>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
goto lenerr;
}
type = *((u8_t *)p->payload);
8019686: 687b ldr r3, [r7, #4]
8019688: 685b ldr r3, [r3, #4]
801968a: 781b ldrb r3, [r3, #0]
801968c: f887 3021 strb.w r3, [r7, #33] ; 0x21
#ifdef LWIP_DEBUG
code = *(((u8_t *)p->payload) + 1);
/* if debug is enabled but debug statement below is somehow disabled: */
LWIP_UNUSED_ARG(code);
#endif /* LWIP_DEBUG */
switch (type) {
8019690: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
8019694: 2b00 cmp r3, #0
8019696: f000 80b7 beq.w 8019808 <icmp_input+0x1b4>
801969a: 2b08 cmp r3, #8
801969c: f040 80b7 bne.w 801980e <icmp_input+0x1ba>
(as obviously, an echo request has been sent, too). */
MIB2_STATS_INC(mib2.icmpinechoreps);
break;
case ICMP_ECHO:
MIB2_STATS_INC(mib2.icmpinechos);
src = ip4_current_dest_addr();
80196a0: 4b69 ldr r3, [pc, #420] ; (8019848 <icmp_input+0x1f4>)
80196a2: 61fb str r3, [r7, #28]
/* multicast destination address? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
80196a4: 4b67 ldr r3, [pc, #412] ; (8019844 <icmp_input+0x1f0>)
80196a6: 695b ldr r3, [r3, #20]
80196a8: f003 03f0 and.w r3, r3, #240 ; 0xf0
80196ac: 2be0 cmp r3, #224 ; 0xe0
80196ae: f000 80bb beq.w 8019828 <icmp_input+0x1d4>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
goto icmperr;
#endif /* LWIP_MULTICAST_PING */
}
/* broadcast destination address? */
if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
80196b2: 4b64 ldr r3, [pc, #400] ; (8019844 <icmp_input+0x1f0>)
80196b4: 695a ldr r2, [r3, #20]
80196b6: 4b63 ldr r3, [pc, #396] ; (8019844 <icmp_input+0x1f0>)
80196b8: 681b ldr r3, [r3, #0]
80196ba: 4619 mov r1, r3
80196bc: 4610 mov r0, r2
80196be: f000 fc09 bl 8019ed4 <ip4_addr_isbroadcast_u32>
80196c2: 4603 mov r3, r0
80196c4: 2b00 cmp r3, #0
80196c6: f040 80b1 bne.w 801982c <icmp_input+0x1d8>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
goto icmperr;
#endif /* LWIP_BROADCAST_PING */
}
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
80196ca: 687b ldr r3, [r7, #4]
80196cc: 891b ldrh r3, [r3, #8]
80196ce: 2b07 cmp r3, #7
80196d0: f240 80a5 bls.w 801981e <icmp_input+0x1ca>
return;
}
}
#endif
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
80196d4: 8c7b ldrh r3, [r7, #34] ; 0x22
80196d6: 330e adds r3, #14
80196d8: 4619 mov r1, r3
80196da: 6878 ldr r0, [r7, #4]
80196dc: f7f6 fef6 bl 80104cc <pbuf_add_header>
80196e0: 4603 mov r3, r0
80196e2: 2b00 cmp r3, #0
80196e4: d04b beq.n 801977e <icmp_input+0x12a>
/* p is not big enough to contain link headers
* allocate a new one and copy p into it
*/
struct pbuf *r;
u16_t alloc_len = (u16_t)(p->tot_len + hlen);
80196e6: 687b ldr r3, [r7, #4]
80196e8: 891a ldrh r2, [r3, #8]
80196ea: 8c7b ldrh r3, [r7, #34] ; 0x22
80196ec: 4413 add r3, r2
80196ee: 837b strh r3, [r7, #26]
if (alloc_len < p->tot_len) {
80196f0: 687b ldr r3, [r7, #4]
80196f2: 891b ldrh r3, [r3, #8]
80196f4: 8b7a ldrh r2, [r7, #26]
80196f6: 429a cmp r2, r3
80196f8: f0c0 809a bcc.w 8019830 <icmp_input+0x1dc>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
goto icmperr;
}
/* allocate new packet buffer with space for link headers */
r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
80196fc: 8b7b ldrh r3, [r7, #26]
80196fe: f44f 7220 mov.w r2, #640 ; 0x280
8019702: 4619 mov r1, r3
8019704: 200e movs r0, #14
8019706: f7f6 fc97 bl 8010038 <pbuf_alloc>
801970a: 6178 str r0, [r7, #20]
if (r == NULL) {
801970c: 697b ldr r3, [r7, #20]
801970e: 2b00 cmp r3, #0
8019710: f000 8090 beq.w 8019834 <icmp_input+0x1e0>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
goto icmperr;
}
if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
8019714: 697b ldr r3, [r7, #20]
8019716: 895b ldrh r3, [r3, #10]
8019718: 461a mov r2, r3
801971a: 8c7b ldrh r3, [r7, #34] ; 0x22
801971c: 3308 adds r3, #8
801971e: 429a cmp r2, r3
8019720: d203 bcs.n 801972a <icmp_input+0xd6>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
pbuf_free(r);
8019722: 6978 ldr r0, [r7, #20]
8019724: f7f6 ff68 bl 80105f8 <pbuf_free>
goto icmperr;
8019728: e085 b.n 8019836 <icmp_input+0x1e2>
}
/* copy the ip header */
MEMCPY(r->payload, iphdr_in, hlen);
801972a: 697b ldr r3, [r7, #20]
801972c: 685b ldr r3, [r3, #4]
801972e: 8c7a ldrh r2, [r7, #34] ; 0x22
8019730: 6a79 ldr r1, [r7, #36] ; 0x24
8019732: 4618 mov r0, r3
8019734: f001 fc63 bl 801affe <memcpy>
/* switch r->payload back to icmp header (cannot fail) */
if (pbuf_remove_header(r, hlen)) {
8019738: 8c7b ldrh r3, [r7, #34] ; 0x22
801973a: 4619 mov r1, r3
801973c: 6978 ldr r0, [r7, #20]
801973e: f7f6 fed5 bl 80104ec <pbuf_remove_header>
8019742: 4603 mov r3, r0
8019744: 2b00 cmp r3, #0
8019746: d009 beq.n 801975c <icmp_input+0x108>
LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
8019748: 4b40 ldr r3, [pc, #256] ; (801984c <icmp_input+0x1f8>)
801974a: 22b6 movs r2, #182 ; 0xb6
801974c: 4940 ldr r1, [pc, #256] ; (8019850 <icmp_input+0x1fc>)
801974e: 4841 ldr r0, [pc, #260] ; (8019854 <icmp_input+0x200>)
8019750: f001 fc68 bl 801b024 <iprintf>
pbuf_free(r);
8019754: 6978 ldr r0, [r7, #20]
8019756: f7f6 ff4f bl 80105f8 <pbuf_free>
goto icmperr;
801975a: e06c b.n 8019836 <icmp_input+0x1e2>
}
/* copy the rest of the packet without ip header */
if (pbuf_copy(r, p) != ERR_OK) {
801975c: 6879 ldr r1, [r7, #4]
801975e: 6978 ldr r0, [r7, #20]
8019760: f7f7 f87e bl 8010860 <pbuf_copy>
8019764: 4603 mov r3, r0
8019766: 2b00 cmp r3, #0
8019768: d003 beq.n 8019772 <icmp_input+0x11e>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
pbuf_free(r);
801976a: 6978 ldr r0, [r7, #20]
801976c: f7f6 ff44 bl 80105f8 <pbuf_free>
goto icmperr;
8019770: e061 b.n 8019836 <icmp_input+0x1e2>
}
/* free the original p */
pbuf_free(p);
8019772: 6878 ldr r0, [r7, #4]
8019774: f7f6 ff40 bl 80105f8 <pbuf_free>
/* we now have an identical copy of p that has room for link headers */
p = r;
8019778: 697b ldr r3, [r7, #20]
801977a: 607b str r3, [r7, #4]
801977c: e00f b.n 801979e <icmp_input+0x14a>
} else {
/* restore p->payload to point to icmp header (cannot fail) */
if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
801977e: 8c7b ldrh r3, [r7, #34] ; 0x22
8019780: 330e adds r3, #14
8019782: 4619 mov r1, r3
8019784: 6878 ldr r0, [r7, #4]
8019786: f7f6 feb1 bl 80104ec <pbuf_remove_header>
801978a: 4603 mov r3, r0
801978c: 2b00 cmp r3, #0
801978e: d006 beq.n 801979e <icmp_input+0x14a>
LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
8019790: 4b2e ldr r3, [pc, #184] ; (801984c <icmp_input+0x1f8>)
8019792: 22c7 movs r2, #199 ; 0xc7
8019794: 4930 ldr r1, [pc, #192] ; (8019858 <icmp_input+0x204>)
8019796: 482f ldr r0, [pc, #188] ; (8019854 <icmp_input+0x200>)
8019798: f001 fc44 bl 801b024 <iprintf>
goto icmperr;
801979c: e04b b.n 8019836 <icmp_input+0x1e2>
}
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
/* At this point, all checks are OK. */
/* We generate an answer by switching the dest and src ip addresses,
* setting the icmp type to ECHO_RESPONSE and updating the checksum. */
iecho = (struct icmp_echo_hdr *)p->payload;
801979e: 687b ldr r3, [r7, #4]
80197a0: 685b ldr r3, [r3, #4]
80197a2: 613b str r3, [r7, #16]
if (pbuf_add_header(p, hlen)) {
80197a4: 8c7b ldrh r3, [r7, #34] ; 0x22
80197a6: 4619 mov r1, r3
80197a8: 6878 ldr r0, [r7, #4]
80197aa: f7f6 fe8f bl 80104cc <pbuf_add_header>
80197ae: 4603 mov r3, r0
80197b0: 2b00 cmp r3, #0
80197b2: d12b bne.n 801980c <icmp_input+0x1b8>
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
} else {
err_t ret;
struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
80197b4: 687b ldr r3, [r7, #4]
80197b6: 685b ldr r3, [r3, #4]
80197b8: 60fb str r3, [r7, #12]
ip4_addr_copy(iphdr->src, *src);
80197ba: 69fb ldr r3, [r7, #28]
80197bc: 681a ldr r2, [r3, #0]
80197be: 68fb ldr r3, [r7, #12]
80197c0: 60da str r2, [r3, #12]
ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
80197c2: 4b20 ldr r3, [pc, #128] ; (8019844 <icmp_input+0x1f0>)
80197c4: 691a ldr r2, [r3, #16]
80197c6: 68fb ldr r3, [r7, #12]
80197c8: 611a str r2, [r3, #16]
ICMPH_TYPE_SET(iecho, ICMP_ER);
80197ca: 693b ldr r3, [r7, #16]
80197cc: 2200 movs r2, #0
80197ce: 701a strb r2, [r3, #0]
else {
iecho->chksum = 0;
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
#else /* CHECKSUM_GEN_ICMP */
iecho->chksum = 0;
80197d0: 693b ldr r3, [r7, #16]
80197d2: 2200 movs r2, #0
80197d4: 709a strb r2, [r3, #2]
80197d6: 2200 movs r2, #0
80197d8: 70da strb r2, [r3, #3]
#endif /* CHECKSUM_GEN_ICMP */
/* Set the correct TTL and recalculate the header checksum. */
IPH_TTL_SET(iphdr, ICMP_TTL);
80197da: 68fb ldr r3, [r7, #12]
80197dc: 22ff movs r2, #255 ; 0xff
80197de: 721a strb r2, [r3, #8]
IPH_CHKSUM_SET(iphdr, 0);
80197e0: 68fb ldr r3, [r7, #12]
80197e2: 2200 movs r2, #0
80197e4: 729a strb r2, [r3, #10]
80197e6: 2200 movs r2, #0
80197e8: 72da strb r2, [r3, #11]
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* increase number of echo replies attempted to send */
MIB2_STATS_INC(mib2.icmpoutechoreps);
/* send an ICMP packet */
ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
80197ea: 683b ldr r3, [r7, #0]
80197ec: 9302 str r3, [sp, #8]
80197ee: 2301 movs r3, #1
80197f0: 9301 str r3, [sp, #4]
80197f2: 2300 movs r3, #0
80197f4: 9300 str r3, [sp, #0]
80197f6: 23ff movs r3, #255 ; 0xff
80197f8: 2200 movs r2, #0
80197fa: 69f9 ldr r1, [r7, #28]
80197fc: 6878 ldr r0, [r7, #4]
80197fe: f000 fa91 bl 8019d24 <ip4_output_if>
8019802: 4603 mov r3, r0
8019804: 72fb strb r3, [r7, #11]
ICMP_TTL, 0, IP_PROTO_ICMP, inp);
if (ret != ERR_OK) {
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
}
}
break;
8019806: e001 b.n 801980c <icmp_input+0x1b8>
break;
8019808: bf00 nop
801980a: e000 b.n 801980e <icmp_input+0x1ba>
break;
801980c: bf00 nop
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
(s16_t)type, (s16_t)code));
ICMP_STATS_INC(icmp.proterr);
ICMP_STATS_INC(icmp.drop);
}
pbuf_free(p);
801980e: 6878 ldr r0, [r7, #4]
8019810: f7f6 fef2 bl 80105f8 <pbuf_free>
return;
8019814: e013 b.n 801983e <icmp_input+0x1ea>
goto lenerr;
8019816: bf00 nop
8019818: e002 b.n 8019820 <icmp_input+0x1cc>
goto lenerr;
801981a: bf00 nop
801981c: e000 b.n 8019820 <icmp_input+0x1cc>
goto lenerr;
801981e: bf00 nop
lenerr:
pbuf_free(p);
8019820: 6878 ldr r0, [r7, #4]
8019822: f7f6 fee9 bl 80105f8 <pbuf_free>
ICMP_STATS_INC(icmp.lenerr);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
8019826: e00a b.n 801983e <icmp_input+0x1ea>
goto icmperr;
8019828: bf00 nop
801982a: e004 b.n 8019836 <icmp_input+0x1e2>
goto icmperr;
801982c: bf00 nop
801982e: e002 b.n 8019836 <icmp_input+0x1e2>
goto icmperr;
8019830: bf00 nop
8019832: e000 b.n 8019836 <icmp_input+0x1e2>
goto icmperr;
8019834: bf00 nop
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
icmperr:
pbuf_free(p);
8019836: 6878 ldr r0, [r7, #4]
8019838: f7f6 fede bl 80105f8 <pbuf_free>
ICMP_STATS_INC(icmp.err);
MIB2_STATS_INC(mib2.icmpinerrors);
return;
801983c: bf00 nop
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
}
801983e: 3728 adds r7, #40 ; 0x28
8019840: 46bd mov sp, r7
8019842: bd80 pop {r7, pc}
8019844: 2000be8c .word 0x2000be8c
8019848: 2000bea0 .word 0x2000bea0
801984c: 0801e9c0 .word 0x0801e9c0
8019850: 0801e9f8 .word 0x0801e9f8
8019854: 0801ea30 .word 0x0801ea30
8019858: 0801ea58 .word 0x0801ea58
0801985c <icmp_dest_unreach>:
* p->payload pointing to the IP header
* @param t type of the 'unreachable' packet
*/
void
icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
{
801985c: b580 push {r7, lr}
801985e: b082 sub sp, #8
8019860: af00 add r7, sp, #0
8019862: 6078 str r0, [r7, #4]
8019864: 460b mov r3, r1
8019866: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpoutdestunreachs);
icmp_send_response(p, ICMP_DUR, t);
8019868: 78fb ldrb r3, [r7, #3]
801986a: 461a mov r2, r3
801986c: 2103 movs r1, #3
801986e: 6878 ldr r0, [r7, #4]
8019870: f000 f814 bl 801989c <icmp_send_response>
}
8019874: bf00 nop
8019876: 3708 adds r7, #8
8019878: 46bd mov sp, r7
801987a: bd80 pop {r7, pc}
0801987c <icmp_time_exceeded>:
* p->payload pointing to the IP header
* @param t type of the 'time exceeded' packet
*/
void
icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
{
801987c: b580 push {r7, lr}
801987e: b082 sub sp, #8
8019880: af00 add r7, sp, #0
8019882: 6078 str r0, [r7, #4]
8019884: 460b mov r3, r1
8019886: 70fb strb r3, [r7, #3]
MIB2_STATS_INC(mib2.icmpouttimeexcds);
icmp_send_response(p, ICMP_TE, t);
8019888: 78fb ldrb r3, [r7, #3]
801988a: 461a mov r2, r3
801988c: 210b movs r1, #11
801988e: 6878 ldr r0, [r7, #4]
8019890: f000 f804 bl 801989c <icmp_send_response>
}
8019894: bf00 nop
8019896: 3708 adds r7, #8
8019898: 46bd mov sp, r7
801989a: bd80 pop {r7, pc}
0801989c <icmp_send_response>:
* @param type Type of the ICMP header
* @param code Code of the ICMP header
*/
static void
icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
{
801989c: b580 push {r7, lr}
801989e: b08c sub sp, #48 ; 0x30
80198a0: af04 add r7, sp, #16
80198a2: 6078 str r0, [r7, #4]
80198a4: 460b mov r3, r1
80198a6: 70fb strb r3, [r7, #3]
80198a8: 4613 mov r3, r2
80198aa: 70bb strb r3, [r7, #2]
/* increase number of messages attempted to send */
MIB2_STATS_INC(mib2.icmpoutmsgs);
/* ICMP header + IP header + 8 bytes of data */
q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
80198ac: f44f 7220 mov.w r2, #640 ; 0x280
80198b0: 2124 movs r1, #36 ; 0x24
80198b2: 2022 movs r0, #34 ; 0x22
80198b4: f7f6 fbc0 bl 8010038 <pbuf_alloc>
80198b8: 61f8 str r0, [r7, #28]
PBUF_RAM);
if (q == NULL) {
80198ba: 69fb ldr r3, [r7, #28]
80198bc: 2b00 cmp r3, #0
80198be: d04c beq.n 801995a <icmp_send_response+0xbe>
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
MIB2_STATS_INC(mib2.icmpouterrors);
return;
}
LWIP_ASSERT("check that first pbuf can hold icmp message",
80198c0: 69fb ldr r3, [r7, #28]
80198c2: 895b ldrh r3, [r3, #10]
80198c4: 2b23 cmp r3, #35 ; 0x23
80198c6: d806 bhi.n 80198d6 <icmp_send_response+0x3a>
80198c8: 4b26 ldr r3, [pc, #152] ; (8019964 <icmp_send_response+0xc8>)
80198ca: f240 1269 movw r2, #361 ; 0x169
80198ce: 4926 ldr r1, [pc, #152] ; (8019968 <icmp_send_response+0xcc>)
80198d0: 4826 ldr r0, [pc, #152] ; (801996c <icmp_send_response+0xd0>)
80198d2: f001 fba7 bl 801b024 <iprintf>
(q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
iphdr = (struct ip_hdr *)p->payload;
80198d6: 687b ldr r3, [r7, #4]
80198d8: 685b ldr r3, [r3, #4]
80198da: 61bb str r3, [r7, #24]
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
LWIP_DEBUGF(ICMP_DEBUG, (" to "));
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
icmphdr = (struct icmp_echo_hdr *)q->payload;
80198dc: 69fb ldr r3, [r7, #28]
80198de: 685b ldr r3, [r3, #4]
80198e0: 617b str r3, [r7, #20]
icmphdr->type = type;
80198e2: 697b ldr r3, [r7, #20]
80198e4: 78fa ldrb r2, [r7, #3]
80198e6: 701a strb r2, [r3, #0]
icmphdr->code = code;
80198e8: 697b ldr r3, [r7, #20]
80198ea: 78ba ldrb r2, [r7, #2]
80198ec: 705a strb r2, [r3, #1]
icmphdr->id = 0;
80198ee: 697b ldr r3, [r7, #20]
80198f0: 2200 movs r2, #0
80198f2: 711a strb r2, [r3, #4]
80198f4: 2200 movs r2, #0
80198f6: 715a strb r2, [r3, #5]
icmphdr->seqno = 0;
80198f8: 697b ldr r3, [r7, #20]
80198fa: 2200 movs r2, #0
80198fc: 719a strb r2, [r3, #6]
80198fe: 2200 movs r2, #0
8019900: 71da strb r2, [r3, #7]
/* copy fields from original packet */
SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
8019902: 69fb ldr r3, [r7, #28]
8019904: 685b ldr r3, [r3, #4]
8019906: f103 0008 add.w r0, r3, #8
801990a: 687b ldr r3, [r7, #4]
801990c: 685b ldr r3, [r3, #4]
801990e: 221c movs r2, #28
8019910: 4619 mov r1, r3
8019912: f001 fb74 bl 801affe <memcpy>
IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
ip4_addr_copy(iphdr_src, iphdr->src);
8019916: 69bb ldr r3, [r7, #24]
8019918: 68db ldr r3, [r3, #12]
801991a: 60fb str r3, [r7, #12]
ip4_addr_t iphdr_dst;
ip4_addr_copy(iphdr_dst, iphdr->dest);
netif = ip4_route_src(&iphdr_dst, &iphdr_src);
}
#else
netif = ip4_route(&iphdr_src);
801991c: f107 030c add.w r3, r7, #12
8019920: 4618 mov r0, r3
8019922: f000 f825 bl 8019970 <ip4_route>
8019926: 6138 str r0, [r7, #16]
#endif
if (netif != NULL) {
8019928: 693b ldr r3, [r7, #16]
801992a: 2b00 cmp r3, #0
801992c: d011 beq.n 8019952 <icmp_send_response+0xb6>
/* calculate checksum */
icmphdr->chksum = 0;
801992e: 697b ldr r3, [r7, #20]
8019930: 2200 movs r2, #0
8019932: 709a strb r2, [r3, #2]
8019934: 2200 movs r2, #0
8019936: 70da strb r2, [r3, #3]
IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
icmphdr->chksum = inet_chksum(icmphdr, q->len);
}
#endif
ICMP_STATS_INC(icmp.xmit);
ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
8019938: f107 020c add.w r2, r7, #12
801993c: 693b ldr r3, [r7, #16]
801993e: 9302 str r3, [sp, #8]
8019940: 2301 movs r3, #1
8019942: 9301 str r3, [sp, #4]
8019944: 2300 movs r3, #0
8019946: 9300 str r3, [sp, #0]
8019948: 23ff movs r3, #255 ; 0xff
801994a: 2100 movs r1, #0
801994c: 69f8 ldr r0, [r7, #28]
801994e: f000 f9e9 bl 8019d24 <ip4_output_if>
}
pbuf_free(q);
8019952: 69f8 ldr r0, [r7, #28]
8019954: f7f6 fe50 bl 80105f8 <pbuf_free>
8019958: e000 b.n 801995c <icmp_send_response+0xc0>
return;
801995a: bf00 nop
}
801995c: 3720 adds r7, #32
801995e: 46bd mov sp, r7
8019960: bd80 pop {r7, pc}
8019962: bf00 nop
8019964: 0801e9c0 .word 0x0801e9c0
8019968: 0801ea8c .word 0x0801ea8c
801996c: 0801ea30 .word 0x0801ea30
08019970 <ip4_route>:
* @param dest the destination IP address for which to find the route
* @return the netif on which to send to reach dest
*/
struct netif *
ip4_route(const ip4_addr_t *dest)
{
8019970: b480 push {r7}
8019972: b085 sub sp, #20
8019974: af00 add r7, sp, #0
8019976: 6078 str r0, [r7, #4]
/* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
LWIP_UNUSED_ARG(dest);
/* iterate through netifs */
NETIF_FOREACH(netif) {
8019978: 4b33 ldr r3, [pc, #204] ; (8019a48 <ip4_route+0xd8>)
801997a: 681b ldr r3, [r3, #0]
801997c: 60fb str r3, [r7, #12]
801997e: e036 b.n 80199ee <ip4_route+0x7e>
/* is the netif up, does it have a link and a valid address? */
if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
8019980: 68fb ldr r3, [r7, #12]
8019982: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019986: f003 0301 and.w r3, r3, #1
801998a: b2db uxtb r3, r3
801998c: 2b00 cmp r3, #0
801998e: d02b beq.n 80199e8 <ip4_route+0x78>
8019990: 68fb ldr r3, [r7, #12]
8019992: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019996: 089b lsrs r3, r3, #2
8019998: f003 0301 and.w r3, r3, #1
801999c: b2db uxtb r3, r3
801999e: 2b00 cmp r3, #0
80199a0: d022 beq.n 80199e8 <ip4_route+0x78>
80199a2: 68fb ldr r3, [r7, #12]
80199a4: 3304 adds r3, #4
80199a6: 681b ldr r3, [r3, #0]
80199a8: 2b00 cmp r3, #0
80199aa: d01d beq.n 80199e8 <ip4_route+0x78>
/* network mask matches? */
if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
80199ac: 687b ldr r3, [r7, #4]
80199ae: 681a ldr r2, [r3, #0]
80199b0: 68fb ldr r3, [r7, #12]
80199b2: 3304 adds r3, #4
80199b4: 681b ldr r3, [r3, #0]
80199b6: 405a eors r2, r3
80199b8: 68fb ldr r3, [r7, #12]
80199ba: 3308 adds r3, #8
80199bc: 681b ldr r3, [r3, #0]
80199be: 4013 ands r3, r2
80199c0: 2b00 cmp r3, #0
80199c2: d101 bne.n 80199c8 <ip4_route+0x58>
/* return netif on which to forward IP packet */
return netif;
80199c4: 68fb ldr r3, [r7, #12]
80199c6: e038 b.n 8019a3a <ip4_route+0xca>
}
/* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
80199c8: 68fb ldr r3, [r7, #12]
80199ca: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80199ce: f003 0302 and.w r3, r3, #2
80199d2: 2b00 cmp r3, #0
80199d4: d108 bne.n 80199e8 <ip4_route+0x78>
80199d6: 687b ldr r3, [r7, #4]
80199d8: 681a ldr r2, [r3, #0]
80199da: 68fb ldr r3, [r7, #12]
80199dc: 330c adds r3, #12
80199de: 681b ldr r3, [r3, #0]
80199e0: 429a cmp r2, r3
80199e2: d101 bne.n 80199e8 <ip4_route+0x78>
/* return netif on which to forward IP packet */
return netif;
80199e4: 68fb ldr r3, [r7, #12]
80199e6: e028 b.n 8019a3a <ip4_route+0xca>
NETIF_FOREACH(netif) {
80199e8: 68fb ldr r3, [r7, #12]
80199ea: 681b ldr r3, [r3, #0]
80199ec: 60fb str r3, [r7, #12]
80199ee: 68fb ldr r3, [r7, #12]
80199f0: 2b00 cmp r3, #0
80199f2: d1c5 bne.n 8019980 <ip4_route+0x10>
return netif;
}
#endif
#endif /* !LWIP_SINGLE_NETIF */
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
80199f4: 4b15 ldr r3, [pc, #84] ; (8019a4c <ip4_route+0xdc>)
80199f6: 681b ldr r3, [r3, #0]
80199f8: 2b00 cmp r3, #0
80199fa: d01a beq.n 8019a32 <ip4_route+0xc2>
80199fc: 4b13 ldr r3, [pc, #76] ; (8019a4c <ip4_route+0xdc>)
80199fe: 681b ldr r3, [r3, #0]
8019a00: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019a04: f003 0301 and.w r3, r3, #1
8019a08: 2b00 cmp r3, #0
8019a0a: d012 beq.n 8019a32 <ip4_route+0xc2>
8019a0c: 4b0f ldr r3, [pc, #60] ; (8019a4c <ip4_route+0xdc>)
8019a0e: 681b ldr r3, [r3, #0]
8019a10: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019a14: f003 0304 and.w r3, r3, #4
8019a18: 2b00 cmp r3, #0
8019a1a: d00a beq.n 8019a32 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
8019a1c: 4b0b ldr r3, [pc, #44] ; (8019a4c <ip4_route+0xdc>)
8019a1e: 681b ldr r3, [r3, #0]
8019a20: 3304 adds r3, #4
8019a22: 681b ldr r3, [r3, #0]
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
8019a24: 2b00 cmp r3, #0
8019a26: d004 beq.n 8019a32 <ip4_route+0xc2>
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
8019a28: 687b ldr r3, [r7, #4]
8019a2a: 681b ldr r3, [r3, #0]
8019a2c: b2db uxtb r3, r3
8019a2e: 2b7f cmp r3, #127 ; 0x7f
8019a30: d101 bne.n 8019a36 <ip4_route+0xc6>
If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
IP_STATS_INC(ip.rterr);
MIB2_STATS_INC(mib2.ipoutnoroutes);
return NULL;
8019a32: 2300 movs r3, #0
8019a34: e001 b.n 8019a3a <ip4_route+0xca>
}
return netif_default;
8019a36: 4b05 ldr r3, [pc, #20] ; (8019a4c <ip4_route+0xdc>)
8019a38: 681b ldr r3, [r3, #0]
}
8019a3a: 4618 mov r0, r3
8019a3c: 3714 adds r7, #20
8019a3e: 46bd mov sp, r7
8019a40: f85d 7b04 ldr.w r7, [sp], #4
8019a44: 4770 bx lr
8019a46: bf00 nop
8019a48: 2000f5b0 .word 0x2000f5b0
8019a4c: 2000f5b4 .word 0x2000f5b4
08019a50 <ip4_input_accept>:
#endif /* IP_FORWARD */
/** Return true if the current input packet should be accepted on this netif */
static int
ip4_input_accept(struct netif *netif)
{
8019a50: b580 push {r7, lr}
8019a52: b082 sub sp, #8
8019a54: af00 add r7, sp, #0
8019a56: 6078 str r0, [r7, #4]
ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
/* interface is up and configured? */
if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
8019a58: 687b ldr r3, [r7, #4]
8019a5a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019a5e: f003 0301 and.w r3, r3, #1
8019a62: b2db uxtb r3, r3
8019a64: 2b00 cmp r3, #0
8019a66: d016 beq.n 8019a96 <ip4_input_accept+0x46>
8019a68: 687b ldr r3, [r7, #4]
8019a6a: 3304 adds r3, #4
8019a6c: 681b ldr r3, [r3, #0]
8019a6e: 2b00 cmp r3, #0
8019a70: d011 beq.n 8019a96 <ip4_input_accept+0x46>
/* unicast to this interface address? */
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a72: 4b0b ldr r3, [pc, #44] ; (8019aa0 <ip4_input_accept+0x50>)
8019a74: 695a ldr r2, [r3, #20]
8019a76: 687b ldr r3, [r7, #4]
8019a78: 3304 adds r3, #4
8019a7a: 681b ldr r3, [r3, #0]
8019a7c: 429a cmp r2, r3
8019a7e: d008 beq.n 8019a92 <ip4_input_accept+0x42>
/* or broadcast on this interface network address? */
ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
8019a80: 4b07 ldr r3, [pc, #28] ; (8019aa0 <ip4_input_accept+0x50>)
8019a82: 695b ldr r3, [r3, #20]
8019a84: 6879 ldr r1, [r7, #4]
8019a86: 4618 mov r0, r3
8019a88: f000 fa24 bl 8019ed4 <ip4_addr_isbroadcast_u32>
8019a8c: 4603 mov r3, r0
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
8019a8e: 2b00 cmp r3, #0
8019a90: d001 beq.n 8019a96 <ip4_input_accept+0x46>
#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
) {
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
netif->name[0], netif->name[1]));
/* accept on this netif */
return 1;
8019a92: 2301 movs r3, #1
8019a94: e000 b.n 8019a98 <ip4_input_accept+0x48>
/* accept on this netif */
return 1;
}
#endif /* LWIP_AUTOIP */
}
return 0;
8019a96: 2300 movs r3, #0
}
8019a98: 4618 mov r0, r3
8019a9a: 3708 adds r7, #8
8019a9c: 46bd mov sp, r7
8019a9e: bd80 pop {r7, pc}
8019aa0: 2000be8c .word 0x2000be8c
08019aa4 <ip4_input>:
* @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
* processed, but currently always returns ERR_OK)
*/
err_t
ip4_input(struct pbuf *p, struct netif *inp)
{
8019aa4: b580 push {r7, lr}
8019aa6: b088 sub sp, #32
8019aa8: af00 add r7, sp, #0
8019aaa: 6078 str r0, [r7, #4]
8019aac: 6039 str r1, [r7, #0]
const struct ip_hdr *iphdr;
struct netif *netif;
u16_t iphdr_hlen;
u16_t iphdr_len;
#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP
int check_ip_src = 1;
8019aae: 2301 movs r3, #1
8019ab0: 617b str r3, [r7, #20]
IP_STATS_INC(ip.recv);
MIB2_STATS_INC(mib2.ipinreceives);
/* identify the IP header */
iphdr = (struct ip_hdr *)p->payload;
8019ab2: 687b ldr r3, [r7, #4]
8019ab4: 685b ldr r3, [r3, #4]
8019ab6: 61fb str r3, [r7, #28]
if (IPH_V(iphdr) != 4) {
8019ab8: 69fb ldr r3, [r7, #28]
8019aba: 781b ldrb r3, [r3, #0]
8019abc: 091b lsrs r3, r3, #4
8019abe: b2db uxtb r3, r3
8019ac0: 2b04 cmp r3, #4
8019ac2: d004 beq.n 8019ace <ip4_input+0x2a>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
ip4_debug_print(p);
pbuf_free(p);
8019ac4: 6878 ldr r0, [r7, #4]
8019ac6: f7f6 fd97 bl 80105f8 <pbuf_free>
IP_STATS_INC(ip.err);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinhdrerrors);
return ERR_OK;
8019aca: 2300 movs r3, #0
8019acc: e121 b.n 8019d12 <ip4_input+0x26e>
return ERR_OK;
}
#endif
/* obtain IP header length in bytes */
iphdr_hlen = IPH_HL_BYTES(iphdr);
8019ace: 69fb ldr r3, [r7, #28]
8019ad0: 781b ldrb r3, [r3, #0]
8019ad2: f003 030f and.w r3, r3, #15
8019ad6: b2db uxtb r3, r3
8019ad8: 009b lsls r3, r3, #2
8019ada: b2db uxtb r3, r3
8019adc: 827b strh r3, [r7, #18]
/* obtain ip length in bytes */
iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
8019ade: 69fb ldr r3, [r7, #28]
8019ae0: 885b ldrh r3, [r3, #2]
8019ae2: b29b uxth r3, r3
8019ae4: 4618 mov r0, r3
8019ae6: f7f5 f9d3 bl 800ee90 <lwip_htons>
8019aea: 4603 mov r3, r0
8019aec: 823b strh r3, [r7, #16]
/* Trim pbuf. This is especially required for packets < 60 bytes. */
if (iphdr_len < p->tot_len) {
8019aee: 687b ldr r3, [r7, #4]
8019af0: 891b ldrh r3, [r3, #8]
8019af2: 8a3a ldrh r2, [r7, #16]
8019af4: 429a cmp r2, r3
8019af6: d204 bcs.n 8019b02 <ip4_input+0x5e>
pbuf_realloc(p, iphdr_len);
8019af8: 8a3b ldrh r3, [r7, #16]
8019afa: 4619 mov r1, r3
8019afc: 6878 ldr r0, [r7, #4]
8019afe: f7f6 fbf5 bl 80102ec <pbuf_realloc>
}
/* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
8019b02: 687b ldr r3, [r7, #4]
8019b04: 895b ldrh r3, [r3, #10]
8019b06: 8a7a ldrh r2, [r7, #18]
8019b08: 429a cmp r2, r3
8019b0a: d807 bhi.n 8019b1c <ip4_input+0x78>
8019b0c: 687b ldr r3, [r7, #4]
8019b0e: 891b ldrh r3, [r3, #8]
8019b10: 8a3a ldrh r2, [r7, #16]
8019b12: 429a cmp r2, r3
8019b14: d802 bhi.n 8019b1c <ip4_input+0x78>
8019b16: 8a7b ldrh r3, [r7, #18]
8019b18: 2b13 cmp r3, #19
8019b1a: d804 bhi.n 8019b26 <ip4_input+0x82>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
iphdr_len, p->tot_len));
}
/* free (drop) packet pbufs */
pbuf_free(p);
8019b1c: 6878 ldr r0, [r7, #4]
8019b1e: f7f6 fd6b bl 80105f8 <pbuf_free>
IP_STATS_INC(ip.lenerr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019b22: 2300 movs r3, #0
8019b24: e0f5 b.n 8019d12 <ip4_input+0x26e>
}
}
#endif
/* copy IP addresses to aligned ip_addr_t */
ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
8019b26: 69fb ldr r3, [r7, #28]
8019b28: 691b ldr r3, [r3, #16]
8019b2a: 4a7c ldr r2, [pc, #496] ; (8019d1c <ip4_input+0x278>)
8019b2c: 6153 str r3, [r2, #20]
ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
8019b2e: 69fb ldr r3, [r7, #28]
8019b30: 68db ldr r3, [r3, #12]
8019b32: 4a7a ldr r2, [pc, #488] ; (8019d1c <ip4_input+0x278>)
8019b34: 6113 str r3, [r2, #16]
/* match packet against an interface, i.e. is this packet for us? */
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019b36: 4b79 ldr r3, [pc, #484] ; (8019d1c <ip4_input+0x278>)
8019b38: 695b ldr r3, [r3, #20]
8019b3a: f003 03f0 and.w r3, r3, #240 ; 0xf0
8019b3e: 2be0 cmp r3, #224 ; 0xe0
8019b40: d112 bne.n 8019b68 <ip4_input+0xc4>
netif = inp;
} else {
netif = NULL;
}
#else /* LWIP_IGMP */
if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
8019b42: 683b ldr r3, [r7, #0]
8019b44: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019b48: f003 0301 and.w r3, r3, #1
8019b4c: b2db uxtb r3, r3
8019b4e: 2b00 cmp r3, #0
8019b50: d007 beq.n 8019b62 <ip4_input+0xbe>
8019b52: 683b ldr r3, [r7, #0]
8019b54: 3304 adds r3, #4
8019b56: 681b ldr r3, [r3, #0]
8019b58: 2b00 cmp r3, #0
8019b5a: d002 beq.n 8019b62 <ip4_input+0xbe>
netif = inp;
8019b5c: 683b ldr r3, [r7, #0]
8019b5e: 61bb str r3, [r7, #24]
8019b60: e02a b.n 8019bb8 <ip4_input+0x114>
} else {
netif = NULL;
8019b62: 2300 movs r3, #0
8019b64: 61bb str r3, [r7, #24]
8019b66: e027 b.n 8019bb8 <ip4_input+0x114>
}
#endif /* LWIP_IGMP */
} else {
/* start trying with inp. if that's not acceptable, start walking the
list of configured netifs. */
if (ip4_input_accept(inp)) {
8019b68: 6838 ldr r0, [r7, #0]
8019b6a: f7ff ff71 bl 8019a50 <ip4_input_accept>
8019b6e: 4603 mov r3, r0
8019b70: 2b00 cmp r3, #0
8019b72: d002 beq.n 8019b7a <ip4_input+0xd6>
netif = inp;
8019b74: 683b ldr r3, [r7, #0]
8019b76: 61bb str r3, [r7, #24]
8019b78: e01e b.n 8019bb8 <ip4_input+0x114>
} else {
netif = NULL;
8019b7a: 2300 movs r3, #0
8019b7c: 61bb str r3, [r7, #24]
#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
/* Packets sent to the loopback address must not be accepted on an
* interface that does not have the loopback address assigned to it,
* unless a non-loopback interface is used for loopback traffic. */
if (!ip4_addr_isloopback(ip4_current_dest_addr()))
8019b7e: 4b67 ldr r3, [pc, #412] ; (8019d1c <ip4_input+0x278>)
8019b80: 695b ldr r3, [r3, #20]
8019b82: b2db uxtb r3, r3
8019b84: 2b7f cmp r3, #127 ; 0x7f
8019b86: d017 beq.n 8019bb8 <ip4_input+0x114>
#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
{
#if !LWIP_SINGLE_NETIF
NETIF_FOREACH(netif) {
8019b88: 4b65 ldr r3, [pc, #404] ; (8019d20 <ip4_input+0x27c>)
8019b8a: 681b ldr r3, [r3, #0]
8019b8c: 61bb str r3, [r7, #24]
8019b8e: e00e b.n 8019bae <ip4_input+0x10a>
if (netif == inp) {
8019b90: 69ba ldr r2, [r7, #24]
8019b92: 683b ldr r3, [r7, #0]
8019b94: 429a cmp r2, r3
8019b96: d006 beq.n 8019ba6 <ip4_input+0x102>
/* we checked that before already */
continue;
}
if (ip4_input_accept(netif)) {
8019b98: 69b8 ldr r0, [r7, #24]
8019b9a: f7ff ff59 bl 8019a50 <ip4_input_accept>
8019b9e: 4603 mov r3, r0
8019ba0: 2b00 cmp r3, #0
8019ba2: d108 bne.n 8019bb6 <ip4_input+0x112>
8019ba4: e000 b.n 8019ba8 <ip4_input+0x104>
continue;
8019ba6: bf00 nop
NETIF_FOREACH(netif) {
8019ba8: 69bb ldr r3, [r7, #24]
8019baa: 681b ldr r3, [r3, #0]
8019bac: 61bb str r3, [r7, #24]
8019bae: 69bb ldr r3, [r7, #24]
8019bb0: 2b00 cmp r3, #0
8019bb2: d1ed bne.n 8019b90 <ip4_input+0xec>
8019bb4: e000 b.n 8019bb8 <ip4_input+0x114>
break;
8019bb6: bf00 nop
* If you want to accept private broadcast communication while a netif is down,
* define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
*
* #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
*/
if (netif == NULL) {
8019bb8: 69bb ldr r3, [r7, #24]
8019bba: 2b00 cmp r3, #0
8019bbc: d111 bne.n 8019be2 <ip4_input+0x13e>
/* remote port is DHCP server? */
if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
8019bbe: 69fb ldr r3, [r7, #28]
8019bc0: 7a5b ldrb r3, [r3, #9]
8019bc2: 2b11 cmp r3, #17
8019bc4: d10d bne.n 8019be2 <ip4_input+0x13e>
const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen);
8019bc6: 8a7b ldrh r3, [r7, #18]
8019bc8: 69fa ldr r2, [r7, #28]
8019bca: 4413 add r3, r2
8019bcc: 60fb str r3, [r7, #12]
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n",
lwip_ntohs(udphdr->dest)));
if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
8019bce: 68fb ldr r3, [r7, #12]
8019bd0: 885b ldrh r3, [r3, #2]
8019bd2: b29b uxth r3, r3
8019bd4: f5b3 4f88 cmp.w r3, #17408 ; 0x4400
8019bd8: d103 bne.n 8019be2 <ip4_input+0x13e>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n"));
netif = inp;
8019bda: 683b ldr r3, [r7, #0]
8019bdc: 61bb str r3, [r7, #24]
check_ip_src = 0;
8019bde: 2300 movs r3, #0
8019be0: 617b str r3, [r7, #20]
}
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
/* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING
if (check_ip_src
8019be2: 697b ldr r3, [r7, #20]
8019be4: 2b00 cmp r3, #0
8019be6: d017 beq.n 8019c18 <ip4_input+0x174>
#if IP_ACCEPT_LINK_LAYER_ADDRESSING
/* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
&& !ip4_addr_isany_val(*ip4_current_src_addr())
8019be8: 4b4c ldr r3, [pc, #304] ; (8019d1c <ip4_input+0x278>)
8019bea: 691b ldr r3, [r3, #16]
8019bec: 2b00 cmp r3, #0
8019bee: d013 beq.n 8019c18 <ip4_input+0x174>
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
)
#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
{
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019bf0: 4b4a ldr r3, [pc, #296] ; (8019d1c <ip4_input+0x278>)
8019bf2: 691b ldr r3, [r3, #16]
8019bf4: 6839 ldr r1, [r7, #0]
8019bf6: 4618 mov r0, r3
8019bf8: f000 f96c bl 8019ed4 <ip4_addr_isbroadcast_u32>
8019bfc: 4603 mov r3, r0
8019bfe: 2b00 cmp r3, #0
8019c00: d105 bne.n 8019c0e <ip4_input+0x16a>
(ip4_addr_ismulticast(ip4_current_src_addr()))) {
8019c02: 4b46 ldr r3, [pc, #280] ; (8019d1c <ip4_input+0x278>)
8019c04: 691b ldr r3, [r3, #16]
8019c06: f003 03f0 and.w r3, r3, #240 ; 0xf0
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
8019c0a: 2be0 cmp r3, #224 ; 0xe0
8019c0c: d104 bne.n 8019c18 <ip4_input+0x174>
/* packet source is not valid */
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
/* free (drop) packet pbufs */
pbuf_free(p);
8019c0e: 6878 ldr r0, [r7, #4]
8019c10: f7f6 fcf2 bl 80105f8 <pbuf_free>
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
return ERR_OK;
8019c14: 2300 movs r3, #0
8019c16: e07c b.n 8019d12 <ip4_input+0x26e>
}
}
/* packet not for us? */
if (netif == NULL) {
8019c18: 69bb ldr r3, [r7, #24]
8019c1a: 2b00 cmp r3, #0
8019c1c: d104 bne.n 8019c28 <ip4_input+0x184>
{
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinaddrerrors);
MIB2_STATS_INC(mib2.ipindiscards);
}
pbuf_free(p);
8019c1e: 6878 ldr r0, [r7, #4]
8019c20: f7f6 fcea bl 80105f8 <pbuf_free>
return ERR_OK;
8019c24: 2300 movs r3, #0
8019c26: e074 b.n 8019d12 <ip4_input+0x26e>
}
/* packet consists of multiple fragments? */
if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
8019c28: 69fb ldr r3, [r7, #28]
8019c2a: 88db ldrh r3, [r3, #6]
8019c2c: b29b uxth r3, r3
8019c2e: 461a mov r2, r3
8019c30: f64f 733f movw r3, #65343 ; 0xff3f
8019c34: 4013 ands r3, r2
8019c36: 2b00 cmp r3, #0
8019c38: d00b beq.n 8019c52 <ip4_input+0x1ae>
#if IP_REASSEMBLY /* packet fragment reassembly code present? */
LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
/* reassemble the packet*/
p = ip4_reass(p);
8019c3a: 6878 ldr r0, [r7, #4]
8019c3c: f000 fc90 bl 801a560 <ip4_reass>
8019c40: 6078 str r0, [r7, #4]
/* packet not fully reassembled yet? */
if (p == NULL) {
8019c42: 687b ldr r3, [r7, #4]
8019c44: 2b00 cmp r3, #0
8019c46: d101 bne.n 8019c4c <ip4_input+0x1a8>
return ERR_OK;
8019c48: 2300 movs r3, #0
8019c4a: e062 b.n 8019d12 <ip4_input+0x26e>
}
iphdr = (const struct ip_hdr *)p->payload;
8019c4c: 687b ldr r3, [r7, #4]
8019c4e: 685b ldr r3, [r3, #4]
8019c50: 61fb str r3, [r7, #28]
/* send to upper layers */
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
ip4_debug_print(p);
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
ip_data.current_netif = netif;
8019c52: 4a32 ldr r2, [pc, #200] ; (8019d1c <ip4_input+0x278>)
8019c54: 69bb ldr r3, [r7, #24]
8019c56: 6013 str r3, [r2, #0]
ip_data.current_input_netif = inp;
8019c58: 4a30 ldr r2, [pc, #192] ; (8019d1c <ip4_input+0x278>)
8019c5a: 683b ldr r3, [r7, #0]
8019c5c: 6053 str r3, [r2, #4]
ip_data.current_ip4_header = iphdr;
8019c5e: 4a2f ldr r2, [pc, #188] ; (8019d1c <ip4_input+0x278>)
8019c60: 69fb ldr r3, [r7, #28]
8019c62: 6093 str r3, [r2, #8]
ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
8019c64: 69fb ldr r3, [r7, #28]
8019c66: 781b ldrb r3, [r3, #0]
8019c68: f003 030f and.w r3, r3, #15
8019c6c: b2db uxtb r3, r3
8019c6e: 009b lsls r3, r3, #2
8019c70: b2db uxtb r3, r3
8019c72: b29a uxth r2, r3
8019c74: 4b29 ldr r3, [pc, #164] ; (8019d1c <ip4_input+0x278>)
8019c76: 819a strh r2, [r3, #12]
/* raw input did not eat the packet? */
raw_status = raw_input(p, inp);
if (raw_status != RAW_INPUT_EATEN)
#endif /* LWIP_RAW */
{
pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
8019c78: 8a7b ldrh r3, [r7, #18]
8019c7a: 4619 mov r1, r3
8019c7c: 6878 ldr r0, [r7, #4]
8019c7e: f7f6 fc35 bl 80104ec <pbuf_remove_header>
switch (IPH_PROTO(iphdr)) {
8019c82: 69fb ldr r3, [r7, #28]
8019c84: 7a5b ldrb r3, [r3, #9]
8019c86: 2b06 cmp r3, #6
8019c88: d009 beq.n 8019c9e <ip4_input+0x1fa>
8019c8a: 2b11 cmp r3, #17
8019c8c: d002 beq.n 8019c94 <ip4_input+0x1f0>
8019c8e: 2b01 cmp r3, #1
8019c90: d00a beq.n 8019ca8 <ip4_input+0x204>
8019c92: e00e b.n 8019cb2 <ip4_input+0x20e>
case IP_PROTO_UDP:
#if LWIP_UDPLITE
case IP_PROTO_UDPLITE:
#endif /* LWIP_UDPLITE */
MIB2_STATS_INC(mib2.ipindelivers);
udp_input(p, inp);
8019c94: 6839 ldr r1, [r7, #0]
8019c96: 6878 ldr r0, [r7, #4]
8019c98: f7fc fada bl 8016250 <udp_input>
break;
8019c9c: e026 b.n 8019cec <ip4_input+0x248>
#endif /* LWIP_UDP */
#if LWIP_TCP
case IP_PROTO_TCP:
MIB2_STATS_INC(mib2.ipindelivers);
tcp_input(p, inp);
8019c9e: 6839 ldr r1, [r7, #0]
8019ca0: 6878 ldr r0, [r7, #4]
8019ca2: f7f8 fae1 bl 8012268 <tcp_input>
break;
8019ca6: e021 b.n 8019cec <ip4_input+0x248>
#endif /* LWIP_TCP */
#if LWIP_ICMP
case IP_PROTO_ICMP:
MIB2_STATS_INC(mib2.ipindelivers);
icmp_input(p, inp);
8019ca8: 6839 ldr r1, [r7, #0]
8019caa: 6878 ldr r0, [r7, #4]
8019cac: f7ff fcd2 bl 8019654 <icmp_input>
break;
8019cb0: e01c b.n 8019cec <ip4_input+0x248>
} else
#endif /* LWIP_RAW */
{
#if LWIP_ICMP
/* send ICMP destination protocol unreachable unless is was a broadcast */
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019cb2: 4b1a ldr r3, [pc, #104] ; (8019d1c <ip4_input+0x278>)
8019cb4: 695b ldr r3, [r3, #20]
8019cb6: 69b9 ldr r1, [r7, #24]
8019cb8: 4618 mov r0, r3
8019cba: f000 f90b bl 8019ed4 <ip4_addr_isbroadcast_u32>
8019cbe: 4603 mov r3, r0
8019cc0: 2b00 cmp r3, #0
8019cc2: d10f bne.n 8019ce4 <ip4_input+0x240>
!ip4_addr_ismulticast(ip4_current_dest_addr())) {
8019cc4: 4b15 ldr r3, [pc, #84] ; (8019d1c <ip4_input+0x278>)
8019cc6: 695b ldr r3, [r3, #20]
8019cc8: f003 03f0 and.w r3, r3, #240 ; 0xf0
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
8019ccc: 2be0 cmp r3, #224 ; 0xe0
8019cce: d009 beq.n 8019ce4 <ip4_input+0x240>
pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
8019cd0: f9b7 3012 ldrsh.w r3, [r7, #18]
8019cd4: 4619 mov r1, r3
8019cd6: 6878 ldr r0, [r7, #4]
8019cd8: f7f6 fc7b bl 80105d2 <pbuf_header_force>
icmp_dest_unreach(p, ICMP_DUR_PROTO);
8019cdc: 2102 movs r1, #2
8019cde: 6878 ldr r0, [r7, #4]
8019ce0: f7ff fdbc bl 801985c <icmp_dest_unreach>
IP_STATS_INC(ip.proterr);
IP_STATS_INC(ip.drop);
MIB2_STATS_INC(mib2.ipinunknownprotos);
}
pbuf_free(p);
8019ce4: 6878 ldr r0, [r7, #4]
8019ce6: f7f6 fc87 bl 80105f8 <pbuf_free>
break;
8019cea: bf00 nop
}
}
/* @todo: this is not really necessary... */
ip_data.current_netif = NULL;
8019cec: 4b0b ldr r3, [pc, #44] ; (8019d1c <ip4_input+0x278>)
8019cee: 2200 movs r2, #0
8019cf0: 601a str r2, [r3, #0]
ip_data.current_input_netif = NULL;
8019cf2: 4b0a ldr r3, [pc, #40] ; (8019d1c <ip4_input+0x278>)
8019cf4: 2200 movs r2, #0
8019cf6: 605a str r2, [r3, #4]
ip_data.current_ip4_header = NULL;
8019cf8: 4b08 ldr r3, [pc, #32] ; (8019d1c <ip4_input+0x278>)
8019cfa: 2200 movs r2, #0
8019cfc: 609a str r2, [r3, #8]
ip_data.current_ip_header_tot_len = 0;
8019cfe: 4b07 ldr r3, [pc, #28] ; (8019d1c <ip4_input+0x278>)
8019d00: 2200 movs r2, #0
8019d02: 819a strh r2, [r3, #12]
ip4_addr_set_any(ip4_current_src_addr());
8019d04: 4b05 ldr r3, [pc, #20] ; (8019d1c <ip4_input+0x278>)
8019d06: 2200 movs r2, #0
8019d08: 611a str r2, [r3, #16]
ip4_addr_set_any(ip4_current_dest_addr());
8019d0a: 4b04 ldr r3, [pc, #16] ; (8019d1c <ip4_input+0x278>)
8019d0c: 2200 movs r2, #0
8019d0e: 615a str r2, [r3, #20]
return ERR_OK;
8019d10: 2300 movs r3, #0
}
8019d12: 4618 mov r0, r3
8019d14: 3720 adds r7, #32
8019d16: 46bd mov sp, r7
8019d18: bd80 pop {r7, pc}
8019d1a: bf00 nop
8019d1c: 2000be8c .word 0x2000be8c
8019d20: 2000f5b0 .word 0x2000f5b0
08019d24 <ip4_output_if>:
*/
err_t
ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019d24: b580 push {r7, lr}
8019d26: b08a sub sp, #40 ; 0x28
8019d28: af04 add r7, sp, #16
8019d2a: 60f8 str r0, [r7, #12]
8019d2c: 60b9 str r1, [r7, #8]
8019d2e: 607a str r2, [r7, #4]
8019d30: 70fb strb r3, [r7, #3]
ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
u16_t optlen)
{
#endif /* IP_OPTIONS_SEND */
const ip4_addr_t *src_used = src;
8019d32: 68bb ldr r3, [r7, #8]
8019d34: 617b str r3, [r7, #20]
if (dest != LWIP_IP_HDRINCL) {
8019d36: 687b ldr r3, [r7, #4]
8019d38: 2b00 cmp r3, #0
8019d3a: d009 beq.n 8019d50 <ip4_output_if+0x2c>
if (ip4_addr_isany(src)) {
8019d3c: 68bb ldr r3, [r7, #8]
8019d3e: 2b00 cmp r3, #0
8019d40: d003 beq.n 8019d4a <ip4_output_if+0x26>
8019d42: 68bb ldr r3, [r7, #8]
8019d44: 681b ldr r3, [r3, #0]
8019d46: 2b00 cmp r3, #0
8019d48: d102 bne.n 8019d50 <ip4_output_if+0x2c>
src_used = netif_ip4_addr(netif);
8019d4a: 6abb ldr r3, [r7, #40] ; 0x28
8019d4c: 3304 adds r3, #4
8019d4e: 617b str r3, [r7, #20]
#if IP_OPTIONS_SEND
return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
ip_options, optlen);
#else /* IP_OPTIONS_SEND */
return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
8019d50: 78fa ldrb r2, [r7, #3]
8019d52: 6abb ldr r3, [r7, #40] ; 0x28
8019d54: 9302 str r3, [sp, #8]
8019d56: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
8019d5a: 9301 str r3, [sp, #4]
8019d5c: f897 3020 ldrb.w r3, [r7, #32]
8019d60: 9300 str r3, [sp, #0]
8019d62: 4613 mov r3, r2
8019d64: 687a ldr r2, [r7, #4]
8019d66: 6979 ldr r1, [r7, #20]
8019d68: 68f8 ldr r0, [r7, #12]
8019d6a: f000 f805 bl 8019d78 <ip4_output_if_src>
8019d6e: 4603 mov r3, r0
#endif /* IP_OPTIONS_SEND */
}
8019d70: 4618 mov r0, r3
8019d72: 3718 adds r7, #24
8019d74: 46bd mov sp, r7
8019d76: bd80 pop {r7, pc}
08019d78 <ip4_output_if_src>:
*/
err_t
ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
u8_t ttl, u8_t tos,
u8_t proto, struct netif *netif)
{
8019d78: b580 push {r7, lr}
8019d7a: b088 sub sp, #32
8019d7c: af00 add r7, sp, #0
8019d7e: 60f8 str r0, [r7, #12]
8019d80: 60b9 str r1, [r7, #8]
8019d82: 607a str r2, [r7, #4]
8019d84: 70fb strb r3, [r7, #3]
#if CHECKSUM_GEN_IP_INLINE
u32_t chk_sum = 0;
#endif /* CHECKSUM_GEN_IP_INLINE */
LWIP_ASSERT_CORE_LOCKED();
LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
8019d86: 68fb ldr r3, [r7, #12]
8019d88: 7b9b ldrb r3, [r3, #14]
8019d8a: 2b01 cmp r3, #1
8019d8c: d006 beq.n 8019d9c <ip4_output_if_src+0x24>
8019d8e: 4b4b ldr r3, [pc, #300] ; (8019ebc <ip4_output_if_src+0x144>)
8019d90: f44f 7255 mov.w r2, #852 ; 0x354
8019d94: 494a ldr r1, [pc, #296] ; (8019ec0 <ip4_output_if_src+0x148>)
8019d96: 484b ldr r0, [pc, #300] ; (8019ec4 <ip4_output_if_src+0x14c>)
8019d98: f001 f944 bl 801b024 <iprintf>
MIB2_STATS_INC(mib2.ipoutrequests);
/* Should the IP header be generated or is it already included in p? */
if (dest != LWIP_IP_HDRINCL) {
8019d9c: 687b ldr r3, [r7, #4]
8019d9e: 2b00 cmp r3, #0
8019da0: d060 beq.n 8019e64 <ip4_output_if_src+0xec>
u16_t ip_hlen = IP_HLEN;
8019da2: 2314 movs r3, #20
8019da4: 837b strh r3, [r7, #26]
}
#endif /* CHECKSUM_GEN_IP_INLINE */
}
#endif /* IP_OPTIONS_SEND */
/* generate IP header */
if (pbuf_add_header(p, IP_HLEN)) {
8019da6: 2114 movs r1, #20
8019da8: 68f8 ldr r0, [r7, #12]
8019daa: f7f6 fb8f bl 80104cc <pbuf_add_header>
8019dae: 4603 mov r3, r0
8019db0: 2b00 cmp r3, #0
8019db2: d002 beq.n 8019dba <ip4_output_if_src+0x42>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019db4: f06f 0301 mvn.w r3, #1
8019db8: e07c b.n 8019eb4 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019dba: 68fb ldr r3, [r7, #12]
8019dbc: 685b ldr r3, [r3, #4]
8019dbe: 61fb str r3, [r7, #28]
LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
8019dc0: 68fb ldr r3, [r7, #12]
8019dc2: 895b ldrh r3, [r3, #10]
8019dc4: 2b13 cmp r3, #19
8019dc6: d806 bhi.n 8019dd6 <ip4_output_if_src+0x5e>
8019dc8: 4b3c ldr r3, [pc, #240] ; (8019ebc <ip4_output_if_src+0x144>)
8019dca: f240 3289 movw r2, #905 ; 0x389
8019dce: 493e ldr r1, [pc, #248] ; (8019ec8 <ip4_output_if_src+0x150>)
8019dd0: 483c ldr r0, [pc, #240] ; (8019ec4 <ip4_output_if_src+0x14c>)
8019dd2: f001 f927 bl 801b024 <iprintf>
(p->len >= sizeof(struct ip_hdr)));
IPH_TTL_SET(iphdr, ttl);
8019dd6: 69fb ldr r3, [r7, #28]
8019dd8: 78fa ldrb r2, [r7, #3]
8019dda: 721a strb r2, [r3, #8]
IPH_PROTO_SET(iphdr, proto);
8019ddc: 69fb ldr r3, [r7, #28]
8019dde: f897 202c ldrb.w r2, [r7, #44] ; 0x2c
8019de2: 725a strb r2, [r3, #9]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(proto | (ttl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
/* dest cannot be NULL here */
ip4_addr_copy(iphdr->dest, *dest);
8019de4: 687b ldr r3, [r7, #4]
8019de6: 681a ldr r2, [r3, #0]
8019de8: 69fb ldr r3, [r7, #28]
8019dea: 611a str r2, [r3, #16]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
8019dec: 8b7b ldrh r3, [r7, #26]
8019dee: 089b lsrs r3, r3, #2
8019df0: b29b uxth r3, r3
8019df2: b2db uxtb r3, r3
8019df4: f043 0340 orr.w r3, r3, #64 ; 0x40
8019df8: b2da uxtb r2, r3
8019dfa: 69fb ldr r3, [r7, #28]
8019dfc: 701a strb r2, [r3, #0]
IPH_TOS_SET(iphdr, tos);
8019dfe: 69fb ldr r3, [r7, #28]
8019e00: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
8019e04: 705a strb r2, [r3, #1]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
8019e06: 68fb ldr r3, [r7, #12]
8019e08: 891b ldrh r3, [r3, #8]
8019e0a: 4618 mov r0, r3
8019e0c: f7f5 f840 bl 800ee90 <lwip_htons>
8019e10: 4603 mov r3, r0
8019e12: 461a mov r2, r3
8019e14: 69fb ldr r3, [r7, #28]
8019e16: 805a strh r2, [r3, #2]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_len;
#endif /* CHECKSUM_GEN_IP_INLINE */
IPH_OFFSET_SET(iphdr, 0);
8019e18: 69fb ldr r3, [r7, #28]
8019e1a: 2200 movs r2, #0
8019e1c: 719a strb r2, [r3, #6]
8019e1e: 2200 movs r2, #0
8019e20: 71da strb r2, [r3, #7]
IPH_ID_SET(iphdr, lwip_htons(ip_id));
8019e22: 4b2a ldr r3, [pc, #168] ; (8019ecc <ip4_output_if_src+0x154>)
8019e24: 881b ldrh r3, [r3, #0]
8019e26: 4618 mov r0, r3
8019e28: f7f5 f832 bl 800ee90 <lwip_htons>
8019e2c: 4603 mov r3, r0
8019e2e: 461a mov r2, r3
8019e30: 69fb ldr r3, [r7, #28]
8019e32: 809a strh r2, [r3, #4]
#if CHECKSUM_GEN_IP_INLINE
chk_sum += iphdr->_id;
#endif /* CHECKSUM_GEN_IP_INLINE */
++ip_id;
8019e34: 4b25 ldr r3, [pc, #148] ; (8019ecc <ip4_output_if_src+0x154>)
8019e36: 881b ldrh r3, [r3, #0]
8019e38: 3301 adds r3, #1
8019e3a: b29a uxth r2, r3
8019e3c: 4b23 ldr r3, [pc, #140] ; (8019ecc <ip4_output_if_src+0x154>)
8019e3e: 801a strh r2, [r3, #0]
if (src == NULL) {
8019e40: 68bb ldr r3, [r7, #8]
8019e42: 2b00 cmp r3, #0
8019e44: d104 bne.n 8019e50 <ip4_output_if_src+0xd8>
ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
8019e46: 4b22 ldr r3, [pc, #136] ; (8019ed0 <ip4_output_if_src+0x158>)
8019e48: 681a ldr r2, [r3, #0]
8019e4a: 69fb ldr r3, [r7, #28]
8019e4c: 60da str r2, [r3, #12]
8019e4e: e003 b.n 8019e58 <ip4_output_if_src+0xe0>
} else {
/* src cannot be NULL here */
ip4_addr_copy(iphdr->src, *src);
8019e50: 68bb ldr r3, [r7, #8]
8019e52: 681a ldr r2, [r3, #0]
8019e54: 69fb ldr r3, [r7, #28]
8019e56: 60da str r2, [r3, #12]
else {
IPH_CHKSUM_SET(iphdr, 0);
}
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
#else /* CHECKSUM_GEN_IP_INLINE */
IPH_CHKSUM_SET(iphdr, 0);
8019e58: 69fb ldr r3, [r7, #28]
8019e5a: 2200 movs r2, #0
8019e5c: 729a strb r2, [r3, #10]
8019e5e: 2200 movs r2, #0
8019e60: 72da strb r2, [r3, #11]
8019e62: e00f b.n 8019e84 <ip4_output_if_src+0x10c>
}
#endif /* CHECKSUM_GEN_IP */
#endif /* CHECKSUM_GEN_IP_INLINE */
} else {
/* IP header already included in p */
if (p->len < IP_HLEN) {
8019e64: 68fb ldr r3, [r7, #12]
8019e66: 895b ldrh r3, [r3, #10]
8019e68: 2b13 cmp r3, #19
8019e6a: d802 bhi.n 8019e72 <ip4_output_if_src+0xfa>
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
IP_STATS_INC(ip.err);
MIB2_STATS_INC(mib2.ipoutdiscards);
return ERR_BUF;
8019e6c: f06f 0301 mvn.w r3, #1
8019e70: e020 b.n 8019eb4 <ip4_output_if_src+0x13c>
}
iphdr = (struct ip_hdr *)p->payload;
8019e72: 68fb ldr r3, [r7, #12]
8019e74: 685b ldr r3, [r3, #4]
8019e76: 61fb str r3, [r7, #28]
ip4_addr_copy(dest_addr, iphdr->dest);
8019e78: 69fb ldr r3, [r7, #28]
8019e7a: 691b ldr r3, [r3, #16]
8019e7c: 617b str r3, [r7, #20]
dest = &dest_addr;
8019e7e: f107 0314 add.w r3, r7, #20
8019e82: 607b str r3, [r7, #4]
}
#endif /* LWIP_MULTICAST_TX_OPTIONS */
#endif /* ENABLE_LOOPBACK */
#if IP_FRAG
/* don't fragment if interface has mtu set to 0 [loopif] */
if (netif->mtu && (p->tot_len > netif->mtu)) {
8019e84: 6b3b ldr r3, [r7, #48] ; 0x30
8019e86: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e88: 2b00 cmp r3, #0
8019e8a: d00c beq.n 8019ea6 <ip4_output_if_src+0x12e>
8019e8c: 68fb ldr r3, [r7, #12]
8019e8e: 891a ldrh r2, [r3, #8]
8019e90: 6b3b ldr r3, [r7, #48] ; 0x30
8019e92: 8d1b ldrh r3, [r3, #40] ; 0x28
8019e94: 429a cmp r2, r3
8019e96: d906 bls.n 8019ea6 <ip4_output_if_src+0x12e>
return ip4_frag(p, netif, dest);
8019e98: 687a ldr r2, [r7, #4]
8019e9a: 6b39 ldr r1, [r7, #48] ; 0x30
8019e9c: 68f8 ldr r0, [r7, #12]
8019e9e: f000 fd4b bl 801a938 <ip4_frag>
8019ea2: 4603 mov r3, r0
8019ea4: e006 b.n 8019eb4 <ip4_output_if_src+0x13c>
}
#endif /* IP_FRAG */
LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
return netif->output(netif, p, dest);
8019ea6: 6b3b ldr r3, [r7, #48] ; 0x30
8019ea8: 695b ldr r3, [r3, #20]
8019eaa: 687a ldr r2, [r7, #4]
8019eac: 68f9 ldr r1, [r7, #12]
8019eae: 6b38 ldr r0, [r7, #48] ; 0x30
8019eb0: 4798 blx r3
8019eb2: 4603 mov r3, r0
}
8019eb4: 4618 mov r0, r3
8019eb6: 3720 adds r7, #32
8019eb8: 46bd mov sp, r7
8019eba: bd80 pop {r7, pc}
8019ebc: 0801eab8 .word 0x0801eab8
8019ec0: 0801eaec .word 0x0801eaec
8019ec4: 0801eaf8 .word 0x0801eaf8
8019ec8: 0801eb20 .word 0x0801eb20
8019ecc: 2000886a .word 0x2000886a
8019ed0: 08020e78 .word 0x08020e78
08019ed4 <ip4_addr_isbroadcast_u32>:
* @param netif the network interface against which the address is checked
* @return returns non-zero if the address is a broadcast address
*/
u8_t
ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
{
8019ed4: b480 push {r7}
8019ed6: b085 sub sp, #20
8019ed8: af00 add r7, sp, #0
8019eda: 6078 str r0, [r7, #4]
8019edc: 6039 str r1, [r7, #0]
ip4_addr_t ipaddr;
ip4_addr_set_u32(&ipaddr, addr);
8019ede: 687b ldr r3, [r7, #4]
8019ee0: 60fb str r3, [r7, #12]
/* all ones (broadcast) or all zeroes (old skool broadcast) */
if ((~addr == IPADDR_ANY) ||
8019ee2: 687b ldr r3, [r7, #4]
8019ee4: f1b3 3fff cmp.w r3, #4294967295
8019ee8: d002 beq.n 8019ef0 <ip4_addr_isbroadcast_u32+0x1c>
8019eea: 687b ldr r3, [r7, #4]
8019eec: 2b00 cmp r3, #0
8019eee: d101 bne.n 8019ef4 <ip4_addr_isbroadcast_u32+0x20>
(addr == IPADDR_ANY)) {
return 1;
8019ef0: 2301 movs r3, #1
8019ef2: e02a b.n 8019f4a <ip4_addr_isbroadcast_u32+0x76>
/* no broadcast support on this network interface? */
} else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
8019ef4: 683b ldr r3, [r7, #0]
8019ef6: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8019efa: f003 0302 and.w r3, r3, #2
8019efe: 2b00 cmp r3, #0
8019f00: d101 bne.n 8019f06 <ip4_addr_isbroadcast_u32+0x32>
/* the given address cannot be a broadcast address
* nor can we check against any broadcast addresses */
return 0;
8019f02: 2300 movs r3, #0
8019f04: e021 b.n 8019f4a <ip4_addr_isbroadcast_u32+0x76>
/* address matches network interface address exactly? => no broadcast */
} else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
8019f06: 683b ldr r3, [r7, #0]
8019f08: 3304 adds r3, #4
8019f0a: 681b ldr r3, [r3, #0]
8019f0c: 687a ldr r2, [r7, #4]
8019f0e: 429a cmp r2, r3
8019f10: d101 bne.n 8019f16 <ip4_addr_isbroadcast_u32+0x42>
return 0;
8019f12: 2300 movs r3, #0
8019f14: e019 b.n 8019f4a <ip4_addr_isbroadcast_u32+0x76>
/* on the same (sub) network... */
} else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
8019f16: 68fa ldr r2, [r7, #12]
8019f18: 683b ldr r3, [r7, #0]
8019f1a: 3304 adds r3, #4
8019f1c: 681b ldr r3, [r3, #0]
8019f1e: 405a eors r2, r3
8019f20: 683b ldr r3, [r7, #0]
8019f22: 3308 adds r3, #8
8019f24: 681b ldr r3, [r3, #0]
8019f26: 4013 ands r3, r2
8019f28: 2b00 cmp r3, #0
8019f2a: d10d bne.n 8019f48 <ip4_addr_isbroadcast_u32+0x74>
/* ...and host identifier bits are all ones? =>... */
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019f2c: 683b ldr r3, [r7, #0]
8019f2e: 3308 adds r3, #8
8019f30: 681b ldr r3, [r3, #0]
8019f32: 43da mvns r2, r3
8019f34: 687b ldr r3, [r7, #4]
8019f36: 401a ands r2, r3
(IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
8019f38: 683b ldr r3, [r7, #0]
8019f3a: 3308 adds r3, #8
8019f3c: 681b ldr r3, [r3, #0]
8019f3e: 43db mvns r3, r3
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
8019f40: 429a cmp r2, r3
8019f42: d101 bne.n 8019f48 <ip4_addr_isbroadcast_u32+0x74>
/* => network broadcast address */
return 1;
8019f44: 2301 movs r3, #1
8019f46: e000 b.n 8019f4a <ip4_addr_isbroadcast_u32+0x76>
} else {
return 0;
8019f48: 2300 movs r3, #0
}
}
8019f4a: 4618 mov r0, r3
8019f4c: 3714 adds r7, #20
8019f4e: 46bd mov sp, r7
8019f50: f85d 7b04 ldr.w r7, [sp], #4
8019f54: 4770 bx lr
...
08019f58 <ip_reass_tmr>:
*
* Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
*/
void
ip_reass_tmr(void)
{
8019f58: b580 push {r7, lr}
8019f5a: b084 sub sp, #16
8019f5c: af00 add r7, sp, #0
struct ip_reassdata *r, *prev = NULL;
8019f5e: 2300 movs r3, #0
8019f60: 60bb str r3, [r7, #8]
r = reassdatagrams;
8019f62: 4b12 ldr r3, [pc, #72] ; (8019fac <ip_reass_tmr+0x54>)
8019f64: 681b ldr r3, [r3, #0]
8019f66: 60fb str r3, [r7, #12]
while (r != NULL) {
8019f68: e018 b.n 8019f9c <ip_reass_tmr+0x44>
/* Decrement the timer. Once it reaches 0,
* clean up the incomplete fragment assembly */
if (r->timer > 0) {
8019f6a: 68fb ldr r3, [r7, #12]
8019f6c: 7fdb ldrb r3, [r3, #31]
8019f6e: 2b00 cmp r3, #0
8019f70: d00b beq.n 8019f8a <ip_reass_tmr+0x32>
r->timer--;
8019f72: 68fb ldr r3, [r7, #12]
8019f74: 7fdb ldrb r3, [r3, #31]
8019f76: 3b01 subs r3, #1
8019f78: b2da uxtb r2, r3
8019f7a: 68fb ldr r3, [r7, #12]
8019f7c: 77da strb r2, [r3, #31]
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
prev = r;
8019f7e: 68fb ldr r3, [r7, #12]
8019f80: 60bb str r3, [r7, #8]
r = r->next;
8019f82: 68fb ldr r3, [r7, #12]
8019f84: 681b ldr r3, [r3, #0]
8019f86: 60fb str r3, [r7, #12]
8019f88: e008 b.n 8019f9c <ip_reass_tmr+0x44>
} else {
/* reassembly timed out */
struct ip_reassdata *tmp;
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
tmp = r;
8019f8a: 68fb ldr r3, [r7, #12]
8019f8c: 607b str r3, [r7, #4]
/* get the next pointer before freeing */
r = r->next;
8019f8e: 68fb ldr r3, [r7, #12]
8019f90: 681b ldr r3, [r3, #0]
8019f92: 60fb str r3, [r7, #12]
/* free the helper struct and all enqueued pbufs */
ip_reass_free_complete_datagram(tmp, prev);
8019f94: 68b9 ldr r1, [r7, #8]
8019f96: 6878 ldr r0, [r7, #4]
8019f98: f000 f80a bl 8019fb0 <ip_reass_free_complete_datagram>
while (r != NULL) {
8019f9c: 68fb ldr r3, [r7, #12]
8019f9e: 2b00 cmp r3, #0
8019fa0: d1e3 bne.n 8019f6a <ip_reass_tmr+0x12>
}
}
}
8019fa2: bf00 nop
8019fa4: 3710 adds r7, #16
8019fa6: 46bd mov sp, r7
8019fa8: bd80 pop {r7, pc}
8019faa: bf00 nop
8019fac: 2000886c .word 0x2000886c
08019fb0 <ip_reass_free_complete_datagram>:
* @param prev the previous datagram in the linked list
* @return the number of pbufs freed
*/
static int
ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
8019fb0: b580 push {r7, lr}
8019fb2: b088 sub sp, #32
8019fb4: af00 add r7, sp, #0
8019fb6: 6078 str r0, [r7, #4]
8019fb8: 6039 str r1, [r7, #0]
u16_t pbufs_freed = 0;
8019fba: 2300 movs r3, #0
8019fbc: 83fb strh r3, [r7, #30]
u16_t clen;
struct pbuf *p;
struct ip_reass_helper *iprh;
LWIP_ASSERT("prev != ipr", prev != ipr);
8019fbe: 683a ldr r2, [r7, #0]
8019fc0: 687b ldr r3, [r7, #4]
8019fc2: 429a cmp r2, r3
8019fc4: d105 bne.n 8019fd2 <ip_reass_free_complete_datagram+0x22>
8019fc6: 4b45 ldr r3, [pc, #276] ; (801a0dc <ip_reass_free_complete_datagram+0x12c>)
8019fc8: 22ab movs r2, #171 ; 0xab
8019fca: 4945 ldr r1, [pc, #276] ; (801a0e0 <ip_reass_free_complete_datagram+0x130>)
8019fcc: 4845 ldr r0, [pc, #276] ; (801a0e4 <ip_reass_free_complete_datagram+0x134>)
8019fce: f001 f829 bl 801b024 <iprintf>
if (prev != NULL) {
8019fd2: 683b ldr r3, [r7, #0]
8019fd4: 2b00 cmp r3, #0
8019fd6: d00a beq.n 8019fee <ip_reass_free_complete_datagram+0x3e>
LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
8019fd8: 683b ldr r3, [r7, #0]
8019fda: 681b ldr r3, [r3, #0]
8019fdc: 687a ldr r2, [r7, #4]
8019fde: 429a cmp r2, r3
8019fe0: d005 beq.n 8019fee <ip_reass_free_complete_datagram+0x3e>
8019fe2: 4b3e ldr r3, [pc, #248] ; (801a0dc <ip_reass_free_complete_datagram+0x12c>)
8019fe4: 22ad movs r2, #173 ; 0xad
8019fe6: 4940 ldr r1, [pc, #256] ; (801a0e8 <ip_reass_free_complete_datagram+0x138>)
8019fe8: 483e ldr r0, [pc, #248] ; (801a0e4 <ip_reass_free_complete_datagram+0x134>)
8019fea: f001 f81b bl 801b024 <iprintf>
}
MIB2_STATS_INC(mib2.ipreasmfails);
#if LWIP_ICMP
iprh = (struct ip_reass_helper *)ipr->p->payload;
8019fee: 687b ldr r3, [r7, #4]
8019ff0: 685b ldr r3, [r3, #4]
8019ff2: 685b ldr r3, [r3, #4]
8019ff4: 617b str r3, [r7, #20]
if (iprh->start == 0) {
8019ff6: 697b ldr r3, [r7, #20]
8019ff8: 889b ldrh r3, [r3, #4]
8019ffa: b29b uxth r3, r3
8019ffc: 2b00 cmp r3, #0
8019ffe: d12a bne.n 801a056 <ip_reass_free_complete_datagram+0xa6>
/* The first fragment was received, send ICMP time exceeded. */
/* First, de-queue the first pbuf from r->p. */
p = ipr->p;
801a000: 687b ldr r3, [r7, #4]
801a002: 685b ldr r3, [r3, #4]
801a004: 61bb str r3, [r7, #24]
ipr->p = iprh->next_pbuf;
801a006: 697b ldr r3, [r7, #20]
801a008: 681a ldr r2, [r3, #0]
801a00a: 687b ldr r3, [r7, #4]
801a00c: 605a str r2, [r3, #4]
/* Then, copy the original header into it. */
SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
801a00e: 69bb ldr r3, [r7, #24]
801a010: 6858 ldr r0, [r3, #4]
801a012: 687b ldr r3, [r7, #4]
801a014: 3308 adds r3, #8
801a016: 2214 movs r2, #20
801a018: 4619 mov r1, r3
801a01a: f000 fff0 bl 801affe <memcpy>
icmp_time_exceeded(p, ICMP_TE_FRAG);
801a01e: 2101 movs r1, #1
801a020: 69b8 ldr r0, [r7, #24]
801a022: f7ff fc2b bl 801987c <icmp_time_exceeded>
clen = pbuf_clen(p);
801a026: 69b8 ldr r0, [r7, #24]
801a028: f7f6 fb74 bl 8010714 <pbuf_clen>
801a02c: 4603 mov r3, r0
801a02e: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
801a030: 8bfa ldrh r2, [r7, #30]
801a032: 8a7b ldrh r3, [r7, #18]
801a034: 4413 add r3, r2
801a036: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801a03a: db05 blt.n 801a048 <ip_reass_free_complete_datagram+0x98>
801a03c: 4b27 ldr r3, [pc, #156] ; (801a0dc <ip_reass_free_complete_datagram+0x12c>)
801a03e: 22bc movs r2, #188 ; 0xbc
801a040: 492a ldr r1, [pc, #168] ; (801a0ec <ip_reass_free_complete_datagram+0x13c>)
801a042: 4828 ldr r0, [pc, #160] ; (801a0e4 <ip_reass_free_complete_datagram+0x134>)
801a044: f000 ffee bl 801b024 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
801a048: 8bfa ldrh r2, [r7, #30]
801a04a: 8a7b ldrh r3, [r7, #18]
801a04c: 4413 add r3, r2
801a04e: 83fb strh r3, [r7, #30]
pbuf_free(p);
801a050: 69b8 ldr r0, [r7, #24]
801a052: f7f6 fad1 bl 80105f8 <pbuf_free>
}
#endif /* LWIP_ICMP */
/* First, free all received pbufs. The individual pbufs need to be released
separately as they have not yet been chained */
p = ipr->p;
801a056: 687b ldr r3, [r7, #4]
801a058: 685b ldr r3, [r3, #4]
801a05a: 61bb str r3, [r7, #24]
while (p != NULL) {
801a05c: e01f b.n 801a09e <ip_reass_free_complete_datagram+0xee>
struct pbuf *pcur;
iprh = (struct ip_reass_helper *)p->payload;
801a05e: 69bb ldr r3, [r7, #24]
801a060: 685b ldr r3, [r3, #4]
801a062: 617b str r3, [r7, #20]
pcur = p;
801a064: 69bb ldr r3, [r7, #24]
801a066: 60fb str r3, [r7, #12]
/* get the next pointer before freeing */
p = iprh->next_pbuf;
801a068: 697b ldr r3, [r7, #20]
801a06a: 681b ldr r3, [r3, #0]
801a06c: 61bb str r3, [r7, #24]
clen = pbuf_clen(pcur);
801a06e: 68f8 ldr r0, [r7, #12]
801a070: f7f6 fb50 bl 8010714 <pbuf_clen>
801a074: 4603 mov r3, r0
801a076: 827b strh r3, [r7, #18]
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
801a078: 8bfa ldrh r2, [r7, #30]
801a07a: 8a7b ldrh r3, [r7, #18]
801a07c: 4413 add r3, r2
801a07e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
801a082: db05 blt.n 801a090 <ip_reass_free_complete_datagram+0xe0>
801a084: 4b15 ldr r3, [pc, #84] ; (801a0dc <ip_reass_free_complete_datagram+0x12c>)
801a086: 22cc movs r2, #204 ; 0xcc
801a088: 4918 ldr r1, [pc, #96] ; (801a0ec <ip_reass_free_complete_datagram+0x13c>)
801a08a: 4816 ldr r0, [pc, #88] ; (801a0e4 <ip_reass_free_complete_datagram+0x134>)
801a08c: f000 ffca bl 801b024 <iprintf>
pbufs_freed = (u16_t)(pbufs_freed + clen);
801a090: 8bfa ldrh r2, [r7, #30]
801a092: 8a7b ldrh r3, [r7, #18]
801a094: 4413 add r3, r2
801a096: 83fb strh r3, [r7, #30]
pbuf_free(pcur);
801a098: 68f8 ldr r0, [r7, #12]
801a09a: f7f6 faad bl 80105f8 <pbuf_free>
while (p != NULL) {
801a09e: 69bb ldr r3, [r7, #24]
801a0a0: 2b00 cmp r3, #0
801a0a2: d1dc bne.n 801a05e <ip_reass_free_complete_datagram+0xae>
}
/* Then, unchain the struct ip_reassdata from the list and free it. */
ip_reass_dequeue_datagram(ipr, prev);
801a0a4: 6839 ldr r1, [r7, #0]
801a0a6: 6878 ldr r0, [r7, #4]
801a0a8: f000 f8c2 bl 801a230 <ip_reass_dequeue_datagram>
LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
801a0ac: 4b10 ldr r3, [pc, #64] ; (801a0f0 <ip_reass_free_complete_datagram+0x140>)
801a0ae: 881b ldrh r3, [r3, #0]
801a0b0: 8bfa ldrh r2, [r7, #30]
801a0b2: 429a cmp r2, r3
801a0b4: d905 bls.n 801a0c2 <ip_reass_free_complete_datagram+0x112>
801a0b6: 4b09 ldr r3, [pc, #36] ; (801a0dc <ip_reass_free_complete_datagram+0x12c>)
801a0b8: 22d2 movs r2, #210 ; 0xd2
801a0ba: 490e ldr r1, [pc, #56] ; (801a0f4 <ip_reass_free_complete_datagram+0x144>)
801a0bc: 4809 ldr r0, [pc, #36] ; (801a0e4 <ip_reass_free_complete_datagram+0x134>)
801a0be: f000 ffb1 bl 801b024 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
801a0c2: 4b0b ldr r3, [pc, #44] ; (801a0f0 <ip_reass_free_complete_datagram+0x140>)
801a0c4: 881a ldrh r2, [r3, #0]
801a0c6: 8bfb ldrh r3, [r7, #30]
801a0c8: 1ad3 subs r3, r2, r3
801a0ca: b29a uxth r2, r3
801a0cc: 4b08 ldr r3, [pc, #32] ; (801a0f0 <ip_reass_free_complete_datagram+0x140>)
801a0ce: 801a strh r2, [r3, #0]
return pbufs_freed;
801a0d0: 8bfb ldrh r3, [r7, #30]
}
801a0d2: 4618 mov r0, r3
801a0d4: 3720 adds r7, #32
801a0d6: 46bd mov sp, r7
801a0d8: bd80 pop {r7, pc}
801a0da: bf00 nop
801a0dc: 0801eb50 .word 0x0801eb50
801a0e0: 0801eb8c .word 0x0801eb8c
801a0e4: 0801eb98 .word 0x0801eb98
801a0e8: 0801ebc0 .word 0x0801ebc0
801a0ec: 0801ebd4 .word 0x0801ebd4
801a0f0: 20008870 .word 0x20008870
801a0f4: 0801ebf4 .word 0x0801ebf4
0801a0f8 <ip_reass_remove_oldest_datagram>:
* (used for freeing other datagrams if not enough space)
* @return the number of pbufs freed
*/
static int
ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
{
801a0f8: b580 push {r7, lr}
801a0fa: b08a sub sp, #40 ; 0x28
801a0fc: af00 add r7, sp, #0
801a0fe: 6078 str r0, [r7, #4]
801a100: 6039 str r1, [r7, #0]
/* @todo Can't we simply remove the last datagram in the
* linked list behind reassdatagrams?
*/
struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
int pbufs_freed = 0, pbufs_freed_current;
801a102: 2300 movs r3, #0
801a104: 617b str r3, [r7, #20]
int other_datagrams;
/* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
* but don't free the datagram that 'fraghdr' belongs to! */
do {
oldest = NULL;
801a106: 2300 movs r3, #0
801a108: 623b str r3, [r7, #32]
prev = NULL;
801a10a: 2300 movs r3, #0
801a10c: 61fb str r3, [r7, #28]
oldest_prev = NULL;
801a10e: 2300 movs r3, #0
801a110: 61bb str r3, [r7, #24]
other_datagrams = 0;
801a112: 2300 movs r3, #0
801a114: 613b str r3, [r7, #16]
r = reassdatagrams;
801a116: 4b28 ldr r3, [pc, #160] ; (801a1b8 <ip_reass_remove_oldest_datagram+0xc0>)
801a118: 681b ldr r3, [r3, #0]
801a11a: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a11c: e030 b.n 801a180 <ip_reass_remove_oldest_datagram+0x88>
if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
801a11e: 6a7b ldr r3, [r7, #36] ; 0x24
801a120: 695a ldr r2, [r3, #20]
801a122: 687b ldr r3, [r7, #4]
801a124: 68db ldr r3, [r3, #12]
801a126: 429a cmp r2, r3
801a128: d10c bne.n 801a144 <ip_reass_remove_oldest_datagram+0x4c>
801a12a: 6a7b ldr r3, [r7, #36] ; 0x24
801a12c: 699a ldr r2, [r3, #24]
801a12e: 687b ldr r3, [r7, #4]
801a130: 691b ldr r3, [r3, #16]
801a132: 429a cmp r2, r3
801a134: d106 bne.n 801a144 <ip_reass_remove_oldest_datagram+0x4c>
801a136: 6a7b ldr r3, [r7, #36] ; 0x24
801a138: 899a ldrh r2, [r3, #12]
801a13a: 687b ldr r3, [r7, #4]
801a13c: 889b ldrh r3, [r3, #4]
801a13e: b29b uxth r3, r3
801a140: 429a cmp r2, r3
801a142: d014 beq.n 801a16e <ip_reass_remove_oldest_datagram+0x76>
/* Not the same datagram as fraghdr */
other_datagrams++;
801a144: 693b ldr r3, [r7, #16]
801a146: 3301 adds r3, #1
801a148: 613b str r3, [r7, #16]
if (oldest == NULL) {
801a14a: 6a3b ldr r3, [r7, #32]
801a14c: 2b00 cmp r3, #0
801a14e: d104 bne.n 801a15a <ip_reass_remove_oldest_datagram+0x62>
oldest = r;
801a150: 6a7b ldr r3, [r7, #36] ; 0x24
801a152: 623b str r3, [r7, #32]
oldest_prev = prev;
801a154: 69fb ldr r3, [r7, #28]
801a156: 61bb str r3, [r7, #24]
801a158: e009 b.n 801a16e <ip_reass_remove_oldest_datagram+0x76>
} else if (r->timer <= oldest->timer) {
801a15a: 6a7b ldr r3, [r7, #36] ; 0x24
801a15c: 7fda ldrb r2, [r3, #31]
801a15e: 6a3b ldr r3, [r7, #32]
801a160: 7fdb ldrb r3, [r3, #31]
801a162: 429a cmp r2, r3
801a164: d803 bhi.n 801a16e <ip_reass_remove_oldest_datagram+0x76>
/* older than the previous oldest */
oldest = r;
801a166: 6a7b ldr r3, [r7, #36] ; 0x24
801a168: 623b str r3, [r7, #32]
oldest_prev = prev;
801a16a: 69fb ldr r3, [r7, #28]
801a16c: 61bb str r3, [r7, #24]
}
}
if (r->next != NULL) {
801a16e: 6a7b ldr r3, [r7, #36] ; 0x24
801a170: 681b ldr r3, [r3, #0]
801a172: 2b00 cmp r3, #0
801a174: d001 beq.n 801a17a <ip_reass_remove_oldest_datagram+0x82>
prev = r;
801a176: 6a7b ldr r3, [r7, #36] ; 0x24
801a178: 61fb str r3, [r7, #28]
}
r = r->next;
801a17a: 6a7b ldr r3, [r7, #36] ; 0x24
801a17c: 681b ldr r3, [r3, #0]
801a17e: 627b str r3, [r7, #36] ; 0x24
while (r != NULL) {
801a180: 6a7b ldr r3, [r7, #36] ; 0x24
801a182: 2b00 cmp r3, #0
801a184: d1cb bne.n 801a11e <ip_reass_remove_oldest_datagram+0x26>
}
if (oldest != NULL) {
801a186: 6a3b ldr r3, [r7, #32]
801a188: 2b00 cmp r3, #0
801a18a: d008 beq.n 801a19e <ip_reass_remove_oldest_datagram+0xa6>
pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
801a18c: 69b9 ldr r1, [r7, #24]
801a18e: 6a38 ldr r0, [r7, #32]
801a190: f7ff ff0e bl 8019fb0 <ip_reass_free_complete_datagram>
801a194: 60f8 str r0, [r7, #12]
pbufs_freed += pbufs_freed_current;
801a196: 697a ldr r2, [r7, #20]
801a198: 68fb ldr r3, [r7, #12]
801a19a: 4413 add r3, r2
801a19c: 617b str r3, [r7, #20]
}
} while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
801a19e: 697a ldr r2, [r7, #20]
801a1a0: 683b ldr r3, [r7, #0]
801a1a2: 429a cmp r2, r3
801a1a4: da02 bge.n 801a1ac <ip_reass_remove_oldest_datagram+0xb4>
801a1a6: 693b ldr r3, [r7, #16]
801a1a8: 2b01 cmp r3, #1
801a1aa: dcac bgt.n 801a106 <ip_reass_remove_oldest_datagram+0xe>
return pbufs_freed;
801a1ac: 697b ldr r3, [r7, #20]
}
801a1ae: 4618 mov r0, r3
801a1b0: 3728 adds r7, #40 ; 0x28
801a1b2: 46bd mov sp, r7
801a1b4: bd80 pop {r7, pc}
801a1b6: bf00 nop
801a1b8: 2000886c .word 0x2000886c
0801a1bc <ip_reass_enqueue_new_datagram>:
* @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
* @return A pointer to the queue location into which the fragment was enqueued
*/
static struct ip_reassdata *
ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
{
801a1bc: b580 push {r7, lr}
801a1be: b084 sub sp, #16
801a1c0: af00 add r7, sp, #0
801a1c2: 6078 str r0, [r7, #4]
801a1c4: 6039 str r1, [r7, #0]
#if ! IP_REASS_FREE_OLDEST
LWIP_UNUSED_ARG(clen);
#endif
/* No matching previous fragment found, allocate a new reassdata struct */
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a1c6: 2004 movs r0, #4
801a1c8: f7f5 fb18 bl 800f7fc <memp_malloc>
801a1cc: 60f8 str r0, [r7, #12]
if (ipr == NULL) {
801a1ce: 68fb ldr r3, [r7, #12]
801a1d0: 2b00 cmp r3, #0
801a1d2: d110 bne.n 801a1f6 <ip_reass_enqueue_new_datagram+0x3a>
#if IP_REASS_FREE_OLDEST
if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
801a1d4: 6839 ldr r1, [r7, #0]
801a1d6: 6878 ldr r0, [r7, #4]
801a1d8: f7ff ff8e bl 801a0f8 <ip_reass_remove_oldest_datagram>
801a1dc: 4602 mov r2, r0
801a1de: 683b ldr r3, [r7, #0]
801a1e0: 4293 cmp r3, r2
801a1e2: dc03 bgt.n 801a1ec <ip_reass_enqueue_new_datagram+0x30>
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
801a1e4: 2004 movs r0, #4
801a1e6: f7f5 fb09 bl 800f7fc <memp_malloc>
801a1ea: 60f8 str r0, [r7, #12]
}
if (ipr == NULL)
801a1ec: 68fb ldr r3, [r7, #12]
801a1ee: 2b00 cmp r3, #0
801a1f0: d101 bne.n 801a1f6 <ip_reass_enqueue_new_datagram+0x3a>
#endif /* IP_REASS_FREE_OLDEST */
{
IPFRAG_STATS_INC(ip_frag.memerr);
LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
return NULL;
801a1f2: 2300 movs r3, #0
801a1f4: e016 b.n 801a224 <ip_reass_enqueue_new_datagram+0x68>
}
}
memset(ipr, 0, sizeof(struct ip_reassdata));
801a1f6: 2220 movs r2, #32
801a1f8: 2100 movs r1, #0
801a1fa: 68f8 ldr r0, [r7, #12]
801a1fc: f000 ff0a bl 801b014 <memset>
ipr->timer = IP_REASS_MAXAGE;
801a200: 68fb ldr r3, [r7, #12]
801a202: 220f movs r2, #15
801a204: 77da strb r2, [r3, #31]
/* enqueue the new structure to the front of the list */
ipr->next = reassdatagrams;
801a206: 4b09 ldr r3, [pc, #36] ; (801a22c <ip_reass_enqueue_new_datagram+0x70>)
801a208: 681a ldr r2, [r3, #0]
801a20a: 68fb ldr r3, [r7, #12]
801a20c: 601a str r2, [r3, #0]
reassdatagrams = ipr;
801a20e: 4a07 ldr r2, [pc, #28] ; (801a22c <ip_reass_enqueue_new_datagram+0x70>)
801a210: 68fb ldr r3, [r7, #12]
801a212: 6013 str r3, [r2, #0]
/* copy the ip header for later tests and input */
/* @todo: no ip options supported? */
SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
801a214: 68fb ldr r3, [r7, #12]
801a216: 3308 adds r3, #8
801a218: 2214 movs r2, #20
801a21a: 6879 ldr r1, [r7, #4]
801a21c: 4618 mov r0, r3
801a21e: f000 feee bl 801affe <memcpy>
return ipr;
801a222: 68fb ldr r3, [r7, #12]
}
801a224: 4618 mov r0, r3
801a226: 3710 adds r7, #16
801a228: 46bd mov sp, r7
801a22a: bd80 pop {r7, pc}
801a22c: 2000886c .word 0x2000886c
0801a230 <ip_reass_dequeue_datagram>:
* Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
* @param ipr points to the queue entry to dequeue
*/
static void
ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
{
801a230: b580 push {r7, lr}
801a232: b082 sub sp, #8
801a234: af00 add r7, sp, #0
801a236: 6078 str r0, [r7, #4]
801a238: 6039 str r1, [r7, #0]
/* dequeue the reass struct */
if (reassdatagrams == ipr) {
801a23a: 4b10 ldr r3, [pc, #64] ; (801a27c <ip_reass_dequeue_datagram+0x4c>)
801a23c: 681b ldr r3, [r3, #0]
801a23e: 687a ldr r2, [r7, #4]
801a240: 429a cmp r2, r3
801a242: d104 bne.n 801a24e <ip_reass_dequeue_datagram+0x1e>
/* it was the first in the list */
reassdatagrams = ipr->next;
801a244: 687b ldr r3, [r7, #4]
801a246: 681b ldr r3, [r3, #0]
801a248: 4a0c ldr r2, [pc, #48] ; (801a27c <ip_reass_dequeue_datagram+0x4c>)
801a24a: 6013 str r3, [r2, #0]
801a24c: e00d b.n 801a26a <ip_reass_dequeue_datagram+0x3a>
} else {
/* it wasn't the first, so it must have a valid 'prev' */
LWIP_ASSERT("sanity check linked list", prev != NULL);
801a24e: 683b ldr r3, [r7, #0]
801a250: 2b00 cmp r3, #0
801a252: d106 bne.n 801a262 <ip_reass_dequeue_datagram+0x32>
801a254: 4b0a ldr r3, [pc, #40] ; (801a280 <ip_reass_dequeue_datagram+0x50>)
801a256: f240 1245 movw r2, #325 ; 0x145
801a25a: 490a ldr r1, [pc, #40] ; (801a284 <ip_reass_dequeue_datagram+0x54>)
801a25c: 480a ldr r0, [pc, #40] ; (801a288 <ip_reass_dequeue_datagram+0x58>)
801a25e: f000 fee1 bl 801b024 <iprintf>
prev->next = ipr->next;
801a262: 687b ldr r3, [r7, #4]
801a264: 681a ldr r2, [r3, #0]
801a266: 683b ldr r3, [r7, #0]
801a268: 601a str r2, [r3, #0]
}
/* now we can free the ip_reassdata struct */
memp_free(MEMP_REASSDATA, ipr);
801a26a: 6879 ldr r1, [r7, #4]
801a26c: 2004 movs r0, #4
801a26e: f7f5 fb17 bl 800f8a0 <memp_free>
}
801a272: bf00 nop
801a274: 3708 adds r7, #8
801a276: 46bd mov sp, r7
801a278: bd80 pop {r7, pc}
801a27a: bf00 nop
801a27c: 2000886c .word 0x2000886c
801a280: 0801eb50 .word 0x0801eb50
801a284: 0801ec18 .word 0x0801ec18
801a288: 0801eb98 .word 0x0801eb98
0801a28c <ip_reass_chain_frag_into_datagram_and_validate>:
* @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
* @return see IP_REASS_VALIDATE_* defines
*/
static int
ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
{
801a28c: b580 push {r7, lr}
801a28e: b08c sub sp, #48 ; 0x30
801a290: af00 add r7, sp, #0
801a292: 60f8 str r0, [r7, #12]
801a294: 60b9 str r1, [r7, #8]
801a296: 607a str r2, [r7, #4]
struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
801a298: 2300 movs r3, #0
801a29a: 62bb str r3, [r7, #40] ; 0x28
struct pbuf *q;
u16_t offset, len;
u8_t hlen;
struct ip_hdr *fraghdr;
int valid = 1;
801a29c: 2301 movs r3, #1
801a29e: 623b str r3, [r7, #32]
/* Extract length and fragment offset from current fragment */
fraghdr = (struct ip_hdr *)new_p->payload;
801a2a0: 68bb ldr r3, [r7, #8]
801a2a2: 685b ldr r3, [r3, #4]
801a2a4: 61fb str r3, [r7, #28]
len = lwip_ntohs(IPH_LEN(fraghdr));
801a2a6: 69fb ldr r3, [r7, #28]
801a2a8: 885b ldrh r3, [r3, #2]
801a2aa: b29b uxth r3, r3
801a2ac: 4618 mov r0, r3
801a2ae: f7f4 fdef bl 800ee90 <lwip_htons>
801a2b2: 4603 mov r3, r0
801a2b4: 837b strh r3, [r7, #26]
hlen = IPH_HL_BYTES(fraghdr);
801a2b6: 69fb ldr r3, [r7, #28]
801a2b8: 781b ldrb r3, [r3, #0]
801a2ba: f003 030f and.w r3, r3, #15
801a2be: b2db uxtb r3, r3
801a2c0: 009b lsls r3, r3, #2
801a2c2: 767b strb r3, [r7, #25]
if (hlen > len) {
801a2c4: 7e7b ldrb r3, [r7, #25]
801a2c6: b29b uxth r3, r3
801a2c8: 8b7a ldrh r2, [r7, #26]
801a2ca: 429a cmp r2, r3
801a2cc: d202 bcs.n 801a2d4 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
/* invalid datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a2ce: f04f 33ff mov.w r3, #4294967295
801a2d2: e135 b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
len = (u16_t)(len - hlen);
801a2d4: 7e7b ldrb r3, [r7, #25]
801a2d6: b29b uxth r3, r3
801a2d8: 8b7a ldrh r2, [r7, #26]
801a2da: 1ad3 subs r3, r2, r3
801a2dc: 837b strh r3, [r7, #26]
offset = IPH_OFFSET_BYTES(fraghdr);
801a2de: 69fb ldr r3, [r7, #28]
801a2e0: 88db ldrh r3, [r3, #6]
801a2e2: b29b uxth r3, r3
801a2e4: 4618 mov r0, r3
801a2e6: f7f4 fdd3 bl 800ee90 <lwip_htons>
801a2ea: 4603 mov r3, r0
801a2ec: f3c3 030c ubfx r3, r3, #0, #13
801a2f0: b29b uxth r3, r3
801a2f2: 00db lsls r3, r3, #3
801a2f4: 82fb strh r3, [r7, #22]
/* overwrite the fragment's ip header from the pbuf with our helper struct,
* and setup the embedded helper structure. */
/* make sure the struct ip_reass_helper fits into the IP header */
LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
sizeof(struct ip_reass_helper) <= IP_HLEN);
iprh = (struct ip_reass_helper *)new_p->payload;
801a2f6: 68bb ldr r3, [r7, #8]
801a2f8: 685b ldr r3, [r3, #4]
801a2fa: 62fb str r3, [r7, #44] ; 0x2c
iprh->next_pbuf = NULL;
801a2fc: 6afb ldr r3, [r7, #44] ; 0x2c
801a2fe: 2200 movs r2, #0
801a300: 701a strb r2, [r3, #0]
801a302: 2200 movs r2, #0
801a304: 705a strb r2, [r3, #1]
801a306: 2200 movs r2, #0
801a308: 709a strb r2, [r3, #2]
801a30a: 2200 movs r2, #0
801a30c: 70da strb r2, [r3, #3]
iprh->start = offset;
801a30e: 6afb ldr r3, [r7, #44] ; 0x2c
801a310: 8afa ldrh r2, [r7, #22]
801a312: 809a strh r2, [r3, #4]
iprh->end = (u16_t)(offset + len);
801a314: 8afa ldrh r2, [r7, #22]
801a316: 8b7b ldrh r3, [r7, #26]
801a318: 4413 add r3, r2
801a31a: b29a uxth r2, r3
801a31c: 6afb ldr r3, [r7, #44] ; 0x2c
801a31e: 80da strh r2, [r3, #6]
if (iprh->end < offset) {
801a320: 6afb ldr r3, [r7, #44] ; 0x2c
801a322: 88db ldrh r3, [r3, #6]
801a324: b29b uxth r3, r3
801a326: 8afa ldrh r2, [r7, #22]
801a328: 429a cmp r2, r3
801a32a: d902 bls.n 801a332 <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
/* u16_t overflow, cannot handle this */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a32c: f04f 33ff mov.w r3, #4294967295
801a330: e106 b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* Iterate through until we either get to the end of the list (append),
* or we find one with a larger offset (insert). */
for (q = ipr->p; q != NULL;) {
801a332: 68fb ldr r3, [r7, #12]
801a334: 685b ldr r3, [r3, #4]
801a336: 627b str r3, [r7, #36] ; 0x24
801a338: e068 b.n 801a40c <ip_reass_chain_frag_into_datagram_and_validate+0x180>
iprh_tmp = (struct ip_reass_helper *)q->payload;
801a33a: 6a7b ldr r3, [r7, #36] ; 0x24
801a33c: 685b ldr r3, [r3, #4]
801a33e: 613b str r3, [r7, #16]
if (iprh->start < iprh_tmp->start) {
801a340: 6afb ldr r3, [r7, #44] ; 0x2c
801a342: 889b ldrh r3, [r3, #4]
801a344: b29a uxth r2, r3
801a346: 693b ldr r3, [r7, #16]
801a348: 889b ldrh r3, [r3, #4]
801a34a: b29b uxth r3, r3
801a34c: 429a cmp r2, r3
801a34e: d235 bcs.n 801a3bc <ip_reass_chain_frag_into_datagram_and_validate+0x130>
/* the new pbuf should be inserted before this */
iprh->next_pbuf = q;
801a350: 6afb ldr r3, [r7, #44] ; 0x2c
801a352: 6a7a ldr r2, [r7, #36] ; 0x24
801a354: 601a str r2, [r3, #0]
if (iprh_prev != NULL) {
801a356: 6abb ldr r3, [r7, #40] ; 0x28
801a358: 2b00 cmp r3, #0
801a35a: d020 beq.n 801a39e <ip_reass_chain_frag_into_datagram_and_validate+0x112>
/* not the fragment with the lowest offset */
#if IP_REASS_CHECK_OVERLAP
if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
801a35c: 6afb ldr r3, [r7, #44] ; 0x2c
801a35e: 889b ldrh r3, [r3, #4]
801a360: b29a uxth r2, r3
801a362: 6abb ldr r3, [r7, #40] ; 0x28
801a364: 88db ldrh r3, [r3, #6]
801a366: b29b uxth r3, r3
801a368: 429a cmp r2, r3
801a36a: d307 bcc.n 801a37c <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
801a36c: 6afb ldr r3, [r7, #44] ; 0x2c
801a36e: 88db ldrh r3, [r3, #6]
801a370: b29a uxth r2, r3
801a372: 693b ldr r3, [r7, #16]
801a374: 889b ldrh r3, [r3, #4]
801a376: b29b uxth r3, r3
801a378: 429a cmp r2, r3
801a37a: d902 bls.n 801a382 <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
/* fragment overlaps with previous or following, throw away */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a37c: f04f 33ff mov.w r3, #4294967295
801a380: e0de b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a382: 6abb ldr r3, [r7, #40] ; 0x28
801a384: 68ba ldr r2, [r7, #8]
801a386: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a388: 6abb ldr r3, [r7, #40] ; 0x28
801a38a: 88db ldrh r3, [r3, #6]
801a38c: b29a uxth r2, r3
801a38e: 6afb ldr r3, [r7, #44] ; 0x2c
801a390: 889b ldrh r3, [r3, #4]
801a392: b29b uxth r3, r3
801a394: 429a cmp r2, r3
801a396: d03d beq.n 801a414 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a398: 2300 movs r3, #0
801a39a: 623b str r3, [r7, #32]
}
#endif /* IP_REASS_CHECK_OVERLAP */
/* fragment with the lowest offset */
ipr->p = new_p;
}
break;
801a39c: e03a b.n 801a414 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
if (iprh->end > iprh_tmp->start) {
801a39e: 6afb ldr r3, [r7, #44] ; 0x2c
801a3a0: 88db ldrh r3, [r3, #6]
801a3a2: b29a uxth r2, r3
801a3a4: 693b ldr r3, [r7, #16]
801a3a6: 889b ldrh r3, [r3, #4]
801a3a8: b29b uxth r3, r3
801a3aa: 429a cmp r2, r3
801a3ac: d902 bls.n 801a3b4 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a3ae: f04f 33ff mov.w r3, #4294967295
801a3b2: e0c5 b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
ipr->p = new_p;
801a3b4: 68fb ldr r3, [r7, #12]
801a3b6: 68ba ldr r2, [r7, #8]
801a3b8: 605a str r2, [r3, #4]
break;
801a3ba: e02b b.n 801a414 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
} else if (iprh->start == iprh_tmp->start) {
801a3bc: 6afb ldr r3, [r7, #44] ; 0x2c
801a3be: 889b ldrh r3, [r3, #4]
801a3c0: b29a uxth r2, r3
801a3c2: 693b ldr r3, [r7, #16]
801a3c4: 889b ldrh r3, [r3, #4]
801a3c6: b29b uxth r3, r3
801a3c8: 429a cmp r2, r3
801a3ca: d102 bne.n 801a3d2 <ip_reass_chain_frag_into_datagram_and_validate+0x146>
/* received the same datagram twice: no need to keep the datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a3cc: f04f 33ff mov.w r3, #4294967295
801a3d0: e0b6 b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#if IP_REASS_CHECK_OVERLAP
} else if (iprh->start < iprh_tmp->end) {
801a3d2: 6afb ldr r3, [r7, #44] ; 0x2c
801a3d4: 889b ldrh r3, [r3, #4]
801a3d6: b29a uxth r2, r3
801a3d8: 693b ldr r3, [r7, #16]
801a3da: 88db ldrh r3, [r3, #6]
801a3dc: b29b uxth r3, r3
801a3de: 429a cmp r2, r3
801a3e0: d202 bcs.n 801a3e8 <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
/* overlap: no need to keep the new datagram */
return IP_REASS_VALIDATE_PBUF_DROPPED;
801a3e2: f04f 33ff mov.w r3, #4294967295
801a3e6: e0ab b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
#endif /* IP_REASS_CHECK_OVERLAP */
} else {
/* Check if the fragments received so far have no holes. */
if (iprh_prev != NULL) {
801a3e8: 6abb ldr r3, [r7, #40] ; 0x28
801a3ea: 2b00 cmp r3, #0
801a3ec: d009 beq.n 801a402 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
if (iprh_prev->end != iprh_tmp->start) {
801a3ee: 6abb ldr r3, [r7, #40] ; 0x28
801a3f0: 88db ldrh r3, [r3, #6]
801a3f2: b29a uxth r2, r3
801a3f4: 693b ldr r3, [r7, #16]
801a3f6: 889b ldrh r3, [r3, #4]
801a3f8: b29b uxth r3, r3
801a3fa: 429a cmp r2, r3
801a3fc: d001 beq.n 801a402 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
/* There is a fragment missing between the current
* and the previous fragment */
valid = 0;
801a3fe: 2300 movs r3, #0
801a400: 623b str r3, [r7, #32]
}
}
}
q = iprh_tmp->next_pbuf;
801a402: 693b ldr r3, [r7, #16]
801a404: 681b ldr r3, [r3, #0]
801a406: 627b str r3, [r7, #36] ; 0x24
iprh_prev = iprh_tmp;
801a408: 693b ldr r3, [r7, #16]
801a40a: 62bb str r3, [r7, #40] ; 0x28
for (q = ipr->p; q != NULL;) {
801a40c: 6a7b ldr r3, [r7, #36] ; 0x24
801a40e: 2b00 cmp r3, #0
801a410: d193 bne.n 801a33a <ip_reass_chain_frag_into_datagram_and_validate+0xae>
801a412: e000 b.n 801a416 <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
break;
801a414: bf00 nop
}
/* If q is NULL, then we made it to the end of the list. Determine what to do now */
if (q == NULL) {
801a416: 6a7b ldr r3, [r7, #36] ; 0x24
801a418: 2b00 cmp r3, #0
801a41a: d12d bne.n 801a478 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
if (iprh_prev != NULL) {
801a41c: 6abb ldr r3, [r7, #40] ; 0x28
801a41e: 2b00 cmp r3, #0
801a420: d01c beq.n 801a45c <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
/* this is (for now), the fragment with the highest offset:
* chain it to the last fragment */
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
801a422: 6abb ldr r3, [r7, #40] ; 0x28
801a424: 88db ldrh r3, [r3, #6]
801a426: b29a uxth r2, r3
801a428: 6afb ldr r3, [r7, #44] ; 0x2c
801a42a: 889b ldrh r3, [r3, #4]
801a42c: b29b uxth r3, r3
801a42e: 429a cmp r2, r3
801a430: d906 bls.n 801a440 <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
801a432: 4b45 ldr r3, [pc, #276] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a434: f44f 72db mov.w r2, #438 ; 0x1b6
801a438: 4944 ldr r1, [pc, #272] ; (801a54c <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
801a43a: 4845 ldr r0, [pc, #276] ; (801a550 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a43c: f000 fdf2 bl 801b024 <iprintf>
#endif /* IP_REASS_CHECK_OVERLAP */
iprh_prev->next_pbuf = new_p;
801a440: 6abb ldr r3, [r7, #40] ; 0x28
801a442: 68ba ldr r2, [r7, #8]
801a444: 601a str r2, [r3, #0]
if (iprh_prev->end != iprh->start) {
801a446: 6abb ldr r3, [r7, #40] ; 0x28
801a448: 88db ldrh r3, [r3, #6]
801a44a: b29a uxth r2, r3
801a44c: 6afb ldr r3, [r7, #44] ; 0x2c
801a44e: 889b ldrh r3, [r3, #4]
801a450: b29b uxth r3, r3
801a452: 429a cmp r2, r3
801a454: d010 beq.n 801a478 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
valid = 0;
801a456: 2300 movs r3, #0
801a458: 623b str r3, [r7, #32]
801a45a: e00d b.n 801a478 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
}
} else {
#if IP_REASS_CHECK_OVERLAP
LWIP_ASSERT("no previous fragment, this must be the first fragment!",
801a45c: 68fb ldr r3, [r7, #12]
801a45e: 685b ldr r3, [r3, #4]
801a460: 2b00 cmp r3, #0
801a462: d006 beq.n 801a472 <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
801a464: 4b38 ldr r3, [pc, #224] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a466: f240 12bf movw r2, #447 ; 0x1bf
801a46a: 493a ldr r1, [pc, #232] ; (801a554 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
801a46c: 4838 ldr r0, [pc, #224] ; (801a550 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a46e: f000 fdd9 bl 801b024 <iprintf>
ipr->p == NULL);
#endif /* IP_REASS_CHECK_OVERLAP */
/* this is the first fragment we ever received for this ip datagram */
ipr->p = new_p;
801a472: 68fb ldr r3, [r7, #12]
801a474: 68ba ldr r2, [r7, #8]
801a476: 605a str r2, [r3, #4]
}
}
/* At this point, the validation part begins: */
/* If we already received the last fragment */
if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
801a478: 687b ldr r3, [r7, #4]
801a47a: 2b00 cmp r3, #0
801a47c: d105 bne.n 801a48a <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
801a47e: 68fb ldr r3, [r7, #12]
801a480: 7f9b ldrb r3, [r3, #30]
801a482: f003 0301 and.w r3, r3, #1
801a486: 2b00 cmp r3, #0
801a488: d059 beq.n 801a53e <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
/* and had no holes so far */
if (valid) {
801a48a: 6a3b ldr r3, [r7, #32]
801a48c: 2b00 cmp r3, #0
801a48e: d04f beq.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
/* then check if the rest of the fragments is here */
/* Check if the queue starts with the first datagram */
if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
801a490: 68fb ldr r3, [r7, #12]
801a492: 685b ldr r3, [r3, #4]
801a494: 2b00 cmp r3, #0
801a496: d006 beq.n 801a4a6 <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
801a498: 68fb ldr r3, [r7, #12]
801a49a: 685b ldr r3, [r3, #4]
801a49c: 685b ldr r3, [r3, #4]
801a49e: 889b ldrh r3, [r3, #4]
801a4a0: b29b uxth r3, r3
801a4a2: 2b00 cmp r3, #0
801a4a4: d002 beq.n 801a4ac <ip_reass_chain_frag_into_datagram_and_validate+0x220>
valid = 0;
801a4a6: 2300 movs r3, #0
801a4a8: 623b str r3, [r7, #32]
801a4aa: e041 b.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
} else {
/* and check that there are no holes after this datagram */
iprh_prev = iprh;
801a4ac: 6afb ldr r3, [r7, #44] ; 0x2c
801a4ae: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a4b0: 6afb ldr r3, [r7, #44] ; 0x2c
801a4b2: 681b ldr r3, [r3, #0]
801a4b4: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a4b6: e012 b.n 801a4de <ip_reass_chain_frag_into_datagram_and_validate+0x252>
iprh = (struct ip_reass_helper *)q->payload;
801a4b8: 6a7b ldr r3, [r7, #36] ; 0x24
801a4ba: 685b ldr r3, [r3, #4]
801a4bc: 62fb str r3, [r7, #44] ; 0x2c
if (iprh_prev->end != iprh->start) {
801a4be: 6abb ldr r3, [r7, #40] ; 0x28
801a4c0: 88db ldrh r3, [r3, #6]
801a4c2: b29a uxth r2, r3
801a4c4: 6afb ldr r3, [r7, #44] ; 0x2c
801a4c6: 889b ldrh r3, [r3, #4]
801a4c8: b29b uxth r3, r3
801a4ca: 429a cmp r2, r3
801a4cc: d002 beq.n 801a4d4 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
valid = 0;
801a4ce: 2300 movs r3, #0
801a4d0: 623b str r3, [r7, #32]
break;
801a4d2: e007 b.n 801a4e4 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
}
iprh_prev = iprh;
801a4d4: 6afb ldr r3, [r7, #44] ; 0x2c
801a4d6: 62bb str r3, [r7, #40] ; 0x28
q = iprh->next_pbuf;
801a4d8: 6afb ldr r3, [r7, #44] ; 0x2c
801a4da: 681b ldr r3, [r3, #0]
801a4dc: 627b str r3, [r7, #36] ; 0x24
while (q != NULL) {
801a4de: 6a7b ldr r3, [r7, #36] ; 0x24
801a4e0: 2b00 cmp r3, #0
801a4e2: d1e9 bne.n 801a4b8 <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
}
/* if still valid, all fragments are received
* (because to the MF==0 already arrived */
if (valid) {
801a4e4: 6a3b ldr r3, [r7, #32]
801a4e6: 2b00 cmp r3, #0
801a4e8: d022 beq.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
LWIP_ASSERT("sanity check", ipr->p != NULL);
801a4ea: 68fb ldr r3, [r7, #12]
801a4ec: 685b ldr r3, [r3, #4]
801a4ee: 2b00 cmp r3, #0
801a4f0: d106 bne.n 801a500 <ip_reass_chain_frag_into_datagram_and_validate+0x274>
801a4f2: 4b15 ldr r3, [pc, #84] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a4f4: f240 12df movw r2, #479 ; 0x1df
801a4f8: 4917 ldr r1, [pc, #92] ; (801a558 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a4fa: 4815 ldr r0, [pc, #84] ; (801a550 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a4fc: f000 fd92 bl 801b024 <iprintf>
LWIP_ASSERT("sanity check",
801a500: 68fb ldr r3, [r7, #12]
801a502: 685b ldr r3, [r3, #4]
801a504: 685b ldr r3, [r3, #4]
801a506: 6afa ldr r2, [r7, #44] ; 0x2c
801a508: 429a cmp r2, r3
801a50a: d106 bne.n 801a51a <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
801a50c: 4b0e ldr r3, [pc, #56] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a50e: f240 12e1 movw r2, #481 ; 0x1e1
801a512: 4911 ldr r1, [pc, #68] ; (801a558 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
801a514: 480e ldr r0, [pc, #56] ; (801a550 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a516: f000 fd85 bl 801b024 <iprintf>
((struct ip_reass_helper *)ipr->p->payload) != iprh);
LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
801a51a: 6afb ldr r3, [r7, #44] ; 0x2c
801a51c: 681b ldr r3, [r3, #0]
801a51e: 2b00 cmp r3, #0
801a520: d006 beq.n 801a530 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
801a522: 4b09 ldr r3, [pc, #36] ; (801a548 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
801a524: f240 12e3 movw r2, #483 ; 0x1e3
801a528: 490c ldr r1, [pc, #48] ; (801a55c <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
801a52a: 4809 ldr r0, [pc, #36] ; (801a550 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
801a52c: f000 fd7a bl 801b024 <iprintf>
}
}
/* If valid is 0 here, there are some fragments missing in the middle
* (since MF == 0 has already arrived). Such datagrams simply time out if
* no more fragments are received... */
return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
801a530: 6a3b ldr r3, [r7, #32]
801a532: 2b00 cmp r3, #0
801a534: bf14 ite ne
801a536: 2301 movne r3, #1
801a538: 2300 moveq r3, #0
801a53a: b2db uxtb r3, r3
801a53c: e000 b.n 801a540 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
}
/* If we come here, not all fragments were received, yet! */
return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
801a53e: 2300 movs r3, #0
}
801a540: 4618 mov r0, r3
801a542: 3730 adds r7, #48 ; 0x30
801a544: 46bd mov sp, r7
801a546: bd80 pop {r7, pc}
801a548: 0801eb50 .word 0x0801eb50
801a54c: 0801ec34 .word 0x0801ec34
801a550: 0801eb98 .word 0x0801eb98
801a554: 0801ec54 .word 0x0801ec54
801a558: 0801ec8c .word 0x0801ec8c
801a55c: 0801ec9c .word 0x0801ec9c
0801a560 <ip4_reass>:
* @param p points to a pbuf chain of the fragment
* @return NULL if reassembly is incomplete, ? otherwise
*/
struct pbuf *
ip4_reass(struct pbuf *p)
{
801a560: b580 push {r7, lr}
801a562: b08e sub sp, #56 ; 0x38
801a564: af00 add r7, sp, #0
801a566: 6078 str r0, [r7, #4]
int is_last;
IPFRAG_STATS_INC(ip_frag.recv);
MIB2_STATS_INC(mib2.ipreasmreqds);
fraghdr = (struct ip_hdr *)p->payload;
801a568: 687b ldr r3, [r7, #4]
801a56a: 685b ldr r3, [r3, #4]
801a56c: 62bb str r3, [r7, #40] ; 0x28
if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
801a56e: 6abb ldr r3, [r7, #40] ; 0x28
801a570: 781b ldrb r3, [r3, #0]
801a572: f003 030f and.w r3, r3, #15
801a576: b2db uxtb r3, r3
801a578: 009b lsls r3, r3, #2
801a57a: b2db uxtb r3, r3
801a57c: 2b14 cmp r3, #20
801a57e: f040 8167 bne.w 801a850 <ip4_reass+0x2f0>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
IPFRAG_STATS_INC(ip_frag.err);
goto nullreturn;
}
offset = IPH_OFFSET_BYTES(fraghdr);
801a582: 6abb ldr r3, [r7, #40] ; 0x28
801a584: 88db ldrh r3, [r3, #6]
801a586: b29b uxth r3, r3
801a588: 4618 mov r0, r3
801a58a: f7f4 fc81 bl 800ee90 <lwip_htons>
801a58e: 4603 mov r3, r0
801a590: f3c3 030c ubfx r3, r3, #0, #13
801a594: b29b uxth r3, r3
801a596: 00db lsls r3, r3, #3
801a598: 84fb strh r3, [r7, #38] ; 0x26
len = lwip_ntohs(IPH_LEN(fraghdr));
801a59a: 6abb ldr r3, [r7, #40] ; 0x28
801a59c: 885b ldrh r3, [r3, #2]
801a59e: b29b uxth r3, r3
801a5a0: 4618 mov r0, r3
801a5a2: f7f4 fc75 bl 800ee90 <lwip_htons>
801a5a6: 4603 mov r3, r0
801a5a8: 84bb strh r3, [r7, #36] ; 0x24
hlen = IPH_HL_BYTES(fraghdr);
801a5aa: 6abb ldr r3, [r7, #40] ; 0x28
801a5ac: 781b ldrb r3, [r3, #0]
801a5ae: f003 030f and.w r3, r3, #15
801a5b2: b2db uxtb r3, r3
801a5b4: 009b lsls r3, r3, #2
801a5b6: f887 3023 strb.w r3, [r7, #35] ; 0x23
if (hlen > len) {
801a5ba: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a5be: b29b uxth r3, r3
801a5c0: 8cba ldrh r2, [r7, #36] ; 0x24
801a5c2: 429a cmp r2, r3
801a5c4: f0c0 8146 bcc.w 801a854 <ip4_reass+0x2f4>
/* invalid datagram */
goto nullreturn;
}
len = (u16_t)(len - hlen);
801a5c8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
801a5cc: b29b uxth r3, r3
801a5ce: 8cba ldrh r2, [r7, #36] ; 0x24
801a5d0: 1ad3 subs r3, r2, r3
801a5d2: 84bb strh r3, [r7, #36] ; 0x24
/* Check if we are allowed to enqueue more datagrams. */
clen = pbuf_clen(p);
801a5d4: 6878 ldr r0, [r7, #4]
801a5d6: f7f6 f89d bl 8010714 <pbuf_clen>
801a5da: 4603 mov r3, r0
801a5dc: 843b strh r3, [r7, #32]
if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
801a5de: 4ba3 ldr r3, [pc, #652] ; (801a86c <ip4_reass+0x30c>)
801a5e0: 881b ldrh r3, [r3, #0]
801a5e2: 461a mov r2, r3
801a5e4: 8c3b ldrh r3, [r7, #32]
801a5e6: 4413 add r3, r2
801a5e8: 2b0a cmp r3, #10
801a5ea: dd10 ble.n 801a60e <ip4_reass+0xae>
#if IP_REASS_FREE_OLDEST
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a5ec: 8c3b ldrh r3, [r7, #32]
801a5ee: 4619 mov r1, r3
801a5f0: 6ab8 ldr r0, [r7, #40] ; 0x28
801a5f2: f7ff fd81 bl 801a0f8 <ip_reass_remove_oldest_datagram>
801a5f6: 4603 mov r3, r0
801a5f8: 2b00 cmp r3, #0
801a5fa: f000 812d beq.w 801a858 <ip4_reass+0x2f8>
((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
801a5fe: 4b9b ldr r3, [pc, #620] ; (801a86c <ip4_reass+0x30c>)
801a600: 881b ldrh r3, [r3, #0]
801a602: 461a mov r2, r3
801a604: 8c3b ldrh r3, [r7, #32]
801a606: 4413 add r3, r2
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
801a608: 2b0a cmp r3, #10
801a60a: f300 8125 bgt.w 801a858 <ip4_reass+0x2f8>
}
}
/* Look for the datagram the fragment belongs to in the current datagram queue,
* remembering the previous in the queue for later dequeueing. */
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a60e: 4b98 ldr r3, [pc, #608] ; (801a870 <ip4_reass+0x310>)
801a610: 681b ldr r3, [r3, #0]
801a612: 633b str r3, [r7, #48] ; 0x30
801a614: e015 b.n 801a642 <ip4_reass+0xe2>
/* Check if the incoming fragment matches the one currently present
in the reassembly buffer. If so, we proceed with copying the
fragment into the buffer. */
if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
801a616: 6b3b ldr r3, [r7, #48] ; 0x30
801a618: 695a ldr r2, [r3, #20]
801a61a: 6abb ldr r3, [r7, #40] ; 0x28
801a61c: 68db ldr r3, [r3, #12]
801a61e: 429a cmp r2, r3
801a620: d10c bne.n 801a63c <ip4_reass+0xdc>
801a622: 6b3b ldr r3, [r7, #48] ; 0x30
801a624: 699a ldr r2, [r3, #24]
801a626: 6abb ldr r3, [r7, #40] ; 0x28
801a628: 691b ldr r3, [r3, #16]
801a62a: 429a cmp r2, r3
801a62c: d106 bne.n 801a63c <ip4_reass+0xdc>
801a62e: 6b3b ldr r3, [r7, #48] ; 0x30
801a630: 899a ldrh r2, [r3, #12]
801a632: 6abb ldr r3, [r7, #40] ; 0x28
801a634: 889b ldrh r3, [r3, #4]
801a636: b29b uxth r3, r3
801a638: 429a cmp r2, r3
801a63a: d006 beq.n 801a64a <ip4_reass+0xea>
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
801a63c: 6b3b ldr r3, [r7, #48] ; 0x30
801a63e: 681b ldr r3, [r3, #0]
801a640: 633b str r3, [r7, #48] ; 0x30
801a642: 6b3b ldr r3, [r7, #48] ; 0x30
801a644: 2b00 cmp r3, #0
801a646: d1e6 bne.n 801a616 <ip4_reass+0xb6>
801a648: e000 b.n 801a64c <ip4_reass+0xec>
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
lwip_ntohs(IPH_ID(fraghdr))));
IPFRAG_STATS_INC(ip_frag.cachehit);
break;
801a64a: bf00 nop
}
}
if (ipr == NULL) {
801a64c: 6b3b ldr r3, [r7, #48] ; 0x30
801a64e: 2b00 cmp r3, #0
801a650: d109 bne.n 801a666 <ip4_reass+0x106>
/* Enqueue a new datagram into the datagram queue */
ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
801a652: 8c3b ldrh r3, [r7, #32]
801a654: 4619 mov r1, r3
801a656: 6ab8 ldr r0, [r7, #40] ; 0x28
801a658: f7ff fdb0 bl 801a1bc <ip_reass_enqueue_new_datagram>
801a65c: 6338 str r0, [r7, #48] ; 0x30
/* Bail if unable to enqueue */
if (ipr == NULL) {
801a65e: 6b3b ldr r3, [r7, #48] ; 0x30
801a660: 2b00 cmp r3, #0
801a662: d11c bne.n 801a69e <ip4_reass+0x13e>
goto nullreturn;
801a664: e0f9 b.n 801a85a <ip4_reass+0x2fa>
}
} else {
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a666: 6abb ldr r3, [r7, #40] ; 0x28
801a668: 88db ldrh r3, [r3, #6]
801a66a: b29b uxth r3, r3
801a66c: 4618 mov r0, r3
801a66e: f7f4 fc0f bl 800ee90 <lwip_htons>
801a672: 4603 mov r3, r0
801a674: f3c3 030c ubfx r3, r3, #0, #13
801a678: 2b00 cmp r3, #0
801a67a: d110 bne.n 801a69e <ip4_reass+0x13e>
((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
801a67c: 6b3b ldr r3, [r7, #48] ; 0x30
801a67e: 89db ldrh r3, [r3, #14]
801a680: 4618 mov r0, r3
801a682: f7f4 fc05 bl 800ee90 <lwip_htons>
801a686: 4603 mov r3, r0
801a688: f3c3 030c ubfx r3, r3, #0, #13
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
801a68c: 2b00 cmp r3, #0
801a68e: d006 beq.n 801a69e <ip4_reass+0x13e>
/* ipr->iphdr is not the header from the first fragment, but fraghdr is
* -> copy fraghdr into ipr->iphdr since we want to have the header
* of the first fragment (for ICMP time exceeded and later, for copying
* all options, if supported)*/
SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
801a690: 6b3b ldr r3, [r7, #48] ; 0x30
801a692: 3308 adds r3, #8
801a694: 2214 movs r2, #20
801a696: 6ab9 ldr r1, [r7, #40] ; 0x28
801a698: 4618 mov r0, r3
801a69a: f000 fcb0 bl 801affe <memcpy>
/* At this point, we have either created a new entry or pointing
* to an existing one */
/* check for 'no more fragments', and update queue entry*/
is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
801a69e: 6abb ldr r3, [r7, #40] ; 0x28
801a6a0: 88db ldrh r3, [r3, #6]
801a6a2: b29b uxth r3, r3
801a6a4: f003 0320 and.w r3, r3, #32
801a6a8: 2b00 cmp r3, #0
801a6aa: bf0c ite eq
801a6ac: 2301 moveq r3, #1
801a6ae: 2300 movne r3, #0
801a6b0: b2db uxtb r3, r3
801a6b2: 61fb str r3, [r7, #28]
if (is_last) {
801a6b4: 69fb ldr r3, [r7, #28]
801a6b6: 2b00 cmp r3, #0
801a6b8: d00e beq.n 801a6d8 <ip4_reass+0x178>
u16_t datagram_len = (u16_t)(offset + len);
801a6ba: 8cfa ldrh r2, [r7, #38] ; 0x26
801a6bc: 8cbb ldrh r3, [r7, #36] ; 0x24
801a6be: 4413 add r3, r2
801a6c0: 837b strh r3, [r7, #26]
if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
801a6c2: 8b7a ldrh r2, [r7, #26]
801a6c4: 8cfb ldrh r3, [r7, #38] ; 0x26
801a6c6: 429a cmp r2, r3
801a6c8: f0c0 80a0 bcc.w 801a80c <ip4_reass+0x2ac>
801a6cc: 8b7b ldrh r3, [r7, #26]
801a6ce: f64f 72eb movw r2, #65515 ; 0xffeb
801a6d2: 4293 cmp r3, r2
801a6d4: f200 809a bhi.w 801a80c <ip4_reass+0x2ac>
goto nullreturn_ipr;
}
}
/* find the right place to insert this pbuf */
/* @todo: trim pbufs if fragments are overlapping */
valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
801a6d8: 69fa ldr r2, [r7, #28]
801a6da: 6879 ldr r1, [r7, #4]
801a6dc: 6b38 ldr r0, [r7, #48] ; 0x30
801a6de: f7ff fdd5 bl 801a28c <ip_reass_chain_frag_into_datagram_and_validate>
801a6e2: 6178 str r0, [r7, #20]
if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
801a6e4: 697b ldr r3, [r7, #20]
801a6e6: f1b3 3fff cmp.w r3, #4294967295
801a6ea: f000 8091 beq.w 801a810 <ip4_reass+0x2b0>
/* if we come here, the pbuf has been enqueued */
/* Track the current number of pbufs current 'in-flight', in order to limit
the number of fragments that may be enqueued at any one time
(overflow checked by testing against IP_REASS_MAX_PBUFS) */
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
801a6ee: 4b5f ldr r3, [pc, #380] ; (801a86c <ip4_reass+0x30c>)
801a6f0: 881a ldrh r2, [r3, #0]
801a6f2: 8c3b ldrh r3, [r7, #32]
801a6f4: 4413 add r3, r2
801a6f6: b29a uxth r2, r3
801a6f8: 4b5c ldr r3, [pc, #368] ; (801a86c <ip4_reass+0x30c>)
801a6fa: 801a strh r2, [r3, #0]
if (is_last) {
801a6fc: 69fb ldr r3, [r7, #28]
801a6fe: 2b00 cmp r3, #0
801a700: d00d beq.n 801a71e <ip4_reass+0x1be>
u16_t datagram_len = (u16_t)(offset + len);
801a702: 8cfa ldrh r2, [r7, #38] ; 0x26
801a704: 8cbb ldrh r3, [r7, #36] ; 0x24
801a706: 4413 add r3, r2
801a708: 827b strh r3, [r7, #18]
ipr->datagram_len = datagram_len;
801a70a: 6b3b ldr r3, [r7, #48] ; 0x30
801a70c: 8a7a ldrh r2, [r7, #18]
801a70e: 839a strh r2, [r3, #28]
ipr->flags |= IP_REASS_FLAG_LASTFRAG;
801a710: 6b3b ldr r3, [r7, #48] ; 0x30
801a712: 7f9b ldrb r3, [r3, #30]
801a714: f043 0301 orr.w r3, r3, #1
801a718: b2da uxtb r2, r3
801a71a: 6b3b ldr r3, [r7, #48] ; 0x30
801a71c: 779a strb r2, [r3, #30]
LWIP_DEBUGF(IP_REASS_DEBUG,
("ip4_reass: last fragment seen, total len %"S16_F"\n",
ipr->datagram_len));
}
if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
801a71e: 697b ldr r3, [r7, #20]
801a720: 2b01 cmp r3, #1
801a722: d171 bne.n 801a808 <ip4_reass+0x2a8>
struct ip_reassdata *ipr_prev;
/* the totally last fragment (flag more fragments = 0) was received at least
* once AND all fragments are received */
u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
801a724: 6b3b ldr r3, [r7, #48] ; 0x30
801a726: 8b9b ldrh r3, [r3, #28]
801a728: 3314 adds r3, #20
801a72a: 823b strh r3, [r7, #16]
/* save the second pbuf before copying the header over the pointer */
r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
801a72c: 6b3b ldr r3, [r7, #48] ; 0x30
801a72e: 685b ldr r3, [r3, #4]
801a730: 685b ldr r3, [r3, #4]
801a732: 681b ldr r3, [r3, #0]
801a734: 637b str r3, [r7, #52] ; 0x34
/* copy the original ip header back to the first pbuf */
fraghdr = (struct ip_hdr *)(ipr->p->payload);
801a736: 6b3b ldr r3, [r7, #48] ; 0x30
801a738: 685b ldr r3, [r3, #4]
801a73a: 685b ldr r3, [r3, #4]
801a73c: 62bb str r3, [r7, #40] ; 0x28
SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
801a73e: 6b3b ldr r3, [r7, #48] ; 0x30
801a740: 3308 adds r3, #8
801a742: 2214 movs r2, #20
801a744: 4619 mov r1, r3
801a746: 6ab8 ldr r0, [r7, #40] ; 0x28
801a748: f000 fc59 bl 801affe <memcpy>
IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
801a74c: 8a3b ldrh r3, [r7, #16]
801a74e: 4618 mov r0, r3
801a750: f7f4 fb9e bl 800ee90 <lwip_htons>
801a754: 4603 mov r3, r0
801a756: 461a mov r2, r3
801a758: 6abb ldr r3, [r7, #40] ; 0x28
801a75a: 805a strh r2, [r3, #2]
IPH_OFFSET_SET(fraghdr, 0);
801a75c: 6abb ldr r3, [r7, #40] ; 0x28
801a75e: 2200 movs r2, #0
801a760: 719a strb r2, [r3, #6]
801a762: 2200 movs r2, #0
801a764: 71da strb r2, [r3, #7]
IPH_CHKSUM_SET(fraghdr, 0);
801a766: 6abb ldr r3, [r7, #40] ; 0x28
801a768: 2200 movs r2, #0
801a76a: 729a strb r2, [r3, #10]
801a76c: 2200 movs r2, #0
801a76e: 72da strb r2, [r3, #11]
IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
}
#endif /* CHECKSUM_GEN_IP */
p = ipr->p;
801a770: 6b3b ldr r3, [r7, #48] ; 0x30
801a772: 685b ldr r3, [r3, #4]
801a774: 607b str r3, [r7, #4]
/* chain together the pbufs contained within the reass_data list. */
while (r != NULL) {
801a776: e00d b.n 801a794 <ip4_reass+0x234>
iprh = (struct ip_reass_helper *)r->payload;
801a778: 6b7b ldr r3, [r7, #52] ; 0x34
801a77a: 685b ldr r3, [r3, #4]
801a77c: 60fb str r3, [r7, #12]
/* hide the ip header for every succeeding fragment */
pbuf_remove_header(r, IP_HLEN);
801a77e: 2114 movs r1, #20
801a780: 6b78 ldr r0, [r7, #52] ; 0x34
801a782: f7f5 feb3 bl 80104ec <pbuf_remove_header>
pbuf_cat(p, r);
801a786: 6b79 ldr r1, [r7, #52] ; 0x34
801a788: 6878 ldr r0, [r7, #4]
801a78a: f7f6 f803 bl 8010794 <pbuf_cat>
r = iprh->next_pbuf;
801a78e: 68fb ldr r3, [r7, #12]
801a790: 681b ldr r3, [r3, #0]
801a792: 637b str r3, [r7, #52] ; 0x34
while (r != NULL) {
801a794: 6b7b ldr r3, [r7, #52] ; 0x34
801a796: 2b00 cmp r3, #0
801a798: d1ee bne.n 801a778 <ip4_reass+0x218>
}
/* find the previous entry in the linked list */
if (ipr == reassdatagrams) {
801a79a: 4b35 ldr r3, [pc, #212] ; (801a870 <ip4_reass+0x310>)
801a79c: 681b ldr r3, [r3, #0]
801a79e: 6b3a ldr r2, [r7, #48] ; 0x30
801a7a0: 429a cmp r2, r3
801a7a2: d102 bne.n 801a7aa <ip4_reass+0x24a>
ipr_prev = NULL;
801a7a4: 2300 movs r3, #0
801a7a6: 62fb str r3, [r7, #44] ; 0x2c
801a7a8: e010 b.n 801a7cc <ip4_reass+0x26c>
} else {
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a7aa: 4b31 ldr r3, [pc, #196] ; (801a870 <ip4_reass+0x310>)
801a7ac: 681b ldr r3, [r3, #0]
801a7ae: 62fb str r3, [r7, #44] ; 0x2c
801a7b0: e007 b.n 801a7c2 <ip4_reass+0x262>
if (ipr_prev->next == ipr) {
801a7b2: 6afb ldr r3, [r7, #44] ; 0x2c
801a7b4: 681b ldr r3, [r3, #0]
801a7b6: 6b3a ldr r2, [r7, #48] ; 0x30
801a7b8: 429a cmp r2, r3
801a7ba: d006 beq.n 801a7ca <ip4_reass+0x26a>
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
801a7bc: 6afb ldr r3, [r7, #44] ; 0x2c
801a7be: 681b ldr r3, [r3, #0]
801a7c0: 62fb str r3, [r7, #44] ; 0x2c
801a7c2: 6afb ldr r3, [r7, #44] ; 0x2c
801a7c4: 2b00 cmp r3, #0
801a7c6: d1f4 bne.n 801a7b2 <ip4_reass+0x252>
801a7c8: e000 b.n 801a7cc <ip4_reass+0x26c>
break;
801a7ca: bf00 nop
}
}
}
/* release the sources allocate for the fragment queue entry */
ip_reass_dequeue_datagram(ipr, ipr_prev);
801a7cc: 6af9 ldr r1, [r7, #44] ; 0x2c
801a7ce: 6b38 ldr r0, [r7, #48] ; 0x30
801a7d0: f7ff fd2e bl 801a230 <ip_reass_dequeue_datagram>
/* and adjust the number of pbufs currently queued for reassembly. */
clen = pbuf_clen(p);
801a7d4: 6878 ldr r0, [r7, #4]
801a7d6: f7f5 ff9d bl 8010714 <pbuf_clen>
801a7da: 4603 mov r3, r0
801a7dc: 843b strh r3, [r7, #32]
LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
801a7de: 4b23 ldr r3, [pc, #140] ; (801a86c <ip4_reass+0x30c>)
801a7e0: 881b ldrh r3, [r3, #0]
801a7e2: 8c3a ldrh r2, [r7, #32]
801a7e4: 429a cmp r2, r3
801a7e6: d906 bls.n 801a7f6 <ip4_reass+0x296>
801a7e8: 4b22 ldr r3, [pc, #136] ; (801a874 <ip4_reass+0x314>)
801a7ea: f240 229b movw r2, #667 ; 0x29b
801a7ee: 4922 ldr r1, [pc, #136] ; (801a878 <ip4_reass+0x318>)
801a7f0: 4822 ldr r0, [pc, #136] ; (801a87c <ip4_reass+0x31c>)
801a7f2: f000 fc17 bl 801b024 <iprintf>
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
801a7f6: 4b1d ldr r3, [pc, #116] ; (801a86c <ip4_reass+0x30c>)
801a7f8: 881a ldrh r2, [r3, #0]
801a7fa: 8c3b ldrh r3, [r7, #32]
801a7fc: 1ad3 subs r3, r2, r3
801a7fe: b29a uxth r2, r3
801a800: 4b1a ldr r3, [pc, #104] ; (801a86c <ip4_reass+0x30c>)
801a802: 801a strh r2, [r3, #0]
MIB2_STATS_INC(mib2.ipreasmoks);
/* Return the pbuf chain */
return p;
801a804: 687b ldr r3, [r7, #4]
801a806: e02c b.n 801a862 <ip4_reass+0x302>
}
/* the datagram is not (yet?) reassembled completely */
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
return NULL;
801a808: 2300 movs r3, #0
801a80a: e02a b.n 801a862 <ip4_reass+0x302>
nullreturn_ipr:
801a80c: bf00 nop
801a80e: e000 b.n 801a812 <ip4_reass+0x2b2>
goto nullreturn_ipr;
801a810: bf00 nop
LWIP_ASSERT("ipr != NULL", ipr != NULL);
801a812: 6b3b ldr r3, [r7, #48] ; 0x30
801a814: 2b00 cmp r3, #0
801a816: d106 bne.n 801a826 <ip4_reass+0x2c6>
801a818: 4b16 ldr r3, [pc, #88] ; (801a874 <ip4_reass+0x314>)
801a81a: f44f 722a mov.w r2, #680 ; 0x2a8
801a81e: 4918 ldr r1, [pc, #96] ; (801a880 <ip4_reass+0x320>)
801a820: 4816 ldr r0, [pc, #88] ; (801a87c <ip4_reass+0x31c>)
801a822: f000 fbff bl 801b024 <iprintf>
if (ipr->p == NULL) {
801a826: 6b3b ldr r3, [r7, #48] ; 0x30
801a828: 685b ldr r3, [r3, #4]
801a82a: 2b00 cmp r3, #0
801a82c: d114 bne.n 801a858 <ip4_reass+0x2f8>
/* dropped pbuf after creating a new datagram entry: remove the entry, too */
LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
801a82e: 4b10 ldr r3, [pc, #64] ; (801a870 <ip4_reass+0x310>)
801a830: 681b ldr r3, [r3, #0]
801a832: 6b3a ldr r2, [r7, #48] ; 0x30
801a834: 429a cmp r2, r3
801a836: d006 beq.n 801a846 <ip4_reass+0x2e6>
801a838: 4b0e ldr r3, [pc, #56] ; (801a874 <ip4_reass+0x314>)
801a83a: f240 22ab movw r2, #683 ; 0x2ab
801a83e: 4911 ldr r1, [pc, #68] ; (801a884 <ip4_reass+0x324>)
801a840: 480e ldr r0, [pc, #56] ; (801a87c <ip4_reass+0x31c>)
801a842: f000 fbef bl 801b024 <iprintf>
ip_reass_dequeue_datagram(ipr, NULL);
801a846: 2100 movs r1, #0
801a848: 6b38 ldr r0, [r7, #48] ; 0x30
801a84a: f7ff fcf1 bl 801a230 <ip_reass_dequeue_datagram>
801a84e: e004 b.n 801a85a <ip4_reass+0x2fa>
goto nullreturn;
801a850: bf00 nop
801a852: e002 b.n 801a85a <ip4_reass+0x2fa>
goto nullreturn;
801a854: bf00 nop
801a856: e000 b.n 801a85a <ip4_reass+0x2fa>
}
nullreturn:
801a858: bf00 nop
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
IPFRAG_STATS_INC(ip_frag.drop);
pbuf_free(p);
801a85a: 6878 ldr r0, [r7, #4]
801a85c: f7f5 fecc bl 80105f8 <pbuf_free>
return NULL;
801a860: 2300 movs r3, #0
}
801a862: 4618 mov r0, r3
801a864: 3738 adds r7, #56 ; 0x38
801a866: 46bd mov sp, r7
801a868: bd80 pop {r7, pc}
801a86a: bf00 nop
801a86c: 20008870 .word 0x20008870
801a870: 2000886c .word 0x2000886c
801a874: 0801eb50 .word 0x0801eb50
801a878: 0801ecc0 .word 0x0801ecc0
801a87c: 0801eb98 .word 0x0801eb98
801a880: 0801ecdc .word 0x0801ecdc
801a884: 0801ece8 .word 0x0801ece8
0801a888 <ip_frag_alloc_pbuf_custom_ref>:
#if IP_FRAG
#if !LWIP_NETIF_TX_SINGLE_PBUF
/** Allocate a new struct pbuf_custom_ref */
static struct pbuf_custom_ref *
ip_frag_alloc_pbuf_custom_ref(void)
{
801a888: b580 push {r7, lr}
801a88a: af00 add r7, sp, #0
return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
801a88c: 2005 movs r0, #5
801a88e: f7f4 ffb5 bl 800f7fc <memp_malloc>
801a892: 4603 mov r3, r0
}
801a894: 4618 mov r0, r3
801a896: bd80 pop {r7, pc}
0801a898 <ip_frag_free_pbuf_custom_ref>:
/** Free a struct pbuf_custom_ref */
static void
ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
{
801a898: b580 push {r7, lr}
801a89a: b082 sub sp, #8
801a89c: af00 add r7, sp, #0
801a89e: 6078 str r0, [r7, #4]
LWIP_ASSERT("p != NULL", p != NULL);
801a8a0: 687b ldr r3, [r7, #4]
801a8a2: 2b00 cmp r3, #0
801a8a4: d106 bne.n 801a8b4 <ip_frag_free_pbuf_custom_ref+0x1c>
801a8a6: 4b07 ldr r3, [pc, #28] ; (801a8c4 <ip_frag_free_pbuf_custom_ref+0x2c>)
801a8a8: f44f 7231 mov.w r2, #708 ; 0x2c4
801a8ac: 4906 ldr r1, [pc, #24] ; (801a8c8 <ip_frag_free_pbuf_custom_ref+0x30>)
801a8ae: 4807 ldr r0, [pc, #28] ; (801a8cc <ip_frag_free_pbuf_custom_ref+0x34>)
801a8b0: f000 fbb8 bl 801b024 <iprintf>
memp_free(MEMP_FRAG_PBUF, p);
801a8b4: 6879 ldr r1, [r7, #4]
801a8b6: 2005 movs r0, #5
801a8b8: f7f4 fff2 bl 800f8a0 <memp_free>
}
801a8bc: bf00 nop
801a8be: 3708 adds r7, #8
801a8c0: 46bd mov sp, r7
801a8c2: bd80 pop {r7, pc}
801a8c4: 0801eb50 .word 0x0801eb50
801a8c8: 0801ed08 .word 0x0801ed08
801a8cc: 0801eb98 .word 0x0801eb98
0801a8d0 <ipfrag_free_pbuf_custom>:
/** Free-callback function to free a 'struct pbuf_custom_ref', called by
* pbuf_free. */
static void
ipfrag_free_pbuf_custom(struct pbuf *p)
{
801a8d0: b580 push {r7, lr}
801a8d2: b084 sub sp, #16
801a8d4: af00 add r7, sp, #0
801a8d6: 6078 str r0, [r7, #4]
struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
801a8d8: 687b ldr r3, [r7, #4]
801a8da: 60fb str r3, [r7, #12]
LWIP_ASSERT("pcr != NULL", pcr != NULL);
801a8dc: 68fb ldr r3, [r7, #12]
801a8de: 2b00 cmp r3, #0
801a8e0: d106 bne.n 801a8f0 <ipfrag_free_pbuf_custom+0x20>
801a8e2: 4b11 ldr r3, [pc, #68] ; (801a928 <ipfrag_free_pbuf_custom+0x58>)
801a8e4: f240 22ce movw r2, #718 ; 0x2ce
801a8e8: 4910 ldr r1, [pc, #64] ; (801a92c <ipfrag_free_pbuf_custom+0x5c>)
801a8ea: 4811 ldr r0, [pc, #68] ; (801a930 <ipfrag_free_pbuf_custom+0x60>)
801a8ec: f000 fb9a bl 801b024 <iprintf>
LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
801a8f0: 68fa ldr r2, [r7, #12]
801a8f2: 687b ldr r3, [r7, #4]
801a8f4: 429a cmp r2, r3
801a8f6: d006 beq.n 801a906 <ipfrag_free_pbuf_custom+0x36>
801a8f8: 4b0b ldr r3, [pc, #44] ; (801a928 <ipfrag_free_pbuf_custom+0x58>)
801a8fa: f240 22cf movw r2, #719 ; 0x2cf
801a8fe: 490d ldr r1, [pc, #52] ; (801a934 <ipfrag_free_pbuf_custom+0x64>)
801a900: 480b ldr r0, [pc, #44] ; (801a930 <ipfrag_free_pbuf_custom+0x60>)
801a902: f000 fb8f bl 801b024 <iprintf>
if (pcr->original != NULL) {
801a906: 68fb ldr r3, [r7, #12]
801a908: 695b ldr r3, [r3, #20]
801a90a: 2b00 cmp r3, #0
801a90c: d004 beq.n 801a918 <ipfrag_free_pbuf_custom+0x48>
pbuf_free(pcr->original);
801a90e: 68fb ldr r3, [r7, #12]
801a910: 695b ldr r3, [r3, #20]
801a912: 4618 mov r0, r3
801a914: f7f5 fe70 bl 80105f8 <pbuf_free>
}
ip_frag_free_pbuf_custom_ref(pcr);
801a918: 68f8 ldr r0, [r7, #12]
801a91a: f7ff ffbd bl 801a898 <ip_frag_free_pbuf_custom_ref>
}
801a91e: bf00 nop
801a920: 3710 adds r7, #16
801a922: 46bd mov sp, r7
801a924: bd80 pop {r7, pc}
801a926: bf00 nop
801a928: 0801eb50 .word 0x0801eb50
801a92c: 0801ed14 .word 0x0801ed14
801a930: 0801eb98 .word 0x0801eb98
801a934: 0801ed20 .word 0x0801ed20
0801a938 <ip4_frag>:
*
* @return ERR_OK if sent successfully, err_t otherwise
*/
err_t
ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
{
801a938: b580 push {r7, lr}
801a93a: b094 sub sp, #80 ; 0x50
801a93c: af02 add r7, sp, #8
801a93e: 60f8 str r0, [r7, #12]
801a940: 60b9 str r1, [r7, #8]
801a942: 607a str r2, [r7, #4]
struct pbuf *rambuf;
#if !LWIP_NETIF_TX_SINGLE_PBUF
struct pbuf *newpbuf;
u16_t newpbuflen = 0;
801a944: 2300 movs r3, #0
801a946: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
u16_t left_to_copy;
#endif
struct ip_hdr *original_iphdr;
struct ip_hdr *iphdr;
const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
801a94a: 68bb ldr r3, [r7, #8]
801a94c: 8d1b ldrh r3, [r3, #40] ; 0x28
801a94e: 3b14 subs r3, #20
801a950: 2b00 cmp r3, #0
801a952: da00 bge.n 801a956 <ip4_frag+0x1e>
801a954: 3307 adds r3, #7
801a956: 10db asrs r3, r3, #3
801a958: 877b strh r3, [r7, #58] ; 0x3a
u16_t left, fragsize;
u16_t ofo;
int last;
u16_t poff = IP_HLEN;
801a95a: 2314 movs r3, #20
801a95c: 87fb strh r3, [r7, #62] ; 0x3e
u16_t tmp;
int mf_set;
original_iphdr = (struct ip_hdr *)p->payload;
801a95e: 68fb ldr r3, [r7, #12]
801a960: 685b ldr r3, [r3, #4]
801a962: 637b str r3, [r7, #52] ; 0x34
iphdr = original_iphdr;
801a964: 6b7b ldr r3, [r7, #52] ; 0x34
801a966: 633b str r3, [r7, #48] ; 0x30
if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
801a968: 6b3b ldr r3, [r7, #48] ; 0x30
801a96a: 781b ldrb r3, [r3, #0]
801a96c: f003 030f and.w r3, r3, #15
801a970: b2db uxtb r3, r3
801a972: 009b lsls r3, r3, #2
801a974: b2db uxtb r3, r3
801a976: 2b14 cmp r3, #20
801a978: d002 beq.n 801a980 <ip4_frag+0x48>
/* ip4_frag() does not support IP options */
return ERR_VAL;
801a97a: f06f 0305 mvn.w r3, #5
801a97e: e10f b.n 801aba0 <ip4_frag+0x268>
}
LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
801a980: 68fb ldr r3, [r7, #12]
801a982: 895b ldrh r3, [r3, #10]
801a984: 2b13 cmp r3, #19
801a986: d809 bhi.n 801a99c <ip4_frag+0x64>
801a988: 4b87 ldr r3, [pc, #540] ; (801aba8 <ip4_frag+0x270>)
801a98a: f44f 723f mov.w r2, #764 ; 0x2fc
801a98e: 4987 ldr r1, [pc, #540] ; (801abac <ip4_frag+0x274>)
801a990: 4887 ldr r0, [pc, #540] ; (801abb0 <ip4_frag+0x278>)
801a992: f000 fb47 bl 801b024 <iprintf>
801a996: f06f 0305 mvn.w r3, #5
801a99a: e101 b.n 801aba0 <ip4_frag+0x268>
/* Save original offset */
tmp = lwip_ntohs(IPH_OFFSET(iphdr));
801a99c: 6b3b ldr r3, [r7, #48] ; 0x30
801a99e: 88db ldrh r3, [r3, #6]
801a9a0: b29b uxth r3, r3
801a9a2: 4618 mov r0, r3
801a9a4: f7f4 fa74 bl 800ee90 <lwip_htons>
801a9a8: 4603 mov r3, r0
801a9aa: 87bb strh r3, [r7, #60] ; 0x3c
ofo = tmp & IP_OFFMASK;
801a9ac: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a9ae: f3c3 030c ubfx r3, r3, #0, #13
801a9b2: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
/* already fragmented? if so, the last fragment we create must have MF, too */
mf_set = tmp & IP_MF;
801a9b6: 8fbb ldrh r3, [r7, #60] ; 0x3c
801a9b8: f403 5300 and.w r3, r3, #8192 ; 0x2000
801a9bc: 62fb str r3, [r7, #44] ; 0x2c
left = (u16_t)(p->tot_len - IP_HLEN);
801a9be: 68fb ldr r3, [r7, #12]
801a9c0: 891b ldrh r3, [r3, #8]
801a9c2: 3b14 subs r3, #20
801a9c4: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
while (left) {
801a9c8: e0e0 b.n 801ab8c <ip4_frag+0x254>
/* Fill this fragment */
fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
801a9ca: 8f7b ldrh r3, [r7, #58] ; 0x3a
801a9cc: 00db lsls r3, r3, #3
801a9ce: b29b uxth r3, r3
801a9d0: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801a9d4: 4293 cmp r3, r2
801a9d6: bf28 it cs
801a9d8: 4613 movcs r3, r2
801a9da: 857b strh r3, [r7, #42] ; 0x2a
/* When not using a static buffer, create a chain of pbufs.
* The first will be a PBUF_RAM holding the link and IP header.
* The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
* but limited to the size of an mtu.
*/
rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
801a9dc: f44f 7220 mov.w r2, #640 ; 0x280
801a9e0: 2114 movs r1, #20
801a9e2: 200e movs r0, #14
801a9e4: f7f5 fb28 bl 8010038 <pbuf_alloc>
801a9e8: 6278 str r0, [r7, #36] ; 0x24
if (rambuf == NULL) {
801a9ea: 6a7b ldr r3, [r7, #36] ; 0x24
801a9ec: 2b00 cmp r3, #0
801a9ee: f000 80d4 beq.w 801ab9a <ip4_frag+0x262>
goto memerr;
}
LWIP_ASSERT("this needs a pbuf in one piece!",
801a9f2: 6a7b ldr r3, [r7, #36] ; 0x24
801a9f4: 895b ldrh r3, [r3, #10]
801a9f6: 2b13 cmp r3, #19
801a9f8: d806 bhi.n 801aa08 <ip4_frag+0xd0>
801a9fa: 4b6b ldr r3, [pc, #428] ; (801aba8 <ip4_frag+0x270>)
801a9fc: f240 3225 movw r2, #805 ; 0x325
801aa00: 496c ldr r1, [pc, #432] ; (801abb4 <ip4_frag+0x27c>)
801aa02: 486b ldr r0, [pc, #428] ; (801abb0 <ip4_frag+0x278>)
801aa04: f000 fb0e bl 801b024 <iprintf>
(rambuf->len >= (IP_HLEN)));
SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
801aa08: 6a7b ldr r3, [r7, #36] ; 0x24
801aa0a: 685b ldr r3, [r3, #4]
801aa0c: 2214 movs r2, #20
801aa0e: 6b79 ldr r1, [r7, #52] ; 0x34
801aa10: 4618 mov r0, r3
801aa12: f000 faf4 bl 801affe <memcpy>
iphdr = (struct ip_hdr *)rambuf->payload;
801aa16: 6a7b ldr r3, [r7, #36] ; 0x24
801aa18: 685b ldr r3, [r3, #4]
801aa1a: 633b str r3, [r7, #48] ; 0x30
left_to_copy = fragsize;
801aa1c: 8d7b ldrh r3, [r7, #42] ; 0x2a
801aa1e: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
while (left_to_copy) {
801aa22: e064 b.n 801aaee <ip4_frag+0x1b6>
struct pbuf_custom_ref *pcr;
u16_t plen = (u16_t)(p->len - poff);
801aa24: 68fb ldr r3, [r7, #12]
801aa26: 895a ldrh r2, [r3, #10]
801aa28: 8ffb ldrh r3, [r7, #62] ; 0x3e
801aa2a: 1ad3 subs r3, r2, r3
801aa2c: 83fb strh r3, [r7, #30]
LWIP_ASSERT("p->len >= poff", p->len >= poff);
801aa2e: 68fb ldr r3, [r7, #12]
801aa30: 895b ldrh r3, [r3, #10]
801aa32: 8ffa ldrh r2, [r7, #62] ; 0x3e
801aa34: 429a cmp r2, r3
801aa36: d906 bls.n 801aa46 <ip4_frag+0x10e>
801aa38: 4b5b ldr r3, [pc, #364] ; (801aba8 <ip4_frag+0x270>)
801aa3a: f240 322d movw r2, #813 ; 0x32d
801aa3e: 495e ldr r1, [pc, #376] ; (801abb8 <ip4_frag+0x280>)
801aa40: 485b ldr r0, [pc, #364] ; (801abb0 <ip4_frag+0x278>)
801aa42: f000 faef bl 801b024 <iprintf>
newpbuflen = LWIP_MIN(left_to_copy, plen);
801aa46: 8bfa ldrh r2, [r7, #30]
801aa48: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aa4c: 4293 cmp r3, r2
801aa4e: bf28 it cs
801aa50: 4613 movcs r3, r2
801aa52: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
/* Is this pbuf already empty? */
if (!newpbuflen) {
801aa56: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aa5a: 2b00 cmp r3, #0
801aa5c: d105 bne.n 801aa6a <ip4_frag+0x132>
poff = 0;
801aa5e: 2300 movs r3, #0
801aa60: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801aa62: 68fb ldr r3, [r7, #12]
801aa64: 681b ldr r3, [r3, #0]
801aa66: 60fb str r3, [r7, #12]
continue;
801aa68: e041 b.n 801aaee <ip4_frag+0x1b6>
}
pcr = ip_frag_alloc_pbuf_custom_ref();
801aa6a: f7ff ff0d bl 801a888 <ip_frag_alloc_pbuf_custom_ref>
801aa6e: 61b8 str r0, [r7, #24]
if (pcr == NULL) {
801aa70: 69bb ldr r3, [r7, #24]
801aa72: 2b00 cmp r3, #0
801aa74: d103 bne.n 801aa7e <ip4_frag+0x146>
pbuf_free(rambuf);
801aa76: 6a78 ldr r0, [r7, #36] ; 0x24
801aa78: f7f5 fdbe bl 80105f8 <pbuf_free>
goto memerr;
801aa7c: e08e b.n 801ab9c <ip4_frag+0x264>
}
/* Mirror this pbuf, although we might not need all of it. */
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa7e: 69b8 ldr r0, [r7, #24]
(u8_t *)p->payload + poff, newpbuflen);
801aa80: 68fb ldr r3, [r7, #12]
801aa82: 685a ldr r2, [r3, #4]
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
801aa84: 8ffb ldrh r3, [r7, #62] ; 0x3e
801aa86: 4413 add r3, r2
801aa88: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46
801aa8c: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
801aa90: 9201 str r2, [sp, #4]
801aa92: 9300 str r3, [sp, #0]
801aa94: 4603 mov r3, r0
801aa96: 2241 movs r2, #65 ; 0x41
801aa98: 2000 movs r0, #0
801aa9a: f7f5 fbf3 bl 8010284 <pbuf_alloced_custom>
801aa9e: 6178 str r0, [r7, #20]
if (newpbuf == NULL) {
801aaa0: 697b ldr r3, [r7, #20]
801aaa2: 2b00 cmp r3, #0
801aaa4: d106 bne.n 801aab4 <ip4_frag+0x17c>
ip_frag_free_pbuf_custom_ref(pcr);
801aaa6: 69b8 ldr r0, [r7, #24]
801aaa8: f7ff fef6 bl 801a898 <ip_frag_free_pbuf_custom_ref>
pbuf_free(rambuf);
801aaac: 6a78 ldr r0, [r7, #36] ; 0x24
801aaae: f7f5 fda3 bl 80105f8 <pbuf_free>
goto memerr;
801aab2: e073 b.n 801ab9c <ip4_frag+0x264>
}
pbuf_ref(p);
801aab4: 68f8 ldr r0, [r7, #12]
801aab6: f7f5 fe45 bl 8010744 <pbuf_ref>
pcr->original = p;
801aaba: 69bb ldr r3, [r7, #24]
801aabc: 68fa ldr r2, [r7, #12]
801aabe: 615a str r2, [r3, #20]
pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
801aac0: 69bb ldr r3, [r7, #24]
801aac2: 4a3e ldr r2, [pc, #248] ; (801abbc <ip4_frag+0x284>)
801aac4: 611a str r2, [r3, #16]
/* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
* so that it is removed when pbuf_dechain is later called on rambuf.
*/
pbuf_cat(rambuf, newpbuf);
801aac6: 6979 ldr r1, [r7, #20]
801aac8: 6a78 ldr r0, [r7, #36] ; 0x24
801aaca: f7f5 fe63 bl 8010794 <pbuf_cat>
left_to_copy = (u16_t)(left_to_copy - newpbuflen);
801aace: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44
801aad2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aad6: 1ad3 subs r3, r2, r3
801aad8: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if (left_to_copy) {
801aadc: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aae0: 2b00 cmp r3, #0
801aae2: d004 beq.n 801aaee <ip4_frag+0x1b6>
poff = 0;
801aae4: 2300 movs r3, #0
801aae6: 87fb strh r3, [r7, #62] ; 0x3e
p = p->next;
801aae8: 68fb ldr r3, [r7, #12]
801aaea: 681b ldr r3, [r3, #0]
801aaec: 60fb str r3, [r7, #12]
while (left_to_copy) {
801aaee: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
801aaf2: 2b00 cmp r3, #0
801aaf4: d196 bne.n 801aa24 <ip4_frag+0xec>
}
}
poff = (u16_t)(poff + newpbuflen);
801aaf6: 8ffa ldrh r2, [r7, #62] ; 0x3e
801aaf8: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
801aafc: 4413 add r3, r2
801aafe: 87fb strh r3, [r7, #62] ; 0x3e
#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
/* Correct header */
last = (left <= netif->mtu - IP_HLEN);
801ab00: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801ab04: 68bb ldr r3, [r7, #8]
801ab06: 8d1b ldrh r3, [r3, #40] ; 0x28
801ab08: 3b14 subs r3, #20
801ab0a: 429a cmp r2, r3
801ab0c: bfd4 ite le
801ab0e: 2301 movle r3, #1
801ab10: 2300 movgt r3, #0
801ab12: b2db uxtb r3, r3
801ab14: 623b str r3, [r7, #32]
/* Set new offset and MF flag */
tmp = (IP_OFFMASK & (ofo));
801ab16: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
801ab1a: f3c3 030c ubfx r3, r3, #0, #13
801ab1e: 87bb strh r3, [r7, #60] ; 0x3c
if (!last || mf_set) {
801ab20: 6a3b ldr r3, [r7, #32]
801ab22: 2b00 cmp r3, #0
801ab24: d002 beq.n 801ab2c <ip4_frag+0x1f4>
801ab26: 6afb ldr r3, [r7, #44] ; 0x2c
801ab28: 2b00 cmp r3, #0
801ab2a: d003 beq.n 801ab34 <ip4_frag+0x1fc>
/* the last fragment has MF set if the input frame had it */
tmp = tmp | IP_MF;
801ab2c: 8fbb ldrh r3, [r7, #60] ; 0x3c
801ab2e: f443 5300 orr.w r3, r3, #8192 ; 0x2000
801ab32: 87bb strh r3, [r7, #60] ; 0x3c
}
IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
801ab34: 8fbb ldrh r3, [r7, #60] ; 0x3c
801ab36: 4618 mov r0, r3
801ab38: f7f4 f9aa bl 800ee90 <lwip_htons>
801ab3c: 4603 mov r3, r0
801ab3e: 461a mov r2, r3
801ab40: 6b3b ldr r3, [r7, #48] ; 0x30
801ab42: 80da strh r2, [r3, #6]
IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
801ab44: 8d7b ldrh r3, [r7, #42] ; 0x2a
801ab46: 3314 adds r3, #20
801ab48: b29b uxth r3, r3
801ab4a: 4618 mov r0, r3
801ab4c: f7f4 f9a0 bl 800ee90 <lwip_htons>
801ab50: 4603 mov r3, r0
801ab52: 461a mov r2, r3
801ab54: 6b3b ldr r3, [r7, #48] ; 0x30
801ab56: 805a strh r2, [r3, #2]
IPH_CHKSUM_SET(iphdr, 0);
801ab58: 6b3b ldr r3, [r7, #48] ; 0x30
801ab5a: 2200 movs r2, #0
801ab5c: 729a strb r2, [r3, #10]
801ab5e: 2200 movs r2, #0
801ab60: 72da strb r2, [r3, #11]
#endif /* CHECKSUM_GEN_IP */
/* No need for separate header pbuf - we allowed room for it in rambuf
* when allocated.
*/
netif->output(netif, rambuf, dest);
801ab62: 68bb ldr r3, [r7, #8]
801ab64: 695b ldr r3, [r3, #20]
801ab66: 687a ldr r2, [r7, #4]
801ab68: 6a79 ldr r1, [r7, #36] ; 0x24
801ab6a: 68b8 ldr r0, [r7, #8]
801ab6c: 4798 blx r3
* recreate it next time round the loop. If we're lucky the hardware
* will have already sent the packet, the free will really free, and
* there will be zero memory penalty.
*/
pbuf_free(rambuf);
801ab6e: 6a78 ldr r0, [r7, #36] ; 0x24
801ab70: f7f5 fd42 bl 80105f8 <pbuf_free>
left = (u16_t)(left - fragsize);
801ab74: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
801ab78: 8d7b ldrh r3, [r7, #42] ; 0x2a
801ab7a: 1ad3 subs r3, r2, r3
801ab7c: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
ofo = (u16_t)(ofo + nfb);
801ab80: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40
801ab84: 8f7b ldrh r3, [r7, #58] ; 0x3a
801ab86: 4413 add r3, r2
801ab88: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
while (left) {
801ab8c: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
801ab90: 2b00 cmp r3, #0
801ab92: f47f af1a bne.w 801a9ca <ip4_frag+0x92>
}
MIB2_STATS_INC(mib2.ipfragoks);
return ERR_OK;
801ab96: 2300 movs r3, #0
801ab98: e002 b.n 801aba0 <ip4_frag+0x268>
goto memerr;
801ab9a: bf00 nop
memerr:
MIB2_STATS_INC(mib2.ipfragfails);
return ERR_MEM;
801ab9c: f04f 33ff mov.w r3, #4294967295
}
801aba0: 4618 mov r0, r3
801aba2: 3748 adds r7, #72 ; 0x48
801aba4: 46bd mov sp, r7
801aba6: bd80 pop {r7, pc}
801aba8: 0801eb50 .word 0x0801eb50
801abac: 0801ed2c .word 0x0801ed2c
801abb0: 0801eb98 .word 0x0801eb98
801abb4: 0801ed48 .word 0x0801ed48
801abb8: 0801ed68 .word 0x0801ed68
801abbc: 0801a8d1 .word 0x0801a8d1
0801abc0 <ethernet_input>:
* @see ETHARP_SUPPORT_VLAN
* @see LWIP_HOOK_VLAN_CHECK
*/
err_t
ethernet_input(struct pbuf *p, struct netif *netif)
{
801abc0: b580 push {r7, lr}
801abc2: b086 sub sp, #24
801abc4: af00 add r7, sp, #0
801abc6: 6078 str r0, [r7, #4]
801abc8: 6039 str r1, [r7, #0]
struct eth_hdr *ethhdr;
u16_t type;
#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
u16_t next_hdr_offset = SIZEOF_ETH_HDR;
801abca: 230e movs r3, #14
801abcc: 82fb strh r3, [r7, #22]
#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
LWIP_ASSERT_CORE_LOCKED();
if (p->len <= SIZEOF_ETH_HDR) {
801abce: 687b ldr r3, [r7, #4]
801abd0: 895b ldrh r3, [r3, #10]
801abd2: 2b0e cmp r3, #14
801abd4: d96e bls.n 801acb4 <ethernet_input+0xf4>
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinerrors);
goto free_and_return;
}
if (p->if_idx == NETIF_NO_INDEX) {
801abd6: 687b ldr r3, [r7, #4]
801abd8: 7bdb ldrb r3, [r3, #15]
801abda: 2b00 cmp r3, #0
801abdc: d106 bne.n 801abec <ethernet_input+0x2c>
p->if_idx = netif_get_index(netif);
801abde: 683b ldr r3, [r7, #0]
801abe0: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
801abe4: 3301 adds r3, #1
801abe6: b2da uxtb r2, r3
801abe8: 687b ldr r3, [r7, #4]
801abea: 73da strb r2, [r3, #15]
}
/* points to packet payload, which starts with an Ethernet header */
ethhdr = (struct eth_hdr *)p->payload;
801abec: 687b ldr r3, [r7, #4]
801abee: 685b ldr r3, [r3, #4]
801abf0: 613b str r3, [r7, #16]
(unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
(unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2],
(unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5],
lwip_htons(ethhdr->type)));
type = ethhdr->type;
801abf2: 693b ldr r3, [r7, #16]
801abf4: 7b1a ldrb r2, [r3, #12]
801abf6: 7b5b ldrb r3, [r3, #13]
801abf8: 021b lsls r3, r3, #8
801abfa: 4313 orrs r3, r2
801abfc: 81fb strh r3, [r7, #14]
#if LWIP_ARP_FILTER_NETIF
netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
#endif /* LWIP_ARP_FILTER_NETIF*/
if (ethhdr->dest.addr[0] & 1) {
801abfe: 693b ldr r3, [r7, #16]
801ac00: 781b ldrb r3, [r3, #0]
801ac02: f003 0301 and.w r3, r3, #1
801ac06: 2b00 cmp r3, #0
801ac08: d023 beq.n 801ac52 <ethernet_input+0x92>
/* this might be a multicast or broadcast packet */
if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
801ac0a: 693b ldr r3, [r7, #16]
801ac0c: 781b ldrb r3, [r3, #0]
801ac0e: 2b01 cmp r3, #1
801ac10: d10f bne.n 801ac32 <ethernet_input+0x72>
#if LWIP_IPV4
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801ac12: 693b ldr r3, [r7, #16]
801ac14: 785b ldrb r3, [r3, #1]
801ac16: 2b00 cmp r3, #0
801ac18: d11b bne.n 801ac52 <ethernet_input+0x92>
(ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
801ac1a: 693b ldr r3, [r7, #16]
801ac1c: 789b ldrb r3, [r3, #2]
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
801ac1e: 2b5e cmp r3, #94 ; 0x5e
801ac20: d117 bne.n 801ac52 <ethernet_input+0x92>
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
801ac22: 687b ldr r3, [r7, #4]
801ac24: 7b5b ldrb r3, [r3, #13]
801ac26: f043 0310 orr.w r3, r3, #16
801ac2a: b2da uxtb r2, r3
801ac2c: 687b ldr r3, [r7, #4]
801ac2e: 735a strb r2, [r3, #13]
801ac30: e00f b.n 801ac52 <ethernet_input+0x92>
(ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
/* mark the pbuf as link-layer multicast */
p->flags |= PBUF_FLAG_LLMCAST;
}
#endif /* LWIP_IPV6 */
else if (eth_addr_cmp(&ethhdr->dest, &ethbroadcast)) {
801ac32: 693b ldr r3, [r7, #16]
801ac34: 2206 movs r2, #6
801ac36: 4928 ldr r1, [pc, #160] ; (801acd8 <ethernet_input+0x118>)
801ac38: 4618 mov r0, r3
801ac3a: f000 f9d1 bl 801afe0 <memcmp>
801ac3e: 4603 mov r3, r0
801ac40: 2b00 cmp r3, #0
801ac42: d106 bne.n 801ac52 <ethernet_input+0x92>
/* mark the pbuf as link-layer broadcast */
p->flags |= PBUF_FLAG_LLBCAST;
801ac44: 687b ldr r3, [r7, #4]
801ac46: 7b5b ldrb r3, [r3, #13]
801ac48: f043 0308 orr.w r3, r3, #8
801ac4c: b2da uxtb r2, r3
801ac4e: 687b ldr r3, [r7, #4]
801ac50: 735a strb r2, [r3, #13]
}
}
switch (type) {
801ac52: 89fb ldrh r3, [r7, #14]
801ac54: 2b08 cmp r3, #8
801ac56: d003 beq.n 801ac60 <ethernet_input+0xa0>
801ac58: f5b3 6fc1 cmp.w r3, #1544 ; 0x608
801ac5c: d014 beq.n 801ac88 <ethernet_input+0xc8>
}
#endif
ETHARP_STATS_INC(etharp.proterr);
ETHARP_STATS_INC(etharp.drop);
MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
goto free_and_return;
801ac5e: e032 b.n 801acc6 <ethernet_input+0x106>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801ac60: 683b ldr r3, [r7, #0]
801ac62: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac66: f003 0308 and.w r3, r3, #8
801ac6a: 2b00 cmp r3, #0
801ac6c: d024 beq.n 801acb8 <ethernet_input+0xf8>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac6e: 8afb ldrh r3, [r7, #22]
801ac70: 4619 mov r1, r3
801ac72: 6878 ldr r0, [r7, #4]
801ac74: f7f5 fc3a bl 80104ec <pbuf_remove_header>
801ac78: 4603 mov r3, r0
801ac7a: 2b00 cmp r3, #0
801ac7c: d11e bne.n 801acbc <ethernet_input+0xfc>
ip4_input(p, netif);
801ac7e: 6839 ldr r1, [r7, #0]
801ac80: 6878 ldr r0, [r7, #4]
801ac82: f7fe ff0f bl 8019aa4 <ip4_input>
break;
801ac86: e013 b.n 801acb0 <ethernet_input+0xf0>
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
801ac88: 683b ldr r3, [r7, #0]
801ac8a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
801ac8e: f003 0308 and.w r3, r3, #8
801ac92: 2b00 cmp r3, #0
801ac94: d014 beq.n 801acc0 <ethernet_input+0x100>
if (pbuf_remove_header(p, next_hdr_offset)) {
801ac96: 8afb ldrh r3, [r7, #22]
801ac98: 4619 mov r1, r3
801ac9a: 6878 ldr r0, [r7, #4]
801ac9c: f7f5 fc26 bl 80104ec <pbuf_remove_header>
801aca0: 4603 mov r3, r0
801aca2: 2b00 cmp r3, #0
801aca4: d10e bne.n 801acc4 <ethernet_input+0x104>
etharp_input(p, netif);
801aca6: 6839 ldr r1, [r7, #0]
801aca8: 6878 ldr r0, [r7, #4]
801acaa: f7fe f8ab bl 8018e04 <etharp_input>
break;
801acae: bf00 nop
}
/* This means the pbuf is freed or consumed,
so the caller doesn't have to free it again */
return ERR_OK;
801acb0: 2300 movs r3, #0
801acb2: e00c b.n 801acce <ethernet_input+0x10e>
goto free_and_return;
801acb4: bf00 nop
801acb6: e006 b.n 801acc6 <ethernet_input+0x106>
goto free_and_return;
801acb8: bf00 nop
801acba: e004 b.n 801acc6 <ethernet_input+0x106>
goto free_and_return;
801acbc: bf00 nop
801acbe: e002 b.n 801acc6 <ethernet_input+0x106>
goto free_and_return;
801acc0: bf00 nop
801acc2: e000 b.n 801acc6 <ethernet_input+0x106>
goto free_and_return;
801acc4: bf00 nop
free_and_return:
pbuf_free(p);
801acc6: 6878 ldr r0, [r7, #4]
801acc8: f7f5 fc96 bl 80105f8 <pbuf_free>
return ERR_OK;
801accc: 2300 movs r3, #0
}
801acce: 4618 mov r0, r3
801acd0: 3718 adds r7, #24
801acd2: 46bd mov sp, r7
801acd4: bd80 pop {r7, pc}
801acd6: bf00 nop
801acd8: 08020e80 .word 0x08020e80
0801acdc <ethernet_output>:
* @return ERR_OK if the packet was sent, any other err_t on failure
*/
err_t
ethernet_output(struct netif * netif, struct pbuf * p,
const struct eth_addr * src, const struct eth_addr * dst,
u16_t eth_type) {
801acdc: b580 push {r7, lr}
801acde: b086 sub sp, #24
801ace0: af00 add r7, sp, #0
801ace2: 60f8 str r0, [r7, #12]
801ace4: 60b9 str r1, [r7, #8]
801ace6: 607a str r2, [r7, #4]
801ace8: 603b str r3, [r7, #0]
struct eth_hdr *ethhdr;
u16_t eth_type_be = lwip_htons(eth_type);
801acea: 8c3b ldrh r3, [r7, #32]
801acec: 4618 mov r0, r3
801acee: f7f4 f8cf bl 800ee90 <lwip_htons>
801acf2: 4603 mov r3, r0
801acf4: 82fb strh r3, [r7, #22]
eth_type_be = PP_HTONS(ETHTYPE_VLAN);
} else
#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
{
if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
801acf6: 210e movs r1, #14
801acf8: 68b8 ldr r0, [r7, #8]
801acfa: f7f5 fbe7 bl 80104cc <pbuf_add_header>
801acfe: 4603 mov r3, r0
801ad00: 2b00 cmp r3, #0
801ad02: d125 bne.n 801ad50 <ethernet_output+0x74>
}
}
LWIP_ASSERT_CORE_LOCKED();
ethhdr = (struct eth_hdr *)p->payload;
801ad04: 68bb ldr r3, [r7, #8]
801ad06: 685b ldr r3, [r3, #4]
801ad08: 613b str r3, [r7, #16]
ethhdr->type = eth_type_be;
801ad0a: 693b ldr r3, [r7, #16]
801ad0c: 8afa ldrh r2, [r7, #22]
801ad0e: 819a strh r2, [r3, #12]
SMEMCPY(&ethhdr->dest, dst, ETH_HWADDR_LEN);
801ad10: 693b ldr r3, [r7, #16]
801ad12: 2206 movs r2, #6
801ad14: 6839 ldr r1, [r7, #0]
801ad16: 4618 mov r0, r3
801ad18: f000 f971 bl 801affe <memcpy>
SMEMCPY(&ethhdr->src, src, ETH_HWADDR_LEN);
801ad1c: 693b ldr r3, [r7, #16]
801ad1e: 3306 adds r3, #6
801ad20: 2206 movs r2, #6
801ad22: 6879 ldr r1, [r7, #4]
801ad24: 4618 mov r0, r3
801ad26: f000 f96a bl 801affe <memcpy>
LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
801ad2a: 68fb ldr r3, [r7, #12]
801ad2c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
801ad30: 2b06 cmp r3, #6
801ad32: d006 beq.n 801ad42 <ethernet_output+0x66>
801ad34: 4b0a ldr r3, [pc, #40] ; (801ad60 <ethernet_output+0x84>)
801ad36: f240 1233 movw r2, #307 ; 0x133
801ad3a: 490a ldr r1, [pc, #40] ; (801ad64 <ethernet_output+0x88>)
801ad3c: 480a ldr r0, [pc, #40] ; (801ad68 <ethernet_output+0x8c>)
801ad3e: f000 f971 bl 801b024 <iprintf>
(netif->hwaddr_len == ETH_HWADDR_LEN));
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
("ethernet_output: sending packet %p\n", (void *)p));
/* send the packet */
return netif->linkoutput(netif, p);
801ad42: 68fb ldr r3, [r7, #12]
801ad44: 699b ldr r3, [r3, #24]
801ad46: 68b9 ldr r1, [r7, #8]
801ad48: 68f8 ldr r0, [r7, #12]
801ad4a: 4798 blx r3
801ad4c: 4603 mov r3, r0
801ad4e: e002 b.n 801ad56 <ethernet_output+0x7a>
goto pbuf_header_failed;
801ad50: bf00 nop
pbuf_header_failed:
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
("ethernet_output: could not allocate room for header.\n"));
LINK_STATS_INC(link.lenerr);
return ERR_BUF;
801ad52: f06f 0301 mvn.w r3, #1
}
801ad56: 4618 mov r0, r3
801ad58: 3718 adds r7, #24
801ad5a: 46bd mov sp, r7
801ad5c: bd80 pop {r7, pc}
801ad5e: bf00 nop
801ad60: 0801ed78 .word 0x0801ed78
801ad64: 0801edb0 .word 0x0801edb0
801ad68: 0801ede4 .word 0x0801ede4
0801ad6c <sys_mbox_new>:
#endif
/*-----------------------------------------------------------------------------------*/
// Creates an empty mailbox.
err_t sys_mbox_new(sys_mbox_t *mbox, int size)
{
801ad6c: b580 push {r7, lr}
801ad6e: b086 sub sp, #24
801ad70: af00 add r7, sp, #0
801ad72: 6078 str r0, [r7, #4]
801ad74: 6039 str r1, [r7, #0]
#if (osCMSIS < 0x20000U)
osMessageQDef(QUEUE, size, void *);
801ad76: 683b ldr r3, [r7, #0]
801ad78: 60bb str r3, [r7, #8]
801ad7a: 2304 movs r3, #4
801ad7c: 60fb str r3, [r7, #12]
801ad7e: 2300 movs r3, #0
801ad80: 613b str r3, [r7, #16]
801ad82: 2300 movs r3, #0
801ad84: 617b str r3, [r7, #20]
*mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
801ad86: f107 0308 add.w r3, r7, #8
801ad8a: 2100 movs r1, #0
801ad8c: 4618 mov r0, r3
801ad8e: f7f0 fff9 bl 800bd84 <osMessageCreate>
801ad92: 4602 mov r2, r0
801ad94: 687b ldr r3, [r7, #4]
801ad96: 601a str r2, [r3, #0]
if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
{
lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
}
#endif /* SYS_STATS */
if(*mbox == NULL)
801ad98: 687b ldr r3, [r7, #4]
801ad9a: 681b ldr r3, [r3, #0]
801ad9c: 2b00 cmp r3, #0
801ad9e: d102 bne.n 801ada6 <sys_mbox_new+0x3a>
return ERR_MEM;
801ada0: f04f 33ff mov.w r3, #4294967295
801ada4: e000 b.n 801ada8 <sys_mbox_new+0x3c>
return ERR_OK;
801ada6: 2300 movs r3, #0
}
801ada8: 4618 mov r0, r3
801adaa: 3718 adds r7, #24
801adac: 46bd mov sp, r7
801adae: bd80 pop {r7, pc}
0801adb0 <sys_mbox_trypost>:
/*-----------------------------------------------------------------------------------*/
// Try to post the "msg" to the mailbox.
err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
{
801adb0: b580 push {r7, lr}
801adb2: b084 sub sp, #16
801adb4: af00 add r7, sp, #0
801adb6: 6078 str r0, [r7, #4]
801adb8: 6039 str r1, [r7, #0]
err_t result;
#if (osCMSIS < 0x20000U)
if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
801adba: 687b ldr r3, [r7, #4]
801adbc: 681b ldr r3, [r3, #0]
801adbe: 6839 ldr r1, [r7, #0]
801adc0: 2200 movs r2, #0
801adc2: 4618 mov r0, r3
801adc4: f7f1 f808 bl 800bdd8 <osMessagePut>
801adc8: 4603 mov r3, r0
801adca: 2b00 cmp r3, #0
801adcc: d102 bne.n 801add4 <sys_mbox_trypost+0x24>
#else
if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
#endif
{
result = ERR_OK;
801adce: 2300 movs r3, #0
801add0: 73fb strb r3, [r7, #15]
801add2: e001 b.n 801add8 <sys_mbox_trypost+0x28>
}
else
{
// could not post, queue must be full
result = ERR_MEM;
801add4: 23ff movs r3, #255 ; 0xff
801add6: 73fb strb r3, [r7, #15]
#if SYS_STATS
lwip_stats.sys.mbox.err++;
#endif /* SYS_STATS */
}
return result;
801add8: f997 300f ldrsb.w r3, [r7, #15]
}
801addc: 4618 mov r0, r3
801adde: 3710 adds r7, #16
801ade0: 46bd mov sp, r7
801ade2: bd80 pop {r7, pc}
0801ade4 <sys_arch_mbox_fetch>:
Note that a function with a similar name, sys_mbox_fetch(), is
implemented by lwIP.
*/
u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
{
801ade4: b580 push {r7, lr}
801ade6: b08c sub sp, #48 ; 0x30
801ade8: af00 add r7, sp, #0
801adea: 61f8 str r0, [r7, #28]
801adec: 61b9 str r1, [r7, #24]
801adee: 617a str r2, [r7, #20]
#if (osCMSIS < 0x20000U)
osEvent event;
uint32_t starttime = osKernelSysTick();
801adf0: f7f0 fdf7 bl 800b9e2 <osKernelSysTick>
801adf4: 62f8 str r0, [r7, #44] ; 0x2c
#else
osStatus_t status;
uint32_t starttime = osKernelGetTickCount();
#endif
if(timeout != 0)
801adf6: 697b ldr r3, [r7, #20]
801adf8: 2b00 cmp r3, #0
801adfa: d017 beq.n 801ae2c <sys_arch_mbox_fetch+0x48>
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, timeout);
801adfc: 69fb ldr r3, [r7, #28]
801adfe: 6819 ldr r1, [r3, #0]
801ae00: f107 0320 add.w r3, r7, #32
801ae04: 697a ldr r2, [r7, #20]
801ae06: 4618 mov r0, r3
801ae08: f7f1 f826 bl 800be58 <osMessageGet>
if(event.status == osEventMessage)
801ae0c: 6a3b ldr r3, [r7, #32]
801ae0e: 2b10 cmp r3, #16
801ae10: d109 bne.n 801ae26 <sys_arch_mbox_fetch+0x42>
{
*msg = (void *)event.value.v;
801ae12: 6a7b ldr r3, [r7, #36] ; 0x24
801ae14: 461a mov r2, r3
801ae16: 69bb ldr r3, [r7, #24]
801ae18: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801ae1a: f7f0 fde2 bl 800b9e2 <osKernelSysTick>
801ae1e: 4602 mov r2, r0
801ae20: 6afb ldr r3, [r7, #44] ; 0x2c
801ae22: 1ad3 subs r3, r2, r3
801ae24: e019 b.n 801ae5a <sys_arch_mbox_fetch+0x76>
return (osKernelGetTickCount() - starttime);
}
#endif
else
{
return SYS_ARCH_TIMEOUT;
801ae26: f04f 33ff mov.w r3, #4294967295
801ae2a: e016 b.n 801ae5a <sys_arch_mbox_fetch+0x76>
}
}
else
{
#if (osCMSIS < 0x20000U)
event = osMessageGet (*mbox, osWaitForever);
801ae2c: 69fb ldr r3, [r7, #28]
801ae2e: 6819 ldr r1, [r3, #0]
801ae30: 463b mov r3, r7
801ae32: f04f 32ff mov.w r2, #4294967295
801ae36: 4618 mov r0, r3
801ae38: f7f1 f80e bl 800be58 <osMessageGet>
801ae3c: f107 0320 add.w r3, r7, #32
801ae40: 463a mov r2, r7
801ae42: ca07 ldmia r2, {r0, r1, r2}
801ae44: e883 0007 stmia.w r3, {r0, r1, r2}
*msg = (void *)event.value.v;
801ae48: 6a7b ldr r3, [r7, #36] ; 0x24
801ae4a: 461a mov r2, r3
801ae4c: 69bb ldr r3, [r7, #24]
801ae4e: 601a str r2, [r3, #0]
return (osKernelSysTick() - starttime);
801ae50: f7f0 fdc7 bl 800b9e2 <osKernelSysTick>
801ae54: 4602 mov r2, r0
801ae56: 6afb ldr r3, [r7, #44] ; 0x2c
801ae58: 1ad3 subs r3, r2, r3
#else
osMessageQueueGet(*mbox, msg, 0, osWaitForever );
return (osKernelGetTickCount() - starttime);
#endif
}
}
801ae5a: 4618 mov r0, r3
801ae5c: 3730 adds r7, #48 ; 0x30
801ae5e: 46bd mov sp, r7
801ae60: bd80 pop {r7, pc}
0801ae62 <sys_mbox_valid>:
return SYS_MBOX_EMPTY;
}
}
/*----------------------------------------------------------------------------------*/
int sys_mbox_valid(sys_mbox_t *mbox)
{
801ae62: b480 push {r7}
801ae64: b083 sub sp, #12
801ae66: af00 add r7, sp, #0
801ae68: 6078 str r0, [r7, #4]
if (*mbox == SYS_MBOX_NULL)
801ae6a: 687b ldr r3, [r7, #4]
801ae6c: 681b ldr r3, [r3, #0]
801ae6e: 2b00 cmp r3, #0
801ae70: d101 bne.n 801ae76 <sys_mbox_valid+0x14>
return 0;
801ae72: 2300 movs r3, #0
801ae74: e000 b.n 801ae78 <sys_mbox_valid+0x16>
else
return 1;
801ae76: 2301 movs r3, #1
}
801ae78: 4618 mov r0, r3
801ae7a: 370c adds r7, #12
801ae7c: 46bd mov sp, r7
801ae7e: f85d 7b04 ldr.w r7, [sp], #4
801ae82: 4770 bx lr
0801ae84 <sys_init>:
#else
osMutexId_t lwip_sys_mutex;
#endif
// Initialize sys arch
void sys_init(void)
{
801ae84: b580 push {r7, lr}
801ae86: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
801ae88: 4803 ldr r0, [pc, #12] ; (801ae98 <sys_init+0x14>)
801ae8a: f7f0 fe1a bl 800bac2 <osMutexCreate>
801ae8e: 4602 mov r2, r0
801ae90: 4b02 ldr r3, [pc, #8] ; (801ae9c <sys_init+0x18>)
801ae92: 601a str r2, [r3, #0]
#else
lwip_sys_mutex = osMutexNew(NULL);
#endif
}
801ae94: bf00 nop
801ae96: bd80 pop {r7, pc}
801ae98: 08020e90 .word 0x08020e90
801ae9c: 2000f608 .word 0x2000f608
0801aea0 <sys_mutex_new>:
/* Mutexes*/
/*-----------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------*/
#if LWIP_COMPAT_MUTEX == 0
/* Create a new mutex*/
err_t sys_mutex_new(sys_mutex_t *mutex) {
801aea0: b580 push {r7, lr}
801aea2: b084 sub sp, #16
801aea4: af00 add r7, sp, #0
801aea6: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexDef(MUTEX);
801aea8: 2300 movs r3, #0
801aeaa: 60bb str r3, [r7, #8]
801aeac: 2300 movs r3, #0
801aeae: 60fb str r3, [r7, #12]
*mutex = osMutexCreate(osMutex(MUTEX));
801aeb0: f107 0308 add.w r3, r7, #8
801aeb4: 4618 mov r0, r3
801aeb6: f7f0 fe04 bl 800bac2 <osMutexCreate>
801aeba: 4602 mov r2, r0
801aebc: 687b ldr r3, [r7, #4]
801aebe: 601a str r2, [r3, #0]
#else
*mutex = osMutexNew(NULL);
#endif
if(*mutex == NULL)
801aec0: 687b ldr r3, [r7, #4]
801aec2: 681b ldr r3, [r3, #0]
801aec4: 2b00 cmp r3, #0
801aec6: d102 bne.n 801aece <sys_mutex_new+0x2e>
{
#if SYS_STATS
++lwip_stats.sys.mutex.err;
#endif /* SYS_STATS */
return ERR_MEM;
801aec8: f04f 33ff mov.w r3, #4294967295
801aecc: e000 b.n 801aed0 <sys_mutex_new+0x30>
++lwip_stats.sys.mutex.used;
if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
}
#endif /* SYS_STATS */
return ERR_OK;
801aece: 2300 movs r3, #0
}
801aed0: 4618 mov r0, r3
801aed2: 3710 adds r7, #16
801aed4: 46bd mov sp, r7
801aed6: bd80 pop {r7, pc}
0801aed8 <sys_mutex_lock>:
osMutexDelete(*mutex);
}
/*-----------------------------------------------------------------------------------*/
/* Lock a mutex*/
void sys_mutex_lock(sys_mutex_t *mutex)
{
801aed8: b580 push {r7, lr}
801aeda: b082 sub sp, #8
801aedc: af00 add r7, sp, #0
801aede: 6078 str r0, [r7, #4]
#if (osCMSIS < 0x20000U)
osMutexWait(*mutex, osWaitForever);
801aee0: 687b ldr r3, [r7, #4]
801aee2: 681b ldr r3, [r3, #0]
801aee4: f04f 31ff mov.w r1, #4294967295
801aee8: 4618 mov r0, r3
801aeea: f7f0 fe03 bl 800baf4 <osMutexWait>
#else
osMutexAcquire(*mutex, osWaitForever);
#endif
}
801aeee: bf00 nop
801aef0: 3708 adds r7, #8
801aef2: 46bd mov sp, r7
801aef4: bd80 pop {r7, pc}
0801aef6 <sys_mutex_unlock>:
/*-----------------------------------------------------------------------------------*/
/* Unlock a mutex*/
void sys_mutex_unlock(sys_mutex_t *mutex)
{
801aef6: b580 push {r7, lr}
801aef8: b082 sub sp, #8
801aefa: af00 add r7, sp, #0
801aefc: 6078 str r0, [r7, #4]
osMutexRelease(*mutex);
801aefe: 687b ldr r3, [r7, #4]
801af00: 681b ldr r3, [r3, #0]
801af02: 4618 mov r0, r3
801af04: f7f0 fe44 bl 800bb90 <osMutexRelease>
}
801af08: bf00 nop
801af0a: 3708 adds r7, #8
801af0c: 46bd mov sp, r7
801af0e: bd80 pop {r7, pc}
0801af10 <sys_thread_new>:
function "thread()". The "arg" argument will be passed as an argument to the
thread() function. The id of the new thread is returned. Both the id and
the priority are system dependent.
*/
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
{
801af10: b580 push {r7, lr}
801af12: b08c sub sp, #48 ; 0x30
801af14: af00 add r7, sp, #0
801af16: 60f8 str r0, [r7, #12]
801af18: 60b9 str r1, [r7, #8]
801af1a: 607a str r2, [r7, #4]
801af1c: 603b str r3, [r7, #0]
#if (osCMSIS < 0x20000U)
const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
801af1e: f107 0314 add.w r3, r7, #20
801af22: 2200 movs r2, #0
801af24: 601a str r2, [r3, #0]
801af26: 605a str r2, [r3, #4]
801af28: 609a str r2, [r3, #8]
801af2a: 60da str r2, [r3, #12]
801af2c: 611a str r2, [r3, #16]
801af2e: 615a str r2, [r3, #20]
801af30: 619a str r2, [r3, #24]
801af32: 68fb ldr r3, [r7, #12]
801af34: 617b str r3, [r7, #20]
801af36: 68bb ldr r3, [r7, #8]
801af38: 61bb str r3, [r7, #24]
801af3a: 6bbb ldr r3, [r7, #56] ; 0x38
801af3c: b21b sxth r3, r3
801af3e: 83bb strh r3, [r7, #28]
801af40: 683b ldr r3, [r7, #0]
801af42: 627b str r3, [r7, #36] ; 0x24
return osThreadCreate(&os_thread_def, arg);
801af44: f107 0314 add.w r3, r7, #20
801af48: 6879 ldr r1, [r7, #4]
801af4a: 4618 mov r0, r3
801af4c: f7f0 fd59 bl 800ba02 <osThreadCreate>
801af50: 4603 mov r3, r0
.stack_size = stacksize,
.priority = (osPriority_t)prio,
};
return osThreadNew(thread, arg, &attributes);
#endif
}
801af52: 4618 mov r0, r3
801af54: 3730 adds r7, #48 ; 0x30
801af56: 46bd mov sp, r7
801af58: bd80 pop {r7, pc}
...
0801af5c <sys_arch_protect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
sys_prot_t sys_arch_protect(void)
{
801af5c: b580 push {r7, lr}
801af5e: af00 add r7, sp, #0
#if (osCMSIS < 0x20000U)
osMutexWait(lwip_sys_mutex, osWaitForever);
801af60: 4b04 ldr r3, [pc, #16] ; (801af74 <sys_arch_protect+0x18>)
801af62: 681b ldr r3, [r3, #0]
801af64: f04f 31ff mov.w r1, #4294967295
801af68: 4618 mov r0, r3
801af6a: f7f0 fdc3 bl 800baf4 <osMutexWait>
#else
osMutexAcquire(lwip_sys_mutex, osWaitForever);
#endif
return (sys_prot_t)1;
801af6e: 2301 movs r3, #1
}
801af70: 4618 mov r0, r3
801af72: bd80 pop {r7, pc}
801af74: 2000f608 .word 0x2000f608
0801af78 <sys_arch_unprotect>:
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
API is available
*/
void sys_arch_unprotect(sys_prot_t pval)
{
801af78: b580 push {r7, lr}
801af7a: b082 sub sp, #8
801af7c: af00 add r7, sp, #0
801af7e: 6078 str r0, [r7, #4]
( void ) pval;
osMutexRelease(lwip_sys_mutex);
801af80: 4b04 ldr r3, [pc, #16] ; (801af94 <sys_arch_unprotect+0x1c>)
801af82: 681b ldr r3, [r3, #0]
801af84: 4618 mov r0, r3
801af86: f7f0 fe03 bl 800bb90 <osMutexRelease>
}
801af8a: bf00 nop
801af8c: 3708 adds r7, #8
801af8e: 46bd mov sp, r7
801af90: bd80 pop {r7, pc}
801af92: bf00 nop
801af94: 2000f608 .word 0x2000f608
0801af98 <__libc_init_array>:
801af98: b570 push {r4, r5, r6, lr}
801af9a: 4e0d ldr r6, [pc, #52] ; (801afd0 <__libc_init_array+0x38>)
801af9c: 4c0d ldr r4, [pc, #52] ; (801afd4 <__libc_init_array+0x3c>)
801af9e: 1ba4 subs r4, r4, r6
801afa0: 10a4 asrs r4, r4, #2
801afa2: 2500 movs r5, #0
801afa4: 42a5 cmp r5, r4
801afa6: d109 bne.n 801afbc <__libc_init_array+0x24>
801afa8: 4e0b ldr r6, [pc, #44] ; (801afd8 <__libc_init_array+0x40>)
801afaa: 4c0c ldr r4, [pc, #48] ; (801afdc <__libc_init_array+0x44>)
801afac: f000 ff5a bl 801be64 <_init>
801afb0: 1ba4 subs r4, r4, r6
801afb2: 10a4 asrs r4, r4, #2
801afb4: 2500 movs r5, #0
801afb6: 42a5 cmp r5, r4
801afb8: d105 bne.n 801afc6 <__libc_init_array+0x2e>
801afba: bd70 pop {r4, r5, r6, pc}
801afbc: f856 3025 ldr.w r3, [r6, r5, lsl #2]
801afc0: 4798 blx r3
801afc2: 3501 adds r5, #1
801afc4: e7ee b.n 801afa4 <__libc_init_array+0xc>
801afc6: f856 3025 ldr.w r3, [r6, r5, lsl #2]
801afca: 4798 blx r3
801afcc: 3501 adds r5, #1
801afce: e7f2 b.n 801afb6 <__libc_init_array+0x1e>
801afd0: 08020f38 .word 0x08020f38
801afd4: 08020f38 .word 0x08020f38
801afd8: 08020f38 .word 0x08020f38
801afdc: 08020f3c .word 0x08020f3c
0801afe0 <memcmp>:
801afe0: b530 push {r4, r5, lr}
801afe2: 2400 movs r4, #0
801afe4: 42a2 cmp r2, r4
801afe6: d101 bne.n 801afec <memcmp+0xc>
801afe8: 2000 movs r0, #0
801afea: e007 b.n 801affc <memcmp+0x1c>
801afec: 5d03 ldrb r3, [r0, r4]
801afee: 3401 adds r4, #1
801aff0: 190d adds r5, r1, r4
801aff2: f815 5c01 ldrb.w r5, [r5, #-1]
801aff6: 42ab cmp r3, r5
801aff8: d0f4 beq.n 801afe4 <memcmp+0x4>
801affa: 1b58 subs r0, r3, r5
801affc: bd30 pop {r4, r5, pc}
0801affe <memcpy>:
801affe: b510 push {r4, lr}
801b000: 1e43 subs r3, r0, #1
801b002: 440a add r2, r1
801b004: 4291 cmp r1, r2
801b006: d100 bne.n 801b00a <memcpy+0xc>
801b008: bd10 pop {r4, pc}
801b00a: f811 4b01 ldrb.w r4, [r1], #1
801b00e: f803 4f01 strb.w r4, [r3, #1]!
801b012: e7f7 b.n 801b004 <memcpy+0x6>
0801b014 <memset>:
801b014: 4402 add r2, r0
801b016: 4603 mov r3, r0
801b018: 4293 cmp r3, r2
801b01a: d100 bne.n 801b01e <memset+0xa>
801b01c: 4770 bx lr
801b01e: f803 1b01 strb.w r1, [r3], #1
801b022: e7f9 b.n 801b018 <memset+0x4>
0801b024 <iprintf>:
801b024: b40f push {r0, r1, r2, r3}
801b026: 4b0a ldr r3, [pc, #40] ; (801b050 <iprintf+0x2c>)
801b028: b513 push {r0, r1, r4, lr}
801b02a: 681c ldr r4, [r3, #0]
801b02c: b124 cbz r4, 801b038 <iprintf+0x14>
801b02e: 69a3 ldr r3, [r4, #24]
801b030: b913 cbnz r3, 801b038 <iprintf+0x14>
801b032: 4620 mov r0, r4
801b034: f000 f882 bl 801b13c <__sinit>
801b038: ab05 add r3, sp, #20
801b03a: 9a04 ldr r2, [sp, #16]
801b03c: 68a1 ldr r1, [r4, #8]
801b03e: 9301 str r3, [sp, #4]
801b040: 4620 mov r0, r4
801b042: f000 f9df bl 801b404 <_vfiprintf_r>
801b046: b002 add sp, #8
801b048: e8bd 4010 ldmia.w sp!, {r4, lr}
801b04c: b004 add sp, #16
801b04e: 4770 bx lr
801b050: 20000084 .word 0x20000084
0801b054 <rand>:
801b054: b538 push {r3, r4, r5, lr}
801b056: 4b13 ldr r3, [pc, #76] ; (801b0a4 <rand+0x50>)
801b058: 681c ldr r4, [r3, #0]
801b05a: 6ba3 ldr r3, [r4, #56] ; 0x38
801b05c: b97b cbnz r3, 801b07e <rand+0x2a>
801b05e: 2018 movs r0, #24
801b060: f000 f8f6 bl 801b250 <malloc>
801b064: 4a10 ldr r2, [pc, #64] ; (801b0a8 <rand+0x54>)
801b066: 4b11 ldr r3, [pc, #68] ; (801b0ac <rand+0x58>)
801b068: 63a0 str r0, [r4, #56] ; 0x38
801b06a: e9c0 2300 strd r2, r3, [r0]
801b06e: 4b10 ldr r3, [pc, #64] ; (801b0b0 <rand+0x5c>)
801b070: 6083 str r3, [r0, #8]
801b072: 230b movs r3, #11
801b074: 8183 strh r3, [r0, #12]
801b076: 2201 movs r2, #1
801b078: 2300 movs r3, #0
801b07a: e9c0 2304 strd r2, r3, [r0, #16]
801b07e: 6ba1 ldr r1, [r4, #56] ; 0x38
801b080: 480c ldr r0, [pc, #48] ; (801b0b4 <rand+0x60>)
801b082: 690a ldr r2, [r1, #16]
801b084: 694b ldr r3, [r1, #20]
801b086: 4c0c ldr r4, [pc, #48] ; (801b0b8 <rand+0x64>)
801b088: 4350 muls r0, r2
801b08a: fb04 0003 mla r0, r4, r3, r0
801b08e: fba2 2304 umull r2, r3, r2, r4
801b092: 4403 add r3, r0
801b094: 1c54 adds r4, r2, #1
801b096: f143 0500 adc.w r5, r3, #0
801b09a: e9c1 4504 strd r4, r5, [r1, #16]
801b09e: f025 4000 bic.w r0, r5, #2147483648 ; 0x80000000
801b0a2: bd38 pop {r3, r4, r5, pc}
801b0a4: 20000084 .word 0x20000084
801b0a8: abcd330e .word 0xabcd330e
801b0ac: e66d1234 .word 0xe66d1234
801b0b0: 0005deec .word 0x0005deec
801b0b4: 5851f42d .word 0x5851f42d
801b0b8: 4c957f2d .word 0x4c957f2d
0801b0bc <std>:
801b0bc: 2300 movs r3, #0
801b0be: b510 push {r4, lr}
801b0c0: 4604 mov r4, r0
801b0c2: e9c0 3300 strd r3, r3, [r0]
801b0c6: 6083 str r3, [r0, #8]
801b0c8: 8181 strh r1, [r0, #12]
801b0ca: 6643 str r3, [r0, #100] ; 0x64
801b0cc: 81c2 strh r2, [r0, #14]
801b0ce: e9c0 3304 strd r3, r3, [r0, #16]
801b0d2: 6183 str r3, [r0, #24]
801b0d4: 4619 mov r1, r3
801b0d6: 2208 movs r2, #8
801b0d8: 305c adds r0, #92 ; 0x5c
801b0da: f7ff ff9b bl 801b014 <memset>
801b0de: 4b05 ldr r3, [pc, #20] ; (801b0f4 <std+0x38>)
801b0e0: 6263 str r3, [r4, #36] ; 0x24
801b0e2: 4b05 ldr r3, [pc, #20] ; (801b0f8 <std+0x3c>)
801b0e4: 62a3 str r3, [r4, #40] ; 0x28
801b0e6: 4b05 ldr r3, [pc, #20] ; (801b0fc <std+0x40>)
801b0e8: 62e3 str r3, [r4, #44] ; 0x2c
801b0ea: 4b05 ldr r3, [pc, #20] ; (801b100 <std+0x44>)
801b0ec: 6224 str r4, [r4, #32]
801b0ee: 6323 str r3, [r4, #48] ; 0x30
801b0f0: bd10 pop {r4, pc}
801b0f2: bf00 nop
801b0f4: 0801b961 .word 0x0801b961
801b0f8: 0801b983 .word 0x0801b983
801b0fc: 0801b9bb .word 0x0801b9bb
801b100: 0801b9df .word 0x0801b9df
0801b104 <_cleanup_r>:
801b104: 4901 ldr r1, [pc, #4] ; (801b10c <_cleanup_r+0x8>)
801b106: f000 b885 b.w 801b214 <_fwalk_reent>
801b10a: bf00 nop
801b10c: 0801bcb9 .word 0x0801bcb9
0801b110 <__sfmoreglue>:
801b110: b570 push {r4, r5, r6, lr}
801b112: 1e4a subs r2, r1, #1
801b114: 2568 movs r5, #104 ; 0x68
801b116: 4355 muls r5, r2
801b118: 460e mov r6, r1
801b11a: f105 0174 add.w r1, r5, #116 ; 0x74
801b11e: f000 f8ed bl 801b2fc <_malloc_r>
801b122: 4604 mov r4, r0
801b124: b140 cbz r0, 801b138 <__sfmoreglue+0x28>
801b126: 2100 movs r1, #0
801b128: e9c0 1600 strd r1, r6, [r0]
801b12c: 300c adds r0, #12
801b12e: 60a0 str r0, [r4, #8]
801b130: f105 0268 add.w r2, r5, #104 ; 0x68
801b134: f7ff ff6e bl 801b014 <memset>
801b138: 4620 mov r0, r4
801b13a: bd70 pop {r4, r5, r6, pc}
0801b13c <__sinit>:
801b13c: 6983 ldr r3, [r0, #24]
801b13e: b510 push {r4, lr}
801b140: 4604 mov r4, r0
801b142: bb33 cbnz r3, 801b192 <__sinit+0x56>
801b144: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48
801b148: 6503 str r3, [r0, #80] ; 0x50
801b14a: 4b12 ldr r3, [pc, #72] ; (801b194 <__sinit+0x58>)
801b14c: 4a12 ldr r2, [pc, #72] ; (801b198 <__sinit+0x5c>)
801b14e: 681b ldr r3, [r3, #0]
801b150: 6282 str r2, [r0, #40] ; 0x28
801b152: 4298 cmp r0, r3
801b154: bf04 itt eq
801b156: 2301 moveq r3, #1
801b158: 6183 streq r3, [r0, #24]
801b15a: f000 f81f bl 801b19c <__sfp>
801b15e: 6060 str r0, [r4, #4]
801b160: 4620 mov r0, r4
801b162: f000 f81b bl 801b19c <__sfp>
801b166: 60a0 str r0, [r4, #8]
801b168: 4620 mov r0, r4
801b16a: f000 f817 bl 801b19c <__sfp>
801b16e: 2200 movs r2, #0
801b170: 60e0 str r0, [r4, #12]
801b172: 2104 movs r1, #4
801b174: 6860 ldr r0, [r4, #4]
801b176: f7ff ffa1 bl 801b0bc <std>
801b17a: 2201 movs r2, #1
801b17c: 2109 movs r1, #9
801b17e: 68a0 ldr r0, [r4, #8]
801b180: f7ff ff9c bl 801b0bc <std>
801b184: 2202 movs r2, #2
801b186: 2112 movs r1, #18
801b188: 68e0 ldr r0, [r4, #12]
801b18a: f7ff ff97 bl 801b0bc <std>
801b18e: 2301 movs r3, #1
801b190: 61a3 str r3, [r4, #24]
801b192: bd10 pop {r4, pc}
801b194: 08020e98 .word 0x08020e98
801b198: 0801b105 .word 0x0801b105
0801b19c <__sfp>:
801b19c: b5f8 push {r3, r4, r5, r6, r7, lr}
801b19e: 4b1b ldr r3, [pc, #108] ; (801b20c <__sfp+0x70>)
801b1a0: 681e ldr r6, [r3, #0]
801b1a2: 69b3 ldr r3, [r6, #24]
801b1a4: 4607 mov r7, r0
801b1a6: b913 cbnz r3, 801b1ae <__sfp+0x12>
801b1a8: 4630 mov r0, r6
801b1aa: f7ff ffc7 bl 801b13c <__sinit>
801b1ae: 3648 adds r6, #72 ; 0x48
801b1b0: e9d6 3401 ldrd r3, r4, [r6, #4]
801b1b4: 3b01 subs r3, #1
801b1b6: d503 bpl.n 801b1c0 <__sfp+0x24>
801b1b8: 6833 ldr r3, [r6, #0]
801b1ba: b133 cbz r3, 801b1ca <__sfp+0x2e>
801b1bc: 6836 ldr r6, [r6, #0]
801b1be: e7f7 b.n 801b1b0 <__sfp+0x14>
801b1c0: f9b4 500c ldrsh.w r5, [r4, #12]
801b1c4: b16d cbz r5, 801b1e2 <__sfp+0x46>
801b1c6: 3468 adds r4, #104 ; 0x68
801b1c8: e7f4 b.n 801b1b4 <__sfp+0x18>
801b1ca: 2104 movs r1, #4
801b1cc: 4638 mov r0, r7
801b1ce: f7ff ff9f bl 801b110 <__sfmoreglue>
801b1d2: 6030 str r0, [r6, #0]
801b1d4: 2800 cmp r0, #0
801b1d6: d1f1 bne.n 801b1bc <__sfp+0x20>
801b1d8: 230c movs r3, #12
801b1da: 603b str r3, [r7, #0]
801b1dc: 4604 mov r4, r0
801b1de: 4620 mov r0, r4
801b1e0: bdf8 pop {r3, r4, r5, r6, r7, pc}
801b1e2: 4b0b ldr r3, [pc, #44] ; (801b210 <__sfp+0x74>)
801b1e4: 6665 str r5, [r4, #100] ; 0x64
801b1e6: e9c4 5500 strd r5, r5, [r4]
801b1ea: 60a5 str r5, [r4, #8]
801b1ec: e9c4 3503 strd r3, r5, [r4, #12]
801b1f0: e9c4 5505 strd r5, r5, [r4, #20]
801b1f4: 2208 movs r2, #8
801b1f6: 4629 mov r1, r5
801b1f8: f104 005c add.w r0, r4, #92 ; 0x5c
801b1fc: f7ff ff0a bl 801b014 <memset>
801b200: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
801b204: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
801b208: e7e9 b.n 801b1de <__sfp+0x42>
801b20a: bf00 nop
801b20c: 08020e98 .word 0x08020e98
801b210: ffff0001 .word 0xffff0001
0801b214 <_fwalk_reent>:
801b214: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
801b218: 4680 mov r8, r0
801b21a: 4689 mov r9, r1
801b21c: f100 0448 add.w r4, r0, #72 ; 0x48
801b220: 2600 movs r6, #0
801b222: b914 cbnz r4, 801b22a <_fwalk_reent+0x16>
801b224: 4630 mov r0, r6
801b226: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
801b22a: e9d4 7501 ldrd r7, r5, [r4, #4]
801b22e: 3f01 subs r7, #1
801b230: d501 bpl.n 801b236 <_fwalk_reent+0x22>
801b232: 6824 ldr r4, [r4, #0]
801b234: e7f5 b.n 801b222 <_fwalk_reent+0xe>
801b236: 89ab ldrh r3, [r5, #12]
801b238: 2b01 cmp r3, #1
801b23a: d907 bls.n 801b24c <_fwalk_reent+0x38>
801b23c: f9b5 300e ldrsh.w r3, [r5, #14]
801b240: 3301 adds r3, #1
801b242: d003 beq.n 801b24c <_fwalk_reent+0x38>
801b244: 4629 mov r1, r5
801b246: 4640 mov r0, r8
801b248: 47c8 blx r9
801b24a: 4306 orrs r6, r0
801b24c: 3568 adds r5, #104 ; 0x68
801b24e: e7ee b.n 801b22e <_fwalk_reent+0x1a>
0801b250 <malloc>:
801b250: 4b02 ldr r3, [pc, #8] ; (801b25c <malloc+0xc>)
801b252: 4601 mov r1, r0
801b254: 6818 ldr r0, [r3, #0]
801b256: f000 b851 b.w 801b2fc <_malloc_r>
801b25a: bf00 nop
801b25c: 20000084 .word 0x20000084
0801b260 <_free_r>:
801b260: b538 push {r3, r4, r5, lr}
801b262: 4605 mov r5, r0
801b264: 2900 cmp r1, #0
801b266: d045 beq.n 801b2f4 <_free_r+0x94>
801b268: f851 3c04 ldr.w r3, [r1, #-4]
801b26c: 1f0c subs r4, r1, #4
801b26e: 2b00 cmp r3, #0
801b270: bfb8 it lt
801b272: 18e4 addlt r4, r4, r3
801b274: f000 fdc0 bl 801bdf8 <__malloc_lock>
801b278: 4a1f ldr r2, [pc, #124] ; (801b2f8 <_free_r+0x98>)
801b27a: 6813 ldr r3, [r2, #0]
801b27c: 4610 mov r0, r2
801b27e: b933 cbnz r3, 801b28e <_free_r+0x2e>
801b280: 6063 str r3, [r4, #4]
801b282: 6014 str r4, [r2, #0]
801b284: 4628 mov r0, r5
801b286: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801b28a: f000 bdb6 b.w 801bdfa <__malloc_unlock>
801b28e: 42a3 cmp r3, r4
801b290: d90c bls.n 801b2ac <_free_r+0x4c>
801b292: 6821 ldr r1, [r4, #0]
801b294: 1862 adds r2, r4, r1
801b296: 4293 cmp r3, r2
801b298: bf04 itt eq
801b29a: 681a ldreq r2, [r3, #0]
801b29c: 685b ldreq r3, [r3, #4]
801b29e: 6063 str r3, [r4, #4]
801b2a0: bf04 itt eq
801b2a2: 1852 addeq r2, r2, r1
801b2a4: 6022 streq r2, [r4, #0]
801b2a6: 6004 str r4, [r0, #0]
801b2a8: e7ec b.n 801b284 <_free_r+0x24>
801b2aa: 4613 mov r3, r2
801b2ac: 685a ldr r2, [r3, #4]
801b2ae: b10a cbz r2, 801b2b4 <_free_r+0x54>
801b2b0: 42a2 cmp r2, r4
801b2b2: d9fa bls.n 801b2aa <_free_r+0x4a>
801b2b4: 6819 ldr r1, [r3, #0]
801b2b6: 1858 adds r0, r3, r1
801b2b8: 42a0 cmp r0, r4
801b2ba: d10b bne.n 801b2d4 <_free_r+0x74>
801b2bc: 6820 ldr r0, [r4, #0]
801b2be: 4401 add r1, r0
801b2c0: 1858 adds r0, r3, r1
801b2c2: 4282 cmp r2, r0
801b2c4: 6019 str r1, [r3, #0]
801b2c6: d1dd bne.n 801b284 <_free_r+0x24>
801b2c8: 6810 ldr r0, [r2, #0]
801b2ca: 6852 ldr r2, [r2, #4]
801b2cc: 605a str r2, [r3, #4]
801b2ce: 4401 add r1, r0
801b2d0: 6019 str r1, [r3, #0]
801b2d2: e7d7 b.n 801b284 <_free_r+0x24>
801b2d4: d902 bls.n 801b2dc <_free_r+0x7c>
801b2d6: 230c movs r3, #12
801b2d8: 602b str r3, [r5, #0]
801b2da: e7d3 b.n 801b284 <_free_r+0x24>
801b2dc: 6820 ldr r0, [r4, #0]
801b2de: 1821 adds r1, r4, r0
801b2e0: 428a cmp r2, r1
801b2e2: bf04 itt eq
801b2e4: 6811 ldreq r1, [r2, #0]
801b2e6: 6852 ldreq r2, [r2, #4]
801b2e8: 6062 str r2, [r4, #4]
801b2ea: bf04 itt eq
801b2ec: 1809 addeq r1, r1, r0
801b2ee: 6021 streq r1, [r4, #0]
801b2f0: 605c str r4, [r3, #4]
801b2f2: e7c7 b.n 801b284 <_free_r+0x24>
801b2f4: bd38 pop {r3, r4, r5, pc}
801b2f6: bf00 nop
801b2f8: 20008874 .word 0x20008874
0801b2fc <_malloc_r>:
801b2fc: b570 push {r4, r5, r6, lr}
801b2fe: 1ccd adds r5, r1, #3
801b300: f025 0503 bic.w r5, r5, #3
801b304: 3508 adds r5, #8
801b306: 2d0c cmp r5, #12
801b308: bf38 it cc
801b30a: 250c movcc r5, #12
801b30c: 2d00 cmp r5, #0
801b30e: 4606 mov r6, r0
801b310: db01 blt.n 801b316 <_malloc_r+0x1a>
801b312: 42a9 cmp r1, r5
801b314: d903 bls.n 801b31e <_malloc_r+0x22>
801b316: 230c movs r3, #12
801b318: 6033 str r3, [r6, #0]
801b31a: 2000 movs r0, #0
801b31c: bd70 pop {r4, r5, r6, pc}
801b31e: f000 fd6b bl 801bdf8 <__malloc_lock>
801b322: 4a21 ldr r2, [pc, #132] ; (801b3a8 <_malloc_r+0xac>)
801b324: 6814 ldr r4, [r2, #0]
801b326: 4621 mov r1, r4
801b328: b991 cbnz r1, 801b350 <_malloc_r+0x54>
801b32a: 4c20 ldr r4, [pc, #128] ; (801b3ac <_malloc_r+0xb0>)
801b32c: 6823 ldr r3, [r4, #0]
801b32e: b91b cbnz r3, 801b338 <_malloc_r+0x3c>
801b330: 4630 mov r0, r6
801b332: f000 fb05 bl 801b940 <_sbrk_r>
801b336: 6020 str r0, [r4, #0]
801b338: 4629 mov r1, r5
801b33a: 4630 mov r0, r6
801b33c: f000 fb00 bl 801b940 <_sbrk_r>
801b340: 1c43 adds r3, r0, #1
801b342: d124 bne.n 801b38e <_malloc_r+0x92>
801b344: 230c movs r3, #12
801b346: 6033 str r3, [r6, #0]
801b348: 4630 mov r0, r6
801b34a: f000 fd56 bl 801bdfa <__malloc_unlock>
801b34e: e7e4 b.n 801b31a <_malloc_r+0x1e>
801b350: 680b ldr r3, [r1, #0]
801b352: 1b5b subs r3, r3, r5
801b354: d418 bmi.n 801b388 <_malloc_r+0x8c>
801b356: 2b0b cmp r3, #11
801b358: d90f bls.n 801b37a <_malloc_r+0x7e>
801b35a: 600b str r3, [r1, #0]
801b35c: 50cd str r5, [r1, r3]
801b35e: 18cc adds r4, r1, r3
801b360: 4630 mov r0, r6
801b362: f000 fd4a bl 801bdfa <__malloc_unlock>
801b366: f104 000b add.w r0, r4, #11
801b36a: 1d23 adds r3, r4, #4
801b36c: f020 0007 bic.w r0, r0, #7
801b370: 1ac3 subs r3, r0, r3
801b372: d0d3 beq.n 801b31c <_malloc_r+0x20>
801b374: 425a negs r2, r3
801b376: 50e2 str r2, [r4, r3]
801b378: e7d0 b.n 801b31c <_malloc_r+0x20>
801b37a: 428c cmp r4, r1
801b37c: 684b ldr r3, [r1, #4]
801b37e: bf16 itet ne
801b380: 6063 strne r3, [r4, #4]
801b382: 6013 streq r3, [r2, #0]
801b384: 460c movne r4, r1
801b386: e7eb b.n 801b360 <_malloc_r+0x64>
801b388: 460c mov r4, r1
801b38a: 6849 ldr r1, [r1, #4]
801b38c: e7cc b.n 801b328 <_malloc_r+0x2c>
801b38e: 1cc4 adds r4, r0, #3
801b390: f024 0403 bic.w r4, r4, #3
801b394: 42a0 cmp r0, r4
801b396: d005 beq.n 801b3a4 <_malloc_r+0xa8>
801b398: 1a21 subs r1, r4, r0
801b39a: 4630 mov r0, r6
801b39c: f000 fad0 bl 801b940 <_sbrk_r>
801b3a0: 3001 adds r0, #1
801b3a2: d0cf beq.n 801b344 <_malloc_r+0x48>
801b3a4: 6025 str r5, [r4, #0]
801b3a6: e7db b.n 801b360 <_malloc_r+0x64>
801b3a8: 20008874 .word 0x20008874
801b3ac: 20008878 .word 0x20008878
0801b3b0 <__sfputc_r>:
801b3b0: 6893 ldr r3, [r2, #8]
801b3b2: 3b01 subs r3, #1
801b3b4: 2b00 cmp r3, #0
801b3b6: b410 push {r4}
801b3b8: 6093 str r3, [r2, #8]
801b3ba: da08 bge.n 801b3ce <__sfputc_r+0x1e>
801b3bc: 6994 ldr r4, [r2, #24]
801b3be: 42a3 cmp r3, r4
801b3c0: db01 blt.n 801b3c6 <__sfputc_r+0x16>
801b3c2: 290a cmp r1, #10
801b3c4: d103 bne.n 801b3ce <__sfputc_r+0x1e>
801b3c6: f85d 4b04 ldr.w r4, [sp], #4
801b3ca: f000 bb0d b.w 801b9e8 <__swbuf_r>
801b3ce: 6813 ldr r3, [r2, #0]
801b3d0: 1c58 adds r0, r3, #1
801b3d2: 6010 str r0, [r2, #0]
801b3d4: 7019 strb r1, [r3, #0]
801b3d6: 4608 mov r0, r1
801b3d8: f85d 4b04 ldr.w r4, [sp], #4
801b3dc: 4770 bx lr
0801b3de <__sfputs_r>:
801b3de: b5f8 push {r3, r4, r5, r6, r7, lr}
801b3e0: 4606 mov r6, r0
801b3e2: 460f mov r7, r1
801b3e4: 4614 mov r4, r2
801b3e6: 18d5 adds r5, r2, r3
801b3e8: 42ac cmp r4, r5
801b3ea: d101 bne.n 801b3f0 <__sfputs_r+0x12>
801b3ec: 2000 movs r0, #0
801b3ee: e007 b.n 801b400 <__sfputs_r+0x22>
801b3f0: 463a mov r2, r7
801b3f2: f814 1b01 ldrb.w r1, [r4], #1
801b3f6: 4630 mov r0, r6
801b3f8: f7ff ffda bl 801b3b0 <__sfputc_r>
801b3fc: 1c43 adds r3, r0, #1
801b3fe: d1f3 bne.n 801b3e8 <__sfputs_r+0xa>
801b400: bdf8 pop {r3, r4, r5, r6, r7, pc}
...
0801b404 <_vfiprintf_r>:
801b404: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
801b408: 460c mov r4, r1
801b40a: b09d sub sp, #116 ; 0x74
801b40c: 4617 mov r7, r2
801b40e: 461d mov r5, r3
801b410: 4606 mov r6, r0
801b412: b118 cbz r0, 801b41c <_vfiprintf_r+0x18>
801b414: 6983 ldr r3, [r0, #24]
801b416: b90b cbnz r3, 801b41c <_vfiprintf_r+0x18>
801b418: f7ff fe90 bl 801b13c <__sinit>
801b41c: 4b7c ldr r3, [pc, #496] ; (801b610 <_vfiprintf_r+0x20c>)
801b41e: 429c cmp r4, r3
801b420: d158 bne.n 801b4d4 <_vfiprintf_r+0xd0>
801b422: 6874 ldr r4, [r6, #4]
801b424: 89a3 ldrh r3, [r4, #12]
801b426: 0718 lsls r0, r3, #28
801b428: d55e bpl.n 801b4e8 <_vfiprintf_r+0xe4>
801b42a: 6923 ldr r3, [r4, #16]
801b42c: 2b00 cmp r3, #0
801b42e: d05b beq.n 801b4e8 <_vfiprintf_r+0xe4>
801b430: 2300 movs r3, #0
801b432: 9309 str r3, [sp, #36] ; 0x24
801b434: 2320 movs r3, #32
801b436: f88d 3029 strb.w r3, [sp, #41] ; 0x29
801b43a: 2330 movs r3, #48 ; 0x30
801b43c: f88d 302a strb.w r3, [sp, #42] ; 0x2a
801b440: 9503 str r5, [sp, #12]
801b442: f04f 0b01 mov.w fp, #1
801b446: 46b8 mov r8, r7
801b448: 4645 mov r5, r8
801b44a: f815 3b01 ldrb.w r3, [r5], #1
801b44e: b10b cbz r3, 801b454 <_vfiprintf_r+0x50>
801b450: 2b25 cmp r3, #37 ; 0x25
801b452: d154 bne.n 801b4fe <_vfiprintf_r+0xfa>
801b454: ebb8 0a07 subs.w sl, r8, r7
801b458: d00b beq.n 801b472 <_vfiprintf_r+0x6e>
801b45a: 4653 mov r3, sl
801b45c: 463a mov r2, r7
801b45e: 4621 mov r1, r4
801b460: 4630 mov r0, r6
801b462: f7ff ffbc bl 801b3de <__sfputs_r>
801b466: 3001 adds r0, #1
801b468: f000 80c2 beq.w 801b5f0 <_vfiprintf_r+0x1ec>
801b46c: 9b09 ldr r3, [sp, #36] ; 0x24
801b46e: 4453 add r3, sl
801b470: 9309 str r3, [sp, #36] ; 0x24
801b472: f898 3000 ldrb.w r3, [r8]
801b476: 2b00 cmp r3, #0
801b478: f000 80ba beq.w 801b5f0 <_vfiprintf_r+0x1ec>
801b47c: 2300 movs r3, #0
801b47e: f04f 32ff mov.w r2, #4294967295
801b482: e9cd 2305 strd r2, r3, [sp, #20]
801b486: 9304 str r3, [sp, #16]
801b488: 9307 str r3, [sp, #28]
801b48a: f88d 3053 strb.w r3, [sp, #83] ; 0x53
801b48e: 931a str r3, [sp, #104] ; 0x68
801b490: 46a8 mov r8, r5
801b492: 2205 movs r2, #5
801b494: f818 1b01 ldrb.w r1, [r8], #1
801b498: 485e ldr r0, [pc, #376] ; (801b614 <_vfiprintf_r+0x210>)
801b49a: f7e4 feb9 bl 8000210 <memchr>
801b49e: 9b04 ldr r3, [sp, #16]
801b4a0: bb78 cbnz r0, 801b502 <_vfiprintf_r+0xfe>
801b4a2: 06d9 lsls r1, r3, #27
801b4a4: bf44 itt mi
801b4a6: 2220 movmi r2, #32
801b4a8: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
801b4ac: 071a lsls r2, r3, #28
801b4ae: bf44 itt mi
801b4b0: 222b movmi r2, #43 ; 0x2b
801b4b2: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
801b4b6: 782a ldrb r2, [r5, #0]
801b4b8: 2a2a cmp r2, #42 ; 0x2a
801b4ba: d02a beq.n 801b512 <_vfiprintf_r+0x10e>
801b4bc: 9a07 ldr r2, [sp, #28]
801b4be: 46a8 mov r8, r5
801b4c0: 2000 movs r0, #0
801b4c2: 250a movs r5, #10
801b4c4: 4641 mov r1, r8
801b4c6: f811 3b01 ldrb.w r3, [r1], #1
801b4ca: 3b30 subs r3, #48 ; 0x30
801b4cc: 2b09 cmp r3, #9
801b4ce: d969 bls.n 801b5a4 <_vfiprintf_r+0x1a0>
801b4d0: b360 cbz r0, 801b52c <_vfiprintf_r+0x128>
801b4d2: e024 b.n 801b51e <_vfiprintf_r+0x11a>
801b4d4: 4b50 ldr r3, [pc, #320] ; (801b618 <_vfiprintf_r+0x214>)
801b4d6: 429c cmp r4, r3
801b4d8: d101 bne.n 801b4de <_vfiprintf_r+0xda>
801b4da: 68b4 ldr r4, [r6, #8]
801b4dc: e7a2 b.n 801b424 <_vfiprintf_r+0x20>
801b4de: 4b4f ldr r3, [pc, #316] ; (801b61c <_vfiprintf_r+0x218>)
801b4e0: 429c cmp r4, r3
801b4e2: bf08 it eq
801b4e4: 68f4 ldreq r4, [r6, #12]
801b4e6: e79d b.n 801b424 <_vfiprintf_r+0x20>
801b4e8: 4621 mov r1, r4
801b4ea: 4630 mov r0, r6
801b4ec: f000 fae0 bl 801bab0 <__swsetup_r>
801b4f0: 2800 cmp r0, #0
801b4f2: d09d beq.n 801b430 <_vfiprintf_r+0x2c>
801b4f4: f04f 30ff mov.w r0, #4294967295
801b4f8: b01d add sp, #116 ; 0x74
801b4fa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
801b4fe: 46a8 mov r8, r5
801b500: e7a2 b.n 801b448 <_vfiprintf_r+0x44>
801b502: 4a44 ldr r2, [pc, #272] ; (801b614 <_vfiprintf_r+0x210>)
801b504: 1a80 subs r0, r0, r2
801b506: fa0b f000 lsl.w r0, fp, r0
801b50a: 4318 orrs r0, r3
801b50c: 9004 str r0, [sp, #16]
801b50e: 4645 mov r5, r8
801b510: e7be b.n 801b490 <_vfiprintf_r+0x8c>
801b512: 9a03 ldr r2, [sp, #12]
801b514: 1d11 adds r1, r2, #4
801b516: 6812 ldr r2, [r2, #0]
801b518: 9103 str r1, [sp, #12]
801b51a: 2a00 cmp r2, #0
801b51c: db01 blt.n 801b522 <_vfiprintf_r+0x11e>
801b51e: 9207 str r2, [sp, #28]
801b520: e004 b.n 801b52c <_vfiprintf_r+0x128>
801b522: 4252 negs r2, r2
801b524: f043 0302 orr.w r3, r3, #2
801b528: 9207 str r2, [sp, #28]
801b52a: 9304 str r3, [sp, #16]
801b52c: f898 3000 ldrb.w r3, [r8]
801b530: 2b2e cmp r3, #46 ; 0x2e
801b532: d10e bne.n 801b552 <_vfiprintf_r+0x14e>
801b534: f898 3001 ldrb.w r3, [r8, #1]
801b538: 2b2a cmp r3, #42 ; 0x2a
801b53a: d138 bne.n 801b5ae <_vfiprintf_r+0x1aa>
801b53c: 9b03 ldr r3, [sp, #12]
801b53e: 1d1a adds r2, r3, #4
801b540: 681b ldr r3, [r3, #0]
801b542: 9203 str r2, [sp, #12]
801b544: 2b00 cmp r3, #0
801b546: bfb8 it lt
801b548: f04f 33ff movlt.w r3, #4294967295
801b54c: f108 0802 add.w r8, r8, #2
801b550: 9305 str r3, [sp, #20]
801b552: 4d33 ldr r5, [pc, #204] ; (801b620 <_vfiprintf_r+0x21c>)
801b554: f898 1000 ldrb.w r1, [r8]
801b558: 2203 movs r2, #3
801b55a: 4628 mov r0, r5
801b55c: f7e4 fe58 bl 8000210 <memchr>
801b560: b140 cbz r0, 801b574 <_vfiprintf_r+0x170>
801b562: 2340 movs r3, #64 ; 0x40
801b564: 1b40 subs r0, r0, r5
801b566: fa03 f000 lsl.w r0, r3, r0
801b56a: 9b04 ldr r3, [sp, #16]
801b56c: 4303 orrs r3, r0
801b56e: f108 0801 add.w r8, r8, #1
801b572: 9304 str r3, [sp, #16]
801b574: f898 1000 ldrb.w r1, [r8]
801b578: 482a ldr r0, [pc, #168] ; (801b624 <_vfiprintf_r+0x220>)
801b57a: f88d 1028 strb.w r1, [sp, #40] ; 0x28
801b57e: 2206 movs r2, #6
801b580: f108 0701 add.w r7, r8, #1
801b584: f7e4 fe44 bl 8000210 <memchr>
801b588: 2800 cmp r0, #0
801b58a: d037 beq.n 801b5fc <_vfiprintf_r+0x1f8>
801b58c: 4b26 ldr r3, [pc, #152] ; (801b628 <_vfiprintf_r+0x224>)
801b58e: bb1b cbnz r3, 801b5d8 <_vfiprintf_r+0x1d4>
801b590: 9b03 ldr r3, [sp, #12]
801b592: 3307 adds r3, #7
801b594: f023 0307 bic.w r3, r3, #7
801b598: 3308 adds r3, #8
801b59a: 9303 str r3, [sp, #12]
801b59c: 9b09 ldr r3, [sp, #36] ; 0x24
801b59e: 444b add r3, r9
801b5a0: 9309 str r3, [sp, #36] ; 0x24
801b5a2: e750 b.n 801b446 <_vfiprintf_r+0x42>
801b5a4: fb05 3202 mla r2, r5, r2, r3
801b5a8: 2001 movs r0, #1
801b5aa: 4688 mov r8, r1
801b5ac: e78a b.n 801b4c4 <_vfiprintf_r+0xc0>
801b5ae: 2300 movs r3, #0
801b5b0: f108 0801 add.w r8, r8, #1
801b5b4: 9305 str r3, [sp, #20]
801b5b6: 4619 mov r1, r3
801b5b8: 250a movs r5, #10
801b5ba: 4640 mov r0, r8
801b5bc: f810 2b01 ldrb.w r2, [r0], #1
801b5c0: 3a30 subs r2, #48 ; 0x30
801b5c2: 2a09 cmp r2, #9
801b5c4: d903 bls.n 801b5ce <_vfiprintf_r+0x1ca>
801b5c6: 2b00 cmp r3, #0
801b5c8: d0c3 beq.n 801b552 <_vfiprintf_r+0x14e>
801b5ca: 9105 str r1, [sp, #20]
801b5cc: e7c1 b.n 801b552 <_vfiprintf_r+0x14e>
801b5ce: fb05 2101 mla r1, r5, r1, r2
801b5d2: 2301 movs r3, #1
801b5d4: 4680 mov r8, r0
801b5d6: e7f0 b.n 801b5ba <_vfiprintf_r+0x1b6>
801b5d8: ab03 add r3, sp, #12
801b5da: 9300 str r3, [sp, #0]
801b5dc: 4622 mov r2, r4
801b5de: 4b13 ldr r3, [pc, #76] ; (801b62c <_vfiprintf_r+0x228>)
801b5e0: a904 add r1, sp, #16
801b5e2: 4630 mov r0, r6
801b5e4: f3af 8000 nop.w
801b5e8: f1b0 3fff cmp.w r0, #4294967295
801b5ec: 4681 mov r9, r0
801b5ee: d1d5 bne.n 801b59c <_vfiprintf_r+0x198>
801b5f0: 89a3 ldrh r3, [r4, #12]
801b5f2: 065b lsls r3, r3, #25
801b5f4: f53f af7e bmi.w 801b4f4 <_vfiprintf_r+0xf0>
801b5f8: 9809 ldr r0, [sp, #36] ; 0x24
801b5fa: e77d b.n 801b4f8 <_vfiprintf_r+0xf4>
801b5fc: ab03 add r3, sp, #12
801b5fe: 9300 str r3, [sp, #0]
801b600: 4622 mov r2, r4
801b602: 4b0a ldr r3, [pc, #40] ; (801b62c <_vfiprintf_r+0x228>)
801b604: a904 add r1, sp, #16
801b606: 4630 mov r0, r6
801b608: f000 f888 bl 801b71c <_printf_i>
801b60c: e7ec b.n 801b5e8 <_vfiprintf_r+0x1e4>
801b60e: bf00 nop
801b610: 08020ebc .word 0x08020ebc
801b614: 08020efc .word 0x08020efc
801b618: 08020edc .word 0x08020edc
801b61c: 08020e9c .word 0x08020e9c
801b620: 08020f02 .word 0x08020f02
801b624: 08020f06 .word 0x08020f06
801b628: 00000000 .word 0x00000000
801b62c: 0801b3df .word 0x0801b3df
0801b630 <_printf_common>:
801b630: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
801b634: 4691 mov r9, r2
801b636: 461f mov r7, r3
801b638: 688a ldr r2, [r1, #8]
801b63a: 690b ldr r3, [r1, #16]
801b63c: f8dd 8020 ldr.w r8, [sp, #32]
801b640: 4293 cmp r3, r2
801b642: bfb8 it lt
801b644: 4613 movlt r3, r2
801b646: f8c9 3000 str.w r3, [r9]
801b64a: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
801b64e: 4606 mov r6, r0
801b650: 460c mov r4, r1
801b652: b112 cbz r2, 801b65a <_printf_common+0x2a>
801b654: 3301 adds r3, #1
801b656: f8c9 3000 str.w r3, [r9]
801b65a: 6823 ldr r3, [r4, #0]
801b65c: 0699 lsls r1, r3, #26
801b65e: bf42 ittt mi
801b660: f8d9 3000 ldrmi.w r3, [r9]
801b664: 3302 addmi r3, #2
801b666: f8c9 3000 strmi.w r3, [r9]
801b66a: 6825 ldr r5, [r4, #0]
801b66c: f015 0506 ands.w r5, r5, #6
801b670: d107 bne.n 801b682 <_printf_common+0x52>
801b672: f104 0a19 add.w sl, r4, #25
801b676: 68e3 ldr r3, [r4, #12]
801b678: f8d9 2000 ldr.w r2, [r9]
801b67c: 1a9b subs r3, r3, r2
801b67e: 42ab cmp r3, r5
801b680: dc28 bgt.n 801b6d4 <_printf_common+0xa4>
801b682: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
801b686: 6822 ldr r2, [r4, #0]
801b688: 3300 adds r3, #0
801b68a: bf18 it ne
801b68c: 2301 movne r3, #1
801b68e: 0692 lsls r2, r2, #26
801b690: d42d bmi.n 801b6ee <_printf_common+0xbe>
801b692: f104 0243 add.w r2, r4, #67 ; 0x43
801b696: 4639 mov r1, r7
801b698: 4630 mov r0, r6
801b69a: 47c0 blx r8
801b69c: 3001 adds r0, #1
801b69e: d020 beq.n 801b6e2 <_printf_common+0xb2>
801b6a0: 6823 ldr r3, [r4, #0]
801b6a2: 68e5 ldr r5, [r4, #12]
801b6a4: f8d9 2000 ldr.w r2, [r9]
801b6a8: f003 0306 and.w r3, r3, #6
801b6ac: 2b04 cmp r3, #4
801b6ae: bf08 it eq
801b6b0: 1aad subeq r5, r5, r2
801b6b2: 68a3 ldr r3, [r4, #8]
801b6b4: 6922 ldr r2, [r4, #16]
801b6b6: bf0c ite eq
801b6b8: ea25 75e5 biceq.w r5, r5, r5, asr #31
801b6bc: 2500 movne r5, #0
801b6be: 4293 cmp r3, r2
801b6c0: bfc4 itt gt
801b6c2: 1a9b subgt r3, r3, r2
801b6c4: 18ed addgt r5, r5, r3
801b6c6: f04f 0900 mov.w r9, #0
801b6ca: 341a adds r4, #26
801b6cc: 454d cmp r5, r9
801b6ce: d11a bne.n 801b706 <_printf_common+0xd6>
801b6d0: 2000 movs r0, #0
801b6d2: e008 b.n 801b6e6 <_printf_common+0xb6>
801b6d4: 2301 movs r3, #1
801b6d6: 4652 mov r2, sl
801b6d8: 4639 mov r1, r7
801b6da: 4630 mov r0, r6
801b6dc: 47c0 blx r8
801b6de: 3001 adds r0, #1
801b6e0: d103 bne.n 801b6ea <_printf_common+0xba>
801b6e2: f04f 30ff mov.w r0, #4294967295
801b6e6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
801b6ea: 3501 adds r5, #1
801b6ec: e7c3 b.n 801b676 <_printf_common+0x46>
801b6ee: 18e1 adds r1, r4, r3
801b6f0: 1c5a adds r2, r3, #1
801b6f2: 2030 movs r0, #48 ; 0x30
801b6f4: f881 0043 strb.w r0, [r1, #67] ; 0x43
801b6f8: 4422 add r2, r4
801b6fa: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
801b6fe: f882 1043 strb.w r1, [r2, #67] ; 0x43
801b702: 3302 adds r3, #2
801b704: e7c5 b.n 801b692 <_printf_common+0x62>
801b706: 2301 movs r3, #1
801b708: 4622 mov r2, r4
801b70a: 4639 mov r1, r7
801b70c: 4630 mov r0, r6
801b70e: 47c0 blx r8
801b710: 3001 adds r0, #1
801b712: d0e6 beq.n 801b6e2 <_printf_common+0xb2>
801b714: f109 0901 add.w r9, r9, #1
801b718: e7d8 b.n 801b6cc <_printf_common+0x9c>
...
0801b71c <_printf_i>:
801b71c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
801b720: f101 0c43 add.w ip, r1, #67 ; 0x43
801b724: 460c mov r4, r1
801b726: 7e09 ldrb r1, [r1, #24]
801b728: b085 sub sp, #20
801b72a: 296e cmp r1, #110 ; 0x6e
801b72c: 4617 mov r7, r2
801b72e: 4606 mov r6, r0
801b730: 4698 mov r8, r3
801b732: 9a0c ldr r2, [sp, #48] ; 0x30
801b734: f000 80b3 beq.w 801b89e <_printf_i+0x182>
801b738: d822 bhi.n 801b780 <_printf_i+0x64>
801b73a: 2963 cmp r1, #99 ; 0x63
801b73c: d036 beq.n 801b7ac <_printf_i+0x90>
801b73e: d80a bhi.n 801b756 <_printf_i+0x3a>
801b740: 2900 cmp r1, #0
801b742: f000 80b9 beq.w 801b8b8 <_printf_i+0x19c>
801b746: 2958 cmp r1, #88 ; 0x58
801b748: f000 8083 beq.w 801b852 <_printf_i+0x136>
801b74c: f104 0542 add.w r5, r4, #66 ; 0x42
801b750: f884 1042 strb.w r1, [r4, #66] ; 0x42
801b754: e032 b.n 801b7bc <_printf_i+0xa0>
801b756: 2964 cmp r1, #100 ; 0x64
801b758: d001 beq.n 801b75e <_printf_i+0x42>
801b75a: 2969 cmp r1, #105 ; 0x69
801b75c: d1f6 bne.n 801b74c <_printf_i+0x30>
801b75e: 6820 ldr r0, [r4, #0]
801b760: 6813 ldr r3, [r2, #0]
801b762: 0605 lsls r5, r0, #24
801b764: f103 0104 add.w r1, r3, #4
801b768: d52a bpl.n 801b7c0 <_printf_i+0xa4>
801b76a: 681b ldr r3, [r3, #0]
801b76c: 6011 str r1, [r2, #0]
801b76e: 2b00 cmp r3, #0
801b770: da03 bge.n 801b77a <_printf_i+0x5e>
801b772: 222d movs r2, #45 ; 0x2d
801b774: 425b negs r3, r3
801b776: f884 2043 strb.w r2, [r4, #67] ; 0x43
801b77a: 486f ldr r0, [pc, #444] ; (801b938 <_printf_i+0x21c>)
801b77c: 220a movs r2, #10
801b77e: e039 b.n 801b7f4 <_printf_i+0xd8>
801b780: 2973 cmp r1, #115 ; 0x73
801b782: f000 809d beq.w 801b8c0 <_printf_i+0x1a4>
801b786: d808 bhi.n 801b79a <_printf_i+0x7e>
801b788: 296f cmp r1, #111 ; 0x6f
801b78a: d020 beq.n 801b7ce <_printf_i+0xb2>
801b78c: 2970 cmp r1, #112 ; 0x70
801b78e: d1dd bne.n 801b74c <_printf_i+0x30>
801b790: 6823 ldr r3, [r4, #0]
801b792: f043 0320 orr.w r3, r3, #32
801b796: 6023 str r3, [r4, #0]
801b798: e003 b.n 801b7a2 <_printf_i+0x86>
801b79a: 2975 cmp r1, #117 ; 0x75
801b79c: d017 beq.n 801b7ce <_printf_i+0xb2>
801b79e: 2978 cmp r1, #120 ; 0x78
801b7a0: d1d4 bne.n 801b74c <_printf_i+0x30>
801b7a2: 2378 movs r3, #120 ; 0x78
801b7a4: f884 3045 strb.w r3, [r4, #69] ; 0x45
801b7a8: 4864 ldr r0, [pc, #400] ; (801b93c <_printf_i+0x220>)
801b7aa: e055 b.n 801b858 <_printf_i+0x13c>
801b7ac: 6813 ldr r3, [r2, #0]
801b7ae: 1d19 adds r1, r3, #4
801b7b0: 681b ldr r3, [r3, #0]
801b7b2: 6011 str r1, [r2, #0]
801b7b4: f104 0542 add.w r5, r4, #66 ; 0x42
801b7b8: f884 3042 strb.w r3, [r4, #66] ; 0x42
801b7bc: 2301 movs r3, #1
801b7be: e08c b.n 801b8da <_printf_i+0x1be>
801b7c0: 681b ldr r3, [r3, #0]
801b7c2: 6011 str r1, [r2, #0]
801b7c4: f010 0f40 tst.w r0, #64 ; 0x40
801b7c8: bf18 it ne
801b7ca: b21b sxthne r3, r3
801b7cc: e7cf b.n 801b76e <_printf_i+0x52>
801b7ce: 6813 ldr r3, [r2, #0]
801b7d0: 6825 ldr r5, [r4, #0]
801b7d2: 1d18 adds r0, r3, #4
801b7d4: 6010 str r0, [r2, #0]
801b7d6: 0628 lsls r0, r5, #24
801b7d8: d501 bpl.n 801b7de <_printf_i+0xc2>
801b7da: 681b ldr r3, [r3, #0]
801b7dc: e002 b.n 801b7e4 <_printf_i+0xc8>
801b7de: 0668 lsls r0, r5, #25
801b7e0: d5fb bpl.n 801b7da <_printf_i+0xbe>
801b7e2: 881b ldrh r3, [r3, #0]
801b7e4: 4854 ldr r0, [pc, #336] ; (801b938 <_printf_i+0x21c>)
801b7e6: 296f cmp r1, #111 ; 0x6f
801b7e8: bf14 ite ne
801b7ea: 220a movne r2, #10
801b7ec: 2208 moveq r2, #8
801b7ee: 2100 movs r1, #0
801b7f0: f884 1043 strb.w r1, [r4, #67] ; 0x43
801b7f4: 6865 ldr r5, [r4, #4]
801b7f6: 60a5 str r5, [r4, #8]
801b7f8: 2d00 cmp r5, #0
801b7fa: f2c0 8095 blt.w 801b928 <_printf_i+0x20c>
801b7fe: 6821 ldr r1, [r4, #0]
801b800: f021 0104 bic.w r1, r1, #4
801b804: 6021 str r1, [r4, #0]
801b806: 2b00 cmp r3, #0
801b808: d13d bne.n 801b886 <_printf_i+0x16a>
801b80a: 2d00 cmp r5, #0
801b80c: f040 808e bne.w 801b92c <_printf_i+0x210>
801b810: 4665 mov r5, ip
801b812: 2a08 cmp r2, #8
801b814: d10b bne.n 801b82e <_printf_i+0x112>
801b816: 6823 ldr r3, [r4, #0]
801b818: 07db lsls r3, r3, #31
801b81a: d508 bpl.n 801b82e <_printf_i+0x112>
801b81c: 6923 ldr r3, [r4, #16]
801b81e: 6862 ldr r2, [r4, #4]
801b820: 429a cmp r2, r3
801b822: bfde ittt le
801b824: 2330 movle r3, #48 ; 0x30
801b826: f805 3c01 strble.w r3, [r5, #-1]
801b82a: f105 35ff addle.w r5, r5, #4294967295
801b82e: ebac 0305 sub.w r3, ip, r5
801b832: 6123 str r3, [r4, #16]
801b834: f8cd 8000 str.w r8, [sp]
801b838: 463b mov r3, r7
801b83a: aa03 add r2, sp, #12
801b83c: 4621 mov r1, r4
801b83e: 4630 mov r0, r6
801b840: f7ff fef6 bl 801b630 <_printf_common>
801b844: 3001 adds r0, #1
801b846: d14d bne.n 801b8e4 <_printf_i+0x1c8>
801b848: f04f 30ff mov.w r0, #4294967295
801b84c: b005 add sp, #20
801b84e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
801b852: 4839 ldr r0, [pc, #228] ; (801b938 <_printf_i+0x21c>)
801b854: f884 1045 strb.w r1, [r4, #69] ; 0x45
801b858: 6813 ldr r3, [r2, #0]
801b85a: 6821 ldr r1, [r4, #0]
801b85c: 1d1d adds r5, r3, #4
801b85e: 681b ldr r3, [r3, #0]
801b860: 6015 str r5, [r2, #0]
801b862: 060a lsls r2, r1, #24
801b864: d50b bpl.n 801b87e <_printf_i+0x162>
801b866: 07ca lsls r2, r1, #31
801b868: bf44 itt mi
801b86a: f041 0120 orrmi.w r1, r1, #32
801b86e: 6021 strmi r1, [r4, #0]
801b870: b91b cbnz r3, 801b87a <_printf_i+0x15e>
801b872: 6822 ldr r2, [r4, #0]
801b874: f022 0220 bic.w r2, r2, #32
801b878: 6022 str r2, [r4, #0]
801b87a: 2210 movs r2, #16
801b87c: e7b7 b.n 801b7ee <_printf_i+0xd2>
801b87e: 064d lsls r5, r1, #25
801b880: bf48 it mi
801b882: b29b uxthmi r3, r3
801b884: e7ef b.n 801b866 <_printf_i+0x14a>
801b886: 4665 mov r5, ip
801b888: fbb3 f1f2 udiv r1, r3, r2
801b88c: fb02 3311 mls r3, r2, r1, r3
801b890: 5cc3 ldrb r3, [r0, r3]
801b892: f805 3d01 strb.w r3, [r5, #-1]!
801b896: 460b mov r3, r1
801b898: 2900 cmp r1, #0
801b89a: d1f5 bne.n 801b888 <_printf_i+0x16c>
801b89c: e7b9 b.n 801b812 <_printf_i+0xf6>
801b89e: 6813 ldr r3, [r2, #0]
801b8a0: 6825 ldr r5, [r4, #0]
801b8a2: 6961 ldr r1, [r4, #20]
801b8a4: 1d18 adds r0, r3, #4
801b8a6: 6010 str r0, [r2, #0]
801b8a8: 0628 lsls r0, r5, #24
801b8aa: 681b ldr r3, [r3, #0]
801b8ac: d501 bpl.n 801b8b2 <_printf_i+0x196>
801b8ae: 6019 str r1, [r3, #0]
801b8b0: e002 b.n 801b8b8 <_printf_i+0x19c>
801b8b2: 066a lsls r2, r5, #25
801b8b4: d5fb bpl.n 801b8ae <_printf_i+0x192>
801b8b6: 8019 strh r1, [r3, #0]
801b8b8: 2300 movs r3, #0
801b8ba: 6123 str r3, [r4, #16]
801b8bc: 4665 mov r5, ip
801b8be: e7b9 b.n 801b834 <_printf_i+0x118>
801b8c0: 6813 ldr r3, [r2, #0]
801b8c2: 1d19 adds r1, r3, #4
801b8c4: 6011 str r1, [r2, #0]
801b8c6: 681d ldr r5, [r3, #0]
801b8c8: 6862 ldr r2, [r4, #4]
801b8ca: 2100 movs r1, #0
801b8cc: 4628 mov r0, r5
801b8ce: f7e4 fc9f bl 8000210 <memchr>
801b8d2: b108 cbz r0, 801b8d8 <_printf_i+0x1bc>
801b8d4: 1b40 subs r0, r0, r5
801b8d6: 6060 str r0, [r4, #4]
801b8d8: 6863 ldr r3, [r4, #4]
801b8da: 6123 str r3, [r4, #16]
801b8dc: 2300 movs r3, #0
801b8de: f884 3043 strb.w r3, [r4, #67] ; 0x43
801b8e2: e7a7 b.n 801b834 <_printf_i+0x118>
801b8e4: 6923 ldr r3, [r4, #16]
801b8e6: 462a mov r2, r5
801b8e8: 4639 mov r1, r7
801b8ea: 4630 mov r0, r6
801b8ec: 47c0 blx r8
801b8ee: 3001 adds r0, #1
801b8f0: d0aa beq.n 801b848 <_printf_i+0x12c>
801b8f2: 6823 ldr r3, [r4, #0]
801b8f4: 079b lsls r3, r3, #30
801b8f6: d413 bmi.n 801b920 <_printf_i+0x204>
801b8f8: 68e0 ldr r0, [r4, #12]
801b8fa: 9b03 ldr r3, [sp, #12]
801b8fc: 4298 cmp r0, r3
801b8fe: bfb8 it lt
801b900: 4618 movlt r0, r3
801b902: e7a3 b.n 801b84c <_printf_i+0x130>
801b904: 2301 movs r3, #1
801b906: 464a mov r2, r9
801b908: 4639 mov r1, r7
801b90a: 4630 mov r0, r6
801b90c: 47c0 blx r8
801b90e: 3001 adds r0, #1
801b910: d09a beq.n 801b848 <_printf_i+0x12c>
801b912: 3501 adds r5, #1
801b914: 68e3 ldr r3, [r4, #12]
801b916: 9a03 ldr r2, [sp, #12]
801b918: 1a9b subs r3, r3, r2
801b91a: 42ab cmp r3, r5
801b91c: dcf2 bgt.n 801b904 <_printf_i+0x1e8>
801b91e: e7eb b.n 801b8f8 <_printf_i+0x1dc>
801b920: 2500 movs r5, #0
801b922: f104 0919 add.w r9, r4, #25
801b926: e7f5 b.n 801b914 <_printf_i+0x1f8>
801b928: 2b00 cmp r3, #0
801b92a: d1ac bne.n 801b886 <_printf_i+0x16a>
801b92c: 7803 ldrb r3, [r0, #0]
801b92e: f884 3042 strb.w r3, [r4, #66] ; 0x42
801b932: f104 0542 add.w r5, r4, #66 ; 0x42
801b936: e76c b.n 801b812 <_printf_i+0xf6>
801b938: 08020f0d .word 0x08020f0d
801b93c: 08020f1e .word 0x08020f1e
0801b940 <_sbrk_r>:
801b940: b538 push {r3, r4, r5, lr}
801b942: 4c06 ldr r4, [pc, #24] ; (801b95c <_sbrk_r+0x1c>)
801b944: 2300 movs r3, #0
801b946: 4605 mov r5, r0
801b948: 4608 mov r0, r1
801b94a: 6023 str r3, [r4, #0]
801b94c: f7e8 ff90 bl 8004870 <_sbrk>
801b950: 1c43 adds r3, r0, #1
801b952: d102 bne.n 801b95a <_sbrk_r+0x1a>
801b954: 6823 ldr r3, [r4, #0]
801b956: b103 cbz r3, 801b95a <_sbrk_r+0x1a>
801b958: 602b str r3, [r5, #0]
801b95a: bd38 pop {r3, r4, r5, pc}
801b95c: 2000f604 .word 0x2000f604
0801b960 <__sread>:
801b960: b510 push {r4, lr}
801b962: 460c mov r4, r1
801b964: f9b1 100e ldrsh.w r1, [r1, #14]
801b968: f000 fa48 bl 801bdfc <_read_r>
801b96c: 2800 cmp r0, #0
801b96e: bfab itete ge
801b970: 6d63 ldrge r3, [r4, #84] ; 0x54
801b972: 89a3 ldrhlt r3, [r4, #12]
801b974: 181b addge r3, r3, r0
801b976: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
801b97a: bfac ite ge
801b97c: 6563 strge r3, [r4, #84] ; 0x54
801b97e: 81a3 strhlt r3, [r4, #12]
801b980: bd10 pop {r4, pc}
0801b982 <__swrite>:
801b982: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801b986: 461f mov r7, r3
801b988: 898b ldrh r3, [r1, #12]
801b98a: 05db lsls r3, r3, #23
801b98c: 4605 mov r5, r0
801b98e: 460c mov r4, r1
801b990: 4616 mov r6, r2
801b992: d505 bpl.n 801b9a0 <__swrite+0x1e>
801b994: 2302 movs r3, #2
801b996: 2200 movs r2, #0
801b998: f9b1 100e ldrsh.w r1, [r1, #14]
801b99c: f000 f9b6 bl 801bd0c <_lseek_r>
801b9a0: 89a3 ldrh r3, [r4, #12]
801b9a2: f9b4 100e ldrsh.w r1, [r4, #14]
801b9a6: f423 5380 bic.w r3, r3, #4096 ; 0x1000
801b9aa: 81a3 strh r3, [r4, #12]
801b9ac: 4632 mov r2, r6
801b9ae: 463b mov r3, r7
801b9b0: 4628 mov r0, r5
801b9b2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
801b9b6: f000 b869 b.w 801ba8c <_write_r>
0801b9ba <__sseek>:
801b9ba: b510 push {r4, lr}
801b9bc: 460c mov r4, r1
801b9be: f9b1 100e ldrsh.w r1, [r1, #14]
801b9c2: f000 f9a3 bl 801bd0c <_lseek_r>
801b9c6: 1c43 adds r3, r0, #1
801b9c8: 89a3 ldrh r3, [r4, #12]
801b9ca: bf15 itete ne
801b9cc: 6560 strne r0, [r4, #84] ; 0x54
801b9ce: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
801b9d2: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
801b9d6: 81a3 strheq r3, [r4, #12]
801b9d8: bf18 it ne
801b9da: 81a3 strhne r3, [r4, #12]
801b9dc: bd10 pop {r4, pc}
0801b9de <__sclose>:
801b9de: f9b1 100e ldrsh.w r1, [r1, #14]
801b9e2: f000 b8d3 b.w 801bb8c <_close_r>
...
0801b9e8 <__swbuf_r>:
801b9e8: b5f8 push {r3, r4, r5, r6, r7, lr}
801b9ea: 460e mov r6, r1
801b9ec: 4614 mov r4, r2
801b9ee: 4605 mov r5, r0
801b9f0: b118 cbz r0, 801b9fa <__swbuf_r+0x12>
801b9f2: 6983 ldr r3, [r0, #24]
801b9f4: b90b cbnz r3, 801b9fa <__swbuf_r+0x12>
801b9f6: f7ff fba1 bl 801b13c <__sinit>
801b9fa: 4b21 ldr r3, [pc, #132] ; (801ba80 <__swbuf_r+0x98>)
801b9fc: 429c cmp r4, r3
801b9fe: d12a bne.n 801ba56 <__swbuf_r+0x6e>
801ba00: 686c ldr r4, [r5, #4]
801ba02: 69a3 ldr r3, [r4, #24]
801ba04: 60a3 str r3, [r4, #8]
801ba06: 89a3 ldrh r3, [r4, #12]
801ba08: 071a lsls r2, r3, #28
801ba0a: d52e bpl.n 801ba6a <__swbuf_r+0x82>
801ba0c: 6923 ldr r3, [r4, #16]
801ba0e: b363 cbz r3, 801ba6a <__swbuf_r+0x82>
801ba10: 6923 ldr r3, [r4, #16]
801ba12: 6820 ldr r0, [r4, #0]
801ba14: 1ac0 subs r0, r0, r3
801ba16: 6963 ldr r3, [r4, #20]
801ba18: b2f6 uxtb r6, r6
801ba1a: 4283 cmp r3, r0
801ba1c: 4637 mov r7, r6
801ba1e: dc04 bgt.n 801ba2a <__swbuf_r+0x42>
801ba20: 4621 mov r1, r4
801ba22: 4628 mov r0, r5
801ba24: f000 f948 bl 801bcb8 <_fflush_r>
801ba28: bb28 cbnz r0, 801ba76 <__swbuf_r+0x8e>
801ba2a: 68a3 ldr r3, [r4, #8]
801ba2c: 3b01 subs r3, #1
801ba2e: 60a3 str r3, [r4, #8]
801ba30: 6823 ldr r3, [r4, #0]
801ba32: 1c5a adds r2, r3, #1
801ba34: 6022 str r2, [r4, #0]
801ba36: 701e strb r6, [r3, #0]
801ba38: 6963 ldr r3, [r4, #20]
801ba3a: 3001 adds r0, #1
801ba3c: 4283 cmp r3, r0
801ba3e: d004 beq.n 801ba4a <__swbuf_r+0x62>
801ba40: 89a3 ldrh r3, [r4, #12]
801ba42: 07db lsls r3, r3, #31
801ba44: d519 bpl.n 801ba7a <__swbuf_r+0x92>
801ba46: 2e0a cmp r6, #10
801ba48: d117 bne.n 801ba7a <__swbuf_r+0x92>
801ba4a: 4621 mov r1, r4
801ba4c: 4628 mov r0, r5
801ba4e: f000 f933 bl 801bcb8 <_fflush_r>
801ba52: b190 cbz r0, 801ba7a <__swbuf_r+0x92>
801ba54: e00f b.n 801ba76 <__swbuf_r+0x8e>
801ba56: 4b0b ldr r3, [pc, #44] ; (801ba84 <__swbuf_r+0x9c>)
801ba58: 429c cmp r4, r3
801ba5a: d101 bne.n 801ba60 <__swbuf_r+0x78>
801ba5c: 68ac ldr r4, [r5, #8]
801ba5e: e7d0 b.n 801ba02 <__swbuf_r+0x1a>
801ba60: 4b09 ldr r3, [pc, #36] ; (801ba88 <__swbuf_r+0xa0>)
801ba62: 429c cmp r4, r3
801ba64: bf08 it eq
801ba66: 68ec ldreq r4, [r5, #12]
801ba68: e7cb b.n 801ba02 <__swbuf_r+0x1a>
801ba6a: 4621 mov r1, r4
801ba6c: 4628 mov r0, r5
801ba6e: f000 f81f bl 801bab0 <__swsetup_r>
801ba72: 2800 cmp r0, #0
801ba74: d0cc beq.n 801ba10 <__swbuf_r+0x28>
801ba76: f04f 37ff mov.w r7, #4294967295
801ba7a: 4638 mov r0, r7
801ba7c: bdf8 pop {r3, r4, r5, r6, r7, pc}
801ba7e: bf00 nop
801ba80: 08020ebc .word 0x08020ebc
801ba84: 08020edc .word 0x08020edc
801ba88: 08020e9c .word 0x08020e9c
0801ba8c <_write_r>:
801ba8c: b538 push {r3, r4, r5, lr}
801ba8e: 4c07 ldr r4, [pc, #28] ; (801baac <_write_r+0x20>)
801ba90: 4605 mov r5, r0
801ba92: 4608 mov r0, r1
801ba94: 4611 mov r1, r2
801ba96: 2200 movs r2, #0
801ba98: 6022 str r2, [r4, #0]
801ba9a: 461a mov r2, r3
801ba9c: f7e8 fe97 bl 80047ce <_write>
801baa0: 1c43 adds r3, r0, #1
801baa2: d102 bne.n 801baaa <_write_r+0x1e>
801baa4: 6823 ldr r3, [r4, #0]
801baa6: b103 cbz r3, 801baaa <_write_r+0x1e>
801baa8: 602b str r3, [r5, #0]
801baaa: bd38 pop {r3, r4, r5, pc}
801baac: 2000f604 .word 0x2000f604
0801bab0 <__swsetup_r>:
801bab0: 4b32 ldr r3, [pc, #200] ; (801bb7c <__swsetup_r+0xcc>)
801bab2: b570 push {r4, r5, r6, lr}
801bab4: 681d ldr r5, [r3, #0]
801bab6: 4606 mov r6, r0
801bab8: 460c mov r4, r1
801baba: b125 cbz r5, 801bac6 <__swsetup_r+0x16>
801babc: 69ab ldr r3, [r5, #24]
801babe: b913 cbnz r3, 801bac6 <__swsetup_r+0x16>
801bac0: 4628 mov r0, r5
801bac2: f7ff fb3b bl 801b13c <__sinit>
801bac6: 4b2e ldr r3, [pc, #184] ; (801bb80 <__swsetup_r+0xd0>)
801bac8: 429c cmp r4, r3
801baca: d10f bne.n 801baec <__swsetup_r+0x3c>
801bacc: 686c ldr r4, [r5, #4]
801bace: f9b4 300c ldrsh.w r3, [r4, #12]
801bad2: b29a uxth r2, r3
801bad4: 0715 lsls r5, r2, #28
801bad6: d42c bmi.n 801bb32 <__swsetup_r+0x82>
801bad8: 06d0 lsls r0, r2, #27
801bada: d411 bmi.n 801bb00 <__swsetup_r+0x50>
801badc: 2209 movs r2, #9
801bade: 6032 str r2, [r6, #0]
801bae0: f043 0340 orr.w r3, r3, #64 ; 0x40
801bae4: 81a3 strh r3, [r4, #12]
801bae6: f04f 30ff mov.w r0, #4294967295
801baea: e03e b.n 801bb6a <__swsetup_r+0xba>
801baec: 4b25 ldr r3, [pc, #148] ; (801bb84 <__swsetup_r+0xd4>)
801baee: 429c cmp r4, r3
801baf0: d101 bne.n 801baf6 <__swsetup_r+0x46>
801baf2: 68ac ldr r4, [r5, #8]
801baf4: e7eb b.n 801bace <__swsetup_r+0x1e>
801baf6: 4b24 ldr r3, [pc, #144] ; (801bb88 <__swsetup_r+0xd8>)
801baf8: 429c cmp r4, r3
801bafa: bf08 it eq
801bafc: 68ec ldreq r4, [r5, #12]
801bafe: e7e6 b.n 801bace <__swsetup_r+0x1e>
801bb00: 0751 lsls r1, r2, #29
801bb02: d512 bpl.n 801bb2a <__swsetup_r+0x7a>
801bb04: 6b61 ldr r1, [r4, #52] ; 0x34
801bb06: b141 cbz r1, 801bb1a <__swsetup_r+0x6a>
801bb08: f104 0344 add.w r3, r4, #68 ; 0x44
801bb0c: 4299 cmp r1, r3
801bb0e: d002 beq.n 801bb16 <__swsetup_r+0x66>
801bb10: 4630 mov r0, r6
801bb12: f7ff fba5 bl 801b260 <_free_r>
801bb16: 2300 movs r3, #0
801bb18: 6363 str r3, [r4, #52] ; 0x34
801bb1a: 89a3 ldrh r3, [r4, #12]
801bb1c: f023 0324 bic.w r3, r3, #36 ; 0x24
801bb20: 81a3 strh r3, [r4, #12]
801bb22: 2300 movs r3, #0
801bb24: 6063 str r3, [r4, #4]
801bb26: 6923 ldr r3, [r4, #16]
801bb28: 6023 str r3, [r4, #0]
801bb2a: 89a3 ldrh r3, [r4, #12]
801bb2c: f043 0308 orr.w r3, r3, #8
801bb30: 81a3 strh r3, [r4, #12]
801bb32: 6923 ldr r3, [r4, #16]
801bb34: b94b cbnz r3, 801bb4a <__swsetup_r+0x9a>
801bb36: 89a3 ldrh r3, [r4, #12]
801bb38: f403 7320 and.w r3, r3, #640 ; 0x280
801bb3c: f5b3 7f00 cmp.w r3, #512 ; 0x200
801bb40: d003 beq.n 801bb4a <__swsetup_r+0x9a>
801bb42: 4621 mov r1, r4
801bb44: 4630 mov r0, r6
801bb46: f000 f917 bl 801bd78 <__smakebuf_r>
801bb4a: 89a2 ldrh r2, [r4, #12]
801bb4c: f012 0301 ands.w r3, r2, #1
801bb50: d00c beq.n 801bb6c <__swsetup_r+0xbc>
801bb52: 2300 movs r3, #0
801bb54: 60a3 str r3, [r4, #8]
801bb56: 6963 ldr r3, [r4, #20]
801bb58: 425b negs r3, r3
801bb5a: 61a3 str r3, [r4, #24]
801bb5c: 6923 ldr r3, [r4, #16]
801bb5e: b953 cbnz r3, 801bb76 <__swsetup_r+0xc6>
801bb60: f9b4 300c ldrsh.w r3, [r4, #12]
801bb64: f013 0080 ands.w r0, r3, #128 ; 0x80
801bb68: d1ba bne.n 801bae0 <__swsetup_r+0x30>
801bb6a: bd70 pop {r4, r5, r6, pc}
801bb6c: 0792 lsls r2, r2, #30
801bb6e: bf58 it pl
801bb70: 6963 ldrpl r3, [r4, #20]
801bb72: 60a3 str r3, [r4, #8]
801bb74: e7f2 b.n 801bb5c <__swsetup_r+0xac>
801bb76: 2000 movs r0, #0
801bb78: e7f7 b.n 801bb6a <__swsetup_r+0xba>
801bb7a: bf00 nop
801bb7c: 20000084 .word 0x20000084
801bb80: 08020ebc .word 0x08020ebc
801bb84: 08020edc .word 0x08020edc
801bb88: 08020e9c .word 0x08020e9c
0801bb8c <_close_r>:
801bb8c: b538 push {r3, r4, r5, lr}
801bb8e: 4c06 ldr r4, [pc, #24] ; (801bba8 <_close_r+0x1c>)
801bb90: 2300 movs r3, #0
801bb92: 4605 mov r5, r0
801bb94: 4608 mov r0, r1
801bb96: 6023 str r3, [r4, #0]
801bb98: f7e8 fe35 bl 8004806 <_close>
801bb9c: 1c43 adds r3, r0, #1
801bb9e: d102 bne.n 801bba6 <_close_r+0x1a>
801bba0: 6823 ldr r3, [r4, #0]
801bba2: b103 cbz r3, 801bba6 <_close_r+0x1a>
801bba4: 602b str r3, [r5, #0]
801bba6: bd38 pop {r3, r4, r5, pc}
801bba8: 2000f604 .word 0x2000f604
0801bbac <__sflush_r>:
801bbac: 898a ldrh r2, [r1, #12]
801bbae: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
801bbb2: 4605 mov r5, r0
801bbb4: 0710 lsls r0, r2, #28
801bbb6: 460c mov r4, r1
801bbb8: d458 bmi.n 801bc6c <__sflush_r+0xc0>
801bbba: 684b ldr r3, [r1, #4]
801bbbc: 2b00 cmp r3, #0
801bbbe: dc05 bgt.n 801bbcc <__sflush_r+0x20>
801bbc0: 6c0b ldr r3, [r1, #64] ; 0x40
801bbc2: 2b00 cmp r3, #0
801bbc4: dc02 bgt.n 801bbcc <__sflush_r+0x20>
801bbc6: 2000 movs r0, #0
801bbc8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
801bbcc: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bbce: 2e00 cmp r6, #0
801bbd0: d0f9 beq.n 801bbc6 <__sflush_r+0x1a>
801bbd2: 2300 movs r3, #0
801bbd4: f412 5280 ands.w r2, r2, #4096 ; 0x1000
801bbd8: 682f ldr r7, [r5, #0]
801bbda: 6a21 ldr r1, [r4, #32]
801bbdc: 602b str r3, [r5, #0]
801bbde: d032 beq.n 801bc46 <__sflush_r+0x9a>
801bbe0: 6d60 ldr r0, [r4, #84] ; 0x54
801bbe2: 89a3 ldrh r3, [r4, #12]
801bbe4: 075a lsls r2, r3, #29
801bbe6: d505 bpl.n 801bbf4 <__sflush_r+0x48>
801bbe8: 6863 ldr r3, [r4, #4]
801bbea: 1ac0 subs r0, r0, r3
801bbec: 6b63 ldr r3, [r4, #52] ; 0x34
801bbee: b10b cbz r3, 801bbf4 <__sflush_r+0x48>
801bbf0: 6c23 ldr r3, [r4, #64] ; 0x40
801bbf2: 1ac0 subs r0, r0, r3
801bbf4: 2300 movs r3, #0
801bbf6: 4602 mov r2, r0
801bbf8: 6ae6 ldr r6, [r4, #44] ; 0x2c
801bbfa: 6a21 ldr r1, [r4, #32]
801bbfc: 4628 mov r0, r5
801bbfe: 47b0 blx r6
801bc00: 1c43 adds r3, r0, #1
801bc02: 89a3 ldrh r3, [r4, #12]
801bc04: d106 bne.n 801bc14 <__sflush_r+0x68>
801bc06: 6829 ldr r1, [r5, #0]
801bc08: 291d cmp r1, #29
801bc0a: d848 bhi.n 801bc9e <__sflush_r+0xf2>
801bc0c: 4a29 ldr r2, [pc, #164] ; (801bcb4 <__sflush_r+0x108>)
801bc0e: 40ca lsrs r2, r1
801bc10: 07d6 lsls r6, r2, #31
801bc12: d544 bpl.n 801bc9e <__sflush_r+0xf2>
801bc14: 2200 movs r2, #0
801bc16: 6062 str r2, [r4, #4]
801bc18: 04d9 lsls r1, r3, #19
801bc1a: 6922 ldr r2, [r4, #16]
801bc1c: 6022 str r2, [r4, #0]
801bc1e: d504 bpl.n 801bc2a <__sflush_r+0x7e>
801bc20: 1c42 adds r2, r0, #1
801bc22: d101 bne.n 801bc28 <__sflush_r+0x7c>
801bc24: 682b ldr r3, [r5, #0]
801bc26: b903 cbnz r3, 801bc2a <__sflush_r+0x7e>
801bc28: 6560 str r0, [r4, #84] ; 0x54
801bc2a: 6b61 ldr r1, [r4, #52] ; 0x34
801bc2c: 602f str r7, [r5, #0]
801bc2e: 2900 cmp r1, #0
801bc30: d0c9 beq.n 801bbc6 <__sflush_r+0x1a>
801bc32: f104 0344 add.w r3, r4, #68 ; 0x44
801bc36: 4299 cmp r1, r3
801bc38: d002 beq.n 801bc40 <__sflush_r+0x94>
801bc3a: 4628 mov r0, r5
801bc3c: f7ff fb10 bl 801b260 <_free_r>
801bc40: 2000 movs r0, #0
801bc42: 6360 str r0, [r4, #52] ; 0x34
801bc44: e7c0 b.n 801bbc8 <__sflush_r+0x1c>
801bc46: 2301 movs r3, #1
801bc48: 4628 mov r0, r5
801bc4a: 47b0 blx r6
801bc4c: 1c41 adds r1, r0, #1
801bc4e: d1c8 bne.n 801bbe2 <__sflush_r+0x36>
801bc50: 682b ldr r3, [r5, #0]
801bc52: 2b00 cmp r3, #0
801bc54: d0c5 beq.n 801bbe2 <__sflush_r+0x36>
801bc56: 2b1d cmp r3, #29
801bc58: d001 beq.n 801bc5e <__sflush_r+0xb2>
801bc5a: 2b16 cmp r3, #22
801bc5c: d101 bne.n 801bc62 <__sflush_r+0xb6>
801bc5e: 602f str r7, [r5, #0]
801bc60: e7b1 b.n 801bbc6 <__sflush_r+0x1a>
801bc62: 89a3 ldrh r3, [r4, #12]
801bc64: f043 0340 orr.w r3, r3, #64 ; 0x40
801bc68: 81a3 strh r3, [r4, #12]
801bc6a: e7ad b.n 801bbc8 <__sflush_r+0x1c>
801bc6c: 690f ldr r7, [r1, #16]
801bc6e: 2f00 cmp r7, #0
801bc70: d0a9 beq.n 801bbc6 <__sflush_r+0x1a>
801bc72: 0793 lsls r3, r2, #30
801bc74: 680e ldr r6, [r1, #0]
801bc76: bf08 it eq
801bc78: 694b ldreq r3, [r1, #20]
801bc7a: 600f str r7, [r1, #0]
801bc7c: bf18 it ne
801bc7e: 2300 movne r3, #0
801bc80: eba6 0807 sub.w r8, r6, r7
801bc84: 608b str r3, [r1, #8]
801bc86: f1b8 0f00 cmp.w r8, #0
801bc8a: dd9c ble.n 801bbc6 <__sflush_r+0x1a>
801bc8c: 4643 mov r3, r8
801bc8e: 463a mov r2, r7
801bc90: 6a21 ldr r1, [r4, #32]
801bc92: 6aa6 ldr r6, [r4, #40] ; 0x28
801bc94: 4628 mov r0, r5
801bc96: 47b0 blx r6
801bc98: 2800 cmp r0, #0
801bc9a: dc06 bgt.n 801bcaa <__sflush_r+0xfe>
801bc9c: 89a3 ldrh r3, [r4, #12]
801bc9e: f043 0340 orr.w r3, r3, #64 ; 0x40
801bca2: 81a3 strh r3, [r4, #12]
801bca4: f04f 30ff mov.w r0, #4294967295
801bca8: e78e b.n 801bbc8 <__sflush_r+0x1c>
801bcaa: 4407 add r7, r0
801bcac: eba8 0800 sub.w r8, r8, r0
801bcb0: e7e9 b.n 801bc86 <__sflush_r+0xda>
801bcb2: bf00 nop
801bcb4: 20400001 .word 0x20400001
0801bcb8 <_fflush_r>:
801bcb8: b538 push {r3, r4, r5, lr}
801bcba: 690b ldr r3, [r1, #16]
801bcbc: 4605 mov r5, r0
801bcbe: 460c mov r4, r1
801bcc0: b1db cbz r3, 801bcfa <_fflush_r+0x42>
801bcc2: b118 cbz r0, 801bccc <_fflush_r+0x14>
801bcc4: 6983 ldr r3, [r0, #24]
801bcc6: b90b cbnz r3, 801bccc <_fflush_r+0x14>
801bcc8: f7ff fa38 bl 801b13c <__sinit>
801bccc: 4b0c ldr r3, [pc, #48] ; (801bd00 <_fflush_r+0x48>)
801bcce: 429c cmp r4, r3
801bcd0: d109 bne.n 801bce6 <_fflush_r+0x2e>
801bcd2: 686c ldr r4, [r5, #4]
801bcd4: f9b4 300c ldrsh.w r3, [r4, #12]
801bcd8: b17b cbz r3, 801bcfa <_fflush_r+0x42>
801bcda: 4621 mov r1, r4
801bcdc: 4628 mov r0, r5
801bcde: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
801bce2: f7ff bf63 b.w 801bbac <__sflush_r>
801bce6: 4b07 ldr r3, [pc, #28] ; (801bd04 <_fflush_r+0x4c>)
801bce8: 429c cmp r4, r3
801bcea: d101 bne.n 801bcf0 <_fflush_r+0x38>
801bcec: 68ac ldr r4, [r5, #8]
801bcee: e7f1 b.n 801bcd4 <_fflush_r+0x1c>
801bcf0: 4b05 ldr r3, [pc, #20] ; (801bd08 <_fflush_r+0x50>)
801bcf2: 429c cmp r4, r3
801bcf4: bf08 it eq
801bcf6: 68ec ldreq r4, [r5, #12]
801bcf8: e7ec b.n 801bcd4 <_fflush_r+0x1c>
801bcfa: 2000 movs r0, #0
801bcfc: bd38 pop {r3, r4, r5, pc}
801bcfe: bf00 nop
801bd00: 08020ebc .word 0x08020ebc
801bd04: 08020edc .word 0x08020edc
801bd08: 08020e9c .word 0x08020e9c
0801bd0c <_lseek_r>:
801bd0c: b538 push {r3, r4, r5, lr}
801bd0e: 4c07 ldr r4, [pc, #28] ; (801bd2c <_lseek_r+0x20>)
801bd10: 4605 mov r5, r0
801bd12: 4608 mov r0, r1
801bd14: 4611 mov r1, r2
801bd16: 2200 movs r2, #0
801bd18: 6022 str r2, [r4, #0]
801bd1a: 461a mov r2, r3
801bd1c: f7e8 fd9a bl 8004854 <_lseek>
801bd20: 1c43 adds r3, r0, #1
801bd22: d102 bne.n 801bd2a <_lseek_r+0x1e>
801bd24: 6823 ldr r3, [r4, #0]
801bd26: b103 cbz r3, 801bd2a <_lseek_r+0x1e>
801bd28: 602b str r3, [r5, #0]
801bd2a: bd38 pop {r3, r4, r5, pc}
801bd2c: 2000f604 .word 0x2000f604
0801bd30 <__swhatbuf_r>:
801bd30: b570 push {r4, r5, r6, lr}
801bd32: 460e mov r6, r1
801bd34: f9b1 100e ldrsh.w r1, [r1, #14]
801bd38: 2900 cmp r1, #0
801bd3a: b096 sub sp, #88 ; 0x58
801bd3c: 4614 mov r4, r2
801bd3e: 461d mov r5, r3
801bd40: da07 bge.n 801bd52 <__swhatbuf_r+0x22>
801bd42: 2300 movs r3, #0
801bd44: 602b str r3, [r5, #0]
801bd46: 89b3 ldrh r3, [r6, #12]
801bd48: 061a lsls r2, r3, #24
801bd4a: d410 bmi.n 801bd6e <__swhatbuf_r+0x3e>
801bd4c: f44f 6380 mov.w r3, #1024 ; 0x400
801bd50: e00e b.n 801bd70 <__swhatbuf_r+0x40>
801bd52: 466a mov r2, sp
801bd54: f000 f864 bl 801be20 <_fstat_r>
801bd58: 2800 cmp r0, #0
801bd5a: dbf2 blt.n 801bd42 <__swhatbuf_r+0x12>
801bd5c: 9a01 ldr r2, [sp, #4]
801bd5e: f402 4270 and.w r2, r2, #61440 ; 0xf000
801bd62: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
801bd66: 425a negs r2, r3
801bd68: 415a adcs r2, r3
801bd6a: 602a str r2, [r5, #0]
801bd6c: e7ee b.n 801bd4c <__swhatbuf_r+0x1c>
801bd6e: 2340 movs r3, #64 ; 0x40
801bd70: 2000 movs r0, #0
801bd72: 6023 str r3, [r4, #0]
801bd74: b016 add sp, #88 ; 0x58
801bd76: bd70 pop {r4, r5, r6, pc}
0801bd78 <__smakebuf_r>:
801bd78: 898b ldrh r3, [r1, #12]
801bd7a: b573 push {r0, r1, r4, r5, r6, lr}
801bd7c: 079d lsls r5, r3, #30
801bd7e: 4606 mov r6, r0
801bd80: 460c mov r4, r1
801bd82: d507 bpl.n 801bd94 <__smakebuf_r+0x1c>
801bd84: f104 0347 add.w r3, r4, #71 ; 0x47
801bd88: 6023 str r3, [r4, #0]
801bd8a: 6123 str r3, [r4, #16]
801bd8c: 2301 movs r3, #1
801bd8e: 6163 str r3, [r4, #20]
801bd90: b002 add sp, #8
801bd92: bd70 pop {r4, r5, r6, pc}
801bd94: ab01 add r3, sp, #4
801bd96: 466a mov r2, sp
801bd98: f7ff ffca bl 801bd30 <__swhatbuf_r>
801bd9c: 9900 ldr r1, [sp, #0]
801bd9e: 4605 mov r5, r0
801bda0: 4630 mov r0, r6
801bda2: f7ff faab bl 801b2fc <_malloc_r>
801bda6: b948 cbnz r0, 801bdbc <__smakebuf_r+0x44>
801bda8: f9b4 300c ldrsh.w r3, [r4, #12]
801bdac: 059a lsls r2, r3, #22
801bdae: d4ef bmi.n 801bd90 <__smakebuf_r+0x18>
801bdb0: f023 0303 bic.w r3, r3, #3
801bdb4: f043 0302 orr.w r3, r3, #2
801bdb8: 81a3 strh r3, [r4, #12]
801bdba: e7e3 b.n 801bd84 <__smakebuf_r+0xc>
801bdbc: 4b0d ldr r3, [pc, #52] ; (801bdf4 <__smakebuf_r+0x7c>)
801bdbe: 62b3 str r3, [r6, #40] ; 0x28
801bdc0: 89a3 ldrh r3, [r4, #12]
801bdc2: 6020 str r0, [r4, #0]
801bdc4: f043 0380 orr.w r3, r3, #128 ; 0x80
801bdc8: 81a3 strh r3, [r4, #12]
801bdca: 9b00 ldr r3, [sp, #0]
801bdcc: 6163 str r3, [r4, #20]
801bdce: 9b01 ldr r3, [sp, #4]
801bdd0: 6120 str r0, [r4, #16]
801bdd2: b15b cbz r3, 801bdec <__smakebuf_r+0x74>
801bdd4: f9b4 100e ldrsh.w r1, [r4, #14]
801bdd8: 4630 mov r0, r6
801bdda: f000 f833 bl 801be44 <_isatty_r>
801bdde: b128 cbz r0, 801bdec <__smakebuf_r+0x74>
801bde0: 89a3 ldrh r3, [r4, #12]
801bde2: f023 0303 bic.w r3, r3, #3
801bde6: f043 0301 orr.w r3, r3, #1
801bdea: 81a3 strh r3, [r4, #12]
801bdec: 89a3 ldrh r3, [r4, #12]
801bdee: 431d orrs r5, r3
801bdf0: 81a5 strh r5, [r4, #12]
801bdf2: e7cd b.n 801bd90 <__smakebuf_r+0x18>
801bdf4: 0801b105 .word 0x0801b105
0801bdf8 <__malloc_lock>:
801bdf8: 4770 bx lr
0801bdfa <__malloc_unlock>:
801bdfa: 4770 bx lr
0801bdfc <_read_r>:
801bdfc: b538 push {r3, r4, r5, lr}
801bdfe: 4c07 ldr r4, [pc, #28] ; (801be1c <_read_r+0x20>)
801be00: 4605 mov r5, r0
801be02: 4608 mov r0, r1
801be04: 4611 mov r1, r2
801be06: 2200 movs r2, #0
801be08: 6022 str r2, [r4, #0]
801be0a: 461a mov r2, r3
801be0c: f7e8 fcc2 bl 8004794 <_read>
801be10: 1c43 adds r3, r0, #1
801be12: d102 bne.n 801be1a <_read_r+0x1e>
801be14: 6823 ldr r3, [r4, #0]
801be16: b103 cbz r3, 801be1a <_read_r+0x1e>
801be18: 602b str r3, [r5, #0]
801be1a: bd38 pop {r3, r4, r5, pc}
801be1c: 2000f604 .word 0x2000f604
0801be20 <_fstat_r>:
801be20: b538 push {r3, r4, r5, lr}
801be22: 4c07 ldr r4, [pc, #28] ; (801be40 <_fstat_r+0x20>)
801be24: 2300 movs r3, #0
801be26: 4605 mov r5, r0
801be28: 4608 mov r0, r1
801be2a: 4611 mov r1, r2
801be2c: 6023 str r3, [r4, #0]
801be2e: f7e8 fcf6 bl 800481e <_fstat>
801be32: 1c43 adds r3, r0, #1
801be34: d102 bne.n 801be3c <_fstat_r+0x1c>
801be36: 6823 ldr r3, [r4, #0]
801be38: b103 cbz r3, 801be3c <_fstat_r+0x1c>
801be3a: 602b str r3, [r5, #0]
801be3c: bd38 pop {r3, r4, r5, pc}
801be3e: bf00 nop
801be40: 2000f604 .word 0x2000f604
0801be44 <_isatty_r>:
801be44: b538 push {r3, r4, r5, lr}
801be46: 4c06 ldr r4, [pc, #24] ; (801be60 <_isatty_r+0x1c>)
801be48: 2300 movs r3, #0
801be4a: 4605 mov r5, r0
801be4c: 4608 mov r0, r1
801be4e: 6023 str r3, [r4, #0]
801be50: f7e8 fcf5 bl 800483e <_isatty>
801be54: 1c43 adds r3, r0, #1
801be56: d102 bne.n 801be5e <_isatty_r+0x1a>
801be58: 6823 ldr r3, [r4, #0]
801be5a: b103 cbz r3, 801be5e <_isatty_r+0x1a>
801be5c: 602b str r3, [r5, #0]
801be5e: bd38 pop {r3, r4, r5, pc}
801be60: 2000f604 .word 0x2000f604
0801be64 <_init>:
801be64: b5f8 push {r3, r4, r5, r6, r7, lr}
801be66: bf00 nop
801be68: bcf8 pop {r3, r4, r5, r6, r7}
801be6a: bc08 pop {r3}
801be6c: 469e mov lr, r3
801be6e: 4770 bx lr
0801be70 <_fini>:
801be70: b5f8 push {r3, r4, r5, r6, r7, lr}
801be72: bf00 nop
801be74: bcf8 pop {r3, r4, r5, r6, r7}
801be76: bc08 pop {r3}
801be78: 469e mov lr, r3
801be7a: 4770 bx lr
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