ea4fb86ac1
- Ajout d'une structure monster pour pouvoir les différentier. - Début de la tache sur les ennemis - Modification de l'interaction projectile/ennemis
80364 lines
3 MiB
80364 lines
3 MiB
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Space_Invaders.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001c8 08000000 08000000 00010000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0001dc80 080001d0 080001d0 000101d0 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000050d0 0801de50 0801de50 0002de50 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08022f20 08022f20 000400e8 2**0
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CONTENTS
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4 .ARM 00000008 08022f20 08022f20 00032f20 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08022f28 08022f28 000400e8 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08022f28 08022f28 00032f28 2**2
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CONTENTS, ALLOC, LOAD, DATA
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7 .fini_array 00000004 08022f2c 08022f2c 00032f2c 2**2
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CONTENTS, ALLOC, LOAD, DATA
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8 .data 000000e8 20000000 08022f30 00040000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 0000f760 200000e8 08023018 000400e8 2**2
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ALLOC
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10 ._user_heap_stack 00000600 2000f848 08023018 0004f848 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 000400e8 2**0
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CONTENTS, READONLY
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12 .debug_info 00055c57 00000000 00000000 00040118 2**0
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CONTENTS, READONLY, DEBUGGING
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13 .debug_abbrev 00009e35 00000000 00000000 00095d6f 2**0
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CONTENTS, READONLY, DEBUGGING
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14 .debug_aranges 00003580 00000000 00000000 0009fba8 2**3
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CONTENTS, READONLY, DEBUGGING
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15 .debug_ranges 00003288 00000000 00000000 000a3128 2**3
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CONTENTS, READONLY, DEBUGGING
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16 .debug_macro 0003df8f 00000000 00000000 000a63b0 2**0
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CONTENTS, READONLY, DEBUGGING
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17 .debug_line 0003e2b5 00000000 00000000 000e433f 2**0
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CONTENTS, READONLY, DEBUGGING
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18 .debug_str 001332e5 00000000 00000000 001225f4 2**0
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CONTENTS, READONLY, DEBUGGING
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19 .comment 0000007b 00000000 00000000 002558d9 2**0
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CONTENTS, READONLY
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20 .debug_frame 0000e6d0 00000000 00000000 00255954 2**2
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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080001d0 <__do_global_dtors_aux>:
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80001d0: b510 push {r4, lr}
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80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
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80001d4: 7823 ldrb r3, [r4, #0]
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80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
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80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
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80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
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80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
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80001de: f3af 8000 nop.w
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80001e2: 2301 movs r3, #1
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80001e4: 7023 strb r3, [r4, #0]
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80001e6: bd10 pop {r4, pc}
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80001e8: 200000e8 .word 0x200000e8
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80001ec: 00000000 .word 0x00000000
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80001f0: 0801de38 .word 0x0801de38
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080001f4 <frame_dummy>:
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80001f4: b508 push {r3, lr}
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80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 <frame_dummy+0x10>)
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80001f8: b11b cbz r3, 8000202 <frame_dummy+0xe>
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80001fa: 4903 ldr r1, [pc, #12] ; (8000208 <frame_dummy+0x14>)
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80001fc: 4803 ldr r0, [pc, #12] ; (800020c <frame_dummy+0x18>)
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80001fe: f3af 8000 nop.w
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8000202: bd08 pop {r3, pc}
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8000204: 00000000 .word 0x00000000
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8000208: 200000ec .word 0x200000ec
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800020c: 0801de38 .word 0x0801de38
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08000210 <memchr>:
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8000210: f001 01ff and.w r1, r1, #255 ; 0xff
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8000214: 2a10 cmp r2, #16
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8000216: db2b blt.n 8000270 <memchr+0x60>
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8000218: f010 0f07 tst.w r0, #7
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800021c: d008 beq.n 8000230 <memchr+0x20>
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800021e: f810 3b01 ldrb.w r3, [r0], #1
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8000222: 3a01 subs r2, #1
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8000224: 428b cmp r3, r1
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8000226: d02d beq.n 8000284 <memchr+0x74>
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8000228: f010 0f07 tst.w r0, #7
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800022c: b342 cbz r2, 8000280 <memchr+0x70>
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800022e: d1f6 bne.n 800021e <memchr+0xe>
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8000230: b4f0 push {r4, r5, r6, r7}
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8000232: ea41 2101 orr.w r1, r1, r1, lsl #8
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8000236: ea41 4101 orr.w r1, r1, r1, lsl #16
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800023a: f022 0407 bic.w r4, r2, #7
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800023e: f07f 0700 mvns.w r7, #0
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8000242: 2300 movs r3, #0
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8000244: e8f0 5602 ldrd r5, r6, [r0], #8
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8000248: 3c08 subs r4, #8
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800024a: ea85 0501 eor.w r5, r5, r1
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800024e: ea86 0601 eor.w r6, r6, r1
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8000252: fa85 f547 uadd8 r5, r5, r7
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8000256: faa3 f587 sel r5, r3, r7
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800025a: fa86 f647 uadd8 r6, r6, r7
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800025e: faa5 f687 sel r6, r5, r7
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8000262: b98e cbnz r6, 8000288 <memchr+0x78>
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8000264: d1ee bne.n 8000244 <memchr+0x34>
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8000266: bcf0 pop {r4, r5, r6, r7}
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8000268: f001 01ff and.w r1, r1, #255 ; 0xff
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800026c: f002 0207 and.w r2, r2, #7
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8000270: b132 cbz r2, 8000280 <memchr+0x70>
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8000272: f810 3b01 ldrb.w r3, [r0], #1
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8000276: 3a01 subs r2, #1
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8000278: ea83 0301 eor.w r3, r3, r1
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800027c: b113 cbz r3, 8000284 <memchr+0x74>
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800027e: d1f8 bne.n 8000272 <memchr+0x62>
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8000280: 2000 movs r0, #0
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8000282: 4770 bx lr
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8000284: 3801 subs r0, #1
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8000286: 4770 bx lr
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8000288: 2d00 cmp r5, #0
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800028a: bf06 itte eq
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800028c: 4635 moveq r5, r6
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800028e: 3803 subeq r0, #3
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8000290: 3807 subne r0, #7
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8000292: f015 0f01 tst.w r5, #1
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8000296: d107 bne.n 80002a8 <memchr+0x98>
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8000298: 3001 adds r0, #1
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800029a: f415 7f80 tst.w r5, #256 ; 0x100
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800029e: bf02 ittt eq
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80002a0: 3001 addeq r0, #1
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80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
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80002a6: 3001 addeq r0, #1
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80002a8: bcf0 pop {r4, r5, r6, r7}
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80002aa: 3801 subs r0, #1
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80002ac: 4770 bx lr
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80002ae: bf00 nop
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080002b0 <__aeabi_uldivmod>:
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80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18>
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80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18>
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80002b4: 2900 cmp r1, #0
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80002b6: bf08 it eq
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80002b8: 2800 cmpeq r0, #0
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80002ba: bf1c itt ne
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80002bc: f04f 31ff movne.w r1, #4294967295
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80002c0: f04f 30ff movne.w r0, #4294967295
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80002c4: f000 b972 b.w 80005ac <__aeabi_idiv0>
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80002c8: f1ad 0c08 sub.w ip, sp, #8
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80002cc: e96d ce04 strd ip, lr, [sp, #-16]!
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80002d0: f000 f806 bl 80002e0 <__udivmoddi4>
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80002d4: f8dd e004 ldr.w lr, [sp, #4]
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80002d8: e9dd 2302 ldrd r2, r3, [sp, #8]
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80002dc: b004 add sp, #16
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80002de: 4770 bx lr
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080002e0 <__udivmoddi4>:
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80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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80002e4: 9e08 ldr r6, [sp, #32]
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80002e6: 4604 mov r4, r0
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80002e8: 4688 mov r8, r1
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80002ea: 2b00 cmp r3, #0
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80002ec: d14b bne.n 8000386 <__udivmoddi4+0xa6>
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80002ee: 428a cmp r2, r1
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80002f0: 4615 mov r5, r2
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80002f2: d967 bls.n 80003c4 <__udivmoddi4+0xe4>
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80002f4: fab2 f282 clz r2, r2
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80002f8: b14a cbz r2, 800030e <__udivmoddi4+0x2e>
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80002fa: f1c2 0720 rsb r7, r2, #32
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80002fe: fa01 f302 lsl.w r3, r1, r2
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8000302: fa20 f707 lsr.w r7, r0, r7
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8000306: 4095 lsls r5, r2
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8000308: ea47 0803 orr.w r8, r7, r3
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800030c: 4094 lsls r4, r2
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800030e: ea4f 4e15 mov.w lr, r5, lsr #16
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8000312: 0c23 lsrs r3, r4, #16
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8000314: fbb8 f7fe udiv r7, r8, lr
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8000318: fa1f fc85 uxth.w ip, r5
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800031c: fb0e 8817 mls r8, lr, r7, r8
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8000320: ea43 4308 orr.w r3, r3, r8, lsl #16
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8000324: fb07 f10c mul.w r1, r7, ip
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8000328: 4299 cmp r1, r3
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800032a: d909 bls.n 8000340 <__udivmoddi4+0x60>
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800032c: 18eb adds r3, r5, r3
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800032e: f107 30ff add.w r0, r7, #4294967295
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8000332: f080 811b bcs.w 800056c <__udivmoddi4+0x28c>
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8000336: 4299 cmp r1, r3
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8000338: f240 8118 bls.w 800056c <__udivmoddi4+0x28c>
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800033c: 3f02 subs r7, #2
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800033e: 442b add r3, r5
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8000340: 1a5b subs r3, r3, r1
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8000342: b2a4 uxth r4, r4
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8000344: fbb3 f0fe udiv r0, r3, lr
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8000348: fb0e 3310 mls r3, lr, r0, r3
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800034c: ea44 4403 orr.w r4, r4, r3, lsl #16
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8000350: fb00 fc0c mul.w ip, r0, ip
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8000354: 45a4 cmp ip, r4
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8000356: d909 bls.n 800036c <__udivmoddi4+0x8c>
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8000358: 192c adds r4, r5, r4
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800035a: f100 33ff add.w r3, r0, #4294967295
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800035e: f080 8107 bcs.w 8000570 <__udivmoddi4+0x290>
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8000362: 45a4 cmp ip, r4
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8000364: f240 8104 bls.w 8000570 <__udivmoddi4+0x290>
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8000368: 3802 subs r0, #2
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800036a: 442c add r4, r5
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800036c: ea40 4007 orr.w r0, r0, r7, lsl #16
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8000370: eba4 040c sub.w r4, r4, ip
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8000374: 2700 movs r7, #0
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8000376: b11e cbz r6, 8000380 <__udivmoddi4+0xa0>
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8000378: 40d4 lsrs r4, r2
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800037a: 2300 movs r3, #0
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800037c: e9c6 4300 strd r4, r3, [r6]
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8000380: 4639 mov r1, r7
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8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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8000386: 428b cmp r3, r1
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8000388: d909 bls.n 800039e <__udivmoddi4+0xbe>
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800038a: 2e00 cmp r6, #0
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800038c: f000 80eb beq.w 8000566 <__udivmoddi4+0x286>
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8000390: 2700 movs r7, #0
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8000392: e9c6 0100 strd r0, r1, [r6]
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8000396: 4638 mov r0, r7
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8000398: 4639 mov r1, r7
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800039a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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800039e: fab3 f783 clz r7, r3
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80003a2: 2f00 cmp r7, #0
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80003a4: d147 bne.n 8000436 <__udivmoddi4+0x156>
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80003a6: 428b cmp r3, r1
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80003a8: d302 bcc.n 80003b0 <__udivmoddi4+0xd0>
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80003aa: 4282 cmp r2, r0
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80003ac: f200 80fa bhi.w 80005a4 <__udivmoddi4+0x2c4>
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80003b0: 1a84 subs r4, r0, r2
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80003b2: eb61 0303 sbc.w r3, r1, r3
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80003b6: 2001 movs r0, #1
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80003b8: 4698 mov r8, r3
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80003ba: 2e00 cmp r6, #0
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80003bc: d0e0 beq.n 8000380 <__udivmoddi4+0xa0>
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80003be: e9c6 4800 strd r4, r8, [r6]
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80003c2: e7dd b.n 8000380 <__udivmoddi4+0xa0>
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80003c4: b902 cbnz r2, 80003c8 <__udivmoddi4+0xe8>
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80003c6: deff udf #255 ; 0xff
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80003c8: fab2 f282 clz r2, r2
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80003cc: 2a00 cmp r2, #0
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80003ce: f040 808f bne.w 80004f0 <__udivmoddi4+0x210>
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80003d2: 1b49 subs r1, r1, r5
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80003d4: ea4f 4e15 mov.w lr, r5, lsr #16
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80003d8: fa1f f885 uxth.w r8, r5
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80003dc: 2701 movs r7, #1
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80003de: fbb1 fcfe udiv ip, r1, lr
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80003e2: 0c23 lsrs r3, r4, #16
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80003e4: fb0e 111c mls r1, lr, ip, r1
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80003e8: ea43 4301 orr.w r3, r3, r1, lsl #16
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80003ec: fb08 f10c mul.w r1, r8, ip
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80003f0: 4299 cmp r1, r3
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80003f2: d907 bls.n 8000404 <__udivmoddi4+0x124>
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80003f4: 18eb adds r3, r5, r3
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80003f6: f10c 30ff add.w r0, ip, #4294967295
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80003fa: d202 bcs.n 8000402 <__udivmoddi4+0x122>
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80003fc: 4299 cmp r1, r3
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80003fe: f200 80cd bhi.w 800059c <__udivmoddi4+0x2bc>
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8000402: 4684 mov ip, r0
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8000404: 1a59 subs r1, r3, r1
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8000406: b2a3 uxth r3, r4
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8000408: fbb1 f0fe udiv r0, r1, lr
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800040c: fb0e 1410 mls r4, lr, r0, r1
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8000410: ea43 4404 orr.w r4, r3, r4, lsl #16
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8000414: fb08 f800 mul.w r8, r8, r0
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8000418: 45a0 cmp r8, r4
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800041a: d907 bls.n 800042c <__udivmoddi4+0x14c>
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800041c: 192c adds r4, r5, r4
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800041e: f100 33ff add.w r3, r0, #4294967295
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8000422: d202 bcs.n 800042a <__udivmoddi4+0x14a>
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8000424: 45a0 cmp r8, r4
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8000426: f200 80b6 bhi.w 8000596 <__udivmoddi4+0x2b6>
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800042a: 4618 mov r0, r3
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800042c: eba4 0408 sub.w r4, r4, r8
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8000430: ea40 400c orr.w r0, r0, ip, lsl #16
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8000434: e79f b.n 8000376 <__udivmoddi4+0x96>
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8000436: f1c7 0c20 rsb ip, r7, #32
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800043a: 40bb lsls r3, r7
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800043c: fa22 fe0c lsr.w lr, r2, ip
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8000440: ea4e 0e03 orr.w lr, lr, r3
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8000444: fa01 f407 lsl.w r4, r1, r7
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8000448: fa20 f50c lsr.w r5, r0, ip
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800044c: fa21 f30c lsr.w r3, r1, ip
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8000450: ea4f 481e mov.w r8, lr, lsr #16
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8000454: 4325 orrs r5, r4
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8000456: fbb3 f9f8 udiv r9, r3, r8
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800045a: 0c2c lsrs r4, r5, #16
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800045c: fb08 3319 mls r3, r8, r9, r3
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8000460: fa1f fa8e uxth.w sl, lr
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8000464: ea44 4303 orr.w r3, r4, r3, lsl #16
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8000468: fb09 f40a mul.w r4, r9, sl
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800046c: 429c cmp r4, r3
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800046e: fa02 f207 lsl.w r2, r2, r7
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8000472: fa00 f107 lsl.w r1, r0, r7
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8000476: d90b bls.n 8000490 <__udivmoddi4+0x1b0>
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8000478: eb1e 0303 adds.w r3, lr, r3
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800047c: f109 30ff add.w r0, r9, #4294967295
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8000480: f080 8087 bcs.w 8000592 <__udivmoddi4+0x2b2>
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8000484: 429c cmp r4, r3
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8000486: f240 8084 bls.w 8000592 <__udivmoddi4+0x2b2>
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800048a: f1a9 0902 sub.w r9, r9, #2
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800048e: 4473 add r3, lr
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8000490: 1b1b subs r3, r3, r4
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8000492: b2ad uxth r5, r5
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8000494: fbb3 f0f8 udiv r0, r3, r8
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8000498: fb08 3310 mls r3, r8, r0, r3
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800049c: ea45 4403 orr.w r4, r5, r3, lsl #16
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80004a0: fb00 fa0a mul.w sl, r0, sl
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80004a4: 45a2 cmp sl, r4
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80004a6: d908 bls.n 80004ba <__udivmoddi4+0x1da>
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80004a8: eb1e 0404 adds.w r4, lr, r4
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80004ac: f100 33ff add.w r3, r0, #4294967295
|
|
80004b0: d26b bcs.n 800058a <__udivmoddi4+0x2aa>
|
|
80004b2: 45a2 cmp sl, r4
|
|
80004b4: d969 bls.n 800058a <__udivmoddi4+0x2aa>
|
|
80004b6: 3802 subs r0, #2
|
|
80004b8: 4474 add r4, lr
|
|
80004ba: ea40 4009 orr.w r0, r0, r9, lsl #16
|
|
80004be: fba0 8902 umull r8, r9, r0, r2
|
|
80004c2: eba4 040a sub.w r4, r4, sl
|
|
80004c6: 454c cmp r4, r9
|
|
80004c8: 46c2 mov sl, r8
|
|
80004ca: 464b mov r3, r9
|
|
80004cc: d354 bcc.n 8000578 <__udivmoddi4+0x298>
|
|
80004ce: d051 beq.n 8000574 <__udivmoddi4+0x294>
|
|
80004d0: 2e00 cmp r6, #0
|
|
80004d2: d069 beq.n 80005a8 <__udivmoddi4+0x2c8>
|
|
80004d4: ebb1 050a subs.w r5, r1, sl
|
|
80004d8: eb64 0403 sbc.w r4, r4, r3
|
|
80004dc: fa04 fc0c lsl.w ip, r4, ip
|
|
80004e0: 40fd lsrs r5, r7
|
|
80004e2: 40fc lsrs r4, r7
|
|
80004e4: ea4c 0505 orr.w r5, ip, r5
|
|
80004e8: e9c6 5400 strd r5, r4, [r6]
|
|
80004ec: 2700 movs r7, #0
|
|
80004ee: e747 b.n 8000380 <__udivmoddi4+0xa0>
|
|
80004f0: f1c2 0320 rsb r3, r2, #32
|
|
80004f4: fa20 f703 lsr.w r7, r0, r3
|
|
80004f8: 4095 lsls r5, r2
|
|
80004fa: fa01 f002 lsl.w r0, r1, r2
|
|
80004fe: fa21 f303 lsr.w r3, r1, r3
|
|
8000502: ea4f 4e15 mov.w lr, r5, lsr #16
|
|
8000506: 4338 orrs r0, r7
|
|
8000508: 0c01 lsrs r1, r0, #16
|
|
800050a: fbb3 f7fe udiv r7, r3, lr
|
|
800050e: fa1f f885 uxth.w r8, r5
|
|
8000512: fb0e 3317 mls r3, lr, r7, r3
|
|
8000516: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
800051a: fb07 f308 mul.w r3, r7, r8
|
|
800051e: 428b cmp r3, r1
|
|
8000520: fa04 f402 lsl.w r4, r4, r2
|
|
8000524: d907 bls.n 8000536 <__udivmoddi4+0x256>
|
|
8000526: 1869 adds r1, r5, r1
|
|
8000528: f107 3cff add.w ip, r7, #4294967295
|
|
800052c: d22f bcs.n 800058e <__udivmoddi4+0x2ae>
|
|
800052e: 428b cmp r3, r1
|
|
8000530: d92d bls.n 800058e <__udivmoddi4+0x2ae>
|
|
8000532: 3f02 subs r7, #2
|
|
8000534: 4429 add r1, r5
|
|
8000536: 1acb subs r3, r1, r3
|
|
8000538: b281 uxth r1, r0
|
|
800053a: fbb3 f0fe udiv r0, r3, lr
|
|
800053e: fb0e 3310 mls r3, lr, r0, r3
|
|
8000542: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000546: fb00 f308 mul.w r3, r0, r8
|
|
800054a: 428b cmp r3, r1
|
|
800054c: d907 bls.n 800055e <__udivmoddi4+0x27e>
|
|
800054e: 1869 adds r1, r5, r1
|
|
8000550: f100 3cff add.w ip, r0, #4294967295
|
|
8000554: d217 bcs.n 8000586 <__udivmoddi4+0x2a6>
|
|
8000556: 428b cmp r3, r1
|
|
8000558: d915 bls.n 8000586 <__udivmoddi4+0x2a6>
|
|
800055a: 3802 subs r0, #2
|
|
800055c: 4429 add r1, r5
|
|
800055e: 1ac9 subs r1, r1, r3
|
|
8000560: ea40 4707 orr.w r7, r0, r7, lsl #16
|
|
8000564: e73b b.n 80003de <__udivmoddi4+0xfe>
|
|
8000566: 4637 mov r7, r6
|
|
8000568: 4630 mov r0, r6
|
|
800056a: e709 b.n 8000380 <__udivmoddi4+0xa0>
|
|
800056c: 4607 mov r7, r0
|
|
800056e: e6e7 b.n 8000340 <__udivmoddi4+0x60>
|
|
8000570: 4618 mov r0, r3
|
|
8000572: e6fb b.n 800036c <__udivmoddi4+0x8c>
|
|
8000574: 4541 cmp r1, r8
|
|
8000576: d2ab bcs.n 80004d0 <__udivmoddi4+0x1f0>
|
|
8000578: ebb8 0a02 subs.w sl, r8, r2
|
|
800057c: eb69 020e sbc.w r2, r9, lr
|
|
8000580: 3801 subs r0, #1
|
|
8000582: 4613 mov r3, r2
|
|
8000584: e7a4 b.n 80004d0 <__udivmoddi4+0x1f0>
|
|
8000586: 4660 mov r0, ip
|
|
8000588: e7e9 b.n 800055e <__udivmoddi4+0x27e>
|
|
800058a: 4618 mov r0, r3
|
|
800058c: e795 b.n 80004ba <__udivmoddi4+0x1da>
|
|
800058e: 4667 mov r7, ip
|
|
8000590: e7d1 b.n 8000536 <__udivmoddi4+0x256>
|
|
8000592: 4681 mov r9, r0
|
|
8000594: e77c b.n 8000490 <__udivmoddi4+0x1b0>
|
|
8000596: 3802 subs r0, #2
|
|
8000598: 442c add r4, r5
|
|
800059a: e747 b.n 800042c <__udivmoddi4+0x14c>
|
|
800059c: f1ac 0c02 sub.w ip, ip, #2
|
|
80005a0: 442b add r3, r5
|
|
80005a2: e72f b.n 8000404 <__udivmoddi4+0x124>
|
|
80005a4: 4638 mov r0, r7
|
|
80005a6: e708 b.n 80003ba <__udivmoddi4+0xda>
|
|
80005a8: 4637 mov r7, r6
|
|
80005aa: e6e9 b.n 8000380 <__udivmoddi4+0xa0>
|
|
|
|
080005ac <__aeabi_idiv0>:
|
|
80005ac: 4770 bx lr
|
|
80005ae: bf00 nop
|
|
|
|
080005b0 <vApplicationIdleHook>:
|
|
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
|
|
void vApplicationMallocFailedHook(void);
|
|
|
|
/* USER CODE BEGIN 2 */
|
|
__weak void vApplicationIdleHook( void )
|
|
{
|
|
80005b0: b480 push {r7}
|
|
80005b2: af00 add r7, sp, #0
|
|
specified, or call vTaskDelay()). If the application makes use of the
|
|
vTaskDelete() API function (as this demo application does) then it is also
|
|
important that vApplicationIdleHook() is permitted to return to its calling
|
|
function, because it is the responsibility of the idle task to clean up
|
|
memory allocated by the kernel to any task that has since been deleted. */
|
|
}
|
|
80005b4: bf00 nop
|
|
80005b6: 46bd mov sp, r7
|
|
80005b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005bc: 4770 bx lr
|
|
|
|
080005be <vApplicationStackOverflowHook>:
|
|
/* USER CODE END 2 */
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
|
|
{
|
|
80005be: b480 push {r7}
|
|
80005c0: b083 sub sp, #12
|
|
80005c2: af00 add r7, sp, #0
|
|
80005c4: 6078 str r0, [r7, #4]
|
|
80005c6: 6039 str r1, [r7, #0]
|
|
/* Run time stack overflow checking is performed if
|
|
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
|
|
called if a stack overflow is detected. */
|
|
}
|
|
80005c8: bf00 nop
|
|
80005ca: 370c adds r7, #12
|
|
80005cc: 46bd mov sp, r7
|
|
80005ce: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005d2: 4770 bx lr
|
|
|
|
080005d4 <vApplicationMallocFailedHook>:
|
|
/* USER CODE END 4 */
|
|
|
|
/* USER CODE BEGIN 5 */
|
|
__weak void vApplicationMallocFailedHook(void)
|
|
{
|
|
80005d4: b480 push {r7}
|
|
80005d6: af00 add r7, sp, #0
|
|
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
|
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
|
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
|
to query the size of free heap space that remains (although it does not
|
|
provide information on how the remaining heap might be fragmented). */
|
|
}
|
|
80005d8: bf00 nop
|
|
80005da: 46bd mov sp, r7
|
|
80005dc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80005e0: 4770 bx lr
|
|
...
|
|
|
|
080005e4 <vApplicationGetIdleTaskMemory>:
|
|
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
|
|
static StaticTask_t xIdleTaskTCBBuffer;
|
|
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
|
|
|
|
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
|
|
{
|
|
80005e4: b480 push {r7}
|
|
80005e6: b085 sub sp, #20
|
|
80005e8: af00 add r7, sp, #0
|
|
80005ea: 60f8 str r0, [r7, #12]
|
|
80005ec: 60b9 str r1, [r7, #8]
|
|
80005ee: 607a str r2, [r7, #4]
|
|
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
|
|
80005f0: 68fb ldr r3, [r7, #12]
|
|
80005f2: 4a07 ldr r2, [pc, #28] ; (8000610 <vApplicationGetIdleTaskMemory+0x2c>)
|
|
80005f4: 601a str r2, [r3, #0]
|
|
*ppxIdleTaskStackBuffer = &xIdleStack[0];
|
|
80005f6: 68bb ldr r3, [r7, #8]
|
|
80005f8: 4a06 ldr r2, [pc, #24] ; (8000614 <vApplicationGetIdleTaskMemory+0x30>)
|
|
80005fa: 601a str r2, [r3, #0]
|
|
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
|
80005fc: 687b ldr r3, [r7, #4]
|
|
80005fe: 2280 movs r2, #128 ; 0x80
|
|
8000600: 601a str r2, [r3, #0]
|
|
/* place for user code */
|
|
}
|
|
8000602: bf00 nop
|
|
8000604: 3714 adds r7, #20
|
|
8000606: 46bd mov sp, r7
|
|
8000608: f85d 7b04 ldr.w r7, [sp], #4
|
|
800060c: 4770 bx lr
|
|
800060e: bf00 nop
|
|
8000610: 20000104 .word 0x20000104
|
|
8000614: 2000015c .word 0x2000015c
|
|
|
|
08000618 <ft5336_Init>:
|
|
* from MCU to FT5336 : ie I2C channel initialization (if required).
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
|
|
* @retval None
|
|
*/
|
|
void ft5336_Init(uint16_t DeviceAddr)
|
|
{
|
|
8000618: b580 push {r7, lr}
|
|
800061a: b082 sub sp, #8
|
|
800061c: af00 add r7, sp, #0
|
|
800061e: 4603 mov r3, r0
|
|
8000620: 80fb strh r3, [r7, #6]
|
|
/* Wait at least 200ms after power up before accessing registers
|
|
* Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */
|
|
TS_IO_Delay(200);
|
|
8000622: 20c8 movs r0, #200 ; 0xc8
|
|
8000624: f002 fac4 bl 8002bb0 <TS_IO_Delay>
|
|
|
|
/* Initialize I2C link if needed */
|
|
ft5336_I2C_InitializeIfRequired();
|
|
8000628: f000 fa7a bl 8000b20 <ft5336_I2C_InitializeIfRequired>
|
|
}
|
|
800062c: bf00 nop
|
|
800062e: 3708 adds r7, #8
|
|
8000630: 46bd mov sp, r7
|
|
8000632: bd80 pop {r7, pc}
|
|
|
|
08000634 <ft5336_Reset>:
|
|
* @note : Not applicable to FT5336.
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
|
|
* @retval None
|
|
*/
|
|
void ft5336_Reset(uint16_t DeviceAddr)
|
|
{
|
|
8000634: b480 push {r7}
|
|
8000636: b083 sub sp, #12
|
|
8000638: af00 add r7, sp, #0
|
|
800063a: 4603 mov r3, r0
|
|
800063c: 80fb strh r3, [r7, #6]
|
|
/* Do nothing */
|
|
/* No software reset sequence available in FT5336 IC */
|
|
}
|
|
800063e: bf00 nop
|
|
8000640: 370c adds r7, #12
|
|
8000642: 46bd mov sp, r7
|
|
8000644: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000648: 4770 bx lr
|
|
|
|
0800064a <ft5336_ReadID>:
|
|
* able to read the FT5336 device ID, and verify this is a FT5336.
|
|
* @param DeviceAddr: I2C FT5336 Slave address.
|
|
* @retval The Device ID (two bytes).
|
|
*/
|
|
uint16_t ft5336_ReadID(uint16_t DeviceAddr)
|
|
{
|
|
800064a: b580 push {r7, lr}
|
|
800064c: b084 sub sp, #16
|
|
800064e: af00 add r7, sp, #0
|
|
8000650: 4603 mov r3, r0
|
|
8000652: 80fb strh r3, [r7, #6]
|
|
volatile uint8_t ucReadId = 0;
|
|
8000654: 2300 movs r3, #0
|
|
8000656: 737b strb r3, [r7, #13]
|
|
uint8_t nbReadAttempts = 0;
|
|
8000658: 2300 movs r3, #0
|
|
800065a: 73fb strb r3, [r7, #15]
|
|
uint8_t bFoundDevice = 0; /* Device not found by default */
|
|
800065c: 2300 movs r3, #0
|
|
800065e: 73bb strb r3, [r7, #14]
|
|
|
|
/* Initialize I2C link if needed */
|
|
ft5336_I2C_InitializeIfRequired();
|
|
8000660: f000 fa5e bl 8000b20 <ft5336_I2C_InitializeIfRequired>
|
|
|
|
/* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */
|
|
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
|
|
8000664: 2300 movs r3, #0
|
|
8000666: 73fb strb r3, [r7, #15]
|
|
8000668: e010 b.n 800068c <ft5336_ReadID+0x42>
|
|
{
|
|
/* Read register FT5336_CHIP_ID_REG as DeviceID detection */
|
|
ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG);
|
|
800066a: 88fb ldrh r3, [r7, #6]
|
|
800066c: b2db uxtb r3, r3
|
|
800066e: 21a8 movs r1, #168 ; 0xa8
|
|
8000670: 4618 mov r0, r3
|
|
8000672: f002 fa7f bl 8002b74 <TS_IO_Read>
|
|
8000676: 4603 mov r3, r0
|
|
8000678: 737b strb r3, [r7, #13]
|
|
|
|
/* Found the searched device ID ? */
|
|
if(ucReadId == FT5336_ID_VALUE)
|
|
800067a: 7b7b ldrb r3, [r7, #13]
|
|
800067c: b2db uxtb r3, r3
|
|
800067e: 2b51 cmp r3, #81 ; 0x51
|
|
8000680: d101 bne.n 8000686 <ft5336_ReadID+0x3c>
|
|
{
|
|
/* Set device as found */
|
|
bFoundDevice = 1;
|
|
8000682: 2301 movs r3, #1
|
|
8000684: 73bb strb r3, [r7, #14]
|
|
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
|
|
8000686: 7bfb ldrb r3, [r7, #15]
|
|
8000688: 3301 adds r3, #1
|
|
800068a: 73fb strb r3, [r7, #15]
|
|
800068c: 7bfb ldrb r3, [r7, #15]
|
|
800068e: 2b02 cmp r3, #2
|
|
8000690: d802 bhi.n 8000698 <ft5336_ReadID+0x4e>
|
|
8000692: 7bbb ldrb r3, [r7, #14]
|
|
8000694: 2b00 cmp r3, #0
|
|
8000696: d0e8 beq.n 800066a <ft5336_ReadID+0x20>
|
|
}
|
|
}
|
|
|
|
/* Return the device ID value */
|
|
return (ucReadId);
|
|
8000698: 7b7b ldrb r3, [r7, #13]
|
|
800069a: b2db uxtb r3, r3
|
|
800069c: b29b uxth r3, r3
|
|
}
|
|
800069e: 4618 mov r0, r3
|
|
80006a0: 3710 adds r7, #16
|
|
80006a2: 46bd mov sp, r7
|
|
80006a4: bd80 pop {r7, pc}
|
|
|
|
080006a6 <ft5336_TS_Start>:
|
|
* @brief Configures the touch Screen IC device to start detecting touches
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address).
|
|
* @retval None.
|
|
*/
|
|
void ft5336_TS_Start(uint16_t DeviceAddr)
|
|
{
|
|
80006a6: b580 push {r7, lr}
|
|
80006a8: b082 sub sp, #8
|
|
80006aa: af00 add r7, sp, #0
|
|
80006ac: 4603 mov r3, r0
|
|
80006ae: 80fb strh r3, [r7, #6]
|
|
/* Minimum static configuration of FT5336 */
|
|
FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr));
|
|
80006b0: 88fb ldrh r3, [r7, #6]
|
|
80006b2: 4618 mov r0, r3
|
|
80006b4: f000 fa44 bl 8000b40 <ft5336_TS_Configure>
|
|
|
|
/* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */
|
|
/* Note TS_INT is active low */
|
|
ft5336_TS_DisableIT(DeviceAddr);
|
|
80006b8: 88fb ldrh r3, [r7, #6]
|
|
80006ba: 4618 mov r0, r3
|
|
80006bc: f000 f932 bl 8000924 <ft5336_TS_DisableIT>
|
|
}
|
|
80006c0: bf00 nop
|
|
80006c2: 3708 adds r7, #8
|
|
80006c4: 46bd mov sp, r7
|
|
80006c6: bd80 pop {r7, pc}
|
|
|
|
080006c8 <ft5336_TS_DetectTouch>:
|
|
* variables).
|
|
* @param DeviceAddr: Device address on communication Bus.
|
|
* @retval : Number of active touches detected (can be 0, 1 or 2).
|
|
*/
|
|
uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr)
|
|
{
|
|
80006c8: b580 push {r7, lr}
|
|
80006ca: b084 sub sp, #16
|
|
80006cc: af00 add r7, sp, #0
|
|
80006ce: 4603 mov r3, r0
|
|
80006d0: 80fb strh r3, [r7, #6]
|
|
volatile uint8_t nbTouch = 0;
|
|
80006d2: 2300 movs r3, #0
|
|
80006d4: 73fb strb r3, [r7, #15]
|
|
|
|
/* Read register FT5336_TD_STAT_REG to check number of touches detection */
|
|
nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG);
|
|
80006d6: 88fb ldrh r3, [r7, #6]
|
|
80006d8: b2db uxtb r3, r3
|
|
80006da: 2102 movs r1, #2
|
|
80006dc: 4618 mov r0, r3
|
|
80006de: f002 fa49 bl 8002b74 <TS_IO_Read>
|
|
80006e2: 4603 mov r3, r0
|
|
80006e4: 73fb strb r3, [r7, #15]
|
|
nbTouch &= FT5336_TD_STAT_MASK;
|
|
80006e6: 7bfb ldrb r3, [r7, #15]
|
|
80006e8: b2db uxtb r3, r3
|
|
80006ea: f003 030f and.w r3, r3, #15
|
|
80006ee: b2db uxtb r3, r3
|
|
80006f0: 73fb strb r3, [r7, #15]
|
|
|
|
if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH)
|
|
80006f2: 7bfb ldrb r3, [r7, #15]
|
|
80006f4: b2db uxtb r3, r3
|
|
80006f6: 2b05 cmp r3, #5
|
|
80006f8: d901 bls.n 80006fe <ft5336_TS_DetectTouch+0x36>
|
|
{
|
|
/* If invalid number of touch detected, set it to zero */
|
|
nbTouch = 0;
|
|
80006fa: 2300 movs r3, #0
|
|
80006fc: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Update ft5336 driver internal global : current number of active touches */
|
|
ft5336_handle.currActiveTouchNb = nbTouch;
|
|
80006fe: 7bfb ldrb r3, [r7, #15]
|
|
8000700: b2da uxtb r2, r3
|
|
8000702: 4b05 ldr r3, [pc, #20] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
|
|
8000704: 705a strb r2, [r3, #1]
|
|
|
|
/* Reset current active touch index on which to work on */
|
|
ft5336_handle.currActiveTouchIdx = 0;
|
|
8000706: 4b04 ldr r3, [pc, #16] ; (8000718 <ft5336_TS_DetectTouch+0x50>)
|
|
8000708: 2200 movs r2, #0
|
|
800070a: 709a strb r2, [r3, #2]
|
|
|
|
return(nbTouch);
|
|
800070c: 7bfb ldrb r3, [r7, #15]
|
|
800070e: b2db uxtb r3, r3
|
|
}
|
|
8000710: 4618 mov r0, r3
|
|
8000712: 3710 adds r7, #16
|
|
8000714: 46bd mov sp, r7
|
|
8000716: bd80 pop {r7, pc}
|
|
8000718: 2000035c .word 0x2000035c
|
|
|
|
0800071c <ft5336_TS_GetXY>:
|
|
* @param X: Pointer to X position value
|
|
* @param Y: Pointer to Y position value
|
|
* @retval None.
|
|
*/
|
|
void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
|
|
{
|
|
800071c: b580 push {r7, lr}
|
|
800071e: b086 sub sp, #24
|
|
8000720: af00 add r7, sp, #0
|
|
8000722: 4603 mov r3, r0
|
|
8000724: 60b9 str r1, [r7, #8]
|
|
8000726: 607a str r2, [r7, #4]
|
|
8000728: 81fb strh r3, [r7, #14]
|
|
volatile uint8_t ucReadData = 0;
|
|
800072a: 2300 movs r3, #0
|
|
800072c: 74fb strb r3, [r7, #19]
|
|
static uint16_t coord;
|
|
uint8_t regAddressXLow = 0;
|
|
800072e: 2300 movs r3, #0
|
|
8000730: 75fb strb r3, [r7, #23]
|
|
uint8_t regAddressXHigh = 0;
|
|
8000732: 2300 movs r3, #0
|
|
8000734: 75bb strb r3, [r7, #22]
|
|
uint8_t regAddressYLow = 0;
|
|
8000736: 2300 movs r3, #0
|
|
8000738: 757b strb r3, [r7, #21]
|
|
uint8_t regAddressYHigh = 0;
|
|
800073a: 2300 movs r3, #0
|
|
800073c: 753b strb r3, [r7, #20]
|
|
|
|
if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb)
|
|
800073e: 4b6d ldr r3, [pc, #436] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
|
|
8000740: 789a ldrb r2, [r3, #2]
|
|
8000742: 4b6c ldr r3, [pc, #432] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
|
|
8000744: 785b ldrb r3, [r3, #1]
|
|
8000746: 429a cmp r2, r3
|
|
8000748: f080 80cf bcs.w 80008ea <ft5336_TS_GetXY+0x1ce>
|
|
{
|
|
switch(ft5336_handle.currActiveTouchIdx)
|
|
800074c: 4b69 ldr r3, [pc, #420] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
|
|
800074e: 789b ldrb r3, [r3, #2]
|
|
8000750: 2b09 cmp r3, #9
|
|
8000752: d871 bhi.n 8000838 <ft5336_TS_GetXY+0x11c>
|
|
8000754: a201 add r2, pc, #4 ; (adr r2, 800075c <ft5336_TS_GetXY+0x40>)
|
|
8000756: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800075a: bf00 nop
|
|
800075c: 08000785 .word 0x08000785
|
|
8000760: 08000797 .word 0x08000797
|
|
8000764: 080007a9 .word 0x080007a9
|
|
8000768: 080007bb .word 0x080007bb
|
|
800076c: 080007cd .word 0x080007cd
|
|
8000770: 080007df .word 0x080007df
|
|
8000774: 080007f1 .word 0x080007f1
|
|
8000778: 08000803 .word 0x08000803
|
|
800077c: 08000815 .word 0x08000815
|
|
8000780: 08000827 .word 0x08000827
|
|
{
|
|
case 0 :
|
|
regAddressXLow = FT5336_P1_XL_REG;
|
|
8000784: 2304 movs r3, #4
|
|
8000786: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P1_XH_REG;
|
|
8000788: 2303 movs r3, #3
|
|
800078a: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P1_YL_REG;
|
|
800078c: 2306 movs r3, #6
|
|
800078e: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P1_YH_REG;
|
|
8000790: 2305 movs r3, #5
|
|
8000792: 753b strb r3, [r7, #20]
|
|
break;
|
|
8000794: e051 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 1 :
|
|
regAddressXLow = FT5336_P2_XL_REG;
|
|
8000796: 230a movs r3, #10
|
|
8000798: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P2_XH_REG;
|
|
800079a: 2309 movs r3, #9
|
|
800079c: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P2_YL_REG;
|
|
800079e: 230c movs r3, #12
|
|
80007a0: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P2_YH_REG;
|
|
80007a2: 230b movs r3, #11
|
|
80007a4: 753b strb r3, [r7, #20]
|
|
break;
|
|
80007a6: e048 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 2 :
|
|
regAddressXLow = FT5336_P3_XL_REG;
|
|
80007a8: 2310 movs r3, #16
|
|
80007aa: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P3_XH_REG;
|
|
80007ac: 230f movs r3, #15
|
|
80007ae: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P3_YL_REG;
|
|
80007b0: 2312 movs r3, #18
|
|
80007b2: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P3_YH_REG;
|
|
80007b4: 2311 movs r3, #17
|
|
80007b6: 753b strb r3, [r7, #20]
|
|
break;
|
|
80007b8: e03f b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 3 :
|
|
regAddressXLow = FT5336_P4_XL_REG;
|
|
80007ba: 2316 movs r3, #22
|
|
80007bc: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P4_XH_REG;
|
|
80007be: 2315 movs r3, #21
|
|
80007c0: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P4_YL_REG;
|
|
80007c2: 2318 movs r3, #24
|
|
80007c4: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P4_YH_REG;
|
|
80007c6: 2317 movs r3, #23
|
|
80007c8: 753b strb r3, [r7, #20]
|
|
break;
|
|
80007ca: e036 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 4 :
|
|
regAddressXLow = FT5336_P5_XL_REG;
|
|
80007cc: 231c movs r3, #28
|
|
80007ce: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P5_XH_REG;
|
|
80007d0: 231b movs r3, #27
|
|
80007d2: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P5_YL_REG;
|
|
80007d4: 231e movs r3, #30
|
|
80007d6: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P5_YH_REG;
|
|
80007d8: 231d movs r3, #29
|
|
80007da: 753b strb r3, [r7, #20]
|
|
break;
|
|
80007dc: e02d b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 5 :
|
|
regAddressXLow = FT5336_P6_XL_REG;
|
|
80007de: 2322 movs r3, #34 ; 0x22
|
|
80007e0: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P6_XH_REG;
|
|
80007e2: 2321 movs r3, #33 ; 0x21
|
|
80007e4: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P6_YL_REG;
|
|
80007e6: 2324 movs r3, #36 ; 0x24
|
|
80007e8: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P6_YH_REG;
|
|
80007ea: 2323 movs r3, #35 ; 0x23
|
|
80007ec: 753b strb r3, [r7, #20]
|
|
break;
|
|
80007ee: e024 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 6 :
|
|
regAddressXLow = FT5336_P7_XL_REG;
|
|
80007f0: 2328 movs r3, #40 ; 0x28
|
|
80007f2: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P7_XH_REG;
|
|
80007f4: 2327 movs r3, #39 ; 0x27
|
|
80007f6: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P7_YL_REG;
|
|
80007f8: 232a movs r3, #42 ; 0x2a
|
|
80007fa: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P7_YH_REG;
|
|
80007fc: 2329 movs r3, #41 ; 0x29
|
|
80007fe: 753b strb r3, [r7, #20]
|
|
break;
|
|
8000800: e01b b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 7 :
|
|
regAddressXLow = FT5336_P8_XL_REG;
|
|
8000802: 232e movs r3, #46 ; 0x2e
|
|
8000804: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P8_XH_REG;
|
|
8000806: 232d movs r3, #45 ; 0x2d
|
|
8000808: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P8_YL_REG;
|
|
800080a: 2330 movs r3, #48 ; 0x30
|
|
800080c: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P8_YH_REG;
|
|
800080e: 232f movs r3, #47 ; 0x2f
|
|
8000810: 753b strb r3, [r7, #20]
|
|
break;
|
|
8000812: e012 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 8 :
|
|
regAddressXLow = FT5336_P9_XL_REG;
|
|
8000814: 2334 movs r3, #52 ; 0x34
|
|
8000816: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P9_XH_REG;
|
|
8000818: 2333 movs r3, #51 ; 0x33
|
|
800081a: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P9_YL_REG;
|
|
800081c: 2336 movs r3, #54 ; 0x36
|
|
800081e: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P9_YH_REG;
|
|
8000820: 2335 movs r3, #53 ; 0x35
|
|
8000822: 753b strb r3, [r7, #20]
|
|
break;
|
|
8000824: e009 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
case 9 :
|
|
regAddressXLow = FT5336_P10_XL_REG;
|
|
8000826: 233a movs r3, #58 ; 0x3a
|
|
8000828: 75fb strb r3, [r7, #23]
|
|
regAddressXHigh = FT5336_P10_XH_REG;
|
|
800082a: 2339 movs r3, #57 ; 0x39
|
|
800082c: 75bb strb r3, [r7, #22]
|
|
regAddressYLow = FT5336_P10_YL_REG;
|
|
800082e: 233c movs r3, #60 ; 0x3c
|
|
8000830: 757b strb r3, [r7, #21]
|
|
regAddressYHigh = FT5336_P10_YH_REG;
|
|
8000832: 233b movs r3, #59 ; 0x3b
|
|
8000834: 753b strb r3, [r7, #20]
|
|
break;
|
|
8000836: e000 b.n 800083a <ft5336_TS_GetXY+0x11e>
|
|
|
|
default :
|
|
break;
|
|
8000838: bf00 nop
|
|
|
|
} /* end switch(ft5336_handle.currActiveTouchIdx) */
|
|
|
|
/* Read low part of X position */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow);
|
|
800083a: 89fb ldrh r3, [r7, #14]
|
|
800083c: b2db uxtb r3, r3
|
|
800083e: 7dfa ldrb r2, [r7, #23]
|
|
8000840: 4611 mov r1, r2
|
|
8000842: 4618 mov r0, r3
|
|
8000844: f002 f996 bl 8002b74 <TS_IO_Read>
|
|
8000848: 4603 mov r3, r0
|
|
800084a: 74fb strb r3, [r7, #19]
|
|
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
|
|
800084c: 7cfb ldrb r3, [r7, #19]
|
|
800084e: b2db uxtb r3, r3
|
|
8000850: b29a uxth r2, r3
|
|
8000852: 4b29 ldr r3, [pc, #164] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
8000854: 801a strh r2, [r3, #0]
|
|
|
|
/* Read high part of X position */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
|
|
8000856: 89fb ldrh r3, [r7, #14]
|
|
8000858: b2db uxtb r3, r3
|
|
800085a: 7dba ldrb r2, [r7, #22]
|
|
800085c: 4611 mov r1, r2
|
|
800085e: 4618 mov r0, r3
|
|
8000860: f002 f988 bl 8002b74 <TS_IO_Read>
|
|
8000864: 4603 mov r3, r0
|
|
8000866: 74fb strb r3, [r7, #19]
|
|
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
|
|
8000868: 7cfb ldrb r3, [r7, #19]
|
|
800086a: b2db uxtb r3, r3
|
|
800086c: 021b lsls r3, r3, #8
|
|
800086e: f403 6370 and.w r3, r3, #3840 ; 0xf00
|
|
8000872: b21a sxth r2, r3
|
|
8000874: 4b20 ldr r3, [pc, #128] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
8000876: 881b ldrh r3, [r3, #0]
|
|
8000878: b21b sxth r3, r3
|
|
800087a: 4313 orrs r3, r2
|
|
800087c: b21b sxth r3, r3
|
|
800087e: b29a uxth r2, r3
|
|
8000880: 4b1d ldr r3, [pc, #116] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
8000882: 801a strh r2, [r3, #0]
|
|
|
|
/* Send back ready X position to caller */
|
|
*X = coord;
|
|
8000884: 4b1c ldr r3, [pc, #112] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
8000886: 881a ldrh r2, [r3, #0]
|
|
8000888: 68bb ldr r3, [r7, #8]
|
|
800088a: 801a strh r2, [r3, #0]
|
|
|
|
/* Read low part of Y position */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow);
|
|
800088c: 89fb ldrh r3, [r7, #14]
|
|
800088e: b2db uxtb r3, r3
|
|
8000890: 7d7a ldrb r2, [r7, #21]
|
|
8000892: 4611 mov r1, r2
|
|
8000894: 4618 mov r0, r3
|
|
8000896: f002 f96d bl 8002b74 <TS_IO_Read>
|
|
800089a: 4603 mov r3, r0
|
|
800089c: 74fb strb r3, [r7, #19]
|
|
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
|
|
800089e: 7cfb ldrb r3, [r7, #19]
|
|
80008a0: b2db uxtb r3, r3
|
|
80008a2: b29a uxth r2, r3
|
|
80008a4: 4b14 ldr r3, [pc, #80] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
80008a6: 801a strh r2, [r3, #0]
|
|
|
|
/* Read high part of Y position */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh);
|
|
80008a8: 89fb ldrh r3, [r7, #14]
|
|
80008aa: b2db uxtb r3, r3
|
|
80008ac: 7d3a ldrb r2, [r7, #20]
|
|
80008ae: 4611 mov r1, r2
|
|
80008b0: 4618 mov r0, r3
|
|
80008b2: f002 f95f bl 8002b74 <TS_IO_Read>
|
|
80008b6: 4603 mov r3, r0
|
|
80008b8: 74fb strb r3, [r7, #19]
|
|
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
|
|
80008ba: 7cfb ldrb r3, [r7, #19]
|
|
80008bc: b2db uxtb r3, r3
|
|
80008be: 021b lsls r3, r3, #8
|
|
80008c0: f403 6370 and.w r3, r3, #3840 ; 0xf00
|
|
80008c4: b21a sxth r2, r3
|
|
80008c6: 4b0c ldr r3, [pc, #48] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
80008c8: 881b ldrh r3, [r3, #0]
|
|
80008ca: b21b sxth r3, r3
|
|
80008cc: 4313 orrs r3, r2
|
|
80008ce: b21b sxth r3, r3
|
|
80008d0: b29a uxth r2, r3
|
|
80008d2: 4b09 ldr r3, [pc, #36] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
80008d4: 801a strh r2, [r3, #0]
|
|
|
|
/* Send back ready Y position to caller */
|
|
*Y = coord;
|
|
80008d6: 4b08 ldr r3, [pc, #32] ; (80008f8 <ft5336_TS_GetXY+0x1dc>)
|
|
80008d8: 881a ldrh r2, [r3, #0]
|
|
80008da: 687b ldr r3, [r7, #4]
|
|
80008dc: 801a strh r2, [r3, #0]
|
|
|
|
ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */
|
|
80008de: 4b05 ldr r3, [pc, #20] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
|
|
80008e0: 789b ldrb r3, [r3, #2]
|
|
80008e2: 3301 adds r3, #1
|
|
80008e4: b2da uxtb r2, r3
|
|
80008e6: 4b03 ldr r3, [pc, #12] ; (80008f4 <ft5336_TS_GetXY+0x1d8>)
|
|
80008e8: 709a strb r2, [r3, #2]
|
|
|
|
} /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */
|
|
}
|
|
80008ea: bf00 nop
|
|
80008ec: 3718 adds r7, #24
|
|
80008ee: 46bd mov sp, r7
|
|
80008f0: bd80 pop {r7, pc}
|
|
80008f2: bf00 nop
|
|
80008f4: 2000035c .word 0x2000035c
|
|
80008f8: 20000360 .word 0x20000360
|
|
|
|
080008fc <ft5336_TS_EnableIT>:
|
|
* connected to MCU as EXTI.
|
|
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
|
|
* @retval None
|
|
*/
|
|
void ft5336_TS_EnableIT(uint16_t DeviceAddr)
|
|
{
|
|
80008fc: b580 push {r7, lr}
|
|
80008fe: b084 sub sp, #16
|
|
8000900: af00 add r7, sp, #0
|
|
8000902: 4603 mov r3, r0
|
|
8000904: 80fb strh r3, [r7, #6]
|
|
uint8_t regValue = 0;
|
|
8000906: 2300 movs r3, #0
|
|
8000908: 73fb strb r3, [r7, #15]
|
|
regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
|
|
800090a: 2301 movs r3, #1
|
|
800090c: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set interrupt trigger mode in FT5336_GMODE_REG */
|
|
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
|
|
800090e: 88fb ldrh r3, [r7, #6]
|
|
8000910: b2db uxtb r3, r3
|
|
8000912: 7bfa ldrb r2, [r7, #15]
|
|
8000914: 21a4 movs r1, #164 ; 0xa4
|
|
8000916: 4618 mov r0, r3
|
|
8000918: f002 f912 bl 8002b40 <TS_IO_Write>
|
|
}
|
|
800091c: bf00 nop
|
|
800091e: 3710 adds r7, #16
|
|
8000920: 46bd mov sp, r7
|
|
8000922: bd80 pop {r7, pc}
|
|
|
|
08000924 <ft5336_TS_DisableIT>:
|
|
* connected to MCU as EXTI.
|
|
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
|
|
* @retval None
|
|
*/
|
|
void ft5336_TS_DisableIT(uint16_t DeviceAddr)
|
|
{
|
|
8000924: b580 push {r7, lr}
|
|
8000926: b084 sub sp, #16
|
|
8000928: af00 add r7, sp, #0
|
|
800092a: 4603 mov r3, r0
|
|
800092c: 80fb strh r3, [r7, #6]
|
|
uint8_t regValue = 0;
|
|
800092e: 2300 movs r3, #0
|
|
8000930: 73fb strb r3, [r7, #15]
|
|
regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
|
|
8000932: 2300 movs r3, #0
|
|
8000934: 73fb strb r3, [r7, #15]
|
|
|
|
/* Set interrupt polling mode in FT5336_GMODE_REG */
|
|
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
|
|
8000936: 88fb ldrh r3, [r7, #6]
|
|
8000938: b2db uxtb r3, r3
|
|
800093a: 7bfa ldrb r2, [r7, #15]
|
|
800093c: 21a4 movs r1, #164 ; 0xa4
|
|
800093e: 4618 mov r0, r3
|
|
8000940: f002 f8fe bl 8002b40 <TS_IO_Write>
|
|
}
|
|
8000944: bf00 nop
|
|
8000946: 3710 adds r7, #16
|
|
8000948: 46bd mov sp, r7
|
|
800094a: bd80 pop {r7, pc}
|
|
|
|
0800094c <ft5336_TS_ITStatus>:
|
|
* @note : This feature is not applicable to FT5336.
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
|
|
* @retval TS interrupts status : always return 0 here
|
|
*/
|
|
uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr)
|
|
{
|
|
800094c: b480 push {r7}
|
|
800094e: b083 sub sp, #12
|
|
8000950: af00 add r7, sp, #0
|
|
8000952: 4603 mov r3, r0
|
|
8000954: 80fb strh r3, [r7, #6]
|
|
/* Always return 0 as feature not applicable to FT5336 */
|
|
return 0;
|
|
8000956: 2300 movs r3, #0
|
|
}
|
|
8000958: 4618 mov r0, r3
|
|
800095a: 370c adds r7, #12
|
|
800095c: 46bd mov sp, r7
|
|
800095e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000962: 4770 bx lr
|
|
|
|
08000964 <ft5336_TS_ClearIT>:
|
|
* @note : This feature is not applicable to FT5336.
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
|
|
* @retval None
|
|
*/
|
|
void ft5336_TS_ClearIT(uint16_t DeviceAddr)
|
|
{
|
|
8000964: b480 push {r7}
|
|
8000966: b083 sub sp, #12
|
|
8000968: af00 add r7, sp, #0
|
|
800096a: 4603 mov r3, r0
|
|
800096c: 80fb strh r3, [r7, #6]
|
|
/* Nothing to be done here for FT5336 */
|
|
}
|
|
800096e: bf00 nop
|
|
8000970: 370c adds r7, #12
|
|
8000972: 46bd mov sp, r7
|
|
8000974: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000978: 4770 bx lr
|
|
|
|
0800097a <ft5336_TS_GetGestureID>:
|
|
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
|
|
* @param pGestureId : Pointer to get last touch gesture Identification.
|
|
* @retval None.
|
|
*/
|
|
void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
|
|
{
|
|
800097a: b580 push {r7, lr}
|
|
800097c: b084 sub sp, #16
|
|
800097e: af00 add r7, sp, #0
|
|
8000980: 4603 mov r3, r0
|
|
8000982: 6039 str r1, [r7, #0]
|
|
8000984: 80fb strh r3, [r7, #6]
|
|
volatile uint8_t ucReadData = 0;
|
|
8000986: 2300 movs r3, #0
|
|
8000988: 73fb strb r3, [r7, #15]
|
|
|
|
ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG);
|
|
800098a: 88fb ldrh r3, [r7, #6]
|
|
800098c: b2db uxtb r3, r3
|
|
800098e: 2101 movs r1, #1
|
|
8000990: 4618 mov r0, r3
|
|
8000992: f002 f8ef bl 8002b74 <TS_IO_Read>
|
|
8000996: 4603 mov r3, r0
|
|
8000998: 73fb strb r3, [r7, #15]
|
|
|
|
* pGestureId = ucReadData;
|
|
800099a: 7bfb ldrb r3, [r7, #15]
|
|
800099c: b2db uxtb r3, r3
|
|
800099e: 461a mov r2, r3
|
|
80009a0: 683b ldr r3, [r7, #0]
|
|
80009a2: 601a str r2, [r3, #0]
|
|
}
|
|
80009a4: bf00 nop
|
|
80009a6: 3710 adds r7, #16
|
|
80009a8: 46bd mov sp, r7
|
|
80009aa: bd80 pop {r7, pc}
|
|
|
|
080009ac <ft5336_TS_GetTouchInfo>:
|
|
void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr,
|
|
uint32_t touchIdx,
|
|
uint32_t * pWeight,
|
|
uint32_t * pArea,
|
|
uint32_t * pEvent)
|
|
{
|
|
80009ac: b580 push {r7, lr}
|
|
80009ae: b086 sub sp, #24
|
|
80009b0: af00 add r7, sp, #0
|
|
80009b2: 60b9 str r1, [r7, #8]
|
|
80009b4: 607a str r2, [r7, #4]
|
|
80009b6: 603b str r3, [r7, #0]
|
|
80009b8: 4603 mov r3, r0
|
|
80009ba: 81fb strh r3, [r7, #14]
|
|
volatile uint8_t ucReadData = 0;
|
|
80009bc: 2300 movs r3, #0
|
|
80009be: 753b strb r3, [r7, #20]
|
|
uint8_t regAddressXHigh = 0;
|
|
80009c0: 2300 movs r3, #0
|
|
80009c2: 75fb strb r3, [r7, #23]
|
|
uint8_t regAddressPWeight = 0;
|
|
80009c4: 2300 movs r3, #0
|
|
80009c6: 75bb strb r3, [r7, #22]
|
|
uint8_t regAddressPMisc = 0;
|
|
80009c8: 2300 movs r3, #0
|
|
80009ca: 757b strb r3, [r7, #21]
|
|
|
|
if(touchIdx < ft5336_handle.currActiveTouchNb)
|
|
80009cc: 4b4d ldr r3, [pc, #308] ; (8000b04 <ft5336_TS_GetTouchInfo+0x158>)
|
|
80009ce: 785b ldrb r3, [r3, #1]
|
|
80009d0: 461a mov r2, r3
|
|
80009d2: 68bb ldr r3, [r7, #8]
|
|
80009d4: 4293 cmp r3, r2
|
|
80009d6: f080 8090 bcs.w 8000afa <ft5336_TS_GetTouchInfo+0x14e>
|
|
{
|
|
switch(touchIdx)
|
|
80009da: 68bb ldr r3, [r7, #8]
|
|
80009dc: 2b09 cmp r3, #9
|
|
80009de: d85d bhi.n 8000a9c <ft5336_TS_GetTouchInfo+0xf0>
|
|
80009e0: a201 add r2, pc, #4 ; (adr r2, 80009e8 <ft5336_TS_GetTouchInfo+0x3c>)
|
|
80009e2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80009e6: bf00 nop
|
|
80009e8: 08000a11 .word 0x08000a11
|
|
80009ec: 08000a1f .word 0x08000a1f
|
|
80009f0: 08000a2d .word 0x08000a2d
|
|
80009f4: 08000a3b .word 0x08000a3b
|
|
80009f8: 08000a49 .word 0x08000a49
|
|
80009fc: 08000a57 .word 0x08000a57
|
|
8000a00: 08000a65 .word 0x08000a65
|
|
8000a04: 08000a73 .word 0x08000a73
|
|
8000a08: 08000a81 .word 0x08000a81
|
|
8000a0c: 08000a8f .word 0x08000a8f
|
|
{
|
|
case 0 :
|
|
regAddressXHigh = FT5336_P1_XH_REG;
|
|
8000a10: 2303 movs r3, #3
|
|
8000a12: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P1_WEIGHT_REG;
|
|
8000a14: 2307 movs r3, #7
|
|
8000a16: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P1_MISC_REG;
|
|
8000a18: 2308 movs r3, #8
|
|
8000a1a: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a1c: e03f b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 1 :
|
|
regAddressXHigh = FT5336_P2_XH_REG;
|
|
8000a1e: 2309 movs r3, #9
|
|
8000a20: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P2_WEIGHT_REG;
|
|
8000a22: 230d movs r3, #13
|
|
8000a24: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P2_MISC_REG;
|
|
8000a26: 230e movs r3, #14
|
|
8000a28: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a2a: e038 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 2 :
|
|
regAddressXHigh = FT5336_P3_XH_REG;
|
|
8000a2c: 230f movs r3, #15
|
|
8000a2e: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P3_WEIGHT_REG;
|
|
8000a30: 2313 movs r3, #19
|
|
8000a32: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P3_MISC_REG;
|
|
8000a34: 2314 movs r3, #20
|
|
8000a36: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a38: e031 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 3 :
|
|
regAddressXHigh = FT5336_P4_XH_REG;
|
|
8000a3a: 2315 movs r3, #21
|
|
8000a3c: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P4_WEIGHT_REG;
|
|
8000a3e: 2319 movs r3, #25
|
|
8000a40: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P4_MISC_REG;
|
|
8000a42: 231a movs r3, #26
|
|
8000a44: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a46: e02a b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 4 :
|
|
regAddressXHigh = FT5336_P5_XH_REG;
|
|
8000a48: 231b movs r3, #27
|
|
8000a4a: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P5_WEIGHT_REG;
|
|
8000a4c: 231f movs r3, #31
|
|
8000a4e: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P5_MISC_REG;
|
|
8000a50: 2320 movs r3, #32
|
|
8000a52: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a54: e023 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 5 :
|
|
regAddressXHigh = FT5336_P6_XH_REG;
|
|
8000a56: 2321 movs r3, #33 ; 0x21
|
|
8000a58: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P6_WEIGHT_REG;
|
|
8000a5a: 2325 movs r3, #37 ; 0x25
|
|
8000a5c: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P6_MISC_REG;
|
|
8000a5e: 2326 movs r3, #38 ; 0x26
|
|
8000a60: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a62: e01c b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 6 :
|
|
regAddressXHigh = FT5336_P7_XH_REG;
|
|
8000a64: 2327 movs r3, #39 ; 0x27
|
|
8000a66: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P7_WEIGHT_REG;
|
|
8000a68: 232b movs r3, #43 ; 0x2b
|
|
8000a6a: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P7_MISC_REG;
|
|
8000a6c: 232c movs r3, #44 ; 0x2c
|
|
8000a6e: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a70: e015 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 7 :
|
|
regAddressXHigh = FT5336_P8_XH_REG;
|
|
8000a72: 232d movs r3, #45 ; 0x2d
|
|
8000a74: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P8_WEIGHT_REG;
|
|
8000a76: 2331 movs r3, #49 ; 0x31
|
|
8000a78: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P8_MISC_REG;
|
|
8000a7a: 2332 movs r3, #50 ; 0x32
|
|
8000a7c: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a7e: e00e b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 8 :
|
|
regAddressXHigh = FT5336_P9_XH_REG;
|
|
8000a80: 2333 movs r3, #51 ; 0x33
|
|
8000a82: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P9_WEIGHT_REG;
|
|
8000a84: 2337 movs r3, #55 ; 0x37
|
|
8000a86: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P9_MISC_REG;
|
|
8000a88: 2338 movs r3, #56 ; 0x38
|
|
8000a8a: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a8c: e007 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
case 9 :
|
|
regAddressXHigh = FT5336_P10_XH_REG;
|
|
8000a8e: 2339 movs r3, #57 ; 0x39
|
|
8000a90: 75fb strb r3, [r7, #23]
|
|
regAddressPWeight = FT5336_P10_WEIGHT_REG;
|
|
8000a92: 233d movs r3, #61 ; 0x3d
|
|
8000a94: 75bb strb r3, [r7, #22]
|
|
regAddressPMisc = FT5336_P10_MISC_REG;
|
|
8000a96: 233e movs r3, #62 ; 0x3e
|
|
8000a98: 757b strb r3, [r7, #21]
|
|
break;
|
|
8000a9a: e000 b.n 8000a9e <ft5336_TS_GetTouchInfo+0xf2>
|
|
|
|
default :
|
|
break;
|
|
8000a9c: bf00 nop
|
|
|
|
} /* end switch(touchIdx) */
|
|
|
|
/* Read Event Id of touch index */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
|
|
8000a9e: 89fb ldrh r3, [r7, #14]
|
|
8000aa0: b2db uxtb r3, r3
|
|
8000aa2: 7dfa ldrb r2, [r7, #23]
|
|
8000aa4: 4611 mov r1, r2
|
|
8000aa6: 4618 mov r0, r3
|
|
8000aa8: f002 f864 bl 8002b74 <TS_IO_Read>
|
|
8000aac: 4603 mov r3, r0
|
|
8000aae: 753b strb r3, [r7, #20]
|
|
* pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT;
|
|
8000ab0: 7d3b ldrb r3, [r7, #20]
|
|
8000ab2: b2db uxtb r3, r3
|
|
8000ab4: 119b asrs r3, r3, #6
|
|
8000ab6: f003 0203 and.w r2, r3, #3
|
|
8000aba: 6a3b ldr r3, [r7, #32]
|
|
8000abc: 601a str r2, [r3, #0]
|
|
|
|
/* Read weight of touch index */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight);
|
|
8000abe: 89fb ldrh r3, [r7, #14]
|
|
8000ac0: b2db uxtb r3, r3
|
|
8000ac2: 7dba ldrb r2, [r7, #22]
|
|
8000ac4: 4611 mov r1, r2
|
|
8000ac6: 4618 mov r0, r3
|
|
8000ac8: f002 f854 bl 8002b74 <TS_IO_Read>
|
|
8000acc: 4603 mov r3, r0
|
|
8000ace: 753b strb r3, [r7, #20]
|
|
* pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT;
|
|
8000ad0: 7d3b ldrb r3, [r7, #20]
|
|
8000ad2: b2db uxtb r3, r3
|
|
8000ad4: 461a mov r2, r3
|
|
8000ad6: 687b ldr r3, [r7, #4]
|
|
8000ad8: 601a str r2, [r3, #0]
|
|
|
|
/* Read area of touch index */
|
|
ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc);
|
|
8000ada: 89fb ldrh r3, [r7, #14]
|
|
8000adc: b2db uxtb r3, r3
|
|
8000ade: 7d7a ldrb r2, [r7, #21]
|
|
8000ae0: 4611 mov r1, r2
|
|
8000ae2: 4618 mov r0, r3
|
|
8000ae4: f002 f846 bl 8002b74 <TS_IO_Read>
|
|
8000ae8: 4603 mov r3, r0
|
|
8000aea: 753b strb r3, [r7, #20]
|
|
* pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT;
|
|
8000aec: 7d3b ldrb r3, [r7, #20]
|
|
8000aee: b2db uxtb r3, r3
|
|
8000af0: 111b asrs r3, r3, #4
|
|
8000af2: f003 0204 and.w r2, r3, #4
|
|
8000af6: 683b ldr r3, [r7, #0]
|
|
8000af8: 601a str r2, [r3, #0]
|
|
|
|
} /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */
|
|
}
|
|
8000afa: bf00 nop
|
|
8000afc: 3718 adds r7, #24
|
|
8000afe: 46bd mov sp, r7
|
|
8000b00: bd80 pop {r7, pc}
|
|
8000b02: bf00 nop
|
|
8000b04: 2000035c .word 0x2000035c
|
|
|
|
08000b08 <ft5336_Get_I2C_InitializedStatus>:
|
|
* @brief Return the status of I2C was initialized or not.
|
|
* @param None.
|
|
* @retval : I2C initialization status.
|
|
*/
|
|
static uint8_t ft5336_Get_I2C_InitializedStatus(void)
|
|
{
|
|
8000b08: b480 push {r7}
|
|
8000b0a: af00 add r7, sp, #0
|
|
return(ft5336_handle.i2cInitialized);
|
|
8000b0c: 4b03 ldr r3, [pc, #12] ; (8000b1c <ft5336_Get_I2C_InitializedStatus+0x14>)
|
|
8000b0e: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8000b10: 4618 mov r0, r3
|
|
8000b12: 46bd mov sp, r7
|
|
8000b14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b18: 4770 bx lr
|
|
8000b1a: bf00 nop
|
|
8000b1c: 2000035c .word 0x2000035c
|
|
|
|
08000b20 <ft5336_I2C_InitializeIfRequired>:
|
|
* @brief I2C initialize if needed.
|
|
* @param None.
|
|
* @retval : None.
|
|
*/
|
|
static void ft5336_I2C_InitializeIfRequired(void)
|
|
{
|
|
8000b20: b580 push {r7, lr}
|
|
8000b22: af00 add r7, sp, #0
|
|
if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED)
|
|
8000b24: f7ff fff0 bl 8000b08 <ft5336_Get_I2C_InitializedStatus>
|
|
8000b28: 4603 mov r3, r0
|
|
8000b2a: 2b00 cmp r3, #0
|
|
8000b2c: d104 bne.n 8000b38 <ft5336_I2C_InitializeIfRequired+0x18>
|
|
{
|
|
/* Initialize TS IO BUS layer (I2C) */
|
|
TS_IO_Init();
|
|
8000b2e: f001 fffd bl 8002b2c <TS_IO_Init>
|
|
|
|
/* Set state to initialized */
|
|
ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED;
|
|
8000b32: 4b02 ldr r3, [pc, #8] ; (8000b3c <ft5336_I2C_InitializeIfRequired+0x1c>)
|
|
8000b34: 2201 movs r2, #1
|
|
8000b36: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
8000b38: bf00 nop
|
|
8000b3a: bd80 pop {r7, pc}
|
|
8000b3c: 2000035c .word 0x2000035c
|
|
|
|
08000b40 <ft5336_TS_Configure>:
|
|
* @brief Basic static configuration of TouchScreen
|
|
* @param DeviceAddr: FT5336 Device address for communication on I2C Bus.
|
|
* @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK.
|
|
*/
|
|
static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr)
|
|
{
|
|
8000b40: b480 push {r7}
|
|
8000b42: b085 sub sp, #20
|
|
8000b44: af00 add r7, sp, #0
|
|
8000b46: 4603 mov r3, r0
|
|
8000b48: 80fb strh r3, [r7, #6]
|
|
uint32_t status = FT5336_STATUS_OK;
|
|
8000b4a: 2300 movs r3, #0
|
|
8000b4c: 60fb str r3, [r7, #12]
|
|
|
|
/* Nothing special to be done for FT5336 */
|
|
|
|
return(status);
|
|
8000b4e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8000b50: 4618 mov r0, r3
|
|
8000b52: 3714 adds r7, #20
|
|
8000b54: 46bd mov sp, r7
|
|
8000b56: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000b5a: 4770 bx lr
|
|
|
|
08000b5c <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000b5c: b5b0 push {r4, r5, r7, lr}
|
|
8000b5e: b0c2 sub sp, #264 ; 0x108
|
|
8000b60: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN 1 */
|
|
char text[50] = {};
|
|
8000b62: f107 03d4 add.w r3, r7, #212 ; 0xd4
|
|
8000b66: 2232 movs r2, #50 ; 0x32
|
|
8000b68: 2100 movs r1, #0
|
|
8000b6a: 4618 mov r0, r3
|
|
8000b6c: f01c f89b bl 801cca6 <memset>
|
|
static TS_StateTypeDef TS_State;
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8000b70: f107 03c4 add.w r3, r7, #196 ; 0xc4
|
|
8000b74: 2200 movs r2, #0
|
|
8000b76: 601a str r2, [r3, #0]
|
|
8000b78: 605a str r2, [r3, #4]
|
|
8000b7a: 609a str r2, [r3, #8]
|
|
8000b7c: 60da str r2, [r3, #12]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
8000b7e: 2301 movs r3, #1
|
|
8000b80: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
|
|
8000b84: 2300 movs r3, #0
|
|
8000b86: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000b8a: f004 fb88 bl 800529e <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8000b8e: f000 f989 bl 8000ea4 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000b92: f001 f85d bl 8001c50 <MX_GPIO_Init>
|
|
MX_ADC3_Init();
|
|
8000b96: f000 fa8b bl 80010b0 <MX_ADC3_Init>
|
|
MX_I2C1_Init();
|
|
8000b9a: f000 fb59 bl 8001250 <MX_I2C1_Init>
|
|
MX_I2C3_Init();
|
|
8000b9e: f000 fb97 bl 80012d0 <MX_I2C3_Init>
|
|
MX_LTDC_Init();
|
|
8000ba2: f000 fbd5 bl 8001350 <MX_LTDC_Init>
|
|
MX_RTC_Init();
|
|
8000ba6: f000 fc69 bl 800147c <MX_RTC_Init>
|
|
MX_SPI2_Init();
|
|
8000baa: f000 fd0d bl 80015c8 <MX_SPI2_Init>
|
|
MX_TIM1_Init();
|
|
8000bae: f000 fd49 bl 8001644 <MX_TIM1_Init>
|
|
MX_TIM2_Init();
|
|
8000bb2: f000 fd9b bl 80016ec <MX_TIM2_Init>
|
|
MX_TIM3_Init();
|
|
8000bb6: f000 fde7 bl 8001788 <MX_TIM3_Init>
|
|
MX_TIM5_Init();
|
|
8000bba: f000 fe73 bl 80018a4 <MX_TIM5_Init>
|
|
MX_TIM8_Init();
|
|
8000bbe: f000 febf bl 8001940 <MX_TIM8_Init>
|
|
MX_USART1_UART_Init();
|
|
8000bc2: f000 ff97 bl 8001af4 <MX_USART1_UART_Init>
|
|
MX_USART6_UART_Init();
|
|
8000bc6: f000 ffc5 bl 8001b54 <MX_USART6_UART_Init>
|
|
MX_ADC1_Init();
|
|
8000bca: f000 fa1f bl 800100c <MX_ADC1_Init>
|
|
MX_DAC_Init();
|
|
8000bce: f000 fae3 bl 8001198 <MX_DAC_Init>
|
|
MX_UART7_Init();
|
|
8000bd2: f000 ff5f bl 8001a94 <MX_UART7_Init>
|
|
MX_FMC_Init();
|
|
8000bd6: f000 ffed bl 8001bb4 <MX_FMC_Init>
|
|
MX_DMA2D_Init();
|
|
8000bda: f000 fb07 bl 80011ec <MX_DMA2D_Init>
|
|
MX_CRC_Init();
|
|
8000bde: f000 fab9 bl 8001154 <MX_CRC_Init>
|
|
MX_RNG_Init();
|
|
8000be2: f000 fc37 bl 8001454 <MX_RNG_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
BSP_LCD_Init();
|
|
8000be6: f001 ffef bl 8002bc8 <BSP_LCD_Init>
|
|
BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS);
|
|
8000bea: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000
|
|
8000bee: 2000 movs r0, #0
|
|
8000bf0: f002 f882 bl 8002cf8 <BSP_LCD_LayerDefaultInit>
|
|
BSP_LCD_LayerDefaultInit(1,
|
|
LCD_FB_START_ADDRESS + BSP_LCD_GetXSize() * BSP_LCD_GetYSize() * 4);
|
|
8000bf4: f002 f858 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8000bf8: 4604 mov r4, r0
|
|
8000bfa: f002 f869 bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8000bfe: 4603 mov r3, r0
|
|
8000c00: fb03 f304 mul.w r3, r3, r4
|
|
BSP_LCD_LayerDefaultInit(1,
|
|
8000c04: f103 5340 add.w r3, r3, #805306368 ; 0x30000000
|
|
8000c08: 009b lsls r3, r3, #2
|
|
8000c0a: 4619 mov r1, r3
|
|
8000c0c: 2001 movs r0, #1
|
|
8000c0e: f002 f873 bl 8002cf8 <BSP_LCD_LayerDefaultInit>
|
|
BSP_LCD_DisplayOn();
|
|
8000c12: f002 fdeb bl 80037ec <BSP_LCD_DisplayOn>
|
|
BSP_LCD_SelectLayer(1);
|
|
8000c16: 2001 movs r0, #1
|
|
8000c18: f002 f8ce bl 8002db8 <BSP_LCD_SelectLayer>
|
|
BSP_LCD_Clear(LCD_COLOR_BLACK);
|
|
8000c1c: f04f 407f mov.w r0, #4278190080 ; 0xff000000
|
|
8000c20: f002 f93c bl 8002e9c <BSP_LCD_Clear>
|
|
BSP_LCD_SetFont(&Font12);
|
|
8000c24: 4887 ldr r0, [pc, #540] ; (8000e44 <main+0x2e8>)
|
|
8000c26: f002 f909 bl 8002e3c <BSP_LCD_SetFont>
|
|
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
|
|
8000c2a: 4887 ldr r0, [pc, #540] ; (8000e48 <main+0x2ec>)
|
|
8000c2c: f002 f8d4 bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
BSP_LCD_SetBackColor(LCD_COLOR_BLACK);
|
|
8000c30: f04f 407f mov.w r0, #4278190080 ; 0xff000000
|
|
8000c34: f002 f8e8 bl 8002e08 <BSP_LCD_SetBackColor>
|
|
|
|
BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
|
|
8000c38: f002 f836 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8000c3c: 4603 mov r3, r0
|
|
8000c3e: b29c uxth r4, r3
|
|
8000c40: f002 f846 bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8000c44: 4603 mov r3, r0
|
|
8000c46: b29b uxth r3, r3
|
|
8000c48: 4619 mov r1, r3
|
|
8000c4a: 4620 mov r0, r4
|
|
8000c4c: f003 f9e0 bl 8004010 <BSP_TS_Init>
|
|
/* start timers, add new ones, ... */
|
|
/* USER CODE END RTOS_TIMERS */
|
|
|
|
/* Create the queue(s) */
|
|
/* definition and creation of Queue_E */
|
|
osMessageQDef(Queue_E, 16, uint16_t);
|
|
8000c50: 4b7e ldr r3, [pc, #504] ; (8000e4c <main+0x2f0>)
|
|
8000c52: f107 04b4 add.w r4, r7, #180 ; 0xb4
|
|
8000c56: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8000c58: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
Queue_EHandle = osMessageCreate(osMessageQ(Queue_E), NULL);
|
|
8000c5c: f107 03b4 add.w r3, r7, #180 ; 0xb4
|
|
8000c60: 2100 movs r1, #0
|
|
8000c62: 4618 mov r0, r3
|
|
8000c64: f00c febc bl 800d9e0 <osMessageCreate>
|
|
8000c68: 4602 mov r2, r0
|
|
8000c6a: 4b79 ldr r3, [pc, #484] ; (8000e50 <main+0x2f4>)
|
|
8000c6c: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Queue_F */
|
|
osMessageQDef(Queue_F, 1, uint8_t);
|
|
8000c6e: 4b79 ldr r3, [pc, #484] ; (8000e54 <main+0x2f8>)
|
|
8000c70: f107 04a4 add.w r4, r7, #164 ; 0xa4
|
|
8000c74: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8000c76: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
Queue_FHandle = osMessageCreate(osMessageQ(Queue_F), NULL);
|
|
8000c7a: f107 03a4 add.w r3, r7, #164 ; 0xa4
|
|
8000c7e: 2100 movs r1, #0
|
|
8000c80: 4618 mov r0, r3
|
|
8000c82: f00c fead bl 800d9e0 <osMessageCreate>
|
|
8000c86: 4602 mov r2, r0
|
|
8000c88: 4b73 ldr r3, [pc, #460] ; (8000e58 <main+0x2fc>)
|
|
8000c8a: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Queue_J */
|
|
osMessageQDef(Queue_J, 16, uint16_t);
|
|
8000c8c: 4b6f ldr r3, [pc, #444] ; (8000e4c <main+0x2f0>)
|
|
8000c8e: f107 0494 add.w r4, r7, #148 ; 0x94
|
|
8000c92: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8000c94: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
Queue_JHandle = osMessageCreate(osMessageQ(Queue_J), NULL);
|
|
8000c98: f107 0394 add.w r3, r7, #148 ; 0x94
|
|
8000c9c: 2100 movs r1, #0
|
|
8000c9e: 4618 mov r0, r3
|
|
8000ca0: f00c fe9e bl 800d9e0 <osMessageCreate>
|
|
8000ca4: 4602 mov r2, r0
|
|
8000ca6: 4b6d ldr r3, [pc, #436] ; (8000e5c <main+0x300>)
|
|
8000ca8: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Queue_P */
|
|
osMessageQDef(Queue_P, 16, uint16_t);
|
|
8000caa: 4b68 ldr r3, [pc, #416] ; (8000e4c <main+0x2f0>)
|
|
8000cac: f107 0484 add.w r4, r7, #132 ; 0x84
|
|
8000cb0: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8000cb2: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
Queue_PHandle = osMessageCreate(osMessageQ(Queue_P), NULL);
|
|
8000cb6: f107 0384 add.w r3, r7, #132 ; 0x84
|
|
8000cba: 2100 movs r1, #0
|
|
8000cbc: 4618 mov r0, r3
|
|
8000cbe: f00c fe8f bl 800d9e0 <osMessageCreate>
|
|
8000cc2: 4602 mov r2, r0
|
|
8000cc4: 4b66 ldr r3, [pc, #408] ; (8000e60 <main+0x304>)
|
|
8000cc6: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Queue_N */
|
|
osMessageQDef(Queue_N, 16, uint16_t);
|
|
8000cc8: 4b60 ldr r3, [pc, #384] ; (8000e4c <main+0x2f0>)
|
|
8000cca: f107 0474 add.w r4, r7, #116 ; 0x74
|
|
8000cce: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8000cd0: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
Queue_NHandle = osMessageCreate(osMessageQ(Queue_N), NULL);
|
|
8000cd4: f107 0374 add.w r3, r7, #116 ; 0x74
|
|
8000cd8: 2100 movs r1, #0
|
|
8000cda: 4618 mov r0, r3
|
|
8000cdc: f00c fe80 bl 800d9e0 <osMessageCreate>
|
|
8000ce0: 4602 mov r2, r0
|
|
8000ce2: 4b60 ldr r3, [pc, #384] ; (8000e64 <main+0x308>)
|
|
8000ce4: 601a str r2, [r3, #0]
|
|
/* add queues, ... */
|
|
/* USER CODE END RTOS_QUEUES */
|
|
|
|
/* Create the thread(s) */
|
|
/* definition and creation of GameMaster */
|
|
osThreadDef(GameMaster, f_GameMaster, osPriorityNormal, 0, 128);
|
|
8000ce6: 4b60 ldr r3, [pc, #384] ; (8000e68 <main+0x30c>)
|
|
8000ce8: f107 0458 add.w r4, r7, #88 ; 0x58
|
|
8000cec: 461d mov r5, r3
|
|
8000cee: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8000cf0: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8000cf2: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
8000cf6: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
GameMasterHandle = osThreadCreate(osThread(GameMaster), NULL);
|
|
8000cfa: f107 0358 add.w r3, r7, #88 ; 0x58
|
|
8000cfe: 2100 movs r1, #0
|
|
8000d00: 4618 mov r0, r3
|
|
8000d02: f00c fcac bl 800d65e <osThreadCreate>
|
|
8000d06: 4602 mov r2, r0
|
|
8000d08: 4b58 ldr r3, [pc, #352] ; (8000e6c <main+0x310>)
|
|
8000d0a: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Joueur_1 */
|
|
osThreadDef(Joueur_1, f_Joueur_1, osPriorityNormal, 0, 128);
|
|
8000d0c: 4b58 ldr r3, [pc, #352] ; (8000e70 <main+0x314>)
|
|
8000d0e: f107 043c add.w r4, r7, #60 ; 0x3c
|
|
8000d12: 461d mov r5, r3
|
|
8000d14: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8000d16: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8000d18: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
8000d1c: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
Joueur_1Handle = osThreadCreate(osThread(Joueur_1), NULL);
|
|
8000d20: f107 033c add.w r3, r7, #60 ; 0x3c
|
|
8000d24: 2100 movs r1, #0
|
|
8000d26: 4618 mov r0, r3
|
|
8000d28: f00c fc99 bl 800d65e <osThreadCreate>
|
|
8000d2c: 4602 mov r2, r0
|
|
8000d2e: 4b51 ldr r3, [pc, #324] ; (8000e74 <main+0x318>)
|
|
8000d30: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Block_Enemie */
|
|
osThreadDef(Block_Enemie, f_block_enemie, osPriorityIdle, 0, 128);
|
|
8000d32: 4b51 ldr r3, [pc, #324] ; (8000e78 <main+0x31c>)
|
|
8000d34: f107 0420 add.w r4, r7, #32
|
|
8000d38: 461d mov r5, r3
|
|
8000d3a: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8000d3c: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8000d3e: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
8000d42: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
Block_EnemieHandle = osThreadCreate(osThread(Block_Enemie), NULL);
|
|
8000d46: f107 0320 add.w r3, r7, #32
|
|
8000d4a: 2100 movs r1, #0
|
|
8000d4c: 4618 mov r0, r3
|
|
8000d4e: f00c fc86 bl 800d65e <osThreadCreate>
|
|
8000d52: 4602 mov r2, r0
|
|
8000d54: 4b49 ldr r3, [pc, #292] ; (8000e7c <main+0x320>)
|
|
8000d56: 601a str r2, [r3, #0]
|
|
|
|
/* definition and creation of Projectile */
|
|
osThreadDef(Projectile, f_projectile, osPriorityNormal, 0, 128);
|
|
8000d58: 1d3b adds r3, r7, #4
|
|
8000d5a: 4a49 ldr r2, [pc, #292] ; (8000e80 <main+0x324>)
|
|
8000d5c: 461c mov r4, r3
|
|
8000d5e: 4615 mov r5, r2
|
|
8000d60: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8000d62: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8000d64: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
8000d68: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
ProjectileHandle = osThreadCreate(osThread(Projectile), NULL);
|
|
8000d6c: 1d3b adds r3, r7, #4
|
|
8000d6e: 2100 movs r1, #0
|
|
8000d70: 4618 mov r0, r3
|
|
8000d72: f00c fc74 bl 800d65e <osThreadCreate>
|
|
8000d76: 4602 mov r2, r0
|
|
8000d78: 4b42 ldr r3, [pc, #264] ; (8000e84 <main+0x328>)
|
|
8000d7a: 601a str r2, [r3, #0]
|
|
/* USER CODE BEGIN RTOS_THREADS */
|
|
/* add threads, ... */
|
|
/* USER CODE END RTOS_THREADS */
|
|
|
|
/* Start scheduler */
|
|
osKernelStart();
|
|
8000d7c: f00c fc58 bl 800d630 <osKernelStart>
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
/* Code de base */
|
|
HAL_GPIO_WritePin(LED13_GPIO_Port, LED13_Pin,
|
|
8000d80: f44f 7180 mov.w r1, #256 ; 0x100
|
|
8000d84: 4840 ldr r0, [pc, #256] ; (8000e88 <main+0x32c>)
|
|
8000d86: f007 f9cf bl 8008128 <HAL_GPIO_ReadPin>
|
|
8000d8a: 4603 mov r3, r0
|
|
8000d8c: 461a mov r2, r3
|
|
8000d8e: f44f 4180 mov.w r1, #16384 ; 0x4000
|
|
8000d92: 483e ldr r0, [pc, #248] ; (8000e8c <main+0x330>)
|
|
8000d94: f007 f9e0 bl 8008158 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_ReadPin(BP1_GPIO_Port, BP1_Pin));
|
|
HAL_GPIO_WritePin(LED14_GPIO_Port, LED14_Pin,
|
|
8000d98: f44f 4100 mov.w r1, #32768 ; 0x8000
|
|
8000d9c: 483a ldr r0, [pc, #232] ; (8000e88 <main+0x32c>)
|
|
8000d9e: f007 f9c3 bl 8008128 <HAL_GPIO_ReadPin>
|
|
8000da2: 4603 mov r3, r0
|
|
8000da4: 461a mov r2, r3
|
|
8000da6: 2120 movs r1, #32
|
|
8000da8: 4839 ldr r0, [pc, #228] ; (8000e90 <main+0x334>)
|
|
8000daa: f007 f9d5 bl 8008158 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_ReadPin(BP2_GPIO_Port, BP2_Pin));
|
|
sprintf(text, "BP1 : %d", HAL_GPIO_ReadPin(BP1_GPIO_Port, BP1_Pin));
|
|
8000dae: f44f 7180 mov.w r1, #256 ; 0x100
|
|
8000db2: 4835 ldr r0, [pc, #212] ; (8000e88 <main+0x32c>)
|
|
8000db4: f007 f9b8 bl 8008128 <HAL_GPIO_ReadPin>
|
|
8000db8: 4603 mov r3, r0
|
|
8000dba: 461a mov r2, r3
|
|
8000dbc: f107 03d4 add.w r3, r7, #212 ; 0xd4
|
|
8000dc0: 4934 ldr r1, [pc, #208] ; (8000e94 <main+0x338>)
|
|
8000dc2: 4618 mov r0, r3
|
|
8000dc4: f01b ffc4 bl 801cd50 <siprintf>
|
|
BSP_LCD_DisplayStringAtLine(5, (uint8_t *)text);
|
|
8000dc8: f107 03d4 add.w r3, r7, #212 ; 0xd4
|
|
8000dcc: 4619 mov r1, r3
|
|
8000dce: 2005 movs r0, #5
|
|
8000dd0: f002 f994 bl 80030fc <BSP_LCD_DisplayStringAtLine>
|
|
|
|
|
|
;
|
|
|
|
sConfig.Channel = ADC_CHANNEL_7;
|
|
8000dd4: 2307 movs r3, #7
|
|
8000dd6: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
|
|
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
|
|
8000dda: f107 03c4 add.w r3, r7, #196 ; 0xc4
|
|
8000dde: 4619 mov r1, r3
|
|
8000de0: 482d ldr r0, [pc, #180] ; (8000e98 <main+0x33c>)
|
|
8000de2: f004 fc41 bl 8005668 <HAL_ADC_ConfigChannel>
|
|
HAL_ADC_Start(&hadc3);
|
|
8000de6: 482c ldr r0, [pc, #176] ; (8000e98 <main+0x33c>)
|
|
8000de8: f004 faec bl 80053c4 <HAL_ADC_Start>
|
|
|
|
sConfig.Channel = ADC_CHANNEL_6;
|
|
8000dec: 2306 movs r3, #6
|
|
8000dee: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
|
|
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
|
|
8000df2: f107 03c4 add.w r3, r7, #196 ; 0xc4
|
|
8000df6: 4619 mov r1, r3
|
|
8000df8: 4827 ldr r0, [pc, #156] ; (8000e98 <main+0x33c>)
|
|
8000dfa: f004 fc35 bl 8005668 <HAL_ADC_ConfigChannel>
|
|
HAL_ADC_Start(&hadc3);
|
|
8000dfe: 4826 ldr r0, [pc, #152] ; (8000e98 <main+0x33c>)
|
|
8000e00: f004 fae0 bl 80053c4 <HAL_ADC_Start>
|
|
sConfig.Channel = ADC_CHANNEL_8;
|
|
8000e04: 2308 movs r3, #8
|
|
8000e06: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
|
|
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
|
|
8000e0a: f107 03c4 add.w r3, r7, #196 ; 0xc4
|
|
8000e0e: 4619 mov r1, r3
|
|
8000e10: 4821 ldr r0, [pc, #132] ; (8000e98 <main+0x33c>)
|
|
8000e12: f004 fc29 bl 8005668 <HAL_ADC_ConfigChannel>
|
|
HAL_ADC_Start(&hadc3);
|
|
8000e16: 4820 ldr r0, [pc, #128] ; (8000e98 <main+0x33c>)
|
|
8000e18: f004 fad4 bl 80053c4 <HAL_ADC_Start>
|
|
|
|
HAL_ADC_Start(&hadc1);
|
|
8000e1c: 481f ldr r0, [pc, #124] ; (8000e9c <main+0x340>)
|
|
8000e1e: f004 fad1 bl 80053c4 <HAL_ADC_Start>
|
|
|
|
|
|
|
|
BSP_TS_GetState(&TS_State);
|
|
8000e22: 481f ldr r0, [pc, #124] ; (8000ea0 <main+0x344>)
|
|
8000e24: f003 f934 bl 8004090 <BSP_TS_GetState>
|
|
if (TS_State.touchDetected)
|
|
8000e28: 4b1d ldr r3, [pc, #116] ; (8000ea0 <main+0x344>)
|
|
8000e2a: 781b ldrb r3, [r3, #0]
|
|
8000e2c: 2b00 cmp r3, #0
|
|
8000e2e: d0a7 beq.n 8000d80 <main+0x224>
|
|
{
|
|
BSP_LCD_FillCircle(TS_State.touchX[0], TS_State.touchY[0], 4);
|
|
8000e30: 4b1b ldr r3, [pc, #108] ; (8000ea0 <main+0x344>)
|
|
8000e32: 8858 ldrh r0, [r3, #2]
|
|
8000e34: 4b1a ldr r3, [pc, #104] ; (8000ea0 <main+0x344>)
|
|
8000e36: 899b ldrh r3, [r3, #12]
|
|
8000e38: 2204 movs r2, #4
|
|
8000e3a: 4619 mov r1, r3
|
|
8000e3c: f002 fc36 bl 80036ac <BSP_LCD_FillCircle>
|
|
HAL_GPIO_WritePin(LED13_GPIO_Port, LED13_Pin,
|
|
8000e40: e79e b.n 8000d80 <main+0x224>
|
|
8000e42: bf00 nop
|
|
8000e44: 20000058 .word 0x20000058
|
|
8000e48: ff0000ff .word 0xff0000ff
|
|
8000e4c: 0801de5c .word 0x0801de5c
|
|
8000e50: 20008e34 .word 0x20008e34
|
|
8000e54: 0801de6c .word 0x0801de6c
|
|
8000e58: 20008ca0 .word 0x20008ca0
|
|
8000e5c: 200089ec .word 0x200089ec
|
|
8000e60: 20008ca4 .word 0x20008ca4
|
|
8000e64: 20008c1c .word 0x20008c1c
|
|
8000e68: 0801de88 .word 0x0801de88
|
|
8000e6c: 20008db0 .word 0x20008db0
|
|
8000e70: 0801deb0 .word 0x0801deb0
|
|
8000e74: 20008a60 .word 0x20008a60
|
|
8000e78: 0801dedc .word 0x0801dedc
|
|
8000e7c: 20008e6c .word 0x20008e6c
|
|
8000e80: 0801df04 .word 0x0801df04
|
|
8000e84: 20008cbc .word 0x20008cbc
|
|
8000e88: 40020000 .word 0x40020000
|
|
8000e8c: 40021c00 .word 0x40021c00
|
|
8000e90: 40021000 .word 0x40021000
|
|
8000e94: 0801de50 .word 0x0801de50
|
|
8000e98: 20008bd4 .word 0x20008bd4
|
|
8000e9c: 20008b8c .word 0x20008b8c
|
|
8000ea0: 20000364 .word 0x20000364
|
|
|
|
08000ea4 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8000ea4: b580 push {r7, lr}
|
|
8000ea6: b0b4 sub sp, #208 ; 0xd0
|
|
8000ea8: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000eaa: f107 03a0 add.w r3, r7, #160 ; 0xa0
|
|
8000eae: 2230 movs r2, #48 ; 0x30
|
|
8000eb0: 2100 movs r1, #0
|
|
8000eb2: 4618 mov r0, r3
|
|
8000eb4: f01b fef7 bl 801cca6 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8000eb8: f107 038c add.w r3, r7, #140 ; 0x8c
|
|
8000ebc: 2200 movs r2, #0
|
|
8000ebe: 601a str r2, [r3, #0]
|
|
8000ec0: 605a str r2, [r3, #4]
|
|
8000ec2: 609a str r2, [r3, #8]
|
|
8000ec4: 60da str r2, [r3, #12]
|
|
8000ec6: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8000ec8: f107 0308 add.w r3, r7, #8
|
|
8000ecc: 2284 movs r2, #132 ; 0x84
|
|
8000ece: 2100 movs r1, #0
|
|
8000ed0: 4618 mov r0, r3
|
|
8000ed2: f01b fee8 bl 801cca6 <memset>
|
|
|
|
/** Configure LSE Drive Capability
|
|
*/
|
|
HAL_PWR_EnableBkUpAccess();
|
|
8000ed6: f008 fa81 bl 80093dc <HAL_PWR_EnableBkUpAccess>
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000eda: 4b49 ldr r3, [pc, #292] ; (8001000 <SystemClock_Config+0x15c>)
|
|
8000edc: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8000ede: 4a48 ldr r2, [pc, #288] ; (8001000 <SystemClock_Config+0x15c>)
|
|
8000ee0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8000ee4: 6413 str r3, [r2, #64] ; 0x40
|
|
8000ee6: 4b46 ldr r3, [pc, #280] ; (8001000 <SystemClock_Config+0x15c>)
|
|
8000ee8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8000eea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8000eee: 607b str r3, [r7, #4]
|
|
8000ef0: 687b ldr r3, [r7, #4]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
8000ef2: 4b44 ldr r3, [pc, #272] ; (8001004 <SystemClock_Config+0x160>)
|
|
8000ef4: 681b ldr r3, [r3, #0]
|
|
8000ef6: 4a43 ldr r2, [pc, #268] ; (8001004 <SystemClock_Config+0x160>)
|
|
8000ef8: f443 4340 orr.w r3, r3, #49152 ; 0xc000
|
|
8000efc: 6013 str r3, [r2, #0]
|
|
8000efe: 4b41 ldr r3, [pc, #260] ; (8001004 <SystemClock_Config+0x160>)
|
|
8000f00: 681b ldr r3, [r3, #0]
|
|
8000f02: f403 4340 and.w r3, r3, #49152 ; 0xc000
|
|
8000f06: 603b str r3, [r7, #0]
|
|
8000f08: 683b ldr r3, [r7, #0]
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
|
|
8000f0a: 2309 movs r3, #9
|
|
8000f0c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8000f10: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
8000f14: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
|
8000f18: 2301 movs r3, #1
|
|
8000f1a: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8000f1e: 2302 movs r3, #2
|
|
8000f20: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
8000f24: f44f 0380 mov.w r3, #4194304 ; 0x400000
|
|
8000f28: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
RCC_OscInitStruct.PLL.PLLM = 25;
|
|
8000f2c: 2319 movs r3, #25
|
|
8000f2e: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
|
|
RCC_OscInitStruct.PLL.PLLN = 400;
|
|
8000f32: f44f 73c8 mov.w r3, #400 ; 0x190
|
|
8000f36: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
8000f3a: 2302 movs r3, #2
|
|
8000f3c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
|
|
RCC_OscInitStruct.PLL.PLLQ = 9;
|
|
8000f40: 2309 movs r3, #9
|
|
8000f42: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000f46: f107 03a0 add.w r3, r7, #160 ; 0xa0
|
|
8000f4a: 4618 mov r0, r3
|
|
8000f4c: f008 faa6 bl 800949c <HAL_RCC_OscConfig>
|
|
8000f50: 4603 mov r3, r0
|
|
8000f52: 2b00 cmp r3, #0
|
|
8000f54: d001 beq.n 8000f5a <SystemClock_Config+0xb6>
|
|
{
|
|
Error_Handler();
|
|
8000f56: f001 fc8f bl 8002878 <Error_Handler>
|
|
}
|
|
/** Activate the Over-Drive mode
|
|
*/
|
|
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
|
|
8000f5a: f008 fa4f bl 80093fc <HAL_PWREx_EnableOverDrive>
|
|
8000f5e: 4603 mov r3, r0
|
|
8000f60: 2b00 cmp r3, #0
|
|
8000f62: d001 beq.n 8000f68 <SystemClock_Config+0xc4>
|
|
{
|
|
Error_Handler();
|
|
8000f64: f001 fc88 bl 8002878 <Error_Handler>
|
|
}
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000f68: 230f movs r3, #15
|
|
8000f6a: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8000f6e: 2302 movs r3, #2
|
|
8000f70: f8c7 3090 str.w r3, [r7, #144] ; 0x90
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8000f74: 2300 movs r3, #0
|
|
8000f76: f8c7 3094 str.w r3, [r7, #148] ; 0x94
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
|
8000f7a: f44f 53a0 mov.w r3, #5120 ; 0x1400
|
|
8000f7e: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
|
8000f82: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8000f86: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
|
|
8000f8a: f107 038c add.w r3, r7, #140 ; 0x8c
|
|
8000f8e: 2106 movs r1, #6
|
|
8000f90: 4618 mov r0, r3
|
|
8000f92: f008 fd27 bl 80099e4 <HAL_RCC_ClockConfig>
|
|
8000f96: 4603 mov r3, r0
|
|
8000f98: 2b00 cmp r3, #0
|
|
8000f9a: d001 beq.n 8000fa0 <SystemClock_Config+0xfc>
|
|
{
|
|
Error_Handler();
|
|
8000f9c: f001 fc6c bl 8002878 <Error_Handler>
|
|
}
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_RTC
|
|
8000fa0: 4b19 ldr r3, [pc, #100] ; (8001008 <SystemClock_Config+0x164>)
|
|
8000fa2: 60bb str r3, [r7, #8]
|
|
|RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART6
|
|
|RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_I2C1
|
|
|RCC_PERIPHCLK_I2C3|RCC_PERIPHCLK_CLK48;
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
|
|
8000fa4: f44f 73c0 mov.w r3, #384 ; 0x180
|
|
8000fa8: 61fb str r3, [r7, #28]
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
|
|
8000faa: 2305 movs r3, #5
|
|
8000fac: 627b str r3, [r7, #36] ; 0x24
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
|
|
8000fae: 2302 movs r3, #2
|
|
8000fb0: 623b str r3, [r7, #32]
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
|
|
8000fb2: 2303 movs r3, #3
|
|
8000fb4: 62bb str r3, [r7, #40] ; 0x28
|
|
PeriphClkInitStruct.PLLSAIDivQ = 1;
|
|
8000fb6: 2301 movs r3, #1
|
|
8000fb8: 633b str r3, [r7, #48] ; 0x30
|
|
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
|
|
8000fba: f44f 3300 mov.w r3, #131072 ; 0x20000
|
|
8000fbe: 637b str r3, [r7, #52] ; 0x34
|
|
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
|
8000fc0: f44f 7300 mov.w r3, #512 ; 0x200
|
|
8000fc4: 63bb str r3, [r7, #56] ; 0x38
|
|
PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
8000fc6: 2300 movs r3, #0
|
|
8000fc8: 64fb str r3, [r7, #76] ; 0x4c
|
|
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
|
|
8000fca: 2300 movs r3, #0
|
|
8000fcc: 663b str r3, [r7, #96] ; 0x60
|
|
PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
|
|
8000fce: 2300 movs r3, #0
|
|
8000fd0: 667b str r3, [r7, #100] ; 0x64
|
|
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
|
|
8000fd2: 2300 movs r3, #0
|
|
8000fd4: 66fb str r3, [r7, #108] ; 0x6c
|
|
PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
|
|
8000fd6: 2300 movs r3, #0
|
|
8000fd8: 677b str r3, [r7, #116] ; 0x74
|
|
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLLSAIP;
|
|
8000fda: f04f 6300 mov.w r3, #134217728 ; 0x8000000
|
|
8000fde: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8000fe2: f107 0308 add.w r3, r7, #8
|
|
8000fe6: 4618 mov r0, r3
|
|
8000fe8: f008 ff00 bl 8009dec <HAL_RCCEx_PeriphCLKConfig>
|
|
8000fec: 4603 mov r3, r0
|
|
8000fee: 2b00 cmp r3, #0
|
|
8000ff0: d001 beq.n 8000ff6 <SystemClock_Config+0x152>
|
|
{
|
|
Error_Handler();
|
|
8000ff2: f001 fc41 bl 8002878 <Error_Handler>
|
|
}
|
|
}
|
|
8000ff6: bf00 nop
|
|
8000ff8: 37d0 adds r7, #208 ; 0xd0
|
|
8000ffa: 46bd mov sp, r7
|
|
8000ffc: bd80 pop {r7, pc}
|
|
8000ffe: bf00 nop
|
|
8001000: 40023800 .word 0x40023800
|
|
8001004: 40007000 .word 0x40007000
|
|
8001008: 00215868 .word 0x00215868
|
|
|
|
0800100c <MX_ADC1_Init>:
|
|
* @brief ADC1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC1_Init(void)
|
|
{
|
|
800100c: b580 push {r7, lr}
|
|
800100e: b084 sub sp, #16
|
|
8001010: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC1_Init 0 */
|
|
|
|
/* USER CODE END ADC1_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8001012: 463b mov r3, r7
|
|
8001014: 2200 movs r2, #0
|
|
8001016: 601a str r2, [r3, #0]
|
|
8001018: 605a str r2, [r3, #4]
|
|
800101a: 609a str r2, [r3, #8]
|
|
800101c: 60da str r2, [r3, #12]
|
|
/* USER CODE BEGIN ADC1_Init 1 */
|
|
|
|
/* USER CODE END ADC1_Init 1 */
|
|
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
|
|
*/
|
|
hadc1.Instance = ADC1;
|
|
800101e: 4b21 ldr r3, [pc, #132] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001020: 4a21 ldr r2, [pc, #132] ; (80010a8 <MX_ADC1_Init+0x9c>)
|
|
8001022: 601a str r2, [r3, #0]
|
|
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
|
|
8001024: 4b1f ldr r3, [pc, #124] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001026: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
800102a: 605a str r2, [r3, #4]
|
|
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
|
|
800102c: 4b1d ldr r3, [pc, #116] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800102e: 2200 movs r2, #0
|
|
8001030: 609a str r2, [r3, #8]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
8001032: 4b1c ldr r3, [pc, #112] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001034: 2200 movs r2, #0
|
|
8001036: 611a str r2, [r3, #16]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
8001038: 4b1a ldr r3, [pc, #104] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800103a: 2200 movs r2, #0
|
|
800103c: 619a str r2, [r3, #24]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
800103e: 4b19 ldr r3, [pc, #100] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001040: 2200 movs r2, #0
|
|
8001042: f883 2020 strb.w r2, [r3, #32]
|
|
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
8001046: 4b17 ldr r3, [pc, #92] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001048: 2200 movs r2, #0
|
|
800104a: 62da str r2, [r3, #44] ; 0x2c
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
800104c: 4b15 ldr r3, [pc, #84] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800104e: 4a17 ldr r2, [pc, #92] ; (80010ac <MX_ADC1_Init+0xa0>)
|
|
8001050: 629a str r2, [r3, #40] ; 0x28
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8001052: 4b14 ldr r3, [pc, #80] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001054: 2200 movs r2, #0
|
|
8001056: 60da str r2, [r3, #12]
|
|
hadc1.Init.NbrOfConversion = 1;
|
|
8001058: 4b12 ldr r3, [pc, #72] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800105a: 2201 movs r2, #1
|
|
800105c: 61da str r2, [r3, #28]
|
|
hadc1.Init.DMAContinuousRequests = DISABLE;
|
|
800105e: 4b11 ldr r3, [pc, #68] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001060: 2200 movs r2, #0
|
|
8001062: f883 2030 strb.w r2, [r3, #48] ; 0x30
|
|
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
8001066: 4b0f ldr r3, [pc, #60] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
8001068: 2201 movs r2, #1
|
|
800106a: 615a str r2, [r3, #20]
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
800106c: 480d ldr r0, [pc, #52] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800106e: f004 f965 bl 800533c <HAL_ADC_Init>
|
|
8001072: 4603 mov r3, r0
|
|
8001074: 2b00 cmp r3, #0
|
|
8001076: d001 beq.n 800107c <MX_ADC1_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
8001078: f001 fbfe bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_0;
|
|
800107c: 2300 movs r3, #0
|
|
800107e: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
8001080: 2301 movs r3, #1
|
|
8001082: 607b str r3, [r7, #4]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
|
|
8001084: 2300 movs r3, #0
|
|
8001086: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001088: 463b mov r3, r7
|
|
800108a: 4619 mov r1, r3
|
|
800108c: 4805 ldr r0, [pc, #20] ; (80010a4 <MX_ADC1_Init+0x98>)
|
|
800108e: f004 faeb bl 8005668 <HAL_ADC_ConfigChannel>
|
|
8001092: 4603 mov r3, r0
|
|
8001094: 2b00 cmp r3, #0
|
|
8001096: d001 beq.n 800109c <MX_ADC1_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
8001098: f001 fbee bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC1_Init 2 */
|
|
|
|
/* USER CODE END ADC1_Init 2 */
|
|
|
|
}
|
|
800109c: bf00 nop
|
|
800109e: 3710 adds r7, #16
|
|
80010a0: 46bd mov sp, r7
|
|
80010a2: bd80 pop {r7, pc}
|
|
80010a4: 20008b8c .word 0x20008b8c
|
|
80010a8: 40012000 .word 0x40012000
|
|
80010ac: 0f000001 .word 0x0f000001
|
|
|
|
080010b0 <MX_ADC3_Init>:
|
|
* @brief ADC3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_ADC3_Init(void)
|
|
{
|
|
80010b0: b580 push {r7, lr}
|
|
80010b2: b084 sub sp, #16
|
|
80010b4: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN ADC3_Init 0 */
|
|
|
|
/* USER CODE END ADC3_Init 0 */
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
80010b6: 463b mov r3, r7
|
|
80010b8: 2200 movs r2, #0
|
|
80010ba: 601a str r2, [r3, #0]
|
|
80010bc: 605a str r2, [r3, #4]
|
|
80010be: 609a str r2, [r3, #8]
|
|
80010c0: 60da str r2, [r3, #12]
|
|
/* USER CODE BEGIN ADC3_Init 1 */
|
|
|
|
/* USER CODE END ADC3_Init 1 */
|
|
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
|
|
*/
|
|
hadc3.Instance = ADC3;
|
|
80010c2: 4b21 ldr r3, [pc, #132] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010c4: 4a21 ldr r2, [pc, #132] ; (800114c <MX_ADC3_Init+0x9c>)
|
|
80010c6: 601a str r2, [r3, #0]
|
|
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
|
|
80010c8: 4b1f ldr r3, [pc, #124] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010ca: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
80010ce: 605a str r2, [r3, #4]
|
|
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
|
|
80010d0: 4b1d ldr r3, [pc, #116] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010d2: 2200 movs r2, #0
|
|
80010d4: 609a str r2, [r3, #8]
|
|
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
|
80010d6: 4b1c ldr r3, [pc, #112] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010d8: 2200 movs r2, #0
|
|
80010da: 611a str r2, [r3, #16]
|
|
hadc3.Init.ContinuousConvMode = DISABLE;
|
|
80010dc: 4b1a ldr r3, [pc, #104] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010de: 2200 movs r2, #0
|
|
80010e0: 619a str r2, [r3, #24]
|
|
hadc3.Init.DiscontinuousConvMode = DISABLE;
|
|
80010e2: 4b19 ldr r3, [pc, #100] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010e4: 2200 movs r2, #0
|
|
80010e6: f883 2020 strb.w r2, [r3, #32]
|
|
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
80010ea: 4b17 ldr r3, [pc, #92] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010ec: 2200 movs r2, #0
|
|
80010ee: 62da str r2, [r3, #44] ; 0x2c
|
|
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
80010f0: 4b15 ldr r3, [pc, #84] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010f2: 4a17 ldr r2, [pc, #92] ; (8001150 <MX_ADC3_Init+0xa0>)
|
|
80010f4: 629a str r2, [r3, #40] ; 0x28
|
|
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
80010f6: 4b14 ldr r3, [pc, #80] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010f8: 2200 movs r2, #0
|
|
80010fa: 60da str r2, [r3, #12]
|
|
hadc3.Init.NbrOfConversion = 1;
|
|
80010fc: 4b12 ldr r3, [pc, #72] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
80010fe: 2201 movs r2, #1
|
|
8001100: 61da str r2, [r3, #28]
|
|
hadc3.Init.DMAContinuousRequests = DISABLE;
|
|
8001102: 4b11 ldr r3, [pc, #68] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
8001104: 2200 movs r2, #0
|
|
8001106: f883 2030 strb.w r2, [r3, #48] ; 0x30
|
|
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
800110a: 4b0f ldr r3, [pc, #60] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
800110c: 2201 movs r2, #1
|
|
800110e: 615a str r2, [r3, #20]
|
|
if (HAL_ADC_Init(&hadc3) != HAL_OK)
|
|
8001110: 480d ldr r0, [pc, #52] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
8001112: f004 f913 bl 800533c <HAL_ADC_Init>
|
|
8001116: 4603 mov r3, r0
|
|
8001118: 2b00 cmp r3, #0
|
|
800111a: d001 beq.n 8001120 <MX_ADC3_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
800111c: f001 fbac bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
|
|
*/
|
|
sConfig.Channel = ADC_CHANNEL_6;
|
|
8001120: 2306 movs r3, #6
|
|
8001122: 603b str r3, [r7, #0]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
8001124: 2301 movs r3, #1
|
|
8001126: 607b str r3, [r7, #4]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
|
|
8001128: 2300 movs r3, #0
|
|
800112a: 60bb str r3, [r7, #8]
|
|
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
|
|
800112c: 463b mov r3, r7
|
|
800112e: 4619 mov r1, r3
|
|
8001130: 4805 ldr r0, [pc, #20] ; (8001148 <MX_ADC3_Init+0x98>)
|
|
8001132: f004 fa99 bl 8005668 <HAL_ADC_ConfigChannel>
|
|
8001136: 4603 mov r3, r0
|
|
8001138: 2b00 cmp r3, #0
|
|
800113a: d001 beq.n 8001140 <MX_ADC3_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
800113c: f001 fb9c bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN ADC3_Init 2 */
|
|
|
|
/* USER CODE END ADC3_Init 2 */
|
|
|
|
}
|
|
8001140: bf00 nop
|
|
8001142: 3710 adds r7, #16
|
|
8001144: 46bd mov sp, r7
|
|
8001146: bd80 pop {r7, pc}
|
|
8001148: 20008bd4 .word 0x20008bd4
|
|
800114c: 40012200 .word 0x40012200
|
|
8001150: 0f000001 .word 0x0f000001
|
|
|
|
08001154 <MX_CRC_Init>:
|
|
* @brief CRC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_CRC_Init(void)
|
|
{
|
|
8001154: b580 push {r7, lr}
|
|
8001156: af00 add r7, sp, #0
|
|
/* USER CODE END CRC_Init 0 */
|
|
|
|
/* USER CODE BEGIN CRC_Init 1 */
|
|
|
|
/* USER CODE END CRC_Init 1 */
|
|
hcrc.Instance = CRC;
|
|
8001158: 4b0d ldr r3, [pc, #52] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
800115a: 4a0e ldr r2, [pc, #56] ; (8001194 <MX_CRC_Init+0x40>)
|
|
800115c: 601a str r2, [r3, #0]
|
|
hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
|
|
800115e: 4b0c ldr r3, [pc, #48] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
8001160: 2200 movs r2, #0
|
|
8001162: 711a strb r2, [r3, #4]
|
|
hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE;
|
|
8001164: 4b0a ldr r3, [pc, #40] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
8001166: 2200 movs r2, #0
|
|
8001168: 715a strb r2, [r3, #5]
|
|
hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE;
|
|
800116a: 4b09 ldr r3, [pc, #36] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
800116c: 2200 movs r2, #0
|
|
800116e: 615a str r2, [r3, #20]
|
|
hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE;
|
|
8001170: 4b07 ldr r3, [pc, #28] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
8001172: 2200 movs r2, #0
|
|
8001174: 619a str r2, [r3, #24]
|
|
hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES;
|
|
8001176: 4b06 ldr r3, [pc, #24] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
8001178: 2201 movs r2, #1
|
|
800117a: 621a str r2, [r3, #32]
|
|
if (HAL_CRC_Init(&hcrc) != HAL_OK)
|
|
800117c: 4804 ldr r0, [pc, #16] ; (8001190 <MX_CRC_Init+0x3c>)
|
|
800117e: f004 fd99 bl 8005cb4 <HAL_CRC_Init>
|
|
8001182: 4603 mov r3, r0
|
|
8001184: 2b00 cmp r3, #0
|
|
8001186: d001 beq.n 800118c <MX_CRC_Init+0x38>
|
|
{
|
|
Error_Handler();
|
|
8001188: f001 fb76 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN CRC_Init 2 */
|
|
|
|
/* USER CODE END CRC_Init 2 */
|
|
|
|
}
|
|
800118c: bf00 nop
|
|
800118e: bd80 pop {r7, pc}
|
|
8001190: 20008a3c .word 0x20008a3c
|
|
8001194: 40023000 .word 0x40023000
|
|
|
|
08001198 <MX_DAC_Init>:
|
|
* @brief DAC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DAC_Init(void)
|
|
{
|
|
8001198: b580 push {r7, lr}
|
|
800119a: b082 sub sp, #8
|
|
800119c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN DAC_Init 0 */
|
|
|
|
/* USER CODE END DAC_Init 0 */
|
|
|
|
DAC_ChannelConfTypeDef sConfig = {0};
|
|
800119e: 463b mov r3, r7
|
|
80011a0: 2200 movs r2, #0
|
|
80011a2: 601a str r2, [r3, #0]
|
|
80011a4: 605a str r2, [r3, #4]
|
|
/* USER CODE BEGIN DAC_Init 1 */
|
|
|
|
/* USER CODE END DAC_Init 1 */
|
|
/** DAC Initialization
|
|
*/
|
|
hdac.Instance = DAC;
|
|
80011a6: 4b0f ldr r3, [pc, #60] ; (80011e4 <MX_DAC_Init+0x4c>)
|
|
80011a8: 4a0f ldr r2, [pc, #60] ; (80011e8 <MX_DAC_Init+0x50>)
|
|
80011aa: 601a str r2, [r3, #0]
|
|
if (HAL_DAC_Init(&hdac) != HAL_OK)
|
|
80011ac: 480d ldr r0, [pc, #52] ; (80011e4 <MX_DAC_Init+0x4c>)
|
|
80011ae: f004 fe6b bl 8005e88 <HAL_DAC_Init>
|
|
80011b2: 4603 mov r3, r0
|
|
80011b4: 2b00 cmp r3, #0
|
|
80011b6: d001 beq.n 80011bc <MX_DAC_Init+0x24>
|
|
{
|
|
Error_Handler();
|
|
80011b8: f001 fb5e bl 8002878 <Error_Handler>
|
|
}
|
|
/** DAC channel OUT1 config
|
|
*/
|
|
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
|
|
80011bc: 2300 movs r3, #0
|
|
80011be: 603b str r3, [r7, #0]
|
|
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
|
|
80011c0: 2300 movs r3, #0
|
|
80011c2: 607b str r3, [r7, #4]
|
|
if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
|
|
80011c4: 463b mov r3, r7
|
|
80011c6: 2200 movs r2, #0
|
|
80011c8: 4619 mov r1, r3
|
|
80011ca: 4806 ldr r0, [pc, #24] ; (80011e4 <MX_DAC_Init+0x4c>)
|
|
80011cc: f004 fed2 bl 8005f74 <HAL_DAC_ConfigChannel>
|
|
80011d0: 4603 mov r3, r0
|
|
80011d2: 2b00 cmp r3, #0
|
|
80011d4: d001 beq.n 80011da <MX_DAC_Init+0x42>
|
|
{
|
|
Error_Handler();
|
|
80011d6: f001 fb4f bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DAC_Init 2 */
|
|
|
|
/* USER CODE END DAC_Init 2 */
|
|
|
|
}
|
|
80011da: bf00 nop
|
|
80011dc: 3708 adds r7, #8
|
|
80011de: 46bd mov sp, r7
|
|
80011e0: bd80 pop {r7, pc}
|
|
80011e2: bf00 nop
|
|
80011e4: 20008ca8 .word 0x20008ca8
|
|
80011e8: 40007400 .word 0x40007400
|
|
|
|
080011ec <MX_DMA2D_Init>:
|
|
* @brief DMA2D Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DMA2D_Init(void)
|
|
{
|
|
80011ec: b580 push {r7, lr}
|
|
80011ee: af00 add r7, sp, #0
|
|
/* USER CODE END DMA2D_Init 0 */
|
|
|
|
/* USER CODE BEGIN DMA2D_Init 1 */
|
|
|
|
/* USER CODE END DMA2D_Init 1 */
|
|
hdma2d.Instance = DMA2D;
|
|
80011f0: 4b15 ldr r3, [pc, #84] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
80011f2: 4a16 ldr r2, [pc, #88] ; (800124c <MX_DMA2D_Init+0x60>)
|
|
80011f4: 601a str r2, [r3, #0]
|
|
hdma2d.Init.Mode = DMA2D_M2M;
|
|
80011f6: 4b14 ldr r3, [pc, #80] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
80011f8: 2200 movs r2, #0
|
|
80011fa: 605a str r2, [r3, #4]
|
|
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
|
|
80011fc: 4b12 ldr r3, [pc, #72] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
80011fe: 2200 movs r2, #0
|
|
8001200: 609a str r2, [r3, #8]
|
|
hdma2d.Init.OutputOffset = 0;
|
|
8001202: 4b11 ldr r3, [pc, #68] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
8001204: 2200 movs r2, #0
|
|
8001206: 60da str r2, [r3, #12]
|
|
hdma2d.LayerCfg[1].InputOffset = 0;
|
|
8001208: 4b0f ldr r3, [pc, #60] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
800120a: 2200 movs r2, #0
|
|
800120c: 629a str r2, [r3, #40] ; 0x28
|
|
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
|
|
800120e: 4b0e ldr r3, [pc, #56] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
8001210: 2200 movs r2, #0
|
|
8001212: 62da str r2, [r3, #44] ; 0x2c
|
|
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
|
|
8001214: 4b0c ldr r3, [pc, #48] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
8001216: 2200 movs r2, #0
|
|
8001218: 631a str r2, [r3, #48] ; 0x30
|
|
hdma2d.LayerCfg[1].InputAlpha = 0;
|
|
800121a: 4b0b ldr r3, [pc, #44] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
800121c: 2200 movs r2, #0
|
|
800121e: 635a str r2, [r3, #52] ; 0x34
|
|
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
|
|
8001220: 4809 ldr r0, [pc, #36] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
8001222: f005 f8bb bl 800639c <HAL_DMA2D_Init>
|
|
8001226: 4603 mov r3, r0
|
|
8001228: 2b00 cmp r3, #0
|
|
800122a: d001 beq.n 8001230 <MX_DMA2D_Init+0x44>
|
|
{
|
|
Error_Handler();
|
|
800122c: f001 fb24 bl 8002878 <Error_Handler>
|
|
}
|
|
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
|
|
8001230: 2101 movs r1, #1
|
|
8001232: 4805 ldr r0, [pc, #20] ; (8001248 <MX_DMA2D_Init+0x5c>)
|
|
8001234: f005 fa10 bl 8006658 <HAL_DMA2D_ConfigLayer>
|
|
8001238: 4603 mov r3, r0
|
|
800123a: 2b00 cmp r3, #0
|
|
800123c: d001 beq.n 8001242 <MX_DMA2D_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
800123e: f001 fb1b bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DMA2D_Init 2 */
|
|
|
|
/* USER CODE END DMA2D_Init 2 */
|
|
|
|
}
|
|
8001242: bf00 nop
|
|
8001244: bd80 pop {r7, pc}
|
|
8001246: bf00 nop
|
|
8001248: 20008db4 .word 0x20008db4
|
|
800124c: 4002b000 .word 0x4002b000
|
|
|
|
08001250 <MX_I2C1_Init>:
|
|
* @brief I2C1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C1_Init(void)
|
|
{
|
|
8001250: b580 push {r7, lr}
|
|
8001252: af00 add r7, sp, #0
|
|
/* USER CODE END I2C1_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C1_Init 1 */
|
|
|
|
/* USER CODE END I2C1_Init 1 */
|
|
hi2c1.Instance = I2C1;
|
|
8001254: 4b1b ldr r3, [pc, #108] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001256: 4a1c ldr r2, [pc, #112] ; (80012c8 <MX_I2C1_Init+0x78>)
|
|
8001258: 601a str r2, [r3, #0]
|
|
hi2c1.Init.Timing = 0x00C0EAFF;
|
|
800125a: 4b1a ldr r3, [pc, #104] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
800125c: 4a1b ldr r2, [pc, #108] ; (80012cc <MX_I2C1_Init+0x7c>)
|
|
800125e: 605a str r2, [r3, #4]
|
|
hi2c1.Init.OwnAddress1 = 0;
|
|
8001260: 4b18 ldr r3, [pc, #96] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001262: 2200 movs r2, #0
|
|
8001264: 609a str r2, [r3, #8]
|
|
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8001266: 4b17 ldr r3, [pc, #92] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001268: 2201 movs r2, #1
|
|
800126a: 60da str r2, [r3, #12]
|
|
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
800126c: 4b15 ldr r3, [pc, #84] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
800126e: 2200 movs r2, #0
|
|
8001270: 611a str r2, [r3, #16]
|
|
hi2c1.Init.OwnAddress2 = 0;
|
|
8001272: 4b14 ldr r3, [pc, #80] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001274: 2200 movs r2, #0
|
|
8001276: 615a str r2, [r3, #20]
|
|
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8001278: 4b12 ldr r3, [pc, #72] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
800127a: 2200 movs r2, #0
|
|
800127c: 619a str r2, [r3, #24]
|
|
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
800127e: 4b11 ldr r3, [pc, #68] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001280: 2200 movs r2, #0
|
|
8001282: 61da str r2, [r3, #28]
|
|
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8001284: 4b0f ldr r3, [pc, #60] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
8001286: 2200 movs r2, #0
|
|
8001288: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
|
|
800128a: 480e ldr r0, [pc, #56] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
800128c: f006 ff7e bl 800818c <HAL_I2C_Init>
|
|
8001290: 4603 mov r3, r0
|
|
8001292: 2b00 cmp r3, #0
|
|
8001294: d001 beq.n 800129a <MX_I2C1_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
8001296: f001 faef bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
800129a: 2100 movs r1, #0
|
|
800129c: 4809 ldr r0, [pc, #36] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
800129e: f007 fc8d bl 8008bbc <HAL_I2CEx_ConfigAnalogFilter>
|
|
80012a2: 4603 mov r3, r0
|
|
80012a4: 2b00 cmp r3, #0
|
|
80012a6: d001 beq.n 80012ac <MX_I2C1_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
80012a8: f001 fae6 bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
|
|
80012ac: 2100 movs r1, #0
|
|
80012ae: 4805 ldr r0, [pc, #20] ; (80012c4 <MX_I2C1_Init+0x74>)
|
|
80012b0: f007 fccf bl 8008c52 <HAL_I2CEx_ConfigDigitalFilter>
|
|
80012b4: 4603 mov r3, r0
|
|
80012b6: 2b00 cmp r3, #0
|
|
80012b8: d001 beq.n 80012be <MX_I2C1_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
80012ba: f001 fadd bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C1_Init 2 */
|
|
|
|
/* USER CODE END I2C1_Init 2 */
|
|
|
|
}
|
|
80012be: bf00 nop
|
|
80012c0: bd80 pop {r7, pc}
|
|
80012c2: bf00 nop
|
|
80012c4: 200089f0 .word 0x200089f0
|
|
80012c8: 40005400 .word 0x40005400
|
|
80012cc: 00c0eaff .word 0x00c0eaff
|
|
|
|
080012d0 <MX_I2C3_Init>:
|
|
* @brief I2C3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C3_Init(void)
|
|
{
|
|
80012d0: b580 push {r7, lr}
|
|
80012d2: af00 add r7, sp, #0
|
|
/* USER CODE END I2C3_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C3_Init 1 */
|
|
|
|
/* USER CODE END I2C3_Init 1 */
|
|
hi2c3.Instance = I2C3;
|
|
80012d4: 4b1b ldr r3, [pc, #108] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012d6: 4a1c ldr r2, [pc, #112] ; (8001348 <MX_I2C3_Init+0x78>)
|
|
80012d8: 601a str r2, [r3, #0]
|
|
hi2c3.Init.Timing = 0x00C0EAFF;
|
|
80012da: 4b1a ldr r3, [pc, #104] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012dc: 4a1b ldr r2, [pc, #108] ; (800134c <MX_I2C3_Init+0x7c>)
|
|
80012de: 605a str r2, [r3, #4]
|
|
hi2c3.Init.OwnAddress1 = 0;
|
|
80012e0: 4b18 ldr r3, [pc, #96] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012e2: 2200 movs r2, #0
|
|
80012e4: 609a str r2, [r3, #8]
|
|
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
80012e6: 4b17 ldr r3, [pc, #92] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012e8: 2201 movs r2, #1
|
|
80012ea: 60da str r2, [r3, #12]
|
|
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
80012ec: 4b15 ldr r3, [pc, #84] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012ee: 2200 movs r2, #0
|
|
80012f0: 611a str r2, [r3, #16]
|
|
hi2c3.Init.OwnAddress2 = 0;
|
|
80012f2: 4b14 ldr r3, [pc, #80] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012f4: 2200 movs r2, #0
|
|
80012f6: 615a str r2, [r3, #20]
|
|
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
80012f8: 4b12 ldr r3, [pc, #72] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
80012fa: 2200 movs r2, #0
|
|
80012fc: 619a str r2, [r3, #24]
|
|
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
80012fe: 4b11 ldr r3, [pc, #68] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
8001300: 2200 movs r2, #0
|
|
8001302: 61da str r2, [r3, #28]
|
|
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8001304: 4b0f ldr r3, [pc, #60] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
8001306: 2200 movs r2, #0
|
|
8001308: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
|
|
800130a: 480e ldr r0, [pc, #56] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
800130c: f006 ff3e bl 800818c <HAL_I2C_Init>
|
|
8001310: 4603 mov r3, r0
|
|
8001312: 2b00 cmp r3, #0
|
|
8001314: d001 beq.n 800131a <MX_I2C3_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
8001316: f001 faaf bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
800131a: 2100 movs r1, #0
|
|
800131c: 4809 ldr r0, [pc, #36] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
800131e: f007 fc4d bl 8008bbc <HAL_I2CEx_ConfigAnalogFilter>
|
|
8001322: 4603 mov r3, r0
|
|
8001324: 2b00 cmp r3, #0
|
|
8001326: d001 beq.n 800132c <MX_I2C3_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8001328: f001 faa6 bl 8002878 <Error_Handler>
|
|
}
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
|
|
800132c: 2100 movs r1, #0
|
|
800132e: 4805 ldr r0, [pc, #20] ; (8001344 <MX_I2C3_Init+0x74>)
|
|
8001330: f007 fc8f bl 8008c52 <HAL_I2CEx_ConfigDigitalFilter>
|
|
8001334: 4603 mov r3, r0
|
|
8001336: 2b00 cmp r3, #0
|
|
8001338: d001 beq.n 800133e <MX_I2C3_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
800133a: f001 fa9d bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C3_Init 2 */
|
|
|
|
/* USER CODE END I2C3_Init 2 */
|
|
|
|
}
|
|
800133e: bf00 nop
|
|
8001340: bd80 pop {r7, pc}
|
|
8001342: bf00 nop
|
|
8001344: 2000887c .word 0x2000887c
|
|
8001348: 40005c00 .word 0x40005c00
|
|
800134c: 00c0eaff .word 0x00c0eaff
|
|
|
|
08001350 <MX_LTDC_Init>:
|
|
* @brief LTDC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_LTDC_Init(void)
|
|
{
|
|
8001350: b580 push {r7, lr}
|
|
8001352: b08e sub sp, #56 ; 0x38
|
|
8001354: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN LTDC_Init 0 */
|
|
|
|
/* USER CODE END LTDC_Init 0 */
|
|
|
|
LTDC_LayerCfgTypeDef pLayerCfg = {0};
|
|
8001356: 1d3b adds r3, r7, #4
|
|
8001358: 2234 movs r2, #52 ; 0x34
|
|
800135a: 2100 movs r1, #0
|
|
800135c: 4618 mov r0, r3
|
|
800135e: f01b fca2 bl 801cca6 <memset>
|
|
|
|
/* USER CODE BEGIN LTDC_Init 1 */
|
|
|
|
/* USER CODE END LTDC_Init 1 */
|
|
hltdc.Instance = LTDC;
|
|
8001362: 4b3a ldr r3, [pc, #232] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001364: 4a3a ldr r2, [pc, #232] ; (8001450 <MX_LTDC_Init+0x100>)
|
|
8001366: 601a str r2, [r3, #0]
|
|
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
|
8001368: 4b38 ldr r3, [pc, #224] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
800136a: 2200 movs r2, #0
|
|
800136c: 605a str r2, [r3, #4]
|
|
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
|
800136e: 4b37 ldr r3, [pc, #220] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001370: 2200 movs r2, #0
|
|
8001372: 609a str r2, [r3, #8]
|
|
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
|
8001374: 4b35 ldr r3, [pc, #212] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001376: 2200 movs r2, #0
|
|
8001378: 60da str r2, [r3, #12]
|
|
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
|
800137a: 4b34 ldr r3, [pc, #208] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
800137c: 2200 movs r2, #0
|
|
800137e: 611a str r2, [r3, #16]
|
|
hltdc.Init.HorizontalSync = 40;
|
|
8001380: 4b32 ldr r3, [pc, #200] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001382: 2228 movs r2, #40 ; 0x28
|
|
8001384: 615a str r2, [r3, #20]
|
|
hltdc.Init.VerticalSync = 9;
|
|
8001386: 4b31 ldr r3, [pc, #196] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001388: 2209 movs r2, #9
|
|
800138a: 619a str r2, [r3, #24]
|
|
hltdc.Init.AccumulatedHBP = 53;
|
|
800138c: 4b2f ldr r3, [pc, #188] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
800138e: 2235 movs r2, #53 ; 0x35
|
|
8001390: 61da str r2, [r3, #28]
|
|
hltdc.Init.AccumulatedVBP = 11;
|
|
8001392: 4b2e ldr r3, [pc, #184] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001394: 220b movs r2, #11
|
|
8001396: 621a str r2, [r3, #32]
|
|
hltdc.Init.AccumulatedActiveW = 533;
|
|
8001398: 4b2c ldr r3, [pc, #176] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
800139a: f240 2215 movw r2, #533 ; 0x215
|
|
800139e: 625a str r2, [r3, #36] ; 0x24
|
|
hltdc.Init.AccumulatedActiveH = 283;
|
|
80013a0: 4b2a ldr r3, [pc, #168] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013a2: f240 121b movw r2, #283 ; 0x11b
|
|
80013a6: 629a str r2, [r3, #40] ; 0x28
|
|
hltdc.Init.TotalWidth = 565;
|
|
80013a8: 4b28 ldr r3, [pc, #160] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013aa: f240 2235 movw r2, #565 ; 0x235
|
|
80013ae: 62da str r2, [r3, #44] ; 0x2c
|
|
hltdc.Init.TotalHeigh = 285;
|
|
80013b0: 4b26 ldr r3, [pc, #152] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013b2: f240 121d movw r2, #285 ; 0x11d
|
|
80013b6: 631a str r2, [r3, #48] ; 0x30
|
|
hltdc.Init.Backcolor.Blue = 0;
|
|
80013b8: 4b24 ldr r3, [pc, #144] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013ba: 2200 movs r2, #0
|
|
80013bc: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
hltdc.Init.Backcolor.Green = 0;
|
|
80013c0: 4b22 ldr r3, [pc, #136] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013c2: 2200 movs r2, #0
|
|
80013c4: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
hltdc.Init.Backcolor.Red = 0;
|
|
80013c8: 4b20 ldr r3, [pc, #128] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013ca: 2200 movs r2, #0
|
|
80013cc: f883 2036 strb.w r2, [r3, #54] ; 0x36
|
|
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
|
|
80013d0: 481e ldr r0, [pc, #120] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
80013d2: f007 fc8b bl 8008cec <HAL_LTDC_Init>
|
|
80013d6: 4603 mov r3, r0
|
|
80013d8: 2b00 cmp r3, #0
|
|
80013da: d001 beq.n 80013e0 <MX_LTDC_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
80013dc: f001 fa4c bl 8002878 <Error_Handler>
|
|
}
|
|
pLayerCfg.WindowX0 = 0;
|
|
80013e0: 2300 movs r3, #0
|
|
80013e2: 607b str r3, [r7, #4]
|
|
pLayerCfg.WindowX1 = 480;
|
|
80013e4: f44f 73f0 mov.w r3, #480 ; 0x1e0
|
|
80013e8: 60bb str r3, [r7, #8]
|
|
pLayerCfg.WindowY0 = 0;
|
|
80013ea: 2300 movs r3, #0
|
|
80013ec: 60fb str r3, [r7, #12]
|
|
pLayerCfg.WindowY1 = 272;
|
|
80013ee: f44f 7388 mov.w r3, #272 ; 0x110
|
|
80013f2: 613b str r3, [r7, #16]
|
|
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
|
|
80013f4: 2302 movs r3, #2
|
|
80013f6: 617b str r3, [r7, #20]
|
|
pLayerCfg.Alpha = 255;
|
|
80013f8: 23ff movs r3, #255 ; 0xff
|
|
80013fa: 61bb str r3, [r7, #24]
|
|
pLayerCfg.Alpha0 = 0;
|
|
80013fc: 2300 movs r3, #0
|
|
80013fe: 61fb str r3, [r7, #28]
|
|
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
|
|
8001400: f44f 63c0 mov.w r3, #1536 ; 0x600
|
|
8001404: 623b str r3, [r7, #32]
|
|
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
|
|
8001406: 2307 movs r3, #7
|
|
8001408: 627b str r3, [r7, #36] ; 0x24
|
|
pLayerCfg.FBStartAdress = 0xC0000000;
|
|
800140a: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000
|
|
800140e: 62bb str r3, [r7, #40] ; 0x28
|
|
pLayerCfg.ImageWidth = 480;
|
|
8001410: f44f 73f0 mov.w r3, #480 ; 0x1e0
|
|
8001414: 62fb str r3, [r7, #44] ; 0x2c
|
|
pLayerCfg.ImageHeight = 272;
|
|
8001416: f44f 7388 mov.w r3, #272 ; 0x110
|
|
800141a: 633b str r3, [r7, #48] ; 0x30
|
|
pLayerCfg.Backcolor.Blue = 0;
|
|
800141c: 2300 movs r3, #0
|
|
800141e: f887 3034 strb.w r3, [r7, #52] ; 0x34
|
|
pLayerCfg.Backcolor.Green = 0;
|
|
8001422: 2300 movs r3, #0
|
|
8001424: f887 3035 strb.w r3, [r7, #53] ; 0x35
|
|
pLayerCfg.Backcolor.Red = 0;
|
|
8001428: 2300 movs r3, #0
|
|
800142a: f887 3036 strb.w r3, [r7, #54] ; 0x36
|
|
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
|
|
800142e: 1d3b adds r3, r7, #4
|
|
8001430: 2200 movs r2, #0
|
|
8001432: 4619 mov r1, r3
|
|
8001434: 4805 ldr r0, [pc, #20] ; (800144c <MX_LTDC_Init+0xfc>)
|
|
8001436: f007 fdeb bl 8009010 <HAL_LTDC_ConfigLayer>
|
|
800143a: 4603 mov r3, r0
|
|
800143c: 2b00 cmp r3, #0
|
|
800143e: d001 beq.n 8001444 <MX_LTDC_Init+0xf4>
|
|
{
|
|
Error_Handler();
|
|
8001440: f001 fa1a bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN LTDC_Init 2 */
|
|
|
|
/* USER CODE END LTDC_Init 2 */
|
|
|
|
}
|
|
8001444: bf00 nop
|
|
8001446: 3738 adds r7, #56 ; 0x38
|
|
8001448: 46bd mov sp, r7
|
|
800144a: bd80 pop {r7, pc}
|
|
800144c: 20008ae4 .word 0x20008ae4
|
|
8001450: 40016800 .word 0x40016800
|
|
|
|
08001454 <MX_RNG_Init>:
|
|
* @brief RNG Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_RNG_Init(void)
|
|
{
|
|
8001454: b580 push {r7, lr}
|
|
8001456: af00 add r7, sp, #0
|
|
/* USER CODE END RNG_Init 0 */
|
|
|
|
/* USER CODE BEGIN RNG_Init 1 */
|
|
|
|
/* USER CODE END RNG_Init 1 */
|
|
hrng.Instance = RNG;
|
|
8001458: 4b06 ldr r3, [pc, #24] ; (8001474 <MX_RNG_Init+0x20>)
|
|
800145a: 4a07 ldr r2, [pc, #28] ; (8001478 <MX_RNG_Init+0x24>)
|
|
800145c: 601a str r2, [r3, #0]
|
|
if (HAL_RNG_Init(&hrng) != HAL_OK)
|
|
800145e: 4805 ldr r0, [pc, #20] ; (8001474 <MX_RNG_Init+0x20>)
|
|
8001460: f009 f8b2 bl 800a5c8 <HAL_RNG_Init>
|
|
8001464: 4603 mov r3, r0
|
|
8001466: 2b00 cmp r3, #0
|
|
8001468: d001 beq.n 800146e <MX_RNG_Init+0x1a>
|
|
{
|
|
Error_Handler();
|
|
800146a: f001 fa05 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN RNG_Init 2 */
|
|
|
|
/* USER CODE END RNG_Init 2 */
|
|
|
|
}
|
|
800146e: bf00 nop
|
|
8001470: bd80 pop {r7, pc}
|
|
8001472: bf00 nop
|
|
8001474: 20008d20 .word 0x20008d20
|
|
8001478: 50060800 .word 0x50060800
|
|
|
|
0800147c <MX_RTC_Init>:
|
|
* @brief RTC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_RTC_Init(void)
|
|
{
|
|
800147c: b580 push {r7, lr}
|
|
800147e: b092 sub sp, #72 ; 0x48
|
|
8001480: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN RTC_Init 0 */
|
|
|
|
/* USER CODE END RTC_Init 0 */
|
|
|
|
RTC_TimeTypeDef sTime = {0};
|
|
8001482: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
8001486: 2200 movs r2, #0
|
|
8001488: 601a str r2, [r3, #0]
|
|
800148a: 605a str r2, [r3, #4]
|
|
800148c: 609a str r2, [r3, #8]
|
|
800148e: 60da str r2, [r3, #12]
|
|
8001490: 611a str r2, [r3, #16]
|
|
8001492: 615a str r2, [r3, #20]
|
|
RTC_DateTypeDef sDate = {0};
|
|
8001494: 2300 movs r3, #0
|
|
8001496: 62fb str r3, [r7, #44] ; 0x2c
|
|
RTC_AlarmTypeDef sAlarm = {0};
|
|
8001498: 463b mov r3, r7
|
|
800149a: 222c movs r2, #44 ; 0x2c
|
|
800149c: 2100 movs r1, #0
|
|
800149e: 4618 mov r0, r3
|
|
80014a0: f01b fc01 bl 801cca6 <memset>
|
|
/* USER CODE BEGIN RTC_Init 1 */
|
|
|
|
/* USER CODE END RTC_Init 1 */
|
|
/** Initialize RTC Only
|
|
*/
|
|
hrtc.Instance = RTC;
|
|
80014a4: 4b46 ldr r3, [pc, #280] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014a6: 4a47 ldr r2, [pc, #284] ; (80015c4 <MX_RTC_Init+0x148>)
|
|
80014a8: 601a str r2, [r3, #0]
|
|
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
|
|
80014aa: 4b45 ldr r3, [pc, #276] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014ac: 2200 movs r2, #0
|
|
80014ae: 605a str r2, [r3, #4]
|
|
hrtc.Init.AsynchPrediv = 127;
|
|
80014b0: 4b43 ldr r3, [pc, #268] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014b2: 227f movs r2, #127 ; 0x7f
|
|
80014b4: 609a str r2, [r3, #8]
|
|
hrtc.Init.SynchPrediv = 255;
|
|
80014b6: 4b42 ldr r3, [pc, #264] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014b8: 22ff movs r2, #255 ; 0xff
|
|
80014ba: 60da str r2, [r3, #12]
|
|
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
|
|
80014bc: 4b40 ldr r3, [pc, #256] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014be: 2200 movs r2, #0
|
|
80014c0: 611a str r2, [r3, #16]
|
|
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
|
80014c2: 4b3f ldr r3, [pc, #252] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014c4: 2200 movs r2, #0
|
|
80014c6: 615a str r2, [r3, #20]
|
|
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
|
80014c8: 4b3d ldr r3, [pc, #244] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014ca: 2200 movs r2, #0
|
|
80014cc: 619a str r2, [r3, #24]
|
|
if (HAL_RTC_Init(&hrtc) != HAL_OK)
|
|
80014ce: 483c ldr r0, [pc, #240] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80014d0: f009 f8a4 bl 800a61c <HAL_RTC_Init>
|
|
80014d4: 4603 mov r3, r0
|
|
80014d6: 2b00 cmp r3, #0
|
|
80014d8: d001 beq.n 80014de <MX_RTC_Init+0x62>
|
|
{
|
|
Error_Handler();
|
|
80014da: f001 f9cd bl 8002878 <Error_Handler>
|
|
|
|
/* USER CODE END Check_RTC_BKUP */
|
|
|
|
/** Initialize RTC and set the Time and Date
|
|
*/
|
|
sTime.Hours = 0x0;
|
|
80014de: 2300 movs r3, #0
|
|
80014e0: f887 3030 strb.w r3, [r7, #48] ; 0x30
|
|
sTime.Minutes = 0x0;
|
|
80014e4: 2300 movs r3, #0
|
|
80014e6: f887 3031 strb.w r3, [r7, #49] ; 0x31
|
|
sTime.Seconds = 0x0;
|
|
80014ea: 2300 movs r3, #0
|
|
80014ec: f887 3032 strb.w r3, [r7, #50] ; 0x32
|
|
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
|
|
80014f0: 2300 movs r3, #0
|
|
80014f2: 643b str r3, [r7, #64] ; 0x40
|
|
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
|
|
80014f4: 2300 movs r3, #0
|
|
80014f6: 647b str r3, [r7, #68] ; 0x44
|
|
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
|
|
80014f8: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
80014fc: 2201 movs r2, #1
|
|
80014fe: 4619 mov r1, r3
|
|
8001500: 482f ldr r0, [pc, #188] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
8001502: f009 f907 bl 800a714 <HAL_RTC_SetTime>
|
|
8001506: 4603 mov r3, r0
|
|
8001508: 2b00 cmp r3, #0
|
|
800150a: d001 beq.n 8001510 <MX_RTC_Init+0x94>
|
|
{
|
|
Error_Handler();
|
|
800150c: f001 f9b4 bl 8002878 <Error_Handler>
|
|
}
|
|
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
|
|
8001510: 2301 movs r3, #1
|
|
8001512: f887 302c strb.w r3, [r7, #44] ; 0x2c
|
|
sDate.Month = RTC_MONTH_JANUARY;
|
|
8001516: 2301 movs r3, #1
|
|
8001518: f887 302d strb.w r3, [r7, #45] ; 0x2d
|
|
sDate.Date = 0x1;
|
|
800151c: 2301 movs r3, #1
|
|
800151e: f887 302e strb.w r3, [r7, #46] ; 0x2e
|
|
sDate.Year = 0x0;
|
|
8001522: 2300 movs r3, #0
|
|
8001524: f887 302f strb.w r3, [r7, #47] ; 0x2f
|
|
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
|
|
8001528: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
800152c: 2201 movs r2, #1
|
|
800152e: 4619 mov r1, r3
|
|
8001530: 4823 ldr r0, [pc, #140] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
8001532: f009 f9ad bl 800a890 <HAL_RTC_SetDate>
|
|
8001536: 4603 mov r3, r0
|
|
8001538: 2b00 cmp r3, #0
|
|
800153a: d001 beq.n 8001540 <MX_RTC_Init+0xc4>
|
|
{
|
|
Error_Handler();
|
|
800153c: f001 f99c bl 8002878 <Error_Handler>
|
|
}
|
|
/** Enable the Alarm A
|
|
*/
|
|
sAlarm.AlarmTime.Hours = 0x0;
|
|
8001540: 2300 movs r3, #0
|
|
8001542: 703b strb r3, [r7, #0]
|
|
sAlarm.AlarmTime.Minutes = 0x0;
|
|
8001544: 2300 movs r3, #0
|
|
8001546: 707b strb r3, [r7, #1]
|
|
sAlarm.AlarmTime.Seconds = 0x0;
|
|
8001548: 2300 movs r3, #0
|
|
800154a: 70bb strb r3, [r7, #2]
|
|
sAlarm.AlarmTime.SubSeconds = 0x0;
|
|
800154c: 2300 movs r3, #0
|
|
800154e: 607b str r3, [r7, #4]
|
|
sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
|
|
8001550: 2300 movs r3, #0
|
|
8001552: 613b str r3, [r7, #16]
|
|
sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET;
|
|
8001554: 2300 movs r3, #0
|
|
8001556: 617b str r3, [r7, #20]
|
|
sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
|
|
8001558: 2300 movs r3, #0
|
|
800155a: 61bb str r3, [r7, #24]
|
|
sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL;
|
|
800155c: 2300 movs r3, #0
|
|
800155e: 61fb str r3, [r7, #28]
|
|
sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE;
|
|
8001560: 2300 movs r3, #0
|
|
8001562: 623b str r3, [r7, #32]
|
|
sAlarm.AlarmDateWeekDay = 0x1;
|
|
8001564: 2301 movs r3, #1
|
|
8001566: f887 3024 strb.w r3, [r7, #36] ; 0x24
|
|
sAlarm.Alarm = RTC_ALARM_A;
|
|
800156a: f44f 7380 mov.w r3, #256 ; 0x100
|
|
800156e: 62bb str r3, [r7, #40] ; 0x28
|
|
if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
|
|
8001570: 463b mov r3, r7
|
|
8001572: 2201 movs r2, #1
|
|
8001574: 4619 mov r1, r3
|
|
8001576: 4812 ldr r0, [pc, #72] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
8001578: f009 fa32 bl 800a9e0 <HAL_RTC_SetAlarm>
|
|
800157c: 4603 mov r3, r0
|
|
800157e: 2b00 cmp r3, #0
|
|
8001580: d001 beq.n 8001586 <MX_RTC_Init+0x10a>
|
|
{
|
|
Error_Handler();
|
|
8001582: f001 f979 bl 8002878 <Error_Handler>
|
|
}
|
|
/** Enable the Alarm B
|
|
*/
|
|
sAlarm.Alarm = RTC_ALARM_B;
|
|
8001586: f44f 7300 mov.w r3, #512 ; 0x200
|
|
800158a: 62bb str r3, [r7, #40] ; 0x28
|
|
if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
|
|
800158c: 463b mov r3, r7
|
|
800158e: 2201 movs r2, #1
|
|
8001590: 4619 mov r1, r3
|
|
8001592: 480b ldr r0, [pc, #44] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
8001594: f009 fa24 bl 800a9e0 <HAL_RTC_SetAlarm>
|
|
8001598: 4603 mov r3, r0
|
|
800159a: 2b00 cmp r3, #0
|
|
800159c: d001 beq.n 80015a2 <MX_RTC_Init+0x126>
|
|
{
|
|
Error_Handler();
|
|
800159e: f001 f96b bl 8002878 <Error_Handler>
|
|
}
|
|
/** Enable the TimeStamp
|
|
*/
|
|
if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_POS1) != HAL_OK)
|
|
80015a2: 2202 movs r2, #2
|
|
80015a4: 2100 movs r1, #0
|
|
80015a6: 4806 ldr r0, [pc, #24] ; (80015c0 <MX_RTC_Init+0x144>)
|
|
80015a8: f009 fba4 bl 800acf4 <HAL_RTCEx_SetTimeStamp>
|
|
80015ac: 4603 mov r3, r0
|
|
80015ae: 2b00 cmp r3, #0
|
|
80015b0: d001 beq.n 80015b6 <MX_RTC_Init+0x13a>
|
|
{
|
|
Error_Handler();
|
|
80015b2: f001 f961 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN RTC_Init 2 */
|
|
|
|
/* USER CODE END RTC_Init 2 */
|
|
|
|
}
|
|
80015b6: bf00 nop
|
|
80015b8: 3748 adds r7, #72 ; 0x48
|
|
80015ba: 46bd mov sp, r7
|
|
80015bc: bd80 pop {r7, pc}
|
|
80015be: bf00 nop
|
|
80015c0: 20008cc0 .word 0x20008cc0
|
|
80015c4: 40002800 .word 0x40002800
|
|
|
|
080015c8 <MX_SPI2_Init>:
|
|
* @brief SPI2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI2_Init(void)
|
|
{
|
|
80015c8: b580 push {r7, lr}
|
|
80015ca: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI2_Init 1 */
|
|
|
|
/* USER CODE END SPI2_Init 1 */
|
|
/* SPI2 parameter configuration*/
|
|
hspi2.Instance = SPI2;
|
|
80015cc: 4b1b ldr r3, [pc, #108] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015ce: 4a1c ldr r2, [pc, #112] ; (8001640 <MX_SPI2_Init+0x78>)
|
|
80015d0: 601a str r2, [r3, #0]
|
|
hspi2.Init.Mode = SPI_MODE_MASTER;
|
|
80015d2: 4b1a ldr r3, [pc, #104] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015d4: f44f 7282 mov.w r2, #260 ; 0x104
|
|
80015d8: 605a str r2, [r3, #4]
|
|
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
|
|
80015da: 4b18 ldr r3, [pc, #96] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015dc: 2200 movs r2, #0
|
|
80015de: 609a str r2, [r3, #8]
|
|
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
|
|
80015e0: 4b16 ldr r3, [pc, #88] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015e2: f44f 7240 mov.w r2, #768 ; 0x300
|
|
80015e6: 60da str r2, [r3, #12]
|
|
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
80015e8: 4b14 ldr r3, [pc, #80] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015ea: 2200 movs r2, #0
|
|
80015ec: 611a str r2, [r3, #16]
|
|
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
80015ee: 4b13 ldr r3, [pc, #76] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015f0: 2200 movs r2, #0
|
|
80015f2: 615a str r2, [r3, #20]
|
|
hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
|
|
80015f4: 4b11 ldr r3, [pc, #68] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015f6: f44f 2280 mov.w r2, #262144 ; 0x40000
|
|
80015fa: 619a str r2, [r3, #24]
|
|
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
80015fc: 4b0f ldr r3, [pc, #60] ; (800163c <MX_SPI2_Init+0x74>)
|
|
80015fe: 2200 movs r2, #0
|
|
8001600: 61da str r2, [r3, #28]
|
|
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8001602: 4b0e ldr r3, [pc, #56] ; (800163c <MX_SPI2_Init+0x74>)
|
|
8001604: 2200 movs r2, #0
|
|
8001606: 621a str r2, [r3, #32]
|
|
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
8001608: 4b0c ldr r3, [pc, #48] ; (800163c <MX_SPI2_Init+0x74>)
|
|
800160a: 2200 movs r2, #0
|
|
800160c: 625a str r2, [r3, #36] ; 0x24
|
|
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800160e: 4b0b ldr r3, [pc, #44] ; (800163c <MX_SPI2_Init+0x74>)
|
|
8001610: 2200 movs r2, #0
|
|
8001612: 629a str r2, [r3, #40] ; 0x28
|
|
hspi2.Init.CRCPolynomial = 7;
|
|
8001614: 4b09 ldr r3, [pc, #36] ; (800163c <MX_SPI2_Init+0x74>)
|
|
8001616: 2207 movs r2, #7
|
|
8001618: 62da str r2, [r3, #44] ; 0x2c
|
|
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
|
800161a: 4b08 ldr r3, [pc, #32] ; (800163c <MX_SPI2_Init+0x74>)
|
|
800161c: 2200 movs r2, #0
|
|
800161e: 631a str r2, [r3, #48] ; 0x30
|
|
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
|
8001620: 4b06 ldr r3, [pc, #24] ; (800163c <MX_SPI2_Init+0x74>)
|
|
8001622: 2208 movs r2, #8
|
|
8001624: 635a str r2, [r3, #52] ; 0x34
|
|
if (HAL_SPI_Init(&hspi2) != HAL_OK)
|
|
8001626: 4805 ldr r0, [pc, #20] ; (800163c <MX_SPI2_Init+0x74>)
|
|
8001628: f009 fc39 bl 800ae9e <HAL_SPI_Init>
|
|
800162c: 4603 mov r3, r0
|
|
800162e: 2b00 cmp r3, #0
|
|
8001630: d001 beq.n 8001636 <MX_SPI2_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8001632: f001 f921 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI2_Init 2 */
|
|
|
|
/* USER CODE END SPI2_Init 2 */
|
|
|
|
}
|
|
8001636: bf00 nop
|
|
8001638: bd80 pop {r7, pc}
|
|
800163a: bf00 nop
|
|
800163c: 200088c8 .word 0x200088c8
|
|
8001640: 40003800 .word 0x40003800
|
|
|
|
08001644 <MX_TIM1_Init>:
|
|
* @brief TIM1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM1_Init(void)
|
|
{
|
|
8001644: b580 push {r7, lr}
|
|
8001646: b088 sub sp, #32
|
|
8001648: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
800164a: f107 0310 add.w r3, r7, #16
|
|
800164e: 2200 movs r2, #0
|
|
8001650: 601a str r2, [r3, #0]
|
|
8001652: 605a str r2, [r3, #4]
|
|
8001654: 609a str r2, [r3, #8]
|
|
8001656: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001658: 1d3b adds r3, r7, #4
|
|
800165a: 2200 movs r2, #0
|
|
800165c: 601a str r2, [r3, #0]
|
|
800165e: 605a str r2, [r3, #4]
|
|
8001660: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
htim1.Instance = TIM1;
|
|
8001662: 4b20 ldr r3, [pc, #128] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
8001664: 4a20 ldr r2, [pc, #128] ; (80016e8 <MX_TIM1_Init+0xa4>)
|
|
8001666: 601a str r2, [r3, #0]
|
|
htim1.Init.Prescaler = 0;
|
|
8001668: 4b1e ldr r3, [pc, #120] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
800166a: 2200 movs r2, #0
|
|
800166c: 605a str r2, [r3, #4]
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800166e: 4b1d ldr r3, [pc, #116] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
8001670: 2200 movs r2, #0
|
|
8001672: 609a str r2, [r3, #8]
|
|
htim1.Init.Period = 65535;
|
|
8001674: 4b1b ldr r3, [pc, #108] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
8001676: f64f 72ff movw r2, #65535 ; 0xffff
|
|
800167a: 60da str r2, [r3, #12]
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800167c: 4b19 ldr r3, [pc, #100] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
800167e: 2200 movs r2, #0
|
|
8001680: 611a str r2, [r3, #16]
|
|
htim1.Init.RepetitionCounter = 0;
|
|
8001682: 4b18 ldr r3, [pc, #96] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
8001684: 2200 movs r2, #0
|
|
8001686: 615a str r2, [r3, #20]
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001688: 4b16 ldr r3, [pc, #88] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
800168a: 2200 movs r2, #0
|
|
800168c: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
800168e: 4815 ldr r0, [pc, #84] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
8001690: f009 fc97 bl 800afc2 <HAL_TIM_Base_Init>
|
|
8001694: 4603 mov r3, r0
|
|
8001696: 2b00 cmp r3, #0
|
|
8001698: d001 beq.n 800169e <MX_TIM1_Init+0x5a>
|
|
{
|
|
Error_Handler();
|
|
800169a: f001 f8ed bl 8002878 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
800169e: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80016a2: 613b str r3, [r7, #16]
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
80016a4: f107 0310 add.w r3, r7, #16
|
|
80016a8: 4619 mov r1, r3
|
|
80016aa: 480e ldr r0, [pc, #56] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
80016ac: f009 ff4a bl 800b544 <HAL_TIM_ConfigClockSource>
|
|
80016b0: 4603 mov r3, r0
|
|
80016b2: 2b00 cmp r3, #0
|
|
80016b4: d001 beq.n 80016ba <MX_TIM1_Init+0x76>
|
|
{
|
|
Error_Handler();
|
|
80016b6: f001 f8df bl 8002878 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80016ba: 2300 movs r3, #0
|
|
80016bc: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
|
|
80016be: 2300 movs r3, #0
|
|
80016c0: 60bb str r3, [r7, #8]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80016c2: 2300 movs r3, #0
|
|
80016c4: 60fb str r3, [r7, #12]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
80016c6: 1d3b adds r3, r7, #4
|
|
80016c8: 4619 mov r1, r3
|
|
80016ca: 4806 ldr r0, [pc, #24] ; (80016e4 <MX_TIM1_Init+0xa0>)
|
|
80016cc: f00a fc7e bl 800bfcc <HAL_TIMEx_MasterConfigSynchronization>
|
|
80016d0: 4603 mov r3, r0
|
|
80016d2: 2b00 cmp r3, #0
|
|
80016d4: d001 beq.n 80016da <MX_TIM1_Init+0x96>
|
|
{
|
|
Error_Handler();
|
|
80016d6: f001 f8cf bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
|
}
|
|
80016da: bf00 nop
|
|
80016dc: 3720 adds r7, #32
|
|
80016de: 46bd mov sp, r7
|
|
80016e0: bd80 pop {r7, pc}
|
|
80016e2: bf00 nop
|
|
80016e4: 20008ce0 .word 0x20008ce0
|
|
80016e8: 40010000 .word 0x40010000
|
|
|
|
080016ec <MX_TIM2_Init>:
|
|
* @brief TIM2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM2_Init(void)
|
|
{
|
|
80016ec: b580 push {r7, lr}
|
|
80016ee: b088 sub sp, #32
|
|
80016f0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM2_Init 0 */
|
|
|
|
/* USER CODE END TIM2_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
80016f2: f107 0310 add.w r3, r7, #16
|
|
80016f6: 2200 movs r2, #0
|
|
80016f8: 601a str r2, [r3, #0]
|
|
80016fa: 605a str r2, [r3, #4]
|
|
80016fc: 609a str r2, [r3, #8]
|
|
80016fe: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001700: 1d3b adds r3, r7, #4
|
|
8001702: 2200 movs r2, #0
|
|
8001704: 601a str r2, [r3, #0]
|
|
8001706: 605a str r2, [r3, #4]
|
|
8001708: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE BEGIN TIM2_Init 1 */
|
|
|
|
/* USER CODE END TIM2_Init 1 */
|
|
htim2.Instance = TIM2;
|
|
800170a: 4b1e ldr r3, [pc, #120] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
800170c: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
|
|
8001710: 601a str r2, [r3, #0]
|
|
htim2.Init.Prescaler = 0;
|
|
8001712: 4b1c ldr r3, [pc, #112] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
8001714: 2200 movs r2, #0
|
|
8001716: 605a str r2, [r3, #4]
|
|
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001718: 4b1a ldr r3, [pc, #104] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
800171a: 2200 movs r2, #0
|
|
800171c: 609a str r2, [r3, #8]
|
|
htim2.Init.Period = 4294967295;
|
|
800171e: 4b19 ldr r3, [pc, #100] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
8001720: f04f 32ff mov.w r2, #4294967295
|
|
8001724: 60da str r2, [r3, #12]
|
|
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001726: 4b17 ldr r3, [pc, #92] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
8001728: 2200 movs r2, #0
|
|
800172a: 611a str r2, [r3, #16]
|
|
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
800172c: 4b15 ldr r3, [pc, #84] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
800172e: 2200 movs r2, #0
|
|
8001730: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
|
|
8001732: 4814 ldr r0, [pc, #80] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
8001734: f009 fc45 bl 800afc2 <HAL_TIM_Base_Init>
|
|
8001738: 4603 mov r3, r0
|
|
800173a: 2b00 cmp r3, #0
|
|
800173c: d001 beq.n 8001742 <MX_TIM2_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
800173e: f001 f89b bl 8002878 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001742: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8001746: 613b str r3, [r7, #16]
|
|
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
|
|
8001748: f107 0310 add.w r3, r7, #16
|
|
800174c: 4619 mov r1, r3
|
|
800174e: 480d ldr r0, [pc, #52] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
8001750: f009 fef8 bl 800b544 <HAL_TIM_ConfigClockSource>
|
|
8001754: 4603 mov r3, r0
|
|
8001756: 2b00 cmp r3, #0
|
|
8001758: d001 beq.n 800175e <MX_TIM2_Init+0x72>
|
|
{
|
|
Error_Handler();
|
|
800175a: f001 f88d bl 8002878 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
800175e: 2300 movs r3, #0
|
|
8001760: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001762: 2300 movs r3, #0
|
|
8001764: 60fb str r3, [r7, #12]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
|
|
8001766: 1d3b adds r3, r7, #4
|
|
8001768: 4619 mov r1, r3
|
|
800176a: 4806 ldr r0, [pc, #24] ; (8001784 <MX_TIM2_Init+0x98>)
|
|
800176c: f00a fc2e bl 800bfcc <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001770: 4603 mov r3, r0
|
|
8001772: 2b00 cmp r3, #0
|
|
8001774: d001 beq.n 800177a <MX_TIM2_Init+0x8e>
|
|
{
|
|
Error_Handler();
|
|
8001776: f001 f87f bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM2_Init 2 */
|
|
|
|
/* USER CODE END TIM2_Init 2 */
|
|
|
|
}
|
|
800177a: bf00 nop
|
|
800177c: 3720 adds r7, #32
|
|
800177e: 46bd mov sp, r7
|
|
8001780: bd80 pop {r7, pc}
|
|
8001782: bf00 nop
|
|
8001784: 20008df4 .word 0x20008df4
|
|
|
|
08001788 <MX_TIM3_Init>:
|
|
* @brief TIM3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM3_Init(void)
|
|
{
|
|
8001788: b580 push {r7, lr}
|
|
800178a: b094 sub sp, #80 ; 0x50
|
|
800178c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM3_Init 0 */
|
|
|
|
/* USER CODE END TIM3_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
800178e: f107 0340 add.w r3, r7, #64 ; 0x40
|
|
8001792: 2200 movs r2, #0
|
|
8001794: 601a str r2, [r3, #0]
|
|
8001796: 605a str r2, [r3, #4]
|
|
8001798: 609a str r2, [r3, #8]
|
|
800179a: 60da str r2, [r3, #12]
|
|
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
|
|
800179c: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
80017a0: 2200 movs r2, #0
|
|
80017a2: 601a str r2, [r3, #0]
|
|
80017a4: 605a str r2, [r3, #4]
|
|
80017a6: 609a str r2, [r3, #8]
|
|
80017a8: 60da str r2, [r3, #12]
|
|
80017aa: 611a str r2, [r3, #16]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80017ac: f107 0320 add.w r3, r7, #32
|
|
80017b0: 2200 movs r2, #0
|
|
80017b2: 601a str r2, [r3, #0]
|
|
80017b4: 605a str r2, [r3, #4]
|
|
80017b6: 609a str r2, [r3, #8]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
80017b8: 1d3b adds r3, r7, #4
|
|
80017ba: 2200 movs r2, #0
|
|
80017bc: 601a str r2, [r3, #0]
|
|
80017be: 605a str r2, [r3, #4]
|
|
80017c0: 609a str r2, [r3, #8]
|
|
80017c2: 60da str r2, [r3, #12]
|
|
80017c4: 611a str r2, [r3, #16]
|
|
80017c6: 615a str r2, [r3, #20]
|
|
80017c8: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE BEGIN TIM3_Init 1 */
|
|
|
|
/* USER CODE END TIM3_Init 1 */
|
|
htim3.Instance = TIM3;
|
|
80017ca: 4b34 ldr r3, [pc, #208] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017cc: 4a34 ldr r2, [pc, #208] ; (80018a0 <MX_TIM3_Init+0x118>)
|
|
80017ce: 601a str r2, [r3, #0]
|
|
htim3.Init.Prescaler = 0;
|
|
80017d0: 4b32 ldr r3, [pc, #200] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017d2: 2200 movs r2, #0
|
|
80017d4: 605a str r2, [r3, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
80017d6: 4b31 ldr r3, [pc, #196] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017d8: 2200 movs r2, #0
|
|
80017da: 609a str r2, [r3, #8]
|
|
htim3.Init.Period = 65535;
|
|
80017dc: 4b2f ldr r3, [pc, #188] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017de: f64f 72ff movw r2, #65535 ; 0xffff
|
|
80017e2: 60da str r2, [r3, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80017e4: 4b2d ldr r3, [pc, #180] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017e6: 2200 movs r2, #0
|
|
80017e8: 611a str r2, [r3, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80017ea: 4b2c ldr r3, [pc, #176] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017ec: 2200 movs r2, #0
|
|
80017ee: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
|
|
80017f0: 482a ldr r0, [pc, #168] ; (800189c <MX_TIM3_Init+0x114>)
|
|
80017f2: f009 fbe6 bl 800afc2 <HAL_TIM_Base_Init>
|
|
80017f6: 4603 mov r3, r0
|
|
80017f8: 2b00 cmp r3, #0
|
|
80017fa: d001 beq.n 8001800 <MX_TIM3_Init+0x78>
|
|
{
|
|
Error_Handler();
|
|
80017fc: f001 f83c bl 8002878 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001800: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8001804: 643b str r3, [r7, #64] ; 0x40
|
|
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
|
|
8001806: f107 0340 add.w r3, r7, #64 ; 0x40
|
|
800180a: 4619 mov r1, r3
|
|
800180c: 4823 ldr r0, [pc, #140] ; (800189c <MX_TIM3_Init+0x114>)
|
|
800180e: f009 fe99 bl 800b544 <HAL_TIM_ConfigClockSource>
|
|
8001812: 4603 mov r3, r0
|
|
8001814: 2b00 cmp r3, #0
|
|
8001816: d001 beq.n 800181c <MX_TIM3_Init+0x94>
|
|
{
|
|
Error_Handler();
|
|
8001818: f001 f82e bl 8002878 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
|
|
800181c: 481f ldr r0, [pc, #124] ; (800189c <MX_TIM3_Init+0x114>)
|
|
800181e: f009 fc25 bl 800b06c <HAL_TIM_PWM_Init>
|
|
8001822: 4603 mov r3, r0
|
|
8001824: 2b00 cmp r3, #0
|
|
8001826: d001 beq.n 800182c <MX_TIM3_Init+0xa4>
|
|
{
|
|
Error_Handler();
|
|
8001828: f001 f826 bl 8002878 <Error_Handler>
|
|
}
|
|
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE;
|
|
800182c: 2300 movs r3, #0
|
|
800182e: 62fb str r3, [r7, #44] ; 0x2c
|
|
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
|
|
8001830: 2300 movs r3, #0
|
|
8001832: 633b str r3, [r7, #48] ; 0x30
|
|
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
|
|
8001834: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001838: 4619 mov r1, r3
|
|
800183a: 4818 ldr r0, [pc, #96] ; (800189c <MX_TIM3_Init+0x114>)
|
|
800183c: f009 ff3c bl 800b6b8 <HAL_TIM_SlaveConfigSynchro>
|
|
8001840: 4603 mov r3, r0
|
|
8001842: 2b00 cmp r3, #0
|
|
8001844: d001 beq.n 800184a <MX_TIM3_Init+0xc2>
|
|
{
|
|
Error_Handler();
|
|
8001846: f001 f817 bl 8002878 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
800184a: 2300 movs r3, #0
|
|
800184c: 623b str r3, [r7, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
800184e: 2300 movs r3, #0
|
|
8001850: 62bb str r3, [r7, #40] ; 0x28
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8001852: f107 0320 add.w r3, r7, #32
|
|
8001856: 4619 mov r1, r3
|
|
8001858: 4810 ldr r0, [pc, #64] ; (800189c <MX_TIM3_Init+0x114>)
|
|
800185a: f00a fbb7 bl 800bfcc <HAL_TIMEx_MasterConfigSynchronization>
|
|
800185e: 4603 mov r3, r0
|
|
8001860: 2b00 cmp r3, #0
|
|
8001862: d001 beq.n 8001868 <MX_TIM3_Init+0xe0>
|
|
{
|
|
Error_Handler();
|
|
8001864: f001 f808 bl 8002878 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8001868: 2360 movs r3, #96 ; 0x60
|
|
800186a: 607b str r3, [r7, #4]
|
|
sConfigOC.Pulse = 0;
|
|
800186c: 2300 movs r3, #0
|
|
800186e: 60bb str r3, [r7, #8]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8001870: 2300 movs r3, #0
|
|
8001872: 60fb str r3, [r7, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8001874: 2300 movs r3, #0
|
|
8001876: 617b str r3, [r7, #20]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8001878: 1d3b adds r3, r7, #4
|
|
800187a: 2200 movs r2, #0
|
|
800187c: 4619 mov r1, r3
|
|
800187e: 4807 ldr r0, [pc, #28] ; (800189c <MX_TIM3_Init+0x114>)
|
|
8001880: f009 fd48 bl 800b314 <HAL_TIM_PWM_ConfigChannel>
|
|
8001884: 4603 mov r3, r0
|
|
8001886: 2b00 cmp r3, #0
|
|
8001888: d001 beq.n 800188e <MX_TIM3_Init+0x106>
|
|
{
|
|
Error_Handler();
|
|
800188a: f000 fff5 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM3_Init 2 */
|
|
|
|
/* USER CODE END TIM3_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim3);
|
|
800188e: 4803 ldr r0, [pc, #12] ; (800189c <MX_TIM3_Init+0x114>)
|
|
8001890: f003 f9d2 bl 8004c38 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8001894: bf00 nop
|
|
8001896: 3750 adds r7, #80 ; 0x50
|
|
8001898: 46bd mov sp, r7
|
|
800189a: bd80 pop {r7, pc}
|
|
800189c: 20008aa4 .word 0x20008aa4
|
|
80018a0: 40000400 .word 0x40000400
|
|
|
|
080018a4 <MX_TIM5_Init>:
|
|
* @brief TIM5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM5_Init(void)
|
|
{
|
|
80018a4: b580 push {r7, lr}
|
|
80018a6: b088 sub sp, #32
|
|
80018a8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM5_Init 0 */
|
|
|
|
/* USER CODE END TIM5_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
80018aa: f107 0310 add.w r3, r7, #16
|
|
80018ae: 2200 movs r2, #0
|
|
80018b0: 601a str r2, [r3, #0]
|
|
80018b2: 605a str r2, [r3, #4]
|
|
80018b4: 609a str r2, [r3, #8]
|
|
80018b6: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80018b8: 1d3b adds r3, r7, #4
|
|
80018ba: 2200 movs r2, #0
|
|
80018bc: 601a str r2, [r3, #0]
|
|
80018be: 605a str r2, [r3, #4]
|
|
80018c0: 609a str r2, [r3, #8]
|
|
|
|
/* USER CODE BEGIN TIM5_Init 1 */
|
|
|
|
/* USER CODE END TIM5_Init 1 */
|
|
htim5.Instance = TIM5;
|
|
80018c2: 4b1d ldr r3, [pc, #116] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018c4: 4a1d ldr r2, [pc, #116] ; (800193c <MX_TIM5_Init+0x98>)
|
|
80018c6: 601a str r2, [r3, #0]
|
|
htim5.Init.Prescaler = 0;
|
|
80018c8: 4b1b ldr r3, [pc, #108] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018ca: 2200 movs r2, #0
|
|
80018cc: 605a str r2, [r3, #4]
|
|
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
80018ce: 4b1a ldr r3, [pc, #104] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018d0: 2200 movs r2, #0
|
|
80018d2: 609a str r2, [r3, #8]
|
|
htim5.Init.Period = 4294967295;
|
|
80018d4: 4b18 ldr r3, [pc, #96] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018d6: f04f 32ff mov.w r2, #4294967295
|
|
80018da: 60da str r2, [r3, #12]
|
|
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
80018dc: 4b16 ldr r3, [pc, #88] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018de: 2200 movs r2, #0
|
|
80018e0: 611a str r2, [r3, #16]
|
|
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80018e2: 4b15 ldr r3, [pc, #84] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018e4: 2200 movs r2, #0
|
|
80018e6: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
|
|
80018e8: 4813 ldr r0, [pc, #76] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
80018ea: f009 fb6a bl 800afc2 <HAL_TIM_Base_Init>
|
|
80018ee: 4603 mov r3, r0
|
|
80018f0: 2b00 cmp r3, #0
|
|
80018f2: d001 beq.n 80018f8 <MX_TIM5_Init+0x54>
|
|
{
|
|
Error_Handler();
|
|
80018f4: f000 ffc0 bl 8002878 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
80018f8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80018fc: 613b str r3, [r7, #16]
|
|
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
|
|
80018fe: f107 0310 add.w r3, r7, #16
|
|
8001902: 4619 mov r1, r3
|
|
8001904: 480c ldr r0, [pc, #48] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
8001906: f009 fe1d bl 800b544 <HAL_TIM_ConfigClockSource>
|
|
800190a: 4603 mov r3, r0
|
|
800190c: 2b00 cmp r3, #0
|
|
800190e: d001 beq.n 8001914 <MX_TIM5_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
8001910: f000 ffb2 bl 8002878 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8001914: 2300 movs r3, #0
|
|
8001916: 607b str r3, [r7, #4]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001918: 2300 movs r3, #0
|
|
800191a: 60fb str r3, [r7, #12]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
|
|
800191c: 1d3b adds r3, r7, #4
|
|
800191e: 4619 mov r1, r3
|
|
8001920: 4805 ldr r0, [pc, #20] ; (8001938 <MX_TIM5_Init+0x94>)
|
|
8001922: f00a fb53 bl 800bfcc <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001926: 4603 mov r3, r0
|
|
8001928: 2b00 cmp r3, #0
|
|
800192a: d001 beq.n 8001930 <MX_TIM5_Init+0x8c>
|
|
{
|
|
Error_Handler();
|
|
800192c: f000 ffa4 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM5_Init 2 */
|
|
|
|
/* USER CODE END TIM5_Init 2 */
|
|
|
|
}
|
|
8001930: bf00 nop
|
|
8001932: 3720 adds r7, #32
|
|
8001934: 46bd mov sp, r7
|
|
8001936: bd80 pop {r7, pc}
|
|
8001938: 20008a64 .word 0x20008a64
|
|
800193c: 40000c00 .word 0x40000c00
|
|
|
|
08001940 <MX_TIM8_Init>:
|
|
* @brief TIM8 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM8_Init(void)
|
|
{
|
|
8001940: b580 push {r7, lr}
|
|
8001942: b09a sub sp, #104 ; 0x68
|
|
8001944: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM8_Init 0 */
|
|
|
|
/* USER CODE END TIM8_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8001946: f107 0358 add.w r3, r7, #88 ; 0x58
|
|
800194a: 2200 movs r2, #0
|
|
800194c: 601a str r2, [r3, #0]
|
|
800194e: 605a str r2, [r3, #4]
|
|
8001950: 609a str r2, [r3, #8]
|
|
8001952: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001954: f107 034c add.w r3, r7, #76 ; 0x4c
|
|
8001958: 2200 movs r2, #0
|
|
800195a: 601a str r2, [r3, #0]
|
|
800195c: 605a str r2, [r3, #4]
|
|
800195e: 609a str r2, [r3, #8]
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8001960: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
8001964: 2200 movs r2, #0
|
|
8001966: 601a str r2, [r3, #0]
|
|
8001968: 605a str r2, [r3, #4]
|
|
800196a: 609a str r2, [r3, #8]
|
|
800196c: 60da str r2, [r3, #12]
|
|
800196e: 611a str r2, [r3, #16]
|
|
8001970: 615a str r2, [r3, #20]
|
|
8001972: 619a str r2, [r3, #24]
|
|
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
|
|
8001974: 1d3b adds r3, r7, #4
|
|
8001976: 222c movs r2, #44 ; 0x2c
|
|
8001978: 2100 movs r1, #0
|
|
800197a: 4618 mov r0, r3
|
|
800197c: f01b f993 bl 801cca6 <memset>
|
|
|
|
/* USER CODE BEGIN TIM8_Init 1 */
|
|
|
|
/* USER CODE END TIM8_Init 1 */
|
|
htim8.Instance = TIM8;
|
|
8001980: 4b42 ldr r3, [pc, #264] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001982: 4a43 ldr r2, [pc, #268] ; (8001a90 <MX_TIM8_Init+0x150>)
|
|
8001984: 601a str r2, [r3, #0]
|
|
htim8.Init.Prescaler = 0;
|
|
8001986: 4b41 ldr r3, [pc, #260] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001988: 2200 movs r2, #0
|
|
800198a: 605a str r2, [r3, #4]
|
|
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800198c: 4b3f ldr r3, [pc, #252] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
800198e: 2200 movs r2, #0
|
|
8001990: 609a str r2, [r3, #8]
|
|
htim8.Init.Period = 65535;
|
|
8001992: 4b3e ldr r3, [pc, #248] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001994: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8001998: 60da str r2, [r3, #12]
|
|
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800199a: 4b3c ldr r3, [pc, #240] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
800199c: 2200 movs r2, #0
|
|
800199e: 611a str r2, [r3, #16]
|
|
htim8.Init.RepetitionCounter = 0;
|
|
80019a0: 4b3a ldr r3, [pc, #232] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019a2: 2200 movs r2, #0
|
|
80019a4: 615a str r2, [r3, #20]
|
|
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80019a6: 4b39 ldr r3, [pc, #228] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019a8: 2200 movs r2, #0
|
|
80019aa: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
|
|
80019ac: 4837 ldr r0, [pc, #220] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019ae: f009 fb08 bl 800afc2 <HAL_TIM_Base_Init>
|
|
80019b2: 4603 mov r3, r0
|
|
80019b4: 2b00 cmp r3, #0
|
|
80019b6: d001 beq.n 80019bc <MX_TIM8_Init+0x7c>
|
|
{
|
|
Error_Handler();
|
|
80019b8: f000 ff5e bl 8002878 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
80019bc: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
80019c0: 65bb str r3, [r7, #88] ; 0x58
|
|
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
|
|
80019c2: f107 0358 add.w r3, r7, #88 ; 0x58
|
|
80019c6: 4619 mov r1, r3
|
|
80019c8: 4830 ldr r0, [pc, #192] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019ca: f009 fdbb bl 800b544 <HAL_TIM_ConfigClockSource>
|
|
80019ce: 4603 mov r3, r0
|
|
80019d0: 2b00 cmp r3, #0
|
|
80019d2: d001 beq.n 80019d8 <MX_TIM8_Init+0x98>
|
|
{
|
|
Error_Handler();
|
|
80019d4: f000 ff50 bl 8002878 <Error_Handler>
|
|
}
|
|
if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
|
|
80019d8: 482c ldr r0, [pc, #176] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019da: f009 fb47 bl 800b06c <HAL_TIM_PWM_Init>
|
|
80019de: 4603 mov r3, r0
|
|
80019e0: 2b00 cmp r3, #0
|
|
80019e2: d001 beq.n 80019e8 <MX_TIM8_Init+0xa8>
|
|
{
|
|
Error_Handler();
|
|
80019e4: f000 ff48 bl 8002878 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80019e8: 2300 movs r3, #0
|
|
80019ea: 64fb str r3, [r7, #76] ; 0x4c
|
|
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
|
|
80019ec: 2300 movs r3, #0
|
|
80019ee: 653b str r3, [r7, #80] ; 0x50
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80019f0: 2300 movs r3, #0
|
|
80019f2: 657b str r3, [r7, #84] ; 0x54
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
|
|
80019f4: f107 034c add.w r3, r7, #76 ; 0x4c
|
|
80019f8: 4619 mov r1, r3
|
|
80019fa: 4824 ldr r0, [pc, #144] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
80019fc: f00a fae6 bl 800bfcc <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001a00: 4603 mov r3, r0
|
|
8001a02: 2b00 cmp r3, #0
|
|
8001a04: d001 beq.n 8001a0a <MX_TIM8_Init+0xca>
|
|
{
|
|
Error_Handler();
|
|
8001a06: f000 ff37 bl 8002878 <Error_Handler>
|
|
}
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8001a0a: 2360 movs r3, #96 ; 0x60
|
|
8001a0c: 633b str r3, [r7, #48] ; 0x30
|
|
sConfigOC.Pulse = 0;
|
|
8001a0e: 2300 movs r3, #0
|
|
8001a10: 637b str r3, [r7, #52] ; 0x34
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8001a12: 2300 movs r3, #0
|
|
8001a14: 63bb str r3, [r7, #56] ; 0x38
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8001a16: 2300 movs r3, #0
|
|
8001a18: 643b str r3, [r7, #64] ; 0x40
|
|
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
|
|
8001a1a: 2300 movs r3, #0
|
|
8001a1c: 647b str r3, [r7, #68] ; 0x44
|
|
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
|
8001a1e: 2300 movs r3, #0
|
|
8001a20: 64bb str r3, [r7, #72] ; 0x48
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
|
|
8001a22: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
8001a26: 220c movs r2, #12
|
|
8001a28: 4619 mov r1, r3
|
|
8001a2a: 4818 ldr r0, [pc, #96] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001a2c: f009 fc72 bl 800b314 <HAL_TIM_PWM_ConfigChannel>
|
|
8001a30: 4603 mov r3, r0
|
|
8001a32: 2b00 cmp r3, #0
|
|
8001a34: d001 beq.n 8001a3a <MX_TIM8_Init+0xfa>
|
|
{
|
|
Error_Handler();
|
|
8001a36: f000 ff1f bl 8002878 <Error_Handler>
|
|
}
|
|
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
|
8001a3a: 2300 movs r3, #0
|
|
8001a3c: 607b str r3, [r7, #4]
|
|
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
|
8001a3e: 2300 movs r3, #0
|
|
8001a40: 60bb str r3, [r7, #8]
|
|
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
|
8001a42: 2300 movs r3, #0
|
|
8001a44: 60fb str r3, [r7, #12]
|
|
sBreakDeadTimeConfig.DeadTime = 0;
|
|
8001a46: 2300 movs r3, #0
|
|
8001a48: 613b str r3, [r7, #16]
|
|
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
|
|
8001a4a: 2300 movs r3, #0
|
|
8001a4c: 617b str r3, [r7, #20]
|
|
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
|
8001a4e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8001a52: 61bb str r3, [r7, #24]
|
|
sBreakDeadTimeConfig.BreakFilter = 0;
|
|
8001a54: 2300 movs r3, #0
|
|
8001a56: 61fb str r3, [r7, #28]
|
|
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
|
|
8001a58: 2300 movs r3, #0
|
|
8001a5a: 623b str r3, [r7, #32]
|
|
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
|
|
8001a5c: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8001a60: 627b str r3, [r7, #36] ; 0x24
|
|
sBreakDeadTimeConfig.Break2Filter = 0;
|
|
8001a62: 2300 movs r3, #0
|
|
8001a64: 62bb str r3, [r7, #40] ; 0x28
|
|
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
|
8001a66: 2300 movs r3, #0
|
|
8001a68: 62fb str r3, [r7, #44] ; 0x2c
|
|
if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
|
|
8001a6a: 1d3b adds r3, r7, #4
|
|
8001a6c: 4619 mov r1, r3
|
|
8001a6e: 4807 ldr r0, [pc, #28] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001a70: f00a fb3a bl 800c0e8 <HAL_TIMEx_ConfigBreakDeadTime>
|
|
8001a74: 4603 mov r3, r0
|
|
8001a76: 2b00 cmp r3, #0
|
|
8001a78: d001 beq.n 8001a7e <MX_TIM8_Init+0x13e>
|
|
{
|
|
Error_Handler();
|
|
8001a7a: f000 fefd bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM8_Init 2 */
|
|
|
|
/* USER CODE END TIM8_Init 2 */
|
|
HAL_TIM_MspPostInit(&htim8);
|
|
8001a7e: 4803 ldr r0, [pc, #12] ; (8001a8c <MX_TIM8_Init+0x14c>)
|
|
8001a80: f003 f8da bl 8004c38 <HAL_TIM_MspPostInit>
|
|
|
|
}
|
|
8001a84: bf00 nop
|
|
8001a86: 3768 adds r7, #104 ; 0x68
|
|
8001a88: 46bd mov sp, r7
|
|
8001a8a: bd80 pop {r7, pc}
|
|
8001a8c: 200089ac .word 0x200089ac
|
|
8001a90: 40010400 .word 0x40010400
|
|
|
|
08001a94 <MX_UART7_Init>:
|
|
* @brief UART7 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_UART7_Init(void)
|
|
{
|
|
8001a94: b580 push {r7, lr}
|
|
8001a96: af00 add r7, sp, #0
|
|
/* USER CODE END UART7_Init 0 */
|
|
|
|
/* USER CODE BEGIN UART7_Init 1 */
|
|
|
|
/* USER CODE END UART7_Init 1 */
|
|
huart7.Instance = UART7;
|
|
8001a98: 4b14 ldr r3, [pc, #80] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001a9a: 4a15 ldr r2, [pc, #84] ; (8001af0 <MX_UART7_Init+0x5c>)
|
|
8001a9c: 601a str r2, [r3, #0]
|
|
huart7.Init.BaudRate = 115200;
|
|
8001a9e: 4b13 ldr r3, [pc, #76] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001aa0: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
8001aa4: 605a str r2, [r3, #4]
|
|
huart7.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001aa6: 4b11 ldr r3, [pc, #68] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001aa8: 2200 movs r2, #0
|
|
8001aaa: 609a str r2, [r3, #8]
|
|
huart7.Init.StopBits = UART_STOPBITS_1;
|
|
8001aac: 4b0f ldr r3, [pc, #60] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001aae: 2200 movs r2, #0
|
|
8001ab0: 60da str r2, [r3, #12]
|
|
huart7.Init.Parity = UART_PARITY_NONE;
|
|
8001ab2: 4b0e ldr r3, [pc, #56] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001ab4: 2200 movs r2, #0
|
|
8001ab6: 611a str r2, [r3, #16]
|
|
huart7.Init.Mode = UART_MODE_TX_RX;
|
|
8001ab8: 4b0c ldr r3, [pc, #48] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001aba: 220c movs r2, #12
|
|
8001abc: 615a str r2, [r3, #20]
|
|
huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001abe: 4b0b ldr r3, [pc, #44] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001ac0: 2200 movs r2, #0
|
|
8001ac2: 619a str r2, [r3, #24]
|
|
huart7.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001ac4: 4b09 ldr r3, [pc, #36] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001ac6: 2200 movs r2, #0
|
|
8001ac8: 61da str r2, [r3, #28]
|
|
huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001aca: 4b08 ldr r3, [pc, #32] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001acc: 2200 movs r2, #0
|
|
8001ace: 621a str r2, [r3, #32]
|
|
huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001ad0: 4b06 ldr r3, [pc, #24] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001ad2: 2200 movs r2, #0
|
|
8001ad4: 625a str r2, [r3, #36] ; 0x24
|
|
if (HAL_UART_Init(&huart7) != HAL_OK)
|
|
8001ad6: 4805 ldr r0, [pc, #20] ; (8001aec <MX_UART7_Init+0x58>)
|
|
8001ad8: f00a fba2 bl 800c220 <HAL_UART_Init>
|
|
8001adc: 4603 mov r3, r0
|
|
8001ade: 2b00 cmp r3, #0
|
|
8001ae0: d001 beq.n 8001ae6 <MX_UART7_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8001ae2: f000 fec9 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN UART7_Init 2 */
|
|
|
|
/* USER CODE END UART7_Init 2 */
|
|
|
|
}
|
|
8001ae6: bf00 nop
|
|
8001ae8: bd80 pop {r7, pc}
|
|
8001aea: bf00 nop
|
|
8001aec: 2000892c .word 0x2000892c
|
|
8001af0: 40007800 .word 0x40007800
|
|
|
|
08001af4 <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8001af4: b580 push {r7, lr}
|
|
8001af6: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8001af8: 4b14 ldr r3, [pc, #80] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001afa: 4a15 ldr r2, [pc, #84] ; (8001b50 <MX_USART1_UART_Init+0x5c>)
|
|
8001afc: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8001afe: 4b13 ldr r3, [pc, #76] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b00: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
8001b04: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001b06: 4b11 ldr r3, [pc, #68] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b08: 2200 movs r2, #0
|
|
8001b0a: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8001b0c: 4b0f ldr r3, [pc, #60] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b0e: 2200 movs r2, #0
|
|
8001b10: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8001b12: 4b0e ldr r3, [pc, #56] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b14: 2200 movs r2, #0
|
|
8001b16: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8001b18: 4b0c ldr r3, [pc, #48] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b1a: 220c movs r2, #12
|
|
8001b1c: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001b1e: 4b0b ldr r3, [pc, #44] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b20: 2200 movs r2, #0
|
|
8001b22: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001b24: 4b09 ldr r3, [pc, #36] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b26: 2200 movs r2, #0
|
|
8001b28: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001b2a: 4b08 ldr r3, [pc, #32] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b2c: 2200 movs r2, #0
|
|
8001b2e: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001b30: 4b06 ldr r3, [pc, #24] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b32: 2200 movs r2, #0
|
|
8001b34: 625a str r2, [r3, #36] ; 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8001b36: 4805 ldr r0, [pc, #20] ; (8001b4c <MX_USART1_UART_Init+0x58>)
|
|
8001b38: f00a fb72 bl 800c220 <HAL_UART_Init>
|
|
8001b3c: 4603 mov r3, r0
|
|
8001b3e: 2b00 cmp r3, #0
|
|
8001b40: d001 beq.n 8001b46 <MX_USART1_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8001b42: f000 fe99 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8001b46: bf00 nop
|
|
8001b48: bd80 pop {r7, pc}
|
|
8001b4a: bf00 nop
|
|
8001b4c: 20008c20 .word 0x20008c20
|
|
8001b50: 40011000 .word 0x40011000
|
|
|
|
08001b54 <MX_USART6_UART_Init>:
|
|
* @brief USART6 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART6_UART_Init(void)
|
|
{
|
|
8001b54: b580 push {r7, lr}
|
|
8001b56: af00 add r7, sp, #0
|
|
/* USER CODE END USART6_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART6_Init 1 */
|
|
|
|
/* USER CODE END USART6_Init 1 */
|
|
huart6.Instance = USART6;
|
|
8001b58: 4b14 ldr r3, [pc, #80] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b5a: 4a15 ldr r2, [pc, #84] ; (8001bb0 <MX_USART6_UART_Init+0x5c>)
|
|
8001b5c: 601a str r2, [r3, #0]
|
|
huart6.Init.BaudRate = 115200;
|
|
8001b5e: 4b13 ldr r3, [pc, #76] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b60: f44f 32e1 mov.w r2, #115200 ; 0x1c200
|
|
8001b64: 605a str r2, [r3, #4]
|
|
huart6.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001b66: 4b11 ldr r3, [pc, #68] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b68: 2200 movs r2, #0
|
|
8001b6a: 609a str r2, [r3, #8]
|
|
huart6.Init.StopBits = UART_STOPBITS_1;
|
|
8001b6c: 4b0f ldr r3, [pc, #60] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b6e: 2200 movs r2, #0
|
|
8001b70: 60da str r2, [r3, #12]
|
|
huart6.Init.Parity = UART_PARITY_NONE;
|
|
8001b72: 4b0e ldr r3, [pc, #56] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b74: 2200 movs r2, #0
|
|
8001b76: 611a str r2, [r3, #16]
|
|
huart6.Init.Mode = UART_MODE_TX_RX;
|
|
8001b78: 4b0c ldr r3, [pc, #48] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b7a: 220c movs r2, #12
|
|
8001b7c: 615a str r2, [r3, #20]
|
|
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001b7e: 4b0b ldr r3, [pc, #44] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b80: 2200 movs r2, #0
|
|
8001b82: 619a str r2, [r3, #24]
|
|
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001b84: 4b09 ldr r3, [pc, #36] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b86: 2200 movs r2, #0
|
|
8001b88: 61da str r2, [r3, #28]
|
|
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001b8a: 4b08 ldr r3, [pc, #32] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b8c: 2200 movs r2, #0
|
|
8001b8e: 621a str r2, [r3, #32]
|
|
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001b90: 4b06 ldr r3, [pc, #24] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b92: 2200 movs r2, #0
|
|
8001b94: 625a str r2, [r3, #36] ; 0x24
|
|
if (HAL_UART_Init(&huart6) != HAL_OK)
|
|
8001b96: 4805 ldr r0, [pc, #20] ; (8001bac <MX_USART6_UART_Init+0x58>)
|
|
8001b98: f00a fb42 bl 800c220 <HAL_UART_Init>
|
|
8001b9c: 4603 mov r3, r0
|
|
8001b9e: 2b00 cmp r3, #0
|
|
8001ba0: d001 beq.n 8001ba6 <MX_USART6_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8001ba2: f000 fe69 bl 8002878 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART6_Init 2 */
|
|
|
|
/* USER CODE END USART6_Init 2 */
|
|
|
|
}
|
|
8001ba6: bf00 nop
|
|
8001ba8: bd80 pop {r7, pc}
|
|
8001baa: bf00 nop
|
|
8001bac: 20008d30 .word 0x20008d30
|
|
8001bb0: 40011400 .word 0x40011400
|
|
|
|
08001bb4 <MX_FMC_Init>:
|
|
|
|
/* FMC initialization function */
|
|
static void MX_FMC_Init(void)
|
|
{
|
|
8001bb4: b580 push {r7, lr}
|
|
8001bb6: b088 sub sp, #32
|
|
8001bb8: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN FMC_Init 0 */
|
|
|
|
/* USER CODE END FMC_Init 0 */
|
|
|
|
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
|
|
8001bba: 1d3b adds r3, r7, #4
|
|
8001bbc: 2200 movs r2, #0
|
|
8001bbe: 601a str r2, [r3, #0]
|
|
8001bc0: 605a str r2, [r3, #4]
|
|
8001bc2: 609a str r2, [r3, #8]
|
|
8001bc4: 60da str r2, [r3, #12]
|
|
8001bc6: 611a str r2, [r3, #16]
|
|
8001bc8: 615a str r2, [r3, #20]
|
|
8001bca: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE END FMC_Init 1 */
|
|
|
|
/** Perform the SDRAM1 memory initialization sequence
|
|
*/
|
|
hsdram1.Instance = FMC_SDRAM_DEVICE;
|
|
8001bcc: 4b1e ldr r3, [pc, #120] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bce: 4a1f ldr r2, [pc, #124] ; (8001c4c <MX_FMC_Init+0x98>)
|
|
8001bd0: 601a str r2, [r3, #0]
|
|
/* hsdram1.Init */
|
|
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
|
|
8001bd2: 4b1d ldr r3, [pc, #116] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bd4: 2200 movs r2, #0
|
|
8001bd6: 605a str r2, [r3, #4]
|
|
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
|
8001bd8: 4b1b ldr r3, [pc, #108] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bda: 2200 movs r2, #0
|
|
8001bdc: 609a str r2, [r3, #8]
|
|
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
|
8001bde: 4b1a ldr r3, [pc, #104] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001be0: 2204 movs r2, #4
|
|
8001be2: 60da str r2, [r3, #12]
|
|
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
|
|
8001be4: 4b18 ldr r3, [pc, #96] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001be6: 2210 movs r2, #16
|
|
8001be8: 611a str r2, [r3, #16]
|
|
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
|
8001bea: 4b17 ldr r3, [pc, #92] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bec: 2240 movs r2, #64 ; 0x40
|
|
8001bee: 615a str r2, [r3, #20]
|
|
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
|
|
8001bf0: 4b15 ldr r3, [pc, #84] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bf2: 2280 movs r2, #128 ; 0x80
|
|
8001bf4: 619a str r2, [r3, #24]
|
|
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
|
8001bf6: 4b14 ldr r3, [pc, #80] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bf8: 2200 movs r2, #0
|
|
8001bfa: 61da str r2, [r3, #28]
|
|
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
|
|
8001bfc: 4b12 ldr r3, [pc, #72] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001bfe: 2200 movs r2, #0
|
|
8001c00: 621a str r2, [r3, #32]
|
|
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
|
|
8001c02: 4b11 ldr r3, [pc, #68] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001c04: 2200 movs r2, #0
|
|
8001c06: 625a str r2, [r3, #36] ; 0x24
|
|
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
|
|
8001c08: 4b0f ldr r3, [pc, #60] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001c0a: 2200 movs r2, #0
|
|
8001c0c: 629a str r2, [r3, #40] ; 0x28
|
|
/* SdramTiming */
|
|
SdramTiming.LoadToActiveDelay = 16;
|
|
8001c0e: 2310 movs r3, #16
|
|
8001c10: 607b str r3, [r7, #4]
|
|
SdramTiming.ExitSelfRefreshDelay = 16;
|
|
8001c12: 2310 movs r3, #16
|
|
8001c14: 60bb str r3, [r7, #8]
|
|
SdramTiming.SelfRefreshTime = 16;
|
|
8001c16: 2310 movs r3, #16
|
|
8001c18: 60fb str r3, [r7, #12]
|
|
SdramTiming.RowCycleDelay = 16;
|
|
8001c1a: 2310 movs r3, #16
|
|
8001c1c: 613b str r3, [r7, #16]
|
|
SdramTiming.WriteRecoveryTime = 16;
|
|
8001c1e: 2310 movs r3, #16
|
|
8001c20: 617b str r3, [r7, #20]
|
|
SdramTiming.RPDelay = 16;
|
|
8001c22: 2310 movs r3, #16
|
|
8001c24: 61bb str r3, [r7, #24]
|
|
SdramTiming.RCDDelay = 16;
|
|
8001c26: 2310 movs r3, #16
|
|
8001c28: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
|
|
8001c2a: 1d3b adds r3, r7, #4
|
|
8001c2c: 4619 mov r1, r3
|
|
8001c2e: 4806 ldr r0, [pc, #24] ; (8001c48 <MX_FMC_Init+0x94>)
|
|
8001c30: f009 f8b6 bl 800ada0 <HAL_SDRAM_Init>
|
|
8001c34: 4603 mov r3, r0
|
|
8001c36: 2b00 cmp r3, #0
|
|
8001c38: d001 beq.n 8001c3e <MX_FMC_Init+0x8a>
|
|
{
|
|
Error_Handler( );
|
|
8001c3a: f000 fe1d bl 8002878 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN FMC_Init 2 */
|
|
|
|
/* USER CODE END FMC_Init 2 */
|
|
}
|
|
8001c3e: bf00 nop
|
|
8001c40: 3720 adds r7, #32
|
|
8001c42: 46bd mov sp, r7
|
|
8001c44: bd80 pop {r7, pc}
|
|
8001c46: bf00 nop
|
|
8001c48: 20008e38 .word 0x20008e38
|
|
8001c4c: a0000140 .word 0xa0000140
|
|
|
|
08001c50 <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8001c50: b580 push {r7, lr}
|
|
8001c52: b090 sub sp, #64 ; 0x40
|
|
8001c54: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001c56: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001c5a: 2200 movs r2, #0
|
|
8001c5c: 601a str r2, [r3, #0]
|
|
8001c5e: 605a str r2, [r3, #4]
|
|
8001c60: 609a str r2, [r3, #8]
|
|
8001c62: 60da str r2, [r3, #12]
|
|
8001c64: 611a str r2, [r3, #16]
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8001c66: 4bb0 ldr r3, [pc, #704] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c68: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001c6a: 4aaf ldr r2, [pc, #700] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c6c: f043 0310 orr.w r3, r3, #16
|
|
8001c70: 6313 str r3, [r2, #48] ; 0x30
|
|
8001c72: 4bad ldr r3, [pc, #692] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c74: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001c76: f003 0310 and.w r3, r3, #16
|
|
8001c7a: 62bb str r3, [r7, #40] ; 0x28
|
|
8001c7c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8001c7e: 4baa ldr r3, [pc, #680] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c80: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001c82: 4aa9 ldr r2, [pc, #676] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c84: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8001c88: 6313 str r3, [r2, #48] ; 0x30
|
|
8001c8a: 4ba7 ldr r3, [pc, #668] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c8c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001c8e: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8001c92: 627b str r3, [r7, #36] ; 0x24
|
|
8001c94: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001c96: 4ba4 ldr r3, [pc, #656] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c98: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001c9a: 4aa3 ldr r2, [pc, #652] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001c9c: f043 0302 orr.w r3, r3, #2
|
|
8001ca0: 6313 str r3, [r2, #48] ; 0x30
|
|
8001ca2: 4ba1 ldr r3, [pc, #644] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001ca4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001ca6: f003 0302 and.w r3, r3, #2
|
|
8001caa: 623b str r3, [r7, #32]
|
|
8001cac: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001cae: 4b9e ldr r3, [pc, #632] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cb0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cb2: 4a9d ldr r2, [pc, #628] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cb4: f043 0301 orr.w r3, r3, #1
|
|
8001cb8: 6313 str r3, [r2, #48] ; 0x30
|
|
8001cba: 4b9b ldr r3, [pc, #620] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cbc: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cbe: f003 0301 and.w r3, r3, #1
|
|
8001cc2: 61fb str r3, [r7, #28]
|
|
8001cc4: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
|
8001cc6: 4b98 ldr r3, [pc, #608] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cc8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cca: 4a97 ldr r2, [pc, #604] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001ccc: f443 7300 orr.w r3, r3, #512 ; 0x200
|
|
8001cd0: 6313 str r3, [r2, #48] ; 0x30
|
|
8001cd2: 4b95 ldr r3, [pc, #596] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cd4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cd6: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
8001cda: 61bb str r3, [r7, #24]
|
|
8001cdc: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8001cde: 4b92 ldr r3, [pc, #584] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001ce0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001ce2: 4a91 ldr r2, [pc, #580] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001ce4: f043 0308 orr.w r3, r3, #8
|
|
8001ce8: 6313 str r3, [r2, #48] ; 0x30
|
|
8001cea: 4b8f ldr r3, [pc, #572] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cec: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cee: f003 0308 and.w r3, r3, #8
|
|
8001cf2: 617b str r3, [r7, #20]
|
|
8001cf4: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
8001cf6: 4b8c ldr r3, [pc, #560] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cf8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001cfa: 4a8b ldr r2, [pc, #556] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001cfc: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8001d00: 6313 str r3, [r2, #48] ; 0x30
|
|
8001d02: 4b89 ldr r3, [pc, #548] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d04: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d06: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8001d0a: 613b str r3, [r7, #16]
|
|
8001d0c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOK_CLK_ENABLE();
|
|
8001d0e: 4b86 ldr r3, [pc, #536] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d10: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d12: 4a85 ldr r2, [pc, #532] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d14: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
8001d18: 6313 str r3, [r2, #48] ; 0x30
|
|
8001d1a: 4b83 ldr r3, [pc, #524] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d1c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d1e: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8001d22: 60fb str r3, [r7, #12]
|
|
8001d24: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001d26: 4b80 ldr r3, [pc, #512] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d28: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d2a: 4a7f ldr r2, [pc, #508] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d2c: f043 0304 orr.w r3, r3, #4
|
|
8001d30: 6313 str r3, [r2, #48] ; 0x30
|
|
8001d32: 4b7d ldr r3, [pc, #500] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d34: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d36: f003 0304 and.w r3, r3, #4
|
|
8001d3a: 60bb str r3, [r7, #8]
|
|
8001d3c: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001d3e: 4b7a ldr r3, [pc, #488] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d40: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d42: 4a79 ldr r2, [pc, #484] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d44: f043 0320 orr.w r3, r3, #32
|
|
8001d48: 6313 str r3, [r2, #48] ; 0x30
|
|
8001d4a: 4b77 ldr r3, [pc, #476] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d4c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d4e: f003 0320 and.w r3, r3, #32
|
|
8001d52: 607b str r3, [r7, #4]
|
|
8001d54: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8001d56: 4b74 ldr r3, [pc, #464] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d58: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d5a: 4a73 ldr r2, [pc, #460] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d5c: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8001d60: 6313 str r3, [r2, #48] ; 0x30
|
|
8001d62: 4b71 ldr r3, [pc, #452] ; (8001f28 <MX_GPIO_Init+0x2d8>)
|
|
8001d64: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8001d66: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
8001d6a: 603b str r3, [r7, #0]
|
|
8001d6c: 683b ldr r3, [r7, #0]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET);
|
|
8001d6e: 2200 movs r2, #0
|
|
8001d70: 2160 movs r1, #96 ; 0x60
|
|
8001d72: 486e ldr r0, [pc, #440] ; (8001f2c <MX_GPIO_Init+0x2dc>)
|
|
8001d74: f006 f9f0 bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET);
|
|
8001d78: 2201 movs r2, #1
|
|
8001d7a: 2120 movs r1, #32
|
|
8001d7c: 486c ldr r0, [pc, #432] ; (8001f30 <MX_GPIO_Init+0x2e0>)
|
|
8001d7e: f006 f9eb bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET);
|
|
8001d82: 2200 movs r2, #0
|
|
8001d84: 2108 movs r1, #8
|
|
8001d86: 486a ldr r0, [pc, #424] ; (8001f30 <MX_GPIO_Init+0x2e0>)
|
|
8001d88: f006 f9e6 bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
|
|
8001d8c: 2200 movs r2, #0
|
|
8001d8e: 2108 movs r1, #8
|
|
8001d90: 4868 ldr r0, [pc, #416] ; (8001f34 <MX_GPIO_Init+0x2e4>)
|
|
8001d92: f006 f9e1 bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET);
|
|
8001d96: 2201 movs r2, #1
|
|
8001d98: 2108 movs r1, #8
|
|
8001d9a: 4867 ldr r0, [pc, #412] ; (8001f38 <MX_GPIO_Init+0x2e8>)
|
|
8001d9c: f006 f9dc bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET);
|
|
8001da0: 2201 movs r2, #1
|
|
8001da2: f44f 5180 mov.w r1, #4096 ; 0x1000
|
|
8001da6: 4863 ldr r0, [pc, #396] ; (8001f34 <MX_GPIO_Init+0x2e4>)
|
|
8001da8: f006 f9d6 bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
|
|
8001dac: 2200 movs r2, #0
|
|
8001dae: f645 6140 movw r1, #24128 ; 0x5e40
|
|
8001db2: 4862 ldr r0, [pc, #392] ; (8001f3c <MX_GPIO_Init+0x2ec>)
|
|
8001db4: f006 f9d0 bl 8008158 <HAL_GPIO_WritePin>
|
|
|LED2_Pin|LED18_Pin, GPIO_PIN_RESET);
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET);
|
|
8001db8: 2200 movs r2, #0
|
|
8001dba: 2108 movs r1, #8
|
|
8001dbc: 4860 ldr r0, [pc, #384] ; (8001f40 <MX_GPIO_Init+0x2f0>)
|
|
8001dbe: f006 f9cb bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin : PE3 */
|
|
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
|
8001dc2: 2308 movs r3, #8
|
|
8001dc4: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001dc6: 2300 movs r3, #0
|
|
8001dc8: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001dca: 2300 movs r3, #0
|
|
8001dcc: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8001dce: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001dd2: 4619 mov r1, r3
|
|
8001dd4: 4855 ldr r0, [pc, #340] ; (8001f2c <MX_GPIO_Init+0x2dc>)
|
|
8001dd6: f005 fef3 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin
|
|
ULPI_D1_Pin ULPI_D4_Pin */
|
|
GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin
|
|
8001dda: f643 0323 movw r3, #14371 ; 0x3823
|
|
8001dde: 62fb str r3, [r7, #44] ; 0x2c
|
|
|ULPI_D1_Pin|ULPI_D4_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001de0: 2302 movs r3, #2
|
|
8001de2: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001de4: 2300 movs r3, #0
|
|
8001de6: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001de8: 2303 movs r3, #3
|
|
8001dea: 63bb str r3, [r7, #56] ; 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
|
|
8001dec: 230a movs r3, #10
|
|
8001dee: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001df0: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001df4: 4619 mov r1, r3
|
|
8001df6: 4853 ldr r0, [pc, #332] ; (8001f44 <MX_GPIO_Init+0x2f4>)
|
|
8001df8: f005 fee2 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : BP2_Pin BP1_Pin */
|
|
GPIO_InitStruct.Pin = BP2_Pin|BP1_Pin;
|
|
8001dfc: f44f 4301 mov.w r3, #33024 ; 0x8100
|
|
8001e00: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001e02: 2300 movs r3, #0
|
|
8001e04: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e06: 2300 movs r3, #0
|
|
8001e08: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001e0a: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e0e: 4619 mov r1, r3
|
|
8001e10: 484d ldr r0, [pc, #308] ; (8001f48 <MX_GPIO_Init+0x2f8>)
|
|
8001e12: f005 fed5 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LED14_Pin LED15_Pin */
|
|
GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin;
|
|
8001e16: 2360 movs r3, #96 ; 0x60
|
|
8001e18: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001e1a: 2301 movs r3, #1
|
|
8001e1c: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e1e: 2300 movs r3, #0
|
|
8001e20: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001e22: 2300 movs r3, #0
|
|
8001e24: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8001e26: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e2a: 4619 mov r1, r3
|
|
8001e2c: 483f ldr r0, [pc, #252] ; (8001f2c <MX_GPIO_Init+0x2dc>)
|
|
8001e2e: f005 fec7 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : OTG_FS_VBUS_Pin */
|
|
GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin;
|
|
8001e32: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8001e36: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001e38: 2300 movs r3, #0
|
|
8001e3a: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e3c: 2300 movs r3, #0
|
|
8001e3e: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
|
|
8001e40: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e44: 4619 mov r1, r3
|
|
8001e46: 4841 ldr r0, [pc, #260] ; (8001f4c <MX_GPIO_Init+0x2fc>)
|
|
8001e48: f005 feba bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : Audio_INT_Pin */
|
|
GPIO_InitStruct.Pin = Audio_INT_Pin;
|
|
8001e4c: 2340 movs r3, #64 ; 0x40
|
|
8001e4e: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8001e50: 4b3f ldr r3, [pc, #252] ; (8001f50 <MX_GPIO_Init+0x300>)
|
|
8001e52: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e54: 2300 movs r3, #0
|
|
8001e56: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct);
|
|
8001e58: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e5c: 4619 mov r1, r3
|
|
8001e5e: 4834 ldr r0, [pc, #208] ; (8001f30 <MX_GPIO_Init+0x2e0>)
|
|
8001e60: f005 feae bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */
|
|
GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin;
|
|
8001e64: 2328 movs r3, #40 ; 0x28
|
|
8001e66: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001e68: 2301 movs r3, #1
|
|
8001e6a: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e6c: 2300 movs r3, #0
|
|
8001e6e: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001e70: 2300 movs r3, #0
|
|
8001e72: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8001e74: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e78: 4619 mov r1, r3
|
|
8001e7a: 482d ldr r0, [pc, #180] ; (8001f30 <MX_GPIO_Init+0x2e0>)
|
|
8001e7c: f005 fea0 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */
|
|
GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin;
|
|
8001e80: f241 0308 movw r3, #4104 ; 0x1008
|
|
8001e84: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001e86: 2301 movs r3, #1
|
|
8001e88: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001e8a: 2300 movs r3, #0
|
|
8001e8c: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001e8e: 2300 movs r3, #0
|
|
8001e90: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
|
8001e92: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001e96: 4619 mov r1, r3
|
|
8001e98: 4826 ldr r0, [pc, #152] ; (8001f34 <MX_GPIO_Init+0x2e4>)
|
|
8001e9a: f005 fe91 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : uSD_Detect_Pin */
|
|
GPIO_InitStruct.Pin = uSD_Detect_Pin;
|
|
8001e9e: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8001ea2: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001ea4: 2300 movs r3, #0
|
|
8001ea6: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ea8: 2300 movs r3, #0
|
|
8001eaa: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
|
|
8001eac: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001eb0: 4619 mov r1, r3
|
|
8001eb2: 4828 ldr r0, [pc, #160] ; (8001f54 <MX_GPIO_Init+0x304>)
|
|
8001eb4: f005 fe84 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : LCD_BL_CTRL_Pin */
|
|
GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
|
|
8001eb8: 2308 movs r3, #8
|
|
8001eba: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001ebc: 2301 movs r3, #1
|
|
8001ebe: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ec0: 2300 movs r3, #0
|
|
8001ec2: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001ec4: 2300 movs r3, #0
|
|
8001ec6: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
|
|
8001ec8: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001ecc: 4619 mov r1, r3
|
|
8001ece: 481a ldr r0, [pc, #104] ; (8001f38 <MX_GPIO_Init+0x2e8>)
|
|
8001ed0: f005 fe76 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : OTG_FS_OverCurrent_Pin */
|
|
GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin;
|
|
8001ed4: 2310 movs r3, #16
|
|
8001ed6: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001ed8: 2300 movs r3, #0
|
|
8001eda: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001edc: 2300 movs r3, #0
|
|
8001ede: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct);
|
|
8001ee0: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001ee4: 4619 mov r1, r3
|
|
8001ee6: 4812 ldr r0, [pc, #72] ; (8001f30 <MX_GPIO_Init+0x2e0>)
|
|
8001ee8: f005 fe6a bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : TP3_Pin NC2_Pin */
|
|
GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin;
|
|
8001eec: f248 0304 movw r3, #32772 ; 0x8004
|
|
8001ef0: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001ef2: 2300 movs r3, #0
|
|
8001ef4: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ef6: 2300 movs r3, #0
|
|
8001ef8: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
|
8001efa: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001efe: 4619 mov r1, r3
|
|
8001f00: 480e ldr r0, [pc, #56] ; (8001f3c <MX_GPIO_Init+0x2ec>)
|
|
8001f02: f005 fe5d bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
|
|
LED2_Pin LED18_Pin */
|
|
GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
|
|
8001f06: f645 6340 movw r3, #24128 ; 0x5e40
|
|
8001f0a: 62fb str r3, [r7, #44] ; 0x2c
|
|
|LED2_Pin|LED18_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001f0c: 2301 movs r3, #1
|
|
8001f0e: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f10: 2300 movs r3, #0
|
|
8001f12: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001f14: 2300 movs r3, #0
|
|
8001f16: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
|
8001f18: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001f1c: 4619 mov r1, r3
|
|
8001f1e: 4807 ldr r0, [pc, #28] ; (8001f3c <MX_GPIO_Init+0x2ec>)
|
|
8001f20: f005 fe4e bl 8007bc0 <HAL_GPIO_Init>
|
|
8001f24: e018 b.n 8001f58 <MX_GPIO_Init+0x308>
|
|
8001f26: bf00 nop
|
|
8001f28: 40023800 .word 0x40023800
|
|
8001f2c: 40021000 .word 0x40021000
|
|
8001f30: 40020c00 .word 0x40020c00
|
|
8001f34: 40022000 .word 0x40022000
|
|
8001f38: 40022800 .word 0x40022800
|
|
8001f3c: 40021c00 .word 0x40021c00
|
|
8001f40: 40021800 .word 0x40021800
|
|
8001f44: 40020400 .word 0x40020400
|
|
8001f48: 40020000 .word 0x40020000
|
|
8001f4c: 40022400 .word 0x40022400
|
|
8001f50: 10120000 .word 0x10120000
|
|
8001f54: 40020800 .word 0x40020800
|
|
|
|
/*Configure GPIO pin : LCD_INT_Pin */
|
|
GPIO_InitStruct.Pin = LCD_INT_Pin;
|
|
8001f58: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8001f5c: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8001f5e: 4b2c ldr r3, [pc, #176] ; (8002010 <MX_GPIO_Init+0x3c0>)
|
|
8001f60: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f62: 2300 movs r3, #0
|
|
8001f64: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
|
|
8001f66: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001f6a: 4619 mov r1, r3
|
|
8001f6c: 4829 ldr r0, [pc, #164] ; (8002014 <MX_GPIO_Init+0x3c4>)
|
|
8001f6e: f005 fe27 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ULPI_NXT_Pin */
|
|
GPIO_InitStruct.Pin = ULPI_NXT_Pin;
|
|
8001f72: 2310 movs r3, #16
|
|
8001f74: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001f76: 2302 movs r3, #2
|
|
8001f78: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f7a: 2300 movs r3, #0
|
|
8001f7c: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001f7e: 2303 movs r3, #3
|
|
8001f80: 63bb str r3, [r7, #56] ; 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
|
|
8001f82: 230a movs r3, #10
|
|
8001f84: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct);
|
|
8001f86: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001f8a: 4619 mov r1, r3
|
|
8001f8c: 4822 ldr r0, [pc, #136] ; (8002018 <MX_GPIO_Init+0x3c8>)
|
|
8001f8e: f005 fe17 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */
|
|
GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin;
|
|
8001f92: 2384 movs r3, #132 ; 0x84
|
|
8001f94: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8001f96: 2300 movs r3, #0
|
|
8001f98: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f9a: 2300 movs r3, #0
|
|
8001f9c: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8001f9e: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001fa2: 4619 mov r1, r3
|
|
8001fa4: 481d ldr r0, [pc, #116] ; (800201c <MX_GPIO_Init+0x3cc>)
|
|
8001fa6: f005 fe0b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */
|
|
GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin;
|
|
8001faa: 2305 movs r3, #5
|
|
8001fac: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001fae: 2302 movs r3, #2
|
|
8001fb0: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001fb2: 2300 movs r3, #0
|
|
8001fb4: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001fb6: 2303 movs r3, #3
|
|
8001fb8: 63bb str r3, [r7, #56] ; 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
|
|
8001fba: 230a movs r3, #10
|
|
8001fbc: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001fbe: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001fc2: 4619 mov r1, r3
|
|
8001fc4: 4816 ldr r0, [pc, #88] ; (8002020 <MX_GPIO_Init+0x3d0>)
|
|
8001fc6: f005 fdfb bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : EXT_RST_Pin */
|
|
GPIO_InitStruct.Pin = EXT_RST_Pin;
|
|
8001fca: 2308 movs r3, #8
|
|
8001fcc: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001fce: 2301 movs r3, #1
|
|
8001fd0: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001fd2: 2300 movs r3, #0
|
|
8001fd4: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001fd6: 2300 movs r3, #0
|
|
8001fd8: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct);
|
|
8001fda: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001fde: 4619 mov r1, r3
|
|
8001fe0: 480e ldr r0, [pc, #56] ; (800201c <MX_GPIO_Init+0x3cc>)
|
|
8001fe2: f005 fded bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */
|
|
GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin;
|
|
8001fe6: 2328 movs r3, #40 ; 0x28
|
|
8001fe8: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001fea: 2302 movs r3, #2
|
|
8001fec: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001fee: 2300 movs r3, #0
|
|
8001ff0: 637b str r3, [r7, #52] ; 0x34
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001ff2: 2303 movs r3, #3
|
|
8001ff4: 63bb str r3, [r7, #56] ; 0x38
|
|
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
|
|
8001ff6: 230a movs r3, #10
|
|
8001ff8: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001ffa: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8001ffe: 4619 mov r1, r3
|
|
8002000: 4808 ldr r0, [pc, #32] ; (8002024 <MX_GPIO_Init+0x3d4>)
|
|
8002002: f005 fddd bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
}
|
|
8002006: bf00 nop
|
|
8002008: 3740 adds r7, #64 ; 0x40
|
|
800200a: 46bd mov sp, r7
|
|
800200c: bd80 pop {r7, pc}
|
|
800200e: bf00 nop
|
|
8002010: 10120000 .word 0x10120000
|
|
8002014: 40022000 .word 0x40022000
|
|
8002018: 40021c00 .word 0x40021c00
|
|
800201c: 40021800 .word 0x40021800
|
|
8002020: 40020800 .word 0x40020800
|
|
8002024: 40020000 .word 0x40020000
|
|
|
|
08002028 <f_GameMaster>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_f_GameMaster */
|
|
void f_GameMaster(void const * argument)
|
|
{
|
|
8002028: b580 push {r7, lr}
|
|
800202a: b086 sub sp, #24
|
|
800202c: af00 add r7, sp, #0
|
|
800202e: 6078 str r0, [r7, #4]
|
|
/* init code for LWIP */
|
|
MX_LWIP_Init();
|
|
8002030: f00a fe60 bl 800ccf4 <MX_LWIP_Init>
|
|
/* USER CODE BEGIN 5 */
|
|
TickType_t xLastWakeTime;
|
|
const TickType_t xPeriodeTache = 10;
|
|
8002034: 230a movs r3, #10
|
|
8002036: 617b str r3, [r7, #20]
|
|
// Si la variable end est à 1, le jeu s'arrete.
|
|
uint8_t end = 0;
|
|
8002038: 2300 movs r3, #0
|
|
800203a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Infinite loop */
|
|
for (;;)
|
|
{
|
|
xQueueReceive(Queue_FHandle, &end, 0);
|
|
800203c: 4b1b ldr r3, [pc, #108] ; (80020ac <f_GameMaster+0x84>)
|
|
800203e: 681b ldr r3, [r3, #0]
|
|
8002040: f107 010f add.w r1, r7, #15
|
|
8002044: 2200 movs r2, #0
|
|
8002046: 4618 mov r0, r3
|
|
8002048: f00c fa8e bl 800e568 <xQueueReceive>
|
|
if (end == 1){
|
|
800204c: 7bfb ldrb r3, [r7, #15]
|
|
800204e: 2b01 cmp r3, #1
|
|
8002050: d10e bne.n 8002070 <f_GameMaster+0x48>
|
|
vTaskDelete(Block_EnemieHandle);
|
|
8002052: 4b17 ldr r3, [pc, #92] ; (80020b0 <f_GameMaster+0x88>)
|
|
8002054: 681b ldr r3, [r3, #0]
|
|
8002056: 4618 mov r0, r3
|
|
8002058: f00c ffc6 bl 800efe8 <vTaskDelete>
|
|
vTaskDelete(ProjectileHandle);
|
|
800205c: 4b15 ldr r3, [pc, #84] ; (80020b4 <f_GameMaster+0x8c>)
|
|
800205e: 681b ldr r3, [r3, #0]
|
|
8002060: 4618 mov r0, r3
|
|
8002062: f00c ffc1 bl 800efe8 <vTaskDelete>
|
|
vTaskDelete(Joueur_1Handle);
|
|
8002066: 4b14 ldr r3, [pc, #80] ; (80020b8 <f_GameMaster+0x90>)
|
|
8002068: 681b ldr r3, [r3, #0]
|
|
800206a: 4618 mov r0, r3
|
|
800206c: f00c ffbc bl 800efe8 <vTaskDelete>
|
|
|
|
//TODO L'affichage de l'écran de fin et des scores
|
|
}
|
|
|
|
if (end == 0){
|
|
8002070: 7bfb ldrb r3, [r7, #15]
|
|
8002072: 2b00 cmp r3, #0
|
|
8002074: d112 bne.n 800209c <f_GameMaster+0x74>
|
|
if (waves_left == 0){
|
|
8002076: 4b11 ldr r3, [pc, #68] ; (80020bc <f_GameMaster+0x94>)
|
|
8002078: 781b ldrb r3, [r3, #0]
|
|
800207a: 2b00 cmp r3, #0
|
|
800207c: d10e bne.n 800209c <f_GameMaster+0x74>
|
|
vTaskDelete(Block_EnemieHandle);
|
|
800207e: 4b0c ldr r3, [pc, #48] ; (80020b0 <f_GameMaster+0x88>)
|
|
8002080: 681b ldr r3, [r3, #0]
|
|
8002082: 4618 mov r0, r3
|
|
8002084: f00c ffb0 bl 800efe8 <vTaskDelete>
|
|
vTaskDelete(ProjectileHandle);
|
|
8002088: 4b0a ldr r3, [pc, #40] ; (80020b4 <f_GameMaster+0x8c>)
|
|
800208a: 681b ldr r3, [r3, #0]
|
|
800208c: 4618 mov r0, r3
|
|
800208e: f00c ffab bl 800efe8 <vTaskDelete>
|
|
vTaskDelete(Joueur_1Handle);
|
|
8002092: 4b09 ldr r3, [pc, #36] ; (80020b8 <f_GameMaster+0x90>)
|
|
8002094: 681b ldr r3, [r3, #0]
|
|
8002096: 4618 mov r0, r3
|
|
8002098: f00c ffa6 bl 800efe8 <vTaskDelete>
|
|
}
|
|
|
|
|
|
|
|
|
|
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
|
800209c: f107 0310 add.w r3, r7, #16
|
|
80020a0: 6979 ldr r1, [r7, #20]
|
|
80020a2: 4618 mov r0, r3
|
|
80020a4: f00d f830 bl 800f108 <vTaskDelayUntil>
|
|
xQueueReceive(Queue_FHandle, &end, 0);
|
|
80020a8: e7c8 b.n 800203c <f_GameMaster+0x14>
|
|
80020aa: bf00 nop
|
|
80020ac: 20008ca0 .word 0x20008ca0
|
|
80020b0: 20008e6c .word 0x20008e6c
|
|
80020b4: 20008cbc .word 0x20008cbc
|
|
80020b8: 20008a60 .word 0x20008a60
|
|
80020bc: 20000048 .word 0x20000048
|
|
|
|
080020c0 <f_Joueur_1>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_f_Joueur_1 */
|
|
void f_Joueur_1(void const * argument)
|
|
{
|
|
80020c0: b580 push {r7, lr}
|
|
80020c2: b092 sub sp, #72 ; 0x48
|
|
80020c4: af00 add r7, sp, #0
|
|
80020c6: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN f_Joueur_1 */
|
|
TickType_t xLastWakeTime;
|
|
const TickType_t xPeriodeTache = 10;
|
|
80020c8: 230a movs r3, #10
|
|
80020ca: 647b str r3, [r7, #68] ; 0x44
|
|
uint16_t Width = 20;
|
|
80020cc: 2314 movs r3, #20
|
|
80020ce: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
|
uint16_t Height = 20;
|
|
80020d2: 2314 movs r3, #20
|
|
80020d4: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
|
|
uint32_t joystick_h, joystick_v;
|
|
uint8_t stop = 1;
|
|
80020d8: 2301 movs r3, #1
|
|
80020da: f887 302b strb.w r3, [r7, #43] ; 0x2b
|
|
|
|
struct Missile missile;
|
|
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
80020de: f107 0308 add.w r3, r7, #8
|
|
80020e2: 2200 movs r2, #0
|
|
80020e4: 601a str r2, [r3, #0]
|
|
80020e6: 605a str r2, [r3, #4]
|
|
80020e8: 609a str r2, [r3, #8]
|
|
80020ea: 60da str r2, [r3, #12]
|
|
sConfig.Rank = ADC_REGULAR_RANK_1;
|
|
80020ec: 2301 movs r3, #1
|
|
80020ee: 60fb str r3, [r7, #12]
|
|
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
|
|
80020f0: 2300 movs r3, #0
|
|
80020f2: 613b str r3, [r7, #16]
|
|
|
|
sConfig.Channel = ADC_CHANNEL_8;
|
|
80020f4: 2308 movs r3, #8
|
|
80020f6: 60bb str r3, [r7, #8]
|
|
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
|
|
80020f8: f107 0308 add.w r3, r7, #8
|
|
80020fc: 4619 mov r1, r3
|
|
80020fe: 4862 ldr r0, [pc, #392] ; (8002288 <f_Joueur_1+0x1c8>)
|
|
8002100: f003 fab2 bl 8005668 <HAL_ADC_ConfigChannel>
|
|
HAL_ADC_Start(&hadc3);
|
|
8002104: 4860 ldr r0, [pc, #384] ; (8002288 <f_Joueur_1+0x1c8>)
|
|
8002106: f003 f95d bl 80053c4 <HAL_ADC_Start>
|
|
|
|
HAL_ADC_Start(&hadc1);
|
|
800210a: 4860 ldr r0, [pc, #384] ; (800228c <f_Joueur_1+0x1cc>)
|
|
800210c: f003 f95a bl 80053c4 <HAL_ADC_Start>
|
|
|
|
// Paramètre de l'écran pour la reprouductibilité
|
|
|
|
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
|
|
8002110: f000 fdca bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002114: 63f8 str r0, [r7, #60] ; 0x3c
|
|
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
|
|
8002116: f000 fddb bl 8002cd0 <BSP_LCD_GetYSize>
|
|
800211a: 63b8 str r0, [r7, #56] ; 0x38
|
|
/* Infinite loop */
|
|
for (;;)
|
|
{
|
|
|
|
|
|
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
|
|
800211c: 4b5c ldr r3, [pc, #368] ; (8002290 <f_Joueur_1+0x1d0>)
|
|
800211e: 681b ldr r3, [r3, #0]
|
|
8002120: 4618 mov r0, r3
|
|
8002122: f000 fe59 bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
|
|
8002126: 4b5b ldr r3, [pc, #364] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002128: 681b ldr r3, [r3, #0]
|
|
800212a: b298 uxth r0, r3
|
|
800212c: 4b59 ldr r3, [pc, #356] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800212e: 685b ldr r3, [r3, #4]
|
|
8002130: b299 uxth r1, r3
|
|
8002132: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
|
|
8002136: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
800213a: f001 fa3d bl 80035b8 <BSP_LCD_FillRect>
|
|
|
|
// BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
|
|
while (HAL_ADC_PollForConversion(&hadc3, 100) != HAL_OK);
|
|
800213e: bf00 nop
|
|
8002140: 2164 movs r1, #100 ; 0x64
|
|
8002142: 4851 ldr r0, [pc, #324] ; (8002288 <f_Joueur_1+0x1c8>)
|
|
8002144: f003 f9fe bl 8005544 <HAL_ADC_PollForConversion>
|
|
8002148: 4603 mov r3, r0
|
|
800214a: 2b00 cmp r3, #0
|
|
800214c: d1f8 bne.n 8002140 <f_Joueur_1+0x80>
|
|
joystick_v = HAL_ADC_GetValue(&hadc3);
|
|
800214e: 484e ldr r0, [pc, #312] ; (8002288 <f_Joueur_1+0x1c8>)
|
|
8002150: f003 fa7c bl 800564c <HAL_ADC_GetValue>
|
|
8002154: 6378 str r0, [r7, #52] ; 0x34
|
|
while (HAL_ADC_PollForConversion(&hadc1, 100) != HAL_OK);
|
|
8002156: bf00 nop
|
|
8002158: 2164 movs r1, #100 ; 0x64
|
|
800215a: 484c ldr r0, [pc, #304] ; (800228c <f_Joueur_1+0x1cc>)
|
|
800215c: f003 f9f2 bl 8005544 <HAL_ADC_PollForConversion>
|
|
8002160: 4603 mov r3, r0
|
|
8002162: 2b00 cmp r3, #0
|
|
8002164: d1f8 bne.n 8002158 <f_Joueur_1+0x98>
|
|
joystick_h = HAL_ADC_GetValue(&hadc1);
|
|
8002166: 4849 ldr r0, [pc, #292] ; (800228c <f_Joueur_1+0x1cc>)
|
|
8002168: f003 fa70 bl 800564c <HAL_ADC_GetValue>
|
|
800216c: 6338 str r0, [r7, #48] ; 0x30
|
|
|
|
if ((joueur.y < LCD_HEIGHT- Width - joueur.dy)&&(joystick_h < 1900)) joueur.y += joueur.dy;
|
|
800216e: 4b49 ldr r3, [pc, #292] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002170: 685a ldr r2, [r3, #4]
|
|
8002172: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
|
8002176: 6bf9 ldr r1, [r7, #60] ; 0x3c
|
|
8002178: 1acb subs r3, r1, r3
|
|
800217a: 4946 ldr r1, [pc, #280] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800217c: 7a49 ldrb r1, [r1, #9]
|
|
800217e: 1a5b subs r3, r3, r1
|
|
8002180: 429a cmp r2, r3
|
|
8002182: d20b bcs.n 800219c <f_Joueur_1+0xdc>
|
|
8002184: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8002186: f240 726b movw r2, #1899 ; 0x76b
|
|
800218a: 4293 cmp r3, r2
|
|
800218c: d806 bhi.n 800219c <f_Joueur_1+0xdc>
|
|
800218e: 4b41 ldr r3, [pc, #260] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002190: 685b ldr r3, [r3, #4]
|
|
8002192: 4a40 ldr r2, [pc, #256] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002194: 7a52 ldrb r2, [r2, #9]
|
|
8002196: 4413 add r3, r2
|
|
8002198: 4a3e ldr r2, [pc, #248] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800219a: 6053 str r3, [r2, #4]
|
|
if ((joueur.y > Width + joueur.dy)&&(joystick_h > 2100)) joueur.y -= joueur.dy;
|
|
800219c: 4b3d ldr r3, [pc, #244] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800219e: 685b ldr r3, [r3, #4]
|
|
80021a0: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
80021a4: 493b ldr r1, [pc, #236] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021a6: 7a49 ldrb r1, [r1, #9]
|
|
80021a8: 440a add r2, r1
|
|
80021aa: 4293 cmp r3, r2
|
|
80021ac: d90b bls.n 80021c6 <f_Joueur_1+0x106>
|
|
80021ae: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
80021b0: f640 0234 movw r2, #2100 ; 0x834
|
|
80021b4: 4293 cmp r3, r2
|
|
80021b6: d906 bls.n 80021c6 <f_Joueur_1+0x106>
|
|
80021b8: 4b36 ldr r3, [pc, #216] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021ba: 685b ldr r3, [r3, #4]
|
|
80021bc: 4a35 ldr r2, [pc, #212] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021be: 7a52 ldrb r2, [r2, #9]
|
|
80021c0: 1a9b subs r3, r3, r2
|
|
80021c2: 4a34 ldr r2, [pc, #208] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021c4: 6053 str r3, [r2, #4]
|
|
|
|
if ((joueur.x > LCD_WIDTH + joueur.dx)&&(joystick_v < 1900)) joueur.x += joueur.dx;
|
|
80021c6: 4b33 ldr r3, [pc, #204] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021c8: 681a ldr r2, [r3, #0]
|
|
80021ca: 4b32 ldr r3, [pc, #200] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021cc: 7a1b ldrb r3, [r3, #8]
|
|
80021ce: 4619 mov r1, r3
|
|
80021d0: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80021d2: 440b add r3, r1
|
|
80021d4: 429a cmp r2, r3
|
|
80021d6: d90b bls.n 80021f0 <f_Joueur_1+0x130>
|
|
80021d8: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
80021da: f240 726b movw r2, #1899 ; 0x76b
|
|
80021de: 4293 cmp r3, r2
|
|
80021e0: d806 bhi.n 80021f0 <f_Joueur_1+0x130>
|
|
80021e2: 4b2c ldr r3, [pc, #176] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021e4: 681b ldr r3, [r3, #0]
|
|
80021e6: 4a2b ldr r2, [pc, #172] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021e8: 7a12 ldrb r2, [r2, #8]
|
|
80021ea: 4413 add r3, r2
|
|
80021ec: 4a29 ldr r2, [pc, #164] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021ee: 6013 str r3, [r2, #0]
|
|
if ((joueur.x < 480-Height - joueur.dx)&&(joystick_v > 2100)) joueur.x -= joueur.dx;
|
|
80021f0: 4b28 ldr r3, [pc, #160] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021f2: 681b ldr r3, [r3, #0]
|
|
80021f4: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40
|
|
80021f8: f5c2 72f0 rsb r2, r2, #480 ; 0x1e0
|
|
80021fc: 4925 ldr r1, [pc, #148] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
80021fe: 7a09 ldrb r1, [r1, #8]
|
|
8002200: 1a52 subs r2, r2, r1
|
|
8002202: 4293 cmp r3, r2
|
|
8002204: d20b bcs.n 800221e <f_Joueur_1+0x15e>
|
|
8002206: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
8002208: f640 0234 movw r2, #2100 ; 0x834
|
|
800220c: 4293 cmp r3, r2
|
|
800220e: d906 bls.n 800221e <f_Joueur_1+0x15e>
|
|
8002210: 4b20 ldr r3, [pc, #128] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002212: 681b ldr r3, [r3, #0]
|
|
8002214: 4a1f ldr r2, [pc, #124] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002216: 7a12 ldrb r2, [r2, #8]
|
|
8002218: 1a9b subs r3, r3, r2
|
|
800221a: 4a1e ldr r2, [pc, #120] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800221c: 6013 str r3, [r2, #0]
|
|
|
|
|
|
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
|
|
800221e: 481e ldr r0, [pc, #120] ; (8002298 <f_Joueur_1+0x1d8>)
|
|
8002220: f000 fdda bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
BSP_LCD_FillRect(joueur.x, joueur.y, Width, Height);
|
|
8002224: 4b1b ldr r3, [pc, #108] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002226: 681b ldr r3, [r3, #0]
|
|
8002228: b298 uxth r0, r3
|
|
800222a: 4b1a ldr r3, [pc, #104] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
800222c: 685b ldr r3, [r3, #4]
|
|
800222e: b299 uxth r1, r3
|
|
8002230: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
|
|
8002234: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
8002238: f001 f9be bl 80035b8 <BSP_LCD_FillRect>
|
|
|
|
if (xQueueReceive(Queue_JHandle, &missile, 0) == pdPASS)
|
|
800223c: 4b17 ldr r3, [pc, #92] ; (800229c <f_Joueur_1+0x1dc>)
|
|
800223e: 681b ldr r3, [r3, #0]
|
|
8002240: f107 0118 add.w r1, r7, #24
|
|
8002244: 2200 movs r2, #0
|
|
8002246: 4618 mov r0, r3
|
|
8002248: f00c f98e bl 800e568 <xQueueReceive>
|
|
800224c: 4603 mov r3, r0
|
|
800224e: 2b01 cmp r3, #1
|
|
8002250: d107 bne.n 8002262 <f_Joueur_1+0x1a2>
|
|
joueur.health = joueur.health - missile.damage;
|
|
8002252: 4b10 ldr r3, [pc, #64] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002254: 7a9a ldrb r2, [r3, #10]
|
|
8002256: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
|
|
800225a: 1ad3 subs r3, r2, r3
|
|
800225c: b2da uxtb r2, r3
|
|
800225e: 4b0d ldr r3, [pc, #52] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002260: 729a strb r2, [r3, #10]
|
|
// On envoie 1 si le joueur est mort et on envoie 0 si les enemis sont tous morts
|
|
if (joueur.health == 0)xQueueSend(Queue_FHandle,&stop,0);
|
|
8002262: 4b0c ldr r3, [pc, #48] ; (8002294 <f_Joueur_1+0x1d4>)
|
|
8002264: 7a9b ldrb r3, [r3, #10]
|
|
8002266: 2b00 cmp r3, #0
|
|
8002268: d107 bne.n 800227a <f_Joueur_1+0x1ba>
|
|
800226a: 4b0d ldr r3, [pc, #52] ; (80022a0 <f_Joueur_1+0x1e0>)
|
|
800226c: 6818 ldr r0, [r3, #0]
|
|
800226e: f107 012b add.w r1, r7, #43 ; 0x2b
|
|
8002272: 2300 movs r3, #0
|
|
8002274: 2200 movs r2, #0
|
|
8002276: f00b ff47 bl 800e108 <xQueueGenericSend>
|
|
|
|
// TODO La condition sur une entrée analogique pour envoyer un missile
|
|
// struct Missile missile = {joueur.x, joueur.y,joueur.missile.dx, joueur.missile.dy, 1, joueur.missile.color, joueur.missile.damage};
|
|
// xQueueSend(Queue_NHandle,&missile,0);
|
|
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
|
800227a: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
800227e: 6c79 ldr r1, [r7, #68] ; 0x44
|
|
8002280: 4618 mov r0, r3
|
|
8002282: f00c ff41 bl 800f108 <vTaskDelayUntil>
|
|
BSP_LCD_SetTextColor(LCD_COLOR_BACKGROUND);
|
|
8002286: e749 b.n 800211c <f_Joueur_1+0x5c>
|
|
8002288: 20008bd4 .word 0x20008bd4
|
|
800228c: 20008b8c .word 0x20008b8c
|
|
8002290: 20000044 .word 0x20000044
|
|
8002294: 20000028 .word 0x20000028
|
|
8002298: ff0000ff .word 0xff0000ff
|
|
800229c: 200089ec .word 0x200089ec
|
|
80022a0: 20008ca0 .word 0x20008ca0
|
|
|
|
080022a4 <f_block_enemie>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_f_block_enemie */
|
|
void f_block_enemie(void const * argument)
|
|
{
|
|
80022a4: b580 push {r7, lr}
|
|
80022a6: f5ad 7d7c sub.w sp, sp, #1008 ; 0x3f0
|
|
80022aa: af00 add r7, sp, #0
|
|
80022ac: 1d3b adds r3, r7, #4
|
|
80022ae: 6018 str r0, [r3, #0]
|
|
/* USER CODE BEGIN f_block_enemie */
|
|
TickType_t xLastWakeTime;
|
|
const TickType_t xPeriodeTache = 10;
|
|
80022b0: 230a movs r3, #10
|
|
80022b2: f8c7 33e4 str.w r3, [r7, #996] ; 0x3e4
|
|
uint8_t number_monsters = 30;
|
|
80022b6: 231e movs r3, #30
|
|
80022b8: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
|
|
struct Monster list_monsters[30];
|
|
uint8_t end = 0;
|
|
80022bc: f107 031f add.w r3, r7, #31
|
|
80022c0: 2200 movs r2, #0
|
|
80022c2: 701a strb r2, [r3, #0]
|
|
uint8_t deplacement = 1;
|
|
80022c4: 2301 movs r3, #1
|
|
80022c6: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
|
|
struct Missile missile;
|
|
/* Infinite loop */
|
|
for (;;)
|
|
{
|
|
xQueueReceive(Queue_EHandle, &missile, 0);
|
|
80022ca: 4b52 ldr r3, [pc, #328] ; (8002414 <f_block_enemie+0x170>)
|
|
80022cc: 681b ldr r3, [r3, #0]
|
|
80022ce: f107 010c add.w r1, r7, #12
|
|
80022d2: 2200 movs r2, #0
|
|
80022d4: 4618 mov r0, r3
|
|
80022d6: f00c f947 bl 800e568 <xQueueReceive>
|
|
if (number_monsters == 0){
|
|
80022da: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
|
|
80022de: 2b00 cmp r3, #0
|
|
80022e0: d107 bne.n 80022f2 <f_block_enemie+0x4e>
|
|
xQueueSend(Queue_FHandle, &end, 0);
|
|
80022e2: 4b4d ldr r3, [pc, #308] ; (8002418 <f_block_enemie+0x174>)
|
|
80022e4: 6818 ldr r0, [r3, #0]
|
|
80022e6: f107 011f add.w r1, r7, #31
|
|
80022ea: 2300 movs r3, #0
|
|
80022ec: 2200 movs r2, #0
|
|
80022ee: f00b ff0b bl 800e108 <xQueueGenericSend>
|
|
}
|
|
|
|
for (int i=0;i< number_monsters;i++){
|
|
80022f2: 2300 movs r3, #0
|
|
80022f4: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
|
|
80022f8: e07a b.n 80023f0 <f_block_enemie+0x14c>
|
|
if (list_monsters[i].health > 0 ){
|
|
80022fa: f107 0220 add.w r2, r7, #32
|
|
80022fe: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
8002302: 015b lsls r3, r3, #5
|
|
8002304: 4413 add r3, r2
|
|
8002306: 331d adds r3, #29
|
|
8002308: 781b ldrb r3, [r3, #0]
|
|
800230a: 2b00 cmp r3, #0
|
|
800230c: d06b beq.n 80023e6 <f_block_enemie+0x142>
|
|
if ((missile.x == list_monsters[i].x)&&(missile.y == list_monsters[i].y))
|
|
800230e: f107 030c add.w r3, r7, #12
|
|
8002312: 881b ldrh r3, [r3, #0]
|
|
8002314: 4619 mov r1, r3
|
|
8002316: f107 0220 add.w r2, r7, #32
|
|
800231a: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
800231e: 015b lsls r3, r3, #5
|
|
8002320: 4413 add r3, r2
|
|
8002322: 681b ldr r3, [r3, #0]
|
|
8002324: 4299 cmp r1, r3
|
|
8002326: d133 bne.n 8002390 <f_block_enemie+0xec>
|
|
8002328: f107 030c add.w r3, r7, #12
|
|
800232c: 885b ldrh r3, [r3, #2]
|
|
800232e: 4619 mov r1, r3
|
|
8002330: f107 0220 add.w r2, r7, #32
|
|
8002334: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
8002338: 015b lsls r3, r3, #5
|
|
800233a: 4413 add r3, r2
|
|
800233c: 3304 adds r3, #4
|
|
800233e: 681b ldr r3, [r3, #0]
|
|
8002340: 4299 cmp r1, r3
|
|
8002342: d125 bne.n 8002390 <f_block_enemie+0xec>
|
|
{
|
|
list_monsters[i].health = list_monsters[i].health -1;
|
|
8002344: f107 0220 add.w r2, r7, #32
|
|
8002348: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
800234c: 015b lsls r3, r3, #5
|
|
800234e: 4413 add r3, r2
|
|
8002350: 331d adds r3, #29
|
|
8002352: 781b ldrb r3, [r3, #0]
|
|
8002354: 3b01 subs r3, #1
|
|
8002356: b2d9 uxtb r1, r3
|
|
8002358: f107 0220 add.w r2, r7, #32
|
|
800235c: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
8002360: 015b lsls r3, r3, #5
|
|
8002362: 4413 add r3, r2
|
|
8002364: 331d adds r3, #29
|
|
8002366: 460a mov r2, r1
|
|
8002368: 701a strb r2, [r3, #0]
|
|
// Est ce que cette ligne va marcher sachant que je transmets l'adresse dans la queue ?
|
|
missile.valide = 0;
|
|
800236a: f107 030c add.w r3, r7, #12
|
|
800236e: 2200 movs r2, #0
|
|
8002370: 735a strb r2, [r3, #13]
|
|
if (list_monsters[i].health == 0){
|
|
8002372: f107 0220 add.w r2, r7, #32
|
|
8002376: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
800237a: 015b lsls r3, r3, #5
|
|
800237c: 4413 add r3, r2
|
|
800237e: 331d adds r3, #29
|
|
8002380: 781b ldrb r3, [r3, #0]
|
|
8002382: 2b00 cmp r3, #0
|
|
8002384: d104 bne.n 8002390 <f_block_enemie+0xec>
|
|
//TODO explosion du plaisir ?
|
|
number_monsters = number_monsters -1;
|
|
8002386: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
|
|
800238a: 3b01 subs r3, #1
|
|
800238c: f887 33ef strb.w r3, [r7, #1007] ; 0x3ef
|
|
}
|
|
}
|
|
|
|
BSP_LCD_DrawBitmap(list_monsters[i].x, list_monsters[i].y, &list_monsters[i].pbmp);
|
|
8002390: f107 0220 add.w r2, r7, #32
|
|
8002394: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
8002398: 015b lsls r3, r3, #5
|
|
800239a: 4413 add r3, r2
|
|
800239c: 6818 ldr r0, [r3, #0]
|
|
800239e: f107 0220 add.w r2, r7, #32
|
|
80023a2: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
80023a6: 015b lsls r3, r3, #5
|
|
80023a8: 4413 add r3, r2
|
|
80023aa: 3304 adds r3, #4
|
|
80023ac: 6819 ldr r1, [r3, #0]
|
|
80023ae: f107 0220 add.w r2, r7, #32
|
|
80023b2: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
80023b6: 015b lsls r3, r3, #5
|
|
80023b8: 3308 adds r3, #8
|
|
80023ba: 4413 add r3, r2
|
|
80023bc: 461a mov r2, r3
|
|
80023be: f001 f84b bl 8003458 <BSP_LCD_DrawBitmap>
|
|
// On alterne le deplacement des méchants comme dans le vrai jeux
|
|
//TODO est ce que ca va posé un décalage entre l'affichage et la hitboxe ?
|
|
list_monsters[i].x = list_monsters[i].x + deplacement*2;
|
|
80023c2: f107 0220 add.w r2, r7, #32
|
|
80023c6: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
80023ca: 015b lsls r3, r3, #5
|
|
80023cc: 4413 add r3, r2
|
|
80023ce: 681b ldr r3, [r3, #0]
|
|
80023d0: f897 23ee ldrb.w r2, [r7, #1006] ; 0x3ee
|
|
80023d4: 0052 lsls r2, r2, #1
|
|
80023d6: 441a add r2, r3
|
|
80023d8: f107 0120 add.w r1, r7, #32
|
|
80023dc: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
80023e0: 015b lsls r3, r3, #5
|
|
80023e2: 440b add r3, r1
|
|
80023e4: 601a str r2, [r3, #0]
|
|
for (int i=0;i< number_monsters;i++){
|
|
80023e6: f8d7 33e8 ldr.w r3, [r7, #1000] ; 0x3e8
|
|
80023ea: 3301 adds r3, #1
|
|
80023ec: f8c7 33e8 str.w r3, [r7, #1000] ; 0x3e8
|
|
80023f0: f897 33ef ldrb.w r3, [r7, #1007] ; 0x3ef
|
|
80023f4: f8d7 23e8 ldr.w r2, [r7, #1000] ; 0x3e8
|
|
80023f8: 429a cmp r2, r3
|
|
80023fa: f6ff af7e blt.w 80022fa <f_block_enemie+0x56>
|
|
}
|
|
}
|
|
deplacement = -1;
|
|
80023fe: 23ff movs r3, #255 ; 0xff
|
|
8002400: f887 33ee strb.w r3, [r7, #1006] ; 0x3ee
|
|
|
|
|
|
|
|
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
|
8002404: f507 7378 add.w r3, r7, #992 ; 0x3e0
|
|
8002408: f8d7 13e4 ldr.w r1, [r7, #996] ; 0x3e4
|
|
800240c: 4618 mov r0, r3
|
|
800240e: f00c fe7b bl 800f108 <vTaskDelayUntil>
|
|
xQueueReceive(Queue_EHandle, &missile, 0);
|
|
8002412: e75a b.n 80022ca <f_block_enemie+0x26>
|
|
8002414: 20008e34 .word 0x20008e34
|
|
8002418: 20008ca0 .word 0x20008ca0
|
|
|
|
0800241c <f_projectile>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_f_projectile */
|
|
void f_projectile(void const * argument)
|
|
{
|
|
800241c: b590 push {r4, r7, lr}
|
|
800241e: b0dd sub sp, #372 ; 0x174
|
|
8002420: af00 add r7, sp, #0
|
|
8002422: 1d3b adds r3, r7, #4
|
|
8002424: 6018 str r0, [r3, #0]
|
|
/* USER CODE BEGIN f_projectile */
|
|
TickType_t xLastWakeTime;
|
|
const TickType_t xPeriodeTache = 5000;
|
|
8002426: f241 3388 movw r3, #5000 ; 0x1388
|
|
800242a: f8c7 3168 str.w r3, [r7, #360] ; 0x168
|
|
/* Infinite loop */
|
|
struct Missile liste_missile[20];
|
|
struct Missile missile = {70, 70, 1, 0, 0, LCD_COLOR_WHITE, 1,1};
|
|
800242e: f107 0308 add.w r3, r7, #8
|
|
8002432: 4a80 ldr r2, [pc, #512] ; (8002634 <f_projectile+0x218>)
|
|
8002434: 461c mov r4, r3
|
|
8002436: 4613 mov r3, r2
|
|
8002438: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
800243a: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
uint8_t indice = 1;
|
|
800243e: 2301 movs r3, #1
|
|
8002440: f887 3167 strb.w r3, [r7, #359] ; 0x167
|
|
liste_missile[0] = missile;
|
|
8002444: f107 0218 add.w r2, r7, #24
|
|
8002448: f107 0308 add.w r3, r7, #8
|
|
800244c: 4614 mov r4, r2
|
|
800244e: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
8002450: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
|
|
// Paramètre de l'écran pour la reprouductibilité
|
|
|
|
uint32_t LCD_HEIGHT = BSP_LCD_GetXSize();
|
|
8002454: f000 fc28 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002458: f8c7 0160 str.w r0, [r7, #352] ; 0x160
|
|
uint32_t LCD_WIDTH = BSP_LCD_GetYSize();
|
|
800245c: f000 fc38 bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8002460: f8c7 015c str.w r0, [r7, #348] ; 0x15c
|
|
for (;;)
|
|
{
|
|
//xQueueReceive(Queue_NHandle, &missile, 0);
|
|
//liste_missile[indice++] = missile;
|
|
|
|
for (int i=0;i< indice;i++)
|
|
8002464: 2300 movs r3, #0
|
|
8002466: f8c7 316c str.w r3, [r7, #364] ; 0x16c
|
|
800246a: e1de b.n 800282a <f_projectile+0x40e>
|
|
{
|
|
|
|
// Si le missile n'est pas sur un bord
|
|
if (liste_missile[i].valide == 1)
|
|
800246c: f107 0218 add.w r2, r7, #24
|
|
8002470: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002474: 011b lsls r3, r3, #4
|
|
8002476: 4413 add r3, r2
|
|
8002478: 330d adds r3, #13
|
|
800247a: 781b ldrb r3, [r3, #0]
|
|
800247c: 2b01 cmp r3, #1
|
|
800247e: f040 81cf bne.w 8002820 <f_projectile+0x404>
|
|
{
|
|
// Si le missile appartient au joueur :
|
|
if (liste_missile[i].equipe == 0)
|
|
8002482: f107 0218 add.w r2, r7, #24
|
|
8002486: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800248a: 011b lsls r3, r3, #4
|
|
800248c: 4413 add r3, r2
|
|
800248e: 3306 adds r3, #6
|
|
8002490: 781b ldrb r3, [r3, #0]
|
|
8002492: 2b00 cmp r3, #0
|
|
8002494: f040 80d6 bne.w 8002644 <f_projectile+0x228>
|
|
{
|
|
if (liste_missile[i].x >= Limit_ennemis_x)
|
|
8002498: f107 0218 add.w r2, r7, #24
|
|
800249c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80024a0: 011b lsls r3, r3, #4
|
|
80024a2: 4413 add r3, r2
|
|
80024a4: 881b ldrh r3, [r3, #0]
|
|
80024a6: 461a mov r2, r3
|
|
80024a8: 4b63 ldr r3, [pc, #396] ; (8002638 <f_projectile+0x21c>)
|
|
80024aa: 681b ldr r3, [r3, #0]
|
|
80024ac: 429a cmp r2, r3
|
|
80024ae: d30f bcc.n 80024d0 <f_projectile+0xb4>
|
|
{
|
|
xQueueSend(Queue_EHandle, &liste_missile+indice,0);
|
|
80024b0: 4b62 ldr r3, [pc, #392] ; (800263c <f_projectile+0x220>)
|
|
80024b2: 6818 ldr r0, [r3, #0]
|
|
80024b4: f897 2167 ldrb.w r2, [r7, #359] ; 0x167
|
|
80024b8: 4613 mov r3, r2
|
|
80024ba: 009b lsls r3, r3, #2
|
|
80024bc: 4413 add r3, r2
|
|
80024be: 019b lsls r3, r3, #6
|
|
80024c0: 461a mov r2, r3
|
|
80024c2: f107 0318 add.w r3, r7, #24
|
|
80024c6: 1899 adds r1, r3, r2
|
|
80024c8: 2300 movs r3, #0
|
|
80024ca: 2200 movs r2, #0
|
|
80024cc: f00b fe1c bl 800e108 <xQueueGenericSend>
|
|
// TODO Une petite animation d'explosion ?
|
|
}
|
|
|
|
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
|
|
80024d0: f107 0218 add.w r2, r7, #24
|
|
80024d4: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80024d8: 011b lsls r3, r3, #4
|
|
80024da: 4413 add r3, r2
|
|
80024dc: 881b ldrh r3, [r3, #0]
|
|
80024de: 2b01 cmp r3, #1
|
|
80024e0: f240 808a bls.w 80025f8 <f_projectile+0x1dc>
|
|
80024e4: f107 0218 add.w r2, r7, #24
|
|
80024e8: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80024ec: 011b lsls r3, r3, #4
|
|
80024ee: 4413 add r3, r2
|
|
80024f0: 881b ldrh r3, [r3, #0]
|
|
80024f2: 461a mov r2, r3
|
|
80024f4: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
|
|
80024f8: 3b01 subs r3, #1
|
|
80024fa: 429a cmp r2, r3
|
|
80024fc: d27c bcs.n 80025f8 <f_projectile+0x1dc>
|
|
80024fe: f107 0218 add.w r2, r7, #24
|
|
8002502: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002506: 011b lsls r3, r3, #4
|
|
8002508: 4413 add r3, r2
|
|
800250a: 3302 adds r3, #2
|
|
800250c: 881b ldrh r3, [r3, #0]
|
|
800250e: 461a mov r2, r3
|
|
8002510: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
|
|
8002514: 3b01 subs r3, #1
|
|
8002516: 429a cmp r2, r3
|
|
8002518: d26e bcs.n 80025f8 <f_projectile+0x1dc>
|
|
800251a: f107 0218 add.w r2, r7, #24
|
|
800251e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002522: 011b lsls r3, r3, #4
|
|
8002524: 4413 add r3, r2
|
|
8002526: 3302 adds r3, #2
|
|
8002528: 881b ldrh r3, [r3, #0]
|
|
800252a: 2b01 cmp r3, #1
|
|
800252c: d964 bls.n 80025f8 <f_projectile+0x1dc>
|
|
{
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
|
|
800252e: f107 0218 add.w r2, r7, #24
|
|
8002532: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002536: 011b lsls r3, r3, #4
|
|
8002538: 4413 add r3, r2
|
|
800253a: 8818 ldrh r0, [r3, #0]
|
|
800253c: f107 0218 add.w r2, r7, #24
|
|
8002540: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002544: 011b lsls r3, r3, #4
|
|
8002546: 4413 add r3, r2
|
|
8002548: 3302 adds r3, #2
|
|
800254a: 8819 ldrh r1, [r3, #0]
|
|
800254c: 4b3c ldr r3, [pc, #240] ; (8002640 <f_projectile+0x224>)
|
|
800254e: 681b ldr r3, [r3, #0]
|
|
8002550: 461a mov r2, r3
|
|
8002552: f000 ff39 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
|
|
8002556: f107 0218 add.w r2, r7, #24
|
|
800255a: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800255e: 011b lsls r3, r3, #4
|
|
8002560: 4413 add r3, r2
|
|
8002562: 881a ldrh r2, [r3, #0]
|
|
8002564: f107 0118 add.w r1, r7, #24
|
|
8002568: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800256c: 011b lsls r3, r3, #4
|
|
800256e: 440b add r3, r1
|
|
8002570: 3304 adds r3, #4
|
|
8002572: 781b ldrb r3, [r3, #0]
|
|
8002574: b29b uxth r3, r3
|
|
8002576: 4413 add r3, r2
|
|
8002578: b299 uxth r1, r3
|
|
800257a: f107 0218 add.w r2, r7, #24
|
|
800257e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002582: 011b lsls r3, r3, #4
|
|
8002584: 4413 add r3, r2
|
|
8002586: 460a mov r2, r1
|
|
8002588: 801a strh r2, [r3, #0]
|
|
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
|
|
800258a: f107 0218 add.w r2, r7, #24
|
|
800258e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002592: 011b lsls r3, r3, #4
|
|
8002594: 4413 add r3, r2
|
|
8002596: 3302 adds r3, #2
|
|
8002598: 881a ldrh r2, [r3, #0]
|
|
800259a: f107 0118 add.w r1, r7, #24
|
|
800259e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80025a2: 011b lsls r3, r3, #4
|
|
80025a4: 440b add r3, r1
|
|
80025a6: 3305 adds r3, #5
|
|
80025a8: 781b ldrb r3, [r3, #0]
|
|
80025aa: b29b uxth r3, r3
|
|
80025ac: 4413 add r3, r2
|
|
80025ae: b299 uxth r1, r3
|
|
80025b0: f107 0218 add.w r2, r7, #24
|
|
80025b4: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80025b8: 011b lsls r3, r3, #4
|
|
80025ba: 4413 add r3, r2
|
|
80025bc: 3302 adds r3, #2
|
|
80025be: 460a mov r2, r1
|
|
80025c0: 801a strh r2, [r3, #0]
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
|
|
80025c2: f107 0218 add.w r2, r7, #24
|
|
80025c6: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80025ca: 011b lsls r3, r3, #4
|
|
80025cc: 4413 add r3, r2
|
|
80025ce: 8818 ldrh r0, [r3, #0]
|
|
80025d0: f107 0218 add.w r2, r7, #24
|
|
80025d4: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80025d8: 011b lsls r3, r3, #4
|
|
80025da: 4413 add r3, r2
|
|
80025dc: 3302 adds r3, #2
|
|
80025de: 8819 ldrh r1, [r3, #0]
|
|
80025e0: f107 0218 add.w r2, r7, #24
|
|
80025e4: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80025e8: 011b lsls r3, r3, #4
|
|
80025ea: 4413 add r3, r2
|
|
80025ec: 3308 adds r3, #8
|
|
80025ee: 681b ldr r3, [r3, #0]
|
|
80025f0: 461a mov r2, r3
|
|
80025f2: f000 fee9 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
80025f6: e113 b.n 8002820 <f_projectile+0x404>
|
|
}
|
|
//TODO test sur tous les ennemis
|
|
else
|
|
{
|
|
liste_missile[i].valide = 0;
|
|
80025f8: f107 0218 add.w r2, r7, #24
|
|
80025fc: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002600: 011b lsls r3, r3, #4
|
|
8002602: 4413 add r3, r2
|
|
8002604: 330d adds r3, #13
|
|
8002606: 2200 movs r2, #0
|
|
8002608: 701a strb r2, [r3, #0]
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
|
|
800260a: f107 0218 add.w r2, r7, #24
|
|
800260e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002612: 011b lsls r3, r3, #4
|
|
8002614: 4413 add r3, r2
|
|
8002616: 8818 ldrh r0, [r3, #0]
|
|
8002618: f107 0218 add.w r2, r7, #24
|
|
800261c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002620: 011b lsls r3, r3, #4
|
|
8002622: 4413 add r3, r2
|
|
8002624: 3302 adds r3, #2
|
|
8002626: 8819 ldrh r1, [r3, #0]
|
|
8002628: 4b05 ldr r3, [pc, #20] ; (8002640 <f_projectile+0x224>)
|
|
800262a: 681b ldr r3, [r3, #0]
|
|
800262c: 461a mov r2, r3
|
|
800262e: f000 fecb bl 80033c8 <BSP_LCD_DrawPixel>
|
|
8002632: e0f5 b.n 8002820 <f_projectile+0x404>
|
|
8002634: 0801df20 .word 0x0801df20
|
|
8002638: 2000004c .word 0x2000004c
|
|
800263c: 20008e34 .word 0x20008e34
|
|
8002640: 20000044 .word 0x20000044
|
|
}
|
|
}
|
|
// Si le missile appartient aux ennemis
|
|
else if (liste_missile[i].equipe == 1)
|
|
8002644: f107 0218 add.w r2, r7, #24
|
|
8002648: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800264c: 011b lsls r3, r3, #4
|
|
800264e: 4413 add r3, r2
|
|
8002650: 3306 adds r3, #6
|
|
8002652: 781b ldrb r3, [r3, #0]
|
|
8002654: 2b01 cmp r3, #1
|
|
8002656: f040 80e3 bne.w 8002820 <f_projectile+0x404>
|
|
{
|
|
if ((liste_missile[i].x == joueur.x)&&(liste_missile[i].y == joueur.y))
|
|
800265a: f107 0218 add.w r2, r7, #24
|
|
800265e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002662: 011b lsls r3, r3, #4
|
|
8002664: 4413 add r3, r2
|
|
8002666: 881b ldrh r3, [r3, #0]
|
|
8002668: 461a mov r2, r3
|
|
800266a: 4b77 ldr r3, [pc, #476] ; (8002848 <f_projectile+0x42c>)
|
|
800266c: 681b ldr r3, [r3, #0]
|
|
800266e: 429a cmp r2, r3
|
|
8002670: d125 bne.n 80026be <f_projectile+0x2a2>
|
|
8002672: f107 0218 add.w r2, r7, #24
|
|
8002676: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800267a: 011b lsls r3, r3, #4
|
|
800267c: 4413 add r3, r2
|
|
800267e: 3302 adds r3, #2
|
|
8002680: 881b ldrh r3, [r3, #0]
|
|
8002682: 461a mov r2, r3
|
|
8002684: 4b70 ldr r3, [pc, #448] ; (8002848 <f_projectile+0x42c>)
|
|
8002686: 685b ldr r3, [r3, #4]
|
|
8002688: 429a cmp r2, r3
|
|
800268a: d118 bne.n 80026be <f_projectile+0x2a2>
|
|
{
|
|
xQueueSend(Queue_JHandle, &liste_missile+indice,0);
|
|
800268c: 4b6f ldr r3, [pc, #444] ; (800284c <f_projectile+0x430>)
|
|
800268e: 6818 ldr r0, [r3, #0]
|
|
8002690: f897 2167 ldrb.w r2, [r7, #359] ; 0x167
|
|
8002694: 4613 mov r3, r2
|
|
8002696: 009b lsls r3, r3, #2
|
|
8002698: 4413 add r3, r2
|
|
800269a: 019b lsls r3, r3, #6
|
|
800269c: 461a mov r2, r3
|
|
800269e: f107 0318 add.w r3, r7, #24
|
|
80026a2: 1899 adds r1, r3, r2
|
|
80026a4: 2300 movs r3, #0
|
|
80026a6: 2200 movs r2, #0
|
|
80026a8: f00b fd2e bl 800e108 <xQueueGenericSend>
|
|
liste_missile[i].valide = 0;
|
|
80026ac: f107 0218 add.w r2, r7, #24
|
|
80026b0: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80026b4: 011b lsls r3, r3, #4
|
|
80026b6: 4413 add r3, r2
|
|
80026b8: 330d adds r3, #13
|
|
80026ba: 2200 movs r2, #0
|
|
80026bc: 701a strb r2, [r3, #0]
|
|
// TODO Une petite animation d'explosion ?
|
|
}
|
|
if ((liste_missile[i].x > 1)&&(liste_missile[i].x < LCD_HEIGHT-1)&&(liste_missile[i].y < LCD_WIDTH-1)&&(liste_missile[i].y > 1))
|
|
80026be: f107 0218 add.w r2, r7, #24
|
|
80026c2: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80026c6: 011b lsls r3, r3, #4
|
|
80026c8: 4413 add r3, r2
|
|
80026ca: 881b ldrh r3, [r3, #0]
|
|
80026cc: 2b01 cmp r3, #1
|
|
80026ce: f240 808a bls.w 80027e6 <f_projectile+0x3ca>
|
|
80026d2: f107 0218 add.w r2, r7, #24
|
|
80026d6: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80026da: 011b lsls r3, r3, #4
|
|
80026dc: 4413 add r3, r2
|
|
80026de: 881b ldrh r3, [r3, #0]
|
|
80026e0: 461a mov r2, r3
|
|
80026e2: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
|
|
80026e6: 3b01 subs r3, #1
|
|
80026e8: 429a cmp r2, r3
|
|
80026ea: d27c bcs.n 80027e6 <f_projectile+0x3ca>
|
|
80026ec: f107 0218 add.w r2, r7, #24
|
|
80026f0: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80026f4: 011b lsls r3, r3, #4
|
|
80026f6: 4413 add r3, r2
|
|
80026f8: 3302 adds r3, #2
|
|
80026fa: 881b ldrh r3, [r3, #0]
|
|
80026fc: 461a mov r2, r3
|
|
80026fe: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
|
|
8002702: 3b01 subs r3, #1
|
|
8002704: 429a cmp r2, r3
|
|
8002706: d26e bcs.n 80027e6 <f_projectile+0x3ca>
|
|
8002708: f107 0218 add.w r2, r7, #24
|
|
800270c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002710: 011b lsls r3, r3, #4
|
|
8002712: 4413 add r3, r2
|
|
8002714: 3302 adds r3, #2
|
|
8002716: 881b ldrh r3, [r3, #0]
|
|
8002718: 2b01 cmp r3, #1
|
|
800271a: d964 bls.n 80027e6 <f_projectile+0x3ca>
|
|
{
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
|
|
800271c: f107 0218 add.w r2, r7, #24
|
|
8002720: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002724: 011b lsls r3, r3, #4
|
|
8002726: 4413 add r3, r2
|
|
8002728: 8818 ldrh r0, [r3, #0]
|
|
800272a: f107 0218 add.w r2, r7, #24
|
|
800272e: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002732: 011b lsls r3, r3, #4
|
|
8002734: 4413 add r3, r2
|
|
8002736: 3302 adds r3, #2
|
|
8002738: 8819 ldrh r1, [r3, #0]
|
|
800273a: 4b45 ldr r3, [pc, #276] ; (8002850 <f_projectile+0x434>)
|
|
800273c: 681b ldr r3, [r3, #0]
|
|
800273e: 461a mov r2, r3
|
|
8002740: f000 fe42 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
liste_missile[i].x = liste_missile[i].x + liste_missile[i].dx ;
|
|
8002744: f107 0218 add.w r2, r7, #24
|
|
8002748: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800274c: 011b lsls r3, r3, #4
|
|
800274e: 4413 add r3, r2
|
|
8002750: 881a ldrh r2, [r3, #0]
|
|
8002752: f107 0118 add.w r1, r7, #24
|
|
8002756: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800275a: 011b lsls r3, r3, #4
|
|
800275c: 440b add r3, r1
|
|
800275e: 3304 adds r3, #4
|
|
8002760: 781b ldrb r3, [r3, #0]
|
|
8002762: b29b uxth r3, r3
|
|
8002764: 4413 add r3, r2
|
|
8002766: b299 uxth r1, r3
|
|
8002768: f107 0218 add.w r2, r7, #24
|
|
800276c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002770: 011b lsls r3, r3, #4
|
|
8002772: 4413 add r3, r2
|
|
8002774: 460a mov r2, r1
|
|
8002776: 801a strh r2, [r3, #0]
|
|
liste_missile[i].y = liste_missile[i].y + liste_missile[i].dy;
|
|
8002778: f107 0218 add.w r2, r7, #24
|
|
800277c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002780: 011b lsls r3, r3, #4
|
|
8002782: 4413 add r3, r2
|
|
8002784: 3302 adds r3, #2
|
|
8002786: 881a ldrh r2, [r3, #0]
|
|
8002788: f107 0118 add.w r1, r7, #24
|
|
800278c: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002790: 011b lsls r3, r3, #4
|
|
8002792: 440b add r3, r1
|
|
8002794: 3305 adds r3, #5
|
|
8002796: 781b ldrb r3, [r3, #0]
|
|
8002798: b29b uxth r3, r3
|
|
800279a: 4413 add r3, r2
|
|
800279c: b299 uxth r1, r3
|
|
800279e: f107 0218 add.w r2, r7, #24
|
|
80027a2: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80027a6: 011b lsls r3, r3, #4
|
|
80027a8: 4413 add r3, r2
|
|
80027aa: 3302 adds r3, #2
|
|
80027ac: 460a mov r2, r1
|
|
80027ae: 801a strh r2, [r3, #0]
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, liste_missile[i].color);
|
|
80027b0: f107 0218 add.w r2, r7, #24
|
|
80027b4: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80027b8: 011b lsls r3, r3, #4
|
|
80027ba: 4413 add r3, r2
|
|
80027bc: 8818 ldrh r0, [r3, #0]
|
|
80027be: f107 0218 add.w r2, r7, #24
|
|
80027c2: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80027c6: 011b lsls r3, r3, #4
|
|
80027c8: 4413 add r3, r2
|
|
80027ca: 3302 adds r3, #2
|
|
80027cc: 8819 ldrh r1, [r3, #0]
|
|
80027ce: f107 0218 add.w r2, r7, #24
|
|
80027d2: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80027d6: 011b lsls r3, r3, #4
|
|
80027d8: 4413 add r3, r2
|
|
80027da: 3308 adds r3, #8
|
|
80027dc: 681b ldr r3, [r3, #0]
|
|
80027de: 461a mov r2, r3
|
|
80027e0: f000 fdf2 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
80027e4: e01c b.n 8002820 <f_projectile+0x404>
|
|
}
|
|
else
|
|
{
|
|
liste_missile[i].valide = 0;
|
|
80027e6: f107 0218 add.w r2, r7, #24
|
|
80027ea: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
80027ee: 011b lsls r3, r3, #4
|
|
80027f0: 4413 add r3, r2
|
|
80027f2: 330d adds r3, #13
|
|
80027f4: 2200 movs r2, #0
|
|
80027f6: 701a strb r2, [r3, #0]
|
|
BSP_LCD_DrawPixel(liste_missile[i].x, liste_missile[i].y, LCD_COLOR_BACKGROUND);
|
|
80027f8: f107 0218 add.w r2, r7, #24
|
|
80027fc: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002800: 011b lsls r3, r3, #4
|
|
8002802: 4413 add r3, r2
|
|
8002804: 8818 ldrh r0, [r3, #0]
|
|
8002806: f107 0218 add.w r2, r7, #24
|
|
800280a: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
800280e: 011b lsls r3, r3, #4
|
|
8002810: 4413 add r3, r2
|
|
8002812: 3302 adds r3, #2
|
|
8002814: 8819 ldrh r1, [r3, #0]
|
|
8002816: 4b0e ldr r3, [pc, #56] ; (8002850 <f_projectile+0x434>)
|
|
8002818: 681b ldr r3, [r3, #0]
|
|
800281a: 461a mov r2, r3
|
|
800281c: f000 fdd4 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
for (int i=0;i< indice;i++)
|
|
8002820: f8d7 316c ldr.w r3, [r7, #364] ; 0x16c
|
|
8002824: 3301 adds r3, #1
|
|
8002826: f8c7 316c str.w r3, [r7, #364] ; 0x16c
|
|
800282a: f897 3167 ldrb.w r3, [r7, #359] ; 0x167
|
|
800282e: f8d7 216c ldr.w r2, [r7, #364] ; 0x16c
|
|
8002832: 429a cmp r2, r3
|
|
8002834: f6ff ae1a blt.w 800246c <f_projectile+0x50>
|
|
}
|
|
}
|
|
|
|
}
|
|
}
|
|
vTaskDelayUntil(&xLastWakeTime, xPeriodeTache);
|
|
8002838: f507 73ac add.w r3, r7, #344 ; 0x158
|
|
800283c: f8d7 1168 ldr.w r1, [r7, #360] ; 0x168
|
|
8002840: 4618 mov r0, r3
|
|
8002842: f00c fc61 bl 800f108 <vTaskDelayUntil>
|
|
for (int i=0;i< indice;i++)
|
|
8002846: e60d b.n 8002464 <f_projectile+0x48>
|
|
8002848: 20000028 .word 0x20000028
|
|
800284c: 200089ec .word 0x200089ec
|
|
8002850: 20000044 .word 0x20000044
|
|
|
|
08002854 <HAL_TIM_PeriodElapsedCallback>:
|
|
* a global variable "uwTick" used as application time base.
|
|
* @param htim : TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8002854: b580 push {r7, lr}
|
|
8002856: b082 sub sp, #8
|
|
8002858: af00 add r7, sp, #0
|
|
800285a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Callback 0 */
|
|
|
|
/* USER CODE END Callback 0 */
|
|
if (htim->Instance == TIM6) {
|
|
800285c: 687b ldr r3, [r7, #4]
|
|
800285e: 681b ldr r3, [r3, #0]
|
|
8002860: 4a04 ldr r2, [pc, #16] ; (8002874 <HAL_TIM_PeriodElapsedCallback+0x20>)
|
|
8002862: 4293 cmp r3, r2
|
|
8002864: d101 bne.n 800286a <HAL_TIM_PeriodElapsedCallback+0x16>
|
|
HAL_IncTick();
|
|
8002866: f002 fd27 bl 80052b8 <HAL_IncTick>
|
|
}
|
|
/* USER CODE BEGIN Callback 1 */
|
|
|
|
/* USER CODE END Callback 1 */
|
|
}
|
|
800286a: bf00 nop
|
|
800286c: 3708 adds r7, #8
|
|
800286e: 46bd mov sp, r7
|
|
8002870: bd80 pop {r7, pc}
|
|
8002872: bf00 nop
|
|
8002874: 40001000 .word 0x40001000
|
|
|
|
08002878 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8002878: b480 push {r7}
|
|
800287a: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800287c: b672 cpsid i
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
800287e: e7fe b.n 800287e <Error_Handler+0x6>
|
|
|
|
08002880 <I2Cx_MspInit>:
|
|
* @brief Initializes I2C MSP.
|
|
* @param i2c_handler : I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
8002880: b580 push {r7, lr}
|
|
8002882: b08c sub sp, #48 ; 0x30
|
|
8002884: af00 add r7, sp, #0
|
|
8002886: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
|
|
8002888: 687b ldr r3, [r7, #4]
|
|
800288a: 4a51 ldr r2, [pc, #324] ; (80029d0 <I2Cx_MspInit+0x150>)
|
|
800288c: 4293 cmp r3, r2
|
|
800288e: d14d bne.n 800292c <I2Cx_MspInit+0xac>
|
|
{
|
|
/* AUDIO and LCD I2C MSP init */
|
|
|
|
/*** Configure the GPIOs ***/
|
|
/* Enable GPIO clock */
|
|
DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
|
|
8002890: 4b50 ldr r3, [pc, #320] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002892: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8002894: 4a4f ldr r2, [pc, #316] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002896: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
800289a: 6313 str r3, [r2, #48] ; 0x30
|
|
800289c: 4b4d ldr r3, [pc, #308] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800289e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80028a0: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
80028a4: 61bb str r3, [r7, #24]
|
|
80028a6: 69bb ldr r3, [r7, #24]
|
|
|
|
/* Configure I2C Tx as alternate function */
|
|
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN;
|
|
80028a8: 2380 movs r3, #128 ; 0x80
|
|
80028aa: 61fb str r3, [r7, #28]
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
|
|
80028ac: 2312 movs r3, #18
|
|
80028ae: 623b str r3, [r7, #32]
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
80028b0: 2300 movs r3, #0
|
|
80028b2: 627b str r3, [r7, #36] ; 0x24
|
|
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
|
80028b4: 2302 movs r3, #2
|
|
80028b6: 62bb str r3, [r7, #40] ; 0x28
|
|
gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF;
|
|
80028b8: 2304 movs r3, #4
|
|
80028ba: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
80028bc: f107 031c add.w r3, r7, #28
|
|
80028c0: 4619 mov r1, r3
|
|
80028c2: 4845 ldr r0, [pc, #276] ; (80029d8 <I2Cx_MspInit+0x158>)
|
|
80028c4: f005 f97c bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* Configure I2C Rx as alternate function */
|
|
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN;
|
|
80028c8: f44f 7380 mov.w r3, #256 ; 0x100
|
|
80028cc: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
80028ce: f107 031c add.w r3, r7, #28
|
|
80028d2: 4619 mov r1, r3
|
|
80028d4: 4840 ldr r0, [pc, #256] ; (80029d8 <I2Cx_MspInit+0x158>)
|
|
80028d6: f005 f973 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/*** Configure the I2C peripheral ***/
|
|
/* Enable I2C clock */
|
|
DISCOVERY_AUDIO_I2Cx_CLK_ENABLE();
|
|
80028da: 4b3e ldr r3, [pc, #248] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80028dc: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80028de: 4a3d ldr r2, [pc, #244] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80028e0: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
80028e4: 6413 str r3, [r2, #64] ; 0x40
|
|
80028e6: 4b3b ldr r3, [pc, #236] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80028e8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80028ea: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
80028ee: 617b str r3, [r7, #20]
|
|
80028f0: 697b ldr r3, [r7, #20]
|
|
|
|
/* Force the I2C peripheral clock reset */
|
|
DISCOVERY_AUDIO_I2Cx_FORCE_RESET();
|
|
80028f2: 4b38 ldr r3, [pc, #224] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80028f4: 6a1b ldr r3, [r3, #32]
|
|
80028f6: 4a37 ldr r2, [pc, #220] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80028f8: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
80028fc: 6213 str r3, [r2, #32]
|
|
|
|
/* Release the I2C peripheral clock reset */
|
|
DISCOVERY_AUDIO_I2Cx_RELEASE_RESET();
|
|
80028fe: 4b35 ldr r3, [pc, #212] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002900: 6a1b ldr r3, [r3, #32]
|
|
8002902: 4a34 ldr r2, [pc, #208] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002904: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
|
|
8002908: 6213 str r3, [r2, #32]
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0);
|
|
800290a: 2200 movs r2, #0
|
|
800290c: 210f movs r1, #15
|
|
800290e: 2048 movs r0, #72 ; 0x48
|
|
8002910: f003 f9a6 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn);
|
|
8002914: 2048 movs r0, #72 ; 0x48
|
|
8002916: f003 f9bf bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0);
|
|
800291a: 2200 movs r2, #0
|
|
800291c: 210f movs r1, #15
|
|
800291e: 2049 movs r0, #73 ; 0x49
|
|
8002920: f003 f99e bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn);
|
|
8002924: 2049 movs r0, #73 ; 0x49
|
|
8002926: f003 f9b7 bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* Enable and set I2Cx Interrupt to a lower priority */
|
|
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
|
|
}
|
|
}
|
|
800292a: e04d b.n 80029c8 <I2Cx_MspInit+0x148>
|
|
DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
|
|
800292c: 4b29 ldr r3, [pc, #164] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800292e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8002930: 4a28 ldr r2, [pc, #160] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002932: f043 0302 orr.w r3, r3, #2
|
|
8002936: 6313 str r3, [r2, #48] ; 0x30
|
|
8002938: 4b26 ldr r3, [pc, #152] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800293a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800293c: f003 0302 and.w r3, r3, #2
|
|
8002940: 613b str r3, [r7, #16]
|
|
8002942: 693b ldr r3, [r7, #16]
|
|
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN;
|
|
8002944: f44f 7380 mov.w r3, #256 ; 0x100
|
|
8002948: 61fb str r3, [r7, #28]
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
|
|
800294a: 2312 movs r3, #18
|
|
800294c: 623b str r3, [r7, #32]
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
800294e: 2300 movs r3, #0
|
|
8002950: 627b str r3, [r7, #36] ; 0x24
|
|
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
|
8002952: 2302 movs r3, #2
|
|
8002954: 62bb str r3, [r7, #40] ; 0x28
|
|
gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF;
|
|
8002956: 2304 movs r3, #4
|
|
8002958: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
800295a: f107 031c add.w r3, r7, #28
|
|
800295e: 4619 mov r1, r3
|
|
8002960: 481e ldr r0, [pc, #120] ; (80029dc <I2Cx_MspInit+0x15c>)
|
|
8002962: f005 f92d bl 8007bc0 <HAL_GPIO_Init>
|
|
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN;
|
|
8002966: f44f 7300 mov.w r3, #512 ; 0x200
|
|
800296a: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
|
|
800296c: f107 031c add.w r3, r7, #28
|
|
8002970: 4619 mov r1, r3
|
|
8002972: 481a ldr r0, [pc, #104] ; (80029dc <I2Cx_MspInit+0x15c>)
|
|
8002974: f005 f924 bl 8007bc0 <HAL_GPIO_Init>
|
|
DISCOVERY_EXT_I2Cx_CLK_ENABLE();
|
|
8002978: 4b16 ldr r3, [pc, #88] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800297a: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800297c: 4a15 ldr r2, [pc, #84] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800297e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
|
|
8002982: 6413 str r3, [r2, #64] ; 0x40
|
|
8002984: 4b13 ldr r3, [pc, #76] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002986: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8002988: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
800298c: 60fb str r3, [r7, #12]
|
|
800298e: 68fb ldr r3, [r7, #12]
|
|
DISCOVERY_EXT_I2Cx_FORCE_RESET();
|
|
8002990: 4b10 ldr r3, [pc, #64] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002992: 6a1b ldr r3, [r3, #32]
|
|
8002994: 4a0f ldr r2, [pc, #60] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
8002996: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
|
|
800299a: 6213 str r3, [r2, #32]
|
|
DISCOVERY_EXT_I2Cx_RELEASE_RESET();
|
|
800299c: 4b0d ldr r3, [pc, #52] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
800299e: 6a1b ldr r3, [r3, #32]
|
|
80029a0: 4a0c ldr r2, [pc, #48] ; (80029d4 <I2Cx_MspInit+0x154>)
|
|
80029a2: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
|
|
80029a6: 6213 str r3, [r2, #32]
|
|
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0);
|
|
80029a8: 2200 movs r2, #0
|
|
80029aa: 210f movs r1, #15
|
|
80029ac: 201f movs r0, #31
|
|
80029ae: f003 f957 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn);
|
|
80029b2: 201f movs r0, #31
|
|
80029b4: f003 f970 bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
|
|
80029b8: 2200 movs r2, #0
|
|
80029ba: 210f movs r1, #15
|
|
80029bc: 2020 movs r0, #32
|
|
80029be: f003 f94f bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
|
|
80029c2: 2020 movs r0, #32
|
|
80029c4: f003 f968 bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
80029c8: bf00 nop
|
|
80029ca: 3730 adds r7, #48 ; 0x30
|
|
80029cc: 46bd mov sp, r7
|
|
80029ce: bd80 pop {r7, pc}
|
|
80029d0: 20000390 .word 0x20000390
|
|
80029d4: 40023800 .word 0x40023800
|
|
80029d8: 40021c00 .word 0x40021c00
|
|
80029dc: 40020400 .word 0x40020400
|
|
|
|
080029e0 <I2Cx_Init>:
|
|
* @brief Initializes I2C HAL.
|
|
* @param i2c_handler : I2C handler
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
|
|
{
|
|
80029e0: b580 push {r7, lr}
|
|
80029e2: b082 sub sp, #8
|
|
80029e4: af00 add r7, sp, #0
|
|
80029e6: 6078 str r0, [r7, #4]
|
|
if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET)
|
|
80029e8: 6878 ldr r0, [r7, #4]
|
|
80029ea: f005 febd bl 8008768 <HAL_I2C_GetState>
|
|
80029ee: 4603 mov r3, r0
|
|
80029f0: 2b00 cmp r3, #0
|
|
80029f2: d125 bne.n 8002a40 <I2Cx_Init+0x60>
|
|
{
|
|
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
|
|
80029f4: 687b ldr r3, [r7, #4]
|
|
80029f6: 4a14 ldr r2, [pc, #80] ; (8002a48 <I2Cx_Init+0x68>)
|
|
80029f8: 4293 cmp r3, r2
|
|
80029fa: d103 bne.n 8002a04 <I2Cx_Init+0x24>
|
|
{
|
|
/* Audio and LCD I2C configuration */
|
|
i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx;
|
|
80029fc: 687b ldr r3, [r7, #4]
|
|
80029fe: 4a13 ldr r2, [pc, #76] ; (8002a4c <I2Cx_Init+0x6c>)
|
|
8002a00: 601a str r2, [r3, #0]
|
|
8002a02: e002 b.n 8002a0a <I2Cx_Init+0x2a>
|
|
}
|
|
else
|
|
{
|
|
/* External, camera and Arduino connector I2C configuration */
|
|
i2c_handler->Instance = DISCOVERY_EXT_I2Cx;
|
|
8002a04: 687b ldr r3, [r7, #4]
|
|
8002a06: 4a12 ldr r2, [pc, #72] ; (8002a50 <I2Cx_Init+0x70>)
|
|
8002a08: 601a str r2, [r3, #0]
|
|
}
|
|
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
|
|
8002a0a: 687b ldr r3, [r7, #4]
|
|
8002a0c: 4a11 ldr r2, [pc, #68] ; (8002a54 <I2Cx_Init+0x74>)
|
|
8002a0e: 605a str r2, [r3, #4]
|
|
i2c_handler->Init.OwnAddress1 = 0;
|
|
8002a10: 687b ldr r3, [r7, #4]
|
|
8002a12: 2200 movs r2, #0
|
|
8002a14: 609a str r2, [r3, #8]
|
|
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8002a16: 687b ldr r3, [r7, #4]
|
|
8002a18: 2201 movs r2, #1
|
|
8002a1a: 60da str r2, [r3, #12]
|
|
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8002a1c: 687b ldr r3, [r7, #4]
|
|
8002a1e: 2200 movs r2, #0
|
|
8002a20: 611a str r2, [r3, #16]
|
|
i2c_handler->Init.OwnAddress2 = 0;
|
|
8002a22: 687b ldr r3, [r7, #4]
|
|
8002a24: 2200 movs r2, #0
|
|
8002a26: 615a str r2, [r3, #20]
|
|
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8002a28: 687b ldr r3, [r7, #4]
|
|
8002a2a: 2200 movs r2, #0
|
|
8002a2c: 61da str r2, [r3, #28]
|
|
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8002a2e: 687b ldr r3, [r7, #4]
|
|
8002a30: 2200 movs r2, #0
|
|
8002a32: 621a str r2, [r3, #32]
|
|
|
|
/* Init the I2C */
|
|
I2Cx_MspInit(i2c_handler);
|
|
8002a34: 6878 ldr r0, [r7, #4]
|
|
8002a36: f7ff ff23 bl 8002880 <I2Cx_MspInit>
|
|
HAL_I2C_Init(i2c_handler);
|
|
8002a3a: 6878 ldr r0, [r7, #4]
|
|
8002a3c: f005 fba6 bl 800818c <HAL_I2C_Init>
|
|
}
|
|
}
|
|
8002a40: bf00 nop
|
|
8002a42: 3708 adds r7, #8
|
|
8002a44: 46bd mov sp, r7
|
|
8002a46: bd80 pop {r7, pc}
|
|
8002a48: 20000390 .word 0x20000390
|
|
8002a4c: 40005c00 .word 0x40005c00
|
|
8002a50: 40005400 .word 0x40005400
|
|
8002a54: 40912732 .word 0x40912732
|
|
|
|
08002a58 <I2Cx_ReadMultiple>:
|
|
uint8_t Addr,
|
|
uint16_t Reg,
|
|
uint16_t MemAddress,
|
|
uint8_t *Buffer,
|
|
uint16_t Length)
|
|
{
|
|
8002a58: b580 push {r7, lr}
|
|
8002a5a: b08a sub sp, #40 ; 0x28
|
|
8002a5c: af04 add r7, sp, #16
|
|
8002a5e: 60f8 str r0, [r7, #12]
|
|
8002a60: 4608 mov r0, r1
|
|
8002a62: 4611 mov r1, r2
|
|
8002a64: 461a mov r2, r3
|
|
8002a66: 4603 mov r3, r0
|
|
8002a68: 72fb strb r3, [r7, #11]
|
|
8002a6a: 460b mov r3, r1
|
|
8002a6c: 813b strh r3, [r7, #8]
|
|
8002a6e: 4613 mov r3, r2
|
|
8002a70: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002a72: 2300 movs r3, #0
|
|
8002a74: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
8002a76: 7afb ldrb r3, [r7, #11]
|
|
8002a78: b299 uxth r1, r3
|
|
8002a7a: 88f8 ldrh r0, [r7, #6]
|
|
8002a7c: 893a ldrh r2, [r7, #8]
|
|
8002a7e: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8002a82: 9302 str r3, [sp, #8]
|
|
8002a84: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
8002a86: 9301 str r3, [sp, #4]
|
|
8002a88: 6a3b ldr r3, [r7, #32]
|
|
8002a8a: 9300 str r3, [sp, #0]
|
|
8002a8c: 4603 mov r3, r0
|
|
8002a8e: 68f8 ldr r0, [r7, #12]
|
|
8002a90: f005 fd50 bl 8008534 <HAL_I2C_Mem_Read>
|
|
8002a94: 4603 mov r3, r0
|
|
8002a96: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
8002a98: 7dfb ldrb r3, [r7, #23]
|
|
8002a9a: 2b00 cmp r3, #0
|
|
8002a9c: d004 beq.n 8002aa8 <I2Cx_ReadMultiple+0x50>
|
|
{
|
|
/* I2C error occurred */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
8002a9e: 7afb ldrb r3, [r7, #11]
|
|
8002aa0: 4619 mov r1, r3
|
|
8002aa2: 68f8 ldr r0, [r7, #12]
|
|
8002aa4: f000 f832 bl 8002b0c <I2Cx_Error>
|
|
}
|
|
return status;
|
|
8002aa8: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8002aaa: 4618 mov r0, r3
|
|
8002aac: 3718 adds r7, #24
|
|
8002aae: 46bd mov sp, r7
|
|
8002ab0: bd80 pop {r7, pc}
|
|
|
|
08002ab2 <I2Cx_WriteMultiple>:
|
|
uint8_t Addr,
|
|
uint16_t Reg,
|
|
uint16_t MemAddress,
|
|
uint8_t *Buffer,
|
|
uint16_t Length)
|
|
{
|
|
8002ab2: b580 push {r7, lr}
|
|
8002ab4: b08a sub sp, #40 ; 0x28
|
|
8002ab6: af04 add r7, sp, #16
|
|
8002ab8: 60f8 str r0, [r7, #12]
|
|
8002aba: 4608 mov r0, r1
|
|
8002abc: 4611 mov r1, r2
|
|
8002abe: 461a mov r2, r3
|
|
8002ac0: 4603 mov r3, r0
|
|
8002ac2: 72fb strb r3, [r7, #11]
|
|
8002ac4: 460b mov r3, r1
|
|
8002ac6: 813b strh r3, [r7, #8]
|
|
8002ac8: 4613 mov r3, r2
|
|
8002aca: 80fb strh r3, [r7, #6]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002acc: 2300 movs r3, #0
|
|
8002ace: 75fb strb r3, [r7, #23]
|
|
|
|
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
|
|
8002ad0: 7afb ldrb r3, [r7, #11]
|
|
8002ad2: b299 uxth r1, r3
|
|
8002ad4: 88f8 ldrh r0, [r7, #6]
|
|
8002ad6: 893a ldrh r2, [r7, #8]
|
|
8002ad8: f44f 737a mov.w r3, #1000 ; 0x3e8
|
|
8002adc: 9302 str r3, [sp, #8]
|
|
8002ade: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
8002ae0: 9301 str r3, [sp, #4]
|
|
8002ae2: 6a3b ldr r3, [r7, #32]
|
|
8002ae4: 9300 str r3, [sp, #0]
|
|
8002ae6: 4603 mov r3, r0
|
|
8002ae8: 68f8 ldr r0, [r7, #12]
|
|
8002aea: f005 fc0f bl 800830c <HAL_I2C_Mem_Write>
|
|
8002aee: 4603 mov r3, r0
|
|
8002af0: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check the communication status */
|
|
if(status != HAL_OK)
|
|
8002af2: 7dfb ldrb r3, [r7, #23]
|
|
8002af4: 2b00 cmp r3, #0
|
|
8002af6: d004 beq.n 8002b02 <I2Cx_WriteMultiple+0x50>
|
|
{
|
|
/* Re-Initiaize the I2C Bus */
|
|
I2Cx_Error(i2c_handler, Addr);
|
|
8002af8: 7afb ldrb r3, [r7, #11]
|
|
8002afa: 4619 mov r1, r3
|
|
8002afc: 68f8 ldr r0, [r7, #12]
|
|
8002afe: f000 f805 bl 8002b0c <I2Cx_Error>
|
|
}
|
|
return status;
|
|
8002b02: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8002b04: 4618 mov r0, r3
|
|
8002b06: 3718 adds r7, #24
|
|
8002b08: 46bd mov sp, r7
|
|
8002b0a: bd80 pop {r7, pc}
|
|
|
|
08002b0c <I2Cx_Error>:
|
|
* @param i2c_handler : I2C handler
|
|
* @param Addr: I2C Address
|
|
* @retval None
|
|
*/
|
|
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
|
|
{
|
|
8002b0c: b580 push {r7, lr}
|
|
8002b0e: b082 sub sp, #8
|
|
8002b10: af00 add r7, sp, #0
|
|
8002b12: 6078 str r0, [r7, #4]
|
|
8002b14: 460b mov r3, r1
|
|
8002b16: 70fb strb r3, [r7, #3]
|
|
/* De-initialize the I2C communication bus */
|
|
HAL_I2C_DeInit(i2c_handler);
|
|
8002b18: 6878 ldr r0, [r7, #4]
|
|
8002b1a: f005 fbc7 bl 80082ac <HAL_I2C_DeInit>
|
|
|
|
/* Re-Initialize the I2C communication bus */
|
|
I2Cx_Init(i2c_handler);
|
|
8002b1e: 6878 ldr r0, [r7, #4]
|
|
8002b20: f7ff ff5e bl 80029e0 <I2Cx_Init>
|
|
}
|
|
8002b24: bf00 nop
|
|
8002b26: 3708 adds r7, #8
|
|
8002b28: 46bd mov sp, r7
|
|
8002b2a: bd80 pop {r7, pc}
|
|
|
|
08002b2c <TS_IO_Init>:
|
|
/**
|
|
* @brief Initializes Touchscreen low level.
|
|
* @retval None
|
|
*/
|
|
void TS_IO_Init(void)
|
|
{
|
|
8002b2c: b580 push {r7, lr}
|
|
8002b2e: af00 add r7, sp, #0
|
|
I2Cx_Init(&hI2cAudioHandler);
|
|
8002b30: 4802 ldr r0, [pc, #8] ; (8002b3c <TS_IO_Init+0x10>)
|
|
8002b32: f7ff ff55 bl 80029e0 <I2Cx_Init>
|
|
}
|
|
8002b36: bf00 nop
|
|
8002b38: bd80 pop {r7, pc}
|
|
8002b3a: bf00 nop
|
|
8002b3c: 20000390 .word 0x20000390
|
|
|
|
08002b40 <TS_IO_Write>:
|
|
* @param Reg: Reg address
|
|
* @param Value: Data to be written
|
|
* @retval None
|
|
*/
|
|
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
|
{
|
|
8002b40: b580 push {r7, lr}
|
|
8002b42: b084 sub sp, #16
|
|
8002b44: af02 add r7, sp, #8
|
|
8002b46: 4603 mov r3, r0
|
|
8002b48: 71fb strb r3, [r7, #7]
|
|
8002b4a: 460b mov r3, r1
|
|
8002b4c: 71bb strb r3, [r7, #6]
|
|
8002b4e: 4613 mov r3, r2
|
|
8002b50: 717b strb r3, [r7, #5]
|
|
I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
|
|
8002b52: 79bb ldrb r3, [r7, #6]
|
|
8002b54: b29a uxth r2, r3
|
|
8002b56: 79f9 ldrb r1, [r7, #7]
|
|
8002b58: 2301 movs r3, #1
|
|
8002b5a: 9301 str r3, [sp, #4]
|
|
8002b5c: 1d7b adds r3, r7, #5
|
|
8002b5e: 9300 str r3, [sp, #0]
|
|
8002b60: 2301 movs r3, #1
|
|
8002b62: 4803 ldr r0, [pc, #12] ; (8002b70 <TS_IO_Write+0x30>)
|
|
8002b64: f7ff ffa5 bl 8002ab2 <I2Cx_WriteMultiple>
|
|
}
|
|
8002b68: bf00 nop
|
|
8002b6a: 3708 adds r7, #8
|
|
8002b6c: 46bd mov sp, r7
|
|
8002b6e: bd80 pop {r7, pc}
|
|
8002b70: 20000390 .word 0x20000390
|
|
|
|
08002b74 <TS_IO_Read>:
|
|
* @param Addr: I2C address
|
|
* @param Reg: Reg address
|
|
* @retval Data to be read
|
|
*/
|
|
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
|
|
{
|
|
8002b74: b580 push {r7, lr}
|
|
8002b76: b086 sub sp, #24
|
|
8002b78: af02 add r7, sp, #8
|
|
8002b7a: 4603 mov r3, r0
|
|
8002b7c: 460a mov r2, r1
|
|
8002b7e: 71fb strb r3, [r7, #7]
|
|
8002b80: 4613 mov r3, r2
|
|
8002b82: 71bb strb r3, [r7, #6]
|
|
uint8_t read_value = 0;
|
|
8002b84: 2300 movs r3, #0
|
|
8002b86: 73fb strb r3, [r7, #15]
|
|
|
|
I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
|
|
8002b88: 79bb ldrb r3, [r7, #6]
|
|
8002b8a: b29a uxth r2, r3
|
|
8002b8c: 79f9 ldrb r1, [r7, #7]
|
|
8002b8e: 2301 movs r3, #1
|
|
8002b90: 9301 str r3, [sp, #4]
|
|
8002b92: f107 030f add.w r3, r7, #15
|
|
8002b96: 9300 str r3, [sp, #0]
|
|
8002b98: 2301 movs r3, #1
|
|
8002b9a: 4804 ldr r0, [pc, #16] ; (8002bac <TS_IO_Read+0x38>)
|
|
8002b9c: f7ff ff5c bl 8002a58 <I2Cx_ReadMultiple>
|
|
|
|
return read_value;
|
|
8002ba0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002ba2: 4618 mov r0, r3
|
|
8002ba4: 3710 adds r7, #16
|
|
8002ba6: 46bd mov sp, r7
|
|
8002ba8: bd80 pop {r7, pc}
|
|
8002baa: bf00 nop
|
|
8002bac: 20000390 .word 0x20000390
|
|
|
|
08002bb0 <TS_IO_Delay>:
|
|
* @brief TS delay
|
|
* @param Delay: Delay in ms
|
|
* @retval None
|
|
*/
|
|
void TS_IO_Delay(uint32_t Delay)
|
|
{
|
|
8002bb0: b580 push {r7, lr}
|
|
8002bb2: b082 sub sp, #8
|
|
8002bb4: af00 add r7, sp, #0
|
|
8002bb6: 6078 str r0, [r7, #4]
|
|
HAL_Delay(Delay);
|
|
8002bb8: 6878 ldr r0, [r7, #4]
|
|
8002bba: f002 fb9d bl 80052f8 <HAL_Delay>
|
|
}
|
|
8002bbe: bf00 nop
|
|
8002bc0: 3708 adds r7, #8
|
|
8002bc2: 46bd mov sp, r7
|
|
8002bc4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002bc8 <BSP_LCD_Init>:
|
|
/**
|
|
* @brief Initializes the LCD.
|
|
* @retval LCD state
|
|
*/
|
|
uint8_t BSP_LCD_Init(void)
|
|
{
|
|
8002bc8: b580 push {r7, lr}
|
|
8002bca: af00 add r7, sp, #0
|
|
/* Select the used LCD */
|
|
|
|
/* The RK043FN48H LCD 480x272 is selected */
|
|
/* Timing Configuration */
|
|
hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
|
|
8002bcc: 4b31 ldr r3, [pc, #196] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bce: 2228 movs r2, #40 ; 0x28
|
|
8002bd0: 615a str r2, [r3, #20]
|
|
hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
|
|
8002bd2: 4b30 ldr r3, [pc, #192] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bd4: 2209 movs r2, #9
|
|
8002bd6: 619a str r2, [r3, #24]
|
|
hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
|
|
8002bd8: 4b2e ldr r3, [pc, #184] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bda: 2235 movs r2, #53 ; 0x35
|
|
8002bdc: 61da str r2, [r3, #28]
|
|
hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
|
|
8002bde: 4b2d ldr r3, [pc, #180] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002be0: 220b movs r2, #11
|
|
8002be2: 621a str r2, [r3, #32]
|
|
hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
|
|
8002be4: 4b2b ldr r3, [pc, #172] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002be6: f240 121b movw r2, #283 ; 0x11b
|
|
8002bea: 629a str r2, [r3, #40] ; 0x28
|
|
hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
|
|
8002bec: 4b29 ldr r3, [pc, #164] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bee: f240 2215 movw r2, #533 ; 0x215
|
|
8002bf2: 625a str r2, [r3, #36] ; 0x24
|
|
hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
|
|
8002bf4: 4b27 ldr r3, [pc, #156] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bf6: f240 121d movw r2, #285 ; 0x11d
|
|
8002bfa: 631a str r2, [r3, #48] ; 0x30
|
|
hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
|
|
8002bfc: 4b25 ldr r3, [pc, #148] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002bfe: f240 2235 movw r2, #565 ; 0x235
|
|
8002c02: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* LCD clock configuration */
|
|
BSP_LCD_ClockConfig(&hLtdcHandler, NULL);
|
|
8002c04: 2100 movs r1, #0
|
|
8002c06: 4823 ldr r0, [pc, #140] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c08: f000 fee8 bl 80039dc <BSP_LCD_ClockConfig>
|
|
|
|
/* Initialize the LCD pixel width and pixel height */
|
|
hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH;
|
|
8002c0c: 4b21 ldr r3, [pc, #132] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c0e: f44f 72f0 mov.w r2, #480 ; 0x1e0
|
|
8002c12: 661a str r2, [r3, #96] ; 0x60
|
|
hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;
|
|
8002c14: 4b1f ldr r3, [pc, #124] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c16: f44f 7288 mov.w r2, #272 ; 0x110
|
|
8002c1a: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
/* Background value */
|
|
hLtdcHandler.Init.Backcolor.Blue = 0;
|
|
8002c1c: 4b1d ldr r3, [pc, #116] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c1e: 2200 movs r2, #0
|
|
8002c20: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
hLtdcHandler.Init.Backcolor.Green = 0;
|
|
8002c24: 4b1b ldr r3, [pc, #108] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c26: 2200 movs r2, #0
|
|
8002c28: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
hLtdcHandler.Init.Backcolor.Red = 0;
|
|
8002c2c: 4b19 ldr r3, [pc, #100] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c2e: 2200 movs r2, #0
|
|
8002c30: f883 2036 strb.w r2, [r3, #54] ; 0x36
|
|
|
|
/* Polarity */
|
|
hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
|
8002c34: 4b17 ldr r3, [pc, #92] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c36: 2200 movs r2, #0
|
|
8002c38: 605a str r2, [r3, #4]
|
|
hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
|
8002c3a: 4b16 ldr r3, [pc, #88] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c3c: 2200 movs r2, #0
|
|
8002c3e: 609a str r2, [r3, #8]
|
|
hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
|
8002c40: 4b14 ldr r3, [pc, #80] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c42: 2200 movs r2, #0
|
|
8002c44: 60da str r2, [r3, #12]
|
|
hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
|
8002c46: 4b13 ldr r3, [pc, #76] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c48: 2200 movs r2, #0
|
|
8002c4a: 611a str r2, [r3, #16]
|
|
hLtdcHandler.Instance = LTDC;
|
|
8002c4c: 4b11 ldr r3, [pc, #68] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c4e: 4a12 ldr r2, [pc, #72] ; (8002c98 <BSP_LCD_Init+0xd0>)
|
|
8002c50: 601a str r2, [r3, #0]
|
|
|
|
if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET)
|
|
8002c52: 4810 ldr r0, [pc, #64] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c54: f006 fa1a bl 800908c <HAL_LTDC_GetState>
|
|
8002c58: 4603 mov r3, r0
|
|
8002c5a: 2b00 cmp r3, #0
|
|
8002c5c: d103 bne.n 8002c66 <BSP_LCD_Init+0x9e>
|
|
{
|
|
/* Initialize the LCD Msp: this __weak function can be rewritten by the application */
|
|
BSP_LCD_MspInit(&hLtdcHandler, NULL);
|
|
8002c5e: 2100 movs r1, #0
|
|
8002c60: 480c ldr r0, [pc, #48] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c62: f000 fde1 bl 8003828 <BSP_LCD_MspInit>
|
|
}
|
|
HAL_LTDC_Init(&hLtdcHandler);
|
|
8002c66: 480b ldr r0, [pc, #44] ; (8002c94 <BSP_LCD_Init+0xcc>)
|
|
8002c68: f006 f840 bl 8008cec <HAL_LTDC_Init>
|
|
|
|
/* Assert display enable LCD_DISP pin */
|
|
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
|
|
8002c6c: 2201 movs r2, #1
|
|
8002c6e: f44f 5180 mov.w r1, #4096 ; 0x1000
|
|
8002c72: 480a ldr r0, [pc, #40] ; (8002c9c <BSP_LCD_Init+0xd4>)
|
|
8002c74: f005 fa70 bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
/* Assert backlight LCD_BL_CTRL pin */
|
|
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
|
|
8002c78: 2201 movs r2, #1
|
|
8002c7a: 2108 movs r1, #8
|
|
8002c7c: 4808 ldr r0, [pc, #32] ; (8002ca0 <BSP_LCD_Init+0xd8>)
|
|
8002c7e: f005 fa6b bl 8008158 <HAL_GPIO_WritePin>
|
|
|
|
#if !defined(DATA_IN_ExtSDRAM)
|
|
/* Initialize the SDRAM */
|
|
BSP_SDRAM_Init();
|
|
8002c82: f001 f80f bl 8003ca4 <BSP_SDRAM_Init>
|
|
#endif
|
|
|
|
/* Initialize the font */
|
|
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
|
|
8002c86: 4807 ldr r0, [pc, #28] ; (8002ca4 <BSP_LCD_Init+0xdc>)
|
|
8002c88: f000 f8d8 bl 8002e3c <BSP_LCD_SetFont>
|
|
|
|
return LCD_OK;
|
|
8002c8c: 2300 movs r3, #0
|
|
}
|
|
8002c8e: 4618 mov r0, r3
|
|
8002c90: bd80 pop {r7, pc}
|
|
8002c92: bf00 nop
|
|
8002c94: 20008e70 .word 0x20008e70
|
|
8002c98: 40016800 .word 0x40016800
|
|
8002c9c: 40022000 .word 0x40022000
|
|
8002ca0: 40022800 .word 0x40022800
|
|
8002ca4: 20000050 .word 0x20000050
|
|
|
|
08002ca8 <BSP_LCD_GetXSize>:
|
|
/**
|
|
* @brief Gets the LCD X size.
|
|
* @retval Used LCD X size
|
|
*/
|
|
uint32_t BSP_LCD_GetXSize(void)
|
|
{
|
|
8002ca8: b480 push {r7}
|
|
8002caa: af00 add r7, sp, #0
|
|
return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth;
|
|
8002cac: 4b06 ldr r3, [pc, #24] ; (8002cc8 <BSP_LCD_GetXSize+0x20>)
|
|
8002cae: 681b ldr r3, [r3, #0]
|
|
8002cb0: 4a06 ldr r2, [pc, #24] ; (8002ccc <BSP_LCD_GetXSize+0x24>)
|
|
8002cb2: 2134 movs r1, #52 ; 0x34
|
|
8002cb4: fb01 f303 mul.w r3, r1, r3
|
|
8002cb8: 4413 add r3, r2
|
|
8002cba: 3360 adds r3, #96 ; 0x60
|
|
8002cbc: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002cbe: 4618 mov r0, r3
|
|
8002cc0: 46bd mov sp, r7
|
|
8002cc2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002cc6: 4770 bx lr
|
|
8002cc8: 2000041c .word 0x2000041c
|
|
8002ccc: 20008e70 .word 0x20008e70
|
|
|
|
08002cd0 <BSP_LCD_GetYSize>:
|
|
/**
|
|
* @brief Gets the LCD Y size.
|
|
* @retval Used LCD Y size
|
|
*/
|
|
uint32_t BSP_LCD_GetYSize(void)
|
|
{
|
|
8002cd0: b480 push {r7}
|
|
8002cd2: af00 add r7, sp, #0
|
|
return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight;
|
|
8002cd4: 4b06 ldr r3, [pc, #24] ; (8002cf0 <BSP_LCD_GetYSize+0x20>)
|
|
8002cd6: 681b ldr r3, [r3, #0]
|
|
8002cd8: 4a06 ldr r2, [pc, #24] ; (8002cf4 <BSP_LCD_GetYSize+0x24>)
|
|
8002cda: 2134 movs r1, #52 ; 0x34
|
|
8002cdc: fb01 f303 mul.w r3, r1, r3
|
|
8002ce0: 4413 add r3, r2
|
|
8002ce2: 3364 adds r3, #100 ; 0x64
|
|
8002ce4: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002ce6: 4618 mov r0, r3
|
|
8002ce8: 46bd mov sp, r7
|
|
8002cea: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002cee: 4770 bx lr
|
|
8002cf0: 2000041c .word 0x2000041c
|
|
8002cf4: 20008e70 .word 0x20008e70
|
|
|
|
08002cf8 <BSP_LCD_LayerDefaultInit>:
|
|
* @param LayerIndex: Layer foreground or background
|
|
* @param FB_Address: Layer frame buffer
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
|
|
{
|
|
8002cf8: b580 push {r7, lr}
|
|
8002cfa: b090 sub sp, #64 ; 0x40
|
|
8002cfc: af00 add r7, sp, #0
|
|
8002cfe: 4603 mov r3, r0
|
|
8002d00: 6039 str r1, [r7, #0]
|
|
8002d02: 80fb strh r3, [r7, #6]
|
|
LCD_LayerCfgTypeDef layer_cfg;
|
|
|
|
/* Layer Init */
|
|
layer_cfg.WindowX0 = 0;
|
|
8002d04: 2300 movs r3, #0
|
|
8002d06: 60fb str r3, [r7, #12]
|
|
layer_cfg.WindowX1 = BSP_LCD_GetXSize();
|
|
8002d08: f7ff ffce bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002d0c: 4603 mov r3, r0
|
|
8002d0e: 613b str r3, [r7, #16]
|
|
layer_cfg.WindowY0 = 0;
|
|
8002d10: 2300 movs r3, #0
|
|
8002d12: 617b str r3, [r7, #20]
|
|
layer_cfg.WindowY1 = BSP_LCD_GetYSize();
|
|
8002d14: f7ff ffdc bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8002d18: 4603 mov r3, r0
|
|
8002d1a: 61bb str r3, [r7, #24]
|
|
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
|
|
8002d1c: 2300 movs r3, #0
|
|
8002d1e: 61fb str r3, [r7, #28]
|
|
layer_cfg.FBStartAdress = FB_Address;
|
|
8002d20: 683b ldr r3, [r7, #0]
|
|
8002d22: 633b str r3, [r7, #48] ; 0x30
|
|
layer_cfg.Alpha = 255;
|
|
8002d24: 23ff movs r3, #255 ; 0xff
|
|
8002d26: 623b str r3, [r7, #32]
|
|
layer_cfg.Alpha0 = 0;
|
|
8002d28: 2300 movs r3, #0
|
|
8002d2a: 627b str r3, [r7, #36] ; 0x24
|
|
layer_cfg.Backcolor.Blue = 0;
|
|
8002d2c: 2300 movs r3, #0
|
|
8002d2e: f887 303c strb.w r3, [r7, #60] ; 0x3c
|
|
layer_cfg.Backcolor.Green = 0;
|
|
8002d32: 2300 movs r3, #0
|
|
8002d34: f887 303d strb.w r3, [r7, #61] ; 0x3d
|
|
layer_cfg.Backcolor.Red = 0;
|
|
8002d38: 2300 movs r3, #0
|
|
8002d3a: f887 303e strb.w r3, [r7, #62] ; 0x3e
|
|
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
|
|
8002d3e: f44f 63c0 mov.w r3, #1536 ; 0x600
|
|
8002d42: 62bb str r3, [r7, #40] ; 0x28
|
|
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
|
|
8002d44: 2307 movs r3, #7
|
|
8002d46: 62fb str r3, [r7, #44] ; 0x2c
|
|
layer_cfg.ImageWidth = BSP_LCD_GetXSize();
|
|
8002d48: f7ff ffae bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002d4c: 4603 mov r3, r0
|
|
8002d4e: 637b str r3, [r7, #52] ; 0x34
|
|
layer_cfg.ImageHeight = BSP_LCD_GetYSize();
|
|
8002d50: f7ff ffbe bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8002d54: 4603 mov r3, r0
|
|
8002d56: 63bb str r3, [r7, #56] ; 0x38
|
|
|
|
HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex);
|
|
8002d58: 88fa ldrh r2, [r7, #6]
|
|
8002d5a: f107 030c add.w r3, r7, #12
|
|
8002d5e: 4619 mov r1, r3
|
|
8002d60: 4812 ldr r0, [pc, #72] ; (8002dac <BSP_LCD_LayerDefaultInit+0xb4>)
|
|
8002d62: f006 f955 bl 8009010 <HAL_LTDC_ConfigLayer>
|
|
|
|
DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
|
|
8002d66: 88fa ldrh r2, [r7, #6]
|
|
8002d68: 4911 ldr r1, [pc, #68] ; (8002db0 <BSP_LCD_LayerDefaultInit+0xb8>)
|
|
8002d6a: 4613 mov r3, r2
|
|
8002d6c: 005b lsls r3, r3, #1
|
|
8002d6e: 4413 add r3, r2
|
|
8002d70: 009b lsls r3, r3, #2
|
|
8002d72: 440b add r3, r1
|
|
8002d74: 3304 adds r3, #4
|
|
8002d76: f04f 32ff mov.w r2, #4294967295
|
|
8002d7a: 601a str r2, [r3, #0]
|
|
DrawProp[LayerIndex].pFont = &Font24;
|
|
8002d7c: 88fa ldrh r2, [r7, #6]
|
|
8002d7e: 490c ldr r1, [pc, #48] ; (8002db0 <BSP_LCD_LayerDefaultInit+0xb8>)
|
|
8002d80: 4613 mov r3, r2
|
|
8002d82: 005b lsls r3, r3, #1
|
|
8002d84: 4413 add r3, r2
|
|
8002d86: 009b lsls r3, r3, #2
|
|
8002d88: 440b add r3, r1
|
|
8002d8a: 3308 adds r3, #8
|
|
8002d8c: 4a09 ldr r2, [pc, #36] ; (8002db4 <BSP_LCD_LayerDefaultInit+0xbc>)
|
|
8002d8e: 601a str r2, [r3, #0]
|
|
DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
|
|
8002d90: 88fa ldrh r2, [r7, #6]
|
|
8002d92: 4907 ldr r1, [pc, #28] ; (8002db0 <BSP_LCD_LayerDefaultInit+0xb8>)
|
|
8002d94: 4613 mov r3, r2
|
|
8002d96: 005b lsls r3, r3, #1
|
|
8002d98: 4413 add r3, r2
|
|
8002d9a: 009b lsls r3, r3, #2
|
|
8002d9c: 440b add r3, r1
|
|
8002d9e: f04f 427f mov.w r2, #4278190080 ; 0xff000000
|
|
8002da2: 601a str r2, [r3, #0]
|
|
}
|
|
8002da4: bf00 nop
|
|
8002da6: 3740 adds r7, #64 ; 0x40
|
|
8002da8: 46bd mov sp, r7
|
|
8002daa: bd80 pop {r7, pc}
|
|
8002dac: 20008e70 .word 0x20008e70
|
|
8002db0: 20000420 .word 0x20000420
|
|
8002db4: 20000050 .word 0x20000050
|
|
|
|
08002db8 <BSP_LCD_SelectLayer>:
|
|
* @brief Selects the LCD Layer.
|
|
* @param LayerIndex: Layer foreground or background
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_SelectLayer(uint32_t LayerIndex)
|
|
{
|
|
8002db8: b480 push {r7}
|
|
8002dba: b083 sub sp, #12
|
|
8002dbc: af00 add r7, sp, #0
|
|
8002dbe: 6078 str r0, [r7, #4]
|
|
ActiveLayer = LayerIndex;
|
|
8002dc0: 4a04 ldr r2, [pc, #16] ; (8002dd4 <BSP_LCD_SelectLayer+0x1c>)
|
|
8002dc2: 687b ldr r3, [r7, #4]
|
|
8002dc4: 6013 str r3, [r2, #0]
|
|
}
|
|
8002dc6: bf00 nop
|
|
8002dc8: 370c adds r7, #12
|
|
8002dca: 46bd mov sp, r7
|
|
8002dcc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002dd0: 4770 bx lr
|
|
8002dd2: bf00 nop
|
|
8002dd4: 2000041c .word 0x2000041c
|
|
|
|
08002dd8 <BSP_LCD_SetTextColor>:
|
|
* @brief Sets the LCD text color.
|
|
* @param Color: Text color code ARGB(8-8-8-8)
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_SetTextColor(uint32_t Color)
|
|
{
|
|
8002dd8: b480 push {r7}
|
|
8002dda: b083 sub sp, #12
|
|
8002ddc: af00 add r7, sp, #0
|
|
8002dde: 6078 str r0, [r7, #4]
|
|
DrawProp[ActiveLayer].TextColor = Color;
|
|
8002de0: 4b07 ldr r3, [pc, #28] ; (8002e00 <BSP_LCD_SetTextColor+0x28>)
|
|
8002de2: 681a ldr r2, [r3, #0]
|
|
8002de4: 4907 ldr r1, [pc, #28] ; (8002e04 <BSP_LCD_SetTextColor+0x2c>)
|
|
8002de6: 4613 mov r3, r2
|
|
8002de8: 005b lsls r3, r3, #1
|
|
8002dea: 4413 add r3, r2
|
|
8002dec: 009b lsls r3, r3, #2
|
|
8002dee: 440b add r3, r1
|
|
8002df0: 687a ldr r2, [r7, #4]
|
|
8002df2: 601a str r2, [r3, #0]
|
|
}
|
|
8002df4: bf00 nop
|
|
8002df6: 370c adds r7, #12
|
|
8002df8: 46bd mov sp, r7
|
|
8002dfa: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002dfe: 4770 bx lr
|
|
8002e00: 2000041c .word 0x2000041c
|
|
8002e04: 20000420 .word 0x20000420
|
|
|
|
08002e08 <BSP_LCD_SetBackColor>:
|
|
* @brief Sets the LCD background color.
|
|
* @param Color: Layer background color code ARGB(8-8-8-8)
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_SetBackColor(uint32_t Color)
|
|
{
|
|
8002e08: b480 push {r7}
|
|
8002e0a: b083 sub sp, #12
|
|
8002e0c: af00 add r7, sp, #0
|
|
8002e0e: 6078 str r0, [r7, #4]
|
|
DrawProp[ActiveLayer].BackColor = Color;
|
|
8002e10: 4b08 ldr r3, [pc, #32] ; (8002e34 <BSP_LCD_SetBackColor+0x2c>)
|
|
8002e12: 681a ldr r2, [r3, #0]
|
|
8002e14: 4908 ldr r1, [pc, #32] ; (8002e38 <BSP_LCD_SetBackColor+0x30>)
|
|
8002e16: 4613 mov r3, r2
|
|
8002e18: 005b lsls r3, r3, #1
|
|
8002e1a: 4413 add r3, r2
|
|
8002e1c: 009b lsls r3, r3, #2
|
|
8002e1e: 440b add r3, r1
|
|
8002e20: 3304 adds r3, #4
|
|
8002e22: 687a ldr r2, [r7, #4]
|
|
8002e24: 601a str r2, [r3, #0]
|
|
}
|
|
8002e26: bf00 nop
|
|
8002e28: 370c adds r7, #12
|
|
8002e2a: 46bd mov sp, r7
|
|
8002e2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e30: 4770 bx lr
|
|
8002e32: bf00 nop
|
|
8002e34: 2000041c .word 0x2000041c
|
|
8002e38: 20000420 .word 0x20000420
|
|
|
|
08002e3c <BSP_LCD_SetFont>:
|
|
* @brief Sets the LCD text font.
|
|
* @param fonts: Layer font to be used
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_SetFont(sFONT *fonts)
|
|
{
|
|
8002e3c: b480 push {r7}
|
|
8002e3e: b083 sub sp, #12
|
|
8002e40: af00 add r7, sp, #0
|
|
8002e42: 6078 str r0, [r7, #4]
|
|
DrawProp[ActiveLayer].pFont = fonts;
|
|
8002e44: 4b08 ldr r3, [pc, #32] ; (8002e68 <BSP_LCD_SetFont+0x2c>)
|
|
8002e46: 681a ldr r2, [r3, #0]
|
|
8002e48: 4908 ldr r1, [pc, #32] ; (8002e6c <BSP_LCD_SetFont+0x30>)
|
|
8002e4a: 4613 mov r3, r2
|
|
8002e4c: 005b lsls r3, r3, #1
|
|
8002e4e: 4413 add r3, r2
|
|
8002e50: 009b lsls r3, r3, #2
|
|
8002e52: 440b add r3, r1
|
|
8002e54: 3308 adds r3, #8
|
|
8002e56: 687a ldr r2, [r7, #4]
|
|
8002e58: 601a str r2, [r3, #0]
|
|
}
|
|
8002e5a: bf00 nop
|
|
8002e5c: 370c adds r7, #12
|
|
8002e5e: 46bd mov sp, r7
|
|
8002e60: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e64: 4770 bx lr
|
|
8002e66: bf00 nop
|
|
8002e68: 2000041c .word 0x2000041c
|
|
8002e6c: 20000420 .word 0x20000420
|
|
|
|
08002e70 <BSP_LCD_GetFont>:
|
|
/**
|
|
* @brief Gets the LCD text font.
|
|
* @retval Used layer font
|
|
*/
|
|
sFONT *BSP_LCD_GetFont(void)
|
|
{
|
|
8002e70: b480 push {r7}
|
|
8002e72: af00 add r7, sp, #0
|
|
return DrawProp[ActiveLayer].pFont;
|
|
8002e74: 4b07 ldr r3, [pc, #28] ; (8002e94 <BSP_LCD_GetFont+0x24>)
|
|
8002e76: 681a ldr r2, [r3, #0]
|
|
8002e78: 4907 ldr r1, [pc, #28] ; (8002e98 <BSP_LCD_GetFont+0x28>)
|
|
8002e7a: 4613 mov r3, r2
|
|
8002e7c: 005b lsls r3, r3, #1
|
|
8002e7e: 4413 add r3, r2
|
|
8002e80: 009b lsls r3, r3, #2
|
|
8002e82: 440b add r3, r1
|
|
8002e84: 3308 adds r3, #8
|
|
8002e86: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002e88: 4618 mov r0, r3
|
|
8002e8a: 46bd mov sp, r7
|
|
8002e8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002e90: 4770 bx lr
|
|
8002e92: bf00 nop
|
|
8002e94: 2000041c .word 0x2000041c
|
|
8002e98: 20000420 .word 0x20000420
|
|
|
|
08002e9c <BSP_LCD_Clear>:
|
|
* @brief Clears the hole LCD.
|
|
* @param Color: Color of the background
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_Clear(uint32_t Color)
|
|
{
|
|
8002e9c: b5f0 push {r4, r5, r6, r7, lr}
|
|
8002e9e: b085 sub sp, #20
|
|
8002ea0: af02 add r7, sp, #8
|
|
8002ea2: 6078 str r0, [r7, #4]
|
|
/* Clear the LCD */
|
|
LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
|
|
8002ea4: 4b0f ldr r3, [pc, #60] ; (8002ee4 <BSP_LCD_Clear+0x48>)
|
|
8002ea6: 681c ldr r4, [r3, #0]
|
|
8002ea8: 4b0e ldr r3, [pc, #56] ; (8002ee4 <BSP_LCD_Clear+0x48>)
|
|
8002eaa: 681b ldr r3, [r3, #0]
|
|
8002eac: 4a0e ldr r2, [pc, #56] ; (8002ee8 <BSP_LCD_Clear+0x4c>)
|
|
8002eae: 2134 movs r1, #52 ; 0x34
|
|
8002eb0: fb01 f303 mul.w r3, r1, r3
|
|
8002eb4: 4413 add r3, r2
|
|
8002eb6: 335c adds r3, #92 ; 0x5c
|
|
8002eb8: 681b ldr r3, [r3, #0]
|
|
8002eba: 461d mov r5, r3
|
|
8002ebc: f7ff fef4 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002ec0: 4606 mov r6, r0
|
|
8002ec2: f7ff ff05 bl 8002cd0 <BSP_LCD_GetYSize>
|
|
8002ec6: 4602 mov r2, r0
|
|
8002ec8: 687b ldr r3, [r7, #4]
|
|
8002eca: 9301 str r3, [sp, #4]
|
|
8002ecc: 2300 movs r3, #0
|
|
8002ece: 9300 str r3, [sp, #0]
|
|
8002ed0: 4613 mov r3, r2
|
|
8002ed2: 4632 mov r2, r6
|
|
8002ed4: 4629 mov r1, r5
|
|
8002ed6: 4620 mov r0, r4
|
|
8002ed8: f000 fe54 bl 8003b84 <LL_FillBuffer>
|
|
}
|
|
8002edc: bf00 nop
|
|
8002ede: 370c adds r7, #12
|
|
8002ee0: 46bd mov sp, r7
|
|
8002ee2: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8002ee4: 2000041c .word 0x2000041c
|
|
8002ee8: 20008e70 .word 0x20008e70
|
|
|
|
08002eec <BSP_LCD_DisplayChar>:
|
|
* @param Ascii: Character ascii code
|
|
* This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii)
|
|
{
|
|
8002eec: b590 push {r4, r7, lr}
|
|
8002eee: b083 sub sp, #12
|
|
8002ef0: af00 add r7, sp, #0
|
|
8002ef2: 4603 mov r3, r0
|
|
8002ef4: 80fb strh r3, [r7, #6]
|
|
8002ef6: 460b mov r3, r1
|
|
8002ef8: 80bb strh r3, [r7, #4]
|
|
8002efa: 4613 mov r3, r2
|
|
8002efc: 70fb strb r3, [r7, #3]
|
|
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
|
|
8002efe: 4b1b ldr r3, [pc, #108] ; (8002f6c <BSP_LCD_DisplayChar+0x80>)
|
|
8002f00: 681a ldr r2, [r3, #0]
|
|
8002f02: 491b ldr r1, [pc, #108] ; (8002f70 <BSP_LCD_DisplayChar+0x84>)
|
|
8002f04: 4613 mov r3, r2
|
|
8002f06: 005b lsls r3, r3, #1
|
|
8002f08: 4413 add r3, r2
|
|
8002f0a: 009b lsls r3, r3, #2
|
|
8002f0c: 440b add r3, r1
|
|
8002f0e: 3308 adds r3, #8
|
|
8002f10: 681b ldr r3, [r3, #0]
|
|
8002f12: 6819 ldr r1, [r3, #0]
|
|
8002f14: 78fb ldrb r3, [r7, #3]
|
|
8002f16: f1a3 0020 sub.w r0, r3, #32
|
|
DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);
|
|
8002f1a: 4b14 ldr r3, [pc, #80] ; (8002f6c <BSP_LCD_DisplayChar+0x80>)
|
|
8002f1c: 681a ldr r2, [r3, #0]
|
|
8002f1e: 4c14 ldr r4, [pc, #80] ; (8002f70 <BSP_LCD_DisplayChar+0x84>)
|
|
8002f20: 4613 mov r3, r2
|
|
8002f22: 005b lsls r3, r3, #1
|
|
8002f24: 4413 add r3, r2
|
|
8002f26: 009b lsls r3, r3, #2
|
|
8002f28: 4423 add r3, r4
|
|
8002f2a: 3308 adds r3, #8
|
|
8002f2c: 681b ldr r3, [r3, #0]
|
|
8002f2e: 88db ldrh r3, [r3, #6]
|
|
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
|
|
8002f30: fb03 f000 mul.w r0, r3, r0
|
|
DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);
|
|
8002f34: 4b0d ldr r3, [pc, #52] ; (8002f6c <BSP_LCD_DisplayChar+0x80>)
|
|
8002f36: 681a ldr r2, [r3, #0]
|
|
8002f38: 4c0d ldr r4, [pc, #52] ; (8002f70 <BSP_LCD_DisplayChar+0x84>)
|
|
8002f3a: 4613 mov r3, r2
|
|
8002f3c: 005b lsls r3, r3, #1
|
|
8002f3e: 4413 add r3, r2
|
|
8002f40: 009b lsls r3, r3, #2
|
|
8002f42: 4423 add r3, r4
|
|
8002f44: 3308 adds r3, #8
|
|
8002f46: 681b ldr r3, [r3, #0]
|
|
8002f48: 889b ldrh r3, [r3, #4]
|
|
8002f4a: 3307 adds r3, #7
|
|
8002f4c: 2b00 cmp r3, #0
|
|
8002f4e: da00 bge.n 8002f52 <BSP_LCD_DisplayChar+0x66>
|
|
8002f50: 3307 adds r3, #7
|
|
8002f52: 10db asrs r3, r3, #3
|
|
8002f54: fb03 f300 mul.w r3, r3, r0
|
|
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
|
|
8002f58: 18ca adds r2, r1, r3
|
|
8002f5a: 88b9 ldrh r1, [r7, #4]
|
|
8002f5c: 88fb ldrh r3, [r7, #6]
|
|
8002f5e: 4618 mov r0, r3
|
|
8002f60: f000 fd58 bl 8003a14 <DrawChar>
|
|
}
|
|
8002f64: bf00 nop
|
|
8002f66: 370c adds r7, #12
|
|
8002f68: 46bd mov sp, r7
|
|
8002f6a: bd90 pop {r4, r7, pc}
|
|
8002f6c: 2000041c .word 0x2000041c
|
|
8002f70: 20000420 .word 0x20000420
|
|
|
|
08002f74 <BSP_LCD_DisplayStringAt>:
|
|
* @arg RIGHT_MODE
|
|
* @arg LEFT_MODE
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode)
|
|
{
|
|
8002f74: b5b0 push {r4, r5, r7, lr}
|
|
8002f76: b088 sub sp, #32
|
|
8002f78: af00 add r7, sp, #0
|
|
8002f7a: 60ba str r2, [r7, #8]
|
|
8002f7c: 461a mov r2, r3
|
|
8002f7e: 4603 mov r3, r0
|
|
8002f80: 81fb strh r3, [r7, #14]
|
|
8002f82: 460b mov r3, r1
|
|
8002f84: 81bb strh r3, [r7, #12]
|
|
8002f86: 4613 mov r3, r2
|
|
8002f88: 71fb strb r3, [r7, #7]
|
|
uint16_t ref_column = 1, i = 0;
|
|
8002f8a: 2301 movs r3, #1
|
|
8002f8c: 83fb strh r3, [r7, #30]
|
|
8002f8e: 2300 movs r3, #0
|
|
8002f90: 83bb strh r3, [r7, #28]
|
|
uint32_t size = 0, xsize = 0;
|
|
8002f92: 2300 movs r3, #0
|
|
8002f94: 61bb str r3, [r7, #24]
|
|
8002f96: 2300 movs r3, #0
|
|
8002f98: 613b str r3, [r7, #16]
|
|
uint8_t *ptr = Text;
|
|
8002f9a: 68bb ldr r3, [r7, #8]
|
|
8002f9c: 617b str r3, [r7, #20]
|
|
|
|
/* Get the text size */
|
|
while (*ptr++) size ++ ;
|
|
8002f9e: e002 b.n 8002fa6 <BSP_LCD_DisplayStringAt+0x32>
|
|
8002fa0: 69bb ldr r3, [r7, #24]
|
|
8002fa2: 3301 adds r3, #1
|
|
8002fa4: 61bb str r3, [r7, #24]
|
|
8002fa6: 697b ldr r3, [r7, #20]
|
|
8002fa8: 1c5a adds r2, r3, #1
|
|
8002faa: 617a str r2, [r7, #20]
|
|
8002fac: 781b ldrb r3, [r3, #0]
|
|
8002fae: 2b00 cmp r3, #0
|
|
8002fb0: d1f6 bne.n 8002fa0 <BSP_LCD_DisplayStringAt+0x2c>
|
|
|
|
/* Characters number per line */
|
|
xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width);
|
|
8002fb2: f7ff fe79 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8002fb6: 4b4f ldr r3, [pc, #316] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
8002fb8: 681a ldr r2, [r3, #0]
|
|
8002fba: 494f ldr r1, [pc, #316] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
8002fbc: 4613 mov r3, r2
|
|
8002fbe: 005b lsls r3, r3, #1
|
|
8002fc0: 4413 add r3, r2
|
|
8002fc2: 009b lsls r3, r3, #2
|
|
8002fc4: 440b add r3, r1
|
|
8002fc6: 3308 adds r3, #8
|
|
8002fc8: 681b ldr r3, [r3, #0]
|
|
8002fca: 889b ldrh r3, [r3, #4]
|
|
8002fcc: fbb0 f3f3 udiv r3, r0, r3
|
|
8002fd0: 613b str r3, [r7, #16]
|
|
|
|
switch (Mode)
|
|
8002fd2: 79fb ldrb r3, [r7, #7]
|
|
8002fd4: 2b02 cmp r3, #2
|
|
8002fd6: d01c beq.n 8003012 <BSP_LCD_DisplayStringAt+0x9e>
|
|
8002fd8: 2b03 cmp r3, #3
|
|
8002fda: d017 beq.n 800300c <BSP_LCD_DisplayStringAt+0x98>
|
|
8002fdc: 2b01 cmp r3, #1
|
|
8002fde: d12e bne.n 800303e <BSP_LCD_DisplayStringAt+0xca>
|
|
{
|
|
case CENTER_MODE:
|
|
{
|
|
ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2;
|
|
8002fe0: 693a ldr r2, [r7, #16]
|
|
8002fe2: 69bb ldr r3, [r7, #24]
|
|
8002fe4: 1ad1 subs r1, r2, r3
|
|
8002fe6: 4b43 ldr r3, [pc, #268] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
8002fe8: 681a ldr r2, [r3, #0]
|
|
8002fea: 4843 ldr r0, [pc, #268] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
8002fec: 4613 mov r3, r2
|
|
8002fee: 005b lsls r3, r3, #1
|
|
8002ff0: 4413 add r3, r2
|
|
8002ff2: 009b lsls r3, r3, #2
|
|
8002ff4: 4403 add r3, r0
|
|
8002ff6: 3308 adds r3, #8
|
|
8002ff8: 681b ldr r3, [r3, #0]
|
|
8002ffa: 889b ldrh r3, [r3, #4]
|
|
8002ffc: fb03 f301 mul.w r3, r3, r1
|
|
8003000: 085b lsrs r3, r3, #1
|
|
8003002: b29a uxth r2, r3
|
|
8003004: 89fb ldrh r3, [r7, #14]
|
|
8003006: 4413 add r3, r2
|
|
8003008: 83fb strh r3, [r7, #30]
|
|
break;
|
|
800300a: e01b b.n 8003044 <BSP_LCD_DisplayStringAt+0xd0>
|
|
}
|
|
case LEFT_MODE:
|
|
{
|
|
ref_column = Xpos;
|
|
800300c: 89fb ldrh r3, [r7, #14]
|
|
800300e: 83fb strh r3, [r7, #30]
|
|
break;
|
|
8003010: e018 b.n 8003044 <BSP_LCD_DisplayStringAt+0xd0>
|
|
}
|
|
case RIGHT_MODE:
|
|
{
|
|
ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width);
|
|
8003012: 693a ldr r2, [r7, #16]
|
|
8003014: 69bb ldr r3, [r7, #24]
|
|
8003016: 1ad3 subs r3, r2, r3
|
|
8003018: b299 uxth r1, r3
|
|
800301a: 4b36 ldr r3, [pc, #216] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
800301c: 681a ldr r2, [r3, #0]
|
|
800301e: 4836 ldr r0, [pc, #216] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
8003020: 4613 mov r3, r2
|
|
8003022: 005b lsls r3, r3, #1
|
|
8003024: 4413 add r3, r2
|
|
8003026: 009b lsls r3, r3, #2
|
|
8003028: 4403 add r3, r0
|
|
800302a: 3308 adds r3, #8
|
|
800302c: 681b ldr r3, [r3, #0]
|
|
800302e: 889b ldrh r3, [r3, #4]
|
|
8003030: fb11 f303 smulbb r3, r1, r3
|
|
8003034: b29a uxth r2, r3
|
|
8003036: 89fb ldrh r3, [r7, #14]
|
|
8003038: 1ad3 subs r3, r2, r3
|
|
800303a: 83fb strh r3, [r7, #30]
|
|
break;
|
|
800303c: e002 b.n 8003044 <BSP_LCD_DisplayStringAt+0xd0>
|
|
}
|
|
default:
|
|
{
|
|
ref_column = Xpos;
|
|
800303e: 89fb ldrh r3, [r7, #14]
|
|
8003040: 83fb strh r3, [r7, #30]
|
|
break;
|
|
8003042: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* Check that the Start column is located in the screen */
|
|
if ((ref_column < 1) || (ref_column >= 0x8000))
|
|
8003044: 8bfb ldrh r3, [r7, #30]
|
|
8003046: 2b00 cmp r3, #0
|
|
8003048: d003 beq.n 8003052 <BSP_LCD_DisplayStringAt+0xde>
|
|
800304a: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
800304e: 2b00 cmp r3, #0
|
|
8003050: da1d bge.n 800308e <BSP_LCD_DisplayStringAt+0x11a>
|
|
{
|
|
ref_column = 1;
|
|
8003052: 2301 movs r3, #1
|
|
8003054: 83fb strh r3, [r7, #30]
|
|
}
|
|
|
|
/* Send the string character by character on LCD */
|
|
while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))
|
|
8003056: e01a b.n 800308e <BSP_LCD_DisplayStringAt+0x11a>
|
|
{
|
|
/* Display one character on LCD */
|
|
BSP_LCD_DisplayChar(ref_column, Ypos, *Text);
|
|
8003058: 68bb ldr r3, [r7, #8]
|
|
800305a: 781a ldrb r2, [r3, #0]
|
|
800305c: 89b9 ldrh r1, [r7, #12]
|
|
800305e: 8bfb ldrh r3, [r7, #30]
|
|
8003060: 4618 mov r0, r3
|
|
8003062: f7ff ff43 bl 8002eec <BSP_LCD_DisplayChar>
|
|
/* Decrement the column position by 16 */
|
|
ref_column += DrawProp[ActiveLayer].pFont->Width;
|
|
8003066: 4b23 ldr r3, [pc, #140] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
8003068: 681a ldr r2, [r3, #0]
|
|
800306a: 4923 ldr r1, [pc, #140] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
800306c: 4613 mov r3, r2
|
|
800306e: 005b lsls r3, r3, #1
|
|
8003070: 4413 add r3, r2
|
|
8003072: 009b lsls r3, r3, #2
|
|
8003074: 440b add r3, r1
|
|
8003076: 3308 adds r3, #8
|
|
8003078: 681b ldr r3, [r3, #0]
|
|
800307a: 889a ldrh r2, [r3, #4]
|
|
800307c: 8bfb ldrh r3, [r7, #30]
|
|
800307e: 4413 add r3, r2
|
|
8003080: 83fb strh r3, [r7, #30]
|
|
/* Point on the next character */
|
|
Text++;
|
|
8003082: 68bb ldr r3, [r7, #8]
|
|
8003084: 3301 adds r3, #1
|
|
8003086: 60bb str r3, [r7, #8]
|
|
i++;
|
|
8003088: 8bbb ldrh r3, [r7, #28]
|
|
800308a: 3301 adds r3, #1
|
|
800308c: 83bb strh r3, [r7, #28]
|
|
while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))
|
|
800308e: 68bb ldr r3, [r7, #8]
|
|
8003090: 781b ldrb r3, [r3, #0]
|
|
8003092: 2b00 cmp r3, #0
|
|
8003094: bf14 ite ne
|
|
8003096: 2301 movne r3, #1
|
|
8003098: 2300 moveq r3, #0
|
|
800309a: b2dc uxtb r4, r3
|
|
800309c: f7ff fe04 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
80030a0: 4605 mov r5, r0
|
|
80030a2: 8bb9 ldrh r1, [r7, #28]
|
|
80030a4: 4b13 ldr r3, [pc, #76] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
80030a6: 681a ldr r2, [r3, #0]
|
|
80030a8: 4813 ldr r0, [pc, #76] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
80030aa: 4613 mov r3, r2
|
|
80030ac: 005b lsls r3, r3, #1
|
|
80030ae: 4413 add r3, r2
|
|
80030b0: 009b lsls r3, r3, #2
|
|
80030b2: 4403 add r3, r0
|
|
80030b4: 3308 adds r3, #8
|
|
80030b6: 681b ldr r3, [r3, #0]
|
|
80030b8: 889b ldrh r3, [r3, #4]
|
|
80030ba: fb03 f301 mul.w r3, r3, r1
|
|
80030be: 1aeb subs r3, r5, r3
|
|
80030c0: b299 uxth r1, r3
|
|
80030c2: 4b0c ldr r3, [pc, #48] ; (80030f4 <BSP_LCD_DisplayStringAt+0x180>)
|
|
80030c4: 681a ldr r2, [r3, #0]
|
|
80030c6: 480c ldr r0, [pc, #48] ; (80030f8 <BSP_LCD_DisplayStringAt+0x184>)
|
|
80030c8: 4613 mov r3, r2
|
|
80030ca: 005b lsls r3, r3, #1
|
|
80030cc: 4413 add r3, r2
|
|
80030ce: 009b lsls r3, r3, #2
|
|
80030d0: 4403 add r3, r0
|
|
80030d2: 3308 adds r3, #8
|
|
80030d4: 681b ldr r3, [r3, #0]
|
|
80030d6: 889b ldrh r3, [r3, #4]
|
|
80030d8: 4299 cmp r1, r3
|
|
80030da: bf2c ite cs
|
|
80030dc: 2301 movcs r3, #1
|
|
80030de: 2300 movcc r3, #0
|
|
80030e0: b2db uxtb r3, r3
|
|
80030e2: 4023 ands r3, r4
|
|
80030e4: b2db uxtb r3, r3
|
|
80030e6: 2b00 cmp r3, #0
|
|
80030e8: d1b6 bne.n 8003058 <BSP_LCD_DisplayStringAt+0xe4>
|
|
}
|
|
}
|
|
80030ea: bf00 nop
|
|
80030ec: 3720 adds r7, #32
|
|
80030ee: 46bd mov sp, r7
|
|
80030f0: bdb0 pop {r4, r5, r7, pc}
|
|
80030f2: bf00 nop
|
|
80030f4: 2000041c .word 0x2000041c
|
|
80030f8: 20000420 .word 0x20000420
|
|
|
|
080030fc <BSP_LCD_DisplayStringAtLine>:
|
|
* @param Line: Line where to display the character shape
|
|
* @param ptr: Pointer to string to display on LCD
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr)
|
|
{
|
|
80030fc: b580 push {r7, lr}
|
|
80030fe: b082 sub sp, #8
|
|
8003100: af00 add r7, sp, #0
|
|
8003102: 4603 mov r3, r0
|
|
8003104: 6039 str r1, [r7, #0]
|
|
8003106: 80fb strh r3, [r7, #6]
|
|
BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE);
|
|
8003108: f7ff feb2 bl 8002e70 <BSP_LCD_GetFont>
|
|
800310c: 4603 mov r3, r0
|
|
800310e: 88db ldrh r3, [r3, #6]
|
|
8003110: 88fa ldrh r2, [r7, #6]
|
|
8003112: fb12 f303 smulbb r3, r2, r3
|
|
8003116: b299 uxth r1, r3
|
|
8003118: 2303 movs r3, #3
|
|
800311a: 683a ldr r2, [r7, #0]
|
|
800311c: 2000 movs r0, #0
|
|
800311e: f7ff ff29 bl 8002f74 <BSP_LCD_DisplayStringAt>
|
|
}
|
|
8003122: bf00 nop
|
|
8003124: 3708 adds r7, #8
|
|
8003126: 46bd mov sp, r7
|
|
8003128: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800312c <BSP_LCD_DrawHLine>:
|
|
* @param Ypos: Y position
|
|
* @param Length: Line length
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
|
|
{
|
|
800312c: b5b0 push {r4, r5, r7, lr}
|
|
800312e: b086 sub sp, #24
|
|
8003130: af02 add r7, sp, #8
|
|
8003132: 4603 mov r3, r0
|
|
8003134: 80fb strh r3, [r7, #6]
|
|
8003136: 460b mov r3, r1
|
|
8003138: 80bb strh r3, [r7, #4]
|
|
800313a: 4613 mov r3, r2
|
|
800313c: 807b strh r3, [r7, #2]
|
|
uint32_t Xaddress = 0;
|
|
800313e: 2300 movs r3, #0
|
|
8003140: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the line address */
|
|
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
|
|
8003142: 4b26 ldr r3, [pc, #152] ; (80031dc <BSP_LCD_DrawHLine+0xb0>)
|
|
8003144: 681b ldr r3, [r3, #0]
|
|
8003146: 4a26 ldr r2, [pc, #152] ; (80031e0 <BSP_LCD_DrawHLine+0xb4>)
|
|
8003148: 2134 movs r1, #52 ; 0x34
|
|
800314a: fb01 f303 mul.w r3, r1, r3
|
|
800314e: 4413 add r3, r2
|
|
8003150: 3348 adds r3, #72 ; 0x48
|
|
8003152: 681b ldr r3, [r3, #0]
|
|
8003154: 2b02 cmp r3, #2
|
|
8003156: d114 bne.n 8003182 <BSP_LCD_DrawHLine+0x56>
|
|
{ /* RGB565 format */
|
|
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
|
|
8003158: 4b20 ldr r3, [pc, #128] ; (80031dc <BSP_LCD_DrawHLine+0xb0>)
|
|
800315a: 681b ldr r3, [r3, #0]
|
|
800315c: 4a20 ldr r2, [pc, #128] ; (80031e0 <BSP_LCD_DrawHLine+0xb4>)
|
|
800315e: 2134 movs r1, #52 ; 0x34
|
|
8003160: fb01 f303 mul.w r3, r1, r3
|
|
8003164: 4413 add r3, r2
|
|
8003166: 335c adds r3, #92 ; 0x5c
|
|
8003168: 681c ldr r4, [r3, #0]
|
|
800316a: f7ff fd9d bl 8002ca8 <BSP_LCD_GetXSize>
|
|
800316e: 4602 mov r2, r0
|
|
8003170: 88bb ldrh r3, [r7, #4]
|
|
8003172: fb03 f202 mul.w r2, r3, r2
|
|
8003176: 88fb ldrh r3, [r7, #6]
|
|
8003178: 4413 add r3, r2
|
|
800317a: 005b lsls r3, r3, #1
|
|
800317c: 4423 add r3, r4
|
|
800317e: 60fb str r3, [r7, #12]
|
|
8003180: e013 b.n 80031aa <BSP_LCD_DrawHLine+0x7e>
|
|
}
|
|
else
|
|
{ /* ARGB8888 format */
|
|
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
|
|
8003182: 4b16 ldr r3, [pc, #88] ; (80031dc <BSP_LCD_DrawHLine+0xb0>)
|
|
8003184: 681b ldr r3, [r3, #0]
|
|
8003186: 4a16 ldr r2, [pc, #88] ; (80031e0 <BSP_LCD_DrawHLine+0xb4>)
|
|
8003188: 2134 movs r1, #52 ; 0x34
|
|
800318a: fb01 f303 mul.w r3, r1, r3
|
|
800318e: 4413 add r3, r2
|
|
8003190: 335c adds r3, #92 ; 0x5c
|
|
8003192: 681c ldr r4, [r3, #0]
|
|
8003194: f7ff fd88 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8003198: 4602 mov r2, r0
|
|
800319a: 88bb ldrh r3, [r7, #4]
|
|
800319c: fb03 f202 mul.w r2, r3, r2
|
|
80031a0: 88fb ldrh r3, [r7, #6]
|
|
80031a2: 4413 add r3, r2
|
|
80031a4: 009b lsls r3, r3, #2
|
|
80031a6: 4423 add r3, r4
|
|
80031a8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Write line */
|
|
LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
|
|
80031aa: 4b0c ldr r3, [pc, #48] ; (80031dc <BSP_LCD_DrawHLine+0xb0>)
|
|
80031ac: 6818 ldr r0, [r3, #0]
|
|
80031ae: 68fc ldr r4, [r7, #12]
|
|
80031b0: 887d ldrh r5, [r7, #2]
|
|
80031b2: 4b0a ldr r3, [pc, #40] ; (80031dc <BSP_LCD_DrawHLine+0xb0>)
|
|
80031b4: 681a ldr r2, [r3, #0]
|
|
80031b6: 490b ldr r1, [pc, #44] ; (80031e4 <BSP_LCD_DrawHLine+0xb8>)
|
|
80031b8: 4613 mov r3, r2
|
|
80031ba: 005b lsls r3, r3, #1
|
|
80031bc: 4413 add r3, r2
|
|
80031be: 009b lsls r3, r3, #2
|
|
80031c0: 440b add r3, r1
|
|
80031c2: 681b ldr r3, [r3, #0]
|
|
80031c4: 9301 str r3, [sp, #4]
|
|
80031c6: 2300 movs r3, #0
|
|
80031c8: 9300 str r3, [sp, #0]
|
|
80031ca: 2301 movs r3, #1
|
|
80031cc: 462a mov r2, r5
|
|
80031ce: 4621 mov r1, r4
|
|
80031d0: f000 fcd8 bl 8003b84 <LL_FillBuffer>
|
|
}
|
|
80031d4: bf00 nop
|
|
80031d6: 3710 adds r7, #16
|
|
80031d8: 46bd mov sp, r7
|
|
80031da: bdb0 pop {r4, r5, r7, pc}
|
|
80031dc: 2000041c .word 0x2000041c
|
|
80031e0: 20008e70 .word 0x20008e70
|
|
80031e4: 20000420 .word 0x20000420
|
|
|
|
080031e8 <BSP_LCD_DrawCircle>:
|
|
* @param Ypos: Y position
|
|
* @param Radius: Circle radius
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
|
|
{
|
|
80031e8: b590 push {r4, r7, lr}
|
|
80031ea: b087 sub sp, #28
|
|
80031ec: af00 add r7, sp, #0
|
|
80031ee: 4603 mov r3, r0
|
|
80031f0: 80fb strh r3, [r7, #6]
|
|
80031f2: 460b mov r3, r1
|
|
80031f4: 80bb strh r3, [r7, #4]
|
|
80031f6: 4613 mov r3, r2
|
|
80031f8: 807b strh r3, [r7, #2]
|
|
int32_t decision; /* Decision Variable */
|
|
uint32_t current_x; /* Current X Value */
|
|
uint32_t current_y; /* Current Y Value */
|
|
|
|
decision = 3 - (Radius << 1);
|
|
80031fa: 887b ldrh r3, [r7, #2]
|
|
80031fc: 005b lsls r3, r3, #1
|
|
80031fe: f1c3 0303 rsb r3, r3, #3
|
|
8003202: 617b str r3, [r7, #20]
|
|
current_x = 0;
|
|
8003204: 2300 movs r3, #0
|
|
8003206: 613b str r3, [r7, #16]
|
|
current_y = Radius;
|
|
8003208: 887b ldrh r3, [r7, #2]
|
|
800320a: 60fb str r3, [r7, #12]
|
|
|
|
while (current_x <= current_y)
|
|
800320c: e0cf b.n 80033ae <BSP_LCD_DrawCircle+0x1c6>
|
|
{
|
|
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
|
|
800320e: 693b ldr r3, [r7, #16]
|
|
8003210: b29a uxth r2, r3
|
|
8003212: 88fb ldrh r3, [r7, #6]
|
|
8003214: 4413 add r3, r2
|
|
8003216: b298 uxth r0, r3
|
|
8003218: 68fb ldr r3, [r7, #12]
|
|
800321a: b29b uxth r3, r3
|
|
800321c: 88ba ldrh r2, [r7, #4]
|
|
800321e: 1ad3 subs r3, r2, r3
|
|
8003220: b29c uxth r4, r3
|
|
8003222: 4b67 ldr r3, [pc, #412] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
8003224: 681a ldr r2, [r3, #0]
|
|
8003226: 4967 ldr r1, [pc, #412] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
8003228: 4613 mov r3, r2
|
|
800322a: 005b lsls r3, r3, #1
|
|
800322c: 4413 add r3, r2
|
|
800322e: 009b lsls r3, r3, #2
|
|
8003230: 440b add r3, r1
|
|
8003232: 681b ldr r3, [r3, #0]
|
|
8003234: 461a mov r2, r3
|
|
8003236: 4621 mov r1, r4
|
|
8003238: f000 f8c6 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
|
|
800323c: 693b ldr r3, [r7, #16]
|
|
800323e: b29b uxth r3, r3
|
|
8003240: 88fa ldrh r2, [r7, #6]
|
|
8003242: 1ad3 subs r3, r2, r3
|
|
8003244: b298 uxth r0, r3
|
|
8003246: 68fb ldr r3, [r7, #12]
|
|
8003248: b29b uxth r3, r3
|
|
800324a: 88ba ldrh r2, [r7, #4]
|
|
800324c: 1ad3 subs r3, r2, r3
|
|
800324e: b29c uxth r4, r3
|
|
8003250: 4b5b ldr r3, [pc, #364] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
8003252: 681a ldr r2, [r3, #0]
|
|
8003254: 495b ldr r1, [pc, #364] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
8003256: 4613 mov r3, r2
|
|
8003258: 005b lsls r3, r3, #1
|
|
800325a: 4413 add r3, r2
|
|
800325c: 009b lsls r3, r3, #2
|
|
800325e: 440b add r3, r1
|
|
8003260: 681b ldr r3, [r3, #0]
|
|
8003262: 461a mov r2, r3
|
|
8003264: 4621 mov r1, r4
|
|
8003266: f000 f8af bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
|
|
800326a: 68fb ldr r3, [r7, #12]
|
|
800326c: b29a uxth r2, r3
|
|
800326e: 88fb ldrh r3, [r7, #6]
|
|
8003270: 4413 add r3, r2
|
|
8003272: b298 uxth r0, r3
|
|
8003274: 693b ldr r3, [r7, #16]
|
|
8003276: b29b uxth r3, r3
|
|
8003278: 88ba ldrh r2, [r7, #4]
|
|
800327a: 1ad3 subs r3, r2, r3
|
|
800327c: b29c uxth r4, r3
|
|
800327e: 4b50 ldr r3, [pc, #320] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
8003280: 681a ldr r2, [r3, #0]
|
|
8003282: 4950 ldr r1, [pc, #320] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
8003284: 4613 mov r3, r2
|
|
8003286: 005b lsls r3, r3, #1
|
|
8003288: 4413 add r3, r2
|
|
800328a: 009b lsls r3, r3, #2
|
|
800328c: 440b add r3, r1
|
|
800328e: 681b ldr r3, [r3, #0]
|
|
8003290: 461a mov r2, r3
|
|
8003292: 4621 mov r1, r4
|
|
8003294: f000 f898 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
|
|
8003298: 68fb ldr r3, [r7, #12]
|
|
800329a: b29b uxth r3, r3
|
|
800329c: 88fa ldrh r2, [r7, #6]
|
|
800329e: 1ad3 subs r3, r2, r3
|
|
80032a0: b298 uxth r0, r3
|
|
80032a2: 693b ldr r3, [r7, #16]
|
|
80032a4: b29b uxth r3, r3
|
|
80032a6: 88ba ldrh r2, [r7, #4]
|
|
80032a8: 1ad3 subs r3, r2, r3
|
|
80032aa: b29c uxth r4, r3
|
|
80032ac: 4b44 ldr r3, [pc, #272] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
80032ae: 681a ldr r2, [r3, #0]
|
|
80032b0: 4944 ldr r1, [pc, #272] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
80032b2: 4613 mov r3, r2
|
|
80032b4: 005b lsls r3, r3, #1
|
|
80032b6: 4413 add r3, r2
|
|
80032b8: 009b lsls r3, r3, #2
|
|
80032ba: 440b add r3, r1
|
|
80032bc: 681b ldr r3, [r3, #0]
|
|
80032be: 461a mov r2, r3
|
|
80032c0: 4621 mov r1, r4
|
|
80032c2: f000 f881 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
|
|
80032c6: 693b ldr r3, [r7, #16]
|
|
80032c8: b29a uxth r2, r3
|
|
80032ca: 88fb ldrh r3, [r7, #6]
|
|
80032cc: 4413 add r3, r2
|
|
80032ce: b298 uxth r0, r3
|
|
80032d0: 68fb ldr r3, [r7, #12]
|
|
80032d2: b29a uxth r2, r3
|
|
80032d4: 88bb ldrh r3, [r7, #4]
|
|
80032d6: 4413 add r3, r2
|
|
80032d8: b29c uxth r4, r3
|
|
80032da: 4b39 ldr r3, [pc, #228] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
80032dc: 681a ldr r2, [r3, #0]
|
|
80032de: 4939 ldr r1, [pc, #228] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
80032e0: 4613 mov r3, r2
|
|
80032e2: 005b lsls r3, r3, #1
|
|
80032e4: 4413 add r3, r2
|
|
80032e6: 009b lsls r3, r3, #2
|
|
80032e8: 440b add r3, r1
|
|
80032ea: 681b ldr r3, [r3, #0]
|
|
80032ec: 461a mov r2, r3
|
|
80032ee: 4621 mov r1, r4
|
|
80032f0: f000 f86a bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
|
|
80032f4: 693b ldr r3, [r7, #16]
|
|
80032f6: b29b uxth r3, r3
|
|
80032f8: 88fa ldrh r2, [r7, #6]
|
|
80032fa: 1ad3 subs r3, r2, r3
|
|
80032fc: b298 uxth r0, r3
|
|
80032fe: 68fb ldr r3, [r7, #12]
|
|
8003300: b29a uxth r2, r3
|
|
8003302: 88bb ldrh r3, [r7, #4]
|
|
8003304: 4413 add r3, r2
|
|
8003306: b29c uxth r4, r3
|
|
8003308: 4b2d ldr r3, [pc, #180] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
800330a: 681a ldr r2, [r3, #0]
|
|
800330c: 492d ldr r1, [pc, #180] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
800330e: 4613 mov r3, r2
|
|
8003310: 005b lsls r3, r3, #1
|
|
8003312: 4413 add r3, r2
|
|
8003314: 009b lsls r3, r3, #2
|
|
8003316: 440b add r3, r1
|
|
8003318: 681b ldr r3, [r3, #0]
|
|
800331a: 461a mov r2, r3
|
|
800331c: 4621 mov r1, r4
|
|
800331e: f000 f853 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
|
|
8003322: 68fb ldr r3, [r7, #12]
|
|
8003324: b29a uxth r2, r3
|
|
8003326: 88fb ldrh r3, [r7, #6]
|
|
8003328: 4413 add r3, r2
|
|
800332a: b298 uxth r0, r3
|
|
800332c: 693b ldr r3, [r7, #16]
|
|
800332e: b29a uxth r2, r3
|
|
8003330: 88bb ldrh r3, [r7, #4]
|
|
8003332: 4413 add r3, r2
|
|
8003334: b29c uxth r4, r3
|
|
8003336: 4b22 ldr r3, [pc, #136] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
8003338: 681a ldr r2, [r3, #0]
|
|
800333a: 4922 ldr r1, [pc, #136] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
800333c: 4613 mov r3, r2
|
|
800333e: 005b lsls r3, r3, #1
|
|
8003340: 4413 add r3, r2
|
|
8003342: 009b lsls r3, r3, #2
|
|
8003344: 440b add r3, r1
|
|
8003346: 681b ldr r3, [r3, #0]
|
|
8003348: 461a mov r2, r3
|
|
800334a: 4621 mov r1, r4
|
|
800334c: f000 f83c bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
|
|
8003350: 68fb ldr r3, [r7, #12]
|
|
8003352: b29b uxth r3, r3
|
|
8003354: 88fa ldrh r2, [r7, #6]
|
|
8003356: 1ad3 subs r3, r2, r3
|
|
8003358: b298 uxth r0, r3
|
|
800335a: 693b ldr r3, [r7, #16]
|
|
800335c: b29a uxth r2, r3
|
|
800335e: 88bb ldrh r3, [r7, #4]
|
|
8003360: 4413 add r3, r2
|
|
8003362: b29c uxth r4, r3
|
|
8003364: 4b16 ldr r3, [pc, #88] ; (80033c0 <BSP_LCD_DrawCircle+0x1d8>)
|
|
8003366: 681a ldr r2, [r3, #0]
|
|
8003368: 4916 ldr r1, [pc, #88] ; (80033c4 <BSP_LCD_DrawCircle+0x1dc>)
|
|
800336a: 4613 mov r3, r2
|
|
800336c: 005b lsls r3, r3, #1
|
|
800336e: 4413 add r3, r2
|
|
8003370: 009b lsls r3, r3, #2
|
|
8003372: 440b add r3, r1
|
|
8003374: 681b ldr r3, [r3, #0]
|
|
8003376: 461a mov r2, r3
|
|
8003378: 4621 mov r1, r4
|
|
800337a: f000 f825 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
|
|
if (decision < 0)
|
|
800337e: 697b ldr r3, [r7, #20]
|
|
8003380: 2b00 cmp r3, #0
|
|
8003382: da06 bge.n 8003392 <BSP_LCD_DrawCircle+0x1aa>
|
|
{
|
|
decision += (current_x << 2) + 6;
|
|
8003384: 693b ldr r3, [r7, #16]
|
|
8003386: 009a lsls r2, r3, #2
|
|
8003388: 697b ldr r3, [r7, #20]
|
|
800338a: 4413 add r3, r2
|
|
800338c: 3306 adds r3, #6
|
|
800338e: 617b str r3, [r7, #20]
|
|
8003390: e00a b.n 80033a8 <BSP_LCD_DrawCircle+0x1c0>
|
|
}
|
|
else
|
|
{
|
|
decision += ((current_x - current_y) << 2) + 10;
|
|
8003392: 693a ldr r2, [r7, #16]
|
|
8003394: 68fb ldr r3, [r7, #12]
|
|
8003396: 1ad3 subs r3, r2, r3
|
|
8003398: 009a lsls r2, r3, #2
|
|
800339a: 697b ldr r3, [r7, #20]
|
|
800339c: 4413 add r3, r2
|
|
800339e: 330a adds r3, #10
|
|
80033a0: 617b str r3, [r7, #20]
|
|
current_y--;
|
|
80033a2: 68fb ldr r3, [r7, #12]
|
|
80033a4: 3b01 subs r3, #1
|
|
80033a6: 60fb str r3, [r7, #12]
|
|
}
|
|
current_x++;
|
|
80033a8: 693b ldr r3, [r7, #16]
|
|
80033aa: 3301 adds r3, #1
|
|
80033ac: 613b str r3, [r7, #16]
|
|
while (current_x <= current_y)
|
|
80033ae: 693a ldr r2, [r7, #16]
|
|
80033b0: 68fb ldr r3, [r7, #12]
|
|
80033b2: 429a cmp r2, r3
|
|
80033b4: f67f af2b bls.w 800320e <BSP_LCD_DrawCircle+0x26>
|
|
}
|
|
}
|
|
80033b8: bf00 nop
|
|
80033ba: 371c adds r7, #28
|
|
80033bc: 46bd mov sp, r7
|
|
80033be: bd90 pop {r4, r7, pc}
|
|
80033c0: 2000041c .word 0x2000041c
|
|
80033c4: 20000420 .word 0x20000420
|
|
|
|
080033c8 <BSP_LCD_DrawPixel>:
|
|
* @param Ypos: Y position
|
|
* @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
|
|
{
|
|
80033c8: b5b0 push {r4, r5, r7, lr}
|
|
80033ca: b082 sub sp, #8
|
|
80033cc: af00 add r7, sp, #0
|
|
80033ce: 4603 mov r3, r0
|
|
80033d0: 603a str r2, [r7, #0]
|
|
80033d2: 80fb strh r3, [r7, #6]
|
|
80033d4: 460b mov r3, r1
|
|
80033d6: 80bb strh r3, [r7, #4]
|
|
/* Write data value to all SDRAM memory */
|
|
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
|
|
80033d8: 4b1d ldr r3, [pc, #116] ; (8003450 <BSP_LCD_DrawPixel+0x88>)
|
|
80033da: 681b ldr r3, [r3, #0]
|
|
80033dc: 4a1d ldr r2, [pc, #116] ; (8003454 <BSP_LCD_DrawPixel+0x8c>)
|
|
80033de: 2134 movs r1, #52 ; 0x34
|
|
80033e0: fb01 f303 mul.w r3, r1, r3
|
|
80033e4: 4413 add r3, r2
|
|
80033e6: 3348 adds r3, #72 ; 0x48
|
|
80033e8: 681b ldr r3, [r3, #0]
|
|
80033ea: 2b02 cmp r3, #2
|
|
80033ec: d116 bne.n 800341c <BSP_LCD_DrawPixel+0x54>
|
|
{ /* RGB565 format */
|
|
*(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code;
|
|
80033ee: 4b18 ldr r3, [pc, #96] ; (8003450 <BSP_LCD_DrawPixel+0x88>)
|
|
80033f0: 681b ldr r3, [r3, #0]
|
|
80033f2: 4a18 ldr r2, [pc, #96] ; (8003454 <BSP_LCD_DrawPixel+0x8c>)
|
|
80033f4: 2134 movs r1, #52 ; 0x34
|
|
80033f6: fb01 f303 mul.w r3, r1, r3
|
|
80033fa: 4413 add r3, r2
|
|
80033fc: 335c adds r3, #92 ; 0x5c
|
|
80033fe: 681c ldr r4, [r3, #0]
|
|
8003400: 88bd ldrh r5, [r7, #4]
|
|
8003402: f7ff fc51 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8003406: 4603 mov r3, r0
|
|
8003408: fb03 f205 mul.w r2, r3, r5
|
|
800340c: 88fb ldrh r3, [r7, #6]
|
|
800340e: 4413 add r3, r2
|
|
8003410: 005b lsls r3, r3, #1
|
|
8003412: 4423 add r3, r4
|
|
8003414: 683a ldr r2, [r7, #0]
|
|
8003416: b292 uxth r2, r2
|
|
8003418: 801a strh r2, [r3, #0]
|
|
}
|
|
else
|
|
{ /* ARGB8888 format */
|
|
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
|
|
}
|
|
}
|
|
800341a: e015 b.n 8003448 <BSP_LCD_DrawPixel+0x80>
|
|
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
|
|
800341c: 4b0c ldr r3, [pc, #48] ; (8003450 <BSP_LCD_DrawPixel+0x88>)
|
|
800341e: 681b ldr r3, [r3, #0]
|
|
8003420: 4a0c ldr r2, [pc, #48] ; (8003454 <BSP_LCD_DrawPixel+0x8c>)
|
|
8003422: 2134 movs r1, #52 ; 0x34
|
|
8003424: fb01 f303 mul.w r3, r1, r3
|
|
8003428: 4413 add r3, r2
|
|
800342a: 335c adds r3, #92 ; 0x5c
|
|
800342c: 681c ldr r4, [r3, #0]
|
|
800342e: 88bd ldrh r5, [r7, #4]
|
|
8003430: f7ff fc3a bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8003434: 4603 mov r3, r0
|
|
8003436: fb03 f205 mul.w r2, r3, r5
|
|
800343a: 88fb ldrh r3, [r7, #6]
|
|
800343c: 4413 add r3, r2
|
|
800343e: 009b lsls r3, r3, #2
|
|
8003440: 4423 add r3, r4
|
|
8003442: 461a mov r2, r3
|
|
8003444: 683b ldr r3, [r7, #0]
|
|
8003446: 6013 str r3, [r2, #0]
|
|
}
|
|
8003448: bf00 nop
|
|
800344a: 3708 adds r7, #8
|
|
800344c: 46bd mov sp, r7
|
|
800344e: bdb0 pop {r4, r5, r7, pc}
|
|
8003450: 2000041c .word 0x2000041c
|
|
8003454: 20008e70 .word 0x20008e70
|
|
|
|
08003458 <BSP_LCD_DrawBitmap>:
|
|
* @param Ypos: Bmp Y position in the LCD
|
|
* @param pbmp: Pointer to Bmp picture address in the internal Flash
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DrawBitmap(uint32_t Xpos, uint32_t Ypos, uint8_t *pbmp)
|
|
{
|
|
8003458: b590 push {r4, r7, lr}
|
|
800345a: b08b sub sp, #44 ; 0x2c
|
|
800345c: af00 add r7, sp, #0
|
|
800345e: 60f8 str r0, [r7, #12]
|
|
8003460: 60b9 str r1, [r7, #8]
|
|
8003462: 607a str r2, [r7, #4]
|
|
uint32_t index = 0, width = 0, height = 0, bit_pixel = 0;
|
|
8003464: 2300 movs r3, #0
|
|
8003466: 627b str r3, [r7, #36] ; 0x24
|
|
8003468: 2300 movs r3, #0
|
|
800346a: 61bb str r3, [r7, #24]
|
|
800346c: 2300 movs r3, #0
|
|
800346e: 617b str r3, [r7, #20]
|
|
8003470: 2300 movs r3, #0
|
|
8003472: 613b str r3, [r7, #16]
|
|
uint32_t address;
|
|
uint32_t input_color_mode = 0;
|
|
8003474: 2300 movs r3, #0
|
|
8003476: 61fb str r3, [r7, #28]
|
|
|
|
/* Get bitmap data address offset */
|
|
index = pbmp[10] + (pbmp[11] << 8) + (pbmp[12] << 16) + (pbmp[13] << 24);
|
|
8003478: 687b ldr r3, [r7, #4]
|
|
800347a: 330a adds r3, #10
|
|
800347c: 781b ldrb r3, [r3, #0]
|
|
800347e: 461a mov r2, r3
|
|
8003480: 687b ldr r3, [r7, #4]
|
|
8003482: 330b adds r3, #11
|
|
8003484: 781b ldrb r3, [r3, #0]
|
|
8003486: 021b lsls r3, r3, #8
|
|
8003488: 441a add r2, r3
|
|
800348a: 687b ldr r3, [r7, #4]
|
|
800348c: 330c adds r3, #12
|
|
800348e: 781b ldrb r3, [r3, #0]
|
|
8003490: 041b lsls r3, r3, #16
|
|
8003492: 441a add r2, r3
|
|
8003494: 687b ldr r3, [r7, #4]
|
|
8003496: 330d adds r3, #13
|
|
8003498: 781b ldrb r3, [r3, #0]
|
|
800349a: 061b lsls r3, r3, #24
|
|
800349c: 4413 add r3, r2
|
|
800349e: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
/* Read bitmap width */
|
|
width = pbmp[18] + (pbmp[19] << 8) + (pbmp[20] << 16) + (pbmp[21] << 24);
|
|
80034a0: 687b ldr r3, [r7, #4]
|
|
80034a2: 3312 adds r3, #18
|
|
80034a4: 781b ldrb r3, [r3, #0]
|
|
80034a6: 461a mov r2, r3
|
|
80034a8: 687b ldr r3, [r7, #4]
|
|
80034aa: 3313 adds r3, #19
|
|
80034ac: 781b ldrb r3, [r3, #0]
|
|
80034ae: 021b lsls r3, r3, #8
|
|
80034b0: 441a add r2, r3
|
|
80034b2: 687b ldr r3, [r7, #4]
|
|
80034b4: 3314 adds r3, #20
|
|
80034b6: 781b ldrb r3, [r3, #0]
|
|
80034b8: 041b lsls r3, r3, #16
|
|
80034ba: 441a add r2, r3
|
|
80034bc: 687b ldr r3, [r7, #4]
|
|
80034be: 3315 adds r3, #21
|
|
80034c0: 781b ldrb r3, [r3, #0]
|
|
80034c2: 061b lsls r3, r3, #24
|
|
80034c4: 4413 add r3, r2
|
|
80034c6: 61bb str r3, [r7, #24]
|
|
|
|
/* Read bitmap height */
|
|
height = pbmp[22] + (pbmp[23] << 8) + (pbmp[24] << 16) + (pbmp[25] << 24);
|
|
80034c8: 687b ldr r3, [r7, #4]
|
|
80034ca: 3316 adds r3, #22
|
|
80034cc: 781b ldrb r3, [r3, #0]
|
|
80034ce: 461a mov r2, r3
|
|
80034d0: 687b ldr r3, [r7, #4]
|
|
80034d2: 3317 adds r3, #23
|
|
80034d4: 781b ldrb r3, [r3, #0]
|
|
80034d6: 021b lsls r3, r3, #8
|
|
80034d8: 441a add r2, r3
|
|
80034da: 687b ldr r3, [r7, #4]
|
|
80034dc: 3318 adds r3, #24
|
|
80034de: 781b ldrb r3, [r3, #0]
|
|
80034e0: 041b lsls r3, r3, #16
|
|
80034e2: 441a add r2, r3
|
|
80034e4: 687b ldr r3, [r7, #4]
|
|
80034e6: 3319 adds r3, #25
|
|
80034e8: 781b ldrb r3, [r3, #0]
|
|
80034ea: 061b lsls r3, r3, #24
|
|
80034ec: 4413 add r3, r2
|
|
80034ee: 617b str r3, [r7, #20]
|
|
|
|
/* Read bit/pixel */
|
|
bit_pixel = pbmp[28] + (pbmp[29] << 8);
|
|
80034f0: 687b ldr r3, [r7, #4]
|
|
80034f2: 331c adds r3, #28
|
|
80034f4: 781b ldrb r3, [r3, #0]
|
|
80034f6: 461a mov r2, r3
|
|
80034f8: 687b ldr r3, [r7, #4]
|
|
80034fa: 331d adds r3, #29
|
|
80034fc: 781b ldrb r3, [r3, #0]
|
|
80034fe: 021b lsls r3, r3, #8
|
|
8003500: 4413 add r3, r2
|
|
8003502: 613b str r3, [r7, #16]
|
|
|
|
/* Set the address */
|
|
address = hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (((BSP_LCD_GetXSize()*Ypos) + Xpos)*(4));
|
|
8003504: 4b2a ldr r3, [pc, #168] ; (80035b0 <BSP_LCD_DrawBitmap+0x158>)
|
|
8003506: 681b ldr r3, [r3, #0]
|
|
8003508: 4a2a ldr r2, [pc, #168] ; (80035b4 <BSP_LCD_DrawBitmap+0x15c>)
|
|
800350a: 2134 movs r1, #52 ; 0x34
|
|
800350c: fb01 f303 mul.w r3, r1, r3
|
|
8003510: 4413 add r3, r2
|
|
8003512: 335c adds r3, #92 ; 0x5c
|
|
8003514: 681c ldr r4, [r3, #0]
|
|
8003516: f7ff fbc7 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
800351a: 4602 mov r2, r0
|
|
800351c: 68bb ldr r3, [r7, #8]
|
|
800351e: fb03 f202 mul.w r2, r3, r2
|
|
8003522: 68fb ldr r3, [r7, #12]
|
|
8003524: 4413 add r3, r2
|
|
8003526: 009b lsls r3, r3, #2
|
|
8003528: 4423 add r3, r4
|
|
800352a: 623b str r3, [r7, #32]
|
|
|
|
/* Get the layer pixel format */
|
|
if ((bit_pixel/8) == 4)
|
|
800352c: 693b ldr r3, [r7, #16]
|
|
800352e: 3b20 subs r3, #32
|
|
8003530: 2b07 cmp r3, #7
|
|
8003532: d802 bhi.n 800353a <BSP_LCD_DrawBitmap+0xe2>
|
|
{
|
|
input_color_mode = CM_ARGB8888;
|
|
8003534: 2300 movs r3, #0
|
|
8003536: 61fb str r3, [r7, #28]
|
|
8003538: e008 b.n 800354c <BSP_LCD_DrawBitmap+0xf4>
|
|
}
|
|
else if ((bit_pixel/8) == 2)
|
|
800353a: 693b ldr r3, [r7, #16]
|
|
800353c: 3b10 subs r3, #16
|
|
800353e: 2b07 cmp r3, #7
|
|
8003540: d802 bhi.n 8003548 <BSP_LCD_DrawBitmap+0xf0>
|
|
{
|
|
input_color_mode = CM_RGB565;
|
|
8003542: 2302 movs r3, #2
|
|
8003544: 61fb str r3, [r7, #28]
|
|
8003546: e001 b.n 800354c <BSP_LCD_DrawBitmap+0xf4>
|
|
}
|
|
else
|
|
{
|
|
input_color_mode = CM_RGB888;
|
|
8003548: 2301 movs r3, #1
|
|
800354a: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Bypass the bitmap header */
|
|
pbmp += (index + (width * (height - 1) * (bit_pixel/8)));
|
|
800354c: 697b ldr r3, [r7, #20]
|
|
800354e: 3b01 subs r3, #1
|
|
8003550: 69ba ldr r2, [r7, #24]
|
|
8003552: fb02 f303 mul.w r3, r2, r3
|
|
8003556: 693a ldr r2, [r7, #16]
|
|
8003558: 08d2 lsrs r2, r2, #3
|
|
800355a: fb02 f203 mul.w r2, r2, r3
|
|
800355e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8003560: 4413 add r3, r2
|
|
8003562: 687a ldr r2, [r7, #4]
|
|
8003564: 4413 add r3, r2
|
|
8003566: 607b str r3, [r7, #4]
|
|
|
|
/* Convert picture to ARGB8888 pixel format */
|
|
for(index=0; index < height; index++)
|
|
8003568: 2300 movs r3, #0
|
|
800356a: 627b str r3, [r7, #36] ; 0x24
|
|
800356c: e018 b.n 80035a0 <BSP_LCD_DrawBitmap+0x148>
|
|
{
|
|
/* Pixel format conversion */
|
|
LL_ConvertLineToARGB8888((uint32_t *)pbmp, (uint32_t *)address, width, input_color_mode);
|
|
800356e: 6a39 ldr r1, [r7, #32]
|
|
8003570: 69fb ldr r3, [r7, #28]
|
|
8003572: 69ba ldr r2, [r7, #24]
|
|
8003574: 6878 ldr r0, [r7, #4]
|
|
8003576: f000 fb51 bl 8003c1c <LL_ConvertLineToARGB8888>
|
|
|
|
/* Increment the source and destination buffers */
|
|
address+= (BSP_LCD_GetXSize()*4);
|
|
800357a: f7ff fb95 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
800357e: 4603 mov r3, r0
|
|
8003580: 009b lsls r3, r3, #2
|
|
8003582: 6a3a ldr r2, [r7, #32]
|
|
8003584: 4413 add r3, r2
|
|
8003586: 623b str r3, [r7, #32]
|
|
pbmp -= width*(bit_pixel/8);
|
|
8003588: 693b ldr r3, [r7, #16]
|
|
800358a: 08db lsrs r3, r3, #3
|
|
800358c: 69ba ldr r2, [r7, #24]
|
|
800358e: fb02 f303 mul.w r3, r2, r3
|
|
8003592: 425b negs r3, r3
|
|
8003594: 687a ldr r2, [r7, #4]
|
|
8003596: 4413 add r3, r2
|
|
8003598: 607b str r3, [r7, #4]
|
|
for(index=0; index < height; index++)
|
|
800359a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800359c: 3301 adds r3, #1
|
|
800359e: 627b str r3, [r7, #36] ; 0x24
|
|
80035a0: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
80035a2: 697b ldr r3, [r7, #20]
|
|
80035a4: 429a cmp r2, r3
|
|
80035a6: d3e2 bcc.n 800356e <BSP_LCD_DrawBitmap+0x116>
|
|
}
|
|
}
|
|
80035a8: bf00 nop
|
|
80035aa: 372c adds r7, #44 ; 0x2c
|
|
80035ac: 46bd mov sp, r7
|
|
80035ae: bd90 pop {r4, r7, pc}
|
|
80035b0: 2000041c .word 0x2000041c
|
|
80035b4: 20008e70 .word 0x20008e70
|
|
|
|
080035b8 <BSP_LCD_FillRect>:
|
|
* @param Width: Rectangle width
|
|
* @param Height: Rectangle height
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_FillRect(uint16_t Xpos, uint16_t Ypos, uint16_t Width, uint16_t Height)
|
|
{
|
|
80035b8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
80035bc: b086 sub sp, #24
|
|
80035be: af02 add r7, sp, #8
|
|
80035c0: 4604 mov r4, r0
|
|
80035c2: 4608 mov r0, r1
|
|
80035c4: 4611 mov r1, r2
|
|
80035c6: 461a mov r2, r3
|
|
80035c8: 4623 mov r3, r4
|
|
80035ca: 80fb strh r3, [r7, #6]
|
|
80035cc: 4603 mov r3, r0
|
|
80035ce: 80bb strh r3, [r7, #4]
|
|
80035d0: 460b mov r3, r1
|
|
80035d2: 807b strh r3, [r7, #2]
|
|
80035d4: 4613 mov r3, r2
|
|
80035d6: 803b strh r3, [r7, #0]
|
|
uint32_t x_address = 0;
|
|
80035d8: 2300 movs r3, #0
|
|
80035da: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the text color */
|
|
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
|
|
80035dc: 4b30 ldr r3, [pc, #192] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
80035de: 681a ldr r2, [r3, #0]
|
|
80035e0: 4930 ldr r1, [pc, #192] ; (80036a4 <BSP_LCD_FillRect+0xec>)
|
|
80035e2: 4613 mov r3, r2
|
|
80035e4: 005b lsls r3, r3, #1
|
|
80035e6: 4413 add r3, r2
|
|
80035e8: 009b lsls r3, r3, #2
|
|
80035ea: 440b add r3, r1
|
|
80035ec: 681b ldr r3, [r3, #0]
|
|
80035ee: 4618 mov r0, r3
|
|
80035f0: f7ff fbf2 bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
|
|
/* Get the rectangle start address */
|
|
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
|
|
80035f4: 4b2a ldr r3, [pc, #168] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
80035f6: 681b ldr r3, [r3, #0]
|
|
80035f8: 4a2b ldr r2, [pc, #172] ; (80036a8 <BSP_LCD_FillRect+0xf0>)
|
|
80035fa: 2134 movs r1, #52 ; 0x34
|
|
80035fc: fb01 f303 mul.w r3, r1, r3
|
|
8003600: 4413 add r3, r2
|
|
8003602: 3348 adds r3, #72 ; 0x48
|
|
8003604: 681b ldr r3, [r3, #0]
|
|
8003606: 2b02 cmp r3, #2
|
|
8003608: d114 bne.n 8003634 <BSP_LCD_FillRect+0x7c>
|
|
{ /* RGB565 format */
|
|
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
|
|
800360a: 4b25 ldr r3, [pc, #148] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
800360c: 681b ldr r3, [r3, #0]
|
|
800360e: 4a26 ldr r2, [pc, #152] ; (80036a8 <BSP_LCD_FillRect+0xf0>)
|
|
8003610: 2134 movs r1, #52 ; 0x34
|
|
8003612: fb01 f303 mul.w r3, r1, r3
|
|
8003616: 4413 add r3, r2
|
|
8003618: 335c adds r3, #92 ; 0x5c
|
|
800361a: 681c ldr r4, [r3, #0]
|
|
800361c: f7ff fb44 bl 8002ca8 <BSP_LCD_GetXSize>
|
|
8003620: 4602 mov r2, r0
|
|
8003622: 88bb ldrh r3, [r7, #4]
|
|
8003624: fb03 f202 mul.w r2, r3, r2
|
|
8003628: 88fb ldrh r3, [r7, #6]
|
|
800362a: 4413 add r3, r2
|
|
800362c: 005b lsls r3, r3, #1
|
|
800362e: 4423 add r3, r4
|
|
8003630: 60fb str r3, [r7, #12]
|
|
8003632: e013 b.n 800365c <BSP_LCD_FillRect+0xa4>
|
|
}
|
|
else
|
|
{ /* ARGB8888 format */
|
|
x_address = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
|
|
8003634: 4b1a ldr r3, [pc, #104] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
8003636: 681b ldr r3, [r3, #0]
|
|
8003638: 4a1b ldr r2, [pc, #108] ; (80036a8 <BSP_LCD_FillRect+0xf0>)
|
|
800363a: 2134 movs r1, #52 ; 0x34
|
|
800363c: fb01 f303 mul.w r3, r1, r3
|
|
8003640: 4413 add r3, r2
|
|
8003642: 335c adds r3, #92 ; 0x5c
|
|
8003644: 681c ldr r4, [r3, #0]
|
|
8003646: f7ff fb2f bl 8002ca8 <BSP_LCD_GetXSize>
|
|
800364a: 4602 mov r2, r0
|
|
800364c: 88bb ldrh r3, [r7, #4]
|
|
800364e: fb03 f202 mul.w r2, r3, r2
|
|
8003652: 88fb ldrh r3, [r7, #6]
|
|
8003654: 4413 add r3, r2
|
|
8003656: 009b lsls r3, r3, #2
|
|
8003658: 4423 add r3, r4
|
|
800365a: 60fb str r3, [r7, #12]
|
|
}
|
|
/* Fill the rectangle */
|
|
LL_FillBuffer(ActiveLayer, (uint32_t *)x_address, Width, Height, (BSP_LCD_GetXSize() - Width), DrawProp[ActiveLayer].TextColor);
|
|
800365c: 4b10 ldr r3, [pc, #64] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
800365e: 681c ldr r4, [r3, #0]
|
|
8003660: 68fd ldr r5, [r7, #12]
|
|
8003662: 887e ldrh r6, [r7, #2]
|
|
8003664: f8b7 8000 ldrh.w r8, [r7]
|
|
8003668: f7ff fb1e bl 8002ca8 <BSP_LCD_GetXSize>
|
|
800366c: 4602 mov r2, r0
|
|
800366e: 887b ldrh r3, [r7, #2]
|
|
8003670: 1ad1 subs r1, r2, r3
|
|
8003672: 4b0b ldr r3, [pc, #44] ; (80036a0 <BSP_LCD_FillRect+0xe8>)
|
|
8003674: 681a ldr r2, [r3, #0]
|
|
8003676: 480b ldr r0, [pc, #44] ; (80036a4 <BSP_LCD_FillRect+0xec>)
|
|
8003678: 4613 mov r3, r2
|
|
800367a: 005b lsls r3, r3, #1
|
|
800367c: 4413 add r3, r2
|
|
800367e: 009b lsls r3, r3, #2
|
|
8003680: 4403 add r3, r0
|
|
8003682: 681b ldr r3, [r3, #0]
|
|
8003684: 9301 str r3, [sp, #4]
|
|
8003686: 9100 str r1, [sp, #0]
|
|
8003688: 4643 mov r3, r8
|
|
800368a: 4632 mov r2, r6
|
|
800368c: 4629 mov r1, r5
|
|
800368e: 4620 mov r0, r4
|
|
8003690: f000 fa78 bl 8003b84 <LL_FillBuffer>
|
|
}
|
|
8003694: bf00 nop
|
|
8003696: 3710 adds r7, #16
|
|
8003698: 46bd mov sp, r7
|
|
800369a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
800369e: bf00 nop
|
|
80036a0: 2000041c .word 0x2000041c
|
|
80036a4: 20000420 .word 0x20000420
|
|
80036a8: 20008e70 .word 0x20008e70
|
|
|
|
080036ac <BSP_LCD_FillCircle>:
|
|
* @param Ypos: Y position
|
|
* @param Radius: Circle radius
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
|
|
{
|
|
80036ac: b580 push {r7, lr}
|
|
80036ae: b086 sub sp, #24
|
|
80036b0: af00 add r7, sp, #0
|
|
80036b2: 4603 mov r3, r0
|
|
80036b4: 80fb strh r3, [r7, #6]
|
|
80036b6: 460b mov r3, r1
|
|
80036b8: 80bb strh r3, [r7, #4]
|
|
80036ba: 4613 mov r3, r2
|
|
80036bc: 807b strh r3, [r7, #2]
|
|
int32_t decision; /* Decision Variable */
|
|
uint32_t current_x; /* Current X Value */
|
|
uint32_t current_y; /* Current Y Value */
|
|
|
|
decision = 3 - (Radius << 1);
|
|
80036be: 887b ldrh r3, [r7, #2]
|
|
80036c0: 005b lsls r3, r3, #1
|
|
80036c2: f1c3 0303 rsb r3, r3, #3
|
|
80036c6: 617b str r3, [r7, #20]
|
|
|
|
current_x = 0;
|
|
80036c8: 2300 movs r3, #0
|
|
80036ca: 613b str r3, [r7, #16]
|
|
current_y = Radius;
|
|
80036cc: 887b ldrh r3, [r7, #2]
|
|
80036ce: 60fb str r3, [r7, #12]
|
|
|
|
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
|
|
80036d0: 4b44 ldr r3, [pc, #272] ; (80037e4 <BSP_LCD_FillCircle+0x138>)
|
|
80036d2: 681a ldr r2, [r3, #0]
|
|
80036d4: 4944 ldr r1, [pc, #272] ; (80037e8 <BSP_LCD_FillCircle+0x13c>)
|
|
80036d6: 4613 mov r3, r2
|
|
80036d8: 005b lsls r3, r3, #1
|
|
80036da: 4413 add r3, r2
|
|
80036dc: 009b lsls r3, r3, #2
|
|
80036de: 440b add r3, r1
|
|
80036e0: 681b ldr r3, [r3, #0]
|
|
80036e2: 4618 mov r0, r3
|
|
80036e4: f7ff fb78 bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
|
|
while (current_x <= current_y)
|
|
80036e8: e061 b.n 80037ae <BSP_LCD_FillCircle+0x102>
|
|
{
|
|
if(current_y > 0)
|
|
80036ea: 68fb ldr r3, [r7, #12]
|
|
80036ec: 2b00 cmp r3, #0
|
|
80036ee: d021 beq.n 8003734 <BSP_LCD_FillCircle+0x88>
|
|
{
|
|
BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);
|
|
80036f0: 68fb ldr r3, [r7, #12]
|
|
80036f2: b29b uxth r3, r3
|
|
80036f4: 88fa ldrh r2, [r7, #6]
|
|
80036f6: 1ad3 subs r3, r2, r3
|
|
80036f8: b298 uxth r0, r3
|
|
80036fa: 693b ldr r3, [r7, #16]
|
|
80036fc: b29a uxth r2, r3
|
|
80036fe: 88bb ldrh r3, [r7, #4]
|
|
8003700: 4413 add r3, r2
|
|
8003702: b299 uxth r1, r3
|
|
8003704: 68fb ldr r3, [r7, #12]
|
|
8003706: b29b uxth r3, r3
|
|
8003708: 005b lsls r3, r3, #1
|
|
800370a: b29b uxth r3, r3
|
|
800370c: 461a mov r2, r3
|
|
800370e: f7ff fd0d bl 800312c <BSP_LCD_DrawHLine>
|
|
BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);
|
|
8003712: 68fb ldr r3, [r7, #12]
|
|
8003714: b29b uxth r3, r3
|
|
8003716: 88fa ldrh r2, [r7, #6]
|
|
8003718: 1ad3 subs r3, r2, r3
|
|
800371a: b298 uxth r0, r3
|
|
800371c: 693b ldr r3, [r7, #16]
|
|
800371e: b29b uxth r3, r3
|
|
8003720: 88ba ldrh r2, [r7, #4]
|
|
8003722: 1ad3 subs r3, r2, r3
|
|
8003724: b299 uxth r1, r3
|
|
8003726: 68fb ldr r3, [r7, #12]
|
|
8003728: b29b uxth r3, r3
|
|
800372a: 005b lsls r3, r3, #1
|
|
800372c: b29b uxth r3, r3
|
|
800372e: 461a mov r2, r3
|
|
8003730: f7ff fcfc bl 800312c <BSP_LCD_DrawHLine>
|
|
}
|
|
|
|
if(current_x > 0)
|
|
8003734: 693b ldr r3, [r7, #16]
|
|
8003736: 2b00 cmp r3, #0
|
|
8003738: d021 beq.n 800377e <BSP_LCD_FillCircle+0xd2>
|
|
{
|
|
BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);
|
|
800373a: 693b ldr r3, [r7, #16]
|
|
800373c: b29b uxth r3, r3
|
|
800373e: 88fa ldrh r2, [r7, #6]
|
|
8003740: 1ad3 subs r3, r2, r3
|
|
8003742: b298 uxth r0, r3
|
|
8003744: 68fb ldr r3, [r7, #12]
|
|
8003746: b29b uxth r3, r3
|
|
8003748: 88ba ldrh r2, [r7, #4]
|
|
800374a: 1ad3 subs r3, r2, r3
|
|
800374c: b299 uxth r1, r3
|
|
800374e: 693b ldr r3, [r7, #16]
|
|
8003750: b29b uxth r3, r3
|
|
8003752: 005b lsls r3, r3, #1
|
|
8003754: b29b uxth r3, r3
|
|
8003756: 461a mov r2, r3
|
|
8003758: f7ff fce8 bl 800312c <BSP_LCD_DrawHLine>
|
|
BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);
|
|
800375c: 693b ldr r3, [r7, #16]
|
|
800375e: b29b uxth r3, r3
|
|
8003760: 88fa ldrh r2, [r7, #6]
|
|
8003762: 1ad3 subs r3, r2, r3
|
|
8003764: b298 uxth r0, r3
|
|
8003766: 68fb ldr r3, [r7, #12]
|
|
8003768: b29a uxth r2, r3
|
|
800376a: 88bb ldrh r3, [r7, #4]
|
|
800376c: 4413 add r3, r2
|
|
800376e: b299 uxth r1, r3
|
|
8003770: 693b ldr r3, [r7, #16]
|
|
8003772: b29b uxth r3, r3
|
|
8003774: 005b lsls r3, r3, #1
|
|
8003776: b29b uxth r3, r3
|
|
8003778: 461a mov r2, r3
|
|
800377a: f7ff fcd7 bl 800312c <BSP_LCD_DrawHLine>
|
|
}
|
|
if (decision < 0)
|
|
800377e: 697b ldr r3, [r7, #20]
|
|
8003780: 2b00 cmp r3, #0
|
|
8003782: da06 bge.n 8003792 <BSP_LCD_FillCircle+0xe6>
|
|
{
|
|
decision += (current_x << 2) + 6;
|
|
8003784: 693b ldr r3, [r7, #16]
|
|
8003786: 009a lsls r2, r3, #2
|
|
8003788: 697b ldr r3, [r7, #20]
|
|
800378a: 4413 add r3, r2
|
|
800378c: 3306 adds r3, #6
|
|
800378e: 617b str r3, [r7, #20]
|
|
8003790: e00a b.n 80037a8 <BSP_LCD_FillCircle+0xfc>
|
|
}
|
|
else
|
|
{
|
|
decision += ((current_x - current_y) << 2) + 10;
|
|
8003792: 693a ldr r2, [r7, #16]
|
|
8003794: 68fb ldr r3, [r7, #12]
|
|
8003796: 1ad3 subs r3, r2, r3
|
|
8003798: 009a lsls r2, r3, #2
|
|
800379a: 697b ldr r3, [r7, #20]
|
|
800379c: 4413 add r3, r2
|
|
800379e: 330a adds r3, #10
|
|
80037a0: 617b str r3, [r7, #20]
|
|
current_y--;
|
|
80037a2: 68fb ldr r3, [r7, #12]
|
|
80037a4: 3b01 subs r3, #1
|
|
80037a6: 60fb str r3, [r7, #12]
|
|
}
|
|
current_x++;
|
|
80037a8: 693b ldr r3, [r7, #16]
|
|
80037aa: 3301 adds r3, #1
|
|
80037ac: 613b str r3, [r7, #16]
|
|
while (current_x <= current_y)
|
|
80037ae: 693a ldr r2, [r7, #16]
|
|
80037b0: 68fb ldr r3, [r7, #12]
|
|
80037b2: 429a cmp r2, r3
|
|
80037b4: d999 bls.n 80036ea <BSP_LCD_FillCircle+0x3e>
|
|
}
|
|
|
|
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
|
|
80037b6: 4b0b ldr r3, [pc, #44] ; (80037e4 <BSP_LCD_FillCircle+0x138>)
|
|
80037b8: 681a ldr r2, [r3, #0]
|
|
80037ba: 490b ldr r1, [pc, #44] ; (80037e8 <BSP_LCD_FillCircle+0x13c>)
|
|
80037bc: 4613 mov r3, r2
|
|
80037be: 005b lsls r3, r3, #1
|
|
80037c0: 4413 add r3, r2
|
|
80037c2: 009b lsls r3, r3, #2
|
|
80037c4: 440b add r3, r1
|
|
80037c6: 681b ldr r3, [r3, #0]
|
|
80037c8: 4618 mov r0, r3
|
|
80037ca: f7ff fb05 bl 8002dd8 <BSP_LCD_SetTextColor>
|
|
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
|
|
80037ce: 887a ldrh r2, [r7, #2]
|
|
80037d0: 88b9 ldrh r1, [r7, #4]
|
|
80037d2: 88fb ldrh r3, [r7, #6]
|
|
80037d4: 4618 mov r0, r3
|
|
80037d6: f7ff fd07 bl 80031e8 <BSP_LCD_DrawCircle>
|
|
}
|
|
80037da: bf00 nop
|
|
80037dc: 3718 adds r7, #24
|
|
80037de: 46bd mov sp, r7
|
|
80037e0: bd80 pop {r7, pc}
|
|
80037e2: bf00 nop
|
|
80037e4: 2000041c .word 0x2000041c
|
|
80037e8: 20000420 .word 0x20000420
|
|
|
|
080037ec <BSP_LCD_DisplayOn>:
|
|
/**
|
|
* @brief Enables the display.
|
|
* @retval None
|
|
*/
|
|
void BSP_LCD_DisplayOn(void)
|
|
{
|
|
80037ec: b580 push {r7, lr}
|
|
80037ee: af00 add r7, sp, #0
|
|
/* Display On */
|
|
__HAL_LTDC_ENABLE(&hLtdcHandler);
|
|
80037f0: 4b0a ldr r3, [pc, #40] ; (800381c <BSP_LCD_DisplayOn+0x30>)
|
|
80037f2: 681b ldr r3, [r3, #0]
|
|
80037f4: 699a ldr r2, [r3, #24]
|
|
80037f6: 4b09 ldr r3, [pc, #36] ; (800381c <BSP_LCD_DisplayOn+0x30>)
|
|
80037f8: 681b ldr r3, [r3, #0]
|
|
80037fa: f042 0201 orr.w r2, r2, #1
|
|
80037fe: 619a str r2, [r3, #24]
|
|
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */
|
|
8003800: 2201 movs r2, #1
|
|
8003802: f44f 5180 mov.w r1, #4096 ; 0x1000
|
|
8003806: 4806 ldr r0, [pc, #24] ; (8003820 <BSP_LCD_DisplayOn+0x34>)
|
|
8003808: f004 fca6 bl 8008158 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */
|
|
800380c: 2201 movs r2, #1
|
|
800380e: 2108 movs r1, #8
|
|
8003810: 4804 ldr r0, [pc, #16] ; (8003824 <BSP_LCD_DisplayOn+0x38>)
|
|
8003812: f004 fca1 bl 8008158 <HAL_GPIO_WritePin>
|
|
}
|
|
8003816: bf00 nop
|
|
8003818: bd80 pop {r7, pc}
|
|
800381a: bf00 nop
|
|
800381c: 20008e70 .word 0x20008e70
|
|
8003820: 40022000 .word 0x40022000
|
|
8003824: 40022800 .word 0x40022800
|
|
|
|
08003828 <BSP_LCD_MspInit>:
|
|
* @param hltdc: LTDC handle
|
|
* @param Params
|
|
* @retval None
|
|
*/
|
|
__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
|
|
{
|
|
8003828: b580 push {r7, lr}
|
|
800382a: b090 sub sp, #64 ; 0x40
|
|
800382c: af00 add r7, sp, #0
|
|
800382e: 6078 str r0, [r7, #4]
|
|
8003830: 6039 str r1, [r7, #0]
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/* Enable the LTDC and DMA2D clocks */
|
|
__HAL_RCC_LTDC_CLK_ENABLE();
|
|
8003832: 4b64 ldr r3, [pc, #400] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003834: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8003836: 4a63 ldr r2, [pc, #396] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003838: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
800383c: 6453 str r3, [r2, #68] ; 0x44
|
|
800383e: 4b61 ldr r3, [pc, #388] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003840: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8003842: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
8003846: 62bb str r3, [r7, #40] ; 0x28
|
|
8003848: 6abb ldr r3, [r7, #40] ; 0x28
|
|
__HAL_RCC_DMA2D_CLK_ENABLE();
|
|
800384a: 4b5e ldr r3, [pc, #376] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
800384c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800384e: 4a5d ldr r2, [pc, #372] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003850: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
8003854: 6313 str r3, [r2, #48] ; 0x30
|
|
8003856: 4b5b ldr r3, [pc, #364] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003858: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800385a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
800385e: 627b str r3, [r7, #36] ; 0x24
|
|
8003860: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
|
/* Enable GPIOs clock */
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8003862: 4b58 ldr r3, [pc, #352] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003864: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003866: 4a57 ldr r2, [pc, #348] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003868: f043 0310 orr.w r3, r3, #16
|
|
800386c: 6313 str r3, [r2, #48] ; 0x30
|
|
800386e: 4b55 ldr r3, [pc, #340] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003870: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003872: f003 0310 and.w r3, r3, #16
|
|
8003876: 623b str r3, [r7, #32]
|
|
8003878: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
800387a: 4b52 ldr r3, [pc, #328] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
800387c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800387e: 4a51 ldr r2, [pc, #324] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003880: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8003884: 6313 str r3, [r2, #48] ; 0x30
|
|
8003886: 4b4f ldr r3, [pc, #316] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003888: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800388a: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800388e: 61fb str r3, [r7, #28]
|
|
8003890: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
8003892: 4b4c ldr r3, [pc, #304] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003894: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003896: 4a4b ldr r2, [pc, #300] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003898: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
800389c: 6313 str r3, [r2, #48] ; 0x30
|
|
800389e: 4b49 ldr r3, [pc, #292] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038a0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038a2: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80038a6: 61bb str r3, [r7, #24]
|
|
80038a8: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
|
80038aa: 4b46 ldr r3, [pc, #280] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038ac: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038ae: 4a45 ldr r2, [pc, #276] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038b0: f443 7300 orr.w r3, r3, #512 ; 0x200
|
|
80038b4: 6313 str r3, [r2, #48] ; 0x30
|
|
80038b6: 4b43 ldr r3, [pc, #268] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038b8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038ba: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
80038be: 617b str r3, [r7, #20]
|
|
80038c0: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOK_CLK_ENABLE();
|
|
80038c2: 4b40 ldr r3, [pc, #256] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038c4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038c6: 4a3f ldr r2, [pc, #252] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038c8: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
80038cc: 6313 str r3, [r2, #48] ; 0x30
|
|
80038ce: 4b3d ldr r3, [pc, #244] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038d0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038d2: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80038d6: 613b str r3, [r7, #16]
|
|
80038d8: 693b ldr r3, [r7, #16]
|
|
LCD_DISP_GPIO_CLK_ENABLE();
|
|
80038da: 4b3a ldr r3, [pc, #232] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038dc: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038de: 4a39 ldr r2, [pc, #228] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038e0: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
80038e4: 6313 str r3, [r2, #48] ; 0x30
|
|
80038e6: 4b37 ldr r3, [pc, #220] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038e8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038ea: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
80038ee: 60fb str r3, [r7, #12]
|
|
80038f0: 68fb ldr r3, [r7, #12]
|
|
LCD_BL_CTRL_GPIO_CLK_ENABLE();
|
|
80038f2: 4b34 ldr r3, [pc, #208] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038f4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80038f6: 4a33 ldr r2, [pc, #204] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
80038f8: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
80038fc: 6313 str r3, [r2, #48] ; 0x30
|
|
80038fe: 4b31 ldr r3, [pc, #196] ; (80039c4 <BSP_LCD_MspInit+0x19c>)
|
|
8003900: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003902: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
8003906: 60bb str r3, [r7, #8]
|
|
8003908: 68bb ldr r3, [r7, #8]
|
|
|
|
/*** LTDC Pins configuration ***/
|
|
/* GPIOE configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_4;
|
|
800390a: 2310 movs r3, #16
|
|
800390c: 62fb str r3, [r7, #44] ; 0x2c
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
800390e: 2302 movs r3, #2
|
|
8003910: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Pull = GPIO_NOPULL;
|
|
8003912: 2300 movs r3, #0
|
|
8003914: 637b str r3, [r7, #52] ; 0x34
|
|
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
|
8003916: 2302 movs r3, #2
|
|
8003918: 63bb str r3, [r7, #56] ; 0x38
|
|
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
|
800391a: 230e movs r3, #14
|
|
800391c: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
|
800391e: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003922: 4619 mov r1, r3
|
|
8003924: 4828 ldr r0, [pc, #160] ; (80039c8 <BSP_LCD_MspInit+0x1a0>)
|
|
8003926: f004 f94b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOG configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_12;
|
|
800392a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800392e: 62fb str r3, [r7, #44] ; 0x2c
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
8003930: 2302 movs r3, #2
|
|
8003932: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
|
|
8003934: 2309 movs r3, #9
|
|
8003936: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
|
8003938: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
800393c: 4619 mov r1, r3
|
|
800393e: 4823 ldr r0, [pc, #140] ; (80039cc <BSP_LCD_MspInit+0x1a4>)
|
|
8003940: f004 f93e bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOI LTDC alternate configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
|
|
8003944: f44f 4366 mov.w r3, #58880 ; 0xe600
|
|
8003948: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
800394a: 2302 movs r3, #2
|
|
800394c: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
|
800394e: 230e movs r3, #14
|
|
8003950: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
|
|
8003952: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003956: 4619 mov r1, r3
|
|
8003958: 481d ldr r0, [pc, #116] ; (80039d0 <BSP_LCD_MspInit+0x1a8>)
|
|
800395a: f004 f931 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOJ configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
|
|
800395e: f64e 73ff movw r3, #61439 ; 0xefff
|
|
8003962: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
|
|
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
|
|
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
8003964: 2302 movs r3, #2
|
|
8003966: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
|
8003968: 230e movs r3, #14
|
|
800396a: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
|
|
800396c: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003970: 4619 mov r1, r3
|
|
8003972: 4818 ldr r0, [pc, #96] ; (80039d4 <BSP_LCD_MspInit+0x1ac>)
|
|
8003974: f004 f924 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOK configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
|
|
8003978: 23f7 movs r3, #247 ; 0xf7
|
|
800397a: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
800397c: 2302 movs r3, #2
|
|
800397e: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
|
8003980: 230e movs r3, #14
|
|
8003982: 63fb str r3, [r7, #60] ; 0x3c
|
|
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
|
|
8003984: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003988: 4619 mov r1, r3
|
|
800398a: 4813 ldr r0, [pc, #76] ; (80039d8 <BSP_LCD_MspInit+0x1b0>)
|
|
800398c: f004 f918 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* LCD_DISP GPIO configuration */
|
|
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
|
|
8003990: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
8003994: 62fb str r3, [r7, #44] ; 0x2c
|
|
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8003996: 2301 movs r3, #1
|
|
8003998: 633b str r3, [r7, #48] ; 0x30
|
|
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
|
|
800399a: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
800399e: 4619 mov r1, r3
|
|
80039a0: 480b ldr r0, [pc, #44] ; (80039d0 <BSP_LCD_MspInit+0x1a8>)
|
|
80039a2: f004 f90d bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* LCD_BL_CTRL GPIO configuration */
|
|
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
|
|
80039a6: 2308 movs r3, #8
|
|
80039a8: 62fb str r3, [r7, #44] ; 0x2c
|
|
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
|
|
80039aa: 2301 movs r3, #1
|
|
80039ac: 633b str r3, [r7, #48] ; 0x30
|
|
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
|
|
80039ae: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
80039b2: 4619 mov r1, r3
|
|
80039b4: 4808 ldr r0, [pc, #32] ; (80039d8 <BSP_LCD_MspInit+0x1b0>)
|
|
80039b6: f004 f903 bl 8007bc0 <HAL_GPIO_Init>
|
|
}
|
|
80039ba: bf00 nop
|
|
80039bc: 3740 adds r7, #64 ; 0x40
|
|
80039be: 46bd mov sp, r7
|
|
80039c0: bd80 pop {r7, pc}
|
|
80039c2: bf00 nop
|
|
80039c4: 40023800 .word 0x40023800
|
|
80039c8: 40021000 .word 0x40021000
|
|
80039cc: 40021800 .word 0x40021800
|
|
80039d0: 40022000 .word 0x40022000
|
|
80039d4: 40022400 .word 0x40022400
|
|
80039d8: 40022800 .word 0x40022800
|
|
|
|
080039dc <BSP_LCD_ClockConfig>:
|
|
* @note This API is called by BSP_LCD_Init()
|
|
* Being __weak it can be overwritten by the application
|
|
* @retval None
|
|
*/
|
|
__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)
|
|
{
|
|
80039dc: b580 push {r7, lr}
|
|
80039de: b082 sub sp, #8
|
|
80039e0: af00 add r7, sp, #0
|
|
80039e2: 6078 str r0, [r7, #4]
|
|
80039e4: 6039 str r1, [r7, #0]
|
|
/* RK043FN48H LCD clock configuration */
|
|
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
|
|
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
|
|
/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
|
|
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
|
|
80039e6: 4b0a ldr r3, [pc, #40] ; (8003a10 <BSP_LCD_ClockConfig+0x34>)
|
|
80039e8: 2208 movs r2, #8
|
|
80039ea: 601a str r2, [r3, #0]
|
|
periph_clk_init_struct.PLLSAI.PLLSAIN = 192;
|
|
80039ec: 4b08 ldr r3, [pc, #32] ; (8003a10 <BSP_LCD_ClockConfig+0x34>)
|
|
80039ee: 22c0 movs r2, #192 ; 0xc0
|
|
80039f0: 615a str r2, [r3, #20]
|
|
periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER;
|
|
80039f2: 4b07 ldr r3, [pc, #28] ; (8003a10 <BSP_LCD_ClockConfig+0x34>)
|
|
80039f4: 2205 movs r2, #5
|
|
80039f6: 61da str r2, [r3, #28]
|
|
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
|
|
80039f8: 4b05 ldr r3, [pc, #20] ; (8003a10 <BSP_LCD_ClockConfig+0x34>)
|
|
80039fa: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
80039fe: 62da str r2, [r3, #44] ; 0x2c
|
|
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
|
|
8003a00: 4803 ldr r0, [pc, #12] ; (8003a10 <BSP_LCD_ClockConfig+0x34>)
|
|
8003a02: f006 f9f3 bl 8009dec <HAL_RCCEx_PeriphCLKConfig>
|
|
}
|
|
8003a06: bf00 nop
|
|
8003a08: 3708 adds r7, #8
|
|
8003a0a: 46bd mov sp, r7
|
|
8003a0c: bd80 pop {r7, pc}
|
|
8003a0e: bf00 nop
|
|
8003a10: 20000438 .word 0x20000438
|
|
|
|
08003a14 <DrawChar>:
|
|
* @param Ypos: Start column address
|
|
* @param c: Pointer to the character data
|
|
* @retval None
|
|
*/
|
|
static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c)
|
|
{
|
|
8003a14: b580 push {r7, lr}
|
|
8003a16: b088 sub sp, #32
|
|
8003a18: af00 add r7, sp, #0
|
|
8003a1a: 4603 mov r3, r0
|
|
8003a1c: 603a str r2, [r7, #0]
|
|
8003a1e: 80fb strh r3, [r7, #6]
|
|
8003a20: 460b mov r3, r1
|
|
8003a22: 80bb strh r3, [r7, #4]
|
|
uint32_t i = 0, j = 0;
|
|
8003a24: 2300 movs r3, #0
|
|
8003a26: 61fb str r3, [r7, #28]
|
|
8003a28: 2300 movs r3, #0
|
|
8003a2a: 61bb str r3, [r7, #24]
|
|
uint16_t height, width;
|
|
uint8_t offset;
|
|
uint8_t *pchar;
|
|
uint32_t line;
|
|
|
|
height = DrawProp[ActiveLayer].pFont->Height;
|
|
8003a2c: 4b53 ldr r3, [pc, #332] ; (8003b7c <DrawChar+0x168>)
|
|
8003a2e: 681a ldr r2, [r3, #0]
|
|
8003a30: 4953 ldr r1, [pc, #332] ; (8003b80 <DrawChar+0x16c>)
|
|
8003a32: 4613 mov r3, r2
|
|
8003a34: 005b lsls r3, r3, #1
|
|
8003a36: 4413 add r3, r2
|
|
8003a38: 009b lsls r3, r3, #2
|
|
8003a3a: 440b add r3, r1
|
|
8003a3c: 3308 adds r3, #8
|
|
8003a3e: 681b ldr r3, [r3, #0]
|
|
8003a40: 88db ldrh r3, [r3, #6]
|
|
8003a42: 827b strh r3, [r7, #18]
|
|
width = DrawProp[ActiveLayer].pFont->Width;
|
|
8003a44: 4b4d ldr r3, [pc, #308] ; (8003b7c <DrawChar+0x168>)
|
|
8003a46: 681a ldr r2, [r3, #0]
|
|
8003a48: 494d ldr r1, [pc, #308] ; (8003b80 <DrawChar+0x16c>)
|
|
8003a4a: 4613 mov r3, r2
|
|
8003a4c: 005b lsls r3, r3, #1
|
|
8003a4e: 4413 add r3, r2
|
|
8003a50: 009b lsls r3, r3, #2
|
|
8003a52: 440b add r3, r1
|
|
8003a54: 3308 adds r3, #8
|
|
8003a56: 681b ldr r3, [r3, #0]
|
|
8003a58: 889b ldrh r3, [r3, #4]
|
|
8003a5a: 823b strh r3, [r7, #16]
|
|
|
|
offset = 8 *((width + 7)/8) - width ;
|
|
8003a5c: 8a3b ldrh r3, [r7, #16]
|
|
8003a5e: 3307 adds r3, #7
|
|
8003a60: 2b00 cmp r3, #0
|
|
8003a62: da00 bge.n 8003a66 <DrawChar+0x52>
|
|
8003a64: 3307 adds r3, #7
|
|
8003a66: 10db asrs r3, r3, #3
|
|
8003a68: b2db uxtb r3, r3
|
|
8003a6a: 00db lsls r3, r3, #3
|
|
8003a6c: b2da uxtb r2, r3
|
|
8003a6e: 8a3b ldrh r3, [r7, #16]
|
|
8003a70: b2db uxtb r3, r3
|
|
8003a72: 1ad3 subs r3, r2, r3
|
|
8003a74: 73fb strb r3, [r7, #15]
|
|
|
|
for(i = 0; i < height; i++)
|
|
8003a76: 2300 movs r3, #0
|
|
8003a78: 61fb str r3, [r7, #28]
|
|
8003a7a: e076 b.n 8003b6a <DrawChar+0x156>
|
|
{
|
|
pchar = ((uint8_t *)c + (width + 7)/8 * i);
|
|
8003a7c: 8a3b ldrh r3, [r7, #16]
|
|
8003a7e: 3307 adds r3, #7
|
|
8003a80: 2b00 cmp r3, #0
|
|
8003a82: da00 bge.n 8003a86 <DrawChar+0x72>
|
|
8003a84: 3307 adds r3, #7
|
|
8003a86: 10db asrs r3, r3, #3
|
|
8003a88: 461a mov r2, r3
|
|
8003a8a: 69fb ldr r3, [r7, #28]
|
|
8003a8c: fb03 f302 mul.w r3, r3, r2
|
|
8003a90: 683a ldr r2, [r7, #0]
|
|
8003a92: 4413 add r3, r2
|
|
8003a94: 60bb str r3, [r7, #8]
|
|
|
|
switch(((width + 7)/8))
|
|
8003a96: 8a3b ldrh r3, [r7, #16]
|
|
8003a98: 3307 adds r3, #7
|
|
8003a9a: 2b00 cmp r3, #0
|
|
8003a9c: da00 bge.n 8003aa0 <DrawChar+0x8c>
|
|
8003a9e: 3307 adds r3, #7
|
|
8003aa0: 10db asrs r3, r3, #3
|
|
8003aa2: 2b01 cmp r3, #1
|
|
8003aa4: d002 beq.n 8003aac <DrawChar+0x98>
|
|
8003aa6: 2b02 cmp r3, #2
|
|
8003aa8: d004 beq.n 8003ab4 <DrawChar+0xa0>
|
|
8003aaa: e00c b.n 8003ac6 <DrawChar+0xb2>
|
|
{
|
|
|
|
case 1:
|
|
line = pchar[0];
|
|
8003aac: 68bb ldr r3, [r7, #8]
|
|
8003aae: 781b ldrb r3, [r3, #0]
|
|
8003ab0: 617b str r3, [r7, #20]
|
|
break;
|
|
8003ab2: e016 b.n 8003ae2 <DrawChar+0xce>
|
|
|
|
case 2:
|
|
line = (pchar[0]<< 8) | pchar[1];
|
|
8003ab4: 68bb ldr r3, [r7, #8]
|
|
8003ab6: 781b ldrb r3, [r3, #0]
|
|
8003ab8: 021b lsls r3, r3, #8
|
|
8003aba: 68ba ldr r2, [r7, #8]
|
|
8003abc: 3201 adds r2, #1
|
|
8003abe: 7812 ldrb r2, [r2, #0]
|
|
8003ac0: 4313 orrs r3, r2
|
|
8003ac2: 617b str r3, [r7, #20]
|
|
break;
|
|
8003ac4: e00d b.n 8003ae2 <DrawChar+0xce>
|
|
|
|
case 3:
|
|
default:
|
|
line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2];
|
|
8003ac6: 68bb ldr r3, [r7, #8]
|
|
8003ac8: 781b ldrb r3, [r3, #0]
|
|
8003aca: 041a lsls r2, r3, #16
|
|
8003acc: 68bb ldr r3, [r7, #8]
|
|
8003ace: 3301 adds r3, #1
|
|
8003ad0: 781b ldrb r3, [r3, #0]
|
|
8003ad2: 021b lsls r3, r3, #8
|
|
8003ad4: 4313 orrs r3, r2
|
|
8003ad6: 68ba ldr r2, [r7, #8]
|
|
8003ad8: 3202 adds r2, #2
|
|
8003ada: 7812 ldrb r2, [r2, #0]
|
|
8003adc: 4313 orrs r3, r2
|
|
8003ade: 617b str r3, [r7, #20]
|
|
break;
|
|
8003ae0: bf00 nop
|
|
}
|
|
|
|
for (j = 0; j < width; j++)
|
|
8003ae2: 2300 movs r3, #0
|
|
8003ae4: 61bb str r3, [r7, #24]
|
|
8003ae6: e036 b.n 8003b56 <DrawChar+0x142>
|
|
{
|
|
if(line & (1 << (width- j + offset- 1)))
|
|
8003ae8: 8a3a ldrh r2, [r7, #16]
|
|
8003aea: 69bb ldr r3, [r7, #24]
|
|
8003aec: 1ad2 subs r2, r2, r3
|
|
8003aee: 7bfb ldrb r3, [r7, #15]
|
|
8003af0: 4413 add r3, r2
|
|
8003af2: 3b01 subs r3, #1
|
|
8003af4: 2201 movs r2, #1
|
|
8003af6: fa02 f303 lsl.w r3, r2, r3
|
|
8003afa: 461a mov r2, r3
|
|
8003afc: 697b ldr r3, [r7, #20]
|
|
8003afe: 4013 ands r3, r2
|
|
8003b00: 2b00 cmp r3, #0
|
|
8003b02: d012 beq.n 8003b2a <DrawChar+0x116>
|
|
{
|
|
BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor);
|
|
8003b04: 69bb ldr r3, [r7, #24]
|
|
8003b06: b29a uxth r2, r3
|
|
8003b08: 88fb ldrh r3, [r7, #6]
|
|
8003b0a: 4413 add r3, r2
|
|
8003b0c: b298 uxth r0, r3
|
|
8003b0e: 4b1b ldr r3, [pc, #108] ; (8003b7c <DrawChar+0x168>)
|
|
8003b10: 681a ldr r2, [r3, #0]
|
|
8003b12: 491b ldr r1, [pc, #108] ; (8003b80 <DrawChar+0x16c>)
|
|
8003b14: 4613 mov r3, r2
|
|
8003b16: 005b lsls r3, r3, #1
|
|
8003b18: 4413 add r3, r2
|
|
8003b1a: 009b lsls r3, r3, #2
|
|
8003b1c: 440b add r3, r1
|
|
8003b1e: 681a ldr r2, [r3, #0]
|
|
8003b20: 88bb ldrh r3, [r7, #4]
|
|
8003b22: 4619 mov r1, r3
|
|
8003b24: f7ff fc50 bl 80033c8 <BSP_LCD_DrawPixel>
|
|
8003b28: e012 b.n 8003b50 <DrawChar+0x13c>
|
|
}
|
|
else
|
|
{
|
|
BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor);
|
|
8003b2a: 69bb ldr r3, [r7, #24]
|
|
8003b2c: b29a uxth r2, r3
|
|
8003b2e: 88fb ldrh r3, [r7, #6]
|
|
8003b30: 4413 add r3, r2
|
|
8003b32: b298 uxth r0, r3
|
|
8003b34: 4b11 ldr r3, [pc, #68] ; (8003b7c <DrawChar+0x168>)
|
|
8003b36: 681a ldr r2, [r3, #0]
|
|
8003b38: 4911 ldr r1, [pc, #68] ; (8003b80 <DrawChar+0x16c>)
|
|
8003b3a: 4613 mov r3, r2
|
|
8003b3c: 005b lsls r3, r3, #1
|
|
8003b3e: 4413 add r3, r2
|
|
8003b40: 009b lsls r3, r3, #2
|
|
8003b42: 440b add r3, r1
|
|
8003b44: 3304 adds r3, #4
|
|
8003b46: 681a ldr r2, [r3, #0]
|
|
8003b48: 88bb ldrh r3, [r7, #4]
|
|
8003b4a: 4619 mov r1, r3
|
|
8003b4c: f7ff fc3c bl 80033c8 <BSP_LCD_DrawPixel>
|
|
for (j = 0; j < width; j++)
|
|
8003b50: 69bb ldr r3, [r7, #24]
|
|
8003b52: 3301 adds r3, #1
|
|
8003b54: 61bb str r3, [r7, #24]
|
|
8003b56: 8a3b ldrh r3, [r7, #16]
|
|
8003b58: 69ba ldr r2, [r7, #24]
|
|
8003b5a: 429a cmp r2, r3
|
|
8003b5c: d3c4 bcc.n 8003ae8 <DrawChar+0xd4>
|
|
}
|
|
}
|
|
Ypos++;
|
|
8003b5e: 88bb ldrh r3, [r7, #4]
|
|
8003b60: 3301 adds r3, #1
|
|
8003b62: 80bb strh r3, [r7, #4]
|
|
for(i = 0; i < height; i++)
|
|
8003b64: 69fb ldr r3, [r7, #28]
|
|
8003b66: 3301 adds r3, #1
|
|
8003b68: 61fb str r3, [r7, #28]
|
|
8003b6a: 8a7b ldrh r3, [r7, #18]
|
|
8003b6c: 69fa ldr r2, [r7, #28]
|
|
8003b6e: 429a cmp r2, r3
|
|
8003b70: d384 bcc.n 8003a7c <DrawChar+0x68>
|
|
}
|
|
}
|
|
8003b72: bf00 nop
|
|
8003b74: 3720 adds r7, #32
|
|
8003b76: 46bd mov sp, r7
|
|
8003b78: bd80 pop {r7, pc}
|
|
8003b7a: bf00 nop
|
|
8003b7c: 2000041c .word 0x2000041c
|
|
8003b80: 20000420 .word 0x20000420
|
|
|
|
08003b84 <LL_FillBuffer>:
|
|
* @param OffLine: Offset
|
|
* @param ColorIndex: Color index
|
|
* @retval None
|
|
*/
|
|
static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
|
|
{
|
|
8003b84: b580 push {r7, lr}
|
|
8003b86: b086 sub sp, #24
|
|
8003b88: af02 add r7, sp, #8
|
|
8003b8a: 60f8 str r0, [r7, #12]
|
|
8003b8c: 60b9 str r1, [r7, #8]
|
|
8003b8e: 607a str r2, [r7, #4]
|
|
8003b90: 603b str r3, [r7, #0]
|
|
/* Register to memory mode with ARGB8888 as color Mode */
|
|
hDma2dHandler.Init.Mode = DMA2D_R2M;
|
|
8003b92: 4b1e ldr r3, [pc, #120] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003b94: f44f 3240 mov.w r2, #196608 ; 0x30000
|
|
8003b98: 605a str r2, [r3, #4]
|
|
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
|
|
8003b9a: 4b1d ldr r3, [pc, #116] ; (8003c10 <LL_FillBuffer+0x8c>)
|
|
8003b9c: 681b ldr r3, [r3, #0]
|
|
8003b9e: 4a1d ldr r2, [pc, #116] ; (8003c14 <LL_FillBuffer+0x90>)
|
|
8003ba0: 2134 movs r1, #52 ; 0x34
|
|
8003ba2: fb01 f303 mul.w r3, r1, r3
|
|
8003ba6: 4413 add r3, r2
|
|
8003ba8: 3348 adds r3, #72 ; 0x48
|
|
8003baa: 681b ldr r3, [r3, #0]
|
|
8003bac: 2b02 cmp r3, #2
|
|
8003bae: d103 bne.n 8003bb8 <LL_FillBuffer+0x34>
|
|
{ /* RGB565 format */
|
|
hDma2dHandler.Init.ColorMode = DMA2D_RGB565;
|
|
8003bb0: 4b16 ldr r3, [pc, #88] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bb2: 2202 movs r2, #2
|
|
8003bb4: 609a str r2, [r3, #8]
|
|
8003bb6: e002 b.n 8003bbe <LL_FillBuffer+0x3a>
|
|
}
|
|
else
|
|
{ /* ARGB8888 format */
|
|
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
|
|
8003bb8: 4b14 ldr r3, [pc, #80] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bba: 2200 movs r2, #0
|
|
8003bbc: 609a str r2, [r3, #8]
|
|
}
|
|
hDma2dHandler.Init.OutputOffset = OffLine;
|
|
8003bbe: 4a13 ldr r2, [pc, #76] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bc0: 69bb ldr r3, [r7, #24]
|
|
8003bc2: 60d3 str r3, [r2, #12]
|
|
|
|
hDma2dHandler.Instance = DMA2D;
|
|
8003bc4: 4b11 ldr r3, [pc, #68] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bc6: 4a14 ldr r2, [pc, #80] ; (8003c18 <LL_FillBuffer+0x94>)
|
|
8003bc8: 601a str r2, [r3, #0]
|
|
|
|
/* DMA2D Initialization */
|
|
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
|
|
8003bca: 4810 ldr r0, [pc, #64] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bcc: f002 fbe6 bl 800639c <HAL_DMA2D_Init>
|
|
8003bd0: 4603 mov r3, r0
|
|
8003bd2: 2b00 cmp r3, #0
|
|
8003bd4: d115 bne.n 8003c02 <LL_FillBuffer+0x7e>
|
|
{
|
|
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK)
|
|
8003bd6: 68f9 ldr r1, [r7, #12]
|
|
8003bd8: 480c ldr r0, [pc, #48] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bda: f002 fd3d bl 8006658 <HAL_DMA2D_ConfigLayer>
|
|
8003bde: 4603 mov r3, r0
|
|
8003be0: 2b00 cmp r3, #0
|
|
8003be2: d10e bne.n 8003c02 <LL_FillBuffer+0x7e>
|
|
{
|
|
if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
|
|
8003be4: 68ba ldr r2, [r7, #8]
|
|
8003be6: 683b ldr r3, [r7, #0]
|
|
8003be8: 9300 str r3, [sp, #0]
|
|
8003bea: 687b ldr r3, [r7, #4]
|
|
8003bec: 69f9 ldr r1, [r7, #28]
|
|
8003bee: 4807 ldr r0, [pc, #28] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bf0: f002 fc1e bl 8006430 <HAL_DMA2D_Start>
|
|
8003bf4: 4603 mov r3, r0
|
|
8003bf6: 2b00 cmp r3, #0
|
|
8003bf8: d103 bne.n 8003c02 <LL_FillBuffer+0x7e>
|
|
{
|
|
/* Polling For DMA transfer */
|
|
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
|
|
8003bfa: 210a movs r1, #10
|
|
8003bfc: 4803 ldr r0, [pc, #12] ; (8003c0c <LL_FillBuffer+0x88>)
|
|
8003bfe: f002 fc42 bl 8006486 <HAL_DMA2D_PollForTransfer>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8003c02: bf00 nop
|
|
8003c04: 3710 adds r7, #16
|
|
8003c06: 46bd mov sp, r7
|
|
8003c08: bd80 pop {r7, pc}
|
|
8003c0a: bf00 nop
|
|
8003c0c: 200003dc .word 0x200003dc
|
|
8003c10: 2000041c .word 0x2000041c
|
|
8003c14: 20008e70 .word 0x20008e70
|
|
8003c18: 4002b000 .word 0x4002b000
|
|
|
|
08003c1c <LL_ConvertLineToARGB8888>:
|
|
* @param xSize: Buffer width
|
|
* @param ColorMode: Input color mode
|
|
* @retval None
|
|
*/
|
|
static void LL_ConvertLineToARGB8888(void *pSrc, void *pDst, uint32_t xSize, uint32_t ColorMode)
|
|
{
|
|
8003c1c: b580 push {r7, lr}
|
|
8003c1e: b086 sub sp, #24
|
|
8003c20: af02 add r7, sp, #8
|
|
8003c22: 60f8 str r0, [r7, #12]
|
|
8003c24: 60b9 str r1, [r7, #8]
|
|
8003c26: 607a str r2, [r7, #4]
|
|
8003c28: 603b str r3, [r7, #0]
|
|
/* Configure the DMA2D Mode, Color Mode and output offset */
|
|
hDma2dHandler.Init.Mode = DMA2D_M2M_PFC;
|
|
8003c2a: 4b1c ldr r3, [pc, #112] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c2c: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
8003c30: 605a str r2, [r3, #4]
|
|
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
|
|
8003c32: 4b1a ldr r3, [pc, #104] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c34: 2200 movs r2, #0
|
|
8003c36: 609a str r2, [r3, #8]
|
|
hDma2dHandler.Init.OutputOffset = 0;
|
|
8003c38: 4b18 ldr r3, [pc, #96] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c3a: 2200 movs r2, #0
|
|
8003c3c: 60da str r2, [r3, #12]
|
|
|
|
/* Foreground Configuration */
|
|
hDma2dHandler.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
|
|
8003c3e: 4b17 ldr r3, [pc, #92] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c40: 2200 movs r2, #0
|
|
8003c42: 631a str r2, [r3, #48] ; 0x30
|
|
hDma2dHandler.LayerCfg[1].InputAlpha = 0xFF;
|
|
8003c44: 4b15 ldr r3, [pc, #84] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c46: 22ff movs r2, #255 ; 0xff
|
|
8003c48: 635a str r2, [r3, #52] ; 0x34
|
|
hDma2dHandler.LayerCfg[1].InputColorMode = ColorMode;
|
|
8003c4a: 4a14 ldr r2, [pc, #80] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c4c: 683b ldr r3, [r7, #0]
|
|
8003c4e: 62d3 str r3, [r2, #44] ; 0x2c
|
|
hDma2dHandler.LayerCfg[1].InputOffset = 0;
|
|
8003c50: 4b12 ldr r3, [pc, #72] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c52: 2200 movs r2, #0
|
|
8003c54: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
hDma2dHandler.Instance = DMA2D;
|
|
8003c56: 4b11 ldr r3, [pc, #68] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c58: 4a11 ldr r2, [pc, #68] ; (8003ca0 <LL_ConvertLineToARGB8888+0x84>)
|
|
8003c5a: 601a str r2, [r3, #0]
|
|
|
|
/* DMA2D Initialization */
|
|
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
|
|
8003c5c: 480f ldr r0, [pc, #60] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c5e: f002 fb9d bl 800639c <HAL_DMA2D_Init>
|
|
8003c62: 4603 mov r3, r0
|
|
8003c64: 2b00 cmp r3, #0
|
|
8003c66: d115 bne.n 8003c94 <LL_ConvertLineToARGB8888+0x78>
|
|
{
|
|
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, 1) == HAL_OK)
|
|
8003c68: 2101 movs r1, #1
|
|
8003c6a: 480c ldr r0, [pc, #48] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c6c: f002 fcf4 bl 8006658 <HAL_DMA2D_ConfigLayer>
|
|
8003c70: 4603 mov r3, r0
|
|
8003c72: 2b00 cmp r3, #0
|
|
8003c74: d10e bne.n 8003c94 <LL_ConvertLineToARGB8888+0x78>
|
|
{
|
|
if (HAL_DMA2D_Start(&hDma2dHandler, (uint32_t)pSrc, (uint32_t)pDst, xSize, 1) == HAL_OK)
|
|
8003c76: 68f9 ldr r1, [r7, #12]
|
|
8003c78: 68ba ldr r2, [r7, #8]
|
|
8003c7a: 2301 movs r3, #1
|
|
8003c7c: 9300 str r3, [sp, #0]
|
|
8003c7e: 687b ldr r3, [r7, #4]
|
|
8003c80: 4806 ldr r0, [pc, #24] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c82: f002 fbd5 bl 8006430 <HAL_DMA2D_Start>
|
|
8003c86: 4603 mov r3, r0
|
|
8003c88: 2b00 cmp r3, #0
|
|
8003c8a: d103 bne.n 8003c94 <LL_ConvertLineToARGB8888+0x78>
|
|
{
|
|
/* Polling For DMA transfer */
|
|
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
|
|
8003c8c: 210a movs r1, #10
|
|
8003c8e: 4803 ldr r0, [pc, #12] ; (8003c9c <LL_ConvertLineToARGB8888+0x80>)
|
|
8003c90: f002 fbf9 bl 8006486 <HAL_DMA2D_PollForTransfer>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8003c94: bf00 nop
|
|
8003c96: 3710 adds r7, #16
|
|
8003c98: 46bd mov sp, r7
|
|
8003c9a: bd80 pop {r7, pc}
|
|
8003c9c: 200003dc .word 0x200003dc
|
|
8003ca0: 4002b000 .word 0x4002b000
|
|
|
|
08003ca4 <BSP_SDRAM_Init>:
|
|
/**
|
|
* @brief Initializes the SDRAM device.
|
|
* @retval SDRAM status
|
|
*/
|
|
uint8_t BSP_SDRAM_Init(void)
|
|
{
|
|
8003ca4: b580 push {r7, lr}
|
|
8003ca6: af00 add r7, sp, #0
|
|
static uint8_t sdramstatus = SDRAM_ERROR;
|
|
/* SDRAM device configuration */
|
|
sdramHandle.Instance = FMC_SDRAM_DEVICE;
|
|
8003ca8: 4b29 ldr r3, [pc, #164] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003caa: 4a2a ldr r2, [pc, #168] ; (8003d54 <BSP_SDRAM_Init+0xb0>)
|
|
8003cac: 601a str r2, [r3, #0]
|
|
|
|
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
|
|
Timing.LoadToActiveDelay = 2;
|
|
8003cae: 4b2a ldr r3, [pc, #168] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cb0: 2202 movs r2, #2
|
|
8003cb2: 601a str r2, [r3, #0]
|
|
Timing.ExitSelfRefreshDelay = 7;
|
|
8003cb4: 4b28 ldr r3, [pc, #160] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cb6: 2207 movs r2, #7
|
|
8003cb8: 605a str r2, [r3, #4]
|
|
Timing.SelfRefreshTime = 4;
|
|
8003cba: 4b27 ldr r3, [pc, #156] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cbc: 2204 movs r2, #4
|
|
8003cbe: 609a str r2, [r3, #8]
|
|
Timing.RowCycleDelay = 7;
|
|
8003cc0: 4b25 ldr r3, [pc, #148] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cc2: 2207 movs r2, #7
|
|
8003cc4: 60da str r2, [r3, #12]
|
|
Timing.WriteRecoveryTime = 2;
|
|
8003cc6: 4b24 ldr r3, [pc, #144] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cc8: 2202 movs r2, #2
|
|
8003cca: 611a str r2, [r3, #16]
|
|
Timing.RPDelay = 2;
|
|
8003ccc: 4b22 ldr r3, [pc, #136] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cce: 2202 movs r2, #2
|
|
8003cd0: 615a str r2, [r3, #20]
|
|
Timing.RCDDelay = 2;
|
|
8003cd2: 4b21 ldr r3, [pc, #132] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003cd4: 2202 movs r2, #2
|
|
8003cd6: 619a str r2, [r3, #24]
|
|
|
|
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
|
|
8003cd8: 4b1d ldr r3, [pc, #116] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003cda: 2200 movs r2, #0
|
|
8003cdc: 605a str r2, [r3, #4]
|
|
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
|
8003cde: 4b1c ldr r3, [pc, #112] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003ce0: 2200 movs r2, #0
|
|
8003ce2: 609a str r2, [r3, #8]
|
|
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
|
8003ce4: 4b1a ldr r3, [pc, #104] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003ce6: 2204 movs r2, #4
|
|
8003ce8: 60da str r2, [r3, #12]
|
|
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
|
|
8003cea: 4b19 ldr r3, [pc, #100] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003cec: 2210 movs r2, #16
|
|
8003cee: 611a str r2, [r3, #16]
|
|
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
|
8003cf0: 4b17 ldr r3, [pc, #92] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003cf2: 2240 movs r2, #64 ; 0x40
|
|
8003cf4: 615a str r2, [r3, #20]
|
|
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
|
|
8003cf6: 4b16 ldr r3, [pc, #88] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003cf8: f44f 7280 mov.w r2, #256 ; 0x100
|
|
8003cfc: 619a str r2, [r3, #24]
|
|
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
|
8003cfe: 4b14 ldr r3, [pc, #80] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d00: 2200 movs r2, #0
|
|
8003d02: 61da str r2, [r3, #28]
|
|
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
|
|
8003d04: 4b12 ldr r3, [pc, #72] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d06: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
8003d0a: 621a str r2, [r3, #32]
|
|
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
|
|
8003d0c: 4b10 ldr r3, [pc, #64] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d0e: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8003d12: 625a str r2, [r3, #36] ; 0x24
|
|
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
|
|
8003d14: 4b0e ldr r3, [pc, #56] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d16: 2200 movs r2, #0
|
|
8003d18: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* SDRAM controller initialization */
|
|
|
|
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
|
|
8003d1a: 2100 movs r1, #0
|
|
8003d1c: 480c ldr r0, [pc, #48] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d1e: f000 f87f bl 8003e20 <BSP_SDRAM_MspInit>
|
|
|
|
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
|
|
8003d22: 490d ldr r1, [pc, #52] ; (8003d58 <BSP_SDRAM_Init+0xb4>)
|
|
8003d24: 480a ldr r0, [pc, #40] ; (8003d50 <BSP_SDRAM_Init+0xac>)
|
|
8003d26: f007 f83b bl 800ada0 <HAL_SDRAM_Init>
|
|
8003d2a: 4603 mov r3, r0
|
|
8003d2c: 2b00 cmp r3, #0
|
|
8003d2e: d003 beq.n 8003d38 <BSP_SDRAM_Init+0x94>
|
|
{
|
|
sdramstatus = SDRAM_ERROR;
|
|
8003d30: 4b0a ldr r3, [pc, #40] ; (8003d5c <BSP_SDRAM_Init+0xb8>)
|
|
8003d32: 2201 movs r2, #1
|
|
8003d34: 701a strb r2, [r3, #0]
|
|
8003d36: e002 b.n 8003d3e <BSP_SDRAM_Init+0x9a>
|
|
}
|
|
else
|
|
{
|
|
sdramstatus = SDRAM_OK;
|
|
8003d38: 4b08 ldr r3, [pc, #32] ; (8003d5c <BSP_SDRAM_Init+0xb8>)
|
|
8003d3a: 2200 movs r2, #0
|
|
8003d3c: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* SDRAM initialization sequence */
|
|
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
|
|
8003d3e: f240 6003 movw r0, #1539 ; 0x603
|
|
8003d42: f000 f80d bl 8003d60 <BSP_SDRAM_Initialization_sequence>
|
|
|
|
return sdramstatus;
|
|
8003d46: 4b05 ldr r3, [pc, #20] ; (8003d5c <BSP_SDRAM_Init+0xb8>)
|
|
8003d48: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8003d4a: 4618 mov r0, r3
|
|
8003d4c: bd80 pop {r7, pc}
|
|
8003d4e: bf00 nop
|
|
8003d50: 20008f18 .word 0x20008f18
|
|
8003d54: a0000140 .word 0xa0000140
|
|
8003d58: 200004bc .word 0x200004bc
|
|
8003d5c: 20000060 .word 0x20000060
|
|
|
|
08003d60 <BSP_SDRAM_Initialization_sequence>:
|
|
* @brief Programs the SDRAM device.
|
|
* @param RefreshCount: SDRAM refresh counter value
|
|
* @retval None
|
|
*/
|
|
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
|
|
{
|
|
8003d60: b580 push {r7, lr}
|
|
8003d62: b084 sub sp, #16
|
|
8003d64: af00 add r7, sp, #0
|
|
8003d66: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpmrd = 0;
|
|
8003d68: 2300 movs r3, #0
|
|
8003d6a: 60fb str r3, [r7, #12]
|
|
|
|
/* Step 1: Configure a clock configuration enable command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
|
|
8003d6c: 4b2a ldr r3, [pc, #168] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d6e: 2201 movs r2, #1
|
|
8003d70: 601a str r2, [r3, #0]
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
8003d72: 4b29 ldr r3, [pc, #164] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d74: 2210 movs r2, #16
|
|
8003d76: 605a str r2, [r3, #4]
|
|
Command.AutoRefreshNumber = 1;
|
|
8003d78: 4b27 ldr r3, [pc, #156] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d7a: 2201 movs r2, #1
|
|
8003d7c: 609a str r2, [r3, #8]
|
|
Command.ModeRegisterDefinition = 0;
|
|
8003d7e: 4b26 ldr r3, [pc, #152] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d80: 2200 movs r2, #0
|
|
8003d82: 60da str r2, [r3, #12]
|
|
|
|
/* Send the command */
|
|
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
|
8003d84: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8003d88: 4923 ldr r1, [pc, #140] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d8a: 4824 ldr r0, [pc, #144] ; (8003e1c <BSP_SDRAM_Initialization_sequence+0xbc>)
|
|
8003d8c: f007 f83c bl 800ae08 <HAL_SDRAM_SendCommand>
|
|
|
|
/* Step 2: Insert 100 us minimum delay */
|
|
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
|
|
HAL_Delay(1);
|
|
8003d90: 2001 movs r0, #1
|
|
8003d92: f001 fab1 bl 80052f8 <HAL_Delay>
|
|
|
|
/* Step 3: Configure a PALL (precharge all) command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_PALL;
|
|
8003d96: 4b20 ldr r3, [pc, #128] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d98: 2202 movs r2, #2
|
|
8003d9a: 601a str r2, [r3, #0]
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
8003d9c: 4b1e ldr r3, [pc, #120] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003d9e: 2210 movs r2, #16
|
|
8003da0: 605a str r2, [r3, #4]
|
|
Command.AutoRefreshNumber = 1;
|
|
8003da2: 4b1d ldr r3, [pc, #116] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003da4: 2201 movs r2, #1
|
|
8003da6: 609a str r2, [r3, #8]
|
|
Command.ModeRegisterDefinition = 0;
|
|
8003da8: 4b1b ldr r3, [pc, #108] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003daa: 2200 movs r2, #0
|
|
8003dac: 60da str r2, [r3, #12]
|
|
|
|
/* Send the command */
|
|
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
|
8003dae: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8003db2: 4919 ldr r1, [pc, #100] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003db4: 4819 ldr r0, [pc, #100] ; (8003e1c <BSP_SDRAM_Initialization_sequence+0xbc>)
|
|
8003db6: f007 f827 bl 800ae08 <HAL_SDRAM_SendCommand>
|
|
|
|
/* Step 4: Configure an Auto Refresh command */
|
|
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
|
|
8003dba: 4b17 ldr r3, [pc, #92] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dbc: 2203 movs r2, #3
|
|
8003dbe: 601a str r2, [r3, #0]
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
8003dc0: 4b15 ldr r3, [pc, #84] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dc2: 2210 movs r2, #16
|
|
8003dc4: 605a str r2, [r3, #4]
|
|
Command.AutoRefreshNumber = 8;
|
|
8003dc6: 4b14 ldr r3, [pc, #80] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dc8: 2208 movs r2, #8
|
|
8003dca: 609a str r2, [r3, #8]
|
|
Command.ModeRegisterDefinition = 0;
|
|
8003dcc: 4b12 ldr r3, [pc, #72] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dce: 2200 movs r2, #0
|
|
8003dd0: 60da str r2, [r3, #12]
|
|
|
|
/* Send the command */
|
|
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
|
8003dd2: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8003dd6: 4910 ldr r1, [pc, #64] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dd8: 4810 ldr r0, [pc, #64] ; (8003e1c <BSP_SDRAM_Initialization_sequence+0xbc>)
|
|
8003dda: f007 f815 bl 800ae08 <HAL_SDRAM_SendCommand>
|
|
|
|
/* Step 5: Program the external memory mode register */
|
|
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
|
|
8003dde: f44f 7308 mov.w r3, #544 ; 0x220
|
|
8003de2: 60fb str r3, [r7, #12]
|
|
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
|
|
SDRAM_MODEREG_CAS_LATENCY_2 |\
|
|
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
|
|
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
|
|
|
|
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
|
|
8003de4: 4b0c ldr r3, [pc, #48] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003de6: 2204 movs r2, #4
|
|
8003de8: 601a str r2, [r3, #0]
|
|
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
|
8003dea: 4b0b ldr r3, [pc, #44] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dec: 2210 movs r2, #16
|
|
8003dee: 605a str r2, [r3, #4]
|
|
Command.AutoRefreshNumber = 1;
|
|
8003df0: 4b09 ldr r3, [pc, #36] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003df2: 2201 movs r2, #1
|
|
8003df4: 609a str r2, [r3, #8]
|
|
Command.ModeRegisterDefinition = tmpmrd;
|
|
8003df6: 68fb ldr r3, [r7, #12]
|
|
8003df8: 4a07 ldr r2, [pc, #28] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003dfa: 60d3 str r3, [r2, #12]
|
|
|
|
/* Send the command */
|
|
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
|
8003dfc: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8003e00: 4905 ldr r1, [pc, #20] ; (8003e18 <BSP_SDRAM_Initialization_sequence+0xb8>)
|
|
8003e02: 4806 ldr r0, [pc, #24] ; (8003e1c <BSP_SDRAM_Initialization_sequence+0xbc>)
|
|
8003e04: f007 f800 bl 800ae08 <HAL_SDRAM_SendCommand>
|
|
|
|
/* Step 6: Set the refresh rate counter */
|
|
/* Set the device refresh rate */
|
|
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
|
|
8003e08: 6879 ldr r1, [r7, #4]
|
|
8003e0a: 4804 ldr r0, [pc, #16] ; (8003e1c <BSP_SDRAM_Initialization_sequence+0xbc>)
|
|
8003e0c: f007 f827 bl 800ae5e <HAL_SDRAM_ProgramRefreshRate>
|
|
}
|
|
8003e10: bf00 nop
|
|
8003e12: 3710 adds r7, #16
|
|
8003e14: 46bd mov sp, r7
|
|
8003e16: bd80 pop {r7, pc}
|
|
8003e18: 200004d8 .word 0x200004d8
|
|
8003e1c: 20008f18 .word 0x20008f18
|
|
|
|
08003e20 <BSP_SDRAM_MspInit>:
|
|
* @param hsdram: SDRAM handle
|
|
* @param Params
|
|
* @retval None
|
|
*/
|
|
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
|
|
{
|
|
8003e20: b580 push {r7, lr}
|
|
8003e22: b090 sub sp, #64 ; 0x40
|
|
8003e24: af00 add r7, sp, #0
|
|
8003e26: 6078 str r0, [r7, #4]
|
|
8003e28: 6039 str r1, [r7, #0]
|
|
static DMA_HandleTypeDef dma_handle;
|
|
GPIO_InitTypeDef gpio_init_structure;
|
|
|
|
/* Enable FMC clock */
|
|
__HAL_RCC_FMC_CLK_ENABLE();
|
|
8003e2a: 4b70 ldr r3, [pc, #448] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e2c: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8003e2e: 4a6f ldr r2, [pc, #444] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e30: f043 0301 orr.w r3, r3, #1
|
|
8003e34: 6393 str r3, [r2, #56] ; 0x38
|
|
8003e36: 4b6d ldr r3, [pc, #436] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e38: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8003e3a: f003 0301 and.w r3, r3, #1
|
|
8003e3e: 62bb str r3, [r7, #40] ; 0x28
|
|
8003e40: 6abb ldr r3, [r7, #40] ; 0x28
|
|
|
|
/* Enable chosen DMAx clock */
|
|
__DMAx_CLK_ENABLE();
|
|
8003e42: 4b6a ldr r3, [pc, #424] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e44: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e46: 4a69 ldr r2, [pc, #420] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e48: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
|
|
8003e4c: 6313 str r3, [r2, #48] ; 0x30
|
|
8003e4e: 4b67 ldr r3, [pc, #412] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e50: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e52: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
8003e56: 627b str r3, [r7, #36] ; 0x24
|
|
8003e58: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
|
|
/* Enable GPIOs clock */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8003e5a: 4b64 ldr r3, [pc, #400] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e5c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e5e: 4a63 ldr r2, [pc, #396] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e60: f043 0304 orr.w r3, r3, #4
|
|
8003e64: 6313 str r3, [r2, #48] ; 0x30
|
|
8003e66: 4b61 ldr r3, [pc, #388] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e68: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e6a: f003 0304 and.w r3, r3, #4
|
|
8003e6e: 623b str r3, [r7, #32]
|
|
8003e70: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8003e72: 4b5e ldr r3, [pc, #376] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e74: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e76: 4a5d ldr r2, [pc, #372] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e78: f043 0308 orr.w r3, r3, #8
|
|
8003e7c: 6313 str r3, [r2, #48] ; 0x30
|
|
8003e7e: 4b5b ldr r3, [pc, #364] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e80: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e82: f003 0308 and.w r3, r3, #8
|
|
8003e86: 61fb str r3, [r7, #28]
|
|
8003e88: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8003e8a: 4b58 ldr r3, [pc, #352] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e8c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e8e: 4a57 ldr r2, [pc, #348] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e90: f043 0310 orr.w r3, r3, #16
|
|
8003e94: 6313 str r3, [r2, #48] ; 0x30
|
|
8003e96: 4b55 ldr r3, [pc, #340] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003e98: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003e9a: f003 0310 and.w r3, r3, #16
|
|
8003e9e: 61bb str r3, [r7, #24]
|
|
8003ea0: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8003ea2: 4b52 ldr r3, [pc, #328] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ea4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003ea6: 4a51 ldr r2, [pc, #324] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ea8: f043 0320 orr.w r3, r3, #32
|
|
8003eac: 6313 str r3, [r2, #48] ; 0x30
|
|
8003eae: 4b4f ldr r3, [pc, #316] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003eb0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003eb2: f003 0320 and.w r3, r3, #32
|
|
8003eb6: 617b str r3, [r7, #20]
|
|
8003eb8: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8003eba: 4b4c ldr r3, [pc, #304] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ebc: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003ebe: 4a4b ldr r2, [pc, #300] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ec0: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8003ec4: 6313 str r3, [r2, #48] ; 0x30
|
|
8003ec6: 4b49 ldr r3, [pc, #292] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ec8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003eca: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8003ece: 613b str r3, [r7, #16]
|
|
8003ed0: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8003ed2: 4b46 ldr r3, [pc, #280] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ed4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003ed6: 4a45 ldr r2, [pc, #276] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ed8: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8003edc: 6313 str r3, [r2, #48] ; 0x30
|
|
8003ede: 4b43 ldr r3, [pc, #268] ; (8003fec <BSP_SDRAM_MspInit+0x1cc>)
|
|
8003ee0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8003ee2: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
8003ee6: 60fb str r3, [r7, #12]
|
|
8003ee8: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Common GPIO configuration */
|
|
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
|
8003eea: 2302 movs r3, #2
|
|
8003eec: 633b str r3, [r7, #48] ; 0x30
|
|
gpio_init_structure.Pull = GPIO_PULLUP;
|
|
8003eee: 2301 movs r3, #1
|
|
8003ef0: 637b str r3, [r7, #52] ; 0x34
|
|
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
|
8003ef2: 2302 movs r3, #2
|
|
8003ef4: 63bb str r3, [r7, #56] ; 0x38
|
|
gpio_init_structure.Alternate = GPIO_AF12_FMC;
|
|
8003ef6: 230c movs r3, #12
|
|
8003ef8: 63fb str r3, [r7, #60] ; 0x3c
|
|
|
|
/* GPIOC configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_3;
|
|
8003efa: 2308 movs r3, #8
|
|
8003efc: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
|
|
8003efe: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f02: 4619 mov r1, r3
|
|
8003f04: 483a ldr r0, [pc, #232] ; (8003ff0 <BSP_SDRAM_MspInit+0x1d0>)
|
|
8003f06: f003 fe5b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOD configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
|
|
8003f0a: f24c 7303 movw r3, #50947 ; 0xc703
|
|
8003f0e: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
|
|
8003f10: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f14: 4619 mov r1, r3
|
|
8003f16: 4837 ldr r0, [pc, #220] ; (8003ff4 <BSP_SDRAM_MspInit+0x1d4>)
|
|
8003f18: f003 fe52 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOE configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
|
|
8003f1c: f64f 7383 movw r3, #65411 ; 0xff83
|
|
8003f20: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
|
8003f22: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f26: 4619 mov r1, r3
|
|
8003f28: 4833 ldr r0, [pc, #204] ; (8003ff8 <BSP_SDRAM_MspInit+0x1d8>)
|
|
8003f2a: f003 fe49 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOF configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
|
|
8003f2e: f64f 033f movw r3, #63551 ; 0xf83f
|
|
8003f32: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
|
|
8003f34: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f38: 4619 mov r1, r3
|
|
8003f3a: 4830 ldr r0, [pc, #192] ; (8003ffc <BSP_SDRAM_MspInit+0x1dc>)
|
|
8003f3c: f003 fe40 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOG configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
|
|
8003f40: f248 1333 movw r3, #33075 ; 0x8133
|
|
8003f44: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_PIN_15;
|
|
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
|
8003f46: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f4a: 4619 mov r1, r3
|
|
8003f4c: 482c ldr r0, [pc, #176] ; (8004000 <BSP_SDRAM_MspInit+0x1e0>)
|
|
8003f4e: f003 fe37 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* GPIOH configuration */
|
|
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
|
|
8003f52: 2328 movs r3, #40 ; 0x28
|
|
8003f54: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
|
|
8003f56: f107 032c add.w r3, r7, #44 ; 0x2c
|
|
8003f5a: 4619 mov r1, r3
|
|
8003f5c: 4829 ldr r0, [pc, #164] ; (8004004 <BSP_SDRAM_MspInit+0x1e4>)
|
|
8003f5e: f003 fe2f bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* Configure common DMA parameters */
|
|
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
|
|
8003f62: 4b29 ldr r3, [pc, #164] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f64: 2200 movs r2, #0
|
|
8003f66: 605a str r2, [r3, #4]
|
|
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
|
|
8003f68: 4b27 ldr r3, [pc, #156] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f6a: 2280 movs r2, #128 ; 0x80
|
|
8003f6c: 609a str r2, [r3, #8]
|
|
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
|
|
8003f6e: 4b26 ldr r3, [pc, #152] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f70: f44f 7200 mov.w r2, #512 ; 0x200
|
|
8003f74: 60da str r2, [r3, #12]
|
|
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
|
|
8003f76: 4b24 ldr r3, [pc, #144] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f78: f44f 6280 mov.w r2, #1024 ; 0x400
|
|
8003f7c: 611a str r2, [r3, #16]
|
|
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
|
8003f7e: 4b22 ldr r3, [pc, #136] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f80: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8003f84: 615a str r2, [r3, #20]
|
|
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
|
8003f86: 4b20 ldr r3, [pc, #128] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f88: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
8003f8c: 619a str r2, [r3, #24]
|
|
dma_handle.Init.Mode = DMA_NORMAL;
|
|
8003f8e: 4b1e ldr r3, [pc, #120] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f90: 2200 movs r2, #0
|
|
8003f92: 61da str r2, [r3, #28]
|
|
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
|
|
8003f94: 4b1c ldr r3, [pc, #112] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f96: f44f 3200 mov.w r2, #131072 ; 0x20000
|
|
8003f9a: 621a str r2, [r3, #32]
|
|
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
|
8003f9c: 4b1a ldr r3, [pc, #104] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003f9e: 2200 movs r2, #0
|
|
8003fa0: 625a str r2, [r3, #36] ; 0x24
|
|
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
|
8003fa2: 4b19 ldr r3, [pc, #100] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fa4: 2203 movs r2, #3
|
|
8003fa6: 629a str r2, [r3, #40] ; 0x28
|
|
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
|
|
8003fa8: 4b17 ldr r3, [pc, #92] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003faa: 2200 movs r2, #0
|
|
8003fac: 62da str r2, [r3, #44] ; 0x2c
|
|
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
|
8003fae: 4b16 ldr r3, [pc, #88] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fb0: 2200 movs r2, #0
|
|
8003fb2: 631a str r2, [r3, #48] ; 0x30
|
|
|
|
dma_handle.Instance = SDRAM_DMAx_STREAM;
|
|
8003fb4: 4b14 ldr r3, [pc, #80] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fb6: 4a15 ldr r2, [pc, #84] ; (800400c <BSP_SDRAM_MspInit+0x1ec>)
|
|
8003fb8: 601a str r2, [r3, #0]
|
|
|
|
/* Associate the DMA handle */
|
|
__HAL_LINKDMA(hsdram, hdma, dma_handle);
|
|
8003fba: 687b ldr r3, [r7, #4]
|
|
8003fbc: 4a12 ldr r2, [pc, #72] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fbe: 631a str r2, [r3, #48] ; 0x30
|
|
8003fc0: 4a11 ldr r2, [pc, #68] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fc2: 687b ldr r3, [r7, #4]
|
|
8003fc4: 6393 str r3, [r2, #56] ; 0x38
|
|
|
|
/* Deinitialize the stream for new transfer */
|
|
HAL_DMA_DeInit(&dma_handle);
|
|
8003fc6: 4810 ldr r0, [pc, #64] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fc8: f002 f8da bl 8006180 <HAL_DMA_DeInit>
|
|
|
|
/* Configure the DMA stream */
|
|
HAL_DMA_Init(&dma_handle);
|
|
8003fcc: 480e ldr r0, [pc, #56] ; (8004008 <BSP_SDRAM_MspInit+0x1e8>)
|
|
8003fce: f002 f829 bl 8006024 <HAL_DMA_Init>
|
|
|
|
/* NVIC configuration for DMA transfer complete interrupt */
|
|
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
|
|
8003fd2: 2200 movs r2, #0
|
|
8003fd4: 210f movs r1, #15
|
|
8003fd6: 2038 movs r0, #56 ; 0x38
|
|
8003fd8: f001 fe42 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
|
|
8003fdc: 2038 movs r0, #56 ; 0x38
|
|
8003fde: f001 fe5b bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8003fe2: bf00 nop
|
|
8003fe4: 3740 adds r7, #64 ; 0x40
|
|
8003fe6: 46bd mov sp, r7
|
|
8003fe8: bd80 pop {r7, pc}
|
|
8003fea: bf00 nop
|
|
8003fec: 40023800 .word 0x40023800
|
|
8003ff0: 40020800 .word 0x40020800
|
|
8003ff4: 40020c00 .word 0x40020c00
|
|
8003ff8: 40021000 .word 0x40021000
|
|
8003ffc: 40021400 .word 0x40021400
|
|
8004000: 40021800 .word 0x40021800
|
|
8004004: 40021c00 .word 0x40021c00
|
|
8004008: 200004e8 .word 0x200004e8
|
|
800400c: 40026410 .word 0x40026410
|
|
|
|
08004010 <BSP_TS_Init>:
|
|
* @param ts_SizeX: Maximum X size of the TS area on LCD
|
|
* @param ts_SizeY: Maximum Y size of the TS area on LCD
|
|
* @retval TS_OK if all initializations are OK. Other value if error.
|
|
*/
|
|
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
|
|
{
|
|
8004010: b580 push {r7, lr}
|
|
8004012: b084 sub sp, #16
|
|
8004014: af00 add r7, sp, #0
|
|
8004016: 4603 mov r3, r0
|
|
8004018: 460a mov r2, r1
|
|
800401a: 80fb strh r3, [r7, #6]
|
|
800401c: 4613 mov r3, r2
|
|
800401e: 80bb strh r3, [r7, #4]
|
|
uint8_t status = TS_OK;
|
|
8004020: 2300 movs r3, #0
|
|
8004022: 73fb strb r3, [r7, #15]
|
|
tsXBoundary = ts_SizeX;
|
|
8004024: 4a14 ldr r2, [pc, #80] ; (8004078 <BSP_TS_Init+0x68>)
|
|
8004026: 88fb ldrh r3, [r7, #6]
|
|
8004028: 8013 strh r3, [r2, #0]
|
|
tsYBoundary = ts_SizeY;
|
|
800402a: 4a14 ldr r2, [pc, #80] ; (800407c <BSP_TS_Init+0x6c>)
|
|
800402c: 88bb ldrh r3, [r7, #4]
|
|
800402e: 8013 strh r3, [r2, #0]
|
|
|
|
/* Read ID and verify if the touch screen driver is ready */
|
|
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
|
|
8004030: 4b13 ldr r3, [pc, #76] ; (8004080 <BSP_TS_Init+0x70>)
|
|
8004032: 681b ldr r3, [r3, #0]
|
|
8004034: 2070 movs r0, #112 ; 0x70
|
|
8004036: 4798 blx r3
|
|
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
|
|
8004038: 4b11 ldr r3, [pc, #68] ; (8004080 <BSP_TS_Init+0x70>)
|
|
800403a: 685b ldr r3, [r3, #4]
|
|
800403c: 2070 movs r0, #112 ; 0x70
|
|
800403e: 4798 blx r3
|
|
8004040: 4603 mov r3, r0
|
|
8004042: 2b51 cmp r3, #81 ; 0x51
|
|
8004044: d111 bne.n 800406a <BSP_TS_Init+0x5a>
|
|
{
|
|
/* Initialize the TS driver structure */
|
|
tsDriver = &ft5336_ts_drv;
|
|
8004046: 4b0f ldr r3, [pc, #60] ; (8004084 <BSP_TS_Init+0x74>)
|
|
8004048: 4a0d ldr r2, [pc, #52] ; (8004080 <BSP_TS_Init+0x70>)
|
|
800404a: 601a str r2, [r3, #0]
|
|
I2cAddress = TS_I2C_ADDRESS;
|
|
800404c: 4b0e ldr r3, [pc, #56] ; (8004088 <BSP_TS_Init+0x78>)
|
|
800404e: 2270 movs r2, #112 ; 0x70
|
|
8004050: 701a strb r2, [r3, #0]
|
|
tsOrientation = TS_SWAP_XY;
|
|
8004052: 4b0e ldr r3, [pc, #56] ; (800408c <BSP_TS_Init+0x7c>)
|
|
8004054: 2208 movs r2, #8
|
|
8004056: 701a strb r2, [r3, #0]
|
|
|
|
/* Initialize the TS driver */
|
|
tsDriver->Start(I2cAddress);
|
|
8004058: 4b0a ldr r3, [pc, #40] ; (8004084 <BSP_TS_Init+0x74>)
|
|
800405a: 681b ldr r3, [r3, #0]
|
|
800405c: 68db ldr r3, [r3, #12]
|
|
800405e: 4a0a ldr r2, [pc, #40] ; (8004088 <BSP_TS_Init+0x78>)
|
|
8004060: 7812 ldrb r2, [r2, #0]
|
|
8004062: b292 uxth r2, r2
|
|
8004064: 4610 mov r0, r2
|
|
8004066: 4798 blx r3
|
|
8004068: e001 b.n 800406e <BSP_TS_Init+0x5e>
|
|
}
|
|
else
|
|
{
|
|
status = TS_DEVICE_NOT_FOUND;
|
|
800406a: 2303 movs r3, #3
|
|
800406c: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
800406e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004070: 4618 mov r0, r3
|
|
8004072: 3710 adds r7, #16
|
|
8004074: 46bd mov sp, r7
|
|
8004076: bd80 pop {r7, pc}
|
|
8004078: 2000054c .word 0x2000054c
|
|
800407c: 2000054e .word 0x2000054e
|
|
8004080: 20000000 .word 0x20000000
|
|
8004084: 20000548 .word 0x20000548
|
|
8004088: 20000551 .word 0x20000551
|
|
800408c: 20000550 .word 0x20000550
|
|
|
|
08004090 <BSP_TS_GetState>:
|
|
* @brief Returns status and positions of the touch screen.
|
|
* @param TS_State: Pointer to touch screen current state structure
|
|
* @retval TS_OK if all initializations are OK. Other value if error.
|
|
*/
|
|
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
|
|
{
|
|
8004090: b590 push {r4, r7, lr}
|
|
8004092: b097 sub sp, #92 ; 0x5c
|
|
8004094: af02 add r7, sp, #8
|
|
8004096: 6078 str r0, [r7, #4]
|
|
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
|
|
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
|
|
uint8_t ts_status = TS_OK;
|
|
8004098: 2300 movs r3, #0
|
|
800409a: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
uint16_t brute_y[TS_MAX_NB_TOUCH];
|
|
uint16_t x_diff;
|
|
uint16_t y_diff;
|
|
uint32_t index;
|
|
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
|
uint32_t weight = 0;
|
|
800409e: 2300 movs r3, #0
|
|
80040a0: 613b str r3, [r7, #16]
|
|
uint32_t area = 0;
|
|
80040a2: 2300 movs r3, #0
|
|
80040a4: 60fb str r3, [r7, #12]
|
|
uint32_t event = 0;
|
|
80040a6: 2300 movs r3, #0
|
|
80040a8: 60bb str r3, [r7, #8]
|
|
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
|
|
|
/* Check and update the number of touches active detected */
|
|
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
|
|
80040aa: 4b97 ldr r3, [pc, #604] ; (8004308 <BSP_TS_GetState+0x278>)
|
|
80040ac: 681b ldr r3, [r3, #0]
|
|
80040ae: 691b ldr r3, [r3, #16]
|
|
80040b0: 4a96 ldr r2, [pc, #600] ; (800430c <BSP_TS_GetState+0x27c>)
|
|
80040b2: 7812 ldrb r2, [r2, #0]
|
|
80040b4: b292 uxth r2, r2
|
|
80040b6: 4610 mov r0, r2
|
|
80040b8: 4798 blx r3
|
|
80040ba: 4603 mov r3, r0
|
|
80040bc: 461a mov r2, r3
|
|
80040be: 687b ldr r3, [r7, #4]
|
|
80040c0: 701a strb r2, [r3, #0]
|
|
|
|
if(TS_State->touchDetected)
|
|
80040c2: 687b ldr r3, [r7, #4]
|
|
80040c4: 781b ldrb r3, [r3, #0]
|
|
80040c6: 2b00 cmp r3, #0
|
|
80040c8: f000 81a8 beq.w 800441c <BSP_TS_GetState+0x38c>
|
|
{
|
|
for(index=0; index < TS_State->touchDetected; index++)
|
|
80040cc: 2300 movs r3, #0
|
|
80040ce: 64bb str r3, [r7, #72] ; 0x48
|
|
80040d0: e197 b.n 8004402 <BSP_TS_GetState+0x372>
|
|
{
|
|
/* Get each touch coordinates */
|
|
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
|
|
80040d2: 4b8d ldr r3, [pc, #564] ; (8004308 <BSP_TS_GetState+0x278>)
|
|
80040d4: 681b ldr r3, [r3, #0]
|
|
80040d6: 695b ldr r3, [r3, #20]
|
|
80040d8: 4a8c ldr r2, [pc, #560] ; (800430c <BSP_TS_GetState+0x27c>)
|
|
80040da: 7812 ldrb r2, [r2, #0]
|
|
80040dc: b290 uxth r0, r2
|
|
80040de: f107 0120 add.w r1, r7, #32
|
|
80040e2: 6cba ldr r2, [r7, #72] ; 0x48
|
|
80040e4: 0052 lsls r2, r2, #1
|
|
80040e6: 188c adds r4, r1, r2
|
|
80040e8: f107 0114 add.w r1, r7, #20
|
|
80040ec: 6cba ldr r2, [r7, #72] ; 0x48
|
|
80040ee: 0052 lsls r2, r2, #1
|
|
80040f0: 440a add r2, r1
|
|
80040f2: 4621 mov r1, r4
|
|
80040f4: 4798 blx r3
|
|
|
|
if(tsOrientation == TS_SWAP_NONE)
|
|
80040f6: 4b86 ldr r3, [pc, #536] ; (8004310 <BSP_TS_GetState+0x280>)
|
|
80040f8: 781b ldrb r3, [r3, #0]
|
|
80040fa: 2b01 cmp r3, #1
|
|
80040fc: d11b bne.n 8004136 <BSP_TS_GetState+0xa6>
|
|
{
|
|
x[index] = brute_x[index];
|
|
80040fe: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004100: 005b lsls r3, r3, #1
|
|
8004102: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
8004106: 4413 add r3, r2
|
|
8004108: f833 2c30 ldrh.w r2, [r3, #-48]
|
|
800410c: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800410e: 005b lsls r3, r3, #1
|
|
8004110: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
8004114: 440b add r3, r1
|
|
8004116: f823 2c18 strh.w r2, [r3, #-24]
|
|
y[index] = brute_y[index];
|
|
800411a: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800411c: 005b lsls r3, r3, #1
|
|
800411e: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
8004122: 4413 add r3, r2
|
|
8004124: f833 2c3c ldrh.w r2, [r3, #-60]
|
|
8004128: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800412a: 005b lsls r3, r3, #1
|
|
800412c: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
8004130: 440b add r3, r1
|
|
8004132: f823 2c24 strh.w r2, [r3, #-36]
|
|
}
|
|
|
|
if(tsOrientation & TS_SWAP_X)
|
|
8004136: 4b76 ldr r3, [pc, #472] ; (8004310 <BSP_TS_GetState+0x280>)
|
|
8004138: 781b ldrb r3, [r3, #0]
|
|
800413a: f003 0302 and.w r3, r3, #2
|
|
800413e: 2b00 cmp r3, #0
|
|
8004140: d010 beq.n 8004164 <BSP_TS_GetState+0xd4>
|
|
{
|
|
x[index] = 4096 - brute_x[index];
|
|
8004142: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004144: 005b lsls r3, r3, #1
|
|
8004146: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
800414a: 4413 add r3, r2
|
|
800414c: f833 3c30 ldrh.w r3, [r3, #-48]
|
|
8004150: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
|
|
8004154: b29a uxth r2, r3
|
|
8004156: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004158: 005b lsls r3, r3, #1
|
|
800415a: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
800415e: 440b add r3, r1
|
|
8004160: f823 2c18 strh.w r2, [r3, #-24]
|
|
}
|
|
|
|
if(tsOrientation & TS_SWAP_Y)
|
|
8004164: 4b6a ldr r3, [pc, #424] ; (8004310 <BSP_TS_GetState+0x280>)
|
|
8004166: 781b ldrb r3, [r3, #0]
|
|
8004168: f003 0304 and.w r3, r3, #4
|
|
800416c: 2b00 cmp r3, #0
|
|
800416e: d010 beq.n 8004192 <BSP_TS_GetState+0x102>
|
|
{
|
|
y[index] = 4096 - brute_y[index];
|
|
8004170: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004172: 005b lsls r3, r3, #1
|
|
8004174: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
8004178: 4413 add r3, r2
|
|
800417a: f833 3c3c ldrh.w r3, [r3, #-60]
|
|
800417e: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
|
|
8004182: b29a uxth r2, r3
|
|
8004184: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004186: 005b lsls r3, r3, #1
|
|
8004188: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
800418c: 440b add r3, r1
|
|
800418e: f823 2c24 strh.w r2, [r3, #-36]
|
|
}
|
|
|
|
if(tsOrientation & TS_SWAP_XY)
|
|
8004192: 4b5f ldr r3, [pc, #380] ; (8004310 <BSP_TS_GetState+0x280>)
|
|
8004194: 781b ldrb r3, [r3, #0]
|
|
8004196: f003 0308 and.w r3, r3, #8
|
|
800419a: 2b00 cmp r3, #0
|
|
800419c: d01b beq.n 80041d6 <BSP_TS_GetState+0x146>
|
|
{
|
|
y[index] = brute_x[index];
|
|
800419e: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041a0: 005b lsls r3, r3, #1
|
|
80041a2: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80041a6: 4413 add r3, r2
|
|
80041a8: f833 2c30 ldrh.w r2, [r3, #-48]
|
|
80041ac: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041ae: 005b lsls r3, r3, #1
|
|
80041b0: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
80041b4: 440b add r3, r1
|
|
80041b6: f823 2c24 strh.w r2, [r3, #-36]
|
|
x[index] = brute_y[index];
|
|
80041ba: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041bc: 005b lsls r3, r3, #1
|
|
80041be: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80041c2: 4413 add r3, r2
|
|
80041c4: f833 2c3c ldrh.w r2, [r3, #-60]
|
|
80041c8: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041ca: 005b lsls r3, r3, #1
|
|
80041cc: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
80041d0: 440b add r3, r1
|
|
80041d2: f823 2c18 strh.w r2, [r3, #-24]
|
|
}
|
|
|
|
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
|
|
80041d6: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041d8: 005b lsls r3, r3, #1
|
|
80041da: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80041de: 4413 add r3, r2
|
|
80041e0: f833 3c18 ldrh.w r3, [r3, #-24]
|
|
80041e4: 4619 mov r1, r3
|
|
80041e6: 4a4b ldr r2, [pc, #300] ; (8004314 <BSP_TS_GetState+0x284>)
|
|
80041e8: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041ea: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80041ee: 4299 cmp r1, r3
|
|
80041f0: d90e bls.n 8004210 <BSP_TS_GetState+0x180>
|
|
80041f2: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80041f4: 005b lsls r3, r3, #1
|
|
80041f6: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80041fa: 4413 add r3, r2
|
|
80041fc: f833 2c18 ldrh.w r2, [r3, #-24]
|
|
8004200: 4944 ldr r1, [pc, #272] ; (8004314 <BSP_TS_GetState+0x284>)
|
|
8004202: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004204: f851 3023 ldr.w r3, [r1, r3, lsl #2]
|
|
8004208: b29b uxth r3, r3
|
|
800420a: 1ad3 subs r3, r2, r3
|
|
800420c: b29b uxth r3, r3
|
|
800420e: e00d b.n 800422c <BSP_TS_GetState+0x19c>
|
|
8004210: 4a40 ldr r2, [pc, #256] ; (8004314 <BSP_TS_GetState+0x284>)
|
|
8004212: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004214: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8004218: b29a uxth r2, r3
|
|
800421a: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800421c: 005b lsls r3, r3, #1
|
|
800421e: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
8004222: 440b add r3, r1
|
|
8004224: f833 3c18 ldrh.w r3, [r3, #-24]
|
|
8004228: 1ad3 subs r3, r2, r3
|
|
800422a: b29b uxth r3, r3
|
|
800422c: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
|
|
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
|
|
8004230: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004232: 005b lsls r3, r3, #1
|
|
8004234: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
8004238: 4413 add r3, r2
|
|
800423a: f833 3c24 ldrh.w r3, [r3, #-36]
|
|
800423e: 4619 mov r1, r3
|
|
8004240: 4a35 ldr r2, [pc, #212] ; (8004318 <BSP_TS_GetState+0x288>)
|
|
8004242: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004244: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8004248: 4299 cmp r1, r3
|
|
800424a: d90e bls.n 800426a <BSP_TS_GetState+0x1da>
|
|
800424c: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800424e: 005b lsls r3, r3, #1
|
|
8004250: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
8004254: 4413 add r3, r2
|
|
8004256: f833 2c24 ldrh.w r2, [r3, #-36]
|
|
800425a: 492f ldr r1, [pc, #188] ; (8004318 <BSP_TS_GetState+0x288>)
|
|
800425c: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800425e: f851 3023 ldr.w r3, [r1, r3, lsl #2]
|
|
8004262: b29b uxth r3, r3
|
|
8004264: 1ad3 subs r3, r2, r3
|
|
8004266: b29b uxth r3, r3
|
|
8004268: e00d b.n 8004286 <BSP_TS_GetState+0x1f6>
|
|
800426a: 4a2b ldr r2, [pc, #172] ; (8004318 <BSP_TS_GetState+0x288>)
|
|
800426c: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800426e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8004272: b29a uxth r2, r3
|
|
8004274: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004276: 005b lsls r3, r3, #1
|
|
8004278: f107 0150 add.w r1, r7, #80 ; 0x50
|
|
800427c: 440b add r3, r1
|
|
800427e: f833 3c24 ldrh.w r3, [r3, #-36]
|
|
8004282: 1ad3 subs r3, r2, r3
|
|
8004284: b29b uxth r3, r3
|
|
8004286: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
|
|
|
|
if ((x_diff + y_diff) > 5)
|
|
800428a: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
|
|
800428e: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
|
|
8004292: 4413 add r3, r2
|
|
8004294: 2b05 cmp r3, #5
|
|
8004296: dd17 ble.n 80042c8 <BSP_TS_GetState+0x238>
|
|
{
|
|
_x[index] = x[index];
|
|
8004298: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800429a: 005b lsls r3, r3, #1
|
|
800429c: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80042a0: 4413 add r3, r2
|
|
80042a2: f833 3c18 ldrh.w r3, [r3, #-24]
|
|
80042a6: 4619 mov r1, r3
|
|
80042a8: 4a1a ldr r2, [pc, #104] ; (8004314 <BSP_TS_GetState+0x284>)
|
|
80042aa: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042ac: f842 1023 str.w r1, [r2, r3, lsl #2]
|
|
_y[index] = y[index];
|
|
80042b0: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042b2: 005b lsls r3, r3, #1
|
|
80042b4: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80042b8: 4413 add r3, r2
|
|
80042ba: f833 3c24 ldrh.w r3, [r3, #-36]
|
|
80042be: 4619 mov r1, r3
|
|
80042c0: 4a15 ldr r2, [pc, #84] ; (8004318 <BSP_TS_GetState+0x288>)
|
|
80042c2: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042c4: f842 1023 str.w r1, [r2, r3, lsl #2]
|
|
}
|
|
|
|
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
|
|
80042c8: 4b10 ldr r3, [pc, #64] ; (800430c <BSP_TS_GetState+0x27c>)
|
|
80042ca: 781b ldrb r3, [r3, #0]
|
|
80042cc: 2b70 cmp r3, #112 ; 0x70
|
|
80042ce: d125 bne.n 800431c <BSP_TS_GetState+0x28c>
|
|
{
|
|
TS_State->touchX[index] = x[index];
|
|
80042d0: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042d2: 005b lsls r3, r3, #1
|
|
80042d4: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80042d8: 4413 add r3, r2
|
|
80042da: f833 1c18 ldrh.w r1, [r3, #-24]
|
|
80042de: 687a ldr r2, [r7, #4]
|
|
80042e0: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042e2: 005b lsls r3, r3, #1
|
|
80042e4: 4413 add r3, r2
|
|
80042e6: 460a mov r2, r1
|
|
80042e8: 805a strh r2, [r3, #2]
|
|
TS_State->touchY[index] = y[index];
|
|
80042ea: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042ec: 005b lsls r3, r3, #1
|
|
80042ee: f107 0250 add.w r2, r7, #80 ; 0x50
|
|
80042f2: 4413 add r3, r2
|
|
80042f4: f833 1c24 ldrh.w r1, [r3, #-36]
|
|
80042f8: 687a ldr r2, [r7, #4]
|
|
80042fa: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80042fc: 3304 adds r3, #4
|
|
80042fe: 005b lsls r3, r3, #1
|
|
8004300: 4413 add r3, r2
|
|
8004302: 460a mov r2, r1
|
|
8004304: 809a strh r2, [r3, #4]
|
|
8004306: e02c b.n 8004362 <BSP_TS_GetState+0x2d2>
|
|
8004308: 20000548 .word 0x20000548
|
|
800430c: 20000551 .word 0x20000551
|
|
8004310: 20000550 .word 0x20000550
|
|
8004314: 20000554 .word 0x20000554
|
|
8004318: 20000568 .word 0x20000568
|
|
}
|
|
else
|
|
{
|
|
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
|
|
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
|
|
800431c: 4b42 ldr r3, [pc, #264] ; (8004428 <BSP_TS_GetState+0x398>)
|
|
800431e: 881b ldrh r3, [r3, #0]
|
|
8004320: 4619 mov r1, r3
|
|
8004322: 4a42 ldr r2, [pc, #264] ; (800442c <BSP_TS_GetState+0x39c>)
|
|
8004324: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004326: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800432a: fb03 f301 mul.w r3, r3, r1
|
|
800432e: 0b1b lsrs r3, r3, #12
|
|
8004330: b299 uxth r1, r3
|
|
8004332: 687a ldr r2, [r7, #4]
|
|
8004334: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004336: 005b lsls r3, r3, #1
|
|
8004338: 4413 add r3, r2
|
|
800433a: 460a mov r2, r1
|
|
800433c: 805a strh r2, [r3, #2]
|
|
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
|
|
800433e: 4b3c ldr r3, [pc, #240] ; (8004430 <BSP_TS_GetState+0x3a0>)
|
|
8004340: 881b ldrh r3, [r3, #0]
|
|
8004342: 4619 mov r1, r3
|
|
8004344: 4a3b ldr r2, [pc, #236] ; (8004434 <BSP_TS_GetState+0x3a4>)
|
|
8004346: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004348: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800434c: fb03 f301 mul.w r3, r3, r1
|
|
8004350: 0b1b lsrs r3, r3, #12
|
|
8004352: b299 uxth r1, r3
|
|
8004354: 687a ldr r2, [r7, #4]
|
|
8004356: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004358: 3304 adds r3, #4
|
|
800435a: 005b lsls r3, r3, #1
|
|
800435c: 4413 add r3, r2
|
|
800435e: 460a mov r2, r1
|
|
8004360: 809a strh r2, [r3, #4]
|
|
}
|
|
|
|
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
|
|
|
/* Get touch info related to the current touch */
|
|
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
|
|
8004362: 4b35 ldr r3, [pc, #212] ; (8004438 <BSP_TS_GetState+0x3a8>)
|
|
8004364: 781b ldrb r3, [r3, #0]
|
|
8004366: b298 uxth r0, r3
|
|
8004368: f107 010c add.w r1, r7, #12
|
|
800436c: f107 0210 add.w r2, r7, #16
|
|
8004370: f107 0308 add.w r3, r7, #8
|
|
8004374: 9300 str r3, [sp, #0]
|
|
8004376: 460b mov r3, r1
|
|
8004378: 6cb9 ldr r1, [r7, #72] ; 0x48
|
|
800437a: f7fc fb17 bl 80009ac <ft5336_TS_GetTouchInfo>
|
|
|
|
/* Update TS_State structure */
|
|
TS_State->touchWeight[index] = weight;
|
|
800437e: 693b ldr r3, [r7, #16]
|
|
8004380: b2d9 uxtb r1, r3
|
|
8004382: 687a ldr r2, [r7, #4]
|
|
8004384: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004386: 4413 add r3, r2
|
|
8004388: 3316 adds r3, #22
|
|
800438a: 460a mov r2, r1
|
|
800438c: 701a strb r2, [r3, #0]
|
|
TS_State->touchArea[index] = area;
|
|
800438e: 68fb ldr r3, [r7, #12]
|
|
8004390: b2d9 uxtb r1, r3
|
|
8004392: 687a ldr r2, [r7, #4]
|
|
8004394: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
8004396: 4413 add r3, r2
|
|
8004398: 3320 adds r3, #32
|
|
800439a: 460a mov r2, r1
|
|
800439c: 701a strb r2, [r3, #0]
|
|
|
|
/* Remap touch event */
|
|
switch(event)
|
|
800439e: 68bb ldr r3, [r7, #8]
|
|
80043a0: 2b03 cmp r3, #3
|
|
80043a2: d827 bhi.n 80043f4 <BSP_TS_GetState+0x364>
|
|
80043a4: a201 add r2, pc, #4 ; (adr r2, 80043ac <BSP_TS_GetState+0x31c>)
|
|
80043a6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80043aa: bf00 nop
|
|
80043ac: 080043bd .word 0x080043bd
|
|
80043b0: 080043cb .word 0x080043cb
|
|
80043b4: 080043d9 .word 0x080043d9
|
|
80043b8: 080043e7 .word 0x080043e7
|
|
{
|
|
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
|
|
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
|
|
80043bc: 687a ldr r2, [r7, #4]
|
|
80043be: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80043c0: 4413 add r3, r2
|
|
80043c2: 331b adds r3, #27
|
|
80043c4: 2201 movs r2, #1
|
|
80043c6: 701a strb r2, [r3, #0]
|
|
break;
|
|
80043c8: e018 b.n 80043fc <BSP_TS_GetState+0x36c>
|
|
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
|
|
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
|
|
80043ca: 687a ldr r2, [r7, #4]
|
|
80043cc: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80043ce: 4413 add r3, r2
|
|
80043d0: 331b adds r3, #27
|
|
80043d2: 2202 movs r2, #2
|
|
80043d4: 701a strb r2, [r3, #0]
|
|
break;
|
|
80043d6: e011 b.n 80043fc <BSP_TS_GetState+0x36c>
|
|
case FT5336_TOUCH_EVT_FLAG_CONTACT :
|
|
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
|
|
80043d8: 687a ldr r2, [r7, #4]
|
|
80043da: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80043dc: 4413 add r3, r2
|
|
80043de: 331b adds r3, #27
|
|
80043e0: 2203 movs r2, #3
|
|
80043e2: 701a strb r2, [r3, #0]
|
|
break;
|
|
80043e4: e00a b.n 80043fc <BSP_TS_GetState+0x36c>
|
|
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
|
|
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
|
|
80043e6: 687a ldr r2, [r7, #4]
|
|
80043e8: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80043ea: 4413 add r3, r2
|
|
80043ec: 331b adds r3, #27
|
|
80043ee: 2200 movs r2, #0
|
|
80043f0: 701a strb r2, [r3, #0]
|
|
break;
|
|
80043f2: e003 b.n 80043fc <BSP_TS_GetState+0x36c>
|
|
default :
|
|
ts_status = TS_ERROR;
|
|
80043f4: 2301 movs r3, #1
|
|
80043f6: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
break;
|
|
80043fa: bf00 nop
|
|
for(index=0; index < TS_State->touchDetected; index++)
|
|
80043fc: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80043fe: 3301 adds r3, #1
|
|
8004400: 64bb str r3, [r7, #72] ; 0x48
|
|
8004402: 687b ldr r3, [r7, #4]
|
|
8004404: 781b ldrb r3, [r3, #0]
|
|
8004406: 461a mov r2, r3
|
|
8004408: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
800440a: 4293 cmp r3, r2
|
|
800440c: f4ff ae61 bcc.w 80040d2 <BSP_TS_GetState+0x42>
|
|
|
|
} /* of for(index=0; index < TS_State->touchDetected; index++) */
|
|
|
|
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
|
|
/* Get gesture Id */
|
|
ts_status = BSP_TS_Get_GestureId(TS_State);
|
|
8004410: 6878 ldr r0, [r7, #4]
|
|
8004412: f000 f813 bl 800443c <BSP_TS_Get_GestureId>
|
|
8004416: 4603 mov r3, r0
|
|
8004418: f887 304f strb.w r3, [r7, #79] ; 0x4f
|
|
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
|
|
|
|
} /* end of if(TS_State->touchDetected != 0) */
|
|
|
|
return (ts_status);
|
|
800441c: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
|
|
}
|
|
8004420: 4618 mov r0, r3
|
|
8004422: 3754 adds r7, #84 ; 0x54
|
|
8004424: 46bd mov sp, r7
|
|
8004426: bd90 pop {r4, r7, pc}
|
|
8004428: 2000054c .word 0x2000054c
|
|
800442c: 20000554 .word 0x20000554
|
|
8004430: 2000054e .word 0x2000054e
|
|
8004434: 20000568 .word 0x20000568
|
|
8004438: 20000551 .word 0x20000551
|
|
|
|
0800443c <BSP_TS_Get_GestureId>:
|
|
* @brief Update gesture Id following a touch detected.
|
|
* @param TS_State: Pointer to touch screen current state structure
|
|
* @retval TS_OK if all initializations are OK. Other value if error.
|
|
*/
|
|
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
|
|
{
|
|
800443c: b580 push {r7, lr}
|
|
800443e: b084 sub sp, #16
|
|
8004440: af00 add r7, sp, #0
|
|
8004442: 6078 str r0, [r7, #4]
|
|
uint32_t gestureId = 0;
|
|
8004444: 2300 movs r3, #0
|
|
8004446: 60bb str r3, [r7, #8]
|
|
uint8_t ts_status = TS_OK;
|
|
8004448: 2300 movs r3, #0
|
|
800444a: 73fb strb r3, [r7, #15]
|
|
|
|
/* Get gesture Id */
|
|
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
|
|
800444c: 4b1f ldr r3, [pc, #124] ; (80044cc <BSP_TS_Get_GestureId+0x90>)
|
|
800444e: 781b ldrb r3, [r3, #0]
|
|
8004450: b29b uxth r3, r3
|
|
8004452: f107 0208 add.w r2, r7, #8
|
|
8004456: 4611 mov r1, r2
|
|
8004458: 4618 mov r0, r3
|
|
800445a: f7fc fa8e bl 800097a <ft5336_TS_GetGestureID>
|
|
|
|
/* Remap gesture Id to a TS_GestureIdTypeDef value */
|
|
switch(gestureId)
|
|
800445e: 68bb ldr r3, [r7, #8]
|
|
8004460: 2b18 cmp r3, #24
|
|
8004462: d01b beq.n 800449c <BSP_TS_Get_GestureId+0x60>
|
|
8004464: 2b18 cmp r3, #24
|
|
8004466: d806 bhi.n 8004476 <BSP_TS_Get_GestureId+0x3a>
|
|
8004468: 2b10 cmp r3, #16
|
|
800446a: d00f beq.n 800448c <BSP_TS_Get_GestureId+0x50>
|
|
800446c: 2b14 cmp r3, #20
|
|
800446e: d011 beq.n 8004494 <BSP_TS_Get_GestureId+0x58>
|
|
8004470: 2b00 cmp r3, #0
|
|
8004472: d007 beq.n 8004484 <BSP_TS_Get_GestureId+0x48>
|
|
8004474: e022 b.n 80044bc <BSP_TS_Get_GestureId+0x80>
|
|
8004476: 2b40 cmp r3, #64 ; 0x40
|
|
8004478: d018 beq.n 80044ac <BSP_TS_Get_GestureId+0x70>
|
|
800447a: 2b49 cmp r3, #73 ; 0x49
|
|
800447c: d01a beq.n 80044b4 <BSP_TS_Get_GestureId+0x78>
|
|
800447e: 2b1c cmp r3, #28
|
|
8004480: d010 beq.n 80044a4 <BSP_TS_Get_GestureId+0x68>
|
|
8004482: e01b b.n 80044bc <BSP_TS_Get_GestureId+0x80>
|
|
{
|
|
case FT5336_GEST_ID_NO_GESTURE :
|
|
TS_State->gestureId = GEST_ID_NO_GESTURE;
|
|
8004484: 687b ldr r3, [r7, #4]
|
|
8004486: 2200 movs r2, #0
|
|
8004488: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
800448a: e01a b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_MOVE_UP :
|
|
TS_State->gestureId = GEST_ID_MOVE_UP;
|
|
800448c: 687b ldr r3, [r7, #4]
|
|
800448e: 2201 movs r2, #1
|
|
8004490: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
8004492: e016 b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_MOVE_RIGHT :
|
|
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
|
|
8004494: 687b ldr r3, [r7, #4]
|
|
8004496: 2202 movs r2, #2
|
|
8004498: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
800449a: e012 b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_MOVE_DOWN :
|
|
TS_State->gestureId = GEST_ID_MOVE_DOWN;
|
|
800449c: 687b ldr r3, [r7, #4]
|
|
800449e: 2203 movs r2, #3
|
|
80044a0: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
80044a2: e00e b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_MOVE_LEFT :
|
|
TS_State->gestureId = GEST_ID_MOVE_LEFT;
|
|
80044a4: 687b ldr r3, [r7, #4]
|
|
80044a6: 2204 movs r2, #4
|
|
80044a8: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
80044aa: e00a b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_ZOOM_IN :
|
|
TS_State->gestureId = GEST_ID_ZOOM_IN;
|
|
80044ac: 687b ldr r3, [r7, #4]
|
|
80044ae: 2205 movs r2, #5
|
|
80044b0: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
80044b2: e006 b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
case FT5336_GEST_ID_ZOOM_OUT :
|
|
TS_State->gestureId = GEST_ID_ZOOM_OUT;
|
|
80044b4: 687b ldr r3, [r7, #4]
|
|
80044b6: 2206 movs r2, #6
|
|
80044b8: 629a str r2, [r3, #40] ; 0x28
|
|
break;
|
|
80044ba: e002 b.n 80044c2 <BSP_TS_Get_GestureId+0x86>
|
|
default :
|
|
ts_status = TS_ERROR;
|
|
80044bc: 2301 movs r3, #1
|
|
80044be: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80044c0: bf00 nop
|
|
} /* of switch(gestureId) */
|
|
|
|
return(ts_status);
|
|
80044c2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80044c4: 4618 mov r0, r3
|
|
80044c6: 3710 adds r7, #16
|
|
80044c8: 46bd mov sp, r7
|
|
80044ca: bd80 pop {r7, pc}
|
|
80044cc: 20000551 .word 0x20000551
|
|
|
|
080044d0 <HAL_MspInit>:
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
80044d0: b580 push {r7, lr}
|
|
80044d2: b082 sub sp, #8
|
|
80044d4: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80044d6: 4b11 ldr r3, [pc, #68] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044d8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80044da: 4a10 ldr r2, [pc, #64] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044dc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
80044e0: 6413 str r3, [r2, #64] ; 0x40
|
|
80044e2: 4b0e ldr r3, [pc, #56] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044e4: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80044e6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
80044ea: 607b str r3, [r7, #4]
|
|
80044ec: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80044ee: 4b0b ldr r3, [pc, #44] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044f0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80044f2: 4a0a ldr r2, [pc, #40] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
|
|
80044f8: 6453 str r3, [r2, #68] ; 0x44
|
|
80044fa: 4b08 ldr r3, [pc, #32] ; (800451c <HAL_MspInit+0x4c>)
|
|
80044fc: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80044fe: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8004502: 603b str r3, [r7, #0]
|
|
8004504: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
/* PendSV_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
|
8004506: 2200 movs r2, #0
|
|
8004508: 210f movs r1, #15
|
|
800450a: f06f 0001 mvn.w r0, #1
|
|
800450e: f001 fba7 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8004512: bf00 nop
|
|
8004514: 3708 adds r7, #8
|
|
8004516: 46bd mov sp, r7
|
|
8004518: bd80 pop {r7, pc}
|
|
800451a: bf00 nop
|
|
800451c: 40023800 .word 0x40023800
|
|
|
|
08004520 <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8004520: b580 push {r7, lr}
|
|
8004522: b08c sub sp, #48 ; 0x30
|
|
8004524: af00 add r7, sp, #0
|
|
8004526: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004528: f107 031c add.w r3, r7, #28
|
|
800452c: 2200 movs r2, #0
|
|
800452e: 601a str r2, [r3, #0]
|
|
8004530: 605a str r2, [r3, #4]
|
|
8004532: 609a str r2, [r3, #8]
|
|
8004534: 60da str r2, [r3, #12]
|
|
8004536: 611a str r2, [r3, #16]
|
|
if(hadc->Instance==ADC1)
|
|
8004538: 687b ldr r3, [r7, #4]
|
|
800453a: 681b ldr r3, [r3, #0]
|
|
800453c: 4a2a ldr r2, [pc, #168] ; (80045e8 <HAL_ADC_MspInit+0xc8>)
|
|
800453e: 4293 cmp r3, r2
|
|
8004540: d124 bne.n 800458c <HAL_ADC_MspInit+0x6c>
|
|
{
|
|
/* USER CODE BEGIN ADC1_MspInit 0 */
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_ADC1_CLK_ENABLE();
|
|
8004542: 4b2a ldr r3, [pc, #168] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004544: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004546: 4a29 ldr r2, [pc, #164] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004548: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
800454c: 6453 str r3, [r2, #68] ; 0x44
|
|
800454e: 4b27 ldr r3, [pc, #156] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004550: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004552: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8004556: 61bb str r3, [r7, #24]
|
|
8004558: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800455a: 4b24 ldr r3, [pc, #144] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
800455c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800455e: 4a23 ldr r2, [pc, #140] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004560: f043 0301 orr.w r3, r3, #1
|
|
8004564: 6313 str r3, [r2, #48] ; 0x30
|
|
8004566: 4b21 ldr r3, [pc, #132] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004568: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800456a: f003 0301 and.w r3, r3, #1
|
|
800456e: 617b str r3, [r7, #20]
|
|
8004570: 697b ldr r3, [r7, #20]
|
|
/**ADC1 GPIO Configuration
|
|
PA0/WKUP ------> ADC1_IN0
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
|
8004572: 2301 movs r3, #1
|
|
8004574: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8004576: 2303 movs r3, #3
|
|
8004578: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800457a: 2300 movs r3, #0
|
|
800457c: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800457e: f107 031c add.w r3, r7, #28
|
|
8004582: 4619 mov r1, r3
|
|
8004584: 481a ldr r0, [pc, #104] ; (80045f0 <HAL_ADC_MspInit+0xd0>)
|
|
8004586: f003 fb1b bl 8007bc0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN ADC3_MspInit 1 */
|
|
|
|
/* USER CODE END ADC3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
800458a: e029 b.n 80045e0 <HAL_ADC_MspInit+0xc0>
|
|
else if(hadc->Instance==ADC3)
|
|
800458c: 687b ldr r3, [r7, #4]
|
|
800458e: 681b ldr r3, [r3, #0]
|
|
8004590: 4a18 ldr r2, [pc, #96] ; (80045f4 <HAL_ADC_MspInit+0xd4>)
|
|
8004592: 4293 cmp r3, r2
|
|
8004594: d124 bne.n 80045e0 <HAL_ADC_MspInit+0xc0>
|
|
__HAL_RCC_ADC3_CLK_ENABLE();
|
|
8004596: 4b15 ldr r3, [pc, #84] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
8004598: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800459a: 4a14 ldr r2, [pc, #80] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
800459c: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
80045a0: 6453 str r3, [r2, #68] ; 0x44
|
|
80045a2: 4b12 ldr r3, [pc, #72] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
80045a4: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80045a6: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80045aa: 613b str r3, [r7, #16]
|
|
80045ac: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
80045ae: 4b0f ldr r3, [pc, #60] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
80045b0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80045b2: 4a0e ldr r2, [pc, #56] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
80045b4: f043 0320 orr.w r3, r3, #32
|
|
80045b8: 6313 str r3, [r2, #48] ; 0x30
|
|
80045ba: 4b0c ldr r3, [pc, #48] ; (80045ec <HAL_ADC_MspInit+0xcc>)
|
|
80045bc: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80045be: f003 0320 and.w r3, r3, #32
|
|
80045c2: 60fb str r3, [r7, #12]
|
|
80045c4: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
|
|
80045c6: f44f 63e0 mov.w r3, #1792 ; 0x700
|
|
80045ca: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80045cc: 2303 movs r3, #3
|
|
80045ce: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80045d0: 2300 movs r3, #0
|
|
80045d2: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
80045d4: f107 031c add.w r3, r7, #28
|
|
80045d8: 4619 mov r1, r3
|
|
80045da: 4807 ldr r0, [pc, #28] ; (80045f8 <HAL_ADC_MspInit+0xd8>)
|
|
80045dc: f003 faf0 bl 8007bc0 <HAL_GPIO_Init>
|
|
}
|
|
80045e0: bf00 nop
|
|
80045e2: 3730 adds r7, #48 ; 0x30
|
|
80045e4: 46bd mov sp, r7
|
|
80045e6: bd80 pop {r7, pc}
|
|
80045e8: 40012000 .word 0x40012000
|
|
80045ec: 40023800 .word 0x40023800
|
|
80045f0: 40020000 .word 0x40020000
|
|
80045f4: 40012200 .word 0x40012200
|
|
80045f8: 40021400 .word 0x40021400
|
|
|
|
080045fc <HAL_CRC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hcrc: CRC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
|
|
{
|
|
80045fc: b480 push {r7}
|
|
80045fe: b085 sub sp, #20
|
|
8004600: af00 add r7, sp, #0
|
|
8004602: 6078 str r0, [r7, #4]
|
|
if(hcrc->Instance==CRC)
|
|
8004604: 687b ldr r3, [r7, #4]
|
|
8004606: 681b ldr r3, [r3, #0]
|
|
8004608: 4a0a ldr r2, [pc, #40] ; (8004634 <HAL_CRC_MspInit+0x38>)
|
|
800460a: 4293 cmp r3, r2
|
|
800460c: d10b bne.n 8004626 <HAL_CRC_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN CRC_MspInit 0 */
|
|
|
|
/* USER CODE END CRC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_CRC_CLK_ENABLE();
|
|
800460e: 4b0a ldr r3, [pc, #40] ; (8004638 <HAL_CRC_MspInit+0x3c>)
|
|
8004610: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004612: 4a09 ldr r2, [pc, #36] ; (8004638 <HAL_CRC_MspInit+0x3c>)
|
|
8004614: f443 5380 orr.w r3, r3, #4096 ; 0x1000
|
|
8004618: 6313 str r3, [r2, #48] ; 0x30
|
|
800461a: 4b07 ldr r3, [pc, #28] ; (8004638 <HAL_CRC_MspInit+0x3c>)
|
|
800461c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800461e: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
8004622: 60fb str r3, [r7, #12]
|
|
8004624: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN CRC_MspInit 1 */
|
|
|
|
/* USER CODE END CRC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004626: bf00 nop
|
|
8004628: 3714 adds r7, #20
|
|
800462a: 46bd mov sp, r7
|
|
800462c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004630: 4770 bx lr
|
|
8004632: bf00 nop
|
|
8004634: 40023000 .word 0x40023000
|
|
8004638: 40023800 .word 0x40023800
|
|
|
|
0800463c <HAL_DAC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdac: DAC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
|
|
{
|
|
800463c: b580 push {r7, lr}
|
|
800463e: b08a sub sp, #40 ; 0x28
|
|
8004640: af00 add r7, sp, #0
|
|
8004642: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004644: f107 0314 add.w r3, r7, #20
|
|
8004648: 2200 movs r2, #0
|
|
800464a: 601a str r2, [r3, #0]
|
|
800464c: 605a str r2, [r3, #4]
|
|
800464e: 609a str r2, [r3, #8]
|
|
8004650: 60da str r2, [r3, #12]
|
|
8004652: 611a str r2, [r3, #16]
|
|
if(hdac->Instance==DAC)
|
|
8004654: 687b ldr r3, [r7, #4]
|
|
8004656: 681b ldr r3, [r3, #0]
|
|
8004658: 4a19 ldr r2, [pc, #100] ; (80046c0 <HAL_DAC_MspInit+0x84>)
|
|
800465a: 4293 cmp r3, r2
|
|
800465c: d12b bne.n 80046b6 <HAL_DAC_MspInit+0x7a>
|
|
{
|
|
/* USER CODE BEGIN DAC_MspInit 0 */
|
|
|
|
/* USER CODE END DAC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DAC_CLK_ENABLE();
|
|
800465e: 4b19 ldr r3, [pc, #100] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
8004660: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004662: 4a18 ldr r2, [pc, #96] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
8004664: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
|
|
8004668: 6413 str r3, [r2, #64] ; 0x40
|
|
800466a: 4b16 ldr r3, [pc, #88] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
800466c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800466e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
8004672: 613b str r3, [r7, #16]
|
|
8004674: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8004676: 4b13 ldr r3, [pc, #76] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
8004678: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800467a: 4a12 ldr r2, [pc, #72] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
800467c: f043 0301 orr.w r3, r3, #1
|
|
8004680: 6313 str r3, [r2, #48] ; 0x30
|
|
8004682: 4b10 ldr r3, [pc, #64] ; (80046c4 <HAL_DAC_MspInit+0x88>)
|
|
8004684: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004686: f003 0301 and.w r3, r3, #1
|
|
800468a: 60fb str r3, [r7, #12]
|
|
800468c: 68fb ldr r3, [r7, #12]
|
|
/**DAC GPIO Configuration
|
|
PA4 ------> DAC_OUT1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
|
800468e: 2310 movs r3, #16
|
|
8004690: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8004692: 2303 movs r3, #3
|
|
8004694: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004696: 2300 movs r3, #0
|
|
8004698: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800469a: f107 0314 add.w r3, r7, #20
|
|
800469e: 4619 mov r1, r3
|
|
80046a0: 4809 ldr r0, [pc, #36] ; (80046c8 <HAL_DAC_MspInit+0x8c>)
|
|
80046a2: f003 fa8d bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* DAC interrupt Init */
|
|
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
|
|
80046a6: 2200 movs r2, #0
|
|
80046a8: 2100 movs r1, #0
|
|
80046aa: 2036 movs r0, #54 ; 0x36
|
|
80046ac: f001 fad8 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
|
80046b0: 2036 movs r0, #54 ; 0x36
|
|
80046b2: f001 faf1 bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN DAC_MspInit 1 */
|
|
|
|
/* USER CODE END DAC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
80046b6: bf00 nop
|
|
80046b8: 3728 adds r7, #40 ; 0x28
|
|
80046ba: 46bd mov sp, r7
|
|
80046bc: bd80 pop {r7, pc}
|
|
80046be: bf00 nop
|
|
80046c0: 40007400 .word 0x40007400
|
|
80046c4: 40023800 .word 0x40023800
|
|
80046c8: 40020000 .word 0x40020000
|
|
|
|
080046cc <HAL_DMA2D_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdma2d: DMA2D handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
|
|
{
|
|
80046cc: b480 push {r7}
|
|
80046ce: b085 sub sp, #20
|
|
80046d0: af00 add r7, sp, #0
|
|
80046d2: 6078 str r0, [r7, #4]
|
|
if(hdma2d->Instance==DMA2D)
|
|
80046d4: 687b ldr r3, [r7, #4]
|
|
80046d6: 681b ldr r3, [r3, #0]
|
|
80046d8: 4a0a ldr r2, [pc, #40] ; (8004704 <HAL_DMA2D_MspInit+0x38>)
|
|
80046da: 4293 cmp r3, r2
|
|
80046dc: d10b bne.n 80046f6 <HAL_DMA2D_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN DMA2D_MspInit 0 */
|
|
|
|
/* USER CODE END DMA2D_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DMA2D_CLK_ENABLE();
|
|
80046de: 4b0a ldr r3, [pc, #40] ; (8004708 <HAL_DMA2D_MspInit+0x3c>)
|
|
80046e0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80046e2: 4a09 ldr r2, [pc, #36] ; (8004708 <HAL_DMA2D_MspInit+0x3c>)
|
|
80046e4: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
80046e8: 6313 str r3, [r2, #48] ; 0x30
|
|
80046ea: 4b07 ldr r3, [pc, #28] ; (8004708 <HAL_DMA2D_MspInit+0x3c>)
|
|
80046ec: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80046ee: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
80046f2: 60fb str r3, [r7, #12]
|
|
80046f4: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN DMA2D_MspInit 1 */
|
|
|
|
/* USER CODE END DMA2D_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
80046f6: bf00 nop
|
|
80046f8: 3714 adds r7, #20
|
|
80046fa: 46bd mov sp, r7
|
|
80046fc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004700: 4770 bx lr
|
|
8004702: bf00 nop
|
|
8004704: 4002b000 .word 0x4002b000
|
|
8004708: 40023800 .word 0x40023800
|
|
|
|
0800470c <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
800470c: b580 push {r7, lr}
|
|
800470e: b08c sub sp, #48 ; 0x30
|
|
8004710: af00 add r7, sp, #0
|
|
8004712: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004714: f107 031c add.w r3, r7, #28
|
|
8004718: 2200 movs r2, #0
|
|
800471a: 601a str r2, [r3, #0]
|
|
800471c: 605a str r2, [r3, #4]
|
|
800471e: 609a str r2, [r3, #8]
|
|
8004720: 60da str r2, [r3, #12]
|
|
8004722: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C1)
|
|
8004724: 687b ldr r3, [r7, #4]
|
|
8004726: 681b ldr r3, [r3, #0]
|
|
8004728: 4a2f ldr r2, [pc, #188] ; (80047e8 <HAL_I2C_MspInit+0xdc>)
|
|
800472a: 4293 cmp r3, r2
|
|
800472c: d129 bne.n 8004782 <HAL_I2C_MspInit+0x76>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800472e: 4b2f ldr r3, [pc, #188] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
8004730: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004732: 4a2e ldr r2, [pc, #184] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
8004734: f043 0302 orr.w r3, r3, #2
|
|
8004738: 6313 str r3, [r2, #48] ; 0x30
|
|
800473a: 4b2c ldr r3, [pc, #176] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
800473c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800473e: f003 0302 and.w r3, r3, #2
|
|
8004742: 61bb str r3, [r7, #24]
|
|
8004744: 69bb ldr r3, [r7, #24]
|
|
/**I2C1 GPIO Configuration
|
|
PB8 ------> I2C1_SCL
|
|
PB9 ------> I2C1_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin;
|
|
8004746: f44f 7340 mov.w r3, #768 ; 0x300
|
|
800474a: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
800474c: 2312 movs r3, #18
|
|
800474e: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8004750: 2301 movs r3, #1
|
|
8004752: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004754: 2300 movs r3, #0
|
|
8004756: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
|
|
8004758: 2304 movs r3, #4
|
|
800475a: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800475c: f107 031c add.w r3, r7, #28
|
|
8004760: 4619 mov r1, r3
|
|
8004762: 4823 ldr r0, [pc, #140] ; (80047f0 <HAL_I2C_MspInit+0xe4>)
|
|
8004764: f003 fa2c bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C1_CLK_ENABLE();
|
|
8004768: 4b20 ldr r3, [pc, #128] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
800476a: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800476c: 4a1f ldr r2, [pc, #124] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
800476e: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
|
|
8004772: 6413 str r3, [r2, #64] ; 0x40
|
|
8004774: 4b1d ldr r3, [pc, #116] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
8004776: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004778: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
800477c: 617b str r3, [r7, #20]
|
|
800477e: 697b ldr r3, [r7, #20]
|
|
/* USER CODE BEGIN I2C3_MspInit 1 */
|
|
|
|
/* USER CODE END I2C3_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004780: e02d b.n 80047de <HAL_I2C_MspInit+0xd2>
|
|
else if(hi2c->Instance==I2C3)
|
|
8004782: 687b ldr r3, [r7, #4]
|
|
8004784: 681b ldr r3, [r3, #0]
|
|
8004786: 4a1b ldr r2, [pc, #108] ; (80047f4 <HAL_I2C_MspInit+0xe8>)
|
|
8004788: 4293 cmp r3, r2
|
|
800478a: d128 bne.n 80047de <HAL_I2C_MspInit+0xd2>
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
800478c: 4b17 ldr r3, [pc, #92] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
800478e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004790: 4a16 ldr r2, [pc, #88] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
8004792: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8004796: 6313 str r3, [r2, #48] ; 0x30
|
|
8004798: 4b14 ldr r3, [pc, #80] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
800479a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800479c: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
80047a0: 613b str r3, [r7, #16]
|
|
80047a2: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin;
|
|
80047a4: f44f 73c0 mov.w r3, #384 ; 0x180
|
|
80047a8: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
80047aa: 2312 movs r3, #18
|
|
80047ac: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
80047ae: 2301 movs r3, #1
|
|
80047b0: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80047b2: 2303 movs r3, #3
|
|
80047b4: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
|
|
80047b6: 2304 movs r3, #4
|
|
80047b8: 62fb str r3, [r7, #44] ; 0x2c
|
|
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
|
80047ba: f107 031c add.w r3, r7, #28
|
|
80047be: 4619 mov r1, r3
|
|
80047c0: 480d ldr r0, [pc, #52] ; (80047f8 <HAL_I2C_MspInit+0xec>)
|
|
80047c2: f003 f9fd bl 8007bc0 <HAL_GPIO_Init>
|
|
__HAL_RCC_I2C3_CLK_ENABLE();
|
|
80047c6: 4b09 ldr r3, [pc, #36] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
80047c8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80047ca: 4a08 ldr r2, [pc, #32] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
80047cc: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
80047d0: 6413 str r3, [r2, #64] ; 0x40
|
|
80047d2: 4b06 ldr r3, [pc, #24] ; (80047ec <HAL_I2C_MspInit+0xe0>)
|
|
80047d4: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80047d6: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
80047da: 60fb str r3, [r7, #12]
|
|
80047dc: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80047de: bf00 nop
|
|
80047e0: 3730 adds r7, #48 ; 0x30
|
|
80047e2: 46bd mov sp, r7
|
|
80047e4: bd80 pop {r7, pc}
|
|
80047e6: bf00 nop
|
|
80047e8: 40005400 .word 0x40005400
|
|
80047ec: 40023800 .word 0x40023800
|
|
80047f0: 40020400 .word 0x40020400
|
|
80047f4: 40005c00 .word 0x40005c00
|
|
80047f8: 40021c00 .word 0x40021c00
|
|
|
|
080047fc <HAL_I2C_MspDeInit>:
|
|
* This function freeze the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
80047fc: b580 push {r7, lr}
|
|
80047fe: b082 sub sp, #8
|
|
8004800: af00 add r7, sp, #0
|
|
8004802: 6078 str r0, [r7, #4]
|
|
if(hi2c->Instance==I2C1)
|
|
8004804: 687b ldr r3, [r7, #4]
|
|
8004806: 681b ldr r3, [r3, #0]
|
|
8004808: 4a15 ldr r2, [pc, #84] ; (8004860 <HAL_I2C_MspDeInit+0x64>)
|
|
800480a: 4293 cmp r3, r2
|
|
800480c: d110 bne.n 8004830 <HAL_I2C_MspDeInit+0x34>
|
|
{
|
|
/* USER CODE BEGIN I2C1_MspDeInit 0 */
|
|
|
|
/* USER CODE END I2C1_MspDeInit 0 */
|
|
/* Peripheral clock disable */
|
|
__HAL_RCC_I2C1_CLK_DISABLE();
|
|
800480e: 4b15 ldr r3, [pc, #84] ; (8004864 <HAL_I2C_MspDeInit+0x68>)
|
|
8004810: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004812: 4a14 ldr r2, [pc, #80] ; (8004864 <HAL_I2C_MspDeInit+0x68>)
|
|
8004814: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
|
|
8004818: 6413 str r3, [r2, #64] ; 0x40
|
|
|
|
/**I2C1 GPIO Configuration
|
|
PB8 ------> I2C1_SCL
|
|
PB9 ------> I2C1_SDA
|
|
*/
|
|
HAL_GPIO_DeInit(ARDUINO_SCL_D15_GPIO_Port, ARDUINO_SCL_D15_Pin);
|
|
800481a: f44f 7180 mov.w r1, #256 ; 0x100
|
|
800481e: 4812 ldr r0, [pc, #72] ; (8004868 <HAL_I2C_MspDeInit+0x6c>)
|
|
8004820: f003 fb78 bl 8007f14 <HAL_GPIO_DeInit>
|
|
|
|
HAL_GPIO_DeInit(ARDUINO_SDA_D14_GPIO_Port, ARDUINO_SDA_D14_Pin);
|
|
8004824: f44f 7100 mov.w r1, #512 ; 0x200
|
|
8004828: 480f ldr r0, [pc, #60] ; (8004868 <HAL_I2C_MspDeInit+0x6c>)
|
|
800482a: f003 fb73 bl 8007f14 <HAL_GPIO_DeInit>
|
|
/* USER CODE BEGIN I2C3_MspDeInit 1 */
|
|
|
|
/* USER CODE END I2C3_MspDeInit 1 */
|
|
}
|
|
|
|
}
|
|
800482e: e013 b.n 8004858 <HAL_I2C_MspDeInit+0x5c>
|
|
else if(hi2c->Instance==I2C3)
|
|
8004830: 687b ldr r3, [r7, #4]
|
|
8004832: 681b ldr r3, [r3, #0]
|
|
8004834: 4a0d ldr r2, [pc, #52] ; (800486c <HAL_I2C_MspDeInit+0x70>)
|
|
8004836: 4293 cmp r3, r2
|
|
8004838: d10e bne.n 8004858 <HAL_I2C_MspDeInit+0x5c>
|
|
__HAL_RCC_I2C3_CLK_DISABLE();
|
|
800483a: 4b0a ldr r3, [pc, #40] ; (8004864 <HAL_I2C_MspDeInit+0x68>)
|
|
800483c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800483e: 4a09 ldr r2, [pc, #36] ; (8004864 <HAL_I2C_MspDeInit+0x68>)
|
|
8004840: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
|
|
8004844: 6413 str r3, [r2, #64] ; 0x40
|
|
HAL_GPIO_DeInit(LCD_SCL_GPIO_Port, LCD_SCL_Pin);
|
|
8004846: 2180 movs r1, #128 ; 0x80
|
|
8004848: 4809 ldr r0, [pc, #36] ; (8004870 <HAL_I2C_MspDeInit+0x74>)
|
|
800484a: f003 fb63 bl 8007f14 <HAL_GPIO_DeInit>
|
|
HAL_GPIO_DeInit(LCD_SDA_GPIO_Port, LCD_SDA_Pin);
|
|
800484e: f44f 7180 mov.w r1, #256 ; 0x100
|
|
8004852: 4807 ldr r0, [pc, #28] ; (8004870 <HAL_I2C_MspDeInit+0x74>)
|
|
8004854: f003 fb5e bl 8007f14 <HAL_GPIO_DeInit>
|
|
}
|
|
8004858: bf00 nop
|
|
800485a: 3708 adds r7, #8
|
|
800485c: 46bd mov sp, r7
|
|
800485e: bd80 pop {r7, pc}
|
|
8004860: 40005400 .word 0x40005400
|
|
8004864: 40023800 .word 0x40023800
|
|
8004868: 40020400 .word 0x40020400
|
|
800486c: 40005c00 .word 0x40005c00
|
|
8004870: 40021c00 .word 0x40021c00
|
|
|
|
08004874 <HAL_LTDC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hltdc: LTDC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
|
|
{
|
|
8004874: b580 push {r7, lr}
|
|
8004876: b08e sub sp, #56 ; 0x38
|
|
8004878: af00 add r7, sp, #0
|
|
800487a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800487c: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004880: 2200 movs r2, #0
|
|
8004882: 601a str r2, [r3, #0]
|
|
8004884: 605a str r2, [r3, #4]
|
|
8004886: 609a str r2, [r3, #8]
|
|
8004888: 60da str r2, [r3, #12]
|
|
800488a: 611a str r2, [r3, #16]
|
|
if(hltdc->Instance==LTDC)
|
|
800488c: 687b ldr r3, [r7, #4]
|
|
800488e: 681b ldr r3, [r3, #0]
|
|
8004890: 4a55 ldr r2, [pc, #340] ; (80049e8 <HAL_LTDC_MspInit+0x174>)
|
|
8004892: 4293 cmp r3, r2
|
|
8004894: f040 80a3 bne.w 80049de <HAL_LTDC_MspInit+0x16a>
|
|
{
|
|
/* USER CODE BEGIN LTDC_MspInit 0 */
|
|
|
|
/* USER CODE END LTDC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_LTDC_CLK_ENABLE();
|
|
8004898: 4b54 ldr r3, [pc, #336] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
800489a: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800489c: 4a53 ldr r2, [pc, #332] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
800489e: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
80048a2: 6453 str r3, [r2, #68] ; 0x44
|
|
80048a4: 4b51 ldr r3, [pc, #324] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048a6: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80048a8: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
80048ac: 623b str r3, [r7, #32]
|
|
80048ae: 6a3b ldr r3, [r7, #32]
|
|
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
80048b0: 4b4e ldr r3, [pc, #312] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048b2: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048b4: 4a4d ldr r2, [pc, #308] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048b6: f043 0310 orr.w r3, r3, #16
|
|
80048ba: 6313 str r3, [r2, #48] ; 0x30
|
|
80048bc: 4b4b ldr r3, [pc, #300] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048be: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048c0: f003 0310 and.w r3, r3, #16
|
|
80048c4: 61fb str r3, [r7, #28]
|
|
80048c6: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
|
80048c8: 4b48 ldr r3, [pc, #288] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048ca: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048cc: 4a47 ldr r2, [pc, #284] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048ce: f443 7300 orr.w r3, r3, #512 ; 0x200
|
|
80048d2: 6313 str r3, [r2, #48] ; 0x30
|
|
80048d4: 4b45 ldr r3, [pc, #276] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048d6: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048d8: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
80048dc: 61bb str r3, [r7, #24]
|
|
80048de: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOK_CLK_ENABLE();
|
|
80048e0: 4b42 ldr r3, [pc, #264] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048e2: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048e4: 4a41 ldr r2, [pc, #260] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048e6: f443 6380 orr.w r3, r3, #1024 ; 0x400
|
|
80048ea: 6313 str r3, [r2, #48] ; 0x30
|
|
80048ec: 4b3f ldr r3, [pc, #252] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048ee: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048f0: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
80048f4: 617b str r3, [r7, #20]
|
|
80048f6: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
80048f8: 4b3c ldr r3, [pc, #240] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048fa: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80048fc: 4a3b ldr r2, [pc, #236] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
80048fe: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8004902: 6313 str r3, [r2, #48] ; 0x30
|
|
8004904: 4b39 ldr r3, [pc, #228] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
8004906: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004908: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800490c: 613b str r3, [r7, #16]
|
|
800490e: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
8004910: 4b36 ldr r3, [pc, #216] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
8004912: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004914: 4a35 ldr r2, [pc, #212] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
8004916: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
800491a: 6313 str r3, [r2, #48] ; 0x30
|
|
800491c: 4b33 ldr r3, [pc, #204] ; (80049ec <HAL_LTDC_MspInit+0x178>)
|
|
800491e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004920: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8004924: 60fb str r3, [r7, #12]
|
|
8004926: 68fb ldr r3, [r7, #12]
|
|
PJ3 ------> LTDC_R4
|
|
PJ2 ------> LTDC_R3
|
|
PJ0 ------> LTDC_R1
|
|
PJ1 ------> LTDC_R2
|
|
*/
|
|
GPIO_InitStruct.Pin = LCD_B0_Pin;
|
|
8004928: 2310 movs r3, #16
|
|
800492a: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800492c: 2302 movs r3, #2
|
|
800492e: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004930: 2300 movs r3, #0
|
|
8004932: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004934: 2300 movs r3, #0
|
|
8004936: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8004938: 230e movs r3, #14
|
|
800493a: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct);
|
|
800493c: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004940: 4619 mov r1, r3
|
|
8004942: 482b ldr r0, [pc, #172] ; (80049f0 <HAL_LTDC_MspInit+0x17c>)
|
|
8004944: f003 f93c bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin
|
|
8004948: f64e 73ff movw r3, #61439 ; 0xefff
|
|
800494c: 627b str r3, [r7, #36] ; 0x24
|
|
|LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin
|
|
|LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin
|
|
|LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800494e: 2302 movs r3, #2
|
|
8004950: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004952: 2300 movs r3, #0
|
|
8004954: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004956: 2300 movs r3, #0
|
|
8004958: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800495a: 230e movs r3, #14
|
|
800495c: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
|
|
800495e: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004962: 4619 mov r1, r3
|
|
8004964: 4823 ldr r0, [pc, #140] ; (80049f4 <HAL_LTDC_MspInit+0x180>)
|
|
8004966: f003 f92b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin
|
|
800496a: 23f7 movs r3, #247 ; 0xf7
|
|
800496c: 627b str r3, [r7, #36] ; 0x24
|
|
|LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800496e: 2302 movs r3, #2
|
|
8004970: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004972: 2300 movs r3, #0
|
|
8004974: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004976: 2300 movs r3, #0
|
|
8004978: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800497a: 230e movs r3, #14
|
|
800497c: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
|
|
800497e: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004982: 4619 mov r1, r3
|
|
8004984: 481c ldr r0, [pc, #112] ; (80049f8 <HAL_LTDC_MspInit+0x184>)
|
|
8004986: f003 f91b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = LCD_B4_Pin;
|
|
800498a: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800498e: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004990: 2302 movs r3, #2
|
|
8004992: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004994: 2300 movs r3, #0
|
|
8004996: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004998: 2300 movs r3, #0
|
|
800499a: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
|
|
800499c: 2309 movs r3, #9
|
|
800499e: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct);
|
|
80049a0: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
80049a4: 4619 mov r1, r3
|
|
80049a6: 4815 ldr r0, [pc, #84] ; (80049fc <HAL_LTDC_MspInit+0x188>)
|
|
80049a8: f003 f90a bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin;
|
|
80049ac: f44f 4346 mov.w r3, #50688 ; 0xc600
|
|
80049b0: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80049b2: 2302 movs r3, #2
|
|
80049b4: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80049b6: 2300 movs r3, #0
|
|
80049b8: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80049ba: 2300 movs r3, #0
|
|
80049bc: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
80049be: 230e movs r3, #14
|
|
80049c0: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
|
80049c2: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
80049c6: 4619 mov r1, r3
|
|
80049c8: 480d ldr r0, [pc, #52] ; (8004a00 <HAL_LTDC_MspInit+0x18c>)
|
|
80049ca: f003 f8f9 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* LTDC interrupt Init */
|
|
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
|
|
80049ce: 2200 movs r2, #0
|
|
80049d0: 2105 movs r1, #5
|
|
80049d2: 2058 movs r0, #88 ; 0x58
|
|
80049d4: f001 f944 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(LTDC_IRQn);
|
|
80049d8: 2058 movs r0, #88 ; 0x58
|
|
80049da: f001 f95d bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN LTDC_MspInit 1 */
|
|
|
|
/* USER CODE END LTDC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
80049de: bf00 nop
|
|
80049e0: 3738 adds r7, #56 ; 0x38
|
|
80049e2: 46bd mov sp, r7
|
|
80049e4: bd80 pop {r7, pc}
|
|
80049e6: bf00 nop
|
|
80049e8: 40016800 .word 0x40016800
|
|
80049ec: 40023800 .word 0x40023800
|
|
80049f0: 40021000 .word 0x40021000
|
|
80049f4: 40022400 .word 0x40022400
|
|
80049f8: 40022800 .word 0x40022800
|
|
80049fc: 40021800 .word 0x40021800
|
|
8004a00: 40022000 .word 0x40022000
|
|
|
|
08004a04 <HAL_RNG_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hrng: RNG handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
|
|
{
|
|
8004a04: b480 push {r7}
|
|
8004a06: b085 sub sp, #20
|
|
8004a08: af00 add r7, sp, #0
|
|
8004a0a: 6078 str r0, [r7, #4]
|
|
if(hrng->Instance==RNG)
|
|
8004a0c: 687b ldr r3, [r7, #4]
|
|
8004a0e: 681b ldr r3, [r3, #0]
|
|
8004a10: 4a0a ldr r2, [pc, #40] ; (8004a3c <HAL_RNG_MspInit+0x38>)
|
|
8004a12: 4293 cmp r3, r2
|
|
8004a14: d10b bne.n 8004a2e <HAL_RNG_MspInit+0x2a>
|
|
{
|
|
/* USER CODE BEGIN RNG_MspInit 0 */
|
|
|
|
/* USER CODE END RNG_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_RNG_CLK_ENABLE();
|
|
8004a16: 4b0a ldr r3, [pc, #40] ; (8004a40 <HAL_RNG_MspInit+0x3c>)
|
|
8004a18: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8004a1a: 4a09 ldr r2, [pc, #36] ; (8004a40 <HAL_RNG_MspInit+0x3c>)
|
|
8004a1c: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
8004a20: 6353 str r3, [r2, #52] ; 0x34
|
|
8004a22: 4b07 ldr r3, [pc, #28] ; (8004a40 <HAL_RNG_MspInit+0x3c>)
|
|
8004a24: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8004a26: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8004a2a: 60fb str r3, [r7, #12]
|
|
8004a2c: 68fb ldr r3, [r7, #12]
|
|
/* USER CODE BEGIN RNG_MspInit 1 */
|
|
|
|
/* USER CODE END RNG_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004a2e: bf00 nop
|
|
8004a30: 3714 adds r7, #20
|
|
8004a32: 46bd mov sp, r7
|
|
8004a34: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a38: 4770 bx lr
|
|
8004a3a: bf00 nop
|
|
8004a3c: 50060800 .word 0x50060800
|
|
8004a40: 40023800 .word 0x40023800
|
|
|
|
08004a44 <HAL_RTC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hrtc: RTC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
|
|
{
|
|
8004a44: b480 push {r7}
|
|
8004a46: b083 sub sp, #12
|
|
8004a48: af00 add r7, sp, #0
|
|
8004a4a: 6078 str r0, [r7, #4]
|
|
if(hrtc->Instance==RTC)
|
|
8004a4c: 687b ldr r3, [r7, #4]
|
|
8004a4e: 681b ldr r3, [r3, #0]
|
|
8004a50: 4a07 ldr r2, [pc, #28] ; (8004a70 <HAL_RTC_MspInit+0x2c>)
|
|
8004a52: 4293 cmp r3, r2
|
|
8004a54: d105 bne.n 8004a62 <HAL_RTC_MspInit+0x1e>
|
|
{
|
|
/* USER CODE BEGIN RTC_MspInit 0 */
|
|
|
|
/* USER CODE END RTC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_RTC_ENABLE();
|
|
8004a56: 4b07 ldr r3, [pc, #28] ; (8004a74 <HAL_RTC_MspInit+0x30>)
|
|
8004a58: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8004a5a: 4a06 ldr r2, [pc, #24] ; (8004a74 <HAL_RTC_MspInit+0x30>)
|
|
8004a5c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
|
|
8004a60: 6713 str r3, [r2, #112] ; 0x70
|
|
/* USER CODE BEGIN RTC_MspInit 1 */
|
|
|
|
/* USER CODE END RTC_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004a62: bf00 nop
|
|
8004a64: 370c adds r7, #12
|
|
8004a66: 46bd mov sp, r7
|
|
8004a68: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004a6c: 4770 bx lr
|
|
8004a6e: bf00 nop
|
|
8004a70: 40002800 .word 0x40002800
|
|
8004a74: 40023800 .word 0x40023800
|
|
|
|
08004a78 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
8004a78: b580 push {r7, lr}
|
|
8004a7a: b08a sub sp, #40 ; 0x28
|
|
8004a7c: af00 add r7, sp, #0
|
|
8004a7e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004a80: f107 0314 add.w r3, r7, #20
|
|
8004a84: 2200 movs r2, #0
|
|
8004a86: 601a str r2, [r3, #0]
|
|
8004a88: 605a str r2, [r3, #4]
|
|
8004a8a: 609a str r2, [r3, #8]
|
|
8004a8c: 60da str r2, [r3, #12]
|
|
8004a8e: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI2)
|
|
8004a90: 687b ldr r3, [r7, #4]
|
|
8004a92: 681b ldr r3, [r3, #0]
|
|
8004a94: 4a2d ldr r2, [pc, #180] ; (8004b4c <HAL_SPI_MspInit+0xd4>)
|
|
8004a96: 4293 cmp r3, r2
|
|
8004a98: d154 bne.n 8004b44 <HAL_SPI_MspInit+0xcc>
|
|
{
|
|
/* USER CODE BEGIN SPI2_MspInit 0 */
|
|
|
|
/* USER CODE END SPI2_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI2_CLK_ENABLE();
|
|
8004a9a: 4b2d ldr r3, [pc, #180] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004a9c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004a9e: 4a2c ldr r2, [pc, #176] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004aa0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
|
|
8004aa4: 6413 str r3, [r2, #64] ; 0x40
|
|
8004aa6: 4b2a ldr r3, [pc, #168] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004aa8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004aaa: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8004aae: 613b str r3, [r7, #16]
|
|
8004ab0: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
8004ab2: 4b27 ldr r3, [pc, #156] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004ab4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004ab6: 4a26 ldr r2, [pc, #152] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004ab8: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8004abc: 6313 str r3, [r2, #48] ; 0x30
|
|
8004abe: 4b24 ldr r3, [pc, #144] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004ac0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004ac2: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8004ac6: 60fb str r3, [r7, #12]
|
|
8004ac8: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8004aca: 4b21 ldr r3, [pc, #132] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004acc: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004ace: 4a20 ldr r2, [pc, #128] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004ad0: f043 0302 orr.w r3, r3, #2
|
|
8004ad4: 6313 str r3, [r2, #48] ; 0x30
|
|
8004ad6: 4b1e ldr r3, [pc, #120] ; (8004b50 <HAL_SPI_MspInit+0xd8>)
|
|
8004ad8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004ada: f003 0302 and.w r3, r3, #2
|
|
8004ade: 60bb str r3, [r7, #8]
|
|
8004ae0: 68bb ldr r3, [r7, #8]
|
|
PI1 ------> SPI2_SCK
|
|
PI0 ------> SPI2_NSS
|
|
PB14 ------> SPI2_MISO
|
|
PB15 ------> SPI2_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
|
|
8004ae2: 2302 movs r3, #2
|
|
8004ae4: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004ae6: 2302 movs r3, #2
|
|
8004ae8: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004aea: 2300 movs r3, #0
|
|
8004aec: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004aee: 2300 movs r3, #0
|
|
8004af0: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
8004af2: 2305 movs r3, #5
|
|
8004af4: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
|
|
8004af6: f107 0314 add.w r3, r7, #20
|
|
8004afa: 4619 mov r1, r3
|
|
8004afc: 4815 ldr r0, [pc, #84] ; (8004b54 <HAL_SPI_MspInit+0xdc>)
|
|
8004afe: f003 f85f bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
|
8004b02: 2301 movs r3, #1
|
|
8004b04: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004b06: 2302 movs r3, #2
|
|
8004b08: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004b0a: 2300 movs r3, #0
|
|
8004b0c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004b0e: 2303 movs r3, #3
|
|
8004b10: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
8004b12: 2305 movs r3, #5
|
|
8004b14: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
|
8004b16: f107 0314 add.w r3, r7, #20
|
|
8004b1a: 4619 mov r1, r3
|
|
8004b1c: 480d ldr r0, [pc, #52] ; (8004b54 <HAL_SPI_MspInit+0xdc>)
|
|
8004b1e: f003 f84f bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
|
|
8004b22: f44f 4340 mov.w r3, #49152 ; 0xc000
|
|
8004b26: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004b28: 2302 movs r3, #2
|
|
8004b2a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004b2c: 2300 movs r3, #0
|
|
8004b2e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004b30: 2303 movs r3, #3
|
|
8004b32: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
|
|
8004b34: 2305 movs r3, #5
|
|
8004b36: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8004b38: f107 0314 add.w r3, r7, #20
|
|
8004b3c: 4619 mov r1, r3
|
|
8004b3e: 4806 ldr r0, [pc, #24] ; (8004b58 <HAL_SPI_MspInit+0xe0>)
|
|
8004b40: f003 f83e bl 8007bc0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN SPI2_MspInit 1 */
|
|
|
|
/* USER CODE END SPI2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004b44: bf00 nop
|
|
8004b46: 3728 adds r7, #40 ; 0x28
|
|
8004b48: 46bd mov sp, r7
|
|
8004b4a: bd80 pop {r7, pc}
|
|
8004b4c: 40003800 .word 0x40003800
|
|
8004b50: 40023800 .word 0x40023800
|
|
8004b54: 40022000 .word 0x40022000
|
|
8004b58: 40020400 .word 0x40020400
|
|
|
|
08004b5c <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8004b5c: b480 push {r7}
|
|
8004b5e: b089 sub sp, #36 ; 0x24
|
|
8004b60: af00 add r7, sp, #0
|
|
8004b62: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM1)
|
|
8004b64: 687b ldr r3, [r7, #4]
|
|
8004b66: 681b ldr r3, [r3, #0]
|
|
8004b68: 4a2e ldr r2, [pc, #184] ; (8004c24 <HAL_TIM_Base_MspInit+0xc8>)
|
|
8004b6a: 4293 cmp r3, r2
|
|
8004b6c: d10c bne.n 8004b88 <HAL_TIM_Base_MspInit+0x2c>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
8004b6e: 4b2e ldr r3, [pc, #184] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004b70: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004b72: 4a2d ldr r2, [pc, #180] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004b74: f043 0301 orr.w r3, r3, #1
|
|
8004b78: 6453 str r3, [r2, #68] ; 0x44
|
|
8004b7a: 4b2b ldr r3, [pc, #172] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004b7c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004b7e: f003 0301 and.w r3, r3, #1
|
|
8004b82: 61fb str r3, [r7, #28]
|
|
8004b84: 69fb ldr r3, [r7, #28]
|
|
/* USER CODE BEGIN TIM8_MspInit 1 */
|
|
|
|
/* USER CODE END TIM8_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004b86: e046 b.n 8004c16 <HAL_TIM_Base_MspInit+0xba>
|
|
else if(htim_base->Instance==TIM2)
|
|
8004b88: 687b ldr r3, [r7, #4]
|
|
8004b8a: 681b ldr r3, [r3, #0]
|
|
8004b8c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8004b90: d10c bne.n 8004bac <HAL_TIM_Base_MspInit+0x50>
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
8004b92: 4b25 ldr r3, [pc, #148] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004b94: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004b96: 4a24 ldr r2, [pc, #144] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004b98: f043 0301 orr.w r3, r3, #1
|
|
8004b9c: 6413 str r3, [r2, #64] ; 0x40
|
|
8004b9e: 4b22 ldr r3, [pc, #136] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004ba0: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004ba2: f003 0301 and.w r3, r3, #1
|
|
8004ba6: 61bb str r3, [r7, #24]
|
|
8004ba8: 69bb ldr r3, [r7, #24]
|
|
}
|
|
8004baa: e034 b.n 8004c16 <HAL_TIM_Base_MspInit+0xba>
|
|
else if(htim_base->Instance==TIM3)
|
|
8004bac: 687b ldr r3, [r7, #4]
|
|
8004bae: 681b ldr r3, [r3, #0]
|
|
8004bb0: 4a1e ldr r2, [pc, #120] ; (8004c2c <HAL_TIM_Base_MspInit+0xd0>)
|
|
8004bb2: 4293 cmp r3, r2
|
|
8004bb4: d10c bne.n 8004bd0 <HAL_TIM_Base_MspInit+0x74>
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
8004bb6: 4b1c ldr r3, [pc, #112] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004bb8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004bba: 4a1b ldr r2, [pc, #108] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004bbc: f043 0302 orr.w r3, r3, #2
|
|
8004bc0: 6413 str r3, [r2, #64] ; 0x40
|
|
8004bc2: 4b19 ldr r3, [pc, #100] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004bc4: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004bc6: f003 0302 and.w r3, r3, #2
|
|
8004bca: 617b str r3, [r7, #20]
|
|
8004bcc: 697b ldr r3, [r7, #20]
|
|
}
|
|
8004bce: e022 b.n 8004c16 <HAL_TIM_Base_MspInit+0xba>
|
|
else if(htim_base->Instance==TIM5)
|
|
8004bd0: 687b ldr r3, [r7, #4]
|
|
8004bd2: 681b ldr r3, [r3, #0]
|
|
8004bd4: 4a16 ldr r2, [pc, #88] ; (8004c30 <HAL_TIM_Base_MspInit+0xd4>)
|
|
8004bd6: 4293 cmp r3, r2
|
|
8004bd8: d10c bne.n 8004bf4 <HAL_TIM_Base_MspInit+0x98>
|
|
__HAL_RCC_TIM5_CLK_ENABLE();
|
|
8004bda: 4b13 ldr r3, [pc, #76] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004bdc: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004bde: 4a12 ldr r2, [pc, #72] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004be0: f043 0308 orr.w r3, r3, #8
|
|
8004be4: 6413 str r3, [r2, #64] ; 0x40
|
|
8004be6: 4b10 ldr r3, [pc, #64] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004be8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004bea: f003 0308 and.w r3, r3, #8
|
|
8004bee: 613b str r3, [r7, #16]
|
|
8004bf0: 693b ldr r3, [r7, #16]
|
|
}
|
|
8004bf2: e010 b.n 8004c16 <HAL_TIM_Base_MspInit+0xba>
|
|
else if(htim_base->Instance==TIM8)
|
|
8004bf4: 687b ldr r3, [r7, #4]
|
|
8004bf6: 681b ldr r3, [r3, #0]
|
|
8004bf8: 4a0e ldr r2, [pc, #56] ; (8004c34 <HAL_TIM_Base_MspInit+0xd8>)
|
|
8004bfa: 4293 cmp r3, r2
|
|
8004bfc: d10b bne.n 8004c16 <HAL_TIM_Base_MspInit+0xba>
|
|
__HAL_RCC_TIM8_CLK_ENABLE();
|
|
8004bfe: 4b0a ldr r3, [pc, #40] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004c00: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004c02: 4a09 ldr r2, [pc, #36] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004c04: f043 0302 orr.w r3, r3, #2
|
|
8004c08: 6453 str r3, [r2, #68] ; 0x44
|
|
8004c0a: 4b07 ldr r3, [pc, #28] ; (8004c28 <HAL_TIM_Base_MspInit+0xcc>)
|
|
8004c0c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004c0e: f003 0302 and.w r3, r3, #2
|
|
8004c12: 60fb str r3, [r7, #12]
|
|
8004c14: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8004c16: bf00 nop
|
|
8004c18: 3724 adds r7, #36 ; 0x24
|
|
8004c1a: 46bd mov sp, r7
|
|
8004c1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c20: 4770 bx lr
|
|
8004c22: bf00 nop
|
|
8004c24: 40010000 .word 0x40010000
|
|
8004c28: 40023800 .word 0x40023800
|
|
8004c2c: 40000400 .word 0x40000400
|
|
8004c30: 40000c00 .word 0x40000c00
|
|
8004c34: 40010400 .word 0x40010400
|
|
|
|
08004c38 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
8004c38: b580 push {r7, lr}
|
|
8004c3a: b08a sub sp, #40 ; 0x28
|
|
8004c3c: af00 add r7, sp, #0
|
|
8004c3e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004c40: f107 0314 add.w r3, r7, #20
|
|
8004c44: 2200 movs r2, #0
|
|
8004c46: 601a str r2, [r3, #0]
|
|
8004c48: 605a str r2, [r3, #4]
|
|
8004c4a: 609a str r2, [r3, #8]
|
|
8004c4c: 60da str r2, [r3, #12]
|
|
8004c4e: 611a str r2, [r3, #16]
|
|
if(htim->Instance==TIM3)
|
|
8004c50: 687b ldr r3, [r7, #4]
|
|
8004c52: 681b ldr r3, [r3, #0]
|
|
8004c54: 4a22 ldr r2, [pc, #136] ; (8004ce0 <HAL_TIM_MspPostInit+0xa8>)
|
|
8004c56: 4293 cmp r3, r2
|
|
8004c58: d11c bne.n 8004c94 <HAL_TIM_MspPostInit+0x5c>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspPostInit 0 */
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8004c5a: 4b22 ldr r3, [pc, #136] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004c5c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004c5e: 4a21 ldr r2, [pc, #132] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004c60: f043 0302 orr.w r3, r3, #2
|
|
8004c64: 6313 str r3, [r2, #48] ; 0x30
|
|
8004c66: 4b1f ldr r3, [pc, #124] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004c68: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004c6a: f003 0302 and.w r3, r3, #2
|
|
8004c6e: 613b str r3, [r7, #16]
|
|
8004c70: 693b ldr r3, [r7, #16]
|
|
/**TIM3 GPIO Configuration
|
|
PB4 ------> TIM3_CH1
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
|
8004c72: 2310 movs r3, #16
|
|
8004c74: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004c76: 2302 movs r3, #2
|
|
8004c78: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004c7a: 2300 movs r3, #0
|
|
8004c7c: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004c7e: 2300 movs r3, #0
|
|
8004c80: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
|
|
8004c82: 2302 movs r3, #2
|
|
8004c84: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8004c86: f107 0314 add.w r3, r7, #20
|
|
8004c8a: 4619 mov r1, r3
|
|
8004c8c: 4816 ldr r0, [pc, #88] ; (8004ce8 <HAL_TIM_MspPostInit+0xb0>)
|
|
8004c8e: f002 ff97 bl 8007bc0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM8_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM8_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
8004c92: e020 b.n 8004cd6 <HAL_TIM_MspPostInit+0x9e>
|
|
else if(htim->Instance==TIM8)
|
|
8004c94: 687b ldr r3, [r7, #4]
|
|
8004c96: 681b ldr r3, [r3, #0]
|
|
8004c98: 4a14 ldr r2, [pc, #80] ; (8004cec <HAL_TIM_MspPostInit+0xb4>)
|
|
8004c9a: 4293 cmp r3, r2
|
|
8004c9c: d11b bne.n 8004cd6 <HAL_TIM_MspPostInit+0x9e>
|
|
__HAL_RCC_GPIOI_CLK_ENABLE();
|
|
8004c9e: 4b11 ldr r3, [pc, #68] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004ca0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004ca2: 4a10 ldr r2, [pc, #64] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004ca4: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8004ca8: 6313 str r3, [r2, #48] ; 0x30
|
|
8004caa: 4b0e ldr r3, [pc, #56] ; (8004ce4 <HAL_TIM_MspPostInit+0xac>)
|
|
8004cac: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004cae: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8004cb2: 60fb str r3, [r7, #12]
|
|
8004cb4: 68fb ldr r3, [r7, #12]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_2;
|
|
8004cb6: 2304 movs r3, #4
|
|
8004cb8: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004cba: 2302 movs r3, #2
|
|
8004cbc: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004cbe: 2300 movs r3, #0
|
|
8004cc0: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004cc2: 2300 movs r3, #0
|
|
8004cc4: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
|
|
8004cc6: 2303 movs r3, #3
|
|
8004cc8: 627b str r3, [r7, #36] ; 0x24
|
|
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
|
8004cca: f107 0314 add.w r3, r7, #20
|
|
8004cce: 4619 mov r1, r3
|
|
8004cd0: 4807 ldr r0, [pc, #28] ; (8004cf0 <HAL_TIM_MspPostInit+0xb8>)
|
|
8004cd2: f002 ff75 bl 8007bc0 <HAL_GPIO_Init>
|
|
}
|
|
8004cd6: bf00 nop
|
|
8004cd8: 3728 adds r7, #40 ; 0x28
|
|
8004cda: 46bd mov sp, r7
|
|
8004cdc: bd80 pop {r7, pc}
|
|
8004cde: bf00 nop
|
|
8004ce0: 40000400 .word 0x40000400
|
|
8004ce4: 40023800 .word 0x40023800
|
|
8004ce8: 40020400 .word 0x40020400
|
|
8004cec: 40010400 .word 0x40010400
|
|
8004cf0: 40022000 .word 0x40022000
|
|
|
|
08004cf4 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8004cf4: b580 push {r7, lr}
|
|
8004cf6: b08e sub sp, #56 ; 0x38
|
|
8004cf8: af00 add r7, sp, #0
|
|
8004cfa: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8004cfc: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004d00: 2200 movs r2, #0
|
|
8004d02: 601a str r2, [r3, #0]
|
|
8004d04: 605a str r2, [r3, #4]
|
|
8004d06: 609a str r2, [r3, #8]
|
|
8004d08: 60da str r2, [r3, #12]
|
|
8004d0a: 611a str r2, [r3, #16]
|
|
if(huart->Instance==UART7)
|
|
8004d0c: 687b ldr r3, [r7, #4]
|
|
8004d0e: 681b ldr r3, [r3, #0]
|
|
8004d10: 4a53 ldr r2, [pc, #332] ; (8004e60 <HAL_UART_MspInit+0x16c>)
|
|
8004d12: 4293 cmp r3, r2
|
|
8004d14: d128 bne.n 8004d68 <HAL_UART_MspInit+0x74>
|
|
{
|
|
/* USER CODE BEGIN UART7_MspInit 0 */
|
|
|
|
/* USER CODE END UART7_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_UART7_CLK_ENABLE();
|
|
8004d16: 4b53 ldr r3, [pc, #332] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d18: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004d1a: 4a52 ldr r2, [pc, #328] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d1c: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
|
|
8004d20: 6413 str r3, [r2, #64] ; 0x40
|
|
8004d22: 4b50 ldr r3, [pc, #320] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d24: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004d26: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
|
|
8004d2a: 623b str r3, [r7, #32]
|
|
8004d2c: 6a3b ldr r3, [r7, #32]
|
|
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8004d2e: 4b4d ldr r3, [pc, #308] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d30: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004d32: 4a4c ldr r2, [pc, #304] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d34: f043 0320 orr.w r3, r3, #32
|
|
8004d38: 6313 str r3, [r2, #48] ; 0x30
|
|
8004d3a: 4b4a ldr r3, [pc, #296] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d3c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004d3e: f003 0320 and.w r3, r3, #32
|
|
8004d42: 61fb str r3, [r7, #28]
|
|
8004d44: 69fb ldr r3, [r7, #28]
|
|
/**UART7 GPIO Configuration
|
|
PF7 ------> UART7_TX
|
|
PF6 ------> UART7_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
|
|
8004d46: 23c0 movs r3, #192 ; 0xc0
|
|
8004d48: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004d4a: 2302 movs r3, #2
|
|
8004d4c: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004d4e: 2300 movs r3, #0
|
|
8004d50: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004d52: 2303 movs r3, #3
|
|
8004d54: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
|
|
8004d56: 2308 movs r3, #8
|
|
8004d58: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
8004d5a: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004d5e: 4619 mov r1, r3
|
|
8004d60: 4841 ldr r0, [pc, #260] ; (8004e68 <HAL_UART_MspInit+0x174>)
|
|
8004d62: f002 ff2d bl 8007bc0 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART6_MspInit 1 */
|
|
|
|
/* USER CODE END USART6_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8004d66: e077 b.n 8004e58 <HAL_UART_MspInit+0x164>
|
|
else if(huart->Instance==USART1)
|
|
8004d68: 687b ldr r3, [r7, #4]
|
|
8004d6a: 681b ldr r3, [r3, #0]
|
|
8004d6c: 4a3f ldr r2, [pc, #252] ; (8004e6c <HAL_UART_MspInit+0x178>)
|
|
8004d6e: 4293 cmp r3, r2
|
|
8004d70: d145 bne.n 8004dfe <HAL_UART_MspInit+0x10a>
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8004d72: 4b3c ldr r3, [pc, #240] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d74: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004d76: 4a3b ldr r2, [pc, #236] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d78: f043 0310 orr.w r3, r3, #16
|
|
8004d7c: 6453 str r3, [r2, #68] ; 0x44
|
|
8004d7e: 4b39 ldr r3, [pc, #228] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d80: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004d82: f003 0310 and.w r3, r3, #16
|
|
8004d86: 61bb str r3, [r7, #24]
|
|
8004d88: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8004d8a: 4b36 ldr r3, [pc, #216] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d8c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004d8e: 4a35 ldr r2, [pc, #212] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d90: f043 0302 orr.w r3, r3, #2
|
|
8004d94: 6313 str r3, [r2, #48] ; 0x30
|
|
8004d96: 4b33 ldr r3, [pc, #204] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004d98: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004d9a: f003 0302 and.w r3, r3, #2
|
|
8004d9e: 617b str r3, [r7, #20]
|
|
8004da0: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8004da2: 4b30 ldr r3, [pc, #192] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004da4: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004da6: 4a2f ldr r2, [pc, #188] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004da8: f043 0301 orr.w r3, r3, #1
|
|
8004dac: 6313 str r3, [r2, #48] ; 0x30
|
|
8004dae: 4b2d ldr r3, [pc, #180] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004db0: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004db2: f003 0301 and.w r3, r3, #1
|
|
8004db6: 613b str r3, [r7, #16]
|
|
8004db8: 693b ldr r3, [r7, #16]
|
|
GPIO_InitStruct.Pin = VCP_RX_Pin;
|
|
8004dba: 2380 movs r3, #128 ; 0x80
|
|
8004dbc: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004dbe: 2302 movs r3, #2
|
|
8004dc0: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004dc2: 2300 movs r3, #0
|
|
8004dc4: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004dc6: 2300 movs r3, #0
|
|
8004dc8: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8004dca: 2307 movs r3, #7
|
|
8004dcc: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
|
|
8004dce: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004dd2: 4619 mov r1, r3
|
|
8004dd4: 4826 ldr r0, [pc, #152] ; (8004e70 <HAL_UART_MspInit+0x17c>)
|
|
8004dd6: f002 fef3 bl 8007bc0 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = VCP_TX_Pin;
|
|
8004dda: f44f 7300 mov.w r3, #512 ; 0x200
|
|
8004dde: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004de0: 2302 movs r3, #2
|
|
8004de2: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004de4: 2300 movs r3, #0
|
|
8004de6: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8004de8: 2300 movs r3, #0
|
|
8004dea: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
8004dec: 2307 movs r3, #7
|
|
8004dee: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
|
|
8004df0: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004df4: 4619 mov r1, r3
|
|
8004df6: 481f ldr r0, [pc, #124] ; (8004e74 <HAL_UART_MspInit+0x180>)
|
|
8004df8: f002 fee2 bl 8007bc0 <HAL_GPIO_Init>
|
|
}
|
|
8004dfc: e02c b.n 8004e58 <HAL_UART_MspInit+0x164>
|
|
else if(huart->Instance==USART6)
|
|
8004dfe: 687b ldr r3, [r7, #4]
|
|
8004e00: 681b ldr r3, [r3, #0]
|
|
8004e02: 4a1d ldr r2, [pc, #116] ; (8004e78 <HAL_UART_MspInit+0x184>)
|
|
8004e04: 4293 cmp r3, r2
|
|
8004e06: d127 bne.n 8004e58 <HAL_UART_MspInit+0x164>
|
|
__HAL_RCC_USART6_CLK_ENABLE();
|
|
8004e08: 4b16 ldr r3, [pc, #88] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e0a: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004e0c: 4a15 ldr r2, [pc, #84] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e0e: f043 0320 orr.w r3, r3, #32
|
|
8004e12: 6453 str r3, [r2, #68] ; 0x44
|
|
8004e14: 4b13 ldr r3, [pc, #76] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e16: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8004e18: f003 0320 and.w r3, r3, #32
|
|
8004e1c: 60fb str r3, [r7, #12]
|
|
8004e1e: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8004e20: 4b10 ldr r3, [pc, #64] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e22: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004e24: 4a0f ldr r2, [pc, #60] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e26: f043 0304 orr.w r3, r3, #4
|
|
8004e2a: 6313 str r3, [r2, #48] ; 0x30
|
|
8004e2c: 4b0d ldr r3, [pc, #52] ; (8004e64 <HAL_UART_MspInit+0x170>)
|
|
8004e2e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8004e30: f003 0304 and.w r3, r3, #4
|
|
8004e34: 60bb str r3, [r7, #8]
|
|
8004e36: 68bb ldr r3, [r7, #8]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
|
|
8004e38: 23c0 movs r3, #192 ; 0xc0
|
|
8004e3a: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004e3c: 2302 movs r3, #2
|
|
8004e3e: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004e40: 2300 movs r3, #0
|
|
8004e42: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004e44: 2303 movs r3, #3
|
|
8004e46: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
|
|
8004e48: 2308 movs r3, #8
|
|
8004e4a: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8004e4c: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
8004e50: 4619 mov r1, r3
|
|
8004e52: 480a ldr r0, [pc, #40] ; (8004e7c <HAL_UART_MspInit+0x188>)
|
|
8004e54: f002 feb4 bl 8007bc0 <HAL_GPIO_Init>
|
|
}
|
|
8004e58: bf00 nop
|
|
8004e5a: 3738 adds r7, #56 ; 0x38
|
|
8004e5c: 46bd mov sp, r7
|
|
8004e5e: bd80 pop {r7, pc}
|
|
8004e60: 40007800 .word 0x40007800
|
|
8004e64: 40023800 .word 0x40023800
|
|
8004e68: 40021400 .word 0x40021400
|
|
8004e6c: 40011000 .word 0x40011000
|
|
8004e70: 40020400 .word 0x40020400
|
|
8004e74: 40020000 .word 0x40020000
|
|
8004e78: 40011400 .word 0x40011400
|
|
8004e7c: 40020800 .word 0x40020800
|
|
|
|
08004e80 <HAL_FMC_MspInit>:
|
|
|
|
}
|
|
|
|
static uint32_t FMC_Initialized = 0;
|
|
|
|
static void HAL_FMC_MspInit(void){
|
|
8004e80: b580 push {r7, lr}
|
|
8004e82: b086 sub sp, #24
|
|
8004e84: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN FMC_MspInit 0 */
|
|
|
|
/* USER CODE END FMC_MspInit 0 */
|
|
GPIO_InitTypeDef GPIO_InitStruct ={0};
|
|
8004e86: 1d3b adds r3, r7, #4
|
|
8004e88: 2200 movs r2, #0
|
|
8004e8a: 601a str r2, [r3, #0]
|
|
8004e8c: 605a str r2, [r3, #4]
|
|
8004e8e: 609a str r2, [r3, #8]
|
|
8004e90: 60da str r2, [r3, #12]
|
|
8004e92: 611a str r2, [r3, #16]
|
|
if (FMC_Initialized) {
|
|
8004e94: 4b3a ldr r3, [pc, #232] ; (8004f80 <HAL_FMC_MspInit+0x100>)
|
|
8004e96: 681b ldr r3, [r3, #0]
|
|
8004e98: 2b00 cmp r3, #0
|
|
8004e9a: d16d bne.n 8004f78 <HAL_FMC_MspInit+0xf8>
|
|
return;
|
|
}
|
|
FMC_Initialized = 1;
|
|
8004e9c: 4b38 ldr r3, [pc, #224] ; (8004f80 <HAL_FMC_MspInit+0x100>)
|
|
8004e9e: 2201 movs r2, #1
|
|
8004ea0: 601a str r2, [r3, #0]
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_FMC_CLK_ENABLE();
|
|
8004ea2: 4b38 ldr r3, [pc, #224] ; (8004f84 <HAL_FMC_MspInit+0x104>)
|
|
8004ea4: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8004ea6: 4a37 ldr r2, [pc, #220] ; (8004f84 <HAL_FMC_MspInit+0x104>)
|
|
8004ea8: f043 0301 orr.w r3, r3, #1
|
|
8004eac: 6393 str r3, [r2, #56] ; 0x38
|
|
8004eae: 4b35 ldr r3, [pc, #212] ; (8004f84 <HAL_FMC_MspInit+0x104>)
|
|
8004eb0: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8004eb2: f003 0301 and.w r3, r3, #1
|
|
8004eb6: 603b str r3, [r7, #0]
|
|
8004eb8: 683b ldr r3, [r7, #0]
|
|
PE10 ------> FMC_D7
|
|
PE12 ------> FMC_D9
|
|
PE15 ------> FMC_D12
|
|
PE13 ------> FMC_D10
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
|
|
8004eba: f64f 7383 movw r3, #65411 ; 0xff83
|
|
8004ebe: 607b str r3, [r7, #4]
|
|
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|
|
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004ec0: 2302 movs r3, #2
|
|
8004ec2: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004ec4: 2300 movs r3, #0
|
|
8004ec6: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004ec8: 2303 movs r3, #3
|
|
8004eca: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004ecc: 230c movs r3, #12
|
|
8004ece: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8004ed0: 1d3b adds r3, r7, #4
|
|
8004ed2: 4619 mov r1, r3
|
|
8004ed4: 482c ldr r0, [pc, #176] ; (8004f88 <HAL_FMC_MspInit+0x108>)
|
|
8004ed6: f002 fe73 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
|
|
8004eda: f248 1333 movw r3, #33075 ; 0x8133
|
|
8004ede: 607b str r3, [r7, #4]
|
|
|GPIO_PIN_5|GPIO_PIN_4;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004ee0: 2302 movs r3, #2
|
|
8004ee2: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004ee4: 2300 movs r3, #0
|
|
8004ee6: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004ee8: 2303 movs r3, #3
|
|
8004eea: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004eec: 230c movs r3, #12
|
|
8004eee: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8004ef0: 1d3b adds r3, r7, #4
|
|
8004ef2: 4619 mov r1, r3
|
|
8004ef4: 4825 ldr r0, [pc, #148] ; (8004f8c <HAL_FMC_MspInit+0x10c>)
|
|
8004ef6: f002 fe63 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
|
|
8004efa: f24c 7303 movw r3, #50947 ; 0xc703
|
|
8004efe: 607b str r3, [r7, #4]
|
|
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004f00: 2302 movs r3, #2
|
|
8004f02: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004f04: 2300 movs r3, #0
|
|
8004f06: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004f08: 2303 movs r3, #3
|
|
8004f0a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004f0c: 230c movs r3, #12
|
|
8004f0e: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8004f10: 1d3b adds r3, r7, #4
|
|
8004f12: 4619 mov r1, r3
|
|
8004f14: 481e ldr r0, [pc, #120] ; (8004f90 <HAL_FMC_MspInit+0x110>)
|
|
8004f16: f002 fe53 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
|
8004f1a: f64f 033f movw r3, #63551 ; 0xf83f
|
|
8004f1e: 607b str r3, [r7, #4]
|
|
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|
|
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004f20: 2302 movs r3, #2
|
|
8004f22: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004f24: 2300 movs r3, #0
|
|
8004f26: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004f28: 2303 movs r3, #3
|
|
8004f2a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004f2c: 230c movs r3, #12
|
|
8004f2e: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
8004f30: 1d3b adds r3, r7, #4
|
|
8004f32: 4619 mov r1, r3
|
|
8004f34: 4817 ldr r0, [pc, #92] ; (8004f94 <HAL_FMC_MspInit+0x114>)
|
|
8004f36: f002 fe43 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
|
|
8004f3a: 2328 movs r3, #40 ; 0x28
|
|
8004f3c: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004f3e: 2302 movs r3, #2
|
|
8004f40: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004f42: 2300 movs r3, #0
|
|
8004f44: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004f46: 2303 movs r3, #3
|
|
8004f48: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004f4a: 230c movs r3, #12
|
|
8004f4c: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
|
8004f4e: 1d3b adds r3, r7, #4
|
|
8004f50: 4619 mov r1, r3
|
|
8004f52: 4811 ldr r0, [pc, #68] ; (8004f98 <HAL_FMC_MspInit+0x118>)
|
|
8004f54: f002 fe34 bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_3;
|
|
8004f58: 2308 movs r3, #8
|
|
8004f5a: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8004f5c: 2302 movs r3, #2
|
|
8004f5e: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8004f60: 2300 movs r3, #0
|
|
8004f62: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8004f64: 2303 movs r3, #3
|
|
8004f66: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8004f68: 230c movs r3, #12
|
|
8004f6a: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8004f6c: 1d3b adds r3, r7, #4
|
|
8004f6e: 4619 mov r1, r3
|
|
8004f70: 480a ldr r0, [pc, #40] ; (8004f9c <HAL_FMC_MspInit+0x11c>)
|
|
8004f72: f002 fe25 bl 8007bc0 <HAL_GPIO_Init>
|
|
8004f76: e000 b.n 8004f7a <HAL_FMC_MspInit+0xfa>
|
|
return;
|
|
8004f78: bf00 nop
|
|
|
|
/* USER CODE BEGIN FMC_MspInit 1 */
|
|
|
|
/* USER CODE END FMC_MspInit 1 */
|
|
}
|
|
8004f7a: 3718 adds r7, #24
|
|
8004f7c: 46bd mov sp, r7
|
|
8004f7e: bd80 pop {r7, pc}
|
|
8004f80: 2000057c .word 0x2000057c
|
|
8004f84: 40023800 .word 0x40023800
|
|
8004f88: 40021000 .word 0x40021000
|
|
8004f8c: 40021800 .word 0x40021800
|
|
8004f90: 40020c00 .word 0x40020c00
|
|
8004f94: 40021400 .word 0x40021400
|
|
8004f98: 40021c00 .word 0x40021c00
|
|
8004f9c: 40020800 .word 0x40020800
|
|
|
|
08004fa0 <HAL_SDRAM_MspInit>:
|
|
|
|
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
|
|
8004fa0: b580 push {r7, lr}
|
|
8004fa2: b082 sub sp, #8
|
|
8004fa4: af00 add r7, sp, #0
|
|
8004fa6: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN SDRAM_MspInit 0 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 0 */
|
|
HAL_FMC_MspInit();
|
|
8004fa8: f7ff ff6a bl 8004e80 <HAL_FMC_MspInit>
|
|
/* USER CODE BEGIN SDRAM_MspInit 1 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 1 */
|
|
}
|
|
8004fac: bf00 nop
|
|
8004fae: 3708 adds r7, #8
|
|
8004fb0: 46bd mov sp, r7
|
|
8004fb2: bd80 pop {r7, pc}
|
|
|
|
08004fb4 <HAL_InitTick>:
|
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8004fb4: b580 push {r7, lr}
|
|
8004fb6: b08c sub sp, #48 ; 0x30
|
|
8004fb8: af00 add r7, sp, #0
|
|
8004fba: 6078 str r0, [r7, #4]
|
|
RCC_ClkInitTypeDef clkconfig;
|
|
uint32_t uwTimclock = 0;
|
|
8004fbc: 2300 movs r3, #0
|
|
8004fbe: 62fb str r3, [r7, #44] ; 0x2c
|
|
uint32_t uwPrescalerValue = 0;
|
|
8004fc0: 2300 movs r3, #0
|
|
8004fc2: 62bb str r3, [r7, #40] ; 0x28
|
|
uint32_t pFLatency;
|
|
/*Configure the TIM6 IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
|
|
8004fc4: 2200 movs r2, #0
|
|
8004fc6: 6879 ldr r1, [r7, #4]
|
|
8004fc8: 2036 movs r0, #54 ; 0x36
|
|
8004fca: f000 fe49 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
|
|
/* Enable the TIM6 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
|
8004fce: 2036 movs r0, #54 ; 0x36
|
|
8004fd0: f000 fe62 bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
/* Enable TIM6 clock */
|
|
__HAL_RCC_TIM6_CLK_ENABLE();
|
|
8004fd4: 4b1f ldr r3, [pc, #124] ; (8005054 <HAL_InitTick+0xa0>)
|
|
8004fd6: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004fd8: 4a1e ldr r2, [pc, #120] ; (8005054 <HAL_InitTick+0xa0>)
|
|
8004fda: f043 0310 orr.w r3, r3, #16
|
|
8004fde: 6413 str r3, [r2, #64] ; 0x40
|
|
8004fe0: 4b1c ldr r3, [pc, #112] ; (8005054 <HAL_InitTick+0xa0>)
|
|
8004fe2: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8004fe4: f003 0310 and.w r3, r3, #16
|
|
8004fe8: 60fb str r3, [r7, #12]
|
|
8004fea: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Get clock configuration */
|
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
|
8004fec: f107 0210 add.w r2, r7, #16
|
|
8004ff0: f107 0314 add.w r3, r7, #20
|
|
8004ff4: 4611 mov r1, r2
|
|
8004ff6: 4618 mov r0, r3
|
|
8004ff8: f004 fec6 bl 8009d88 <HAL_RCC_GetClockConfig>
|
|
|
|
/* Compute TIM6 clock */
|
|
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
|
|
8004ffc: f004 fe9c bl 8009d38 <HAL_RCC_GetPCLK1Freq>
|
|
8005000: 4603 mov r3, r0
|
|
8005002: 005b lsls r3, r3, #1
|
|
8005004: 62fb str r3, [r7, #44] ; 0x2c
|
|
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
|
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
|
8005006: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8005008: 4a13 ldr r2, [pc, #76] ; (8005058 <HAL_InitTick+0xa4>)
|
|
800500a: fba2 2303 umull r2, r3, r2, r3
|
|
800500e: 0c9b lsrs r3, r3, #18
|
|
8005010: 3b01 subs r3, #1
|
|
8005012: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
/* Initialize TIM6 */
|
|
htim6.Instance = TIM6;
|
|
8005014: 4b11 ldr r3, [pc, #68] ; (800505c <HAL_InitTick+0xa8>)
|
|
8005016: 4a12 ldr r2, [pc, #72] ; (8005060 <HAL_InitTick+0xac>)
|
|
8005018: 601a str r2, [r3, #0]
|
|
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
|
|
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
|
+ ClockDivision = 0
|
|
+ Counter direction = Up
|
|
*/
|
|
htim6.Init.Period = (1000000U / 1000U) - 1U;
|
|
800501a: 4b10 ldr r3, [pc, #64] ; (800505c <HAL_InitTick+0xa8>)
|
|
800501c: f240 32e7 movw r2, #999 ; 0x3e7
|
|
8005020: 60da str r2, [r3, #12]
|
|
htim6.Init.Prescaler = uwPrescalerValue;
|
|
8005022: 4a0e ldr r2, [pc, #56] ; (800505c <HAL_InitTick+0xa8>)
|
|
8005024: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8005026: 6053 str r3, [r2, #4]
|
|
htim6.Init.ClockDivision = 0;
|
|
8005028: 4b0c ldr r3, [pc, #48] ; (800505c <HAL_InitTick+0xa8>)
|
|
800502a: 2200 movs r2, #0
|
|
800502c: 611a str r2, [r3, #16]
|
|
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800502e: 4b0b ldr r3, [pc, #44] ; (800505c <HAL_InitTick+0xa8>)
|
|
8005030: 2200 movs r2, #0
|
|
8005032: 609a str r2, [r3, #8]
|
|
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
|
|
8005034: 4809 ldr r0, [pc, #36] ; (800505c <HAL_InitTick+0xa8>)
|
|
8005036: f005 ffc4 bl 800afc2 <HAL_TIM_Base_Init>
|
|
800503a: 4603 mov r3, r0
|
|
800503c: 2b00 cmp r3, #0
|
|
800503e: d104 bne.n 800504a <HAL_InitTick+0x96>
|
|
{
|
|
/* Start the TIM time Base generation in interrupt mode */
|
|
return HAL_TIM_Base_Start_IT(&htim6);
|
|
8005040: 4806 ldr r0, [pc, #24] ; (800505c <HAL_InitTick+0xa8>)
|
|
8005042: f005 ffe9 bl 800b018 <HAL_TIM_Base_Start_IT>
|
|
8005046: 4603 mov r3, r0
|
|
8005048: e000 b.n 800504c <HAL_InitTick+0x98>
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
800504a: 2301 movs r3, #1
|
|
}
|
|
800504c: 4618 mov r0, r3
|
|
800504e: 3730 adds r7, #48 ; 0x30
|
|
8005050: 46bd mov sp, r7
|
|
8005052: bd80 pop {r7, pc}
|
|
8005054: 40023800 .word 0x40023800
|
|
8005058: 431bde83 .word 0x431bde83
|
|
800505c: 20008f4c .word 0x20008f4c
|
|
8005060: 40001000 .word 0x40001000
|
|
|
|
08005064 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8005064: b480 push {r7}
|
|
8005066: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8005068: e7fe b.n 8005068 <NMI_Handler+0x4>
|
|
|
|
0800506a <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800506a: b480 push {r7}
|
|
800506c: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800506e: e7fe b.n 800506e <HardFault_Handler+0x4>
|
|
|
|
08005070 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8005070: b480 push {r7}
|
|
8005072: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8005074: e7fe b.n 8005074 <MemManage_Handler+0x4>
|
|
|
|
08005076 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8005076: b480 push {r7}
|
|
8005078: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800507a: e7fe b.n 800507a <BusFault_Handler+0x4>
|
|
|
|
0800507c <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
800507c: b480 push {r7}
|
|
800507e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8005080: e7fe b.n 8005080 <UsageFault_Handler+0x4>
|
|
|
|
08005082 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8005082: b480 push {r7}
|
|
8005084: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8005086: bf00 nop
|
|
8005088: 46bd mov sp, r7
|
|
800508a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800508e: 4770 bx lr
|
|
|
|
08005090 <TIM6_DAC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
|
|
*/
|
|
void TIM6_DAC_IRQHandler(void)
|
|
{
|
|
8005090: b580 push {r7, lr}
|
|
8005092: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 0 */
|
|
HAL_DAC_IRQHandler(&hdac);
|
|
8005094: 4803 ldr r0, [pc, #12] ; (80050a4 <TIM6_DAC_IRQHandler+0x14>)
|
|
8005096: f000 ff19 bl 8005ecc <HAL_DAC_IRQHandler>
|
|
HAL_TIM_IRQHandler(&htim6);
|
|
800509a: 4803 ldr r0, [pc, #12] ; (80050a8 <TIM6_DAC_IRQHandler+0x18>)
|
|
800509c: f006 f81b bl 800b0d6 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 1 */
|
|
}
|
|
80050a0: bf00 nop
|
|
80050a2: bd80 pop {r7, pc}
|
|
80050a4: 20008ca8 .word 0x20008ca8
|
|
80050a8: 20008f4c .word 0x20008f4c
|
|
|
|
080050ac <ETH_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles Ethernet global interrupt.
|
|
*/
|
|
void ETH_IRQHandler(void)
|
|
{
|
|
80050ac: b580 push {r7, lr}
|
|
80050ae: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN ETH_IRQn 0 */
|
|
|
|
/* USER CODE END ETH_IRQn 0 */
|
|
HAL_ETH_IRQHandler(&heth);
|
|
80050b0: 4802 ldr r0, [pc, #8] ; (80050bc <ETH_IRQHandler+0x10>)
|
|
80050b2: f001 ffe3 bl 800707c <HAL_ETH_IRQHandler>
|
|
/* USER CODE BEGIN ETH_IRQn 1 */
|
|
|
|
/* USER CODE END ETH_IRQn 1 */
|
|
}
|
|
80050b6: bf00 nop
|
|
80050b8: bd80 pop {r7, pc}
|
|
80050ba: bf00 nop
|
|
80050bc: 2000a8ac .word 0x2000a8ac
|
|
|
|
080050c0 <LTDC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles LTDC global interrupt.
|
|
*/
|
|
void LTDC_IRQHandler(void)
|
|
{
|
|
80050c0: b580 push {r7, lr}
|
|
80050c2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN LTDC_IRQn 0 */
|
|
|
|
/* USER CODE END LTDC_IRQn 0 */
|
|
HAL_LTDC_IRQHandler(&hltdc);
|
|
80050c4: 4802 ldr r0, [pc, #8] ; (80050d0 <LTDC_IRQHandler+0x10>)
|
|
80050c6: f003 fee1 bl 8008e8c <HAL_LTDC_IRQHandler>
|
|
/* USER CODE BEGIN LTDC_IRQn 1 */
|
|
|
|
/* USER CODE END LTDC_IRQn 1 */
|
|
}
|
|
80050ca: bf00 nop
|
|
80050cc: bd80 pop {r7, pc}
|
|
80050ce: bf00 nop
|
|
80050d0: 20008ae4 .word 0x20008ae4
|
|
|
|
080050d4 <_read>:
|
|
_kill(status, -1);
|
|
while (1) {} /* Make sure we hang here */
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
80050d4: b580 push {r7, lr}
|
|
80050d6: b086 sub sp, #24
|
|
80050d8: af00 add r7, sp, #0
|
|
80050da: 60f8 str r0, [r7, #12]
|
|
80050dc: 60b9 str r1, [r7, #8]
|
|
80050de: 607a str r2, [r7, #4]
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
80050e0: 2300 movs r3, #0
|
|
80050e2: 617b str r3, [r7, #20]
|
|
80050e4: e00a b.n 80050fc <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
80050e6: f3af 8000 nop.w
|
|
80050ea: 4601 mov r1, r0
|
|
80050ec: 68bb ldr r3, [r7, #8]
|
|
80050ee: 1c5a adds r2, r3, #1
|
|
80050f0: 60ba str r2, [r7, #8]
|
|
80050f2: b2ca uxtb r2, r1
|
|
80050f4: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
80050f6: 697b ldr r3, [r7, #20]
|
|
80050f8: 3301 adds r3, #1
|
|
80050fa: 617b str r3, [r7, #20]
|
|
80050fc: 697a ldr r2, [r7, #20]
|
|
80050fe: 687b ldr r3, [r7, #4]
|
|
8005100: 429a cmp r2, r3
|
|
8005102: dbf0 blt.n 80050e6 <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
8005104: 687b ldr r3, [r7, #4]
|
|
}
|
|
8005106: 4618 mov r0, r3
|
|
8005108: 3718 adds r7, #24
|
|
800510a: 46bd mov sp, r7
|
|
800510c: bd80 pop {r7, pc}
|
|
|
|
0800510e <_write>:
|
|
|
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
|
{
|
|
800510e: b580 push {r7, lr}
|
|
8005110: b086 sub sp, #24
|
|
8005112: af00 add r7, sp, #0
|
|
8005114: 60f8 str r0, [r7, #12]
|
|
8005116: 60b9 str r1, [r7, #8]
|
|
8005118: 607a str r2, [r7, #4]
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
800511a: 2300 movs r3, #0
|
|
800511c: 617b str r3, [r7, #20]
|
|
800511e: e009 b.n 8005134 <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
8005120: 68bb ldr r3, [r7, #8]
|
|
8005122: 1c5a adds r2, r3, #1
|
|
8005124: 60ba str r2, [r7, #8]
|
|
8005126: 781b ldrb r3, [r3, #0]
|
|
8005128: 4618 mov r0, r3
|
|
800512a: f3af 8000 nop.w
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
800512e: 697b ldr r3, [r7, #20]
|
|
8005130: 3301 adds r3, #1
|
|
8005132: 617b str r3, [r7, #20]
|
|
8005134: 697a ldr r2, [r7, #20]
|
|
8005136: 687b ldr r3, [r7, #4]
|
|
8005138: 429a cmp r2, r3
|
|
800513a: dbf1 blt.n 8005120 <_write+0x12>
|
|
}
|
|
return len;
|
|
800513c: 687b ldr r3, [r7, #4]
|
|
}
|
|
800513e: 4618 mov r0, r3
|
|
8005140: 3718 adds r7, #24
|
|
8005142: 46bd mov sp, r7
|
|
8005144: bd80 pop {r7, pc}
|
|
|
|
08005146 <_close>:
|
|
|
|
int _close(int file)
|
|
{
|
|
8005146: b480 push {r7}
|
|
8005148: b083 sub sp, #12
|
|
800514a: af00 add r7, sp, #0
|
|
800514c: 6078 str r0, [r7, #4]
|
|
return -1;
|
|
800514e: f04f 33ff mov.w r3, #4294967295
|
|
}
|
|
8005152: 4618 mov r0, r3
|
|
8005154: 370c adds r7, #12
|
|
8005156: 46bd mov sp, r7
|
|
8005158: f85d 7b04 ldr.w r7, [sp], #4
|
|
800515c: 4770 bx lr
|
|
|
|
0800515e <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
800515e: b480 push {r7}
|
|
8005160: b083 sub sp, #12
|
|
8005162: af00 add r7, sp, #0
|
|
8005164: 6078 str r0, [r7, #4]
|
|
8005166: 6039 str r1, [r7, #0]
|
|
st->st_mode = S_IFCHR;
|
|
8005168: 683b ldr r3, [r7, #0]
|
|
800516a: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
800516e: 605a str r2, [r3, #4]
|
|
return 0;
|
|
8005170: 2300 movs r3, #0
|
|
}
|
|
8005172: 4618 mov r0, r3
|
|
8005174: 370c adds r7, #12
|
|
8005176: 46bd mov sp, r7
|
|
8005178: f85d 7b04 ldr.w r7, [sp], #4
|
|
800517c: 4770 bx lr
|
|
|
|
0800517e <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
800517e: b480 push {r7}
|
|
8005180: b083 sub sp, #12
|
|
8005182: af00 add r7, sp, #0
|
|
8005184: 6078 str r0, [r7, #4]
|
|
return 1;
|
|
8005186: 2301 movs r3, #1
|
|
}
|
|
8005188: 4618 mov r0, r3
|
|
800518a: 370c adds r7, #12
|
|
800518c: 46bd mov sp, r7
|
|
800518e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005192: 4770 bx lr
|
|
|
|
08005194 <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
8005194: b480 push {r7}
|
|
8005196: b085 sub sp, #20
|
|
8005198: af00 add r7, sp, #0
|
|
800519a: 60f8 str r0, [r7, #12]
|
|
800519c: 60b9 str r1, [r7, #8]
|
|
800519e: 607a str r2, [r7, #4]
|
|
return 0;
|
|
80051a0: 2300 movs r3, #0
|
|
}
|
|
80051a2: 4618 mov r0, r3
|
|
80051a4: 3714 adds r7, #20
|
|
80051a6: 46bd mov sp, r7
|
|
80051a8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80051ac: 4770 bx lr
|
|
...
|
|
|
|
080051b0 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
80051b0: b480 push {r7}
|
|
80051b2: b087 sub sp, #28
|
|
80051b4: af00 add r7, sp, #0
|
|
80051b6: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
80051b8: 4a14 ldr r2, [pc, #80] ; (800520c <_sbrk+0x5c>)
|
|
80051ba: 4b15 ldr r3, [pc, #84] ; (8005210 <_sbrk+0x60>)
|
|
80051bc: 1ad3 subs r3, r2, r3
|
|
80051be: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
80051c0: 697b ldr r3, [r7, #20]
|
|
80051c2: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
80051c4: 4b13 ldr r3, [pc, #76] ; (8005214 <_sbrk+0x64>)
|
|
80051c6: 681b ldr r3, [r3, #0]
|
|
80051c8: 2b00 cmp r3, #0
|
|
80051ca: d102 bne.n 80051d2 <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
80051cc: 4b11 ldr r3, [pc, #68] ; (8005214 <_sbrk+0x64>)
|
|
80051ce: 4a12 ldr r2, [pc, #72] ; (8005218 <_sbrk+0x68>)
|
|
80051d0: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
80051d2: 4b10 ldr r3, [pc, #64] ; (8005214 <_sbrk+0x64>)
|
|
80051d4: 681a ldr r2, [r3, #0]
|
|
80051d6: 687b ldr r3, [r7, #4]
|
|
80051d8: 4413 add r3, r2
|
|
80051da: 693a ldr r2, [r7, #16]
|
|
80051dc: 429a cmp r2, r3
|
|
80051de: d205 bcs.n 80051ec <_sbrk+0x3c>
|
|
{
|
|
errno = ENOMEM;
|
|
80051e0: 4b0e ldr r3, [pc, #56] ; (800521c <_sbrk+0x6c>)
|
|
80051e2: 220c movs r2, #12
|
|
80051e4: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
80051e6: f04f 33ff mov.w r3, #4294967295
|
|
80051ea: e009 b.n 8005200 <_sbrk+0x50>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
80051ec: 4b09 ldr r3, [pc, #36] ; (8005214 <_sbrk+0x64>)
|
|
80051ee: 681b ldr r3, [r3, #0]
|
|
80051f0: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
80051f2: 4b08 ldr r3, [pc, #32] ; (8005214 <_sbrk+0x64>)
|
|
80051f4: 681a ldr r2, [r3, #0]
|
|
80051f6: 687b ldr r3, [r7, #4]
|
|
80051f8: 4413 add r3, r2
|
|
80051fa: 4a06 ldr r2, [pc, #24] ; (8005214 <_sbrk+0x64>)
|
|
80051fc: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80051fe: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8005200: 4618 mov r0, r3
|
|
8005202: 371c adds r7, #28
|
|
8005204: 46bd mov sp, r7
|
|
8005206: f85d 7b04 ldr.w r7, [sp], #4
|
|
800520a: 4770 bx lr
|
|
800520c: 20050000 .word 0x20050000
|
|
8005210: 00000400 .word 0x00000400
|
|
8005214: 20000580 .word 0x20000580
|
|
8005218: 2000f848 .word 0x2000f848
|
|
800521c: 2000f840 .word 0x2000f840
|
|
|
|
08005220 <SystemInit>:
|
|
* SystemFrequency variable.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
8005220: b480 push {r7}
|
|
8005222: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
8005224: 4b08 ldr r3, [pc, #32] ; (8005248 <SystemInit+0x28>)
|
|
8005226: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800522a: 4a07 ldr r2, [pc, #28] ; (8005248 <SystemInit+0x28>)
|
|
800522c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
8005230: f8c2 3088 str.w r3, [r2, #136] ; 0x88
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#ifdef VECT_TAB_SRAM
|
|
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#else
|
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
8005234: 4b04 ldr r3, [pc, #16] ; (8005248 <SystemInit+0x28>)
|
|
8005236: f04f 6200 mov.w r2, #134217728 ; 0x8000000
|
|
800523a: 609a str r2, [r3, #8]
|
|
#endif
|
|
}
|
|
800523c: bf00 nop
|
|
800523e: 46bd mov sp, r7
|
|
8005240: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005244: 4770 bx lr
|
|
8005246: bf00 nop
|
|
8005248: e000ed00 .word 0xe000ed00
|
|
|
|
0800524c <Reset_Handler>:
|
|
*/
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler: ldr sp, =_estack /* set stack pointer */
|
|
800524c: f8df d034 ldr.w sp, [pc, #52] ; 8005284 <LoopFillZerobss+0x14>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
8005250: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
8005252: e003 b.n 800525c <LoopCopyDataInit>
|
|
|
|
08005254 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8005254: 4b0c ldr r3, [pc, #48] ; (8005288 <LoopFillZerobss+0x18>)
|
|
ldr r3, [r3, r1]
|
|
8005256: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
8005258: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
800525a: 3104 adds r1, #4
|
|
|
|
0800525c <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
800525c: 480b ldr r0, [pc, #44] ; (800528c <LoopFillZerobss+0x1c>)
|
|
ldr r3, =_edata
|
|
800525e: 4b0c ldr r3, [pc, #48] ; (8005290 <LoopFillZerobss+0x20>)
|
|
adds r2, r0, r1
|
|
8005260: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
8005262: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
8005264: d3f6 bcc.n 8005254 <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
8005266: 4a0b ldr r2, [pc, #44] ; (8005294 <LoopFillZerobss+0x24>)
|
|
b LoopFillZerobss
|
|
8005268: e002 b.n 8005270 <LoopFillZerobss>
|
|
|
|
0800526a <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
800526a: 2300 movs r3, #0
|
|
str r3, [r2], #4
|
|
800526c: f842 3b04 str.w r3, [r2], #4
|
|
|
|
08005270 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
8005270: 4b09 ldr r3, [pc, #36] ; (8005298 <LoopFillZerobss+0x28>)
|
|
cmp r2, r3
|
|
8005272: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
8005274: d3f9 bcc.n 800526a <FillZerobss>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8005276: f7ff ffd3 bl 8005220 <SystemInit>
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800527a: f017 fcbd bl 801cbf8 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800527e: f7fb fc6d bl 8000b5c <main>
|
|
bx lr
|
|
8005282: 4770 bx lr
|
|
Reset_Handler: ldr sp, =_estack /* set stack pointer */
|
|
8005284: 20050000 .word 0x20050000
|
|
ldr r3, =_sidata
|
|
8005288: 08022f30 .word 0x08022f30
|
|
ldr r0, =_sdata
|
|
800528c: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
8005290: 200000e8 .word 0x200000e8
|
|
ldr r2, =_sbss
|
|
8005294: 200000e8 .word 0x200000e8
|
|
ldr r3, = _ebss
|
|
8005298: 2000f848 .word 0x2000f848
|
|
|
|
0800529c <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800529c: e7fe b.n 800529c <ADC_IRQHandler>
|
|
|
|
0800529e <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
800529e: b580 push {r7, lr}
|
|
80052a0: af00 add r7, sp, #0
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
80052a2: 2003 movs r0, #3
|
|
80052a4: f000 fcd1 bl 8005c4a <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
80052a8: 2000 movs r0, #0
|
|
80052aa: f7ff fe83 bl 8004fb4 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80052ae: f7ff f90f bl 80044d0 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80052b2: 2300 movs r3, #0
|
|
}
|
|
80052b4: 4618 mov r0, r3
|
|
80052b6: bd80 pop {r7, pc}
|
|
|
|
080052b8 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80052b8: b480 push {r7}
|
|
80052ba: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80052bc: 4b06 ldr r3, [pc, #24] ; (80052d8 <HAL_IncTick+0x20>)
|
|
80052be: 781b ldrb r3, [r3, #0]
|
|
80052c0: 461a mov r2, r3
|
|
80052c2: 4b06 ldr r3, [pc, #24] ; (80052dc <HAL_IncTick+0x24>)
|
|
80052c4: 681b ldr r3, [r3, #0]
|
|
80052c6: 4413 add r3, r2
|
|
80052c8: 4a04 ldr r2, [pc, #16] ; (80052dc <HAL_IncTick+0x24>)
|
|
80052ca: 6013 str r3, [r2, #0]
|
|
}
|
|
80052cc: bf00 nop
|
|
80052ce: 46bd mov sp, r7
|
|
80052d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80052d4: 4770 bx lr
|
|
80052d6: bf00 nop
|
|
80052d8: 2000006c .word 0x2000006c
|
|
80052dc: 20008f8c .word 0x20008f8c
|
|
|
|
080052e0 <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80052e0: b480 push {r7}
|
|
80052e2: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80052e4: 4b03 ldr r3, [pc, #12] ; (80052f4 <HAL_GetTick+0x14>)
|
|
80052e6: 681b ldr r3, [r3, #0]
|
|
}
|
|
80052e8: 4618 mov r0, r3
|
|
80052ea: 46bd mov sp, r7
|
|
80052ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80052f0: 4770 bx lr
|
|
80052f2: bf00 nop
|
|
80052f4: 20008f8c .word 0x20008f8c
|
|
|
|
080052f8 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
80052f8: b580 push {r7, lr}
|
|
80052fa: b084 sub sp, #16
|
|
80052fc: af00 add r7, sp, #0
|
|
80052fe: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8005300: f7ff ffee bl 80052e0 <HAL_GetTick>
|
|
8005304: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8005306: 687b ldr r3, [r7, #4]
|
|
8005308: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
800530a: 68fb ldr r3, [r7, #12]
|
|
800530c: f1b3 3fff cmp.w r3, #4294967295
|
|
8005310: d005 beq.n 800531e <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
8005312: 4b09 ldr r3, [pc, #36] ; (8005338 <HAL_Delay+0x40>)
|
|
8005314: 781b ldrb r3, [r3, #0]
|
|
8005316: 461a mov r2, r3
|
|
8005318: 68fb ldr r3, [r7, #12]
|
|
800531a: 4413 add r3, r2
|
|
800531c: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800531e: bf00 nop
|
|
8005320: f7ff ffde bl 80052e0 <HAL_GetTick>
|
|
8005324: 4602 mov r2, r0
|
|
8005326: 68bb ldr r3, [r7, #8]
|
|
8005328: 1ad3 subs r3, r2, r3
|
|
800532a: 68fa ldr r2, [r7, #12]
|
|
800532c: 429a cmp r2, r3
|
|
800532e: d8f7 bhi.n 8005320 <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
8005330: bf00 nop
|
|
8005332: 3710 adds r7, #16
|
|
8005334: 46bd mov sp, r7
|
|
8005336: bd80 pop {r7, pc}
|
|
8005338: 2000006c .word 0x2000006c
|
|
|
|
0800533c <HAL_ADC_Init>:
|
|
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified ADC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
800533c: b580 push {r7, lr}
|
|
800533e: b084 sub sp, #16
|
|
8005340: af00 add r7, sp, #0
|
|
8005342: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8005344: 2300 movs r3, #0
|
|
8005346: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check ADC handle */
|
|
if(hadc == NULL)
|
|
8005348: 687b ldr r3, [r7, #4]
|
|
800534a: 2b00 cmp r3, #0
|
|
800534c: d101 bne.n 8005352 <HAL_ADC_Init+0x16>
|
|
{
|
|
return HAL_ERROR;
|
|
800534e: 2301 movs r3, #1
|
|
8005350: e031 b.n 80053b6 <HAL_ADC_Init+0x7a>
|
|
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
{
|
|
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
|
|
}
|
|
|
|
if(hadc->State == HAL_ADC_STATE_RESET)
|
|
8005352: 687b ldr r3, [r7, #4]
|
|
8005354: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005356: 2b00 cmp r3, #0
|
|
8005358: d109 bne.n 800536e <HAL_ADC_Init+0x32>
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
800535a: 6878 ldr r0, [r7, #4]
|
|
800535c: f7ff f8e0 bl 8004520 <HAL_ADC_MspInit>
|
|
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
|
|
|
/* Initialize ADC error code */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8005360: 687b ldr r3, [r7, #4]
|
|
8005362: 2200 movs r2, #0
|
|
8005364: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Allocate lock resource and initialize it */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
8005366: 687b ldr r3, [r7, #4]
|
|
8005368: 2200 movs r2, #0
|
|
800536a: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed. */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
|
|
800536e: 687b ldr r3, [r7, #4]
|
|
8005370: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005372: f003 0310 and.w r3, r3, #16
|
|
8005376: 2b00 cmp r3, #0
|
|
8005378: d116 bne.n 80053a8 <HAL_ADC_Init+0x6c>
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
800537a: 687b ldr r3, [r7, #4]
|
|
800537c: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
800537e: 4b10 ldr r3, [pc, #64] ; (80053c0 <HAL_ADC_Init+0x84>)
|
|
8005380: 4013 ands r3, r2
|
|
8005382: f043 0202 orr.w r2, r3, #2
|
|
8005386: 687b ldr r3, [r7, #4]
|
|
8005388: 641a str r2, [r3, #64] ; 0x40
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_BUSY_INTERNAL);
|
|
|
|
/* Set ADC parameters */
|
|
ADC_Init(hadc);
|
|
800538a: 6878 ldr r0, [r7, #4]
|
|
800538c: f000 fab6 bl 80058fc <ADC_Init>
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8005390: 687b ldr r3, [r7, #4]
|
|
8005392: 2200 movs r2, #0
|
|
8005394: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8005396: 687b ldr r3, [r7, #4]
|
|
8005398: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800539a: f023 0303 bic.w r3, r3, #3
|
|
800539e: f043 0201 orr.w r2, r3, #1
|
|
80053a2: 687b ldr r3, [r7, #4]
|
|
80053a4: 641a str r2, [r3, #64] ; 0x40
|
|
80053a6: e001 b.n 80053ac <HAL_ADC_Init+0x70>
|
|
HAL_ADC_STATE_BUSY_INTERNAL,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
else
|
|
{
|
|
tmp_hal_status = HAL_ERROR;
|
|
80053a8: 2301 movs r3, #1
|
|
80053aa: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hadc);
|
|
80053ac: 687b ldr r3, [r7, #4]
|
|
80053ae: 2200 movs r2, #0
|
|
80053b0: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
80053b4: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80053b6: 4618 mov r0, r3
|
|
80053b8: 3710 adds r7, #16
|
|
80053ba: 46bd mov sp, r7
|
|
80053bc: bd80 pop {r7, pc}
|
|
80053be: bf00 nop
|
|
80053c0: ffffeefd .word 0xffffeefd
|
|
|
|
080053c4 <HAL_ADC_Start>:
|
|
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified ADC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
|
|
{
|
|
80053c4: b480 push {r7}
|
|
80053c6: b085 sub sp, #20
|
|
80053c8: af00 add r7, sp, #0
|
|
80053ca: 6078 str r0, [r7, #4]
|
|
__IO uint32_t counter = 0;
|
|
80053cc: 2300 movs r3, #0
|
|
80053ce: 60fb str r3, [r7, #12]
|
|
/* Check the parameters */
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
80053d0: 687b ldr r3, [r7, #4]
|
|
80053d2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
80053d6: 2b01 cmp r3, #1
|
|
80053d8: d101 bne.n 80053de <HAL_ADC_Start+0x1a>
|
|
80053da: 2302 movs r3, #2
|
|
80053dc: e0a0 b.n 8005520 <HAL_ADC_Start+0x15c>
|
|
80053de: 687b ldr r3, [r7, #4]
|
|
80053e0: 2201 movs r2, #1
|
|
80053e2: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Enable the ADC peripheral */
|
|
/* Check if ADC peripheral is disabled in order to enable it and wait during
|
|
Tstab time the ADC's stabilization */
|
|
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
|
|
80053e6: 687b ldr r3, [r7, #4]
|
|
80053e8: 681b ldr r3, [r3, #0]
|
|
80053ea: 689b ldr r3, [r3, #8]
|
|
80053ec: f003 0301 and.w r3, r3, #1
|
|
80053f0: 2b01 cmp r3, #1
|
|
80053f2: d018 beq.n 8005426 <HAL_ADC_Start+0x62>
|
|
{
|
|
/* Enable the Peripheral */
|
|
__HAL_ADC_ENABLE(hadc);
|
|
80053f4: 687b ldr r3, [r7, #4]
|
|
80053f6: 681b ldr r3, [r3, #0]
|
|
80053f8: 689a ldr r2, [r3, #8]
|
|
80053fa: 687b ldr r3, [r7, #4]
|
|
80053fc: 681b ldr r3, [r3, #0]
|
|
80053fe: f042 0201 orr.w r2, r2, #1
|
|
8005402: 609a str r2, [r3, #8]
|
|
|
|
/* Delay for ADC stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
|
|
8005404: 4b49 ldr r3, [pc, #292] ; (800552c <HAL_ADC_Start+0x168>)
|
|
8005406: 681b ldr r3, [r3, #0]
|
|
8005408: 4a49 ldr r2, [pc, #292] ; (8005530 <HAL_ADC_Start+0x16c>)
|
|
800540a: fba2 2303 umull r2, r3, r2, r3
|
|
800540e: 0c9a lsrs r2, r3, #18
|
|
8005410: 4613 mov r3, r2
|
|
8005412: 005b lsls r3, r3, #1
|
|
8005414: 4413 add r3, r2
|
|
8005416: 60fb str r3, [r7, #12]
|
|
while(counter != 0)
|
|
8005418: e002 b.n 8005420 <HAL_ADC_Start+0x5c>
|
|
{
|
|
counter--;
|
|
800541a: 68fb ldr r3, [r7, #12]
|
|
800541c: 3b01 subs r3, #1
|
|
800541e: 60fb str r3, [r7, #12]
|
|
while(counter != 0)
|
|
8005420: 68fb ldr r3, [r7, #12]
|
|
8005422: 2b00 cmp r3, #0
|
|
8005424: d1f9 bne.n 800541a <HAL_ADC_Start+0x56>
|
|
}
|
|
}
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
|
|
8005426: 687b ldr r3, [r7, #4]
|
|
8005428: 681b ldr r3, [r3, #0]
|
|
800542a: 689b ldr r3, [r3, #8]
|
|
800542c: f003 0301 and.w r3, r3, #1
|
|
8005430: 2b01 cmp r3, #1
|
|
8005432: d174 bne.n 800551e <HAL_ADC_Start+0x15a>
|
|
{
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to regular group conversion results */
|
|
/* - Set state bitfield related to regular group operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8005434: 687b ldr r3, [r7, #4]
|
|
8005436: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8005438: 4b3e ldr r3, [pc, #248] ; (8005534 <HAL_ADC_Start+0x170>)
|
|
800543a: 4013 ands r3, r2
|
|
800543c: f443 7280 orr.w r2, r3, #256 ; 0x100
|
|
8005440: 687b ldr r3, [r7, #4]
|
|
8005442: 641a str r2, [r3, #64] ; 0x40
|
|
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
|
|
HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* If conversions on group regular are also triggering group injected, */
|
|
/* update ADC state. */
|
|
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
|
|
8005444: 687b ldr r3, [r7, #4]
|
|
8005446: 681b ldr r3, [r3, #0]
|
|
8005448: 685b ldr r3, [r3, #4]
|
|
800544a: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
800544e: 2b00 cmp r3, #0
|
|
8005450: d007 beq.n 8005462 <HAL_ADC_Start+0x9e>
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
8005452: 687b ldr r3, [r7, #4]
|
|
8005454: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005456: f423 5340 bic.w r3, r3, #12288 ; 0x3000
|
|
800545a: f443 5280 orr.w r2, r3, #4096 ; 0x1000
|
|
800545e: 687b ldr r3, [r7, #4]
|
|
8005460: 641a str r2, [r3, #64] ; 0x40
|
|
}
|
|
|
|
/* State machine update: Check if an injected conversion is ongoing */
|
|
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
8005462: 687b ldr r3, [r7, #4]
|
|
8005464: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005466: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
800546a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800546e: d106 bne.n 800547e <HAL_ADC_Start+0xba>
|
|
{
|
|
/* Reset ADC error code fields related to conversions on group regular */
|
|
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
|
|
8005470: 687b ldr r3, [r7, #4]
|
|
8005472: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8005474: f023 0206 bic.w r2, r3, #6
|
|
8005478: 687b ldr r3, [r7, #4]
|
|
800547a: 645a str r2, [r3, #68] ; 0x44
|
|
800547c: e002 b.n 8005484 <HAL_ADC_Start+0xc0>
|
|
}
|
|
else
|
|
{
|
|
/* Reset ADC all error code fields */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
800547e: 687b ldr r3, [r7, #4]
|
|
8005480: 2200 movs r2, #0
|
|
8005482: 645a str r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
8005484: 687b ldr r3, [r7, #4]
|
|
8005486: 2200 movs r2, #0
|
|
8005488: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Clear regular group conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
|
|
800548c: 687b ldr r3, [r7, #4]
|
|
800548e: 681b ldr r3, [r3, #0]
|
|
8005490: f06f 0222 mvn.w r2, #34 ; 0x22
|
|
8005494: 601a str r2, [r3, #0]
|
|
|
|
/* Check if Multimode enabled */
|
|
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
|
|
8005496: 4b28 ldr r3, [pc, #160] ; (8005538 <HAL_ADC_Start+0x174>)
|
|
8005498: 685b ldr r3, [r3, #4]
|
|
800549a: f003 031f and.w r3, r3, #31
|
|
800549e: 2b00 cmp r3, #0
|
|
80054a0: d10f bne.n 80054c2 <HAL_ADC_Start+0xfe>
|
|
{
|
|
/* if no external trigger present enable software conversion of regular channels */
|
|
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
|
|
80054a2: 687b ldr r3, [r7, #4]
|
|
80054a4: 681b ldr r3, [r3, #0]
|
|
80054a6: 689b ldr r3, [r3, #8]
|
|
80054a8: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
|
|
80054ac: 2b00 cmp r3, #0
|
|
80054ae: d136 bne.n 800551e <HAL_ADC_Start+0x15a>
|
|
{
|
|
/* Enable the selected ADC software conversion for regular group */
|
|
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
|
|
80054b0: 687b ldr r3, [r7, #4]
|
|
80054b2: 681b ldr r3, [r3, #0]
|
|
80054b4: 689a ldr r2, [r3, #8]
|
|
80054b6: 687b ldr r3, [r7, #4]
|
|
80054b8: 681b ldr r3, [r3, #0]
|
|
80054ba: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
|
|
80054be: 609a str r2, [r3, #8]
|
|
80054c0: e02d b.n 800551e <HAL_ADC_Start+0x15a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
|
|
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
|
|
80054c2: 687b ldr r3, [r7, #4]
|
|
80054c4: 681b ldr r3, [r3, #0]
|
|
80054c6: 4a1d ldr r2, [pc, #116] ; (800553c <HAL_ADC_Start+0x178>)
|
|
80054c8: 4293 cmp r3, r2
|
|
80054ca: d10e bne.n 80054ea <HAL_ADC_Start+0x126>
|
|
80054cc: 687b ldr r3, [r7, #4]
|
|
80054ce: 681b ldr r3, [r3, #0]
|
|
80054d0: 689b ldr r3, [r3, #8]
|
|
80054d2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
|
|
80054d6: 2b00 cmp r3, #0
|
|
80054d8: d107 bne.n 80054ea <HAL_ADC_Start+0x126>
|
|
{
|
|
/* Enable the selected ADC software conversion for regular group */
|
|
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
|
|
80054da: 687b ldr r3, [r7, #4]
|
|
80054dc: 681b ldr r3, [r3, #0]
|
|
80054de: 689a ldr r2, [r3, #8]
|
|
80054e0: 687b ldr r3, [r7, #4]
|
|
80054e2: 681b ldr r3, [r3, #0]
|
|
80054e4: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
|
|
80054e8: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if dual mode is selected, ADC3 works independently. */
|
|
/* check if the mode selected is not triple */
|
|
if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
|
|
80054ea: 4b13 ldr r3, [pc, #76] ; (8005538 <HAL_ADC_Start+0x174>)
|
|
80054ec: 685b ldr r3, [r3, #4]
|
|
80054ee: f003 0310 and.w r3, r3, #16
|
|
80054f2: 2b00 cmp r3, #0
|
|
80054f4: d113 bne.n 800551e <HAL_ADC_Start+0x15a>
|
|
{
|
|
/* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
|
|
if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
|
|
80054f6: 687b ldr r3, [r7, #4]
|
|
80054f8: 681b ldr r3, [r3, #0]
|
|
80054fa: 4a11 ldr r2, [pc, #68] ; (8005540 <HAL_ADC_Start+0x17c>)
|
|
80054fc: 4293 cmp r3, r2
|
|
80054fe: d10e bne.n 800551e <HAL_ADC_Start+0x15a>
|
|
8005500: 687b ldr r3, [r7, #4]
|
|
8005502: 681b ldr r3, [r3, #0]
|
|
8005504: 689b ldr r3, [r3, #8]
|
|
8005506: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
|
|
800550a: 2b00 cmp r3, #0
|
|
800550c: d107 bne.n 800551e <HAL_ADC_Start+0x15a>
|
|
{
|
|
/* Enable the selected ADC software conversion for regular group */
|
|
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
|
|
800550e: 687b ldr r3, [r7, #4]
|
|
8005510: 681b ldr r3, [r3, #0]
|
|
8005512: 689a ldr r2, [r3, #8]
|
|
8005514: 687b ldr r3, [r7, #4]
|
|
8005516: 681b ldr r3, [r3, #0]
|
|
8005518: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
|
|
800551c: 609a str r2, [r3, #8]
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800551e: 2300 movs r3, #0
|
|
}
|
|
8005520: 4618 mov r0, r3
|
|
8005522: 3714 adds r7, #20
|
|
8005524: 46bd mov sp, r7
|
|
8005526: f85d 7b04 ldr.w r7, [sp], #4
|
|
800552a: 4770 bx lr
|
|
800552c: 20000064 .word 0x20000064
|
|
8005530: 431bde83 .word 0x431bde83
|
|
8005534: fffff8fe .word 0xfffff8fe
|
|
8005538: 40012300 .word 0x40012300
|
|
800553c: 40012000 .word 0x40012000
|
|
8005540: 40012200 .word 0x40012200
|
|
|
|
08005544 <HAL_ADC_PollForConversion>:
|
|
* the configuration information for the specified ADC.
|
|
* @param Timeout Timeout value in millisecond.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
|
|
{
|
|
8005544: b580 push {r7, lr}
|
|
8005546: b084 sub sp, #16
|
|
8005548: af00 add r7, sp, #0
|
|
800554a: 6078 str r0, [r7, #4]
|
|
800554c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart = 0;
|
|
800554e: 2300 movs r3, #0
|
|
8005550: 60fb str r3, [r7, #12]
|
|
/* each conversion: */
|
|
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
|
|
/* several ranks and polling for end of each conversion. */
|
|
/* For code simplicity sake, this particular case is generalized to */
|
|
/* ADC configured in DMA mode and polling for end of each conversion. */
|
|
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
|
|
8005552: 687b ldr r3, [r7, #4]
|
|
8005554: 681b ldr r3, [r3, #0]
|
|
8005556: 689b ldr r3, [r3, #8]
|
|
8005558: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
800555c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
8005560: d113 bne.n 800558a <HAL_ADC_PollForConversion+0x46>
|
|
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
|
|
8005562: 687b ldr r3, [r7, #4]
|
|
8005564: 681b ldr r3, [r3, #0]
|
|
8005566: 689b ldr r3, [r3, #8]
|
|
8005568: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
|
|
800556c: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
8005570: d10b bne.n 800558a <HAL_ADC_PollForConversion+0x46>
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8005572: 687b ldr r3, [r7, #4]
|
|
8005574: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005576: f043 0220 orr.w r2, r3, #32
|
|
800557a: 687b ldr r3, [r7, #4]
|
|
800557c: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
800557e: 687b ldr r3, [r7, #4]
|
|
8005580: 2200 movs r2, #0
|
|
8005582: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_ERROR;
|
|
8005586: 2301 movs r3, #1
|
|
8005588: e05c b.n 8005644 <HAL_ADC_PollForConversion+0x100>
|
|
}
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800558a: f7ff fea9 bl 80052e0 <HAL_GetTick>
|
|
800558e: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check End of conversion flag */
|
|
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
|
|
8005590: e01a b.n 80055c8 <HAL_ADC_PollForConversion+0x84>
|
|
{
|
|
/* Check if timeout is disabled (set to infinite wait) */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
8005592: 683b ldr r3, [r7, #0]
|
|
8005594: f1b3 3fff cmp.w r3, #4294967295
|
|
8005598: d016 beq.n 80055c8 <HAL_ADC_PollForConversion+0x84>
|
|
{
|
|
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
|
|
800559a: 683b ldr r3, [r7, #0]
|
|
800559c: 2b00 cmp r3, #0
|
|
800559e: d007 beq.n 80055b0 <HAL_ADC_PollForConversion+0x6c>
|
|
80055a0: f7ff fe9e bl 80052e0 <HAL_GetTick>
|
|
80055a4: 4602 mov r2, r0
|
|
80055a6: 68fb ldr r3, [r7, #12]
|
|
80055a8: 1ad3 subs r3, r2, r3
|
|
80055aa: 683a ldr r2, [r7, #0]
|
|
80055ac: 429a cmp r2, r3
|
|
80055ae: d20b bcs.n 80055c8 <HAL_ADC_PollForConversion+0x84>
|
|
{
|
|
/* Update ADC state machine to timeout */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
|
|
80055b0: 687b ldr r3, [r7, #4]
|
|
80055b2: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80055b4: f043 0204 orr.w r2, r3, #4
|
|
80055b8: 687b ldr r3, [r7, #4]
|
|
80055ba: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80055bc: 687b ldr r3, [r7, #4]
|
|
80055be: 2200 movs r2, #0
|
|
80055c0: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_TIMEOUT;
|
|
80055c4: 2303 movs r3, #3
|
|
80055c6: e03d b.n 8005644 <HAL_ADC_PollForConversion+0x100>
|
|
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
|
|
80055c8: 687b ldr r3, [r7, #4]
|
|
80055ca: 681b ldr r3, [r3, #0]
|
|
80055cc: 681b ldr r3, [r3, #0]
|
|
80055ce: f003 0302 and.w r3, r3, #2
|
|
80055d2: 2b02 cmp r3, #2
|
|
80055d4: d1dd bne.n 8005592 <HAL_ADC_PollForConversion+0x4e>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Clear regular group conversion flag */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
|
|
80055d6: 687b ldr r3, [r7, #4]
|
|
80055d8: 681b ldr r3, [r3, #0]
|
|
80055da: f06f 0212 mvn.w r2, #18
|
|
80055de: 601a str r2, [r3, #0]
|
|
|
|
/* Update ADC state machine */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
|
|
80055e0: 687b ldr r3, [r7, #4]
|
|
80055e2: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
80055e4: f443 7200 orr.w r2, r3, #512 ; 0x200
|
|
80055e8: 687b ldr r3, [r7, #4]
|
|
80055ea: 641a str r2, [r3, #64] ; 0x40
|
|
/* by external trigger, continuous mode or scan sequence on going. */
|
|
/* Note: On STM32F7, there is no independent flag of end of sequence. */
|
|
/* The test of scan sequence on going is done either with scan */
|
|
/* sequence disabled or with end of conversion flag set to */
|
|
/* of end of sequence. */
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
80055ec: 687b ldr r3, [r7, #4]
|
|
80055ee: 681b ldr r3, [r3, #0]
|
|
80055f0: 689b ldr r3, [r3, #8]
|
|
80055f2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
|
|
80055f6: 2b00 cmp r3, #0
|
|
80055f8: d123 bne.n 8005642 <HAL_ADC_PollForConversion+0xfe>
|
|
(hadc->Init.ContinuousConvMode == DISABLE) &&
|
|
80055fa: 687b ldr r3, [r7, #4]
|
|
80055fc: 699b ldr r3, [r3, #24]
|
|
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
|
|
80055fe: 2b00 cmp r3, #0
|
|
8005600: d11f bne.n 8005642 <HAL_ADC_PollForConversion+0xfe>
|
|
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
|
|
8005602: 687b ldr r3, [r7, #4]
|
|
8005604: 681b ldr r3, [r3, #0]
|
|
8005606: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8005608: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
|
|
(hadc->Init.ContinuousConvMode == DISABLE) &&
|
|
800560c: 2b00 cmp r3, #0
|
|
800560e: d006 beq.n 800561e <HAL_ADC_PollForConversion+0xda>
|
|
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
|
|
8005610: 687b ldr r3, [r7, #4]
|
|
8005612: 681b ldr r3, [r3, #0]
|
|
8005614: 689b ldr r3, [r3, #8]
|
|
8005616: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
|
|
800561a: 2b00 cmp r3, #0
|
|
800561c: d111 bne.n 8005642 <HAL_ADC_PollForConversion+0xfe>
|
|
{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
|
|
800561e: 687b ldr r3, [r7, #4]
|
|
8005620: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8005622: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
8005626: 687b ldr r3, [r7, #4]
|
|
8005628: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
|
|
800562a: 687b ldr r3, [r7, #4]
|
|
800562c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800562e: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
8005632: 2b00 cmp r3, #0
|
|
8005634: d105 bne.n 8005642 <HAL_ADC_PollForConversion+0xfe>
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
8005636: 687b ldr r3, [r7, #4]
|
|
8005638: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800563a: f043 0201 orr.w r2, r3, #1
|
|
800563e: 687b ldr r3, [r7, #4]
|
|
8005640: 641a str r2, [r3, #64] ; 0x40
|
|
}
|
|
}
|
|
|
|
/* Return ADC state */
|
|
return HAL_OK;
|
|
8005642: 2300 movs r3, #0
|
|
}
|
|
8005644: 4618 mov r0, r3
|
|
8005646: 3710 adds r7, #16
|
|
8005648: 46bd mov sp, r7
|
|
800564a: bd80 pop {r7, pc}
|
|
|
|
0800564c <HAL_ADC_GetValue>:
|
|
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified ADC.
|
|
* @retval Converted value
|
|
*/
|
|
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
|
|
{
|
|
800564c: b480 push {r7}
|
|
800564e: b083 sub sp, #12
|
|
8005650: af00 add r7, sp, #0
|
|
8005652: 6078 str r0, [r7, #4]
|
|
/* Return the selected ADC converted value */
|
|
return hadc->Instance->DR;
|
|
8005654: 687b ldr r3, [r7, #4]
|
|
8005656: 681b ldr r3, [r3, #0]
|
|
8005658: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
}
|
|
800565a: 4618 mov r0, r3
|
|
800565c: 370c adds r7, #12
|
|
800565e: 46bd mov sp, r7
|
|
8005660: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005664: 4770 bx lr
|
|
...
|
|
|
|
08005668 <HAL_ADC_ConfigChannel>:
|
|
* the configuration information for the specified ADC.
|
|
* @param sConfig ADC configuration structure.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
|
|
{
|
|
8005668: b480 push {r7}
|
|
800566a: b085 sub sp, #20
|
|
800566c: af00 add r7, sp, #0
|
|
800566e: 6078 str r0, [r7, #4]
|
|
8005670: 6039 str r1, [r7, #0]
|
|
__IO uint32_t counter = 0;
|
|
8005672: 2300 movs r3, #0
|
|
8005674: 60fb str r3, [r7, #12]
|
|
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
|
|
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
|
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8005676: 687b ldr r3, [r7, #4]
|
|
8005678: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800567c: 2b01 cmp r3, #1
|
|
800567e: d101 bne.n 8005684 <HAL_ADC_ConfigChannel+0x1c>
|
|
8005680: 2302 movs r3, #2
|
|
8005682: e12a b.n 80058da <HAL_ADC_ConfigChannel+0x272>
|
|
8005684: 687b ldr r3, [r7, #4]
|
|
8005686: 2201 movs r2, #1
|
|
8005688: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
|
|
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
|
|
800568c: 683b ldr r3, [r7, #0]
|
|
800568e: 681b ldr r3, [r3, #0]
|
|
8005690: 2b09 cmp r3, #9
|
|
8005692: d93a bls.n 800570a <HAL_ADC_ConfigChannel+0xa2>
|
|
8005694: 683b ldr r3, [r7, #0]
|
|
8005696: 681b ldr r3, [r3, #0]
|
|
8005698: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
|
|
800569c: d035 beq.n 800570a <HAL_ADC_ConfigChannel+0xa2>
|
|
{
|
|
/* Clear the old sample time */
|
|
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
|
|
800569e: 687b ldr r3, [r7, #4]
|
|
80056a0: 681b ldr r3, [r3, #0]
|
|
80056a2: 68d9 ldr r1, [r3, #12]
|
|
80056a4: 683b ldr r3, [r7, #0]
|
|
80056a6: 681b ldr r3, [r3, #0]
|
|
80056a8: b29b uxth r3, r3
|
|
80056aa: 461a mov r2, r3
|
|
80056ac: 4613 mov r3, r2
|
|
80056ae: 005b lsls r3, r3, #1
|
|
80056b0: 4413 add r3, r2
|
|
80056b2: 3b1e subs r3, #30
|
|
80056b4: 2207 movs r2, #7
|
|
80056b6: fa02 f303 lsl.w r3, r2, r3
|
|
80056ba: 43da mvns r2, r3
|
|
80056bc: 687b ldr r3, [r7, #4]
|
|
80056be: 681b ldr r3, [r3, #0]
|
|
80056c0: 400a ands r2, r1
|
|
80056c2: 60da str r2, [r3, #12]
|
|
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
80056c4: 683b ldr r3, [r7, #0]
|
|
80056c6: 681b ldr r3, [r3, #0]
|
|
80056c8: 4a87 ldr r2, [pc, #540] ; (80058e8 <HAL_ADC_ConfigChannel+0x280>)
|
|
80056ca: 4293 cmp r3, r2
|
|
80056cc: d10a bne.n 80056e4 <HAL_ADC_ConfigChannel+0x7c>
|
|
{
|
|
/* Set the new sample time */
|
|
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
|
|
80056ce: 687b ldr r3, [r7, #4]
|
|
80056d0: 681b ldr r3, [r3, #0]
|
|
80056d2: 68d9 ldr r1, [r3, #12]
|
|
80056d4: 683b ldr r3, [r7, #0]
|
|
80056d6: 689b ldr r3, [r3, #8]
|
|
80056d8: 061a lsls r2, r3, #24
|
|
80056da: 687b ldr r3, [r7, #4]
|
|
80056dc: 681b ldr r3, [r3, #0]
|
|
80056de: 430a orrs r2, r1
|
|
80056e0: 60da str r2, [r3, #12]
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
80056e2: e035 b.n 8005750 <HAL_ADC_ConfigChannel+0xe8>
|
|
}
|
|
else
|
|
{
|
|
/* Set the new sample time */
|
|
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
|
|
80056e4: 687b ldr r3, [r7, #4]
|
|
80056e6: 681b ldr r3, [r3, #0]
|
|
80056e8: 68d9 ldr r1, [r3, #12]
|
|
80056ea: 683b ldr r3, [r7, #0]
|
|
80056ec: 689a ldr r2, [r3, #8]
|
|
80056ee: 683b ldr r3, [r7, #0]
|
|
80056f0: 681b ldr r3, [r3, #0]
|
|
80056f2: b29b uxth r3, r3
|
|
80056f4: 4618 mov r0, r3
|
|
80056f6: 4603 mov r3, r0
|
|
80056f8: 005b lsls r3, r3, #1
|
|
80056fa: 4403 add r3, r0
|
|
80056fc: 3b1e subs r3, #30
|
|
80056fe: 409a lsls r2, r3
|
|
8005700: 687b ldr r3, [r7, #4]
|
|
8005702: 681b ldr r3, [r3, #0]
|
|
8005704: 430a orrs r2, r1
|
|
8005706: 60da str r2, [r3, #12]
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
8005708: e022 b.n 8005750 <HAL_ADC_ConfigChannel+0xe8>
|
|
}
|
|
}
|
|
else /* ADC_Channel include in ADC_Channel_[0..9] */
|
|
{
|
|
/* Clear the old sample time */
|
|
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
|
|
800570a: 687b ldr r3, [r7, #4]
|
|
800570c: 681b ldr r3, [r3, #0]
|
|
800570e: 6919 ldr r1, [r3, #16]
|
|
8005710: 683b ldr r3, [r7, #0]
|
|
8005712: 681b ldr r3, [r3, #0]
|
|
8005714: b29b uxth r3, r3
|
|
8005716: 461a mov r2, r3
|
|
8005718: 4613 mov r3, r2
|
|
800571a: 005b lsls r3, r3, #1
|
|
800571c: 4413 add r3, r2
|
|
800571e: 2207 movs r2, #7
|
|
8005720: fa02 f303 lsl.w r3, r2, r3
|
|
8005724: 43da mvns r2, r3
|
|
8005726: 687b ldr r3, [r7, #4]
|
|
8005728: 681b ldr r3, [r3, #0]
|
|
800572a: 400a ands r2, r1
|
|
800572c: 611a str r2, [r3, #16]
|
|
|
|
/* Set the new sample time */
|
|
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
|
|
800572e: 687b ldr r3, [r7, #4]
|
|
8005730: 681b ldr r3, [r3, #0]
|
|
8005732: 6919 ldr r1, [r3, #16]
|
|
8005734: 683b ldr r3, [r7, #0]
|
|
8005736: 689a ldr r2, [r3, #8]
|
|
8005738: 683b ldr r3, [r7, #0]
|
|
800573a: 681b ldr r3, [r3, #0]
|
|
800573c: b29b uxth r3, r3
|
|
800573e: 4618 mov r0, r3
|
|
8005740: 4603 mov r3, r0
|
|
8005742: 005b lsls r3, r3, #1
|
|
8005744: 4403 add r3, r0
|
|
8005746: 409a lsls r2, r3
|
|
8005748: 687b ldr r3, [r7, #4]
|
|
800574a: 681b ldr r3, [r3, #0]
|
|
800574c: 430a orrs r2, r1
|
|
800574e: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
/* For Rank 1 to 6 */
|
|
if (sConfig->Rank < 7)
|
|
8005750: 683b ldr r3, [r7, #0]
|
|
8005752: 685b ldr r3, [r3, #4]
|
|
8005754: 2b06 cmp r3, #6
|
|
8005756: d824 bhi.n 80057a2 <HAL_ADC_ConfigChannel+0x13a>
|
|
{
|
|
/* Clear the old SQx bits for the selected rank */
|
|
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
|
|
8005758: 687b ldr r3, [r7, #4]
|
|
800575a: 681b ldr r3, [r3, #0]
|
|
800575c: 6b59 ldr r1, [r3, #52] ; 0x34
|
|
800575e: 683b ldr r3, [r7, #0]
|
|
8005760: 685a ldr r2, [r3, #4]
|
|
8005762: 4613 mov r3, r2
|
|
8005764: 009b lsls r3, r3, #2
|
|
8005766: 4413 add r3, r2
|
|
8005768: 3b05 subs r3, #5
|
|
800576a: 221f movs r2, #31
|
|
800576c: fa02 f303 lsl.w r3, r2, r3
|
|
8005770: 43da mvns r2, r3
|
|
8005772: 687b ldr r3, [r7, #4]
|
|
8005774: 681b ldr r3, [r3, #0]
|
|
8005776: 400a ands r2, r1
|
|
8005778: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Set the SQx bits for the selected rank */
|
|
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
|
|
800577a: 687b ldr r3, [r7, #4]
|
|
800577c: 681b ldr r3, [r3, #0]
|
|
800577e: 6b59 ldr r1, [r3, #52] ; 0x34
|
|
8005780: 683b ldr r3, [r7, #0]
|
|
8005782: 681b ldr r3, [r3, #0]
|
|
8005784: b29b uxth r3, r3
|
|
8005786: 4618 mov r0, r3
|
|
8005788: 683b ldr r3, [r7, #0]
|
|
800578a: 685a ldr r2, [r3, #4]
|
|
800578c: 4613 mov r3, r2
|
|
800578e: 009b lsls r3, r3, #2
|
|
8005790: 4413 add r3, r2
|
|
8005792: 3b05 subs r3, #5
|
|
8005794: fa00 f203 lsl.w r2, r0, r3
|
|
8005798: 687b ldr r3, [r7, #4]
|
|
800579a: 681b ldr r3, [r3, #0]
|
|
800579c: 430a orrs r2, r1
|
|
800579e: 635a str r2, [r3, #52] ; 0x34
|
|
80057a0: e04c b.n 800583c <HAL_ADC_ConfigChannel+0x1d4>
|
|
}
|
|
/* For Rank 7 to 12 */
|
|
else if (sConfig->Rank < 13)
|
|
80057a2: 683b ldr r3, [r7, #0]
|
|
80057a4: 685b ldr r3, [r3, #4]
|
|
80057a6: 2b0c cmp r3, #12
|
|
80057a8: d824 bhi.n 80057f4 <HAL_ADC_ConfigChannel+0x18c>
|
|
{
|
|
/* Clear the old SQx bits for the selected rank */
|
|
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
|
|
80057aa: 687b ldr r3, [r7, #4]
|
|
80057ac: 681b ldr r3, [r3, #0]
|
|
80057ae: 6b19 ldr r1, [r3, #48] ; 0x30
|
|
80057b0: 683b ldr r3, [r7, #0]
|
|
80057b2: 685a ldr r2, [r3, #4]
|
|
80057b4: 4613 mov r3, r2
|
|
80057b6: 009b lsls r3, r3, #2
|
|
80057b8: 4413 add r3, r2
|
|
80057ba: 3b23 subs r3, #35 ; 0x23
|
|
80057bc: 221f movs r2, #31
|
|
80057be: fa02 f303 lsl.w r3, r2, r3
|
|
80057c2: 43da mvns r2, r3
|
|
80057c4: 687b ldr r3, [r7, #4]
|
|
80057c6: 681b ldr r3, [r3, #0]
|
|
80057c8: 400a ands r2, r1
|
|
80057ca: 631a str r2, [r3, #48] ; 0x30
|
|
|
|
/* Set the SQx bits for the selected rank */
|
|
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
|
|
80057cc: 687b ldr r3, [r7, #4]
|
|
80057ce: 681b ldr r3, [r3, #0]
|
|
80057d0: 6b19 ldr r1, [r3, #48] ; 0x30
|
|
80057d2: 683b ldr r3, [r7, #0]
|
|
80057d4: 681b ldr r3, [r3, #0]
|
|
80057d6: b29b uxth r3, r3
|
|
80057d8: 4618 mov r0, r3
|
|
80057da: 683b ldr r3, [r7, #0]
|
|
80057dc: 685a ldr r2, [r3, #4]
|
|
80057de: 4613 mov r3, r2
|
|
80057e0: 009b lsls r3, r3, #2
|
|
80057e2: 4413 add r3, r2
|
|
80057e4: 3b23 subs r3, #35 ; 0x23
|
|
80057e6: fa00 f203 lsl.w r2, r0, r3
|
|
80057ea: 687b ldr r3, [r7, #4]
|
|
80057ec: 681b ldr r3, [r3, #0]
|
|
80057ee: 430a orrs r2, r1
|
|
80057f0: 631a str r2, [r3, #48] ; 0x30
|
|
80057f2: e023 b.n 800583c <HAL_ADC_ConfigChannel+0x1d4>
|
|
}
|
|
/* For Rank 13 to 16 */
|
|
else
|
|
{
|
|
/* Clear the old SQx bits for the selected rank */
|
|
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
|
|
80057f4: 687b ldr r3, [r7, #4]
|
|
80057f6: 681b ldr r3, [r3, #0]
|
|
80057f8: 6ad9 ldr r1, [r3, #44] ; 0x2c
|
|
80057fa: 683b ldr r3, [r7, #0]
|
|
80057fc: 685a ldr r2, [r3, #4]
|
|
80057fe: 4613 mov r3, r2
|
|
8005800: 009b lsls r3, r3, #2
|
|
8005802: 4413 add r3, r2
|
|
8005804: 3b41 subs r3, #65 ; 0x41
|
|
8005806: 221f movs r2, #31
|
|
8005808: fa02 f303 lsl.w r3, r2, r3
|
|
800580c: 43da mvns r2, r3
|
|
800580e: 687b ldr r3, [r7, #4]
|
|
8005810: 681b ldr r3, [r3, #0]
|
|
8005812: 400a ands r2, r1
|
|
8005814: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the SQx bits for the selected rank */
|
|
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
|
|
8005816: 687b ldr r3, [r7, #4]
|
|
8005818: 681b ldr r3, [r3, #0]
|
|
800581a: 6ad9 ldr r1, [r3, #44] ; 0x2c
|
|
800581c: 683b ldr r3, [r7, #0]
|
|
800581e: 681b ldr r3, [r3, #0]
|
|
8005820: b29b uxth r3, r3
|
|
8005822: 4618 mov r0, r3
|
|
8005824: 683b ldr r3, [r7, #0]
|
|
8005826: 685a ldr r2, [r3, #4]
|
|
8005828: 4613 mov r3, r2
|
|
800582a: 009b lsls r3, r3, #2
|
|
800582c: 4413 add r3, r2
|
|
800582e: 3b41 subs r3, #65 ; 0x41
|
|
8005830: fa00 f203 lsl.w r2, r0, r3
|
|
8005834: 687b ldr r3, [r7, #4]
|
|
8005836: 681b ldr r3, [r3, #0]
|
|
8005838: 430a orrs r2, r1
|
|
800583a: 62da str r2, [r3, #44] ; 0x2c
|
|
}
|
|
|
|
/* if no internal channel selected */
|
|
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
|
|
800583c: 687b ldr r3, [r7, #4]
|
|
800583e: 681b ldr r3, [r3, #0]
|
|
8005840: 4a2a ldr r2, [pc, #168] ; (80058ec <HAL_ADC_ConfigChannel+0x284>)
|
|
8005842: 4293 cmp r3, r2
|
|
8005844: d10a bne.n 800585c <HAL_ADC_ConfigChannel+0x1f4>
|
|
8005846: 683b ldr r3, [r7, #0]
|
|
8005848: 681b ldr r3, [r3, #0]
|
|
800584a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
|
|
800584e: d105 bne.n 800585c <HAL_ADC_ConfigChannel+0x1f4>
|
|
{
|
|
/* Disable the VBAT & TSVREFE channel*/
|
|
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
|
|
8005850: 4b27 ldr r3, [pc, #156] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
8005852: 685b ldr r3, [r3, #4]
|
|
8005854: 4a26 ldr r2, [pc, #152] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
8005856: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000
|
|
800585a: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* if ADC1 Channel_18 is selected enable VBAT Channel */
|
|
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
|
|
800585c: 687b ldr r3, [r7, #4]
|
|
800585e: 681b ldr r3, [r3, #0]
|
|
8005860: 4a22 ldr r2, [pc, #136] ; (80058ec <HAL_ADC_ConfigChannel+0x284>)
|
|
8005862: 4293 cmp r3, r2
|
|
8005864: d109 bne.n 800587a <HAL_ADC_ConfigChannel+0x212>
|
|
8005866: 683b ldr r3, [r7, #0]
|
|
8005868: 681b ldr r3, [r3, #0]
|
|
800586a: 2b12 cmp r3, #18
|
|
800586c: d105 bne.n 800587a <HAL_ADC_ConfigChannel+0x212>
|
|
{
|
|
/* Enable the VBAT channel*/
|
|
ADC->CCR |= ADC_CCR_VBATE;
|
|
800586e: 4b20 ldr r3, [pc, #128] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
8005870: 685b ldr r3, [r3, #4]
|
|
8005872: 4a1f ldr r2, [pc, #124] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
8005874: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
|
|
8005878: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
|
|
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
|
|
800587a: 687b ldr r3, [r7, #4]
|
|
800587c: 681b ldr r3, [r3, #0]
|
|
800587e: 4a1b ldr r2, [pc, #108] ; (80058ec <HAL_ADC_ConfigChannel+0x284>)
|
|
8005880: 4293 cmp r3, r2
|
|
8005882: d125 bne.n 80058d0 <HAL_ADC_ConfigChannel+0x268>
|
|
8005884: 683b ldr r3, [r7, #0]
|
|
8005886: 681b ldr r3, [r3, #0]
|
|
8005888: 4a17 ldr r2, [pc, #92] ; (80058e8 <HAL_ADC_ConfigChannel+0x280>)
|
|
800588a: 4293 cmp r3, r2
|
|
800588c: d003 beq.n 8005896 <HAL_ADC_ConfigChannel+0x22e>
|
|
800588e: 683b ldr r3, [r7, #0]
|
|
8005890: 681b ldr r3, [r3, #0]
|
|
8005892: 2b11 cmp r3, #17
|
|
8005894: d11c bne.n 80058d0 <HAL_ADC_ConfigChannel+0x268>
|
|
{
|
|
/* Enable the TSVREFE channel*/
|
|
ADC->CCR |= ADC_CCR_TSVREFE;
|
|
8005896: 4b16 ldr r3, [pc, #88] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
8005898: 685b ldr r3, [r3, #4]
|
|
800589a: 4a15 ldr r2, [pc, #84] ; (80058f0 <HAL_ADC_ConfigChannel+0x288>)
|
|
800589c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
|
|
80058a0: 6053 str r3, [r2, #4]
|
|
|
|
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
80058a2: 683b ldr r3, [r7, #0]
|
|
80058a4: 681b ldr r3, [r3, #0]
|
|
80058a6: 4a10 ldr r2, [pc, #64] ; (80058e8 <HAL_ADC_ConfigChannel+0x280>)
|
|
80058a8: 4293 cmp r3, r2
|
|
80058aa: d111 bne.n 80058d0 <HAL_ADC_ConfigChannel+0x268>
|
|
{
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Compute number of CPU cycles to wait for */
|
|
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
|
|
80058ac: 4b11 ldr r3, [pc, #68] ; (80058f4 <HAL_ADC_ConfigChannel+0x28c>)
|
|
80058ae: 681b ldr r3, [r3, #0]
|
|
80058b0: 4a11 ldr r2, [pc, #68] ; (80058f8 <HAL_ADC_ConfigChannel+0x290>)
|
|
80058b2: fba2 2303 umull r2, r3, r2, r3
|
|
80058b6: 0c9a lsrs r2, r3, #18
|
|
80058b8: 4613 mov r3, r2
|
|
80058ba: 009b lsls r3, r3, #2
|
|
80058bc: 4413 add r3, r2
|
|
80058be: 005b lsls r3, r3, #1
|
|
80058c0: 60fb str r3, [r7, #12]
|
|
while(counter != 0)
|
|
80058c2: e002 b.n 80058ca <HAL_ADC_ConfigChannel+0x262>
|
|
{
|
|
counter--;
|
|
80058c4: 68fb ldr r3, [r7, #12]
|
|
80058c6: 3b01 subs r3, #1
|
|
80058c8: 60fb str r3, [r7, #12]
|
|
while(counter != 0)
|
|
80058ca: 68fb ldr r3, [r7, #12]
|
|
80058cc: 2b00 cmp r3, #0
|
|
80058ce: d1f9 bne.n 80058c4 <HAL_ADC_ConfigChannel+0x25c>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
80058d0: 687b ldr r3, [r7, #4]
|
|
80058d2: 2200 movs r2, #0
|
|
80058d4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80058d8: 2300 movs r3, #0
|
|
}
|
|
80058da: 4618 mov r0, r3
|
|
80058dc: 3714 adds r7, #20
|
|
80058de: 46bd mov sp, r7
|
|
80058e0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80058e4: 4770 bx lr
|
|
80058e6: bf00 nop
|
|
80058e8: 10000012 .word 0x10000012
|
|
80058ec: 40012000 .word 0x40012000
|
|
80058f0: 40012300 .word 0x40012300
|
|
80058f4: 20000064 .word 0x20000064
|
|
80058f8: 431bde83 .word 0x431bde83
|
|
|
|
080058fc <ADC_Init>:
|
|
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified ADC.
|
|
* @retval None
|
|
*/
|
|
static void ADC_Init(ADC_HandleTypeDef* hadc)
|
|
{
|
|
80058fc: b480 push {r7}
|
|
80058fe: b083 sub sp, #12
|
|
8005900: af00 add r7, sp, #0
|
|
8005902: 6078 str r0, [r7, #4]
|
|
/* Set ADC parameters */
|
|
/* Set the ADC clock prescaler */
|
|
ADC->CCR &= ~(ADC_CCR_ADCPRE);
|
|
8005904: 4b78 ldr r3, [pc, #480] ; (8005ae8 <ADC_Init+0x1ec>)
|
|
8005906: 685b ldr r3, [r3, #4]
|
|
8005908: 4a77 ldr r2, [pc, #476] ; (8005ae8 <ADC_Init+0x1ec>)
|
|
800590a: f423 3340 bic.w r3, r3, #196608 ; 0x30000
|
|
800590e: 6053 str r3, [r2, #4]
|
|
ADC->CCR |= hadc->Init.ClockPrescaler;
|
|
8005910: 4b75 ldr r3, [pc, #468] ; (8005ae8 <ADC_Init+0x1ec>)
|
|
8005912: 685a ldr r2, [r3, #4]
|
|
8005914: 687b ldr r3, [r7, #4]
|
|
8005916: 685b ldr r3, [r3, #4]
|
|
8005918: 4973 ldr r1, [pc, #460] ; (8005ae8 <ADC_Init+0x1ec>)
|
|
800591a: 4313 orrs r3, r2
|
|
800591c: 604b str r3, [r1, #4]
|
|
|
|
/* Set ADC scan mode */
|
|
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
|
|
800591e: 687b ldr r3, [r7, #4]
|
|
8005920: 681b ldr r3, [r3, #0]
|
|
8005922: 685a ldr r2, [r3, #4]
|
|
8005924: 687b ldr r3, [r7, #4]
|
|
8005926: 681b ldr r3, [r3, #0]
|
|
8005928: f422 7280 bic.w r2, r2, #256 ; 0x100
|
|
800592c: 605a str r2, [r3, #4]
|
|
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
|
|
800592e: 687b ldr r3, [r7, #4]
|
|
8005930: 681b ldr r3, [r3, #0]
|
|
8005932: 6859 ldr r1, [r3, #4]
|
|
8005934: 687b ldr r3, [r7, #4]
|
|
8005936: 691b ldr r3, [r3, #16]
|
|
8005938: 021a lsls r2, r3, #8
|
|
800593a: 687b ldr r3, [r7, #4]
|
|
800593c: 681b ldr r3, [r3, #0]
|
|
800593e: 430a orrs r2, r1
|
|
8005940: 605a str r2, [r3, #4]
|
|
|
|
/* Set ADC resolution */
|
|
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
|
|
8005942: 687b ldr r3, [r7, #4]
|
|
8005944: 681b ldr r3, [r3, #0]
|
|
8005946: 685a ldr r2, [r3, #4]
|
|
8005948: 687b ldr r3, [r7, #4]
|
|
800594a: 681b ldr r3, [r3, #0]
|
|
800594c: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
|
|
8005950: 605a str r2, [r3, #4]
|
|
hadc->Instance->CR1 |= hadc->Init.Resolution;
|
|
8005952: 687b ldr r3, [r7, #4]
|
|
8005954: 681b ldr r3, [r3, #0]
|
|
8005956: 6859 ldr r1, [r3, #4]
|
|
8005958: 687b ldr r3, [r7, #4]
|
|
800595a: 689a ldr r2, [r3, #8]
|
|
800595c: 687b ldr r3, [r7, #4]
|
|
800595e: 681b ldr r3, [r3, #0]
|
|
8005960: 430a orrs r2, r1
|
|
8005962: 605a str r2, [r3, #4]
|
|
|
|
/* Set ADC data alignment */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
|
|
8005964: 687b ldr r3, [r7, #4]
|
|
8005966: 681b ldr r3, [r3, #0]
|
|
8005968: 689a ldr r2, [r3, #8]
|
|
800596a: 687b ldr r3, [r7, #4]
|
|
800596c: 681b ldr r3, [r3, #0]
|
|
800596e: f422 6200 bic.w r2, r2, #2048 ; 0x800
|
|
8005972: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= hadc->Init.DataAlign;
|
|
8005974: 687b ldr r3, [r7, #4]
|
|
8005976: 681b ldr r3, [r3, #0]
|
|
8005978: 6899 ldr r1, [r3, #8]
|
|
800597a: 687b ldr r3, [r7, #4]
|
|
800597c: 68da ldr r2, [r3, #12]
|
|
800597e: 687b ldr r3, [r7, #4]
|
|
8005980: 681b ldr r3, [r3, #0]
|
|
8005982: 430a orrs r2, r1
|
|
8005984: 609a str r2, [r3, #8]
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
8005986: 687b ldr r3, [r7, #4]
|
|
8005988: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800598a: 4a58 ldr r2, [pc, #352] ; (8005aec <ADC_Init+0x1f0>)
|
|
800598c: 4293 cmp r3, r2
|
|
800598e: d022 beq.n 80059d6 <ADC_Init+0xda>
|
|
{
|
|
/* Select external trigger to start conversion */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
|
|
8005990: 687b ldr r3, [r7, #4]
|
|
8005992: 681b ldr r3, [r3, #0]
|
|
8005994: 689a ldr r2, [r3, #8]
|
|
8005996: 687b ldr r3, [r7, #4]
|
|
8005998: 681b ldr r3, [r3, #0]
|
|
800599a: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
|
|
800599e: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
|
|
80059a0: 687b ldr r3, [r7, #4]
|
|
80059a2: 681b ldr r3, [r3, #0]
|
|
80059a4: 6899 ldr r1, [r3, #8]
|
|
80059a6: 687b ldr r3, [r7, #4]
|
|
80059a8: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
80059aa: 687b ldr r3, [r7, #4]
|
|
80059ac: 681b ldr r3, [r3, #0]
|
|
80059ae: 430a orrs r2, r1
|
|
80059b0: 609a str r2, [r3, #8]
|
|
|
|
/* Select external trigger polarity */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
|
|
80059b2: 687b ldr r3, [r7, #4]
|
|
80059b4: 681b ldr r3, [r3, #0]
|
|
80059b6: 689a ldr r2, [r3, #8]
|
|
80059b8: 687b ldr r3, [r7, #4]
|
|
80059ba: 681b ldr r3, [r3, #0]
|
|
80059bc: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
|
|
80059c0: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
|
|
80059c2: 687b ldr r3, [r7, #4]
|
|
80059c4: 681b ldr r3, [r3, #0]
|
|
80059c6: 6899 ldr r1, [r3, #8]
|
|
80059c8: 687b ldr r3, [r7, #4]
|
|
80059ca: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
80059cc: 687b ldr r3, [r7, #4]
|
|
80059ce: 681b ldr r3, [r3, #0]
|
|
80059d0: 430a orrs r2, r1
|
|
80059d2: 609a str r2, [r3, #8]
|
|
80059d4: e00f b.n 80059f6 <ADC_Init+0xfa>
|
|
}
|
|
else
|
|
{
|
|
/* Reset the external trigger */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
|
|
80059d6: 687b ldr r3, [r7, #4]
|
|
80059d8: 681b ldr r3, [r3, #0]
|
|
80059da: 689a ldr r2, [r3, #8]
|
|
80059dc: 687b ldr r3, [r7, #4]
|
|
80059de: 681b ldr r3, [r3, #0]
|
|
80059e0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
|
|
80059e4: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
|
|
80059e6: 687b ldr r3, [r7, #4]
|
|
80059e8: 681b ldr r3, [r3, #0]
|
|
80059ea: 689a ldr r2, [r3, #8]
|
|
80059ec: 687b ldr r3, [r7, #4]
|
|
80059ee: 681b ldr r3, [r3, #0]
|
|
80059f0: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
|
|
80059f4: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Enable or disable ADC continuous conversion mode */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
|
|
80059f6: 687b ldr r3, [r7, #4]
|
|
80059f8: 681b ldr r3, [r3, #0]
|
|
80059fa: 689a ldr r2, [r3, #8]
|
|
80059fc: 687b ldr r3, [r7, #4]
|
|
80059fe: 681b ldr r3, [r3, #0]
|
|
8005a00: f022 0202 bic.w r2, r2, #2
|
|
8005a04: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
|
|
8005a06: 687b ldr r3, [r7, #4]
|
|
8005a08: 681b ldr r3, [r3, #0]
|
|
8005a0a: 6899 ldr r1, [r3, #8]
|
|
8005a0c: 687b ldr r3, [r7, #4]
|
|
8005a0e: 699b ldr r3, [r3, #24]
|
|
8005a10: 005a lsls r2, r3, #1
|
|
8005a12: 687b ldr r3, [r7, #4]
|
|
8005a14: 681b ldr r3, [r3, #0]
|
|
8005a16: 430a orrs r2, r1
|
|
8005a18: 609a str r2, [r3, #8]
|
|
|
|
if(hadc->Init.DiscontinuousConvMode != DISABLE)
|
|
8005a1a: 687b ldr r3, [r7, #4]
|
|
8005a1c: f893 3020 ldrb.w r3, [r3, #32]
|
|
8005a20: 2b00 cmp r3, #0
|
|
8005a22: d01b beq.n 8005a5c <ADC_Init+0x160>
|
|
{
|
|
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
|
|
|
|
/* Enable the selected ADC regular discontinuous mode */
|
|
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
|
|
8005a24: 687b ldr r3, [r7, #4]
|
|
8005a26: 681b ldr r3, [r3, #0]
|
|
8005a28: 685a ldr r2, [r3, #4]
|
|
8005a2a: 687b ldr r3, [r7, #4]
|
|
8005a2c: 681b ldr r3, [r3, #0]
|
|
8005a2e: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
8005a32: 605a str r2, [r3, #4]
|
|
|
|
/* Set the number of channels to be converted in discontinuous mode */
|
|
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
|
|
8005a34: 687b ldr r3, [r7, #4]
|
|
8005a36: 681b ldr r3, [r3, #0]
|
|
8005a38: 685a ldr r2, [r3, #4]
|
|
8005a3a: 687b ldr r3, [r7, #4]
|
|
8005a3c: 681b ldr r3, [r3, #0]
|
|
8005a3e: f422 4260 bic.w r2, r2, #57344 ; 0xe000
|
|
8005a42: 605a str r2, [r3, #4]
|
|
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
|
|
8005a44: 687b ldr r3, [r7, #4]
|
|
8005a46: 681b ldr r3, [r3, #0]
|
|
8005a48: 6859 ldr r1, [r3, #4]
|
|
8005a4a: 687b ldr r3, [r7, #4]
|
|
8005a4c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8005a4e: 3b01 subs r3, #1
|
|
8005a50: 035a lsls r2, r3, #13
|
|
8005a52: 687b ldr r3, [r7, #4]
|
|
8005a54: 681b ldr r3, [r3, #0]
|
|
8005a56: 430a orrs r2, r1
|
|
8005a58: 605a str r2, [r3, #4]
|
|
8005a5a: e007 b.n 8005a6c <ADC_Init+0x170>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the selected ADC regular discontinuous mode */
|
|
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
|
|
8005a5c: 687b ldr r3, [r7, #4]
|
|
8005a5e: 681b ldr r3, [r3, #0]
|
|
8005a60: 685a ldr r2, [r3, #4]
|
|
8005a62: 687b ldr r3, [r7, #4]
|
|
8005a64: 681b ldr r3, [r3, #0]
|
|
8005a66: f422 6200 bic.w r2, r2, #2048 ; 0x800
|
|
8005a6a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Set ADC number of conversion */
|
|
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
|
|
8005a6c: 687b ldr r3, [r7, #4]
|
|
8005a6e: 681b ldr r3, [r3, #0]
|
|
8005a70: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
8005a72: 687b ldr r3, [r7, #4]
|
|
8005a74: 681b ldr r3, [r3, #0]
|
|
8005a76: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
|
|
8005a7a: 62da str r2, [r3, #44] ; 0x2c
|
|
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
|
|
8005a7c: 687b ldr r3, [r7, #4]
|
|
8005a7e: 681b ldr r3, [r3, #0]
|
|
8005a80: 6ad9 ldr r1, [r3, #44] ; 0x2c
|
|
8005a82: 687b ldr r3, [r7, #4]
|
|
8005a84: 69db ldr r3, [r3, #28]
|
|
8005a86: 3b01 subs r3, #1
|
|
8005a88: 051a lsls r2, r3, #20
|
|
8005a8a: 687b ldr r3, [r7, #4]
|
|
8005a8c: 681b ldr r3, [r3, #0]
|
|
8005a8e: 430a orrs r2, r1
|
|
8005a90: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Enable or disable ADC DMA continuous request */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
|
|
8005a92: 687b ldr r3, [r7, #4]
|
|
8005a94: 681b ldr r3, [r3, #0]
|
|
8005a96: 689a ldr r2, [r3, #8]
|
|
8005a98: 687b ldr r3, [r7, #4]
|
|
8005a9a: 681b ldr r3, [r3, #0]
|
|
8005a9c: f422 7200 bic.w r2, r2, #512 ; 0x200
|
|
8005aa0: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
|
|
8005aa2: 687b ldr r3, [r7, #4]
|
|
8005aa4: 681b ldr r3, [r3, #0]
|
|
8005aa6: 6899 ldr r1, [r3, #8]
|
|
8005aa8: 687b ldr r3, [r7, #4]
|
|
8005aaa: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
8005aae: 025a lsls r2, r3, #9
|
|
8005ab0: 687b ldr r3, [r7, #4]
|
|
8005ab2: 681b ldr r3, [r3, #0]
|
|
8005ab4: 430a orrs r2, r1
|
|
8005ab6: 609a str r2, [r3, #8]
|
|
|
|
/* Enable or disable ADC end of conversion selection */
|
|
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
|
|
8005ab8: 687b ldr r3, [r7, #4]
|
|
8005aba: 681b ldr r3, [r3, #0]
|
|
8005abc: 689a ldr r2, [r3, #8]
|
|
8005abe: 687b ldr r3, [r7, #4]
|
|
8005ac0: 681b ldr r3, [r3, #0]
|
|
8005ac2: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
8005ac6: 609a str r2, [r3, #8]
|
|
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
|
|
8005ac8: 687b ldr r3, [r7, #4]
|
|
8005aca: 681b ldr r3, [r3, #0]
|
|
8005acc: 6899 ldr r1, [r3, #8]
|
|
8005ace: 687b ldr r3, [r7, #4]
|
|
8005ad0: 695b ldr r3, [r3, #20]
|
|
8005ad2: 029a lsls r2, r3, #10
|
|
8005ad4: 687b ldr r3, [r7, #4]
|
|
8005ad6: 681b ldr r3, [r3, #0]
|
|
8005ad8: 430a orrs r2, r1
|
|
8005ada: 609a str r2, [r3, #8]
|
|
}
|
|
8005adc: bf00 nop
|
|
8005ade: 370c adds r7, #12
|
|
8005ae0: 46bd mov sp, r7
|
|
8005ae2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ae6: 4770 bx lr
|
|
8005ae8: 40012300 .word 0x40012300
|
|
8005aec: 0f000001 .word 0x0f000001
|
|
|
|
08005af0 <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8005af0: b480 push {r7}
|
|
8005af2: b085 sub sp, #20
|
|
8005af4: af00 add r7, sp, #0
|
|
8005af6: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8005af8: 687b ldr r3, [r7, #4]
|
|
8005afa: f003 0307 and.w r3, r3, #7
|
|
8005afe: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
8005b00: 4b0b ldr r3, [pc, #44] ; (8005b30 <__NVIC_SetPriorityGrouping+0x40>)
|
|
8005b02: 68db ldr r3, [r3, #12]
|
|
8005b04: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8005b06: 68ba ldr r2, [r7, #8]
|
|
8005b08: f64f 03ff movw r3, #63743 ; 0xf8ff
|
|
8005b0c: 4013 ands r3, r2
|
|
8005b0e: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
8005b10: 68fb ldr r3, [r7, #12]
|
|
8005b12: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8005b14: 68bb ldr r3, [r7, #8]
|
|
8005b16: 431a orrs r2, r3
|
|
reg_value = (reg_value |
|
|
8005b18: 4b06 ldr r3, [pc, #24] ; (8005b34 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8005b1a: 4313 orrs r3, r2
|
|
8005b1c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
8005b1e: 4a04 ldr r2, [pc, #16] ; (8005b30 <__NVIC_SetPriorityGrouping+0x40>)
|
|
8005b20: 68bb ldr r3, [r7, #8]
|
|
8005b22: 60d3 str r3, [r2, #12]
|
|
}
|
|
8005b24: bf00 nop
|
|
8005b26: 3714 adds r7, #20
|
|
8005b28: 46bd mov sp, r7
|
|
8005b2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005b2e: 4770 bx lr
|
|
8005b30: e000ed00 .word 0xe000ed00
|
|
8005b34: 05fa0000 .word 0x05fa0000
|
|
|
|
08005b38 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8005b38: b480 push {r7}
|
|
8005b3a: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8005b3c: 4b04 ldr r3, [pc, #16] ; (8005b50 <__NVIC_GetPriorityGrouping+0x18>)
|
|
8005b3e: 68db ldr r3, [r3, #12]
|
|
8005b40: 0a1b lsrs r3, r3, #8
|
|
8005b42: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8005b46: 4618 mov r0, r3
|
|
8005b48: 46bd mov sp, r7
|
|
8005b4a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005b4e: 4770 bx lr
|
|
8005b50: e000ed00 .word 0xe000ed00
|
|
|
|
08005b54 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8005b54: b480 push {r7}
|
|
8005b56: b083 sub sp, #12
|
|
8005b58: af00 add r7, sp, #0
|
|
8005b5a: 4603 mov r3, r0
|
|
8005b5c: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8005b5e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8005b62: 2b00 cmp r3, #0
|
|
8005b64: db0b blt.n 8005b7e <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8005b66: 79fb ldrb r3, [r7, #7]
|
|
8005b68: f003 021f and.w r2, r3, #31
|
|
8005b6c: 4907 ldr r1, [pc, #28] ; (8005b8c <__NVIC_EnableIRQ+0x38>)
|
|
8005b6e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8005b72: 095b lsrs r3, r3, #5
|
|
8005b74: 2001 movs r0, #1
|
|
8005b76: fa00 f202 lsl.w r2, r0, r2
|
|
8005b7a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
}
|
|
8005b7e: bf00 nop
|
|
8005b80: 370c adds r7, #12
|
|
8005b82: 46bd mov sp, r7
|
|
8005b84: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005b88: 4770 bx lr
|
|
8005b8a: bf00 nop
|
|
8005b8c: e000e100 .word 0xe000e100
|
|
|
|
08005b90 <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
8005b90: b480 push {r7}
|
|
8005b92: b083 sub sp, #12
|
|
8005b94: af00 add r7, sp, #0
|
|
8005b96: 4603 mov r3, r0
|
|
8005b98: 6039 str r1, [r7, #0]
|
|
8005b9a: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8005b9c: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8005ba0: 2b00 cmp r3, #0
|
|
8005ba2: db0a blt.n 8005bba <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8005ba4: 683b ldr r3, [r7, #0]
|
|
8005ba6: b2da uxtb r2, r3
|
|
8005ba8: 490c ldr r1, [pc, #48] ; (8005bdc <__NVIC_SetPriority+0x4c>)
|
|
8005baa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8005bae: 0112 lsls r2, r2, #4
|
|
8005bb0: b2d2 uxtb r2, r2
|
|
8005bb2: 440b add r3, r1
|
|
8005bb4: f883 2300 strb.w r2, [r3, #768] ; 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8005bb8: e00a b.n 8005bd0 <__NVIC_SetPriority+0x40>
|
|
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8005bba: 683b ldr r3, [r7, #0]
|
|
8005bbc: b2da uxtb r2, r3
|
|
8005bbe: 4908 ldr r1, [pc, #32] ; (8005be0 <__NVIC_SetPriority+0x50>)
|
|
8005bc0: 79fb ldrb r3, [r7, #7]
|
|
8005bc2: f003 030f and.w r3, r3, #15
|
|
8005bc6: 3b04 subs r3, #4
|
|
8005bc8: 0112 lsls r2, r2, #4
|
|
8005bca: b2d2 uxtb r2, r2
|
|
8005bcc: 440b add r3, r1
|
|
8005bce: 761a strb r2, [r3, #24]
|
|
}
|
|
8005bd0: bf00 nop
|
|
8005bd2: 370c adds r7, #12
|
|
8005bd4: 46bd mov sp, r7
|
|
8005bd6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005bda: 4770 bx lr
|
|
8005bdc: e000e100 .word 0xe000e100
|
|
8005be0: e000ed00 .word 0xe000ed00
|
|
|
|
08005be4 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8005be4: b480 push {r7}
|
|
8005be6: b089 sub sp, #36 ; 0x24
|
|
8005be8: af00 add r7, sp, #0
|
|
8005bea: 60f8 str r0, [r7, #12]
|
|
8005bec: 60b9 str r1, [r7, #8]
|
|
8005bee: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8005bf0: 68fb ldr r3, [r7, #12]
|
|
8005bf2: f003 0307 and.w r3, r3, #7
|
|
8005bf6: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8005bf8: 69fb ldr r3, [r7, #28]
|
|
8005bfa: f1c3 0307 rsb r3, r3, #7
|
|
8005bfe: 2b04 cmp r3, #4
|
|
8005c00: bf28 it cs
|
|
8005c02: 2304 movcs r3, #4
|
|
8005c04: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8005c06: 69fb ldr r3, [r7, #28]
|
|
8005c08: 3304 adds r3, #4
|
|
8005c0a: 2b06 cmp r3, #6
|
|
8005c0c: d902 bls.n 8005c14 <NVIC_EncodePriority+0x30>
|
|
8005c0e: 69fb ldr r3, [r7, #28]
|
|
8005c10: 3b03 subs r3, #3
|
|
8005c12: e000 b.n 8005c16 <NVIC_EncodePriority+0x32>
|
|
8005c14: 2300 movs r3, #0
|
|
8005c16: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8005c18: f04f 32ff mov.w r2, #4294967295
|
|
8005c1c: 69bb ldr r3, [r7, #24]
|
|
8005c1e: fa02 f303 lsl.w r3, r2, r3
|
|
8005c22: 43da mvns r2, r3
|
|
8005c24: 68bb ldr r3, [r7, #8]
|
|
8005c26: 401a ands r2, r3
|
|
8005c28: 697b ldr r3, [r7, #20]
|
|
8005c2a: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8005c2c: f04f 31ff mov.w r1, #4294967295
|
|
8005c30: 697b ldr r3, [r7, #20]
|
|
8005c32: fa01 f303 lsl.w r3, r1, r3
|
|
8005c36: 43d9 mvns r1, r3
|
|
8005c38: 687b ldr r3, [r7, #4]
|
|
8005c3a: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8005c3c: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
8005c3e: 4618 mov r0, r3
|
|
8005c40: 3724 adds r7, #36 ; 0x24
|
|
8005c42: 46bd mov sp, r7
|
|
8005c44: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c48: 4770 bx lr
|
|
|
|
08005c4a <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8005c4a: b580 push {r7, lr}
|
|
8005c4c: b082 sub sp, #8
|
|
8005c4e: af00 add r7, sp, #0
|
|
8005c50: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8005c52: 6878 ldr r0, [r7, #4]
|
|
8005c54: f7ff ff4c bl 8005af0 <__NVIC_SetPriorityGrouping>
|
|
}
|
|
8005c58: bf00 nop
|
|
8005c5a: 3708 adds r7, #8
|
|
8005c5c: 46bd mov sp, r7
|
|
8005c5e: bd80 pop {r7, pc}
|
|
|
|
08005c60 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8005c60: b580 push {r7, lr}
|
|
8005c62: b086 sub sp, #24
|
|
8005c64: af00 add r7, sp, #0
|
|
8005c66: 4603 mov r3, r0
|
|
8005c68: 60b9 str r1, [r7, #8]
|
|
8005c6a: 607a str r2, [r7, #4]
|
|
8005c6c: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8005c6e: 2300 movs r3, #0
|
|
8005c70: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8005c72: f7ff ff61 bl 8005b38 <__NVIC_GetPriorityGrouping>
|
|
8005c76: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
8005c78: 687a ldr r2, [r7, #4]
|
|
8005c7a: 68b9 ldr r1, [r7, #8]
|
|
8005c7c: 6978 ldr r0, [r7, #20]
|
|
8005c7e: f7ff ffb1 bl 8005be4 <NVIC_EncodePriority>
|
|
8005c82: 4602 mov r2, r0
|
|
8005c84: f997 300f ldrsb.w r3, [r7, #15]
|
|
8005c88: 4611 mov r1, r2
|
|
8005c8a: 4618 mov r0, r3
|
|
8005c8c: f7ff ff80 bl 8005b90 <__NVIC_SetPriority>
|
|
}
|
|
8005c90: bf00 nop
|
|
8005c92: 3718 adds r7, #24
|
|
8005c94: 46bd mov sp, r7
|
|
8005c96: bd80 pop {r7, pc}
|
|
|
|
08005c98 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8005c98: b580 push {r7, lr}
|
|
8005c9a: b082 sub sp, #8
|
|
8005c9c: af00 add r7, sp, #0
|
|
8005c9e: 4603 mov r3, r0
|
|
8005ca0: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
8005ca2: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8005ca6: 4618 mov r0, r3
|
|
8005ca8: f7ff ff54 bl 8005b54 <__NVIC_EnableIRQ>
|
|
}
|
|
8005cac: bf00 nop
|
|
8005cae: 3708 adds r7, #8
|
|
8005cb0: 46bd mov sp, r7
|
|
8005cb2: bd80 pop {r7, pc}
|
|
|
|
08005cb4 <HAL_CRC_Init>:
|
|
* parameters in the CRC_InitTypeDef and create the associated handle.
|
|
* @param hcrc CRC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
|
{
|
|
8005cb4: b580 push {r7, lr}
|
|
8005cb6: b082 sub sp, #8
|
|
8005cb8: af00 add r7, sp, #0
|
|
8005cba: 6078 str r0, [r7, #4]
|
|
/* Check the CRC handle allocation */
|
|
if (hcrc == NULL)
|
|
8005cbc: 687b ldr r3, [r7, #4]
|
|
8005cbe: 2b00 cmp r3, #0
|
|
8005cc0: d101 bne.n 8005cc6 <HAL_CRC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005cc2: 2301 movs r3, #1
|
|
8005cc4: e054 b.n 8005d70 <HAL_CRC_Init+0xbc>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
|
|
|
if (hcrc->State == HAL_CRC_STATE_RESET)
|
|
8005cc6: 687b ldr r3, [r7, #4]
|
|
8005cc8: 7f5b ldrb r3, [r3, #29]
|
|
8005cca: b2db uxtb r3, r3
|
|
8005ccc: 2b00 cmp r3, #0
|
|
8005cce: d105 bne.n 8005cdc <HAL_CRC_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hcrc->Lock = HAL_UNLOCKED;
|
|
8005cd0: 687b ldr r3, [r7, #4]
|
|
8005cd2: 2200 movs r2, #0
|
|
8005cd4: 771a strb r2, [r3, #28]
|
|
/* Init the low level hardware */
|
|
HAL_CRC_MspInit(hcrc);
|
|
8005cd6: 6878 ldr r0, [r7, #4]
|
|
8005cd8: f7fe fc90 bl 80045fc <HAL_CRC_MspInit>
|
|
}
|
|
|
|
hcrc->State = HAL_CRC_STATE_BUSY;
|
|
8005cdc: 687b ldr r3, [r7, #4]
|
|
8005cde: 2202 movs r2, #2
|
|
8005ce0: 775a strb r2, [r3, #29]
|
|
|
|
/* check whether or not non-default generating polynomial has been
|
|
* picked up by user */
|
|
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
|
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
|
8005ce2: 687b ldr r3, [r7, #4]
|
|
8005ce4: 791b ldrb r3, [r3, #4]
|
|
8005ce6: 2b00 cmp r3, #0
|
|
8005ce8: d10c bne.n 8005d04 <HAL_CRC_Init+0x50>
|
|
{
|
|
/* initialize peripheral with default generating polynomial */
|
|
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
|
8005cea: 687b ldr r3, [r7, #4]
|
|
8005cec: 681b ldr r3, [r3, #0]
|
|
8005cee: 4a22 ldr r2, [pc, #136] ; (8005d78 <HAL_CRC_Init+0xc4>)
|
|
8005cf0: 615a str r2, [r3, #20]
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
|
8005cf2: 687b ldr r3, [r7, #4]
|
|
8005cf4: 681b ldr r3, [r3, #0]
|
|
8005cf6: 689a ldr r2, [r3, #8]
|
|
8005cf8: 687b ldr r3, [r7, #4]
|
|
8005cfa: 681b ldr r3, [r3, #0]
|
|
8005cfc: f022 0218 bic.w r2, r2, #24
|
|
8005d00: 609a str r2, [r3, #8]
|
|
8005d02: e00c b.n 8005d1e <HAL_CRC_Init+0x6a>
|
|
}
|
|
else
|
|
{
|
|
/* initialize CRC peripheral with generating polynomial defined by user */
|
|
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
|
8005d04: 687b ldr r3, [r7, #4]
|
|
8005d06: 6899 ldr r1, [r3, #8]
|
|
8005d08: 687b ldr r3, [r7, #4]
|
|
8005d0a: 68db ldr r3, [r3, #12]
|
|
8005d0c: 461a mov r2, r3
|
|
8005d0e: 6878 ldr r0, [r7, #4]
|
|
8005d10: f000 f834 bl 8005d7c <HAL_CRCEx_Polynomial_Set>
|
|
8005d14: 4603 mov r3, r0
|
|
8005d16: 2b00 cmp r3, #0
|
|
8005d18: d001 beq.n 8005d1e <HAL_CRC_Init+0x6a>
|
|
{
|
|
return HAL_ERROR;
|
|
8005d1a: 2301 movs r3, #1
|
|
8005d1c: e028 b.n 8005d70 <HAL_CRC_Init+0xbc>
|
|
}
|
|
|
|
/* check whether or not non-default CRC initial value has been
|
|
* picked up by user */
|
|
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
|
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
|
8005d1e: 687b ldr r3, [r7, #4]
|
|
8005d20: 795b ldrb r3, [r3, #5]
|
|
8005d22: 2b00 cmp r3, #0
|
|
8005d24: d105 bne.n 8005d32 <HAL_CRC_Init+0x7e>
|
|
{
|
|
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
|
8005d26: 687b ldr r3, [r7, #4]
|
|
8005d28: 681b ldr r3, [r3, #0]
|
|
8005d2a: f04f 32ff mov.w r2, #4294967295
|
|
8005d2e: 611a str r2, [r3, #16]
|
|
8005d30: e004 b.n 8005d3c <HAL_CRC_Init+0x88>
|
|
}
|
|
else
|
|
{
|
|
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
|
8005d32: 687b ldr r3, [r7, #4]
|
|
8005d34: 681b ldr r3, [r3, #0]
|
|
8005d36: 687a ldr r2, [r7, #4]
|
|
8005d38: 6912 ldr r2, [r2, #16]
|
|
8005d3a: 611a str r2, [r3, #16]
|
|
}
|
|
|
|
|
|
/* set input data inversion mode */
|
|
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
|
8005d3c: 687b ldr r3, [r7, #4]
|
|
8005d3e: 681b ldr r3, [r3, #0]
|
|
8005d40: 689b ldr r3, [r3, #8]
|
|
8005d42: f023 0160 bic.w r1, r3, #96 ; 0x60
|
|
8005d46: 687b ldr r3, [r7, #4]
|
|
8005d48: 695a ldr r2, [r3, #20]
|
|
8005d4a: 687b ldr r3, [r7, #4]
|
|
8005d4c: 681b ldr r3, [r3, #0]
|
|
8005d4e: 430a orrs r2, r1
|
|
8005d50: 609a str r2, [r3, #8]
|
|
|
|
/* set output data inversion mode */
|
|
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
|
8005d52: 687b ldr r3, [r7, #4]
|
|
8005d54: 681b ldr r3, [r3, #0]
|
|
8005d56: 689b ldr r3, [r3, #8]
|
|
8005d58: f023 0180 bic.w r1, r3, #128 ; 0x80
|
|
8005d5c: 687b ldr r3, [r7, #4]
|
|
8005d5e: 699a ldr r2, [r3, #24]
|
|
8005d60: 687b ldr r3, [r7, #4]
|
|
8005d62: 681b ldr r3, [r3, #0]
|
|
8005d64: 430a orrs r2, r1
|
|
8005d66: 609a str r2, [r3, #8]
|
|
/* makes sure the input data format (bytes, halfwords or words stream)
|
|
* is properly specified by user */
|
|
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_READY;
|
|
8005d68: 687b ldr r3, [r7, #4]
|
|
8005d6a: 2201 movs r2, #1
|
|
8005d6c: 775a strb r2, [r3, #29]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8005d6e: 2300 movs r3, #0
|
|
}
|
|
8005d70: 4618 mov r0, r3
|
|
8005d72: 3708 adds r7, #8
|
|
8005d74: 46bd mov sp, r7
|
|
8005d76: bd80 pop {r7, pc}
|
|
8005d78: 04c11db7 .word 0x04c11db7
|
|
|
|
08005d7c <HAL_CRCEx_Polynomial_Set>:
|
|
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
|
|
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
|
{
|
|
8005d7c: b480 push {r7}
|
|
8005d7e: b087 sub sp, #28
|
|
8005d80: af00 add r7, sp, #0
|
|
8005d82: 60f8 str r0, [r7, #12]
|
|
8005d84: 60b9 str r1, [r7, #8]
|
|
8005d86: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8005d88: 2300 movs r3, #0
|
|
8005d8a: 75fb strb r3, [r7, #23]
|
|
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
|
8005d8c: 231f movs r3, #31
|
|
8005d8e: 613b str r3, [r7, #16]
|
|
* definition. HAL_ERROR is reported if Pol degree is
|
|
* larger than that indicated by PolyLength.
|
|
* Look for MSB position: msb will contain the degree of
|
|
* the second to the largest polynomial member. E.g., for
|
|
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
|
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
|
8005d90: bf00 nop
|
|
8005d92: 693b ldr r3, [r7, #16]
|
|
8005d94: 1e5a subs r2, r3, #1
|
|
8005d96: 613a str r2, [r7, #16]
|
|
8005d98: 2b00 cmp r3, #0
|
|
8005d9a: d009 beq.n 8005db0 <HAL_CRCEx_Polynomial_Set+0x34>
|
|
8005d9c: 693b ldr r3, [r7, #16]
|
|
8005d9e: f003 031f and.w r3, r3, #31
|
|
8005da2: 68ba ldr r2, [r7, #8]
|
|
8005da4: fa22 f303 lsr.w r3, r2, r3
|
|
8005da8: f003 0301 and.w r3, r3, #1
|
|
8005dac: 2b00 cmp r3, #0
|
|
8005dae: d0f0 beq.n 8005d92 <HAL_CRCEx_Polynomial_Set+0x16>
|
|
{
|
|
}
|
|
|
|
switch (PolyLength)
|
|
8005db0: 687b ldr r3, [r7, #4]
|
|
8005db2: 2b18 cmp r3, #24
|
|
8005db4: d846 bhi.n 8005e44 <HAL_CRCEx_Polynomial_Set+0xc8>
|
|
8005db6: a201 add r2, pc, #4 ; (adr r2, 8005dbc <HAL_CRCEx_Polynomial_Set+0x40>)
|
|
8005db8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005dbc: 08005e4b .word 0x08005e4b
|
|
8005dc0: 08005e45 .word 0x08005e45
|
|
8005dc4: 08005e45 .word 0x08005e45
|
|
8005dc8: 08005e45 .word 0x08005e45
|
|
8005dcc: 08005e45 .word 0x08005e45
|
|
8005dd0: 08005e45 .word 0x08005e45
|
|
8005dd4: 08005e45 .word 0x08005e45
|
|
8005dd8: 08005e45 .word 0x08005e45
|
|
8005ddc: 08005e39 .word 0x08005e39
|
|
8005de0: 08005e45 .word 0x08005e45
|
|
8005de4: 08005e45 .word 0x08005e45
|
|
8005de8: 08005e45 .word 0x08005e45
|
|
8005dec: 08005e45 .word 0x08005e45
|
|
8005df0: 08005e45 .word 0x08005e45
|
|
8005df4: 08005e45 .word 0x08005e45
|
|
8005df8: 08005e45 .word 0x08005e45
|
|
8005dfc: 08005e2d .word 0x08005e2d
|
|
8005e00: 08005e45 .word 0x08005e45
|
|
8005e04: 08005e45 .word 0x08005e45
|
|
8005e08: 08005e45 .word 0x08005e45
|
|
8005e0c: 08005e45 .word 0x08005e45
|
|
8005e10: 08005e45 .word 0x08005e45
|
|
8005e14: 08005e45 .word 0x08005e45
|
|
8005e18: 08005e45 .word 0x08005e45
|
|
8005e1c: 08005e21 .word 0x08005e21
|
|
{
|
|
case CRC_POLYLENGTH_7B:
|
|
if (msb >= HAL_CRC_LENGTH_7B)
|
|
8005e20: 693b ldr r3, [r7, #16]
|
|
8005e22: 2b06 cmp r3, #6
|
|
8005e24: d913 bls.n 8005e4e <HAL_CRCEx_Polynomial_Set+0xd2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8005e26: 2301 movs r3, #1
|
|
8005e28: 75fb strb r3, [r7, #23]
|
|
}
|
|
break;
|
|
8005e2a: e010 b.n 8005e4e <HAL_CRCEx_Polynomial_Set+0xd2>
|
|
case CRC_POLYLENGTH_8B:
|
|
if (msb >= HAL_CRC_LENGTH_8B)
|
|
8005e2c: 693b ldr r3, [r7, #16]
|
|
8005e2e: 2b07 cmp r3, #7
|
|
8005e30: d90f bls.n 8005e52 <HAL_CRCEx_Polynomial_Set+0xd6>
|
|
{
|
|
status = HAL_ERROR;
|
|
8005e32: 2301 movs r3, #1
|
|
8005e34: 75fb strb r3, [r7, #23]
|
|
}
|
|
break;
|
|
8005e36: e00c b.n 8005e52 <HAL_CRCEx_Polynomial_Set+0xd6>
|
|
case CRC_POLYLENGTH_16B:
|
|
if (msb >= HAL_CRC_LENGTH_16B)
|
|
8005e38: 693b ldr r3, [r7, #16]
|
|
8005e3a: 2b0f cmp r3, #15
|
|
8005e3c: d90b bls.n 8005e56 <HAL_CRCEx_Polynomial_Set+0xda>
|
|
{
|
|
status = HAL_ERROR;
|
|
8005e3e: 2301 movs r3, #1
|
|
8005e40: 75fb strb r3, [r7, #23]
|
|
}
|
|
break;
|
|
8005e42: e008 b.n 8005e56 <HAL_CRCEx_Polynomial_Set+0xda>
|
|
|
|
case CRC_POLYLENGTH_32B:
|
|
/* no polynomial definition vs. polynomial length issue possible */
|
|
break;
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005e44: 2301 movs r3, #1
|
|
8005e46: 75fb strb r3, [r7, #23]
|
|
break;
|
|
8005e48: e006 b.n 8005e58 <HAL_CRCEx_Polynomial_Set+0xdc>
|
|
break;
|
|
8005e4a: bf00 nop
|
|
8005e4c: e004 b.n 8005e58 <HAL_CRCEx_Polynomial_Set+0xdc>
|
|
break;
|
|
8005e4e: bf00 nop
|
|
8005e50: e002 b.n 8005e58 <HAL_CRCEx_Polynomial_Set+0xdc>
|
|
break;
|
|
8005e52: bf00 nop
|
|
8005e54: e000 b.n 8005e58 <HAL_CRCEx_Polynomial_Set+0xdc>
|
|
break;
|
|
8005e56: bf00 nop
|
|
}
|
|
if (status == HAL_OK)
|
|
8005e58: 7dfb ldrb r3, [r7, #23]
|
|
8005e5a: 2b00 cmp r3, #0
|
|
8005e5c: d10d bne.n 8005e7a <HAL_CRCEx_Polynomial_Set+0xfe>
|
|
{
|
|
/* set generating polynomial */
|
|
WRITE_REG(hcrc->Instance->POL, Pol);
|
|
8005e5e: 68fb ldr r3, [r7, #12]
|
|
8005e60: 681b ldr r3, [r3, #0]
|
|
8005e62: 68ba ldr r2, [r7, #8]
|
|
8005e64: 615a str r2, [r3, #20]
|
|
|
|
/* set generating polynomial size */
|
|
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
|
8005e66: 68fb ldr r3, [r7, #12]
|
|
8005e68: 681b ldr r3, [r3, #0]
|
|
8005e6a: 689b ldr r3, [r3, #8]
|
|
8005e6c: f023 0118 bic.w r1, r3, #24
|
|
8005e70: 68fb ldr r3, [r7, #12]
|
|
8005e72: 681b ldr r3, [r3, #0]
|
|
8005e74: 687a ldr r2, [r7, #4]
|
|
8005e76: 430a orrs r2, r1
|
|
8005e78: 609a str r2, [r3, #8]
|
|
}
|
|
/* Return function status */
|
|
return status;
|
|
8005e7a: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8005e7c: 4618 mov r0, r3
|
|
8005e7e: 371c adds r7, #28
|
|
8005e80: 46bd mov sp, r7
|
|
8005e82: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005e86: 4770 bx lr
|
|
|
|
08005e88 <HAL_DAC_Init>:
|
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DAC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
|
|
{
|
|
8005e88: b580 push {r7, lr}
|
|
8005e8a: b082 sub sp, #8
|
|
8005e8c: af00 add r7, sp, #0
|
|
8005e8e: 6078 str r0, [r7, #4]
|
|
/* Check DAC handle */
|
|
if(hdac == NULL)
|
|
8005e90: 687b ldr r3, [r7, #4]
|
|
8005e92: 2b00 cmp r3, #0
|
|
8005e94: d101 bne.n 8005e9a <HAL_DAC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005e96: 2301 movs r3, #1
|
|
8005e98: e014 b.n 8005ec4 <HAL_DAC_Init+0x3c>
|
|
}
|
|
/* Check the parameters */
|
|
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
|
|
|
|
if(hdac->State == HAL_DAC_STATE_RESET)
|
|
8005e9a: 687b ldr r3, [r7, #4]
|
|
8005e9c: 791b ldrb r3, [r3, #4]
|
|
8005e9e: b2db uxtb r3, r3
|
|
8005ea0: 2b00 cmp r3, #0
|
|
8005ea2: d105 bne.n 8005eb0 <HAL_DAC_Init+0x28>
|
|
{
|
|
hdac->MspInitCallback = HAL_DAC_MspInit;
|
|
}
|
|
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
/* Allocate lock resource and initialize it */
|
|
hdac->Lock = HAL_UNLOCKED;
|
|
8005ea4: 687b ldr r3, [r7, #4]
|
|
8005ea6: 2200 movs r2, #0
|
|
8005ea8: 715a strb r2, [r3, #5]
|
|
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
/* Init the low level hardware */
|
|
hdac->MspInitCallback(hdac);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_DAC_MspInit(hdac);
|
|
8005eaa: 6878 ldr r0, [r7, #4]
|
|
8005eac: f7fe fbc6 bl 800463c <HAL_DAC_MspInit>
|
|
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Initialize the DAC state*/
|
|
hdac->State = HAL_DAC_STATE_BUSY;
|
|
8005eb0: 687b ldr r3, [r7, #4]
|
|
8005eb2: 2202 movs r2, #2
|
|
8005eb4: 711a strb r2, [r3, #4]
|
|
|
|
/* Set DAC error code to none */
|
|
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
|
|
8005eb6: 687b ldr r3, [r7, #4]
|
|
8005eb8: 2200 movs r2, #0
|
|
8005eba: 611a str r2, [r3, #16]
|
|
|
|
/* Initialize the DAC state*/
|
|
hdac->State = HAL_DAC_STATE_READY;
|
|
8005ebc: 687b ldr r3, [r7, #4]
|
|
8005ebe: 2201 movs r2, #1
|
|
8005ec0: 711a strb r2, [r3, #4]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8005ec2: 2300 movs r3, #0
|
|
}
|
|
8005ec4: 4618 mov r0, r3
|
|
8005ec6: 3708 adds r7, #8
|
|
8005ec8: 46bd mov sp, r7
|
|
8005eca: bd80 pop {r7, pc}
|
|
|
|
08005ecc <HAL_DAC_IRQHandler>:
|
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DAC.
|
|
* @retval None
|
|
*/
|
|
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
|
|
{
|
|
8005ecc: b580 push {r7, lr}
|
|
8005ece: b082 sub sp, #8
|
|
8005ed0: af00 add r7, sp, #0
|
|
8005ed2: 6078 str r0, [r7, #4]
|
|
/* Check underrun channel 1 flag */
|
|
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
|
|
8005ed4: 687b ldr r3, [r7, #4]
|
|
8005ed6: 681b ldr r3, [r3, #0]
|
|
8005ed8: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8005eda: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
|
8005ede: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
8005ee2: d118 bne.n 8005f16 <HAL_DAC_IRQHandler+0x4a>
|
|
{
|
|
/* Change DAC state to error state */
|
|
hdac->State = HAL_DAC_STATE_ERROR;
|
|
8005ee4: 687b ldr r3, [r7, #4]
|
|
8005ee6: 2204 movs r2, #4
|
|
8005ee8: 711a strb r2, [r3, #4]
|
|
|
|
/* Set DAC error code to channel1 DMA underrun error */
|
|
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
|
|
8005eea: 687b ldr r3, [r7, #4]
|
|
8005eec: 691b ldr r3, [r3, #16]
|
|
8005eee: f043 0201 orr.w r2, r3, #1
|
|
8005ef2: 687b ldr r3, [r7, #4]
|
|
8005ef4: 611a str r2, [r3, #16]
|
|
|
|
/* Clear the underrun flag */
|
|
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
|
|
8005ef6: 687b ldr r3, [r7, #4]
|
|
8005ef8: 681b ldr r3, [r3, #0]
|
|
8005efa: f44f 5200 mov.w r2, #8192 ; 0x2000
|
|
8005efe: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Disable the selected DAC channel1 DMA request */
|
|
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
|
|
8005f00: 687b ldr r3, [r7, #4]
|
|
8005f02: 681b ldr r3, [r3, #0]
|
|
8005f04: 681a ldr r2, [r3, #0]
|
|
8005f06: 687b ldr r3, [r7, #4]
|
|
8005f08: 681b ldr r3, [r3, #0]
|
|
8005f0a: f422 5280 bic.w r2, r2, #4096 ; 0x1000
|
|
8005f0e: 601a str r2, [r3, #0]
|
|
|
|
/* Error callback */
|
|
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
hdac->DMAUnderrunCallbackCh1(hdac);
|
|
#else
|
|
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
|
|
8005f10: 6878 ldr r0, [r7, #4]
|
|
8005f12: f000 f825 bl 8005f60 <HAL_DAC_DMAUnderrunCallbackCh1>
|
|
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
}
|
|
/* Check underrun channel 2 flag */
|
|
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
|
|
8005f16: 687b ldr r3, [r7, #4]
|
|
8005f18: 681b ldr r3, [r3, #0]
|
|
8005f1a: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8005f1c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
8005f20: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
8005f24: d118 bne.n 8005f58 <HAL_DAC_IRQHandler+0x8c>
|
|
{
|
|
/* Change DAC state to error state */
|
|
hdac->State = HAL_DAC_STATE_ERROR;
|
|
8005f26: 687b ldr r3, [r7, #4]
|
|
8005f28: 2204 movs r2, #4
|
|
8005f2a: 711a strb r2, [r3, #4]
|
|
|
|
/* Set DAC error code to channel2 DMA underrun error */
|
|
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
|
|
8005f2c: 687b ldr r3, [r7, #4]
|
|
8005f2e: 691b ldr r3, [r3, #16]
|
|
8005f30: f043 0202 orr.w r2, r3, #2
|
|
8005f34: 687b ldr r3, [r7, #4]
|
|
8005f36: 611a str r2, [r3, #16]
|
|
|
|
/* Clear the underrun flag */
|
|
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
|
|
8005f38: 687b ldr r3, [r7, #4]
|
|
8005f3a: 681b ldr r3, [r3, #0]
|
|
8005f3c: f04f 5200 mov.w r2, #536870912 ; 0x20000000
|
|
8005f40: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Disable the selected DAC channel1 DMA request */
|
|
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
|
|
8005f42: 687b ldr r3, [r7, #4]
|
|
8005f44: 681b ldr r3, [r3, #0]
|
|
8005f46: 681a ldr r2, [r3, #0]
|
|
8005f48: 687b ldr r3, [r7, #4]
|
|
8005f4a: 681b ldr r3, [r3, #0]
|
|
8005f4c: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
|
|
8005f50: 601a str r2, [r3, #0]
|
|
|
|
/* Error callback */
|
|
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
|
hdac->DMAUnderrunCallbackCh2(hdac);
|
|
#else
|
|
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
|
|
8005f52: 6878 ldr r0, [r7, #4]
|
|
8005f54: f000 f85b bl 800600e <HAL_DACEx_DMAUnderrunCallbackCh2>
|
|
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8005f58: bf00 nop
|
|
8005f5a: 3708 adds r7, #8
|
|
8005f5c: 46bd mov sp, r7
|
|
8005f5e: bd80 pop {r7, pc}
|
|
|
|
08005f60 <HAL_DAC_DMAUnderrunCallbackCh1>:
|
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DAC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
|
|
{
|
|
8005f60: b480 push {r7}
|
|
8005f62: b083 sub sp, #12
|
|
8005f64: af00 add r7, sp, #0
|
|
8005f66: 6078 str r0, [r7, #4]
|
|
UNUSED(hdac);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
|
|
*/
|
|
}
|
|
8005f68: bf00 nop
|
|
8005f6a: 370c adds r7, #12
|
|
8005f6c: 46bd mov sp, r7
|
|
8005f6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005f72: 4770 bx lr
|
|
|
|
08005f74 <HAL_DAC_ConfigChannel>:
|
|
* @arg DAC_CHANNEL_1: DAC Channel1 selected
|
|
* @arg DAC_CHANNEL_2: DAC Channel2 selected
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
|
|
{
|
|
8005f74: b480 push {r7}
|
|
8005f76: b087 sub sp, #28
|
|
8005f78: af00 add r7, sp, #0
|
|
8005f7a: 60f8 str r0, [r7, #12]
|
|
8005f7c: 60b9 str r1, [r7, #8]
|
|
8005f7e: 607a str r2, [r7, #4]
|
|
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
|
8005f80: 2300 movs r3, #0
|
|
8005f82: 617b str r3, [r7, #20]
|
|
8005f84: 2300 movs r3, #0
|
|
8005f86: 613b str r3, [r7, #16]
|
|
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
|
|
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
|
|
assert_param(IS_DAC_CHANNEL(Channel));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdac);
|
|
8005f88: 68fb ldr r3, [r7, #12]
|
|
8005f8a: 795b ldrb r3, [r3, #5]
|
|
8005f8c: 2b01 cmp r3, #1
|
|
8005f8e: d101 bne.n 8005f94 <HAL_DAC_ConfigChannel+0x20>
|
|
8005f90: 2302 movs r3, #2
|
|
8005f92: e036 b.n 8006002 <HAL_DAC_ConfigChannel+0x8e>
|
|
8005f94: 68fb ldr r3, [r7, #12]
|
|
8005f96: 2201 movs r2, #1
|
|
8005f98: 715a strb r2, [r3, #5]
|
|
|
|
/* Change DAC state */
|
|
hdac->State = HAL_DAC_STATE_BUSY;
|
|
8005f9a: 68fb ldr r3, [r7, #12]
|
|
8005f9c: 2202 movs r2, #2
|
|
8005f9e: 711a strb r2, [r3, #4]
|
|
|
|
/* Get the DAC CR value */
|
|
tmpreg1 = hdac->Instance->CR;
|
|
8005fa0: 68fb ldr r3, [r7, #12]
|
|
8005fa2: 681b ldr r3, [r3, #0]
|
|
8005fa4: 681b ldr r3, [r3, #0]
|
|
8005fa6: 617b str r3, [r7, #20]
|
|
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
|
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
|
|
8005fa8: f640 72fe movw r2, #4094 ; 0xffe
|
|
8005fac: 687b ldr r3, [r7, #4]
|
|
8005fae: fa02 f303 lsl.w r3, r2, r3
|
|
8005fb2: 43db mvns r3, r3
|
|
8005fb4: 697a ldr r2, [r7, #20]
|
|
8005fb6: 4013 ands r3, r2
|
|
8005fb8: 617b str r3, [r7, #20]
|
|
/* Configure for the selected DAC channel: buffer output, trigger */
|
|
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
|
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
|
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
|
|
8005fba: 68bb ldr r3, [r7, #8]
|
|
8005fbc: 681a ldr r2, [r3, #0]
|
|
8005fbe: 68bb ldr r3, [r7, #8]
|
|
8005fc0: 685b ldr r3, [r3, #4]
|
|
8005fc2: 4313 orrs r3, r2
|
|
8005fc4: 613b str r3, [r7, #16]
|
|
/* Calculate CR register value depending on DAC_Channel */
|
|
tmpreg1 |= tmpreg2 << Channel;
|
|
8005fc6: 693a ldr r2, [r7, #16]
|
|
8005fc8: 687b ldr r3, [r7, #4]
|
|
8005fca: fa02 f303 lsl.w r3, r2, r3
|
|
8005fce: 697a ldr r2, [r7, #20]
|
|
8005fd0: 4313 orrs r3, r2
|
|
8005fd2: 617b str r3, [r7, #20]
|
|
/* Write to DAC CR */
|
|
hdac->Instance->CR = tmpreg1;
|
|
8005fd4: 68fb ldr r3, [r7, #12]
|
|
8005fd6: 681b ldr r3, [r3, #0]
|
|
8005fd8: 697a ldr r2, [r7, #20]
|
|
8005fda: 601a str r2, [r3, #0]
|
|
/* Disable wave generation */
|
|
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
|
|
8005fdc: 68fb ldr r3, [r7, #12]
|
|
8005fde: 681b ldr r3, [r3, #0]
|
|
8005fe0: 6819 ldr r1, [r3, #0]
|
|
8005fe2: 22c0 movs r2, #192 ; 0xc0
|
|
8005fe4: 687b ldr r3, [r7, #4]
|
|
8005fe6: fa02 f303 lsl.w r3, r2, r3
|
|
8005fea: 43da mvns r2, r3
|
|
8005fec: 68fb ldr r3, [r7, #12]
|
|
8005fee: 681b ldr r3, [r3, #0]
|
|
8005ff0: 400a ands r2, r1
|
|
8005ff2: 601a str r2, [r3, #0]
|
|
|
|
/* Change DAC state */
|
|
hdac->State = HAL_DAC_STATE_READY;
|
|
8005ff4: 68fb ldr r3, [r7, #12]
|
|
8005ff6: 2201 movs r2, #1
|
|
8005ff8: 711a strb r2, [r3, #4]
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdac);
|
|
8005ffa: 68fb ldr r3, [r7, #12]
|
|
8005ffc: 2200 movs r2, #0
|
|
8005ffe: 715a strb r2, [r3, #5]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006000: 2300 movs r3, #0
|
|
}
|
|
8006002: 4618 mov r0, r3
|
|
8006004: 371c adds r7, #28
|
|
8006006: 46bd mov sp, r7
|
|
8006008: f85d 7b04 ldr.w r7, [sp], #4
|
|
800600c: 4770 bx lr
|
|
|
|
0800600e <HAL_DACEx_DMAUnderrunCallbackCh2>:
|
|
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DAC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
|
|
{
|
|
800600e: b480 push {r7}
|
|
8006010: b083 sub sp, #12
|
|
8006012: af00 add r7, sp, #0
|
|
8006014: 6078 str r0, [r7, #4]
|
|
UNUSED(hdac);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
|
|
*/
|
|
}
|
|
8006016: bf00 nop
|
|
8006018: 370c adds r7, #12
|
|
800601a: 46bd mov sp, r7
|
|
800601c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006020: 4770 bx lr
|
|
...
|
|
|
|
08006024 <HAL_DMA_Init>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006024: b580 push {r7, lr}
|
|
8006026: b086 sub sp, #24
|
|
8006028: af00 add r7, sp, #0
|
|
800602a: 6078 str r0, [r7, #4]
|
|
uint32_t tmp = 0U;
|
|
800602c: 2300 movs r3, #0
|
|
800602e: 617b str r3, [r7, #20]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8006030: f7ff f956 bl 80052e0 <HAL_GetTick>
|
|
8006034: 6138 str r0, [r7, #16]
|
|
DMA_Base_Registers *regs;
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma == NULL)
|
|
8006036: 687b ldr r3, [r7, #4]
|
|
8006038: 2b00 cmp r3, #0
|
|
800603a: d101 bne.n 8006040 <HAL_DMA_Init+0x1c>
|
|
{
|
|
return HAL_ERROR;
|
|
800603c: 2301 movs r3, #1
|
|
800603e: e099 b.n 8006174 <HAL_DMA_Init+0x150>
|
|
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
|
|
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
|
|
}
|
|
|
|
/* Allocate lock resource */
|
|
__HAL_UNLOCK(hdma);
|
|
8006040: 687b ldr r3, [r7, #4]
|
|
8006042: 2200 movs r2, #0
|
|
8006044: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
|
|
/* Change DMA peripheral state */
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8006048: 687b ldr r3, [r7, #4]
|
|
800604a: 2202 movs r2, #2
|
|
800604c: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8006050: 687b ldr r3, [r7, #4]
|
|
8006052: 681b ldr r3, [r3, #0]
|
|
8006054: 681a ldr r2, [r3, #0]
|
|
8006056: 687b ldr r3, [r7, #4]
|
|
8006058: 681b ldr r3, [r3, #0]
|
|
800605a: f022 0201 bic.w r2, r2, #1
|
|
800605e: 601a str r2, [r3, #0]
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8006060: e00f b.n 8006082 <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
8006062: f7ff f93d bl 80052e0 <HAL_GetTick>
|
|
8006066: 4602 mov r2, r0
|
|
8006068: 693b ldr r3, [r7, #16]
|
|
800606a: 1ad3 subs r3, r2, r3
|
|
800606c: 2b05 cmp r3, #5
|
|
800606e: d908 bls.n 8006082 <HAL_DMA_Init+0x5e>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
8006070: 687b ldr r3, [r7, #4]
|
|
8006072: 2220 movs r2, #32
|
|
8006074: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
8006076: 687b ldr r3, [r7, #4]
|
|
8006078: 2203 movs r2, #3
|
|
800607a: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
|
|
return HAL_TIMEOUT;
|
|
800607e: 2303 movs r3, #3
|
|
8006080: e078 b.n 8006174 <HAL_DMA_Init+0x150>
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
8006082: 687b ldr r3, [r7, #4]
|
|
8006084: 681b ldr r3, [r3, #0]
|
|
8006086: 681b ldr r3, [r3, #0]
|
|
8006088: f003 0301 and.w r3, r3, #1
|
|
800608c: 2b00 cmp r3, #0
|
|
800608e: d1e8 bne.n 8006062 <HAL_DMA_Init+0x3e>
|
|
}
|
|
}
|
|
|
|
/* Get the CR register value */
|
|
tmp = hdma->Instance->CR;
|
|
8006090: 687b ldr r3, [r7, #4]
|
|
8006092: 681b ldr r3, [r3, #0]
|
|
8006094: 681b ldr r3, [r3, #0]
|
|
8006096: 617b str r3, [r7, #20]
|
|
|
|
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
|
|
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
|
|
8006098: 697a ldr r2, [r7, #20]
|
|
800609a: 4b38 ldr r3, [pc, #224] ; (800617c <HAL_DMA_Init+0x158>)
|
|
800609c: 4013 ands r3, r2
|
|
800609e: 617b str r3, [r7, #20]
|
|
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
|
|
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
|
|
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
|
|
|
|
/* Prepare the DMA Stream configuration */
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
80060a0: 687b ldr r3, [r7, #4]
|
|
80060a2: 685a ldr r2, [r3, #4]
|
|
80060a4: 687b ldr r3, [r7, #4]
|
|
80060a6: 689b ldr r3, [r3, #8]
|
|
80060a8: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80060aa: 687b ldr r3, [r7, #4]
|
|
80060ac: 68db ldr r3, [r3, #12]
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
80060ae: 431a orrs r2, r3
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80060b0: 687b ldr r3, [r7, #4]
|
|
80060b2: 691b ldr r3, [r3, #16]
|
|
80060b4: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
80060b6: 687b ldr r3, [r7, #4]
|
|
80060b8: 695b ldr r3, [r3, #20]
|
|
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
|
80060ba: 431a orrs r2, r3
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
80060bc: 687b ldr r3, [r7, #4]
|
|
80060be: 699b ldr r3, [r3, #24]
|
|
80060c0: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
80060c2: 687b ldr r3, [r7, #4]
|
|
80060c4: 69db ldr r3, [r3, #28]
|
|
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
|
80060c6: 431a orrs r2, r3
|
|
hdma->Init.Mode | hdma->Init.Priority;
|
|
80060c8: 687b ldr r3, [r7, #4]
|
|
80060ca: 6a1b ldr r3, [r3, #32]
|
|
80060cc: 4313 orrs r3, r2
|
|
tmp |= hdma->Init.Channel | hdma->Init.Direction |
|
|
80060ce: 697a ldr r2, [r7, #20]
|
|
80060d0: 4313 orrs r3, r2
|
|
80060d2: 617b str r3, [r7, #20]
|
|
|
|
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
80060d4: 687b ldr r3, [r7, #4]
|
|
80060d6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80060d8: 2b04 cmp r3, #4
|
|
80060da: d107 bne.n 80060ec <HAL_DMA_Init+0xc8>
|
|
{
|
|
/* Get memory burst and peripheral burst */
|
|
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
|
|
80060dc: 687b ldr r3, [r7, #4]
|
|
80060de: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
80060e0: 687b ldr r3, [r7, #4]
|
|
80060e2: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80060e4: 4313 orrs r3, r2
|
|
80060e6: 697a ldr r2, [r7, #20]
|
|
80060e8: 4313 orrs r3, r2
|
|
80060ea: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to DMA Stream CR register */
|
|
hdma->Instance->CR = tmp;
|
|
80060ec: 687b ldr r3, [r7, #4]
|
|
80060ee: 681b ldr r3, [r3, #0]
|
|
80060f0: 697a ldr r2, [r7, #20]
|
|
80060f2: 601a str r2, [r3, #0]
|
|
|
|
/* Get the FCR register value */
|
|
tmp = hdma->Instance->FCR;
|
|
80060f4: 687b ldr r3, [r7, #4]
|
|
80060f6: 681b ldr r3, [r3, #0]
|
|
80060f8: 695b ldr r3, [r3, #20]
|
|
80060fa: 617b str r3, [r7, #20]
|
|
|
|
/* Clear Direct mode and FIFO threshold bits */
|
|
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
|
|
80060fc: 697b ldr r3, [r7, #20]
|
|
80060fe: f023 0307 bic.w r3, r3, #7
|
|
8006102: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the DMA Stream FIFO configuration */
|
|
tmp |= hdma->Init.FIFOMode;
|
|
8006104: 687b ldr r3, [r7, #4]
|
|
8006106: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8006108: 697a ldr r2, [r7, #20]
|
|
800610a: 4313 orrs r3, r2
|
|
800610c: 617b str r3, [r7, #20]
|
|
|
|
/* The FIFO threshold is not used when the FIFO mode is disabled */
|
|
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
|
|
800610e: 687b ldr r3, [r7, #4]
|
|
8006110: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8006112: 2b04 cmp r3, #4
|
|
8006114: d117 bne.n 8006146 <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Get the FIFO threshold */
|
|
tmp |= hdma->Init.FIFOThreshold;
|
|
8006116: 687b ldr r3, [r7, #4]
|
|
8006118: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800611a: 697a ldr r2, [r7, #20]
|
|
800611c: 4313 orrs r3, r2
|
|
800611e: 617b str r3, [r7, #20]
|
|
|
|
/* Check compatibility between FIFO threshold level and size of the memory burst */
|
|
/* for INCR4, INCR8, INCR16 bursts */
|
|
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
|
|
8006120: 687b ldr r3, [r7, #4]
|
|
8006122: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006124: 2b00 cmp r3, #0
|
|
8006126: d00e beq.n 8006146 <HAL_DMA_Init+0x122>
|
|
{
|
|
if (DMA_CheckFifoParam(hdma) != HAL_OK)
|
|
8006128: 6878 ldr r0, [r7, #4]
|
|
800612a: f000 f8bd bl 80062a8 <DMA_CheckFifoParam>
|
|
800612e: 4603 mov r3, r0
|
|
8006130: 2b00 cmp r3, #0
|
|
8006132: d008 beq.n 8006146 <HAL_DMA_Init+0x122>
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
|
8006134: 687b ldr r3, [r7, #4]
|
|
8006136: 2240 movs r2, #64 ; 0x40
|
|
8006138: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800613a: 687b ldr r3, [r7, #4]
|
|
800613c: 2201 movs r2, #1
|
|
800613e: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
|
|
return HAL_ERROR;
|
|
8006142: 2301 movs r3, #1
|
|
8006144: e016 b.n 8006174 <HAL_DMA_Init+0x150>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Write to DMA Stream FCR */
|
|
hdma->Instance->FCR = tmp;
|
|
8006146: 687b ldr r3, [r7, #4]
|
|
8006148: 681b ldr r3, [r3, #0]
|
|
800614a: 697a ldr r2, [r7, #20]
|
|
800614c: 615a str r2, [r3, #20]
|
|
|
|
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
|
|
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
|
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
|
800614e: 6878 ldr r0, [r7, #4]
|
|
8006150: f000 f874 bl 800623c <DMA_CalcBaseAndBitshift>
|
|
8006154: 4603 mov r3, r0
|
|
8006156: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear all interrupt flags */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
8006158: 687b ldr r3, [r7, #4]
|
|
800615a: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
800615c: 223f movs r2, #63 ; 0x3f
|
|
800615e: 409a lsls r2, r3
|
|
8006160: 68fb ldr r3, [r7, #12]
|
|
8006162: 609a str r2, [r3, #8]
|
|
|
|
/* Initialize the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8006164: 687b ldr r3, [r7, #4]
|
|
8006166: 2200 movs r2, #0
|
|
8006168: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Initialize the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800616a: 687b ldr r3, [r7, #4]
|
|
800616c: 2201 movs r2, #1
|
|
800616e: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
|
|
return HAL_OK;
|
|
8006172: 2300 movs r3, #0
|
|
}
|
|
8006174: 4618 mov r0, r3
|
|
8006176: 3718 adds r7, #24
|
|
8006178: 46bd mov sp, r7
|
|
800617a: bd80 pop {r7, pc}
|
|
800617c: f010803f .word 0xf010803f
|
|
|
|
08006180 <HAL_DMA_DeInit>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8006180: b580 push {r7, lr}
|
|
8006182: b084 sub sp, #16
|
|
8006184: af00 add r7, sp, #0
|
|
8006186: 6078 str r0, [r7, #4]
|
|
DMA_Base_Registers *regs;
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma == NULL)
|
|
8006188: 687b ldr r3, [r7, #4]
|
|
800618a: 2b00 cmp r3, #0
|
|
800618c: d101 bne.n 8006192 <HAL_DMA_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800618e: 2301 movs r3, #1
|
|
8006190: e050 b.n 8006234 <HAL_DMA_DeInit+0xb4>
|
|
}
|
|
|
|
/* Check the DMA peripheral state */
|
|
if(hdma->State == HAL_DMA_STATE_BUSY)
|
|
8006192: 687b ldr r3, [r7, #4]
|
|
8006194: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
|
|
8006198: b2db uxtb r3, r3
|
|
800619a: 2b02 cmp r3, #2
|
|
800619c: d101 bne.n 80061a2 <HAL_DMA_DeInit+0x22>
|
|
{
|
|
/* Return error status */
|
|
return HAL_BUSY;
|
|
800619e: 2302 movs r3, #2
|
|
80061a0: e048 b.n 8006234 <HAL_DMA_DeInit+0xb4>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
|
|
|
|
/* Disable the selected DMA Streamx */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80061a2: 687b ldr r3, [r7, #4]
|
|
80061a4: 681b ldr r3, [r3, #0]
|
|
80061a6: 681a ldr r2, [r3, #0]
|
|
80061a8: 687b ldr r3, [r7, #4]
|
|
80061aa: 681b ldr r3, [r3, #0]
|
|
80061ac: f022 0201 bic.w r2, r2, #1
|
|
80061b0: 601a str r2, [r3, #0]
|
|
|
|
/* Reset DMA Streamx control register */
|
|
hdma->Instance->CR = 0U;
|
|
80061b2: 687b ldr r3, [r7, #4]
|
|
80061b4: 681b ldr r3, [r3, #0]
|
|
80061b6: 2200 movs r2, #0
|
|
80061b8: 601a str r2, [r3, #0]
|
|
|
|
/* Reset DMA Streamx number of data to transfer register */
|
|
hdma->Instance->NDTR = 0U;
|
|
80061ba: 687b ldr r3, [r7, #4]
|
|
80061bc: 681b ldr r3, [r3, #0]
|
|
80061be: 2200 movs r2, #0
|
|
80061c0: 605a str r2, [r3, #4]
|
|
|
|
/* Reset DMA Streamx peripheral address register */
|
|
hdma->Instance->PAR = 0U;
|
|
80061c2: 687b ldr r3, [r7, #4]
|
|
80061c4: 681b ldr r3, [r3, #0]
|
|
80061c6: 2200 movs r2, #0
|
|
80061c8: 609a str r2, [r3, #8]
|
|
|
|
/* Reset DMA Streamx memory 0 address register */
|
|
hdma->Instance->M0AR = 0U;
|
|
80061ca: 687b ldr r3, [r7, #4]
|
|
80061cc: 681b ldr r3, [r3, #0]
|
|
80061ce: 2200 movs r2, #0
|
|
80061d0: 60da str r2, [r3, #12]
|
|
|
|
/* Reset DMA Streamx memory 1 address register */
|
|
hdma->Instance->M1AR = 0U;
|
|
80061d2: 687b ldr r3, [r7, #4]
|
|
80061d4: 681b ldr r3, [r3, #0]
|
|
80061d6: 2200 movs r2, #0
|
|
80061d8: 611a str r2, [r3, #16]
|
|
|
|
/* Reset DMA Streamx FIFO control register */
|
|
hdma->Instance->FCR = (uint32_t)0x00000021U;
|
|
80061da: 687b ldr r3, [r7, #4]
|
|
80061dc: 681b ldr r3, [r3, #0]
|
|
80061de: 2221 movs r2, #33 ; 0x21
|
|
80061e0: 615a str r2, [r3, #20]
|
|
|
|
/* Get DMA steam Base Address */
|
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
|
80061e2: 6878 ldr r0, [r7, #4]
|
|
80061e4: f000 f82a bl 800623c <DMA_CalcBaseAndBitshift>
|
|
80061e8: 4603 mov r3, r0
|
|
80061ea: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
80061ec: 687b ldr r3, [r7, #4]
|
|
80061ee: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
80061f0: 223f movs r2, #63 ; 0x3f
|
|
80061f2: 409a lsls r2, r3
|
|
80061f4: 68fb ldr r3, [r7, #12]
|
|
80061f6: 609a str r2, [r3, #8]
|
|
|
|
/* Clean all callbacks */
|
|
hdma->XferCpltCallback = NULL;
|
|
80061f8: 687b ldr r3, [r7, #4]
|
|
80061fa: 2200 movs r2, #0
|
|
80061fc: 63da str r2, [r3, #60] ; 0x3c
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
80061fe: 687b ldr r3, [r7, #4]
|
|
8006200: 2200 movs r2, #0
|
|
8006202: 641a str r2, [r3, #64] ; 0x40
|
|
hdma->XferM1CpltCallback = NULL;
|
|
8006204: 687b ldr r3, [r7, #4]
|
|
8006206: 2200 movs r2, #0
|
|
8006208: 645a str r2, [r3, #68] ; 0x44
|
|
hdma->XferM1HalfCpltCallback = NULL;
|
|
800620a: 687b ldr r3, [r7, #4]
|
|
800620c: 2200 movs r2, #0
|
|
800620e: 649a str r2, [r3, #72] ; 0x48
|
|
hdma->XferErrorCallback = NULL;
|
|
8006210: 687b ldr r3, [r7, #4]
|
|
8006212: 2200 movs r2, #0
|
|
8006214: 64da str r2, [r3, #76] ; 0x4c
|
|
hdma->XferAbortCallback = NULL;
|
|
8006216: 687b ldr r3, [r7, #4]
|
|
8006218: 2200 movs r2, #0
|
|
800621a: 651a str r2, [r3, #80] ; 0x50
|
|
|
|
/* Reset the error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
800621c: 687b ldr r3, [r7, #4]
|
|
800621e: 2200 movs r2, #0
|
|
8006220: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Reset the DMA state */
|
|
hdma->State = HAL_DMA_STATE_RESET;
|
|
8006222: 687b ldr r3, [r7, #4]
|
|
8006224: 2200 movs r2, #0
|
|
8006226: f883 2035 strb.w r2, [r3, #53] ; 0x35
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
800622a: 687b ldr r3, [r7, #4]
|
|
800622c: 2200 movs r2, #0
|
|
800622e: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
|
|
return HAL_OK;
|
|
8006232: 2300 movs r3, #0
|
|
}
|
|
8006234: 4618 mov r0, r3
|
|
8006236: 3710 adds r7, #16
|
|
8006238: 46bd mov sp, r7
|
|
800623a: bd80 pop {r7, pc}
|
|
|
|
0800623c <DMA_CalcBaseAndBitshift>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval Stream base address
|
|
*/
|
|
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800623c: b480 push {r7}
|
|
800623e: b085 sub sp, #20
|
|
8006240: af00 add r7, sp, #0
|
|
8006242: 6078 str r0, [r7, #4]
|
|
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
|
|
8006244: 687b ldr r3, [r7, #4]
|
|
8006246: 681b ldr r3, [r3, #0]
|
|
8006248: b2db uxtb r3, r3
|
|
800624a: 3b10 subs r3, #16
|
|
800624c: 4a13 ldr r2, [pc, #76] ; (800629c <DMA_CalcBaseAndBitshift+0x60>)
|
|
800624e: fba2 2303 umull r2, r3, r2, r3
|
|
8006252: 091b lsrs r3, r3, #4
|
|
8006254: 60fb str r3, [r7, #12]
|
|
|
|
/* lookup table for necessary bitshift of flags within status registers */
|
|
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
|
|
hdma->StreamIndex = flagBitshiftOffset[stream_number];
|
|
8006256: 4a12 ldr r2, [pc, #72] ; (80062a0 <DMA_CalcBaseAndBitshift+0x64>)
|
|
8006258: 68fb ldr r3, [r7, #12]
|
|
800625a: 4413 add r3, r2
|
|
800625c: 781b ldrb r3, [r3, #0]
|
|
800625e: 461a mov r2, r3
|
|
8006260: 687b ldr r3, [r7, #4]
|
|
8006262: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
if (stream_number > 3U)
|
|
8006264: 68fb ldr r3, [r7, #12]
|
|
8006266: 2b03 cmp r3, #3
|
|
8006268: d908 bls.n 800627c <DMA_CalcBaseAndBitshift+0x40>
|
|
{
|
|
/* return pointer to HISR and HIFCR */
|
|
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
|
|
800626a: 687b ldr r3, [r7, #4]
|
|
800626c: 681b ldr r3, [r3, #0]
|
|
800626e: 461a mov r2, r3
|
|
8006270: 4b0c ldr r3, [pc, #48] ; (80062a4 <DMA_CalcBaseAndBitshift+0x68>)
|
|
8006272: 4013 ands r3, r2
|
|
8006274: 1d1a adds r2, r3, #4
|
|
8006276: 687b ldr r3, [r7, #4]
|
|
8006278: 659a str r2, [r3, #88] ; 0x58
|
|
800627a: e006 b.n 800628a <DMA_CalcBaseAndBitshift+0x4e>
|
|
}
|
|
else
|
|
{
|
|
/* return pointer to LISR and LIFCR */
|
|
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
|
|
800627c: 687b ldr r3, [r7, #4]
|
|
800627e: 681b ldr r3, [r3, #0]
|
|
8006280: 461a mov r2, r3
|
|
8006282: 4b08 ldr r3, [pc, #32] ; (80062a4 <DMA_CalcBaseAndBitshift+0x68>)
|
|
8006284: 4013 ands r3, r2
|
|
8006286: 687a ldr r2, [r7, #4]
|
|
8006288: 6593 str r3, [r2, #88] ; 0x58
|
|
}
|
|
|
|
return hdma->StreamBaseAddress;
|
|
800628a: 687b ldr r3, [r7, #4]
|
|
800628c: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
}
|
|
800628e: 4618 mov r0, r3
|
|
8006290: 3714 adds r7, #20
|
|
8006292: 46bd mov sp, r7
|
|
8006294: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006298: 4770 bx lr
|
|
800629a: bf00 nop
|
|
800629c: aaaaaaab .word 0xaaaaaaab
|
|
80062a0: 08022d40 .word 0x08022d40
|
|
80062a4: fffffc00 .word 0xfffffc00
|
|
|
|
080062a8 <DMA_CheckFifoParam>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80062a8: b480 push {r7}
|
|
80062aa: b085 sub sp, #20
|
|
80062ac: af00 add r7, sp, #0
|
|
80062ae: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80062b0: 2300 movs r3, #0
|
|
80062b2: 73fb strb r3, [r7, #15]
|
|
uint32_t tmp = hdma->Init.FIFOThreshold;
|
|
80062b4: 687b ldr r3, [r7, #4]
|
|
80062b6: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80062b8: 60bb str r3, [r7, #8]
|
|
|
|
/* Memory Data size equal to Byte */
|
|
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
|
|
80062ba: 687b ldr r3, [r7, #4]
|
|
80062bc: 699b ldr r3, [r3, #24]
|
|
80062be: 2b00 cmp r3, #0
|
|
80062c0: d11f bne.n 8006302 <DMA_CheckFifoParam+0x5a>
|
|
{
|
|
switch (tmp)
|
|
80062c2: 68bb ldr r3, [r7, #8]
|
|
80062c4: 2b03 cmp r3, #3
|
|
80062c6: d855 bhi.n 8006374 <DMA_CheckFifoParam+0xcc>
|
|
80062c8: a201 add r2, pc, #4 ; (adr r2, 80062d0 <DMA_CheckFifoParam+0x28>)
|
|
80062ca: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80062ce: bf00 nop
|
|
80062d0: 080062e1 .word 0x080062e1
|
|
80062d4: 080062f3 .word 0x080062f3
|
|
80062d8: 080062e1 .word 0x080062e1
|
|
80062dc: 08006375 .word 0x08006375
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
80062e0: 687b ldr r3, [r7, #4]
|
|
80062e2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80062e4: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
80062e8: 2b00 cmp r3, #0
|
|
80062ea: d045 beq.n 8006378 <DMA_CheckFifoParam+0xd0>
|
|
{
|
|
status = HAL_ERROR;
|
|
80062ec: 2301 movs r3, #1
|
|
80062ee: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
80062f0: e042 b.n 8006378 <DMA_CheckFifoParam+0xd0>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
80062f2: 687b ldr r3, [r7, #4]
|
|
80062f4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80062f6: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
|
|
80062fa: d13f bne.n 800637c <DMA_CheckFifoParam+0xd4>
|
|
{
|
|
status = HAL_ERROR;
|
|
80062fc: 2301 movs r3, #1
|
|
80062fe: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8006300: e03c b.n 800637c <DMA_CheckFifoParam+0xd4>
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Memory Data size equal to Half-Word */
|
|
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
8006302: 687b ldr r3, [r7, #4]
|
|
8006304: 699b ldr r3, [r3, #24]
|
|
8006306: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
800630a: d121 bne.n 8006350 <DMA_CheckFifoParam+0xa8>
|
|
{
|
|
switch (tmp)
|
|
800630c: 68bb ldr r3, [r7, #8]
|
|
800630e: 2b03 cmp r3, #3
|
|
8006310: d836 bhi.n 8006380 <DMA_CheckFifoParam+0xd8>
|
|
8006312: a201 add r2, pc, #4 ; (adr r2, 8006318 <DMA_CheckFifoParam+0x70>)
|
|
8006314: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8006318: 08006329 .word 0x08006329
|
|
800631c: 0800632f .word 0x0800632f
|
|
8006320: 08006329 .word 0x08006329
|
|
8006324: 08006341 .word 0x08006341
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
status = HAL_ERROR;
|
|
8006328: 2301 movs r3, #1
|
|
800632a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800632c: e02f b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
800632e: 687b ldr r3, [r7, #4]
|
|
8006330: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006332: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
8006336: 2b00 cmp r3, #0
|
|
8006338: d024 beq.n 8006384 <DMA_CheckFifoParam+0xdc>
|
|
{
|
|
status = HAL_ERROR;
|
|
800633a: 2301 movs r3, #1
|
|
800633c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800633e: e021 b.n 8006384 <DMA_CheckFifoParam+0xdc>
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
8006340: 687b ldr r3, [r7, #4]
|
|
8006342: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006344: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
|
|
8006348: d11e bne.n 8006388 <DMA_CheckFifoParam+0xe0>
|
|
{
|
|
status = HAL_ERROR;
|
|
800634a: 2301 movs r3, #1
|
|
800634c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
800634e: e01b b.n 8006388 <DMA_CheckFifoParam+0xe0>
|
|
}
|
|
|
|
/* Memory Data size equal to Word */
|
|
else
|
|
{
|
|
switch (tmp)
|
|
8006350: 68bb ldr r3, [r7, #8]
|
|
8006352: 2b02 cmp r3, #2
|
|
8006354: d902 bls.n 800635c <DMA_CheckFifoParam+0xb4>
|
|
8006356: 2b03 cmp r3, #3
|
|
8006358: d003 beq.n 8006362 <DMA_CheckFifoParam+0xba>
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
800635a: e018 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
status = HAL_ERROR;
|
|
800635c: 2301 movs r3, #1
|
|
800635e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006360: e015 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
8006362: 687b ldr r3, [r7, #4]
|
|
8006364: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006366: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
800636a: 2b00 cmp r3, #0
|
|
800636c: d00e beq.n 800638c <DMA_CheckFifoParam+0xe4>
|
|
status = HAL_ERROR;
|
|
800636e: 2301 movs r3, #1
|
|
8006370: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8006372: e00b b.n 800638c <DMA_CheckFifoParam+0xe4>
|
|
break;
|
|
8006374: bf00 nop
|
|
8006376: e00a b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
8006378: bf00 nop
|
|
800637a: e008 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
800637c: bf00 nop
|
|
800637e: e006 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
8006380: bf00 nop
|
|
8006382: e004 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
8006384: bf00 nop
|
|
8006386: e002 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
8006388: bf00 nop
|
|
800638a: e000 b.n 800638e <DMA_CheckFifoParam+0xe6>
|
|
break;
|
|
800638c: bf00 nop
|
|
}
|
|
}
|
|
|
|
return status;
|
|
800638e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006390: 4618 mov r0, r3
|
|
8006392: 3714 adds r7, #20
|
|
8006394: 46bd mov sp, r7
|
|
8006396: f85d 7b04 ldr.w r7, [sp], #4
|
|
800639a: 4770 bx lr
|
|
|
|
0800639c <HAL_DMA2D_Init>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
800639c: b580 push {r7, lr}
|
|
800639e: b082 sub sp, #8
|
|
80063a0: af00 add r7, sp, #0
|
|
80063a2: 6078 str r0, [r7, #4]
|
|
/* Check the DMA2D peripheral state */
|
|
if(hdma2d == NULL)
|
|
80063a4: 687b ldr r3, [r7, #4]
|
|
80063a6: 2b00 cmp r3, #0
|
|
80063a8: d101 bne.n 80063ae <HAL_DMA2D_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80063aa: 2301 movs r3, #1
|
|
80063ac: e039 b.n 8006422 <HAL_DMA2D_Init+0x86>
|
|
|
|
/* Init the low level hardware */
|
|
hdma2d->MspInitCallback(hdma2d);
|
|
}
|
|
#else
|
|
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
|
|
80063ae: 687b ldr r3, [r7, #4]
|
|
80063b0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
|
|
80063b4: b2db uxtb r3, r3
|
|
80063b6: 2b00 cmp r3, #0
|
|
80063b8: d106 bne.n 80063c8 <HAL_DMA2D_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hdma2d->Lock = HAL_UNLOCKED;
|
|
80063ba: 687b ldr r3, [r7, #4]
|
|
80063bc: 2200 movs r2, #0
|
|
80063be: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
/* Init the low level hardware */
|
|
HAL_DMA2D_MspInit(hdma2d);
|
|
80063c2: 6878 ldr r0, [r7, #4]
|
|
80063c4: f7fe f982 bl 80046cc <HAL_DMA2D_MspInit>
|
|
}
|
|
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
80063c8: 687b ldr r3, [r7, #4]
|
|
80063ca: 2202 movs r2, #2
|
|
80063cc: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* DMA2D CR register configuration -------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
|
|
80063d0: 687b ldr r3, [r7, #4]
|
|
80063d2: 681b ldr r3, [r3, #0]
|
|
80063d4: 681b ldr r3, [r3, #0]
|
|
80063d6: f423 3140 bic.w r1, r3, #196608 ; 0x30000
|
|
80063da: 687b ldr r3, [r7, #4]
|
|
80063dc: 685a ldr r2, [r3, #4]
|
|
80063de: 687b ldr r3, [r7, #4]
|
|
80063e0: 681b ldr r3, [r3, #0]
|
|
80063e2: 430a orrs r2, r1
|
|
80063e4: 601a str r2, [r3, #0]
|
|
|
|
/* DMA2D OPFCCR register configuration ---------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
|
|
80063e6: 687b ldr r3, [r7, #4]
|
|
80063e8: 681b ldr r3, [r3, #0]
|
|
80063ea: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
80063ec: f023 0107 bic.w r1, r3, #7
|
|
80063f0: 687b ldr r3, [r7, #4]
|
|
80063f2: 689a ldr r2, [r3, #8]
|
|
80063f4: 687b ldr r3, [r7, #4]
|
|
80063f6: 681b ldr r3, [r3, #0]
|
|
80063f8: 430a orrs r2, r1
|
|
80063fa: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* DMA2D OOR register configuration ------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
|
|
80063fc: 687b ldr r3, [r7, #4]
|
|
80063fe: 681b ldr r3, [r3, #0]
|
|
8006400: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
8006402: 4b0a ldr r3, [pc, #40] ; (800642c <HAL_DMA2D_Init+0x90>)
|
|
8006404: 4013 ands r3, r2
|
|
8006406: 687a ldr r2, [r7, #4]
|
|
8006408: 68d1 ldr r1, [r2, #12]
|
|
800640a: 687a ldr r2, [r7, #4]
|
|
800640c: 6812 ldr r2, [r2, #0]
|
|
800640e: 430b orrs r3, r1
|
|
8006410: 6413 str r3, [r2, #64] ; 0x40
|
|
MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
|
|
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
|
|
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
|
|
8006412: 687b ldr r3, [r7, #4]
|
|
8006414: 2200 movs r2, #0
|
|
8006416: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8006418: 687b ldr r3, [r7, #4]
|
|
800641a: 2201 movs r2, #1
|
|
800641c: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
return HAL_OK;
|
|
8006420: 2300 movs r3, #0
|
|
}
|
|
8006422: 4618 mov r0, r3
|
|
8006424: 3708 adds r7, #8
|
|
8006426: 46bd mov sp, r7
|
|
8006428: bd80 pop {r7, pc}
|
|
800642a: bf00 nop
|
|
800642c: ffffc000 .word 0xffffc000
|
|
|
|
08006430 <HAL_DMA2D_Start>:
|
|
* @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
|
|
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
|
|
{
|
|
8006430: b580 push {r7, lr}
|
|
8006432: b086 sub sp, #24
|
|
8006434: af02 add r7, sp, #8
|
|
8006436: 60f8 str r0, [r7, #12]
|
|
8006438: 60b9 str r1, [r7, #8]
|
|
800643a: 607a str r2, [r7, #4]
|
|
800643c: 603b str r3, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA2D_LINE(Height));
|
|
assert_param(IS_DMA2D_PIXEL(Width));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma2d);
|
|
800643e: 68fb ldr r3, [r7, #12]
|
|
8006440: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
|
|
8006444: 2b01 cmp r3, #1
|
|
8006446: d101 bne.n 800644c <HAL_DMA2D_Start+0x1c>
|
|
8006448: 2302 movs r3, #2
|
|
800644a: e018 b.n 800647e <HAL_DMA2D_Start+0x4e>
|
|
800644c: 68fb ldr r3, [r7, #12]
|
|
800644e: 2201 movs r2, #1
|
|
8006450: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8006454: 68fb ldr r3, [r7, #12]
|
|
8006456: 2202 movs r2, #2
|
|
8006458: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Configure the source, destination address and the data size */
|
|
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
|
|
800645c: 69bb ldr r3, [r7, #24]
|
|
800645e: 9300 str r3, [sp, #0]
|
|
8006460: 683b ldr r3, [r7, #0]
|
|
8006462: 687a ldr r2, [r7, #4]
|
|
8006464: 68b9 ldr r1, [r7, #8]
|
|
8006466: 68f8 ldr r0, [r7, #12]
|
|
8006468: f000 f988 bl 800677c <DMA2D_SetConfig>
|
|
|
|
/* Enable the Peripheral */
|
|
__HAL_DMA2D_ENABLE(hdma2d);
|
|
800646c: 68fb ldr r3, [r7, #12]
|
|
800646e: 681b ldr r3, [r3, #0]
|
|
8006470: 681a ldr r2, [r3, #0]
|
|
8006472: 68fb ldr r3, [r7, #12]
|
|
8006474: 681b ldr r3, [r3, #0]
|
|
8006476: f042 0201 orr.w r2, r2, #1
|
|
800647a: 601a str r2, [r3, #0]
|
|
|
|
return HAL_OK;
|
|
800647c: 2300 movs r3, #0
|
|
}
|
|
800647e: 4618 mov r0, r3
|
|
8006480: 3710 adds r7, #16
|
|
8006482: 46bd mov sp, r7
|
|
8006484: bd80 pop {r7, pc}
|
|
|
|
08006486 <HAL_DMA2D_PollForTransfer>:
|
|
* the configuration information for the DMA2D.
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
|
|
{
|
|
8006486: b580 push {r7, lr}
|
|
8006488: b086 sub sp, #24
|
|
800648a: af00 add r7, sp, #0
|
|
800648c: 6078 str r0, [r7, #4]
|
|
800648e: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
uint32_t layer_start;
|
|
__IO uint32_t isrflags = 0x0U;
|
|
8006490: 2300 movs r3, #0
|
|
8006492: 60fb str r3, [r7, #12]
|
|
|
|
/* Polling for DMA2D transfer */
|
|
if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
|
|
8006494: 687b ldr r3, [r7, #4]
|
|
8006496: 681b ldr r3, [r3, #0]
|
|
8006498: 681b ldr r3, [r3, #0]
|
|
800649a: f003 0301 and.w r3, r3, #1
|
|
800649e: 2b00 cmp r3, #0
|
|
80064a0: d056 beq.n 8006550 <HAL_DMA2D_PollForTransfer+0xca>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80064a2: f7fe ff1d bl 80052e0 <HAL_GetTick>
|
|
80064a6: 6178 str r0, [r7, #20]
|
|
|
|
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
|
|
80064a8: e04b b.n 8006542 <HAL_DMA2D_PollForTransfer+0xbc>
|
|
{
|
|
isrflags = READ_REG(hdma2d->Instance->ISR);
|
|
80064aa: 687b ldr r3, [r7, #4]
|
|
80064ac: 681b ldr r3, [r3, #0]
|
|
80064ae: 685b ldr r3, [r3, #4]
|
|
80064b0: 60fb str r3, [r7, #12]
|
|
if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
|
|
80064b2: 68fb ldr r3, [r7, #12]
|
|
80064b4: f003 0321 and.w r3, r3, #33 ; 0x21
|
|
80064b8: 2b00 cmp r3, #0
|
|
80064ba: d023 beq.n 8006504 <HAL_DMA2D_PollForTransfer+0x7e>
|
|
{
|
|
if ((isrflags & DMA2D_FLAG_CE) != 0U)
|
|
80064bc: 68fb ldr r3, [r7, #12]
|
|
80064be: f003 0320 and.w r3, r3, #32
|
|
80064c2: 2b00 cmp r3, #0
|
|
80064c4: d005 beq.n 80064d2 <HAL_DMA2D_PollForTransfer+0x4c>
|
|
{
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
|
|
80064c6: 687b ldr r3, [r7, #4]
|
|
80064c8: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
80064ca: f043 0202 orr.w r2, r3, #2
|
|
80064ce: 687b ldr r3, [r7, #4]
|
|
80064d0: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
if ((isrflags & DMA2D_FLAG_TE) != 0U)
|
|
80064d2: 68fb ldr r3, [r7, #12]
|
|
80064d4: f003 0301 and.w r3, r3, #1
|
|
80064d8: 2b00 cmp r3, #0
|
|
80064da: d005 beq.n 80064e8 <HAL_DMA2D_PollForTransfer+0x62>
|
|
{
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
|
|
80064dc: 687b ldr r3, [r7, #4]
|
|
80064de: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
80064e0: f043 0201 orr.w r2, r3, #1
|
|
80064e4: 687b ldr r3, [r7, #4]
|
|
80064e6: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Clear the transfer and configuration error flags */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
|
|
80064e8: 687b ldr r3, [r7, #4]
|
|
80064ea: 681b ldr r3, [r3, #0]
|
|
80064ec: 2221 movs r2, #33 ; 0x21
|
|
80064ee: 609a str r2, [r3, #8]
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
80064f0: 687b ldr r3, [r7, #4]
|
|
80064f2: 2204 movs r2, #4
|
|
80064f4: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
80064f8: 687b ldr r3, [r7, #4]
|
|
80064fa: 2200 movs r2, #0
|
|
80064fc: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_ERROR;
|
|
8006500: 2301 movs r3, #1
|
|
8006502: e0a5 b.n 8006650 <HAL_DMA2D_PollForTransfer+0x1ca>
|
|
}
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
8006504: 683b ldr r3, [r7, #0]
|
|
8006506: f1b3 3fff cmp.w r3, #4294967295
|
|
800650a: d01a beq.n 8006542 <HAL_DMA2D_PollForTransfer+0xbc>
|
|
{
|
|
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
|
|
800650c: f7fe fee8 bl 80052e0 <HAL_GetTick>
|
|
8006510: 4602 mov r2, r0
|
|
8006512: 697b ldr r3, [r7, #20]
|
|
8006514: 1ad3 subs r3, r2, r3
|
|
8006516: 683a ldr r2, [r7, #0]
|
|
8006518: 429a cmp r2, r3
|
|
800651a: d302 bcc.n 8006522 <HAL_DMA2D_PollForTransfer+0x9c>
|
|
800651c: 683b ldr r3, [r7, #0]
|
|
800651e: 2b00 cmp r3, #0
|
|
8006520: d10f bne.n 8006542 <HAL_DMA2D_PollForTransfer+0xbc>
|
|
{
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
|
|
8006522: 687b ldr r3, [r7, #4]
|
|
8006524: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
8006526: f043 0220 orr.w r2, r3, #32
|
|
800652a: 687b ldr r3, [r7, #4]
|
|
800652c: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
|
|
800652e: 687b ldr r3, [r7, #4]
|
|
8006530: 2203 movs r2, #3
|
|
8006532: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8006536: 687b ldr r3, [r7, #4]
|
|
8006538: 2200 movs r2, #0
|
|
800653a: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_TIMEOUT;
|
|
800653e: 2303 movs r3, #3
|
|
8006540: e086 b.n 8006650 <HAL_DMA2D_PollForTransfer+0x1ca>
|
|
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
|
|
8006542: 687b ldr r3, [r7, #4]
|
|
8006544: 681b ldr r3, [r3, #0]
|
|
8006546: 685b ldr r3, [r3, #4]
|
|
8006548: f003 0302 and.w r3, r3, #2
|
|
800654c: 2b00 cmp r3, #0
|
|
800654e: d0ac beq.n 80064aa <HAL_DMA2D_PollForTransfer+0x24>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Polling for CLUT loading (foreground or background) */
|
|
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
|
|
8006550: 687b ldr r3, [r7, #4]
|
|
8006552: 681b ldr r3, [r3, #0]
|
|
8006554: 69db ldr r3, [r3, #28]
|
|
8006556: f003 0320 and.w r3, r3, #32
|
|
800655a: 613b str r3, [r7, #16]
|
|
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
|
|
800655c: 687b ldr r3, [r7, #4]
|
|
800655e: 681b ldr r3, [r3, #0]
|
|
8006560: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8006562: f003 0320 and.w r3, r3, #32
|
|
8006566: 693a ldr r2, [r7, #16]
|
|
8006568: 4313 orrs r3, r2
|
|
800656a: 613b str r3, [r7, #16]
|
|
if (layer_start != 0U)
|
|
800656c: 693b ldr r3, [r7, #16]
|
|
800656e: 2b00 cmp r3, #0
|
|
8006570: d061 beq.n 8006636 <HAL_DMA2D_PollForTransfer+0x1b0>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8006572: f7fe feb5 bl 80052e0 <HAL_GetTick>
|
|
8006576: 6178 str r0, [r7, #20]
|
|
|
|
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
|
|
8006578: e056 b.n 8006628 <HAL_DMA2D_PollForTransfer+0x1a2>
|
|
{
|
|
isrflags = READ_REG(hdma2d->Instance->ISR);
|
|
800657a: 687b ldr r3, [r7, #4]
|
|
800657c: 681b ldr r3, [r3, #0]
|
|
800657e: 685b ldr r3, [r3, #4]
|
|
8006580: 60fb str r3, [r7, #12]
|
|
if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
|
|
8006582: 68fb ldr r3, [r7, #12]
|
|
8006584: f003 0329 and.w r3, r3, #41 ; 0x29
|
|
8006588: 2b00 cmp r3, #0
|
|
800658a: d02e beq.n 80065ea <HAL_DMA2D_PollForTransfer+0x164>
|
|
{
|
|
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
|
|
800658c: 68fb ldr r3, [r7, #12]
|
|
800658e: f003 0308 and.w r3, r3, #8
|
|
8006592: 2b00 cmp r3, #0
|
|
8006594: d005 beq.n 80065a2 <HAL_DMA2D_PollForTransfer+0x11c>
|
|
{
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
|
|
8006596: 687b ldr r3, [r7, #4]
|
|
8006598: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800659a: f043 0204 orr.w r2, r3, #4
|
|
800659e: 687b ldr r3, [r7, #4]
|
|
80065a0: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
if ((isrflags & DMA2D_FLAG_CE) != 0U)
|
|
80065a2: 68fb ldr r3, [r7, #12]
|
|
80065a4: f003 0320 and.w r3, r3, #32
|
|
80065a8: 2b00 cmp r3, #0
|
|
80065aa: d005 beq.n 80065b8 <HAL_DMA2D_PollForTransfer+0x132>
|
|
{
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
|
|
80065ac: 687b ldr r3, [r7, #4]
|
|
80065ae: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
80065b0: f043 0202 orr.w r2, r3, #2
|
|
80065b4: 687b ldr r3, [r7, #4]
|
|
80065b6: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
if ((isrflags & DMA2D_FLAG_TE) != 0U)
|
|
80065b8: 68fb ldr r3, [r7, #12]
|
|
80065ba: f003 0301 and.w r3, r3, #1
|
|
80065be: 2b00 cmp r3, #0
|
|
80065c0: d005 beq.n 80065ce <HAL_DMA2D_PollForTransfer+0x148>
|
|
{
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
|
|
80065c2: 687b ldr r3, [r7, #4]
|
|
80065c4: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
80065c6: f043 0201 orr.w r2, r3, #1
|
|
80065ca: 687b ldr r3, [r7, #4]
|
|
80065cc: 63da str r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
|
|
80065ce: 687b ldr r3, [r7, #4]
|
|
80065d0: 681b ldr r3, [r3, #0]
|
|
80065d2: 2229 movs r2, #41 ; 0x29
|
|
80065d4: 609a str r2, [r3, #8]
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State= HAL_DMA2D_STATE_ERROR;
|
|
80065d6: 687b ldr r3, [r7, #4]
|
|
80065d8: 2204 movs r2, #4
|
|
80065da: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
80065de: 687b ldr r3, [r7, #4]
|
|
80065e0: 2200 movs r2, #0
|
|
80065e2: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_ERROR;
|
|
80065e6: 2301 movs r3, #1
|
|
80065e8: e032 b.n 8006650 <HAL_DMA2D_PollForTransfer+0x1ca>
|
|
}
|
|
/* Check for the Timeout */
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
80065ea: 683b ldr r3, [r7, #0]
|
|
80065ec: f1b3 3fff cmp.w r3, #4294967295
|
|
80065f0: d01a beq.n 8006628 <HAL_DMA2D_PollForTransfer+0x1a2>
|
|
{
|
|
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
|
|
80065f2: f7fe fe75 bl 80052e0 <HAL_GetTick>
|
|
80065f6: 4602 mov r2, r0
|
|
80065f8: 697b ldr r3, [r7, #20]
|
|
80065fa: 1ad3 subs r3, r2, r3
|
|
80065fc: 683a ldr r2, [r7, #0]
|
|
80065fe: 429a cmp r2, r3
|
|
8006600: d302 bcc.n 8006608 <HAL_DMA2D_PollForTransfer+0x182>
|
|
8006602: 683b ldr r3, [r7, #0]
|
|
8006604: 2b00 cmp r3, #0
|
|
8006606: d10f bne.n 8006628 <HAL_DMA2D_PollForTransfer+0x1a2>
|
|
{
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
|
|
8006608: 687b ldr r3, [r7, #4]
|
|
800660a: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800660c: f043 0220 orr.w r2, r3, #32
|
|
8006610: 687b ldr r3, [r7, #4]
|
|
8006612: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the DMA2D state */
|
|
hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
|
|
8006614: 687b ldr r3, [r7, #4]
|
|
8006616: 2203 movs r2, #3
|
|
8006618: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
800661c: 687b ldr r3, [r7, #4]
|
|
800661e: 2200 movs r2, #0
|
|
8006620: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_TIMEOUT;
|
|
8006624: 2303 movs r3, #3
|
|
8006626: e013 b.n 8006650 <HAL_DMA2D_PollForTransfer+0x1ca>
|
|
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
|
|
8006628: 687b ldr r3, [r7, #4]
|
|
800662a: 681b ldr r3, [r3, #0]
|
|
800662c: 685b ldr r3, [r3, #4]
|
|
800662e: f003 0310 and.w r3, r3, #16
|
|
8006632: 2b00 cmp r3, #0
|
|
8006634: d0a1 beq.n 800657a <HAL_DMA2D_PollForTransfer+0xf4>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Clear the transfer complete and CLUT loading flags */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
|
|
8006636: 687b ldr r3, [r7, #4]
|
|
8006638: 681b ldr r3, [r3, #0]
|
|
800663a: 2212 movs r2, #18
|
|
800663c: 609a str r2, [r3, #8]
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
800663e: 687b ldr r3, [r7, #4]
|
|
8006640: 2201 movs r2, #1
|
|
8006642: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8006646: 687b ldr r3, [r7, #4]
|
|
8006648: 2200 movs r2, #0
|
|
800664a: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_OK;
|
|
800664e: 2300 movs r3, #0
|
|
}
|
|
8006650: 4618 mov r0, r3
|
|
8006652: 3718 adds r7, #24
|
|
8006654: 46bd mov sp, r7
|
|
8006656: bd80 pop {r7, pc}
|
|
|
|
08006658 <HAL_DMA2D_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
|
|
{
|
|
8006658: b480 push {r7}
|
|
800665a: b087 sub sp, #28
|
|
800665c: af00 add r7, sp, #0
|
|
800665e: 6078 str r0, [r7, #4]
|
|
8006660: 6039 str r1, [r7, #0]
|
|
uint32_t regMask, regValue;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA2D_LAYER(LayerIdx));
|
|
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
|
|
if(hdma2d->Init.Mode != DMA2D_R2M)
|
|
8006662: 687b ldr r3, [r7, #4]
|
|
8006664: 685b ldr r3, [r3, #4]
|
|
8006666: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
|
|
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
|
|
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
|
|
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma2d);
|
|
800666a: 687b ldr r3, [r7, #4]
|
|
800666c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
|
|
8006670: 2b01 cmp r3, #1
|
|
8006672: d101 bne.n 8006678 <HAL_DMA2D_ConfigLayer+0x20>
|
|
8006674: 2302 movs r3, #2
|
|
8006676: e079 b.n 800676c <HAL_DMA2D_ConfigLayer+0x114>
|
|
8006678: 687b ldr r3, [r7, #4]
|
|
800667a: 2201 movs r2, #1
|
|
800667c: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8006680: 687b ldr r3, [r7, #4]
|
|
8006682: 2202 movs r2, #2
|
|
8006684: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
|
|
8006688: 683b ldr r3, [r7, #0]
|
|
800668a: 011b lsls r3, r3, #4
|
|
800668c: 3318 adds r3, #24
|
|
800668e: 687a ldr r2, [r7, #4]
|
|
8006690: 4413 add r3, r2
|
|
8006692: 613b str r3, [r7, #16]
|
|
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
|
|
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
|
|
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
|
|
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
|
|
#else
|
|
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
|
|
8006694: 693b ldr r3, [r7, #16]
|
|
8006696: 685a ldr r2, [r3, #4]
|
|
8006698: 693b ldr r3, [r7, #16]
|
|
800669a: 689b ldr r3, [r3, #8]
|
|
800669c: 041b lsls r3, r3, #16
|
|
800669e: 4313 orrs r3, r2
|
|
80066a0: 617b str r3, [r7, #20]
|
|
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
|
|
80066a2: 4b35 ldr r3, [pc, #212] ; (8006778 <HAL_DMA2D_ConfigLayer+0x120>)
|
|
80066a4: 60fb str r3, [r7, #12]
|
|
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
|
|
|
|
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
80066a6: 693b ldr r3, [r7, #16]
|
|
80066a8: 685b ldr r3, [r3, #4]
|
|
80066aa: 2b0a cmp r3, #10
|
|
80066ac: d003 beq.n 80066b6 <HAL_DMA2D_ConfigLayer+0x5e>
|
|
80066ae: 693b ldr r3, [r7, #16]
|
|
80066b0: 685b ldr r3, [r3, #4]
|
|
80066b2: 2b09 cmp r3, #9
|
|
80066b4: d107 bne.n 80066c6 <HAL_DMA2D_ConfigLayer+0x6e>
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
|
|
80066b6: 693b ldr r3, [r7, #16]
|
|
80066b8: 68db ldr r3, [r3, #12]
|
|
80066ba: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
|
|
80066be: 697a ldr r2, [r7, #20]
|
|
80066c0: 4313 orrs r3, r2
|
|
80066c2: 617b str r3, [r7, #20]
|
|
80066c4: e005 b.n 80066d2 <HAL_DMA2D_ConfigLayer+0x7a>
|
|
}
|
|
else
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
|
|
80066c6: 693b ldr r3, [r7, #16]
|
|
80066c8: 68db ldr r3, [r3, #12]
|
|
80066ca: 061b lsls r3, r3, #24
|
|
80066cc: 697a ldr r2, [r7, #20]
|
|
80066ce: 4313 orrs r3, r2
|
|
80066d0: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Configure the background DMA2D layer */
|
|
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
|
|
80066d2: 683b ldr r3, [r7, #0]
|
|
80066d4: 2b00 cmp r3, #0
|
|
80066d6: d120 bne.n 800671a <HAL_DMA2D_ConfigLayer+0xc2>
|
|
{
|
|
/* Write DMA2D BGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
|
|
80066d8: 687b ldr r3, [r7, #4]
|
|
80066da: 681b ldr r3, [r3, #0]
|
|
80066dc: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
80066de: 68fb ldr r3, [r7, #12]
|
|
80066e0: 43db mvns r3, r3
|
|
80066e2: ea02 0103 and.w r1, r2, r3
|
|
80066e6: 687b ldr r3, [r7, #4]
|
|
80066e8: 681b ldr r3, [r3, #0]
|
|
80066ea: 697a ldr r2, [r7, #20]
|
|
80066ec: 430a orrs r2, r1
|
|
80066ee: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* DMA2D BGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
|
|
80066f0: 687b ldr r3, [r7, #4]
|
|
80066f2: 681b ldr r3, [r3, #0]
|
|
80066f4: 693a ldr r2, [r7, #16]
|
|
80066f6: 6812 ldr r2, [r2, #0]
|
|
80066f8: 619a str r2, [r3, #24]
|
|
|
|
/* DMA2D BGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
80066fa: 693b ldr r3, [r7, #16]
|
|
80066fc: 685b ldr r3, [r3, #4]
|
|
80066fe: 2b0a cmp r3, #10
|
|
8006700: d003 beq.n 800670a <HAL_DMA2D_ConfigLayer+0xb2>
|
|
8006702: 693b ldr r3, [r7, #16]
|
|
8006704: 685b ldr r3, [r3, #4]
|
|
8006706: 2b09 cmp r3, #9
|
|
8006708: d127 bne.n 800675a <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
|
|
800670a: 693b ldr r3, [r7, #16]
|
|
800670c: 68da ldr r2, [r3, #12]
|
|
800670e: 687b ldr r3, [r7, #4]
|
|
8006710: 681b ldr r3, [r3, #0]
|
|
8006712: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
|
|
8006716: 629a str r2, [r3, #40] ; 0x28
|
|
8006718: e01f b.n 800675a <HAL_DMA2D_ConfigLayer+0x102>
|
|
else
|
|
{
|
|
|
|
|
|
/* Write DMA2D FGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
|
|
800671a: 687b ldr r3, [r7, #4]
|
|
800671c: 681b ldr r3, [r3, #0]
|
|
800671e: 69da ldr r2, [r3, #28]
|
|
8006720: 68fb ldr r3, [r7, #12]
|
|
8006722: 43db mvns r3, r3
|
|
8006724: ea02 0103 and.w r1, r2, r3
|
|
8006728: 687b ldr r3, [r7, #4]
|
|
800672a: 681b ldr r3, [r3, #0]
|
|
800672c: 697a ldr r2, [r7, #20]
|
|
800672e: 430a orrs r2, r1
|
|
8006730: 61da str r2, [r3, #28]
|
|
|
|
/* DMA2D FGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
|
|
8006732: 687b ldr r3, [r7, #4]
|
|
8006734: 681b ldr r3, [r3, #0]
|
|
8006736: 693a ldr r2, [r7, #16]
|
|
8006738: 6812 ldr r2, [r2, #0]
|
|
800673a: 611a str r2, [r3, #16]
|
|
|
|
/* DMA2D FGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
800673c: 693b ldr r3, [r7, #16]
|
|
800673e: 685b ldr r3, [r3, #4]
|
|
8006740: 2b0a cmp r3, #10
|
|
8006742: d003 beq.n 800674c <HAL_DMA2D_ConfigLayer+0xf4>
|
|
8006744: 693b ldr r3, [r7, #16]
|
|
8006746: 685b ldr r3, [r3, #4]
|
|
8006748: 2b09 cmp r3, #9
|
|
800674a: d106 bne.n 800675a <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
|
|
800674c: 693b ldr r3, [r7, #16]
|
|
800674e: 68da ldr r2, [r3, #12]
|
|
8006750: 687b ldr r3, [r7, #4]
|
|
8006752: 681b ldr r3, [r3, #0]
|
|
8006754: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
|
|
8006758: 621a str r2, [r3, #32]
|
|
}
|
|
}
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
800675a: 687b ldr r3, [r7, #4]
|
|
800675c: 2201 movs r2, #1
|
|
800675e: f883 2039 strb.w r2, [r3, #57] ; 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8006762: 687b ldr r3, [r7, #4]
|
|
8006764: 2200 movs r2, #0
|
|
8006766: f883 2038 strb.w r2, [r3, #56] ; 0x38
|
|
|
|
return HAL_OK;
|
|
800676a: 2300 movs r3, #0
|
|
}
|
|
800676c: 4618 mov r0, r3
|
|
800676e: 371c adds r7, #28
|
|
8006770: 46bd mov sp, r7
|
|
8006772: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006776: 4770 bx lr
|
|
8006778: ff03000f .word 0xff03000f
|
|
|
|
0800677c <DMA2D_SetConfig>:
|
|
* @param Width The width of data to be transferred from source to destination.
|
|
* @param Height The height of data to be transferred from source to destination.
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
|
|
{
|
|
800677c: b480 push {r7}
|
|
800677e: b08b sub sp, #44 ; 0x2c
|
|
8006780: af00 add r7, sp, #0
|
|
8006782: 60f8 str r0, [r7, #12]
|
|
8006784: 60b9 str r1, [r7, #8]
|
|
8006786: 607a str r2, [r7, #4]
|
|
8006788: 603b str r3, [r7, #0]
|
|
uint32_t tmp2;
|
|
uint32_t tmp3;
|
|
uint32_t tmp4;
|
|
|
|
/* Configure DMA2D data size */
|
|
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
|
|
800678a: 68fb ldr r3, [r7, #12]
|
|
800678c: 681b ldr r3, [r3, #0]
|
|
800678e: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8006790: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
|
|
8006794: 683b ldr r3, [r7, #0]
|
|
8006796: 041a lsls r2, r3, #16
|
|
8006798: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800679a: 431a orrs r2, r3
|
|
800679c: 68fb ldr r3, [r7, #12]
|
|
800679e: 681b ldr r3, [r3, #0]
|
|
80067a0: 430a orrs r2, r1
|
|
80067a2: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Configure DMA2D destination address */
|
|
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
|
|
80067a4: 68fb ldr r3, [r7, #12]
|
|
80067a6: 681b ldr r3, [r3, #0]
|
|
80067a8: 687a ldr r2, [r7, #4]
|
|
80067aa: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Register to memory DMA2D mode selected */
|
|
if (hdma2d->Init.Mode == DMA2D_R2M)
|
|
80067ac: 68fb ldr r3, [r7, #12]
|
|
80067ae: 685b ldr r3, [r3, #4]
|
|
80067b0: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
|
|
80067b4: d174 bne.n 80068a0 <DMA2D_SetConfig+0x124>
|
|
{
|
|
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
|
|
80067b6: 68bb ldr r3, [r7, #8]
|
|
80067b8: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
|
|
80067bc: 623b str r3, [r7, #32]
|
|
tmp2 = pdata & DMA2D_OCOLR_RED_1;
|
|
80067be: 68bb ldr r3, [r7, #8]
|
|
80067c0: f403 037f and.w r3, r3, #16711680 ; 0xff0000
|
|
80067c4: 61fb str r3, [r7, #28]
|
|
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
|
|
80067c6: 68bb ldr r3, [r7, #8]
|
|
80067c8: f403 437f and.w r3, r3, #65280 ; 0xff00
|
|
80067cc: 61bb str r3, [r7, #24]
|
|
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
|
|
80067ce: 68bb ldr r3, [r7, #8]
|
|
80067d0: b2db uxtb r3, r3
|
|
80067d2: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the value to be written to the OCOLR register according to the color mode */
|
|
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
|
|
80067d4: 68fb ldr r3, [r7, #12]
|
|
80067d6: 689b ldr r3, [r3, #8]
|
|
80067d8: 2b00 cmp r3, #0
|
|
80067da: d108 bne.n 80067ee <DMA2D_SetConfig+0x72>
|
|
{
|
|
tmp = (tmp3 | tmp2 | tmp1| tmp4);
|
|
80067dc: 69ba ldr r2, [r7, #24]
|
|
80067de: 69fb ldr r3, [r7, #28]
|
|
80067e0: 431a orrs r2, r3
|
|
80067e2: 6a3b ldr r3, [r7, #32]
|
|
80067e4: 4313 orrs r3, r2
|
|
80067e6: 697a ldr r2, [r7, #20]
|
|
80067e8: 4313 orrs r3, r2
|
|
80067ea: 627b str r3, [r7, #36] ; 0x24
|
|
80067ec: e053 b.n 8006896 <DMA2D_SetConfig+0x11a>
|
|
}
|
|
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
|
|
80067ee: 68fb ldr r3, [r7, #12]
|
|
80067f0: 689b ldr r3, [r3, #8]
|
|
80067f2: 2b01 cmp r3, #1
|
|
80067f4: d106 bne.n 8006804 <DMA2D_SetConfig+0x88>
|
|
{
|
|
tmp = (tmp3 | tmp2 | tmp4);
|
|
80067f6: 69ba ldr r2, [r7, #24]
|
|
80067f8: 69fb ldr r3, [r7, #28]
|
|
80067fa: 4313 orrs r3, r2
|
|
80067fc: 697a ldr r2, [r7, #20]
|
|
80067fe: 4313 orrs r3, r2
|
|
8006800: 627b str r3, [r7, #36] ; 0x24
|
|
8006802: e048 b.n 8006896 <DMA2D_SetConfig+0x11a>
|
|
}
|
|
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
|
|
8006804: 68fb ldr r3, [r7, #12]
|
|
8006806: 689b ldr r3, [r3, #8]
|
|
8006808: 2b02 cmp r3, #2
|
|
800680a: d111 bne.n 8006830 <DMA2D_SetConfig+0xb4>
|
|
{
|
|
tmp2 = (tmp2 >> 19U);
|
|
800680c: 69fb ldr r3, [r7, #28]
|
|
800680e: 0cdb lsrs r3, r3, #19
|
|
8006810: 61fb str r3, [r7, #28]
|
|
tmp3 = (tmp3 >> 10U);
|
|
8006812: 69bb ldr r3, [r7, #24]
|
|
8006814: 0a9b lsrs r3, r3, #10
|
|
8006816: 61bb str r3, [r7, #24]
|
|
tmp4 = (tmp4 >> 3U );
|
|
8006818: 697b ldr r3, [r7, #20]
|
|
800681a: 08db lsrs r3, r3, #3
|
|
800681c: 617b str r3, [r7, #20]
|
|
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
|
|
800681e: 69bb ldr r3, [r7, #24]
|
|
8006820: 015a lsls r2, r3, #5
|
|
8006822: 69fb ldr r3, [r7, #28]
|
|
8006824: 02db lsls r3, r3, #11
|
|
8006826: 4313 orrs r3, r2
|
|
8006828: 697a ldr r2, [r7, #20]
|
|
800682a: 4313 orrs r3, r2
|
|
800682c: 627b str r3, [r7, #36] ; 0x24
|
|
800682e: e032 b.n 8006896 <DMA2D_SetConfig+0x11a>
|
|
}
|
|
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
|
|
8006830: 68fb ldr r3, [r7, #12]
|
|
8006832: 689b ldr r3, [r3, #8]
|
|
8006834: 2b03 cmp r3, #3
|
|
8006836: d117 bne.n 8006868 <DMA2D_SetConfig+0xec>
|
|
{
|
|
tmp1 = (tmp1 >> 31U);
|
|
8006838: 6a3b ldr r3, [r7, #32]
|
|
800683a: 0fdb lsrs r3, r3, #31
|
|
800683c: 623b str r3, [r7, #32]
|
|
tmp2 = (tmp2 >> 19U);
|
|
800683e: 69fb ldr r3, [r7, #28]
|
|
8006840: 0cdb lsrs r3, r3, #19
|
|
8006842: 61fb str r3, [r7, #28]
|
|
tmp3 = (tmp3 >> 11U);
|
|
8006844: 69bb ldr r3, [r7, #24]
|
|
8006846: 0adb lsrs r3, r3, #11
|
|
8006848: 61bb str r3, [r7, #24]
|
|
tmp4 = (tmp4 >> 3U );
|
|
800684a: 697b ldr r3, [r7, #20]
|
|
800684c: 08db lsrs r3, r3, #3
|
|
800684e: 617b str r3, [r7, #20]
|
|
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
|
|
8006850: 69bb ldr r3, [r7, #24]
|
|
8006852: 015a lsls r2, r3, #5
|
|
8006854: 69fb ldr r3, [r7, #28]
|
|
8006856: 029b lsls r3, r3, #10
|
|
8006858: 431a orrs r2, r3
|
|
800685a: 6a3b ldr r3, [r7, #32]
|
|
800685c: 03db lsls r3, r3, #15
|
|
800685e: 4313 orrs r3, r2
|
|
8006860: 697a ldr r2, [r7, #20]
|
|
8006862: 4313 orrs r3, r2
|
|
8006864: 627b str r3, [r7, #36] ; 0x24
|
|
8006866: e016 b.n 8006896 <DMA2D_SetConfig+0x11a>
|
|
}
|
|
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
|
|
{
|
|
tmp1 = (tmp1 >> 28U);
|
|
8006868: 6a3b ldr r3, [r7, #32]
|
|
800686a: 0f1b lsrs r3, r3, #28
|
|
800686c: 623b str r3, [r7, #32]
|
|
tmp2 = (tmp2 >> 20U);
|
|
800686e: 69fb ldr r3, [r7, #28]
|
|
8006870: 0d1b lsrs r3, r3, #20
|
|
8006872: 61fb str r3, [r7, #28]
|
|
tmp3 = (tmp3 >> 12U);
|
|
8006874: 69bb ldr r3, [r7, #24]
|
|
8006876: 0b1b lsrs r3, r3, #12
|
|
8006878: 61bb str r3, [r7, #24]
|
|
tmp4 = (tmp4 >> 4U );
|
|
800687a: 697b ldr r3, [r7, #20]
|
|
800687c: 091b lsrs r3, r3, #4
|
|
800687e: 617b str r3, [r7, #20]
|
|
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
|
|
8006880: 69bb ldr r3, [r7, #24]
|
|
8006882: 011a lsls r2, r3, #4
|
|
8006884: 69fb ldr r3, [r7, #28]
|
|
8006886: 021b lsls r3, r3, #8
|
|
8006888: 431a orrs r2, r3
|
|
800688a: 6a3b ldr r3, [r7, #32]
|
|
800688c: 031b lsls r3, r3, #12
|
|
800688e: 4313 orrs r3, r2
|
|
8006890: 697a ldr r2, [r7, #20]
|
|
8006892: 4313 orrs r3, r2
|
|
8006894: 627b str r3, [r7, #36] ; 0x24
|
|
}
|
|
/* Write to DMA2D OCOLR register */
|
|
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
|
|
8006896: 68fb ldr r3, [r7, #12]
|
|
8006898: 681b ldr r3, [r3, #0]
|
|
800689a: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
800689c: 639a str r2, [r3, #56] ; 0x38
|
|
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
|
|
{
|
|
/* Configure DMA2D source address */
|
|
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
|
|
}
|
|
}
|
|
800689e: e003 b.n 80068a8 <DMA2D_SetConfig+0x12c>
|
|
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
|
|
80068a0: 68fb ldr r3, [r7, #12]
|
|
80068a2: 681b ldr r3, [r3, #0]
|
|
80068a4: 68ba ldr r2, [r7, #8]
|
|
80068a6: 60da str r2, [r3, #12]
|
|
}
|
|
80068a8: bf00 nop
|
|
80068aa: 372c adds r7, #44 ; 0x2c
|
|
80068ac: 46bd mov sp, r7
|
|
80068ae: f85d 7b04 ldr.w r7, [sp], #4
|
|
80068b2: 4770 bx lr
|
|
|
|
080068b4 <HAL_ETH_Init>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
|
|
{
|
|
80068b4: b580 push {r7, lr}
|
|
80068b6: b088 sub sp, #32
|
|
80068b8: af00 add r7, sp, #0
|
|
80068ba: 6078 str r0, [r7, #4]
|
|
uint32_t tempreg = 0, phyreg = 0;
|
|
80068bc: 2300 movs r3, #0
|
|
80068be: 61fb str r3, [r7, #28]
|
|
80068c0: 2300 movs r3, #0
|
|
80068c2: 60fb str r3, [r7, #12]
|
|
uint32_t hclk = 60000000;
|
|
80068c4: 4ba9 ldr r3, [pc, #676] ; (8006b6c <HAL_ETH_Init+0x2b8>)
|
|
80068c6: 61bb str r3, [r7, #24]
|
|
uint32_t tickstart = 0;
|
|
80068c8: 2300 movs r3, #0
|
|
80068ca: 617b str r3, [r7, #20]
|
|
uint32_t err = ETH_SUCCESS;
|
|
80068cc: 2300 movs r3, #0
|
|
80068ce: 613b str r3, [r7, #16]
|
|
|
|
/* Check the ETH peripheral state */
|
|
if(heth == NULL)
|
|
80068d0: 687b ldr r3, [r7, #4]
|
|
80068d2: 2b00 cmp r3, #0
|
|
80068d4: d101 bne.n 80068da <HAL_ETH_Init+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
80068d6: 2301 movs r3, #1
|
|
80068d8: e183 b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
|
|
assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
|
|
assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
|
|
assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
|
|
|
|
if(heth->State == HAL_ETH_STATE_RESET)
|
|
80068da: 687b ldr r3, [r7, #4]
|
|
80068dc: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
80068e0: b2db uxtb r3, r3
|
|
80068e2: 2b00 cmp r3, #0
|
|
80068e4: d106 bne.n 80068f4 <HAL_ETH_Init+0x40>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
heth->Lock = HAL_UNLOCKED;
|
|
80068e6: 687b ldr r3, [r7, #4]
|
|
80068e8: 2200 movs r2, #0
|
|
80068ea: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
heth->MspInitCallback(heth);
|
|
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
|
|
HAL_ETH_MspInit(heth);
|
|
80068ee: 6878 ldr r0, [r7, #4]
|
|
80068f0: f006 fa70 bl 800cdd4 <HAL_ETH_MspInit>
|
|
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
80068f4: 4b9e ldr r3, [pc, #632] ; (8006b70 <HAL_ETH_Init+0x2bc>)
|
|
80068f6: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80068f8: 4a9d ldr r2, [pc, #628] ; (8006b70 <HAL_ETH_Init+0x2bc>)
|
|
80068fa: f443 4380 orr.w r3, r3, #16384 ; 0x4000
|
|
80068fe: 6453 str r3, [r2, #68] ; 0x44
|
|
8006900: 4b9b ldr r3, [pc, #620] ; (8006b70 <HAL_ETH_Init+0x2bc>)
|
|
8006902: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8006904: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8006908: 60bb str r3, [r7, #8]
|
|
800690a: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Select MII or RMII Mode*/
|
|
SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
|
|
800690c: 4b99 ldr r3, [pc, #612] ; (8006b74 <HAL_ETH_Init+0x2c0>)
|
|
800690e: 685b ldr r3, [r3, #4]
|
|
8006910: 4a98 ldr r2, [pc, #608] ; (8006b74 <HAL_ETH_Init+0x2c0>)
|
|
8006912: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
|
|
8006916: 6053 str r3, [r2, #4]
|
|
SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
|
|
8006918: 4b96 ldr r3, [pc, #600] ; (8006b74 <HAL_ETH_Init+0x2c0>)
|
|
800691a: 685a ldr r2, [r3, #4]
|
|
800691c: 687b ldr r3, [r7, #4]
|
|
800691e: 6a1b ldr r3, [r3, #32]
|
|
8006920: 4994 ldr r1, [pc, #592] ; (8006b74 <HAL_ETH_Init+0x2c0>)
|
|
8006922: 4313 orrs r3, r2
|
|
8006924: 604b str r3, [r1, #4]
|
|
|
|
/* Ethernet Software reset */
|
|
/* Set the SWR bit: resets all MAC subsystem internal registers and logic */
|
|
/* After reset all the registers holds their respective reset values */
|
|
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
|
|
8006926: 687b ldr r3, [r7, #4]
|
|
8006928: 681b ldr r3, [r3, #0]
|
|
800692a: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
800692e: 681a ldr r2, [r3, #0]
|
|
8006930: 687b ldr r3, [r7, #4]
|
|
8006932: 681b ldr r3, [r3, #0]
|
|
8006934: f042 0201 orr.w r2, r2, #1
|
|
8006938: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
800693c: 601a str r2, [r3, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800693e: f7fe fccf bl 80052e0 <HAL_GetTick>
|
|
8006942: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait for software reset */
|
|
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
|
|
8006944: e011 b.n 800696a <HAL_ETH_Init+0xb6>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
|
|
8006946: f7fe fccb bl 80052e0 <HAL_GetTick>
|
|
800694a: 4602 mov r2, r0
|
|
800694c: 697b ldr r3, [r7, #20]
|
|
800694e: 1ad3 subs r3, r2, r3
|
|
8006950: f5b3 7ffa cmp.w r3, #500 ; 0x1f4
|
|
8006954: d909 bls.n 800696a <HAL_ETH_Init+0xb6>
|
|
{
|
|
heth->State= HAL_ETH_STATE_TIMEOUT;
|
|
8006956: 687b ldr r3, [r7, #4]
|
|
8006958: 2203 movs r2, #3
|
|
800695a: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
800695e: 687b ldr r3, [r7, #4]
|
|
8006960: 2200 movs r2, #0
|
|
8006962: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
|
|
not available, please check your external PHY or the IO configuration */
|
|
|
|
return HAL_TIMEOUT;
|
|
8006966: 2303 movs r3, #3
|
|
8006968: e13b b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
|
|
800696a: 687b ldr r3, [r7, #4]
|
|
800696c: 681b ldr r3, [r3, #0]
|
|
800696e: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
8006972: 681b ldr r3, [r3, #0]
|
|
8006974: f003 0301 and.w r3, r3, #1
|
|
8006978: 2b00 cmp r3, #0
|
|
800697a: d1e4 bne.n 8006946 <HAL_ETH_Init+0x92>
|
|
}
|
|
}
|
|
|
|
/*-------------------------------- MAC Initialization ----------------------*/
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
tempreg = (heth->Instance)->MACMIIAR;
|
|
800697c: 687b ldr r3, [r7, #4]
|
|
800697e: 681b ldr r3, [r3, #0]
|
|
8006980: 691b ldr r3, [r3, #16]
|
|
8006982: 61fb str r3, [r7, #28]
|
|
/* Clear CSR Clock Range CR[2:0] bits */
|
|
tempreg &= ETH_MACMIIAR_CR_MASK;
|
|
8006984: 69fb ldr r3, [r7, #28]
|
|
8006986: f023 031c bic.w r3, r3, #28
|
|
800698a: 61fb str r3, [r7, #28]
|
|
|
|
/* Get hclk frequency value */
|
|
hclk = HAL_RCC_GetHCLKFreq();
|
|
800698c: f003 f9c8 bl 8009d20 <HAL_RCC_GetHCLKFreq>
|
|
8006990: 61b8 str r0, [r7, #24]
|
|
|
|
/* Set CR bits depending on hclk value */
|
|
if((hclk >= 20000000)&&(hclk < 35000000))
|
|
8006992: 69bb ldr r3, [r7, #24]
|
|
8006994: 4a78 ldr r2, [pc, #480] ; (8006b78 <HAL_ETH_Init+0x2c4>)
|
|
8006996: 4293 cmp r3, r2
|
|
8006998: d908 bls.n 80069ac <HAL_ETH_Init+0xf8>
|
|
800699a: 69bb ldr r3, [r7, #24]
|
|
800699c: 4a77 ldr r2, [pc, #476] ; (8006b7c <HAL_ETH_Init+0x2c8>)
|
|
800699e: 4293 cmp r3, r2
|
|
80069a0: d804 bhi.n 80069ac <HAL_ETH_Init+0xf8>
|
|
{
|
|
/* CSR Clock Range between 20-35 MHz */
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
|
|
80069a2: 69fb ldr r3, [r7, #28]
|
|
80069a4: f043 0308 orr.w r3, r3, #8
|
|
80069a8: 61fb str r3, [r7, #28]
|
|
80069aa: e027 b.n 80069fc <HAL_ETH_Init+0x148>
|
|
}
|
|
else if((hclk >= 35000000)&&(hclk < 60000000))
|
|
80069ac: 69bb ldr r3, [r7, #24]
|
|
80069ae: 4a73 ldr r2, [pc, #460] ; (8006b7c <HAL_ETH_Init+0x2c8>)
|
|
80069b0: 4293 cmp r3, r2
|
|
80069b2: d908 bls.n 80069c6 <HAL_ETH_Init+0x112>
|
|
80069b4: 69bb ldr r3, [r7, #24]
|
|
80069b6: 4a72 ldr r2, [pc, #456] ; (8006b80 <HAL_ETH_Init+0x2cc>)
|
|
80069b8: 4293 cmp r3, r2
|
|
80069ba: d804 bhi.n 80069c6 <HAL_ETH_Init+0x112>
|
|
{
|
|
/* CSR Clock Range between 35-60 MHz */
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
|
|
80069bc: 69fb ldr r3, [r7, #28]
|
|
80069be: f043 030c orr.w r3, r3, #12
|
|
80069c2: 61fb str r3, [r7, #28]
|
|
80069c4: e01a b.n 80069fc <HAL_ETH_Init+0x148>
|
|
}
|
|
else if((hclk >= 60000000)&&(hclk < 100000000))
|
|
80069c6: 69bb ldr r3, [r7, #24]
|
|
80069c8: 4a6d ldr r2, [pc, #436] ; (8006b80 <HAL_ETH_Init+0x2cc>)
|
|
80069ca: 4293 cmp r3, r2
|
|
80069cc: d903 bls.n 80069d6 <HAL_ETH_Init+0x122>
|
|
80069ce: 69bb ldr r3, [r7, #24]
|
|
80069d0: 4a6c ldr r2, [pc, #432] ; (8006b84 <HAL_ETH_Init+0x2d0>)
|
|
80069d2: 4293 cmp r3, r2
|
|
80069d4: d911 bls.n 80069fa <HAL_ETH_Init+0x146>
|
|
{
|
|
/* CSR Clock Range between 60-100 MHz */
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
|
|
}
|
|
else if((hclk >= 100000000)&&(hclk < 150000000))
|
|
80069d6: 69bb ldr r3, [r7, #24]
|
|
80069d8: 4a6a ldr r2, [pc, #424] ; (8006b84 <HAL_ETH_Init+0x2d0>)
|
|
80069da: 4293 cmp r3, r2
|
|
80069dc: d908 bls.n 80069f0 <HAL_ETH_Init+0x13c>
|
|
80069de: 69bb ldr r3, [r7, #24]
|
|
80069e0: 4a69 ldr r2, [pc, #420] ; (8006b88 <HAL_ETH_Init+0x2d4>)
|
|
80069e2: 4293 cmp r3, r2
|
|
80069e4: d804 bhi.n 80069f0 <HAL_ETH_Init+0x13c>
|
|
{
|
|
/* CSR Clock Range between 100-150 MHz */
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
|
|
80069e6: 69fb ldr r3, [r7, #28]
|
|
80069e8: f043 0304 orr.w r3, r3, #4
|
|
80069ec: 61fb str r3, [r7, #28]
|
|
80069ee: e005 b.n 80069fc <HAL_ETH_Init+0x148>
|
|
}
|
|
else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
|
|
{
|
|
/* CSR Clock Range between 150-216 MHz */
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
|
|
80069f0: 69fb ldr r3, [r7, #28]
|
|
80069f2: f043 0310 orr.w r3, r3, #16
|
|
80069f6: 61fb str r3, [r7, #28]
|
|
80069f8: e000 b.n 80069fc <HAL_ETH_Init+0x148>
|
|
tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
|
|
80069fa: bf00 nop
|
|
}
|
|
|
|
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
|
|
(heth->Instance)->MACMIIAR = (uint32_t)tempreg;
|
|
80069fc: 687b ldr r3, [r7, #4]
|
|
80069fe: 681b ldr r3, [r3, #0]
|
|
8006a00: 69fa ldr r2, [r7, #28]
|
|
8006a02: 611a str r2, [r3, #16]
|
|
|
|
/*-------------------- PHY initialization and configuration ----------------*/
|
|
/* Put the PHY in reset mode */
|
|
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
|
|
8006a04: f44f 4200 mov.w r2, #32768 ; 0x8000
|
|
8006a08: 2100 movs r1, #0
|
|
8006a0a: 6878 ldr r0, [r7, #4]
|
|
8006a0c: f000 fc19 bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
8006a10: 4603 mov r3, r0
|
|
8006a12: 2b00 cmp r3, #0
|
|
8006a14: d00b beq.n 8006a2e <HAL_ETH_Init+0x17a>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006a16: 2301 movs r3, #1
|
|
8006a18: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006a1a: 6939 ldr r1, [r7, #16]
|
|
8006a1c: 6878 ldr r0, [r7, #4]
|
|
8006a1e: f000 fdcf bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
/* Set the ETH peripheral state to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006a22: 687b ldr r3, [r7, #4]
|
|
8006a24: 2201 movs r2, #1
|
|
8006a26: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return HAL_ERROR */
|
|
return HAL_ERROR;
|
|
8006a2a: 2301 movs r3, #1
|
|
8006a2c: e0d9 b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
|
|
/* Delay to assure PHY reset */
|
|
HAL_Delay(PHY_RESET_DELAY);
|
|
8006a2e: 20ff movs r0, #255 ; 0xff
|
|
8006a30: f7fe fc62 bl 80052f8 <HAL_Delay>
|
|
|
|
if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
|
|
8006a34: 687b ldr r3, [r7, #4]
|
|
8006a36: 685b ldr r3, [r3, #4]
|
|
8006a38: 2b00 cmp r3, #0
|
|
8006a3a: f000 80a7 beq.w 8006b8c <HAL_ETH_Init+0x2d8>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8006a3e: f7fe fc4f bl 80052e0 <HAL_GetTick>
|
|
8006a42: 6178 str r0, [r7, #20]
|
|
|
|
/* We wait for linked status */
|
|
do
|
|
{
|
|
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
|
|
8006a44: f107 030c add.w r3, r7, #12
|
|
8006a48: 461a mov r2, r3
|
|
8006a4a: 2101 movs r1, #1
|
|
8006a4c: 6878 ldr r0, [r7, #4]
|
|
8006a4e: f000 fb90 bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
|
|
8006a52: f7fe fc45 bl 80052e0 <HAL_GetTick>
|
|
8006a56: 4602 mov r2, r0
|
|
8006a58: 697b ldr r3, [r7, #20]
|
|
8006a5a: 1ad3 subs r3, r2, r3
|
|
8006a5c: f241 3288 movw r2, #5000 ; 0x1388
|
|
8006a60: 4293 cmp r3, r2
|
|
8006a62: d90f bls.n 8006a84 <HAL_ETH_Init+0x1d0>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006a64: 2301 movs r3, #1
|
|
8006a66: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006a68: 6939 ldr r1, [r7, #16]
|
|
8006a6a: 6878 ldr r0, [r7, #4]
|
|
8006a6c: f000 fda8 bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8006a70: 687b ldr r3, [r7, #4]
|
|
8006a72: 2201 movs r2, #1
|
|
8006a74: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006a78: 687b ldr r3, [r7, #4]
|
|
8006a7a: 2200 movs r2, #0
|
|
8006a7c: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_TIMEOUT;
|
|
8006a80: 2303 movs r3, #3
|
|
8006a82: e0ae b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
} while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
|
|
8006a84: 68fb ldr r3, [r7, #12]
|
|
8006a86: f003 0304 and.w r3, r3, #4
|
|
8006a8a: 2b00 cmp r3, #0
|
|
8006a8c: d0da beq.n 8006a44 <HAL_ETH_Init+0x190>
|
|
|
|
|
|
/* Enable Auto-Negotiation */
|
|
if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
|
|
8006a8e: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
8006a92: 2100 movs r1, #0
|
|
8006a94: 6878 ldr r0, [r7, #4]
|
|
8006a96: f000 fbd4 bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
8006a9a: 4603 mov r3, r0
|
|
8006a9c: 2b00 cmp r3, #0
|
|
8006a9e: d00b beq.n 8006ab8 <HAL_ETH_Init+0x204>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006aa0: 2301 movs r3, #1
|
|
8006aa2: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006aa4: 6939 ldr r1, [r7, #16]
|
|
8006aa6: 6878 ldr r0, [r7, #4]
|
|
8006aa8: f000 fd8a bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
/* Set the ETH peripheral state to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006aac: 687b ldr r3, [r7, #4]
|
|
8006aae: 2201 movs r2, #1
|
|
8006ab0: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return HAL_ERROR */
|
|
return HAL_ERROR;
|
|
8006ab4: 2301 movs r3, #1
|
|
8006ab6: e094 b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8006ab8: f7fe fc12 bl 80052e0 <HAL_GetTick>
|
|
8006abc: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
do
|
|
{
|
|
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
|
|
8006abe: f107 030c add.w r3, r7, #12
|
|
8006ac2: 461a mov r2, r3
|
|
8006ac4: 2101 movs r1, #1
|
|
8006ac6: 6878 ldr r0, [r7, #4]
|
|
8006ac8: f000 fb53 bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
|
|
8006acc: f7fe fc08 bl 80052e0 <HAL_GetTick>
|
|
8006ad0: 4602 mov r2, r0
|
|
8006ad2: 697b ldr r3, [r7, #20]
|
|
8006ad4: 1ad3 subs r3, r2, r3
|
|
8006ad6: f241 3288 movw r2, #5000 ; 0x1388
|
|
8006ada: 4293 cmp r3, r2
|
|
8006adc: d90f bls.n 8006afe <HAL_ETH_Init+0x24a>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006ade: 2301 movs r3, #1
|
|
8006ae0: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006ae2: 6939 ldr r1, [r7, #16]
|
|
8006ae4: 6878 ldr r0, [r7, #4]
|
|
8006ae6: f000 fd6b bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8006aea: 687b ldr r3, [r7, #4]
|
|
8006aec: 2201 movs r2, #1
|
|
8006aee: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006af2: 687b ldr r3, [r7, #4]
|
|
8006af4: 2200 movs r2, #0
|
|
8006af6: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_TIMEOUT;
|
|
8006afa: 2303 movs r3, #3
|
|
8006afc: e071 b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
|
|
} while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
|
|
8006afe: 68fb ldr r3, [r7, #12]
|
|
8006b00: f003 0320 and.w r3, r3, #32
|
|
8006b04: 2b00 cmp r3, #0
|
|
8006b06: d0da beq.n 8006abe <HAL_ETH_Init+0x20a>
|
|
|
|
/* Read the result of the auto-negotiation */
|
|
if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
|
|
8006b08: f107 030c add.w r3, r7, #12
|
|
8006b0c: 461a mov r2, r3
|
|
8006b0e: 211f movs r1, #31
|
|
8006b10: 6878 ldr r0, [r7, #4]
|
|
8006b12: f000 fb2e bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
8006b16: 4603 mov r3, r0
|
|
8006b18: 2b00 cmp r3, #0
|
|
8006b1a: d00b beq.n 8006b34 <HAL_ETH_Init+0x280>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006b1c: 2301 movs r3, #1
|
|
8006b1e: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006b20: 6939 ldr r1, [r7, #16]
|
|
8006b22: 6878 ldr r0, [r7, #4]
|
|
8006b24: f000 fd4c bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
/* Set the ETH peripheral state to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006b28: 687b ldr r3, [r7, #4]
|
|
8006b2a: 2201 movs r2, #1
|
|
8006b2c: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return HAL_ERROR */
|
|
return HAL_ERROR;
|
|
8006b30: 2301 movs r3, #1
|
|
8006b32: e056 b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
|
|
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
|
|
if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
|
|
8006b34: 68fb ldr r3, [r7, #12]
|
|
8006b36: f003 0310 and.w r3, r3, #16
|
|
8006b3a: 2b00 cmp r3, #0
|
|
8006b3c: d004 beq.n 8006b48 <HAL_ETH_Init+0x294>
|
|
{
|
|
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
|
|
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
|
|
8006b3e: 687b ldr r3, [r7, #4]
|
|
8006b40: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
8006b44: 60da str r2, [r3, #12]
|
|
8006b46: e002 b.n 8006b4e <HAL_ETH_Init+0x29a>
|
|
}
|
|
else
|
|
{
|
|
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
|
|
(heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
|
|
8006b48: 687b ldr r3, [r7, #4]
|
|
8006b4a: 2200 movs r2, #0
|
|
8006b4c: 60da str r2, [r3, #12]
|
|
}
|
|
/* Configure the MAC with the speed fixed by the auto-negotiation process */
|
|
if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
|
|
8006b4e: 68fb ldr r3, [r7, #12]
|
|
8006b50: f003 0304 and.w r3, r3, #4
|
|
8006b54: 2b00 cmp r3, #0
|
|
8006b56: d003 beq.n 8006b60 <HAL_ETH_Init+0x2ac>
|
|
{
|
|
/* Set Ethernet speed to 10M following the auto-negotiation */
|
|
(heth->Init).Speed = ETH_SPEED_10M;
|
|
8006b58: 687b ldr r3, [r7, #4]
|
|
8006b5a: 2200 movs r2, #0
|
|
8006b5c: 609a str r2, [r3, #8]
|
|
8006b5e: e037 b.n 8006bd0 <HAL_ETH_Init+0x31c>
|
|
}
|
|
else
|
|
{
|
|
/* Set Ethernet speed to 100M following the auto-negotiation */
|
|
(heth->Init).Speed = ETH_SPEED_100M;
|
|
8006b60: 687b ldr r3, [r7, #4]
|
|
8006b62: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
8006b66: 609a str r2, [r3, #8]
|
|
8006b68: e032 b.n 8006bd0 <HAL_ETH_Init+0x31c>
|
|
8006b6a: bf00 nop
|
|
8006b6c: 03938700 .word 0x03938700
|
|
8006b70: 40023800 .word 0x40023800
|
|
8006b74: 40013800 .word 0x40013800
|
|
8006b78: 01312cff .word 0x01312cff
|
|
8006b7c: 02160ebf .word 0x02160ebf
|
|
8006b80: 039386ff .word 0x039386ff
|
|
8006b84: 05f5e0ff .word 0x05f5e0ff
|
|
8006b88: 08f0d17f .word 0x08f0d17f
|
|
/* Check parameters */
|
|
assert_param(IS_ETH_SPEED(heth->Init.Speed));
|
|
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
|
|
|
|
/* Set MAC Speed and Duplex Mode */
|
|
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
|
|
8006b8c: 687b ldr r3, [r7, #4]
|
|
8006b8e: 68db ldr r3, [r3, #12]
|
|
8006b90: 08db lsrs r3, r3, #3
|
|
8006b92: b29a uxth r2, r3
|
|
(uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
|
|
8006b94: 687b ldr r3, [r7, #4]
|
|
8006b96: 689b ldr r3, [r3, #8]
|
|
8006b98: 085b lsrs r3, r3, #1
|
|
8006b9a: b29b uxth r3, r3
|
|
if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
|
|
8006b9c: 4313 orrs r3, r2
|
|
8006b9e: b29b uxth r3, r3
|
|
8006ba0: 461a mov r2, r3
|
|
8006ba2: 2100 movs r1, #0
|
|
8006ba4: 6878 ldr r0, [r7, #4]
|
|
8006ba6: f000 fb4c bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
8006baa: 4603 mov r3, r0
|
|
8006bac: 2b00 cmp r3, #0
|
|
8006bae: d00b beq.n 8006bc8 <HAL_ETH_Init+0x314>
|
|
{
|
|
/* In case of write timeout */
|
|
err = ETH_ERROR;
|
|
8006bb0: 2301 movs r3, #1
|
|
8006bb2: 613b str r3, [r7, #16]
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006bb4: 6939 ldr r1, [r7, #16]
|
|
8006bb6: 6878 ldr r0, [r7, #4]
|
|
8006bb8: f000 fd02 bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
/* Set the ETH peripheral state to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006bbc: 687b ldr r3, [r7, #4]
|
|
8006bbe: 2201 movs r2, #1
|
|
8006bc0: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return HAL_ERROR */
|
|
return HAL_ERROR;
|
|
8006bc4: 2301 movs r3, #1
|
|
8006bc6: e00c b.n 8006be2 <HAL_ETH_Init+0x32e>
|
|
}
|
|
|
|
/* Delay to assure PHY configuration */
|
|
HAL_Delay(PHY_CONFIG_DELAY);
|
|
8006bc8: f640 70ff movw r0, #4095 ; 0xfff
|
|
8006bcc: f7fe fb94 bl 80052f8 <HAL_Delay>
|
|
}
|
|
|
|
/* Config MAC and DMA */
|
|
ETH_MACDMAConfig(heth, err);
|
|
8006bd0: 6939 ldr r1, [r7, #16]
|
|
8006bd2: 6878 ldr r0, [r7, #4]
|
|
8006bd4: f000 fcf4 bl 80075c0 <ETH_MACDMAConfig>
|
|
|
|
/* Set ETH HAL State to Ready */
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8006bd8: 687b ldr r3, [r7, #4]
|
|
8006bda: 2201 movs r2, #1
|
|
8006bdc: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006be0: 2300 movs r3, #0
|
|
}
|
|
8006be2: 4618 mov r0, r3
|
|
8006be4: 3720 adds r7, #32
|
|
8006be6: 46bd mov sp, r7
|
|
8006be8: bd80 pop {r7, pc}
|
|
8006bea: bf00 nop
|
|
|
|
08006bec <HAL_ETH_DMATxDescListInit>:
|
|
* @param TxBuff Pointer to the first TxBuffer list
|
|
* @param TxBuffCount Number of the used Tx desc in the list
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
|
|
{
|
|
8006bec: b480 push {r7}
|
|
8006bee: b087 sub sp, #28
|
|
8006bf0: af00 add r7, sp, #0
|
|
8006bf2: 60f8 str r0, [r7, #12]
|
|
8006bf4: 60b9 str r1, [r7, #8]
|
|
8006bf6: 607a str r2, [r7, #4]
|
|
8006bf8: 603b str r3, [r7, #0]
|
|
uint32_t i = 0;
|
|
8006bfa: 2300 movs r3, #0
|
|
8006bfc: 617b str r3, [r7, #20]
|
|
ETH_DMADescTypeDef *dmatxdesc;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8006bfe: 68fb ldr r3, [r7, #12]
|
|
8006c00: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
8006c04: 2b01 cmp r3, #1
|
|
8006c06: d101 bne.n 8006c0c <HAL_ETH_DMATxDescListInit+0x20>
|
|
8006c08: 2302 movs r3, #2
|
|
8006c0a: e052 b.n 8006cb2 <HAL_ETH_DMATxDescListInit+0xc6>
|
|
8006c0c: 68fb ldr r3, [r7, #12]
|
|
8006c0e: 2201 movs r2, #1
|
|
8006c10: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
8006c14: 68fb ldr r3, [r7, #12]
|
|
8006c16: 2202 movs r2, #2
|
|
8006c18: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
|
|
heth->TxDesc = DMATxDescTab;
|
|
8006c1c: 68fb ldr r3, [r7, #12]
|
|
8006c1e: 68ba ldr r2, [r7, #8]
|
|
8006c20: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Fill each DMATxDesc descriptor with the right values */
|
|
for(i=0; i < TxBuffCount; i++)
|
|
8006c22: 2300 movs r3, #0
|
|
8006c24: 617b str r3, [r7, #20]
|
|
8006c26: e030 b.n 8006c8a <HAL_ETH_DMATxDescListInit+0x9e>
|
|
{
|
|
/* Get the pointer on the ith member of the Tx Desc list */
|
|
dmatxdesc = DMATxDescTab + i;
|
|
8006c28: 697b ldr r3, [r7, #20]
|
|
8006c2a: 015b lsls r3, r3, #5
|
|
8006c2c: 68ba ldr r2, [r7, #8]
|
|
8006c2e: 4413 add r3, r2
|
|
8006c30: 613b str r3, [r7, #16]
|
|
|
|
/* Set Second Address Chained bit */
|
|
dmatxdesc->Status = ETH_DMATXDESC_TCH;
|
|
8006c32: 693b ldr r3, [r7, #16]
|
|
8006c34: f44f 1280 mov.w r2, #1048576 ; 0x100000
|
|
8006c38: 601a str r2, [r3, #0]
|
|
|
|
/* Set Buffer1 address pointer */
|
|
dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
|
|
8006c3a: 697b ldr r3, [r7, #20]
|
|
8006c3c: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
8006c40: fb02 f303 mul.w r3, r2, r3
|
|
8006c44: 687a ldr r2, [r7, #4]
|
|
8006c46: 4413 add r3, r2
|
|
8006c48: 461a mov r2, r3
|
|
8006c4a: 693b ldr r3, [r7, #16]
|
|
8006c4c: 609a str r2, [r3, #8]
|
|
|
|
if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
|
|
8006c4e: 68fb ldr r3, [r7, #12]
|
|
8006c50: 69db ldr r3, [r3, #28]
|
|
8006c52: 2b00 cmp r3, #0
|
|
8006c54: d105 bne.n 8006c62 <HAL_ETH_DMATxDescListInit+0x76>
|
|
{
|
|
/* Set the DMA Tx descriptors checksum insertion */
|
|
dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
|
|
8006c56: 693b ldr r3, [r7, #16]
|
|
8006c58: 681b ldr r3, [r3, #0]
|
|
8006c5a: f443 0240 orr.w r2, r3, #12582912 ; 0xc00000
|
|
8006c5e: 693b ldr r3, [r7, #16]
|
|
8006c60: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
if(i < (TxBuffCount-1))
|
|
8006c62: 683b ldr r3, [r7, #0]
|
|
8006c64: 3b01 subs r3, #1
|
|
8006c66: 697a ldr r2, [r7, #20]
|
|
8006c68: 429a cmp r2, r3
|
|
8006c6a: d208 bcs.n 8006c7e <HAL_ETH_DMATxDescListInit+0x92>
|
|
{
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
|
|
8006c6c: 697b ldr r3, [r7, #20]
|
|
8006c6e: 3301 adds r3, #1
|
|
8006c70: 015b lsls r3, r3, #5
|
|
8006c72: 68ba ldr r2, [r7, #8]
|
|
8006c74: 4413 add r3, r2
|
|
8006c76: 461a mov r2, r3
|
|
8006c78: 693b ldr r3, [r7, #16]
|
|
8006c7a: 60da str r2, [r3, #12]
|
|
8006c7c: e002 b.n 8006c84 <HAL_ETH_DMATxDescListInit+0x98>
|
|
}
|
|
else
|
|
{
|
|
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
|
dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
|
|
8006c7e: 68ba ldr r2, [r7, #8]
|
|
8006c80: 693b ldr r3, [r7, #16]
|
|
8006c82: 60da str r2, [r3, #12]
|
|
for(i=0; i < TxBuffCount; i++)
|
|
8006c84: 697b ldr r3, [r7, #20]
|
|
8006c86: 3301 adds r3, #1
|
|
8006c88: 617b str r3, [r7, #20]
|
|
8006c8a: 697a ldr r2, [r7, #20]
|
|
8006c8c: 683b ldr r3, [r7, #0]
|
|
8006c8e: 429a cmp r2, r3
|
|
8006c90: d3ca bcc.n 8006c28 <HAL_ETH_DMATxDescListInit+0x3c>
|
|
}
|
|
}
|
|
|
|
/* Set Transmit Descriptor List Address Register */
|
|
(heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
|
|
8006c92: 68fb ldr r3, [r7, #12]
|
|
8006c94: 6819 ldr r1, [r3, #0]
|
|
8006c96: 68ba ldr r2, [r7, #8]
|
|
8006c98: f241 0310 movw r3, #4112 ; 0x1010
|
|
8006c9c: 440b add r3, r1
|
|
8006c9e: 601a str r2, [r3, #0]
|
|
|
|
/* Set ETH HAL State to Ready */
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8006ca0: 68fb ldr r3, [r7, #12]
|
|
8006ca2: 2201 movs r2, #1
|
|
8006ca4: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006ca8: 68fb ldr r3, [r7, #12]
|
|
8006caa: 2200 movs r2, #0
|
|
8006cac: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006cb0: 2300 movs r3, #0
|
|
}
|
|
8006cb2: 4618 mov r0, r3
|
|
8006cb4: 371c adds r7, #28
|
|
8006cb6: 46bd mov sp, r7
|
|
8006cb8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006cbc: 4770 bx lr
|
|
|
|
08006cbe <HAL_ETH_DMARxDescListInit>:
|
|
* @param RxBuff Pointer to the first RxBuffer list
|
|
* @param RxBuffCount Number of the used Rx desc in the list
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
|
|
{
|
|
8006cbe: b480 push {r7}
|
|
8006cc0: b087 sub sp, #28
|
|
8006cc2: af00 add r7, sp, #0
|
|
8006cc4: 60f8 str r0, [r7, #12]
|
|
8006cc6: 60b9 str r1, [r7, #8]
|
|
8006cc8: 607a str r2, [r7, #4]
|
|
8006cca: 603b str r3, [r7, #0]
|
|
uint32_t i = 0;
|
|
8006ccc: 2300 movs r3, #0
|
|
8006cce: 617b str r3, [r7, #20]
|
|
ETH_DMADescTypeDef *DMARxDesc;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8006cd0: 68fb ldr r3, [r7, #12]
|
|
8006cd2: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
8006cd6: 2b01 cmp r3, #1
|
|
8006cd8: d101 bne.n 8006cde <HAL_ETH_DMARxDescListInit+0x20>
|
|
8006cda: 2302 movs r3, #2
|
|
8006cdc: e056 b.n 8006d8c <HAL_ETH_DMARxDescListInit+0xce>
|
|
8006cde: 68fb ldr r3, [r7, #12]
|
|
8006ce0: 2201 movs r2, #1
|
|
8006ce2: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
8006ce6: 68fb ldr r3, [r7, #12]
|
|
8006ce8: 2202 movs r2, #2
|
|
8006cea: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
|
|
heth->RxDesc = DMARxDescTab;
|
|
8006cee: 68fb ldr r3, [r7, #12]
|
|
8006cf0: 68ba ldr r2, [r7, #8]
|
|
8006cf2: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Fill each DMARxDesc descriptor with the right values */
|
|
for(i=0; i < RxBuffCount; i++)
|
|
8006cf4: 2300 movs r3, #0
|
|
8006cf6: 617b str r3, [r7, #20]
|
|
8006cf8: e034 b.n 8006d64 <HAL_ETH_DMARxDescListInit+0xa6>
|
|
{
|
|
/* Get the pointer on the ith member of the Rx Desc list */
|
|
DMARxDesc = DMARxDescTab+i;
|
|
8006cfa: 697b ldr r3, [r7, #20]
|
|
8006cfc: 015b lsls r3, r3, #5
|
|
8006cfe: 68ba ldr r2, [r7, #8]
|
|
8006d00: 4413 add r3, r2
|
|
8006d02: 613b str r3, [r7, #16]
|
|
|
|
/* Set Own bit of the Rx descriptor Status */
|
|
DMARxDesc->Status = ETH_DMARXDESC_OWN;
|
|
8006d04: 693b ldr r3, [r7, #16]
|
|
8006d06: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
|
|
8006d0a: 601a str r2, [r3, #0]
|
|
|
|
/* Set Buffer1 size and Second Address Chained bit */
|
|
DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
|
|
8006d0c: 693b ldr r3, [r7, #16]
|
|
8006d0e: f244 52f4 movw r2, #17908 ; 0x45f4
|
|
8006d12: 605a str r2, [r3, #4]
|
|
|
|
/* Set Buffer1 address pointer */
|
|
DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
|
|
8006d14: 697b ldr r3, [r7, #20]
|
|
8006d16: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
8006d1a: fb02 f303 mul.w r3, r2, r3
|
|
8006d1e: 687a ldr r2, [r7, #4]
|
|
8006d20: 4413 add r3, r2
|
|
8006d22: 461a mov r2, r3
|
|
8006d24: 693b ldr r3, [r7, #16]
|
|
8006d26: 609a str r2, [r3, #8]
|
|
|
|
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
|
|
8006d28: 68fb ldr r3, [r7, #12]
|
|
8006d2a: 699b ldr r3, [r3, #24]
|
|
8006d2c: 2b01 cmp r3, #1
|
|
8006d2e: d105 bne.n 8006d3c <HAL_ETH_DMARxDescListInit+0x7e>
|
|
{
|
|
/* Enable Ethernet DMA Rx Descriptor interrupt */
|
|
DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
|
|
8006d30: 693b ldr r3, [r7, #16]
|
|
8006d32: 685b ldr r3, [r3, #4]
|
|
8006d34: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000
|
|
8006d38: 693b ldr r3, [r7, #16]
|
|
8006d3a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
|
if(i < (RxBuffCount-1))
|
|
8006d3c: 683b ldr r3, [r7, #0]
|
|
8006d3e: 3b01 subs r3, #1
|
|
8006d40: 697a ldr r2, [r7, #20]
|
|
8006d42: 429a cmp r2, r3
|
|
8006d44: d208 bcs.n 8006d58 <HAL_ETH_DMARxDescListInit+0x9a>
|
|
{
|
|
/* Set next descriptor address register with next descriptor base address */
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
|
|
8006d46: 697b ldr r3, [r7, #20]
|
|
8006d48: 3301 adds r3, #1
|
|
8006d4a: 015b lsls r3, r3, #5
|
|
8006d4c: 68ba ldr r2, [r7, #8]
|
|
8006d4e: 4413 add r3, r2
|
|
8006d50: 461a mov r2, r3
|
|
8006d52: 693b ldr r3, [r7, #16]
|
|
8006d54: 60da str r2, [r3, #12]
|
|
8006d56: e002 b.n 8006d5e <HAL_ETH_DMARxDescListInit+0xa0>
|
|
}
|
|
else
|
|
{
|
|
/* For last descriptor, set next descriptor address register equal to the first descriptor base address */
|
|
DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
|
|
8006d58: 68ba ldr r2, [r7, #8]
|
|
8006d5a: 693b ldr r3, [r7, #16]
|
|
8006d5c: 60da str r2, [r3, #12]
|
|
for(i=0; i < RxBuffCount; i++)
|
|
8006d5e: 697b ldr r3, [r7, #20]
|
|
8006d60: 3301 adds r3, #1
|
|
8006d62: 617b str r3, [r7, #20]
|
|
8006d64: 697a ldr r2, [r7, #20]
|
|
8006d66: 683b ldr r3, [r7, #0]
|
|
8006d68: 429a cmp r2, r3
|
|
8006d6a: d3c6 bcc.n 8006cfa <HAL_ETH_DMARxDescListInit+0x3c>
|
|
}
|
|
}
|
|
|
|
/* Set Receive Descriptor List Address Register */
|
|
(heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
|
|
8006d6c: 68fb ldr r3, [r7, #12]
|
|
8006d6e: 6819 ldr r1, [r3, #0]
|
|
8006d70: 68ba ldr r2, [r7, #8]
|
|
8006d72: f241 030c movw r3, #4108 ; 0x100c
|
|
8006d76: 440b add r3, r1
|
|
8006d78: 601a str r2, [r3, #0]
|
|
|
|
/* Set ETH HAL State to Ready */
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8006d7a: 68fb ldr r3, [r7, #12]
|
|
8006d7c: 2201 movs r2, #1
|
|
8006d7e: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006d82: 68fb ldr r3, [r7, #12]
|
|
8006d84: 2200 movs r2, #0
|
|
8006d86: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006d8a: 2300 movs r3, #0
|
|
}
|
|
8006d8c: 4618 mov r0, r3
|
|
8006d8e: 371c adds r7, #28
|
|
8006d90: 46bd mov sp, r7
|
|
8006d92: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d96: 4770 bx lr
|
|
|
|
08006d98 <HAL_ETH_TransmitFrame>:
|
|
* the configuration information for ETHERNET module
|
|
* @param FrameLength Amount of data to be sent
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
|
|
{
|
|
8006d98: b480 push {r7}
|
|
8006d9a: b087 sub sp, #28
|
|
8006d9c: af00 add r7, sp, #0
|
|
8006d9e: 6078 str r0, [r7, #4]
|
|
8006da0: 6039 str r1, [r7, #0]
|
|
uint32_t bufcount = 0, size = 0, i = 0;
|
|
8006da2: 2300 movs r3, #0
|
|
8006da4: 617b str r3, [r7, #20]
|
|
8006da6: 2300 movs r3, #0
|
|
8006da8: 60fb str r3, [r7, #12]
|
|
8006daa: 2300 movs r3, #0
|
|
8006dac: 613b str r3, [r7, #16]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8006dae: 687b ldr r3, [r7, #4]
|
|
8006db0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
8006db4: 2b01 cmp r3, #1
|
|
8006db6: d101 bne.n 8006dbc <HAL_ETH_TransmitFrame+0x24>
|
|
8006db8: 2302 movs r3, #2
|
|
8006dba: e0cd b.n 8006f58 <HAL_ETH_TransmitFrame+0x1c0>
|
|
8006dbc: 687b ldr r3, [r7, #4]
|
|
8006dbe: 2201 movs r2, #1
|
|
8006dc0: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
8006dc4: 687b ldr r3, [r7, #4]
|
|
8006dc6: 2202 movs r2, #2
|
|
8006dc8: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
if (FrameLength == 0)
|
|
8006dcc: 683b ldr r3, [r7, #0]
|
|
8006dce: 2b00 cmp r3, #0
|
|
8006dd0: d109 bne.n 8006de6 <HAL_ETH_TransmitFrame+0x4e>
|
|
{
|
|
/* Set ETH HAL state to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006dd2: 687b ldr r3, [r7, #4]
|
|
8006dd4: 2201 movs r2, #1
|
|
8006dd6: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006dda: 687b ldr r3, [r7, #4]
|
|
8006ddc: 2200 movs r2, #0
|
|
8006dde: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_ERROR;
|
|
8006de2: 2301 movs r3, #1
|
|
8006de4: e0b8 b.n 8006f58 <HAL_ETH_TransmitFrame+0x1c0>
|
|
}
|
|
|
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
|
if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
|
8006de6: 687b ldr r3, [r7, #4]
|
|
8006de8: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006dea: 681b ldr r3, [r3, #0]
|
|
8006dec: 2b00 cmp r3, #0
|
|
8006dee: da09 bge.n 8006e04 <HAL_ETH_TransmitFrame+0x6c>
|
|
{
|
|
/* OWN bit set */
|
|
heth->State = HAL_ETH_STATE_BUSY_TX;
|
|
8006df0: 687b ldr r3, [r7, #4]
|
|
8006df2: 2212 movs r2, #18
|
|
8006df4: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006df8: 687b ldr r3, [r7, #4]
|
|
8006dfa: 2200 movs r2, #0
|
|
8006dfc: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_ERROR;
|
|
8006e00: 2301 movs r3, #1
|
|
8006e02: e0a9 b.n 8006f58 <HAL_ETH_TransmitFrame+0x1c0>
|
|
}
|
|
|
|
/* Get the number of needed Tx buffers for the current frame */
|
|
if (FrameLength > ETH_TX_BUF_SIZE)
|
|
8006e04: 683b ldr r3, [r7, #0]
|
|
8006e06: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
8006e0a: 4293 cmp r3, r2
|
|
8006e0c: d915 bls.n 8006e3a <HAL_ETH_TransmitFrame+0xa2>
|
|
{
|
|
bufcount = FrameLength/ETH_TX_BUF_SIZE;
|
|
8006e0e: 683b ldr r3, [r7, #0]
|
|
8006e10: 4a54 ldr r2, [pc, #336] ; (8006f64 <HAL_ETH_TransmitFrame+0x1cc>)
|
|
8006e12: fba2 2303 umull r2, r3, r2, r3
|
|
8006e16: 0a9b lsrs r3, r3, #10
|
|
8006e18: 617b str r3, [r7, #20]
|
|
if (FrameLength % ETH_TX_BUF_SIZE)
|
|
8006e1a: 683a ldr r2, [r7, #0]
|
|
8006e1c: 4b51 ldr r3, [pc, #324] ; (8006f64 <HAL_ETH_TransmitFrame+0x1cc>)
|
|
8006e1e: fba3 1302 umull r1, r3, r3, r2
|
|
8006e22: 0a9b lsrs r3, r3, #10
|
|
8006e24: f240 51f4 movw r1, #1524 ; 0x5f4
|
|
8006e28: fb01 f303 mul.w r3, r1, r3
|
|
8006e2c: 1ad3 subs r3, r2, r3
|
|
8006e2e: 2b00 cmp r3, #0
|
|
8006e30: d005 beq.n 8006e3e <HAL_ETH_TransmitFrame+0xa6>
|
|
{
|
|
bufcount++;
|
|
8006e32: 697b ldr r3, [r7, #20]
|
|
8006e34: 3301 adds r3, #1
|
|
8006e36: 617b str r3, [r7, #20]
|
|
8006e38: e001 b.n 8006e3e <HAL_ETH_TransmitFrame+0xa6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
bufcount = 1;
|
|
8006e3a: 2301 movs r3, #1
|
|
8006e3c: 617b str r3, [r7, #20]
|
|
}
|
|
if (bufcount == 1)
|
|
8006e3e: 697b ldr r3, [r7, #20]
|
|
8006e40: 2b01 cmp r3, #1
|
|
8006e42: d11c bne.n 8006e7e <HAL_ETH_TransmitFrame+0xe6>
|
|
{
|
|
/* Set LAST and FIRST segment */
|
|
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
|
|
8006e44: 687b ldr r3, [r7, #4]
|
|
8006e46: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e48: 681a ldr r2, [r3, #0]
|
|
8006e4a: 687b ldr r3, [r7, #4]
|
|
8006e4c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e4e: f042 5240 orr.w r2, r2, #805306368 ; 0x30000000
|
|
8006e52: 601a str r2, [r3, #0]
|
|
/* Set frame size */
|
|
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
|
|
8006e54: 687b ldr r3, [r7, #4]
|
|
8006e56: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e58: 683a ldr r2, [r7, #0]
|
|
8006e5a: f3c2 020c ubfx r2, r2, #0, #13
|
|
8006e5e: 605a str r2, [r3, #4]
|
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
|
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
|
|
8006e60: 687b ldr r3, [r7, #4]
|
|
8006e62: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e64: 681a ldr r2, [r3, #0]
|
|
8006e66: 687b ldr r3, [r7, #4]
|
|
8006e68: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e6a: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
|
8006e6e: 601a str r2, [r3, #0]
|
|
/* Point to next descriptor */
|
|
heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
|
|
8006e70: 687b ldr r3, [r7, #4]
|
|
8006e72: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e74: 68db ldr r3, [r3, #12]
|
|
8006e76: 461a mov r2, r3
|
|
8006e78: 687b ldr r3, [r7, #4]
|
|
8006e7a: 62da str r2, [r3, #44] ; 0x2c
|
|
8006e7c: e04b b.n 8006f16 <HAL_ETH_TransmitFrame+0x17e>
|
|
}
|
|
else
|
|
{
|
|
for (i=0; i< bufcount; i++)
|
|
8006e7e: 2300 movs r3, #0
|
|
8006e80: 613b str r3, [r7, #16]
|
|
8006e82: e044 b.n 8006f0e <HAL_ETH_TransmitFrame+0x176>
|
|
{
|
|
/* Clear FIRST and LAST segment bits */
|
|
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
|
|
8006e84: 687b ldr r3, [r7, #4]
|
|
8006e86: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e88: 681a ldr r2, [r3, #0]
|
|
8006e8a: 687b ldr r3, [r7, #4]
|
|
8006e8c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e8e: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
|
|
8006e92: 601a str r2, [r3, #0]
|
|
|
|
if (i == 0)
|
|
8006e94: 693b ldr r3, [r7, #16]
|
|
8006e96: 2b00 cmp r3, #0
|
|
8006e98: d107 bne.n 8006eaa <HAL_ETH_TransmitFrame+0x112>
|
|
{
|
|
/* Setting the first segment bit */
|
|
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
|
|
8006e9a: 687b ldr r3, [r7, #4]
|
|
8006e9c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006e9e: 681a ldr r2, [r3, #0]
|
|
8006ea0: 687b ldr r3, [r7, #4]
|
|
8006ea2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ea4: f042 5280 orr.w r2, r2, #268435456 ; 0x10000000
|
|
8006ea8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Program size */
|
|
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
|
|
8006eaa: 687b ldr r3, [r7, #4]
|
|
8006eac: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006eae: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
8006eb2: 605a str r2, [r3, #4]
|
|
|
|
if (i == (bufcount-1))
|
|
8006eb4: 697b ldr r3, [r7, #20]
|
|
8006eb6: 3b01 subs r3, #1
|
|
8006eb8: 693a ldr r2, [r7, #16]
|
|
8006eba: 429a cmp r2, r3
|
|
8006ebc: d116 bne.n 8006eec <HAL_ETH_TransmitFrame+0x154>
|
|
{
|
|
/* Setting the last segment bit */
|
|
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
|
|
8006ebe: 687b ldr r3, [r7, #4]
|
|
8006ec0: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ec2: 681a ldr r2, [r3, #0]
|
|
8006ec4: 687b ldr r3, [r7, #4]
|
|
8006ec6: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ec8: f042 5200 orr.w r2, r2, #536870912 ; 0x20000000
|
|
8006ecc: 601a str r2, [r3, #0]
|
|
size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
|
|
8006ece: 697b ldr r3, [r7, #20]
|
|
8006ed0: 4a25 ldr r2, [pc, #148] ; (8006f68 <HAL_ETH_TransmitFrame+0x1d0>)
|
|
8006ed2: fb02 f203 mul.w r2, r2, r3
|
|
8006ed6: 683b ldr r3, [r7, #0]
|
|
8006ed8: 4413 add r3, r2
|
|
8006eda: f203 53f4 addw r3, r3, #1524 ; 0x5f4
|
|
8006ede: 60fb str r3, [r7, #12]
|
|
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
|
|
8006ee0: 687b ldr r3, [r7, #4]
|
|
8006ee2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ee4: 68fa ldr r2, [r7, #12]
|
|
8006ee6: f3c2 020c ubfx r2, r2, #0, #13
|
|
8006eea: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
|
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
|
|
8006eec: 687b ldr r3, [r7, #4]
|
|
8006eee: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ef0: 681a ldr r2, [r3, #0]
|
|
8006ef2: 687b ldr r3, [r7, #4]
|
|
8006ef4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006ef6: f042 4200 orr.w r2, r2, #2147483648 ; 0x80000000
|
|
8006efa: 601a str r2, [r3, #0]
|
|
/* point to next descriptor */
|
|
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
|
|
8006efc: 687b ldr r3, [r7, #4]
|
|
8006efe: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8006f00: 68db ldr r3, [r3, #12]
|
|
8006f02: 461a mov r2, r3
|
|
8006f04: 687b ldr r3, [r7, #4]
|
|
8006f06: 62da str r2, [r3, #44] ; 0x2c
|
|
for (i=0; i< bufcount; i++)
|
|
8006f08: 693b ldr r3, [r7, #16]
|
|
8006f0a: 3301 adds r3, #1
|
|
8006f0c: 613b str r3, [r7, #16]
|
|
8006f0e: 693a ldr r2, [r7, #16]
|
|
8006f10: 697b ldr r3, [r7, #20]
|
|
8006f12: 429a cmp r2, r3
|
|
8006f14: d3b6 bcc.n 8006e84 <HAL_ETH_TransmitFrame+0xec>
|
|
}
|
|
}
|
|
|
|
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
|
|
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
|
|
8006f16: 687b ldr r3, [r7, #4]
|
|
8006f18: 681a ldr r2, [r3, #0]
|
|
8006f1a: f241 0314 movw r3, #4116 ; 0x1014
|
|
8006f1e: 4413 add r3, r2
|
|
8006f20: 681b ldr r3, [r3, #0]
|
|
8006f22: f003 0304 and.w r3, r3, #4
|
|
8006f26: 2b00 cmp r3, #0
|
|
8006f28: d00d beq.n 8006f46 <HAL_ETH_TransmitFrame+0x1ae>
|
|
{
|
|
/* Clear TBUS ETHERNET DMA flag */
|
|
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
|
|
8006f2a: 687b ldr r3, [r7, #4]
|
|
8006f2c: 681a ldr r2, [r3, #0]
|
|
8006f2e: f241 0314 movw r3, #4116 ; 0x1014
|
|
8006f32: 4413 add r3, r2
|
|
8006f34: 2204 movs r2, #4
|
|
8006f36: 601a str r2, [r3, #0]
|
|
/* Resume DMA transmission*/
|
|
(heth->Instance)->DMATPDR = 0;
|
|
8006f38: 687b ldr r3, [r7, #4]
|
|
8006f3a: 681a ldr r2, [r3, #0]
|
|
8006f3c: f241 0304 movw r3, #4100 ; 0x1004
|
|
8006f40: 4413 add r3, r2
|
|
8006f42: 2200 movs r2, #0
|
|
8006f44: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set ETH HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8006f46: 687b ldr r3, [r7, #4]
|
|
8006f48: 2201 movs r2, #1
|
|
8006f4a: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8006f4e: 687b ldr r3, [r7, #4]
|
|
8006f50: 2200 movs r2, #0
|
|
8006f52: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8006f56: 2300 movs r3, #0
|
|
}
|
|
8006f58: 4618 mov r0, r3
|
|
8006f5a: 371c adds r7, #28
|
|
8006f5c: 46bd mov sp, r7
|
|
8006f5e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f62: 4770 bx lr
|
|
8006f64: ac02b00b .word 0xac02b00b
|
|
8006f68: fffffa0c .word 0xfffffa0c
|
|
|
|
08006f6c <HAL_ETH_GetReceivedFrame_IT>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
|
|
{
|
|
8006f6c: b480 push {r7}
|
|
8006f6e: b085 sub sp, #20
|
|
8006f70: af00 add r7, sp, #0
|
|
8006f72: 6078 str r0, [r7, #4]
|
|
uint32_t descriptorscancounter = 0;
|
|
8006f74: 2300 movs r3, #0
|
|
8006f76: 60fb str r3, [r7, #12]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8006f78: 687b ldr r3, [r7, #4]
|
|
8006f7a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
8006f7e: 2b01 cmp r3, #1
|
|
8006f80: d101 bne.n 8006f86 <HAL_ETH_GetReceivedFrame_IT+0x1a>
|
|
8006f82: 2302 movs r3, #2
|
|
8006f84: e074 b.n 8007070 <HAL_ETH_GetReceivedFrame_IT+0x104>
|
|
8006f86: 687b ldr r3, [r7, #4]
|
|
8006f88: 2201 movs r2, #1
|
|
8006f8a: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set ETH HAL State to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
8006f8e: 687b ldr r3, [r7, #4]
|
|
8006f90: 2202 movs r2, #2
|
|
8006f92: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Scan descriptors owned by CPU */
|
|
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
|
|
8006f96: e05a b.n 800704e <HAL_ETH_GetReceivedFrame_IT+0xe2>
|
|
{
|
|
/* Just for security */
|
|
descriptorscancounter++;
|
|
8006f98: 68fb ldr r3, [r7, #12]
|
|
8006f9a: 3301 adds r3, #1
|
|
8006f9c: 60fb str r3, [r7, #12]
|
|
|
|
/* Check if first segment in frame */
|
|
/* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
|
|
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
|
|
8006f9e: 687b ldr r3, [r7, #4]
|
|
8006fa0: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8006fa2: 681b ldr r3, [r3, #0]
|
|
8006fa4: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8006fa8: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
8006fac: d10d bne.n 8006fca <HAL_ETH_GetReceivedFrame_IT+0x5e>
|
|
{
|
|
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
|
|
8006fae: 687b ldr r3, [r7, #4]
|
|
8006fb0: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
8006fb2: 687b ldr r3, [r7, #4]
|
|
8006fb4: 631a str r2, [r3, #48] ; 0x30
|
|
heth->RxFrameInfos.SegCount = 1;
|
|
8006fb6: 687b ldr r3, [r7, #4]
|
|
8006fb8: 2201 movs r2, #1
|
|
8006fba: 639a str r2, [r3, #56] ; 0x38
|
|
/* Point to next descriptor */
|
|
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
|
8006fbc: 687b ldr r3, [r7, #4]
|
|
8006fbe: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8006fc0: 68db ldr r3, [r3, #12]
|
|
8006fc2: 461a mov r2, r3
|
|
8006fc4: 687b ldr r3, [r7, #4]
|
|
8006fc6: 629a str r2, [r3, #40] ; 0x28
|
|
8006fc8: e041 b.n 800704e <HAL_ETH_GetReceivedFrame_IT+0xe2>
|
|
}
|
|
/* Check if intermediate segment */
|
|
/* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
|
|
else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
|
|
8006fca: 687b ldr r3, [r7, #4]
|
|
8006fcc: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8006fce: 681b ldr r3, [r3, #0]
|
|
8006fd0: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8006fd4: 2b00 cmp r3, #0
|
|
8006fd6: d10b bne.n 8006ff0 <HAL_ETH_GetReceivedFrame_IT+0x84>
|
|
{
|
|
/* Increment segment count */
|
|
(heth->RxFrameInfos.SegCount)++;
|
|
8006fd8: 687b ldr r3, [r7, #4]
|
|
8006fda: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8006fdc: 1c5a adds r2, r3, #1
|
|
8006fde: 687b ldr r3, [r7, #4]
|
|
8006fe0: 639a str r2, [r3, #56] ; 0x38
|
|
/* Point to next descriptor */
|
|
heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
|
|
8006fe2: 687b ldr r3, [r7, #4]
|
|
8006fe4: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8006fe6: 68db ldr r3, [r3, #12]
|
|
8006fe8: 461a mov r2, r3
|
|
8006fea: 687b ldr r3, [r7, #4]
|
|
8006fec: 629a str r2, [r3, #40] ; 0x28
|
|
8006fee: e02e b.n 800704e <HAL_ETH_GetReceivedFrame_IT+0xe2>
|
|
}
|
|
/* Should be last segment */
|
|
else
|
|
{
|
|
/* Last segment */
|
|
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
|
|
8006ff0: 687b ldr r3, [r7, #4]
|
|
8006ff2: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
8006ff4: 687b ldr r3, [r7, #4]
|
|
8006ff6: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Increment segment count */
|
|
(heth->RxFrameInfos.SegCount)++;
|
|
8006ff8: 687b ldr r3, [r7, #4]
|
|
8006ffa: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8006ffc: 1c5a adds r2, r3, #1
|
|
8006ffe: 687b ldr r3, [r7, #4]
|
|
8007000: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* Check if last segment is first segment: one segment contains the frame */
|
|
if ((heth->RxFrameInfos.SegCount) == 1)
|
|
8007002: 687b ldr r3, [r7, #4]
|
|
8007004: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8007006: 2b01 cmp r3, #1
|
|
8007008: d103 bne.n 8007012 <HAL_ETH_GetReceivedFrame_IT+0xa6>
|
|
{
|
|
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
|
|
800700a: 687b ldr r3, [r7, #4]
|
|
800700c: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
800700e: 687b ldr r3, [r7, #4]
|
|
8007010: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
|
|
heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
|
|
8007012: 687b ldr r3, [r7, #4]
|
|
8007014: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8007016: 681b ldr r3, [r3, #0]
|
|
8007018: 0c1b lsrs r3, r3, #16
|
|
800701a: f3c3 030d ubfx r3, r3, #0, #14
|
|
800701e: 1f1a subs r2, r3, #4
|
|
8007020: 687b ldr r3, [r7, #4]
|
|
8007022: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Get the address of the buffer start address */
|
|
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
|
|
8007024: 687b ldr r3, [r7, #4]
|
|
8007026: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8007028: 689a ldr r2, [r3, #8]
|
|
800702a: 687b ldr r3, [r7, #4]
|
|
800702c: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Point to next descriptor */
|
|
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
|
|
800702e: 687b ldr r3, [r7, #4]
|
|
8007030: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8007032: 68db ldr r3, [r3, #12]
|
|
8007034: 461a mov r2, r3
|
|
8007036: 687b ldr r3, [r7, #4]
|
|
8007038: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Set HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
800703a: 687b ldr r3, [r7, #4]
|
|
800703c: 2201 movs r2, #1
|
|
800703e: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8007042: 687b ldr r3, [r7, #4]
|
|
8007044: 2200 movs r2, #0
|
|
8007046: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800704a: 2300 movs r3, #0
|
|
800704c: e010 b.n 8007070 <HAL_ETH_GetReceivedFrame_IT+0x104>
|
|
while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
|
|
800704e: 687b ldr r3, [r7, #4]
|
|
8007050: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8007052: 681b ldr r3, [r3, #0]
|
|
8007054: 2b00 cmp r3, #0
|
|
8007056: db02 blt.n 800705e <HAL_ETH_GetReceivedFrame_IT+0xf2>
|
|
8007058: 68fb ldr r3, [r7, #12]
|
|
800705a: 2b03 cmp r3, #3
|
|
800705c: d99c bls.n 8006f98 <HAL_ETH_GetReceivedFrame_IT+0x2c>
|
|
}
|
|
}
|
|
|
|
/* Set HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
800705e: 687b ldr r3, [r7, #4]
|
|
8007060: 2201 movs r2, #1
|
|
8007062: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8007066: 687b ldr r3, [r7, #4]
|
|
8007068: 2200 movs r2, #0
|
|
800706a: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_ERROR;
|
|
800706e: 2301 movs r3, #1
|
|
}
|
|
8007070: 4618 mov r0, r3
|
|
8007072: 3714 adds r7, #20
|
|
8007074: 46bd mov sp, r7
|
|
8007076: f85d 7b04 ldr.w r7, [sp], #4
|
|
800707a: 4770 bx lr
|
|
|
|
0800707c <HAL_ETH_IRQHandler>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
|
|
{
|
|
800707c: b580 push {r7, lr}
|
|
800707e: b082 sub sp, #8
|
|
8007080: af00 add r7, sp, #0
|
|
8007082: 6078 str r0, [r7, #4]
|
|
/* Frame received */
|
|
if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
|
|
8007084: 687b ldr r3, [r7, #4]
|
|
8007086: 681a ldr r2, [r3, #0]
|
|
8007088: f241 0314 movw r3, #4116 ; 0x1014
|
|
800708c: 4413 add r3, r2
|
|
800708e: 681b ldr r3, [r3, #0]
|
|
8007090: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
8007094: 2b40 cmp r3, #64 ; 0x40
|
|
8007096: d112 bne.n 80070be <HAL_ETH_IRQHandler+0x42>
|
|
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Receive complete callback*/
|
|
heth->RxCpltCallback(heth);
|
|
#else
|
|
/* Receive complete callback */
|
|
HAL_ETH_RxCpltCallback(heth);
|
|
8007098: 6878 ldr r0, [r7, #4]
|
|
800709a: f005 ff3d bl 800cf18 <HAL_ETH_RxCpltCallback>
|
|
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
|
|
|
/* Clear the Eth DMA Rx IT pending bits */
|
|
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
|
|
800709e: 687b ldr r3, [r7, #4]
|
|
80070a0: 681a ldr r2, [r3, #0]
|
|
80070a2: f241 0314 movw r3, #4116 ; 0x1014
|
|
80070a6: 4413 add r3, r2
|
|
80070a8: 2240 movs r2, #64 ; 0x40
|
|
80070aa: 601a str r2, [r3, #0]
|
|
|
|
/* Set HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
80070ac: 687b ldr r3, [r7, #4]
|
|
80070ae: 2201 movs r2, #1
|
|
80070b0: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
80070b4: 687b ldr r3, [r7, #4]
|
|
80070b6: 2200 movs r2, #0
|
|
80070b8: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
80070bc: e01b b.n 80070f6 <HAL_ETH_IRQHandler+0x7a>
|
|
|
|
}
|
|
/* Frame transmitted */
|
|
else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
|
|
80070be: 687b ldr r3, [r7, #4]
|
|
80070c0: 681a ldr r2, [r3, #0]
|
|
80070c2: f241 0314 movw r3, #4116 ; 0x1014
|
|
80070c6: 4413 add r3, r2
|
|
80070c8: 681b ldr r3, [r3, #0]
|
|
80070ca: f003 0301 and.w r3, r3, #1
|
|
80070ce: 2b01 cmp r3, #1
|
|
80070d0: d111 bne.n 80070f6 <HAL_ETH_IRQHandler+0x7a>
|
|
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
|
/* Call resgistered Transfer complete callback*/
|
|
heth->TxCpltCallback(heth);
|
|
#else
|
|
/* Transfer complete callback */
|
|
HAL_ETH_TxCpltCallback(heth);
|
|
80070d2: 6878 ldr r0, [r7, #4]
|
|
80070d4: f000 f839 bl 800714a <HAL_ETH_TxCpltCallback>
|
|
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
|
|
|
/* Clear the Eth DMA Tx IT pending bits */
|
|
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
|
|
80070d8: 687b ldr r3, [r7, #4]
|
|
80070da: 681a ldr r2, [r3, #0]
|
|
80070dc: f241 0314 movw r3, #4116 ; 0x1014
|
|
80070e0: 4413 add r3, r2
|
|
80070e2: 2201 movs r2, #1
|
|
80070e4: 601a str r2, [r3, #0]
|
|
|
|
/* Set HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
80070e6: 687b ldr r3, [r7, #4]
|
|
80070e8: 2201 movs r2, #1
|
|
80070ea: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
80070ee: 687b ldr r3, [r7, #4]
|
|
80070f0: 2200 movs r2, #0
|
|
80070f2: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
|
|
/* Clear the interrupt flags */
|
|
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
|
|
80070f6: 687b ldr r3, [r7, #4]
|
|
80070f8: 681a ldr r2, [r3, #0]
|
|
80070fa: f241 0314 movw r3, #4116 ; 0x1014
|
|
80070fe: 4413 add r3, r2
|
|
8007100: f44f 3280 mov.w r2, #65536 ; 0x10000
|
|
8007104: 601a str r2, [r3, #0]
|
|
|
|
/* ETH DMA Error */
|
|
if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
|
|
8007106: 687b ldr r3, [r7, #4]
|
|
8007108: 681a ldr r2, [r3, #0]
|
|
800710a: f241 0314 movw r3, #4116 ; 0x1014
|
|
800710e: 4413 add r3, r2
|
|
8007110: 681b ldr r3, [r3, #0]
|
|
8007112: f403 4300 and.w r3, r3, #32768 ; 0x8000
|
|
8007116: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
|
800711a: d112 bne.n 8007142 <HAL_ETH_IRQHandler+0xc6>
|
|
{
|
|
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
|
|
heth->DMAErrorCallback(heth);
|
|
#else
|
|
/* Ethernet Error callback */
|
|
HAL_ETH_ErrorCallback(heth);
|
|
800711c: 6878 ldr r0, [r7, #4]
|
|
800711e: f000 f81e bl 800715e <HAL_ETH_ErrorCallback>
|
|
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
|
|
|
|
/* Clear the interrupt flags */
|
|
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
|
|
8007122: 687b ldr r3, [r7, #4]
|
|
8007124: 681a ldr r2, [r3, #0]
|
|
8007126: f241 0314 movw r3, #4116 ; 0x1014
|
|
800712a: 4413 add r3, r2
|
|
800712c: f44f 4200 mov.w r2, #32768 ; 0x8000
|
|
8007130: 601a str r2, [r3, #0]
|
|
|
|
/* Set HAL State to Ready */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8007132: 687b ldr r3, [r7, #4]
|
|
8007134: 2201 movs r2, #1
|
|
8007136: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
800713a: 687b ldr r3, [r7, #4]
|
|
800713c: 2200 movs r2, #0
|
|
800713e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
}
|
|
8007142: bf00 nop
|
|
8007144: 3708 adds r7, #8
|
|
8007146: 46bd mov sp, r7
|
|
8007148: bd80 pop {r7, pc}
|
|
|
|
0800714a <HAL_ETH_TxCpltCallback>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
|
|
{
|
|
800714a: b480 push {r7}
|
|
800714c: b083 sub sp, #12
|
|
800714e: af00 add r7, sp, #0
|
|
8007150: 6078 str r0, [r7, #4]
|
|
UNUSED(heth);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_ETH_TxCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007152: bf00 nop
|
|
8007154: 370c adds r7, #12
|
|
8007156: 46bd mov sp, r7
|
|
8007158: f85d 7b04 ldr.w r7, [sp], #4
|
|
800715c: 4770 bx lr
|
|
|
|
0800715e <HAL_ETH_ErrorCallback>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
|
{
|
|
800715e: b480 push {r7}
|
|
8007160: b083 sub sp, #12
|
|
8007162: af00 add r7, sp, #0
|
|
8007164: 6078 str r0, [r7, #4]
|
|
UNUSED(heth);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_ETH_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8007166: bf00 nop
|
|
8007168: 370c adds r7, #12
|
|
800716a: 46bd mov sp, r7
|
|
800716c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007170: 4770 bx lr
|
|
|
|
08007172 <HAL_ETH_ReadPHYRegister>:
|
|
* More PHY register could be read depending on the used PHY
|
|
* @param RegValue PHY register value
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
|
|
{
|
|
8007172: b580 push {r7, lr}
|
|
8007174: b086 sub sp, #24
|
|
8007176: af00 add r7, sp, #0
|
|
8007178: 60f8 str r0, [r7, #12]
|
|
800717a: 460b mov r3, r1
|
|
800717c: 607a str r2, [r7, #4]
|
|
800717e: 817b strh r3, [r7, #10]
|
|
uint32_t tmpreg = 0;
|
|
8007180: 2300 movs r3, #0
|
|
8007182: 617b str r3, [r7, #20]
|
|
uint32_t tickstart = 0;
|
|
8007184: 2300 movs r3, #0
|
|
8007186: 613b str r3, [r7, #16]
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
|
|
|
|
/* Check the ETH peripheral state */
|
|
if(heth->State == HAL_ETH_STATE_BUSY_RD)
|
|
8007188: 68fb ldr r3, [r7, #12]
|
|
800718a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800718e: b2db uxtb r3, r3
|
|
8007190: 2b82 cmp r3, #130 ; 0x82
|
|
8007192: d101 bne.n 8007198 <HAL_ETH_ReadPHYRegister+0x26>
|
|
{
|
|
return HAL_BUSY;
|
|
8007194: 2302 movs r3, #2
|
|
8007196: e050 b.n 800723a <HAL_ETH_ReadPHYRegister+0xc8>
|
|
}
|
|
/* Set ETH HAL State to BUSY_RD */
|
|
heth->State = HAL_ETH_STATE_BUSY_RD;
|
|
8007198: 68fb ldr r3, [r7, #12]
|
|
800719a: 2282 movs r2, #130 ; 0x82
|
|
800719c: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
tmpreg = heth->Instance->MACMIIAR;
|
|
80071a0: 68fb ldr r3, [r7, #12]
|
|
80071a2: 681b ldr r3, [r3, #0]
|
|
80071a4: 691b ldr r3, [r3, #16]
|
|
80071a6: 617b str r3, [r7, #20]
|
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
|
|
80071a8: 697b ldr r3, [r7, #20]
|
|
80071aa: f003 031c and.w r3, r3, #28
|
|
80071ae: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the MII address register value */
|
|
tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
80071b0: 68fb ldr r3, [r7, #12]
|
|
80071b2: 8a1b ldrh r3, [r3, #16]
|
|
80071b4: 02db lsls r3, r3, #11
|
|
80071b6: b29b uxth r3, r3
|
|
80071b8: 697a ldr r2, [r7, #20]
|
|
80071ba: 4313 orrs r3, r2
|
|
80071bc: 617b str r3, [r7, #20]
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
80071be: 897b ldrh r3, [r7, #10]
|
|
80071c0: 019b lsls r3, r3, #6
|
|
80071c2: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
|
|
80071c6: 697a ldr r2, [r7, #20]
|
|
80071c8: 4313 orrs r3, r2
|
|
80071ca: 617b str r3, [r7, #20]
|
|
tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
|
|
80071cc: 697b ldr r3, [r7, #20]
|
|
80071ce: f023 0302 bic.w r3, r3, #2
|
|
80071d2: 617b str r3, [r7, #20]
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
80071d4: 697b ldr r3, [r7, #20]
|
|
80071d6: f043 0301 orr.w r3, r3, #1
|
|
80071da: 617b str r3, [r7, #20]
|
|
|
|
/* Write the result value into the MII Address register */
|
|
heth->Instance->MACMIIAR = tmpreg;
|
|
80071dc: 68fb ldr r3, [r7, #12]
|
|
80071de: 681b ldr r3, [r3, #0]
|
|
80071e0: 697a ldr r2, [r7, #20]
|
|
80071e2: 611a str r2, [r3, #16]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80071e4: f7fe f87c bl 80052e0 <HAL_GetTick>
|
|
80071e8: 6138 str r0, [r7, #16]
|
|
|
|
/* Check for the Busy flag */
|
|
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
|
80071ea: e015 b.n 8007218 <HAL_ETH_ReadPHYRegister+0xa6>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
|
|
80071ec: f7fe f878 bl 80052e0 <HAL_GetTick>
|
|
80071f0: 4602 mov r2, r0
|
|
80071f2: 693b ldr r3, [r7, #16]
|
|
80071f4: 1ad3 subs r3, r2, r3
|
|
80071f6: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
80071fa: d309 bcc.n 8007210 <HAL_ETH_ReadPHYRegister+0x9e>
|
|
{
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
80071fc: 68fb ldr r3, [r7, #12]
|
|
80071fe: 2201 movs r2, #1
|
|
8007200: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
8007204: 68fb ldr r3, [r7, #12]
|
|
8007206: 2200 movs r2, #0
|
|
8007208: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_TIMEOUT;
|
|
800720c: 2303 movs r3, #3
|
|
800720e: e014 b.n 800723a <HAL_ETH_ReadPHYRegister+0xc8>
|
|
}
|
|
|
|
tmpreg = heth->Instance->MACMIIAR;
|
|
8007210: 68fb ldr r3, [r7, #12]
|
|
8007212: 681b ldr r3, [r3, #0]
|
|
8007214: 691b ldr r3, [r3, #16]
|
|
8007216: 617b str r3, [r7, #20]
|
|
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
|
8007218: 697b ldr r3, [r7, #20]
|
|
800721a: f003 0301 and.w r3, r3, #1
|
|
800721e: 2b00 cmp r3, #0
|
|
8007220: d1e4 bne.n 80071ec <HAL_ETH_ReadPHYRegister+0x7a>
|
|
}
|
|
|
|
/* Get MACMIIDR value */
|
|
*RegValue = (uint16_t)(heth->Instance->MACMIIDR);
|
|
8007222: 68fb ldr r3, [r7, #12]
|
|
8007224: 681b ldr r3, [r3, #0]
|
|
8007226: 695b ldr r3, [r3, #20]
|
|
8007228: b29b uxth r3, r3
|
|
800722a: 461a mov r2, r3
|
|
800722c: 687b ldr r3, [r7, #4]
|
|
800722e: 601a str r2, [r3, #0]
|
|
|
|
/* Set ETH HAL State to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
8007230: 68fb ldr r3, [r7, #12]
|
|
8007232: 2201 movs r2, #1
|
|
8007234: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8007238: 2300 movs r3, #0
|
|
}
|
|
800723a: 4618 mov r0, r3
|
|
800723c: 3718 adds r7, #24
|
|
800723e: 46bd mov sp, r7
|
|
8007240: bd80 pop {r7, pc}
|
|
|
|
08007242 <HAL_ETH_WritePHYRegister>:
|
|
* More PHY register could be written depending on the used PHY
|
|
* @param RegValue the value to write
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
|
|
{
|
|
8007242: b580 push {r7, lr}
|
|
8007244: b086 sub sp, #24
|
|
8007246: af00 add r7, sp, #0
|
|
8007248: 60f8 str r0, [r7, #12]
|
|
800724a: 460b mov r3, r1
|
|
800724c: 607a str r2, [r7, #4]
|
|
800724e: 817b strh r3, [r7, #10]
|
|
uint32_t tmpreg = 0;
|
|
8007250: 2300 movs r3, #0
|
|
8007252: 617b str r3, [r7, #20]
|
|
uint32_t tickstart = 0;
|
|
8007254: 2300 movs r3, #0
|
|
8007256: 613b str r3, [r7, #16]
|
|
|
|
/* Check parameters */
|
|
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
|
|
|
|
/* Check the ETH peripheral state */
|
|
if(heth->State == HAL_ETH_STATE_BUSY_WR)
|
|
8007258: 68fb ldr r3, [r7, #12]
|
|
800725a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800725e: b2db uxtb r3, r3
|
|
8007260: 2b42 cmp r3, #66 ; 0x42
|
|
8007262: d101 bne.n 8007268 <HAL_ETH_WritePHYRegister+0x26>
|
|
{
|
|
return HAL_BUSY;
|
|
8007264: 2302 movs r3, #2
|
|
8007266: e04e b.n 8007306 <HAL_ETH_WritePHYRegister+0xc4>
|
|
}
|
|
/* Set ETH HAL State to BUSY_WR */
|
|
heth->State = HAL_ETH_STATE_BUSY_WR;
|
|
8007268: 68fb ldr r3, [r7, #12]
|
|
800726a: 2242 movs r2, #66 ; 0x42
|
|
800726c: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Get the ETHERNET MACMIIAR value */
|
|
tmpreg = heth->Instance->MACMIIAR;
|
|
8007270: 68fb ldr r3, [r7, #12]
|
|
8007272: 681b ldr r3, [r3, #0]
|
|
8007274: 691b ldr r3, [r3, #16]
|
|
8007276: 617b str r3, [r7, #20]
|
|
|
|
/* Keep only the CSR Clock Range CR[2:0] bits value */
|
|
tmpreg &= ~ETH_MACMIIAR_CR_MASK;
|
|
8007278: 697b ldr r3, [r7, #20]
|
|
800727a: f003 031c and.w r3, r3, #28
|
|
800727e: 617b str r3, [r7, #20]
|
|
|
|
/* Prepare the MII register address value */
|
|
tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
|
|
8007280: 68fb ldr r3, [r7, #12]
|
|
8007282: 8a1b ldrh r3, [r3, #16]
|
|
8007284: 02db lsls r3, r3, #11
|
|
8007286: b29b uxth r3, r3
|
|
8007288: 697a ldr r2, [r7, #20]
|
|
800728a: 4313 orrs r3, r2
|
|
800728c: 617b str r3, [r7, #20]
|
|
tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
|
|
800728e: 897b ldrh r3, [r7, #10]
|
|
8007290: 019b lsls r3, r3, #6
|
|
8007292: f403 63f8 and.w r3, r3, #1984 ; 0x7c0
|
|
8007296: 697a ldr r2, [r7, #20]
|
|
8007298: 4313 orrs r3, r2
|
|
800729a: 617b str r3, [r7, #20]
|
|
tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
|
|
800729c: 697b ldr r3, [r7, #20]
|
|
800729e: f043 0302 orr.w r3, r3, #2
|
|
80072a2: 617b str r3, [r7, #20]
|
|
tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
|
|
80072a4: 697b ldr r3, [r7, #20]
|
|
80072a6: f043 0301 orr.w r3, r3, #1
|
|
80072aa: 617b str r3, [r7, #20]
|
|
|
|
/* Give the value to the MII data register */
|
|
heth->Instance->MACMIIDR = (uint16_t)RegValue;
|
|
80072ac: 687b ldr r3, [r7, #4]
|
|
80072ae: b29a uxth r2, r3
|
|
80072b0: 68fb ldr r3, [r7, #12]
|
|
80072b2: 681b ldr r3, [r3, #0]
|
|
80072b4: 615a str r2, [r3, #20]
|
|
|
|
/* Write the result value into the MII Address register */
|
|
heth->Instance->MACMIIAR = tmpreg;
|
|
80072b6: 68fb ldr r3, [r7, #12]
|
|
80072b8: 681b ldr r3, [r3, #0]
|
|
80072ba: 697a ldr r2, [r7, #20]
|
|
80072bc: 611a str r2, [r3, #16]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80072be: f7fe f80f bl 80052e0 <HAL_GetTick>
|
|
80072c2: 6138 str r0, [r7, #16]
|
|
|
|
/* Check for the Busy flag */
|
|
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
|
80072c4: e015 b.n 80072f2 <HAL_ETH_WritePHYRegister+0xb0>
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
|
|
80072c6: f7fe f80b bl 80052e0 <HAL_GetTick>
|
|
80072ca: 4602 mov r2, r0
|
|
80072cc: 693b ldr r3, [r7, #16]
|
|
80072ce: 1ad3 subs r3, r2, r3
|
|
80072d0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
80072d4: d309 bcc.n 80072ea <HAL_ETH_WritePHYRegister+0xa8>
|
|
{
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
80072d6: 68fb ldr r3, [r7, #12]
|
|
80072d8: 2201 movs r2, #1
|
|
80072da: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
80072de: 68fb ldr r3, [r7, #12]
|
|
80072e0: 2200 movs r2, #0
|
|
80072e2: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
return HAL_TIMEOUT;
|
|
80072e6: 2303 movs r3, #3
|
|
80072e8: e00d b.n 8007306 <HAL_ETH_WritePHYRegister+0xc4>
|
|
}
|
|
|
|
tmpreg = heth->Instance->MACMIIAR;
|
|
80072ea: 68fb ldr r3, [r7, #12]
|
|
80072ec: 681b ldr r3, [r3, #0]
|
|
80072ee: 691b ldr r3, [r3, #16]
|
|
80072f0: 617b str r3, [r7, #20]
|
|
while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
|
|
80072f2: 697b ldr r3, [r7, #20]
|
|
80072f4: f003 0301 and.w r3, r3, #1
|
|
80072f8: 2b00 cmp r3, #0
|
|
80072fa: d1e4 bne.n 80072c6 <HAL_ETH_WritePHYRegister+0x84>
|
|
}
|
|
|
|
/* Set ETH HAL State to READY */
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
80072fc: 68fb ldr r3, [r7, #12]
|
|
80072fe: 2201 movs r2, #1
|
|
8007300: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8007304: 2300 movs r3, #0
|
|
}
|
|
8007306: 4618 mov r0, r3
|
|
8007308: 3718 adds r7, #24
|
|
800730a: 46bd mov sp, r7
|
|
800730c: bd80 pop {r7, pc}
|
|
|
|
0800730e <HAL_ETH_Start>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
|
|
{
|
|
800730e: b580 push {r7, lr}
|
|
8007310: b082 sub sp, #8
|
|
8007312: af00 add r7, sp, #0
|
|
8007314: 6078 str r0, [r7, #4]
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8007316: 687b ldr r3, [r7, #4]
|
|
8007318: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800731c: 2b01 cmp r3, #1
|
|
800731e: d101 bne.n 8007324 <HAL_ETH_Start+0x16>
|
|
8007320: 2302 movs r3, #2
|
|
8007322: e01f b.n 8007364 <HAL_ETH_Start+0x56>
|
|
8007324: 687b ldr r3, [r7, #4]
|
|
8007326: 2201 movs r2, #1
|
|
8007328: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
800732c: 687b ldr r3, [r7, #4]
|
|
800732e: 2202 movs r2, #2
|
|
8007330: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Enable transmit state machine of the MAC for transmission on the MII */
|
|
ETH_MACTransmissionEnable(heth);
|
|
8007334: 6878 ldr r0, [r7, #4]
|
|
8007336: f000 fb45 bl 80079c4 <ETH_MACTransmissionEnable>
|
|
|
|
/* Enable receive state machine of the MAC for reception from the MII */
|
|
ETH_MACReceptionEnable(heth);
|
|
800733a: 6878 ldr r0, [r7, #4]
|
|
800733c: f000 fb7c bl 8007a38 <ETH_MACReceptionEnable>
|
|
|
|
/* Flush Transmit FIFO */
|
|
ETH_FlushTransmitFIFO(heth);
|
|
8007340: 6878 ldr r0, [r7, #4]
|
|
8007342: f000 fc13 bl 8007b6c <ETH_FlushTransmitFIFO>
|
|
|
|
/* Start DMA transmission */
|
|
ETH_DMATransmissionEnable(heth);
|
|
8007346: 6878 ldr r0, [r7, #4]
|
|
8007348: f000 fbb0 bl 8007aac <ETH_DMATransmissionEnable>
|
|
|
|
/* Start DMA reception */
|
|
ETH_DMAReceptionEnable(heth);
|
|
800734c: 6878 ldr r0, [r7, #4]
|
|
800734e: f000 fbdd bl 8007b0c <ETH_DMAReceptionEnable>
|
|
|
|
/* Set the ETH state to READY*/
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
8007352: 687b ldr r3, [r7, #4]
|
|
8007354: 2201 movs r2, #1
|
|
8007356: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
800735a: 687b ldr r3, [r7, #4]
|
|
800735c: 2200 movs r2, #0
|
|
800735e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8007362: 2300 movs r3, #0
|
|
}
|
|
8007364: 4618 mov r0, r3
|
|
8007366: 3708 adds r7, #8
|
|
8007368: 46bd mov sp, r7
|
|
800736a: bd80 pop {r7, pc}
|
|
|
|
0800736c <HAL_ETH_Stop>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
|
|
{
|
|
800736c: b580 push {r7, lr}
|
|
800736e: b082 sub sp, #8
|
|
8007370: af00 add r7, sp, #0
|
|
8007372: 6078 str r0, [r7, #4]
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
8007374: 687b ldr r3, [r7, #4]
|
|
8007376: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800737a: 2b01 cmp r3, #1
|
|
800737c: d101 bne.n 8007382 <HAL_ETH_Stop+0x16>
|
|
800737e: 2302 movs r3, #2
|
|
8007380: e01f b.n 80073c2 <HAL_ETH_Stop+0x56>
|
|
8007382: 687b ldr r3, [r7, #4]
|
|
8007384: 2201 movs r2, #1
|
|
8007386: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State = HAL_ETH_STATE_BUSY;
|
|
800738a: 687b ldr r3, [r7, #4]
|
|
800738c: 2202 movs r2, #2
|
|
800738e: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Stop DMA transmission */
|
|
ETH_DMATransmissionDisable(heth);
|
|
8007392: 6878 ldr r0, [r7, #4]
|
|
8007394: f000 fba2 bl 8007adc <ETH_DMATransmissionDisable>
|
|
|
|
/* Stop DMA reception */
|
|
ETH_DMAReceptionDisable(heth);
|
|
8007398: 6878 ldr r0, [r7, #4]
|
|
800739a: f000 fbcf bl 8007b3c <ETH_DMAReceptionDisable>
|
|
|
|
/* Disable receive state machine of the MAC for reception from the MII */
|
|
ETH_MACReceptionDisable(heth);
|
|
800739e: 6878 ldr r0, [r7, #4]
|
|
80073a0: f000 fb67 bl 8007a72 <ETH_MACReceptionDisable>
|
|
|
|
/* Flush Transmit FIFO */
|
|
ETH_FlushTransmitFIFO(heth);
|
|
80073a4: 6878 ldr r0, [r7, #4]
|
|
80073a6: f000 fbe1 bl 8007b6c <ETH_FlushTransmitFIFO>
|
|
|
|
/* Disable transmit state machine of the MAC for transmission on the MII */
|
|
ETH_MACTransmissionDisable(heth);
|
|
80073aa: 6878 ldr r0, [r7, #4]
|
|
80073ac: f000 fb27 bl 80079fe <ETH_MACTransmissionDisable>
|
|
|
|
/* Set the ETH state*/
|
|
heth->State = HAL_ETH_STATE_READY;
|
|
80073b0: 687b ldr r3, [r7, #4]
|
|
80073b2: 2201 movs r2, #1
|
|
80073b4: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
80073b8: 687b ldr r3, [r7, #4]
|
|
80073ba: 2200 movs r2, #0
|
|
80073bc: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80073c0: 2300 movs r3, #0
|
|
}
|
|
80073c2: 4618 mov r0, r3
|
|
80073c4: 3708 adds r7, #8
|
|
80073c6: 46bd mov sp, r7
|
|
80073c8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080073cc <HAL_ETH_ConfigMAC>:
|
|
* the configuration information for ETHERNET module
|
|
* @param macconf MAC Configuration structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
|
|
{
|
|
80073cc: b580 push {r7, lr}
|
|
80073ce: b084 sub sp, #16
|
|
80073d0: af00 add r7, sp, #0
|
|
80073d2: 6078 str r0, [r7, #4]
|
|
80073d4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpreg = 0;
|
|
80073d6: 2300 movs r3, #0
|
|
80073d8: 60fb str r3, [r7, #12]
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(heth);
|
|
80073da: 687b ldr r3, [r7, #4]
|
|
80073dc: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
80073e0: 2b01 cmp r3, #1
|
|
80073e2: d101 bne.n 80073e8 <HAL_ETH_ConfigMAC+0x1c>
|
|
80073e4: 2302 movs r3, #2
|
|
80073e6: e0e4 b.n 80075b2 <HAL_ETH_ConfigMAC+0x1e6>
|
|
80073e8: 687b ldr r3, [r7, #4]
|
|
80073ea: 2201 movs r2, #1
|
|
80073ec: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Set the ETH peripheral state to BUSY */
|
|
heth->State= HAL_ETH_STATE_BUSY;
|
|
80073f0: 687b ldr r3, [r7, #4]
|
|
80073f2: 2202 movs r2, #2
|
|
80073f4: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
assert_param(IS_ETH_SPEED(heth->Init.Speed));
|
|
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
|
|
|
|
if (macconf != NULL)
|
|
80073f8: 683b ldr r3, [r7, #0]
|
|
80073fa: 2b00 cmp r3, #0
|
|
80073fc: f000 80b1 beq.w 8007562 <HAL_ETH_ConfigMAC+0x196>
|
|
assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
|
|
assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
|
|
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
/* Get the ETHERNET MACCR value */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
8007400: 687b ldr r3, [r7, #4]
|
|
8007402: 681b ldr r3, [r3, #0]
|
|
8007404: 681b ldr r3, [r3, #0]
|
|
8007406: 60fb str r3, [r7, #12]
|
|
/* Clear WD, PCE, PS, TE and RE bits */
|
|
tmpreg &= ETH_MACCR_CLEAR_MASK;
|
|
8007408: 68fa ldr r2, [r7, #12]
|
|
800740a: 4b6c ldr r3, [pc, #432] ; (80075bc <HAL_ETH_ConfigMAC+0x1f0>)
|
|
800740c: 4013 ands r3, r2
|
|
800740e: 60fb str r3, [r7, #12]
|
|
|
|
tmpreg |= (uint32_t)(macconf->Watchdog |
|
|
8007410: 683b ldr r3, [r7, #0]
|
|
8007412: 681a ldr r2, [r3, #0]
|
|
macconf->Jabber |
|
|
8007414: 683b ldr r3, [r7, #0]
|
|
8007416: 685b ldr r3, [r3, #4]
|
|
tmpreg |= (uint32_t)(macconf->Watchdog |
|
|
8007418: 431a orrs r2, r3
|
|
macconf->InterFrameGap |
|
|
800741a: 683b ldr r3, [r7, #0]
|
|
800741c: 689b ldr r3, [r3, #8]
|
|
macconf->Jabber |
|
|
800741e: 431a orrs r2, r3
|
|
macconf->CarrierSense |
|
|
8007420: 683b ldr r3, [r7, #0]
|
|
8007422: 68db ldr r3, [r3, #12]
|
|
macconf->InterFrameGap |
|
|
8007424: 431a orrs r2, r3
|
|
(heth->Init).Speed |
|
|
8007426: 687b ldr r3, [r7, #4]
|
|
8007428: 689b ldr r3, [r3, #8]
|
|
macconf->CarrierSense |
|
|
800742a: 431a orrs r2, r3
|
|
macconf->ReceiveOwn |
|
|
800742c: 683b ldr r3, [r7, #0]
|
|
800742e: 691b ldr r3, [r3, #16]
|
|
(heth->Init).Speed |
|
|
8007430: 431a orrs r2, r3
|
|
macconf->LoopbackMode |
|
|
8007432: 683b ldr r3, [r7, #0]
|
|
8007434: 695b ldr r3, [r3, #20]
|
|
macconf->ReceiveOwn |
|
|
8007436: 431a orrs r2, r3
|
|
(heth->Init).DuplexMode |
|
|
8007438: 687b ldr r3, [r7, #4]
|
|
800743a: 68db ldr r3, [r3, #12]
|
|
macconf->LoopbackMode |
|
|
800743c: 431a orrs r2, r3
|
|
macconf->ChecksumOffload |
|
|
800743e: 683b ldr r3, [r7, #0]
|
|
8007440: 699b ldr r3, [r3, #24]
|
|
(heth->Init).DuplexMode |
|
|
8007442: 431a orrs r2, r3
|
|
macconf->RetryTransmission |
|
|
8007444: 683b ldr r3, [r7, #0]
|
|
8007446: 69db ldr r3, [r3, #28]
|
|
macconf->ChecksumOffload |
|
|
8007448: 431a orrs r2, r3
|
|
macconf->AutomaticPadCRCStrip |
|
|
800744a: 683b ldr r3, [r7, #0]
|
|
800744c: 6a1b ldr r3, [r3, #32]
|
|
macconf->RetryTransmission |
|
|
800744e: 431a orrs r2, r3
|
|
macconf->BackOffLimit |
|
|
8007450: 683b ldr r3, [r7, #0]
|
|
8007452: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
macconf->AutomaticPadCRCStrip |
|
|
8007454: 431a orrs r2, r3
|
|
macconf->DeferralCheck);
|
|
8007456: 683b ldr r3, [r7, #0]
|
|
8007458: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
macconf->BackOffLimit |
|
|
800745a: 4313 orrs r3, r2
|
|
tmpreg |= (uint32_t)(macconf->Watchdog |
|
|
800745c: 68fa ldr r2, [r7, #12]
|
|
800745e: 4313 orrs r3, r2
|
|
8007460: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to ETHERNET MACCR */
|
|
(heth->Instance)->MACCR = (uint32_t)tmpreg;
|
|
8007462: 687b ldr r3, [r7, #4]
|
|
8007464: 681b ldr r3, [r3, #0]
|
|
8007466: 68fa ldr r2, [r7, #12]
|
|
8007468: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account :
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
800746a: 687b ldr r3, [r7, #4]
|
|
800746c: 681b ldr r3, [r3, #0]
|
|
800746e: 681b ldr r3, [r3, #0]
|
|
8007470: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007472: 2001 movs r0, #1
|
|
8007474: f7fd ff40 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
8007478: 687b ldr r3, [r7, #4]
|
|
800747a: 681b ldr r3, [r3, #0]
|
|
800747c: 68fa ldr r2, [r7, #12]
|
|
800747e: 601a str r2, [r3, #0]
|
|
|
|
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
|
|
/* Write to ETHERNET MACFFR */
|
|
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
|
|
8007480: 683b ldr r3, [r7, #0]
|
|
8007482: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
macconf->SourceAddrFilter |
|
|
8007484: 683b ldr r3, [r7, #0]
|
|
8007486: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
|
|
8007488: 431a orrs r2, r3
|
|
macconf->PassControlFrames |
|
|
800748a: 683b ldr r3, [r7, #0]
|
|
800748c: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
macconf->SourceAddrFilter |
|
|
800748e: 431a orrs r2, r3
|
|
macconf->BroadcastFramesReception |
|
|
8007490: 683b ldr r3, [r7, #0]
|
|
8007492: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
macconf->PassControlFrames |
|
|
8007494: 431a orrs r2, r3
|
|
macconf->DestinationAddrFilter |
|
|
8007496: 683b ldr r3, [r7, #0]
|
|
8007498: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
macconf->BroadcastFramesReception |
|
|
800749a: 431a orrs r2, r3
|
|
macconf->PromiscuousMode |
|
|
800749c: 683b ldr r3, [r7, #0]
|
|
800749e: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
macconf->DestinationAddrFilter |
|
|
80074a0: 431a orrs r2, r3
|
|
macconf->MulticastFramesFilter |
|
|
80074a2: 683b ldr r3, [r7, #0]
|
|
80074a4: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
macconf->PromiscuousMode |
|
|
80074a6: ea42 0103 orr.w r1, r2, r3
|
|
macconf->UnicastFramesFilter);
|
|
80074aa: 683b ldr r3, [r7, #0]
|
|
80074ac: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
|
|
80074ae: 687b ldr r3, [r7, #4]
|
|
80074b0: 681b ldr r3, [r3, #0]
|
|
macconf->MulticastFramesFilter |
|
|
80074b2: 430a orrs r2, r1
|
|
(heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
|
|
80074b4: 605a str r2, [r3, #4]
|
|
|
|
/* Wait until the write operation will be taken into account :
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACFFR;
|
|
80074b6: 687b ldr r3, [r7, #4]
|
|
80074b8: 681b ldr r3, [r3, #0]
|
|
80074ba: 685b ldr r3, [r3, #4]
|
|
80074bc: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80074be: 2001 movs r0, #1
|
|
80074c0: f7fd ff1a bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACFFR = tmpreg;
|
|
80074c4: 687b ldr r3, [r7, #4]
|
|
80074c6: 681b ldr r3, [r3, #0]
|
|
80074c8: 68fa ldr r2, [r7, #12]
|
|
80074ca: 605a str r2, [r3, #4]
|
|
|
|
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
|
|
/* Write to ETHERNET MACHTHR */
|
|
(heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
|
|
80074cc: 687b ldr r3, [r7, #4]
|
|
80074ce: 681b ldr r3, [r3, #0]
|
|
80074d0: 683a ldr r2, [r7, #0]
|
|
80074d2: 6cd2 ldr r2, [r2, #76] ; 0x4c
|
|
80074d4: 609a str r2, [r3, #8]
|
|
|
|
/* Write to ETHERNET MACHTLR */
|
|
(heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
|
|
80074d6: 687b ldr r3, [r7, #4]
|
|
80074d8: 681b ldr r3, [r3, #0]
|
|
80074da: 683a ldr r2, [r7, #0]
|
|
80074dc: 6d12 ldr r2, [r2, #80] ; 0x50
|
|
80074de: 60da str r2, [r3, #12]
|
|
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
|
|
|
|
/* Get the ETHERNET MACFCR value */
|
|
tmpreg = (heth->Instance)->MACFCR;
|
|
80074e0: 687b ldr r3, [r7, #4]
|
|
80074e2: 681b ldr r3, [r3, #0]
|
|
80074e4: 699b ldr r3, [r3, #24]
|
|
80074e6: 60fb str r3, [r7, #12]
|
|
/* Clear xx bits */
|
|
tmpreg &= ETH_MACFCR_CLEAR_MASK;
|
|
80074e8: 68fa ldr r2, [r7, #12]
|
|
80074ea: f64f 7341 movw r3, #65345 ; 0xff41
|
|
80074ee: 4013 ands r3, r2
|
|
80074f0: 60fb str r3, [r7, #12]
|
|
|
|
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
|
|
80074f2: 683b ldr r3, [r7, #0]
|
|
80074f4: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
80074f6: 041a lsls r2, r3, #16
|
|
macconf->ZeroQuantaPause |
|
|
80074f8: 683b ldr r3, [r7, #0]
|
|
80074fa: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
|
|
80074fc: 431a orrs r2, r3
|
|
macconf->PauseLowThreshold |
|
|
80074fe: 683b ldr r3, [r7, #0]
|
|
8007500: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
macconf->ZeroQuantaPause |
|
|
8007502: 431a orrs r2, r3
|
|
macconf->UnicastPauseFrameDetect |
|
|
8007504: 683b ldr r3, [r7, #0]
|
|
8007506: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
macconf->PauseLowThreshold |
|
|
8007508: 431a orrs r2, r3
|
|
macconf->ReceiveFlowControl |
|
|
800750a: 683b ldr r3, [r7, #0]
|
|
800750c: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
macconf->UnicastPauseFrameDetect |
|
|
800750e: 431a orrs r2, r3
|
|
macconf->TransmitFlowControl);
|
|
8007510: 683b ldr r3, [r7, #0]
|
|
8007512: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
macconf->ReceiveFlowControl |
|
|
8007514: 4313 orrs r3, r2
|
|
tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
|
|
8007516: 68fa ldr r2, [r7, #12]
|
|
8007518: 4313 orrs r3, r2
|
|
800751a: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to ETHERNET MACFCR */
|
|
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
|
|
800751c: 687b ldr r3, [r7, #4]
|
|
800751e: 681b ldr r3, [r3, #0]
|
|
8007520: 68fa ldr r2, [r7, #12]
|
|
8007522: 619a str r2, [r3, #24]
|
|
|
|
/* Wait until the write operation will be taken into account :
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACFCR;
|
|
8007524: 687b ldr r3, [r7, #4]
|
|
8007526: 681b ldr r3, [r3, #0]
|
|
8007528: 699b ldr r3, [r3, #24]
|
|
800752a: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
800752c: 2001 movs r0, #1
|
|
800752e: f7fd fee3 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACFCR = tmpreg;
|
|
8007532: 687b ldr r3, [r7, #4]
|
|
8007534: 681b ldr r3, [r3, #0]
|
|
8007536: 68fa ldr r2, [r7, #12]
|
|
8007538: 619a str r2, [r3, #24]
|
|
|
|
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
|
|
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
|
|
800753a: 683b ldr r3, [r7, #0]
|
|
800753c: 6ed9 ldr r1, [r3, #108] ; 0x6c
|
|
macconf->VLANTagIdentifier);
|
|
800753e: 683b ldr r3, [r7, #0]
|
|
8007540: 6f1a ldr r2, [r3, #112] ; 0x70
|
|
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
|
|
8007542: 687b ldr r3, [r7, #4]
|
|
8007544: 681b ldr r3, [r3, #0]
|
|
8007546: 430a orrs r2, r1
|
|
8007548: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until the write operation will be taken into account :
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACVLANTR;
|
|
800754a: 687b ldr r3, [r7, #4]
|
|
800754c: 681b ldr r3, [r3, #0]
|
|
800754e: 69db ldr r3, [r3, #28]
|
|
8007550: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007552: 2001 movs r0, #1
|
|
8007554: f7fd fed0 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACVLANTR = tmpreg;
|
|
8007558: 687b ldr r3, [r7, #4]
|
|
800755a: 681b ldr r3, [r3, #0]
|
|
800755c: 68fa ldr r2, [r7, #12]
|
|
800755e: 61da str r2, [r3, #28]
|
|
8007560: e01e b.n 80075a0 <HAL_ETH_ConfigMAC+0x1d4>
|
|
}
|
|
else /* macconf == NULL : here we just configure Speed and Duplex mode */
|
|
{
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
/* Get the ETHERNET MACCR value */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
8007562: 687b ldr r3, [r7, #4]
|
|
8007564: 681b ldr r3, [r3, #0]
|
|
8007566: 681b ldr r3, [r3, #0]
|
|
8007568: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear FES and DM bits */
|
|
tmpreg &= ~((uint32_t)0x00004800);
|
|
800756a: 68fb ldr r3, [r7, #12]
|
|
800756c: f423 4390 bic.w r3, r3, #18432 ; 0x4800
|
|
8007570: 60fb str r3, [r7, #12]
|
|
|
|
tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
|
|
8007572: 687b ldr r3, [r7, #4]
|
|
8007574: 689a ldr r2, [r3, #8]
|
|
8007576: 687b ldr r3, [r7, #4]
|
|
8007578: 68db ldr r3, [r3, #12]
|
|
800757a: 4313 orrs r3, r2
|
|
800757c: 68fa ldr r2, [r7, #12]
|
|
800757e: 4313 orrs r3, r2
|
|
8007580: 60fb str r3, [r7, #12]
|
|
|
|
/* Write to ETHERNET MACCR */
|
|
(heth->Instance)->MACCR = (uint32_t)tmpreg;
|
|
8007582: 687b ldr r3, [r7, #4]
|
|
8007584: 681b ldr r3, [r3, #0]
|
|
8007586: 68fa ldr r2, [r7, #12]
|
|
8007588: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
800758a: 687b ldr r3, [r7, #4]
|
|
800758c: 681b ldr r3, [r3, #0]
|
|
800758e: 681b ldr r3, [r3, #0]
|
|
8007590: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007592: 2001 movs r0, #1
|
|
8007594: f7fd feb0 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
8007598: 687b ldr r3, [r7, #4]
|
|
800759a: 681b ldr r3, [r3, #0]
|
|
800759c: 68fa ldr r2, [r7, #12]
|
|
800759e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the ETH state to Ready */
|
|
heth->State= HAL_ETH_STATE_READY;
|
|
80075a0: 687b ldr r3, [r7, #4]
|
|
80075a2: 2201 movs r2, #1
|
|
80075a4: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(heth);
|
|
80075a8: 687b ldr r3, [r7, #4]
|
|
80075aa: 2200 movs r2, #0
|
|
80075ac: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80075b0: 2300 movs r3, #0
|
|
}
|
|
80075b2: 4618 mov r0, r3
|
|
80075b4: 3710 adds r7, #16
|
|
80075b6: 46bd mov sp, r7
|
|
80075b8: bd80 pop {r7, pc}
|
|
80075ba: bf00 nop
|
|
80075bc: ff20810f .word 0xff20810f
|
|
|
|
080075c0 <ETH_MACDMAConfig>:
|
|
* the configuration information for ETHERNET module
|
|
* @param err Ethernet Init error
|
|
* @retval HAL status
|
|
*/
|
|
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
|
|
{
|
|
80075c0: b580 push {r7, lr}
|
|
80075c2: b0b0 sub sp, #192 ; 0xc0
|
|
80075c4: af00 add r7, sp, #0
|
|
80075c6: 6078 str r0, [r7, #4]
|
|
80075c8: 6039 str r1, [r7, #0]
|
|
ETH_MACInitTypeDef macinit;
|
|
ETH_DMAInitTypeDef dmainit;
|
|
uint32_t tmpreg = 0;
|
|
80075ca: 2300 movs r3, #0
|
|
80075cc: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
|
|
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
|
|
80075d0: 683b ldr r3, [r7, #0]
|
|
80075d2: 2b00 cmp r3, #0
|
|
80075d4: d007 beq.n 80075e6 <ETH_MACDMAConfig+0x26>
|
|
{
|
|
/* Set Ethernet duplex mode to Full-duplex */
|
|
(heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
|
|
80075d6: 687b ldr r3, [r7, #4]
|
|
80075d8: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
80075dc: 60da str r2, [r3, #12]
|
|
|
|
/* Set Ethernet speed to 100M */
|
|
(heth->Init).Speed = ETH_SPEED_100M;
|
|
80075de: 687b ldr r3, [r7, #4]
|
|
80075e0: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
80075e4: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Ethernet MAC default initialization **************************************/
|
|
macinit.Watchdog = ETH_WATCHDOG_ENABLE;
|
|
80075e6: 2300 movs r3, #0
|
|
80075e8: 64bb str r3, [r7, #72] ; 0x48
|
|
macinit.Jabber = ETH_JABBER_ENABLE;
|
|
80075ea: 2300 movs r3, #0
|
|
80075ec: 64fb str r3, [r7, #76] ; 0x4c
|
|
macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
|
|
80075ee: 2300 movs r3, #0
|
|
80075f0: 653b str r3, [r7, #80] ; 0x50
|
|
macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
|
|
80075f2: 2300 movs r3, #0
|
|
80075f4: 657b str r3, [r7, #84] ; 0x54
|
|
macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
|
|
80075f6: 2300 movs r3, #0
|
|
80075f8: 65bb str r3, [r7, #88] ; 0x58
|
|
macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
|
|
80075fa: 2300 movs r3, #0
|
|
80075fc: 65fb str r3, [r7, #92] ; 0x5c
|
|
if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
|
|
80075fe: 687b ldr r3, [r7, #4]
|
|
8007600: 69db ldr r3, [r3, #28]
|
|
8007602: 2b00 cmp r3, #0
|
|
8007604: d103 bne.n 800760e <ETH_MACDMAConfig+0x4e>
|
|
{
|
|
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
|
|
8007606: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
800760a: 663b str r3, [r7, #96] ; 0x60
|
|
800760c: e001 b.n 8007612 <ETH_MACDMAConfig+0x52>
|
|
}
|
|
else
|
|
{
|
|
macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
|
|
800760e: 2300 movs r3, #0
|
|
8007610: 663b str r3, [r7, #96] ; 0x60
|
|
}
|
|
macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
|
|
8007612: f44f 7300 mov.w r3, #512 ; 0x200
|
|
8007616: 667b str r3, [r7, #100] ; 0x64
|
|
macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
|
|
8007618: 2300 movs r3, #0
|
|
800761a: 66bb str r3, [r7, #104] ; 0x68
|
|
macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
|
|
800761c: 2300 movs r3, #0
|
|
800761e: 66fb str r3, [r7, #108] ; 0x6c
|
|
macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
|
|
8007620: 2300 movs r3, #0
|
|
8007622: 673b str r3, [r7, #112] ; 0x70
|
|
macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
|
|
8007624: 2300 movs r3, #0
|
|
8007626: 677b str r3, [r7, #116] ; 0x74
|
|
macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
|
|
8007628: 2300 movs r3, #0
|
|
800762a: 67bb str r3, [r7, #120] ; 0x78
|
|
macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
|
|
800762c: 2340 movs r3, #64 ; 0x40
|
|
800762e: 67fb str r3, [r7, #124] ; 0x7c
|
|
macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
|
|
8007630: 2300 movs r3, #0
|
|
8007632: f8c7 3080 str.w r3, [r7, #128] ; 0x80
|
|
macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
|
|
8007636: 2300 movs r3, #0
|
|
8007638: f8c7 3084 str.w r3, [r7, #132] ; 0x84
|
|
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
|
|
800763c: 2300 movs r3, #0
|
|
800763e: f8c7 3088 str.w r3, [r7, #136] ; 0x88
|
|
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
|
|
8007642: 2300 movs r3, #0
|
|
8007644: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|
|
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
|
|
8007648: 2300 movs r3, #0
|
|
800764a: f8c7 3090 str.w r3, [r7, #144] ; 0x90
|
|
macinit.HashTableHigh = 0x0;
|
|
800764e: 2300 movs r3, #0
|
|
8007650: f8c7 3094 str.w r3, [r7, #148] ; 0x94
|
|
macinit.HashTableLow = 0x0;
|
|
8007654: 2300 movs r3, #0
|
|
8007656: f8c7 3098 str.w r3, [r7, #152] ; 0x98
|
|
macinit.PauseTime = 0x0;
|
|
800765a: 2300 movs r3, #0
|
|
800765c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
|
|
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
|
|
8007660: 2380 movs r3, #128 ; 0x80
|
|
8007662: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
|
|
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
|
|
8007666: 2300 movs r3, #0
|
|
8007668: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
|
|
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
|
|
800766c: 2300 movs r3, #0
|
|
800766e: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
|
|
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
|
|
8007672: 2300 movs r3, #0
|
|
8007674: f8c7 30ac str.w r3, [r7, #172] ; 0xac
|
|
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
|
|
8007678: 2300 movs r3, #0
|
|
800767a: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
|
|
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
|
|
800767e: 2300 movs r3, #0
|
|
8007680: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
|
|
macinit.VLANTagIdentifier = 0x0;
|
|
8007684: 2300 movs r3, #0
|
|
8007686: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
|
|
|
|
/*------------------------ ETHERNET MACCR Configuration --------------------*/
|
|
/* Get the ETHERNET MACCR value */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
800768a: 687b ldr r3, [r7, #4]
|
|
800768c: 681b ldr r3, [r3, #0]
|
|
800768e: 681b ldr r3, [r3, #0]
|
|
8007690: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Clear WD, PCE, PS, TE and RE bits */
|
|
tmpreg &= ETH_MACCR_CLEAR_MASK;
|
|
8007694: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007698: 4bab ldr r3, [pc, #684] ; (8007948 <ETH_MACDMAConfig+0x388>)
|
|
800769a: 4013 ands r3, r2
|
|
800769c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Set the IPCO bit according to ETH ChecksumOffload value */
|
|
/* Set the DR bit according to ETH RetryTransmission value */
|
|
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
|
|
/* Set the BL bit according to ETH BackOffLimit value */
|
|
/* Set the DC bit according to ETH DeferralCheck value */
|
|
tmpreg |= (uint32_t)(macinit.Watchdog |
|
|
80076a0: 6cba ldr r2, [r7, #72] ; 0x48
|
|
macinit.Jabber |
|
|
80076a2: 6cfb ldr r3, [r7, #76] ; 0x4c
|
|
tmpreg |= (uint32_t)(macinit.Watchdog |
|
|
80076a4: 431a orrs r2, r3
|
|
macinit.InterFrameGap |
|
|
80076a6: 6d3b ldr r3, [r7, #80] ; 0x50
|
|
macinit.Jabber |
|
|
80076a8: 431a orrs r2, r3
|
|
macinit.CarrierSense |
|
|
80076aa: 6d7b ldr r3, [r7, #84] ; 0x54
|
|
macinit.InterFrameGap |
|
|
80076ac: 431a orrs r2, r3
|
|
(heth->Init).Speed |
|
|
80076ae: 687b ldr r3, [r7, #4]
|
|
80076b0: 689b ldr r3, [r3, #8]
|
|
macinit.CarrierSense |
|
|
80076b2: 431a orrs r2, r3
|
|
macinit.ReceiveOwn |
|
|
80076b4: 6dbb ldr r3, [r7, #88] ; 0x58
|
|
(heth->Init).Speed |
|
|
80076b6: 431a orrs r2, r3
|
|
macinit.LoopbackMode |
|
|
80076b8: 6dfb ldr r3, [r7, #92] ; 0x5c
|
|
macinit.ReceiveOwn |
|
|
80076ba: 431a orrs r2, r3
|
|
(heth->Init).DuplexMode |
|
|
80076bc: 687b ldr r3, [r7, #4]
|
|
80076be: 68db ldr r3, [r3, #12]
|
|
macinit.LoopbackMode |
|
|
80076c0: 431a orrs r2, r3
|
|
macinit.ChecksumOffload |
|
|
80076c2: 6e3b ldr r3, [r7, #96] ; 0x60
|
|
(heth->Init).DuplexMode |
|
|
80076c4: 431a orrs r2, r3
|
|
macinit.RetryTransmission |
|
|
80076c6: 6e7b ldr r3, [r7, #100] ; 0x64
|
|
macinit.ChecksumOffload |
|
|
80076c8: 431a orrs r2, r3
|
|
macinit.AutomaticPadCRCStrip |
|
|
80076ca: 6ebb ldr r3, [r7, #104] ; 0x68
|
|
macinit.RetryTransmission |
|
|
80076cc: 431a orrs r2, r3
|
|
macinit.BackOffLimit |
|
|
80076ce: 6efb ldr r3, [r7, #108] ; 0x6c
|
|
macinit.AutomaticPadCRCStrip |
|
|
80076d0: 431a orrs r2, r3
|
|
macinit.DeferralCheck);
|
|
80076d2: 6f3b ldr r3, [r7, #112] ; 0x70
|
|
macinit.BackOffLimit |
|
|
80076d4: 4313 orrs r3, r2
|
|
tmpreg |= (uint32_t)(macinit.Watchdog |
|
|
80076d6: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80076da: 4313 orrs r3, r2
|
|
80076dc: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
|
|
/* Write to ETHERNET MACCR */
|
|
(heth->Instance)->MACCR = (uint32_t)tmpreg;
|
|
80076e0: 687b ldr r3, [r7, #4]
|
|
80076e2: 681b ldr r3, [r3, #0]
|
|
80076e4: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80076e8: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
80076ea: 687b ldr r3, [r7, #4]
|
|
80076ec: 681b ldr r3, [r3, #0]
|
|
80076ee: 681b ldr r3, [r3, #0]
|
|
80076f0: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80076f4: 2001 movs r0, #1
|
|
80076f6: f7fd fdff bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
80076fa: 687b ldr r3, [r7, #4]
|
|
80076fc: 681b ldr r3, [r3, #0]
|
|
80076fe: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007702: 601a str r2, [r3, #0]
|
|
/* Set the DAIF bit according to ETH DestinationAddrFilter value */
|
|
/* Set the PR bit according to ETH PromiscuousMode value */
|
|
/* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
|
|
/* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
|
|
/* Write to ETHERNET MACFFR */
|
|
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
|
|
8007704: 6f7a ldr r2, [r7, #116] ; 0x74
|
|
macinit.SourceAddrFilter |
|
|
8007706: 6fbb ldr r3, [r7, #120] ; 0x78
|
|
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
|
|
8007708: 431a orrs r2, r3
|
|
macinit.PassControlFrames |
|
|
800770a: 6ffb ldr r3, [r7, #124] ; 0x7c
|
|
macinit.SourceAddrFilter |
|
|
800770c: 431a orrs r2, r3
|
|
macinit.BroadcastFramesReception |
|
|
800770e: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80
|
|
macinit.PassControlFrames |
|
|
8007712: 431a orrs r2, r3
|
|
macinit.DestinationAddrFilter |
|
|
8007714: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
|
|
macinit.BroadcastFramesReception |
|
|
8007718: 431a orrs r2, r3
|
|
macinit.PromiscuousMode |
|
|
800771a: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
|
|
macinit.DestinationAddrFilter |
|
|
800771e: 431a orrs r2, r3
|
|
macinit.MulticastFramesFilter |
|
|
8007720: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
|
|
macinit.PromiscuousMode |
|
|
8007724: ea42 0103 orr.w r1, r2, r3
|
|
macinit.UnicastFramesFilter);
|
|
8007728: f8d7 2090 ldr.w r2, [r7, #144] ; 0x90
|
|
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
|
|
800772c: 687b ldr r3, [r7, #4]
|
|
800772e: 681b ldr r3, [r3, #0]
|
|
macinit.MulticastFramesFilter |
|
|
8007730: 430a orrs r2, r1
|
|
(heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
|
|
8007732: 605a str r2, [r3, #4]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACFFR;
|
|
8007734: 687b ldr r3, [r7, #4]
|
|
8007736: 681b ldr r3, [r3, #0]
|
|
8007738: 685b ldr r3, [r3, #4]
|
|
800773a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
800773e: 2001 movs r0, #1
|
|
8007740: f7fd fdda bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACFFR = tmpreg;
|
|
8007744: 687b ldr r3, [r7, #4]
|
|
8007746: 681b ldr r3, [r3, #0]
|
|
8007748: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
800774c: 605a str r2, [r3, #4]
|
|
|
|
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
|
|
/* Write to ETHERNET MACHTHR */
|
|
(heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
|
|
800774e: 687b ldr r3, [r7, #4]
|
|
8007750: 681b ldr r3, [r3, #0]
|
|
8007752: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
|
|
8007756: 609a str r2, [r3, #8]
|
|
|
|
/* Write to ETHERNET MACHTLR */
|
|
(heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
|
|
8007758: 687b ldr r3, [r7, #4]
|
|
800775a: 681b ldr r3, [r3, #0]
|
|
800775c: f8d7 2098 ldr.w r2, [r7, #152] ; 0x98
|
|
8007760: 60da str r2, [r3, #12]
|
|
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
|
|
|
|
/* Get the ETHERNET MACFCR value */
|
|
tmpreg = (heth->Instance)->MACFCR;
|
|
8007762: 687b ldr r3, [r7, #4]
|
|
8007764: 681b ldr r3, [r3, #0]
|
|
8007766: 699b ldr r3, [r3, #24]
|
|
8007768: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Clear xx bits */
|
|
tmpreg &= ETH_MACFCR_CLEAR_MASK;
|
|
800776c: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007770: f64f 7341 movw r3, #65345 ; 0xff41
|
|
8007774: 4013 ands r3, r2
|
|
8007776: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
|
|
/* Set the PLT bit according to ETH PauseLowThreshold value */
|
|
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
|
|
/* Set the RFE bit according to ETH ReceiveFlowControl value */
|
|
/* Set the TFE bit according to ETH TransmitFlowControl value */
|
|
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
|
|
800777a: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
|
|
800777e: 041a lsls r2, r3, #16
|
|
macinit.ZeroQuantaPause |
|
|
8007780: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
|
|
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
|
|
8007784: 431a orrs r2, r3
|
|
macinit.PauseLowThreshold |
|
|
8007786: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
|
|
macinit.ZeroQuantaPause |
|
|
800778a: 431a orrs r2, r3
|
|
macinit.UnicastPauseFrameDetect |
|
|
800778c: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8
|
|
macinit.PauseLowThreshold |
|
|
8007790: 431a orrs r2, r3
|
|
macinit.ReceiveFlowControl |
|
|
8007792: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
|
|
macinit.UnicastPauseFrameDetect |
|
|
8007796: 431a orrs r2, r3
|
|
macinit.TransmitFlowControl);
|
|
8007798: f8d7 30b0 ldr.w r3, [r7, #176] ; 0xb0
|
|
macinit.ReceiveFlowControl |
|
|
800779c: 4313 orrs r3, r2
|
|
tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
|
|
800779e: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80077a2: 4313 orrs r3, r2
|
|
80077a4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
|
|
/* Write to ETHERNET MACFCR */
|
|
(heth->Instance)->MACFCR = (uint32_t)tmpreg;
|
|
80077a8: 687b ldr r3, [r7, #4]
|
|
80077aa: 681b ldr r3, [r3, #0]
|
|
80077ac: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80077b0: 619a str r2, [r3, #24]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACFCR;
|
|
80077b2: 687b ldr r3, [r7, #4]
|
|
80077b4: 681b ldr r3, [r3, #0]
|
|
80077b6: 699b ldr r3, [r3, #24]
|
|
80077b8: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80077bc: 2001 movs r0, #1
|
|
80077be: f7fd fd9b bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACFCR = tmpreg;
|
|
80077c2: 687b ldr r3, [r7, #4]
|
|
80077c4: 681b ldr r3, [r3, #0]
|
|
80077c6: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80077ca: 619a str r2, [r3, #24]
|
|
|
|
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
|
|
/* Set the ETV bit according to ETH VLANTagComparison value */
|
|
/* Set the VL bit according to ETH VLANTagIdentifier value */
|
|
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
|
|
80077cc: f8d7 10b4 ldr.w r1, [r7, #180] ; 0xb4
|
|
macinit.VLANTagIdentifier);
|
|
80077d0: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
|
|
(heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
|
|
80077d4: 687b ldr r3, [r7, #4]
|
|
80077d6: 681b ldr r3, [r3, #0]
|
|
80077d8: 430a orrs r2, r1
|
|
80077da: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACVLANTR;
|
|
80077dc: 687b ldr r3, [r7, #4]
|
|
80077de: 681b ldr r3, [r3, #0]
|
|
80077e0: 69db ldr r3, [r3, #28]
|
|
80077e2: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80077e6: 2001 movs r0, #1
|
|
80077e8: f7fd fd86 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACVLANTR = tmpreg;
|
|
80077ec: 687b ldr r3, [r7, #4]
|
|
80077ee: 681b ldr r3, [r3, #0]
|
|
80077f0: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80077f4: 61da str r2, [r3, #28]
|
|
|
|
/* Ethernet DMA default initialization ************************************/
|
|
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
|
|
80077f6: 2300 movs r3, #0
|
|
80077f8: 60bb str r3, [r7, #8]
|
|
dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
|
|
80077fa: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
80077fe: 60fb str r3, [r7, #12]
|
|
dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
|
|
8007800: 2300 movs r3, #0
|
|
8007802: 613b str r3, [r7, #16]
|
|
dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
|
|
8007804: f44f 1300 mov.w r3, #2097152 ; 0x200000
|
|
8007808: 617b str r3, [r7, #20]
|
|
dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
|
|
800780a: 2300 movs r3, #0
|
|
800780c: 61bb str r3, [r7, #24]
|
|
dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
|
|
800780e: 2300 movs r3, #0
|
|
8007810: 61fb str r3, [r7, #28]
|
|
dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
|
|
8007812: 2300 movs r3, #0
|
|
8007814: 623b str r3, [r7, #32]
|
|
dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
|
|
8007816: 2300 movs r3, #0
|
|
8007818: 627b str r3, [r7, #36] ; 0x24
|
|
dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
|
|
800781a: 2304 movs r3, #4
|
|
800781c: 62bb str r3, [r7, #40] ; 0x28
|
|
dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
|
|
800781e: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8007822: 62fb str r3, [r7, #44] ; 0x2c
|
|
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
|
|
8007824: f44f 3380 mov.w r3, #65536 ; 0x10000
|
|
8007828: 633b str r3, [r7, #48] ; 0x30
|
|
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
|
|
800782a: f44f 0380 mov.w r3, #4194304 ; 0x400000
|
|
800782e: 637b str r3, [r7, #52] ; 0x34
|
|
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
|
|
8007830: f44f 5300 mov.w r3, #8192 ; 0x2000
|
|
8007834: 63bb str r3, [r7, #56] ; 0x38
|
|
dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
|
|
8007836: 2380 movs r3, #128 ; 0x80
|
|
8007838: 63fb str r3, [r7, #60] ; 0x3c
|
|
dmainit.DescriptorSkipLength = 0x0;
|
|
800783a: 2300 movs r3, #0
|
|
800783c: 643b str r3, [r7, #64] ; 0x40
|
|
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
|
|
800783e: 2300 movs r3, #0
|
|
8007840: 647b str r3, [r7, #68] ; 0x44
|
|
|
|
/* Get the ETHERNET DMAOMR value */
|
|
tmpreg = (heth->Instance)->DMAOMR;
|
|
8007842: 687b ldr r3, [r7, #4]
|
|
8007844: 681a ldr r2, [r3, #0]
|
|
8007846: f241 0318 movw r3, #4120 ; 0x1018
|
|
800784a: 4413 add r3, r2
|
|
800784c: 681b ldr r3, [r3, #0]
|
|
800784e: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Clear xx bits */
|
|
tmpreg &= ETH_DMAOMR_CLEAR_MASK;
|
|
8007852: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007856: 4b3d ldr r3, [pc, #244] ; (800794c <ETH_MACDMAConfig+0x38c>)
|
|
8007858: 4013 ands r3, r2
|
|
800785a: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
/* Set the TTC bit according to ETH TransmitThresholdControl value */
|
|
/* Set the FEF bit according to ETH ForwardErrorFrames value */
|
|
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
|
|
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
|
|
/* Set the OSF bit according to ETH SecondFrameOperate value */
|
|
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
|
|
800785e: 68ba ldr r2, [r7, #8]
|
|
dmainit.ReceiveStoreForward |
|
|
8007860: 68fb ldr r3, [r7, #12]
|
|
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
|
|
8007862: 431a orrs r2, r3
|
|
dmainit.FlushReceivedFrame |
|
|
8007864: 693b ldr r3, [r7, #16]
|
|
dmainit.ReceiveStoreForward |
|
|
8007866: 431a orrs r2, r3
|
|
dmainit.TransmitStoreForward |
|
|
8007868: 697b ldr r3, [r7, #20]
|
|
dmainit.FlushReceivedFrame |
|
|
800786a: 431a orrs r2, r3
|
|
dmainit.TransmitThresholdControl |
|
|
800786c: 69bb ldr r3, [r7, #24]
|
|
dmainit.TransmitStoreForward |
|
|
800786e: 431a orrs r2, r3
|
|
dmainit.ForwardErrorFrames |
|
|
8007870: 69fb ldr r3, [r7, #28]
|
|
dmainit.TransmitThresholdControl |
|
|
8007872: 431a orrs r2, r3
|
|
dmainit.ForwardUndersizedGoodFrames |
|
|
8007874: 6a3b ldr r3, [r7, #32]
|
|
dmainit.ForwardErrorFrames |
|
|
8007876: 431a orrs r2, r3
|
|
dmainit.ReceiveThresholdControl |
|
|
8007878: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
dmainit.ForwardUndersizedGoodFrames |
|
|
800787a: 431a orrs r2, r3
|
|
dmainit.SecondFrameOperate);
|
|
800787c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
dmainit.ReceiveThresholdControl |
|
|
800787e: 4313 orrs r3, r2
|
|
tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
|
|
8007880: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007884: 4313 orrs r3, r2
|
|
8007886: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
|
|
/* Write to ETHERNET DMAOMR */
|
|
(heth->Instance)->DMAOMR = (uint32_t)tmpreg;
|
|
800788a: 687b ldr r3, [r7, #4]
|
|
800788c: 681a ldr r2, [r3, #0]
|
|
800788e: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007892: 4413 add r3, r2
|
|
8007894: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
8007898: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->DMAOMR;
|
|
800789a: 687b ldr r3, [r7, #4]
|
|
800789c: 681a ldr r2, [r3, #0]
|
|
800789e: f241 0318 movw r3, #4120 ; 0x1018
|
|
80078a2: 4413 add r3, r2
|
|
80078a4: 681b ldr r3, [r3, #0]
|
|
80078a6: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80078aa: 2001 movs r0, #1
|
|
80078ac: f7fd fd24 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->DMAOMR = tmpreg;
|
|
80078b0: 687b ldr r3, [r7, #4]
|
|
80078b2: 681a ldr r2, [r3, #0]
|
|
80078b4: f241 0318 movw r3, #4120 ; 0x1018
|
|
80078b8: 4413 add r3, r2
|
|
80078ba: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
80078be: 601a str r2, [r3, #0]
|
|
/* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
|
|
/* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
|
|
/* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
|
|
/* Set the DSL bit according to ETH DesciptorSkipLength value */
|
|
/* Set the PR and DA bits according to ETH DMAArbitration value */
|
|
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
|
|
80078c0: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
dmainit.FixedBurst |
|
|
80078c2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
|
|
80078c4: 431a orrs r2, r3
|
|
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
|
80078c6: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
dmainit.FixedBurst |
|
|
80078c8: 431a orrs r2, r3
|
|
dmainit.TxDMABurstLength |
|
|
80078ca: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
|
|
80078cc: 431a orrs r2, r3
|
|
dmainit.EnhancedDescriptorFormat |
|
|
80078ce: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
dmainit.TxDMABurstLength |
|
|
80078d0: 431a orrs r2, r3
|
|
(dmainit.DescriptorSkipLength << 2) |
|
|
80078d2: 6c3b ldr r3, [r7, #64] ; 0x40
|
|
80078d4: 009b lsls r3, r3, #2
|
|
dmainit.EnhancedDescriptorFormat |
|
|
80078d6: 431a orrs r2, r3
|
|
dmainit.DMAArbitration |
|
|
80078d8: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
(dmainit.DescriptorSkipLength << 2) |
|
|
80078da: 431a orrs r2, r3
|
|
(heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
|
|
80078dc: 687b ldr r3, [r7, #4]
|
|
80078de: 681b ldr r3, [r3, #0]
|
|
80078e0: f442 0200 orr.w r2, r2, #8388608 ; 0x800000
|
|
80078e4: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
80078e8: 601a str r2, [r3, #0]
|
|
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->DMABMR;
|
|
80078ea: 687b ldr r3, [r7, #4]
|
|
80078ec: 681b ldr r3, [r3, #0]
|
|
80078ee: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
80078f2: 681b ldr r3, [r3, #0]
|
|
80078f4: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80078f8: 2001 movs r0, #1
|
|
80078fa: f7fd fcfd bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->DMABMR = tmpreg;
|
|
80078fe: 687b ldr r3, [r7, #4]
|
|
8007900: 681b ldr r3, [r3, #0]
|
|
8007902: f503 5380 add.w r3, r3, #4096 ; 0x1000
|
|
8007906: f8d7 20bc ldr.w r2, [r7, #188] ; 0xbc
|
|
800790a: 601a str r2, [r3, #0]
|
|
|
|
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
|
|
800790c: 687b ldr r3, [r7, #4]
|
|
800790e: 699b ldr r3, [r3, #24]
|
|
8007910: 2b01 cmp r3, #1
|
|
8007912: d10d bne.n 8007930 <ETH_MACDMAConfig+0x370>
|
|
{
|
|
/* Enable the Ethernet Rx Interrupt */
|
|
__HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
|
|
8007914: 687b ldr r3, [r7, #4]
|
|
8007916: 681a ldr r2, [r3, #0]
|
|
8007918: f241 031c movw r3, #4124 ; 0x101c
|
|
800791c: 4413 add r3, r2
|
|
800791e: 681b ldr r3, [r3, #0]
|
|
8007920: 687a ldr r2, [r7, #4]
|
|
8007922: 6811 ldr r1, [r2, #0]
|
|
8007924: 4a0a ldr r2, [pc, #40] ; (8007950 <ETH_MACDMAConfig+0x390>)
|
|
8007926: 431a orrs r2, r3
|
|
8007928: f241 031c movw r3, #4124 ; 0x101c
|
|
800792c: 440b add r3, r1
|
|
800792e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialize MAC address in ethernet MAC */
|
|
ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
|
|
8007930: 687b ldr r3, [r7, #4]
|
|
8007932: 695b ldr r3, [r3, #20]
|
|
8007934: 461a mov r2, r3
|
|
8007936: 2100 movs r1, #0
|
|
8007938: 6878 ldr r0, [r7, #4]
|
|
800793a: f000 f80b bl 8007954 <ETH_MACAddressConfig>
|
|
}
|
|
800793e: bf00 nop
|
|
8007940: 37c0 adds r7, #192 ; 0xc0
|
|
8007942: 46bd mov sp, r7
|
|
8007944: bd80 pop {r7, pc}
|
|
8007946: bf00 nop
|
|
8007948: ff20810f .word 0xff20810f
|
|
800794c: f8de3f23 .word 0xf8de3f23
|
|
8007950: 00010040 .word 0x00010040
|
|
|
|
08007954 <ETH_MACAddressConfig>:
|
|
* @arg ETH_MAC_Address3: MAC Address3
|
|
* @param Addr Pointer to MAC address buffer data (6 bytes)
|
|
* @retval HAL status
|
|
*/
|
|
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
|
|
{
|
|
8007954: b480 push {r7}
|
|
8007956: b087 sub sp, #28
|
|
8007958: af00 add r7, sp, #0
|
|
800795a: 60f8 str r0, [r7, #12]
|
|
800795c: 60b9 str r1, [r7, #8]
|
|
800795e: 607a str r2, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
|
|
|
|
/* Calculate the selected MAC address high register */
|
|
tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
|
|
8007960: 687b ldr r3, [r7, #4]
|
|
8007962: 3305 adds r3, #5
|
|
8007964: 781b ldrb r3, [r3, #0]
|
|
8007966: 021b lsls r3, r3, #8
|
|
8007968: 687a ldr r2, [r7, #4]
|
|
800796a: 3204 adds r2, #4
|
|
800796c: 7812 ldrb r2, [r2, #0]
|
|
800796e: 4313 orrs r3, r2
|
|
8007970: 617b str r3, [r7, #20]
|
|
/* Load the selected MAC address high register */
|
|
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
|
|
8007972: 68ba ldr r2, [r7, #8]
|
|
8007974: 4b11 ldr r3, [pc, #68] ; (80079bc <ETH_MACAddressConfig+0x68>)
|
|
8007976: 4413 add r3, r2
|
|
8007978: 461a mov r2, r3
|
|
800797a: 697b ldr r3, [r7, #20]
|
|
800797c: 6013 str r3, [r2, #0]
|
|
/* Calculate the selected MAC address low register */
|
|
tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
|
|
800797e: 687b ldr r3, [r7, #4]
|
|
8007980: 3303 adds r3, #3
|
|
8007982: 781b ldrb r3, [r3, #0]
|
|
8007984: 061a lsls r2, r3, #24
|
|
8007986: 687b ldr r3, [r7, #4]
|
|
8007988: 3302 adds r3, #2
|
|
800798a: 781b ldrb r3, [r3, #0]
|
|
800798c: 041b lsls r3, r3, #16
|
|
800798e: 431a orrs r2, r3
|
|
8007990: 687b ldr r3, [r7, #4]
|
|
8007992: 3301 adds r3, #1
|
|
8007994: 781b ldrb r3, [r3, #0]
|
|
8007996: 021b lsls r3, r3, #8
|
|
8007998: 4313 orrs r3, r2
|
|
800799a: 687a ldr r2, [r7, #4]
|
|
800799c: 7812 ldrb r2, [r2, #0]
|
|
800799e: 4313 orrs r3, r2
|
|
80079a0: 617b str r3, [r7, #20]
|
|
|
|
/* Load the selected MAC address low register */
|
|
(*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
|
|
80079a2: 68ba ldr r2, [r7, #8]
|
|
80079a4: 4b06 ldr r3, [pc, #24] ; (80079c0 <ETH_MACAddressConfig+0x6c>)
|
|
80079a6: 4413 add r3, r2
|
|
80079a8: 461a mov r2, r3
|
|
80079aa: 697b ldr r3, [r7, #20]
|
|
80079ac: 6013 str r3, [r2, #0]
|
|
}
|
|
80079ae: bf00 nop
|
|
80079b0: 371c adds r7, #28
|
|
80079b2: 46bd mov sp, r7
|
|
80079b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80079b8: 4770 bx lr
|
|
80079ba: bf00 nop
|
|
80079bc: 40028040 .word 0x40028040
|
|
80079c0: 40028044 .word 0x40028044
|
|
|
|
080079c4 <ETH_MACTransmissionEnable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
|
|
{
|
|
80079c4: b580 push {r7, lr}
|
|
80079c6: b084 sub sp, #16
|
|
80079c8: af00 add r7, sp, #0
|
|
80079ca: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg = 0;
|
|
80079cc: 2300 movs r3, #0
|
|
80079ce: 60fb str r3, [r7, #12]
|
|
|
|
/* Enable the MAC transmission */
|
|
(heth->Instance)->MACCR |= ETH_MACCR_TE;
|
|
80079d0: 687b ldr r3, [r7, #4]
|
|
80079d2: 681b ldr r3, [r3, #0]
|
|
80079d4: 681a ldr r2, [r3, #0]
|
|
80079d6: 687b ldr r3, [r7, #4]
|
|
80079d8: 681b ldr r3, [r3, #0]
|
|
80079da: f042 0208 orr.w r2, r2, #8
|
|
80079de: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
80079e0: 687b ldr r3, [r7, #4]
|
|
80079e2: 681b ldr r3, [r3, #0]
|
|
80079e4: 681b ldr r3, [r3, #0]
|
|
80079e6: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
80079e8: 2001 movs r0, #1
|
|
80079ea: f7fd fc85 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
80079ee: 687b ldr r3, [r7, #4]
|
|
80079f0: 681b ldr r3, [r3, #0]
|
|
80079f2: 68fa ldr r2, [r7, #12]
|
|
80079f4: 601a str r2, [r3, #0]
|
|
}
|
|
80079f6: bf00 nop
|
|
80079f8: 3710 adds r7, #16
|
|
80079fa: 46bd mov sp, r7
|
|
80079fc: bd80 pop {r7, pc}
|
|
|
|
080079fe <ETH_MACTransmissionDisable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
|
|
{
|
|
80079fe: b580 push {r7, lr}
|
|
8007a00: b084 sub sp, #16
|
|
8007a02: af00 add r7, sp, #0
|
|
8007a04: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg = 0;
|
|
8007a06: 2300 movs r3, #0
|
|
8007a08: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable the MAC transmission */
|
|
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
|
|
8007a0a: 687b ldr r3, [r7, #4]
|
|
8007a0c: 681b ldr r3, [r3, #0]
|
|
8007a0e: 681a ldr r2, [r3, #0]
|
|
8007a10: 687b ldr r3, [r7, #4]
|
|
8007a12: 681b ldr r3, [r3, #0]
|
|
8007a14: f022 0208 bic.w r2, r2, #8
|
|
8007a18: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
8007a1a: 687b ldr r3, [r7, #4]
|
|
8007a1c: 681b ldr r3, [r3, #0]
|
|
8007a1e: 681b ldr r3, [r3, #0]
|
|
8007a20: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007a22: 2001 movs r0, #1
|
|
8007a24: f7fd fc68 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
8007a28: 687b ldr r3, [r7, #4]
|
|
8007a2a: 681b ldr r3, [r3, #0]
|
|
8007a2c: 68fa ldr r2, [r7, #12]
|
|
8007a2e: 601a str r2, [r3, #0]
|
|
}
|
|
8007a30: bf00 nop
|
|
8007a32: 3710 adds r7, #16
|
|
8007a34: 46bd mov sp, r7
|
|
8007a36: bd80 pop {r7, pc}
|
|
|
|
08007a38 <ETH_MACReceptionEnable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007a38: b580 push {r7, lr}
|
|
8007a3a: b084 sub sp, #16
|
|
8007a3c: af00 add r7, sp, #0
|
|
8007a3e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg = 0;
|
|
8007a40: 2300 movs r3, #0
|
|
8007a42: 60fb str r3, [r7, #12]
|
|
|
|
/* Enable the MAC reception */
|
|
(heth->Instance)->MACCR |= ETH_MACCR_RE;
|
|
8007a44: 687b ldr r3, [r7, #4]
|
|
8007a46: 681b ldr r3, [r3, #0]
|
|
8007a48: 681a ldr r2, [r3, #0]
|
|
8007a4a: 687b ldr r3, [r7, #4]
|
|
8007a4c: 681b ldr r3, [r3, #0]
|
|
8007a4e: f042 0204 orr.w r2, r2, #4
|
|
8007a52: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
8007a54: 687b ldr r3, [r7, #4]
|
|
8007a56: 681b ldr r3, [r3, #0]
|
|
8007a58: 681b ldr r3, [r3, #0]
|
|
8007a5a: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007a5c: 2001 movs r0, #1
|
|
8007a5e: f7fd fc4b bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
8007a62: 687b ldr r3, [r7, #4]
|
|
8007a64: 681b ldr r3, [r3, #0]
|
|
8007a66: 68fa ldr r2, [r7, #12]
|
|
8007a68: 601a str r2, [r3, #0]
|
|
}
|
|
8007a6a: bf00 nop
|
|
8007a6c: 3710 adds r7, #16
|
|
8007a6e: 46bd mov sp, r7
|
|
8007a70: bd80 pop {r7, pc}
|
|
|
|
08007a72 <ETH_MACReceptionDisable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007a72: b580 push {r7, lr}
|
|
8007a74: b084 sub sp, #16
|
|
8007a76: af00 add r7, sp, #0
|
|
8007a78: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg = 0;
|
|
8007a7a: 2300 movs r3, #0
|
|
8007a7c: 60fb str r3, [r7, #12]
|
|
|
|
/* Disable the MAC reception */
|
|
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
|
|
8007a7e: 687b ldr r3, [r7, #4]
|
|
8007a80: 681b ldr r3, [r3, #0]
|
|
8007a82: 681a ldr r2, [r3, #0]
|
|
8007a84: 687b ldr r3, [r7, #4]
|
|
8007a86: 681b ldr r3, [r3, #0]
|
|
8007a88: f022 0204 bic.w r2, r2, #4
|
|
8007a8c: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->MACCR;
|
|
8007a8e: 687b ldr r3, [r7, #4]
|
|
8007a90: 681b ldr r3, [r3, #0]
|
|
8007a92: 681b ldr r3, [r3, #0]
|
|
8007a94: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007a96: 2001 movs r0, #1
|
|
8007a98: f7fd fc2e bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->MACCR = tmpreg;
|
|
8007a9c: 687b ldr r3, [r7, #4]
|
|
8007a9e: 681b ldr r3, [r3, #0]
|
|
8007aa0: 68fa ldr r2, [r7, #12]
|
|
8007aa2: 601a str r2, [r3, #0]
|
|
}
|
|
8007aa4: bf00 nop
|
|
8007aa6: 3710 adds r7, #16
|
|
8007aa8: 46bd mov sp, r7
|
|
8007aaa: bd80 pop {r7, pc}
|
|
|
|
08007aac <ETH_DMATransmissionEnable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007aac: b480 push {r7}
|
|
8007aae: b083 sub sp, #12
|
|
8007ab0: af00 add r7, sp, #0
|
|
8007ab2: 6078 str r0, [r7, #4]
|
|
/* Enable the DMA transmission */
|
|
(heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
|
|
8007ab4: 687b ldr r3, [r7, #4]
|
|
8007ab6: 681a ldr r2, [r3, #0]
|
|
8007ab8: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007abc: 4413 add r3, r2
|
|
8007abe: 681b ldr r3, [r3, #0]
|
|
8007ac0: 687a ldr r2, [r7, #4]
|
|
8007ac2: 6811 ldr r1, [r2, #0]
|
|
8007ac4: f443 5200 orr.w r2, r3, #8192 ; 0x2000
|
|
8007ac8: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007acc: 440b add r3, r1
|
|
8007ace: 601a str r2, [r3, #0]
|
|
}
|
|
8007ad0: bf00 nop
|
|
8007ad2: 370c adds r7, #12
|
|
8007ad4: 46bd mov sp, r7
|
|
8007ad6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ada: 4770 bx lr
|
|
|
|
08007adc <ETH_DMATransmissionDisable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007adc: b480 push {r7}
|
|
8007ade: b083 sub sp, #12
|
|
8007ae0: af00 add r7, sp, #0
|
|
8007ae2: 6078 str r0, [r7, #4]
|
|
/* Disable the DMA transmission */
|
|
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
|
|
8007ae4: 687b ldr r3, [r7, #4]
|
|
8007ae6: 681a ldr r2, [r3, #0]
|
|
8007ae8: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007aec: 4413 add r3, r2
|
|
8007aee: 681b ldr r3, [r3, #0]
|
|
8007af0: 687a ldr r2, [r7, #4]
|
|
8007af2: 6811 ldr r1, [r2, #0]
|
|
8007af4: f423 5200 bic.w r2, r3, #8192 ; 0x2000
|
|
8007af8: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007afc: 440b add r3, r1
|
|
8007afe: 601a str r2, [r3, #0]
|
|
}
|
|
8007b00: bf00 nop
|
|
8007b02: 370c adds r7, #12
|
|
8007b04: 46bd mov sp, r7
|
|
8007b06: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b0a: 4770 bx lr
|
|
|
|
08007b0c <ETH_DMAReceptionEnable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007b0c: b480 push {r7}
|
|
8007b0e: b083 sub sp, #12
|
|
8007b10: af00 add r7, sp, #0
|
|
8007b12: 6078 str r0, [r7, #4]
|
|
/* Enable the DMA reception */
|
|
(heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
|
|
8007b14: 687b ldr r3, [r7, #4]
|
|
8007b16: 681a ldr r2, [r3, #0]
|
|
8007b18: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b1c: 4413 add r3, r2
|
|
8007b1e: 681b ldr r3, [r3, #0]
|
|
8007b20: 687a ldr r2, [r7, #4]
|
|
8007b22: 6811 ldr r1, [r2, #0]
|
|
8007b24: f043 0202 orr.w r2, r3, #2
|
|
8007b28: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b2c: 440b add r3, r1
|
|
8007b2e: 601a str r2, [r3, #0]
|
|
}
|
|
8007b30: bf00 nop
|
|
8007b32: 370c adds r7, #12
|
|
8007b34: 46bd mov sp, r7
|
|
8007b36: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b3a: 4770 bx lr
|
|
|
|
08007b3c <ETH_DMAReceptionDisable>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007b3c: b480 push {r7}
|
|
8007b3e: b083 sub sp, #12
|
|
8007b40: af00 add r7, sp, #0
|
|
8007b42: 6078 str r0, [r7, #4]
|
|
/* Disable the DMA reception */
|
|
(heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
|
|
8007b44: 687b ldr r3, [r7, #4]
|
|
8007b46: 681a ldr r2, [r3, #0]
|
|
8007b48: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b4c: 4413 add r3, r2
|
|
8007b4e: 681b ldr r3, [r3, #0]
|
|
8007b50: 687a ldr r2, [r7, #4]
|
|
8007b52: 6811 ldr r1, [r2, #0]
|
|
8007b54: f023 0202 bic.w r2, r3, #2
|
|
8007b58: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b5c: 440b add r3, r1
|
|
8007b5e: 601a str r2, [r3, #0]
|
|
}
|
|
8007b60: bf00 nop
|
|
8007b62: 370c adds r7, #12
|
|
8007b64: 46bd mov sp, r7
|
|
8007b66: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b6a: 4770 bx lr
|
|
|
|
08007b6c <ETH_FlushTransmitFIFO>:
|
|
* @param heth pointer to a ETH_HandleTypeDef structure that contains
|
|
* the configuration information for ETHERNET module
|
|
* @retval None
|
|
*/
|
|
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
|
|
{
|
|
8007b6c: b580 push {r7, lr}
|
|
8007b6e: b084 sub sp, #16
|
|
8007b70: af00 add r7, sp, #0
|
|
8007b72: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tmpreg = 0;
|
|
8007b74: 2300 movs r3, #0
|
|
8007b76: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Flush Transmit FIFO bit */
|
|
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
|
|
8007b78: 687b ldr r3, [r7, #4]
|
|
8007b7a: 681a ldr r2, [r3, #0]
|
|
8007b7c: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b80: 4413 add r3, r2
|
|
8007b82: 681b ldr r3, [r3, #0]
|
|
8007b84: 687a ldr r2, [r7, #4]
|
|
8007b86: 6811 ldr r1, [r2, #0]
|
|
8007b88: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
|
|
8007b8c: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b90: 440b add r3, r1
|
|
8007b92: 601a str r2, [r3, #0]
|
|
|
|
/* Wait until the write operation will be taken into account:
|
|
at least four TX_CLK/RX_CLK clock cycles */
|
|
tmpreg = (heth->Instance)->DMAOMR;
|
|
8007b94: 687b ldr r3, [r7, #4]
|
|
8007b96: 681a ldr r2, [r3, #0]
|
|
8007b98: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007b9c: 4413 add r3, r2
|
|
8007b9e: 681b ldr r3, [r3, #0]
|
|
8007ba0: 60fb str r3, [r7, #12]
|
|
HAL_Delay(ETH_REG_WRITE_DELAY);
|
|
8007ba2: 2001 movs r0, #1
|
|
8007ba4: f7fd fba8 bl 80052f8 <HAL_Delay>
|
|
(heth->Instance)->DMAOMR = tmpreg;
|
|
8007ba8: 687b ldr r3, [r7, #4]
|
|
8007baa: 6819 ldr r1, [r3, #0]
|
|
8007bac: 68fa ldr r2, [r7, #12]
|
|
8007bae: f241 0318 movw r3, #4120 ; 0x1018
|
|
8007bb2: 440b add r3, r1
|
|
8007bb4: 601a str r2, [r3, #0]
|
|
}
|
|
8007bb6: bf00 nop
|
|
8007bb8: 3710 adds r7, #16
|
|
8007bba: 46bd mov sp, r7
|
|
8007bbc: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007bc0 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8007bc0: b480 push {r7}
|
|
8007bc2: b089 sub sp, #36 ; 0x24
|
|
8007bc4: af00 add r7, sp, #0
|
|
8007bc6: 6078 str r0, [r7, #4]
|
|
8007bc8: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00;
|
|
8007bca: 2300 movs r3, #0
|
|
8007bcc: 61fb str r3, [r7, #28]
|
|
uint32_t ioposition = 0x00;
|
|
8007bce: 2300 movs r3, #0
|
|
8007bd0: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00;
|
|
8007bd2: 2300 movs r3, #0
|
|
8007bd4: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00;
|
|
8007bd6: 2300 movs r3, #0
|
|
8007bd8: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0; position < GPIO_NUMBER; position++)
|
|
8007bda: 2300 movs r3, #0
|
|
8007bdc: 61fb str r3, [r7, #28]
|
|
8007bde: e175 b.n 8007ecc <HAL_GPIO_Init+0x30c>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = ((uint32_t)0x01) << position;
|
|
8007be0: 2201 movs r2, #1
|
|
8007be2: 69fb ldr r3, [r7, #28]
|
|
8007be4: fa02 f303 lsl.w r3, r2, r3
|
|
8007be8: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8007bea: 683b ldr r3, [r7, #0]
|
|
8007bec: 681b ldr r3, [r3, #0]
|
|
8007bee: 697a ldr r2, [r7, #20]
|
|
8007bf0: 4013 ands r3, r2
|
|
8007bf2: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
8007bf4: 693a ldr r2, [r7, #16]
|
|
8007bf6: 697b ldr r3, [r7, #20]
|
|
8007bf8: 429a cmp r2, r3
|
|
8007bfa: f040 8164 bne.w 8007ec6 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8007bfe: 683b ldr r3, [r7, #0]
|
|
8007c00: 685b ldr r3, [r3, #4]
|
|
8007c02: 2b01 cmp r3, #1
|
|
8007c04: d00b beq.n 8007c1e <HAL_GPIO_Init+0x5e>
|
|
8007c06: 683b ldr r3, [r7, #0]
|
|
8007c08: 685b ldr r3, [r3, #4]
|
|
8007c0a: 2b02 cmp r3, #2
|
|
8007c0c: d007 beq.n 8007c1e <HAL_GPIO_Init+0x5e>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8007c0e: 683b ldr r3, [r7, #0]
|
|
8007c10: 685b ldr r3, [r3, #4]
|
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8007c12: 2b11 cmp r3, #17
|
|
8007c14: d003 beq.n 8007c1e <HAL_GPIO_Init+0x5e>
|
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8007c16: 683b ldr r3, [r7, #0]
|
|
8007c18: 685b ldr r3, [r3, #4]
|
|
8007c1a: 2b12 cmp r3, #18
|
|
8007c1c: d130 bne.n 8007c80 <HAL_GPIO_Init+0xc0>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8007c1e: 687b ldr r3, [r7, #4]
|
|
8007c20: 689b ldr r3, [r3, #8]
|
|
8007c22: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
|
8007c24: 69fb ldr r3, [r7, #28]
|
|
8007c26: 005b lsls r3, r3, #1
|
|
8007c28: 2203 movs r2, #3
|
|
8007c2a: fa02 f303 lsl.w r3, r2, r3
|
|
8007c2e: 43db mvns r3, r3
|
|
8007c30: 69ba ldr r2, [r7, #24]
|
|
8007c32: 4013 ands r3, r2
|
|
8007c34: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2));
|
|
8007c36: 683b ldr r3, [r7, #0]
|
|
8007c38: 68da ldr r2, [r3, #12]
|
|
8007c3a: 69fb ldr r3, [r7, #28]
|
|
8007c3c: 005b lsls r3, r3, #1
|
|
8007c3e: fa02 f303 lsl.w r3, r2, r3
|
|
8007c42: 69ba ldr r2, [r7, #24]
|
|
8007c44: 4313 orrs r3, r2
|
|
8007c46: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8007c48: 687b ldr r3, [r7, #4]
|
|
8007c4a: 69ba ldr r2, [r7, #24]
|
|
8007c4c: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8007c4e: 687b ldr r3, [r7, #4]
|
|
8007c50: 685b ldr r3, [r3, #4]
|
|
8007c52: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8007c54: 2201 movs r2, #1
|
|
8007c56: 69fb ldr r3, [r7, #28]
|
|
8007c58: fa02 f303 lsl.w r3, r2, r3
|
|
8007c5c: 43db mvns r3, r3
|
|
8007c5e: 69ba ldr r2, [r7, #24]
|
|
8007c60: 4013 ands r3, r2
|
|
8007c62: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
|
|
8007c64: 683b ldr r3, [r7, #0]
|
|
8007c66: 685b ldr r3, [r3, #4]
|
|
8007c68: 091b lsrs r3, r3, #4
|
|
8007c6a: f003 0201 and.w r2, r3, #1
|
|
8007c6e: 69fb ldr r3, [r7, #28]
|
|
8007c70: fa02 f303 lsl.w r3, r2, r3
|
|
8007c74: 69ba ldr r2, [r7, #24]
|
|
8007c76: 4313 orrs r3, r2
|
|
8007c78: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8007c7a: 687b ldr r3, [r7, #4]
|
|
8007c7c: 69ba ldr r2, [r7, #24]
|
|
8007c7e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8007c80: 687b ldr r3, [r7, #4]
|
|
8007c82: 68db ldr r3, [r3, #12]
|
|
8007c84: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
|
8007c86: 69fb ldr r3, [r7, #28]
|
|
8007c88: 005b lsls r3, r3, #1
|
|
8007c8a: 2203 movs r2, #3
|
|
8007c8c: fa02 f303 lsl.w r3, r2, r3
|
|
8007c90: 43db mvns r3, r3
|
|
8007c92: 69ba ldr r2, [r7, #24]
|
|
8007c94: 4013 ands r3, r2
|
|
8007c96: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2));
|
|
8007c98: 683b ldr r3, [r7, #0]
|
|
8007c9a: 689a ldr r2, [r3, #8]
|
|
8007c9c: 69fb ldr r3, [r7, #28]
|
|
8007c9e: 005b lsls r3, r3, #1
|
|
8007ca0: fa02 f303 lsl.w r3, r2, r3
|
|
8007ca4: 69ba ldr r2, [r7, #24]
|
|
8007ca6: 4313 orrs r3, r2
|
|
8007ca8: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
8007caa: 687b ldr r3, [r7, #4]
|
|
8007cac: 69ba ldr r2, [r7, #24]
|
|
8007cae: 60da str r2, [r3, #12]
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
8007cb0: 683b ldr r3, [r7, #0]
|
|
8007cb2: 685b ldr r3, [r3, #4]
|
|
8007cb4: 2b02 cmp r3, #2
|
|
8007cb6: d003 beq.n 8007cc0 <HAL_GPIO_Init+0x100>
|
|
8007cb8: 683b ldr r3, [r7, #0]
|
|
8007cba: 685b ldr r3, [r3, #4]
|
|
8007cbc: 2b12 cmp r3, #18
|
|
8007cbe: d123 bne.n 8007d08 <HAL_GPIO_Init+0x148>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3];
|
|
8007cc0: 69fb ldr r3, [r7, #28]
|
|
8007cc2: 08da lsrs r2, r3, #3
|
|
8007cc4: 687b ldr r3, [r7, #4]
|
|
8007cc6: 3208 adds r2, #8
|
|
8007cc8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8007ccc: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
|
8007cce: 69fb ldr r3, [r7, #28]
|
|
8007cd0: f003 0307 and.w r3, r3, #7
|
|
8007cd4: 009b lsls r3, r3, #2
|
|
8007cd6: 220f movs r2, #15
|
|
8007cd8: fa02 f303 lsl.w r3, r2, r3
|
|
8007cdc: 43db mvns r3, r3
|
|
8007cde: 69ba ldr r2, [r7, #24]
|
|
8007ce0: 4013 ands r3, r2
|
|
8007ce2: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
|
|
8007ce4: 683b ldr r3, [r7, #0]
|
|
8007ce6: 691a ldr r2, [r3, #16]
|
|
8007ce8: 69fb ldr r3, [r7, #28]
|
|
8007cea: f003 0307 and.w r3, r3, #7
|
|
8007cee: 009b lsls r3, r3, #2
|
|
8007cf0: fa02 f303 lsl.w r3, r2, r3
|
|
8007cf4: 69ba ldr r2, [r7, #24]
|
|
8007cf6: 4313 orrs r3, r2
|
|
8007cf8: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3] = temp;
|
|
8007cfa: 69fb ldr r3, [r7, #28]
|
|
8007cfc: 08da lsrs r2, r3, #3
|
|
8007cfe: 687b ldr r3, [r7, #4]
|
|
8007d00: 3208 adds r2, #8
|
|
8007d02: 69b9 ldr r1, [r7, #24]
|
|
8007d04: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8007d08: 687b ldr r3, [r7, #4]
|
|
8007d0a: 681b ldr r3, [r3, #0]
|
|
8007d0c: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
|
|
8007d0e: 69fb ldr r3, [r7, #28]
|
|
8007d10: 005b lsls r3, r3, #1
|
|
8007d12: 2203 movs r2, #3
|
|
8007d14: fa02 f303 lsl.w r3, r2, r3
|
|
8007d18: 43db mvns r3, r3
|
|
8007d1a: 69ba ldr r2, [r7, #24]
|
|
8007d1c: 4013 ands r3, r2
|
|
8007d1e: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
|
8007d20: 683b ldr r3, [r7, #0]
|
|
8007d22: 685b ldr r3, [r3, #4]
|
|
8007d24: f003 0203 and.w r2, r3, #3
|
|
8007d28: 69fb ldr r3, [r7, #28]
|
|
8007d2a: 005b lsls r3, r3, #1
|
|
8007d2c: fa02 f303 lsl.w r3, r2, r3
|
|
8007d30: 69ba ldr r2, [r7, #24]
|
|
8007d32: 4313 orrs r3, r2
|
|
8007d34: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8007d36: 687b ldr r3, [r7, #4]
|
|
8007d38: 69ba ldr r2, [r7, #24]
|
|
8007d3a: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
8007d3c: 683b ldr r3, [r7, #0]
|
|
8007d3e: 685b ldr r3, [r3, #4]
|
|
8007d40: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8007d44: 2b00 cmp r3, #0
|
|
8007d46: f000 80be beq.w 8007ec6 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8007d4a: 4b65 ldr r3, [pc, #404] ; (8007ee0 <HAL_GPIO_Init+0x320>)
|
|
8007d4c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8007d4e: 4a64 ldr r2, [pc, #400] ; (8007ee0 <HAL_GPIO_Init+0x320>)
|
|
8007d50: f443 4380 orr.w r3, r3, #16384 ; 0x4000
|
|
8007d54: 6453 str r3, [r2, #68] ; 0x44
|
|
8007d56: 4b62 ldr r3, [pc, #392] ; (8007ee0 <HAL_GPIO_Init+0x320>)
|
|
8007d58: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8007d5a: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
8007d5e: 60fb str r3, [r7, #12]
|
|
8007d60: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2];
|
|
8007d62: 4a60 ldr r2, [pc, #384] ; (8007ee4 <HAL_GPIO_Init+0x324>)
|
|
8007d64: 69fb ldr r3, [r7, #28]
|
|
8007d66: 089b lsrs r3, r3, #2
|
|
8007d68: 3302 adds r3, #2
|
|
8007d6a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8007d6e: 61bb str r3, [r7, #24]
|
|
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
|
|
8007d70: 69fb ldr r3, [r7, #28]
|
|
8007d72: f003 0303 and.w r3, r3, #3
|
|
8007d76: 009b lsls r3, r3, #2
|
|
8007d78: 220f movs r2, #15
|
|
8007d7a: fa02 f303 lsl.w r3, r2, r3
|
|
8007d7e: 43db mvns r3, r3
|
|
8007d80: 69ba ldr r2, [r7, #24]
|
|
8007d82: 4013 ands r3, r2
|
|
8007d84: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
|
|
8007d86: 687b ldr r3, [r7, #4]
|
|
8007d88: 4a57 ldr r2, [pc, #348] ; (8007ee8 <HAL_GPIO_Init+0x328>)
|
|
8007d8a: 4293 cmp r3, r2
|
|
8007d8c: d037 beq.n 8007dfe <HAL_GPIO_Init+0x23e>
|
|
8007d8e: 687b ldr r3, [r7, #4]
|
|
8007d90: 4a56 ldr r2, [pc, #344] ; (8007eec <HAL_GPIO_Init+0x32c>)
|
|
8007d92: 4293 cmp r3, r2
|
|
8007d94: d031 beq.n 8007dfa <HAL_GPIO_Init+0x23a>
|
|
8007d96: 687b ldr r3, [r7, #4]
|
|
8007d98: 4a55 ldr r2, [pc, #340] ; (8007ef0 <HAL_GPIO_Init+0x330>)
|
|
8007d9a: 4293 cmp r3, r2
|
|
8007d9c: d02b beq.n 8007df6 <HAL_GPIO_Init+0x236>
|
|
8007d9e: 687b ldr r3, [r7, #4]
|
|
8007da0: 4a54 ldr r2, [pc, #336] ; (8007ef4 <HAL_GPIO_Init+0x334>)
|
|
8007da2: 4293 cmp r3, r2
|
|
8007da4: d025 beq.n 8007df2 <HAL_GPIO_Init+0x232>
|
|
8007da6: 687b ldr r3, [r7, #4]
|
|
8007da8: 4a53 ldr r2, [pc, #332] ; (8007ef8 <HAL_GPIO_Init+0x338>)
|
|
8007daa: 4293 cmp r3, r2
|
|
8007dac: d01f beq.n 8007dee <HAL_GPIO_Init+0x22e>
|
|
8007dae: 687b ldr r3, [r7, #4]
|
|
8007db0: 4a52 ldr r2, [pc, #328] ; (8007efc <HAL_GPIO_Init+0x33c>)
|
|
8007db2: 4293 cmp r3, r2
|
|
8007db4: d019 beq.n 8007dea <HAL_GPIO_Init+0x22a>
|
|
8007db6: 687b ldr r3, [r7, #4]
|
|
8007db8: 4a51 ldr r2, [pc, #324] ; (8007f00 <HAL_GPIO_Init+0x340>)
|
|
8007dba: 4293 cmp r3, r2
|
|
8007dbc: d013 beq.n 8007de6 <HAL_GPIO_Init+0x226>
|
|
8007dbe: 687b ldr r3, [r7, #4]
|
|
8007dc0: 4a50 ldr r2, [pc, #320] ; (8007f04 <HAL_GPIO_Init+0x344>)
|
|
8007dc2: 4293 cmp r3, r2
|
|
8007dc4: d00d beq.n 8007de2 <HAL_GPIO_Init+0x222>
|
|
8007dc6: 687b ldr r3, [r7, #4]
|
|
8007dc8: 4a4f ldr r2, [pc, #316] ; (8007f08 <HAL_GPIO_Init+0x348>)
|
|
8007dca: 4293 cmp r3, r2
|
|
8007dcc: d007 beq.n 8007dde <HAL_GPIO_Init+0x21e>
|
|
8007dce: 687b ldr r3, [r7, #4]
|
|
8007dd0: 4a4e ldr r2, [pc, #312] ; (8007f0c <HAL_GPIO_Init+0x34c>)
|
|
8007dd2: 4293 cmp r3, r2
|
|
8007dd4: d101 bne.n 8007dda <HAL_GPIO_Init+0x21a>
|
|
8007dd6: 2309 movs r3, #9
|
|
8007dd8: e012 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dda: 230a movs r3, #10
|
|
8007ddc: e010 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dde: 2308 movs r3, #8
|
|
8007de0: e00e b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007de2: 2307 movs r3, #7
|
|
8007de4: e00c b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007de6: 2306 movs r3, #6
|
|
8007de8: e00a b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dea: 2305 movs r3, #5
|
|
8007dec: e008 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dee: 2304 movs r3, #4
|
|
8007df0: e006 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007df2: 2303 movs r3, #3
|
|
8007df4: e004 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007df6: 2302 movs r3, #2
|
|
8007df8: e002 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dfa: 2301 movs r3, #1
|
|
8007dfc: e000 b.n 8007e00 <HAL_GPIO_Init+0x240>
|
|
8007dfe: 2300 movs r3, #0
|
|
8007e00: 69fa ldr r2, [r7, #28]
|
|
8007e02: f002 0203 and.w r2, r2, #3
|
|
8007e06: 0092 lsls r2, r2, #2
|
|
8007e08: 4093 lsls r3, r2
|
|
8007e0a: 69ba ldr r2, [r7, #24]
|
|
8007e0c: 4313 orrs r3, r2
|
|
8007e0e: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2] = temp;
|
|
8007e10: 4934 ldr r1, [pc, #208] ; (8007ee4 <HAL_GPIO_Init+0x324>)
|
|
8007e12: 69fb ldr r3, [r7, #28]
|
|
8007e14: 089b lsrs r3, r3, #2
|
|
8007e16: 3302 adds r3, #2
|
|
8007e18: 69ba ldr r2, [r7, #24]
|
|
8007e1a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8007e1e: 4b3c ldr r3, [pc, #240] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e20: 681b ldr r3, [r3, #0]
|
|
8007e22: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8007e24: 693b ldr r3, [r7, #16]
|
|
8007e26: 43db mvns r3, r3
|
|
8007e28: 69ba ldr r2, [r7, #24]
|
|
8007e2a: 4013 ands r3, r2
|
|
8007e2c: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
8007e2e: 683b ldr r3, [r7, #0]
|
|
8007e30: 685b ldr r3, [r3, #4]
|
|
8007e32: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
8007e36: 2b00 cmp r3, #0
|
|
8007e38: d003 beq.n 8007e42 <HAL_GPIO_Init+0x282>
|
|
{
|
|
temp |= iocurrent;
|
|
8007e3a: 69ba ldr r2, [r7, #24]
|
|
8007e3c: 693b ldr r3, [r7, #16]
|
|
8007e3e: 4313 orrs r3, r2
|
|
8007e40: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8007e42: 4a33 ldr r2, [pc, #204] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e44: 69bb ldr r3, [r7, #24]
|
|
8007e46: 6013 str r3, [r2, #0]
|
|
|
|
temp = EXTI->EMR;
|
|
8007e48: 4b31 ldr r3, [pc, #196] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e4a: 685b ldr r3, [r3, #4]
|
|
8007e4c: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8007e4e: 693b ldr r3, [r7, #16]
|
|
8007e50: 43db mvns r3, r3
|
|
8007e52: 69ba ldr r2, [r7, #24]
|
|
8007e54: 4013 ands r3, r2
|
|
8007e56: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
8007e58: 683b ldr r3, [r7, #0]
|
|
8007e5a: 685b ldr r3, [r3, #4]
|
|
8007e5c: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8007e60: 2b00 cmp r3, #0
|
|
8007e62: d003 beq.n 8007e6c <HAL_GPIO_Init+0x2ac>
|
|
{
|
|
temp |= iocurrent;
|
|
8007e64: 69ba ldr r2, [r7, #24]
|
|
8007e66: 693b ldr r3, [r7, #16]
|
|
8007e68: 4313 orrs r3, r2
|
|
8007e6a: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8007e6c: 4a28 ldr r2, [pc, #160] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e6e: 69bb ldr r3, [r7, #24]
|
|
8007e70: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8007e72: 4b27 ldr r3, [pc, #156] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e74: 689b ldr r3, [r3, #8]
|
|
8007e76: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8007e78: 693b ldr r3, [r7, #16]
|
|
8007e7a: 43db mvns r3, r3
|
|
8007e7c: 69ba ldr r2, [r7, #24]
|
|
8007e7e: 4013 ands r3, r2
|
|
8007e80: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
8007e82: 683b ldr r3, [r7, #0]
|
|
8007e84: 685b ldr r3, [r3, #4]
|
|
8007e86: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8007e8a: 2b00 cmp r3, #0
|
|
8007e8c: d003 beq.n 8007e96 <HAL_GPIO_Init+0x2d6>
|
|
{
|
|
temp |= iocurrent;
|
|
8007e8e: 69ba ldr r2, [r7, #24]
|
|
8007e90: 693b ldr r3, [r7, #16]
|
|
8007e92: 4313 orrs r3, r2
|
|
8007e94: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8007e96: 4a1e ldr r2, [pc, #120] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e98: 69bb ldr r3, [r7, #24]
|
|
8007e9a: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8007e9c: 4b1c ldr r3, [pc, #112] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007e9e: 68db ldr r3, [r3, #12]
|
|
8007ea0: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8007ea2: 693b ldr r3, [r7, #16]
|
|
8007ea4: 43db mvns r3, r3
|
|
8007ea6: 69ba ldr r2, [r7, #24]
|
|
8007ea8: 4013 ands r3, r2
|
|
8007eaa: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
8007eac: 683b ldr r3, [r7, #0]
|
|
8007eae: 685b ldr r3, [r3, #4]
|
|
8007eb0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
8007eb4: 2b00 cmp r3, #0
|
|
8007eb6: d003 beq.n 8007ec0 <HAL_GPIO_Init+0x300>
|
|
{
|
|
temp |= iocurrent;
|
|
8007eb8: 69ba ldr r2, [r7, #24]
|
|
8007eba: 693b ldr r3, [r7, #16]
|
|
8007ebc: 4313 orrs r3, r2
|
|
8007ebe: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8007ec0: 4a13 ldr r2, [pc, #76] ; (8007f10 <HAL_GPIO_Init+0x350>)
|
|
8007ec2: 69bb ldr r3, [r7, #24]
|
|
8007ec4: 60d3 str r3, [r2, #12]
|
|
for(position = 0; position < GPIO_NUMBER; position++)
|
|
8007ec6: 69fb ldr r3, [r7, #28]
|
|
8007ec8: 3301 adds r3, #1
|
|
8007eca: 61fb str r3, [r7, #28]
|
|
8007ecc: 69fb ldr r3, [r7, #28]
|
|
8007ece: 2b0f cmp r3, #15
|
|
8007ed0: f67f ae86 bls.w 8007be0 <HAL_GPIO_Init+0x20>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8007ed4: bf00 nop
|
|
8007ed6: 3724 adds r7, #36 ; 0x24
|
|
8007ed8: 46bd mov sp, r7
|
|
8007eda: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ede: 4770 bx lr
|
|
8007ee0: 40023800 .word 0x40023800
|
|
8007ee4: 40013800 .word 0x40013800
|
|
8007ee8: 40020000 .word 0x40020000
|
|
8007eec: 40020400 .word 0x40020400
|
|
8007ef0: 40020800 .word 0x40020800
|
|
8007ef4: 40020c00 .word 0x40020c00
|
|
8007ef8: 40021000 .word 0x40021000
|
|
8007efc: 40021400 .word 0x40021400
|
|
8007f00: 40021800 .word 0x40021800
|
|
8007f04: 40021c00 .word 0x40021c00
|
|
8007f08: 40022000 .word 0x40022000
|
|
8007f0c: 40022400 .word 0x40022400
|
|
8007f10: 40013c00 .word 0x40013c00
|
|
|
|
08007f14 <HAL_GPIO_DeInit>:
|
|
* @param GPIO_Pin specifies the port bit to be written.
|
|
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|
{
|
|
8007f14: b480 push {r7}
|
|
8007f16: b087 sub sp, #28
|
|
8007f18: af00 add r7, sp, #0
|
|
8007f1a: 6078 str r0, [r7, #4]
|
|
8007f1c: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00;
|
|
8007f1e: 2300 movs r3, #0
|
|
8007f20: 613b str r3, [r7, #16]
|
|
uint32_t iocurrent = 0x00;
|
|
8007f22: 2300 movs r3, #0
|
|
8007f24: 60fb str r3, [r7, #12]
|
|
uint32_t tmp = 0x00;
|
|
8007f26: 2300 movs r3, #0
|
|
8007f28: 60bb str r3, [r7, #8]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0; position < GPIO_NUMBER; position++)
|
|
8007f2a: 2300 movs r3, #0
|
|
8007f2c: 617b str r3, [r7, #20]
|
|
8007f2e: e0d9 b.n 80080e4 <HAL_GPIO_DeInit+0x1d0>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = ((uint32_t)0x01) << position;
|
|
8007f30: 2201 movs r2, #1
|
|
8007f32: 697b ldr r3, [r7, #20]
|
|
8007f34: fa02 f303 lsl.w r3, r2, r3
|
|
8007f38: 613b str r3, [r7, #16]
|
|
/* Get the current IO position */
|
|
iocurrent = (GPIO_Pin) & ioposition;
|
|
8007f3a: 683a ldr r2, [r7, #0]
|
|
8007f3c: 693b ldr r3, [r7, #16]
|
|
8007f3e: 4013 ands r3, r2
|
|
8007f40: 60fb str r3, [r7, #12]
|
|
|
|
if(iocurrent == ioposition)
|
|
8007f42: 68fa ldr r2, [r7, #12]
|
|
8007f44: 693b ldr r3, [r7, #16]
|
|
8007f46: 429a cmp r2, r3
|
|
8007f48: f040 80c9 bne.w 80080de <HAL_GPIO_DeInit+0x1ca>
|
|
{
|
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
|
tmp = SYSCFG->EXTICR[position >> 2];
|
|
8007f4c: 4a6a ldr r2, [pc, #424] ; (80080f8 <HAL_GPIO_DeInit+0x1e4>)
|
|
8007f4e: 697b ldr r3, [r7, #20]
|
|
8007f50: 089b lsrs r3, r3, #2
|
|
8007f52: 3302 adds r3, #2
|
|
8007f54: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8007f58: 60bb str r3, [r7, #8]
|
|
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
|
|
8007f5a: 697b ldr r3, [r7, #20]
|
|
8007f5c: f003 0303 and.w r3, r3, #3
|
|
8007f60: 009b lsls r3, r3, #2
|
|
8007f62: 220f movs r2, #15
|
|
8007f64: fa02 f303 lsl.w r3, r2, r3
|
|
8007f68: 68ba ldr r2, [r7, #8]
|
|
8007f6a: 4013 ands r3, r2
|
|
8007f6c: 60bb str r3, [r7, #8]
|
|
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
|
|
8007f6e: 687b ldr r3, [r7, #4]
|
|
8007f70: 4a62 ldr r2, [pc, #392] ; (80080fc <HAL_GPIO_DeInit+0x1e8>)
|
|
8007f72: 4293 cmp r3, r2
|
|
8007f74: d037 beq.n 8007fe6 <HAL_GPIO_DeInit+0xd2>
|
|
8007f76: 687b ldr r3, [r7, #4]
|
|
8007f78: 4a61 ldr r2, [pc, #388] ; (8008100 <HAL_GPIO_DeInit+0x1ec>)
|
|
8007f7a: 4293 cmp r3, r2
|
|
8007f7c: d031 beq.n 8007fe2 <HAL_GPIO_DeInit+0xce>
|
|
8007f7e: 687b ldr r3, [r7, #4]
|
|
8007f80: 4a60 ldr r2, [pc, #384] ; (8008104 <HAL_GPIO_DeInit+0x1f0>)
|
|
8007f82: 4293 cmp r3, r2
|
|
8007f84: d02b beq.n 8007fde <HAL_GPIO_DeInit+0xca>
|
|
8007f86: 687b ldr r3, [r7, #4]
|
|
8007f88: 4a5f ldr r2, [pc, #380] ; (8008108 <HAL_GPIO_DeInit+0x1f4>)
|
|
8007f8a: 4293 cmp r3, r2
|
|
8007f8c: d025 beq.n 8007fda <HAL_GPIO_DeInit+0xc6>
|
|
8007f8e: 687b ldr r3, [r7, #4]
|
|
8007f90: 4a5e ldr r2, [pc, #376] ; (800810c <HAL_GPIO_DeInit+0x1f8>)
|
|
8007f92: 4293 cmp r3, r2
|
|
8007f94: d01f beq.n 8007fd6 <HAL_GPIO_DeInit+0xc2>
|
|
8007f96: 687b ldr r3, [r7, #4]
|
|
8007f98: 4a5d ldr r2, [pc, #372] ; (8008110 <HAL_GPIO_DeInit+0x1fc>)
|
|
8007f9a: 4293 cmp r3, r2
|
|
8007f9c: d019 beq.n 8007fd2 <HAL_GPIO_DeInit+0xbe>
|
|
8007f9e: 687b ldr r3, [r7, #4]
|
|
8007fa0: 4a5c ldr r2, [pc, #368] ; (8008114 <HAL_GPIO_DeInit+0x200>)
|
|
8007fa2: 4293 cmp r3, r2
|
|
8007fa4: d013 beq.n 8007fce <HAL_GPIO_DeInit+0xba>
|
|
8007fa6: 687b ldr r3, [r7, #4]
|
|
8007fa8: 4a5b ldr r2, [pc, #364] ; (8008118 <HAL_GPIO_DeInit+0x204>)
|
|
8007faa: 4293 cmp r3, r2
|
|
8007fac: d00d beq.n 8007fca <HAL_GPIO_DeInit+0xb6>
|
|
8007fae: 687b ldr r3, [r7, #4]
|
|
8007fb0: 4a5a ldr r2, [pc, #360] ; (800811c <HAL_GPIO_DeInit+0x208>)
|
|
8007fb2: 4293 cmp r3, r2
|
|
8007fb4: d007 beq.n 8007fc6 <HAL_GPIO_DeInit+0xb2>
|
|
8007fb6: 687b ldr r3, [r7, #4]
|
|
8007fb8: 4a59 ldr r2, [pc, #356] ; (8008120 <HAL_GPIO_DeInit+0x20c>)
|
|
8007fba: 4293 cmp r3, r2
|
|
8007fbc: d101 bne.n 8007fc2 <HAL_GPIO_DeInit+0xae>
|
|
8007fbe: 2309 movs r3, #9
|
|
8007fc0: e012 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fc2: 230a movs r3, #10
|
|
8007fc4: e010 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fc6: 2308 movs r3, #8
|
|
8007fc8: e00e b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fca: 2307 movs r3, #7
|
|
8007fcc: e00c b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fce: 2306 movs r3, #6
|
|
8007fd0: e00a b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fd2: 2305 movs r3, #5
|
|
8007fd4: e008 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fd6: 2304 movs r3, #4
|
|
8007fd8: e006 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fda: 2303 movs r3, #3
|
|
8007fdc: e004 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fde: 2302 movs r3, #2
|
|
8007fe0: e002 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fe2: 2301 movs r3, #1
|
|
8007fe4: e000 b.n 8007fe8 <HAL_GPIO_DeInit+0xd4>
|
|
8007fe6: 2300 movs r3, #0
|
|
8007fe8: 697a ldr r2, [r7, #20]
|
|
8007fea: f002 0203 and.w r2, r2, #3
|
|
8007fee: 0092 lsls r2, r2, #2
|
|
8007ff0: 4093 lsls r3, r2
|
|
8007ff2: 68ba ldr r2, [r7, #8]
|
|
8007ff4: 429a cmp r2, r3
|
|
8007ff6: d132 bne.n 800805e <HAL_GPIO_DeInit+0x14a>
|
|
{
|
|
/* Clear EXTI line configuration */
|
|
EXTI->IMR &= ~((uint32_t)iocurrent);
|
|
8007ff8: 4b4a ldr r3, [pc, #296] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8007ffa: 681a ldr r2, [r3, #0]
|
|
8007ffc: 68fb ldr r3, [r7, #12]
|
|
8007ffe: 43db mvns r3, r3
|
|
8008000: 4948 ldr r1, [pc, #288] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8008002: 4013 ands r3, r2
|
|
8008004: 600b str r3, [r1, #0]
|
|
EXTI->EMR &= ~((uint32_t)iocurrent);
|
|
8008006: 4b47 ldr r3, [pc, #284] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8008008: 685a ldr r2, [r3, #4]
|
|
800800a: 68fb ldr r3, [r7, #12]
|
|
800800c: 43db mvns r3, r3
|
|
800800e: 4945 ldr r1, [pc, #276] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8008010: 4013 ands r3, r2
|
|
8008012: 604b str r3, [r1, #4]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
|
8008014: 4b43 ldr r3, [pc, #268] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8008016: 689a ldr r2, [r3, #8]
|
|
8008018: 68fb ldr r3, [r7, #12]
|
|
800801a: 43db mvns r3, r3
|
|
800801c: 4941 ldr r1, [pc, #260] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
800801e: 4013 ands r3, r2
|
|
8008020: 608b str r3, [r1, #8]
|
|
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
|
8008022: 4b40 ldr r3, [pc, #256] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
8008024: 68da ldr r2, [r3, #12]
|
|
8008026: 68fb ldr r3, [r7, #12]
|
|
8008028: 43db mvns r3, r3
|
|
800802a: 493e ldr r1, [pc, #248] ; (8008124 <HAL_GPIO_DeInit+0x210>)
|
|
800802c: 4013 ands r3, r2
|
|
800802e: 60cb str r3, [r1, #12]
|
|
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
|
|
8008030: 697b ldr r3, [r7, #20]
|
|
8008032: f003 0303 and.w r3, r3, #3
|
|
8008036: 009b lsls r3, r3, #2
|
|
8008038: 220f movs r2, #15
|
|
800803a: fa02 f303 lsl.w r3, r2, r3
|
|
800803e: 60bb str r3, [r7, #8]
|
|
SYSCFG->EXTICR[position >> 2] &= ~tmp;
|
|
8008040: 4a2d ldr r2, [pc, #180] ; (80080f8 <HAL_GPIO_DeInit+0x1e4>)
|
|
8008042: 697b ldr r3, [r7, #20]
|
|
8008044: 089b lsrs r3, r3, #2
|
|
8008046: 3302 adds r3, #2
|
|
8008048: f852 1023 ldr.w r1, [r2, r3, lsl #2]
|
|
800804c: 68bb ldr r3, [r7, #8]
|
|
800804e: 43da mvns r2, r3
|
|
8008050: 4829 ldr r0, [pc, #164] ; (80080f8 <HAL_GPIO_DeInit+0x1e4>)
|
|
8008052: 697b ldr r3, [r7, #20]
|
|
8008054: 089b lsrs r3, r3, #2
|
|
8008056: 400a ands r2, r1
|
|
8008058: 3302 adds r3, #2
|
|
800805a: f840 2023 str.w r2, [r0, r3, lsl #2]
|
|
}
|
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
|
/* Configure IO Direction in Input Floating Mode */
|
|
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
|
|
800805e: 687b ldr r3, [r7, #4]
|
|
8008060: 681a ldr r2, [r3, #0]
|
|
8008062: 697b ldr r3, [r7, #20]
|
|
8008064: 005b lsls r3, r3, #1
|
|
8008066: 2103 movs r1, #3
|
|
8008068: fa01 f303 lsl.w r3, r1, r3
|
|
800806c: 43db mvns r3, r3
|
|
800806e: 401a ands r2, r3
|
|
8008070: 687b ldr r3, [r7, #4]
|
|
8008072: 601a str r2, [r3, #0]
|
|
|
|
/* Configure the default Alternate Function in current IO */
|
|
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
|
8008074: 697b ldr r3, [r7, #20]
|
|
8008076: 08da lsrs r2, r3, #3
|
|
8008078: 687b ldr r3, [r7, #4]
|
|
800807a: 3208 adds r2, #8
|
|
800807c: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
8008080: 697b ldr r3, [r7, #20]
|
|
8008082: f003 0307 and.w r3, r3, #7
|
|
8008086: 009b lsls r3, r3, #2
|
|
8008088: 220f movs r2, #15
|
|
800808a: fa02 f303 lsl.w r3, r2, r3
|
|
800808e: 43db mvns r3, r3
|
|
8008090: 697a ldr r2, [r7, #20]
|
|
8008092: 08d2 lsrs r2, r2, #3
|
|
8008094: 4019 ands r1, r3
|
|
8008096: 687b ldr r3, [r7, #4]
|
|
8008098: 3208 adds r2, #8
|
|
800809a: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
|
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
|
800809e: 687b ldr r3, [r7, #4]
|
|
80080a0: 68da ldr r2, [r3, #12]
|
|
80080a2: 697b ldr r3, [r7, #20]
|
|
80080a4: 005b lsls r3, r3, #1
|
|
80080a6: 2103 movs r1, #3
|
|
80080a8: fa01 f303 lsl.w r3, r1, r3
|
|
80080ac: 43db mvns r3, r3
|
|
80080ae: 401a ands r2, r3
|
|
80080b0: 687b ldr r3, [r7, #4]
|
|
80080b2: 60da str r2, [r3, #12]
|
|
|
|
/* Configure the default value IO Output Type */
|
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
80080b4: 687b ldr r3, [r7, #4]
|
|
80080b6: 685a ldr r2, [r3, #4]
|
|
80080b8: 2101 movs r1, #1
|
|
80080ba: 697b ldr r3, [r7, #20]
|
|
80080bc: fa01 f303 lsl.w r3, r1, r3
|
|
80080c0: 43db mvns r3, r3
|
|
80080c2: 401a ands r2, r3
|
|
80080c4: 687b ldr r3, [r7, #4]
|
|
80080c6: 605a str r2, [r3, #4]
|
|
|
|
/* Configure the default value for IO Speed */
|
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
|
80080c8: 687b ldr r3, [r7, #4]
|
|
80080ca: 689a ldr r2, [r3, #8]
|
|
80080cc: 697b ldr r3, [r7, #20]
|
|
80080ce: 005b lsls r3, r3, #1
|
|
80080d0: 2103 movs r1, #3
|
|
80080d2: fa01 f303 lsl.w r3, r1, r3
|
|
80080d6: 43db mvns r3, r3
|
|
80080d8: 401a ands r2, r3
|
|
80080da: 687b ldr r3, [r7, #4]
|
|
80080dc: 609a str r2, [r3, #8]
|
|
for(position = 0; position < GPIO_NUMBER; position++)
|
|
80080de: 697b ldr r3, [r7, #20]
|
|
80080e0: 3301 adds r3, #1
|
|
80080e2: 617b str r3, [r7, #20]
|
|
80080e4: 697b ldr r3, [r7, #20]
|
|
80080e6: 2b0f cmp r3, #15
|
|
80080e8: f67f af22 bls.w 8007f30 <HAL_GPIO_DeInit+0x1c>
|
|
}
|
|
}
|
|
}
|
|
80080ec: bf00 nop
|
|
80080ee: 371c adds r7, #28
|
|
80080f0: 46bd mov sp, r7
|
|
80080f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80080f6: 4770 bx lr
|
|
80080f8: 40013800 .word 0x40013800
|
|
80080fc: 40020000 .word 0x40020000
|
|
8008100: 40020400 .word 0x40020400
|
|
8008104: 40020800 .word 0x40020800
|
|
8008108: 40020c00 .word 0x40020c00
|
|
800810c: 40021000 .word 0x40021000
|
|
8008110: 40021400 .word 0x40021400
|
|
8008114: 40021800 .word 0x40021800
|
|
8008118: 40021c00 .word 0x40021c00
|
|
800811c: 40022000 .word 0x40022000
|
|
8008120: 40022400 .word 0x40022400
|
|
8008124: 40013c00 .word 0x40013c00
|
|
|
|
08008128 <HAL_GPIO_ReadPin>:
|
|
* @param GPIO_Pin specifies the port bit to read.
|
|
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
|
* @retval The input port pin value.
|
|
*/
|
|
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8008128: b480 push {r7}
|
|
800812a: b085 sub sp, #20
|
|
800812c: af00 add r7, sp, #0
|
|
800812e: 6078 str r0, [r7, #4]
|
|
8008130: 460b mov r3, r1
|
|
8008132: 807b strh r3, [r7, #2]
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
|
8008134: 687b ldr r3, [r7, #4]
|
|
8008136: 691a ldr r2, [r3, #16]
|
|
8008138: 887b ldrh r3, [r7, #2]
|
|
800813a: 4013 ands r3, r2
|
|
800813c: 2b00 cmp r3, #0
|
|
800813e: d002 beq.n 8008146 <HAL_GPIO_ReadPin+0x1e>
|
|
{
|
|
bitstatus = GPIO_PIN_SET;
|
|
8008140: 2301 movs r3, #1
|
|
8008142: 73fb strb r3, [r7, #15]
|
|
8008144: e001 b.n 800814a <HAL_GPIO_ReadPin+0x22>
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
8008146: 2300 movs r3, #0
|
|
8008148: 73fb strb r3, [r7, #15]
|
|
}
|
|
return bitstatus;
|
|
800814a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800814c: 4618 mov r0, r3
|
|
800814e: 3714 adds r7, #20
|
|
8008150: 46bd mov sp, r7
|
|
8008152: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008156: 4770 bx lr
|
|
|
|
08008158 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8008158: b480 push {r7}
|
|
800815a: b083 sub sp, #12
|
|
800815c: af00 add r7, sp, #0
|
|
800815e: 6078 str r0, [r7, #4]
|
|
8008160: 460b mov r3, r1
|
|
8008162: 807b strh r3, [r7, #2]
|
|
8008164: 4613 mov r3, r2
|
|
8008166: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8008168: 787b ldrb r3, [r7, #1]
|
|
800816a: 2b00 cmp r3, #0
|
|
800816c: d003 beq.n 8008176 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
800816e: 887a ldrh r2, [r7, #2]
|
|
8008170: 687b ldr r3, [r7, #4]
|
|
8008172: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
|
|
}
|
|
}
|
|
8008174: e003 b.n 800817e <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
|
|
8008176: 887b ldrh r3, [r7, #2]
|
|
8008178: 041a lsls r2, r3, #16
|
|
800817a: 687b ldr r3, [r7, #4]
|
|
800817c: 619a str r2, [r3, #24]
|
|
}
|
|
800817e: bf00 nop
|
|
8008180: 370c adds r7, #12
|
|
8008182: 46bd mov sp, r7
|
|
8008184: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008188: 4770 bx lr
|
|
...
|
|
|
|
0800818c <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
800818c: b580 push {r7, lr}
|
|
800818e: b082 sub sp, #8
|
|
8008190: af00 add r7, sp, #0
|
|
8008192: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8008194: 687b ldr r3, [r7, #4]
|
|
8008196: 2b00 cmp r3, #0
|
|
8008198: d101 bne.n 800819e <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800819a: 2301 movs r3, #1
|
|
800819c: e07f b.n 800829e <HAL_I2C_Init+0x112>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
800819e: 687b ldr r3, [r7, #4]
|
|
80081a0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
80081a4: b2db uxtb r3, r3
|
|
80081a6: 2b00 cmp r3, #0
|
|
80081a8: d106 bne.n 80081b8 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
80081aa: 687b ldr r3, [r7, #4]
|
|
80081ac: 2200 movs r2, #0
|
|
80081ae: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
80081b2: 6878 ldr r0, [r7, #4]
|
|
80081b4: f7fc faaa bl 800470c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80081b8: 687b ldr r3, [r7, #4]
|
|
80081ba: 2224 movs r2, #36 ; 0x24
|
|
80081bc: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80081c0: 687b ldr r3, [r7, #4]
|
|
80081c2: 681b ldr r3, [r3, #0]
|
|
80081c4: 681a ldr r2, [r3, #0]
|
|
80081c6: 687b ldr r3, [r7, #4]
|
|
80081c8: 681b ldr r3, [r3, #0]
|
|
80081ca: f022 0201 bic.w r2, r2, #1
|
|
80081ce: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
80081d0: 687b ldr r3, [r7, #4]
|
|
80081d2: 685a ldr r2, [r3, #4]
|
|
80081d4: 687b ldr r3, [r7, #4]
|
|
80081d6: 681b ldr r3, [r3, #0]
|
|
80081d8: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
|
|
80081dc: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
80081de: 687b ldr r3, [r7, #4]
|
|
80081e0: 681b ldr r3, [r3, #0]
|
|
80081e2: 689a ldr r2, [r3, #8]
|
|
80081e4: 687b ldr r3, [r7, #4]
|
|
80081e6: 681b ldr r3, [r3, #0]
|
|
80081e8: f422 4200 bic.w r2, r2, #32768 ; 0x8000
|
|
80081ec: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
80081ee: 687b ldr r3, [r7, #4]
|
|
80081f0: 68db ldr r3, [r3, #12]
|
|
80081f2: 2b01 cmp r3, #1
|
|
80081f4: d107 bne.n 8008206 <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
80081f6: 687b ldr r3, [r7, #4]
|
|
80081f8: 689a ldr r2, [r3, #8]
|
|
80081fa: 687b ldr r3, [r7, #4]
|
|
80081fc: 681b ldr r3, [r3, #0]
|
|
80081fe: f442 4200 orr.w r2, r2, #32768 ; 0x8000
|
|
8008202: 609a str r2, [r3, #8]
|
|
8008204: e006 b.n 8008214 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8008206: 687b ldr r3, [r7, #4]
|
|
8008208: 689a ldr r2, [r3, #8]
|
|
800820a: 687b ldr r3, [r7, #4]
|
|
800820c: 681b ldr r3, [r3, #0]
|
|
800820e: f442 4204 orr.w r2, r2, #33792 ; 0x8400
|
|
8008212: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8008214: 687b ldr r3, [r7, #4]
|
|
8008216: 68db ldr r3, [r3, #12]
|
|
8008218: 2b02 cmp r3, #2
|
|
800821a: d104 bne.n 8008226 <HAL_I2C_Init+0x9a>
|
|
{
|
|
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
|
|
800821c: 687b ldr r3, [r7, #4]
|
|
800821e: 681b ldr r3, [r3, #0]
|
|
8008220: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
8008224: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8008226: 687b ldr r3, [r7, #4]
|
|
8008228: 681b ldr r3, [r3, #0]
|
|
800822a: 6859 ldr r1, [r3, #4]
|
|
800822c: 687b ldr r3, [r7, #4]
|
|
800822e: 681a ldr r2, [r3, #0]
|
|
8008230: 4b1d ldr r3, [pc, #116] ; (80082a8 <HAL_I2C_Init+0x11c>)
|
|
8008232: 430b orrs r3, r1
|
|
8008234: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8008236: 687b ldr r3, [r7, #4]
|
|
8008238: 681b ldr r3, [r3, #0]
|
|
800823a: 68da ldr r2, [r3, #12]
|
|
800823c: 687b ldr r3, [r7, #4]
|
|
800823e: 681b ldr r3, [r3, #0]
|
|
8008240: f422 4200 bic.w r2, r2, #32768 ; 0x8000
|
|
8008244: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
|
|
8008246: 687b ldr r3, [r7, #4]
|
|
8008248: 691a ldr r2, [r3, #16]
|
|
800824a: 687b ldr r3, [r7, #4]
|
|
800824c: 695b ldr r3, [r3, #20]
|
|
800824e: ea42 0103 orr.w r1, r2, r3
|
|
8008252: 687b ldr r3, [r7, #4]
|
|
8008254: 699b ldr r3, [r3, #24]
|
|
8008256: 021a lsls r2, r3, #8
|
|
8008258: 687b ldr r3, [r7, #4]
|
|
800825a: 681b ldr r3, [r3, #0]
|
|
800825c: 430a orrs r2, r1
|
|
800825e: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8008260: 687b ldr r3, [r7, #4]
|
|
8008262: 69d9 ldr r1, [r3, #28]
|
|
8008264: 687b ldr r3, [r7, #4]
|
|
8008266: 6a1a ldr r2, [r3, #32]
|
|
8008268: 687b ldr r3, [r7, #4]
|
|
800826a: 681b ldr r3, [r3, #0]
|
|
800826c: 430a orrs r2, r1
|
|
800826e: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8008270: 687b ldr r3, [r7, #4]
|
|
8008272: 681b ldr r3, [r3, #0]
|
|
8008274: 681a ldr r2, [r3, #0]
|
|
8008276: 687b ldr r3, [r7, #4]
|
|
8008278: 681b ldr r3, [r3, #0]
|
|
800827a: f042 0201 orr.w r2, r2, #1
|
|
800827e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8008280: 687b ldr r3, [r7, #4]
|
|
8008282: 2200 movs r2, #0
|
|
8008284: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008286: 687b ldr r3, [r7, #4]
|
|
8008288: 2220 movs r2, #32
|
|
800828a: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800828e: 687b ldr r3, [r7, #4]
|
|
8008290: 2200 movs r2, #0
|
|
8008292: 631a str r2, [r3, #48] ; 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008294: 687b ldr r3, [r7, #4]
|
|
8008296: 2200 movs r2, #0
|
|
8008298: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
return HAL_OK;
|
|
800829c: 2300 movs r3, #0
|
|
}
|
|
800829e: 4618 mov r0, r3
|
|
80082a0: 3708 adds r7, #8
|
|
80082a2: 46bd mov sp, r7
|
|
80082a4: bd80 pop {r7, pc}
|
|
80082a6: bf00 nop
|
|
80082a8: 02008000 .word 0x02008000
|
|
|
|
080082ac <HAL_I2C_DeInit>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80082ac: b580 push {r7, lr}
|
|
80082ae: b082 sub sp, #8
|
|
80082b0: af00 add r7, sp, #0
|
|
80082b2: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
80082b4: 687b ldr r3, [r7, #4]
|
|
80082b6: 2b00 cmp r3, #0
|
|
80082b8: d101 bne.n 80082be <HAL_I2C_DeInit+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80082ba: 2301 movs r3, #1
|
|
80082bc: e021 b.n 8008302 <HAL_I2C_DeInit+0x56>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80082be: 687b ldr r3, [r7, #4]
|
|
80082c0: 2224 movs r2, #36 ; 0x24
|
|
80082c2: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the I2C Peripheral Clock */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80082c6: 687b ldr r3, [r7, #4]
|
|
80082c8: 681b ldr r3, [r3, #0]
|
|
80082ca: 681a ldr r2, [r3, #0]
|
|
80082cc: 687b ldr r3, [r7, #4]
|
|
80082ce: 681b ldr r3, [r3, #0]
|
|
80082d0: f022 0201 bic.w r2, r2, #1
|
|
80082d4: 601a str r2, [r3, #0]
|
|
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
hi2c->MspDeInitCallback(hi2c);
|
|
#else
|
|
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspDeInit(hi2c);
|
|
80082d6: 6878 ldr r0, [r7, #4]
|
|
80082d8: f7fc fa90 bl 80047fc <HAL_I2C_MspDeInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
80082dc: 687b ldr r3, [r7, #4]
|
|
80082de: 2200 movs r2, #0
|
|
80082e0: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_RESET;
|
|
80082e2: 687b ldr r3, [r7, #4]
|
|
80082e4: 2200 movs r2, #0
|
|
80082e6: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
80082ea: 687b ldr r3, [r7, #4]
|
|
80082ec: 2200 movs r2, #0
|
|
80082ee: 631a str r2, [r3, #48] ; 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80082f0: 687b ldr r3, [r7, #4]
|
|
80082f2: 2200 movs r2, #0
|
|
80082f4: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hi2c);
|
|
80082f8: 687b ldr r3, [r7, #4]
|
|
80082fa: 2200 movs r2, #0
|
|
80082fc: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8008300: 2300 movs r3, #0
|
|
}
|
|
8008302: 4618 mov r0, r3
|
|
8008304: 3708 adds r7, #8
|
|
8008306: 46bd mov sp, r7
|
|
8008308: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800830c <HAL_I2C_Mem_Write>:
|
|
* @param Size Amount of data to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
800830c: b580 push {r7, lr}
|
|
800830e: b088 sub sp, #32
|
|
8008310: af02 add r7, sp, #8
|
|
8008312: 60f8 str r0, [r7, #12]
|
|
8008314: 4608 mov r0, r1
|
|
8008316: 4611 mov r1, r2
|
|
8008318: 461a mov r2, r3
|
|
800831a: 4603 mov r3, r0
|
|
800831c: 817b strh r3, [r7, #10]
|
|
800831e: 460b mov r3, r1
|
|
8008320: 813b strh r3, [r7, #8]
|
|
8008322: 4613 mov r3, r2
|
|
8008324: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8008326: 68fb ldr r3, [r7, #12]
|
|
8008328: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
800832c: b2db uxtb r3, r3
|
|
800832e: 2b20 cmp r3, #32
|
|
8008330: f040 80f9 bne.w 8008526 <HAL_I2C_Mem_Write+0x21a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8008334: 6a3b ldr r3, [r7, #32]
|
|
8008336: 2b00 cmp r3, #0
|
|
8008338: d002 beq.n 8008340 <HAL_I2C_Mem_Write+0x34>
|
|
800833a: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
800833c: 2b00 cmp r3, #0
|
|
800833e: d105 bne.n 800834c <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8008340: 68fb ldr r3, [r7, #12]
|
|
8008342: f44f 7200 mov.w r2, #512 ; 0x200
|
|
8008346: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
8008348: 2301 movs r3, #1
|
|
800834a: e0ed b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
800834c: 68fb ldr r3, [r7, #12]
|
|
800834e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8008352: 2b01 cmp r3, #1
|
|
8008354: d101 bne.n 800835a <HAL_I2C_Mem_Write+0x4e>
|
|
8008356: 2302 movs r3, #2
|
|
8008358: e0e6 b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
800835a: 68fb ldr r3, [r7, #12]
|
|
800835c: 2201 movs r2, #1
|
|
800835e: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8008362: f7fc ffbd bl 80052e0 <HAL_GetTick>
|
|
8008366: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8008368: 697b ldr r3, [r7, #20]
|
|
800836a: 9300 str r3, [sp, #0]
|
|
800836c: 2319 movs r3, #25
|
|
800836e: 2201 movs r2, #1
|
|
8008370: f44f 4100 mov.w r1, #32768 ; 0x8000
|
|
8008374: 68f8 ldr r0, [r7, #12]
|
|
8008376: f000 fad1 bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
800837a: 4603 mov r3, r0
|
|
800837c: 2b00 cmp r3, #0
|
|
800837e: d001 beq.n 8008384 <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8008380: 2301 movs r3, #1
|
|
8008382: e0d1 b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8008384: 68fb ldr r3, [r7, #12]
|
|
8008386: 2221 movs r2, #33 ; 0x21
|
|
8008388: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
800838c: 68fb ldr r3, [r7, #12]
|
|
800838e: 2240 movs r2, #64 ; 0x40
|
|
8008390: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8008394: 68fb ldr r3, [r7, #12]
|
|
8008396: 2200 movs r2, #0
|
|
8008398: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
800839a: 68fb ldr r3, [r7, #12]
|
|
800839c: 6a3a ldr r2, [r7, #32]
|
|
800839e: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
80083a0: 68fb ldr r3, [r7, #12]
|
|
80083a2: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
80083a4: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
80083a6: 68fb ldr r3, [r7, #12]
|
|
80083a8: 2200 movs r2, #0
|
|
80083aa: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
80083ac: 88f8 ldrh r0, [r7, #6]
|
|
80083ae: 893a ldrh r2, [r7, #8]
|
|
80083b0: 8979 ldrh r1, [r7, #10]
|
|
80083b2: 697b ldr r3, [r7, #20]
|
|
80083b4: 9301 str r3, [sp, #4]
|
|
80083b6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80083b8: 9300 str r3, [sp, #0]
|
|
80083ba: 4603 mov r3, r0
|
|
80083bc: 68f8 ldr r0, [r7, #12]
|
|
80083be: f000 f9e1 bl 8008784 <I2C_RequestMemoryWrite>
|
|
80083c2: 4603 mov r3, r0
|
|
80083c4: 2b00 cmp r3, #0
|
|
80083c6: d005 beq.n 80083d4 <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80083c8: 68fb ldr r3, [r7, #12]
|
|
80083ca: 2200 movs r2, #0
|
|
80083cc: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
80083d0: 2301 movs r3, #1
|
|
80083d2: e0a9 b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
80083d4: 68fb ldr r3, [r7, #12]
|
|
80083d6: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80083d8: b29b uxth r3, r3
|
|
80083da: 2bff cmp r3, #255 ; 0xff
|
|
80083dc: d90e bls.n 80083fc <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
80083de: 68fb ldr r3, [r7, #12]
|
|
80083e0: 22ff movs r2, #255 ; 0xff
|
|
80083e2: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
80083e4: 68fb ldr r3, [r7, #12]
|
|
80083e6: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80083e8: b2da uxtb r2, r3
|
|
80083ea: 8979 ldrh r1, [r7, #10]
|
|
80083ec: 2300 movs r3, #0
|
|
80083ee: 9300 str r3, [sp, #0]
|
|
80083f0: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
80083f4: 68f8 ldr r0, [r7, #12]
|
|
80083f6: f000 fbb3 bl 8008b60 <I2C_TransferConfig>
|
|
80083fa: e00f b.n 800841c <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80083fc: 68fb ldr r3, [r7, #12]
|
|
80083fe: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008400: b29a uxth r2, r3
|
|
8008402: 68fb ldr r3, [r7, #12]
|
|
8008404: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8008406: 68fb ldr r3, [r7, #12]
|
|
8008408: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800840a: b2da uxtb r2, r3
|
|
800840c: 8979 ldrh r1, [r7, #10]
|
|
800840e: 2300 movs r3, #0
|
|
8008410: 9300 str r3, [sp, #0]
|
|
8008412: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
8008416: 68f8 ldr r0, [r7, #12]
|
|
8008418: f000 fba2 bl 8008b60 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
800841c: 697a ldr r2, [r7, #20]
|
|
800841e: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
8008420: 68f8 ldr r0, [r7, #12]
|
|
8008422: f000 fabb bl 800899c <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8008426: 4603 mov r3, r0
|
|
8008428: 2b00 cmp r3, #0
|
|
800842a: d001 beq.n 8008430 <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
800842c: 2301 movs r3, #1
|
|
800842e: e07b b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8008430: 68fb ldr r3, [r7, #12]
|
|
8008432: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8008434: 781a ldrb r2, [r3, #0]
|
|
8008436: 68fb ldr r3, [r7, #12]
|
|
8008438: 681b ldr r3, [r3, #0]
|
|
800843a: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
800843c: 68fb ldr r3, [r7, #12]
|
|
800843e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8008440: 1c5a adds r2, r3, #1
|
|
8008442: 68fb ldr r3, [r7, #12]
|
|
8008444: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8008446: 68fb ldr r3, [r7, #12]
|
|
8008448: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
800844a: b29b uxth r3, r3
|
|
800844c: 3b01 subs r3, #1
|
|
800844e: b29a uxth r2, r3
|
|
8008450: 68fb ldr r3, [r7, #12]
|
|
8008452: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferSize--;
|
|
8008454: 68fb ldr r3, [r7, #12]
|
|
8008456: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8008458: 3b01 subs r3, #1
|
|
800845a: b29a uxth r2, r3
|
|
800845c: 68fb ldr r3, [r7, #12]
|
|
800845e: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8008460: 68fb ldr r3, [r7, #12]
|
|
8008462: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008464: b29b uxth r3, r3
|
|
8008466: 2b00 cmp r3, #0
|
|
8008468: d034 beq.n 80084d4 <HAL_I2C_Mem_Write+0x1c8>
|
|
800846a: 68fb ldr r3, [r7, #12]
|
|
800846c: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800846e: 2b00 cmp r3, #0
|
|
8008470: d130 bne.n 80084d4 <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8008472: 697b ldr r3, [r7, #20]
|
|
8008474: 9300 str r3, [sp, #0]
|
|
8008476: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8008478: 2200 movs r2, #0
|
|
800847a: 2180 movs r1, #128 ; 0x80
|
|
800847c: 68f8 ldr r0, [r7, #12]
|
|
800847e: f000 fa4d bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
8008482: 4603 mov r3, r0
|
|
8008484: 2b00 cmp r3, #0
|
|
8008486: d001 beq.n 800848c <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8008488: 2301 movs r3, #1
|
|
800848a: e04d b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
800848c: 68fb ldr r3, [r7, #12]
|
|
800848e: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008490: b29b uxth r3, r3
|
|
8008492: 2bff cmp r3, #255 ; 0xff
|
|
8008494: d90e bls.n 80084b4 <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8008496: 68fb ldr r3, [r7, #12]
|
|
8008498: 22ff movs r2, #255 ; 0xff
|
|
800849a: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
800849c: 68fb ldr r3, [r7, #12]
|
|
800849e: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80084a0: b2da uxtb r2, r3
|
|
80084a2: 8979 ldrh r1, [r7, #10]
|
|
80084a4: 2300 movs r3, #0
|
|
80084a6: 9300 str r3, [sp, #0]
|
|
80084a8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
80084ac: 68f8 ldr r0, [r7, #12]
|
|
80084ae: f000 fb57 bl 8008b60 <I2C_TransferConfig>
|
|
80084b2: e00f b.n 80084d4 <HAL_I2C_Mem_Write+0x1c8>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80084b4: 68fb ldr r3, [r7, #12]
|
|
80084b6: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80084b8: b29a uxth r2, r3
|
|
80084ba: 68fb ldr r3, [r7, #12]
|
|
80084bc: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
80084be: 68fb ldr r3, [r7, #12]
|
|
80084c0: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80084c2: b2da uxtb r2, r3
|
|
80084c4: 8979 ldrh r1, [r7, #10]
|
|
80084c6: 2300 movs r3, #0
|
|
80084c8: 9300 str r3, [sp, #0]
|
|
80084ca: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
80084ce: 68f8 ldr r0, [r7, #12]
|
|
80084d0: f000 fb46 bl 8008b60 <I2C_TransferConfig>
|
|
}
|
|
}
|
|
|
|
}
|
|
while (hi2c->XferCount > 0U);
|
|
80084d4: 68fb ldr r3, [r7, #12]
|
|
80084d6: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80084d8: b29b uxth r3, r3
|
|
80084da: 2b00 cmp r3, #0
|
|
80084dc: d19e bne.n 800841c <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
80084de: 697a ldr r2, [r7, #20]
|
|
80084e0: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
80084e2: 68f8 ldr r0, [r7, #12]
|
|
80084e4: f000 fa9a bl 8008a1c <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
80084e8: 4603 mov r3, r0
|
|
80084ea: 2b00 cmp r3, #0
|
|
80084ec: d001 beq.n 80084f2 <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
80084ee: 2301 movs r3, #1
|
|
80084f0: e01a b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80084f2: 68fb ldr r3, [r7, #12]
|
|
80084f4: 681b ldr r3, [r3, #0]
|
|
80084f6: 2220 movs r2, #32
|
|
80084f8: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80084fa: 68fb ldr r3, [r7, #12]
|
|
80084fc: 681b ldr r3, [r3, #0]
|
|
80084fe: 6859 ldr r1, [r3, #4]
|
|
8008500: 68fb ldr r3, [r7, #12]
|
|
8008502: 681a ldr r2, [r3, #0]
|
|
8008504: 4b0a ldr r3, [pc, #40] ; (8008530 <HAL_I2C_Mem_Write+0x224>)
|
|
8008506: 400b ands r3, r1
|
|
8008508: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800850a: 68fb ldr r3, [r7, #12]
|
|
800850c: 2220 movs r2, #32
|
|
800850e: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008512: 68fb ldr r3, [r7, #12]
|
|
8008514: 2200 movs r2, #0
|
|
8008516: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800851a: 68fb ldr r3, [r7, #12]
|
|
800851c: 2200 movs r2, #0
|
|
800851e: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8008522: 2300 movs r3, #0
|
|
8008524: e000 b.n 8008528 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008526: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008528: 4618 mov r0, r3
|
|
800852a: 3718 adds r7, #24
|
|
800852c: 46bd mov sp, r7
|
|
800852e: bd80 pop {r7, pc}
|
|
8008530: fe00e800 .word 0xfe00e800
|
|
|
|
08008534 <HAL_I2C_Mem_Read>:
|
|
* @param Size Amount of data to be sent
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8008534: b580 push {r7, lr}
|
|
8008536: b088 sub sp, #32
|
|
8008538: af02 add r7, sp, #8
|
|
800853a: 60f8 str r0, [r7, #12]
|
|
800853c: 4608 mov r0, r1
|
|
800853e: 4611 mov r1, r2
|
|
8008540: 461a mov r2, r3
|
|
8008542: 4603 mov r3, r0
|
|
8008544: 817b strh r3, [r7, #10]
|
|
8008546: 460b mov r3, r1
|
|
8008548: 813b strh r3, [r7, #8]
|
|
800854a: 4613 mov r3, r2
|
|
800854c: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
800854e: 68fb ldr r3, [r7, #12]
|
|
8008550: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8008554: b2db uxtb r3, r3
|
|
8008556: 2b20 cmp r3, #32
|
|
8008558: f040 80fd bne.w 8008756 <HAL_I2C_Mem_Read+0x222>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
800855c: 6a3b ldr r3, [r7, #32]
|
|
800855e: 2b00 cmp r3, #0
|
|
8008560: d002 beq.n 8008568 <HAL_I2C_Mem_Read+0x34>
|
|
8008562: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
8008564: 2b00 cmp r3, #0
|
|
8008566: d105 bne.n 8008574 <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8008568: 68fb ldr r3, [r7, #12]
|
|
800856a: f44f 7200 mov.w r2, #512 ; 0x200
|
|
800856e: 645a str r2, [r3, #68] ; 0x44
|
|
return HAL_ERROR;
|
|
8008570: 2301 movs r3, #1
|
|
8008572: e0f1 b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8008574: 68fb ldr r3, [r7, #12]
|
|
8008576: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
800857a: 2b01 cmp r3, #1
|
|
800857c: d101 bne.n 8008582 <HAL_I2C_Mem_Read+0x4e>
|
|
800857e: 2302 movs r3, #2
|
|
8008580: e0ea b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
8008582: 68fb ldr r3, [r7, #12]
|
|
8008584: 2201 movs r2, #1
|
|
8008586: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
800858a: f7fc fea9 bl 80052e0 <HAL_GetTick>
|
|
800858e: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8008590: 697b ldr r3, [r7, #20]
|
|
8008592: 9300 str r3, [sp, #0]
|
|
8008594: 2319 movs r3, #25
|
|
8008596: 2201 movs r2, #1
|
|
8008598: f44f 4100 mov.w r1, #32768 ; 0x8000
|
|
800859c: 68f8 ldr r0, [r7, #12]
|
|
800859e: f000 f9bd bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
80085a2: 4603 mov r3, r0
|
|
80085a4: 2b00 cmp r3, #0
|
|
80085a6: d001 beq.n 80085ac <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
80085a8: 2301 movs r3, #1
|
|
80085aa: e0d5 b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
80085ac: 68fb ldr r3, [r7, #12]
|
|
80085ae: 2222 movs r2, #34 ; 0x22
|
|
80085b0: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
80085b4: 68fb ldr r3, [r7, #12]
|
|
80085b6: 2240 movs r2, #64 ; 0x40
|
|
80085b8: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
80085bc: 68fb ldr r3, [r7, #12]
|
|
80085be: 2200 movs r2, #0
|
|
80085c0: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
80085c2: 68fb ldr r3, [r7, #12]
|
|
80085c4: 6a3a ldr r2, [r7, #32]
|
|
80085c6: 625a str r2, [r3, #36] ; 0x24
|
|
hi2c->XferCount = Size;
|
|
80085c8: 68fb ldr r3, [r7, #12]
|
|
80085ca: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
80085cc: 855a strh r2, [r3, #42] ; 0x2a
|
|
hi2c->XferISR = NULL;
|
|
80085ce: 68fb ldr r3, [r7, #12]
|
|
80085d0: 2200 movs r2, #0
|
|
80085d2: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
80085d4: 88f8 ldrh r0, [r7, #6]
|
|
80085d6: 893a ldrh r2, [r7, #8]
|
|
80085d8: 8979 ldrh r1, [r7, #10]
|
|
80085da: 697b ldr r3, [r7, #20]
|
|
80085dc: 9301 str r3, [sp, #4]
|
|
80085de: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80085e0: 9300 str r3, [sp, #0]
|
|
80085e2: 4603 mov r3, r0
|
|
80085e4: 68f8 ldr r0, [r7, #12]
|
|
80085e6: f000 f921 bl 800882c <I2C_RequestMemoryRead>
|
|
80085ea: 4603 mov r3, r0
|
|
80085ec: 2b00 cmp r3, #0
|
|
80085ee: d005 beq.n 80085fc <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80085f0: 68fb ldr r3, [r7, #12]
|
|
80085f2: 2200 movs r2, #0
|
|
80085f4: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
80085f8: 2301 movs r3, #1
|
|
80085fa: e0ad b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
80085fc: 68fb ldr r3, [r7, #12]
|
|
80085fe: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008600: b29b uxth r3, r3
|
|
8008602: 2bff cmp r3, #255 ; 0xff
|
|
8008604: d90e bls.n 8008624 <HAL_I2C_Mem_Read+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8008606: 68fb ldr r3, [r7, #12]
|
|
8008608: 22ff movs r2, #255 ; 0xff
|
|
800860a: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
|
|
800860c: 68fb ldr r3, [r7, #12]
|
|
800860e: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8008610: b2da uxtb r2, r3
|
|
8008612: 8979 ldrh r1, [r7, #10]
|
|
8008614: 4b52 ldr r3, [pc, #328] ; (8008760 <HAL_I2C_Mem_Read+0x22c>)
|
|
8008616: 9300 str r3, [sp, #0]
|
|
8008618: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
800861c: 68f8 ldr r0, [r7, #12]
|
|
800861e: f000 fa9f bl 8008b60 <I2C_TransferConfig>
|
|
8008622: e00f b.n 8008644 <HAL_I2C_Mem_Read+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8008624: 68fb ldr r3, [r7, #12]
|
|
8008626: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008628: b29a uxth r2, r3
|
|
800862a: 68fb ldr r3, [r7, #12]
|
|
800862c: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
|
|
800862e: 68fb ldr r3, [r7, #12]
|
|
8008630: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8008632: b2da uxtb r2, r3
|
|
8008634: 8979 ldrh r1, [r7, #10]
|
|
8008636: 4b4a ldr r3, [pc, #296] ; (8008760 <HAL_I2C_Mem_Read+0x22c>)
|
|
8008638: 9300 str r3, [sp, #0]
|
|
800863a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
800863e: 68f8 ldr r0, [r7, #12]
|
|
8008640: f000 fa8e bl 8008b60 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
8008644: 697b ldr r3, [r7, #20]
|
|
8008646: 9300 str r3, [sp, #0]
|
|
8008648: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800864a: 2200 movs r2, #0
|
|
800864c: 2104 movs r1, #4
|
|
800864e: 68f8 ldr r0, [r7, #12]
|
|
8008650: f000 f964 bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
8008654: 4603 mov r3, r0
|
|
8008656: 2b00 cmp r3, #0
|
|
8008658: d001 beq.n 800865e <HAL_I2C_Mem_Read+0x12a>
|
|
{
|
|
return HAL_ERROR;
|
|
800865a: 2301 movs r3, #1
|
|
800865c: e07c b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
800865e: 68fb ldr r3, [r7, #12]
|
|
8008660: 681b ldr r3, [r3, #0]
|
|
8008662: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8008664: 68fb ldr r3, [r7, #12]
|
|
8008666: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8008668: b2d2 uxtb r2, r2
|
|
800866a: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
800866c: 68fb ldr r3, [r7, #12]
|
|
800866e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8008670: 1c5a adds r2, r3, #1
|
|
8008672: 68fb ldr r3, [r7, #12]
|
|
8008674: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hi2c->XferSize--;
|
|
8008676: 68fb ldr r3, [r7, #12]
|
|
8008678: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800867a: 3b01 subs r3, #1
|
|
800867c: b29a uxth r2, r3
|
|
800867e: 68fb ldr r3, [r7, #12]
|
|
8008680: 851a strh r2, [r3, #40] ; 0x28
|
|
hi2c->XferCount--;
|
|
8008682: 68fb ldr r3, [r7, #12]
|
|
8008684: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008686: b29b uxth r3, r3
|
|
8008688: 3b01 subs r3, #1
|
|
800868a: b29a uxth r2, r3
|
|
800868c: 68fb ldr r3, [r7, #12]
|
|
800868e: 855a strh r2, [r3, #42] ; 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8008690: 68fb ldr r3, [r7, #12]
|
|
8008692: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008694: b29b uxth r3, r3
|
|
8008696: 2b00 cmp r3, #0
|
|
8008698: d034 beq.n 8008704 <HAL_I2C_Mem_Read+0x1d0>
|
|
800869a: 68fb ldr r3, [r7, #12]
|
|
800869c: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
800869e: 2b00 cmp r3, #0
|
|
80086a0: d130 bne.n 8008704 <HAL_I2C_Mem_Read+0x1d0>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
80086a2: 697b ldr r3, [r7, #20]
|
|
80086a4: 9300 str r3, [sp, #0]
|
|
80086a6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80086a8: 2200 movs r2, #0
|
|
80086aa: 2180 movs r1, #128 ; 0x80
|
|
80086ac: 68f8 ldr r0, [r7, #12]
|
|
80086ae: f000 f935 bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
80086b2: 4603 mov r3, r0
|
|
80086b4: 2b00 cmp r3, #0
|
|
80086b6: d001 beq.n 80086bc <HAL_I2C_Mem_Read+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
80086b8: 2301 movs r3, #1
|
|
80086ba: e04d b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
80086bc: 68fb ldr r3, [r7, #12]
|
|
80086be: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80086c0: b29b uxth r3, r3
|
|
80086c2: 2bff cmp r3, #255 ; 0xff
|
|
80086c4: d90e bls.n 80086e4 <HAL_I2C_Mem_Read+0x1b0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
80086c6: 68fb ldr r3, [r7, #12]
|
|
80086c8: 22ff movs r2, #255 ; 0xff
|
|
80086ca: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
80086cc: 68fb ldr r3, [r7, #12]
|
|
80086ce: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80086d0: b2da uxtb r2, r3
|
|
80086d2: 8979 ldrh r1, [r7, #10]
|
|
80086d4: 2300 movs r3, #0
|
|
80086d6: 9300 str r3, [sp, #0]
|
|
80086d8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
80086dc: 68f8 ldr r0, [r7, #12]
|
|
80086de: f000 fa3f bl 8008b60 <I2C_TransferConfig>
|
|
80086e2: e00f b.n 8008704 <HAL_I2C_Mem_Read+0x1d0>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
80086e4: 68fb ldr r3, [r7, #12]
|
|
80086e6: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80086e8: b29a uxth r2, r3
|
|
80086ea: 68fb ldr r3, [r7, #12]
|
|
80086ec: 851a strh r2, [r3, #40] ; 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
80086ee: 68fb ldr r3, [r7, #12]
|
|
80086f0: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80086f2: b2da uxtb r2, r3
|
|
80086f4: 8979 ldrh r1, [r7, #10]
|
|
80086f6: 2300 movs r3, #0
|
|
80086f8: 9300 str r3, [sp, #0]
|
|
80086fa: f04f 7300 mov.w r3, #33554432 ; 0x2000000
|
|
80086fe: 68f8 ldr r0, [r7, #12]
|
|
8008700: f000 fa2e bl 8008b60 <I2C_TransferConfig>
|
|
}
|
|
}
|
|
}
|
|
while (hi2c->XferCount > 0U);
|
|
8008704: 68fb ldr r3, [r7, #12]
|
|
8008706: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
8008708: b29b uxth r3, r3
|
|
800870a: 2b00 cmp r3, #0
|
|
800870c: d19a bne.n 8008644 <HAL_I2C_Mem_Read+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
800870e: 697a ldr r2, [r7, #20]
|
|
8008710: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
8008712: 68f8 ldr r0, [r7, #12]
|
|
8008714: f000 f982 bl 8008a1c <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8008718: 4603 mov r3, r0
|
|
800871a: 2b00 cmp r3, #0
|
|
800871c: d001 beq.n 8008722 <HAL_I2C_Mem_Read+0x1ee>
|
|
{
|
|
return HAL_ERROR;
|
|
800871e: 2301 movs r3, #1
|
|
8008720: e01a b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8008722: 68fb ldr r3, [r7, #12]
|
|
8008724: 681b ldr r3, [r3, #0]
|
|
8008726: 2220 movs r2, #32
|
|
8008728: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
800872a: 68fb ldr r3, [r7, #12]
|
|
800872c: 681b ldr r3, [r3, #0]
|
|
800872e: 6859 ldr r1, [r3, #4]
|
|
8008730: 68fb ldr r3, [r7, #12]
|
|
8008732: 681a ldr r2, [r3, #0]
|
|
8008734: 4b0b ldr r3, [pc, #44] ; (8008764 <HAL_I2C_Mem_Read+0x230>)
|
|
8008736: 400b ands r3, r1
|
|
8008738: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800873a: 68fb ldr r3, [r7, #12]
|
|
800873c: 2220 movs r2, #32
|
|
800873e: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008742: 68fb ldr r3, [r7, #12]
|
|
8008744: 2200 movs r2, #0
|
|
8008746: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800874a: 68fb ldr r3, [r7, #12]
|
|
800874c: 2200 movs r2, #0
|
|
800874e: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8008752: 2300 movs r3, #0
|
|
8008754: e000 b.n 8008758 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008756: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008758: 4618 mov r0, r3
|
|
800875a: 3718 adds r7, #24
|
|
800875c: 46bd mov sp, r7
|
|
800875e: bd80 pop {r7, pc}
|
|
8008760: 80002400 .word 0x80002400
|
|
8008764: fe00e800 .word 0xfe00e800
|
|
|
|
08008768 <HAL_I2C_GetState>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8008768: b480 push {r7}
|
|
800876a: b083 sub sp, #12
|
|
800876c: af00 add r7, sp, #0
|
|
800876e: 6078 str r0, [r7, #4]
|
|
/* Return I2C handle state */
|
|
return hi2c->State;
|
|
8008770: 687b ldr r3, [r7, #4]
|
|
8008772: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8008776: b2db uxtb r3, r3
|
|
}
|
|
8008778: 4618 mov r0, r3
|
|
800877a: 370c adds r7, #12
|
|
800877c: 46bd mov sp, r7
|
|
800877e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008782: 4770 bx lr
|
|
|
|
08008784 <I2C_RequestMemoryWrite>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008784: b580 push {r7, lr}
|
|
8008786: b086 sub sp, #24
|
|
8008788: af02 add r7, sp, #8
|
|
800878a: 60f8 str r0, [r7, #12]
|
|
800878c: 4608 mov r0, r1
|
|
800878e: 4611 mov r1, r2
|
|
8008790: 461a mov r2, r3
|
|
8008792: 4603 mov r3, r0
|
|
8008794: 817b strh r3, [r7, #10]
|
|
8008796: 460b mov r3, r1
|
|
8008798: 813b strh r3, [r7, #8]
|
|
800879a: 4613 mov r3, r2
|
|
800879c: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
800879e: 88fb ldrh r3, [r7, #6]
|
|
80087a0: b2da uxtb r2, r3
|
|
80087a2: 8979 ldrh r1, [r7, #10]
|
|
80087a4: 4b20 ldr r3, [pc, #128] ; (8008828 <I2C_RequestMemoryWrite+0xa4>)
|
|
80087a6: 9300 str r3, [sp, #0]
|
|
80087a8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
|
|
80087ac: 68f8 ldr r0, [r7, #12]
|
|
80087ae: f000 f9d7 bl 8008b60 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80087b2: 69fa ldr r2, [r7, #28]
|
|
80087b4: 69b9 ldr r1, [r7, #24]
|
|
80087b6: 68f8 ldr r0, [r7, #12]
|
|
80087b8: f000 f8f0 bl 800899c <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80087bc: 4603 mov r3, r0
|
|
80087be: 2b00 cmp r3, #0
|
|
80087c0: d001 beq.n 80087c6 <I2C_RequestMemoryWrite+0x42>
|
|
{
|
|
return HAL_ERROR;
|
|
80087c2: 2301 movs r3, #1
|
|
80087c4: e02c b.n 8008820 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80087c6: 88fb ldrh r3, [r7, #6]
|
|
80087c8: 2b01 cmp r3, #1
|
|
80087ca: d105 bne.n 80087d8 <I2C_RequestMemoryWrite+0x54>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80087cc: 893b ldrh r3, [r7, #8]
|
|
80087ce: b2da uxtb r2, r3
|
|
80087d0: 68fb ldr r3, [r7, #12]
|
|
80087d2: 681b ldr r3, [r3, #0]
|
|
80087d4: 629a str r2, [r3, #40] ; 0x28
|
|
80087d6: e015 b.n 8008804 <I2C_RequestMemoryWrite+0x80>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
80087d8: 893b ldrh r3, [r7, #8]
|
|
80087da: 0a1b lsrs r3, r3, #8
|
|
80087dc: b29b uxth r3, r3
|
|
80087de: b2da uxtb r2, r3
|
|
80087e0: 68fb ldr r3, [r7, #12]
|
|
80087e2: 681b ldr r3, [r3, #0]
|
|
80087e4: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80087e6: 69fa ldr r2, [r7, #28]
|
|
80087e8: 69b9 ldr r1, [r7, #24]
|
|
80087ea: 68f8 ldr r0, [r7, #12]
|
|
80087ec: f000 f8d6 bl 800899c <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80087f0: 4603 mov r3, r0
|
|
80087f2: 2b00 cmp r3, #0
|
|
80087f4: d001 beq.n 80087fa <I2C_RequestMemoryWrite+0x76>
|
|
{
|
|
return HAL_ERROR;
|
|
80087f6: 2301 movs r3, #1
|
|
80087f8: e012 b.n 8008820 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80087fa: 893b ldrh r3, [r7, #8]
|
|
80087fc: b2da uxtb r2, r3
|
|
80087fe: 68fb ldr r3, [r7, #12]
|
|
8008800: 681b ldr r3, [r3, #0]
|
|
8008802: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8008804: 69fb ldr r3, [r7, #28]
|
|
8008806: 9300 str r3, [sp, #0]
|
|
8008808: 69bb ldr r3, [r7, #24]
|
|
800880a: 2200 movs r2, #0
|
|
800880c: 2180 movs r1, #128 ; 0x80
|
|
800880e: 68f8 ldr r0, [r7, #12]
|
|
8008810: f000 f884 bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
8008814: 4603 mov r3, r0
|
|
8008816: 2b00 cmp r3, #0
|
|
8008818: d001 beq.n 800881e <I2C_RequestMemoryWrite+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
800881a: 2301 movs r3, #1
|
|
800881c: e000 b.n 8008820 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800881e: 2300 movs r3, #0
|
|
}
|
|
8008820: 4618 mov r0, r3
|
|
8008822: 3710 adds r7, #16
|
|
8008824: 46bd mov sp, r7
|
|
8008826: bd80 pop {r7, pc}
|
|
8008828: 80002000 .word 0x80002000
|
|
|
|
0800882c <I2C_RequestMemoryRead>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800882c: b580 push {r7, lr}
|
|
800882e: b086 sub sp, #24
|
|
8008830: af02 add r7, sp, #8
|
|
8008832: 60f8 str r0, [r7, #12]
|
|
8008834: 4608 mov r0, r1
|
|
8008836: 4611 mov r1, r2
|
|
8008838: 461a mov r2, r3
|
|
800883a: 4603 mov r3, r0
|
|
800883c: 817b strh r3, [r7, #10]
|
|
800883e: 460b mov r3, r1
|
|
8008840: 813b strh r3, [r7, #8]
|
|
8008842: 4613 mov r3, r2
|
|
8008844: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
8008846: 88fb ldrh r3, [r7, #6]
|
|
8008848: b2da uxtb r2, r3
|
|
800884a: 8979 ldrh r1, [r7, #10]
|
|
800884c: 4b20 ldr r3, [pc, #128] ; (80088d0 <I2C_RequestMemoryRead+0xa4>)
|
|
800884e: 9300 str r3, [sp, #0]
|
|
8008850: 2300 movs r3, #0
|
|
8008852: 68f8 ldr r0, [r7, #12]
|
|
8008854: f000 f984 bl 8008b60 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8008858: 69fa ldr r2, [r7, #28]
|
|
800885a: 69b9 ldr r1, [r7, #24]
|
|
800885c: 68f8 ldr r0, [r7, #12]
|
|
800885e: f000 f89d bl 800899c <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8008862: 4603 mov r3, r0
|
|
8008864: 2b00 cmp r3, #0
|
|
8008866: d001 beq.n 800886c <I2C_RequestMemoryRead+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
8008868: 2301 movs r3, #1
|
|
800886a: e02c b.n 80088c6 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
800886c: 88fb ldrh r3, [r7, #6]
|
|
800886e: 2b01 cmp r3, #1
|
|
8008870: d105 bne.n 800887e <I2C_RequestMemoryRead+0x52>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8008872: 893b ldrh r3, [r7, #8]
|
|
8008874: b2da uxtb r2, r3
|
|
8008876: 68fb ldr r3, [r7, #12]
|
|
8008878: 681b ldr r3, [r3, #0]
|
|
800887a: 629a str r2, [r3, #40] ; 0x28
|
|
800887c: e015 b.n 80088aa <I2C_RequestMemoryRead+0x7e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
800887e: 893b ldrh r3, [r7, #8]
|
|
8008880: 0a1b lsrs r3, r3, #8
|
|
8008882: b29b uxth r3, r3
|
|
8008884: b2da uxtb r2, r3
|
|
8008886: 68fb ldr r3, [r7, #12]
|
|
8008888: 681b ldr r3, [r3, #0]
|
|
800888a: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800888c: 69fa ldr r2, [r7, #28]
|
|
800888e: 69b9 ldr r1, [r7, #24]
|
|
8008890: 68f8 ldr r0, [r7, #12]
|
|
8008892: f000 f883 bl 800899c <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8008896: 4603 mov r3, r0
|
|
8008898: 2b00 cmp r3, #0
|
|
800889a: d001 beq.n 80088a0 <I2C_RequestMemoryRead+0x74>
|
|
{
|
|
return HAL_ERROR;
|
|
800889c: 2301 movs r3, #1
|
|
800889e: e012 b.n 80088c6 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80088a0: 893b ldrh r3, [r7, #8]
|
|
80088a2: b2da uxtb r2, r3
|
|
80088a4: 68fb ldr r3, [r7, #12]
|
|
80088a6: 681b ldr r3, [r3, #0]
|
|
80088a8: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
80088aa: 69fb ldr r3, [r7, #28]
|
|
80088ac: 9300 str r3, [sp, #0]
|
|
80088ae: 69bb ldr r3, [r7, #24]
|
|
80088b0: 2200 movs r2, #0
|
|
80088b2: 2140 movs r1, #64 ; 0x40
|
|
80088b4: 68f8 ldr r0, [r7, #12]
|
|
80088b6: f000 f831 bl 800891c <I2C_WaitOnFlagUntilTimeout>
|
|
80088ba: 4603 mov r3, r0
|
|
80088bc: 2b00 cmp r3, #0
|
|
80088be: d001 beq.n 80088c4 <I2C_RequestMemoryRead+0x98>
|
|
{
|
|
return HAL_ERROR;
|
|
80088c0: 2301 movs r3, #1
|
|
80088c2: e000 b.n 80088c6 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80088c4: 2300 movs r3, #0
|
|
}
|
|
80088c6: 4618 mov r0, r3
|
|
80088c8: 3710 adds r7, #16
|
|
80088ca: 46bd mov sp, r7
|
|
80088cc: bd80 pop {r7, pc}
|
|
80088ce: bf00 nop
|
|
80088d0: 80002000 .word 0x80002000
|
|
|
|
080088d4 <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80088d4: b480 push {r7}
|
|
80088d6: b083 sub sp, #12
|
|
80088d8: af00 add r7, sp, #0
|
|
80088da: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
80088dc: 687b ldr r3, [r7, #4]
|
|
80088de: 681b ldr r3, [r3, #0]
|
|
80088e0: 699b ldr r3, [r3, #24]
|
|
80088e2: f003 0302 and.w r3, r3, #2
|
|
80088e6: 2b02 cmp r3, #2
|
|
80088e8: d103 bne.n 80088f2 <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
80088ea: 687b ldr r3, [r7, #4]
|
|
80088ec: 681b ldr r3, [r3, #0]
|
|
80088ee: 2200 movs r2, #0
|
|
80088f0: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
80088f2: 687b ldr r3, [r7, #4]
|
|
80088f4: 681b ldr r3, [r3, #0]
|
|
80088f6: 699b ldr r3, [r3, #24]
|
|
80088f8: f003 0301 and.w r3, r3, #1
|
|
80088fc: 2b01 cmp r3, #1
|
|
80088fe: d007 beq.n 8008910 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8008900: 687b ldr r3, [r7, #4]
|
|
8008902: 681b ldr r3, [r3, #0]
|
|
8008904: 699a ldr r2, [r3, #24]
|
|
8008906: 687b ldr r3, [r7, #4]
|
|
8008908: 681b ldr r3, [r3, #0]
|
|
800890a: f042 0201 orr.w r2, r2, #1
|
|
800890e: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
8008910: bf00 nop
|
|
8008912: 370c adds r7, #12
|
|
8008914: 46bd mov sp, r7
|
|
8008916: f85d 7b04 ldr.w r7, [sp], #4
|
|
800891a: 4770 bx lr
|
|
|
|
0800891c <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800891c: b580 push {r7, lr}
|
|
800891e: b084 sub sp, #16
|
|
8008920: af00 add r7, sp, #0
|
|
8008922: 60f8 str r0, [r7, #12]
|
|
8008924: 60b9 str r1, [r7, #8]
|
|
8008926: 603b str r3, [r7, #0]
|
|
8008928: 4613 mov r3, r2
|
|
800892a: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
800892c: e022 b.n 8008974 <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800892e: 683b ldr r3, [r7, #0]
|
|
8008930: f1b3 3fff cmp.w r3, #4294967295
|
|
8008934: d01e beq.n 8008974 <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8008936: f7fc fcd3 bl 80052e0 <HAL_GetTick>
|
|
800893a: 4602 mov r2, r0
|
|
800893c: 69bb ldr r3, [r7, #24]
|
|
800893e: 1ad3 subs r3, r2, r3
|
|
8008940: 683a ldr r2, [r7, #0]
|
|
8008942: 429a cmp r2, r3
|
|
8008944: d302 bcc.n 800894c <I2C_WaitOnFlagUntilTimeout+0x30>
|
|
8008946: 683b ldr r3, [r7, #0]
|
|
8008948: 2b00 cmp r3, #0
|
|
800894a: d113 bne.n 8008974 <I2C_WaitOnFlagUntilTimeout+0x58>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800894c: 68fb ldr r3, [r7, #12]
|
|
800894e: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8008950: f043 0220 orr.w r2, r3, #32
|
|
8008954: 68fb ldr r3, [r7, #12]
|
|
8008956: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008958: 68fb ldr r3, [r7, #12]
|
|
800895a: 2220 movs r2, #32
|
|
800895c: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008960: 68fb ldr r3, [r7, #12]
|
|
8008962: 2200 movs r2, #0
|
|
8008964: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008968: 68fb ldr r3, [r7, #12]
|
|
800896a: 2200 movs r2, #0
|
|
800896c: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
return HAL_ERROR;
|
|
8008970: 2301 movs r3, #1
|
|
8008972: e00f b.n 8008994 <I2C_WaitOnFlagUntilTimeout+0x78>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8008974: 68fb ldr r3, [r7, #12]
|
|
8008976: 681b ldr r3, [r3, #0]
|
|
8008978: 699a ldr r2, [r3, #24]
|
|
800897a: 68bb ldr r3, [r7, #8]
|
|
800897c: 4013 ands r3, r2
|
|
800897e: 68ba ldr r2, [r7, #8]
|
|
8008980: 429a cmp r2, r3
|
|
8008982: bf0c ite eq
|
|
8008984: 2301 moveq r3, #1
|
|
8008986: 2300 movne r3, #0
|
|
8008988: b2db uxtb r3, r3
|
|
800898a: 461a mov r2, r3
|
|
800898c: 79fb ldrb r3, [r7, #7]
|
|
800898e: 429a cmp r2, r3
|
|
8008990: d0cd beq.n 800892e <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8008992: 2300 movs r3, #0
|
|
}
|
|
8008994: 4618 mov r0, r3
|
|
8008996: 3710 adds r7, #16
|
|
8008998: 46bd mov sp, r7
|
|
800899a: bd80 pop {r7, pc}
|
|
|
|
0800899c <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800899c: b580 push {r7, lr}
|
|
800899e: b084 sub sp, #16
|
|
80089a0: af00 add r7, sp, #0
|
|
80089a2: 60f8 str r0, [r7, #12]
|
|
80089a4: 60b9 str r1, [r7, #8]
|
|
80089a6: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
80089a8: e02c b.n 8008a04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80089aa: 687a ldr r2, [r7, #4]
|
|
80089ac: 68b9 ldr r1, [r7, #8]
|
|
80089ae: 68f8 ldr r0, [r7, #12]
|
|
80089b0: f000 f870 bl 8008a94 <I2C_IsAcknowledgeFailed>
|
|
80089b4: 4603 mov r3, r0
|
|
80089b6: 2b00 cmp r3, #0
|
|
80089b8: d001 beq.n 80089be <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80089ba: 2301 movs r3, #1
|
|
80089bc: e02a b.n 8008a14 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80089be: 68bb ldr r3, [r7, #8]
|
|
80089c0: f1b3 3fff cmp.w r3, #4294967295
|
|
80089c4: d01e beq.n 8008a04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80089c6: f7fc fc8b bl 80052e0 <HAL_GetTick>
|
|
80089ca: 4602 mov r2, r0
|
|
80089cc: 687b ldr r3, [r7, #4]
|
|
80089ce: 1ad3 subs r3, r2, r3
|
|
80089d0: 68ba ldr r2, [r7, #8]
|
|
80089d2: 429a cmp r2, r3
|
|
80089d4: d302 bcc.n 80089dc <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
80089d6: 68bb ldr r3, [r7, #8]
|
|
80089d8: 2b00 cmp r3, #0
|
|
80089da: d113 bne.n 8008a04 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80089dc: 68fb ldr r3, [r7, #12]
|
|
80089de: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80089e0: f043 0220 orr.w r2, r3, #32
|
|
80089e4: 68fb ldr r3, [r7, #12]
|
|
80089e6: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80089e8: 68fb ldr r3, [r7, #12]
|
|
80089ea: 2220 movs r2, #32
|
|
80089ec: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80089f0: 68fb ldr r3, [r7, #12]
|
|
80089f2: 2200 movs r2, #0
|
|
80089f4: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80089f8: 68fb ldr r3, [r7, #12]
|
|
80089fa: 2200 movs r2, #0
|
|
80089fc: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8008a00: 2301 movs r3, #1
|
|
8008a02: e007 b.n 8008a14 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
8008a04: 68fb ldr r3, [r7, #12]
|
|
8008a06: 681b ldr r3, [r3, #0]
|
|
8008a08: 699b ldr r3, [r3, #24]
|
|
8008a0a: f003 0302 and.w r3, r3, #2
|
|
8008a0e: 2b02 cmp r3, #2
|
|
8008a10: d1cb bne.n 80089aa <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8008a12: 2300 movs r3, #0
|
|
}
|
|
8008a14: 4618 mov r0, r3
|
|
8008a16: 3710 adds r7, #16
|
|
8008a18: 46bd mov sp, r7
|
|
8008a1a: bd80 pop {r7, pc}
|
|
|
|
08008a1c <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008a1c: b580 push {r7, lr}
|
|
8008a1e: b084 sub sp, #16
|
|
8008a20: af00 add r7, sp, #0
|
|
8008a22: 60f8 str r0, [r7, #12]
|
|
8008a24: 60b9 str r1, [r7, #8]
|
|
8008a26: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8008a28: e028 b.n 8008a7c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
/* Check if a NACK is detected */
|
|
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8008a2a: 687a ldr r2, [r7, #4]
|
|
8008a2c: 68b9 ldr r1, [r7, #8]
|
|
8008a2e: 68f8 ldr r0, [r7, #12]
|
|
8008a30: f000 f830 bl 8008a94 <I2C_IsAcknowledgeFailed>
|
|
8008a34: 4603 mov r3, r0
|
|
8008a36: 2b00 cmp r3, #0
|
|
8008a38: d001 beq.n 8008a3e <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
8008a3a: 2301 movs r3, #1
|
|
8008a3c: e026 b.n 8008a8c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8008a3e: f7fc fc4f bl 80052e0 <HAL_GetTick>
|
|
8008a42: 4602 mov r2, r0
|
|
8008a44: 687b ldr r3, [r7, #4]
|
|
8008a46: 1ad3 subs r3, r2, r3
|
|
8008a48: 68ba ldr r2, [r7, #8]
|
|
8008a4a: 429a cmp r2, r3
|
|
8008a4c: d302 bcc.n 8008a54 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
8008a4e: 68bb ldr r3, [r7, #8]
|
|
8008a50: 2b00 cmp r3, #0
|
|
8008a52: d113 bne.n 8008a7c <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8008a54: 68fb ldr r3, [r7, #12]
|
|
8008a56: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8008a58: f043 0220 orr.w r2, r3, #32
|
|
8008a5c: 68fb ldr r3, [r7, #12]
|
|
8008a5e: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008a60: 68fb ldr r3, [r7, #12]
|
|
8008a62: 2220 movs r2, #32
|
|
8008a64: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008a68: 68fb ldr r3, [r7, #12]
|
|
8008a6a: 2200 movs r2, #0
|
|
8008a6c: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008a70: 68fb ldr r3, [r7, #12]
|
|
8008a72: 2200 movs r2, #0
|
|
8008a74: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8008a78: 2301 movs r3, #1
|
|
8008a7a: e007 b.n 8008a8c <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8008a7c: 68fb ldr r3, [r7, #12]
|
|
8008a7e: 681b ldr r3, [r3, #0]
|
|
8008a80: 699b ldr r3, [r3, #24]
|
|
8008a82: f003 0320 and.w r3, r3, #32
|
|
8008a86: 2b20 cmp r3, #32
|
|
8008a88: d1cf bne.n 8008a2a <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8008a8a: 2300 movs r3, #0
|
|
}
|
|
8008a8c: 4618 mov r0, r3
|
|
8008a8e: 3710 adds r7, #16
|
|
8008a90: 46bd mov sp, r7
|
|
8008a92: bd80 pop {r7, pc}
|
|
|
|
08008a94 <I2C_IsAcknowledgeFailed>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8008a94: b580 push {r7, lr}
|
|
8008a96: b084 sub sp, #16
|
|
8008a98: af00 add r7, sp, #0
|
|
8008a9a: 60f8 str r0, [r7, #12]
|
|
8008a9c: 60b9 str r1, [r7, #8]
|
|
8008a9e: 607a str r2, [r7, #4]
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
|
8008aa0: 68fb ldr r3, [r7, #12]
|
|
8008aa2: 681b ldr r3, [r3, #0]
|
|
8008aa4: 699b ldr r3, [r3, #24]
|
|
8008aa6: f003 0310 and.w r3, r3, #16
|
|
8008aaa: 2b10 cmp r3, #16
|
|
8008aac: d151 bne.n 8008b52 <I2C_IsAcknowledgeFailed+0xbe>
|
|
{
|
|
/* Wait until STOP Flag is reset */
|
|
/* AutoEnd should be initiate after AF */
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8008aae: e022 b.n 8008af6 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8008ab0: 68bb ldr r3, [r7, #8]
|
|
8008ab2: f1b3 3fff cmp.w r3, #4294967295
|
|
8008ab6: d01e beq.n 8008af6 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8008ab8: f7fc fc12 bl 80052e0 <HAL_GetTick>
|
|
8008abc: 4602 mov r2, r0
|
|
8008abe: 687b ldr r3, [r7, #4]
|
|
8008ac0: 1ad3 subs r3, r2, r3
|
|
8008ac2: 68ba ldr r2, [r7, #8]
|
|
8008ac4: 429a cmp r2, r3
|
|
8008ac6: d302 bcc.n 8008ace <I2C_IsAcknowledgeFailed+0x3a>
|
|
8008ac8: 68bb ldr r3, [r7, #8]
|
|
8008aca: 2b00 cmp r3, #0
|
|
8008acc: d113 bne.n 8008af6 <I2C_IsAcknowledgeFailed+0x62>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8008ace: 68fb ldr r3, [r7, #12]
|
|
8008ad0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8008ad2: f043 0220 orr.w r2, r3, #32
|
|
8008ad6: 68fb ldr r3, [r7, #12]
|
|
8008ad8: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008ada: 68fb ldr r3, [r7, #12]
|
|
8008adc: 2220 movs r2, #32
|
|
8008ade: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008ae2: 68fb ldr r3, [r7, #12]
|
|
8008ae4: 2200 movs r2, #0
|
|
8008ae6: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008aea: 68fb ldr r3, [r7, #12]
|
|
8008aec: 2200 movs r2, #0
|
|
8008aee: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8008af2: 2301 movs r3, #1
|
|
8008af4: e02e b.n 8008b54 <I2C_IsAcknowledgeFailed+0xc0>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8008af6: 68fb ldr r3, [r7, #12]
|
|
8008af8: 681b ldr r3, [r3, #0]
|
|
8008afa: 699b ldr r3, [r3, #24]
|
|
8008afc: f003 0320 and.w r3, r3, #32
|
|
8008b00: 2b20 cmp r3, #32
|
|
8008b02: d1d5 bne.n 8008ab0 <I2C_IsAcknowledgeFailed+0x1c>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8008b04: 68fb ldr r3, [r7, #12]
|
|
8008b06: 681b ldr r3, [r3, #0]
|
|
8008b08: 2210 movs r2, #16
|
|
8008b0a: 61da str r2, [r3, #28]
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8008b0c: 68fb ldr r3, [r7, #12]
|
|
8008b0e: 681b ldr r3, [r3, #0]
|
|
8008b10: 2220 movs r2, #32
|
|
8008b12: 61da str r2, [r3, #28]
|
|
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
8008b14: 68f8 ldr r0, [r7, #12]
|
|
8008b16: f7ff fedd bl 80088d4 <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8008b1a: 68fb ldr r3, [r7, #12]
|
|
8008b1c: 681b ldr r3, [r3, #0]
|
|
8008b1e: 6859 ldr r1, [r3, #4]
|
|
8008b20: 68fb ldr r3, [r7, #12]
|
|
8008b22: 681a ldr r2, [r3, #0]
|
|
8008b24: 4b0d ldr r3, [pc, #52] ; (8008b5c <I2C_IsAcknowledgeFailed+0xc8>)
|
|
8008b26: 400b ands r3, r1
|
|
8008b28: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
|
8008b2a: 68fb ldr r3, [r7, #12]
|
|
8008b2c: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8008b2e: f043 0204 orr.w r2, r3, #4
|
|
8008b32: 68fb ldr r3, [r7, #12]
|
|
8008b34: 645a str r2, [r3, #68] ; 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008b36: 68fb ldr r3, [r7, #12]
|
|
8008b38: 2220 movs r2, #32
|
|
8008b3a: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8008b3e: 68fb ldr r3, [r7, #12]
|
|
8008b40: 2200 movs r2, #0
|
|
8008b42: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008b46: 68fb ldr r3, [r7, #12]
|
|
8008b48: 2200 movs r2, #0
|
|
8008b4a: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_ERROR;
|
|
8008b4e: 2301 movs r3, #1
|
|
8008b50: e000 b.n 8008b54 <I2C_IsAcknowledgeFailed+0xc0>
|
|
}
|
|
return HAL_OK;
|
|
8008b52: 2300 movs r3, #0
|
|
}
|
|
8008b54: 4618 mov r0, r3
|
|
8008b56: 3710 adds r7, #16
|
|
8008b58: 46bd mov sp, r7
|
|
8008b5a: bd80 pop {r7, pc}
|
|
8008b5c: fe00e800 .word 0xfe00e800
|
|
|
|
08008b60 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
|
|
{
|
|
8008b60: b480 push {r7}
|
|
8008b62: b085 sub sp, #20
|
|
8008b64: af00 add r7, sp, #0
|
|
8008b66: 60f8 str r0, [r7, #12]
|
|
8008b68: 607b str r3, [r7, #4]
|
|
8008b6a: 460b mov r3, r1
|
|
8008b6c: 817b strh r3, [r7, #10]
|
|
8008b6e: 4613 mov r3, r2
|
|
8008b70: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
|
|
8008b72: 68fb ldr r3, [r7, #12]
|
|
8008b74: 681b ldr r3, [r3, #0]
|
|
8008b76: 685a ldr r2, [r3, #4]
|
|
8008b78: 69bb ldr r3, [r7, #24]
|
|
8008b7a: 0d5b lsrs r3, r3, #21
|
|
8008b7c: f403 6180 and.w r1, r3, #1024 ; 0x400
|
|
8008b80: 4b0d ldr r3, [pc, #52] ; (8008bb8 <I2C_TransferConfig+0x58>)
|
|
8008b82: 430b orrs r3, r1
|
|
8008b84: 43db mvns r3, r3
|
|
8008b86: ea02 0103 and.w r1, r2, r3
|
|
8008b8a: 897b ldrh r3, [r7, #10]
|
|
8008b8c: f3c3 0209 ubfx r2, r3, #0, #10
|
|
8008b90: 7a7b ldrb r3, [r7, #9]
|
|
8008b92: 041b lsls r3, r3, #16
|
|
8008b94: f403 037f and.w r3, r3, #16711680 ; 0xff0000
|
|
8008b98: 431a orrs r2, r3
|
|
8008b9a: 687b ldr r3, [r7, #4]
|
|
8008b9c: 431a orrs r2, r3
|
|
8008b9e: 69bb ldr r3, [r7, #24]
|
|
8008ba0: 431a orrs r2, r3
|
|
8008ba2: 68fb ldr r3, [r7, #12]
|
|
8008ba4: 681b ldr r3, [r3, #0]
|
|
8008ba6: 430a orrs r2, r1
|
|
8008ba8: 605a str r2, [r3, #4]
|
|
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
|
|
}
|
|
8008baa: bf00 nop
|
|
8008bac: 3714 adds r7, #20
|
|
8008bae: 46bd mov sp, r7
|
|
8008bb0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008bb4: 4770 bx lr
|
|
8008bb6: bf00 nop
|
|
8008bb8: 03ff63ff .word 0x03ff63ff
|
|
|
|
08008bbc <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8008bbc: b480 push {r7}
|
|
8008bbe: b083 sub sp, #12
|
|
8008bc0: af00 add r7, sp, #0
|
|
8008bc2: 6078 str r0, [r7, #4]
|
|
8008bc4: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8008bc6: 687b ldr r3, [r7, #4]
|
|
8008bc8: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8008bcc: b2db uxtb r3, r3
|
|
8008bce: 2b20 cmp r3, #32
|
|
8008bd0: d138 bne.n 8008c44 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8008bd2: 687b ldr r3, [r7, #4]
|
|
8008bd4: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8008bd8: 2b01 cmp r3, #1
|
|
8008bda: d101 bne.n 8008be0 <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
8008bdc: 2302 movs r3, #2
|
|
8008bde: e032 b.n 8008c46 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
8008be0: 687b ldr r3, [r7, #4]
|
|
8008be2: 2201 movs r2, #1
|
|
8008be4: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8008be8: 687b ldr r3, [r7, #4]
|
|
8008bea: 2224 movs r2, #36 ; 0x24
|
|
8008bec: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8008bf0: 687b ldr r3, [r7, #4]
|
|
8008bf2: 681b ldr r3, [r3, #0]
|
|
8008bf4: 681a ldr r2, [r3, #0]
|
|
8008bf6: 687b ldr r3, [r7, #4]
|
|
8008bf8: 681b ldr r3, [r3, #0]
|
|
8008bfa: f022 0201 bic.w r2, r2, #1
|
|
8008bfe: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
8008c00: 687b ldr r3, [r7, #4]
|
|
8008c02: 681b ldr r3, [r3, #0]
|
|
8008c04: 681a ldr r2, [r3, #0]
|
|
8008c06: 687b ldr r3, [r7, #4]
|
|
8008c08: 681b ldr r3, [r3, #0]
|
|
8008c0a: f422 5280 bic.w r2, r2, #4096 ; 0x1000
|
|
8008c0e: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
8008c10: 687b ldr r3, [r7, #4]
|
|
8008c12: 681b ldr r3, [r3, #0]
|
|
8008c14: 6819 ldr r1, [r3, #0]
|
|
8008c16: 687b ldr r3, [r7, #4]
|
|
8008c18: 681b ldr r3, [r3, #0]
|
|
8008c1a: 683a ldr r2, [r7, #0]
|
|
8008c1c: 430a orrs r2, r1
|
|
8008c1e: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8008c20: 687b ldr r3, [r7, #4]
|
|
8008c22: 681b ldr r3, [r3, #0]
|
|
8008c24: 681a ldr r2, [r3, #0]
|
|
8008c26: 687b ldr r3, [r7, #4]
|
|
8008c28: 681b ldr r3, [r3, #0]
|
|
8008c2a: f042 0201 orr.w r2, r2, #1
|
|
8008c2e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008c30: 687b ldr r3, [r7, #4]
|
|
8008c32: 2220 movs r2, #32
|
|
8008c34: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008c38: 687b ldr r3, [r7, #4]
|
|
8008c3a: 2200 movs r2, #0
|
|
8008c3c: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8008c40: 2300 movs r3, #0
|
|
8008c42: e000 b.n 8008c46 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008c44: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008c46: 4618 mov r0, r3
|
|
8008c48: 370c adds r7, #12
|
|
8008c4a: 46bd mov sp, r7
|
|
8008c4c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008c50: 4770 bx lr
|
|
|
|
08008c52 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8008c52: b480 push {r7}
|
|
8008c54: b085 sub sp, #20
|
|
8008c56: af00 add r7, sp, #0
|
|
8008c58: 6078 str r0, [r7, #4]
|
|
8008c5a: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8008c5c: 687b ldr r3, [r7, #4]
|
|
8008c5e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
|
|
8008c62: b2db uxtb r3, r3
|
|
8008c64: 2b20 cmp r3, #32
|
|
8008c66: d139 bne.n 8008cdc <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8008c68: 687b ldr r3, [r7, #4]
|
|
8008c6a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
|
|
8008c6e: 2b01 cmp r3, #1
|
|
8008c70: d101 bne.n 8008c76 <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
8008c72: 2302 movs r3, #2
|
|
8008c74: e033 b.n 8008cde <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
8008c76: 687b ldr r3, [r7, #4]
|
|
8008c78: 2201 movs r2, #1
|
|
8008c7a: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8008c7e: 687b ldr r3, [r7, #4]
|
|
8008c80: 2224 movs r2, #36 ; 0x24
|
|
8008c82: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8008c86: 687b ldr r3, [r7, #4]
|
|
8008c88: 681b ldr r3, [r3, #0]
|
|
8008c8a: 681a ldr r2, [r3, #0]
|
|
8008c8c: 687b ldr r3, [r7, #4]
|
|
8008c8e: 681b ldr r3, [r3, #0]
|
|
8008c90: f022 0201 bic.w r2, r2, #1
|
|
8008c94: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
8008c96: 687b ldr r3, [r7, #4]
|
|
8008c98: 681b ldr r3, [r3, #0]
|
|
8008c9a: 681b ldr r3, [r3, #0]
|
|
8008c9c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
8008c9e: 68fb ldr r3, [r7, #12]
|
|
8008ca0: f423 6370 bic.w r3, r3, #3840 ; 0xf00
|
|
8008ca4: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
8008ca6: 683b ldr r3, [r7, #0]
|
|
8008ca8: 021b lsls r3, r3, #8
|
|
8008caa: 68fa ldr r2, [r7, #12]
|
|
8008cac: 4313 orrs r3, r2
|
|
8008cae: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
8008cb0: 687b ldr r3, [r7, #4]
|
|
8008cb2: 681b ldr r3, [r3, #0]
|
|
8008cb4: 68fa ldr r2, [r7, #12]
|
|
8008cb6: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8008cb8: 687b ldr r3, [r7, #4]
|
|
8008cba: 681b ldr r3, [r3, #0]
|
|
8008cbc: 681a ldr r2, [r3, #0]
|
|
8008cbe: 687b ldr r3, [r7, #4]
|
|
8008cc0: 681b ldr r3, [r3, #0]
|
|
8008cc2: f042 0201 orr.w r2, r2, #1
|
|
8008cc6: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8008cc8: 687b ldr r3, [r7, #4]
|
|
8008cca: 2220 movs r2, #32
|
|
8008ccc: f883 2041 strb.w r2, [r3, #65] ; 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8008cd0: 687b ldr r3, [r7, #4]
|
|
8008cd2: 2200 movs r2, #0
|
|
8008cd4: f883 2040 strb.w r2, [r3, #64] ; 0x40
|
|
|
|
return HAL_OK;
|
|
8008cd8: 2300 movs r3, #0
|
|
8008cda: e000 b.n 8008cde <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8008cdc: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8008cde: 4618 mov r0, r3
|
|
8008ce0: 3714 adds r7, #20
|
|
8008ce2: 46bd mov sp, r7
|
|
8008ce4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ce8: 4770 bx lr
|
|
...
|
|
|
|
08008cec <HAL_LTDC_Init>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8008cec: b580 push {r7, lr}
|
|
8008cee: b084 sub sp, #16
|
|
8008cf0: af00 add r7, sp, #0
|
|
8008cf2: 6078 str r0, [r7, #4]
|
|
uint32_t tmp, tmp1;
|
|
|
|
/* Check the LTDC peripheral state */
|
|
if (hltdc == NULL)
|
|
8008cf4: 687b ldr r3, [r7, #4]
|
|
8008cf6: 2b00 cmp r3, #0
|
|
8008cf8: d101 bne.n 8008cfe <HAL_LTDC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8008cfa: 2301 movs r3, #1
|
|
8008cfc: e0bf b.n 8008e7e <HAL_LTDC_Init+0x192>
|
|
}
|
|
/* Init the low level hardware */
|
|
hltdc->MspInitCallback(hltdc);
|
|
}
|
|
#else
|
|
if (hltdc->State == HAL_LTDC_STATE_RESET)
|
|
8008cfe: 687b ldr r3, [r7, #4]
|
|
8008d00: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
|
|
8008d04: b2db uxtb r3, r3
|
|
8008d06: 2b00 cmp r3, #0
|
|
8008d08: d106 bne.n 8008d18 <HAL_LTDC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hltdc->Lock = HAL_UNLOCKED;
|
|
8008d0a: 687b ldr r3, [r7, #4]
|
|
8008d0c: 2200 movs r2, #0
|
|
8008d0e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
/* Init the low level hardware */
|
|
HAL_LTDC_MspInit(hltdc);
|
|
8008d12: 6878 ldr r0, [r7, #4]
|
|
8008d14: f7fb fdae bl 8004874 <HAL_LTDC_MspInit>
|
|
}
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
8008d18: 687b ldr r3, [r7, #4]
|
|
8008d1a: 2202 movs r2, #2
|
|
8008d1c: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Configure the HS, VS, DE and PC polarity */
|
|
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
|
|
8008d20: 687b ldr r3, [r7, #4]
|
|
8008d22: 681b ldr r3, [r3, #0]
|
|
8008d24: 699a ldr r2, [r3, #24]
|
|
8008d26: 687b ldr r3, [r7, #4]
|
|
8008d28: 681b ldr r3, [r3, #0]
|
|
8008d2a: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
|
|
8008d2e: 619a str r2, [r3, #24]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8008d30: 687b ldr r3, [r7, #4]
|
|
8008d32: 681b ldr r3, [r3, #0]
|
|
8008d34: 6999 ldr r1, [r3, #24]
|
|
8008d36: 687b ldr r3, [r7, #4]
|
|
8008d38: 685a ldr r2, [r3, #4]
|
|
8008d3a: 687b ldr r3, [r7, #4]
|
|
8008d3c: 689b ldr r3, [r3, #8]
|
|
8008d3e: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
8008d40: 687b ldr r3, [r7, #4]
|
|
8008d42: 68db ldr r3, [r3, #12]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8008d44: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
8008d46: 687b ldr r3, [r7, #4]
|
|
8008d48: 691b ldr r3, [r3, #16]
|
|
8008d4a: 431a orrs r2, r3
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8008d4c: 687b ldr r3, [r7, #4]
|
|
8008d4e: 681b ldr r3, [r3, #0]
|
|
8008d50: 430a orrs r2, r1
|
|
8008d52: 619a str r2, [r3, #24]
|
|
|
|
/* Set Synchronization size */
|
|
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
|
|
8008d54: 687b ldr r3, [r7, #4]
|
|
8008d56: 681b ldr r3, [r3, #0]
|
|
8008d58: 6899 ldr r1, [r3, #8]
|
|
8008d5a: 687b ldr r3, [r7, #4]
|
|
8008d5c: 681a ldr r2, [r3, #0]
|
|
8008d5e: 4b4a ldr r3, [pc, #296] ; (8008e88 <HAL_LTDC_Init+0x19c>)
|
|
8008d60: 400b ands r3, r1
|
|
8008d62: 6093 str r3, [r2, #8]
|
|
tmp = (hltdc->Init.HorizontalSync << 16U);
|
|
8008d64: 687b ldr r3, [r7, #4]
|
|
8008d66: 695b ldr r3, [r3, #20]
|
|
8008d68: 041b lsls r3, r3, #16
|
|
8008d6a: 60fb str r3, [r7, #12]
|
|
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
|
|
8008d6c: 687b ldr r3, [r7, #4]
|
|
8008d6e: 681b ldr r3, [r3, #0]
|
|
8008d70: 6899 ldr r1, [r3, #8]
|
|
8008d72: 687b ldr r3, [r7, #4]
|
|
8008d74: 699a ldr r2, [r3, #24]
|
|
8008d76: 68fb ldr r3, [r7, #12]
|
|
8008d78: 431a orrs r2, r3
|
|
8008d7a: 687b ldr r3, [r7, #4]
|
|
8008d7c: 681b ldr r3, [r3, #0]
|
|
8008d7e: 430a orrs r2, r1
|
|
8008d80: 609a str r2, [r3, #8]
|
|
|
|
/* Set Accumulated Back porch */
|
|
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
|
|
8008d82: 687b ldr r3, [r7, #4]
|
|
8008d84: 681b ldr r3, [r3, #0]
|
|
8008d86: 68d9 ldr r1, [r3, #12]
|
|
8008d88: 687b ldr r3, [r7, #4]
|
|
8008d8a: 681a ldr r2, [r3, #0]
|
|
8008d8c: 4b3e ldr r3, [pc, #248] ; (8008e88 <HAL_LTDC_Init+0x19c>)
|
|
8008d8e: 400b ands r3, r1
|
|
8008d90: 60d3 str r3, [r2, #12]
|
|
tmp = (hltdc->Init.AccumulatedHBP << 16U);
|
|
8008d92: 687b ldr r3, [r7, #4]
|
|
8008d94: 69db ldr r3, [r3, #28]
|
|
8008d96: 041b lsls r3, r3, #16
|
|
8008d98: 60fb str r3, [r7, #12]
|
|
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
|
|
8008d9a: 687b ldr r3, [r7, #4]
|
|
8008d9c: 681b ldr r3, [r3, #0]
|
|
8008d9e: 68d9 ldr r1, [r3, #12]
|
|
8008da0: 687b ldr r3, [r7, #4]
|
|
8008da2: 6a1a ldr r2, [r3, #32]
|
|
8008da4: 68fb ldr r3, [r7, #12]
|
|
8008da6: 431a orrs r2, r3
|
|
8008da8: 687b ldr r3, [r7, #4]
|
|
8008daa: 681b ldr r3, [r3, #0]
|
|
8008dac: 430a orrs r2, r1
|
|
8008dae: 60da str r2, [r3, #12]
|
|
|
|
/* Set Accumulated Active Width */
|
|
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
|
|
8008db0: 687b ldr r3, [r7, #4]
|
|
8008db2: 681b ldr r3, [r3, #0]
|
|
8008db4: 6919 ldr r1, [r3, #16]
|
|
8008db6: 687b ldr r3, [r7, #4]
|
|
8008db8: 681a ldr r2, [r3, #0]
|
|
8008dba: 4b33 ldr r3, [pc, #204] ; (8008e88 <HAL_LTDC_Init+0x19c>)
|
|
8008dbc: 400b ands r3, r1
|
|
8008dbe: 6113 str r3, [r2, #16]
|
|
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
|
|
8008dc0: 687b ldr r3, [r7, #4]
|
|
8008dc2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8008dc4: 041b lsls r3, r3, #16
|
|
8008dc6: 60fb str r3, [r7, #12]
|
|
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
|
|
8008dc8: 687b ldr r3, [r7, #4]
|
|
8008dca: 681b ldr r3, [r3, #0]
|
|
8008dcc: 6919 ldr r1, [r3, #16]
|
|
8008dce: 687b ldr r3, [r7, #4]
|
|
8008dd0: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
8008dd2: 68fb ldr r3, [r7, #12]
|
|
8008dd4: 431a orrs r2, r3
|
|
8008dd6: 687b ldr r3, [r7, #4]
|
|
8008dd8: 681b ldr r3, [r3, #0]
|
|
8008dda: 430a orrs r2, r1
|
|
8008ddc: 611a str r2, [r3, #16]
|
|
|
|
/* Set Total Width */
|
|
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
|
|
8008dde: 687b ldr r3, [r7, #4]
|
|
8008de0: 681b ldr r3, [r3, #0]
|
|
8008de2: 6959 ldr r1, [r3, #20]
|
|
8008de4: 687b ldr r3, [r7, #4]
|
|
8008de6: 681a ldr r2, [r3, #0]
|
|
8008de8: 4b27 ldr r3, [pc, #156] ; (8008e88 <HAL_LTDC_Init+0x19c>)
|
|
8008dea: 400b ands r3, r1
|
|
8008dec: 6153 str r3, [r2, #20]
|
|
tmp = (hltdc->Init.TotalWidth << 16U);
|
|
8008dee: 687b ldr r3, [r7, #4]
|
|
8008df0: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8008df2: 041b lsls r3, r3, #16
|
|
8008df4: 60fb str r3, [r7, #12]
|
|
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
|
|
8008df6: 687b ldr r3, [r7, #4]
|
|
8008df8: 681b ldr r3, [r3, #0]
|
|
8008dfa: 6959 ldr r1, [r3, #20]
|
|
8008dfc: 687b ldr r3, [r7, #4]
|
|
8008dfe: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
8008e00: 68fb ldr r3, [r7, #12]
|
|
8008e02: 431a orrs r2, r3
|
|
8008e04: 687b ldr r3, [r7, #4]
|
|
8008e06: 681b ldr r3, [r3, #0]
|
|
8008e08: 430a orrs r2, r1
|
|
8008e0a: 615a str r2, [r3, #20]
|
|
|
|
/* Set the background color value */
|
|
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
|
|
8008e0c: 687b ldr r3, [r7, #4]
|
|
8008e0e: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
|
|
8008e12: 021b lsls r3, r3, #8
|
|
8008e14: 60fb str r3, [r7, #12]
|
|
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
|
|
8008e16: 687b ldr r3, [r7, #4]
|
|
8008e18: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
|
|
8008e1c: 041b lsls r3, r3, #16
|
|
8008e1e: 60bb str r3, [r7, #8]
|
|
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
|
|
8008e20: 687b ldr r3, [r7, #4]
|
|
8008e22: 681b ldr r3, [r3, #0]
|
|
8008e24: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
8008e26: 687b ldr r3, [r7, #4]
|
|
8008e28: 681b ldr r3, [r3, #0]
|
|
8008e2a: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
|
|
8008e2e: 62da str r2, [r3, #44] ; 0x2c
|
|
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
|
|
8008e30: 687b ldr r3, [r7, #4]
|
|
8008e32: 681b ldr r3, [r3, #0]
|
|
8008e34: 6ad9 ldr r1, [r3, #44] ; 0x2c
|
|
8008e36: 68ba ldr r2, [r7, #8]
|
|
8008e38: 68fb ldr r3, [r7, #12]
|
|
8008e3a: 4313 orrs r3, r2
|
|
8008e3c: 687a ldr r2, [r7, #4]
|
|
8008e3e: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
|
|
8008e42: 431a orrs r2, r3
|
|
8008e44: 687b ldr r3, [r7, #4]
|
|
8008e46: 681b ldr r3, [r3, #0]
|
|
8008e48: 430a orrs r2, r1
|
|
8008e4a: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Enable the Transfer Error and FIFO underrun interrupts */
|
|
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
|
|
8008e4c: 687b ldr r3, [r7, #4]
|
|
8008e4e: 681b ldr r3, [r3, #0]
|
|
8008e50: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8008e52: 687b ldr r3, [r7, #4]
|
|
8008e54: 681b ldr r3, [r3, #0]
|
|
8008e56: f042 0206 orr.w r2, r2, #6
|
|
8008e5a: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Enable LTDC by setting LTDCEN bit */
|
|
__HAL_LTDC_ENABLE(hltdc);
|
|
8008e5c: 687b ldr r3, [r7, #4]
|
|
8008e5e: 681b ldr r3, [r3, #0]
|
|
8008e60: 699a ldr r2, [r3, #24]
|
|
8008e62: 687b ldr r3, [r7, #4]
|
|
8008e64: 681b ldr r3, [r3, #0]
|
|
8008e66: f042 0201 orr.w r2, r2, #1
|
|
8008e6a: 619a str r2, [r3, #24]
|
|
|
|
/* Initialize the error code */
|
|
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
|
|
8008e6c: 687b ldr r3, [r7, #4]
|
|
8008e6e: 2200 movs r2, #0
|
|
8008e70: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8008e74: 687b ldr r3, [r7, #4]
|
|
8008e76: 2201 movs r2, #1
|
|
8008e78: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
return HAL_OK;
|
|
8008e7c: 2300 movs r3, #0
|
|
}
|
|
8008e7e: 4618 mov r0, r3
|
|
8008e80: 3710 adds r7, #16
|
|
8008e82: 46bd mov sp, r7
|
|
8008e84: bd80 pop {r7, pc}
|
|
8008e86: bf00 nop
|
|
8008e88: f000f800 .word 0xf000f800
|
|
|
|
08008e8c <HAL_LTDC_IRQHandler>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8008e8c: b580 push {r7, lr}
|
|
8008e8e: b084 sub sp, #16
|
|
8008e90: af00 add r7, sp, #0
|
|
8008e92: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
|
|
8008e94: 687b ldr r3, [r7, #4]
|
|
8008e96: 681b ldr r3, [r3, #0]
|
|
8008e98: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
8008e9a: 60fb str r3, [r7, #12]
|
|
uint32_t itsources = READ_REG(hltdc->Instance->IER);
|
|
8008e9c: 687b ldr r3, [r7, #4]
|
|
8008e9e: 681b ldr r3, [r3, #0]
|
|
8008ea0: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8008ea2: 60bb str r3, [r7, #8]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
|
|
8008ea4: 68fb ldr r3, [r7, #12]
|
|
8008ea6: f003 0304 and.w r3, r3, #4
|
|
8008eaa: 2b00 cmp r3, #0
|
|
8008eac: d023 beq.n 8008ef6 <HAL_LTDC_IRQHandler+0x6a>
|
|
8008eae: 68bb ldr r3, [r7, #8]
|
|
8008eb0: f003 0304 and.w r3, r3, #4
|
|
8008eb4: 2b00 cmp r3, #0
|
|
8008eb6: d01e beq.n 8008ef6 <HAL_LTDC_IRQHandler+0x6a>
|
|
{
|
|
/* Disable the transfer Error interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
|
|
8008eb8: 687b ldr r3, [r7, #4]
|
|
8008eba: 681b ldr r3, [r3, #0]
|
|
8008ebc: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8008ebe: 687b ldr r3, [r7, #4]
|
|
8008ec0: 681b ldr r3, [r3, #0]
|
|
8008ec2: f022 0204 bic.w r2, r2, #4
|
|
8008ec6: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Clear the transfer error flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
|
|
8008ec8: 687b ldr r3, [r7, #4]
|
|
8008eca: 681b ldr r3, [r3, #0]
|
|
8008ecc: 2204 movs r2, #4
|
|
8008ece: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
|
|
8008ed0: 687b ldr r3, [r7, #4]
|
|
8008ed2: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
|
|
8008ed6: f043 0201 orr.w r2, r3, #1
|
|
8008eda: 687b ldr r3, [r7, #4]
|
|
8008edc: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
8008ee0: 687b ldr r3, [r7, #4]
|
|
8008ee2: 2204 movs r2, #4
|
|
8008ee4: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8008ee8: 687b ldr r3, [r7, #4]
|
|
8008eea: 2200 movs r2, #0
|
|
8008eec: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
8008ef0: 6878 ldr r0, [r7, #4]
|
|
8008ef2: f000 f86f bl 8008fd4 <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* FIFO underrun Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
|
|
8008ef6: 68fb ldr r3, [r7, #12]
|
|
8008ef8: f003 0302 and.w r3, r3, #2
|
|
8008efc: 2b00 cmp r3, #0
|
|
8008efe: d023 beq.n 8008f48 <HAL_LTDC_IRQHandler+0xbc>
|
|
8008f00: 68bb ldr r3, [r7, #8]
|
|
8008f02: f003 0302 and.w r3, r3, #2
|
|
8008f06: 2b00 cmp r3, #0
|
|
8008f08: d01e beq.n 8008f48 <HAL_LTDC_IRQHandler+0xbc>
|
|
{
|
|
/* Disable the FIFO underrun interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
|
|
8008f0a: 687b ldr r3, [r7, #4]
|
|
8008f0c: 681b ldr r3, [r3, #0]
|
|
8008f0e: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8008f10: 687b ldr r3, [r7, #4]
|
|
8008f12: 681b ldr r3, [r3, #0]
|
|
8008f14: f022 0202 bic.w r2, r2, #2
|
|
8008f18: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Clear the FIFO underrun flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
|
|
8008f1a: 687b ldr r3, [r7, #4]
|
|
8008f1c: 681b ldr r3, [r3, #0]
|
|
8008f1e: 2202 movs r2, #2
|
|
8008f20: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
|
|
8008f22: 687b ldr r3, [r7, #4]
|
|
8008f24: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
|
|
8008f28: f043 0202 orr.w r2, r3, #2
|
|
8008f2c: 687b ldr r3, [r7, #4]
|
|
8008f2e: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
8008f32: 687b ldr r3, [r7, #4]
|
|
8008f34: 2204 movs r2, #4
|
|
8008f36: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8008f3a: 687b ldr r3, [r7, #4]
|
|
8008f3c: 2200 movs r2, #0
|
|
8008f3e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
8008f42: 6878 ldr r0, [r7, #4]
|
|
8008f44: f000 f846 bl 8008fd4 <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Line Interrupt management ************************************************/
|
|
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
|
|
8008f48: 68fb ldr r3, [r7, #12]
|
|
8008f4a: f003 0301 and.w r3, r3, #1
|
|
8008f4e: 2b00 cmp r3, #0
|
|
8008f50: d01b beq.n 8008f8a <HAL_LTDC_IRQHandler+0xfe>
|
|
8008f52: 68bb ldr r3, [r7, #8]
|
|
8008f54: f003 0301 and.w r3, r3, #1
|
|
8008f58: 2b00 cmp r3, #0
|
|
8008f5a: d016 beq.n 8008f8a <HAL_LTDC_IRQHandler+0xfe>
|
|
{
|
|
/* Disable the Line interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
|
|
8008f5c: 687b ldr r3, [r7, #4]
|
|
8008f5e: 681b ldr r3, [r3, #0]
|
|
8008f60: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8008f62: 687b ldr r3, [r7, #4]
|
|
8008f64: 681b ldr r3, [r3, #0]
|
|
8008f66: f022 0201 bic.w r2, r2, #1
|
|
8008f6a: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Clear the Line interrupt flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
|
|
8008f6c: 687b ldr r3, [r7, #4]
|
|
8008f6e: 681b ldr r3, [r3, #0]
|
|
8008f70: 2201 movs r2, #1
|
|
8008f72: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8008f74: 687b ldr r3, [r7, #4]
|
|
8008f76: 2201 movs r2, #1
|
|
8008f78: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8008f7c: 687b ldr r3, [r7, #4]
|
|
8008f7e: 2200 movs r2, #0
|
|
8008f80: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Line Event callback */
|
|
hltdc->LineEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Line Event callback */
|
|
HAL_LTDC_LineEventCallback(hltdc);
|
|
8008f84: 6878 ldr r0, [r7, #4]
|
|
8008f86: f000 f82f bl 8008fe8 <HAL_LTDC_LineEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Register reload Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
|
|
8008f8a: 68fb ldr r3, [r7, #12]
|
|
8008f8c: f003 0308 and.w r3, r3, #8
|
|
8008f90: 2b00 cmp r3, #0
|
|
8008f92: d01b beq.n 8008fcc <HAL_LTDC_IRQHandler+0x140>
|
|
8008f94: 68bb ldr r3, [r7, #8]
|
|
8008f96: f003 0308 and.w r3, r3, #8
|
|
8008f9a: 2b00 cmp r3, #0
|
|
8008f9c: d016 beq.n 8008fcc <HAL_LTDC_IRQHandler+0x140>
|
|
{
|
|
/* Disable the register reload interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
|
|
8008f9e: 687b ldr r3, [r7, #4]
|
|
8008fa0: 681b ldr r3, [r3, #0]
|
|
8008fa2: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
8008fa4: 687b ldr r3, [r7, #4]
|
|
8008fa6: 681b ldr r3, [r3, #0]
|
|
8008fa8: f022 0208 bic.w r2, r2, #8
|
|
8008fac: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Clear the register reload flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
|
|
8008fae: 687b ldr r3, [r7, #4]
|
|
8008fb0: 681b ldr r3, [r3, #0]
|
|
8008fb2: 2208 movs r2, #8
|
|
8008fb4: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8008fb6: 687b ldr r3, [r7, #4]
|
|
8008fb8: 2201 movs r2, #1
|
|
8008fba: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8008fbe: 687b ldr r3, [r7, #4]
|
|
8008fc0: 2200 movs r2, #0
|
|
8008fc2: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered reload Event callback */
|
|
hltdc->ReloadEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Reload Event callback */
|
|
HAL_LTDC_ReloadEventCallback(hltdc);
|
|
8008fc6: 6878 ldr r0, [r7, #4]
|
|
8008fc8: f000 f818 bl 8008ffc <HAL_LTDC_ReloadEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8008fcc: bf00 nop
|
|
8008fce: 3710 adds r7, #16
|
|
8008fd0: 46bd mov sp, r7
|
|
8008fd2: bd80 pop {r7, pc}
|
|
|
|
08008fd4 <HAL_LTDC_ErrorCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8008fd4: b480 push {r7}
|
|
8008fd6: b083 sub sp, #12
|
|
8008fd8: af00 add r7, sp, #0
|
|
8008fda: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8008fdc: bf00 nop
|
|
8008fde: 370c adds r7, #12
|
|
8008fe0: 46bd mov sp, r7
|
|
8008fe2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008fe6: 4770 bx lr
|
|
|
|
08008fe8 <HAL_LTDC_LineEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8008fe8: b480 push {r7}
|
|
8008fea: b083 sub sp, #12
|
|
8008fec: af00 add r7, sp, #0
|
|
8008fee: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_LineEventCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8008ff0: bf00 nop
|
|
8008ff2: 370c adds r7, #12
|
|
8008ff4: 46bd mov sp, r7
|
|
8008ff6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008ffa: 4770 bx lr
|
|
|
|
08008ffc <HAL_LTDC_ReloadEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8008ffc: b480 push {r7}
|
|
8008ffe: b083 sub sp, #12
|
|
8009000: af00 add r7, sp, #0
|
|
8009002: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8009004: bf00 nop
|
|
8009006: 370c adds r7, #12
|
|
8009008: 46bd mov sp, r7
|
|
800900a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800900e: 4770 bx lr
|
|
|
|
08009010 <HAL_LTDC_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
8009010: b5b0 push {r4, r5, r7, lr}
|
|
8009012: b084 sub sp, #16
|
|
8009014: af00 add r7, sp, #0
|
|
8009016: 60f8 str r0, [r7, #12]
|
|
8009018: 60b9 str r1, [r7, #8]
|
|
800901a: 607a str r2, [r7, #4]
|
|
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
|
|
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
|
|
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hltdc);
|
|
800901c: 68fb ldr r3, [r7, #12]
|
|
800901e: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
|
|
8009022: 2b01 cmp r3, #1
|
|
8009024: d101 bne.n 800902a <HAL_LTDC_ConfigLayer+0x1a>
|
|
8009026: 2302 movs r3, #2
|
|
8009028: e02c b.n 8009084 <HAL_LTDC_ConfigLayer+0x74>
|
|
800902a: 68fb ldr r3, [r7, #12]
|
|
800902c: 2201 movs r2, #1
|
|
800902e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
8009032: 68fb ldr r3, [r7, #12]
|
|
8009034: 2202 movs r2, #2
|
|
8009036: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Copy new layer configuration into handle structure */
|
|
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
|
|
800903a: 68fa ldr r2, [r7, #12]
|
|
800903c: 687b ldr r3, [r7, #4]
|
|
800903e: 2134 movs r1, #52 ; 0x34
|
|
8009040: fb01 f303 mul.w r3, r1, r3
|
|
8009044: 4413 add r3, r2
|
|
8009046: f103 0238 add.w r2, r3, #56 ; 0x38
|
|
800904a: 68bb ldr r3, [r7, #8]
|
|
800904c: 4614 mov r4, r2
|
|
800904e: 461d mov r5, r3
|
|
8009050: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8009052: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8009054: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8009056: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8009058: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800905a: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800905c: 682b ldr r3, [r5, #0]
|
|
800905e: 6023 str r3, [r4, #0]
|
|
|
|
/* Configure the LTDC Layer */
|
|
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
|
|
8009060: 687a ldr r2, [r7, #4]
|
|
8009062: 68b9 ldr r1, [r7, #8]
|
|
8009064: 68f8 ldr r0, [r7, #12]
|
|
8009066: f000 f81f bl 80090a8 <LTDC_SetConfig>
|
|
|
|
/* Set the Immediate Reload type */
|
|
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
|
|
800906a: 68fb ldr r3, [r7, #12]
|
|
800906c: 681b ldr r3, [r3, #0]
|
|
800906e: 2201 movs r2, #1
|
|
8009070: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8009072: 68fb ldr r3, [r7, #12]
|
|
8009074: 2201 movs r2, #1
|
|
8009076: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
800907a: 68fb ldr r3, [r7, #12]
|
|
800907c: 2200 movs r2, #0
|
|
800907e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
|
|
|
|
return HAL_OK;
|
|
8009082: 2300 movs r3, #0
|
|
}
|
|
8009084: 4618 mov r0, r3
|
|
8009086: 3710 adds r7, #16
|
|
8009088: 46bd mov sp, r7
|
|
800908a: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
0800908c <HAL_LTDC_GetState>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
800908c: b480 push {r7}
|
|
800908e: b083 sub sp, #12
|
|
8009090: af00 add r7, sp, #0
|
|
8009092: 6078 str r0, [r7, #4]
|
|
return hltdc->State;
|
|
8009094: 687b ldr r3, [r7, #4]
|
|
8009096: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
|
|
800909a: b2db uxtb r3, r3
|
|
}
|
|
800909c: 4618 mov r0, r3
|
|
800909e: 370c adds r7, #12
|
|
80090a0: 46bd mov sp, r7
|
|
80090a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80090a6: 4770 bx lr
|
|
|
|
080090a8 <LTDC_SetConfig>:
|
|
* @param LayerIdx LTDC Layer index.
|
|
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval None
|
|
*/
|
|
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
80090a8: b480 push {r7}
|
|
80090aa: b089 sub sp, #36 ; 0x24
|
|
80090ac: af00 add r7, sp, #0
|
|
80090ae: 60f8 str r0, [r7, #12]
|
|
80090b0: 60b9 str r1, [r7, #8]
|
|
80090b2: 607a str r2, [r7, #4]
|
|
uint32_t tmp;
|
|
uint32_t tmp1;
|
|
uint32_t tmp2;
|
|
|
|
/* Configure the horizontal start and stop position */
|
|
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
|
|
80090b4: 68bb ldr r3, [r7, #8]
|
|
80090b6: 685a ldr r2, [r3, #4]
|
|
80090b8: 68fb ldr r3, [r7, #12]
|
|
80090ba: 681b ldr r3, [r3, #0]
|
|
80090bc: 68db ldr r3, [r3, #12]
|
|
80090be: 0c1b lsrs r3, r3, #16
|
|
80090c0: f3c3 030b ubfx r3, r3, #0, #12
|
|
80090c4: 4413 add r3, r2
|
|
80090c6: 041b lsls r3, r3, #16
|
|
80090c8: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
|
|
80090ca: 68fb ldr r3, [r7, #12]
|
|
80090cc: 681b ldr r3, [r3, #0]
|
|
80090ce: 461a mov r2, r3
|
|
80090d0: 687b ldr r3, [r7, #4]
|
|
80090d2: 01db lsls r3, r3, #7
|
|
80090d4: 4413 add r3, r2
|
|
80090d6: 3384 adds r3, #132 ; 0x84
|
|
80090d8: 685b ldr r3, [r3, #4]
|
|
80090da: 68fa ldr r2, [r7, #12]
|
|
80090dc: 6812 ldr r2, [r2, #0]
|
|
80090de: 4611 mov r1, r2
|
|
80090e0: 687a ldr r2, [r7, #4]
|
|
80090e2: 01d2 lsls r2, r2, #7
|
|
80090e4: 440a add r2, r1
|
|
80090e6: 3284 adds r2, #132 ; 0x84
|
|
80090e8: f403 4370 and.w r3, r3, #61440 ; 0xf000
|
|
80090ec: 6053 str r3, [r2, #4]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
80090ee: 68bb ldr r3, [r7, #8]
|
|
80090f0: 681a ldr r2, [r3, #0]
|
|
80090f2: 68fb ldr r3, [r7, #12]
|
|
80090f4: 681b ldr r3, [r3, #0]
|
|
80090f6: 68db ldr r3, [r3, #12]
|
|
80090f8: 0c1b lsrs r3, r3, #16
|
|
80090fa: f3c3 030b ubfx r3, r3, #0, #12
|
|
80090fe: 4413 add r3, r2
|
|
8009100: 1c5a adds r2, r3, #1
|
|
8009102: 68fb ldr r3, [r7, #12]
|
|
8009104: 681b ldr r3, [r3, #0]
|
|
8009106: 4619 mov r1, r3
|
|
8009108: 687b ldr r3, [r7, #4]
|
|
800910a: 01db lsls r3, r3, #7
|
|
800910c: 440b add r3, r1
|
|
800910e: 3384 adds r3, #132 ; 0x84
|
|
8009110: 4619 mov r1, r3
|
|
8009112: 69fb ldr r3, [r7, #28]
|
|
8009114: 4313 orrs r3, r2
|
|
8009116: 604b str r3, [r1, #4]
|
|
|
|
/* Configure the vertical start and stop position */
|
|
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
|
|
8009118: 68bb ldr r3, [r7, #8]
|
|
800911a: 68da ldr r2, [r3, #12]
|
|
800911c: 68fb ldr r3, [r7, #12]
|
|
800911e: 681b ldr r3, [r3, #0]
|
|
8009120: 68db ldr r3, [r3, #12]
|
|
8009122: f3c3 030a ubfx r3, r3, #0, #11
|
|
8009126: 4413 add r3, r2
|
|
8009128: 041b lsls r3, r3, #16
|
|
800912a: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
|
|
800912c: 68fb ldr r3, [r7, #12]
|
|
800912e: 681b ldr r3, [r3, #0]
|
|
8009130: 461a mov r2, r3
|
|
8009132: 687b ldr r3, [r7, #4]
|
|
8009134: 01db lsls r3, r3, #7
|
|
8009136: 4413 add r3, r2
|
|
8009138: 3384 adds r3, #132 ; 0x84
|
|
800913a: 689b ldr r3, [r3, #8]
|
|
800913c: 68fa ldr r2, [r7, #12]
|
|
800913e: 6812 ldr r2, [r2, #0]
|
|
8009140: 4611 mov r1, r2
|
|
8009142: 687a ldr r2, [r7, #4]
|
|
8009144: 01d2 lsls r2, r2, #7
|
|
8009146: 440a add r2, r1
|
|
8009148: 3284 adds r2, #132 ; 0x84
|
|
800914a: f403 4370 and.w r3, r3, #61440 ; 0xf000
|
|
800914e: 6093 str r3, [r2, #8]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
|
|
8009150: 68bb ldr r3, [r7, #8]
|
|
8009152: 689a ldr r2, [r3, #8]
|
|
8009154: 68fb ldr r3, [r7, #12]
|
|
8009156: 681b ldr r3, [r3, #0]
|
|
8009158: 68db ldr r3, [r3, #12]
|
|
800915a: f3c3 030a ubfx r3, r3, #0, #11
|
|
800915e: 4413 add r3, r2
|
|
8009160: 1c5a adds r2, r3, #1
|
|
8009162: 68fb ldr r3, [r7, #12]
|
|
8009164: 681b ldr r3, [r3, #0]
|
|
8009166: 4619 mov r1, r3
|
|
8009168: 687b ldr r3, [r7, #4]
|
|
800916a: 01db lsls r3, r3, #7
|
|
800916c: 440b add r3, r1
|
|
800916e: 3384 adds r3, #132 ; 0x84
|
|
8009170: 4619 mov r1, r3
|
|
8009172: 69fb ldr r3, [r7, #28]
|
|
8009174: 4313 orrs r3, r2
|
|
8009176: 608b str r3, [r1, #8]
|
|
|
|
/* Specifies the pixel format */
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
|
|
8009178: 68fb ldr r3, [r7, #12]
|
|
800917a: 681b ldr r3, [r3, #0]
|
|
800917c: 461a mov r2, r3
|
|
800917e: 687b ldr r3, [r7, #4]
|
|
8009180: 01db lsls r3, r3, #7
|
|
8009182: 4413 add r3, r2
|
|
8009184: 3384 adds r3, #132 ; 0x84
|
|
8009186: 691b ldr r3, [r3, #16]
|
|
8009188: 68fa ldr r2, [r7, #12]
|
|
800918a: 6812 ldr r2, [r2, #0]
|
|
800918c: 4611 mov r1, r2
|
|
800918e: 687a ldr r2, [r7, #4]
|
|
8009190: 01d2 lsls r2, r2, #7
|
|
8009192: 440a add r2, r1
|
|
8009194: 3284 adds r2, #132 ; 0x84
|
|
8009196: f023 0307 bic.w r3, r3, #7
|
|
800919a: 6113 str r3, [r2, #16]
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
|
|
800919c: 68fb ldr r3, [r7, #12]
|
|
800919e: 681b ldr r3, [r3, #0]
|
|
80091a0: 461a mov r2, r3
|
|
80091a2: 687b ldr r3, [r7, #4]
|
|
80091a4: 01db lsls r3, r3, #7
|
|
80091a6: 4413 add r3, r2
|
|
80091a8: 3384 adds r3, #132 ; 0x84
|
|
80091aa: 461a mov r2, r3
|
|
80091ac: 68bb ldr r3, [r7, #8]
|
|
80091ae: 691b ldr r3, [r3, #16]
|
|
80091b0: 6113 str r3, [r2, #16]
|
|
|
|
/* Configure the default color values */
|
|
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
|
|
80091b2: 68bb ldr r3, [r7, #8]
|
|
80091b4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
80091b8: 021b lsls r3, r3, #8
|
|
80091ba: 61fb str r3, [r7, #28]
|
|
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
|
|
80091bc: 68bb ldr r3, [r7, #8]
|
|
80091be: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
|
|
80091c2: 041b lsls r3, r3, #16
|
|
80091c4: 61bb str r3, [r7, #24]
|
|
tmp2 = (pLayerCfg->Alpha0 << 24U);
|
|
80091c6: 68bb ldr r3, [r7, #8]
|
|
80091c8: 699b ldr r3, [r3, #24]
|
|
80091ca: 061b lsls r3, r3, #24
|
|
80091cc: 617b str r3, [r7, #20]
|
|
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
|
|
80091ce: 68fb ldr r3, [r7, #12]
|
|
80091d0: 681b ldr r3, [r3, #0]
|
|
80091d2: 461a mov r2, r3
|
|
80091d4: 687b ldr r3, [r7, #4]
|
|
80091d6: 01db lsls r3, r3, #7
|
|
80091d8: 4413 add r3, r2
|
|
80091da: 3384 adds r3, #132 ; 0x84
|
|
80091dc: 699b ldr r3, [r3, #24]
|
|
80091de: 68fb ldr r3, [r7, #12]
|
|
80091e0: 681b ldr r3, [r3, #0]
|
|
80091e2: 461a mov r2, r3
|
|
80091e4: 687b ldr r3, [r7, #4]
|
|
80091e6: 01db lsls r3, r3, #7
|
|
80091e8: 4413 add r3, r2
|
|
80091ea: 3384 adds r3, #132 ; 0x84
|
|
80091ec: 461a mov r2, r3
|
|
80091ee: 2300 movs r3, #0
|
|
80091f0: 6193 str r3, [r2, #24]
|
|
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
|
|
80091f2: 68bb ldr r3, [r7, #8]
|
|
80091f4: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
80091f8: 461a mov r2, r3
|
|
80091fa: 69fb ldr r3, [r7, #28]
|
|
80091fc: 431a orrs r2, r3
|
|
80091fe: 69bb ldr r3, [r7, #24]
|
|
8009200: 431a orrs r2, r3
|
|
8009202: 68fb ldr r3, [r7, #12]
|
|
8009204: 681b ldr r3, [r3, #0]
|
|
8009206: 4619 mov r1, r3
|
|
8009208: 687b ldr r3, [r7, #4]
|
|
800920a: 01db lsls r3, r3, #7
|
|
800920c: 440b add r3, r1
|
|
800920e: 3384 adds r3, #132 ; 0x84
|
|
8009210: 4619 mov r1, r3
|
|
8009212: 697b ldr r3, [r7, #20]
|
|
8009214: 4313 orrs r3, r2
|
|
8009216: 618b str r3, [r1, #24]
|
|
|
|
/* Specifies the constant alpha value */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
|
|
8009218: 68fb ldr r3, [r7, #12]
|
|
800921a: 681b ldr r3, [r3, #0]
|
|
800921c: 461a mov r2, r3
|
|
800921e: 687b ldr r3, [r7, #4]
|
|
8009220: 01db lsls r3, r3, #7
|
|
8009222: 4413 add r3, r2
|
|
8009224: 3384 adds r3, #132 ; 0x84
|
|
8009226: 695b ldr r3, [r3, #20]
|
|
8009228: 68fa ldr r2, [r7, #12]
|
|
800922a: 6812 ldr r2, [r2, #0]
|
|
800922c: 4611 mov r1, r2
|
|
800922e: 687a ldr r2, [r7, #4]
|
|
8009230: 01d2 lsls r2, r2, #7
|
|
8009232: 440a add r2, r1
|
|
8009234: 3284 adds r2, #132 ; 0x84
|
|
8009236: f023 03ff bic.w r3, r3, #255 ; 0xff
|
|
800923a: 6153 str r3, [r2, #20]
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
|
|
800923c: 68fb ldr r3, [r7, #12]
|
|
800923e: 681b ldr r3, [r3, #0]
|
|
8009240: 461a mov r2, r3
|
|
8009242: 687b ldr r3, [r7, #4]
|
|
8009244: 01db lsls r3, r3, #7
|
|
8009246: 4413 add r3, r2
|
|
8009248: 3384 adds r3, #132 ; 0x84
|
|
800924a: 461a mov r2, r3
|
|
800924c: 68bb ldr r3, [r7, #8]
|
|
800924e: 695b ldr r3, [r3, #20]
|
|
8009250: 6153 str r3, [r2, #20]
|
|
|
|
/* Specifies the blending factors */
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
|
|
8009252: 68fb ldr r3, [r7, #12]
|
|
8009254: 681b ldr r3, [r3, #0]
|
|
8009256: 461a mov r2, r3
|
|
8009258: 687b ldr r3, [r7, #4]
|
|
800925a: 01db lsls r3, r3, #7
|
|
800925c: 4413 add r3, r2
|
|
800925e: 3384 adds r3, #132 ; 0x84
|
|
8009260: 69da ldr r2, [r3, #28]
|
|
8009262: 68fb ldr r3, [r7, #12]
|
|
8009264: 681b ldr r3, [r3, #0]
|
|
8009266: 4619 mov r1, r3
|
|
8009268: 687b ldr r3, [r7, #4]
|
|
800926a: 01db lsls r3, r3, #7
|
|
800926c: 440b add r3, r1
|
|
800926e: 3384 adds r3, #132 ; 0x84
|
|
8009270: 4619 mov r1, r3
|
|
8009272: 4b58 ldr r3, [pc, #352] ; (80093d4 <LTDC_SetConfig+0x32c>)
|
|
8009274: 4013 ands r3, r2
|
|
8009276: 61cb str r3, [r1, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
|
|
8009278: 68bb ldr r3, [r7, #8]
|
|
800927a: 69da ldr r2, [r3, #28]
|
|
800927c: 68bb ldr r3, [r7, #8]
|
|
800927e: 6a1b ldr r3, [r3, #32]
|
|
8009280: 68f9 ldr r1, [r7, #12]
|
|
8009282: 6809 ldr r1, [r1, #0]
|
|
8009284: 4608 mov r0, r1
|
|
8009286: 6879 ldr r1, [r7, #4]
|
|
8009288: 01c9 lsls r1, r1, #7
|
|
800928a: 4401 add r1, r0
|
|
800928c: 3184 adds r1, #132 ; 0x84
|
|
800928e: 4313 orrs r3, r2
|
|
8009290: 61cb str r3, [r1, #28]
|
|
|
|
/* Configure the color frame buffer start address */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
|
|
8009292: 68fb ldr r3, [r7, #12]
|
|
8009294: 681b ldr r3, [r3, #0]
|
|
8009296: 461a mov r2, r3
|
|
8009298: 687b ldr r3, [r7, #4]
|
|
800929a: 01db lsls r3, r3, #7
|
|
800929c: 4413 add r3, r2
|
|
800929e: 3384 adds r3, #132 ; 0x84
|
|
80092a0: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80092a2: 68fb ldr r3, [r7, #12]
|
|
80092a4: 681b ldr r3, [r3, #0]
|
|
80092a6: 461a mov r2, r3
|
|
80092a8: 687b ldr r3, [r7, #4]
|
|
80092aa: 01db lsls r3, r3, #7
|
|
80092ac: 4413 add r3, r2
|
|
80092ae: 3384 adds r3, #132 ; 0x84
|
|
80092b0: 461a mov r2, r3
|
|
80092b2: 2300 movs r3, #0
|
|
80092b4: 6293 str r3, [r2, #40] ; 0x28
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
|
|
80092b6: 68fb ldr r3, [r7, #12]
|
|
80092b8: 681b ldr r3, [r3, #0]
|
|
80092ba: 461a mov r2, r3
|
|
80092bc: 687b ldr r3, [r7, #4]
|
|
80092be: 01db lsls r3, r3, #7
|
|
80092c0: 4413 add r3, r2
|
|
80092c2: 3384 adds r3, #132 ; 0x84
|
|
80092c4: 461a mov r2, r3
|
|
80092c6: 68bb ldr r3, [r7, #8]
|
|
80092c8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80092ca: 6293 str r3, [r2, #40] ; 0x28
|
|
|
|
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
|
|
80092cc: 68bb ldr r3, [r7, #8]
|
|
80092ce: 691b ldr r3, [r3, #16]
|
|
80092d0: 2b00 cmp r3, #0
|
|
80092d2: d102 bne.n 80092da <LTDC_SetConfig+0x232>
|
|
{
|
|
tmp = 4U;
|
|
80092d4: 2304 movs r3, #4
|
|
80092d6: 61fb str r3, [r7, #28]
|
|
80092d8: e01b b.n 8009312 <LTDC_SetConfig+0x26a>
|
|
}
|
|
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
|
|
80092da: 68bb ldr r3, [r7, #8]
|
|
80092dc: 691b ldr r3, [r3, #16]
|
|
80092de: 2b01 cmp r3, #1
|
|
80092e0: d102 bne.n 80092e8 <LTDC_SetConfig+0x240>
|
|
{
|
|
tmp = 3U;
|
|
80092e2: 2303 movs r3, #3
|
|
80092e4: 61fb str r3, [r7, #28]
|
|
80092e6: e014 b.n 8009312 <LTDC_SetConfig+0x26a>
|
|
}
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
80092e8: 68bb ldr r3, [r7, #8]
|
|
80092ea: 691b ldr r3, [r3, #16]
|
|
80092ec: 2b04 cmp r3, #4
|
|
80092ee: d00b beq.n 8009308 <LTDC_SetConfig+0x260>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
80092f0: 68bb ldr r3, [r7, #8]
|
|
80092f2: 691b ldr r3, [r3, #16]
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
80092f4: 2b02 cmp r3, #2
|
|
80092f6: d007 beq.n 8009308 <LTDC_SetConfig+0x260>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
80092f8: 68bb ldr r3, [r7, #8]
|
|
80092fa: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
80092fc: 2b03 cmp r3, #3
|
|
80092fe: d003 beq.n 8009308 <LTDC_SetConfig+0x260>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
|
|
8009300: 68bb ldr r3, [r7, #8]
|
|
8009302: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
8009304: 2b07 cmp r3, #7
|
|
8009306: d102 bne.n 800930e <LTDC_SetConfig+0x266>
|
|
{
|
|
tmp = 2U;
|
|
8009308: 2302 movs r3, #2
|
|
800930a: 61fb str r3, [r7, #28]
|
|
800930c: e001 b.n 8009312 <LTDC_SetConfig+0x26a>
|
|
}
|
|
else
|
|
{
|
|
tmp = 1U;
|
|
800930e: 2301 movs r3, #1
|
|
8009310: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Configure the color frame buffer pitch in byte */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
|
|
8009312: 68fb ldr r3, [r7, #12]
|
|
8009314: 681b ldr r3, [r3, #0]
|
|
8009316: 461a mov r2, r3
|
|
8009318: 687b ldr r3, [r7, #4]
|
|
800931a: 01db lsls r3, r3, #7
|
|
800931c: 4413 add r3, r2
|
|
800931e: 3384 adds r3, #132 ; 0x84
|
|
8009320: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8009322: 68fa ldr r2, [r7, #12]
|
|
8009324: 6812 ldr r2, [r2, #0]
|
|
8009326: 4611 mov r1, r2
|
|
8009328: 687a ldr r2, [r7, #4]
|
|
800932a: 01d2 lsls r2, r2, #7
|
|
800932c: 440a add r2, r1
|
|
800932e: 3284 adds r2, #132 ; 0x84
|
|
8009330: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
|
|
8009334: 62d3 str r3, [r2, #44] ; 0x2c
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
|
|
8009336: 68bb ldr r3, [r7, #8]
|
|
8009338: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800933a: 69fa ldr r2, [r7, #28]
|
|
800933c: fb02 f303 mul.w r3, r2, r3
|
|
8009340: 041a lsls r2, r3, #16
|
|
8009342: 68bb ldr r3, [r7, #8]
|
|
8009344: 6859 ldr r1, [r3, #4]
|
|
8009346: 68bb ldr r3, [r7, #8]
|
|
8009348: 681b ldr r3, [r3, #0]
|
|
800934a: 1acb subs r3, r1, r3
|
|
800934c: 69f9 ldr r1, [r7, #28]
|
|
800934e: fb01 f303 mul.w r3, r1, r3
|
|
8009352: 3303 adds r3, #3
|
|
8009354: 68f9 ldr r1, [r7, #12]
|
|
8009356: 6809 ldr r1, [r1, #0]
|
|
8009358: 4608 mov r0, r1
|
|
800935a: 6879 ldr r1, [r7, #4]
|
|
800935c: 01c9 lsls r1, r1, #7
|
|
800935e: 4401 add r1, r0
|
|
8009360: 3184 adds r1, #132 ; 0x84
|
|
8009362: 4313 orrs r3, r2
|
|
8009364: 62cb str r3, [r1, #44] ; 0x2c
|
|
/* Configure the frame buffer line number */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
|
|
8009366: 68fb ldr r3, [r7, #12]
|
|
8009368: 681b ldr r3, [r3, #0]
|
|
800936a: 461a mov r2, r3
|
|
800936c: 687b ldr r3, [r7, #4]
|
|
800936e: 01db lsls r3, r3, #7
|
|
8009370: 4413 add r3, r2
|
|
8009372: 3384 adds r3, #132 ; 0x84
|
|
8009374: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
8009376: 68fb ldr r3, [r7, #12]
|
|
8009378: 681b ldr r3, [r3, #0]
|
|
800937a: 4619 mov r1, r3
|
|
800937c: 687b ldr r3, [r7, #4]
|
|
800937e: 01db lsls r3, r3, #7
|
|
8009380: 440b add r3, r1
|
|
8009382: 3384 adds r3, #132 ; 0x84
|
|
8009384: 4619 mov r1, r3
|
|
8009386: 4b14 ldr r3, [pc, #80] ; (80093d8 <LTDC_SetConfig+0x330>)
|
|
8009388: 4013 ands r3, r2
|
|
800938a: 630b str r3, [r1, #48] ; 0x30
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
|
|
800938c: 68fb ldr r3, [r7, #12]
|
|
800938e: 681b ldr r3, [r3, #0]
|
|
8009390: 461a mov r2, r3
|
|
8009392: 687b ldr r3, [r7, #4]
|
|
8009394: 01db lsls r3, r3, #7
|
|
8009396: 4413 add r3, r2
|
|
8009398: 3384 adds r3, #132 ; 0x84
|
|
800939a: 461a mov r2, r3
|
|
800939c: 68bb ldr r3, [r7, #8]
|
|
800939e: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80093a0: 6313 str r3, [r2, #48] ; 0x30
|
|
|
|
/* Enable LTDC_Layer by setting LEN bit */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
|
|
80093a2: 68fb ldr r3, [r7, #12]
|
|
80093a4: 681b ldr r3, [r3, #0]
|
|
80093a6: 461a mov r2, r3
|
|
80093a8: 687b ldr r3, [r7, #4]
|
|
80093aa: 01db lsls r3, r3, #7
|
|
80093ac: 4413 add r3, r2
|
|
80093ae: 3384 adds r3, #132 ; 0x84
|
|
80093b0: 681b ldr r3, [r3, #0]
|
|
80093b2: 68fa ldr r2, [r7, #12]
|
|
80093b4: 6812 ldr r2, [r2, #0]
|
|
80093b6: 4611 mov r1, r2
|
|
80093b8: 687a ldr r2, [r7, #4]
|
|
80093ba: 01d2 lsls r2, r2, #7
|
|
80093bc: 440a add r2, r1
|
|
80093be: 3284 adds r2, #132 ; 0x84
|
|
80093c0: f043 0301 orr.w r3, r3, #1
|
|
80093c4: 6013 str r3, [r2, #0]
|
|
}
|
|
80093c6: bf00 nop
|
|
80093c8: 3724 adds r7, #36 ; 0x24
|
|
80093ca: 46bd mov sp, r7
|
|
80093cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80093d0: 4770 bx lr
|
|
80093d2: bf00 nop
|
|
80093d4: fffff8f8 .word 0xfffff8f8
|
|
80093d8: fffff800 .word 0xfffff800
|
|
|
|
080093dc <HAL_PWR_EnableBkUpAccess>:
|
|
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
|
* Backup Domain Access should be kept enabled.
|
|
* @retval None
|
|
*/
|
|
void HAL_PWR_EnableBkUpAccess(void)
|
|
{
|
|
80093dc: b480 push {r7}
|
|
80093de: af00 add r7, sp, #0
|
|
/* Enable access to RTC and backup registers */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80093e0: 4b05 ldr r3, [pc, #20] ; (80093f8 <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
80093e2: 681b ldr r3, [r3, #0]
|
|
80093e4: 4a04 ldr r2, [pc, #16] ; (80093f8 <HAL_PWR_EnableBkUpAccess+0x1c>)
|
|
80093e6: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
80093ea: 6013 str r3, [r2, #0]
|
|
}
|
|
80093ec: bf00 nop
|
|
80093ee: 46bd mov sp, r7
|
|
80093f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80093f4: 4770 bx lr
|
|
80093f6: bf00 nop
|
|
80093f8: 40007000 .word 0x40007000
|
|
|
|
080093fc <HAL_PWREx_EnableOverDrive>:
|
|
* During the Over-drive switch activation, no peripheral clocks should be enabled.
|
|
* The peripheral clocks must be enabled once the Over-drive mode is activated.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
|
|
{
|
|
80093fc: b580 push {r7, lr}
|
|
80093fe: b082 sub sp, #8
|
|
8009400: af00 add r7, sp, #0
|
|
uint32_t tickstart = 0;
|
|
8009402: 2300 movs r3, #0
|
|
8009404: 607b str r3, [r7, #4]
|
|
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8009406: 4b23 ldr r3, [pc, #140] ; (8009494 <HAL_PWREx_EnableOverDrive+0x98>)
|
|
8009408: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800940a: 4a22 ldr r2, [pc, #136] ; (8009494 <HAL_PWREx_EnableOverDrive+0x98>)
|
|
800940c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8009410: 6413 str r3, [r2, #64] ; 0x40
|
|
8009412: 4b20 ldr r3, [pc, #128] ; (8009494 <HAL_PWREx_EnableOverDrive+0x98>)
|
|
8009414: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009416: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800941a: 603b str r3, [r7, #0]
|
|
800941c: 683b ldr r3, [r7, #0]
|
|
|
|
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
|
|
__HAL_PWR_OVERDRIVE_ENABLE();
|
|
800941e: 4b1e ldr r3, [pc, #120] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
8009420: 681b ldr r3, [r3, #0]
|
|
8009422: 4a1d ldr r2, [pc, #116] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
8009424: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8009428: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800942a: f7fb ff59 bl 80052e0 <HAL_GetTick>
|
|
800942e: 6078 str r0, [r7, #4]
|
|
|
|
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
|
8009430: e009 b.n 8009446 <HAL_PWREx_EnableOverDrive+0x4a>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
8009432: f7fb ff55 bl 80052e0 <HAL_GetTick>
|
|
8009436: 4602 mov r2, r0
|
|
8009438: 687b ldr r3, [r7, #4]
|
|
800943a: 1ad3 subs r3, r2, r3
|
|
800943c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
8009440: d901 bls.n 8009446 <HAL_PWREx_EnableOverDrive+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009442: 2303 movs r3, #3
|
|
8009444: e022 b.n 800948c <HAL_PWREx_EnableOverDrive+0x90>
|
|
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
|
8009446: 4b14 ldr r3, [pc, #80] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
8009448: 685b ldr r3, [r3, #4]
|
|
800944a: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
800944e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8009452: d1ee bne.n 8009432 <HAL_PWREx_EnableOverDrive+0x36>
|
|
}
|
|
}
|
|
|
|
/* Enable the Over-drive switch */
|
|
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
|
|
8009454: 4b10 ldr r3, [pc, #64] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
8009456: 681b ldr r3, [r3, #0]
|
|
8009458: 4a0f ldr r2, [pc, #60] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
800945a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
|
|
800945e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8009460: f7fb ff3e bl 80052e0 <HAL_GetTick>
|
|
8009464: 6078 str r0, [r7, #4]
|
|
|
|
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
|
8009466: e009 b.n 800947c <HAL_PWREx_EnableOverDrive+0x80>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
8009468: f7fb ff3a bl 80052e0 <HAL_GetTick>
|
|
800946c: 4602 mov r2, r0
|
|
800946e: 687b ldr r3, [r7, #4]
|
|
8009470: 1ad3 subs r3, r2, r3
|
|
8009472: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
8009476: d901 bls.n 800947c <HAL_PWREx_EnableOverDrive+0x80>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009478: 2303 movs r3, #3
|
|
800947a: e007 b.n 800948c <HAL_PWREx_EnableOverDrive+0x90>
|
|
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
|
800947c: 4b06 ldr r3, [pc, #24] ; (8009498 <HAL_PWREx_EnableOverDrive+0x9c>)
|
|
800947e: 685b ldr r3, [r3, #4]
|
|
8009480: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8009484: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
|
|
8009488: d1ee bne.n 8009468 <HAL_PWREx_EnableOverDrive+0x6c>
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800948a: 2300 movs r3, #0
|
|
}
|
|
800948c: 4618 mov r0, r3
|
|
800948e: 3708 adds r7, #8
|
|
8009490: 46bd mov sp, r7
|
|
8009492: bd80 pop {r7, pc}
|
|
8009494: 40023800 .word 0x40023800
|
|
8009498: 40007000 .word 0x40007000
|
|
|
|
0800949c <HAL_RCC_OscConfig>:
|
|
* supported by this function. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
800949c: b580 push {r7, lr}
|
|
800949e: b086 sub sp, #24
|
|
80094a0: af00 add r7, sp, #0
|
|
80094a2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
FlagStatus pwrclkchanged = RESET;
|
|
80094a4: 2300 movs r3, #0
|
|
80094a6: 75fb strb r3, [r7, #23]
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
80094a8: 687b ldr r3, [r7, #4]
|
|
80094aa: 2b00 cmp r3, #0
|
|
80094ac: d101 bne.n 80094b2 <HAL_RCC_OscConfig+0x16>
|
|
{
|
|
return HAL_ERROR;
|
|
80094ae: 2301 movs r3, #1
|
|
80094b0: e291 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
80094b2: 687b ldr r3, [r7, #4]
|
|
80094b4: 681b ldr r3, [r3, #0]
|
|
80094b6: f003 0301 and.w r3, r3, #1
|
|
80094ba: 2b00 cmp r3, #0
|
|
80094bc: f000 8087 beq.w 80095ce <HAL_RCC_OscConfig+0x132>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
80094c0: 4b96 ldr r3, [pc, #600] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80094c2: 689b ldr r3, [r3, #8]
|
|
80094c4: f003 030c and.w r3, r3, #12
|
|
80094c8: 2b04 cmp r3, #4
|
|
80094ca: d00c beq.n 80094e6 <HAL_RCC_OscConfig+0x4a>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80094cc: 4b93 ldr r3, [pc, #588] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80094ce: 689b ldr r3, [r3, #8]
|
|
80094d0: f003 030c and.w r3, r3, #12
|
|
80094d4: 2b08 cmp r3, #8
|
|
80094d6: d112 bne.n 80094fe <HAL_RCC_OscConfig+0x62>
|
|
80094d8: 4b90 ldr r3, [pc, #576] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80094da: 685b ldr r3, [r3, #4]
|
|
80094dc: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
80094e0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
|
80094e4: d10b bne.n 80094fe <HAL_RCC_OscConfig+0x62>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80094e6: 4b8d ldr r3, [pc, #564] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80094e8: 681b ldr r3, [r3, #0]
|
|
80094ea: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80094ee: 2b00 cmp r3, #0
|
|
80094f0: d06c beq.n 80095cc <HAL_RCC_OscConfig+0x130>
|
|
80094f2: 687b ldr r3, [r7, #4]
|
|
80094f4: 685b ldr r3, [r3, #4]
|
|
80094f6: 2b00 cmp r3, #0
|
|
80094f8: d168 bne.n 80095cc <HAL_RCC_OscConfig+0x130>
|
|
{
|
|
return HAL_ERROR;
|
|
80094fa: 2301 movs r3, #1
|
|
80094fc: e26b b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80094fe: 687b ldr r3, [r7, #4]
|
|
8009500: 685b ldr r3, [r3, #4]
|
|
8009502: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8009506: d106 bne.n 8009516 <HAL_RCC_OscConfig+0x7a>
|
|
8009508: 4b84 ldr r3, [pc, #528] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800950a: 681b ldr r3, [r3, #0]
|
|
800950c: 4a83 ldr r2, [pc, #524] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800950e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8009512: 6013 str r3, [r2, #0]
|
|
8009514: e02e b.n 8009574 <HAL_RCC_OscConfig+0xd8>
|
|
8009516: 687b ldr r3, [r7, #4]
|
|
8009518: 685b ldr r3, [r3, #4]
|
|
800951a: 2b00 cmp r3, #0
|
|
800951c: d10c bne.n 8009538 <HAL_RCC_OscConfig+0x9c>
|
|
800951e: 4b7f ldr r3, [pc, #508] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009520: 681b ldr r3, [r3, #0]
|
|
8009522: 4a7e ldr r2, [pc, #504] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009524: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8009528: 6013 str r3, [r2, #0]
|
|
800952a: 4b7c ldr r3, [pc, #496] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800952c: 681b ldr r3, [r3, #0]
|
|
800952e: 4a7b ldr r2, [pc, #492] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009530: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8009534: 6013 str r3, [r2, #0]
|
|
8009536: e01d b.n 8009574 <HAL_RCC_OscConfig+0xd8>
|
|
8009538: 687b ldr r3, [r7, #4]
|
|
800953a: 685b ldr r3, [r3, #4]
|
|
800953c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
|
|
8009540: d10c bne.n 800955c <HAL_RCC_OscConfig+0xc0>
|
|
8009542: 4b76 ldr r3, [pc, #472] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009544: 681b ldr r3, [r3, #0]
|
|
8009546: 4a75 ldr r2, [pc, #468] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009548: f443 2380 orr.w r3, r3, #262144 ; 0x40000
|
|
800954c: 6013 str r3, [r2, #0]
|
|
800954e: 4b73 ldr r3, [pc, #460] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009550: 681b ldr r3, [r3, #0]
|
|
8009552: 4a72 ldr r2, [pc, #456] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009554: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8009558: 6013 str r3, [r2, #0]
|
|
800955a: e00b b.n 8009574 <HAL_RCC_OscConfig+0xd8>
|
|
800955c: 4b6f ldr r3, [pc, #444] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800955e: 681b ldr r3, [r3, #0]
|
|
8009560: 4a6e ldr r2, [pc, #440] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009562: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8009566: 6013 str r3, [r2, #0]
|
|
8009568: 4b6c ldr r3, [pc, #432] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800956a: 681b ldr r3, [r3, #0]
|
|
800956c: 4a6b ldr r2, [pc, #428] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800956e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
8009572: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8009574: 687b ldr r3, [r7, #4]
|
|
8009576: 685b ldr r3, [r3, #4]
|
|
8009578: 2b00 cmp r3, #0
|
|
800957a: d013 beq.n 80095a4 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800957c: f7fb feb0 bl 80052e0 <HAL_GetTick>
|
|
8009580: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8009582: e008 b.n 8009596 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8009584: f7fb feac bl 80052e0 <HAL_GetTick>
|
|
8009588: 4602 mov r2, r0
|
|
800958a: 693b ldr r3, [r7, #16]
|
|
800958c: 1ad3 subs r3, r2, r3
|
|
800958e: 2b64 cmp r3, #100 ; 0x64
|
|
8009590: d901 bls.n 8009596 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009592: 2303 movs r3, #3
|
|
8009594: e21f b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8009596: 4b61 ldr r3, [pc, #388] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009598: 681b ldr r3, [r3, #0]
|
|
800959a: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
800959e: 2b00 cmp r3, #0
|
|
80095a0: d0f0 beq.n 8009584 <HAL_RCC_OscConfig+0xe8>
|
|
80095a2: e014 b.n 80095ce <HAL_RCC_OscConfig+0x132>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80095a4: f7fb fe9c bl 80052e0 <HAL_GetTick>
|
|
80095a8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80095aa: e008 b.n 80095be <HAL_RCC_OscConfig+0x122>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80095ac: f7fb fe98 bl 80052e0 <HAL_GetTick>
|
|
80095b0: 4602 mov r2, r0
|
|
80095b2: 693b ldr r3, [r7, #16]
|
|
80095b4: 1ad3 subs r3, r2, r3
|
|
80095b6: 2b64 cmp r3, #100 ; 0x64
|
|
80095b8: d901 bls.n 80095be <HAL_RCC_OscConfig+0x122>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80095ba: 2303 movs r3, #3
|
|
80095bc: e20b b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80095be: 4b57 ldr r3, [pc, #348] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80095c0: 681b ldr r3, [r3, #0]
|
|
80095c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
80095c6: 2b00 cmp r3, #0
|
|
80095c8: d1f0 bne.n 80095ac <HAL_RCC_OscConfig+0x110>
|
|
80095ca: e000 b.n 80095ce <HAL_RCC_OscConfig+0x132>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80095cc: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80095ce: 687b ldr r3, [r7, #4]
|
|
80095d0: 681b ldr r3, [r3, #0]
|
|
80095d2: f003 0302 and.w r3, r3, #2
|
|
80095d6: 2b00 cmp r3, #0
|
|
80095d8: d069 beq.n 80096ae <HAL_RCC_OscConfig+0x212>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
80095da: 4b50 ldr r3, [pc, #320] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80095dc: 689b ldr r3, [r3, #8]
|
|
80095de: f003 030c and.w r3, r3, #12
|
|
80095e2: 2b00 cmp r3, #0
|
|
80095e4: d00b beq.n 80095fe <HAL_RCC_OscConfig+0x162>
|
|
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
80095e6: 4b4d ldr r3, [pc, #308] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80095e8: 689b ldr r3, [r3, #8]
|
|
80095ea: f003 030c and.w r3, r3, #12
|
|
80095ee: 2b08 cmp r3, #8
|
|
80095f0: d11c bne.n 800962c <HAL_RCC_OscConfig+0x190>
|
|
80095f2: 4b4a ldr r3, [pc, #296] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80095f4: 685b ldr r3, [r3, #4]
|
|
80095f6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
80095fa: 2b00 cmp r3, #0
|
|
80095fc: d116 bne.n 800962c <HAL_RCC_OscConfig+0x190>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
80095fe: 4b47 ldr r3, [pc, #284] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009600: 681b ldr r3, [r3, #0]
|
|
8009602: f003 0302 and.w r3, r3, #2
|
|
8009606: 2b00 cmp r3, #0
|
|
8009608: d005 beq.n 8009616 <HAL_RCC_OscConfig+0x17a>
|
|
800960a: 687b ldr r3, [r7, #4]
|
|
800960c: 68db ldr r3, [r3, #12]
|
|
800960e: 2b01 cmp r3, #1
|
|
8009610: d001 beq.n 8009616 <HAL_RCC_OscConfig+0x17a>
|
|
{
|
|
return HAL_ERROR;
|
|
8009612: 2301 movs r3, #1
|
|
8009614: e1df b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8009616: 4b41 ldr r3, [pc, #260] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009618: 681b ldr r3, [r3, #0]
|
|
800961a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
800961e: 687b ldr r3, [r7, #4]
|
|
8009620: 691b ldr r3, [r3, #16]
|
|
8009622: 00db lsls r3, r3, #3
|
|
8009624: 493d ldr r1, [pc, #244] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009626: 4313 orrs r3, r2
|
|
8009628: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
800962a: e040 b.n 80096ae <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
800962c: 687b ldr r3, [r7, #4]
|
|
800962e: 68db ldr r3, [r3, #12]
|
|
8009630: 2b00 cmp r3, #0
|
|
8009632: d023 beq.n 800967c <HAL_RCC_OscConfig+0x1e0>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8009634: 4b39 ldr r3, [pc, #228] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009636: 681b ldr r3, [r3, #0]
|
|
8009638: 4a38 ldr r2, [pc, #224] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800963a: f043 0301 orr.w r3, r3, #1
|
|
800963e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009640: f7fb fe4e bl 80052e0 <HAL_GetTick>
|
|
8009644: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8009646: e008 b.n 800965a <HAL_RCC_OscConfig+0x1be>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8009648: f7fb fe4a bl 80052e0 <HAL_GetTick>
|
|
800964c: 4602 mov r2, r0
|
|
800964e: 693b ldr r3, [r7, #16]
|
|
8009650: 1ad3 subs r3, r2, r3
|
|
8009652: 2b02 cmp r3, #2
|
|
8009654: d901 bls.n 800965a <HAL_RCC_OscConfig+0x1be>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009656: 2303 movs r3, #3
|
|
8009658: e1bd b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800965a: 4b30 ldr r3, [pc, #192] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800965c: 681b ldr r3, [r3, #0]
|
|
800965e: f003 0302 and.w r3, r3, #2
|
|
8009662: 2b00 cmp r3, #0
|
|
8009664: d0f0 beq.n 8009648 <HAL_RCC_OscConfig+0x1ac>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8009666: 4b2d ldr r3, [pc, #180] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009668: 681b ldr r3, [r3, #0]
|
|
800966a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
|
|
800966e: 687b ldr r3, [r7, #4]
|
|
8009670: 691b ldr r3, [r3, #16]
|
|
8009672: 00db lsls r3, r3, #3
|
|
8009674: 4929 ldr r1, [pc, #164] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009676: 4313 orrs r3, r2
|
|
8009678: 600b str r3, [r1, #0]
|
|
800967a: e018 b.n 80096ae <HAL_RCC_OscConfig+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800967c: 4b27 ldr r3, [pc, #156] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
800967e: 681b ldr r3, [r3, #0]
|
|
8009680: 4a26 ldr r2, [pc, #152] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
8009682: f023 0301 bic.w r3, r3, #1
|
|
8009686: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009688: f7fb fe2a bl 80052e0 <HAL_GetTick>
|
|
800968c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800968e: e008 b.n 80096a2 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8009690: f7fb fe26 bl 80052e0 <HAL_GetTick>
|
|
8009694: 4602 mov r2, r0
|
|
8009696: 693b ldr r3, [r7, #16]
|
|
8009698: 1ad3 subs r3, r2, r3
|
|
800969a: 2b02 cmp r3, #2
|
|
800969c: d901 bls.n 80096a2 <HAL_RCC_OscConfig+0x206>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800969e: 2303 movs r3, #3
|
|
80096a0: e199 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
80096a2: 4b1e ldr r3, [pc, #120] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096a4: 681b ldr r3, [r3, #0]
|
|
80096a6: f003 0302 and.w r3, r3, #2
|
|
80096aa: 2b00 cmp r3, #0
|
|
80096ac: d1f0 bne.n 8009690 <HAL_RCC_OscConfig+0x1f4>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
80096ae: 687b ldr r3, [r7, #4]
|
|
80096b0: 681b ldr r3, [r3, #0]
|
|
80096b2: f003 0308 and.w r3, r3, #8
|
|
80096b6: 2b00 cmp r3, #0
|
|
80096b8: d038 beq.n 800972c <HAL_RCC_OscConfig+0x290>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
80096ba: 687b ldr r3, [r7, #4]
|
|
80096bc: 695b ldr r3, [r3, #20]
|
|
80096be: 2b00 cmp r3, #0
|
|
80096c0: d019 beq.n 80096f6 <HAL_RCC_OscConfig+0x25a>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80096c2: 4b16 ldr r3, [pc, #88] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096c4: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
80096c6: 4a15 ldr r2, [pc, #84] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096c8: f043 0301 orr.w r3, r3, #1
|
|
80096cc: 6753 str r3, [r2, #116] ; 0x74
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80096ce: f7fb fe07 bl 80052e0 <HAL_GetTick>
|
|
80096d2: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80096d4: e008 b.n 80096e8 <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80096d6: f7fb fe03 bl 80052e0 <HAL_GetTick>
|
|
80096da: 4602 mov r2, r0
|
|
80096dc: 693b ldr r3, [r7, #16]
|
|
80096de: 1ad3 subs r3, r2, r3
|
|
80096e0: 2b02 cmp r3, #2
|
|
80096e2: d901 bls.n 80096e8 <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80096e4: 2303 movs r3, #3
|
|
80096e6: e176 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80096e8: 4b0c ldr r3, [pc, #48] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096ea: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
80096ec: f003 0302 and.w r3, r3, #2
|
|
80096f0: 2b00 cmp r3, #0
|
|
80096f2: d0f0 beq.n 80096d6 <HAL_RCC_OscConfig+0x23a>
|
|
80096f4: e01a b.n 800972c <HAL_RCC_OscConfig+0x290>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80096f6: 4b09 ldr r3, [pc, #36] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096f8: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
80096fa: 4a08 ldr r2, [pc, #32] ; (800971c <HAL_RCC_OscConfig+0x280>)
|
|
80096fc: f023 0301 bic.w r3, r3, #1
|
|
8009700: 6753 str r3, [r2, #116] ; 0x74
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009702: f7fb fded bl 80052e0 <HAL_GetTick>
|
|
8009706: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8009708: e00a b.n 8009720 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
800970a: f7fb fde9 bl 80052e0 <HAL_GetTick>
|
|
800970e: 4602 mov r2, r0
|
|
8009710: 693b ldr r3, [r7, #16]
|
|
8009712: 1ad3 subs r3, r2, r3
|
|
8009714: 2b02 cmp r3, #2
|
|
8009716: d903 bls.n 8009720 <HAL_RCC_OscConfig+0x284>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009718: 2303 movs r3, #3
|
|
800971a: e15c b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
800971c: 40023800 .word 0x40023800
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8009720: 4b91 ldr r3, [pc, #580] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009722: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8009724: f003 0302 and.w r3, r3, #2
|
|
8009728: 2b00 cmp r3, #0
|
|
800972a: d1ee bne.n 800970a <HAL_RCC_OscConfig+0x26e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800972c: 687b ldr r3, [r7, #4]
|
|
800972e: 681b ldr r3, [r3, #0]
|
|
8009730: f003 0304 and.w r3, r3, #4
|
|
8009734: 2b00 cmp r3, #0
|
|
8009736: f000 80a4 beq.w 8009882 <HAL_RCC_OscConfig+0x3e6>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800973a: 4b8b ldr r3, [pc, #556] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800973c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800973e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8009742: 2b00 cmp r3, #0
|
|
8009744: d10d bne.n 8009762 <HAL_RCC_OscConfig+0x2c6>
|
|
{
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8009746: 4b88 ldr r3, [pc, #544] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009748: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800974a: 4a87 ldr r2, [pc, #540] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800974c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8009750: 6413 str r3, [r2, #64] ; 0x40
|
|
8009752: 4b85 ldr r3, [pc, #532] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009754: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009756: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
800975a: 60bb str r3, [r7, #8]
|
|
800975c: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
800975e: 2301 movs r3, #1
|
|
8009760: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8009762: 4b82 ldr r3, [pc, #520] ; (800996c <HAL_RCC_OscConfig+0x4d0>)
|
|
8009764: 681b ldr r3, [r3, #0]
|
|
8009766: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
800976a: 2b00 cmp r3, #0
|
|
800976c: d118 bne.n 80097a0 <HAL_RCC_OscConfig+0x304>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR1 |= PWR_CR1_DBP;
|
|
800976e: 4b7f ldr r3, [pc, #508] ; (800996c <HAL_RCC_OscConfig+0x4d0>)
|
|
8009770: 681b ldr r3, [r3, #0]
|
|
8009772: 4a7e ldr r2, [pc, #504] ; (800996c <HAL_RCC_OscConfig+0x4d0>)
|
|
8009774: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8009778: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800977a: f7fb fdb1 bl 80052e0 <HAL_GetTick>
|
|
800977e: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8009780: e008 b.n 8009794 <HAL_RCC_OscConfig+0x2f8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8009782: f7fb fdad bl 80052e0 <HAL_GetTick>
|
|
8009786: 4602 mov r2, r0
|
|
8009788: 693b ldr r3, [r7, #16]
|
|
800978a: 1ad3 subs r3, r2, r3
|
|
800978c: 2b64 cmp r3, #100 ; 0x64
|
|
800978e: d901 bls.n 8009794 <HAL_RCC_OscConfig+0x2f8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009790: 2303 movs r3, #3
|
|
8009792: e120 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8009794: 4b75 ldr r3, [pc, #468] ; (800996c <HAL_RCC_OscConfig+0x4d0>)
|
|
8009796: 681b ldr r3, [r3, #0]
|
|
8009798: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
800979c: 2b00 cmp r3, #0
|
|
800979e: d0f0 beq.n 8009782 <HAL_RCC_OscConfig+0x2e6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
80097a0: 687b ldr r3, [r7, #4]
|
|
80097a2: 689b ldr r3, [r3, #8]
|
|
80097a4: 2b01 cmp r3, #1
|
|
80097a6: d106 bne.n 80097b6 <HAL_RCC_OscConfig+0x31a>
|
|
80097a8: 4b6f ldr r3, [pc, #444] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097aa: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097ac: 4a6e ldr r2, [pc, #440] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097ae: f043 0301 orr.w r3, r3, #1
|
|
80097b2: 6713 str r3, [r2, #112] ; 0x70
|
|
80097b4: e02d b.n 8009812 <HAL_RCC_OscConfig+0x376>
|
|
80097b6: 687b ldr r3, [r7, #4]
|
|
80097b8: 689b ldr r3, [r3, #8]
|
|
80097ba: 2b00 cmp r3, #0
|
|
80097bc: d10c bne.n 80097d8 <HAL_RCC_OscConfig+0x33c>
|
|
80097be: 4b6a ldr r3, [pc, #424] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097c0: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097c2: 4a69 ldr r2, [pc, #420] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097c4: f023 0301 bic.w r3, r3, #1
|
|
80097c8: 6713 str r3, [r2, #112] ; 0x70
|
|
80097ca: 4b67 ldr r3, [pc, #412] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097cc: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097ce: 4a66 ldr r2, [pc, #408] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097d0: f023 0304 bic.w r3, r3, #4
|
|
80097d4: 6713 str r3, [r2, #112] ; 0x70
|
|
80097d6: e01c b.n 8009812 <HAL_RCC_OscConfig+0x376>
|
|
80097d8: 687b ldr r3, [r7, #4]
|
|
80097da: 689b ldr r3, [r3, #8]
|
|
80097dc: 2b05 cmp r3, #5
|
|
80097de: d10c bne.n 80097fa <HAL_RCC_OscConfig+0x35e>
|
|
80097e0: 4b61 ldr r3, [pc, #388] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097e2: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097e4: 4a60 ldr r2, [pc, #384] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097e6: f043 0304 orr.w r3, r3, #4
|
|
80097ea: 6713 str r3, [r2, #112] ; 0x70
|
|
80097ec: 4b5e ldr r3, [pc, #376] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097ee: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097f0: 4a5d ldr r2, [pc, #372] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097f2: f043 0301 orr.w r3, r3, #1
|
|
80097f6: 6713 str r3, [r2, #112] ; 0x70
|
|
80097f8: e00b b.n 8009812 <HAL_RCC_OscConfig+0x376>
|
|
80097fa: 4b5b ldr r3, [pc, #364] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80097fc: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80097fe: 4a5a ldr r2, [pc, #360] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009800: f023 0301 bic.w r3, r3, #1
|
|
8009804: 6713 str r3, [r2, #112] ; 0x70
|
|
8009806: 4b58 ldr r3, [pc, #352] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009808: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800980a: 4a57 ldr r2, [pc, #348] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800980c: f023 0304 bic.w r3, r3, #4
|
|
8009810: 6713 str r3, [r2, #112] ; 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
8009812: 687b ldr r3, [r7, #4]
|
|
8009814: 689b ldr r3, [r3, #8]
|
|
8009816: 2b00 cmp r3, #0
|
|
8009818: d015 beq.n 8009846 <HAL_RCC_OscConfig+0x3aa>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800981a: f7fb fd61 bl 80052e0 <HAL_GetTick>
|
|
800981e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8009820: e00a b.n 8009838 <HAL_RCC_OscConfig+0x39c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8009822: f7fb fd5d bl 80052e0 <HAL_GetTick>
|
|
8009826: 4602 mov r2, r0
|
|
8009828: 693b ldr r3, [r7, #16]
|
|
800982a: 1ad3 subs r3, r2, r3
|
|
800982c: f241 3288 movw r2, #5000 ; 0x1388
|
|
8009830: 4293 cmp r3, r2
|
|
8009832: d901 bls.n 8009838 <HAL_RCC_OscConfig+0x39c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009834: 2303 movs r3, #3
|
|
8009836: e0ce b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8009838: 4b4b ldr r3, [pc, #300] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800983a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800983c: f003 0302 and.w r3, r3, #2
|
|
8009840: 2b00 cmp r3, #0
|
|
8009842: d0ee beq.n 8009822 <HAL_RCC_OscConfig+0x386>
|
|
8009844: e014 b.n 8009870 <HAL_RCC_OscConfig+0x3d4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009846: f7fb fd4b bl 80052e0 <HAL_GetTick>
|
|
800984a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
800984c: e00a b.n 8009864 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800984e: f7fb fd47 bl 80052e0 <HAL_GetTick>
|
|
8009852: 4602 mov r2, r0
|
|
8009854: 693b ldr r3, [r7, #16]
|
|
8009856: 1ad3 subs r3, r2, r3
|
|
8009858: f241 3288 movw r2, #5000 ; 0x1388
|
|
800985c: 4293 cmp r3, r2
|
|
800985e: d901 bls.n 8009864 <HAL_RCC_OscConfig+0x3c8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009860: 2303 movs r3, #3
|
|
8009862: e0b8 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8009864: 4b40 ldr r3, [pc, #256] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009866: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009868: f003 0302 and.w r3, r3, #2
|
|
800986c: 2b00 cmp r3, #0
|
|
800986e: d1ee bne.n 800984e <HAL_RCC_OscConfig+0x3b2>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8009870: 7dfb ldrb r3, [r7, #23]
|
|
8009872: 2b01 cmp r3, #1
|
|
8009874: d105 bne.n 8009882 <HAL_RCC_OscConfig+0x3e6>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8009876: 4b3c ldr r3, [pc, #240] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009878: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800987a: 4a3b ldr r2, [pc, #236] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800987c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
8009880: 6413 str r3, [r2, #64] ; 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8009882: 687b ldr r3, [r7, #4]
|
|
8009884: 699b ldr r3, [r3, #24]
|
|
8009886: 2b00 cmp r3, #0
|
|
8009888: f000 80a4 beq.w 80099d4 <HAL_RCC_OscConfig+0x538>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
800988c: 4b36 ldr r3, [pc, #216] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800988e: 689b ldr r3, [r3, #8]
|
|
8009890: f003 030c and.w r3, r3, #12
|
|
8009894: 2b08 cmp r3, #8
|
|
8009896: d06b beq.n 8009970 <HAL_RCC_OscConfig+0x4d4>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8009898: 687b ldr r3, [r7, #4]
|
|
800989a: 699b ldr r3, [r3, #24]
|
|
800989c: 2b02 cmp r3, #2
|
|
800989e: d149 bne.n 8009934 <HAL_RCC_OscConfig+0x498>
|
|
#if defined (RCC_PLLCFGR_PLLR)
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
#endif
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80098a0: 4b31 ldr r3, [pc, #196] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80098a2: 681b ldr r3, [r3, #0]
|
|
80098a4: 4a30 ldr r2, [pc, #192] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80098a6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
80098aa: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80098ac: f7fb fd18 bl 80052e0 <HAL_GetTick>
|
|
80098b0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80098b2: e008 b.n 80098c6 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80098b4: f7fb fd14 bl 80052e0 <HAL_GetTick>
|
|
80098b8: 4602 mov r2, r0
|
|
80098ba: 693b ldr r3, [r7, #16]
|
|
80098bc: 1ad3 subs r3, r2, r3
|
|
80098be: 2b02 cmp r3, #2
|
|
80098c0: d901 bls.n 80098c6 <HAL_RCC_OscConfig+0x42a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80098c2: 2303 movs r3, #3
|
|
80098c4: e087 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80098c6: 4b28 ldr r3, [pc, #160] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80098c8: 681b ldr r3, [r3, #0]
|
|
80098ca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
80098ce: 2b00 cmp r3, #0
|
|
80098d0: d1f0 bne.n 80098b4 <HAL_RCC_OscConfig+0x418>
|
|
RCC_OscInitStruct->PLL.PLLN,
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#else
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
80098d2: 687b ldr r3, [r7, #4]
|
|
80098d4: 69da ldr r2, [r3, #28]
|
|
80098d6: 687b ldr r3, [r7, #4]
|
|
80098d8: 6a1b ldr r3, [r3, #32]
|
|
80098da: 431a orrs r2, r3
|
|
80098dc: 687b ldr r3, [r7, #4]
|
|
80098de: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80098e0: 019b lsls r3, r3, #6
|
|
80098e2: 431a orrs r2, r3
|
|
80098e4: 687b ldr r3, [r7, #4]
|
|
80098e6: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80098e8: 085b lsrs r3, r3, #1
|
|
80098ea: 3b01 subs r3, #1
|
|
80098ec: 041b lsls r3, r3, #16
|
|
80098ee: 431a orrs r2, r3
|
|
80098f0: 687b ldr r3, [r7, #4]
|
|
80098f2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80098f4: 061b lsls r3, r3, #24
|
|
80098f6: 4313 orrs r3, r2
|
|
80098f8: 4a1b ldr r2, [pc, #108] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
80098fa: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
|
|
80098fe: 6053 str r3, [r2, #4]
|
|
RCC_OscInitStruct->PLL.PLLP,
|
|
RCC_OscInitStruct->PLL.PLLQ);
|
|
#endif
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8009900: 4b19 ldr r3, [pc, #100] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009902: 681b ldr r3, [r3, #0]
|
|
8009904: 4a18 ldr r2, [pc, #96] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009906: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
800990a: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800990c: f7fb fce8 bl 80052e0 <HAL_GetTick>
|
|
8009910: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8009912: e008 b.n 8009926 <HAL_RCC_OscConfig+0x48a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8009914: f7fb fce4 bl 80052e0 <HAL_GetTick>
|
|
8009918: 4602 mov r2, r0
|
|
800991a: 693b ldr r3, [r7, #16]
|
|
800991c: 1ad3 subs r3, r2, r3
|
|
800991e: 2b02 cmp r3, #2
|
|
8009920: d901 bls.n 8009926 <HAL_RCC_OscConfig+0x48a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009922: 2303 movs r3, #3
|
|
8009924: e057 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8009926: 4b10 ldr r3, [pc, #64] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009928: 681b ldr r3, [r3, #0]
|
|
800992a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
800992e: 2b00 cmp r3, #0
|
|
8009930: d0f0 beq.n 8009914 <HAL_RCC_OscConfig+0x478>
|
|
8009932: e04f b.n 80099d4 <HAL_RCC_OscConfig+0x538>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8009934: 4b0c ldr r3, [pc, #48] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
8009936: 681b ldr r3, [r3, #0]
|
|
8009938: 4a0b ldr r2, [pc, #44] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800993a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
800993e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009940: f7fb fcce bl 80052e0 <HAL_GetTick>
|
|
8009944: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8009946: e008 b.n 800995a <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8009948: f7fb fcca bl 80052e0 <HAL_GetTick>
|
|
800994c: 4602 mov r2, r0
|
|
800994e: 693b ldr r3, [r7, #16]
|
|
8009950: 1ad3 subs r3, r2, r3
|
|
8009952: 2b02 cmp r3, #2
|
|
8009954: d901 bls.n 800995a <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009956: 2303 movs r3, #3
|
|
8009958: e03d b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800995a: 4b03 ldr r3, [pc, #12] ; (8009968 <HAL_RCC_OscConfig+0x4cc>)
|
|
800995c: 681b ldr r3, [r3, #0]
|
|
800995e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8009962: 2b00 cmp r3, #0
|
|
8009964: d1f0 bne.n 8009948 <HAL_RCC_OscConfig+0x4ac>
|
|
8009966: e035 b.n 80099d4 <HAL_RCC_OscConfig+0x538>
|
|
8009968: 40023800 .word 0x40023800
|
|
800996c: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8009970: 4b1b ldr r3, [pc, #108] ; (80099e0 <HAL_RCC_OscConfig+0x544>)
|
|
8009972: 685b ldr r3, [r3, #4]
|
|
8009974: 60fb str r3, [r7, #12]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
#else
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8009976: 687b ldr r3, [r7, #4]
|
|
8009978: 699b ldr r3, [r3, #24]
|
|
800997a: 2b01 cmp r3, #1
|
|
800997c: d028 beq.n 80099d0 <HAL_RCC_OscConfig+0x534>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800997e: 68fb ldr r3, [r7, #12]
|
|
8009980: f403 0280 and.w r2, r3, #4194304 ; 0x400000
|
|
8009984: 687b ldr r3, [r7, #4]
|
|
8009986: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8009988: 429a cmp r2, r3
|
|
800998a: d121 bne.n 80099d0 <HAL_RCC_OscConfig+0x534>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
800998c: 68fb ldr r3, [r7, #12]
|
|
800998e: f003 023f and.w r2, r3, #63 ; 0x3f
|
|
8009992: 687b ldr r3, [r7, #4]
|
|
8009994: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8009996: 429a cmp r2, r3
|
|
8009998: d11a bne.n 80099d0 <HAL_RCC_OscConfig+0x534>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
800999a: 68fa ldr r2, [r7, #12]
|
|
800999c: f647 73c0 movw r3, #32704 ; 0x7fc0
|
|
80099a0: 4013 ands r3, r2
|
|
80099a2: 687a ldr r2, [r7, #4]
|
|
80099a4: 6a52 ldr r2, [r2, #36] ; 0x24
|
|
80099a6: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
|
80099a8: 4293 cmp r3, r2
|
|
80099aa: d111 bne.n 80099d0 <HAL_RCC_OscConfig+0x534>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
|
|
80099ac: 68fb ldr r3, [r7, #12]
|
|
80099ae: f403 3240 and.w r2, r3, #196608 ; 0x30000
|
|
80099b2: 687b ldr r3, [r7, #4]
|
|
80099b4: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
80099b6: 085b lsrs r3, r3, #1
|
|
80099b8: 3b01 subs r3, #1
|
|
80099ba: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
80099bc: 429a cmp r2, r3
|
|
80099be: d107 bne.n 80099d0 <HAL_RCC_OscConfig+0x534>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
80099c0: 68fb ldr r3, [r7, #12]
|
|
80099c2: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
|
|
80099c6: 687b ldr r3, [r7, #4]
|
|
80099c8: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
80099ca: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
|
|
80099cc: 429a cmp r2, r3
|
|
80099ce: d001 beq.n 80099d4 <HAL_RCC_OscConfig+0x538>
|
|
#endif
|
|
{
|
|
return HAL_ERROR;
|
|
80099d0: 2301 movs r3, #1
|
|
80099d2: e000 b.n 80099d6 <HAL_RCC_OscConfig+0x53a>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80099d4: 2300 movs r3, #0
|
|
}
|
|
80099d6: 4618 mov r0, r3
|
|
80099d8: 3718 adds r7, #24
|
|
80099da: 46bd mov sp, r7
|
|
80099dc: bd80 pop {r7, pc}
|
|
80099de: bf00 nop
|
|
80099e0: 40023800 .word 0x40023800
|
|
|
|
080099e4 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80099e4: b580 push {r7, lr}
|
|
80099e6: b084 sub sp, #16
|
|
80099e8: af00 add r7, sp, #0
|
|
80099ea: 6078 str r0, [r7, #4]
|
|
80099ec: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart = 0;
|
|
80099ee: 2300 movs r3, #0
|
|
80099f0: 60fb str r3, [r7, #12]
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
80099f2: 687b ldr r3, [r7, #4]
|
|
80099f4: 2b00 cmp r3, #0
|
|
80099f6: d101 bne.n 80099fc <HAL_RCC_ClockConfig+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
80099f8: 2301 movs r3, #1
|
|
80099fa: e0d0 b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80099fc: 4b6a ldr r3, [pc, #424] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
80099fe: 681b ldr r3, [r3, #0]
|
|
8009a00: f003 030f and.w r3, r3, #15
|
|
8009a04: 683a ldr r2, [r7, #0]
|
|
8009a06: 429a cmp r2, r3
|
|
8009a08: d910 bls.n 8009a2c <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8009a0a: 4b67 ldr r3, [pc, #412] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009a0c: 681b ldr r3, [r3, #0]
|
|
8009a0e: f023 020f bic.w r2, r3, #15
|
|
8009a12: 4965 ldr r1, [pc, #404] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009a14: 683b ldr r3, [r7, #0]
|
|
8009a16: 4313 orrs r3, r2
|
|
8009a18: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8009a1a: 4b63 ldr r3, [pc, #396] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009a1c: 681b ldr r3, [r3, #0]
|
|
8009a1e: f003 030f and.w r3, r3, #15
|
|
8009a22: 683a ldr r2, [r7, #0]
|
|
8009a24: 429a cmp r2, r3
|
|
8009a26: d001 beq.n 8009a2c <HAL_RCC_ClockConfig+0x48>
|
|
{
|
|
return HAL_ERROR;
|
|
8009a28: 2301 movs r3, #1
|
|
8009a2a: e0b8 b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8009a2c: 687b ldr r3, [r7, #4]
|
|
8009a2e: 681b ldr r3, [r3, #0]
|
|
8009a30: f003 0302 and.w r3, r3, #2
|
|
8009a34: 2b00 cmp r3, #0
|
|
8009a36: d020 beq.n 8009a7a <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8009a38: 687b ldr r3, [r7, #4]
|
|
8009a3a: 681b ldr r3, [r3, #0]
|
|
8009a3c: f003 0304 and.w r3, r3, #4
|
|
8009a40: 2b00 cmp r3, #0
|
|
8009a42: d005 beq.n 8009a50 <HAL_RCC_ClockConfig+0x6c>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8009a44: 4b59 ldr r3, [pc, #356] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a46: 689b ldr r3, [r3, #8]
|
|
8009a48: 4a58 ldr r2, [pc, #352] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a4a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
|
|
8009a4e: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8009a50: 687b ldr r3, [r7, #4]
|
|
8009a52: 681b ldr r3, [r3, #0]
|
|
8009a54: f003 0308 and.w r3, r3, #8
|
|
8009a58: 2b00 cmp r3, #0
|
|
8009a5a: d005 beq.n 8009a68 <HAL_RCC_ClockConfig+0x84>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8009a5c: 4b53 ldr r3, [pc, #332] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a5e: 689b ldr r3, [r3, #8]
|
|
8009a60: 4a52 ldr r2, [pc, #328] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a62: f443 4360 orr.w r3, r3, #57344 ; 0xe000
|
|
8009a66: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
/* Set the new HCLK clock divider */
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8009a68: 4b50 ldr r3, [pc, #320] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a6a: 689b ldr r3, [r3, #8]
|
|
8009a6c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
|
|
8009a70: 687b ldr r3, [r7, #4]
|
|
8009a72: 689b ldr r3, [r3, #8]
|
|
8009a74: 494d ldr r1, [pc, #308] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a76: 4313 orrs r3, r2
|
|
8009a78: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8009a7a: 687b ldr r3, [r7, #4]
|
|
8009a7c: 681b ldr r3, [r3, #0]
|
|
8009a7e: f003 0301 and.w r3, r3, #1
|
|
8009a82: 2b00 cmp r3, #0
|
|
8009a84: d040 beq.n 8009b08 <HAL_RCC_ClockConfig+0x124>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8009a86: 687b ldr r3, [r7, #4]
|
|
8009a88: 685b ldr r3, [r3, #4]
|
|
8009a8a: 2b01 cmp r3, #1
|
|
8009a8c: d107 bne.n 8009a9e <HAL_RCC_ClockConfig+0xba>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8009a8e: 4b47 ldr r3, [pc, #284] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009a90: 681b ldr r3, [r3, #0]
|
|
8009a92: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
8009a96: 2b00 cmp r3, #0
|
|
8009a98: d115 bne.n 8009ac6 <HAL_RCC_ClockConfig+0xe2>
|
|
{
|
|
return HAL_ERROR;
|
|
8009a9a: 2301 movs r3, #1
|
|
8009a9c: e07f b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
8009a9e: 687b ldr r3, [r7, #4]
|
|
8009aa0: 685b ldr r3, [r3, #4]
|
|
8009aa2: 2b02 cmp r3, #2
|
|
8009aa4: d107 bne.n 8009ab6 <HAL_RCC_ClockConfig+0xd2>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8009aa6: 4b41 ldr r3, [pc, #260] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009aa8: 681b ldr r3, [r3, #0]
|
|
8009aaa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
8009aae: 2b00 cmp r3, #0
|
|
8009ab0: d109 bne.n 8009ac6 <HAL_RCC_ClockConfig+0xe2>
|
|
{
|
|
return HAL_ERROR;
|
|
8009ab2: 2301 movs r3, #1
|
|
8009ab4: e073 b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8009ab6: 4b3d ldr r3, [pc, #244] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009ab8: 681b ldr r3, [r3, #0]
|
|
8009aba: f003 0302 and.w r3, r3, #2
|
|
8009abe: 2b00 cmp r3, #0
|
|
8009ac0: d101 bne.n 8009ac6 <HAL_RCC_ClockConfig+0xe2>
|
|
{
|
|
return HAL_ERROR;
|
|
8009ac2: 2301 movs r3, #1
|
|
8009ac4: e06b b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8009ac6: 4b39 ldr r3, [pc, #228] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009ac8: 689b ldr r3, [r3, #8]
|
|
8009aca: f023 0203 bic.w r2, r3, #3
|
|
8009ace: 687b ldr r3, [r7, #4]
|
|
8009ad0: 685b ldr r3, [r3, #4]
|
|
8009ad2: 4936 ldr r1, [pc, #216] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009ad4: 4313 orrs r3, r2
|
|
8009ad6: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009ad8: f7fb fc02 bl 80052e0 <HAL_GetTick>
|
|
8009adc: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8009ade: e00a b.n 8009af6 <HAL_RCC_ClockConfig+0x112>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8009ae0: f7fb fbfe bl 80052e0 <HAL_GetTick>
|
|
8009ae4: 4602 mov r2, r0
|
|
8009ae6: 68fb ldr r3, [r7, #12]
|
|
8009ae8: 1ad3 subs r3, r2, r3
|
|
8009aea: f241 3288 movw r2, #5000 ; 0x1388
|
|
8009aee: 4293 cmp r3, r2
|
|
8009af0: d901 bls.n 8009af6 <HAL_RCC_ClockConfig+0x112>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009af2: 2303 movs r3, #3
|
|
8009af4: e053 b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8009af6: 4b2d ldr r3, [pc, #180] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009af8: 689b ldr r3, [r3, #8]
|
|
8009afa: f003 020c and.w r2, r3, #12
|
|
8009afe: 687b ldr r3, [r7, #4]
|
|
8009b00: 685b ldr r3, [r3, #4]
|
|
8009b02: 009b lsls r3, r3, #2
|
|
8009b04: 429a cmp r2, r3
|
|
8009b06: d1eb bne.n 8009ae0 <HAL_RCC_ClockConfig+0xfc>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8009b08: 4b27 ldr r3, [pc, #156] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009b0a: 681b ldr r3, [r3, #0]
|
|
8009b0c: f003 030f and.w r3, r3, #15
|
|
8009b10: 683a ldr r2, [r7, #0]
|
|
8009b12: 429a cmp r2, r3
|
|
8009b14: d210 bcs.n 8009b38 <HAL_RCC_ClockConfig+0x154>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8009b16: 4b24 ldr r3, [pc, #144] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009b18: 681b ldr r3, [r3, #0]
|
|
8009b1a: f023 020f bic.w r2, r3, #15
|
|
8009b1e: 4922 ldr r1, [pc, #136] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009b20: 683b ldr r3, [r7, #0]
|
|
8009b22: 4313 orrs r3, r2
|
|
8009b24: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8009b26: 4b20 ldr r3, [pc, #128] ; (8009ba8 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8009b28: 681b ldr r3, [r3, #0]
|
|
8009b2a: f003 030f and.w r3, r3, #15
|
|
8009b2e: 683a ldr r2, [r7, #0]
|
|
8009b30: 429a cmp r2, r3
|
|
8009b32: d001 beq.n 8009b38 <HAL_RCC_ClockConfig+0x154>
|
|
{
|
|
return HAL_ERROR;
|
|
8009b34: 2301 movs r3, #1
|
|
8009b36: e032 b.n 8009b9e <HAL_RCC_ClockConfig+0x1ba>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8009b38: 687b ldr r3, [r7, #4]
|
|
8009b3a: 681b ldr r3, [r3, #0]
|
|
8009b3c: f003 0304 and.w r3, r3, #4
|
|
8009b40: 2b00 cmp r3, #0
|
|
8009b42: d008 beq.n 8009b56 <HAL_RCC_ClockConfig+0x172>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8009b44: 4b19 ldr r3, [pc, #100] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009b46: 689b ldr r3, [r3, #8]
|
|
8009b48: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
|
|
8009b4c: 687b ldr r3, [r7, #4]
|
|
8009b4e: 68db ldr r3, [r3, #12]
|
|
8009b50: 4916 ldr r1, [pc, #88] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009b52: 4313 orrs r3, r2
|
|
8009b54: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8009b56: 687b ldr r3, [r7, #4]
|
|
8009b58: 681b ldr r3, [r3, #0]
|
|
8009b5a: f003 0308 and.w r3, r3, #8
|
|
8009b5e: 2b00 cmp r3, #0
|
|
8009b60: d009 beq.n 8009b76 <HAL_RCC_ClockConfig+0x192>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
8009b62: 4b12 ldr r3, [pc, #72] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009b64: 689b ldr r3, [r3, #8]
|
|
8009b66: f423 4260 bic.w r2, r3, #57344 ; 0xe000
|
|
8009b6a: 687b ldr r3, [r7, #4]
|
|
8009b6c: 691b ldr r3, [r3, #16]
|
|
8009b6e: 00db lsls r3, r3, #3
|
|
8009b70: 490e ldr r1, [pc, #56] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009b72: 4313 orrs r3, r2
|
|
8009b74: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8009b76: f000 f821 bl 8009bbc <HAL_RCC_GetSysClockFreq>
|
|
8009b7a: 4601 mov r1, r0
|
|
8009b7c: 4b0b ldr r3, [pc, #44] ; (8009bac <HAL_RCC_ClockConfig+0x1c8>)
|
|
8009b7e: 689b ldr r3, [r3, #8]
|
|
8009b80: 091b lsrs r3, r3, #4
|
|
8009b82: f003 030f and.w r3, r3, #15
|
|
8009b86: 4a0a ldr r2, [pc, #40] ; (8009bb0 <HAL_RCC_ClockConfig+0x1cc>)
|
|
8009b88: 5cd3 ldrb r3, [r2, r3]
|
|
8009b8a: fa21 f303 lsr.w r3, r1, r3
|
|
8009b8e: 4a09 ldr r2, [pc, #36] ; (8009bb4 <HAL_RCC_ClockConfig+0x1d0>)
|
|
8009b90: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick(uwTickPrio);
|
|
8009b92: 4b09 ldr r3, [pc, #36] ; (8009bb8 <HAL_RCC_ClockConfig+0x1d4>)
|
|
8009b94: 681b ldr r3, [r3, #0]
|
|
8009b96: 4618 mov r0, r3
|
|
8009b98: f7fb fa0c bl 8004fb4 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8009b9c: 2300 movs r3, #0
|
|
}
|
|
8009b9e: 4618 mov r0, r3
|
|
8009ba0: 3710 adds r7, #16
|
|
8009ba2: 46bd mov sp, r7
|
|
8009ba4: bd80 pop {r7, pc}
|
|
8009ba6: bf00 nop
|
|
8009ba8: 40023c00 .word 0x40023c00
|
|
8009bac: 40023800 .word 0x40023800
|
|
8009bb0: 08022d28 .word 0x08022d28
|
|
8009bb4: 20000064 .word 0x20000064
|
|
8009bb8: 20000068 .word 0x20000068
|
|
|
|
08009bbc <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8009bbc: b5f0 push {r4, r5, r6, r7, lr}
|
|
8009bbe: b085 sub sp, #20
|
|
8009bc0: af00 add r7, sp, #0
|
|
uint32_t pllm = 0, pllvco = 0, pllp = 0;
|
|
8009bc2: 2300 movs r3, #0
|
|
8009bc4: 607b str r3, [r7, #4]
|
|
8009bc6: 2300 movs r3, #0
|
|
8009bc8: 60fb str r3, [r7, #12]
|
|
8009bca: 2300 movs r3, #0
|
|
8009bcc: 603b str r3, [r7, #0]
|
|
uint32_t sysclockfreq = 0;
|
|
8009bce: 2300 movs r3, #0
|
|
8009bd0: 60bb str r3, [r7, #8]
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8009bd2: 4b50 ldr r3, [pc, #320] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009bd4: 689b ldr r3, [r3, #8]
|
|
8009bd6: f003 030c and.w r3, r3, #12
|
|
8009bda: 2b04 cmp r3, #4
|
|
8009bdc: d007 beq.n 8009bee <HAL_RCC_GetSysClockFreq+0x32>
|
|
8009bde: 2b08 cmp r3, #8
|
|
8009be0: d008 beq.n 8009bf4 <HAL_RCC_GetSysClockFreq+0x38>
|
|
8009be2: 2b00 cmp r3, #0
|
|
8009be4: f040 808d bne.w 8009d02 <HAL_RCC_GetSysClockFreq+0x146>
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8009be8: 4b4b ldr r3, [pc, #300] ; (8009d18 <HAL_RCC_GetSysClockFreq+0x15c>)
|
|
8009bea: 60bb str r3, [r7, #8]
|
|
break;
|
|
8009bec: e08c b.n 8009d08 <HAL_RCC_GetSysClockFreq+0x14c>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8009bee: 4b4b ldr r3, [pc, #300] ; (8009d1c <HAL_RCC_GetSysClockFreq+0x160>)
|
|
8009bf0: 60bb str r3, [r7, #8]
|
|
break;
|
|
8009bf2: e089 b.n 8009d08 <HAL_RCC_GetSysClockFreq+0x14c>
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8009bf4: 4b47 ldr r3, [pc, #284] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009bf6: 685b ldr r3, [r3, #4]
|
|
8009bf8: f003 033f and.w r3, r3, #63 ; 0x3f
|
|
8009bfc: 607b str r3, [r7, #4]
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
|
|
8009bfe: 4b45 ldr r3, [pc, #276] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009c00: 685b ldr r3, [r3, #4]
|
|
8009c02: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
8009c06: 2b00 cmp r3, #0
|
|
8009c08: d023 beq.n 8009c52 <HAL_RCC_GetSysClockFreq+0x96>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8009c0a: 4b42 ldr r3, [pc, #264] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009c0c: 685b ldr r3, [r3, #4]
|
|
8009c0e: 099b lsrs r3, r3, #6
|
|
8009c10: f04f 0400 mov.w r4, #0
|
|
8009c14: f240 11ff movw r1, #511 ; 0x1ff
|
|
8009c18: f04f 0200 mov.w r2, #0
|
|
8009c1c: ea03 0501 and.w r5, r3, r1
|
|
8009c20: ea04 0602 and.w r6, r4, r2
|
|
8009c24: 4a3d ldr r2, [pc, #244] ; (8009d1c <HAL_RCC_GetSysClockFreq+0x160>)
|
|
8009c26: fb02 f106 mul.w r1, r2, r6
|
|
8009c2a: 2200 movs r2, #0
|
|
8009c2c: fb02 f205 mul.w r2, r2, r5
|
|
8009c30: 440a add r2, r1
|
|
8009c32: 493a ldr r1, [pc, #232] ; (8009d1c <HAL_RCC_GetSysClockFreq+0x160>)
|
|
8009c34: fba5 0101 umull r0, r1, r5, r1
|
|
8009c38: 1853 adds r3, r2, r1
|
|
8009c3a: 4619 mov r1, r3
|
|
8009c3c: 687b ldr r3, [r7, #4]
|
|
8009c3e: f04f 0400 mov.w r4, #0
|
|
8009c42: 461a mov r2, r3
|
|
8009c44: 4623 mov r3, r4
|
|
8009c46: f7f6 fb33 bl 80002b0 <__aeabi_uldivmod>
|
|
8009c4a: 4603 mov r3, r0
|
|
8009c4c: 460c mov r4, r1
|
|
8009c4e: 60fb str r3, [r7, #12]
|
|
8009c50: e049 b.n 8009ce6 <HAL_RCC_GetSysClockFreq+0x12a>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8009c52: 4b30 ldr r3, [pc, #192] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009c54: 685b ldr r3, [r3, #4]
|
|
8009c56: 099b lsrs r3, r3, #6
|
|
8009c58: f04f 0400 mov.w r4, #0
|
|
8009c5c: f240 11ff movw r1, #511 ; 0x1ff
|
|
8009c60: f04f 0200 mov.w r2, #0
|
|
8009c64: ea03 0501 and.w r5, r3, r1
|
|
8009c68: ea04 0602 and.w r6, r4, r2
|
|
8009c6c: 4629 mov r1, r5
|
|
8009c6e: 4632 mov r2, r6
|
|
8009c70: f04f 0300 mov.w r3, #0
|
|
8009c74: f04f 0400 mov.w r4, #0
|
|
8009c78: 0154 lsls r4, r2, #5
|
|
8009c7a: ea44 64d1 orr.w r4, r4, r1, lsr #27
|
|
8009c7e: 014b lsls r3, r1, #5
|
|
8009c80: 4619 mov r1, r3
|
|
8009c82: 4622 mov r2, r4
|
|
8009c84: 1b49 subs r1, r1, r5
|
|
8009c86: eb62 0206 sbc.w r2, r2, r6
|
|
8009c8a: f04f 0300 mov.w r3, #0
|
|
8009c8e: f04f 0400 mov.w r4, #0
|
|
8009c92: 0194 lsls r4, r2, #6
|
|
8009c94: ea44 6491 orr.w r4, r4, r1, lsr #26
|
|
8009c98: 018b lsls r3, r1, #6
|
|
8009c9a: 1a5b subs r3, r3, r1
|
|
8009c9c: eb64 0402 sbc.w r4, r4, r2
|
|
8009ca0: f04f 0100 mov.w r1, #0
|
|
8009ca4: f04f 0200 mov.w r2, #0
|
|
8009ca8: 00e2 lsls r2, r4, #3
|
|
8009caa: ea42 7253 orr.w r2, r2, r3, lsr #29
|
|
8009cae: 00d9 lsls r1, r3, #3
|
|
8009cb0: 460b mov r3, r1
|
|
8009cb2: 4614 mov r4, r2
|
|
8009cb4: 195b adds r3, r3, r5
|
|
8009cb6: eb44 0406 adc.w r4, r4, r6
|
|
8009cba: f04f 0100 mov.w r1, #0
|
|
8009cbe: f04f 0200 mov.w r2, #0
|
|
8009cc2: 02a2 lsls r2, r4, #10
|
|
8009cc4: ea42 5293 orr.w r2, r2, r3, lsr #22
|
|
8009cc8: 0299 lsls r1, r3, #10
|
|
8009cca: 460b mov r3, r1
|
|
8009ccc: 4614 mov r4, r2
|
|
8009cce: 4618 mov r0, r3
|
|
8009cd0: 4621 mov r1, r4
|
|
8009cd2: 687b ldr r3, [r7, #4]
|
|
8009cd4: f04f 0400 mov.w r4, #0
|
|
8009cd8: 461a mov r2, r3
|
|
8009cda: 4623 mov r3, r4
|
|
8009cdc: f7f6 fae8 bl 80002b0 <__aeabi_uldivmod>
|
|
8009ce0: 4603 mov r3, r0
|
|
8009ce2: 460c mov r4, r1
|
|
8009ce4: 60fb str r3, [r7, #12]
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
|
|
8009ce6: 4b0b ldr r3, [pc, #44] ; (8009d14 <HAL_RCC_GetSysClockFreq+0x158>)
|
|
8009ce8: 685b ldr r3, [r3, #4]
|
|
8009cea: 0c1b lsrs r3, r3, #16
|
|
8009cec: f003 0303 and.w r3, r3, #3
|
|
8009cf0: 3301 adds r3, #1
|
|
8009cf2: 005b lsls r3, r3, #1
|
|
8009cf4: 603b str r3, [r7, #0]
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8009cf6: 68fa ldr r2, [r7, #12]
|
|
8009cf8: 683b ldr r3, [r7, #0]
|
|
8009cfa: fbb2 f3f3 udiv r3, r2, r3
|
|
8009cfe: 60bb str r3, [r7, #8]
|
|
break;
|
|
8009d00: e002 b.n 8009d08 <HAL_RCC_GetSysClockFreq+0x14c>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8009d02: 4b05 ldr r3, [pc, #20] ; (8009d18 <HAL_RCC_GetSysClockFreq+0x15c>)
|
|
8009d04: 60bb str r3, [r7, #8]
|
|
break;
|
|
8009d06: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8009d08: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8009d0a: 4618 mov r0, r3
|
|
8009d0c: 3714 adds r7, #20
|
|
8009d0e: 46bd mov sp, r7
|
|
8009d10: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8009d12: bf00 nop
|
|
8009d14: 40023800 .word 0x40023800
|
|
8009d18: 00f42400 .word 0x00f42400
|
|
8009d1c: 017d7840 .word 0x017d7840
|
|
|
|
08009d20 <HAL_RCC_GetHCLKFreq>:
|
|
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8009d20: b480 push {r7}
|
|
8009d22: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8009d24: 4b03 ldr r3, [pc, #12] ; (8009d34 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8009d26: 681b ldr r3, [r3, #0]
|
|
}
|
|
8009d28: 4618 mov r0, r3
|
|
8009d2a: 46bd mov sp, r7
|
|
8009d2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009d30: 4770 bx lr
|
|
8009d32: bf00 nop
|
|
8009d34: 20000064 .word 0x20000064
|
|
|
|
08009d38 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8009d38: b580 push {r7, lr}
|
|
8009d3a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
8009d3c: f7ff fff0 bl 8009d20 <HAL_RCC_GetHCLKFreq>
|
|
8009d40: 4601 mov r1, r0
|
|
8009d42: 4b05 ldr r3, [pc, #20] ; (8009d58 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
8009d44: 689b ldr r3, [r3, #8]
|
|
8009d46: 0a9b lsrs r3, r3, #10
|
|
8009d48: f003 0307 and.w r3, r3, #7
|
|
8009d4c: 4a03 ldr r2, [pc, #12] ; (8009d5c <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8009d4e: 5cd3 ldrb r3, [r2, r3]
|
|
8009d50: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8009d54: 4618 mov r0, r3
|
|
8009d56: bd80 pop {r7, pc}
|
|
8009d58: 40023800 .word 0x40023800
|
|
8009d5c: 08022d38 .word 0x08022d38
|
|
|
|
08009d60 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8009d60: b580 push {r7, lr}
|
|
8009d62: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
8009d64: f7ff ffdc bl 8009d20 <HAL_RCC_GetHCLKFreq>
|
|
8009d68: 4601 mov r1, r0
|
|
8009d6a: 4b05 ldr r3, [pc, #20] ; (8009d80 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
8009d6c: 689b ldr r3, [r3, #8]
|
|
8009d6e: 0b5b lsrs r3, r3, #13
|
|
8009d70: f003 0307 and.w r3, r3, #7
|
|
8009d74: 4a03 ldr r2, [pc, #12] ; (8009d84 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8009d76: 5cd3 ldrb r3, [r2, r3]
|
|
8009d78: fa21 f303 lsr.w r3, r1, r3
|
|
}
|
|
8009d7c: 4618 mov r0, r3
|
|
8009d7e: bd80 pop {r7, pc}
|
|
8009d80: 40023800 .word 0x40023800
|
|
8009d84: 08022d38 .word 0x08022d38
|
|
|
|
08009d88 <HAL_RCC_GetClockConfig>:
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
8009d88: b480 push {r7}
|
|
8009d8a: b083 sub sp, #12
|
|
8009d8c: af00 add r7, sp, #0
|
|
8009d8e: 6078 str r0, [r7, #4]
|
|
8009d90: 6039 str r1, [r7, #0]
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
8009d92: 687b ldr r3, [r7, #4]
|
|
8009d94: 220f movs r2, #15
|
|
8009d96: 601a str r2, [r3, #0]
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
8009d98: 4b12 ldr r3, [pc, #72] ; (8009de4 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8009d9a: 689b ldr r3, [r3, #8]
|
|
8009d9c: f003 0203 and.w r2, r3, #3
|
|
8009da0: 687b ldr r3, [r7, #4]
|
|
8009da2: 605a str r2, [r3, #4]
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
8009da4: 4b0f ldr r3, [pc, #60] ; (8009de4 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8009da6: 689b ldr r3, [r3, #8]
|
|
8009da8: f003 02f0 and.w r2, r3, #240 ; 0xf0
|
|
8009dac: 687b ldr r3, [r7, #4]
|
|
8009dae: 609a str r2, [r3, #8]
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
8009db0: 4b0c ldr r3, [pc, #48] ; (8009de4 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8009db2: 689b ldr r3, [r3, #8]
|
|
8009db4: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
|
|
8009db8: 687b ldr r3, [r7, #4]
|
|
8009dba: 60da str r2, [r3, #12]
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
|
|
8009dbc: 4b09 ldr r3, [pc, #36] ; (8009de4 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8009dbe: 689b ldr r3, [r3, #8]
|
|
8009dc0: 08db lsrs r3, r3, #3
|
|
8009dc2: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
|
|
8009dc6: 687b ldr r3, [r7, #4]
|
|
8009dc8: 611a str r2, [r3, #16]
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
8009dca: 4b07 ldr r3, [pc, #28] ; (8009de8 <HAL_RCC_GetClockConfig+0x60>)
|
|
8009dcc: 681b ldr r3, [r3, #0]
|
|
8009dce: f003 020f and.w r2, r3, #15
|
|
8009dd2: 683b ldr r3, [r7, #0]
|
|
8009dd4: 601a str r2, [r3, #0]
|
|
}
|
|
8009dd6: bf00 nop
|
|
8009dd8: 370c adds r7, #12
|
|
8009dda: 46bd mov sp, r7
|
|
8009ddc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009de0: 4770 bx lr
|
|
8009de2: bf00 nop
|
|
8009de4: 40023800 .word 0x40023800
|
|
8009de8: 40023c00 .word 0x40023c00
|
|
|
|
08009dec <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8009dec: b580 push {r7, lr}
|
|
8009dee: b088 sub sp, #32
|
|
8009df0: af00 add r7, sp, #0
|
|
8009df2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0;
|
|
8009df4: 2300 movs r3, #0
|
|
8009df6: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg0 = 0;
|
|
8009df8: 2300 movs r3, #0
|
|
8009dfa: 613b str r3, [r7, #16]
|
|
uint32_t tmpreg1 = 0;
|
|
8009dfc: 2300 movs r3, #0
|
|
8009dfe: 60fb str r3, [r7, #12]
|
|
uint32_t plli2sused = 0;
|
|
8009e00: 2300 movs r3, #0
|
|
8009e02: 61fb str r3, [r7, #28]
|
|
uint32_t pllsaiused = 0;
|
|
8009e04: 2300 movs r3, #0
|
|
8009e06: 61bb str r3, [r7, #24]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*----------------------------------- I2S configuration ----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
|
8009e08: 687b ldr r3, [r7, #4]
|
|
8009e0a: 681b ldr r3, [r3, #0]
|
|
8009e0c: f003 0301 and.w r3, r3, #1
|
|
8009e10: 2b00 cmp r3, #0
|
|
8009e12: d012 beq.n 8009e3a <HAL_RCCEx_PeriphCLKConfig+0x4e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
|
|
|
|
/* Configure I2S Clock source */
|
|
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
|
|
8009e14: 4b69 ldr r3, [pc, #420] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e16: 689b ldr r3, [r3, #8]
|
|
8009e18: 4a68 ldr r2, [pc, #416] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e1a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
|
|
8009e1e: 6093 str r3, [r2, #8]
|
|
8009e20: 4b66 ldr r3, [pc, #408] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e22: 689a ldr r2, [r3, #8]
|
|
8009e24: 687b ldr r3, [r7, #4]
|
|
8009e26: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8009e28: 4964 ldr r1, [pc, #400] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e2a: 4313 orrs r3, r2
|
|
8009e2c: 608b str r3, [r1, #8]
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for I2S */
|
|
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
|
|
8009e2e: 687b ldr r3, [r7, #4]
|
|
8009e30: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8009e32: 2b00 cmp r3, #0
|
|
8009e34: d101 bne.n 8009e3a <HAL_RCCEx_PeriphCLKConfig+0x4e>
|
|
{
|
|
plli2sused = 1;
|
|
8009e36: 2301 movs r3, #1
|
|
8009e38: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
|
|
/*------------------------------------ SAI1 configuration --------------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
|
|
8009e3a: 687b ldr r3, [r7, #4]
|
|
8009e3c: 681b ldr r3, [r3, #0]
|
|
8009e3e: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
|
8009e42: 2b00 cmp r3, #0
|
|
8009e44: d017 beq.n 8009e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
/* Configure SAI1 Clock source */
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
8009e46: 4b5d ldr r3, [pc, #372] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e48: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
8009e4c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
|
|
8009e50: 687b ldr r3, [r7, #4]
|
|
8009e52: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
8009e54: 4959 ldr r1, [pc, #356] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e56: 4313 orrs r3, r2
|
|
8009e58: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
|
|
8009e5c: 687b ldr r3, [r7, #4]
|
|
8009e5e: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
8009e60: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
8009e64: d101 bne.n 8009e6a <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
{
|
|
plli2sused = 1;
|
|
8009e66: 2301 movs r3, #1
|
|
8009e68: 61fb str r3, [r7, #28]
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
|
|
8009e6a: 687b ldr r3, [r7, #4]
|
|
8009e6c: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
8009e6e: 2b00 cmp r3, #0
|
|
8009e70: d101 bne.n 8009e76 <HAL_RCCEx_PeriphCLKConfig+0x8a>
|
|
{
|
|
pllsaiused = 1;
|
|
8009e72: 2301 movs r3, #1
|
|
8009e74: 61bb str r3, [r7, #24]
|
|
}
|
|
}
|
|
|
|
/*------------------------------------ SAI2 configuration --------------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
|
|
8009e76: 687b ldr r3, [r7, #4]
|
|
8009e78: 681b ldr r3, [r3, #0]
|
|
8009e7a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
8009e7e: 2b00 cmp r3, #0
|
|
8009e80: d017 beq.n 8009eb2 <HAL_RCCEx_PeriphCLKConfig+0xc6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
/* Configure SAI2 Clock source */
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8009e82: 4b4e ldr r3, [pc, #312] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e84: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
8009e88: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
|
|
8009e8c: 687b ldr r3, [r7, #4]
|
|
8009e8e: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009e90: 494a ldr r1, [pc, #296] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009e92: 4313 orrs r3, r2
|
|
8009e94: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
|
|
/* Enable the PLLI2S when it's used as clock source for SAI */
|
|
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
|
|
8009e98: 687b ldr r3, [r7, #4]
|
|
8009e9a: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009e9c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
|
8009ea0: d101 bne.n 8009ea6 <HAL_RCCEx_PeriphCLKConfig+0xba>
|
|
{
|
|
plli2sused = 1;
|
|
8009ea2: 2301 movs r3, #1
|
|
8009ea4: 61fb str r3, [r7, #28]
|
|
}
|
|
/* Enable the PLLSAI when it's used as clock source for SAI */
|
|
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
|
|
8009ea6: 687b ldr r3, [r7, #4]
|
|
8009ea8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009eaa: 2b00 cmp r3, #0
|
|
8009eac: d101 bne.n 8009eb2 <HAL_RCCEx_PeriphCLKConfig+0xc6>
|
|
{
|
|
pllsaiused = 1;
|
|
8009eae: 2301 movs r3, #1
|
|
8009eb0: 61bb str r3, [r7, #24]
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
8009eb2: 687b ldr r3, [r7, #4]
|
|
8009eb4: 681b ldr r3, [r3, #0]
|
|
8009eb6: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
8009eba: 2b00 cmp r3, #0
|
|
8009ebc: d001 beq.n 8009ec2 <HAL_RCCEx_PeriphCLKConfig+0xd6>
|
|
{
|
|
plli2sused = 1;
|
|
8009ebe: 2301 movs r3, #1
|
|
8009ec0: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/*------------------------------------ RTC configuration --------------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
8009ec2: 687b ldr r3, [r7, #4]
|
|
8009ec4: 681b ldr r3, [r3, #0]
|
|
8009ec6: f003 0320 and.w r3, r3, #32
|
|
8009eca: 2b00 cmp r3, #0
|
|
8009ecc: f000 808b beq.w 8009fe6 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8009ed0: 4b3a ldr r3, [pc, #232] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009ed2: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009ed4: 4a39 ldr r2, [pc, #228] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009ed6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
8009eda: 6413 str r3, [r2, #64] ; 0x40
|
|
8009edc: 4b37 ldr r3, [pc, #220] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009ede: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
8009ee0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
|
|
8009ee4: 60bb str r3, [r7, #8]
|
|
8009ee6: 68bb ldr r3, [r7, #8]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR1 |= PWR_CR1_DBP;
|
|
8009ee8: 4b35 ldr r3, [pc, #212] ; (8009fc0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
|
|
8009eea: 681b ldr r3, [r3, #0]
|
|
8009eec: 4a34 ldr r2, [pc, #208] ; (8009fc0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
|
|
8009eee: f443 7380 orr.w r3, r3, #256 ; 0x100
|
|
8009ef2: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009ef4: f7fb f9f4 bl 80052e0 <HAL_GetTick>
|
|
8009ef8: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
|
|
8009efa: e008 b.n 8009f0e <HAL_RCCEx_PeriphCLKConfig+0x122>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8009efc: f7fb f9f0 bl 80052e0 <HAL_GetTick>
|
|
8009f00: 4602 mov r2, r0
|
|
8009f02: 697b ldr r3, [r7, #20]
|
|
8009f04: 1ad3 subs r3, r2, r3
|
|
8009f06: 2b64 cmp r3, #100 ; 0x64
|
|
8009f08: d901 bls.n 8009f0e <HAL_RCCEx_PeriphCLKConfig+0x122>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009f0a: 2303 movs r3, #3
|
|
8009f0c: e355 b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
|
|
8009f0e: 4b2c ldr r3, [pc, #176] ; (8009fc0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
|
|
8009f10: 681b ldr r3, [r3, #0]
|
|
8009f12: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
8009f16: 2b00 cmp r3, #0
|
|
8009f18: d0f0 beq.n 8009efc <HAL_RCCEx_PeriphCLKConfig+0x110>
|
|
}
|
|
}
|
|
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified */
|
|
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
8009f1a: 4b28 ldr r3, [pc, #160] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f1c: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f1e: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8009f22: 613b str r3, [r7, #16]
|
|
|
|
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
8009f24: 693b ldr r3, [r7, #16]
|
|
8009f26: 2b00 cmp r3, #0
|
|
8009f28: d035 beq.n 8009f96 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
8009f2a: 687b ldr r3, [r7, #4]
|
|
8009f2c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8009f2e: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8009f32: 693a ldr r2, [r7, #16]
|
|
8009f34: 429a cmp r2, r3
|
|
8009f36: d02e beq.n 8009f96 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8009f38: 4b20 ldr r3, [pc, #128] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f3a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f3c: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
8009f40: 613b str r3, [r7, #16]
|
|
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8009f42: 4b1e ldr r3, [pc, #120] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f44: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f46: 4a1d ldr r2, [pc, #116] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f48: f443 3380 orr.w r3, r3, #65536 ; 0x10000
|
|
8009f4c: 6713 str r3, [r2, #112] ; 0x70
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8009f4e: 4b1b ldr r3, [pc, #108] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f50: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f52: 4a1a ldr r2, [pc, #104] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f54: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
8009f58: 6713 str r3, [r2, #112] ; 0x70
|
|
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg0;
|
|
8009f5a: 4a18 ldr r2, [pc, #96] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f5c: 693b ldr r3, [r7, #16]
|
|
8009f5e: 6713 str r3, [r2, #112] ; 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
8009f60: 4b16 ldr r3, [pc, #88] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f62: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f64: f003 0301 and.w r3, r3, #1
|
|
8009f68: 2b01 cmp r3, #1
|
|
8009f6a: d114 bne.n 8009f96 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8009f6c: f7fb f9b8 bl 80052e0 <HAL_GetTick>
|
|
8009f70: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8009f72: e00a b.n 8009f8a <HAL_RCCEx_PeriphCLKConfig+0x19e>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
8009f74: f7fb f9b4 bl 80052e0 <HAL_GetTick>
|
|
8009f78: 4602 mov r2, r0
|
|
8009f7a: 697b ldr r3, [r7, #20]
|
|
8009f7c: 1ad3 subs r3, r2, r3
|
|
8009f7e: f241 3288 movw r2, #5000 ; 0x1388
|
|
8009f82: 4293 cmp r3, r2
|
|
8009f84: d901 bls.n 8009f8a <HAL_RCCEx_PeriphCLKConfig+0x19e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8009f86: 2303 movs r3, #3
|
|
8009f88: e317 b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8009f8a: 4b0c ldr r3, [pc, #48] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009f8c: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8009f8e: f003 0302 and.w r3, r3, #2
|
|
8009f92: 2b00 cmp r3, #0
|
|
8009f94: d0ee beq.n 8009f74 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8009f96: 687b ldr r3, [r7, #4]
|
|
8009f98: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8009f9a: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
8009f9e: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
8009fa2: d111 bne.n 8009fc8 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
|
|
8009fa4: 4b05 ldr r3, [pc, #20] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009fa6: 689b ldr r3, [r3, #8]
|
|
8009fa8: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
|
|
8009fac: 687b ldr r3, [r7, #4]
|
|
8009fae: 6b19 ldr r1, [r3, #48] ; 0x30
|
|
8009fb0: 4b04 ldr r3, [pc, #16] ; (8009fc4 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
|
|
8009fb2: 400b ands r3, r1
|
|
8009fb4: 4901 ldr r1, [pc, #4] ; (8009fbc <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
|
|
8009fb6: 4313 orrs r3, r2
|
|
8009fb8: 608b str r3, [r1, #8]
|
|
8009fba: e00b b.n 8009fd4 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
|
|
8009fbc: 40023800 .word 0x40023800
|
|
8009fc0: 40007000 .word 0x40007000
|
|
8009fc4: 0ffffcff .word 0x0ffffcff
|
|
8009fc8: 4bb0 ldr r3, [pc, #704] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009fca: 689b ldr r3, [r3, #8]
|
|
8009fcc: 4aaf ldr r2, [pc, #700] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009fce: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
|
|
8009fd2: 6093 str r3, [r2, #8]
|
|
8009fd4: 4bad ldr r3, [pc, #692] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009fd6: 6f1a ldr r2, [r3, #112] ; 0x70
|
|
8009fd8: 687b ldr r3, [r7, #4]
|
|
8009fda: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
8009fdc: f3c3 030b ubfx r3, r3, #0, #12
|
|
8009fe0: 49aa ldr r1, [pc, #680] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009fe2: 4313 orrs r3, r2
|
|
8009fe4: 670b str r3, [r1, #112] ; 0x70
|
|
}
|
|
|
|
/*------------------------------------ TIM configuration --------------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
8009fe6: 687b ldr r3, [r7, #4]
|
|
8009fe8: 681b ldr r3, [r3, #0]
|
|
8009fea: f003 0310 and.w r3, r3, #16
|
|
8009fee: 2b00 cmp r3, #0
|
|
8009ff0: d010 beq.n 800a014 <HAL_RCCEx_PeriphCLKConfig+0x228>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
|
|
|
|
/* Configure Timer Prescaler */
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
8009ff2: 4ba6 ldr r3, [pc, #664] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009ff4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
8009ff8: 4aa4 ldr r2, [pc, #656] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
8009ffa: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
|
|
8009ffe: f8c2 308c str.w r3, [r2, #140] ; 0x8c
|
|
800a002: 4ba2 ldr r3, [pc, #648] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a004: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
|
|
800a008: 687b ldr r3, [r7, #4]
|
|
800a00a: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800a00c: 499f ldr r1, [pc, #636] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a00e: 4313 orrs r3, r2
|
|
800a010: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
}
|
|
|
|
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
800a014: 687b ldr r3, [r7, #4]
|
|
800a016: 681b ldr r3, [r3, #0]
|
|
800a018: f403 4380 and.w r3, r3, #16384 ; 0x4000
|
|
800a01c: 2b00 cmp r3, #0
|
|
800a01e: d00a beq.n 800a036 <HAL_RCCEx_PeriphCLKConfig+0x24a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
800a020: 4b9a ldr r3, [pc, #616] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a022: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a026: f423 3240 bic.w r2, r3, #196608 ; 0x30000
|
|
800a02a: 687b ldr r3, [r7, #4]
|
|
800a02c: 6e5b ldr r3, [r3, #100] ; 0x64
|
|
800a02e: 4997 ldr r1, [pc, #604] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a030: 4313 orrs r3, r2
|
|
800a032: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
800a036: 687b ldr r3, [r7, #4]
|
|
800a038: 681b ldr r3, [r3, #0]
|
|
800a03a: f403 4300 and.w r3, r3, #32768 ; 0x8000
|
|
800a03e: 2b00 cmp r3, #0
|
|
800a040: d00a beq.n 800a058 <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
800a042: 4b92 ldr r3, [pc, #584] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a044: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a048: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
|
|
800a04c: 687b ldr r3, [r7, #4]
|
|
800a04e: 6e9b ldr r3, [r3, #104] ; 0x68
|
|
800a050: 498e ldr r1, [pc, #568] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a052: 4313 orrs r3, r2
|
|
800a054: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
800a058: 687b ldr r3, [r7, #4]
|
|
800a05a: 681b ldr r3, [r3, #0]
|
|
800a05c: f403 3380 and.w r3, r3, #65536 ; 0x10000
|
|
800a060: 2b00 cmp r3, #0
|
|
800a062: d00a beq.n 800a07a <HAL_RCCEx_PeriphCLKConfig+0x28e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
800a064: 4b89 ldr r3, [pc, #548] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a066: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a06a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
|
|
800a06e: 687b ldr r3, [r7, #4]
|
|
800a070: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
800a072: 4986 ldr r1, [pc, #536] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a074: 4313 orrs r3, r2
|
|
800a076: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
|
|
800a07a: 687b ldr r3, [r7, #4]
|
|
800a07c: 681b ldr r3, [r3, #0]
|
|
800a07e: f403 3300 and.w r3, r3, #131072 ; 0x20000
|
|
800a082: 2b00 cmp r3, #0
|
|
800a084: d00a beq.n 800a09c <HAL_RCCEx_PeriphCLKConfig+0x2b0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
|
|
|
|
/* Configure the I2C4 clock source */
|
|
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
|
|
800a086: 4b81 ldr r3, [pc, #516] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a088: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a08c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
|
|
800a090: 687b ldr r3, [r7, #4]
|
|
800a092: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
800a094: 497d ldr r1, [pc, #500] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a096: 4313 orrs r3, r2
|
|
800a098: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- USART1 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
800a09c: 687b ldr r3, [r7, #4]
|
|
800a09e: 681b ldr r3, [r3, #0]
|
|
800a0a0: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a0a4: 2b00 cmp r3, #0
|
|
800a0a6: d00a beq.n 800a0be <HAL_RCCEx_PeriphCLKConfig+0x2d2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
800a0a8: 4b78 ldr r3, [pc, #480] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0aa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a0ae: f023 0203 bic.w r2, r3, #3
|
|
800a0b2: 687b ldr r3, [r7, #4]
|
|
800a0b4: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800a0b6: 4975 ldr r1, [pc, #468] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0b8: 4313 orrs r3, r2
|
|
800a0ba: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- USART2 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
800a0be: 687b ldr r3, [r7, #4]
|
|
800a0c0: 681b ldr r3, [r3, #0]
|
|
800a0c2: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800a0c6: 2b00 cmp r3, #0
|
|
800a0c8: d00a beq.n 800a0e0 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
800a0ca: 4b70 ldr r3, [pc, #448] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0cc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a0d0: f023 020c bic.w r2, r3, #12
|
|
800a0d4: 687b ldr r3, [r7, #4]
|
|
800a0d6: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800a0d8: 496c ldr r1, [pc, #432] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0da: 4313 orrs r3, r2
|
|
800a0dc: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- USART3 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
800a0e0: 687b ldr r3, [r7, #4]
|
|
800a0e2: 681b ldr r3, [r3, #0]
|
|
800a0e4: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
800a0e8: 2b00 cmp r3, #0
|
|
800a0ea: d00a beq.n 800a102 <HAL_RCCEx_PeriphCLKConfig+0x316>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
800a0ec: 4b67 ldr r3, [pc, #412] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0ee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a0f2: f023 0230 bic.w r2, r3, #48 ; 0x30
|
|
800a0f6: 687b ldr r3, [r7, #4]
|
|
800a0f8: 6cdb ldr r3, [r3, #76] ; 0x4c
|
|
800a0fa: 4964 ldr r1, [pc, #400] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a0fc: 4313 orrs r3, r2
|
|
800a0fe: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- UART4 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
800a102: 687b ldr r3, [r7, #4]
|
|
800a104: 681b ldr r3, [r3, #0]
|
|
800a106: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
800a10a: 2b00 cmp r3, #0
|
|
800a10c: d00a beq.n 800a124 <HAL_RCCEx_PeriphCLKConfig+0x338>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
800a10e: 4b5f ldr r3, [pc, #380] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a110: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a114: f023 02c0 bic.w r2, r3, #192 ; 0xc0
|
|
800a118: 687b ldr r3, [r7, #4]
|
|
800a11a: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
800a11c: 495b ldr r1, [pc, #364] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a11e: 4313 orrs r3, r2
|
|
800a120: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- UART5 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
800a124: 687b ldr r3, [r7, #4]
|
|
800a126: 681b ldr r3, [r3, #0]
|
|
800a128: f403 6380 and.w r3, r3, #1024 ; 0x400
|
|
800a12c: 2b00 cmp r3, #0
|
|
800a12e: d00a beq.n 800a146 <HAL_RCCEx_PeriphCLKConfig+0x35a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
800a130: 4b56 ldr r3, [pc, #344] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a132: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a136: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
800a13a: 687b ldr r3, [r7, #4]
|
|
800a13c: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800a13e: 4953 ldr r1, [pc, #332] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a140: 4313 orrs r3, r2
|
|
800a142: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- USART6 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
|
|
800a146: 687b ldr r3, [r7, #4]
|
|
800a148: 681b ldr r3, [r3, #0]
|
|
800a14a: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
800a14e: 2b00 cmp r3, #0
|
|
800a150: d00a beq.n 800a168 <HAL_RCCEx_PeriphCLKConfig+0x37c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
|
|
|
|
/* Configure the USART6 clock source */
|
|
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
|
|
800a152: 4b4e ldr r3, [pc, #312] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a154: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a158: f423 6240 bic.w r2, r3, #3072 ; 0xc00
|
|
800a15c: 687b ldr r3, [r7, #4]
|
|
800a15e: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
800a160: 494a ldr r1, [pc, #296] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a162: 4313 orrs r3, r2
|
|
800a164: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- UART7 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
|
|
800a168: 687b ldr r3, [r7, #4]
|
|
800a16a: 681b ldr r3, [r3, #0]
|
|
800a16c: f403 5380 and.w r3, r3, #4096 ; 0x1000
|
|
800a170: 2b00 cmp r3, #0
|
|
800a172: d00a beq.n 800a18a <HAL_RCCEx_PeriphCLKConfig+0x39e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
|
|
|
|
/* Configure the UART7 clock source */
|
|
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
|
|
800a174: 4b45 ldr r3, [pc, #276] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a176: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a17a: f423 5240 bic.w r2, r3, #12288 ; 0x3000
|
|
800a17e: 687b ldr r3, [r7, #4]
|
|
800a180: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
800a182: 4942 ldr r1, [pc, #264] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a184: 4313 orrs r3, r2
|
|
800a186: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- UART8 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
|
|
800a18a: 687b ldr r3, [r7, #4]
|
|
800a18c: 681b ldr r3, [r3, #0]
|
|
800a18e: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
|
800a192: 2b00 cmp r3, #0
|
|
800a194: d00a beq.n 800a1ac <HAL_RCCEx_PeriphCLKConfig+0x3c0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
|
|
|
|
/* Configure the UART8 clock source */
|
|
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
|
|
800a196: 4b3d ldr r3, [pc, #244] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a198: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a19c: f423 4240 bic.w r2, r3, #49152 ; 0xc000
|
|
800a1a0: 687b ldr r3, [r7, #4]
|
|
800a1a2: 6e1b ldr r3, [r3, #96] ; 0x60
|
|
800a1a4: 4939 ldr r1, [pc, #228] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a1a6: 4313 orrs r3, r2
|
|
800a1a8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*--------------------------------------- CEC Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
|
|
800a1ac: 687b ldr r3, [r7, #4]
|
|
800a1ae: 681b ldr r3, [r3, #0]
|
|
800a1b0: f403 0380 and.w r3, r3, #4194304 ; 0x400000
|
|
800a1b4: 2b00 cmp r3, #0
|
|
800a1b6: d00a beq.n 800a1ce <HAL_RCCEx_PeriphCLKConfig+0x3e2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
|
|
|
|
/* Configure the CEC clock source */
|
|
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
|
|
800a1b8: 4b34 ldr r3, [pc, #208] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a1ba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a1be: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
|
|
800a1c2: 687b ldr r3, [r7, #4]
|
|
800a1c4: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
800a1c6: 4931 ldr r1, [pc, #196] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a1c8: 4313 orrs r3, r2
|
|
800a1ca: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*-------------------------------------- CK48 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
|
|
800a1ce: 687b ldr r3, [r7, #4]
|
|
800a1d0: 681b ldr r3, [r3, #0]
|
|
800a1d2: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
800a1d6: 2b00 cmp r3, #0
|
|
800a1d8: d011 beq.n 800a1fe <HAL_RCCEx_PeriphCLKConfig+0x412>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
|
|
|
|
/* Configure the CLK48 source */
|
|
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
|
|
800a1da: 4b2c ldr r3, [pc, #176] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a1dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a1e0: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
|
|
800a1e4: 687b ldr r3, [r7, #4]
|
|
800a1e6: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
800a1e8: 4928 ldr r1, [pc, #160] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a1ea: 4313 orrs r3, r2
|
|
800a1ec: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
|
|
/* Enable the PLLSAI when it's used as clock source for CK48 */
|
|
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
|
|
800a1f0: 687b ldr r3, [r7, #4]
|
|
800a1f2: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
800a1f4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
800a1f8: d101 bne.n 800a1fe <HAL_RCCEx_PeriphCLKConfig+0x412>
|
|
{
|
|
pllsaiused = 1;
|
|
800a1fa: 2301 movs r3, #1
|
|
800a1fc: 61bb str r3, [r7, #24]
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------- LTDC Configuration -----------------------------------*/
|
|
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
|
|
800a1fe: 687b ldr r3, [r7, #4]
|
|
800a200: 681b ldr r3, [r3, #0]
|
|
800a202: f003 0308 and.w r3, r3, #8
|
|
800a206: 2b00 cmp r3, #0
|
|
800a208: d001 beq.n 800a20e <HAL_RCCEx_PeriphCLKConfig+0x422>
|
|
{
|
|
pllsaiused = 1;
|
|
800a20a: 2301 movs r3, #1
|
|
800a20c: 61bb str r3, [r7, #24]
|
|
}
|
|
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
|
|
|
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
|
|
800a20e: 687b ldr r3, [r7, #4]
|
|
800a210: 681b ldr r3, [r3, #0]
|
|
800a212: f403 2380 and.w r3, r3, #262144 ; 0x40000
|
|
800a216: 2b00 cmp r3, #0
|
|
800a218: d00a beq.n 800a230 <HAL_RCCEx_PeriphCLKConfig+0x444>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
|
|
/* Configure the LTPIM1 clock source */
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
800a21a: 4b1c ldr r3, [pc, #112] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a21c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a220: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
|
|
800a224: 687b ldr r3, [r7, #4]
|
|
800a226: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
800a228: 4918 ldr r1, [pc, #96] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a22a: 4313 orrs r3, r2
|
|
800a22c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
|
|
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
|
|
800a230: 687b ldr r3, [r7, #4]
|
|
800a232: 681b ldr r3, [r3, #0]
|
|
800a234: f403 0300 and.w r3, r3, #8388608 ; 0x800000
|
|
800a238: 2b00 cmp r3, #0
|
|
800a23a: d00b beq.n 800a254 <HAL_RCCEx_PeriphCLKConfig+0x468>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
|
|
/* Configure the SDMMC1 clock source */
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
800a23c: 4b13 ldr r3, [pc, #76] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a23e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800a242: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
|
|
800a246: 687b ldr r3, [r7, #4]
|
|
800a248: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
800a24c: 490f ldr r1, [pc, #60] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a24e: 4313 orrs r3, r2
|
|
800a250: f8c1 3090 str.w r3, [r1, #144] ; 0x90
|
|
}
|
|
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
|
|
|
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
|
|
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
|
|
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
|
|
800a254: 69fb ldr r3, [r7, #28]
|
|
800a256: 2b01 cmp r3, #1
|
|
800a258: d005 beq.n 800a266 <HAL_RCCEx_PeriphCLKConfig+0x47a>
|
|
800a25a: 687b ldr r3, [r7, #4]
|
|
800a25c: 681b ldr r3, [r3, #0]
|
|
800a25e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
|
|
800a262: f040 80d8 bne.w 800a416 <HAL_RCCEx_PeriphCLKConfig+0x62a>
|
|
{
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
800a266: 4b09 ldr r3, [pc, #36] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a268: 681b ldr r3, [r3, #0]
|
|
800a26a: 4a08 ldr r2, [pc, #32] ; (800a28c <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
|
|
800a26c: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
|
|
800a270: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800a272: f7fb f835 bl 80052e0 <HAL_GetTick>
|
|
800a276: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLLI2S is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
800a278: e00a b.n 800a290 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
800a27a: f7fb f831 bl 80052e0 <HAL_GetTick>
|
|
800a27e: 4602 mov r2, r0
|
|
800a280: 697b ldr r3, [r7, #20]
|
|
800a282: 1ad3 subs r3, r2, r3
|
|
800a284: 2b64 cmp r3, #100 ; 0x64
|
|
800a286: d903 bls.n 800a290 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800a288: 2303 movs r3, #3
|
|
800a28a: e196 b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
800a28c: 40023800 .word 0x40023800
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
800a290: 4b6c ldr r3, [pc, #432] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a292: 681b ldr r3, [r3, #0]
|
|
800a294: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
800a298: 2b00 cmp r3, #0
|
|
800a29a: d1ee bne.n 800a27a <HAL_RCCEx_PeriphCLKConfig+0x48e>
|
|
|
|
/* check for common PLLI2S Parameters */
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
|
|
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
|
|
800a29c: 687b ldr r3, [r7, #4]
|
|
800a29e: 681b ldr r3, [r3, #0]
|
|
800a2a0: f003 0301 and.w r3, r3, #1
|
|
800a2a4: 2b00 cmp r3, #0
|
|
800a2a6: d021 beq.n 800a2ec <HAL_RCCEx_PeriphCLKConfig+0x500>
|
|
800a2a8: 687b ldr r3, [r7, #4]
|
|
800a2aa: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
800a2ac: 2b00 cmp r3, #0
|
|
800a2ae: d11d bne.n 800a2ec <HAL_RCCEx_PeriphCLKConfig+0x500>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
|
|
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
|
|
800a2b0: 4b64 ldr r3, [pc, #400] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a2b2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a2b6: 0c1b lsrs r3, r3, #16
|
|
800a2b8: f003 0303 and.w r3, r3, #3
|
|
800a2bc: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
800a2be: 4b61 ldr r3, [pc, #388] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a2c0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a2c4: 0e1b lsrs r3, r3, #24
|
|
800a2c6: f003 030f and.w r3, r3, #15
|
|
800a2ca: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
800a2cc: 687b ldr r3, [r7, #4]
|
|
800a2ce: 685b ldr r3, [r3, #4]
|
|
800a2d0: 019a lsls r2, r3, #6
|
|
800a2d2: 693b ldr r3, [r7, #16]
|
|
800a2d4: 041b lsls r3, r3, #16
|
|
800a2d6: 431a orrs r2, r3
|
|
800a2d8: 68fb ldr r3, [r7, #12]
|
|
800a2da: 061b lsls r3, r3, #24
|
|
800a2dc: 431a orrs r2, r3
|
|
800a2de: 687b ldr r3, [r7, #4]
|
|
800a2e0: 689b ldr r3, [r3, #8]
|
|
800a2e2: 071b lsls r3, r3, #28
|
|
800a2e4: 4957 ldr r1, [pc, #348] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a2e6: 4313 orrs r3, r2
|
|
800a2e8: f8c1 3084 str.w r3, [r1, #132] ; 0x84
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
|
|
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
800a2ec: 687b ldr r3, [r7, #4]
|
|
800a2ee: 681b ldr r3, [r3, #0]
|
|
800a2f0: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
|
800a2f4: 2b00 cmp r3, #0
|
|
800a2f6: d004 beq.n 800a302 <HAL_RCCEx_PeriphCLKConfig+0x516>
|
|
800a2f8: 687b ldr r3, [r7, #4]
|
|
800a2fa: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800a2fc: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
800a300: d00a beq.n 800a318 <HAL_RCCEx_PeriphCLKConfig+0x52c>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
800a302: 687b ldr r3, [r7, #4]
|
|
800a304: 681b ldr r3, [r3, #0]
|
|
800a306: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
|
|
800a30a: 2b00 cmp r3, #0
|
|
800a30c: d02e beq.n 800a36c <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
|
|
800a30e: 687b ldr r3, [r7, #4]
|
|
800a310: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800a312: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
|
|
800a316: d129 bne.n 800a36c <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
/* Check for PLLI2S/DIVQ parameters */
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
|
|
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
|
|
800a318: 4b4a ldr r3, [pc, #296] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a31a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a31e: 0c1b lsrs r3, r3, #16
|
|
800a320: f003 0303 and.w r3, r3, #3
|
|
800a324: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
800a326: 4b47 ldr r3, [pc, #284] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a328: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a32c: 0f1b lsrs r3, r3, #28
|
|
800a32e: f003 0307 and.w r3, r3, #7
|
|
800a332: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
|
|
800a334: 687b ldr r3, [r7, #4]
|
|
800a336: 685b ldr r3, [r3, #4]
|
|
800a338: 019a lsls r2, r3, #6
|
|
800a33a: 693b ldr r3, [r7, #16]
|
|
800a33c: 041b lsls r3, r3, #16
|
|
800a33e: 431a orrs r2, r3
|
|
800a340: 687b ldr r3, [r7, #4]
|
|
800a342: 68db ldr r3, [r3, #12]
|
|
800a344: 061b lsls r3, r3, #24
|
|
800a346: 431a orrs r2, r3
|
|
800a348: 68fb ldr r3, [r7, #12]
|
|
800a34a: 071b lsls r3, r3, #28
|
|
800a34c: 493d ldr r1, [pc, #244] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a34e: 4313 orrs r3, r2
|
|
800a350: f8c1 3084 str.w r3, [r1, #132] ; 0x84
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
800a354: 4b3b ldr r3, [pc, #236] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a356: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
800a35a: f023 021f bic.w r2, r3, #31
|
|
800a35e: 687b ldr r3, [r7, #4]
|
|
800a360: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800a362: 3b01 subs r3, #1
|
|
800a364: 4937 ldr r1, [pc, #220] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a366: 4313 orrs r3, r2
|
|
800a368: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
|
|
800a36c: 687b ldr r3, [r7, #4]
|
|
800a36e: 681b ldr r3, [r3, #0]
|
|
800a370: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
|
|
800a374: 2b00 cmp r3, #0
|
|
800a376: d01d beq.n 800a3b4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
|
|
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
|
|
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
|
|
800a378: 4b32 ldr r3, [pc, #200] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a37a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a37e: 0e1b lsrs r3, r3, #24
|
|
800a380: f003 030f and.w r3, r3, #15
|
|
800a384: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
800a386: 4b2f ldr r3, [pc, #188] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a388: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
800a38c: 0f1b lsrs r3, r3, #28
|
|
800a38e: f003 0307 and.w r3, r3, #7
|
|
800a392: 60fb str r3, [r7, #12]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
|
|
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
|
|
800a394: 687b ldr r3, [r7, #4]
|
|
800a396: 685b ldr r3, [r3, #4]
|
|
800a398: 019a lsls r2, r3, #6
|
|
800a39a: 687b ldr r3, [r7, #4]
|
|
800a39c: 691b ldr r3, [r3, #16]
|
|
800a39e: 041b lsls r3, r3, #16
|
|
800a3a0: 431a orrs r2, r3
|
|
800a3a2: 693b ldr r3, [r7, #16]
|
|
800a3a4: 061b lsls r3, r3, #24
|
|
800a3a6: 431a orrs r2, r3
|
|
800a3a8: 68fb ldr r3, [r7, #12]
|
|
800a3aa: 071b lsls r3, r3, #28
|
|
800a3ac: 4925 ldr r1, [pc, #148] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a3ae: 4313 orrs r3, r2
|
|
800a3b0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
800a3b4: 687b ldr r3, [r7, #4]
|
|
800a3b6: 681b ldr r3, [r3, #0]
|
|
800a3b8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
800a3bc: 2b00 cmp r3, #0
|
|
800a3be: d011 beq.n 800a3e4 <HAL_RCCEx_PeriphCLKConfig+0x5f8>
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
|
|
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
800a3c0: 687b ldr r3, [r7, #4]
|
|
800a3c2: 685b ldr r3, [r3, #4]
|
|
800a3c4: 019a lsls r2, r3, #6
|
|
800a3c6: 687b ldr r3, [r7, #4]
|
|
800a3c8: 691b ldr r3, [r3, #16]
|
|
800a3ca: 041b lsls r3, r3, #16
|
|
800a3cc: 431a orrs r2, r3
|
|
800a3ce: 687b ldr r3, [r7, #4]
|
|
800a3d0: 68db ldr r3, [r3, #12]
|
|
800a3d2: 061b lsls r3, r3, #24
|
|
800a3d4: 431a orrs r2, r3
|
|
800a3d6: 687b ldr r3, [r7, #4]
|
|
800a3d8: 689b ldr r3, [r3, #8]
|
|
800a3da: 071b lsls r3, r3, #28
|
|
800a3dc: 4919 ldr r1, [pc, #100] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a3de: 4313 orrs r3, r2
|
|
800a3e0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
800a3e4: 4b17 ldr r3, [pc, #92] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a3e6: 681b ldr r3, [r3, #0]
|
|
800a3e8: 4a16 ldr r2, [pc, #88] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a3ea: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
800a3ee: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800a3f0: f7fa ff76 bl 80052e0 <HAL_GetTick>
|
|
800a3f4: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLLI2S is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
800a3f6: e008 b.n 800a40a <HAL_RCCEx_PeriphCLKConfig+0x61e>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
800a3f8: f7fa ff72 bl 80052e0 <HAL_GetTick>
|
|
800a3fc: 4602 mov r2, r0
|
|
800a3fe: 697b ldr r3, [r7, #20]
|
|
800a400: 1ad3 subs r3, r2, r3
|
|
800a402: 2b64 cmp r3, #100 ; 0x64
|
|
800a404: d901 bls.n 800a40a <HAL_RCCEx_PeriphCLKConfig+0x61e>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800a406: 2303 movs r3, #3
|
|
800a408: e0d7 b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
800a40a: 4b0e ldr r3, [pc, #56] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a40c: 681b ldr r3, [r3, #0]
|
|
800a40e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
800a412: 2b00 cmp r3, #0
|
|
800a414: d0f0 beq.n 800a3f8 <HAL_RCCEx_PeriphCLKConfig+0x60c>
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
|
|
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
|
|
if(pllsaiused == 1)
|
|
800a416: 69bb ldr r3, [r7, #24]
|
|
800a418: 2b01 cmp r3, #1
|
|
800a41a: f040 80cd bne.w 800a5b8 <HAL_RCCEx_PeriphCLKConfig+0x7cc>
|
|
{
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
800a41e: 4b09 ldr r3, [pc, #36] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a420: 681b ldr r3, [r3, #0]
|
|
800a422: 4a08 ldr r2, [pc, #32] ; (800a444 <HAL_RCCEx_PeriphCLKConfig+0x658>)
|
|
800a424: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
|
|
800a428: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800a42a: f7fa ff59 bl 80052e0 <HAL_GetTick>
|
|
800a42e: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLLSAI is disabled */
|
|
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
800a430: e00a b.n 800a448 <HAL_RCCEx_PeriphCLKConfig+0x65c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
800a432: f7fa ff55 bl 80052e0 <HAL_GetTick>
|
|
800a436: 4602 mov r2, r0
|
|
800a438: 697b ldr r3, [r7, #20]
|
|
800a43a: 1ad3 subs r3, r2, r3
|
|
800a43c: 2b64 cmp r3, #100 ; 0x64
|
|
800a43e: d903 bls.n 800a448 <HAL_RCCEx_PeriphCLKConfig+0x65c>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800a440: 2303 movs r3, #3
|
|
800a442: e0ba b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
800a444: 40023800 .word 0x40023800
|
|
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
800a448: 4b5e ldr r3, [pc, #376] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a44a: 681b ldr r3, [r3, #0]
|
|
800a44c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
800a450: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
800a454: d0ed beq.n 800a432 <HAL_RCCEx_PeriphCLKConfig+0x646>
|
|
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
|
|
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
|
|
800a456: 687b ldr r3, [r7, #4]
|
|
800a458: 681b ldr r3, [r3, #0]
|
|
800a45a: f403 2300 and.w r3, r3, #524288 ; 0x80000
|
|
800a45e: 2b00 cmp r3, #0
|
|
800a460: d003 beq.n 800a46a <HAL_RCCEx_PeriphCLKConfig+0x67e>
|
|
800a462: 687b ldr r3, [r7, #4]
|
|
800a464: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800a466: 2b00 cmp r3, #0
|
|
800a468: d009 beq.n 800a47e <HAL_RCCEx_PeriphCLKConfig+0x692>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
800a46a: 687b ldr r3, [r7, #4]
|
|
800a46c: 681b ldr r3, [r3, #0]
|
|
800a46e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
|
|
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
|
|
800a472: 2b00 cmp r3, #0
|
|
800a474: d02e beq.n 800a4d4 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
|
|
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
|
|
800a476: 687b ldr r3, [r7, #4]
|
|
800a478: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800a47a: 2b00 cmp r3, #0
|
|
800a47c: d12a bne.n 800a4d4 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
/* check for PLLSAI/DIVQ Parameter */
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
|
|
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
|
|
800a47e: 4b51 ldr r3, [pc, #324] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a480: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a484: 0c1b lsrs r3, r3, #16
|
|
800a486: f003 0303 and.w r3, r3, #3
|
|
800a48a: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
|
|
800a48c: 4b4d ldr r3, [pc, #308] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a48e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a492: 0f1b lsrs r3, r3, #28
|
|
800a494: f003 0307 and.w r3, r3, #7
|
|
800a498: 60fb str r3, [r7, #12]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
|
|
800a49a: 687b ldr r3, [r7, #4]
|
|
800a49c: 695b ldr r3, [r3, #20]
|
|
800a49e: 019a lsls r2, r3, #6
|
|
800a4a0: 693b ldr r3, [r7, #16]
|
|
800a4a2: 041b lsls r3, r3, #16
|
|
800a4a4: 431a orrs r2, r3
|
|
800a4a6: 687b ldr r3, [r7, #4]
|
|
800a4a8: 699b ldr r3, [r3, #24]
|
|
800a4aa: 061b lsls r3, r3, #24
|
|
800a4ac: 431a orrs r2, r3
|
|
800a4ae: 68fb ldr r3, [r7, #12]
|
|
800a4b0: 071b lsls r3, r3, #28
|
|
800a4b2: 4944 ldr r1, [pc, #272] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a4b4: 4313 orrs r3, r2
|
|
800a4b6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
800a4ba: 4b42 ldr r3, [pc, #264] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a4bc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
800a4c0: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
|
|
800a4c4: 687b ldr r3, [r7, #4]
|
|
800a4c6: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800a4c8: 3b01 subs r3, #1
|
|
800a4ca: 021b lsls r3, r3, #8
|
|
800a4cc: 493d ldr r1, [pc, #244] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a4ce: 4313 orrs r3, r2
|
|
800a4d0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
}
|
|
|
|
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
|
|
/* In Case of PLLI2S is selected as source clock for CK48 */
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
|
|
800a4d4: 687b ldr r3, [r7, #4]
|
|
800a4d6: 681b ldr r3, [r3, #0]
|
|
800a4d8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
|
|
800a4dc: 2b00 cmp r3, #0
|
|
800a4de: d022 beq.n 800a526 <HAL_RCCEx_PeriphCLKConfig+0x73a>
|
|
800a4e0: 687b ldr r3, [r7, #4]
|
|
800a4e2: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
800a4e4: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
|
|
800a4e8: d11d bne.n 800a526 <HAL_RCCEx_PeriphCLKConfig+0x73a>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
|
|
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
|
|
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
800a4ea: 4b36 ldr r3, [pc, #216] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a4ec: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a4f0: 0e1b lsrs r3, r3, #24
|
|
800a4f2: f003 030f and.w r3, r3, #15
|
|
800a4f6: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
|
|
800a4f8: 4b32 ldr r3, [pc, #200] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a4fa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a4fe: 0f1b lsrs r3, r3, #28
|
|
800a500: f003 0307 and.w r3, r3, #7
|
|
800a504: 60fb str r3, [r7, #12]
|
|
|
|
/* Configure the PLLSAI division factors */
|
|
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
|
|
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
|
|
800a506: 687b ldr r3, [r7, #4]
|
|
800a508: 695b ldr r3, [r3, #20]
|
|
800a50a: 019a lsls r2, r3, #6
|
|
800a50c: 687b ldr r3, [r7, #4]
|
|
800a50e: 6a1b ldr r3, [r3, #32]
|
|
800a510: 041b lsls r3, r3, #16
|
|
800a512: 431a orrs r2, r3
|
|
800a514: 693b ldr r3, [r7, #16]
|
|
800a516: 061b lsls r3, r3, #24
|
|
800a518: 431a orrs r2, r3
|
|
800a51a: 68fb ldr r3, [r7, #12]
|
|
800a51c: 071b lsls r3, r3, #28
|
|
800a51e: 4929 ldr r1, [pc, #164] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a520: 4313 orrs r3, r2
|
|
800a522: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
}
|
|
|
|
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
|
/*---------------------------- LTDC configuration -------------------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
|
|
800a526: 687b ldr r3, [r7, #4]
|
|
800a528: 681b ldr r3, [r3, #0]
|
|
800a52a: f003 0308 and.w r3, r3, #8
|
|
800a52e: 2b00 cmp r3, #0
|
|
800a530: d028 beq.n 800a584 <HAL_RCCEx_PeriphCLKConfig+0x798>
|
|
{
|
|
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
|
|
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
|
|
|
|
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
|
|
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
800a532: 4b24 ldr r3, [pc, #144] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a534: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a538: 0e1b lsrs r3, r3, #24
|
|
800a53a: f003 030f and.w r3, r3, #15
|
|
800a53e: 613b str r3, [r7, #16]
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
|
|
800a540: 4b20 ldr r3, [pc, #128] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a542: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
800a546: 0c1b lsrs r3, r3, #16
|
|
800a548: f003 0303 and.w r3, r3, #3
|
|
800a54c: 60fb str r3, [r7, #12]
|
|
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
|
|
800a54e: 687b ldr r3, [r7, #4]
|
|
800a550: 695b ldr r3, [r3, #20]
|
|
800a552: 019a lsls r2, r3, #6
|
|
800a554: 68fb ldr r3, [r7, #12]
|
|
800a556: 041b lsls r3, r3, #16
|
|
800a558: 431a orrs r2, r3
|
|
800a55a: 693b ldr r3, [r7, #16]
|
|
800a55c: 061b lsls r3, r3, #24
|
|
800a55e: 431a orrs r2, r3
|
|
800a560: 687b ldr r3, [r7, #4]
|
|
800a562: 69db ldr r3, [r3, #28]
|
|
800a564: 071b lsls r3, r3, #28
|
|
800a566: 4917 ldr r1, [pc, #92] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a568: 4313 orrs r3, r2
|
|
800a56a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
|
|
|
|
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
|
|
800a56e: 4b15 ldr r3, [pc, #84] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a570: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
800a574: f423 3240 bic.w r2, r3, #196608 ; 0x30000
|
|
800a578: 687b ldr r3, [r7, #4]
|
|
800a57a: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800a57c: 4911 ldr r1, [pc, #68] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a57e: 4313 orrs r3, r2
|
|
800a580: f8c1 308c str.w r3, [r1, #140] ; 0x8c
|
|
}
|
|
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
|
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
800a584: 4b0f ldr r3, [pc, #60] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a586: 681b ldr r3, [r3, #0]
|
|
800a588: 4a0e ldr r2, [pc, #56] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a58a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
|
|
800a58e: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800a590: f7fa fea6 bl 80052e0 <HAL_GetTick>
|
|
800a594: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till PLLSAI is ready */
|
|
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800a596: e008 b.n 800a5aa <HAL_RCCEx_PeriphCLKConfig+0x7be>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
800a598: f7fa fea2 bl 80052e0 <HAL_GetTick>
|
|
800a59c: 4602 mov r2, r0
|
|
800a59e: 697b ldr r3, [r7, #20]
|
|
800a5a0: 1ad3 subs r3, r2, r3
|
|
800a5a2: 2b64 cmp r3, #100 ; 0x64
|
|
800a5a4: d901 bls.n 800a5aa <HAL_RCCEx_PeriphCLKConfig+0x7be>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800a5a6: 2303 movs r3, #3
|
|
800a5a8: e007 b.n 800a5ba <HAL_RCCEx_PeriphCLKConfig+0x7ce>
|
|
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800a5aa: 4b06 ldr r3, [pc, #24] ; (800a5c4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
|
|
800a5ac: 681b ldr r3, [r3, #0]
|
|
800a5ae: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
|
|
800a5b2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
|
|
800a5b6: d1ef bne.n 800a598 <HAL_RCCEx_PeriphCLKConfig+0x7ac>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800a5b8: 2300 movs r3, #0
|
|
}
|
|
800a5ba: 4618 mov r0, r3
|
|
800a5bc: 3720 adds r7, #32
|
|
800a5be: 46bd mov sp, r7
|
|
800a5c0: bd80 pop {r7, pc}
|
|
800a5c2: bf00 nop
|
|
800a5c4: 40023800 .word 0x40023800
|
|
|
|
0800a5c8 <HAL_RNG_Init>:
|
|
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
|
* the configuration information for RNG.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
|
{
|
|
800a5c8: b580 push {r7, lr}
|
|
800a5ca: b082 sub sp, #8
|
|
800a5cc: af00 add r7, sp, #0
|
|
800a5ce: 6078 str r0, [r7, #4]
|
|
/* Check the RNG handle allocation */
|
|
if (hrng == NULL)
|
|
800a5d0: 687b ldr r3, [r7, #4]
|
|
800a5d2: 2b00 cmp r3, #0
|
|
800a5d4: d101 bne.n 800a5da <HAL_RNG_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800a5d6: 2301 movs r3, #1
|
|
800a5d8: e01c b.n 800a614 <HAL_RNG_Init+0x4c>
|
|
|
|
/* Init the low level hardware */
|
|
hrng->MspInitCallback(hrng);
|
|
}
|
|
#else
|
|
if (hrng->State == HAL_RNG_STATE_RESET)
|
|
800a5da: 687b ldr r3, [r7, #4]
|
|
800a5dc: 795b ldrb r3, [r3, #5]
|
|
800a5de: b2db uxtb r3, r3
|
|
800a5e0: 2b00 cmp r3, #0
|
|
800a5e2: d105 bne.n 800a5f0 <HAL_RNG_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hrng->Lock = HAL_UNLOCKED;
|
|
800a5e4: 687b ldr r3, [r7, #4]
|
|
800a5e6: 2200 movs r2, #0
|
|
800a5e8: 711a strb r2, [r3, #4]
|
|
|
|
/* Init the low level hardware */
|
|
HAL_RNG_MspInit(hrng);
|
|
800a5ea: 6878 ldr r0, [r7, #4]
|
|
800a5ec: f7fa fa0a bl 8004a04 <HAL_RNG_MspInit>
|
|
}
|
|
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
|
|
|
/* Change RNG peripheral state */
|
|
hrng->State = HAL_RNG_STATE_BUSY;
|
|
800a5f0: 687b ldr r3, [r7, #4]
|
|
800a5f2: 2202 movs r2, #2
|
|
800a5f4: 715a strb r2, [r3, #5]
|
|
|
|
|
|
/* Enable the RNG Peripheral */
|
|
__HAL_RNG_ENABLE(hrng);
|
|
800a5f6: 687b ldr r3, [r7, #4]
|
|
800a5f8: 681b ldr r3, [r3, #0]
|
|
800a5fa: 681a ldr r2, [r3, #0]
|
|
800a5fc: 687b ldr r3, [r7, #4]
|
|
800a5fe: 681b ldr r3, [r3, #0]
|
|
800a600: f042 0204 orr.w r2, r2, #4
|
|
800a604: 601a str r2, [r3, #0]
|
|
|
|
/* Initialize the RNG state */
|
|
hrng->State = HAL_RNG_STATE_READY;
|
|
800a606: 687b ldr r3, [r7, #4]
|
|
800a608: 2201 movs r2, #1
|
|
800a60a: 715a strb r2, [r3, #5]
|
|
|
|
/* Initialise the error code */
|
|
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
|
|
800a60c: 687b ldr r3, [r7, #4]
|
|
800a60e: 2200 movs r2, #0
|
|
800a610: 609a str r2, [r3, #8]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800a612: 2300 movs r3, #0
|
|
}
|
|
800a614: 4618 mov r0, r3
|
|
800a616: 3708 adds r7, #8
|
|
800a618: 46bd mov sp, r7
|
|
800a61a: bd80 pop {r7, pc}
|
|
|
|
0800a61c <HAL_RTC_Init>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
|
|
{
|
|
800a61c: b580 push {r7, lr}
|
|
800a61e: b082 sub sp, #8
|
|
800a620: af00 add r7, sp, #0
|
|
800a622: 6078 str r0, [r7, #4]
|
|
/* Check the RTC peripheral state */
|
|
if(hrtc == NULL)
|
|
800a624: 687b ldr r3, [r7, #4]
|
|
800a626: 2b00 cmp r3, #0
|
|
800a628: d101 bne.n 800a62e <HAL_RTC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800a62a: 2301 movs r3, #1
|
|
800a62c: e06b b.n 800a706 <HAL_RTC_Init+0xea>
|
|
{
|
|
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
|
|
}
|
|
}
|
|
#else
|
|
if(hrtc->State == HAL_RTC_STATE_RESET)
|
|
800a62e: 687b ldr r3, [r7, #4]
|
|
800a630: 7f5b ldrb r3, [r3, #29]
|
|
800a632: b2db uxtb r3, r3
|
|
800a634: 2b00 cmp r3, #0
|
|
800a636: d105 bne.n 800a644 <HAL_RTC_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hrtc->Lock = HAL_UNLOCKED;
|
|
800a638: 687b ldr r3, [r7, #4]
|
|
800a63a: 2200 movs r2, #0
|
|
800a63c: 771a strb r2, [r3, #28]
|
|
|
|
/* Initialize RTC MSP */
|
|
HAL_RTC_MspInit(hrtc);
|
|
800a63e: 6878 ldr r0, [r7, #4]
|
|
800a640: f7fa fa00 bl 8004a44 <HAL_RTC_MspInit>
|
|
}
|
|
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800a644: 687b ldr r3, [r7, #4]
|
|
800a646: 2202 movs r2, #2
|
|
800a648: 775a strb r2, [r3, #29]
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800a64a: 687b ldr r3, [r7, #4]
|
|
800a64c: 681b ldr r3, [r3, #0]
|
|
800a64e: 22ca movs r2, #202 ; 0xca
|
|
800a650: 625a str r2, [r3, #36] ; 0x24
|
|
800a652: 687b ldr r3, [r7, #4]
|
|
800a654: 681b ldr r3, [r3, #0]
|
|
800a656: 2253 movs r2, #83 ; 0x53
|
|
800a658: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set Initialization mode */
|
|
if(RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
800a65a: 6878 ldr r0, [r7, #4]
|
|
800a65c: f000 fb00 bl 800ac60 <RTC_EnterInitMode>
|
|
800a660: 4603 mov r3, r0
|
|
800a662: 2b00 cmp r3, #0
|
|
800a664: d008 beq.n 800a678 <HAL_RTC_Init+0x5c>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a666: 687b ldr r3, [r7, #4]
|
|
800a668: 681b ldr r3, [r3, #0]
|
|
800a66a: 22ff movs r2, #255 ; 0xff
|
|
800a66c: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800a66e: 687b ldr r3, [r7, #4]
|
|
800a670: 2204 movs r2, #4
|
|
800a672: 775a strb r2, [r3, #29]
|
|
|
|
return HAL_ERROR;
|
|
800a674: 2301 movs r3, #1
|
|
800a676: e046 b.n 800a706 <HAL_RTC_Init+0xea>
|
|
}
|
|
else
|
|
{
|
|
/* Clear RTC_CR FMT, OSEL and POL Bits */
|
|
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
|
|
800a678: 687b ldr r3, [r7, #4]
|
|
800a67a: 681b ldr r3, [r3, #0]
|
|
800a67c: 6899 ldr r1, [r3, #8]
|
|
800a67e: 687b ldr r3, [r7, #4]
|
|
800a680: 681a ldr r2, [r3, #0]
|
|
800a682: 4b23 ldr r3, [pc, #140] ; (800a710 <HAL_RTC_Init+0xf4>)
|
|
800a684: 400b ands r3, r1
|
|
800a686: 6093 str r3, [r2, #8]
|
|
/* Set RTC_CR register */
|
|
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
|
|
800a688: 687b ldr r3, [r7, #4]
|
|
800a68a: 681b ldr r3, [r3, #0]
|
|
800a68c: 6899 ldr r1, [r3, #8]
|
|
800a68e: 687b ldr r3, [r7, #4]
|
|
800a690: 685a ldr r2, [r3, #4]
|
|
800a692: 687b ldr r3, [r7, #4]
|
|
800a694: 691b ldr r3, [r3, #16]
|
|
800a696: 431a orrs r2, r3
|
|
800a698: 687b ldr r3, [r7, #4]
|
|
800a69a: 695b ldr r3, [r3, #20]
|
|
800a69c: 431a orrs r2, r3
|
|
800a69e: 687b ldr r3, [r7, #4]
|
|
800a6a0: 681b ldr r3, [r3, #0]
|
|
800a6a2: 430a orrs r2, r1
|
|
800a6a4: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the RTC PRER */
|
|
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
|
|
800a6a6: 687b ldr r3, [r7, #4]
|
|
800a6a8: 681b ldr r3, [r3, #0]
|
|
800a6aa: 687a ldr r2, [r7, #4]
|
|
800a6ac: 68d2 ldr r2, [r2, #12]
|
|
800a6ae: 611a str r2, [r3, #16]
|
|
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
|
|
800a6b0: 687b ldr r3, [r7, #4]
|
|
800a6b2: 681b ldr r3, [r3, #0]
|
|
800a6b4: 6919 ldr r1, [r3, #16]
|
|
800a6b6: 687b ldr r3, [r7, #4]
|
|
800a6b8: 689b ldr r3, [r3, #8]
|
|
800a6ba: 041a lsls r2, r3, #16
|
|
800a6bc: 687b ldr r3, [r7, #4]
|
|
800a6be: 681b ldr r3, [r3, #0]
|
|
800a6c0: 430a orrs r2, r1
|
|
800a6c2: 611a str r2, [r3, #16]
|
|
|
|
/* Exit Initialization mode */
|
|
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
|
800a6c4: 687b ldr r3, [r7, #4]
|
|
800a6c6: 681b ldr r3, [r3, #0]
|
|
800a6c8: 68da ldr r2, [r3, #12]
|
|
800a6ca: 687b ldr r3, [r7, #4]
|
|
800a6cc: 681b ldr r3, [r3, #0]
|
|
800a6ce: f022 0280 bic.w r2, r2, #128 ; 0x80
|
|
800a6d2: 60da str r2, [r3, #12]
|
|
|
|
hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
|
|
800a6d4: 687b ldr r3, [r7, #4]
|
|
800a6d6: 681b ldr r3, [r3, #0]
|
|
800a6d8: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
800a6da: 687b ldr r3, [r7, #4]
|
|
800a6dc: 681b ldr r3, [r3, #0]
|
|
800a6de: f022 0208 bic.w r2, r2, #8
|
|
800a6e2: 64da str r2, [r3, #76] ; 0x4c
|
|
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
|
|
800a6e4: 687b ldr r3, [r7, #4]
|
|
800a6e6: 681b ldr r3, [r3, #0]
|
|
800a6e8: 6cd9 ldr r1, [r3, #76] ; 0x4c
|
|
800a6ea: 687b ldr r3, [r7, #4]
|
|
800a6ec: 699a ldr r2, [r3, #24]
|
|
800a6ee: 687b ldr r3, [r7, #4]
|
|
800a6f0: 681b ldr r3, [r3, #0]
|
|
800a6f2: 430a orrs r2, r1
|
|
800a6f4: 64da str r2, [r3, #76] ; 0x4c
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a6f6: 687b ldr r3, [r7, #4]
|
|
800a6f8: 681b ldr r3, [r3, #0]
|
|
800a6fa: 22ff movs r2, #255 ; 0xff
|
|
800a6fc: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800a6fe: 687b ldr r3, [r7, #4]
|
|
800a700: 2201 movs r2, #1
|
|
800a702: 775a strb r2, [r3, #29]
|
|
|
|
return HAL_OK;
|
|
800a704: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800a706: 4618 mov r0, r3
|
|
800a708: 3708 adds r7, #8
|
|
800a70a: 46bd mov sp, r7
|
|
800a70c: bd80 pop {r7, pc}
|
|
800a70e: bf00 nop
|
|
800a710: ff8fffbf .word 0xff8fffbf
|
|
|
|
0800a714 <HAL_RTC_SetTime>:
|
|
* @arg FORMAT_BIN: Binary data format
|
|
* @arg FORMAT_BCD: BCD data format
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
|
|
{
|
|
800a714: b590 push {r4, r7, lr}
|
|
800a716: b087 sub sp, #28
|
|
800a718: af00 add r7, sp, #0
|
|
800a71a: 60f8 str r0, [r7, #12]
|
|
800a71c: 60b9 str r1, [r7, #8]
|
|
800a71e: 607a str r2, [r7, #4]
|
|
uint32_t tmpreg = 0;
|
|
800a720: 2300 movs r3, #0
|
|
800a722: 617b str r3, [r7, #20]
|
|
assert_param(IS_RTC_FORMAT(Format));
|
|
assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
|
|
assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800a724: 68fb ldr r3, [r7, #12]
|
|
800a726: 7f1b ldrb r3, [r3, #28]
|
|
800a728: 2b01 cmp r3, #1
|
|
800a72a: d101 bne.n 800a730 <HAL_RTC_SetTime+0x1c>
|
|
800a72c: 2302 movs r3, #2
|
|
800a72e: e0a8 b.n 800a882 <HAL_RTC_SetTime+0x16e>
|
|
800a730: 68fb ldr r3, [r7, #12]
|
|
800a732: 2201 movs r2, #1
|
|
800a734: 771a strb r2, [r3, #28]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800a736: 68fb ldr r3, [r7, #12]
|
|
800a738: 2202 movs r2, #2
|
|
800a73a: 775a strb r2, [r3, #29]
|
|
|
|
if(Format == RTC_FORMAT_BIN)
|
|
800a73c: 687b ldr r3, [r7, #4]
|
|
800a73e: 2b00 cmp r3, #0
|
|
800a740: d126 bne.n 800a790 <HAL_RTC_SetTime+0x7c>
|
|
{
|
|
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
|
|
800a742: 68fb ldr r3, [r7, #12]
|
|
800a744: 681b ldr r3, [r3, #0]
|
|
800a746: 689b ldr r3, [r3, #8]
|
|
800a748: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a74c: 2b00 cmp r3, #0
|
|
800a74e: d102 bne.n 800a756 <HAL_RTC_SetTime+0x42>
|
|
assert_param(IS_RTC_HOUR12(sTime->Hours));
|
|
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sTime->TimeFormat = 0x00;
|
|
800a750: 68bb ldr r3, [r7, #8]
|
|
800a752: 2200 movs r2, #0
|
|
800a754: 731a strb r2, [r3, #12]
|
|
assert_param(IS_RTC_HOUR24(sTime->Hours));
|
|
}
|
|
assert_param(IS_RTC_MINUTES(sTime->Minutes));
|
|
assert_param(IS_RTC_SECONDS(sTime->Seconds));
|
|
|
|
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
|
|
800a756: 68bb ldr r3, [r7, #8]
|
|
800a758: 781b ldrb r3, [r3, #0]
|
|
800a75a: 4618 mov r0, r3
|
|
800a75c: f000 faac bl 800acb8 <RTC_ByteToBcd2>
|
|
800a760: 4603 mov r3, r0
|
|
800a762: 041c lsls r4, r3, #16
|
|
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
|
|
800a764: 68bb ldr r3, [r7, #8]
|
|
800a766: 785b ldrb r3, [r3, #1]
|
|
800a768: 4618 mov r0, r3
|
|
800a76a: f000 faa5 bl 800acb8 <RTC_ByteToBcd2>
|
|
800a76e: 4603 mov r3, r0
|
|
800a770: 021b lsls r3, r3, #8
|
|
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
|
|
800a772: 431c orrs r4, r3
|
|
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
|
|
800a774: 68bb ldr r3, [r7, #8]
|
|
800a776: 789b ldrb r3, [r3, #2]
|
|
800a778: 4618 mov r0, r3
|
|
800a77a: f000 fa9d bl 800acb8 <RTC_ByteToBcd2>
|
|
800a77e: 4603 mov r3, r0
|
|
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
|
|
800a780: ea44 0203 orr.w r2, r4, r3
|
|
(((uint32_t)sTime->TimeFormat) << 16));
|
|
800a784: 68bb ldr r3, [r7, #8]
|
|
800a786: 7b1b ldrb r3, [r3, #12]
|
|
800a788: 041b lsls r3, r3, #16
|
|
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
|
|
800a78a: 4313 orrs r3, r2
|
|
800a78c: 617b str r3, [r7, #20]
|
|
800a78e: e018 b.n 800a7c2 <HAL_RTC_SetTime+0xae>
|
|
}
|
|
else
|
|
{
|
|
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
|
|
800a790: 68fb ldr r3, [r7, #12]
|
|
800a792: 681b ldr r3, [r3, #0]
|
|
800a794: 689b ldr r3, [r3, #8]
|
|
800a796: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800a79a: 2b00 cmp r3, #0
|
|
800a79c: d102 bne.n 800a7a4 <HAL_RTC_SetTime+0x90>
|
|
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
|
|
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sTime->TimeFormat = 0x00;
|
|
800a79e: 68bb ldr r3, [r7, #8]
|
|
800a7a0: 2200 movs r2, #0
|
|
800a7a2: 731a strb r2, [r3, #12]
|
|
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
|
|
}
|
|
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
|
|
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
|
|
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
|
|
800a7a4: 68bb ldr r3, [r7, #8]
|
|
800a7a6: 781b ldrb r3, [r3, #0]
|
|
800a7a8: 041a lsls r2, r3, #16
|
|
((uint32_t)(sTime->Minutes) << 8) | \
|
|
800a7aa: 68bb ldr r3, [r7, #8]
|
|
800a7ac: 785b ldrb r3, [r3, #1]
|
|
800a7ae: 021b lsls r3, r3, #8
|
|
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
|
|
800a7b0: 4313 orrs r3, r2
|
|
((uint32_t)sTime->Seconds) | \
|
|
800a7b2: 68ba ldr r2, [r7, #8]
|
|
800a7b4: 7892 ldrb r2, [r2, #2]
|
|
((uint32_t)(sTime->Minutes) << 8) | \
|
|
800a7b6: 431a orrs r2, r3
|
|
((uint32_t)(sTime->TimeFormat) << 16));
|
|
800a7b8: 68bb ldr r3, [r7, #8]
|
|
800a7ba: 7b1b ldrb r3, [r3, #12]
|
|
800a7bc: 041b lsls r3, r3, #16
|
|
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
|
|
800a7be: 4313 orrs r3, r2
|
|
800a7c0: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800a7c2: 68fb ldr r3, [r7, #12]
|
|
800a7c4: 681b ldr r3, [r3, #0]
|
|
800a7c6: 22ca movs r2, #202 ; 0xca
|
|
800a7c8: 625a str r2, [r3, #36] ; 0x24
|
|
800a7ca: 68fb ldr r3, [r7, #12]
|
|
800a7cc: 681b ldr r3, [r3, #0]
|
|
800a7ce: 2253 movs r2, #83 ; 0x53
|
|
800a7d0: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set Initialization mode */
|
|
if(RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
800a7d2: 68f8 ldr r0, [r7, #12]
|
|
800a7d4: f000 fa44 bl 800ac60 <RTC_EnterInitMode>
|
|
800a7d8: 4603 mov r3, r0
|
|
800a7da: 2b00 cmp r3, #0
|
|
800a7dc: d00b beq.n 800a7f6 <HAL_RTC_SetTime+0xe2>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a7de: 68fb ldr r3, [r7, #12]
|
|
800a7e0: 681b ldr r3, [r3, #0]
|
|
800a7e2: 22ff movs r2, #255 ; 0xff
|
|
800a7e4: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set RTC state */
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800a7e6: 68fb ldr r3, [r7, #12]
|
|
800a7e8: 2204 movs r2, #4
|
|
800a7ea: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800a7ec: 68fb ldr r3, [r7, #12]
|
|
800a7ee: 2200 movs r2, #0
|
|
800a7f0: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_ERROR;
|
|
800a7f2: 2301 movs r3, #1
|
|
800a7f4: e045 b.n 800a882 <HAL_RTC_SetTime+0x16e>
|
|
}
|
|
else
|
|
{
|
|
/* Set the RTC_TR register */
|
|
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
|
|
800a7f6: 68fb ldr r3, [r7, #12]
|
|
800a7f8: 681a ldr r2, [r3, #0]
|
|
800a7fa: 6979 ldr r1, [r7, #20]
|
|
800a7fc: 4b23 ldr r3, [pc, #140] ; (800a88c <HAL_RTC_SetTime+0x178>)
|
|
800a7fe: 400b ands r3, r1
|
|
800a800: 6013 str r3, [r2, #0]
|
|
|
|
/* Clear the bits to be configured */
|
|
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
|
|
800a802: 68fb ldr r3, [r7, #12]
|
|
800a804: 681b ldr r3, [r3, #0]
|
|
800a806: 689a ldr r2, [r3, #8]
|
|
800a808: 68fb ldr r3, [r7, #12]
|
|
800a80a: 681b ldr r3, [r3, #0]
|
|
800a80c: f422 2280 bic.w r2, r2, #262144 ; 0x40000
|
|
800a810: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the RTC_CR register */
|
|
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
|
|
800a812: 68fb ldr r3, [r7, #12]
|
|
800a814: 681b ldr r3, [r3, #0]
|
|
800a816: 6899 ldr r1, [r3, #8]
|
|
800a818: 68bb ldr r3, [r7, #8]
|
|
800a81a: 691a ldr r2, [r3, #16]
|
|
800a81c: 68bb ldr r3, [r7, #8]
|
|
800a81e: 695b ldr r3, [r3, #20]
|
|
800a820: 431a orrs r2, r3
|
|
800a822: 68fb ldr r3, [r7, #12]
|
|
800a824: 681b ldr r3, [r3, #0]
|
|
800a826: 430a orrs r2, r1
|
|
800a828: 609a str r2, [r3, #8]
|
|
|
|
/* Exit Initialization mode */
|
|
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
|
800a82a: 68fb ldr r3, [r7, #12]
|
|
800a82c: 681b ldr r3, [r3, #0]
|
|
800a82e: 68da ldr r2, [r3, #12]
|
|
800a830: 68fb ldr r3, [r7, #12]
|
|
800a832: 681b ldr r3, [r3, #0]
|
|
800a834: f022 0280 bic.w r2, r2, #128 ; 0x80
|
|
800a838: 60da str r2, [r3, #12]
|
|
|
|
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
|
|
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
|
|
800a83a: 68fb ldr r3, [r7, #12]
|
|
800a83c: 681b ldr r3, [r3, #0]
|
|
800a83e: 689b ldr r3, [r3, #8]
|
|
800a840: f003 0320 and.w r3, r3, #32
|
|
800a844: 2b00 cmp r3, #0
|
|
800a846: d111 bne.n 800a86c <HAL_RTC_SetTime+0x158>
|
|
{
|
|
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
800a848: 68f8 ldr r0, [r7, #12]
|
|
800a84a: f000 f9e1 bl 800ac10 <HAL_RTC_WaitForSynchro>
|
|
800a84e: 4603 mov r3, r0
|
|
800a850: 2b00 cmp r3, #0
|
|
800a852: d00b beq.n 800a86c <HAL_RTC_SetTime+0x158>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a854: 68fb ldr r3, [r7, #12]
|
|
800a856: 681b ldr r3, [r3, #0]
|
|
800a858: 22ff movs r2, #255 ; 0xff
|
|
800a85a: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800a85c: 68fb ldr r3, [r7, #12]
|
|
800a85e: 2204 movs r2, #4
|
|
800a860: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800a862: 68fb ldr r3, [r7, #12]
|
|
800a864: 2200 movs r2, #0
|
|
800a866: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_ERROR;
|
|
800a868: 2301 movs r3, #1
|
|
800a86a: e00a b.n 800a882 <HAL_RTC_SetTime+0x16e>
|
|
}
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a86c: 68fb ldr r3, [r7, #12]
|
|
800a86e: 681b ldr r3, [r3, #0]
|
|
800a870: 22ff movs r2, #255 ; 0xff
|
|
800a872: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800a874: 68fb ldr r3, [r7, #12]
|
|
800a876: 2201 movs r2, #1
|
|
800a878: 775a strb r2, [r3, #29]
|
|
|
|
__HAL_UNLOCK(hrtc);
|
|
800a87a: 68fb ldr r3, [r7, #12]
|
|
800a87c: 2200 movs r2, #0
|
|
800a87e: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_OK;
|
|
800a880: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800a882: 4618 mov r0, r3
|
|
800a884: 371c adds r7, #28
|
|
800a886: 46bd mov sp, r7
|
|
800a888: bd90 pop {r4, r7, pc}
|
|
800a88a: bf00 nop
|
|
800a88c: 007f7f7f .word 0x007f7f7f
|
|
|
|
0800a890 <HAL_RTC_SetDate>:
|
|
* @arg RTC_FORMAT_BIN: Binary data format
|
|
* @arg RTC_FORMAT_BCD: BCD data format
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
|
|
{
|
|
800a890: b590 push {r4, r7, lr}
|
|
800a892: b087 sub sp, #28
|
|
800a894: af00 add r7, sp, #0
|
|
800a896: 60f8 str r0, [r7, #12]
|
|
800a898: 60b9 str r1, [r7, #8]
|
|
800a89a: 607a str r2, [r7, #4]
|
|
uint32_t datetmpreg = 0;
|
|
800a89c: 2300 movs r3, #0
|
|
800a89e: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RTC_FORMAT(Format));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800a8a0: 68fb ldr r3, [r7, #12]
|
|
800a8a2: 7f1b ldrb r3, [r3, #28]
|
|
800a8a4: 2b01 cmp r3, #1
|
|
800a8a6: d101 bne.n 800a8ac <HAL_RTC_SetDate+0x1c>
|
|
800a8a8: 2302 movs r3, #2
|
|
800a8aa: e092 b.n 800a9d2 <HAL_RTC_SetDate+0x142>
|
|
800a8ac: 68fb ldr r3, [r7, #12]
|
|
800a8ae: 2201 movs r2, #1
|
|
800a8b0: 771a strb r2, [r3, #28]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800a8b2: 68fb ldr r3, [r7, #12]
|
|
800a8b4: 2202 movs r2, #2
|
|
800a8b6: 775a strb r2, [r3, #29]
|
|
|
|
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
|
|
800a8b8: 687b ldr r3, [r7, #4]
|
|
800a8ba: 2b00 cmp r3, #0
|
|
800a8bc: d10e bne.n 800a8dc <HAL_RTC_SetDate+0x4c>
|
|
800a8be: 68bb ldr r3, [r7, #8]
|
|
800a8c0: 785b ldrb r3, [r3, #1]
|
|
800a8c2: f003 0310 and.w r3, r3, #16
|
|
800a8c6: 2b00 cmp r3, #0
|
|
800a8c8: d008 beq.n 800a8dc <HAL_RTC_SetDate+0x4c>
|
|
{
|
|
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
|
|
800a8ca: 68bb ldr r3, [r7, #8]
|
|
800a8cc: 785b ldrb r3, [r3, #1]
|
|
800a8ce: f023 0310 bic.w r3, r3, #16
|
|
800a8d2: b2db uxtb r3, r3
|
|
800a8d4: 330a adds r3, #10
|
|
800a8d6: b2da uxtb r2, r3
|
|
800a8d8: 68bb ldr r3, [r7, #8]
|
|
800a8da: 705a strb r2, [r3, #1]
|
|
}
|
|
|
|
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
|
|
|
|
if(Format == RTC_FORMAT_BIN)
|
|
800a8dc: 687b ldr r3, [r7, #4]
|
|
800a8de: 2b00 cmp r3, #0
|
|
800a8e0: d11c bne.n 800a91c <HAL_RTC_SetDate+0x8c>
|
|
{
|
|
assert_param(IS_RTC_YEAR(sDate->Year));
|
|
assert_param(IS_RTC_MONTH(sDate->Month));
|
|
assert_param(IS_RTC_DATE(sDate->Date));
|
|
|
|
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
|
|
800a8e2: 68bb ldr r3, [r7, #8]
|
|
800a8e4: 78db ldrb r3, [r3, #3]
|
|
800a8e6: 4618 mov r0, r3
|
|
800a8e8: f000 f9e6 bl 800acb8 <RTC_ByteToBcd2>
|
|
800a8ec: 4603 mov r3, r0
|
|
800a8ee: 041c lsls r4, r3, #16
|
|
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
|
|
800a8f0: 68bb ldr r3, [r7, #8]
|
|
800a8f2: 785b ldrb r3, [r3, #1]
|
|
800a8f4: 4618 mov r0, r3
|
|
800a8f6: f000 f9df bl 800acb8 <RTC_ByteToBcd2>
|
|
800a8fa: 4603 mov r3, r0
|
|
800a8fc: 021b lsls r3, r3, #8
|
|
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
|
|
800a8fe: 431c orrs r4, r3
|
|
((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
|
|
800a900: 68bb ldr r3, [r7, #8]
|
|
800a902: 789b ldrb r3, [r3, #2]
|
|
800a904: 4618 mov r0, r3
|
|
800a906: f000 f9d7 bl 800acb8 <RTC_ByteToBcd2>
|
|
800a90a: 4603 mov r3, r0
|
|
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
|
|
800a90c: ea44 0203 orr.w r2, r4, r3
|
|
((uint32_t)sDate->WeekDay << 13));
|
|
800a910: 68bb ldr r3, [r7, #8]
|
|
800a912: 781b ldrb r3, [r3, #0]
|
|
800a914: 035b lsls r3, r3, #13
|
|
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
|
|
800a916: 4313 orrs r3, r2
|
|
800a918: 617b str r3, [r7, #20]
|
|
800a91a: e00e b.n 800a93a <HAL_RTC_SetDate+0xaa>
|
|
{
|
|
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
|
|
assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
|
|
assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
|
|
|
|
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
|
|
800a91c: 68bb ldr r3, [r7, #8]
|
|
800a91e: 78db ldrb r3, [r3, #3]
|
|
800a920: 041a lsls r2, r3, #16
|
|
(((uint32_t)sDate->Month) << 8) | \
|
|
800a922: 68bb ldr r3, [r7, #8]
|
|
800a924: 785b ldrb r3, [r3, #1]
|
|
800a926: 021b lsls r3, r3, #8
|
|
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
|
|
800a928: 4313 orrs r3, r2
|
|
((uint32_t)sDate->Date) | \
|
|
800a92a: 68ba ldr r2, [r7, #8]
|
|
800a92c: 7892 ldrb r2, [r2, #2]
|
|
(((uint32_t)sDate->Month) << 8) | \
|
|
800a92e: 431a orrs r2, r3
|
|
(((uint32_t)sDate->WeekDay) << 13));
|
|
800a930: 68bb ldr r3, [r7, #8]
|
|
800a932: 781b ldrb r3, [r3, #0]
|
|
800a934: 035b lsls r3, r3, #13
|
|
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
|
|
800a936: 4313 orrs r3, r2
|
|
800a938: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800a93a: 68fb ldr r3, [r7, #12]
|
|
800a93c: 681b ldr r3, [r3, #0]
|
|
800a93e: 22ca movs r2, #202 ; 0xca
|
|
800a940: 625a str r2, [r3, #36] ; 0x24
|
|
800a942: 68fb ldr r3, [r7, #12]
|
|
800a944: 681b ldr r3, [r3, #0]
|
|
800a946: 2253 movs r2, #83 ; 0x53
|
|
800a948: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set Initialization mode */
|
|
if(RTC_EnterInitMode(hrtc) != HAL_OK)
|
|
800a94a: 68f8 ldr r0, [r7, #12]
|
|
800a94c: f000 f988 bl 800ac60 <RTC_EnterInitMode>
|
|
800a950: 4603 mov r3, r0
|
|
800a952: 2b00 cmp r3, #0
|
|
800a954: d00b beq.n 800a96e <HAL_RTC_SetDate+0xde>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a956: 68fb ldr r3, [r7, #12]
|
|
800a958: 681b ldr r3, [r3, #0]
|
|
800a95a: 22ff movs r2, #255 ; 0xff
|
|
800a95c: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Set RTC state*/
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800a95e: 68fb ldr r3, [r7, #12]
|
|
800a960: 2204 movs r2, #4
|
|
800a962: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800a964: 68fb ldr r3, [r7, #12]
|
|
800a966: 2200 movs r2, #0
|
|
800a968: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_ERROR;
|
|
800a96a: 2301 movs r3, #1
|
|
800a96c: e031 b.n 800a9d2 <HAL_RTC_SetDate+0x142>
|
|
}
|
|
else
|
|
{
|
|
/* Set the RTC_DR register */
|
|
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
|
|
800a96e: 68fb ldr r3, [r7, #12]
|
|
800a970: 681a ldr r2, [r3, #0]
|
|
800a972: 6979 ldr r1, [r7, #20]
|
|
800a974: 4b19 ldr r3, [pc, #100] ; (800a9dc <HAL_RTC_SetDate+0x14c>)
|
|
800a976: 400b ands r3, r1
|
|
800a978: 6053 str r3, [r2, #4]
|
|
|
|
/* Exit Initialization mode */
|
|
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
|
|
800a97a: 68fb ldr r3, [r7, #12]
|
|
800a97c: 681b ldr r3, [r3, #0]
|
|
800a97e: 68da ldr r2, [r3, #12]
|
|
800a980: 68fb ldr r3, [r7, #12]
|
|
800a982: 681b ldr r3, [r3, #0]
|
|
800a984: f022 0280 bic.w r2, r2, #128 ; 0x80
|
|
800a988: 60da str r2, [r3, #12]
|
|
|
|
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
|
|
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
|
|
800a98a: 68fb ldr r3, [r7, #12]
|
|
800a98c: 681b ldr r3, [r3, #0]
|
|
800a98e: 689b ldr r3, [r3, #8]
|
|
800a990: f003 0320 and.w r3, r3, #32
|
|
800a994: 2b00 cmp r3, #0
|
|
800a996: d111 bne.n 800a9bc <HAL_RTC_SetDate+0x12c>
|
|
{
|
|
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
|
800a998: 68f8 ldr r0, [r7, #12]
|
|
800a99a: f000 f939 bl 800ac10 <HAL_RTC_WaitForSynchro>
|
|
800a99e: 4603 mov r3, r0
|
|
800a9a0: 2b00 cmp r3, #0
|
|
800a9a2: d00b beq.n 800a9bc <HAL_RTC_SetDate+0x12c>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a9a4: 68fb ldr r3, [r7, #12]
|
|
800a9a6: 681b ldr r3, [r3, #0]
|
|
800a9a8: 22ff movs r2, #255 ; 0xff
|
|
800a9aa: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_ERROR;
|
|
800a9ac: 68fb ldr r3, [r7, #12]
|
|
800a9ae: 2204 movs r2, #4
|
|
800a9b0: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800a9b2: 68fb ldr r3, [r7, #12]
|
|
800a9b4: 2200 movs r2, #0
|
|
800a9b6: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_ERROR;
|
|
800a9b8: 2301 movs r3, #1
|
|
800a9ba: e00a b.n 800a9d2 <HAL_RTC_SetDate+0x142>
|
|
}
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800a9bc: 68fb ldr r3, [r7, #12]
|
|
800a9be: 681b ldr r3, [r3, #0]
|
|
800a9c0: 22ff movs r2, #255 ; 0xff
|
|
800a9c2: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_READY ;
|
|
800a9c4: 68fb ldr r3, [r7, #12]
|
|
800a9c6: 2201 movs r2, #1
|
|
800a9c8: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800a9ca: 68fb ldr r3, [r7, #12]
|
|
800a9cc: 2200 movs r2, #0
|
|
800a9ce: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_OK;
|
|
800a9d0: 2300 movs r3, #0
|
|
}
|
|
}
|
|
800a9d2: 4618 mov r0, r3
|
|
800a9d4: 371c adds r7, #28
|
|
800a9d6: 46bd mov sp, r7
|
|
800a9d8: bd90 pop {r4, r7, pc}
|
|
800a9da: bf00 nop
|
|
800a9dc: 00ffff3f .word 0x00ffff3f
|
|
|
|
0800a9e0 <HAL_RTC_SetAlarm>:
|
|
* @arg FORMAT_BIN: Binary data format
|
|
* @arg FORMAT_BCD: BCD data format
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
|
|
{
|
|
800a9e0: b590 push {r4, r7, lr}
|
|
800a9e2: b089 sub sp, #36 ; 0x24
|
|
800a9e4: af00 add r7, sp, #0
|
|
800a9e6: 60f8 str r0, [r7, #12]
|
|
800a9e8: 60b9 str r1, [r7, #8]
|
|
800a9ea: 607a str r2, [r7, #4]
|
|
uint32_t tickstart = 0;
|
|
800a9ec: 2300 movs r3, #0
|
|
800a9ee: 61bb str r3, [r7, #24]
|
|
uint32_t tmpreg = 0, subsecondtmpreg = 0;
|
|
800a9f0: 2300 movs r3, #0
|
|
800a9f2: 61fb str r3, [r7, #28]
|
|
800a9f4: 2300 movs r3, #0
|
|
800a9f6: 617b str r3, [r7, #20]
|
|
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
|
|
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
|
|
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800a9f8: 68fb ldr r3, [r7, #12]
|
|
800a9fa: 7f1b ldrb r3, [r3, #28]
|
|
800a9fc: 2b01 cmp r3, #1
|
|
800a9fe: d101 bne.n 800aa04 <HAL_RTC_SetAlarm+0x24>
|
|
800aa00: 2302 movs r3, #2
|
|
800aa02: e101 b.n 800ac08 <HAL_RTC_SetAlarm+0x228>
|
|
800aa04: 68fb ldr r3, [r7, #12]
|
|
800aa06: 2201 movs r2, #1
|
|
800aa08: 771a strb r2, [r3, #28]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800aa0a: 68fb ldr r3, [r7, #12]
|
|
800aa0c: 2202 movs r2, #2
|
|
800aa0e: 775a strb r2, [r3, #29]
|
|
|
|
if(Format == RTC_FORMAT_BIN)
|
|
800aa10: 687b ldr r3, [r7, #4]
|
|
800aa12: 2b00 cmp r3, #0
|
|
800aa14: d137 bne.n 800aa86 <HAL_RTC_SetAlarm+0xa6>
|
|
{
|
|
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
|
|
800aa16: 68fb ldr r3, [r7, #12]
|
|
800aa18: 681b ldr r3, [r3, #0]
|
|
800aa1a: 689b ldr r3, [r3, #8]
|
|
800aa1c: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800aa20: 2b00 cmp r3, #0
|
|
800aa22: d102 bne.n 800aa2a <HAL_RTC_SetAlarm+0x4a>
|
|
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
|
|
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sAlarm->AlarmTime.TimeFormat = 0x00;
|
|
800aa24: 68bb ldr r3, [r7, #8]
|
|
800aa26: 2200 movs r2, #0
|
|
800aa28: 731a strb r2, [r3, #12]
|
|
else
|
|
{
|
|
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
|
|
}
|
|
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aa2a: 68bb ldr r3, [r7, #8]
|
|
800aa2c: 781b ldrb r3, [r3, #0]
|
|
800aa2e: 4618 mov r0, r3
|
|
800aa30: f000 f942 bl 800acb8 <RTC_ByteToBcd2>
|
|
800aa34: 4603 mov r3, r0
|
|
800aa36: 041c lsls r4, r3, #16
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
|
|
800aa38: 68bb ldr r3, [r7, #8]
|
|
800aa3a: 785b ldrb r3, [r3, #1]
|
|
800aa3c: 4618 mov r0, r3
|
|
800aa3e: f000 f93b bl 800acb8 <RTC_ByteToBcd2>
|
|
800aa42: 4603 mov r3, r0
|
|
800aa44: 021b lsls r3, r3, #8
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aa46: 431c orrs r4, r3
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
|
|
800aa48: 68bb ldr r3, [r7, #8]
|
|
800aa4a: 789b ldrb r3, [r3, #2]
|
|
800aa4c: 4618 mov r0, r3
|
|
800aa4e: f000 f933 bl 800acb8 <RTC_ByteToBcd2>
|
|
800aa52: 4603 mov r3, r0
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
|
|
800aa54: ea44 0203 orr.w r2, r4, r3
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
|
|
800aa58: 68bb ldr r3, [r7, #8]
|
|
800aa5a: 7b1b ldrb r3, [r3, #12]
|
|
800aa5c: 041b lsls r3, r3, #16
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
|
|
800aa5e: ea42 0403 orr.w r4, r2, r3
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
|
|
800aa62: 68bb ldr r3, [r7, #8]
|
|
800aa64: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
|
|
800aa68: 4618 mov r0, r3
|
|
800aa6a: f000 f925 bl 800acb8 <RTC_ByteToBcd2>
|
|
800aa6e: 4603 mov r3, r0
|
|
800aa70: 061b lsls r3, r3, #24
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
|
|
800aa72: ea44 0203 orr.w r2, r4, r3
|
|
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
|
|
800aa76: 68bb ldr r3, [r7, #8]
|
|
800aa78: 6a1b ldr r3, [r3, #32]
|
|
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
|
|
800aa7a: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmMask));
|
|
800aa7c: 68bb ldr r3, [r7, #8]
|
|
800aa7e: 699b ldr r3, [r3, #24]
|
|
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aa80: 4313 orrs r3, r2
|
|
800aa82: 61fb str r3, [r7, #28]
|
|
800aa84: e023 b.n 800aace <HAL_RTC_SetAlarm+0xee>
|
|
}
|
|
else
|
|
{
|
|
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
|
|
800aa86: 68fb ldr r3, [r7, #12]
|
|
800aa88: 681b ldr r3, [r3, #0]
|
|
800aa8a: 689b ldr r3, [r3, #8]
|
|
800aa8c: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800aa90: 2b00 cmp r3, #0
|
|
800aa92: d102 bne.n 800aa9a <HAL_RTC_SetAlarm+0xba>
|
|
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
|
|
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
|
|
}
|
|
else
|
|
{
|
|
sAlarm->AlarmTime.TimeFormat = 0x00;
|
|
800aa94: 68bb ldr r3, [r7, #8]
|
|
800aa96: 2200 movs r2, #0
|
|
800aa98: 731a strb r2, [r3, #12]
|
|
else
|
|
{
|
|
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
|
|
}
|
|
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aa9a: 68bb ldr r3, [r7, #8]
|
|
800aa9c: 781b ldrb r3, [r3, #0]
|
|
800aa9e: 041a lsls r2, r3, #16
|
|
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
|
|
800aaa0: 68bb ldr r3, [r7, #8]
|
|
800aaa2: 785b ldrb r3, [r3, #1]
|
|
800aaa4: 021b lsls r3, r3, #8
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aaa6: 4313 orrs r3, r2
|
|
((uint32_t) sAlarm->AlarmTime.Seconds) | \
|
|
800aaa8: 68ba ldr r2, [r7, #8]
|
|
800aaaa: 7892 ldrb r2, [r2, #2]
|
|
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
|
|
800aaac: 431a orrs r2, r3
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
|
|
800aaae: 68bb ldr r3, [r7, #8]
|
|
800aab0: 7b1b ldrb r3, [r3, #12]
|
|
800aab2: 041b lsls r3, r3, #16
|
|
((uint32_t) sAlarm->AlarmTime.Seconds) | \
|
|
800aab4: 431a orrs r2, r3
|
|
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
|
|
800aab6: 68bb ldr r3, [r7, #8]
|
|
800aab8: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
|
|
800aabc: 061b lsls r3, r3, #24
|
|
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
|
|
800aabe: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
|
|
800aac0: 68bb ldr r3, [r7, #8]
|
|
800aac2: 6a1b ldr r3, [r3, #32]
|
|
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
|
|
800aac4: 431a orrs r2, r3
|
|
((uint32_t)sAlarm->AlarmMask));
|
|
800aac6: 68bb ldr r3, [r7, #8]
|
|
800aac8: 699b ldr r3, [r3, #24]
|
|
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
|
|
800aaca: 4313 orrs r3, r2
|
|
800aacc: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Configure the Alarm A or Alarm B Sub Second registers */
|
|
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
|
|
800aace: 68bb ldr r3, [r7, #8]
|
|
800aad0: 685a ldr r2, [r3, #4]
|
|
800aad2: 68bb ldr r3, [r7, #8]
|
|
800aad4: 69db ldr r3, [r3, #28]
|
|
800aad6: 4313 orrs r3, r2
|
|
800aad8: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800aada: 68fb ldr r3, [r7, #12]
|
|
800aadc: 681b ldr r3, [r3, #0]
|
|
800aade: 22ca movs r2, #202 ; 0xca
|
|
800aae0: 625a str r2, [r3, #36] ; 0x24
|
|
800aae2: 68fb ldr r3, [r7, #12]
|
|
800aae4: 681b ldr r3, [r3, #0]
|
|
800aae6: 2253 movs r2, #83 ; 0x53
|
|
800aae8: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Configure the Alarm register */
|
|
if(sAlarm->Alarm == RTC_ALARM_A)
|
|
800aaea: 68bb ldr r3, [r7, #8]
|
|
800aaec: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800aaee: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
800aaf2: d13f bne.n 800ab74 <HAL_RTC_SetAlarm+0x194>
|
|
{
|
|
/* Disable the Alarm A interrupt */
|
|
__HAL_RTC_ALARMA_DISABLE(hrtc);
|
|
800aaf4: 68fb ldr r3, [r7, #12]
|
|
800aaf6: 681b ldr r3, [r3, #0]
|
|
800aaf8: 689a ldr r2, [r3, #8]
|
|
800aafa: 68fb ldr r3, [r7, #12]
|
|
800aafc: 681b ldr r3, [r3, #0]
|
|
800aafe: f422 7280 bic.w r2, r2, #256 ; 0x100
|
|
800ab02: 609a str r2, [r3, #8]
|
|
|
|
/* In case of interrupt mode is used, the interrupt source must disabled */
|
|
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
|
|
800ab04: 68fb ldr r3, [r7, #12]
|
|
800ab06: 681b ldr r3, [r3, #0]
|
|
800ab08: 689a ldr r2, [r3, #8]
|
|
800ab0a: 68fb ldr r3, [r7, #12]
|
|
800ab0c: 681b ldr r3, [r3, #0]
|
|
800ab0e: f422 5280 bic.w r2, r2, #4096 ; 0x1000
|
|
800ab12: 609a str r2, [r3, #8]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800ab14: f7fa fbe4 bl 80052e0 <HAL_GetTick>
|
|
800ab18: 61b8 str r0, [r7, #24]
|
|
|
|
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
|
|
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
|
|
800ab1a: e013 b.n 800ab44 <HAL_RTC_SetAlarm+0x164>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
|
|
800ab1c: f7fa fbe0 bl 80052e0 <HAL_GetTick>
|
|
800ab20: 4602 mov r2, r0
|
|
800ab22: 69bb ldr r3, [r7, #24]
|
|
800ab24: 1ad3 subs r3, r2, r3
|
|
800ab26: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
800ab2a: d90b bls.n 800ab44 <HAL_RTC_SetAlarm+0x164>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800ab2c: 68fb ldr r3, [r7, #12]
|
|
800ab2e: 681b ldr r3, [r3, #0]
|
|
800ab30: 22ff movs r2, #255 ; 0xff
|
|
800ab32: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800ab34: 68fb ldr r3, [r7, #12]
|
|
800ab36: 2203 movs r2, #3
|
|
800ab38: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800ab3a: 68fb ldr r3, [r7, #12]
|
|
800ab3c: 2200 movs r2, #0
|
|
800ab3e: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_TIMEOUT;
|
|
800ab40: 2303 movs r3, #3
|
|
800ab42: e061 b.n 800ac08 <HAL_RTC_SetAlarm+0x228>
|
|
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
|
|
800ab44: 68fb ldr r3, [r7, #12]
|
|
800ab46: 681b ldr r3, [r3, #0]
|
|
800ab48: 68db ldr r3, [r3, #12]
|
|
800ab4a: f003 0301 and.w r3, r3, #1
|
|
800ab4e: 2b00 cmp r3, #0
|
|
800ab50: d0e4 beq.n 800ab1c <HAL_RTC_SetAlarm+0x13c>
|
|
}
|
|
}
|
|
|
|
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
|
|
800ab52: 68fb ldr r3, [r7, #12]
|
|
800ab54: 681b ldr r3, [r3, #0]
|
|
800ab56: 69fa ldr r2, [r7, #28]
|
|
800ab58: 61da str r2, [r3, #28]
|
|
/* Configure the Alarm A Sub Second register */
|
|
hrtc->Instance->ALRMASSR = subsecondtmpreg;
|
|
800ab5a: 68fb ldr r3, [r7, #12]
|
|
800ab5c: 681b ldr r3, [r3, #0]
|
|
800ab5e: 697a ldr r2, [r7, #20]
|
|
800ab60: 645a str r2, [r3, #68] ; 0x44
|
|
/* Configure the Alarm state: Enable Alarm */
|
|
__HAL_RTC_ALARMA_ENABLE(hrtc);
|
|
800ab62: 68fb ldr r3, [r7, #12]
|
|
800ab64: 681b ldr r3, [r3, #0]
|
|
800ab66: 689a ldr r2, [r3, #8]
|
|
800ab68: 68fb ldr r3, [r7, #12]
|
|
800ab6a: 681b ldr r3, [r3, #0]
|
|
800ab6c: f442 7280 orr.w r2, r2, #256 ; 0x100
|
|
800ab70: 609a str r2, [r3, #8]
|
|
800ab72: e03e b.n 800abf2 <HAL_RTC_SetAlarm+0x212>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Alarm B interrupt */
|
|
__HAL_RTC_ALARMB_DISABLE(hrtc);
|
|
800ab74: 68fb ldr r3, [r7, #12]
|
|
800ab76: 681b ldr r3, [r3, #0]
|
|
800ab78: 689a ldr r2, [r3, #8]
|
|
800ab7a: 68fb ldr r3, [r7, #12]
|
|
800ab7c: 681b ldr r3, [r3, #0]
|
|
800ab7e: f422 7200 bic.w r2, r2, #512 ; 0x200
|
|
800ab82: 609a str r2, [r3, #8]
|
|
|
|
/* In case of interrupt mode is used, the interrupt source must disabled */
|
|
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
|
|
800ab84: 68fb ldr r3, [r7, #12]
|
|
800ab86: 681b ldr r3, [r3, #0]
|
|
800ab88: 689a ldr r2, [r3, #8]
|
|
800ab8a: 68fb ldr r3, [r7, #12]
|
|
800ab8c: 681b ldr r3, [r3, #0]
|
|
800ab8e: f422 5200 bic.w r2, r2, #8192 ; 0x2000
|
|
800ab92: 609a str r2, [r3, #8]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800ab94: f7fa fba4 bl 80052e0 <HAL_GetTick>
|
|
800ab98: 61b8 str r0, [r7, #24]
|
|
|
|
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
|
|
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
|
|
800ab9a: e013 b.n 800abc4 <HAL_RTC_SetAlarm+0x1e4>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
|
|
800ab9c: f7fa fba0 bl 80052e0 <HAL_GetTick>
|
|
800aba0: 4602 mov r2, r0
|
|
800aba2: 69bb ldr r3, [r7, #24]
|
|
800aba4: 1ad3 subs r3, r2, r3
|
|
800aba6: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
800abaa: d90b bls.n 800abc4 <HAL_RTC_SetAlarm+0x1e4>
|
|
{
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800abac: 68fb ldr r3, [r7, #12]
|
|
800abae: 681b ldr r3, [r3, #0]
|
|
800abb0: 22ff movs r2, #255 ; 0xff
|
|
800abb2: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->State = HAL_RTC_STATE_TIMEOUT;
|
|
800abb4: 68fb ldr r3, [r7, #12]
|
|
800abb6: 2203 movs r2, #3
|
|
800abb8: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800abba: 68fb ldr r3, [r7, #12]
|
|
800abbc: 2200 movs r2, #0
|
|
800abbe: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_TIMEOUT;
|
|
800abc0: 2303 movs r3, #3
|
|
800abc2: e021 b.n 800ac08 <HAL_RTC_SetAlarm+0x228>
|
|
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
|
|
800abc4: 68fb ldr r3, [r7, #12]
|
|
800abc6: 681b ldr r3, [r3, #0]
|
|
800abc8: 68db ldr r3, [r3, #12]
|
|
800abca: f003 0302 and.w r3, r3, #2
|
|
800abce: 2b00 cmp r3, #0
|
|
800abd0: d0e4 beq.n 800ab9c <HAL_RTC_SetAlarm+0x1bc>
|
|
}
|
|
}
|
|
|
|
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
|
|
800abd2: 68fb ldr r3, [r7, #12]
|
|
800abd4: 681b ldr r3, [r3, #0]
|
|
800abd6: 69fa ldr r2, [r7, #28]
|
|
800abd8: 621a str r2, [r3, #32]
|
|
/* Configure the Alarm B Sub Second register */
|
|
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
|
|
800abda: 68fb ldr r3, [r7, #12]
|
|
800abdc: 681b ldr r3, [r3, #0]
|
|
800abde: 697a ldr r2, [r7, #20]
|
|
800abe0: 649a str r2, [r3, #72] ; 0x48
|
|
/* Configure the Alarm state: Enable Alarm */
|
|
__HAL_RTC_ALARMB_ENABLE(hrtc);
|
|
800abe2: 68fb ldr r3, [r7, #12]
|
|
800abe4: 681b ldr r3, [r3, #0]
|
|
800abe6: 689a ldr r2, [r3, #8]
|
|
800abe8: 68fb ldr r3, [r7, #12]
|
|
800abea: 681b ldr r3, [r3, #0]
|
|
800abec: f442 7200 orr.w r2, r2, #512 ; 0x200
|
|
800abf0: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800abf2: 68fb ldr r3, [r7, #12]
|
|
800abf4: 681b ldr r3, [r3, #0]
|
|
800abf6: 22ff movs r2, #255 ; 0xff
|
|
800abf8: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800abfa: 68fb ldr r3, [r7, #12]
|
|
800abfc: 2201 movs r2, #1
|
|
800abfe: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800ac00: 68fb ldr r3, [r7, #12]
|
|
800ac02: 2200 movs r2, #0
|
|
800ac04: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_OK;
|
|
800ac06: 2300 movs r3, #0
|
|
}
|
|
800ac08: 4618 mov r0, r3
|
|
800ac0a: 3724 adds r7, #36 ; 0x24
|
|
800ac0c: 46bd mov sp, r7
|
|
800ac0e: bd90 pop {r4, r7, pc}
|
|
|
|
0800ac10 <HAL_RTC_WaitForSynchro>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
|
|
{
|
|
800ac10: b580 push {r7, lr}
|
|
800ac12: b084 sub sp, #16
|
|
800ac14: af00 add r7, sp, #0
|
|
800ac16: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0;
|
|
800ac18: 2300 movs r3, #0
|
|
800ac1a: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear RSF flag */
|
|
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
|
|
800ac1c: 687b ldr r3, [r7, #4]
|
|
800ac1e: 681b ldr r3, [r3, #0]
|
|
800ac20: 68da ldr r2, [r3, #12]
|
|
800ac22: 687b ldr r3, [r7, #4]
|
|
800ac24: 681b ldr r3, [r3, #0]
|
|
800ac26: f022 02a0 bic.w r2, r2, #160 ; 0xa0
|
|
800ac2a: 60da str r2, [r3, #12]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800ac2c: f7fa fb58 bl 80052e0 <HAL_GetTick>
|
|
800ac30: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait the registers to be synchronised */
|
|
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
|
|
800ac32: e009 b.n 800ac48 <HAL_RTC_WaitForSynchro+0x38>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
|
|
800ac34: f7fa fb54 bl 80052e0 <HAL_GetTick>
|
|
800ac38: 4602 mov r2, r0
|
|
800ac3a: 68fb ldr r3, [r7, #12]
|
|
800ac3c: 1ad3 subs r3, r2, r3
|
|
800ac3e: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
800ac42: d901 bls.n 800ac48 <HAL_RTC_WaitForSynchro+0x38>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ac44: 2303 movs r3, #3
|
|
800ac46: e007 b.n 800ac58 <HAL_RTC_WaitForSynchro+0x48>
|
|
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
|
|
800ac48: 687b ldr r3, [r7, #4]
|
|
800ac4a: 681b ldr r3, [r3, #0]
|
|
800ac4c: 68db ldr r3, [r3, #12]
|
|
800ac4e: f003 0320 and.w r3, r3, #32
|
|
800ac52: 2b00 cmp r3, #0
|
|
800ac54: d0ee beq.n 800ac34 <HAL_RTC_WaitForSynchro+0x24>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800ac56: 2300 movs r3, #0
|
|
}
|
|
800ac58: 4618 mov r0, r3
|
|
800ac5a: 3710 adds r7, #16
|
|
800ac5c: 46bd mov sp, r7
|
|
800ac5e: bd80 pop {r7, pc}
|
|
|
|
0800ac60 <RTC_EnterInitMode>:
|
|
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
|
|
* the configuration information for RTC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
|
|
{
|
|
800ac60: b580 push {r7, lr}
|
|
800ac62: b084 sub sp, #16
|
|
800ac64: af00 add r7, sp, #0
|
|
800ac66: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0;
|
|
800ac68: 2300 movs r3, #0
|
|
800ac6a: 60fb str r3, [r7, #12]
|
|
|
|
/* Check if the Initialization mode is set */
|
|
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
|
800ac6c: 687b ldr r3, [r7, #4]
|
|
800ac6e: 681b ldr r3, [r3, #0]
|
|
800ac70: 68db ldr r3, [r3, #12]
|
|
800ac72: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800ac76: 2b00 cmp r3, #0
|
|
800ac78: d119 bne.n 800acae <RTC_EnterInitMode+0x4e>
|
|
{
|
|
/* Set the Initialization mode */
|
|
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
|
|
800ac7a: 687b ldr r3, [r7, #4]
|
|
800ac7c: 681b ldr r3, [r3, #0]
|
|
800ac7e: f04f 32ff mov.w r2, #4294967295
|
|
800ac82: 60da str r2, [r3, #12]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800ac84: f7fa fb2c bl 80052e0 <HAL_GetTick>
|
|
800ac88: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till RTC is in INIT state and if Time out is reached exit */
|
|
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
|
800ac8a: e009 b.n 800aca0 <RTC_EnterInitMode+0x40>
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
|
|
800ac8c: f7fa fb28 bl 80052e0 <HAL_GetTick>
|
|
800ac90: 4602 mov r2, r0
|
|
800ac92: 68fb ldr r3, [r7, #12]
|
|
800ac94: 1ad3 subs r3, r2, r3
|
|
800ac96: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
800ac9a: d901 bls.n 800aca0 <RTC_EnterInitMode+0x40>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800ac9c: 2303 movs r3, #3
|
|
800ac9e: e007 b.n 800acb0 <RTC_EnterInitMode+0x50>
|
|
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
|
|
800aca0: 687b ldr r3, [r7, #4]
|
|
800aca2: 681b ldr r3, [r3, #0]
|
|
800aca4: 68db ldr r3, [r3, #12]
|
|
800aca6: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800acaa: 2b00 cmp r3, #0
|
|
800acac: d0ee beq.n 800ac8c <RTC_EnterInitMode+0x2c>
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
800acae: 2300 movs r3, #0
|
|
}
|
|
800acb0: 4618 mov r0, r3
|
|
800acb2: 3710 adds r7, #16
|
|
800acb4: 46bd mov sp, r7
|
|
800acb6: bd80 pop {r7, pc}
|
|
|
|
0800acb8 <RTC_ByteToBcd2>:
|
|
* @brief Converts a 2 digit decimal to BCD format.
|
|
* @param Value Byte to be converted
|
|
* @retval Converted byte
|
|
*/
|
|
uint8_t RTC_ByteToBcd2(uint8_t Value)
|
|
{
|
|
800acb8: b480 push {r7}
|
|
800acba: b085 sub sp, #20
|
|
800acbc: af00 add r7, sp, #0
|
|
800acbe: 4603 mov r3, r0
|
|
800acc0: 71fb strb r3, [r7, #7]
|
|
uint32_t bcdhigh = 0;
|
|
800acc2: 2300 movs r3, #0
|
|
800acc4: 60fb str r3, [r7, #12]
|
|
|
|
while(Value >= 10)
|
|
800acc6: e005 b.n 800acd4 <RTC_ByteToBcd2+0x1c>
|
|
{
|
|
bcdhigh++;
|
|
800acc8: 68fb ldr r3, [r7, #12]
|
|
800acca: 3301 adds r3, #1
|
|
800accc: 60fb str r3, [r7, #12]
|
|
Value -= 10;
|
|
800acce: 79fb ldrb r3, [r7, #7]
|
|
800acd0: 3b0a subs r3, #10
|
|
800acd2: 71fb strb r3, [r7, #7]
|
|
while(Value >= 10)
|
|
800acd4: 79fb ldrb r3, [r7, #7]
|
|
800acd6: 2b09 cmp r3, #9
|
|
800acd8: d8f6 bhi.n 800acc8 <RTC_ByteToBcd2+0x10>
|
|
}
|
|
|
|
return ((uint8_t)(bcdhigh << 4) | Value);
|
|
800acda: 68fb ldr r3, [r7, #12]
|
|
800acdc: b2db uxtb r3, r3
|
|
800acde: 011b lsls r3, r3, #4
|
|
800ace0: b2da uxtb r2, r3
|
|
800ace2: 79fb ldrb r3, [r7, #7]
|
|
800ace4: 4313 orrs r3, r2
|
|
800ace6: b2db uxtb r3, r3
|
|
}
|
|
800ace8: 4618 mov r0, r3
|
|
800acea: 3714 adds r7, #20
|
|
800acec: 46bd mov sp, r7
|
|
800acee: f85d 7b04 ldr.w r7, [sp], #4
|
|
800acf2: 4770 bx lr
|
|
|
|
0800acf4 <HAL_RTCEx_SetTimeStamp>:
|
|
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
|
|
* @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
|
|
{
|
|
800acf4: b480 push {r7}
|
|
800acf6: b087 sub sp, #28
|
|
800acf8: af00 add r7, sp, #0
|
|
800acfa: 60f8 str r0, [r7, #12]
|
|
800acfc: 60b9 str r1, [r7, #8]
|
|
800acfe: 607a str r2, [r7, #4]
|
|
uint32_t tmpreg = 0;
|
|
800ad00: 2300 movs r3, #0
|
|
800ad02: 617b str r3, [r7, #20]
|
|
/* Check the parameters */
|
|
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
|
|
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hrtc);
|
|
800ad04: 68fb ldr r3, [r7, #12]
|
|
800ad06: 7f1b ldrb r3, [r3, #28]
|
|
800ad08: 2b01 cmp r3, #1
|
|
800ad0a: d101 bne.n 800ad10 <HAL_RTCEx_SetTimeStamp+0x1c>
|
|
800ad0c: 2302 movs r3, #2
|
|
800ad0e: e03e b.n 800ad8e <HAL_RTCEx_SetTimeStamp+0x9a>
|
|
800ad10: 68fb ldr r3, [r7, #12]
|
|
800ad12: 2201 movs r2, #1
|
|
800ad14: 771a strb r2, [r3, #28]
|
|
|
|
hrtc->State = HAL_RTC_STATE_BUSY;
|
|
800ad16: 68fb ldr r3, [r7, #12]
|
|
800ad18: 2202 movs r2, #2
|
|
800ad1a: 775a strb r2, [r3, #29]
|
|
|
|
/* Get the RTC_CR register and clear the bits to be configured */
|
|
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
|
|
800ad1c: 68fb ldr r3, [r7, #12]
|
|
800ad1e: 681b ldr r3, [r3, #0]
|
|
800ad20: 689a ldr r2, [r3, #8]
|
|
800ad22: 4b1e ldr r3, [pc, #120] ; (800ad9c <HAL_RTCEx_SetTimeStamp+0xa8>)
|
|
800ad24: 4013 ands r3, r2
|
|
800ad26: 617b str r3, [r7, #20]
|
|
|
|
tmpreg|= TimeStampEdge;
|
|
800ad28: 697a ldr r2, [r7, #20]
|
|
800ad2a: 68bb ldr r3, [r7, #8]
|
|
800ad2c: 4313 orrs r3, r2
|
|
800ad2e: 617b str r3, [r7, #20]
|
|
|
|
/* Disable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
|
|
800ad30: 68fb ldr r3, [r7, #12]
|
|
800ad32: 681b ldr r3, [r3, #0]
|
|
800ad34: 22ca movs r2, #202 ; 0xca
|
|
800ad36: 625a str r2, [r3, #36] ; 0x24
|
|
800ad38: 68fb ldr r3, [r7, #12]
|
|
800ad3a: 681b ldr r3, [r3, #0]
|
|
800ad3c: 2253 movs r2, #83 ; 0x53
|
|
800ad3e: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
|
|
800ad40: 68fb ldr r3, [r7, #12]
|
|
800ad42: 681b ldr r3, [r3, #0]
|
|
800ad44: 6cda ldr r2, [r3, #76] ; 0x4c
|
|
800ad46: 68fb ldr r3, [r7, #12]
|
|
800ad48: 681b ldr r3, [r3, #0]
|
|
800ad4a: f022 0206 bic.w r2, r2, #6
|
|
800ad4e: 64da str r2, [r3, #76] ; 0x4c
|
|
hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
|
|
800ad50: 68fb ldr r3, [r7, #12]
|
|
800ad52: 681b ldr r3, [r3, #0]
|
|
800ad54: 6cd9 ldr r1, [r3, #76] ; 0x4c
|
|
800ad56: 68fb ldr r3, [r7, #12]
|
|
800ad58: 681b ldr r3, [r3, #0]
|
|
800ad5a: 687a ldr r2, [r7, #4]
|
|
800ad5c: 430a orrs r2, r1
|
|
800ad5e: 64da str r2, [r3, #76] ; 0x4c
|
|
|
|
/* Configure the Time Stamp TSEDGE and Enable bits */
|
|
hrtc->Instance->CR = (uint32_t)tmpreg;
|
|
800ad60: 68fb ldr r3, [r7, #12]
|
|
800ad62: 681b ldr r3, [r3, #0]
|
|
800ad64: 697a ldr r2, [r7, #20]
|
|
800ad66: 609a str r2, [r3, #8]
|
|
|
|
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
|
|
800ad68: 68fb ldr r3, [r7, #12]
|
|
800ad6a: 681b ldr r3, [r3, #0]
|
|
800ad6c: 689a ldr r2, [r3, #8]
|
|
800ad6e: 68fb ldr r3, [r7, #12]
|
|
800ad70: 681b ldr r3, [r3, #0]
|
|
800ad72: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800ad76: 609a str r2, [r3, #8]
|
|
|
|
/* Enable the write protection for RTC registers */
|
|
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
|
|
800ad78: 68fb ldr r3, [r7, #12]
|
|
800ad7a: 681b ldr r3, [r3, #0]
|
|
800ad7c: 22ff movs r2, #255 ; 0xff
|
|
800ad7e: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Change RTC state */
|
|
hrtc->State = HAL_RTC_STATE_READY;
|
|
800ad80: 68fb ldr r3, [r7, #12]
|
|
800ad82: 2201 movs r2, #1
|
|
800ad84: 775a strb r2, [r3, #29]
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hrtc);
|
|
800ad86: 68fb ldr r3, [r7, #12]
|
|
800ad88: 2200 movs r2, #0
|
|
800ad8a: 771a strb r2, [r3, #28]
|
|
|
|
return HAL_OK;
|
|
800ad8c: 2300 movs r3, #0
|
|
}
|
|
800ad8e: 4618 mov r0, r3
|
|
800ad90: 371c adds r7, #28
|
|
800ad92: 46bd mov sp, r7
|
|
800ad94: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ad98: 4770 bx lr
|
|
800ad9a: bf00 nop
|
|
800ad9c: fffff7f7 .word 0xfffff7f7
|
|
|
|
0800ada0 <HAL_SDRAM_Init>:
|
|
* the configuration information for SDRAM module.
|
|
* @param Timing Pointer to SDRAM control timing structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
|
|
{
|
|
800ada0: b580 push {r7, lr}
|
|
800ada2: b082 sub sp, #8
|
|
800ada4: af00 add r7, sp, #0
|
|
800ada6: 6078 str r0, [r7, #4]
|
|
800ada8: 6039 str r1, [r7, #0]
|
|
/* Check the SDRAM handle parameter */
|
|
if(hsdram == NULL)
|
|
800adaa: 687b ldr r3, [r7, #4]
|
|
800adac: 2b00 cmp r3, #0
|
|
800adae: d101 bne.n 800adb4 <HAL_SDRAM_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
800adb0: 2301 movs r3, #1
|
|
800adb2: e025 b.n 800ae00 <HAL_SDRAM_Init+0x60>
|
|
}
|
|
|
|
if(hsdram->State == HAL_SDRAM_STATE_RESET)
|
|
800adb4: 687b ldr r3, [r7, #4]
|
|
800adb6: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
|
|
800adba: b2db uxtb r3, r3
|
|
800adbc: 2b00 cmp r3, #0
|
|
800adbe: d106 bne.n 800adce <HAL_SDRAM_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hsdram->Lock = HAL_UNLOCKED;
|
|
800adc0: 687b ldr r3, [r7, #4]
|
|
800adc2: 2200 movs r2, #0
|
|
800adc4: f883 202d strb.w r2, [r3, #45] ; 0x2d
|
|
|
|
/* Init the low level hardware */
|
|
hsdram->MspInitCallback(hsdram);
|
|
#else
|
|
/* Initialize the low level hardware (MSP) */
|
|
HAL_SDRAM_MspInit(hsdram);
|
|
800adc8: 6878 ldr r0, [r7, #4]
|
|
800adca: f7fa f8e9 bl 8004fa0 <HAL_SDRAM_MspInit>
|
|
#endif
|
|
}
|
|
|
|
/* Initialize the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
800adce: 687b ldr r3, [r7, #4]
|
|
800add0: 2202 movs r2, #2
|
|
800add2: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
/* Initialize SDRAM control Interface */
|
|
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
|
|
800add6: 687b ldr r3, [r7, #4]
|
|
800add8: 681a ldr r2, [r3, #0]
|
|
800adda: 687b ldr r3, [r7, #4]
|
|
800addc: 3304 adds r3, #4
|
|
800adde: 4619 mov r1, r3
|
|
800ade0: 4610 mov r0, r2
|
|
800ade2: f001 fe61 bl 800caa8 <FMC_SDRAM_Init>
|
|
|
|
/* Initialize SDRAM timing Interface */
|
|
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
|
|
800ade6: 687b ldr r3, [r7, #4]
|
|
800ade8: 6818 ldr r0, [r3, #0]
|
|
800adea: 687b ldr r3, [r7, #4]
|
|
800adec: 685b ldr r3, [r3, #4]
|
|
800adee: 461a mov r2, r3
|
|
800adf0: 6839 ldr r1, [r7, #0]
|
|
800adf2: f001 fecb bl 800cb8c <FMC_SDRAM_Timing_Init>
|
|
|
|
/* Update the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
800adf6: 687b ldr r3, [r7, #4]
|
|
800adf8: 2201 movs r2, #1
|
|
800adfa: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
return HAL_OK;
|
|
800adfe: 2300 movs r3, #0
|
|
}
|
|
800ae00: 4618 mov r0, r3
|
|
800ae02: 3708 adds r7, #8
|
|
800ae04: 46bd mov sp, r7
|
|
800ae06: bd80 pop {r7, pc}
|
|
|
|
0800ae08 <HAL_SDRAM_SendCommand>:
|
|
* @param Command SDRAM command structure
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
|
{
|
|
800ae08: b580 push {r7, lr}
|
|
800ae0a: b084 sub sp, #16
|
|
800ae0c: af00 add r7, sp, #0
|
|
800ae0e: 60f8 str r0, [r7, #12]
|
|
800ae10: 60b9 str r1, [r7, #8]
|
|
800ae12: 607a str r2, [r7, #4]
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
800ae14: 68fb ldr r3, [r7, #12]
|
|
800ae16: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
|
|
800ae1a: b2db uxtb r3, r3
|
|
800ae1c: 2b02 cmp r3, #2
|
|
800ae1e: d101 bne.n 800ae24 <HAL_SDRAM_SendCommand+0x1c>
|
|
{
|
|
return HAL_BUSY;
|
|
800ae20: 2302 movs r3, #2
|
|
800ae22: e018 b.n 800ae56 <HAL_SDRAM_SendCommand+0x4e>
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
800ae24: 68fb ldr r3, [r7, #12]
|
|
800ae26: 2202 movs r2, #2
|
|
800ae28: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
/* Send SDRAM command */
|
|
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
|
|
800ae2c: 68fb ldr r3, [r7, #12]
|
|
800ae2e: 681b ldr r3, [r3, #0]
|
|
800ae30: 687a ldr r2, [r7, #4]
|
|
800ae32: 68b9 ldr r1, [r7, #8]
|
|
800ae34: 4618 mov r0, r3
|
|
800ae36: f001 ff29 bl 800cc8c <FMC_SDRAM_SendCommand>
|
|
|
|
/* Update the SDRAM controller state state */
|
|
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
|
|
800ae3a: 68bb ldr r3, [r7, #8]
|
|
800ae3c: 681b ldr r3, [r3, #0]
|
|
800ae3e: 2b02 cmp r3, #2
|
|
800ae40: d104 bne.n 800ae4c <HAL_SDRAM_SendCommand+0x44>
|
|
{
|
|
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
|
|
800ae42: 68fb ldr r3, [r7, #12]
|
|
800ae44: 2205 movs r2, #5
|
|
800ae46: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
800ae4a: e003 b.n 800ae54 <HAL_SDRAM_SendCommand+0x4c>
|
|
}
|
|
else
|
|
{
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
800ae4c: 68fb ldr r3, [r7, #12]
|
|
800ae4e: 2201 movs r2, #1
|
|
800ae50: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
}
|
|
|
|
return HAL_OK;
|
|
800ae54: 2300 movs r3, #0
|
|
}
|
|
800ae56: 4618 mov r0, r3
|
|
800ae58: 3710 adds r7, #16
|
|
800ae5a: 46bd mov sp, r7
|
|
800ae5c: bd80 pop {r7, pc}
|
|
|
|
0800ae5e <HAL_SDRAM_ProgramRefreshRate>:
|
|
* the configuration information for SDRAM module.
|
|
* @param RefreshRate The SDRAM refresh rate value
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
|
|
{
|
|
800ae5e: b580 push {r7, lr}
|
|
800ae60: b082 sub sp, #8
|
|
800ae62: af00 add r7, sp, #0
|
|
800ae64: 6078 str r0, [r7, #4]
|
|
800ae66: 6039 str r1, [r7, #0]
|
|
/* Check the SDRAM controller state */
|
|
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
800ae68: 687b ldr r3, [r7, #4]
|
|
800ae6a: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
|
|
800ae6e: b2db uxtb r3, r3
|
|
800ae70: 2b02 cmp r3, #2
|
|
800ae72: d101 bne.n 800ae78 <HAL_SDRAM_ProgramRefreshRate+0x1a>
|
|
{
|
|
return HAL_BUSY;
|
|
800ae74: 2302 movs r3, #2
|
|
800ae76: e00e b.n 800ae96 <HAL_SDRAM_ProgramRefreshRate+0x38>
|
|
}
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
800ae78: 687b ldr r3, [r7, #4]
|
|
800ae7a: 2202 movs r2, #2
|
|
800ae7c: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
/* Program the refresh rate */
|
|
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
|
|
800ae80: 687b ldr r3, [r7, #4]
|
|
800ae82: 681b ldr r3, [r3, #0]
|
|
800ae84: 6839 ldr r1, [r7, #0]
|
|
800ae86: 4618 mov r0, r3
|
|
800ae88: f001 ff21 bl 800ccce <FMC_SDRAM_ProgramRefreshRate>
|
|
|
|
/* Update the SDRAM state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
800ae8c: 687b ldr r3, [r7, #4]
|
|
800ae8e: 2201 movs r2, #1
|
|
800ae90: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
|
|
return HAL_OK;
|
|
800ae94: 2300 movs r3, #0
|
|
}
|
|
800ae96: 4618 mov r0, r3
|
|
800ae98: 3708 adds r7, #8
|
|
800ae9a: 46bd mov sp, r7
|
|
800ae9c: bd80 pop {r7, pc}
|
|
|
|
0800ae9e <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
800ae9e: b580 push {r7, lr}
|
|
800aea0: b084 sub sp, #16
|
|
800aea2: af00 add r7, sp, #0
|
|
800aea4: 6078 str r0, [r7, #4]
|
|
uint32_t frxth;
|
|
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
800aea6: 687b ldr r3, [r7, #4]
|
|
800aea8: 2b00 cmp r3, #0
|
|
800aeaa: d101 bne.n 800aeb0 <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800aeac: 2301 movs r3, #1
|
|
800aeae: e084 b.n 800afba <HAL_SPI_Init+0x11c>
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800aeb0: 687b ldr r3, [r7, #4]
|
|
800aeb2: 2200 movs r2, #0
|
|
800aeb4: 629a str r2, [r3, #40] ; 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
800aeb6: 687b ldr r3, [r7, #4]
|
|
800aeb8: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
|
|
800aebc: b2db uxtb r3, r3
|
|
800aebe: 2b00 cmp r3, #0
|
|
800aec0: d106 bne.n 800aed0 <HAL_SPI_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
800aec2: 687b ldr r3, [r7, #4]
|
|
800aec4: 2200 movs r2, #0
|
|
800aec6: f883 205c strb.w r2, [r3, #92] ; 0x5c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
800aeca: 6878 ldr r0, [r7, #4]
|
|
800aecc: f7f9 fdd4 bl 8004a78 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
800aed0: 687b ldr r3, [r7, #4]
|
|
800aed2: 2202 movs r2, #2
|
|
800aed4: f883 205d strb.w r2, [r3, #93] ; 0x5d
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
800aed8: 687b ldr r3, [r7, #4]
|
|
800aeda: 681b ldr r3, [r3, #0]
|
|
800aedc: 681a ldr r2, [r3, #0]
|
|
800aede: 687b ldr r3, [r7, #4]
|
|
800aee0: 681b ldr r3, [r3, #0]
|
|
800aee2: f022 0240 bic.w r2, r2, #64 ; 0x40
|
|
800aee6: 601a str r2, [r3, #0]
|
|
|
|
/* Align by default the rs fifo threshold on the data size */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800aee8: 687b ldr r3, [r7, #4]
|
|
800aeea: 68db ldr r3, [r3, #12]
|
|
800aeec: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
|
|
800aef0: d902 bls.n 800aef8 <HAL_SPI_Init+0x5a>
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_HF;
|
|
800aef2: 2300 movs r3, #0
|
|
800aef4: 60fb str r3, [r7, #12]
|
|
800aef6: e002 b.n 800aefe <HAL_SPI_Init+0x60>
|
|
}
|
|
else
|
|
{
|
|
frxth = SPI_RXFIFO_THRESHOLD_QF;
|
|
800aef8: f44f 5380 mov.w r3, #4096 ; 0x1000
|
|
800aefc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* CRC calculation is valid only for 16Bit and 8 Bit */
|
|
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
|
|
800aefe: 687b ldr r3, [r7, #4]
|
|
800af00: 68db ldr r3, [r3, #12]
|
|
800af02: f5b3 6f70 cmp.w r3, #3840 ; 0xf00
|
|
800af06: d007 beq.n 800af18 <HAL_SPI_Init+0x7a>
|
|
800af08: 687b ldr r3, [r7, #4]
|
|
800af0a: 68db ldr r3, [r3, #12]
|
|
800af0c: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
|
|
800af10: d002 beq.n 800af18 <HAL_SPI_Init+0x7a>
|
|
{
|
|
/* CRC must be disabled */
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
800af12: 687b ldr r3, [r7, #4]
|
|
800af14: 2200 movs r2, #0
|
|
800af16: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
/* Align the CRC Length on the data size */
|
|
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
|
|
800af18: 687b ldr r3, [r7, #4]
|
|
800af1a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800af1c: 2b00 cmp r3, #0
|
|
800af1e: d10b bne.n 800af38 <HAL_SPI_Init+0x9a>
|
|
{
|
|
/* CRC Length aligned on the data size : value set by default */
|
|
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
|
|
800af20: 687b ldr r3, [r7, #4]
|
|
800af22: 68db ldr r3, [r3, #12]
|
|
800af24: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
|
|
800af28: d903 bls.n 800af32 <HAL_SPI_Init+0x94>
|
|
{
|
|
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
|
|
800af2a: 687b ldr r3, [r7, #4]
|
|
800af2c: 2202 movs r2, #2
|
|
800af2e: 631a str r2, [r3, #48] ; 0x30
|
|
800af30: e002 b.n 800af38 <HAL_SPI_Init+0x9a>
|
|
}
|
|
else
|
|
{
|
|
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
|
|
800af32: 687b ldr r3, [r7, #4]
|
|
800af34: 2201 movs r2, #1
|
|
800af36: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
|
|
800af38: 687b ldr r3, [r7, #4]
|
|
800af3a: 685a ldr r2, [r3, #4]
|
|
800af3c: 687b ldr r3, [r7, #4]
|
|
800af3e: 689b ldr r3, [r3, #8]
|
|
800af40: 431a orrs r2, r3
|
|
800af42: 687b ldr r3, [r7, #4]
|
|
800af44: 691b ldr r3, [r3, #16]
|
|
800af46: 431a orrs r2, r3
|
|
800af48: 687b ldr r3, [r7, #4]
|
|
800af4a: 695b ldr r3, [r3, #20]
|
|
800af4c: 431a orrs r2, r3
|
|
800af4e: 687b ldr r3, [r7, #4]
|
|
800af50: 699b ldr r3, [r3, #24]
|
|
800af52: f403 7300 and.w r3, r3, #512 ; 0x200
|
|
800af56: 431a orrs r2, r3
|
|
800af58: 687b ldr r3, [r7, #4]
|
|
800af5a: 69db ldr r3, [r3, #28]
|
|
800af5c: 431a orrs r2, r3
|
|
800af5e: 687b ldr r3, [r7, #4]
|
|
800af60: 6a1b ldr r3, [r3, #32]
|
|
800af62: ea42 0103 orr.w r1, r2, r3
|
|
800af66: 687b ldr r3, [r7, #4]
|
|
800af68: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
800af6a: 687b ldr r3, [r7, #4]
|
|
800af6c: 681b ldr r3, [r3, #0]
|
|
800af6e: 430a orrs r2, r1
|
|
800af70: 601a str r2, [r3, #0]
|
|
hspi->Instance->CR1 |= SPI_CR1_CRCL;
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
|
|
800af72: 687b ldr r3, [r7, #4]
|
|
800af74: 699b ldr r3, [r3, #24]
|
|
800af76: 0c1b lsrs r3, r3, #16
|
|
800af78: f003 0204 and.w r2, r3, #4
|
|
800af7c: 687b ldr r3, [r7, #4]
|
|
800af7e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800af80: 431a orrs r2, r3
|
|
800af82: 687b ldr r3, [r7, #4]
|
|
800af84: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
800af86: 431a orrs r2, r3
|
|
800af88: 687b ldr r3, [r7, #4]
|
|
800af8a: 68db ldr r3, [r3, #12]
|
|
800af8c: ea42 0103 orr.w r1, r2, r3
|
|
800af90: 687b ldr r3, [r7, #4]
|
|
800af92: 681b ldr r3, [r3, #0]
|
|
800af94: 68fa ldr r2, [r7, #12]
|
|
800af96: 430a orrs r2, r1
|
|
800af98: 605a str r2, [r3, #4]
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
800af9a: 687b ldr r3, [r7, #4]
|
|
800af9c: 681b ldr r3, [r3, #0]
|
|
800af9e: 69da ldr r2, [r3, #28]
|
|
800afa0: 687b ldr r3, [r7, #4]
|
|
800afa2: 681b ldr r3, [r3, #0]
|
|
800afa4: f422 6200 bic.w r2, r2, #2048 ; 0x800
|
|
800afa8: 61da str r2, [r3, #28]
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
800afaa: 687b ldr r3, [r7, #4]
|
|
800afac: 2200 movs r2, #0
|
|
800afae: 661a str r2, [r3, #96] ; 0x60
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
800afb0: 687b ldr r3, [r7, #4]
|
|
800afb2: 2201 movs r2, #1
|
|
800afb4: f883 205d strb.w r2, [r3, #93] ; 0x5d
|
|
|
|
return HAL_OK;
|
|
800afb8: 2300 movs r3, #0
|
|
}
|
|
800afba: 4618 mov r0, r3
|
|
800afbc: 3710 adds r7, #16
|
|
800afbe: 46bd mov sp, r7
|
|
800afc0: bd80 pop {r7, pc}
|
|
|
|
0800afc2 <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800afc2: b580 push {r7, lr}
|
|
800afc4: b082 sub sp, #8
|
|
800afc6: af00 add r7, sp, #0
|
|
800afc8: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800afca: 687b ldr r3, [r7, #4]
|
|
800afcc: 2b00 cmp r3, #0
|
|
800afce: d101 bne.n 800afd4 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800afd0: 2301 movs r3, #1
|
|
800afd2: e01d b.n 800b010 <HAL_TIM_Base_Init+0x4e>
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800afd4: 687b ldr r3, [r7, #4]
|
|
800afd6: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
800afda: b2db uxtb r3, r3
|
|
800afdc: 2b00 cmp r3, #0
|
|
800afde: d106 bne.n 800afee <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800afe0: 687b ldr r3, [r7, #4]
|
|
800afe2: 2200 movs r2, #0
|
|
800afe4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
800afe8: 6878 ldr r0, [r7, #4]
|
|
800afea: f7f9 fdb7 bl 8004b5c <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800afee: 687b ldr r3, [r7, #4]
|
|
800aff0: 2202 movs r2, #2
|
|
800aff2: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800aff6: 687b ldr r3, [r7, #4]
|
|
800aff8: 681a ldr r2, [r3, #0]
|
|
800affa: 687b ldr r3, [r7, #4]
|
|
800affc: 3304 adds r3, #4
|
|
800affe: 4619 mov r1, r3
|
|
800b000: 4610 mov r0, r2
|
|
800b002: f000 fbc3 bl 800b78c <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b006: 687b ldr r3, [r7, #4]
|
|
800b008: 2201 movs r2, #1
|
|
800b00a: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
800b00e: 2300 movs r3, #0
|
|
}
|
|
800b010: 4618 mov r0, r3
|
|
800b012: 3708 adds r7, #8
|
|
800b014: 46bd mov sp, r7
|
|
800b016: bd80 pop {r7, pc}
|
|
|
|
0800b018 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b018: b480 push {r7}
|
|
800b01a: b085 sub sp, #20
|
|
800b01c: af00 add r7, sp, #0
|
|
800b01e: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
800b020: 687b ldr r3, [r7, #4]
|
|
800b022: 681b ldr r3, [r3, #0]
|
|
800b024: 68da ldr r2, [r3, #12]
|
|
800b026: 687b ldr r3, [r7, #4]
|
|
800b028: 681b ldr r3, [r3, #0]
|
|
800b02a: f042 0201 orr.w r2, r2, #1
|
|
800b02e: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
800b030: 687b ldr r3, [r7, #4]
|
|
800b032: 681b ldr r3, [r3, #0]
|
|
800b034: 689a ldr r2, [r3, #8]
|
|
800b036: 4b0c ldr r3, [pc, #48] ; (800b068 <HAL_TIM_Base_Start_IT+0x50>)
|
|
800b038: 4013 ands r3, r2
|
|
800b03a: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800b03c: 68fb ldr r3, [r7, #12]
|
|
800b03e: 2b06 cmp r3, #6
|
|
800b040: d00b beq.n 800b05a <HAL_TIM_Base_Start_IT+0x42>
|
|
800b042: 68fb ldr r3, [r7, #12]
|
|
800b044: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800b048: d007 beq.n 800b05a <HAL_TIM_Base_Start_IT+0x42>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800b04a: 687b ldr r3, [r7, #4]
|
|
800b04c: 681b ldr r3, [r3, #0]
|
|
800b04e: 681a ldr r2, [r3, #0]
|
|
800b050: 687b ldr r3, [r7, #4]
|
|
800b052: 681b ldr r3, [r3, #0]
|
|
800b054: f042 0201 orr.w r2, r2, #1
|
|
800b058: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800b05a: 2300 movs r3, #0
|
|
}
|
|
800b05c: 4618 mov r0, r3
|
|
800b05e: 3714 adds r7, #20
|
|
800b060: 46bd mov sp, r7
|
|
800b062: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b066: 4770 bx lr
|
|
800b068: 00010007 .word 0x00010007
|
|
|
|
0800b06c <HAL_TIM_PWM_Init>:
|
|
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
|
|
* @param htim TIM PWM handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b06c: b580 push {r7, lr}
|
|
800b06e: b082 sub sp, #8
|
|
800b070: af00 add r7, sp, #0
|
|
800b072: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
800b074: 687b ldr r3, [r7, #4]
|
|
800b076: 2b00 cmp r3, #0
|
|
800b078: d101 bne.n 800b07e <HAL_TIM_PWM_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800b07a: 2301 movs r3, #1
|
|
800b07c: e01d b.n 800b0ba <HAL_TIM_PWM_Init+0x4e>
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800b07e: 687b ldr r3, [r7, #4]
|
|
800b080: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
|
|
800b084: b2db uxtb r3, r3
|
|
800b086: 2b00 cmp r3, #0
|
|
800b088: d106 bne.n 800b098 <HAL_TIM_PWM_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
800b08a: 687b ldr r3, [r7, #4]
|
|
800b08c: 2200 movs r2, #0
|
|
800b08e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->PWM_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
800b092: 6878 ldr r0, [r7, #4]
|
|
800b094: f000 f815 bl 800b0c2 <HAL_TIM_PWM_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800b098: 687b ldr r3, [r7, #4]
|
|
800b09a: 2202 movs r2, #2
|
|
800b09c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Init the base time for the PWM */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800b0a0: 687b ldr r3, [r7, #4]
|
|
800b0a2: 681a ldr r2, [r3, #0]
|
|
800b0a4: 687b ldr r3, [r7, #4]
|
|
800b0a6: 3304 adds r3, #4
|
|
800b0a8: 4619 mov r1, r3
|
|
800b0aa: 4610 mov r0, r2
|
|
800b0ac: f000 fb6e bl 800b78c <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b0b0: 687b ldr r3, [r7, #4]
|
|
800b0b2: 2201 movs r2, #1
|
|
800b0b4: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
return HAL_OK;
|
|
800b0b8: 2300 movs r3, #0
|
|
}
|
|
800b0ba: 4618 mov r0, r3
|
|
800b0bc: 3708 adds r7, #8
|
|
800b0be: 46bd mov sp, r7
|
|
800b0c0: bd80 pop {r7, pc}
|
|
|
|
0800b0c2 <HAL_TIM_PWM_MspInit>:
|
|
* @brief Initializes the TIM PWM MSP.
|
|
* @param htim TIM PWM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b0c2: b480 push {r7}
|
|
800b0c4: b083 sub sp, #12
|
|
800b0c6: af00 add r7, sp, #0
|
|
800b0c8: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_MspInit could be implemented in the user file
|
|
*/
|
|
}
|
|
800b0ca: bf00 nop
|
|
800b0cc: 370c adds r7, #12
|
|
800b0ce: 46bd mov sp, r7
|
|
800b0d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b0d4: 4770 bx lr
|
|
|
|
0800b0d6 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b0d6: b580 push {r7, lr}
|
|
800b0d8: b082 sub sp, #8
|
|
800b0da: af00 add r7, sp, #0
|
|
800b0dc: 6078 str r0, [r7, #4]
|
|
/* Capture compare 1 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
|
800b0de: 687b ldr r3, [r7, #4]
|
|
800b0e0: 681b ldr r3, [r3, #0]
|
|
800b0e2: 691b ldr r3, [r3, #16]
|
|
800b0e4: f003 0302 and.w r3, r3, #2
|
|
800b0e8: 2b02 cmp r3, #2
|
|
800b0ea: d122 bne.n 800b132 <HAL_TIM_IRQHandler+0x5c>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
|
|
800b0ec: 687b ldr r3, [r7, #4]
|
|
800b0ee: 681b ldr r3, [r3, #0]
|
|
800b0f0: 68db ldr r3, [r3, #12]
|
|
800b0f2: f003 0302 and.w r3, r3, #2
|
|
800b0f6: 2b02 cmp r3, #2
|
|
800b0f8: d11b bne.n 800b132 <HAL_TIM_IRQHandler+0x5c>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
|
800b0fa: 687b ldr r3, [r7, #4]
|
|
800b0fc: 681b ldr r3, [r3, #0]
|
|
800b0fe: f06f 0202 mvn.w r2, #2
|
|
800b102: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
800b104: 687b ldr r3, [r7, #4]
|
|
800b106: 2201 movs r2, #1
|
|
800b108: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
800b10a: 687b ldr r3, [r7, #4]
|
|
800b10c: 681b ldr r3, [r3, #0]
|
|
800b10e: 699b ldr r3, [r3, #24]
|
|
800b110: f003 0303 and.w r3, r3, #3
|
|
800b114: 2b00 cmp r3, #0
|
|
800b116: d003 beq.n 800b120 <HAL_TIM_IRQHandler+0x4a>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800b118: 6878 ldr r0, [r7, #4]
|
|
800b11a: f000 fb19 bl 800b750 <HAL_TIM_IC_CaptureCallback>
|
|
800b11e: e005 b.n 800b12c <HAL_TIM_IRQHandler+0x56>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800b120: 6878 ldr r0, [r7, #4]
|
|
800b122: f000 fb0b bl 800b73c <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800b126: 6878 ldr r0, [r7, #4]
|
|
800b128: f000 fb1c bl 800b764 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800b12c: 687b ldr r3, [r7, #4]
|
|
800b12e: 2200 movs r2, #0
|
|
800b130: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
|
800b132: 687b ldr r3, [r7, #4]
|
|
800b134: 681b ldr r3, [r3, #0]
|
|
800b136: 691b ldr r3, [r3, #16]
|
|
800b138: f003 0304 and.w r3, r3, #4
|
|
800b13c: 2b04 cmp r3, #4
|
|
800b13e: d122 bne.n 800b186 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
|
|
800b140: 687b ldr r3, [r7, #4]
|
|
800b142: 681b ldr r3, [r3, #0]
|
|
800b144: 68db ldr r3, [r3, #12]
|
|
800b146: f003 0304 and.w r3, r3, #4
|
|
800b14a: 2b04 cmp r3, #4
|
|
800b14c: d11b bne.n 800b186 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
|
800b14e: 687b ldr r3, [r7, #4]
|
|
800b150: 681b ldr r3, [r3, #0]
|
|
800b152: f06f 0204 mvn.w r2, #4
|
|
800b156: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800b158: 687b ldr r3, [r7, #4]
|
|
800b15a: 2202 movs r2, #2
|
|
800b15c: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
800b15e: 687b ldr r3, [r7, #4]
|
|
800b160: 681b ldr r3, [r3, #0]
|
|
800b162: 699b ldr r3, [r3, #24]
|
|
800b164: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
800b168: 2b00 cmp r3, #0
|
|
800b16a: d003 beq.n 800b174 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800b16c: 6878 ldr r0, [r7, #4]
|
|
800b16e: f000 faef bl 800b750 <HAL_TIM_IC_CaptureCallback>
|
|
800b172: e005 b.n 800b180 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800b174: 6878 ldr r0, [r7, #4]
|
|
800b176: f000 fae1 bl 800b73c <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800b17a: 6878 ldr r0, [r7, #4]
|
|
800b17c: f000 faf2 bl 800b764 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800b180: 687b ldr r3, [r7, #4]
|
|
800b182: 2200 movs r2, #0
|
|
800b184: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
|
800b186: 687b ldr r3, [r7, #4]
|
|
800b188: 681b ldr r3, [r3, #0]
|
|
800b18a: 691b ldr r3, [r3, #16]
|
|
800b18c: f003 0308 and.w r3, r3, #8
|
|
800b190: 2b08 cmp r3, #8
|
|
800b192: d122 bne.n 800b1da <HAL_TIM_IRQHandler+0x104>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
|
|
800b194: 687b ldr r3, [r7, #4]
|
|
800b196: 681b ldr r3, [r3, #0]
|
|
800b198: 68db ldr r3, [r3, #12]
|
|
800b19a: f003 0308 and.w r3, r3, #8
|
|
800b19e: 2b08 cmp r3, #8
|
|
800b1a0: d11b bne.n 800b1da <HAL_TIM_IRQHandler+0x104>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
|
800b1a2: 687b ldr r3, [r7, #4]
|
|
800b1a4: 681b ldr r3, [r3, #0]
|
|
800b1a6: f06f 0208 mvn.w r2, #8
|
|
800b1aa: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
800b1ac: 687b ldr r3, [r7, #4]
|
|
800b1ae: 2204 movs r2, #4
|
|
800b1b0: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
800b1b2: 687b ldr r3, [r7, #4]
|
|
800b1b4: 681b ldr r3, [r3, #0]
|
|
800b1b6: 69db ldr r3, [r3, #28]
|
|
800b1b8: f003 0303 and.w r3, r3, #3
|
|
800b1bc: 2b00 cmp r3, #0
|
|
800b1be: d003 beq.n 800b1c8 <HAL_TIM_IRQHandler+0xf2>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800b1c0: 6878 ldr r0, [r7, #4]
|
|
800b1c2: f000 fac5 bl 800b750 <HAL_TIM_IC_CaptureCallback>
|
|
800b1c6: e005 b.n 800b1d4 <HAL_TIM_IRQHandler+0xfe>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800b1c8: 6878 ldr r0, [r7, #4]
|
|
800b1ca: f000 fab7 bl 800b73c <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800b1ce: 6878 ldr r0, [r7, #4]
|
|
800b1d0: f000 fac8 bl 800b764 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800b1d4: 687b ldr r3, [r7, #4]
|
|
800b1d6: 2200 movs r2, #0
|
|
800b1d8: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
|
800b1da: 687b ldr r3, [r7, #4]
|
|
800b1dc: 681b ldr r3, [r3, #0]
|
|
800b1de: 691b ldr r3, [r3, #16]
|
|
800b1e0: f003 0310 and.w r3, r3, #16
|
|
800b1e4: 2b10 cmp r3, #16
|
|
800b1e6: d122 bne.n 800b22e <HAL_TIM_IRQHandler+0x158>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
|
|
800b1e8: 687b ldr r3, [r7, #4]
|
|
800b1ea: 681b ldr r3, [r3, #0]
|
|
800b1ec: 68db ldr r3, [r3, #12]
|
|
800b1ee: f003 0310 and.w r3, r3, #16
|
|
800b1f2: 2b10 cmp r3, #16
|
|
800b1f4: d11b bne.n 800b22e <HAL_TIM_IRQHandler+0x158>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
|
800b1f6: 687b ldr r3, [r7, #4]
|
|
800b1f8: 681b ldr r3, [r3, #0]
|
|
800b1fa: f06f 0210 mvn.w r2, #16
|
|
800b1fe: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
800b200: 687b ldr r3, [r7, #4]
|
|
800b202: 2208 movs r2, #8
|
|
800b204: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
800b206: 687b ldr r3, [r7, #4]
|
|
800b208: 681b ldr r3, [r3, #0]
|
|
800b20a: 69db ldr r3, [r3, #28]
|
|
800b20c: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
800b210: 2b00 cmp r3, #0
|
|
800b212: d003 beq.n 800b21c <HAL_TIM_IRQHandler+0x146>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800b214: 6878 ldr r0, [r7, #4]
|
|
800b216: f000 fa9b bl 800b750 <HAL_TIM_IC_CaptureCallback>
|
|
800b21a: e005 b.n 800b228 <HAL_TIM_IRQHandler+0x152>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800b21c: 6878 ldr r0, [r7, #4]
|
|
800b21e: f000 fa8d bl 800b73c <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800b222: 6878 ldr r0, [r7, #4]
|
|
800b224: f000 fa9e bl 800b764 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800b228: 687b ldr r3, [r7, #4]
|
|
800b22a: 2200 movs r2, #0
|
|
800b22c: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
|
800b22e: 687b ldr r3, [r7, #4]
|
|
800b230: 681b ldr r3, [r3, #0]
|
|
800b232: 691b ldr r3, [r3, #16]
|
|
800b234: f003 0301 and.w r3, r3, #1
|
|
800b238: 2b01 cmp r3, #1
|
|
800b23a: d10e bne.n 800b25a <HAL_TIM_IRQHandler+0x184>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
|
|
800b23c: 687b ldr r3, [r7, #4]
|
|
800b23e: 681b ldr r3, [r3, #0]
|
|
800b240: 68db ldr r3, [r3, #12]
|
|
800b242: f003 0301 and.w r3, r3, #1
|
|
800b246: 2b01 cmp r3, #1
|
|
800b248: d107 bne.n 800b25a <HAL_TIM_IRQHandler+0x184>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
|
800b24a: 687b ldr r3, [r7, #4]
|
|
800b24c: 681b ldr r3, [r3, #0]
|
|
800b24e: f06f 0201 mvn.w r2, #1
|
|
800b252: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
800b254: 6878 ldr r0, [r7, #4]
|
|
800b256: f7f7 fafd bl 8002854 <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
|
800b25a: 687b ldr r3, [r7, #4]
|
|
800b25c: 681b ldr r3, [r3, #0]
|
|
800b25e: 691b ldr r3, [r3, #16]
|
|
800b260: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800b264: 2b80 cmp r3, #128 ; 0x80
|
|
800b266: d10e bne.n 800b286 <HAL_TIM_IRQHandler+0x1b0>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
|
800b268: 687b ldr r3, [r7, #4]
|
|
800b26a: 681b ldr r3, [r3, #0]
|
|
800b26c: 68db ldr r3, [r3, #12]
|
|
800b26e: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800b272: 2b80 cmp r3, #128 ; 0x80
|
|
800b274: d107 bne.n 800b286 <HAL_TIM_IRQHandler+0x1b0>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
|
800b276: 687b ldr r3, [r7, #4]
|
|
800b278: 681b ldr r3, [r3, #0]
|
|
800b27a: f06f 0280 mvn.w r2, #128 ; 0x80
|
|
800b27e: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
800b280: 6878 ldr r0, [r7, #4]
|
|
800b282: f000 ffb9 bl 800c1f8 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break2 input event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
|
|
800b286: 687b ldr r3, [r7, #4]
|
|
800b288: 681b ldr r3, [r3, #0]
|
|
800b28a: 691b ldr r3, [r3, #16]
|
|
800b28c: f403 7380 and.w r3, r3, #256 ; 0x100
|
|
800b290: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
800b294: d10e bne.n 800b2b4 <HAL_TIM_IRQHandler+0x1de>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
|
800b296: 687b ldr r3, [r7, #4]
|
|
800b298: 681b ldr r3, [r3, #0]
|
|
800b29a: 68db ldr r3, [r3, #12]
|
|
800b29c: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800b2a0: 2b80 cmp r3, #128 ; 0x80
|
|
800b2a2: d107 bne.n 800b2b4 <HAL_TIM_IRQHandler+0x1de>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
800b2a4: 687b ldr r3, [r7, #4]
|
|
800b2a6: 681b ldr r3, [r3, #0]
|
|
800b2a8: f46f 7280 mvn.w r2, #256 ; 0x100
|
|
800b2ac: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->Break2Callback(htim);
|
|
#else
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
800b2ae: 6878 ldr r0, [r7, #4]
|
|
800b2b0: f000 ffac bl 800c20c <HAL_TIMEx_Break2Callback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
|
800b2b4: 687b ldr r3, [r7, #4]
|
|
800b2b6: 681b ldr r3, [r3, #0]
|
|
800b2b8: 691b ldr r3, [r3, #16]
|
|
800b2ba: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800b2be: 2b40 cmp r3, #64 ; 0x40
|
|
800b2c0: d10e bne.n 800b2e0 <HAL_TIM_IRQHandler+0x20a>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
|
|
800b2c2: 687b ldr r3, [r7, #4]
|
|
800b2c4: 681b ldr r3, [r3, #0]
|
|
800b2c6: 68db ldr r3, [r3, #12]
|
|
800b2c8: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800b2cc: 2b40 cmp r3, #64 ; 0x40
|
|
800b2ce: d107 bne.n 800b2e0 <HAL_TIM_IRQHandler+0x20a>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
|
800b2d0: 687b ldr r3, [r7, #4]
|
|
800b2d2: 681b ldr r3, [r3, #0]
|
|
800b2d4: f06f 0240 mvn.w r2, #64 ; 0x40
|
|
800b2d8: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
800b2da: 6878 ldr r0, [r7, #4]
|
|
800b2dc: f000 fa4c bl 800b778 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
|
800b2e0: 687b ldr r3, [r7, #4]
|
|
800b2e2: 681b ldr r3, [r3, #0]
|
|
800b2e4: 691b ldr r3, [r3, #16]
|
|
800b2e6: f003 0320 and.w r3, r3, #32
|
|
800b2ea: 2b20 cmp r3, #32
|
|
800b2ec: d10e bne.n 800b30c <HAL_TIM_IRQHandler+0x236>
|
|
{
|
|
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
|
|
800b2ee: 687b ldr r3, [r7, #4]
|
|
800b2f0: 681b ldr r3, [r3, #0]
|
|
800b2f2: 68db ldr r3, [r3, #12]
|
|
800b2f4: f003 0320 and.w r3, r3, #32
|
|
800b2f8: 2b20 cmp r3, #32
|
|
800b2fa: d107 bne.n 800b30c <HAL_TIM_IRQHandler+0x236>
|
|
{
|
|
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
|
800b2fc: 687b ldr r3, [r7, #4]
|
|
800b2fe: 681b ldr r3, [r3, #0]
|
|
800b300: f06f 0220 mvn.w r2, #32
|
|
800b304: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
800b306: 6878 ldr r0, [r7, #4]
|
|
800b308: f000 ff6c bl 800c1e4 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
800b30c: bf00 nop
|
|
800b30e: 3708 adds r7, #8
|
|
800b310: 46bd mov sp, r7
|
|
800b312: bd80 pop {r7, pc}
|
|
|
|
0800b314 <HAL_TIM_PWM_ConfigChannel>:
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
|
|
TIM_OC_InitTypeDef *sConfig,
|
|
uint32_t Channel)
|
|
{
|
|
800b314: b580 push {r7, lr}
|
|
800b316: b084 sub sp, #16
|
|
800b318: af00 add r7, sp, #0
|
|
800b31a: 60f8 str r0, [r7, #12]
|
|
800b31c: 60b9 str r1, [r7, #8]
|
|
800b31e: 607a str r2, [r7, #4]
|
|
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
|
|
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
|
|
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
800b320: 68fb ldr r3, [r7, #12]
|
|
800b322: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800b326: 2b01 cmp r3, #1
|
|
800b328: d101 bne.n 800b32e <HAL_TIM_PWM_ConfigChannel+0x1a>
|
|
800b32a: 2302 movs r3, #2
|
|
800b32c: e105 b.n 800b53a <HAL_TIM_PWM_ConfigChannel+0x226>
|
|
800b32e: 68fb ldr r3, [r7, #12]
|
|
800b330: 2201 movs r2, #1
|
|
800b332: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800b336: 68fb ldr r3, [r7, #12]
|
|
800b338: 2202 movs r2, #2
|
|
800b33a: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
switch (Channel)
|
|
800b33e: 687b ldr r3, [r7, #4]
|
|
800b340: 2b14 cmp r3, #20
|
|
800b342: f200 80f0 bhi.w 800b526 <HAL_TIM_PWM_ConfigChannel+0x212>
|
|
800b346: a201 add r2, pc, #4 ; (adr r2, 800b34c <HAL_TIM_PWM_ConfigChannel+0x38>)
|
|
800b348: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800b34c: 0800b3a1 .word 0x0800b3a1
|
|
800b350: 0800b527 .word 0x0800b527
|
|
800b354: 0800b527 .word 0x0800b527
|
|
800b358: 0800b527 .word 0x0800b527
|
|
800b35c: 0800b3e1 .word 0x0800b3e1
|
|
800b360: 0800b527 .word 0x0800b527
|
|
800b364: 0800b527 .word 0x0800b527
|
|
800b368: 0800b527 .word 0x0800b527
|
|
800b36c: 0800b423 .word 0x0800b423
|
|
800b370: 0800b527 .word 0x0800b527
|
|
800b374: 0800b527 .word 0x0800b527
|
|
800b378: 0800b527 .word 0x0800b527
|
|
800b37c: 0800b463 .word 0x0800b463
|
|
800b380: 0800b527 .word 0x0800b527
|
|
800b384: 0800b527 .word 0x0800b527
|
|
800b388: 0800b527 .word 0x0800b527
|
|
800b38c: 0800b4a5 .word 0x0800b4a5
|
|
800b390: 0800b527 .word 0x0800b527
|
|
800b394: 0800b527 .word 0x0800b527
|
|
800b398: 0800b527 .word 0x0800b527
|
|
800b39c: 0800b4e5 .word 0x0800b4e5
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 1 in PWM mode */
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
800b3a0: 68fb ldr r3, [r7, #12]
|
|
800b3a2: 681b ldr r3, [r3, #0]
|
|
800b3a4: 68b9 ldr r1, [r7, #8]
|
|
800b3a6: 4618 mov r0, r3
|
|
800b3a8: f000 fa90 bl 800b8cc <TIM_OC1_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel1 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
800b3ac: 68fb ldr r3, [r7, #12]
|
|
800b3ae: 681b ldr r3, [r3, #0]
|
|
800b3b0: 699a ldr r2, [r3, #24]
|
|
800b3b2: 68fb ldr r3, [r7, #12]
|
|
800b3b4: 681b ldr r3, [r3, #0]
|
|
800b3b6: f042 0208 orr.w r2, r2, #8
|
|
800b3ba: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
800b3bc: 68fb ldr r3, [r7, #12]
|
|
800b3be: 681b ldr r3, [r3, #0]
|
|
800b3c0: 699a ldr r2, [r3, #24]
|
|
800b3c2: 68fb ldr r3, [r7, #12]
|
|
800b3c4: 681b ldr r3, [r3, #0]
|
|
800b3c6: f022 0204 bic.w r2, r2, #4
|
|
800b3ca: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
800b3cc: 68fb ldr r3, [r7, #12]
|
|
800b3ce: 681b ldr r3, [r3, #0]
|
|
800b3d0: 6999 ldr r1, [r3, #24]
|
|
800b3d2: 68bb ldr r3, [r7, #8]
|
|
800b3d4: 691a ldr r2, [r3, #16]
|
|
800b3d6: 68fb ldr r3, [r7, #12]
|
|
800b3d8: 681b ldr r3, [r3, #0]
|
|
800b3da: 430a orrs r2, r1
|
|
800b3dc: 619a str r2, [r3, #24]
|
|
break;
|
|
800b3de: e0a3 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 2 in PWM mode */
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
800b3e0: 68fb ldr r3, [r7, #12]
|
|
800b3e2: 681b ldr r3, [r3, #0]
|
|
800b3e4: 68b9 ldr r1, [r7, #8]
|
|
800b3e6: 4618 mov r0, r3
|
|
800b3e8: f000 fae2 bl 800b9b0 <TIM_OC2_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel2 */
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
800b3ec: 68fb ldr r3, [r7, #12]
|
|
800b3ee: 681b ldr r3, [r3, #0]
|
|
800b3f0: 699a ldr r2, [r3, #24]
|
|
800b3f2: 68fb ldr r3, [r7, #12]
|
|
800b3f4: 681b ldr r3, [r3, #0]
|
|
800b3f6: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800b3fa: 619a str r2, [r3, #24]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
800b3fc: 68fb ldr r3, [r7, #12]
|
|
800b3fe: 681b ldr r3, [r3, #0]
|
|
800b400: 699a ldr r2, [r3, #24]
|
|
800b402: 68fb ldr r3, [r7, #12]
|
|
800b404: 681b ldr r3, [r3, #0]
|
|
800b406: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800b40a: 619a str r2, [r3, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
800b40c: 68fb ldr r3, [r7, #12]
|
|
800b40e: 681b ldr r3, [r3, #0]
|
|
800b410: 6999 ldr r1, [r3, #24]
|
|
800b412: 68bb ldr r3, [r7, #8]
|
|
800b414: 691b ldr r3, [r3, #16]
|
|
800b416: 021a lsls r2, r3, #8
|
|
800b418: 68fb ldr r3, [r7, #12]
|
|
800b41a: 681b ldr r3, [r3, #0]
|
|
800b41c: 430a orrs r2, r1
|
|
800b41e: 619a str r2, [r3, #24]
|
|
break;
|
|
800b420: e082 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 3 in PWM mode */
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
800b422: 68fb ldr r3, [r7, #12]
|
|
800b424: 681b ldr r3, [r3, #0]
|
|
800b426: 68b9 ldr r1, [r7, #8]
|
|
800b428: 4618 mov r0, r3
|
|
800b42a: f000 fb39 bl 800baa0 <TIM_OC3_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel3 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
800b42e: 68fb ldr r3, [r7, #12]
|
|
800b430: 681b ldr r3, [r3, #0]
|
|
800b432: 69da ldr r2, [r3, #28]
|
|
800b434: 68fb ldr r3, [r7, #12]
|
|
800b436: 681b ldr r3, [r3, #0]
|
|
800b438: f042 0208 orr.w r2, r2, #8
|
|
800b43c: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
800b43e: 68fb ldr r3, [r7, #12]
|
|
800b440: 681b ldr r3, [r3, #0]
|
|
800b442: 69da ldr r2, [r3, #28]
|
|
800b444: 68fb ldr r3, [r7, #12]
|
|
800b446: 681b ldr r3, [r3, #0]
|
|
800b448: f022 0204 bic.w r2, r2, #4
|
|
800b44c: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
800b44e: 68fb ldr r3, [r7, #12]
|
|
800b450: 681b ldr r3, [r3, #0]
|
|
800b452: 69d9 ldr r1, [r3, #28]
|
|
800b454: 68bb ldr r3, [r7, #8]
|
|
800b456: 691a ldr r2, [r3, #16]
|
|
800b458: 68fb ldr r3, [r7, #12]
|
|
800b45a: 681b ldr r3, [r3, #0]
|
|
800b45c: 430a orrs r2, r1
|
|
800b45e: 61da str r2, [r3, #28]
|
|
break;
|
|
800b460: e062 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 4 in PWM mode */
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
800b462: 68fb ldr r3, [r7, #12]
|
|
800b464: 681b ldr r3, [r3, #0]
|
|
800b466: 68b9 ldr r1, [r7, #8]
|
|
800b468: 4618 mov r0, r3
|
|
800b46a: f000 fb8f bl 800bb8c <TIM_OC4_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel4 */
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
800b46e: 68fb ldr r3, [r7, #12]
|
|
800b470: 681b ldr r3, [r3, #0]
|
|
800b472: 69da ldr r2, [r3, #28]
|
|
800b474: 68fb ldr r3, [r7, #12]
|
|
800b476: 681b ldr r3, [r3, #0]
|
|
800b478: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800b47c: 61da str r2, [r3, #28]
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
800b47e: 68fb ldr r3, [r7, #12]
|
|
800b480: 681b ldr r3, [r3, #0]
|
|
800b482: 69da ldr r2, [r3, #28]
|
|
800b484: 68fb ldr r3, [r7, #12]
|
|
800b486: 681b ldr r3, [r3, #0]
|
|
800b488: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800b48c: 61da str r2, [r3, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
800b48e: 68fb ldr r3, [r7, #12]
|
|
800b490: 681b ldr r3, [r3, #0]
|
|
800b492: 69d9 ldr r1, [r3, #28]
|
|
800b494: 68bb ldr r3, [r7, #8]
|
|
800b496: 691b ldr r3, [r3, #16]
|
|
800b498: 021a lsls r2, r3, #8
|
|
800b49a: 68fb ldr r3, [r7, #12]
|
|
800b49c: 681b ldr r3, [r3, #0]
|
|
800b49e: 430a orrs r2, r1
|
|
800b4a0: 61da str r2, [r3, #28]
|
|
break;
|
|
800b4a2: e041 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 5 in PWM mode */
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
800b4a4: 68fb ldr r3, [r7, #12]
|
|
800b4a6: 681b ldr r3, [r3, #0]
|
|
800b4a8: 68b9 ldr r1, [r7, #8]
|
|
800b4aa: 4618 mov r0, r3
|
|
800b4ac: f000 fbc6 bl 800bc3c <TIM_OC5_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel5*/
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
800b4b0: 68fb ldr r3, [r7, #12]
|
|
800b4b2: 681b ldr r3, [r3, #0]
|
|
800b4b4: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
800b4b6: 68fb ldr r3, [r7, #12]
|
|
800b4b8: 681b ldr r3, [r3, #0]
|
|
800b4ba: f042 0208 orr.w r2, r2, #8
|
|
800b4be: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
800b4c0: 68fb ldr r3, [r7, #12]
|
|
800b4c2: 681b ldr r3, [r3, #0]
|
|
800b4c4: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
800b4c6: 68fb ldr r3, [r7, #12]
|
|
800b4c8: 681b ldr r3, [r3, #0]
|
|
800b4ca: f022 0204 bic.w r2, r2, #4
|
|
800b4ce: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
800b4d0: 68fb ldr r3, [r7, #12]
|
|
800b4d2: 681b ldr r3, [r3, #0]
|
|
800b4d4: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
800b4d6: 68bb ldr r3, [r7, #8]
|
|
800b4d8: 691a ldr r2, [r3, #16]
|
|
800b4da: 68fb ldr r3, [r7, #12]
|
|
800b4dc: 681b ldr r3, [r3, #0]
|
|
800b4de: 430a orrs r2, r1
|
|
800b4e0: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
800b4e2: e021 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
|
|
|
|
/* Configure the Channel 6 in PWM mode */
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
800b4e4: 68fb ldr r3, [r7, #12]
|
|
800b4e6: 681b ldr r3, [r3, #0]
|
|
800b4e8: 68b9 ldr r1, [r7, #8]
|
|
800b4ea: 4618 mov r0, r3
|
|
800b4ec: f000 fbf8 bl 800bce0 <TIM_OC6_SetConfig>
|
|
|
|
/* Set the Preload enable bit for channel6 */
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
800b4f0: 68fb ldr r3, [r7, #12]
|
|
800b4f2: 681b ldr r3, [r3, #0]
|
|
800b4f4: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
800b4f6: 68fb ldr r3, [r7, #12]
|
|
800b4f8: 681b ldr r3, [r3, #0]
|
|
800b4fa: f442 6200 orr.w r2, r2, #2048 ; 0x800
|
|
800b4fe: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Configure the Output Fast mode */
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
800b500: 68fb ldr r3, [r7, #12]
|
|
800b502: 681b ldr r3, [r3, #0]
|
|
800b504: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
800b506: 68fb ldr r3, [r7, #12]
|
|
800b508: 681b ldr r3, [r3, #0]
|
|
800b50a: f422 6280 bic.w r2, r2, #1024 ; 0x400
|
|
800b50e: 655a str r2, [r3, #84] ; 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
800b510: 68fb ldr r3, [r7, #12]
|
|
800b512: 681b ldr r3, [r3, #0]
|
|
800b514: 6d59 ldr r1, [r3, #84] ; 0x54
|
|
800b516: 68bb ldr r3, [r7, #8]
|
|
800b518: 691b ldr r3, [r3, #16]
|
|
800b51a: 021a lsls r2, r3, #8
|
|
800b51c: 68fb ldr r3, [r7, #12]
|
|
800b51e: 681b ldr r3, [r3, #0]
|
|
800b520: 430a orrs r2, r1
|
|
800b522: 655a str r2, [r3, #84] ; 0x54
|
|
break;
|
|
800b524: e000 b.n 800b528 <HAL_TIM_PWM_ConfigChannel+0x214>
|
|
}
|
|
|
|
default:
|
|
break;
|
|
800b526: bf00 nop
|
|
}
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b528: 68fb ldr r3, [r7, #12]
|
|
800b52a: 2201 movs r2, #1
|
|
800b52c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800b530: 68fb ldr r3, [r7, #12]
|
|
800b532: 2200 movs r2, #0
|
|
800b534: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800b538: 2300 movs r3, #0
|
|
}
|
|
800b53a: 4618 mov r0, r3
|
|
800b53c: 3710 adds r7, #16
|
|
800b53e: 46bd mov sp, r7
|
|
800b540: bd80 pop {r7, pc}
|
|
800b542: bf00 nop
|
|
|
|
0800b544 <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
800b544: b580 push {r7, lr}
|
|
800b546: b084 sub sp, #16
|
|
800b548: af00 add r7, sp, #0
|
|
800b54a: 6078 str r0, [r7, #4]
|
|
800b54c: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
800b54e: 687b ldr r3, [r7, #4]
|
|
800b550: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800b554: 2b01 cmp r3, #1
|
|
800b556: d101 bne.n 800b55c <HAL_TIM_ConfigClockSource+0x18>
|
|
800b558: 2302 movs r3, #2
|
|
800b55a: e0a6 b.n 800b6aa <HAL_TIM_ConfigClockSource+0x166>
|
|
800b55c: 687b ldr r3, [r7, #4]
|
|
800b55e: 2201 movs r2, #1
|
|
800b560: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800b564: 687b ldr r3, [r7, #4]
|
|
800b566: 2202 movs r2, #2
|
|
800b568: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800b56c: 687b ldr r3, [r7, #4]
|
|
800b56e: 681b ldr r3, [r3, #0]
|
|
800b570: 689b ldr r3, [r3, #8]
|
|
800b572: 60fb str r3, [r7, #12]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
800b574: 68fa ldr r2, [r7, #12]
|
|
800b576: 4b4f ldr r3, [pc, #316] ; (800b6b4 <HAL_TIM_ConfigClockSource+0x170>)
|
|
800b578: 4013 ands r3, r2
|
|
800b57a: 60fb str r3, [r7, #12]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
800b57c: 68fb ldr r3, [r7, #12]
|
|
800b57e: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
800b582: 60fb str r3, [r7, #12]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800b584: 687b ldr r3, [r7, #4]
|
|
800b586: 681b ldr r3, [r3, #0]
|
|
800b588: 68fa ldr r2, [r7, #12]
|
|
800b58a: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800b58c: 683b ldr r3, [r7, #0]
|
|
800b58e: 681b ldr r3, [r3, #0]
|
|
800b590: 2b40 cmp r3, #64 ; 0x40
|
|
800b592: d067 beq.n 800b664 <HAL_TIM_ConfigClockSource+0x120>
|
|
800b594: 2b40 cmp r3, #64 ; 0x40
|
|
800b596: d80b bhi.n 800b5b0 <HAL_TIM_ConfigClockSource+0x6c>
|
|
800b598: 2b10 cmp r3, #16
|
|
800b59a: d073 beq.n 800b684 <HAL_TIM_ConfigClockSource+0x140>
|
|
800b59c: 2b10 cmp r3, #16
|
|
800b59e: d802 bhi.n 800b5a6 <HAL_TIM_ConfigClockSource+0x62>
|
|
800b5a0: 2b00 cmp r3, #0
|
|
800b5a2: d06f beq.n 800b684 <HAL_TIM_ConfigClockSource+0x140>
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
800b5a4: e078 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800b5a6: 2b20 cmp r3, #32
|
|
800b5a8: d06c beq.n 800b684 <HAL_TIM_ConfigClockSource+0x140>
|
|
800b5aa: 2b30 cmp r3, #48 ; 0x30
|
|
800b5ac: d06a beq.n 800b684 <HAL_TIM_ConfigClockSource+0x140>
|
|
break;
|
|
800b5ae: e073 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800b5b0: 2b70 cmp r3, #112 ; 0x70
|
|
800b5b2: d00d beq.n 800b5d0 <HAL_TIM_ConfigClockSource+0x8c>
|
|
800b5b4: 2b70 cmp r3, #112 ; 0x70
|
|
800b5b6: d804 bhi.n 800b5c2 <HAL_TIM_ConfigClockSource+0x7e>
|
|
800b5b8: 2b50 cmp r3, #80 ; 0x50
|
|
800b5ba: d033 beq.n 800b624 <HAL_TIM_ConfigClockSource+0xe0>
|
|
800b5bc: 2b60 cmp r3, #96 ; 0x60
|
|
800b5be: d041 beq.n 800b644 <HAL_TIM_ConfigClockSource+0x100>
|
|
break;
|
|
800b5c0: e06a b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800b5c2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800b5c6: d066 beq.n 800b696 <HAL_TIM_ConfigClockSource+0x152>
|
|
800b5c8: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
800b5cc: d017 beq.n 800b5fe <HAL_TIM_ConfigClockSource+0xba>
|
|
break;
|
|
800b5ce: e063 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800b5d0: 687b ldr r3, [r7, #4]
|
|
800b5d2: 6818 ldr r0, [r3, #0]
|
|
800b5d4: 683b ldr r3, [r7, #0]
|
|
800b5d6: 6899 ldr r1, [r3, #8]
|
|
800b5d8: 683b ldr r3, [r7, #0]
|
|
800b5da: 685a ldr r2, [r3, #4]
|
|
800b5dc: 683b ldr r3, [r7, #0]
|
|
800b5de: 68db ldr r3, [r3, #12]
|
|
800b5e0: f000 fcd4 bl 800bf8c <TIM_ETR_SetConfig>
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800b5e4: 687b ldr r3, [r7, #4]
|
|
800b5e6: 681b ldr r3, [r3, #0]
|
|
800b5e8: 689b ldr r3, [r3, #8]
|
|
800b5ea: 60fb str r3, [r7, #12]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
800b5ec: 68fb ldr r3, [r7, #12]
|
|
800b5ee: f043 0377 orr.w r3, r3, #119 ; 0x77
|
|
800b5f2: 60fb str r3, [r7, #12]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800b5f4: 687b ldr r3, [r7, #4]
|
|
800b5f6: 681b ldr r3, [r3, #0]
|
|
800b5f8: 68fa ldr r2, [r7, #12]
|
|
800b5fa: 609a str r2, [r3, #8]
|
|
break;
|
|
800b5fc: e04c b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800b5fe: 687b ldr r3, [r7, #4]
|
|
800b600: 6818 ldr r0, [r3, #0]
|
|
800b602: 683b ldr r3, [r7, #0]
|
|
800b604: 6899 ldr r1, [r3, #8]
|
|
800b606: 683b ldr r3, [r7, #0]
|
|
800b608: 685a ldr r2, [r3, #4]
|
|
800b60a: 683b ldr r3, [r7, #0]
|
|
800b60c: 68db ldr r3, [r3, #12]
|
|
800b60e: f000 fcbd bl 800bf8c <TIM_ETR_SetConfig>
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
800b612: 687b ldr r3, [r7, #4]
|
|
800b614: 681b ldr r3, [r3, #0]
|
|
800b616: 689a ldr r2, [r3, #8]
|
|
800b618: 687b ldr r3, [r7, #4]
|
|
800b61a: 681b ldr r3, [r3, #0]
|
|
800b61c: f442 4280 orr.w r2, r2, #16384 ; 0x4000
|
|
800b620: 609a str r2, [r3, #8]
|
|
break;
|
|
800b622: e039 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800b624: 687b ldr r3, [r7, #4]
|
|
800b626: 6818 ldr r0, [r3, #0]
|
|
800b628: 683b ldr r3, [r7, #0]
|
|
800b62a: 6859 ldr r1, [r3, #4]
|
|
800b62c: 683b ldr r3, [r7, #0]
|
|
800b62e: 68db ldr r3, [r3, #12]
|
|
800b630: 461a mov r2, r3
|
|
800b632: f000 fc31 bl 800be98 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
800b636: 687b ldr r3, [r7, #4]
|
|
800b638: 681b ldr r3, [r3, #0]
|
|
800b63a: 2150 movs r1, #80 ; 0x50
|
|
800b63c: 4618 mov r0, r3
|
|
800b63e: f000 fc8a bl 800bf56 <TIM_ITRx_SetConfig>
|
|
break;
|
|
800b642: e029 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
800b644: 687b ldr r3, [r7, #4]
|
|
800b646: 6818 ldr r0, [r3, #0]
|
|
800b648: 683b ldr r3, [r7, #0]
|
|
800b64a: 6859 ldr r1, [r3, #4]
|
|
800b64c: 683b ldr r3, [r7, #0]
|
|
800b64e: 68db ldr r3, [r3, #12]
|
|
800b650: 461a mov r2, r3
|
|
800b652: f000 fc50 bl 800bef6 <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
800b656: 687b ldr r3, [r7, #4]
|
|
800b658: 681b ldr r3, [r3, #0]
|
|
800b65a: 2160 movs r1, #96 ; 0x60
|
|
800b65c: 4618 mov r0, r3
|
|
800b65e: f000 fc7a bl 800bf56 <TIM_ITRx_SetConfig>
|
|
break;
|
|
800b662: e019 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800b664: 687b ldr r3, [r7, #4]
|
|
800b666: 6818 ldr r0, [r3, #0]
|
|
800b668: 683b ldr r3, [r7, #0]
|
|
800b66a: 6859 ldr r1, [r3, #4]
|
|
800b66c: 683b ldr r3, [r7, #0]
|
|
800b66e: 68db ldr r3, [r3, #12]
|
|
800b670: 461a mov r2, r3
|
|
800b672: f000 fc11 bl 800be98 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
800b676: 687b ldr r3, [r7, #4]
|
|
800b678: 681b ldr r3, [r3, #0]
|
|
800b67a: 2140 movs r1, #64 ; 0x40
|
|
800b67c: 4618 mov r0, r3
|
|
800b67e: f000 fc6a bl 800bf56 <TIM_ITRx_SetConfig>
|
|
break;
|
|
800b682: e009 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
800b684: 687b ldr r3, [r7, #4]
|
|
800b686: 681a ldr r2, [r3, #0]
|
|
800b688: 683b ldr r3, [r7, #0]
|
|
800b68a: 681b ldr r3, [r3, #0]
|
|
800b68c: 4619 mov r1, r3
|
|
800b68e: 4610 mov r0, r2
|
|
800b690: f000 fc61 bl 800bf56 <TIM_ITRx_SetConfig>
|
|
break;
|
|
800b694: e000 b.n 800b698 <HAL_TIM_ConfigClockSource+0x154>
|
|
break;
|
|
800b696: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b698: 687b ldr r3, [r7, #4]
|
|
800b69a: 2201 movs r2, #1
|
|
800b69c: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800b6a0: 687b ldr r3, [r7, #4]
|
|
800b6a2: 2200 movs r2, #0
|
|
800b6a4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800b6a8: 2300 movs r3, #0
|
|
}
|
|
800b6aa: 4618 mov r0, r3
|
|
800b6ac: 3710 adds r7, #16
|
|
800b6ae: 46bd mov sp, r7
|
|
800b6b0: bd80 pop {r7, pc}
|
|
800b6b2: bf00 nop
|
|
800b6b4: fffeff88 .word 0xfffeff88
|
|
|
|
0800b6b8 <HAL_TIM_SlaveConfigSynchro>:
|
|
* timer input or external trigger input) and the Slave mode
|
|
* (Disable, Reset, Gated, Trigger, External clock mode 1).
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
|
|
{
|
|
800b6b8: b580 push {r7, lr}
|
|
800b6ba: b082 sub sp, #8
|
|
800b6bc: af00 add r7, sp, #0
|
|
800b6be: 6078 str r0, [r7, #4]
|
|
800b6c0: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
|
|
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
|
|
|
|
__HAL_LOCK(htim);
|
|
800b6c2: 687b ldr r3, [r7, #4]
|
|
800b6c4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800b6c8: 2b01 cmp r3, #1
|
|
800b6ca: d101 bne.n 800b6d0 <HAL_TIM_SlaveConfigSynchro+0x18>
|
|
800b6cc: 2302 movs r3, #2
|
|
800b6ce: e031 b.n 800b734 <HAL_TIM_SlaveConfigSynchro+0x7c>
|
|
800b6d0: 687b ldr r3, [r7, #4]
|
|
800b6d2: 2201 movs r2, #1
|
|
800b6d4: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800b6d8: 687b ldr r3, [r7, #4]
|
|
800b6da: 2202 movs r2, #2
|
|
800b6dc: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
|
|
800b6e0: 6839 ldr r1, [r7, #0]
|
|
800b6e2: 6878 ldr r0, [r7, #4]
|
|
800b6e4: f000 fb50 bl 800bd88 <TIM_SlaveTimer_SetConfig>
|
|
800b6e8: 4603 mov r3, r0
|
|
800b6ea: 2b00 cmp r3, #0
|
|
800b6ec: d009 beq.n 800b702 <HAL_TIM_SlaveConfigSynchro+0x4a>
|
|
{
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b6ee: 687b ldr r3, [r7, #4]
|
|
800b6f0: 2201 movs r2, #1
|
|
800b6f2: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
__HAL_UNLOCK(htim);
|
|
800b6f6: 687b ldr r3, [r7, #4]
|
|
800b6f8: 2200 movs r2, #0
|
|
800b6fa: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
return HAL_ERROR;
|
|
800b6fe: 2301 movs r3, #1
|
|
800b700: e018 b.n 800b734 <HAL_TIM_SlaveConfigSynchro+0x7c>
|
|
}
|
|
|
|
/* Disable Trigger Interrupt */
|
|
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
|
|
800b702: 687b ldr r3, [r7, #4]
|
|
800b704: 681b ldr r3, [r3, #0]
|
|
800b706: 68da ldr r2, [r3, #12]
|
|
800b708: 687b ldr r3, [r7, #4]
|
|
800b70a: 681b ldr r3, [r3, #0]
|
|
800b70c: f022 0240 bic.w r2, r2, #64 ; 0x40
|
|
800b710: 60da str r2, [r3, #12]
|
|
|
|
/* Disable Trigger DMA request */
|
|
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
|
|
800b712: 687b ldr r3, [r7, #4]
|
|
800b714: 681b ldr r3, [r3, #0]
|
|
800b716: 68da ldr r2, [r3, #12]
|
|
800b718: 687b ldr r3, [r7, #4]
|
|
800b71a: 681b ldr r3, [r3, #0]
|
|
800b71c: f422 4280 bic.w r2, r2, #16384 ; 0x4000
|
|
800b720: 60da str r2, [r3, #12]
|
|
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800b722: 687b ldr r3, [r7, #4]
|
|
800b724: 2201 movs r2, #1
|
|
800b726: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800b72a: 687b ldr r3, [r7, #4]
|
|
800b72c: 2200 movs r2, #0
|
|
800b72e: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800b732: 2300 movs r3, #0
|
|
}
|
|
800b734: 4618 mov r0, r3
|
|
800b736: 3708 adds r7, #8
|
|
800b738: 46bd mov sp, r7
|
|
800b73a: bd80 pop {r7, pc}
|
|
|
|
0800b73c <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b73c: b480 push {r7}
|
|
800b73e: b083 sub sp, #12
|
|
800b740: af00 add r7, sp, #0
|
|
800b742: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800b744: bf00 nop
|
|
800b746: 370c adds r7, #12
|
|
800b748: 46bd mov sp, r7
|
|
800b74a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b74e: 4770 bx lr
|
|
|
|
0800b750 <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b750: b480 push {r7}
|
|
800b752: b083 sub sp, #12
|
|
800b754: af00 add r7, sp, #0
|
|
800b756: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800b758: bf00 nop
|
|
800b75a: 370c adds r7, #12
|
|
800b75c: 46bd mov sp, r7
|
|
800b75e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b762: 4770 bx lr
|
|
|
|
0800b764 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b764: b480 push {r7}
|
|
800b766: b083 sub sp, #12
|
|
800b768: af00 add r7, sp, #0
|
|
800b76a: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800b76c: bf00 nop
|
|
800b76e: 370c adds r7, #12
|
|
800b770: 46bd mov sp, r7
|
|
800b772: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b776: 4770 bx lr
|
|
|
|
0800b778 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800b778: b480 push {r7}
|
|
800b77a: b083 sub sp, #12
|
|
800b77c: af00 add r7, sp, #0
|
|
800b77e: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800b780: bf00 nop
|
|
800b782: 370c adds r7, #12
|
|
800b784: 46bd mov sp, r7
|
|
800b786: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b78a: 4770 bx lr
|
|
|
|
0800b78c <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
800b78c: b480 push {r7}
|
|
800b78e: b085 sub sp, #20
|
|
800b790: af00 add r7, sp, #0
|
|
800b792: 6078 str r0, [r7, #4]
|
|
800b794: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
800b796: 687b ldr r3, [r7, #4]
|
|
800b798: 681b ldr r3, [r3, #0]
|
|
800b79a: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
800b79c: 687b ldr r3, [r7, #4]
|
|
800b79e: 4a40 ldr r2, [pc, #256] ; (800b8a0 <TIM_Base_SetConfig+0x114>)
|
|
800b7a0: 4293 cmp r3, r2
|
|
800b7a2: d013 beq.n 800b7cc <TIM_Base_SetConfig+0x40>
|
|
800b7a4: 687b ldr r3, [r7, #4]
|
|
800b7a6: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
800b7aa: d00f beq.n 800b7cc <TIM_Base_SetConfig+0x40>
|
|
800b7ac: 687b ldr r3, [r7, #4]
|
|
800b7ae: 4a3d ldr r2, [pc, #244] ; (800b8a4 <TIM_Base_SetConfig+0x118>)
|
|
800b7b0: 4293 cmp r3, r2
|
|
800b7b2: d00b beq.n 800b7cc <TIM_Base_SetConfig+0x40>
|
|
800b7b4: 687b ldr r3, [r7, #4]
|
|
800b7b6: 4a3c ldr r2, [pc, #240] ; (800b8a8 <TIM_Base_SetConfig+0x11c>)
|
|
800b7b8: 4293 cmp r3, r2
|
|
800b7ba: d007 beq.n 800b7cc <TIM_Base_SetConfig+0x40>
|
|
800b7bc: 687b ldr r3, [r7, #4]
|
|
800b7be: 4a3b ldr r2, [pc, #236] ; (800b8ac <TIM_Base_SetConfig+0x120>)
|
|
800b7c0: 4293 cmp r3, r2
|
|
800b7c2: d003 beq.n 800b7cc <TIM_Base_SetConfig+0x40>
|
|
800b7c4: 687b ldr r3, [r7, #4]
|
|
800b7c6: 4a3a ldr r2, [pc, #232] ; (800b8b0 <TIM_Base_SetConfig+0x124>)
|
|
800b7c8: 4293 cmp r3, r2
|
|
800b7ca: d108 bne.n 800b7de <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
800b7cc: 68fb ldr r3, [r7, #12]
|
|
800b7ce: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
800b7d2: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
800b7d4: 683b ldr r3, [r7, #0]
|
|
800b7d6: 685b ldr r3, [r3, #4]
|
|
800b7d8: 68fa ldr r2, [r7, #12]
|
|
800b7da: 4313 orrs r3, r2
|
|
800b7dc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
800b7de: 687b ldr r3, [r7, #4]
|
|
800b7e0: 4a2f ldr r2, [pc, #188] ; (800b8a0 <TIM_Base_SetConfig+0x114>)
|
|
800b7e2: 4293 cmp r3, r2
|
|
800b7e4: d02b beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b7e6: 687b ldr r3, [r7, #4]
|
|
800b7e8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
800b7ec: d027 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b7ee: 687b ldr r3, [r7, #4]
|
|
800b7f0: 4a2c ldr r2, [pc, #176] ; (800b8a4 <TIM_Base_SetConfig+0x118>)
|
|
800b7f2: 4293 cmp r3, r2
|
|
800b7f4: d023 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b7f6: 687b ldr r3, [r7, #4]
|
|
800b7f8: 4a2b ldr r2, [pc, #172] ; (800b8a8 <TIM_Base_SetConfig+0x11c>)
|
|
800b7fa: 4293 cmp r3, r2
|
|
800b7fc: d01f beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b7fe: 687b ldr r3, [r7, #4]
|
|
800b800: 4a2a ldr r2, [pc, #168] ; (800b8ac <TIM_Base_SetConfig+0x120>)
|
|
800b802: 4293 cmp r3, r2
|
|
800b804: d01b beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b806: 687b ldr r3, [r7, #4]
|
|
800b808: 4a29 ldr r2, [pc, #164] ; (800b8b0 <TIM_Base_SetConfig+0x124>)
|
|
800b80a: 4293 cmp r3, r2
|
|
800b80c: d017 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b80e: 687b ldr r3, [r7, #4]
|
|
800b810: 4a28 ldr r2, [pc, #160] ; (800b8b4 <TIM_Base_SetConfig+0x128>)
|
|
800b812: 4293 cmp r3, r2
|
|
800b814: d013 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b816: 687b ldr r3, [r7, #4]
|
|
800b818: 4a27 ldr r2, [pc, #156] ; (800b8b8 <TIM_Base_SetConfig+0x12c>)
|
|
800b81a: 4293 cmp r3, r2
|
|
800b81c: d00f beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b81e: 687b ldr r3, [r7, #4]
|
|
800b820: 4a26 ldr r2, [pc, #152] ; (800b8bc <TIM_Base_SetConfig+0x130>)
|
|
800b822: 4293 cmp r3, r2
|
|
800b824: d00b beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b826: 687b ldr r3, [r7, #4]
|
|
800b828: 4a25 ldr r2, [pc, #148] ; (800b8c0 <TIM_Base_SetConfig+0x134>)
|
|
800b82a: 4293 cmp r3, r2
|
|
800b82c: d007 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b82e: 687b ldr r3, [r7, #4]
|
|
800b830: 4a24 ldr r2, [pc, #144] ; (800b8c4 <TIM_Base_SetConfig+0x138>)
|
|
800b832: 4293 cmp r3, r2
|
|
800b834: d003 beq.n 800b83e <TIM_Base_SetConfig+0xb2>
|
|
800b836: 687b ldr r3, [r7, #4]
|
|
800b838: 4a23 ldr r2, [pc, #140] ; (800b8c8 <TIM_Base_SetConfig+0x13c>)
|
|
800b83a: 4293 cmp r3, r2
|
|
800b83c: d108 bne.n 800b850 <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800b83e: 68fb ldr r3, [r7, #12]
|
|
800b840: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
800b844: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
800b846: 683b ldr r3, [r7, #0]
|
|
800b848: 68db ldr r3, [r3, #12]
|
|
800b84a: 68fa ldr r2, [r7, #12]
|
|
800b84c: 4313 orrs r3, r2
|
|
800b84e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
800b850: 68fb ldr r3, [r7, #12]
|
|
800b852: f023 0280 bic.w r2, r3, #128 ; 0x80
|
|
800b856: 683b ldr r3, [r7, #0]
|
|
800b858: 695b ldr r3, [r3, #20]
|
|
800b85a: 4313 orrs r3, r2
|
|
800b85c: 60fb str r3, [r7, #12]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
800b85e: 687b ldr r3, [r7, #4]
|
|
800b860: 68fa ldr r2, [r7, #12]
|
|
800b862: 601a str r2, [r3, #0]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800b864: 683b ldr r3, [r7, #0]
|
|
800b866: 689a ldr r2, [r3, #8]
|
|
800b868: 687b ldr r3, [r7, #4]
|
|
800b86a: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
800b86c: 683b ldr r3, [r7, #0]
|
|
800b86e: 681a ldr r2, [r3, #0]
|
|
800b870: 687b ldr r3, [r7, #4]
|
|
800b872: 629a str r2, [r3, #40] ; 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800b874: 687b ldr r3, [r7, #4]
|
|
800b876: 4a0a ldr r2, [pc, #40] ; (800b8a0 <TIM_Base_SetConfig+0x114>)
|
|
800b878: 4293 cmp r3, r2
|
|
800b87a: d003 beq.n 800b884 <TIM_Base_SetConfig+0xf8>
|
|
800b87c: 687b ldr r3, [r7, #4]
|
|
800b87e: 4a0c ldr r2, [pc, #48] ; (800b8b0 <TIM_Base_SetConfig+0x124>)
|
|
800b880: 4293 cmp r3, r2
|
|
800b882: d103 bne.n 800b88c <TIM_Base_SetConfig+0x100>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800b884: 683b ldr r3, [r7, #0]
|
|
800b886: 691a ldr r2, [r3, #16]
|
|
800b888: 687b ldr r3, [r7, #4]
|
|
800b88a: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800b88c: 687b ldr r3, [r7, #4]
|
|
800b88e: 2201 movs r2, #1
|
|
800b890: 615a str r2, [r3, #20]
|
|
}
|
|
800b892: bf00 nop
|
|
800b894: 3714 adds r7, #20
|
|
800b896: 46bd mov sp, r7
|
|
800b898: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b89c: 4770 bx lr
|
|
800b89e: bf00 nop
|
|
800b8a0: 40010000 .word 0x40010000
|
|
800b8a4: 40000400 .word 0x40000400
|
|
800b8a8: 40000800 .word 0x40000800
|
|
800b8ac: 40000c00 .word 0x40000c00
|
|
800b8b0: 40010400 .word 0x40010400
|
|
800b8b4: 40014000 .word 0x40014000
|
|
800b8b8: 40014400 .word 0x40014400
|
|
800b8bc: 40014800 .word 0x40014800
|
|
800b8c0: 40001800 .word 0x40001800
|
|
800b8c4: 40001c00 .word 0x40001c00
|
|
800b8c8: 40002000 .word 0x40002000
|
|
|
|
0800b8cc <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800b8cc: b480 push {r7}
|
|
800b8ce: b087 sub sp, #28
|
|
800b8d0: af00 add r7, sp, #0
|
|
800b8d2: 6078 str r0, [r7, #4]
|
|
800b8d4: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800b8d6: 687b ldr r3, [r7, #4]
|
|
800b8d8: 6a1b ldr r3, [r3, #32]
|
|
800b8da: f023 0201 bic.w r2, r3, #1
|
|
800b8de: 687b ldr r3, [r7, #4]
|
|
800b8e0: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800b8e2: 687b ldr r3, [r7, #4]
|
|
800b8e4: 6a1b ldr r3, [r3, #32]
|
|
800b8e6: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800b8e8: 687b ldr r3, [r7, #4]
|
|
800b8ea: 685b ldr r3, [r3, #4]
|
|
800b8ec: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800b8ee: 687b ldr r3, [r7, #4]
|
|
800b8f0: 699b ldr r3, [r3, #24]
|
|
800b8f2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
800b8f4: 68fa ldr r2, [r7, #12]
|
|
800b8f6: 4b2b ldr r3, [pc, #172] ; (800b9a4 <TIM_OC1_SetConfig+0xd8>)
|
|
800b8f8: 4013 ands r3, r2
|
|
800b8fa: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
800b8fc: 68fb ldr r3, [r7, #12]
|
|
800b8fe: f023 0303 bic.w r3, r3, #3
|
|
800b902: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800b904: 683b ldr r3, [r7, #0]
|
|
800b906: 681b ldr r3, [r3, #0]
|
|
800b908: 68fa ldr r2, [r7, #12]
|
|
800b90a: 4313 orrs r3, r2
|
|
800b90c: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
800b90e: 697b ldr r3, [r7, #20]
|
|
800b910: f023 0302 bic.w r3, r3, #2
|
|
800b914: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
800b916: 683b ldr r3, [r7, #0]
|
|
800b918: 689b ldr r3, [r3, #8]
|
|
800b91a: 697a ldr r2, [r7, #20]
|
|
800b91c: 4313 orrs r3, r2
|
|
800b91e: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
800b920: 687b ldr r3, [r7, #4]
|
|
800b922: 4a21 ldr r2, [pc, #132] ; (800b9a8 <TIM_OC1_SetConfig+0xdc>)
|
|
800b924: 4293 cmp r3, r2
|
|
800b926: d003 beq.n 800b930 <TIM_OC1_SetConfig+0x64>
|
|
800b928: 687b ldr r3, [r7, #4]
|
|
800b92a: 4a20 ldr r2, [pc, #128] ; (800b9ac <TIM_OC1_SetConfig+0xe0>)
|
|
800b92c: 4293 cmp r3, r2
|
|
800b92e: d10c bne.n 800b94a <TIM_OC1_SetConfig+0x7e>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
800b930: 697b ldr r3, [r7, #20]
|
|
800b932: f023 0308 bic.w r3, r3, #8
|
|
800b936: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
800b938: 683b ldr r3, [r7, #0]
|
|
800b93a: 68db ldr r3, [r3, #12]
|
|
800b93c: 697a ldr r2, [r7, #20]
|
|
800b93e: 4313 orrs r3, r2
|
|
800b940: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
800b942: 697b ldr r3, [r7, #20]
|
|
800b944: f023 0304 bic.w r3, r3, #4
|
|
800b948: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800b94a: 687b ldr r3, [r7, #4]
|
|
800b94c: 4a16 ldr r2, [pc, #88] ; (800b9a8 <TIM_OC1_SetConfig+0xdc>)
|
|
800b94e: 4293 cmp r3, r2
|
|
800b950: d003 beq.n 800b95a <TIM_OC1_SetConfig+0x8e>
|
|
800b952: 687b ldr r3, [r7, #4]
|
|
800b954: 4a15 ldr r2, [pc, #84] ; (800b9ac <TIM_OC1_SetConfig+0xe0>)
|
|
800b956: 4293 cmp r3, r2
|
|
800b958: d111 bne.n 800b97e <TIM_OC1_SetConfig+0xb2>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
800b95a: 693b ldr r3, [r7, #16]
|
|
800b95c: f423 7380 bic.w r3, r3, #256 ; 0x100
|
|
800b960: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
800b962: 693b ldr r3, [r7, #16]
|
|
800b964: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
800b968: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
800b96a: 683b ldr r3, [r7, #0]
|
|
800b96c: 695b ldr r3, [r3, #20]
|
|
800b96e: 693a ldr r2, [r7, #16]
|
|
800b970: 4313 orrs r3, r2
|
|
800b972: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
800b974: 683b ldr r3, [r7, #0]
|
|
800b976: 699b ldr r3, [r3, #24]
|
|
800b978: 693a ldr r2, [r7, #16]
|
|
800b97a: 4313 orrs r3, r2
|
|
800b97c: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800b97e: 687b ldr r3, [r7, #4]
|
|
800b980: 693a ldr r2, [r7, #16]
|
|
800b982: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800b984: 687b ldr r3, [r7, #4]
|
|
800b986: 68fa ldr r2, [r7, #12]
|
|
800b988: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
800b98a: 683b ldr r3, [r7, #0]
|
|
800b98c: 685a ldr r2, [r3, #4]
|
|
800b98e: 687b ldr r3, [r7, #4]
|
|
800b990: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800b992: 687b ldr r3, [r7, #4]
|
|
800b994: 697a ldr r2, [r7, #20]
|
|
800b996: 621a str r2, [r3, #32]
|
|
}
|
|
800b998: bf00 nop
|
|
800b99a: 371c adds r7, #28
|
|
800b99c: 46bd mov sp, r7
|
|
800b99e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b9a2: 4770 bx lr
|
|
800b9a4: fffeff8f .word 0xfffeff8f
|
|
800b9a8: 40010000 .word 0x40010000
|
|
800b9ac: 40010400 .word 0x40010400
|
|
|
|
0800b9b0 <TIM_OC2_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800b9b0: b480 push {r7}
|
|
800b9b2: b087 sub sp, #28
|
|
800b9b4: af00 add r7, sp, #0
|
|
800b9b6: 6078 str r0, [r7, #4]
|
|
800b9b8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800b9ba: 687b ldr r3, [r7, #4]
|
|
800b9bc: 6a1b ldr r3, [r3, #32]
|
|
800b9be: f023 0210 bic.w r2, r3, #16
|
|
800b9c2: 687b ldr r3, [r7, #4]
|
|
800b9c4: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800b9c6: 687b ldr r3, [r7, #4]
|
|
800b9c8: 6a1b ldr r3, [r3, #32]
|
|
800b9ca: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800b9cc: 687b ldr r3, [r7, #4]
|
|
800b9ce: 685b ldr r3, [r3, #4]
|
|
800b9d0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
800b9d2: 687b ldr r3, [r7, #4]
|
|
800b9d4: 699b ldr r3, [r3, #24]
|
|
800b9d6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC2M;
|
|
800b9d8: 68fa ldr r2, [r7, #12]
|
|
800b9da: 4b2e ldr r3, [pc, #184] ; (800ba94 <TIM_OC2_SetConfig+0xe4>)
|
|
800b9dc: 4013 ands r3, r2
|
|
800b9de: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
800b9e0: 68fb ldr r3, [r7, #12]
|
|
800b9e2: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
800b9e6: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800b9e8: 683b ldr r3, [r7, #0]
|
|
800b9ea: 681b ldr r3, [r3, #0]
|
|
800b9ec: 021b lsls r3, r3, #8
|
|
800b9ee: 68fa ldr r2, [r7, #12]
|
|
800b9f0: 4313 orrs r3, r2
|
|
800b9f2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
800b9f4: 697b ldr r3, [r7, #20]
|
|
800b9f6: f023 0320 bic.w r3, r3, #32
|
|
800b9fa: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
800b9fc: 683b ldr r3, [r7, #0]
|
|
800b9fe: 689b ldr r3, [r3, #8]
|
|
800ba00: 011b lsls r3, r3, #4
|
|
800ba02: 697a ldr r2, [r7, #20]
|
|
800ba04: 4313 orrs r3, r2
|
|
800ba06: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
800ba08: 687b ldr r3, [r7, #4]
|
|
800ba0a: 4a23 ldr r2, [pc, #140] ; (800ba98 <TIM_OC2_SetConfig+0xe8>)
|
|
800ba0c: 4293 cmp r3, r2
|
|
800ba0e: d003 beq.n 800ba18 <TIM_OC2_SetConfig+0x68>
|
|
800ba10: 687b ldr r3, [r7, #4]
|
|
800ba12: 4a22 ldr r2, [pc, #136] ; (800ba9c <TIM_OC2_SetConfig+0xec>)
|
|
800ba14: 4293 cmp r3, r2
|
|
800ba16: d10d bne.n 800ba34 <TIM_OC2_SetConfig+0x84>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
800ba18: 697b ldr r3, [r7, #20]
|
|
800ba1a: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
800ba1e: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
800ba20: 683b ldr r3, [r7, #0]
|
|
800ba22: 68db ldr r3, [r3, #12]
|
|
800ba24: 011b lsls r3, r3, #4
|
|
800ba26: 697a ldr r2, [r7, #20]
|
|
800ba28: 4313 orrs r3, r2
|
|
800ba2a: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
800ba2c: 697b ldr r3, [r7, #20]
|
|
800ba2e: f023 0340 bic.w r3, r3, #64 ; 0x40
|
|
800ba32: 617b str r3, [r7, #20]
|
|
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800ba34: 687b ldr r3, [r7, #4]
|
|
800ba36: 4a18 ldr r2, [pc, #96] ; (800ba98 <TIM_OC2_SetConfig+0xe8>)
|
|
800ba38: 4293 cmp r3, r2
|
|
800ba3a: d003 beq.n 800ba44 <TIM_OC2_SetConfig+0x94>
|
|
800ba3c: 687b ldr r3, [r7, #4]
|
|
800ba3e: 4a17 ldr r2, [pc, #92] ; (800ba9c <TIM_OC2_SetConfig+0xec>)
|
|
800ba40: 4293 cmp r3, r2
|
|
800ba42: d113 bne.n 800ba6c <TIM_OC2_SetConfig+0xbc>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS2;
|
|
800ba44: 693b ldr r3, [r7, #16]
|
|
800ba46: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
800ba4a: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
800ba4c: 693b ldr r3, [r7, #16]
|
|
800ba4e: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
800ba52: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 2U);
|
|
800ba54: 683b ldr r3, [r7, #0]
|
|
800ba56: 695b ldr r3, [r3, #20]
|
|
800ba58: 009b lsls r3, r3, #2
|
|
800ba5a: 693a ldr r2, [r7, #16]
|
|
800ba5c: 4313 orrs r3, r2
|
|
800ba5e: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
800ba60: 683b ldr r3, [r7, #0]
|
|
800ba62: 699b ldr r3, [r3, #24]
|
|
800ba64: 009b lsls r3, r3, #2
|
|
800ba66: 693a ldr r2, [r7, #16]
|
|
800ba68: 4313 orrs r3, r2
|
|
800ba6a: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800ba6c: 687b ldr r3, [r7, #4]
|
|
800ba6e: 693a ldr r2, [r7, #16]
|
|
800ba70: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800ba72: 687b ldr r3, [r7, #4]
|
|
800ba74: 68fa ldr r2, [r7, #12]
|
|
800ba76: 619a str r2, [r3, #24]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
800ba78: 683b ldr r3, [r7, #0]
|
|
800ba7a: 685a ldr r2, [r3, #4]
|
|
800ba7c: 687b ldr r3, [r7, #4]
|
|
800ba7e: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800ba80: 687b ldr r3, [r7, #4]
|
|
800ba82: 697a ldr r2, [r7, #20]
|
|
800ba84: 621a str r2, [r3, #32]
|
|
}
|
|
800ba86: bf00 nop
|
|
800ba88: 371c adds r7, #28
|
|
800ba8a: 46bd mov sp, r7
|
|
800ba8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ba90: 4770 bx lr
|
|
800ba92: bf00 nop
|
|
800ba94: feff8fff .word 0xfeff8fff
|
|
800ba98: 40010000 .word 0x40010000
|
|
800ba9c: 40010400 .word 0x40010400
|
|
|
|
0800baa0 <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800baa0: b480 push {r7}
|
|
800baa2: b087 sub sp, #28
|
|
800baa4: af00 add r7, sp, #0
|
|
800baa6: 6078 str r0, [r7, #4]
|
|
800baa8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
800baaa: 687b ldr r3, [r7, #4]
|
|
800baac: 6a1b ldr r3, [r3, #32]
|
|
800baae: f423 7280 bic.w r2, r3, #256 ; 0x100
|
|
800bab2: 687b ldr r3, [r7, #4]
|
|
800bab4: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800bab6: 687b ldr r3, [r7, #4]
|
|
800bab8: 6a1b ldr r3, [r3, #32]
|
|
800baba: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800babc: 687b ldr r3, [r7, #4]
|
|
800babe: 685b ldr r3, [r3, #4]
|
|
800bac0: 613b str r3, [r7, #16]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800bac2: 687b ldr r3, [r7, #4]
|
|
800bac4: 69db ldr r3, [r3, #28]
|
|
800bac6: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
800bac8: 68fa ldr r2, [r7, #12]
|
|
800baca: 4b2d ldr r3, [pc, #180] ; (800bb80 <TIM_OC3_SetConfig+0xe0>)
|
|
800bacc: 4013 ands r3, r2
|
|
800bace: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
800bad0: 68fb ldr r3, [r7, #12]
|
|
800bad2: f023 0303 bic.w r3, r3, #3
|
|
800bad6: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800bad8: 683b ldr r3, [r7, #0]
|
|
800bada: 681b ldr r3, [r3, #0]
|
|
800badc: 68fa ldr r2, [r7, #12]
|
|
800bade: 4313 orrs r3, r2
|
|
800bae0: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
800bae2: 697b ldr r3, [r7, #20]
|
|
800bae4: f423 7300 bic.w r3, r3, #512 ; 0x200
|
|
800bae8: 617b str r3, [r7, #20]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
800baea: 683b ldr r3, [r7, #0]
|
|
800baec: 689b ldr r3, [r3, #8]
|
|
800baee: 021b lsls r3, r3, #8
|
|
800baf0: 697a ldr r2, [r7, #20]
|
|
800baf2: 4313 orrs r3, r2
|
|
800baf4: 617b str r3, [r7, #20]
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
800baf6: 687b ldr r3, [r7, #4]
|
|
800baf8: 4a22 ldr r2, [pc, #136] ; (800bb84 <TIM_OC3_SetConfig+0xe4>)
|
|
800bafa: 4293 cmp r3, r2
|
|
800bafc: d003 beq.n 800bb06 <TIM_OC3_SetConfig+0x66>
|
|
800bafe: 687b ldr r3, [r7, #4]
|
|
800bb00: 4a21 ldr r2, [pc, #132] ; (800bb88 <TIM_OC3_SetConfig+0xe8>)
|
|
800bb02: 4293 cmp r3, r2
|
|
800bb04: d10d bne.n 800bb22 <TIM_OC3_SetConfig+0x82>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
800bb06: 697b ldr r3, [r7, #20]
|
|
800bb08: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
800bb0c: 617b str r3, [r7, #20]
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
800bb0e: 683b ldr r3, [r7, #0]
|
|
800bb10: 68db ldr r3, [r3, #12]
|
|
800bb12: 021b lsls r3, r3, #8
|
|
800bb14: 697a ldr r2, [r7, #20]
|
|
800bb16: 4313 orrs r3, r2
|
|
800bb18: 617b str r3, [r7, #20]
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
800bb1a: 697b ldr r3, [r7, #20]
|
|
800bb1c: f423 6380 bic.w r3, r3, #1024 ; 0x400
|
|
800bb20: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800bb22: 687b ldr r3, [r7, #4]
|
|
800bb24: 4a17 ldr r2, [pc, #92] ; (800bb84 <TIM_OC3_SetConfig+0xe4>)
|
|
800bb26: 4293 cmp r3, r2
|
|
800bb28: d003 beq.n 800bb32 <TIM_OC3_SetConfig+0x92>
|
|
800bb2a: 687b ldr r3, [r7, #4]
|
|
800bb2c: 4a16 ldr r2, [pc, #88] ; (800bb88 <TIM_OC3_SetConfig+0xe8>)
|
|
800bb2e: 4293 cmp r3, r2
|
|
800bb30: d113 bne.n 800bb5a <TIM_OC3_SetConfig+0xba>
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
800bb32: 693b ldr r3, [r7, #16]
|
|
800bb34: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
800bb38: 613b str r3, [r7, #16]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
800bb3a: 693b ldr r3, [r7, #16]
|
|
800bb3c: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
800bb40: 613b str r3, [r7, #16]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
800bb42: 683b ldr r3, [r7, #0]
|
|
800bb44: 695b ldr r3, [r3, #20]
|
|
800bb46: 011b lsls r3, r3, #4
|
|
800bb48: 693a ldr r2, [r7, #16]
|
|
800bb4a: 4313 orrs r3, r2
|
|
800bb4c: 613b str r3, [r7, #16]
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
800bb4e: 683b ldr r3, [r7, #0]
|
|
800bb50: 699b ldr r3, [r3, #24]
|
|
800bb52: 011b lsls r3, r3, #4
|
|
800bb54: 693a ldr r2, [r7, #16]
|
|
800bb56: 4313 orrs r3, r2
|
|
800bb58: 613b str r3, [r7, #16]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800bb5a: 687b ldr r3, [r7, #4]
|
|
800bb5c: 693a ldr r2, [r7, #16]
|
|
800bb5e: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800bb60: 687b ldr r3, [r7, #4]
|
|
800bb62: 68fa ldr r2, [r7, #12]
|
|
800bb64: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
800bb66: 683b ldr r3, [r7, #0]
|
|
800bb68: 685a ldr r2, [r3, #4]
|
|
800bb6a: 687b ldr r3, [r7, #4]
|
|
800bb6c: 63da str r2, [r3, #60] ; 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800bb6e: 687b ldr r3, [r7, #4]
|
|
800bb70: 697a ldr r2, [r7, #20]
|
|
800bb72: 621a str r2, [r3, #32]
|
|
}
|
|
800bb74: bf00 nop
|
|
800bb76: 371c adds r7, #28
|
|
800bb78: 46bd mov sp, r7
|
|
800bb7a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bb7e: 4770 bx lr
|
|
800bb80: fffeff8f .word 0xfffeff8f
|
|
800bb84: 40010000 .word 0x40010000
|
|
800bb88: 40010400 .word 0x40010400
|
|
|
|
0800bb8c <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800bb8c: b480 push {r7}
|
|
800bb8e: b087 sub sp, #28
|
|
800bb90: af00 add r7, sp, #0
|
|
800bb92: 6078 str r0, [r7, #4]
|
|
800bb94: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
800bb96: 687b ldr r3, [r7, #4]
|
|
800bb98: 6a1b ldr r3, [r3, #32]
|
|
800bb9a: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
800bb9e: 687b ldr r3, [r7, #4]
|
|
800bba0: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800bba2: 687b ldr r3, [r7, #4]
|
|
800bba4: 6a1b ldr r3, [r3, #32]
|
|
800bba6: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800bba8: 687b ldr r3, [r7, #4]
|
|
800bbaa: 685b ldr r3, [r3, #4]
|
|
800bbac: 617b str r3, [r7, #20]
|
|
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800bbae: 687b ldr r3, [r7, #4]
|
|
800bbb0: 69db ldr r3, [r3, #28]
|
|
800bbb2: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
800bbb4: 68fa ldr r2, [r7, #12]
|
|
800bbb6: 4b1e ldr r3, [pc, #120] ; (800bc30 <TIM_OC4_SetConfig+0xa4>)
|
|
800bbb8: 4013 ands r3, r2
|
|
800bbba: 60fb str r3, [r7, #12]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
800bbbc: 68fb ldr r3, [r7, #12]
|
|
800bbbe: f423 7340 bic.w r3, r3, #768 ; 0x300
|
|
800bbc2: 60fb str r3, [r7, #12]
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800bbc4: 683b ldr r3, [r7, #0]
|
|
800bbc6: 681b ldr r3, [r3, #0]
|
|
800bbc8: 021b lsls r3, r3, #8
|
|
800bbca: 68fa ldr r2, [r7, #12]
|
|
800bbcc: 4313 orrs r3, r2
|
|
800bbce: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
800bbd0: 693b ldr r3, [r7, #16]
|
|
800bbd2: f423 5300 bic.w r3, r3, #8192 ; 0x2000
|
|
800bbd6: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
800bbd8: 683b ldr r3, [r7, #0]
|
|
800bbda: 689b ldr r3, [r3, #8]
|
|
800bbdc: 031b lsls r3, r3, #12
|
|
800bbde: 693a ldr r2, [r7, #16]
|
|
800bbe0: 4313 orrs r3, r2
|
|
800bbe2: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800bbe4: 687b ldr r3, [r7, #4]
|
|
800bbe6: 4a13 ldr r2, [pc, #76] ; (800bc34 <TIM_OC4_SetConfig+0xa8>)
|
|
800bbe8: 4293 cmp r3, r2
|
|
800bbea: d003 beq.n 800bbf4 <TIM_OC4_SetConfig+0x68>
|
|
800bbec: 687b ldr r3, [r7, #4]
|
|
800bbee: 4a12 ldr r2, [pc, #72] ; (800bc38 <TIM_OC4_SetConfig+0xac>)
|
|
800bbf0: 4293 cmp r3, r2
|
|
800bbf2: d109 bne.n 800bc08 <TIM_OC4_SetConfig+0x7c>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
800bbf4: 697b ldr r3, [r7, #20]
|
|
800bbf6: f423 4380 bic.w r3, r3, #16384 ; 0x4000
|
|
800bbfa: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
800bbfc: 683b ldr r3, [r7, #0]
|
|
800bbfe: 695b ldr r3, [r3, #20]
|
|
800bc00: 019b lsls r3, r3, #6
|
|
800bc02: 697a ldr r2, [r7, #20]
|
|
800bc04: 4313 orrs r3, r2
|
|
800bc06: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800bc08: 687b ldr r3, [r7, #4]
|
|
800bc0a: 697a ldr r2, [r7, #20]
|
|
800bc0c: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
800bc0e: 687b ldr r3, [r7, #4]
|
|
800bc10: 68fa ldr r2, [r7, #12]
|
|
800bc12: 61da str r2, [r3, #28]
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
800bc14: 683b ldr r3, [r7, #0]
|
|
800bc16: 685a ldr r2, [r3, #4]
|
|
800bc18: 687b ldr r3, [r7, #4]
|
|
800bc1a: 641a str r2, [r3, #64] ; 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800bc1c: 687b ldr r3, [r7, #4]
|
|
800bc1e: 693a ldr r2, [r7, #16]
|
|
800bc20: 621a str r2, [r3, #32]
|
|
}
|
|
800bc22: bf00 nop
|
|
800bc24: 371c adds r7, #28
|
|
800bc26: 46bd mov sp, r7
|
|
800bc28: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bc2c: 4770 bx lr
|
|
800bc2e: bf00 nop
|
|
800bc30: feff8fff .word 0xfeff8fff
|
|
800bc34: 40010000 .word 0x40010000
|
|
800bc38: 40010400 .word 0x40010400
|
|
|
|
0800bc3c <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800bc3c: b480 push {r7}
|
|
800bc3e: b087 sub sp, #28
|
|
800bc40: af00 add r7, sp, #0
|
|
800bc42: 6078 str r0, [r7, #4]
|
|
800bc44: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
800bc46: 687b ldr r3, [r7, #4]
|
|
800bc48: 6a1b ldr r3, [r3, #32]
|
|
800bc4a: f423 3280 bic.w r2, r3, #65536 ; 0x10000
|
|
800bc4e: 687b ldr r3, [r7, #4]
|
|
800bc50: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800bc52: 687b ldr r3, [r7, #4]
|
|
800bc54: 6a1b ldr r3, [r3, #32]
|
|
800bc56: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800bc58: 687b ldr r3, [r7, #4]
|
|
800bc5a: 685b ldr r3, [r3, #4]
|
|
800bc5c: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800bc5e: 687b ldr r3, [r7, #4]
|
|
800bc60: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800bc62: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
800bc64: 68fa ldr r2, [r7, #12]
|
|
800bc66: 4b1b ldr r3, [pc, #108] ; (800bcd4 <TIM_OC5_SetConfig+0x98>)
|
|
800bc68: 4013 ands r3, r2
|
|
800bc6a: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
800bc6c: 683b ldr r3, [r7, #0]
|
|
800bc6e: 681b ldr r3, [r3, #0]
|
|
800bc70: 68fa ldr r2, [r7, #12]
|
|
800bc72: 4313 orrs r3, r2
|
|
800bc74: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
800bc76: 693b ldr r3, [r7, #16]
|
|
800bc78: f423 3300 bic.w r3, r3, #131072 ; 0x20000
|
|
800bc7c: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
800bc7e: 683b ldr r3, [r7, #0]
|
|
800bc80: 689b ldr r3, [r3, #8]
|
|
800bc82: 041b lsls r3, r3, #16
|
|
800bc84: 693a ldr r2, [r7, #16]
|
|
800bc86: 4313 orrs r3, r2
|
|
800bc88: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800bc8a: 687b ldr r3, [r7, #4]
|
|
800bc8c: 4a12 ldr r2, [pc, #72] ; (800bcd8 <TIM_OC5_SetConfig+0x9c>)
|
|
800bc8e: 4293 cmp r3, r2
|
|
800bc90: d003 beq.n 800bc9a <TIM_OC5_SetConfig+0x5e>
|
|
800bc92: 687b ldr r3, [r7, #4]
|
|
800bc94: 4a11 ldr r2, [pc, #68] ; (800bcdc <TIM_OC5_SetConfig+0xa0>)
|
|
800bc96: 4293 cmp r3, r2
|
|
800bc98: d109 bne.n 800bcae <TIM_OC5_SetConfig+0x72>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
800bc9a: 697b ldr r3, [r7, #20]
|
|
800bc9c: f423 3380 bic.w r3, r3, #65536 ; 0x10000
|
|
800bca0: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
800bca2: 683b ldr r3, [r7, #0]
|
|
800bca4: 695b ldr r3, [r3, #20]
|
|
800bca6: 021b lsls r3, r3, #8
|
|
800bca8: 697a ldr r2, [r7, #20]
|
|
800bcaa: 4313 orrs r3, r2
|
|
800bcac: 617b str r3, [r7, #20]
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800bcae: 687b ldr r3, [r7, #4]
|
|
800bcb0: 697a ldr r2, [r7, #20]
|
|
800bcb2: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
800bcb4: 687b ldr r3, [r7, #4]
|
|
800bcb6: 68fa ldr r2, [r7, #12]
|
|
800bcb8: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
800bcba: 683b ldr r3, [r7, #0]
|
|
800bcbc: 685a ldr r2, [r3, #4]
|
|
800bcbe: 687b ldr r3, [r7, #4]
|
|
800bcc0: 659a str r2, [r3, #88] ; 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800bcc2: 687b ldr r3, [r7, #4]
|
|
800bcc4: 693a ldr r2, [r7, #16]
|
|
800bcc6: 621a str r2, [r3, #32]
|
|
}
|
|
800bcc8: bf00 nop
|
|
800bcca: 371c adds r7, #28
|
|
800bccc: 46bd mov sp, r7
|
|
800bcce: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bcd2: 4770 bx lr
|
|
800bcd4: fffeff8f .word 0xfffeff8f
|
|
800bcd8: 40010000 .word 0x40010000
|
|
800bcdc: 40010400 .word 0x40010400
|
|
|
|
0800bce0 <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The ouput configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800bce0: b480 push {r7}
|
|
800bce2: b087 sub sp, #28
|
|
800bce4: af00 add r7, sp, #0
|
|
800bce6: 6078 str r0, [r7, #4]
|
|
800bce8: 6039 str r1, [r7, #0]
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
800bcea: 687b ldr r3, [r7, #4]
|
|
800bcec: 6a1b ldr r3, [r3, #32]
|
|
800bcee: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
|
|
800bcf2: 687b ldr r3, [r7, #4]
|
|
800bcf4: 621a str r2, [r3, #32]
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
800bcf6: 687b ldr r3, [r7, #4]
|
|
800bcf8: 6a1b ldr r3, [r3, #32]
|
|
800bcfa: 613b str r3, [r7, #16]
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800bcfc: 687b ldr r3, [r7, #4]
|
|
800bcfe: 685b ldr r3, [r3, #4]
|
|
800bd00: 617b str r3, [r7, #20]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
800bd02: 687b ldr r3, [r7, #4]
|
|
800bd04: 6d5b ldr r3, [r3, #84] ; 0x54
|
|
800bd06: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
800bd08: 68fa ldr r2, [r7, #12]
|
|
800bd0a: 4b1c ldr r3, [pc, #112] ; (800bd7c <TIM_OC6_SetConfig+0x9c>)
|
|
800bd0c: 4013 ands r3, r2
|
|
800bd0e: 60fb str r3, [r7, #12]
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
800bd10: 683b ldr r3, [r7, #0]
|
|
800bd12: 681b ldr r3, [r3, #0]
|
|
800bd14: 021b lsls r3, r3, #8
|
|
800bd16: 68fa ldr r2, [r7, #12]
|
|
800bd18: 4313 orrs r3, r2
|
|
800bd1a: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
800bd1c: 693b ldr r3, [r7, #16]
|
|
800bd1e: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
|
|
800bd22: 613b str r3, [r7, #16]
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
800bd24: 683b ldr r3, [r7, #0]
|
|
800bd26: 689b ldr r3, [r3, #8]
|
|
800bd28: 051b lsls r3, r3, #20
|
|
800bd2a: 693a ldr r2, [r7, #16]
|
|
800bd2c: 4313 orrs r3, r2
|
|
800bd2e: 613b str r3, [r7, #16]
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
800bd30: 687b ldr r3, [r7, #4]
|
|
800bd32: 4a13 ldr r2, [pc, #76] ; (800bd80 <TIM_OC6_SetConfig+0xa0>)
|
|
800bd34: 4293 cmp r3, r2
|
|
800bd36: d003 beq.n 800bd40 <TIM_OC6_SetConfig+0x60>
|
|
800bd38: 687b ldr r3, [r7, #4]
|
|
800bd3a: 4a12 ldr r2, [pc, #72] ; (800bd84 <TIM_OC6_SetConfig+0xa4>)
|
|
800bd3c: 4293 cmp r3, r2
|
|
800bd3e: d109 bne.n 800bd54 <TIM_OC6_SetConfig+0x74>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
800bd40: 697b ldr r3, [r7, #20]
|
|
800bd42: f423 2380 bic.w r3, r3, #262144 ; 0x40000
|
|
800bd46: 617b str r3, [r7, #20]
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
800bd48: 683b ldr r3, [r7, #0]
|
|
800bd4a: 695b ldr r3, [r3, #20]
|
|
800bd4c: 029b lsls r3, r3, #10
|
|
800bd4e: 697a ldr r2, [r7, #20]
|
|
800bd50: 4313 orrs r3, r2
|
|
800bd52: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
800bd54: 687b ldr r3, [r7, #4]
|
|
800bd56: 697a ldr r2, [r7, #20]
|
|
800bd58: 605a str r2, [r3, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
800bd5a: 687b ldr r3, [r7, #4]
|
|
800bd5c: 68fa ldr r2, [r7, #12]
|
|
800bd5e: 655a str r2, [r3, #84] ; 0x54
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
800bd60: 683b ldr r3, [r7, #0]
|
|
800bd62: 685a ldr r2, [r3, #4]
|
|
800bd64: 687b ldr r3, [r7, #4]
|
|
800bd66: 65da str r2, [r3, #92] ; 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
800bd68: 687b ldr r3, [r7, #4]
|
|
800bd6a: 693a ldr r2, [r7, #16]
|
|
800bd6c: 621a str r2, [r3, #32]
|
|
}
|
|
800bd6e: bf00 nop
|
|
800bd70: 371c adds r7, #28
|
|
800bd72: 46bd mov sp, r7
|
|
800bd74: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bd78: 4770 bx lr
|
|
800bd7a: bf00 nop
|
|
800bd7c: feff8fff .word 0xfeff8fff
|
|
800bd80: 40010000 .word 0x40010000
|
|
800bd84: 40010400 .word 0x40010400
|
|
|
|
0800bd88 <TIM_SlaveTimer_SetConfig>:
|
|
* @param sSlaveConfig Slave timer configuration
|
|
* @retval None
|
|
*/
|
|
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
|
|
TIM_SlaveConfigTypeDef *sSlaveConfig)
|
|
{
|
|
800bd88: b580 push {r7, lr}
|
|
800bd8a: b086 sub sp, #24
|
|
800bd8c: af00 add r7, sp, #0
|
|
800bd8e: 6078 str r0, [r7, #4]
|
|
800bd90: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800bd92: 687b ldr r3, [r7, #4]
|
|
800bd94: 681b ldr r3, [r3, #0]
|
|
800bd96: 689b ldr r3, [r3, #8]
|
|
800bd98: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the Trigger Selection Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
800bd9a: 697b ldr r3, [r7, #20]
|
|
800bd9c: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
800bda0: 617b str r3, [r7, #20]
|
|
/* Set the Input Trigger source */
|
|
tmpsmcr |= sSlaveConfig->InputTrigger;
|
|
800bda2: 683b ldr r3, [r7, #0]
|
|
800bda4: 685b ldr r3, [r3, #4]
|
|
800bda6: 697a ldr r2, [r7, #20]
|
|
800bda8: 4313 orrs r3, r2
|
|
800bdaa: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the slave mode Bits */
|
|
tmpsmcr &= ~TIM_SMCR_SMS;
|
|
800bdac: 697a ldr r2, [r7, #20]
|
|
800bdae: 4b39 ldr r3, [pc, #228] ; (800be94 <TIM_SlaveTimer_SetConfig+0x10c>)
|
|
800bdb0: 4013 ands r3, r2
|
|
800bdb2: 617b str r3, [r7, #20]
|
|
/* Set the slave mode */
|
|
tmpsmcr |= sSlaveConfig->SlaveMode;
|
|
800bdb4: 683b ldr r3, [r7, #0]
|
|
800bdb6: 681b ldr r3, [r3, #0]
|
|
800bdb8: 697a ldr r2, [r7, #20]
|
|
800bdba: 4313 orrs r3, r2
|
|
800bdbc: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800bdbe: 687b ldr r3, [r7, #4]
|
|
800bdc0: 681b ldr r3, [r3, #0]
|
|
800bdc2: 697a ldr r2, [r7, #20]
|
|
800bdc4: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the trigger prescaler, filter, and polarity */
|
|
switch (sSlaveConfig->InputTrigger)
|
|
800bdc6: 683b ldr r3, [r7, #0]
|
|
800bdc8: 685b ldr r3, [r3, #4]
|
|
800bdca: 2b30 cmp r3, #48 ; 0x30
|
|
800bdcc: d05c beq.n 800be88 <TIM_SlaveTimer_SetConfig+0x100>
|
|
800bdce: 2b30 cmp r3, #48 ; 0x30
|
|
800bdd0: d806 bhi.n 800bde0 <TIM_SlaveTimer_SetConfig+0x58>
|
|
800bdd2: 2b10 cmp r3, #16
|
|
800bdd4: d058 beq.n 800be88 <TIM_SlaveTimer_SetConfig+0x100>
|
|
800bdd6: 2b20 cmp r3, #32
|
|
800bdd8: d056 beq.n 800be88 <TIM_SlaveTimer_SetConfig+0x100>
|
|
800bdda: 2b00 cmp r3, #0
|
|
800bddc: d054 beq.n 800be88 <TIM_SlaveTimer_SetConfig+0x100>
|
|
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
|
|
break;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
800bdde: e054 b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
switch (sSlaveConfig->InputTrigger)
|
|
800bde0: 2b50 cmp r3, #80 ; 0x50
|
|
800bde2: d03d beq.n 800be60 <TIM_SlaveTimer_SetConfig+0xd8>
|
|
800bde4: 2b50 cmp r3, #80 ; 0x50
|
|
800bde6: d802 bhi.n 800bdee <TIM_SlaveTimer_SetConfig+0x66>
|
|
800bde8: 2b40 cmp r3, #64 ; 0x40
|
|
800bdea: d010 beq.n 800be0e <TIM_SlaveTimer_SetConfig+0x86>
|
|
break;
|
|
800bdec: e04d b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
switch (sSlaveConfig->InputTrigger)
|
|
800bdee: 2b60 cmp r3, #96 ; 0x60
|
|
800bdf0: d040 beq.n 800be74 <TIM_SlaveTimer_SetConfig+0xec>
|
|
800bdf2: 2b70 cmp r3, #112 ; 0x70
|
|
800bdf4: d000 beq.n 800bdf8 <TIM_SlaveTimer_SetConfig+0x70>
|
|
break;
|
|
800bdf6: e048 b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800bdf8: 687b ldr r3, [r7, #4]
|
|
800bdfa: 6818 ldr r0, [r3, #0]
|
|
800bdfc: 683b ldr r3, [r7, #0]
|
|
800bdfe: 68d9 ldr r1, [r3, #12]
|
|
800be00: 683b ldr r3, [r7, #0]
|
|
800be02: 689a ldr r2, [r3, #8]
|
|
800be04: 683b ldr r3, [r7, #0]
|
|
800be06: 691b ldr r3, [r3, #16]
|
|
800be08: f000 f8c0 bl 800bf8c <TIM_ETR_SetConfig>
|
|
break;
|
|
800be0c: e03d b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
|
|
800be0e: 683b ldr r3, [r7, #0]
|
|
800be10: 681b ldr r3, [r3, #0]
|
|
800be12: 2b05 cmp r3, #5
|
|
800be14: d101 bne.n 800be1a <TIM_SlaveTimer_SetConfig+0x92>
|
|
return HAL_ERROR;
|
|
800be16: 2301 movs r3, #1
|
|
800be18: e038 b.n 800be8c <TIM_SlaveTimer_SetConfig+0x104>
|
|
tmpccer = htim->Instance->CCER;
|
|
800be1a: 687b ldr r3, [r7, #4]
|
|
800be1c: 681b ldr r3, [r3, #0]
|
|
800be1e: 6a1b ldr r3, [r3, #32]
|
|
800be20: 613b str r3, [r7, #16]
|
|
htim->Instance->CCER &= ~TIM_CCER_CC1E;
|
|
800be22: 687b ldr r3, [r7, #4]
|
|
800be24: 681b ldr r3, [r3, #0]
|
|
800be26: 6a1a ldr r2, [r3, #32]
|
|
800be28: 687b ldr r3, [r7, #4]
|
|
800be2a: 681b ldr r3, [r3, #0]
|
|
800be2c: f022 0201 bic.w r2, r2, #1
|
|
800be30: 621a str r2, [r3, #32]
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
800be32: 687b ldr r3, [r7, #4]
|
|
800be34: 681b ldr r3, [r3, #0]
|
|
800be36: 699b ldr r3, [r3, #24]
|
|
800be38: 60fb str r3, [r7, #12]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
800be3a: 68fb ldr r3, [r7, #12]
|
|
800be3c: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
800be40: 60fb str r3, [r7, #12]
|
|
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
|
|
800be42: 683b ldr r3, [r7, #0]
|
|
800be44: 691b ldr r3, [r3, #16]
|
|
800be46: 011b lsls r3, r3, #4
|
|
800be48: 68fa ldr r2, [r7, #12]
|
|
800be4a: 4313 orrs r3, r2
|
|
800be4c: 60fb str r3, [r7, #12]
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
800be4e: 687b ldr r3, [r7, #4]
|
|
800be50: 681b ldr r3, [r3, #0]
|
|
800be52: 68fa ldr r2, [r7, #12]
|
|
800be54: 619a str r2, [r3, #24]
|
|
htim->Instance->CCER = tmpccer;
|
|
800be56: 687b ldr r3, [r7, #4]
|
|
800be58: 681b ldr r3, [r3, #0]
|
|
800be5a: 693a ldr r2, [r7, #16]
|
|
800be5c: 621a str r2, [r3, #32]
|
|
break;
|
|
800be5e: e014 b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
800be60: 687b ldr r3, [r7, #4]
|
|
800be62: 6818 ldr r0, [r3, #0]
|
|
800be64: 683b ldr r3, [r7, #0]
|
|
800be66: 6899 ldr r1, [r3, #8]
|
|
800be68: 683b ldr r3, [r7, #0]
|
|
800be6a: 691b ldr r3, [r3, #16]
|
|
800be6c: 461a mov r2, r3
|
|
800be6e: f000 f813 bl 800be98 <TIM_TI1_ConfigInputStage>
|
|
break;
|
|
800be72: e00a b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
800be74: 687b ldr r3, [r7, #4]
|
|
800be76: 6818 ldr r0, [r3, #0]
|
|
800be78: 683b ldr r3, [r7, #0]
|
|
800be7a: 6899 ldr r1, [r3, #8]
|
|
800be7c: 683b ldr r3, [r7, #0]
|
|
800be7e: 691b ldr r3, [r3, #16]
|
|
800be80: 461a mov r2, r3
|
|
800be82: f000 f838 bl 800bef6 <TIM_TI2_ConfigInputStage>
|
|
break;
|
|
800be86: e000 b.n 800be8a <TIM_SlaveTimer_SetConfig+0x102>
|
|
break;
|
|
800be88: bf00 nop
|
|
}
|
|
return HAL_OK;
|
|
800be8a: 2300 movs r3, #0
|
|
}
|
|
800be8c: 4618 mov r0, r3
|
|
800be8e: 3718 adds r7, #24
|
|
800be90: 46bd mov sp, r7
|
|
800be92: bd80 pop {r7, pc}
|
|
800be94: fffefff8 .word 0xfffefff8
|
|
|
|
0800be98 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
800be98: b480 push {r7}
|
|
800be9a: b087 sub sp, #28
|
|
800be9c: af00 add r7, sp, #0
|
|
800be9e: 60f8 str r0, [r7, #12]
|
|
800bea0: 60b9 str r1, [r7, #8]
|
|
800bea2: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
800bea4: 68fb ldr r3, [r7, #12]
|
|
800bea6: 6a1b ldr r3, [r3, #32]
|
|
800bea8: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800beaa: 68fb ldr r3, [r7, #12]
|
|
800beac: 6a1b ldr r3, [r3, #32]
|
|
800beae: f023 0201 bic.w r2, r3, #1
|
|
800beb2: 68fb ldr r3, [r7, #12]
|
|
800beb4: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
800beb6: 68fb ldr r3, [r7, #12]
|
|
800beb8: 699b ldr r3, [r3, #24]
|
|
800beba: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
800bebc: 693b ldr r3, [r7, #16]
|
|
800bebe: f023 03f0 bic.w r3, r3, #240 ; 0xf0
|
|
800bec2: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
800bec4: 687b ldr r3, [r7, #4]
|
|
800bec6: 011b lsls r3, r3, #4
|
|
800bec8: 693a ldr r2, [r7, #16]
|
|
800beca: 4313 orrs r3, r2
|
|
800becc: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
800bece: 697b ldr r3, [r7, #20]
|
|
800bed0: f023 030a bic.w r3, r3, #10
|
|
800bed4: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
800bed6: 697a ldr r2, [r7, #20]
|
|
800bed8: 68bb ldr r3, [r7, #8]
|
|
800beda: 4313 orrs r3, r2
|
|
800bedc: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
800bede: 68fb ldr r3, [r7, #12]
|
|
800bee0: 693a ldr r2, [r7, #16]
|
|
800bee2: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
800bee4: 68fb ldr r3, [r7, #12]
|
|
800bee6: 697a ldr r2, [r7, #20]
|
|
800bee8: 621a str r2, [r3, #32]
|
|
}
|
|
800beea: bf00 nop
|
|
800beec: 371c adds r7, #28
|
|
800beee: 46bd mov sp, r7
|
|
800bef0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bef4: 4770 bx lr
|
|
|
|
0800bef6 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
800bef6: b480 push {r7}
|
|
800bef8: b087 sub sp, #28
|
|
800befa: af00 add r7, sp, #0
|
|
800befc: 60f8 str r0, [r7, #12]
|
|
800befe: 60b9 str r1, [r7, #8]
|
|
800bf00: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800bf02: 68fb ldr r3, [r7, #12]
|
|
800bf04: 6a1b ldr r3, [r3, #32]
|
|
800bf06: f023 0210 bic.w r2, r3, #16
|
|
800bf0a: 68fb ldr r3, [r7, #12]
|
|
800bf0c: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
800bf0e: 68fb ldr r3, [r7, #12]
|
|
800bf10: 699b ldr r3, [r3, #24]
|
|
800bf12: 617b str r3, [r7, #20]
|
|
tmpccer = TIMx->CCER;
|
|
800bf14: 68fb ldr r3, [r7, #12]
|
|
800bf16: 6a1b ldr r3, [r3, #32]
|
|
800bf18: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
800bf1a: 697b ldr r3, [r7, #20]
|
|
800bf1c: f423 4370 bic.w r3, r3, #61440 ; 0xf000
|
|
800bf20: 617b str r3, [r7, #20]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
800bf22: 687b ldr r3, [r7, #4]
|
|
800bf24: 031b lsls r3, r3, #12
|
|
800bf26: 697a ldr r2, [r7, #20]
|
|
800bf28: 4313 orrs r3, r2
|
|
800bf2a: 617b str r3, [r7, #20]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
800bf2c: 693b ldr r3, [r7, #16]
|
|
800bf2e: f023 03a0 bic.w r3, r3, #160 ; 0xa0
|
|
800bf32: 613b str r3, [r7, #16]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
800bf34: 68bb ldr r3, [r7, #8]
|
|
800bf36: 011b lsls r3, r3, #4
|
|
800bf38: 693a ldr r2, [r7, #16]
|
|
800bf3a: 4313 orrs r3, r2
|
|
800bf3c: 613b str r3, [r7, #16]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
800bf3e: 68fb ldr r3, [r7, #12]
|
|
800bf40: 697a ldr r2, [r7, #20]
|
|
800bf42: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
800bf44: 68fb ldr r3, [r7, #12]
|
|
800bf46: 693a ldr r2, [r7, #16]
|
|
800bf48: 621a str r2, [r3, #32]
|
|
}
|
|
800bf4a: bf00 nop
|
|
800bf4c: 371c adds r7, #28
|
|
800bf4e: 46bd mov sp, r7
|
|
800bf50: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bf54: 4770 bx lr
|
|
|
|
0800bf56 <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
800bf56: b480 push {r7}
|
|
800bf58: b085 sub sp, #20
|
|
800bf5a: af00 add r7, sp, #0
|
|
800bf5c: 6078 str r0, [r7, #4]
|
|
800bf5e: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
800bf60: 687b ldr r3, [r7, #4]
|
|
800bf62: 689b ldr r3, [r3, #8]
|
|
800bf64: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
800bf66: 68fb ldr r3, [r7, #12]
|
|
800bf68: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
800bf6c: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
800bf6e: 683a ldr r2, [r7, #0]
|
|
800bf70: 68fb ldr r3, [r7, #12]
|
|
800bf72: 4313 orrs r3, r2
|
|
800bf74: f043 0307 orr.w r3, r3, #7
|
|
800bf78: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
800bf7a: 687b ldr r3, [r7, #4]
|
|
800bf7c: 68fa ldr r2, [r7, #12]
|
|
800bf7e: 609a str r2, [r3, #8]
|
|
}
|
|
800bf80: bf00 nop
|
|
800bf82: 3714 adds r7, #20
|
|
800bf84: 46bd mov sp, r7
|
|
800bf86: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bf8a: 4770 bx lr
|
|
|
|
0800bf8c <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
800bf8c: b480 push {r7}
|
|
800bf8e: b087 sub sp, #28
|
|
800bf90: af00 add r7, sp, #0
|
|
800bf92: 60f8 str r0, [r7, #12]
|
|
800bf94: 60b9 str r1, [r7, #8]
|
|
800bf96: 607a str r2, [r7, #4]
|
|
800bf98: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
800bf9a: 68fb ldr r3, [r7, #12]
|
|
800bf9c: 689b ldr r3, [r3, #8]
|
|
800bf9e: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
800bfa0: 697b ldr r3, [r7, #20]
|
|
800bfa2: f423 437f bic.w r3, r3, #65280 ; 0xff00
|
|
800bfa6: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
800bfa8: 683b ldr r3, [r7, #0]
|
|
800bfaa: 021a lsls r2, r3, #8
|
|
800bfac: 687b ldr r3, [r7, #4]
|
|
800bfae: 431a orrs r2, r3
|
|
800bfb0: 68bb ldr r3, [r7, #8]
|
|
800bfb2: 4313 orrs r3, r2
|
|
800bfb4: 697a ldr r2, [r7, #20]
|
|
800bfb6: 4313 orrs r3, r2
|
|
800bfb8: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
800bfba: 68fb ldr r3, [r7, #12]
|
|
800bfbc: 697a ldr r2, [r7, #20]
|
|
800bfbe: 609a str r2, [r3, #8]
|
|
}
|
|
800bfc0: bf00 nop
|
|
800bfc2: 371c adds r7, #28
|
|
800bfc4: 46bd mov sp, r7
|
|
800bfc6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bfca: 4770 bx lr
|
|
|
|
0800bfcc <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
800bfcc: b480 push {r7}
|
|
800bfce: b085 sub sp, #20
|
|
800bfd0: af00 add r7, sp, #0
|
|
800bfd2: 6078 str r0, [r7, #4]
|
|
800bfd4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
800bfd6: 687b ldr r3, [r7, #4]
|
|
800bfd8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800bfdc: 2b01 cmp r3, #1
|
|
800bfde: d101 bne.n 800bfe4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
800bfe0: 2302 movs r3, #2
|
|
800bfe2: e06d b.n 800c0c0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>
|
|
800bfe4: 687b ldr r3, [r7, #4]
|
|
800bfe6: 2201 movs r2, #1
|
|
800bfe8: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800bfec: 687b ldr r3, [r7, #4]
|
|
800bfee: 2202 movs r2, #2
|
|
800bff0: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
800bff4: 687b ldr r3, [r7, #4]
|
|
800bff6: 681b ldr r3, [r3, #0]
|
|
800bff8: 685b ldr r3, [r3, #4]
|
|
800bffa: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800bffc: 687b ldr r3, [r7, #4]
|
|
800bffe: 681b ldr r3, [r3, #0]
|
|
800c000: 689b ldr r3, [r3, #8]
|
|
800c002: 60bb str r3, [r7, #8]
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
800c004: 687b ldr r3, [r7, #4]
|
|
800c006: 681b ldr r3, [r3, #0]
|
|
800c008: 4a30 ldr r2, [pc, #192] ; (800c0cc <HAL_TIMEx_MasterConfigSynchronization+0x100>)
|
|
800c00a: 4293 cmp r3, r2
|
|
800c00c: d004 beq.n 800c018 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
|
|
800c00e: 687b ldr r3, [r7, #4]
|
|
800c010: 681b ldr r3, [r3, #0]
|
|
800c012: 4a2f ldr r2, [pc, #188] ; (800c0d0 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
|
|
800c014: 4293 cmp r3, r2
|
|
800c016: d108 bne.n 800c02a <HAL_TIMEx_MasterConfigSynchronization+0x5e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
800c018: 68fb ldr r3, [r7, #12]
|
|
800c01a: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
|
|
800c01e: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
800c020: 683b ldr r3, [r7, #0]
|
|
800c022: 685b ldr r3, [r3, #4]
|
|
800c024: 68fa ldr r2, [r7, #12]
|
|
800c026: 4313 orrs r3, r2
|
|
800c028: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
800c02a: 68fb ldr r3, [r7, #12]
|
|
800c02c: f023 0370 bic.w r3, r3, #112 ; 0x70
|
|
800c030: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
800c032: 683b ldr r3, [r7, #0]
|
|
800c034: 681b ldr r3, [r3, #0]
|
|
800c036: 68fa ldr r2, [r7, #12]
|
|
800c038: 4313 orrs r3, r2
|
|
800c03a: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
800c03c: 687b ldr r3, [r7, #4]
|
|
800c03e: 681b ldr r3, [r3, #0]
|
|
800c040: 68fa ldr r2, [r7, #12]
|
|
800c042: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800c044: 687b ldr r3, [r7, #4]
|
|
800c046: 681b ldr r3, [r3, #0]
|
|
800c048: 4a20 ldr r2, [pc, #128] ; (800c0cc <HAL_TIMEx_MasterConfigSynchronization+0x100>)
|
|
800c04a: 4293 cmp r3, r2
|
|
800c04c: d022 beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c04e: 687b ldr r3, [r7, #4]
|
|
800c050: 681b ldr r3, [r3, #0]
|
|
800c052: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
800c056: d01d beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c058: 687b ldr r3, [r7, #4]
|
|
800c05a: 681b ldr r3, [r3, #0]
|
|
800c05c: 4a1d ldr r2, [pc, #116] ; (800c0d4 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
|
|
800c05e: 4293 cmp r3, r2
|
|
800c060: d018 beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c062: 687b ldr r3, [r7, #4]
|
|
800c064: 681b ldr r3, [r3, #0]
|
|
800c066: 4a1c ldr r2, [pc, #112] ; (800c0d8 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
|
|
800c068: 4293 cmp r3, r2
|
|
800c06a: d013 beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c06c: 687b ldr r3, [r7, #4]
|
|
800c06e: 681b ldr r3, [r3, #0]
|
|
800c070: 4a1a ldr r2, [pc, #104] ; (800c0dc <HAL_TIMEx_MasterConfigSynchronization+0x110>)
|
|
800c072: 4293 cmp r3, r2
|
|
800c074: d00e beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c076: 687b ldr r3, [r7, #4]
|
|
800c078: 681b ldr r3, [r3, #0]
|
|
800c07a: 4a15 ldr r2, [pc, #84] ; (800c0d0 <HAL_TIMEx_MasterConfigSynchronization+0x104>)
|
|
800c07c: 4293 cmp r3, r2
|
|
800c07e: d009 beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c080: 687b ldr r3, [r7, #4]
|
|
800c082: 681b ldr r3, [r3, #0]
|
|
800c084: 4a16 ldr r2, [pc, #88] ; (800c0e0 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
|
|
800c086: 4293 cmp r3, r2
|
|
800c088: d004 beq.n 800c094 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
|
|
800c08a: 687b ldr r3, [r7, #4]
|
|
800c08c: 681b ldr r3, [r3, #0]
|
|
800c08e: 4a15 ldr r2, [pc, #84] ; (800c0e4 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
|
|
800c090: 4293 cmp r3, r2
|
|
800c092: d10c bne.n 800c0ae <HAL_TIMEx_MasterConfigSynchronization+0xe2>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
800c094: 68bb ldr r3, [r7, #8]
|
|
800c096: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
800c09a: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
800c09c: 683b ldr r3, [r7, #0]
|
|
800c09e: 689b ldr r3, [r3, #8]
|
|
800c0a0: 68ba ldr r2, [r7, #8]
|
|
800c0a2: 4313 orrs r3, r2
|
|
800c0a4: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800c0a6: 687b ldr r3, [r7, #4]
|
|
800c0a8: 681b ldr r3, [r3, #0]
|
|
800c0aa: 68ba ldr r2, [r7, #8]
|
|
800c0ac: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800c0ae: 687b ldr r3, [r7, #4]
|
|
800c0b0: 2201 movs r2, #1
|
|
800c0b2: f883 203d strb.w r2, [r3, #61] ; 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800c0b6: 687b ldr r3, [r7, #4]
|
|
800c0b8: 2200 movs r2, #0
|
|
800c0ba: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800c0be: 2300 movs r3, #0
|
|
}
|
|
800c0c0: 4618 mov r0, r3
|
|
800c0c2: 3714 adds r7, #20
|
|
800c0c4: 46bd mov sp, r7
|
|
800c0c6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c0ca: 4770 bx lr
|
|
800c0cc: 40010000 .word 0x40010000
|
|
800c0d0: 40010400 .word 0x40010400
|
|
800c0d4: 40000400 .word 0x40000400
|
|
800c0d8: 40000800 .word 0x40000800
|
|
800c0dc: 40000c00 .word 0x40000c00
|
|
800c0e0: 40014000 .word 0x40014000
|
|
800c0e4: 40001800 .word 0x40001800
|
|
|
|
0800c0e8 <HAL_TIMEx_ConfigBreakDeadTime>:
|
|
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
|
|
{
|
|
800c0e8: b480 push {r7}
|
|
800c0ea: b085 sub sp, #20
|
|
800c0ec: af00 add r7, sp, #0
|
|
800c0ee: 6078 str r0, [r7, #4]
|
|
800c0f0: 6039 str r1, [r7, #0]
|
|
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
|
|
uint32_t tmpbdtr = 0U;
|
|
800c0f2: 2300 movs r3, #0
|
|
800c0f4: 60fb str r3, [r7, #12]
|
|
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
800c0f6: 687b ldr r3, [r7, #4]
|
|
800c0f8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
|
|
800c0fc: 2b01 cmp r3, #1
|
|
800c0fe: d101 bne.n 800c104 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
|
|
800c100: 2302 movs r3, #2
|
|
800c102: e065 b.n 800c1d0 <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
|
|
800c104: 687b ldr r3, [r7, #4]
|
|
800c106: 2201 movs r2, #1
|
|
800c108: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
800c10c: 68fb ldr r3, [r7, #12]
|
|
800c10e: f023 02ff bic.w r2, r3, #255 ; 0xff
|
|
800c112: 683b ldr r3, [r7, #0]
|
|
800c114: 68db ldr r3, [r3, #12]
|
|
800c116: 4313 orrs r3, r2
|
|
800c118: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
800c11a: 68fb ldr r3, [r7, #12]
|
|
800c11c: f423 7240 bic.w r2, r3, #768 ; 0x300
|
|
800c120: 683b ldr r3, [r7, #0]
|
|
800c122: 689b ldr r3, [r3, #8]
|
|
800c124: 4313 orrs r3, r2
|
|
800c126: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
800c128: 68fb ldr r3, [r7, #12]
|
|
800c12a: f423 6280 bic.w r2, r3, #1024 ; 0x400
|
|
800c12e: 683b ldr r3, [r7, #0]
|
|
800c130: 685b ldr r3, [r3, #4]
|
|
800c132: 4313 orrs r3, r2
|
|
800c134: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
800c136: 68fb ldr r3, [r7, #12]
|
|
800c138: f423 6200 bic.w r2, r3, #2048 ; 0x800
|
|
800c13c: 683b ldr r3, [r7, #0]
|
|
800c13e: 681b ldr r3, [r3, #0]
|
|
800c140: 4313 orrs r3, r2
|
|
800c142: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
800c144: 68fb ldr r3, [r7, #12]
|
|
800c146: f423 5280 bic.w r2, r3, #4096 ; 0x1000
|
|
800c14a: 683b ldr r3, [r7, #0]
|
|
800c14c: 691b ldr r3, [r3, #16]
|
|
800c14e: 4313 orrs r3, r2
|
|
800c150: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
800c152: 68fb ldr r3, [r7, #12]
|
|
800c154: f423 5200 bic.w r2, r3, #8192 ; 0x2000
|
|
800c158: 683b ldr r3, [r7, #0]
|
|
800c15a: 695b ldr r3, [r3, #20]
|
|
800c15c: 4313 orrs r3, r2
|
|
800c15e: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
800c160: 68fb ldr r3, [r7, #12]
|
|
800c162: f423 4280 bic.w r2, r3, #16384 ; 0x4000
|
|
800c166: 683b ldr r3, [r7, #0]
|
|
800c168: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800c16a: 4313 orrs r3, r2
|
|
800c16c: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
|
800c16e: 68fb ldr r3, [r7, #12]
|
|
800c170: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
|
|
800c174: 683b ldr r3, [r7, #0]
|
|
800c176: 699b ldr r3, [r3, #24]
|
|
800c178: 041b lsls r3, r3, #16
|
|
800c17a: 4313 orrs r3, r2
|
|
800c17c: 60fb str r3, [r7, #12]
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
800c17e: 687b ldr r3, [r7, #4]
|
|
800c180: 681b ldr r3, [r3, #0]
|
|
800c182: 4a16 ldr r2, [pc, #88] ; (800c1dc <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
|
|
800c184: 4293 cmp r3, r2
|
|
800c186: d004 beq.n 800c192 <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
|
|
800c188: 687b ldr r3, [r7, #4]
|
|
800c18a: 681b ldr r3, [r3, #0]
|
|
800c18c: 4a14 ldr r2, [pc, #80] ; (800c1e0 <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
|
|
800c18e: 4293 cmp r3, r2
|
|
800c190: d115 bne.n 800c1be <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
|
|
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
|
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
|
|
/* Set the BREAK2 input related BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
|
800c192: 68fb ldr r3, [r7, #12]
|
|
800c194: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
|
|
800c198: 683b ldr r3, [r7, #0]
|
|
800c19a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c19c: 051b lsls r3, r3, #20
|
|
800c19e: 4313 orrs r3, r2
|
|
800c1a0: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
800c1a2: 68fb ldr r3, [r7, #12]
|
|
800c1a4: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
|
|
800c1a8: 683b ldr r3, [r7, #0]
|
|
800c1aa: 69db ldr r3, [r3, #28]
|
|
800c1ac: 4313 orrs r3, r2
|
|
800c1ae: 60fb str r3, [r7, #12]
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
800c1b0: 68fb ldr r3, [r7, #12]
|
|
800c1b2: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
|
|
800c1b6: 683b ldr r3, [r7, #0]
|
|
800c1b8: 6a1b ldr r3, [r3, #32]
|
|
800c1ba: 4313 orrs r3, r2
|
|
800c1bc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set TIMx_BDTR */
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
800c1be: 687b ldr r3, [r7, #4]
|
|
800c1c0: 681b ldr r3, [r3, #0]
|
|
800c1c2: 68fa ldr r2, [r7, #12]
|
|
800c1c4: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800c1c6: 687b ldr r3, [r7, #4]
|
|
800c1c8: 2200 movs r2, #0
|
|
800c1ca: f883 203c strb.w r2, [r3, #60] ; 0x3c
|
|
|
|
return HAL_OK;
|
|
800c1ce: 2300 movs r3, #0
|
|
}
|
|
800c1d0: 4618 mov r0, r3
|
|
800c1d2: 3714 adds r7, #20
|
|
800c1d4: 46bd mov sp, r7
|
|
800c1d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c1da: 4770 bx lr
|
|
800c1dc: 40010000 .word 0x40010000
|
|
800c1e0: 40010400 .word 0x40010400
|
|
|
|
0800c1e4 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Hall commutation changed callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800c1e4: b480 push {r7}
|
|
800c1e6: b083 sub sp, #12
|
|
800c1e8: af00 add r7, sp, #0
|
|
800c1ea: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800c1ec: bf00 nop
|
|
800c1ee: 370c adds r7, #12
|
|
800c1f0: 46bd mov sp, r7
|
|
800c1f2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c1f6: 4770 bx lr
|
|
|
|
0800c1f8 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Hall Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800c1f8: b480 push {r7}
|
|
800c1fa: b083 sub sp, #12
|
|
800c1fc: af00 add r7, sp, #0
|
|
800c1fe: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800c200: bf00 nop
|
|
800c202: 370c adds r7, #12
|
|
800c204: 46bd mov sp, r7
|
|
800c206: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c20a: 4770 bx lr
|
|
|
|
0800c20c <HAL_TIMEx_Break2Callback>:
|
|
* @brief Hall Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800c20c: b480 push {r7}
|
|
800c20e: b083 sub sp, #12
|
|
800c210: af00 add r7, sp, #0
|
|
800c212: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_Break2Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
800c214: bf00 nop
|
|
800c216: 370c adds r7, #12
|
|
800c218: 46bd mov sp, r7
|
|
800c21a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c21e: 4770 bx lr
|
|
|
|
0800c220 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
800c220: b580 push {r7, lr}
|
|
800c222: b082 sub sp, #8
|
|
800c224: af00 add r7, sp, #0
|
|
800c226: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
800c228: 687b ldr r3, [r7, #4]
|
|
800c22a: 2b00 cmp r3, #0
|
|
800c22c: d101 bne.n 800c232 <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800c22e: 2301 movs r3, #1
|
|
800c230: e040 b.n 800c2b4 <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
800c232: 687b ldr r3, [r7, #4]
|
|
800c234: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
800c236: 2b00 cmp r3, #0
|
|
800c238: d106 bne.n 800c248 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800c23a: 687b ldr r3, [r7, #4]
|
|
800c23c: 2200 movs r2, #0
|
|
800c23e: f883 2070 strb.w r2, [r3, #112] ; 0x70
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
800c242: 6878 ldr r0, [r7, #4]
|
|
800c244: f7f8 fd56 bl 8004cf4 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800c248: 687b ldr r3, [r7, #4]
|
|
800c24a: 2224 movs r2, #36 ; 0x24
|
|
800c24c: 675a str r2, [r3, #116] ; 0x74
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
800c24e: 687b ldr r3, [r7, #4]
|
|
800c250: 681b ldr r3, [r3, #0]
|
|
800c252: 681a ldr r2, [r3, #0]
|
|
800c254: 687b ldr r3, [r7, #4]
|
|
800c256: 681b ldr r3, [r3, #0]
|
|
800c258: f022 0201 bic.w r2, r2, #1
|
|
800c25c: 601a str r2, [r3, #0]
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
800c25e: 6878 ldr r0, [r7, #4]
|
|
800c260: f000 f82c bl 800c2bc <UART_SetConfig>
|
|
800c264: 4603 mov r3, r0
|
|
800c266: 2b01 cmp r3, #1
|
|
800c268: d101 bne.n 800c26e <HAL_UART_Init+0x4e>
|
|
{
|
|
return HAL_ERROR;
|
|
800c26a: 2301 movs r3, #1
|
|
800c26c: e022 b.n 800c2b4 <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
800c26e: 687b ldr r3, [r7, #4]
|
|
800c270: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c272: 2b00 cmp r3, #0
|
|
800c274: d002 beq.n 800c27c <HAL_UART_Init+0x5c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
800c276: 6878 ldr r0, [r7, #4]
|
|
800c278: f000 faca bl 800c810 <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
800c27c: 687b ldr r3, [r7, #4]
|
|
800c27e: 681b ldr r3, [r3, #0]
|
|
800c280: 685a ldr r2, [r3, #4]
|
|
800c282: 687b ldr r3, [r7, #4]
|
|
800c284: 681b ldr r3, [r3, #0]
|
|
800c286: f422 4290 bic.w r2, r2, #18432 ; 0x4800
|
|
800c28a: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
800c28c: 687b ldr r3, [r7, #4]
|
|
800c28e: 681b ldr r3, [r3, #0]
|
|
800c290: 689a ldr r2, [r3, #8]
|
|
800c292: 687b ldr r3, [r7, #4]
|
|
800c294: 681b ldr r3, [r3, #0]
|
|
800c296: f022 022a bic.w r2, r2, #42 ; 0x2a
|
|
800c29a: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
800c29c: 687b ldr r3, [r7, #4]
|
|
800c29e: 681b ldr r3, [r3, #0]
|
|
800c2a0: 681a ldr r2, [r3, #0]
|
|
800c2a2: 687b ldr r3, [r7, #4]
|
|
800c2a4: 681b ldr r3, [r3, #0]
|
|
800c2a6: f042 0201 orr.w r2, r2, #1
|
|
800c2aa: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
800c2ac: 6878 ldr r0, [r7, #4]
|
|
800c2ae: f000 fb51 bl 800c954 <UART_CheckIdleState>
|
|
800c2b2: 4603 mov r3, r0
|
|
}
|
|
800c2b4: 4618 mov r0, r3
|
|
800c2b6: 3708 adds r7, #8
|
|
800c2b8: 46bd mov sp, r7
|
|
800c2ba: bd80 pop {r7, pc}
|
|
|
|
0800c2bc <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800c2bc: b580 push {r7, lr}
|
|
800c2be: b088 sub sp, #32
|
|
800c2c0: af00 add r7, sp, #0
|
|
800c2c2: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv = 0x00000000U;
|
|
800c2c4: 2300 movs r3, #0
|
|
800c2c6: 61bb str r3, [r7, #24]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
800c2c8: 2300 movs r3, #0
|
|
800c2ca: 75fb strb r3, [r7, #23]
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
800c2cc: 687b ldr r3, [r7, #4]
|
|
800c2ce: 689a ldr r2, [r3, #8]
|
|
800c2d0: 687b ldr r3, [r7, #4]
|
|
800c2d2: 691b ldr r3, [r3, #16]
|
|
800c2d4: 431a orrs r2, r3
|
|
800c2d6: 687b ldr r3, [r7, #4]
|
|
800c2d8: 695b ldr r3, [r3, #20]
|
|
800c2da: 431a orrs r2, r3
|
|
800c2dc: 687b ldr r3, [r7, #4]
|
|
800c2de: 69db ldr r3, [r3, #28]
|
|
800c2e0: 4313 orrs r3, r2
|
|
800c2e2: 613b str r3, [r7, #16]
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
800c2e4: 687b ldr r3, [r7, #4]
|
|
800c2e6: 681b ldr r3, [r3, #0]
|
|
800c2e8: 681a ldr r2, [r3, #0]
|
|
800c2ea: 4bb1 ldr r3, [pc, #708] ; (800c5b0 <UART_SetConfig+0x2f4>)
|
|
800c2ec: 4013 ands r3, r2
|
|
800c2ee: 687a ldr r2, [r7, #4]
|
|
800c2f0: 6812 ldr r2, [r2, #0]
|
|
800c2f2: 6939 ldr r1, [r7, #16]
|
|
800c2f4: 430b orrs r3, r1
|
|
800c2f6: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
800c2f8: 687b ldr r3, [r7, #4]
|
|
800c2fa: 681b ldr r3, [r3, #0]
|
|
800c2fc: 685b ldr r3, [r3, #4]
|
|
800c2fe: f423 5140 bic.w r1, r3, #12288 ; 0x3000
|
|
800c302: 687b ldr r3, [r7, #4]
|
|
800c304: 68da ldr r2, [r3, #12]
|
|
800c306: 687b ldr r3, [r7, #4]
|
|
800c308: 681b ldr r3, [r3, #0]
|
|
800c30a: 430a orrs r2, r1
|
|
800c30c: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
800c30e: 687b ldr r3, [r7, #4]
|
|
800c310: 699b ldr r3, [r3, #24]
|
|
800c312: 613b str r3, [r7, #16]
|
|
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
800c314: 687b ldr r3, [r7, #4]
|
|
800c316: 6a1b ldr r3, [r3, #32]
|
|
800c318: 693a ldr r2, [r7, #16]
|
|
800c31a: 4313 orrs r3, r2
|
|
800c31c: 613b str r3, [r7, #16]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
800c31e: 687b ldr r3, [r7, #4]
|
|
800c320: 681b ldr r3, [r3, #0]
|
|
800c322: 689b ldr r3, [r3, #8]
|
|
800c324: f423 6130 bic.w r1, r3, #2816 ; 0xb00
|
|
800c328: 687b ldr r3, [r7, #4]
|
|
800c32a: 681b ldr r3, [r3, #0]
|
|
800c32c: 693a ldr r2, [r7, #16]
|
|
800c32e: 430a orrs r2, r1
|
|
800c330: 609a str r2, [r3, #8]
|
|
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
800c332: 687b ldr r3, [r7, #4]
|
|
800c334: 681b ldr r3, [r3, #0]
|
|
800c336: 4a9f ldr r2, [pc, #636] ; (800c5b4 <UART_SetConfig+0x2f8>)
|
|
800c338: 4293 cmp r3, r2
|
|
800c33a: d121 bne.n 800c380 <UART_SetConfig+0xc4>
|
|
800c33c: 4b9e ldr r3, [pc, #632] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c33e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c342: f003 0303 and.w r3, r3, #3
|
|
800c346: 2b03 cmp r3, #3
|
|
800c348: d816 bhi.n 800c378 <UART_SetConfig+0xbc>
|
|
800c34a: a201 add r2, pc, #4 ; (adr r2, 800c350 <UART_SetConfig+0x94>)
|
|
800c34c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c350: 0800c361 .word 0x0800c361
|
|
800c354: 0800c36d .word 0x0800c36d
|
|
800c358: 0800c367 .word 0x0800c367
|
|
800c35c: 0800c373 .word 0x0800c373
|
|
800c360: 2301 movs r3, #1
|
|
800c362: 77fb strb r3, [r7, #31]
|
|
800c364: e151 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c366: 2302 movs r3, #2
|
|
800c368: 77fb strb r3, [r7, #31]
|
|
800c36a: e14e b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c36c: 2304 movs r3, #4
|
|
800c36e: 77fb strb r3, [r7, #31]
|
|
800c370: e14b b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c372: 2308 movs r3, #8
|
|
800c374: 77fb strb r3, [r7, #31]
|
|
800c376: e148 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c378: 2310 movs r3, #16
|
|
800c37a: 77fb strb r3, [r7, #31]
|
|
800c37c: bf00 nop
|
|
800c37e: e144 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c380: 687b ldr r3, [r7, #4]
|
|
800c382: 681b ldr r3, [r3, #0]
|
|
800c384: 4a8d ldr r2, [pc, #564] ; (800c5bc <UART_SetConfig+0x300>)
|
|
800c386: 4293 cmp r3, r2
|
|
800c388: d134 bne.n 800c3f4 <UART_SetConfig+0x138>
|
|
800c38a: 4b8b ldr r3, [pc, #556] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c38c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c390: f003 030c and.w r3, r3, #12
|
|
800c394: 2b0c cmp r3, #12
|
|
800c396: d829 bhi.n 800c3ec <UART_SetConfig+0x130>
|
|
800c398: a201 add r2, pc, #4 ; (adr r2, 800c3a0 <UART_SetConfig+0xe4>)
|
|
800c39a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c39e: bf00 nop
|
|
800c3a0: 0800c3d5 .word 0x0800c3d5
|
|
800c3a4: 0800c3ed .word 0x0800c3ed
|
|
800c3a8: 0800c3ed .word 0x0800c3ed
|
|
800c3ac: 0800c3ed .word 0x0800c3ed
|
|
800c3b0: 0800c3e1 .word 0x0800c3e1
|
|
800c3b4: 0800c3ed .word 0x0800c3ed
|
|
800c3b8: 0800c3ed .word 0x0800c3ed
|
|
800c3bc: 0800c3ed .word 0x0800c3ed
|
|
800c3c0: 0800c3db .word 0x0800c3db
|
|
800c3c4: 0800c3ed .word 0x0800c3ed
|
|
800c3c8: 0800c3ed .word 0x0800c3ed
|
|
800c3cc: 0800c3ed .word 0x0800c3ed
|
|
800c3d0: 0800c3e7 .word 0x0800c3e7
|
|
800c3d4: 2300 movs r3, #0
|
|
800c3d6: 77fb strb r3, [r7, #31]
|
|
800c3d8: e117 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c3da: 2302 movs r3, #2
|
|
800c3dc: 77fb strb r3, [r7, #31]
|
|
800c3de: e114 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c3e0: 2304 movs r3, #4
|
|
800c3e2: 77fb strb r3, [r7, #31]
|
|
800c3e4: e111 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c3e6: 2308 movs r3, #8
|
|
800c3e8: 77fb strb r3, [r7, #31]
|
|
800c3ea: e10e b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c3ec: 2310 movs r3, #16
|
|
800c3ee: 77fb strb r3, [r7, #31]
|
|
800c3f0: bf00 nop
|
|
800c3f2: e10a b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c3f4: 687b ldr r3, [r7, #4]
|
|
800c3f6: 681b ldr r3, [r3, #0]
|
|
800c3f8: 4a71 ldr r2, [pc, #452] ; (800c5c0 <UART_SetConfig+0x304>)
|
|
800c3fa: 4293 cmp r3, r2
|
|
800c3fc: d120 bne.n 800c440 <UART_SetConfig+0x184>
|
|
800c3fe: 4b6e ldr r3, [pc, #440] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c400: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c404: f003 0330 and.w r3, r3, #48 ; 0x30
|
|
800c408: 2b10 cmp r3, #16
|
|
800c40a: d00f beq.n 800c42c <UART_SetConfig+0x170>
|
|
800c40c: 2b10 cmp r3, #16
|
|
800c40e: d802 bhi.n 800c416 <UART_SetConfig+0x15a>
|
|
800c410: 2b00 cmp r3, #0
|
|
800c412: d005 beq.n 800c420 <UART_SetConfig+0x164>
|
|
800c414: e010 b.n 800c438 <UART_SetConfig+0x17c>
|
|
800c416: 2b20 cmp r3, #32
|
|
800c418: d005 beq.n 800c426 <UART_SetConfig+0x16a>
|
|
800c41a: 2b30 cmp r3, #48 ; 0x30
|
|
800c41c: d009 beq.n 800c432 <UART_SetConfig+0x176>
|
|
800c41e: e00b b.n 800c438 <UART_SetConfig+0x17c>
|
|
800c420: 2300 movs r3, #0
|
|
800c422: 77fb strb r3, [r7, #31]
|
|
800c424: e0f1 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c426: 2302 movs r3, #2
|
|
800c428: 77fb strb r3, [r7, #31]
|
|
800c42a: e0ee b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c42c: 2304 movs r3, #4
|
|
800c42e: 77fb strb r3, [r7, #31]
|
|
800c430: e0eb b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c432: 2308 movs r3, #8
|
|
800c434: 77fb strb r3, [r7, #31]
|
|
800c436: e0e8 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c438: 2310 movs r3, #16
|
|
800c43a: 77fb strb r3, [r7, #31]
|
|
800c43c: bf00 nop
|
|
800c43e: e0e4 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c440: 687b ldr r3, [r7, #4]
|
|
800c442: 681b ldr r3, [r3, #0]
|
|
800c444: 4a5f ldr r2, [pc, #380] ; (800c5c4 <UART_SetConfig+0x308>)
|
|
800c446: 4293 cmp r3, r2
|
|
800c448: d120 bne.n 800c48c <UART_SetConfig+0x1d0>
|
|
800c44a: 4b5b ldr r3, [pc, #364] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c44c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c450: f003 03c0 and.w r3, r3, #192 ; 0xc0
|
|
800c454: 2b40 cmp r3, #64 ; 0x40
|
|
800c456: d00f beq.n 800c478 <UART_SetConfig+0x1bc>
|
|
800c458: 2b40 cmp r3, #64 ; 0x40
|
|
800c45a: d802 bhi.n 800c462 <UART_SetConfig+0x1a6>
|
|
800c45c: 2b00 cmp r3, #0
|
|
800c45e: d005 beq.n 800c46c <UART_SetConfig+0x1b0>
|
|
800c460: e010 b.n 800c484 <UART_SetConfig+0x1c8>
|
|
800c462: 2b80 cmp r3, #128 ; 0x80
|
|
800c464: d005 beq.n 800c472 <UART_SetConfig+0x1b6>
|
|
800c466: 2bc0 cmp r3, #192 ; 0xc0
|
|
800c468: d009 beq.n 800c47e <UART_SetConfig+0x1c2>
|
|
800c46a: e00b b.n 800c484 <UART_SetConfig+0x1c8>
|
|
800c46c: 2300 movs r3, #0
|
|
800c46e: 77fb strb r3, [r7, #31]
|
|
800c470: e0cb b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c472: 2302 movs r3, #2
|
|
800c474: 77fb strb r3, [r7, #31]
|
|
800c476: e0c8 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c478: 2304 movs r3, #4
|
|
800c47a: 77fb strb r3, [r7, #31]
|
|
800c47c: e0c5 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c47e: 2308 movs r3, #8
|
|
800c480: 77fb strb r3, [r7, #31]
|
|
800c482: e0c2 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c484: 2310 movs r3, #16
|
|
800c486: 77fb strb r3, [r7, #31]
|
|
800c488: bf00 nop
|
|
800c48a: e0be b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c48c: 687b ldr r3, [r7, #4]
|
|
800c48e: 681b ldr r3, [r3, #0]
|
|
800c490: 4a4d ldr r2, [pc, #308] ; (800c5c8 <UART_SetConfig+0x30c>)
|
|
800c492: 4293 cmp r3, r2
|
|
800c494: d124 bne.n 800c4e0 <UART_SetConfig+0x224>
|
|
800c496: 4b48 ldr r3, [pc, #288] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c498: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c49c: f403 7340 and.w r3, r3, #768 ; 0x300
|
|
800c4a0: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
800c4a4: d012 beq.n 800c4cc <UART_SetConfig+0x210>
|
|
800c4a6: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
800c4aa: d802 bhi.n 800c4b2 <UART_SetConfig+0x1f6>
|
|
800c4ac: 2b00 cmp r3, #0
|
|
800c4ae: d007 beq.n 800c4c0 <UART_SetConfig+0x204>
|
|
800c4b0: e012 b.n 800c4d8 <UART_SetConfig+0x21c>
|
|
800c4b2: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
800c4b6: d006 beq.n 800c4c6 <UART_SetConfig+0x20a>
|
|
800c4b8: f5b3 7f40 cmp.w r3, #768 ; 0x300
|
|
800c4bc: d009 beq.n 800c4d2 <UART_SetConfig+0x216>
|
|
800c4be: e00b b.n 800c4d8 <UART_SetConfig+0x21c>
|
|
800c4c0: 2300 movs r3, #0
|
|
800c4c2: 77fb strb r3, [r7, #31]
|
|
800c4c4: e0a1 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c4c6: 2302 movs r3, #2
|
|
800c4c8: 77fb strb r3, [r7, #31]
|
|
800c4ca: e09e b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c4cc: 2304 movs r3, #4
|
|
800c4ce: 77fb strb r3, [r7, #31]
|
|
800c4d0: e09b b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c4d2: 2308 movs r3, #8
|
|
800c4d4: 77fb strb r3, [r7, #31]
|
|
800c4d6: e098 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c4d8: 2310 movs r3, #16
|
|
800c4da: 77fb strb r3, [r7, #31]
|
|
800c4dc: bf00 nop
|
|
800c4de: e094 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c4e0: 687b ldr r3, [r7, #4]
|
|
800c4e2: 681b ldr r3, [r3, #0]
|
|
800c4e4: 4a39 ldr r2, [pc, #228] ; (800c5cc <UART_SetConfig+0x310>)
|
|
800c4e6: 4293 cmp r3, r2
|
|
800c4e8: d124 bne.n 800c534 <UART_SetConfig+0x278>
|
|
800c4ea: 4b33 ldr r3, [pc, #204] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c4ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c4f0: f403 6340 and.w r3, r3, #3072 ; 0xc00
|
|
800c4f4: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
800c4f8: d012 beq.n 800c520 <UART_SetConfig+0x264>
|
|
800c4fa: f5b3 6f80 cmp.w r3, #1024 ; 0x400
|
|
800c4fe: d802 bhi.n 800c506 <UART_SetConfig+0x24a>
|
|
800c500: 2b00 cmp r3, #0
|
|
800c502: d007 beq.n 800c514 <UART_SetConfig+0x258>
|
|
800c504: e012 b.n 800c52c <UART_SetConfig+0x270>
|
|
800c506: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
800c50a: d006 beq.n 800c51a <UART_SetConfig+0x25e>
|
|
800c50c: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
|
|
800c510: d009 beq.n 800c526 <UART_SetConfig+0x26a>
|
|
800c512: e00b b.n 800c52c <UART_SetConfig+0x270>
|
|
800c514: 2301 movs r3, #1
|
|
800c516: 77fb strb r3, [r7, #31]
|
|
800c518: e077 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c51a: 2302 movs r3, #2
|
|
800c51c: 77fb strb r3, [r7, #31]
|
|
800c51e: e074 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c520: 2304 movs r3, #4
|
|
800c522: 77fb strb r3, [r7, #31]
|
|
800c524: e071 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c526: 2308 movs r3, #8
|
|
800c528: 77fb strb r3, [r7, #31]
|
|
800c52a: e06e b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c52c: 2310 movs r3, #16
|
|
800c52e: 77fb strb r3, [r7, #31]
|
|
800c530: bf00 nop
|
|
800c532: e06a b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c534: 687b ldr r3, [r7, #4]
|
|
800c536: 681b ldr r3, [r3, #0]
|
|
800c538: 4a25 ldr r2, [pc, #148] ; (800c5d0 <UART_SetConfig+0x314>)
|
|
800c53a: 4293 cmp r3, r2
|
|
800c53c: d124 bne.n 800c588 <UART_SetConfig+0x2cc>
|
|
800c53e: 4b1e ldr r3, [pc, #120] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c540: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c544: f403 5340 and.w r3, r3, #12288 ; 0x3000
|
|
800c548: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800c54c: d012 beq.n 800c574 <UART_SetConfig+0x2b8>
|
|
800c54e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
|
|
800c552: d802 bhi.n 800c55a <UART_SetConfig+0x29e>
|
|
800c554: 2b00 cmp r3, #0
|
|
800c556: d007 beq.n 800c568 <UART_SetConfig+0x2ac>
|
|
800c558: e012 b.n 800c580 <UART_SetConfig+0x2c4>
|
|
800c55a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
|
|
800c55e: d006 beq.n 800c56e <UART_SetConfig+0x2b2>
|
|
800c560: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
|
|
800c564: d009 beq.n 800c57a <UART_SetConfig+0x2be>
|
|
800c566: e00b b.n 800c580 <UART_SetConfig+0x2c4>
|
|
800c568: 2300 movs r3, #0
|
|
800c56a: 77fb strb r3, [r7, #31]
|
|
800c56c: e04d b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c56e: 2302 movs r3, #2
|
|
800c570: 77fb strb r3, [r7, #31]
|
|
800c572: e04a b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c574: 2304 movs r3, #4
|
|
800c576: 77fb strb r3, [r7, #31]
|
|
800c578: e047 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c57a: 2308 movs r3, #8
|
|
800c57c: 77fb strb r3, [r7, #31]
|
|
800c57e: e044 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c580: 2310 movs r3, #16
|
|
800c582: 77fb strb r3, [r7, #31]
|
|
800c584: bf00 nop
|
|
800c586: e040 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c588: 687b ldr r3, [r7, #4]
|
|
800c58a: 681b ldr r3, [r3, #0]
|
|
800c58c: 4a11 ldr r2, [pc, #68] ; (800c5d4 <UART_SetConfig+0x318>)
|
|
800c58e: 4293 cmp r3, r2
|
|
800c590: d139 bne.n 800c606 <UART_SetConfig+0x34a>
|
|
800c592: 4b09 ldr r3, [pc, #36] ; (800c5b8 <UART_SetConfig+0x2fc>)
|
|
800c594: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
800c598: f403 4340 and.w r3, r3, #49152 ; 0xc000
|
|
800c59c: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
|
|
800c5a0: d027 beq.n 800c5f2 <UART_SetConfig+0x336>
|
|
800c5a2: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
|
|
800c5a6: d817 bhi.n 800c5d8 <UART_SetConfig+0x31c>
|
|
800c5a8: 2b00 cmp r3, #0
|
|
800c5aa: d01c beq.n 800c5e6 <UART_SetConfig+0x32a>
|
|
800c5ac: e027 b.n 800c5fe <UART_SetConfig+0x342>
|
|
800c5ae: bf00 nop
|
|
800c5b0: efff69f3 .word 0xefff69f3
|
|
800c5b4: 40011000 .word 0x40011000
|
|
800c5b8: 40023800 .word 0x40023800
|
|
800c5bc: 40004400 .word 0x40004400
|
|
800c5c0: 40004800 .word 0x40004800
|
|
800c5c4: 40004c00 .word 0x40004c00
|
|
800c5c8: 40005000 .word 0x40005000
|
|
800c5cc: 40011400 .word 0x40011400
|
|
800c5d0: 40007800 .word 0x40007800
|
|
800c5d4: 40007c00 .word 0x40007c00
|
|
800c5d8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
|
800c5dc: d006 beq.n 800c5ec <UART_SetConfig+0x330>
|
|
800c5de: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
|
|
800c5e2: d009 beq.n 800c5f8 <UART_SetConfig+0x33c>
|
|
800c5e4: e00b b.n 800c5fe <UART_SetConfig+0x342>
|
|
800c5e6: 2300 movs r3, #0
|
|
800c5e8: 77fb strb r3, [r7, #31]
|
|
800c5ea: e00e b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c5ec: 2302 movs r3, #2
|
|
800c5ee: 77fb strb r3, [r7, #31]
|
|
800c5f0: e00b b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c5f2: 2304 movs r3, #4
|
|
800c5f4: 77fb strb r3, [r7, #31]
|
|
800c5f6: e008 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c5f8: 2308 movs r3, #8
|
|
800c5fa: 77fb strb r3, [r7, #31]
|
|
800c5fc: e005 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c5fe: 2310 movs r3, #16
|
|
800c600: 77fb strb r3, [r7, #31]
|
|
800c602: bf00 nop
|
|
800c604: e001 b.n 800c60a <UART_SetConfig+0x34e>
|
|
800c606: 2310 movs r3, #16
|
|
800c608: 77fb strb r3, [r7, #31]
|
|
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
800c60a: 687b ldr r3, [r7, #4]
|
|
800c60c: 69db ldr r3, [r3, #28]
|
|
800c60e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
|
|
800c612: d17f bne.n 800c714 <UART_SetConfig+0x458>
|
|
{
|
|
switch (clocksource)
|
|
800c614: 7ffb ldrb r3, [r7, #31]
|
|
800c616: 2b08 cmp r3, #8
|
|
800c618: d85c bhi.n 800c6d4 <UART_SetConfig+0x418>
|
|
800c61a: a201 add r2, pc, #4 ; (adr r2, 800c620 <UART_SetConfig+0x364>)
|
|
800c61c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c620: 0800c645 .word 0x0800c645
|
|
800c624: 0800c665 .word 0x0800c665
|
|
800c628: 0800c685 .word 0x0800c685
|
|
800c62c: 0800c6d5 .word 0x0800c6d5
|
|
800c630: 0800c69d .word 0x0800c69d
|
|
800c634: 0800c6d5 .word 0x0800c6d5
|
|
800c638: 0800c6d5 .word 0x0800c6d5
|
|
800c63c: 0800c6d5 .word 0x0800c6d5
|
|
800c640: 0800c6bd .word 0x0800c6bd
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800c644: f7fd fb78 bl 8009d38 <HAL_RCC_GetPCLK1Freq>
|
|
800c648: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
800c64a: 68fb ldr r3, [r7, #12]
|
|
800c64c: 005a lsls r2, r3, #1
|
|
800c64e: 687b ldr r3, [r7, #4]
|
|
800c650: 685b ldr r3, [r3, #4]
|
|
800c652: 085b lsrs r3, r3, #1
|
|
800c654: 441a add r2, r3
|
|
800c656: 687b ldr r3, [r7, #4]
|
|
800c658: 685b ldr r3, [r3, #4]
|
|
800c65a: fbb2 f3f3 udiv r3, r2, r3
|
|
800c65e: b29b uxth r3, r3
|
|
800c660: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c662: e03a b.n 800c6da <UART_SetConfig+0x41e>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800c664: f7fd fb7c bl 8009d60 <HAL_RCC_GetPCLK2Freq>
|
|
800c668: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
800c66a: 68fb ldr r3, [r7, #12]
|
|
800c66c: 005a lsls r2, r3, #1
|
|
800c66e: 687b ldr r3, [r7, #4]
|
|
800c670: 685b ldr r3, [r3, #4]
|
|
800c672: 085b lsrs r3, r3, #1
|
|
800c674: 441a add r2, r3
|
|
800c676: 687b ldr r3, [r7, #4]
|
|
800c678: 685b ldr r3, [r3, #4]
|
|
800c67a: fbb2 f3f3 udiv r3, r2, r3
|
|
800c67e: b29b uxth r3, r3
|
|
800c680: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c682: e02a b.n 800c6da <UART_SetConfig+0x41e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
|
|
800c684: 687b ldr r3, [r7, #4]
|
|
800c686: 685b ldr r3, [r3, #4]
|
|
800c688: 085a lsrs r2, r3, #1
|
|
800c68a: 4b5f ldr r3, [pc, #380] ; (800c808 <UART_SetConfig+0x54c>)
|
|
800c68c: 4413 add r3, r2
|
|
800c68e: 687a ldr r2, [r7, #4]
|
|
800c690: 6852 ldr r2, [r2, #4]
|
|
800c692: fbb3 f3f2 udiv r3, r3, r2
|
|
800c696: b29b uxth r3, r3
|
|
800c698: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c69a: e01e b.n 800c6da <UART_SetConfig+0x41e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800c69c: f7fd fa8e bl 8009bbc <HAL_RCC_GetSysClockFreq>
|
|
800c6a0: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
800c6a2: 68fb ldr r3, [r7, #12]
|
|
800c6a4: 005a lsls r2, r3, #1
|
|
800c6a6: 687b ldr r3, [r7, #4]
|
|
800c6a8: 685b ldr r3, [r3, #4]
|
|
800c6aa: 085b lsrs r3, r3, #1
|
|
800c6ac: 441a add r2, r3
|
|
800c6ae: 687b ldr r3, [r7, #4]
|
|
800c6b0: 685b ldr r3, [r3, #4]
|
|
800c6b2: fbb2 f3f3 udiv r3, r2, r3
|
|
800c6b6: b29b uxth r3, r3
|
|
800c6b8: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c6ba: e00e b.n 800c6da <UART_SetConfig+0x41e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
|
|
800c6bc: 687b ldr r3, [r7, #4]
|
|
800c6be: 685b ldr r3, [r3, #4]
|
|
800c6c0: 085b lsrs r3, r3, #1
|
|
800c6c2: f503 3280 add.w r2, r3, #65536 ; 0x10000
|
|
800c6c6: 687b ldr r3, [r7, #4]
|
|
800c6c8: 685b ldr r3, [r3, #4]
|
|
800c6ca: fbb2 f3f3 udiv r3, r2, r3
|
|
800c6ce: b29b uxth r3, r3
|
|
800c6d0: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c6d2: e002 b.n 800c6da <UART_SetConfig+0x41e>
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800c6d4: 2301 movs r3, #1
|
|
800c6d6: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800c6d8: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
800c6da: 69bb ldr r3, [r7, #24]
|
|
800c6dc: 2b0f cmp r3, #15
|
|
800c6de: d916 bls.n 800c70e <UART_SetConfig+0x452>
|
|
800c6e0: 69bb ldr r3, [r7, #24]
|
|
800c6e2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800c6e6: d212 bcs.n 800c70e <UART_SetConfig+0x452>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
800c6e8: 69bb ldr r3, [r7, #24]
|
|
800c6ea: b29b uxth r3, r3
|
|
800c6ec: f023 030f bic.w r3, r3, #15
|
|
800c6f0: 817b strh r3, [r7, #10]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
800c6f2: 69bb ldr r3, [r7, #24]
|
|
800c6f4: 085b lsrs r3, r3, #1
|
|
800c6f6: b29b uxth r3, r3
|
|
800c6f8: f003 0307 and.w r3, r3, #7
|
|
800c6fc: b29a uxth r2, r3
|
|
800c6fe: 897b ldrh r3, [r7, #10]
|
|
800c700: 4313 orrs r3, r2
|
|
800c702: 817b strh r3, [r7, #10]
|
|
huart->Instance->BRR = brrtemp;
|
|
800c704: 687b ldr r3, [r7, #4]
|
|
800c706: 681b ldr r3, [r3, #0]
|
|
800c708: 897a ldrh r2, [r7, #10]
|
|
800c70a: 60da str r2, [r3, #12]
|
|
800c70c: e070 b.n 800c7f0 <UART_SetConfig+0x534>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800c70e: 2301 movs r3, #1
|
|
800c710: 75fb strb r3, [r7, #23]
|
|
800c712: e06d b.n 800c7f0 <UART_SetConfig+0x534>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
800c714: 7ffb ldrb r3, [r7, #31]
|
|
800c716: 2b08 cmp r3, #8
|
|
800c718: d859 bhi.n 800c7ce <UART_SetConfig+0x512>
|
|
800c71a: a201 add r2, pc, #4 ; (adr r2, 800c720 <UART_SetConfig+0x464>)
|
|
800c71c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c720: 0800c745 .word 0x0800c745
|
|
800c724: 0800c763 .word 0x0800c763
|
|
800c728: 0800c781 .word 0x0800c781
|
|
800c72c: 0800c7cf .word 0x0800c7cf
|
|
800c730: 0800c799 .word 0x0800c799
|
|
800c734: 0800c7cf .word 0x0800c7cf
|
|
800c738: 0800c7cf .word 0x0800c7cf
|
|
800c73c: 0800c7cf .word 0x0800c7cf
|
|
800c740: 0800c7b7 .word 0x0800c7b7
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
800c744: f7fd faf8 bl 8009d38 <HAL_RCC_GetPCLK1Freq>
|
|
800c748: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
800c74a: 687b ldr r3, [r7, #4]
|
|
800c74c: 685b ldr r3, [r3, #4]
|
|
800c74e: 085a lsrs r2, r3, #1
|
|
800c750: 68fb ldr r3, [r7, #12]
|
|
800c752: 441a add r2, r3
|
|
800c754: 687b ldr r3, [r7, #4]
|
|
800c756: 685b ldr r3, [r3, #4]
|
|
800c758: fbb2 f3f3 udiv r3, r2, r3
|
|
800c75c: b29b uxth r3, r3
|
|
800c75e: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c760: e038 b.n 800c7d4 <UART_SetConfig+0x518>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800c762: f7fd fafd bl 8009d60 <HAL_RCC_GetPCLK2Freq>
|
|
800c766: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
800c768: 687b ldr r3, [r7, #4]
|
|
800c76a: 685b ldr r3, [r3, #4]
|
|
800c76c: 085a lsrs r2, r3, #1
|
|
800c76e: 68fb ldr r3, [r7, #12]
|
|
800c770: 441a add r2, r3
|
|
800c772: 687b ldr r3, [r7, #4]
|
|
800c774: 685b ldr r3, [r3, #4]
|
|
800c776: fbb2 f3f3 udiv r3, r2, r3
|
|
800c77a: b29b uxth r3, r3
|
|
800c77c: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c77e: e029 b.n 800c7d4 <UART_SetConfig+0x518>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
|
|
800c780: 687b ldr r3, [r7, #4]
|
|
800c782: 685b ldr r3, [r3, #4]
|
|
800c784: 085a lsrs r2, r3, #1
|
|
800c786: 4b21 ldr r3, [pc, #132] ; (800c80c <UART_SetConfig+0x550>)
|
|
800c788: 4413 add r3, r2
|
|
800c78a: 687a ldr r2, [r7, #4]
|
|
800c78c: 6852 ldr r2, [r2, #4]
|
|
800c78e: fbb3 f3f2 udiv r3, r3, r2
|
|
800c792: b29b uxth r3, r3
|
|
800c794: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c796: e01d b.n 800c7d4 <UART_SetConfig+0x518>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
800c798: f7fd fa10 bl 8009bbc <HAL_RCC_GetSysClockFreq>
|
|
800c79c: 60f8 str r0, [r7, #12]
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
800c79e: 687b ldr r3, [r7, #4]
|
|
800c7a0: 685b ldr r3, [r3, #4]
|
|
800c7a2: 085a lsrs r2, r3, #1
|
|
800c7a4: 68fb ldr r3, [r7, #12]
|
|
800c7a6: 441a add r2, r3
|
|
800c7a8: 687b ldr r3, [r7, #4]
|
|
800c7aa: 685b ldr r3, [r3, #4]
|
|
800c7ac: fbb2 f3f3 udiv r3, r2, r3
|
|
800c7b0: b29b uxth r3, r3
|
|
800c7b2: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c7b4: e00e b.n 800c7d4 <UART_SetConfig+0x518>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
|
|
800c7b6: 687b ldr r3, [r7, #4]
|
|
800c7b8: 685b ldr r3, [r3, #4]
|
|
800c7ba: 085b lsrs r3, r3, #1
|
|
800c7bc: f503 4200 add.w r2, r3, #32768 ; 0x8000
|
|
800c7c0: 687b ldr r3, [r7, #4]
|
|
800c7c2: 685b ldr r3, [r3, #4]
|
|
800c7c4: fbb2 f3f3 udiv r3, r2, r3
|
|
800c7c8: b29b uxth r3, r3
|
|
800c7ca: 61bb str r3, [r7, #24]
|
|
break;
|
|
800c7cc: e002 b.n 800c7d4 <UART_SetConfig+0x518>
|
|
default:
|
|
ret = HAL_ERROR;
|
|
800c7ce: 2301 movs r3, #1
|
|
800c7d0: 75fb strb r3, [r7, #23]
|
|
break;
|
|
800c7d2: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
800c7d4: 69bb ldr r3, [r7, #24]
|
|
800c7d6: 2b0f cmp r3, #15
|
|
800c7d8: d908 bls.n 800c7ec <UART_SetConfig+0x530>
|
|
800c7da: 69bb ldr r3, [r7, #24]
|
|
800c7dc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
800c7e0: d204 bcs.n 800c7ec <UART_SetConfig+0x530>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
800c7e2: 687b ldr r3, [r7, #4]
|
|
800c7e4: 681b ldr r3, [r3, #0]
|
|
800c7e6: 69ba ldr r2, [r7, #24]
|
|
800c7e8: 60da str r2, [r3, #12]
|
|
800c7ea: e001 b.n 800c7f0 <UART_SetConfig+0x534>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
800c7ec: 2301 movs r3, #1
|
|
800c7ee: 75fb strb r3, [r7, #23]
|
|
}
|
|
}
|
|
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
800c7f0: 687b ldr r3, [r7, #4]
|
|
800c7f2: 2200 movs r2, #0
|
|
800c7f4: 661a str r2, [r3, #96] ; 0x60
|
|
huart->TxISR = NULL;
|
|
800c7f6: 687b ldr r3, [r7, #4]
|
|
800c7f8: 2200 movs r2, #0
|
|
800c7fa: 665a str r2, [r3, #100] ; 0x64
|
|
|
|
return ret;
|
|
800c7fc: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800c7fe: 4618 mov r0, r3
|
|
800c800: 3720 adds r7, #32
|
|
800c802: 46bd mov sp, r7
|
|
800c804: bd80 pop {r7, pc}
|
|
800c806: bf00 nop
|
|
800c808: 01e84800 .word 0x01e84800
|
|
800c80c: 00f42400 .word 0x00f42400
|
|
|
|
0800c810 <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800c810: b480 push {r7}
|
|
800c812: b083 sub sp, #12
|
|
800c814: af00 add r7, sp, #0
|
|
800c816: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
800c818: 687b ldr r3, [r7, #4]
|
|
800c81a: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c81c: f003 0301 and.w r3, r3, #1
|
|
800c820: 2b00 cmp r3, #0
|
|
800c822: d00a beq.n 800c83a <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
800c824: 687b ldr r3, [r7, #4]
|
|
800c826: 681b ldr r3, [r3, #0]
|
|
800c828: 685b ldr r3, [r3, #4]
|
|
800c82a: f423 3100 bic.w r1, r3, #131072 ; 0x20000
|
|
800c82e: 687b ldr r3, [r7, #4]
|
|
800c830: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
800c832: 687b ldr r3, [r7, #4]
|
|
800c834: 681b ldr r3, [r3, #0]
|
|
800c836: 430a orrs r2, r1
|
|
800c838: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
800c83a: 687b ldr r3, [r7, #4]
|
|
800c83c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c83e: f003 0302 and.w r3, r3, #2
|
|
800c842: 2b00 cmp r3, #0
|
|
800c844: d00a beq.n 800c85c <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
800c846: 687b ldr r3, [r7, #4]
|
|
800c848: 681b ldr r3, [r3, #0]
|
|
800c84a: 685b ldr r3, [r3, #4]
|
|
800c84c: f423 3180 bic.w r1, r3, #65536 ; 0x10000
|
|
800c850: 687b ldr r3, [r7, #4]
|
|
800c852: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800c854: 687b ldr r3, [r7, #4]
|
|
800c856: 681b ldr r3, [r3, #0]
|
|
800c858: 430a orrs r2, r1
|
|
800c85a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
800c85c: 687b ldr r3, [r7, #4]
|
|
800c85e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c860: f003 0304 and.w r3, r3, #4
|
|
800c864: 2b00 cmp r3, #0
|
|
800c866: d00a beq.n 800c87e <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
800c868: 687b ldr r3, [r7, #4]
|
|
800c86a: 681b ldr r3, [r3, #0]
|
|
800c86c: 685b ldr r3, [r3, #4]
|
|
800c86e: f423 2180 bic.w r1, r3, #262144 ; 0x40000
|
|
800c872: 687b ldr r3, [r7, #4]
|
|
800c874: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
800c876: 687b ldr r3, [r7, #4]
|
|
800c878: 681b ldr r3, [r3, #0]
|
|
800c87a: 430a orrs r2, r1
|
|
800c87c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
800c87e: 687b ldr r3, [r7, #4]
|
|
800c880: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c882: f003 0308 and.w r3, r3, #8
|
|
800c886: 2b00 cmp r3, #0
|
|
800c888: d00a beq.n 800c8a0 <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
800c88a: 687b ldr r3, [r7, #4]
|
|
800c88c: 681b ldr r3, [r3, #0]
|
|
800c88e: 685b ldr r3, [r3, #4]
|
|
800c890: f423 4100 bic.w r1, r3, #32768 ; 0x8000
|
|
800c894: 687b ldr r3, [r7, #4]
|
|
800c896: 6b5a ldr r2, [r3, #52] ; 0x34
|
|
800c898: 687b ldr r3, [r7, #4]
|
|
800c89a: 681b ldr r3, [r3, #0]
|
|
800c89c: 430a orrs r2, r1
|
|
800c89e: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
800c8a0: 687b ldr r3, [r7, #4]
|
|
800c8a2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c8a4: f003 0310 and.w r3, r3, #16
|
|
800c8a8: 2b00 cmp r3, #0
|
|
800c8aa: d00a beq.n 800c8c2 <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
800c8ac: 687b ldr r3, [r7, #4]
|
|
800c8ae: 681b ldr r3, [r3, #0]
|
|
800c8b0: 689b ldr r3, [r3, #8]
|
|
800c8b2: f423 5180 bic.w r1, r3, #4096 ; 0x1000
|
|
800c8b6: 687b ldr r3, [r7, #4]
|
|
800c8b8: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
800c8ba: 687b ldr r3, [r7, #4]
|
|
800c8bc: 681b ldr r3, [r3, #0]
|
|
800c8be: 430a orrs r2, r1
|
|
800c8c0: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
800c8c2: 687b ldr r3, [r7, #4]
|
|
800c8c4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c8c6: f003 0320 and.w r3, r3, #32
|
|
800c8ca: 2b00 cmp r3, #0
|
|
800c8cc: d00a beq.n 800c8e4 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
800c8ce: 687b ldr r3, [r7, #4]
|
|
800c8d0: 681b ldr r3, [r3, #0]
|
|
800c8d2: 689b ldr r3, [r3, #8]
|
|
800c8d4: f423 5100 bic.w r1, r3, #8192 ; 0x2000
|
|
800c8d8: 687b ldr r3, [r7, #4]
|
|
800c8da: 6bda ldr r2, [r3, #60] ; 0x3c
|
|
800c8dc: 687b ldr r3, [r7, #4]
|
|
800c8de: 681b ldr r3, [r3, #0]
|
|
800c8e0: 430a orrs r2, r1
|
|
800c8e2: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
800c8e4: 687b ldr r3, [r7, #4]
|
|
800c8e6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c8e8: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800c8ec: 2b00 cmp r3, #0
|
|
800c8ee: d01a beq.n 800c926 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
800c8f0: 687b ldr r3, [r7, #4]
|
|
800c8f2: 681b ldr r3, [r3, #0]
|
|
800c8f4: 685b ldr r3, [r3, #4]
|
|
800c8f6: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
|
|
800c8fa: 687b ldr r3, [r7, #4]
|
|
800c8fc: 6c1a ldr r2, [r3, #64] ; 0x40
|
|
800c8fe: 687b ldr r3, [r7, #4]
|
|
800c900: 681b ldr r3, [r3, #0]
|
|
800c902: 430a orrs r2, r1
|
|
800c904: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
800c906: 687b ldr r3, [r7, #4]
|
|
800c908: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800c90a: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
|
|
800c90e: d10a bne.n 800c926 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
800c910: 687b ldr r3, [r7, #4]
|
|
800c912: 681b ldr r3, [r3, #0]
|
|
800c914: 685b ldr r3, [r3, #4]
|
|
800c916: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
|
|
800c91a: 687b ldr r3, [r7, #4]
|
|
800c91c: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
800c91e: 687b ldr r3, [r7, #4]
|
|
800c920: 681b ldr r3, [r3, #0]
|
|
800c922: 430a orrs r2, r1
|
|
800c924: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
800c926: 687b ldr r3, [r7, #4]
|
|
800c928: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800c92a: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800c92e: 2b00 cmp r3, #0
|
|
800c930: d00a beq.n 800c948 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
800c932: 687b ldr r3, [r7, #4]
|
|
800c934: 681b ldr r3, [r3, #0]
|
|
800c936: 685b ldr r3, [r3, #4]
|
|
800c938: f423 2100 bic.w r1, r3, #524288 ; 0x80000
|
|
800c93c: 687b ldr r3, [r7, #4]
|
|
800c93e: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
800c940: 687b ldr r3, [r7, #4]
|
|
800c942: 681b ldr r3, [r3, #0]
|
|
800c944: 430a orrs r2, r1
|
|
800c946: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
800c948: bf00 nop
|
|
800c94a: 370c adds r7, #12
|
|
800c94c: 46bd mov sp, r7
|
|
800c94e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c952: 4770 bx lr
|
|
|
|
0800c954 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
800c954: b580 push {r7, lr}
|
|
800c956: b086 sub sp, #24
|
|
800c958: af02 add r7, sp, #8
|
|
800c95a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
800c95c: 687b ldr r3, [r7, #4]
|
|
800c95e: 2200 movs r2, #0
|
|
800c960: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
/* Init tickstart for timeout managment*/
|
|
tickstart = HAL_GetTick();
|
|
800c962: f7f8 fcbd bl 80052e0 <HAL_GetTick>
|
|
800c966: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
800c968: 687b ldr r3, [r7, #4]
|
|
800c96a: 681b ldr r3, [r3, #0]
|
|
800c96c: 681b ldr r3, [r3, #0]
|
|
800c96e: f003 0308 and.w r3, r3, #8
|
|
800c972: 2b08 cmp r3, #8
|
|
800c974: d10e bne.n 800c994 <UART_CheckIdleState+0x40>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
800c976: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
|
|
800c97a: 9300 str r3, [sp, #0]
|
|
800c97c: 68fb ldr r3, [r7, #12]
|
|
800c97e: 2200 movs r2, #0
|
|
800c980: f44f 1100 mov.w r1, #2097152 ; 0x200000
|
|
800c984: 6878 ldr r0, [r7, #4]
|
|
800c986: f000 f814 bl 800c9b2 <UART_WaitOnFlagUntilTimeout>
|
|
800c98a: 4603 mov r3, r0
|
|
800c98c: 2b00 cmp r3, #0
|
|
800c98e: d001 beq.n 800c994 <UART_CheckIdleState+0x40>
|
|
{
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
800c990: 2303 movs r3, #3
|
|
800c992: e00a b.n 800c9aa <UART_CheckIdleState+0x56>
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800c994: 687b ldr r3, [r7, #4]
|
|
800c996: 2220 movs r2, #32
|
|
800c998: 675a str r2, [r3, #116] ; 0x74
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800c99a: 687b ldr r3, [r7, #4]
|
|
800c99c: 2220 movs r2, #32
|
|
800c99e: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800c9a0: 687b ldr r3, [r7, #4]
|
|
800c9a2: 2200 movs r2, #0
|
|
800c9a4: f883 2070 strb.w r2, [r3, #112] ; 0x70
|
|
|
|
return HAL_OK;
|
|
800c9a8: 2300 movs r3, #0
|
|
}
|
|
800c9aa: 4618 mov r0, r3
|
|
800c9ac: 3710 adds r7, #16
|
|
800c9ae: 46bd mov sp, r7
|
|
800c9b0: bd80 pop {r7, pc}
|
|
|
|
0800c9b2 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
800c9b2: b580 push {r7, lr}
|
|
800c9b4: b084 sub sp, #16
|
|
800c9b6: af00 add r7, sp, #0
|
|
800c9b8: 60f8 str r0, [r7, #12]
|
|
800c9ba: 60b9 str r1, [r7, #8]
|
|
800c9bc: 603b str r3, [r7, #0]
|
|
800c9be: 4613 mov r3, r2
|
|
800c9c0: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800c9c2: e05d b.n 800ca80 <UART_WaitOnFlagUntilTimeout+0xce>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800c9c4: 69bb ldr r3, [r7, #24]
|
|
800c9c6: f1b3 3fff cmp.w r3, #4294967295
|
|
800c9ca: d059 beq.n 800ca80 <UART_WaitOnFlagUntilTimeout+0xce>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
800c9cc: f7f8 fc88 bl 80052e0 <HAL_GetTick>
|
|
800c9d0: 4602 mov r2, r0
|
|
800c9d2: 683b ldr r3, [r7, #0]
|
|
800c9d4: 1ad3 subs r3, r2, r3
|
|
800c9d6: 69ba ldr r2, [r7, #24]
|
|
800c9d8: 429a cmp r2, r3
|
|
800c9da: d302 bcc.n 800c9e2 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
800c9dc: 69bb ldr r3, [r7, #24]
|
|
800c9de: 2b00 cmp r3, #0
|
|
800c9e0: d11b bne.n 800ca1a <UART_WaitOnFlagUntilTimeout+0x68>
|
|
{
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
800c9e2: 68fb ldr r3, [r7, #12]
|
|
800c9e4: 681b ldr r3, [r3, #0]
|
|
800c9e6: 681a ldr r2, [r3, #0]
|
|
800c9e8: 68fb ldr r3, [r7, #12]
|
|
800c9ea: 681b ldr r3, [r3, #0]
|
|
800c9ec: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
800c9f0: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800c9f2: 68fb ldr r3, [r7, #12]
|
|
800c9f4: 681b ldr r3, [r3, #0]
|
|
800c9f6: 689a ldr r2, [r3, #8]
|
|
800c9f8: 68fb ldr r3, [r7, #12]
|
|
800c9fa: 681b ldr r3, [r3, #0]
|
|
800c9fc: f022 0201 bic.w r2, r2, #1
|
|
800ca00: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800ca02: 68fb ldr r3, [r7, #12]
|
|
800ca04: 2220 movs r2, #32
|
|
800ca06: 675a str r2, [r3, #116] ; 0x74
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800ca08: 68fb ldr r3, [r7, #12]
|
|
800ca0a: 2220 movs r2, #32
|
|
800ca0c: 679a str r2, [r3, #120] ; 0x78
|
|
|
|
__HAL_UNLOCK(huart);
|
|
800ca0e: 68fb ldr r3, [r7, #12]
|
|
800ca10: 2200 movs r2, #0
|
|
800ca12: f883 2070 strb.w r2, [r3, #112] ; 0x70
|
|
|
|
return HAL_TIMEOUT;
|
|
800ca16: 2303 movs r3, #3
|
|
800ca18: e042 b.n 800caa0 <UART_WaitOnFlagUntilTimeout+0xee>
|
|
}
|
|
|
|
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
|
800ca1a: 68fb ldr r3, [r7, #12]
|
|
800ca1c: 681b ldr r3, [r3, #0]
|
|
800ca1e: 681b ldr r3, [r3, #0]
|
|
800ca20: f003 0304 and.w r3, r3, #4
|
|
800ca24: 2b00 cmp r3, #0
|
|
800ca26: d02b beq.n 800ca80 <UART_WaitOnFlagUntilTimeout+0xce>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
800ca28: 68fb ldr r3, [r7, #12]
|
|
800ca2a: 681b ldr r3, [r3, #0]
|
|
800ca2c: 69db ldr r3, [r3, #28]
|
|
800ca2e: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
800ca32: f5b3 6f00 cmp.w r3, #2048 ; 0x800
|
|
800ca36: d123 bne.n 800ca80 <UART_WaitOnFlagUntilTimeout+0xce>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
800ca38: 68fb ldr r3, [r7, #12]
|
|
800ca3a: 681b ldr r3, [r3, #0]
|
|
800ca3c: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
800ca40: 621a str r2, [r3, #32]
|
|
|
|
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
|
|
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
|
|
800ca42: 68fb ldr r3, [r7, #12]
|
|
800ca44: 681b ldr r3, [r3, #0]
|
|
800ca46: 681a ldr r2, [r3, #0]
|
|
800ca48: 68fb ldr r3, [r7, #12]
|
|
800ca4a: 681b ldr r3, [r3, #0]
|
|
800ca4c: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
|
|
800ca50: 601a str r2, [r3, #0]
|
|
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800ca52: 68fb ldr r3, [r7, #12]
|
|
800ca54: 681b ldr r3, [r3, #0]
|
|
800ca56: 689a ldr r2, [r3, #8]
|
|
800ca58: 68fb ldr r3, [r7, #12]
|
|
800ca5a: 681b ldr r3, [r3, #0]
|
|
800ca5c: f022 0201 bic.w r2, r2, #1
|
|
800ca60: 609a str r2, [r3, #8]
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800ca62: 68fb ldr r3, [r7, #12]
|
|
800ca64: 2220 movs r2, #32
|
|
800ca66: 675a str r2, [r3, #116] ; 0x74
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800ca68: 68fb ldr r3, [r7, #12]
|
|
800ca6a: 2220 movs r2, #32
|
|
800ca6c: 679a str r2, [r3, #120] ; 0x78
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
800ca6e: 68fb ldr r3, [r7, #12]
|
|
800ca70: 2220 movs r2, #32
|
|
800ca72: 67da str r2, [r3, #124] ; 0x7c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
800ca74: 68fb ldr r3, [r7, #12]
|
|
800ca76: 2200 movs r2, #0
|
|
800ca78: f883 2070 strb.w r2, [r3, #112] ; 0x70
|
|
|
|
return HAL_TIMEOUT;
|
|
800ca7c: 2303 movs r3, #3
|
|
800ca7e: e00f b.n 800caa0 <UART_WaitOnFlagUntilTimeout+0xee>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
800ca80: 68fb ldr r3, [r7, #12]
|
|
800ca82: 681b ldr r3, [r3, #0]
|
|
800ca84: 69da ldr r2, [r3, #28]
|
|
800ca86: 68bb ldr r3, [r7, #8]
|
|
800ca88: 4013 ands r3, r2
|
|
800ca8a: 68ba ldr r2, [r7, #8]
|
|
800ca8c: 429a cmp r2, r3
|
|
800ca8e: bf0c ite eq
|
|
800ca90: 2301 moveq r3, #1
|
|
800ca92: 2300 movne r3, #0
|
|
800ca94: b2db uxtb r3, r3
|
|
800ca96: 461a mov r2, r3
|
|
800ca98: 79fb ldrb r3, [r7, #7]
|
|
800ca9a: 429a cmp r2, r3
|
|
800ca9c: d092 beq.n 800c9c4 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800ca9e: 2300 movs r3, #0
|
|
}
|
|
800caa0: 4618 mov r0, r3
|
|
800caa2: 3710 adds r7, #16
|
|
800caa4: 46bd mov sp, r7
|
|
800caa6: bd80 pop {r7, pc}
|
|
|
|
0800caa8 <FMC_SDRAM_Init>:
|
|
* @param Device Pointer to SDRAM device instance
|
|
* @param Init Pointer to SDRAM Initialization structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
|
|
{
|
|
800caa8: b480 push {r7}
|
|
800caaa: b085 sub sp, #20
|
|
800caac: af00 add r7, sp, #0
|
|
800caae: 6078 str r0, [r7, #4]
|
|
800cab0: 6039 str r1, [r7, #0]
|
|
uint32_t tmpr1 = 0;
|
|
800cab2: 2300 movs r3, #0
|
|
800cab4: 60fb str r3, [r7, #12]
|
|
uint32_t tmpr2 = 0;
|
|
800cab6: 2300 movs r3, #0
|
|
800cab8: 60bb str r3, [r7, #8]
|
|
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
|
|
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
|
|
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
|
|
|
|
/* Set SDRAM bank configuration parameters */
|
|
if (Init->SDBank != FMC_SDRAM_BANK2)
|
|
800caba: 683b ldr r3, [r7, #0]
|
|
800cabc: 681b ldr r3, [r3, #0]
|
|
800cabe: 2b01 cmp r3, #1
|
|
800cac0: d027 beq.n 800cb12 <FMC_SDRAM_Init+0x6a>
|
|
{
|
|
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
|
|
800cac2: 687b ldr r3, [r7, #4]
|
|
800cac4: 681b ldr r3, [r3, #0]
|
|
800cac6: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
|
|
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
|
|
800cac8: 68fa ldr r2, [r7, #12]
|
|
800caca: 4b2f ldr r3, [pc, #188] ; (800cb88 <FMC_SDRAM_Init+0xe0>)
|
|
800cacc: 4013 ands r3, r2
|
|
800cace: 60fb str r3, [r7, #12]
|
|
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
|
|
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
|
|
|
|
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cad0: 683b ldr r3, [r7, #0]
|
|
800cad2: 685a ldr r2, [r3, #4]
|
|
Init->RowBitsNumber |\
|
|
800cad4: 683b ldr r3, [r7, #0]
|
|
800cad6: 689b ldr r3, [r3, #8]
|
|
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cad8: 431a orrs r2, r3
|
|
Init->MemoryDataWidth |\
|
|
800cada: 683b ldr r3, [r7, #0]
|
|
800cadc: 68db ldr r3, [r3, #12]
|
|
Init->RowBitsNumber |\
|
|
800cade: 431a orrs r2, r3
|
|
Init->InternalBankNumber |\
|
|
800cae0: 683b ldr r3, [r7, #0]
|
|
800cae2: 691b ldr r3, [r3, #16]
|
|
Init->MemoryDataWidth |\
|
|
800cae4: 431a orrs r2, r3
|
|
Init->CASLatency |\
|
|
800cae6: 683b ldr r3, [r7, #0]
|
|
800cae8: 695b ldr r3, [r3, #20]
|
|
Init->InternalBankNumber |\
|
|
800caea: 431a orrs r2, r3
|
|
Init->WriteProtection |\
|
|
800caec: 683b ldr r3, [r7, #0]
|
|
800caee: 699b ldr r3, [r3, #24]
|
|
Init->CASLatency |\
|
|
800caf0: 431a orrs r2, r3
|
|
Init->SDClockPeriod |\
|
|
800caf2: 683b ldr r3, [r7, #0]
|
|
800caf4: 69db ldr r3, [r3, #28]
|
|
Init->WriteProtection |\
|
|
800caf6: 431a orrs r2, r3
|
|
Init->ReadBurst |\
|
|
800caf8: 683b ldr r3, [r7, #0]
|
|
800cafa: 6a1b ldr r3, [r3, #32]
|
|
Init->SDClockPeriod |\
|
|
800cafc: 431a orrs r2, r3
|
|
Init->ReadPipeDelay
|
|
800cafe: 683b ldr r3, [r7, #0]
|
|
800cb00: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
Init->ReadBurst |\
|
|
800cb02: 4313 orrs r3, r2
|
|
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cb04: 68fa ldr r2, [r7, #12]
|
|
800cb06: 4313 orrs r3, r2
|
|
800cb08: 60fb str r3, [r7, #12]
|
|
);
|
|
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
|
|
800cb0a: 687b ldr r3, [r7, #4]
|
|
800cb0c: 68fa ldr r2, [r7, #12]
|
|
800cb0e: 601a str r2, [r3, #0]
|
|
800cb10: e032 b.n 800cb78 <FMC_SDRAM_Init+0xd0>
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
|
|
800cb12: 687b ldr r3, [r7, #4]
|
|
800cb14: 681b ldr r3, [r3, #0]
|
|
800cb16: 60fb str r3, [r7, #12]
|
|
|
|
/* Clear SDCLK, RBURST, and RPIPE bits */
|
|
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
|
|
800cb18: 68fb ldr r3, [r7, #12]
|
|
800cb1a: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
|
|
800cb1e: 60fb str r3, [r7, #12]
|
|
|
|
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
|
|
800cb20: 683b ldr r3, [r7, #0]
|
|
800cb22: 69da ldr r2, [r3, #28]
|
|
Init->ReadBurst |\
|
|
800cb24: 683b ldr r3, [r7, #0]
|
|
800cb26: 6a1b ldr r3, [r3, #32]
|
|
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
|
|
800cb28: 431a orrs r2, r3
|
|
Init->ReadPipeDelay);
|
|
800cb2a: 683b ldr r3, [r7, #0]
|
|
800cb2c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
Init->ReadBurst |\
|
|
800cb2e: 4313 orrs r3, r2
|
|
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
|
|
800cb30: 68fa ldr r2, [r7, #12]
|
|
800cb32: 4313 orrs r3, r2
|
|
800cb34: 60fb str r3, [r7, #12]
|
|
|
|
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
|
|
800cb36: 687b ldr r3, [r7, #4]
|
|
800cb38: 685b ldr r3, [r3, #4]
|
|
800cb3a: 60bb str r3, [r7, #8]
|
|
|
|
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
|
|
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
|
|
800cb3c: 68ba ldr r2, [r7, #8]
|
|
800cb3e: 4b12 ldr r3, [pc, #72] ; (800cb88 <FMC_SDRAM_Init+0xe0>)
|
|
800cb40: 4013 ands r3, r2
|
|
800cb42: 60bb str r3, [r7, #8]
|
|
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
|
|
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
|
|
|
|
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cb44: 683b ldr r3, [r7, #0]
|
|
800cb46: 685a ldr r2, [r3, #4]
|
|
Init->RowBitsNumber |\
|
|
800cb48: 683b ldr r3, [r7, #0]
|
|
800cb4a: 689b ldr r3, [r3, #8]
|
|
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cb4c: 431a orrs r2, r3
|
|
Init->MemoryDataWidth |\
|
|
800cb4e: 683b ldr r3, [r7, #0]
|
|
800cb50: 68db ldr r3, [r3, #12]
|
|
Init->RowBitsNumber |\
|
|
800cb52: 431a orrs r2, r3
|
|
Init->InternalBankNumber |\
|
|
800cb54: 683b ldr r3, [r7, #0]
|
|
800cb56: 691b ldr r3, [r3, #16]
|
|
Init->MemoryDataWidth |\
|
|
800cb58: 431a orrs r2, r3
|
|
Init->CASLatency |\
|
|
800cb5a: 683b ldr r3, [r7, #0]
|
|
800cb5c: 695b ldr r3, [r3, #20]
|
|
Init->InternalBankNumber |\
|
|
800cb5e: 431a orrs r2, r3
|
|
Init->WriteProtection);
|
|
800cb60: 683b ldr r3, [r7, #0]
|
|
800cb62: 699b ldr r3, [r3, #24]
|
|
Init->CASLatency |\
|
|
800cb64: 4313 orrs r3, r2
|
|
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
|
|
800cb66: 68ba ldr r2, [r7, #8]
|
|
800cb68: 4313 orrs r3, r2
|
|
800cb6a: 60bb str r3, [r7, #8]
|
|
|
|
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
|
|
800cb6c: 687b ldr r3, [r7, #4]
|
|
800cb6e: 68fa ldr r2, [r7, #12]
|
|
800cb70: 601a str r2, [r3, #0]
|
|
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
|
|
800cb72: 687b ldr r3, [r7, #4]
|
|
800cb74: 68ba ldr r2, [r7, #8]
|
|
800cb76: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800cb78: 2300 movs r3, #0
|
|
}
|
|
800cb7a: 4618 mov r0, r3
|
|
800cb7c: 3714 adds r7, #20
|
|
800cb7e: 46bd mov sp, r7
|
|
800cb80: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cb84: 4770 bx lr
|
|
800cb86: bf00 nop
|
|
800cb88: ffff8000 .word 0xffff8000
|
|
|
|
0800cb8c <FMC_SDRAM_Timing_Init>:
|
|
* @param Timing Pointer to SDRAM Timing structure
|
|
* @param Bank SDRAM bank number
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
|
|
{
|
|
800cb8c: b480 push {r7}
|
|
800cb8e: b087 sub sp, #28
|
|
800cb90: af00 add r7, sp, #0
|
|
800cb92: 60f8 str r0, [r7, #12]
|
|
800cb94: 60b9 str r1, [r7, #8]
|
|
800cb96: 607a str r2, [r7, #4]
|
|
uint32_t tmpr1 = 0;
|
|
800cb98: 2300 movs r3, #0
|
|
800cb9a: 617b str r3, [r7, #20]
|
|
uint32_t tmpr2 = 0;
|
|
800cb9c: 2300 movs r3, #0
|
|
800cb9e: 613b str r3, [r7, #16]
|
|
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
|
|
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
|
|
assert_param(IS_FMC_SDRAM_BANK(Bank));
|
|
|
|
/* Set SDRAM device timing parameters */
|
|
if (Bank != FMC_SDRAM_BANK2)
|
|
800cba0: 687b ldr r3, [r7, #4]
|
|
800cba2: 2b01 cmp r3, #1
|
|
800cba4: d02e beq.n 800cc04 <FMC_SDRAM_Timing_Init+0x78>
|
|
{
|
|
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
|
|
800cba6: 68fb ldr r3, [r7, #12]
|
|
800cba8: 689b ldr r3, [r3, #8]
|
|
800cbaa: 617b str r3, [r7, #20]
|
|
|
|
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
|
|
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
|
|
800cbac: 697b ldr r3, [r7, #20]
|
|
800cbae: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
|
|
800cbb2: 617b str r3, [r7, #20]
|
|
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
|
|
FMC_SDTR1_TRCD));
|
|
|
|
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cbb4: 68bb ldr r3, [r7, #8]
|
|
800cbb6: 681b ldr r3, [r3, #0]
|
|
800cbb8: 1e5a subs r2, r3, #1
|
|
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
|
|
800cbba: 68bb ldr r3, [r7, #8]
|
|
800cbbc: 685b ldr r3, [r3, #4]
|
|
800cbbe: 3b01 subs r3, #1
|
|
800cbc0: 011b lsls r3, r3, #4
|
|
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cbc2: 431a orrs r2, r3
|
|
(((Timing->SelfRefreshTime)-1) << 8) |\
|
|
800cbc4: 68bb ldr r3, [r7, #8]
|
|
800cbc6: 689b ldr r3, [r3, #8]
|
|
800cbc8: 3b01 subs r3, #1
|
|
800cbca: 021b lsls r3, r3, #8
|
|
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
|
|
800cbcc: 431a orrs r2, r3
|
|
(((Timing->RowCycleDelay)-1) << 12) |\
|
|
800cbce: 68bb ldr r3, [r7, #8]
|
|
800cbd0: 68db ldr r3, [r3, #12]
|
|
800cbd2: 3b01 subs r3, #1
|
|
800cbd4: 031b lsls r3, r3, #12
|
|
(((Timing->SelfRefreshTime)-1) << 8) |\
|
|
800cbd6: 431a orrs r2, r3
|
|
(((Timing->WriteRecoveryTime)-1) <<16) |\
|
|
800cbd8: 68bb ldr r3, [r7, #8]
|
|
800cbda: 691b ldr r3, [r3, #16]
|
|
800cbdc: 3b01 subs r3, #1
|
|
800cbde: 041b lsls r3, r3, #16
|
|
(((Timing->RowCycleDelay)-1) << 12) |\
|
|
800cbe0: 431a orrs r2, r3
|
|
(((Timing->RPDelay)-1) << 20) |\
|
|
800cbe2: 68bb ldr r3, [r7, #8]
|
|
800cbe4: 695b ldr r3, [r3, #20]
|
|
800cbe6: 3b01 subs r3, #1
|
|
800cbe8: 051b lsls r3, r3, #20
|
|
(((Timing->WriteRecoveryTime)-1) <<16) |\
|
|
800cbea: 431a orrs r2, r3
|
|
(((Timing->RCDDelay)-1) << 24));
|
|
800cbec: 68bb ldr r3, [r7, #8]
|
|
800cbee: 699b ldr r3, [r3, #24]
|
|
800cbf0: 3b01 subs r3, #1
|
|
800cbf2: 061b lsls r3, r3, #24
|
|
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cbf4: 4313 orrs r3, r2
|
|
800cbf6: 697a ldr r2, [r7, #20]
|
|
800cbf8: 4313 orrs r3, r2
|
|
800cbfa: 617b str r3, [r7, #20]
|
|
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
|
|
800cbfc: 68fb ldr r3, [r7, #12]
|
|
800cbfe: 697a ldr r2, [r7, #20]
|
|
800cc00: 609a str r2, [r3, #8]
|
|
800cc02: e039 b.n 800cc78 <FMC_SDRAM_Timing_Init+0xec>
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
|
|
800cc04: 68fb ldr r3, [r7, #12]
|
|
800cc06: 689b ldr r3, [r3, #8]
|
|
800cc08: 617b str r3, [r7, #20]
|
|
|
|
/* Clear TRC and TRP bits */
|
|
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
|
|
800cc0a: 697a ldr r2, [r7, #20]
|
|
800cc0c: 4b1e ldr r3, [pc, #120] ; (800cc88 <FMC_SDRAM_Timing_Init+0xfc>)
|
|
800cc0e: 4013 ands r3, r2
|
|
800cc10: 617b str r3, [r7, #20]
|
|
|
|
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
|
|
800cc12: 68bb ldr r3, [r7, #8]
|
|
800cc14: 68db ldr r3, [r3, #12]
|
|
800cc16: 3b01 subs r3, #1
|
|
800cc18: 031a lsls r2, r3, #12
|
|
(((Timing->RPDelay)-1) << 20));
|
|
800cc1a: 68bb ldr r3, [r7, #8]
|
|
800cc1c: 695b ldr r3, [r3, #20]
|
|
800cc1e: 3b01 subs r3, #1
|
|
800cc20: 051b lsls r3, r3, #20
|
|
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
|
|
800cc22: 4313 orrs r3, r2
|
|
800cc24: 697a ldr r2, [r7, #20]
|
|
800cc26: 4313 orrs r3, r2
|
|
800cc28: 617b str r3, [r7, #20]
|
|
|
|
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
|
|
800cc2a: 68fb ldr r3, [r7, #12]
|
|
800cc2c: 68db ldr r3, [r3, #12]
|
|
800cc2e: 613b str r3, [r7, #16]
|
|
|
|
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
|
|
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
|
|
800cc30: 693b ldr r3, [r7, #16]
|
|
800cc32: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
|
|
800cc36: 613b str r3, [r7, #16]
|
|
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
|
|
FMC_SDTR1_TRCD));
|
|
|
|
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cc38: 68bb ldr r3, [r7, #8]
|
|
800cc3a: 681b ldr r3, [r3, #0]
|
|
800cc3c: 1e5a subs r2, r3, #1
|
|
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
|
|
800cc3e: 68bb ldr r3, [r7, #8]
|
|
800cc40: 685b ldr r3, [r3, #4]
|
|
800cc42: 3b01 subs r3, #1
|
|
800cc44: 011b lsls r3, r3, #4
|
|
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cc46: 431a orrs r2, r3
|
|
(((Timing->SelfRefreshTime)-1) << 8) |\
|
|
800cc48: 68bb ldr r3, [r7, #8]
|
|
800cc4a: 689b ldr r3, [r3, #8]
|
|
800cc4c: 3b01 subs r3, #1
|
|
800cc4e: 021b lsls r3, r3, #8
|
|
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
|
|
800cc50: 431a orrs r2, r3
|
|
(((Timing->WriteRecoveryTime)-1) <<16) |\
|
|
800cc52: 68bb ldr r3, [r7, #8]
|
|
800cc54: 691b ldr r3, [r3, #16]
|
|
800cc56: 3b01 subs r3, #1
|
|
800cc58: 041b lsls r3, r3, #16
|
|
(((Timing->SelfRefreshTime)-1) << 8) |\
|
|
800cc5a: 431a orrs r2, r3
|
|
(((Timing->RCDDelay)-1) << 24));
|
|
800cc5c: 68bb ldr r3, [r7, #8]
|
|
800cc5e: 699b ldr r3, [r3, #24]
|
|
800cc60: 3b01 subs r3, #1
|
|
800cc62: 061b lsls r3, r3, #24
|
|
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
|
|
800cc64: 4313 orrs r3, r2
|
|
800cc66: 693a ldr r2, [r7, #16]
|
|
800cc68: 4313 orrs r3, r2
|
|
800cc6a: 613b str r3, [r7, #16]
|
|
|
|
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
|
|
800cc6c: 68fb ldr r3, [r7, #12]
|
|
800cc6e: 697a ldr r2, [r7, #20]
|
|
800cc70: 609a str r2, [r3, #8]
|
|
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
|
|
800cc72: 68fb ldr r3, [r7, #12]
|
|
800cc74: 693a ldr r2, [r7, #16]
|
|
800cc76: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
return HAL_OK;
|
|
800cc78: 2300 movs r3, #0
|
|
}
|
|
800cc7a: 4618 mov r0, r3
|
|
800cc7c: 371c adds r7, #28
|
|
800cc7e: 46bd mov sp, r7
|
|
800cc80: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cc84: 4770 bx lr
|
|
800cc86: bf00 nop
|
|
800cc88: ff0f0fff .word 0xff0f0fff
|
|
|
|
0800cc8c <FMC_SDRAM_SendCommand>:
|
|
* @param Timing Pointer to SDRAM Timing structure
|
|
* @param Timeout Timeout wait value
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
|
{
|
|
800cc8c: b480 push {r7}
|
|
800cc8e: b087 sub sp, #28
|
|
800cc90: af00 add r7, sp, #0
|
|
800cc92: 60f8 str r0, [r7, #12]
|
|
800cc94: 60b9 str r1, [r7, #8]
|
|
800cc96: 607a str r2, [r7, #4]
|
|
__IO uint32_t tmpr = 0;
|
|
800cc98: 2300 movs r3, #0
|
|
800cc9a: 617b str r3, [r7, #20]
|
|
assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
|
|
assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
|
|
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
|
|
|
|
/* Set command register */
|
|
tmpr = (uint32_t)((Command->CommandMode) |\
|
|
800cc9c: 68bb ldr r3, [r7, #8]
|
|
800cc9e: 681a ldr r2, [r3, #0]
|
|
(Command->CommandTarget) |\
|
|
800cca0: 68bb ldr r3, [r7, #8]
|
|
800cca2: 685b ldr r3, [r3, #4]
|
|
tmpr = (uint32_t)((Command->CommandMode) |\
|
|
800cca4: 431a orrs r2, r3
|
|
(((Command->AutoRefreshNumber)-1) << 5) |\
|
|
800cca6: 68bb ldr r3, [r7, #8]
|
|
800cca8: 689b ldr r3, [r3, #8]
|
|
800ccaa: 3b01 subs r3, #1
|
|
800ccac: 015b lsls r3, r3, #5
|
|
(Command->CommandTarget) |\
|
|
800ccae: 431a orrs r2, r3
|
|
((Command->ModeRegisterDefinition) << 9)
|
|
800ccb0: 68bb ldr r3, [r7, #8]
|
|
800ccb2: 68db ldr r3, [r3, #12]
|
|
800ccb4: 025b lsls r3, r3, #9
|
|
tmpr = (uint32_t)((Command->CommandMode) |\
|
|
800ccb6: 4313 orrs r3, r2
|
|
800ccb8: 617b str r3, [r7, #20]
|
|
);
|
|
|
|
Device->SDCMR = tmpr;
|
|
800ccba: 697a ldr r2, [r7, #20]
|
|
800ccbc: 68fb ldr r3, [r7, #12]
|
|
800ccbe: 611a str r2, [r3, #16]
|
|
|
|
return HAL_OK;
|
|
800ccc0: 2300 movs r3, #0
|
|
}
|
|
800ccc2: 4618 mov r0, r3
|
|
800ccc4: 371c adds r7, #28
|
|
800ccc6: 46bd mov sp, r7
|
|
800ccc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cccc: 4770 bx lr
|
|
|
|
0800ccce <FMC_SDRAM_ProgramRefreshRate>:
|
|
* @param Device Pointer to SDRAM device instance
|
|
* @param RefreshRate The SDRAM refresh rate value.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
|
|
{
|
|
800ccce: b480 push {r7}
|
|
800ccd0: b083 sub sp, #12
|
|
800ccd2: af00 add r7, sp, #0
|
|
800ccd4: 6078 str r0, [r7, #4]
|
|
800ccd6: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_FMC_SDRAM_DEVICE(Device));
|
|
assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
|
|
|
|
/* Set the refresh rate in command register */
|
|
Device->SDRTR |= (RefreshRate<<1);
|
|
800ccd8: 687b ldr r3, [r7, #4]
|
|
800ccda: 695a ldr r2, [r3, #20]
|
|
800ccdc: 683b ldr r3, [r7, #0]
|
|
800ccde: 005b lsls r3, r3, #1
|
|
800cce0: 431a orrs r2, r3
|
|
800cce2: 687b ldr r3, [r7, #4]
|
|
800cce4: 615a str r2, [r3, #20]
|
|
|
|
return HAL_OK;
|
|
800cce6: 2300 movs r3, #0
|
|
}
|
|
800cce8: 4618 mov r0, r3
|
|
800ccea: 370c adds r7, #12
|
|
800ccec: 46bd mov sp, r7
|
|
800ccee: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ccf2: 4770 bx lr
|
|
|
|
0800ccf4 <MX_LWIP_Init>:
|
|
|
|
/**
|
|
* LwIP initialization function
|
|
*/
|
|
void MX_LWIP_Init(void)
|
|
{
|
|
800ccf4: b5b0 push {r4, r5, r7, lr}
|
|
800ccf6: b08e sub sp, #56 ; 0x38
|
|
800ccf8: af04 add r7, sp, #16
|
|
/* Initilialize the LwIP stack with RTOS */
|
|
tcpip_init( NULL, NULL );
|
|
800ccfa: 2100 movs r1, #0
|
|
800ccfc: 2000 movs r0, #0
|
|
800ccfe: f003 fead bl 8010a5c <tcpip_init>
|
|
|
|
/* IP addresses initialization with DHCP (IPv4) */
|
|
ipaddr.addr = 0;
|
|
800cd02: 4b2a ldr r3, [pc, #168] ; (800cdac <MX_LWIP_Init+0xb8>)
|
|
800cd04: 2200 movs r2, #0
|
|
800cd06: 601a str r2, [r3, #0]
|
|
netmask.addr = 0;
|
|
800cd08: 4b29 ldr r3, [pc, #164] ; (800cdb0 <MX_LWIP_Init+0xbc>)
|
|
800cd0a: 2200 movs r2, #0
|
|
800cd0c: 601a str r2, [r3, #0]
|
|
gw.addr = 0;
|
|
800cd0e: 4b29 ldr r3, [pc, #164] ; (800cdb4 <MX_LWIP_Init+0xc0>)
|
|
800cd10: 2200 movs r2, #0
|
|
800cd12: 601a str r2, [r3, #0]
|
|
|
|
/* add the network interface (IPv4/IPv6) with RTOS */
|
|
netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, &tcpip_input);
|
|
800cd14: 4b28 ldr r3, [pc, #160] ; (800cdb8 <MX_LWIP_Init+0xc4>)
|
|
800cd16: 9302 str r3, [sp, #8]
|
|
800cd18: 4b28 ldr r3, [pc, #160] ; (800cdbc <MX_LWIP_Init+0xc8>)
|
|
800cd1a: 9301 str r3, [sp, #4]
|
|
800cd1c: 2300 movs r3, #0
|
|
800cd1e: 9300 str r3, [sp, #0]
|
|
800cd20: 4b24 ldr r3, [pc, #144] ; (800cdb4 <MX_LWIP_Init+0xc0>)
|
|
800cd22: 4a23 ldr r2, [pc, #140] ; (800cdb0 <MX_LWIP_Init+0xbc>)
|
|
800cd24: 4921 ldr r1, [pc, #132] ; (800cdac <MX_LWIP_Init+0xb8>)
|
|
800cd26: 4826 ldr r0, [pc, #152] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd28: f004 fc1c bl 8011564 <netif_add>
|
|
|
|
/* Registers the default network interface */
|
|
netif_set_default(&gnetif);
|
|
800cd2c: 4824 ldr r0, [pc, #144] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd2e: f004 fdd3 bl 80118d8 <netif_set_default>
|
|
|
|
if (netif_is_link_up(&gnetif))
|
|
800cd32: 4b23 ldr r3, [pc, #140] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd34: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800cd38: 089b lsrs r3, r3, #2
|
|
800cd3a: f003 0301 and.w r3, r3, #1
|
|
800cd3e: b2db uxtb r3, r3
|
|
800cd40: 2b00 cmp r3, #0
|
|
800cd42: d003 beq.n 800cd4c <MX_LWIP_Init+0x58>
|
|
{
|
|
/* When the netif is fully configured this function must be called */
|
|
netif_set_up(&gnetif);
|
|
800cd44: 481e ldr r0, [pc, #120] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd46: f004 fdd7 bl 80118f8 <netif_set_up>
|
|
800cd4a: e002 b.n 800cd52 <MX_LWIP_Init+0x5e>
|
|
}
|
|
else
|
|
{
|
|
/* When the netif link is down this function must be called */
|
|
netif_set_down(&gnetif);
|
|
800cd4c: 481c ldr r0, [pc, #112] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd4e: f004 fe3f bl 80119d0 <netif_set_down>
|
|
}
|
|
|
|
/* Set the link callback function, this function is called on change of link status*/
|
|
netif_set_link_callback(&gnetif, ethernetif_update_config);
|
|
800cd52: 491c ldr r1, [pc, #112] ; (800cdc4 <MX_LWIP_Init+0xd0>)
|
|
800cd54: 481a ldr r0, [pc, #104] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd56: f004 fed5 bl 8011b04 <netif_set_link_callback>
|
|
|
|
/* create a binary semaphore used for informing ethernetif of frame reception */
|
|
osSemaphoreDef(Netif_SEM);
|
|
800cd5a: 2300 movs r3, #0
|
|
800cd5c: 623b str r3, [r7, #32]
|
|
800cd5e: 2300 movs r3, #0
|
|
800cd60: 627b str r3, [r7, #36] ; 0x24
|
|
Netif_LinkSemaphore = osSemaphoreCreate(osSemaphore(Netif_SEM) , 1 );
|
|
800cd62: f107 0320 add.w r3, r7, #32
|
|
800cd66: 2101 movs r1, #1
|
|
800cd68: 4618 mov r0, r3
|
|
800cd6a: f000 fd75 bl 800d858 <osSemaphoreCreate>
|
|
800cd6e: 4602 mov r2, r0
|
|
800cd70: 4b15 ldr r3, [pc, #84] ; (800cdc8 <MX_LWIP_Init+0xd4>)
|
|
800cd72: 601a str r2, [r3, #0]
|
|
|
|
link_arg.netif = &gnetif;
|
|
800cd74: 4b15 ldr r3, [pc, #84] ; (800cdcc <MX_LWIP_Init+0xd8>)
|
|
800cd76: 4a12 ldr r2, [pc, #72] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cd78: 601a str r2, [r3, #0]
|
|
link_arg.semaphore = Netif_LinkSemaphore;
|
|
800cd7a: 4b13 ldr r3, [pc, #76] ; (800cdc8 <MX_LWIP_Init+0xd4>)
|
|
800cd7c: 681b ldr r3, [r3, #0]
|
|
800cd7e: 4a13 ldr r2, [pc, #76] ; (800cdcc <MX_LWIP_Init+0xd8>)
|
|
800cd80: 6053 str r3, [r2, #4]
|
|
/* Create the Ethernet link handler thread */
|
|
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
|
|
osThreadDef(LinkThr, ethernetif_set_link, osPriorityBelowNormal, 0, configMINIMAL_STACK_SIZE * 2);
|
|
800cd82: 4b13 ldr r3, [pc, #76] ; (800cdd0 <MX_LWIP_Init+0xdc>)
|
|
800cd84: 1d3c adds r4, r7, #4
|
|
800cd86: 461d mov r5, r3
|
|
800cd88: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800cd8a: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800cd8c: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
800cd90: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
osThreadCreate (osThread(LinkThr), &link_arg);
|
|
800cd94: 1d3b adds r3, r7, #4
|
|
800cd96: 490d ldr r1, [pc, #52] ; (800cdcc <MX_LWIP_Init+0xd8>)
|
|
800cd98: 4618 mov r0, r3
|
|
800cd9a: f000 fc60 bl 800d65e <osThreadCreate>
|
|
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
|
|
|
|
/* Start DHCP negotiation for a network interface (IPv4) */
|
|
dhcp_start(&gnetif);
|
|
800cd9e: 4808 ldr r0, [pc, #32] ; (800cdc0 <MX_LWIP_Init+0xcc>)
|
|
800cda0: f00c f812 bl 8018dc8 <dhcp_start>
|
|
|
|
/* USER CODE BEGIN 3 */
|
|
|
|
/* USER CODE END 3 */
|
|
}
|
|
800cda4: bf00 nop
|
|
800cda6: 3728 adds r7, #40 ; 0x28
|
|
800cda8: 46bd mov sp, r7
|
|
800cdaa: bdb0 pop {r4, r5, r7, pc}
|
|
800cdac: 20008fd0 .word 0x20008fd0
|
|
800cdb0: 20008fd4 .word 0x20008fd4
|
|
800cdb4: 20008fd8 .word 0x20008fd8
|
|
800cdb8: 08010999 .word 0x08010999
|
|
800cdbc: 0800d3ed .word 0x0800d3ed
|
|
800cdc0: 20008f98 .word 0x20008f98
|
|
800cdc4: 0800d4d1 .word 0x0800d4d1
|
|
800cdc8: 20000584 .word 0x20000584
|
|
800cdcc: 20008f90 .word 0x20008f90
|
|
800cdd0: 0801df38 .word 0x0801df38
|
|
|
|
0800cdd4 <HAL_ETH_MspInit>:
|
|
/* USER CODE END 3 */
|
|
|
|
/* Private functions ---------------------------------------------------------*/
|
|
|
|
void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle)
|
|
{
|
|
800cdd4: b580 push {r7, lr}
|
|
800cdd6: b08e sub sp, #56 ; 0x38
|
|
800cdd8: af00 add r7, sp, #0
|
|
800cdda: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800cddc: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
800cde0: 2200 movs r2, #0
|
|
800cde2: 601a str r2, [r3, #0]
|
|
800cde4: 605a str r2, [r3, #4]
|
|
800cde6: 609a str r2, [r3, #8]
|
|
800cde8: 60da str r2, [r3, #12]
|
|
800cdea: 611a str r2, [r3, #16]
|
|
if(ethHandle->Instance==ETH)
|
|
800cdec: 687b ldr r3, [r7, #4]
|
|
800cdee: 681b ldr r3, [r3, #0]
|
|
800cdf0: 4a44 ldr r2, [pc, #272] ; (800cf04 <HAL_ETH_MspInit+0x130>)
|
|
800cdf2: 4293 cmp r3, r2
|
|
800cdf4: f040 8081 bne.w 800cefa <HAL_ETH_MspInit+0x126>
|
|
{
|
|
/* USER CODE BEGIN ETH_MspInit 0 */
|
|
|
|
/* USER CODE END ETH_MspInit 0 */
|
|
/* Enable Peripheral clock */
|
|
__HAL_RCC_ETH_CLK_ENABLE();
|
|
800cdf8: 4b43 ldr r3, [pc, #268] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800cdfa: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800cdfc: 4a42 ldr r2, [pc, #264] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800cdfe: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
|
|
800ce02: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce04: 4b40 ldr r3, [pc, #256] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce06: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce08: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
|
|
800ce0c: 623b str r3, [r7, #32]
|
|
800ce0e: 6a3b ldr r3, [r7, #32]
|
|
800ce10: 4b3d ldr r3, [pc, #244] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce12: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce14: 4a3c ldr r2, [pc, #240] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce16: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
|
|
800ce1a: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce1c: 4b3a ldr r3, [pc, #232] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce1e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce20: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
|
|
800ce24: 61fb str r3, [r7, #28]
|
|
800ce26: 69fb ldr r3, [r7, #28]
|
|
800ce28: 4b37 ldr r3, [pc, #220] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce2a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce2c: 4a36 ldr r2, [pc, #216] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce2e: f043 6300 orr.w r3, r3, #134217728 ; 0x8000000
|
|
800ce32: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce34: 4b34 ldr r3, [pc, #208] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce36: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce38: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
|
|
800ce3c: 61bb str r3, [r7, #24]
|
|
800ce3e: 69bb ldr r3, [r7, #24]
|
|
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
800ce40: 4b31 ldr r3, [pc, #196] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce42: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce44: 4a30 ldr r2, [pc, #192] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce46: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
800ce4a: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce4c: 4b2e ldr r3, [pc, #184] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce4e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce50: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
800ce54: 617b str r3, [r7, #20]
|
|
800ce56: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
800ce58: 4b2b ldr r3, [pc, #172] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce5a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce5c: 4a2a ldr r2, [pc, #168] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce5e: f043 0304 orr.w r3, r3, #4
|
|
800ce62: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce64: 4b28 ldr r3, [pc, #160] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce66: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce68: f003 0304 and.w r3, r3, #4
|
|
800ce6c: 613b str r3, [r7, #16]
|
|
800ce6e: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800ce70: 4b25 ldr r3, [pc, #148] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce72: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce74: 4a24 ldr r2, [pc, #144] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce76: f043 0301 orr.w r3, r3, #1
|
|
800ce7a: 6313 str r3, [r2, #48] ; 0x30
|
|
800ce7c: 4b22 ldr r3, [pc, #136] ; (800cf08 <HAL_ETH_MspInit+0x134>)
|
|
800ce7e: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ce80: f003 0301 and.w r3, r3, #1
|
|
800ce84: 60fb str r3, [r7, #12]
|
|
800ce86: 68fb ldr r3, [r7, #12]
|
|
PC4 ------> ETH_RXD0
|
|
PA2 ------> ETH_MDIO
|
|
PC5 ------> ETH_RXD1
|
|
PA7 ------> ETH_CRS_DV
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11;
|
|
800ce88: f44f 43d0 mov.w r3, #26624 ; 0x6800
|
|
800ce8c: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800ce8e: 2302 movs r3, #2
|
|
800ce90: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800ce92: 2300 movs r3, #0
|
|
800ce94: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800ce96: 2303 movs r3, #3
|
|
800ce98: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
|
800ce9a: 230b movs r3, #11
|
|
800ce9c: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
800ce9e: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
800cea2: 4619 mov r1, r3
|
|
800cea4: 4819 ldr r0, [pc, #100] ; (800cf0c <HAL_ETH_MspInit+0x138>)
|
|
800cea6: f7fa fe8b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
|
|
800ceaa: 2332 movs r3, #50 ; 0x32
|
|
800ceac: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800ceae: 2302 movs r3, #2
|
|
800ceb0: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800ceb2: 2300 movs r3, #0
|
|
800ceb4: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800ceb6: 2303 movs r3, #3
|
|
800ceb8: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
|
800ceba: 230b movs r3, #11
|
|
800cebc: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
800cebe: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
800cec2: 4619 mov r1, r3
|
|
800cec4: 4812 ldr r0, [pc, #72] ; (800cf10 <HAL_ETH_MspInit+0x13c>)
|
|
800cec6: f7fa fe7b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
|
|
800ceca: 2386 movs r3, #134 ; 0x86
|
|
800cecc: 627b str r3, [r7, #36] ; 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800cece: 2302 movs r3, #2
|
|
800ced0: 62bb str r3, [r7, #40] ; 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800ced2: 2300 movs r3, #0
|
|
800ced4: 62fb str r3, [r7, #44] ; 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800ced6: 2303 movs r3, #3
|
|
800ced8: 633b str r3, [r7, #48] ; 0x30
|
|
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
|
|
800ceda: 230b movs r3, #11
|
|
800cedc: 637b str r3, [r7, #52] ; 0x34
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800cede: f107 0324 add.w r3, r7, #36 ; 0x24
|
|
800cee2: 4619 mov r1, r3
|
|
800cee4: 480b ldr r0, [pc, #44] ; (800cf14 <HAL_ETH_MspInit+0x140>)
|
|
800cee6: f7fa fe6b bl 8007bc0 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(ETH_IRQn, 5, 0);
|
|
800ceea: 2200 movs r2, #0
|
|
800ceec: 2105 movs r1, #5
|
|
800ceee: 203d movs r0, #61 ; 0x3d
|
|
800cef0: f7f8 feb6 bl 8005c60 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
|
800cef4: 203d movs r0, #61 ; 0x3d
|
|
800cef6: f7f8 fecf bl 8005c98 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN ETH_MspInit 1 */
|
|
|
|
/* USER CODE END ETH_MspInit 1 */
|
|
}
|
|
}
|
|
800cefa: bf00 nop
|
|
800cefc: 3738 adds r7, #56 ; 0x38
|
|
800cefe: 46bd mov sp, r7
|
|
800cf00: bd80 pop {r7, pc}
|
|
800cf02: bf00 nop
|
|
800cf04: 40028000 .word 0x40028000
|
|
800cf08: 40023800 .word 0x40023800
|
|
800cf0c: 40021800 .word 0x40021800
|
|
800cf10: 40020800 .word 0x40020800
|
|
800cf14: 40020000 .word 0x40020000
|
|
|
|
0800cf18 <HAL_ETH_RxCpltCallback>:
|
|
* @brief Ethernet Rx Transfer completed callback
|
|
* @param heth: ETH handle
|
|
* @retval None
|
|
*/
|
|
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
|
{
|
|
800cf18: b580 push {r7, lr}
|
|
800cf1a: b082 sub sp, #8
|
|
800cf1c: af00 add r7, sp, #0
|
|
800cf1e: 6078 str r0, [r7, #4]
|
|
osSemaphoreRelease(s_xSemaphore);
|
|
800cf20: 4b04 ldr r3, [pc, #16] ; (800cf34 <HAL_ETH_RxCpltCallback+0x1c>)
|
|
800cf22: 681b ldr r3, [r3, #0]
|
|
800cf24: 4618 mov r0, r3
|
|
800cf26: f000 fd25 bl 800d974 <osSemaphoreRelease>
|
|
}
|
|
800cf2a: bf00 nop
|
|
800cf2c: 3708 adds r7, #8
|
|
800cf2e: 46bd mov sp, r7
|
|
800cf30: bd80 pop {r7, pc}
|
|
800cf32: bf00 nop
|
|
800cf34: 20000588 .word 0x20000588
|
|
|
|
0800cf38 <low_level_init>:
|
|
*
|
|
* @param netif the already initialized lwip network interface structure
|
|
* for this ethernetif
|
|
*/
|
|
static void low_level_init(struct netif *netif)
|
|
{
|
|
800cf38: b5b0 push {r4, r5, r7, lr}
|
|
800cf3a: b090 sub sp, #64 ; 0x40
|
|
800cf3c: af00 add r7, sp, #0
|
|
800cf3e: 6078 str r0, [r7, #4]
|
|
uint32_t regvalue = 0;
|
|
800cf40: 2300 movs r3, #0
|
|
800cf42: 63bb str r3, [r7, #56] ; 0x38
|
|
HAL_StatusTypeDef hal_eth_init_status;
|
|
|
|
/* Init ETH */
|
|
|
|
uint8_t MACAddr[6] ;
|
|
heth.Instance = ETH;
|
|
800cf44: 4b60 ldr r3, [pc, #384] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf46: 4a61 ldr r2, [pc, #388] ; (800d0cc <low_level_init+0x194>)
|
|
800cf48: 601a str r2, [r3, #0]
|
|
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
|
800cf4a: 4b5f ldr r3, [pc, #380] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf4c: 2201 movs r2, #1
|
|
800cf4e: 605a str r2, [r3, #4]
|
|
heth.Init.Speed = ETH_SPEED_100M;
|
|
800cf50: 4b5d ldr r3, [pc, #372] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf52: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
800cf56: 609a str r2, [r3, #8]
|
|
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
|
800cf58: 4b5b ldr r3, [pc, #364] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf5a: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
800cf5e: 60da str r2, [r3, #12]
|
|
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
|
|
800cf60: 4b59 ldr r3, [pc, #356] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf62: 2201 movs r2, #1
|
|
800cf64: 821a strh r2, [r3, #16]
|
|
MACAddr[0] = 0x00;
|
|
800cf66: 2300 movs r3, #0
|
|
800cf68: f887 3030 strb.w r3, [r7, #48] ; 0x30
|
|
MACAddr[1] = 0x80;
|
|
800cf6c: 2380 movs r3, #128 ; 0x80
|
|
800cf6e: f887 3031 strb.w r3, [r7, #49] ; 0x31
|
|
MACAddr[2] = 0xE1;
|
|
800cf72: 23e1 movs r3, #225 ; 0xe1
|
|
800cf74: f887 3032 strb.w r3, [r7, #50] ; 0x32
|
|
MACAddr[3] = 0x00;
|
|
800cf78: 2300 movs r3, #0
|
|
800cf7a: f887 3033 strb.w r3, [r7, #51] ; 0x33
|
|
MACAddr[4] = 0x00;
|
|
800cf7e: 2300 movs r3, #0
|
|
800cf80: f887 3034 strb.w r3, [r7, #52] ; 0x34
|
|
MACAddr[5] = 0x00;
|
|
800cf84: 2300 movs r3, #0
|
|
800cf86: f887 3035 strb.w r3, [r7, #53] ; 0x35
|
|
heth.Init.MACAddr = &MACAddr[0];
|
|
800cf8a: 4a4f ldr r2, [pc, #316] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf8c: f107 0330 add.w r3, r7, #48 ; 0x30
|
|
800cf90: 6153 str r3, [r2, #20]
|
|
heth.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
|
800cf92: 4b4d ldr r3, [pc, #308] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf94: 2201 movs r2, #1
|
|
800cf96: 619a str r2, [r3, #24]
|
|
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
|
800cf98: 4b4b ldr r3, [pc, #300] ; (800d0c8 <low_level_init+0x190>)
|
|
800cf9a: 2200 movs r2, #0
|
|
800cf9c: 61da str r2, [r3, #28]
|
|
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
|
800cf9e: 4b4a ldr r3, [pc, #296] ; (800d0c8 <low_level_init+0x190>)
|
|
800cfa0: f44f 0200 mov.w r2, #8388608 ; 0x800000
|
|
800cfa4: 621a str r2, [r3, #32]
|
|
|
|
/* USER CODE BEGIN MACADDRESS */
|
|
|
|
/* USER CODE END MACADDRESS */
|
|
|
|
hal_eth_init_status = HAL_ETH_Init(&heth);
|
|
800cfa6: 4848 ldr r0, [pc, #288] ; (800d0c8 <low_level_init+0x190>)
|
|
800cfa8: f7f9 fc84 bl 80068b4 <HAL_ETH_Init>
|
|
800cfac: 4603 mov r3, r0
|
|
800cfae: f887 303f strb.w r3, [r7, #63] ; 0x3f
|
|
|
|
if (hal_eth_init_status == HAL_OK)
|
|
800cfb2: f897 303f ldrb.w r3, [r7, #63] ; 0x3f
|
|
800cfb6: 2b00 cmp r3, #0
|
|
800cfb8: d108 bne.n 800cfcc <low_level_init+0x94>
|
|
{
|
|
/* Set netif link flag */
|
|
netif->flags |= NETIF_FLAG_LINK_UP;
|
|
800cfba: 687b ldr r3, [r7, #4]
|
|
800cfbc: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800cfc0: f043 0304 orr.w r3, r3, #4
|
|
800cfc4: b2da uxtb r2, r3
|
|
800cfc6: 687b ldr r3, [r7, #4]
|
|
800cfc8: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
}
|
|
/* Initialize Tx Descriptors list: Chain Mode */
|
|
HAL_ETH_DMATxDescListInit(&heth, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
|
|
800cfcc: 2304 movs r3, #4
|
|
800cfce: 4a40 ldr r2, [pc, #256] ; (800d0d0 <low_level_init+0x198>)
|
|
800cfd0: 4940 ldr r1, [pc, #256] ; (800d0d4 <low_level_init+0x19c>)
|
|
800cfd2: 483d ldr r0, [pc, #244] ; (800d0c8 <low_level_init+0x190>)
|
|
800cfd4: f7f9 fe0a bl 8006bec <HAL_ETH_DMATxDescListInit>
|
|
|
|
/* Initialize Rx Descriptors list: Chain Mode */
|
|
HAL_ETH_DMARxDescListInit(&heth, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
|
|
800cfd8: 2304 movs r3, #4
|
|
800cfda: 4a3f ldr r2, [pc, #252] ; (800d0d8 <low_level_init+0x1a0>)
|
|
800cfdc: 493f ldr r1, [pc, #252] ; (800d0dc <low_level_init+0x1a4>)
|
|
800cfde: 483a ldr r0, [pc, #232] ; (800d0c8 <low_level_init+0x190>)
|
|
800cfe0: f7f9 fe6d bl 8006cbe <HAL_ETH_DMARxDescListInit>
|
|
|
|
#if LWIP_ARP || LWIP_ETHERNET
|
|
|
|
/* set MAC hardware address length */
|
|
netif->hwaddr_len = ETH_HWADDR_LEN;
|
|
800cfe4: 687b ldr r3, [r7, #4]
|
|
800cfe6: 2206 movs r2, #6
|
|
800cfe8: f883 2030 strb.w r2, [r3, #48] ; 0x30
|
|
|
|
/* set MAC hardware address */
|
|
netif->hwaddr[0] = heth.Init.MACAddr[0];
|
|
800cfec: 4b36 ldr r3, [pc, #216] ; (800d0c8 <low_level_init+0x190>)
|
|
800cfee: 695b ldr r3, [r3, #20]
|
|
800cff0: 781a ldrb r2, [r3, #0]
|
|
800cff2: 687b ldr r3, [r7, #4]
|
|
800cff4: f883 202a strb.w r2, [r3, #42] ; 0x2a
|
|
netif->hwaddr[1] = heth.Init.MACAddr[1];
|
|
800cff8: 4b33 ldr r3, [pc, #204] ; (800d0c8 <low_level_init+0x190>)
|
|
800cffa: 695b ldr r3, [r3, #20]
|
|
800cffc: 785a ldrb r2, [r3, #1]
|
|
800cffe: 687b ldr r3, [r7, #4]
|
|
800d000: f883 202b strb.w r2, [r3, #43] ; 0x2b
|
|
netif->hwaddr[2] = heth.Init.MACAddr[2];
|
|
800d004: 4b30 ldr r3, [pc, #192] ; (800d0c8 <low_level_init+0x190>)
|
|
800d006: 695b ldr r3, [r3, #20]
|
|
800d008: 789a ldrb r2, [r3, #2]
|
|
800d00a: 687b ldr r3, [r7, #4]
|
|
800d00c: f883 202c strb.w r2, [r3, #44] ; 0x2c
|
|
netif->hwaddr[3] = heth.Init.MACAddr[3];
|
|
800d010: 4b2d ldr r3, [pc, #180] ; (800d0c8 <low_level_init+0x190>)
|
|
800d012: 695b ldr r3, [r3, #20]
|
|
800d014: 78da ldrb r2, [r3, #3]
|
|
800d016: 687b ldr r3, [r7, #4]
|
|
800d018: f883 202d strb.w r2, [r3, #45] ; 0x2d
|
|
netif->hwaddr[4] = heth.Init.MACAddr[4];
|
|
800d01c: 4b2a ldr r3, [pc, #168] ; (800d0c8 <low_level_init+0x190>)
|
|
800d01e: 695b ldr r3, [r3, #20]
|
|
800d020: 791a ldrb r2, [r3, #4]
|
|
800d022: 687b ldr r3, [r7, #4]
|
|
800d024: f883 202e strb.w r2, [r3, #46] ; 0x2e
|
|
netif->hwaddr[5] = heth.Init.MACAddr[5];
|
|
800d028: 4b27 ldr r3, [pc, #156] ; (800d0c8 <low_level_init+0x190>)
|
|
800d02a: 695b ldr r3, [r3, #20]
|
|
800d02c: 795a ldrb r2, [r3, #5]
|
|
800d02e: 687b ldr r3, [r7, #4]
|
|
800d030: f883 202f strb.w r2, [r3, #47] ; 0x2f
|
|
|
|
/* maximum transfer unit */
|
|
netif->mtu = 1500;
|
|
800d034: 687b ldr r3, [r7, #4]
|
|
800d036: f240 52dc movw r2, #1500 ; 0x5dc
|
|
800d03a: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
/* Accept broadcast address and ARP traffic */
|
|
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
|
|
#if LWIP_ARP
|
|
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
|
|
800d03c: 687b ldr r3, [r7, #4]
|
|
800d03e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800d042: f043 030a orr.w r3, r3, #10
|
|
800d046: b2da uxtb r2, r3
|
|
800d048: 687b ldr r3, [r7, #4]
|
|
800d04a: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
#else
|
|
netif->flags |= NETIF_FLAG_BROADCAST;
|
|
#endif /* LWIP_ARP */
|
|
|
|
/* create a binary semaphore used for informing ethernetif of frame reception */
|
|
osSemaphoreDef(SEM);
|
|
800d04e: 2300 movs r3, #0
|
|
800d050: 62bb str r3, [r7, #40] ; 0x28
|
|
800d052: 2300 movs r3, #0
|
|
800d054: 62fb str r3, [r7, #44] ; 0x2c
|
|
s_xSemaphore = osSemaphoreCreate(osSemaphore(SEM), 1);
|
|
800d056: f107 0328 add.w r3, r7, #40 ; 0x28
|
|
800d05a: 2101 movs r1, #1
|
|
800d05c: 4618 mov r0, r3
|
|
800d05e: f000 fbfb bl 800d858 <osSemaphoreCreate>
|
|
800d062: 4602 mov r2, r0
|
|
800d064: 4b1e ldr r3, [pc, #120] ; (800d0e0 <low_level_init+0x1a8>)
|
|
800d066: 601a str r2, [r3, #0]
|
|
|
|
/* create the task that handles the ETH_MAC */
|
|
/* USER CODE BEGIN OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
|
|
osThreadDef(EthIf, ethernetif_input, osPriorityRealtime, 0, INTERFACE_THREAD_STACK_SIZE);
|
|
800d068: 4b1e ldr r3, [pc, #120] ; (800d0e4 <low_level_init+0x1ac>)
|
|
800d06a: f107 040c add.w r4, r7, #12
|
|
800d06e: 461d mov r5, r3
|
|
800d070: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800d072: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800d074: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
800d078: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
osThreadCreate (osThread(EthIf), netif);
|
|
800d07c: f107 030c add.w r3, r7, #12
|
|
800d080: 6879 ldr r1, [r7, #4]
|
|
800d082: 4618 mov r0, r3
|
|
800d084: f000 faeb bl 800d65e <osThreadCreate>
|
|
/* USER CODE END OS_THREAD_DEF_CREATE_CMSIS_RTOS_V1 */
|
|
/* Enable MAC and DMA transmission and reception */
|
|
HAL_ETH_Start(&heth);
|
|
800d088: 480f ldr r0, [pc, #60] ; (800d0c8 <low_level_init+0x190>)
|
|
800d08a: f7fa f940 bl 800730e <HAL_ETH_Start>
|
|
/* USER CODE BEGIN PHY_PRE_CONFIG */
|
|
|
|
/* USER CODE END PHY_PRE_CONFIG */
|
|
|
|
/* Read Register Configuration */
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR, ®value);
|
|
800d08e: f107 0338 add.w r3, r7, #56 ; 0x38
|
|
800d092: 461a mov r2, r3
|
|
800d094: 211d movs r1, #29
|
|
800d096: 480c ldr r0, [pc, #48] ; (800d0c8 <low_level_init+0x190>)
|
|
800d098: f7fa f86b bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
regvalue |= (PHY_ISFR_INT4);
|
|
800d09c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
800d09e: f043 030b orr.w r3, r3, #11
|
|
800d0a2: 63bb str r3, [r7, #56] ; 0x38
|
|
|
|
/* Enable Interrupt on change of link status */
|
|
HAL_ETH_WritePHYRegister(&heth, PHY_ISFR , regvalue );
|
|
800d0a4: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
800d0a6: 461a mov r2, r3
|
|
800d0a8: 211d movs r1, #29
|
|
800d0aa: 4807 ldr r0, [pc, #28] ; (800d0c8 <low_level_init+0x190>)
|
|
800d0ac: f7fa f8c9 bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
|
|
/* Read Register Configuration */
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_ISFR , ®value);
|
|
800d0b0: f107 0338 add.w r3, r7, #56 ; 0x38
|
|
800d0b4: 461a mov r2, r3
|
|
800d0b6: 211d movs r1, #29
|
|
800d0b8: 4803 ldr r0, [pc, #12] ; (800d0c8 <low_level_init+0x190>)
|
|
800d0ba: f7fa f85a bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
#endif /* LWIP_ARP || LWIP_ETHERNET */
|
|
|
|
/* USER CODE BEGIN LOW_LEVEL_INIT */
|
|
|
|
/* USER CODE END LOW_LEVEL_INIT */
|
|
}
|
|
800d0be: bf00 nop
|
|
800d0c0: 3740 adds r7, #64 ; 0x40
|
|
800d0c2: 46bd mov sp, r7
|
|
800d0c4: bdb0 pop {r4, r5, r7, pc}
|
|
800d0c6: bf00 nop
|
|
800d0c8: 2000a8ac .word 0x2000a8ac
|
|
800d0cc: 40028000 .word 0x40028000
|
|
800d0d0: 2000a8f4 .word 0x2000a8f4
|
|
800d0d4: 20008fdc .word 0x20008fdc
|
|
800d0d8: 2000905c .word 0x2000905c
|
|
800d0dc: 2000a82c .word 0x2000a82c
|
|
800d0e0: 20000588 .word 0x20000588
|
|
800d0e4: 0801df5c .word 0x0801df5c
|
|
|
|
0800d0e8 <low_level_output>:
|
|
* to become availale since the stack doesn't retry to send a packet
|
|
* dropped because of memory failure (except for the TCP timers).
|
|
*/
|
|
|
|
static err_t low_level_output(struct netif *netif, struct pbuf *p)
|
|
{
|
|
800d0e8: b580 push {r7, lr}
|
|
800d0ea: b08a sub sp, #40 ; 0x28
|
|
800d0ec: af00 add r7, sp, #0
|
|
800d0ee: 6078 str r0, [r7, #4]
|
|
800d0f0: 6039 str r1, [r7, #0]
|
|
err_t errval;
|
|
struct pbuf *q;
|
|
uint8_t *buffer = (uint8_t *)(heth.TxDesc->Buffer1Addr);
|
|
800d0f2: 4b4b ldr r3, [pc, #300] ; (800d220 <low_level_output+0x138>)
|
|
800d0f4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800d0f6: 689b ldr r3, [r3, #8]
|
|
800d0f8: 61fb str r3, [r7, #28]
|
|
__IO ETH_DMADescTypeDef *DmaTxDesc;
|
|
uint32_t framelength = 0;
|
|
800d0fa: 2300 movs r3, #0
|
|
800d0fc: 617b str r3, [r7, #20]
|
|
uint32_t bufferoffset = 0;
|
|
800d0fe: 2300 movs r3, #0
|
|
800d100: 613b str r3, [r7, #16]
|
|
uint32_t byteslefttocopy = 0;
|
|
800d102: 2300 movs r3, #0
|
|
800d104: 60fb str r3, [r7, #12]
|
|
uint32_t payloadoffset = 0;
|
|
800d106: 2300 movs r3, #0
|
|
800d108: 60bb str r3, [r7, #8]
|
|
DmaTxDesc = heth.TxDesc;
|
|
800d10a: 4b45 ldr r3, [pc, #276] ; (800d220 <low_level_output+0x138>)
|
|
800d10c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800d10e: 61bb str r3, [r7, #24]
|
|
bufferoffset = 0;
|
|
800d110: 2300 movs r3, #0
|
|
800d112: 613b str r3, [r7, #16]
|
|
|
|
/* copy frame from pbufs to driver buffers */
|
|
for(q = p; q != NULL; q = q->next)
|
|
800d114: 683b ldr r3, [r7, #0]
|
|
800d116: 623b str r3, [r7, #32]
|
|
800d118: e05a b.n 800d1d0 <low_level_output+0xe8>
|
|
{
|
|
/* Is this buffer available? If not, goto error */
|
|
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
|
800d11a: 69bb ldr r3, [r7, #24]
|
|
800d11c: 681b ldr r3, [r3, #0]
|
|
800d11e: 2b00 cmp r3, #0
|
|
800d120: da03 bge.n 800d12a <low_level_output+0x42>
|
|
{
|
|
errval = ERR_USE;
|
|
800d122: 23f8 movs r3, #248 ; 0xf8
|
|
800d124: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
goto error;
|
|
800d128: e05c b.n 800d1e4 <low_level_output+0xfc>
|
|
}
|
|
|
|
/* Get bytes in current lwIP buffer */
|
|
byteslefttocopy = q->len;
|
|
800d12a: 6a3b ldr r3, [r7, #32]
|
|
800d12c: 895b ldrh r3, [r3, #10]
|
|
800d12e: 60fb str r3, [r7, #12]
|
|
payloadoffset = 0;
|
|
800d130: 2300 movs r3, #0
|
|
800d132: 60bb str r3, [r7, #8]
|
|
|
|
/* Check if the length of data to copy is bigger than Tx buffer size*/
|
|
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
|
|
800d134: e02f b.n 800d196 <low_level_output+0xae>
|
|
{
|
|
/* Copy data to Tx buffer*/
|
|
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
|
|
800d136: 69fa ldr r2, [r7, #28]
|
|
800d138: 693b ldr r3, [r7, #16]
|
|
800d13a: 18d0 adds r0, r2, r3
|
|
800d13c: 6a3b ldr r3, [r7, #32]
|
|
800d13e: 685a ldr r2, [r3, #4]
|
|
800d140: 68bb ldr r3, [r7, #8]
|
|
800d142: 18d1 adds r1, r2, r3
|
|
800d144: 693a ldr r2, [r7, #16]
|
|
800d146: f240 53f4 movw r3, #1524 ; 0x5f4
|
|
800d14a: 1a9b subs r3, r3, r2
|
|
800d14c: 461a mov r2, r3
|
|
800d14e: f00f fd86 bl 801cc5e <memcpy>
|
|
|
|
/* Point to next descriptor */
|
|
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
|
|
800d152: 69bb ldr r3, [r7, #24]
|
|
800d154: 68db ldr r3, [r3, #12]
|
|
800d156: 61bb str r3, [r7, #24]
|
|
|
|
/* Check if the buffer is available */
|
|
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
|
800d158: 69bb ldr r3, [r7, #24]
|
|
800d15a: 681b ldr r3, [r3, #0]
|
|
800d15c: 2b00 cmp r3, #0
|
|
800d15e: da03 bge.n 800d168 <low_level_output+0x80>
|
|
{
|
|
errval = ERR_USE;
|
|
800d160: 23f8 movs r3, #248 ; 0xf8
|
|
800d162: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
goto error;
|
|
800d166: e03d b.n 800d1e4 <low_level_output+0xfc>
|
|
}
|
|
|
|
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
|
|
800d168: 69bb ldr r3, [r7, #24]
|
|
800d16a: 689b ldr r3, [r3, #8]
|
|
800d16c: 61fb str r3, [r7, #28]
|
|
|
|
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
|
|
800d16e: 693a ldr r2, [r7, #16]
|
|
800d170: 68fb ldr r3, [r7, #12]
|
|
800d172: 4413 add r3, r2
|
|
800d174: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
|
|
800d178: 60fb str r3, [r7, #12]
|
|
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
|
|
800d17a: 68ba ldr r2, [r7, #8]
|
|
800d17c: 693b ldr r3, [r7, #16]
|
|
800d17e: 1ad3 subs r3, r2, r3
|
|
800d180: f203 53f4 addw r3, r3, #1524 ; 0x5f4
|
|
800d184: 60bb str r3, [r7, #8]
|
|
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
|
|
800d186: 697a ldr r2, [r7, #20]
|
|
800d188: 693b ldr r3, [r7, #16]
|
|
800d18a: 1ad3 subs r3, r2, r3
|
|
800d18c: f203 53f4 addw r3, r3, #1524 ; 0x5f4
|
|
800d190: 617b str r3, [r7, #20]
|
|
bufferoffset = 0;
|
|
800d192: 2300 movs r3, #0
|
|
800d194: 613b str r3, [r7, #16]
|
|
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
|
|
800d196: 68fa ldr r2, [r7, #12]
|
|
800d198: 693b ldr r3, [r7, #16]
|
|
800d19a: 4413 add r3, r2
|
|
800d19c: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
800d1a0: 4293 cmp r3, r2
|
|
800d1a2: d8c8 bhi.n 800d136 <low_level_output+0x4e>
|
|
}
|
|
|
|
/* Copy the remaining bytes */
|
|
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
|
|
800d1a4: 69fa ldr r2, [r7, #28]
|
|
800d1a6: 693b ldr r3, [r7, #16]
|
|
800d1a8: 18d0 adds r0, r2, r3
|
|
800d1aa: 6a3b ldr r3, [r7, #32]
|
|
800d1ac: 685a ldr r2, [r3, #4]
|
|
800d1ae: 68bb ldr r3, [r7, #8]
|
|
800d1b0: 4413 add r3, r2
|
|
800d1b2: 68fa ldr r2, [r7, #12]
|
|
800d1b4: 4619 mov r1, r3
|
|
800d1b6: f00f fd52 bl 801cc5e <memcpy>
|
|
bufferoffset = bufferoffset + byteslefttocopy;
|
|
800d1ba: 693a ldr r2, [r7, #16]
|
|
800d1bc: 68fb ldr r3, [r7, #12]
|
|
800d1be: 4413 add r3, r2
|
|
800d1c0: 613b str r3, [r7, #16]
|
|
framelength = framelength + byteslefttocopy;
|
|
800d1c2: 697a ldr r2, [r7, #20]
|
|
800d1c4: 68fb ldr r3, [r7, #12]
|
|
800d1c6: 4413 add r3, r2
|
|
800d1c8: 617b str r3, [r7, #20]
|
|
for(q = p; q != NULL; q = q->next)
|
|
800d1ca: 6a3b ldr r3, [r7, #32]
|
|
800d1cc: 681b ldr r3, [r3, #0]
|
|
800d1ce: 623b str r3, [r7, #32]
|
|
800d1d0: 6a3b ldr r3, [r7, #32]
|
|
800d1d2: 2b00 cmp r3, #0
|
|
800d1d4: d1a1 bne.n 800d11a <low_level_output+0x32>
|
|
}
|
|
|
|
/* Prepare transmit descriptors to give to DMA */
|
|
HAL_ETH_TransmitFrame(&heth, framelength);
|
|
800d1d6: 6979 ldr r1, [r7, #20]
|
|
800d1d8: 4811 ldr r0, [pc, #68] ; (800d220 <low_level_output+0x138>)
|
|
800d1da: f7f9 fddd bl 8006d98 <HAL_ETH_TransmitFrame>
|
|
|
|
errval = ERR_OK;
|
|
800d1de: 2300 movs r3, #0
|
|
800d1e0: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
error:
|
|
|
|
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
|
|
if ((heth.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
|
|
800d1e4: 4b0e ldr r3, [pc, #56] ; (800d220 <low_level_output+0x138>)
|
|
800d1e6: 681a ldr r2, [r3, #0]
|
|
800d1e8: f241 0314 movw r3, #4116 ; 0x1014
|
|
800d1ec: 4413 add r3, r2
|
|
800d1ee: 681b ldr r3, [r3, #0]
|
|
800d1f0: f003 0320 and.w r3, r3, #32
|
|
800d1f4: 2b00 cmp r3, #0
|
|
800d1f6: d00d beq.n 800d214 <low_level_output+0x12c>
|
|
{
|
|
/* Clear TUS ETHERNET DMA flag */
|
|
heth.Instance->DMASR = ETH_DMASR_TUS;
|
|
800d1f8: 4b09 ldr r3, [pc, #36] ; (800d220 <low_level_output+0x138>)
|
|
800d1fa: 681a ldr r2, [r3, #0]
|
|
800d1fc: f241 0314 movw r3, #4116 ; 0x1014
|
|
800d200: 4413 add r3, r2
|
|
800d202: 2220 movs r2, #32
|
|
800d204: 601a str r2, [r3, #0]
|
|
|
|
/* Resume DMA transmission*/
|
|
heth.Instance->DMATPDR = 0;
|
|
800d206: 4b06 ldr r3, [pc, #24] ; (800d220 <low_level_output+0x138>)
|
|
800d208: 681a ldr r2, [r3, #0]
|
|
800d20a: f241 0304 movw r3, #4100 ; 0x1004
|
|
800d20e: 4413 add r3, r2
|
|
800d210: 2200 movs r2, #0
|
|
800d212: 601a str r2, [r3, #0]
|
|
}
|
|
return errval;
|
|
800d214: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
800d218: 4618 mov r0, r3
|
|
800d21a: 3728 adds r7, #40 ; 0x28
|
|
800d21c: 46bd mov sp, r7
|
|
800d21e: bd80 pop {r7, pc}
|
|
800d220: 2000a8ac .word 0x2000a8ac
|
|
|
|
0800d224 <low_level_input>:
|
|
* @param netif the lwip network interface structure for this ethernetif
|
|
* @return a pbuf filled with the received packet (including MAC header)
|
|
* NULL on memory error
|
|
*/
|
|
static struct pbuf * low_level_input(struct netif *netif)
|
|
{
|
|
800d224: b580 push {r7, lr}
|
|
800d226: b08c sub sp, #48 ; 0x30
|
|
800d228: af00 add r7, sp, #0
|
|
800d22a: 6078 str r0, [r7, #4]
|
|
struct pbuf *p = NULL;
|
|
800d22c: 2300 movs r3, #0
|
|
800d22e: 62fb str r3, [r7, #44] ; 0x2c
|
|
struct pbuf *q = NULL;
|
|
800d230: 2300 movs r3, #0
|
|
800d232: 62bb str r3, [r7, #40] ; 0x28
|
|
uint16_t len = 0;
|
|
800d234: 2300 movs r3, #0
|
|
800d236: 81fb strh r3, [r7, #14]
|
|
uint8_t *buffer;
|
|
__IO ETH_DMADescTypeDef *dmarxdesc;
|
|
uint32_t bufferoffset = 0;
|
|
800d238: 2300 movs r3, #0
|
|
800d23a: 61fb str r3, [r7, #28]
|
|
uint32_t payloadoffset = 0;
|
|
800d23c: 2300 movs r3, #0
|
|
800d23e: 61bb str r3, [r7, #24]
|
|
uint32_t byteslefttocopy = 0;
|
|
800d240: 2300 movs r3, #0
|
|
800d242: 617b str r3, [r7, #20]
|
|
uint32_t i=0;
|
|
800d244: 2300 movs r3, #0
|
|
800d246: 613b str r3, [r7, #16]
|
|
|
|
/* get received frame */
|
|
if (HAL_ETH_GetReceivedFrame_IT(&heth) != HAL_OK)
|
|
800d248: 484f ldr r0, [pc, #316] ; (800d388 <low_level_input+0x164>)
|
|
800d24a: f7f9 fe8f bl 8006f6c <HAL_ETH_GetReceivedFrame_IT>
|
|
800d24e: 4603 mov r3, r0
|
|
800d250: 2b00 cmp r3, #0
|
|
800d252: d001 beq.n 800d258 <low_level_input+0x34>
|
|
|
|
return NULL;
|
|
800d254: 2300 movs r3, #0
|
|
800d256: e092 b.n 800d37e <low_level_input+0x15a>
|
|
|
|
/* Obtain the size of the packet and put it into the "len" variable. */
|
|
len = heth.RxFrameInfos.length;
|
|
800d258: 4b4b ldr r3, [pc, #300] ; (800d388 <low_level_input+0x164>)
|
|
800d25a: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800d25c: 81fb strh r3, [r7, #14]
|
|
buffer = (uint8_t *)heth.RxFrameInfos.buffer;
|
|
800d25e: 4b4a ldr r3, [pc, #296] ; (800d388 <low_level_input+0x164>)
|
|
800d260: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800d262: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
if (len > 0)
|
|
800d264: 89fb ldrh r3, [r7, #14]
|
|
800d266: 2b00 cmp r3, #0
|
|
800d268: d007 beq.n 800d27a <low_level_input+0x56>
|
|
{
|
|
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
|
|
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
|
800d26a: 89fb ldrh r3, [r7, #14]
|
|
800d26c: f44f 72c1 mov.w r2, #386 ; 0x182
|
|
800d270: 4619 mov r1, r3
|
|
800d272: 2000 movs r0, #0
|
|
800d274: f004 fd10 bl 8011c98 <pbuf_alloc>
|
|
800d278: 62f8 str r0, [r7, #44] ; 0x2c
|
|
}
|
|
|
|
if (p != NULL)
|
|
800d27a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800d27c: 2b00 cmp r3, #0
|
|
800d27e: d04b beq.n 800d318 <low_level_input+0xf4>
|
|
{
|
|
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
|
|
800d280: 4b41 ldr r3, [pc, #260] ; (800d388 <low_level_input+0x164>)
|
|
800d282: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800d284: 623b str r3, [r7, #32]
|
|
bufferoffset = 0;
|
|
800d286: 2300 movs r3, #0
|
|
800d288: 61fb str r3, [r7, #28]
|
|
for(q = p; q != NULL; q = q->next)
|
|
800d28a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800d28c: 62bb str r3, [r7, #40] ; 0x28
|
|
800d28e: e040 b.n 800d312 <low_level_input+0xee>
|
|
{
|
|
byteslefttocopy = q->len;
|
|
800d290: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800d292: 895b ldrh r3, [r3, #10]
|
|
800d294: 617b str r3, [r7, #20]
|
|
payloadoffset = 0;
|
|
800d296: 2300 movs r3, #0
|
|
800d298: 61bb str r3, [r7, #24]
|
|
|
|
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
|
|
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
|
|
800d29a: e021 b.n 800d2e0 <low_level_input+0xbc>
|
|
{
|
|
/* Copy data to pbuf */
|
|
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
|
800d29c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800d29e: 685a ldr r2, [r3, #4]
|
|
800d2a0: 69bb ldr r3, [r7, #24]
|
|
800d2a2: 18d0 adds r0, r2, r3
|
|
800d2a4: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
800d2a6: 69fb ldr r3, [r7, #28]
|
|
800d2a8: 18d1 adds r1, r2, r3
|
|
800d2aa: 69fa ldr r2, [r7, #28]
|
|
800d2ac: f240 53f4 movw r3, #1524 ; 0x5f4
|
|
800d2b0: 1a9b subs r3, r3, r2
|
|
800d2b2: 461a mov r2, r3
|
|
800d2b4: f00f fcd3 bl 801cc5e <memcpy>
|
|
|
|
/* Point to next descriptor */
|
|
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
|
800d2b8: 6a3b ldr r3, [r7, #32]
|
|
800d2ba: 68db ldr r3, [r3, #12]
|
|
800d2bc: 623b str r3, [r7, #32]
|
|
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
|
|
800d2be: 6a3b ldr r3, [r7, #32]
|
|
800d2c0: 689b ldr r3, [r3, #8]
|
|
800d2c2: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
|
|
800d2c4: 69fa ldr r2, [r7, #28]
|
|
800d2c6: 697b ldr r3, [r7, #20]
|
|
800d2c8: 4413 add r3, r2
|
|
800d2ca: f2a3 53f4 subw r3, r3, #1524 ; 0x5f4
|
|
800d2ce: 617b str r3, [r7, #20]
|
|
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
|
|
800d2d0: 69ba ldr r2, [r7, #24]
|
|
800d2d2: 69fb ldr r3, [r7, #28]
|
|
800d2d4: 1ad3 subs r3, r2, r3
|
|
800d2d6: f203 53f4 addw r3, r3, #1524 ; 0x5f4
|
|
800d2da: 61bb str r3, [r7, #24]
|
|
bufferoffset = 0;
|
|
800d2dc: 2300 movs r3, #0
|
|
800d2de: 61fb str r3, [r7, #28]
|
|
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
|
|
800d2e0: 697a ldr r2, [r7, #20]
|
|
800d2e2: 69fb ldr r3, [r7, #28]
|
|
800d2e4: 4413 add r3, r2
|
|
800d2e6: f240 52f4 movw r2, #1524 ; 0x5f4
|
|
800d2ea: 4293 cmp r3, r2
|
|
800d2ec: d8d6 bhi.n 800d29c <low_level_input+0x78>
|
|
}
|
|
/* Copy remaining data in pbuf */
|
|
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
|
|
800d2ee: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800d2f0: 685a ldr r2, [r3, #4]
|
|
800d2f2: 69bb ldr r3, [r7, #24]
|
|
800d2f4: 18d0 adds r0, r2, r3
|
|
800d2f6: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
800d2f8: 69fb ldr r3, [r7, #28]
|
|
800d2fa: 4413 add r3, r2
|
|
800d2fc: 697a ldr r2, [r7, #20]
|
|
800d2fe: 4619 mov r1, r3
|
|
800d300: f00f fcad bl 801cc5e <memcpy>
|
|
bufferoffset = bufferoffset + byteslefttocopy;
|
|
800d304: 69fa ldr r2, [r7, #28]
|
|
800d306: 697b ldr r3, [r7, #20]
|
|
800d308: 4413 add r3, r2
|
|
800d30a: 61fb str r3, [r7, #28]
|
|
for(q = p; q != NULL; q = q->next)
|
|
800d30c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800d30e: 681b ldr r3, [r3, #0]
|
|
800d310: 62bb str r3, [r7, #40] ; 0x28
|
|
800d312: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800d314: 2b00 cmp r3, #0
|
|
800d316: d1bb bne.n 800d290 <low_level_input+0x6c>
|
|
}
|
|
}
|
|
|
|
/* Release descriptors to DMA */
|
|
/* Point to first descriptor */
|
|
dmarxdesc = heth.RxFrameInfos.FSRxDesc;
|
|
800d318: 4b1b ldr r3, [pc, #108] ; (800d388 <low_level_input+0x164>)
|
|
800d31a: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800d31c: 623b str r3, [r7, #32]
|
|
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
|
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
|
|
800d31e: 2300 movs r3, #0
|
|
800d320: 613b str r3, [r7, #16]
|
|
800d322: e00b b.n 800d33c <low_level_input+0x118>
|
|
{
|
|
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
|
|
800d324: 6a3b ldr r3, [r7, #32]
|
|
800d326: 681b ldr r3, [r3, #0]
|
|
800d328: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000
|
|
800d32c: 6a3b ldr r3, [r7, #32]
|
|
800d32e: 601a str r2, [r3, #0]
|
|
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
|
800d330: 6a3b ldr r3, [r7, #32]
|
|
800d332: 68db ldr r3, [r3, #12]
|
|
800d334: 623b str r3, [r7, #32]
|
|
for (i=0; i< heth.RxFrameInfos.SegCount; i++)
|
|
800d336: 693b ldr r3, [r7, #16]
|
|
800d338: 3301 adds r3, #1
|
|
800d33a: 613b str r3, [r7, #16]
|
|
800d33c: 4b12 ldr r3, [pc, #72] ; (800d388 <low_level_input+0x164>)
|
|
800d33e: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800d340: 693a ldr r2, [r7, #16]
|
|
800d342: 429a cmp r2, r3
|
|
800d344: d3ee bcc.n 800d324 <low_level_input+0x100>
|
|
}
|
|
|
|
/* Clear Segment_Count */
|
|
heth.RxFrameInfos.SegCount =0;
|
|
800d346: 4b10 ldr r3, [pc, #64] ; (800d388 <low_level_input+0x164>)
|
|
800d348: 2200 movs r2, #0
|
|
800d34a: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
|
if ((heth.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
|
|
800d34c: 4b0e ldr r3, [pc, #56] ; (800d388 <low_level_input+0x164>)
|
|
800d34e: 681a ldr r2, [r3, #0]
|
|
800d350: f241 0314 movw r3, #4116 ; 0x1014
|
|
800d354: 4413 add r3, r2
|
|
800d356: 681b ldr r3, [r3, #0]
|
|
800d358: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
800d35c: 2b00 cmp r3, #0
|
|
800d35e: d00d beq.n 800d37c <low_level_input+0x158>
|
|
{
|
|
/* Clear RBUS ETHERNET DMA flag */
|
|
heth.Instance->DMASR = ETH_DMASR_RBUS;
|
|
800d360: 4b09 ldr r3, [pc, #36] ; (800d388 <low_level_input+0x164>)
|
|
800d362: 681a ldr r2, [r3, #0]
|
|
800d364: f241 0314 movw r3, #4116 ; 0x1014
|
|
800d368: 4413 add r3, r2
|
|
800d36a: 2280 movs r2, #128 ; 0x80
|
|
800d36c: 601a str r2, [r3, #0]
|
|
/* Resume DMA reception */
|
|
heth.Instance->DMARPDR = 0;
|
|
800d36e: 4b06 ldr r3, [pc, #24] ; (800d388 <low_level_input+0x164>)
|
|
800d370: 681a ldr r2, [r3, #0]
|
|
800d372: f241 0308 movw r3, #4104 ; 0x1008
|
|
800d376: 4413 add r3, r2
|
|
800d378: 2200 movs r2, #0
|
|
800d37a: 601a str r2, [r3, #0]
|
|
}
|
|
return p;
|
|
800d37c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
}
|
|
800d37e: 4618 mov r0, r3
|
|
800d380: 3730 adds r7, #48 ; 0x30
|
|
800d382: 46bd mov sp, r7
|
|
800d384: bd80 pop {r7, pc}
|
|
800d386: bf00 nop
|
|
800d388: 2000a8ac .word 0x2000a8ac
|
|
|
|
0800d38c <ethernetif_input>:
|
|
* the appropriate input function is called.
|
|
*
|
|
* @param netif the lwip network interface structure for this ethernetif
|
|
*/
|
|
void ethernetif_input(void const * argument)
|
|
{
|
|
800d38c: b580 push {r7, lr}
|
|
800d38e: b084 sub sp, #16
|
|
800d390: af00 add r7, sp, #0
|
|
800d392: 6078 str r0, [r7, #4]
|
|
struct pbuf *p;
|
|
struct netif *netif = (struct netif *) argument;
|
|
800d394: 687b ldr r3, [r7, #4]
|
|
800d396: 60fb str r3, [r7, #12]
|
|
|
|
for( ;; )
|
|
{
|
|
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
|
|
800d398: 4b12 ldr r3, [pc, #72] ; (800d3e4 <ethernetif_input+0x58>)
|
|
800d39a: 681b ldr r3, [r3, #0]
|
|
800d39c: f04f 31ff mov.w r1, #4294967295
|
|
800d3a0: 4618 mov r0, r3
|
|
800d3a2: f000 fa99 bl 800d8d8 <osSemaphoreWait>
|
|
800d3a6: 4603 mov r3, r0
|
|
800d3a8: 2b00 cmp r3, #0
|
|
800d3aa: d1f5 bne.n 800d398 <ethernetif_input+0xc>
|
|
{
|
|
do
|
|
{
|
|
LOCK_TCPIP_CORE();
|
|
800d3ac: 480e ldr r0, [pc, #56] ; (800d3e8 <ethernetif_input+0x5c>)
|
|
800d3ae: f00f fbc3 bl 801cb38 <sys_mutex_lock>
|
|
p = low_level_input( netif );
|
|
800d3b2: 68f8 ldr r0, [r7, #12]
|
|
800d3b4: f7ff ff36 bl 800d224 <low_level_input>
|
|
800d3b8: 60b8 str r0, [r7, #8]
|
|
if (p != NULL)
|
|
800d3ba: 68bb ldr r3, [r7, #8]
|
|
800d3bc: 2b00 cmp r3, #0
|
|
800d3be: d00a beq.n 800d3d6 <ethernetif_input+0x4a>
|
|
{
|
|
if (netif->input( p, netif) != ERR_OK )
|
|
800d3c0: 68fb ldr r3, [r7, #12]
|
|
800d3c2: 691b ldr r3, [r3, #16]
|
|
800d3c4: 68f9 ldr r1, [r7, #12]
|
|
800d3c6: 68b8 ldr r0, [r7, #8]
|
|
800d3c8: 4798 blx r3
|
|
800d3ca: 4603 mov r3, r0
|
|
800d3cc: 2b00 cmp r3, #0
|
|
800d3ce: d002 beq.n 800d3d6 <ethernetif_input+0x4a>
|
|
{
|
|
pbuf_free(p);
|
|
800d3d0: 68b8 ldr r0, [r7, #8]
|
|
800d3d2: f004 ff41 bl 8012258 <pbuf_free>
|
|
}
|
|
}
|
|
UNLOCK_TCPIP_CORE();
|
|
800d3d6: 4804 ldr r0, [pc, #16] ; (800d3e8 <ethernetif_input+0x5c>)
|
|
800d3d8: f00f fbbd bl 801cb56 <sys_mutex_unlock>
|
|
} while(p!=NULL);
|
|
800d3dc: 68bb ldr r3, [r7, #8]
|
|
800d3de: 2b00 cmp r3, #0
|
|
800d3e0: d1e4 bne.n 800d3ac <ethernetif_input+0x20>
|
|
if (osSemaphoreWait(s_xSemaphore, TIME_WAITING_FOR_INPUT) == osOK)
|
|
800d3e2: e7d9 b.n 800d398 <ethernetif_input+0xc>
|
|
800d3e4: 20000588 .word 0x20000588
|
|
800d3e8: 2000c0c4 .word 0x2000c0c4
|
|
|
|
0800d3ec <ethernetif_init>:
|
|
* @return ERR_OK if the loopif is initialized
|
|
* ERR_MEM if private data couldn't be allocated
|
|
* any other err_t on error
|
|
*/
|
|
err_t ethernetif_init(struct netif *netif)
|
|
{
|
|
800d3ec: b580 push {r7, lr}
|
|
800d3ee: b082 sub sp, #8
|
|
800d3f0: af00 add r7, sp, #0
|
|
800d3f2: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
|
800d3f4: 687b ldr r3, [r7, #4]
|
|
800d3f6: 2b00 cmp r3, #0
|
|
800d3f8: d106 bne.n 800d408 <ethernetif_init+0x1c>
|
|
800d3fa: 4b0e ldr r3, [pc, #56] ; (800d434 <ethernetif_init+0x48>)
|
|
800d3fc: f240 222b movw r2, #555 ; 0x22b
|
|
800d400: 490d ldr r1, [pc, #52] ; (800d438 <ethernetif_init+0x4c>)
|
|
800d402: 480e ldr r0, [pc, #56] ; (800d43c <ethernetif_init+0x50>)
|
|
800d404: f00f fc58 bl 801ccb8 <iprintf>
|
|
#if LWIP_NETIF_HOSTNAME
|
|
/* Initialize interface hostname */
|
|
netif->hostname = "lwip";
|
|
#endif /* LWIP_NETIF_HOSTNAME */
|
|
|
|
netif->name[0] = IFNAME0;
|
|
800d408: 687b ldr r3, [r7, #4]
|
|
800d40a: 2273 movs r2, #115 ; 0x73
|
|
800d40c: f883 2032 strb.w r2, [r3, #50] ; 0x32
|
|
netif->name[1] = IFNAME1;
|
|
800d410: 687b ldr r3, [r7, #4]
|
|
800d412: 2274 movs r2, #116 ; 0x74
|
|
800d414: f883 2033 strb.w r2, [r3, #51] ; 0x33
|
|
* is available...) */
|
|
|
|
#if LWIP_IPV4
|
|
#if LWIP_ARP || LWIP_ETHERNET
|
|
#if LWIP_ARP
|
|
netif->output = etharp_output;
|
|
800d418: 687b ldr r3, [r7, #4]
|
|
800d41a: 4a09 ldr r2, [pc, #36] ; (800d440 <ethernetif_init+0x54>)
|
|
800d41c: 615a str r2, [r3, #20]
|
|
|
|
#if LWIP_IPV6
|
|
netif->output_ip6 = ethip6_output;
|
|
#endif /* LWIP_IPV6 */
|
|
|
|
netif->linkoutput = low_level_output;
|
|
800d41e: 687b ldr r3, [r7, #4]
|
|
800d420: 4a08 ldr r2, [pc, #32] ; (800d444 <ethernetif_init+0x58>)
|
|
800d422: 619a str r2, [r3, #24]
|
|
|
|
/* initialize the hardware */
|
|
low_level_init(netif);
|
|
800d424: 6878 ldr r0, [r7, #4]
|
|
800d426: f7ff fd87 bl 800cf38 <low_level_init>
|
|
|
|
return ERR_OK;
|
|
800d42a: 2300 movs r3, #0
|
|
}
|
|
800d42c: 4618 mov r0, r3
|
|
800d42e: 3708 adds r7, #8
|
|
800d430: 46bd mov sp, r7
|
|
800d432: bd80 pop {r7, pc}
|
|
800d434: 0801df78 .word 0x0801df78
|
|
800d438: 0801df94 .word 0x0801df94
|
|
800d43c: 0801dfa4 .word 0x0801dfa4
|
|
800d440: 0801acb5 .word 0x0801acb5
|
|
800d444: 0800d0e9 .word 0x0800d0e9
|
|
|
|
0800d448 <sys_now>:
|
|
* when LWIP_TIMERS == 1 and NO_SYS == 1
|
|
* @param None
|
|
* @retval Time
|
|
*/
|
|
u32_t sys_now(void)
|
|
{
|
|
800d448: b580 push {r7, lr}
|
|
800d44a: af00 add r7, sp, #0
|
|
return HAL_GetTick();
|
|
800d44c: f7f7 ff48 bl 80052e0 <HAL_GetTick>
|
|
800d450: 4603 mov r3, r0
|
|
}
|
|
800d452: 4618 mov r0, r3
|
|
800d454: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800d458 <ethernetif_set_link>:
|
|
* @param netif: the network interface
|
|
* @retval None
|
|
*/
|
|
void ethernetif_set_link(void const *argument)
|
|
|
|
{
|
|
800d458: b580 push {r7, lr}
|
|
800d45a: b084 sub sp, #16
|
|
800d45c: af00 add r7, sp, #0
|
|
800d45e: 6078 str r0, [r7, #4]
|
|
uint32_t regvalue = 0;
|
|
800d460: 2300 movs r3, #0
|
|
800d462: 60bb str r3, [r7, #8]
|
|
struct link_str *link_arg = (struct link_str *)argument;
|
|
800d464: 687b ldr r3, [r7, #4]
|
|
800d466: 60fb str r3, [r7, #12]
|
|
|
|
for(;;)
|
|
{
|
|
/* Read PHY_BSR*/
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, ®value);
|
|
800d468: f107 0308 add.w r3, r7, #8
|
|
800d46c: 461a mov r2, r3
|
|
800d46e: 2101 movs r1, #1
|
|
800d470: 4816 ldr r0, [pc, #88] ; (800d4cc <ethernetif_set_link+0x74>)
|
|
800d472: f7f9 fe7e bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
|
|
regvalue &= PHY_LINKED_STATUS;
|
|
800d476: 68bb ldr r3, [r7, #8]
|
|
800d478: f003 0304 and.w r3, r3, #4
|
|
800d47c: 60bb str r3, [r7, #8]
|
|
|
|
/* Check whether the netif link down and the PHY link is up */
|
|
if(!netif_is_link_up(link_arg->netif) && (regvalue))
|
|
800d47e: 68fb ldr r3, [r7, #12]
|
|
800d480: 681b ldr r3, [r3, #0]
|
|
800d482: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800d486: f003 0304 and.w r3, r3, #4
|
|
800d48a: 2b00 cmp r3, #0
|
|
800d48c: d108 bne.n 800d4a0 <ethernetif_set_link+0x48>
|
|
800d48e: 68bb ldr r3, [r7, #8]
|
|
800d490: 2b00 cmp r3, #0
|
|
800d492: d005 beq.n 800d4a0 <ethernetif_set_link+0x48>
|
|
{
|
|
/* network cable is connected */
|
|
netif_set_link_up(link_arg->netif);
|
|
800d494: 68fb ldr r3, [r7, #12]
|
|
800d496: 681b ldr r3, [r3, #0]
|
|
800d498: 4618 mov r0, r3
|
|
800d49a: f004 facb bl 8011a34 <netif_set_link_up>
|
|
800d49e: e011 b.n 800d4c4 <ethernetif_set_link+0x6c>
|
|
}
|
|
else if(netif_is_link_up(link_arg->netif) && (!regvalue))
|
|
800d4a0: 68fb ldr r3, [r7, #12]
|
|
800d4a2: 681b ldr r3, [r3, #0]
|
|
800d4a4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800d4a8: 089b lsrs r3, r3, #2
|
|
800d4aa: f003 0301 and.w r3, r3, #1
|
|
800d4ae: b2db uxtb r3, r3
|
|
800d4b0: 2b00 cmp r3, #0
|
|
800d4b2: d007 beq.n 800d4c4 <ethernetif_set_link+0x6c>
|
|
800d4b4: 68bb ldr r3, [r7, #8]
|
|
800d4b6: 2b00 cmp r3, #0
|
|
800d4b8: d104 bne.n 800d4c4 <ethernetif_set_link+0x6c>
|
|
{
|
|
/* network cable is dis-connected */
|
|
netif_set_link_down(link_arg->netif);
|
|
800d4ba: 68fb ldr r3, [r7, #12]
|
|
800d4bc: 681b ldr r3, [r3, #0]
|
|
800d4be: 4618 mov r0, r3
|
|
800d4c0: f004 faf0 bl 8011aa4 <netif_set_link_down>
|
|
}
|
|
|
|
/* Suspend thread for 200 ms */
|
|
osDelay(200);
|
|
800d4c4: 20c8 movs r0, #200 ; 0xc8
|
|
800d4c6: f000 f916 bl 800d6f6 <osDelay>
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, ®value);
|
|
800d4ca: e7cd b.n 800d468 <ethernetif_set_link+0x10>
|
|
800d4cc: 2000a8ac .word 0x2000a8ac
|
|
|
|
0800d4d0 <ethernetif_update_config>:
|
|
* to update low level driver configuration.
|
|
* @param netif: The network interface
|
|
* @retval None
|
|
*/
|
|
void ethernetif_update_config(struct netif *netif)
|
|
{
|
|
800d4d0: b580 push {r7, lr}
|
|
800d4d2: b084 sub sp, #16
|
|
800d4d4: af00 add r7, sp, #0
|
|
800d4d6: 6078 str r0, [r7, #4]
|
|
__IO uint32_t tickstart = 0;
|
|
800d4d8: 2300 movs r3, #0
|
|
800d4da: 60fb str r3, [r7, #12]
|
|
uint32_t regvalue = 0;
|
|
800d4dc: 2300 movs r3, #0
|
|
800d4de: 60bb str r3, [r7, #8]
|
|
|
|
if(netif_is_link_up(netif))
|
|
800d4e0: 687b ldr r3, [r7, #4]
|
|
800d4e2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
800d4e6: 089b lsrs r3, r3, #2
|
|
800d4e8: f003 0301 and.w r3, r3, #1
|
|
800d4ec: b2db uxtb r3, r3
|
|
800d4ee: 2b00 cmp r3, #0
|
|
800d4f0: d05d beq.n 800d5ae <ethernetif_update_config+0xde>
|
|
{
|
|
/* Restart the auto-negotiation */
|
|
if(heth.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
|
|
800d4f2: 4b34 ldr r3, [pc, #208] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d4f4: 685b ldr r3, [r3, #4]
|
|
800d4f6: 2b00 cmp r3, #0
|
|
800d4f8: d03f beq.n 800d57a <ethernetif_update_config+0xaa>
|
|
{
|
|
/* Enable Auto-Negotiation */
|
|
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, PHY_AUTONEGOTIATION);
|
|
800d4fa: f44f 5280 mov.w r2, #4096 ; 0x1000
|
|
800d4fe: 2100 movs r1, #0
|
|
800d500: 4830 ldr r0, [pc, #192] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d502: f7f9 fe9e bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800d506: f7f7 feeb bl 80052e0 <HAL_GetTick>
|
|
800d50a: 4603 mov r3, r0
|
|
800d50c: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait until the auto-negotiation will be completed */
|
|
do
|
|
{
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_BSR, ®value);
|
|
800d50e: f107 0308 add.w r3, r7, #8
|
|
800d512: 461a mov r2, r3
|
|
800d514: 2101 movs r1, #1
|
|
800d516: 482b ldr r0, [pc, #172] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d518: f7f9 fe2b bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
|
|
/* Check for the Timeout ( 1s ) */
|
|
if((HAL_GetTick() - tickstart ) > 1000)
|
|
800d51c: f7f7 fee0 bl 80052e0 <HAL_GetTick>
|
|
800d520: 4602 mov r2, r0
|
|
800d522: 68fb ldr r3, [r7, #12]
|
|
800d524: 1ad3 subs r3, r2, r3
|
|
800d526: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
|
|
800d52a: d828 bhi.n 800d57e <ethernetif_update_config+0xae>
|
|
{
|
|
/* In case of timeout */
|
|
goto error;
|
|
}
|
|
} while (((regvalue & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
|
|
800d52c: 68bb ldr r3, [r7, #8]
|
|
800d52e: f003 0320 and.w r3, r3, #32
|
|
800d532: 2b00 cmp r3, #0
|
|
800d534: d0eb beq.n 800d50e <ethernetif_update_config+0x3e>
|
|
|
|
/* Read the result of the auto-negotiation */
|
|
HAL_ETH_ReadPHYRegister(&heth, PHY_SR, ®value);
|
|
800d536: f107 0308 add.w r3, r7, #8
|
|
800d53a: 461a mov r2, r3
|
|
800d53c: 211f movs r1, #31
|
|
800d53e: 4821 ldr r0, [pc, #132] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d540: f7f9 fe17 bl 8007172 <HAL_ETH_ReadPHYRegister>
|
|
|
|
/* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
|
|
if((regvalue & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
|
|
800d544: 68bb ldr r3, [r7, #8]
|
|
800d546: f003 0310 and.w r3, r3, #16
|
|
800d54a: 2b00 cmp r3, #0
|
|
800d54c: d004 beq.n 800d558 <ethernetif_update_config+0x88>
|
|
{
|
|
/* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
|
|
heth.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
|
800d54e: 4b1d ldr r3, [pc, #116] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d550: f44f 6200 mov.w r2, #2048 ; 0x800
|
|
800d554: 60da str r2, [r3, #12]
|
|
800d556: e002 b.n 800d55e <ethernetif_update_config+0x8e>
|
|
}
|
|
else
|
|
{
|
|
/* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
|
|
heth.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
|
|
800d558: 4b1a ldr r3, [pc, #104] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d55a: 2200 movs r2, #0
|
|
800d55c: 60da str r2, [r3, #12]
|
|
}
|
|
/* Configure the MAC with the speed fixed by the auto-negotiation process */
|
|
if(regvalue & PHY_SPEED_STATUS)
|
|
800d55e: 68bb ldr r3, [r7, #8]
|
|
800d560: f003 0304 and.w r3, r3, #4
|
|
800d564: 2b00 cmp r3, #0
|
|
800d566: d003 beq.n 800d570 <ethernetif_update_config+0xa0>
|
|
{
|
|
/* Set Ethernet speed to 10M following the auto-negotiation */
|
|
heth.Init.Speed = ETH_SPEED_10M;
|
|
800d568: 4b16 ldr r3, [pc, #88] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d56a: 2200 movs r2, #0
|
|
800d56c: 609a str r2, [r3, #8]
|
|
800d56e: e016 b.n 800d59e <ethernetif_update_config+0xce>
|
|
}
|
|
else
|
|
{
|
|
/* Set Ethernet speed to 100M following the auto-negotiation */
|
|
heth.Init.Speed = ETH_SPEED_100M;
|
|
800d570: 4b14 ldr r3, [pc, #80] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d572: f44f 4280 mov.w r2, #16384 ; 0x4000
|
|
800d576: 609a str r2, [r3, #8]
|
|
800d578: e011 b.n 800d59e <ethernetif_update_config+0xce>
|
|
}
|
|
}
|
|
else /* AutoNegotiation Disable */
|
|
{
|
|
error :
|
|
800d57a: bf00 nop
|
|
800d57c: e000 b.n 800d580 <ethernetif_update_config+0xb0>
|
|
goto error;
|
|
800d57e: bf00 nop
|
|
/* Check parameters */
|
|
assert_param(IS_ETH_SPEED(heth.Init.Speed));
|
|
assert_param(IS_ETH_DUPLEX_MODE(heth.Init.DuplexMode));
|
|
|
|
/* Set MAC Speed and Duplex Mode to PHY */
|
|
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
|
|
800d580: 4b10 ldr r3, [pc, #64] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d582: 68db ldr r3, [r3, #12]
|
|
800d584: 08db lsrs r3, r3, #3
|
|
800d586: b29a uxth r2, r3
|
|
(uint16_t)(heth.Init.Speed >> 1)));
|
|
800d588: 4b0e ldr r3, [pc, #56] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d58a: 689b ldr r3, [r3, #8]
|
|
800d58c: 085b lsrs r3, r3, #1
|
|
800d58e: b29b uxth r3, r3
|
|
HAL_ETH_WritePHYRegister(&heth, PHY_BCR, ((uint16_t)(heth.Init.DuplexMode >> 3) |
|
|
800d590: 4313 orrs r3, r2
|
|
800d592: b29b uxth r3, r3
|
|
800d594: 461a mov r2, r3
|
|
800d596: 2100 movs r1, #0
|
|
800d598: 480a ldr r0, [pc, #40] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d59a: f7f9 fe52 bl 8007242 <HAL_ETH_WritePHYRegister>
|
|
}
|
|
|
|
/* ETHERNET MAC Re-Configuration */
|
|
HAL_ETH_ConfigMAC(&heth, (ETH_MACInitTypeDef *) NULL);
|
|
800d59e: 2100 movs r1, #0
|
|
800d5a0: 4808 ldr r0, [pc, #32] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d5a2: f7f9 ff13 bl 80073cc <HAL_ETH_ConfigMAC>
|
|
|
|
/* Restart MAC interface */
|
|
HAL_ETH_Start(&heth);
|
|
800d5a6: 4807 ldr r0, [pc, #28] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d5a8: f7f9 feb1 bl 800730e <HAL_ETH_Start>
|
|
800d5ac: e002 b.n 800d5b4 <ethernetif_update_config+0xe4>
|
|
}
|
|
else
|
|
{
|
|
/* Stop MAC interface */
|
|
HAL_ETH_Stop(&heth);
|
|
800d5ae: 4805 ldr r0, [pc, #20] ; (800d5c4 <ethernetif_update_config+0xf4>)
|
|
800d5b0: f7f9 fedc bl 800736c <HAL_ETH_Stop>
|
|
}
|
|
|
|
ethernetif_notify_conn_changed(netif);
|
|
800d5b4: 6878 ldr r0, [r7, #4]
|
|
800d5b6: f000 f807 bl 800d5c8 <ethernetif_notify_conn_changed>
|
|
}
|
|
800d5ba: bf00 nop
|
|
800d5bc: 3710 adds r7, #16
|
|
800d5be: 46bd mov sp, r7
|
|
800d5c0: bd80 pop {r7, pc}
|
|
800d5c2: bf00 nop
|
|
800d5c4: 2000a8ac .word 0x2000a8ac
|
|
|
|
0800d5c8 <ethernetif_notify_conn_changed>:
|
|
* @brief This function notify user about link status changement.
|
|
* @param netif: the network interface
|
|
* @retval None
|
|
*/
|
|
__weak void ethernetif_notify_conn_changed(struct netif *netif)
|
|
{
|
|
800d5c8: b480 push {r7}
|
|
800d5ca: b083 sub sp, #12
|
|
800d5cc: af00 add r7, sp, #0
|
|
800d5ce: 6078 str r0, [r7, #4]
|
|
/* NOTE : This is function could be implemented in user file
|
|
when the callback is needed,
|
|
*/
|
|
|
|
}
|
|
800d5d0: bf00 nop
|
|
800d5d2: 370c adds r7, #12
|
|
800d5d4: 46bd mov sp, r7
|
|
800d5d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d5da: 4770 bx lr
|
|
|
|
0800d5dc <makeFreeRtosPriority>:
|
|
|
|
extern void xPortSysTickHandler(void);
|
|
|
|
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
|
|
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
|
|
{
|
|
800d5dc: b480 push {r7}
|
|
800d5de: b085 sub sp, #20
|
|
800d5e0: af00 add r7, sp, #0
|
|
800d5e2: 4603 mov r3, r0
|
|
800d5e4: 80fb strh r3, [r7, #6]
|
|
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
|
|
800d5e6: 2300 movs r3, #0
|
|
800d5e8: 60fb str r3, [r7, #12]
|
|
|
|
if (priority != osPriorityError) {
|
|
800d5ea: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800d5ee: 2b84 cmp r3, #132 ; 0x84
|
|
800d5f0: d005 beq.n 800d5fe <makeFreeRtosPriority+0x22>
|
|
fpriority += (priority - osPriorityIdle);
|
|
800d5f2: f9b7 2006 ldrsh.w r2, [r7, #6]
|
|
800d5f6: 68fb ldr r3, [r7, #12]
|
|
800d5f8: 4413 add r3, r2
|
|
800d5fa: 3303 adds r3, #3
|
|
800d5fc: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return fpriority;
|
|
800d5fe: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d600: 4618 mov r0, r3
|
|
800d602: 3714 adds r7, #20
|
|
800d604: 46bd mov sp, r7
|
|
800d606: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d60a: 4770 bx lr
|
|
|
|
0800d60c <inHandlerMode>:
|
|
#endif
|
|
|
|
|
|
/* Determine whether we are in thread mode or handler mode. */
|
|
static int inHandlerMode (void)
|
|
{
|
|
800d60c: b480 push {r7}
|
|
800d60e: b083 sub sp, #12
|
|
800d610: af00 add r7, sp, #0
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
800d612: f3ef 8305 mrs r3, IPSR
|
|
800d616: 607b str r3, [r7, #4]
|
|
return(result);
|
|
800d618: 687b ldr r3, [r7, #4]
|
|
return __get_IPSR() != 0;
|
|
800d61a: 2b00 cmp r3, #0
|
|
800d61c: bf14 ite ne
|
|
800d61e: 2301 movne r3, #1
|
|
800d620: 2300 moveq r3, #0
|
|
800d622: b2db uxtb r3, r3
|
|
}
|
|
800d624: 4618 mov r0, r3
|
|
800d626: 370c adds r7, #12
|
|
800d628: 46bd mov sp, r7
|
|
800d62a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800d62e: 4770 bx lr
|
|
|
|
0800d630 <osKernelStart>:
|
|
* @param argument pointer that is passed to the thread function as start argument.
|
|
* @retval status code that indicates the execution status of the function
|
|
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osKernelStart (void)
|
|
{
|
|
800d630: b580 push {r7, lr}
|
|
800d632: af00 add r7, sp, #0
|
|
vTaskStartScheduler();
|
|
800d634: f001 fe1e bl 800f274 <vTaskStartScheduler>
|
|
|
|
return osOK;
|
|
800d638: 2300 movs r3, #0
|
|
}
|
|
800d63a: 4618 mov r0, r3
|
|
800d63c: bd80 pop {r7, pc}
|
|
|
|
0800d63e <osKernelSysTick>:
|
|
* @param None
|
|
* @retval None
|
|
* @note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
uint32_t osKernelSysTick(void)
|
|
{
|
|
800d63e: b580 push {r7, lr}
|
|
800d640: af00 add r7, sp, #0
|
|
if (inHandlerMode()) {
|
|
800d642: f7ff ffe3 bl 800d60c <inHandlerMode>
|
|
800d646: 4603 mov r3, r0
|
|
800d648: 2b00 cmp r3, #0
|
|
800d64a: d003 beq.n 800d654 <osKernelSysTick+0x16>
|
|
return xTaskGetTickCountFromISR();
|
|
800d64c: f001 ff30 bl 800f4b0 <xTaskGetTickCountFromISR>
|
|
800d650: 4603 mov r3, r0
|
|
800d652: e002 b.n 800d65a <osKernelSysTick+0x1c>
|
|
}
|
|
else {
|
|
return xTaskGetTickCount();
|
|
800d654: f001 ff1c bl 800f490 <xTaskGetTickCount>
|
|
800d658: 4603 mov r3, r0
|
|
}
|
|
}
|
|
800d65a: 4618 mov r0, r3
|
|
800d65c: bd80 pop {r7, pc}
|
|
|
|
0800d65e <osThreadCreate>:
|
|
* @param argument pointer that is passed to the thread function as start argument.
|
|
* @retval thread ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
|
|
{
|
|
800d65e: b5f0 push {r4, r5, r6, r7, lr}
|
|
800d660: b089 sub sp, #36 ; 0x24
|
|
800d662: af04 add r7, sp, #16
|
|
800d664: 6078 str r0, [r7, #4]
|
|
800d666: 6039 str r1, [r7, #0]
|
|
TaskHandle_t handle;
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
|
|
800d668: 687b ldr r3, [r7, #4]
|
|
800d66a: 695b ldr r3, [r3, #20]
|
|
800d66c: 2b00 cmp r3, #0
|
|
800d66e: d020 beq.n 800d6b2 <osThreadCreate+0x54>
|
|
800d670: 687b ldr r3, [r7, #4]
|
|
800d672: 699b ldr r3, [r3, #24]
|
|
800d674: 2b00 cmp r3, #0
|
|
800d676: d01c beq.n 800d6b2 <osThreadCreate+0x54>
|
|
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800d678: 687b ldr r3, [r7, #4]
|
|
800d67a: 685c ldr r4, [r3, #4]
|
|
800d67c: 687b ldr r3, [r7, #4]
|
|
800d67e: 681d ldr r5, [r3, #0]
|
|
800d680: 687b ldr r3, [r7, #4]
|
|
800d682: 691e ldr r6, [r3, #16]
|
|
800d684: 687b ldr r3, [r7, #4]
|
|
800d686: f9b3 3008 ldrsh.w r3, [r3, #8]
|
|
800d68a: 4618 mov r0, r3
|
|
800d68c: f7ff ffa6 bl 800d5dc <makeFreeRtosPriority>
|
|
800d690: 4601 mov r1, r0
|
|
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
|
|
thread_def->buffer, thread_def->controlblock);
|
|
800d692: 687b ldr r3, [r7, #4]
|
|
800d694: 695b ldr r3, [r3, #20]
|
|
800d696: 687a ldr r2, [r7, #4]
|
|
800d698: 6992 ldr r2, [r2, #24]
|
|
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800d69a: 9202 str r2, [sp, #8]
|
|
800d69c: 9301 str r3, [sp, #4]
|
|
800d69e: 9100 str r1, [sp, #0]
|
|
800d6a0: 683b ldr r3, [r7, #0]
|
|
800d6a2: 4632 mov r2, r6
|
|
800d6a4: 4629 mov r1, r5
|
|
800d6a6: 4620 mov r0, r4
|
|
800d6a8: f001 fafb bl 800eca2 <xTaskCreateStatic>
|
|
800d6ac: 4603 mov r3, r0
|
|
800d6ae: 60fb str r3, [r7, #12]
|
|
800d6b0: e01c b.n 800d6ec <osThreadCreate+0x8e>
|
|
}
|
|
else {
|
|
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800d6b2: 687b ldr r3, [r7, #4]
|
|
800d6b4: 685c ldr r4, [r3, #4]
|
|
800d6b6: 687b ldr r3, [r7, #4]
|
|
800d6b8: 681d ldr r5, [r3, #0]
|
|
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
|
|
800d6ba: 687b ldr r3, [r7, #4]
|
|
800d6bc: 691b ldr r3, [r3, #16]
|
|
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800d6be: b29e uxth r6, r3
|
|
800d6c0: 687b ldr r3, [r7, #4]
|
|
800d6c2: f9b3 3008 ldrsh.w r3, [r3, #8]
|
|
800d6c6: 4618 mov r0, r3
|
|
800d6c8: f7ff ff88 bl 800d5dc <makeFreeRtosPriority>
|
|
800d6cc: 4602 mov r2, r0
|
|
800d6ce: f107 030c add.w r3, r7, #12
|
|
800d6d2: 9301 str r3, [sp, #4]
|
|
800d6d4: 9200 str r2, [sp, #0]
|
|
800d6d6: 683b ldr r3, [r7, #0]
|
|
800d6d8: 4632 mov r2, r6
|
|
800d6da: 4629 mov r1, r5
|
|
800d6dc: 4620 mov r0, r4
|
|
800d6de: f001 fb40 bl 800ed62 <xTaskCreate>
|
|
800d6e2: 4603 mov r3, r0
|
|
800d6e4: 2b01 cmp r3, #1
|
|
800d6e6: d001 beq.n 800d6ec <osThreadCreate+0x8e>
|
|
&handle) != pdPASS) {
|
|
return NULL;
|
|
800d6e8: 2300 movs r3, #0
|
|
800d6ea: e000 b.n 800d6ee <osThreadCreate+0x90>
|
|
&handle) != pdPASS) {
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
return handle;
|
|
800d6ec: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d6ee: 4618 mov r0, r3
|
|
800d6f0: 3714 adds r7, #20
|
|
800d6f2: 46bd mov sp, r7
|
|
800d6f4: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
|
0800d6f6 <osDelay>:
|
|
* @brief Wait for Timeout (Time Delay)
|
|
* @param millisec time delay value
|
|
* @retval status code that indicates the execution status of the function.
|
|
*/
|
|
osStatus osDelay (uint32_t millisec)
|
|
{
|
|
800d6f6: b580 push {r7, lr}
|
|
800d6f8: b084 sub sp, #16
|
|
800d6fa: af00 add r7, sp, #0
|
|
800d6fc: 6078 str r0, [r7, #4]
|
|
#if INCLUDE_vTaskDelay
|
|
TickType_t ticks = millisec / portTICK_PERIOD_MS;
|
|
800d6fe: 687b ldr r3, [r7, #4]
|
|
800d700: 60fb str r3, [r7, #12]
|
|
|
|
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
|
|
800d702: 68fb ldr r3, [r7, #12]
|
|
800d704: 2b00 cmp r3, #0
|
|
800d706: d001 beq.n 800d70c <osDelay+0x16>
|
|
800d708: 68fb ldr r3, [r7, #12]
|
|
800d70a: e000 b.n 800d70e <osDelay+0x18>
|
|
800d70c: 2301 movs r3, #1
|
|
800d70e: 4618 mov r0, r3
|
|
800d710: f001 fd7a bl 800f208 <vTaskDelay>
|
|
|
|
return osOK;
|
|
800d714: 2300 movs r3, #0
|
|
#else
|
|
(void) millisec;
|
|
|
|
return osErrorResource;
|
|
#endif
|
|
}
|
|
800d716: 4618 mov r0, r3
|
|
800d718: 3710 adds r7, #16
|
|
800d71a: 46bd mov sp, r7
|
|
800d71c: bd80 pop {r7, pc}
|
|
|
|
0800d71e <osMutexCreate>:
|
|
* @param mutex_def mutex definition referenced with \ref osMutex.
|
|
* @retval mutex ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osMutexId osMutexCreate (const osMutexDef_t *mutex_def)
|
|
{
|
|
800d71e: b580 push {r7, lr}
|
|
800d720: b082 sub sp, #8
|
|
800d722: af00 add r7, sp, #0
|
|
800d724: 6078 str r0, [r7, #4]
|
|
#if ( configUSE_MUTEXES == 1)
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
if (mutex_def->controlblock != NULL) {
|
|
800d726: 687b ldr r3, [r7, #4]
|
|
800d728: 685b ldr r3, [r3, #4]
|
|
800d72a: 2b00 cmp r3, #0
|
|
800d72c: d007 beq.n 800d73e <osMutexCreate+0x20>
|
|
return xSemaphoreCreateMutexStatic( mutex_def->controlblock );
|
|
800d72e: 687b ldr r3, [r7, #4]
|
|
800d730: 685b ldr r3, [r3, #4]
|
|
800d732: 4619 mov r1, r3
|
|
800d734: 2001 movs r0, #1
|
|
800d736: f000 fc5e bl 800dff6 <xQueueCreateMutexStatic>
|
|
800d73a: 4603 mov r3, r0
|
|
800d73c: e003 b.n 800d746 <osMutexCreate+0x28>
|
|
}
|
|
else {
|
|
return xSemaphoreCreateMutex();
|
|
800d73e: 2001 movs r0, #1
|
|
800d740: f000 fc41 bl 800dfc6 <xQueueCreateMutex>
|
|
800d744: 4603 mov r3, r0
|
|
return xSemaphoreCreateMutex();
|
|
#endif
|
|
#else
|
|
return NULL;
|
|
#endif
|
|
}
|
|
800d746: 4618 mov r0, r3
|
|
800d748: 3708 adds r7, #8
|
|
800d74a: 46bd mov sp, r7
|
|
800d74c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800d750 <osMutexWait>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)
|
|
{
|
|
800d750: b580 push {r7, lr}
|
|
800d752: b084 sub sp, #16
|
|
800d754: af00 add r7, sp, #0
|
|
800d756: 6078 str r0, [r7, #4]
|
|
800d758: 6039 str r1, [r7, #0]
|
|
TickType_t ticks;
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800d75a: 2300 movs r3, #0
|
|
800d75c: 60bb str r3, [r7, #8]
|
|
|
|
|
|
if (mutex_id == NULL) {
|
|
800d75e: 687b ldr r3, [r7, #4]
|
|
800d760: 2b00 cmp r3, #0
|
|
800d762: d101 bne.n 800d768 <osMutexWait+0x18>
|
|
return osErrorParameter;
|
|
800d764: 2380 movs r3, #128 ; 0x80
|
|
800d766: e03a b.n 800d7de <osMutexWait+0x8e>
|
|
}
|
|
|
|
ticks = 0;
|
|
800d768: 2300 movs r3, #0
|
|
800d76a: 60fb str r3, [r7, #12]
|
|
if (millisec == osWaitForever) {
|
|
800d76c: 683b ldr r3, [r7, #0]
|
|
800d76e: f1b3 3fff cmp.w r3, #4294967295
|
|
800d772: d103 bne.n 800d77c <osMutexWait+0x2c>
|
|
ticks = portMAX_DELAY;
|
|
800d774: f04f 33ff mov.w r3, #4294967295
|
|
800d778: 60fb str r3, [r7, #12]
|
|
800d77a: e009 b.n 800d790 <osMutexWait+0x40>
|
|
}
|
|
else if (millisec != 0) {
|
|
800d77c: 683b ldr r3, [r7, #0]
|
|
800d77e: 2b00 cmp r3, #0
|
|
800d780: d006 beq.n 800d790 <osMutexWait+0x40>
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800d782: 683b ldr r3, [r7, #0]
|
|
800d784: 60fb str r3, [r7, #12]
|
|
if (ticks == 0) {
|
|
800d786: 68fb ldr r3, [r7, #12]
|
|
800d788: 2b00 cmp r3, #0
|
|
800d78a: d101 bne.n 800d790 <osMutexWait+0x40>
|
|
ticks = 1;
|
|
800d78c: 2301 movs r3, #1
|
|
800d78e: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800d790: f7ff ff3c bl 800d60c <inHandlerMode>
|
|
800d794: 4603 mov r3, r0
|
|
800d796: 2b00 cmp r3, #0
|
|
800d798: d017 beq.n 800d7ca <osMutexWait+0x7a>
|
|
if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {
|
|
800d79a: f107 0308 add.w r3, r7, #8
|
|
800d79e: 461a mov r2, r3
|
|
800d7a0: 2100 movs r1, #0
|
|
800d7a2: 6878 ldr r0, [r7, #4]
|
|
800d7a4: f001 f8d2 bl 800e94c <xQueueReceiveFromISR>
|
|
800d7a8: 4603 mov r3, r0
|
|
800d7aa: 2b01 cmp r3, #1
|
|
800d7ac: d001 beq.n 800d7b2 <osMutexWait+0x62>
|
|
return osErrorOS;
|
|
800d7ae: 23ff movs r3, #255 ; 0xff
|
|
800d7b0: e015 b.n 800d7de <osMutexWait+0x8e>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800d7b2: 68bb ldr r3, [r7, #8]
|
|
800d7b4: 2b00 cmp r3, #0
|
|
800d7b6: d011 beq.n 800d7dc <osMutexWait+0x8c>
|
|
800d7b8: 4b0b ldr r3, [pc, #44] ; (800d7e8 <osMutexWait+0x98>)
|
|
800d7ba: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800d7be: 601a str r2, [r3, #0]
|
|
800d7c0: f3bf 8f4f dsb sy
|
|
800d7c4: f3bf 8f6f isb sy
|
|
800d7c8: e008 b.n 800d7dc <osMutexWait+0x8c>
|
|
}
|
|
else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {
|
|
800d7ca: 68f9 ldr r1, [r7, #12]
|
|
800d7cc: 6878 ldr r0, [r7, #4]
|
|
800d7ce: f000 ffad bl 800e72c <xQueueSemaphoreTake>
|
|
800d7d2: 4603 mov r3, r0
|
|
800d7d4: 2b01 cmp r3, #1
|
|
800d7d6: d001 beq.n 800d7dc <osMutexWait+0x8c>
|
|
return osErrorOS;
|
|
800d7d8: 23ff movs r3, #255 ; 0xff
|
|
800d7da: e000 b.n 800d7de <osMutexWait+0x8e>
|
|
}
|
|
|
|
return osOK;
|
|
800d7dc: 2300 movs r3, #0
|
|
}
|
|
800d7de: 4618 mov r0, r3
|
|
800d7e0: 3710 adds r7, #16
|
|
800d7e2: 46bd mov sp, r7
|
|
800d7e4: bd80 pop {r7, pc}
|
|
800d7e6: bf00 nop
|
|
800d7e8: e000ed04 .word 0xe000ed04
|
|
|
|
0800d7ec <osMutexRelease>:
|
|
* @param mutex_id mutex ID obtained by \ref osMutexCreate.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osMutexRelease (osMutexId mutex_id)
|
|
{
|
|
800d7ec: b580 push {r7, lr}
|
|
800d7ee: b084 sub sp, #16
|
|
800d7f0: af00 add r7, sp, #0
|
|
800d7f2: 6078 str r0, [r7, #4]
|
|
osStatus result = osOK;
|
|
800d7f4: 2300 movs r3, #0
|
|
800d7f6: 60fb str r3, [r7, #12]
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800d7f8: 2300 movs r3, #0
|
|
800d7fa: 60bb str r3, [r7, #8]
|
|
|
|
if (inHandlerMode()) {
|
|
800d7fc: f7ff ff06 bl 800d60c <inHandlerMode>
|
|
800d800: 4603 mov r3, r0
|
|
800d802: 2b00 cmp r3, #0
|
|
800d804: d016 beq.n 800d834 <osMutexRelease+0x48>
|
|
if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {
|
|
800d806: f107 0308 add.w r3, r7, #8
|
|
800d80a: 4619 mov r1, r3
|
|
800d80c: 6878 ldr r0, [r7, #4]
|
|
800d80e: f000 fe19 bl 800e444 <xQueueGiveFromISR>
|
|
800d812: 4603 mov r3, r0
|
|
800d814: 2b01 cmp r3, #1
|
|
800d816: d001 beq.n 800d81c <osMutexRelease+0x30>
|
|
return osErrorOS;
|
|
800d818: 23ff movs r3, #255 ; 0xff
|
|
800d81a: e017 b.n 800d84c <osMutexRelease+0x60>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800d81c: 68bb ldr r3, [r7, #8]
|
|
800d81e: 2b00 cmp r3, #0
|
|
800d820: d013 beq.n 800d84a <osMutexRelease+0x5e>
|
|
800d822: 4b0c ldr r3, [pc, #48] ; (800d854 <osMutexRelease+0x68>)
|
|
800d824: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800d828: 601a str r2, [r3, #0]
|
|
800d82a: f3bf 8f4f dsb sy
|
|
800d82e: f3bf 8f6f isb sy
|
|
800d832: e00a b.n 800d84a <osMutexRelease+0x5e>
|
|
}
|
|
else if (xSemaphoreGive(mutex_id) != pdTRUE)
|
|
800d834: 2300 movs r3, #0
|
|
800d836: 2200 movs r2, #0
|
|
800d838: 2100 movs r1, #0
|
|
800d83a: 6878 ldr r0, [r7, #4]
|
|
800d83c: f000 fc64 bl 800e108 <xQueueGenericSend>
|
|
800d840: 4603 mov r3, r0
|
|
800d842: 2b01 cmp r3, #1
|
|
800d844: d001 beq.n 800d84a <osMutexRelease+0x5e>
|
|
{
|
|
result = osErrorOS;
|
|
800d846: 23ff movs r3, #255 ; 0xff
|
|
800d848: 60fb str r3, [r7, #12]
|
|
}
|
|
return result;
|
|
800d84a: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d84c: 4618 mov r0, r3
|
|
800d84e: 3710 adds r7, #16
|
|
800d850: 46bd mov sp, r7
|
|
800d852: bd80 pop {r7, pc}
|
|
800d854: e000ed04 .word 0xe000ed04
|
|
|
|
0800d858 <osSemaphoreCreate>:
|
|
* @param count number of available resources.
|
|
* @retval semaphore ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)
|
|
{
|
|
800d858: b580 push {r7, lr}
|
|
800d85a: b086 sub sp, #24
|
|
800d85c: af02 add r7, sp, #8
|
|
800d85e: 6078 str r0, [r7, #4]
|
|
800d860: 6039 str r1, [r7, #0]
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
osSemaphoreId sema;
|
|
|
|
if (semaphore_def->controlblock != NULL){
|
|
800d862: 687b ldr r3, [r7, #4]
|
|
800d864: 685b ldr r3, [r3, #4]
|
|
800d866: 2b00 cmp r3, #0
|
|
800d868: d017 beq.n 800d89a <osSemaphoreCreate+0x42>
|
|
if (count == 1) {
|
|
800d86a: 683b ldr r3, [r7, #0]
|
|
800d86c: 2b01 cmp r3, #1
|
|
800d86e: d10b bne.n 800d888 <osSemaphoreCreate+0x30>
|
|
return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );
|
|
800d870: 687b ldr r3, [r7, #4]
|
|
800d872: 685a ldr r2, [r3, #4]
|
|
800d874: 2303 movs r3, #3
|
|
800d876: 9300 str r3, [sp, #0]
|
|
800d878: 4613 mov r3, r2
|
|
800d87a: 2200 movs r2, #0
|
|
800d87c: 2100 movs r1, #0
|
|
800d87e: 2001 movs r0, #1
|
|
800d880: f000 faaa bl 800ddd8 <xQueueGenericCreateStatic>
|
|
800d884: 4603 mov r3, r0
|
|
800d886: e023 b.n 800d8d0 <osSemaphoreCreate+0x78>
|
|
}
|
|
else {
|
|
#if (configUSE_COUNTING_SEMAPHORES == 1 )
|
|
return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );
|
|
800d888: 6838 ldr r0, [r7, #0]
|
|
800d88a: 6839 ldr r1, [r7, #0]
|
|
800d88c: 687b ldr r3, [r7, #4]
|
|
800d88e: 685b ldr r3, [r3, #4]
|
|
800d890: 461a mov r2, r3
|
|
800d892: f000 fbcb bl 800e02c <xQueueCreateCountingSemaphoreStatic>
|
|
800d896: 4603 mov r3, r0
|
|
800d898: e01a b.n 800d8d0 <osSemaphoreCreate+0x78>
|
|
return NULL;
|
|
#endif
|
|
}
|
|
}
|
|
else {
|
|
if (count == 1) {
|
|
800d89a: 683b ldr r3, [r7, #0]
|
|
800d89c: 2b01 cmp r3, #1
|
|
800d89e: d110 bne.n 800d8c2 <osSemaphoreCreate+0x6a>
|
|
vSemaphoreCreateBinary(sema);
|
|
800d8a0: 2203 movs r2, #3
|
|
800d8a2: 2100 movs r1, #0
|
|
800d8a4: 2001 movs r0, #1
|
|
800d8a6: f000 fb14 bl 800ded2 <xQueueGenericCreate>
|
|
800d8aa: 60f8 str r0, [r7, #12]
|
|
800d8ac: 68fb ldr r3, [r7, #12]
|
|
800d8ae: 2b00 cmp r3, #0
|
|
800d8b0: d005 beq.n 800d8be <osSemaphoreCreate+0x66>
|
|
800d8b2: 2300 movs r3, #0
|
|
800d8b4: 2200 movs r2, #0
|
|
800d8b6: 2100 movs r1, #0
|
|
800d8b8: 68f8 ldr r0, [r7, #12]
|
|
800d8ba: f000 fc25 bl 800e108 <xQueueGenericSend>
|
|
return sema;
|
|
800d8be: 68fb ldr r3, [r7, #12]
|
|
800d8c0: e006 b.n 800d8d0 <osSemaphoreCreate+0x78>
|
|
}
|
|
else {
|
|
#if (configUSE_COUNTING_SEMAPHORES == 1 )
|
|
return xSemaphoreCreateCounting(count, count);
|
|
800d8c2: 683b ldr r3, [r7, #0]
|
|
800d8c4: 683a ldr r2, [r7, #0]
|
|
800d8c6: 4611 mov r1, r2
|
|
800d8c8: 4618 mov r0, r3
|
|
800d8ca: f000 fbe8 bl 800e09e <xQueueCreateCountingSemaphore>
|
|
800d8ce: 4603 mov r3, r0
|
|
#else
|
|
return NULL;
|
|
#endif
|
|
}
|
|
#endif
|
|
}
|
|
800d8d0: 4618 mov r0, r3
|
|
800d8d2: 3710 adds r7, #16
|
|
800d8d4: 46bd mov sp, r7
|
|
800d8d6: bd80 pop {r7, pc}
|
|
|
|
0800d8d8 <osSemaphoreWait>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval number of available tokens, or -1 in case of incorrect parameters.
|
|
* @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)
|
|
{
|
|
800d8d8: b580 push {r7, lr}
|
|
800d8da: b084 sub sp, #16
|
|
800d8dc: af00 add r7, sp, #0
|
|
800d8de: 6078 str r0, [r7, #4]
|
|
800d8e0: 6039 str r1, [r7, #0]
|
|
TickType_t ticks;
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800d8e2: 2300 movs r3, #0
|
|
800d8e4: 60bb str r3, [r7, #8]
|
|
|
|
|
|
if (semaphore_id == NULL) {
|
|
800d8e6: 687b ldr r3, [r7, #4]
|
|
800d8e8: 2b00 cmp r3, #0
|
|
800d8ea: d101 bne.n 800d8f0 <osSemaphoreWait+0x18>
|
|
return osErrorParameter;
|
|
800d8ec: 2380 movs r3, #128 ; 0x80
|
|
800d8ee: e03a b.n 800d966 <osSemaphoreWait+0x8e>
|
|
}
|
|
|
|
ticks = 0;
|
|
800d8f0: 2300 movs r3, #0
|
|
800d8f2: 60fb str r3, [r7, #12]
|
|
if (millisec == osWaitForever) {
|
|
800d8f4: 683b ldr r3, [r7, #0]
|
|
800d8f6: f1b3 3fff cmp.w r3, #4294967295
|
|
800d8fa: d103 bne.n 800d904 <osSemaphoreWait+0x2c>
|
|
ticks = portMAX_DELAY;
|
|
800d8fc: f04f 33ff mov.w r3, #4294967295
|
|
800d900: 60fb str r3, [r7, #12]
|
|
800d902: e009 b.n 800d918 <osSemaphoreWait+0x40>
|
|
}
|
|
else if (millisec != 0) {
|
|
800d904: 683b ldr r3, [r7, #0]
|
|
800d906: 2b00 cmp r3, #0
|
|
800d908: d006 beq.n 800d918 <osSemaphoreWait+0x40>
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800d90a: 683b ldr r3, [r7, #0]
|
|
800d90c: 60fb str r3, [r7, #12]
|
|
if (ticks == 0) {
|
|
800d90e: 68fb ldr r3, [r7, #12]
|
|
800d910: 2b00 cmp r3, #0
|
|
800d912: d101 bne.n 800d918 <osSemaphoreWait+0x40>
|
|
ticks = 1;
|
|
800d914: 2301 movs r3, #1
|
|
800d916: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800d918: f7ff fe78 bl 800d60c <inHandlerMode>
|
|
800d91c: 4603 mov r3, r0
|
|
800d91e: 2b00 cmp r3, #0
|
|
800d920: d017 beq.n 800d952 <osSemaphoreWait+0x7a>
|
|
if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {
|
|
800d922: f107 0308 add.w r3, r7, #8
|
|
800d926: 461a mov r2, r3
|
|
800d928: 2100 movs r1, #0
|
|
800d92a: 6878 ldr r0, [r7, #4]
|
|
800d92c: f001 f80e bl 800e94c <xQueueReceiveFromISR>
|
|
800d930: 4603 mov r3, r0
|
|
800d932: 2b01 cmp r3, #1
|
|
800d934: d001 beq.n 800d93a <osSemaphoreWait+0x62>
|
|
return osErrorOS;
|
|
800d936: 23ff movs r3, #255 ; 0xff
|
|
800d938: e015 b.n 800d966 <osSemaphoreWait+0x8e>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800d93a: 68bb ldr r3, [r7, #8]
|
|
800d93c: 2b00 cmp r3, #0
|
|
800d93e: d011 beq.n 800d964 <osSemaphoreWait+0x8c>
|
|
800d940: 4b0b ldr r3, [pc, #44] ; (800d970 <osSemaphoreWait+0x98>)
|
|
800d942: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800d946: 601a str r2, [r3, #0]
|
|
800d948: f3bf 8f4f dsb sy
|
|
800d94c: f3bf 8f6f isb sy
|
|
800d950: e008 b.n 800d964 <osSemaphoreWait+0x8c>
|
|
}
|
|
else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {
|
|
800d952: 68f9 ldr r1, [r7, #12]
|
|
800d954: 6878 ldr r0, [r7, #4]
|
|
800d956: f000 fee9 bl 800e72c <xQueueSemaphoreTake>
|
|
800d95a: 4603 mov r3, r0
|
|
800d95c: 2b01 cmp r3, #1
|
|
800d95e: d001 beq.n 800d964 <osSemaphoreWait+0x8c>
|
|
return osErrorOS;
|
|
800d960: 23ff movs r3, #255 ; 0xff
|
|
800d962: e000 b.n 800d966 <osSemaphoreWait+0x8e>
|
|
}
|
|
|
|
return osOK;
|
|
800d964: 2300 movs r3, #0
|
|
}
|
|
800d966: 4618 mov r0, r3
|
|
800d968: 3710 adds r7, #16
|
|
800d96a: 46bd mov sp, r7
|
|
800d96c: bd80 pop {r7, pc}
|
|
800d96e: bf00 nop
|
|
800d970: e000ed04 .word 0xe000ed04
|
|
|
|
0800d974 <osSemaphoreRelease>:
|
|
* @param semaphore_id semaphore object referenced with \ref osSemaphore.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id)
|
|
{
|
|
800d974: b580 push {r7, lr}
|
|
800d976: b084 sub sp, #16
|
|
800d978: af00 add r7, sp, #0
|
|
800d97a: 6078 str r0, [r7, #4]
|
|
osStatus result = osOK;
|
|
800d97c: 2300 movs r3, #0
|
|
800d97e: 60fb str r3, [r7, #12]
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800d980: 2300 movs r3, #0
|
|
800d982: 60bb str r3, [r7, #8]
|
|
|
|
|
|
if (inHandlerMode()) {
|
|
800d984: f7ff fe42 bl 800d60c <inHandlerMode>
|
|
800d988: 4603 mov r3, r0
|
|
800d98a: 2b00 cmp r3, #0
|
|
800d98c: d016 beq.n 800d9bc <osSemaphoreRelease+0x48>
|
|
if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {
|
|
800d98e: f107 0308 add.w r3, r7, #8
|
|
800d992: 4619 mov r1, r3
|
|
800d994: 6878 ldr r0, [r7, #4]
|
|
800d996: f000 fd55 bl 800e444 <xQueueGiveFromISR>
|
|
800d99a: 4603 mov r3, r0
|
|
800d99c: 2b01 cmp r3, #1
|
|
800d99e: d001 beq.n 800d9a4 <osSemaphoreRelease+0x30>
|
|
return osErrorOS;
|
|
800d9a0: 23ff movs r3, #255 ; 0xff
|
|
800d9a2: e017 b.n 800d9d4 <osSemaphoreRelease+0x60>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800d9a4: 68bb ldr r3, [r7, #8]
|
|
800d9a6: 2b00 cmp r3, #0
|
|
800d9a8: d013 beq.n 800d9d2 <osSemaphoreRelease+0x5e>
|
|
800d9aa: 4b0c ldr r3, [pc, #48] ; (800d9dc <osSemaphoreRelease+0x68>)
|
|
800d9ac: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800d9b0: 601a str r2, [r3, #0]
|
|
800d9b2: f3bf 8f4f dsb sy
|
|
800d9b6: f3bf 8f6f isb sy
|
|
800d9ba: e00a b.n 800d9d2 <osSemaphoreRelease+0x5e>
|
|
}
|
|
else {
|
|
if (xSemaphoreGive(semaphore_id) != pdTRUE) {
|
|
800d9bc: 2300 movs r3, #0
|
|
800d9be: 2200 movs r2, #0
|
|
800d9c0: 2100 movs r1, #0
|
|
800d9c2: 6878 ldr r0, [r7, #4]
|
|
800d9c4: f000 fba0 bl 800e108 <xQueueGenericSend>
|
|
800d9c8: 4603 mov r3, r0
|
|
800d9ca: 2b01 cmp r3, #1
|
|
800d9cc: d001 beq.n 800d9d2 <osSemaphoreRelease+0x5e>
|
|
result = osErrorOS;
|
|
800d9ce: 23ff movs r3, #255 ; 0xff
|
|
800d9d0: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
|
|
return result;
|
|
800d9d2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800d9d4: 4618 mov r0, r3
|
|
800d9d6: 3710 adds r7, #16
|
|
800d9d8: 46bd mov sp, r7
|
|
800d9da: bd80 pop {r7, pc}
|
|
800d9dc: e000ed04 .word 0xe000ed04
|
|
|
|
0800d9e0 <osMessageCreate>:
|
|
* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
|
* @retval message queue ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
|
|
{
|
|
800d9e0: b590 push {r4, r7, lr}
|
|
800d9e2: b085 sub sp, #20
|
|
800d9e4: af02 add r7, sp, #8
|
|
800d9e6: 6078 str r0, [r7, #4]
|
|
800d9e8: 6039 str r1, [r7, #0]
|
|
(void) thread_id;
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
|
|
800d9ea: 687b ldr r3, [r7, #4]
|
|
800d9ec: 689b ldr r3, [r3, #8]
|
|
800d9ee: 2b00 cmp r3, #0
|
|
800d9f0: d012 beq.n 800da18 <osMessageCreate+0x38>
|
|
800d9f2: 687b ldr r3, [r7, #4]
|
|
800d9f4: 68db ldr r3, [r3, #12]
|
|
800d9f6: 2b00 cmp r3, #0
|
|
800d9f8: d00e beq.n 800da18 <osMessageCreate+0x38>
|
|
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
|
|
800d9fa: 687b ldr r3, [r7, #4]
|
|
800d9fc: 6818 ldr r0, [r3, #0]
|
|
800d9fe: 687b ldr r3, [r7, #4]
|
|
800da00: 6859 ldr r1, [r3, #4]
|
|
800da02: 687b ldr r3, [r7, #4]
|
|
800da04: 689a ldr r2, [r3, #8]
|
|
800da06: 687b ldr r3, [r7, #4]
|
|
800da08: 68dc ldr r4, [r3, #12]
|
|
800da0a: 2300 movs r3, #0
|
|
800da0c: 9300 str r3, [sp, #0]
|
|
800da0e: 4623 mov r3, r4
|
|
800da10: f000 f9e2 bl 800ddd8 <xQueueGenericCreateStatic>
|
|
800da14: 4603 mov r3, r0
|
|
800da16: e008 b.n 800da2a <osMessageCreate+0x4a>
|
|
}
|
|
else {
|
|
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
|
|
800da18: 687b ldr r3, [r7, #4]
|
|
800da1a: 6818 ldr r0, [r3, #0]
|
|
800da1c: 687b ldr r3, [r7, #4]
|
|
800da1e: 685b ldr r3, [r3, #4]
|
|
800da20: 2200 movs r2, #0
|
|
800da22: 4619 mov r1, r3
|
|
800da24: f000 fa55 bl 800ded2 <xQueueGenericCreate>
|
|
800da28: 4603 mov r3, r0
|
|
#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
|
|
#else
|
|
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
|
|
#endif
|
|
}
|
|
800da2a: 4618 mov r0, r3
|
|
800da2c: 370c adds r7, #12
|
|
800da2e: 46bd mov sp, r7
|
|
800da30: bd90 pop {r4, r7, pc}
|
|
...
|
|
|
|
0800da34 <osMessagePut>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
|
|
{
|
|
800da34: b580 push {r7, lr}
|
|
800da36: b086 sub sp, #24
|
|
800da38: af00 add r7, sp, #0
|
|
800da3a: 60f8 str r0, [r7, #12]
|
|
800da3c: 60b9 str r1, [r7, #8]
|
|
800da3e: 607a str r2, [r7, #4]
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800da40: 2300 movs r3, #0
|
|
800da42: 613b str r3, [r7, #16]
|
|
TickType_t ticks;
|
|
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800da44: 687b ldr r3, [r7, #4]
|
|
800da46: 617b str r3, [r7, #20]
|
|
if (ticks == 0) {
|
|
800da48: 697b ldr r3, [r7, #20]
|
|
800da4a: 2b00 cmp r3, #0
|
|
800da4c: d101 bne.n 800da52 <osMessagePut+0x1e>
|
|
ticks = 1;
|
|
800da4e: 2301 movs r3, #1
|
|
800da50: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800da52: f7ff fddb bl 800d60c <inHandlerMode>
|
|
800da56: 4603 mov r3, r0
|
|
800da58: 2b00 cmp r3, #0
|
|
800da5a: d018 beq.n 800da8e <osMessagePut+0x5a>
|
|
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
|
|
800da5c: f107 0210 add.w r2, r7, #16
|
|
800da60: f107 0108 add.w r1, r7, #8
|
|
800da64: 2300 movs r3, #0
|
|
800da66: 68f8 ldr r0, [r7, #12]
|
|
800da68: f000 fc50 bl 800e30c <xQueueGenericSendFromISR>
|
|
800da6c: 4603 mov r3, r0
|
|
800da6e: 2b01 cmp r3, #1
|
|
800da70: d001 beq.n 800da76 <osMessagePut+0x42>
|
|
return osErrorOS;
|
|
800da72: 23ff movs r3, #255 ; 0xff
|
|
800da74: e018 b.n 800daa8 <osMessagePut+0x74>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800da76: 693b ldr r3, [r7, #16]
|
|
800da78: 2b00 cmp r3, #0
|
|
800da7a: d014 beq.n 800daa6 <osMessagePut+0x72>
|
|
800da7c: 4b0c ldr r3, [pc, #48] ; (800dab0 <osMessagePut+0x7c>)
|
|
800da7e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800da82: 601a str r2, [r3, #0]
|
|
800da84: f3bf 8f4f dsb sy
|
|
800da88: f3bf 8f6f isb sy
|
|
800da8c: e00b b.n 800daa6 <osMessagePut+0x72>
|
|
}
|
|
else {
|
|
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
|
|
800da8e: f107 0108 add.w r1, r7, #8
|
|
800da92: 2300 movs r3, #0
|
|
800da94: 697a ldr r2, [r7, #20]
|
|
800da96: 68f8 ldr r0, [r7, #12]
|
|
800da98: f000 fb36 bl 800e108 <xQueueGenericSend>
|
|
800da9c: 4603 mov r3, r0
|
|
800da9e: 2b01 cmp r3, #1
|
|
800daa0: d001 beq.n 800daa6 <osMessagePut+0x72>
|
|
return osErrorOS;
|
|
800daa2: 23ff movs r3, #255 ; 0xff
|
|
800daa4: e000 b.n 800daa8 <osMessagePut+0x74>
|
|
}
|
|
}
|
|
|
|
return osOK;
|
|
800daa6: 2300 movs r3, #0
|
|
}
|
|
800daa8: 4618 mov r0, r3
|
|
800daaa: 3718 adds r7, #24
|
|
800daac: 46bd mov sp, r7
|
|
800daae: bd80 pop {r7, pc}
|
|
800dab0: e000ed04 .word 0xe000ed04
|
|
|
|
0800dab4 <osMessageGet>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval event information that includes status code.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
|
|
{
|
|
800dab4: b590 push {r4, r7, lr}
|
|
800dab6: b08b sub sp, #44 ; 0x2c
|
|
800dab8: af00 add r7, sp, #0
|
|
800daba: 60f8 str r0, [r7, #12]
|
|
800dabc: 60b9 str r1, [r7, #8]
|
|
800dabe: 607a str r2, [r7, #4]
|
|
portBASE_TYPE taskWoken;
|
|
TickType_t ticks;
|
|
osEvent event;
|
|
|
|
event.def.message_id = queue_id;
|
|
800dac0: 68bb ldr r3, [r7, #8]
|
|
800dac2: 61fb str r3, [r7, #28]
|
|
event.value.v = 0;
|
|
800dac4: 2300 movs r3, #0
|
|
800dac6: 61bb str r3, [r7, #24]
|
|
|
|
if (queue_id == NULL) {
|
|
800dac8: 68bb ldr r3, [r7, #8]
|
|
800daca: 2b00 cmp r3, #0
|
|
800dacc: d10a bne.n 800dae4 <osMessageGet+0x30>
|
|
event.status = osErrorParameter;
|
|
800dace: 2380 movs r3, #128 ; 0x80
|
|
800dad0: 617b str r3, [r7, #20]
|
|
return event;
|
|
800dad2: 68fb ldr r3, [r7, #12]
|
|
800dad4: 461c mov r4, r3
|
|
800dad6: f107 0314 add.w r3, r7, #20
|
|
800dada: e893 0007 ldmia.w r3, {r0, r1, r2}
|
|
800dade: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
800dae2: e054 b.n 800db8e <osMessageGet+0xda>
|
|
}
|
|
|
|
taskWoken = pdFALSE;
|
|
800dae4: 2300 movs r3, #0
|
|
800dae6: 623b str r3, [r7, #32]
|
|
|
|
ticks = 0;
|
|
800dae8: 2300 movs r3, #0
|
|
800daea: 627b str r3, [r7, #36] ; 0x24
|
|
if (millisec == osWaitForever) {
|
|
800daec: 687b ldr r3, [r7, #4]
|
|
800daee: f1b3 3fff cmp.w r3, #4294967295
|
|
800daf2: d103 bne.n 800dafc <osMessageGet+0x48>
|
|
ticks = portMAX_DELAY;
|
|
800daf4: f04f 33ff mov.w r3, #4294967295
|
|
800daf8: 627b str r3, [r7, #36] ; 0x24
|
|
800dafa: e009 b.n 800db10 <osMessageGet+0x5c>
|
|
}
|
|
else if (millisec != 0) {
|
|
800dafc: 687b ldr r3, [r7, #4]
|
|
800dafe: 2b00 cmp r3, #0
|
|
800db00: d006 beq.n 800db10 <osMessageGet+0x5c>
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800db02: 687b ldr r3, [r7, #4]
|
|
800db04: 627b str r3, [r7, #36] ; 0x24
|
|
if (ticks == 0) {
|
|
800db06: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800db08: 2b00 cmp r3, #0
|
|
800db0a: d101 bne.n 800db10 <osMessageGet+0x5c>
|
|
ticks = 1;
|
|
800db0c: 2301 movs r3, #1
|
|
800db0e: 627b str r3, [r7, #36] ; 0x24
|
|
}
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800db10: f7ff fd7c bl 800d60c <inHandlerMode>
|
|
800db14: 4603 mov r3, r0
|
|
800db16: 2b00 cmp r3, #0
|
|
800db18: d01c beq.n 800db54 <osMessageGet+0xa0>
|
|
if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
|
|
800db1a: f107 0220 add.w r2, r7, #32
|
|
800db1e: f107 0314 add.w r3, r7, #20
|
|
800db22: 3304 adds r3, #4
|
|
800db24: 4619 mov r1, r3
|
|
800db26: 68b8 ldr r0, [r7, #8]
|
|
800db28: f000 ff10 bl 800e94c <xQueueReceiveFromISR>
|
|
800db2c: 4603 mov r3, r0
|
|
800db2e: 2b01 cmp r3, #1
|
|
800db30: d102 bne.n 800db38 <osMessageGet+0x84>
|
|
/* We have mail */
|
|
event.status = osEventMessage;
|
|
800db32: 2310 movs r3, #16
|
|
800db34: 617b str r3, [r7, #20]
|
|
800db36: e001 b.n 800db3c <osMessageGet+0x88>
|
|
}
|
|
else {
|
|
event.status = osOK;
|
|
800db38: 2300 movs r3, #0
|
|
800db3a: 617b str r3, [r7, #20]
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800db3c: 6a3b ldr r3, [r7, #32]
|
|
800db3e: 2b00 cmp r3, #0
|
|
800db40: d01d beq.n 800db7e <osMessageGet+0xca>
|
|
800db42: 4b15 ldr r3, [pc, #84] ; (800db98 <osMessageGet+0xe4>)
|
|
800db44: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800db48: 601a str r2, [r3, #0]
|
|
800db4a: f3bf 8f4f dsb sy
|
|
800db4e: f3bf 8f6f isb sy
|
|
800db52: e014 b.n 800db7e <osMessageGet+0xca>
|
|
}
|
|
else {
|
|
if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
|
|
800db54: f107 0314 add.w r3, r7, #20
|
|
800db58: 3304 adds r3, #4
|
|
800db5a: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
800db5c: 4619 mov r1, r3
|
|
800db5e: 68b8 ldr r0, [r7, #8]
|
|
800db60: f000 fd02 bl 800e568 <xQueueReceive>
|
|
800db64: 4603 mov r3, r0
|
|
800db66: 2b01 cmp r3, #1
|
|
800db68: d102 bne.n 800db70 <osMessageGet+0xbc>
|
|
/* We have mail */
|
|
event.status = osEventMessage;
|
|
800db6a: 2310 movs r3, #16
|
|
800db6c: 617b str r3, [r7, #20]
|
|
800db6e: e006 b.n 800db7e <osMessageGet+0xca>
|
|
}
|
|
else {
|
|
event.status = (ticks == 0) ? osOK : osEventTimeout;
|
|
800db70: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800db72: 2b00 cmp r3, #0
|
|
800db74: d101 bne.n 800db7a <osMessageGet+0xc6>
|
|
800db76: 2300 movs r3, #0
|
|
800db78: e000 b.n 800db7c <osMessageGet+0xc8>
|
|
800db7a: 2340 movs r3, #64 ; 0x40
|
|
800db7c: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
|
|
return event;
|
|
800db7e: 68fb ldr r3, [r7, #12]
|
|
800db80: 461c mov r4, r3
|
|
800db82: f107 0314 add.w r3, r7, #20
|
|
800db86: e893 0007 ldmia.w r3, {r0, r1, r2}
|
|
800db8a: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
}
|
|
800db8e: 68f8 ldr r0, [r7, #12]
|
|
800db90: 372c adds r7, #44 ; 0x2c
|
|
800db92: 46bd mov sp, r7
|
|
800db94: bd90 pop {r4, r7, pc}
|
|
800db96: bf00 nop
|
|
800db98: e000ed04 .word 0xe000ed04
|
|
|
|
0800db9c <vListInitialise>:
|
|
/*-----------------------------------------------------------
|
|
* PUBLIC LIST API documented in list.h
|
|
*----------------------------------------------------------*/
|
|
|
|
void vListInitialise( List_t * const pxList )
|
|
{
|
|
800db9c: b480 push {r7}
|
|
800db9e: b083 sub sp, #12
|
|
800dba0: af00 add r7, sp, #0
|
|
800dba2: 6078 str r0, [r7, #4]
|
|
/* The list structure contains a list item which is used to mark the
|
|
end of the list. To initialise the list the list end is inserted
|
|
as the only list entry. */
|
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800dba4: 687b ldr r3, [r7, #4]
|
|
800dba6: f103 0208 add.w r2, r3, #8
|
|
800dbaa: 687b ldr r3, [r7, #4]
|
|
800dbac: 605a str r2, [r3, #4]
|
|
|
|
/* The list end value is the highest possible value in the list to
|
|
ensure it remains at the end of the list. */
|
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
|
800dbae: 687b ldr r3, [r7, #4]
|
|
800dbb0: f04f 32ff mov.w r2, #4294967295
|
|
800dbb4: 609a str r2, [r3, #8]
|
|
|
|
/* The list end next and previous pointers point to itself so we know
|
|
when the list is empty. */
|
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800dbb6: 687b ldr r3, [r7, #4]
|
|
800dbb8: f103 0208 add.w r2, r3, #8
|
|
800dbbc: 687b ldr r3, [r7, #4]
|
|
800dbbe: 60da str r2, [r3, #12]
|
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800dbc0: 687b ldr r3, [r7, #4]
|
|
800dbc2: f103 0208 add.w r2, r3, #8
|
|
800dbc6: 687b ldr r3, [r7, #4]
|
|
800dbc8: 611a str r2, [r3, #16]
|
|
|
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
|
800dbca: 687b ldr r3, [r7, #4]
|
|
800dbcc: 2200 movs r2, #0
|
|
800dbce: 601a str r2, [r3, #0]
|
|
|
|
/* Write known values into the list if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
|
}
|
|
800dbd0: bf00 nop
|
|
800dbd2: 370c adds r7, #12
|
|
800dbd4: 46bd mov sp, r7
|
|
800dbd6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dbda: 4770 bx lr
|
|
|
|
0800dbdc <vListInitialiseItem>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
|
{
|
|
800dbdc: b480 push {r7}
|
|
800dbde: b083 sub sp, #12
|
|
800dbe0: af00 add r7, sp, #0
|
|
800dbe2: 6078 str r0, [r7, #4]
|
|
/* Make sure the list item is not recorded as being on a list. */
|
|
pxItem->pxContainer = NULL;
|
|
800dbe4: 687b ldr r3, [r7, #4]
|
|
800dbe6: 2200 movs r2, #0
|
|
800dbe8: 611a str r2, [r3, #16]
|
|
|
|
/* Write known values into the list item if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
}
|
|
800dbea: bf00 nop
|
|
800dbec: 370c adds r7, #12
|
|
800dbee: 46bd mov sp, r7
|
|
800dbf0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dbf4: 4770 bx lr
|
|
|
|
0800dbf6 <vListInsertEnd>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800dbf6: b480 push {r7}
|
|
800dbf8: b085 sub sp, #20
|
|
800dbfa: af00 add r7, sp, #0
|
|
800dbfc: 6078 str r0, [r7, #4]
|
|
800dbfe: 6039 str r1, [r7, #0]
|
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
|
800dc00: 687b ldr r3, [r7, #4]
|
|
800dc02: 685b ldr r3, [r3, #4]
|
|
800dc04: 60fb str r3, [r7, #12]
|
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
|
|
|
/* Insert a new list item into pxList, but rather than sort the list,
|
|
makes the new list item the last item to be removed by a call to
|
|
listGET_OWNER_OF_NEXT_ENTRY(). */
|
|
pxNewListItem->pxNext = pxIndex;
|
|
800dc06: 683b ldr r3, [r7, #0]
|
|
800dc08: 68fa ldr r2, [r7, #12]
|
|
800dc0a: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
|
800dc0c: 68fb ldr r3, [r7, #12]
|
|
800dc0e: 689a ldr r2, [r3, #8]
|
|
800dc10: 683b ldr r3, [r7, #0]
|
|
800dc12: 609a str r2, [r3, #8]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
|
800dc14: 68fb ldr r3, [r7, #12]
|
|
800dc16: 689b ldr r3, [r3, #8]
|
|
800dc18: 683a ldr r2, [r7, #0]
|
|
800dc1a: 605a str r2, [r3, #4]
|
|
pxIndex->pxPrevious = pxNewListItem;
|
|
800dc1c: 68fb ldr r3, [r7, #12]
|
|
800dc1e: 683a ldr r2, [r7, #0]
|
|
800dc20: 609a str r2, [r3, #8]
|
|
|
|
/* Remember which list the item is in. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800dc22: 683b ldr r3, [r7, #0]
|
|
800dc24: 687a ldr r2, [r7, #4]
|
|
800dc26: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800dc28: 687b ldr r3, [r7, #4]
|
|
800dc2a: 681b ldr r3, [r3, #0]
|
|
800dc2c: 1c5a adds r2, r3, #1
|
|
800dc2e: 687b ldr r3, [r7, #4]
|
|
800dc30: 601a str r2, [r3, #0]
|
|
}
|
|
800dc32: bf00 nop
|
|
800dc34: 3714 adds r7, #20
|
|
800dc36: 46bd mov sp, r7
|
|
800dc38: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dc3c: 4770 bx lr
|
|
|
|
0800dc3e <vListInsert>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800dc3e: b480 push {r7}
|
|
800dc40: b085 sub sp, #20
|
|
800dc42: af00 add r7, sp, #0
|
|
800dc44: 6078 str r0, [r7, #4]
|
|
800dc46: 6039 str r1, [r7, #0]
|
|
ListItem_t *pxIterator;
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
|
800dc48: 683b ldr r3, [r7, #0]
|
|
800dc4a: 681b ldr r3, [r3, #0]
|
|
800dc4c: 60bb str r3, [r7, #8]
|
|
new list item should be placed after it. This ensures that TCBs which are
|
|
stored in ready lists (all of which have the same xItemValue value) get a
|
|
share of the CPU. However, if the xItemValue is the same as the back marker
|
|
the iteration loop below will not end. Therefore the value is checked
|
|
first, and the algorithm slightly modified if necessary. */
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
|
800dc4e: 68bb ldr r3, [r7, #8]
|
|
800dc50: f1b3 3fff cmp.w r3, #4294967295
|
|
800dc54: d103 bne.n 800dc5e <vListInsert+0x20>
|
|
{
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
|
800dc56: 687b ldr r3, [r7, #4]
|
|
800dc58: 691b ldr r3, [r3, #16]
|
|
800dc5a: 60fb str r3, [r7, #12]
|
|
800dc5c: e00c b.n 800dc78 <vListInsert+0x3a>
|
|
4) Using a queue or semaphore before it has been initialised or
|
|
before the scheduler has been started (are interrupts firing
|
|
before vTaskStartScheduler() has been called?).
|
|
**********************************************************************/
|
|
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
|
800dc5e: 687b ldr r3, [r7, #4]
|
|
800dc60: 3308 adds r3, #8
|
|
800dc62: 60fb str r3, [r7, #12]
|
|
800dc64: e002 b.n 800dc6c <vListInsert+0x2e>
|
|
800dc66: 68fb ldr r3, [r7, #12]
|
|
800dc68: 685b ldr r3, [r3, #4]
|
|
800dc6a: 60fb str r3, [r7, #12]
|
|
800dc6c: 68fb ldr r3, [r7, #12]
|
|
800dc6e: 685b ldr r3, [r3, #4]
|
|
800dc70: 681b ldr r3, [r3, #0]
|
|
800dc72: 68ba ldr r2, [r7, #8]
|
|
800dc74: 429a cmp r2, r3
|
|
800dc76: d2f6 bcs.n 800dc66 <vListInsert+0x28>
|
|
/* There is nothing to do here, just iterating to the wanted
|
|
insertion position. */
|
|
}
|
|
}
|
|
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
|
800dc78: 68fb ldr r3, [r7, #12]
|
|
800dc7a: 685a ldr r2, [r3, #4]
|
|
800dc7c: 683b ldr r3, [r7, #0]
|
|
800dc7e: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
|
800dc80: 683b ldr r3, [r7, #0]
|
|
800dc82: 685b ldr r3, [r3, #4]
|
|
800dc84: 683a ldr r2, [r7, #0]
|
|
800dc86: 609a str r2, [r3, #8]
|
|
pxNewListItem->pxPrevious = pxIterator;
|
|
800dc88: 683b ldr r3, [r7, #0]
|
|
800dc8a: 68fa ldr r2, [r7, #12]
|
|
800dc8c: 609a str r2, [r3, #8]
|
|
pxIterator->pxNext = pxNewListItem;
|
|
800dc8e: 68fb ldr r3, [r7, #12]
|
|
800dc90: 683a ldr r2, [r7, #0]
|
|
800dc92: 605a str r2, [r3, #4]
|
|
|
|
/* Remember which list the item is in. This allows fast removal of the
|
|
item later. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800dc94: 683b ldr r3, [r7, #0]
|
|
800dc96: 687a ldr r2, [r7, #4]
|
|
800dc98: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800dc9a: 687b ldr r3, [r7, #4]
|
|
800dc9c: 681b ldr r3, [r3, #0]
|
|
800dc9e: 1c5a adds r2, r3, #1
|
|
800dca0: 687b ldr r3, [r7, #4]
|
|
800dca2: 601a str r2, [r3, #0]
|
|
}
|
|
800dca4: bf00 nop
|
|
800dca6: 3714 adds r7, #20
|
|
800dca8: 46bd mov sp, r7
|
|
800dcaa: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dcae: 4770 bx lr
|
|
|
|
0800dcb0 <uxListRemove>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
|
{
|
|
800dcb0: b480 push {r7}
|
|
800dcb2: b085 sub sp, #20
|
|
800dcb4: af00 add r7, sp, #0
|
|
800dcb6: 6078 str r0, [r7, #4]
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
|
item. */
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
|
800dcb8: 687b ldr r3, [r7, #4]
|
|
800dcba: 691b ldr r3, [r3, #16]
|
|
800dcbc: 60fb str r3, [r7, #12]
|
|
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
|
800dcbe: 687b ldr r3, [r7, #4]
|
|
800dcc0: 685b ldr r3, [r3, #4]
|
|
800dcc2: 687a ldr r2, [r7, #4]
|
|
800dcc4: 6892 ldr r2, [r2, #8]
|
|
800dcc6: 609a str r2, [r3, #8]
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
|
800dcc8: 687b ldr r3, [r7, #4]
|
|
800dcca: 689b ldr r3, [r3, #8]
|
|
800dccc: 687a ldr r2, [r7, #4]
|
|
800dcce: 6852 ldr r2, [r2, #4]
|
|
800dcd0: 605a str r2, [r3, #4]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
/* Make sure the index is left pointing to a valid item. */
|
|
if( pxList->pxIndex == pxItemToRemove )
|
|
800dcd2: 68fb ldr r3, [r7, #12]
|
|
800dcd4: 685b ldr r3, [r3, #4]
|
|
800dcd6: 687a ldr r2, [r7, #4]
|
|
800dcd8: 429a cmp r2, r3
|
|
800dcda: d103 bne.n 800dce4 <uxListRemove+0x34>
|
|
{
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
|
800dcdc: 687b ldr r3, [r7, #4]
|
|
800dcde: 689a ldr r2, [r3, #8]
|
|
800dce0: 68fb ldr r3, [r7, #12]
|
|
800dce2: 605a str r2, [r3, #4]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxItemToRemove->pxContainer = NULL;
|
|
800dce4: 687b ldr r3, [r7, #4]
|
|
800dce6: 2200 movs r2, #0
|
|
800dce8: 611a str r2, [r3, #16]
|
|
( pxList->uxNumberOfItems )--;
|
|
800dcea: 68fb ldr r3, [r7, #12]
|
|
800dcec: 681b ldr r3, [r3, #0]
|
|
800dcee: 1e5a subs r2, r3, #1
|
|
800dcf0: 68fb ldr r3, [r7, #12]
|
|
800dcf2: 601a str r2, [r3, #0]
|
|
|
|
return pxList->uxNumberOfItems;
|
|
800dcf4: 68fb ldr r3, [r7, #12]
|
|
800dcf6: 681b ldr r3, [r3, #0]
|
|
}
|
|
800dcf8: 4618 mov r0, r3
|
|
800dcfa: 3714 adds r7, #20
|
|
800dcfc: 46bd mov sp, r7
|
|
800dcfe: f85d 7b04 ldr.w r7, [sp], #4
|
|
800dd02: 4770 bx lr
|
|
|
|
0800dd04 <xQueueGenericReset>:
|
|
} \
|
|
taskEXIT_CRITICAL()
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
|
|
{
|
|
800dd04: b580 push {r7, lr}
|
|
800dd06: b084 sub sp, #16
|
|
800dd08: af00 add r7, sp, #0
|
|
800dd0a: 6078 str r0, [r7, #4]
|
|
800dd0c: 6039 str r1, [r7, #0]
|
|
Queue_t * const pxQueue = xQueue;
|
|
800dd0e: 687b ldr r3, [r7, #4]
|
|
800dd10: 60fb str r3, [r7, #12]
|
|
|
|
configASSERT( pxQueue );
|
|
800dd12: 68fb ldr r3, [r7, #12]
|
|
800dd14: 2b00 cmp r3, #0
|
|
800dd16: d10b bne.n 800dd30 <xQueueGenericReset+0x2c>
|
|
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800dd18: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800dd1c: b672 cpsid i
|
|
800dd1e: f383 8811 msr BASEPRI, r3
|
|
800dd22: f3bf 8f6f isb sy
|
|
800dd26: f3bf 8f4f dsb sy
|
|
800dd2a: b662 cpsie i
|
|
800dd2c: 60bb str r3, [r7, #8]
|
|
800dd2e: e7fe b.n 800dd2e <xQueueGenericReset+0x2a>
|
|
|
|
taskENTER_CRITICAL();
|
|
800dd30: f002 fa3a bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800dd34: 68fb ldr r3, [r7, #12]
|
|
800dd36: 681a ldr r2, [r3, #0]
|
|
800dd38: 68fb ldr r3, [r7, #12]
|
|
800dd3a: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800dd3c: 68f9 ldr r1, [r7, #12]
|
|
800dd3e: 6c09 ldr r1, [r1, #64] ; 0x40
|
|
800dd40: fb01 f303 mul.w r3, r1, r3
|
|
800dd44: 441a add r2, r3
|
|
800dd46: 68fb ldr r3, [r7, #12]
|
|
800dd48: 609a str r2, [r3, #8]
|
|
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
|
|
800dd4a: 68fb ldr r3, [r7, #12]
|
|
800dd4c: 2200 movs r2, #0
|
|
800dd4e: 639a str r2, [r3, #56] ; 0x38
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800dd50: 68fb ldr r3, [r7, #12]
|
|
800dd52: 681a ldr r2, [r3, #0]
|
|
800dd54: 68fb ldr r3, [r7, #12]
|
|
800dd56: 605a str r2, [r3, #4]
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800dd58: 68fb ldr r3, [r7, #12]
|
|
800dd5a: 681a ldr r2, [r3, #0]
|
|
800dd5c: 68fb ldr r3, [r7, #12]
|
|
800dd5e: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800dd60: 3b01 subs r3, #1
|
|
800dd62: 68f9 ldr r1, [r7, #12]
|
|
800dd64: 6c09 ldr r1, [r1, #64] ; 0x40
|
|
800dd66: fb01 f303 mul.w r3, r1, r3
|
|
800dd6a: 441a add r2, r3
|
|
800dd6c: 68fb ldr r3, [r7, #12]
|
|
800dd6e: 60da str r2, [r3, #12]
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800dd70: 68fb ldr r3, [r7, #12]
|
|
800dd72: 22ff movs r2, #255 ; 0xff
|
|
800dd74: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800dd78: 68fb ldr r3, [r7, #12]
|
|
800dd7a: 22ff movs r2, #255 ; 0xff
|
|
800dd7c: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
|
|
if( xNewQueue == pdFALSE )
|
|
800dd80: 683b ldr r3, [r7, #0]
|
|
800dd82: 2b00 cmp r3, #0
|
|
800dd84: d114 bne.n 800ddb0 <xQueueGenericReset+0xac>
|
|
/* If there are tasks blocked waiting to read from the queue, then
|
|
the tasks will remain blocked as after this function exits the queue
|
|
will still be empty. If there are tasks blocked waiting to write to
|
|
the queue, then one should be unblocked as after this function exits
|
|
it will be possible to write to it. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800dd86: 68fb ldr r3, [r7, #12]
|
|
800dd88: 691b ldr r3, [r3, #16]
|
|
800dd8a: 2b00 cmp r3, #0
|
|
800dd8c: d01a beq.n 800ddc4 <xQueueGenericReset+0xc0>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800dd8e: 68fb ldr r3, [r7, #12]
|
|
800dd90: 3310 adds r3, #16
|
|
800dd92: 4618 mov r0, r3
|
|
800dd94: f001 fd00 bl 800f798 <xTaskRemoveFromEventList>
|
|
800dd98: 4603 mov r3, r0
|
|
800dd9a: 2b00 cmp r3, #0
|
|
800dd9c: d012 beq.n 800ddc4 <xQueueGenericReset+0xc0>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800dd9e: 4b0d ldr r3, [pc, #52] ; (800ddd4 <xQueueGenericReset+0xd0>)
|
|
800dda0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800dda4: 601a str r2, [r3, #0]
|
|
800dda6: f3bf 8f4f dsb sy
|
|
800ddaa: f3bf 8f6f isb sy
|
|
800ddae: e009 b.n 800ddc4 <xQueueGenericReset+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the event queues start in the correct state. */
|
|
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
|
|
800ddb0: 68fb ldr r3, [r7, #12]
|
|
800ddb2: 3310 adds r3, #16
|
|
800ddb4: 4618 mov r0, r3
|
|
800ddb6: f7ff fef1 bl 800db9c <vListInitialise>
|
|
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
|
|
800ddba: 68fb ldr r3, [r7, #12]
|
|
800ddbc: 3324 adds r3, #36 ; 0x24
|
|
800ddbe: 4618 mov r0, r3
|
|
800ddc0: f7ff feec bl 800db9c <vListInitialise>
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ddc4: f002 fa22 bl 801020c <vPortExitCritical>
|
|
|
|
/* A value is returned for calling semantic consistency with previous
|
|
versions. */
|
|
return pdPASS;
|
|
800ddc8: 2301 movs r3, #1
|
|
}
|
|
800ddca: 4618 mov r0, r3
|
|
800ddcc: 3710 adds r7, #16
|
|
800ddce: 46bd mov sp, r7
|
|
800ddd0: bd80 pop {r7, pc}
|
|
800ddd2: bf00 nop
|
|
800ddd4: e000ed04 .word 0xe000ed04
|
|
|
|
0800ddd8 <xQueueGenericCreateStatic>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
|
|
{
|
|
800ddd8: b580 push {r7, lr}
|
|
800ddda: b08e sub sp, #56 ; 0x38
|
|
800dddc: af02 add r7, sp, #8
|
|
800ddde: 60f8 str r0, [r7, #12]
|
|
800dde0: 60b9 str r1, [r7, #8]
|
|
800dde2: 607a str r2, [r7, #4]
|
|
800dde4: 603b str r3, [r7, #0]
|
|
Queue_t *pxNewQueue;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800dde6: 68fb ldr r3, [r7, #12]
|
|
800dde8: 2b00 cmp r3, #0
|
|
800ddea: d10b bne.n 800de04 <xQueueGenericCreateStatic+0x2c>
|
|
800ddec: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800ddf0: b672 cpsid i
|
|
800ddf2: f383 8811 msr BASEPRI, r3
|
|
800ddf6: f3bf 8f6f isb sy
|
|
800ddfa: f3bf 8f4f dsb sy
|
|
800ddfe: b662 cpsie i
|
|
800de00: 62bb str r3, [r7, #40] ; 0x28
|
|
800de02: e7fe b.n 800de02 <xQueueGenericCreateStatic+0x2a>
|
|
|
|
/* The StaticQueue_t structure and the queue storage area must be
|
|
supplied. */
|
|
configASSERT( pxStaticQueue != NULL );
|
|
800de04: 683b ldr r3, [r7, #0]
|
|
800de06: 2b00 cmp r3, #0
|
|
800de08: d10b bne.n 800de22 <xQueueGenericCreateStatic+0x4a>
|
|
800de0a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800de0e: b672 cpsid i
|
|
800de10: f383 8811 msr BASEPRI, r3
|
|
800de14: f3bf 8f6f isb sy
|
|
800de18: f3bf 8f4f dsb sy
|
|
800de1c: b662 cpsie i
|
|
800de1e: 627b str r3, [r7, #36] ; 0x24
|
|
800de20: e7fe b.n 800de20 <xQueueGenericCreateStatic+0x48>
|
|
|
|
/* A queue storage area should be provided if the item size is not 0, and
|
|
should not be provided if the item size is 0. */
|
|
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
|
|
800de22: 687b ldr r3, [r7, #4]
|
|
800de24: 2b00 cmp r3, #0
|
|
800de26: d002 beq.n 800de2e <xQueueGenericCreateStatic+0x56>
|
|
800de28: 68bb ldr r3, [r7, #8]
|
|
800de2a: 2b00 cmp r3, #0
|
|
800de2c: d001 beq.n 800de32 <xQueueGenericCreateStatic+0x5a>
|
|
800de2e: 2301 movs r3, #1
|
|
800de30: e000 b.n 800de34 <xQueueGenericCreateStatic+0x5c>
|
|
800de32: 2300 movs r3, #0
|
|
800de34: 2b00 cmp r3, #0
|
|
800de36: d10b bne.n 800de50 <xQueueGenericCreateStatic+0x78>
|
|
800de38: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800de3c: b672 cpsid i
|
|
800de3e: f383 8811 msr BASEPRI, r3
|
|
800de42: f3bf 8f6f isb sy
|
|
800de46: f3bf 8f4f dsb sy
|
|
800de4a: b662 cpsie i
|
|
800de4c: 623b str r3, [r7, #32]
|
|
800de4e: e7fe b.n 800de4e <xQueueGenericCreateStatic+0x76>
|
|
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
|
|
800de50: 687b ldr r3, [r7, #4]
|
|
800de52: 2b00 cmp r3, #0
|
|
800de54: d102 bne.n 800de5c <xQueueGenericCreateStatic+0x84>
|
|
800de56: 68bb ldr r3, [r7, #8]
|
|
800de58: 2b00 cmp r3, #0
|
|
800de5a: d101 bne.n 800de60 <xQueueGenericCreateStatic+0x88>
|
|
800de5c: 2301 movs r3, #1
|
|
800de5e: e000 b.n 800de62 <xQueueGenericCreateStatic+0x8a>
|
|
800de60: 2300 movs r3, #0
|
|
800de62: 2b00 cmp r3, #0
|
|
800de64: d10b bne.n 800de7e <xQueueGenericCreateStatic+0xa6>
|
|
800de66: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800de6a: b672 cpsid i
|
|
800de6c: f383 8811 msr BASEPRI, r3
|
|
800de70: f3bf 8f6f isb sy
|
|
800de74: f3bf 8f4f dsb sy
|
|
800de78: b662 cpsie i
|
|
800de7a: 61fb str r3, [r7, #28]
|
|
800de7c: e7fe b.n 800de7c <xQueueGenericCreateStatic+0xa4>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
|
|
the real queue and semaphore structures. */
|
|
volatile size_t xSize = sizeof( StaticQueue_t );
|
|
800de7e: 2348 movs r3, #72 ; 0x48
|
|
800de80: 617b str r3, [r7, #20]
|
|
configASSERT( xSize == sizeof( Queue_t ) );
|
|
800de82: 697b ldr r3, [r7, #20]
|
|
800de84: 2b48 cmp r3, #72 ; 0x48
|
|
800de86: d00b beq.n 800dea0 <xQueueGenericCreateStatic+0xc8>
|
|
800de88: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800de8c: b672 cpsid i
|
|
800de8e: f383 8811 msr BASEPRI, r3
|
|
800de92: f3bf 8f6f isb sy
|
|
800de96: f3bf 8f4f dsb sy
|
|
800de9a: b662 cpsie i
|
|
800de9c: 61bb str r3, [r7, #24]
|
|
800de9e: e7fe b.n 800de9e <xQueueGenericCreateStatic+0xc6>
|
|
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
|
|
800dea0: 697b ldr r3, [r7, #20]
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* The address of a statically allocated queue was passed in, use it.
|
|
The address of a statically allocated storage area was also passed in
|
|
but is already set. */
|
|
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800dea2: 683b ldr r3, [r7, #0]
|
|
800dea4: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
|
if( pxNewQueue != NULL )
|
|
800dea6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800dea8: 2b00 cmp r3, #0
|
|
800deaa: d00d beq.n 800dec8 <xQueueGenericCreateStatic+0xf0>
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be allocated wither statically or dynamically, so
|
|
note this queue was allocated statically in case the queue is
|
|
later deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdTRUE;
|
|
800deac: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800deae: 2201 movs r2, #1
|
|
800deb0: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800deb4: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
|
|
800deb8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800deba: 9300 str r3, [sp, #0]
|
|
800debc: 4613 mov r3, r2
|
|
800debe: 687a ldr r2, [r7, #4]
|
|
800dec0: 68b9 ldr r1, [r7, #8]
|
|
800dec2: 68f8 ldr r0, [r7, #12]
|
|
800dec4: f000 f846 bl 800df54 <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800dec8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
}
|
|
800deca: 4618 mov r0, r3
|
|
800decc: 3730 adds r7, #48 ; 0x30
|
|
800dece: 46bd mov sp, r7
|
|
800ded0: bd80 pop {r7, pc}
|
|
|
|
0800ded2 <xQueueGenericCreate>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
|
|
{
|
|
800ded2: b580 push {r7, lr}
|
|
800ded4: b08a sub sp, #40 ; 0x28
|
|
800ded6: af02 add r7, sp, #8
|
|
800ded8: 60f8 str r0, [r7, #12]
|
|
800deda: 60b9 str r1, [r7, #8]
|
|
800dedc: 4613 mov r3, r2
|
|
800dede: 71fb strb r3, [r7, #7]
|
|
Queue_t *pxNewQueue;
|
|
size_t xQueueSizeInBytes;
|
|
uint8_t *pucQueueStorage;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800dee0: 68fb ldr r3, [r7, #12]
|
|
800dee2: 2b00 cmp r3, #0
|
|
800dee4: d10b bne.n 800defe <xQueueGenericCreate+0x2c>
|
|
800dee6: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800deea: b672 cpsid i
|
|
800deec: f383 8811 msr BASEPRI, r3
|
|
800def0: f3bf 8f6f isb sy
|
|
800def4: f3bf 8f4f dsb sy
|
|
800def8: b662 cpsie i
|
|
800defa: 613b str r3, [r7, #16]
|
|
800defc: e7fe b.n 800defc <xQueueGenericCreate+0x2a>
|
|
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
|
800defe: 68bb ldr r3, [r7, #8]
|
|
800df00: 2b00 cmp r3, #0
|
|
800df02: d102 bne.n 800df0a <xQueueGenericCreate+0x38>
|
|
{
|
|
/* There is not going to be a queue storage area. */
|
|
xQueueSizeInBytes = ( size_t ) 0;
|
|
800df04: 2300 movs r3, #0
|
|
800df06: 61fb str r3, [r7, #28]
|
|
800df08: e004 b.n 800df14 <xQueueGenericCreate+0x42>
|
|
}
|
|
else
|
|
{
|
|
/* Allocate enough space to hold the maximum number of items that
|
|
can be in the queue at any time. */
|
|
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800df0a: 68fb ldr r3, [r7, #12]
|
|
800df0c: 68ba ldr r2, [r7, #8]
|
|
800df0e: fb02 f303 mul.w r3, r2, r3
|
|
800df12: 61fb str r3, [r7, #28]
|
|
alignment requirements of the Queue_t structure - which in this case
|
|
is an int8_t *. Therefore, whenever the stack alignment requirements
|
|
are greater than or equal to the pointer to char requirements the cast
|
|
is safe. In other cases alignment requirements are not strict (one or
|
|
two bytes). */
|
|
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
|
|
800df14: 69fb ldr r3, [r7, #28]
|
|
800df16: 3348 adds r3, #72 ; 0x48
|
|
800df18: 4618 mov r0, r3
|
|
800df1a: f002 fa67 bl 80103ec <pvPortMalloc>
|
|
800df1e: 61b8 str r0, [r7, #24]
|
|
|
|
if( pxNewQueue != NULL )
|
|
800df20: 69bb ldr r3, [r7, #24]
|
|
800df22: 2b00 cmp r3, #0
|
|
800df24: d011 beq.n 800df4a <xQueueGenericCreate+0x78>
|
|
{
|
|
/* Jump past the queue structure to find the location of the queue
|
|
storage area. */
|
|
pucQueueStorage = ( uint8_t * ) pxNewQueue;
|
|
800df26: 69bb ldr r3, [r7, #24]
|
|
800df28: 617b str r3, [r7, #20]
|
|
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800df2a: 697b ldr r3, [r7, #20]
|
|
800df2c: 3348 adds r3, #72 ; 0x48
|
|
800df2e: 617b str r3, [r7, #20]
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be created either statically or dynamically, so
|
|
note this task was created dynamically in case it is later
|
|
deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdFALSE;
|
|
800df30: 69bb ldr r3, [r7, #24]
|
|
800df32: 2200 movs r2, #0
|
|
800df34: f883 2046 strb.w r2, [r3, #70] ; 0x46
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800df38: 79fa ldrb r2, [r7, #7]
|
|
800df3a: 69bb ldr r3, [r7, #24]
|
|
800df3c: 9300 str r3, [sp, #0]
|
|
800df3e: 4613 mov r3, r2
|
|
800df40: 697a ldr r2, [r7, #20]
|
|
800df42: 68b9 ldr r1, [r7, #8]
|
|
800df44: 68f8 ldr r0, [r7, #12]
|
|
800df46: f000 f805 bl 800df54 <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800df4a: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800df4c: 4618 mov r0, r3
|
|
800df4e: 3720 adds r7, #32
|
|
800df50: 46bd mov sp, r7
|
|
800df52: bd80 pop {r7, pc}
|
|
|
|
0800df54 <prvInitialiseNewQueue>:
|
|
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
|
|
{
|
|
800df54: b580 push {r7, lr}
|
|
800df56: b084 sub sp, #16
|
|
800df58: af00 add r7, sp, #0
|
|
800df5a: 60f8 str r0, [r7, #12]
|
|
800df5c: 60b9 str r1, [r7, #8]
|
|
800df5e: 607a str r2, [r7, #4]
|
|
800df60: 70fb strb r3, [r7, #3]
|
|
/* Remove compiler warnings about unused parameters should
|
|
configUSE_TRACE_FACILITY not be set to 1. */
|
|
( void ) ucQueueType;
|
|
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
|
800df62: 68bb ldr r3, [r7, #8]
|
|
800df64: 2b00 cmp r3, #0
|
|
800df66: d103 bne.n 800df70 <prvInitialiseNewQueue+0x1c>
|
|
{
|
|
/* No RAM was allocated for the queue storage area, but PC head cannot
|
|
be set to NULL because NULL is used as a key to say the queue is used as
|
|
a mutex. Therefore just set pcHead to point to the queue as a benign
|
|
value that is known to be within the memory map. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
|
|
800df68: 69bb ldr r3, [r7, #24]
|
|
800df6a: 69ba ldr r2, [r7, #24]
|
|
800df6c: 601a str r2, [r3, #0]
|
|
800df6e: e002 b.n 800df76 <prvInitialiseNewQueue+0x22>
|
|
}
|
|
else
|
|
{
|
|
/* Set the head to the start of the queue storage area. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
|
|
800df70: 69bb ldr r3, [r7, #24]
|
|
800df72: 687a ldr r2, [r7, #4]
|
|
800df74: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialise the queue members as described where the queue type is
|
|
defined. */
|
|
pxNewQueue->uxLength = uxQueueLength;
|
|
800df76: 69bb ldr r3, [r7, #24]
|
|
800df78: 68fa ldr r2, [r7, #12]
|
|
800df7a: 63da str r2, [r3, #60] ; 0x3c
|
|
pxNewQueue->uxItemSize = uxItemSize;
|
|
800df7c: 69bb ldr r3, [r7, #24]
|
|
800df7e: 68ba ldr r2, [r7, #8]
|
|
800df80: 641a str r2, [r3, #64] ; 0x40
|
|
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
|
|
800df82: 2101 movs r1, #1
|
|
800df84: 69b8 ldr r0, [r7, #24]
|
|
800df86: f7ff febd bl 800dd04 <xQueueGenericReset>
|
|
pxNewQueue->pxQueueSetContainer = NULL;
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
traceQUEUE_CREATE( pxNewQueue );
|
|
}
|
|
800df8a: bf00 nop
|
|
800df8c: 3710 adds r7, #16
|
|
800df8e: 46bd mov sp, r7
|
|
800df90: bd80 pop {r7, pc}
|
|
|
|
0800df92 <prvInitialiseMutex>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_MUTEXES == 1 )
|
|
|
|
static void prvInitialiseMutex( Queue_t *pxNewQueue )
|
|
{
|
|
800df92: b580 push {r7, lr}
|
|
800df94: b082 sub sp, #8
|
|
800df96: af00 add r7, sp, #0
|
|
800df98: 6078 str r0, [r7, #4]
|
|
if( pxNewQueue != NULL )
|
|
800df9a: 687b ldr r3, [r7, #4]
|
|
800df9c: 2b00 cmp r3, #0
|
|
800df9e: d00e beq.n 800dfbe <prvInitialiseMutex+0x2c>
|
|
{
|
|
/* The queue create function will set all the queue structure members
|
|
correctly for a generic queue, but this function is creating a
|
|
mutex. Overwrite those members that need to be set differently -
|
|
in particular the information required for priority inheritance. */
|
|
pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
800dfa0: 687b ldr r3, [r7, #4]
|
|
800dfa2: 2200 movs r2, #0
|
|
800dfa4: 609a str r2, [r3, #8]
|
|
pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
|
|
800dfa6: 687b ldr r3, [r7, #4]
|
|
800dfa8: 2200 movs r2, #0
|
|
800dfaa: 601a str r2, [r3, #0]
|
|
|
|
/* In case this is a recursive mutex. */
|
|
pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
|
|
800dfac: 687b ldr r3, [r7, #4]
|
|
800dfae: 2200 movs r2, #0
|
|
800dfb0: 60da str r2, [r3, #12]
|
|
|
|
traceCREATE_MUTEX( pxNewQueue );
|
|
|
|
/* Start with the semaphore in the expected state. */
|
|
( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
|
|
800dfb2: 2300 movs r3, #0
|
|
800dfb4: 2200 movs r2, #0
|
|
800dfb6: 2100 movs r1, #0
|
|
800dfb8: 6878 ldr r0, [r7, #4]
|
|
800dfba: f000 f8a5 bl 800e108 <xQueueGenericSend>
|
|
}
|
|
else
|
|
{
|
|
traceCREATE_MUTEX_FAILED();
|
|
}
|
|
}
|
|
800dfbe: bf00 nop
|
|
800dfc0: 3708 adds r7, #8
|
|
800dfc2: 46bd mov sp, r7
|
|
800dfc4: bd80 pop {r7, pc}
|
|
|
|
0800dfc6 <xQueueCreateMutex>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
|
|
{
|
|
800dfc6: b580 push {r7, lr}
|
|
800dfc8: b086 sub sp, #24
|
|
800dfca: af00 add r7, sp, #0
|
|
800dfcc: 4603 mov r3, r0
|
|
800dfce: 71fb strb r3, [r7, #7]
|
|
QueueHandle_t xNewQueue;
|
|
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
|
|
800dfd0: 2301 movs r3, #1
|
|
800dfd2: 617b str r3, [r7, #20]
|
|
800dfd4: 2300 movs r3, #0
|
|
800dfd6: 613b str r3, [r7, #16]
|
|
|
|
xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
|
|
800dfd8: 79fb ldrb r3, [r7, #7]
|
|
800dfda: 461a mov r2, r3
|
|
800dfdc: 6939 ldr r1, [r7, #16]
|
|
800dfde: 6978 ldr r0, [r7, #20]
|
|
800dfe0: f7ff ff77 bl 800ded2 <xQueueGenericCreate>
|
|
800dfe4: 60f8 str r0, [r7, #12]
|
|
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
|
|
800dfe6: 68f8 ldr r0, [r7, #12]
|
|
800dfe8: f7ff ffd3 bl 800df92 <prvInitialiseMutex>
|
|
|
|
return xNewQueue;
|
|
800dfec: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800dfee: 4618 mov r0, r3
|
|
800dff0: 3718 adds r7, #24
|
|
800dff2: 46bd mov sp, r7
|
|
800dff4: bd80 pop {r7, pc}
|
|
|
|
0800dff6 <xQueueCreateMutexStatic>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
|
|
{
|
|
800dff6: b580 push {r7, lr}
|
|
800dff8: b088 sub sp, #32
|
|
800dffa: af02 add r7, sp, #8
|
|
800dffc: 4603 mov r3, r0
|
|
800dffe: 6039 str r1, [r7, #0]
|
|
800e000: 71fb strb r3, [r7, #7]
|
|
QueueHandle_t xNewQueue;
|
|
const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
|
|
800e002: 2301 movs r3, #1
|
|
800e004: 617b str r3, [r7, #20]
|
|
800e006: 2300 movs r3, #0
|
|
800e008: 613b str r3, [r7, #16]
|
|
|
|
/* Prevent compiler warnings about unused parameters if
|
|
configUSE_TRACE_FACILITY does not equal 1. */
|
|
( void ) ucQueueType;
|
|
|
|
xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
|
|
800e00a: 79fb ldrb r3, [r7, #7]
|
|
800e00c: 9300 str r3, [sp, #0]
|
|
800e00e: 683b ldr r3, [r7, #0]
|
|
800e010: 2200 movs r2, #0
|
|
800e012: 6939 ldr r1, [r7, #16]
|
|
800e014: 6978 ldr r0, [r7, #20]
|
|
800e016: f7ff fedf bl 800ddd8 <xQueueGenericCreateStatic>
|
|
800e01a: 60f8 str r0, [r7, #12]
|
|
prvInitialiseMutex( ( Queue_t * ) xNewQueue );
|
|
800e01c: 68f8 ldr r0, [r7, #12]
|
|
800e01e: f7ff ffb8 bl 800df92 <prvInitialiseMutex>
|
|
|
|
return xNewQueue;
|
|
800e022: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800e024: 4618 mov r0, r3
|
|
800e026: 3718 adds r7, #24
|
|
800e028: 46bd mov sp, r7
|
|
800e02a: bd80 pop {r7, pc}
|
|
|
|
0800e02c <xQueueCreateCountingSemaphoreStatic>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
|
|
{
|
|
800e02c: b580 push {r7, lr}
|
|
800e02e: b08a sub sp, #40 ; 0x28
|
|
800e030: af02 add r7, sp, #8
|
|
800e032: 60f8 str r0, [r7, #12]
|
|
800e034: 60b9 str r1, [r7, #8]
|
|
800e036: 607a str r2, [r7, #4]
|
|
QueueHandle_t xHandle;
|
|
|
|
configASSERT( uxMaxCount != 0 );
|
|
800e038: 68fb ldr r3, [r7, #12]
|
|
800e03a: 2b00 cmp r3, #0
|
|
800e03c: d10b bne.n 800e056 <xQueueCreateCountingSemaphoreStatic+0x2a>
|
|
800e03e: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e042: b672 cpsid i
|
|
800e044: f383 8811 msr BASEPRI, r3
|
|
800e048: f3bf 8f6f isb sy
|
|
800e04c: f3bf 8f4f dsb sy
|
|
800e050: b662 cpsie i
|
|
800e052: 61bb str r3, [r7, #24]
|
|
800e054: e7fe b.n 800e054 <xQueueCreateCountingSemaphoreStatic+0x28>
|
|
configASSERT( uxInitialCount <= uxMaxCount );
|
|
800e056: 68ba ldr r2, [r7, #8]
|
|
800e058: 68fb ldr r3, [r7, #12]
|
|
800e05a: 429a cmp r2, r3
|
|
800e05c: d90b bls.n 800e076 <xQueueCreateCountingSemaphoreStatic+0x4a>
|
|
800e05e: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e062: b672 cpsid i
|
|
800e064: f383 8811 msr BASEPRI, r3
|
|
800e068: f3bf 8f6f isb sy
|
|
800e06c: f3bf 8f4f dsb sy
|
|
800e070: b662 cpsie i
|
|
800e072: 617b str r3, [r7, #20]
|
|
800e074: e7fe b.n 800e074 <xQueueCreateCountingSemaphoreStatic+0x48>
|
|
|
|
xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
|
|
800e076: 2302 movs r3, #2
|
|
800e078: 9300 str r3, [sp, #0]
|
|
800e07a: 687b ldr r3, [r7, #4]
|
|
800e07c: 2200 movs r2, #0
|
|
800e07e: 2100 movs r1, #0
|
|
800e080: 68f8 ldr r0, [r7, #12]
|
|
800e082: f7ff fea9 bl 800ddd8 <xQueueGenericCreateStatic>
|
|
800e086: 61f8 str r0, [r7, #28]
|
|
|
|
if( xHandle != NULL )
|
|
800e088: 69fb ldr r3, [r7, #28]
|
|
800e08a: 2b00 cmp r3, #0
|
|
800e08c: d002 beq.n 800e094 <xQueueCreateCountingSemaphoreStatic+0x68>
|
|
{
|
|
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
|
|
800e08e: 69fb ldr r3, [r7, #28]
|
|
800e090: 68ba ldr r2, [r7, #8]
|
|
800e092: 639a str r2, [r3, #56] ; 0x38
|
|
else
|
|
{
|
|
traceCREATE_COUNTING_SEMAPHORE_FAILED();
|
|
}
|
|
|
|
return xHandle;
|
|
800e094: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800e096: 4618 mov r0, r3
|
|
800e098: 3720 adds r7, #32
|
|
800e09a: 46bd mov sp, r7
|
|
800e09c: bd80 pop {r7, pc}
|
|
|
|
0800e09e <xQueueCreateCountingSemaphore>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
|
|
|
QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
|
|
{
|
|
800e09e: b580 push {r7, lr}
|
|
800e0a0: b086 sub sp, #24
|
|
800e0a2: af00 add r7, sp, #0
|
|
800e0a4: 6078 str r0, [r7, #4]
|
|
800e0a6: 6039 str r1, [r7, #0]
|
|
QueueHandle_t xHandle;
|
|
|
|
configASSERT( uxMaxCount != 0 );
|
|
800e0a8: 687b ldr r3, [r7, #4]
|
|
800e0aa: 2b00 cmp r3, #0
|
|
800e0ac: d10b bne.n 800e0c6 <xQueueCreateCountingSemaphore+0x28>
|
|
800e0ae: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e0b2: b672 cpsid i
|
|
800e0b4: f383 8811 msr BASEPRI, r3
|
|
800e0b8: f3bf 8f6f isb sy
|
|
800e0bc: f3bf 8f4f dsb sy
|
|
800e0c0: b662 cpsie i
|
|
800e0c2: 613b str r3, [r7, #16]
|
|
800e0c4: e7fe b.n 800e0c4 <xQueueCreateCountingSemaphore+0x26>
|
|
configASSERT( uxInitialCount <= uxMaxCount );
|
|
800e0c6: 683a ldr r2, [r7, #0]
|
|
800e0c8: 687b ldr r3, [r7, #4]
|
|
800e0ca: 429a cmp r2, r3
|
|
800e0cc: d90b bls.n 800e0e6 <xQueueCreateCountingSemaphore+0x48>
|
|
800e0ce: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e0d2: b672 cpsid i
|
|
800e0d4: f383 8811 msr BASEPRI, r3
|
|
800e0d8: f3bf 8f6f isb sy
|
|
800e0dc: f3bf 8f4f dsb sy
|
|
800e0e0: b662 cpsie i
|
|
800e0e2: 60fb str r3, [r7, #12]
|
|
800e0e4: e7fe b.n 800e0e4 <xQueueCreateCountingSemaphore+0x46>
|
|
|
|
xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
|
|
800e0e6: 2202 movs r2, #2
|
|
800e0e8: 2100 movs r1, #0
|
|
800e0ea: 6878 ldr r0, [r7, #4]
|
|
800e0ec: f7ff fef1 bl 800ded2 <xQueueGenericCreate>
|
|
800e0f0: 6178 str r0, [r7, #20]
|
|
|
|
if( xHandle != NULL )
|
|
800e0f2: 697b ldr r3, [r7, #20]
|
|
800e0f4: 2b00 cmp r3, #0
|
|
800e0f6: d002 beq.n 800e0fe <xQueueCreateCountingSemaphore+0x60>
|
|
{
|
|
( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
|
|
800e0f8: 697b ldr r3, [r7, #20]
|
|
800e0fa: 683a ldr r2, [r7, #0]
|
|
800e0fc: 639a str r2, [r3, #56] ; 0x38
|
|
else
|
|
{
|
|
traceCREATE_COUNTING_SEMAPHORE_FAILED();
|
|
}
|
|
|
|
return xHandle;
|
|
800e0fe: 697b ldr r3, [r7, #20]
|
|
}
|
|
800e100: 4618 mov r0, r3
|
|
800e102: 3718 adds r7, #24
|
|
800e104: 46bd mov sp, r7
|
|
800e106: bd80 pop {r7, pc}
|
|
|
|
0800e108 <xQueueGenericSend>:
|
|
|
|
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
|
|
{
|
|
800e108: b580 push {r7, lr}
|
|
800e10a: b08e sub sp, #56 ; 0x38
|
|
800e10c: af00 add r7, sp, #0
|
|
800e10e: 60f8 str r0, [r7, #12]
|
|
800e110: 60b9 str r1, [r7, #8]
|
|
800e112: 607a str r2, [r7, #4]
|
|
800e114: 603b str r3, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
|
800e116: 2300 movs r3, #0
|
|
800e118: 637b str r3, [r7, #52] ; 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e11a: 68fb ldr r3, [r7, #12]
|
|
800e11c: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800e11e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e120: 2b00 cmp r3, #0
|
|
800e122: d10b bne.n 800e13c <xQueueGenericSend+0x34>
|
|
800e124: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e128: b672 cpsid i
|
|
800e12a: f383 8811 msr BASEPRI, r3
|
|
800e12e: f3bf 8f6f isb sy
|
|
800e132: f3bf 8f4f dsb sy
|
|
800e136: b662 cpsie i
|
|
800e138: 62bb str r3, [r7, #40] ; 0x28
|
|
800e13a: e7fe b.n 800e13a <xQueueGenericSend+0x32>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800e13c: 68bb ldr r3, [r7, #8]
|
|
800e13e: 2b00 cmp r3, #0
|
|
800e140: d103 bne.n 800e14a <xQueueGenericSend+0x42>
|
|
800e142: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e144: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e146: 2b00 cmp r3, #0
|
|
800e148: d101 bne.n 800e14e <xQueueGenericSend+0x46>
|
|
800e14a: 2301 movs r3, #1
|
|
800e14c: e000 b.n 800e150 <xQueueGenericSend+0x48>
|
|
800e14e: 2300 movs r3, #0
|
|
800e150: 2b00 cmp r3, #0
|
|
800e152: d10b bne.n 800e16c <xQueueGenericSend+0x64>
|
|
800e154: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e158: b672 cpsid i
|
|
800e15a: f383 8811 msr BASEPRI, r3
|
|
800e15e: f3bf 8f6f isb sy
|
|
800e162: f3bf 8f4f dsb sy
|
|
800e166: b662 cpsie i
|
|
800e168: 627b str r3, [r7, #36] ; 0x24
|
|
800e16a: e7fe b.n 800e16a <xQueueGenericSend+0x62>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800e16c: 683b ldr r3, [r7, #0]
|
|
800e16e: 2b02 cmp r3, #2
|
|
800e170: d103 bne.n 800e17a <xQueueGenericSend+0x72>
|
|
800e172: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e174: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800e176: 2b01 cmp r3, #1
|
|
800e178: d101 bne.n 800e17e <xQueueGenericSend+0x76>
|
|
800e17a: 2301 movs r3, #1
|
|
800e17c: e000 b.n 800e180 <xQueueGenericSend+0x78>
|
|
800e17e: 2300 movs r3, #0
|
|
800e180: 2b00 cmp r3, #0
|
|
800e182: d10b bne.n 800e19c <xQueueGenericSend+0x94>
|
|
800e184: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e188: b672 cpsid i
|
|
800e18a: f383 8811 msr BASEPRI, r3
|
|
800e18e: f3bf 8f6f isb sy
|
|
800e192: f3bf 8f4f dsb sy
|
|
800e196: b662 cpsie i
|
|
800e198: 623b str r3, [r7, #32]
|
|
800e19a: e7fe b.n 800e19a <xQueueGenericSend+0x92>
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800e19c: f001 fcbc bl 800fb18 <xTaskGetSchedulerState>
|
|
800e1a0: 4603 mov r3, r0
|
|
800e1a2: 2b00 cmp r3, #0
|
|
800e1a4: d102 bne.n 800e1ac <xQueueGenericSend+0xa4>
|
|
800e1a6: 687b ldr r3, [r7, #4]
|
|
800e1a8: 2b00 cmp r3, #0
|
|
800e1aa: d101 bne.n 800e1b0 <xQueueGenericSend+0xa8>
|
|
800e1ac: 2301 movs r3, #1
|
|
800e1ae: e000 b.n 800e1b2 <xQueueGenericSend+0xaa>
|
|
800e1b0: 2300 movs r3, #0
|
|
800e1b2: 2b00 cmp r3, #0
|
|
800e1b4: d10b bne.n 800e1ce <xQueueGenericSend+0xc6>
|
|
800e1b6: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e1ba: b672 cpsid i
|
|
800e1bc: f383 8811 msr BASEPRI, r3
|
|
800e1c0: f3bf 8f6f isb sy
|
|
800e1c4: f3bf 8f4f dsb sy
|
|
800e1c8: b662 cpsie i
|
|
800e1ca: 61fb str r3, [r7, #28]
|
|
800e1cc: e7fe b.n 800e1cc <xQueueGenericSend+0xc4>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800e1ce: f001 ffeb bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
/* Is there room on the queue now? The running task must be the
|
|
highest priority task wanting to access the queue. If the head item
|
|
in the queue is to be overwritten then it does not matter if the
|
|
queue is full. */
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800e1d2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e1d4: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
800e1d6: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e1d8: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800e1da: 429a cmp r2, r3
|
|
800e1dc: d302 bcc.n 800e1e4 <xQueueGenericSend+0xdc>
|
|
800e1de: 683b ldr r3, [r7, #0]
|
|
800e1e0: 2b02 cmp r3, #2
|
|
800e1e2: d129 bne.n 800e238 <xQueueGenericSend+0x130>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800e1e4: 683a ldr r2, [r7, #0]
|
|
800e1e6: 68b9 ldr r1, [r7, #8]
|
|
800e1e8: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e1ea: f000 fc4a bl 800ea82 <prvCopyDataToQueue>
|
|
800e1ee: 62f8 str r0, [r7, #44] ; 0x2c
|
|
|
|
/* If there was a task waiting for data to arrive on the
|
|
queue then unblock it now. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800e1f0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e1f2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800e1f4: 2b00 cmp r3, #0
|
|
800e1f6: d010 beq.n 800e21a <xQueueGenericSend+0x112>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800e1f8: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e1fa: 3324 adds r3, #36 ; 0x24
|
|
800e1fc: 4618 mov r0, r3
|
|
800e1fe: f001 facb bl 800f798 <xTaskRemoveFromEventList>
|
|
800e202: 4603 mov r3, r0
|
|
800e204: 2b00 cmp r3, #0
|
|
800e206: d013 beq.n 800e230 <xQueueGenericSend+0x128>
|
|
{
|
|
/* The unblocked task has a priority higher than
|
|
our own so yield immediately. Yes it is ok to do
|
|
this from within the critical section - the kernel
|
|
takes care of that. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800e208: 4b3f ldr r3, [pc, #252] ; (800e308 <xQueueGenericSend+0x200>)
|
|
800e20a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e20e: 601a str r2, [r3, #0]
|
|
800e210: f3bf 8f4f dsb sy
|
|
800e214: f3bf 8f6f isb sy
|
|
800e218: e00a b.n 800e230 <xQueueGenericSend+0x128>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else if( xYieldRequired != pdFALSE )
|
|
800e21a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e21c: 2b00 cmp r3, #0
|
|
800e21e: d007 beq.n 800e230 <xQueueGenericSend+0x128>
|
|
{
|
|
/* This path is a special case that will only get
|
|
executed if the task was holding multiple mutexes and
|
|
the mutexes were given back in an order that is
|
|
different to that in which they were taken. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800e220: 4b39 ldr r3, [pc, #228] ; (800e308 <xQueueGenericSend+0x200>)
|
|
800e222: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e226: 601a str r2, [r3, #0]
|
|
800e228: f3bf 8f4f dsb sy
|
|
800e22c: f3bf 8f6f isb sy
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
taskEXIT_CRITICAL();
|
|
800e230: f001 ffec bl 801020c <vPortExitCritical>
|
|
return pdPASS;
|
|
800e234: 2301 movs r3, #1
|
|
800e236: e063 b.n 800e300 <xQueueGenericSend+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800e238: 687b ldr r3, [r7, #4]
|
|
800e23a: 2b00 cmp r3, #0
|
|
800e23c: d103 bne.n 800e246 <xQueueGenericSend+0x13e>
|
|
{
|
|
/* The queue was full and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800e23e: f001 ffe5 bl 801020c <vPortExitCritical>
|
|
|
|
/* Return to the original privilege level before exiting
|
|
the function. */
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800e242: 2300 movs r3, #0
|
|
800e244: e05c b.n 800e300 <xQueueGenericSend+0x1f8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800e246: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
800e248: 2b00 cmp r3, #0
|
|
800e24a: d106 bne.n 800e25a <xQueueGenericSend+0x152>
|
|
{
|
|
/* The queue was full and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800e24c: f107 0314 add.w r3, r7, #20
|
|
800e250: 4618 mov r0, r3
|
|
800e252: f001 fb05 bl 800f860 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800e256: 2301 movs r3, #1
|
|
800e258: 637b str r3, [r7, #52] ; 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e25a: f001 ffd7 bl 801020c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800e25e: f001 f86b bl 800f338 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800e262: f001 ffa1 bl 80101a8 <vPortEnterCritical>
|
|
800e266: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e268: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800e26c: b25b sxtb r3, r3
|
|
800e26e: f1b3 3fff cmp.w r3, #4294967295
|
|
800e272: d103 bne.n 800e27c <xQueueGenericSend+0x174>
|
|
800e274: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e276: 2200 movs r2, #0
|
|
800e278: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
800e27c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e27e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800e282: b25b sxtb r3, r3
|
|
800e284: f1b3 3fff cmp.w r3, #4294967295
|
|
800e288: d103 bne.n 800e292 <xQueueGenericSend+0x18a>
|
|
800e28a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e28c: 2200 movs r2, #0
|
|
800e28e: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
800e292: f001 ffbb bl 801020c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800e296: 1d3a adds r2, r7, #4
|
|
800e298: f107 0314 add.w r3, r7, #20
|
|
800e29c: 4611 mov r1, r2
|
|
800e29e: 4618 mov r0, r3
|
|
800e2a0: f001 faf4 bl 800f88c <xTaskCheckForTimeOut>
|
|
800e2a4: 4603 mov r3, r0
|
|
800e2a6: 2b00 cmp r3, #0
|
|
800e2a8: d124 bne.n 800e2f4 <xQueueGenericSend+0x1ec>
|
|
{
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
|
800e2aa: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e2ac: f000 fce1 bl 800ec72 <prvIsQueueFull>
|
|
800e2b0: 4603 mov r3, r0
|
|
800e2b2: 2b00 cmp r3, #0
|
|
800e2b4: d018 beq.n 800e2e8 <xQueueGenericSend+0x1e0>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
|
800e2b6: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e2b8: 3310 adds r3, #16
|
|
800e2ba: 687a ldr r2, [r7, #4]
|
|
800e2bc: 4611 mov r1, r2
|
|
800e2be: 4618 mov r0, r3
|
|
800e2c0: f001 fa44 bl 800f74c <vTaskPlaceOnEventList>
|
|
/* Unlocking the queue means queue events can effect the
|
|
event list. It is possible that interrupts occurring now
|
|
remove this task from the event list again - but as the
|
|
scheduler is suspended the task will go onto the pending
|
|
ready last instead of the actual ready list. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e2c4: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e2c6: f000 fc6c bl 800eba2 <prvUnlockQueue>
|
|
/* Resuming the scheduler will move tasks from the pending
|
|
ready list into the ready list - so it is feasible that this
|
|
task is already in a ready list before it yields - in which
|
|
case the yield will not cause a context switch unless there
|
|
is also a higher priority task in the pending ready list. */
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800e2ca: f001 f843 bl 800f354 <xTaskResumeAll>
|
|
800e2ce: 4603 mov r3, r0
|
|
800e2d0: 2b00 cmp r3, #0
|
|
800e2d2: f47f af7c bne.w 800e1ce <xQueueGenericSend+0xc6>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800e2d6: 4b0c ldr r3, [pc, #48] ; (800e308 <xQueueGenericSend+0x200>)
|
|
800e2d8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e2dc: 601a str r2, [r3, #0]
|
|
800e2de: f3bf 8f4f dsb sy
|
|
800e2e2: f3bf 8f6f isb sy
|
|
800e2e6: e772 b.n 800e1ce <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Try again. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e2e8: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e2ea: f000 fc5a bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e2ee: f001 f831 bl 800f354 <xTaskResumeAll>
|
|
800e2f2: e76c b.n 800e1ce <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The timeout has expired. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e2f4: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e2f6: f000 fc54 bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e2fa: f001 f82b bl 800f354 <xTaskResumeAll>
|
|
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800e2fe: 2300 movs r3, #0
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800e300: 4618 mov r0, r3
|
|
800e302: 3738 adds r7, #56 ; 0x38
|
|
800e304: 46bd mov sp, r7
|
|
800e306: bd80 pop {r7, pc}
|
|
800e308: e000ed04 .word 0xe000ed04
|
|
|
|
0800e30c <xQueueGenericSendFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
|
|
{
|
|
800e30c: b580 push {r7, lr}
|
|
800e30e: b08e sub sp, #56 ; 0x38
|
|
800e310: af00 add r7, sp, #0
|
|
800e312: 60f8 str r0, [r7, #12]
|
|
800e314: 60b9 str r1, [r7, #8]
|
|
800e316: 607a str r2, [r7, #4]
|
|
800e318: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e31a: 68fb ldr r3, [r7, #12]
|
|
800e31c: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800e31e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e320: 2b00 cmp r3, #0
|
|
800e322: d10b bne.n 800e33c <xQueueGenericSendFromISR+0x30>
|
|
800e324: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e328: b672 cpsid i
|
|
800e32a: f383 8811 msr BASEPRI, r3
|
|
800e32e: f3bf 8f6f isb sy
|
|
800e332: f3bf 8f4f dsb sy
|
|
800e336: b662 cpsie i
|
|
800e338: 627b str r3, [r7, #36] ; 0x24
|
|
800e33a: e7fe b.n 800e33a <xQueueGenericSendFromISR+0x2e>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800e33c: 68bb ldr r3, [r7, #8]
|
|
800e33e: 2b00 cmp r3, #0
|
|
800e340: d103 bne.n 800e34a <xQueueGenericSendFromISR+0x3e>
|
|
800e342: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e344: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e346: 2b00 cmp r3, #0
|
|
800e348: d101 bne.n 800e34e <xQueueGenericSendFromISR+0x42>
|
|
800e34a: 2301 movs r3, #1
|
|
800e34c: e000 b.n 800e350 <xQueueGenericSendFromISR+0x44>
|
|
800e34e: 2300 movs r3, #0
|
|
800e350: 2b00 cmp r3, #0
|
|
800e352: d10b bne.n 800e36c <xQueueGenericSendFromISR+0x60>
|
|
800e354: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e358: b672 cpsid i
|
|
800e35a: f383 8811 msr BASEPRI, r3
|
|
800e35e: f3bf 8f6f isb sy
|
|
800e362: f3bf 8f4f dsb sy
|
|
800e366: b662 cpsie i
|
|
800e368: 623b str r3, [r7, #32]
|
|
800e36a: e7fe b.n 800e36a <xQueueGenericSendFromISR+0x5e>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800e36c: 683b ldr r3, [r7, #0]
|
|
800e36e: 2b02 cmp r3, #2
|
|
800e370: d103 bne.n 800e37a <xQueueGenericSendFromISR+0x6e>
|
|
800e372: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e374: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800e376: 2b01 cmp r3, #1
|
|
800e378: d101 bne.n 800e37e <xQueueGenericSendFromISR+0x72>
|
|
800e37a: 2301 movs r3, #1
|
|
800e37c: e000 b.n 800e380 <xQueueGenericSendFromISR+0x74>
|
|
800e37e: 2300 movs r3, #0
|
|
800e380: 2b00 cmp r3, #0
|
|
800e382: d10b bne.n 800e39c <xQueueGenericSendFromISR+0x90>
|
|
800e384: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e388: b672 cpsid i
|
|
800e38a: f383 8811 msr BASEPRI, r3
|
|
800e38e: f3bf 8f6f isb sy
|
|
800e392: f3bf 8f4f dsb sy
|
|
800e396: b662 cpsie i
|
|
800e398: 61fb str r3, [r7, #28]
|
|
800e39a: e7fe b.n 800e39a <xQueueGenericSendFromISR+0x8e>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800e39c: f001 ffe4 bl 8010368 <vPortValidateInterruptPriority>
|
|
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800e3a0: f3ef 8211 mrs r2, BASEPRI
|
|
800e3a4: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e3a8: b672 cpsid i
|
|
800e3aa: f383 8811 msr BASEPRI, r3
|
|
800e3ae: f3bf 8f6f isb sy
|
|
800e3b2: f3bf 8f4f dsb sy
|
|
800e3b6: b662 cpsie i
|
|
800e3b8: 61ba str r2, [r7, #24]
|
|
800e3ba: 617b str r3, [r7, #20]
|
|
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
|
|
/* This return will not be reached but is necessary to prevent compiler
|
|
warnings. */
|
|
return ulOriginalBASEPRI;
|
|
800e3bc: 69bb ldr r3, [r7, #24]
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
|
in the queue. Also don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800e3be: 62fb str r3, [r7, #44] ; 0x2c
|
|
{
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800e3c0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e3c2: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
800e3c4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e3c6: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800e3c8: 429a cmp r2, r3
|
|
800e3ca: d302 bcc.n 800e3d2 <xQueueGenericSendFromISR+0xc6>
|
|
800e3cc: 683b ldr r3, [r7, #0]
|
|
800e3ce: 2b02 cmp r3, #2
|
|
800e3d0: d12c bne.n 800e42c <xQueueGenericSendFromISR+0x120>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
800e3d2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e3d4: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800e3d8: f887 302b strb.w r3, [r7, #43] ; 0x2b
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
|
semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
|
in a task disinheriting a priority and prvCopyDataToQueue() can be
|
|
called here even though the disinherit function does not check if
|
|
the scheduler is suspended before accessing the ready lists. */
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800e3dc: 683a ldr r2, [r7, #0]
|
|
800e3de: 68b9 ldr r1, [r7, #8]
|
|
800e3e0: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e3e2: f000 fb4e bl 800ea82 <prvCopyDataToQueue>
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
800e3e6: f997 302b ldrsb.w r3, [r7, #43] ; 0x2b
|
|
800e3ea: f1b3 3fff cmp.w r3, #4294967295
|
|
800e3ee: d112 bne.n 800e416 <xQueueGenericSendFromISR+0x10a>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800e3f0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e3f2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800e3f4: 2b00 cmp r3, #0
|
|
800e3f6: d016 beq.n 800e426 <xQueueGenericSendFromISR+0x11a>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800e3f8: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e3fa: 3324 adds r3, #36 ; 0x24
|
|
800e3fc: 4618 mov r0, r3
|
|
800e3fe: f001 f9cb bl 800f798 <xTaskRemoveFromEventList>
|
|
800e402: 4603 mov r3, r0
|
|
800e404: 2b00 cmp r3, #0
|
|
800e406: d00e beq.n 800e426 <xQueueGenericSendFromISR+0x11a>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800e408: 687b ldr r3, [r7, #4]
|
|
800e40a: 2b00 cmp r3, #0
|
|
800e40c: d00b beq.n 800e426 <xQueueGenericSendFromISR+0x11a>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800e40e: 687b ldr r3, [r7, #4]
|
|
800e410: 2201 movs r2, #1
|
|
800e412: 601a str r2, [r3, #0]
|
|
800e414: e007 b.n 800e426 <xQueueGenericSendFromISR+0x11a>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
800e416: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
|
|
800e41a: 3301 adds r3, #1
|
|
800e41c: b2db uxtb r3, r3
|
|
800e41e: b25a sxtb r2, r3
|
|
800e420: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e422: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800e426: 2301 movs r3, #1
|
|
800e428: 637b str r3, [r7, #52] ; 0x34
|
|
{
|
|
800e42a: e001 b.n 800e430 <xQueueGenericSendFromISR+0x124>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800e42c: 2300 movs r3, #0
|
|
800e42e: 637b str r3, [r7, #52] ; 0x34
|
|
800e430: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e432: 613b str r3, [r7, #16]
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
{
|
|
__asm volatile
|
|
800e434: 693b ldr r3, [r7, #16]
|
|
800e436: f383 8811 msr BASEPRI, r3
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800e43a: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
}
|
|
800e43c: 4618 mov r0, r3
|
|
800e43e: 3738 adds r7, #56 ; 0x38
|
|
800e440: 46bd mov sp, r7
|
|
800e442: bd80 pop {r7, pc}
|
|
|
|
0800e444 <xQueueGiveFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
800e444: b580 push {r7, lr}
|
|
800e446: b08e sub sp, #56 ; 0x38
|
|
800e448: af00 add r7, sp, #0
|
|
800e44a: 6078 str r0, [r7, #4]
|
|
800e44c: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e44e: 687b ldr r3, [r7, #4]
|
|
800e450: 633b str r3, [r7, #48] ; 0x30
|
|
item size is 0. Don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
|
|
configASSERT( pxQueue );
|
|
800e452: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e454: 2b00 cmp r3, #0
|
|
800e456: d10b bne.n 800e470 <xQueueGiveFromISR+0x2c>
|
|
__asm volatile
|
|
800e458: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e45c: b672 cpsid i
|
|
800e45e: f383 8811 msr BASEPRI, r3
|
|
800e462: f3bf 8f6f isb sy
|
|
800e466: f3bf 8f4f dsb sy
|
|
800e46a: b662 cpsie i
|
|
800e46c: 623b str r3, [r7, #32]
|
|
800e46e: e7fe b.n 800e46e <xQueueGiveFromISR+0x2a>
|
|
|
|
/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
|
|
if the item size is not 0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
800e470: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e472: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e474: 2b00 cmp r3, #0
|
|
800e476: d00b beq.n 800e490 <xQueueGiveFromISR+0x4c>
|
|
800e478: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e47c: b672 cpsid i
|
|
800e47e: f383 8811 msr BASEPRI, r3
|
|
800e482: f3bf 8f6f isb sy
|
|
800e486: f3bf 8f4f dsb sy
|
|
800e48a: b662 cpsie i
|
|
800e48c: 61fb str r3, [r7, #28]
|
|
800e48e: e7fe b.n 800e48e <xQueueGiveFromISR+0x4a>
|
|
|
|
/* Normally a mutex would not be given from an interrupt, especially if
|
|
there is a mutex holder, as priority inheritance makes no sense for an
|
|
interrupts, only tasks. */
|
|
configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
|
|
800e490: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e492: 681b ldr r3, [r3, #0]
|
|
800e494: 2b00 cmp r3, #0
|
|
800e496: d103 bne.n 800e4a0 <xQueueGiveFromISR+0x5c>
|
|
800e498: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e49a: 689b ldr r3, [r3, #8]
|
|
800e49c: 2b00 cmp r3, #0
|
|
800e49e: d101 bne.n 800e4a4 <xQueueGiveFromISR+0x60>
|
|
800e4a0: 2301 movs r3, #1
|
|
800e4a2: e000 b.n 800e4a6 <xQueueGiveFromISR+0x62>
|
|
800e4a4: 2300 movs r3, #0
|
|
800e4a6: 2b00 cmp r3, #0
|
|
800e4a8: d10b bne.n 800e4c2 <xQueueGiveFromISR+0x7e>
|
|
800e4aa: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e4ae: b672 cpsid i
|
|
800e4b0: f383 8811 msr BASEPRI, r3
|
|
800e4b4: f3bf 8f6f isb sy
|
|
800e4b8: f3bf 8f4f dsb sy
|
|
800e4bc: b662 cpsie i
|
|
800e4be: 61bb str r3, [r7, #24]
|
|
800e4c0: e7fe b.n 800e4c0 <xQueueGiveFromISR+0x7c>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800e4c2: f001 ff51 bl 8010368 <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
800e4c6: f3ef 8211 mrs r2, BASEPRI
|
|
800e4ca: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e4ce: b672 cpsid i
|
|
800e4d0: f383 8811 msr BASEPRI, r3
|
|
800e4d4: f3bf 8f6f isb sy
|
|
800e4d8: f3bf 8f4f dsb sy
|
|
800e4dc: b662 cpsie i
|
|
800e4de: 617a str r2, [r7, #20]
|
|
800e4e0: 613b str r3, [r7, #16]
|
|
return ulOriginalBASEPRI;
|
|
800e4e2: 697b ldr r3, [r7, #20]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800e4e4: 62fb str r3, [r7, #44] ; 0x2c
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800e4e6: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e4e8: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800e4ea: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
/* When the queue is used to implement a semaphore no data is ever
|
|
moved through the queue but it is still valid to see if the queue 'has
|
|
space'. */
|
|
if( uxMessagesWaiting < pxQueue->uxLength )
|
|
800e4ec: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e4ee: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800e4f0: 6aba ldr r2, [r7, #40] ; 0x28
|
|
800e4f2: 429a cmp r2, r3
|
|
800e4f4: d22b bcs.n 800e54e <xQueueGiveFromISR+0x10a>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
800e4f6: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e4f8: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800e4fc: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
holder - and if there is a mutex holder then the mutex cannot be
|
|
given from an ISR. As this is the ISR version of the function it
|
|
can be assumed there is no mutex holder and no need to determine if
|
|
priority disinheritance is needed. Simply increase the count of
|
|
messages (semaphores) available. */
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
800e500: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e502: 1c5a adds r2, r3, #1
|
|
800e504: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e506: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
800e508: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
800e50c: f1b3 3fff cmp.w r3, #4294967295
|
|
800e510: d112 bne.n 800e538 <xQueueGiveFromISR+0xf4>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800e512: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e514: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800e516: 2b00 cmp r3, #0
|
|
800e518: d016 beq.n 800e548 <xQueueGiveFromISR+0x104>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800e51a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e51c: 3324 adds r3, #36 ; 0x24
|
|
800e51e: 4618 mov r0, r3
|
|
800e520: f001 f93a bl 800f798 <xTaskRemoveFromEventList>
|
|
800e524: 4603 mov r3, r0
|
|
800e526: 2b00 cmp r3, #0
|
|
800e528: d00e beq.n 800e548 <xQueueGiveFromISR+0x104>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800e52a: 683b ldr r3, [r7, #0]
|
|
800e52c: 2b00 cmp r3, #0
|
|
800e52e: d00b beq.n 800e548 <xQueueGiveFromISR+0x104>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800e530: 683b ldr r3, [r7, #0]
|
|
800e532: 2201 movs r2, #1
|
|
800e534: 601a str r2, [r3, #0]
|
|
800e536: e007 b.n 800e548 <xQueueGiveFromISR+0x104>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
800e538: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
800e53c: 3301 adds r3, #1
|
|
800e53e: b2db uxtb r3, r3
|
|
800e540: b25a sxtb r2, r3
|
|
800e542: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e544: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800e548: 2301 movs r3, #1
|
|
800e54a: 637b str r3, [r7, #52] ; 0x34
|
|
800e54c: e001 b.n 800e552 <xQueueGiveFromISR+0x10e>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800e54e: 2300 movs r3, #0
|
|
800e550: 637b str r3, [r7, #52] ; 0x34
|
|
800e552: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e554: 60fb str r3, [r7, #12]
|
|
__asm volatile
|
|
800e556: 68fb ldr r3, [r7, #12]
|
|
800e558: f383 8811 msr BASEPRI, r3
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800e55c: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
}
|
|
800e55e: 4618 mov r0, r3
|
|
800e560: 3738 adds r7, #56 ; 0x38
|
|
800e562: 46bd mov sp, r7
|
|
800e564: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800e568 <xQueueReceive>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
|
|
{
|
|
800e568: b580 push {r7, lr}
|
|
800e56a: b08c sub sp, #48 ; 0x30
|
|
800e56c: af00 add r7, sp, #0
|
|
800e56e: 60f8 str r0, [r7, #12]
|
|
800e570: 60b9 str r1, [r7, #8]
|
|
800e572: 607a str r2, [r7, #4]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
800e574: 2300 movs r3, #0
|
|
800e576: 62fb str r3, [r7, #44] ; 0x2c
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e578: 68fb ldr r3, [r7, #12]
|
|
800e57a: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
/* Check the pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
800e57c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e57e: 2b00 cmp r3, #0
|
|
800e580: d10b bne.n 800e59a <xQueueReceive+0x32>
|
|
__asm volatile
|
|
800e582: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e586: b672 cpsid i
|
|
800e588: f383 8811 msr BASEPRI, r3
|
|
800e58c: f3bf 8f6f isb sy
|
|
800e590: f3bf 8f4f dsb sy
|
|
800e594: b662 cpsie i
|
|
800e596: 623b str r3, [r7, #32]
|
|
800e598: e7fe b.n 800e598 <xQueueReceive+0x30>
|
|
|
|
/* The buffer into which data is received can only be NULL if the data size
|
|
is zero (so no data is copied into the buffer. */
|
|
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800e59a: 68bb ldr r3, [r7, #8]
|
|
800e59c: 2b00 cmp r3, #0
|
|
800e59e: d103 bne.n 800e5a8 <xQueueReceive+0x40>
|
|
800e5a0: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e5a2: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e5a4: 2b00 cmp r3, #0
|
|
800e5a6: d101 bne.n 800e5ac <xQueueReceive+0x44>
|
|
800e5a8: 2301 movs r3, #1
|
|
800e5aa: e000 b.n 800e5ae <xQueueReceive+0x46>
|
|
800e5ac: 2300 movs r3, #0
|
|
800e5ae: 2b00 cmp r3, #0
|
|
800e5b0: d10b bne.n 800e5ca <xQueueReceive+0x62>
|
|
800e5b2: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e5b6: b672 cpsid i
|
|
800e5b8: f383 8811 msr BASEPRI, r3
|
|
800e5bc: f3bf 8f6f isb sy
|
|
800e5c0: f3bf 8f4f dsb sy
|
|
800e5c4: b662 cpsie i
|
|
800e5c6: 61fb str r3, [r7, #28]
|
|
800e5c8: e7fe b.n 800e5c8 <xQueueReceive+0x60>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800e5ca: f001 faa5 bl 800fb18 <xTaskGetSchedulerState>
|
|
800e5ce: 4603 mov r3, r0
|
|
800e5d0: 2b00 cmp r3, #0
|
|
800e5d2: d102 bne.n 800e5da <xQueueReceive+0x72>
|
|
800e5d4: 687b ldr r3, [r7, #4]
|
|
800e5d6: 2b00 cmp r3, #0
|
|
800e5d8: d101 bne.n 800e5de <xQueueReceive+0x76>
|
|
800e5da: 2301 movs r3, #1
|
|
800e5dc: e000 b.n 800e5e0 <xQueueReceive+0x78>
|
|
800e5de: 2300 movs r3, #0
|
|
800e5e0: 2b00 cmp r3, #0
|
|
800e5e2: d10b bne.n 800e5fc <xQueueReceive+0x94>
|
|
800e5e4: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e5e8: b672 cpsid i
|
|
800e5ea: f383 8811 msr BASEPRI, r3
|
|
800e5ee: f3bf 8f6f isb sy
|
|
800e5f2: f3bf 8f4f dsb sy
|
|
800e5f6: b662 cpsie i
|
|
800e5f8: 61bb str r3, [r7, #24]
|
|
800e5fa: e7fe b.n 800e5fa <xQueueReceive+0x92>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800e5fc: f001 fdd4 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800e600: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e602: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800e604: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
must be the highest priority task wanting to access the queue. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800e606: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800e608: 2b00 cmp r3, #0
|
|
800e60a: d01f beq.n 800e64c <xQueueReceive+0xe4>
|
|
{
|
|
/* Data available, remove one item. */
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
800e60c: 68b9 ldr r1, [r7, #8]
|
|
800e60e: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e610: f000 faa1 bl 800eb56 <prvCopyDataFromQueue>
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
800e614: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800e616: 1e5a subs r2, r3, #1
|
|
800e618: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e61a: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* There is now space in the queue, were any tasks waiting to
|
|
post to the queue? If so, unblock the highest priority waiting
|
|
task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800e61c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e61e: 691b ldr r3, [r3, #16]
|
|
800e620: 2b00 cmp r3, #0
|
|
800e622: d00f beq.n 800e644 <xQueueReceive+0xdc>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800e624: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e626: 3310 adds r3, #16
|
|
800e628: 4618 mov r0, r3
|
|
800e62a: f001 f8b5 bl 800f798 <xTaskRemoveFromEventList>
|
|
800e62e: 4603 mov r3, r0
|
|
800e630: 2b00 cmp r3, #0
|
|
800e632: d007 beq.n 800e644 <xQueueReceive+0xdc>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800e634: 4b3c ldr r3, [pc, #240] ; (800e728 <xQueueReceive+0x1c0>)
|
|
800e636: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e63a: 601a str r2, [r3, #0]
|
|
800e63c: f3bf 8f4f dsb sy
|
|
800e640: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
800e644: f001 fde2 bl 801020c <vPortExitCritical>
|
|
return pdPASS;
|
|
800e648: 2301 movs r3, #1
|
|
800e64a: e069 b.n 800e720 <xQueueReceive+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800e64c: 687b ldr r3, [r7, #4]
|
|
800e64e: 2b00 cmp r3, #0
|
|
800e650: d103 bne.n 800e65a <xQueueReceive+0xf2>
|
|
{
|
|
/* The queue was empty and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800e652: f001 fddb bl 801020c <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800e656: 2300 movs r3, #0
|
|
800e658: e062 b.n 800e720 <xQueueReceive+0x1b8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800e65a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e65c: 2b00 cmp r3, #0
|
|
800e65e: d106 bne.n 800e66e <xQueueReceive+0x106>
|
|
{
|
|
/* The queue was empty and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800e660: f107 0310 add.w r3, r7, #16
|
|
800e664: 4618 mov r0, r3
|
|
800e666: f001 f8fb bl 800f860 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800e66a: 2301 movs r3, #1
|
|
800e66c: 62fb str r3, [r7, #44] ; 0x2c
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e66e: f001 fdcd bl 801020c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800e672: f000 fe61 bl 800f338 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800e676: f001 fd97 bl 80101a8 <vPortEnterCritical>
|
|
800e67a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e67c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800e680: b25b sxtb r3, r3
|
|
800e682: f1b3 3fff cmp.w r3, #4294967295
|
|
800e686: d103 bne.n 800e690 <xQueueReceive+0x128>
|
|
800e688: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e68a: 2200 movs r2, #0
|
|
800e68c: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
800e690: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e692: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800e696: b25b sxtb r3, r3
|
|
800e698: f1b3 3fff cmp.w r3, #4294967295
|
|
800e69c: d103 bne.n 800e6a6 <xQueueReceive+0x13e>
|
|
800e69e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e6a0: 2200 movs r2, #0
|
|
800e6a2: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
800e6a6: f001 fdb1 bl 801020c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800e6aa: 1d3a adds r2, r7, #4
|
|
800e6ac: f107 0310 add.w r3, r7, #16
|
|
800e6b0: 4611 mov r1, r2
|
|
800e6b2: 4618 mov r0, r3
|
|
800e6b4: f001 f8ea bl 800f88c <xTaskCheckForTimeOut>
|
|
800e6b8: 4603 mov r3, r0
|
|
800e6ba: 2b00 cmp r3, #0
|
|
800e6bc: d123 bne.n 800e706 <xQueueReceive+0x19e>
|
|
{
|
|
/* The timeout has not expired. If the queue is still empty place
|
|
the task on the list of tasks waiting to receive from the queue. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800e6be: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e6c0: f000 fac1 bl 800ec46 <prvIsQueueEmpty>
|
|
800e6c4: 4603 mov r3, r0
|
|
800e6c6: 2b00 cmp r3, #0
|
|
800e6c8: d017 beq.n 800e6fa <xQueueReceive+0x192>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
800e6ca: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e6cc: 3324 adds r3, #36 ; 0x24
|
|
800e6ce: 687a ldr r2, [r7, #4]
|
|
800e6d0: 4611 mov r1, r2
|
|
800e6d2: 4618 mov r0, r3
|
|
800e6d4: f001 f83a bl 800f74c <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
800e6d8: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e6da: f000 fa62 bl 800eba2 <prvUnlockQueue>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800e6de: f000 fe39 bl 800f354 <xTaskResumeAll>
|
|
800e6e2: 4603 mov r3, r0
|
|
800e6e4: 2b00 cmp r3, #0
|
|
800e6e6: d189 bne.n 800e5fc <xQueueReceive+0x94>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800e6e8: 4b0f ldr r3, [pc, #60] ; (800e728 <xQueueReceive+0x1c0>)
|
|
800e6ea: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e6ee: 601a str r2, [r3, #0]
|
|
800e6f0: f3bf 8f4f dsb sy
|
|
800e6f4: f3bf 8f6f isb sy
|
|
800e6f8: e780 b.n 800e5fc <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* The queue contains data again. Loop back to try and read the
|
|
data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e6fa: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e6fc: f000 fa51 bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e700: f000 fe28 bl 800f354 <xTaskResumeAll>
|
|
800e704: e77a b.n 800e5fc <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. If there is no data in the queue exit, otherwise loop
|
|
back and attempt to read the data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e706: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e708: f000 fa4b bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e70c: f000 fe22 bl 800f354 <xTaskResumeAll>
|
|
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800e710: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
800e712: f000 fa98 bl 800ec46 <prvIsQueueEmpty>
|
|
800e716: 4603 mov r3, r0
|
|
800e718: 2b00 cmp r3, #0
|
|
800e71a: f43f af6f beq.w 800e5fc <xQueueReceive+0x94>
|
|
{
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800e71e: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800e720: 4618 mov r0, r3
|
|
800e722: 3730 adds r7, #48 ; 0x30
|
|
800e724: 46bd mov sp, r7
|
|
800e726: bd80 pop {r7, pc}
|
|
800e728: e000ed04 .word 0xe000ed04
|
|
|
|
0800e72c <xQueueSemaphoreTake>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
|
|
{
|
|
800e72c: b580 push {r7, lr}
|
|
800e72e: b08e sub sp, #56 ; 0x38
|
|
800e730: af00 add r7, sp, #0
|
|
800e732: 6078 str r0, [r7, #4]
|
|
800e734: 6039 str r1, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
800e736: 2300 movs r3, #0
|
|
800e738: 637b str r3, [r7, #52] ; 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e73a: 687b ldr r3, [r7, #4]
|
|
800e73c: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
|
#if( configUSE_MUTEXES == 1 )
|
|
BaseType_t xInheritanceOccurred = pdFALSE;
|
|
800e73e: 2300 movs r3, #0
|
|
800e740: 633b str r3, [r7, #48] ; 0x30
|
|
#endif
|
|
|
|
/* Check the queue pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
800e742: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e744: 2b00 cmp r3, #0
|
|
800e746: d10b bne.n 800e760 <xQueueSemaphoreTake+0x34>
|
|
800e748: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e74c: b672 cpsid i
|
|
800e74e: f383 8811 msr BASEPRI, r3
|
|
800e752: f3bf 8f6f isb sy
|
|
800e756: f3bf 8f4f dsb sy
|
|
800e75a: b662 cpsie i
|
|
800e75c: 623b str r3, [r7, #32]
|
|
800e75e: e7fe b.n 800e75e <xQueueSemaphoreTake+0x32>
|
|
|
|
/* Check this really is a semaphore, in which case the item size will be
|
|
0. */
|
|
configASSERT( pxQueue->uxItemSize == 0 );
|
|
800e760: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e762: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e764: 2b00 cmp r3, #0
|
|
800e766: d00b beq.n 800e780 <xQueueSemaphoreTake+0x54>
|
|
800e768: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e76c: b672 cpsid i
|
|
800e76e: f383 8811 msr BASEPRI, r3
|
|
800e772: f3bf 8f6f isb sy
|
|
800e776: f3bf 8f4f dsb sy
|
|
800e77a: b662 cpsie i
|
|
800e77c: 61fb str r3, [r7, #28]
|
|
800e77e: e7fe b.n 800e77e <xQueueSemaphoreTake+0x52>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800e780: f001 f9ca bl 800fb18 <xTaskGetSchedulerState>
|
|
800e784: 4603 mov r3, r0
|
|
800e786: 2b00 cmp r3, #0
|
|
800e788: d102 bne.n 800e790 <xQueueSemaphoreTake+0x64>
|
|
800e78a: 683b ldr r3, [r7, #0]
|
|
800e78c: 2b00 cmp r3, #0
|
|
800e78e: d101 bne.n 800e794 <xQueueSemaphoreTake+0x68>
|
|
800e790: 2301 movs r3, #1
|
|
800e792: e000 b.n 800e796 <xQueueSemaphoreTake+0x6a>
|
|
800e794: 2300 movs r3, #0
|
|
800e796: 2b00 cmp r3, #0
|
|
800e798: d10b bne.n 800e7b2 <xQueueSemaphoreTake+0x86>
|
|
800e79a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e79e: b672 cpsid i
|
|
800e7a0: f383 8811 msr BASEPRI, r3
|
|
800e7a4: f3bf 8f6f isb sy
|
|
800e7a8: f3bf 8f4f dsb sy
|
|
800e7ac: b662 cpsie i
|
|
800e7ae: 61bb str r3, [r7, #24]
|
|
800e7b0: e7fe b.n 800e7b0 <xQueueSemaphoreTake+0x84>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
|
|
statements within the function itself. This is done in the interest
|
|
of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800e7b2: f001 fcf9 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
/* Semaphores are queues with an item size of 0, and where the
|
|
number of messages in the queue is the semaphore's count value. */
|
|
const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
|
|
800e7b6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7b8: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800e7ba: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
must be the highest priority task wanting to access the queue. */
|
|
if( uxSemaphoreCount > ( UBaseType_t ) 0 )
|
|
800e7bc: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e7be: 2b00 cmp r3, #0
|
|
800e7c0: d024 beq.n 800e80c <xQueueSemaphoreTake+0xe0>
|
|
{
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
|
|
/* Semaphores are queues with a data size of zero and where the
|
|
messages waiting is the semaphore's count. Reduce the count. */
|
|
pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
|
|
800e7c2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e7c4: 1e5a subs r2, r3, #1
|
|
800e7c6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7c8: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800e7ca: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7cc: 681b ldr r3, [r3, #0]
|
|
800e7ce: 2b00 cmp r3, #0
|
|
800e7d0: d104 bne.n 800e7dc <xQueueSemaphoreTake+0xb0>
|
|
{
|
|
/* Record the information required to implement
|
|
priority inheritance should it become necessary. */
|
|
pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
|
|
800e7d2: f001 fb63 bl 800fe9c <pvTaskIncrementMutexHeldCount>
|
|
800e7d6: 4602 mov r2, r0
|
|
800e7d8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7da: 609a str r2, [r3, #8]
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
/* Check to see if other tasks are blocked waiting to give the
|
|
semaphore, and if so, unblock the highest priority such task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800e7dc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7de: 691b ldr r3, [r3, #16]
|
|
800e7e0: 2b00 cmp r3, #0
|
|
800e7e2: d00f beq.n 800e804 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800e7e4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e7e6: 3310 adds r3, #16
|
|
800e7e8: 4618 mov r0, r3
|
|
800e7ea: f000 ffd5 bl 800f798 <xTaskRemoveFromEventList>
|
|
800e7ee: 4603 mov r3, r0
|
|
800e7f0: 2b00 cmp r3, #0
|
|
800e7f2: d007 beq.n 800e804 <xQueueSemaphoreTake+0xd8>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800e7f4: 4b54 ldr r3, [pc, #336] ; (800e948 <xQueueSemaphoreTake+0x21c>)
|
|
800e7f6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e7fa: 601a str r2, [r3, #0]
|
|
800e7fc: f3bf 8f4f dsb sy
|
|
800e800: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
800e804: f001 fd02 bl 801020c <vPortExitCritical>
|
|
return pdPASS;
|
|
800e808: 2301 movs r3, #1
|
|
800e80a: e098 b.n 800e93e <xQueueSemaphoreTake+0x212>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800e80c: 683b ldr r3, [r7, #0]
|
|
800e80e: 2b00 cmp r3, #0
|
|
800e810: d112 bne.n 800e838 <xQueueSemaphoreTake+0x10c>
|
|
/* For inheritance to have occurred there must have been an
|
|
initial timeout, and an adjusted timeout cannot become 0, as
|
|
if it were 0 the function would have exited. */
|
|
#if( configUSE_MUTEXES == 1 )
|
|
{
|
|
configASSERT( xInheritanceOccurred == pdFALSE );
|
|
800e812: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e814: 2b00 cmp r3, #0
|
|
800e816: d00b beq.n 800e830 <xQueueSemaphoreTake+0x104>
|
|
800e818: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e81c: b672 cpsid i
|
|
800e81e: f383 8811 msr BASEPRI, r3
|
|
800e822: f3bf 8f6f isb sy
|
|
800e826: f3bf 8f4f dsb sy
|
|
800e82a: b662 cpsie i
|
|
800e82c: 617b str r3, [r7, #20]
|
|
800e82e: e7fe b.n 800e82e <xQueueSemaphoreTake+0x102>
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
/* The semaphore count was 0 and no block time is specified
|
|
(or the block time has expired) so exit now. */
|
|
taskEXIT_CRITICAL();
|
|
800e830: f001 fcec bl 801020c <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800e834: 2300 movs r3, #0
|
|
800e836: e082 b.n 800e93e <xQueueSemaphoreTake+0x212>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800e838: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
800e83a: 2b00 cmp r3, #0
|
|
800e83c: d106 bne.n 800e84c <xQueueSemaphoreTake+0x120>
|
|
{
|
|
/* The semaphore count was 0 and a block time was specified
|
|
so configure the timeout structure ready to block. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800e83e: f107 030c add.w r3, r7, #12
|
|
800e842: 4618 mov r0, r3
|
|
800e844: f001 f80c bl 800f860 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800e848: 2301 movs r3, #1
|
|
800e84a: 637b str r3, [r7, #52] ; 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e84c: f001 fcde bl 801020c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can give to and take from the semaphore
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800e850: f000 fd72 bl 800f338 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800e854: f001 fca8 bl 80101a8 <vPortEnterCritical>
|
|
800e858: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e85a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800e85e: b25b sxtb r3, r3
|
|
800e860: f1b3 3fff cmp.w r3, #4294967295
|
|
800e864: d103 bne.n 800e86e <xQueueSemaphoreTake+0x142>
|
|
800e866: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e868: 2200 movs r2, #0
|
|
800e86a: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
800e86e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e870: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800e874: b25b sxtb r3, r3
|
|
800e876: f1b3 3fff cmp.w r3, #4294967295
|
|
800e87a: d103 bne.n 800e884 <xQueueSemaphoreTake+0x158>
|
|
800e87c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e87e: 2200 movs r2, #0
|
|
800e880: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
800e884: f001 fcc2 bl 801020c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800e888: 463a mov r2, r7
|
|
800e88a: f107 030c add.w r3, r7, #12
|
|
800e88e: 4611 mov r1, r2
|
|
800e890: 4618 mov r0, r3
|
|
800e892: f000 fffb bl 800f88c <xTaskCheckForTimeOut>
|
|
800e896: 4603 mov r3, r0
|
|
800e898: 2b00 cmp r3, #0
|
|
800e89a: d132 bne.n 800e902 <xQueueSemaphoreTake+0x1d6>
|
|
{
|
|
/* A block time is specified and not expired. If the semaphore
|
|
count is 0 then enter the Blocked state to wait for a semaphore to
|
|
become available. As semaphores are implemented with queues the
|
|
queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800e89c: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e89e: f000 f9d2 bl 800ec46 <prvIsQueueEmpty>
|
|
800e8a2: 4603 mov r3, r0
|
|
800e8a4: 2b00 cmp r3, #0
|
|
800e8a6: d026 beq.n 800e8f6 <xQueueSemaphoreTake+0x1ca>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800e8a8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e8aa: 681b ldr r3, [r3, #0]
|
|
800e8ac: 2b00 cmp r3, #0
|
|
800e8ae: d109 bne.n 800e8c4 <xQueueSemaphoreTake+0x198>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800e8b0: f001 fc7a bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
800e8b4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e8b6: 689b ldr r3, [r3, #8]
|
|
800e8b8: 4618 mov r0, r3
|
|
800e8ba: f001 f94b bl 800fb54 <xTaskPriorityInherit>
|
|
800e8be: 6338 str r0, [r7, #48] ; 0x30
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e8c0: f001 fca4 bl 801020c <vPortExitCritical>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
800e8c4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e8c6: 3324 adds r3, #36 ; 0x24
|
|
800e8c8: 683a ldr r2, [r7, #0]
|
|
800e8ca: 4611 mov r1, r2
|
|
800e8cc: 4618 mov r0, r3
|
|
800e8ce: f000 ff3d bl 800f74c <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
800e8d2: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e8d4: f000 f965 bl 800eba2 <prvUnlockQueue>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800e8d8: f000 fd3c bl 800f354 <xTaskResumeAll>
|
|
800e8dc: 4603 mov r3, r0
|
|
800e8de: 2b00 cmp r3, #0
|
|
800e8e0: f47f af67 bne.w 800e7b2 <xQueueSemaphoreTake+0x86>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800e8e4: 4b18 ldr r3, [pc, #96] ; (800e948 <xQueueSemaphoreTake+0x21c>)
|
|
800e8e6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800e8ea: 601a str r2, [r3, #0]
|
|
800e8ec: f3bf 8f4f dsb sy
|
|
800e8f0: f3bf 8f6f isb sy
|
|
800e8f4: e75d b.n 800e7b2 <xQueueSemaphoreTake+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* There was no timeout and the semaphore count was not 0, so
|
|
attempt to take the semaphore again. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e8f6: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e8f8: f000 f953 bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e8fc: f000 fd2a bl 800f354 <xTaskResumeAll>
|
|
800e900: e757 b.n 800e7b2 <xQueueSemaphoreTake+0x86>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. */
|
|
prvUnlockQueue( pxQueue );
|
|
800e902: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e904: f000 f94d bl 800eba2 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800e908: f000 fd24 bl 800f354 <xTaskResumeAll>
|
|
|
|
/* If the semaphore count is 0 exit now as the timeout has
|
|
expired. Otherwise return to attempt to take the semaphore that is
|
|
known to be available. As semaphores are implemented by queues the
|
|
queue being empty is equivalent to the semaphore count being 0. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800e90c: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e90e: f000 f99a bl 800ec46 <prvIsQueueEmpty>
|
|
800e912: 4603 mov r3, r0
|
|
800e914: 2b00 cmp r3, #0
|
|
800e916: f43f af4c beq.w 800e7b2 <xQueueSemaphoreTake+0x86>
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
/* xInheritanceOccurred could only have be set if
|
|
pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
|
|
test the mutex type again to check it is actually a mutex. */
|
|
if( xInheritanceOccurred != pdFALSE )
|
|
800e91a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e91c: 2b00 cmp r3, #0
|
|
800e91e: d00d beq.n 800e93c <xQueueSemaphoreTake+0x210>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800e920: f001 fc42 bl 80101a8 <vPortEnterCritical>
|
|
/* This task blocking on the mutex caused another
|
|
task to inherit this task's priority. Now this task
|
|
has timed out the priority should be disinherited
|
|
again, but only as low as the next highest priority
|
|
task that is waiting for the same mutex. */
|
|
uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
|
|
800e924: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
800e926: f000 f894 bl 800ea52 <prvGetDisinheritPriorityAfterTimeout>
|
|
800e92a: 6278 str r0, [r7, #36] ; 0x24
|
|
vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
|
|
800e92c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800e92e: 689b ldr r3, [r3, #8]
|
|
800e930: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
800e932: 4618 mov r0, r3
|
|
800e934: f001 fa16 bl 800fd64 <vTaskPriorityDisinheritAfterTimeout>
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800e938: f001 fc68 bl 801020c <vPortExitCritical>
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800e93c: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800e93e: 4618 mov r0, r3
|
|
800e940: 3738 adds r7, #56 ; 0x38
|
|
800e942: 46bd mov sp, r7
|
|
800e944: bd80 pop {r7, pc}
|
|
800e946: bf00 nop
|
|
800e948: e000ed04 .word 0xe000ed04
|
|
|
|
0800e94c <xQueueReceiveFromISR>:
|
|
} /*lint -restore */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
800e94c: b580 push {r7, lr}
|
|
800e94e: b08e sub sp, #56 ; 0x38
|
|
800e950: af00 add r7, sp, #0
|
|
800e952: 60f8 str r0, [r7, #12]
|
|
800e954: 60b9 str r1, [r7, #8]
|
|
800e956: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800e958: 68fb ldr r3, [r7, #12]
|
|
800e95a: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800e95c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e95e: 2b00 cmp r3, #0
|
|
800e960: d10b bne.n 800e97a <xQueueReceiveFromISR+0x2e>
|
|
800e962: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e966: b672 cpsid i
|
|
800e968: f383 8811 msr BASEPRI, r3
|
|
800e96c: f3bf 8f6f isb sy
|
|
800e970: f3bf 8f4f dsb sy
|
|
800e974: b662 cpsie i
|
|
800e976: 623b str r3, [r7, #32]
|
|
800e978: e7fe b.n 800e978 <xQueueReceiveFromISR+0x2c>
|
|
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800e97a: 68bb ldr r3, [r7, #8]
|
|
800e97c: 2b00 cmp r3, #0
|
|
800e97e: d103 bne.n 800e988 <xQueueReceiveFromISR+0x3c>
|
|
800e980: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e982: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800e984: 2b00 cmp r3, #0
|
|
800e986: d101 bne.n 800e98c <xQueueReceiveFromISR+0x40>
|
|
800e988: 2301 movs r3, #1
|
|
800e98a: e000 b.n 800e98e <xQueueReceiveFromISR+0x42>
|
|
800e98c: 2300 movs r3, #0
|
|
800e98e: 2b00 cmp r3, #0
|
|
800e990: d10b bne.n 800e9aa <xQueueReceiveFromISR+0x5e>
|
|
800e992: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e996: b672 cpsid i
|
|
800e998: f383 8811 msr BASEPRI, r3
|
|
800e99c: f3bf 8f6f isb sy
|
|
800e9a0: f3bf 8f4f dsb sy
|
|
800e9a4: b662 cpsie i
|
|
800e9a6: 61fb str r3, [r7, #28]
|
|
800e9a8: e7fe b.n 800e9a8 <xQueueReceiveFromISR+0x5c>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800e9aa: f001 fcdd bl 8010368 <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
800e9ae: f3ef 8211 mrs r2, BASEPRI
|
|
800e9b2: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800e9b6: b672 cpsid i
|
|
800e9b8: f383 8811 msr BASEPRI, r3
|
|
800e9bc: f3bf 8f6f isb sy
|
|
800e9c0: f3bf 8f4f dsb sy
|
|
800e9c4: b662 cpsie i
|
|
800e9c6: 61ba str r2, [r7, #24]
|
|
800e9c8: 617b str r3, [r7, #20]
|
|
return ulOriginalBASEPRI;
|
|
800e9ca: 69bb ldr r3, [r7, #24]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800e9cc: 62fb str r3, [r7, #44] ; 0x2c
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800e9ce: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e9d0: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800e9d2: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
/* Cannot block in an ISR, so check there is data available. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800e9d4: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e9d6: 2b00 cmp r3, #0
|
|
800e9d8: d02f beq.n 800ea3a <xQueueReceiveFromISR+0xee>
|
|
{
|
|
const int8_t cRxLock = pxQueue->cRxLock;
|
|
800e9da: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e9dc: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800e9e0: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
|
|
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
800e9e4: 68b9 ldr r1, [r7, #8]
|
|
800e9e6: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
800e9e8: f000 f8b5 bl 800eb56 <prvCopyDataFromQueue>
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
800e9ec: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800e9ee: 1e5a subs r2, r3, #1
|
|
800e9f0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800e9f2: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
/* If the queue is locked the event list will not be modified.
|
|
Instead update the lock count so the task that unlocks the queue
|
|
will know that an ISR has removed data while the queue was
|
|
locked. */
|
|
if( cRxLock == queueUNLOCKED )
|
|
800e9f4: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
800e9f8: f1b3 3fff cmp.w r3, #4294967295
|
|
800e9fc: d112 bne.n 800ea24 <xQueueReceiveFromISR+0xd8>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800e9fe: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ea00: 691b ldr r3, [r3, #16]
|
|
800ea02: 2b00 cmp r3, #0
|
|
800ea04: d016 beq.n 800ea34 <xQueueReceiveFromISR+0xe8>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800ea06: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ea08: 3310 adds r3, #16
|
|
800ea0a: 4618 mov r0, r3
|
|
800ea0c: f000 fec4 bl 800f798 <xTaskRemoveFromEventList>
|
|
800ea10: 4603 mov r3, r0
|
|
800ea12: 2b00 cmp r3, #0
|
|
800ea14: d00e beq.n 800ea34 <xQueueReceiveFromISR+0xe8>
|
|
{
|
|
/* The task waiting has a higher priority than us so
|
|
force a context switch. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800ea16: 687b ldr r3, [r7, #4]
|
|
800ea18: 2b00 cmp r3, #0
|
|
800ea1a: d00b beq.n 800ea34 <xQueueReceiveFromISR+0xe8>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800ea1c: 687b ldr r3, [r7, #4]
|
|
800ea1e: 2201 movs r2, #1
|
|
800ea20: 601a str r2, [r3, #0]
|
|
800ea22: e007 b.n 800ea34 <xQueueReceiveFromISR+0xe8>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was removed while it was locked. */
|
|
pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
|
|
800ea24: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
800ea28: 3301 adds r3, #1
|
|
800ea2a: b2db uxtb r3, r3
|
|
800ea2c: b25a sxtb r2, r3
|
|
800ea2e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ea30: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800ea34: 2301 movs r3, #1
|
|
800ea36: 637b str r3, [r7, #52] ; 0x34
|
|
800ea38: e001 b.n 800ea3e <xQueueReceiveFromISR+0xf2>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
800ea3a: 2300 movs r3, #0
|
|
800ea3c: 637b str r3, [r7, #52] ; 0x34
|
|
800ea3e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800ea40: 613b str r3, [r7, #16]
|
|
__asm volatile
|
|
800ea42: 693b ldr r3, [r7, #16]
|
|
800ea44: f383 8811 msr BASEPRI, r3
|
|
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800ea48: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
}
|
|
800ea4a: 4618 mov r0, r3
|
|
800ea4c: 3738 adds r7, #56 ; 0x38
|
|
800ea4e: 46bd mov sp, r7
|
|
800ea50: bd80 pop {r7, pc}
|
|
|
|
0800ea52 <prvGetDisinheritPriorityAfterTimeout>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configUSE_MUTEXES == 1 )
|
|
|
|
static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
|
|
{
|
|
800ea52: b480 push {r7}
|
|
800ea54: b085 sub sp, #20
|
|
800ea56: af00 add r7, sp, #0
|
|
800ea58: 6078 str r0, [r7, #4]
|
|
priority, but the waiting task times out, then the holder should
|
|
disinherit the priority - but only down to the highest priority of any
|
|
other tasks that are waiting for the same mutex. For this purpose,
|
|
return the priority of the highest priority task that is waiting for the
|
|
mutex. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
|
|
800ea5a: 687b ldr r3, [r7, #4]
|
|
800ea5c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ea5e: 2b00 cmp r3, #0
|
|
800ea60: d006 beq.n 800ea70 <prvGetDisinheritPriorityAfterTimeout+0x1e>
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
|
|
800ea62: 687b ldr r3, [r7, #4]
|
|
800ea64: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800ea66: 681b ldr r3, [r3, #0]
|
|
800ea68: f1c3 0307 rsb r3, r3, #7
|
|
800ea6c: 60fb str r3, [r7, #12]
|
|
800ea6e: e001 b.n 800ea74 <prvGetDisinheritPriorityAfterTimeout+0x22>
|
|
}
|
|
else
|
|
{
|
|
uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
|
|
800ea70: 2300 movs r3, #0
|
|
800ea72: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return uxHighestPriorityOfWaitingTasks;
|
|
800ea74: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800ea76: 4618 mov r0, r3
|
|
800ea78: 3714 adds r7, #20
|
|
800ea7a: 46bd mov sp, r7
|
|
800ea7c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800ea80: 4770 bx lr
|
|
|
|
0800ea82 <prvCopyDataToQueue>:
|
|
|
|
#endif /* configUSE_MUTEXES */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
|
|
{
|
|
800ea82: b580 push {r7, lr}
|
|
800ea84: b086 sub sp, #24
|
|
800ea86: af00 add r7, sp, #0
|
|
800ea88: 60f8 str r0, [r7, #12]
|
|
800ea8a: 60b9 str r1, [r7, #8]
|
|
800ea8c: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800ea8e: 2300 movs r3, #0
|
|
800ea90: 617b str r3, [r7, #20]
|
|
UBaseType_t uxMessagesWaiting;
|
|
|
|
/* This function is called from a critical section. */
|
|
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800ea92: 68fb ldr r3, [r7, #12]
|
|
800ea94: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800ea96: 613b str r3, [r7, #16]
|
|
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
|
800ea98: 68fb ldr r3, [r7, #12]
|
|
800ea9a: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800ea9c: 2b00 cmp r3, #0
|
|
800ea9e: d10d bne.n 800eabc <prvCopyDataToQueue+0x3a>
|
|
{
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800eaa0: 68fb ldr r3, [r7, #12]
|
|
800eaa2: 681b ldr r3, [r3, #0]
|
|
800eaa4: 2b00 cmp r3, #0
|
|
800eaa6: d14d bne.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* The mutex is no longer being held. */
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
800eaa8: 68fb ldr r3, [r7, #12]
|
|
800eaaa: 689b ldr r3, [r3, #8]
|
|
800eaac: 4618 mov r0, r3
|
|
800eaae: f001 f8d1 bl 800fc54 <xTaskPriorityDisinherit>
|
|
800eab2: 6178 str r0, [r7, #20]
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
800eab4: 68fb ldr r3, [r7, #12]
|
|
800eab6: 2200 movs r2, #0
|
|
800eab8: 609a str r2, [r3, #8]
|
|
800eaba: e043 b.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
}
|
|
else if( xPosition == queueSEND_TO_BACK )
|
|
800eabc: 687b ldr r3, [r7, #4]
|
|
800eabe: 2b00 cmp r3, #0
|
|
800eac0: d119 bne.n 800eaf6 <prvCopyDataToQueue+0x74>
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800eac2: 68fb ldr r3, [r7, #12]
|
|
800eac4: 6858 ldr r0, [r3, #4]
|
|
800eac6: 68fb ldr r3, [r7, #12]
|
|
800eac8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eaca: 461a mov r2, r3
|
|
800eacc: 68b9 ldr r1, [r7, #8]
|
|
800eace: f00e f8c6 bl 801cc5e <memcpy>
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800ead2: 68fb ldr r3, [r7, #12]
|
|
800ead4: 685a ldr r2, [r3, #4]
|
|
800ead6: 68fb ldr r3, [r7, #12]
|
|
800ead8: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eada: 441a add r2, r3
|
|
800eadc: 68fb ldr r3, [r7, #12]
|
|
800eade: 605a str r2, [r3, #4]
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800eae0: 68fb ldr r3, [r7, #12]
|
|
800eae2: 685a ldr r2, [r3, #4]
|
|
800eae4: 68fb ldr r3, [r7, #12]
|
|
800eae6: 689b ldr r3, [r3, #8]
|
|
800eae8: 429a cmp r2, r3
|
|
800eaea: d32b bcc.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800eaec: 68fb ldr r3, [r7, #12]
|
|
800eaee: 681a ldr r2, [r3, #0]
|
|
800eaf0: 68fb ldr r3, [r7, #12]
|
|
800eaf2: 605a str r2, [r3, #4]
|
|
800eaf4: e026 b.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
|
800eaf6: 68fb ldr r3, [r7, #12]
|
|
800eaf8: 68d8 ldr r0, [r3, #12]
|
|
800eafa: 68fb ldr r3, [r7, #12]
|
|
800eafc: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eafe: 461a mov r2, r3
|
|
800eb00: 68b9 ldr r1, [r7, #8]
|
|
800eb02: f00e f8ac bl 801cc5e <memcpy>
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
|
800eb06: 68fb ldr r3, [r7, #12]
|
|
800eb08: 68da ldr r2, [r3, #12]
|
|
800eb0a: 68fb ldr r3, [r7, #12]
|
|
800eb0c: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eb0e: 425b negs r3, r3
|
|
800eb10: 441a add r2, r3
|
|
800eb12: 68fb ldr r3, [r7, #12]
|
|
800eb14: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800eb16: 68fb ldr r3, [r7, #12]
|
|
800eb18: 68da ldr r2, [r3, #12]
|
|
800eb1a: 68fb ldr r3, [r7, #12]
|
|
800eb1c: 681b ldr r3, [r3, #0]
|
|
800eb1e: 429a cmp r2, r3
|
|
800eb20: d207 bcs.n 800eb32 <prvCopyDataToQueue+0xb0>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
|
800eb22: 68fb ldr r3, [r7, #12]
|
|
800eb24: 689a ldr r2, [r3, #8]
|
|
800eb26: 68fb ldr r3, [r7, #12]
|
|
800eb28: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eb2a: 425b negs r3, r3
|
|
800eb2c: 441a add r2, r3
|
|
800eb2e: 68fb ldr r3, [r7, #12]
|
|
800eb30: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xPosition == queueOVERWRITE )
|
|
800eb32: 687b ldr r3, [r7, #4]
|
|
800eb34: 2b02 cmp r3, #2
|
|
800eb36: d105 bne.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800eb38: 693b ldr r3, [r7, #16]
|
|
800eb3a: 2b00 cmp r3, #0
|
|
800eb3c: d002 beq.n 800eb44 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* An item is not being added but overwritten, so subtract
|
|
one from the recorded number of items in the queue so when
|
|
one is added again below the number of recorded items remains
|
|
correct. */
|
|
--uxMessagesWaiting;
|
|
800eb3e: 693b ldr r3, [r7, #16]
|
|
800eb40: 3b01 subs r3, #1
|
|
800eb42: 613b str r3, [r7, #16]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
800eb44: 693b ldr r3, [r7, #16]
|
|
800eb46: 1c5a adds r2, r3, #1
|
|
800eb48: 68fb ldr r3, [r7, #12]
|
|
800eb4a: 639a str r2, [r3, #56] ; 0x38
|
|
|
|
return xReturn;
|
|
800eb4c: 697b ldr r3, [r7, #20]
|
|
}
|
|
800eb4e: 4618 mov r0, r3
|
|
800eb50: 3718 adds r7, #24
|
|
800eb52: 46bd mov sp, r7
|
|
800eb54: bd80 pop {r7, pc}
|
|
|
|
0800eb56 <prvCopyDataFromQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
|
|
{
|
|
800eb56: b580 push {r7, lr}
|
|
800eb58: b082 sub sp, #8
|
|
800eb5a: af00 add r7, sp, #0
|
|
800eb5c: 6078 str r0, [r7, #4]
|
|
800eb5e: 6039 str r1, [r7, #0]
|
|
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
|
|
800eb60: 687b ldr r3, [r7, #4]
|
|
800eb62: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eb64: 2b00 cmp r3, #0
|
|
800eb66: d018 beq.n 800eb9a <prvCopyDataFromQueue+0x44>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800eb68: 687b ldr r3, [r7, #4]
|
|
800eb6a: 68da ldr r2, [r3, #12]
|
|
800eb6c: 687b ldr r3, [r7, #4]
|
|
800eb6e: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eb70: 441a add r2, r3
|
|
800eb72: 687b ldr r3, [r7, #4]
|
|
800eb74: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
|
|
800eb76: 687b ldr r3, [r7, #4]
|
|
800eb78: 68da ldr r2, [r3, #12]
|
|
800eb7a: 687b ldr r3, [r7, #4]
|
|
800eb7c: 689b ldr r3, [r3, #8]
|
|
800eb7e: 429a cmp r2, r3
|
|
800eb80: d303 bcc.n 800eb8a <prvCopyDataFromQueue+0x34>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
|
|
800eb82: 687b ldr r3, [r7, #4]
|
|
800eb84: 681a ldr r2, [r3, #0]
|
|
800eb86: 687b ldr r3, [r7, #4]
|
|
800eb88: 60da str r2, [r3, #12]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800eb8a: 687b ldr r3, [r7, #4]
|
|
800eb8c: 68d9 ldr r1, [r3, #12]
|
|
800eb8e: 687b ldr r3, [r7, #4]
|
|
800eb90: 6c1b ldr r3, [r3, #64] ; 0x40
|
|
800eb92: 461a mov r2, r3
|
|
800eb94: 6838 ldr r0, [r7, #0]
|
|
800eb96: f00e f862 bl 801cc5e <memcpy>
|
|
}
|
|
}
|
|
800eb9a: bf00 nop
|
|
800eb9c: 3708 adds r7, #8
|
|
800eb9e: 46bd mov sp, r7
|
|
800eba0: bd80 pop {r7, pc}
|
|
|
|
0800eba2 <prvUnlockQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
|
{
|
|
800eba2: b580 push {r7, lr}
|
|
800eba4: b084 sub sp, #16
|
|
800eba6: af00 add r7, sp, #0
|
|
800eba8: 6078 str r0, [r7, #4]
|
|
|
|
/* The lock counts contains the number of extra data items placed or
|
|
removed from the queue while the queue was locked. When a queue is
|
|
locked items can be added or removed, but the event lists cannot be
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800ebaa: f001 fafd bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
|
800ebae: 687b ldr r3, [r7, #4]
|
|
800ebb0: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
|
|
800ebb4: 73fb strb r3, [r7, #15]
|
|
|
|
/* See if data was added to the queue while it was locked. */
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800ebb6: e011 b.n 800ebdc <prvUnlockQueue+0x3a>
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
/* Tasks that are removed from the event list will get added to
|
|
the pending ready list as the scheduler is still suspended. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800ebb8: 687b ldr r3, [r7, #4]
|
|
800ebba: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
800ebbc: 2b00 cmp r3, #0
|
|
800ebbe: d012 beq.n 800ebe6 <prvUnlockQueue+0x44>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800ebc0: 687b ldr r3, [r7, #4]
|
|
800ebc2: 3324 adds r3, #36 ; 0x24
|
|
800ebc4: 4618 mov r0, r3
|
|
800ebc6: f000 fde7 bl 800f798 <xTaskRemoveFromEventList>
|
|
800ebca: 4603 mov r3, r0
|
|
800ebcc: 2b00 cmp r3, #0
|
|
800ebce: d001 beq.n 800ebd4 <prvUnlockQueue+0x32>
|
|
{
|
|
/* The task waiting has a higher priority so record that
|
|
a context switch is required. */
|
|
vTaskMissedYield();
|
|
800ebd0: f000 fec0 bl 800f954 <vTaskMissedYield>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
--cTxLock;
|
|
800ebd4: 7bfb ldrb r3, [r7, #15]
|
|
800ebd6: 3b01 subs r3, #1
|
|
800ebd8: b2db uxtb r3, r3
|
|
800ebda: 73fb strb r3, [r7, #15]
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800ebdc: f997 300f ldrsb.w r3, [r7, #15]
|
|
800ebe0: 2b00 cmp r3, #0
|
|
800ebe2: dce9 bgt.n 800ebb8 <prvUnlockQueue+0x16>
|
|
800ebe4: e000 b.n 800ebe8 <prvUnlockQueue+0x46>
|
|
break;
|
|
800ebe6: bf00 nop
|
|
}
|
|
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800ebe8: 687b ldr r3, [r7, #4]
|
|
800ebea: 22ff movs r2, #255 ; 0xff
|
|
800ebec: f883 2045 strb.w r2, [r3, #69] ; 0x45
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ebf0: f001 fb0c bl 801020c <vPortExitCritical>
|
|
|
|
/* Do the same for the Rx lock. */
|
|
taskENTER_CRITICAL();
|
|
800ebf4: f001 fad8 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
|
800ebf8: 687b ldr r3, [r7, #4]
|
|
800ebfa: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
|
|
800ebfe: 73bb strb r3, [r7, #14]
|
|
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800ec00: e011 b.n 800ec26 <prvUnlockQueue+0x84>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800ec02: 687b ldr r3, [r7, #4]
|
|
800ec04: 691b ldr r3, [r3, #16]
|
|
800ec06: 2b00 cmp r3, #0
|
|
800ec08: d012 beq.n 800ec30 <prvUnlockQueue+0x8e>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800ec0a: 687b ldr r3, [r7, #4]
|
|
800ec0c: 3310 adds r3, #16
|
|
800ec0e: 4618 mov r0, r3
|
|
800ec10: f000 fdc2 bl 800f798 <xTaskRemoveFromEventList>
|
|
800ec14: 4603 mov r3, r0
|
|
800ec16: 2b00 cmp r3, #0
|
|
800ec18: d001 beq.n 800ec1e <prvUnlockQueue+0x7c>
|
|
{
|
|
vTaskMissedYield();
|
|
800ec1a: f000 fe9b bl 800f954 <vTaskMissedYield>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--cRxLock;
|
|
800ec1e: 7bbb ldrb r3, [r7, #14]
|
|
800ec20: 3b01 subs r3, #1
|
|
800ec22: b2db uxtb r3, r3
|
|
800ec24: 73bb strb r3, [r7, #14]
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800ec26: f997 300e ldrsb.w r3, [r7, #14]
|
|
800ec2a: 2b00 cmp r3, #0
|
|
800ec2c: dce9 bgt.n 800ec02 <prvUnlockQueue+0x60>
|
|
800ec2e: e000 b.n 800ec32 <prvUnlockQueue+0x90>
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
800ec30: bf00 nop
|
|
}
|
|
}
|
|
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800ec32: 687b ldr r3, [r7, #4]
|
|
800ec34: 22ff movs r2, #255 ; 0xff
|
|
800ec36: f883 2044 strb.w r2, [r3, #68] ; 0x44
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ec3a: f001 fae7 bl 801020c <vPortExitCritical>
|
|
}
|
|
800ec3e: bf00 nop
|
|
800ec40: 3710 adds r7, #16
|
|
800ec42: 46bd mov sp, r7
|
|
800ec44: bd80 pop {r7, pc}
|
|
|
|
0800ec46 <prvIsQueueEmpty>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
|
|
{
|
|
800ec46: b580 push {r7, lr}
|
|
800ec48: b084 sub sp, #16
|
|
800ec4a: af00 add r7, sp, #0
|
|
800ec4c: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800ec4e: f001 faab bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
|
|
800ec52: 687b ldr r3, [r7, #4]
|
|
800ec54: 6b9b ldr r3, [r3, #56] ; 0x38
|
|
800ec56: 2b00 cmp r3, #0
|
|
800ec58: d102 bne.n 800ec60 <prvIsQueueEmpty+0x1a>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800ec5a: 2301 movs r3, #1
|
|
800ec5c: 60fb str r3, [r7, #12]
|
|
800ec5e: e001 b.n 800ec64 <prvIsQueueEmpty+0x1e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800ec60: 2300 movs r3, #0
|
|
800ec62: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ec64: f001 fad2 bl 801020c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800ec68: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800ec6a: 4618 mov r0, r3
|
|
800ec6c: 3710 adds r7, #16
|
|
800ec6e: 46bd mov sp, r7
|
|
800ec70: bd80 pop {r7, pc}
|
|
|
|
0800ec72 <prvIsQueueFull>:
|
|
return xReturn;
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
|
|
{
|
|
800ec72: b580 push {r7, lr}
|
|
800ec74: b084 sub sp, #16
|
|
800ec76: af00 add r7, sp, #0
|
|
800ec78: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800ec7a: f001 fa95 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
|
800ec7e: 687b ldr r3, [r7, #4]
|
|
800ec80: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
800ec82: 687b ldr r3, [r7, #4]
|
|
800ec84: 6bdb ldr r3, [r3, #60] ; 0x3c
|
|
800ec86: 429a cmp r2, r3
|
|
800ec88: d102 bne.n 800ec90 <prvIsQueueFull+0x1e>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800ec8a: 2301 movs r3, #1
|
|
800ec8c: 60fb str r3, [r7, #12]
|
|
800ec8e: e001 b.n 800ec94 <prvIsQueueFull+0x22>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800ec90: 2300 movs r3, #0
|
|
800ec92: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ec94: f001 faba bl 801020c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800ec98: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800ec9a: 4618 mov r0, r3
|
|
800ec9c: 3710 adds r7, #16
|
|
800ec9e: 46bd mov sp, r7
|
|
800eca0: bd80 pop {r7, pc}
|
|
|
|
0800eca2 <xTaskCreateStatic>:
|
|
const uint32_t ulStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
StackType_t * const puxStackBuffer,
|
|
StaticTask_t * const pxTaskBuffer )
|
|
{
|
|
800eca2: b580 push {r7, lr}
|
|
800eca4: b08e sub sp, #56 ; 0x38
|
|
800eca6: af04 add r7, sp, #16
|
|
800eca8: 60f8 str r0, [r7, #12]
|
|
800ecaa: 60b9 str r1, [r7, #8]
|
|
800ecac: 607a str r2, [r7, #4]
|
|
800ecae: 603b str r3, [r7, #0]
|
|
TCB_t *pxNewTCB;
|
|
TaskHandle_t xReturn;
|
|
|
|
configASSERT( puxStackBuffer != NULL );
|
|
800ecb0: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
800ecb2: 2b00 cmp r3, #0
|
|
800ecb4: d10b bne.n 800ecce <xTaskCreateStatic+0x2c>
|
|
__asm volatile
|
|
800ecb6: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800ecba: b672 cpsid i
|
|
800ecbc: f383 8811 msr BASEPRI, r3
|
|
800ecc0: f3bf 8f6f isb sy
|
|
800ecc4: f3bf 8f4f dsb sy
|
|
800ecc8: b662 cpsie i
|
|
800ecca: 623b str r3, [r7, #32]
|
|
800eccc: e7fe b.n 800eccc <xTaskCreateStatic+0x2a>
|
|
configASSERT( pxTaskBuffer != NULL );
|
|
800ecce: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
800ecd0: 2b00 cmp r3, #0
|
|
800ecd2: d10b bne.n 800ecec <xTaskCreateStatic+0x4a>
|
|
800ecd4: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800ecd8: b672 cpsid i
|
|
800ecda: f383 8811 msr BASEPRI, r3
|
|
800ecde: f3bf 8f6f isb sy
|
|
800ece2: f3bf 8f4f dsb sy
|
|
800ece6: b662 cpsie i
|
|
800ece8: 61fb str r3, [r7, #28]
|
|
800ecea: e7fe b.n 800ecea <xTaskCreateStatic+0x48>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticTask_t equals the size of the real task
|
|
structure. */
|
|
volatile size_t xSize = sizeof( StaticTask_t );
|
|
800ecec: 2358 movs r3, #88 ; 0x58
|
|
800ecee: 613b str r3, [r7, #16]
|
|
configASSERT( xSize == sizeof( TCB_t ) );
|
|
800ecf0: 693b ldr r3, [r7, #16]
|
|
800ecf2: 2b58 cmp r3, #88 ; 0x58
|
|
800ecf4: d00b beq.n 800ed0e <xTaskCreateStatic+0x6c>
|
|
800ecf6: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800ecfa: b672 cpsid i
|
|
800ecfc: f383 8811 msr BASEPRI, r3
|
|
800ed00: f3bf 8f6f isb sy
|
|
800ed04: f3bf 8f4f dsb sy
|
|
800ed08: b662 cpsie i
|
|
800ed0a: 61bb str r3, [r7, #24]
|
|
800ed0c: e7fe b.n 800ed0c <xTaskCreateStatic+0x6a>
|
|
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
|
|
800ed0e: 693b ldr r3, [r7, #16]
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
|
|
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
|
|
800ed10: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
800ed12: 2b00 cmp r3, #0
|
|
800ed14: d01e beq.n 800ed54 <xTaskCreateStatic+0xb2>
|
|
800ed16: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
800ed18: 2b00 cmp r3, #0
|
|
800ed1a: d01b beq.n 800ed54 <xTaskCreateStatic+0xb2>
|
|
{
|
|
/* The memory used for the task's TCB and stack are passed into this
|
|
function - use them. */
|
|
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800ed1c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
800ed1e: 627b str r3, [r7, #36] ; 0x24
|
|
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
|
|
800ed20: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800ed22: 6b7a ldr r2, [r7, #52] ; 0x34
|
|
800ed24: 631a str r2, [r3, #48] ; 0x30
|
|
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created statically in case the task is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800ed26: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800ed28: 2202 movs r2, #2
|
|
800ed2a: f883 2055 strb.w r2, [r3, #85] ; 0x55
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
|
|
800ed2e: 2300 movs r3, #0
|
|
800ed30: 9303 str r3, [sp, #12]
|
|
800ed32: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800ed34: 9302 str r3, [sp, #8]
|
|
800ed36: f107 0314 add.w r3, r7, #20
|
|
800ed3a: 9301 str r3, [sp, #4]
|
|
800ed3c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ed3e: 9300 str r3, [sp, #0]
|
|
800ed40: 683b ldr r3, [r7, #0]
|
|
800ed42: 687a ldr r2, [r7, #4]
|
|
800ed44: 68b9 ldr r1, [r7, #8]
|
|
800ed46: 68f8 ldr r0, [r7, #12]
|
|
800ed48: f000 f850 bl 800edec <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800ed4c: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
800ed4e: f000 f8e1 bl 800ef14 <prvAddNewTaskToReadyList>
|
|
800ed52: e001 b.n 800ed58 <xTaskCreateStatic+0xb6>
|
|
}
|
|
else
|
|
{
|
|
xReturn = NULL;
|
|
800ed54: 2300 movs r3, #0
|
|
800ed56: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800ed58: 697b ldr r3, [r7, #20]
|
|
}
|
|
800ed5a: 4618 mov r0, r3
|
|
800ed5c: 3728 adds r7, #40 ; 0x28
|
|
800ed5e: 46bd mov sp, r7
|
|
800ed60: bd80 pop {r7, pc}
|
|
|
|
0800ed62 <xTaskCreate>:
|
|
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
const configSTACK_DEPTH_TYPE usStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask )
|
|
{
|
|
800ed62: b580 push {r7, lr}
|
|
800ed64: b08c sub sp, #48 ; 0x30
|
|
800ed66: af04 add r7, sp, #16
|
|
800ed68: 60f8 str r0, [r7, #12]
|
|
800ed6a: 60b9 str r1, [r7, #8]
|
|
800ed6c: 603b str r3, [r7, #0]
|
|
800ed6e: 4613 mov r3, r2
|
|
800ed70: 80fb strh r3, [r7, #6]
|
|
#else /* portSTACK_GROWTH */
|
|
{
|
|
StackType_t *pxStack;
|
|
|
|
/* Allocate space for the stack used by the task being created. */
|
|
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
|
|
800ed72: 88fb ldrh r3, [r7, #6]
|
|
800ed74: 009b lsls r3, r3, #2
|
|
800ed76: 4618 mov r0, r3
|
|
800ed78: f001 fb38 bl 80103ec <pvPortMalloc>
|
|
800ed7c: 6178 str r0, [r7, #20]
|
|
|
|
if( pxStack != NULL )
|
|
800ed7e: 697b ldr r3, [r7, #20]
|
|
800ed80: 2b00 cmp r3, #0
|
|
800ed82: d00e beq.n 800eda2 <xTaskCreate+0x40>
|
|
{
|
|
/* Allocate space for the TCB. */
|
|
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
|
|
800ed84: 2058 movs r0, #88 ; 0x58
|
|
800ed86: f001 fb31 bl 80103ec <pvPortMalloc>
|
|
800ed8a: 61f8 str r0, [r7, #28]
|
|
|
|
if( pxNewTCB != NULL )
|
|
800ed8c: 69fb ldr r3, [r7, #28]
|
|
800ed8e: 2b00 cmp r3, #0
|
|
800ed90: d003 beq.n 800ed9a <xTaskCreate+0x38>
|
|
{
|
|
/* Store the stack location in the TCB. */
|
|
pxNewTCB->pxStack = pxStack;
|
|
800ed92: 69fb ldr r3, [r7, #28]
|
|
800ed94: 697a ldr r2, [r7, #20]
|
|
800ed96: 631a str r2, [r3, #48] ; 0x30
|
|
800ed98: e005 b.n 800eda6 <xTaskCreate+0x44>
|
|
}
|
|
else
|
|
{
|
|
/* The stack cannot be used as the TCB was not created. Free
|
|
it again. */
|
|
vPortFree( pxStack );
|
|
800ed9a: 6978 ldr r0, [r7, #20]
|
|
800ed9c: f001 fbf2 bl 8010584 <vPortFree>
|
|
800eda0: e001 b.n 800eda6 <xTaskCreate+0x44>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxNewTCB = NULL;
|
|
800eda2: 2300 movs r3, #0
|
|
800eda4: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
if( pxNewTCB != NULL )
|
|
800eda6: 69fb ldr r3, [r7, #28]
|
|
800eda8: 2b00 cmp r3, #0
|
|
800edaa: d017 beq.n 800eddc <xTaskCreate+0x7a>
|
|
{
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created dynamically in case it is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800edac: 69fb ldr r3, [r7, #28]
|
|
800edae: 2200 movs r2, #0
|
|
800edb0: f883 2055 strb.w r2, [r3, #85] ; 0x55
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
|
|
800edb4: 88fa ldrh r2, [r7, #6]
|
|
800edb6: 2300 movs r3, #0
|
|
800edb8: 9303 str r3, [sp, #12]
|
|
800edba: 69fb ldr r3, [r7, #28]
|
|
800edbc: 9302 str r3, [sp, #8]
|
|
800edbe: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800edc0: 9301 str r3, [sp, #4]
|
|
800edc2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800edc4: 9300 str r3, [sp, #0]
|
|
800edc6: 683b ldr r3, [r7, #0]
|
|
800edc8: 68b9 ldr r1, [r7, #8]
|
|
800edca: 68f8 ldr r0, [r7, #12]
|
|
800edcc: f000 f80e bl 800edec <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800edd0: 69f8 ldr r0, [r7, #28]
|
|
800edd2: f000 f89f bl 800ef14 <prvAddNewTaskToReadyList>
|
|
xReturn = pdPASS;
|
|
800edd6: 2301 movs r3, #1
|
|
800edd8: 61bb str r3, [r7, #24]
|
|
800edda: e002 b.n 800ede2 <xTaskCreate+0x80>
|
|
}
|
|
else
|
|
{
|
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
|
800eddc: f04f 33ff mov.w r3, #4294967295
|
|
800ede0: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return xReturn;
|
|
800ede2: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800ede4: 4618 mov r0, r3
|
|
800ede6: 3720 adds r7, #32
|
|
800ede8: 46bd mov sp, r7
|
|
800edea: bd80 pop {r7, pc}
|
|
|
|
0800edec <prvInitialiseNewTask>:
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask,
|
|
TCB_t *pxNewTCB,
|
|
const MemoryRegion_t * const xRegions )
|
|
{
|
|
800edec: b580 push {r7, lr}
|
|
800edee: b088 sub sp, #32
|
|
800edf0: af00 add r7, sp, #0
|
|
800edf2: 60f8 str r0, [r7, #12]
|
|
800edf4: 60b9 str r1, [r7, #8]
|
|
800edf6: 607a str r2, [r7, #4]
|
|
800edf8: 603b str r3, [r7, #0]
|
|
|
|
/* Avoid dependency on memset() if it is not required. */
|
|
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
|
|
{
|
|
/* Fill the stack with a known value to assist debugging. */
|
|
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
|
|
800edfa: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800edfc: 6b18 ldr r0, [r3, #48] ; 0x30
|
|
800edfe: 687b ldr r3, [r7, #4]
|
|
800ee00: 009b lsls r3, r3, #2
|
|
800ee02: 461a mov r2, r3
|
|
800ee04: 21a5 movs r1, #165 ; 0xa5
|
|
800ee06: f00d ff4e bl 801cca6 <memset>
|
|
grows from high memory to low (as per the 80x86) or vice versa.
|
|
portSTACK_GROWTH is used to make the result positive or negative as required
|
|
by the port. */
|
|
#if( portSTACK_GROWTH < 0 )
|
|
{
|
|
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
|
|
800ee0a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ee0c: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
800ee0e: 6879 ldr r1, [r7, #4]
|
|
800ee10: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000
|
|
800ee14: 440b add r3, r1
|
|
800ee16: 009b lsls r3, r3, #2
|
|
800ee18: 4413 add r3, r2
|
|
800ee1a: 61bb str r3, [r7, #24]
|
|
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
|
|
800ee1c: 69bb ldr r3, [r7, #24]
|
|
800ee1e: f023 0307 bic.w r3, r3, #7
|
|
800ee22: 61bb str r3, [r7, #24]
|
|
|
|
/* Check the alignment of the calculated top of stack is correct. */
|
|
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
|
|
800ee24: 69bb ldr r3, [r7, #24]
|
|
800ee26: f003 0307 and.w r3, r3, #7
|
|
800ee2a: 2b00 cmp r3, #0
|
|
800ee2c: d00b beq.n 800ee46 <prvInitialiseNewTask+0x5a>
|
|
800ee2e: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800ee32: b672 cpsid i
|
|
800ee34: f383 8811 msr BASEPRI, r3
|
|
800ee38: f3bf 8f6f isb sy
|
|
800ee3c: f3bf 8f4f dsb sy
|
|
800ee40: b662 cpsie i
|
|
800ee42: 617b str r3, [r7, #20]
|
|
800ee44: e7fe b.n 800ee44 <prvInitialiseNewTask+0x58>
|
|
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
/* Store the task name in the TCB. */
|
|
if( pcName != NULL )
|
|
800ee46: 68bb ldr r3, [r7, #8]
|
|
800ee48: 2b00 cmp r3, #0
|
|
800ee4a: d01f beq.n 800ee8c <prvInitialiseNewTask+0xa0>
|
|
{
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800ee4c: 2300 movs r3, #0
|
|
800ee4e: 61fb str r3, [r7, #28]
|
|
800ee50: e012 b.n 800ee78 <prvInitialiseNewTask+0x8c>
|
|
{
|
|
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
|
|
800ee52: 68ba ldr r2, [r7, #8]
|
|
800ee54: 69fb ldr r3, [r7, #28]
|
|
800ee56: 4413 add r3, r2
|
|
800ee58: 7819 ldrb r1, [r3, #0]
|
|
800ee5a: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
800ee5c: 69fb ldr r3, [r7, #28]
|
|
800ee5e: 4413 add r3, r2
|
|
800ee60: 3334 adds r3, #52 ; 0x34
|
|
800ee62: 460a mov r2, r1
|
|
800ee64: 701a strb r2, [r3, #0]
|
|
|
|
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
|
|
configMAX_TASK_NAME_LEN characters just in case the memory after the
|
|
string is not accessible (extremely unlikely). */
|
|
if( pcName[ x ] == ( char ) 0x00 )
|
|
800ee66: 68ba ldr r2, [r7, #8]
|
|
800ee68: 69fb ldr r3, [r7, #28]
|
|
800ee6a: 4413 add r3, r2
|
|
800ee6c: 781b ldrb r3, [r3, #0]
|
|
800ee6e: 2b00 cmp r3, #0
|
|
800ee70: d006 beq.n 800ee80 <prvInitialiseNewTask+0x94>
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800ee72: 69fb ldr r3, [r7, #28]
|
|
800ee74: 3301 adds r3, #1
|
|
800ee76: 61fb str r3, [r7, #28]
|
|
800ee78: 69fb ldr r3, [r7, #28]
|
|
800ee7a: 2b0f cmp r3, #15
|
|
800ee7c: d9e9 bls.n 800ee52 <prvInitialiseNewTask+0x66>
|
|
800ee7e: e000 b.n 800ee82 <prvInitialiseNewTask+0x96>
|
|
{
|
|
break;
|
|
800ee80: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* Ensure the name string is terminated in the case that the string length
|
|
was greater or equal to configMAX_TASK_NAME_LEN. */
|
|
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
|
|
800ee82: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ee84: 2200 movs r2, #0
|
|
800ee86: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
800ee8a: e003 b.n 800ee94 <prvInitialiseNewTask+0xa8>
|
|
}
|
|
else
|
|
{
|
|
/* The task has not been given a name, so just ensure there is a NULL
|
|
terminator when it is read out. */
|
|
pxNewTCB->pcTaskName[ 0 ] = 0x00;
|
|
800ee8c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800ee8e: 2200 movs r2, #0
|
|
800ee90: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
}
|
|
|
|
/* This is used as an array index so must ensure it's not too large. First
|
|
remove the privilege bit if one is present. */
|
|
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
|
|
800ee94: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800ee96: 2b06 cmp r3, #6
|
|
800ee98: d901 bls.n 800ee9e <prvInitialiseNewTask+0xb2>
|
|
{
|
|
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
|
|
800ee9a: 2306 movs r3, #6
|
|
800ee9c: 62bb str r3, [r7, #40] ; 0x28
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxNewTCB->uxPriority = uxPriority;
|
|
800ee9e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eea0: 6aba ldr r2, [r7, #40] ; 0x28
|
|
800eea2: 62da str r2, [r3, #44] ; 0x2c
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
pxNewTCB->uxBasePriority = uxPriority;
|
|
800eea4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eea6: 6aba ldr r2, [r7, #40] ; 0x28
|
|
800eea8: 645a str r2, [r3, #68] ; 0x44
|
|
pxNewTCB->uxMutexesHeld = 0;
|
|
800eeaa: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eeac: 2200 movs r2, #0
|
|
800eeae: 649a str r2, [r3, #72] ; 0x48
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
|
|
800eeb0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eeb2: 3304 adds r3, #4
|
|
800eeb4: 4618 mov r0, r3
|
|
800eeb6: f7fe fe91 bl 800dbdc <vListInitialiseItem>
|
|
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
|
|
800eeba: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eebc: 3318 adds r3, #24
|
|
800eebe: 4618 mov r0, r3
|
|
800eec0: f7fe fe8c bl 800dbdc <vListInitialiseItem>
|
|
|
|
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
|
|
back to the containing TCB from a generic item in a list. */
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
|
|
800eec4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eec6: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
800eec8: 611a str r2, [r3, #16]
|
|
|
|
/* Event lists are always in priority order. */
|
|
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800eeca: 6abb ldr r3, [r7, #40] ; 0x28
|
|
800eecc: f1c3 0207 rsb r2, r3, #7
|
|
800eed0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eed2: 619a str r2, [r3, #24]
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
|
|
800eed4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eed6: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
800eed8: 625a str r2, [r3, #36] ; 0x24
|
|
}
|
|
#endif /* portCRITICAL_NESTING_IN_TCB */
|
|
|
|
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
|
|
{
|
|
pxNewTCB->pxTaskTag = NULL;
|
|
800eeda: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eedc: 2200 movs r2, #0
|
|
800eede: 64da str r2, [r3, #76] ; 0x4c
|
|
}
|
|
#endif
|
|
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
{
|
|
pxNewTCB->ulNotifiedValue = 0;
|
|
800eee0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eee2: 2200 movs r2, #0
|
|
800eee4: 651a str r2, [r3, #80] ; 0x50
|
|
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
|
|
800eee6: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eee8: 2200 movs r2, #0
|
|
800eeea: f883 2054 strb.w r2, [r3, #84] ; 0x54
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
}
|
|
#else /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
{
|
|
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
|
|
800eeee: 683a ldr r2, [r7, #0]
|
|
800eef0: 68f9 ldr r1, [r7, #12]
|
|
800eef2: 69b8 ldr r0, [r7, #24]
|
|
800eef4: f001 f84c bl 800ff90 <pxPortInitialiseStack>
|
|
800eef8: 4602 mov r2, r0
|
|
800eefa: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
800eefc: 601a str r2, [r3, #0]
|
|
}
|
|
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
}
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
|
|
if( pxCreatedTask != NULL )
|
|
800eefe: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800ef00: 2b00 cmp r3, #0
|
|
800ef02: d002 beq.n 800ef0a <prvInitialiseNewTask+0x11e>
|
|
{
|
|
/* Pass the handle out in an anonymous way. The handle can be used to
|
|
change the created task's priority, delete the created task, etc.*/
|
|
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
|
|
800ef04: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
800ef06: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
800ef08: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800ef0a: bf00 nop
|
|
800ef0c: 3720 adds r7, #32
|
|
800ef0e: 46bd mov sp, r7
|
|
800ef10: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800ef14 <prvAddNewTaskToReadyList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
|
|
{
|
|
800ef14: b580 push {r7, lr}
|
|
800ef16: b082 sub sp, #8
|
|
800ef18: af00 add r7, sp, #0
|
|
800ef1a: 6078 str r0, [r7, #4]
|
|
/* Ensure interrupts don't access the task lists while the lists are being
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800ef1c: f001 f944 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
uxCurrentNumberOfTasks++;
|
|
800ef20: 4b2a ldr r3, [pc, #168] ; (800efcc <prvAddNewTaskToReadyList+0xb8>)
|
|
800ef22: 681b ldr r3, [r3, #0]
|
|
800ef24: 3301 adds r3, #1
|
|
800ef26: 4a29 ldr r2, [pc, #164] ; (800efcc <prvAddNewTaskToReadyList+0xb8>)
|
|
800ef28: 6013 str r3, [r2, #0]
|
|
if( pxCurrentTCB == NULL )
|
|
800ef2a: 4b29 ldr r3, [pc, #164] ; (800efd0 <prvAddNewTaskToReadyList+0xbc>)
|
|
800ef2c: 681b ldr r3, [r3, #0]
|
|
800ef2e: 2b00 cmp r3, #0
|
|
800ef30: d109 bne.n 800ef46 <prvAddNewTaskToReadyList+0x32>
|
|
{
|
|
/* There are no other tasks, or all the other tasks are in
|
|
the suspended state - make this the current task. */
|
|
pxCurrentTCB = pxNewTCB;
|
|
800ef32: 4a27 ldr r2, [pc, #156] ; (800efd0 <prvAddNewTaskToReadyList+0xbc>)
|
|
800ef34: 687b ldr r3, [r7, #4]
|
|
800ef36: 6013 str r3, [r2, #0]
|
|
|
|
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
|
|
800ef38: 4b24 ldr r3, [pc, #144] ; (800efcc <prvAddNewTaskToReadyList+0xb8>)
|
|
800ef3a: 681b ldr r3, [r3, #0]
|
|
800ef3c: 2b01 cmp r3, #1
|
|
800ef3e: d110 bne.n 800ef62 <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
/* This is the first task to be created so do the preliminary
|
|
initialisation required. We will not recover if this call
|
|
fails, but we will report the failure. */
|
|
prvInitialiseTaskLists();
|
|
800ef40: f000 fd2e bl 800f9a0 <prvInitialiseTaskLists>
|
|
800ef44: e00d b.n 800ef62 <prvAddNewTaskToReadyList+0x4e>
|
|
else
|
|
{
|
|
/* If the scheduler is not already running, make this task the
|
|
current task if it is the highest priority task to be created
|
|
so far. */
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800ef46: 4b23 ldr r3, [pc, #140] ; (800efd4 <prvAddNewTaskToReadyList+0xc0>)
|
|
800ef48: 681b ldr r3, [r3, #0]
|
|
800ef4a: 2b00 cmp r3, #0
|
|
800ef4c: d109 bne.n 800ef62 <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
|
|
800ef4e: 4b20 ldr r3, [pc, #128] ; (800efd0 <prvAddNewTaskToReadyList+0xbc>)
|
|
800ef50: 681b ldr r3, [r3, #0]
|
|
800ef52: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800ef54: 687b ldr r3, [r7, #4]
|
|
800ef56: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800ef58: 429a cmp r2, r3
|
|
800ef5a: d802 bhi.n 800ef62 <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
pxCurrentTCB = pxNewTCB;
|
|
800ef5c: 4a1c ldr r2, [pc, #112] ; (800efd0 <prvAddNewTaskToReadyList+0xbc>)
|
|
800ef5e: 687b ldr r3, [r7, #4]
|
|
800ef60: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
uxTaskNumber++;
|
|
800ef62: 4b1d ldr r3, [pc, #116] ; (800efd8 <prvAddNewTaskToReadyList+0xc4>)
|
|
800ef64: 681b ldr r3, [r3, #0]
|
|
800ef66: 3301 adds r3, #1
|
|
800ef68: 4a1b ldr r2, [pc, #108] ; (800efd8 <prvAddNewTaskToReadyList+0xc4>)
|
|
800ef6a: 6013 str r3, [r2, #0]
|
|
pxNewTCB->uxTCBNumber = uxTaskNumber;
|
|
}
|
|
#endif /* configUSE_TRACE_FACILITY */
|
|
traceTASK_CREATE( pxNewTCB );
|
|
|
|
prvAddTaskToReadyList( pxNewTCB );
|
|
800ef6c: 687b ldr r3, [r7, #4]
|
|
800ef6e: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800ef70: 2201 movs r2, #1
|
|
800ef72: 409a lsls r2, r3
|
|
800ef74: 4b19 ldr r3, [pc, #100] ; (800efdc <prvAddNewTaskToReadyList+0xc8>)
|
|
800ef76: 681b ldr r3, [r3, #0]
|
|
800ef78: 4313 orrs r3, r2
|
|
800ef7a: 4a18 ldr r2, [pc, #96] ; (800efdc <prvAddNewTaskToReadyList+0xc8>)
|
|
800ef7c: 6013 str r3, [r2, #0]
|
|
800ef7e: 687b ldr r3, [r7, #4]
|
|
800ef80: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800ef82: 4613 mov r3, r2
|
|
800ef84: 009b lsls r3, r3, #2
|
|
800ef86: 4413 add r3, r2
|
|
800ef88: 009b lsls r3, r3, #2
|
|
800ef8a: 4a15 ldr r2, [pc, #84] ; (800efe0 <prvAddNewTaskToReadyList+0xcc>)
|
|
800ef8c: 441a add r2, r3
|
|
800ef8e: 687b ldr r3, [r7, #4]
|
|
800ef90: 3304 adds r3, #4
|
|
800ef92: 4619 mov r1, r3
|
|
800ef94: 4610 mov r0, r2
|
|
800ef96: f7fe fe2e bl 800dbf6 <vListInsertEnd>
|
|
|
|
portSETUP_TCB( pxNewTCB );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800ef9a: f001 f937 bl 801020c <vPortExitCritical>
|
|
|
|
if( xSchedulerRunning != pdFALSE )
|
|
800ef9e: 4b0d ldr r3, [pc, #52] ; (800efd4 <prvAddNewTaskToReadyList+0xc0>)
|
|
800efa0: 681b ldr r3, [r3, #0]
|
|
800efa2: 2b00 cmp r3, #0
|
|
800efa4: d00e beq.n 800efc4 <prvAddNewTaskToReadyList+0xb0>
|
|
{
|
|
/* If the created task is of a higher priority than the current task
|
|
then it should run now. */
|
|
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
|
|
800efa6: 4b0a ldr r3, [pc, #40] ; (800efd0 <prvAddNewTaskToReadyList+0xbc>)
|
|
800efa8: 681b ldr r3, [r3, #0]
|
|
800efaa: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800efac: 687b ldr r3, [r7, #4]
|
|
800efae: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800efb0: 429a cmp r2, r3
|
|
800efb2: d207 bcs.n 800efc4 <prvAddNewTaskToReadyList+0xb0>
|
|
{
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800efb4: 4b0b ldr r3, [pc, #44] ; (800efe4 <prvAddNewTaskToReadyList+0xd0>)
|
|
800efb6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800efba: 601a str r2, [r3, #0]
|
|
800efbc: f3bf 8f4f dsb sy
|
|
800efc0: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800efc4: bf00 nop
|
|
800efc6: 3708 adds r7, #8
|
|
800efc8: 46bd mov sp, r7
|
|
800efca: bd80 pop {r7, pc}
|
|
800efcc: 2000068c .word 0x2000068c
|
|
800efd0: 2000058c .word 0x2000058c
|
|
800efd4: 20000698 .word 0x20000698
|
|
800efd8: 200006a8 .word 0x200006a8
|
|
800efdc: 20000694 .word 0x20000694
|
|
800efe0: 20000590 .word 0x20000590
|
|
800efe4: e000ed04 .word 0xe000ed04
|
|
|
|
0800efe8 <vTaskDelete>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
|
|
void vTaskDelete( TaskHandle_t xTaskToDelete )
|
|
{
|
|
800efe8: b580 push {r7, lr}
|
|
800efea: b084 sub sp, #16
|
|
800efec: af00 add r7, sp, #0
|
|
800efee: 6078 str r0, [r7, #4]
|
|
TCB_t *pxTCB;
|
|
|
|
taskENTER_CRITICAL();
|
|
800eff0: f001 f8da bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
/* If null is passed in here then it is the calling task that is
|
|
being deleted. */
|
|
pxTCB = prvGetTCBFromHandle( xTaskToDelete );
|
|
800eff4: 687b ldr r3, [r7, #4]
|
|
800eff6: 2b00 cmp r3, #0
|
|
800eff8: d102 bne.n 800f000 <vTaskDelete+0x18>
|
|
800effa: 4b39 ldr r3, [pc, #228] ; (800f0e0 <vTaskDelete+0xf8>)
|
|
800effc: 681b ldr r3, [r3, #0]
|
|
800effe: e000 b.n 800f002 <vTaskDelete+0x1a>
|
|
800f000: 687b ldr r3, [r7, #4]
|
|
800f002: 60fb str r3, [r7, #12]
|
|
|
|
/* Remove task from the ready list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800f004: 68fb ldr r3, [r7, #12]
|
|
800f006: 3304 adds r3, #4
|
|
800f008: 4618 mov r0, r3
|
|
800f00a: f7fe fe51 bl 800dcb0 <uxListRemove>
|
|
800f00e: 4603 mov r3, r0
|
|
800f010: 2b00 cmp r3, #0
|
|
800f012: d115 bne.n 800f040 <vTaskDelete+0x58>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
|
|
800f014: 68fb ldr r3, [r7, #12]
|
|
800f016: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f018: 4932 ldr r1, [pc, #200] ; (800f0e4 <vTaskDelete+0xfc>)
|
|
800f01a: 4613 mov r3, r2
|
|
800f01c: 009b lsls r3, r3, #2
|
|
800f01e: 4413 add r3, r2
|
|
800f020: 009b lsls r3, r3, #2
|
|
800f022: 440b add r3, r1
|
|
800f024: 681b ldr r3, [r3, #0]
|
|
800f026: 2b00 cmp r3, #0
|
|
800f028: d10a bne.n 800f040 <vTaskDelete+0x58>
|
|
800f02a: 68fb ldr r3, [r7, #12]
|
|
800f02c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f02e: 2201 movs r2, #1
|
|
800f030: fa02 f303 lsl.w r3, r2, r3
|
|
800f034: 43da mvns r2, r3
|
|
800f036: 4b2c ldr r3, [pc, #176] ; (800f0e8 <vTaskDelete+0x100>)
|
|
800f038: 681b ldr r3, [r3, #0]
|
|
800f03a: 4013 ands r3, r2
|
|
800f03c: 4a2a ldr r2, [pc, #168] ; (800f0e8 <vTaskDelete+0x100>)
|
|
800f03e: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Is the task waiting on an event also? */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
800f040: 68fb ldr r3, [r7, #12]
|
|
800f042: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800f044: 2b00 cmp r3, #0
|
|
800f046: d004 beq.n 800f052 <vTaskDelete+0x6a>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800f048: 68fb ldr r3, [r7, #12]
|
|
800f04a: 3318 adds r3, #24
|
|
800f04c: 4618 mov r0, r3
|
|
800f04e: f7fe fe2f bl 800dcb0 <uxListRemove>
|
|
|
|
/* Increment the uxTaskNumber also so kernel aware debuggers can
|
|
detect that the task lists need re-generating. This is done before
|
|
portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
|
|
not return. */
|
|
uxTaskNumber++;
|
|
800f052: 4b26 ldr r3, [pc, #152] ; (800f0ec <vTaskDelete+0x104>)
|
|
800f054: 681b ldr r3, [r3, #0]
|
|
800f056: 3301 adds r3, #1
|
|
800f058: 4a24 ldr r2, [pc, #144] ; (800f0ec <vTaskDelete+0x104>)
|
|
800f05a: 6013 str r3, [r2, #0]
|
|
|
|
if( pxTCB == pxCurrentTCB )
|
|
800f05c: 4b20 ldr r3, [pc, #128] ; (800f0e0 <vTaskDelete+0xf8>)
|
|
800f05e: 681b ldr r3, [r3, #0]
|
|
800f060: 68fa ldr r2, [r7, #12]
|
|
800f062: 429a cmp r2, r3
|
|
800f064: d10b bne.n 800f07e <vTaskDelete+0x96>
|
|
/* A task is deleting itself. This cannot complete within the
|
|
task itself, as a context switch to another task is required.
|
|
Place the task in the termination list. The idle task will
|
|
check the termination list and free up any memory allocated by
|
|
the scheduler for the TCB and stack of the deleted task. */
|
|
vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
|
|
800f066: 68fb ldr r3, [r7, #12]
|
|
800f068: 3304 adds r3, #4
|
|
800f06a: 4619 mov r1, r3
|
|
800f06c: 4820 ldr r0, [pc, #128] ; (800f0f0 <vTaskDelete+0x108>)
|
|
800f06e: f7fe fdc2 bl 800dbf6 <vListInsertEnd>
|
|
|
|
/* Increment the ucTasksDeleted variable so the idle task knows
|
|
there is a task that has been deleted and that it should therefore
|
|
check the xTasksWaitingTermination list. */
|
|
++uxDeletedTasksWaitingCleanUp;
|
|
800f072: 4b20 ldr r3, [pc, #128] ; (800f0f4 <vTaskDelete+0x10c>)
|
|
800f074: 681b ldr r3, [r3, #0]
|
|
800f076: 3301 adds r3, #1
|
|
800f078: 4a1e ldr r2, [pc, #120] ; (800f0f4 <vTaskDelete+0x10c>)
|
|
800f07a: 6013 str r3, [r2, #0]
|
|
800f07c: e009 b.n 800f092 <vTaskDelete+0xaa>
|
|
required. */
|
|
portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
|
|
}
|
|
else
|
|
{
|
|
--uxCurrentNumberOfTasks;
|
|
800f07e: 4b1e ldr r3, [pc, #120] ; (800f0f8 <vTaskDelete+0x110>)
|
|
800f080: 681b ldr r3, [r3, #0]
|
|
800f082: 3b01 subs r3, #1
|
|
800f084: 4a1c ldr r2, [pc, #112] ; (800f0f8 <vTaskDelete+0x110>)
|
|
800f086: 6013 str r3, [r2, #0]
|
|
prvDeleteTCB( pxTCB );
|
|
800f088: 68f8 ldr r0, [r7, #12]
|
|
800f08a: f000 fcf5 bl 800fa78 <prvDeleteTCB>
|
|
|
|
/* Reset the next expected unblock time in case it referred to
|
|
the task that has just been deleted. */
|
|
prvResetNextTaskUnblockTime();
|
|
800f08e: f000 fd23 bl 800fad8 <prvResetNextTaskUnblockTime>
|
|
}
|
|
|
|
traceTASK_DELETE( pxTCB );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800f092: f001 f8bb bl 801020c <vPortExitCritical>
|
|
|
|
/* Force a reschedule if it is the currently running task that has just
|
|
been deleted. */
|
|
if( xSchedulerRunning != pdFALSE )
|
|
800f096: 4b19 ldr r3, [pc, #100] ; (800f0fc <vTaskDelete+0x114>)
|
|
800f098: 681b ldr r3, [r3, #0]
|
|
800f09a: 2b00 cmp r3, #0
|
|
800f09c: d01c beq.n 800f0d8 <vTaskDelete+0xf0>
|
|
{
|
|
if( pxTCB == pxCurrentTCB )
|
|
800f09e: 4b10 ldr r3, [pc, #64] ; (800f0e0 <vTaskDelete+0xf8>)
|
|
800f0a0: 681b ldr r3, [r3, #0]
|
|
800f0a2: 68fa ldr r2, [r7, #12]
|
|
800f0a4: 429a cmp r2, r3
|
|
800f0a6: d117 bne.n 800f0d8 <vTaskDelete+0xf0>
|
|
{
|
|
configASSERT( uxSchedulerSuspended == 0 );
|
|
800f0a8: 4b15 ldr r3, [pc, #84] ; (800f100 <vTaskDelete+0x118>)
|
|
800f0aa: 681b ldr r3, [r3, #0]
|
|
800f0ac: 2b00 cmp r3, #0
|
|
800f0ae: d00b beq.n 800f0c8 <vTaskDelete+0xe0>
|
|
800f0b0: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f0b4: b672 cpsid i
|
|
800f0b6: f383 8811 msr BASEPRI, r3
|
|
800f0ba: f3bf 8f6f isb sy
|
|
800f0be: f3bf 8f4f dsb sy
|
|
800f0c2: b662 cpsie i
|
|
800f0c4: 60bb str r3, [r7, #8]
|
|
800f0c6: e7fe b.n 800f0c6 <vTaskDelete+0xde>
|
|
portYIELD_WITHIN_API();
|
|
800f0c8: 4b0e ldr r3, [pc, #56] ; (800f104 <vTaskDelete+0x11c>)
|
|
800f0ca: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800f0ce: 601a str r2, [r3, #0]
|
|
800f0d0: f3bf 8f4f dsb sy
|
|
800f0d4: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
800f0d8: bf00 nop
|
|
800f0da: 3710 adds r7, #16
|
|
800f0dc: 46bd mov sp, r7
|
|
800f0de: bd80 pop {r7, pc}
|
|
800f0e0: 2000058c .word 0x2000058c
|
|
800f0e4: 20000590 .word 0x20000590
|
|
800f0e8: 20000694 .word 0x20000694
|
|
800f0ec: 200006a8 .word 0x200006a8
|
|
800f0f0: 20000660 .word 0x20000660
|
|
800f0f4: 20000674 .word 0x20000674
|
|
800f0f8: 2000068c .word 0x2000068c
|
|
800f0fc: 20000698 .word 0x20000698
|
|
800f100: 200006b4 .word 0x200006b4
|
|
800f104: e000ed04 .word 0xe000ed04
|
|
|
|
0800f108 <vTaskDelayUntil>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelayUntil == 1 )
|
|
|
|
void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
|
|
{
|
|
800f108: b580 push {r7, lr}
|
|
800f10a: b08a sub sp, #40 ; 0x28
|
|
800f10c: af00 add r7, sp, #0
|
|
800f10e: 6078 str r0, [r7, #4]
|
|
800f110: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
|
|
800f112: 2300 movs r3, #0
|
|
800f114: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
configASSERT( pxPreviousWakeTime );
|
|
800f116: 687b ldr r3, [r7, #4]
|
|
800f118: 2b00 cmp r3, #0
|
|
800f11a: d10b bne.n 800f134 <vTaskDelayUntil+0x2c>
|
|
800f11c: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f120: b672 cpsid i
|
|
800f122: f383 8811 msr BASEPRI, r3
|
|
800f126: f3bf 8f6f isb sy
|
|
800f12a: f3bf 8f4f dsb sy
|
|
800f12e: b662 cpsie i
|
|
800f130: 617b str r3, [r7, #20]
|
|
800f132: e7fe b.n 800f132 <vTaskDelayUntil+0x2a>
|
|
configASSERT( ( xTimeIncrement > 0U ) );
|
|
800f134: 683b ldr r3, [r7, #0]
|
|
800f136: 2b00 cmp r3, #0
|
|
800f138: d10b bne.n 800f152 <vTaskDelayUntil+0x4a>
|
|
800f13a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f13e: b672 cpsid i
|
|
800f140: f383 8811 msr BASEPRI, r3
|
|
800f144: f3bf 8f6f isb sy
|
|
800f148: f3bf 8f4f dsb sy
|
|
800f14c: b662 cpsie i
|
|
800f14e: 613b str r3, [r7, #16]
|
|
800f150: e7fe b.n 800f150 <vTaskDelayUntil+0x48>
|
|
configASSERT( uxSchedulerSuspended == 0 );
|
|
800f152: 4b2a ldr r3, [pc, #168] ; (800f1fc <vTaskDelayUntil+0xf4>)
|
|
800f154: 681b ldr r3, [r3, #0]
|
|
800f156: 2b00 cmp r3, #0
|
|
800f158: d00b beq.n 800f172 <vTaskDelayUntil+0x6a>
|
|
800f15a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f15e: b672 cpsid i
|
|
800f160: f383 8811 msr BASEPRI, r3
|
|
800f164: f3bf 8f6f isb sy
|
|
800f168: f3bf 8f4f dsb sy
|
|
800f16c: b662 cpsie i
|
|
800f16e: 60fb str r3, [r7, #12]
|
|
800f170: e7fe b.n 800f170 <vTaskDelayUntil+0x68>
|
|
|
|
vTaskSuspendAll();
|
|
800f172: f000 f8e1 bl 800f338 <vTaskSuspendAll>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800f176: 4b22 ldr r3, [pc, #136] ; (800f200 <vTaskDelayUntil+0xf8>)
|
|
800f178: 681b ldr r3, [r3, #0]
|
|
800f17a: 623b str r3, [r7, #32]
|
|
|
|
/* Generate the tick time at which the task wants to wake. */
|
|
xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
|
|
800f17c: 687b ldr r3, [r7, #4]
|
|
800f17e: 681b ldr r3, [r3, #0]
|
|
800f180: 683a ldr r2, [r7, #0]
|
|
800f182: 4413 add r3, r2
|
|
800f184: 61fb str r3, [r7, #28]
|
|
|
|
if( xConstTickCount < *pxPreviousWakeTime )
|
|
800f186: 687b ldr r3, [r7, #4]
|
|
800f188: 681b ldr r3, [r3, #0]
|
|
800f18a: 6a3a ldr r2, [r7, #32]
|
|
800f18c: 429a cmp r2, r3
|
|
800f18e: d20b bcs.n 800f1a8 <vTaskDelayUntil+0xa0>
|
|
/* The tick count has overflowed since this function was
|
|
lasted called. In this case the only time we should ever
|
|
actually delay is if the wake time has also overflowed,
|
|
and the wake time is greater than the tick time. When this
|
|
is the case it is as if neither time had overflowed. */
|
|
if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
|
|
800f190: 687b ldr r3, [r7, #4]
|
|
800f192: 681b ldr r3, [r3, #0]
|
|
800f194: 69fa ldr r2, [r7, #28]
|
|
800f196: 429a cmp r2, r3
|
|
800f198: d211 bcs.n 800f1be <vTaskDelayUntil+0xb6>
|
|
800f19a: 69fa ldr r2, [r7, #28]
|
|
800f19c: 6a3b ldr r3, [r7, #32]
|
|
800f19e: 429a cmp r2, r3
|
|
800f1a0: d90d bls.n 800f1be <vTaskDelayUntil+0xb6>
|
|
{
|
|
xShouldDelay = pdTRUE;
|
|
800f1a2: 2301 movs r3, #1
|
|
800f1a4: 627b str r3, [r7, #36] ; 0x24
|
|
800f1a6: e00a b.n 800f1be <vTaskDelayUntil+0xb6>
|
|
else
|
|
{
|
|
/* The tick time has not overflowed. In this case we will
|
|
delay if either the wake time has overflowed, and/or the
|
|
tick time is less than the wake time. */
|
|
if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
|
|
800f1a8: 687b ldr r3, [r7, #4]
|
|
800f1aa: 681b ldr r3, [r3, #0]
|
|
800f1ac: 69fa ldr r2, [r7, #28]
|
|
800f1ae: 429a cmp r2, r3
|
|
800f1b0: d303 bcc.n 800f1ba <vTaskDelayUntil+0xb2>
|
|
800f1b2: 69fa ldr r2, [r7, #28]
|
|
800f1b4: 6a3b ldr r3, [r7, #32]
|
|
800f1b6: 429a cmp r2, r3
|
|
800f1b8: d901 bls.n 800f1be <vTaskDelayUntil+0xb6>
|
|
{
|
|
xShouldDelay = pdTRUE;
|
|
800f1ba: 2301 movs r3, #1
|
|
800f1bc: 627b str r3, [r7, #36] ; 0x24
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
/* Update the wake time ready for the next call. */
|
|
*pxPreviousWakeTime = xTimeToWake;
|
|
800f1be: 687b ldr r3, [r7, #4]
|
|
800f1c0: 69fa ldr r2, [r7, #28]
|
|
800f1c2: 601a str r2, [r3, #0]
|
|
|
|
if( xShouldDelay != pdFALSE )
|
|
800f1c4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
800f1c6: 2b00 cmp r3, #0
|
|
800f1c8: d006 beq.n 800f1d8 <vTaskDelayUntil+0xd0>
|
|
{
|
|
traceTASK_DELAY_UNTIL( xTimeToWake );
|
|
|
|
/* prvAddCurrentTaskToDelayedList() needs the block time, not
|
|
the time to wake, so subtract the current tick count. */
|
|
prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
|
|
800f1ca: 69fa ldr r2, [r7, #28]
|
|
800f1cc: 6a3b ldr r3, [r7, #32]
|
|
800f1ce: 1ad3 subs r3, r2, r3
|
|
800f1d0: 2100 movs r1, #0
|
|
800f1d2: 4618 mov r0, r3
|
|
800f1d4: f000 fe76 bl 800fec4 <prvAddCurrentTaskToDelayedList>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
xAlreadyYielded = xTaskResumeAll();
|
|
800f1d8: f000 f8bc bl 800f354 <xTaskResumeAll>
|
|
800f1dc: 61b8 str r0, [r7, #24]
|
|
|
|
/* Force a reschedule if xTaskResumeAll has not already done so, we may
|
|
have put ourselves to sleep. */
|
|
if( xAlreadyYielded == pdFALSE )
|
|
800f1de: 69bb ldr r3, [r7, #24]
|
|
800f1e0: 2b00 cmp r3, #0
|
|
800f1e2: d107 bne.n 800f1f4 <vTaskDelayUntil+0xec>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800f1e4: 4b07 ldr r3, [pc, #28] ; (800f204 <vTaskDelayUntil+0xfc>)
|
|
800f1e6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800f1ea: 601a str r2, [r3, #0]
|
|
800f1ec: f3bf 8f4f dsb sy
|
|
800f1f0: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800f1f4: bf00 nop
|
|
800f1f6: 3728 adds r7, #40 ; 0x28
|
|
800f1f8: 46bd mov sp, r7
|
|
800f1fa: bd80 pop {r7, pc}
|
|
800f1fc: 200006b4 .word 0x200006b4
|
|
800f200: 20000690 .word 0x20000690
|
|
800f204: e000ed04 .word 0xe000ed04
|
|
|
|
0800f208 <vTaskDelay>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelay == 1 )
|
|
|
|
void vTaskDelay( const TickType_t xTicksToDelay )
|
|
{
|
|
800f208: b580 push {r7, lr}
|
|
800f20a: b084 sub sp, #16
|
|
800f20c: af00 add r7, sp, #0
|
|
800f20e: 6078 str r0, [r7, #4]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
800f210: 2300 movs r3, #0
|
|
800f212: 60fb str r3, [r7, #12]
|
|
|
|
/* A delay time of zero just forces a reschedule. */
|
|
if( xTicksToDelay > ( TickType_t ) 0U )
|
|
800f214: 687b ldr r3, [r7, #4]
|
|
800f216: 2b00 cmp r3, #0
|
|
800f218: d018 beq.n 800f24c <vTaskDelay+0x44>
|
|
{
|
|
configASSERT( uxSchedulerSuspended == 0 );
|
|
800f21a: 4b14 ldr r3, [pc, #80] ; (800f26c <vTaskDelay+0x64>)
|
|
800f21c: 681b ldr r3, [r3, #0]
|
|
800f21e: 2b00 cmp r3, #0
|
|
800f220: d00b beq.n 800f23a <vTaskDelay+0x32>
|
|
800f222: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f226: b672 cpsid i
|
|
800f228: f383 8811 msr BASEPRI, r3
|
|
800f22c: f3bf 8f6f isb sy
|
|
800f230: f3bf 8f4f dsb sy
|
|
800f234: b662 cpsie i
|
|
800f236: 60bb str r3, [r7, #8]
|
|
800f238: e7fe b.n 800f238 <vTaskDelay+0x30>
|
|
vTaskSuspendAll();
|
|
800f23a: f000 f87d bl 800f338 <vTaskSuspendAll>
|
|
list or removed from the blocked list until the scheduler
|
|
is resumed.
|
|
|
|
This task cannot be in an event list as it is the currently
|
|
executing task. */
|
|
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
|
|
800f23e: 2100 movs r1, #0
|
|
800f240: 6878 ldr r0, [r7, #4]
|
|
800f242: f000 fe3f bl 800fec4 <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
xAlreadyYielded = xTaskResumeAll();
|
|
800f246: f000 f885 bl 800f354 <xTaskResumeAll>
|
|
800f24a: 60f8 str r0, [r7, #12]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Force a reschedule if xTaskResumeAll has not already done so, we may
|
|
have put ourselves to sleep. */
|
|
if( xAlreadyYielded == pdFALSE )
|
|
800f24c: 68fb ldr r3, [r7, #12]
|
|
800f24e: 2b00 cmp r3, #0
|
|
800f250: d107 bne.n 800f262 <vTaskDelay+0x5a>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800f252: 4b07 ldr r3, [pc, #28] ; (800f270 <vTaskDelay+0x68>)
|
|
800f254: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800f258: 601a str r2, [r3, #0]
|
|
800f25a: f3bf 8f4f dsb sy
|
|
800f25e: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800f262: bf00 nop
|
|
800f264: 3710 adds r7, #16
|
|
800f266: 46bd mov sp, r7
|
|
800f268: bd80 pop {r7, pc}
|
|
800f26a: bf00 nop
|
|
800f26c: 200006b4 .word 0x200006b4
|
|
800f270: e000ed04 .word 0xe000ed04
|
|
|
|
0800f274 <vTaskStartScheduler>:
|
|
|
|
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskStartScheduler( void )
|
|
{
|
|
800f274: b580 push {r7, lr}
|
|
800f276: b08a sub sp, #40 ; 0x28
|
|
800f278: af04 add r7, sp, #16
|
|
BaseType_t xReturn;
|
|
|
|
/* Add the idle task at the lowest priority. */
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
|
|
800f27a: 2300 movs r3, #0
|
|
800f27c: 60bb str r3, [r7, #8]
|
|
StackType_t *pxIdleTaskStackBuffer = NULL;
|
|
800f27e: 2300 movs r3, #0
|
|
800f280: 607b str r3, [r7, #4]
|
|
uint32_t ulIdleTaskStackSize;
|
|
|
|
/* The Idle task is created using user provided RAM - obtain the
|
|
address of the RAM then create the idle task. */
|
|
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
|
|
800f282: 463a mov r2, r7
|
|
800f284: 1d39 adds r1, r7, #4
|
|
800f286: f107 0308 add.w r3, r7, #8
|
|
800f28a: 4618 mov r0, r3
|
|
800f28c: f7f1 f9aa bl 80005e4 <vApplicationGetIdleTaskMemory>
|
|
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
|
|
800f290: 6839 ldr r1, [r7, #0]
|
|
800f292: 687b ldr r3, [r7, #4]
|
|
800f294: 68ba ldr r2, [r7, #8]
|
|
800f296: 9202 str r2, [sp, #8]
|
|
800f298: 9301 str r3, [sp, #4]
|
|
800f29a: 2300 movs r3, #0
|
|
800f29c: 9300 str r3, [sp, #0]
|
|
800f29e: 2300 movs r3, #0
|
|
800f2a0: 460a mov r2, r1
|
|
800f2a2: 491f ldr r1, [pc, #124] ; (800f320 <vTaskStartScheduler+0xac>)
|
|
800f2a4: 481f ldr r0, [pc, #124] ; (800f324 <vTaskStartScheduler+0xb0>)
|
|
800f2a6: f7ff fcfc bl 800eca2 <xTaskCreateStatic>
|
|
800f2aa: 4602 mov r2, r0
|
|
800f2ac: 4b1e ldr r3, [pc, #120] ; (800f328 <vTaskStartScheduler+0xb4>)
|
|
800f2ae: 601a str r2, [r3, #0]
|
|
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
|
|
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
|
|
pxIdleTaskStackBuffer,
|
|
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
|
|
|
|
if( xIdleTaskHandle != NULL )
|
|
800f2b0: 4b1d ldr r3, [pc, #116] ; (800f328 <vTaskStartScheduler+0xb4>)
|
|
800f2b2: 681b ldr r3, [r3, #0]
|
|
800f2b4: 2b00 cmp r3, #0
|
|
800f2b6: d002 beq.n 800f2be <vTaskStartScheduler+0x4a>
|
|
{
|
|
xReturn = pdPASS;
|
|
800f2b8: 2301 movs r3, #1
|
|
800f2ba: 617b str r3, [r7, #20]
|
|
800f2bc: e001 b.n 800f2c2 <vTaskStartScheduler+0x4e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
800f2be: 2300 movs r3, #0
|
|
800f2c0: 617b str r3, [r7, #20]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_TIMERS */
|
|
|
|
if( xReturn == pdPASS )
|
|
800f2c2: 697b ldr r3, [r7, #20]
|
|
800f2c4: 2b01 cmp r3, #1
|
|
800f2c6: d117 bne.n 800f2f8 <vTaskStartScheduler+0x84>
|
|
800f2c8: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f2cc: b672 cpsid i
|
|
800f2ce: f383 8811 msr BASEPRI, r3
|
|
800f2d2: f3bf 8f6f isb sy
|
|
800f2d6: f3bf 8f4f dsb sy
|
|
800f2da: b662 cpsie i
|
|
800f2dc: 613b str r3, [r7, #16]
|
|
structure specific to the task that will run first. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800f2de: 4b13 ldr r3, [pc, #76] ; (800f32c <vTaskStartScheduler+0xb8>)
|
|
800f2e0: f04f 32ff mov.w r2, #4294967295
|
|
800f2e4: 601a str r2, [r3, #0]
|
|
xSchedulerRunning = pdTRUE;
|
|
800f2e6: 4b12 ldr r3, [pc, #72] ; (800f330 <vTaskStartScheduler+0xbc>)
|
|
800f2e8: 2201 movs r2, #1
|
|
800f2ea: 601a str r2, [r3, #0]
|
|
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
|
|
800f2ec: 4b11 ldr r3, [pc, #68] ; (800f334 <vTaskStartScheduler+0xc0>)
|
|
800f2ee: 2200 movs r2, #0
|
|
800f2f0: 601a str r2, [r3, #0]
|
|
|
|
traceTASK_SWITCHED_IN();
|
|
|
|
/* Setting up the timer tick is hardware specific and thus in the
|
|
portable interface. */
|
|
if( xPortStartScheduler() != pdFALSE )
|
|
800f2f2: f000 fedd bl 80100b0 <xPortStartScheduler>
|
|
}
|
|
|
|
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
|
|
meaning xIdleTaskHandle is not used anywhere else. */
|
|
( void ) xIdleTaskHandle;
|
|
}
|
|
800f2f6: e00f b.n 800f318 <vTaskStartScheduler+0xa4>
|
|
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
|
|
800f2f8: 697b ldr r3, [r7, #20]
|
|
800f2fa: f1b3 3fff cmp.w r3, #4294967295
|
|
800f2fe: d10b bne.n 800f318 <vTaskStartScheduler+0xa4>
|
|
800f300: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f304: b672 cpsid i
|
|
800f306: f383 8811 msr BASEPRI, r3
|
|
800f30a: f3bf 8f6f isb sy
|
|
800f30e: f3bf 8f4f dsb sy
|
|
800f312: b662 cpsie i
|
|
800f314: 60fb str r3, [r7, #12]
|
|
800f316: e7fe b.n 800f316 <vTaskStartScheduler+0xa2>
|
|
}
|
|
800f318: bf00 nop
|
|
800f31a: 3718 adds r7, #24
|
|
800f31c: 46bd mov sp, r7
|
|
800f31e: bd80 pop {r7, pc}
|
|
800f320: 0801dfcc .word 0x0801dfcc
|
|
800f324: 0800f96d .word 0x0800f96d
|
|
800f328: 200006b0 .word 0x200006b0
|
|
800f32c: 200006ac .word 0x200006ac
|
|
800f330: 20000698 .word 0x20000698
|
|
800f334: 20000690 .word 0x20000690
|
|
|
|
0800f338 <vTaskSuspendAll>:
|
|
vPortEndScheduler();
|
|
}
|
|
/*----------------------------------------------------------*/
|
|
|
|
void vTaskSuspendAll( void )
|
|
{
|
|
800f338: b480 push {r7}
|
|
800f33a: af00 add r7, sp, #0
|
|
/* A critical section is not required as the variable is of type
|
|
BaseType_t. Please read Richard Barry's reply in the following link to a
|
|
post in the FreeRTOS support forum before reporting this as a bug! -
|
|
http://goo.gl/wu4acr */
|
|
++uxSchedulerSuspended;
|
|
800f33c: 4b04 ldr r3, [pc, #16] ; (800f350 <vTaskSuspendAll+0x18>)
|
|
800f33e: 681b ldr r3, [r3, #0]
|
|
800f340: 3301 adds r3, #1
|
|
800f342: 4a03 ldr r2, [pc, #12] ; (800f350 <vTaskSuspendAll+0x18>)
|
|
800f344: 6013 str r3, [r2, #0]
|
|
portMEMORY_BARRIER();
|
|
}
|
|
800f346: bf00 nop
|
|
800f348: 46bd mov sp, r7
|
|
800f34a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f34e: 4770 bx lr
|
|
800f350: 200006b4 .word 0x200006b4
|
|
|
|
0800f354 <xTaskResumeAll>:
|
|
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskResumeAll( void )
|
|
{
|
|
800f354: b580 push {r7, lr}
|
|
800f356: b084 sub sp, #16
|
|
800f358: af00 add r7, sp, #0
|
|
TCB_t *pxTCB = NULL;
|
|
800f35a: 2300 movs r3, #0
|
|
800f35c: 60fb str r3, [r7, #12]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
800f35e: 2300 movs r3, #0
|
|
800f360: 60bb str r3, [r7, #8]
|
|
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
|
previous call to vTaskSuspendAll(). */
|
|
configASSERT( uxSchedulerSuspended );
|
|
800f362: 4b42 ldr r3, [pc, #264] ; (800f46c <xTaskResumeAll+0x118>)
|
|
800f364: 681b ldr r3, [r3, #0]
|
|
800f366: 2b00 cmp r3, #0
|
|
800f368: d10b bne.n 800f382 <xTaskResumeAll+0x2e>
|
|
800f36a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f36e: b672 cpsid i
|
|
800f370: f383 8811 msr BASEPRI, r3
|
|
800f374: f3bf 8f6f isb sy
|
|
800f378: f3bf 8f4f dsb sy
|
|
800f37c: b662 cpsie i
|
|
800f37e: 603b str r3, [r7, #0]
|
|
800f380: e7fe b.n 800f380 <xTaskResumeAll+0x2c>
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
|
list while the scheduler was suspended. If this was the case then the
|
|
removed task will have been added to the xPendingReadyList. Once the
|
|
scheduler has been resumed it is safe to move all the pending ready
|
|
tasks from this list into their appropriate ready list. */
|
|
taskENTER_CRITICAL();
|
|
800f382: f000 ff11 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
--uxSchedulerSuspended;
|
|
800f386: 4b39 ldr r3, [pc, #228] ; (800f46c <xTaskResumeAll+0x118>)
|
|
800f388: 681b ldr r3, [r3, #0]
|
|
800f38a: 3b01 subs r3, #1
|
|
800f38c: 4a37 ldr r2, [pc, #220] ; (800f46c <xTaskResumeAll+0x118>)
|
|
800f38e: 6013 str r3, [r2, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800f390: 4b36 ldr r3, [pc, #216] ; (800f46c <xTaskResumeAll+0x118>)
|
|
800f392: 681b ldr r3, [r3, #0]
|
|
800f394: 2b00 cmp r3, #0
|
|
800f396: d161 bne.n 800f45c <xTaskResumeAll+0x108>
|
|
{
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
|
800f398: 4b35 ldr r3, [pc, #212] ; (800f470 <xTaskResumeAll+0x11c>)
|
|
800f39a: 681b ldr r3, [r3, #0]
|
|
800f39c: 2b00 cmp r3, #0
|
|
800f39e: d05d beq.n 800f45c <xTaskResumeAll+0x108>
|
|
{
|
|
/* Move any readied tasks from the pending list into the
|
|
appropriate ready list. */
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800f3a0: e02e b.n 800f400 <xTaskResumeAll+0xac>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800f3a2: 4b34 ldr r3, [pc, #208] ; (800f474 <xTaskResumeAll+0x120>)
|
|
800f3a4: 68db ldr r3, [r3, #12]
|
|
800f3a6: 68db ldr r3, [r3, #12]
|
|
800f3a8: 60fb str r3, [r7, #12]
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800f3aa: 68fb ldr r3, [r7, #12]
|
|
800f3ac: 3318 adds r3, #24
|
|
800f3ae: 4618 mov r0, r3
|
|
800f3b0: f7fe fc7e bl 800dcb0 <uxListRemove>
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800f3b4: 68fb ldr r3, [r7, #12]
|
|
800f3b6: 3304 adds r3, #4
|
|
800f3b8: 4618 mov r0, r3
|
|
800f3ba: f7fe fc79 bl 800dcb0 <uxListRemove>
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800f3be: 68fb ldr r3, [r7, #12]
|
|
800f3c0: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f3c2: 2201 movs r2, #1
|
|
800f3c4: 409a lsls r2, r3
|
|
800f3c6: 4b2c ldr r3, [pc, #176] ; (800f478 <xTaskResumeAll+0x124>)
|
|
800f3c8: 681b ldr r3, [r3, #0]
|
|
800f3ca: 4313 orrs r3, r2
|
|
800f3cc: 4a2a ldr r2, [pc, #168] ; (800f478 <xTaskResumeAll+0x124>)
|
|
800f3ce: 6013 str r3, [r2, #0]
|
|
800f3d0: 68fb ldr r3, [r7, #12]
|
|
800f3d2: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f3d4: 4613 mov r3, r2
|
|
800f3d6: 009b lsls r3, r3, #2
|
|
800f3d8: 4413 add r3, r2
|
|
800f3da: 009b lsls r3, r3, #2
|
|
800f3dc: 4a27 ldr r2, [pc, #156] ; (800f47c <xTaskResumeAll+0x128>)
|
|
800f3de: 441a add r2, r3
|
|
800f3e0: 68fb ldr r3, [r7, #12]
|
|
800f3e2: 3304 adds r3, #4
|
|
800f3e4: 4619 mov r1, r3
|
|
800f3e6: 4610 mov r0, r2
|
|
800f3e8: f7fe fc05 bl 800dbf6 <vListInsertEnd>
|
|
|
|
/* If the moved task has a priority higher than the current
|
|
task then a yield must be performed. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800f3ec: 68fb ldr r3, [r7, #12]
|
|
800f3ee: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f3f0: 4b23 ldr r3, [pc, #140] ; (800f480 <xTaskResumeAll+0x12c>)
|
|
800f3f2: 681b ldr r3, [r3, #0]
|
|
800f3f4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f3f6: 429a cmp r2, r3
|
|
800f3f8: d302 bcc.n 800f400 <xTaskResumeAll+0xac>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800f3fa: 4b22 ldr r3, [pc, #136] ; (800f484 <xTaskResumeAll+0x130>)
|
|
800f3fc: 2201 movs r2, #1
|
|
800f3fe: 601a str r2, [r3, #0]
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800f400: 4b1c ldr r3, [pc, #112] ; (800f474 <xTaskResumeAll+0x120>)
|
|
800f402: 681b ldr r3, [r3, #0]
|
|
800f404: 2b00 cmp r3, #0
|
|
800f406: d1cc bne.n 800f3a2 <xTaskResumeAll+0x4e>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( pxTCB != NULL )
|
|
800f408: 68fb ldr r3, [r7, #12]
|
|
800f40a: 2b00 cmp r3, #0
|
|
800f40c: d001 beq.n 800f412 <xTaskResumeAll+0xbe>
|
|
which may have prevented the next unblock time from being
|
|
re-calculated, in which case re-calculate it now. Mainly
|
|
important for low power tickless implementations, where
|
|
this can prevent an unnecessary exit from low power
|
|
state. */
|
|
prvResetNextTaskUnblockTime();
|
|
800f40e: f000 fb63 bl 800fad8 <prvResetNextTaskUnblockTime>
|
|
/* If any ticks occurred while the scheduler was suspended then
|
|
they should be processed now. This ensures the tick count does
|
|
not slip, and that any delayed tasks are resumed at the correct
|
|
time. */
|
|
{
|
|
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
|
|
800f412: 4b1d ldr r3, [pc, #116] ; (800f488 <xTaskResumeAll+0x134>)
|
|
800f414: 681b ldr r3, [r3, #0]
|
|
800f416: 607b str r3, [r7, #4]
|
|
|
|
if( uxPendedCounts > ( UBaseType_t ) 0U )
|
|
800f418: 687b ldr r3, [r7, #4]
|
|
800f41a: 2b00 cmp r3, #0
|
|
800f41c: d010 beq.n 800f440 <xTaskResumeAll+0xec>
|
|
{
|
|
do
|
|
{
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800f41e: f000 f859 bl 800f4d4 <xTaskIncrementTick>
|
|
800f422: 4603 mov r3, r0
|
|
800f424: 2b00 cmp r3, #0
|
|
800f426: d002 beq.n 800f42e <xTaskResumeAll+0xda>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800f428: 4b16 ldr r3, [pc, #88] ; (800f484 <xTaskResumeAll+0x130>)
|
|
800f42a: 2201 movs r2, #1
|
|
800f42c: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
--uxPendedCounts;
|
|
800f42e: 687b ldr r3, [r7, #4]
|
|
800f430: 3b01 subs r3, #1
|
|
800f432: 607b str r3, [r7, #4]
|
|
} while( uxPendedCounts > ( UBaseType_t ) 0U );
|
|
800f434: 687b ldr r3, [r7, #4]
|
|
800f436: 2b00 cmp r3, #0
|
|
800f438: d1f1 bne.n 800f41e <xTaskResumeAll+0xca>
|
|
|
|
uxPendedTicks = 0;
|
|
800f43a: 4b13 ldr r3, [pc, #76] ; (800f488 <xTaskResumeAll+0x134>)
|
|
800f43c: 2200 movs r2, #0
|
|
800f43e: 601a str r2, [r3, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( xYieldPending != pdFALSE )
|
|
800f440: 4b10 ldr r3, [pc, #64] ; (800f484 <xTaskResumeAll+0x130>)
|
|
800f442: 681b ldr r3, [r3, #0]
|
|
800f444: 2b00 cmp r3, #0
|
|
800f446: d009 beq.n 800f45c <xTaskResumeAll+0x108>
|
|
{
|
|
#if( configUSE_PREEMPTION != 0 )
|
|
{
|
|
xAlreadyYielded = pdTRUE;
|
|
800f448: 2301 movs r3, #1
|
|
800f44a: 60bb str r3, [r7, #8]
|
|
}
|
|
#endif
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800f44c: 4b0f ldr r3, [pc, #60] ; (800f48c <xTaskResumeAll+0x138>)
|
|
800f44e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800f452: 601a str r2, [r3, #0]
|
|
800f454: f3bf 8f4f dsb sy
|
|
800f458: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800f45c: f000 fed6 bl 801020c <vPortExitCritical>
|
|
|
|
return xAlreadyYielded;
|
|
800f460: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800f462: 4618 mov r0, r3
|
|
800f464: 3710 adds r7, #16
|
|
800f466: 46bd mov sp, r7
|
|
800f468: bd80 pop {r7, pc}
|
|
800f46a: bf00 nop
|
|
800f46c: 200006b4 .word 0x200006b4
|
|
800f470: 2000068c .word 0x2000068c
|
|
800f474: 2000064c .word 0x2000064c
|
|
800f478: 20000694 .word 0x20000694
|
|
800f47c: 20000590 .word 0x20000590
|
|
800f480: 2000058c .word 0x2000058c
|
|
800f484: 200006a0 .word 0x200006a0
|
|
800f488: 2000069c .word 0x2000069c
|
|
800f48c: e000ed04 .word 0xe000ed04
|
|
|
|
0800f490 <xTaskGetTickCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
TickType_t xTaskGetTickCount( void )
|
|
{
|
|
800f490: b480 push {r7}
|
|
800f492: b083 sub sp, #12
|
|
800f494: af00 add r7, sp, #0
|
|
TickType_t xTicks;
|
|
|
|
/* Critical section required if running on a 16 bit processor. */
|
|
portTICK_TYPE_ENTER_CRITICAL();
|
|
{
|
|
xTicks = xTickCount;
|
|
800f496: 4b05 ldr r3, [pc, #20] ; (800f4ac <xTaskGetTickCount+0x1c>)
|
|
800f498: 681b ldr r3, [r3, #0]
|
|
800f49a: 607b str r3, [r7, #4]
|
|
}
|
|
portTICK_TYPE_EXIT_CRITICAL();
|
|
|
|
return xTicks;
|
|
800f49c: 687b ldr r3, [r7, #4]
|
|
}
|
|
800f49e: 4618 mov r0, r3
|
|
800f4a0: 370c adds r7, #12
|
|
800f4a2: 46bd mov sp, r7
|
|
800f4a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f4a8: 4770 bx lr
|
|
800f4aa: bf00 nop
|
|
800f4ac: 20000690 .word 0x20000690
|
|
|
|
0800f4b0 <xTaskGetTickCountFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
TickType_t xTaskGetTickCountFromISR( void )
|
|
{
|
|
800f4b0: b580 push {r7, lr}
|
|
800f4b2: b082 sub sp, #8
|
|
800f4b4: af00 add r7, sp, #0
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800f4b6: f000 ff57 bl 8010368 <vPortValidateInterruptPriority>
|
|
|
|
uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
|
|
800f4ba: 2300 movs r3, #0
|
|
800f4bc: 607b str r3, [r7, #4]
|
|
{
|
|
xReturn = xTickCount;
|
|
800f4be: 4b04 ldr r3, [pc, #16] ; (800f4d0 <xTaskGetTickCountFromISR+0x20>)
|
|
800f4c0: 681b ldr r3, [r3, #0]
|
|
800f4c2: 603b str r3, [r7, #0]
|
|
}
|
|
portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800f4c4: 683b ldr r3, [r7, #0]
|
|
}
|
|
800f4c6: 4618 mov r0, r3
|
|
800f4c8: 3708 adds r7, #8
|
|
800f4ca: 46bd mov sp, r7
|
|
800f4cc: bd80 pop {r7, pc}
|
|
800f4ce: bf00 nop
|
|
800f4d0: 20000690 .word 0x20000690
|
|
|
|
0800f4d4 <xTaskIncrementTick>:
|
|
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskIncrementTick( void )
|
|
{
|
|
800f4d4: b580 push {r7, lr}
|
|
800f4d6: b086 sub sp, #24
|
|
800f4d8: af00 add r7, sp, #0
|
|
TCB_t * pxTCB;
|
|
TickType_t xItemValue;
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
|
800f4da: 2300 movs r3, #0
|
|
800f4dc: 617b str r3, [r7, #20]
|
|
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
|
Increments the tick then checks to see if the new tick value will cause any
|
|
tasks to be unblocked. */
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800f4de: 4b4f ldr r3, [pc, #316] ; (800f61c <xTaskIncrementTick+0x148>)
|
|
800f4e0: 681b ldr r3, [r3, #0]
|
|
800f4e2: 2b00 cmp r3, #0
|
|
800f4e4: f040 8089 bne.w 800f5fa <xTaskIncrementTick+0x126>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
block. */
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
|
800f4e8: 4b4d ldr r3, [pc, #308] ; (800f620 <xTaskIncrementTick+0x14c>)
|
|
800f4ea: 681b ldr r3, [r3, #0]
|
|
800f4ec: 3301 adds r3, #1
|
|
800f4ee: 613b str r3, [r7, #16]
|
|
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
|
delayed lists if it wraps to 0. */
|
|
xTickCount = xConstTickCount;
|
|
800f4f0: 4a4b ldr r2, [pc, #300] ; (800f620 <xTaskIncrementTick+0x14c>)
|
|
800f4f2: 693b ldr r3, [r7, #16]
|
|
800f4f4: 6013 str r3, [r2, #0]
|
|
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
|
800f4f6: 693b ldr r3, [r7, #16]
|
|
800f4f8: 2b00 cmp r3, #0
|
|
800f4fa: d121 bne.n 800f540 <xTaskIncrementTick+0x6c>
|
|
{
|
|
taskSWITCH_DELAYED_LISTS();
|
|
800f4fc: 4b49 ldr r3, [pc, #292] ; (800f624 <xTaskIncrementTick+0x150>)
|
|
800f4fe: 681b ldr r3, [r3, #0]
|
|
800f500: 681b ldr r3, [r3, #0]
|
|
800f502: 2b00 cmp r3, #0
|
|
800f504: d00b beq.n 800f51e <xTaskIncrementTick+0x4a>
|
|
800f506: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f50a: b672 cpsid i
|
|
800f50c: f383 8811 msr BASEPRI, r3
|
|
800f510: f3bf 8f6f isb sy
|
|
800f514: f3bf 8f4f dsb sy
|
|
800f518: b662 cpsie i
|
|
800f51a: 603b str r3, [r7, #0]
|
|
800f51c: e7fe b.n 800f51c <xTaskIncrementTick+0x48>
|
|
800f51e: 4b41 ldr r3, [pc, #260] ; (800f624 <xTaskIncrementTick+0x150>)
|
|
800f520: 681b ldr r3, [r3, #0]
|
|
800f522: 60fb str r3, [r7, #12]
|
|
800f524: 4b40 ldr r3, [pc, #256] ; (800f628 <xTaskIncrementTick+0x154>)
|
|
800f526: 681b ldr r3, [r3, #0]
|
|
800f528: 4a3e ldr r2, [pc, #248] ; (800f624 <xTaskIncrementTick+0x150>)
|
|
800f52a: 6013 str r3, [r2, #0]
|
|
800f52c: 4a3e ldr r2, [pc, #248] ; (800f628 <xTaskIncrementTick+0x154>)
|
|
800f52e: 68fb ldr r3, [r7, #12]
|
|
800f530: 6013 str r3, [r2, #0]
|
|
800f532: 4b3e ldr r3, [pc, #248] ; (800f62c <xTaskIncrementTick+0x158>)
|
|
800f534: 681b ldr r3, [r3, #0]
|
|
800f536: 3301 adds r3, #1
|
|
800f538: 4a3c ldr r2, [pc, #240] ; (800f62c <xTaskIncrementTick+0x158>)
|
|
800f53a: 6013 str r3, [r2, #0]
|
|
800f53c: f000 facc bl 800fad8 <prvResetNextTaskUnblockTime>
|
|
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
|
the queue in the order of their wake time - meaning once one task
|
|
has been found whose block time has not expired there is no need to
|
|
look any further down the list. */
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
|
800f540: 4b3b ldr r3, [pc, #236] ; (800f630 <xTaskIncrementTick+0x15c>)
|
|
800f542: 681b ldr r3, [r3, #0]
|
|
800f544: 693a ldr r2, [r7, #16]
|
|
800f546: 429a cmp r2, r3
|
|
800f548: d348 bcc.n 800f5dc <xTaskIncrementTick+0x108>
|
|
{
|
|
for( ;; )
|
|
{
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800f54a: 4b36 ldr r3, [pc, #216] ; (800f624 <xTaskIncrementTick+0x150>)
|
|
800f54c: 681b ldr r3, [r3, #0]
|
|
800f54e: 681b ldr r3, [r3, #0]
|
|
800f550: 2b00 cmp r3, #0
|
|
800f552: d104 bne.n 800f55e <xTaskIncrementTick+0x8a>
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
|
to the maximum possible value so it is extremely
|
|
unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
|
next time through. */
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800f554: 4b36 ldr r3, [pc, #216] ; (800f630 <xTaskIncrementTick+0x15c>)
|
|
800f556: f04f 32ff mov.w r2, #4294967295
|
|
800f55a: 601a str r2, [r3, #0]
|
|
break;
|
|
800f55c: e03e b.n 800f5dc <xTaskIncrementTick+0x108>
|
|
{
|
|
/* The delayed list is not empty, get the value of the
|
|
item at the head of the delayed list. This is the time
|
|
at which the task at the head of the delayed list must
|
|
be removed from the Blocked state. */
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800f55e: 4b31 ldr r3, [pc, #196] ; (800f624 <xTaskIncrementTick+0x150>)
|
|
800f560: 681b ldr r3, [r3, #0]
|
|
800f562: 68db ldr r3, [r3, #12]
|
|
800f564: 68db ldr r3, [r3, #12]
|
|
800f566: 60bb str r3, [r7, #8]
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
|
800f568: 68bb ldr r3, [r7, #8]
|
|
800f56a: 685b ldr r3, [r3, #4]
|
|
800f56c: 607b str r3, [r7, #4]
|
|
|
|
if( xConstTickCount < xItemValue )
|
|
800f56e: 693a ldr r2, [r7, #16]
|
|
800f570: 687b ldr r3, [r7, #4]
|
|
800f572: 429a cmp r2, r3
|
|
800f574: d203 bcs.n 800f57e <xTaskIncrementTick+0xaa>
|
|
/* It is not time to unblock this item yet, but the
|
|
item value is the time at which the task at the head
|
|
of the blocked list must be removed from the Blocked
|
|
state - so record the item value in
|
|
xNextTaskUnblockTime. */
|
|
xNextTaskUnblockTime = xItemValue;
|
|
800f576: 4a2e ldr r2, [pc, #184] ; (800f630 <xTaskIncrementTick+0x15c>)
|
|
800f578: 687b ldr r3, [r7, #4]
|
|
800f57a: 6013 str r3, [r2, #0]
|
|
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
|
|
800f57c: e02e b.n 800f5dc <xTaskIncrementTick+0x108>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* It is time to remove the item from the Blocked state. */
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800f57e: 68bb ldr r3, [r7, #8]
|
|
800f580: 3304 adds r3, #4
|
|
800f582: 4618 mov r0, r3
|
|
800f584: f7fe fb94 bl 800dcb0 <uxListRemove>
|
|
|
|
/* Is the task waiting on an event also? If so remove
|
|
it from the event list. */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
800f588: 68bb ldr r3, [r7, #8]
|
|
800f58a: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
800f58c: 2b00 cmp r3, #0
|
|
800f58e: d004 beq.n 800f59a <xTaskIncrementTick+0xc6>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800f590: 68bb ldr r3, [r7, #8]
|
|
800f592: 3318 adds r3, #24
|
|
800f594: 4618 mov r0, r3
|
|
800f596: f7fe fb8b bl 800dcb0 <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Place the unblocked task into the appropriate ready
|
|
list. */
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800f59a: 68bb ldr r3, [r7, #8]
|
|
800f59c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f59e: 2201 movs r2, #1
|
|
800f5a0: 409a lsls r2, r3
|
|
800f5a2: 4b24 ldr r3, [pc, #144] ; (800f634 <xTaskIncrementTick+0x160>)
|
|
800f5a4: 681b ldr r3, [r3, #0]
|
|
800f5a6: 4313 orrs r3, r2
|
|
800f5a8: 4a22 ldr r2, [pc, #136] ; (800f634 <xTaskIncrementTick+0x160>)
|
|
800f5aa: 6013 str r3, [r2, #0]
|
|
800f5ac: 68bb ldr r3, [r7, #8]
|
|
800f5ae: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f5b0: 4613 mov r3, r2
|
|
800f5b2: 009b lsls r3, r3, #2
|
|
800f5b4: 4413 add r3, r2
|
|
800f5b6: 009b lsls r3, r3, #2
|
|
800f5b8: 4a1f ldr r2, [pc, #124] ; (800f638 <xTaskIncrementTick+0x164>)
|
|
800f5ba: 441a add r2, r3
|
|
800f5bc: 68bb ldr r3, [r7, #8]
|
|
800f5be: 3304 adds r3, #4
|
|
800f5c0: 4619 mov r1, r3
|
|
800f5c2: 4610 mov r0, r2
|
|
800f5c4: f7fe fb17 bl 800dbf6 <vListInsertEnd>
|
|
{
|
|
/* Preemption is on, but a context switch should
|
|
only be performed if the unblocked task has a
|
|
priority that is equal to or higher than the
|
|
currently executing task. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800f5c8: 68bb ldr r3, [r7, #8]
|
|
800f5ca: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f5cc: 4b1b ldr r3, [pc, #108] ; (800f63c <xTaskIncrementTick+0x168>)
|
|
800f5ce: 681b ldr r3, [r3, #0]
|
|
800f5d0: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f5d2: 429a cmp r2, r3
|
|
800f5d4: d3b9 bcc.n 800f54a <xTaskIncrementTick+0x76>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800f5d6: 2301 movs r3, #1
|
|
800f5d8: 617b str r3, [r7, #20]
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800f5da: e7b6 b.n 800f54a <xTaskIncrementTick+0x76>
|
|
/* Tasks of equal priority to the currently running task will share
|
|
processing time (time slice) if preemption is on, and the application
|
|
writer has not explicitly turned time slicing off. */
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
|
{
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
|
800f5dc: 4b17 ldr r3, [pc, #92] ; (800f63c <xTaskIncrementTick+0x168>)
|
|
800f5de: 681b ldr r3, [r3, #0]
|
|
800f5e0: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f5e2: 4915 ldr r1, [pc, #84] ; (800f638 <xTaskIncrementTick+0x164>)
|
|
800f5e4: 4613 mov r3, r2
|
|
800f5e6: 009b lsls r3, r3, #2
|
|
800f5e8: 4413 add r3, r2
|
|
800f5ea: 009b lsls r3, r3, #2
|
|
800f5ec: 440b add r3, r1
|
|
800f5ee: 681b ldr r3, [r3, #0]
|
|
800f5f0: 2b01 cmp r3, #1
|
|
800f5f2: d907 bls.n 800f604 <xTaskIncrementTick+0x130>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800f5f4: 2301 movs r3, #1
|
|
800f5f6: 617b str r3, [r7, #20]
|
|
800f5f8: e004 b.n 800f604 <xTaskIncrementTick+0x130>
|
|
}
|
|
#endif /* configUSE_TICK_HOOK */
|
|
}
|
|
else
|
|
{
|
|
++uxPendedTicks;
|
|
800f5fa: 4b11 ldr r3, [pc, #68] ; (800f640 <xTaskIncrementTick+0x16c>)
|
|
800f5fc: 681b ldr r3, [r3, #0]
|
|
800f5fe: 3301 adds r3, #1
|
|
800f600: 4a0f ldr r2, [pc, #60] ; (800f640 <xTaskIncrementTick+0x16c>)
|
|
800f602: 6013 str r3, [r2, #0]
|
|
#endif
|
|
}
|
|
|
|
#if ( configUSE_PREEMPTION == 1 )
|
|
{
|
|
if( xYieldPending != pdFALSE )
|
|
800f604: 4b0f ldr r3, [pc, #60] ; (800f644 <xTaskIncrementTick+0x170>)
|
|
800f606: 681b ldr r3, [r3, #0]
|
|
800f608: 2b00 cmp r3, #0
|
|
800f60a: d001 beq.n 800f610 <xTaskIncrementTick+0x13c>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800f60c: 2301 movs r3, #1
|
|
800f60e: 617b str r3, [r7, #20]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_PREEMPTION */
|
|
|
|
return xSwitchRequired;
|
|
800f610: 697b ldr r3, [r7, #20]
|
|
}
|
|
800f612: 4618 mov r0, r3
|
|
800f614: 3718 adds r7, #24
|
|
800f616: 46bd mov sp, r7
|
|
800f618: bd80 pop {r7, pc}
|
|
800f61a: bf00 nop
|
|
800f61c: 200006b4 .word 0x200006b4
|
|
800f620: 20000690 .word 0x20000690
|
|
800f624: 20000644 .word 0x20000644
|
|
800f628: 20000648 .word 0x20000648
|
|
800f62c: 200006a4 .word 0x200006a4
|
|
800f630: 200006ac .word 0x200006ac
|
|
800f634: 20000694 .word 0x20000694
|
|
800f638: 20000590 .word 0x20000590
|
|
800f63c: 2000058c .word 0x2000058c
|
|
800f640: 2000069c .word 0x2000069c
|
|
800f644: 200006a0 .word 0x200006a0
|
|
|
|
0800f648 <vTaskSwitchContext>:
|
|
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskSwitchContext( void )
|
|
{
|
|
800f648: b580 push {r7, lr}
|
|
800f64a: b088 sub sp, #32
|
|
800f64c: af00 add r7, sp, #0
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
|
|
800f64e: 4b3a ldr r3, [pc, #232] ; (800f738 <vTaskSwitchContext+0xf0>)
|
|
800f650: 681b ldr r3, [r3, #0]
|
|
800f652: 2b00 cmp r3, #0
|
|
800f654: d003 beq.n 800f65e <vTaskSwitchContext+0x16>
|
|
{
|
|
/* The scheduler is currently suspended - do not allow a context
|
|
switch. */
|
|
xYieldPending = pdTRUE;
|
|
800f656: 4b39 ldr r3, [pc, #228] ; (800f73c <vTaskSwitchContext+0xf4>)
|
|
800f658: 2201 movs r2, #1
|
|
800f65a: 601a str r2, [r3, #0]
|
|
structure specific to this task. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
}
|
|
}
|
|
800f65c: e067 b.n 800f72e <vTaskSwitchContext+0xe6>
|
|
xYieldPending = pdFALSE;
|
|
800f65e: 4b37 ldr r3, [pc, #220] ; (800f73c <vTaskSwitchContext+0xf4>)
|
|
800f660: 2200 movs r2, #0
|
|
800f662: 601a str r2, [r3, #0]
|
|
taskCHECK_FOR_STACK_OVERFLOW();
|
|
800f664: 4b36 ldr r3, [pc, #216] ; (800f740 <vTaskSwitchContext+0xf8>)
|
|
800f666: 681b ldr r3, [r3, #0]
|
|
800f668: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800f66a: 61fb str r3, [r7, #28]
|
|
800f66c: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5
|
|
800f670: 61bb str r3, [r7, #24]
|
|
800f672: 69fb ldr r3, [r7, #28]
|
|
800f674: 681b ldr r3, [r3, #0]
|
|
800f676: 69ba ldr r2, [r7, #24]
|
|
800f678: 429a cmp r2, r3
|
|
800f67a: d111 bne.n 800f6a0 <vTaskSwitchContext+0x58>
|
|
800f67c: 69fb ldr r3, [r7, #28]
|
|
800f67e: 3304 adds r3, #4
|
|
800f680: 681b ldr r3, [r3, #0]
|
|
800f682: 69ba ldr r2, [r7, #24]
|
|
800f684: 429a cmp r2, r3
|
|
800f686: d10b bne.n 800f6a0 <vTaskSwitchContext+0x58>
|
|
800f688: 69fb ldr r3, [r7, #28]
|
|
800f68a: 3308 adds r3, #8
|
|
800f68c: 681b ldr r3, [r3, #0]
|
|
800f68e: 69ba ldr r2, [r7, #24]
|
|
800f690: 429a cmp r2, r3
|
|
800f692: d105 bne.n 800f6a0 <vTaskSwitchContext+0x58>
|
|
800f694: 69fb ldr r3, [r7, #28]
|
|
800f696: 330c adds r3, #12
|
|
800f698: 681b ldr r3, [r3, #0]
|
|
800f69a: 69ba ldr r2, [r7, #24]
|
|
800f69c: 429a cmp r2, r3
|
|
800f69e: d008 beq.n 800f6b2 <vTaskSwitchContext+0x6a>
|
|
800f6a0: 4b27 ldr r3, [pc, #156] ; (800f740 <vTaskSwitchContext+0xf8>)
|
|
800f6a2: 681a ldr r2, [r3, #0]
|
|
800f6a4: 4b26 ldr r3, [pc, #152] ; (800f740 <vTaskSwitchContext+0xf8>)
|
|
800f6a6: 681b ldr r3, [r3, #0]
|
|
800f6a8: 3334 adds r3, #52 ; 0x34
|
|
800f6aa: 4619 mov r1, r3
|
|
800f6ac: 4610 mov r0, r2
|
|
800f6ae: f7f0 ff86 bl 80005be <vApplicationStackOverflowHook>
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800f6b2: 4b24 ldr r3, [pc, #144] ; (800f744 <vTaskSwitchContext+0xfc>)
|
|
800f6b4: 681b ldr r3, [r3, #0]
|
|
800f6b6: 60fb str r3, [r7, #12]
|
|
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
|
800f6b8: 68fb ldr r3, [r7, #12]
|
|
800f6ba: fab3 f383 clz r3, r3
|
|
800f6be: 72fb strb r3, [r7, #11]
|
|
return ucReturn;
|
|
800f6c0: 7afb ldrb r3, [r7, #11]
|
|
800f6c2: f1c3 031f rsb r3, r3, #31
|
|
800f6c6: 617b str r3, [r7, #20]
|
|
800f6c8: 491f ldr r1, [pc, #124] ; (800f748 <vTaskSwitchContext+0x100>)
|
|
800f6ca: 697a ldr r2, [r7, #20]
|
|
800f6cc: 4613 mov r3, r2
|
|
800f6ce: 009b lsls r3, r3, #2
|
|
800f6d0: 4413 add r3, r2
|
|
800f6d2: 009b lsls r3, r3, #2
|
|
800f6d4: 440b add r3, r1
|
|
800f6d6: 681b ldr r3, [r3, #0]
|
|
800f6d8: 2b00 cmp r3, #0
|
|
800f6da: d10b bne.n 800f6f4 <vTaskSwitchContext+0xac>
|
|
__asm volatile
|
|
800f6dc: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f6e0: b672 cpsid i
|
|
800f6e2: f383 8811 msr BASEPRI, r3
|
|
800f6e6: f3bf 8f6f isb sy
|
|
800f6ea: f3bf 8f4f dsb sy
|
|
800f6ee: b662 cpsie i
|
|
800f6f0: 607b str r3, [r7, #4]
|
|
800f6f2: e7fe b.n 800f6f2 <vTaskSwitchContext+0xaa>
|
|
800f6f4: 697a ldr r2, [r7, #20]
|
|
800f6f6: 4613 mov r3, r2
|
|
800f6f8: 009b lsls r3, r3, #2
|
|
800f6fa: 4413 add r3, r2
|
|
800f6fc: 009b lsls r3, r3, #2
|
|
800f6fe: 4a12 ldr r2, [pc, #72] ; (800f748 <vTaskSwitchContext+0x100>)
|
|
800f700: 4413 add r3, r2
|
|
800f702: 613b str r3, [r7, #16]
|
|
800f704: 693b ldr r3, [r7, #16]
|
|
800f706: 685b ldr r3, [r3, #4]
|
|
800f708: 685a ldr r2, [r3, #4]
|
|
800f70a: 693b ldr r3, [r7, #16]
|
|
800f70c: 605a str r2, [r3, #4]
|
|
800f70e: 693b ldr r3, [r7, #16]
|
|
800f710: 685a ldr r2, [r3, #4]
|
|
800f712: 693b ldr r3, [r7, #16]
|
|
800f714: 3308 adds r3, #8
|
|
800f716: 429a cmp r2, r3
|
|
800f718: d104 bne.n 800f724 <vTaskSwitchContext+0xdc>
|
|
800f71a: 693b ldr r3, [r7, #16]
|
|
800f71c: 685b ldr r3, [r3, #4]
|
|
800f71e: 685a ldr r2, [r3, #4]
|
|
800f720: 693b ldr r3, [r7, #16]
|
|
800f722: 605a str r2, [r3, #4]
|
|
800f724: 693b ldr r3, [r7, #16]
|
|
800f726: 685b ldr r3, [r3, #4]
|
|
800f728: 68db ldr r3, [r3, #12]
|
|
800f72a: 4a05 ldr r2, [pc, #20] ; (800f740 <vTaskSwitchContext+0xf8>)
|
|
800f72c: 6013 str r3, [r2, #0]
|
|
}
|
|
800f72e: bf00 nop
|
|
800f730: 3720 adds r7, #32
|
|
800f732: 46bd mov sp, r7
|
|
800f734: bd80 pop {r7, pc}
|
|
800f736: bf00 nop
|
|
800f738: 200006b4 .word 0x200006b4
|
|
800f73c: 200006a0 .word 0x200006a0
|
|
800f740: 2000058c .word 0x2000058c
|
|
800f744: 20000694 .word 0x20000694
|
|
800f748: 20000590 .word 0x20000590
|
|
|
|
0800f74c <vTaskPlaceOnEventList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
|
|
{
|
|
800f74c: b580 push {r7, lr}
|
|
800f74e: b084 sub sp, #16
|
|
800f750: af00 add r7, sp, #0
|
|
800f752: 6078 str r0, [r7, #4]
|
|
800f754: 6039 str r1, [r7, #0]
|
|
configASSERT( pxEventList );
|
|
800f756: 687b ldr r3, [r7, #4]
|
|
800f758: 2b00 cmp r3, #0
|
|
800f75a: d10b bne.n 800f774 <vTaskPlaceOnEventList+0x28>
|
|
800f75c: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f760: b672 cpsid i
|
|
800f762: f383 8811 msr BASEPRI, r3
|
|
800f766: f3bf 8f6f isb sy
|
|
800f76a: f3bf 8f4f dsb sy
|
|
800f76e: b662 cpsie i
|
|
800f770: 60fb str r3, [r7, #12]
|
|
800f772: e7fe b.n 800f772 <vTaskPlaceOnEventList+0x26>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
This is placed in the list in priority order so the highest priority task
|
|
is the first to be woken by the event. The queue that contains the event
|
|
list is locked, preventing simultaneous access from interrupts. */
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
800f774: 4b07 ldr r3, [pc, #28] ; (800f794 <vTaskPlaceOnEventList+0x48>)
|
|
800f776: 681b ldr r3, [r3, #0]
|
|
800f778: 3318 adds r3, #24
|
|
800f77a: 4619 mov r1, r3
|
|
800f77c: 6878 ldr r0, [r7, #4]
|
|
800f77e: f7fe fa5e bl 800dc3e <vListInsert>
|
|
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
800f782: 2101 movs r1, #1
|
|
800f784: 6838 ldr r0, [r7, #0]
|
|
800f786: f000 fb9d bl 800fec4 <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
800f78a: bf00 nop
|
|
800f78c: 3710 adds r7, #16
|
|
800f78e: 46bd mov sp, r7
|
|
800f790: bd80 pop {r7, pc}
|
|
800f792: bf00 nop
|
|
800f794: 2000058c .word 0x2000058c
|
|
|
|
0800f798 <xTaskRemoveFromEventList>:
|
|
|
|
#endif /* configUSE_TIMERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
|
{
|
|
800f798: b580 push {r7, lr}
|
|
800f79a: b086 sub sp, #24
|
|
800f79c: af00 add r7, sp, #0
|
|
800f79e: 6078 str r0, [r7, #4]
|
|
get called - the lock count on the queue will get modified instead. This
|
|
means exclusive access to the event list is guaranteed here.
|
|
|
|
This function assumes that a check has already been made to ensure that
|
|
pxEventList is not empty. */
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800f7a0: 687b ldr r3, [r7, #4]
|
|
800f7a2: 68db ldr r3, [r3, #12]
|
|
800f7a4: 68db ldr r3, [r3, #12]
|
|
800f7a6: 613b str r3, [r7, #16]
|
|
configASSERT( pxUnblockedTCB );
|
|
800f7a8: 693b ldr r3, [r7, #16]
|
|
800f7aa: 2b00 cmp r3, #0
|
|
800f7ac: d10b bne.n 800f7c6 <xTaskRemoveFromEventList+0x2e>
|
|
800f7ae: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f7b2: b672 cpsid i
|
|
800f7b4: f383 8811 msr BASEPRI, r3
|
|
800f7b8: f3bf 8f6f isb sy
|
|
800f7bc: f3bf 8f4f dsb sy
|
|
800f7c0: b662 cpsie i
|
|
800f7c2: 60fb str r3, [r7, #12]
|
|
800f7c4: e7fe b.n 800f7c4 <xTaskRemoveFromEventList+0x2c>
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
|
|
800f7c6: 693b ldr r3, [r7, #16]
|
|
800f7c8: 3318 adds r3, #24
|
|
800f7ca: 4618 mov r0, r3
|
|
800f7cc: f7fe fa70 bl 800dcb0 <uxListRemove>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800f7d0: 4b1d ldr r3, [pc, #116] ; (800f848 <xTaskRemoveFromEventList+0xb0>)
|
|
800f7d2: 681b ldr r3, [r3, #0]
|
|
800f7d4: 2b00 cmp r3, #0
|
|
800f7d6: d11c bne.n 800f812 <xTaskRemoveFromEventList+0x7a>
|
|
{
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
|
|
800f7d8: 693b ldr r3, [r7, #16]
|
|
800f7da: 3304 adds r3, #4
|
|
800f7dc: 4618 mov r0, r3
|
|
800f7de: f7fe fa67 bl 800dcb0 <uxListRemove>
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
|
800f7e2: 693b ldr r3, [r7, #16]
|
|
800f7e4: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f7e6: 2201 movs r2, #1
|
|
800f7e8: 409a lsls r2, r3
|
|
800f7ea: 4b18 ldr r3, [pc, #96] ; (800f84c <xTaskRemoveFromEventList+0xb4>)
|
|
800f7ec: 681b ldr r3, [r3, #0]
|
|
800f7ee: 4313 orrs r3, r2
|
|
800f7f0: 4a16 ldr r2, [pc, #88] ; (800f84c <xTaskRemoveFromEventList+0xb4>)
|
|
800f7f2: 6013 str r3, [r2, #0]
|
|
800f7f4: 693b ldr r3, [r7, #16]
|
|
800f7f6: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f7f8: 4613 mov r3, r2
|
|
800f7fa: 009b lsls r3, r3, #2
|
|
800f7fc: 4413 add r3, r2
|
|
800f7fe: 009b lsls r3, r3, #2
|
|
800f800: 4a13 ldr r2, [pc, #76] ; (800f850 <xTaskRemoveFromEventList+0xb8>)
|
|
800f802: 441a add r2, r3
|
|
800f804: 693b ldr r3, [r7, #16]
|
|
800f806: 3304 adds r3, #4
|
|
800f808: 4619 mov r1, r3
|
|
800f80a: 4610 mov r0, r2
|
|
800f80c: f7fe f9f3 bl 800dbf6 <vListInsertEnd>
|
|
800f810: e005 b.n 800f81e <xTaskRemoveFromEventList+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
|
pending until the scheduler is resumed. */
|
|
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
|
800f812: 693b ldr r3, [r7, #16]
|
|
800f814: 3318 adds r3, #24
|
|
800f816: 4619 mov r1, r3
|
|
800f818: 480e ldr r0, [pc, #56] ; (800f854 <xTaskRemoveFromEventList+0xbc>)
|
|
800f81a: f7fe f9ec bl 800dbf6 <vListInsertEnd>
|
|
}
|
|
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
800f81e: 693b ldr r3, [r7, #16]
|
|
800f820: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800f822: 4b0d ldr r3, [pc, #52] ; (800f858 <xTaskRemoveFromEventList+0xc0>)
|
|
800f824: 681b ldr r3, [r3, #0]
|
|
800f826: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800f828: 429a cmp r2, r3
|
|
800f82a: d905 bls.n 800f838 <xTaskRemoveFromEventList+0xa0>
|
|
{
|
|
/* Return true if the task removed from the event list has a higher
|
|
priority than the calling task. This allows the calling task to know if
|
|
it should force a context switch now. */
|
|
xReturn = pdTRUE;
|
|
800f82c: 2301 movs r3, #1
|
|
800f82e: 617b str r3, [r7, #20]
|
|
|
|
/* Mark that a yield is pending in case the user is not using the
|
|
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
800f830: 4b0a ldr r3, [pc, #40] ; (800f85c <xTaskRemoveFromEventList+0xc4>)
|
|
800f832: 2201 movs r2, #1
|
|
800f834: 601a str r2, [r3, #0]
|
|
800f836: e001 b.n 800f83c <xTaskRemoveFromEventList+0xa4>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800f838: 2300 movs r3, #0
|
|
800f83a: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800f83c: 697b ldr r3, [r7, #20]
|
|
}
|
|
800f83e: 4618 mov r0, r3
|
|
800f840: 3718 adds r7, #24
|
|
800f842: 46bd mov sp, r7
|
|
800f844: bd80 pop {r7, pc}
|
|
800f846: bf00 nop
|
|
800f848: 200006b4 .word 0x200006b4
|
|
800f84c: 20000694 .word 0x20000694
|
|
800f850: 20000590 .word 0x20000590
|
|
800f854: 2000064c .word 0x2000064c
|
|
800f858: 2000058c .word 0x2000058c
|
|
800f85c: 200006a0 .word 0x200006a0
|
|
|
|
0800f860 <vTaskInternalSetTimeOutState>:
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
|
{
|
|
800f860: b480 push {r7}
|
|
800f862: b083 sub sp, #12
|
|
800f864: af00 add r7, sp, #0
|
|
800f866: 6078 str r0, [r7, #4]
|
|
/* For internal use only as it does not use a critical section. */
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
|
800f868: 4b06 ldr r3, [pc, #24] ; (800f884 <vTaskInternalSetTimeOutState+0x24>)
|
|
800f86a: 681a ldr r2, [r3, #0]
|
|
800f86c: 687b ldr r3, [r7, #4]
|
|
800f86e: 601a str r2, [r3, #0]
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
|
800f870: 4b05 ldr r3, [pc, #20] ; (800f888 <vTaskInternalSetTimeOutState+0x28>)
|
|
800f872: 681a ldr r2, [r3, #0]
|
|
800f874: 687b ldr r3, [r7, #4]
|
|
800f876: 605a str r2, [r3, #4]
|
|
}
|
|
800f878: bf00 nop
|
|
800f87a: 370c adds r7, #12
|
|
800f87c: 46bd mov sp, r7
|
|
800f87e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f882: 4770 bx lr
|
|
800f884: 200006a4 .word 0x200006a4
|
|
800f888: 20000690 .word 0x20000690
|
|
|
|
0800f88c <xTaskCheckForTimeOut>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
|
|
{
|
|
800f88c: b580 push {r7, lr}
|
|
800f88e: b088 sub sp, #32
|
|
800f890: af00 add r7, sp, #0
|
|
800f892: 6078 str r0, [r7, #4]
|
|
800f894: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( pxTimeOut );
|
|
800f896: 687b ldr r3, [r7, #4]
|
|
800f898: 2b00 cmp r3, #0
|
|
800f89a: d10b bne.n 800f8b4 <xTaskCheckForTimeOut+0x28>
|
|
800f89c: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f8a0: b672 cpsid i
|
|
800f8a2: f383 8811 msr BASEPRI, r3
|
|
800f8a6: f3bf 8f6f isb sy
|
|
800f8aa: f3bf 8f4f dsb sy
|
|
800f8ae: b662 cpsie i
|
|
800f8b0: 613b str r3, [r7, #16]
|
|
800f8b2: e7fe b.n 800f8b2 <xTaskCheckForTimeOut+0x26>
|
|
configASSERT( pxTicksToWait );
|
|
800f8b4: 683b ldr r3, [r7, #0]
|
|
800f8b6: 2b00 cmp r3, #0
|
|
800f8b8: d10b bne.n 800f8d2 <xTaskCheckForTimeOut+0x46>
|
|
800f8ba: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800f8be: b672 cpsid i
|
|
800f8c0: f383 8811 msr BASEPRI, r3
|
|
800f8c4: f3bf 8f6f isb sy
|
|
800f8c8: f3bf 8f4f dsb sy
|
|
800f8cc: b662 cpsie i
|
|
800f8ce: 60fb str r3, [r7, #12]
|
|
800f8d0: e7fe b.n 800f8d0 <xTaskCheckForTimeOut+0x44>
|
|
|
|
taskENTER_CRITICAL();
|
|
800f8d2: f000 fc69 bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800f8d6: 4b1d ldr r3, [pc, #116] ; (800f94c <xTaskCheckForTimeOut+0xc0>)
|
|
800f8d8: 681b ldr r3, [r3, #0]
|
|
800f8da: 61bb str r3, [r7, #24]
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
|
800f8dc: 687b ldr r3, [r7, #4]
|
|
800f8de: 685b ldr r3, [r3, #4]
|
|
800f8e0: 69ba ldr r2, [r7, #24]
|
|
800f8e2: 1ad3 subs r3, r2, r3
|
|
800f8e4: 617b str r3, [r7, #20]
|
|
}
|
|
else
|
|
#endif
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
|
800f8e6: 683b ldr r3, [r7, #0]
|
|
800f8e8: 681b ldr r3, [r3, #0]
|
|
800f8ea: f1b3 3fff cmp.w r3, #4294967295
|
|
800f8ee: d102 bne.n 800f8f6 <xTaskCheckForTimeOut+0x6a>
|
|
{
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
|
specified is the maximum block time then the task should block
|
|
indefinitely, and therefore never time out. */
|
|
xReturn = pdFALSE;
|
|
800f8f0: 2300 movs r3, #0
|
|
800f8f2: 61fb str r3, [r7, #28]
|
|
800f8f4: e023 b.n 800f93e <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
#endif
|
|
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
|
800f8f6: 687b ldr r3, [r7, #4]
|
|
800f8f8: 681a ldr r2, [r3, #0]
|
|
800f8fa: 4b15 ldr r3, [pc, #84] ; (800f950 <xTaskCheckForTimeOut+0xc4>)
|
|
800f8fc: 681b ldr r3, [r3, #0]
|
|
800f8fe: 429a cmp r2, r3
|
|
800f900: d007 beq.n 800f912 <xTaskCheckForTimeOut+0x86>
|
|
800f902: 687b ldr r3, [r7, #4]
|
|
800f904: 685b ldr r3, [r3, #4]
|
|
800f906: 69ba ldr r2, [r7, #24]
|
|
800f908: 429a cmp r2, r3
|
|
800f90a: d302 bcc.n 800f912 <xTaskCheckForTimeOut+0x86>
|
|
/* The tick count is greater than the time at which
|
|
vTaskSetTimeout() was called, but has also overflowed since
|
|
vTaskSetTimeOut() was called. It must have wrapped all the way
|
|
around and gone past again. This passed since vTaskSetTimeout()
|
|
was called. */
|
|
xReturn = pdTRUE;
|
|
800f90c: 2301 movs r3, #1
|
|
800f90e: 61fb str r3, [r7, #28]
|
|
800f910: e015 b.n 800f93e <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
|
800f912: 683b ldr r3, [r7, #0]
|
|
800f914: 681b ldr r3, [r3, #0]
|
|
800f916: 697a ldr r2, [r7, #20]
|
|
800f918: 429a cmp r2, r3
|
|
800f91a: d20b bcs.n 800f934 <xTaskCheckForTimeOut+0xa8>
|
|
{
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
|
*pxTicksToWait -= xElapsedTime;
|
|
800f91c: 683b ldr r3, [r7, #0]
|
|
800f91e: 681a ldr r2, [r3, #0]
|
|
800f920: 697b ldr r3, [r7, #20]
|
|
800f922: 1ad2 subs r2, r2, r3
|
|
800f924: 683b ldr r3, [r7, #0]
|
|
800f926: 601a str r2, [r3, #0]
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
|
800f928: 6878 ldr r0, [r7, #4]
|
|
800f92a: f7ff ff99 bl 800f860 <vTaskInternalSetTimeOutState>
|
|
xReturn = pdFALSE;
|
|
800f92e: 2300 movs r3, #0
|
|
800f930: 61fb str r3, [r7, #28]
|
|
800f932: e004 b.n 800f93e <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
{
|
|
*pxTicksToWait = 0;
|
|
800f934: 683b ldr r3, [r7, #0]
|
|
800f936: 2200 movs r2, #0
|
|
800f938: 601a str r2, [r3, #0]
|
|
xReturn = pdTRUE;
|
|
800f93a: 2301 movs r3, #1
|
|
800f93c: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800f93e: f000 fc65 bl 801020c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800f942: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800f944: 4618 mov r0, r3
|
|
800f946: 3720 adds r7, #32
|
|
800f948: 46bd mov sp, r7
|
|
800f94a: bd80 pop {r7, pc}
|
|
800f94c: 20000690 .word 0x20000690
|
|
800f950: 200006a4 .word 0x200006a4
|
|
|
|
0800f954 <vTaskMissedYield>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskMissedYield( void )
|
|
{
|
|
800f954: b480 push {r7}
|
|
800f956: af00 add r7, sp, #0
|
|
xYieldPending = pdTRUE;
|
|
800f958: 4b03 ldr r3, [pc, #12] ; (800f968 <vTaskMissedYield+0x14>)
|
|
800f95a: 2201 movs r2, #1
|
|
800f95c: 601a str r2, [r3, #0]
|
|
}
|
|
800f95e: bf00 nop
|
|
800f960: 46bd mov sp, r7
|
|
800f962: f85d 7b04 ldr.w r7, [sp], #4
|
|
800f966: 4770 bx lr
|
|
800f968: 200006a0 .word 0x200006a0
|
|
|
|
0800f96c <prvIdleTask>:
|
|
*
|
|
* void prvIdleTask( void *pvParameters );
|
|
*
|
|
*/
|
|
static portTASK_FUNCTION( prvIdleTask, pvParameters )
|
|
{
|
|
800f96c: b580 push {r7, lr}
|
|
800f96e: b082 sub sp, #8
|
|
800f970: af00 add r7, sp, #0
|
|
800f972: 6078 str r0, [r7, #4]
|
|
|
|
for( ;; )
|
|
{
|
|
/* See if any tasks have deleted themselves - if so then the idle task
|
|
is responsible for freeing the deleted task's TCB and stack. */
|
|
prvCheckTasksWaitingTermination();
|
|
800f974: f000 f854 bl 800fa20 <prvCheckTasksWaitingTermination>
|
|
|
|
A critical region is not required here as we are just reading from
|
|
the list, and an occasional incorrect value will not matter. If
|
|
the ready list at the idle priority contains more than one task
|
|
then a task other than the idle task is ready to execute. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
|
|
800f978: 4b07 ldr r3, [pc, #28] ; (800f998 <prvIdleTask+0x2c>)
|
|
800f97a: 681b ldr r3, [r3, #0]
|
|
800f97c: 2b01 cmp r3, #1
|
|
800f97e: d907 bls.n 800f990 <prvIdleTask+0x24>
|
|
{
|
|
taskYIELD();
|
|
800f980: 4b06 ldr r3, [pc, #24] ; (800f99c <prvIdleTask+0x30>)
|
|
800f982: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
800f986: 601a str r2, [r3, #0]
|
|
800f988: f3bf 8f4f dsb sy
|
|
800f98c: f3bf 8f6f isb sy
|
|
/* Call the user defined function from within the idle task. This
|
|
allows the application designer to add background functionality
|
|
without the overhead of a separate task.
|
|
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
|
|
CALL A FUNCTION THAT MIGHT BLOCK. */
|
|
vApplicationIdleHook();
|
|
800f990: f7f0 fe0e bl 80005b0 <vApplicationIdleHook>
|
|
prvCheckTasksWaitingTermination();
|
|
800f994: e7ee b.n 800f974 <prvIdleTask+0x8>
|
|
800f996: bf00 nop
|
|
800f998: 20000590 .word 0x20000590
|
|
800f99c: e000ed04 .word 0xe000ed04
|
|
|
|
0800f9a0 <prvInitialiseTaskLists>:
|
|
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseTaskLists( void )
|
|
{
|
|
800f9a0: b580 push {r7, lr}
|
|
800f9a2: b082 sub sp, #8
|
|
800f9a4: af00 add r7, sp, #0
|
|
UBaseType_t uxPriority;
|
|
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800f9a6: 2300 movs r3, #0
|
|
800f9a8: 607b str r3, [r7, #4]
|
|
800f9aa: e00c b.n 800f9c6 <prvInitialiseTaskLists+0x26>
|
|
{
|
|
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
|
|
800f9ac: 687a ldr r2, [r7, #4]
|
|
800f9ae: 4613 mov r3, r2
|
|
800f9b0: 009b lsls r3, r3, #2
|
|
800f9b2: 4413 add r3, r2
|
|
800f9b4: 009b lsls r3, r3, #2
|
|
800f9b6: 4a12 ldr r2, [pc, #72] ; (800fa00 <prvInitialiseTaskLists+0x60>)
|
|
800f9b8: 4413 add r3, r2
|
|
800f9ba: 4618 mov r0, r3
|
|
800f9bc: f7fe f8ee bl 800db9c <vListInitialise>
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800f9c0: 687b ldr r3, [r7, #4]
|
|
800f9c2: 3301 adds r3, #1
|
|
800f9c4: 607b str r3, [r7, #4]
|
|
800f9c6: 687b ldr r3, [r7, #4]
|
|
800f9c8: 2b06 cmp r3, #6
|
|
800f9ca: d9ef bls.n 800f9ac <prvInitialiseTaskLists+0xc>
|
|
}
|
|
|
|
vListInitialise( &xDelayedTaskList1 );
|
|
800f9cc: 480d ldr r0, [pc, #52] ; (800fa04 <prvInitialiseTaskLists+0x64>)
|
|
800f9ce: f7fe f8e5 bl 800db9c <vListInitialise>
|
|
vListInitialise( &xDelayedTaskList2 );
|
|
800f9d2: 480d ldr r0, [pc, #52] ; (800fa08 <prvInitialiseTaskLists+0x68>)
|
|
800f9d4: f7fe f8e2 bl 800db9c <vListInitialise>
|
|
vListInitialise( &xPendingReadyList );
|
|
800f9d8: 480c ldr r0, [pc, #48] ; (800fa0c <prvInitialiseTaskLists+0x6c>)
|
|
800f9da: f7fe f8df bl 800db9c <vListInitialise>
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
{
|
|
vListInitialise( &xTasksWaitingTermination );
|
|
800f9de: 480c ldr r0, [pc, #48] ; (800fa10 <prvInitialiseTaskLists+0x70>)
|
|
800f9e0: f7fe f8dc bl 800db9c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
vListInitialise( &xSuspendedTaskList );
|
|
800f9e4: 480b ldr r0, [pc, #44] ; (800fa14 <prvInitialiseTaskLists+0x74>)
|
|
800f9e6: f7fe f8d9 bl 800db9c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
|
|
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
|
|
using list2. */
|
|
pxDelayedTaskList = &xDelayedTaskList1;
|
|
800f9ea: 4b0b ldr r3, [pc, #44] ; (800fa18 <prvInitialiseTaskLists+0x78>)
|
|
800f9ec: 4a05 ldr r2, [pc, #20] ; (800fa04 <prvInitialiseTaskLists+0x64>)
|
|
800f9ee: 601a str r2, [r3, #0]
|
|
pxOverflowDelayedTaskList = &xDelayedTaskList2;
|
|
800f9f0: 4b0a ldr r3, [pc, #40] ; (800fa1c <prvInitialiseTaskLists+0x7c>)
|
|
800f9f2: 4a05 ldr r2, [pc, #20] ; (800fa08 <prvInitialiseTaskLists+0x68>)
|
|
800f9f4: 601a str r2, [r3, #0]
|
|
}
|
|
800f9f6: bf00 nop
|
|
800f9f8: 3708 adds r7, #8
|
|
800f9fa: 46bd mov sp, r7
|
|
800f9fc: bd80 pop {r7, pc}
|
|
800f9fe: bf00 nop
|
|
800fa00: 20000590 .word 0x20000590
|
|
800fa04: 2000061c .word 0x2000061c
|
|
800fa08: 20000630 .word 0x20000630
|
|
800fa0c: 2000064c .word 0x2000064c
|
|
800fa10: 20000660 .word 0x20000660
|
|
800fa14: 20000678 .word 0x20000678
|
|
800fa18: 20000644 .word 0x20000644
|
|
800fa1c: 20000648 .word 0x20000648
|
|
|
|
0800fa20 <prvCheckTasksWaitingTermination>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckTasksWaitingTermination( void )
|
|
{
|
|
800fa20: b580 push {r7, lr}
|
|
800fa22: b082 sub sp, #8
|
|
800fa24: af00 add r7, sp, #0
|
|
{
|
|
TCB_t *pxTCB;
|
|
|
|
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
|
|
being called too often in the idle task. */
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800fa26: e019 b.n 800fa5c <prvCheckTasksWaitingTermination+0x3c>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800fa28: f000 fbbe bl 80101a8 <vPortEnterCritical>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800fa2c: 4b0f ldr r3, [pc, #60] ; (800fa6c <prvCheckTasksWaitingTermination+0x4c>)
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|
800fa2e: 68db ldr r3, [r3, #12]
|
|
800fa30: 68db ldr r3, [r3, #12]
|
|
800fa32: 607b str r3, [r7, #4]
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800fa34: 687b ldr r3, [r7, #4]
|
|
800fa36: 3304 adds r3, #4
|
|
800fa38: 4618 mov r0, r3
|
|
800fa3a: f7fe f939 bl 800dcb0 <uxListRemove>
|
|
--uxCurrentNumberOfTasks;
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|
800fa3e: 4b0c ldr r3, [pc, #48] ; (800fa70 <prvCheckTasksWaitingTermination+0x50>)
|
|
800fa40: 681b ldr r3, [r3, #0]
|
|
800fa42: 3b01 subs r3, #1
|
|
800fa44: 4a0a ldr r2, [pc, #40] ; (800fa70 <prvCheckTasksWaitingTermination+0x50>)
|
|
800fa46: 6013 str r3, [r2, #0]
|
|
--uxDeletedTasksWaitingCleanUp;
|
|
800fa48: 4b0a ldr r3, [pc, #40] ; (800fa74 <prvCheckTasksWaitingTermination+0x54>)
|
|
800fa4a: 681b ldr r3, [r3, #0]
|
|
800fa4c: 3b01 subs r3, #1
|
|
800fa4e: 4a09 ldr r2, [pc, #36] ; (800fa74 <prvCheckTasksWaitingTermination+0x54>)
|
|
800fa50: 6013 str r3, [r2, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
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|
800fa52: f000 fbdb bl 801020c <vPortExitCritical>
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|
|
|
prvDeleteTCB( pxTCB );
|
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800fa56: 6878 ldr r0, [r7, #4]
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|
800fa58: f000 f80e bl 800fa78 <prvDeleteTCB>
|
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while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800fa5c: 4b05 ldr r3, [pc, #20] ; (800fa74 <prvCheckTasksWaitingTermination+0x54>)
|
|
800fa5e: 681b ldr r3, [r3, #0]
|
|
800fa60: 2b00 cmp r3, #0
|
|
800fa62: d1e1 bne.n 800fa28 <prvCheckTasksWaitingTermination+0x8>
|
|
}
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
}
|
|
800fa64: bf00 nop
|
|
800fa66: 3708 adds r7, #8
|
|
800fa68: 46bd mov sp, r7
|
|
800fa6a: bd80 pop {r7, pc}
|
|
800fa6c: 20000660 .word 0x20000660
|
|
800fa70: 2000068c .word 0x2000068c
|
|
800fa74: 20000674 .word 0x20000674
|
|
|
|
0800fa78 <prvDeleteTCB>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
|
|
static void prvDeleteTCB( TCB_t *pxTCB )
|
|
{
|
|
800fa78: b580 push {r7, lr}
|
|
800fa7a: b084 sub sp, #16
|
|
800fa7c: af00 add r7, sp, #0
|
|
800fa7e: 6078 str r0, [r7, #4]
|
|
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* The task could have been allocated statically or dynamically, so
|
|
check what was statically allocated before trying to free the
|
|
memory. */
|
|
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
|
|
800fa80: 687b ldr r3, [r7, #4]
|
|
800fa82: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
|
|
800fa86: 2b00 cmp r3, #0
|
|
800fa88: d108 bne.n 800fa9c <prvDeleteTCB+0x24>
|
|
{
|
|
/* Both the stack and TCB were allocated dynamically, so both
|
|
must be freed. */
|
|
vPortFree( pxTCB->pxStack );
|
|
800fa8a: 687b ldr r3, [r7, #4]
|
|
800fa8c: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
800fa8e: 4618 mov r0, r3
|
|
800fa90: f000 fd78 bl 8010584 <vPortFree>
|
|
vPortFree( pxTCB );
|
|
800fa94: 6878 ldr r0, [r7, #4]
|
|
800fa96: f000 fd75 bl 8010584 <vPortFree>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
}
|
|
800fa9a: e019 b.n 800fad0 <prvDeleteTCB+0x58>
|
|
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
|
|
800fa9c: 687b ldr r3, [r7, #4]
|
|
800fa9e: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
|
|
800faa2: 2b01 cmp r3, #1
|
|
800faa4: d103 bne.n 800faae <prvDeleteTCB+0x36>
|
|
vPortFree( pxTCB );
|
|
800faa6: 6878 ldr r0, [r7, #4]
|
|
800faa8: f000 fd6c bl 8010584 <vPortFree>
|
|
}
|
|
800faac: e010 b.n 800fad0 <prvDeleteTCB+0x58>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
800faae: 687b ldr r3, [r7, #4]
|
|
800fab0: f893 3055 ldrb.w r3, [r3, #85] ; 0x55
|
|
800fab4: 2b02 cmp r3, #2
|
|
800fab6: d00b beq.n 800fad0 <prvDeleteTCB+0x58>
|
|
800fab8: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800fabc: b672 cpsid i
|
|
800fabe: f383 8811 msr BASEPRI, r3
|
|
800fac2: f3bf 8f6f isb sy
|
|
800fac6: f3bf 8f4f dsb sy
|
|
800faca: b662 cpsie i
|
|
800facc: 60fb str r3, [r7, #12]
|
|
800face: e7fe b.n 800face <prvDeleteTCB+0x56>
|
|
}
|
|
800fad0: bf00 nop
|
|
800fad2: 3710 adds r7, #16
|
|
800fad4: 46bd mov sp, r7
|
|
800fad6: bd80 pop {r7, pc}
|
|
|
|
0800fad8 <prvResetNextTaskUnblockTime>:
|
|
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvResetNextTaskUnblockTime( void )
|
|
{
|
|
800fad8: b480 push {r7}
|
|
800fada: b083 sub sp, #12
|
|
800fadc: af00 add r7, sp, #0
|
|
TCB_t *pxTCB;
|
|
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800fade: 4b0c ldr r3, [pc, #48] ; (800fb10 <prvResetNextTaskUnblockTime+0x38>)
|
|
800fae0: 681b ldr r3, [r3, #0]
|
|
800fae2: 681b ldr r3, [r3, #0]
|
|
800fae4: 2b00 cmp r3, #0
|
|
800fae6: d104 bne.n 800faf2 <prvResetNextTaskUnblockTime+0x1a>
|
|
{
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
|
the maximum possible value so it is extremely unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
|
there is an item in the delayed list. */
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800fae8: 4b0a ldr r3, [pc, #40] ; (800fb14 <prvResetNextTaskUnblockTime+0x3c>)
|
|
800faea: f04f 32ff mov.w r2, #4294967295
|
|
800faee: 601a str r2, [r3, #0]
|
|
which the task at the head of the delayed list should be removed
|
|
from the Blocked state. */
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
}
|
|
}
|
|
800faf0: e008 b.n 800fb04 <prvResetNextTaskUnblockTime+0x2c>
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800faf2: 4b07 ldr r3, [pc, #28] ; (800fb10 <prvResetNextTaskUnblockTime+0x38>)
|
|
800faf4: 681b ldr r3, [r3, #0]
|
|
800faf6: 68db ldr r3, [r3, #12]
|
|
800faf8: 68db ldr r3, [r3, #12]
|
|
800fafa: 607b str r3, [r7, #4]
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
800fafc: 687b ldr r3, [r7, #4]
|
|
800fafe: 685b ldr r3, [r3, #4]
|
|
800fb00: 4a04 ldr r2, [pc, #16] ; (800fb14 <prvResetNextTaskUnblockTime+0x3c>)
|
|
800fb02: 6013 str r3, [r2, #0]
|
|
}
|
|
800fb04: bf00 nop
|
|
800fb06: 370c adds r7, #12
|
|
800fb08: 46bd mov sp, r7
|
|
800fb0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800fb0e: 4770 bx lr
|
|
800fb10: 20000644 .word 0x20000644
|
|
800fb14: 200006ac .word 0x200006ac
|
|
|
|
0800fb18 <xTaskGetSchedulerState>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
|
|
BaseType_t xTaskGetSchedulerState( void )
|
|
{
|
|
800fb18: b480 push {r7}
|
|
800fb1a: b083 sub sp, #12
|
|
800fb1c: af00 add r7, sp, #0
|
|
BaseType_t xReturn;
|
|
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800fb1e: 4b0b ldr r3, [pc, #44] ; (800fb4c <xTaskGetSchedulerState+0x34>)
|
|
800fb20: 681b ldr r3, [r3, #0]
|
|
800fb22: 2b00 cmp r3, #0
|
|
800fb24: d102 bne.n 800fb2c <xTaskGetSchedulerState+0x14>
|
|
{
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
|
800fb26: 2301 movs r3, #1
|
|
800fb28: 607b str r3, [r7, #4]
|
|
800fb2a: e008 b.n 800fb3e <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800fb2c: 4b08 ldr r3, [pc, #32] ; (800fb50 <xTaskGetSchedulerState+0x38>)
|
|
800fb2e: 681b ldr r3, [r3, #0]
|
|
800fb30: 2b00 cmp r3, #0
|
|
800fb32: d102 bne.n 800fb3a <xTaskGetSchedulerState+0x22>
|
|
{
|
|
xReturn = taskSCHEDULER_RUNNING;
|
|
800fb34: 2302 movs r3, #2
|
|
800fb36: 607b str r3, [r7, #4]
|
|
800fb38: e001 b.n 800fb3e <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
|
800fb3a: 2300 movs r3, #0
|
|
800fb3c: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
800fb3e: 687b ldr r3, [r7, #4]
|
|
}
|
|
800fb40: 4618 mov r0, r3
|
|
800fb42: 370c adds r7, #12
|
|
800fb44: 46bd mov sp, r7
|
|
800fb46: f85d 7b04 ldr.w r7, [sp], #4
|
|
800fb4a: 4770 bx lr
|
|
800fb4c: 20000698 .word 0x20000698
|
|
800fb50: 200006b4 .word 0x200006b4
|
|
|
|
0800fb54 <xTaskPriorityInherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
800fb54: b580 push {r7, lr}
|
|
800fb56: b084 sub sp, #16
|
|
800fb58: af00 add r7, sp, #0
|
|
800fb5a: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxMutexHolderTCB = pxMutexHolder;
|
|
800fb5c: 687b ldr r3, [r7, #4]
|
|
800fb5e: 60bb str r3, [r7, #8]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800fb60: 2300 movs r3, #0
|
|
800fb62: 60fb str r3, [r7, #12]
|
|
|
|
/* If the mutex was given back by an interrupt while the queue was
|
|
locked then the mutex holder might now be NULL. _RB_ Is this still
|
|
needed as interrupts can no longer use mutexes? */
|
|
if( pxMutexHolder != NULL )
|
|
800fb64: 687b ldr r3, [r7, #4]
|
|
800fb66: 2b00 cmp r3, #0
|
|
800fb68: d069 beq.n 800fc3e <xTaskPriorityInherit+0xea>
|
|
{
|
|
/* If the holder of the mutex has a priority below the priority of
|
|
the task attempting to obtain the mutex then it will temporarily
|
|
inherit the priority of the task attempting to obtain the mutex. */
|
|
if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
|
|
800fb6a: 68bb ldr r3, [r7, #8]
|
|
800fb6c: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fb6e: 4b36 ldr r3, [pc, #216] ; (800fc48 <xTaskPriorityInherit+0xf4>)
|
|
800fb70: 681b ldr r3, [r3, #0]
|
|
800fb72: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fb74: 429a cmp r2, r3
|
|
800fb76: d259 bcs.n 800fc2c <xTaskPriorityInherit+0xd8>
|
|
{
|
|
/* Adjust the mutex holder state to account for its new
|
|
priority. Only reset the event list item value if the value is
|
|
not being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
800fb78: 68bb ldr r3, [r7, #8]
|
|
800fb7a: 699b ldr r3, [r3, #24]
|
|
800fb7c: 2b00 cmp r3, #0
|
|
800fb7e: db06 blt.n 800fb8e <xTaskPriorityInherit+0x3a>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800fb80: 4b31 ldr r3, [pc, #196] ; (800fc48 <xTaskPriorityInherit+0xf4>)
|
|
800fb82: 681b ldr r3, [r3, #0]
|
|
800fb84: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fb86: f1c3 0207 rsb r2, r3, #7
|
|
800fb8a: 68bb ldr r3, [r7, #8]
|
|
800fb8c: 619a str r2, [r3, #24]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* If the task being modified is in the ready state it will need
|
|
to be moved into a new list. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
|
|
800fb8e: 68bb ldr r3, [r7, #8]
|
|
800fb90: 6959 ldr r1, [r3, #20]
|
|
800fb92: 68bb ldr r3, [r7, #8]
|
|
800fb94: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fb96: 4613 mov r3, r2
|
|
800fb98: 009b lsls r3, r3, #2
|
|
800fb9a: 4413 add r3, r2
|
|
800fb9c: 009b lsls r3, r3, #2
|
|
800fb9e: 4a2b ldr r2, [pc, #172] ; (800fc4c <xTaskPriorityInherit+0xf8>)
|
|
800fba0: 4413 add r3, r2
|
|
800fba2: 4299 cmp r1, r3
|
|
800fba4: d13a bne.n 800fc1c <xTaskPriorityInherit+0xc8>
|
|
{
|
|
if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800fba6: 68bb ldr r3, [r7, #8]
|
|
800fba8: 3304 adds r3, #4
|
|
800fbaa: 4618 mov r0, r3
|
|
800fbac: f7fe f880 bl 800dcb0 <uxListRemove>
|
|
800fbb0: 4603 mov r3, r0
|
|
800fbb2: 2b00 cmp r3, #0
|
|
800fbb4: d115 bne.n 800fbe2 <xTaskPriorityInherit+0x8e>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
|
|
800fbb6: 68bb ldr r3, [r7, #8]
|
|
800fbb8: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fbba: 4924 ldr r1, [pc, #144] ; (800fc4c <xTaskPriorityInherit+0xf8>)
|
|
800fbbc: 4613 mov r3, r2
|
|
800fbbe: 009b lsls r3, r3, #2
|
|
800fbc0: 4413 add r3, r2
|
|
800fbc2: 009b lsls r3, r3, #2
|
|
800fbc4: 440b add r3, r1
|
|
800fbc6: 681b ldr r3, [r3, #0]
|
|
800fbc8: 2b00 cmp r3, #0
|
|
800fbca: d10a bne.n 800fbe2 <xTaskPriorityInherit+0x8e>
|
|
800fbcc: 68bb ldr r3, [r7, #8]
|
|
800fbce: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fbd0: 2201 movs r2, #1
|
|
800fbd2: fa02 f303 lsl.w r3, r2, r3
|
|
800fbd6: 43da mvns r2, r3
|
|
800fbd8: 4b1d ldr r3, [pc, #116] ; (800fc50 <xTaskPriorityInherit+0xfc>)
|
|
800fbda: 681b ldr r3, [r3, #0]
|
|
800fbdc: 4013 ands r3, r2
|
|
800fbde: 4a1c ldr r2, [pc, #112] ; (800fc50 <xTaskPriorityInherit+0xfc>)
|
|
800fbe0: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Inherit the priority before being moved into the new list. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
800fbe2: 4b19 ldr r3, [pc, #100] ; (800fc48 <xTaskPriorityInherit+0xf4>)
|
|
800fbe4: 681b ldr r3, [r3, #0]
|
|
800fbe6: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fbe8: 68bb ldr r3, [r7, #8]
|
|
800fbea: 62da str r2, [r3, #44] ; 0x2c
|
|
prvAddTaskToReadyList( pxMutexHolderTCB );
|
|
800fbec: 68bb ldr r3, [r7, #8]
|
|
800fbee: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fbf0: 2201 movs r2, #1
|
|
800fbf2: 409a lsls r2, r3
|
|
800fbf4: 4b16 ldr r3, [pc, #88] ; (800fc50 <xTaskPriorityInherit+0xfc>)
|
|
800fbf6: 681b ldr r3, [r3, #0]
|
|
800fbf8: 4313 orrs r3, r2
|
|
800fbfa: 4a15 ldr r2, [pc, #84] ; (800fc50 <xTaskPriorityInherit+0xfc>)
|
|
800fbfc: 6013 str r3, [r2, #0]
|
|
800fbfe: 68bb ldr r3, [r7, #8]
|
|
800fc00: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fc02: 4613 mov r3, r2
|
|
800fc04: 009b lsls r3, r3, #2
|
|
800fc06: 4413 add r3, r2
|
|
800fc08: 009b lsls r3, r3, #2
|
|
800fc0a: 4a10 ldr r2, [pc, #64] ; (800fc4c <xTaskPriorityInherit+0xf8>)
|
|
800fc0c: 441a add r2, r3
|
|
800fc0e: 68bb ldr r3, [r7, #8]
|
|
800fc10: 3304 adds r3, #4
|
|
800fc12: 4619 mov r1, r3
|
|
800fc14: 4610 mov r0, r2
|
|
800fc16: f7fd ffee bl 800dbf6 <vListInsertEnd>
|
|
800fc1a: e004 b.n 800fc26 <xTaskPriorityInherit+0xd2>
|
|
}
|
|
else
|
|
{
|
|
/* Just inherit the priority. */
|
|
pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
|
|
800fc1c: 4b0a ldr r3, [pc, #40] ; (800fc48 <xTaskPriorityInherit+0xf4>)
|
|
800fc1e: 681b ldr r3, [r3, #0]
|
|
800fc20: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fc22: 68bb ldr r3, [r7, #8]
|
|
800fc24: 62da str r2, [r3, #44] ; 0x2c
|
|
}
|
|
|
|
traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
|
|
|
|
/* Inheritance occurred. */
|
|
xReturn = pdTRUE;
|
|
800fc26: 2301 movs r3, #1
|
|
800fc28: 60fb str r3, [r7, #12]
|
|
800fc2a: e008 b.n 800fc3e <xTaskPriorityInherit+0xea>
|
|
}
|
|
else
|
|
{
|
|
if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
|
|
800fc2c: 68bb ldr r3, [r7, #8]
|
|
800fc2e: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
800fc30: 4b05 ldr r3, [pc, #20] ; (800fc48 <xTaskPriorityInherit+0xf4>)
|
|
800fc32: 681b ldr r3, [r3, #0]
|
|
800fc34: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fc36: 429a cmp r2, r3
|
|
800fc38: d201 bcs.n 800fc3e <xTaskPriorityInherit+0xea>
|
|
current priority of the mutex holder is not lower than the
|
|
priority of the task attempting to take the mutex.
|
|
Therefore the mutex holder must have already inherited a
|
|
priority, but inheritance would have occurred if that had
|
|
not been the case. */
|
|
xReturn = pdTRUE;
|
|
800fc3a: 2301 movs r3, #1
|
|
800fc3c: 60fb str r3, [r7, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800fc3e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800fc40: 4618 mov r0, r3
|
|
800fc42: 3710 adds r7, #16
|
|
800fc44: 46bd mov sp, r7
|
|
800fc46: bd80 pop {r7, pc}
|
|
800fc48: 2000058c .word 0x2000058c
|
|
800fc4c: 20000590 .word 0x20000590
|
|
800fc50: 20000694 .word 0x20000694
|
|
|
|
0800fc54 <xTaskPriorityDisinherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
800fc54: b580 push {r7, lr}
|
|
800fc56: b086 sub sp, #24
|
|
800fc58: af00 add r7, sp, #0
|
|
800fc5a: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
800fc5c: 687b ldr r3, [r7, #4]
|
|
800fc5e: 613b str r3, [r7, #16]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800fc60: 2300 movs r3, #0
|
|
800fc62: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
800fc64: 687b ldr r3, [r7, #4]
|
|
800fc66: 2b00 cmp r3, #0
|
|
800fc68: d070 beq.n 800fd4c <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
|
If the mutex is held by a task then it cannot be given from an
|
|
interrupt, and if a mutex is given by the holding task then it must
|
|
be the running state task. */
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
|
800fc6a: 4b3b ldr r3, [pc, #236] ; (800fd58 <xTaskPriorityDisinherit+0x104>)
|
|
800fc6c: 681b ldr r3, [r3, #0]
|
|
800fc6e: 693a ldr r2, [r7, #16]
|
|
800fc70: 429a cmp r2, r3
|
|
800fc72: d00b beq.n 800fc8c <xTaskPriorityDisinherit+0x38>
|
|
800fc74: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800fc78: b672 cpsid i
|
|
800fc7a: f383 8811 msr BASEPRI, r3
|
|
800fc7e: f3bf 8f6f isb sy
|
|
800fc82: f3bf 8f4f dsb sy
|
|
800fc86: b662 cpsie i
|
|
800fc88: 60fb str r3, [r7, #12]
|
|
800fc8a: e7fe b.n 800fc8a <xTaskPriorityDisinherit+0x36>
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800fc8c: 693b ldr r3, [r7, #16]
|
|
800fc8e: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800fc90: 2b00 cmp r3, #0
|
|
800fc92: d10b bne.n 800fcac <xTaskPriorityDisinherit+0x58>
|
|
800fc94: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800fc98: b672 cpsid i
|
|
800fc9a: f383 8811 msr BASEPRI, r3
|
|
800fc9e: f3bf 8f6f isb sy
|
|
800fca2: f3bf 8f4f dsb sy
|
|
800fca6: b662 cpsie i
|
|
800fca8: 60bb str r3, [r7, #8]
|
|
800fcaa: e7fe b.n 800fcaa <xTaskPriorityDisinherit+0x56>
|
|
( pxTCB->uxMutexesHeld )--;
|
|
800fcac: 693b ldr r3, [r7, #16]
|
|
800fcae: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800fcb0: 1e5a subs r2, r3, #1
|
|
800fcb2: 693b ldr r3, [r7, #16]
|
|
800fcb4: 649a str r2, [r3, #72] ; 0x48
|
|
|
|
/* Has the holder of the mutex inherited the priority of another
|
|
task? */
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
|
800fcb6: 693b ldr r3, [r7, #16]
|
|
800fcb8: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fcba: 693b ldr r3, [r7, #16]
|
|
800fcbc: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800fcbe: 429a cmp r2, r3
|
|
800fcc0: d044 beq.n 800fd4c <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. */
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
|
800fcc2: 693b ldr r3, [r7, #16]
|
|
800fcc4: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800fcc6: 2b00 cmp r3, #0
|
|
800fcc8: d140 bne.n 800fd4c <xTaskPriorityDisinherit+0xf8>
|
|
/* A task can only have an inherited priority if it holds
|
|
the mutex. If the mutex is held by a task then it cannot be
|
|
given from an interrupt, and if a mutex is given by the
|
|
holding task then it must be the running state task. Remove
|
|
the holding task from the ready list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800fcca: 693b ldr r3, [r7, #16]
|
|
800fccc: 3304 adds r3, #4
|
|
800fcce: 4618 mov r0, r3
|
|
800fcd0: f7fd ffee bl 800dcb0 <uxListRemove>
|
|
800fcd4: 4603 mov r3, r0
|
|
800fcd6: 2b00 cmp r3, #0
|
|
800fcd8: d115 bne.n 800fd06 <xTaskPriorityDisinherit+0xb2>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
|
|
800fcda: 693b ldr r3, [r7, #16]
|
|
800fcdc: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fcde: 491f ldr r1, [pc, #124] ; (800fd5c <xTaskPriorityDisinherit+0x108>)
|
|
800fce0: 4613 mov r3, r2
|
|
800fce2: 009b lsls r3, r3, #2
|
|
800fce4: 4413 add r3, r2
|
|
800fce6: 009b lsls r3, r3, #2
|
|
800fce8: 440b add r3, r1
|
|
800fcea: 681b ldr r3, [r3, #0]
|
|
800fcec: 2b00 cmp r3, #0
|
|
800fcee: d10a bne.n 800fd06 <xTaskPriorityDisinherit+0xb2>
|
|
800fcf0: 693b ldr r3, [r7, #16]
|
|
800fcf2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fcf4: 2201 movs r2, #1
|
|
800fcf6: fa02 f303 lsl.w r3, r2, r3
|
|
800fcfa: 43da mvns r2, r3
|
|
800fcfc: 4b18 ldr r3, [pc, #96] ; (800fd60 <xTaskPriorityDisinherit+0x10c>)
|
|
800fcfe: 681b ldr r3, [r3, #0]
|
|
800fd00: 4013 ands r3, r2
|
|
800fd02: 4a17 ldr r2, [pc, #92] ; (800fd60 <xTaskPriorityDisinherit+0x10c>)
|
|
800fd04: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Disinherit the priority before adding the task into the
|
|
new ready list. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
|
800fd06: 693b ldr r3, [r7, #16]
|
|
800fd08: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
800fd0a: 693b ldr r3, [r7, #16]
|
|
800fd0c: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Reset the event list item value. It cannot be in use for
|
|
any other purpose if this task is running, and it must be
|
|
running to give back the mutex. */
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800fd0e: 693b ldr r3, [r7, #16]
|
|
800fd10: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fd12: f1c3 0207 rsb r2, r3, #7
|
|
800fd16: 693b ldr r3, [r7, #16]
|
|
800fd18: 619a str r2, [r3, #24]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800fd1a: 693b ldr r3, [r7, #16]
|
|
800fd1c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fd1e: 2201 movs r2, #1
|
|
800fd20: 409a lsls r2, r3
|
|
800fd22: 4b0f ldr r3, [pc, #60] ; (800fd60 <xTaskPriorityDisinherit+0x10c>)
|
|
800fd24: 681b ldr r3, [r3, #0]
|
|
800fd26: 4313 orrs r3, r2
|
|
800fd28: 4a0d ldr r2, [pc, #52] ; (800fd60 <xTaskPriorityDisinherit+0x10c>)
|
|
800fd2a: 6013 str r3, [r2, #0]
|
|
800fd2c: 693b ldr r3, [r7, #16]
|
|
800fd2e: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fd30: 4613 mov r3, r2
|
|
800fd32: 009b lsls r3, r3, #2
|
|
800fd34: 4413 add r3, r2
|
|
800fd36: 009b lsls r3, r3, #2
|
|
800fd38: 4a08 ldr r2, [pc, #32] ; (800fd5c <xTaskPriorityDisinherit+0x108>)
|
|
800fd3a: 441a add r2, r3
|
|
800fd3c: 693b ldr r3, [r7, #16]
|
|
800fd3e: 3304 adds r3, #4
|
|
800fd40: 4619 mov r1, r3
|
|
800fd42: 4610 mov r0, r2
|
|
800fd44: f7fd ff57 bl 800dbf6 <vListInsertEnd>
|
|
in an order different to that in which they were taken.
|
|
If a context switch did not occur when the first mutex was
|
|
returned, even if a task was waiting on it, then a context
|
|
switch should occur when the last mutex is returned whether
|
|
a task is waiting on it or not. */
|
|
xReturn = pdTRUE;
|
|
800fd48: 2301 movs r3, #1
|
|
800fd4a: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800fd4c: 697b ldr r3, [r7, #20]
|
|
}
|
|
800fd4e: 4618 mov r0, r3
|
|
800fd50: 3718 adds r7, #24
|
|
800fd52: 46bd mov sp, r7
|
|
800fd54: bd80 pop {r7, pc}
|
|
800fd56: bf00 nop
|
|
800fd58: 2000058c .word 0x2000058c
|
|
800fd5c: 20000590 .word 0x20000590
|
|
800fd60: 20000694 .word 0x20000694
|
|
|
|
0800fd64 <vTaskPriorityDisinheritAfterTimeout>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
|
|
{
|
|
800fd64: b580 push {r7, lr}
|
|
800fd66: b088 sub sp, #32
|
|
800fd68: af00 add r7, sp, #0
|
|
800fd6a: 6078 str r0, [r7, #4]
|
|
800fd6c: 6039 str r1, [r7, #0]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
800fd6e: 687b ldr r3, [r7, #4]
|
|
800fd70: 61bb str r3, [r7, #24]
|
|
UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
|
|
const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
|
|
800fd72: 2301 movs r3, #1
|
|
800fd74: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
800fd76: 687b ldr r3, [r7, #4]
|
|
800fd78: 2b00 cmp r3, #0
|
|
800fd7a: f000 8085 beq.w 800fe88 <vTaskPriorityDisinheritAfterTimeout+0x124>
|
|
{
|
|
/* If pxMutexHolder is not NULL then the holder must hold at least
|
|
one mutex. */
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800fd7e: 69bb ldr r3, [r7, #24]
|
|
800fd80: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800fd82: 2b00 cmp r3, #0
|
|
800fd84: d10b bne.n 800fd9e <vTaskPriorityDisinheritAfterTimeout+0x3a>
|
|
800fd86: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800fd8a: b672 cpsid i
|
|
800fd8c: f383 8811 msr BASEPRI, r3
|
|
800fd90: f3bf 8f6f isb sy
|
|
800fd94: f3bf 8f4f dsb sy
|
|
800fd98: b662 cpsie i
|
|
800fd9a: 60fb str r3, [r7, #12]
|
|
800fd9c: e7fe b.n 800fd9c <vTaskPriorityDisinheritAfterTimeout+0x38>
|
|
|
|
/* Determine the priority to which the priority of the task that
|
|
holds the mutex should be set. This will be the greater of the
|
|
holding task's base priority and the priority of the highest
|
|
priority task that is waiting to obtain the mutex. */
|
|
if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
|
|
800fd9e: 69bb ldr r3, [r7, #24]
|
|
800fda0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800fda2: 683a ldr r2, [r7, #0]
|
|
800fda4: 429a cmp r2, r3
|
|
800fda6: d902 bls.n 800fdae <vTaskPriorityDisinheritAfterTimeout+0x4a>
|
|
{
|
|
uxPriorityToUse = uxHighestPriorityWaitingTask;
|
|
800fda8: 683b ldr r3, [r7, #0]
|
|
800fdaa: 61fb str r3, [r7, #28]
|
|
800fdac: e002 b.n 800fdb4 <vTaskPriorityDisinheritAfterTimeout+0x50>
|
|
}
|
|
else
|
|
{
|
|
uxPriorityToUse = pxTCB->uxBasePriority;
|
|
800fdae: 69bb ldr r3, [r7, #24]
|
|
800fdb0: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
800fdb2: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Does the priority need to change? */
|
|
if( pxTCB->uxPriority != uxPriorityToUse )
|
|
800fdb4: 69bb ldr r3, [r7, #24]
|
|
800fdb6: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fdb8: 69fa ldr r2, [r7, #28]
|
|
800fdba: 429a cmp r2, r3
|
|
800fdbc: d064 beq.n 800fe88 <vTaskPriorityDisinheritAfterTimeout+0x124>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. This is a
|
|
simplification in the priority inheritance implementation. If
|
|
the task that holds the mutex is also holding other mutexes then
|
|
the other mutexes may have caused the priority inheritance. */
|
|
if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
|
|
800fdbe: 69bb ldr r3, [r7, #24]
|
|
800fdc0: 6c9b ldr r3, [r3, #72] ; 0x48
|
|
800fdc2: 697a ldr r2, [r7, #20]
|
|
800fdc4: 429a cmp r2, r3
|
|
800fdc6: d15f bne.n 800fe88 <vTaskPriorityDisinheritAfterTimeout+0x124>
|
|
{
|
|
/* If a task has timed out because it already holds the
|
|
mutex it was trying to obtain then it cannot of inherited
|
|
its own priority. */
|
|
configASSERT( pxTCB != pxCurrentTCB );
|
|
800fdc8: 4b31 ldr r3, [pc, #196] ; (800fe90 <vTaskPriorityDisinheritAfterTimeout+0x12c>)
|
|
800fdca: 681b ldr r3, [r3, #0]
|
|
800fdcc: 69ba ldr r2, [r7, #24]
|
|
800fdce: 429a cmp r2, r3
|
|
800fdd0: d10b bne.n 800fdea <vTaskPriorityDisinheritAfterTimeout+0x86>
|
|
800fdd2: f04f 0350 mov.w r3, #80 ; 0x50
|
|
800fdd6: b672 cpsid i
|
|
800fdd8: f383 8811 msr BASEPRI, r3
|
|
800fddc: f3bf 8f6f isb sy
|
|
800fde0: f3bf 8f4f dsb sy
|
|
800fde4: b662 cpsie i
|
|
800fde6: 60bb str r3, [r7, #8]
|
|
800fde8: e7fe b.n 800fde8 <vTaskPriorityDisinheritAfterTimeout+0x84>
|
|
|
|
/* Disinherit the priority, remembering the previous
|
|
priority to facilitate determining the subject task's
|
|
state. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
uxPriorityUsedOnEntry = pxTCB->uxPriority;
|
|
800fdea: 69bb ldr r3, [r7, #24]
|
|
800fdec: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fdee: 613b str r3, [r7, #16]
|
|
pxTCB->uxPriority = uxPriorityToUse;
|
|
800fdf0: 69bb ldr r3, [r7, #24]
|
|
800fdf2: 69fa ldr r2, [r7, #28]
|
|
800fdf4: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Only reset the event list item value if the value is not
|
|
being used for anything else. */
|
|
if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
|
|
800fdf6: 69bb ldr r3, [r7, #24]
|
|
800fdf8: 699b ldr r3, [r3, #24]
|
|
800fdfa: 2b00 cmp r3, #0
|
|
800fdfc: db04 blt.n 800fe08 <vTaskPriorityDisinheritAfterTimeout+0xa4>
|
|
{
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800fdfe: 69fb ldr r3, [r7, #28]
|
|
800fe00: f1c3 0207 rsb r2, r3, #7
|
|
800fe04: 69bb ldr r3, [r7, #24]
|
|
800fe06: 619a str r2, [r3, #24]
|
|
then the task that holds the mutex could be in either the
|
|
Ready, Blocked or Suspended states. Only remove the task
|
|
from its current state list if it is in the Ready state as
|
|
the task's priority is going to change and there is one
|
|
Ready list per priority. */
|
|
if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
|
|
800fe08: 69bb ldr r3, [r7, #24]
|
|
800fe0a: 6959 ldr r1, [r3, #20]
|
|
800fe0c: 693a ldr r2, [r7, #16]
|
|
800fe0e: 4613 mov r3, r2
|
|
800fe10: 009b lsls r3, r3, #2
|
|
800fe12: 4413 add r3, r2
|
|
800fe14: 009b lsls r3, r3, #2
|
|
800fe16: 4a1f ldr r2, [pc, #124] ; (800fe94 <vTaskPriorityDisinheritAfterTimeout+0x130>)
|
|
800fe18: 4413 add r3, r2
|
|
800fe1a: 4299 cmp r1, r3
|
|
800fe1c: d134 bne.n 800fe88 <vTaskPriorityDisinheritAfterTimeout+0x124>
|
|
{
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800fe1e: 69bb ldr r3, [r7, #24]
|
|
800fe20: 3304 adds r3, #4
|
|
800fe22: 4618 mov r0, r3
|
|
800fe24: f7fd ff44 bl 800dcb0 <uxListRemove>
|
|
800fe28: 4603 mov r3, r0
|
|
800fe2a: 2b00 cmp r3, #0
|
|
800fe2c: d115 bne.n 800fe5a <vTaskPriorityDisinheritAfterTimeout+0xf6>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
|
|
800fe2e: 69bb ldr r3, [r7, #24]
|
|
800fe30: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fe32: 4918 ldr r1, [pc, #96] ; (800fe94 <vTaskPriorityDisinheritAfterTimeout+0x130>)
|
|
800fe34: 4613 mov r3, r2
|
|
800fe36: 009b lsls r3, r3, #2
|
|
800fe38: 4413 add r3, r2
|
|
800fe3a: 009b lsls r3, r3, #2
|
|
800fe3c: 440b add r3, r1
|
|
800fe3e: 681b ldr r3, [r3, #0]
|
|
800fe40: 2b00 cmp r3, #0
|
|
800fe42: d10a bne.n 800fe5a <vTaskPriorityDisinheritAfterTimeout+0xf6>
|
|
800fe44: 69bb ldr r3, [r7, #24]
|
|
800fe46: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fe48: 2201 movs r2, #1
|
|
800fe4a: fa02 f303 lsl.w r3, r2, r3
|
|
800fe4e: 43da mvns r2, r3
|
|
800fe50: 4b11 ldr r3, [pc, #68] ; (800fe98 <vTaskPriorityDisinheritAfterTimeout+0x134>)
|
|
800fe52: 681b ldr r3, [r3, #0]
|
|
800fe54: 4013 ands r3, r2
|
|
800fe56: 4a10 ldr r2, [pc, #64] ; (800fe98 <vTaskPriorityDisinheritAfterTimeout+0x134>)
|
|
800fe58: 6013 str r3, [r2, #0]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800fe5a: 69bb ldr r3, [r7, #24]
|
|
800fe5c: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800fe5e: 2201 movs r2, #1
|
|
800fe60: 409a lsls r2, r3
|
|
800fe62: 4b0d ldr r3, [pc, #52] ; (800fe98 <vTaskPriorityDisinheritAfterTimeout+0x134>)
|
|
800fe64: 681b ldr r3, [r3, #0]
|
|
800fe66: 4313 orrs r3, r2
|
|
800fe68: 4a0b ldr r2, [pc, #44] ; (800fe98 <vTaskPriorityDisinheritAfterTimeout+0x134>)
|
|
800fe6a: 6013 str r3, [r2, #0]
|
|
800fe6c: 69bb ldr r3, [r7, #24]
|
|
800fe6e: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
800fe70: 4613 mov r3, r2
|
|
800fe72: 009b lsls r3, r3, #2
|
|
800fe74: 4413 add r3, r2
|
|
800fe76: 009b lsls r3, r3, #2
|
|
800fe78: 4a06 ldr r2, [pc, #24] ; (800fe94 <vTaskPriorityDisinheritAfterTimeout+0x130>)
|
|
800fe7a: 441a add r2, r3
|
|
800fe7c: 69bb ldr r3, [r7, #24]
|
|
800fe7e: 3304 adds r3, #4
|
|
800fe80: 4619 mov r1, r3
|
|
800fe82: 4610 mov r0, r2
|
|
800fe84: f7fd feb7 bl 800dbf6 <vListInsertEnd>
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800fe88: bf00 nop
|
|
800fe8a: 3720 adds r7, #32
|
|
800fe8c: 46bd mov sp, r7
|
|
800fe8e: bd80 pop {r7, pc}
|
|
800fe90: 2000058c .word 0x2000058c
|
|
800fe94: 20000590 .word 0x20000590
|
|
800fe98: 20000694 .word 0x20000694
|
|
|
|
0800fe9c <pvTaskIncrementMutexHeldCount>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
TaskHandle_t pvTaskIncrementMutexHeldCount( void )
|
|
{
|
|
800fe9c: b480 push {r7}
|
|
800fe9e: af00 add r7, sp, #0
|
|
/* If xSemaphoreCreateMutex() is called before any tasks have been created
|
|
then pxCurrentTCB will be NULL. */
|
|
if( pxCurrentTCB != NULL )
|
|
800fea0: 4b07 ldr r3, [pc, #28] ; (800fec0 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800fea2: 681b ldr r3, [r3, #0]
|
|
800fea4: 2b00 cmp r3, #0
|
|
800fea6: d004 beq.n 800feb2 <pvTaskIncrementMutexHeldCount+0x16>
|
|
{
|
|
( pxCurrentTCB->uxMutexesHeld )++;
|
|
800fea8: 4b05 ldr r3, [pc, #20] ; (800fec0 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800feaa: 681b ldr r3, [r3, #0]
|
|
800feac: 6c9a ldr r2, [r3, #72] ; 0x48
|
|
800feae: 3201 adds r2, #1
|
|
800feb0: 649a str r2, [r3, #72] ; 0x48
|
|
}
|
|
|
|
return pxCurrentTCB;
|
|
800feb2: 4b03 ldr r3, [pc, #12] ; (800fec0 <pvTaskIncrementMutexHeldCount+0x24>)
|
|
800feb4: 681b ldr r3, [r3, #0]
|
|
}
|
|
800feb6: 4618 mov r0, r3
|
|
800feb8: 46bd mov sp, r7
|
|
800feba: f85d 7b04 ldr.w r7, [sp], #4
|
|
800febe: 4770 bx lr
|
|
800fec0: 2000058c .word 0x2000058c
|
|
|
|
0800fec4 <prvAddCurrentTaskToDelayedList>:
|
|
}
|
|
#endif
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
|
|
{
|
|
800fec4: b580 push {r7, lr}
|
|
800fec6: b084 sub sp, #16
|
|
800fec8: af00 add r7, sp, #0
|
|
800feca: 6078 str r0, [r7, #4]
|
|
800fecc: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800fece: 4b29 ldr r3, [pc, #164] ; (800ff74 <prvAddCurrentTaskToDelayedList+0xb0>)
|
|
800fed0: 681b ldr r3, [r3, #0]
|
|
800fed2: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif
|
|
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
|
as the same list item is used for both lists. */
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800fed4: 4b28 ldr r3, [pc, #160] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800fed6: 681b ldr r3, [r3, #0]
|
|
800fed8: 3304 adds r3, #4
|
|
800feda: 4618 mov r0, r3
|
|
800fedc: f7fd fee8 bl 800dcb0 <uxListRemove>
|
|
800fee0: 4603 mov r3, r0
|
|
800fee2: 2b00 cmp r3, #0
|
|
800fee4: d10b bne.n 800fefe <prvAddCurrentTaskToDelayedList+0x3a>
|
|
{
|
|
/* The current task must be in a ready list, so there is no need to
|
|
check, and the port reset macro can be called directly. */
|
|
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
|
|
800fee6: 4b24 ldr r3, [pc, #144] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800fee8: 681b ldr r3, [r3, #0]
|
|
800feea: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
800feec: 2201 movs r2, #1
|
|
800feee: fa02 f303 lsl.w r3, r2, r3
|
|
800fef2: 43da mvns r2, r3
|
|
800fef4: 4b21 ldr r3, [pc, #132] ; (800ff7c <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
800fef6: 681b ldr r3, [r3, #0]
|
|
800fef8: 4013 ands r3, r2
|
|
800fefa: 4a20 ldr r2, [pc, #128] ; (800ff7c <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
800fefc: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
|
800fefe: 687b ldr r3, [r7, #4]
|
|
800ff00: f1b3 3fff cmp.w r3, #4294967295
|
|
800ff04: d10a bne.n 800ff1c <prvAddCurrentTaskToDelayedList+0x58>
|
|
800ff06: 683b ldr r3, [r7, #0]
|
|
800ff08: 2b00 cmp r3, #0
|
|
800ff0a: d007 beq.n 800ff1c <prvAddCurrentTaskToDelayedList+0x58>
|
|
{
|
|
/* Add the task to the suspended task list instead of a delayed task
|
|
list to ensure it is not woken by a timing event. It will block
|
|
indefinitely. */
|
|
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800ff0c: 4b1a ldr r3, [pc, #104] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800ff0e: 681b ldr r3, [r3, #0]
|
|
800ff10: 3304 adds r3, #4
|
|
800ff12: 4619 mov r1, r3
|
|
800ff14: 481a ldr r0, [pc, #104] ; (800ff80 <prvAddCurrentTaskToDelayedList+0xbc>)
|
|
800ff16: f7fd fe6e bl 800dbf6 <vListInsertEnd>
|
|
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
|
( void ) xCanBlockIndefinitely;
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
}
|
|
800ff1a: e026 b.n 800ff6a <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
|
800ff1c: 68fa ldr r2, [r7, #12]
|
|
800ff1e: 687b ldr r3, [r7, #4]
|
|
800ff20: 4413 add r3, r2
|
|
800ff22: 60bb str r3, [r7, #8]
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
|
800ff24: 4b14 ldr r3, [pc, #80] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800ff26: 681b ldr r3, [r3, #0]
|
|
800ff28: 68ba ldr r2, [r7, #8]
|
|
800ff2a: 605a str r2, [r3, #4]
|
|
if( xTimeToWake < xConstTickCount )
|
|
800ff2c: 68ba ldr r2, [r7, #8]
|
|
800ff2e: 68fb ldr r3, [r7, #12]
|
|
800ff30: 429a cmp r2, r3
|
|
800ff32: d209 bcs.n 800ff48 <prvAddCurrentTaskToDelayedList+0x84>
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800ff34: 4b13 ldr r3, [pc, #76] ; (800ff84 <prvAddCurrentTaskToDelayedList+0xc0>)
|
|
800ff36: 681a ldr r2, [r3, #0]
|
|
800ff38: 4b0f ldr r3, [pc, #60] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800ff3a: 681b ldr r3, [r3, #0]
|
|
800ff3c: 3304 adds r3, #4
|
|
800ff3e: 4619 mov r1, r3
|
|
800ff40: 4610 mov r0, r2
|
|
800ff42: f7fd fe7c bl 800dc3e <vListInsert>
|
|
}
|
|
800ff46: e010 b.n 800ff6a <prvAddCurrentTaskToDelayedList+0xa6>
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800ff48: 4b0f ldr r3, [pc, #60] ; (800ff88 <prvAddCurrentTaskToDelayedList+0xc4>)
|
|
800ff4a: 681a ldr r2, [r3, #0]
|
|
800ff4c: 4b0a ldr r3, [pc, #40] ; (800ff78 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800ff4e: 681b ldr r3, [r3, #0]
|
|
800ff50: 3304 adds r3, #4
|
|
800ff52: 4619 mov r1, r3
|
|
800ff54: 4610 mov r0, r2
|
|
800ff56: f7fd fe72 bl 800dc3e <vListInsert>
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
|
800ff5a: 4b0c ldr r3, [pc, #48] ; (800ff8c <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
800ff5c: 681b ldr r3, [r3, #0]
|
|
800ff5e: 68ba ldr r2, [r7, #8]
|
|
800ff60: 429a cmp r2, r3
|
|
800ff62: d202 bcs.n 800ff6a <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xNextTaskUnblockTime = xTimeToWake;
|
|
800ff64: 4a09 ldr r2, [pc, #36] ; (800ff8c <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
800ff66: 68bb ldr r3, [r7, #8]
|
|
800ff68: 6013 str r3, [r2, #0]
|
|
}
|
|
800ff6a: bf00 nop
|
|
800ff6c: 3710 adds r7, #16
|
|
800ff6e: 46bd mov sp, r7
|
|
800ff70: bd80 pop {r7, pc}
|
|
800ff72: bf00 nop
|
|
800ff74: 20000690 .word 0x20000690
|
|
800ff78: 2000058c .word 0x2000058c
|
|
800ff7c: 20000694 .word 0x20000694
|
|
800ff80: 20000678 .word 0x20000678
|
|
800ff84: 20000648 .word 0x20000648
|
|
800ff88: 20000644 .word 0x20000644
|
|
800ff8c: 200006ac .word 0x200006ac
|
|
|
|
0800ff90 <pxPortInitialiseStack>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
|
{
|
|
800ff90: b480 push {r7}
|
|
800ff92: b085 sub sp, #20
|
|
800ff94: af00 add r7, sp, #0
|
|
800ff96: 60f8 str r0, [r7, #12]
|
|
800ff98: 60b9 str r1, [r7, #8]
|
|
800ff9a: 607a str r2, [r7, #4]
|
|
/* Simulate the stack frame as it would be created by a context switch
|
|
interrupt. */
|
|
|
|
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
|
of interrupts, and to ensure alignment. */
|
|
pxTopOfStack--;
|
|
800ff9c: 68fb ldr r3, [r7, #12]
|
|
800ff9e: 3b04 subs r3, #4
|
|
800ffa0: 60fb str r3, [r7, #12]
|
|
|
|
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
|
800ffa2: 68fb ldr r3, [r7, #12]
|
|
800ffa4: f04f 7280 mov.w r2, #16777216 ; 0x1000000
|
|
800ffa8: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800ffaa: 68fb ldr r3, [r7, #12]
|
|
800ffac: 3b04 subs r3, #4
|
|
800ffae: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
|
|
800ffb0: 68bb ldr r3, [r7, #8]
|
|
800ffb2: f023 0201 bic.w r2, r3, #1
|
|
800ffb6: 68fb ldr r3, [r7, #12]
|
|
800ffb8: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800ffba: 68fb ldr r3, [r7, #12]
|
|
800ffbc: 3b04 subs r3, #4
|
|
800ffbe: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
|
|
800ffc0: 4a0c ldr r2, [pc, #48] ; (800fff4 <pxPortInitialiseStack+0x64>)
|
|
800ffc2: 68fb ldr r3, [r7, #12]
|
|
800ffc4: 601a str r2, [r3, #0]
|
|
|
|
/* Save code space by skipping register initialisation. */
|
|
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
|
800ffc6: 68fb ldr r3, [r7, #12]
|
|
800ffc8: 3b14 subs r3, #20
|
|
800ffca: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
|
800ffcc: 687a ldr r2, [r7, #4]
|
|
800ffce: 68fb ldr r3, [r7, #12]
|
|
800ffd0: 601a str r2, [r3, #0]
|
|
|
|
/* A save method is being used that requires each task to maintain its
|
|
own exec return value. */
|
|
pxTopOfStack--;
|
|
800ffd2: 68fb ldr r3, [r7, #12]
|
|
800ffd4: 3b04 subs r3, #4
|
|
800ffd6: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
|
800ffd8: 68fb ldr r3, [r7, #12]
|
|
800ffda: f06f 0202 mvn.w r2, #2
|
|
800ffde: 601a str r2, [r3, #0]
|
|
|
|
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
|
800ffe0: 68fb ldr r3, [r7, #12]
|
|
800ffe2: 3b20 subs r3, #32
|
|
800ffe4: 60fb str r3, [r7, #12]
|
|
|
|
return pxTopOfStack;
|
|
800ffe6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800ffe8: 4618 mov r0, r3
|
|
800ffea: 3714 adds r7, #20
|
|
800ffec: 46bd mov sp, r7
|
|
800ffee: f85d 7b04 ldr.w r7, [sp], #4
|
|
800fff2: 4770 bx lr
|
|
800fff4: 0800fff9 .word 0x0800fff9
|
|
|
|
0800fff8 <prvTaskExitError>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvTaskExitError( void )
|
|
{
|
|
800fff8: b480 push {r7}
|
|
800fffa: b085 sub sp, #20
|
|
800fffc: af00 add r7, sp, #0
|
|
volatile uint32_t ulDummy = 0;
|
|
800fffe: 2300 movs r3, #0
|
|
8010000: 607b str r3, [r7, #4]
|
|
its caller as there is nothing to return to. If a task wants to exit it
|
|
should instead call vTaskDelete( NULL ).
|
|
|
|
Artificially force an assert() to be triggered if configASSERT() is
|
|
defined, then stop here so application writers can catch the error. */
|
|
configASSERT( uxCriticalNesting == ~0UL );
|
|
8010002: 4b13 ldr r3, [pc, #76] ; (8010050 <prvTaskExitError+0x58>)
|
|
8010004: 681b ldr r3, [r3, #0]
|
|
8010006: f1b3 3fff cmp.w r3, #4294967295
|
|
801000a: d00b beq.n 8010024 <prvTaskExitError+0x2c>
|
|
801000c: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010010: b672 cpsid i
|
|
8010012: f383 8811 msr BASEPRI, r3
|
|
8010016: f3bf 8f6f isb sy
|
|
801001a: f3bf 8f4f dsb sy
|
|
801001e: b662 cpsie i
|
|
8010020: 60fb str r3, [r7, #12]
|
|
8010022: e7fe b.n 8010022 <prvTaskExitError+0x2a>
|
|
8010024: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010028: b672 cpsid i
|
|
801002a: f383 8811 msr BASEPRI, r3
|
|
801002e: f3bf 8f6f isb sy
|
|
8010032: f3bf 8f4f dsb sy
|
|
8010036: b662 cpsie i
|
|
8010038: 60bb str r3, [r7, #8]
|
|
portDISABLE_INTERRUPTS();
|
|
while( ulDummy == 0 )
|
|
801003a: bf00 nop
|
|
801003c: 687b ldr r3, [r7, #4]
|
|
801003e: 2b00 cmp r3, #0
|
|
8010040: d0fc beq.n 801003c <prvTaskExitError+0x44>
|
|
about code appearing after this function is called - making ulDummy
|
|
volatile makes the compiler think the function could return and
|
|
therefore not output an 'unreachable code' warning for code that appears
|
|
after it. */
|
|
}
|
|
}
|
|
8010042: bf00 nop
|
|
8010044: 3714 adds r7, #20
|
|
8010046: 46bd mov sp, r7
|
|
8010048: f85d 7b04 ldr.w r7, [sp], #4
|
|
801004c: 4770 bx lr
|
|
801004e: bf00 nop
|
|
8010050: 20000070 .word 0x20000070
|
|
...
|
|
|
|
08010060 <SVC_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortSVCHandler( void )
|
|
{
|
|
__asm volatile (
|
|
8010060: 4b07 ldr r3, [pc, #28] ; (8010080 <pxCurrentTCBConst2>)
|
|
8010062: 6819 ldr r1, [r3, #0]
|
|
8010064: 6808 ldr r0, [r1, #0]
|
|
8010066: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801006a: f380 8809 msr PSP, r0
|
|
801006e: f3bf 8f6f isb sy
|
|
8010072: f04f 0000 mov.w r0, #0
|
|
8010076: f380 8811 msr BASEPRI, r0
|
|
801007a: 4770 bx lr
|
|
801007c: f3af 8000 nop.w
|
|
|
|
08010080 <pxCurrentTCBConst2>:
|
|
8010080: 2000058c .word 0x2000058c
|
|
" bx r14 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
|
);
|
|
}
|
|
8010084: bf00 nop
|
|
8010086: bf00 nop
|
|
|
|
08010088 <prvPortStartFirstTask>:
|
|
{
|
|
/* Start the first task. This also clears the bit that indicates the FPU is
|
|
in use in case the FPU was used before the scheduler was started - which
|
|
would otherwise result in the unnecessary leaving of space in the SVC stack
|
|
for lazy saving of FPU registers. */
|
|
__asm volatile(
|
|
8010088: 4808 ldr r0, [pc, #32] ; (80100ac <prvPortStartFirstTask+0x24>)
|
|
801008a: 6800 ldr r0, [r0, #0]
|
|
801008c: 6800 ldr r0, [r0, #0]
|
|
801008e: f380 8808 msr MSP, r0
|
|
8010092: f04f 0000 mov.w r0, #0
|
|
8010096: f380 8814 msr CONTROL, r0
|
|
801009a: b662 cpsie i
|
|
801009c: b661 cpsie f
|
|
801009e: f3bf 8f4f dsb sy
|
|
80100a2: f3bf 8f6f isb sy
|
|
80100a6: df00 svc 0
|
|
80100a8: bf00 nop
|
|
" dsb \n"
|
|
" isb \n"
|
|
" svc 0 \n" /* System call to start first task. */
|
|
" nop \n"
|
|
);
|
|
}
|
|
80100aa: bf00 nop
|
|
80100ac: e000ed08 .word 0xe000ed08
|
|
|
|
080100b0 <xPortStartScheduler>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
80100b0: b580 push {r7, lr}
|
|
80100b2: b084 sub sp, #16
|
|
80100b4: af00 add r7, sp, #0
|
|
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
volatile uint32_t ulOriginalPriority;
|
|
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
|
|
80100b6: 4b36 ldr r3, [pc, #216] ; (8010190 <xPortStartScheduler+0xe0>)
|
|
80100b8: 60fb str r3, [r7, #12]
|
|
functions can be called. ISR safe functions are those that end in
|
|
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
|
|
ensure interrupt entry is as fast and simple as possible.
|
|
|
|
Save the interrupt priority value that is about to be clobbered. */
|
|
ulOriginalPriority = *pucFirstUserPriorityRegister;
|
|
80100ba: 68fb ldr r3, [r7, #12]
|
|
80100bc: 781b ldrb r3, [r3, #0]
|
|
80100be: b2db uxtb r3, r3
|
|
80100c0: 607b str r3, [r7, #4]
|
|
|
|
/* Determine the number of priority bits available. First write to all
|
|
possible bits. */
|
|
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
|
|
80100c2: 68fb ldr r3, [r7, #12]
|
|
80100c4: 22ff movs r2, #255 ; 0xff
|
|
80100c6: 701a strb r2, [r3, #0]
|
|
|
|
/* Read the value back to see how many bits stuck. */
|
|
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
|
80100c8: 68fb ldr r3, [r7, #12]
|
|
80100ca: 781b ldrb r3, [r3, #0]
|
|
80100cc: b2db uxtb r3, r3
|
|
80100ce: 70fb strb r3, [r7, #3]
|
|
|
|
/* Use the same mask on the maximum system call priority. */
|
|
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
|
80100d0: 78fb ldrb r3, [r7, #3]
|
|
80100d2: b2db uxtb r3, r3
|
|
80100d4: f003 0350 and.w r3, r3, #80 ; 0x50
|
|
80100d8: b2da uxtb r2, r3
|
|
80100da: 4b2e ldr r3, [pc, #184] ; (8010194 <xPortStartScheduler+0xe4>)
|
|
80100dc: 701a strb r2, [r3, #0]
|
|
|
|
/* Calculate the maximum acceptable priority group value for the number
|
|
of bits read back. */
|
|
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
|
80100de: 4b2e ldr r3, [pc, #184] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
80100e0: 2207 movs r2, #7
|
|
80100e2: 601a str r2, [r3, #0]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
80100e4: e009 b.n 80100fa <xPortStartScheduler+0x4a>
|
|
{
|
|
ulMaxPRIGROUPValue--;
|
|
80100e6: 4b2c ldr r3, [pc, #176] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
80100e8: 681b ldr r3, [r3, #0]
|
|
80100ea: 3b01 subs r3, #1
|
|
80100ec: 4a2a ldr r2, [pc, #168] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
80100ee: 6013 str r3, [r2, #0]
|
|
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
|
80100f0: 78fb ldrb r3, [r7, #3]
|
|
80100f2: b2db uxtb r3, r3
|
|
80100f4: 005b lsls r3, r3, #1
|
|
80100f6: b2db uxtb r3, r3
|
|
80100f8: 70fb strb r3, [r7, #3]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
80100fa: 78fb ldrb r3, [r7, #3]
|
|
80100fc: b2db uxtb r3, r3
|
|
80100fe: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
8010102: 2b80 cmp r3, #128 ; 0x80
|
|
8010104: d0ef beq.n 80100e6 <xPortStartScheduler+0x36>
|
|
#ifdef configPRIO_BITS
|
|
{
|
|
/* Check the FreeRTOS configuration that defines the number of
|
|
priority bits matches the number of priority bits actually queried
|
|
from the hardware. */
|
|
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
|
|
8010106: 4b24 ldr r3, [pc, #144] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
8010108: 681b ldr r3, [r3, #0]
|
|
801010a: f1c3 0307 rsb r3, r3, #7
|
|
801010e: 2b04 cmp r3, #4
|
|
8010110: d00b beq.n 801012a <xPortStartScheduler+0x7a>
|
|
8010112: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010116: b672 cpsid i
|
|
8010118: f383 8811 msr BASEPRI, r3
|
|
801011c: f3bf 8f6f isb sy
|
|
8010120: f3bf 8f4f dsb sy
|
|
8010124: b662 cpsie i
|
|
8010126: 60bb str r3, [r7, #8]
|
|
8010128: e7fe b.n 8010128 <xPortStartScheduler+0x78>
|
|
}
|
|
#endif
|
|
|
|
/* Shift the priority group value back to its position within the AIRCR
|
|
register. */
|
|
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
|
801012a: 4b1b ldr r3, [pc, #108] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
801012c: 681b ldr r3, [r3, #0]
|
|
801012e: 021b lsls r3, r3, #8
|
|
8010130: 4a19 ldr r2, [pc, #100] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
8010132: 6013 str r3, [r2, #0]
|
|
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
|
8010134: 4b18 ldr r3, [pc, #96] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
8010136: 681b ldr r3, [r3, #0]
|
|
8010138: f403 63e0 and.w r3, r3, #1792 ; 0x700
|
|
801013c: 4a16 ldr r2, [pc, #88] ; (8010198 <xPortStartScheduler+0xe8>)
|
|
801013e: 6013 str r3, [r2, #0]
|
|
|
|
/* Restore the clobbered interrupt priority register to its original
|
|
value. */
|
|
*pucFirstUserPriorityRegister = ulOriginalPriority;
|
|
8010140: 687b ldr r3, [r7, #4]
|
|
8010142: b2da uxtb r2, r3
|
|
8010144: 68fb ldr r3, [r7, #12]
|
|
8010146: 701a strb r2, [r3, #0]
|
|
}
|
|
#endif /* conifgASSERT_DEFINED */
|
|
|
|
/* Make PendSV and SysTick the lowest priority interrupts. */
|
|
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
|
8010148: 4b14 ldr r3, [pc, #80] ; (801019c <xPortStartScheduler+0xec>)
|
|
801014a: 681b ldr r3, [r3, #0]
|
|
801014c: 4a13 ldr r2, [pc, #76] ; (801019c <xPortStartScheduler+0xec>)
|
|
801014e: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
|
|
8010152: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
|
8010154: 4b11 ldr r3, [pc, #68] ; (801019c <xPortStartScheduler+0xec>)
|
|
8010156: 681b ldr r3, [r3, #0]
|
|
8010158: 4a10 ldr r2, [pc, #64] ; (801019c <xPortStartScheduler+0xec>)
|
|
801015a: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
|
|
801015e: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
|
here already. */
|
|
vPortSetupTimerInterrupt();
|
|
8010160: f000 f8d4 bl 801030c <vPortSetupTimerInterrupt>
|
|
|
|
/* Initialise the critical nesting count ready for the first task. */
|
|
uxCriticalNesting = 0;
|
|
8010164: 4b0e ldr r3, [pc, #56] ; (80101a0 <xPortStartScheduler+0xf0>)
|
|
8010166: 2200 movs r2, #0
|
|
8010168: 601a str r2, [r3, #0]
|
|
|
|
/* Ensure the VFP is enabled - it should be anyway. */
|
|
vPortEnableVFP();
|
|
801016a: f000 f8f3 bl 8010354 <vPortEnableVFP>
|
|
|
|
/* Lazy save always. */
|
|
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
|
801016e: 4b0d ldr r3, [pc, #52] ; (80101a4 <xPortStartScheduler+0xf4>)
|
|
8010170: 681b ldr r3, [r3, #0]
|
|
8010172: 4a0c ldr r2, [pc, #48] ; (80101a4 <xPortStartScheduler+0xf4>)
|
|
8010174: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
|
|
8010178: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the first task. */
|
|
prvPortStartFirstTask();
|
|
801017a: f7ff ff85 bl 8010088 <prvPortStartFirstTask>
|
|
exit error function to prevent compiler warnings about a static function
|
|
not being called in the case that the application writer overrides this
|
|
functionality by defining configTASK_RETURN_ADDRESS. Call
|
|
vTaskSwitchContext() so link time optimisation does not remove the
|
|
symbol. */
|
|
vTaskSwitchContext();
|
|
801017e: f7ff fa63 bl 800f648 <vTaskSwitchContext>
|
|
prvTaskExitError();
|
|
8010182: f7ff ff39 bl 800fff8 <prvTaskExitError>
|
|
|
|
/* Should not get here! */
|
|
return 0;
|
|
8010186: 2300 movs r3, #0
|
|
}
|
|
8010188: 4618 mov r0, r3
|
|
801018a: 3710 adds r7, #16
|
|
801018c: 46bd mov sp, r7
|
|
801018e: bd80 pop {r7, pc}
|
|
8010190: e000e400 .word 0xe000e400
|
|
8010194: 200006b8 .word 0x200006b8
|
|
8010198: 200006bc .word 0x200006bc
|
|
801019c: e000ed20 .word 0xe000ed20
|
|
80101a0: 20000070 .word 0x20000070
|
|
80101a4: e000ef34 .word 0xe000ef34
|
|
|
|
080101a8 <vPortEnterCritical>:
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
80101a8: b480 push {r7}
|
|
80101aa: b083 sub sp, #12
|
|
80101ac: af00 add r7, sp, #0
|
|
80101ae: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80101b2: b672 cpsid i
|
|
80101b4: f383 8811 msr BASEPRI, r3
|
|
80101b8: f3bf 8f6f isb sy
|
|
80101bc: f3bf 8f4f dsb sy
|
|
80101c0: b662 cpsie i
|
|
80101c2: 607b str r3, [r7, #4]
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
80101c4: 4b0f ldr r3, [pc, #60] ; (8010204 <vPortEnterCritical+0x5c>)
|
|
80101c6: 681b ldr r3, [r3, #0]
|
|
80101c8: 3301 adds r3, #1
|
|
80101ca: 4a0e ldr r2, [pc, #56] ; (8010204 <vPortEnterCritical+0x5c>)
|
|
80101cc: 6013 str r3, [r2, #0]
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
assert() if it is being called from an interrupt context. Only API
|
|
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
the critical nesting count is 1 to protect against recursive calls if the
|
|
assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
80101ce: 4b0d ldr r3, [pc, #52] ; (8010204 <vPortEnterCritical+0x5c>)
|
|
80101d0: 681b ldr r3, [r3, #0]
|
|
80101d2: 2b01 cmp r3, #1
|
|
80101d4: d110 bne.n 80101f8 <vPortEnterCritical+0x50>
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
80101d6: 4b0c ldr r3, [pc, #48] ; (8010208 <vPortEnterCritical+0x60>)
|
|
80101d8: 681b ldr r3, [r3, #0]
|
|
80101da: b2db uxtb r3, r3
|
|
80101dc: 2b00 cmp r3, #0
|
|
80101de: d00b beq.n 80101f8 <vPortEnterCritical+0x50>
|
|
80101e0: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80101e4: b672 cpsid i
|
|
80101e6: f383 8811 msr BASEPRI, r3
|
|
80101ea: f3bf 8f6f isb sy
|
|
80101ee: f3bf 8f4f dsb sy
|
|
80101f2: b662 cpsie i
|
|
80101f4: 603b str r3, [r7, #0]
|
|
80101f6: e7fe b.n 80101f6 <vPortEnterCritical+0x4e>
|
|
}
|
|
}
|
|
80101f8: bf00 nop
|
|
80101fa: 370c adds r7, #12
|
|
80101fc: 46bd mov sp, r7
|
|
80101fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010202: 4770 bx lr
|
|
8010204: 20000070 .word 0x20000070
|
|
8010208: e000ed04 .word 0xe000ed04
|
|
|
|
0801020c <vPortExitCritical>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
801020c: b480 push {r7}
|
|
801020e: b083 sub sp, #12
|
|
8010210: af00 add r7, sp, #0
|
|
configASSERT( uxCriticalNesting );
|
|
8010212: 4b12 ldr r3, [pc, #72] ; (801025c <vPortExitCritical+0x50>)
|
|
8010214: 681b ldr r3, [r3, #0]
|
|
8010216: 2b00 cmp r3, #0
|
|
8010218: d10b bne.n 8010232 <vPortExitCritical+0x26>
|
|
801021a: f04f 0350 mov.w r3, #80 ; 0x50
|
|
801021e: b672 cpsid i
|
|
8010220: f383 8811 msr BASEPRI, r3
|
|
8010224: f3bf 8f6f isb sy
|
|
8010228: f3bf 8f4f dsb sy
|
|
801022c: b662 cpsie i
|
|
801022e: 607b str r3, [r7, #4]
|
|
8010230: e7fe b.n 8010230 <vPortExitCritical+0x24>
|
|
uxCriticalNesting--;
|
|
8010232: 4b0a ldr r3, [pc, #40] ; (801025c <vPortExitCritical+0x50>)
|
|
8010234: 681b ldr r3, [r3, #0]
|
|
8010236: 3b01 subs r3, #1
|
|
8010238: 4a08 ldr r2, [pc, #32] ; (801025c <vPortExitCritical+0x50>)
|
|
801023a: 6013 str r3, [r2, #0]
|
|
if( uxCriticalNesting == 0 )
|
|
801023c: 4b07 ldr r3, [pc, #28] ; (801025c <vPortExitCritical+0x50>)
|
|
801023e: 681b ldr r3, [r3, #0]
|
|
8010240: 2b00 cmp r3, #0
|
|
8010242: d104 bne.n 801024e <vPortExitCritical+0x42>
|
|
8010244: 2300 movs r3, #0
|
|
8010246: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
8010248: 683b ldr r3, [r7, #0]
|
|
801024a: f383 8811 msr BASEPRI, r3
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
}
|
|
801024e: bf00 nop
|
|
8010250: 370c adds r7, #12
|
|
8010252: 46bd mov sp, r7
|
|
8010254: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010258: 4770 bx lr
|
|
801025a: bf00 nop
|
|
801025c: 20000070 .word 0x20000070
|
|
|
|
08010260 <PendSV_Handler>:
|
|
|
|
void xPortPendSVHandler( void )
|
|
{
|
|
/* This is a naked function. */
|
|
|
|
__asm volatile
|
|
8010260: f3ef 8009 mrs r0, PSP
|
|
8010264: f3bf 8f6f isb sy
|
|
8010268: 4b15 ldr r3, [pc, #84] ; (80102c0 <pxCurrentTCBConst>)
|
|
801026a: 681a ldr r2, [r3, #0]
|
|
801026c: f01e 0f10 tst.w lr, #16
|
|
8010270: bf08 it eq
|
|
8010272: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
|
8010276: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801027a: 6010 str r0, [r2, #0]
|
|
801027c: e92d 0009 stmdb sp!, {r0, r3}
|
|
8010280: f04f 0050 mov.w r0, #80 ; 0x50
|
|
8010284: b672 cpsid i
|
|
8010286: f380 8811 msr BASEPRI, r0
|
|
801028a: f3bf 8f4f dsb sy
|
|
801028e: f3bf 8f6f isb sy
|
|
8010292: b662 cpsie i
|
|
8010294: f7ff f9d8 bl 800f648 <vTaskSwitchContext>
|
|
8010298: f04f 0000 mov.w r0, #0
|
|
801029c: f380 8811 msr BASEPRI, r0
|
|
80102a0: bc09 pop {r0, r3}
|
|
80102a2: 6819 ldr r1, [r3, #0]
|
|
80102a4: 6808 ldr r0, [r1, #0]
|
|
80102a6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80102aa: f01e 0f10 tst.w lr, #16
|
|
80102ae: bf08 it eq
|
|
80102b0: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
|
80102b4: f380 8809 msr PSP, r0
|
|
80102b8: f3bf 8f6f isb sy
|
|
80102bc: 4770 bx lr
|
|
80102be: bf00 nop
|
|
|
|
080102c0 <pxCurrentTCBConst>:
|
|
80102c0: 2000058c .word 0x2000058c
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
|
);
|
|
}
|
|
80102c4: bf00 nop
|
|
80102c6: bf00 nop
|
|
|
|
080102c8 <SysTick_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
80102c8: b580 push {r7, lr}
|
|
80102ca: b082 sub sp, #8
|
|
80102cc: af00 add r7, sp, #0
|
|
__asm volatile
|
|
80102ce: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80102d2: b672 cpsid i
|
|
80102d4: f383 8811 msr BASEPRI, r3
|
|
80102d8: f3bf 8f6f isb sy
|
|
80102dc: f3bf 8f4f dsb sy
|
|
80102e0: b662 cpsie i
|
|
80102e2: 607b str r3, [r7, #4]
|
|
save and then restore the interrupt mask value as its value is already
|
|
known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
80102e4: f7ff f8f6 bl 800f4d4 <xTaskIncrementTick>
|
|
80102e8: 4603 mov r3, r0
|
|
80102ea: 2b00 cmp r3, #0
|
|
80102ec: d003 beq.n 80102f6 <SysTick_Handler+0x2e>
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
80102ee: 4b06 ldr r3, [pc, #24] ; (8010308 <SysTick_Handler+0x40>)
|
|
80102f0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
|
|
80102f4: 601a str r2, [r3, #0]
|
|
80102f6: 2300 movs r3, #0
|
|
80102f8: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
80102fa: 683b ldr r3, [r7, #0]
|
|
80102fc: f383 8811 msr BASEPRI, r3
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
8010300: bf00 nop
|
|
8010302: 3708 adds r7, #8
|
|
8010304: 46bd mov sp, r7
|
|
8010306: bd80 pop {r7, pc}
|
|
8010308: e000ed04 .word 0xe000ed04
|
|
|
|
0801030c <vPortSetupTimerInterrupt>:
|
|
/*
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
|
* frequency.
|
|
*/
|
|
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
|
{
|
|
801030c: b480 push {r7}
|
|
801030e: af00 add r7, sp, #0
|
|
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
|
}
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
|
|
/* Stop and clear the SysTick. */
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
8010310: 4b0b ldr r3, [pc, #44] ; (8010340 <vPortSetupTimerInterrupt+0x34>)
|
|
8010312: 2200 movs r2, #0
|
|
8010314: 601a str r2, [r3, #0]
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
8010316: 4b0b ldr r3, [pc, #44] ; (8010344 <vPortSetupTimerInterrupt+0x38>)
|
|
8010318: 2200 movs r2, #0
|
|
801031a: 601a str r2, [r3, #0]
|
|
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
801031c: 4b0a ldr r3, [pc, #40] ; (8010348 <vPortSetupTimerInterrupt+0x3c>)
|
|
801031e: 681b ldr r3, [r3, #0]
|
|
8010320: 4a0a ldr r2, [pc, #40] ; (801034c <vPortSetupTimerInterrupt+0x40>)
|
|
8010322: fba2 2303 umull r2, r3, r2, r3
|
|
8010326: 099b lsrs r3, r3, #6
|
|
8010328: 4a09 ldr r2, [pc, #36] ; (8010350 <vPortSetupTimerInterrupt+0x44>)
|
|
801032a: 3b01 subs r3, #1
|
|
801032c: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
801032e: 4b04 ldr r3, [pc, #16] ; (8010340 <vPortSetupTimerInterrupt+0x34>)
|
|
8010330: 2207 movs r2, #7
|
|
8010332: 601a str r2, [r3, #0]
|
|
}
|
|
8010334: bf00 nop
|
|
8010336: 46bd mov sp, r7
|
|
8010338: f85d 7b04 ldr.w r7, [sp], #4
|
|
801033c: 4770 bx lr
|
|
801033e: bf00 nop
|
|
8010340: e000e010 .word 0xe000e010
|
|
8010344: e000e018 .word 0xe000e018
|
|
8010348: 20000064 .word 0x20000064
|
|
801034c: 10624dd3 .word 0x10624dd3
|
|
8010350: e000e014 .word 0xe000e014
|
|
|
|
08010354 <vPortEnableVFP>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/* This is a naked function. */
|
|
static void vPortEnableVFP( void )
|
|
{
|
|
__asm volatile
|
|
8010354: f8df 000c ldr.w r0, [pc, #12] ; 8010364 <vPortEnableVFP+0x10>
|
|
8010358: 6801 ldr r1, [r0, #0]
|
|
801035a: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
|
|
801035e: 6001 str r1, [r0, #0]
|
|
8010360: 4770 bx lr
|
|
" \n"
|
|
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
|
" str r1, [r0] \n"
|
|
" bx r14 "
|
|
);
|
|
}
|
|
8010362: bf00 nop
|
|
8010364: e000ed88 .word 0xe000ed88
|
|
|
|
08010368 <vPortValidateInterruptPriority>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
8010368: b480 push {r7}
|
|
801036a: b085 sub sp, #20
|
|
801036c: af00 add r7, sp, #0
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
801036e: f3ef 8305 mrs r3, IPSR
|
|
8010372: 60fb str r3, [r7, #12]
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
8010374: 68fb ldr r3, [r7, #12]
|
|
8010376: 2b0f cmp r3, #15
|
|
8010378: d915 bls.n 80103a6 <vPortValidateInterruptPriority+0x3e>
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
801037a: 4a18 ldr r2, [pc, #96] ; (80103dc <vPortValidateInterruptPriority+0x74>)
|
|
801037c: 68fb ldr r3, [r7, #12]
|
|
801037e: 4413 add r3, r2
|
|
8010380: 781b ldrb r3, [r3, #0]
|
|
8010382: 72fb strb r3, [r7, #11]
|
|
interrupt entry is as fast and simple as possible.
|
|
|
|
The following links provide detailed information:
|
|
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
http://www.freertos.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
8010384: 4b16 ldr r3, [pc, #88] ; (80103e0 <vPortValidateInterruptPriority+0x78>)
|
|
8010386: 781b ldrb r3, [r3, #0]
|
|
8010388: 7afa ldrb r2, [r7, #11]
|
|
801038a: 429a cmp r2, r3
|
|
801038c: d20b bcs.n 80103a6 <vPortValidateInterruptPriority+0x3e>
|
|
__asm volatile
|
|
801038e: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010392: b672 cpsid i
|
|
8010394: f383 8811 msr BASEPRI, r3
|
|
8010398: f3bf 8f6f isb sy
|
|
801039c: f3bf 8f4f dsb sy
|
|
80103a0: b662 cpsie i
|
|
80103a2: 607b str r3, [r7, #4]
|
|
80103a4: e7fe b.n 80103a4 <vPortValidateInterruptPriority+0x3c>
|
|
configuration then the correct setting can be achieved on all Cortex-M
|
|
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
scheduler. Note however that some vendor specific peripheral libraries
|
|
assume a non-zero priority group setting, in which cases using a value
|
|
of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
80103a6: 4b0f ldr r3, [pc, #60] ; (80103e4 <vPortValidateInterruptPriority+0x7c>)
|
|
80103a8: 681b ldr r3, [r3, #0]
|
|
80103aa: f403 62e0 and.w r2, r3, #1792 ; 0x700
|
|
80103ae: 4b0e ldr r3, [pc, #56] ; (80103e8 <vPortValidateInterruptPriority+0x80>)
|
|
80103b0: 681b ldr r3, [r3, #0]
|
|
80103b2: 429a cmp r2, r3
|
|
80103b4: d90b bls.n 80103ce <vPortValidateInterruptPriority+0x66>
|
|
80103b6: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80103ba: b672 cpsid i
|
|
80103bc: f383 8811 msr BASEPRI, r3
|
|
80103c0: f3bf 8f6f isb sy
|
|
80103c4: f3bf 8f4f dsb sy
|
|
80103c8: b662 cpsie i
|
|
80103ca: 603b str r3, [r7, #0]
|
|
80103cc: e7fe b.n 80103cc <vPortValidateInterruptPriority+0x64>
|
|
}
|
|
80103ce: bf00 nop
|
|
80103d0: 3714 adds r7, #20
|
|
80103d2: 46bd mov sp, r7
|
|
80103d4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80103d8: 4770 bx lr
|
|
80103da: bf00 nop
|
|
80103dc: e000e3f0 .word 0xe000e3f0
|
|
80103e0: 200006b8 .word 0x200006b8
|
|
80103e4: e000ed0c .word 0xe000ed0c
|
|
80103e8: 200006bc .word 0x200006bc
|
|
|
|
080103ec <pvPortMalloc>:
|
|
static size_t xBlockAllocatedBit = 0;
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void *pvPortMalloc( size_t xWantedSize )
|
|
{
|
|
80103ec: b580 push {r7, lr}
|
|
80103ee: b08a sub sp, #40 ; 0x28
|
|
80103f0: af00 add r7, sp, #0
|
|
80103f2: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
|
|
void *pvReturn = NULL;
|
|
80103f4: 2300 movs r3, #0
|
|
80103f6: 61fb str r3, [r7, #28]
|
|
|
|
vTaskSuspendAll();
|
|
80103f8: f7fe ff9e bl 800f338 <vTaskSuspendAll>
|
|
{
|
|
/* If this is the first call to malloc then the heap will require
|
|
initialisation to setup the list of free blocks. */
|
|
if( pxEnd == NULL )
|
|
80103fc: 4b5c ldr r3, [pc, #368] ; (8010570 <pvPortMalloc+0x184>)
|
|
80103fe: 681b ldr r3, [r3, #0]
|
|
8010400: 2b00 cmp r3, #0
|
|
8010402: d101 bne.n 8010408 <pvPortMalloc+0x1c>
|
|
{
|
|
prvHeapInit();
|
|
8010404: f000 f91a bl 801063c <prvHeapInit>
|
|
|
|
/* Check the requested block size is not so large that the top bit is
|
|
set. The top bit of the block size member of the BlockLink_t structure
|
|
is used to determine who owns the block - the application or the
|
|
kernel, so it must be free. */
|
|
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
|
|
8010408: 4b5a ldr r3, [pc, #360] ; (8010574 <pvPortMalloc+0x188>)
|
|
801040a: 681a ldr r2, [r3, #0]
|
|
801040c: 687b ldr r3, [r7, #4]
|
|
801040e: 4013 ands r3, r2
|
|
8010410: 2b00 cmp r3, #0
|
|
8010412: f040 8090 bne.w 8010536 <pvPortMalloc+0x14a>
|
|
{
|
|
/* The wanted size is increased so it can contain a BlockLink_t
|
|
structure in addition to the requested amount of bytes. */
|
|
if( xWantedSize > 0 )
|
|
8010416: 687b ldr r3, [r7, #4]
|
|
8010418: 2b00 cmp r3, #0
|
|
801041a: d01e beq.n 801045a <pvPortMalloc+0x6e>
|
|
{
|
|
xWantedSize += xHeapStructSize;
|
|
801041c: 2208 movs r2, #8
|
|
801041e: 687b ldr r3, [r7, #4]
|
|
8010420: 4413 add r3, r2
|
|
8010422: 607b str r3, [r7, #4]
|
|
|
|
/* Ensure that blocks are always aligned to the required number
|
|
of bytes. */
|
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
|
8010424: 687b ldr r3, [r7, #4]
|
|
8010426: f003 0307 and.w r3, r3, #7
|
|
801042a: 2b00 cmp r3, #0
|
|
801042c: d015 beq.n 801045a <pvPortMalloc+0x6e>
|
|
{
|
|
/* Byte alignment required. */
|
|
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
|
|
801042e: 687b ldr r3, [r7, #4]
|
|
8010430: f023 0307 bic.w r3, r3, #7
|
|
8010434: 3308 adds r3, #8
|
|
8010436: 607b str r3, [r7, #4]
|
|
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
8010438: 687b ldr r3, [r7, #4]
|
|
801043a: f003 0307 and.w r3, r3, #7
|
|
801043e: 2b00 cmp r3, #0
|
|
8010440: d00b beq.n 801045a <pvPortMalloc+0x6e>
|
|
8010442: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010446: b672 cpsid i
|
|
8010448: f383 8811 msr BASEPRI, r3
|
|
801044c: f3bf 8f6f isb sy
|
|
8010450: f3bf 8f4f dsb sy
|
|
8010454: b662 cpsie i
|
|
8010456: 617b str r3, [r7, #20]
|
|
8010458: e7fe b.n 8010458 <pvPortMalloc+0x6c>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
|
801045a: 687b ldr r3, [r7, #4]
|
|
801045c: 2b00 cmp r3, #0
|
|
801045e: d06a beq.n 8010536 <pvPortMalloc+0x14a>
|
|
8010460: 4b45 ldr r3, [pc, #276] ; (8010578 <pvPortMalloc+0x18c>)
|
|
8010462: 681b ldr r3, [r3, #0]
|
|
8010464: 687a ldr r2, [r7, #4]
|
|
8010466: 429a cmp r2, r3
|
|
8010468: d865 bhi.n 8010536 <pvPortMalloc+0x14a>
|
|
{
|
|
/* Traverse the list from the start (lowest address) block until
|
|
one of adequate size is found. */
|
|
pxPreviousBlock = &xStart;
|
|
801046a: 4b44 ldr r3, [pc, #272] ; (801057c <pvPortMalloc+0x190>)
|
|
801046c: 623b str r3, [r7, #32]
|
|
pxBlock = xStart.pxNextFreeBlock;
|
|
801046e: 4b43 ldr r3, [pc, #268] ; (801057c <pvPortMalloc+0x190>)
|
|
8010470: 681b ldr r3, [r3, #0]
|
|
8010472: 627b str r3, [r7, #36] ; 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
8010474: e004 b.n 8010480 <pvPortMalloc+0x94>
|
|
{
|
|
pxPreviousBlock = pxBlock;
|
|
8010476: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8010478: 623b str r3, [r7, #32]
|
|
pxBlock = pxBlock->pxNextFreeBlock;
|
|
801047a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801047c: 681b ldr r3, [r3, #0]
|
|
801047e: 627b str r3, [r7, #36] ; 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
8010480: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8010482: 685b ldr r3, [r3, #4]
|
|
8010484: 687a ldr r2, [r7, #4]
|
|
8010486: 429a cmp r2, r3
|
|
8010488: d903 bls.n 8010492 <pvPortMalloc+0xa6>
|
|
801048a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801048c: 681b ldr r3, [r3, #0]
|
|
801048e: 2b00 cmp r3, #0
|
|
8010490: d1f1 bne.n 8010476 <pvPortMalloc+0x8a>
|
|
}
|
|
|
|
/* If the end marker was reached then a block of adequate size
|
|
was not found. */
|
|
if( pxBlock != pxEnd )
|
|
8010492: 4b37 ldr r3, [pc, #220] ; (8010570 <pvPortMalloc+0x184>)
|
|
8010494: 681b ldr r3, [r3, #0]
|
|
8010496: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8010498: 429a cmp r2, r3
|
|
801049a: d04c beq.n 8010536 <pvPortMalloc+0x14a>
|
|
{
|
|
/* Return the memory space pointed to - jumping over the
|
|
BlockLink_t structure at its start. */
|
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
|
801049c: 6a3b ldr r3, [r7, #32]
|
|
801049e: 681b ldr r3, [r3, #0]
|
|
80104a0: 2208 movs r2, #8
|
|
80104a2: 4413 add r3, r2
|
|
80104a4: 61fb str r3, [r7, #28]
|
|
|
|
/* This block is being returned for use so must be taken out
|
|
of the list of free blocks. */
|
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
|
80104a6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80104a8: 681a ldr r2, [r3, #0]
|
|
80104aa: 6a3b ldr r3, [r7, #32]
|
|
80104ac: 601a str r2, [r3, #0]
|
|
|
|
/* If the block is larger than required it can be split into
|
|
two. */
|
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
|
80104ae: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80104b0: 685a ldr r2, [r3, #4]
|
|
80104b2: 687b ldr r3, [r7, #4]
|
|
80104b4: 1ad2 subs r2, r2, r3
|
|
80104b6: 2308 movs r3, #8
|
|
80104b8: 005b lsls r3, r3, #1
|
|
80104ba: 429a cmp r2, r3
|
|
80104bc: d920 bls.n 8010500 <pvPortMalloc+0x114>
|
|
{
|
|
/* This block is to be split into two. Create a new
|
|
block following the number of bytes requested. The void
|
|
cast is used to prevent byte alignment warnings from the
|
|
compiler. */
|
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
|
80104be: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
80104c0: 687b ldr r3, [r7, #4]
|
|
80104c2: 4413 add r3, r2
|
|
80104c4: 61bb str r3, [r7, #24]
|
|
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
80104c6: 69bb ldr r3, [r7, #24]
|
|
80104c8: f003 0307 and.w r3, r3, #7
|
|
80104cc: 2b00 cmp r3, #0
|
|
80104ce: d00b beq.n 80104e8 <pvPortMalloc+0xfc>
|
|
80104d0: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80104d4: b672 cpsid i
|
|
80104d6: f383 8811 msr BASEPRI, r3
|
|
80104da: f3bf 8f6f isb sy
|
|
80104de: f3bf 8f4f dsb sy
|
|
80104e2: b662 cpsie i
|
|
80104e4: 613b str r3, [r7, #16]
|
|
80104e6: e7fe b.n 80104e6 <pvPortMalloc+0xfa>
|
|
|
|
/* Calculate the sizes of two blocks split from the
|
|
single block. */
|
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
|
80104e8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80104ea: 685a ldr r2, [r3, #4]
|
|
80104ec: 687b ldr r3, [r7, #4]
|
|
80104ee: 1ad2 subs r2, r2, r3
|
|
80104f0: 69bb ldr r3, [r7, #24]
|
|
80104f2: 605a str r2, [r3, #4]
|
|
pxBlock->xBlockSize = xWantedSize;
|
|
80104f4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80104f6: 687a ldr r2, [r7, #4]
|
|
80104f8: 605a str r2, [r3, #4]
|
|
|
|
/* Insert the new block into the list of free blocks. */
|
|
prvInsertBlockIntoFreeList( pxNewBlockLink );
|
|
80104fa: 69b8 ldr r0, [r7, #24]
|
|
80104fc: f000 f900 bl 8010700 <prvInsertBlockIntoFreeList>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
|
8010500: 4b1d ldr r3, [pc, #116] ; (8010578 <pvPortMalloc+0x18c>)
|
|
8010502: 681a ldr r2, [r3, #0]
|
|
8010504: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8010506: 685b ldr r3, [r3, #4]
|
|
8010508: 1ad3 subs r3, r2, r3
|
|
801050a: 4a1b ldr r2, [pc, #108] ; (8010578 <pvPortMalloc+0x18c>)
|
|
801050c: 6013 str r3, [r2, #0]
|
|
|
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
|
801050e: 4b1a ldr r3, [pc, #104] ; (8010578 <pvPortMalloc+0x18c>)
|
|
8010510: 681a ldr r2, [r3, #0]
|
|
8010512: 4b1b ldr r3, [pc, #108] ; (8010580 <pvPortMalloc+0x194>)
|
|
8010514: 681b ldr r3, [r3, #0]
|
|
8010516: 429a cmp r2, r3
|
|
8010518: d203 bcs.n 8010522 <pvPortMalloc+0x136>
|
|
{
|
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
|
801051a: 4b17 ldr r3, [pc, #92] ; (8010578 <pvPortMalloc+0x18c>)
|
|
801051c: 681b ldr r3, [r3, #0]
|
|
801051e: 4a18 ldr r2, [pc, #96] ; (8010580 <pvPortMalloc+0x194>)
|
|
8010520: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* The block is being returned - it is allocated and owned
|
|
by the application and has no "next" block. */
|
|
pxBlock->xBlockSize |= xBlockAllocatedBit;
|
|
8010522: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8010524: 685a ldr r2, [r3, #4]
|
|
8010526: 4b13 ldr r3, [pc, #76] ; (8010574 <pvPortMalloc+0x188>)
|
|
8010528: 681b ldr r3, [r3, #0]
|
|
801052a: 431a orrs r2, r3
|
|
801052c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801052e: 605a str r2, [r3, #4]
|
|
pxBlock->pxNextFreeBlock = NULL;
|
|
8010530: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8010532: 2200 movs r2, #0
|
|
8010534: 601a str r2, [r3, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
traceMALLOC( pvReturn, xWantedSize );
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
8010536: f7fe ff0d bl 800f354 <xTaskResumeAll>
|
|
|
|
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
|
|
{
|
|
if( pvReturn == NULL )
|
|
801053a: 69fb ldr r3, [r7, #28]
|
|
801053c: 2b00 cmp r3, #0
|
|
801053e: d101 bne.n 8010544 <pvPortMalloc+0x158>
|
|
{
|
|
extern void vApplicationMallocFailedHook( void );
|
|
vApplicationMallocFailedHook();
|
|
8010540: f7f0 f848 bl 80005d4 <vApplicationMallocFailedHook>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
8010544: 69fb ldr r3, [r7, #28]
|
|
8010546: f003 0307 and.w r3, r3, #7
|
|
801054a: 2b00 cmp r3, #0
|
|
801054c: d00b beq.n 8010566 <pvPortMalloc+0x17a>
|
|
801054e: f04f 0350 mov.w r3, #80 ; 0x50
|
|
8010552: b672 cpsid i
|
|
8010554: f383 8811 msr BASEPRI, r3
|
|
8010558: f3bf 8f6f isb sy
|
|
801055c: f3bf 8f4f dsb sy
|
|
8010560: b662 cpsie i
|
|
8010562: 60fb str r3, [r7, #12]
|
|
8010564: e7fe b.n 8010564 <pvPortMalloc+0x178>
|
|
return pvReturn;
|
|
8010566: 69fb ldr r3, [r7, #28]
|
|
}
|
|
8010568: 4618 mov r0, r3
|
|
801056a: 3728 adds r7, #40 ; 0x28
|
|
801056c: 46bd mov sp, r7
|
|
801056e: bd80 pop {r7, pc}
|
|
8010570: 200086c8 .word 0x200086c8
|
|
8010574: 200086d4 .word 0x200086d4
|
|
8010578: 200086cc .word 0x200086cc
|
|
801057c: 200086c0 .word 0x200086c0
|
|
8010580: 200086d0 .word 0x200086d0
|
|
|
|
08010584 <vPortFree>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortFree( void *pv )
|
|
{
|
|
8010584: b580 push {r7, lr}
|
|
8010586: b086 sub sp, #24
|
|
8010588: af00 add r7, sp, #0
|
|
801058a: 6078 str r0, [r7, #4]
|
|
uint8_t *puc = ( uint8_t * ) pv;
|
|
801058c: 687b ldr r3, [r7, #4]
|
|
801058e: 617b str r3, [r7, #20]
|
|
BlockLink_t *pxLink;
|
|
|
|
if( pv != NULL )
|
|
8010590: 687b ldr r3, [r7, #4]
|
|
8010592: 2b00 cmp r3, #0
|
|
8010594: d04a beq.n 801062c <vPortFree+0xa8>
|
|
{
|
|
/* The memory being freed will have an BlockLink_t structure immediately
|
|
before it. */
|
|
puc -= xHeapStructSize;
|
|
8010596: 2308 movs r3, #8
|
|
8010598: 425b negs r3, r3
|
|
801059a: 697a ldr r2, [r7, #20]
|
|
801059c: 4413 add r3, r2
|
|
801059e: 617b str r3, [r7, #20]
|
|
|
|
/* This casting is to keep the compiler from issuing warnings. */
|
|
pxLink = ( void * ) puc;
|
|
80105a0: 697b ldr r3, [r7, #20]
|
|
80105a2: 613b str r3, [r7, #16]
|
|
|
|
/* Check the block is actually allocated. */
|
|
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
|
|
80105a4: 693b ldr r3, [r7, #16]
|
|
80105a6: 685a ldr r2, [r3, #4]
|
|
80105a8: 4b22 ldr r3, [pc, #136] ; (8010634 <vPortFree+0xb0>)
|
|
80105aa: 681b ldr r3, [r3, #0]
|
|
80105ac: 4013 ands r3, r2
|
|
80105ae: 2b00 cmp r3, #0
|
|
80105b0: d10b bne.n 80105ca <vPortFree+0x46>
|
|
80105b2: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80105b6: b672 cpsid i
|
|
80105b8: f383 8811 msr BASEPRI, r3
|
|
80105bc: f3bf 8f6f isb sy
|
|
80105c0: f3bf 8f4f dsb sy
|
|
80105c4: b662 cpsie i
|
|
80105c6: 60fb str r3, [r7, #12]
|
|
80105c8: e7fe b.n 80105c8 <vPortFree+0x44>
|
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
|
80105ca: 693b ldr r3, [r7, #16]
|
|
80105cc: 681b ldr r3, [r3, #0]
|
|
80105ce: 2b00 cmp r3, #0
|
|
80105d0: d00b beq.n 80105ea <vPortFree+0x66>
|
|
80105d2: f04f 0350 mov.w r3, #80 ; 0x50
|
|
80105d6: b672 cpsid i
|
|
80105d8: f383 8811 msr BASEPRI, r3
|
|
80105dc: f3bf 8f6f isb sy
|
|
80105e0: f3bf 8f4f dsb sy
|
|
80105e4: b662 cpsie i
|
|
80105e6: 60bb str r3, [r7, #8]
|
|
80105e8: e7fe b.n 80105e8 <vPortFree+0x64>
|
|
|
|
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
|
|
80105ea: 693b ldr r3, [r7, #16]
|
|
80105ec: 685a ldr r2, [r3, #4]
|
|
80105ee: 4b11 ldr r3, [pc, #68] ; (8010634 <vPortFree+0xb0>)
|
|
80105f0: 681b ldr r3, [r3, #0]
|
|
80105f2: 4013 ands r3, r2
|
|
80105f4: 2b00 cmp r3, #0
|
|
80105f6: d019 beq.n 801062c <vPortFree+0xa8>
|
|
{
|
|
if( pxLink->pxNextFreeBlock == NULL )
|
|
80105f8: 693b ldr r3, [r7, #16]
|
|
80105fa: 681b ldr r3, [r3, #0]
|
|
80105fc: 2b00 cmp r3, #0
|
|
80105fe: d115 bne.n 801062c <vPortFree+0xa8>
|
|
{
|
|
/* The block is being returned to the heap - it is no longer
|
|
allocated. */
|
|
pxLink->xBlockSize &= ~xBlockAllocatedBit;
|
|
8010600: 693b ldr r3, [r7, #16]
|
|
8010602: 685a ldr r2, [r3, #4]
|
|
8010604: 4b0b ldr r3, [pc, #44] ; (8010634 <vPortFree+0xb0>)
|
|
8010606: 681b ldr r3, [r3, #0]
|
|
8010608: 43db mvns r3, r3
|
|
801060a: 401a ands r2, r3
|
|
801060c: 693b ldr r3, [r7, #16]
|
|
801060e: 605a str r2, [r3, #4]
|
|
|
|
vTaskSuspendAll();
|
|
8010610: f7fe fe92 bl 800f338 <vTaskSuspendAll>
|
|
{
|
|
/* Add this block to the list of free blocks. */
|
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
|
8010614: 693b ldr r3, [r7, #16]
|
|
8010616: 685a ldr r2, [r3, #4]
|
|
8010618: 4b07 ldr r3, [pc, #28] ; (8010638 <vPortFree+0xb4>)
|
|
801061a: 681b ldr r3, [r3, #0]
|
|
801061c: 4413 add r3, r2
|
|
801061e: 4a06 ldr r2, [pc, #24] ; (8010638 <vPortFree+0xb4>)
|
|
8010620: 6013 str r3, [r2, #0]
|
|
traceFREE( pv, pxLink->xBlockSize );
|
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
|
8010622: 6938 ldr r0, [r7, #16]
|
|
8010624: f000 f86c bl 8010700 <prvInsertBlockIntoFreeList>
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
8010628: f7fe fe94 bl 800f354 <xTaskResumeAll>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
801062c: bf00 nop
|
|
801062e: 3718 adds r7, #24
|
|
8010630: 46bd mov sp, r7
|
|
8010632: bd80 pop {r7, pc}
|
|
8010634: 200086d4 .word 0x200086d4
|
|
8010638: 200086cc .word 0x200086cc
|
|
|
|
0801063c <prvHeapInit>:
|
|
/* This just exists to keep the linker quiet. */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvHeapInit( void )
|
|
{
|
|
801063c: b480 push {r7}
|
|
801063e: b085 sub sp, #20
|
|
8010640: af00 add r7, sp, #0
|
|
BlockLink_t *pxFirstFreeBlock;
|
|
uint8_t *pucAlignedHeap;
|
|
size_t uxAddress;
|
|
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
|
|
8010642: f44f 4300 mov.w r3, #32768 ; 0x8000
|
|
8010646: 60bb str r3, [r7, #8]
|
|
|
|
/* Ensure the heap starts on a correctly aligned boundary. */
|
|
uxAddress = ( size_t ) ucHeap;
|
|
8010648: 4b27 ldr r3, [pc, #156] ; (80106e8 <prvHeapInit+0xac>)
|
|
801064a: 60fb str r3, [r7, #12]
|
|
|
|
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
|
801064c: 68fb ldr r3, [r7, #12]
|
|
801064e: f003 0307 and.w r3, r3, #7
|
|
8010652: 2b00 cmp r3, #0
|
|
8010654: d00c beq.n 8010670 <prvHeapInit+0x34>
|
|
{
|
|
uxAddress += ( portBYTE_ALIGNMENT - 1 );
|
|
8010656: 68fb ldr r3, [r7, #12]
|
|
8010658: 3307 adds r3, #7
|
|
801065a: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
801065c: 68fb ldr r3, [r7, #12]
|
|
801065e: f023 0307 bic.w r3, r3, #7
|
|
8010662: 60fb str r3, [r7, #12]
|
|
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
|
|
8010664: 68ba ldr r2, [r7, #8]
|
|
8010666: 68fb ldr r3, [r7, #12]
|
|
8010668: 1ad3 subs r3, r2, r3
|
|
801066a: 4a1f ldr r2, [pc, #124] ; (80106e8 <prvHeapInit+0xac>)
|
|
801066c: 4413 add r3, r2
|
|
801066e: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
pucAlignedHeap = ( uint8_t * ) uxAddress;
|
|
8010670: 68fb ldr r3, [r7, #12]
|
|
8010672: 607b str r3, [r7, #4]
|
|
|
|
/* xStart is used to hold a pointer to the first item in the list of free
|
|
blocks. The void cast is used to prevent compiler warnings. */
|
|
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
|
|
8010674: 4a1d ldr r2, [pc, #116] ; (80106ec <prvHeapInit+0xb0>)
|
|
8010676: 687b ldr r3, [r7, #4]
|
|
8010678: 6013 str r3, [r2, #0]
|
|
xStart.xBlockSize = ( size_t ) 0;
|
|
801067a: 4b1c ldr r3, [pc, #112] ; (80106ec <prvHeapInit+0xb0>)
|
|
801067c: 2200 movs r2, #0
|
|
801067e: 605a str r2, [r3, #4]
|
|
|
|
/* pxEnd is used to mark the end of the list of free blocks and is inserted
|
|
at the end of the heap space. */
|
|
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
|
|
8010680: 687b ldr r3, [r7, #4]
|
|
8010682: 68ba ldr r2, [r7, #8]
|
|
8010684: 4413 add r3, r2
|
|
8010686: 60fb str r3, [r7, #12]
|
|
uxAddress -= xHeapStructSize;
|
|
8010688: 2208 movs r2, #8
|
|
801068a: 68fb ldr r3, [r7, #12]
|
|
801068c: 1a9b subs r3, r3, r2
|
|
801068e: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
8010690: 68fb ldr r3, [r7, #12]
|
|
8010692: f023 0307 bic.w r3, r3, #7
|
|
8010696: 60fb str r3, [r7, #12]
|
|
pxEnd = ( void * ) uxAddress;
|
|
8010698: 68fb ldr r3, [r7, #12]
|
|
801069a: 4a15 ldr r2, [pc, #84] ; (80106f0 <prvHeapInit+0xb4>)
|
|
801069c: 6013 str r3, [r2, #0]
|
|
pxEnd->xBlockSize = 0;
|
|
801069e: 4b14 ldr r3, [pc, #80] ; (80106f0 <prvHeapInit+0xb4>)
|
|
80106a0: 681b ldr r3, [r3, #0]
|
|
80106a2: 2200 movs r2, #0
|
|
80106a4: 605a str r2, [r3, #4]
|
|
pxEnd->pxNextFreeBlock = NULL;
|
|
80106a6: 4b12 ldr r3, [pc, #72] ; (80106f0 <prvHeapInit+0xb4>)
|
|
80106a8: 681b ldr r3, [r3, #0]
|
|
80106aa: 2200 movs r2, #0
|
|
80106ac: 601a str r2, [r3, #0]
|
|
|
|
/* To start with there is a single free block that is sized to take up the
|
|
entire heap space, minus the space taken by pxEnd. */
|
|
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
|
|
80106ae: 687b ldr r3, [r7, #4]
|
|
80106b0: 603b str r3, [r7, #0]
|
|
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
|
|
80106b2: 683b ldr r3, [r7, #0]
|
|
80106b4: 68fa ldr r2, [r7, #12]
|
|
80106b6: 1ad2 subs r2, r2, r3
|
|
80106b8: 683b ldr r3, [r7, #0]
|
|
80106ba: 605a str r2, [r3, #4]
|
|
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
|
|
80106bc: 4b0c ldr r3, [pc, #48] ; (80106f0 <prvHeapInit+0xb4>)
|
|
80106be: 681a ldr r2, [r3, #0]
|
|
80106c0: 683b ldr r3, [r7, #0]
|
|
80106c2: 601a str r2, [r3, #0]
|
|
|
|
/* Only one block exists - and it covers the entire usable heap space. */
|
|
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
80106c4: 683b ldr r3, [r7, #0]
|
|
80106c6: 685b ldr r3, [r3, #4]
|
|
80106c8: 4a0a ldr r2, [pc, #40] ; (80106f4 <prvHeapInit+0xb8>)
|
|
80106ca: 6013 str r3, [r2, #0]
|
|
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
80106cc: 683b ldr r3, [r7, #0]
|
|
80106ce: 685b ldr r3, [r3, #4]
|
|
80106d0: 4a09 ldr r2, [pc, #36] ; (80106f8 <prvHeapInit+0xbc>)
|
|
80106d2: 6013 str r3, [r2, #0]
|
|
|
|
/* Work out the position of the top bit in a size_t variable. */
|
|
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
|
|
80106d4: 4b09 ldr r3, [pc, #36] ; (80106fc <prvHeapInit+0xc0>)
|
|
80106d6: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
|
|
80106da: 601a str r2, [r3, #0]
|
|
}
|
|
80106dc: bf00 nop
|
|
80106de: 3714 adds r7, #20
|
|
80106e0: 46bd mov sp, r7
|
|
80106e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80106e6: 4770 bx lr
|
|
80106e8: 200006c0 .word 0x200006c0
|
|
80106ec: 200086c0 .word 0x200086c0
|
|
80106f0: 200086c8 .word 0x200086c8
|
|
80106f4: 200086d0 .word 0x200086d0
|
|
80106f8: 200086cc .word 0x200086cc
|
|
80106fc: 200086d4 .word 0x200086d4
|
|
|
|
08010700 <prvInsertBlockIntoFreeList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
|
|
{
|
|
8010700: b480 push {r7}
|
|
8010702: b085 sub sp, #20
|
|
8010704: af00 add r7, sp, #0
|
|
8010706: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxIterator;
|
|
uint8_t *puc;
|
|
|
|
/* Iterate through the list until a block is found that has a higher address
|
|
than the block being inserted. */
|
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
|
8010708: 4b28 ldr r3, [pc, #160] ; (80107ac <prvInsertBlockIntoFreeList+0xac>)
|
|
801070a: 60fb str r3, [r7, #12]
|
|
801070c: e002 b.n 8010714 <prvInsertBlockIntoFreeList+0x14>
|
|
801070e: 68fb ldr r3, [r7, #12]
|
|
8010710: 681b ldr r3, [r3, #0]
|
|
8010712: 60fb str r3, [r7, #12]
|
|
8010714: 68fb ldr r3, [r7, #12]
|
|
8010716: 681b ldr r3, [r3, #0]
|
|
8010718: 687a ldr r2, [r7, #4]
|
|
801071a: 429a cmp r2, r3
|
|
801071c: d8f7 bhi.n 801070e <prvInsertBlockIntoFreeList+0xe>
|
|
/* Nothing to do here, just iterate to the right position. */
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted after
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxIterator;
|
|
801071e: 68fb ldr r3, [r7, #12]
|
|
8010720: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
|
8010722: 68fb ldr r3, [r7, #12]
|
|
8010724: 685b ldr r3, [r3, #4]
|
|
8010726: 68ba ldr r2, [r7, #8]
|
|
8010728: 4413 add r3, r2
|
|
801072a: 687a ldr r2, [r7, #4]
|
|
801072c: 429a cmp r2, r3
|
|
801072e: d108 bne.n 8010742 <prvInsertBlockIntoFreeList+0x42>
|
|
{
|
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
|
8010730: 68fb ldr r3, [r7, #12]
|
|
8010732: 685a ldr r2, [r3, #4]
|
|
8010734: 687b ldr r3, [r7, #4]
|
|
8010736: 685b ldr r3, [r3, #4]
|
|
8010738: 441a add r2, r3
|
|
801073a: 68fb ldr r3, [r7, #12]
|
|
801073c: 605a str r2, [r3, #4]
|
|
pxBlockToInsert = pxIterator;
|
|
801073e: 68fb ldr r3, [r7, #12]
|
|
8010740: 607b str r3, [r7, #4]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted before
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxBlockToInsert;
|
|
8010742: 687b ldr r3, [r7, #4]
|
|
8010744: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
|
8010746: 687b ldr r3, [r7, #4]
|
|
8010748: 685b ldr r3, [r3, #4]
|
|
801074a: 68ba ldr r2, [r7, #8]
|
|
801074c: 441a add r2, r3
|
|
801074e: 68fb ldr r3, [r7, #12]
|
|
8010750: 681b ldr r3, [r3, #0]
|
|
8010752: 429a cmp r2, r3
|
|
8010754: d118 bne.n 8010788 <prvInsertBlockIntoFreeList+0x88>
|
|
{
|
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
|
8010756: 68fb ldr r3, [r7, #12]
|
|
8010758: 681a ldr r2, [r3, #0]
|
|
801075a: 4b15 ldr r3, [pc, #84] ; (80107b0 <prvInsertBlockIntoFreeList+0xb0>)
|
|
801075c: 681b ldr r3, [r3, #0]
|
|
801075e: 429a cmp r2, r3
|
|
8010760: d00d beq.n 801077e <prvInsertBlockIntoFreeList+0x7e>
|
|
{
|
|
/* Form one big block from the two blocks. */
|
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
|
8010762: 687b ldr r3, [r7, #4]
|
|
8010764: 685a ldr r2, [r3, #4]
|
|
8010766: 68fb ldr r3, [r7, #12]
|
|
8010768: 681b ldr r3, [r3, #0]
|
|
801076a: 685b ldr r3, [r3, #4]
|
|
801076c: 441a add r2, r3
|
|
801076e: 687b ldr r3, [r7, #4]
|
|
8010770: 605a str r2, [r3, #4]
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
|
8010772: 68fb ldr r3, [r7, #12]
|
|
8010774: 681b ldr r3, [r3, #0]
|
|
8010776: 681a ldr r2, [r3, #0]
|
|
8010778: 687b ldr r3, [r7, #4]
|
|
801077a: 601a str r2, [r3, #0]
|
|
801077c: e008 b.n 8010790 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
|
801077e: 4b0c ldr r3, [pc, #48] ; (80107b0 <prvInsertBlockIntoFreeList+0xb0>)
|
|
8010780: 681a ldr r2, [r3, #0]
|
|
8010782: 687b ldr r3, [r7, #4]
|
|
8010784: 601a str r2, [r3, #0]
|
|
8010786: e003 b.n 8010790 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
|
8010788: 68fb ldr r3, [r7, #12]
|
|
801078a: 681a ldr r2, [r3, #0]
|
|
801078c: 687b ldr r3, [r7, #4]
|
|
801078e: 601a str r2, [r3, #0]
|
|
|
|
/* If the block being inserted plugged a gab, so was merged with the block
|
|
before and the block after, then it's pxNextFreeBlock pointer will have
|
|
already been set, and should not be set here as that would make it point
|
|
to itself. */
|
|
if( pxIterator != pxBlockToInsert )
|
|
8010790: 68fa ldr r2, [r7, #12]
|
|
8010792: 687b ldr r3, [r7, #4]
|
|
8010794: 429a cmp r2, r3
|
|
8010796: d002 beq.n 801079e <prvInsertBlockIntoFreeList+0x9e>
|
|
{
|
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
|
8010798: 68fb ldr r3, [r7, #12]
|
|
801079a: 687a ldr r2, [r7, #4]
|
|
801079c: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
801079e: bf00 nop
|
|
80107a0: 3714 adds r7, #20
|
|
80107a2: 46bd mov sp, r7
|
|
80107a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80107a8: 4770 bx lr
|
|
80107aa: bf00 nop
|
|
80107ac: 200086c0 .word 0x200086c0
|
|
80107b0: 200086c8 .word 0x200086c8
|
|
|
|
080107b4 <tcpip_timeouts_mbox_fetch>:
|
|
* @param mbox the mbox to fetch the message from
|
|
* @param msg the place to store the message
|
|
*/
|
|
static void
|
|
tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg)
|
|
{
|
|
80107b4: b580 push {r7, lr}
|
|
80107b6: b084 sub sp, #16
|
|
80107b8: af00 add r7, sp, #0
|
|
80107ba: 6078 str r0, [r7, #4]
|
|
80107bc: 6039 str r1, [r7, #0]
|
|
u32_t sleeptime, res;
|
|
|
|
again:
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
sleeptime = sys_timeouts_sleeptime();
|
|
80107be: f007 fa91 bl 8017ce4 <sys_timeouts_sleeptime>
|
|
80107c2: 60f8 str r0, [r7, #12]
|
|
if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) {
|
|
80107c4: 68fb ldr r3, [r7, #12]
|
|
80107c6: f1b3 3fff cmp.w r3, #4294967295
|
|
80107ca: d10b bne.n 80107e4 <tcpip_timeouts_mbox_fetch+0x30>
|
|
UNLOCK_TCPIP_CORE();
|
|
80107cc: 4813 ldr r0, [pc, #76] ; (801081c <tcpip_timeouts_mbox_fetch+0x68>)
|
|
80107ce: f00c f9c2 bl 801cb56 <sys_mutex_unlock>
|
|
sys_arch_mbox_fetch(mbox, msg, 0);
|
|
80107d2: 2200 movs r2, #0
|
|
80107d4: 6839 ldr r1, [r7, #0]
|
|
80107d6: 6878 ldr r0, [r7, #4]
|
|
80107d8: f00c f934 bl 801ca44 <sys_arch_mbox_fetch>
|
|
LOCK_TCPIP_CORE();
|
|
80107dc: 480f ldr r0, [pc, #60] ; (801081c <tcpip_timeouts_mbox_fetch+0x68>)
|
|
80107de: f00c f9ab bl 801cb38 <sys_mutex_lock>
|
|
return;
|
|
80107e2: e018 b.n 8010816 <tcpip_timeouts_mbox_fetch+0x62>
|
|
} else if (sleeptime == 0) {
|
|
80107e4: 68fb ldr r3, [r7, #12]
|
|
80107e6: 2b00 cmp r3, #0
|
|
80107e8: d102 bne.n 80107f0 <tcpip_timeouts_mbox_fetch+0x3c>
|
|
sys_check_timeouts();
|
|
80107ea: f007 fa41 bl 8017c70 <sys_check_timeouts>
|
|
/* We try again to fetch a message from the mbox. */
|
|
goto again;
|
|
80107ee: e7e6 b.n 80107be <tcpip_timeouts_mbox_fetch+0xa>
|
|
}
|
|
|
|
UNLOCK_TCPIP_CORE();
|
|
80107f0: 480a ldr r0, [pc, #40] ; (801081c <tcpip_timeouts_mbox_fetch+0x68>)
|
|
80107f2: f00c f9b0 bl 801cb56 <sys_mutex_unlock>
|
|
res = sys_arch_mbox_fetch(mbox, msg, sleeptime);
|
|
80107f6: 68fa ldr r2, [r7, #12]
|
|
80107f8: 6839 ldr r1, [r7, #0]
|
|
80107fa: 6878 ldr r0, [r7, #4]
|
|
80107fc: f00c f922 bl 801ca44 <sys_arch_mbox_fetch>
|
|
8010800: 60b8 str r0, [r7, #8]
|
|
LOCK_TCPIP_CORE();
|
|
8010802: 4806 ldr r0, [pc, #24] ; (801081c <tcpip_timeouts_mbox_fetch+0x68>)
|
|
8010804: f00c f998 bl 801cb38 <sys_mutex_lock>
|
|
if (res == SYS_ARCH_TIMEOUT) {
|
|
8010808: 68bb ldr r3, [r7, #8]
|
|
801080a: f1b3 3fff cmp.w r3, #4294967295
|
|
801080e: d102 bne.n 8010816 <tcpip_timeouts_mbox_fetch+0x62>
|
|
/* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred
|
|
before a message could be fetched. */
|
|
sys_check_timeouts();
|
|
8010810: f007 fa2e bl 8017c70 <sys_check_timeouts>
|
|
/* We try again to fetch a message from the mbox. */
|
|
goto again;
|
|
8010814: e7d3 b.n 80107be <tcpip_timeouts_mbox_fetch+0xa>
|
|
}
|
|
}
|
|
8010816: 3710 adds r7, #16
|
|
8010818: 46bd mov sp, r7
|
|
801081a: bd80 pop {r7, pc}
|
|
801081c: 2000c0c4 .word 0x2000c0c4
|
|
|
|
08010820 <tcpip_thread>:
|
|
*
|
|
* @param arg unused argument
|
|
*/
|
|
static void
|
|
tcpip_thread(void *arg)
|
|
{
|
|
8010820: b580 push {r7, lr}
|
|
8010822: b084 sub sp, #16
|
|
8010824: af00 add r7, sp, #0
|
|
8010826: 6078 str r0, [r7, #4]
|
|
struct tcpip_msg *msg;
|
|
LWIP_UNUSED_ARG(arg);
|
|
|
|
LWIP_MARK_TCPIP_THREAD();
|
|
|
|
LOCK_TCPIP_CORE();
|
|
8010828: 4810 ldr r0, [pc, #64] ; (801086c <tcpip_thread+0x4c>)
|
|
801082a: f00c f985 bl 801cb38 <sys_mutex_lock>
|
|
if (tcpip_init_done != NULL) {
|
|
801082e: 4b10 ldr r3, [pc, #64] ; (8010870 <tcpip_thread+0x50>)
|
|
8010830: 681b ldr r3, [r3, #0]
|
|
8010832: 2b00 cmp r3, #0
|
|
8010834: d005 beq.n 8010842 <tcpip_thread+0x22>
|
|
tcpip_init_done(tcpip_init_done_arg);
|
|
8010836: 4b0e ldr r3, [pc, #56] ; (8010870 <tcpip_thread+0x50>)
|
|
8010838: 681b ldr r3, [r3, #0]
|
|
801083a: 4a0e ldr r2, [pc, #56] ; (8010874 <tcpip_thread+0x54>)
|
|
801083c: 6812 ldr r2, [r2, #0]
|
|
801083e: 4610 mov r0, r2
|
|
8010840: 4798 blx r3
|
|
}
|
|
|
|
while (1) { /* MAIN Loop */
|
|
LWIP_TCPIP_THREAD_ALIVE();
|
|
/* wait for a message, timeouts are processed while waiting */
|
|
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
|
|
8010842: f107 030c add.w r3, r7, #12
|
|
8010846: 4619 mov r1, r3
|
|
8010848: 480b ldr r0, [pc, #44] ; (8010878 <tcpip_thread+0x58>)
|
|
801084a: f7ff ffb3 bl 80107b4 <tcpip_timeouts_mbox_fetch>
|
|
if (msg == NULL) {
|
|
801084e: 68fb ldr r3, [r7, #12]
|
|
8010850: 2b00 cmp r3, #0
|
|
8010852: d106 bne.n 8010862 <tcpip_thread+0x42>
|
|
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n"));
|
|
LWIP_ASSERT("tcpip_thread: invalid message", 0);
|
|
8010854: 4b09 ldr r3, [pc, #36] ; (801087c <tcpip_thread+0x5c>)
|
|
8010856: 2291 movs r2, #145 ; 0x91
|
|
8010858: 4909 ldr r1, [pc, #36] ; (8010880 <tcpip_thread+0x60>)
|
|
801085a: 480a ldr r0, [pc, #40] ; (8010884 <tcpip_thread+0x64>)
|
|
801085c: f00c fa2c bl 801ccb8 <iprintf>
|
|
continue;
|
|
8010860: e003 b.n 801086a <tcpip_thread+0x4a>
|
|
}
|
|
tcpip_thread_handle_msg(msg);
|
|
8010862: 68fb ldr r3, [r7, #12]
|
|
8010864: 4618 mov r0, r3
|
|
8010866: f000 f80f bl 8010888 <tcpip_thread_handle_msg>
|
|
TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg);
|
|
801086a: e7ea b.n 8010842 <tcpip_thread+0x22>
|
|
801086c: 2000c0c4 .word 0x2000c0c4
|
|
8010870: 200086d8 .word 0x200086d8
|
|
8010874: 200086dc .word 0x200086dc
|
|
8010878: 200086e0 .word 0x200086e0
|
|
801087c: 0801dfd4 .word 0x0801dfd4
|
|
8010880: 0801e004 .word 0x0801e004
|
|
8010884: 0801e024 .word 0x0801e024
|
|
|
|
08010888 <tcpip_thread_handle_msg>:
|
|
/* Handle a single tcpip_msg
|
|
* This is in its own function for access by tests only.
|
|
*/
|
|
static void
|
|
tcpip_thread_handle_msg(struct tcpip_msg *msg)
|
|
{
|
|
8010888: b580 push {r7, lr}
|
|
801088a: b082 sub sp, #8
|
|
801088c: af00 add r7, sp, #0
|
|
801088e: 6078 str r0, [r7, #4]
|
|
switch (msg->type) {
|
|
8010890: 687b ldr r3, [r7, #4]
|
|
8010892: 781b ldrb r3, [r3, #0]
|
|
8010894: 2b01 cmp r3, #1
|
|
8010896: d018 beq.n 80108ca <tcpip_thread_handle_msg+0x42>
|
|
8010898: 2b02 cmp r3, #2
|
|
801089a: d021 beq.n 80108e0 <tcpip_thread_handle_msg+0x58>
|
|
801089c: 2b00 cmp r3, #0
|
|
801089e: d126 bne.n 80108ee <tcpip_thread_handle_msg+0x66>
|
|
#endif /* !LWIP_TCPIP_CORE_LOCKING */
|
|
|
|
#if !LWIP_TCPIP_CORE_LOCKING_INPUT
|
|
case TCPIP_MSG_INPKT:
|
|
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg));
|
|
if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) {
|
|
80108a0: 687b ldr r3, [r7, #4]
|
|
80108a2: 68db ldr r3, [r3, #12]
|
|
80108a4: 687a ldr r2, [r7, #4]
|
|
80108a6: 6850 ldr r0, [r2, #4]
|
|
80108a8: 687a ldr r2, [r7, #4]
|
|
80108aa: 6892 ldr r2, [r2, #8]
|
|
80108ac: 4611 mov r1, r2
|
|
80108ae: 4798 blx r3
|
|
80108b0: 4603 mov r3, r0
|
|
80108b2: 2b00 cmp r3, #0
|
|
80108b4: d004 beq.n 80108c0 <tcpip_thread_handle_msg+0x38>
|
|
pbuf_free(msg->msg.inp.p);
|
|
80108b6: 687b ldr r3, [r7, #4]
|
|
80108b8: 685b ldr r3, [r3, #4]
|
|
80108ba: 4618 mov r0, r3
|
|
80108bc: f001 fccc bl 8012258 <pbuf_free>
|
|
}
|
|
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
|
|
80108c0: 6879 ldr r1, [r7, #4]
|
|
80108c2: 2009 movs r0, #9
|
|
80108c4: f000 fe1c bl 8011500 <memp_free>
|
|
break;
|
|
80108c8: e018 b.n 80108fc <tcpip_thread_handle_msg+0x74>
|
|
break;
|
|
#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */
|
|
|
|
case TCPIP_MSG_CALLBACK:
|
|
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg));
|
|
msg->msg.cb.function(msg->msg.cb.ctx);
|
|
80108ca: 687b ldr r3, [r7, #4]
|
|
80108cc: 685b ldr r3, [r3, #4]
|
|
80108ce: 687a ldr r2, [r7, #4]
|
|
80108d0: 6892 ldr r2, [r2, #8]
|
|
80108d2: 4610 mov r0, r2
|
|
80108d4: 4798 blx r3
|
|
memp_free(MEMP_TCPIP_MSG_API, msg);
|
|
80108d6: 6879 ldr r1, [r7, #4]
|
|
80108d8: 2008 movs r0, #8
|
|
80108da: f000 fe11 bl 8011500 <memp_free>
|
|
break;
|
|
80108de: e00d b.n 80108fc <tcpip_thread_handle_msg+0x74>
|
|
|
|
case TCPIP_MSG_CALLBACK_STATIC:
|
|
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg));
|
|
msg->msg.cb.function(msg->msg.cb.ctx);
|
|
80108e0: 687b ldr r3, [r7, #4]
|
|
80108e2: 685b ldr r3, [r3, #4]
|
|
80108e4: 687a ldr r2, [r7, #4]
|
|
80108e6: 6892 ldr r2, [r2, #8]
|
|
80108e8: 4610 mov r0, r2
|
|
80108ea: 4798 blx r3
|
|
break;
|
|
80108ec: e006 b.n 80108fc <tcpip_thread_handle_msg+0x74>
|
|
|
|
default:
|
|
LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type));
|
|
LWIP_ASSERT("tcpip_thread: invalid message", 0);
|
|
80108ee: 4b05 ldr r3, [pc, #20] ; (8010904 <tcpip_thread_handle_msg+0x7c>)
|
|
80108f0: 22cf movs r2, #207 ; 0xcf
|
|
80108f2: 4905 ldr r1, [pc, #20] ; (8010908 <tcpip_thread_handle_msg+0x80>)
|
|
80108f4: 4805 ldr r0, [pc, #20] ; (801090c <tcpip_thread_handle_msg+0x84>)
|
|
80108f6: f00c f9df bl 801ccb8 <iprintf>
|
|
break;
|
|
80108fa: bf00 nop
|
|
}
|
|
}
|
|
80108fc: bf00 nop
|
|
80108fe: 3708 adds r7, #8
|
|
8010900: 46bd mov sp, r7
|
|
8010902: bd80 pop {r7, pc}
|
|
8010904: 0801dfd4 .word 0x0801dfd4
|
|
8010908: 0801e004 .word 0x0801e004
|
|
801090c: 0801e024 .word 0x0801e024
|
|
|
|
08010910 <tcpip_inpkt>:
|
|
* @param inp the network interface on which the packet was received
|
|
* @param input_fn input function to call
|
|
*/
|
|
err_t
|
|
tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn)
|
|
{
|
|
8010910: b580 push {r7, lr}
|
|
8010912: b086 sub sp, #24
|
|
8010914: af00 add r7, sp, #0
|
|
8010916: 60f8 str r0, [r7, #12]
|
|
8010918: 60b9 str r1, [r7, #8]
|
|
801091a: 607a str r2, [r7, #4]
|
|
UNLOCK_TCPIP_CORE();
|
|
return ret;
|
|
#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */
|
|
struct tcpip_msg *msg;
|
|
|
|
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
|
|
801091c: 481a ldr r0, [pc, #104] ; (8010988 <tcpip_inpkt+0x78>)
|
|
801091e: f00c f8d0 bl 801cac2 <sys_mbox_valid>
|
|
8010922: 4603 mov r3, r0
|
|
8010924: 2b00 cmp r3, #0
|
|
8010926: d105 bne.n 8010934 <tcpip_inpkt+0x24>
|
|
8010928: 4b18 ldr r3, [pc, #96] ; (801098c <tcpip_inpkt+0x7c>)
|
|
801092a: 22fc movs r2, #252 ; 0xfc
|
|
801092c: 4918 ldr r1, [pc, #96] ; (8010990 <tcpip_inpkt+0x80>)
|
|
801092e: 4819 ldr r0, [pc, #100] ; (8010994 <tcpip_inpkt+0x84>)
|
|
8010930: f00c f9c2 bl 801ccb8 <iprintf>
|
|
|
|
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT);
|
|
8010934: 2009 movs r0, #9
|
|
8010936: f000 fd91 bl 801145c <memp_malloc>
|
|
801093a: 6178 str r0, [r7, #20]
|
|
if (msg == NULL) {
|
|
801093c: 697b ldr r3, [r7, #20]
|
|
801093e: 2b00 cmp r3, #0
|
|
8010940: d102 bne.n 8010948 <tcpip_inpkt+0x38>
|
|
return ERR_MEM;
|
|
8010942: f04f 33ff mov.w r3, #4294967295
|
|
8010946: e01a b.n 801097e <tcpip_inpkt+0x6e>
|
|
}
|
|
|
|
msg->type = TCPIP_MSG_INPKT;
|
|
8010948: 697b ldr r3, [r7, #20]
|
|
801094a: 2200 movs r2, #0
|
|
801094c: 701a strb r2, [r3, #0]
|
|
msg->msg.inp.p = p;
|
|
801094e: 697b ldr r3, [r7, #20]
|
|
8010950: 68fa ldr r2, [r7, #12]
|
|
8010952: 605a str r2, [r3, #4]
|
|
msg->msg.inp.netif = inp;
|
|
8010954: 697b ldr r3, [r7, #20]
|
|
8010956: 68ba ldr r2, [r7, #8]
|
|
8010958: 609a str r2, [r3, #8]
|
|
msg->msg.inp.input_fn = input_fn;
|
|
801095a: 697b ldr r3, [r7, #20]
|
|
801095c: 687a ldr r2, [r7, #4]
|
|
801095e: 60da str r2, [r3, #12]
|
|
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
|
|
8010960: 6979 ldr r1, [r7, #20]
|
|
8010962: 4809 ldr r0, [pc, #36] ; (8010988 <tcpip_inpkt+0x78>)
|
|
8010964: f00c f854 bl 801ca10 <sys_mbox_trypost>
|
|
8010968: 4603 mov r3, r0
|
|
801096a: 2b00 cmp r3, #0
|
|
801096c: d006 beq.n 801097c <tcpip_inpkt+0x6c>
|
|
memp_free(MEMP_TCPIP_MSG_INPKT, msg);
|
|
801096e: 6979 ldr r1, [r7, #20]
|
|
8010970: 2009 movs r0, #9
|
|
8010972: f000 fdc5 bl 8011500 <memp_free>
|
|
return ERR_MEM;
|
|
8010976: f04f 33ff mov.w r3, #4294967295
|
|
801097a: e000 b.n 801097e <tcpip_inpkt+0x6e>
|
|
}
|
|
return ERR_OK;
|
|
801097c: 2300 movs r3, #0
|
|
#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */
|
|
}
|
|
801097e: 4618 mov r0, r3
|
|
8010980: 3718 adds r7, #24
|
|
8010982: 46bd mov sp, r7
|
|
8010984: bd80 pop {r7, pc}
|
|
8010986: bf00 nop
|
|
8010988: 200086e0 .word 0x200086e0
|
|
801098c: 0801dfd4 .word 0x0801dfd4
|
|
8010990: 0801e04c .word 0x0801e04c
|
|
8010994: 0801e024 .word 0x0801e024
|
|
|
|
08010998 <tcpip_input>:
|
|
* NETIF_FLAG_ETHERNET flags)
|
|
* @param inp the network interface on which the packet was received
|
|
*/
|
|
err_t
|
|
tcpip_input(struct pbuf *p, struct netif *inp)
|
|
{
|
|
8010998: b580 push {r7, lr}
|
|
801099a: b082 sub sp, #8
|
|
801099c: af00 add r7, sp, #0
|
|
801099e: 6078 str r0, [r7, #4]
|
|
80109a0: 6039 str r1, [r7, #0]
|
|
#if LWIP_ETHERNET
|
|
if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) {
|
|
80109a2: 683b ldr r3, [r7, #0]
|
|
80109a4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
80109a8: f003 0318 and.w r3, r3, #24
|
|
80109ac: 2b00 cmp r3, #0
|
|
80109ae: d006 beq.n 80109be <tcpip_input+0x26>
|
|
return tcpip_inpkt(p, inp, ethernet_input);
|
|
80109b0: 4a08 ldr r2, [pc, #32] ; (80109d4 <tcpip_input+0x3c>)
|
|
80109b2: 6839 ldr r1, [r7, #0]
|
|
80109b4: 6878 ldr r0, [r7, #4]
|
|
80109b6: f7ff ffab bl 8010910 <tcpip_inpkt>
|
|
80109ba: 4603 mov r3, r0
|
|
80109bc: e005 b.n 80109ca <tcpip_input+0x32>
|
|
} else
|
|
#endif /* LWIP_ETHERNET */
|
|
return tcpip_inpkt(p, inp, ip_input);
|
|
80109be: 4a06 ldr r2, [pc, #24] ; (80109d8 <tcpip_input+0x40>)
|
|
80109c0: 6839 ldr r1, [r7, #0]
|
|
80109c2: 6878 ldr r0, [r7, #4]
|
|
80109c4: f7ff ffa4 bl 8010910 <tcpip_inpkt>
|
|
80109c8: 4603 mov r3, r0
|
|
}
|
|
80109ca: 4618 mov r0, r3
|
|
80109cc: 3708 adds r7, #8
|
|
80109ce: 46bd mov sp, r7
|
|
80109d0: bd80 pop {r7, pc}
|
|
80109d2: bf00 nop
|
|
80109d4: 0801c821 .word 0x0801c821
|
|
80109d8: 0801b705 .word 0x0801b705
|
|
|
|
080109dc <tcpip_try_callback>:
|
|
*
|
|
* @see tcpip_callback
|
|
*/
|
|
err_t
|
|
tcpip_try_callback(tcpip_callback_fn function, void *ctx)
|
|
{
|
|
80109dc: b580 push {r7, lr}
|
|
80109de: b084 sub sp, #16
|
|
80109e0: af00 add r7, sp, #0
|
|
80109e2: 6078 str r0, [r7, #4]
|
|
80109e4: 6039 str r1, [r7, #0]
|
|
struct tcpip_msg *msg;
|
|
|
|
LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox));
|
|
80109e6: 4819 ldr r0, [pc, #100] ; (8010a4c <tcpip_try_callback+0x70>)
|
|
80109e8: f00c f86b bl 801cac2 <sys_mbox_valid>
|
|
80109ec: 4603 mov r3, r0
|
|
80109ee: 2b00 cmp r3, #0
|
|
80109f0: d106 bne.n 8010a00 <tcpip_try_callback+0x24>
|
|
80109f2: 4b17 ldr r3, [pc, #92] ; (8010a50 <tcpip_try_callback+0x74>)
|
|
80109f4: f240 125d movw r2, #349 ; 0x15d
|
|
80109f8: 4916 ldr r1, [pc, #88] ; (8010a54 <tcpip_try_callback+0x78>)
|
|
80109fa: 4817 ldr r0, [pc, #92] ; (8010a58 <tcpip_try_callback+0x7c>)
|
|
80109fc: f00c f95c bl 801ccb8 <iprintf>
|
|
|
|
msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API);
|
|
8010a00: 2008 movs r0, #8
|
|
8010a02: f000 fd2b bl 801145c <memp_malloc>
|
|
8010a06: 60f8 str r0, [r7, #12]
|
|
if (msg == NULL) {
|
|
8010a08: 68fb ldr r3, [r7, #12]
|
|
8010a0a: 2b00 cmp r3, #0
|
|
8010a0c: d102 bne.n 8010a14 <tcpip_try_callback+0x38>
|
|
return ERR_MEM;
|
|
8010a0e: f04f 33ff mov.w r3, #4294967295
|
|
8010a12: e017 b.n 8010a44 <tcpip_try_callback+0x68>
|
|
}
|
|
|
|
msg->type = TCPIP_MSG_CALLBACK;
|
|
8010a14: 68fb ldr r3, [r7, #12]
|
|
8010a16: 2201 movs r2, #1
|
|
8010a18: 701a strb r2, [r3, #0]
|
|
msg->msg.cb.function = function;
|
|
8010a1a: 68fb ldr r3, [r7, #12]
|
|
8010a1c: 687a ldr r2, [r7, #4]
|
|
8010a1e: 605a str r2, [r3, #4]
|
|
msg->msg.cb.ctx = ctx;
|
|
8010a20: 68fb ldr r3, [r7, #12]
|
|
8010a22: 683a ldr r2, [r7, #0]
|
|
8010a24: 609a str r2, [r3, #8]
|
|
|
|
if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) {
|
|
8010a26: 68f9 ldr r1, [r7, #12]
|
|
8010a28: 4808 ldr r0, [pc, #32] ; (8010a4c <tcpip_try_callback+0x70>)
|
|
8010a2a: f00b fff1 bl 801ca10 <sys_mbox_trypost>
|
|
8010a2e: 4603 mov r3, r0
|
|
8010a30: 2b00 cmp r3, #0
|
|
8010a32: d006 beq.n 8010a42 <tcpip_try_callback+0x66>
|
|
memp_free(MEMP_TCPIP_MSG_API, msg);
|
|
8010a34: 68f9 ldr r1, [r7, #12]
|
|
8010a36: 2008 movs r0, #8
|
|
8010a38: f000 fd62 bl 8011500 <memp_free>
|
|
return ERR_MEM;
|
|
8010a3c: f04f 33ff mov.w r3, #4294967295
|
|
8010a40: e000 b.n 8010a44 <tcpip_try_callback+0x68>
|
|
}
|
|
return ERR_OK;
|
|
8010a42: 2300 movs r3, #0
|
|
}
|
|
8010a44: 4618 mov r0, r3
|
|
8010a46: 3710 adds r7, #16
|
|
8010a48: 46bd mov sp, r7
|
|
8010a4a: bd80 pop {r7, pc}
|
|
8010a4c: 200086e0 .word 0x200086e0
|
|
8010a50: 0801dfd4 .word 0x0801dfd4
|
|
8010a54: 0801e04c .word 0x0801e04c
|
|
8010a58: 0801e024 .word 0x0801e024
|
|
|
|
08010a5c <tcpip_init>:
|
|
* @param initfunc a function to call when tcpip_thread is running and finished initializing
|
|
* @param arg argument to pass to initfunc
|
|
*/
|
|
void
|
|
tcpip_init(tcpip_init_done_fn initfunc, void *arg)
|
|
{
|
|
8010a5c: b580 push {r7, lr}
|
|
8010a5e: b084 sub sp, #16
|
|
8010a60: af02 add r7, sp, #8
|
|
8010a62: 6078 str r0, [r7, #4]
|
|
8010a64: 6039 str r1, [r7, #0]
|
|
lwip_init();
|
|
8010a66: f000 f871 bl 8010b4c <lwip_init>
|
|
|
|
tcpip_init_done = initfunc;
|
|
8010a6a: 4a17 ldr r2, [pc, #92] ; (8010ac8 <tcpip_init+0x6c>)
|
|
8010a6c: 687b ldr r3, [r7, #4]
|
|
8010a6e: 6013 str r3, [r2, #0]
|
|
tcpip_init_done_arg = arg;
|
|
8010a70: 4a16 ldr r2, [pc, #88] ; (8010acc <tcpip_init+0x70>)
|
|
8010a72: 683b ldr r3, [r7, #0]
|
|
8010a74: 6013 str r3, [r2, #0]
|
|
if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) {
|
|
8010a76: 2106 movs r1, #6
|
|
8010a78: 4815 ldr r0, [pc, #84] ; (8010ad0 <tcpip_init+0x74>)
|
|
8010a7a: f00b ffa7 bl 801c9cc <sys_mbox_new>
|
|
8010a7e: 4603 mov r3, r0
|
|
8010a80: 2b00 cmp r3, #0
|
|
8010a82: d006 beq.n 8010a92 <tcpip_init+0x36>
|
|
LWIP_ASSERT("failed to create tcpip_thread mbox", 0);
|
|
8010a84: 4b13 ldr r3, [pc, #76] ; (8010ad4 <tcpip_init+0x78>)
|
|
8010a86: f240 2261 movw r2, #609 ; 0x261
|
|
8010a8a: 4913 ldr r1, [pc, #76] ; (8010ad8 <tcpip_init+0x7c>)
|
|
8010a8c: 4813 ldr r0, [pc, #76] ; (8010adc <tcpip_init+0x80>)
|
|
8010a8e: f00c f913 bl 801ccb8 <iprintf>
|
|
}
|
|
#if LWIP_TCPIP_CORE_LOCKING
|
|
if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) {
|
|
8010a92: 4813 ldr r0, [pc, #76] ; (8010ae0 <tcpip_init+0x84>)
|
|
8010a94: f00c f834 bl 801cb00 <sys_mutex_new>
|
|
8010a98: 4603 mov r3, r0
|
|
8010a9a: 2b00 cmp r3, #0
|
|
8010a9c: d006 beq.n 8010aac <tcpip_init+0x50>
|
|
LWIP_ASSERT("failed to create lock_tcpip_core", 0);
|
|
8010a9e: 4b0d ldr r3, [pc, #52] ; (8010ad4 <tcpip_init+0x78>)
|
|
8010aa0: f240 2265 movw r2, #613 ; 0x265
|
|
8010aa4: 490f ldr r1, [pc, #60] ; (8010ae4 <tcpip_init+0x88>)
|
|
8010aa6: 480d ldr r0, [pc, #52] ; (8010adc <tcpip_init+0x80>)
|
|
8010aa8: f00c f906 bl 801ccb8 <iprintf>
|
|
}
|
|
#endif /* LWIP_TCPIP_CORE_LOCKING */
|
|
|
|
sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO);
|
|
8010aac: 2300 movs r3, #0
|
|
8010aae: 9300 str r3, [sp, #0]
|
|
8010ab0: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
8010ab4: 2200 movs r2, #0
|
|
8010ab6: 490c ldr r1, [pc, #48] ; (8010ae8 <tcpip_init+0x8c>)
|
|
8010ab8: 480c ldr r0, [pc, #48] ; (8010aec <tcpip_init+0x90>)
|
|
8010aba: f00c f859 bl 801cb70 <sys_thread_new>
|
|
}
|
|
8010abe: bf00 nop
|
|
8010ac0: 3708 adds r7, #8
|
|
8010ac2: 46bd mov sp, r7
|
|
8010ac4: bd80 pop {r7, pc}
|
|
8010ac6: bf00 nop
|
|
8010ac8: 200086d8 .word 0x200086d8
|
|
8010acc: 200086dc .word 0x200086dc
|
|
8010ad0: 200086e0 .word 0x200086e0
|
|
8010ad4: 0801dfd4 .word 0x0801dfd4
|
|
8010ad8: 0801e05c .word 0x0801e05c
|
|
8010adc: 0801e024 .word 0x0801e024
|
|
8010ae0: 2000c0c4 .word 0x2000c0c4
|
|
8010ae4: 0801e080 .word 0x0801e080
|
|
8010ae8: 08010821 .word 0x08010821
|
|
8010aec: 0801e0a4 .word 0x0801e0a4
|
|
|
|
08010af0 <lwip_htons>:
|
|
* @param n u16_t in host byte order
|
|
* @return n in network byte order
|
|
*/
|
|
u16_t
|
|
lwip_htons(u16_t n)
|
|
{
|
|
8010af0: b480 push {r7}
|
|
8010af2: b083 sub sp, #12
|
|
8010af4: af00 add r7, sp, #0
|
|
8010af6: 4603 mov r3, r0
|
|
8010af8: 80fb strh r3, [r7, #6]
|
|
return PP_HTONS(n);
|
|
8010afa: 88fb ldrh r3, [r7, #6]
|
|
8010afc: 021b lsls r3, r3, #8
|
|
8010afe: b21a sxth r2, r3
|
|
8010b00: 88fb ldrh r3, [r7, #6]
|
|
8010b02: 0a1b lsrs r3, r3, #8
|
|
8010b04: b29b uxth r3, r3
|
|
8010b06: b21b sxth r3, r3
|
|
8010b08: 4313 orrs r3, r2
|
|
8010b0a: b21b sxth r3, r3
|
|
8010b0c: b29b uxth r3, r3
|
|
}
|
|
8010b0e: 4618 mov r0, r3
|
|
8010b10: 370c adds r7, #12
|
|
8010b12: 46bd mov sp, r7
|
|
8010b14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010b18: 4770 bx lr
|
|
|
|
08010b1a <lwip_htonl>:
|
|
* @param n u32_t in host byte order
|
|
* @return n in network byte order
|
|
*/
|
|
u32_t
|
|
lwip_htonl(u32_t n)
|
|
{
|
|
8010b1a: b480 push {r7}
|
|
8010b1c: b083 sub sp, #12
|
|
8010b1e: af00 add r7, sp, #0
|
|
8010b20: 6078 str r0, [r7, #4]
|
|
return PP_HTONL(n);
|
|
8010b22: 687b ldr r3, [r7, #4]
|
|
8010b24: 061a lsls r2, r3, #24
|
|
8010b26: 687b ldr r3, [r7, #4]
|
|
8010b28: 021b lsls r3, r3, #8
|
|
8010b2a: f403 037f and.w r3, r3, #16711680 ; 0xff0000
|
|
8010b2e: 431a orrs r2, r3
|
|
8010b30: 687b ldr r3, [r7, #4]
|
|
8010b32: 0a1b lsrs r3, r3, #8
|
|
8010b34: f403 437f and.w r3, r3, #65280 ; 0xff00
|
|
8010b38: 431a orrs r2, r3
|
|
8010b3a: 687b ldr r3, [r7, #4]
|
|
8010b3c: 0e1b lsrs r3, r3, #24
|
|
8010b3e: 4313 orrs r3, r2
|
|
}
|
|
8010b40: 4618 mov r0, r3
|
|
8010b42: 370c adds r7, #12
|
|
8010b44: 46bd mov sp, r7
|
|
8010b46: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010b4a: 4770 bx lr
|
|
|
|
08010b4c <lwip_init>:
|
|
* Initialize all modules.
|
|
* Use this in NO_SYS mode. Use tcpip_init() otherwise.
|
|
*/
|
|
void
|
|
lwip_init(void)
|
|
{
|
|
8010b4c: b580 push {r7, lr}
|
|
8010b4e: b082 sub sp, #8
|
|
8010b50: af00 add r7, sp, #0
|
|
#ifndef LWIP_SKIP_CONST_CHECK
|
|
int a = 0;
|
|
8010b52: 2300 movs r3, #0
|
|
8010b54: 607b str r3, [r7, #4]
|
|
#endif
|
|
|
|
/* Modules initialization */
|
|
stats_init();
|
|
#if !NO_SYS
|
|
sys_init();
|
|
8010b56: f00b ffc5 bl 801cae4 <sys_init>
|
|
#endif /* !NO_SYS */
|
|
mem_init();
|
|
8010b5a: f000 f8d5 bl 8010d08 <mem_init>
|
|
memp_init();
|
|
8010b5e: f000 fc31 bl 80113c4 <memp_init>
|
|
pbuf_init();
|
|
netif_init();
|
|
8010b62: f000 fcf7 bl 8011554 <netif_init>
|
|
#endif /* LWIP_IPV4 */
|
|
#if LWIP_RAW
|
|
raw_init();
|
|
#endif /* LWIP_RAW */
|
|
#if LWIP_UDP
|
|
udp_init();
|
|
8010b66: f007 f8f5 bl 8017d54 <udp_init>
|
|
#endif /* LWIP_UDP */
|
|
#if LWIP_TCP
|
|
tcp_init();
|
|
8010b6a: f001 fe1f bl 80127ac <tcp_init>
|
|
#if PPP_SUPPORT
|
|
ppp_init();
|
|
#endif
|
|
|
|
#if LWIP_TIMERS
|
|
sys_timeouts_init();
|
|
8010b6e: f007 f839 bl 8017be4 <sys_timeouts_init>
|
|
#endif /* LWIP_TIMERS */
|
|
}
|
|
8010b72: bf00 nop
|
|
8010b74: 3708 adds r7, #8
|
|
8010b76: 46bd mov sp, r7
|
|
8010b78: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08010b7c <ptr_to_mem>:
|
|
#define mem_overflow_check_element(mem)
|
|
#endif /* MEM_OVERFLOW_CHECK */
|
|
|
|
static struct mem *
|
|
ptr_to_mem(mem_size_t ptr)
|
|
{
|
|
8010b7c: b480 push {r7}
|
|
8010b7e: b083 sub sp, #12
|
|
8010b80: af00 add r7, sp, #0
|
|
8010b82: 4603 mov r3, r0
|
|
8010b84: 80fb strh r3, [r7, #6]
|
|
return (struct mem *)(void *)&ram[ptr];
|
|
8010b86: 4b05 ldr r3, [pc, #20] ; (8010b9c <ptr_to_mem+0x20>)
|
|
8010b88: 681a ldr r2, [r3, #0]
|
|
8010b8a: 88fb ldrh r3, [r7, #6]
|
|
8010b8c: 4413 add r3, r2
|
|
}
|
|
8010b8e: 4618 mov r0, r3
|
|
8010b90: 370c adds r7, #12
|
|
8010b92: 46bd mov sp, r7
|
|
8010b94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010b98: 4770 bx lr
|
|
8010b9a: bf00 nop
|
|
8010b9c: 200086e4 .word 0x200086e4
|
|
|
|
08010ba0 <mem_to_ptr>:
|
|
|
|
static mem_size_t
|
|
mem_to_ptr(void *mem)
|
|
{
|
|
8010ba0: b480 push {r7}
|
|
8010ba2: b083 sub sp, #12
|
|
8010ba4: af00 add r7, sp, #0
|
|
8010ba6: 6078 str r0, [r7, #4]
|
|
return (mem_size_t)((u8_t *)mem - ram);
|
|
8010ba8: 687b ldr r3, [r7, #4]
|
|
8010baa: 4a05 ldr r2, [pc, #20] ; (8010bc0 <mem_to_ptr+0x20>)
|
|
8010bac: 6812 ldr r2, [r2, #0]
|
|
8010bae: 1a9b subs r3, r3, r2
|
|
8010bb0: b29b uxth r3, r3
|
|
}
|
|
8010bb2: 4618 mov r0, r3
|
|
8010bb4: 370c adds r7, #12
|
|
8010bb6: 46bd mov sp, r7
|
|
8010bb8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8010bbc: 4770 bx lr
|
|
8010bbe: bf00 nop
|
|
8010bc0: 200086e4 .word 0x200086e4
|
|
|
|
08010bc4 <plug_holes>:
|
|
* This assumes access to the heap is protected by the calling function
|
|
* already.
|
|
*/
|
|
static void
|
|
plug_holes(struct mem *mem)
|
|
{
|
|
8010bc4: b590 push {r4, r7, lr}
|
|
8010bc6: b085 sub sp, #20
|
|
8010bc8: af00 add r7, sp, #0
|
|
8010bca: 6078 str r0, [r7, #4]
|
|
struct mem *nmem;
|
|
struct mem *pmem;
|
|
|
|
LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram);
|
|
8010bcc: 4b45 ldr r3, [pc, #276] ; (8010ce4 <plug_holes+0x120>)
|
|
8010bce: 681b ldr r3, [r3, #0]
|
|
8010bd0: 687a ldr r2, [r7, #4]
|
|
8010bd2: 429a cmp r2, r3
|
|
8010bd4: d206 bcs.n 8010be4 <plug_holes+0x20>
|
|
8010bd6: 4b44 ldr r3, [pc, #272] ; (8010ce8 <plug_holes+0x124>)
|
|
8010bd8: f240 12df movw r2, #479 ; 0x1df
|
|
8010bdc: 4943 ldr r1, [pc, #268] ; (8010cec <plug_holes+0x128>)
|
|
8010bde: 4844 ldr r0, [pc, #272] ; (8010cf0 <plug_holes+0x12c>)
|
|
8010be0: f00c f86a bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end);
|
|
8010be4: 4b43 ldr r3, [pc, #268] ; (8010cf4 <plug_holes+0x130>)
|
|
8010be6: 681b ldr r3, [r3, #0]
|
|
8010be8: 687a ldr r2, [r7, #4]
|
|
8010bea: 429a cmp r2, r3
|
|
8010bec: d306 bcc.n 8010bfc <plug_holes+0x38>
|
|
8010bee: 4b3e ldr r3, [pc, #248] ; (8010ce8 <plug_holes+0x124>)
|
|
8010bf0: f44f 72f0 mov.w r2, #480 ; 0x1e0
|
|
8010bf4: 4940 ldr r1, [pc, #256] ; (8010cf8 <plug_holes+0x134>)
|
|
8010bf6: 483e ldr r0, [pc, #248] ; (8010cf0 <plug_holes+0x12c>)
|
|
8010bf8: f00c f85e bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0);
|
|
8010bfc: 687b ldr r3, [r7, #4]
|
|
8010bfe: 791b ldrb r3, [r3, #4]
|
|
8010c00: 2b00 cmp r3, #0
|
|
8010c02: d006 beq.n 8010c12 <plug_holes+0x4e>
|
|
8010c04: 4b38 ldr r3, [pc, #224] ; (8010ce8 <plug_holes+0x124>)
|
|
8010c06: f240 12e1 movw r2, #481 ; 0x1e1
|
|
8010c0a: 493c ldr r1, [pc, #240] ; (8010cfc <plug_holes+0x138>)
|
|
8010c0c: 4838 ldr r0, [pc, #224] ; (8010cf0 <plug_holes+0x12c>)
|
|
8010c0e: f00c f853 bl 801ccb8 <iprintf>
|
|
|
|
/* plug hole forward */
|
|
LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED);
|
|
8010c12: 687b ldr r3, [r7, #4]
|
|
8010c14: 881b ldrh r3, [r3, #0]
|
|
8010c16: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010c1a: d906 bls.n 8010c2a <plug_holes+0x66>
|
|
8010c1c: 4b32 ldr r3, [pc, #200] ; (8010ce8 <plug_holes+0x124>)
|
|
8010c1e: f44f 72f2 mov.w r2, #484 ; 0x1e4
|
|
8010c22: 4937 ldr r1, [pc, #220] ; (8010d00 <plug_holes+0x13c>)
|
|
8010c24: 4832 ldr r0, [pc, #200] ; (8010cf0 <plug_holes+0x12c>)
|
|
8010c26: f00c f847 bl 801ccb8 <iprintf>
|
|
|
|
nmem = ptr_to_mem(mem->next);
|
|
8010c2a: 687b ldr r3, [r7, #4]
|
|
8010c2c: 881b ldrh r3, [r3, #0]
|
|
8010c2e: 4618 mov r0, r3
|
|
8010c30: f7ff ffa4 bl 8010b7c <ptr_to_mem>
|
|
8010c34: 60f8 str r0, [r7, #12]
|
|
if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) {
|
|
8010c36: 687a ldr r2, [r7, #4]
|
|
8010c38: 68fb ldr r3, [r7, #12]
|
|
8010c3a: 429a cmp r2, r3
|
|
8010c3c: d024 beq.n 8010c88 <plug_holes+0xc4>
|
|
8010c3e: 68fb ldr r3, [r7, #12]
|
|
8010c40: 791b ldrb r3, [r3, #4]
|
|
8010c42: 2b00 cmp r3, #0
|
|
8010c44: d120 bne.n 8010c88 <plug_holes+0xc4>
|
|
8010c46: 4b2b ldr r3, [pc, #172] ; (8010cf4 <plug_holes+0x130>)
|
|
8010c48: 681b ldr r3, [r3, #0]
|
|
8010c4a: 68fa ldr r2, [r7, #12]
|
|
8010c4c: 429a cmp r2, r3
|
|
8010c4e: d01b beq.n 8010c88 <plug_holes+0xc4>
|
|
/* if mem->next is unused and not end of ram, combine mem and mem->next */
|
|
if (lfree == nmem) {
|
|
8010c50: 4b2c ldr r3, [pc, #176] ; (8010d04 <plug_holes+0x140>)
|
|
8010c52: 681b ldr r3, [r3, #0]
|
|
8010c54: 68fa ldr r2, [r7, #12]
|
|
8010c56: 429a cmp r2, r3
|
|
8010c58: d102 bne.n 8010c60 <plug_holes+0x9c>
|
|
lfree = mem;
|
|
8010c5a: 4a2a ldr r2, [pc, #168] ; (8010d04 <plug_holes+0x140>)
|
|
8010c5c: 687b ldr r3, [r7, #4]
|
|
8010c5e: 6013 str r3, [r2, #0]
|
|
}
|
|
mem->next = nmem->next;
|
|
8010c60: 68fb ldr r3, [r7, #12]
|
|
8010c62: 881a ldrh r2, [r3, #0]
|
|
8010c64: 687b ldr r3, [r7, #4]
|
|
8010c66: 801a strh r2, [r3, #0]
|
|
if (nmem->next != MEM_SIZE_ALIGNED) {
|
|
8010c68: 68fb ldr r3, [r7, #12]
|
|
8010c6a: 881b ldrh r3, [r3, #0]
|
|
8010c6c: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010c70: d00a beq.n 8010c88 <plug_holes+0xc4>
|
|
ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem);
|
|
8010c72: 68fb ldr r3, [r7, #12]
|
|
8010c74: 881b ldrh r3, [r3, #0]
|
|
8010c76: 4618 mov r0, r3
|
|
8010c78: f7ff ff80 bl 8010b7c <ptr_to_mem>
|
|
8010c7c: 4604 mov r4, r0
|
|
8010c7e: 6878 ldr r0, [r7, #4]
|
|
8010c80: f7ff ff8e bl 8010ba0 <mem_to_ptr>
|
|
8010c84: 4603 mov r3, r0
|
|
8010c86: 8063 strh r3, [r4, #2]
|
|
}
|
|
}
|
|
|
|
/* plug hole backward */
|
|
pmem = ptr_to_mem(mem->prev);
|
|
8010c88: 687b ldr r3, [r7, #4]
|
|
8010c8a: 885b ldrh r3, [r3, #2]
|
|
8010c8c: 4618 mov r0, r3
|
|
8010c8e: f7ff ff75 bl 8010b7c <ptr_to_mem>
|
|
8010c92: 60b8 str r0, [r7, #8]
|
|
if (pmem != mem && pmem->used == 0) {
|
|
8010c94: 68ba ldr r2, [r7, #8]
|
|
8010c96: 687b ldr r3, [r7, #4]
|
|
8010c98: 429a cmp r2, r3
|
|
8010c9a: d01f beq.n 8010cdc <plug_holes+0x118>
|
|
8010c9c: 68bb ldr r3, [r7, #8]
|
|
8010c9e: 791b ldrb r3, [r3, #4]
|
|
8010ca0: 2b00 cmp r3, #0
|
|
8010ca2: d11b bne.n 8010cdc <plug_holes+0x118>
|
|
/* if mem->prev is unused, combine mem and mem->prev */
|
|
if (lfree == mem) {
|
|
8010ca4: 4b17 ldr r3, [pc, #92] ; (8010d04 <plug_holes+0x140>)
|
|
8010ca6: 681b ldr r3, [r3, #0]
|
|
8010ca8: 687a ldr r2, [r7, #4]
|
|
8010caa: 429a cmp r2, r3
|
|
8010cac: d102 bne.n 8010cb4 <plug_holes+0xf0>
|
|
lfree = pmem;
|
|
8010cae: 4a15 ldr r2, [pc, #84] ; (8010d04 <plug_holes+0x140>)
|
|
8010cb0: 68bb ldr r3, [r7, #8]
|
|
8010cb2: 6013 str r3, [r2, #0]
|
|
}
|
|
pmem->next = mem->next;
|
|
8010cb4: 687b ldr r3, [r7, #4]
|
|
8010cb6: 881a ldrh r2, [r3, #0]
|
|
8010cb8: 68bb ldr r3, [r7, #8]
|
|
8010cba: 801a strh r2, [r3, #0]
|
|
if (mem->next != MEM_SIZE_ALIGNED) {
|
|
8010cbc: 687b ldr r3, [r7, #4]
|
|
8010cbe: 881b ldrh r3, [r3, #0]
|
|
8010cc0: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010cc4: d00a beq.n 8010cdc <plug_holes+0x118>
|
|
ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem);
|
|
8010cc6: 687b ldr r3, [r7, #4]
|
|
8010cc8: 881b ldrh r3, [r3, #0]
|
|
8010cca: 4618 mov r0, r3
|
|
8010ccc: f7ff ff56 bl 8010b7c <ptr_to_mem>
|
|
8010cd0: 4604 mov r4, r0
|
|
8010cd2: 68b8 ldr r0, [r7, #8]
|
|
8010cd4: f7ff ff64 bl 8010ba0 <mem_to_ptr>
|
|
8010cd8: 4603 mov r3, r0
|
|
8010cda: 8063 strh r3, [r4, #2]
|
|
}
|
|
}
|
|
}
|
|
8010cdc: bf00 nop
|
|
8010cde: 3714 adds r7, #20
|
|
8010ce0: 46bd mov sp, r7
|
|
8010ce2: bd90 pop {r4, r7, pc}
|
|
8010ce4: 200086e4 .word 0x200086e4
|
|
8010ce8: 0801e0b4 .word 0x0801e0b4
|
|
8010cec: 0801e0e4 .word 0x0801e0e4
|
|
8010cf0: 0801e0fc .word 0x0801e0fc
|
|
8010cf4: 200086e8 .word 0x200086e8
|
|
8010cf8: 0801e124 .word 0x0801e124
|
|
8010cfc: 0801e140 .word 0x0801e140
|
|
8010d00: 0801e15c .word 0x0801e15c
|
|
8010d04: 200086f0 .word 0x200086f0
|
|
|
|
08010d08 <mem_init>:
|
|
/**
|
|
* Zero the heap and initialize start, end and lowest-free
|
|
*/
|
|
void
|
|
mem_init(void)
|
|
{
|
|
8010d08: b580 push {r7, lr}
|
|
8010d0a: b082 sub sp, #8
|
|
8010d0c: af00 add r7, sp, #0
|
|
|
|
LWIP_ASSERT("Sanity check alignment",
|
|
(SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0);
|
|
|
|
/* align the heap */
|
|
ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER);
|
|
8010d0e: 4b1f ldr r3, [pc, #124] ; (8010d8c <mem_init+0x84>)
|
|
8010d10: 3303 adds r3, #3
|
|
8010d12: f023 0303 bic.w r3, r3, #3
|
|
8010d16: 461a mov r2, r3
|
|
8010d18: 4b1d ldr r3, [pc, #116] ; (8010d90 <mem_init+0x88>)
|
|
8010d1a: 601a str r2, [r3, #0]
|
|
/* initialize the start of the heap */
|
|
mem = (struct mem *)(void *)ram;
|
|
8010d1c: 4b1c ldr r3, [pc, #112] ; (8010d90 <mem_init+0x88>)
|
|
8010d1e: 681b ldr r3, [r3, #0]
|
|
8010d20: 607b str r3, [r7, #4]
|
|
mem->next = MEM_SIZE_ALIGNED;
|
|
8010d22: 687b ldr r3, [r7, #4]
|
|
8010d24: f44f 62c8 mov.w r2, #1600 ; 0x640
|
|
8010d28: 801a strh r2, [r3, #0]
|
|
mem->prev = 0;
|
|
8010d2a: 687b ldr r3, [r7, #4]
|
|
8010d2c: 2200 movs r2, #0
|
|
8010d2e: 805a strh r2, [r3, #2]
|
|
mem->used = 0;
|
|
8010d30: 687b ldr r3, [r7, #4]
|
|
8010d32: 2200 movs r2, #0
|
|
8010d34: 711a strb r2, [r3, #4]
|
|
/* initialize the end of the heap */
|
|
ram_end = ptr_to_mem(MEM_SIZE_ALIGNED);
|
|
8010d36: f44f 60c8 mov.w r0, #1600 ; 0x640
|
|
8010d3a: f7ff ff1f bl 8010b7c <ptr_to_mem>
|
|
8010d3e: 4602 mov r2, r0
|
|
8010d40: 4b14 ldr r3, [pc, #80] ; (8010d94 <mem_init+0x8c>)
|
|
8010d42: 601a str r2, [r3, #0]
|
|
ram_end->used = 1;
|
|
8010d44: 4b13 ldr r3, [pc, #76] ; (8010d94 <mem_init+0x8c>)
|
|
8010d46: 681b ldr r3, [r3, #0]
|
|
8010d48: 2201 movs r2, #1
|
|
8010d4a: 711a strb r2, [r3, #4]
|
|
ram_end->next = MEM_SIZE_ALIGNED;
|
|
8010d4c: 4b11 ldr r3, [pc, #68] ; (8010d94 <mem_init+0x8c>)
|
|
8010d4e: 681b ldr r3, [r3, #0]
|
|
8010d50: f44f 62c8 mov.w r2, #1600 ; 0x640
|
|
8010d54: 801a strh r2, [r3, #0]
|
|
ram_end->prev = MEM_SIZE_ALIGNED;
|
|
8010d56: 4b0f ldr r3, [pc, #60] ; (8010d94 <mem_init+0x8c>)
|
|
8010d58: 681b ldr r3, [r3, #0]
|
|
8010d5a: f44f 62c8 mov.w r2, #1600 ; 0x640
|
|
8010d5e: 805a strh r2, [r3, #2]
|
|
MEM_SANITY();
|
|
|
|
/* initialize the lowest-free pointer to the start of the heap */
|
|
lfree = (struct mem *)(void *)ram;
|
|
8010d60: 4b0b ldr r3, [pc, #44] ; (8010d90 <mem_init+0x88>)
|
|
8010d62: 681b ldr r3, [r3, #0]
|
|
8010d64: 4a0c ldr r2, [pc, #48] ; (8010d98 <mem_init+0x90>)
|
|
8010d66: 6013 str r3, [r2, #0]
|
|
|
|
MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED);
|
|
|
|
if (sys_mutex_new(&mem_mutex) != ERR_OK) {
|
|
8010d68: 480c ldr r0, [pc, #48] ; (8010d9c <mem_init+0x94>)
|
|
8010d6a: f00b fec9 bl 801cb00 <sys_mutex_new>
|
|
8010d6e: 4603 mov r3, r0
|
|
8010d70: 2b00 cmp r3, #0
|
|
8010d72: d006 beq.n 8010d82 <mem_init+0x7a>
|
|
LWIP_ASSERT("failed to create mem_mutex", 0);
|
|
8010d74: 4b0a ldr r3, [pc, #40] ; (8010da0 <mem_init+0x98>)
|
|
8010d76: f240 221f movw r2, #543 ; 0x21f
|
|
8010d7a: 490a ldr r1, [pc, #40] ; (8010da4 <mem_init+0x9c>)
|
|
8010d7c: 480a ldr r0, [pc, #40] ; (8010da8 <mem_init+0xa0>)
|
|
8010d7e: f00b ff9b bl 801ccb8 <iprintf>
|
|
}
|
|
}
|
|
8010d82: bf00 nop
|
|
8010d84: 3708 adds r7, #8
|
|
8010d86: 46bd mov sp, r7
|
|
8010d88: bd80 pop {r7, pc}
|
|
8010d8a: bf00 nop
|
|
8010d8c: 2000c0e0 .word 0x2000c0e0
|
|
8010d90: 200086e4 .word 0x200086e4
|
|
8010d94: 200086e8 .word 0x200086e8
|
|
8010d98: 200086f0 .word 0x200086f0
|
|
8010d9c: 200086ec .word 0x200086ec
|
|
8010da0: 0801e0b4 .word 0x0801e0b4
|
|
8010da4: 0801e188 .word 0x0801e188
|
|
8010da8: 0801e0fc .word 0x0801e0fc
|
|
|
|
08010dac <mem_link_valid>:
|
|
/* Check if a struct mem is correctly linked.
|
|
* If not, double-free is a possible reason.
|
|
*/
|
|
static int
|
|
mem_link_valid(struct mem *mem)
|
|
{
|
|
8010dac: b580 push {r7, lr}
|
|
8010dae: b086 sub sp, #24
|
|
8010db0: af00 add r7, sp, #0
|
|
8010db2: 6078 str r0, [r7, #4]
|
|
struct mem *nmem, *pmem;
|
|
mem_size_t rmem_idx;
|
|
rmem_idx = mem_to_ptr(mem);
|
|
8010db4: 6878 ldr r0, [r7, #4]
|
|
8010db6: f7ff fef3 bl 8010ba0 <mem_to_ptr>
|
|
8010dba: 4603 mov r3, r0
|
|
8010dbc: 82fb strh r3, [r7, #22]
|
|
nmem = ptr_to_mem(mem->next);
|
|
8010dbe: 687b ldr r3, [r7, #4]
|
|
8010dc0: 881b ldrh r3, [r3, #0]
|
|
8010dc2: 4618 mov r0, r3
|
|
8010dc4: f7ff feda bl 8010b7c <ptr_to_mem>
|
|
8010dc8: 6138 str r0, [r7, #16]
|
|
pmem = ptr_to_mem(mem->prev);
|
|
8010dca: 687b ldr r3, [r7, #4]
|
|
8010dcc: 885b ldrh r3, [r3, #2]
|
|
8010dce: 4618 mov r0, r3
|
|
8010dd0: f7ff fed4 bl 8010b7c <ptr_to_mem>
|
|
8010dd4: 60f8 str r0, [r7, #12]
|
|
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
|
|
8010dd6: 687b ldr r3, [r7, #4]
|
|
8010dd8: 881b ldrh r3, [r3, #0]
|
|
8010dda: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010dde: d818 bhi.n 8010e12 <mem_link_valid+0x66>
|
|
8010de0: 687b ldr r3, [r7, #4]
|
|
8010de2: 885b ldrh r3, [r3, #2]
|
|
8010de4: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010de8: d813 bhi.n 8010e12 <mem_link_valid+0x66>
|
|
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
|
|
8010dea: 687b ldr r3, [r7, #4]
|
|
8010dec: 885b ldrh r3, [r3, #2]
|
|
if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) ||
|
|
8010dee: 8afa ldrh r2, [r7, #22]
|
|
8010df0: 429a cmp r2, r3
|
|
8010df2: d004 beq.n 8010dfe <mem_link_valid+0x52>
|
|
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
|
|
8010df4: 68fb ldr r3, [r7, #12]
|
|
8010df6: 881b ldrh r3, [r3, #0]
|
|
8010df8: 8afa ldrh r2, [r7, #22]
|
|
8010dfa: 429a cmp r2, r3
|
|
8010dfc: d109 bne.n 8010e12 <mem_link_valid+0x66>
|
|
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
|
|
8010dfe: 4b08 ldr r3, [pc, #32] ; (8010e20 <mem_link_valid+0x74>)
|
|
8010e00: 681b ldr r3, [r3, #0]
|
|
((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) ||
|
|
8010e02: 693a ldr r2, [r7, #16]
|
|
8010e04: 429a cmp r2, r3
|
|
8010e06: d006 beq.n 8010e16 <mem_link_valid+0x6a>
|
|
((nmem != ram_end) && (nmem->prev != rmem_idx))) {
|
|
8010e08: 693b ldr r3, [r7, #16]
|
|
8010e0a: 885b ldrh r3, [r3, #2]
|
|
8010e0c: 8afa ldrh r2, [r7, #22]
|
|
8010e0e: 429a cmp r2, r3
|
|
8010e10: d001 beq.n 8010e16 <mem_link_valid+0x6a>
|
|
return 0;
|
|
8010e12: 2300 movs r3, #0
|
|
8010e14: e000 b.n 8010e18 <mem_link_valid+0x6c>
|
|
}
|
|
return 1;
|
|
8010e16: 2301 movs r3, #1
|
|
}
|
|
8010e18: 4618 mov r0, r3
|
|
8010e1a: 3718 adds r7, #24
|
|
8010e1c: 46bd mov sp, r7
|
|
8010e1e: bd80 pop {r7, pc}
|
|
8010e20: 200086e8 .word 0x200086e8
|
|
|
|
08010e24 <mem_free>:
|
|
* @param rmem is the data portion of a struct mem as returned by a previous
|
|
* call to mem_malloc()
|
|
*/
|
|
void
|
|
mem_free(void *rmem)
|
|
{
|
|
8010e24: b580 push {r7, lr}
|
|
8010e26: b088 sub sp, #32
|
|
8010e28: af00 add r7, sp, #0
|
|
8010e2a: 6078 str r0, [r7, #4]
|
|
struct mem *mem;
|
|
LWIP_MEM_FREE_DECL_PROTECT();
|
|
|
|
if (rmem == NULL) {
|
|
8010e2c: 687b ldr r3, [r7, #4]
|
|
8010e2e: 2b00 cmp r3, #0
|
|
8010e30: d070 beq.n 8010f14 <mem_free+0xf0>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n"));
|
|
return;
|
|
}
|
|
if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) {
|
|
8010e32: 687b ldr r3, [r7, #4]
|
|
8010e34: f003 0303 and.w r3, r3, #3
|
|
8010e38: 2b00 cmp r3, #0
|
|
8010e3a: d00d beq.n 8010e58 <mem_free+0x34>
|
|
LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment");
|
|
8010e3c: 4b37 ldr r3, [pc, #220] ; (8010f1c <mem_free+0xf8>)
|
|
8010e3e: f240 2273 movw r2, #627 ; 0x273
|
|
8010e42: 4937 ldr r1, [pc, #220] ; (8010f20 <mem_free+0xfc>)
|
|
8010e44: 4837 ldr r0, [pc, #220] ; (8010f24 <mem_free+0x100>)
|
|
8010e46: f00b ff37 bl 801ccb8 <iprintf>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n"));
|
|
/* protect mem stats from concurrent access */
|
|
MEM_STATS_INC_LOCKED(illegal);
|
|
8010e4a: f00b feb7 bl 801cbbc <sys_arch_protect>
|
|
8010e4e: 60f8 str r0, [r7, #12]
|
|
8010e50: 68f8 ldr r0, [r7, #12]
|
|
8010e52: f00b fec1 bl 801cbd8 <sys_arch_unprotect>
|
|
return;
|
|
8010e56: e05e b.n 8010f16 <mem_free+0xf2>
|
|
}
|
|
|
|
/* Get the corresponding struct mem: */
|
|
/* cast through void* to get rid of alignment warnings */
|
|
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
|
|
8010e58: 687b ldr r3, [r7, #4]
|
|
8010e5a: 3b08 subs r3, #8
|
|
8010e5c: 61fb str r3, [r7, #28]
|
|
|
|
if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) {
|
|
8010e5e: 4b32 ldr r3, [pc, #200] ; (8010f28 <mem_free+0x104>)
|
|
8010e60: 681b ldr r3, [r3, #0]
|
|
8010e62: 69fa ldr r2, [r7, #28]
|
|
8010e64: 429a cmp r2, r3
|
|
8010e66: d306 bcc.n 8010e76 <mem_free+0x52>
|
|
8010e68: 687b ldr r3, [r7, #4]
|
|
8010e6a: f103 020c add.w r2, r3, #12
|
|
8010e6e: 4b2f ldr r3, [pc, #188] ; (8010f2c <mem_free+0x108>)
|
|
8010e70: 681b ldr r3, [r3, #0]
|
|
8010e72: 429a cmp r2, r3
|
|
8010e74: d90d bls.n 8010e92 <mem_free+0x6e>
|
|
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory");
|
|
8010e76: 4b29 ldr r3, [pc, #164] ; (8010f1c <mem_free+0xf8>)
|
|
8010e78: f240 227f movw r2, #639 ; 0x27f
|
|
8010e7c: 492c ldr r1, [pc, #176] ; (8010f30 <mem_free+0x10c>)
|
|
8010e7e: 4829 ldr r0, [pc, #164] ; (8010f24 <mem_free+0x100>)
|
|
8010e80: f00b ff1a bl 801ccb8 <iprintf>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n"));
|
|
/* protect mem stats from concurrent access */
|
|
MEM_STATS_INC_LOCKED(illegal);
|
|
8010e84: f00b fe9a bl 801cbbc <sys_arch_protect>
|
|
8010e88: 6138 str r0, [r7, #16]
|
|
8010e8a: 6938 ldr r0, [r7, #16]
|
|
8010e8c: f00b fea4 bl 801cbd8 <sys_arch_unprotect>
|
|
return;
|
|
8010e90: e041 b.n 8010f16 <mem_free+0xf2>
|
|
}
|
|
#if MEM_OVERFLOW_CHECK
|
|
mem_overflow_check_element(mem);
|
|
#endif
|
|
/* protect the heap from concurrent access */
|
|
LWIP_MEM_FREE_PROTECT();
|
|
8010e92: 4828 ldr r0, [pc, #160] ; (8010f34 <mem_free+0x110>)
|
|
8010e94: f00b fe50 bl 801cb38 <sys_mutex_lock>
|
|
/* mem has to be in a used state */
|
|
if (!mem->used) {
|
|
8010e98: 69fb ldr r3, [r7, #28]
|
|
8010e9a: 791b ldrb r3, [r3, #4]
|
|
8010e9c: 2b00 cmp r3, #0
|
|
8010e9e: d110 bne.n 8010ec2 <mem_free+0x9e>
|
|
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free");
|
|
8010ea0: 4b1e ldr r3, [pc, #120] ; (8010f1c <mem_free+0xf8>)
|
|
8010ea2: f44f 7223 mov.w r2, #652 ; 0x28c
|
|
8010ea6: 4924 ldr r1, [pc, #144] ; (8010f38 <mem_free+0x114>)
|
|
8010ea8: 481e ldr r0, [pc, #120] ; (8010f24 <mem_free+0x100>)
|
|
8010eaa: f00b ff05 bl 801ccb8 <iprintf>
|
|
LWIP_MEM_FREE_UNPROTECT();
|
|
8010eae: 4821 ldr r0, [pc, #132] ; (8010f34 <mem_free+0x110>)
|
|
8010eb0: f00b fe51 bl 801cb56 <sys_mutex_unlock>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n"));
|
|
/* protect mem stats from concurrent access */
|
|
MEM_STATS_INC_LOCKED(illegal);
|
|
8010eb4: f00b fe82 bl 801cbbc <sys_arch_protect>
|
|
8010eb8: 6178 str r0, [r7, #20]
|
|
8010eba: 6978 ldr r0, [r7, #20]
|
|
8010ebc: f00b fe8c bl 801cbd8 <sys_arch_unprotect>
|
|
return;
|
|
8010ec0: e029 b.n 8010f16 <mem_free+0xf2>
|
|
}
|
|
|
|
if (!mem_link_valid(mem)) {
|
|
8010ec2: 69f8 ldr r0, [r7, #28]
|
|
8010ec4: f7ff ff72 bl 8010dac <mem_link_valid>
|
|
8010ec8: 4603 mov r3, r0
|
|
8010eca: 2b00 cmp r3, #0
|
|
8010ecc: d110 bne.n 8010ef0 <mem_free+0xcc>
|
|
LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free");
|
|
8010ece: 4b13 ldr r3, [pc, #76] ; (8010f1c <mem_free+0xf8>)
|
|
8010ed0: f240 2295 movw r2, #661 ; 0x295
|
|
8010ed4: 4919 ldr r1, [pc, #100] ; (8010f3c <mem_free+0x118>)
|
|
8010ed6: 4813 ldr r0, [pc, #76] ; (8010f24 <mem_free+0x100>)
|
|
8010ed8: f00b feee bl 801ccb8 <iprintf>
|
|
LWIP_MEM_FREE_UNPROTECT();
|
|
8010edc: 4815 ldr r0, [pc, #84] ; (8010f34 <mem_free+0x110>)
|
|
8010ede: f00b fe3a bl 801cb56 <sys_mutex_unlock>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n"));
|
|
/* protect mem stats from concurrent access */
|
|
MEM_STATS_INC_LOCKED(illegal);
|
|
8010ee2: f00b fe6b bl 801cbbc <sys_arch_protect>
|
|
8010ee6: 61b8 str r0, [r7, #24]
|
|
8010ee8: 69b8 ldr r0, [r7, #24]
|
|
8010eea: f00b fe75 bl 801cbd8 <sys_arch_unprotect>
|
|
return;
|
|
8010eee: e012 b.n 8010f16 <mem_free+0xf2>
|
|
}
|
|
|
|
/* mem is now unused. */
|
|
mem->used = 0;
|
|
8010ef0: 69fb ldr r3, [r7, #28]
|
|
8010ef2: 2200 movs r2, #0
|
|
8010ef4: 711a strb r2, [r3, #4]
|
|
|
|
if (mem < lfree) {
|
|
8010ef6: 4b12 ldr r3, [pc, #72] ; (8010f40 <mem_free+0x11c>)
|
|
8010ef8: 681b ldr r3, [r3, #0]
|
|
8010efa: 69fa ldr r2, [r7, #28]
|
|
8010efc: 429a cmp r2, r3
|
|
8010efe: d202 bcs.n 8010f06 <mem_free+0xe2>
|
|
/* the newly freed struct is now the lowest */
|
|
lfree = mem;
|
|
8010f00: 4a0f ldr r2, [pc, #60] ; (8010f40 <mem_free+0x11c>)
|
|
8010f02: 69fb ldr r3, [r7, #28]
|
|
8010f04: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram)));
|
|
|
|
/* finally, see if prev or next are free also */
|
|
plug_holes(mem);
|
|
8010f06: 69f8 ldr r0, [r7, #28]
|
|
8010f08: f7ff fe5c bl 8010bc4 <plug_holes>
|
|
MEM_SANITY();
|
|
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
|
mem_free_count = 1;
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
LWIP_MEM_FREE_UNPROTECT();
|
|
8010f0c: 4809 ldr r0, [pc, #36] ; (8010f34 <mem_free+0x110>)
|
|
8010f0e: f00b fe22 bl 801cb56 <sys_mutex_unlock>
|
|
8010f12: e000 b.n 8010f16 <mem_free+0xf2>
|
|
return;
|
|
8010f14: bf00 nop
|
|
}
|
|
8010f16: 3720 adds r7, #32
|
|
8010f18: 46bd mov sp, r7
|
|
8010f1a: bd80 pop {r7, pc}
|
|
8010f1c: 0801e0b4 .word 0x0801e0b4
|
|
8010f20: 0801e1a4 .word 0x0801e1a4
|
|
8010f24: 0801e0fc .word 0x0801e0fc
|
|
8010f28: 200086e4 .word 0x200086e4
|
|
8010f2c: 200086e8 .word 0x200086e8
|
|
8010f30: 0801e1c8 .word 0x0801e1c8
|
|
8010f34: 200086ec .word 0x200086ec
|
|
8010f38: 0801e1e4 .word 0x0801e1e4
|
|
8010f3c: 0801e20c .word 0x0801e20c
|
|
8010f40: 200086f0 .word 0x200086f0
|
|
|
|
08010f44 <mem_trim>:
|
|
* or NULL if newsize is > old size, in which case rmem is NOT touched
|
|
* or freed!
|
|
*/
|
|
void *
|
|
mem_trim(void *rmem, mem_size_t new_size)
|
|
{
|
|
8010f44: b580 push {r7, lr}
|
|
8010f46: b088 sub sp, #32
|
|
8010f48: af00 add r7, sp, #0
|
|
8010f4a: 6078 str r0, [r7, #4]
|
|
8010f4c: 460b mov r3, r1
|
|
8010f4e: 807b strh r3, [r7, #2]
|
|
/* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */
|
|
LWIP_MEM_FREE_DECL_PROTECT();
|
|
|
|
/* Expand the size of the allocated memory region so that we can
|
|
adjust for alignment. */
|
|
newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size);
|
|
8010f50: 887b ldrh r3, [r7, #2]
|
|
8010f52: 3303 adds r3, #3
|
|
8010f54: b29b uxth r3, r3
|
|
8010f56: f023 0303 bic.w r3, r3, #3
|
|
8010f5a: 83fb strh r3, [r7, #30]
|
|
if (newsize < MIN_SIZE_ALIGNED) {
|
|
8010f5c: 8bfb ldrh r3, [r7, #30]
|
|
8010f5e: 2b0b cmp r3, #11
|
|
8010f60: d801 bhi.n 8010f66 <mem_trim+0x22>
|
|
/* every data block must be at least MIN_SIZE_ALIGNED long */
|
|
newsize = MIN_SIZE_ALIGNED;
|
|
8010f62: 230c movs r3, #12
|
|
8010f64: 83fb strh r3, [r7, #30]
|
|
}
|
|
#if MEM_OVERFLOW_CHECK
|
|
newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
|
|
#endif
|
|
if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) {
|
|
8010f66: 8bfb ldrh r3, [r7, #30]
|
|
8010f68: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8010f6c: d803 bhi.n 8010f76 <mem_trim+0x32>
|
|
8010f6e: 8bfa ldrh r2, [r7, #30]
|
|
8010f70: 887b ldrh r3, [r7, #2]
|
|
8010f72: 429a cmp r2, r3
|
|
8010f74: d201 bcs.n 8010f7a <mem_trim+0x36>
|
|
return NULL;
|
|
8010f76: 2300 movs r3, #0
|
|
8010f78: e0d8 b.n 801112c <mem_trim+0x1e8>
|
|
}
|
|
|
|
LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram &&
|
|
8010f7a: 4b6e ldr r3, [pc, #440] ; (8011134 <mem_trim+0x1f0>)
|
|
8010f7c: 681b ldr r3, [r3, #0]
|
|
8010f7e: 687a ldr r2, [r7, #4]
|
|
8010f80: 429a cmp r2, r3
|
|
8010f82: d304 bcc.n 8010f8e <mem_trim+0x4a>
|
|
8010f84: 4b6c ldr r3, [pc, #432] ; (8011138 <mem_trim+0x1f4>)
|
|
8010f86: 681b ldr r3, [r3, #0]
|
|
8010f88: 687a ldr r2, [r7, #4]
|
|
8010f8a: 429a cmp r2, r3
|
|
8010f8c: d306 bcc.n 8010f9c <mem_trim+0x58>
|
|
8010f8e: 4b6b ldr r3, [pc, #428] ; (801113c <mem_trim+0x1f8>)
|
|
8010f90: f240 22d2 movw r2, #722 ; 0x2d2
|
|
8010f94: 496a ldr r1, [pc, #424] ; (8011140 <mem_trim+0x1fc>)
|
|
8010f96: 486b ldr r0, [pc, #428] ; (8011144 <mem_trim+0x200>)
|
|
8010f98: f00b fe8e bl 801ccb8 <iprintf>
|
|
(u8_t *)rmem < (u8_t *)ram_end);
|
|
|
|
if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) {
|
|
8010f9c: 4b65 ldr r3, [pc, #404] ; (8011134 <mem_trim+0x1f0>)
|
|
8010f9e: 681b ldr r3, [r3, #0]
|
|
8010fa0: 687a ldr r2, [r7, #4]
|
|
8010fa2: 429a cmp r2, r3
|
|
8010fa4: d304 bcc.n 8010fb0 <mem_trim+0x6c>
|
|
8010fa6: 4b64 ldr r3, [pc, #400] ; (8011138 <mem_trim+0x1f4>)
|
|
8010fa8: 681b ldr r3, [r3, #0]
|
|
8010faa: 687a ldr r2, [r7, #4]
|
|
8010fac: 429a cmp r2, r3
|
|
8010fae: d307 bcc.n 8010fc0 <mem_trim+0x7c>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n"));
|
|
/* protect mem stats from concurrent access */
|
|
MEM_STATS_INC_LOCKED(illegal);
|
|
8010fb0: f00b fe04 bl 801cbbc <sys_arch_protect>
|
|
8010fb4: 60b8 str r0, [r7, #8]
|
|
8010fb6: 68b8 ldr r0, [r7, #8]
|
|
8010fb8: f00b fe0e bl 801cbd8 <sys_arch_unprotect>
|
|
return rmem;
|
|
8010fbc: 687b ldr r3, [r7, #4]
|
|
8010fbe: e0b5 b.n 801112c <mem_trim+0x1e8>
|
|
}
|
|
/* Get the corresponding struct mem ... */
|
|
/* cast through void* to get rid of alignment warnings */
|
|
mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET));
|
|
8010fc0: 687b ldr r3, [r7, #4]
|
|
8010fc2: 3b08 subs r3, #8
|
|
8010fc4: 61bb str r3, [r7, #24]
|
|
#if MEM_OVERFLOW_CHECK
|
|
mem_overflow_check_element(mem);
|
|
#endif
|
|
/* ... and its offset pointer */
|
|
ptr = mem_to_ptr(mem);
|
|
8010fc6: 69b8 ldr r0, [r7, #24]
|
|
8010fc8: f7ff fdea bl 8010ba0 <mem_to_ptr>
|
|
8010fcc: 4603 mov r3, r0
|
|
8010fce: 82fb strh r3, [r7, #22]
|
|
|
|
size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD));
|
|
8010fd0: 69bb ldr r3, [r7, #24]
|
|
8010fd2: 881a ldrh r2, [r3, #0]
|
|
8010fd4: 8afb ldrh r3, [r7, #22]
|
|
8010fd6: 1ad3 subs r3, r2, r3
|
|
8010fd8: b29b uxth r3, r3
|
|
8010fda: 3b08 subs r3, #8
|
|
8010fdc: 82bb strh r3, [r7, #20]
|
|
LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size);
|
|
8010fde: 8bfa ldrh r2, [r7, #30]
|
|
8010fe0: 8abb ldrh r3, [r7, #20]
|
|
8010fe2: 429a cmp r2, r3
|
|
8010fe4: d906 bls.n 8010ff4 <mem_trim+0xb0>
|
|
8010fe6: 4b55 ldr r3, [pc, #340] ; (801113c <mem_trim+0x1f8>)
|
|
8010fe8: f44f 7239 mov.w r2, #740 ; 0x2e4
|
|
8010fec: 4956 ldr r1, [pc, #344] ; (8011148 <mem_trim+0x204>)
|
|
8010fee: 4855 ldr r0, [pc, #340] ; (8011144 <mem_trim+0x200>)
|
|
8010ff0: f00b fe62 bl 801ccb8 <iprintf>
|
|
if (newsize > size) {
|
|
8010ff4: 8bfa ldrh r2, [r7, #30]
|
|
8010ff6: 8abb ldrh r3, [r7, #20]
|
|
8010ff8: 429a cmp r2, r3
|
|
8010ffa: d901 bls.n 8011000 <mem_trim+0xbc>
|
|
/* not supported */
|
|
return NULL;
|
|
8010ffc: 2300 movs r3, #0
|
|
8010ffe: e095 b.n 801112c <mem_trim+0x1e8>
|
|
}
|
|
if (newsize == size) {
|
|
8011000: 8bfa ldrh r2, [r7, #30]
|
|
8011002: 8abb ldrh r3, [r7, #20]
|
|
8011004: 429a cmp r2, r3
|
|
8011006: d101 bne.n 801100c <mem_trim+0xc8>
|
|
/* No change in size, simply return */
|
|
return rmem;
|
|
8011008: 687b ldr r3, [r7, #4]
|
|
801100a: e08f b.n 801112c <mem_trim+0x1e8>
|
|
}
|
|
|
|
/* protect the heap from concurrent access */
|
|
LWIP_MEM_FREE_PROTECT();
|
|
801100c: 484f ldr r0, [pc, #316] ; (801114c <mem_trim+0x208>)
|
|
801100e: f00b fd93 bl 801cb38 <sys_mutex_lock>
|
|
|
|
mem2 = ptr_to_mem(mem->next);
|
|
8011012: 69bb ldr r3, [r7, #24]
|
|
8011014: 881b ldrh r3, [r3, #0]
|
|
8011016: 4618 mov r0, r3
|
|
8011018: f7ff fdb0 bl 8010b7c <ptr_to_mem>
|
|
801101c: 6138 str r0, [r7, #16]
|
|
if (mem2->used == 0) {
|
|
801101e: 693b ldr r3, [r7, #16]
|
|
8011020: 791b ldrb r3, [r3, #4]
|
|
8011022: 2b00 cmp r3, #0
|
|
8011024: d13f bne.n 80110a6 <mem_trim+0x162>
|
|
/* The next struct is unused, we can simply move it at little */
|
|
mem_size_t next;
|
|
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
|
|
8011026: 69bb ldr r3, [r7, #24]
|
|
8011028: 881b ldrh r3, [r3, #0]
|
|
801102a: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
801102e: d106 bne.n 801103e <mem_trim+0xfa>
|
|
8011030: 4b42 ldr r3, [pc, #264] ; (801113c <mem_trim+0x1f8>)
|
|
8011032: f240 22f5 movw r2, #757 ; 0x2f5
|
|
8011036: 4946 ldr r1, [pc, #280] ; (8011150 <mem_trim+0x20c>)
|
|
8011038: 4842 ldr r0, [pc, #264] ; (8011144 <mem_trim+0x200>)
|
|
801103a: f00b fe3d bl 801ccb8 <iprintf>
|
|
/* remember the old next pointer */
|
|
next = mem2->next;
|
|
801103e: 693b ldr r3, [r7, #16]
|
|
8011040: 881b ldrh r3, [r3, #0]
|
|
8011042: 81bb strh r3, [r7, #12]
|
|
/* create new struct mem which is moved directly after the shrinked mem */
|
|
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
|
|
8011044: 8afa ldrh r2, [r7, #22]
|
|
8011046: 8bfb ldrh r3, [r7, #30]
|
|
8011048: 4413 add r3, r2
|
|
801104a: b29b uxth r3, r3
|
|
801104c: 3308 adds r3, #8
|
|
801104e: 81fb strh r3, [r7, #14]
|
|
if (lfree == mem2) {
|
|
8011050: 4b40 ldr r3, [pc, #256] ; (8011154 <mem_trim+0x210>)
|
|
8011052: 681b ldr r3, [r3, #0]
|
|
8011054: 693a ldr r2, [r7, #16]
|
|
8011056: 429a cmp r2, r3
|
|
8011058: d106 bne.n 8011068 <mem_trim+0x124>
|
|
lfree = ptr_to_mem(ptr2);
|
|
801105a: 89fb ldrh r3, [r7, #14]
|
|
801105c: 4618 mov r0, r3
|
|
801105e: f7ff fd8d bl 8010b7c <ptr_to_mem>
|
|
8011062: 4602 mov r2, r0
|
|
8011064: 4b3b ldr r3, [pc, #236] ; (8011154 <mem_trim+0x210>)
|
|
8011066: 601a str r2, [r3, #0]
|
|
}
|
|
mem2 = ptr_to_mem(ptr2);
|
|
8011068: 89fb ldrh r3, [r7, #14]
|
|
801106a: 4618 mov r0, r3
|
|
801106c: f7ff fd86 bl 8010b7c <ptr_to_mem>
|
|
8011070: 6138 str r0, [r7, #16]
|
|
mem2->used = 0;
|
|
8011072: 693b ldr r3, [r7, #16]
|
|
8011074: 2200 movs r2, #0
|
|
8011076: 711a strb r2, [r3, #4]
|
|
/* restore the next pointer */
|
|
mem2->next = next;
|
|
8011078: 693b ldr r3, [r7, #16]
|
|
801107a: 89ba ldrh r2, [r7, #12]
|
|
801107c: 801a strh r2, [r3, #0]
|
|
/* link it back to mem */
|
|
mem2->prev = ptr;
|
|
801107e: 693b ldr r3, [r7, #16]
|
|
8011080: 8afa ldrh r2, [r7, #22]
|
|
8011082: 805a strh r2, [r3, #2]
|
|
/* link mem to it */
|
|
mem->next = ptr2;
|
|
8011084: 69bb ldr r3, [r7, #24]
|
|
8011086: 89fa ldrh r2, [r7, #14]
|
|
8011088: 801a strh r2, [r3, #0]
|
|
/* last thing to restore linked list: as we have moved mem2,
|
|
* let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not
|
|
* the end of the heap */
|
|
if (mem2->next != MEM_SIZE_ALIGNED) {
|
|
801108a: 693b ldr r3, [r7, #16]
|
|
801108c: 881b ldrh r3, [r3, #0]
|
|
801108e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8011092: d047 beq.n 8011124 <mem_trim+0x1e0>
|
|
ptr_to_mem(mem2->next)->prev = ptr2;
|
|
8011094: 693b ldr r3, [r7, #16]
|
|
8011096: 881b ldrh r3, [r3, #0]
|
|
8011098: 4618 mov r0, r3
|
|
801109a: f7ff fd6f bl 8010b7c <ptr_to_mem>
|
|
801109e: 4602 mov r2, r0
|
|
80110a0: 89fb ldrh r3, [r7, #14]
|
|
80110a2: 8053 strh r3, [r2, #2]
|
|
80110a4: e03e b.n 8011124 <mem_trim+0x1e0>
|
|
}
|
|
MEM_STATS_DEC_USED(used, (size - newsize));
|
|
/* no need to plug holes, we've already done that */
|
|
} else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) {
|
|
80110a6: 8bfb ldrh r3, [r7, #30]
|
|
80110a8: f103 0214 add.w r2, r3, #20
|
|
80110ac: 8abb ldrh r3, [r7, #20]
|
|
80110ae: 429a cmp r2, r3
|
|
80110b0: d838 bhi.n 8011124 <mem_trim+0x1e0>
|
|
* Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem
|
|
* ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED').
|
|
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
|
|
* region that couldn't hold data, but when mem->next gets freed,
|
|
* the 2 regions would be combined, resulting in more free memory */
|
|
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize);
|
|
80110b2: 8afa ldrh r2, [r7, #22]
|
|
80110b4: 8bfb ldrh r3, [r7, #30]
|
|
80110b6: 4413 add r3, r2
|
|
80110b8: b29b uxth r3, r3
|
|
80110ba: 3308 adds r3, #8
|
|
80110bc: 81fb strh r3, [r7, #14]
|
|
LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED);
|
|
80110be: 69bb ldr r3, [r7, #24]
|
|
80110c0: 881b ldrh r3, [r3, #0]
|
|
80110c2: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
80110c6: d106 bne.n 80110d6 <mem_trim+0x192>
|
|
80110c8: 4b1c ldr r3, [pc, #112] ; (801113c <mem_trim+0x1f8>)
|
|
80110ca: f240 3216 movw r2, #790 ; 0x316
|
|
80110ce: 4920 ldr r1, [pc, #128] ; (8011150 <mem_trim+0x20c>)
|
|
80110d0: 481c ldr r0, [pc, #112] ; (8011144 <mem_trim+0x200>)
|
|
80110d2: f00b fdf1 bl 801ccb8 <iprintf>
|
|
mem2 = ptr_to_mem(ptr2);
|
|
80110d6: 89fb ldrh r3, [r7, #14]
|
|
80110d8: 4618 mov r0, r3
|
|
80110da: f7ff fd4f bl 8010b7c <ptr_to_mem>
|
|
80110de: 6138 str r0, [r7, #16]
|
|
if (mem2 < lfree) {
|
|
80110e0: 4b1c ldr r3, [pc, #112] ; (8011154 <mem_trim+0x210>)
|
|
80110e2: 681b ldr r3, [r3, #0]
|
|
80110e4: 693a ldr r2, [r7, #16]
|
|
80110e6: 429a cmp r2, r3
|
|
80110e8: d202 bcs.n 80110f0 <mem_trim+0x1ac>
|
|
lfree = mem2;
|
|
80110ea: 4a1a ldr r2, [pc, #104] ; (8011154 <mem_trim+0x210>)
|
|
80110ec: 693b ldr r3, [r7, #16]
|
|
80110ee: 6013 str r3, [r2, #0]
|
|
}
|
|
mem2->used = 0;
|
|
80110f0: 693b ldr r3, [r7, #16]
|
|
80110f2: 2200 movs r2, #0
|
|
80110f4: 711a strb r2, [r3, #4]
|
|
mem2->next = mem->next;
|
|
80110f6: 69bb ldr r3, [r7, #24]
|
|
80110f8: 881a ldrh r2, [r3, #0]
|
|
80110fa: 693b ldr r3, [r7, #16]
|
|
80110fc: 801a strh r2, [r3, #0]
|
|
mem2->prev = ptr;
|
|
80110fe: 693b ldr r3, [r7, #16]
|
|
8011100: 8afa ldrh r2, [r7, #22]
|
|
8011102: 805a strh r2, [r3, #2]
|
|
mem->next = ptr2;
|
|
8011104: 69bb ldr r3, [r7, #24]
|
|
8011106: 89fa ldrh r2, [r7, #14]
|
|
8011108: 801a strh r2, [r3, #0]
|
|
if (mem2->next != MEM_SIZE_ALIGNED) {
|
|
801110a: 693b ldr r3, [r7, #16]
|
|
801110c: 881b ldrh r3, [r3, #0]
|
|
801110e: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8011112: d007 beq.n 8011124 <mem_trim+0x1e0>
|
|
ptr_to_mem(mem2->next)->prev = ptr2;
|
|
8011114: 693b ldr r3, [r7, #16]
|
|
8011116: 881b ldrh r3, [r3, #0]
|
|
8011118: 4618 mov r0, r3
|
|
801111a: f7ff fd2f bl 8010b7c <ptr_to_mem>
|
|
801111e: 4602 mov r2, r0
|
|
8011120: 89fb ldrh r3, [r7, #14]
|
|
8011122: 8053 strh r3, [r2, #2]
|
|
#endif
|
|
MEM_SANITY();
|
|
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
|
mem_free_count = 1;
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
LWIP_MEM_FREE_UNPROTECT();
|
|
8011124: 4809 ldr r0, [pc, #36] ; (801114c <mem_trim+0x208>)
|
|
8011126: f00b fd16 bl 801cb56 <sys_mutex_unlock>
|
|
return rmem;
|
|
801112a: 687b ldr r3, [r7, #4]
|
|
}
|
|
801112c: 4618 mov r0, r3
|
|
801112e: 3720 adds r7, #32
|
|
8011130: 46bd mov sp, r7
|
|
8011132: bd80 pop {r7, pc}
|
|
8011134: 200086e4 .word 0x200086e4
|
|
8011138: 200086e8 .word 0x200086e8
|
|
801113c: 0801e0b4 .word 0x0801e0b4
|
|
8011140: 0801e240 .word 0x0801e240
|
|
8011144: 0801e0fc .word 0x0801e0fc
|
|
8011148: 0801e258 .word 0x0801e258
|
|
801114c: 200086ec .word 0x200086ec
|
|
8011150: 0801e278 .word 0x0801e278
|
|
8011154: 200086f0 .word 0x200086f0
|
|
|
|
08011158 <mem_malloc>:
|
|
*
|
|
* Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT).
|
|
*/
|
|
void *
|
|
mem_malloc(mem_size_t size_in)
|
|
{
|
|
8011158: b580 push {r7, lr}
|
|
801115a: b088 sub sp, #32
|
|
801115c: af00 add r7, sp, #0
|
|
801115e: 4603 mov r3, r0
|
|
8011160: 80fb strh r3, [r7, #6]
|
|
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
|
u8_t local_mem_free_count = 0;
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
LWIP_MEM_ALLOC_DECL_PROTECT();
|
|
|
|
if (size_in == 0) {
|
|
8011162: 88fb ldrh r3, [r7, #6]
|
|
8011164: 2b00 cmp r3, #0
|
|
8011166: d101 bne.n 801116c <mem_malloc+0x14>
|
|
return NULL;
|
|
8011168: 2300 movs r3, #0
|
|
801116a: e0e2 b.n 8011332 <mem_malloc+0x1da>
|
|
}
|
|
|
|
/* Expand the size of the allocated memory region so that we can
|
|
adjust for alignment. */
|
|
size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in);
|
|
801116c: 88fb ldrh r3, [r7, #6]
|
|
801116e: 3303 adds r3, #3
|
|
8011170: b29b uxth r3, r3
|
|
8011172: f023 0303 bic.w r3, r3, #3
|
|
8011176: 83bb strh r3, [r7, #28]
|
|
if (size < MIN_SIZE_ALIGNED) {
|
|
8011178: 8bbb ldrh r3, [r7, #28]
|
|
801117a: 2b0b cmp r3, #11
|
|
801117c: d801 bhi.n 8011182 <mem_malloc+0x2a>
|
|
/* every data block must be at least MIN_SIZE_ALIGNED long */
|
|
size = MIN_SIZE_ALIGNED;
|
|
801117e: 230c movs r3, #12
|
|
8011180: 83bb strh r3, [r7, #28]
|
|
}
|
|
#if MEM_OVERFLOW_CHECK
|
|
size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED;
|
|
#endif
|
|
if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) {
|
|
8011182: 8bbb ldrh r3, [r7, #28]
|
|
8011184: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8011188: d803 bhi.n 8011192 <mem_malloc+0x3a>
|
|
801118a: 8bba ldrh r2, [r7, #28]
|
|
801118c: 88fb ldrh r3, [r7, #6]
|
|
801118e: 429a cmp r2, r3
|
|
8011190: d201 bcs.n 8011196 <mem_malloc+0x3e>
|
|
return NULL;
|
|
8011192: 2300 movs r3, #0
|
|
8011194: e0cd b.n 8011332 <mem_malloc+0x1da>
|
|
}
|
|
|
|
/* protect the heap from concurrent access */
|
|
sys_mutex_lock(&mem_mutex);
|
|
8011196: 4869 ldr r0, [pc, #420] ; (801133c <mem_malloc+0x1e4>)
|
|
8011198: f00b fcce bl 801cb38 <sys_mutex_lock>
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
|
|
/* Scan through the heap searching for a free block that is big enough,
|
|
* beginning with the lowest free block.
|
|
*/
|
|
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
|
|
801119c: 4b68 ldr r3, [pc, #416] ; (8011340 <mem_malloc+0x1e8>)
|
|
801119e: 681b ldr r3, [r3, #0]
|
|
80111a0: 4618 mov r0, r3
|
|
80111a2: f7ff fcfd bl 8010ba0 <mem_to_ptr>
|
|
80111a6: 4603 mov r3, r0
|
|
80111a8: 83fb strh r3, [r7, #30]
|
|
80111aa: e0b7 b.n 801131c <mem_malloc+0x1c4>
|
|
ptr = ptr_to_mem(ptr)->next) {
|
|
mem = ptr_to_mem(ptr);
|
|
80111ac: 8bfb ldrh r3, [r7, #30]
|
|
80111ae: 4618 mov r0, r3
|
|
80111b0: f7ff fce4 bl 8010b7c <ptr_to_mem>
|
|
80111b4: 6178 str r0, [r7, #20]
|
|
local_mem_free_count = 1;
|
|
break;
|
|
}
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
|
|
if ((!mem->used) &&
|
|
80111b6: 697b ldr r3, [r7, #20]
|
|
80111b8: 791b ldrb r3, [r3, #4]
|
|
80111ba: 2b00 cmp r3, #0
|
|
80111bc: f040 80a7 bne.w 801130e <mem_malloc+0x1b6>
|
|
(mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) {
|
|
80111c0: 697b ldr r3, [r7, #20]
|
|
80111c2: 881b ldrh r3, [r3, #0]
|
|
80111c4: 461a mov r2, r3
|
|
80111c6: 8bfb ldrh r3, [r7, #30]
|
|
80111c8: 1ad3 subs r3, r2, r3
|
|
80111ca: f1a3 0208 sub.w r2, r3, #8
|
|
80111ce: 8bbb ldrh r3, [r7, #28]
|
|
if ((!mem->used) &&
|
|
80111d0: 429a cmp r2, r3
|
|
80111d2: f0c0 809c bcc.w 801130e <mem_malloc+0x1b6>
|
|
/* mem is not used and at least perfect fit is possible:
|
|
* mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */
|
|
|
|
if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) {
|
|
80111d6: 697b ldr r3, [r7, #20]
|
|
80111d8: 881b ldrh r3, [r3, #0]
|
|
80111da: 461a mov r2, r3
|
|
80111dc: 8bfb ldrh r3, [r7, #30]
|
|
80111de: 1ad3 subs r3, r2, r3
|
|
80111e0: f1a3 0208 sub.w r2, r3, #8
|
|
80111e4: 8bbb ldrh r3, [r7, #28]
|
|
80111e6: 3314 adds r3, #20
|
|
80111e8: 429a cmp r2, r3
|
|
80111ea: d333 bcc.n 8011254 <mem_malloc+0xfc>
|
|
* struct mem would fit in but no data between mem2 and mem2->next
|
|
* @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty
|
|
* region that couldn't hold data, but when mem->next gets freed,
|
|
* the 2 regions would be combined, resulting in more free memory
|
|
*/
|
|
ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size);
|
|
80111ec: 8bfa ldrh r2, [r7, #30]
|
|
80111ee: 8bbb ldrh r3, [r7, #28]
|
|
80111f0: 4413 add r3, r2
|
|
80111f2: b29b uxth r3, r3
|
|
80111f4: 3308 adds r3, #8
|
|
80111f6: 827b strh r3, [r7, #18]
|
|
LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED);
|
|
80111f8: 8a7b ldrh r3, [r7, #18]
|
|
80111fa: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
80111fe: d106 bne.n 801120e <mem_malloc+0xb6>
|
|
8011200: 4b50 ldr r3, [pc, #320] ; (8011344 <mem_malloc+0x1ec>)
|
|
8011202: f240 3287 movw r2, #903 ; 0x387
|
|
8011206: 4950 ldr r1, [pc, #320] ; (8011348 <mem_malloc+0x1f0>)
|
|
8011208: 4850 ldr r0, [pc, #320] ; (801134c <mem_malloc+0x1f4>)
|
|
801120a: f00b fd55 bl 801ccb8 <iprintf>
|
|
/* create mem2 struct */
|
|
mem2 = ptr_to_mem(ptr2);
|
|
801120e: 8a7b ldrh r3, [r7, #18]
|
|
8011210: 4618 mov r0, r3
|
|
8011212: f7ff fcb3 bl 8010b7c <ptr_to_mem>
|
|
8011216: 60f8 str r0, [r7, #12]
|
|
mem2->used = 0;
|
|
8011218: 68fb ldr r3, [r7, #12]
|
|
801121a: 2200 movs r2, #0
|
|
801121c: 711a strb r2, [r3, #4]
|
|
mem2->next = mem->next;
|
|
801121e: 697b ldr r3, [r7, #20]
|
|
8011220: 881a ldrh r2, [r3, #0]
|
|
8011222: 68fb ldr r3, [r7, #12]
|
|
8011224: 801a strh r2, [r3, #0]
|
|
mem2->prev = ptr;
|
|
8011226: 68fb ldr r3, [r7, #12]
|
|
8011228: 8bfa ldrh r2, [r7, #30]
|
|
801122a: 805a strh r2, [r3, #2]
|
|
/* and insert it between mem and mem->next */
|
|
mem->next = ptr2;
|
|
801122c: 697b ldr r3, [r7, #20]
|
|
801122e: 8a7a ldrh r2, [r7, #18]
|
|
8011230: 801a strh r2, [r3, #0]
|
|
mem->used = 1;
|
|
8011232: 697b ldr r3, [r7, #20]
|
|
8011234: 2201 movs r2, #1
|
|
8011236: 711a strb r2, [r3, #4]
|
|
|
|
if (mem2->next != MEM_SIZE_ALIGNED) {
|
|
8011238: 68fb ldr r3, [r7, #12]
|
|
801123a: 881b ldrh r3, [r3, #0]
|
|
801123c: f5b3 6fc8 cmp.w r3, #1600 ; 0x640
|
|
8011240: d00b beq.n 801125a <mem_malloc+0x102>
|
|
ptr_to_mem(mem2->next)->prev = ptr2;
|
|
8011242: 68fb ldr r3, [r7, #12]
|
|
8011244: 881b ldrh r3, [r3, #0]
|
|
8011246: 4618 mov r0, r3
|
|
8011248: f7ff fc98 bl 8010b7c <ptr_to_mem>
|
|
801124c: 4602 mov r2, r0
|
|
801124e: 8a7b ldrh r3, [r7, #18]
|
|
8011250: 8053 strh r3, [r2, #2]
|
|
8011252: e002 b.n 801125a <mem_malloc+0x102>
|
|
* take care of this).
|
|
* -> near fit or exact fit: do not split, no mem2 creation
|
|
* also can't move mem->next directly behind mem, since mem->next
|
|
* will always be used at this point!
|
|
*/
|
|
mem->used = 1;
|
|
8011254: 697b ldr r3, [r7, #20]
|
|
8011256: 2201 movs r2, #1
|
|
8011258: 711a strb r2, [r3, #4]
|
|
MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem));
|
|
}
|
|
#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
|
|
mem_malloc_adjust_lfree:
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
if (mem == lfree) {
|
|
801125a: 4b39 ldr r3, [pc, #228] ; (8011340 <mem_malloc+0x1e8>)
|
|
801125c: 681b ldr r3, [r3, #0]
|
|
801125e: 697a ldr r2, [r7, #20]
|
|
8011260: 429a cmp r2, r3
|
|
8011262: d127 bne.n 80112b4 <mem_malloc+0x15c>
|
|
struct mem *cur = lfree;
|
|
8011264: 4b36 ldr r3, [pc, #216] ; (8011340 <mem_malloc+0x1e8>)
|
|
8011266: 681b ldr r3, [r3, #0]
|
|
8011268: 61bb str r3, [r7, #24]
|
|
/* Find next free block after mem and update lowest free pointer */
|
|
while (cur->used && cur != ram_end) {
|
|
801126a: e005 b.n 8011278 <mem_malloc+0x120>
|
|
/* If mem_free or mem_trim have run, we have to restart since they
|
|
could have altered our current struct mem or lfree. */
|
|
goto mem_malloc_adjust_lfree;
|
|
}
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
cur = ptr_to_mem(cur->next);
|
|
801126c: 69bb ldr r3, [r7, #24]
|
|
801126e: 881b ldrh r3, [r3, #0]
|
|
8011270: 4618 mov r0, r3
|
|
8011272: f7ff fc83 bl 8010b7c <ptr_to_mem>
|
|
8011276: 61b8 str r0, [r7, #24]
|
|
while (cur->used && cur != ram_end) {
|
|
8011278: 69bb ldr r3, [r7, #24]
|
|
801127a: 791b ldrb r3, [r3, #4]
|
|
801127c: 2b00 cmp r3, #0
|
|
801127e: d004 beq.n 801128a <mem_malloc+0x132>
|
|
8011280: 4b33 ldr r3, [pc, #204] ; (8011350 <mem_malloc+0x1f8>)
|
|
8011282: 681b ldr r3, [r3, #0]
|
|
8011284: 69ba ldr r2, [r7, #24]
|
|
8011286: 429a cmp r2, r3
|
|
8011288: d1f0 bne.n 801126c <mem_malloc+0x114>
|
|
}
|
|
lfree = cur;
|
|
801128a: 4a2d ldr r2, [pc, #180] ; (8011340 <mem_malloc+0x1e8>)
|
|
801128c: 69bb ldr r3, [r7, #24]
|
|
801128e: 6013 str r3, [r2, #0]
|
|
LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used)));
|
|
8011290: 4b2b ldr r3, [pc, #172] ; (8011340 <mem_malloc+0x1e8>)
|
|
8011292: 681a ldr r2, [r3, #0]
|
|
8011294: 4b2e ldr r3, [pc, #184] ; (8011350 <mem_malloc+0x1f8>)
|
|
8011296: 681b ldr r3, [r3, #0]
|
|
8011298: 429a cmp r2, r3
|
|
801129a: d00b beq.n 80112b4 <mem_malloc+0x15c>
|
|
801129c: 4b28 ldr r3, [pc, #160] ; (8011340 <mem_malloc+0x1e8>)
|
|
801129e: 681b ldr r3, [r3, #0]
|
|
80112a0: 791b ldrb r3, [r3, #4]
|
|
80112a2: 2b00 cmp r3, #0
|
|
80112a4: d006 beq.n 80112b4 <mem_malloc+0x15c>
|
|
80112a6: 4b27 ldr r3, [pc, #156] ; (8011344 <mem_malloc+0x1ec>)
|
|
80112a8: f240 32b5 movw r2, #949 ; 0x3b5
|
|
80112ac: 4929 ldr r1, [pc, #164] ; (8011354 <mem_malloc+0x1fc>)
|
|
80112ae: 4827 ldr r0, [pc, #156] ; (801134c <mem_malloc+0x1f4>)
|
|
80112b0: f00b fd02 bl 801ccb8 <iprintf>
|
|
}
|
|
LWIP_MEM_ALLOC_UNPROTECT();
|
|
sys_mutex_unlock(&mem_mutex);
|
|
80112b4: 4821 ldr r0, [pc, #132] ; (801133c <mem_malloc+0x1e4>)
|
|
80112b6: f00b fc4e bl 801cb56 <sys_mutex_unlock>
|
|
LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.",
|
|
80112ba: 8bba ldrh r2, [r7, #28]
|
|
80112bc: 697b ldr r3, [r7, #20]
|
|
80112be: 4413 add r3, r2
|
|
80112c0: 3308 adds r3, #8
|
|
80112c2: 4a23 ldr r2, [pc, #140] ; (8011350 <mem_malloc+0x1f8>)
|
|
80112c4: 6812 ldr r2, [r2, #0]
|
|
80112c6: 4293 cmp r3, r2
|
|
80112c8: d906 bls.n 80112d8 <mem_malloc+0x180>
|
|
80112ca: 4b1e ldr r3, [pc, #120] ; (8011344 <mem_malloc+0x1ec>)
|
|
80112cc: f240 32ba movw r2, #954 ; 0x3ba
|
|
80112d0: 4921 ldr r1, [pc, #132] ; (8011358 <mem_malloc+0x200>)
|
|
80112d2: 481e ldr r0, [pc, #120] ; (801134c <mem_malloc+0x1f4>)
|
|
80112d4: f00b fcf0 bl 801ccb8 <iprintf>
|
|
(mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end);
|
|
LWIP_ASSERT("mem_malloc: allocated memory properly aligned.",
|
|
80112d8: 697b ldr r3, [r7, #20]
|
|
80112da: f003 0303 and.w r3, r3, #3
|
|
80112de: 2b00 cmp r3, #0
|
|
80112e0: d006 beq.n 80112f0 <mem_malloc+0x198>
|
|
80112e2: 4b18 ldr r3, [pc, #96] ; (8011344 <mem_malloc+0x1ec>)
|
|
80112e4: f44f 726f mov.w r2, #956 ; 0x3bc
|
|
80112e8: 491c ldr r1, [pc, #112] ; (801135c <mem_malloc+0x204>)
|
|
80112ea: 4818 ldr r0, [pc, #96] ; (801134c <mem_malloc+0x1f4>)
|
|
80112ec: f00b fce4 bl 801ccb8 <iprintf>
|
|
((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0);
|
|
LWIP_ASSERT("mem_malloc: sanity check alignment",
|
|
80112f0: 697b ldr r3, [r7, #20]
|
|
80112f2: f003 0303 and.w r3, r3, #3
|
|
80112f6: 2b00 cmp r3, #0
|
|
80112f8: d006 beq.n 8011308 <mem_malloc+0x1b0>
|
|
80112fa: 4b12 ldr r3, [pc, #72] ; (8011344 <mem_malloc+0x1ec>)
|
|
80112fc: f240 32be movw r2, #958 ; 0x3be
|
|
8011300: 4917 ldr r1, [pc, #92] ; (8011360 <mem_malloc+0x208>)
|
|
8011302: 4812 ldr r0, [pc, #72] ; (801134c <mem_malloc+0x1f4>)
|
|
8011304: f00b fcd8 bl 801ccb8 <iprintf>
|
|
|
|
#if MEM_OVERFLOW_CHECK
|
|
mem_overflow_init_element(mem, size_in);
|
|
#endif
|
|
MEM_SANITY();
|
|
return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET;
|
|
8011308: 697b ldr r3, [r7, #20]
|
|
801130a: 3308 adds r3, #8
|
|
801130c: e011 b.n 8011332 <mem_malloc+0x1da>
|
|
ptr = ptr_to_mem(ptr)->next) {
|
|
801130e: 8bfb ldrh r3, [r7, #30]
|
|
8011310: 4618 mov r0, r3
|
|
8011312: f7ff fc33 bl 8010b7c <ptr_to_mem>
|
|
8011316: 4603 mov r3, r0
|
|
8011318: 881b ldrh r3, [r3, #0]
|
|
801131a: 83fb strh r3, [r7, #30]
|
|
for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size;
|
|
801131c: 8bfa ldrh r2, [r7, #30]
|
|
801131e: 8bbb ldrh r3, [r7, #28]
|
|
8011320: f5c3 63c8 rsb r3, r3, #1600 ; 0x640
|
|
8011324: 429a cmp r2, r3
|
|
8011326: f4ff af41 bcc.w 80111ac <mem_malloc+0x54>
|
|
/* if we got interrupted by a mem_free, try again */
|
|
} while (local_mem_free_count != 0);
|
|
#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */
|
|
MEM_STATS_INC(err);
|
|
LWIP_MEM_ALLOC_UNPROTECT();
|
|
sys_mutex_unlock(&mem_mutex);
|
|
801132a: 4804 ldr r0, [pc, #16] ; (801133c <mem_malloc+0x1e4>)
|
|
801132c: f00b fc13 bl 801cb56 <sys_mutex_unlock>
|
|
LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size));
|
|
return NULL;
|
|
8011330: 2300 movs r3, #0
|
|
}
|
|
8011332: 4618 mov r0, r3
|
|
8011334: 3720 adds r7, #32
|
|
8011336: 46bd mov sp, r7
|
|
8011338: bd80 pop {r7, pc}
|
|
801133a: bf00 nop
|
|
801133c: 200086ec .word 0x200086ec
|
|
8011340: 200086f0 .word 0x200086f0
|
|
8011344: 0801e0b4 .word 0x0801e0b4
|
|
8011348: 0801e278 .word 0x0801e278
|
|
801134c: 0801e0fc .word 0x0801e0fc
|
|
8011350: 200086e8 .word 0x200086e8
|
|
8011354: 0801e28c .word 0x0801e28c
|
|
8011358: 0801e2a8 .word 0x0801e2a8
|
|
801135c: 0801e2d8 .word 0x0801e2d8
|
|
8011360: 0801e308 .word 0x0801e308
|
|
|
|
08011364 <memp_init_pool>:
|
|
*
|
|
* @param desc pool to initialize
|
|
*/
|
|
void
|
|
memp_init_pool(const struct memp_desc *desc)
|
|
{
|
|
8011364: b480 push {r7}
|
|
8011366: b085 sub sp, #20
|
|
8011368: af00 add r7, sp, #0
|
|
801136a: 6078 str r0, [r7, #4]
|
|
LWIP_UNUSED_ARG(desc);
|
|
#else
|
|
int i;
|
|
struct memp *memp;
|
|
|
|
*desc->tab = NULL;
|
|
801136c: 687b ldr r3, [r7, #4]
|
|
801136e: 689b ldr r3, [r3, #8]
|
|
8011370: 2200 movs r2, #0
|
|
8011372: 601a str r2, [r3, #0]
|
|
memp = (struct memp *)LWIP_MEM_ALIGN(desc->base);
|
|
8011374: 687b ldr r3, [r7, #4]
|
|
8011376: 685b ldr r3, [r3, #4]
|
|
8011378: 3303 adds r3, #3
|
|
801137a: f023 0303 bic.w r3, r3, #3
|
|
801137e: 60bb str r3, [r7, #8]
|
|
+ MEM_SANITY_REGION_AFTER_ALIGNED
|
|
#endif
|
|
));
|
|
#endif
|
|
/* create a linked list of memp elements */
|
|
for (i = 0; i < desc->num; ++i) {
|
|
8011380: 2300 movs r3, #0
|
|
8011382: 60fb str r3, [r7, #12]
|
|
8011384: e011 b.n 80113aa <memp_init_pool+0x46>
|
|
memp->next = *desc->tab;
|
|
8011386: 687b ldr r3, [r7, #4]
|
|
8011388: 689b ldr r3, [r3, #8]
|
|
801138a: 681a ldr r2, [r3, #0]
|
|
801138c: 68bb ldr r3, [r7, #8]
|
|
801138e: 601a str r2, [r3, #0]
|
|
*desc->tab = memp;
|
|
8011390: 687b ldr r3, [r7, #4]
|
|
8011392: 689b ldr r3, [r3, #8]
|
|
8011394: 68ba ldr r2, [r7, #8]
|
|
8011396: 601a str r2, [r3, #0]
|
|
#if MEMP_OVERFLOW_CHECK
|
|
memp_overflow_init_element(memp, desc);
|
|
#endif /* MEMP_OVERFLOW_CHECK */
|
|
/* cast through void* to get rid of alignment warnings */
|
|
memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size
|
|
8011398: 687b ldr r3, [r7, #4]
|
|
801139a: 881b ldrh r3, [r3, #0]
|
|
801139c: 461a mov r2, r3
|
|
801139e: 68bb ldr r3, [r7, #8]
|
|
80113a0: 4413 add r3, r2
|
|
80113a2: 60bb str r3, [r7, #8]
|
|
for (i = 0; i < desc->num; ++i) {
|
|
80113a4: 68fb ldr r3, [r7, #12]
|
|
80113a6: 3301 adds r3, #1
|
|
80113a8: 60fb str r3, [r7, #12]
|
|
80113aa: 687b ldr r3, [r7, #4]
|
|
80113ac: 885b ldrh r3, [r3, #2]
|
|
80113ae: 461a mov r2, r3
|
|
80113b0: 68fb ldr r3, [r7, #12]
|
|
80113b2: 4293 cmp r3, r2
|
|
80113b4: dbe7 blt.n 8011386 <memp_init_pool+0x22>
|
|
#endif /* !MEMP_MEM_MALLOC */
|
|
|
|
#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY)
|
|
desc->stats->name = desc->desc;
|
|
#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */
|
|
}
|
|
80113b6: bf00 nop
|
|
80113b8: 3714 adds r7, #20
|
|
80113ba: 46bd mov sp, r7
|
|
80113bc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80113c0: 4770 bx lr
|
|
...
|
|
|
|
080113c4 <memp_init>:
|
|
*
|
|
* Carves out memp_memory into linked lists for each pool-type.
|
|
*/
|
|
void
|
|
memp_init(void)
|
|
{
|
|
80113c4: b580 push {r7, lr}
|
|
80113c6: b082 sub sp, #8
|
|
80113c8: af00 add r7, sp, #0
|
|
u16_t i;
|
|
|
|
/* for every pool: */
|
|
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
|
|
80113ca: 2300 movs r3, #0
|
|
80113cc: 80fb strh r3, [r7, #6]
|
|
80113ce: e009 b.n 80113e4 <memp_init+0x20>
|
|
memp_init_pool(memp_pools[i]);
|
|
80113d0: 88fb ldrh r3, [r7, #6]
|
|
80113d2: 4a08 ldr r2, [pc, #32] ; (80113f4 <memp_init+0x30>)
|
|
80113d4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80113d8: 4618 mov r0, r3
|
|
80113da: f7ff ffc3 bl 8011364 <memp_init_pool>
|
|
for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) {
|
|
80113de: 88fb ldrh r3, [r7, #6]
|
|
80113e0: 3301 adds r3, #1
|
|
80113e2: 80fb strh r3, [r7, #6]
|
|
80113e4: 88fb ldrh r3, [r7, #6]
|
|
80113e6: 2b0c cmp r3, #12
|
|
80113e8: d9f2 bls.n 80113d0 <memp_init+0xc>
|
|
|
|
#if MEMP_OVERFLOW_CHECK >= 2
|
|
/* check everything a first time to see if it worked */
|
|
memp_overflow_check_all();
|
|
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
|
|
}
|
|
80113ea: bf00 nop
|
|
80113ec: 3708 adds r7, #8
|
|
80113ee: 46bd mov sp, r7
|
|
80113f0: bd80 pop {r7, pc}
|
|
80113f2: bf00 nop
|
|
80113f4: 08022de4 .word 0x08022de4
|
|
|
|
080113f8 <do_memp_malloc_pool>:
|
|
#if !MEMP_OVERFLOW_CHECK
|
|
do_memp_malloc_pool(const struct memp_desc *desc)
|
|
#else
|
|
do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line)
|
|
#endif
|
|
{
|
|
80113f8: b580 push {r7, lr}
|
|
80113fa: b084 sub sp, #16
|
|
80113fc: af00 add r7, sp, #0
|
|
80113fe: 6078 str r0, [r7, #4]
|
|
|
|
#if MEMP_MEM_MALLOC
|
|
memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size));
|
|
SYS_ARCH_PROTECT(old_level);
|
|
#else /* MEMP_MEM_MALLOC */
|
|
SYS_ARCH_PROTECT(old_level);
|
|
8011400: f00b fbdc bl 801cbbc <sys_arch_protect>
|
|
8011404: 60f8 str r0, [r7, #12]
|
|
|
|
memp = *desc->tab;
|
|
8011406: 687b ldr r3, [r7, #4]
|
|
8011408: 689b ldr r3, [r3, #8]
|
|
801140a: 681b ldr r3, [r3, #0]
|
|
801140c: 60bb str r3, [r7, #8]
|
|
#endif /* MEMP_MEM_MALLOC */
|
|
|
|
if (memp != NULL) {
|
|
801140e: 68bb ldr r3, [r7, #8]
|
|
8011410: 2b00 cmp r3, #0
|
|
8011412: d015 beq.n 8011440 <do_memp_malloc_pool+0x48>
|
|
#if !MEMP_MEM_MALLOC
|
|
#if MEMP_OVERFLOW_CHECK == 1
|
|
memp_overflow_check_element(memp, desc);
|
|
#endif /* MEMP_OVERFLOW_CHECK */
|
|
|
|
*desc->tab = memp->next;
|
|
8011414: 687b ldr r3, [r7, #4]
|
|
8011416: 689b ldr r3, [r3, #8]
|
|
8011418: 68ba ldr r2, [r7, #8]
|
|
801141a: 6812 ldr r2, [r2, #0]
|
|
801141c: 601a str r2, [r3, #0]
|
|
memp->line = line;
|
|
#if MEMP_MEM_MALLOC
|
|
memp_overflow_init_element(memp, desc);
|
|
#endif /* MEMP_MEM_MALLOC */
|
|
#endif /* MEMP_OVERFLOW_CHECK */
|
|
LWIP_ASSERT("memp_malloc: memp properly aligned",
|
|
801141e: 68bb ldr r3, [r7, #8]
|
|
8011420: f003 0303 and.w r3, r3, #3
|
|
8011424: 2b00 cmp r3, #0
|
|
8011426: d006 beq.n 8011436 <do_memp_malloc_pool+0x3e>
|
|
8011428: 4b09 ldr r3, [pc, #36] ; (8011450 <do_memp_malloc_pool+0x58>)
|
|
801142a: f240 1219 movw r2, #281 ; 0x119
|
|
801142e: 4909 ldr r1, [pc, #36] ; (8011454 <do_memp_malloc_pool+0x5c>)
|
|
8011430: 4809 ldr r0, [pc, #36] ; (8011458 <do_memp_malloc_pool+0x60>)
|
|
8011432: f00b fc41 bl 801ccb8 <iprintf>
|
|
desc->stats->used++;
|
|
if (desc->stats->used > desc->stats->max) {
|
|
desc->stats->max = desc->stats->used;
|
|
}
|
|
#endif
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
8011436: 68f8 ldr r0, [r7, #12]
|
|
8011438: f00b fbce bl 801cbd8 <sys_arch_unprotect>
|
|
/* cast through u8_t* to get rid of alignment warnings */
|
|
return ((u8_t *)memp + MEMP_SIZE);
|
|
801143c: 68bb ldr r3, [r7, #8]
|
|
801143e: e003 b.n 8011448 <do_memp_malloc_pool+0x50>
|
|
} else {
|
|
#if MEMP_STATS
|
|
desc->stats->err++;
|
|
#endif
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
8011440: 68f8 ldr r0, [r7, #12]
|
|
8011442: f00b fbc9 bl 801cbd8 <sys_arch_unprotect>
|
|
LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc));
|
|
}
|
|
|
|
return NULL;
|
|
8011446: 2300 movs r3, #0
|
|
}
|
|
8011448: 4618 mov r0, r3
|
|
801144a: 3710 adds r7, #16
|
|
801144c: 46bd mov sp, r7
|
|
801144e: bd80 pop {r7, pc}
|
|
8011450: 0801e32c .word 0x0801e32c
|
|
8011454: 0801e35c .word 0x0801e35c
|
|
8011458: 0801e380 .word 0x0801e380
|
|
|
|
0801145c <memp_malloc>:
|
|
#if !MEMP_OVERFLOW_CHECK
|
|
memp_malloc(memp_t type)
|
|
#else
|
|
memp_malloc_fn(memp_t type, const char *file, const int line)
|
|
#endif
|
|
{
|
|
801145c: b580 push {r7, lr}
|
|
801145e: b084 sub sp, #16
|
|
8011460: af00 add r7, sp, #0
|
|
8011462: 4603 mov r3, r0
|
|
8011464: 71fb strb r3, [r7, #7]
|
|
void *memp;
|
|
LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;);
|
|
8011466: 79fb ldrb r3, [r7, #7]
|
|
8011468: 2b0c cmp r3, #12
|
|
801146a: d908 bls.n 801147e <memp_malloc+0x22>
|
|
801146c: 4b0a ldr r3, [pc, #40] ; (8011498 <memp_malloc+0x3c>)
|
|
801146e: f240 1257 movw r2, #343 ; 0x157
|
|
8011472: 490a ldr r1, [pc, #40] ; (801149c <memp_malloc+0x40>)
|
|
8011474: 480a ldr r0, [pc, #40] ; (80114a0 <memp_malloc+0x44>)
|
|
8011476: f00b fc1f bl 801ccb8 <iprintf>
|
|
801147a: 2300 movs r3, #0
|
|
801147c: e008 b.n 8011490 <memp_malloc+0x34>
|
|
#if MEMP_OVERFLOW_CHECK >= 2
|
|
memp_overflow_check_all();
|
|
#endif /* MEMP_OVERFLOW_CHECK >= 2 */
|
|
|
|
#if !MEMP_OVERFLOW_CHECK
|
|
memp = do_memp_malloc_pool(memp_pools[type]);
|
|
801147e: 79fb ldrb r3, [r7, #7]
|
|
8011480: 4a08 ldr r2, [pc, #32] ; (80114a4 <memp_malloc+0x48>)
|
|
8011482: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8011486: 4618 mov r0, r3
|
|
8011488: f7ff ffb6 bl 80113f8 <do_memp_malloc_pool>
|
|
801148c: 60f8 str r0, [r7, #12]
|
|
#else
|
|
memp = do_memp_malloc_pool_fn(memp_pools[type], file, line);
|
|
#endif
|
|
|
|
return memp;
|
|
801148e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8011490: 4618 mov r0, r3
|
|
8011492: 3710 adds r7, #16
|
|
8011494: 46bd mov sp, r7
|
|
8011496: bd80 pop {r7, pc}
|
|
8011498: 0801e32c .word 0x0801e32c
|
|
801149c: 0801e3bc .word 0x0801e3bc
|
|
80114a0: 0801e380 .word 0x0801e380
|
|
80114a4: 08022de4 .word 0x08022de4
|
|
|
|
080114a8 <do_memp_free_pool>:
|
|
|
|
static void
|
|
do_memp_free_pool(const struct memp_desc *desc, void *mem)
|
|
{
|
|
80114a8: b580 push {r7, lr}
|
|
80114aa: b084 sub sp, #16
|
|
80114ac: af00 add r7, sp, #0
|
|
80114ae: 6078 str r0, [r7, #4]
|
|
80114b0: 6039 str r1, [r7, #0]
|
|
struct memp *memp;
|
|
SYS_ARCH_DECL_PROTECT(old_level);
|
|
|
|
LWIP_ASSERT("memp_free: mem properly aligned",
|
|
80114b2: 683b ldr r3, [r7, #0]
|
|
80114b4: f003 0303 and.w r3, r3, #3
|
|
80114b8: 2b00 cmp r3, #0
|
|
80114ba: d006 beq.n 80114ca <do_memp_free_pool+0x22>
|
|
80114bc: 4b0d ldr r3, [pc, #52] ; (80114f4 <do_memp_free_pool+0x4c>)
|
|
80114be: f240 126d movw r2, #365 ; 0x16d
|
|
80114c2: 490d ldr r1, [pc, #52] ; (80114f8 <do_memp_free_pool+0x50>)
|
|
80114c4: 480d ldr r0, [pc, #52] ; (80114fc <do_memp_free_pool+0x54>)
|
|
80114c6: f00b fbf7 bl 801ccb8 <iprintf>
|
|
((mem_ptr_t)mem % MEM_ALIGNMENT) == 0);
|
|
|
|
/* cast through void* to get rid of alignment warnings */
|
|
memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE);
|
|
80114ca: 683b ldr r3, [r7, #0]
|
|
80114cc: 60fb str r3, [r7, #12]
|
|
|
|
SYS_ARCH_PROTECT(old_level);
|
|
80114ce: f00b fb75 bl 801cbbc <sys_arch_protect>
|
|
80114d2: 60b8 str r0, [r7, #8]
|
|
#if MEMP_MEM_MALLOC
|
|
LWIP_UNUSED_ARG(desc);
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
mem_free(memp);
|
|
#else /* MEMP_MEM_MALLOC */
|
|
memp->next = *desc->tab;
|
|
80114d4: 687b ldr r3, [r7, #4]
|
|
80114d6: 689b ldr r3, [r3, #8]
|
|
80114d8: 681a ldr r2, [r3, #0]
|
|
80114da: 68fb ldr r3, [r7, #12]
|
|
80114dc: 601a str r2, [r3, #0]
|
|
*desc->tab = memp;
|
|
80114de: 687b ldr r3, [r7, #4]
|
|
80114e0: 689b ldr r3, [r3, #8]
|
|
80114e2: 68fa ldr r2, [r7, #12]
|
|
80114e4: 601a str r2, [r3, #0]
|
|
|
|
#if MEMP_SANITY_CHECK
|
|
LWIP_ASSERT("memp sanity", memp_sanity(desc));
|
|
#endif /* MEMP_SANITY_CHECK */
|
|
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
80114e6: 68b8 ldr r0, [r7, #8]
|
|
80114e8: f00b fb76 bl 801cbd8 <sys_arch_unprotect>
|
|
#endif /* !MEMP_MEM_MALLOC */
|
|
}
|
|
80114ec: bf00 nop
|
|
80114ee: 3710 adds r7, #16
|
|
80114f0: 46bd mov sp, r7
|
|
80114f2: bd80 pop {r7, pc}
|
|
80114f4: 0801e32c .word 0x0801e32c
|
|
80114f8: 0801e3dc .word 0x0801e3dc
|
|
80114fc: 0801e380 .word 0x0801e380
|
|
|
|
08011500 <memp_free>:
|
|
* @param type the pool where to put mem
|
|
* @param mem the memp element to free
|
|
*/
|
|
void
|
|
memp_free(memp_t type, void *mem)
|
|
{
|
|
8011500: b580 push {r7, lr}
|
|
8011502: b082 sub sp, #8
|
|
8011504: af00 add r7, sp, #0
|
|
8011506: 4603 mov r3, r0
|
|
8011508: 6039 str r1, [r7, #0]
|
|
801150a: 71fb strb r3, [r7, #7]
|
|
#ifdef LWIP_HOOK_MEMP_AVAILABLE
|
|
struct memp *old_first;
|
|
#endif
|
|
|
|
LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;);
|
|
801150c: 79fb ldrb r3, [r7, #7]
|
|
801150e: 2b0c cmp r3, #12
|
|
8011510: d907 bls.n 8011522 <memp_free+0x22>
|
|
8011512: 4b0c ldr r3, [pc, #48] ; (8011544 <memp_free+0x44>)
|
|
8011514: f44f 72d5 mov.w r2, #426 ; 0x1aa
|
|
8011518: 490b ldr r1, [pc, #44] ; (8011548 <memp_free+0x48>)
|
|
801151a: 480c ldr r0, [pc, #48] ; (801154c <memp_free+0x4c>)
|
|
801151c: f00b fbcc bl 801ccb8 <iprintf>
|
|
8011520: e00c b.n 801153c <memp_free+0x3c>
|
|
|
|
if (mem == NULL) {
|
|
8011522: 683b ldr r3, [r7, #0]
|
|
8011524: 2b00 cmp r3, #0
|
|
8011526: d008 beq.n 801153a <memp_free+0x3a>
|
|
|
|
#ifdef LWIP_HOOK_MEMP_AVAILABLE
|
|
old_first = *memp_pools[type]->tab;
|
|
#endif
|
|
|
|
do_memp_free_pool(memp_pools[type], mem);
|
|
8011528: 79fb ldrb r3, [r7, #7]
|
|
801152a: 4a09 ldr r2, [pc, #36] ; (8011550 <memp_free+0x50>)
|
|
801152c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8011530: 6839 ldr r1, [r7, #0]
|
|
8011532: 4618 mov r0, r3
|
|
8011534: f7ff ffb8 bl 80114a8 <do_memp_free_pool>
|
|
8011538: e000 b.n 801153c <memp_free+0x3c>
|
|
return;
|
|
801153a: bf00 nop
|
|
#ifdef LWIP_HOOK_MEMP_AVAILABLE
|
|
if (old_first == NULL) {
|
|
LWIP_HOOK_MEMP_AVAILABLE(type);
|
|
}
|
|
#endif
|
|
}
|
|
801153c: 3708 adds r7, #8
|
|
801153e: 46bd mov sp, r7
|
|
8011540: bd80 pop {r7, pc}
|
|
8011542: bf00 nop
|
|
8011544: 0801e32c .word 0x0801e32c
|
|
8011548: 0801e3fc .word 0x0801e3fc
|
|
801154c: 0801e380 .word 0x0801e380
|
|
8011550: 08022de4 .word 0x08022de4
|
|
|
|
08011554 <netif_init>:
|
|
}
|
|
#endif /* LWIP_HAVE_LOOPIF */
|
|
|
|
void
|
|
netif_init(void)
|
|
{
|
|
8011554: b480 push {r7}
|
|
8011556: af00 add r7, sp, #0
|
|
|
|
netif_set_link_up(&loop_netif);
|
|
netif_set_up(&loop_netif);
|
|
|
|
#endif /* LWIP_HAVE_LOOPIF */
|
|
}
|
|
8011558: bf00 nop
|
|
801155a: 46bd mov sp, r7
|
|
801155c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011560: 4770 bx lr
|
|
...
|
|
|
|
08011564 <netif_add>:
|
|
netif_add(struct netif *netif,
|
|
#if LWIP_IPV4
|
|
const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw,
|
|
#endif /* LWIP_IPV4 */
|
|
void *state, netif_init_fn init, netif_input_fn input)
|
|
{
|
|
8011564: b580 push {r7, lr}
|
|
8011566: b086 sub sp, #24
|
|
8011568: af00 add r7, sp, #0
|
|
801156a: 60f8 str r0, [r7, #12]
|
|
801156c: 60b9 str r1, [r7, #8]
|
|
801156e: 607a str r2, [r7, #4]
|
|
8011570: 603b str r3, [r7, #0]
|
|
LWIP_ASSERT("single netif already set", 0);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL);
|
|
8011572: 68fb ldr r3, [r7, #12]
|
|
8011574: 2b00 cmp r3, #0
|
|
8011576: d108 bne.n 801158a <netif_add+0x26>
|
|
8011578: 4b5b ldr r3, [pc, #364] ; (80116e8 <netif_add+0x184>)
|
|
801157a: f240 1227 movw r2, #295 ; 0x127
|
|
801157e: 495b ldr r1, [pc, #364] ; (80116ec <netif_add+0x188>)
|
|
8011580: 485b ldr r0, [pc, #364] ; (80116f0 <netif_add+0x18c>)
|
|
8011582: f00b fb99 bl 801ccb8 <iprintf>
|
|
8011586: 2300 movs r3, #0
|
|
8011588: e0a9 b.n 80116de <netif_add+0x17a>
|
|
LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL);
|
|
801158a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801158c: 2b00 cmp r3, #0
|
|
801158e: d108 bne.n 80115a2 <netif_add+0x3e>
|
|
8011590: 4b55 ldr r3, [pc, #340] ; (80116e8 <netif_add+0x184>)
|
|
8011592: f44f 7294 mov.w r2, #296 ; 0x128
|
|
8011596: 4957 ldr r1, [pc, #348] ; (80116f4 <netif_add+0x190>)
|
|
8011598: 4855 ldr r0, [pc, #340] ; (80116f0 <netif_add+0x18c>)
|
|
801159a: f00b fb8d bl 801ccb8 <iprintf>
|
|
801159e: 2300 movs r3, #0
|
|
80115a0: e09d b.n 80116de <netif_add+0x17a>
|
|
|
|
#if LWIP_IPV4
|
|
if (ipaddr == NULL) {
|
|
80115a2: 68bb ldr r3, [r7, #8]
|
|
80115a4: 2b00 cmp r3, #0
|
|
80115a6: d101 bne.n 80115ac <netif_add+0x48>
|
|
ipaddr = ip_2_ip4(IP4_ADDR_ANY);
|
|
80115a8: 4b53 ldr r3, [pc, #332] ; (80116f8 <netif_add+0x194>)
|
|
80115aa: 60bb str r3, [r7, #8]
|
|
}
|
|
if (netmask == NULL) {
|
|
80115ac: 687b ldr r3, [r7, #4]
|
|
80115ae: 2b00 cmp r3, #0
|
|
80115b0: d101 bne.n 80115b6 <netif_add+0x52>
|
|
netmask = ip_2_ip4(IP4_ADDR_ANY);
|
|
80115b2: 4b51 ldr r3, [pc, #324] ; (80116f8 <netif_add+0x194>)
|
|
80115b4: 607b str r3, [r7, #4]
|
|
}
|
|
if (gw == NULL) {
|
|
80115b6: 683b ldr r3, [r7, #0]
|
|
80115b8: 2b00 cmp r3, #0
|
|
80115ba: d101 bne.n 80115c0 <netif_add+0x5c>
|
|
gw = ip_2_ip4(IP4_ADDR_ANY);
|
|
80115bc: 4b4e ldr r3, [pc, #312] ; (80116f8 <netif_add+0x194>)
|
|
80115be: 603b str r3, [r7, #0]
|
|
}
|
|
|
|
/* reset new interface configuration state */
|
|
ip_addr_set_zero_ip4(&netif->ip_addr);
|
|
80115c0: 68fb ldr r3, [r7, #12]
|
|
80115c2: 2200 movs r2, #0
|
|
80115c4: 605a str r2, [r3, #4]
|
|
ip_addr_set_zero_ip4(&netif->netmask);
|
|
80115c6: 68fb ldr r3, [r7, #12]
|
|
80115c8: 2200 movs r2, #0
|
|
80115ca: 609a str r2, [r3, #8]
|
|
ip_addr_set_zero_ip4(&netif->gw);
|
|
80115cc: 68fb ldr r3, [r7, #12]
|
|
80115ce: 2200 movs r2, #0
|
|
80115d0: 60da str r2, [r3, #12]
|
|
netif->output = netif_null_output_ip4;
|
|
80115d2: 68fb ldr r3, [r7, #12]
|
|
80115d4: 4a49 ldr r2, [pc, #292] ; (80116fc <netif_add+0x198>)
|
|
80115d6: 615a str r2, [r3, #20]
|
|
#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */
|
|
}
|
|
netif->output_ip6 = netif_null_output_ip6;
|
|
#endif /* LWIP_IPV6 */
|
|
NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL);
|
|
netif->mtu = 0;
|
|
80115d8: 68fb ldr r3, [r7, #12]
|
|
80115da: 2200 movs r2, #0
|
|
80115dc: 851a strh r2, [r3, #40] ; 0x28
|
|
netif->flags = 0;
|
|
80115de: 68fb ldr r3, [r7, #12]
|
|
80115e0: 2200 movs r2, #0
|
|
80115e2: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
#ifdef netif_get_client_data
|
|
memset(netif->client_data, 0, sizeof(netif->client_data));
|
|
80115e6: 68fb ldr r3, [r7, #12]
|
|
80115e8: 3324 adds r3, #36 ; 0x24
|
|
80115ea: 2204 movs r2, #4
|
|
80115ec: 2100 movs r1, #0
|
|
80115ee: 4618 mov r0, r3
|
|
80115f0: f00b fb59 bl 801cca6 <memset>
|
|
#endif /* LWIP_IPV6 */
|
|
#if LWIP_NETIF_STATUS_CALLBACK
|
|
netif->status_callback = NULL;
|
|
#endif /* LWIP_NETIF_STATUS_CALLBACK */
|
|
#if LWIP_NETIF_LINK_CALLBACK
|
|
netif->link_callback = NULL;
|
|
80115f4: 68fb ldr r3, [r7, #12]
|
|
80115f6: 2200 movs r2, #0
|
|
80115f8: 61da str r2, [r3, #28]
|
|
netif->loop_first = NULL;
|
|
netif->loop_last = NULL;
|
|
#endif /* ENABLE_LOOPBACK */
|
|
|
|
/* remember netif specific state information data */
|
|
netif->state = state;
|
|
80115fa: 68fb ldr r3, [r7, #12]
|
|
80115fc: 6a3a ldr r2, [r7, #32]
|
|
80115fe: 621a str r2, [r3, #32]
|
|
netif->num = netif_num;
|
|
8011600: 4b3f ldr r3, [pc, #252] ; (8011700 <netif_add+0x19c>)
|
|
8011602: 781a ldrb r2, [r3, #0]
|
|
8011604: 68fb ldr r3, [r7, #12]
|
|
8011606: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
netif->input = input;
|
|
801160a: 68fb ldr r3, [r7, #12]
|
|
801160c: 6aba ldr r2, [r7, #40] ; 0x28
|
|
801160e: 611a str r2, [r3, #16]
|
|
#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS
|
|
netif->loop_cnt_current = 0;
|
|
#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */
|
|
|
|
#if LWIP_IPV4
|
|
netif_set_addr(netif, ipaddr, netmask, gw);
|
|
8011610: 683b ldr r3, [r7, #0]
|
|
8011612: 687a ldr r2, [r7, #4]
|
|
8011614: 68b9 ldr r1, [r7, #8]
|
|
8011616: 68f8 ldr r0, [r7, #12]
|
|
8011618: f000 f914 bl 8011844 <netif_set_addr>
|
|
#endif /* LWIP_IPV4 */
|
|
|
|
/* call user specified initialization function for netif */
|
|
if (init(netif) != ERR_OK) {
|
|
801161c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801161e: 68f8 ldr r0, [r7, #12]
|
|
8011620: 4798 blx r3
|
|
8011622: 4603 mov r3, r0
|
|
8011624: 2b00 cmp r3, #0
|
|
8011626: d001 beq.n 801162c <netif_add+0xc8>
|
|
return NULL;
|
|
8011628: 2300 movs r3, #0
|
|
801162a: e058 b.n 80116de <netif_add+0x17a>
|
|
*/
|
|
{
|
|
struct netif *netif2;
|
|
int num_netifs;
|
|
do {
|
|
if (netif->num == 255) {
|
|
801162c: 68fb ldr r3, [r7, #12]
|
|
801162e: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8011632: 2bff cmp r3, #255 ; 0xff
|
|
8011634: d103 bne.n 801163e <netif_add+0xda>
|
|
netif->num = 0;
|
|
8011636: 68fb ldr r3, [r7, #12]
|
|
8011638: 2200 movs r2, #0
|
|
801163a: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
}
|
|
num_netifs = 0;
|
|
801163e: 2300 movs r3, #0
|
|
8011640: 613b str r3, [r7, #16]
|
|
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
|
|
8011642: 4b30 ldr r3, [pc, #192] ; (8011704 <netif_add+0x1a0>)
|
|
8011644: 681b ldr r3, [r3, #0]
|
|
8011646: 617b str r3, [r7, #20]
|
|
8011648: e02b b.n 80116a2 <netif_add+0x13e>
|
|
LWIP_ASSERT("netif already added", netif2 != netif);
|
|
801164a: 697a ldr r2, [r7, #20]
|
|
801164c: 68fb ldr r3, [r7, #12]
|
|
801164e: 429a cmp r2, r3
|
|
8011650: d106 bne.n 8011660 <netif_add+0xfc>
|
|
8011652: 4b25 ldr r3, [pc, #148] ; (80116e8 <netif_add+0x184>)
|
|
8011654: f240 128b movw r2, #395 ; 0x18b
|
|
8011658: 492b ldr r1, [pc, #172] ; (8011708 <netif_add+0x1a4>)
|
|
801165a: 4825 ldr r0, [pc, #148] ; (80116f0 <netif_add+0x18c>)
|
|
801165c: f00b fb2c bl 801ccb8 <iprintf>
|
|
num_netifs++;
|
|
8011660: 693b ldr r3, [r7, #16]
|
|
8011662: 3301 adds r3, #1
|
|
8011664: 613b str r3, [r7, #16]
|
|
LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255);
|
|
8011666: 693b ldr r3, [r7, #16]
|
|
8011668: 2bff cmp r3, #255 ; 0xff
|
|
801166a: dd06 ble.n 801167a <netif_add+0x116>
|
|
801166c: 4b1e ldr r3, [pc, #120] ; (80116e8 <netif_add+0x184>)
|
|
801166e: f240 128d movw r2, #397 ; 0x18d
|
|
8011672: 4926 ldr r1, [pc, #152] ; (801170c <netif_add+0x1a8>)
|
|
8011674: 481e ldr r0, [pc, #120] ; (80116f0 <netif_add+0x18c>)
|
|
8011676: f00b fb1f bl 801ccb8 <iprintf>
|
|
if (netif2->num == netif->num) {
|
|
801167a: 697b ldr r3, [r7, #20]
|
|
801167c: f893 2034 ldrb.w r2, [r3, #52] ; 0x34
|
|
8011680: 68fb ldr r3, [r7, #12]
|
|
8011682: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8011686: 429a cmp r2, r3
|
|
8011688: d108 bne.n 801169c <netif_add+0x138>
|
|
netif->num++;
|
|
801168a: 68fb ldr r3, [r7, #12]
|
|
801168c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8011690: 3301 adds r3, #1
|
|
8011692: b2da uxtb r2, r3
|
|
8011694: 68fb ldr r3, [r7, #12]
|
|
8011696: f883 2034 strb.w r2, [r3, #52] ; 0x34
|
|
break;
|
|
801169a: e005 b.n 80116a8 <netif_add+0x144>
|
|
for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) {
|
|
801169c: 697b ldr r3, [r7, #20]
|
|
801169e: 681b ldr r3, [r3, #0]
|
|
80116a0: 617b str r3, [r7, #20]
|
|
80116a2: 697b ldr r3, [r7, #20]
|
|
80116a4: 2b00 cmp r3, #0
|
|
80116a6: d1d0 bne.n 801164a <netif_add+0xe6>
|
|
}
|
|
}
|
|
} while (netif2 != NULL);
|
|
80116a8: 697b ldr r3, [r7, #20]
|
|
80116aa: 2b00 cmp r3, #0
|
|
80116ac: d1be bne.n 801162c <netif_add+0xc8>
|
|
}
|
|
if (netif->num == 254) {
|
|
80116ae: 68fb ldr r3, [r7, #12]
|
|
80116b0: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
80116b4: 2bfe cmp r3, #254 ; 0xfe
|
|
80116b6: d103 bne.n 80116c0 <netif_add+0x15c>
|
|
netif_num = 0;
|
|
80116b8: 4b11 ldr r3, [pc, #68] ; (8011700 <netif_add+0x19c>)
|
|
80116ba: 2200 movs r2, #0
|
|
80116bc: 701a strb r2, [r3, #0]
|
|
80116be: e006 b.n 80116ce <netif_add+0x16a>
|
|
} else {
|
|
netif_num = (u8_t)(netif->num + 1);
|
|
80116c0: 68fb ldr r3, [r7, #12]
|
|
80116c2: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
80116c6: 3301 adds r3, #1
|
|
80116c8: b2da uxtb r2, r3
|
|
80116ca: 4b0d ldr r3, [pc, #52] ; (8011700 <netif_add+0x19c>)
|
|
80116cc: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* add this netif to the list */
|
|
netif->next = netif_list;
|
|
80116ce: 4b0d ldr r3, [pc, #52] ; (8011704 <netif_add+0x1a0>)
|
|
80116d0: 681a ldr r2, [r3, #0]
|
|
80116d2: 68fb ldr r3, [r7, #12]
|
|
80116d4: 601a str r2, [r3, #0]
|
|
netif_list = netif;
|
|
80116d6: 4a0b ldr r2, [pc, #44] ; (8011704 <netif_add+0x1a0>)
|
|
80116d8: 68fb ldr r3, [r7, #12]
|
|
80116da: 6013 str r3, [r2, #0]
|
|
#endif /* LWIP_IPV4 */
|
|
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
|
|
|
|
netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL);
|
|
|
|
return netif;
|
|
80116dc: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80116de: 4618 mov r0, r3
|
|
80116e0: 3718 adds r7, #24
|
|
80116e2: 46bd mov sp, r7
|
|
80116e4: bd80 pop {r7, pc}
|
|
80116e6: bf00 nop
|
|
80116e8: 0801e418 .word 0x0801e418
|
|
80116ec: 0801e4ac .word 0x0801e4ac
|
|
80116f0: 0801e468 .word 0x0801e468
|
|
80116f4: 0801e4c8 .word 0x0801e4c8
|
|
80116f8: 08022e68 .word 0x08022e68
|
|
80116fc: 08011b27 .word 0x08011b27
|
|
8011700: 20008728 .word 0x20008728
|
|
8011704: 2000f7ec .word 0x2000f7ec
|
|
8011708: 0801e4ec .word 0x0801e4ec
|
|
801170c: 0801e500 .word 0x0801e500
|
|
|
|
08011710 <netif_do_ip_addr_changed>:
|
|
|
|
static void
|
|
netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
|
|
{
|
|
8011710: b580 push {r7, lr}
|
|
8011712: b082 sub sp, #8
|
|
8011714: af00 add r7, sp, #0
|
|
8011716: 6078 str r0, [r7, #4]
|
|
8011718: 6039 str r1, [r7, #0]
|
|
#if LWIP_TCP
|
|
tcp_netif_ip_addr_changed(old_addr, new_addr);
|
|
801171a: 6839 ldr r1, [r7, #0]
|
|
801171c: 6878 ldr r0, [r7, #4]
|
|
801171e: f002 fb81 bl 8013e24 <tcp_netif_ip_addr_changed>
|
|
#endif /* LWIP_TCP */
|
|
#if LWIP_UDP
|
|
udp_netif_ip_addr_changed(old_addr, new_addr);
|
|
8011722: 6839 ldr r1, [r7, #0]
|
|
8011724: 6878 ldr r0, [r7, #4]
|
|
8011726: f006 ffa1 bl 801866c <udp_netif_ip_addr_changed>
|
|
#endif /* LWIP_UDP */
|
|
#if LWIP_RAW
|
|
raw_netif_ip_addr_changed(old_addr, new_addr);
|
|
#endif /* LWIP_RAW */
|
|
}
|
|
801172a: bf00 nop
|
|
801172c: 3708 adds r7, #8
|
|
801172e: 46bd mov sp, r7
|
|
8011730: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08011734 <netif_do_set_ipaddr>:
|
|
|
|
#if LWIP_IPV4
|
|
static int
|
|
netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr)
|
|
{
|
|
8011734: b580 push {r7, lr}
|
|
8011736: b086 sub sp, #24
|
|
8011738: af00 add r7, sp, #0
|
|
801173a: 60f8 str r0, [r7, #12]
|
|
801173c: 60b9 str r1, [r7, #8]
|
|
801173e: 607a str r2, [r7, #4]
|
|
LWIP_ASSERT("invalid pointer", ipaddr != NULL);
|
|
8011740: 68bb ldr r3, [r7, #8]
|
|
8011742: 2b00 cmp r3, #0
|
|
8011744: d106 bne.n 8011754 <netif_do_set_ipaddr+0x20>
|
|
8011746: 4b1d ldr r3, [pc, #116] ; (80117bc <netif_do_set_ipaddr+0x88>)
|
|
8011748: f240 12cb movw r2, #459 ; 0x1cb
|
|
801174c: 491c ldr r1, [pc, #112] ; (80117c0 <netif_do_set_ipaddr+0x8c>)
|
|
801174e: 481d ldr r0, [pc, #116] ; (80117c4 <netif_do_set_ipaddr+0x90>)
|
|
8011750: f00b fab2 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("invalid pointer", old_addr != NULL);
|
|
8011754: 687b ldr r3, [r7, #4]
|
|
8011756: 2b00 cmp r3, #0
|
|
8011758: d106 bne.n 8011768 <netif_do_set_ipaddr+0x34>
|
|
801175a: 4b18 ldr r3, [pc, #96] ; (80117bc <netif_do_set_ipaddr+0x88>)
|
|
801175c: f44f 72e6 mov.w r2, #460 ; 0x1cc
|
|
8011760: 4917 ldr r1, [pc, #92] ; (80117c0 <netif_do_set_ipaddr+0x8c>)
|
|
8011762: 4818 ldr r0, [pc, #96] ; (80117c4 <netif_do_set_ipaddr+0x90>)
|
|
8011764: f00b faa8 bl 801ccb8 <iprintf>
|
|
|
|
/* address is actually being changed? */
|
|
if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) {
|
|
8011768: 68bb ldr r3, [r7, #8]
|
|
801176a: 681a ldr r2, [r3, #0]
|
|
801176c: 68fb ldr r3, [r7, #12]
|
|
801176e: 3304 adds r3, #4
|
|
8011770: 681b ldr r3, [r3, #0]
|
|
8011772: 429a cmp r2, r3
|
|
8011774: d01c beq.n 80117b0 <netif_do_set_ipaddr+0x7c>
|
|
ip_addr_t new_addr;
|
|
*ip_2_ip4(&new_addr) = *ipaddr;
|
|
8011776: 68bb ldr r3, [r7, #8]
|
|
8011778: 681b ldr r3, [r3, #0]
|
|
801177a: 617b str r3, [r7, #20]
|
|
IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4);
|
|
|
|
ip_addr_copy(*old_addr, *netif_ip_addr4(netif));
|
|
801177c: 68fb ldr r3, [r7, #12]
|
|
801177e: 3304 adds r3, #4
|
|
8011780: 681a ldr r2, [r3, #0]
|
|
8011782: 687b ldr r3, [r7, #4]
|
|
8011784: 601a str r2, [r3, #0]
|
|
|
|
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n"));
|
|
netif_do_ip_addr_changed(old_addr, &new_addr);
|
|
8011786: f107 0314 add.w r3, r7, #20
|
|
801178a: 4619 mov r1, r3
|
|
801178c: 6878 ldr r0, [r7, #4]
|
|
801178e: f7ff ffbf bl 8011710 <netif_do_ip_addr_changed>
|
|
|
|
mib2_remove_ip4(netif);
|
|
mib2_remove_route_ip4(0, netif);
|
|
/* set new IP address to netif */
|
|
ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr);
|
|
8011792: 68bb ldr r3, [r7, #8]
|
|
8011794: 2b00 cmp r3, #0
|
|
8011796: d002 beq.n 801179e <netif_do_set_ipaddr+0x6a>
|
|
8011798: 68bb ldr r3, [r7, #8]
|
|
801179a: 681b ldr r3, [r3, #0]
|
|
801179c: e000 b.n 80117a0 <netif_do_set_ipaddr+0x6c>
|
|
801179e: 2300 movs r3, #0
|
|
80117a0: 68fa ldr r2, [r7, #12]
|
|
80117a2: 6053 str r3, [r2, #4]
|
|
IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4);
|
|
mib2_add_ip4(netif);
|
|
mib2_add_route_ip4(0, netif);
|
|
|
|
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4);
|
|
80117a4: 2101 movs r1, #1
|
|
80117a6: 68f8 ldr r0, [r7, #12]
|
|
80117a8: f000 f8d2 bl 8011950 <netif_issue_reports>
|
|
|
|
NETIF_STATUS_CALLBACK(netif);
|
|
return 1; /* address changed */
|
|
80117ac: 2301 movs r3, #1
|
|
80117ae: e000 b.n 80117b2 <netif_do_set_ipaddr+0x7e>
|
|
}
|
|
return 0; /* address unchanged */
|
|
80117b0: 2300 movs r3, #0
|
|
}
|
|
80117b2: 4618 mov r0, r3
|
|
80117b4: 3718 adds r7, #24
|
|
80117b6: 46bd mov sp, r7
|
|
80117b8: bd80 pop {r7, pc}
|
|
80117ba: bf00 nop
|
|
80117bc: 0801e418 .word 0x0801e418
|
|
80117c0: 0801e530 .word 0x0801e530
|
|
80117c4: 0801e468 .word 0x0801e468
|
|
|
|
080117c8 <netif_do_set_netmask>:
|
|
}
|
|
}
|
|
|
|
static int
|
|
netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm)
|
|
{
|
|
80117c8: b480 push {r7}
|
|
80117ca: b085 sub sp, #20
|
|
80117cc: af00 add r7, sp, #0
|
|
80117ce: 60f8 str r0, [r7, #12]
|
|
80117d0: 60b9 str r1, [r7, #8]
|
|
80117d2: 607a str r2, [r7, #4]
|
|
/* address is actually being changed? */
|
|
if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) {
|
|
80117d4: 68bb ldr r3, [r7, #8]
|
|
80117d6: 681a ldr r2, [r3, #0]
|
|
80117d8: 68fb ldr r3, [r7, #12]
|
|
80117da: 3308 adds r3, #8
|
|
80117dc: 681b ldr r3, [r3, #0]
|
|
80117de: 429a cmp r2, r3
|
|
80117e0: d00a beq.n 80117f8 <netif_do_set_netmask+0x30>
|
|
#else
|
|
LWIP_UNUSED_ARG(old_nm);
|
|
#endif
|
|
mib2_remove_route_ip4(0, netif);
|
|
/* set new netmask to netif */
|
|
ip4_addr_set(ip_2_ip4(&netif->netmask), netmask);
|
|
80117e2: 68bb ldr r3, [r7, #8]
|
|
80117e4: 2b00 cmp r3, #0
|
|
80117e6: d002 beq.n 80117ee <netif_do_set_netmask+0x26>
|
|
80117e8: 68bb ldr r3, [r7, #8]
|
|
80117ea: 681b ldr r3, [r3, #0]
|
|
80117ec: e000 b.n 80117f0 <netif_do_set_netmask+0x28>
|
|
80117ee: 2300 movs r3, #0
|
|
80117f0: 68fa ldr r2, [r7, #12]
|
|
80117f2: 6093 str r3, [r2, #8]
|
|
netif->name[0], netif->name[1],
|
|
ip4_addr1_16(netif_ip4_netmask(netif)),
|
|
ip4_addr2_16(netif_ip4_netmask(netif)),
|
|
ip4_addr3_16(netif_ip4_netmask(netif)),
|
|
ip4_addr4_16(netif_ip4_netmask(netif))));
|
|
return 1; /* netmask changed */
|
|
80117f4: 2301 movs r3, #1
|
|
80117f6: e000 b.n 80117fa <netif_do_set_netmask+0x32>
|
|
}
|
|
return 0; /* netmask unchanged */
|
|
80117f8: 2300 movs r3, #0
|
|
}
|
|
80117fa: 4618 mov r0, r3
|
|
80117fc: 3714 adds r7, #20
|
|
80117fe: 46bd mov sp, r7
|
|
8011800: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011804: 4770 bx lr
|
|
|
|
08011806 <netif_do_set_gw>:
|
|
}
|
|
}
|
|
|
|
static int
|
|
netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw)
|
|
{
|
|
8011806: b480 push {r7}
|
|
8011808: b085 sub sp, #20
|
|
801180a: af00 add r7, sp, #0
|
|
801180c: 60f8 str r0, [r7, #12]
|
|
801180e: 60b9 str r1, [r7, #8]
|
|
8011810: 607a str r2, [r7, #4]
|
|
/* address is actually being changed? */
|
|
if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) {
|
|
8011812: 68bb ldr r3, [r7, #8]
|
|
8011814: 681a ldr r2, [r3, #0]
|
|
8011816: 68fb ldr r3, [r7, #12]
|
|
8011818: 330c adds r3, #12
|
|
801181a: 681b ldr r3, [r3, #0]
|
|
801181c: 429a cmp r2, r3
|
|
801181e: d00a beq.n 8011836 <netif_do_set_gw+0x30>
|
|
ip_addr_copy(*old_gw, *netif_ip_gw4(netif));
|
|
#else
|
|
LWIP_UNUSED_ARG(old_gw);
|
|
#endif
|
|
|
|
ip4_addr_set(ip_2_ip4(&netif->gw), gw);
|
|
8011820: 68bb ldr r3, [r7, #8]
|
|
8011822: 2b00 cmp r3, #0
|
|
8011824: d002 beq.n 801182c <netif_do_set_gw+0x26>
|
|
8011826: 68bb ldr r3, [r7, #8]
|
|
8011828: 681b ldr r3, [r3, #0]
|
|
801182a: e000 b.n 801182e <netif_do_set_gw+0x28>
|
|
801182c: 2300 movs r3, #0
|
|
801182e: 68fa ldr r2, [r7, #12]
|
|
8011830: 60d3 str r3, [r2, #12]
|
|
netif->name[0], netif->name[1],
|
|
ip4_addr1_16(netif_ip4_gw(netif)),
|
|
ip4_addr2_16(netif_ip4_gw(netif)),
|
|
ip4_addr3_16(netif_ip4_gw(netif)),
|
|
ip4_addr4_16(netif_ip4_gw(netif))));
|
|
return 1; /* gateway changed */
|
|
8011832: 2301 movs r3, #1
|
|
8011834: e000 b.n 8011838 <netif_do_set_gw+0x32>
|
|
}
|
|
return 0; /* gateway unchanged */
|
|
8011836: 2300 movs r3, #0
|
|
}
|
|
8011838: 4618 mov r0, r3
|
|
801183a: 3714 adds r7, #20
|
|
801183c: 46bd mov sp, r7
|
|
801183e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011842: 4770 bx lr
|
|
|
|
08011844 <netif_set_addr>:
|
|
* @param gw the new default gateway
|
|
*/
|
|
void
|
|
netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask,
|
|
const ip4_addr_t *gw)
|
|
{
|
|
8011844: b580 push {r7, lr}
|
|
8011846: b088 sub sp, #32
|
|
8011848: af00 add r7, sp, #0
|
|
801184a: 60f8 str r0, [r7, #12]
|
|
801184c: 60b9 str r1, [r7, #8]
|
|
801184e: 607a str r2, [r7, #4]
|
|
8011850: 603b str r3, [r7, #0]
|
|
ip_addr_t old_nm_val;
|
|
ip_addr_t old_gw_val;
|
|
ip_addr_t *old_nm = &old_nm_val;
|
|
ip_addr_t *old_gw = &old_gw_val;
|
|
#else
|
|
ip_addr_t *old_nm = NULL;
|
|
8011852: 2300 movs r3, #0
|
|
8011854: 61fb str r3, [r7, #28]
|
|
ip_addr_t *old_gw = NULL;
|
|
8011856: 2300 movs r3, #0
|
|
8011858: 61bb str r3, [r7, #24]
|
|
int remove;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
|
|
if (ipaddr == NULL) {
|
|
801185a: 68bb ldr r3, [r7, #8]
|
|
801185c: 2b00 cmp r3, #0
|
|
801185e: d101 bne.n 8011864 <netif_set_addr+0x20>
|
|
ipaddr = IP4_ADDR_ANY4;
|
|
8011860: 4b1c ldr r3, [pc, #112] ; (80118d4 <netif_set_addr+0x90>)
|
|
8011862: 60bb str r3, [r7, #8]
|
|
}
|
|
if (netmask == NULL) {
|
|
8011864: 687b ldr r3, [r7, #4]
|
|
8011866: 2b00 cmp r3, #0
|
|
8011868: d101 bne.n 801186e <netif_set_addr+0x2a>
|
|
netmask = IP4_ADDR_ANY4;
|
|
801186a: 4b1a ldr r3, [pc, #104] ; (80118d4 <netif_set_addr+0x90>)
|
|
801186c: 607b str r3, [r7, #4]
|
|
}
|
|
if (gw == NULL) {
|
|
801186e: 683b ldr r3, [r7, #0]
|
|
8011870: 2b00 cmp r3, #0
|
|
8011872: d101 bne.n 8011878 <netif_set_addr+0x34>
|
|
gw = IP4_ADDR_ANY4;
|
|
8011874: 4b17 ldr r3, [pc, #92] ; (80118d4 <netif_set_addr+0x90>)
|
|
8011876: 603b str r3, [r7, #0]
|
|
}
|
|
|
|
remove = ip4_addr_isany(ipaddr);
|
|
8011878: 68bb ldr r3, [r7, #8]
|
|
801187a: 2b00 cmp r3, #0
|
|
801187c: d003 beq.n 8011886 <netif_set_addr+0x42>
|
|
801187e: 68bb ldr r3, [r7, #8]
|
|
8011880: 681b ldr r3, [r3, #0]
|
|
8011882: 2b00 cmp r3, #0
|
|
8011884: d101 bne.n 801188a <netif_set_addr+0x46>
|
|
8011886: 2301 movs r3, #1
|
|
8011888: e000 b.n 801188c <netif_set_addr+0x48>
|
|
801188a: 2300 movs r3, #0
|
|
801188c: 617b str r3, [r7, #20]
|
|
if (remove) {
|
|
801188e: 697b ldr r3, [r7, #20]
|
|
8011890: 2b00 cmp r3, #0
|
|
8011892: d006 beq.n 80118a2 <netif_set_addr+0x5e>
|
|
/* when removing an address, we have to remove it *before* changing netmask/gw
|
|
to ensure that tcp RST segment can be sent correctly */
|
|
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
|
|
8011894: f107 0310 add.w r3, r7, #16
|
|
8011898: 461a mov r2, r3
|
|
801189a: 68b9 ldr r1, [r7, #8]
|
|
801189c: 68f8 ldr r0, [r7, #12]
|
|
801189e: f7ff ff49 bl 8011734 <netif_do_set_ipaddr>
|
|
change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED;
|
|
cb_args.ipv4_changed.old_address = &old_addr;
|
|
#endif
|
|
}
|
|
}
|
|
if (netif_do_set_netmask(netif, netmask, old_nm)) {
|
|
80118a2: 69fa ldr r2, [r7, #28]
|
|
80118a4: 6879 ldr r1, [r7, #4]
|
|
80118a6: 68f8 ldr r0, [r7, #12]
|
|
80118a8: f7ff ff8e bl 80117c8 <netif_do_set_netmask>
|
|
#if LWIP_NETIF_EXT_STATUS_CALLBACK
|
|
change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED;
|
|
cb_args.ipv4_changed.old_netmask = old_nm;
|
|
#endif
|
|
}
|
|
if (netif_do_set_gw(netif, gw, old_gw)) {
|
|
80118ac: 69ba ldr r2, [r7, #24]
|
|
80118ae: 6839 ldr r1, [r7, #0]
|
|
80118b0: 68f8 ldr r0, [r7, #12]
|
|
80118b2: f7ff ffa8 bl 8011806 <netif_do_set_gw>
|
|
#if LWIP_NETIF_EXT_STATUS_CALLBACK
|
|
change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED;
|
|
cb_args.ipv4_changed.old_gw = old_gw;
|
|
#endif
|
|
}
|
|
if (!remove) {
|
|
80118b6: 697b ldr r3, [r7, #20]
|
|
80118b8: 2b00 cmp r3, #0
|
|
80118ba: d106 bne.n 80118ca <netif_set_addr+0x86>
|
|
/* set ipaddr last to ensure netmask/gw have been set when status callback is called */
|
|
if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) {
|
|
80118bc: f107 0310 add.w r3, r7, #16
|
|
80118c0: 461a mov r2, r3
|
|
80118c2: 68b9 ldr r1, [r7, #8]
|
|
80118c4: 68f8 ldr r0, [r7, #12]
|
|
80118c6: f7ff ff35 bl 8011734 <netif_do_set_ipaddr>
|
|
if (change_reason != LWIP_NSC_NONE) {
|
|
change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED;
|
|
netif_invoke_ext_callback(netif, change_reason, &cb_args);
|
|
}
|
|
#endif
|
|
}
|
|
80118ca: bf00 nop
|
|
80118cc: 3720 adds r7, #32
|
|
80118ce: 46bd mov sp, r7
|
|
80118d0: bd80 pop {r7, pc}
|
|
80118d2: bf00 nop
|
|
80118d4: 08022e68 .word 0x08022e68
|
|
|
|
080118d8 <netif_set_default>:
|
|
*
|
|
* @param netif the default network interface
|
|
*/
|
|
void
|
|
netif_set_default(struct netif *netif)
|
|
{
|
|
80118d8: b480 push {r7}
|
|
80118da: b083 sub sp, #12
|
|
80118dc: af00 add r7, sp, #0
|
|
80118de: 6078 str r0, [r7, #4]
|
|
mib2_remove_route_ip4(1, netif);
|
|
} else {
|
|
/* install default route */
|
|
mib2_add_route_ip4(1, netif);
|
|
}
|
|
netif_default = netif;
|
|
80118e0: 4a04 ldr r2, [pc, #16] ; (80118f4 <netif_set_default+0x1c>)
|
|
80118e2: 687b ldr r3, [r7, #4]
|
|
80118e4: 6013 str r3, [r2, #0]
|
|
LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n",
|
|
netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\''));
|
|
}
|
|
80118e6: bf00 nop
|
|
80118e8: 370c adds r7, #12
|
|
80118ea: 46bd mov sp, r7
|
|
80118ec: f85d 7b04 ldr.w r7, [sp], #4
|
|
80118f0: 4770 bx lr
|
|
80118f2: bf00 nop
|
|
80118f4: 2000f7f0 .word 0x2000f7f0
|
|
|
|
080118f8 <netif_set_up>:
|
|
* Bring an interface up, available for processing
|
|
* traffic.
|
|
*/
|
|
void
|
|
netif_set_up(struct netif *netif)
|
|
{
|
|
80118f8: b580 push {r7, lr}
|
|
80118fa: b082 sub sp, #8
|
|
80118fc: af00 add r7, sp, #0
|
|
80118fe: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return);
|
|
8011900: 687b ldr r3, [r7, #4]
|
|
8011902: 2b00 cmp r3, #0
|
|
8011904: d107 bne.n 8011916 <netif_set_up+0x1e>
|
|
8011906: 4b0f ldr r3, [pc, #60] ; (8011944 <netif_set_up+0x4c>)
|
|
8011908: f44f 7254 mov.w r2, #848 ; 0x350
|
|
801190c: 490e ldr r1, [pc, #56] ; (8011948 <netif_set_up+0x50>)
|
|
801190e: 480f ldr r0, [pc, #60] ; (801194c <netif_set_up+0x54>)
|
|
8011910: f00b f9d2 bl 801ccb8 <iprintf>
|
|
8011914: e013 b.n 801193e <netif_set_up+0x46>
|
|
|
|
if (!(netif->flags & NETIF_FLAG_UP)) {
|
|
8011916: 687b ldr r3, [r7, #4]
|
|
8011918: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801191c: f003 0301 and.w r3, r3, #1
|
|
8011920: 2b00 cmp r3, #0
|
|
8011922: d10c bne.n 801193e <netif_set_up+0x46>
|
|
netif_set_flags(netif, NETIF_FLAG_UP);
|
|
8011924: 687b ldr r3, [r7, #4]
|
|
8011926: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801192a: f043 0301 orr.w r3, r3, #1
|
|
801192e: b2da uxtb r2, r3
|
|
8011930: 687b ldr r3, [r7, #4]
|
|
8011932: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
args.status_changed.state = 1;
|
|
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
|
|
}
|
|
#endif
|
|
|
|
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
|
|
8011936: 2103 movs r1, #3
|
|
8011938: 6878 ldr r0, [r7, #4]
|
|
801193a: f000 f809 bl 8011950 <netif_issue_reports>
|
|
#if LWIP_IPV6
|
|
nd6_restart_netif(netif);
|
|
#endif /* LWIP_IPV6 */
|
|
}
|
|
}
|
|
801193e: 3708 adds r7, #8
|
|
8011940: 46bd mov sp, r7
|
|
8011942: bd80 pop {r7, pc}
|
|
8011944: 0801e418 .word 0x0801e418
|
|
8011948: 0801e5a0 .word 0x0801e5a0
|
|
801194c: 0801e468 .word 0x0801e468
|
|
|
|
08011950 <netif_issue_reports>:
|
|
|
|
/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change
|
|
*/
|
|
static void
|
|
netif_issue_reports(struct netif *netif, u8_t report_type)
|
|
{
|
|
8011950: b580 push {r7, lr}
|
|
8011952: b082 sub sp, #8
|
|
8011954: af00 add r7, sp, #0
|
|
8011956: 6078 str r0, [r7, #4]
|
|
8011958: 460b mov r3, r1
|
|
801195a: 70fb strb r3, [r7, #3]
|
|
LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL);
|
|
801195c: 687b ldr r3, [r7, #4]
|
|
801195e: 2b00 cmp r3, #0
|
|
8011960: d106 bne.n 8011970 <netif_issue_reports+0x20>
|
|
8011962: 4b18 ldr r3, [pc, #96] ; (80119c4 <netif_issue_reports+0x74>)
|
|
8011964: f240 326d movw r2, #877 ; 0x36d
|
|
8011968: 4917 ldr r1, [pc, #92] ; (80119c8 <netif_issue_reports+0x78>)
|
|
801196a: 4818 ldr r0, [pc, #96] ; (80119cc <netif_issue_reports+0x7c>)
|
|
801196c: f00b f9a4 bl 801ccb8 <iprintf>
|
|
|
|
/* Only send reports when both link and admin states are up */
|
|
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
|
|
8011970: 687b ldr r3, [r7, #4]
|
|
8011972: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011976: f003 0304 and.w r3, r3, #4
|
|
801197a: 2b00 cmp r3, #0
|
|
801197c: d01e beq.n 80119bc <netif_issue_reports+0x6c>
|
|
!(netif->flags & NETIF_FLAG_UP)) {
|
|
801197e: 687b ldr r3, [r7, #4]
|
|
8011980: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011984: f003 0301 and.w r3, r3, #1
|
|
if (!(netif->flags & NETIF_FLAG_LINK_UP) ||
|
|
8011988: 2b00 cmp r3, #0
|
|
801198a: d017 beq.n 80119bc <netif_issue_reports+0x6c>
|
|
return;
|
|
}
|
|
|
|
#if LWIP_IPV4
|
|
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
|
|
801198c: 78fb ldrb r3, [r7, #3]
|
|
801198e: f003 0301 and.w r3, r3, #1
|
|
8011992: 2b00 cmp r3, #0
|
|
8011994: d013 beq.n 80119be <netif_issue_reports+0x6e>
|
|
!ip4_addr_isany_val(*netif_ip4_addr(netif))) {
|
|
8011996: 687b ldr r3, [r7, #4]
|
|
8011998: 3304 adds r3, #4
|
|
801199a: 681b ldr r3, [r3, #0]
|
|
if ((report_type & NETIF_REPORT_TYPE_IPV4) &&
|
|
801199c: 2b00 cmp r3, #0
|
|
801199e: d00e beq.n 80119be <netif_issue_reports+0x6e>
|
|
#if LWIP_ARP
|
|
/* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */
|
|
if (netif->flags & (NETIF_FLAG_ETHARP)) {
|
|
80119a0: 687b ldr r3, [r7, #4]
|
|
80119a2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
80119a6: f003 0308 and.w r3, r3, #8
|
|
80119aa: 2b00 cmp r3, #0
|
|
80119ac: d007 beq.n 80119be <netif_issue_reports+0x6e>
|
|
etharp_gratuitous(netif);
|
|
80119ae: 687b ldr r3, [r7, #4]
|
|
80119b0: 3304 adds r3, #4
|
|
80119b2: 4619 mov r1, r3
|
|
80119b4: 6878 ldr r0, [r7, #4]
|
|
80119b6: f009 fc6b bl 801b290 <etharp_request>
|
|
80119ba: e000 b.n 80119be <netif_issue_reports+0x6e>
|
|
return;
|
|
80119bc: bf00 nop
|
|
/* send mld memberships */
|
|
mld6_report_groups(netif);
|
|
#endif /* LWIP_IPV6_MLD */
|
|
}
|
|
#endif /* LWIP_IPV6 */
|
|
}
|
|
80119be: 3708 adds r7, #8
|
|
80119c0: 46bd mov sp, r7
|
|
80119c2: bd80 pop {r7, pc}
|
|
80119c4: 0801e418 .word 0x0801e418
|
|
80119c8: 0801e5bc .word 0x0801e5bc
|
|
80119cc: 0801e468 .word 0x0801e468
|
|
|
|
080119d0 <netif_set_down>:
|
|
* @ingroup netif
|
|
* Bring an interface down, disabling any traffic processing.
|
|
*/
|
|
void
|
|
netif_set_down(struct netif *netif)
|
|
{
|
|
80119d0: b580 push {r7, lr}
|
|
80119d2: b082 sub sp, #8
|
|
80119d4: af00 add r7, sp, #0
|
|
80119d6: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return);
|
|
80119d8: 687b ldr r3, [r7, #4]
|
|
80119da: 2b00 cmp r3, #0
|
|
80119dc: d107 bne.n 80119ee <netif_set_down+0x1e>
|
|
80119de: 4b12 ldr r3, [pc, #72] ; (8011a28 <netif_set_down+0x58>)
|
|
80119e0: f240 329b movw r2, #923 ; 0x39b
|
|
80119e4: 4911 ldr r1, [pc, #68] ; (8011a2c <netif_set_down+0x5c>)
|
|
80119e6: 4812 ldr r0, [pc, #72] ; (8011a30 <netif_set_down+0x60>)
|
|
80119e8: f00b f966 bl 801ccb8 <iprintf>
|
|
80119ec: e019 b.n 8011a22 <netif_set_down+0x52>
|
|
|
|
if (netif->flags & NETIF_FLAG_UP) {
|
|
80119ee: 687b ldr r3, [r7, #4]
|
|
80119f0: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
80119f4: f003 0301 and.w r3, r3, #1
|
|
80119f8: 2b00 cmp r3, #0
|
|
80119fa: d012 beq.n 8011a22 <netif_set_down+0x52>
|
|
args.status_changed.state = 0;
|
|
netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args);
|
|
}
|
|
#endif
|
|
|
|
netif_clear_flags(netif, NETIF_FLAG_UP);
|
|
80119fc: 687b ldr r3, [r7, #4]
|
|
80119fe: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011a02: f023 0301 bic.w r3, r3, #1
|
|
8011a06: b2da uxtb r2, r3
|
|
8011a08: 687b ldr r3, [r7, #4]
|
|
8011a0a: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
MIB2_COPY_SYSUPTIME_TO(&netif->ts);
|
|
|
|
#if LWIP_IPV4 && LWIP_ARP
|
|
if (netif->flags & NETIF_FLAG_ETHARP) {
|
|
8011a0e: 687b ldr r3, [r7, #4]
|
|
8011a10: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011a14: f003 0308 and.w r3, r3, #8
|
|
8011a18: 2b00 cmp r3, #0
|
|
8011a1a: d002 beq.n 8011a22 <netif_set_down+0x52>
|
|
etharp_cleanup_netif(netif);
|
|
8011a1c: 6878 ldr r0, [r7, #4]
|
|
8011a1e: f008 fff1 bl 801aa04 <etharp_cleanup_netif>
|
|
nd6_cleanup_netif(netif);
|
|
#endif /* LWIP_IPV6 */
|
|
|
|
NETIF_STATUS_CALLBACK(netif);
|
|
}
|
|
}
|
|
8011a22: 3708 adds r7, #8
|
|
8011a24: 46bd mov sp, r7
|
|
8011a26: bd80 pop {r7, pc}
|
|
8011a28: 0801e418 .word 0x0801e418
|
|
8011a2c: 0801e5e0 .word 0x0801e5e0
|
|
8011a30: 0801e468 .word 0x0801e468
|
|
|
|
08011a34 <netif_set_link_up>:
|
|
* @ingroup netif
|
|
* Called by a driver when its link goes up
|
|
*/
|
|
void
|
|
netif_set_link_up(struct netif *netif)
|
|
{
|
|
8011a34: b580 push {r7, lr}
|
|
8011a36: b082 sub sp, #8
|
|
8011a38: af00 add r7, sp, #0
|
|
8011a3a: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return);
|
|
8011a3c: 687b ldr r3, [r7, #4]
|
|
8011a3e: 2b00 cmp r3, #0
|
|
8011a40: d107 bne.n 8011a52 <netif_set_link_up+0x1e>
|
|
8011a42: 4b15 ldr r3, [pc, #84] ; (8011a98 <netif_set_link_up+0x64>)
|
|
8011a44: f44f 7278 mov.w r2, #992 ; 0x3e0
|
|
8011a48: 4914 ldr r1, [pc, #80] ; (8011a9c <netif_set_link_up+0x68>)
|
|
8011a4a: 4815 ldr r0, [pc, #84] ; (8011aa0 <netif_set_link_up+0x6c>)
|
|
8011a4c: f00b f934 bl 801ccb8 <iprintf>
|
|
8011a50: e01e b.n 8011a90 <netif_set_link_up+0x5c>
|
|
|
|
if (!(netif->flags & NETIF_FLAG_LINK_UP)) {
|
|
8011a52: 687b ldr r3, [r7, #4]
|
|
8011a54: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011a58: f003 0304 and.w r3, r3, #4
|
|
8011a5c: 2b00 cmp r3, #0
|
|
8011a5e: d117 bne.n 8011a90 <netif_set_link_up+0x5c>
|
|
netif_set_flags(netif, NETIF_FLAG_LINK_UP);
|
|
8011a60: 687b ldr r3, [r7, #4]
|
|
8011a62: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011a66: f043 0304 orr.w r3, r3, #4
|
|
8011a6a: b2da uxtb r2, r3
|
|
8011a6c: 687b ldr r3, [r7, #4]
|
|
8011a6e: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
|
|
#if LWIP_DHCP
|
|
dhcp_network_changed(netif);
|
|
8011a72: 6878 ldr r0, [r7, #4]
|
|
8011a74: f007 fa26 bl 8018ec4 <dhcp_network_changed>
|
|
|
|
#if LWIP_AUTOIP
|
|
autoip_network_changed(netif);
|
|
#endif /* LWIP_AUTOIP */
|
|
|
|
netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6);
|
|
8011a78: 2103 movs r1, #3
|
|
8011a7a: 6878 ldr r0, [r7, #4]
|
|
8011a7c: f7ff ff68 bl 8011950 <netif_issue_reports>
|
|
#if LWIP_IPV6
|
|
nd6_restart_netif(netif);
|
|
#endif /* LWIP_IPV6 */
|
|
|
|
NETIF_LINK_CALLBACK(netif);
|
|
8011a80: 687b ldr r3, [r7, #4]
|
|
8011a82: 69db ldr r3, [r3, #28]
|
|
8011a84: 2b00 cmp r3, #0
|
|
8011a86: d003 beq.n 8011a90 <netif_set_link_up+0x5c>
|
|
8011a88: 687b ldr r3, [r7, #4]
|
|
8011a8a: 69db ldr r3, [r3, #28]
|
|
8011a8c: 6878 ldr r0, [r7, #4]
|
|
8011a8e: 4798 blx r3
|
|
args.link_changed.state = 1;
|
|
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
8011a90: 3708 adds r7, #8
|
|
8011a92: 46bd mov sp, r7
|
|
8011a94: bd80 pop {r7, pc}
|
|
8011a96: bf00 nop
|
|
8011a98: 0801e418 .word 0x0801e418
|
|
8011a9c: 0801e600 .word 0x0801e600
|
|
8011aa0: 0801e468 .word 0x0801e468
|
|
|
|
08011aa4 <netif_set_link_down>:
|
|
* @ingroup netif
|
|
* Called by a driver when its link goes down
|
|
*/
|
|
void
|
|
netif_set_link_down(struct netif *netif)
|
|
{
|
|
8011aa4: b580 push {r7, lr}
|
|
8011aa6: b082 sub sp, #8
|
|
8011aa8: af00 add r7, sp, #0
|
|
8011aaa: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return);
|
|
8011aac: 687b ldr r3, [r7, #4]
|
|
8011aae: 2b00 cmp r3, #0
|
|
8011ab0: d107 bne.n 8011ac2 <netif_set_link_down+0x1e>
|
|
8011ab2: 4b11 ldr r3, [pc, #68] ; (8011af8 <netif_set_link_down+0x54>)
|
|
8011ab4: f240 4206 movw r2, #1030 ; 0x406
|
|
8011ab8: 4910 ldr r1, [pc, #64] ; (8011afc <netif_set_link_down+0x58>)
|
|
8011aba: 4811 ldr r0, [pc, #68] ; (8011b00 <netif_set_link_down+0x5c>)
|
|
8011abc: f00b f8fc bl 801ccb8 <iprintf>
|
|
8011ac0: e017 b.n 8011af2 <netif_set_link_down+0x4e>
|
|
|
|
if (netif->flags & NETIF_FLAG_LINK_UP) {
|
|
8011ac2: 687b ldr r3, [r7, #4]
|
|
8011ac4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011ac8: f003 0304 and.w r3, r3, #4
|
|
8011acc: 2b00 cmp r3, #0
|
|
8011ace: d010 beq.n 8011af2 <netif_set_link_down+0x4e>
|
|
netif_clear_flags(netif, NETIF_FLAG_LINK_UP);
|
|
8011ad0: 687b ldr r3, [r7, #4]
|
|
8011ad2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8011ad6: f023 0304 bic.w r3, r3, #4
|
|
8011ada: b2da uxtb r2, r3
|
|
8011adc: 687b ldr r3, [r7, #4]
|
|
8011ade: f883 2031 strb.w r2, [r3, #49] ; 0x31
|
|
NETIF_LINK_CALLBACK(netif);
|
|
8011ae2: 687b ldr r3, [r7, #4]
|
|
8011ae4: 69db ldr r3, [r3, #28]
|
|
8011ae6: 2b00 cmp r3, #0
|
|
8011ae8: d003 beq.n 8011af2 <netif_set_link_down+0x4e>
|
|
8011aea: 687b ldr r3, [r7, #4]
|
|
8011aec: 69db ldr r3, [r3, #28]
|
|
8011aee: 6878 ldr r0, [r7, #4]
|
|
8011af0: 4798 blx r3
|
|
args.link_changed.state = 0;
|
|
netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
8011af2: 3708 adds r7, #8
|
|
8011af4: 46bd mov sp, r7
|
|
8011af6: bd80 pop {r7, pc}
|
|
8011af8: 0801e418 .word 0x0801e418
|
|
8011afc: 0801e624 .word 0x0801e624
|
|
8011b00: 0801e468 .word 0x0801e468
|
|
|
|
08011b04 <netif_set_link_callback>:
|
|
* @ingroup netif
|
|
* Set callback to be called when link is brought up/down
|
|
*/
|
|
void
|
|
netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback)
|
|
{
|
|
8011b04: b480 push {r7}
|
|
8011b06: b083 sub sp, #12
|
|
8011b08: af00 add r7, sp, #0
|
|
8011b0a: 6078 str r0, [r7, #4]
|
|
8011b0c: 6039 str r1, [r7, #0]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
if (netif) {
|
|
8011b0e: 687b ldr r3, [r7, #4]
|
|
8011b10: 2b00 cmp r3, #0
|
|
8011b12: d002 beq.n 8011b1a <netif_set_link_callback+0x16>
|
|
netif->link_callback = link_callback;
|
|
8011b14: 687b ldr r3, [r7, #4]
|
|
8011b16: 683a ldr r2, [r7, #0]
|
|
8011b18: 61da str r2, [r3, #28]
|
|
}
|
|
}
|
|
8011b1a: bf00 nop
|
|
8011b1c: 370c adds r7, #12
|
|
8011b1e: 46bd mov sp, r7
|
|
8011b20: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011b24: 4770 bx lr
|
|
|
|
08011b26 <netif_null_output_ip4>:
|
|
#if LWIP_IPV4
|
|
/** Dummy IPv4 output function for netifs not supporting IPv4
|
|
*/
|
|
static err_t
|
|
netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr)
|
|
{
|
|
8011b26: b480 push {r7}
|
|
8011b28: b085 sub sp, #20
|
|
8011b2a: af00 add r7, sp, #0
|
|
8011b2c: 60f8 str r0, [r7, #12]
|
|
8011b2e: 60b9 str r1, [r7, #8]
|
|
8011b30: 607a str r2, [r7, #4]
|
|
LWIP_UNUSED_ARG(netif);
|
|
LWIP_UNUSED_ARG(p);
|
|
LWIP_UNUSED_ARG(ipaddr);
|
|
|
|
return ERR_IF;
|
|
8011b32: f06f 030b mvn.w r3, #11
|
|
}
|
|
8011b36: 4618 mov r0, r3
|
|
8011b38: 3714 adds r7, #20
|
|
8011b3a: 46bd mov sp, r7
|
|
8011b3c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011b40: 4770 bx lr
|
|
...
|
|
|
|
08011b44 <netif_get_by_index>:
|
|
*
|
|
* @param idx index of netif to find
|
|
*/
|
|
struct netif *
|
|
netif_get_by_index(u8_t idx)
|
|
{
|
|
8011b44: b480 push {r7}
|
|
8011b46: b085 sub sp, #20
|
|
8011b48: af00 add r7, sp, #0
|
|
8011b4a: 4603 mov r3, r0
|
|
8011b4c: 71fb strb r3, [r7, #7]
|
|
struct netif *netif;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
if (idx != NETIF_NO_INDEX) {
|
|
8011b4e: 79fb ldrb r3, [r7, #7]
|
|
8011b50: 2b00 cmp r3, #0
|
|
8011b52: d013 beq.n 8011b7c <netif_get_by_index+0x38>
|
|
NETIF_FOREACH(netif) {
|
|
8011b54: 4b0d ldr r3, [pc, #52] ; (8011b8c <netif_get_by_index+0x48>)
|
|
8011b56: 681b ldr r3, [r3, #0]
|
|
8011b58: 60fb str r3, [r7, #12]
|
|
8011b5a: e00c b.n 8011b76 <netif_get_by_index+0x32>
|
|
if (idx == netif_get_index(netif)) {
|
|
8011b5c: 68fb ldr r3, [r7, #12]
|
|
8011b5e: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8011b62: 3301 adds r3, #1
|
|
8011b64: b2db uxtb r3, r3
|
|
8011b66: 79fa ldrb r2, [r7, #7]
|
|
8011b68: 429a cmp r2, r3
|
|
8011b6a: d101 bne.n 8011b70 <netif_get_by_index+0x2c>
|
|
return netif; /* found! */
|
|
8011b6c: 68fb ldr r3, [r7, #12]
|
|
8011b6e: e006 b.n 8011b7e <netif_get_by_index+0x3a>
|
|
NETIF_FOREACH(netif) {
|
|
8011b70: 68fb ldr r3, [r7, #12]
|
|
8011b72: 681b ldr r3, [r3, #0]
|
|
8011b74: 60fb str r3, [r7, #12]
|
|
8011b76: 68fb ldr r3, [r7, #12]
|
|
8011b78: 2b00 cmp r3, #0
|
|
8011b7a: d1ef bne.n 8011b5c <netif_get_by_index+0x18>
|
|
}
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
8011b7c: 2300 movs r3, #0
|
|
}
|
|
8011b7e: 4618 mov r0, r3
|
|
8011b80: 3714 adds r7, #20
|
|
8011b82: 46bd mov sp, r7
|
|
8011b84: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011b88: 4770 bx lr
|
|
8011b8a: bf00 nop
|
|
8011b8c: 2000f7ec .word 0x2000f7ec
|
|
|
|
08011b90 <pbuf_free_ooseq>:
|
|
#if !NO_SYS
|
|
static
|
|
#endif /* !NO_SYS */
|
|
void
|
|
pbuf_free_ooseq(void)
|
|
{
|
|
8011b90: b580 push {r7, lr}
|
|
8011b92: b082 sub sp, #8
|
|
8011b94: af00 add r7, sp, #0
|
|
struct tcp_pcb *pcb;
|
|
SYS_ARCH_SET(pbuf_free_ooseq_pending, 0);
|
|
8011b96: f00b f811 bl 801cbbc <sys_arch_protect>
|
|
8011b9a: 6038 str r0, [r7, #0]
|
|
8011b9c: 4b0d ldr r3, [pc, #52] ; (8011bd4 <pbuf_free_ooseq+0x44>)
|
|
8011b9e: 2200 movs r2, #0
|
|
8011ba0: 701a strb r2, [r3, #0]
|
|
8011ba2: 6838 ldr r0, [r7, #0]
|
|
8011ba4: f00b f818 bl 801cbd8 <sys_arch_unprotect>
|
|
|
|
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
|
|
8011ba8: 4b0b ldr r3, [pc, #44] ; (8011bd8 <pbuf_free_ooseq+0x48>)
|
|
8011baa: 681b ldr r3, [r3, #0]
|
|
8011bac: 607b str r3, [r7, #4]
|
|
8011bae: e00a b.n 8011bc6 <pbuf_free_ooseq+0x36>
|
|
if (pcb->ooseq != NULL) {
|
|
8011bb0: 687b ldr r3, [r7, #4]
|
|
8011bb2: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8011bb4: 2b00 cmp r3, #0
|
|
8011bb6: d003 beq.n 8011bc0 <pbuf_free_ooseq+0x30>
|
|
/** Free the ooseq pbufs of one PCB only */
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n"));
|
|
tcp_free_ooseq(pcb);
|
|
8011bb8: 6878 ldr r0, [r7, #4]
|
|
8011bba: f002 f971 bl 8013ea0 <tcp_free_ooseq>
|
|
return;
|
|
8011bbe: e005 b.n 8011bcc <pbuf_free_ooseq+0x3c>
|
|
for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) {
|
|
8011bc0: 687b ldr r3, [r7, #4]
|
|
8011bc2: 68db ldr r3, [r3, #12]
|
|
8011bc4: 607b str r3, [r7, #4]
|
|
8011bc6: 687b ldr r3, [r7, #4]
|
|
8011bc8: 2b00 cmp r3, #0
|
|
8011bca: d1f1 bne.n 8011bb0 <pbuf_free_ooseq+0x20>
|
|
}
|
|
}
|
|
}
|
|
8011bcc: 3708 adds r7, #8
|
|
8011bce: 46bd mov sp, r7
|
|
8011bd0: bd80 pop {r7, pc}
|
|
8011bd2: bf00 nop
|
|
8011bd4: 2000f7f4 .word 0x2000f7f4
|
|
8011bd8: 2000f7fc .word 0x2000f7fc
|
|
|
|
08011bdc <pbuf_free_ooseq_callback>:
|
|
/**
|
|
* Just a callback function for tcpip_callback() that calls pbuf_free_ooseq().
|
|
*/
|
|
static void
|
|
pbuf_free_ooseq_callback(void *arg)
|
|
{
|
|
8011bdc: b580 push {r7, lr}
|
|
8011bde: b082 sub sp, #8
|
|
8011be0: af00 add r7, sp, #0
|
|
8011be2: 6078 str r0, [r7, #4]
|
|
LWIP_UNUSED_ARG(arg);
|
|
pbuf_free_ooseq();
|
|
8011be4: f7ff ffd4 bl 8011b90 <pbuf_free_ooseq>
|
|
}
|
|
8011be8: bf00 nop
|
|
8011bea: 3708 adds r7, #8
|
|
8011bec: 46bd mov sp, r7
|
|
8011bee: bd80 pop {r7, pc}
|
|
|
|
08011bf0 <pbuf_pool_is_empty>:
|
|
#endif /* !NO_SYS */
|
|
|
|
/** Queue a call to pbuf_free_ooseq if not already queued. */
|
|
static void
|
|
pbuf_pool_is_empty(void)
|
|
{
|
|
8011bf0: b580 push {r7, lr}
|
|
8011bf2: b082 sub sp, #8
|
|
8011bf4: af00 add r7, sp, #0
|
|
#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL
|
|
SYS_ARCH_SET(pbuf_free_ooseq_pending, 1);
|
|
#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
|
|
u8_t queued;
|
|
SYS_ARCH_DECL_PROTECT(old_level);
|
|
SYS_ARCH_PROTECT(old_level);
|
|
8011bf6: f00a ffe1 bl 801cbbc <sys_arch_protect>
|
|
8011bfa: 6078 str r0, [r7, #4]
|
|
queued = pbuf_free_ooseq_pending;
|
|
8011bfc: 4b0f ldr r3, [pc, #60] ; (8011c3c <pbuf_pool_is_empty+0x4c>)
|
|
8011bfe: 781b ldrb r3, [r3, #0]
|
|
8011c00: 70fb strb r3, [r7, #3]
|
|
pbuf_free_ooseq_pending = 1;
|
|
8011c02: 4b0e ldr r3, [pc, #56] ; (8011c3c <pbuf_pool_is_empty+0x4c>)
|
|
8011c04: 2201 movs r2, #1
|
|
8011c06: 701a strb r2, [r3, #0]
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
8011c08: 6878 ldr r0, [r7, #4]
|
|
8011c0a: f00a ffe5 bl 801cbd8 <sys_arch_unprotect>
|
|
|
|
if (!queued) {
|
|
8011c0e: 78fb ldrb r3, [r7, #3]
|
|
8011c10: 2b00 cmp r3, #0
|
|
8011c12: d10f bne.n 8011c34 <pbuf_pool_is_empty+0x44>
|
|
/* queue a call to pbuf_free_ooseq if not already queued */
|
|
PBUF_POOL_FREE_OOSEQ_QUEUE_CALL();
|
|
8011c14: 2100 movs r1, #0
|
|
8011c16: 480a ldr r0, [pc, #40] ; (8011c40 <pbuf_pool_is_empty+0x50>)
|
|
8011c18: f7fe fee0 bl 80109dc <tcpip_try_callback>
|
|
8011c1c: 4603 mov r3, r0
|
|
8011c1e: 2b00 cmp r3, #0
|
|
8011c20: d008 beq.n 8011c34 <pbuf_pool_is_empty+0x44>
|
|
8011c22: f00a ffcb bl 801cbbc <sys_arch_protect>
|
|
8011c26: 6078 str r0, [r7, #4]
|
|
8011c28: 4b04 ldr r3, [pc, #16] ; (8011c3c <pbuf_pool_is_empty+0x4c>)
|
|
8011c2a: 2200 movs r2, #0
|
|
8011c2c: 701a strb r2, [r3, #0]
|
|
8011c2e: 6878 ldr r0, [r7, #4]
|
|
8011c30: f00a ffd2 bl 801cbd8 <sys_arch_unprotect>
|
|
}
|
|
#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */
|
|
}
|
|
8011c34: bf00 nop
|
|
8011c36: 3708 adds r7, #8
|
|
8011c38: 46bd mov sp, r7
|
|
8011c3a: bd80 pop {r7, pc}
|
|
8011c3c: 2000f7f4 .word 0x2000f7f4
|
|
8011c40: 08011bdd .word 0x08011bdd
|
|
|
|
08011c44 <pbuf_init_alloced_pbuf>:
|
|
#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */
|
|
|
|
/* Initialize members of struct pbuf after allocation */
|
|
static void
|
|
pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags)
|
|
{
|
|
8011c44: b480 push {r7}
|
|
8011c46: b085 sub sp, #20
|
|
8011c48: af00 add r7, sp, #0
|
|
8011c4a: 60f8 str r0, [r7, #12]
|
|
8011c4c: 60b9 str r1, [r7, #8]
|
|
8011c4e: 4611 mov r1, r2
|
|
8011c50: 461a mov r2, r3
|
|
8011c52: 460b mov r3, r1
|
|
8011c54: 80fb strh r3, [r7, #6]
|
|
8011c56: 4613 mov r3, r2
|
|
8011c58: 80bb strh r3, [r7, #4]
|
|
p->next = NULL;
|
|
8011c5a: 68fb ldr r3, [r7, #12]
|
|
8011c5c: 2200 movs r2, #0
|
|
8011c5e: 601a str r2, [r3, #0]
|
|
p->payload = payload;
|
|
8011c60: 68fb ldr r3, [r7, #12]
|
|
8011c62: 68ba ldr r2, [r7, #8]
|
|
8011c64: 605a str r2, [r3, #4]
|
|
p->tot_len = tot_len;
|
|
8011c66: 68fb ldr r3, [r7, #12]
|
|
8011c68: 88fa ldrh r2, [r7, #6]
|
|
8011c6a: 811a strh r2, [r3, #8]
|
|
p->len = len;
|
|
8011c6c: 68fb ldr r3, [r7, #12]
|
|
8011c6e: 88ba ldrh r2, [r7, #4]
|
|
8011c70: 815a strh r2, [r3, #10]
|
|
p->type_internal = (u8_t)type;
|
|
8011c72: 8b3b ldrh r3, [r7, #24]
|
|
8011c74: b2da uxtb r2, r3
|
|
8011c76: 68fb ldr r3, [r7, #12]
|
|
8011c78: 731a strb r2, [r3, #12]
|
|
p->flags = flags;
|
|
8011c7a: 68fb ldr r3, [r7, #12]
|
|
8011c7c: 7f3a ldrb r2, [r7, #28]
|
|
8011c7e: 735a strb r2, [r3, #13]
|
|
p->ref = 1;
|
|
8011c80: 68fb ldr r3, [r7, #12]
|
|
8011c82: 2201 movs r2, #1
|
|
8011c84: 739a strb r2, [r3, #14]
|
|
p->if_idx = NETIF_NO_INDEX;
|
|
8011c86: 68fb ldr r3, [r7, #12]
|
|
8011c88: 2200 movs r2, #0
|
|
8011c8a: 73da strb r2, [r3, #15]
|
|
}
|
|
8011c8c: bf00 nop
|
|
8011c8e: 3714 adds r7, #20
|
|
8011c90: 46bd mov sp, r7
|
|
8011c92: f85d 7b04 ldr.w r7, [sp], #4
|
|
8011c96: 4770 bx lr
|
|
|
|
08011c98 <pbuf_alloc>:
|
|
* @return the allocated pbuf. If multiple pbufs where allocated, this
|
|
* is the first pbuf of a pbuf chain.
|
|
*/
|
|
struct pbuf *
|
|
pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type)
|
|
{
|
|
8011c98: b580 push {r7, lr}
|
|
8011c9a: b08c sub sp, #48 ; 0x30
|
|
8011c9c: af02 add r7, sp, #8
|
|
8011c9e: 4603 mov r3, r0
|
|
8011ca0: 71fb strb r3, [r7, #7]
|
|
8011ca2: 460b mov r3, r1
|
|
8011ca4: 80bb strh r3, [r7, #4]
|
|
8011ca6: 4613 mov r3, r2
|
|
8011ca8: 807b strh r3, [r7, #2]
|
|
struct pbuf *p;
|
|
u16_t offset = (u16_t)layer;
|
|
8011caa: 79fb ldrb r3, [r7, #7]
|
|
8011cac: 847b strh r3, [r7, #34] ; 0x22
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length));
|
|
|
|
switch (type) {
|
|
8011cae: 887b ldrh r3, [r7, #2]
|
|
8011cb0: 2b41 cmp r3, #65 ; 0x41
|
|
8011cb2: d00b beq.n 8011ccc <pbuf_alloc+0x34>
|
|
8011cb4: 2b41 cmp r3, #65 ; 0x41
|
|
8011cb6: dc02 bgt.n 8011cbe <pbuf_alloc+0x26>
|
|
8011cb8: 2b01 cmp r3, #1
|
|
8011cba: d007 beq.n 8011ccc <pbuf_alloc+0x34>
|
|
8011cbc: e0c2 b.n 8011e44 <pbuf_alloc+0x1ac>
|
|
8011cbe: f5b3 7fc1 cmp.w r3, #386 ; 0x182
|
|
8011cc2: d00b beq.n 8011cdc <pbuf_alloc+0x44>
|
|
8011cc4: f5b3 7f20 cmp.w r3, #640 ; 0x280
|
|
8011cc8: d070 beq.n 8011dac <pbuf_alloc+0x114>
|
|
8011cca: e0bb b.n 8011e44 <pbuf_alloc+0x1ac>
|
|
case PBUF_REF: /* fall through */
|
|
case PBUF_ROM:
|
|
p = pbuf_alloc_reference(NULL, length, type);
|
|
8011ccc: 887a ldrh r2, [r7, #2]
|
|
8011cce: 88bb ldrh r3, [r7, #4]
|
|
8011cd0: 4619 mov r1, r3
|
|
8011cd2: 2000 movs r0, #0
|
|
8011cd4: f000 f8d2 bl 8011e7c <pbuf_alloc_reference>
|
|
8011cd8: 6278 str r0, [r7, #36] ; 0x24
|
|
break;
|
|
8011cda: e0bd b.n 8011e58 <pbuf_alloc+0x1c0>
|
|
case PBUF_POOL: {
|
|
struct pbuf *q, *last;
|
|
u16_t rem_len; /* remaining length */
|
|
p = NULL;
|
|
8011cdc: 2300 movs r3, #0
|
|
8011cde: 627b str r3, [r7, #36] ; 0x24
|
|
last = NULL;
|
|
8011ce0: 2300 movs r3, #0
|
|
8011ce2: 61fb str r3, [r7, #28]
|
|
rem_len = length;
|
|
8011ce4: 88bb ldrh r3, [r7, #4]
|
|
8011ce6: 837b strh r3, [r7, #26]
|
|
do {
|
|
u16_t qlen;
|
|
q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL);
|
|
8011ce8: 200c movs r0, #12
|
|
8011cea: f7ff fbb7 bl 801145c <memp_malloc>
|
|
8011cee: 6138 str r0, [r7, #16]
|
|
if (q == NULL) {
|
|
8011cf0: 693b ldr r3, [r7, #16]
|
|
8011cf2: 2b00 cmp r3, #0
|
|
8011cf4: d109 bne.n 8011d0a <pbuf_alloc+0x72>
|
|
PBUF_POOL_IS_EMPTY();
|
|
8011cf6: f7ff ff7b bl 8011bf0 <pbuf_pool_is_empty>
|
|
/* free chain so far allocated */
|
|
if (p) {
|
|
8011cfa: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8011cfc: 2b00 cmp r3, #0
|
|
8011cfe: d002 beq.n 8011d06 <pbuf_alloc+0x6e>
|
|
pbuf_free(p);
|
|
8011d00: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
8011d02: f000 faa9 bl 8012258 <pbuf_free>
|
|
}
|
|
/* bail out unsuccessfully */
|
|
return NULL;
|
|
8011d06: 2300 movs r3, #0
|
|
8011d08: e0a7 b.n 8011e5a <pbuf_alloc+0x1c2>
|
|
}
|
|
qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)));
|
|
8011d0a: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
8011d0c: 3303 adds r3, #3
|
|
8011d0e: b29b uxth r3, r3
|
|
8011d10: f023 0303 bic.w r3, r3, #3
|
|
8011d14: b29b uxth r3, r3
|
|
8011d16: f5c3 7314 rsb r3, r3, #592 ; 0x250
|
|
8011d1a: b29b uxth r3, r3
|
|
8011d1c: 8b7a ldrh r2, [r7, #26]
|
|
8011d1e: 4293 cmp r3, r2
|
|
8011d20: bf28 it cs
|
|
8011d22: 4613 movcs r3, r2
|
|
8011d24: 81fb strh r3, [r7, #14]
|
|
pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)),
|
|
8011d26: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
8011d28: 3310 adds r3, #16
|
|
8011d2a: 693a ldr r2, [r7, #16]
|
|
8011d2c: 4413 add r3, r2
|
|
8011d2e: 3303 adds r3, #3
|
|
8011d30: f023 0303 bic.w r3, r3, #3
|
|
8011d34: 4618 mov r0, r3
|
|
8011d36: 89f9 ldrh r1, [r7, #14]
|
|
8011d38: 8b7a ldrh r2, [r7, #26]
|
|
8011d3a: 2300 movs r3, #0
|
|
8011d3c: 9301 str r3, [sp, #4]
|
|
8011d3e: 887b ldrh r3, [r7, #2]
|
|
8011d40: 9300 str r3, [sp, #0]
|
|
8011d42: 460b mov r3, r1
|
|
8011d44: 4601 mov r1, r0
|
|
8011d46: 6938 ldr r0, [r7, #16]
|
|
8011d48: f7ff ff7c bl 8011c44 <pbuf_init_alloced_pbuf>
|
|
rem_len, qlen, type, 0);
|
|
LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned",
|
|
8011d4c: 693b ldr r3, [r7, #16]
|
|
8011d4e: 685b ldr r3, [r3, #4]
|
|
8011d50: f003 0303 and.w r3, r3, #3
|
|
8011d54: 2b00 cmp r3, #0
|
|
8011d56: d006 beq.n 8011d66 <pbuf_alloc+0xce>
|
|
8011d58: 4b42 ldr r3, [pc, #264] ; (8011e64 <pbuf_alloc+0x1cc>)
|
|
8011d5a: f240 1201 movw r2, #257 ; 0x101
|
|
8011d5e: 4942 ldr r1, [pc, #264] ; (8011e68 <pbuf_alloc+0x1d0>)
|
|
8011d60: 4842 ldr r0, [pc, #264] ; (8011e6c <pbuf_alloc+0x1d4>)
|
|
8011d62: f00a ffa9 bl 801ccb8 <iprintf>
|
|
((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0);
|
|
LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT",
|
|
8011d66: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
8011d68: 3303 adds r3, #3
|
|
8011d6a: f023 0303 bic.w r3, r3, #3
|
|
8011d6e: f5b3 7f14 cmp.w r3, #592 ; 0x250
|
|
8011d72: d106 bne.n 8011d82 <pbuf_alloc+0xea>
|
|
8011d74: 4b3b ldr r3, [pc, #236] ; (8011e64 <pbuf_alloc+0x1cc>)
|
|
8011d76: f240 1203 movw r2, #259 ; 0x103
|
|
8011d7a: 493d ldr r1, [pc, #244] ; (8011e70 <pbuf_alloc+0x1d8>)
|
|
8011d7c: 483b ldr r0, [pc, #236] ; (8011e6c <pbuf_alloc+0x1d4>)
|
|
8011d7e: f00a ff9b bl 801ccb8 <iprintf>
|
|
(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 );
|
|
if (p == NULL) {
|
|
8011d82: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8011d84: 2b00 cmp r3, #0
|
|
8011d86: d102 bne.n 8011d8e <pbuf_alloc+0xf6>
|
|
/* allocated head of pbuf chain (into p) */
|
|
p = q;
|
|
8011d88: 693b ldr r3, [r7, #16]
|
|
8011d8a: 627b str r3, [r7, #36] ; 0x24
|
|
8011d8c: e002 b.n 8011d94 <pbuf_alloc+0xfc>
|
|
} else {
|
|
/* make previous pbuf point to this pbuf */
|
|
last->next = q;
|
|
8011d8e: 69fb ldr r3, [r7, #28]
|
|
8011d90: 693a ldr r2, [r7, #16]
|
|
8011d92: 601a str r2, [r3, #0]
|
|
}
|
|
last = q;
|
|
8011d94: 693b ldr r3, [r7, #16]
|
|
8011d96: 61fb str r3, [r7, #28]
|
|
rem_len = (u16_t)(rem_len - qlen);
|
|
8011d98: 8b7a ldrh r2, [r7, #26]
|
|
8011d9a: 89fb ldrh r3, [r7, #14]
|
|
8011d9c: 1ad3 subs r3, r2, r3
|
|
8011d9e: 837b strh r3, [r7, #26]
|
|
offset = 0;
|
|
8011da0: 2300 movs r3, #0
|
|
8011da2: 847b strh r3, [r7, #34] ; 0x22
|
|
} while (rem_len > 0);
|
|
8011da4: 8b7b ldrh r3, [r7, #26]
|
|
8011da6: 2b00 cmp r3, #0
|
|
8011da8: d19e bne.n 8011ce8 <pbuf_alloc+0x50>
|
|
break;
|
|
8011daa: e055 b.n 8011e58 <pbuf_alloc+0x1c0>
|
|
}
|
|
case PBUF_RAM: {
|
|
u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length));
|
|
8011dac: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
8011dae: 3303 adds r3, #3
|
|
8011db0: b29b uxth r3, r3
|
|
8011db2: f023 0303 bic.w r3, r3, #3
|
|
8011db6: b29a uxth r2, r3
|
|
8011db8: 88bb ldrh r3, [r7, #4]
|
|
8011dba: 3303 adds r3, #3
|
|
8011dbc: b29b uxth r3, r3
|
|
8011dbe: f023 0303 bic.w r3, r3, #3
|
|
8011dc2: b29b uxth r3, r3
|
|
8011dc4: 4413 add r3, r2
|
|
8011dc6: 833b strh r3, [r7, #24]
|
|
mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len);
|
|
8011dc8: 8b3b ldrh r3, [r7, #24]
|
|
8011dca: 3310 adds r3, #16
|
|
8011dcc: 82fb strh r3, [r7, #22]
|
|
|
|
/* bug #50040: Check for integer overflow when calculating alloc_len */
|
|
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
|
|
8011dce: 8b3a ldrh r2, [r7, #24]
|
|
8011dd0: 88bb ldrh r3, [r7, #4]
|
|
8011dd2: 3303 adds r3, #3
|
|
8011dd4: f023 0303 bic.w r3, r3, #3
|
|
8011dd8: 429a cmp r2, r3
|
|
8011dda: d306 bcc.n 8011dea <pbuf_alloc+0x152>
|
|
(alloc_len < LWIP_MEM_ALIGN_SIZE(length))) {
|
|
8011ddc: 8afa ldrh r2, [r7, #22]
|
|
8011dde: 88bb ldrh r3, [r7, #4]
|
|
8011de0: 3303 adds r3, #3
|
|
8011de2: f023 0303 bic.w r3, r3, #3
|
|
if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) ||
|
|
8011de6: 429a cmp r2, r3
|
|
8011de8: d201 bcs.n 8011dee <pbuf_alloc+0x156>
|
|
return NULL;
|
|
8011dea: 2300 movs r3, #0
|
|
8011dec: e035 b.n 8011e5a <pbuf_alloc+0x1c2>
|
|
}
|
|
|
|
/* If pbuf is to be allocated in RAM, allocate memory for it. */
|
|
p = (struct pbuf *)mem_malloc(alloc_len);
|
|
8011dee: 8afb ldrh r3, [r7, #22]
|
|
8011df0: 4618 mov r0, r3
|
|
8011df2: f7ff f9b1 bl 8011158 <mem_malloc>
|
|
8011df6: 6278 str r0, [r7, #36] ; 0x24
|
|
if (p == NULL) {
|
|
8011df8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8011dfa: 2b00 cmp r3, #0
|
|
8011dfc: d101 bne.n 8011e02 <pbuf_alloc+0x16a>
|
|
return NULL;
|
|
8011dfe: 2300 movs r3, #0
|
|
8011e00: e02b b.n 8011e5a <pbuf_alloc+0x1c2>
|
|
}
|
|
pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)),
|
|
8011e02: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
8011e04: 3310 adds r3, #16
|
|
8011e06: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8011e08: 4413 add r3, r2
|
|
8011e0a: 3303 adds r3, #3
|
|
8011e0c: f023 0303 bic.w r3, r3, #3
|
|
8011e10: 4618 mov r0, r3
|
|
8011e12: 88b9 ldrh r1, [r7, #4]
|
|
8011e14: 88ba ldrh r2, [r7, #4]
|
|
8011e16: 2300 movs r3, #0
|
|
8011e18: 9301 str r3, [sp, #4]
|
|
8011e1a: 887b ldrh r3, [r7, #2]
|
|
8011e1c: 9300 str r3, [sp, #0]
|
|
8011e1e: 460b mov r3, r1
|
|
8011e20: 4601 mov r1, r0
|
|
8011e22: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
8011e24: f7ff ff0e bl 8011c44 <pbuf_init_alloced_pbuf>
|
|
length, length, type, 0);
|
|
LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned",
|
|
8011e28: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8011e2a: 685b ldr r3, [r3, #4]
|
|
8011e2c: f003 0303 and.w r3, r3, #3
|
|
8011e30: 2b00 cmp r3, #0
|
|
8011e32: d010 beq.n 8011e56 <pbuf_alloc+0x1be>
|
|
8011e34: 4b0b ldr r3, [pc, #44] ; (8011e64 <pbuf_alloc+0x1cc>)
|
|
8011e36: f240 1223 movw r2, #291 ; 0x123
|
|
8011e3a: 490e ldr r1, [pc, #56] ; (8011e74 <pbuf_alloc+0x1dc>)
|
|
8011e3c: 480b ldr r0, [pc, #44] ; (8011e6c <pbuf_alloc+0x1d4>)
|
|
8011e3e: f00a ff3b bl 801ccb8 <iprintf>
|
|
((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0);
|
|
break;
|
|
8011e42: e008 b.n 8011e56 <pbuf_alloc+0x1be>
|
|
}
|
|
default:
|
|
LWIP_ASSERT("pbuf_alloc: erroneous type", 0);
|
|
8011e44: 4b07 ldr r3, [pc, #28] ; (8011e64 <pbuf_alloc+0x1cc>)
|
|
8011e46: f240 1227 movw r2, #295 ; 0x127
|
|
8011e4a: 490b ldr r1, [pc, #44] ; (8011e78 <pbuf_alloc+0x1e0>)
|
|
8011e4c: 4807 ldr r0, [pc, #28] ; (8011e6c <pbuf_alloc+0x1d4>)
|
|
8011e4e: f00a ff33 bl 801ccb8 <iprintf>
|
|
return NULL;
|
|
8011e52: 2300 movs r3, #0
|
|
8011e54: e001 b.n 8011e5a <pbuf_alloc+0x1c2>
|
|
break;
|
|
8011e56: bf00 nop
|
|
}
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p));
|
|
return p;
|
|
8011e58: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
}
|
|
8011e5a: 4618 mov r0, r3
|
|
8011e5c: 3728 adds r7, #40 ; 0x28
|
|
8011e5e: 46bd mov sp, r7
|
|
8011e60: bd80 pop {r7, pc}
|
|
8011e62: bf00 nop
|
|
8011e64: 0801e648 .word 0x0801e648
|
|
8011e68: 0801e678 .word 0x0801e678
|
|
8011e6c: 0801e6a8 .word 0x0801e6a8
|
|
8011e70: 0801e6d0 .word 0x0801e6d0
|
|
8011e74: 0801e704 .word 0x0801e704
|
|
8011e78: 0801e730 .word 0x0801e730
|
|
|
|
08011e7c <pbuf_alloc_reference>:
|
|
*
|
|
* @return the allocated pbuf.
|
|
*/
|
|
struct pbuf *
|
|
pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type)
|
|
{
|
|
8011e7c: b580 push {r7, lr}
|
|
8011e7e: b086 sub sp, #24
|
|
8011e80: af02 add r7, sp, #8
|
|
8011e82: 6078 str r0, [r7, #4]
|
|
8011e84: 460b mov r3, r1
|
|
8011e86: 807b strh r3, [r7, #2]
|
|
8011e88: 4613 mov r3, r2
|
|
8011e8a: 803b strh r3, [r7, #0]
|
|
struct pbuf *p;
|
|
LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM));
|
|
8011e8c: 883b ldrh r3, [r7, #0]
|
|
8011e8e: 2b41 cmp r3, #65 ; 0x41
|
|
8011e90: d009 beq.n 8011ea6 <pbuf_alloc_reference+0x2a>
|
|
8011e92: 883b ldrh r3, [r7, #0]
|
|
8011e94: 2b01 cmp r3, #1
|
|
8011e96: d006 beq.n 8011ea6 <pbuf_alloc_reference+0x2a>
|
|
8011e98: 4b0f ldr r3, [pc, #60] ; (8011ed8 <pbuf_alloc_reference+0x5c>)
|
|
8011e9a: f44f 72a5 mov.w r2, #330 ; 0x14a
|
|
8011e9e: 490f ldr r1, [pc, #60] ; (8011edc <pbuf_alloc_reference+0x60>)
|
|
8011ea0: 480f ldr r0, [pc, #60] ; (8011ee0 <pbuf_alloc_reference+0x64>)
|
|
8011ea2: f00a ff09 bl 801ccb8 <iprintf>
|
|
/* only allocate memory for the pbuf structure */
|
|
p = (struct pbuf *)memp_malloc(MEMP_PBUF);
|
|
8011ea6: 200b movs r0, #11
|
|
8011ea8: f7ff fad8 bl 801145c <memp_malloc>
|
|
8011eac: 60f8 str r0, [r7, #12]
|
|
if (p == NULL) {
|
|
8011eae: 68fb ldr r3, [r7, #12]
|
|
8011eb0: 2b00 cmp r3, #0
|
|
8011eb2: d101 bne.n 8011eb8 <pbuf_alloc_reference+0x3c>
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
|
|
("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n",
|
|
(type == PBUF_ROM) ? "ROM" : "REF"));
|
|
return NULL;
|
|
8011eb4: 2300 movs r3, #0
|
|
8011eb6: e00b b.n 8011ed0 <pbuf_alloc_reference+0x54>
|
|
}
|
|
pbuf_init_alloced_pbuf(p, payload, length, length, type, 0);
|
|
8011eb8: 8879 ldrh r1, [r7, #2]
|
|
8011eba: 887a ldrh r2, [r7, #2]
|
|
8011ebc: 2300 movs r3, #0
|
|
8011ebe: 9301 str r3, [sp, #4]
|
|
8011ec0: 883b ldrh r3, [r7, #0]
|
|
8011ec2: 9300 str r3, [sp, #0]
|
|
8011ec4: 460b mov r3, r1
|
|
8011ec6: 6879 ldr r1, [r7, #4]
|
|
8011ec8: 68f8 ldr r0, [r7, #12]
|
|
8011eca: f7ff febb bl 8011c44 <pbuf_init_alloced_pbuf>
|
|
return p;
|
|
8011ece: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8011ed0: 4618 mov r0, r3
|
|
8011ed2: 3710 adds r7, #16
|
|
8011ed4: 46bd mov sp, r7
|
|
8011ed6: bd80 pop {r7, pc}
|
|
8011ed8: 0801e648 .word 0x0801e648
|
|
8011edc: 0801e74c .word 0x0801e74c
|
|
8011ee0: 0801e6a8 .word 0x0801e6a8
|
|
|
|
08011ee4 <pbuf_alloced_custom>:
|
|
* big enough to hold 'length' plus the header size
|
|
*/
|
|
struct pbuf *
|
|
pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p,
|
|
void *payload_mem, u16_t payload_mem_len)
|
|
{
|
|
8011ee4: b580 push {r7, lr}
|
|
8011ee6: b088 sub sp, #32
|
|
8011ee8: af02 add r7, sp, #8
|
|
8011eea: 607b str r3, [r7, #4]
|
|
8011eec: 4603 mov r3, r0
|
|
8011eee: 73fb strb r3, [r7, #15]
|
|
8011ef0: 460b mov r3, r1
|
|
8011ef2: 81bb strh r3, [r7, #12]
|
|
8011ef4: 4613 mov r3, r2
|
|
8011ef6: 817b strh r3, [r7, #10]
|
|
u16_t offset = (u16_t)l;
|
|
8011ef8: 7bfb ldrb r3, [r7, #15]
|
|
8011efa: 827b strh r3, [r7, #18]
|
|
void *payload;
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length));
|
|
|
|
if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) {
|
|
8011efc: 8a7b ldrh r3, [r7, #18]
|
|
8011efe: 3303 adds r3, #3
|
|
8011f00: f023 0203 bic.w r2, r3, #3
|
|
8011f04: 89bb ldrh r3, [r7, #12]
|
|
8011f06: 441a add r2, r3
|
|
8011f08: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
8011f0a: 429a cmp r2, r3
|
|
8011f0c: d901 bls.n 8011f12 <pbuf_alloced_custom+0x2e>
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length));
|
|
return NULL;
|
|
8011f0e: 2300 movs r3, #0
|
|
8011f10: e018 b.n 8011f44 <pbuf_alloced_custom+0x60>
|
|
}
|
|
|
|
if (payload_mem != NULL) {
|
|
8011f12: 6a3b ldr r3, [r7, #32]
|
|
8011f14: 2b00 cmp r3, #0
|
|
8011f16: d007 beq.n 8011f28 <pbuf_alloced_custom+0x44>
|
|
payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset);
|
|
8011f18: 8a7b ldrh r3, [r7, #18]
|
|
8011f1a: 3303 adds r3, #3
|
|
8011f1c: f023 0303 bic.w r3, r3, #3
|
|
8011f20: 6a3a ldr r2, [r7, #32]
|
|
8011f22: 4413 add r3, r2
|
|
8011f24: 617b str r3, [r7, #20]
|
|
8011f26: e001 b.n 8011f2c <pbuf_alloced_custom+0x48>
|
|
} else {
|
|
payload = NULL;
|
|
8011f28: 2300 movs r3, #0
|
|
8011f2a: 617b str r3, [r7, #20]
|
|
}
|
|
pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM);
|
|
8011f2c: 6878 ldr r0, [r7, #4]
|
|
8011f2e: 89b9 ldrh r1, [r7, #12]
|
|
8011f30: 89ba ldrh r2, [r7, #12]
|
|
8011f32: 2302 movs r3, #2
|
|
8011f34: 9301 str r3, [sp, #4]
|
|
8011f36: 897b ldrh r3, [r7, #10]
|
|
8011f38: 9300 str r3, [sp, #0]
|
|
8011f3a: 460b mov r3, r1
|
|
8011f3c: 6979 ldr r1, [r7, #20]
|
|
8011f3e: f7ff fe81 bl 8011c44 <pbuf_init_alloced_pbuf>
|
|
return &p->pbuf;
|
|
8011f42: 687b ldr r3, [r7, #4]
|
|
}
|
|
8011f44: 4618 mov r0, r3
|
|
8011f46: 3718 adds r7, #24
|
|
8011f48: 46bd mov sp, r7
|
|
8011f4a: bd80 pop {r7, pc}
|
|
|
|
08011f4c <pbuf_realloc>:
|
|
*
|
|
* @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain).
|
|
*/
|
|
void
|
|
pbuf_realloc(struct pbuf *p, u16_t new_len)
|
|
{
|
|
8011f4c: b580 push {r7, lr}
|
|
8011f4e: b084 sub sp, #16
|
|
8011f50: af00 add r7, sp, #0
|
|
8011f52: 6078 str r0, [r7, #4]
|
|
8011f54: 460b mov r3, r1
|
|
8011f56: 807b strh r3, [r7, #2]
|
|
struct pbuf *q;
|
|
u16_t rem_len; /* remaining length */
|
|
u16_t shrink;
|
|
|
|
LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL);
|
|
8011f58: 687b ldr r3, [r7, #4]
|
|
8011f5a: 2b00 cmp r3, #0
|
|
8011f5c: d106 bne.n 8011f6c <pbuf_realloc+0x20>
|
|
8011f5e: 4b3a ldr r3, [pc, #232] ; (8012048 <pbuf_realloc+0xfc>)
|
|
8011f60: f44f 72cc mov.w r2, #408 ; 0x198
|
|
8011f64: 4939 ldr r1, [pc, #228] ; (801204c <pbuf_realloc+0x100>)
|
|
8011f66: 483a ldr r0, [pc, #232] ; (8012050 <pbuf_realloc+0x104>)
|
|
8011f68: f00a fea6 bl 801ccb8 <iprintf>
|
|
|
|
/* desired length larger than current length? */
|
|
if (new_len >= p->tot_len) {
|
|
8011f6c: 687b ldr r3, [r7, #4]
|
|
8011f6e: 891b ldrh r3, [r3, #8]
|
|
8011f70: 887a ldrh r2, [r7, #2]
|
|
8011f72: 429a cmp r2, r3
|
|
8011f74: d264 bcs.n 8012040 <pbuf_realloc+0xf4>
|
|
return;
|
|
}
|
|
|
|
/* the pbuf chain grows by (new_len - p->tot_len) bytes
|
|
* (which may be negative in case of shrinking) */
|
|
shrink = (u16_t)(p->tot_len - new_len);
|
|
8011f76: 687b ldr r3, [r7, #4]
|
|
8011f78: 891a ldrh r2, [r3, #8]
|
|
8011f7a: 887b ldrh r3, [r7, #2]
|
|
8011f7c: 1ad3 subs r3, r2, r3
|
|
8011f7e: 813b strh r3, [r7, #8]
|
|
|
|
/* first, step over any pbufs that should remain in the chain */
|
|
rem_len = new_len;
|
|
8011f80: 887b ldrh r3, [r7, #2]
|
|
8011f82: 817b strh r3, [r7, #10]
|
|
q = p;
|
|
8011f84: 687b ldr r3, [r7, #4]
|
|
8011f86: 60fb str r3, [r7, #12]
|
|
/* should this pbuf be kept? */
|
|
while (rem_len > q->len) {
|
|
8011f88: e018 b.n 8011fbc <pbuf_realloc+0x70>
|
|
/* decrease remaining length by pbuf length */
|
|
rem_len = (u16_t)(rem_len - q->len);
|
|
8011f8a: 68fb ldr r3, [r7, #12]
|
|
8011f8c: 895b ldrh r3, [r3, #10]
|
|
8011f8e: 897a ldrh r2, [r7, #10]
|
|
8011f90: 1ad3 subs r3, r2, r3
|
|
8011f92: 817b strh r3, [r7, #10]
|
|
/* decrease total length indicator */
|
|
q->tot_len = (u16_t)(q->tot_len - shrink);
|
|
8011f94: 68fb ldr r3, [r7, #12]
|
|
8011f96: 891a ldrh r2, [r3, #8]
|
|
8011f98: 893b ldrh r3, [r7, #8]
|
|
8011f9a: 1ad3 subs r3, r2, r3
|
|
8011f9c: b29a uxth r2, r3
|
|
8011f9e: 68fb ldr r3, [r7, #12]
|
|
8011fa0: 811a strh r2, [r3, #8]
|
|
/* proceed to next pbuf in chain */
|
|
q = q->next;
|
|
8011fa2: 68fb ldr r3, [r7, #12]
|
|
8011fa4: 681b ldr r3, [r3, #0]
|
|
8011fa6: 60fb str r3, [r7, #12]
|
|
LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL);
|
|
8011fa8: 68fb ldr r3, [r7, #12]
|
|
8011faa: 2b00 cmp r3, #0
|
|
8011fac: d106 bne.n 8011fbc <pbuf_realloc+0x70>
|
|
8011fae: 4b26 ldr r3, [pc, #152] ; (8012048 <pbuf_realloc+0xfc>)
|
|
8011fb0: f240 12af movw r2, #431 ; 0x1af
|
|
8011fb4: 4927 ldr r1, [pc, #156] ; (8012054 <pbuf_realloc+0x108>)
|
|
8011fb6: 4826 ldr r0, [pc, #152] ; (8012050 <pbuf_realloc+0x104>)
|
|
8011fb8: f00a fe7e bl 801ccb8 <iprintf>
|
|
while (rem_len > q->len) {
|
|
8011fbc: 68fb ldr r3, [r7, #12]
|
|
8011fbe: 895b ldrh r3, [r3, #10]
|
|
8011fc0: 897a ldrh r2, [r7, #10]
|
|
8011fc2: 429a cmp r2, r3
|
|
8011fc4: d8e1 bhi.n 8011f8a <pbuf_realloc+0x3e>
|
|
/* we have now reached the new last pbuf (in q) */
|
|
/* rem_len == desired length for pbuf q */
|
|
|
|
/* shrink allocated memory for PBUF_RAM */
|
|
/* (other types merely adjust their length fields */
|
|
if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len)
|
|
8011fc6: 68fb ldr r3, [r7, #12]
|
|
8011fc8: 7b1b ldrb r3, [r3, #12]
|
|
8011fca: f003 030f and.w r3, r3, #15
|
|
8011fce: 2b00 cmp r3, #0
|
|
8011fd0: d122 bne.n 8012018 <pbuf_realloc+0xcc>
|
|
8011fd2: 68fb ldr r3, [r7, #12]
|
|
8011fd4: 895b ldrh r3, [r3, #10]
|
|
8011fd6: 897a ldrh r2, [r7, #10]
|
|
8011fd8: 429a cmp r2, r3
|
|
8011fda: d01d beq.n 8012018 <pbuf_realloc+0xcc>
|
|
#if LWIP_SUPPORT_CUSTOM_PBUF
|
|
&& ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0)
|
|
8011fdc: 68fb ldr r3, [r7, #12]
|
|
8011fde: 7b5b ldrb r3, [r3, #13]
|
|
8011fe0: f003 0302 and.w r3, r3, #2
|
|
8011fe4: 2b00 cmp r3, #0
|
|
8011fe6: d117 bne.n 8012018 <pbuf_realloc+0xcc>
|
|
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
|
|
) {
|
|
/* reallocate and adjust the length of the pbuf that will be split */
|
|
q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len));
|
|
8011fe8: 68fb ldr r3, [r7, #12]
|
|
8011fea: 685b ldr r3, [r3, #4]
|
|
8011fec: 461a mov r2, r3
|
|
8011fee: 68fb ldr r3, [r7, #12]
|
|
8011ff0: 1ad3 subs r3, r2, r3
|
|
8011ff2: b29a uxth r2, r3
|
|
8011ff4: 897b ldrh r3, [r7, #10]
|
|
8011ff6: 4413 add r3, r2
|
|
8011ff8: b29b uxth r3, r3
|
|
8011ffa: 4619 mov r1, r3
|
|
8011ffc: 68f8 ldr r0, [r7, #12]
|
|
8011ffe: f7fe ffa1 bl 8010f44 <mem_trim>
|
|
8012002: 60f8 str r0, [r7, #12]
|
|
LWIP_ASSERT("mem_trim returned q == NULL", q != NULL);
|
|
8012004: 68fb ldr r3, [r7, #12]
|
|
8012006: 2b00 cmp r3, #0
|
|
8012008: d106 bne.n 8012018 <pbuf_realloc+0xcc>
|
|
801200a: 4b0f ldr r3, [pc, #60] ; (8012048 <pbuf_realloc+0xfc>)
|
|
801200c: f240 12bd movw r2, #445 ; 0x1bd
|
|
8012010: 4911 ldr r1, [pc, #68] ; (8012058 <pbuf_realloc+0x10c>)
|
|
8012012: 480f ldr r0, [pc, #60] ; (8012050 <pbuf_realloc+0x104>)
|
|
8012014: f00a fe50 bl 801ccb8 <iprintf>
|
|
}
|
|
/* adjust length fields for new last pbuf */
|
|
q->len = rem_len;
|
|
8012018: 68fb ldr r3, [r7, #12]
|
|
801201a: 897a ldrh r2, [r7, #10]
|
|
801201c: 815a strh r2, [r3, #10]
|
|
q->tot_len = q->len;
|
|
801201e: 68fb ldr r3, [r7, #12]
|
|
8012020: 895a ldrh r2, [r3, #10]
|
|
8012022: 68fb ldr r3, [r7, #12]
|
|
8012024: 811a strh r2, [r3, #8]
|
|
|
|
/* any remaining pbufs in chain? */
|
|
if (q->next != NULL) {
|
|
8012026: 68fb ldr r3, [r7, #12]
|
|
8012028: 681b ldr r3, [r3, #0]
|
|
801202a: 2b00 cmp r3, #0
|
|
801202c: d004 beq.n 8012038 <pbuf_realloc+0xec>
|
|
/* free remaining pbufs in chain */
|
|
pbuf_free(q->next);
|
|
801202e: 68fb ldr r3, [r7, #12]
|
|
8012030: 681b ldr r3, [r3, #0]
|
|
8012032: 4618 mov r0, r3
|
|
8012034: f000 f910 bl 8012258 <pbuf_free>
|
|
}
|
|
/* q is last packet in chain */
|
|
q->next = NULL;
|
|
8012038: 68fb ldr r3, [r7, #12]
|
|
801203a: 2200 movs r2, #0
|
|
801203c: 601a str r2, [r3, #0]
|
|
801203e: e000 b.n 8012042 <pbuf_realloc+0xf6>
|
|
return;
|
|
8012040: bf00 nop
|
|
|
|
}
|
|
8012042: 3710 adds r7, #16
|
|
8012044: 46bd mov sp, r7
|
|
8012046: bd80 pop {r7, pc}
|
|
8012048: 0801e648 .word 0x0801e648
|
|
801204c: 0801e760 .word 0x0801e760
|
|
8012050: 0801e6a8 .word 0x0801e6a8
|
|
8012054: 0801e778 .word 0x0801e778
|
|
8012058: 0801e790 .word 0x0801e790
|
|
|
|
0801205c <pbuf_add_header_impl>:
|
|
* @return non-zero on failure, zero on success.
|
|
*
|
|
*/
|
|
static u8_t
|
|
pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force)
|
|
{
|
|
801205c: b580 push {r7, lr}
|
|
801205e: b086 sub sp, #24
|
|
8012060: af00 add r7, sp, #0
|
|
8012062: 60f8 str r0, [r7, #12]
|
|
8012064: 60b9 str r1, [r7, #8]
|
|
8012066: 4613 mov r3, r2
|
|
8012068: 71fb strb r3, [r7, #7]
|
|
u16_t type_internal;
|
|
void *payload;
|
|
u16_t increment_magnitude;
|
|
|
|
LWIP_ASSERT("p != NULL", p != NULL);
|
|
801206a: 68fb ldr r3, [r7, #12]
|
|
801206c: 2b00 cmp r3, #0
|
|
801206e: d106 bne.n 801207e <pbuf_add_header_impl+0x22>
|
|
8012070: 4b2b ldr r3, [pc, #172] ; (8012120 <pbuf_add_header_impl+0xc4>)
|
|
8012072: f240 12df movw r2, #479 ; 0x1df
|
|
8012076: 492b ldr r1, [pc, #172] ; (8012124 <pbuf_add_header_impl+0xc8>)
|
|
8012078: 482b ldr r0, [pc, #172] ; (8012128 <pbuf_add_header_impl+0xcc>)
|
|
801207a: f00a fe1d bl 801ccb8 <iprintf>
|
|
if ((p == NULL) || (header_size_increment > 0xFFFF)) {
|
|
801207e: 68fb ldr r3, [r7, #12]
|
|
8012080: 2b00 cmp r3, #0
|
|
8012082: d003 beq.n 801208c <pbuf_add_header_impl+0x30>
|
|
8012084: 68bb ldr r3, [r7, #8]
|
|
8012086: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
801208a: d301 bcc.n 8012090 <pbuf_add_header_impl+0x34>
|
|
return 1;
|
|
801208c: 2301 movs r3, #1
|
|
801208e: e043 b.n 8012118 <pbuf_add_header_impl+0xbc>
|
|
}
|
|
if (header_size_increment == 0) {
|
|
8012090: 68bb ldr r3, [r7, #8]
|
|
8012092: 2b00 cmp r3, #0
|
|
8012094: d101 bne.n 801209a <pbuf_add_header_impl+0x3e>
|
|
return 0;
|
|
8012096: 2300 movs r3, #0
|
|
8012098: e03e b.n 8012118 <pbuf_add_header_impl+0xbc>
|
|
}
|
|
|
|
increment_magnitude = (u16_t)header_size_increment;
|
|
801209a: 68bb ldr r3, [r7, #8]
|
|
801209c: 827b strh r3, [r7, #18]
|
|
/* Do not allow tot_len to wrap as a result. */
|
|
if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) {
|
|
801209e: 68fb ldr r3, [r7, #12]
|
|
80120a0: 891a ldrh r2, [r3, #8]
|
|
80120a2: 8a7b ldrh r3, [r7, #18]
|
|
80120a4: 4413 add r3, r2
|
|
80120a6: b29b uxth r3, r3
|
|
80120a8: 8a7a ldrh r2, [r7, #18]
|
|
80120aa: 429a cmp r2, r3
|
|
80120ac: d901 bls.n 80120b2 <pbuf_add_header_impl+0x56>
|
|
return 1;
|
|
80120ae: 2301 movs r3, #1
|
|
80120b0: e032 b.n 8012118 <pbuf_add_header_impl+0xbc>
|
|
}
|
|
|
|
type_internal = p->type_internal;
|
|
80120b2: 68fb ldr r3, [r7, #12]
|
|
80120b4: 7b1b ldrb r3, [r3, #12]
|
|
80120b6: 823b strh r3, [r7, #16]
|
|
|
|
/* pbuf types containing payloads? */
|
|
if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) {
|
|
80120b8: 8a3b ldrh r3, [r7, #16]
|
|
80120ba: f003 0380 and.w r3, r3, #128 ; 0x80
|
|
80120be: 2b00 cmp r3, #0
|
|
80120c0: d00c beq.n 80120dc <pbuf_add_header_impl+0x80>
|
|
/* set new payload pointer */
|
|
payload = (u8_t *)p->payload - header_size_increment;
|
|
80120c2: 68fb ldr r3, [r7, #12]
|
|
80120c4: 685a ldr r2, [r3, #4]
|
|
80120c6: 68bb ldr r3, [r7, #8]
|
|
80120c8: 425b negs r3, r3
|
|
80120ca: 4413 add r3, r2
|
|
80120cc: 617b str r3, [r7, #20]
|
|
/* boundary check fails? */
|
|
if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) {
|
|
80120ce: 68fb ldr r3, [r7, #12]
|
|
80120d0: 3310 adds r3, #16
|
|
80120d2: 697a ldr r2, [r7, #20]
|
|
80120d4: 429a cmp r2, r3
|
|
80120d6: d20d bcs.n 80120f4 <pbuf_add_header_impl+0x98>
|
|
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE,
|
|
("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n",
|
|
(void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF)));
|
|
/* bail out unsuccessfully */
|
|
return 1;
|
|
80120d8: 2301 movs r3, #1
|
|
80120da: e01d b.n 8012118 <pbuf_add_header_impl+0xbc>
|
|
}
|
|
/* pbuf types referring to external payloads? */
|
|
} else {
|
|
/* hide a header in the payload? */
|
|
if (force) {
|
|
80120dc: 79fb ldrb r3, [r7, #7]
|
|
80120de: 2b00 cmp r3, #0
|
|
80120e0: d006 beq.n 80120f0 <pbuf_add_header_impl+0x94>
|
|
payload = (u8_t *)p->payload - header_size_increment;
|
|
80120e2: 68fb ldr r3, [r7, #12]
|
|
80120e4: 685a ldr r2, [r3, #4]
|
|
80120e6: 68bb ldr r3, [r7, #8]
|
|
80120e8: 425b negs r3, r3
|
|
80120ea: 4413 add r3, r2
|
|
80120ec: 617b str r3, [r7, #20]
|
|
80120ee: e001 b.n 80120f4 <pbuf_add_header_impl+0x98>
|
|
} else {
|
|
/* cannot expand payload to front (yet!)
|
|
* bail out unsuccessfully */
|
|
return 1;
|
|
80120f0: 2301 movs r3, #1
|
|
80120f2: e011 b.n 8012118 <pbuf_add_header_impl+0xbc>
|
|
}
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n",
|
|
(void *)p->payload, (void *)payload, increment_magnitude));
|
|
|
|
/* modify pbuf fields */
|
|
p->payload = payload;
|
|
80120f4: 68fb ldr r3, [r7, #12]
|
|
80120f6: 697a ldr r2, [r7, #20]
|
|
80120f8: 605a str r2, [r3, #4]
|
|
p->len = (u16_t)(p->len + increment_magnitude);
|
|
80120fa: 68fb ldr r3, [r7, #12]
|
|
80120fc: 895a ldrh r2, [r3, #10]
|
|
80120fe: 8a7b ldrh r3, [r7, #18]
|
|
8012100: 4413 add r3, r2
|
|
8012102: b29a uxth r2, r3
|
|
8012104: 68fb ldr r3, [r7, #12]
|
|
8012106: 815a strh r2, [r3, #10]
|
|
p->tot_len = (u16_t)(p->tot_len + increment_magnitude);
|
|
8012108: 68fb ldr r3, [r7, #12]
|
|
801210a: 891a ldrh r2, [r3, #8]
|
|
801210c: 8a7b ldrh r3, [r7, #18]
|
|
801210e: 4413 add r3, r2
|
|
8012110: b29a uxth r2, r3
|
|
8012112: 68fb ldr r3, [r7, #12]
|
|
8012114: 811a strh r2, [r3, #8]
|
|
|
|
|
|
return 0;
|
|
8012116: 2300 movs r3, #0
|
|
}
|
|
8012118: 4618 mov r0, r3
|
|
801211a: 3718 adds r7, #24
|
|
801211c: 46bd mov sp, r7
|
|
801211e: bd80 pop {r7, pc}
|
|
8012120: 0801e648 .word 0x0801e648
|
|
8012124: 0801e7ac .word 0x0801e7ac
|
|
8012128: 0801e6a8 .word 0x0801e6a8
|
|
|
|
0801212c <pbuf_add_header>:
|
|
* @return non-zero on failure, zero on success.
|
|
*
|
|
*/
|
|
u8_t
|
|
pbuf_add_header(struct pbuf *p, size_t header_size_increment)
|
|
{
|
|
801212c: b580 push {r7, lr}
|
|
801212e: b082 sub sp, #8
|
|
8012130: af00 add r7, sp, #0
|
|
8012132: 6078 str r0, [r7, #4]
|
|
8012134: 6039 str r1, [r7, #0]
|
|
return pbuf_add_header_impl(p, header_size_increment, 0);
|
|
8012136: 2200 movs r2, #0
|
|
8012138: 6839 ldr r1, [r7, #0]
|
|
801213a: 6878 ldr r0, [r7, #4]
|
|
801213c: f7ff ff8e bl 801205c <pbuf_add_header_impl>
|
|
8012140: 4603 mov r3, r0
|
|
}
|
|
8012142: 4618 mov r0, r3
|
|
8012144: 3708 adds r7, #8
|
|
8012146: 46bd mov sp, r7
|
|
8012148: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0801214c <pbuf_remove_header>:
|
|
* @return non-zero on failure, zero on success.
|
|
*
|
|
*/
|
|
u8_t
|
|
pbuf_remove_header(struct pbuf *p, size_t header_size_decrement)
|
|
{
|
|
801214c: b580 push {r7, lr}
|
|
801214e: b084 sub sp, #16
|
|
8012150: af00 add r7, sp, #0
|
|
8012152: 6078 str r0, [r7, #4]
|
|
8012154: 6039 str r1, [r7, #0]
|
|
void *payload;
|
|
u16_t increment_magnitude;
|
|
|
|
LWIP_ASSERT("p != NULL", p != NULL);
|
|
8012156: 687b ldr r3, [r7, #4]
|
|
8012158: 2b00 cmp r3, #0
|
|
801215a: d106 bne.n 801216a <pbuf_remove_header+0x1e>
|
|
801215c: 4b20 ldr r3, [pc, #128] ; (80121e0 <pbuf_remove_header+0x94>)
|
|
801215e: f240 224b movw r2, #587 ; 0x24b
|
|
8012162: 4920 ldr r1, [pc, #128] ; (80121e4 <pbuf_remove_header+0x98>)
|
|
8012164: 4820 ldr r0, [pc, #128] ; (80121e8 <pbuf_remove_header+0x9c>)
|
|
8012166: f00a fda7 bl 801ccb8 <iprintf>
|
|
if ((p == NULL) || (header_size_decrement > 0xFFFF)) {
|
|
801216a: 687b ldr r3, [r7, #4]
|
|
801216c: 2b00 cmp r3, #0
|
|
801216e: d003 beq.n 8012178 <pbuf_remove_header+0x2c>
|
|
8012170: 683b ldr r3, [r7, #0]
|
|
8012172: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8012176: d301 bcc.n 801217c <pbuf_remove_header+0x30>
|
|
return 1;
|
|
8012178: 2301 movs r3, #1
|
|
801217a: e02c b.n 80121d6 <pbuf_remove_header+0x8a>
|
|
}
|
|
if (header_size_decrement == 0) {
|
|
801217c: 683b ldr r3, [r7, #0]
|
|
801217e: 2b00 cmp r3, #0
|
|
8012180: d101 bne.n 8012186 <pbuf_remove_header+0x3a>
|
|
return 0;
|
|
8012182: 2300 movs r3, #0
|
|
8012184: e027 b.n 80121d6 <pbuf_remove_header+0x8a>
|
|
}
|
|
|
|
increment_magnitude = (u16_t)header_size_decrement;
|
|
8012186: 683b ldr r3, [r7, #0]
|
|
8012188: 81fb strh r3, [r7, #14]
|
|
/* Check that we aren't going to move off the end of the pbuf */
|
|
LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;);
|
|
801218a: 687b ldr r3, [r7, #4]
|
|
801218c: 895b ldrh r3, [r3, #10]
|
|
801218e: 89fa ldrh r2, [r7, #14]
|
|
8012190: 429a cmp r2, r3
|
|
8012192: d908 bls.n 80121a6 <pbuf_remove_header+0x5a>
|
|
8012194: 4b12 ldr r3, [pc, #72] ; (80121e0 <pbuf_remove_header+0x94>)
|
|
8012196: f240 2255 movw r2, #597 ; 0x255
|
|
801219a: 4914 ldr r1, [pc, #80] ; (80121ec <pbuf_remove_header+0xa0>)
|
|
801219c: 4812 ldr r0, [pc, #72] ; (80121e8 <pbuf_remove_header+0x9c>)
|
|
801219e: f00a fd8b bl 801ccb8 <iprintf>
|
|
80121a2: 2301 movs r3, #1
|
|
80121a4: e017 b.n 80121d6 <pbuf_remove_header+0x8a>
|
|
|
|
/* remember current payload pointer */
|
|
payload = p->payload;
|
|
80121a6: 687b ldr r3, [r7, #4]
|
|
80121a8: 685b ldr r3, [r3, #4]
|
|
80121aa: 60bb str r3, [r7, #8]
|
|
LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */
|
|
|
|
/* increase payload pointer (guarded by length check above) */
|
|
p->payload = (u8_t *)p->payload + header_size_decrement;
|
|
80121ac: 687b ldr r3, [r7, #4]
|
|
80121ae: 685a ldr r2, [r3, #4]
|
|
80121b0: 683b ldr r3, [r7, #0]
|
|
80121b2: 441a add r2, r3
|
|
80121b4: 687b ldr r3, [r7, #4]
|
|
80121b6: 605a str r2, [r3, #4]
|
|
/* modify pbuf length fields */
|
|
p->len = (u16_t)(p->len - increment_magnitude);
|
|
80121b8: 687b ldr r3, [r7, #4]
|
|
80121ba: 895a ldrh r2, [r3, #10]
|
|
80121bc: 89fb ldrh r3, [r7, #14]
|
|
80121be: 1ad3 subs r3, r2, r3
|
|
80121c0: b29a uxth r2, r3
|
|
80121c2: 687b ldr r3, [r7, #4]
|
|
80121c4: 815a strh r2, [r3, #10]
|
|
p->tot_len = (u16_t)(p->tot_len - increment_magnitude);
|
|
80121c6: 687b ldr r3, [r7, #4]
|
|
80121c8: 891a ldrh r2, [r3, #8]
|
|
80121ca: 89fb ldrh r3, [r7, #14]
|
|
80121cc: 1ad3 subs r3, r2, r3
|
|
80121ce: b29a uxth r2, r3
|
|
80121d0: 687b ldr r3, [r7, #4]
|
|
80121d2: 811a strh r2, [r3, #8]
|
|
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n",
|
|
(void *)payload, (void *)p->payload, increment_magnitude));
|
|
|
|
return 0;
|
|
80121d4: 2300 movs r3, #0
|
|
}
|
|
80121d6: 4618 mov r0, r3
|
|
80121d8: 3710 adds r7, #16
|
|
80121da: 46bd mov sp, r7
|
|
80121dc: bd80 pop {r7, pc}
|
|
80121de: bf00 nop
|
|
80121e0: 0801e648 .word 0x0801e648
|
|
80121e4: 0801e7ac .word 0x0801e7ac
|
|
80121e8: 0801e6a8 .word 0x0801e6a8
|
|
80121ec: 0801e7b8 .word 0x0801e7b8
|
|
|
|
080121f0 <pbuf_header_impl>:
|
|
|
|
static u8_t
|
|
pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force)
|
|
{
|
|
80121f0: b580 push {r7, lr}
|
|
80121f2: b082 sub sp, #8
|
|
80121f4: af00 add r7, sp, #0
|
|
80121f6: 6078 str r0, [r7, #4]
|
|
80121f8: 460b mov r3, r1
|
|
80121fa: 807b strh r3, [r7, #2]
|
|
80121fc: 4613 mov r3, r2
|
|
80121fe: 707b strb r3, [r7, #1]
|
|
if (header_size_increment < 0) {
|
|
8012200: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
8012204: 2b00 cmp r3, #0
|
|
8012206: da08 bge.n 801221a <pbuf_header_impl+0x2a>
|
|
return pbuf_remove_header(p, (size_t) - header_size_increment);
|
|
8012208: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
801220c: 425b negs r3, r3
|
|
801220e: 4619 mov r1, r3
|
|
8012210: 6878 ldr r0, [r7, #4]
|
|
8012212: f7ff ff9b bl 801214c <pbuf_remove_header>
|
|
8012216: 4603 mov r3, r0
|
|
8012218: e007 b.n 801222a <pbuf_header_impl+0x3a>
|
|
} else {
|
|
return pbuf_add_header_impl(p, (size_t)header_size_increment, force);
|
|
801221a: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
801221e: 787a ldrb r2, [r7, #1]
|
|
8012220: 4619 mov r1, r3
|
|
8012222: 6878 ldr r0, [r7, #4]
|
|
8012224: f7ff ff1a bl 801205c <pbuf_add_header_impl>
|
|
8012228: 4603 mov r3, r0
|
|
}
|
|
}
|
|
801222a: 4618 mov r0, r3
|
|
801222c: 3708 adds r7, #8
|
|
801222e: 46bd mov sp, r7
|
|
8012230: bd80 pop {r7, pc}
|
|
|
|
08012232 <pbuf_header_force>:
|
|
* Same as pbuf_header but does not check if 'header_size > 0' is allowed.
|
|
* This is used internally only, to allow PBUF_REF for RX.
|
|
*/
|
|
u8_t
|
|
pbuf_header_force(struct pbuf *p, s16_t header_size_increment)
|
|
{
|
|
8012232: b580 push {r7, lr}
|
|
8012234: b082 sub sp, #8
|
|
8012236: af00 add r7, sp, #0
|
|
8012238: 6078 str r0, [r7, #4]
|
|
801223a: 460b mov r3, r1
|
|
801223c: 807b strh r3, [r7, #2]
|
|
return pbuf_header_impl(p, header_size_increment, 1);
|
|
801223e: f9b7 3002 ldrsh.w r3, [r7, #2]
|
|
8012242: 2201 movs r2, #1
|
|
8012244: 4619 mov r1, r3
|
|
8012246: 6878 ldr r0, [r7, #4]
|
|
8012248: f7ff ffd2 bl 80121f0 <pbuf_header_impl>
|
|
801224c: 4603 mov r3, r0
|
|
}
|
|
801224e: 4618 mov r0, r3
|
|
8012250: 3708 adds r7, #8
|
|
8012252: 46bd mov sp, r7
|
|
8012254: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08012258 <pbuf_free>:
|
|
* 1->1->1 becomes .......
|
|
*
|
|
*/
|
|
u8_t
|
|
pbuf_free(struct pbuf *p)
|
|
{
|
|
8012258: b580 push {r7, lr}
|
|
801225a: b088 sub sp, #32
|
|
801225c: af00 add r7, sp, #0
|
|
801225e: 6078 str r0, [r7, #4]
|
|
u8_t alloc_src;
|
|
struct pbuf *q;
|
|
u8_t count;
|
|
|
|
if (p == NULL) {
|
|
8012260: 687b ldr r3, [r7, #4]
|
|
8012262: 2b00 cmp r3, #0
|
|
8012264: d10b bne.n 801227e <pbuf_free+0x26>
|
|
LWIP_ASSERT("p != NULL", p != NULL);
|
|
8012266: 687b ldr r3, [r7, #4]
|
|
8012268: 2b00 cmp r3, #0
|
|
801226a: d106 bne.n 801227a <pbuf_free+0x22>
|
|
801226c: 4b3b ldr r3, [pc, #236] ; (801235c <pbuf_free+0x104>)
|
|
801226e: f44f 7237 mov.w r2, #732 ; 0x2dc
|
|
8012272: 493b ldr r1, [pc, #236] ; (8012360 <pbuf_free+0x108>)
|
|
8012274: 483b ldr r0, [pc, #236] ; (8012364 <pbuf_free+0x10c>)
|
|
8012276: f00a fd1f bl 801ccb8 <iprintf>
|
|
/* if assertions are disabled, proceed with debug output */
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
|
|
("pbuf_free(p == NULL) was called.\n"));
|
|
return 0;
|
|
801227a: 2300 movs r3, #0
|
|
801227c: e069 b.n 8012352 <pbuf_free+0xfa>
|
|
}
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p));
|
|
|
|
PERF_START;
|
|
|
|
count = 0;
|
|
801227e: 2300 movs r3, #0
|
|
8012280: 77fb strb r3, [r7, #31]
|
|
/* de-allocate all consecutive pbufs from the head of the chain that
|
|
* obtain a zero reference count after decrementing*/
|
|
while (p != NULL) {
|
|
8012282: e062 b.n 801234a <pbuf_free+0xf2>
|
|
LWIP_PBUF_REF_T ref;
|
|
SYS_ARCH_DECL_PROTECT(old_level);
|
|
/* Since decrementing ref cannot be guaranteed to be a single machine operation
|
|
* we must protect it. We put the new ref into a local variable to prevent
|
|
* further protection. */
|
|
SYS_ARCH_PROTECT(old_level);
|
|
8012284: f00a fc9a bl 801cbbc <sys_arch_protect>
|
|
8012288: 61b8 str r0, [r7, #24]
|
|
/* all pbufs in a chain are referenced at least once */
|
|
LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0);
|
|
801228a: 687b ldr r3, [r7, #4]
|
|
801228c: 7b9b ldrb r3, [r3, #14]
|
|
801228e: 2b00 cmp r3, #0
|
|
8012290: d106 bne.n 80122a0 <pbuf_free+0x48>
|
|
8012292: 4b32 ldr r3, [pc, #200] ; (801235c <pbuf_free+0x104>)
|
|
8012294: f240 22f1 movw r2, #753 ; 0x2f1
|
|
8012298: 4933 ldr r1, [pc, #204] ; (8012368 <pbuf_free+0x110>)
|
|
801229a: 4832 ldr r0, [pc, #200] ; (8012364 <pbuf_free+0x10c>)
|
|
801229c: f00a fd0c bl 801ccb8 <iprintf>
|
|
/* decrease reference count (number of pointers to pbuf) */
|
|
ref = --(p->ref);
|
|
80122a0: 687b ldr r3, [r7, #4]
|
|
80122a2: 7b9b ldrb r3, [r3, #14]
|
|
80122a4: 3b01 subs r3, #1
|
|
80122a6: b2da uxtb r2, r3
|
|
80122a8: 687b ldr r3, [r7, #4]
|
|
80122aa: 739a strb r2, [r3, #14]
|
|
80122ac: 687b ldr r3, [r7, #4]
|
|
80122ae: 7b9b ldrb r3, [r3, #14]
|
|
80122b0: 75fb strb r3, [r7, #23]
|
|
SYS_ARCH_UNPROTECT(old_level);
|
|
80122b2: 69b8 ldr r0, [r7, #24]
|
|
80122b4: f00a fc90 bl 801cbd8 <sys_arch_unprotect>
|
|
/* this pbuf is no longer referenced to? */
|
|
if (ref == 0) {
|
|
80122b8: 7dfb ldrb r3, [r7, #23]
|
|
80122ba: 2b00 cmp r3, #0
|
|
80122bc: d143 bne.n 8012346 <pbuf_free+0xee>
|
|
/* remember next pbuf in chain for next iteration */
|
|
q = p->next;
|
|
80122be: 687b ldr r3, [r7, #4]
|
|
80122c0: 681b ldr r3, [r3, #0]
|
|
80122c2: 613b str r3, [r7, #16]
|
|
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p));
|
|
alloc_src = pbuf_get_allocsrc(p);
|
|
80122c4: 687b ldr r3, [r7, #4]
|
|
80122c6: 7b1b ldrb r3, [r3, #12]
|
|
80122c8: f003 030f and.w r3, r3, #15
|
|
80122cc: 73fb strb r3, [r7, #15]
|
|
#if LWIP_SUPPORT_CUSTOM_PBUF
|
|
/* is this a custom pbuf? */
|
|
if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) {
|
|
80122ce: 687b ldr r3, [r7, #4]
|
|
80122d0: 7b5b ldrb r3, [r3, #13]
|
|
80122d2: f003 0302 and.w r3, r3, #2
|
|
80122d6: 2b00 cmp r3, #0
|
|
80122d8: d011 beq.n 80122fe <pbuf_free+0xa6>
|
|
struct pbuf_custom *pc = (struct pbuf_custom *)p;
|
|
80122da: 687b ldr r3, [r7, #4]
|
|
80122dc: 60bb str r3, [r7, #8]
|
|
LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL);
|
|
80122de: 68bb ldr r3, [r7, #8]
|
|
80122e0: 691b ldr r3, [r3, #16]
|
|
80122e2: 2b00 cmp r3, #0
|
|
80122e4: d106 bne.n 80122f4 <pbuf_free+0x9c>
|
|
80122e6: 4b1d ldr r3, [pc, #116] ; (801235c <pbuf_free+0x104>)
|
|
80122e8: f240 22ff movw r2, #767 ; 0x2ff
|
|
80122ec: 491f ldr r1, [pc, #124] ; (801236c <pbuf_free+0x114>)
|
|
80122ee: 481d ldr r0, [pc, #116] ; (8012364 <pbuf_free+0x10c>)
|
|
80122f0: f00a fce2 bl 801ccb8 <iprintf>
|
|
pc->custom_free_function(p);
|
|
80122f4: 68bb ldr r3, [r7, #8]
|
|
80122f6: 691b ldr r3, [r3, #16]
|
|
80122f8: 6878 ldr r0, [r7, #4]
|
|
80122fa: 4798 blx r3
|
|
80122fc: e01d b.n 801233a <pbuf_free+0xe2>
|
|
} else
|
|
#endif /* LWIP_SUPPORT_CUSTOM_PBUF */
|
|
{
|
|
/* is this a pbuf from the pool? */
|
|
if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) {
|
|
80122fe: 7bfb ldrb r3, [r7, #15]
|
|
8012300: 2b02 cmp r3, #2
|
|
8012302: d104 bne.n 801230e <pbuf_free+0xb6>
|
|
memp_free(MEMP_PBUF_POOL, p);
|
|
8012304: 6879 ldr r1, [r7, #4]
|
|
8012306: 200c movs r0, #12
|
|
8012308: f7ff f8fa bl 8011500 <memp_free>
|
|
801230c: e015 b.n 801233a <pbuf_free+0xe2>
|
|
/* is this a ROM or RAM referencing pbuf? */
|
|
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) {
|
|
801230e: 7bfb ldrb r3, [r7, #15]
|
|
8012310: 2b01 cmp r3, #1
|
|
8012312: d104 bne.n 801231e <pbuf_free+0xc6>
|
|
memp_free(MEMP_PBUF, p);
|
|
8012314: 6879 ldr r1, [r7, #4]
|
|
8012316: 200b movs r0, #11
|
|
8012318: f7ff f8f2 bl 8011500 <memp_free>
|
|
801231c: e00d b.n 801233a <pbuf_free+0xe2>
|
|
/* type == PBUF_RAM */
|
|
} else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) {
|
|
801231e: 7bfb ldrb r3, [r7, #15]
|
|
8012320: 2b00 cmp r3, #0
|
|
8012322: d103 bne.n 801232c <pbuf_free+0xd4>
|
|
mem_free(p);
|
|
8012324: 6878 ldr r0, [r7, #4]
|
|
8012326: f7fe fd7d bl 8010e24 <mem_free>
|
|
801232a: e006 b.n 801233a <pbuf_free+0xe2>
|
|
} else {
|
|
/* @todo: support freeing other types */
|
|
LWIP_ASSERT("invalid pbuf type", 0);
|
|
801232c: 4b0b ldr r3, [pc, #44] ; (801235c <pbuf_free+0x104>)
|
|
801232e: f240 320f movw r2, #783 ; 0x30f
|
|
8012332: 490f ldr r1, [pc, #60] ; (8012370 <pbuf_free+0x118>)
|
|
8012334: 480b ldr r0, [pc, #44] ; (8012364 <pbuf_free+0x10c>)
|
|
8012336: f00a fcbf bl 801ccb8 <iprintf>
|
|
}
|
|
}
|
|
count++;
|
|
801233a: 7ffb ldrb r3, [r7, #31]
|
|
801233c: 3301 adds r3, #1
|
|
801233e: 77fb strb r3, [r7, #31]
|
|
/* proceed to next pbuf */
|
|
p = q;
|
|
8012340: 693b ldr r3, [r7, #16]
|
|
8012342: 607b str r3, [r7, #4]
|
|
8012344: e001 b.n 801234a <pbuf_free+0xf2>
|
|
/* p->ref > 0, this pbuf is still referenced to */
|
|
/* (and so the remaining pbufs in chain as well) */
|
|
} else {
|
|
LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref));
|
|
/* stop walking through the chain */
|
|
p = NULL;
|
|
8012346: 2300 movs r3, #0
|
|
8012348: 607b str r3, [r7, #4]
|
|
while (p != NULL) {
|
|
801234a: 687b ldr r3, [r7, #4]
|
|
801234c: 2b00 cmp r3, #0
|
|
801234e: d199 bne.n 8012284 <pbuf_free+0x2c>
|
|
}
|
|
}
|
|
PERF_STOP("pbuf_free");
|
|
/* return number of de-allocated pbufs */
|
|
return count;
|
|
8012350: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
8012352: 4618 mov r0, r3
|
|
8012354: 3720 adds r7, #32
|
|
8012356: 46bd mov sp, r7
|
|
8012358: bd80 pop {r7, pc}
|
|
801235a: bf00 nop
|
|
801235c: 0801e648 .word 0x0801e648
|
|
8012360: 0801e7ac .word 0x0801e7ac
|
|
8012364: 0801e6a8 .word 0x0801e6a8
|
|
8012368: 0801e7d8 .word 0x0801e7d8
|
|
801236c: 0801e7f0 .word 0x0801e7f0
|
|
8012370: 0801e814 .word 0x0801e814
|
|
|
|
08012374 <pbuf_clen>:
|
|
* @param p first pbuf of chain
|
|
* @return the number of pbufs in a chain
|
|
*/
|
|
u16_t
|
|
pbuf_clen(const struct pbuf *p)
|
|
{
|
|
8012374: b480 push {r7}
|
|
8012376: b085 sub sp, #20
|
|
8012378: af00 add r7, sp, #0
|
|
801237a: 6078 str r0, [r7, #4]
|
|
u16_t len;
|
|
|
|
len = 0;
|
|
801237c: 2300 movs r3, #0
|
|
801237e: 81fb strh r3, [r7, #14]
|
|
while (p != NULL) {
|
|
8012380: e005 b.n 801238e <pbuf_clen+0x1a>
|
|
++len;
|
|
8012382: 89fb ldrh r3, [r7, #14]
|
|
8012384: 3301 adds r3, #1
|
|
8012386: 81fb strh r3, [r7, #14]
|
|
p = p->next;
|
|
8012388: 687b ldr r3, [r7, #4]
|
|
801238a: 681b ldr r3, [r3, #0]
|
|
801238c: 607b str r3, [r7, #4]
|
|
while (p != NULL) {
|
|
801238e: 687b ldr r3, [r7, #4]
|
|
8012390: 2b00 cmp r3, #0
|
|
8012392: d1f6 bne.n 8012382 <pbuf_clen+0xe>
|
|
}
|
|
return len;
|
|
8012394: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8012396: 4618 mov r0, r3
|
|
8012398: 3714 adds r7, #20
|
|
801239a: 46bd mov sp, r7
|
|
801239c: f85d 7b04 ldr.w r7, [sp], #4
|
|
80123a0: 4770 bx lr
|
|
...
|
|
|
|
080123a4 <pbuf_ref>:
|
|
* @param p pbuf to increase reference counter of
|
|
*
|
|
*/
|
|
void
|
|
pbuf_ref(struct pbuf *p)
|
|
{
|
|
80123a4: b580 push {r7, lr}
|
|
80123a6: b084 sub sp, #16
|
|
80123a8: af00 add r7, sp, #0
|
|
80123aa: 6078 str r0, [r7, #4]
|
|
/* pbuf given? */
|
|
if (p != NULL) {
|
|
80123ac: 687b ldr r3, [r7, #4]
|
|
80123ae: 2b00 cmp r3, #0
|
|
80123b0: d016 beq.n 80123e0 <pbuf_ref+0x3c>
|
|
SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1));
|
|
80123b2: f00a fc03 bl 801cbbc <sys_arch_protect>
|
|
80123b6: 60f8 str r0, [r7, #12]
|
|
80123b8: 687b ldr r3, [r7, #4]
|
|
80123ba: 7b9b ldrb r3, [r3, #14]
|
|
80123bc: 3301 adds r3, #1
|
|
80123be: b2da uxtb r2, r3
|
|
80123c0: 687b ldr r3, [r7, #4]
|
|
80123c2: 739a strb r2, [r3, #14]
|
|
80123c4: 68f8 ldr r0, [r7, #12]
|
|
80123c6: f00a fc07 bl 801cbd8 <sys_arch_unprotect>
|
|
LWIP_ASSERT("pbuf ref overflow", p->ref > 0);
|
|
80123ca: 687b ldr r3, [r7, #4]
|
|
80123cc: 7b9b ldrb r3, [r3, #14]
|
|
80123ce: 2b00 cmp r3, #0
|
|
80123d0: d106 bne.n 80123e0 <pbuf_ref+0x3c>
|
|
80123d2: 4b05 ldr r3, [pc, #20] ; (80123e8 <pbuf_ref+0x44>)
|
|
80123d4: f240 3242 movw r2, #834 ; 0x342
|
|
80123d8: 4904 ldr r1, [pc, #16] ; (80123ec <pbuf_ref+0x48>)
|
|
80123da: 4805 ldr r0, [pc, #20] ; (80123f0 <pbuf_ref+0x4c>)
|
|
80123dc: f00a fc6c bl 801ccb8 <iprintf>
|
|
}
|
|
}
|
|
80123e0: bf00 nop
|
|
80123e2: 3710 adds r7, #16
|
|
80123e4: 46bd mov sp, r7
|
|
80123e6: bd80 pop {r7, pc}
|
|
80123e8: 0801e648 .word 0x0801e648
|
|
80123ec: 0801e828 .word 0x0801e828
|
|
80123f0: 0801e6a8 .word 0x0801e6a8
|
|
|
|
080123f4 <pbuf_cat>:
|
|
*
|
|
* @see pbuf_chain()
|
|
*/
|
|
void
|
|
pbuf_cat(struct pbuf *h, struct pbuf *t)
|
|
{
|
|
80123f4: b580 push {r7, lr}
|
|
80123f6: b084 sub sp, #16
|
|
80123f8: af00 add r7, sp, #0
|
|
80123fa: 6078 str r0, [r7, #4]
|
|
80123fc: 6039 str r1, [r7, #0]
|
|
struct pbuf *p;
|
|
|
|
LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)",
|
|
80123fe: 687b ldr r3, [r7, #4]
|
|
8012400: 2b00 cmp r3, #0
|
|
8012402: d002 beq.n 801240a <pbuf_cat+0x16>
|
|
8012404: 683b ldr r3, [r7, #0]
|
|
8012406: 2b00 cmp r3, #0
|
|
8012408: d107 bne.n 801241a <pbuf_cat+0x26>
|
|
801240a: 4b20 ldr r3, [pc, #128] ; (801248c <pbuf_cat+0x98>)
|
|
801240c: f240 325a movw r2, #858 ; 0x35a
|
|
8012410: 491f ldr r1, [pc, #124] ; (8012490 <pbuf_cat+0x9c>)
|
|
8012412: 4820 ldr r0, [pc, #128] ; (8012494 <pbuf_cat+0xa0>)
|
|
8012414: f00a fc50 bl 801ccb8 <iprintf>
|
|
8012418: e034 b.n 8012484 <pbuf_cat+0x90>
|
|
((h != NULL) && (t != NULL)), return;);
|
|
|
|
/* proceed to last pbuf of chain */
|
|
for (p = h; p->next != NULL; p = p->next) {
|
|
801241a: 687b ldr r3, [r7, #4]
|
|
801241c: 60fb str r3, [r7, #12]
|
|
801241e: e00a b.n 8012436 <pbuf_cat+0x42>
|
|
/* add total length of second chain to all totals of first chain */
|
|
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
|
|
8012420: 68fb ldr r3, [r7, #12]
|
|
8012422: 891a ldrh r2, [r3, #8]
|
|
8012424: 683b ldr r3, [r7, #0]
|
|
8012426: 891b ldrh r3, [r3, #8]
|
|
8012428: 4413 add r3, r2
|
|
801242a: b29a uxth r2, r3
|
|
801242c: 68fb ldr r3, [r7, #12]
|
|
801242e: 811a strh r2, [r3, #8]
|
|
for (p = h; p->next != NULL; p = p->next) {
|
|
8012430: 68fb ldr r3, [r7, #12]
|
|
8012432: 681b ldr r3, [r3, #0]
|
|
8012434: 60fb str r3, [r7, #12]
|
|
8012436: 68fb ldr r3, [r7, #12]
|
|
8012438: 681b ldr r3, [r3, #0]
|
|
801243a: 2b00 cmp r3, #0
|
|
801243c: d1f0 bne.n 8012420 <pbuf_cat+0x2c>
|
|
}
|
|
/* { p is last pbuf of first h chain, p->next == NULL } */
|
|
LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len);
|
|
801243e: 68fb ldr r3, [r7, #12]
|
|
8012440: 891a ldrh r2, [r3, #8]
|
|
8012442: 68fb ldr r3, [r7, #12]
|
|
8012444: 895b ldrh r3, [r3, #10]
|
|
8012446: 429a cmp r2, r3
|
|
8012448: d006 beq.n 8012458 <pbuf_cat+0x64>
|
|
801244a: 4b10 ldr r3, [pc, #64] ; (801248c <pbuf_cat+0x98>)
|
|
801244c: f240 3262 movw r2, #866 ; 0x362
|
|
8012450: 4911 ldr r1, [pc, #68] ; (8012498 <pbuf_cat+0xa4>)
|
|
8012452: 4810 ldr r0, [pc, #64] ; (8012494 <pbuf_cat+0xa0>)
|
|
8012454: f00a fc30 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("p->next == NULL", p->next == NULL);
|
|
8012458: 68fb ldr r3, [r7, #12]
|
|
801245a: 681b ldr r3, [r3, #0]
|
|
801245c: 2b00 cmp r3, #0
|
|
801245e: d006 beq.n 801246e <pbuf_cat+0x7a>
|
|
8012460: 4b0a ldr r3, [pc, #40] ; (801248c <pbuf_cat+0x98>)
|
|
8012462: f240 3263 movw r2, #867 ; 0x363
|
|
8012466: 490d ldr r1, [pc, #52] ; (801249c <pbuf_cat+0xa8>)
|
|
8012468: 480a ldr r0, [pc, #40] ; (8012494 <pbuf_cat+0xa0>)
|
|
801246a: f00a fc25 bl 801ccb8 <iprintf>
|
|
/* add total length of second chain to last pbuf total of first chain */
|
|
p->tot_len = (u16_t)(p->tot_len + t->tot_len);
|
|
801246e: 68fb ldr r3, [r7, #12]
|
|
8012470: 891a ldrh r2, [r3, #8]
|
|
8012472: 683b ldr r3, [r7, #0]
|
|
8012474: 891b ldrh r3, [r3, #8]
|
|
8012476: 4413 add r3, r2
|
|
8012478: b29a uxth r2, r3
|
|
801247a: 68fb ldr r3, [r7, #12]
|
|
801247c: 811a strh r2, [r3, #8]
|
|
/* chain last pbuf of head (p) with first of tail (t) */
|
|
p->next = t;
|
|
801247e: 68fb ldr r3, [r7, #12]
|
|
8012480: 683a ldr r2, [r7, #0]
|
|
8012482: 601a str r2, [r3, #0]
|
|
/* p->next now references t, but the caller will drop its reference to t,
|
|
* so netto there is no change to the reference count of t.
|
|
*/
|
|
}
|
|
8012484: 3710 adds r7, #16
|
|
8012486: 46bd mov sp, r7
|
|
8012488: bd80 pop {r7, pc}
|
|
801248a: bf00 nop
|
|
801248c: 0801e648 .word 0x0801e648
|
|
8012490: 0801e83c .word 0x0801e83c
|
|
8012494: 0801e6a8 .word 0x0801e6a8
|
|
8012498: 0801e874 .word 0x0801e874
|
|
801249c: 0801e8a4 .word 0x0801e8a4
|
|
|
|
080124a0 <pbuf_chain>:
|
|
* The ->ref field of the first pbuf of the tail chain is adjusted.
|
|
*
|
|
*/
|
|
void
|
|
pbuf_chain(struct pbuf *h, struct pbuf *t)
|
|
{
|
|
80124a0: b580 push {r7, lr}
|
|
80124a2: b082 sub sp, #8
|
|
80124a4: af00 add r7, sp, #0
|
|
80124a6: 6078 str r0, [r7, #4]
|
|
80124a8: 6039 str r1, [r7, #0]
|
|
pbuf_cat(h, t);
|
|
80124aa: 6839 ldr r1, [r7, #0]
|
|
80124ac: 6878 ldr r0, [r7, #4]
|
|
80124ae: f7ff ffa1 bl 80123f4 <pbuf_cat>
|
|
/* t is now referenced by h */
|
|
pbuf_ref(t);
|
|
80124b2: 6838 ldr r0, [r7, #0]
|
|
80124b4: f7ff ff76 bl 80123a4 <pbuf_ref>
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t));
|
|
}
|
|
80124b8: bf00 nop
|
|
80124ba: 3708 adds r7, #8
|
|
80124bc: 46bd mov sp, r7
|
|
80124be: bd80 pop {r7, pc}
|
|
|
|
080124c0 <pbuf_copy>:
|
|
* ERR_ARG if one of the pbufs is NULL or p_to is not big
|
|
* enough to hold p_from
|
|
*/
|
|
err_t
|
|
pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from)
|
|
{
|
|
80124c0: b580 push {r7, lr}
|
|
80124c2: b086 sub sp, #24
|
|
80124c4: af00 add r7, sp, #0
|
|
80124c6: 6078 str r0, [r7, #4]
|
|
80124c8: 6039 str r1, [r7, #0]
|
|
size_t offset_to = 0, offset_from = 0, len;
|
|
80124ca: 2300 movs r3, #0
|
|
80124cc: 617b str r3, [r7, #20]
|
|
80124ce: 2300 movs r3, #0
|
|
80124d0: 613b str r3, [r7, #16]
|
|
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n",
|
|
(const void *)p_to, (const void *)p_from));
|
|
|
|
/* is the target big enough to hold the source? */
|
|
LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) &&
|
|
80124d2: 687b ldr r3, [r7, #4]
|
|
80124d4: 2b00 cmp r3, #0
|
|
80124d6: d008 beq.n 80124ea <pbuf_copy+0x2a>
|
|
80124d8: 683b ldr r3, [r7, #0]
|
|
80124da: 2b00 cmp r3, #0
|
|
80124dc: d005 beq.n 80124ea <pbuf_copy+0x2a>
|
|
80124de: 687b ldr r3, [r7, #4]
|
|
80124e0: 891a ldrh r2, [r3, #8]
|
|
80124e2: 683b ldr r3, [r7, #0]
|
|
80124e4: 891b ldrh r3, [r3, #8]
|
|
80124e6: 429a cmp r2, r3
|
|
80124e8: d209 bcs.n 80124fe <pbuf_copy+0x3e>
|
|
80124ea: 4b57 ldr r3, [pc, #348] ; (8012648 <pbuf_copy+0x188>)
|
|
80124ec: f240 32ca movw r2, #970 ; 0x3ca
|
|
80124f0: 4956 ldr r1, [pc, #344] ; (801264c <pbuf_copy+0x18c>)
|
|
80124f2: 4857 ldr r0, [pc, #348] ; (8012650 <pbuf_copy+0x190>)
|
|
80124f4: f00a fbe0 bl 801ccb8 <iprintf>
|
|
80124f8: f06f 030f mvn.w r3, #15
|
|
80124fc: e09f b.n 801263e <pbuf_copy+0x17e>
|
|
(p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;);
|
|
|
|
/* iterate through pbuf chain */
|
|
do {
|
|
/* copy one part of the original chain */
|
|
if ((p_to->len - offset_to) >= (p_from->len - offset_from)) {
|
|
80124fe: 687b ldr r3, [r7, #4]
|
|
8012500: 895b ldrh r3, [r3, #10]
|
|
8012502: 461a mov r2, r3
|
|
8012504: 697b ldr r3, [r7, #20]
|
|
8012506: 1ad2 subs r2, r2, r3
|
|
8012508: 683b ldr r3, [r7, #0]
|
|
801250a: 895b ldrh r3, [r3, #10]
|
|
801250c: 4619 mov r1, r3
|
|
801250e: 693b ldr r3, [r7, #16]
|
|
8012510: 1acb subs r3, r1, r3
|
|
8012512: 429a cmp r2, r3
|
|
8012514: d306 bcc.n 8012524 <pbuf_copy+0x64>
|
|
/* complete current p_from fits into current p_to */
|
|
len = p_from->len - offset_from;
|
|
8012516: 683b ldr r3, [r7, #0]
|
|
8012518: 895b ldrh r3, [r3, #10]
|
|
801251a: 461a mov r2, r3
|
|
801251c: 693b ldr r3, [r7, #16]
|
|
801251e: 1ad3 subs r3, r2, r3
|
|
8012520: 60fb str r3, [r7, #12]
|
|
8012522: e005 b.n 8012530 <pbuf_copy+0x70>
|
|
} else {
|
|
/* current p_from does not fit into current p_to */
|
|
len = p_to->len - offset_to;
|
|
8012524: 687b ldr r3, [r7, #4]
|
|
8012526: 895b ldrh r3, [r3, #10]
|
|
8012528: 461a mov r2, r3
|
|
801252a: 697b ldr r3, [r7, #20]
|
|
801252c: 1ad3 subs r3, r2, r3
|
|
801252e: 60fb str r3, [r7, #12]
|
|
}
|
|
MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len);
|
|
8012530: 687b ldr r3, [r7, #4]
|
|
8012532: 685a ldr r2, [r3, #4]
|
|
8012534: 697b ldr r3, [r7, #20]
|
|
8012536: 18d0 adds r0, r2, r3
|
|
8012538: 683b ldr r3, [r7, #0]
|
|
801253a: 685a ldr r2, [r3, #4]
|
|
801253c: 693b ldr r3, [r7, #16]
|
|
801253e: 4413 add r3, r2
|
|
8012540: 68fa ldr r2, [r7, #12]
|
|
8012542: 4619 mov r1, r3
|
|
8012544: f00a fb8b bl 801cc5e <memcpy>
|
|
offset_to += len;
|
|
8012548: 697a ldr r2, [r7, #20]
|
|
801254a: 68fb ldr r3, [r7, #12]
|
|
801254c: 4413 add r3, r2
|
|
801254e: 617b str r3, [r7, #20]
|
|
offset_from += len;
|
|
8012550: 693a ldr r2, [r7, #16]
|
|
8012552: 68fb ldr r3, [r7, #12]
|
|
8012554: 4413 add r3, r2
|
|
8012556: 613b str r3, [r7, #16]
|
|
LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len);
|
|
8012558: 687b ldr r3, [r7, #4]
|
|
801255a: 895b ldrh r3, [r3, #10]
|
|
801255c: 461a mov r2, r3
|
|
801255e: 697b ldr r3, [r7, #20]
|
|
8012560: 4293 cmp r3, r2
|
|
8012562: d906 bls.n 8012572 <pbuf_copy+0xb2>
|
|
8012564: 4b38 ldr r3, [pc, #224] ; (8012648 <pbuf_copy+0x188>)
|
|
8012566: f240 32d9 movw r2, #985 ; 0x3d9
|
|
801256a: 493a ldr r1, [pc, #232] ; (8012654 <pbuf_copy+0x194>)
|
|
801256c: 4838 ldr r0, [pc, #224] ; (8012650 <pbuf_copy+0x190>)
|
|
801256e: f00a fba3 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len);
|
|
8012572: 683b ldr r3, [r7, #0]
|
|
8012574: 895b ldrh r3, [r3, #10]
|
|
8012576: 461a mov r2, r3
|
|
8012578: 693b ldr r3, [r7, #16]
|
|
801257a: 4293 cmp r3, r2
|
|
801257c: d906 bls.n 801258c <pbuf_copy+0xcc>
|
|
801257e: 4b32 ldr r3, [pc, #200] ; (8012648 <pbuf_copy+0x188>)
|
|
8012580: f240 32da movw r2, #986 ; 0x3da
|
|
8012584: 4934 ldr r1, [pc, #208] ; (8012658 <pbuf_copy+0x198>)
|
|
8012586: 4832 ldr r0, [pc, #200] ; (8012650 <pbuf_copy+0x190>)
|
|
8012588: f00a fb96 bl 801ccb8 <iprintf>
|
|
if (offset_from >= p_from->len) {
|
|
801258c: 683b ldr r3, [r7, #0]
|
|
801258e: 895b ldrh r3, [r3, #10]
|
|
8012590: 461a mov r2, r3
|
|
8012592: 693b ldr r3, [r7, #16]
|
|
8012594: 4293 cmp r3, r2
|
|
8012596: d304 bcc.n 80125a2 <pbuf_copy+0xe2>
|
|
/* on to next p_from (if any) */
|
|
offset_from = 0;
|
|
8012598: 2300 movs r3, #0
|
|
801259a: 613b str r3, [r7, #16]
|
|
p_from = p_from->next;
|
|
801259c: 683b ldr r3, [r7, #0]
|
|
801259e: 681b ldr r3, [r3, #0]
|
|
80125a0: 603b str r3, [r7, #0]
|
|
}
|
|
if (offset_to == p_to->len) {
|
|
80125a2: 687b ldr r3, [r7, #4]
|
|
80125a4: 895b ldrh r3, [r3, #10]
|
|
80125a6: 461a mov r2, r3
|
|
80125a8: 697b ldr r3, [r7, #20]
|
|
80125aa: 4293 cmp r3, r2
|
|
80125ac: d114 bne.n 80125d8 <pbuf_copy+0x118>
|
|
/* on to next p_to (if any) */
|
|
offset_to = 0;
|
|
80125ae: 2300 movs r3, #0
|
|
80125b0: 617b str r3, [r7, #20]
|
|
p_to = p_to->next;
|
|
80125b2: 687b ldr r3, [r7, #4]
|
|
80125b4: 681b ldr r3, [r3, #0]
|
|
80125b6: 607b str r3, [r7, #4]
|
|
LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;);
|
|
80125b8: 687b ldr r3, [r7, #4]
|
|
80125ba: 2b00 cmp r3, #0
|
|
80125bc: d10c bne.n 80125d8 <pbuf_copy+0x118>
|
|
80125be: 683b ldr r3, [r7, #0]
|
|
80125c0: 2b00 cmp r3, #0
|
|
80125c2: d009 beq.n 80125d8 <pbuf_copy+0x118>
|
|
80125c4: 4b20 ldr r3, [pc, #128] ; (8012648 <pbuf_copy+0x188>)
|
|
80125c6: f44f 7279 mov.w r2, #996 ; 0x3e4
|
|
80125ca: 4924 ldr r1, [pc, #144] ; (801265c <pbuf_copy+0x19c>)
|
|
80125cc: 4820 ldr r0, [pc, #128] ; (8012650 <pbuf_copy+0x190>)
|
|
80125ce: f00a fb73 bl 801ccb8 <iprintf>
|
|
80125d2: f06f 030f mvn.w r3, #15
|
|
80125d6: e032 b.n 801263e <pbuf_copy+0x17e>
|
|
}
|
|
|
|
if ((p_from != NULL) && (p_from->len == p_from->tot_len)) {
|
|
80125d8: 683b ldr r3, [r7, #0]
|
|
80125da: 2b00 cmp r3, #0
|
|
80125dc: d013 beq.n 8012606 <pbuf_copy+0x146>
|
|
80125de: 683b ldr r3, [r7, #0]
|
|
80125e0: 895a ldrh r2, [r3, #10]
|
|
80125e2: 683b ldr r3, [r7, #0]
|
|
80125e4: 891b ldrh r3, [r3, #8]
|
|
80125e6: 429a cmp r2, r3
|
|
80125e8: d10d bne.n 8012606 <pbuf_copy+0x146>
|
|
/* don't copy more than one packet! */
|
|
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
|
|
80125ea: 683b ldr r3, [r7, #0]
|
|
80125ec: 681b ldr r3, [r3, #0]
|
|
80125ee: 2b00 cmp r3, #0
|
|
80125f0: d009 beq.n 8012606 <pbuf_copy+0x146>
|
|
80125f2: 4b15 ldr r3, [pc, #84] ; (8012648 <pbuf_copy+0x188>)
|
|
80125f4: f240 32ea movw r2, #1002 ; 0x3ea
|
|
80125f8: 4919 ldr r1, [pc, #100] ; (8012660 <pbuf_copy+0x1a0>)
|
|
80125fa: 4815 ldr r0, [pc, #84] ; (8012650 <pbuf_copy+0x190>)
|
|
80125fc: f00a fb5c bl 801ccb8 <iprintf>
|
|
8012600: f06f 0305 mvn.w r3, #5
|
|
8012604: e01b b.n 801263e <pbuf_copy+0x17e>
|
|
(p_from->next == NULL), return ERR_VAL;);
|
|
}
|
|
if ((p_to != NULL) && (p_to->len == p_to->tot_len)) {
|
|
8012606: 687b ldr r3, [r7, #4]
|
|
8012608: 2b00 cmp r3, #0
|
|
801260a: d013 beq.n 8012634 <pbuf_copy+0x174>
|
|
801260c: 687b ldr r3, [r7, #4]
|
|
801260e: 895a ldrh r2, [r3, #10]
|
|
8012610: 687b ldr r3, [r7, #4]
|
|
8012612: 891b ldrh r3, [r3, #8]
|
|
8012614: 429a cmp r2, r3
|
|
8012616: d10d bne.n 8012634 <pbuf_copy+0x174>
|
|
/* don't copy more than one packet! */
|
|
LWIP_ERROR("pbuf_copy() does not allow packet queues!",
|
|
8012618: 687b ldr r3, [r7, #4]
|
|
801261a: 681b ldr r3, [r3, #0]
|
|
801261c: 2b00 cmp r3, #0
|
|
801261e: d009 beq.n 8012634 <pbuf_copy+0x174>
|
|
8012620: 4b09 ldr r3, [pc, #36] ; (8012648 <pbuf_copy+0x188>)
|
|
8012622: f240 32ef movw r2, #1007 ; 0x3ef
|
|
8012626: 490e ldr r1, [pc, #56] ; (8012660 <pbuf_copy+0x1a0>)
|
|
8012628: 4809 ldr r0, [pc, #36] ; (8012650 <pbuf_copy+0x190>)
|
|
801262a: f00a fb45 bl 801ccb8 <iprintf>
|
|
801262e: f06f 0305 mvn.w r3, #5
|
|
8012632: e004 b.n 801263e <pbuf_copy+0x17e>
|
|
(p_to->next == NULL), return ERR_VAL;);
|
|
}
|
|
} while (p_from);
|
|
8012634: 683b ldr r3, [r7, #0]
|
|
8012636: 2b00 cmp r3, #0
|
|
8012638: f47f af61 bne.w 80124fe <pbuf_copy+0x3e>
|
|
LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n"));
|
|
return ERR_OK;
|
|
801263c: 2300 movs r3, #0
|
|
}
|
|
801263e: 4618 mov r0, r3
|
|
8012640: 3718 adds r7, #24
|
|
8012642: 46bd mov sp, r7
|
|
8012644: bd80 pop {r7, pc}
|
|
8012646: bf00 nop
|
|
8012648: 0801e648 .word 0x0801e648
|
|
801264c: 0801e8f0 .word 0x0801e8f0
|
|
8012650: 0801e6a8 .word 0x0801e6a8
|
|
8012654: 0801e920 .word 0x0801e920
|
|
8012658: 0801e938 .word 0x0801e938
|
|
801265c: 0801e954 .word 0x0801e954
|
|
8012660: 0801e964 .word 0x0801e964
|
|
|
|
08012664 <pbuf_copy_partial>:
|
|
* @param offset offset into the packet buffer from where to begin copying len bytes
|
|
* @return the number of bytes copied, or 0 on failure
|
|
*/
|
|
u16_t
|
|
pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset)
|
|
{
|
|
8012664: b580 push {r7, lr}
|
|
8012666: b088 sub sp, #32
|
|
8012668: af00 add r7, sp, #0
|
|
801266a: 60f8 str r0, [r7, #12]
|
|
801266c: 60b9 str r1, [r7, #8]
|
|
801266e: 4611 mov r1, r2
|
|
8012670: 461a mov r2, r3
|
|
8012672: 460b mov r3, r1
|
|
8012674: 80fb strh r3, [r7, #6]
|
|
8012676: 4613 mov r3, r2
|
|
8012678: 80bb strh r3, [r7, #4]
|
|
const struct pbuf *p;
|
|
u16_t left = 0;
|
|
801267a: 2300 movs r3, #0
|
|
801267c: 837b strh r3, [r7, #26]
|
|
u16_t buf_copy_len;
|
|
u16_t copied_total = 0;
|
|
801267e: 2300 movs r3, #0
|
|
8012680: 82fb strh r3, [r7, #22]
|
|
|
|
LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;);
|
|
8012682: 68fb ldr r3, [r7, #12]
|
|
8012684: 2b00 cmp r3, #0
|
|
8012686: d108 bne.n 801269a <pbuf_copy_partial+0x36>
|
|
8012688: 4b2b ldr r3, [pc, #172] ; (8012738 <pbuf_copy_partial+0xd4>)
|
|
801268a: f240 420a movw r2, #1034 ; 0x40a
|
|
801268e: 492b ldr r1, [pc, #172] ; (801273c <pbuf_copy_partial+0xd8>)
|
|
8012690: 482b ldr r0, [pc, #172] ; (8012740 <pbuf_copy_partial+0xdc>)
|
|
8012692: f00a fb11 bl 801ccb8 <iprintf>
|
|
8012696: 2300 movs r3, #0
|
|
8012698: e04a b.n 8012730 <pbuf_copy_partial+0xcc>
|
|
LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;);
|
|
801269a: 68bb ldr r3, [r7, #8]
|
|
801269c: 2b00 cmp r3, #0
|
|
801269e: d108 bne.n 80126b2 <pbuf_copy_partial+0x4e>
|
|
80126a0: 4b25 ldr r3, [pc, #148] ; (8012738 <pbuf_copy_partial+0xd4>)
|
|
80126a2: f240 420b movw r2, #1035 ; 0x40b
|
|
80126a6: 4927 ldr r1, [pc, #156] ; (8012744 <pbuf_copy_partial+0xe0>)
|
|
80126a8: 4825 ldr r0, [pc, #148] ; (8012740 <pbuf_copy_partial+0xdc>)
|
|
80126aa: f00a fb05 bl 801ccb8 <iprintf>
|
|
80126ae: 2300 movs r3, #0
|
|
80126b0: e03e b.n 8012730 <pbuf_copy_partial+0xcc>
|
|
|
|
/* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */
|
|
for (p = buf; len != 0 && p != NULL; p = p->next) {
|
|
80126b2: 68fb ldr r3, [r7, #12]
|
|
80126b4: 61fb str r3, [r7, #28]
|
|
80126b6: e034 b.n 8012722 <pbuf_copy_partial+0xbe>
|
|
if ((offset != 0) && (offset >= p->len)) {
|
|
80126b8: 88bb ldrh r3, [r7, #4]
|
|
80126ba: 2b00 cmp r3, #0
|
|
80126bc: d00a beq.n 80126d4 <pbuf_copy_partial+0x70>
|
|
80126be: 69fb ldr r3, [r7, #28]
|
|
80126c0: 895b ldrh r3, [r3, #10]
|
|
80126c2: 88ba ldrh r2, [r7, #4]
|
|
80126c4: 429a cmp r2, r3
|
|
80126c6: d305 bcc.n 80126d4 <pbuf_copy_partial+0x70>
|
|
/* don't copy from this buffer -> on to the next */
|
|
offset = (u16_t)(offset - p->len);
|
|
80126c8: 69fb ldr r3, [r7, #28]
|
|
80126ca: 895b ldrh r3, [r3, #10]
|
|
80126cc: 88ba ldrh r2, [r7, #4]
|
|
80126ce: 1ad3 subs r3, r2, r3
|
|
80126d0: 80bb strh r3, [r7, #4]
|
|
80126d2: e023 b.n 801271c <pbuf_copy_partial+0xb8>
|
|
} else {
|
|
/* copy from this buffer. maybe only partially. */
|
|
buf_copy_len = (u16_t)(p->len - offset);
|
|
80126d4: 69fb ldr r3, [r7, #28]
|
|
80126d6: 895a ldrh r2, [r3, #10]
|
|
80126d8: 88bb ldrh r3, [r7, #4]
|
|
80126da: 1ad3 subs r3, r2, r3
|
|
80126dc: 833b strh r3, [r7, #24]
|
|
if (buf_copy_len > len) {
|
|
80126de: 8b3a ldrh r2, [r7, #24]
|
|
80126e0: 88fb ldrh r3, [r7, #6]
|
|
80126e2: 429a cmp r2, r3
|
|
80126e4: d901 bls.n 80126ea <pbuf_copy_partial+0x86>
|
|
buf_copy_len = len;
|
|
80126e6: 88fb ldrh r3, [r7, #6]
|
|
80126e8: 833b strh r3, [r7, #24]
|
|
}
|
|
/* copy the necessary parts of the buffer */
|
|
MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len);
|
|
80126ea: 8b7b ldrh r3, [r7, #26]
|
|
80126ec: 68ba ldr r2, [r7, #8]
|
|
80126ee: 18d0 adds r0, r2, r3
|
|
80126f0: 69fb ldr r3, [r7, #28]
|
|
80126f2: 685a ldr r2, [r3, #4]
|
|
80126f4: 88bb ldrh r3, [r7, #4]
|
|
80126f6: 4413 add r3, r2
|
|
80126f8: 8b3a ldrh r2, [r7, #24]
|
|
80126fa: 4619 mov r1, r3
|
|
80126fc: f00a faaf bl 801cc5e <memcpy>
|
|
copied_total = (u16_t)(copied_total + buf_copy_len);
|
|
8012700: 8afa ldrh r2, [r7, #22]
|
|
8012702: 8b3b ldrh r3, [r7, #24]
|
|
8012704: 4413 add r3, r2
|
|
8012706: 82fb strh r3, [r7, #22]
|
|
left = (u16_t)(left + buf_copy_len);
|
|
8012708: 8b7a ldrh r2, [r7, #26]
|
|
801270a: 8b3b ldrh r3, [r7, #24]
|
|
801270c: 4413 add r3, r2
|
|
801270e: 837b strh r3, [r7, #26]
|
|
len = (u16_t)(len - buf_copy_len);
|
|
8012710: 88fa ldrh r2, [r7, #6]
|
|
8012712: 8b3b ldrh r3, [r7, #24]
|
|
8012714: 1ad3 subs r3, r2, r3
|
|
8012716: 80fb strh r3, [r7, #6]
|
|
offset = 0;
|
|
8012718: 2300 movs r3, #0
|
|
801271a: 80bb strh r3, [r7, #4]
|
|
for (p = buf; len != 0 && p != NULL; p = p->next) {
|
|
801271c: 69fb ldr r3, [r7, #28]
|
|
801271e: 681b ldr r3, [r3, #0]
|
|
8012720: 61fb str r3, [r7, #28]
|
|
8012722: 88fb ldrh r3, [r7, #6]
|
|
8012724: 2b00 cmp r3, #0
|
|
8012726: d002 beq.n 801272e <pbuf_copy_partial+0xca>
|
|
8012728: 69fb ldr r3, [r7, #28]
|
|
801272a: 2b00 cmp r3, #0
|
|
801272c: d1c4 bne.n 80126b8 <pbuf_copy_partial+0x54>
|
|
}
|
|
}
|
|
return copied_total;
|
|
801272e: 8afb ldrh r3, [r7, #22]
|
|
}
|
|
8012730: 4618 mov r0, r3
|
|
8012732: 3720 adds r7, #32
|
|
8012734: 46bd mov sp, r7
|
|
8012736: bd80 pop {r7, pc}
|
|
8012738: 0801e648 .word 0x0801e648
|
|
801273c: 0801e990 .word 0x0801e990
|
|
8012740: 0801e6a8 .word 0x0801e6a8
|
|
8012744: 0801e9b0 .word 0x0801e9b0
|
|
|
|
08012748 <pbuf_clone>:
|
|
*
|
|
* @return a new pbuf or NULL if allocation fails
|
|
*/
|
|
struct pbuf *
|
|
pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p)
|
|
{
|
|
8012748: b580 push {r7, lr}
|
|
801274a: b084 sub sp, #16
|
|
801274c: af00 add r7, sp, #0
|
|
801274e: 4603 mov r3, r0
|
|
8012750: 603a str r2, [r7, #0]
|
|
8012752: 71fb strb r3, [r7, #7]
|
|
8012754: 460b mov r3, r1
|
|
8012756: 80bb strh r3, [r7, #4]
|
|
struct pbuf *q;
|
|
err_t err;
|
|
q = pbuf_alloc(layer, p->tot_len, type);
|
|
8012758: 683b ldr r3, [r7, #0]
|
|
801275a: 8919 ldrh r1, [r3, #8]
|
|
801275c: 88ba ldrh r2, [r7, #4]
|
|
801275e: 79fb ldrb r3, [r7, #7]
|
|
8012760: 4618 mov r0, r3
|
|
8012762: f7ff fa99 bl 8011c98 <pbuf_alloc>
|
|
8012766: 60f8 str r0, [r7, #12]
|
|
if (q == NULL) {
|
|
8012768: 68fb ldr r3, [r7, #12]
|
|
801276a: 2b00 cmp r3, #0
|
|
801276c: d101 bne.n 8012772 <pbuf_clone+0x2a>
|
|
return NULL;
|
|
801276e: 2300 movs r3, #0
|
|
8012770: e011 b.n 8012796 <pbuf_clone+0x4e>
|
|
}
|
|
err = pbuf_copy(q, p);
|
|
8012772: 6839 ldr r1, [r7, #0]
|
|
8012774: 68f8 ldr r0, [r7, #12]
|
|
8012776: f7ff fea3 bl 80124c0 <pbuf_copy>
|
|
801277a: 4603 mov r3, r0
|
|
801277c: 72fb strb r3, [r7, #11]
|
|
LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */
|
|
LWIP_ASSERT("pbuf_copy failed", err == ERR_OK);
|
|
801277e: f997 300b ldrsb.w r3, [r7, #11]
|
|
8012782: 2b00 cmp r3, #0
|
|
8012784: d006 beq.n 8012794 <pbuf_clone+0x4c>
|
|
8012786: 4b06 ldr r3, [pc, #24] ; (80127a0 <pbuf_clone+0x58>)
|
|
8012788: f240 5224 movw r2, #1316 ; 0x524
|
|
801278c: 4905 ldr r1, [pc, #20] ; (80127a4 <pbuf_clone+0x5c>)
|
|
801278e: 4806 ldr r0, [pc, #24] ; (80127a8 <pbuf_clone+0x60>)
|
|
8012790: f00a fa92 bl 801ccb8 <iprintf>
|
|
return q;
|
|
8012794: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8012796: 4618 mov r0, r3
|
|
8012798: 3710 adds r7, #16
|
|
801279a: 46bd mov sp, r7
|
|
801279c: bd80 pop {r7, pc}
|
|
801279e: bf00 nop
|
|
80127a0: 0801e648 .word 0x0801e648
|
|
80127a4: 0801eabc .word 0x0801eabc
|
|
80127a8: 0801e6a8 .word 0x0801e6a8
|
|
|
|
080127ac <tcp_init>:
|
|
/**
|
|
* Initialize this module.
|
|
*/
|
|
void
|
|
tcp_init(void)
|
|
{
|
|
80127ac: b580 push {r7, lr}
|
|
80127ae: af00 add r7, sp, #0
|
|
#ifdef LWIP_RAND
|
|
tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
|
|
80127b0: f00a fa9a bl 801cce8 <rand>
|
|
80127b4: 4603 mov r3, r0
|
|
80127b6: b29b uxth r3, r3
|
|
80127b8: f3c3 030d ubfx r3, r3, #0, #14
|
|
80127bc: b29b uxth r3, r3
|
|
80127be: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
|
|
80127c2: b29a uxth r2, r3
|
|
80127c4: 4b01 ldr r3, [pc, #4] ; (80127cc <tcp_init+0x20>)
|
|
80127c6: 801a strh r2, [r3, #0]
|
|
#endif /* LWIP_RAND */
|
|
}
|
|
80127c8: bf00 nop
|
|
80127ca: bd80 pop {r7, pc}
|
|
80127cc: 20000074 .word 0x20000074
|
|
|
|
080127d0 <tcp_free>:
|
|
|
|
/** Free a tcp pcb */
|
|
void
|
|
tcp_free(struct tcp_pcb *pcb)
|
|
{
|
|
80127d0: b580 push {r7, lr}
|
|
80127d2: b082 sub sp, #8
|
|
80127d4: af00 add r7, sp, #0
|
|
80127d6: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN);
|
|
80127d8: 687b ldr r3, [r7, #4]
|
|
80127da: 7d1b ldrb r3, [r3, #20]
|
|
80127dc: 2b01 cmp r3, #1
|
|
80127de: d105 bne.n 80127ec <tcp_free+0x1c>
|
|
80127e0: 4b06 ldr r3, [pc, #24] ; (80127fc <tcp_free+0x2c>)
|
|
80127e2: 22d4 movs r2, #212 ; 0xd4
|
|
80127e4: 4906 ldr r1, [pc, #24] ; (8012800 <tcp_free+0x30>)
|
|
80127e6: 4807 ldr r0, [pc, #28] ; (8012804 <tcp_free+0x34>)
|
|
80127e8: f00a fa66 bl 801ccb8 <iprintf>
|
|
#if LWIP_TCP_PCB_NUM_EXT_ARGS
|
|
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
|
|
#endif
|
|
memp_free(MEMP_TCP_PCB, pcb);
|
|
80127ec: 6879 ldr r1, [r7, #4]
|
|
80127ee: 2001 movs r0, #1
|
|
80127f0: f7fe fe86 bl 8011500 <memp_free>
|
|
}
|
|
80127f4: bf00 nop
|
|
80127f6: 3708 adds r7, #8
|
|
80127f8: 46bd mov sp, r7
|
|
80127fa: bd80 pop {r7, pc}
|
|
80127fc: 0801eb48 .word 0x0801eb48
|
|
8012800: 0801eb78 .word 0x0801eb78
|
|
8012804: 0801eb8c .word 0x0801eb8c
|
|
|
|
08012808 <tcp_free_listen>:
|
|
|
|
/** Free a tcp listen pcb */
|
|
static void
|
|
tcp_free_listen(struct tcp_pcb *pcb)
|
|
{
|
|
8012808: b580 push {r7, lr}
|
|
801280a: b082 sub sp, #8
|
|
801280c: af00 add r7, sp, #0
|
|
801280e: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN);
|
|
8012810: 687b ldr r3, [r7, #4]
|
|
8012812: 7d1b ldrb r3, [r3, #20]
|
|
8012814: 2b01 cmp r3, #1
|
|
8012816: d105 bne.n 8012824 <tcp_free_listen+0x1c>
|
|
8012818: 4b06 ldr r3, [pc, #24] ; (8012834 <tcp_free_listen+0x2c>)
|
|
801281a: 22df movs r2, #223 ; 0xdf
|
|
801281c: 4906 ldr r1, [pc, #24] ; (8012838 <tcp_free_listen+0x30>)
|
|
801281e: 4807 ldr r0, [pc, #28] ; (801283c <tcp_free_listen+0x34>)
|
|
8012820: f00a fa4a bl 801ccb8 <iprintf>
|
|
#if LWIP_TCP_PCB_NUM_EXT_ARGS
|
|
tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args);
|
|
#endif
|
|
memp_free(MEMP_TCP_PCB_LISTEN, pcb);
|
|
8012824: 6879 ldr r1, [r7, #4]
|
|
8012826: 2002 movs r0, #2
|
|
8012828: f7fe fe6a bl 8011500 <memp_free>
|
|
}
|
|
801282c: bf00 nop
|
|
801282e: 3708 adds r7, #8
|
|
8012830: 46bd mov sp, r7
|
|
8012832: bd80 pop {r7, pc}
|
|
8012834: 0801eb48 .word 0x0801eb48
|
|
8012838: 0801ebb4 .word 0x0801ebb4
|
|
801283c: 0801eb8c .word 0x0801eb8c
|
|
|
|
08012840 <tcp_tmr>:
|
|
/**
|
|
* Called periodically to dispatch TCP timers.
|
|
*/
|
|
void
|
|
tcp_tmr(void)
|
|
{
|
|
8012840: b580 push {r7, lr}
|
|
8012842: af00 add r7, sp, #0
|
|
/* Call tcp_fasttmr() every 250 ms */
|
|
tcp_fasttmr();
|
|
8012844: f000 fe98 bl 8013578 <tcp_fasttmr>
|
|
|
|
if (++tcp_timer & 1) {
|
|
8012848: 4b07 ldr r3, [pc, #28] ; (8012868 <tcp_tmr+0x28>)
|
|
801284a: 781b ldrb r3, [r3, #0]
|
|
801284c: 3301 adds r3, #1
|
|
801284e: b2da uxtb r2, r3
|
|
8012850: 4b05 ldr r3, [pc, #20] ; (8012868 <tcp_tmr+0x28>)
|
|
8012852: 701a strb r2, [r3, #0]
|
|
8012854: 4b04 ldr r3, [pc, #16] ; (8012868 <tcp_tmr+0x28>)
|
|
8012856: 781b ldrb r3, [r3, #0]
|
|
8012858: f003 0301 and.w r3, r3, #1
|
|
801285c: 2b00 cmp r3, #0
|
|
801285e: d001 beq.n 8012864 <tcp_tmr+0x24>
|
|
/* Call tcp_slowtmr() every 500 ms, i.e., every other timer
|
|
tcp_tmr() is called. */
|
|
tcp_slowtmr();
|
|
8012860: f000 fb4c bl 8012efc <tcp_slowtmr>
|
|
}
|
|
}
|
|
8012864: bf00 nop
|
|
8012866: bd80 pop {r7, pc}
|
|
8012868: 20008729 .word 0x20008729
|
|
|
|
0801286c <tcp_remove_listener>:
|
|
/** Called when a listen pcb is closed. Iterates one pcb list and removes the
|
|
* closed listener pcb from pcb->listener if matching.
|
|
*/
|
|
static void
|
|
tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb)
|
|
{
|
|
801286c: b580 push {r7, lr}
|
|
801286e: b084 sub sp, #16
|
|
8012870: af00 add r7, sp, #0
|
|
8012872: 6078 str r0, [r7, #4]
|
|
8012874: 6039 str r1, [r7, #0]
|
|
struct tcp_pcb *pcb;
|
|
|
|
LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL);
|
|
8012876: 683b ldr r3, [r7, #0]
|
|
8012878: 2b00 cmp r3, #0
|
|
801287a: d105 bne.n 8012888 <tcp_remove_listener+0x1c>
|
|
801287c: 4b0d ldr r3, [pc, #52] ; (80128b4 <tcp_remove_listener+0x48>)
|
|
801287e: 22ff movs r2, #255 ; 0xff
|
|
8012880: 490d ldr r1, [pc, #52] ; (80128b8 <tcp_remove_listener+0x4c>)
|
|
8012882: 480e ldr r0, [pc, #56] ; (80128bc <tcp_remove_listener+0x50>)
|
|
8012884: f00a fa18 bl 801ccb8 <iprintf>
|
|
|
|
for (pcb = list; pcb != NULL; pcb = pcb->next) {
|
|
8012888: 687b ldr r3, [r7, #4]
|
|
801288a: 60fb str r3, [r7, #12]
|
|
801288c: e00a b.n 80128a4 <tcp_remove_listener+0x38>
|
|
if (pcb->listener == lpcb) {
|
|
801288e: 68fb ldr r3, [r7, #12]
|
|
8012890: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
8012892: 683a ldr r2, [r7, #0]
|
|
8012894: 429a cmp r2, r3
|
|
8012896: d102 bne.n 801289e <tcp_remove_listener+0x32>
|
|
pcb->listener = NULL;
|
|
8012898: 68fb ldr r3, [r7, #12]
|
|
801289a: 2200 movs r2, #0
|
|
801289c: 67da str r2, [r3, #124] ; 0x7c
|
|
for (pcb = list; pcb != NULL; pcb = pcb->next) {
|
|
801289e: 68fb ldr r3, [r7, #12]
|
|
80128a0: 68db ldr r3, [r3, #12]
|
|
80128a2: 60fb str r3, [r7, #12]
|
|
80128a4: 68fb ldr r3, [r7, #12]
|
|
80128a6: 2b00 cmp r3, #0
|
|
80128a8: d1f1 bne.n 801288e <tcp_remove_listener+0x22>
|
|
}
|
|
}
|
|
}
|
|
80128aa: bf00 nop
|
|
80128ac: 3710 adds r7, #16
|
|
80128ae: 46bd mov sp, r7
|
|
80128b0: bd80 pop {r7, pc}
|
|
80128b2: bf00 nop
|
|
80128b4: 0801eb48 .word 0x0801eb48
|
|
80128b8: 0801ebd0 .word 0x0801ebd0
|
|
80128bc: 0801eb8c .word 0x0801eb8c
|
|
|
|
080128c0 <tcp_listen_closed>:
|
|
/** Called when a listen pcb is closed. Iterates all pcb lists and removes the
|
|
* closed listener pcb from pcb->listener if matching.
|
|
*/
|
|
static void
|
|
tcp_listen_closed(struct tcp_pcb *pcb)
|
|
{
|
|
80128c0: b580 push {r7, lr}
|
|
80128c2: b084 sub sp, #16
|
|
80128c4: af00 add r7, sp, #0
|
|
80128c6: 6078 str r0, [r7, #4]
|
|
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
|
|
size_t i;
|
|
LWIP_ASSERT("pcb != NULL", pcb != NULL);
|
|
80128c8: 687b ldr r3, [r7, #4]
|
|
80128ca: 2b00 cmp r3, #0
|
|
80128cc: d106 bne.n 80128dc <tcp_listen_closed+0x1c>
|
|
80128ce: 4b14 ldr r3, [pc, #80] ; (8012920 <tcp_listen_closed+0x60>)
|
|
80128d0: f240 1211 movw r2, #273 ; 0x111
|
|
80128d4: 4913 ldr r1, [pc, #76] ; (8012924 <tcp_listen_closed+0x64>)
|
|
80128d6: 4814 ldr r0, [pc, #80] ; (8012928 <tcp_listen_closed+0x68>)
|
|
80128d8: f00a f9ee bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN);
|
|
80128dc: 687b ldr r3, [r7, #4]
|
|
80128de: 7d1b ldrb r3, [r3, #20]
|
|
80128e0: 2b01 cmp r3, #1
|
|
80128e2: d006 beq.n 80128f2 <tcp_listen_closed+0x32>
|
|
80128e4: 4b0e ldr r3, [pc, #56] ; (8012920 <tcp_listen_closed+0x60>)
|
|
80128e6: f44f 7289 mov.w r2, #274 ; 0x112
|
|
80128ea: 4910 ldr r1, [pc, #64] ; (801292c <tcp_listen_closed+0x6c>)
|
|
80128ec: 480e ldr r0, [pc, #56] ; (8012928 <tcp_listen_closed+0x68>)
|
|
80128ee: f00a f9e3 bl 801ccb8 <iprintf>
|
|
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
|
|
80128f2: 2301 movs r3, #1
|
|
80128f4: 60fb str r3, [r7, #12]
|
|
80128f6: e00b b.n 8012910 <tcp_listen_closed+0x50>
|
|
tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb);
|
|
80128f8: 4a0d ldr r2, [pc, #52] ; (8012930 <tcp_listen_closed+0x70>)
|
|
80128fa: 68fb ldr r3, [r7, #12]
|
|
80128fc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8012900: 681b ldr r3, [r3, #0]
|
|
8012902: 6879 ldr r1, [r7, #4]
|
|
8012904: 4618 mov r0, r3
|
|
8012906: f7ff ffb1 bl 801286c <tcp_remove_listener>
|
|
for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) {
|
|
801290a: 68fb ldr r3, [r7, #12]
|
|
801290c: 3301 adds r3, #1
|
|
801290e: 60fb str r3, [r7, #12]
|
|
8012910: 68fb ldr r3, [r7, #12]
|
|
8012912: 2b03 cmp r3, #3
|
|
8012914: d9f0 bls.n 80128f8 <tcp_listen_closed+0x38>
|
|
}
|
|
#endif
|
|
LWIP_UNUSED_ARG(pcb);
|
|
}
|
|
8012916: bf00 nop
|
|
8012918: 3710 adds r7, #16
|
|
801291a: 46bd mov sp, r7
|
|
801291c: bd80 pop {r7, pc}
|
|
801291e: bf00 nop
|
|
8012920: 0801eb48 .word 0x0801eb48
|
|
8012924: 0801ebf8 .word 0x0801ebf8
|
|
8012928: 0801eb8c .word 0x0801eb8c
|
|
801292c: 0801ec04 .word 0x0801ec04
|
|
8012930: 08022e30 .word 0x08022e30
|
|
|
|
08012934 <tcp_close_shutdown>:
|
|
* @return ERR_OK if connection has been closed
|
|
* another err_t if closing failed and pcb is not freed
|
|
*/
|
|
static err_t
|
|
tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data)
|
|
{
|
|
8012934: b5b0 push {r4, r5, r7, lr}
|
|
8012936: b088 sub sp, #32
|
|
8012938: af04 add r7, sp, #16
|
|
801293a: 6078 str r0, [r7, #4]
|
|
801293c: 460b mov r3, r1
|
|
801293e: 70fb strb r3, [r7, #3]
|
|
LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL);
|
|
8012940: 687b ldr r3, [r7, #4]
|
|
8012942: 2b00 cmp r3, #0
|
|
8012944: d106 bne.n 8012954 <tcp_close_shutdown+0x20>
|
|
8012946: 4b61 ldr r3, [pc, #388] ; (8012acc <tcp_close_shutdown+0x198>)
|
|
8012948: f44f 72af mov.w r2, #350 ; 0x15e
|
|
801294c: 4960 ldr r1, [pc, #384] ; (8012ad0 <tcp_close_shutdown+0x19c>)
|
|
801294e: 4861 ldr r0, [pc, #388] ; (8012ad4 <tcp_close_shutdown+0x1a0>)
|
|
8012950: f00a f9b2 bl 801ccb8 <iprintf>
|
|
|
|
if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) {
|
|
8012954: 78fb ldrb r3, [r7, #3]
|
|
8012956: 2b00 cmp r3, #0
|
|
8012958: d066 beq.n 8012a28 <tcp_close_shutdown+0xf4>
|
|
801295a: 687b ldr r3, [r7, #4]
|
|
801295c: 7d1b ldrb r3, [r3, #20]
|
|
801295e: 2b04 cmp r3, #4
|
|
8012960: d003 beq.n 801296a <tcp_close_shutdown+0x36>
|
|
8012962: 687b ldr r3, [r7, #4]
|
|
8012964: 7d1b ldrb r3, [r3, #20]
|
|
8012966: 2b07 cmp r3, #7
|
|
8012968: d15e bne.n 8012a28 <tcp_close_shutdown+0xf4>
|
|
if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) {
|
|
801296a: 687b ldr r3, [r7, #4]
|
|
801296c: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
801296e: 2b00 cmp r3, #0
|
|
8012970: d104 bne.n 801297c <tcp_close_shutdown+0x48>
|
|
8012972: 687b ldr r3, [r7, #4]
|
|
8012974: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8012976: f5b3 6f06 cmp.w r3, #2144 ; 0x860
|
|
801297a: d055 beq.n 8012a28 <tcp_close_shutdown+0xf4>
|
|
/* Not all data received by application, send RST to tell the remote
|
|
side about this. */
|
|
LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED);
|
|
801297c: 687b ldr r3, [r7, #4]
|
|
801297e: 8b5b ldrh r3, [r3, #26]
|
|
8012980: f003 0310 and.w r3, r3, #16
|
|
8012984: 2b00 cmp r3, #0
|
|
8012986: d106 bne.n 8012996 <tcp_close_shutdown+0x62>
|
|
8012988: 4b50 ldr r3, [pc, #320] ; (8012acc <tcp_close_shutdown+0x198>)
|
|
801298a: f44f 72b2 mov.w r2, #356 ; 0x164
|
|
801298e: 4952 ldr r1, [pc, #328] ; (8012ad8 <tcp_close_shutdown+0x1a4>)
|
|
8012990: 4850 ldr r0, [pc, #320] ; (8012ad4 <tcp_close_shutdown+0x1a0>)
|
|
8012992: f00a f991 bl 801ccb8 <iprintf>
|
|
|
|
/* don't call tcp_abort here: we must not deallocate the pcb since
|
|
that might not be expected when calling tcp_close */
|
|
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
|
|
8012996: 687b ldr r3, [r7, #4]
|
|
8012998: 6d18 ldr r0, [r3, #80] ; 0x50
|
|
801299a: 687b ldr r3, [r7, #4]
|
|
801299c: 6a5c ldr r4, [r3, #36] ; 0x24
|
|
801299e: 687d ldr r5, [r7, #4]
|
|
80129a0: 687b ldr r3, [r7, #4]
|
|
80129a2: 3304 adds r3, #4
|
|
80129a4: 687a ldr r2, [r7, #4]
|
|
80129a6: 8ad2 ldrh r2, [r2, #22]
|
|
80129a8: 6879 ldr r1, [r7, #4]
|
|
80129aa: 8b09 ldrh r1, [r1, #24]
|
|
80129ac: 9102 str r1, [sp, #8]
|
|
80129ae: 9201 str r2, [sp, #4]
|
|
80129b0: 9300 str r3, [sp, #0]
|
|
80129b2: 462b mov r3, r5
|
|
80129b4: 4622 mov r2, r4
|
|
80129b6: 4601 mov r1, r0
|
|
80129b8: 6878 ldr r0, [r7, #4]
|
|
80129ba: f004 fe91 bl 80176e0 <tcp_rst>
|
|
pcb->local_port, pcb->remote_port);
|
|
|
|
tcp_pcb_purge(pcb);
|
|
80129be: 6878 ldr r0, [r7, #4]
|
|
80129c0: f001 f8ba bl 8013b38 <tcp_pcb_purge>
|
|
TCP_RMV_ACTIVE(pcb);
|
|
80129c4: 4b45 ldr r3, [pc, #276] ; (8012adc <tcp_close_shutdown+0x1a8>)
|
|
80129c6: 681b ldr r3, [r3, #0]
|
|
80129c8: 687a ldr r2, [r7, #4]
|
|
80129ca: 429a cmp r2, r3
|
|
80129cc: d105 bne.n 80129da <tcp_close_shutdown+0xa6>
|
|
80129ce: 4b43 ldr r3, [pc, #268] ; (8012adc <tcp_close_shutdown+0x1a8>)
|
|
80129d0: 681b ldr r3, [r3, #0]
|
|
80129d2: 68db ldr r3, [r3, #12]
|
|
80129d4: 4a41 ldr r2, [pc, #260] ; (8012adc <tcp_close_shutdown+0x1a8>)
|
|
80129d6: 6013 str r3, [r2, #0]
|
|
80129d8: e013 b.n 8012a02 <tcp_close_shutdown+0xce>
|
|
80129da: 4b40 ldr r3, [pc, #256] ; (8012adc <tcp_close_shutdown+0x1a8>)
|
|
80129dc: 681b ldr r3, [r3, #0]
|
|
80129de: 60fb str r3, [r7, #12]
|
|
80129e0: e00c b.n 80129fc <tcp_close_shutdown+0xc8>
|
|
80129e2: 68fb ldr r3, [r7, #12]
|
|
80129e4: 68db ldr r3, [r3, #12]
|
|
80129e6: 687a ldr r2, [r7, #4]
|
|
80129e8: 429a cmp r2, r3
|
|
80129ea: d104 bne.n 80129f6 <tcp_close_shutdown+0xc2>
|
|
80129ec: 687b ldr r3, [r7, #4]
|
|
80129ee: 68da ldr r2, [r3, #12]
|
|
80129f0: 68fb ldr r3, [r7, #12]
|
|
80129f2: 60da str r2, [r3, #12]
|
|
80129f4: e005 b.n 8012a02 <tcp_close_shutdown+0xce>
|
|
80129f6: 68fb ldr r3, [r7, #12]
|
|
80129f8: 68db ldr r3, [r3, #12]
|
|
80129fa: 60fb str r3, [r7, #12]
|
|
80129fc: 68fb ldr r3, [r7, #12]
|
|
80129fe: 2b00 cmp r3, #0
|
|
8012a00: d1ef bne.n 80129e2 <tcp_close_shutdown+0xae>
|
|
8012a02: 687b ldr r3, [r7, #4]
|
|
8012a04: 2200 movs r2, #0
|
|
8012a06: 60da str r2, [r3, #12]
|
|
8012a08: 4b35 ldr r3, [pc, #212] ; (8012ae0 <tcp_close_shutdown+0x1ac>)
|
|
8012a0a: 2201 movs r2, #1
|
|
8012a0c: 701a strb r2, [r3, #0]
|
|
/* Deallocate the pcb since we already sent a RST for it */
|
|
if (tcp_input_pcb == pcb) {
|
|
8012a0e: 4b35 ldr r3, [pc, #212] ; (8012ae4 <tcp_close_shutdown+0x1b0>)
|
|
8012a10: 681b ldr r3, [r3, #0]
|
|
8012a12: 687a ldr r2, [r7, #4]
|
|
8012a14: 429a cmp r2, r3
|
|
8012a16: d102 bne.n 8012a1e <tcp_close_shutdown+0xea>
|
|
/* prevent using a deallocated pcb: free it from tcp_input later */
|
|
tcp_trigger_input_pcb_close();
|
|
8012a18: f003 fd4c bl 80164b4 <tcp_trigger_input_pcb_close>
|
|
8012a1c: e002 b.n 8012a24 <tcp_close_shutdown+0xf0>
|
|
} else {
|
|
tcp_free(pcb);
|
|
8012a1e: 6878 ldr r0, [r7, #4]
|
|
8012a20: f7ff fed6 bl 80127d0 <tcp_free>
|
|
}
|
|
return ERR_OK;
|
|
8012a24: 2300 movs r3, #0
|
|
8012a26: e04d b.n 8012ac4 <tcp_close_shutdown+0x190>
|
|
}
|
|
}
|
|
|
|
/* - states which free the pcb are handled here,
|
|
- states which send FIN and change state are handled in tcp_close_shutdown_fin() */
|
|
switch (pcb->state) {
|
|
8012a28: 687b ldr r3, [r7, #4]
|
|
8012a2a: 7d1b ldrb r3, [r3, #20]
|
|
8012a2c: 2b01 cmp r3, #1
|
|
8012a2e: d02d beq.n 8012a8c <tcp_close_shutdown+0x158>
|
|
8012a30: 2b02 cmp r3, #2
|
|
8012a32: d036 beq.n 8012aa2 <tcp_close_shutdown+0x16e>
|
|
8012a34: 2b00 cmp r3, #0
|
|
8012a36: d13f bne.n 8012ab8 <tcp_close_shutdown+0x184>
|
|
* and the user needs some way to free it should the need arise.
|
|
* Calling tcp_close() with a pcb that has already been closed, (i.e. twice)
|
|
* or for a pcb that has been used and then entered the CLOSED state
|
|
* is erroneous, but this should never happen as the pcb has in those cases
|
|
* been freed, and so any remaining handles are bogus. */
|
|
if (pcb->local_port != 0) {
|
|
8012a38: 687b ldr r3, [r7, #4]
|
|
8012a3a: 8adb ldrh r3, [r3, #22]
|
|
8012a3c: 2b00 cmp r3, #0
|
|
8012a3e: d021 beq.n 8012a84 <tcp_close_shutdown+0x150>
|
|
TCP_RMV(&tcp_bound_pcbs, pcb);
|
|
8012a40: 4b29 ldr r3, [pc, #164] ; (8012ae8 <tcp_close_shutdown+0x1b4>)
|
|
8012a42: 681b ldr r3, [r3, #0]
|
|
8012a44: 687a ldr r2, [r7, #4]
|
|
8012a46: 429a cmp r2, r3
|
|
8012a48: d105 bne.n 8012a56 <tcp_close_shutdown+0x122>
|
|
8012a4a: 4b27 ldr r3, [pc, #156] ; (8012ae8 <tcp_close_shutdown+0x1b4>)
|
|
8012a4c: 681b ldr r3, [r3, #0]
|
|
8012a4e: 68db ldr r3, [r3, #12]
|
|
8012a50: 4a25 ldr r2, [pc, #148] ; (8012ae8 <tcp_close_shutdown+0x1b4>)
|
|
8012a52: 6013 str r3, [r2, #0]
|
|
8012a54: e013 b.n 8012a7e <tcp_close_shutdown+0x14a>
|
|
8012a56: 4b24 ldr r3, [pc, #144] ; (8012ae8 <tcp_close_shutdown+0x1b4>)
|
|
8012a58: 681b ldr r3, [r3, #0]
|
|
8012a5a: 60bb str r3, [r7, #8]
|
|
8012a5c: e00c b.n 8012a78 <tcp_close_shutdown+0x144>
|
|
8012a5e: 68bb ldr r3, [r7, #8]
|
|
8012a60: 68db ldr r3, [r3, #12]
|
|
8012a62: 687a ldr r2, [r7, #4]
|
|
8012a64: 429a cmp r2, r3
|
|
8012a66: d104 bne.n 8012a72 <tcp_close_shutdown+0x13e>
|
|
8012a68: 687b ldr r3, [r7, #4]
|
|
8012a6a: 68da ldr r2, [r3, #12]
|
|
8012a6c: 68bb ldr r3, [r7, #8]
|
|
8012a6e: 60da str r2, [r3, #12]
|
|
8012a70: e005 b.n 8012a7e <tcp_close_shutdown+0x14a>
|
|
8012a72: 68bb ldr r3, [r7, #8]
|
|
8012a74: 68db ldr r3, [r3, #12]
|
|
8012a76: 60bb str r3, [r7, #8]
|
|
8012a78: 68bb ldr r3, [r7, #8]
|
|
8012a7a: 2b00 cmp r3, #0
|
|
8012a7c: d1ef bne.n 8012a5e <tcp_close_shutdown+0x12a>
|
|
8012a7e: 687b ldr r3, [r7, #4]
|
|
8012a80: 2200 movs r2, #0
|
|
8012a82: 60da str r2, [r3, #12]
|
|
}
|
|
tcp_free(pcb);
|
|
8012a84: 6878 ldr r0, [r7, #4]
|
|
8012a86: f7ff fea3 bl 80127d0 <tcp_free>
|
|
break;
|
|
8012a8a: e01a b.n 8012ac2 <tcp_close_shutdown+0x18e>
|
|
case LISTEN:
|
|
tcp_listen_closed(pcb);
|
|
8012a8c: 6878 ldr r0, [r7, #4]
|
|
8012a8e: f7ff ff17 bl 80128c0 <tcp_listen_closed>
|
|
tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb);
|
|
8012a92: 6879 ldr r1, [r7, #4]
|
|
8012a94: 4815 ldr r0, [pc, #84] ; (8012aec <tcp_close_shutdown+0x1b8>)
|
|
8012a96: f001 f89f bl 8013bd8 <tcp_pcb_remove>
|
|
tcp_free_listen(pcb);
|
|
8012a9a: 6878 ldr r0, [r7, #4]
|
|
8012a9c: f7ff feb4 bl 8012808 <tcp_free_listen>
|
|
break;
|
|
8012aa0: e00f b.n 8012ac2 <tcp_close_shutdown+0x18e>
|
|
case SYN_SENT:
|
|
TCP_PCB_REMOVE_ACTIVE(pcb);
|
|
8012aa2: 6879 ldr r1, [r7, #4]
|
|
8012aa4: 480d ldr r0, [pc, #52] ; (8012adc <tcp_close_shutdown+0x1a8>)
|
|
8012aa6: f001 f897 bl 8013bd8 <tcp_pcb_remove>
|
|
8012aaa: 4b0d ldr r3, [pc, #52] ; (8012ae0 <tcp_close_shutdown+0x1ac>)
|
|
8012aac: 2201 movs r2, #1
|
|
8012aae: 701a strb r2, [r3, #0]
|
|
tcp_free(pcb);
|
|
8012ab0: 6878 ldr r0, [r7, #4]
|
|
8012ab2: f7ff fe8d bl 80127d0 <tcp_free>
|
|
MIB2_STATS_INC(mib2.tcpattemptfails);
|
|
break;
|
|
8012ab6: e004 b.n 8012ac2 <tcp_close_shutdown+0x18e>
|
|
default:
|
|
return tcp_close_shutdown_fin(pcb);
|
|
8012ab8: 6878 ldr r0, [r7, #4]
|
|
8012aba: f000 f819 bl 8012af0 <tcp_close_shutdown_fin>
|
|
8012abe: 4603 mov r3, r0
|
|
8012ac0: e000 b.n 8012ac4 <tcp_close_shutdown+0x190>
|
|
}
|
|
return ERR_OK;
|
|
8012ac2: 2300 movs r3, #0
|
|
}
|
|
8012ac4: 4618 mov r0, r3
|
|
8012ac6: 3710 adds r7, #16
|
|
8012ac8: 46bd mov sp, r7
|
|
8012aca: bdb0 pop {r4, r5, r7, pc}
|
|
8012acc: 0801eb48 .word 0x0801eb48
|
|
8012ad0: 0801ec1c .word 0x0801ec1c
|
|
8012ad4: 0801eb8c .word 0x0801eb8c
|
|
8012ad8: 0801ec3c .word 0x0801ec3c
|
|
8012adc: 2000f7fc .word 0x2000f7fc
|
|
8012ae0: 2000f7f8 .word 0x2000f7f8
|
|
8012ae4: 2000f810 .word 0x2000f810
|
|
8012ae8: 2000f808 .word 0x2000f808
|
|
8012aec: 2000f804 .word 0x2000f804
|
|
|
|
08012af0 <tcp_close_shutdown_fin>:
|
|
|
|
static err_t
|
|
tcp_close_shutdown_fin(struct tcp_pcb *pcb)
|
|
{
|
|
8012af0: b580 push {r7, lr}
|
|
8012af2: b084 sub sp, #16
|
|
8012af4: af00 add r7, sp, #0
|
|
8012af6: 6078 str r0, [r7, #4]
|
|
err_t err;
|
|
LWIP_ASSERT("pcb != NULL", pcb != NULL);
|
|
8012af8: 687b ldr r3, [r7, #4]
|
|
8012afa: 2b00 cmp r3, #0
|
|
8012afc: d106 bne.n 8012b0c <tcp_close_shutdown_fin+0x1c>
|
|
8012afe: 4b2c ldr r3, [pc, #176] ; (8012bb0 <tcp_close_shutdown_fin+0xc0>)
|
|
8012b00: f44f 72ce mov.w r2, #412 ; 0x19c
|
|
8012b04: 492b ldr r1, [pc, #172] ; (8012bb4 <tcp_close_shutdown_fin+0xc4>)
|
|
8012b06: 482c ldr r0, [pc, #176] ; (8012bb8 <tcp_close_shutdown_fin+0xc8>)
|
|
8012b08: f00a f8d6 bl 801ccb8 <iprintf>
|
|
|
|
switch (pcb->state) {
|
|
8012b0c: 687b ldr r3, [r7, #4]
|
|
8012b0e: 7d1b ldrb r3, [r3, #20]
|
|
8012b10: 2b04 cmp r3, #4
|
|
8012b12: d010 beq.n 8012b36 <tcp_close_shutdown_fin+0x46>
|
|
8012b14: 2b07 cmp r3, #7
|
|
8012b16: d01b beq.n 8012b50 <tcp_close_shutdown_fin+0x60>
|
|
8012b18: 2b03 cmp r3, #3
|
|
8012b1a: d126 bne.n 8012b6a <tcp_close_shutdown_fin+0x7a>
|
|
case SYN_RCVD:
|
|
err = tcp_send_fin(pcb);
|
|
8012b1c: 6878 ldr r0, [r7, #4]
|
|
8012b1e: f003 fedb bl 80168d8 <tcp_send_fin>
|
|
8012b22: 4603 mov r3, r0
|
|
8012b24: 73fb strb r3, [r7, #15]
|
|
if (err == ERR_OK) {
|
|
8012b26: f997 300f ldrsb.w r3, [r7, #15]
|
|
8012b2a: 2b00 cmp r3, #0
|
|
8012b2c: d11f bne.n 8012b6e <tcp_close_shutdown_fin+0x7e>
|
|
tcp_backlog_accepted(pcb);
|
|
MIB2_STATS_INC(mib2.tcpattemptfails);
|
|
pcb->state = FIN_WAIT_1;
|
|
8012b2e: 687b ldr r3, [r7, #4]
|
|
8012b30: 2205 movs r2, #5
|
|
8012b32: 751a strb r2, [r3, #20]
|
|
}
|
|
break;
|
|
8012b34: e01b b.n 8012b6e <tcp_close_shutdown_fin+0x7e>
|
|
case ESTABLISHED:
|
|
err = tcp_send_fin(pcb);
|
|
8012b36: 6878 ldr r0, [r7, #4]
|
|
8012b38: f003 fece bl 80168d8 <tcp_send_fin>
|
|
8012b3c: 4603 mov r3, r0
|
|
8012b3e: 73fb strb r3, [r7, #15]
|
|
if (err == ERR_OK) {
|
|
8012b40: f997 300f ldrsb.w r3, [r7, #15]
|
|
8012b44: 2b00 cmp r3, #0
|
|
8012b46: d114 bne.n 8012b72 <tcp_close_shutdown_fin+0x82>
|
|
MIB2_STATS_INC(mib2.tcpestabresets);
|
|
pcb->state = FIN_WAIT_1;
|
|
8012b48: 687b ldr r3, [r7, #4]
|
|
8012b4a: 2205 movs r2, #5
|
|
8012b4c: 751a strb r2, [r3, #20]
|
|
}
|
|
break;
|
|
8012b4e: e010 b.n 8012b72 <tcp_close_shutdown_fin+0x82>
|
|
case CLOSE_WAIT:
|
|
err = tcp_send_fin(pcb);
|
|
8012b50: 6878 ldr r0, [r7, #4]
|
|
8012b52: f003 fec1 bl 80168d8 <tcp_send_fin>
|
|
8012b56: 4603 mov r3, r0
|
|
8012b58: 73fb strb r3, [r7, #15]
|
|
if (err == ERR_OK) {
|
|
8012b5a: f997 300f ldrsb.w r3, [r7, #15]
|
|
8012b5e: 2b00 cmp r3, #0
|
|
8012b60: d109 bne.n 8012b76 <tcp_close_shutdown_fin+0x86>
|
|
MIB2_STATS_INC(mib2.tcpestabresets);
|
|
pcb->state = LAST_ACK;
|
|
8012b62: 687b ldr r3, [r7, #4]
|
|
8012b64: 2209 movs r2, #9
|
|
8012b66: 751a strb r2, [r3, #20]
|
|
}
|
|
break;
|
|
8012b68: e005 b.n 8012b76 <tcp_close_shutdown_fin+0x86>
|
|
default:
|
|
/* Has already been closed, do nothing. */
|
|
return ERR_OK;
|
|
8012b6a: 2300 movs r3, #0
|
|
8012b6c: e01c b.n 8012ba8 <tcp_close_shutdown_fin+0xb8>
|
|
break;
|
|
8012b6e: bf00 nop
|
|
8012b70: e002 b.n 8012b78 <tcp_close_shutdown_fin+0x88>
|
|
break;
|
|
8012b72: bf00 nop
|
|
8012b74: e000 b.n 8012b78 <tcp_close_shutdown_fin+0x88>
|
|
break;
|
|
8012b76: bf00 nop
|
|
}
|
|
|
|
if (err == ERR_OK) {
|
|
8012b78: f997 300f ldrsb.w r3, [r7, #15]
|
|
8012b7c: 2b00 cmp r3, #0
|
|
8012b7e: d103 bne.n 8012b88 <tcp_close_shutdown_fin+0x98>
|
|
/* To ensure all data has been sent when tcp_close returns, we have
|
|
to make sure tcp_output doesn't fail.
|
|
Since we don't really have to ensure all data has been sent when tcp_close
|
|
returns (unsent data is sent from tcp timer functions, also), we don't care
|
|
for the return value of tcp_output for now. */
|
|
tcp_output(pcb);
|
|
8012b80: 6878 ldr r0, [r7, #4]
|
|
8012b82: f003 ffe7 bl 8016b54 <tcp_output>
|
|
8012b86: e00d b.n 8012ba4 <tcp_close_shutdown_fin+0xb4>
|
|
} else if (err == ERR_MEM) {
|
|
8012b88: f997 300f ldrsb.w r3, [r7, #15]
|
|
8012b8c: f1b3 3fff cmp.w r3, #4294967295
|
|
8012b90: d108 bne.n 8012ba4 <tcp_close_shutdown_fin+0xb4>
|
|
/* Mark this pcb for closing. Closing is retried from tcp_tmr. */
|
|
tcp_set_flags(pcb, TF_CLOSEPEND);
|
|
8012b92: 687b ldr r3, [r7, #4]
|
|
8012b94: 8b5b ldrh r3, [r3, #26]
|
|
8012b96: f043 0308 orr.w r3, r3, #8
|
|
8012b9a: b29a uxth r2, r3
|
|
8012b9c: 687b ldr r3, [r7, #4]
|
|
8012b9e: 835a strh r2, [r3, #26]
|
|
/* We have to return ERR_OK from here to indicate to the callers that this
|
|
pcb should not be used any more as it will be freed soon via tcp_tmr.
|
|
This is OK here since sending FIN does not guarantee a time frime for
|
|
actually freeing the pcb, either (it is left in closure states for
|
|
remote ACK or timeout) */
|
|
return ERR_OK;
|
|
8012ba0: 2300 movs r3, #0
|
|
8012ba2: e001 b.n 8012ba8 <tcp_close_shutdown_fin+0xb8>
|
|
}
|
|
return err;
|
|
8012ba4: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8012ba8: 4618 mov r0, r3
|
|
8012baa: 3710 adds r7, #16
|
|
8012bac: 46bd mov sp, r7
|
|
8012bae: bd80 pop {r7, pc}
|
|
8012bb0: 0801eb48 .word 0x0801eb48
|
|
8012bb4: 0801ebf8 .word 0x0801ebf8
|
|
8012bb8: 0801eb8c .word 0x0801eb8c
|
|
|
|
08012bbc <tcp_close>:
|
|
* @return ERR_OK if connection has been closed
|
|
* another err_t if closing failed and pcb is not freed
|
|
*/
|
|
err_t
|
|
tcp_close(struct tcp_pcb *pcb)
|
|
{
|
|
8012bbc: b580 push {r7, lr}
|
|
8012bbe: b082 sub sp, #8
|
|
8012bc0: af00 add r7, sp, #0
|
|
8012bc2: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
8012bc4: 687b ldr r3, [r7, #4]
|
|
8012bc6: 2b00 cmp r3, #0
|
|
8012bc8: d109 bne.n 8012bde <tcp_close+0x22>
|
|
8012bca: 4b0f ldr r3, [pc, #60] ; (8012c08 <tcp_close+0x4c>)
|
|
8012bcc: f44f 72f4 mov.w r2, #488 ; 0x1e8
|
|
8012bd0: 490e ldr r1, [pc, #56] ; (8012c0c <tcp_close+0x50>)
|
|
8012bd2: 480f ldr r0, [pc, #60] ; (8012c10 <tcp_close+0x54>)
|
|
8012bd4: f00a f870 bl 801ccb8 <iprintf>
|
|
8012bd8: f06f 030f mvn.w r3, #15
|
|
8012bdc: e00f b.n 8012bfe <tcp_close+0x42>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in "));
|
|
|
|
tcp_debug_print_state(pcb->state);
|
|
|
|
if (pcb->state != LISTEN) {
|
|
8012bde: 687b ldr r3, [r7, #4]
|
|
8012be0: 7d1b ldrb r3, [r3, #20]
|
|
8012be2: 2b01 cmp r3, #1
|
|
8012be4: d006 beq.n 8012bf4 <tcp_close+0x38>
|
|
/* Set a flag not to receive any more data... */
|
|
tcp_set_flags(pcb, TF_RXCLOSED);
|
|
8012be6: 687b ldr r3, [r7, #4]
|
|
8012be8: 8b5b ldrh r3, [r3, #26]
|
|
8012bea: f043 0310 orr.w r3, r3, #16
|
|
8012bee: b29a uxth r2, r3
|
|
8012bf0: 687b ldr r3, [r7, #4]
|
|
8012bf2: 835a strh r2, [r3, #26]
|
|
}
|
|
/* ... and close */
|
|
return tcp_close_shutdown(pcb, 1);
|
|
8012bf4: 2101 movs r1, #1
|
|
8012bf6: 6878 ldr r0, [r7, #4]
|
|
8012bf8: f7ff fe9c bl 8012934 <tcp_close_shutdown>
|
|
8012bfc: 4603 mov r3, r0
|
|
}
|
|
8012bfe: 4618 mov r0, r3
|
|
8012c00: 3708 adds r7, #8
|
|
8012c02: 46bd mov sp, r7
|
|
8012c04: bd80 pop {r7, pc}
|
|
8012c06: bf00 nop
|
|
8012c08: 0801eb48 .word 0x0801eb48
|
|
8012c0c: 0801ec58 .word 0x0801ec58
|
|
8012c10: 0801eb8c .word 0x0801eb8c
|
|
|
|
08012c14 <tcp_abandon>:
|
|
* @param pcb the tcp_pcb to abort
|
|
* @param reset boolean to indicate whether a reset should be sent
|
|
*/
|
|
void
|
|
tcp_abandon(struct tcp_pcb *pcb, int reset)
|
|
{
|
|
8012c14: b580 push {r7, lr}
|
|
8012c16: b08e sub sp, #56 ; 0x38
|
|
8012c18: af04 add r7, sp, #16
|
|
8012c1a: 6078 str r0, [r7, #4]
|
|
8012c1c: 6039 str r1, [r7, #0]
|
|
#endif /* LWIP_CALLBACK_API */
|
|
void *errf_arg;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return);
|
|
8012c1e: 687b ldr r3, [r7, #4]
|
|
8012c20: 2b00 cmp r3, #0
|
|
8012c22: d107 bne.n 8012c34 <tcp_abandon+0x20>
|
|
8012c24: 4b52 ldr r3, [pc, #328] ; (8012d70 <tcp_abandon+0x15c>)
|
|
8012c26: f240 223d movw r2, #573 ; 0x23d
|
|
8012c2a: 4952 ldr r1, [pc, #328] ; (8012d74 <tcp_abandon+0x160>)
|
|
8012c2c: 4852 ldr r0, [pc, #328] ; (8012d78 <tcp_abandon+0x164>)
|
|
8012c2e: f00a f843 bl 801ccb8 <iprintf>
|
|
8012c32: e099 b.n 8012d68 <tcp_abandon+0x154>
|
|
|
|
/* pcb->state LISTEN not allowed here */
|
|
LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs",
|
|
8012c34: 687b ldr r3, [r7, #4]
|
|
8012c36: 7d1b ldrb r3, [r3, #20]
|
|
8012c38: 2b01 cmp r3, #1
|
|
8012c3a: d106 bne.n 8012c4a <tcp_abandon+0x36>
|
|
8012c3c: 4b4c ldr r3, [pc, #304] ; (8012d70 <tcp_abandon+0x15c>)
|
|
8012c3e: f240 2241 movw r2, #577 ; 0x241
|
|
8012c42: 494e ldr r1, [pc, #312] ; (8012d7c <tcp_abandon+0x168>)
|
|
8012c44: 484c ldr r0, [pc, #304] ; (8012d78 <tcp_abandon+0x164>)
|
|
8012c46: f00a f837 bl 801ccb8 <iprintf>
|
|
pcb->state != LISTEN);
|
|
/* Figure out on which TCP PCB list we are, and remove us. If we
|
|
are in an active state, call the receive function associated with
|
|
the PCB with a NULL argument, and send an RST to the remote end. */
|
|
if (pcb->state == TIME_WAIT) {
|
|
8012c4a: 687b ldr r3, [r7, #4]
|
|
8012c4c: 7d1b ldrb r3, [r3, #20]
|
|
8012c4e: 2b0a cmp r3, #10
|
|
8012c50: d107 bne.n 8012c62 <tcp_abandon+0x4e>
|
|
tcp_pcb_remove(&tcp_tw_pcbs, pcb);
|
|
8012c52: 6879 ldr r1, [r7, #4]
|
|
8012c54: 484a ldr r0, [pc, #296] ; (8012d80 <tcp_abandon+0x16c>)
|
|
8012c56: f000 ffbf bl 8013bd8 <tcp_pcb_remove>
|
|
tcp_free(pcb);
|
|
8012c5a: 6878 ldr r0, [r7, #4]
|
|
8012c5c: f7ff fdb8 bl 80127d0 <tcp_free>
|
|
8012c60: e082 b.n 8012d68 <tcp_abandon+0x154>
|
|
} else {
|
|
int send_rst = 0;
|
|
8012c62: 2300 movs r3, #0
|
|
8012c64: 627b str r3, [r7, #36] ; 0x24
|
|
u16_t local_port = 0;
|
|
8012c66: 2300 movs r3, #0
|
|
8012c68: 847b strh r3, [r7, #34] ; 0x22
|
|
enum tcp_state last_state;
|
|
seqno = pcb->snd_nxt;
|
|
8012c6a: 687b ldr r3, [r7, #4]
|
|
8012c6c: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8012c6e: 61bb str r3, [r7, #24]
|
|
ackno = pcb->rcv_nxt;
|
|
8012c70: 687b ldr r3, [r7, #4]
|
|
8012c72: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8012c74: 617b str r3, [r7, #20]
|
|
#if LWIP_CALLBACK_API
|
|
errf = pcb->errf;
|
|
8012c76: 687b ldr r3, [r7, #4]
|
|
8012c78: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8012c7c: 613b str r3, [r7, #16]
|
|
#endif /* LWIP_CALLBACK_API */
|
|
errf_arg = pcb->callback_arg;
|
|
8012c7e: 687b ldr r3, [r7, #4]
|
|
8012c80: 691b ldr r3, [r3, #16]
|
|
8012c82: 60fb str r3, [r7, #12]
|
|
if (pcb->state == CLOSED) {
|
|
8012c84: 687b ldr r3, [r7, #4]
|
|
8012c86: 7d1b ldrb r3, [r3, #20]
|
|
8012c88: 2b00 cmp r3, #0
|
|
8012c8a: d126 bne.n 8012cda <tcp_abandon+0xc6>
|
|
if (pcb->local_port != 0) {
|
|
8012c8c: 687b ldr r3, [r7, #4]
|
|
8012c8e: 8adb ldrh r3, [r3, #22]
|
|
8012c90: 2b00 cmp r3, #0
|
|
8012c92: d02e beq.n 8012cf2 <tcp_abandon+0xde>
|
|
/* bound, not yet opened */
|
|
TCP_RMV(&tcp_bound_pcbs, pcb);
|
|
8012c94: 4b3b ldr r3, [pc, #236] ; (8012d84 <tcp_abandon+0x170>)
|
|
8012c96: 681b ldr r3, [r3, #0]
|
|
8012c98: 687a ldr r2, [r7, #4]
|
|
8012c9a: 429a cmp r2, r3
|
|
8012c9c: d105 bne.n 8012caa <tcp_abandon+0x96>
|
|
8012c9e: 4b39 ldr r3, [pc, #228] ; (8012d84 <tcp_abandon+0x170>)
|
|
8012ca0: 681b ldr r3, [r3, #0]
|
|
8012ca2: 68db ldr r3, [r3, #12]
|
|
8012ca4: 4a37 ldr r2, [pc, #220] ; (8012d84 <tcp_abandon+0x170>)
|
|
8012ca6: 6013 str r3, [r2, #0]
|
|
8012ca8: e013 b.n 8012cd2 <tcp_abandon+0xbe>
|
|
8012caa: 4b36 ldr r3, [pc, #216] ; (8012d84 <tcp_abandon+0x170>)
|
|
8012cac: 681b ldr r3, [r3, #0]
|
|
8012cae: 61fb str r3, [r7, #28]
|
|
8012cb0: e00c b.n 8012ccc <tcp_abandon+0xb8>
|
|
8012cb2: 69fb ldr r3, [r7, #28]
|
|
8012cb4: 68db ldr r3, [r3, #12]
|
|
8012cb6: 687a ldr r2, [r7, #4]
|
|
8012cb8: 429a cmp r2, r3
|
|
8012cba: d104 bne.n 8012cc6 <tcp_abandon+0xb2>
|
|
8012cbc: 687b ldr r3, [r7, #4]
|
|
8012cbe: 68da ldr r2, [r3, #12]
|
|
8012cc0: 69fb ldr r3, [r7, #28]
|
|
8012cc2: 60da str r2, [r3, #12]
|
|
8012cc4: e005 b.n 8012cd2 <tcp_abandon+0xbe>
|
|
8012cc6: 69fb ldr r3, [r7, #28]
|
|
8012cc8: 68db ldr r3, [r3, #12]
|
|
8012cca: 61fb str r3, [r7, #28]
|
|
8012ccc: 69fb ldr r3, [r7, #28]
|
|
8012cce: 2b00 cmp r3, #0
|
|
8012cd0: d1ef bne.n 8012cb2 <tcp_abandon+0x9e>
|
|
8012cd2: 687b ldr r3, [r7, #4]
|
|
8012cd4: 2200 movs r2, #0
|
|
8012cd6: 60da str r2, [r3, #12]
|
|
8012cd8: e00b b.n 8012cf2 <tcp_abandon+0xde>
|
|
}
|
|
} else {
|
|
send_rst = reset;
|
|
8012cda: 683b ldr r3, [r7, #0]
|
|
8012cdc: 627b str r3, [r7, #36] ; 0x24
|
|
local_port = pcb->local_port;
|
|
8012cde: 687b ldr r3, [r7, #4]
|
|
8012ce0: 8adb ldrh r3, [r3, #22]
|
|
8012ce2: 847b strh r3, [r7, #34] ; 0x22
|
|
TCP_PCB_REMOVE_ACTIVE(pcb);
|
|
8012ce4: 6879 ldr r1, [r7, #4]
|
|
8012ce6: 4828 ldr r0, [pc, #160] ; (8012d88 <tcp_abandon+0x174>)
|
|
8012ce8: f000 ff76 bl 8013bd8 <tcp_pcb_remove>
|
|
8012cec: 4b27 ldr r3, [pc, #156] ; (8012d8c <tcp_abandon+0x178>)
|
|
8012cee: 2201 movs r2, #1
|
|
8012cf0: 701a strb r2, [r3, #0]
|
|
}
|
|
if (pcb->unacked != NULL) {
|
|
8012cf2: 687b ldr r3, [r7, #4]
|
|
8012cf4: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8012cf6: 2b00 cmp r3, #0
|
|
8012cf8: d004 beq.n 8012d04 <tcp_abandon+0xf0>
|
|
tcp_segs_free(pcb->unacked);
|
|
8012cfa: 687b ldr r3, [r7, #4]
|
|
8012cfc: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8012cfe: 4618 mov r0, r3
|
|
8012d00: f000 fd1a bl 8013738 <tcp_segs_free>
|
|
}
|
|
if (pcb->unsent != NULL) {
|
|
8012d04: 687b ldr r3, [r7, #4]
|
|
8012d06: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8012d08: 2b00 cmp r3, #0
|
|
8012d0a: d004 beq.n 8012d16 <tcp_abandon+0x102>
|
|
tcp_segs_free(pcb->unsent);
|
|
8012d0c: 687b ldr r3, [r7, #4]
|
|
8012d0e: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8012d10: 4618 mov r0, r3
|
|
8012d12: f000 fd11 bl 8013738 <tcp_segs_free>
|
|
}
|
|
#if TCP_QUEUE_OOSEQ
|
|
if (pcb->ooseq != NULL) {
|
|
8012d16: 687b ldr r3, [r7, #4]
|
|
8012d18: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8012d1a: 2b00 cmp r3, #0
|
|
8012d1c: d004 beq.n 8012d28 <tcp_abandon+0x114>
|
|
tcp_segs_free(pcb->ooseq);
|
|
8012d1e: 687b ldr r3, [r7, #4]
|
|
8012d20: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8012d22: 4618 mov r0, r3
|
|
8012d24: f000 fd08 bl 8013738 <tcp_segs_free>
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
tcp_backlog_accepted(pcb);
|
|
if (send_rst) {
|
|
8012d28: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8012d2a: 2b00 cmp r3, #0
|
|
8012d2c: d00e beq.n 8012d4c <tcp_abandon+0x138>
|
|
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n"));
|
|
tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port);
|
|
8012d2e: 6879 ldr r1, [r7, #4]
|
|
8012d30: 687b ldr r3, [r7, #4]
|
|
8012d32: 3304 adds r3, #4
|
|
8012d34: 687a ldr r2, [r7, #4]
|
|
8012d36: 8b12 ldrh r2, [r2, #24]
|
|
8012d38: 9202 str r2, [sp, #8]
|
|
8012d3a: 8c7a ldrh r2, [r7, #34] ; 0x22
|
|
8012d3c: 9201 str r2, [sp, #4]
|
|
8012d3e: 9300 str r3, [sp, #0]
|
|
8012d40: 460b mov r3, r1
|
|
8012d42: 697a ldr r2, [r7, #20]
|
|
8012d44: 69b9 ldr r1, [r7, #24]
|
|
8012d46: 6878 ldr r0, [r7, #4]
|
|
8012d48: f004 fcca bl 80176e0 <tcp_rst>
|
|
}
|
|
last_state = pcb->state;
|
|
8012d4c: 687b ldr r3, [r7, #4]
|
|
8012d4e: 7d1b ldrb r3, [r3, #20]
|
|
8012d50: 72fb strb r3, [r7, #11]
|
|
tcp_free(pcb);
|
|
8012d52: 6878 ldr r0, [r7, #4]
|
|
8012d54: f7ff fd3c bl 80127d0 <tcp_free>
|
|
TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT);
|
|
8012d58: 693b ldr r3, [r7, #16]
|
|
8012d5a: 2b00 cmp r3, #0
|
|
8012d5c: d004 beq.n 8012d68 <tcp_abandon+0x154>
|
|
8012d5e: 693b ldr r3, [r7, #16]
|
|
8012d60: f06f 010c mvn.w r1, #12
|
|
8012d64: 68f8 ldr r0, [r7, #12]
|
|
8012d66: 4798 blx r3
|
|
}
|
|
}
|
|
8012d68: 3728 adds r7, #40 ; 0x28
|
|
8012d6a: 46bd mov sp, r7
|
|
8012d6c: bd80 pop {r7, pc}
|
|
8012d6e: bf00 nop
|
|
8012d70: 0801eb48 .word 0x0801eb48
|
|
8012d74: 0801ec8c .word 0x0801ec8c
|
|
8012d78: 0801eb8c .word 0x0801eb8c
|
|
8012d7c: 0801eca8 .word 0x0801eca8
|
|
8012d80: 2000f80c .word 0x2000f80c
|
|
8012d84: 2000f808 .word 0x2000f808
|
|
8012d88: 2000f7fc .word 0x2000f7fc
|
|
8012d8c: 2000f7f8 .word 0x2000f7f8
|
|
|
|
08012d90 <tcp_abort>:
|
|
*
|
|
* @param pcb the tcp pcb to abort
|
|
*/
|
|
void
|
|
tcp_abort(struct tcp_pcb *pcb)
|
|
{
|
|
8012d90: b580 push {r7, lr}
|
|
8012d92: b082 sub sp, #8
|
|
8012d94: af00 add r7, sp, #0
|
|
8012d96: 6078 str r0, [r7, #4]
|
|
tcp_abandon(pcb, 1);
|
|
8012d98: 2101 movs r1, #1
|
|
8012d9a: 6878 ldr r0, [r7, #4]
|
|
8012d9c: f7ff ff3a bl 8012c14 <tcp_abandon>
|
|
}
|
|
8012da0: bf00 nop
|
|
8012da2: 3708 adds r7, #8
|
|
8012da4: 46bd mov sp, r7
|
|
8012da6: bd80 pop {r7, pc}
|
|
|
|
08012da8 <tcp_update_rcv_ann_wnd>:
|
|
* Returns how much extra window would be advertised if we sent an
|
|
* update now.
|
|
*/
|
|
u32_t
|
|
tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb)
|
|
{
|
|
8012da8: b580 push {r7, lr}
|
|
8012daa: b084 sub sp, #16
|
|
8012dac: af00 add r7, sp, #0
|
|
8012dae: 6078 str r0, [r7, #4]
|
|
u32_t new_right_edge;
|
|
|
|
LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL);
|
|
8012db0: 687b ldr r3, [r7, #4]
|
|
8012db2: 2b00 cmp r3, #0
|
|
8012db4: d106 bne.n 8012dc4 <tcp_update_rcv_ann_wnd+0x1c>
|
|
8012db6: 4b25 ldr r3, [pc, #148] ; (8012e4c <tcp_update_rcv_ann_wnd+0xa4>)
|
|
8012db8: f240 32a6 movw r2, #934 ; 0x3a6
|
|
8012dbc: 4924 ldr r1, [pc, #144] ; (8012e50 <tcp_update_rcv_ann_wnd+0xa8>)
|
|
8012dbe: 4825 ldr r0, [pc, #148] ; (8012e54 <tcp_update_rcv_ann_wnd+0xac>)
|
|
8012dc0: f009 ff7a bl 801ccb8 <iprintf>
|
|
new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd;
|
|
8012dc4: 687b ldr r3, [r7, #4]
|
|
8012dc6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8012dc8: 687a ldr r2, [r7, #4]
|
|
8012dca: 8d12 ldrh r2, [r2, #40] ; 0x28
|
|
8012dcc: 4413 add r3, r2
|
|
8012dce: 60fb str r3, [r7, #12]
|
|
|
|
if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) {
|
|
8012dd0: 687b ldr r3, [r7, #4]
|
|
8012dd2: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8012dd4: 687a ldr r2, [r7, #4]
|
|
8012dd6: 8e52 ldrh r2, [r2, #50] ; 0x32
|
|
8012dd8: f5b2 6f86 cmp.w r2, #1072 ; 0x430
|
|
8012ddc: bf28 it cs
|
|
8012dde: f44f 6286 movcs.w r2, #1072 ; 0x430
|
|
8012de2: b292 uxth r2, r2
|
|
8012de4: 4413 add r3, r2
|
|
8012de6: 68fa ldr r2, [r7, #12]
|
|
8012de8: 1ad3 subs r3, r2, r3
|
|
8012dea: 2b00 cmp r3, #0
|
|
8012dec: db08 blt.n 8012e00 <tcp_update_rcv_ann_wnd+0x58>
|
|
/* we can advertise more window */
|
|
pcb->rcv_ann_wnd = pcb->rcv_wnd;
|
|
8012dee: 687b ldr r3, [r7, #4]
|
|
8012df0: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8012df2: 687b ldr r3, [r7, #4]
|
|
8012df4: 855a strh r2, [r3, #42] ; 0x2a
|
|
return new_right_edge - pcb->rcv_ann_right_edge;
|
|
8012df6: 687b ldr r3, [r7, #4]
|
|
8012df8: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8012dfa: 68fa ldr r2, [r7, #12]
|
|
8012dfc: 1ad3 subs r3, r2, r3
|
|
8012dfe: e020 b.n 8012e42 <tcp_update_rcv_ann_wnd+0x9a>
|
|
} else {
|
|
if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) {
|
|
8012e00: 687b ldr r3, [r7, #4]
|
|
8012e02: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8012e04: 687b ldr r3, [r7, #4]
|
|
8012e06: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8012e08: 1ad3 subs r3, r2, r3
|
|
8012e0a: 2b00 cmp r3, #0
|
|
8012e0c: dd03 ble.n 8012e16 <tcp_update_rcv_ann_wnd+0x6e>
|
|
/* Can happen due to other end sending out of advertised window,
|
|
* but within actual available (but not yet advertised) window */
|
|
pcb->rcv_ann_wnd = 0;
|
|
8012e0e: 687b ldr r3, [r7, #4]
|
|
8012e10: 2200 movs r2, #0
|
|
8012e12: 855a strh r2, [r3, #42] ; 0x2a
|
|
8012e14: e014 b.n 8012e40 <tcp_update_rcv_ann_wnd+0x98>
|
|
} else {
|
|
/* keep the right edge of window constant */
|
|
u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt;
|
|
8012e16: 687b ldr r3, [r7, #4]
|
|
8012e18: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
8012e1a: 687b ldr r3, [r7, #4]
|
|
8012e1c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8012e1e: 1ad3 subs r3, r2, r3
|
|
8012e20: 60bb str r3, [r7, #8]
|
|
#if !LWIP_WND_SCALE
|
|
LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff);
|
|
8012e22: 68bb ldr r3, [r7, #8]
|
|
8012e24: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8012e28: d306 bcc.n 8012e38 <tcp_update_rcv_ann_wnd+0x90>
|
|
8012e2a: 4b08 ldr r3, [pc, #32] ; (8012e4c <tcp_update_rcv_ann_wnd+0xa4>)
|
|
8012e2c: f240 32b6 movw r2, #950 ; 0x3b6
|
|
8012e30: 4909 ldr r1, [pc, #36] ; (8012e58 <tcp_update_rcv_ann_wnd+0xb0>)
|
|
8012e32: 4808 ldr r0, [pc, #32] ; (8012e54 <tcp_update_rcv_ann_wnd+0xac>)
|
|
8012e34: f009 ff40 bl 801ccb8 <iprintf>
|
|
#endif
|
|
pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd;
|
|
8012e38: 68bb ldr r3, [r7, #8]
|
|
8012e3a: b29a uxth r2, r3
|
|
8012e3c: 687b ldr r3, [r7, #4]
|
|
8012e3e: 855a strh r2, [r3, #42] ; 0x2a
|
|
}
|
|
return 0;
|
|
8012e40: 2300 movs r3, #0
|
|
}
|
|
}
|
|
8012e42: 4618 mov r0, r3
|
|
8012e44: 3710 adds r7, #16
|
|
8012e46: 46bd mov sp, r7
|
|
8012e48: bd80 pop {r7, pc}
|
|
8012e4a: bf00 nop
|
|
8012e4c: 0801eb48 .word 0x0801eb48
|
|
8012e50: 0801eda4 .word 0x0801eda4
|
|
8012e54: 0801eb8c .word 0x0801eb8c
|
|
8012e58: 0801edc8 .word 0x0801edc8
|
|
|
|
08012e5c <tcp_recved>:
|
|
* @param pcb the tcp_pcb for which data is read
|
|
* @param len the amount of bytes that have been read by the application
|
|
*/
|
|
void
|
|
tcp_recved(struct tcp_pcb *pcb, u16_t len)
|
|
{
|
|
8012e5c: b580 push {r7, lr}
|
|
8012e5e: b084 sub sp, #16
|
|
8012e60: af00 add r7, sp, #0
|
|
8012e62: 6078 str r0, [r7, #4]
|
|
8012e64: 460b mov r3, r1
|
|
8012e66: 807b strh r3, [r7, #2]
|
|
u32_t wnd_inflation;
|
|
tcpwnd_size_t rcv_wnd;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return);
|
|
8012e68: 687b ldr r3, [r7, #4]
|
|
8012e6a: 2b00 cmp r3, #0
|
|
8012e6c: d107 bne.n 8012e7e <tcp_recved+0x22>
|
|
8012e6e: 4b1f ldr r3, [pc, #124] ; (8012eec <tcp_recved+0x90>)
|
|
8012e70: f240 32cf movw r2, #975 ; 0x3cf
|
|
8012e74: 491e ldr r1, [pc, #120] ; (8012ef0 <tcp_recved+0x94>)
|
|
8012e76: 481f ldr r0, [pc, #124] ; (8012ef4 <tcp_recved+0x98>)
|
|
8012e78: f009 ff1e bl 801ccb8 <iprintf>
|
|
8012e7c: e032 b.n 8012ee4 <tcp_recved+0x88>
|
|
|
|
/* pcb->state LISTEN not allowed here */
|
|
LWIP_ASSERT("don't call tcp_recved for listen-pcbs",
|
|
8012e7e: 687b ldr r3, [r7, #4]
|
|
8012e80: 7d1b ldrb r3, [r3, #20]
|
|
8012e82: 2b01 cmp r3, #1
|
|
8012e84: d106 bne.n 8012e94 <tcp_recved+0x38>
|
|
8012e86: 4b19 ldr r3, [pc, #100] ; (8012eec <tcp_recved+0x90>)
|
|
8012e88: f240 32d3 movw r2, #979 ; 0x3d3
|
|
8012e8c: 491a ldr r1, [pc, #104] ; (8012ef8 <tcp_recved+0x9c>)
|
|
8012e8e: 4819 ldr r0, [pc, #100] ; (8012ef4 <tcp_recved+0x98>)
|
|
8012e90: f009 ff12 bl 801ccb8 <iprintf>
|
|
pcb->state != LISTEN);
|
|
|
|
rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len);
|
|
8012e94: 687b ldr r3, [r7, #4]
|
|
8012e96: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8012e98: 887b ldrh r3, [r7, #2]
|
|
8012e9a: 4413 add r3, r2
|
|
8012e9c: 81fb strh r3, [r7, #14]
|
|
if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) {
|
|
8012e9e: 89fb ldrh r3, [r7, #14]
|
|
8012ea0: f5b3 6f06 cmp.w r3, #2144 ; 0x860
|
|
8012ea4: d804 bhi.n 8012eb0 <tcp_recved+0x54>
|
|
8012ea6: 687b ldr r3, [r7, #4]
|
|
8012ea8: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8012eaa: 89fa ldrh r2, [r7, #14]
|
|
8012eac: 429a cmp r2, r3
|
|
8012eae: d204 bcs.n 8012eba <tcp_recved+0x5e>
|
|
/* window got too big or tcpwnd_size_t overflow */
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n"));
|
|
pcb->rcv_wnd = TCP_WND_MAX(pcb);
|
|
8012eb0: 687b ldr r3, [r7, #4]
|
|
8012eb2: f44f 6206 mov.w r2, #2144 ; 0x860
|
|
8012eb6: 851a strh r2, [r3, #40] ; 0x28
|
|
8012eb8: e002 b.n 8012ec0 <tcp_recved+0x64>
|
|
} else {
|
|
pcb->rcv_wnd = rcv_wnd;
|
|
8012eba: 687b ldr r3, [r7, #4]
|
|
8012ebc: 89fa ldrh r2, [r7, #14]
|
|
8012ebe: 851a strh r2, [r3, #40] ; 0x28
|
|
}
|
|
|
|
wnd_inflation = tcp_update_rcv_ann_wnd(pcb);
|
|
8012ec0: 6878 ldr r0, [r7, #4]
|
|
8012ec2: f7ff ff71 bl 8012da8 <tcp_update_rcv_ann_wnd>
|
|
8012ec6: 60b8 str r0, [r7, #8]
|
|
|
|
/* If the change in the right edge of window is significant (default
|
|
* watermark is TCP_WND/4), then send an explicit update now.
|
|
* Otherwise wait for a packet to be sent in the normal course of
|
|
* events (or more window to be available later) */
|
|
if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) {
|
|
8012ec8: 68bb ldr r3, [r7, #8]
|
|
8012eca: f5b3 7f06 cmp.w r3, #536 ; 0x218
|
|
8012ece: d309 bcc.n 8012ee4 <tcp_recved+0x88>
|
|
tcp_ack_now(pcb);
|
|
8012ed0: 687b ldr r3, [r7, #4]
|
|
8012ed2: 8b5b ldrh r3, [r3, #26]
|
|
8012ed4: f043 0302 orr.w r3, r3, #2
|
|
8012ed8: b29a uxth r2, r3
|
|
8012eda: 687b ldr r3, [r7, #4]
|
|
8012edc: 835a strh r2, [r3, #26]
|
|
tcp_output(pcb);
|
|
8012ede: 6878 ldr r0, [r7, #4]
|
|
8012ee0: f003 fe38 bl 8016b54 <tcp_output>
|
|
}
|
|
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n",
|
|
len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd)));
|
|
}
|
|
8012ee4: 3710 adds r7, #16
|
|
8012ee6: 46bd mov sp, r7
|
|
8012ee8: bd80 pop {r7, pc}
|
|
8012eea: bf00 nop
|
|
8012eec: 0801eb48 .word 0x0801eb48
|
|
8012ef0: 0801ede4 .word 0x0801ede4
|
|
8012ef4: 0801eb8c .word 0x0801eb8c
|
|
8012ef8: 0801edfc .word 0x0801edfc
|
|
|
|
08012efc <tcp_slowtmr>:
|
|
*
|
|
* Automatically called from tcp_tmr().
|
|
*/
|
|
void
|
|
tcp_slowtmr(void)
|
|
{
|
|
8012efc: b5b0 push {r4, r5, r7, lr}
|
|
8012efe: b090 sub sp, #64 ; 0x40
|
|
8012f00: af04 add r7, sp, #16
|
|
tcpwnd_size_t eff_wnd;
|
|
u8_t pcb_remove; /* flag if a PCB should be removed */
|
|
u8_t pcb_reset; /* flag if a RST should be sent when removing */
|
|
err_t err;
|
|
|
|
err = ERR_OK;
|
|
8012f02: 2300 movs r3, #0
|
|
8012f04: f887 3025 strb.w r3, [r7, #37] ; 0x25
|
|
|
|
++tcp_ticks;
|
|
8012f08: 4b94 ldr r3, [pc, #592] ; (801315c <tcp_slowtmr+0x260>)
|
|
8012f0a: 681b ldr r3, [r3, #0]
|
|
8012f0c: 3301 adds r3, #1
|
|
8012f0e: 4a93 ldr r2, [pc, #588] ; (801315c <tcp_slowtmr+0x260>)
|
|
8012f10: 6013 str r3, [r2, #0]
|
|
++tcp_timer_ctr;
|
|
8012f12: 4b93 ldr r3, [pc, #588] ; (8013160 <tcp_slowtmr+0x264>)
|
|
8012f14: 781b ldrb r3, [r3, #0]
|
|
8012f16: 3301 adds r3, #1
|
|
8012f18: b2da uxtb r2, r3
|
|
8012f1a: 4b91 ldr r3, [pc, #580] ; (8013160 <tcp_slowtmr+0x264>)
|
|
8012f1c: 701a strb r2, [r3, #0]
|
|
|
|
tcp_slowtmr_start:
|
|
/* Steps through all of the active PCBs. */
|
|
prev = NULL;
|
|
8012f1e: 2300 movs r3, #0
|
|
8012f20: 62bb str r3, [r7, #40] ; 0x28
|
|
pcb = tcp_active_pcbs;
|
|
8012f22: 4b90 ldr r3, [pc, #576] ; (8013164 <tcp_slowtmr+0x268>)
|
|
8012f24: 681b ldr r3, [r3, #0]
|
|
8012f26: 62fb str r3, [r7, #44] ; 0x2c
|
|
if (pcb == NULL) {
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n"));
|
|
}
|
|
while (pcb != NULL) {
|
|
8012f28: e29d b.n 8013466 <tcp_slowtmr+0x56a>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n"));
|
|
LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED);
|
|
8012f2a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f2c: 7d1b ldrb r3, [r3, #20]
|
|
8012f2e: 2b00 cmp r3, #0
|
|
8012f30: d106 bne.n 8012f40 <tcp_slowtmr+0x44>
|
|
8012f32: 4b8d ldr r3, [pc, #564] ; (8013168 <tcp_slowtmr+0x26c>)
|
|
8012f34: f240 42be movw r2, #1214 ; 0x4be
|
|
8012f38: 498c ldr r1, [pc, #560] ; (801316c <tcp_slowtmr+0x270>)
|
|
8012f3a: 488d ldr r0, [pc, #564] ; (8013170 <tcp_slowtmr+0x274>)
|
|
8012f3c: f009 febc bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN);
|
|
8012f40: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f42: 7d1b ldrb r3, [r3, #20]
|
|
8012f44: 2b01 cmp r3, #1
|
|
8012f46: d106 bne.n 8012f56 <tcp_slowtmr+0x5a>
|
|
8012f48: 4b87 ldr r3, [pc, #540] ; (8013168 <tcp_slowtmr+0x26c>)
|
|
8012f4a: f240 42bf movw r2, #1215 ; 0x4bf
|
|
8012f4e: 4989 ldr r1, [pc, #548] ; (8013174 <tcp_slowtmr+0x278>)
|
|
8012f50: 4887 ldr r0, [pc, #540] ; (8013170 <tcp_slowtmr+0x274>)
|
|
8012f52: f009 feb1 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT);
|
|
8012f56: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f58: 7d1b ldrb r3, [r3, #20]
|
|
8012f5a: 2b0a cmp r3, #10
|
|
8012f5c: d106 bne.n 8012f6c <tcp_slowtmr+0x70>
|
|
8012f5e: 4b82 ldr r3, [pc, #520] ; (8013168 <tcp_slowtmr+0x26c>)
|
|
8012f60: f44f 6298 mov.w r2, #1216 ; 0x4c0
|
|
8012f64: 4984 ldr r1, [pc, #528] ; (8013178 <tcp_slowtmr+0x27c>)
|
|
8012f66: 4882 ldr r0, [pc, #520] ; (8013170 <tcp_slowtmr+0x274>)
|
|
8012f68: f009 fea6 bl 801ccb8 <iprintf>
|
|
if (pcb->last_timer == tcp_timer_ctr) {
|
|
8012f6c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f6e: 7f9a ldrb r2, [r3, #30]
|
|
8012f70: 4b7b ldr r3, [pc, #492] ; (8013160 <tcp_slowtmr+0x264>)
|
|
8012f72: 781b ldrb r3, [r3, #0]
|
|
8012f74: 429a cmp r2, r3
|
|
8012f76: d105 bne.n 8012f84 <tcp_slowtmr+0x88>
|
|
/* skip this pcb, we have already processed it */
|
|
prev = pcb;
|
|
8012f78: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f7a: 62bb str r3, [r7, #40] ; 0x28
|
|
pcb = pcb->next;
|
|
8012f7c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f7e: 68db ldr r3, [r3, #12]
|
|
8012f80: 62fb str r3, [r7, #44] ; 0x2c
|
|
continue;
|
|
8012f82: e270 b.n 8013466 <tcp_slowtmr+0x56a>
|
|
}
|
|
pcb->last_timer = tcp_timer_ctr;
|
|
8012f84: 4b76 ldr r3, [pc, #472] ; (8013160 <tcp_slowtmr+0x264>)
|
|
8012f86: 781a ldrb r2, [r3, #0]
|
|
8012f88: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f8a: 779a strb r2, [r3, #30]
|
|
|
|
pcb_remove = 0;
|
|
8012f8c: 2300 movs r3, #0
|
|
8012f8e: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
pcb_reset = 0;
|
|
8012f92: 2300 movs r3, #0
|
|
8012f94: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
|
|
if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) {
|
|
8012f98: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012f9a: 7d1b ldrb r3, [r3, #20]
|
|
8012f9c: 2b02 cmp r3, #2
|
|
8012f9e: d10a bne.n 8012fb6 <tcp_slowtmr+0xba>
|
|
8012fa0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012fa2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8012fa6: 2b05 cmp r3, #5
|
|
8012fa8: d905 bls.n 8012fb6 <tcp_slowtmr+0xba>
|
|
++pcb_remove;
|
|
8012faa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8012fae: 3301 adds r3, #1
|
|
8012fb0: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8012fb4: e11e b.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n"));
|
|
} else if (pcb->nrtx >= TCP_MAXRTX) {
|
|
8012fb6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012fb8: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8012fbc: 2b0b cmp r3, #11
|
|
8012fbe: d905 bls.n 8012fcc <tcp_slowtmr+0xd0>
|
|
++pcb_remove;
|
|
8012fc0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8012fc4: 3301 adds r3, #1
|
|
8012fc6: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8012fca: e113 b.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n"));
|
|
} else {
|
|
if (pcb->persist_backoff > 0) {
|
|
8012fcc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012fce: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
|
|
8012fd2: 2b00 cmp r3, #0
|
|
8012fd4: d075 beq.n 80130c2 <tcp_slowtmr+0x1c6>
|
|
LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL);
|
|
8012fd6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012fd8: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8012fda: 2b00 cmp r3, #0
|
|
8012fdc: d006 beq.n 8012fec <tcp_slowtmr+0xf0>
|
|
8012fde: 4b62 ldr r3, [pc, #392] ; (8013168 <tcp_slowtmr+0x26c>)
|
|
8012fe0: f240 42d4 movw r2, #1236 ; 0x4d4
|
|
8012fe4: 4965 ldr r1, [pc, #404] ; (801317c <tcp_slowtmr+0x280>)
|
|
8012fe6: 4862 ldr r0, [pc, #392] ; (8013170 <tcp_slowtmr+0x274>)
|
|
8012fe8: f009 fe66 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL);
|
|
8012fec: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8012fee: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8012ff0: 2b00 cmp r3, #0
|
|
8012ff2: d106 bne.n 8013002 <tcp_slowtmr+0x106>
|
|
8012ff4: 4b5c ldr r3, [pc, #368] ; (8013168 <tcp_slowtmr+0x26c>)
|
|
8012ff6: f240 42d5 movw r2, #1237 ; 0x4d5
|
|
8012ffa: 4961 ldr r1, [pc, #388] ; (8013180 <tcp_slowtmr+0x284>)
|
|
8012ffc: 485c ldr r0, [pc, #368] ; (8013170 <tcp_slowtmr+0x274>)
|
|
8012ffe: f009 fe5b bl 801ccb8 <iprintf>
|
|
if (pcb->persist_probe >= TCP_MAXRTX) {
|
|
8013002: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013004: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
|
|
8013008: 2b0b cmp r3, #11
|
|
801300a: d905 bls.n 8013018 <tcp_slowtmr+0x11c>
|
|
++pcb_remove; /* max probes reached */
|
|
801300c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8013010: 3301 adds r3, #1
|
|
8013012: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8013016: e0ed b.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
} else {
|
|
u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1];
|
|
8013018: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801301a: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
|
|
801301e: 3b01 subs r3, #1
|
|
8013020: 4a58 ldr r2, [pc, #352] ; (8013184 <tcp_slowtmr+0x288>)
|
|
8013022: 5cd3 ldrb r3, [r2, r3]
|
|
8013024: 747b strb r3, [r7, #17]
|
|
if (pcb->persist_cnt < backoff_cnt) {
|
|
8013026: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013028: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
|
|
801302c: 7c7a ldrb r2, [r7, #17]
|
|
801302e: 429a cmp r2, r3
|
|
8013030: d907 bls.n 8013042 <tcp_slowtmr+0x146>
|
|
pcb->persist_cnt++;
|
|
8013032: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013034: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
|
|
8013038: 3301 adds r3, #1
|
|
801303a: b2da uxtb r2, r3
|
|
801303c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801303e: f883 2098 strb.w r2, [r3, #152] ; 0x98
|
|
}
|
|
if (pcb->persist_cnt >= backoff_cnt) {
|
|
8013042: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013044: f893 3098 ldrb.w r3, [r3, #152] ; 0x98
|
|
8013048: 7c7a ldrb r2, [r7, #17]
|
|
801304a: 429a cmp r2, r3
|
|
801304c: f200 80d2 bhi.w 80131f4 <tcp_slowtmr+0x2f8>
|
|
int next_slot = 1; /* increment timer to next slot */
|
|
8013050: 2301 movs r3, #1
|
|
8013052: 623b str r3, [r7, #32]
|
|
/* If snd_wnd is zero, send 1 byte probes */
|
|
if (pcb->snd_wnd == 0) {
|
|
8013054: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013056: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
801305a: 2b00 cmp r3, #0
|
|
801305c: d108 bne.n 8013070 <tcp_slowtmr+0x174>
|
|
if (tcp_zero_window_probe(pcb) != ERR_OK) {
|
|
801305e: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
8013060: f004 fc32 bl 80178c8 <tcp_zero_window_probe>
|
|
8013064: 4603 mov r3, r0
|
|
8013066: 2b00 cmp r3, #0
|
|
8013068: d014 beq.n 8013094 <tcp_slowtmr+0x198>
|
|
next_slot = 0; /* try probe again with current slot */
|
|
801306a: 2300 movs r3, #0
|
|
801306c: 623b str r3, [r7, #32]
|
|
801306e: e011 b.n 8013094 <tcp_slowtmr+0x198>
|
|
}
|
|
/* snd_wnd not fully closed, split unsent head and fill window */
|
|
} else {
|
|
if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) {
|
|
8013070: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013072: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
8013076: 4619 mov r1, r3
|
|
8013078: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
801307a: f003 fae5 bl 8016648 <tcp_split_unsent_seg>
|
|
801307e: 4603 mov r3, r0
|
|
8013080: 2b00 cmp r3, #0
|
|
8013082: d107 bne.n 8013094 <tcp_slowtmr+0x198>
|
|
if (tcp_output(pcb) == ERR_OK) {
|
|
8013084: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
8013086: f003 fd65 bl 8016b54 <tcp_output>
|
|
801308a: 4603 mov r3, r0
|
|
801308c: 2b00 cmp r3, #0
|
|
801308e: d101 bne.n 8013094 <tcp_slowtmr+0x198>
|
|
/* sending will cancel persist timer, else retry with current slot */
|
|
next_slot = 0;
|
|
8013090: 2300 movs r3, #0
|
|
8013092: 623b str r3, [r7, #32]
|
|
}
|
|
}
|
|
}
|
|
if (next_slot) {
|
|
8013094: 6a3b ldr r3, [r7, #32]
|
|
8013096: 2b00 cmp r3, #0
|
|
8013098: f000 80ac beq.w 80131f4 <tcp_slowtmr+0x2f8>
|
|
pcb->persist_cnt = 0;
|
|
801309c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801309e: 2200 movs r2, #0
|
|
80130a0: f883 2098 strb.w r2, [r3, #152] ; 0x98
|
|
if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) {
|
|
80130a4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130a6: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
|
|
80130aa: 2b06 cmp r3, #6
|
|
80130ac: f200 80a2 bhi.w 80131f4 <tcp_slowtmr+0x2f8>
|
|
pcb->persist_backoff++;
|
|
80130b0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130b2: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
|
|
80130b6: 3301 adds r3, #1
|
|
80130b8: b2da uxtb r2, r3
|
|
80130ba: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130bc: f883 2099 strb.w r2, [r3, #153] ; 0x99
|
|
80130c0: e098 b.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
/* Increase the retransmission timer if it is running */
|
|
if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) {
|
|
80130c2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130c4: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
|
|
80130c8: 2b00 cmp r3, #0
|
|
80130ca: db0f blt.n 80130ec <tcp_slowtmr+0x1f0>
|
|
80130cc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130ce: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
|
|
80130d2: f647 72ff movw r2, #32767 ; 0x7fff
|
|
80130d6: 4293 cmp r3, r2
|
|
80130d8: d008 beq.n 80130ec <tcp_slowtmr+0x1f0>
|
|
++pcb->rtime;
|
|
80130da: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130dc: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
|
|
80130e0: b29b uxth r3, r3
|
|
80130e2: 3301 adds r3, #1
|
|
80130e4: b29b uxth r3, r3
|
|
80130e6: b21a sxth r2, r3
|
|
80130e8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130ea: 861a strh r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
if (pcb->rtime >= pcb->rto) {
|
|
80130ec: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130ee: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30
|
|
80130f2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80130f4: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
|
|
80130f8: 429a cmp r2, r3
|
|
80130fa: db7b blt.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
" pcb->rto %"S16_F"\n",
|
|
pcb->rtime, pcb->rto));
|
|
/* If prepare phase fails but we have unsent data but no unacked data,
|
|
still execute the backoff calculations below, as this means we somehow
|
|
failed to send segment. */
|
|
if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) {
|
|
80130fc: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80130fe: f004 f821 bl 8017144 <tcp_rexmit_rto_prepare>
|
|
8013102: 4603 mov r3, r0
|
|
8013104: 2b00 cmp r3, #0
|
|
8013106: d007 beq.n 8013118 <tcp_slowtmr+0x21c>
|
|
8013108: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801310a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
801310c: 2b00 cmp r3, #0
|
|
801310e: d171 bne.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
8013110: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013112: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8013114: 2b00 cmp r3, #0
|
|
8013116: d06d beq.n 80131f4 <tcp_slowtmr+0x2f8>
|
|
/* Double retransmission time-out unless we are trying to
|
|
* connect to somebody (i.e., we are in SYN_SENT). */
|
|
if (pcb->state != SYN_SENT) {
|
|
8013118: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801311a: 7d1b ldrb r3, [r3, #20]
|
|
801311c: 2b02 cmp r3, #2
|
|
801311e: d03a beq.n 8013196 <tcp_slowtmr+0x29a>
|
|
u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1);
|
|
8013120: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013122: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8013126: 2b0c cmp r3, #12
|
|
8013128: bf28 it cs
|
|
801312a: 230c movcs r3, #12
|
|
801312c: 76fb strb r3, [r7, #27]
|
|
int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx];
|
|
801312e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013130: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
|
|
8013134: 10db asrs r3, r3, #3
|
|
8013136: b21b sxth r3, r3
|
|
8013138: 461a mov r2, r3
|
|
801313a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801313c: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
|
|
8013140: 4413 add r3, r2
|
|
8013142: 7efa ldrb r2, [r7, #27]
|
|
8013144: 4910 ldr r1, [pc, #64] ; (8013188 <tcp_slowtmr+0x28c>)
|
|
8013146: 5c8a ldrb r2, [r1, r2]
|
|
8013148: 4093 lsls r3, r2
|
|
801314a: 617b str r3, [r7, #20]
|
|
pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF);
|
|
801314c: 697b ldr r3, [r7, #20]
|
|
801314e: f647 72fe movw r2, #32766 ; 0x7ffe
|
|
8013152: 4293 cmp r3, r2
|
|
8013154: dc1a bgt.n 801318c <tcp_slowtmr+0x290>
|
|
8013156: 697b ldr r3, [r7, #20]
|
|
8013158: b21a sxth r2, r3
|
|
801315a: e019 b.n 8013190 <tcp_slowtmr+0x294>
|
|
801315c: 2000f800 .word 0x2000f800
|
|
8013160: 2000872a .word 0x2000872a
|
|
8013164: 2000f7fc .word 0x2000f7fc
|
|
8013168: 0801eb48 .word 0x0801eb48
|
|
801316c: 0801ee8c .word 0x0801ee8c
|
|
8013170: 0801eb8c .word 0x0801eb8c
|
|
8013174: 0801eeb8 .word 0x0801eeb8
|
|
8013178: 0801eee4 .word 0x0801eee4
|
|
801317c: 0801ef14 .word 0x0801ef14
|
|
8013180: 0801ef48 .word 0x0801ef48
|
|
8013184: 08022e28 .word 0x08022e28
|
|
8013188: 08022e18 .word 0x08022e18
|
|
801318c: f647 72ff movw r2, #32767 ; 0x7fff
|
|
8013190: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013192: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
}
|
|
|
|
/* Reset the retransmission timer. */
|
|
pcb->rtime = 0;
|
|
8013196: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013198: 2200 movs r2, #0
|
|
801319a: 861a strh r2, [r3, #48] ; 0x30
|
|
|
|
/* Reduce congestion window and ssthresh. */
|
|
eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd);
|
|
801319c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801319e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
|
|
80131a2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131a4: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
80131a8: 4293 cmp r3, r2
|
|
80131aa: bf28 it cs
|
|
80131ac: 4613 movcs r3, r2
|
|
80131ae: 827b strh r3, [r7, #18]
|
|
pcb->ssthresh = eff_wnd >> 1;
|
|
80131b0: 8a7b ldrh r3, [r7, #18]
|
|
80131b2: 085b lsrs r3, r3, #1
|
|
80131b4: b29a uxth r2, r3
|
|
80131b6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131b8: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
|
|
if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) {
|
|
80131bc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131be: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
|
|
80131c2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131c4: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
80131c6: 005b lsls r3, r3, #1
|
|
80131c8: b29b uxth r3, r3
|
|
80131ca: 429a cmp r2, r3
|
|
80131cc: d206 bcs.n 80131dc <tcp_slowtmr+0x2e0>
|
|
pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1);
|
|
80131ce: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131d0: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
80131d2: 005b lsls r3, r3, #1
|
|
80131d4: b29a uxth r2, r3
|
|
80131d6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131d8: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
|
|
}
|
|
pcb->cwnd = pcb->mss;
|
|
80131dc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131de: 8e5a ldrh r2, [r3, #50] ; 0x32
|
|
80131e0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131e2: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F
|
|
" ssthresh %"TCPWNDSIZE_F"\n",
|
|
pcb->cwnd, pcb->ssthresh));
|
|
pcb->bytes_acked = 0;
|
|
80131e6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131e8: 2200 movs r2, #0
|
|
80131ea: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
|
|
|
|
/* The following needs to be called AFTER cwnd is set to one
|
|
mss - STJ */
|
|
tcp_rexmit_rto_commit(pcb);
|
|
80131ee: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80131f0: f004 f818 bl 8017224 <tcp_rexmit_rto_commit>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Check if this PCB has stayed too long in FIN-WAIT-2 */
|
|
if (pcb->state == FIN_WAIT_2) {
|
|
80131f4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131f6: 7d1b ldrb r3, [r3, #20]
|
|
80131f8: 2b06 cmp r3, #6
|
|
80131fa: d111 bne.n 8013220 <tcp_slowtmr+0x324>
|
|
/* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */
|
|
if (pcb->flags & TF_RXCLOSED) {
|
|
80131fc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80131fe: 8b5b ldrh r3, [r3, #26]
|
|
8013200: f003 0310 and.w r3, r3, #16
|
|
8013204: 2b00 cmp r3, #0
|
|
8013206: d00b beq.n 8013220 <tcp_slowtmr+0x324>
|
|
/* PCB was fully closed (either through close() or SHUT_RDWR):
|
|
normal FIN-WAIT timeout handling. */
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
8013208: 4b9c ldr r3, [pc, #624] ; (801347c <tcp_slowtmr+0x580>)
|
|
801320a: 681a ldr r2, [r3, #0]
|
|
801320c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801320e: 6a1b ldr r3, [r3, #32]
|
|
8013210: 1ad3 subs r3, r2, r3
|
|
8013212: 2b28 cmp r3, #40 ; 0x28
|
|
8013214: d904 bls.n 8013220 <tcp_slowtmr+0x324>
|
|
TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) {
|
|
++pcb_remove;
|
|
8013216: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
801321a: 3301 adds r3, #1
|
|
801321c: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Check if KEEPALIVE should be sent */
|
|
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
|
|
8013220: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013222: 7a5b ldrb r3, [r3, #9]
|
|
8013224: f003 0308 and.w r3, r3, #8
|
|
8013228: 2b00 cmp r3, #0
|
|
801322a: d04a beq.n 80132c2 <tcp_slowtmr+0x3c6>
|
|
((pcb->state == ESTABLISHED) ||
|
|
801322c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801322e: 7d1b ldrb r3, [r3, #20]
|
|
if (ip_get_option(pcb, SOF_KEEPALIVE) &&
|
|
8013230: 2b04 cmp r3, #4
|
|
8013232: d003 beq.n 801323c <tcp_slowtmr+0x340>
|
|
(pcb->state == CLOSE_WAIT))) {
|
|
8013234: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013236: 7d1b ldrb r3, [r3, #20]
|
|
((pcb->state == ESTABLISHED) ||
|
|
8013238: 2b07 cmp r3, #7
|
|
801323a: d142 bne.n 80132c2 <tcp_slowtmr+0x3c6>
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
801323c: 4b8f ldr r3, [pc, #572] ; (801347c <tcp_slowtmr+0x580>)
|
|
801323e: 681a ldr r2, [r3, #0]
|
|
8013240: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013242: 6a1b ldr r3, [r3, #32]
|
|
8013244: 1ad2 subs r2, r2, r3
|
|
(pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) {
|
|
8013246: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013248: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
|
|
801324c: 4b8c ldr r3, [pc, #560] ; (8013480 <tcp_slowtmr+0x584>)
|
|
801324e: 440b add r3, r1
|
|
8013250: 498c ldr r1, [pc, #560] ; (8013484 <tcp_slowtmr+0x588>)
|
|
8013252: fba1 1303 umull r1, r3, r1, r3
|
|
8013256: 095b lsrs r3, r3, #5
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
8013258: 429a cmp r2, r3
|
|
801325a: d90a bls.n 8013272 <tcp_slowtmr+0x376>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to "));
|
|
ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip);
|
|
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
|
|
|
|
++pcb_remove;
|
|
801325c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8013260: 3301 adds r3, #1
|
|
8013262: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
++pcb_reset;
|
|
8013266: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
801326a: 3301 adds r3, #1
|
|
801326c: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
8013270: e027 b.n 80132c2 <tcp_slowtmr+0x3c6>
|
|
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
8013272: 4b82 ldr r3, [pc, #520] ; (801347c <tcp_slowtmr+0x580>)
|
|
8013274: 681a ldr r2, [r3, #0]
|
|
8013276: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013278: 6a1b ldr r3, [r3, #32]
|
|
801327a: 1ad2 subs r2, r2, r3
|
|
(pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb))
|
|
801327c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801327e: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94
|
|
8013282: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013284: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
|
|
8013288: 4618 mov r0, r3
|
|
801328a: 4b7f ldr r3, [pc, #508] ; (8013488 <tcp_slowtmr+0x58c>)
|
|
801328c: fb03 f300 mul.w r3, r3, r0
|
|
8013290: 440b add r3, r1
|
|
/ TCP_SLOW_INTERVAL) {
|
|
8013292: 497c ldr r1, [pc, #496] ; (8013484 <tcp_slowtmr+0x588>)
|
|
8013294: fba1 1303 umull r1, r3, r1, r3
|
|
8013298: 095b lsrs r3, r3, #5
|
|
} else if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
801329a: 429a cmp r2, r3
|
|
801329c: d911 bls.n 80132c2 <tcp_slowtmr+0x3c6>
|
|
err = tcp_keepalive(pcb);
|
|
801329e: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80132a0: f004 fad2 bl 8017848 <tcp_keepalive>
|
|
80132a4: 4603 mov r3, r0
|
|
80132a6: f887 3025 strb.w r3, [r7, #37] ; 0x25
|
|
if (err == ERR_OK) {
|
|
80132aa: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
|
|
80132ae: 2b00 cmp r3, #0
|
|
80132b0: d107 bne.n 80132c2 <tcp_slowtmr+0x3c6>
|
|
pcb->keep_cnt_sent++;
|
|
80132b2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132b4: f893 309b ldrb.w r3, [r3, #155] ; 0x9b
|
|
80132b8: 3301 adds r3, #1
|
|
80132ba: b2da uxtb r2, r3
|
|
80132bc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132be: f883 209b strb.w r2, [r3, #155] ; 0x9b
|
|
|
|
/* If this PCB has queued out of sequence data, but has been
|
|
inactive for too long, will drop the data (it will eventually
|
|
be retransmitted). */
|
|
#if TCP_QUEUE_OOSEQ
|
|
if (pcb->ooseq != NULL &&
|
|
80132c2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132c4: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
80132c6: 2b00 cmp r3, #0
|
|
80132c8: d011 beq.n 80132ee <tcp_slowtmr+0x3f2>
|
|
(tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) {
|
|
80132ca: 4b6c ldr r3, [pc, #432] ; (801347c <tcp_slowtmr+0x580>)
|
|
80132cc: 681a ldr r2, [r3, #0]
|
|
80132ce: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132d0: 6a1b ldr r3, [r3, #32]
|
|
80132d2: 1ad2 subs r2, r2, r3
|
|
80132d4: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132d6: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40
|
|
80132da: 4619 mov r1, r3
|
|
80132dc: 460b mov r3, r1
|
|
80132de: 005b lsls r3, r3, #1
|
|
80132e0: 440b add r3, r1
|
|
80132e2: 005b lsls r3, r3, #1
|
|
if (pcb->ooseq != NULL &&
|
|
80132e4: 429a cmp r2, r3
|
|
80132e6: d302 bcc.n 80132ee <tcp_slowtmr+0x3f2>
|
|
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n"));
|
|
tcp_free_ooseq(pcb);
|
|
80132e8: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80132ea: f000 fdd9 bl 8013ea0 <tcp_free_ooseq>
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
|
|
/* Check if this PCB has stayed too long in SYN-RCVD */
|
|
if (pcb->state == SYN_RCVD) {
|
|
80132ee: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132f0: 7d1b ldrb r3, [r3, #20]
|
|
80132f2: 2b03 cmp r3, #3
|
|
80132f4: d10b bne.n 801330e <tcp_slowtmr+0x412>
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >
|
|
80132f6: 4b61 ldr r3, [pc, #388] ; (801347c <tcp_slowtmr+0x580>)
|
|
80132f8: 681a ldr r2, [r3, #0]
|
|
80132fa: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80132fc: 6a1b ldr r3, [r3, #32]
|
|
80132fe: 1ad3 subs r3, r2, r3
|
|
8013300: 2b28 cmp r3, #40 ; 0x28
|
|
8013302: d904 bls.n 801330e <tcp_slowtmr+0x412>
|
|
TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) {
|
|
++pcb_remove;
|
|
8013304: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8013308: 3301 adds r3, #1
|
|
801330a: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n"));
|
|
}
|
|
}
|
|
|
|
/* Check if this PCB has stayed too long in LAST-ACK */
|
|
if (pcb->state == LAST_ACK) {
|
|
801330e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013310: 7d1b ldrb r3, [r3, #20]
|
|
8013312: 2b09 cmp r3, #9
|
|
8013314: d10b bne.n 801332e <tcp_slowtmr+0x432>
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
|
|
8013316: 4b59 ldr r3, [pc, #356] ; (801347c <tcp_slowtmr+0x580>)
|
|
8013318: 681a ldr r2, [r3, #0]
|
|
801331a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801331c: 6a1b ldr r3, [r3, #32]
|
|
801331e: 1ad3 subs r3, r2, r3
|
|
8013320: 2bf0 cmp r3, #240 ; 0xf0
|
|
8013322: d904 bls.n 801332e <tcp_slowtmr+0x432>
|
|
++pcb_remove;
|
|
8013324: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8013328: 3301 adds r3, #1
|
|
801332a: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n"));
|
|
}
|
|
}
|
|
|
|
/* If the PCB should be removed, do it. */
|
|
if (pcb_remove) {
|
|
801332e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8013332: 2b00 cmp r3, #0
|
|
8013334: d060 beq.n 80133f8 <tcp_slowtmr+0x4fc>
|
|
struct tcp_pcb *pcb2;
|
|
#if LWIP_CALLBACK_API
|
|
tcp_err_fn err_fn = pcb->errf;
|
|
8013336: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013338: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
801333c: 60fb str r3, [r7, #12]
|
|
#endif /* LWIP_CALLBACK_API */
|
|
void *err_arg;
|
|
enum tcp_state last_state;
|
|
tcp_pcb_purge(pcb);
|
|
801333e: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
8013340: f000 fbfa bl 8013b38 <tcp_pcb_purge>
|
|
/* Remove PCB from tcp_active_pcbs list. */
|
|
if (prev != NULL) {
|
|
8013344: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013346: 2b00 cmp r3, #0
|
|
8013348: d010 beq.n 801336c <tcp_slowtmr+0x470>
|
|
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs);
|
|
801334a: 4b50 ldr r3, [pc, #320] ; (801348c <tcp_slowtmr+0x590>)
|
|
801334c: 681b ldr r3, [r3, #0]
|
|
801334e: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
8013350: 429a cmp r2, r3
|
|
8013352: d106 bne.n 8013362 <tcp_slowtmr+0x466>
|
|
8013354: 4b4e ldr r3, [pc, #312] ; (8013490 <tcp_slowtmr+0x594>)
|
|
8013356: f240 526d movw r2, #1389 ; 0x56d
|
|
801335a: 494e ldr r1, [pc, #312] ; (8013494 <tcp_slowtmr+0x598>)
|
|
801335c: 484e ldr r0, [pc, #312] ; (8013498 <tcp_slowtmr+0x59c>)
|
|
801335e: f009 fcab bl 801ccb8 <iprintf>
|
|
prev->next = pcb->next;
|
|
8013362: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013364: 68da ldr r2, [r3, #12]
|
|
8013366: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013368: 60da str r2, [r3, #12]
|
|
801336a: e00f b.n 801338c <tcp_slowtmr+0x490>
|
|
} else {
|
|
/* This PCB was the first. */
|
|
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb);
|
|
801336c: 4b47 ldr r3, [pc, #284] ; (801348c <tcp_slowtmr+0x590>)
|
|
801336e: 681b ldr r3, [r3, #0]
|
|
8013370: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
8013372: 429a cmp r2, r3
|
|
8013374: d006 beq.n 8013384 <tcp_slowtmr+0x488>
|
|
8013376: 4b46 ldr r3, [pc, #280] ; (8013490 <tcp_slowtmr+0x594>)
|
|
8013378: f240 5271 movw r2, #1393 ; 0x571
|
|
801337c: 4947 ldr r1, [pc, #284] ; (801349c <tcp_slowtmr+0x5a0>)
|
|
801337e: 4846 ldr r0, [pc, #280] ; (8013498 <tcp_slowtmr+0x59c>)
|
|
8013380: f009 fc9a bl 801ccb8 <iprintf>
|
|
tcp_active_pcbs = pcb->next;
|
|
8013384: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013386: 68db ldr r3, [r3, #12]
|
|
8013388: 4a40 ldr r2, [pc, #256] ; (801348c <tcp_slowtmr+0x590>)
|
|
801338a: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
if (pcb_reset) {
|
|
801338c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8013390: 2b00 cmp r3, #0
|
|
8013392: d013 beq.n 80133bc <tcp_slowtmr+0x4c0>
|
|
tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip,
|
|
8013394: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013396: 6d18 ldr r0, [r3, #80] ; 0x50
|
|
8013398: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801339a: 6a5c ldr r4, [r3, #36] ; 0x24
|
|
801339c: 6afd ldr r5, [r7, #44] ; 0x2c
|
|
801339e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133a0: 3304 adds r3, #4
|
|
80133a2: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
80133a4: 8ad2 ldrh r2, [r2, #22]
|
|
80133a6: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
80133a8: 8b09 ldrh r1, [r1, #24]
|
|
80133aa: 9102 str r1, [sp, #8]
|
|
80133ac: 9201 str r2, [sp, #4]
|
|
80133ae: 9300 str r3, [sp, #0]
|
|
80133b0: 462b mov r3, r5
|
|
80133b2: 4622 mov r2, r4
|
|
80133b4: 4601 mov r1, r0
|
|
80133b6: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80133b8: f004 f992 bl 80176e0 <tcp_rst>
|
|
pcb->local_port, pcb->remote_port);
|
|
}
|
|
|
|
err_arg = pcb->callback_arg;
|
|
80133bc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133be: 691b ldr r3, [r3, #16]
|
|
80133c0: 60bb str r3, [r7, #8]
|
|
last_state = pcb->state;
|
|
80133c2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133c4: 7d1b ldrb r3, [r3, #20]
|
|
80133c6: 71fb strb r3, [r7, #7]
|
|
pcb2 = pcb;
|
|
80133c8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133ca: 603b str r3, [r7, #0]
|
|
pcb = pcb->next;
|
|
80133cc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133ce: 68db ldr r3, [r3, #12]
|
|
80133d0: 62fb str r3, [r7, #44] ; 0x2c
|
|
tcp_free(pcb2);
|
|
80133d2: 6838 ldr r0, [r7, #0]
|
|
80133d4: f7ff f9fc bl 80127d0 <tcp_free>
|
|
|
|
tcp_active_pcbs_changed = 0;
|
|
80133d8: 4b31 ldr r3, [pc, #196] ; (80134a0 <tcp_slowtmr+0x5a4>)
|
|
80133da: 2200 movs r2, #0
|
|
80133dc: 701a strb r2, [r3, #0]
|
|
TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT);
|
|
80133de: 68fb ldr r3, [r7, #12]
|
|
80133e0: 2b00 cmp r3, #0
|
|
80133e2: d004 beq.n 80133ee <tcp_slowtmr+0x4f2>
|
|
80133e4: 68fb ldr r3, [r7, #12]
|
|
80133e6: f06f 010c mvn.w r1, #12
|
|
80133ea: 68b8 ldr r0, [r7, #8]
|
|
80133ec: 4798 blx r3
|
|
if (tcp_active_pcbs_changed) {
|
|
80133ee: 4b2c ldr r3, [pc, #176] ; (80134a0 <tcp_slowtmr+0x5a4>)
|
|
80133f0: 781b ldrb r3, [r3, #0]
|
|
80133f2: 2b00 cmp r3, #0
|
|
80133f4: d037 beq.n 8013466 <tcp_slowtmr+0x56a>
|
|
goto tcp_slowtmr_start;
|
|
80133f6: e592 b.n 8012f1e <tcp_slowtmr+0x22>
|
|
}
|
|
} else {
|
|
/* get the 'next' element now and work with 'prev' below (in case of abort) */
|
|
prev = pcb;
|
|
80133f8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133fa: 62bb str r3, [r7, #40] ; 0x28
|
|
pcb = pcb->next;
|
|
80133fc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80133fe: 68db ldr r3, [r3, #12]
|
|
8013400: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
|
/* We check if we should poll the connection. */
|
|
++prev->polltmr;
|
|
8013402: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013404: 7f1b ldrb r3, [r3, #28]
|
|
8013406: 3301 adds r3, #1
|
|
8013408: b2da uxtb r2, r3
|
|
801340a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801340c: 771a strb r2, [r3, #28]
|
|
if (prev->polltmr >= prev->pollinterval) {
|
|
801340e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013410: 7f1a ldrb r2, [r3, #28]
|
|
8013412: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013414: 7f5b ldrb r3, [r3, #29]
|
|
8013416: 429a cmp r2, r3
|
|
8013418: d325 bcc.n 8013466 <tcp_slowtmr+0x56a>
|
|
prev->polltmr = 0;
|
|
801341a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801341c: 2200 movs r2, #0
|
|
801341e: 771a strb r2, [r3, #28]
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n"));
|
|
tcp_active_pcbs_changed = 0;
|
|
8013420: 4b1f ldr r3, [pc, #124] ; (80134a0 <tcp_slowtmr+0x5a4>)
|
|
8013422: 2200 movs r2, #0
|
|
8013424: 701a strb r2, [r3, #0]
|
|
TCP_EVENT_POLL(prev, err);
|
|
8013426: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013428: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
801342c: 2b00 cmp r3, #0
|
|
801342e: d00b beq.n 8013448 <tcp_slowtmr+0x54c>
|
|
8013430: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8013432: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
|
|
8013436: 6aba ldr r2, [r7, #40] ; 0x28
|
|
8013438: 6912 ldr r2, [r2, #16]
|
|
801343a: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
801343c: 4610 mov r0, r2
|
|
801343e: 4798 blx r3
|
|
8013440: 4603 mov r3, r0
|
|
8013442: f887 3025 strb.w r3, [r7, #37] ; 0x25
|
|
8013446: e002 b.n 801344e <tcp_slowtmr+0x552>
|
|
8013448: 2300 movs r3, #0
|
|
801344a: f887 3025 strb.w r3, [r7, #37] ; 0x25
|
|
if (tcp_active_pcbs_changed) {
|
|
801344e: 4b14 ldr r3, [pc, #80] ; (80134a0 <tcp_slowtmr+0x5a4>)
|
|
8013450: 781b ldrb r3, [r3, #0]
|
|
8013452: 2b00 cmp r3, #0
|
|
8013454: d000 beq.n 8013458 <tcp_slowtmr+0x55c>
|
|
goto tcp_slowtmr_start;
|
|
8013456: e562 b.n 8012f1e <tcp_slowtmr+0x22>
|
|
}
|
|
/* if err == ERR_ABRT, 'prev' is already deallocated */
|
|
if (err == ERR_OK) {
|
|
8013458: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25
|
|
801345c: 2b00 cmp r3, #0
|
|
801345e: d102 bne.n 8013466 <tcp_slowtmr+0x56a>
|
|
tcp_output(prev);
|
|
8013460: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
8013462: f003 fb77 bl 8016b54 <tcp_output>
|
|
while (pcb != NULL) {
|
|
8013466: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013468: 2b00 cmp r3, #0
|
|
801346a: f47f ad5e bne.w 8012f2a <tcp_slowtmr+0x2e>
|
|
}
|
|
}
|
|
|
|
|
|
/* Steps through all of the TIME-WAIT PCBs. */
|
|
prev = NULL;
|
|
801346e: 2300 movs r3, #0
|
|
8013470: 62bb str r3, [r7, #40] ; 0x28
|
|
pcb = tcp_tw_pcbs;
|
|
8013472: 4b0c ldr r3, [pc, #48] ; (80134a4 <tcp_slowtmr+0x5a8>)
|
|
8013474: 681b ldr r3, [r3, #0]
|
|
8013476: 62fb str r3, [r7, #44] ; 0x2c
|
|
while (pcb != NULL) {
|
|
8013478: e069 b.n 801354e <tcp_slowtmr+0x652>
|
|
801347a: bf00 nop
|
|
801347c: 2000f800 .word 0x2000f800
|
|
8013480: 000a4cb8 .word 0x000a4cb8
|
|
8013484: 10624dd3 .word 0x10624dd3
|
|
8013488: 000124f8 .word 0x000124f8
|
|
801348c: 2000f7fc .word 0x2000f7fc
|
|
8013490: 0801eb48 .word 0x0801eb48
|
|
8013494: 0801ef80 .word 0x0801ef80
|
|
8013498: 0801eb8c .word 0x0801eb8c
|
|
801349c: 0801efac .word 0x0801efac
|
|
80134a0: 2000f7f8 .word 0x2000f7f8
|
|
80134a4: 2000f80c .word 0x2000f80c
|
|
LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
|
|
80134a8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80134aa: 7d1b ldrb r3, [r3, #20]
|
|
80134ac: 2b0a cmp r3, #10
|
|
80134ae: d006 beq.n 80134be <tcp_slowtmr+0x5c2>
|
|
80134b0: 4b2a ldr r3, [pc, #168] ; (801355c <tcp_slowtmr+0x660>)
|
|
80134b2: f240 52a1 movw r2, #1441 ; 0x5a1
|
|
80134b6: 492a ldr r1, [pc, #168] ; (8013560 <tcp_slowtmr+0x664>)
|
|
80134b8: 482a ldr r0, [pc, #168] ; (8013564 <tcp_slowtmr+0x668>)
|
|
80134ba: f009 fbfd bl 801ccb8 <iprintf>
|
|
pcb_remove = 0;
|
|
80134be: 2300 movs r3, #0
|
|
80134c0: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
/* Check if this PCB has stayed long enough in TIME-WAIT */
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) {
|
|
80134c4: 4b28 ldr r3, [pc, #160] ; (8013568 <tcp_slowtmr+0x66c>)
|
|
80134c6: 681a ldr r2, [r3, #0]
|
|
80134c8: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
80134ca: 6a1b ldr r3, [r3, #32]
|
|
80134cc: 1ad3 subs r3, r2, r3
|
|
80134ce: 2bf0 cmp r3, #240 ; 0xf0
|
|
80134d0: d904 bls.n 80134dc <tcp_slowtmr+0x5e0>
|
|
++pcb_remove;
|
|
80134d2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
80134d6: 3301 adds r3, #1
|
|
80134d8: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
|
|
/* If the PCB should be removed, do it. */
|
|
if (pcb_remove) {
|
|
80134dc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
80134e0: 2b00 cmp r3, #0
|
|
80134e2: d02f beq.n 8013544 <tcp_slowtmr+0x648>
|
|
struct tcp_pcb *pcb2;
|
|
tcp_pcb_purge(pcb);
|
|
80134e4: 6af8 ldr r0, [r7, #44] ; 0x2c
|
|
80134e6: f000 fb27 bl 8013b38 <tcp_pcb_purge>
|
|
/* Remove PCB from tcp_tw_pcbs list. */
|
|
if (prev != NULL) {
|
|
80134ea: 6abb ldr r3, [r7, #40] ; 0x28
|
|
80134ec: 2b00 cmp r3, #0
|
|
80134ee: d010 beq.n 8013512 <tcp_slowtmr+0x616>
|
|
LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs);
|
|
80134f0: 4b1e ldr r3, [pc, #120] ; (801356c <tcp_slowtmr+0x670>)
|
|
80134f2: 681b ldr r3, [r3, #0]
|
|
80134f4: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
80134f6: 429a cmp r2, r3
|
|
80134f8: d106 bne.n 8013508 <tcp_slowtmr+0x60c>
|
|
80134fa: 4b18 ldr r3, [pc, #96] ; (801355c <tcp_slowtmr+0x660>)
|
|
80134fc: f240 52af movw r2, #1455 ; 0x5af
|
|
8013500: 491b ldr r1, [pc, #108] ; (8013570 <tcp_slowtmr+0x674>)
|
|
8013502: 4818 ldr r0, [pc, #96] ; (8013564 <tcp_slowtmr+0x668>)
|
|
8013504: f009 fbd8 bl 801ccb8 <iprintf>
|
|
prev->next = pcb->next;
|
|
8013508: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801350a: 68da ldr r2, [r3, #12]
|
|
801350c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801350e: 60da str r2, [r3, #12]
|
|
8013510: e00f b.n 8013532 <tcp_slowtmr+0x636>
|
|
} else {
|
|
/* This PCB was the first. */
|
|
LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb);
|
|
8013512: 4b16 ldr r3, [pc, #88] ; (801356c <tcp_slowtmr+0x670>)
|
|
8013514: 681b ldr r3, [r3, #0]
|
|
8013516: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
8013518: 429a cmp r2, r3
|
|
801351a: d006 beq.n 801352a <tcp_slowtmr+0x62e>
|
|
801351c: 4b0f ldr r3, [pc, #60] ; (801355c <tcp_slowtmr+0x660>)
|
|
801351e: f240 52b3 movw r2, #1459 ; 0x5b3
|
|
8013522: 4914 ldr r1, [pc, #80] ; (8013574 <tcp_slowtmr+0x678>)
|
|
8013524: 480f ldr r0, [pc, #60] ; (8013564 <tcp_slowtmr+0x668>)
|
|
8013526: f009 fbc7 bl 801ccb8 <iprintf>
|
|
tcp_tw_pcbs = pcb->next;
|
|
801352a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801352c: 68db ldr r3, [r3, #12]
|
|
801352e: 4a0f ldr r2, [pc, #60] ; (801356c <tcp_slowtmr+0x670>)
|
|
8013530: 6013 str r3, [r2, #0]
|
|
}
|
|
pcb2 = pcb;
|
|
8013532: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013534: 61fb str r3, [r7, #28]
|
|
pcb = pcb->next;
|
|
8013536: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013538: 68db ldr r3, [r3, #12]
|
|
801353a: 62fb str r3, [r7, #44] ; 0x2c
|
|
tcp_free(pcb2);
|
|
801353c: 69f8 ldr r0, [r7, #28]
|
|
801353e: f7ff f947 bl 80127d0 <tcp_free>
|
|
8013542: e004 b.n 801354e <tcp_slowtmr+0x652>
|
|
} else {
|
|
prev = pcb;
|
|
8013544: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013546: 62bb str r3, [r7, #40] ; 0x28
|
|
pcb = pcb->next;
|
|
8013548: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801354a: 68db ldr r3, [r3, #12]
|
|
801354c: 62fb str r3, [r7, #44] ; 0x2c
|
|
while (pcb != NULL) {
|
|
801354e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8013550: 2b00 cmp r3, #0
|
|
8013552: d1a9 bne.n 80134a8 <tcp_slowtmr+0x5ac>
|
|
}
|
|
}
|
|
}
|
|
8013554: bf00 nop
|
|
8013556: 3730 adds r7, #48 ; 0x30
|
|
8013558: 46bd mov sp, r7
|
|
801355a: bdb0 pop {r4, r5, r7, pc}
|
|
801355c: 0801eb48 .word 0x0801eb48
|
|
8013560: 0801efd8 .word 0x0801efd8
|
|
8013564: 0801eb8c .word 0x0801eb8c
|
|
8013568: 2000f800 .word 0x2000f800
|
|
801356c: 2000f80c .word 0x2000f80c
|
|
8013570: 0801f008 .word 0x0801f008
|
|
8013574: 0801f030 .word 0x0801f030
|
|
|
|
08013578 <tcp_fasttmr>:
|
|
*
|
|
* Automatically called from tcp_tmr().
|
|
*/
|
|
void
|
|
tcp_fasttmr(void)
|
|
{
|
|
8013578: b580 push {r7, lr}
|
|
801357a: b082 sub sp, #8
|
|
801357c: af00 add r7, sp, #0
|
|
struct tcp_pcb *pcb;
|
|
|
|
++tcp_timer_ctr;
|
|
801357e: 4b2d ldr r3, [pc, #180] ; (8013634 <tcp_fasttmr+0xbc>)
|
|
8013580: 781b ldrb r3, [r3, #0]
|
|
8013582: 3301 adds r3, #1
|
|
8013584: b2da uxtb r2, r3
|
|
8013586: 4b2b ldr r3, [pc, #172] ; (8013634 <tcp_fasttmr+0xbc>)
|
|
8013588: 701a strb r2, [r3, #0]
|
|
|
|
tcp_fasttmr_start:
|
|
pcb = tcp_active_pcbs;
|
|
801358a: 4b2b ldr r3, [pc, #172] ; (8013638 <tcp_fasttmr+0xc0>)
|
|
801358c: 681b ldr r3, [r3, #0]
|
|
801358e: 607b str r3, [r7, #4]
|
|
|
|
while (pcb != NULL) {
|
|
8013590: e048 b.n 8013624 <tcp_fasttmr+0xac>
|
|
if (pcb->last_timer != tcp_timer_ctr) {
|
|
8013592: 687b ldr r3, [r7, #4]
|
|
8013594: 7f9a ldrb r2, [r3, #30]
|
|
8013596: 4b27 ldr r3, [pc, #156] ; (8013634 <tcp_fasttmr+0xbc>)
|
|
8013598: 781b ldrb r3, [r3, #0]
|
|
801359a: 429a cmp r2, r3
|
|
801359c: d03f beq.n 801361e <tcp_fasttmr+0xa6>
|
|
struct tcp_pcb *next;
|
|
pcb->last_timer = tcp_timer_ctr;
|
|
801359e: 4b25 ldr r3, [pc, #148] ; (8013634 <tcp_fasttmr+0xbc>)
|
|
80135a0: 781a ldrb r2, [r3, #0]
|
|
80135a2: 687b ldr r3, [r7, #4]
|
|
80135a4: 779a strb r2, [r3, #30]
|
|
/* send delayed ACKs */
|
|
if (pcb->flags & TF_ACK_DELAY) {
|
|
80135a6: 687b ldr r3, [r7, #4]
|
|
80135a8: 8b5b ldrh r3, [r3, #26]
|
|
80135aa: f003 0301 and.w r3, r3, #1
|
|
80135ae: 2b00 cmp r3, #0
|
|
80135b0: d010 beq.n 80135d4 <tcp_fasttmr+0x5c>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n"));
|
|
tcp_ack_now(pcb);
|
|
80135b2: 687b ldr r3, [r7, #4]
|
|
80135b4: 8b5b ldrh r3, [r3, #26]
|
|
80135b6: f043 0302 orr.w r3, r3, #2
|
|
80135ba: b29a uxth r2, r3
|
|
80135bc: 687b ldr r3, [r7, #4]
|
|
80135be: 835a strh r2, [r3, #26]
|
|
tcp_output(pcb);
|
|
80135c0: 6878 ldr r0, [r7, #4]
|
|
80135c2: f003 fac7 bl 8016b54 <tcp_output>
|
|
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
|
|
80135c6: 687b ldr r3, [r7, #4]
|
|
80135c8: 8b5b ldrh r3, [r3, #26]
|
|
80135ca: f023 0303 bic.w r3, r3, #3
|
|
80135ce: b29a uxth r2, r3
|
|
80135d0: 687b ldr r3, [r7, #4]
|
|
80135d2: 835a strh r2, [r3, #26]
|
|
}
|
|
/* send pending FIN */
|
|
if (pcb->flags & TF_CLOSEPEND) {
|
|
80135d4: 687b ldr r3, [r7, #4]
|
|
80135d6: 8b5b ldrh r3, [r3, #26]
|
|
80135d8: f003 0308 and.w r3, r3, #8
|
|
80135dc: 2b00 cmp r3, #0
|
|
80135de: d009 beq.n 80135f4 <tcp_fasttmr+0x7c>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n"));
|
|
tcp_clear_flags(pcb, TF_CLOSEPEND);
|
|
80135e0: 687b ldr r3, [r7, #4]
|
|
80135e2: 8b5b ldrh r3, [r3, #26]
|
|
80135e4: f023 0308 bic.w r3, r3, #8
|
|
80135e8: b29a uxth r2, r3
|
|
80135ea: 687b ldr r3, [r7, #4]
|
|
80135ec: 835a strh r2, [r3, #26]
|
|
tcp_close_shutdown_fin(pcb);
|
|
80135ee: 6878 ldr r0, [r7, #4]
|
|
80135f0: f7ff fa7e bl 8012af0 <tcp_close_shutdown_fin>
|
|
}
|
|
|
|
next = pcb->next;
|
|
80135f4: 687b ldr r3, [r7, #4]
|
|
80135f6: 68db ldr r3, [r3, #12]
|
|
80135f8: 603b str r3, [r7, #0]
|
|
|
|
/* If there is data which was previously "refused" by upper layer */
|
|
if (pcb->refused_data != NULL) {
|
|
80135fa: 687b ldr r3, [r7, #4]
|
|
80135fc: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
80135fe: 2b00 cmp r3, #0
|
|
8013600: d00a beq.n 8013618 <tcp_fasttmr+0xa0>
|
|
tcp_active_pcbs_changed = 0;
|
|
8013602: 4b0e ldr r3, [pc, #56] ; (801363c <tcp_fasttmr+0xc4>)
|
|
8013604: 2200 movs r2, #0
|
|
8013606: 701a strb r2, [r3, #0]
|
|
tcp_process_refused_data(pcb);
|
|
8013608: 6878 ldr r0, [r7, #4]
|
|
801360a: f000 f819 bl 8013640 <tcp_process_refused_data>
|
|
if (tcp_active_pcbs_changed) {
|
|
801360e: 4b0b ldr r3, [pc, #44] ; (801363c <tcp_fasttmr+0xc4>)
|
|
8013610: 781b ldrb r3, [r3, #0]
|
|
8013612: 2b00 cmp r3, #0
|
|
8013614: d000 beq.n 8013618 <tcp_fasttmr+0xa0>
|
|
/* application callback has changed the pcb list: restart the loop */
|
|
goto tcp_fasttmr_start;
|
|
8013616: e7b8 b.n 801358a <tcp_fasttmr+0x12>
|
|
}
|
|
}
|
|
pcb = next;
|
|
8013618: 683b ldr r3, [r7, #0]
|
|
801361a: 607b str r3, [r7, #4]
|
|
801361c: e002 b.n 8013624 <tcp_fasttmr+0xac>
|
|
} else {
|
|
pcb = pcb->next;
|
|
801361e: 687b ldr r3, [r7, #4]
|
|
8013620: 68db ldr r3, [r3, #12]
|
|
8013622: 607b str r3, [r7, #4]
|
|
while (pcb != NULL) {
|
|
8013624: 687b ldr r3, [r7, #4]
|
|
8013626: 2b00 cmp r3, #0
|
|
8013628: d1b3 bne.n 8013592 <tcp_fasttmr+0x1a>
|
|
}
|
|
}
|
|
}
|
|
801362a: bf00 nop
|
|
801362c: 3708 adds r7, #8
|
|
801362e: 46bd mov sp, r7
|
|
8013630: bd80 pop {r7, pc}
|
|
8013632: bf00 nop
|
|
8013634: 2000872a .word 0x2000872a
|
|
8013638: 2000f7fc .word 0x2000f7fc
|
|
801363c: 2000f7f8 .word 0x2000f7f8
|
|
|
|
08013640 <tcp_process_refused_data>:
|
|
}
|
|
|
|
/** Pass pcb->refused_data to the recv callback */
|
|
err_t
|
|
tcp_process_refused_data(struct tcp_pcb *pcb)
|
|
{
|
|
8013640: b590 push {r4, r7, lr}
|
|
8013642: b085 sub sp, #20
|
|
8013644: af00 add r7, sp, #0
|
|
8013646: 6078 str r0, [r7, #4]
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
struct pbuf *rest;
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
|
|
LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
8013648: 687b ldr r3, [r7, #4]
|
|
801364a: 2b00 cmp r3, #0
|
|
801364c: d109 bne.n 8013662 <tcp_process_refused_data+0x22>
|
|
801364e: 4b37 ldr r3, [pc, #220] ; (801372c <tcp_process_refused_data+0xec>)
|
|
8013650: f240 6209 movw r2, #1545 ; 0x609
|
|
8013654: 4936 ldr r1, [pc, #216] ; (8013730 <tcp_process_refused_data+0xf0>)
|
|
8013656: 4837 ldr r0, [pc, #220] ; (8013734 <tcp_process_refused_data+0xf4>)
|
|
8013658: f009 fb2e bl 801ccb8 <iprintf>
|
|
801365c: f06f 030f mvn.w r3, #15
|
|
8013660: e060 b.n 8013724 <tcp_process_refused_data+0xe4>
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
while (pcb->refused_data != NULL)
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
{
|
|
err_t err;
|
|
u8_t refused_flags = pcb->refused_data->flags;
|
|
8013662: 687b ldr r3, [r7, #4]
|
|
8013664: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8013666: 7b5b ldrb r3, [r3, #13]
|
|
8013668: 73bb strb r3, [r7, #14]
|
|
/* set pcb->refused_data to NULL in case the callback frees it and then
|
|
closes the pcb */
|
|
struct pbuf *refused_data = pcb->refused_data;
|
|
801366a: 687b ldr r3, [r7, #4]
|
|
801366c: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
801366e: 60bb str r3, [r7, #8]
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
pbuf_split_64k(refused_data, &rest);
|
|
pcb->refused_data = rest;
|
|
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
pcb->refused_data = NULL;
|
|
8013670: 687b ldr r3, [r7, #4]
|
|
8013672: 2200 movs r2, #0
|
|
8013674: 679a str r2, [r3, #120] ; 0x78
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
/* Notify again application with data previously received. */
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n"));
|
|
TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err);
|
|
8013676: 687b ldr r3, [r7, #4]
|
|
8013678: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
801367c: 2b00 cmp r3, #0
|
|
801367e: d00b beq.n 8013698 <tcp_process_refused_data+0x58>
|
|
8013680: 687b ldr r3, [r7, #4]
|
|
8013682: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
|
|
8013686: 687b ldr r3, [r7, #4]
|
|
8013688: 6918 ldr r0, [r3, #16]
|
|
801368a: 2300 movs r3, #0
|
|
801368c: 68ba ldr r2, [r7, #8]
|
|
801368e: 6879 ldr r1, [r7, #4]
|
|
8013690: 47a0 blx r4
|
|
8013692: 4603 mov r3, r0
|
|
8013694: 73fb strb r3, [r7, #15]
|
|
8013696: e007 b.n 80136a8 <tcp_process_refused_data+0x68>
|
|
8013698: 2300 movs r3, #0
|
|
801369a: 68ba ldr r2, [r7, #8]
|
|
801369c: 6879 ldr r1, [r7, #4]
|
|
801369e: 2000 movs r0, #0
|
|
80136a0: f000 f8a2 bl 80137e8 <tcp_recv_null>
|
|
80136a4: 4603 mov r3, r0
|
|
80136a6: 73fb strb r3, [r7, #15]
|
|
if (err == ERR_OK) {
|
|
80136a8: f997 300f ldrsb.w r3, [r7, #15]
|
|
80136ac: 2b00 cmp r3, #0
|
|
80136ae: d12a bne.n 8013706 <tcp_process_refused_data+0xc6>
|
|
/* did refused_data include a FIN? */
|
|
if ((refused_flags & PBUF_FLAG_TCP_FIN)
|
|
80136b0: 7bbb ldrb r3, [r7, #14]
|
|
80136b2: f003 0320 and.w r3, r3, #32
|
|
80136b6: 2b00 cmp r3, #0
|
|
80136b8: d033 beq.n 8013722 <tcp_process_refused_data+0xe2>
|
|
&& (rest == NULL)
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
) {
|
|
/* correct rcv_wnd as the application won't call tcp_recved()
|
|
for the FIN's seqno */
|
|
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
|
|
80136ba: 687b ldr r3, [r7, #4]
|
|
80136bc: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80136be: f5b3 6f06 cmp.w r3, #2144 ; 0x860
|
|
80136c2: d005 beq.n 80136d0 <tcp_process_refused_data+0x90>
|
|
pcb->rcv_wnd++;
|
|
80136c4: 687b ldr r3, [r7, #4]
|
|
80136c6: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80136c8: 3301 adds r3, #1
|
|
80136ca: b29a uxth r2, r3
|
|
80136cc: 687b ldr r3, [r7, #4]
|
|
80136ce: 851a strh r2, [r3, #40] ; 0x28
|
|
}
|
|
TCP_EVENT_CLOSED(pcb, err);
|
|
80136d0: 687b ldr r3, [r7, #4]
|
|
80136d2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
80136d6: 2b00 cmp r3, #0
|
|
80136d8: d00b beq.n 80136f2 <tcp_process_refused_data+0xb2>
|
|
80136da: 687b ldr r3, [r7, #4]
|
|
80136dc: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
|
|
80136e0: 687b ldr r3, [r7, #4]
|
|
80136e2: 6918 ldr r0, [r3, #16]
|
|
80136e4: 2300 movs r3, #0
|
|
80136e6: 2200 movs r2, #0
|
|
80136e8: 6879 ldr r1, [r7, #4]
|
|
80136ea: 47a0 blx r4
|
|
80136ec: 4603 mov r3, r0
|
|
80136ee: 73fb strb r3, [r7, #15]
|
|
80136f0: e001 b.n 80136f6 <tcp_process_refused_data+0xb6>
|
|
80136f2: 2300 movs r3, #0
|
|
80136f4: 73fb strb r3, [r7, #15]
|
|
if (err == ERR_ABRT) {
|
|
80136f6: f997 300f ldrsb.w r3, [r7, #15]
|
|
80136fa: f113 0f0d cmn.w r3, #13
|
|
80136fe: d110 bne.n 8013722 <tcp_process_refused_data+0xe2>
|
|
return ERR_ABRT;
|
|
8013700: f06f 030c mvn.w r3, #12
|
|
8013704: e00e b.n 8013724 <tcp_process_refused_data+0xe4>
|
|
}
|
|
}
|
|
} else if (err == ERR_ABRT) {
|
|
8013706: f997 300f ldrsb.w r3, [r7, #15]
|
|
801370a: f113 0f0d cmn.w r3, #13
|
|
801370e: d102 bne.n 8013716 <tcp_process_refused_data+0xd6>
|
|
/* if err == ERR_ABRT, 'pcb' is already deallocated */
|
|
/* Drop incoming packets because pcb is "full" (only if the incoming
|
|
segment contains data). */
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n"));
|
|
return ERR_ABRT;
|
|
8013710: f06f 030c mvn.w r3, #12
|
|
8013714: e006 b.n 8013724 <tcp_process_refused_data+0xe4>
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
if (rest != NULL) {
|
|
pbuf_cat(refused_data, rest);
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
pcb->refused_data = refused_data;
|
|
8013716: 687b ldr r3, [r7, #4]
|
|
8013718: 68ba ldr r2, [r7, #8]
|
|
801371a: 679a str r2, [r3, #120] ; 0x78
|
|
return ERR_INPROGRESS;
|
|
801371c: f06f 0304 mvn.w r3, #4
|
|
8013720: e000 b.n 8013724 <tcp_process_refused_data+0xe4>
|
|
}
|
|
}
|
|
return ERR_OK;
|
|
8013722: 2300 movs r3, #0
|
|
}
|
|
8013724: 4618 mov r0, r3
|
|
8013726: 3714 adds r7, #20
|
|
8013728: 46bd mov sp, r7
|
|
801372a: bd90 pop {r4, r7, pc}
|
|
801372c: 0801eb48 .word 0x0801eb48
|
|
8013730: 0801f058 .word 0x0801f058
|
|
8013734: 0801eb8c .word 0x0801eb8c
|
|
|
|
08013738 <tcp_segs_free>:
|
|
*
|
|
* @param seg tcp_seg list of TCP segments to free
|
|
*/
|
|
void
|
|
tcp_segs_free(struct tcp_seg *seg)
|
|
{
|
|
8013738: b580 push {r7, lr}
|
|
801373a: b084 sub sp, #16
|
|
801373c: af00 add r7, sp, #0
|
|
801373e: 6078 str r0, [r7, #4]
|
|
while (seg != NULL) {
|
|
8013740: e007 b.n 8013752 <tcp_segs_free+0x1a>
|
|
struct tcp_seg *next = seg->next;
|
|
8013742: 687b ldr r3, [r7, #4]
|
|
8013744: 681b ldr r3, [r3, #0]
|
|
8013746: 60fb str r3, [r7, #12]
|
|
tcp_seg_free(seg);
|
|
8013748: 6878 ldr r0, [r7, #4]
|
|
801374a: f000 f809 bl 8013760 <tcp_seg_free>
|
|
seg = next;
|
|
801374e: 68fb ldr r3, [r7, #12]
|
|
8013750: 607b str r3, [r7, #4]
|
|
while (seg != NULL) {
|
|
8013752: 687b ldr r3, [r7, #4]
|
|
8013754: 2b00 cmp r3, #0
|
|
8013756: d1f4 bne.n 8013742 <tcp_segs_free+0xa>
|
|
}
|
|
}
|
|
8013758: bf00 nop
|
|
801375a: 3710 adds r7, #16
|
|
801375c: 46bd mov sp, r7
|
|
801375e: bd80 pop {r7, pc}
|
|
|
|
08013760 <tcp_seg_free>:
|
|
*
|
|
* @param seg single tcp_seg to free
|
|
*/
|
|
void
|
|
tcp_seg_free(struct tcp_seg *seg)
|
|
{
|
|
8013760: b580 push {r7, lr}
|
|
8013762: b082 sub sp, #8
|
|
8013764: af00 add r7, sp, #0
|
|
8013766: 6078 str r0, [r7, #4]
|
|
if (seg != NULL) {
|
|
8013768: 687b ldr r3, [r7, #4]
|
|
801376a: 2b00 cmp r3, #0
|
|
801376c: d00c beq.n 8013788 <tcp_seg_free+0x28>
|
|
if (seg->p != NULL) {
|
|
801376e: 687b ldr r3, [r7, #4]
|
|
8013770: 685b ldr r3, [r3, #4]
|
|
8013772: 2b00 cmp r3, #0
|
|
8013774: d004 beq.n 8013780 <tcp_seg_free+0x20>
|
|
pbuf_free(seg->p);
|
|
8013776: 687b ldr r3, [r7, #4]
|
|
8013778: 685b ldr r3, [r3, #4]
|
|
801377a: 4618 mov r0, r3
|
|
801377c: f7fe fd6c bl 8012258 <pbuf_free>
|
|
#if TCP_DEBUG
|
|
seg->p = NULL;
|
|
#endif /* TCP_DEBUG */
|
|
}
|
|
memp_free(MEMP_TCP_SEG, seg);
|
|
8013780: 6879 ldr r1, [r7, #4]
|
|
8013782: 2003 movs r0, #3
|
|
8013784: f7fd febc bl 8011500 <memp_free>
|
|
}
|
|
}
|
|
8013788: bf00 nop
|
|
801378a: 3708 adds r7, #8
|
|
801378c: 46bd mov sp, r7
|
|
801378e: bd80 pop {r7, pc}
|
|
|
|
08013790 <tcp_seg_copy>:
|
|
* @param seg the old tcp_seg
|
|
* @return a copy of seg
|
|
*/
|
|
struct tcp_seg *
|
|
tcp_seg_copy(struct tcp_seg *seg)
|
|
{
|
|
8013790: b580 push {r7, lr}
|
|
8013792: b084 sub sp, #16
|
|
8013794: af00 add r7, sp, #0
|
|
8013796: 6078 str r0, [r7, #4]
|
|
struct tcp_seg *cseg;
|
|
|
|
LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL);
|
|
8013798: 687b ldr r3, [r7, #4]
|
|
801379a: 2b00 cmp r3, #0
|
|
801379c: d106 bne.n 80137ac <tcp_seg_copy+0x1c>
|
|
801379e: 4b0f ldr r3, [pc, #60] ; (80137dc <tcp_seg_copy+0x4c>)
|
|
80137a0: f240 6282 movw r2, #1666 ; 0x682
|
|
80137a4: 490e ldr r1, [pc, #56] ; (80137e0 <tcp_seg_copy+0x50>)
|
|
80137a6: 480f ldr r0, [pc, #60] ; (80137e4 <tcp_seg_copy+0x54>)
|
|
80137a8: f009 fa86 bl 801ccb8 <iprintf>
|
|
|
|
cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG);
|
|
80137ac: 2003 movs r0, #3
|
|
80137ae: f7fd fe55 bl 801145c <memp_malloc>
|
|
80137b2: 60f8 str r0, [r7, #12]
|
|
if (cseg == NULL) {
|
|
80137b4: 68fb ldr r3, [r7, #12]
|
|
80137b6: 2b00 cmp r3, #0
|
|
80137b8: d101 bne.n 80137be <tcp_seg_copy+0x2e>
|
|
return NULL;
|
|
80137ba: 2300 movs r3, #0
|
|
80137bc: e00a b.n 80137d4 <tcp_seg_copy+0x44>
|
|
}
|
|
SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg));
|
|
80137be: 2210 movs r2, #16
|
|
80137c0: 6879 ldr r1, [r7, #4]
|
|
80137c2: 68f8 ldr r0, [r7, #12]
|
|
80137c4: f009 fa4b bl 801cc5e <memcpy>
|
|
pbuf_ref(cseg->p);
|
|
80137c8: 68fb ldr r3, [r7, #12]
|
|
80137ca: 685b ldr r3, [r3, #4]
|
|
80137cc: 4618 mov r0, r3
|
|
80137ce: f7fe fde9 bl 80123a4 <pbuf_ref>
|
|
return cseg;
|
|
80137d2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80137d4: 4618 mov r0, r3
|
|
80137d6: 3710 adds r7, #16
|
|
80137d8: 46bd mov sp, r7
|
|
80137da: bd80 pop {r7, pc}
|
|
80137dc: 0801eb48 .word 0x0801eb48
|
|
80137e0: 0801f09c .word 0x0801f09c
|
|
80137e4: 0801eb8c .word 0x0801eb8c
|
|
|
|
080137e8 <tcp_recv_null>:
|
|
* Default receive callback that is called if the user didn't register
|
|
* a recv callback for the pcb.
|
|
*/
|
|
err_t
|
|
tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err)
|
|
{
|
|
80137e8: b580 push {r7, lr}
|
|
80137ea: b084 sub sp, #16
|
|
80137ec: af00 add r7, sp, #0
|
|
80137ee: 60f8 str r0, [r7, #12]
|
|
80137f0: 60b9 str r1, [r7, #8]
|
|
80137f2: 607a str r2, [r7, #4]
|
|
80137f4: 70fb strb r3, [r7, #3]
|
|
LWIP_UNUSED_ARG(arg);
|
|
|
|
LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
80137f6: 68bb ldr r3, [r7, #8]
|
|
80137f8: 2b00 cmp r3, #0
|
|
80137fa: d109 bne.n 8013810 <tcp_recv_null+0x28>
|
|
80137fc: 4b12 ldr r3, [pc, #72] ; (8013848 <tcp_recv_null+0x60>)
|
|
80137fe: f44f 62d3 mov.w r2, #1688 ; 0x698
|
|
8013802: 4912 ldr r1, [pc, #72] ; (801384c <tcp_recv_null+0x64>)
|
|
8013804: 4812 ldr r0, [pc, #72] ; (8013850 <tcp_recv_null+0x68>)
|
|
8013806: f009 fa57 bl 801ccb8 <iprintf>
|
|
801380a: f06f 030f mvn.w r3, #15
|
|
801380e: e016 b.n 801383e <tcp_recv_null+0x56>
|
|
|
|
if (p != NULL) {
|
|
8013810: 687b ldr r3, [r7, #4]
|
|
8013812: 2b00 cmp r3, #0
|
|
8013814: d009 beq.n 801382a <tcp_recv_null+0x42>
|
|
tcp_recved(pcb, p->tot_len);
|
|
8013816: 687b ldr r3, [r7, #4]
|
|
8013818: 891b ldrh r3, [r3, #8]
|
|
801381a: 4619 mov r1, r3
|
|
801381c: 68b8 ldr r0, [r7, #8]
|
|
801381e: f7ff fb1d bl 8012e5c <tcp_recved>
|
|
pbuf_free(p);
|
|
8013822: 6878 ldr r0, [r7, #4]
|
|
8013824: f7fe fd18 bl 8012258 <pbuf_free>
|
|
8013828: e008 b.n 801383c <tcp_recv_null+0x54>
|
|
} else if (err == ERR_OK) {
|
|
801382a: f997 3003 ldrsb.w r3, [r7, #3]
|
|
801382e: 2b00 cmp r3, #0
|
|
8013830: d104 bne.n 801383c <tcp_recv_null+0x54>
|
|
return tcp_close(pcb);
|
|
8013832: 68b8 ldr r0, [r7, #8]
|
|
8013834: f7ff f9c2 bl 8012bbc <tcp_close>
|
|
8013838: 4603 mov r3, r0
|
|
801383a: e000 b.n 801383e <tcp_recv_null+0x56>
|
|
}
|
|
return ERR_OK;
|
|
801383c: 2300 movs r3, #0
|
|
}
|
|
801383e: 4618 mov r0, r3
|
|
8013840: 3710 adds r7, #16
|
|
8013842: 46bd mov sp, r7
|
|
8013844: bd80 pop {r7, pc}
|
|
8013846: bf00 nop
|
|
8013848: 0801eb48 .word 0x0801eb48
|
|
801384c: 0801f0b8 .word 0x0801f0b8
|
|
8013850: 0801eb8c .word 0x0801eb8c
|
|
|
|
08013854 <tcp_kill_prio>:
|
|
*
|
|
* @param prio minimum priority
|
|
*/
|
|
static void
|
|
tcp_kill_prio(u8_t prio)
|
|
{
|
|
8013854: b580 push {r7, lr}
|
|
8013856: b086 sub sp, #24
|
|
8013858: af00 add r7, sp, #0
|
|
801385a: 4603 mov r3, r0
|
|
801385c: 71fb strb r3, [r7, #7]
|
|
struct tcp_pcb *pcb, *inactive;
|
|
u32_t inactivity;
|
|
u8_t mprio;
|
|
|
|
mprio = LWIP_MIN(TCP_PRIO_MAX, prio);
|
|
801385e: f997 3007 ldrsb.w r3, [r7, #7]
|
|
8013862: 2b00 cmp r3, #0
|
|
8013864: db01 blt.n 801386a <tcp_kill_prio+0x16>
|
|
8013866: 79fb ldrb r3, [r7, #7]
|
|
8013868: e000 b.n 801386c <tcp_kill_prio+0x18>
|
|
801386a: 237f movs r3, #127 ; 0x7f
|
|
801386c: 72fb strb r3, [r7, #11]
|
|
|
|
/* We want to kill connections with a lower prio, so bail out if
|
|
* supplied prio is 0 - there can never be a lower prio
|
|
*/
|
|
if (mprio == 0) {
|
|
801386e: 7afb ldrb r3, [r7, #11]
|
|
8013870: 2b00 cmp r3, #0
|
|
8013872: d034 beq.n 80138de <tcp_kill_prio+0x8a>
|
|
/* We only want kill connections with a lower prio, so decrement prio by one
|
|
* and start searching for oldest connection with same or lower priority than mprio.
|
|
* We want to find the connections with the lowest possible prio, and among
|
|
* these the one with the longest inactivity time.
|
|
*/
|
|
mprio--;
|
|
8013874: 7afb ldrb r3, [r7, #11]
|
|
8013876: 3b01 subs r3, #1
|
|
8013878: 72fb strb r3, [r7, #11]
|
|
|
|
inactivity = 0;
|
|
801387a: 2300 movs r3, #0
|
|
801387c: 60fb str r3, [r7, #12]
|
|
inactive = NULL;
|
|
801387e: 2300 movs r3, #0
|
|
8013880: 613b str r3, [r7, #16]
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8013882: 4b19 ldr r3, [pc, #100] ; (80138e8 <tcp_kill_prio+0x94>)
|
|
8013884: 681b ldr r3, [r3, #0]
|
|
8013886: 617b str r3, [r7, #20]
|
|
8013888: e01f b.n 80138ca <tcp_kill_prio+0x76>
|
|
/* lower prio is always a kill candidate */
|
|
if ((pcb->prio < mprio) ||
|
|
801388a: 697b ldr r3, [r7, #20]
|
|
801388c: 7d5b ldrb r3, [r3, #21]
|
|
801388e: 7afa ldrb r2, [r7, #11]
|
|
8013890: 429a cmp r2, r3
|
|
8013892: d80c bhi.n 80138ae <tcp_kill_prio+0x5a>
|
|
/* longer inactivity is also a kill candidate */
|
|
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
|
|
8013894: 697b ldr r3, [r7, #20]
|
|
8013896: 7d5b ldrb r3, [r3, #21]
|
|
if ((pcb->prio < mprio) ||
|
|
8013898: 7afa ldrb r2, [r7, #11]
|
|
801389a: 429a cmp r2, r3
|
|
801389c: d112 bne.n 80138c4 <tcp_kill_prio+0x70>
|
|
((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) {
|
|
801389e: 4b13 ldr r3, [pc, #76] ; (80138ec <tcp_kill_prio+0x98>)
|
|
80138a0: 681a ldr r2, [r3, #0]
|
|
80138a2: 697b ldr r3, [r7, #20]
|
|
80138a4: 6a1b ldr r3, [r3, #32]
|
|
80138a6: 1ad3 subs r3, r2, r3
|
|
80138a8: 68fa ldr r2, [r7, #12]
|
|
80138aa: 429a cmp r2, r3
|
|
80138ac: d80a bhi.n 80138c4 <tcp_kill_prio+0x70>
|
|
inactivity = tcp_ticks - pcb->tmr;
|
|
80138ae: 4b0f ldr r3, [pc, #60] ; (80138ec <tcp_kill_prio+0x98>)
|
|
80138b0: 681a ldr r2, [r3, #0]
|
|
80138b2: 697b ldr r3, [r7, #20]
|
|
80138b4: 6a1b ldr r3, [r3, #32]
|
|
80138b6: 1ad3 subs r3, r2, r3
|
|
80138b8: 60fb str r3, [r7, #12]
|
|
inactive = pcb;
|
|
80138ba: 697b ldr r3, [r7, #20]
|
|
80138bc: 613b str r3, [r7, #16]
|
|
mprio = pcb->prio;
|
|
80138be: 697b ldr r3, [r7, #20]
|
|
80138c0: 7d5b ldrb r3, [r3, #21]
|
|
80138c2: 72fb strb r3, [r7, #11]
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
80138c4: 697b ldr r3, [r7, #20]
|
|
80138c6: 68db ldr r3, [r3, #12]
|
|
80138c8: 617b str r3, [r7, #20]
|
|
80138ca: 697b ldr r3, [r7, #20]
|
|
80138cc: 2b00 cmp r3, #0
|
|
80138ce: d1dc bne.n 801388a <tcp_kill_prio+0x36>
|
|
}
|
|
}
|
|
if (inactive != NULL) {
|
|
80138d0: 693b ldr r3, [r7, #16]
|
|
80138d2: 2b00 cmp r3, #0
|
|
80138d4: d004 beq.n 80138e0 <tcp_kill_prio+0x8c>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n",
|
|
(void *)inactive, inactivity));
|
|
tcp_abort(inactive);
|
|
80138d6: 6938 ldr r0, [r7, #16]
|
|
80138d8: f7ff fa5a bl 8012d90 <tcp_abort>
|
|
80138dc: e000 b.n 80138e0 <tcp_kill_prio+0x8c>
|
|
return;
|
|
80138de: bf00 nop
|
|
}
|
|
}
|
|
80138e0: 3718 adds r7, #24
|
|
80138e2: 46bd mov sp, r7
|
|
80138e4: bd80 pop {r7, pc}
|
|
80138e6: bf00 nop
|
|
80138e8: 2000f7fc .word 0x2000f7fc
|
|
80138ec: 2000f800 .word 0x2000f800
|
|
|
|
080138f0 <tcp_kill_state>:
|
|
* Kills the oldest connection that is in specific state.
|
|
* Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available.
|
|
*/
|
|
static void
|
|
tcp_kill_state(enum tcp_state state)
|
|
{
|
|
80138f0: b580 push {r7, lr}
|
|
80138f2: b086 sub sp, #24
|
|
80138f4: af00 add r7, sp, #0
|
|
80138f6: 4603 mov r3, r0
|
|
80138f8: 71fb strb r3, [r7, #7]
|
|
struct tcp_pcb *pcb, *inactive;
|
|
u32_t inactivity;
|
|
|
|
LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK));
|
|
80138fa: 79fb ldrb r3, [r7, #7]
|
|
80138fc: 2b08 cmp r3, #8
|
|
80138fe: d009 beq.n 8013914 <tcp_kill_state+0x24>
|
|
8013900: 79fb ldrb r3, [r7, #7]
|
|
8013902: 2b09 cmp r3, #9
|
|
8013904: d006 beq.n 8013914 <tcp_kill_state+0x24>
|
|
8013906: 4b1a ldr r3, [pc, #104] ; (8013970 <tcp_kill_state+0x80>)
|
|
8013908: f240 62dd movw r2, #1757 ; 0x6dd
|
|
801390c: 4919 ldr r1, [pc, #100] ; (8013974 <tcp_kill_state+0x84>)
|
|
801390e: 481a ldr r0, [pc, #104] ; (8013978 <tcp_kill_state+0x88>)
|
|
8013910: f009 f9d2 bl 801ccb8 <iprintf>
|
|
|
|
inactivity = 0;
|
|
8013914: 2300 movs r3, #0
|
|
8013916: 60fb str r3, [r7, #12]
|
|
inactive = NULL;
|
|
8013918: 2300 movs r3, #0
|
|
801391a: 613b str r3, [r7, #16]
|
|
/* Go through the list of active pcbs and get the oldest pcb that is in state
|
|
CLOSING/LAST_ACK. */
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
801391c: 4b17 ldr r3, [pc, #92] ; (801397c <tcp_kill_state+0x8c>)
|
|
801391e: 681b ldr r3, [r3, #0]
|
|
8013920: 617b str r3, [r7, #20]
|
|
8013922: e017 b.n 8013954 <tcp_kill_state+0x64>
|
|
if (pcb->state == state) {
|
|
8013924: 697b ldr r3, [r7, #20]
|
|
8013926: 7d1b ldrb r3, [r3, #20]
|
|
8013928: 79fa ldrb r2, [r7, #7]
|
|
801392a: 429a cmp r2, r3
|
|
801392c: d10f bne.n 801394e <tcp_kill_state+0x5e>
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
|
|
801392e: 4b14 ldr r3, [pc, #80] ; (8013980 <tcp_kill_state+0x90>)
|
|
8013930: 681a ldr r2, [r3, #0]
|
|
8013932: 697b ldr r3, [r7, #20]
|
|
8013934: 6a1b ldr r3, [r3, #32]
|
|
8013936: 1ad3 subs r3, r2, r3
|
|
8013938: 68fa ldr r2, [r7, #12]
|
|
801393a: 429a cmp r2, r3
|
|
801393c: d807 bhi.n 801394e <tcp_kill_state+0x5e>
|
|
inactivity = tcp_ticks - pcb->tmr;
|
|
801393e: 4b10 ldr r3, [pc, #64] ; (8013980 <tcp_kill_state+0x90>)
|
|
8013940: 681a ldr r2, [r3, #0]
|
|
8013942: 697b ldr r3, [r7, #20]
|
|
8013944: 6a1b ldr r3, [r3, #32]
|
|
8013946: 1ad3 subs r3, r2, r3
|
|
8013948: 60fb str r3, [r7, #12]
|
|
inactive = pcb;
|
|
801394a: 697b ldr r3, [r7, #20]
|
|
801394c: 613b str r3, [r7, #16]
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
801394e: 697b ldr r3, [r7, #20]
|
|
8013950: 68db ldr r3, [r3, #12]
|
|
8013952: 617b str r3, [r7, #20]
|
|
8013954: 697b ldr r3, [r7, #20]
|
|
8013956: 2b00 cmp r3, #0
|
|
8013958: d1e4 bne.n 8013924 <tcp_kill_state+0x34>
|
|
}
|
|
}
|
|
}
|
|
if (inactive != NULL) {
|
|
801395a: 693b ldr r3, [r7, #16]
|
|
801395c: 2b00 cmp r3, #0
|
|
801395e: d003 beq.n 8013968 <tcp_kill_state+0x78>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n",
|
|
tcp_state_str[state], (void *)inactive, inactivity));
|
|
/* Don't send a RST, since no data is lost. */
|
|
tcp_abandon(inactive, 0);
|
|
8013960: 2100 movs r1, #0
|
|
8013962: 6938 ldr r0, [r7, #16]
|
|
8013964: f7ff f956 bl 8012c14 <tcp_abandon>
|
|
}
|
|
}
|
|
8013968: bf00 nop
|
|
801396a: 3718 adds r7, #24
|
|
801396c: 46bd mov sp, r7
|
|
801396e: bd80 pop {r7, pc}
|
|
8013970: 0801eb48 .word 0x0801eb48
|
|
8013974: 0801f0d4 .word 0x0801f0d4
|
|
8013978: 0801eb8c .word 0x0801eb8c
|
|
801397c: 2000f7fc .word 0x2000f7fc
|
|
8013980: 2000f800 .word 0x2000f800
|
|
|
|
08013984 <tcp_kill_timewait>:
|
|
* Kills the oldest connection that is in TIME_WAIT state.
|
|
* Called from tcp_alloc() if no more connections are available.
|
|
*/
|
|
static void
|
|
tcp_kill_timewait(void)
|
|
{
|
|
8013984: b580 push {r7, lr}
|
|
8013986: b084 sub sp, #16
|
|
8013988: af00 add r7, sp, #0
|
|
struct tcp_pcb *pcb, *inactive;
|
|
u32_t inactivity;
|
|
|
|
inactivity = 0;
|
|
801398a: 2300 movs r3, #0
|
|
801398c: 607b str r3, [r7, #4]
|
|
inactive = NULL;
|
|
801398e: 2300 movs r3, #0
|
|
8013990: 60bb str r3, [r7, #8]
|
|
/* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */
|
|
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8013992: 4b12 ldr r3, [pc, #72] ; (80139dc <tcp_kill_timewait+0x58>)
|
|
8013994: 681b ldr r3, [r3, #0]
|
|
8013996: 60fb str r3, [r7, #12]
|
|
8013998: e012 b.n 80139c0 <tcp_kill_timewait+0x3c>
|
|
if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) {
|
|
801399a: 4b11 ldr r3, [pc, #68] ; (80139e0 <tcp_kill_timewait+0x5c>)
|
|
801399c: 681a ldr r2, [r3, #0]
|
|
801399e: 68fb ldr r3, [r7, #12]
|
|
80139a0: 6a1b ldr r3, [r3, #32]
|
|
80139a2: 1ad3 subs r3, r2, r3
|
|
80139a4: 687a ldr r2, [r7, #4]
|
|
80139a6: 429a cmp r2, r3
|
|
80139a8: d807 bhi.n 80139ba <tcp_kill_timewait+0x36>
|
|
inactivity = tcp_ticks - pcb->tmr;
|
|
80139aa: 4b0d ldr r3, [pc, #52] ; (80139e0 <tcp_kill_timewait+0x5c>)
|
|
80139ac: 681a ldr r2, [r3, #0]
|
|
80139ae: 68fb ldr r3, [r7, #12]
|
|
80139b0: 6a1b ldr r3, [r3, #32]
|
|
80139b2: 1ad3 subs r3, r2, r3
|
|
80139b4: 607b str r3, [r7, #4]
|
|
inactive = pcb;
|
|
80139b6: 68fb ldr r3, [r7, #12]
|
|
80139b8: 60bb str r3, [r7, #8]
|
|
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
80139ba: 68fb ldr r3, [r7, #12]
|
|
80139bc: 68db ldr r3, [r3, #12]
|
|
80139be: 60fb str r3, [r7, #12]
|
|
80139c0: 68fb ldr r3, [r7, #12]
|
|
80139c2: 2b00 cmp r3, #0
|
|
80139c4: d1e9 bne.n 801399a <tcp_kill_timewait+0x16>
|
|
}
|
|
}
|
|
if (inactive != NULL) {
|
|
80139c6: 68bb ldr r3, [r7, #8]
|
|
80139c8: 2b00 cmp r3, #0
|
|
80139ca: d002 beq.n 80139d2 <tcp_kill_timewait+0x4e>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n",
|
|
(void *)inactive, inactivity));
|
|
tcp_abort(inactive);
|
|
80139cc: 68b8 ldr r0, [r7, #8]
|
|
80139ce: f7ff f9df bl 8012d90 <tcp_abort>
|
|
}
|
|
}
|
|
80139d2: bf00 nop
|
|
80139d4: 3710 adds r7, #16
|
|
80139d6: 46bd mov sp, r7
|
|
80139d8: bd80 pop {r7, pc}
|
|
80139da: bf00 nop
|
|
80139dc: 2000f80c .word 0x2000f80c
|
|
80139e0: 2000f800 .word 0x2000f800
|
|
|
|
080139e4 <tcp_handle_closepend>:
|
|
* now send the FIN (which failed before), the pcb might be in a state that is
|
|
* OK for us to now free it.
|
|
*/
|
|
static void
|
|
tcp_handle_closepend(void)
|
|
{
|
|
80139e4: b580 push {r7, lr}
|
|
80139e6: b082 sub sp, #8
|
|
80139e8: af00 add r7, sp, #0
|
|
struct tcp_pcb *pcb = tcp_active_pcbs;
|
|
80139ea: 4b10 ldr r3, [pc, #64] ; (8013a2c <tcp_handle_closepend+0x48>)
|
|
80139ec: 681b ldr r3, [r3, #0]
|
|
80139ee: 607b str r3, [r7, #4]
|
|
|
|
while (pcb != NULL) {
|
|
80139f0: e014 b.n 8013a1c <tcp_handle_closepend+0x38>
|
|
struct tcp_pcb *next = pcb->next;
|
|
80139f2: 687b ldr r3, [r7, #4]
|
|
80139f4: 68db ldr r3, [r3, #12]
|
|
80139f6: 603b str r3, [r7, #0]
|
|
/* send pending FIN */
|
|
if (pcb->flags & TF_CLOSEPEND) {
|
|
80139f8: 687b ldr r3, [r7, #4]
|
|
80139fa: 8b5b ldrh r3, [r3, #26]
|
|
80139fc: f003 0308 and.w r3, r3, #8
|
|
8013a00: 2b00 cmp r3, #0
|
|
8013a02: d009 beq.n 8013a18 <tcp_handle_closepend+0x34>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n"));
|
|
tcp_clear_flags(pcb, TF_CLOSEPEND);
|
|
8013a04: 687b ldr r3, [r7, #4]
|
|
8013a06: 8b5b ldrh r3, [r3, #26]
|
|
8013a08: f023 0308 bic.w r3, r3, #8
|
|
8013a0c: b29a uxth r2, r3
|
|
8013a0e: 687b ldr r3, [r7, #4]
|
|
8013a10: 835a strh r2, [r3, #26]
|
|
tcp_close_shutdown_fin(pcb);
|
|
8013a12: 6878 ldr r0, [r7, #4]
|
|
8013a14: f7ff f86c bl 8012af0 <tcp_close_shutdown_fin>
|
|
}
|
|
pcb = next;
|
|
8013a18: 683b ldr r3, [r7, #0]
|
|
8013a1a: 607b str r3, [r7, #4]
|
|
while (pcb != NULL) {
|
|
8013a1c: 687b ldr r3, [r7, #4]
|
|
8013a1e: 2b00 cmp r3, #0
|
|
8013a20: d1e7 bne.n 80139f2 <tcp_handle_closepend+0xe>
|
|
}
|
|
}
|
|
8013a22: bf00 nop
|
|
8013a24: 3708 adds r7, #8
|
|
8013a26: 46bd mov sp, r7
|
|
8013a28: bd80 pop {r7, pc}
|
|
8013a2a: bf00 nop
|
|
8013a2c: 2000f7fc .word 0x2000f7fc
|
|
|
|
08013a30 <tcp_alloc>:
|
|
* @param prio priority for the new pcb
|
|
* @return a new tcp_pcb that initially is in state CLOSED
|
|
*/
|
|
struct tcp_pcb *
|
|
tcp_alloc(u8_t prio)
|
|
{
|
|
8013a30: b580 push {r7, lr}
|
|
8013a32: b084 sub sp, #16
|
|
8013a34: af00 add r7, sp, #0
|
|
8013a36: 4603 mov r3, r0
|
|
8013a38: 71fb strb r3, [r7, #7]
|
|
struct tcp_pcb *pcb;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
|
|
8013a3a: 2001 movs r0, #1
|
|
8013a3c: f7fd fd0e bl 801145c <memp_malloc>
|
|
8013a40: 60f8 str r0, [r7, #12]
|
|
if (pcb == NULL) {
|
|
8013a42: 68fb ldr r3, [r7, #12]
|
|
8013a44: 2b00 cmp r3, #0
|
|
8013a46: d126 bne.n 8013a96 <tcp_alloc+0x66>
|
|
/* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */
|
|
tcp_handle_closepend();
|
|
8013a48: f7ff ffcc bl 80139e4 <tcp_handle_closepend>
|
|
|
|
/* Try killing oldest connection in TIME-WAIT. */
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n"));
|
|
tcp_kill_timewait();
|
|
8013a4c: f7ff ff9a bl 8013984 <tcp_kill_timewait>
|
|
/* Try to allocate a tcp_pcb again. */
|
|
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
|
|
8013a50: 2001 movs r0, #1
|
|
8013a52: f7fd fd03 bl 801145c <memp_malloc>
|
|
8013a56: 60f8 str r0, [r7, #12]
|
|
if (pcb == NULL) {
|
|
8013a58: 68fb ldr r3, [r7, #12]
|
|
8013a5a: 2b00 cmp r3, #0
|
|
8013a5c: d11b bne.n 8013a96 <tcp_alloc+0x66>
|
|
/* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n"));
|
|
tcp_kill_state(LAST_ACK);
|
|
8013a5e: 2009 movs r0, #9
|
|
8013a60: f7ff ff46 bl 80138f0 <tcp_kill_state>
|
|
/* Try to allocate a tcp_pcb again. */
|
|
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
|
|
8013a64: 2001 movs r0, #1
|
|
8013a66: f7fd fcf9 bl 801145c <memp_malloc>
|
|
8013a6a: 60f8 str r0, [r7, #12]
|
|
if (pcb == NULL) {
|
|
8013a6c: 68fb ldr r3, [r7, #12]
|
|
8013a6e: 2b00 cmp r3, #0
|
|
8013a70: d111 bne.n 8013a96 <tcp_alloc+0x66>
|
|
/* Try killing oldest connection in CLOSING. */
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n"));
|
|
tcp_kill_state(CLOSING);
|
|
8013a72: 2008 movs r0, #8
|
|
8013a74: f7ff ff3c bl 80138f0 <tcp_kill_state>
|
|
/* Try to allocate a tcp_pcb again. */
|
|
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
|
|
8013a78: 2001 movs r0, #1
|
|
8013a7a: f7fd fcef bl 801145c <memp_malloc>
|
|
8013a7e: 60f8 str r0, [r7, #12]
|
|
if (pcb == NULL) {
|
|
8013a80: 68fb ldr r3, [r7, #12]
|
|
8013a82: 2b00 cmp r3, #0
|
|
8013a84: d107 bne.n 8013a96 <tcp_alloc+0x66>
|
|
/* Try killing oldest active connection with lower priority than the new one. */
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio));
|
|
tcp_kill_prio(prio);
|
|
8013a86: 79fb ldrb r3, [r7, #7]
|
|
8013a88: 4618 mov r0, r3
|
|
8013a8a: f7ff fee3 bl 8013854 <tcp_kill_prio>
|
|
/* Try to allocate a tcp_pcb again. */
|
|
pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB);
|
|
8013a8e: 2001 movs r0, #1
|
|
8013a90: f7fd fce4 bl 801145c <memp_malloc>
|
|
8013a94: 60f8 str r0, [r7, #12]
|
|
if (pcb != NULL) {
|
|
/* adjust err stats: memp_malloc failed above */
|
|
MEMP_STATS_DEC(err, MEMP_TCP_PCB);
|
|
}
|
|
}
|
|
if (pcb != NULL) {
|
|
8013a96: 68fb ldr r3, [r7, #12]
|
|
8013a98: 2b00 cmp r3, #0
|
|
8013a9a: d03f beq.n 8013b1c <tcp_alloc+0xec>
|
|
/* zero out the whole pcb, so there is no need to initialize members to zero */
|
|
memset(pcb, 0, sizeof(struct tcp_pcb));
|
|
8013a9c: 229c movs r2, #156 ; 0x9c
|
|
8013a9e: 2100 movs r1, #0
|
|
8013aa0: 68f8 ldr r0, [r7, #12]
|
|
8013aa2: f009 f900 bl 801cca6 <memset>
|
|
pcb->prio = prio;
|
|
8013aa6: 68fb ldr r3, [r7, #12]
|
|
8013aa8: 79fa ldrb r2, [r7, #7]
|
|
8013aaa: 755a strb r2, [r3, #21]
|
|
pcb->snd_buf = TCP_SND_BUF;
|
|
8013aac: 68fb ldr r3, [r7, #12]
|
|
8013aae: f44f 6286 mov.w r2, #1072 ; 0x430
|
|
8013ab2: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
|
|
/* Start with a window that does not need scaling. When window scaling is
|
|
enabled and used, the window is enlarged when both sides agree on scaling. */
|
|
pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND);
|
|
8013ab6: 68fb ldr r3, [r7, #12]
|
|
8013ab8: f44f 6206 mov.w r2, #2144 ; 0x860
|
|
8013abc: 855a strh r2, [r3, #42] ; 0x2a
|
|
8013abe: 68fb ldr r3, [r7, #12]
|
|
8013ac0: 8d5a ldrh r2, [r3, #42] ; 0x2a
|
|
8013ac2: 68fb ldr r3, [r7, #12]
|
|
8013ac4: 851a strh r2, [r3, #40] ; 0x28
|
|
pcb->ttl = TCP_TTL;
|
|
8013ac6: 68fb ldr r3, [r7, #12]
|
|
8013ac8: 22ff movs r2, #255 ; 0xff
|
|
8013aca: 72da strb r2, [r3, #11]
|
|
/* As initial send MSS, we use TCP_MSS but limit it to 536.
|
|
The send MSS is updated when an MSS option is received. */
|
|
pcb->mss = INITIAL_MSS;
|
|
8013acc: 68fb ldr r3, [r7, #12]
|
|
8013ace: f44f 7206 mov.w r2, #536 ; 0x218
|
|
8013ad2: 865a strh r2, [r3, #50] ; 0x32
|
|
pcb->rto = 3000 / TCP_SLOW_INTERVAL;
|
|
8013ad4: 68fb ldr r3, [r7, #12]
|
|
8013ad6: 2206 movs r2, #6
|
|
8013ad8: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
pcb->sv = 3000 / TCP_SLOW_INTERVAL;
|
|
8013adc: 68fb ldr r3, [r7, #12]
|
|
8013ade: 2206 movs r2, #6
|
|
8013ae0: 87da strh r2, [r3, #62] ; 0x3e
|
|
pcb->rtime = -1;
|
|
8013ae2: 68fb ldr r3, [r7, #12]
|
|
8013ae4: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8013ae8: 861a strh r2, [r3, #48] ; 0x30
|
|
pcb->cwnd = 1;
|
|
8013aea: 68fb ldr r3, [r7, #12]
|
|
8013aec: 2201 movs r2, #1
|
|
8013aee: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
pcb->tmr = tcp_ticks;
|
|
8013af2: 4b0d ldr r3, [pc, #52] ; (8013b28 <tcp_alloc+0xf8>)
|
|
8013af4: 681a ldr r2, [r3, #0]
|
|
8013af6: 68fb ldr r3, [r7, #12]
|
|
8013af8: 621a str r2, [r3, #32]
|
|
pcb->last_timer = tcp_timer_ctr;
|
|
8013afa: 4b0c ldr r3, [pc, #48] ; (8013b2c <tcp_alloc+0xfc>)
|
|
8013afc: 781a ldrb r2, [r3, #0]
|
|
8013afe: 68fb ldr r3, [r7, #12]
|
|
8013b00: 779a strb r2, [r3, #30]
|
|
of using the largest advertised receive window. We've seen complications with
|
|
receiving TCPs that use window scaling and/or window auto-tuning where the
|
|
initial advertised window is very small and then grows rapidly once the
|
|
connection is established. To avoid these complications, we set ssthresh to the
|
|
largest effective cwnd (amount of in-flight data) that the sender can have. */
|
|
pcb->ssthresh = TCP_SND_BUF;
|
|
8013b02: 68fb ldr r3, [r7, #12]
|
|
8013b04: f44f 6286 mov.w r2, #1072 ; 0x430
|
|
8013b08: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
|
|
|
|
#if LWIP_CALLBACK_API
|
|
pcb->recv = tcp_recv_null;
|
|
8013b0c: 68fb ldr r3, [r7, #12]
|
|
8013b0e: 4a08 ldr r2, [pc, #32] ; (8013b30 <tcp_alloc+0x100>)
|
|
8013b10: f8c3 2084 str.w r2, [r3, #132] ; 0x84
|
|
#endif /* LWIP_CALLBACK_API */
|
|
|
|
/* Init KEEPALIVE timer */
|
|
pcb->keep_idle = TCP_KEEPIDLE_DEFAULT;
|
|
8013b14: 68fb ldr r3, [r7, #12]
|
|
8013b16: 4a07 ldr r2, [pc, #28] ; (8013b34 <tcp_alloc+0x104>)
|
|
8013b18: f8c3 2094 str.w r2, [r3, #148] ; 0x94
|
|
#if LWIP_TCP_KEEPALIVE
|
|
pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT;
|
|
pcb->keep_cnt = TCP_KEEPCNT_DEFAULT;
|
|
#endif /* LWIP_TCP_KEEPALIVE */
|
|
}
|
|
return pcb;
|
|
8013b1c: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8013b1e: 4618 mov r0, r3
|
|
8013b20: 3710 adds r7, #16
|
|
8013b22: 46bd mov sp, r7
|
|
8013b24: bd80 pop {r7, pc}
|
|
8013b26: bf00 nop
|
|
8013b28: 2000f800 .word 0x2000f800
|
|
8013b2c: 2000872a .word 0x2000872a
|
|
8013b30: 080137e9 .word 0x080137e9
|
|
8013b34: 006ddd00 .word 0x006ddd00
|
|
|
|
08013b38 <tcp_pcb_purge>:
|
|
*
|
|
* @param pcb tcp_pcb to purge. The pcb itself is not deallocated!
|
|
*/
|
|
void
|
|
tcp_pcb_purge(struct tcp_pcb *pcb)
|
|
{
|
|
8013b38: b580 push {r7, lr}
|
|
8013b3a: b082 sub sp, #8
|
|
8013b3c: af00 add r7, sp, #0
|
|
8013b3e: 6078 str r0, [r7, #4]
|
|
LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return);
|
|
8013b40: 687b ldr r3, [r7, #4]
|
|
8013b42: 2b00 cmp r3, #0
|
|
8013b44: d107 bne.n 8013b56 <tcp_pcb_purge+0x1e>
|
|
8013b46: 4b21 ldr r3, [pc, #132] ; (8013bcc <tcp_pcb_purge+0x94>)
|
|
8013b48: f640 0251 movw r2, #2129 ; 0x851
|
|
8013b4c: 4920 ldr r1, [pc, #128] ; (8013bd0 <tcp_pcb_purge+0x98>)
|
|
8013b4e: 4821 ldr r0, [pc, #132] ; (8013bd4 <tcp_pcb_purge+0x9c>)
|
|
8013b50: f009 f8b2 bl 801ccb8 <iprintf>
|
|
8013b54: e037 b.n 8013bc6 <tcp_pcb_purge+0x8e>
|
|
|
|
if (pcb->state != CLOSED &&
|
|
8013b56: 687b ldr r3, [r7, #4]
|
|
8013b58: 7d1b ldrb r3, [r3, #20]
|
|
8013b5a: 2b00 cmp r3, #0
|
|
8013b5c: d033 beq.n 8013bc6 <tcp_pcb_purge+0x8e>
|
|
pcb->state != TIME_WAIT &&
|
|
8013b5e: 687b ldr r3, [r7, #4]
|
|
8013b60: 7d1b ldrb r3, [r3, #20]
|
|
if (pcb->state != CLOSED &&
|
|
8013b62: 2b0a cmp r3, #10
|
|
8013b64: d02f beq.n 8013bc6 <tcp_pcb_purge+0x8e>
|
|
pcb->state != LISTEN) {
|
|
8013b66: 687b ldr r3, [r7, #4]
|
|
8013b68: 7d1b ldrb r3, [r3, #20]
|
|
pcb->state != TIME_WAIT &&
|
|
8013b6a: 2b01 cmp r3, #1
|
|
8013b6c: d02b beq.n 8013bc6 <tcp_pcb_purge+0x8e>
|
|
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n"));
|
|
|
|
tcp_backlog_accepted(pcb);
|
|
|
|
if (pcb->refused_data != NULL) {
|
|
8013b6e: 687b ldr r3, [r7, #4]
|
|
8013b70: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8013b72: 2b00 cmp r3, #0
|
|
8013b74: d007 beq.n 8013b86 <tcp_pcb_purge+0x4e>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n"));
|
|
pbuf_free(pcb->refused_data);
|
|
8013b76: 687b ldr r3, [r7, #4]
|
|
8013b78: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8013b7a: 4618 mov r0, r3
|
|
8013b7c: f7fe fb6c bl 8012258 <pbuf_free>
|
|
pcb->refused_data = NULL;
|
|
8013b80: 687b ldr r3, [r7, #4]
|
|
8013b82: 2200 movs r2, #0
|
|
8013b84: 679a str r2, [r3, #120] ; 0x78
|
|
}
|
|
if (pcb->unacked != NULL) {
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n"));
|
|
}
|
|
#if TCP_QUEUE_OOSEQ
|
|
if (pcb->ooseq != NULL) {
|
|
8013b86: 687b ldr r3, [r7, #4]
|
|
8013b88: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8013b8a: 2b00 cmp r3, #0
|
|
8013b8c: d002 beq.n 8013b94 <tcp_pcb_purge+0x5c>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n"));
|
|
tcp_free_ooseq(pcb);
|
|
8013b8e: 6878 ldr r0, [r7, #4]
|
|
8013b90: f000 f986 bl 8013ea0 <tcp_free_ooseq>
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
|
|
/* Stop the retransmission timer as it will expect data on unacked
|
|
queue if it fires */
|
|
pcb->rtime = -1;
|
|
8013b94: 687b ldr r3, [r7, #4]
|
|
8013b96: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8013b9a: 861a strh r2, [r3, #48] ; 0x30
|
|
|
|
tcp_segs_free(pcb->unsent);
|
|
8013b9c: 687b ldr r3, [r7, #4]
|
|
8013b9e: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8013ba0: 4618 mov r0, r3
|
|
8013ba2: f7ff fdc9 bl 8013738 <tcp_segs_free>
|
|
tcp_segs_free(pcb->unacked);
|
|
8013ba6: 687b ldr r3, [r7, #4]
|
|
8013ba8: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8013baa: 4618 mov r0, r3
|
|
8013bac: f7ff fdc4 bl 8013738 <tcp_segs_free>
|
|
pcb->unacked = pcb->unsent = NULL;
|
|
8013bb0: 687b ldr r3, [r7, #4]
|
|
8013bb2: 2200 movs r2, #0
|
|
8013bb4: 66da str r2, [r3, #108] ; 0x6c
|
|
8013bb6: 687b ldr r3, [r7, #4]
|
|
8013bb8: 6eda ldr r2, [r3, #108] ; 0x6c
|
|
8013bba: 687b ldr r3, [r7, #4]
|
|
8013bbc: 671a str r2, [r3, #112] ; 0x70
|
|
#if TCP_OVERSIZE
|
|
pcb->unsent_oversize = 0;
|
|
8013bbe: 687b ldr r3, [r7, #4]
|
|
8013bc0: 2200 movs r2, #0
|
|
8013bc2: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
#endif /* TCP_OVERSIZE */
|
|
}
|
|
}
|
|
8013bc6: 3708 adds r7, #8
|
|
8013bc8: 46bd mov sp, r7
|
|
8013bca: bd80 pop {r7, pc}
|
|
8013bcc: 0801eb48 .word 0x0801eb48
|
|
8013bd0: 0801f194 .word 0x0801f194
|
|
8013bd4: 0801eb8c .word 0x0801eb8c
|
|
|
|
08013bd8 <tcp_pcb_remove>:
|
|
* @param pcblist PCB list to purge.
|
|
* @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated!
|
|
*/
|
|
void
|
|
tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb)
|
|
{
|
|
8013bd8: b580 push {r7, lr}
|
|
8013bda: b084 sub sp, #16
|
|
8013bdc: af00 add r7, sp, #0
|
|
8013bde: 6078 str r0, [r7, #4]
|
|
8013be0: 6039 str r1, [r7, #0]
|
|
LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL);
|
|
8013be2: 683b ldr r3, [r7, #0]
|
|
8013be4: 2b00 cmp r3, #0
|
|
8013be6: d106 bne.n 8013bf6 <tcp_pcb_remove+0x1e>
|
|
8013be8: 4b3e ldr r3, [pc, #248] ; (8013ce4 <tcp_pcb_remove+0x10c>)
|
|
8013bea: f640 0283 movw r2, #2179 ; 0x883
|
|
8013bee: 493e ldr r1, [pc, #248] ; (8013ce8 <tcp_pcb_remove+0x110>)
|
|
8013bf0: 483e ldr r0, [pc, #248] ; (8013cec <tcp_pcb_remove+0x114>)
|
|
8013bf2: f009 f861 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL);
|
|
8013bf6: 687b ldr r3, [r7, #4]
|
|
8013bf8: 2b00 cmp r3, #0
|
|
8013bfa: d106 bne.n 8013c0a <tcp_pcb_remove+0x32>
|
|
8013bfc: 4b39 ldr r3, [pc, #228] ; (8013ce4 <tcp_pcb_remove+0x10c>)
|
|
8013bfe: f640 0284 movw r2, #2180 ; 0x884
|
|
8013c02: 493b ldr r1, [pc, #236] ; (8013cf0 <tcp_pcb_remove+0x118>)
|
|
8013c04: 4839 ldr r0, [pc, #228] ; (8013cec <tcp_pcb_remove+0x114>)
|
|
8013c06: f009 f857 bl 801ccb8 <iprintf>
|
|
|
|
TCP_RMV(pcblist, pcb);
|
|
8013c0a: 687b ldr r3, [r7, #4]
|
|
8013c0c: 681b ldr r3, [r3, #0]
|
|
8013c0e: 683a ldr r2, [r7, #0]
|
|
8013c10: 429a cmp r2, r3
|
|
8013c12: d105 bne.n 8013c20 <tcp_pcb_remove+0x48>
|
|
8013c14: 687b ldr r3, [r7, #4]
|
|
8013c16: 681b ldr r3, [r3, #0]
|
|
8013c18: 68da ldr r2, [r3, #12]
|
|
8013c1a: 687b ldr r3, [r7, #4]
|
|
8013c1c: 601a str r2, [r3, #0]
|
|
8013c1e: e013 b.n 8013c48 <tcp_pcb_remove+0x70>
|
|
8013c20: 687b ldr r3, [r7, #4]
|
|
8013c22: 681b ldr r3, [r3, #0]
|
|
8013c24: 60fb str r3, [r7, #12]
|
|
8013c26: e00c b.n 8013c42 <tcp_pcb_remove+0x6a>
|
|
8013c28: 68fb ldr r3, [r7, #12]
|
|
8013c2a: 68db ldr r3, [r3, #12]
|
|
8013c2c: 683a ldr r2, [r7, #0]
|
|
8013c2e: 429a cmp r2, r3
|
|
8013c30: d104 bne.n 8013c3c <tcp_pcb_remove+0x64>
|
|
8013c32: 683b ldr r3, [r7, #0]
|
|
8013c34: 68da ldr r2, [r3, #12]
|
|
8013c36: 68fb ldr r3, [r7, #12]
|
|
8013c38: 60da str r2, [r3, #12]
|
|
8013c3a: e005 b.n 8013c48 <tcp_pcb_remove+0x70>
|
|
8013c3c: 68fb ldr r3, [r7, #12]
|
|
8013c3e: 68db ldr r3, [r3, #12]
|
|
8013c40: 60fb str r3, [r7, #12]
|
|
8013c42: 68fb ldr r3, [r7, #12]
|
|
8013c44: 2b00 cmp r3, #0
|
|
8013c46: d1ef bne.n 8013c28 <tcp_pcb_remove+0x50>
|
|
8013c48: 683b ldr r3, [r7, #0]
|
|
8013c4a: 2200 movs r2, #0
|
|
8013c4c: 60da str r2, [r3, #12]
|
|
|
|
tcp_pcb_purge(pcb);
|
|
8013c4e: 6838 ldr r0, [r7, #0]
|
|
8013c50: f7ff ff72 bl 8013b38 <tcp_pcb_purge>
|
|
|
|
/* if there is an outstanding delayed ACKs, send it */
|
|
if ((pcb->state != TIME_WAIT) &&
|
|
8013c54: 683b ldr r3, [r7, #0]
|
|
8013c56: 7d1b ldrb r3, [r3, #20]
|
|
8013c58: 2b0a cmp r3, #10
|
|
8013c5a: d013 beq.n 8013c84 <tcp_pcb_remove+0xac>
|
|
(pcb->state != LISTEN) &&
|
|
8013c5c: 683b ldr r3, [r7, #0]
|
|
8013c5e: 7d1b ldrb r3, [r3, #20]
|
|
if ((pcb->state != TIME_WAIT) &&
|
|
8013c60: 2b01 cmp r3, #1
|
|
8013c62: d00f beq.n 8013c84 <tcp_pcb_remove+0xac>
|
|
(pcb->flags & TF_ACK_DELAY)) {
|
|
8013c64: 683b ldr r3, [r7, #0]
|
|
8013c66: 8b5b ldrh r3, [r3, #26]
|
|
8013c68: f003 0301 and.w r3, r3, #1
|
|
(pcb->state != LISTEN) &&
|
|
8013c6c: 2b00 cmp r3, #0
|
|
8013c6e: d009 beq.n 8013c84 <tcp_pcb_remove+0xac>
|
|
tcp_ack_now(pcb);
|
|
8013c70: 683b ldr r3, [r7, #0]
|
|
8013c72: 8b5b ldrh r3, [r3, #26]
|
|
8013c74: f043 0302 orr.w r3, r3, #2
|
|
8013c78: b29a uxth r2, r3
|
|
8013c7a: 683b ldr r3, [r7, #0]
|
|
8013c7c: 835a strh r2, [r3, #26]
|
|
tcp_output(pcb);
|
|
8013c7e: 6838 ldr r0, [r7, #0]
|
|
8013c80: f002 ff68 bl 8016b54 <tcp_output>
|
|
}
|
|
|
|
if (pcb->state != LISTEN) {
|
|
8013c84: 683b ldr r3, [r7, #0]
|
|
8013c86: 7d1b ldrb r3, [r3, #20]
|
|
8013c88: 2b01 cmp r3, #1
|
|
8013c8a: d020 beq.n 8013cce <tcp_pcb_remove+0xf6>
|
|
LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL);
|
|
8013c8c: 683b ldr r3, [r7, #0]
|
|
8013c8e: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8013c90: 2b00 cmp r3, #0
|
|
8013c92: d006 beq.n 8013ca2 <tcp_pcb_remove+0xca>
|
|
8013c94: 4b13 ldr r3, [pc, #76] ; (8013ce4 <tcp_pcb_remove+0x10c>)
|
|
8013c96: f640 0293 movw r2, #2195 ; 0x893
|
|
8013c9a: 4916 ldr r1, [pc, #88] ; (8013cf4 <tcp_pcb_remove+0x11c>)
|
|
8013c9c: 4813 ldr r0, [pc, #76] ; (8013cec <tcp_pcb_remove+0x114>)
|
|
8013c9e: f009 f80b bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL);
|
|
8013ca2: 683b ldr r3, [r7, #0]
|
|
8013ca4: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8013ca6: 2b00 cmp r3, #0
|
|
8013ca8: d006 beq.n 8013cb8 <tcp_pcb_remove+0xe0>
|
|
8013caa: 4b0e ldr r3, [pc, #56] ; (8013ce4 <tcp_pcb_remove+0x10c>)
|
|
8013cac: f640 0294 movw r2, #2196 ; 0x894
|
|
8013cb0: 4911 ldr r1, [pc, #68] ; (8013cf8 <tcp_pcb_remove+0x120>)
|
|
8013cb2: 480e ldr r0, [pc, #56] ; (8013cec <tcp_pcb_remove+0x114>)
|
|
8013cb4: f009 f800 bl 801ccb8 <iprintf>
|
|
#if TCP_QUEUE_OOSEQ
|
|
LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL);
|
|
8013cb8: 683b ldr r3, [r7, #0]
|
|
8013cba: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8013cbc: 2b00 cmp r3, #0
|
|
8013cbe: d006 beq.n 8013cce <tcp_pcb_remove+0xf6>
|
|
8013cc0: 4b08 ldr r3, [pc, #32] ; (8013ce4 <tcp_pcb_remove+0x10c>)
|
|
8013cc2: f640 0296 movw r2, #2198 ; 0x896
|
|
8013cc6: 490d ldr r1, [pc, #52] ; (8013cfc <tcp_pcb_remove+0x124>)
|
|
8013cc8: 4808 ldr r0, [pc, #32] ; (8013cec <tcp_pcb_remove+0x114>)
|
|
8013cca: f008 fff5 bl 801ccb8 <iprintf>
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
}
|
|
|
|
pcb->state = CLOSED;
|
|
8013cce: 683b ldr r3, [r7, #0]
|
|
8013cd0: 2200 movs r2, #0
|
|
8013cd2: 751a strb r2, [r3, #20]
|
|
/* reset the local port to prevent the pcb from being 'bound' */
|
|
pcb->local_port = 0;
|
|
8013cd4: 683b ldr r3, [r7, #0]
|
|
8013cd6: 2200 movs r2, #0
|
|
8013cd8: 82da strh r2, [r3, #22]
|
|
|
|
LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane());
|
|
}
|
|
8013cda: bf00 nop
|
|
8013cdc: 3710 adds r7, #16
|
|
8013cde: 46bd mov sp, r7
|
|
8013ce0: bd80 pop {r7, pc}
|
|
8013ce2: bf00 nop
|
|
8013ce4: 0801eb48 .word 0x0801eb48
|
|
8013ce8: 0801f1b0 .word 0x0801f1b0
|
|
8013cec: 0801eb8c .word 0x0801eb8c
|
|
8013cf0: 0801f1cc .word 0x0801f1cc
|
|
8013cf4: 0801f1ec .word 0x0801f1ec
|
|
8013cf8: 0801f204 .word 0x0801f204
|
|
8013cfc: 0801f220 .word 0x0801f220
|
|
|
|
08013d00 <tcp_next_iss>:
|
|
*
|
|
* @return u32_t pseudo random sequence number
|
|
*/
|
|
u32_t
|
|
tcp_next_iss(struct tcp_pcb *pcb)
|
|
{
|
|
8013d00: b580 push {r7, lr}
|
|
8013d02: b082 sub sp, #8
|
|
8013d04: af00 add r7, sp, #0
|
|
8013d06: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
|
|
return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port);
|
|
#else /* LWIP_HOOK_TCP_ISN */
|
|
static u32_t iss = 6510;
|
|
|
|
LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL);
|
|
8013d08: 687b ldr r3, [r7, #4]
|
|
8013d0a: 2b00 cmp r3, #0
|
|
8013d0c: d106 bne.n 8013d1c <tcp_next_iss+0x1c>
|
|
8013d0e: 4b0a ldr r3, [pc, #40] ; (8013d38 <tcp_next_iss+0x38>)
|
|
8013d10: f640 02af movw r2, #2223 ; 0x8af
|
|
8013d14: 4909 ldr r1, [pc, #36] ; (8013d3c <tcp_next_iss+0x3c>)
|
|
8013d16: 480a ldr r0, [pc, #40] ; (8013d40 <tcp_next_iss+0x40>)
|
|
8013d18: f008 ffce bl 801ccb8 <iprintf>
|
|
LWIP_UNUSED_ARG(pcb);
|
|
|
|
iss += tcp_ticks; /* XXX */
|
|
8013d1c: 4b09 ldr r3, [pc, #36] ; (8013d44 <tcp_next_iss+0x44>)
|
|
8013d1e: 681a ldr r2, [r3, #0]
|
|
8013d20: 4b09 ldr r3, [pc, #36] ; (8013d48 <tcp_next_iss+0x48>)
|
|
8013d22: 681b ldr r3, [r3, #0]
|
|
8013d24: 4413 add r3, r2
|
|
8013d26: 4a07 ldr r2, [pc, #28] ; (8013d44 <tcp_next_iss+0x44>)
|
|
8013d28: 6013 str r3, [r2, #0]
|
|
return iss;
|
|
8013d2a: 4b06 ldr r3, [pc, #24] ; (8013d44 <tcp_next_iss+0x44>)
|
|
8013d2c: 681b ldr r3, [r3, #0]
|
|
#endif /* LWIP_HOOK_TCP_ISN */
|
|
}
|
|
8013d2e: 4618 mov r0, r3
|
|
8013d30: 3708 adds r7, #8
|
|
8013d32: 46bd mov sp, r7
|
|
8013d34: bd80 pop {r7, pc}
|
|
8013d36: bf00 nop
|
|
8013d38: 0801eb48 .word 0x0801eb48
|
|
8013d3c: 0801f238 .word 0x0801f238
|
|
8013d40: 0801eb8c .word 0x0801eb8c
|
|
8013d44: 20000078 .word 0x20000078
|
|
8013d48: 2000f800 .word 0x2000f800
|
|
|
|
08013d4c <tcp_eff_send_mss_netif>:
|
|
* by calculating the minimum of TCP_MSS and the mtu (if set) of the target
|
|
* netif (if not NULL).
|
|
*/
|
|
u16_t
|
|
tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest)
|
|
{
|
|
8013d4c: b580 push {r7, lr}
|
|
8013d4e: b086 sub sp, #24
|
|
8013d50: af00 add r7, sp, #0
|
|
8013d52: 4603 mov r3, r0
|
|
8013d54: 60b9 str r1, [r7, #8]
|
|
8013d56: 607a str r2, [r7, #4]
|
|
8013d58: 81fb strh r3, [r7, #14]
|
|
u16_t mss_s;
|
|
u16_t mtu;
|
|
|
|
LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */
|
|
|
|
LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL);
|
|
8013d5a: 687b ldr r3, [r7, #4]
|
|
8013d5c: 2b00 cmp r3, #0
|
|
8013d5e: d106 bne.n 8013d6e <tcp_eff_send_mss_netif+0x22>
|
|
8013d60: 4b14 ldr r3, [pc, #80] ; (8013db4 <tcp_eff_send_mss_netif+0x68>)
|
|
8013d62: f640 02c5 movw r2, #2245 ; 0x8c5
|
|
8013d66: 4914 ldr r1, [pc, #80] ; (8013db8 <tcp_eff_send_mss_netif+0x6c>)
|
|
8013d68: 4814 ldr r0, [pc, #80] ; (8013dbc <tcp_eff_send_mss_netif+0x70>)
|
|
8013d6a: f008 ffa5 bl 801ccb8 <iprintf>
|
|
else
|
|
#endif /* LWIP_IPV4 */
|
|
#endif /* LWIP_IPV6 */
|
|
#if LWIP_IPV4
|
|
{
|
|
if (outif == NULL) {
|
|
8013d6e: 68bb ldr r3, [r7, #8]
|
|
8013d70: 2b00 cmp r3, #0
|
|
8013d72: d101 bne.n 8013d78 <tcp_eff_send_mss_netif+0x2c>
|
|
return sendmss;
|
|
8013d74: 89fb ldrh r3, [r7, #14]
|
|
8013d76: e019 b.n 8013dac <tcp_eff_send_mss_netif+0x60>
|
|
}
|
|
mtu = outif->mtu;
|
|
8013d78: 68bb ldr r3, [r7, #8]
|
|
8013d7a: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8013d7c: 82fb strh r3, [r7, #22]
|
|
}
|
|
#endif /* LWIP_IPV4 */
|
|
|
|
if (mtu != 0) {
|
|
8013d7e: 8afb ldrh r3, [r7, #22]
|
|
8013d80: 2b00 cmp r3, #0
|
|
8013d82: d012 beq.n 8013daa <tcp_eff_send_mss_netif+0x5e>
|
|
else
|
|
#endif /* LWIP_IPV4 */
|
|
#endif /* LWIP_IPV6 */
|
|
#if LWIP_IPV4
|
|
{
|
|
offset = IP_HLEN + TCP_HLEN;
|
|
8013d84: 2328 movs r3, #40 ; 0x28
|
|
8013d86: 82bb strh r3, [r7, #20]
|
|
}
|
|
#endif /* LWIP_IPV4 */
|
|
mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0;
|
|
8013d88: 8afa ldrh r2, [r7, #22]
|
|
8013d8a: 8abb ldrh r3, [r7, #20]
|
|
8013d8c: 429a cmp r2, r3
|
|
8013d8e: d904 bls.n 8013d9a <tcp_eff_send_mss_netif+0x4e>
|
|
8013d90: 8afa ldrh r2, [r7, #22]
|
|
8013d92: 8abb ldrh r3, [r7, #20]
|
|
8013d94: 1ad3 subs r3, r2, r3
|
|
8013d96: b29b uxth r3, r3
|
|
8013d98: e000 b.n 8013d9c <tcp_eff_send_mss_netif+0x50>
|
|
8013d9a: 2300 movs r3, #0
|
|
8013d9c: 827b strh r3, [r7, #18]
|
|
/* RFC 1122, chap 4.2.2.6:
|
|
* Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize
|
|
* We correct for TCP options in tcp_write(), and don't support IP options.
|
|
*/
|
|
sendmss = LWIP_MIN(sendmss, mss_s);
|
|
8013d9e: 8a7a ldrh r2, [r7, #18]
|
|
8013da0: 89fb ldrh r3, [r7, #14]
|
|
8013da2: 4293 cmp r3, r2
|
|
8013da4: bf28 it cs
|
|
8013da6: 4613 movcs r3, r2
|
|
8013da8: 81fb strh r3, [r7, #14]
|
|
}
|
|
return sendmss;
|
|
8013daa: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8013dac: 4618 mov r0, r3
|
|
8013dae: 3718 adds r7, #24
|
|
8013db0: 46bd mov sp, r7
|
|
8013db2: bd80 pop {r7, pc}
|
|
8013db4: 0801eb48 .word 0x0801eb48
|
|
8013db8: 0801f254 .word 0x0801f254
|
|
8013dbc: 0801eb8c .word 0x0801eb8c
|
|
|
|
08013dc0 <tcp_netif_ip_addr_changed_pcblist>:
|
|
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
|
|
|
|
/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */
|
|
static void
|
|
tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list)
|
|
{
|
|
8013dc0: b580 push {r7, lr}
|
|
8013dc2: b084 sub sp, #16
|
|
8013dc4: af00 add r7, sp, #0
|
|
8013dc6: 6078 str r0, [r7, #4]
|
|
8013dc8: 6039 str r1, [r7, #0]
|
|
struct tcp_pcb *pcb;
|
|
pcb = pcb_list;
|
|
8013dca: 683b ldr r3, [r7, #0]
|
|
8013dcc: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL);
|
|
8013dce: 687b ldr r3, [r7, #4]
|
|
8013dd0: 2b00 cmp r3, #0
|
|
8013dd2: d119 bne.n 8013e08 <tcp_netif_ip_addr_changed_pcblist+0x48>
|
|
8013dd4: 4b10 ldr r3, [pc, #64] ; (8013e18 <tcp_netif_ip_addr_changed_pcblist+0x58>)
|
|
8013dd6: f44f 6210 mov.w r2, #2304 ; 0x900
|
|
8013dda: 4910 ldr r1, [pc, #64] ; (8013e1c <tcp_netif_ip_addr_changed_pcblist+0x5c>)
|
|
8013ddc: 4810 ldr r0, [pc, #64] ; (8013e20 <tcp_netif_ip_addr_changed_pcblist+0x60>)
|
|
8013dde: f008 ff6b bl 801ccb8 <iprintf>
|
|
|
|
while (pcb != NULL) {
|
|
8013de2: e011 b.n 8013e08 <tcp_netif_ip_addr_changed_pcblist+0x48>
|
|
/* PCB bound to current local interface address? */
|
|
if (ip_addr_cmp(&pcb->local_ip, old_addr)
|
|
8013de4: 68fb ldr r3, [r7, #12]
|
|
8013de6: 681a ldr r2, [r3, #0]
|
|
8013de8: 687b ldr r3, [r7, #4]
|
|
8013dea: 681b ldr r3, [r3, #0]
|
|
8013dec: 429a cmp r2, r3
|
|
8013dee: d108 bne.n 8013e02 <tcp_netif_ip_addr_changed_pcblist+0x42>
|
|
/* connections to link-local addresses must persist (RFC3927 ch. 1.9) */
|
|
&& (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip)))
|
|
#endif /* LWIP_AUTOIP */
|
|
) {
|
|
/* this connection must be aborted */
|
|
struct tcp_pcb *next = pcb->next;
|
|
8013df0: 68fb ldr r3, [r7, #12]
|
|
8013df2: 68db ldr r3, [r3, #12]
|
|
8013df4: 60bb str r3, [r7, #8]
|
|
LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb));
|
|
tcp_abort(pcb);
|
|
8013df6: 68f8 ldr r0, [r7, #12]
|
|
8013df8: f7fe ffca bl 8012d90 <tcp_abort>
|
|
pcb = next;
|
|
8013dfc: 68bb ldr r3, [r7, #8]
|
|
8013dfe: 60fb str r3, [r7, #12]
|
|
8013e00: e002 b.n 8013e08 <tcp_netif_ip_addr_changed_pcblist+0x48>
|
|
} else {
|
|
pcb = pcb->next;
|
|
8013e02: 68fb ldr r3, [r7, #12]
|
|
8013e04: 68db ldr r3, [r3, #12]
|
|
8013e06: 60fb str r3, [r7, #12]
|
|
while (pcb != NULL) {
|
|
8013e08: 68fb ldr r3, [r7, #12]
|
|
8013e0a: 2b00 cmp r3, #0
|
|
8013e0c: d1ea bne.n 8013de4 <tcp_netif_ip_addr_changed_pcblist+0x24>
|
|
}
|
|
}
|
|
}
|
|
8013e0e: bf00 nop
|
|
8013e10: 3710 adds r7, #16
|
|
8013e12: 46bd mov sp, r7
|
|
8013e14: bd80 pop {r7, pc}
|
|
8013e16: bf00 nop
|
|
8013e18: 0801eb48 .word 0x0801eb48
|
|
8013e1c: 0801f27c .word 0x0801f27c
|
|
8013e20: 0801eb8c .word 0x0801eb8c
|
|
|
|
08013e24 <tcp_netif_ip_addr_changed>:
|
|
* @param old_addr IP address of the netif before change
|
|
* @param new_addr IP address of the netif after change or NULL if netif has been removed
|
|
*/
|
|
void
|
|
tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
|
|
{
|
|
8013e24: b580 push {r7, lr}
|
|
8013e26: b084 sub sp, #16
|
|
8013e28: af00 add r7, sp, #0
|
|
8013e2a: 6078 str r0, [r7, #4]
|
|
8013e2c: 6039 str r1, [r7, #0]
|
|
struct tcp_pcb_listen *lpcb;
|
|
|
|
if (!ip_addr_isany(old_addr)) {
|
|
8013e2e: 687b ldr r3, [r7, #4]
|
|
8013e30: 2b00 cmp r3, #0
|
|
8013e32: d02a beq.n 8013e8a <tcp_netif_ip_addr_changed+0x66>
|
|
8013e34: 687b ldr r3, [r7, #4]
|
|
8013e36: 681b ldr r3, [r3, #0]
|
|
8013e38: 2b00 cmp r3, #0
|
|
8013e3a: d026 beq.n 8013e8a <tcp_netif_ip_addr_changed+0x66>
|
|
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs);
|
|
8013e3c: 4b15 ldr r3, [pc, #84] ; (8013e94 <tcp_netif_ip_addr_changed+0x70>)
|
|
8013e3e: 681b ldr r3, [r3, #0]
|
|
8013e40: 4619 mov r1, r3
|
|
8013e42: 6878 ldr r0, [r7, #4]
|
|
8013e44: f7ff ffbc bl 8013dc0 <tcp_netif_ip_addr_changed_pcblist>
|
|
tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs);
|
|
8013e48: 4b13 ldr r3, [pc, #76] ; (8013e98 <tcp_netif_ip_addr_changed+0x74>)
|
|
8013e4a: 681b ldr r3, [r3, #0]
|
|
8013e4c: 4619 mov r1, r3
|
|
8013e4e: 6878 ldr r0, [r7, #4]
|
|
8013e50: f7ff ffb6 bl 8013dc0 <tcp_netif_ip_addr_changed_pcblist>
|
|
|
|
if (!ip_addr_isany(new_addr)) {
|
|
8013e54: 683b ldr r3, [r7, #0]
|
|
8013e56: 2b00 cmp r3, #0
|
|
8013e58: d017 beq.n 8013e8a <tcp_netif_ip_addr_changed+0x66>
|
|
8013e5a: 683b ldr r3, [r7, #0]
|
|
8013e5c: 681b ldr r3, [r3, #0]
|
|
8013e5e: 2b00 cmp r3, #0
|
|
8013e60: d013 beq.n 8013e8a <tcp_netif_ip_addr_changed+0x66>
|
|
/* PCB bound to current local interface address? */
|
|
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
|
|
8013e62: 4b0e ldr r3, [pc, #56] ; (8013e9c <tcp_netif_ip_addr_changed+0x78>)
|
|
8013e64: 681b ldr r3, [r3, #0]
|
|
8013e66: 60fb str r3, [r7, #12]
|
|
8013e68: e00c b.n 8013e84 <tcp_netif_ip_addr_changed+0x60>
|
|
/* PCB bound to current local interface address? */
|
|
if (ip_addr_cmp(&lpcb->local_ip, old_addr)) {
|
|
8013e6a: 68fb ldr r3, [r7, #12]
|
|
8013e6c: 681a ldr r2, [r3, #0]
|
|
8013e6e: 687b ldr r3, [r7, #4]
|
|
8013e70: 681b ldr r3, [r3, #0]
|
|
8013e72: 429a cmp r2, r3
|
|
8013e74: d103 bne.n 8013e7e <tcp_netif_ip_addr_changed+0x5a>
|
|
/* The PCB is listening to the old ipaddr and
|
|
* is set to listen to the new one instead */
|
|
ip_addr_copy(lpcb->local_ip, *new_addr);
|
|
8013e76: 683b ldr r3, [r7, #0]
|
|
8013e78: 681a ldr r2, [r3, #0]
|
|
8013e7a: 68fb ldr r3, [r7, #12]
|
|
8013e7c: 601a str r2, [r3, #0]
|
|
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
|
|
8013e7e: 68fb ldr r3, [r7, #12]
|
|
8013e80: 68db ldr r3, [r3, #12]
|
|
8013e82: 60fb str r3, [r7, #12]
|
|
8013e84: 68fb ldr r3, [r7, #12]
|
|
8013e86: 2b00 cmp r3, #0
|
|
8013e88: d1ef bne.n 8013e6a <tcp_netif_ip_addr_changed+0x46>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8013e8a: bf00 nop
|
|
8013e8c: 3710 adds r7, #16
|
|
8013e8e: 46bd mov sp, r7
|
|
8013e90: bd80 pop {r7, pc}
|
|
8013e92: bf00 nop
|
|
8013e94: 2000f7fc .word 0x2000f7fc
|
|
8013e98: 2000f808 .word 0x2000f808
|
|
8013e9c: 2000f804 .word 0x2000f804
|
|
|
|
08013ea0 <tcp_free_ooseq>:
|
|
|
|
#if TCP_QUEUE_OOSEQ
|
|
/* Free all ooseq pbufs (and possibly reset SACK state) */
|
|
void
|
|
tcp_free_ooseq(struct tcp_pcb *pcb)
|
|
{
|
|
8013ea0: b580 push {r7, lr}
|
|
8013ea2: b082 sub sp, #8
|
|
8013ea4: af00 add r7, sp, #0
|
|
8013ea6: 6078 str r0, [r7, #4]
|
|
if (pcb->ooseq) {
|
|
8013ea8: 687b ldr r3, [r7, #4]
|
|
8013eaa: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8013eac: 2b00 cmp r3, #0
|
|
8013eae: d007 beq.n 8013ec0 <tcp_free_ooseq+0x20>
|
|
tcp_segs_free(pcb->ooseq);
|
|
8013eb0: 687b ldr r3, [r7, #4]
|
|
8013eb2: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8013eb4: 4618 mov r0, r3
|
|
8013eb6: f7ff fc3f bl 8013738 <tcp_segs_free>
|
|
pcb->ooseq = NULL;
|
|
8013eba: 687b ldr r3, [r7, #4]
|
|
8013ebc: 2200 movs r2, #0
|
|
8013ebe: 675a str r2, [r3, #116] ; 0x74
|
|
#if LWIP_TCP_SACK_OUT
|
|
memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks));
|
|
#endif /* LWIP_TCP_SACK_OUT */
|
|
}
|
|
}
|
|
8013ec0: bf00 nop
|
|
8013ec2: 3708 adds r7, #8
|
|
8013ec4: 46bd mov sp, r7
|
|
8013ec6: bd80 pop {r7, pc}
|
|
|
|
08013ec8 <tcp_input>:
|
|
* @param p received TCP segment to process (p->payload pointing to the TCP header)
|
|
* @param inp network interface on which this segment was received
|
|
*/
|
|
void
|
|
tcp_input(struct pbuf *p, struct netif *inp)
|
|
{
|
|
8013ec8: b590 push {r4, r7, lr}
|
|
8013eca: b08d sub sp, #52 ; 0x34
|
|
8013ecc: af04 add r7, sp, #16
|
|
8013ece: 6078 str r0, [r7, #4]
|
|
8013ed0: 6039 str r1, [r7, #0]
|
|
u8_t hdrlen_bytes;
|
|
err_t err;
|
|
|
|
LWIP_UNUSED_ARG(inp);
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL);
|
|
8013ed2: 687b ldr r3, [r7, #4]
|
|
8013ed4: 2b00 cmp r3, #0
|
|
8013ed6: d105 bne.n 8013ee4 <tcp_input+0x1c>
|
|
8013ed8: 4b9b ldr r3, [pc, #620] ; (8014148 <tcp_input+0x280>)
|
|
8013eda: 2283 movs r2, #131 ; 0x83
|
|
8013edc: 499b ldr r1, [pc, #620] ; (801414c <tcp_input+0x284>)
|
|
8013ede: 489c ldr r0, [pc, #624] ; (8014150 <tcp_input+0x288>)
|
|
8013ee0: f008 feea bl 801ccb8 <iprintf>
|
|
PERF_START;
|
|
|
|
TCP_STATS_INC(tcp.recv);
|
|
MIB2_STATS_INC(mib2.tcpinsegs);
|
|
|
|
tcphdr = (struct tcp_hdr *)p->payload;
|
|
8013ee4: 687b ldr r3, [r7, #4]
|
|
8013ee6: 685b ldr r3, [r3, #4]
|
|
8013ee8: 4a9a ldr r2, [pc, #616] ; (8014154 <tcp_input+0x28c>)
|
|
8013eea: 6013 str r3, [r2, #0]
|
|
#if TCP_INPUT_DEBUG
|
|
tcp_debug_print(tcphdr);
|
|
#endif
|
|
|
|
/* Check that TCP header fits in payload */
|
|
if (p->len < TCP_HLEN) {
|
|
8013eec: 687b ldr r3, [r7, #4]
|
|
8013eee: 895b ldrh r3, [r3, #10]
|
|
8013ef0: 2b13 cmp r3, #19
|
|
8013ef2: f240 83c4 bls.w 801467e <tcp_input+0x7b6>
|
|
TCP_STATS_INC(tcp.lenerr);
|
|
goto dropped;
|
|
}
|
|
|
|
/* Don't even process incoming broadcasts/multicasts. */
|
|
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
|
|
8013ef6: 4b98 ldr r3, [pc, #608] ; (8014158 <tcp_input+0x290>)
|
|
8013ef8: 695a ldr r2, [r3, #20]
|
|
8013efa: 4b97 ldr r3, [pc, #604] ; (8014158 <tcp_input+0x290>)
|
|
8013efc: 681b ldr r3, [r3, #0]
|
|
8013efe: 4619 mov r1, r3
|
|
8013f00: 4610 mov r0, r2
|
|
8013f02: f007 fe17 bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
8013f06: 4603 mov r3, r0
|
|
8013f08: 2b00 cmp r3, #0
|
|
8013f0a: f040 83ba bne.w 8014682 <tcp_input+0x7ba>
|
|
ip_addr_ismulticast(ip_current_dest_addr())) {
|
|
8013f0e: 4b92 ldr r3, [pc, #584] ; (8014158 <tcp_input+0x290>)
|
|
8013f10: 695b ldr r3, [r3, #20]
|
|
8013f12: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) ||
|
|
8013f16: 2be0 cmp r3, #224 ; 0xe0
|
|
8013f18: f000 83b3 beq.w 8014682 <tcp_input+0x7ba>
|
|
}
|
|
}
|
|
#endif /* CHECKSUM_CHECK_TCP */
|
|
|
|
/* sanity-check header length */
|
|
hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr);
|
|
8013f1c: 4b8d ldr r3, [pc, #564] ; (8014154 <tcp_input+0x28c>)
|
|
8013f1e: 681b ldr r3, [r3, #0]
|
|
8013f20: 899b ldrh r3, [r3, #12]
|
|
8013f22: b29b uxth r3, r3
|
|
8013f24: 4618 mov r0, r3
|
|
8013f26: f7fc fde3 bl 8010af0 <lwip_htons>
|
|
8013f2a: 4603 mov r3, r0
|
|
8013f2c: 0b1b lsrs r3, r3, #12
|
|
8013f2e: b29b uxth r3, r3
|
|
8013f30: b2db uxtb r3, r3
|
|
8013f32: 009b lsls r3, r3, #2
|
|
8013f34: 74bb strb r3, [r7, #18]
|
|
if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) {
|
|
8013f36: 7cbb ldrb r3, [r7, #18]
|
|
8013f38: 2b13 cmp r3, #19
|
|
8013f3a: f240 83a2 bls.w 8014682 <tcp_input+0x7ba>
|
|
8013f3e: 7cbb ldrb r3, [r7, #18]
|
|
8013f40: b29a uxth r2, r3
|
|
8013f42: 687b ldr r3, [r7, #4]
|
|
8013f44: 891b ldrh r3, [r3, #8]
|
|
8013f46: 429a cmp r2, r3
|
|
8013f48: f200 839b bhi.w 8014682 <tcp_input+0x7ba>
|
|
goto dropped;
|
|
}
|
|
|
|
/* Move the payload pointer in the pbuf so that it points to the
|
|
TCP data instead of the TCP header. */
|
|
tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN);
|
|
8013f4c: 7cbb ldrb r3, [r7, #18]
|
|
8013f4e: b29b uxth r3, r3
|
|
8013f50: 3b14 subs r3, #20
|
|
8013f52: b29a uxth r2, r3
|
|
8013f54: 4b81 ldr r3, [pc, #516] ; (801415c <tcp_input+0x294>)
|
|
8013f56: 801a strh r2, [r3, #0]
|
|
tcphdr_opt2 = NULL;
|
|
8013f58: 4b81 ldr r3, [pc, #516] ; (8014160 <tcp_input+0x298>)
|
|
8013f5a: 2200 movs r2, #0
|
|
8013f5c: 601a str r2, [r3, #0]
|
|
if (p->len >= hdrlen_bytes) {
|
|
8013f5e: 687b ldr r3, [r7, #4]
|
|
8013f60: 895a ldrh r2, [r3, #10]
|
|
8013f62: 7cbb ldrb r3, [r7, #18]
|
|
8013f64: b29b uxth r3, r3
|
|
8013f66: 429a cmp r2, r3
|
|
8013f68: d309 bcc.n 8013f7e <tcp_input+0xb6>
|
|
/* all options are in the first pbuf */
|
|
tcphdr_opt1len = tcphdr_optlen;
|
|
8013f6a: 4b7c ldr r3, [pc, #496] ; (801415c <tcp_input+0x294>)
|
|
8013f6c: 881a ldrh r2, [r3, #0]
|
|
8013f6e: 4b7d ldr r3, [pc, #500] ; (8014164 <tcp_input+0x29c>)
|
|
8013f70: 801a strh r2, [r3, #0]
|
|
pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */
|
|
8013f72: 7cbb ldrb r3, [r7, #18]
|
|
8013f74: 4619 mov r1, r3
|
|
8013f76: 6878 ldr r0, [r7, #4]
|
|
8013f78: f7fe f8e8 bl 801214c <pbuf_remove_header>
|
|
8013f7c: e04e b.n 801401c <tcp_input+0x154>
|
|
} else {
|
|
u16_t opt2len;
|
|
/* TCP header fits into first pbuf, options don't - data is in the next pbuf */
|
|
/* there must be a next pbuf, due to hdrlen_bytes sanity check above */
|
|
LWIP_ASSERT("p->next != NULL", p->next != NULL);
|
|
8013f7e: 687b ldr r3, [r7, #4]
|
|
8013f80: 681b ldr r3, [r3, #0]
|
|
8013f82: 2b00 cmp r3, #0
|
|
8013f84: d105 bne.n 8013f92 <tcp_input+0xca>
|
|
8013f86: 4b70 ldr r3, [pc, #448] ; (8014148 <tcp_input+0x280>)
|
|
8013f88: 22c2 movs r2, #194 ; 0xc2
|
|
8013f8a: 4977 ldr r1, [pc, #476] ; (8014168 <tcp_input+0x2a0>)
|
|
8013f8c: 4870 ldr r0, [pc, #448] ; (8014150 <tcp_input+0x288>)
|
|
8013f8e: f008 fe93 bl 801ccb8 <iprintf>
|
|
|
|
/* advance over the TCP header (cannot fail) */
|
|
pbuf_remove_header(p, TCP_HLEN);
|
|
8013f92: 2114 movs r1, #20
|
|
8013f94: 6878 ldr r0, [r7, #4]
|
|
8013f96: f7fe f8d9 bl 801214c <pbuf_remove_header>
|
|
|
|
/* determine how long the first and second parts of the options are */
|
|
tcphdr_opt1len = p->len;
|
|
8013f9a: 687b ldr r3, [r7, #4]
|
|
8013f9c: 895a ldrh r2, [r3, #10]
|
|
8013f9e: 4b71 ldr r3, [pc, #452] ; (8014164 <tcp_input+0x29c>)
|
|
8013fa0: 801a strh r2, [r3, #0]
|
|
opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len);
|
|
8013fa2: 4b6e ldr r3, [pc, #440] ; (801415c <tcp_input+0x294>)
|
|
8013fa4: 881a ldrh r2, [r3, #0]
|
|
8013fa6: 4b6f ldr r3, [pc, #444] ; (8014164 <tcp_input+0x29c>)
|
|
8013fa8: 881b ldrh r3, [r3, #0]
|
|
8013faa: 1ad3 subs r3, r2, r3
|
|
8013fac: 823b strh r3, [r7, #16]
|
|
|
|
/* options continue in the next pbuf: set p to zero length and hide the
|
|
options in the next pbuf (adjusting p->tot_len) */
|
|
pbuf_remove_header(p, tcphdr_opt1len);
|
|
8013fae: 4b6d ldr r3, [pc, #436] ; (8014164 <tcp_input+0x29c>)
|
|
8013fb0: 881b ldrh r3, [r3, #0]
|
|
8013fb2: 4619 mov r1, r3
|
|
8013fb4: 6878 ldr r0, [r7, #4]
|
|
8013fb6: f7fe f8c9 bl 801214c <pbuf_remove_header>
|
|
|
|
/* check that the options fit in the second pbuf */
|
|
if (opt2len > p->next->len) {
|
|
8013fba: 687b ldr r3, [r7, #4]
|
|
8013fbc: 681b ldr r3, [r3, #0]
|
|
8013fbe: 895b ldrh r3, [r3, #10]
|
|
8013fc0: 8a3a ldrh r2, [r7, #16]
|
|
8013fc2: 429a cmp r2, r3
|
|
8013fc4: f200 835f bhi.w 8014686 <tcp_input+0x7be>
|
|
TCP_STATS_INC(tcp.lenerr);
|
|
goto dropped;
|
|
}
|
|
|
|
/* remember the pointer to the second part of the options */
|
|
tcphdr_opt2 = (u8_t *)p->next->payload;
|
|
8013fc8: 687b ldr r3, [r7, #4]
|
|
8013fca: 681b ldr r3, [r3, #0]
|
|
8013fcc: 685b ldr r3, [r3, #4]
|
|
8013fce: 4a64 ldr r2, [pc, #400] ; (8014160 <tcp_input+0x298>)
|
|
8013fd0: 6013 str r3, [r2, #0]
|
|
|
|
/* advance p->next to point after the options, and manually
|
|
adjust p->tot_len to keep it consistent with the changed p->next */
|
|
pbuf_remove_header(p->next, opt2len);
|
|
8013fd2: 687b ldr r3, [r7, #4]
|
|
8013fd4: 681b ldr r3, [r3, #0]
|
|
8013fd6: 8a3a ldrh r2, [r7, #16]
|
|
8013fd8: 4611 mov r1, r2
|
|
8013fda: 4618 mov r0, r3
|
|
8013fdc: f7fe f8b6 bl 801214c <pbuf_remove_header>
|
|
p->tot_len = (u16_t)(p->tot_len - opt2len);
|
|
8013fe0: 687b ldr r3, [r7, #4]
|
|
8013fe2: 891a ldrh r2, [r3, #8]
|
|
8013fe4: 8a3b ldrh r3, [r7, #16]
|
|
8013fe6: 1ad3 subs r3, r2, r3
|
|
8013fe8: b29a uxth r2, r3
|
|
8013fea: 687b ldr r3, [r7, #4]
|
|
8013fec: 811a strh r2, [r3, #8]
|
|
|
|
LWIP_ASSERT("p->len == 0", p->len == 0);
|
|
8013fee: 687b ldr r3, [r7, #4]
|
|
8013ff0: 895b ldrh r3, [r3, #10]
|
|
8013ff2: 2b00 cmp r3, #0
|
|
8013ff4: d005 beq.n 8014002 <tcp_input+0x13a>
|
|
8013ff6: 4b54 ldr r3, [pc, #336] ; (8014148 <tcp_input+0x280>)
|
|
8013ff8: 22df movs r2, #223 ; 0xdf
|
|
8013ffa: 495c ldr r1, [pc, #368] ; (801416c <tcp_input+0x2a4>)
|
|
8013ffc: 4854 ldr r0, [pc, #336] ; (8014150 <tcp_input+0x288>)
|
|
8013ffe: f008 fe5b bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len);
|
|
8014002: 687b ldr r3, [r7, #4]
|
|
8014004: 891a ldrh r2, [r3, #8]
|
|
8014006: 687b ldr r3, [r7, #4]
|
|
8014008: 681b ldr r3, [r3, #0]
|
|
801400a: 891b ldrh r3, [r3, #8]
|
|
801400c: 429a cmp r2, r3
|
|
801400e: d005 beq.n 801401c <tcp_input+0x154>
|
|
8014010: 4b4d ldr r3, [pc, #308] ; (8014148 <tcp_input+0x280>)
|
|
8014012: 22e0 movs r2, #224 ; 0xe0
|
|
8014014: 4956 ldr r1, [pc, #344] ; (8014170 <tcp_input+0x2a8>)
|
|
8014016: 484e ldr r0, [pc, #312] ; (8014150 <tcp_input+0x288>)
|
|
8014018: f008 fe4e bl 801ccb8 <iprintf>
|
|
}
|
|
|
|
/* Convert fields in TCP header to host byte order. */
|
|
tcphdr->src = lwip_ntohs(tcphdr->src);
|
|
801401c: 4b4d ldr r3, [pc, #308] ; (8014154 <tcp_input+0x28c>)
|
|
801401e: 681b ldr r3, [r3, #0]
|
|
8014020: 881b ldrh r3, [r3, #0]
|
|
8014022: b29a uxth r2, r3
|
|
8014024: 4b4b ldr r3, [pc, #300] ; (8014154 <tcp_input+0x28c>)
|
|
8014026: 681c ldr r4, [r3, #0]
|
|
8014028: 4610 mov r0, r2
|
|
801402a: f7fc fd61 bl 8010af0 <lwip_htons>
|
|
801402e: 4603 mov r3, r0
|
|
8014030: 8023 strh r3, [r4, #0]
|
|
tcphdr->dest = lwip_ntohs(tcphdr->dest);
|
|
8014032: 4b48 ldr r3, [pc, #288] ; (8014154 <tcp_input+0x28c>)
|
|
8014034: 681b ldr r3, [r3, #0]
|
|
8014036: 885b ldrh r3, [r3, #2]
|
|
8014038: b29a uxth r2, r3
|
|
801403a: 4b46 ldr r3, [pc, #280] ; (8014154 <tcp_input+0x28c>)
|
|
801403c: 681c ldr r4, [r3, #0]
|
|
801403e: 4610 mov r0, r2
|
|
8014040: f7fc fd56 bl 8010af0 <lwip_htons>
|
|
8014044: 4603 mov r3, r0
|
|
8014046: 8063 strh r3, [r4, #2]
|
|
seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno);
|
|
8014048: 4b42 ldr r3, [pc, #264] ; (8014154 <tcp_input+0x28c>)
|
|
801404a: 681b ldr r3, [r3, #0]
|
|
801404c: 685a ldr r2, [r3, #4]
|
|
801404e: 4b41 ldr r3, [pc, #260] ; (8014154 <tcp_input+0x28c>)
|
|
8014050: 681c ldr r4, [r3, #0]
|
|
8014052: 4610 mov r0, r2
|
|
8014054: f7fc fd61 bl 8010b1a <lwip_htonl>
|
|
8014058: 4603 mov r3, r0
|
|
801405a: 6063 str r3, [r4, #4]
|
|
801405c: 6863 ldr r3, [r4, #4]
|
|
801405e: 4a45 ldr r2, [pc, #276] ; (8014174 <tcp_input+0x2ac>)
|
|
8014060: 6013 str r3, [r2, #0]
|
|
ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno);
|
|
8014062: 4b3c ldr r3, [pc, #240] ; (8014154 <tcp_input+0x28c>)
|
|
8014064: 681b ldr r3, [r3, #0]
|
|
8014066: 689a ldr r2, [r3, #8]
|
|
8014068: 4b3a ldr r3, [pc, #232] ; (8014154 <tcp_input+0x28c>)
|
|
801406a: 681c ldr r4, [r3, #0]
|
|
801406c: 4610 mov r0, r2
|
|
801406e: f7fc fd54 bl 8010b1a <lwip_htonl>
|
|
8014072: 4603 mov r3, r0
|
|
8014074: 60a3 str r3, [r4, #8]
|
|
8014076: 68a3 ldr r3, [r4, #8]
|
|
8014078: 4a3f ldr r2, [pc, #252] ; (8014178 <tcp_input+0x2b0>)
|
|
801407a: 6013 str r3, [r2, #0]
|
|
tcphdr->wnd = lwip_ntohs(tcphdr->wnd);
|
|
801407c: 4b35 ldr r3, [pc, #212] ; (8014154 <tcp_input+0x28c>)
|
|
801407e: 681b ldr r3, [r3, #0]
|
|
8014080: 89db ldrh r3, [r3, #14]
|
|
8014082: b29a uxth r2, r3
|
|
8014084: 4b33 ldr r3, [pc, #204] ; (8014154 <tcp_input+0x28c>)
|
|
8014086: 681c ldr r4, [r3, #0]
|
|
8014088: 4610 mov r0, r2
|
|
801408a: f7fc fd31 bl 8010af0 <lwip_htons>
|
|
801408e: 4603 mov r3, r0
|
|
8014090: 81e3 strh r3, [r4, #14]
|
|
|
|
flags = TCPH_FLAGS(tcphdr);
|
|
8014092: 4b30 ldr r3, [pc, #192] ; (8014154 <tcp_input+0x28c>)
|
|
8014094: 681b ldr r3, [r3, #0]
|
|
8014096: 899b ldrh r3, [r3, #12]
|
|
8014098: b29b uxth r3, r3
|
|
801409a: 4618 mov r0, r3
|
|
801409c: f7fc fd28 bl 8010af0 <lwip_htons>
|
|
80140a0: 4603 mov r3, r0
|
|
80140a2: b2db uxtb r3, r3
|
|
80140a4: f003 033f and.w r3, r3, #63 ; 0x3f
|
|
80140a8: b2da uxtb r2, r3
|
|
80140aa: 4b34 ldr r3, [pc, #208] ; (801417c <tcp_input+0x2b4>)
|
|
80140ac: 701a strb r2, [r3, #0]
|
|
tcplen = p->tot_len;
|
|
80140ae: 687b ldr r3, [r7, #4]
|
|
80140b0: 891a ldrh r2, [r3, #8]
|
|
80140b2: 4b33 ldr r3, [pc, #204] ; (8014180 <tcp_input+0x2b8>)
|
|
80140b4: 801a strh r2, [r3, #0]
|
|
if (flags & (TCP_FIN | TCP_SYN)) {
|
|
80140b6: 4b31 ldr r3, [pc, #196] ; (801417c <tcp_input+0x2b4>)
|
|
80140b8: 781b ldrb r3, [r3, #0]
|
|
80140ba: f003 0303 and.w r3, r3, #3
|
|
80140be: 2b00 cmp r3, #0
|
|
80140c0: d00c beq.n 80140dc <tcp_input+0x214>
|
|
tcplen++;
|
|
80140c2: 4b2f ldr r3, [pc, #188] ; (8014180 <tcp_input+0x2b8>)
|
|
80140c4: 881b ldrh r3, [r3, #0]
|
|
80140c6: 3301 adds r3, #1
|
|
80140c8: b29a uxth r2, r3
|
|
80140ca: 4b2d ldr r3, [pc, #180] ; (8014180 <tcp_input+0x2b8>)
|
|
80140cc: 801a strh r2, [r3, #0]
|
|
if (tcplen < p->tot_len) {
|
|
80140ce: 687b ldr r3, [r7, #4]
|
|
80140d0: 891a ldrh r2, [r3, #8]
|
|
80140d2: 4b2b ldr r3, [pc, #172] ; (8014180 <tcp_input+0x2b8>)
|
|
80140d4: 881b ldrh r3, [r3, #0]
|
|
80140d6: 429a cmp r2, r3
|
|
80140d8: f200 82d7 bhi.w 801468a <tcp_input+0x7c2>
|
|
}
|
|
}
|
|
|
|
/* Demultiplex an incoming segment. First, we check if it is destined
|
|
for an active connection. */
|
|
prev = NULL;
|
|
80140dc: 2300 movs r3, #0
|
|
80140de: 61bb str r3, [r7, #24]
|
|
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
80140e0: 4b28 ldr r3, [pc, #160] ; (8014184 <tcp_input+0x2bc>)
|
|
80140e2: 681b ldr r3, [r3, #0]
|
|
80140e4: 61fb str r3, [r7, #28]
|
|
80140e6: e09d b.n 8014224 <tcp_input+0x35c>
|
|
LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED);
|
|
80140e8: 69fb ldr r3, [r7, #28]
|
|
80140ea: 7d1b ldrb r3, [r3, #20]
|
|
80140ec: 2b00 cmp r3, #0
|
|
80140ee: d105 bne.n 80140fc <tcp_input+0x234>
|
|
80140f0: 4b15 ldr r3, [pc, #84] ; (8014148 <tcp_input+0x280>)
|
|
80140f2: 22fb movs r2, #251 ; 0xfb
|
|
80140f4: 4924 ldr r1, [pc, #144] ; (8014188 <tcp_input+0x2c0>)
|
|
80140f6: 4816 ldr r0, [pc, #88] ; (8014150 <tcp_input+0x288>)
|
|
80140f8: f008 fdde bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT);
|
|
80140fc: 69fb ldr r3, [r7, #28]
|
|
80140fe: 7d1b ldrb r3, [r3, #20]
|
|
8014100: 2b0a cmp r3, #10
|
|
8014102: d105 bne.n 8014110 <tcp_input+0x248>
|
|
8014104: 4b10 ldr r3, [pc, #64] ; (8014148 <tcp_input+0x280>)
|
|
8014106: 22fc movs r2, #252 ; 0xfc
|
|
8014108: 4920 ldr r1, [pc, #128] ; (801418c <tcp_input+0x2c4>)
|
|
801410a: 4811 ldr r0, [pc, #68] ; (8014150 <tcp_input+0x288>)
|
|
801410c: f008 fdd4 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN);
|
|
8014110: 69fb ldr r3, [r7, #28]
|
|
8014112: 7d1b ldrb r3, [r3, #20]
|
|
8014114: 2b01 cmp r3, #1
|
|
8014116: d105 bne.n 8014124 <tcp_input+0x25c>
|
|
8014118: 4b0b ldr r3, [pc, #44] ; (8014148 <tcp_input+0x280>)
|
|
801411a: 22fd movs r2, #253 ; 0xfd
|
|
801411c: 491c ldr r1, [pc, #112] ; (8014190 <tcp_input+0x2c8>)
|
|
801411e: 480c ldr r0, [pc, #48] ; (8014150 <tcp_input+0x288>)
|
|
8014120: f008 fdca bl 801ccb8 <iprintf>
|
|
|
|
/* check if PCB is bound to specific netif */
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
8014124: 69fb ldr r3, [r7, #28]
|
|
8014126: 7a1b ldrb r3, [r3, #8]
|
|
8014128: 2b00 cmp r3, #0
|
|
801412a: d033 beq.n 8014194 <tcp_input+0x2cc>
|
|
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
|
|
801412c: 69fb ldr r3, [r7, #28]
|
|
801412e: 7a1a ldrb r2, [r3, #8]
|
|
8014130: 4b09 ldr r3, [pc, #36] ; (8014158 <tcp_input+0x290>)
|
|
8014132: 685b ldr r3, [r3, #4]
|
|
8014134: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8014138: 3301 adds r3, #1
|
|
801413a: b2db uxtb r3, r3
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
801413c: 429a cmp r2, r3
|
|
801413e: d029 beq.n 8014194 <tcp_input+0x2cc>
|
|
prev = pcb;
|
|
8014140: 69fb ldr r3, [r7, #28]
|
|
8014142: 61bb str r3, [r7, #24]
|
|
continue;
|
|
8014144: e06b b.n 801421e <tcp_input+0x356>
|
|
8014146: bf00 nop
|
|
8014148: 0801f2b0 .word 0x0801f2b0
|
|
801414c: 0801f2e4 .word 0x0801f2e4
|
|
8014150: 0801f2fc .word 0x0801f2fc
|
|
8014154: 2000873c .word 0x2000873c
|
|
8014158: 2000c0c8 .word 0x2000c0c8
|
|
801415c: 20008740 .word 0x20008740
|
|
8014160: 20008744 .word 0x20008744
|
|
8014164: 20008742 .word 0x20008742
|
|
8014168: 0801f324 .word 0x0801f324
|
|
801416c: 0801f334 .word 0x0801f334
|
|
8014170: 0801f340 .word 0x0801f340
|
|
8014174: 2000874c .word 0x2000874c
|
|
8014178: 20008750 .word 0x20008750
|
|
801417c: 20008758 .word 0x20008758
|
|
8014180: 20008756 .word 0x20008756
|
|
8014184: 2000f7fc .word 0x2000f7fc
|
|
8014188: 0801f360 .word 0x0801f360
|
|
801418c: 0801f388 .word 0x0801f388
|
|
8014190: 0801f3b4 .word 0x0801f3b4
|
|
}
|
|
|
|
if (pcb->remote_port == tcphdr->src &&
|
|
8014194: 69fb ldr r3, [r7, #28]
|
|
8014196: 8b1a ldrh r2, [r3, #24]
|
|
8014198: 4b94 ldr r3, [pc, #592] ; (80143ec <tcp_input+0x524>)
|
|
801419a: 681b ldr r3, [r3, #0]
|
|
801419c: 881b ldrh r3, [r3, #0]
|
|
801419e: b29b uxth r3, r3
|
|
80141a0: 429a cmp r2, r3
|
|
80141a2: d13a bne.n 801421a <tcp_input+0x352>
|
|
pcb->local_port == tcphdr->dest &&
|
|
80141a4: 69fb ldr r3, [r7, #28]
|
|
80141a6: 8ada ldrh r2, [r3, #22]
|
|
80141a8: 4b90 ldr r3, [pc, #576] ; (80143ec <tcp_input+0x524>)
|
|
80141aa: 681b ldr r3, [r3, #0]
|
|
80141ac: 885b ldrh r3, [r3, #2]
|
|
80141ae: b29b uxth r3, r3
|
|
if (pcb->remote_port == tcphdr->src &&
|
|
80141b0: 429a cmp r2, r3
|
|
80141b2: d132 bne.n 801421a <tcp_input+0x352>
|
|
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
|
|
80141b4: 69fb ldr r3, [r7, #28]
|
|
80141b6: 685a ldr r2, [r3, #4]
|
|
80141b8: 4b8d ldr r3, [pc, #564] ; (80143f0 <tcp_input+0x528>)
|
|
80141ba: 691b ldr r3, [r3, #16]
|
|
pcb->local_port == tcphdr->dest &&
|
|
80141bc: 429a cmp r2, r3
|
|
80141be: d12c bne.n 801421a <tcp_input+0x352>
|
|
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
|
|
80141c0: 69fb ldr r3, [r7, #28]
|
|
80141c2: 681a ldr r2, [r3, #0]
|
|
80141c4: 4b8a ldr r3, [pc, #552] ; (80143f0 <tcp_input+0x528>)
|
|
80141c6: 695b ldr r3, [r3, #20]
|
|
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
|
|
80141c8: 429a cmp r2, r3
|
|
80141ca: d126 bne.n 801421a <tcp_input+0x352>
|
|
/* Move this PCB to the front of the list so that subsequent
|
|
lookups will be faster (we exploit locality in TCP segment
|
|
arrivals). */
|
|
LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb);
|
|
80141cc: 69fb ldr r3, [r7, #28]
|
|
80141ce: 68db ldr r3, [r3, #12]
|
|
80141d0: 69fa ldr r2, [r7, #28]
|
|
80141d2: 429a cmp r2, r3
|
|
80141d4: d106 bne.n 80141e4 <tcp_input+0x31c>
|
|
80141d6: 4b87 ldr r3, [pc, #540] ; (80143f4 <tcp_input+0x52c>)
|
|
80141d8: f240 120d movw r2, #269 ; 0x10d
|
|
80141dc: 4986 ldr r1, [pc, #536] ; (80143f8 <tcp_input+0x530>)
|
|
80141de: 4887 ldr r0, [pc, #540] ; (80143fc <tcp_input+0x534>)
|
|
80141e0: f008 fd6a bl 801ccb8 <iprintf>
|
|
if (prev != NULL) {
|
|
80141e4: 69bb ldr r3, [r7, #24]
|
|
80141e6: 2b00 cmp r3, #0
|
|
80141e8: d00a beq.n 8014200 <tcp_input+0x338>
|
|
prev->next = pcb->next;
|
|
80141ea: 69fb ldr r3, [r7, #28]
|
|
80141ec: 68da ldr r2, [r3, #12]
|
|
80141ee: 69bb ldr r3, [r7, #24]
|
|
80141f0: 60da str r2, [r3, #12]
|
|
pcb->next = tcp_active_pcbs;
|
|
80141f2: 4b83 ldr r3, [pc, #524] ; (8014400 <tcp_input+0x538>)
|
|
80141f4: 681a ldr r2, [r3, #0]
|
|
80141f6: 69fb ldr r3, [r7, #28]
|
|
80141f8: 60da str r2, [r3, #12]
|
|
tcp_active_pcbs = pcb;
|
|
80141fa: 4a81 ldr r2, [pc, #516] ; (8014400 <tcp_input+0x538>)
|
|
80141fc: 69fb ldr r3, [r7, #28]
|
|
80141fe: 6013 str r3, [r2, #0]
|
|
} else {
|
|
TCP_STATS_INC(tcp.cachehit);
|
|
}
|
|
LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb);
|
|
8014200: 69fb ldr r3, [r7, #28]
|
|
8014202: 68db ldr r3, [r3, #12]
|
|
8014204: 69fa ldr r2, [r7, #28]
|
|
8014206: 429a cmp r2, r3
|
|
8014208: d111 bne.n 801422e <tcp_input+0x366>
|
|
801420a: 4b7a ldr r3, [pc, #488] ; (80143f4 <tcp_input+0x52c>)
|
|
801420c: f240 1215 movw r2, #277 ; 0x115
|
|
8014210: 497c ldr r1, [pc, #496] ; (8014404 <tcp_input+0x53c>)
|
|
8014212: 487a ldr r0, [pc, #488] ; (80143fc <tcp_input+0x534>)
|
|
8014214: f008 fd50 bl 801ccb8 <iprintf>
|
|
break;
|
|
8014218: e009 b.n 801422e <tcp_input+0x366>
|
|
}
|
|
prev = pcb;
|
|
801421a: 69fb ldr r3, [r7, #28]
|
|
801421c: 61bb str r3, [r7, #24]
|
|
for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
801421e: 69fb ldr r3, [r7, #28]
|
|
8014220: 68db ldr r3, [r3, #12]
|
|
8014222: 61fb str r3, [r7, #28]
|
|
8014224: 69fb ldr r3, [r7, #28]
|
|
8014226: 2b00 cmp r3, #0
|
|
8014228: f47f af5e bne.w 80140e8 <tcp_input+0x220>
|
|
801422c: e000 b.n 8014230 <tcp_input+0x368>
|
|
break;
|
|
801422e: bf00 nop
|
|
}
|
|
|
|
if (pcb == NULL) {
|
|
8014230: 69fb ldr r3, [r7, #28]
|
|
8014232: 2b00 cmp r3, #0
|
|
8014234: f040 8095 bne.w 8014362 <tcp_input+0x49a>
|
|
/* If it did not go to an active connection, we check the connections
|
|
in the TIME-WAIT state. */
|
|
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8014238: 4b73 ldr r3, [pc, #460] ; (8014408 <tcp_input+0x540>)
|
|
801423a: 681b ldr r3, [r3, #0]
|
|
801423c: 61fb str r3, [r7, #28]
|
|
801423e: e03f b.n 80142c0 <tcp_input+0x3f8>
|
|
LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT);
|
|
8014240: 69fb ldr r3, [r7, #28]
|
|
8014242: 7d1b ldrb r3, [r3, #20]
|
|
8014244: 2b0a cmp r3, #10
|
|
8014246: d006 beq.n 8014256 <tcp_input+0x38e>
|
|
8014248: 4b6a ldr r3, [pc, #424] ; (80143f4 <tcp_input+0x52c>)
|
|
801424a: f240 121f movw r2, #287 ; 0x11f
|
|
801424e: 496f ldr r1, [pc, #444] ; (801440c <tcp_input+0x544>)
|
|
8014250: 486a ldr r0, [pc, #424] ; (80143fc <tcp_input+0x534>)
|
|
8014252: f008 fd31 bl 801ccb8 <iprintf>
|
|
|
|
/* check if PCB is bound to specific netif */
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
8014256: 69fb ldr r3, [r7, #28]
|
|
8014258: 7a1b ldrb r3, [r3, #8]
|
|
801425a: 2b00 cmp r3, #0
|
|
801425c: d009 beq.n 8014272 <tcp_input+0x3aa>
|
|
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
|
|
801425e: 69fb ldr r3, [r7, #28]
|
|
8014260: 7a1a ldrb r2, [r3, #8]
|
|
8014262: 4b63 ldr r3, [pc, #396] ; (80143f0 <tcp_input+0x528>)
|
|
8014264: 685b ldr r3, [r3, #4]
|
|
8014266: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
801426a: 3301 adds r3, #1
|
|
801426c: b2db uxtb r3, r3
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
801426e: 429a cmp r2, r3
|
|
8014270: d122 bne.n 80142b8 <tcp_input+0x3f0>
|
|
continue;
|
|
}
|
|
|
|
if (pcb->remote_port == tcphdr->src &&
|
|
8014272: 69fb ldr r3, [r7, #28]
|
|
8014274: 8b1a ldrh r2, [r3, #24]
|
|
8014276: 4b5d ldr r3, [pc, #372] ; (80143ec <tcp_input+0x524>)
|
|
8014278: 681b ldr r3, [r3, #0]
|
|
801427a: 881b ldrh r3, [r3, #0]
|
|
801427c: b29b uxth r3, r3
|
|
801427e: 429a cmp r2, r3
|
|
8014280: d11b bne.n 80142ba <tcp_input+0x3f2>
|
|
pcb->local_port == tcphdr->dest &&
|
|
8014282: 69fb ldr r3, [r7, #28]
|
|
8014284: 8ada ldrh r2, [r3, #22]
|
|
8014286: 4b59 ldr r3, [pc, #356] ; (80143ec <tcp_input+0x524>)
|
|
8014288: 681b ldr r3, [r3, #0]
|
|
801428a: 885b ldrh r3, [r3, #2]
|
|
801428c: b29b uxth r3, r3
|
|
if (pcb->remote_port == tcphdr->src &&
|
|
801428e: 429a cmp r2, r3
|
|
8014290: d113 bne.n 80142ba <tcp_input+0x3f2>
|
|
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
|
|
8014292: 69fb ldr r3, [r7, #28]
|
|
8014294: 685a ldr r2, [r3, #4]
|
|
8014296: 4b56 ldr r3, [pc, #344] ; (80143f0 <tcp_input+0x528>)
|
|
8014298: 691b ldr r3, [r3, #16]
|
|
pcb->local_port == tcphdr->dest &&
|
|
801429a: 429a cmp r2, r3
|
|
801429c: d10d bne.n 80142ba <tcp_input+0x3f2>
|
|
ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
|
|
801429e: 69fb ldr r3, [r7, #28]
|
|
80142a0: 681a ldr r2, [r3, #0]
|
|
80142a2: 4b53 ldr r3, [pc, #332] ; (80143f0 <tcp_input+0x528>)
|
|
80142a4: 695b ldr r3, [r3, #20]
|
|
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) &&
|
|
80142a6: 429a cmp r2, r3
|
|
80142a8: d107 bne.n 80142ba <tcp_input+0x3f2>
|
|
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
|
|
if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len,
|
|
tcphdr_opt2, p) == ERR_OK)
|
|
#endif
|
|
{
|
|
tcp_timewait_input(pcb);
|
|
80142aa: 69f8 ldr r0, [r7, #28]
|
|
80142ac: f000 fb52 bl 8014954 <tcp_timewait_input>
|
|
}
|
|
pbuf_free(p);
|
|
80142b0: 6878 ldr r0, [r7, #4]
|
|
80142b2: f7fd ffd1 bl 8012258 <pbuf_free>
|
|
return;
|
|
80142b6: e1ee b.n 8014696 <tcp_input+0x7ce>
|
|
continue;
|
|
80142b8: bf00 nop
|
|
for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
80142ba: 69fb ldr r3, [r7, #28]
|
|
80142bc: 68db ldr r3, [r3, #12]
|
|
80142be: 61fb str r3, [r7, #28]
|
|
80142c0: 69fb ldr r3, [r7, #28]
|
|
80142c2: 2b00 cmp r3, #0
|
|
80142c4: d1bc bne.n 8014240 <tcp_input+0x378>
|
|
}
|
|
}
|
|
|
|
/* Finally, if we still did not get a match, we check all PCBs that
|
|
are LISTENing for incoming connections. */
|
|
prev = NULL;
|
|
80142c6: 2300 movs r3, #0
|
|
80142c8: 61bb str r3, [r7, #24]
|
|
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
|
|
80142ca: 4b51 ldr r3, [pc, #324] ; (8014410 <tcp_input+0x548>)
|
|
80142cc: 681b ldr r3, [r3, #0]
|
|
80142ce: 617b str r3, [r7, #20]
|
|
80142d0: e02a b.n 8014328 <tcp_input+0x460>
|
|
/* check if PCB is bound to specific netif */
|
|
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
|
|
80142d2: 697b ldr r3, [r7, #20]
|
|
80142d4: 7a1b ldrb r3, [r3, #8]
|
|
80142d6: 2b00 cmp r3, #0
|
|
80142d8: d00c beq.n 80142f4 <tcp_input+0x42c>
|
|
(lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
|
|
80142da: 697b ldr r3, [r7, #20]
|
|
80142dc: 7a1a ldrb r2, [r3, #8]
|
|
80142de: 4b44 ldr r3, [pc, #272] ; (80143f0 <tcp_input+0x528>)
|
|
80142e0: 685b ldr r3, [r3, #4]
|
|
80142e2: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
80142e6: 3301 adds r3, #1
|
|
80142e8: b2db uxtb r3, r3
|
|
if ((lpcb->netif_idx != NETIF_NO_INDEX) &&
|
|
80142ea: 429a cmp r2, r3
|
|
80142ec: d002 beq.n 80142f4 <tcp_input+0x42c>
|
|
prev = (struct tcp_pcb *)lpcb;
|
|
80142ee: 697b ldr r3, [r7, #20]
|
|
80142f0: 61bb str r3, [r7, #24]
|
|
continue;
|
|
80142f2: e016 b.n 8014322 <tcp_input+0x45a>
|
|
}
|
|
|
|
if (lpcb->local_port == tcphdr->dest) {
|
|
80142f4: 697b ldr r3, [r7, #20]
|
|
80142f6: 8ada ldrh r2, [r3, #22]
|
|
80142f8: 4b3c ldr r3, [pc, #240] ; (80143ec <tcp_input+0x524>)
|
|
80142fa: 681b ldr r3, [r3, #0]
|
|
80142fc: 885b ldrh r3, [r3, #2]
|
|
80142fe: b29b uxth r3, r3
|
|
8014300: 429a cmp r2, r3
|
|
8014302: d10c bne.n 801431e <tcp_input+0x456>
|
|
lpcb_prev = prev;
|
|
#else /* SO_REUSE */
|
|
break;
|
|
#endif /* SO_REUSE */
|
|
} else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) {
|
|
if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) {
|
|
8014304: 697b ldr r3, [r7, #20]
|
|
8014306: 681a ldr r2, [r3, #0]
|
|
8014308: 4b39 ldr r3, [pc, #228] ; (80143f0 <tcp_input+0x528>)
|
|
801430a: 695b ldr r3, [r3, #20]
|
|
801430c: 429a cmp r2, r3
|
|
801430e: d00f beq.n 8014330 <tcp_input+0x468>
|
|
/* found an exact match */
|
|
break;
|
|
} else if (ip_addr_isany(&lpcb->local_ip)) {
|
|
8014310: 697b ldr r3, [r7, #20]
|
|
8014312: 2b00 cmp r3, #0
|
|
8014314: d00d beq.n 8014332 <tcp_input+0x46a>
|
|
8014316: 697b ldr r3, [r7, #20]
|
|
8014318: 681b ldr r3, [r3, #0]
|
|
801431a: 2b00 cmp r3, #0
|
|
801431c: d009 beq.n 8014332 <tcp_input+0x46a>
|
|
break;
|
|
#endif /* SO_REUSE */
|
|
}
|
|
}
|
|
}
|
|
prev = (struct tcp_pcb *)lpcb;
|
|
801431e: 697b ldr r3, [r7, #20]
|
|
8014320: 61bb str r3, [r7, #24]
|
|
for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) {
|
|
8014322: 697b ldr r3, [r7, #20]
|
|
8014324: 68db ldr r3, [r3, #12]
|
|
8014326: 617b str r3, [r7, #20]
|
|
8014328: 697b ldr r3, [r7, #20]
|
|
801432a: 2b00 cmp r3, #0
|
|
801432c: d1d1 bne.n 80142d2 <tcp_input+0x40a>
|
|
801432e: e000 b.n 8014332 <tcp_input+0x46a>
|
|
break;
|
|
8014330: bf00 nop
|
|
/* only pass to ANY if no specific local IP has been found */
|
|
lpcb = lpcb_any;
|
|
prev = lpcb_prev;
|
|
}
|
|
#endif /* SO_REUSE */
|
|
if (lpcb != NULL) {
|
|
8014332: 697b ldr r3, [r7, #20]
|
|
8014334: 2b00 cmp r3, #0
|
|
8014336: d014 beq.n 8014362 <tcp_input+0x49a>
|
|
/* Move this PCB to the front of the list so that subsequent
|
|
lookups will be faster (we exploit locality in TCP segment
|
|
arrivals). */
|
|
if (prev != NULL) {
|
|
8014338: 69bb ldr r3, [r7, #24]
|
|
801433a: 2b00 cmp r3, #0
|
|
801433c: d00a beq.n 8014354 <tcp_input+0x48c>
|
|
((struct tcp_pcb_listen *)prev)->next = lpcb->next;
|
|
801433e: 697b ldr r3, [r7, #20]
|
|
8014340: 68da ldr r2, [r3, #12]
|
|
8014342: 69bb ldr r3, [r7, #24]
|
|
8014344: 60da str r2, [r3, #12]
|
|
/* our successor is the remainder of the listening list */
|
|
lpcb->next = tcp_listen_pcbs.listen_pcbs;
|
|
8014346: 4b32 ldr r3, [pc, #200] ; (8014410 <tcp_input+0x548>)
|
|
8014348: 681a ldr r2, [r3, #0]
|
|
801434a: 697b ldr r3, [r7, #20]
|
|
801434c: 60da str r2, [r3, #12]
|
|
/* put this listening pcb at the head of the listening list */
|
|
tcp_listen_pcbs.listen_pcbs = lpcb;
|
|
801434e: 4a30 ldr r2, [pc, #192] ; (8014410 <tcp_input+0x548>)
|
|
8014350: 697b ldr r3, [r7, #20]
|
|
8014352: 6013 str r3, [r2, #0]
|
|
#ifdef LWIP_HOOK_TCP_INPACKET_PCB
|
|
if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen,
|
|
tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK)
|
|
#endif
|
|
{
|
|
tcp_listen_input(lpcb);
|
|
8014354: 6978 ldr r0, [r7, #20]
|
|
8014356: f000 f9ff bl 8014758 <tcp_listen_input>
|
|
}
|
|
pbuf_free(p);
|
|
801435a: 6878 ldr r0, [r7, #4]
|
|
801435c: f7fd ff7c bl 8012258 <pbuf_free>
|
|
return;
|
|
8014360: e199 b.n 8014696 <tcp_input+0x7ce>
|
|
tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) {
|
|
pbuf_free(p);
|
|
return;
|
|
}
|
|
#endif
|
|
if (pcb != NULL) {
|
|
8014362: 69fb ldr r3, [r7, #28]
|
|
8014364: 2b00 cmp r3, #0
|
|
8014366: f000 8160 beq.w 801462a <tcp_input+0x762>
|
|
#if TCP_INPUT_DEBUG
|
|
tcp_debug_print_state(pcb->state);
|
|
#endif /* TCP_INPUT_DEBUG */
|
|
|
|
/* Set up a tcp_seg structure. */
|
|
inseg.next = NULL;
|
|
801436a: 4b2a ldr r3, [pc, #168] ; (8014414 <tcp_input+0x54c>)
|
|
801436c: 2200 movs r2, #0
|
|
801436e: 601a str r2, [r3, #0]
|
|
inseg.len = p->tot_len;
|
|
8014370: 687b ldr r3, [r7, #4]
|
|
8014372: 891a ldrh r2, [r3, #8]
|
|
8014374: 4b27 ldr r3, [pc, #156] ; (8014414 <tcp_input+0x54c>)
|
|
8014376: 811a strh r2, [r3, #8]
|
|
inseg.p = p;
|
|
8014378: 4a26 ldr r2, [pc, #152] ; (8014414 <tcp_input+0x54c>)
|
|
801437a: 687b ldr r3, [r7, #4]
|
|
801437c: 6053 str r3, [r2, #4]
|
|
inseg.tcphdr = tcphdr;
|
|
801437e: 4b1b ldr r3, [pc, #108] ; (80143ec <tcp_input+0x524>)
|
|
8014380: 681b ldr r3, [r3, #0]
|
|
8014382: 4a24 ldr r2, [pc, #144] ; (8014414 <tcp_input+0x54c>)
|
|
8014384: 60d3 str r3, [r2, #12]
|
|
|
|
recv_data = NULL;
|
|
8014386: 4b24 ldr r3, [pc, #144] ; (8014418 <tcp_input+0x550>)
|
|
8014388: 2200 movs r2, #0
|
|
801438a: 601a str r2, [r3, #0]
|
|
recv_flags = 0;
|
|
801438c: 4b23 ldr r3, [pc, #140] ; (801441c <tcp_input+0x554>)
|
|
801438e: 2200 movs r2, #0
|
|
8014390: 701a strb r2, [r3, #0]
|
|
recv_acked = 0;
|
|
8014392: 4b23 ldr r3, [pc, #140] ; (8014420 <tcp_input+0x558>)
|
|
8014394: 2200 movs r2, #0
|
|
8014396: 801a strh r2, [r3, #0]
|
|
|
|
if (flags & TCP_PSH) {
|
|
8014398: 4b22 ldr r3, [pc, #136] ; (8014424 <tcp_input+0x55c>)
|
|
801439a: 781b ldrb r3, [r3, #0]
|
|
801439c: f003 0308 and.w r3, r3, #8
|
|
80143a0: 2b00 cmp r3, #0
|
|
80143a2: d006 beq.n 80143b2 <tcp_input+0x4ea>
|
|
p->flags |= PBUF_FLAG_PUSH;
|
|
80143a4: 687b ldr r3, [r7, #4]
|
|
80143a6: 7b5b ldrb r3, [r3, #13]
|
|
80143a8: f043 0301 orr.w r3, r3, #1
|
|
80143ac: b2da uxtb r2, r3
|
|
80143ae: 687b ldr r3, [r7, #4]
|
|
80143b0: 735a strb r2, [r3, #13]
|
|
}
|
|
|
|
/* If there is data which was previously "refused" by upper layer */
|
|
if (pcb->refused_data != NULL) {
|
|
80143b2: 69fb ldr r3, [r7, #28]
|
|
80143b4: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
80143b6: 2b00 cmp r3, #0
|
|
80143b8: d038 beq.n 801442c <tcp_input+0x564>
|
|
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
|
|
80143ba: 69f8 ldr r0, [r7, #28]
|
|
80143bc: f7ff f940 bl 8013640 <tcp_process_refused_data>
|
|
80143c0: 4603 mov r3, r0
|
|
80143c2: f113 0f0d cmn.w r3, #13
|
|
80143c6: d007 beq.n 80143d8 <tcp_input+0x510>
|
|
((pcb->refused_data != NULL) && (tcplen > 0))) {
|
|
80143c8: 69fb ldr r3, [r7, #28]
|
|
80143ca: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
if ((tcp_process_refused_data(pcb) == ERR_ABRT) ||
|
|
80143cc: 2b00 cmp r3, #0
|
|
80143ce: d02d beq.n 801442c <tcp_input+0x564>
|
|
((pcb->refused_data != NULL) && (tcplen > 0))) {
|
|
80143d0: 4b15 ldr r3, [pc, #84] ; (8014428 <tcp_input+0x560>)
|
|
80143d2: 881b ldrh r3, [r3, #0]
|
|
80143d4: 2b00 cmp r3, #0
|
|
80143d6: d029 beq.n 801442c <tcp_input+0x564>
|
|
/* pcb has been aborted or refused data is still refused and the new
|
|
segment contains data */
|
|
if (pcb->rcv_ann_wnd == 0) {
|
|
80143d8: 69fb ldr r3, [r7, #28]
|
|
80143da: 8d5b ldrh r3, [r3, #42] ; 0x2a
|
|
80143dc: 2b00 cmp r3, #0
|
|
80143de: f040 8104 bne.w 80145ea <tcp_input+0x722>
|
|
/* this is a zero-window probe, we respond to it with current RCV.NXT
|
|
and drop the data segment */
|
|
tcp_send_empty_ack(pcb);
|
|
80143e2: 69f8 ldr r0, [r7, #28]
|
|
80143e4: f003 f9ce bl 8017784 <tcp_send_empty_ack>
|
|
}
|
|
TCP_STATS_INC(tcp.drop);
|
|
MIB2_STATS_INC(mib2.tcpinerrs);
|
|
goto aborted;
|
|
80143e8: e0ff b.n 80145ea <tcp_input+0x722>
|
|
80143ea: bf00 nop
|
|
80143ec: 2000873c .word 0x2000873c
|
|
80143f0: 2000c0c8 .word 0x2000c0c8
|
|
80143f4: 0801f2b0 .word 0x0801f2b0
|
|
80143f8: 0801f3dc .word 0x0801f3dc
|
|
80143fc: 0801f2fc .word 0x0801f2fc
|
|
8014400: 2000f7fc .word 0x2000f7fc
|
|
8014404: 0801f408 .word 0x0801f408
|
|
8014408: 2000f80c .word 0x2000f80c
|
|
801440c: 0801f434 .word 0x0801f434
|
|
8014410: 2000f804 .word 0x2000f804
|
|
8014414: 2000872c .word 0x2000872c
|
|
8014418: 2000875c .word 0x2000875c
|
|
801441c: 20008759 .word 0x20008759
|
|
8014420: 20008754 .word 0x20008754
|
|
8014424: 20008758 .word 0x20008758
|
|
8014428: 20008756 .word 0x20008756
|
|
}
|
|
}
|
|
tcp_input_pcb = pcb;
|
|
801442c: 4a9b ldr r2, [pc, #620] ; (801469c <tcp_input+0x7d4>)
|
|
801442e: 69fb ldr r3, [r7, #28]
|
|
8014430: 6013 str r3, [r2, #0]
|
|
err = tcp_process(pcb);
|
|
8014432: 69f8 ldr r0, [r7, #28]
|
|
8014434: f000 fb0a bl 8014a4c <tcp_process>
|
|
8014438: 4603 mov r3, r0
|
|
801443a: 74fb strb r3, [r7, #19]
|
|
/* A return value of ERR_ABRT means that tcp_abort() was called
|
|
and that the pcb has been freed. If so, we don't do anything. */
|
|
if (err != ERR_ABRT) {
|
|
801443c: f997 3013 ldrsb.w r3, [r7, #19]
|
|
8014440: f113 0f0d cmn.w r3, #13
|
|
8014444: f000 80d3 beq.w 80145ee <tcp_input+0x726>
|
|
if (recv_flags & TF_RESET) {
|
|
8014448: 4b95 ldr r3, [pc, #596] ; (80146a0 <tcp_input+0x7d8>)
|
|
801444a: 781b ldrb r3, [r3, #0]
|
|
801444c: f003 0308 and.w r3, r3, #8
|
|
8014450: 2b00 cmp r3, #0
|
|
8014452: d015 beq.n 8014480 <tcp_input+0x5b8>
|
|
/* TF_RESET means that the connection was reset by the other
|
|
end. We then call the error callback to inform the
|
|
application that the connection is dead before we
|
|
deallocate the PCB. */
|
|
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST);
|
|
8014454: 69fb ldr r3, [r7, #28]
|
|
8014456: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
801445a: 2b00 cmp r3, #0
|
|
801445c: d008 beq.n 8014470 <tcp_input+0x5a8>
|
|
801445e: 69fb ldr r3, [r7, #28]
|
|
8014460: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8014464: 69fa ldr r2, [r7, #28]
|
|
8014466: 6912 ldr r2, [r2, #16]
|
|
8014468: f06f 010d mvn.w r1, #13
|
|
801446c: 4610 mov r0, r2
|
|
801446e: 4798 blx r3
|
|
tcp_pcb_remove(&tcp_active_pcbs, pcb);
|
|
8014470: 69f9 ldr r1, [r7, #28]
|
|
8014472: 488c ldr r0, [pc, #560] ; (80146a4 <tcp_input+0x7dc>)
|
|
8014474: f7ff fbb0 bl 8013bd8 <tcp_pcb_remove>
|
|
tcp_free(pcb);
|
|
8014478: 69f8 ldr r0, [r7, #28]
|
|
801447a: f7fe f9a9 bl 80127d0 <tcp_free>
|
|
801447e: e0c1 b.n 8014604 <tcp_input+0x73c>
|
|
} else {
|
|
err = ERR_OK;
|
|
8014480: 2300 movs r3, #0
|
|
8014482: 74fb strb r3, [r7, #19]
|
|
/* If the application has registered a "sent" function to be
|
|
called when new send buffer space is available, we call it
|
|
now. */
|
|
if (recv_acked > 0) {
|
|
8014484: 4b88 ldr r3, [pc, #544] ; (80146a8 <tcp_input+0x7e0>)
|
|
8014486: 881b ldrh r3, [r3, #0]
|
|
8014488: 2b00 cmp r3, #0
|
|
801448a: d01d beq.n 80144c8 <tcp_input+0x600>
|
|
while (acked > 0) {
|
|
acked16 = (u16_t)LWIP_MIN(acked, 0xffffu);
|
|
acked -= acked16;
|
|
#else
|
|
{
|
|
acked16 = recv_acked;
|
|
801448c: 4b86 ldr r3, [pc, #536] ; (80146a8 <tcp_input+0x7e0>)
|
|
801448e: 881b ldrh r3, [r3, #0]
|
|
8014490: 81fb strh r3, [r7, #14]
|
|
#endif
|
|
TCP_EVENT_SENT(pcb, (u16_t)acked16, err);
|
|
8014492: 69fb ldr r3, [r7, #28]
|
|
8014494: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
8014498: 2b00 cmp r3, #0
|
|
801449a: d00a beq.n 80144b2 <tcp_input+0x5ea>
|
|
801449c: 69fb ldr r3, [r7, #28]
|
|
801449e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
|
|
80144a2: 69fa ldr r2, [r7, #28]
|
|
80144a4: 6910 ldr r0, [r2, #16]
|
|
80144a6: 89fa ldrh r2, [r7, #14]
|
|
80144a8: 69f9 ldr r1, [r7, #28]
|
|
80144aa: 4798 blx r3
|
|
80144ac: 4603 mov r3, r0
|
|
80144ae: 74fb strb r3, [r7, #19]
|
|
80144b0: e001 b.n 80144b6 <tcp_input+0x5ee>
|
|
80144b2: 2300 movs r3, #0
|
|
80144b4: 74fb strb r3, [r7, #19]
|
|
if (err == ERR_ABRT) {
|
|
80144b6: f997 3013 ldrsb.w r3, [r7, #19]
|
|
80144ba: f113 0f0d cmn.w r3, #13
|
|
80144be: f000 8098 beq.w 80145f2 <tcp_input+0x72a>
|
|
goto aborted;
|
|
}
|
|
}
|
|
recv_acked = 0;
|
|
80144c2: 4b79 ldr r3, [pc, #484] ; (80146a8 <tcp_input+0x7e0>)
|
|
80144c4: 2200 movs r2, #0
|
|
80144c6: 801a strh r2, [r3, #0]
|
|
}
|
|
if (tcp_input_delayed_close(pcb)) {
|
|
80144c8: 69f8 ldr r0, [r7, #28]
|
|
80144ca: f000 f905 bl 80146d8 <tcp_input_delayed_close>
|
|
80144ce: 4603 mov r3, r0
|
|
80144d0: 2b00 cmp r3, #0
|
|
80144d2: f040 8090 bne.w 80145f6 <tcp_input+0x72e>
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
while (recv_data != NULL) {
|
|
struct pbuf *rest = NULL;
|
|
pbuf_split_64k(recv_data, &rest);
|
|
#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
if (recv_data != NULL) {
|
|
80144d6: 4b75 ldr r3, [pc, #468] ; (80146ac <tcp_input+0x7e4>)
|
|
80144d8: 681b ldr r3, [r3, #0]
|
|
80144da: 2b00 cmp r3, #0
|
|
80144dc: d041 beq.n 8014562 <tcp_input+0x69a>
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
|
|
LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL);
|
|
80144de: 69fb ldr r3, [r7, #28]
|
|
80144e0: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
80144e2: 2b00 cmp r3, #0
|
|
80144e4: d006 beq.n 80144f4 <tcp_input+0x62c>
|
|
80144e6: 4b72 ldr r3, [pc, #456] ; (80146b0 <tcp_input+0x7e8>)
|
|
80144e8: f44f 72f3 mov.w r2, #486 ; 0x1e6
|
|
80144ec: 4971 ldr r1, [pc, #452] ; (80146b4 <tcp_input+0x7ec>)
|
|
80144ee: 4872 ldr r0, [pc, #456] ; (80146b8 <tcp_input+0x7f0>)
|
|
80144f0: f008 fbe2 bl 801ccb8 <iprintf>
|
|
if (pcb->flags & TF_RXCLOSED) {
|
|
80144f4: 69fb ldr r3, [r7, #28]
|
|
80144f6: 8b5b ldrh r3, [r3, #26]
|
|
80144f8: f003 0310 and.w r3, r3, #16
|
|
80144fc: 2b00 cmp r3, #0
|
|
80144fe: d008 beq.n 8014512 <tcp_input+0x64a>
|
|
/* received data although already closed -> abort (send RST) to
|
|
notify the remote host that not all data has been processed */
|
|
pbuf_free(recv_data);
|
|
8014500: 4b6a ldr r3, [pc, #424] ; (80146ac <tcp_input+0x7e4>)
|
|
8014502: 681b ldr r3, [r3, #0]
|
|
8014504: 4618 mov r0, r3
|
|
8014506: f7fd fea7 bl 8012258 <pbuf_free>
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
if (rest != NULL) {
|
|
pbuf_free(rest);
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
tcp_abort(pcb);
|
|
801450a: 69f8 ldr r0, [r7, #28]
|
|
801450c: f7fe fc40 bl 8012d90 <tcp_abort>
|
|
goto aborted;
|
|
8014510: e078 b.n 8014604 <tcp_input+0x73c>
|
|
}
|
|
|
|
/* Notify application that data has been received. */
|
|
TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err);
|
|
8014512: 69fb ldr r3, [r7, #28]
|
|
8014514: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
8014518: 2b00 cmp r3, #0
|
|
801451a: d00c beq.n 8014536 <tcp_input+0x66e>
|
|
801451c: 69fb ldr r3, [r7, #28]
|
|
801451e: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
|
|
8014522: 69fb ldr r3, [r7, #28]
|
|
8014524: 6918 ldr r0, [r3, #16]
|
|
8014526: 4b61 ldr r3, [pc, #388] ; (80146ac <tcp_input+0x7e4>)
|
|
8014528: 681a ldr r2, [r3, #0]
|
|
801452a: 2300 movs r3, #0
|
|
801452c: 69f9 ldr r1, [r7, #28]
|
|
801452e: 47a0 blx r4
|
|
8014530: 4603 mov r3, r0
|
|
8014532: 74fb strb r3, [r7, #19]
|
|
8014534: e008 b.n 8014548 <tcp_input+0x680>
|
|
8014536: 4b5d ldr r3, [pc, #372] ; (80146ac <tcp_input+0x7e4>)
|
|
8014538: 681a ldr r2, [r3, #0]
|
|
801453a: 2300 movs r3, #0
|
|
801453c: 69f9 ldr r1, [r7, #28]
|
|
801453e: 2000 movs r0, #0
|
|
8014540: f7ff f952 bl 80137e8 <tcp_recv_null>
|
|
8014544: 4603 mov r3, r0
|
|
8014546: 74fb strb r3, [r7, #19]
|
|
if (err == ERR_ABRT) {
|
|
8014548: f997 3013 ldrsb.w r3, [r7, #19]
|
|
801454c: f113 0f0d cmn.w r3, #13
|
|
8014550: d053 beq.n 80145fa <tcp_input+0x732>
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
goto aborted;
|
|
}
|
|
|
|
/* If the upper layer can't receive this data, store it */
|
|
if (err != ERR_OK) {
|
|
8014552: f997 3013 ldrsb.w r3, [r7, #19]
|
|
8014556: 2b00 cmp r3, #0
|
|
8014558: d003 beq.n 8014562 <tcp_input+0x69a>
|
|
#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE
|
|
if (rest != NULL) {
|
|
pbuf_cat(recv_data, rest);
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */
|
|
pcb->refused_data = recv_data;
|
|
801455a: 4b54 ldr r3, [pc, #336] ; (80146ac <tcp_input+0x7e4>)
|
|
801455c: 681a ldr r2, [r3, #0]
|
|
801455e: 69fb ldr r3, [r7, #28]
|
|
8014560: 679a str r2, [r3, #120] ; 0x78
|
|
}
|
|
}
|
|
|
|
/* If a FIN segment was received, we call the callback
|
|
function with a NULL buffer to indicate EOF. */
|
|
if (recv_flags & TF_GOT_FIN) {
|
|
8014562: 4b4f ldr r3, [pc, #316] ; (80146a0 <tcp_input+0x7d8>)
|
|
8014564: 781b ldrb r3, [r3, #0]
|
|
8014566: f003 0320 and.w r3, r3, #32
|
|
801456a: 2b00 cmp r3, #0
|
|
801456c: d030 beq.n 80145d0 <tcp_input+0x708>
|
|
if (pcb->refused_data != NULL) {
|
|
801456e: 69fb ldr r3, [r7, #28]
|
|
8014570: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8014572: 2b00 cmp r3, #0
|
|
8014574: d009 beq.n 801458a <tcp_input+0x6c2>
|
|
/* Delay this if we have refused data. */
|
|
pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN;
|
|
8014576: 69fb ldr r3, [r7, #28]
|
|
8014578: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
801457a: 7b5a ldrb r2, [r3, #13]
|
|
801457c: 69fb ldr r3, [r7, #28]
|
|
801457e: 6f9b ldr r3, [r3, #120] ; 0x78
|
|
8014580: f042 0220 orr.w r2, r2, #32
|
|
8014584: b2d2 uxtb r2, r2
|
|
8014586: 735a strb r2, [r3, #13]
|
|
8014588: e022 b.n 80145d0 <tcp_input+0x708>
|
|
} else {
|
|
/* correct rcv_wnd as the application won't call tcp_recved()
|
|
for the FIN's seqno */
|
|
if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) {
|
|
801458a: 69fb ldr r3, [r7, #28]
|
|
801458c: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
801458e: f5b3 6f06 cmp.w r3, #2144 ; 0x860
|
|
8014592: d005 beq.n 80145a0 <tcp_input+0x6d8>
|
|
pcb->rcv_wnd++;
|
|
8014594: 69fb ldr r3, [r7, #28]
|
|
8014596: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8014598: 3301 adds r3, #1
|
|
801459a: b29a uxth r2, r3
|
|
801459c: 69fb ldr r3, [r7, #28]
|
|
801459e: 851a strh r2, [r3, #40] ; 0x28
|
|
}
|
|
TCP_EVENT_CLOSED(pcb, err);
|
|
80145a0: 69fb ldr r3, [r7, #28]
|
|
80145a2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
|
|
80145a6: 2b00 cmp r3, #0
|
|
80145a8: d00b beq.n 80145c2 <tcp_input+0x6fa>
|
|
80145aa: 69fb ldr r3, [r7, #28]
|
|
80145ac: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84
|
|
80145b0: 69fb ldr r3, [r7, #28]
|
|
80145b2: 6918 ldr r0, [r3, #16]
|
|
80145b4: 2300 movs r3, #0
|
|
80145b6: 2200 movs r2, #0
|
|
80145b8: 69f9 ldr r1, [r7, #28]
|
|
80145ba: 47a0 blx r4
|
|
80145bc: 4603 mov r3, r0
|
|
80145be: 74fb strb r3, [r7, #19]
|
|
80145c0: e001 b.n 80145c6 <tcp_input+0x6fe>
|
|
80145c2: 2300 movs r3, #0
|
|
80145c4: 74fb strb r3, [r7, #19]
|
|
if (err == ERR_ABRT) {
|
|
80145c6: f997 3013 ldrsb.w r3, [r7, #19]
|
|
80145ca: f113 0f0d cmn.w r3, #13
|
|
80145ce: d016 beq.n 80145fe <tcp_input+0x736>
|
|
goto aborted;
|
|
}
|
|
}
|
|
}
|
|
|
|
tcp_input_pcb = NULL;
|
|
80145d0: 4b32 ldr r3, [pc, #200] ; (801469c <tcp_input+0x7d4>)
|
|
80145d2: 2200 movs r2, #0
|
|
80145d4: 601a str r2, [r3, #0]
|
|
if (tcp_input_delayed_close(pcb)) {
|
|
80145d6: 69f8 ldr r0, [r7, #28]
|
|
80145d8: f000 f87e bl 80146d8 <tcp_input_delayed_close>
|
|
80145dc: 4603 mov r3, r0
|
|
80145de: 2b00 cmp r3, #0
|
|
80145e0: d10f bne.n 8014602 <tcp_input+0x73a>
|
|
goto aborted;
|
|
}
|
|
/* Try to send something out. */
|
|
tcp_output(pcb);
|
|
80145e2: 69f8 ldr r0, [r7, #28]
|
|
80145e4: f002 fab6 bl 8016b54 <tcp_output>
|
|
80145e8: e00c b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
80145ea: bf00 nop
|
|
80145ec: e00a b.n 8014604 <tcp_input+0x73c>
|
|
#endif /* TCP_INPUT_DEBUG */
|
|
}
|
|
}
|
|
/* Jump target if pcb has been aborted in a callback (by calling tcp_abort()).
|
|
Below this line, 'pcb' may not be dereferenced! */
|
|
aborted:
|
|
80145ee: bf00 nop
|
|
80145f0: e008 b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
80145f2: bf00 nop
|
|
80145f4: e006 b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
80145f6: bf00 nop
|
|
80145f8: e004 b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
80145fa: bf00 nop
|
|
80145fc: e002 b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
80145fe: bf00 nop
|
|
8014600: e000 b.n 8014604 <tcp_input+0x73c>
|
|
goto aborted;
|
|
8014602: bf00 nop
|
|
tcp_input_pcb = NULL;
|
|
8014604: 4b25 ldr r3, [pc, #148] ; (801469c <tcp_input+0x7d4>)
|
|
8014606: 2200 movs r2, #0
|
|
8014608: 601a str r2, [r3, #0]
|
|
recv_data = NULL;
|
|
801460a: 4b28 ldr r3, [pc, #160] ; (80146ac <tcp_input+0x7e4>)
|
|
801460c: 2200 movs r2, #0
|
|
801460e: 601a str r2, [r3, #0]
|
|
|
|
/* give up our reference to inseg.p */
|
|
if (inseg.p != NULL) {
|
|
8014610: 4b2a ldr r3, [pc, #168] ; (80146bc <tcp_input+0x7f4>)
|
|
8014612: 685b ldr r3, [r3, #4]
|
|
8014614: 2b00 cmp r3, #0
|
|
8014616: d03d beq.n 8014694 <tcp_input+0x7cc>
|
|
pbuf_free(inseg.p);
|
|
8014618: 4b28 ldr r3, [pc, #160] ; (80146bc <tcp_input+0x7f4>)
|
|
801461a: 685b ldr r3, [r3, #4]
|
|
801461c: 4618 mov r0, r3
|
|
801461e: f7fd fe1b bl 8012258 <pbuf_free>
|
|
inseg.p = NULL;
|
|
8014622: 4b26 ldr r3, [pc, #152] ; (80146bc <tcp_input+0x7f4>)
|
|
8014624: 2200 movs r2, #0
|
|
8014626: 605a str r2, [r3, #4]
|
|
pbuf_free(p);
|
|
}
|
|
|
|
LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane());
|
|
PERF_STOP("tcp_input");
|
|
return;
|
|
8014628: e034 b.n 8014694 <tcp_input+0x7cc>
|
|
if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) {
|
|
801462a: 4b25 ldr r3, [pc, #148] ; (80146c0 <tcp_input+0x7f8>)
|
|
801462c: 681b ldr r3, [r3, #0]
|
|
801462e: 899b ldrh r3, [r3, #12]
|
|
8014630: b29b uxth r3, r3
|
|
8014632: 4618 mov r0, r3
|
|
8014634: f7fc fa5c bl 8010af0 <lwip_htons>
|
|
8014638: 4603 mov r3, r0
|
|
801463a: b2db uxtb r3, r3
|
|
801463c: f003 0304 and.w r3, r3, #4
|
|
8014640: 2b00 cmp r3, #0
|
|
8014642: d118 bne.n 8014676 <tcp_input+0x7ae>
|
|
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014644: 4b1f ldr r3, [pc, #124] ; (80146c4 <tcp_input+0x7fc>)
|
|
8014646: 6819 ldr r1, [r3, #0]
|
|
8014648: 4b1f ldr r3, [pc, #124] ; (80146c8 <tcp_input+0x800>)
|
|
801464a: 881b ldrh r3, [r3, #0]
|
|
801464c: 461a mov r2, r3
|
|
801464e: 4b1f ldr r3, [pc, #124] ; (80146cc <tcp_input+0x804>)
|
|
8014650: 681b ldr r3, [r3, #0]
|
|
8014652: 18d0 adds r0, r2, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
8014654: 4b1a ldr r3, [pc, #104] ; (80146c0 <tcp_input+0x7f8>)
|
|
8014656: 681b ldr r3, [r3, #0]
|
|
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014658: 885b ldrh r3, [r3, #2]
|
|
801465a: b29b uxth r3, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
801465c: 4a18 ldr r2, [pc, #96] ; (80146c0 <tcp_input+0x7f8>)
|
|
801465e: 6812 ldr r2, [r2, #0]
|
|
tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014660: 8812 ldrh r2, [r2, #0]
|
|
8014662: b292 uxth r2, r2
|
|
8014664: 9202 str r2, [sp, #8]
|
|
8014666: 9301 str r3, [sp, #4]
|
|
8014668: 4b19 ldr r3, [pc, #100] ; (80146d0 <tcp_input+0x808>)
|
|
801466a: 9300 str r3, [sp, #0]
|
|
801466c: 4b19 ldr r3, [pc, #100] ; (80146d4 <tcp_input+0x80c>)
|
|
801466e: 4602 mov r2, r0
|
|
8014670: 2000 movs r0, #0
|
|
8014672: f003 f835 bl 80176e0 <tcp_rst>
|
|
pbuf_free(p);
|
|
8014676: 6878 ldr r0, [r7, #4]
|
|
8014678: f7fd fdee bl 8012258 <pbuf_free>
|
|
return;
|
|
801467c: e00a b.n 8014694 <tcp_input+0x7cc>
|
|
goto dropped;
|
|
801467e: bf00 nop
|
|
8014680: e004 b.n 801468c <tcp_input+0x7c4>
|
|
dropped:
|
|
8014682: bf00 nop
|
|
8014684: e002 b.n 801468c <tcp_input+0x7c4>
|
|
goto dropped;
|
|
8014686: bf00 nop
|
|
8014688: e000 b.n 801468c <tcp_input+0x7c4>
|
|
goto dropped;
|
|
801468a: bf00 nop
|
|
TCP_STATS_INC(tcp.drop);
|
|
MIB2_STATS_INC(mib2.tcpinerrs);
|
|
pbuf_free(p);
|
|
801468c: 6878 ldr r0, [r7, #4]
|
|
801468e: f7fd fde3 bl 8012258 <pbuf_free>
|
|
8014692: e000 b.n 8014696 <tcp_input+0x7ce>
|
|
return;
|
|
8014694: bf00 nop
|
|
}
|
|
8014696: 3724 adds r7, #36 ; 0x24
|
|
8014698: 46bd mov sp, r7
|
|
801469a: bd90 pop {r4, r7, pc}
|
|
801469c: 2000f810 .word 0x2000f810
|
|
80146a0: 20008759 .word 0x20008759
|
|
80146a4: 2000f7fc .word 0x2000f7fc
|
|
80146a8: 20008754 .word 0x20008754
|
|
80146ac: 2000875c .word 0x2000875c
|
|
80146b0: 0801f2b0 .word 0x0801f2b0
|
|
80146b4: 0801f464 .word 0x0801f464
|
|
80146b8: 0801f2fc .word 0x0801f2fc
|
|
80146bc: 2000872c .word 0x2000872c
|
|
80146c0: 2000873c .word 0x2000873c
|
|
80146c4: 20008750 .word 0x20008750
|
|
80146c8: 20008756 .word 0x20008756
|
|
80146cc: 2000874c .word 0x2000874c
|
|
80146d0: 2000c0d8 .word 0x2000c0d8
|
|
80146d4: 2000c0dc .word 0x2000c0dc
|
|
|
|
080146d8 <tcp_input_delayed_close>:
|
|
* any more.
|
|
* @returns 1 if the pcb has been closed and deallocated, 0 otherwise
|
|
*/
|
|
static int
|
|
tcp_input_delayed_close(struct tcp_pcb *pcb)
|
|
{
|
|
80146d8: b580 push {r7, lr}
|
|
80146da: b082 sub sp, #8
|
|
80146dc: af00 add r7, sp, #0
|
|
80146de: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL);
|
|
80146e0: 687b ldr r3, [r7, #4]
|
|
80146e2: 2b00 cmp r3, #0
|
|
80146e4: d106 bne.n 80146f4 <tcp_input_delayed_close+0x1c>
|
|
80146e6: 4b17 ldr r3, [pc, #92] ; (8014744 <tcp_input_delayed_close+0x6c>)
|
|
80146e8: f240 225a movw r2, #602 ; 0x25a
|
|
80146ec: 4916 ldr r1, [pc, #88] ; (8014748 <tcp_input_delayed_close+0x70>)
|
|
80146ee: 4817 ldr r0, [pc, #92] ; (801474c <tcp_input_delayed_close+0x74>)
|
|
80146f0: f008 fae2 bl 801ccb8 <iprintf>
|
|
|
|
if (recv_flags & TF_CLOSED) {
|
|
80146f4: 4b16 ldr r3, [pc, #88] ; (8014750 <tcp_input_delayed_close+0x78>)
|
|
80146f6: 781b ldrb r3, [r3, #0]
|
|
80146f8: f003 0310 and.w r3, r3, #16
|
|
80146fc: 2b00 cmp r3, #0
|
|
80146fe: d01c beq.n 801473a <tcp_input_delayed_close+0x62>
|
|
/* The connection has been closed and we will deallocate the
|
|
PCB. */
|
|
if (!(pcb->flags & TF_RXCLOSED)) {
|
|
8014700: 687b ldr r3, [r7, #4]
|
|
8014702: 8b5b ldrh r3, [r3, #26]
|
|
8014704: f003 0310 and.w r3, r3, #16
|
|
8014708: 2b00 cmp r3, #0
|
|
801470a: d10d bne.n 8014728 <tcp_input_delayed_close+0x50>
|
|
/* Connection closed although the application has only shut down the
|
|
tx side: call the PCB's err callback and indicate the closure to
|
|
ensure the application doesn't continue using the PCB. */
|
|
TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD);
|
|
801470c: 687b ldr r3, [r7, #4]
|
|
801470e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
8014712: 2b00 cmp r3, #0
|
|
8014714: d008 beq.n 8014728 <tcp_input_delayed_close+0x50>
|
|
8014716: 687b ldr r3, [r7, #4]
|
|
8014718: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
|
|
801471c: 687a ldr r2, [r7, #4]
|
|
801471e: 6912 ldr r2, [r2, #16]
|
|
8014720: f06f 010e mvn.w r1, #14
|
|
8014724: 4610 mov r0, r2
|
|
8014726: 4798 blx r3
|
|
}
|
|
tcp_pcb_remove(&tcp_active_pcbs, pcb);
|
|
8014728: 6879 ldr r1, [r7, #4]
|
|
801472a: 480a ldr r0, [pc, #40] ; (8014754 <tcp_input_delayed_close+0x7c>)
|
|
801472c: f7ff fa54 bl 8013bd8 <tcp_pcb_remove>
|
|
tcp_free(pcb);
|
|
8014730: 6878 ldr r0, [r7, #4]
|
|
8014732: f7fe f84d bl 80127d0 <tcp_free>
|
|
return 1;
|
|
8014736: 2301 movs r3, #1
|
|
8014738: e000 b.n 801473c <tcp_input_delayed_close+0x64>
|
|
}
|
|
return 0;
|
|
801473a: 2300 movs r3, #0
|
|
}
|
|
801473c: 4618 mov r0, r3
|
|
801473e: 3708 adds r7, #8
|
|
8014740: 46bd mov sp, r7
|
|
8014742: bd80 pop {r7, pc}
|
|
8014744: 0801f2b0 .word 0x0801f2b0
|
|
8014748: 0801f480 .word 0x0801f480
|
|
801474c: 0801f2fc .word 0x0801f2fc
|
|
8014750: 20008759 .word 0x20008759
|
|
8014754: 2000f7fc .word 0x2000f7fc
|
|
|
|
08014758 <tcp_listen_input>:
|
|
* @note the segment which arrived is saved in global variables, therefore only the pcb
|
|
* involved is passed as a parameter to this function
|
|
*/
|
|
static void
|
|
tcp_listen_input(struct tcp_pcb_listen *pcb)
|
|
{
|
|
8014758: b590 push {r4, r7, lr}
|
|
801475a: b08b sub sp, #44 ; 0x2c
|
|
801475c: af04 add r7, sp, #16
|
|
801475e: 6078 str r0, [r7, #4]
|
|
struct tcp_pcb *npcb;
|
|
u32_t iss;
|
|
err_t rc;
|
|
|
|
if (flags & TCP_RST) {
|
|
8014760: 4b6f ldr r3, [pc, #444] ; (8014920 <tcp_listen_input+0x1c8>)
|
|
8014762: 781b ldrb r3, [r3, #0]
|
|
8014764: f003 0304 and.w r3, r3, #4
|
|
8014768: 2b00 cmp r3, #0
|
|
801476a: f040 80d3 bne.w 8014914 <tcp_listen_input+0x1bc>
|
|
/* An incoming RST should be ignored. Return. */
|
|
return;
|
|
}
|
|
|
|
LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL);
|
|
801476e: 687b ldr r3, [r7, #4]
|
|
8014770: 2b00 cmp r3, #0
|
|
8014772: d106 bne.n 8014782 <tcp_listen_input+0x2a>
|
|
8014774: 4b6b ldr r3, [pc, #428] ; (8014924 <tcp_listen_input+0x1cc>)
|
|
8014776: f240 2281 movw r2, #641 ; 0x281
|
|
801477a: 496b ldr r1, [pc, #428] ; (8014928 <tcp_listen_input+0x1d0>)
|
|
801477c: 486b ldr r0, [pc, #428] ; (801492c <tcp_listen_input+0x1d4>)
|
|
801477e: f008 fa9b bl 801ccb8 <iprintf>
|
|
|
|
/* In the LISTEN state, we check for incoming SYN segments,
|
|
creates a new PCB, and responds with a SYN|ACK. */
|
|
if (flags & TCP_ACK) {
|
|
8014782: 4b67 ldr r3, [pc, #412] ; (8014920 <tcp_listen_input+0x1c8>)
|
|
8014784: 781b ldrb r3, [r3, #0]
|
|
8014786: f003 0310 and.w r3, r3, #16
|
|
801478a: 2b00 cmp r3, #0
|
|
801478c: d019 beq.n 80147c2 <tcp_listen_input+0x6a>
|
|
/* For incoming segments with the ACK flag set, respond with a
|
|
RST. */
|
|
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n"));
|
|
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
801478e: 4b68 ldr r3, [pc, #416] ; (8014930 <tcp_listen_input+0x1d8>)
|
|
8014790: 6819 ldr r1, [r3, #0]
|
|
8014792: 4b68 ldr r3, [pc, #416] ; (8014934 <tcp_listen_input+0x1dc>)
|
|
8014794: 881b ldrh r3, [r3, #0]
|
|
8014796: 461a mov r2, r3
|
|
8014798: 4b67 ldr r3, [pc, #412] ; (8014938 <tcp_listen_input+0x1e0>)
|
|
801479a: 681b ldr r3, [r3, #0]
|
|
801479c: 18d0 adds r0, r2, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
801479e: 4b67 ldr r3, [pc, #412] ; (801493c <tcp_listen_input+0x1e4>)
|
|
80147a0: 681b ldr r3, [r3, #0]
|
|
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
80147a2: 885b ldrh r3, [r3, #2]
|
|
80147a4: b29b uxth r3, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
80147a6: 4a65 ldr r2, [pc, #404] ; (801493c <tcp_listen_input+0x1e4>)
|
|
80147a8: 6812 ldr r2, [r2, #0]
|
|
tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
80147aa: 8812 ldrh r2, [r2, #0]
|
|
80147ac: b292 uxth r2, r2
|
|
80147ae: 9202 str r2, [sp, #8]
|
|
80147b0: 9301 str r3, [sp, #4]
|
|
80147b2: 4b63 ldr r3, [pc, #396] ; (8014940 <tcp_listen_input+0x1e8>)
|
|
80147b4: 9300 str r3, [sp, #0]
|
|
80147b6: 4b63 ldr r3, [pc, #396] ; (8014944 <tcp_listen_input+0x1ec>)
|
|
80147b8: 4602 mov r2, r0
|
|
80147ba: 6878 ldr r0, [r7, #4]
|
|
80147bc: f002 ff90 bl 80176e0 <tcp_rst>
|
|
tcp_abandon(npcb, 0);
|
|
return;
|
|
}
|
|
tcp_output(npcb);
|
|
}
|
|
return;
|
|
80147c0: e0aa b.n 8014918 <tcp_listen_input+0x1c0>
|
|
} else if (flags & TCP_SYN) {
|
|
80147c2: 4b57 ldr r3, [pc, #348] ; (8014920 <tcp_listen_input+0x1c8>)
|
|
80147c4: 781b ldrb r3, [r3, #0]
|
|
80147c6: f003 0302 and.w r3, r3, #2
|
|
80147ca: 2b00 cmp r3, #0
|
|
80147cc: f000 80a4 beq.w 8014918 <tcp_listen_input+0x1c0>
|
|
npcb = tcp_alloc(pcb->prio);
|
|
80147d0: 687b ldr r3, [r7, #4]
|
|
80147d2: 7d5b ldrb r3, [r3, #21]
|
|
80147d4: 4618 mov r0, r3
|
|
80147d6: f7ff f92b bl 8013a30 <tcp_alloc>
|
|
80147da: 6178 str r0, [r7, #20]
|
|
if (npcb == NULL) {
|
|
80147dc: 697b ldr r3, [r7, #20]
|
|
80147de: 2b00 cmp r3, #0
|
|
80147e0: d111 bne.n 8014806 <tcp_listen_input+0xae>
|
|
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
|
|
80147e2: 687b ldr r3, [r7, #4]
|
|
80147e4: 699b ldr r3, [r3, #24]
|
|
80147e6: 2b00 cmp r3, #0
|
|
80147e8: d00a beq.n 8014800 <tcp_listen_input+0xa8>
|
|
80147ea: 687b ldr r3, [r7, #4]
|
|
80147ec: 699b ldr r3, [r3, #24]
|
|
80147ee: 687a ldr r2, [r7, #4]
|
|
80147f0: 6910 ldr r0, [r2, #16]
|
|
80147f2: f04f 32ff mov.w r2, #4294967295
|
|
80147f6: 2100 movs r1, #0
|
|
80147f8: 4798 blx r3
|
|
80147fa: 4603 mov r3, r0
|
|
80147fc: 73bb strb r3, [r7, #14]
|
|
return;
|
|
80147fe: e08c b.n 801491a <tcp_listen_input+0x1c2>
|
|
TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err);
|
|
8014800: 23f0 movs r3, #240 ; 0xf0
|
|
8014802: 73bb strb r3, [r7, #14]
|
|
return;
|
|
8014804: e089 b.n 801491a <tcp_listen_input+0x1c2>
|
|
ip_addr_copy(npcb->local_ip, *ip_current_dest_addr());
|
|
8014806: 4b50 ldr r3, [pc, #320] ; (8014948 <tcp_listen_input+0x1f0>)
|
|
8014808: 695a ldr r2, [r3, #20]
|
|
801480a: 697b ldr r3, [r7, #20]
|
|
801480c: 601a str r2, [r3, #0]
|
|
ip_addr_copy(npcb->remote_ip, *ip_current_src_addr());
|
|
801480e: 4b4e ldr r3, [pc, #312] ; (8014948 <tcp_listen_input+0x1f0>)
|
|
8014810: 691a ldr r2, [r3, #16]
|
|
8014812: 697b ldr r3, [r7, #20]
|
|
8014814: 605a str r2, [r3, #4]
|
|
npcb->local_port = pcb->local_port;
|
|
8014816: 687b ldr r3, [r7, #4]
|
|
8014818: 8ada ldrh r2, [r3, #22]
|
|
801481a: 697b ldr r3, [r7, #20]
|
|
801481c: 82da strh r2, [r3, #22]
|
|
npcb->remote_port = tcphdr->src;
|
|
801481e: 4b47 ldr r3, [pc, #284] ; (801493c <tcp_listen_input+0x1e4>)
|
|
8014820: 681b ldr r3, [r3, #0]
|
|
8014822: 881b ldrh r3, [r3, #0]
|
|
8014824: b29a uxth r2, r3
|
|
8014826: 697b ldr r3, [r7, #20]
|
|
8014828: 831a strh r2, [r3, #24]
|
|
npcb->state = SYN_RCVD;
|
|
801482a: 697b ldr r3, [r7, #20]
|
|
801482c: 2203 movs r2, #3
|
|
801482e: 751a strb r2, [r3, #20]
|
|
npcb->rcv_nxt = seqno + 1;
|
|
8014830: 4b41 ldr r3, [pc, #260] ; (8014938 <tcp_listen_input+0x1e0>)
|
|
8014832: 681b ldr r3, [r3, #0]
|
|
8014834: 1c5a adds r2, r3, #1
|
|
8014836: 697b ldr r3, [r7, #20]
|
|
8014838: 625a str r2, [r3, #36] ; 0x24
|
|
npcb->rcv_ann_right_edge = npcb->rcv_nxt;
|
|
801483a: 697b ldr r3, [r7, #20]
|
|
801483c: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
801483e: 697b ldr r3, [r7, #20]
|
|
8014840: 62da str r2, [r3, #44] ; 0x2c
|
|
iss = tcp_next_iss(npcb);
|
|
8014842: 6978 ldr r0, [r7, #20]
|
|
8014844: f7ff fa5c bl 8013d00 <tcp_next_iss>
|
|
8014848: 6138 str r0, [r7, #16]
|
|
npcb->snd_wl2 = iss;
|
|
801484a: 697b ldr r3, [r7, #20]
|
|
801484c: 693a ldr r2, [r7, #16]
|
|
801484e: 659a str r2, [r3, #88] ; 0x58
|
|
npcb->snd_nxt = iss;
|
|
8014850: 697b ldr r3, [r7, #20]
|
|
8014852: 693a ldr r2, [r7, #16]
|
|
8014854: 651a str r2, [r3, #80] ; 0x50
|
|
npcb->lastack = iss;
|
|
8014856: 697b ldr r3, [r7, #20]
|
|
8014858: 693a ldr r2, [r7, #16]
|
|
801485a: 645a str r2, [r3, #68] ; 0x44
|
|
npcb->snd_lbb = iss;
|
|
801485c: 697b ldr r3, [r7, #20]
|
|
801485e: 693a ldr r2, [r7, #16]
|
|
8014860: 65da str r2, [r3, #92] ; 0x5c
|
|
npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */
|
|
8014862: 4b35 ldr r3, [pc, #212] ; (8014938 <tcp_listen_input+0x1e0>)
|
|
8014864: 681b ldr r3, [r3, #0]
|
|
8014866: 1e5a subs r2, r3, #1
|
|
8014868: 697b ldr r3, [r7, #20]
|
|
801486a: 655a str r2, [r3, #84] ; 0x54
|
|
npcb->callback_arg = pcb->callback_arg;
|
|
801486c: 687b ldr r3, [r7, #4]
|
|
801486e: 691a ldr r2, [r3, #16]
|
|
8014870: 697b ldr r3, [r7, #20]
|
|
8014872: 611a str r2, [r3, #16]
|
|
npcb->listener = pcb;
|
|
8014874: 697b ldr r3, [r7, #20]
|
|
8014876: 687a ldr r2, [r7, #4]
|
|
8014878: 67da str r2, [r3, #124] ; 0x7c
|
|
npcb->so_options = pcb->so_options & SOF_INHERITED;
|
|
801487a: 687b ldr r3, [r7, #4]
|
|
801487c: 7a5b ldrb r3, [r3, #9]
|
|
801487e: f003 030c and.w r3, r3, #12
|
|
8014882: b2da uxtb r2, r3
|
|
8014884: 697b ldr r3, [r7, #20]
|
|
8014886: 725a strb r2, [r3, #9]
|
|
npcb->netif_idx = pcb->netif_idx;
|
|
8014888: 687b ldr r3, [r7, #4]
|
|
801488a: 7a1a ldrb r2, [r3, #8]
|
|
801488c: 697b ldr r3, [r7, #20]
|
|
801488e: 721a strb r2, [r3, #8]
|
|
TCP_REG_ACTIVE(npcb);
|
|
8014890: 4b2e ldr r3, [pc, #184] ; (801494c <tcp_listen_input+0x1f4>)
|
|
8014892: 681a ldr r2, [r3, #0]
|
|
8014894: 697b ldr r3, [r7, #20]
|
|
8014896: 60da str r2, [r3, #12]
|
|
8014898: 4a2c ldr r2, [pc, #176] ; (801494c <tcp_listen_input+0x1f4>)
|
|
801489a: 697b ldr r3, [r7, #20]
|
|
801489c: 6013 str r3, [r2, #0]
|
|
801489e: f003 f8e1 bl 8017a64 <tcp_timer_needed>
|
|
80148a2: 4b2b ldr r3, [pc, #172] ; (8014950 <tcp_listen_input+0x1f8>)
|
|
80148a4: 2201 movs r2, #1
|
|
80148a6: 701a strb r2, [r3, #0]
|
|
tcp_parseopt(npcb);
|
|
80148a8: 6978 ldr r0, [r7, #20]
|
|
80148aa: f001 fd8f bl 80163cc <tcp_parseopt>
|
|
npcb->snd_wnd = tcphdr->wnd;
|
|
80148ae: 4b23 ldr r3, [pc, #140] ; (801493c <tcp_listen_input+0x1e4>)
|
|
80148b0: 681b ldr r3, [r3, #0]
|
|
80148b2: 89db ldrh r3, [r3, #14]
|
|
80148b4: b29a uxth r2, r3
|
|
80148b6: 697b ldr r3, [r7, #20]
|
|
80148b8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
|
|
npcb->snd_wnd_max = npcb->snd_wnd;
|
|
80148bc: 697b ldr r3, [r7, #20]
|
|
80148be: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
|
|
80148c2: 697b ldr r3, [r7, #20]
|
|
80148c4: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
|
|
npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip);
|
|
80148c8: 697b ldr r3, [r7, #20]
|
|
80148ca: 8e5c ldrh r4, [r3, #50] ; 0x32
|
|
80148cc: 697b ldr r3, [r7, #20]
|
|
80148ce: 3304 adds r3, #4
|
|
80148d0: 4618 mov r0, r3
|
|
80148d2: f006 fe7d bl 801b5d0 <ip4_route>
|
|
80148d6: 4601 mov r1, r0
|
|
80148d8: 697b ldr r3, [r7, #20]
|
|
80148da: 3304 adds r3, #4
|
|
80148dc: 461a mov r2, r3
|
|
80148de: 4620 mov r0, r4
|
|
80148e0: f7ff fa34 bl 8013d4c <tcp_eff_send_mss_netif>
|
|
80148e4: 4603 mov r3, r0
|
|
80148e6: 461a mov r2, r3
|
|
80148e8: 697b ldr r3, [r7, #20]
|
|
80148ea: 865a strh r2, [r3, #50] ; 0x32
|
|
rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK);
|
|
80148ec: 2112 movs r1, #18
|
|
80148ee: 6978 ldr r0, [r7, #20]
|
|
80148f0: f002 f842 bl 8016978 <tcp_enqueue_flags>
|
|
80148f4: 4603 mov r3, r0
|
|
80148f6: 73fb strb r3, [r7, #15]
|
|
if (rc != ERR_OK) {
|
|
80148f8: f997 300f ldrsb.w r3, [r7, #15]
|
|
80148fc: 2b00 cmp r3, #0
|
|
80148fe: d004 beq.n 801490a <tcp_listen_input+0x1b2>
|
|
tcp_abandon(npcb, 0);
|
|
8014900: 2100 movs r1, #0
|
|
8014902: 6978 ldr r0, [r7, #20]
|
|
8014904: f7fe f986 bl 8012c14 <tcp_abandon>
|
|
return;
|
|
8014908: e007 b.n 801491a <tcp_listen_input+0x1c2>
|
|
tcp_output(npcb);
|
|
801490a: 6978 ldr r0, [r7, #20]
|
|
801490c: f002 f922 bl 8016b54 <tcp_output>
|
|
return;
|
|
8014910: bf00 nop
|
|
8014912: e001 b.n 8014918 <tcp_listen_input+0x1c0>
|
|
return;
|
|
8014914: bf00 nop
|
|
8014916: e000 b.n 801491a <tcp_listen_input+0x1c2>
|
|
return;
|
|
8014918: bf00 nop
|
|
}
|
|
801491a: 371c adds r7, #28
|
|
801491c: 46bd mov sp, r7
|
|
801491e: bd90 pop {r4, r7, pc}
|
|
8014920: 20008758 .word 0x20008758
|
|
8014924: 0801f2b0 .word 0x0801f2b0
|
|
8014928: 0801f4a8 .word 0x0801f4a8
|
|
801492c: 0801f2fc .word 0x0801f2fc
|
|
8014930: 20008750 .word 0x20008750
|
|
8014934: 20008756 .word 0x20008756
|
|
8014938: 2000874c .word 0x2000874c
|
|
801493c: 2000873c .word 0x2000873c
|
|
8014940: 2000c0d8 .word 0x2000c0d8
|
|
8014944: 2000c0dc .word 0x2000c0dc
|
|
8014948: 2000c0c8 .word 0x2000c0c8
|
|
801494c: 2000f7fc .word 0x2000f7fc
|
|
8014950: 2000f7f8 .word 0x2000f7f8
|
|
|
|
08014954 <tcp_timewait_input>:
|
|
* @note the segment which arrived is saved in global variables, therefore only the pcb
|
|
* involved is passed as a parameter to this function
|
|
*/
|
|
static void
|
|
tcp_timewait_input(struct tcp_pcb *pcb)
|
|
{
|
|
8014954: b580 push {r7, lr}
|
|
8014956: b086 sub sp, #24
|
|
8014958: af04 add r7, sp, #16
|
|
801495a: 6078 str r0, [r7, #4]
|
|
/* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */
|
|
/* RFC 793 3.9 Event Processing - Segment Arrives:
|
|
* - first check sequence number - we skip that one in TIME_WAIT (always
|
|
* acceptable since we only send ACKs)
|
|
* - second check the RST bit (... return) */
|
|
if (flags & TCP_RST) {
|
|
801495c: 4b30 ldr r3, [pc, #192] ; (8014a20 <tcp_timewait_input+0xcc>)
|
|
801495e: 781b ldrb r3, [r3, #0]
|
|
8014960: f003 0304 and.w r3, r3, #4
|
|
8014964: 2b00 cmp r3, #0
|
|
8014966: d154 bne.n 8014a12 <tcp_timewait_input+0xbe>
|
|
return;
|
|
}
|
|
|
|
LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL);
|
|
8014968: 687b ldr r3, [r7, #4]
|
|
801496a: 2b00 cmp r3, #0
|
|
801496c: d106 bne.n 801497c <tcp_timewait_input+0x28>
|
|
801496e: 4b2d ldr r3, [pc, #180] ; (8014a24 <tcp_timewait_input+0xd0>)
|
|
8014970: f240 22ee movw r2, #750 ; 0x2ee
|
|
8014974: 492c ldr r1, [pc, #176] ; (8014a28 <tcp_timewait_input+0xd4>)
|
|
8014976: 482d ldr r0, [pc, #180] ; (8014a2c <tcp_timewait_input+0xd8>)
|
|
8014978: f008 f99e bl 801ccb8 <iprintf>
|
|
|
|
/* - fourth, check the SYN bit, */
|
|
if (flags & TCP_SYN) {
|
|
801497c: 4b28 ldr r3, [pc, #160] ; (8014a20 <tcp_timewait_input+0xcc>)
|
|
801497e: 781b ldrb r3, [r3, #0]
|
|
8014980: f003 0302 and.w r3, r3, #2
|
|
8014984: 2b00 cmp r3, #0
|
|
8014986: d02a beq.n 80149de <tcp_timewait_input+0x8a>
|
|
/* If an incoming segment is not acceptable, an acknowledgment
|
|
should be sent in reply */
|
|
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) {
|
|
8014988: 4b29 ldr r3, [pc, #164] ; (8014a30 <tcp_timewait_input+0xdc>)
|
|
801498a: 681a ldr r2, [r3, #0]
|
|
801498c: 687b ldr r3, [r7, #4]
|
|
801498e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8014990: 1ad3 subs r3, r2, r3
|
|
8014992: 2b00 cmp r3, #0
|
|
8014994: db2d blt.n 80149f2 <tcp_timewait_input+0x9e>
|
|
8014996: 4b26 ldr r3, [pc, #152] ; (8014a30 <tcp_timewait_input+0xdc>)
|
|
8014998: 681a ldr r2, [r3, #0]
|
|
801499a: 687b ldr r3, [r7, #4]
|
|
801499c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801499e: 6879 ldr r1, [r7, #4]
|
|
80149a0: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
80149a2: 440b add r3, r1
|
|
80149a4: 1ad3 subs r3, r2, r3
|
|
80149a6: 2b00 cmp r3, #0
|
|
80149a8: dc23 bgt.n 80149f2 <tcp_timewait_input+0x9e>
|
|
/* If the SYN is in the window it is an error, send a reset */
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
80149aa: 4b22 ldr r3, [pc, #136] ; (8014a34 <tcp_timewait_input+0xe0>)
|
|
80149ac: 6819 ldr r1, [r3, #0]
|
|
80149ae: 4b22 ldr r3, [pc, #136] ; (8014a38 <tcp_timewait_input+0xe4>)
|
|
80149b0: 881b ldrh r3, [r3, #0]
|
|
80149b2: 461a mov r2, r3
|
|
80149b4: 4b1e ldr r3, [pc, #120] ; (8014a30 <tcp_timewait_input+0xdc>)
|
|
80149b6: 681b ldr r3, [r3, #0]
|
|
80149b8: 18d0 adds r0, r2, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
80149ba: 4b20 ldr r3, [pc, #128] ; (8014a3c <tcp_timewait_input+0xe8>)
|
|
80149bc: 681b ldr r3, [r3, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
80149be: 885b ldrh r3, [r3, #2]
|
|
80149c0: b29b uxth r3, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
80149c2: 4a1e ldr r2, [pc, #120] ; (8014a3c <tcp_timewait_input+0xe8>)
|
|
80149c4: 6812 ldr r2, [r2, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
80149c6: 8812 ldrh r2, [r2, #0]
|
|
80149c8: b292 uxth r2, r2
|
|
80149ca: 9202 str r2, [sp, #8]
|
|
80149cc: 9301 str r3, [sp, #4]
|
|
80149ce: 4b1c ldr r3, [pc, #112] ; (8014a40 <tcp_timewait_input+0xec>)
|
|
80149d0: 9300 str r3, [sp, #0]
|
|
80149d2: 4b1c ldr r3, [pc, #112] ; (8014a44 <tcp_timewait_input+0xf0>)
|
|
80149d4: 4602 mov r2, r0
|
|
80149d6: 6878 ldr r0, [r7, #4]
|
|
80149d8: f002 fe82 bl 80176e0 <tcp_rst>
|
|
return;
|
|
80149dc: e01c b.n 8014a18 <tcp_timewait_input+0xc4>
|
|
}
|
|
} else if (flags & TCP_FIN) {
|
|
80149de: 4b10 ldr r3, [pc, #64] ; (8014a20 <tcp_timewait_input+0xcc>)
|
|
80149e0: 781b ldrb r3, [r3, #0]
|
|
80149e2: f003 0301 and.w r3, r3, #1
|
|
80149e6: 2b00 cmp r3, #0
|
|
80149e8: d003 beq.n 80149f2 <tcp_timewait_input+0x9e>
|
|
/* - eighth, check the FIN bit: Remain in the TIME-WAIT state.
|
|
Restart the 2 MSL time-wait timeout.*/
|
|
pcb->tmr = tcp_ticks;
|
|
80149ea: 4b17 ldr r3, [pc, #92] ; (8014a48 <tcp_timewait_input+0xf4>)
|
|
80149ec: 681a ldr r2, [r3, #0]
|
|
80149ee: 687b ldr r3, [r7, #4]
|
|
80149f0: 621a str r2, [r3, #32]
|
|
}
|
|
|
|
if ((tcplen > 0)) {
|
|
80149f2: 4b11 ldr r3, [pc, #68] ; (8014a38 <tcp_timewait_input+0xe4>)
|
|
80149f4: 881b ldrh r3, [r3, #0]
|
|
80149f6: 2b00 cmp r3, #0
|
|
80149f8: d00d beq.n 8014a16 <tcp_timewait_input+0xc2>
|
|
/* Acknowledge data, FIN or out-of-window SYN */
|
|
tcp_ack_now(pcb);
|
|
80149fa: 687b ldr r3, [r7, #4]
|
|
80149fc: 8b5b ldrh r3, [r3, #26]
|
|
80149fe: f043 0302 orr.w r3, r3, #2
|
|
8014a02: b29a uxth r2, r3
|
|
8014a04: 687b ldr r3, [r7, #4]
|
|
8014a06: 835a strh r2, [r3, #26]
|
|
tcp_output(pcb);
|
|
8014a08: 6878 ldr r0, [r7, #4]
|
|
8014a0a: f002 f8a3 bl 8016b54 <tcp_output>
|
|
}
|
|
return;
|
|
8014a0e: bf00 nop
|
|
8014a10: e001 b.n 8014a16 <tcp_timewait_input+0xc2>
|
|
return;
|
|
8014a12: bf00 nop
|
|
8014a14: e000 b.n 8014a18 <tcp_timewait_input+0xc4>
|
|
return;
|
|
8014a16: bf00 nop
|
|
}
|
|
8014a18: 3708 adds r7, #8
|
|
8014a1a: 46bd mov sp, r7
|
|
8014a1c: bd80 pop {r7, pc}
|
|
8014a1e: bf00 nop
|
|
8014a20: 20008758 .word 0x20008758
|
|
8014a24: 0801f2b0 .word 0x0801f2b0
|
|
8014a28: 0801f4c8 .word 0x0801f4c8
|
|
8014a2c: 0801f2fc .word 0x0801f2fc
|
|
8014a30: 2000874c .word 0x2000874c
|
|
8014a34: 20008750 .word 0x20008750
|
|
8014a38: 20008756 .word 0x20008756
|
|
8014a3c: 2000873c .word 0x2000873c
|
|
8014a40: 2000c0d8 .word 0x2000c0d8
|
|
8014a44: 2000c0dc .word 0x2000c0dc
|
|
8014a48: 2000f800 .word 0x2000f800
|
|
|
|
08014a4c <tcp_process>:
|
|
* @note the segment which arrived is saved in global variables, therefore only the pcb
|
|
* involved is passed as a parameter to this function
|
|
*/
|
|
static err_t
|
|
tcp_process(struct tcp_pcb *pcb)
|
|
{
|
|
8014a4c: b590 push {r4, r7, lr}
|
|
8014a4e: b08d sub sp, #52 ; 0x34
|
|
8014a50: af04 add r7, sp, #16
|
|
8014a52: 6078 str r0, [r7, #4]
|
|
struct tcp_seg *rseg;
|
|
u8_t acceptable = 0;
|
|
8014a54: 2300 movs r3, #0
|
|
8014a56: 76fb strb r3, [r7, #27]
|
|
err_t err;
|
|
|
|
err = ERR_OK;
|
|
8014a58: 2300 movs r3, #0
|
|
8014a5a: 76bb strb r3, [r7, #26]
|
|
|
|
LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL);
|
|
8014a5c: 687b ldr r3, [r7, #4]
|
|
8014a5e: 2b00 cmp r3, #0
|
|
8014a60: d106 bne.n 8014a70 <tcp_process+0x24>
|
|
8014a62: 4ba5 ldr r3, [pc, #660] ; (8014cf8 <tcp_process+0x2ac>)
|
|
8014a64: f44f 7247 mov.w r2, #796 ; 0x31c
|
|
8014a68: 49a4 ldr r1, [pc, #656] ; (8014cfc <tcp_process+0x2b0>)
|
|
8014a6a: 48a5 ldr r0, [pc, #660] ; (8014d00 <tcp_process+0x2b4>)
|
|
8014a6c: f008 f924 bl 801ccb8 <iprintf>
|
|
|
|
/* Process incoming RST segments. */
|
|
if (flags & TCP_RST) {
|
|
8014a70: 4ba4 ldr r3, [pc, #656] ; (8014d04 <tcp_process+0x2b8>)
|
|
8014a72: 781b ldrb r3, [r3, #0]
|
|
8014a74: f003 0304 and.w r3, r3, #4
|
|
8014a78: 2b00 cmp r3, #0
|
|
8014a7a: d04e beq.n 8014b1a <tcp_process+0xce>
|
|
/* First, determine if the reset is acceptable. */
|
|
if (pcb->state == SYN_SENT) {
|
|
8014a7c: 687b ldr r3, [r7, #4]
|
|
8014a7e: 7d1b ldrb r3, [r3, #20]
|
|
8014a80: 2b02 cmp r3, #2
|
|
8014a82: d108 bne.n 8014a96 <tcp_process+0x4a>
|
|
/* "In the SYN-SENT state (a RST received in response to an initial SYN),
|
|
the RST is acceptable if the ACK field acknowledges the SYN." */
|
|
if (ackno == pcb->snd_nxt) {
|
|
8014a84: 687b ldr r3, [r7, #4]
|
|
8014a86: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
8014a88: 4b9f ldr r3, [pc, #636] ; (8014d08 <tcp_process+0x2bc>)
|
|
8014a8a: 681b ldr r3, [r3, #0]
|
|
8014a8c: 429a cmp r2, r3
|
|
8014a8e: d123 bne.n 8014ad8 <tcp_process+0x8c>
|
|
acceptable = 1;
|
|
8014a90: 2301 movs r3, #1
|
|
8014a92: 76fb strb r3, [r7, #27]
|
|
8014a94: e020 b.n 8014ad8 <tcp_process+0x8c>
|
|
}
|
|
} else {
|
|
/* "In all states except SYN-SENT, all reset (RST) segments are validated
|
|
by checking their SEQ-fields." */
|
|
if (seqno == pcb->rcv_nxt) {
|
|
8014a96: 687b ldr r3, [r7, #4]
|
|
8014a98: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8014a9a: 4b9c ldr r3, [pc, #624] ; (8014d0c <tcp_process+0x2c0>)
|
|
8014a9c: 681b ldr r3, [r3, #0]
|
|
8014a9e: 429a cmp r2, r3
|
|
8014aa0: d102 bne.n 8014aa8 <tcp_process+0x5c>
|
|
acceptable = 1;
|
|
8014aa2: 2301 movs r3, #1
|
|
8014aa4: 76fb strb r3, [r7, #27]
|
|
8014aa6: e017 b.n 8014ad8 <tcp_process+0x8c>
|
|
} else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
|
|
8014aa8: 4b98 ldr r3, [pc, #608] ; (8014d0c <tcp_process+0x2c0>)
|
|
8014aaa: 681a ldr r2, [r3, #0]
|
|
8014aac: 687b ldr r3, [r7, #4]
|
|
8014aae: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8014ab0: 1ad3 subs r3, r2, r3
|
|
8014ab2: 2b00 cmp r3, #0
|
|
8014ab4: db10 blt.n 8014ad8 <tcp_process+0x8c>
|
|
8014ab6: 4b95 ldr r3, [pc, #596] ; (8014d0c <tcp_process+0x2c0>)
|
|
8014ab8: 681a ldr r2, [r3, #0]
|
|
8014aba: 687b ldr r3, [r7, #4]
|
|
8014abc: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8014abe: 6879 ldr r1, [r7, #4]
|
|
8014ac0: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
8014ac2: 440b add r3, r1
|
|
8014ac4: 1ad3 subs r3, r2, r3
|
|
8014ac6: 2b00 cmp r3, #0
|
|
8014ac8: dc06 bgt.n 8014ad8 <tcp_process+0x8c>
|
|
pcb->rcv_nxt + pcb->rcv_wnd)) {
|
|
/* If the sequence number is inside the window, we send a challenge ACK
|
|
and wait for a re-send with matching sequence number.
|
|
This follows RFC 5961 section 3.2 and addresses CVE-2004-0230
|
|
(RST spoofing attack), which is present in RFC 793 RST handling. */
|
|
tcp_ack_now(pcb);
|
|
8014aca: 687b ldr r3, [r7, #4]
|
|
8014acc: 8b5b ldrh r3, [r3, #26]
|
|
8014ace: f043 0302 orr.w r3, r3, #2
|
|
8014ad2: b29a uxth r2, r3
|
|
8014ad4: 687b ldr r3, [r7, #4]
|
|
8014ad6: 835a strh r2, [r3, #26]
|
|
}
|
|
}
|
|
|
|
if (acceptable) {
|
|
8014ad8: 7efb ldrb r3, [r7, #27]
|
|
8014ada: 2b00 cmp r3, #0
|
|
8014adc: d01b beq.n 8014b16 <tcp_process+0xca>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n"));
|
|
LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED);
|
|
8014ade: 687b ldr r3, [r7, #4]
|
|
8014ae0: 7d1b ldrb r3, [r3, #20]
|
|
8014ae2: 2b00 cmp r3, #0
|
|
8014ae4: d106 bne.n 8014af4 <tcp_process+0xa8>
|
|
8014ae6: 4b84 ldr r3, [pc, #528] ; (8014cf8 <tcp_process+0x2ac>)
|
|
8014ae8: f44f 724e mov.w r2, #824 ; 0x338
|
|
8014aec: 4988 ldr r1, [pc, #544] ; (8014d10 <tcp_process+0x2c4>)
|
|
8014aee: 4884 ldr r0, [pc, #528] ; (8014d00 <tcp_process+0x2b4>)
|
|
8014af0: f008 f8e2 bl 801ccb8 <iprintf>
|
|
recv_flags |= TF_RESET;
|
|
8014af4: 4b87 ldr r3, [pc, #540] ; (8014d14 <tcp_process+0x2c8>)
|
|
8014af6: 781b ldrb r3, [r3, #0]
|
|
8014af8: f043 0308 orr.w r3, r3, #8
|
|
8014afc: b2da uxtb r2, r3
|
|
8014afe: 4b85 ldr r3, [pc, #532] ; (8014d14 <tcp_process+0x2c8>)
|
|
8014b00: 701a strb r2, [r3, #0]
|
|
tcp_clear_flags(pcb, TF_ACK_DELAY);
|
|
8014b02: 687b ldr r3, [r7, #4]
|
|
8014b04: 8b5b ldrh r3, [r3, #26]
|
|
8014b06: f023 0301 bic.w r3, r3, #1
|
|
8014b0a: b29a uxth r2, r3
|
|
8014b0c: 687b ldr r3, [r7, #4]
|
|
8014b0e: 835a strh r2, [r3, #26]
|
|
return ERR_RST;
|
|
8014b10: f06f 030d mvn.w r3, #13
|
|
8014b14: e37a b.n 801520c <tcp_process+0x7c0>
|
|
} else {
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
|
|
seqno, pcb->rcv_nxt));
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n",
|
|
seqno, pcb->rcv_nxt));
|
|
return ERR_OK;
|
|
8014b16: 2300 movs r3, #0
|
|
8014b18: e378 b.n 801520c <tcp_process+0x7c0>
|
|
}
|
|
}
|
|
|
|
if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) {
|
|
8014b1a: 4b7a ldr r3, [pc, #488] ; (8014d04 <tcp_process+0x2b8>)
|
|
8014b1c: 781b ldrb r3, [r3, #0]
|
|
8014b1e: f003 0302 and.w r3, r3, #2
|
|
8014b22: 2b00 cmp r3, #0
|
|
8014b24: d010 beq.n 8014b48 <tcp_process+0xfc>
|
|
8014b26: 687b ldr r3, [r7, #4]
|
|
8014b28: 7d1b ldrb r3, [r3, #20]
|
|
8014b2a: 2b02 cmp r3, #2
|
|
8014b2c: d00c beq.n 8014b48 <tcp_process+0xfc>
|
|
8014b2e: 687b ldr r3, [r7, #4]
|
|
8014b30: 7d1b ldrb r3, [r3, #20]
|
|
8014b32: 2b03 cmp r3, #3
|
|
8014b34: d008 beq.n 8014b48 <tcp_process+0xfc>
|
|
/* Cope with new connection attempt after remote end crashed */
|
|
tcp_ack_now(pcb);
|
|
8014b36: 687b ldr r3, [r7, #4]
|
|
8014b38: 8b5b ldrh r3, [r3, #26]
|
|
8014b3a: f043 0302 orr.w r3, r3, #2
|
|
8014b3e: b29a uxth r2, r3
|
|
8014b40: 687b ldr r3, [r7, #4]
|
|
8014b42: 835a strh r2, [r3, #26]
|
|
return ERR_OK;
|
|
8014b44: 2300 movs r3, #0
|
|
8014b46: e361 b.n 801520c <tcp_process+0x7c0>
|
|
}
|
|
|
|
if ((pcb->flags & TF_RXCLOSED) == 0) {
|
|
8014b48: 687b ldr r3, [r7, #4]
|
|
8014b4a: 8b5b ldrh r3, [r3, #26]
|
|
8014b4c: f003 0310 and.w r3, r3, #16
|
|
8014b50: 2b00 cmp r3, #0
|
|
8014b52: d103 bne.n 8014b5c <tcp_process+0x110>
|
|
/* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */
|
|
pcb->tmr = tcp_ticks;
|
|
8014b54: 4b70 ldr r3, [pc, #448] ; (8014d18 <tcp_process+0x2cc>)
|
|
8014b56: 681a ldr r2, [r3, #0]
|
|
8014b58: 687b ldr r3, [r7, #4]
|
|
8014b5a: 621a str r2, [r3, #32]
|
|
}
|
|
pcb->keep_cnt_sent = 0;
|
|
8014b5c: 687b ldr r3, [r7, #4]
|
|
8014b5e: 2200 movs r2, #0
|
|
8014b60: f883 209b strb.w r2, [r3, #155] ; 0x9b
|
|
pcb->persist_probe = 0;
|
|
8014b64: 687b ldr r3, [r7, #4]
|
|
8014b66: 2200 movs r2, #0
|
|
8014b68: f883 209a strb.w r2, [r3, #154] ; 0x9a
|
|
|
|
tcp_parseopt(pcb);
|
|
8014b6c: 6878 ldr r0, [r7, #4]
|
|
8014b6e: f001 fc2d bl 80163cc <tcp_parseopt>
|
|
|
|
/* Do different things depending on the TCP state. */
|
|
switch (pcb->state) {
|
|
8014b72: 687b ldr r3, [r7, #4]
|
|
8014b74: 7d1b ldrb r3, [r3, #20]
|
|
8014b76: 3b02 subs r3, #2
|
|
8014b78: 2b07 cmp r3, #7
|
|
8014b7a: f200 8337 bhi.w 80151ec <tcp_process+0x7a0>
|
|
8014b7e: a201 add r2, pc, #4 ; (adr r2, 8014b84 <tcp_process+0x138>)
|
|
8014b80: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8014b84: 08014ba5 .word 0x08014ba5
|
|
8014b88: 08014dd5 .word 0x08014dd5
|
|
8014b8c: 08014f4d .word 0x08014f4d
|
|
8014b90: 08014f77 .word 0x08014f77
|
|
8014b94: 0801509b .word 0x0801509b
|
|
8014b98: 08014f4d .word 0x08014f4d
|
|
8014b9c: 08015127 .word 0x08015127
|
|
8014ba0: 080151b7 .word 0x080151b7
|
|
case SYN_SENT:
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno,
|
|
pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno)));
|
|
/* received SYN ACK with expected sequence number? */
|
|
if ((flags & TCP_ACK) && (flags & TCP_SYN)
|
|
8014ba4: 4b57 ldr r3, [pc, #348] ; (8014d04 <tcp_process+0x2b8>)
|
|
8014ba6: 781b ldrb r3, [r3, #0]
|
|
8014ba8: f003 0310 and.w r3, r3, #16
|
|
8014bac: 2b00 cmp r3, #0
|
|
8014bae: f000 80e4 beq.w 8014d7a <tcp_process+0x32e>
|
|
8014bb2: 4b54 ldr r3, [pc, #336] ; (8014d04 <tcp_process+0x2b8>)
|
|
8014bb4: 781b ldrb r3, [r3, #0]
|
|
8014bb6: f003 0302 and.w r3, r3, #2
|
|
8014bba: 2b00 cmp r3, #0
|
|
8014bbc: f000 80dd beq.w 8014d7a <tcp_process+0x32e>
|
|
&& (ackno == pcb->lastack + 1)) {
|
|
8014bc0: 687b ldr r3, [r7, #4]
|
|
8014bc2: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8014bc4: 1c5a adds r2, r3, #1
|
|
8014bc6: 4b50 ldr r3, [pc, #320] ; (8014d08 <tcp_process+0x2bc>)
|
|
8014bc8: 681b ldr r3, [r3, #0]
|
|
8014bca: 429a cmp r2, r3
|
|
8014bcc: f040 80d5 bne.w 8014d7a <tcp_process+0x32e>
|
|
pcb->rcv_nxt = seqno + 1;
|
|
8014bd0: 4b4e ldr r3, [pc, #312] ; (8014d0c <tcp_process+0x2c0>)
|
|
8014bd2: 681b ldr r3, [r3, #0]
|
|
8014bd4: 1c5a adds r2, r3, #1
|
|
8014bd6: 687b ldr r3, [r7, #4]
|
|
8014bd8: 625a str r2, [r3, #36] ; 0x24
|
|
pcb->rcv_ann_right_edge = pcb->rcv_nxt;
|
|
8014bda: 687b ldr r3, [r7, #4]
|
|
8014bdc: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8014bde: 687b ldr r3, [r7, #4]
|
|
8014be0: 62da str r2, [r3, #44] ; 0x2c
|
|
pcb->lastack = ackno;
|
|
8014be2: 4b49 ldr r3, [pc, #292] ; (8014d08 <tcp_process+0x2bc>)
|
|
8014be4: 681a ldr r2, [r3, #0]
|
|
8014be6: 687b ldr r3, [r7, #4]
|
|
8014be8: 645a str r2, [r3, #68] ; 0x44
|
|
pcb->snd_wnd = tcphdr->wnd;
|
|
8014bea: 4b4c ldr r3, [pc, #304] ; (8014d1c <tcp_process+0x2d0>)
|
|
8014bec: 681b ldr r3, [r3, #0]
|
|
8014bee: 89db ldrh r3, [r3, #14]
|
|
8014bf0: b29a uxth r2, r3
|
|
8014bf2: 687b ldr r3, [r7, #4]
|
|
8014bf4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
|
|
pcb->snd_wnd_max = pcb->snd_wnd;
|
|
8014bf8: 687b ldr r3, [r7, #4]
|
|
8014bfa: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
|
|
8014bfe: 687b ldr r3, [r7, #4]
|
|
8014c00: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
|
|
pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */
|
|
8014c04: 4b41 ldr r3, [pc, #260] ; (8014d0c <tcp_process+0x2c0>)
|
|
8014c06: 681b ldr r3, [r3, #0]
|
|
8014c08: 1e5a subs r2, r3, #1
|
|
8014c0a: 687b ldr r3, [r7, #4]
|
|
8014c0c: 655a str r2, [r3, #84] ; 0x54
|
|
pcb->state = ESTABLISHED;
|
|
8014c0e: 687b ldr r3, [r7, #4]
|
|
8014c10: 2204 movs r2, #4
|
|
8014c12: 751a strb r2, [r3, #20]
|
|
|
|
#if TCP_CALCULATE_EFF_SEND_MSS
|
|
pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip);
|
|
8014c14: 687b ldr r3, [r7, #4]
|
|
8014c16: 8e5c ldrh r4, [r3, #50] ; 0x32
|
|
8014c18: 687b ldr r3, [r7, #4]
|
|
8014c1a: 3304 adds r3, #4
|
|
8014c1c: 4618 mov r0, r3
|
|
8014c1e: f006 fcd7 bl 801b5d0 <ip4_route>
|
|
8014c22: 4601 mov r1, r0
|
|
8014c24: 687b ldr r3, [r7, #4]
|
|
8014c26: 3304 adds r3, #4
|
|
8014c28: 461a mov r2, r3
|
|
8014c2a: 4620 mov r0, r4
|
|
8014c2c: f7ff f88e bl 8013d4c <tcp_eff_send_mss_netif>
|
|
8014c30: 4603 mov r3, r0
|
|
8014c32: 461a mov r2, r3
|
|
8014c34: 687b ldr r3, [r7, #4]
|
|
8014c36: 865a strh r2, [r3, #50] ; 0x32
|
|
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
|
|
|
|
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
|
|
8014c38: 687b ldr r3, [r7, #4]
|
|
8014c3a: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014c3c: 009a lsls r2, r3, #2
|
|
8014c3e: 687b ldr r3, [r7, #4]
|
|
8014c40: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014c42: 005b lsls r3, r3, #1
|
|
8014c44: f241 111c movw r1, #4380 ; 0x111c
|
|
8014c48: 428b cmp r3, r1
|
|
8014c4a: bf38 it cc
|
|
8014c4c: 460b movcc r3, r1
|
|
8014c4e: 429a cmp r2, r3
|
|
8014c50: d204 bcs.n 8014c5c <tcp_process+0x210>
|
|
8014c52: 687b ldr r3, [r7, #4]
|
|
8014c54: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014c56: 009b lsls r3, r3, #2
|
|
8014c58: b29b uxth r3, r3
|
|
8014c5a: e00d b.n 8014c78 <tcp_process+0x22c>
|
|
8014c5c: 687b ldr r3, [r7, #4]
|
|
8014c5e: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014c60: 005b lsls r3, r3, #1
|
|
8014c62: f241 121c movw r2, #4380 ; 0x111c
|
|
8014c66: 4293 cmp r3, r2
|
|
8014c68: d904 bls.n 8014c74 <tcp_process+0x228>
|
|
8014c6a: 687b ldr r3, [r7, #4]
|
|
8014c6c: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014c6e: 005b lsls r3, r3, #1
|
|
8014c70: b29b uxth r3, r3
|
|
8014c72: e001 b.n 8014c78 <tcp_process+0x22c>
|
|
8014c74: f241 131c movw r3, #4380 ; 0x111c
|
|
8014c78: 687a ldr r2, [r7, #4]
|
|
8014c7a: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
|
|
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F
|
|
" ssthresh %"TCPWNDSIZE_F"\n",
|
|
pcb->cwnd, pcb->ssthresh));
|
|
LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0));
|
|
8014c7e: 687b ldr r3, [r7, #4]
|
|
8014c80: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
8014c84: 2b00 cmp r3, #0
|
|
8014c86: d106 bne.n 8014c96 <tcp_process+0x24a>
|
|
8014c88: 4b1b ldr r3, [pc, #108] ; (8014cf8 <tcp_process+0x2ac>)
|
|
8014c8a: f44f 725b mov.w r2, #876 ; 0x36c
|
|
8014c8e: 4924 ldr r1, [pc, #144] ; (8014d20 <tcp_process+0x2d4>)
|
|
8014c90: 481b ldr r0, [pc, #108] ; (8014d00 <tcp_process+0x2b4>)
|
|
8014c92: f008 f811 bl 801ccb8 <iprintf>
|
|
--pcb->snd_queuelen;
|
|
8014c96: 687b ldr r3, [r7, #4]
|
|
8014c98: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
8014c9c: 3b01 subs r3, #1
|
|
8014c9e: b29a uxth r2, r3
|
|
8014ca0: 687b ldr r3, [r7, #4]
|
|
8014ca2: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen));
|
|
rseg = pcb->unacked;
|
|
8014ca6: 687b ldr r3, [r7, #4]
|
|
8014ca8: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8014caa: 61fb str r3, [r7, #28]
|
|
if (rseg == NULL) {
|
|
8014cac: 69fb ldr r3, [r7, #28]
|
|
8014cae: 2b00 cmp r3, #0
|
|
8014cb0: d111 bne.n 8014cd6 <tcp_process+0x28a>
|
|
/* might happen if tcp_output fails in tcp_rexmit_rto()
|
|
in which case the segment is on the unsent list */
|
|
rseg = pcb->unsent;
|
|
8014cb2: 687b ldr r3, [r7, #4]
|
|
8014cb4: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8014cb6: 61fb str r3, [r7, #28]
|
|
LWIP_ASSERT("no segment to free", rseg != NULL);
|
|
8014cb8: 69fb ldr r3, [r7, #28]
|
|
8014cba: 2b00 cmp r3, #0
|
|
8014cbc: d106 bne.n 8014ccc <tcp_process+0x280>
|
|
8014cbe: 4b0e ldr r3, [pc, #56] ; (8014cf8 <tcp_process+0x2ac>)
|
|
8014cc0: f44f 725d mov.w r2, #884 ; 0x374
|
|
8014cc4: 4917 ldr r1, [pc, #92] ; (8014d24 <tcp_process+0x2d8>)
|
|
8014cc6: 480e ldr r0, [pc, #56] ; (8014d00 <tcp_process+0x2b4>)
|
|
8014cc8: f007 fff6 bl 801ccb8 <iprintf>
|
|
pcb->unsent = rseg->next;
|
|
8014ccc: 69fb ldr r3, [r7, #28]
|
|
8014cce: 681a ldr r2, [r3, #0]
|
|
8014cd0: 687b ldr r3, [r7, #4]
|
|
8014cd2: 66da str r2, [r3, #108] ; 0x6c
|
|
8014cd4: e003 b.n 8014cde <tcp_process+0x292>
|
|
} else {
|
|
pcb->unacked = rseg->next;
|
|
8014cd6: 69fb ldr r3, [r7, #28]
|
|
8014cd8: 681a ldr r2, [r3, #0]
|
|
8014cda: 687b ldr r3, [r7, #4]
|
|
8014cdc: 671a str r2, [r3, #112] ; 0x70
|
|
}
|
|
tcp_seg_free(rseg);
|
|
8014cde: 69f8 ldr r0, [r7, #28]
|
|
8014ce0: f7fe fd3e bl 8013760 <tcp_seg_free>
|
|
|
|
/* If there's nothing left to acknowledge, stop the retransmit
|
|
timer, otherwise reset it to start again */
|
|
if (pcb->unacked == NULL) {
|
|
8014ce4: 687b ldr r3, [r7, #4]
|
|
8014ce6: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8014ce8: 2b00 cmp r3, #0
|
|
8014cea: d11d bne.n 8014d28 <tcp_process+0x2dc>
|
|
pcb->rtime = -1;
|
|
8014cec: 687b ldr r3, [r7, #4]
|
|
8014cee: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8014cf2: 861a strh r2, [r3, #48] ; 0x30
|
|
8014cf4: e01f b.n 8014d36 <tcp_process+0x2ea>
|
|
8014cf6: bf00 nop
|
|
8014cf8: 0801f2b0 .word 0x0801f2b0
|
|
8014cfc: 0801f4e8 .word 0x0801f4e8
|
|
8014d00: 0801f2fc .word 0x0801f2fc
|
|
8014d04: 20008758 .word 0x20008758
|
|
8014d08: 20008750 .word 0x20008750
|
|
8014d0c: 2000874c .word 0x2000874c
|
|
8014d10: 0801f504 .word 0x0801f504
|
|
8014d14: 20008759 .word 0x20008759
|
|
8014d18: 2000f800 .word 0x2000f800
|
|
8014d1c: 2000873c .word 0x2000873c
|
|
8014d20: 0801f524 .word 0x0801f524
|
|
8014d24: 0801f53c .word 0x0801f53c
|
|
} else {
|
|
pcb->rtime = 0;
|
|
8014d28: 687b ldr r3, [r7, #4]
|
|
8014d2a: 2200 movs r2, #0
|
|
8014d2c: 861a strh r2, [r3, #48] ; 0x30
|
|
pcb->nrtx = 0;
|
|
8014d2e: 687b ldr r3, [r7, #4]
|
|
8014d30: 2200 movs r2, #0
|
|
8014d32: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
}
|
|
|
|
/* Call the user specified function to call when successfully
|
|
* connected. */
|
|
TCP_EVENT_CONNECTED(pcb, ERR_OK, err);
|
|
8014d36: 687b ldr r3, [r7, #4]
|
|
8014d38: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8014d3c: 2b00 cmp r3, #0
|
|
8014d3e: d00a beq.n 8014d56 <tcp_process+0x30a>
|
|
8014d40: 687b ldr r3, [r7, #4]
|
|
8014d42: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
|
|
8014d46: 687a ldr r2, [r7, #4]
|
|
8014d48: 6910 ldr r0, [r2, #16]
|
|
8014d4a: 2200 movs r2, #0
|
|
8014d4c: 6879 ldr r1, [r7, #4]
|
|
8014d4e: 4798 blx r3
|
|
8014d50: 4603 mov r3, r0
|
|
8014d52: 76bb strb r3, [r7, #26]
|
|
8014d54: e001 b.n 8014d5a <tcp_process+0x30e>
|
|
8014d56: 2300 movs r3, #0
|
|
8014d58: 76bb strb r3, [r7, #26]
|
|
if (err == ERR_ABRT) {
|
|
8014d5a: f997 301a ldrsb.w r3, [r7, #26]
|
|
8014d5e: f113 0f0d cmn.w r3, #13
|
|
8014d62: d102 bne.n 8014d6a <tcp_process+0x31e>
|
|
return ERR_ABRT;
|
|
8014d64: f06f 030c mvn.w r3, #12
|
|
8014d68: e250 b.n 801520c <tcp_process+0x7c0>
|
|
}
|
|
tcp_ack_now(pcb);
|
|
8014d6a: 687b ldr r3, [r7, #4]
|
|
8014d6c: 8b5b ldrh r3, [r3, #26]
|
|
8014d6e: f043 0302 orr.w r3, r3, #2
|
|
8014d72: b29a uxth r2, r3
|
|
8014d74: 687b ldr r3, [r7, #4]
|
|
8014d76: 835a strh r2, [r3, #26]
|
|
if (pcb->nrtx < TCP_SYNMAXRTX) {
|
|
pcb->rtime = 0;
|
|
tcp_rexmit_rto(pcb);
|
|
}
|
|
}
|
|
break;
|
|
8014d78: e23a b.n 80151f0 <tcp_process+0x7a4>
|
|
else if (flags & TCP_ACK) {
|
|
8014d7a: 4b9d ldr r3, [pc, #628] ; (8014ff0 <tcp_process+0x5a4>)
|
|
8014d7c: 781b ldrb r3, [r3, #0]
|
|
8014d7e: f003 0310 and.w r3, r3, #16
|
|
8014d82: 2b00 cmp r3, #0
|
|
8014d84: f000 8234 beq.w 80151f0 <tcp_process+0x7a4>
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014d88: 4b9a ldr r3, [pc, #616] ; (8014ff4 <tcp_process+0x5a8>)
|
|
8014d8a: 6819 ldr r1, [r3, #0]
|
|
8014d8c: 4b9a ldr r3, [pc, #616] ; (8014ff8 <tcp_process+0x5ac>)
|
|
8014d8e: 881b ldrh r3, [r3, #0]
|
|
8014d90: 461a mov r2, r3
|
|
8014d92: 4b9a ldr r3, [pc, #616] ; (8014ffc <tcp_process+0x5b0>)
|
|
8014d94: 681b ldr r3, [r3, #0]
|
|
8014d96: 18d0 adds r0, r2, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
8014d98: 4b99 ldr r3, [pc, #612] ; (8015000 <tcp_process+0x5b4>)
|
|
8014d9a: 681b ldr r3, [r3, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014d9c: 885b ldrh r3, [r3, #2]
|
|
8014d9e: b29b uxth r3, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
8014da0: 4a97 ldr r2, [pc, #604] ; (8015000 <tcp_process+0x5b4>)
|
|
8014da2: 6812 ldr r2, [r2, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014da4: 8812 ldrh r2, [r2, #0]
|
|
8014da6: b292 uxth r2, r2
|
|
8014da8: 9202 str r2, [sp, #8]
|
|
8014daa: 9301 str r3, [sp, #4]
|
|
8014dac: 4b95 ldr r3, [pc, #596] ; (8015004 <tcp_process+0x5b8>)
|
|
8014dae: 9300 str r3, [sp, #0]
|
|
8014db0: 4b95 ldr r3, [pc, #596] ; (8015008 <tcp_process+0x5bc>)
|
|
8014db2: 4602 mov r2, r0
|
|
8014db4: 6878 ldr r0, [r7, #4]
|
|
8014db6: f002 fc93 bl 80176e0 <tcp_rst>
|
|
if (pcb->nrtx < TCP_SYNMAXRTX) {
|
|
8014dba: 687b ldr r3, [r7, #4]
|
|
8014dbc: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8014dc0: 2b05 cmp r3, #5
|
|
8014dc2: f200 8215 bhi.w 80151f0 <tcp_process+0x7a4>
|
|
pcb->rtime = 0;
|
|
8014dc6: 687b ldr r3, [r7, #4]
|
|
8014dc8: 2200 movs r2, #0
|
|
8014dca: 861a strh r2, [r3, #48] ; 0x30
|
|
tcp_rexmit_rto(pcb);
|
|
8014dcc: 6878 ldr r0, [r7, #4]
|
|
8014dce: f002 fa51 bl 8017274 <tcp_rexmit_rto>
|
|
break;
|
|
8014dd2: e20d b.n 80151f0 <tcp_process+0x7a4>
|
|
case SYN_RCVD:
|
|
if (flags & TCP_ACK) {
|
|
8014dd4: 4b86 ldr r3, [pc, #536] ; (8014ff0 <tcp_process+0x5a4>)
|
|
8014dd6: 781b ldrb r3, [r3, #0]
|
|
8014dd8: f003 0310 and.w r3, r3, #16
|
|
8014ddc: 2b00 cmp r3, #0
|
|
8014dde: f000 80a1 beq.w 8014f24 <tcp_process+0x4d8>
|
|
/* expected ACK number? */
|
|
if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
|
|
8014de2: 4b84 ldr r3, [pc, #528] ; (8014ff4 <tcp_process+0x5a8>)
|
|
8014de4: 681a ldr r2, [r3, #0]
|
|
8014de6: 687b ldr r3, [r7, #4]
|
|
8014de8: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8014dea: 1ad3 subs r3, r2, r3
|
|
8014dec: 3b01 subs r3, #1
|
|
8014dee: 2b00 cmp r3, #0
|
|
8014df0: db7e blt.n 8014ef0 <tcp_process+0x4a4>
|
|
8014df2: 4b80 ldr r3, [pc, #512] ; (8014ff4 <tcp_process+0x5a8>)
|
|
8014df4: 681a ldr r2, [r3, #0]
|
|
8014df6: 687b ldr r3, [r7, #4]
|
|
8014df8: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8014dfa: 1ad3 subs r3, r2, r3
|
|
8014dfc: 2b00 cmp r3, #0
|
|
8014dfe: dc77 bgt.n 8014ef0 <tcp_process+0x4a4>
|
|
pcb->state = ESTABLISHED;
|
|
8014e00: 687b ldr r3, [r7, #4]
|
|
8014e02: 2204 movs r2, #4
|
|
8014e04: 751a strb r2, [r3, #20]
|
|
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
|
|
#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG
|
|
if (pcb->listener == NULL) {
|
|
8014e06: 687b ldr r3, [r7, #4]
|
|
8014e08: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
8014e0a: 2b00 cmp r3, #0
|
|
8014e0c: d102 bne.n 8014e14 <tcp_process+0x3c8>
|
|
/* listen pcb might be closed by now */
|
|
err = ERR_VAL;
|
|
8014e0e: 23fa movs r3, #250 ; 0xfa
|
|
8014e10: 76bb strb r3, [r7, #26]
|
|
8014e12: e01d b.n 8014e50 <tcp_process+0x404>
|
|
} else
|
|
#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */
|
|
{
|
|
#if LWIP_CALLBACK_API
|
|
LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL);
|
|
8014e14: 687b ldr r3, [r7, #4]
|
|
8014e16: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
8014e18: 699b ldr r3, [r3, #24]
|
|
8014e1a: 2b00 cmp r3, #0
|
|
8014e1c: d106 bne.n 8014e2c <tcp_process+0x3e0>
|
|
8014e1e: 4b7b ldr r3, [pc, #492] ; (801500c <tcp_process+0x5c0>)
|
|
8014e20: f44f 726a mov.w r2, #936 ; 0x3a8
|
|
8014e24: 497a ldr r1, [pc, #488] ; (8015010 <tcp_process+0x5c4>)
|
|
8014e26: 487b ldr r0, [pc, #492] ; (8015014 <tcp_process+0x5c8>)
|
|
8014e28: f007 ff46 bl 801ccb8 <iprintf>
|
|
#endif
|
|
tcp_backlog_accepted(pcb);
|
|
/* Call the accept function. */
|
|
TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err);
|
|
8014e2c: 687b ldr r3, [r7, #4]
|
|
8014e2e: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
8014e30: 699b ldr r3, [r3, #24]
|
|
8014e32: 2b00 cmp r3, #0
|
|
8014e34: d00a beq.n 8014e4c <tcp_process+0x400>
|
|
8014e36: 687b ldr r3, [r7, #4]
|
|
8014e38: 6fdb ldr r3, [r3, #124] ; 0x7c
|
|
8014e3a: 699b ldr r3, [r3, #24]
|
|
8014e3c: 687a ldr r2, [r7, #4]
|
|
8014e3e: 6910 ldr r0, [r2, #16]
|
|
8014e40: 2200 movs r2, #0
|
|
8014e42: 6879 ldr r1, [r7, #4]
|
|
8014e44: 4798 blx r3
|
|
8014e46: 4603 mov r3, r0
|
|
8014e48: 76bb strb r3, [r7, #26]
|
|
8014e4a: e001 b.n 8014e50 <tcp_process+0x404>
|
|
8014e4c: 23f0 movs r3, #240 ; 0xf0
|
|
8014e4e: 76bb strb r3, [r7, #26]
|
|
}
|
|
if (err != ERR_OK) {
|
|
8014e50: f997 301a ldrsb.w r3, [r7, #26]
|
|
8014e54: 2b00 cmp r3, #0
|
|
8014e56: d00a beq.n 8014e6e <tcp_process+0x422>
|
|
/* If the accept function returns with an error, we abort
|
|
* the connection. */
|
|
/* Already aborted? */
|
|
if (err != ERR_ABRT) {
|
|
8014e58: f997 301a ldrsb.w r3, [r7, #26]
|
|
8014e5c: f113 0f0d cmn.w r3, #13
|
|
8014e60: d002 beq.n 8014e68 <tcp_process+0x41c>
|
|
tcp_abort(pcb);
|
|
8014e62: 6878 ldr r0, [r7, #4]
|
|
8014e64: f7fd ff94 bl 8012d90 <tcp_abort>
|
|
}
|
|
return ERR_ABRT;
|
|
8014e68: f06f 030c mvn.w r3, #12
|
|
8014e6c: e1ce b.n 801520c <tcp_process+0x7c0>
|
|
}
|
|
/* If there was any data contained within this ACK,
|
|
* we'd better pass it on to the application as well. */
|
|
tcp_receive(pcb);
|
|
8014e6e: 6878 ldr r0, [r7, #4]
|
|
8014e70: f000 fae0 bl 8015434 <tcp_receive>
|
|
|
|
/* Prevent ACK for SYN to generate a sent event */
|
|
if (recv_acked != 0) {
|
|
8014e74: 4b68 ldr r3, [pc, #416] ; (8015018 <tcp_process+0x5cc>)
|
|
8014e76: 881b ldrh r3, [r3, #0]
|
|
8014e78: 2b00 cmp r3, #0
|
|
8014e7a: d005 beq.n 8014e88 <tcp_process+0x43c>
|
|
recv_acked--;
|
|
8014e7c: 4b66 ldr r3, [pc, #408] ; (8015018 <tcp_process+0x5cc>)
|
|
8014e7e: 881b ldrh r3, [r3, #0]
|
|
8014e80: 3b01 subs r3, #1
|
|
8014e82: b29a uxth r2, r3
|
|
8014e84: 4b64 ldr r3, [pc, #400] ; (8015018 <tcp_process+0x5cc>)
|
|
8014e86: 801a strh r2, [r3, #0]
|
|
}
|
|
|
|
pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss);
|
|
8014e88: 687b ldr r3, [r7, #4]
|
|
8014e8a: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014e8c: 009a lsls r2, r3, #2
|
|
8014e8e: 687b ldr r3, [r7, #4]
|
|
8014e90: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014e92: 005b lsls r3, r3, #1
|
|
8014e94: f241 111c movw r1, #4380 ; 0x111c
|
|
8014e98: 428b cmp r3, r1
|
|
8014e9a: bf38 it cc
|
|
8014e9c: 460b movcc r3, r1
|
|
8014e9e: 429a cmp r2, r3
|
|
8014ea0: d204 bcs.n 8014eac <tcp_process+0x460>
|
|
8014ea2: 687b ldr r3, [r7, #4]
|
|
8014ea4: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014ea6: 009b lsls r3, r3, #2
|
|
8014ea8: b29b uxth r3, r3
|
|
8014eaa: e00d b.n 8014ec8 <tcp_process+0x47c>
|
|
8014eac: 687b ldr r3, [r7, #4]
|
|
8014eae: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014eb0: 005b lsls r3, r3, #1
|
|
8014eb2: f241 121c movw r2, #4380 ; 0x111c
|
|
8014eb6: 4293 cmp r3, r2
|
|
8014eb8: d904 bls.n 8014ec4 <tcp_process+0x478>
|
|
8014eba: 687b ldr r3, [r7, #4]
|
|
8014ebc: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8014ebe: 005b lsls r3, r3, #1
|
|
8014ec0: b29b uxth r3, r3
|
|
8014ec2: e001 b.n 8014ec8 <tcp_process+0x47c>
|
|
8014ec4: f241 131c movw r3, #4380 ; 0x111c
|
|
8014ec8: 687a ldr r2, [r7, #4]
|
|
8014eca: f8a2 3048 strh.w r3, [r2, #72] ; 0x48
|
|
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F
|
|
" ssthresh %"TCPWNDSIZE_F"\n",
|
|
pcb->cwnd, pcb->ssthresh));
|
|
|
|
if (recv_flags & TF_GOT_FIN) {
|
|
8014ece: 4b53 ldr r3, [pc, #332] ; (801501c <tcp_process+0x5d0>)
|
|
8014ed0: 781b ldrb r3, [r3, #0]
|
|
8014ed2: f003 0320 and.w r3, r3, #32
|
|
8014ed6: 2b00 cmp r3, #0
|
|
8014ed8: d037 beq.n 8014f4a <tcp_process+0x4fe>
|
|
tcp_ack_now(pcb);
|
|
8014eda: 687b ldr r3, [r7, #4]
|
|
8014edc: 8b5b ldrh r3, [r3, #26]
|
|
8014ede: f043 0302 orr.w r3, r3, #2
|
|
8014ee2: b29a uxth r2, r3
|
|
8014ee4: 687b ldr r3, [r7, #4]
|
|
8014ee6: 835a strh r2, [r3, #26]
|
|
pcb->state = CLOSE_WAIT;
|
|
8014ee8: 687b ldr r3, [r7, #4]
|
|
8014eea: 2207 movs r2, #7
|
|
8014eec: 751a strb r2, [r3, #20]
|
|
if (recv_flags & TF_GOT_FIN) {
|
|
8014eee: e02c b.n 8014f4a <tcp_process+0x4fe>
|
|
}
|
|
} else {
|
|
/* incorrect ACK number, send RST */
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014ef0: 4b40 ldr r3, [pc, #256] ; (8014ff4 <tcp_process+0x5a8>)
|
|
8014ef2: 6819 ldr r1, [r3, #0]
|
|
8014ef4: 4b40 ldr r3, [pc, #256] ; (8014ff8 <tcp_process+0x5ac>)
|
|
8014ef6: 881b ldrh r3, [r3, #0]
|
|
8014ef8: 461a mov r2, r3
|
|
8014efa: 4b40 ldr r3, [pc, #256] ; (8014ffc <tcp_process+0x5b0>)
|
|
8014efc: 681b ldr r3, [r3, #0]
|
|
8014efe: 18d0 adds r0, r2, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
8014f00: 4b3f ldr r3, [pc, #252] ; (8015000 <tcp_process+0x5b4>)
|
|
8014f02: 681b ldr r3, [r3, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014f04: 885b ldrh r3, [r3, #2]
|
|
8014f06: b29b uxth r3, r3
|
|
ip_current_src_addr(), tcphdr->dest, tcphdr->src);
|
|
8014f08: 4a3d ldr r2, [pc, #244] ; (8015000 <tcp_process+0x5b4>)
|
|
8014f0a: 6812 ldr r2, [r2, #0]
|
|
tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(),
|
|
8014f0c: 8812 ldrh r2, [r2, #0]
|
|
8014f0e: b292 uxth r2, r2
|
|
8014f10: 9202 str r2, [sp, #8]
|
|
8014f12: 9301 str r3, [sp, #4]
|
|
8014f14: 4b3b ldr r3, [pc, #236] ; (8015004 <tcp_process+0x5b8>)
|
|
8014f16: 9300 str r3, [sp, #0]
|
|
8014f18: 4b3b ldr r3, [pc, #236] ; (8015008 <tcp_process+0x5bc>)
|
|
8014f1a: 4602 mov r2, r0
|
|
8014f1c: 6878 ldr r0, [r7, #4]
|
|
8014f1e: f002 fbdf bl 80176e0 <tcp_rst>
|
|
}
|
|
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
|
|
/* Looks like another copy of the SYN - retransmit our SYN-ACK */
|
|
tcp_rexmit(pcb);
|
|
}
|
|
break;
|
|
8014f22: e167 b.n 80151f4 <tcp_process+0x7a8>
|
|
} else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) {
|
|
8014f24: 4b32 ldr r3, [pc, #200] ; (8014ff0 <tcp_process+0x5a4>)
|
|
8014f26: 781b ldrb r3, [r3, #0]
|
|
8014f28: f003 0302 and.w r3, r3, #2
|
|
8014f2c: 2b00 cmp r3, #0
|
|
8014f2e: f000 8161 beq.w 80151f4 <tcp_process+0x7a8>
|
|
8014f32: 687b ldr r3, [r7, #4]
|
|
8014f34: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8014f36: 1e5a subs r2, r3, #1
|
|
8014f38: 4b30 ldr r3, [pc, #192] ; (8014ffc <tcp_process+0x5b0>)
|
|
8014f3a: 681b ldr r3, [r3, #0]
|
|
8014f3c: 429a cmp r2, r3
|
|
8014f3e: f040 8159 bne.w 80151f4 <tcp_process+0x7a8>
|
|
tcp_rexmit(pcb);
|
|
8014f42: 6878 ldr r0, [r7, #4]
|
|
8014f44: f002 f9b8 bl 80172b8 <tcp_rexmit>
|
|
break;
|
|
8014f48: e154 b.n 80151f4 <tcp_process+0x7a8>
|
|
8014f4a: e153 b.n 80151f4 <tcp_process+0x7a8>
|
|
case CLOSE_WAIT:
|
|
/* FALLTHROUGH */
|
|
case ESTABLISHED:
|
|
tcp_receive(pcb);
|
|
8014f4c: 6878 ldr r0, [r7, #4]
|
|
8014f4e: f000 fa71 bl 8015434 <tcp_receive>
|
|
if (recv_flags & TF_GOT_FIN) { /* passive close */
|
|
8014f52: 4b32 ldr r3, [pc, #200] ; (801501c <tcp_process+0x5d0>)
|
|
8014f54: 781b ldrb r3, [r3, #0]
|
|
8014f56: f003 0320 and.w r3, r3, #32
|
|
8014f5a: 2b00 cmp r3, #0
|
|
8014f5c: f000 814c beq.w 80151f8 <tcp_process+0x7ac>
|
|
tcp_ack_now(pcb);
|
|
8014f60: 687b ldr r3, [r7, #4]
|
|
8014f62: 8b5b ldrh r3, [r3, #26]
|
|
8014f64: f043 0302 orr.w r3, r3, #2
|
|
8014f68: b29a uxth r2, r3
|
|
8014f6a: 687b ldr r3, [r7, #4]
|
|
8014f6c: 835a strh r2, [r3, #26]
|
|
pcb->state = CLOSE_WAIT;
|
|
8014f6e: 687b ldr r3, [r7, #4]
|
|
8014f70: 2207 movs r2, #7
|
|
8014f72: 751a strb r2, [r3, #20]
|
|
}
|
|
break;
|
|
8014f74: e140 b.n 80151f8 <tcp_process+0x7ac>
|
|
case FIN_WAIT_1:
|
|
tcp_receive(pcb);
|
|
8014f76: 6878 ldr r0, [r7, #4]
|
|
8014f78: f000 fa5c bl 8015434 <tcp_receive>
|
|
if (recv_flags & TF_GOT_FIN) {
|
|
8014f7c: 4b27 ldr r3, [pc, #156] ; (801501c <tcp_process+0x5d0>)
|
|
8014f7e: 781b ldrb r3, [r3, #0]
|
|
8014f80: f003 0320 and.w r3, r3, #32
|
|
8014f84: 2b00 cmp r3, #0
|
|
8014f86: d071 beq.n 801506c <tcp_process+0x620>
|
|
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
|
|
8014f88: 4b19 ldr r3, [pc, #100] ; (8014ff0 <tcp_process+0x5a4>)
|
|
8014f8a: 781b ldrb r3, [r3, #0]
|
|
8014f8c: f003 0310 and.w r3, r3, #16
|
|
8014f90: 2b00 cmp r3, #0
|
|
8014f92: d060 beq.n 8015056 <tcp_process+0x60a>
|
|
8014f94: 687b ldr r3, [r7, #4]
|
|
8014f96: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
8014f98: 4b16 ldr r3, [pc, #88] ; (8014ff4 <tcp_process+0x5a8>)
|
|
8014f9a: 681b ldr r3, [r3, #0]
|
|
8014f9c: 429a cmp r2, r3
|
|
8014f9e: d15a bne.n 8015056 <tcp_process+0x60a>
|
|
pcb->unsent == NULL) {
|
|
8014fa0: 687b ldr r3, [r7, #4]
|
|
8014fa2: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
|
|
8014fa4: 2b00 cmp r3, #0
|
|
8014fa6: d156 bne.n 8015056 <tcp_process+0x60a>
|
|
LWIP_DEBUGF(TCP_DEBUG,
|
|
("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
|
|
tcp_ack_now(pcb);
|
|
8014fa8: 687b ldr r3, [r7, #4]
|
|
8014faa: 8b5b ldrh r3, [r3, #26]
|
|
8014fac: f043 0302 orr.w r3, r3, #2
|
|
8014fb0: b29a uxth r2, r3
|
|
8014fb2: 687b ldr r3, [r7, #4]
|
|
8014fb4: 835a strh r2, [r3, #26]
|
|
tcp_pcb_purge(pcb);
|
|
8014fb6: 6878 ldr r0, [r7, #4]
|
|
8014fb8: f7fe fdbe bl 8013b38 <tcp_pcb_purge>
|
|
TCP_RMV_ACTIVE(pcb);
|
|
8014fbc: 4b18 ldr r3, [pc, #96] ; (8015020 <tcp_process+0x5d4>)
|
|
8014fbe: 681b ldr r3, [r3, #0]
|
|
8014fc0: 687a ldr r2, [r7, #4]
|
|
8014fc2: 429a cmp r2, r3
|
|
8014fc4: d105 bne.n 8014fd2 <tcp_process+0x586>
|
|
8014fc6: 4b16 ldr r3, [pc, #88] ; (8015020 <tcp_process+0x5d4>)
|
|
8014fc8: 681b ldr r3, [r3, #0]
|
|
8014fca: 68db ldr r3, [r3, #12]
|
|
8014fcc: 4a14 ldr r2, [pc, #80] ; (8015020 <tcp_process+0x5d4>)
|
|
8014fce: 6013 str r3, [r2, #0]
|
|
8014fd0: e02e b.n 8015030 <tcp_process+0x5e4>
|
|
8014fd2: 4b13 ldr r3, [pc, #76] ; (8015020 <tcp_process+0x5d4>)
|
|
8014fd4: 681b ldr r3, [r3, #0]
|
|
8014fd6: 617b str r3, [r7, #20]
|
|
8014fd8: e027 b.n 801502a <tcp_process+0x5de>
|
|
8014fda: 697b ldr r3, [r7, #20]
|
|
8014fdc: 68db ldr r3, [r3, #12]
|
|
8014fde: 687a ldr r2, [r7, #4]
|
|
8014fe0: 429a cmp r2, r3
|
|
8014fe2: d11f bne.n 8015024 <tcp_process+0x5d8>
|
|
8014fe4: 687b ldr r3, [r7, #4]
|
|
8014fe6: 68da ldr r2, [r3, #12]
|
|
8014fe8: 697b ldr r3, [r7, #20]
|
|
8014fea: 60da str r2, [r3, #12]
|
|
8014fec: e020 b.n 8015030 <tcp_process+0x5e4>
|
|
8014fee: bf00 nop
|
|
8014ff0: 20008758 .word 0x20008758
|
|
8014ff4: 20008750 .word 0x20008750
|
|
8014ff8: 20008756 .word 0x20008756
|
|
8014ffc: 2000874c .word 0x2000874c
|
|
8015000: 2000873c .word 0x2000873c
|
|
8015004: 2000c0d8 .word 0x2000c0d8
|
|
8015008: 2000c0dc .word 0x2000c0dc
|
|
801500c: 0801f2b0 .word 0x0801f2b0
|
|
8015010: 0801f550 .word 0x0801f550
|
|
8015014: 0801f2fc .word 0x0801f2fc
|
|
8015018: 20008754 .word 0x20008754
|
|
801501c: 20008759 .word 0x20008759
|
|
8015020: 2000f7fc .word 0x2000f7fc
|
|
8015024: 697b ldr r3, [r7, #20]
|
|
8015026: 68db ldr r3, [r3, #12]
|
|
8015028: 617b str r3, [r7, #20]
|
|
801502a: 697b ldr r3, [r7, #20]
|
|
801502c: 2b00 cmp r3, #0
|
|
801502e: d1d4 bne.n 8014fda <tcp_process+0x58e>
|
|
8015030: 687b ldr r3, [r7, #4]
|
|
8015032: 2200 movs r2, #0
|
|
8015034: 60da str r2, [r3, #12]
|
|
8015036: 4b77 ldr r3, [pc, #476] ; (8015214 <tcp_process+0x7c8>)
|
|
8015038: 2201 movs r2, #1
|
|
801503a: 701a strb r2, [r3, #0]
|
|
pcb->state = TIME_WAIT;
|
|
801503c: 687b ldr r3, [r7, #4]
|
|
801503e: 220a movs r2, #10
|
|
8015040: 751a strb r2, [r3, #20]
|
|
TCP_REG(&tcp_tw_pcbs, pcb);
|
|
8015042: 4b75 ldr r3, [pc, #468] ; (8015218 <tcp_process+0x7cc>)
|
|
8015044: 681a ldr r2, [r3, #0]
|
|
8015046: 687b ldr r3, [r7, #4]
|
|
8015048: 60da str r2, [r3, #12]
|
|
801504a: 4a73 ldr r2, [pc, #460] ; (8015218 <tcp_process+0x7cc>)
|
|
801504c: 687b ldr r3, [r7, #4]
|
|
801504e: 6013 str r3, [r2, #0]
|
|
8015050: f002 fd08 bl 8017a64 <tcp_timer_needed>
|
|
}
|
|
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
|
|
pcb->unsent == NULL) {
|
|
pcb->state = FIN_WAIT_2;
|
|
}
|
|
break;
|
|
8015054: e0d2 b.n 80151fc <tcp_process+0x7b0>
|
|
tcp_ack_now(pcb);
|
|
8015056: 687b ldr r3, [r7, #4]
|
|
8015058: 8b5b ldrh r3, [r3, #26]
|
|
801505a: f043 0302 orr.w r3, r3, #2
|
|
801505e: b29a uxth r2, r3
|
|
8015060: 687b ldr r3, [r7, #4]
|
|
8015062: 835a strh r2, [r3, #26]
|
|
pcb->state = CLOSING;
|
|
8015064: 687b ldr r3, [r7, #4]
|
|
8015066: 2208 movs r2, #8
|
|
8015068: 751a strb r2, [r3, #20]
|
|
break;
|
|
801506a: e0c7 b.n 80151fc <tcp_process+0x7b0>
|
|
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
|
|
801506c: 4b6b ldr r3, [pc, #428] ; (801521c <tcp_process+0x7d0>)
|
|
801506e: 781b ldrb r3, [r3, #0]
|
|
8015070: f003 0310 and.w r3, r3, #16
|
|
8015074: 2b00 cmp r3, #0
|
|
8015076: f000 80c1 beq.w 80151fc <tcp_process+0x7b0>
|
|
801507a: 687b ldr r3, [r7, #4]
|
|
801507c: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
801507e: 4b68 ldr r3, [pc, #416] ; (8015220 <tcp_process+0x7d4>)
|
|
8015080: 681b ldr r3, [r3, #0]
|
|
8015082: 429a cmp r2, r3
|
|
8015084: f040 80ba bne.w 80151fc <tcp_process+0x7b0>
|
|
pcb->unsent == NULL) {
|
|
8015088: 687b ldr r3, [r7, #4]
|
|
801508a: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
} else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) &&
|
|
801508c: 2b00 cmp r3, #0
|
|
801508e: f040 80b5 bne.w 80151fc <tcp_process+0x7b0>
|
|
pcb->state = FIN_WAIT_2;
|
|
8015092: 687b ldr r3, [r7, #4]
|
|
8015094: 2206 movs r2, #6
|
|
8015096: 751a strb r2, [r3, #20]
|
|
break;
|
|
8015098: e0b0 b.n 80151fc <tcp_process+0x7b0>
|
|
case FIN_WAIT_2:
|
|
tcp_receive(pcb);
|
|
801509a: 6878 ldr r0, [r7, #4]
|
|
801509c: f000 f9ca bl 8015434 <tcp_receive>
|
|
if (recv_flags & TF_GOT_FIN) {
|
|
80150a0: 4b60 ldr r3, [pc, #384] ; (8015224 <tcp_process+0x7d8>)
|
|
80150a2: 781b ldrb r3, [r3, #0]
|
|
80150a4: f003 0320 and.w r3, r3, #32
|
|
80150a8: 2b00 cmp r3, #0
|
|
80150aa: f000 80a9 beq.w 8015200 <tcp_process+0x7b4>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
|
|
tcp_ack_now(pcb);
|
|
80150ae: 687b ldr r3, [r7, #4]
|
|
80150b0: 8b5b ldrh r3, [r3, #26]
|
|
80150b2: f043 0302 orr.w r3, r3, #2
|
|
80150b6: b29a uxth r2, r3
|
|
80150b8: 687b ldr r3, [r7, #4]
|
|
80150ba: 835a strh r2, [r3, #26]
|
|
tcp_pcb_purge(pcb);
|
|
80150bc: 6878 ldr r0, [r7, #4]
|
|
80150be: f7fe fd3b bl 8013b38 <tcp_pcb_purge>
|
|
TCP_RMV_ACTIVE(pcb);
|
|
80150c2: 4b59 ldr r3, [pc, #356] ; (8015228 <tcp_process+0x7dc>)
|
|
80150c4: 681b ldr r3, [r3, #0]
|
|
80150c6: 687a ldr r2, [r7, #4]
|
|
80150c8: 429a cmp r2, r3
|
|
80150ca: d105 bne.n 80150d8 <tcp_process+0x68c>
|
|
80150cc: 4b56 ldr r3, [pc, #344] ; (8015228 <tcp_process+0x7dc>)
|
|
80150ce: 681b ldr r3, [r3, #0]
|
|
80150d0: 68db ldr r3, [r3, #12]
|
|
80150d2: 4a55 ldr r2, [pc, #340] ; (8015228 <tcp_process+0x7dc>)
|
|
80150d4: 6013 str r3, [r2, #0]
|
|
80150d6: e013 b.n 8015100 <tcp_process+0x6b4>
|
|
80150d8: 4b53 ldr r3, [pc, #332] ; (8015228 <tcp_process+0x7dc>)
|
|
80150da: 681b ldr r3, [r3, #0]
|
|
80150dc: 613b str r3, [r7, #16]
|
|
80150de: e00c b.n 80150fa <tcp_process+0x6ae>
|
|
80150e0: 693b ldr r3, [r7, #16]
|
|
80150e2: 68db ldr r3, [r3, #12]
|
|
80150e4: 687a ldr r2, [r7, #4]
|
|
80150e6: 429a cmp r2, r3
|
|
80150e8: d104 bne.n 80150f4 <tcp_process+0x6a8>
|
|
80150ea: 687b ldr r3, [r7, #4]
|
|
80150ec: 68da ldr r2, [r3, #12]
|
|
80150ee: 693b ldr r3, [r7, #16]
|
|
80150f0: 60da str r2, [r3, #12]
|
|
80150f2: e005 b.n 8015100 <tcp_process+0x6b4>
|
|
80150f4: 693b ldr r3, [r7, #16]
|
|
80150f6: 68db ldr r3, [r3, #12]
|
|
80150f8: 613b str r3, [r7, #16]
|
|
80150fa: 693b ldr r3, [r7, #16]
|
|
80150fc: 2b00 cmp r3, #0
|
|
80150fe: d1ef bne.n 80150e0 <tcp_process+0x694>
|
|
8015100: 687b ldr r3, [r7, #4]
|
|
8015102: 2200 movs r2, #0
|
|
8015104: 60da str r2, [r3, #12]
|
|
8015106: 4b43 ldr r3, [pc, #268] ; (8015214 <tcp_process+0x7c8>)
|
|
8015108: 2201 movs r2, #1
|
|
801510a: 701a strb r2, [r3, #0]
|
|
pcb->state = TIME_WAIT;
|
|
801510c: 687b ldr r3, [r7, #4]
|
|
801510e: 220a movs r2, #10
|
|
8015110: 751a strb r2, [r3, #20]
|
|
TCP_REG(&tcp_tw_pcbs, pcb);
|
|
8015112: 4b41 ldr r3, [pc, #260] ; (8015218 <tcp_process+0x7cc>)
|
|
8015114: 681a ldr r2, [r3, #0]
|
|
8015116: 687b ldr r3, [r7, #4]
|
|
8015118: 60da str r2, [r3, #12]
|
|
801511a: 4a3f ldr r2, [pc, #252] ; (8015218 <tcp_process+0x7cc>)
|
|
801511c: 687b ldr r3, [r7, #4]
|
|
801511e: 6013 str r3, [r2, #0]
|
|
8015120: f002 fca0 bl 8017a64 <tcp_timer_needed>
|
|
}
|
|
break;
|
|
8015124: e06c b.n 8015200 <tcp_process+0x7b4>
|
|
case CLOSING:
|
|
tcp_receive(pcb);
|
|
8015126: 6878 ldr r0, [r7, #4]
|
|
8015128: f000 f984 bl 8015434 <tcp_receive>
|
|
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
|
|
801512c: 4b3b ldr r3, [pc, #236] ; (801521c <tcp_process+0x7d0>)
|
|
801512e: 781b ldrb r3, [r3, #0]
|
|
8015130: f003 0310 and.w r3, r3, #16
|
|
8015134: 2b00 cmp r3, #0
|
|
8015136: d065 beq.n 8015204 <tcp_process+0x7b8>
|
|
8015138: 687b ldr r3, [r7, #4]
|
|
801513a: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
801513c: 4b38 ldr r3, [pc, #224] ; (8015220 <tcp_process+0x7d4>)
|
|
801513e: 681b ldr r3, [r3, #0]
|
|
8015140: 429a cmp r2, r3
|
|
8015142: d15f bne.n 8015204 <tcp_process+0x7b8>
|
|
8015144: 687b ldr r3, [r7, #4]
|
|
8015146: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8015148: 2b00 cmp r3, #0
|
|
801514a: d15b bne.n 8015204 <tcp_process+0x7b8>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
|
|
tcp_pcb_purge(pcb);
|
|
801514c: 6878 ldr r0, [r7, #4]
|
|
801514e: f7fe fcf3 bl 8013b38 <tcp_pcb_purge>
|
|
TCP_RMV_ACTIVE(pcb);
|
|
8015152: 4b35 ldr r3, [pc, #212] ; (8015228 <tcp_process+0x7dc>)
|
|
8015154: 681b ldr r3, [r3, #0]
|
|
8015156: 687a ldr r2, [r7, #4]
|
|
8015158: 429a cmp r2, r3
|
|
801515a: d105 bne.n 8015168 <tcp_process+0x71c>
|
|
801515c: 4b32 ldr r3, [pc, #200] ; (8015228 <tcp_process+0x7dc>)
|
|
801515e: 681b ldr r3, [r3, #0]
|
|
8015160: 68db ldr r3, [r3, #12]
|
|
8015162: 4a31 ldr r2, [pc, #196] ; (8015228 <tcp_process+0x7dc>)
|
|
8015164: 6013 str r3, [r2, #0]
|
|
8015166: e013 b.n 8015190 <tcp_process+0x744>
|
|
8015168: 4b2f ldr r3, [pc, #188] ; (8015228 <tcp_process+0x7dc>)
|
|
801516a: 681b ldr r3, [r3, #0]
|
|
801516c: 60fb str r3, [r7, #12]
|
|
801516e: e00c b.n 801518a <tcp_process+0x73e>
|
|
8015170: 68fb ldr r3, [r7, #12]
|
|
8015172: 68db ldr r3, [r3, #12]
|
|
8015174: 687a ldr r2, [r7, #4]
|
|
8015176: 429a cmp r2, r3
|
|
8015178: d104 bne.n 8015184 <tcp_process+0x738>
|
|
801517a: 687b ldr r3, [r7, #4]
|
|
801517c: 68da ldr r2, [r3, #12]
|
|
801517e: 68fb ldr r3, [r7, #12]
|
|
8015180: 60da str r2, [r3, #12]
|
|
8015182: e005 b.n 8015190 <tcp_process+0x744>
|
|
8015184: 68fb ldr r3, [r7, #12]
|
|
8015186: 68db ldr r3, [r3, #12]
|
|
8015188: 60fb str r3, [r7, #12]
|
|
801518a: 68fb ldr r3, [r7, #12]
|
|
801518c: 2b00 cmp r3, #0
|
|
801518e: d1ef bne.n 8015170 <tcp_process+0x724>
|
|
8015190: 687b ldr r3, [r7, #4]
|
|
8015192: 2200 movs r2, #0
|
|
8015194: 60da str r2, [r3, #12]
|
|
8015196: 4b1f ldr r3, [pc, #124] ; (8015214 <tcp_process+0x7c8>)
|
|
8015198: 2201 movs r2, #1
|
|
801519a: 701a strb r2, [r3, #0]
|
|
pcb->state = TIME_WAIT;
|
|
801519c: 687b ldr r3, [r7, #4]
|
|
801519e: 220a movs r2, #10
|
|
80151a0: 751a strb r2, [r3, #20]
|
|
TCP_REG(&tcp_tw_pcbs, pcb);
|
|
80151a2: 4b1d ldr r3, [pc, #116] ; (8015218 <tcp_process+0x7cc>)
|
|
80151a4: 681a ldr r2, [r3, #0]
|
|
80151a6: 687b ldr r3, [r7, #4]
|
|
80151a8: 60da str r2, [r3, #12]
|
|
80151aa: 4a1b ldr r2, [pc, #108] ; (8015218 <tcp_process+0x7cc>)
|
|
80151ac: 687b ldr r3, [r7, #4]
|
|
80151ae: 6013 str r3, [r2, #0]
|
|
80151b0: f002 fc58 bl 8017a64 <tcp_timer_needed>
|
|
}
|
|
break;
|
|
80151b4: e026 b.n 8015204 <tcp_process+0x7b8>
|
|
case LAST_ACK:
|
|
tcp_receive(pcb);
|
|
80151b6: 6878 ldr r0, [r7, #4]
|
|
80151b8: f000 f93c bl 8015434 <tcp_receive>
|
|
if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) {
|
|
80151bc: 4b17 ldr r3, [pc, #92] ; (801521c <tcp_process+0x7d0>)
|
|
80151be: 781b ldrb r3, [r3, #0]
|
|
80151c0: f003 0310 and.w r3, r3, #16
|
|
80151c4: 2b00 cmp r3, #0
|
|
80151c6: d01f beq.n 8015208 <tcp_process+0x7bc>
|
|
80151c8: 687b ldr r3, [r7, #4]
|
|
80151ca: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
80151cc: 4b14 ldr r3, [pc, #80] ; (8015220 <tcp_process+0x7d4>)
|
|
80151ce: 681b ldr r3, [r3, #0]
|
|
80151d0: 429a cmp r2, r3
|
|
80151d2: d119 bne.n 8015208 <tcp_process+0x7bc>
|
|
80151d4: 687b ldr r3, [r7, #4]
|
|
80151d6: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
80151d8: 2b00 cmp r3, #0
|
|
80151da: d115 bne.n 8015208 <tcp_process+0x7bc>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest));
|
|
/* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */
|
|
recv_flags |= TF_CLOSED;
|
|
80151dc: 4b11 ldr r3, [pc, #68] ; (8015224 <tcp_process+0x7d8>)
|
|
80151de: 781b ldrb r3, [r3, #0]
|
|
80151e0: f043 0310 orr.w r3, r3, #16
|
|
80151e4: b2da uxtb r2, r3
|
|
80151e6: 4b0f ldr r3, [pc, #60] ; (8015224 <tcp_process+0x7d8>)
|
|
80151e8: 701a strb r2, [r3, #0]
|
|
}
|
|
break;
|
|
80151ea: e00d b.n 8015208 <tcp_process+0x7bc>
|
|
default:
|
|
break;
|
|
80151ec: bf00 nop
|
|
80151ee: e00c b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
80151f0: bf00 nop
|
|
80151f2: e00a b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
80151f4: bf00 nop
|
|
80151f6: e008 b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
80151f8: bf00 nop
|
|
80151fa: e006 b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
80151fc: bf00 nop
|
|
80151fe: e004 b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
8015200: bf00 nop
|
|
8015202: e002 b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
8015204: bf00 nop
|
|
8015206: e000 b.n 801520a <tcp_process+0x7be>
|
|
break;
|
|
8015208: bf00 nop
|
|
}
|
|
return ERR_OK;
|
|
801520a: 2300 movs r3, #0
|
|
}
|
|
801520c: 4618 mov r0, r3
|
|
801520e: 3724 adds r7, #36 ; 0x24
|
|
8015210: 46bd mov sp, r7
|
|
8015212: bd90 pop {r4, r7, pc}
|
|
8015214: 2000f7f8 .word 0x2000f7f8
|
|
8015218: 2000f80c .word 0x2000f80c
|
|
801521c: 20008758 .word 0x20008758
|
|
8015220: 20008750 .word 0x20008750
|
|
8015224: 20008759 .word 0x20008759
|
|
8015228: 2000f7fc .word 0x2000f7fc
|
|
|
|
0801522c <tcp_oos_insert_segment>:
|
|
*
|
|
* Called from tcp_receive()
|
|
*/
|
|
static void
|
|
tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next)
|
|
{
|
|
801522c: b590 push {r4, r7, lr}
|
|
801522e: b085 sub sp, #20
|
|
8015230: af00 add r7, sp, #0
|
|
8015232: 6078 str r0, [r7, #4]
|
|
8015234: 6039 str r1, [r7, #0]
|
|
struct tcp_seg *old_seg;
|
|
|
|
LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL);
|
|
8015236: 687b ldr r3, [r7, #4]
|
|
8015238: 2b00 cmp r3, #0
|
|
801523a: d106 bne.n 801524a <tcp_oos_insert_segment+0x1e>
|
|
801523c: 4b3b ldr r3, [pc, #236] ; (801532c <tcp_oos_insert_segment+0x100>)
|
|
801523e: f240 421f movw r2, #1055 ; 0x41f
|
|
8015242: 493b ldr r1, [pc, #236] ; (8015330 <tcp_oos_insert_segment+0x104>)
|
|
8015244: 483b ldr r0, [pc, #236] ; (8015334 <tcp_oos_insert_segment+0x108>)
|
|
8015246: f007 fd37 bl 801ccb8 <iprintf>
|
|
|
|
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
|
|
801524a: 687b ldr r3, [r7, #4]
|
|
801524c: 68db ldr r3, [r3, #12]
|
|
801524e: 899b ldrh r3, [r3, #12]
|
|
8015250: b29b uxth r3, r3
|
|
8015252: 4618 mov r0, r3
|
|
8015254: f7fb fc4c bl 8010af0 <lwip_htons>
|
|
8015258: 4603 mov r3, r0
|
|
801525a: b2db uxtb r3, r3
|
|
801525c: f003 0301 and.w r3, r3, #1
|
|
8015260: 2b00 cmp r3, #0
|
|
8015262: d028 beq.n 80152b6 <tcp_oos_insert_segment+0x8a>
|
|
/* received segment overlaps all following segments */
|
|
tcp_segs_free(next);
|
|
8015264: 6838 ldr r0, [r7, #0]
|
|
8015266: f7fe fa67 bl 8013738 <tcp_segs_free>
|
|
next = NULL;
|
|
801526a: 2300 movs r3, #0
|
|
801526c: 603b str r3, [r7, #0]
|
|
801526e: e056 b.n 801531e <tcp_oos_insert_segment+0xf2>
|
|
oos queue may have segments with FIN flag */
|
|
while (next &&
|
|
TCP_SEQ_GEQ((seqno + cseg->len),
|
|
(next->tcphdr->seqno + next->len))) {
|
|
/* cseg with FIN already processed */
|
|
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
|
|
8015270: 683b ldr r3, [r7, #0]
|
|
8015272: 68db ldr r3, [r3, #12]
|
|
8015274: 899b ldrh r3, [r3, #12]
|
|
8015276: b29b uxth r3, r3
|
|
8015278: 4618 mov r0, r3
|
|
801527a: f7fb fc39 bl 8010af0 <lwip_htons>
|
|
801527e: 4603 mov r3, r0
|
|
8015280: b2db uxtb r3, r3
|
|
8015282: f003 0301 and.w r3, r3, #1
|
|
8015286: 2b00 cmp r3, #0
|
|
8015288: d00d beq.n 80152a6 <tcp_oos_insert_segment+0x7a>
|
|
TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN);
|
|
801528a: 687b ldr r3, [r7, #4]
|
|
801528c: 68db ldr r3, [r3, #12]
|
|
801528e: 899b ldrh r3, [r3, #12]
|
|
8015290: b29c uxth r4, r3
|
|
8015292: 2001 movs r0, #1
|
|
8015294: f7fb fc2c bl 8010af0 <lwip_htons>
|
|
8015298: 4603 mov r3, r0
|
|
801529a: 461a mov r2, r3
|
|
801529c: 687b ldr r3, [r7, #4]
|
|
801529e: 68db ldr r3, [r3, #12]
|
|
80152a0: 4322 orrs r2, r4
|
|
80152a2: b292 uxth r2, r2
|
|
80152a4: 819a strh r2, [r3, #12]
|
|
}
|
|
old_seg = next;
|
|
80152a6: 683b ldr r3, [r7, #0]
|
|
80152a8: 60fb str r3, [r7, #12]
|
|
next = next->next;
|
|
80152aa: 683b ldr r3, [r7, #0]
|
|
80152ac: 681b ldr r3, [r3, #0]
|
|
80152ae: 603b str r3, [r7, #0]
|
|
tcp_seg_free(old_seg);
|
|
80152b0: 68f8 ldr r0, [r7, #12]
|
|
80152b2: f7fe fa55 bl 8013760 <tcp_seg_free>
|
|
while (next &&
|
|
80152b6: 683b ldr r3, [r7, #0]
|
|
80152b8: 2b00 cmp r3, #0
|
|
80152ba: d00e beq.n 80152da <tcp_oos_insert_segment+0xae>
|
|
TCP_SEQ_GEQ((seqno + cseg->len),
|
|
80152bc: 687b ldr r3, [r7, #4]
|
|
80152be: 891b ldrh r3, [r3, #8]
|
|
80152c0: 461a mov r2, r3
|
|
80152c2: 4b1d ldr r3, [pc, #116] ; (8015338 <tcp_oos_insert_segment+0x10c>)
|
|
80152c4: 681b ldr r3, [r3, #0]
|
|
80152c6: 441a add r2, r3
|
|
80152c8: 683b ldr r3, [r7, #0]
|
|
80152ca: 68db ldr r3, [r3, #12]
|
|
80152cc: 685b ldr r3, [r3, #4]
|
|
80152ce: 6839 ldr r1, [r7, #0]
|
|
80152d0: 8909 ldrh r1, [r1, #8]
|
|
80152d2: 440b add r3, r1
|
|
80152d4: 1ad3 subs r3, r2, r3
|
|
while (next &&
|
|
80152d6: 2b00 cmp r3, #0
|
|
80152d8: daca bge.n 8015270 <tcp_oos_insert_segment+0x44>
|
|
}
|
|
if (next &&
|
|
80152da: 683b ldr r3, [r7, #0]
|
|
80152dc: 2b00 cmp r3, #0
|
|
80152de: d01e beq.n 801531e <tcp_oos_insert_segment+0xf2>
|
|
TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) {
|
|
80152e0: 687b ldr r3, [r7, #4]
|
|
80152e2: 891b ldrh r3, [r3, #8]
|
|
80152e4: 461a mov r2, r3
|
|
80152e6: 4b14 ldr r3, [pc, #80] ; (8015338 <tcp_oos_insert_segment+0x10c>)
|
|
80152e8: 681b ldr r3, [r3, #0]
|
|
80152ea: 441a add r2, r3
|
|
80152ec: 683b ldr r3, [r7, #0]
|
|
80152ee: 68db ldr r3, [r3, #12]
|
|
80152f0: 685b ldr r3, [r3, #4]
|
|
80152f2: 1ad3 subs r3, r2, r3
|
|
if (next &&
|
|
80152f4: 2b00 cmp r3, #0
|
|
80152f6: dd12 ble.n 801531e <tcp_oos_insert_segment+0xf2>
|
|
/* We need to trim the incoming segment. */
|
|
cseg->len = (u16_t)(next->tcphdr->seqno - seqno);
|
|
80152f8: 683b ldr r3, [r7, #0]
|
|
80152fa: 68db ldr r3, [r3, #12]
|
|
80152fc: 685b ldr r3, [r3, #4]
|
|
80152fe: b29a uxth r2, r3
|
|
8015300: 4b0d ldr r3, [pc, #52] ; (8015338 <tcp_oos_insert_segment+0x10c>)
|
|
8015302: 681b ldr r3, [r3, #0]
|
|
8015304: b29b uxth r3, r3
|
|
8015306: 1ad3 subs r3, r2, r3
|
|
8015308: b29a uxth r2, r3
|
|
801530a: 687b ldr r3, [r7, #4]
|
|
801530c: 811a strh r2, [r3, #8]
|
|
pbuf_realloc(cseg->p, cseg->len);
|
|
801530e: 687b ldr r3, [r7, #4]
|
|
8015310: 685a ldr r2, [r3, #4]
|
|
8015312: 687b ldr r3, [r7, #4]
|
|
8015314: 891b ldrh r3, [r3, #8]
|
|
8015316: 4619 mov r1, r3
|
|
8015318: 4610 mov r0, r2
|
|
801531a: f7fc fe17 bl 8011f4c <pbuf_realloc>
|
|
}
|
|
}
|
|
cseg->next = next;
|
|
801531e: 687b ldr r3, [r7, #4]
|
|
8015320: 683a ldr r2, [r7, #0]
|
|
8015322: 601a str r2, [r3, #0]
|
|
}
|
|
8015324: bf00 nop
|
|
8015326: 3714 adds r7, #20
|
|
8015328: 46bd mov sp, r7
|
|
801532a: bd90 pop {r4, r7, pc}
|
|
801532c: 0801f2b0 .word 0x0801f2b0
|
|
8015330: 0801f570 .word 0x0801f570
|
|
8015334: 0801f2fc .word 0x0801f2fc
|
|
8015338: 2000874c .word 0x2000874c
|
|
|
|
0801533c <tcp_free_acked_segments>:
|
|
|
|
/** Remove segments from a list if the incoming ACK acknowledges them */
|
|
static struct tcp_seg *
|
|
tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name,
|
|
struct tcp_seg *dbg_other_seg_list)
|
|
{
|
|
801533c: b5b0 push {r4, r5, r7, lr}
|
|
801533e: b086 sub sp, #24
|
|
8015340: af00 add r7, sp, #0
|
|
8015342: 60f8 str r0, [r7, #12]
|
|
8015344: 60b9 str r1, [r7, #8]
|
|
8015346: 607a str r2, [r7, #4]
|
|
8015348: 603b str r3, [r7, #0]
|
|
u16_t clen;
|
|
|
|
LWIP_UNUSED_ARG(dbg_list_name);
|
|
LWIP_UNUSED_ARG(dbg_other_seg_list);
|
|
|
|
while (seg_list != NULL &&
|
|
801534a: e03e b.n 80153ca <tcp_free_acked_segments+0x8e>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n",
|
|
lwip_ntohl(seg_list->tcphdr->seqno),
|
|
lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list),
|
|
dbg_list_name));
|
|
|
|
next = seg_list;
|
|
801534c: 68bb ldr r3, [r7, #8]
|
|
801534e: 617b str r3, [r7, #20]
|
|
seg_list = seg_list->next;
|
|
8015350: 68bb ldr r3, [r7, #8]
|
|
8015352: 681b ldr r3, [r3, #0]
|
|
8015354: 60bb str r3, [r7, #8]
|
|
|
|
clen = pbuf_clen(next->p);
|
|
8015356: 697b ldr r3, [r7, #20]
|
|
8015358: 685b ldr r3, [r3, #4]
|
|
801535a: 4618 mov r0, r3
|
|
801535c: f7fd f80a bl 8012374 <pbuf_clen>
|
|
8015360: 4603 mov r3, r0
|
|
8015362: 827b strh r3, [r7, #18]
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ",
|
|
(tcpwnd_size_t)pcb->snd_queuelen));
|
|
LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen));
|
|
8015364: 68fb ldr r3, [r7, #12]
|
|
8015366: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
801536a: 8a7a ldrh r2, [r7, #18]
|
|
801536c: 429a cmp r2, r3
|
|
801536e: d906 bls.n 801537e <tcp_free_acked_segments+0x42>
|
|
8015370: 4b2a ldr r3, [pc, #168] ; (801541c <tcp_free_acked_segments+0xe0>)
|
|
8015372: f240 4257 movw r2, #1111 ; 0x457
|
|
8015376: 492a ldr r1, [pc, #168] ; (8015420 <tcp_free_acked_segments+0xe4>)
|
|
8015378: 482a ldr r0, [pc, #168] ; (8015424 <tcp_free_acked_segments+0xe8>)
|
|
801537a: f007 fc9d bl 801ccb8 <iprintf>
|
|
|
|
pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen);
|
|
801537e: 68fb ldr r3, [r7, #12]
|
|
8015380: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66
|
|
8015384: 8a7b ldrh r3, [r7, #18]
|
|
8015386: 1ad3 subs r3, r2, r3
|
|
8015388: b29a uxth r2, r3
|
|
801538a: 68fb ldr r3, [r7, #12]
|
|
801538c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
recv_acked = (tcpwnd_size_t)(recv_acked + next->len);
|
|
8015390: 697b ldr r3, [r7, #20]
|
|
8015392: 891a ldrh r2, [r3, #8]
|
|
8015394: 4b24 ldr r3, [pc, #144] ; (8015428 <tcp_free_acked_segments+0xec>)
|
|
8015396: 881b ldrh r3, [r3, #0]
|
|
8015398: 4413 add r3, r2
|
|
801539a: b29a uxth r2, r3
|
|
801539c: 4b22 ldr r3, [pc, #136] ; (8015428 <tcp_free_acked_segments+0xec>)
|
|
801539e: 801a strh r2, [r3, #0]
|
|
tcp_seg_free(next);
|
|
80153a0: 6978 ldr r0, [r7, #20]
|
|
80153a2: f7fe f9dd bl 8013760 <tcp_seg_free>
|
|
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n",
|
|
(tcpwnd_size_t)pcb->snd_queuelen,
|
|
dbg_list_name));
|
|
if (pcb->snd_queuelen != 0) {
|
|
80153a6: 68fb ldr r3, [r7, #12]
|
|
80153a8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
80153ac: 2b00 cmp r3, #0
|
|
80153ae: d00c beq.n 80153ca <tcp_free_acked_segments+0x8e>
|
|
LWIP_ASSERT("tcp_receive: valid queue length",
|
|
80153b0: 68bb ldr r3, [r7, #8]
|
|
80153b2: 2b00 cmp r3, #0
|
|
80153b4: d109 bne.n 80153ca <tcp_free_acked_segments+0x8e>
|
|
80153b6: 683b ldr r3, [r7, #0]
|
|
80153b8: 2b00 cmp r3, #0
|
|
80153ba: d106 bne.n 80153ca <tcp_free_acked_segments+0x8e>
|
|
80153bc: 4b17 ldr r3, [pc, #92] ; (801541c <tcp_free_acked_segments+0xe0>)
|
|
80153be: f240 4262 movw r2, #1122 ; 0x462
|
|
80153c2: 491a ldr r1, [pc, #104] ; (801542c <tcp_free_acked_segments+0xf0>)
|
|
80153c4: 4817 ldr r0, [pc, #92] ; (8015424 <tcp_free_acked_segments+0xe8>)
|
|
80153c6: f007 fc77 bl 801ccb8 <iprintf>
|
|
while (seg_list != NULL &&
|
|
80153ca: 68bb ldr r3, [r7, #8]
|
|
80153cc: 2b00 cmp r3, #0
|
|
80153ce: d020 beq.n 8015412 <tcp_free_acked_segments+0xd6>
|
|
TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) +
|
|
80153d0: 68bb ldr r3, [r7, #8]
|
|
80153d2: 68db ldr r3, [r3, #12]
|
|
80153d4: 685b ldr r3, [r3, #4]
|
|
80153d6: 4618 mov r0, r3
|
|
80153d8: f7fb fb9f bl 8010b1a <lwip_htonl>
|
|
80153dc: 4604 mov r4, r0
|
|
80153de: 68bb ldr r3, [r7, #8]
|
|
80153e0: 891b ldrh r3, [r3, #8]
|
|
80153e2: 461d mov r5, r3
|
|
80153e4: 68bb ldr r3, [r7, #8]
|
|
80153e6: 68db ldr r3, [r3, #12]
|
|
80153e8: 899b ldrh r3, [r3, #12]
|
|
80153ea: b29b uxth r3, r3
|
|
80153ec: 4618 mov r0, r3
|
|
80153ee: f7fb fb7f bl 8010af0 <lwip_htons>
|
|
80153f2: 4603 mov r3, r0
|
|
80153f4: b2db uxtb r3, r3
|
|
80153f6: f003 0303 and.w r3, r3, #3
|
|
80153fa: 2b00 cmp r3, #0
|
|
80153fc: d001 beq.n 8015402 <tcp_free_acked_segments+0xc6>
|
|
80153fe: 2301 movs r3, #1
|
|
8015400: e000 b.n 8015404 <tcp_free_acked_segments+0xc8>
|
|
8015402: 2300 movs r3, #0
|
|
8015404: 442b add r3, r5
|
|
8015406: 18e2 adds r2, r4, r3
|
|
8015408: 4b09 ldr r3, [pc, #36] ; (8015430 <tcp_free_acked_segments+0xf4>)
|
|
801540a: 681b ldr r3, [r3, #0]
|
|
801540c: 1ad3 subs r3, r2, r3
|
|
while (seg_list != NULL &&
|
|
801540e: 2b00 cmp r3, #0
|
|
8015410: dd9c ble.n 801534c <tcp_free_acked_segments+0x10>
|
|
seg_list != NULL || dbg_other_seg_list != NULL);
|
|
}
|
|
}
|
|
return seg_list;
|
|
8015412: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8015414: 4618 mov r0, r3
|
|
8015416: 3718 adds r7, #24
|
|
8015418: 46bd mov sp, r7
|
|
801541a: bdb0 pop {r4, r5, r7, pc}
|
|
801541c: 0801f2b0 .word 0x0801f2b0
|
|
8015420: 0801f598 .word 0x0801f598
|
|
8015424: 0801f2fc .word 0x0801f2fc
|
|
8015428: 20008754 .word 0x20008754
|
|
801542c: 0801f5c0 .word 0x0801f5c0
|
|
8015430: 20008750 .word 0x20008750
|
|
|
|
08015434 <tcp_receive>:
|
|
*
|
|
* Called from tcp_process().
|
|
*/
|
|
static void
|
|
tcp_receive(struct tcp_pcb *pcb)
|
|
{
|
|
8015434: b5b0 push {r4, r5, r7, lr}
|
|
8015436: b094 sub sp, #80 ; 0x50
|
|
8015438: af00 add r7, sp, #0
|
|
801543a: 6078 str r0, [r7, #4]
|
|
s16_t m;
|
|
u32_t right_wnd_edge;
|
|
int found_dupack = 0;
|
|
801543c: 2300 movs r3, #0
|
|
801543e: 64bb str r3, [r7, #72] ; 0x48
|
|
|
|
LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL);
|
|
8015440: 687b ldr r3, [r7, #4]
|
|
8015442: 2b00 cmp r3, #0
|
|
8015444: d106 bne.n 8015454 <tcp_receive+0x20>
|
|
8015446: 4ba6 ldr r3, [pc, #664] ; (80156e0 <tcp_receive+0x2ac>)
|
|
8015448: f240 427b movw r2, #1147 ; 0x47b
|
|
801544c: 49a5 ldr r1, [pc, #660] ; (80156e4 <tcp_receive+0x2b0>)
|
|
801544e: 48a6 ldr r0, [pc, #664] ; (80156e8 <tcp_receive+0x2b4>)
|
|
8015450: f007 fc32 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED);
|
|
8015454: 687b ldr r3, [r7, #4]
|
|
8015456: 7d1b ldrb r3, [r3, #20]
|
|
8015458: 2b03 cmp r3, #3
|
|
801545a: d806 bhi.n 801546a <tcp_receive+0x36>
|
|
801545c: 4ba0 ldr r3, [pc, #640] ; (80156e0 <tcp_receive+0x2ac>)
|
|
801545e: f240 427c movw r2, #1148 ; 0x47c
|
|
8015462: 49a2 ldr r1, [pc, #648] ; (80156ec <tcp_receive+0x2b8>)
|
|
8015464: 48a0 ldr r0, [pc, #640] ; (80156e8 <tcp_receive+0x2b4>)
|
|
8015466: f007 fc27 bl 801ccb8 <iprintf>
|
|
|
|
if (flags & TCP_ACK) {
|
|
801546a: 4ba1 ldr r3, [pc, #644] ; (80156f0 <tcp_receive+0x2bc>)
|
|
801546c: 781b ldrb r3, [r3, #0]
|
|
801546e: f003 0310 and.w r3, r3, #16
|
|
8015472: 2b00 cmp r3, #0
|
|
8015474: f000 8263 beq.w 801593e <tcp_receive+0x50a>
|
|
right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2;
|
|
8015478: 687b ldr r3, [r7, #4]
|
|
801547a: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
801547e: 461a mov r2, r3
|
|
8015480: 687b ldr r3, [r7, #4]
|
|
8015482: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8015484: 4413 add r3, r2
|
|
8015486: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
/* Update window. */
|
|
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
|
|
8015488: 687b ldr r3, [r7, #4]
|
|
801548a: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
801548c: 4b99 ldr r3, [pc, #612] ; (80156f4 <tcp_receive+0x2c0>)
|
|
801548e: 681b ldr r3, [r3, #0]
|
|
8015490: 1ad3 subs r3, r2, r3
|
|
8015492: 2b00 cmp r3, #0
|
|
8015494: db1b blt.n 80154ce <tcp_receive+0x9a>
|
|
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
|
|
8015496: 687b ldr r3, [r7, #4]
|
|
8015498: 6d5a ldr r2, [r3, #84] ; 0x54
|
|
801549a: 4b96 ldr r3, [pc, #600] ; (80156f4 <tcp_receive+0x2c0>)
|
|
801549c: 681b ldr r3, [r3, #0]
|
|
if (TCP_SEQ_LT(pcb->snd_wl1, seqno) ||
|
|
801549e: 429a cmp r2, r3
|
|
80154a0: d106 bne.n 80154b0 <tcp_receive+0x7c>
|
|
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
|
|
80154a2: 687b ldr r3, [r7, #4]
|
|
80154a4: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
80154a6: 4b94 ldr r3, [pc, #592] ; (80156f8 <tcp_receive+0x2c4>)
|
|
80154a8: 681b ldr r3, [r3, #0]
|
|
80154aa: 1ad3 subs r3, r2, r3
|
|
80154ac: 2b00 cmp r3, #0
|
|
80154ae: db0e blt.n 80154ce <tcp_receive+0x9a>
|
|
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
|
|
80154b0: 687b ldr r3, [r7, #4]
|
|
80154b2: 6d9a ldr r2, [r3, #88] ; 0x58
|
|
80154b4: 4b90 ldr r3, [pc, #576] ; (80156f8 <tcp_receive+0x2c4>)
|
|
80154b6: 681b ldr r3, [r3, #0]
|
|
(pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) ||
|
|
80154b8: 429a cmp r2, r3
|
|
80154ba: d125 bne.n 8015508 <tcp_receive+0xd4>
|
|
(pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) {
|
|
80154bc: 4b8f ldr r3, [pc, #572] ; (80156fc <tcp_receive+0x2c8>)
|
|
80154be: 681b ldr r3, [r3, #0]
|
|
80154c0: 89db ldrh r3, [r3, #14]
|
|
80154c2: b29a uxth r2, r3
|
|
80154c4: 687b ldr r3, [r7, #4]
|
|
80154c6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
80154ca: 429a cmp r2, r3
|
|
80154cc: d91c bls.n 8015508 <tcp_receive+0xd4>
|
|
pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd);
|
|
80154ce: 4b8b ldr r3, [pc, #556] ; (80156fc <tcp_receive+0x2c8>)
|
|
80154d0: 681b ldr r3, [r3, #0]
|
|
80154d2: 89db ldrh r3, [r3, #14]
|
|
80154d4: b29a uxth r2, r3
|
|
80154d6: 687b ldr r3, [r7, #4]
|
|
80154d8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60
|
|
/* keep track of the biggest window announced by the remote host to calculate
|
|
the maximum segment size */
|
|
if (pcb->snd_wnd_max < pcb->snd_wnd) {
|
|
80154dc: 687b ldr r3, [r7, #4]
|
|
80154de: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62
|
|
80154e2: 687b ldr r3, [r7, #4]
|
|
80154e4: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
80154e8: 429a cmp r2, r3
|
|
80154ea: d205 bcs.n 80154f8 <tcp_receive+0xc4>
|
|
pcb->snd_wnd_max = pcb->snd_wnd;
|
|
80154ec: 687b ldr r3, [r7, #4]
|
|
80154ee: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
|
|
80154f2: 687b ldr r3, [r7, #4]
|
|
80154f4: f8a3 2062 strh.w r2, [r3, #98] ; 0x62
|
|
}
|
|
pcb->snd_wl1 = seqno;
|
|
80154f8: 4b7e ldr r3, [pc, #504] ; (80156f4 <tcp_receive+0x2c0>)
|
|
80154fa: 681a ldr r2, [r3, #0]
|
|
80154fc: 687b ldr r3, [r7, #4]
|
|
80154fe: 655a str r2, [r3, #84] ; 0x54
|
|
pcb->snd_wl2 = ackno;
|
|
8015500: 4b7d ldr r3, [pc, #500] ; (80156f8 <tcp_receive+0x2c4>)
|
|
8015502: 681a ldr r2, [r3, #0]
|
|
8015504: 687b ldr r3, [r7, #4]
|
|
8015506: 659a str r2, [r3, #88] ; 0x58
|
|
* If it only passes 1, should reset dupack counter
|
|
*
|
|
*/
|
|
|
|
/* Clause 1 */
|
|
if (TCP_SEQ_LEQ(ackno, pcb->lastack)) {
|
|
8015508: 4b7b ldr r3, [pc, #492] ; (80156f8 <tcp_receive+0x2c4>)
|
|
801550a: 681a ldr r2, [r3, #0]
|
|
801550c: 687b ldr r3, [r7, #4]
|
|
801550e: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8015510: 1ad3 subs r3, r2, r3
|
|
8015512: 2b00 cmp r3, #0
|
|
8015514: dc58 bgt.n 80155c8 <tcp_receive+0x194>
|
|
/* Clause 2 */
|
|
if (tcplen == 0) {
|
|
8015516: 4b7a ldr r3, [pc, #488] ; (8015700 <tcp_receive+0x2cc>)
|
|
8015518: 881b ldrh r3, [r3, #0]
|
|
801551a: 2b00 cmp r3, #0
|
|
801551c: d14b bne.n 80155b6 <tcp_receive+0x182>
|
|
/* Clause 3 */
|
|
if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) {
|
|
801551e: 687b ldr r3, [r7, #4]
|
|
8015520: 6d9b ldr r3, [r3, #88] ; 0x58
|
|
8015522: 687a ldr r2, [r7, #4]
|
|
8015524: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60
|
|
8015528: 4413 add r3, r2
|
|
801552a: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
801552c: 429a cmp r2, r3
|
|
801552e: d142 bne.n 80155b6 <tcp_receive+0x182>
|
|
/* Clause 4 */
|
|
if (pcb->rtime >= 0) {
|
|
8015530: 687b ldr r3, [r7, #4]
|
|
8015532: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
|
|
8015536: 2b00 cmp r3, #0
|
|
8015538: db3d blt.n 80155b6 <tcp_receive+0x182>
|
|
/* Clause 5 */
|
|
if (pcb->lastack == ackno) {
|
|
801553a: 687b ldr r3, [r7, #4]
|
|
801553c: 6c5a ldr r2, [r3, #68] ; 0x44
|
|
801553e: 4b6e ldr r3, [pc, #440] ; (80156f8 <tcp_receive+0x2c4>)
|
|
8015540: 681b ldr r3, [r3, #0]
|
|
8015542: 429a cmp r2, r3
|
|
8015544: d137 bne.n 80155b6 <tcp_receive+0x182>
|
|
found_dupack = 1;
|
|
8015546: 2301 movs r3, #1
|
|
8015548: 64bb str r3, [r7, #72] ; 0x48
|
|
if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) {
|
|
801554a: 687b ldr r3, [r7, #4]
|
|
801554c: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
8015550: 2bff cmp r3, #255 ; 0xff
|
|
8015552: d007 beq.n 8015564 <tcp_receive+0x130>
|
|
++pcb->dupacks;
|
|
8015554: 687b ldr r3, [r7, #4]
|
|
8015556: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
801555a: 3301 adds r3, #1
|
|
801555c: b2da uxtb r2, r3
|
|
801555e: 687b ldr r3, [r7, #4]
|
|
8015560: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
}
|
|
if (pcb->dupacks > 3) {
|
|
8015564: 687b ldr r3, [r7, #4]
|
|
8015566: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
801556a: 2b03 cmp r3, #3
|
|
801556c: d91b bls.n 80155a6 <tcp_receive+0x172>
|
|
/* Inflate the congestion window */
|
|
TCP_WND_INC(pcb->cwnd, pcb->mss);
|
|
801556e: 687b ldr r3, [r7, #4]
|
|
8015570: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
8015574: 687b ldr r3, [r7, #4]
|
|
8015576: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8015578: 4413 add r3, r2
|
|
801557a: b29a uxth r2, r3
|
|
801557c: 687b ldr r3, [r7, #4]
|
|
801557e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8015582: 429a cmp r2, r3
|
|
8015584: d30a bcc.n 801559c <tcp_receive+0x168>
|
|
8015586: 687b ldr r3, [r7, #4]
|
|
8015588: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
801558c: 687b ldr r3, [r7, #4]
|
|
801558e: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8015590: 4413 add r3, r2
|
|
8015592: b29a uxth r2, r3
|
|
8015594: 687b ldr r3, [r7, #4]
|
|
8015596: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
801559a: e004 b.n 80155a6 <tcp_receive+0x172>
|
|
801559c: 687b ldr r3, [r7, #4]
|
|
801559e: f64f 72ff movw r2, #65535 ; 0xffff
|
|
80155a2: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
}
|
|
if (pcb->dupacks >= 3) {
|
|
80155a6: 687b ldr r3, [r7, #4]
|
|
80155a8: f893 3043 ldrb.w r3, [r3, #67] ; 0x43
|
|
80155ac: 2b02 cmp r3, #2
|
|
80155ae: d902 bls.n 80155b6 <tcp_receive+0x182>
|
|
/* Do fast retransmit (checked via TF_INFR, not via dupacks count) */
|
|
tcp_rexmit_fast(pcb);
|
|
80155b0: 6878 ldr r0, [r7, #4]
|
|
80155b2: f001 feed bl 8017390 <tcp_rexmit_fast>
|
|
}
|
|
}
|
|
}
|
|
/* If Clause (1) or more is true, but not a duplicate ack, reset
|
|
* count of consecutive duplicate acks */
|
|
if (!found_dupack) {
|
|
80155b6: 6cbb ldr r3, [r7, #72] ; 0x48
|
|
80155b8: 2b00 cmp r3, #0
|
|
80155ba: f040 8160 bne.w 801587e <tcp_receive+0x44a>
|
|
pcb->dupacks = 0;
|
|
80155be: 687b ldr r3, [r7, #4]
|
|
80155c0: 2200 movs r2, #0
|
|
80155c2: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
80155c6: e15a b.n 801587e <tcp_receive+0x44a>
|
|
}
|
|
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
|
|
80155c8: 4b4b ldr r3, [pc, #300] ; (80156f8 <tcp_receive+0x2c4>)
|
|
80155ca: 681a ldr r2, [r3, #0]
|
|
80155cc: 687b ldr r3, [r7, #4]
|
|
80155ce: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
80155d0: 1ad3 subs r3, r2, r3
|
|
80155d2: 3b01 subs r3, #1
|
|
80155d4: 2b00 cmp r3, #0
|
|
80155d6: f2c0 814d blt.w 8015874 <tcp_receive+0x440>
|
|
80155da: 4b47 ldr r3, [pc, #284] ; (80156f8 <tcp_receive+0x2c4>)
|
|
80155dc: 681a ldr r2, [r3, #0]
|
|
80155de: 687b ldr r3, [r7, #4]
|
|
80155e0: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
80155e2: 1ad3 subs r3, r2, r3
|
|
80155e4: 2b00 cmp r3, #0
|
|
80155e6: f300 8145 bgt.w 8015874 <tcp_receive+0x440>
|
|
tcpwnd_size_t acked;
|
|
|
|
/* Reset the "IN Fast Retransmit" flag, since we are no longer
|
|
in fast retransmit. Also reset the congestion window to the
|
|
slow start threshold. */
|
|
if (pcb->flags & TF_INFR) {
|
|
80155ea: 687b ldr r3, [r7, #4]
|
|
80155ec: 8b5b ldrh r3, [r3, #26]
|
|
80155ee: f003 0304 and.w r3, r3, #4
|
|
80155f2: 2b00 cmp r3, #0
|
|
80155f4: d010 beq.n 8015618 <tcp_receive+0x1e4>
|
|
tcp_clear_flags(pcb, TF_INFR);
|
|
80155f6: 687b ldr r3, [r7, #4]
|
|
80155f8: 8b5b ldrh r3, [r3, #26]
|
|
80155fa: f023 0304 bic.w r3, r3, #4
|
|
80155fe: b29a uxth r2, r3
|
|
8015600: 687b ldr r3, [r7, #4]
|
|
8015602: 835a strh r2, [r3, #26]
|
|
pcb->cwnd = pcb->ssthresh;
|
|
8015604: 687b ldr r3, [r7, #4]
|
|
8015606: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
|
|
801560a: 687b ldr r3, [r7, #4]
|
|
801560c: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
pcb->bytes_acked = 0;
|
|
8015610: 687b ldr r3, [r7, #4]
|
|
8015612: 2200 movs r2, #0
|
|
8015614: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
|
|
}
|
|
|
|
/* Reset the number of retransmissions. */
|
|
pcb->nrtx = 0;
|
|
8015618: 687b ldr r3, [r7, #4]
|
|
801561a: 2200 movs r2, #0
|
|
801561c: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
|
|
/* Reset the retransmission time-out. */
|
|
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
|
|
8015620: 687b ldr r3, [r7, #4]
|
|
8015622: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
|
|
8015626: 10db asrs r3, r3, #3
|
|
8015628: b21b sxth r3, r3
|
|
801562a: b29a uxth r2, r3
|
|
801562c: 687b ldr r3, [r7, #4]
|
|
801562e: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
|
|
8015632: b29b uxth r3, r3
|
|
8015634: 4413 add r3, r2
|
|
8015636: b29b uxth r3, r3
|
|
8015638: b21a sxth r2, r3
|
|
801563a: 687b ldr r3, [r7, #4]
|
|
801563c: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
|
|
/* Record how much data this ACK acks */
|
|
acked = (tcpwnd_size_t)(ackno - pcb->lastack);
|
|
8015640: 4b2d ldr r3, [pc, #180] ; (80156f8 <tcp_receive+0x2c4>)
|
|
8015642: 681b ldr r3, [r3, #0]
|
|
8015644: b29a uxth r2, r3
|
|
8015646: 687b ldr r3, [r7, #4]
|
|
8015648: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
801564a: b29b uxth r3, r3
|
|
801564c: 1ad3 subs r3, r2, r3
|
|
801564e: 85fb strh r3, [r7, #46] ; 0x2e
|
|
|
|
/* Reset the fast retransmit variables. */
|
|
pcb->dupacks = 0;
|
|
8015650: 687b ldr r3, [r7, #4]
|
|
8015652: 2200 movs r2, #0
|
|
8015654: f883 2043 strb.w r2, [r3, #67] ; 0x43
|
|
pcb->lastack = ackno;
|
|
8015658: 4b27 ldr r3, [pc, #156] ; (80156f8 <tcp_receive+0x2c4>)
|
|
801565a: 681a ldr r2, [r3, #0]
|
|
801565c: 687b ldr r3, [r7, #4]
|
|
801565e: 645a str r2, [r3, #68] ; 0x44
|
|
|
|
/* Update the congestion control variables (cwnd and
|
|
ssthresh). */
|
|
if (pcb->state >= ESTABLISHED) {
|
|
8015660: 687b ldr r3, [r7, #4]
|
|
8015662: 7d1b ldrb r3, [r3, #20]
|
|
8015664: 2b03 cmp r3, #3
|
|
8015666: f240 8096 bls.w 8015796 <tcp_receive+0x362>
|
|
if (pcb->cwnd < pcb->ssthresh) {
|
|
801566a: 687b ldr r3, [r7, #4]
|
|
801566c: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
8015670: 687b ldr r3, [r7, #4]
|
|
8015672: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
|
|
8015676: 429a cmp r2, r3
|
|
8015678: d244 bcs.n 8015704 <tcp_receive+0x2d0>
|
|
tcpwnd_size_t increase;
|
|
/* limit to 1 SMSS segment during period following RTO */
|
|
u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2;
|
|
801567a: 687b ldr r3, [r7, #4]
|
|
801567c: 8b5b ldrh r3, [r3, #26]
|
|
801567e: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
8015682: 2b00 cmp r3, #0
|
|
8015684: d001 beq.n 801568a <tcp_receive+0x256>
|
|
8015686: 2301 movs r3, #1
|
|
8015688: e000 b.n 801568c <tcp_receive+0x258>
|
|
801568a: 2302 movs r3, #2
|
|
801568c: f887 302d strb.w r3, [r7, #45] ; 0x2d
|
|
/* RFC 3465, section 2.2 Slow Start */
|
|
increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss));
|
|
8015690: f897 302d ldrb.w r3, [r7, #45] ; 0x2d
|
|
8015694: b29a uxth r2, r3
|
|
8015696: 687b ldr r3, [r7, #4]
|
|
8015698: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
801569a: fb12 f303 smulbb r3, r2, r3
|
|
801569e: b29b uxth r3, r3
|
|
80156a0: 8dfa ldrh r2, [r7, #46] ; 0x2e
|
|
80156a2: 4293 cmp r3, r2
|
|
80156a4: bf28 it cs
|
|
80156a6: 4613 movcs r3, r2
|
|
80156a8: 857b strh r3, [r7, #42] ; 0x2a
|
|
TCP_WND_INC(pcb->cwnd, increase);
|
|
80156aa: 687b ldr r3, [r7, #4]
|
|
80156ac: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
80156b0: 8d7b ldrh r3, [r7, #42] ; 0x2a
|
|
80156b2: 4413 add r3, r2
|
|
80156b4: b29a uxth r2, r3
|
|
80156b6: 687b ldr r3, [r7, #4]
|
|
80156b8: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
80156bc: 429a cmp r2, r3
|
|
80156be: d309 bcc.n 80156d4 <tcp_receive+0x2a0>
|
|
80156c0: 687b ldr r3, [r7, #4]
|
|
80156c2: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
80156c6: 8d7b ldrh r3, [r7, #42] ; 0x2a
|
|
80156c8: 4413 add r3, r2
|
|
80156ca: b29a uxth r2, r3
|
|
80156cc: 687b ldr r3, [r7, #4]
|
|
80156ce: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
80156d2: e060 b.n 8015796 <tcp_receive+0x362>
|
|
80156d4: 687b ldr r3, [r7, #4]
|
|
80156d6: f64f 72ff movw r2, #65535 ; 0xffff
|
|
80156da: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
80156de: e05a b.n 8015796 <tcp_receive+0x362>
|
|
80156e0: 0801f2b0 .word 0x0801f2b0
|
|
80156e4: 0801f5e0 .word 0x0801f5e0
|
|
80156e8: 0801f2fc .word 0x0801f2fc
|
|
80156ec: 0801f5fc .word 0x0801f5fc
|
|
80156f0: 20008758 .word 0x20008758
|
|
80156f4: 2000874c .word 0x2000874c
|
|
80156f8: 20008750 .word 0x20008750
|
|
80156fc: 2000873c .word 0x2000873c
|
|
8015700: 20008756 .word 0x20008756
|
|
LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd));
|
|
} else {
|
|
/* RFC 3465, section 2.1 Congestion Avoidance */
|
|
TCP_WND_INC(pcb->bytes_acked, acked);
|
|
8015704: 687b ldr r3, [r7, #4]
|
|
8015706: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
|
|
801570a: 8dfb ldrh r3, [r7, #46] ; 0x2e
|
|
801570c: 4413 add r3, r2
|
|
801570e: b29a uxth r2, r3
|
|
8015710: 687b ldr r3, [r7, #4]
|
|
8015712: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a
|
|
8015716: 429a cmp r2, r3
|
|
8015718: d309 bcc.n 801572e <tcp_receive+0x2fa>
|
|
801571a: 687b ldr r3, [r7, #4]
|
|
801571c: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
|
|
8015720: 8dfb ldrh r3, [r7, #46] ; 0x2e
|
|
8015722: 4413 add r3, r2
|
|
8015724: b29a uxth r2, r3
|
|
8015726: 687b ldr r3, [r7, #4]
|
|
8015728: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
|
|
801572c: e004 b.n 8015738 <tcp_receive+0x304>
|
|
801572e: 687b ldr r3, [r7, #4]
|
|
8015730: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8015734: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
|
|
if (pcb->bytes_acked >= pcb->cwnd) {
|
|
8015738: 687b ldr r3, [r7, #4]
|
|
801573a: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
|
|
801573e: 687b ldr r3, [r7, #4]
|
|
8015740: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8015744: 429a cmp r2, r3
|
|
8015746: d326 bcc.n 8015796 <tcp_receive+0x362>
|
|
pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd);
|
|
8015748: 687b ldr r3, [r7, #4]
|
|
801574a: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a
|
|
801574e: 687b ldr r3, [r7, #4]
|
|
8015750: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8015754: 1ad3 subs r3, r2, r3
|
|
8015756: b29a uxth r2, r3
|
|
8015758: 687b ldr r3, [r7, #4]
|
|
801575a: f8a3 206a strh.w r2, [r3, #106] ; 0x6a
|
|
TCP_WND_INC(pcb->cwnd, pcb->mss);
|
|
801575e: 687b ldr r3, [r7, #4]
|
|
8015760: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
8015764: 687b ldr r3, [r7, #4]
|
|
8015766: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8015768: 4413 add r3, r2
|
|
801576a: b29a uxth r2, r3
|
|
801576c: 687b ldr r3, [r7, #4]
|
|
801576e: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8015772: 429a cmp r2, r3
|
|
8015774: d30a bcc.n 801578c <tcp_receive+0x358>
|
|
8015776: 687b ldr r3, [r7, #4]
|
|
8015778: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
801577c: 687b ldr r3, [r7, #4]
|
|
801577e: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8015780: 4413 add r3, r2
|
|
8015782: b29a uxth r2, r3
|
|
8015784: 687b ldr r3, [r7, #4]
|
|
8015786: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
801578a: e004 b.n 8015796 <tcp_receive+0x362>
|
|
801578c: 687b ldr r3, [r7, #4]
|
|
801578e: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8015792: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
pcb->unacked != NULL ?
|
|
lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0));
|
|
|
|
/* Remove segment from the unacknowledged list if the incoming
|
|
ACK acknowledges them. */
|
|
pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent);
|
|
8015796: 687b ldr r3, [r7, #4]
|
|
8015798: 6f19 ldr r1, [r3, #112] ; 0x70
|
|
801579a: 687b ldr r3, [r7, #4]
|
|
801579c: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
801579e: 4a98 ldr r2, [pc, #608] ; (8015a00 <tcp_receive+0x5cc>)
|
|
80157a0: 6878 ldr r0, [r7, #4]
|
|
80157a2: f7ff fdcb bl 801533c <tcp_free_acked_segments>
|
|
80157a6: 4602 mov r2, r0
|
|
80157a8: 687b ldr r3, [r7, #4]
|
|
80157aa: 671a str r2, [r3, #112] ; 0x70
|
|
on the list are acknowledged by the ACK. This may seem
|
|
strange since an "unsent" segment shouldn't be acked. The
|
|
rationale is that lwIP puts all outstanding segments on the
|
|
->unsent list after a retransmission, so these segments may
|
|
in fact have been sent once. */
|
|
pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked);
|
|
80157ac: 687b ldr r3, [r7, #4]
|
|
80157ae: 6ed9 ldr r1, [r3, #108] ; 0x6c
|
|
80157b0: 687b ldr r3, [r7, #4]
|
|
80157b2: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80157b4: 4a93 ldr r2, [pc, #588] ; (8015a04 <tcp_receive+0x5d0>)
|
|
80157b6: 6878 ldr r0, [r7, #4]
|
|
80157b8: f7ff fdc0 bl 801533c <tcp_free_acked_segments>
|
|
80157bc: 4602 mov r2, r0
|
|
80157be: 687b ldr r3, [r7, #4]
|
|
80157c0: 66da str r2, [r3, #108] ; 0x6c
|
|
|
|
/* If there's nothing left to acknowledge, stop the retransmit
|
|
timer, otherwise reset it to start again */
|
|
if (pcb->unacked == NULL) {
|
|
80157c2: 687b ldr r3, [r7, #4]
|
|
80157c4: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80157c6: 2b00 cmp r3, #0
|
|
80157c8: d104 bne.n 80157d4 <tcp_receive+0x3a0>
|
|
pcb->rtime = -1;
|
|
80157ca: 687b ldr r3, [r7, #4]
|
|
80157cc: f64f 72ff movw r2, #65535 ; 0xffff
|
|
80157d0: 861a strh r2, [r3, #48] ; 0x30
|
|
80157d2: e002 b.n 80157da <tcp_receive+0x3a6>
|
|
} else {
|
|
pcb->rtime = 0;
|
|
80157d4: 687b ldr r3, [r7, #4]
|
|
80157d6: 2200 movs r2, #0
|
|
80157d8: 861a strh r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
pcb->polltmr = 0;
|
|
80157da: 687b ldr r3, [r7, #4]
|
|
80157dc: 2200 movs r2, #0
|
|
80157de: 771a strb r2, [r3, #28]
|
|
|
|
#if TCP_OVERSIZE
|
|
if (pcb->unsent == NULL) {
|
|
80157e0: 687b ldr r3, [r7, #4]
|
|
80157e2: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
80157e4: 2b00 cmp r3, #0
|
|
80157e6: d103 bne.n 80157f0 <tcp_receive+0x3bc>
|
|
pcb->unsent_oversize = 0;
|
|
80157e8: 687b ldr r3, [r7, #4]
|
|
80157ea: 2200 movs r2, #0
|
|
80157ec: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
/* Inform neighbor reachability of forward progress. */
|
|
nd6_reachability_hint(ip6_current_src_addr());
|
|
}
|
|
#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/
|
|
|
|
pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked);
|
|
80157f0: 687b ldr r3, [r7, #4]
|
|
80157f2: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64
|
|
80157f6: 4b84 ldr r3, [pc, #528] ; (8015a08 <tcp_receive+0x5d4>)
|
|
80157f8: 881b ldrh r3, [r3, #0]
|
|
80157fa: 4413 add r3, r2
|
|
80157fc: b29a uxth r2, r3
|
|
80157fe: 687b ldr r3, [r7, #4]
|
|
8015800: f8a3 2064 strh.w r2, [r3, #100] ; 0x64
|
|
/* check if this ACK ends our retransmission of in-flight data */
|
|
if (pcb->flags & TF_RTO) {
|
|
8015804: 687b ldr r3, [r7, #4]
|
|
8015806: 8b5b ldrh r3, [r3, #26]
|
|
8015808: f403 6300 and.w r3, r3, #2048 ; 0x800
|
|
801580c: 2b00 cmp r3, #0
|
|
801580e: d035 beq.n 801587c <tcp_receive+0x448>
|
|
/* RTO is done if
|
|
1) both queues are empty or
|
|
2) unacked is empty and unsent head contains data not part of RTO or
|
|
3) unacked head contains data not part of RTO */
|
|
if (pcb->unacked == NULL) {
|
|
8015810: 687b ldr r3, [r7, #4]
|
|
8015812: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8015814: 2b00 cmp r3, #0
|
|
8015816: d118 bne.n 801584a <tcp_receive+0x416>
|
|
if ((pcb->unsent == NULL) ||
|
|
8015818: 687b ldr r3, [r7, #4]
|
|
801581a: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
801581c: 2b00 cmp r3, #0
|
|
801581e: d00c beq.n 801583a <tcp_receive+0x406>
|
|
(TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) {
|
|
8015820: 687b ldr r3, [r7, #4]
|
|
8015822: 6cdc ldr r4, [r3, #76] ; 0x4c
|
|
8015824: 687b ldr r3, [r7, #4]
|
|
8015826: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8015828: 68db ldr r3, [r3, #12]
|
|
801582a: 685b ldr r3, [r3, #4]
|
|
801582c: 4618 mov r0, r3
|
|
801582e: f7fb f974 bl 8010b1a <lwip_htonl>
|
|
8015832: 4603 mov r3, r0
|
|
8015834: 1ae3 subs r3, r4, r3
|
|
if ((pcb->unsent == NULL) ||
|
|
8015836: 2b00 cmp r3, #0
|
|
8015838: dc20 bgt.n 801587c <tcp_receive+0x448>
|
|
tcp_clear_flags(pcb, TF_RTO);
|
|
801583a: 687b ldr r3, [r7, #4]
|
|
801583c: 8b5b ldrh r3, [r3, #26]
|
|
801583e: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
8015842: b29a uxth r2, r3
|
|
8015844: 687b ldr r3, [r7, #4]
|
|
8015846: 835a strh r2, [r3, #26]
|
|
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
|
|
8015848: e018 b.n 801587c <tcp_receive+0x448>
|
|
}
|
|
} else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) {
|
|
801584a: 687b ldr r3, [r7, #4]
|
|
801584c: 6cdc ldr r4, [r3, #76] ; 0x4c
|
|
801584e: 687b ldr r3, [r7, #4]
|
|
8015850: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8015852: 68db ldr r3, [r3, #12]
|
|
8015854: 685b ldr r3, [r3, #4]
|
|
8015856: 4618 mov r0, r3
|
|
8015858: f7fb f95f bl 8010b1a <lwip_htonl>
|
|
801585c: 4603 mov r3, r0
|
|
801585e: 1ae3 subs r3, r4, r3
|
|
8015860: 2b00 cmp r3, #0
|
|
8015862: dc0b bgt.n 801587c <tcp_receive+0x448>
|
|
tcp_clear_flags(pcb, TF_RTO);
|
|
8015864: 687b ldr r3, [r7, #4]
|
|
8015866: 8b5b ldrh r3, [r3, #26]
|
|
8015868: f423 6300 bic.w r3, r3, #2048 ; 0x800
|
|
801586c: b29a uxth r2, r3
|
|
801586e: 687b ldr r3, [r7, #4]
|
|
8015870: 835a strh r2, [r3, #26]
|
|
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
|
|
8015872: e003 b.n 801587c <tcp_receive+0x448>
|
|
}
|
|
}
|
|
/* End of ACK for new data processing. */
|
|
} else {
|
|
/* Out of sequence ACK, didn't really ack anything */
|
|
tcp_send_empty_ack(pcb);
|
|
8015874: 6878 ldr r0, [r7, #4]
|
|
8015876: f001 ff85 bl 8017784 <tcp_send_empty_ack>
|
|
801587a: e000 b.n 801587e <tcp_receive+0x44a>
|
|
} else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) {
|
|
801587c: bf00 nop
|
|
pcb->rttest, pcb->rtseq, ackno));
|
|
|
|
/* RTT estimation calculations. This is done by checking if the
|
|
incoming segment acknowledges the segment we use to take a
|
|
round-trip time measurement. */
|
|
if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) {
|
|
801587e: 687b ldr r3, [r7, #4]
|
|
8015880: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8015882: 2b00 cmp r3, #0
|
|
8015884: d05b beq.n 801593e <tcp_receive+0x50a>
|
|
8015886: 687b ldr r3, [r7, #4]
|
|
8015888: 6b9a ldr r2, [r3, #56] ; 0x38
|
|
801588a: 4b60 ldr r3, [pc, #384] ; (8015a0c <tcp_receive+0x5d8>)
|
|
801588c: 681b ldr r3, [r3, #0]
|
|
801588e: 1ad3 subs r3, r2, r3
|
|
8015890: 2b00 cmp r3, #0
|
|
8015892: da54 bge.n 801593e <tcp_receive+0x50a>
|
|
/* diff between this shouldn't exceed 32K since this are tcp timer ticks
|
|
and a round-trip shouldn't be that long... */
|
|
m = (s16_t)(tcp_ticks - pcb->rttest);
|
|
8015894: 4b5e ldr r3, [pc, #376] ; (8015a10 <tcp_receive+0x5dc>)
|
|
8015896: 681b ldr r3, [r3, #0]
|
|
8015898: b29a uxth r2, r3
|
|
801589a: 687b ldr r3, [r7, #4]
|
|
801589c: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
801589e: b29b uxth r3, r3
|
|
80158a0: 1ad3 subs r3, r2, r3
|
|
80158a2: b29b uxth r3, r3
|
|
80158a4: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
|
|
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n",
|
|
m, (u16_t)(m * TCP_SLOW_INTERVAL)));
|
|
|
|
/* This is taken directly from VJs original code in his paper */
|
|
m = (s16_t)(m - (pcb->sa >> 3));
|
|
80158a8: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
|
|
80158ac: 687b ldr r3, [r7, #4]
|
|
80158ae: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
|
|
80158b2: 10db asrs r3, r3, #3
|
|
80158b4: b21b sxth r3, r3
|
|
80158b6: b29b uxth r3, r3
|
|
80158b8: 1ad3 subs r3, r2, r3
|
|
80158ba: b29b uxth r3, r3
|
|
80158bc: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
|
|
pcb->sa = (s16_t)(pcb->sa + m);
|
|
80158c0: 687b ldr r3, [r7, #4]
|
|
80158c2: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
|
|
80158c6: b29a uxth r2, r3
|
|
80158c8: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
|
|
80158cc: 4413 add r3, r2
|
|
80158ce: b29b uxth r3, r3
|
|
80158d0: b21a sxth r2, r3
|
|
80158d2: 687b ldr r3, [r7, #4]
|
|
80158d4: 879a strh r2, [r3, #60] ; 0x3c
|
|
if (m < 0) {
|
|
80158d6: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e
|
|
80158da: 2b00 cmp r3, #0
|
|
80158dc: da05 bge.n 80158ea <tcp_receive+0x4b6>
|
|
m = (s16_t) - m;
|
|
80158de: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
|
|
80158e2: 425b negs r3, r3
|
|
80158e4: b29b uxth r3, r3
|
|
80158e6: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
|
|
}
|
|
m = (s16_t)(m - (pcb->sv >> 2));
|
|
80158ea: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e
|
|
80158ee: 687b ldr r3, [r7, #4]
|
|
80158f0: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
|
|
80158f4: 109b asrs r3, r3, #2
|
|
80158f6: b21b sxth r3, r3
|
|
80158f8: b29b uxth r3, r3
|
|
80158fa: 1ad3 subs r3, r2, r3
|
|
80158fc: b29b uxth r3, r3
|
|
80158fe: f8a7 304e strh.w r3, [r7, #78] ; 0x4e
|
|
pcb->sv = (s16_t)(pcb->sv + m);
|
|
8015902: 687b ldr r3, [r7, #4]
|
|
8015904: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
|
|
8015908: b29a uxth r2, r3
|
|
801590a: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e
|
|
801590e: 4413 add r3, r2
|
|
8015910: b29b uxth r3, r3
|
|
8015912: b21a sxth r2, r3
|
|
8015914: 687b ldr r3, [r7, #4]
|
|
8015916: 87da strh r2, [r3, #62] ; 0x3e
|
|
pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv);
|
|
8015918: 687b ldr r3, [r7, #4]
|
|
801591a: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c
|
|
801591e: 10db asrs r3, r3, #3
|
|
8015920: b21b sxth r3, r3
|
|
8015922: b29a uxth r2, r3
|
|
8015924: 687b ldr r3, [r7, #4]
|
|
8015926: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e
|
|
801592a: b29b uxth r3, r3
|
|
801592c: 4413 add r3, r2
|
|
801592e: b29b uxth r3, r3
|
|
8015930: b21a sxth r2, r3
|
|
8015932: 687b ldr r3, [r7, #4]
|
|
8015934: f8a3 2040 strh.w r2, [r3, #64] ; 0x40
|
|
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n",
|
|
pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL)));
|
|
|
|
pcb->rttest = 0;
|
|
8015938: 687b ldr r3, [r7, #4]
|
|
801593a: 2200 movs r2, #0
|
|
801593c: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* If the incoming segment contains data, we must process it
|
|
further unless the pcb already received a FIN.
|
|
(RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING,
|
|
LAST-ACK and TIME-WAIT: "Ignore the segment text.") */
|
|
if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) {
|
|
801593e: 4b35 ldr r3, [pc, #212] ; (8015a14 <tcp_receive+0x5e0>)
|
|
8015940: 881b ldrh r3, [r3, #0]
|
|
8015942: 2b00 cmp r3, #0
|
|
8015944: f000 84e1 beq.w 801630a <tcp_receive+0xed6>
|
|
8015948: 687b ldr r3, [r7, #4]
|
|
801594a: 7d1b ldrb r3, [r3, #20]
|
|
801594c: 2b06 cmp r3, #6
|
|
801594e: f200 84dc bhi.w 801630a <tcp_receive+0xed6>
|
|
this if the sequence number of the incoming segment is less
|
|
than rcv_nxt, and the sequence number plus the length of the
|
|
segment is larger than rcv_nxt. */
|
|
/* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
|
|
if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/
|
|
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
|
|
8015952: 687b ldr r3, [r7, #4]
|
|
8015954: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8015956: 4b30 ldr r3, [pc, #192] ; (8015a18 <tcp_receive+0x5e4>)
|
|
8015958: 681b ldr r3, [r3, #0]
|
|
801595a: 1ad3 subs r3, r2, r3
|
|
801595c: 3b01 subs r3, #1
|
|
801595e: 2b00 cmp r3, #0
|
|
8015960: f2c0 808e blt.w 8015a80 <tcp_receive+0x64c>
|
|
8015964: 687b ldr r3, [r7, #4]
|
|
8015966: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8015968: 4b2a ldr r3, [pc, #168] ; (8015a14 <tcp_receive+0x5e0>)
|
|
801596a: 881b ldrh r3, [r3, #0]
|
|
801596c: 4619 mov r1, r3
|
|
801596e: 4b2a ldr r3, [pc, #168] ; (8015a18 <tcp_receive+0x5e4>)
|
|
8015970: 681b ldr r3, [r3, #0]
|
|
8015972: 440b add r3, r1
|
|
8015974: 1ad3 subs r3, r2, r3
|
|
8015976: 3301 adds r3, #1
|
|
8015978: 2b00 cmp r3, #0
|
|
801597a: f300 8081 bgt.w 8015a80 <tcp_receive+0x64c>
|
|
|
|
After we are done with adjusting the pbuf pointers we must
|
|
adjust the ->data pointer in the seg and the segment
|
|
length.*/
|
|
|
|
struct pbuf *p = inseg.p;
|
|
801597e: 4b27 ldr r3, [pc, #156] ; (8015a1c <tcp_receive+0x5e8>)
|
|
8015980: 685b ldr r3, [r3, #4]
|
|
8015982: 647b str r3, [r7, #68] ; 0x44
|
|
u32_t off32 = pcb->rcv_nxt - seqno;
|
|
8015984: 687b ldr r3, [r7, #4]
|
|
8015986: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8015988: 4b23 ldr r3, [pc, #140] ; (8015a18 <tcp_receive+0x5e4>)
|
|
801598a: 681b ldr r3, [r3, #0]
|
|
801598c: 1ad3 subs r3, r2, r3
|
|
801598e: 627b str r3, [r7, #36] ; 0x24
|
|
u16_t new_tot_len, off;
|
|
LWIP_ASSERT("inseg.p != NULL", inseg.p);
|
|
8015990: 4b22 ldr r3, [pc, #136] ; (8015a1c <tcp_receive+0x5e8>)
|
|
8015992: 685b ldr r3, [r3, #4]
|
|
8015994: 2b00 cmp r3, #0
|
|
8015996: d106 bne.n 80159a6 <tcp_receive+0x572>
|
|
8015998: 4b21 ldr r3, [pc, #132] ; (8015a20 <tcp_receive+0x5ec>)
|
|
801599a: f240 5294 movw r2, #1428 ; 0x594
|
|
801599e: 4921 ldr r1, [pc, #132] ; (8015a24 <tcp_receive+0x5f0>)
|
|
80159a0: 4821 ldr r0, [pc, #132] ; (8015a28 <tcp_receive+0x5f4>)
|
|
80159a2: f007 f989 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("insane offset!", (off32 < 0xffff));
|
|
80159a6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80159a8: f64f 72fe movw r2, #65534 ; 0xfffe
|
|
80159ac: 4293 cmp r3, r2
|
|
80159ae: d906 bls.n 80159be <tcp_receive+0x58a>
|
|
80159b0: 4b1b ldr r3, [pc, #108] ; (8015a20 <tcp_receive+0x5ec>)
|
|
80159b2: f240 5295 movw r2, #1429 ; 0x595
|
|
80159b6: 491d ldr r1, [pc, #116] ; (8015a2c <tcp_receive+0x5f8>)
|
|
80159b8: 481b ldr r0, [pc, #108] ; (8015a28 <tcp_receive+0x5f4>)
|
|
80159ba: f007 f97d bl 801ccb8 <iprintf>
|
|
off = (u16_t)off32;
|
|
80159be: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
80159c0: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
|
LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off));
|
|
80159c4: 4b15 ldr r3, [pc, #84] ; (8015a1c <tcp_receive+0x5e8>)
|
|
80159c6: 685b ldr r3, [r3, #4]
|
|
80159c8: 891b ldrh r3, [r3, #8]
|
|
80159ca: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
80159ce: 429a cmp r2, r3
|
|
80159d0: d906 bls.n 80159e0 <tcp_receive+0x5ac>
|
|
80159d2: 4b13 ldr r3, [pc, #76] ; (8015a20 <tcp_receive+0x5ec>)
|
|
80159d4: f240 5297 movw r2, #1431 ; 0x597
|
|
80159d8: 4915 ldr r1, [pc, #84] ; (8015a30 <tcp_receive+0x5fc>)
|
|
80159da: 4813 ldr r0, [pc, #76] ; (8015a28 <tcp_receive+0x5f4>)
|
|
80159dc: f007 f96c bl 801ccb8 <iprintf>
|
|
inseg.len -= off;
|
|
80159e0: 4b0e ldr r3, [pc, #56] ; (8015a1c <tcp_receive+0x5e8>)
|
|
80159e2: 891a ldrh r2, [r3, #8]
|
|
80159e4: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
|
80159e8: 1ad3 subs r3, r2, r3
|
|
80159ea: b29a uxth r2, r3
|
|
80159ec: 4b0b ldr r3, [pc, #44] ; (8015a1c <tcp_receive+0x5e8>)
|
|
80159ee: 811a strh r2, [r3, #8]
|
|
new_tot_len = (u16_t)(inseg.p->tot_len - off);
|
|
80159f0: 4b0a ldr r3, [pc, #40] ; (8015a1c <tcp_receive+0x5e8>)
|
|
80159f2: 685b ldr r3, [r3, #4]
|
|
80159f4: 891a ldrh r2, [r3, #8]
|
|
80159f6: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
|
80159fa: 1ad3 subs r3, r2, r3
|
|
80159fc: 847b strh r3, [r7, #34] ; 0x22
|
|
while (p->len < off) {
|
|
80159fe: e029 b.n 8015a54 <tcp_receive+0x620>
|
|
8015a00: 0801f618 .word 0x0801f618
|
|
8015a04: 0801f620 .word 0x0801f620
|
|
8015a08: 20008754 .word 0x20008754
|
|
8015a0c: 20008750 .word 0x20008750
|
|
8015a10: 2000f800 .word 0x2000f800
|
|
8015a14: 20008756 .word 0x20008756
|
|
8015a18: 2000874c .word 0x2000874c
|
|
8015a1c: 2000872c .word 0x2000872c
|
|
8015a20: 0801f2b0 .word 0x0801f2b0
|
|
8015a24: 0801f628 .word 0x0801f628
|
|
8015a28: 0801f2fc .word 0x0801f2fc
|
|
8015a2c: 0801f638 .word 0x0801f638
|
|
8015a30: 0801f648 .word 0x0801f648
|
|
off -= p->len;
|
|
8015a34: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8015a36: 895b ldrh r3, [r3, #10]
|
|
8015a38: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
8015a3c: 1ad3 subs r3, r2, r3
|
|
8015a3e: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
|
/* all pbufs up to and including this one have len==0, so tot_len is equal */
|
|
p->tot_len = new_tot_len;
|
|
8015a42: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8015a44: 8c7a ldrh r2, [r7, #34] ; 0x22
|
|
8015a46: 811a strh r2, [r3, #8]
|
|
p->len = 0;
|
|
8015a48: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8015a4a: 2200 movs r2, #0
|
|
8015a4c: 815a strh r2, [r3, #10]
|
|
p = p->next;
|
|
8015a4e: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8015a50: 681b ldr r3, [r3, #0]
|
|
8015a52: 647b str r3, [r7, #68] ; 0x44
|
|
while (p->len < off) {
|
|
8015a54: 6c7b ldr r3, [r7, #68] ; 0x44
|
|
8015a56: 895b ldrh r3, [r3, #10]
|
|
8015a58: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
8015a5c: 429a cmp r2, r3
|
|
8015a5e: d8e9 bhi.n 8015a34 <tcp_receive+0x600>
|
|
}
|
|
/* cannot fail... */
|
|
pbuf_remove_header(p, off);
|
|
8015a60: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
|
8015a64: 4619 mov r1, r3
|
|
8015a66: 6c78 ldr r0, [r7, #68] ; 0x44
|
|
8015a68: f7fc fb70 bl 801214c <pbuf_remove_header>
|
|
inseg.tcphdr->seqno = seqno = pcb->rcv_nxt;
|
|
8015a6c: 687b ldr r3, [r7, #4]
|
|
8015a6e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015a70: 4a91 ldr r2, [pc, #580] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015a72: 6013 str r3, [r2, #0]
|
|
8015a74: 4b91 ldr r3, [pc, #580] ; (8015cbc <tcp_receive+0x888>)
|
|
8015a76: 68db ldr r3, [r3, #12]
|
|
8015a78: 4a8f ldr r2, [pc, #572] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015a7a: 6812 ldr r2, [r2, #0]
|
|
8015a7c: 605a str r2, [r3, #4]
|
|
if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) {
|
|
8015a7e: e00d b.n 8015a9c <tcp_receive+0x668>
|
|
} else {
|
|
if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) {
|
|
8015a80: 4b8d ldr r3, [pc, #564] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015a82: 681a ldr r2, [r3, #0]
|
|
8015a84: 687b ldr r3, [r7, #4]
|
|
8015a86: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015a88: 1ad3 subs r3, r2, r3
|
|
8015a8a: 2b00 cmp r3, #0
|
|
8015a8c: da06 bge.n 8015a9c <tcp_receive+0x668>
|
|
/* the whole segment is < rcv_nxt */
|
|
/* must be a duplicate of a packet that has already been correctly handled */
|
|
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno));
|
|
tcp_ack_now(pcb);
|
|
8015a8e: 687b ldr r3, [r7, #4]
|
|
8015a90: 8b5b ldrh r3, [r3, #26]
|
|
8015a92: f043 0302 orr.w r3, r3, #2
|
|
8015a96: b29a uxth r2, r3
|
|
8015a98: 687b ldr r3, [r7, #4]
|
|
8015a9a: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* The sequence number must be within the window (above rcv_nxt
|
|
and below rcv_nxt + rcv_wnd) in order to be further
|
|
processed. */
|
|
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
|
|
8015a9c: 4b86 ldr r3, [pc, #536] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015a9e: 681a ldr r2, [r3, #0]
|
|
8015aa0: 687b ldr r3, [r7, #4]
|
|
8015aa2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015aa4: 1ad3 subs r3, r2, r3
|
|
8015aa6: 2b00 cmp r3, #0
|
|
8015aa8: f2c0 842a blt.w 8016300 <tcp_receive+0xecc>
|
|
8015aac: 4b82 ldr r3, [pc, #520] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015aae: 681a ldr r2, [r3, #0]
|
|
8015ab0: 687b ldr r3, [r7, #4]
|
|
8015ab2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015ab4: 6879 ldr r1, [r7, #4]
|
|
8015ab6: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
8015ab8: 440b add r3, r1
|
|
8015aba: 1ad3 subs r3, r2, r3
|
|
8015abc: 3301 adds r3, #1
|
|
8015abe: 2b00 cmp r3, #0
|
|
8015ac0: f300 841e bgt.w 8016300 <tcp_receive+0xecc>
|
|
pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
|
|
if (pcb->rcv_nxt == seqno) {
|
|
8015ac4: 687b ldr r3, [r7, #4]
|
|
8015ac6: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8015ac8: 4b7b ldr r3, [pc, #492] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015aca: 681b ldr r3, [r3, #0]
|
|
8015acc: 429a cmp r2, r3
|
|
8015ace: f040 829a bne.w 8016006 <tcp_receive+0xbd2>
|
|
/* The incoming segment is the next in sequence. We check if
|
|
we have to trim the end of the segment and update rcv_nxt
|
|
and pass the data to the application. */
|
|
tcplen = TCP_TCPLEN(&inseg);
|
|
8015ad2: 4b7a ldr r3, [pc, #488] ; (8015cbc <tcp_receive+0x888>)
|
|
8015ad4: 891c ldrh r4, [r3, #8]
|
|
8015ad6: 4b79 ldr r3, [pc, #484] ; (8015cbc <tcp_receive+0x888>)
|
|
8015ad8: 68db ldr r3, [r3, #12]
|
|
8015ada: 899b ldrh r3, [r3, #12]
|
|
8015adc: b29b uxth r3, r3
|
|
8015ade: 4618 mov r0, r3
|
|
8015ae0: f7fb f806 bl 8010af0 <lwip_htons>
|
|
8015ae4: 4603 mov r3, r0
|
|
8015ae6: b2db uxtb r3, r3
|
|
8015ae8: f003 0303 and.w r3, r3, #3
|
|
8015aec: 2b00 cmp r3, #0
|
|
8015aee: d001 beq.n 8015af4 <tcp_receive+0x6c0>
|
|
8015af0: 2301 movs r3, #1
|
|
8015af2: e000 b.n 8015af6 <tcp_receive+0x6c2>
|
|
8015af4: 2300 movs r3, #0
|
|
8015af6: 4423 add r3, r4
|
|
8015af8: b29a uxth r2, r3
|
|
8015afa: 4b71 ldr r3, [pc, #452] ; (8015cc0 <tcp_receive+0x88c>)
|
|
8015afc: 801a strh r2, [r3, #0]
|
|
|
|
if (tcplen > pcb->rcv_wnd) {
|
|
8015afe: 687b ldr r3, [r7, #4]
|
|
8015b00: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8015b02: 4b6f ldr r3, [pc, #444] ; (8015cc0 <tcp_receive+0x88c>)
|
|
8015b04: 881b ldrh r3, [r3, #0]
|
|
8015b06: 429a cmp r2, r3
|
|
8015b08: d275 bcs.n 8015bf6 <tcp_receive+0x7c2>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG,
|
|
("tcp_receive: other end overran receive window"
|
|
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
|
|
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
|
|
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
|
|
8015b0a: 4b6c ldr r3, [pc, #432] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b0c: 68db ldr r3, [r3, #12]
|
|
8015b0e: 899b ldrh r3, [r3, #12]
|
|
8015b10: b29b uxth r3, r3
|
|
8015b12: 4618 mov r0, r3
|
|
8015b14: f7fa ffec bl 8010af0 <lwip_htons>
|
|
8015b18: 4603 mov r3, r0
|
|
8015b1a: b2db uxtb r3, r3
|
|
8015b1c: f003 0301 and.w r3, r3, #1
|
|
8015b20: 2b00 cmp r3, #0
|
|
8015b22: d01f beq.n 8015b64 <tcp_receive+0x730>
|
|
/* Must remove the FIN from the header as we're trimming
|
|
* that byte of sequence-space from the packet */
|
|
TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN);
|
|
8015b24: 4b65 ldr r3, [pc, #404] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b26: 68db ldr r3, [r3, #12]
|
|
8015b28: 899b ldrh r3, [r3, #12]
|
|
8015b2a: b29b uxth r3, r3
|
|
8015b2c: b21b sxth r3, r3
|
|
8015b2e: f423 537c bic.w r3, r3, #16128 ; 0x3f00
|
|
8015b32: b21c sxth r4, r3
|
|
8015b34: 4b61 ldr r3, [pc, #388] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b36: 68db ldr r3, [r3, #12]
|
|
8015b38: 899b ldrh r3, [r3, #12]
|
|
8015b3a: b29b uxth r3, r3
|
|
8015b3c: 4618 mov r0, r3
|
|
8015b3e: f7fa ffd7 bl 8010af0 <lwip_htons>
|
|
8015b42: 4603 mov r3, r0
|
|
8015b44: b2db uxtb r3, r3
|
|
8015b46: b29b uxth r3, r3
|
|
8015b48: f003 033e and.w r3, r3, #62 ; 0x3e
|
|
8015b4c: b29b uxth r3, r3
|
|
8015b4e: 4618 mov r0, r3
|
|
8015b50: f7fa ffce bl 8010af0 <lwip_htons>
|
|
8015b54: 4603 mov r3, r0
|
|
8015b56: b21b sxth r3, r3
|
|
8015b58: 4323 orrs r3, r4
|
|
8015b5a: b21a sxth r2, r3
|
|
8015b5c: 4b57 ldr r3, [pc, #348] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b5e: 68db ldr r3, [r3, #12]
|
|
8015b60: b292 uxth r2, r2
|
|
8015b62: 819a strh r2, [r3, #12]
|
|
}
|
|
/* Adjust length of segment to fit in the window. */
|
|
TCPWND_CHECK16(pcb->rcv_wnd);
|
|
inseg.len = (u16_t)pcb->rcv_wnd;
|
|
8015b64: 687b ldr r3, [r7, #4]
|
|
8015b66: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8015b68: 4b54 ldr r3, [pc, #336] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b6a: 811a strh r2, [r3, #8]
|
|
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
|
|
8015b6c: 4b53 ldr r3, [pc, #332] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b6e: 68db ldr r3, [r3, #12]
|
|
8015b70: 899b ldrh r3, [r3, #12]
|
|
8015b72: b29b uxth r3, r3
|
|
8015b74: 4618 mov r0, r3
|
|
8015b76: f7fa ffbb bl 8010af0 <lwip_htons>
|
|
8015b7a: 4603 mov r3, r0
|
|
8015b7c: b2db uxtb r3, r3
|
|
8015b7e: f003 0302 and.w r3, r3, #2
|
|
8015b82: 2b00 cmp r3, #0
|
|
8015b84: d005 beq.n 8015b92 <tcp_receive+0x75e>
|
|
inseg.len -= 1;
|
|
8015b86: 4b4d ldr r3, [pc, #308] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b88: 891b ldrh r3, [r3, #8]
|
|
8015b8a: 3b01 subs r3, #1
|
|
8015b8c: b29a uxth r2, r3
|
|
8015b8e: 4b4b ldr r3, [pc, #300] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b90: 811a strh r2, [r3, #8]
|
|
}
|
|
pbuf_realloc(inseg.p, inseg.len);
|
|
8015b92: 4b4a ldr r3, [pc, #296] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b94: 685a ldr r2, [r3, #4]
|
|
8015b96: 4b49 ldr r3, [pc, #292] ; (8015cbc <tcp_receive+0x888>)
|
|
8015b98: 891b ldrh r3, [r3, #8]
|
|
8015b9a: 4619 mov r1, r3
|
|
8015b9c: 4610 mov r0, r2
|
|
8015b9e: f7fc f9d5 bl 8011f4c <pbuf_realloc>
|
|
tcplen = TCP_TCPLEN(&inseg);
|
|
8015ba2: 4b46 ldr r3, [pc, #280] ; (8015cbc <tcp_receive+0x888>)
|
|
8015ba4: 891c ldrh r4, [r3, #8]
|
|
8015ba6: 4b45 ldr r3, [pc, #276] ; (8015cbc <tcp_receive+0x888>)
|
|
8015ba8: 68db ldr r3, [r3, #12]
|
|
8015baa: 899b ldrh r3, [r3, #12]
|
|
8015bac: b29b uxth r3, r3
|
|
8015bae: 4618 mov r0, r3
|
|
8015bb0: f7fa ff9e bl 8010af0 <lwip_htons>
|
|
8015bb4: 4603 mov r3, r0
|
|
8015bb6: b2db uxtb r3, r3
|
|
8015bb8: f003 0303 and.w r3, r3, #3
|
|
8015bbc: 2b00 cmp r3, #0
|
|
8015bbe: d001 beq.n 8015bc4 <tcp_receive+0x790>
|
|
8015bc0: 2301 movs r3, #1
|
|
8015bc2: e000 b.n 8015bc6 <tcp_receive+0x792>
|
|
8015bc4: 2300 movs r3, #0
|
|
8015bc6: 4423 add r3, r4
|
|
8015bc8: b29a uxth r2, r3
|
|
8015bca: 4b3d ldr r3, [pc, #244] ; (8015cc0 <tcp_receive+0x88c>)
|
|
8015bcc: 801a strh r2, [r3, #0]
|
|
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
|
|
8015bce: 4b3c ldr r3, [pc, #240] ; (8015cc0 <tcp_receive+0x88c>)
|
|
8015bd0: 881b ldrh r3, [r3, #0]
|
|
8015bd2: 461a mov r2, r3
|
|
8015bd4: 4b38 ldr r3, [pc, #224] ; (8015cb8 <tcp_receive+0x884>)
|
|
8015bd6: 681b ldr r3, [r3, #0]
|
|
8015bd8: 441a add r2, r3
|
|
8015bda: 687b ldr r3, [r7, #4]
|
|
8015bdc: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015bde: 6879 ldr r1, [r7, #4]
|
|
8015be0: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
8015be2: 440b add r3, r1
|
|
8015be4: 429a cmp r2, r3
|
|
8015be6: d006 beq.n 8015bf6 <tcp_receive+0x7c2>
|
|
8015be8: 4b36 ldr r3, [pc, #216] ; (8015cc4 <tcp_receive+0x890>)
|
|
8015bea: f240 52cc movw r2, #1484 ; 0x5cc
|
|
8015bee: 4936 ldr r1, [pc, #216] ; (8015cc8 <tcp_receive+0x894>)
|
|
8015bf0: 4836 ldr r0, [pc, #216] ; (8015ccc <tcp_receive+0x898>)
|
|
8015bf2: f007 f861 bl 801ccb8 <iprintf>
|
|
}
|
|
#if TCP_QUEUE_OOSEQ
|
|
/* Received in-sequence data, adjust ooseq data if:
|
|
- FIN has been received or
|
|
- inseq overlaps with ooseq */
|
|
if (pcb->ooseq != NULL) {
|
|
8015bf6: 687b ldr r3, [r7, #4]
|
|
8015bf8: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015bfa: 2b00 cmp r3, #0
|
|
8015bfc: f000 80e7 beq.w 8015dce <tcp_receive+0x99a>
|
|
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
|
|
8015c00: 4b2e ldr r3, [pc, #184] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c02: 68db ldr r3, [r3, #12]
|
|
8015c04: 899b ldrh r3, [r3, #12]
|
|
8015c06: b29b uxth r3, r3
|
|
8015c08: 4618 mov r0, r3
|
|
8015c0a: f7fa ff71 bl 8010af0 <lwip_htons>
|
|
8015c0e: 4603 mov r3, r0
|
|
8015c10: b2db uxtb r3, r3
|
|
8015c12: f003 0301 and.w r3, r3, #1
|
|
8015c16: 2b00 cmp r3, #0
|
|
8015c18: d010 beq.n 8015c3c <tcp_receive+0x808>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG,
|
|
("tcp_receive: received in-order FIN, binning ooseq queue\n"));
|
|
/* Received in-order FIN means anything that was received
|
|
* out of order must now have been received in-order, so
|
|
* bin the ooseq queue */
|
|
while (pcb->ooseq != NULL) {
|
|
8015c1a: e00a b.n 8015c32 <tcp_receive+0x7fe>
|
|
struct tcp_seg *old_ooseq = pcb->ooseq;
|
|
8015c1c: 687b ldr r3, [r7, #4]
|
|
8015c1e: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015c20: 60fb str r3, [r7, #12]
|
|
pcb->ooseq = pcb->ooseq->next;
|
|
8015c22: 687b ldr r3, [r7, #4]
|
|
8015c24: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015c26: 681a ldr r2, [r3, #0]
|
|
8015c28: 687b ldr r3, [r7, #4]
|
|
8015c2a: 675a str r2, [r3, #116] ; 0x74
|
|
tcp_seg_free(old_ooseq);
|
|
8015c2c: 68f8 ldr r0, [r7, #12]
|
|
8015c2e: f7fd fd97 bl 8013760 <tcp_seg_free>
|
|
while (pcb->ooseq != NULL) {
|
|
8015c32: 687b ldr r3, [r7, #4]
|
|
8015c34: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015c36: 2b00 cmp r3, #0
|
|
8015c38: d1f0 bne.n 8015c1c <tcp_receive+0x7e8>
|
|
8015c3a: e0c8 b.n 8015dce <tcp_receive+0x99a>
|
|
}
|
|
} else {
|
|
struct tcp_seg *next = pcb->ooseq;
|
|
8015c3c: 687b ldr r3, [r7, #4]
|
|
8015c3e: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015c40: 63fb str r3, [r7, #60] ; 0x3c
|
|
/* Remove all segments on ooseq that are covered by inseg already.
|
|
* FIN is copied from ooseq to inseg if present. */
|
|
while (next &&
|
|
8015c42: e052 b.n 8015cea <tcp_receive+0x8b6>
|
|
TCP_SEQ_GEQ(seqno + tcplen,
|
|
next->tcphdr->seqno + next->len)) {
|
|
struct tcp_seg *tmp;
|
|
/* inseg cannot have FIN here (already processed above) */
|
|
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
|
|
8015c44: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015c46: 68db ldr r3, [r3, #12]
|
|
8015c48: 899b ldrh r3, [r3, #12]
|
|
8015c4a: b29b uxth r3, r3
|
|
8015c4c: 4618 mov r0, r3
|
|
8015c4e: f7fa ff4f bl 8010af0 <lwip_htons>
|
|
8015c52: 4603 mov r3, r0
|
|
8015c54: b2db uxtb r3, r3
|
|
8015c56: f003 0301 and.w r3, r3, #1
|
|
8015c5a: 2b00 cmp r3, #0
|
|
8015c5c: d03d beq.n 8015cda <tcp_receive+0x8a6>
|
|
(TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) {
|
|
8015c5e: 4b17 ldr r3, [pc, #92] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c60: 68db ldr r3, [r3, #12]
|
|
8015c62: 899b ldrh r3, [r3, #12]
|
|
8015c64: b29b uxth r3, r3
|
|
8015c66: 4618 mov r0, r3
|
|
8015c68: f7fa ff42 bl 8010af0 <lwip_htons>
|
|
8015c6c: 4603 mov r3, r0
|
|
8015c6e: b2db uxtb r3, r3
|
|
8015c70: f003 0302 and.w r3, r3, #2
|
|
if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 &&
|
|
8015c74: 2b00 cmp r3, #0
|
|
8015c76: d130 bne.n 8015cda <tcp_receive+0x8a6>
|
|
TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN);
|
|
8015c78: 4b10 ldr r3, [pc, #64] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c7a: 68db ldr r3, [r3, #12]
|
|
8015c7c: 899b ldrh r3, [r3, #12]
|
|
8015c7e: b29c uxth r4, r3
|
|
8015c80: 2001 movs r0, #1
|
|
8015c82: f7fa ff35 bl 8010af0 <lwip_htons>
|
|
8015c86: 4603 mov r3, r0
|
|
8015c88: 461a mov r2, r3
|
|
8015c8a: 4b0c ldr r3, [pc, #48] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c8c: 68db ldr r3, [r3, #12]
|
|
8015c8e: 4322 orrs r2, r4
|
|
8015c90: b292 uxth r2, r2
|
|
8015c92: 819a strh r2, [r3, #12]
|
|
tcplen = TCP_TCPLEN(&inseg);
|
|
8015c94: 4b09 ldr r3, [pc, #36] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c96: 891c ldrh r4, [r3, #8]
|
|
8015c98: 4b08 ldr r3, [pc, #32] ; (8015cbc <tcp_receive+0x888>)
|
|
8015c9a: 68db ldr r3, [r3, #12]
|
|
8015c9c: 899b ldrh r3, [r3, #12]
|
|
8015c9e: b29b uxth r3, r3
|
|
8015ca0: 4618 mov r0, r3
|
|
8015ca2: f7fa ff25 bl 8010af0 <lwip_htons>
|
|
8015ca6: 4603 mov r3, r0
|
|
8015ca8: b2db uxtb r3, r3
|
|
8015caa: f003 0303 and.w r3, r3, #3
|
|
8015cae: 2b00 cmp r3, #0
|
|
8015cb0: d00e beq.n 8015cd0 <tcp_receive+0x89c>
|
|
8015cb2: 2301 movs r3, #1
|
|
8015cb4: e00d b.n 8015cd2 <tcp_receive+0x89e>
|
|
8015cb6: bf00 nop
|
|
8015cb8: 2000874c .word 0x2000874c
|
|
8015cbc: 2000872c .word 0x2000872c
|
|
8015cc0: 20008756 .word 0x20008756
|
|
8015cc4: 0801f2b0 .word 0x0801f2b0
|
|
8015cc8: 0801f658 .word 0x0801f658
|
|
8015ccc: 0801f2fc .word 0x0801f2fc
|
|
8015cd0: 2300 movs r3, #0
|
|
8015cd2: 4423 add r3, r4
|
|
8015cd4: b29a uxth r2, r3
|
|
8015cd6: 4b98 ldr r3, [pc, #608] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015cd8: 801a strh r2, [r3, #0]
|
|
}
|
|
tmp = next;
|
|
8015cda: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015cdc: 613b str r3, [r7, #16]
|
|
next = next->next;
|
|
8015cde: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015ce0: 681b ldr r3, [r3, #0]
|
|
8015ce2: 63fb str r3, [r7, #60] ; 0x3c
|
|
tcp_seg_free(tmp);
|
|
8015ce4: 6938 ldr r0, [r7, #16]
|
|
8015ce6: f7fd fd3b bl 8013760 <tcp_seg_free>
|
|
while (next &&
|
|
8015cea: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015cec: 2b00 cmp r3, #0
|
|
8015cee: d00e beq.n 8015d0e <tcp_receive+0x8da>
|
|
TCP_SEQ_GEQ(seqno + tcplen,
|
|
8015cf0: 4b91 ldr r3, [pc, #580] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015cf2: 881b ldrh r3, [r3, #0]
|
|
8015cf4: 461a mov r2, r3
|
|
8015cf6: 4b91 ldr r3, [pc, #580] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015cf8: 681b ldr r3, [r3, #0]
|
|
8015cfa: 441a add r2, r3
|
|
8015cfc: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015cfe: 68db ldr r3, [r3, #12]
|
|
8015d00: 685b ldr r3, [r3, #4]
|
|
8015d02: 6bf9 ldr r1, [r7, #60] ; 0x3c
|
|
8015d04: 8909 ldrh r1, [r1, #8]
|
|
8015d06: 440b add r3, r1
|
|
8015d08: 1ad3 subs r3, r2, r3
|
|
while (next &&
|
|
8015d0a: 2b00 cmp r3, #0
|
|
8015d0c: da9a bge.n 8015c44 <tcp_receive+0x810>
|
|
}
|
|
/* Now trim right side of inseg if it overlaps with the first
|
|
* segment on ooseq */
|
|
if (next &&
|
|
8015d0e: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015d10: 2b00 cmp r3, #0
|
|
8015d12: d059 beq.n 8015dc8 <tcp_receive+0x994>
|
|
TCP_SEQ_GT(seqno + tcplen,
|
|
8015d14: 4b88 ldr r3, [pc, #544] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015d16: 881b ldrh r3, [r3, #0]
|
|
8015d18: 461a mov r2, r3
|
|
8015d1a: 4b88 ldr r3, [pc, #544] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015d1c: 681b ldr r3, [r3, #0]
|
|
8015d1e: 441a add r2, r3
|
|
8015d20: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015d22: 68db ldr r3, [r3, #12]
|
|
8015d24: 685b ldr r3, [r3, #4]
|
|
8015d26: 1ad3 subs r3, r2, r3
|
|
if (next &&
|
|
8015d28: 2b00 cmp r3, #0
|
|
8015d2a: dd4d ble.n 8015dc8 <tcp_receive+0x994>
|
|
next->tcphdr->seqno)) {
|
|
/* inseg cannot have FIN here (already processed above) */
|
|
inseg.len = (u16_t)(next->tcphdr->seqno - seqno);
|
|
8015d2c: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015d2e: 68db ldr r3, [r3, #12]
|
|
8015d30: 685b ldr r3, [r3, #4]
|
|
8015d32: b29a uxth r2, r3
|
|
8015d34: 4b81 ldr r3, [pc, #516] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015d36: 681b ldr r3, [r3, #0]
|
|
8015d38: b29b uxth r3, r3
|
|
8015d3a: 1ad3 subs r3, r2, r3
|
|
8015d3c: b29a uxth r2, r3
|
|
8015d3e: 4b80 ldr r3, [pc, #512] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d40: 811a strh r2, [r3, #8]
|
|
if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) {
|
|
8015d42: 4b7f ldr r3, [pc, #508] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d44: 68db ldr r3, [r3, #12]
|
|
8015d46: 899b ldrh r3, [r3, #12]
|
|
8015d48: b29b uxth r3, r3
|
|
8015d4a: 4618 mov r0, r3
|
|
8015d4c: f7fa fed0 bl 8010af0 <lwip_htons>
|
|
8015d50: 4603 mov r3, r0
|
|
8015d52: b2db uxtb r3, r3
|
|
8015d54: f003 0302 and.w r3, r3, #2
|
|
8015d58: 2b00 cmp r3, #0
|
|
8015d5a: d005 beq.n 8015d68 <tcp_receive+0x934>
|
|
inseg.len -= 1;
|
|
8015d5c: 4b78 ldr r3, [pc, #480] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d5e: 891b ldrh r3, [r3, #8]
|
|
8015d60: 3b01 subs r3, #1
|
|
8015d62: b29a uxth r2, r3
|
|
8015d64: 4b76 ldr r3, [pc, #472] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d66: 811a strh r2, [r3, #8]
|
|
}
|
|
pbuf_realloc(inseg.p, inseg.len);
|
|
8015d68: 4b75 ldr r3, [pc, #468] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d6a: 685a ldr r2, [r3, #4]
|
|
8015d6c: 4b74 ldr r3, [pc, #464] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d6e: 891b ldrh r3, [r3, #8]
|
|
8015d70: 4619 mov r1, r3
|
|
8015d72: 4610 mov r0, r2
|
|
8015d74: f7fc f8ea bl 8011f4c <pbuf_realloc>
|
|
tcplen = TCP_TCPLEN(&inseg);
|
|
8015d78: 4b71 ldr r3, [pc, #452] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d7a: 891c ldrh r4, [r3, #8]
|
|
8015d7c: 4b70 ldr r3, [pc, #448] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015d7e: 68db ldr r3, [r3, #12]
|
|
8015d80: 899b ldrh r3, [r3, #12]
|
|
8015d82: b29b uxth r3, r3
|
|
8015d84: 4618 mov r0, r3
|
|
8015d86: f7fa feb3 bl 8010af0 <lwip_htons>
|
|
8015d8a: 4603 mov r3, r0
|
|
8015d8c: b2db uxtb r3, r3
|
|
8015d8e: f003 0303 and.w r3, r3, #3
|
|
8015d92: 2b00 cmp r3, #0
|
|
8015d94: d001 beq.n 8015d9a <tcp_receive+0x966>
|
|
8015d96: 2301 movs r3, #1
|
|
8015d98: e000 b.n 8015d9c <tcp_receive+0x968>
|
|
8015d9a: 2300 movs r3, #0
|
|
8015d9c: 4423 add r3, r4
|
|
8015d9e: b29a uxth r2, r3
|
|
8015da0: 4b65 ldr r3, [pc, #404] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015da2: 801a strh r2, [r3, #0]
|
|
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n",
|
|
8015da4: 4b64 ldr r3, [pc, #400] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015da6: 881b ldrh r3, [r3, #0]
|
|
8015da8: 461a mov r2, r3
|
|
8015daa: 4b64 ldr r3, [pc, #400] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015dac: 681b ldr r3, [r3, #0]
|
|
8015dae: 441a add r2, r3
|
|
8015db0: 6bfb ldr r3, [r7, #60] ; 0x3c
|
|
8015db2: 68db ldr r3, [r3, #12]
|
|
8015db4: 685b ldr r3, [r3, #4]
|
|
8015db6: 429a cmp r2, r3
|
|
8015db8: d006 beq.n 8015dc8 <tcp_receive+0x994>
|
|
8015dba: 4b62 ldr r3, [pc, #392] ; (8015f44 <tcp_receive+0xb10>)
|
|
8015dbc: f240 52fd movw r2, #1533 ; 0x5fd
|
|
8015dc0: 4961 ldr r1, [pc, #388] ; (8015f48 <tcp_receive+0xb14>)
|
|
8015dc2: 4862 ldr r0, [pc, #392] ; (8015f4c <tcp_receive+0xb18>)
|
|
8015dc4: f006 ff78 bl 801ccb8 <iprintf>
|
|
(seqno + tcplen) == next->tcphdr->seqno);
|
|
}
|
|
pcb->ooseq = next;
|
|
8015dc8: 687b ldr r3, [r7, #4]
|
|
8015dca: 6bfa ldr r2, [r7, #60] ; 0x3c
|
|
8015dcc: 675a str r2, [r3, #116] ; 0x74
|
|
}
|
|
}
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
|
|
pcb->rcv_nxt = seqno + tcplen;
|
|
8015dce: 4b5a ldr r3, [pc, #360] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015dd0: 881b ldrh r3, [r3, #0]
|
|
8015dd2: 461a mov r2, r3
|
|
8015dd4: 4b59 ldr r3, [pc, #356] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015dd6: 681b ldr r3, [r3, #0]
|
|
8015dd8: 441a add r2, r3
|
|
8015dda: 687b ldr r3, [r7, #4]
|
|
8015ddc: 625a str r2, [r3, #36] ; 0x24
|
|
|
|
/* Update the receiver's (our) window. */
|
|
LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen);
|
|
8015dde: 687b ldr r3, [r7, #4]
|
|
8015de0: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8015de2: 4b55 ldr r3, [pc, #340] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015de4: 881b ldrh r3, [r3, #0]
|
|
8015de6: 429a cmp r2, r3
|
|
8015de8: d206 bcs.n 8015df8 <tcp_receive+0x9c4>
|
|
8015dea: 4b56 ldr r3, [pc, #344] ; (8015f44 <tcp_receive+0xb10>)
|
|
8015dec: f240 6207 movw r2, #1543 ; 0x607
|
|
8015df0: 4957 ldr r1, [pc, #348] ; (8015f50 <tcp_receive+0xb1c>)
|
|
8015df2: 4856 ldr r0, [pc, #344] ; (8015f4c <tcp_receive+0xb18>)
|
|
8015df4: f006 ff60 bl 801ccb8 <iprintf>
|
|
pcb->rcv_wnd -= tcplen;
|
|
8015df8: 687b ldr r3, [r7, #4]
|
|
8015dfa: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8015dfc: 4b4e ldr r3, [pc, #312] ; (8015f38 <tcp_receive+0xb04>)
|
|
8015dfe: 881b ldrh r3, [r3, #0]
|
|
8015e00: 1ad3 subs r3, r2, r3
|
|
8015e02: b29a uxth r2, r3
|
|
8015e04: 687b ldr r3, [r7, #4]
|
|
8015e06: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
tcp_update_rcv_ann_wnd(pcb);
|
|
8015e08: 6878 ldr r0, [r7, #4]
|
|
8015e0a: f7fc ffcd bl 8012da8 <tcp_update_rcv_ann_wnd>
|
|
chains its data on this pbuf as well.
|
|
|
|
If the segment was a FIN, we set the TF_GOT_FIN flag that will
|
|
be used to indicate to the application that the remote side has
|
|
closed its end of the connection. */
|
|
if (inseg.p->tot_len > 0) {
|
|
8015e0e: 4b4c ldr r3, [pc, #304] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015e10: 685b ldr r3, [r3, #4]
|
|
8015e12: 891b ldrh r3, [r3, #8]
|
|
8015e14: 2b00 cmp r3, #0
|
|
8015e16: d006 beq.n 8015e26 <tcp_receive+0x9f2>
|
|
recv_data = inseg.p;
|
|
8015e18: 4b49 ldr r3, [pc, #292] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015e1a: 685b ldr r3, [r3, #4]
|
|
8015e1c: 4a4d ldr r2, [pc, #308] ; (8015f54 <tcp_receive+0xb20>)
|
|
8015e1e: 6013 str r3, [r2, #0]
|
|
/* Since this pbuf now is the responsibility of the
|
|
application, we delete our reference to it so that we won't
|
|
(mistakingly) deallocate it. */
|
|
inseg.p = NULL;
|
|
8015e20: 4b47 ldr r3, [pc, #284] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015e22: 2200 movs r2, #0
|
|
8015e24: 605a str r2, [r3, #4]
|
|
}
|
|
if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) {
|
|
8015e26: 4b46 ldr r3, [pc, #280] ; (8015f40 <tcp_receive+0xb0c>)
|
|
8015e28: 68db ldr r3, [r3, #12]
|
|
8015e2a: 899b ldrh r3, [r3, #12]
|
|
8015e2c: b29b uxth r3, r3
|
|
8015e2e: 4618 mov r0, r3
|
|
8015e30: f7fa fe5e bl 8010af0 <lwip_htons>
|
|
8015e34: 4603 mov r3, r0
|
|
8015e36: b2db uxtb r3, r3
|
|
8015e38: f003 0301 and.w r3, r3, #1
|
|
8015e3c: 2b00 cmp r3, #0
|
|
8015e3e: f000 80b8 beq.w 8015fb2 <tcp_receive+0xb7e>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n"));
|
|
recv_flags |= TF_GOT_FIN;
|
|
8015e42: 4b45 ldr r3, [pc, #276] ; (8015f58 <tcp_receive+0xb24>)
|
|
8015e44: 781b ldrb r3, [r3, #0]
|
|
8015e46: f043 0320 orr.w r3, r3, #32
|
|
8015e4a: b2da uxtb r2, r3
|
|
8015e4c: 4b42 ldr r3, [pc, #264] ; (8015f58 <tcp_receive+0xb24>)
|
|
8015e4e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
#if TCP_QUEUE_OOSEQ
|
|
/* We now check if we have segments on the ->ooseq queue that
|
|
are now in sequence. */
|
|
while (pcb->ooseq != NULL &&
|
|
8015e50: e0af b.n 8015fb2 <tcp_receive+0xb7e>
|
|
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
|
|
|
|
struct tcp_seg *cseg = pcb->ooseq;
|
|
8015e52: 687b ldr r3, [r7, #4]
|
|
8015e54: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015e56: 60bb str r3, [r7, #8]
|
|
seqno = pcb->ooseq->tcphdr->seqno;
|
|
8015e58: 687b ldr r3, [r7, #4]
|
|
8015e5a: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015e5c: 68db ldr r3, [r3, #12]
|
|
8015e5e: 685b ldr r3, [r3, #4]
|
|
8015e60: 4a36 ldr r2, [pc, #216] ; (8015f3c <tcp_receive+0xb08>)
|
|
8015e62: 6013 str r3, [r2, #0]
|
|
|
|
pcb->rcv_nxt += TCP_TCPLEN(cseg);
|
|
8015e64: 68bb ldr r3, [r7, #8]
|
|
8015e66: 891b ldrh r3, [r3, #8]
|
|
8015e68: 461c mov r4, r3
|
|
8015e6a: 68bb ldr r3, [r7, #8]
|
|
8015e6c: 68db ldr r3, [r3, #12]
|
|
8015e6e: 899b ldrh r3, [r3, #12]
|
|
8015e70: b29b uxth r3, r3
|
|
8015e72: 4618 mov r0, r3
|
|
8015e74: f7fa fe3c bl 8010af0 <lwip_htons>
|
|
8015e78: 4603 mov r3, r0
|
|
8015e7a: b2db uxtb r3, r3
|
|
8015e7c: f003 0303 and.w r3, r3, #3
|
|
8015e80: 2b00 cmp r3, #0
|
|
8015e82: d001 beq.n 8015e88 <tcp_receive+0xa54>
|
|
8015e84: 2301 movs r3, #1
|
|
8015e86: e000 b.n 8015e8a <tcp_receive+0xa56>
|
|
8015e88: 2300 movs r3, #0
|
|
8015e8a: 191a adds r2, r3, r4
|
|
8015e8c: 687b ldr r3, [r7, #4]
|
|
8015e8e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8015e90: 441a add r2, r3
|
|
8015e92: 687b ldr r3, [r7, #4]
|
|
8015e94: 625a str r2, [r3, #36] ; 0x24
|
|
LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n",
|
|
8015e96: 687b ldr r3, [r7, #4]
|
|
8015e98: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8015e9a: 461c mov r4, r3
|
|
8015e9c: 68bb ldr r3, [r7, #8]
|
|
8015e9e: 891b ldrh r3, [r3, #8]
|
|
8015ea0: 461d mov r5, r3
|
|
8015ea2: 68bb ldr r3, [r7, #8]
|
|
8015ea4: 68db ldr r3, [r3, #12]
|
|
8015ea6: 899b ldrh r3, [r3, #12]
|
|
8015ea8: b29b uxth r3, r3
|
|
8015eaa: 4618 mov r0, r3
|
|
8015eac: f7fa fe20 bl 8010af0 <lwip_htons>
|
|
8015eb0: 4603 mov r3, r0
|
|
8015eb2: b2db uxtb r3, r3
|
|
8015eb4: f003 0303 and.w r3, r3, #3
|
|
8015eb8: 2b00 cmp r3, #0
|
|
8015eba: d001 beq.n 8015ec0 <tcp_receive+0xa8c>
|
|
8015ebc: 2301 movs r3, #1
|
|
8015ebe: e000 b.n 8015ec2 <tcp_receive+0xa8e>
|
|
8015ec0: 2300 movs r3, #0
|
|
8015ec2: 442b add r3, r5
|
|
8015ec4: 429c cmp r4, r3
|
|
8015ec6: d206 bcs.n 8015ed6 <tcp_receive+0xaa2>
|
|
8015ec8: 4b1e ldr r3, [pc, #120] ; (8015f44 <tcp_receive+0xb10>)
|
|
8015eca: f240 622c movw r2, #1580 ; 0x62c
|
|
8015ece: 4923 ldr r1, [pc, #140] ; (8015f5c <tcp_receive+0xb28>)
|
|
8015ed0: 481e ldr r0, [pc, #120] ; (8015f4c <tcp_receive+0xb18>)
|
|
8015ed2: f006 fef1 bl 801ccb8 <iprintf>
|
|
pcb->rcv_wnd >= TCP_TCPLEN(cseg));
|
|
pcb->rcv_wnd -= TCP_TCPLEN(cseg);
|
|
8015ed6: 68bb ldr r3, [r7, #8]
|
|
8015ed8: 891b ldrh r3, [r3, #8]
|
|
8015eda: 461c mov r4, r3
|
|
8015edc: 68bb ldr r3, [r7, #8]
|
|
8015ede: 68db ldr r3, [r3, #12]
|
|
8015ee0: 899b ldrh r3, [r3, #12]
|
|
8015ee2: b29b uxth r3, r3
|
|
8015ee4: 4618 mov r0, r3
|
|
8015ee6: f7fa fe03 bl 8010af0 <lwip_htons>
|
|
8015eea: 4603 mov r3, r0
|
|
8015eec: b2db uxtb r3, r3
|
|
8015eee: f003 0303 and.w r3, r3, #3
|
|
8015ef2: 2b00 cmp r3, #0
|
|
8015ef4: d001 beq.n 8015efa <tcp_receive+0xac6>
|
|
8015ef6: 2301 movs r3, #1
|
|
8015ef8: e000 b.n 8015efc <tcp_receive+0xac8>
|
|
8015efa: 2300 movs r3, #0
|
|
8015efc: 1919 adds r1, r3, r4
|
|
8015efe: 687b ldr r3, [r7, #4]
|
|
8015f00: 8d1a ldrh r2, [r3, #40] ; 0x28
|
|
8015f02: b28b uxth r3, r1
|
|
8015f04: 1ad3 subs r3, r2, r3
|
|
8015f06: b29a uxth r2, r3
|
|
8015f08: 687b ldr r3, [r7, #4]
|
|
8015f0a: 851a strh r2, [r3, #40] ; 0x28
|
|
|
|
tcp_update_rcv_ann_wnd(pcb);
|
|
8015f0c: 6878 ldr r0, [r7, #4]
|
|
8015f0e: f7fc ff4b bl 8012da8 <tcp_update_rcv_ann_wnd>
|
|
|
|
if (cseg->p->tot_len > 0) {
|
|
8015f12: 68bb ldr r3, [r7, #8]
|
|
8015f14: 685b ldr r3, [r3, #4]
|
|
8015f16: 891b ldrh r3, [r3, #8]
|
|
8015f18: 2b00 cmp r3, #0
|
|
8015f1a: d028 beq.n 8015f6e <tcp_receive+0xb3a>
|
|
/* Chain this pbuf onto the pbuf that we will pass to
|
|
the application. */
|
|
/* With window scaling, this can overflow recv_data->tot_len, but
|
|
that's not a problem since we explicitly fix that before passing
|
|
recv_data to the application. */
|
|
if (recv_data) {
|
|
8015f1c: 4b0d ldr r3, [pc, #52] ; (8015f54 <tcp_receive+0xb20>)
|
|
8015f1e: 681b ldr r3, [r3, #0]
|
|
8015f20: 2b00 cmp r3, #0
|
|
8015f22: d01d beq.n 8015f60 <tcp_receive+0xb2c>
|
|
pbuf_cat(recv_data, cseg->p);
|
|
8015f24: 4b0b ldr r3, [pc, #44] ; (8015f54 <tcp_receive+0xb20>)
|
|
8015f26: 681a ldr r2, [r3, #0]
|
|
8015f28: 68bb ldr r3, [r7, #8]
|
|
8015f2a: 685b ldr r3, [r3, #4]
|
|
8015f2c: 4619 mov r1, r3
|
|
8015f2e: 4610 mov r0, r2
|
|
8015f30: f7fc fa60 bl 80123f4 <pbuf_cat>
|
|
8015f34: e018 b.n 8015f68 <tcp_receive+0xb34>
|
|
8015f36: bf00 nop
|
|
8015f38: 20008756 .word 0x20008756
|
|
8015f3c: 2000874c .word 0x2000874c
|
|
8015f40: 2000872c .word 0x2000872c
|
|
8015f44: 0801f2b0 .word 0x0801f2b0
|
|
8015f48: 0801f690 .word 0x0801f690
|
|
8015f4c: 0801f2fc .word 0x0801f2fc
|
|
8015f50: 0801f6cc .word 0x0801f6cc
|
|
8015f54: 2000875c .word 0x2000875c
|
|
8015f58: 20008759 .word 0x20008759
|
|
8015f5c: 0801f6ec .word 0x0801f6ec
|
|
} else {
|
|
recv_data = cseg->p;
|
|
8015f60: 68bb ldr r3, [r7, #8]
|
|
8015f62: 685b ldr r3, [r3, #4]
|
|
8015f64: 4a70 ldr r2, [pc, #448] ; (8016128 <tcp_receive+0xcf4>)
|
|
8015f66: 6013 str r3, [r2, #0]
|
|
}
|
|
cseg->p = NULL;
|
|
8015f68: 68bb ldr r3, [r7, #8]
|
|
8015f6a: 2200 movs r2, #0
|
|
8015f6c: 605a str r2, [r3, #4]
|
|
}
|
|
if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) {
|
|
8015f6e: 68bb ldr r3, [r7, #8]
|
|
8015f70: 68db ldr r3, [r3, #12]
|
|
8015f72: 899b ldrh r3, [r3, #12]
|
|
8015f74: b29b uxth r3, r3
|
|
8015f76: 4618 mov r0, r3
|
|
8015f78: f7fa fdba bl 8010af0 <lwip_htons>
|
|
8015f7c: 4603 mov r3, r0
|
|
8015f7e: b2db uxtb r3, r3
|
|
8015f80: f003 0301 and.w r3, r3, #1
|
|
8015f84: 2b00 cmp r3, #0
|
|
8015f86: d00d beq.n 8015fa4 <tcp_receive+0xb70>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n"));
|
|
recv_flags |= TF_GOT_FIN;
|
|
8015f88: 4b68 ldr r3, [pc, #416] ; (801612c <tcp_receive+0xcf8>)
|
|
8015f8a: 781b ldrb r3, [r3, #0]
|
|
8015f8c: f043 0320 orr.w r3, r3, #32
|
|
8015f90: b2da uxtb r2, r3
|
|
8015f92: 4b66 ldr r3, [pc, #408] ; (801612c <tcp_receive+0xcf8>)
|
|
8015f94: 701a strb r2, [r3, #0]
|
|
if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */
|
|
8015f96: 687b ldr r3, [r7, #4]
|
|
8015f98: 7d1b ldrb r3, [r3, #20]
|
|
8015f9a: 2b04 cmp r3, #4
|
|
8015f9c: d102 bne.n 8015fa4 <tcp_receive+0xb70>
|
|
pcb->state = CLOSE_WAIT;
|
|
8015f9e: 687b ldr r3, [r7, #4]
|
|
8015fa0: 2207 movs r2, #7
|
|
8015fa2: 751a strb r2, [r3, #20]
|
|
}
|
|
}
|
|
|
|
pcb->ooseq = cseg->next;
|
|
8015fa4: 68bb ldr r3, [r7, #8]
|
|
8015fa6: 681a ldr r2, [r3, #0]
|
|
8015fa8: 687b ldr r3, [r7, #4]
|
|
8015faa: 675a str r2, [r3, #116] ; 0x74
|
|
tcp_seg_free(cseg);
|
|
8015fac: 68b8 ldr r0, [r7, #8]
|
|
8015fae: f7fd fbd7 bl 8013760 <tcp_seg_free>
|
|
while (pcb->ooseq != NULL &&
|
|
8015fb2: 687b ldr r3, [r7, #4]
|
|
8015fb4: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015fb6: 2b00 cmp r3, #0
|
|
8015fb8: d008 beq.n 8015fcc <tcp_receive+0xb98>
|
|
pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) {
|
|
8015fba: 687b ldr r3, [r7, #4]
|
|
8015fbc: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8015fbe: 68db ldr r3, [r3, #12]
|
|
8015fc0: 685a ldr r2, [r3, #4]
|
|
8015fc2: 687b ldr r3, [r7, #4]
|
|
8015fc4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
while (pcb->ooseq != NULL &&
|
|
8015fc6: 429a cmp r2, r3
|
|
8015fc8: f43f af43 beq.w 8015e52 <tcp_receive+0xa1e>
|
|
#endif /* LWIP_TCP_SACK_OUT */
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
|
|
|
|
/* Acknowledge the segment(s). */
|
|
tcp_ack(pcb);
|
|
8015fcc: 687b ldr r3, [r7, #4]
|
|
8015fce: 8b5b ldrh r3, [r3, #26]
|
|
8015fd0: f003 0301 and.w r3, r3, #1
|
|
8015fd4: 2b00 cmp r3, #0
|
|
8015fd6: d00e beq.n 8015ff6 <tcp_receive+0xbc2>
|
|
8015fd8: 687b ldr r3, [r7, #4]
|
|
8015fda: 8b5b ldrh r3, [r3, #26]
|
|
8015fdc: f023 0301 bic.w r3, r3, #1
|
|
8015fe0: b29a uxth r2, r3
|
|
8015fe2: 687b ldr r3, [r7, #4]
|
|
8015fe4: 835a strh r2, [r3, #26]
|
|
8015fe6: 687b ldr r3, [r7, #4]
|
|
8015fe8: 8b5b ldrh r3, [r3, #26]
|
|
8015fea: f043 0302 orr.w r3, r3, #2
|
|
8015fee: b29a uxth r2, r3
|
|
8015ff0: 687b ldr r3, [r7, #4]
|
|
8015ff2: 835a strh r2, [r3, #26]
|
|
if (pcb->rcv_nxt == seqno) {
|
|
8015ff4: e188 b.n 8016308 <tcp_receive+0xed4>
|
|
tcp_ack(pcb);
|
|
8015ff6: 687b ldr r3, [r7, #4]
|
|
8015ff8: 8b5b ldrh r3, [r3, #26]
|
|
8015ffa: f043 0301 orr.w r3, r3, #1
|
|
8015ffe: b29a uxth r2, r3
|
|
8016000: 687b ldr r3, [r7, #4]
|
|
8016002: 835a strh r2, [r3, #26]
|
|
if (pcb->rcv_nxt == seqno) {
|
|
8016004: e180 b.n 8016308 <tcp_receive+0xed4>
|
|
} else {
|
|
/* We get here if the incoming segment is out-of-sequence. */
|
|
|
|
#if TCP_QUEUE_OOSEQ
|
|
/* We queue the segment on the ->ooseq queue. */
|
|
if (pcb->ooseq == NULL) {
|
|
8016006: 687b ldr r3, [r7, #4]
|
|
8016008: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
801600a: 2b00 cmp r3, #0
|
|
801600c: d106 bne.n 801601c <tcp_receive+0xbe8>
|
|
pcb->ooseq = tcp_seg_copy(&inseg);
|
|
801600e: 4848 ldr r0, [pc, #288] ; (8016130 <tcp_receive+0xcfc>)
|
|
8016010: f7fd fbbe bl 8013790 <tcp_seg_copy>
|
|
8016014: 4602 mov r2, r0
|
|
8016016: 687b ldr r3, [r7, #4]
|
|
8016018: 675a str r2, [r3, #116] ; 0x74
|
|
801601a: e16d b.n 80162f8 <tcp_receive+0xec4>
|
|
#if LWIP_TCP_SACK_OUT
|
|
/* This is the left edge of the lowest possible SACK range.
|
|
It may start before the newly received segment (possibly adjusted below). */
|
|
u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno;
|
|
#endif /* LWIP_TCP_SACK_OUT */
|
|
struct tcp_seg *next, *prev = NULL;
|
|
801601c: 2300 movs r3, #0
|
|
801601e: 637b str r3, [r7, #52] ; 0x34
|
|
for (next = pcb->ooseq; next != NULL; next = next->next) {
|
|
8016020: 687b ldr r3, [r7, #4]
|
|
8016022: 6f5b ldr r3, [r3, #116] ; 0x74
|
|
8016024: 63bb str r3, [r7, #56] ; 0x38
|
|
8016026: e157 b.n 80162d8 <tcp_receive+0xea4>
|
|
if (seqno == next->tcphdr->seqno) {
|
|
8016028: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801602a: 68db ldr r3, [r3, #12]
|
|
801602c: 685a ldr r2, [r3, #4]
|
|
801602e: 4b41 ldr r3, [pc, #260] ; (8016134 <tcp_receive+0xd00>)
|
|
8016030: 681b ldr r3, [r3, #0]
|
|
8016032: 429a cmp r2, r3
|
|
8016034: d11d bne.n 8016072 <tcp_receive+0xc3e>
|
|
/* The sequence number of the incoming segment is the
|
|
same as the sequence number of the segment on
|
|
->ooseq. We check the lengths to see which one to
|
|
discard. */
|
|
if (inseg.len > next->len) {
|
|
8016036: 4b3e ldr r3, [pc, #248] ; (8016130 <tcp_receive+0xcfc>)
|
|
8016038: 891a ldrh r2, [r3, #8]
|
|
801603a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801603c: 891b ldrh r3, [r3, #8]
|
|
801603e: 429a cmp r2, r3
|
|
8016040: f240 814f bls.w 80162e2 <tcp_receive+0xeae>
|
|
/* The incoming segment is larger than the old
|
|
segment. We replace some segments with the new
|
|
one. */
|
|
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
|
|
8016044: 483a ldr r0, [pc, #232] ; (8016130 <tcp_receive+0xcfc>)
|
|
8016046: f7fd fba3 bl 8013790 <tcp_seg_copy>
|
|
801604a: 6178 str r0, [r7, #20]
|
|
if (cseg != NULL) {
|
|
801604c: 697b ldr r3, [r7, #20]
|
|
801604e: 2b00 cmp r3, #0
|
|
8016050: f000 8149 beq.w 80162e6 <tcp_receive+0xeb2>
|
|
if (prev != NULL) {
|
|
8016054: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
8016056: 2b00 cmp r3, #0
|
|
8016058: d003 beq.n 8016062 <tcp_receive+0xc2e>
|
|
prev->next = cseg;
|
|
801605a: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801605c: 697a ldr r2, [r7, #20]
|
|
801605e: 601a str r2, [r3, #0]
|
|
8016060: e002 b.n 8016068 <tcp_receive+0xc34>
|
|
} else {
|
|
pcb->ooseq = cseg;
|
|
8016062: 687b ldr r3, [r7, #4]
|
|
8016064: 697a ldr r2, [r7, #20]
|
|
8016066: 675a str r2, [r3, #116] ; 0x74
|
|
}
|
|
tcp_oos_insert_segment(cseg, next);
|
|
8016068: 6bb9 ldr r1, [r7, #56] ; 0x38
|
|
801606a: 6978 ldr r0, [r7, #20]
|
|
801606c: f7ff f8de bl 801522c <tcp_oos_insert_segment>
|
|
}
|
|
break;
|
|
8016070: e139 b.n 80162e6 <tcp_receive+0xeb2>
|
|
segment was smaller than the old one; in either
|
|
case, we ditch the incoming segment. */
|
|
break;
|
|
}
|
|
} else {
|
|
if (prev == NULL) {
|
|
8016072: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
8016074: 2b00 cmp r3, #0
|
|
8016076: d117 bne.n 80160a8 <tcp_receive+0xc74>
|
|
if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {
|
|
8016078: 4b2e ldr r3, [pc, #184] ; (8016134 <tcp_receive+0xd00>)
|
|
801607a: 681a ldr r2, [r3, #0]
|
|
801607c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801607e: 68db ldr r3, [r3, #12]
|
|
8016080: 685b ldr r3, [r3, #4]
|
|
8016082: 1ad3 subs r3, r2, r3
|
|
8016084: 2b00 cmp r3, #0
|
|
8016086: da57 bge.n 8016138 <tcp_receive+0xd04>
|
|
/* The sequence number of the incoming segment is lower
|
|
than the sequence number of the first segment on the
|
|
queue. We put the incoming segment first on the
|
|
queue. */
|
|
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
|
|
8016088: 4829 ldr r0, [pc, #164] ; (8016130 <tcp_receive+0xcfc>)
|
|
801608a: f7fd fb81 bl 8013790 <tcp_seg_copy>
|
|
801608e: 61b8 str r0, [r7, #24]
|
|
if (cseg != NULL) {
|
|
8016090: 69bb ldr r3, [r7, #24]
|
|
8016092: 2b00 cmp r3, #0
|
|
8016094: f000 8129 beq.w 80162ea <tcp_receive+0xeb6>
|
|
pcb->ooseq = cseg;
|
|
8016098: 687b ldr r3, [r7, #4]
|
|
801609a: 69ba ldr r2, [r7, #24]
|
|
801609c: 675a str r2, [r3, #116] ; 0x74
|
|
tcp_oos_insert_segment(cseg, next);
|
|
801609e: 6bb9 ldr r1, [r7, #56] ; 0x38
|
|
80160a0: 69b8 ldr r0, [r7, #24]
|
|
80160a2: f7ff f8c3 bl 801522c <tcp_oos_insert_segment>
|
|
}
|
|
break;
|
|
80160a6: e120 b.n 80162ea <tcp_receive+0xeb6>
|
|
}
|
|
} else {
|
|
/*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) &&
|
|
TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/
|
|
if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) {
|
|
80160a8: 4b22 ldr r3, [pc, #136] ; (8016134 <tcp_receive+0xd00>)
|
|
80160aa: 681a ldr r2, [r3, #0]
|
|
80160ac: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
80160ae: 68db ldr r3, [r3, #12]
|
|
80160b0: 685b ldr r3, [r3, #4]
|
|
80160b2: 1ad3 subs r3, r2, r3
|
|
80160b4: 3b01 subs r3, #1
|
|
80160b6: 2b00 cmp r3, #0
|
|
80160b8: db3e blt.n 8016138 <tcp_receive+0xd04>
|
|
80160ba: 4b1e ldr r3, [pc, #120] ; (8016134 <tcp_receive+0xd00>)
|
|
80160bc: 681a ldr r2, [r3, #0]
|
|
80160be: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80160c0: 68db ldr r3, [r3, #12]
|
|
80160c2: 685b ldr r3, [r3, #4]
|
|
80160c4: 1ad3 subs r3, r2, r3
|
|
80160c6: 3301 adds r3, #1
|
|
80160c8: 2b00 cmp r3, #0
|
|
80160ca: dc35 bgt.n 8016138 <tcp_receive+0xd04>
|
|
/* The sequence number of the incoming segment is in
|
|
between the sequence numbers of the previous and
|
|
the next segment on ->ooseq. We trim trim the previous
|
|
segment, delete next segments that included in received segment
|
|
and trim received, if needed. */
|
|
struct tcp_seg *cseg = tcp_seg_copy(&inseg);
|
|
80160cc: 4818 ldr r0, [pc, #96] ; (8016130 <tcp_receive+0xcfc>)
|
|
80160ce: f7fd fb5f bl 8013790 <tcp_seg_copy>
|
|
80160d2: 61f8 str r0, [r7, #28]
|
|
if (cseg != NULL) {
|
|
80160d4: 69fb ldr r3, [r7, #28]
|
|
80160d6: 2b00 cmp r3, #0
|
|
80160d8: f000 8109 beq.w 80162ee <tcp_receive+0xeba>
|
|
if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) {
|
|
80160dc: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
80160de: 68db ldr r3, [r3, #12]
|
|
80160e0: 685b ldr r3, [r3, #4]
|
|
80160e2: 6b7a ldr r2, [r7, #52] ; 0x34
|
|
80160e4: 8912 ldrh r2, [r2, #8]
|
|
80160e6: 441a add r2, r3
|
|
80160e8: 4b12 ldr r3, [pc, #72] ; (8016134 <tcp_receive+0xd00>)
|
|
80160ea: 681b ldr r3, [r3, #0]
|
|
80160ec: 1ad3 subs r3, r2, r3
|
|
80160ee: 2b00 cmp r3, #0
|
|
80160f0: dd12 ble.n 8016118 <tcp_receive+0xce4>
|
|
/* We need to trim the prev segment. */
|
|
prev->len = (u16_t)(seqno - prev->tcphdr->seqno);
|
|
80160f2: 4b10 ldr r3, [pc, #64] ; (8016134 <tcp_receive+0xd00>)
|
|
80160f4: 681b ldr r3, [r3, #0]
|
|
80160f6: b29a uxth r2, r3
|
|
80160f8: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
80160fa: 68db ldr r3, [r3, #12]
|
|
80160fc: 685b ldr r3, [r3, #4]
|
|
80160fe: b29b uxth r3, r3
|
|
8016100: 1ad3 subs r3, r2, r3
|
|
8016102: b29a uxth r2, r3
|
|
8016104: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
8016106: 811a strh r2, [r3, #8]
|
|
pbuf_realloc(prev->p, prev->len);
|
|
8016108: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801610a: 685a ldr r2, [r3, #4]
|
|
801610c: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801610e: 891b ldrh r3, [r3, #8]
|
|
8016110: 4619 mov r1, r3
|
|
8016112: 4610 mov r0, r2
|
|
8016114: f7fb ff1a bl 8011f4c <pbuf_realloc>
|
|
}
|
|
prev->next = cseg;
|
|
8016118: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801611a: 69fa ldr r2, [r7, #28]
|
|
801611c: 601a str r2, [r3, #0]
|
|
tcp_oos_insert_segment(cseg, next);
|
|
801611e: 6bb9 ldr r1, [r7, #56] ; 0x38
|
|
8016120: 69f8 ldr r0, [r7, #28]
|
|
8016122: f7ff f883 bl 801522c <tcp_oos_insert_segment>
|
|
}
|
|
break;
|
|
8016126: e0e2 b.n 80162ee <tcp_receive+0xeba>
|
|
8016128: 2000875c .word 0x2000875c
|
|
801612c: 20008759 .word 0x20008759
|
|
8016130: 2000872c .word 0x2000872c
|
|
8016134: 2000874c .word 0x2000874c
|
|
#endif /* LWIP_TCP_SACK_OUT */
|
|
|
|
/* We don't use 'prev' below, so let's set it to current 'next'.
|
|
This way even if we break the loop below, 'prev' will be pointing
|
|
at the segment right in front of the newly added one. */
|
|
prev = next;
|
|
8016138: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801613a: 637b str r3, [r7, #52] ; 0x34
|
|
|
|
/* If the "next" segment is the last segment on the
|
|
ooseq queue, we add the incoming segment to the end
|
|
of the list. */
|
|
if (next->next == NULL &&
|
|
801613c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801613e: 681b ldr r3, [r3, #0]
|
|
8016140: 2b00 cmp r3, #0
|
|
8016142: f040 80c6 bne.w 80162d2 <tcp_receive+0xe9e>
|
|
TCP_SEQ_GT(seqno, next->tcphdr->seqno)) {
|
|
8016146: 4b80 ldr r3, [pc, #512] ; (8016348 <tcp_receive+0xf14>)
|
|
8016148: 681a ldr r2, [r3, #0]
|
|
801614a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801614c: 68db ldr r3, [r3, #12]
|
|
801614e: 685b ldr r3, [r3, #4]
|
|
8016150: 1ad3 subs r3, r2, r3
|
|
if (next->next == NULL &&
|
|
8016152: 2b00 cmp r3, #0
|
|
8016154: f340 80bd ble.w 80162d2 <tcp_receive+0xe9e>
|
|
if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) {
|
|
8016158: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801615a: 68db ldr r3, [r3, #12]
|
|
801615c: 899b ldrh r3, [r3, #12]
|
|
801615e: b29b uxth r3, r3
|
|
8016160: 4618 mov r0, r3
|
|
8016162: f7fa fcc5 bl 8010af0 <lwip_htons>
|
|
8016166: 4603 mov r3, r0
|
|
8016168: b2db uxtb r3, r3
|
|
801616a: f003 0301 and.w r3, r3, #1
|
|
801616e: 2b00 cmp r3, #0
|
|
8016170: f040 80bf bne.w 80162f2 <tcp_receive+0xebe>
|
|
/* segment "next" already contains all data */
|
|
break;
|
|
}
|
|
next->next = tcp_seg_copy(&inseg);
|
|
8016174: 4875 ldr r0, [pc, #468] ; (801634c <tcp_receive+0xf18>)
|
|
8016176: f7fd fb0b bl 8013790 <tcp_seg_copy>
|
|
801617a: 4602 mov r2, r0
|
|
801617c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801617e: 601a str r2, [r3, #0]
|
|
if (next->next != NULL) {
|
|
8016180: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8016182: 681b ldr r3, [r3, #0]
|
|
8016184: 2b00 cmp r3, #0
|
|
8016186: f000 80b6 beq.w 80162f6 <tcp_receive+0xec2>
|
|
if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) {
|
|
801618a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801618c: 68db ldr r3, [r3, #12]
|
|
801618e: 685b ldr r3, [r3, #4]
|
|
8016190: 6bba ldr r2, [r7, #56] ; 0x38
|
|
8016192: 8912 ldrh r2, [r2, #8]
|
|
8016194: 441a add r2, r3
|
|
8016196: 4b6c ldr r3, [pc, #432] ; (8016348 <tcp_receive+0xf14>)
|
|
8016198: 681b ldr r3, [r3, #0]
|
|
801619a: 1ad3 subs r3, r2, r3
|
|
801619c: 2b00 cmp r3, #0
|
|
801619e: dd12 ble.n 80161c6 <tcp_receive+0xd92>
|
|
/* We need to trim the last segment. */
|
|
next->len = (u16_t)(seqno - next->tcphdr->seqno);
|
|
80161a0: 4b69 ldr r3, [pc, #420] ; (8016348 <tcp_receive+0xf14>)
|
|
80161a2: 681b ldr r3, [r3, #0]
|
|
80161a4: b29a uxth r2, r3
|
|
80161a6: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80161a8: 68db ldr r3, [r3, #12]
|
|
80161aa: 685b ldr r3, [r3, #4]
|
|
80161ac: b29b uxth r3, r3
|
|
80161ae: 1ad3 subs r3, r2, r3
|
|
80161b0: b29a uxth r2, r3
|
|
80161b2: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80161b4: 811a strh r2, [r3, #8]
|
|
pbuf_realloc(next->p, next->len);
|
|
80161b6: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80161b8: 685a ldr r2, [r3, #4]
|
|
80161ba: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80161bc: 891b ldrh r3, [r3, #8]
|
|
80161be: 4619 mov r1, r3
|
|
80161c0: 4610 mov r0, r2
|
|
80161c2: f7fb fec3 bl 8011f4c <pbuf_realloc>
|
|
}
|
|
/* check if the remote side overruns our receive window */
|
|
if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) {
|
|
80161c6: 4b62 ldr r3, [pc, #392] ; (8016350 <tcp_receive+0xf1c>)
|
|
80161c8: 881b ldrh r3, [r3, #0]
|
|
80161ca: 461a mov r2, r3
|
|
80161cc: 4b5e ldr r3, [pc, #376] ; (8016348 <tcp_receive+0xf14>)
|
|
80161ce: 681b ldr r3, [r3, #0]
|
|
80161d0: 441a add r2, r3
|
|
80161d2: 687b ldr r3, [r7, #4]
|
|
80161d4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80161d6: 6879 ldr r1, [r7, #4]
|
|
80161d8: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
80161da: 440b add r3, r1
|
|
80161dc: 1ad3 subs r3, r2, r3
|
|
80161de: 2b00 cmp r3, #0
|
|
80161e0: f340 8089 ble.w 80162f6 <tcp_receive+0xec2>
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG,
|
|
("tcp_receive: other end overran receive window"
|
|
"seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n",
|
|
seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd));
|
|
if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) {
|
|
80161e4: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80161e6: 681b ldr r3, [r3, #0]
|
|
80161e8: 68db ldr r3, [r3, #12]
|
|
80161ea: 899b ldrh r3, [r3, #12]
|
|
80161ec: b29b uxth r3, r3
|
|
80161ee: 4618 mov r0, r3
|
|
80161f0: f7fa fc7e bl 8010af0 <lwip_htons>
|
|
80161f4: 4603 mov r3, r0
|
|
80161f6: b2db uxtb r3, r3
|
|
80161f8: f003 0301 and.w r3, r3, #1
|
|
80161fc: 2b00 cmp r3, #0
|
|
80161fe: d022 beq.n 8016246 <tcp_receive+0xe12>
|
|
/* Must remove the FIN from the header as we're trimming
|
|
* that byte of sequence-space from the packet */
|
|
TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN);
|
|
8016200: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8016202: 681b ldr r3, [r3, #0]
|
|
8016204: 68db ldr r3, [r3, #12]
|
|
8016206: 899b ldrh r3, [r3, #12]
|
|
8016208: b29b uxth r3, r3
|
|
801620a: b21b sxth r3, r3
|
|
801620c: f423 537c bic.w r3, r3, #16128 ; 0x3f00
|
|
8016210: b21c sxth r4, r3
|
|
8016212: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8016214: 681b ldr r3, [r3, #0]
|
|
8016216: 68db ldr r3, [r3, #12]
|
|
8016218: 899b ldrh r3, [r3, #12]
|
|
801621a: b29b uxth r3, r3
|
|
801621c: 4618 mov r0, r3
|
|
801621e: f7fa fc67 bl 8010af0 <lwip_htons>
|
|
8016222: 4603 mov r3, r0
|
|
8016224: b2db uxtb r3, r3
|
|
8016226: b29b uxth r3, r3
|
|
8016228: f003 033e and.w r3, r3, #62 ; 0x3e
|
|
801622c: b29b uxth r3, r3
|
|
801622e: 4618 mov r0, r3
|
|
8016230: f7fa fc5e bl 8010af0 <lwip_htons>
|
|
8016234: 4603 mov r3, r0
|
|
8016236: b21b sxth r3, r3
|
|
8016238: 4323 orrs r3, r4
|
|
801623a: b21a sxth r2, r3
|
|
801623c: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801623e: 681b ldr r3, [r3, #0]
|
|
8016240: 68db ldr r3, [r3, #12]
|
|
8016242: b292 uxth r2, r2
|
|
8016244: 819a strh r2, [r3, #12]
|
|
}
|
|
/* Adjust length of segment to fit in the window. */
|
|
next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno);
|
|
8016246: 687b ldr r3, [r7, #4]
|
|
8016248: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801624a: b29a uxth r2, r3
|
|
801624c: 687b ldr r3, [r7, #4]
|
|
801624e: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8016250: 4413 add r3, r2
|
|
8016252: b299 uxth r1, r3
|
|
8016254: 4b3c ldr r3, [pc, #240] ; (8016348 <tcp_receive+0xf14>)
|
|
8016256: 681b ldr r3, [r3, #0]
|
|
8016258: b29a uxth r2, r3
|
|
801625a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801625c: 681b ldr r3, [r3, #0]
|
|
801625e: 1a8a subs r2, r1, r2
|
|
8016260: b292 uxth r2, r2
|
|
8016262: 811a strh r2, [r3, #8]
|
|
pbuf_realloc(next->next->p, next->next->len);
|
|
8016264: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8016266: 681b ldr r3, [r3, #0]
|
|
8016268: 685a ldr r2, [r3, #4]
|
|
801626a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801626c: 681b ldr r3, [r3, #0]
|
|
801626e: 891b ldrh r3, [r3, #8]
|
|
8016270: 4619 mov r1, r3
|
|
8016272: 4610 mov r0, r2
|
|
8016274: f7fb fe6a bl 8011f4c <pbuf_realloc>
|
|
tcplen = TCP_TCPLEN(next->next);
|
|
8016278: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801627a: 681b ldr r3, [r3, #0]
|
|
801627c: 891c ldrh r4, [r3, #8]
|
|
801627e: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
8016280: 681b ldr r3, [r3, #0]
|
|
8016282: 68db ldr r3, [r3, #12]
|
|
8016284: 899b ldrh r3, [r3, #12]
|
|
8016286: b29b uxth r3, r3
|
|
8016288: 4618 mov r0, r3
|
|
801628a: f7fa fc31 bl 8010af0 <lwip_htons>
|
|
801628e: 4603 mov r3, r0
|
|
8016290: b2db uxtb r3, r3
|
|
8016292: f003 0303 and.w r3, r3, #3
|
|
8016296: 2b00 cmp r3, #0
|
|
8016298: d001 beq.n 801629e <tcp_receive+0xe6a>
|
|
801629a: 2301 movs r3, #1
|
|
801629c: e000 b.n 80162a0 <tcp_receive+0xe6c>
|
|
801629e: 2300 movs r3, #0
|
|
80162a0: 4423 add r3, r4
|
|
80162a2: b29a uxth r2, r3
|
|
80162a4: 4b2a ldr r3, [pc, #168] ; (8016350 <tcp_receive+0xf1c>)
|
|
80162a6: 801a strh r2, [r3, #0]
|
|
LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n",
|
|
80162a8: 4b29 ldr r3, [pc, #164] ; (8016350 <tcp_receive+0xf1c>)
|
|
80162aa: 881b ldrh r3, [r3, #0]
|
|
80162ac: 461a mov r2, r3
|
|
80162ae: 4b26 ldr r3, [pc, #152] ; (8016348 <tcp_receive+0xf14>)
|
|
80162b0: 681b ldr r3, [r3, #0]
|
|
80162b2: 441a add r2, r3
|
|
80162b4: 687b ldr r3, [r7, #4]
|
|
80162b6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80162b8: 6879 ldr r1, [r7, #4]
|
|
80162ba: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
80162bc: 440b add r3, r1
|
|
80162be: 429a cmp r2, r3
|
|
80162c0: d019 beq.n 80162f6 <tcp_receive+0xec2>
|
|
80162c2: 4b24 ldr r3, [pc, #144] ; (8016354 <tcp_receive+0xf20>)
|
|
80162c4: f240 62f9 movw r2, #1785 ; 0x6f9
|
|
80162c8: 4923 ldr r1, [pc, #140] ; (8016358 <tcp_receive+0xf24>)
|
|
80162ca: 4824 ldr r0, [pc, #144] ; (801635c <tcp_receive+0xf28>)
|
|
80162cc: f006 fcf4 bl 801ccb8 <iprintf>
|
|
(seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd));
|
|
}
|
|
}
|
|
break;
|
|
80162d0: e011 b.n 80162f6 <tcp_receive+0xec2>
|
|
for (next = pcb->ooseq; next != NULL; next = next->next) {
|
|
80162d2: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80162d4: 681b ldr r3, [r3, #0]
|
|
80162d6: 63bb str r3, [r7, #56] ; 0x38
|
|
80162d8: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
80162da: 2b00 cmp r3, #0
|
|
80162dc: f47f aea4 bne.w 8016028 <tcp_receive+0xbf4>
|
|
80162e0: e00a b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162e2: bf00 nop
|
|
80162e4: e008 b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162e6: bf00 nop
|
|
80162e8: e006 b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162ea: bf00 nop
|
|
80162ec: e004 b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162ee: bf00 nop
|
|
80162f0: e002 b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162f2: bf00 nop
|
|
80162f4: e000 b.n 80162f8 <tcp_receive+0xec4>
|
|
break;
|
|
80162f6: bf00 nop
|
|
#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */
|
|
#endif /* TCP_QUEUE_OOSEQ */
|
|
|
|
/* We send the ACK packet after we've (potentially) dealt with SACKs,
|
|
so they can be included in the acknowledgment. */
|
|
tcp_send_empty_ack(pcb);
|
|
80162f8: 6878 ldr r0, [r7, #4]
|
|
80162fa: f001 fa43 bl 8017784 <tcp_send_empty_ack>
|
|
if (pcb->rcv_nxt == seqno) {
|
|
80162fe: e003 b.n 8016308 <tcp_receive+0xed4>
|
|
}
|
|
} else {
|
|
/* The incoming segment is not within the window. */
|
|
tcp_send_empty_ack(pcb);
|
|
8016300: 6878 ldr r0, [r7, #4]
|
|
8016302: f001 fa3f bl 8017784 <tcp_send_empty_ack>
|
|
if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt,
|
|
8016306: e01a b.n 801633e <tcp_receive+0xf0a>
|
|
8016308: e019 b.n 801633e <tcp_receive+0xf0a>
|
|
}
|
|
} else {
|
|
/* Segments with length 0 is taken care of here. Segments that
|
|
fall out of the window are ACKed. */
|
|
if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) {
|
|
801630a: 4b0f ldr r3, [pc, #60] ; (8016348 <tcp_receive+0xf14>)
|
|
801630c: 681a ldr r2, [r3, #0]
|
|
801630e: 687b ldr r3, [r7, #4]
|
|
8016310: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8016312: 1ad3 subs r3, r2, r3
|
|
8016314: 2b00 cmp r3, #0
|
|
8016316: db0a blt.n 801632e <tcp_receive+0xefa>
|
|
8016318: 4b0b ldr r3, [pc, #44] ; (8016348 <tcp_receive+0xf14>)
|
|
801631a: 681a ldr r2, [r3, #0]
|
|
801631c: 687b ldr r3, [r7, #4]
|
|
801631e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8016320: 6879 ldr r1, [r7, #4]
|
|
8016322: 8d09 ldrh r1, [r1, #40] ; 0x28
|
|
8016324: 440b add r3, r1
|
|
8016326: 1ad3 subs r3, r2, r3
|
|
8016328: 3301 adds r3, #1
|
|
801632a: 2b00 cmp r3, #0
|
|
801632c: dd07 ble.n 801633e <tcp_receive+0xf0a>
|
|
tcp_ack_now(pcb);
|
|
801632e: 687b ldr r3, [r7, #4]
|
|
8016330: 8b5b ldrh r3, [r3, #26]
|
|
8016332: f043 0302 orr.w r3, r3, #2
|
|
8016336: b29a uxth r2, r3
|
|
8016338: 687b ldr r3, [r7, #4]
|
|
801633a: 835a strh r2, [r3, #26]
|
|
}
|
|
}
|
|
}
|
|
801633c: e7ff b.n 801633e <tcp_receive+0xf0a>
|
|
801633e: bf00 nop
|
|
8016340: 3750 adds r7, #80 ; 0x50
|
|
8016342: 46bd mov sp, r7
|
|
8016344: bdb0 pop {r4, r5, r7, pc}
|
|
8016346: bf00 nop
|
|
8016348: 2000874c .word 0x2000874c
|
|
801634c: 2000872c .word 0x2000872c
|
|
8016350: 20008756 .word 0x20008756
|
|
8016354: 0801f2b0 .word 0x0801f2b0
|
|
8016358: 0801f658 .word 0x0801f658
|
|
801635c: 0801f2fc .word 0x0801f2fc
|
|
|
|
08016360 <tcp_get_next_optbyte>:
|
|
|
|
static u8_t
|
|
tcp_get_next_optbyte(void)
|
|
{
|
|
8016360: b480 push {r7}
|
|
8016362: b083 sub sp, #12
|
|
8016364: af00 add r7, sp, #0
|
|
u16_t optidx = tcp_optidx++;
|
|
8016366: 4b15 ldr r3, [pc, #84] ; (80163bc <tcp_get_next_optbyte+0x5c>)
|
|
8016368: 881b ldrh r3, [r3, #0]
|
|
801636a: 1c5a adds r2, r3, #1
|
|
801636c: b291 uxth r1, r2
|
|
801636e: 4a13 ldr r2, [pc, #76] ; (80163bc <tcp_get_next_optbyte+0x5c>)
|
|
8016370: 8011 strh r1, [r2, #0]
|
|
8016372: 80fb strh r3, [r7, #6]
|
|
if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) {
|
|
8016374: 4b12 ldr r3, [pc, #72] ; (80163c0 <tcp_get_next_optbyte+0x60>)
|
|
8016376: 681b ldr r3, [r3, #0]
|
|
8016378: 2b00 cmp r3, #0
|
|
801637a: d004 beq.n 8016386 <tcp_get_next_optbyte+0x26>
|
|
801637c: 4b11 ldr r3, [pc, #68] ; (80163c4 <tcp_get_next_optbyte+0x64>)
|
|
801637e: 881b ldrh r3, [r3, #0]
|
|
8016380: 88fa ldrh r2, [r7, #6]
|
|
8016382: 429a cmp r2, r3
|
|
8016384: d208 bcs.n 8016398 <tcp_get_next_optbyte+0x38>
|
|
u8_t *opts = (u8_t *)tcphdr + TCP_HLEN;
|
|
8016386: 4b10 ldr r3, [pc, #64] ; (80163c8 <tcp_get_next_optbyte+0x68>)
|
|
8016388: 681b ldr r3, [r3, #0]
|
|
801638a: 3314 adds r3, #20
|
|
801638c: 603b str r3, [r7, #0]
|
|
return opts[optidx];
|
|
801638e: 88fb ldrh r3, [r7, #6]
|
|
8016390: 683a ldr r2, [r7, #0]
|
|
8016392: 4413 add r3, r2
|
|
8016394: 781b ldrb r3, [r3, #0]
|
|
8016396: e00b b.n 80163b0 <tcp_get_next_optbyte+0x50>
|
|
} else {
|
|
u8_t idx = (u8_t)(optidx - tcphdr_opt1len);
|
|
8016398: 88fb ldrh r3, [r7, #6]
|
|
801639a: b2da uxtb r2, r3
|
|
801639c: 4b09 ldr r3, [pc, #36] ; (80163c4 <tcp_get_next_optbyte+0x64>)
|
|
801639e: 881b ldrh r3, [r3, #0]
|
|
80163a0: b2db uxtb r3, r3
|
|
80163a2: 1ad3 subs r3, r2, r3
|
|
80163a4: 717b strb r3, [r7, #5]
|
|
return tcphdr_opt2[idx];
|
|
80163a6: 4b06 ldr r3, [pc, #24] ; (80163c0 <tcp_get_next_optbyte+0x60>)
|
|
80163a8: 681a ldr r2, [r3, #0]
|
|
80163aa: 797b ldrb r3, [r7, #5]
|
|
80163ac: 4413 add r3, r2
|
|
80163ae: 781b ldrb r3, [r3, #0]
|
|
}
|
|
}
|
|
80163b0: 4618 mov r0, r3
|
|
80163b2: 370c adds r7, #12
|
|
80163b4: 46bd mov sp, r7
|
|
80163b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80163ba: 4770 bx lr
|
|
80163bc: 20008748 .word 0x20008748
|
|
80163c0: 20008744 .word 0x20008744
|
|
80163c4: 20008742 .word 0x20008742
|
|
80163c8: 2000873c .word 0x2000873c
|
|
|
|
080163cc <tcp_parseopt>:
|
|
*
|
|
* @param pcb the tcp_pcb for which a segment arrived
|
|
*/
|
|
static void
|
|
tcp_parseopt(struct tcp_pcb *pcb)
|
|
{
|
|
80163cc: b580 push {r7, lr}
|
|
80163ce: b084 sub sp, #16
|
|
80163d0: af00 add r7, sp, #0
|
|
80163d2: 6078 str r0, [r7, #4]
|
|
u16_t mss;
|
|
#if LWIP_TCP_TIMESTAMPS
|
|
u32_t tsval;
|
|
#endif
|
|
|
|
LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL);
|
|
80163d4: 687b ldr r3, [r7, #4]
|
|
80163d6: 2b00 cmp r3, #0
|
|
80163d8: d106 bne.n 80163e8 <tcp_parseopt+0x1c>
|
|
80163da: 4b31 ldr r3, [pc, #196] ; (80164a0 <tcp_parseopt+0xd4>)
|
|
80163dc: f240 727d movw r2, #1917 ; 0x77d
|
|
80163e0: 4930 ldr r1, [pc, #192] ; (80164a4 <tcp_parseopt+0xd8>)
|
|
80163e2: 4831 ldr r0, [pc, #196] ; (80164a8 <tcp_parseopt+0xdc>)
|
|
80163e4: f006 fc68 bl 801ccb8 <iprintf>
|
|
|
|
/* Parse the TCP MSS option, if present. */
|
|
if (tcphdr_optlen != 0) {
|
|
80163e8: 4b30 ldr r3, [pc, #192] ; (80164ac <tcp_parseopt+0xe0>)
|
|
80163ea: 881b ldrh r3, [r3, #0]
|
|
80163ec: 2b00 cmp r3, #0
|
|
80163ee: d053 beq.n 8016498 <tcp_parseopt+0xcc>
|
|
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
|
|
80163f0: 4b2f ldr r3, [pc, #188] ; (80164b0 <tcp_parseopt+0xe4>)
|
|
80163f2: 2200 movs r2, #0
|
|
80163f4: 801a strh r2, [r3, #0]
|
|
80163f6: e043 b.n 8016480 <tcp_parseopt+0xb4>
|
|
u8_t opt = tcp_get_next_optbyte();
|
|
80163f8: f7ff ffb2 bl 8016360 <tcp_get_next_optbyte>
|
|
80163fc: 4603 mov r3, r0
|
|
80163fe: 73fb strb r3, [r7, #15]
|
|
switch (opt) {
|
|
8016400: 7bfb ldrb r3, [r7, #15]
|
|
8016402: 2b01 cmp r3, #1
|
|
8016404: d03c beq.n 8016480 <tcp_parseopt+0xb4>
|
|
8016406: 2b02 cmp r3, #2
|
|
8016408: d002 beq.n 8016410 <tcp_parseopt+0x44>
|
|
801640a: 2b00 cmp r3, #0
|
|
801640c: d03f beq.n 801648e <tcp_parseopt+0xc2>
|
|
801640e: e026 b.n 801645e <tcp_parseopt+0x92>
|
|
/* NOP option. */
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n"));
|
|
break;
|
|
case LWIP_TCP_OPT_MSS:
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n"));
|
|
if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) {
|
|
8016410: f7ff ffa6 bl 8016360 <tcp_get_next_optbyte>
|
|
8016414: 4603 mov r3, r0
|
|
8016416: 2b04 cmp r3, #4
|
|
8016418: d13b bne.n 8016492 <tcp_parseopt+0xc6>
|
|
801641a: 4b25 ldr r3, [pc, #148] ; (80164b0 <tcp_parseopt+0xe4>)
|
|
801641c: 881b ldrh r3, [r3, #0]
|
|
801641e: 3302 adds r3, #2
|
|
8016420: 4a22 ldr r2, [pc, #136] ; (80164ac <tcp_parseopt+0xe0>)
|
|
8016422: 8812 ldrh r2, [r2, #0]
|
|
8016424: 4293 cmp r3, r2
|
|
8016426: dc34 bgt.n 8016492 <tcp_parseopt+0xc6>
|
|
/* Bad length */
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n"));
|
|
return;
|
|
}
|
|
/* An MSS option with the right option length. */
|
|
mss = (u16_t)(tcp_get_next_optbyte() << 8);
|
|
8016428: f7ff ff9a bl 8016360 <tcp_get_next_optbyte>
|
|
801642c: 4603 mov r3, r0
|
|
801642e: b29b uxth r3, r3
|
|
8016430: 021b lsls r3, r3, #8
|
|
8016432: 81bb strh r3, [r7, #12]
|
|
mss |= tcp_get_next_optbyte();
|
|
8016434: f7ff ff94 bl 8016360 <tcp_get_next_optbyte>
|
|
8016438: 4603 mov r3, r0
|
|
801643a: b29a uxth r2, r3
|
|
801643c: 89bb ldrh r3, [r7, #12]
|
|
801643e: 4313 orrs r3, r2
|
|
8016440: 81bb strh r3, [r7, #12]
|
|
/* Limit the mss to the configured TCP_MSS and prevent division by zero */
|
|
pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss;
|
|
8016442: 89bb ldrh r3, [r7, #12]
|
|
8016444: f5b3 7f06 cmp.w r3, #536 ; 0x218
|
|
8016448: d804 bhi.n 8016454 <tcp_parseopt+0x88>
|
|
801644a: 89bb ldrh r3, [r7, #12]
|
|
801644c: 2b00 cmp r3, #0
|
|
801644e: d001 beq.n 8016454 <tcp_parseopt+0x88>
|
|
8016450: 89ba ldrh r2, [r7, #12]
|
|
8016452: e001 b.n 8016458 <tcp_parseopt+0x8c>
|
|
8016454: f44f 7206 mov.w r2, #536 ; 0x218
|
|
8016458: 687b ldr r3, [r7, #4]
|
|
801645a: 865a strh r2, [r3, #50] ; 0x32
|
|
break;
|
|
801645c: e010 b.n 8016480 <tcp_parseopt+0xb4>
|
|
}
|
|
break;
|
|
#endif /* LWIP_TCP_SACK_OUT */
|
|
default:
|
|
LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n"));
|
|
data = tcp_get_next_optbyte();
|
|
801645e: f7ff ff7f bl 8016360 <tcp_get_next_optbyte>
|
|
8016462: 4603 mov r3, r0
|
|
8016464: 72fb strb r3, [r7, #11]
|
|
if (data < 2) {
|
|
8016466: 7afb ldrb r3, [r7, #11]
|
|
8016468: 2b01 cmp r3, #1
|
|
801646a: d914 bls.n 8016496 <tcp_parseopt+0xca>
|
|
and we don't process them further. */
|
|
return;
|
|
}
|
|
/* All other options have a length field, so that we easily
|
|
can skip past them. */
|
|
tcp_optidx += data - 2;
|
|
801646c: 7afb ldrb r3, [r7, #11]
|
|
801646e: b29a uxth r2, r3
|
|
8016470: 4b0f ldr r3, [pc, #60] ; (80164b0 <tcp_parseopt+0xe4>)
|
|
8016472: 881b ldrh r3, [r3, #0]
|
|
8016474: 4413 add r3, r2
|
|
8016476: b29b uxth r3, r3
|
|
8016478: 3b02 subs r3, #2
|
|
801647a: b29a uxth r2, r3
|
|
801647c: 4b0c ldr r3, [pc, #48] ; (80164b0 <tcp_parseopt+0xe4>)
|
|
801647e: 801a strh r2, [r3, #0]
|
|
for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) {
|
|
8016480: 4b0b ldr r3, [pc, #44] ; (80164b0 <tcp_parseopt+0xe4>)
|
|
8016482: 881a ldrh r2, [r3, #0]
|
|
8016484: 4b09 ldr r3, [pc, #36] ; (80164ac <tcp_parseopt+0xe0>)
|
|
8016486: 881b ldrh r3, [r3, #0]
|
|
8016488: 429a cmp r2, r3
|
|
801648a: d3b5 bcc.n 80163f8 <tcp_parseopt+0x2c>
|
|
801648c: e004 b.n 8016498 <tcp_parseopt+0xcc>
|
|
return;
|
|
801648e: bf00 nop
|
|
8016490: e002 b.n 8016498 <tcp_parseopt+0xcc>
|
|
return;
|
|
8016492: bf00 nop
|
|
8016494: e000 b.n 8016498 <tcp_parseopt+0xcc>
|
|
return;
|
|
8016496: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8016498: 3710 adds r7, #16
|
|
801649a: 46bd mov sp, r7
|
|
801649c: bd80 pop {r7, pc}
|
|
801649e: bf00 nop
|
|
80164a0: 0801f2b0 .word 0x0801f2b0
|
|
80164a4: 0801f714 .word 0x0801f714
|
|
80164a8: 0801f2fc .word 0x0801f2fc
|
|
80164ac: 20008740 .word 0x20008740
|
|
80164b0: 20008748 .word 0x20008748
|
|
|
|
080164b4 <tcp_trigger_input_pcb_close>:
|
|
|
|
void
|
|
tcp_trigger_input_pcb_close(void)
|
|
{
|
|
80164b4: b480 push {r7}
|
|
80164b6: af00 add r7, sp, #0
|
|
recv_flags |= TF_CLOSED;
|
|
80164b8: 4b05 ldr r3, [pc, #20] ; (80164d0 <tcp_trigger_input_pcb_close+0x1c>)
|
|
80164ba: 781b ldrb r3, [r3, #0]
|
|
80164bc: f043 0310 orr.w r3, r3, #16
|
|
80164c0: b2da uxtb r2, r3
|
|
80164c2: 4b03 ldr r3, [pc, #12] ; (80164d0 <tcp_trigger_input_pcb_close+0x1c>)
|
|
80164c4: 701a strb r2, [r3, #0]
|
|
}
|
|
80164c6: bf00 nop
|
|
80164c8: 46bd mov sp, r7
|
|
80164ca: f85d 7b04 ldr.w r7, [sp], #4
|
|
80164ce: 4770 bx lr
|
|
80164d0: 20008759 .word 0x20008759
|
|
|
|
080164d4 <tcp_route>:
|
|
static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif);
|
|
|
|
/* tcp_route: common code that returns a fixed bound netif or calls ip_route */
|
|
static struct netif *
|
|
tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst)
|
|
{
|
|
80164d4: b580 push {r7, lr}
|
|
80164d6: b084 sub sp, #16
|
|
80164d8: af00 add r7, sp, #0
|
|
80164da: 60f8 str r0, [r7, #12]
|
|
80164dc: 60b9 str r1, [r7, #8]
|
|
80164de: 607a str r2, [r7, #4]
|
|
LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */
|
|
|
|
if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) {
|
|
80164e0: 68fb ldr r3, [r7, #12]
|
|
80164e2: 2b00 cmp r3, #0
|
|
80164e4: d00a beq.n 80164fc <tcp_route+0x28>
|
|
80164e6: 68fb ldr r3, [r7, #12]
|
|
80164e8: 7a1b ldrb r3, [r3, #8]
|
|
80164ea: 2b00 cmp r3, #0
|
|
80164ec: d006 beq.n 80164fc <tcp_route+0x28>
|
|
return netif_get_by_index(pcb->netif_idx);
|
|
80164ee: 68fb ldr r3, [r7, #12]
|
|
80164f0: 7a1b ldrb r3, [r3, #8]
|
|
80164f2: 4618 mov r0, r3
|
|
80164f4: f7fb fb26 bl 8011b44 <netif_get_by_index>
|
|
80164f8: 4603 mov r3, r0
|
|
80164fa: e003 b.n 8016504 <tcp_route+0x30>
|
|
} else {
|
|
return ip_route(src, dst);
|
|
80164fc: 6878 ldr r0, [r7, #4]
|
|
80164fe: f005 f867 bl 801b5d0 <ip4_route>
|
|
8016502: 4603 mov r3, r0
|
|
}
|
|
}
|
|
8016504: 4618 mov r0, r3
|
|
8016506: 3710 adds r7, #16
|
|
8016508: 46bd mov sp, r7
|
|
801650a: bd80 pop {r7, pc}
|
|
|
|
0801650c <tcp_create_segment>:
|
|
* The TCP header is filled in except ackno and wnd.
|
|
* p is freed on failure.
|
|
*/
|
|
static struct tcp_seg *
|
|
tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags)
|
|
{
|
|
801650c: b590 push {r4, r7, lr}
|
|
801650e: b087 sub sp, #28
|
|
8016510: af00 add r7, sp, #0
|
|
8016512: 60f8 str r0, [r7, #12]
|
|
8016514: 60b9 str r1, [r7, #8]
|
|
8016516: 603b str r3, [r7, #0]
|
|
8016518: 4613 mov r3, r2
|
|
801651a: 71fb strb r3, [r7, #7]
|
|
struct tcp_seg *seg;
|
|
u8_t optlen;
|
|
|
|
LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL);
|
|
801651c: 68fb ldr r3, [r7, #12]
|
|
801651e: 2b00 cmp r3, #0
|
|
8016520: d105 bne.n 801652e <tcp_create_segment+0x22>
|
|
8016522: 4b44 ldr r3, [pc, #272] ; (8016634 <tcp_create_segment+0x128>)
|
|
8016524: 22a3 movs r2, #163 ; 0xa3
|
|
8016526: 4944 ldr r1, [pc, #272] ; (8016638 <tcp_create_segment+0x12c>)
|
|
8016528: 4844 ldr r0, [pc, #272] ; (801663c <tcp_create_segment+0x130>)
|
|
801652a: f006 fbc5 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL);
|
|
801652e: 68bb ldr r3, [r7, #8]
|
|
8016530: 2b00 cmp r3, #0
|
|
8016532: d105 bne.n 8016540 <tcp_create_segment+0x34>
|
|
8016534: 4b3f ldr r3, [pc, #252] ; (8016634 <tcp_create_segment+0x128>)
|
|
8016536: 22a4 movs r2, #164 ; 0xa4
|
|
8016538: 4941 ldr r1, [pc, #260] ; (8016640 <tcp_create_segment+0x134>)
|
|
801653a: 4840 ldr r0, [pc, #256] ; (801663c <tcp_create_segment+0x130>)
|
|
801653c: f006 fbbc bl 801ccb8 <iprintf>
|
|
|
|
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
|
|
8016540: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
|
|
8016544: 009b lsls r3, r3, #2
|
|
8016546: b2db uxtb r3, r3
|
|
8016548: f003 0304 and.w r3, r3, #4
|
|
801654c: 75fb strb r3, [r7, #23]
|
|
|
|
if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) {
|
|
801654e: 2003 movs r0, #3
|
|
8016550: f7fa ff84 bl 801145c <memp_malloc>
|
|
8016554: 6138 str r0, [r7, #16]
|
|
8016556: 693b ldr r3, [r7, #16]
|
|
8016558: 2b00 cmp r3, #0
|
|
801655a: d104 bne.n 8016566 <tcp_create_segment+0x5a>
|
|
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n"));
|
|
pbuf_free(p);
|
|
801655c: 68b8 ldr r0, [r7, #8]
|
|
801655e: f7fb fe7b bl 8012258 <pbuf_free>
|
|
return NULL;
|
|
8016562: 2300 movs r3, #0
|
|
8016564: e061 b.n 801662a <tcp_create_segment+0x11e>
|
|
}
|
|
seg->flags = optflags;
|
|
8016566: 693b ldr r3, [r7, #16]
|
|
8016568: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
|
|
801656c: 729a strb r2, [r3, #10]
|
|
seg->next = NULL;
|
|
801656e: 693b ldr r3, [r7, #16]
|
|
8016570: 2200 movs r2, #0
|
|
8016572: 601a str r2, [r3, #0]
|
|
seg->p = p;
|
|
8016574: 693b ldr r3, [r7, #16]
|
|
8016576: 68ba ldr r2, [r7, #8]
|
|
8016578: 605a str r2, [r3, #4]
|
|
LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen);
|
|
801657a: 68bb ldr r3, [r7, #8]
|
|
801657c: 891a ldrh r2, [r3, #8]
|
|
801657e: 7dfb ldrb r3, [r7, #23]
|
|
8016580: b29b uxth r3, r3
|
|
8016582: 429a cmp r2, r3
|
|
8016584: d205 bcs.n 8016592 <tcp_create_segment+0x86>
|
|
8016586: 4b2b ldr r3, [pc, #172] ; (8016634 <tcp_create_segment+0x128>)
|
|
8016588: 22b0 movs r2, #176 ; 0xb0
|
|
801658a: 492e ldr r1, [pc, #184] ; (8016644 <tcp_create_segment+0x138>)
|
|
801658c: 482b ldr r0, [pc, #172] ; (801663c <tcp_create_segment+0x130>)
|
|
801658e: f006 fb93 bl 801ccb8 <iprintf>
|
|
seg->len = p->tot_len - optlen;
|
|
8016592: 68bb ldr r3, [r7, #8]
|
|
8016594: 891a ldrh r2, [r3, #8]
|
|
8016596: 7dfb ldrb r3, [r7, #23]
|
|
8016598: b29b uxth r3, r3
|
|
801659a: 1ad3 subs r3, r2, r3
|
|
801659c: b29a uxth r2, r3
|
|
801659e: 693b ldr r3, [r7, #16]
|
|
80165a0: 811a strh r2, [r3, #8]
|
|
LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED",
|
|
(optflags & TF_SEG_DATA_CHECKSUMMED) == 0);
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
|
|
/* build TCP header */
|
|
if (pbuf_add_header(p, TCP_HLEN)) {
|
|
80165a2: 2114 movs r1, #20
|
|
80165a4: 68b8 ldr r0, [r7, #8]
|
|
80165a6: f7fb fdc1 bl 801212c <pbuf_add_header>
|
|
80165aa: 4603 mov r3, r0
|
|
80165ac: 2b00 cmp r3, #0
|
|
80165ae: d004 beq.n 80165ba <tcp_create_segment+0xae>
|
|
LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n"));
|
|
TCP_STATS_INC(tcp.err);
|
|
tcp_seg_free(seg);
|
|
80165b0: 6938 ldr r0, [r7, #16]
|
|
80165b2: f7fd f8d5 bl 8013760 <tcp_seg_free>
|
|
return NULL;
|
|
80165b6: 2300 movs r3, #0
|
|
80165b8: e037 b.n 801662a <tcp_create_segment+0x11e>
|
|
}
|
|
seg->tcphdr = (struct tcp_hdr *)seg->p->payload;
|
|
80165ba: 693b ldr r3, [r7, #16]
|
|
80165bc: 685b ldr r3, [r3, #4]
|
|
80165be: 685a ldr r2, [r3, #4]
|
|
80165c0: 693b ldr r3, [r7, #16]
|
|
80165c2: 60da str r2, [r3, #12]
|
|
seg->tcphdr->src = lwip_htons(pcb->local_port);
|
|
80165c4: 68fb ldr r3, [r7, #12]
|
|
80165c6: 8ada ldrh r2, [r3, #22]
|
|
80165c8: 693b ldr r3, [r7, #16]
|
|
80165ca: 68dc ldr r4, [r3, #12]
|
|
80165cc: 4610 mov r0, r2
|
|
80165ce: f7fa fa8f bl 8010af0 <lwip_htons>
|
|
80165d2: 4603 mov r3, r0
|
|
80165d4: 8023 strh r3, [r4, #0]
|
|
seg->tcphdr->dest = lwip_htons(pcb->remote_port);
|
|
80165d6: 68fb ldr r3, [r7, #12]
|
|
80165d8: 8b1a ldrh r2, [r3, #24]
|
|
80165da: 693b ldr r3, [r7, #16]
|
|
80165dc: 68dc ldr r4, [r3, #12]
|
|
80165de: 4610 mov r0, r2
|
|
80165e0: f7fa fa86 bl 8010af0 <lwip_htons>
|
|
80165e4: 4603 mov r3, r0
|
|
80165e6: 8063 strh r3, [r4, #2]
|
|
seg->tcphdr->seqno = lwip_htonl(seqno);
|
|
80165e8: 693b ldr r3, [r7, #16]
|
|
80165ea: 68dc ldr r4, [r3, #12]
|
|
80165ec: 6838 ldr r0, [r7, #0]
|
|
80165ee: f7fa fa94 bl 8010b1a <lwip_htonl>
|
|
80165f2: 4603 mov r3, r0
|
|
80165f4: 6063 str r3, [r4, #4]
|
|
/* ackno is set in tcp_output */
|
|
TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags);
|
|
80165f6: 7dfb ldrb r3, [r7, #23]
|
|
80165f8: 089b lsrs r3, r3, #2
|
|
80165fa: b2db uxtb r3, r3
|
|
80165fc: b29b uxth r3, r3
|
|
80165fe: 3305 adds r3, #5
|
|
8016600: b29b uxth r3, r3
|
|
8016602: 031b lsls r3, r3, #12
|
|
8016604: b29a uxth r2, r3
|
|
8016606: 79fb ldrb r3, [r7, #7]
|
|
8016608: b29b uxth r3, r3
|
|
801660a: 4313 orrs r3, r2
|
|
801660c: b29a uxth r2, r3
|
|
801660e: 693b ldr r3, [r7, #16]
|
|
8016610: 68dc ldr r4, [r3, #12]
|
|
8016612: 4610 mov r0, r2
|
|
8016614: f7fa fa6c bl 8010af0 <lwip_htons>
|
|
8016618: 4603 mov r3, r0
|
|
801661a: 81a3 strh r3, [r4, #12]
|
|
/* wnd and chksum are set in tcp_output */
|
|
seg->tcphdr->urgp = 0;
|
|
801661c: 693b ldr r3, [r7, #16]
|
|
801661e: 68db ldr r3, [r3, #12]
|
|
8016620: 2200 movs r2, #0
|
|
8016622: 749a strb r2, [r3, #18]
|
|
8016624: 2200 movs r2, #0
|
|
8016626: 74da strb r2, [r3, #19]
|
|
return seg;
|
|
8016628: 693b ldr r3, [r7, #16]
|
|
}
|
|
801662a: 4618 mov r0, r3
|
|
801662c: 371c adds r7, #28
|
|
801662e: 46bd mov sp, r7
|
|
8016630: bd90 pop {r4, r7, pc}
|
|
8016632: bf00 nop
|
|
8016634: 0801f730 .word 0x0801f730
|
|
8016638: 0801f764 .word 0x0801f764
|
|
801663c: 0801f784 .word 0x0801f784
|
|
8016640: 0801f7ac .word 0x0801f7ac
|
|
8016644: 0801f7d0 .word 0x0801f7d0
|
|
|
|
08016648 <tcp_split_unsent_seg>:
|
|
* @param pcb the tcp_pcb for which to split the unsent head
|
|
* @param split the amount of payload to remain in the head
|
|
*/
|
|
err_t
|
|
tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split)
|
|
{
|
|
8016648: b590 push {r4, r7, lr}
|
|
801664a: b08b sub sp, #44 ; 0x2c
|
|
801664c: af02 add r7, sp, #8
|
|
801664e: 6078 str r0, [r7, #4]
|
|
8016650: 460b mov r3, r1
|
|
8016652: 807b strh r3, [r7, #2]
|
|
struct tcp_seg *seg = NULL, *useg = NULL;
|
|
8016654: 2300 movs r3, #0
|
|
8016656: 61fb str r3, [r7, #28]
|
|
8016658: 2300 movs r3, #0
|
|
801665a: 617b str r3, [r7, #20]
|
|
struct pbuf *p = NULL;
|
|
801665c: 2300 movs r3, #0
|
|
801665e: 613b str r3, [r7, #16]
|
|
u16_t chksum = 0;
|
|
u8_t chksum_swapped = 0;
|
|
struct pbuf *q;
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
|
|
LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL);
|
|
8016660: 687b ldr r3, [r7, #4]
|
|
8016662: 2b00 cmp r3, #0
|
|
8016664: d106 bne.n 8016674 <tcp_split_unsent_seg+0x2c>
|
|
8016666: 4b95 ldr r3, [pc, #596] ; (80168bc <tcp_split_unsent_seg+0x274>)
|
|
8016668: f240 324b movw r2, #843 ; 0x34b
|
|
801666c: 4994 ldr r1, [pc, #592] ; (80168c0 <tcp_split_unsent_seg+0x278>)
|
|
801666e: 4895 ldr r0, [pc, #596] ; (80168c4 <tcp_split_unsent_seg+0x27c>)
|
|
8016670: f006 fb22 bl 801ccb8 <iprintf>
|
|
|
|
useg = pcb->unsent;
|
|
8016674: 687b ldr r3, [r7, #4]
|
|
8016676: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016678: 617b str r3, [r7, #20]
|
|
if (useg == NULL) {
|
|
801667a: 697b ldr r3, [r7, #20]
|
|
801667c: 2b00 cmp r3, #0
|
|
801667e: d102 bne.n 8016686 <tcp_split_unsent_seg+0x3e>
|
|
return ERR_MEM;
|
|
8016680: f04f 33ff mov.w r3, #4294967295
|
|
8016684: e116 b.n 80168b4 <tcp_split_unsent_seg+0x26c>
|
|
}
|
|
|
|
if (split == 0) {
|
|
8016686: 887b ldrh r3, [r7, #2]
|
|
8016688: 2b00 cmp r3, #0
|
|
801668a: d109 bne.n 80166a0 <tcp_split_unsent_seg+0x58>
|
|
LWIP_ASSERT("Can't split segment into length 0", 0);
|
|
801668c: 4b8b ldr r3, [pc, #556] ; (80168bc <tcp_split_unsent_seg+0x274>)
|
|
801668e: f240 3253 movw r2, #851 ; 0x353
|
|
8016692: 498d ldr r1, [pc, #564] ; (80168c8 <tcp_split_unsent_seg+0x280>)
|
|
8016694: 488b ldr r0, [pc, #556] ; (80168c4 <tcp_split_unsent_seg+0x27c>)
|
|
8016696: f006 fb0f bl 801ccb8 <iprintf>
|
|
return ERR_VAL;
|
|
801669a: f06f 0305 mvn.w r3, #5
|
|
801669e: e109 b.n 80168b4 <tcp_split_unsent_seg+0x26c>
|
|
}
|
|
|
|
if (useg->len <= split) {
|
|
80166a0: 697b ldr r3, [r7, #20]
|
|
80166a2: 891b ldrh r3, [r3, #8]
|
|
80166a4: 887a ldrh r2, [r7, #2]
|
|
80166a6: 429a cmp r2, r3
|
|
80166a8: d301 bcc.n 80166ae <tcp_split_unsent_seg+0x66>
|
|
return ERR_OK;
|
|
80166aa: 2300 movs r3, #0
|
|
80166ac: e102 b.n 80168b4 <tcp_split_unsent_seg+0x26c>
|
|
}
|
|
|
|
LWIP_ASSERT("split <= mss", split <= pcb->mss);
|
|
80166ae: 687b ldr r3, [r7, #4]
|
|
80166b0: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
80166b2: 887a ldrh r2, [r7, #2]
|
|
80166b4: 429a cmp r2, r3
|
|
80166b6: d906 bls.n 80166c6 <tcp_split_unsent_seg+0x7e>
|
|
80166b8: 4b80 ldr r3, [pc, #512] ; (80168bc <tcp_split_unsent_seg+0x274>)
|
|
80166ba: f240 325b movw r2, #859 ; 0x35b
|
|
80166be: 4983 ldr r1, [pc, #524] ; (80168cc <tcp_split_unsent_seg+0x284>)
|
|
80166c0: 4880 ldr r0, [pc, #512] ; (80168c4 <tcp_split_unsent_seg+0x27c>)
|
|
80166c2: f006 faf9 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("useg->len > 0", useg->len > 0);
|
|
80166c6: 697b ldr r3, [r7, #20]
|
|
80166c8: 891b ldrh r3, [r3, #8]
|
|
80166ca: 2b00 cmp r3, #0
|
|
80166cc: d106 bne.n 80166dc <tcp_split_unsent_seg+0x94>
|
|
80166ce: 4b7b ldr r3, [pc, #492] ; (80168bc <tcp_split_unsent_seg+0x274>)
|
|
80166d0: f44f 7257 mov.w r2, #860 ; 0x35c
|
|
80166d4: 497e ldr r1, [pc, #504] ; (80168d0 <tcp_split_unsent_seg+0x288>)
|
|
80166d6: 487b ldr r0, [pc, #492] ; (80168c4 <tcp_split_unsent_seg+0x27c>)
|
|
80166d8: f006 faee bl 801ccb8 <iprintf>
|
|
* to split this packet so we may actually exceed the max value by
|
|
* one!
|
|
*/
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen));
|
|
|
|
optflags = useg->flags;
|
|
80166dc: 697b ldr r3, [r7, #20]
|
|
80166de: 7a9b ldrb r3, [r3, #10]
|
|
80166e0: 73fb strb r3, [r7, #15]
|
|
#if TCP_CHECKSUM_ON_COPY
|
|
/* Remove since checksum is not stored until after tcp_create_segment() */
|
|
optflags &= ~TF_SEG_DATA_CHECKSUMMED;
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
optlen = LWIP_TCP_OPT_LENGTH(optflags);
|
|
80166e2: 7bfb ldrb r3, [r7, #15]
|
|
80166e4: 009b lsls r3, r3, #2
|
|
80166e6: b2db uxtb r3, r3
|
|
80166e8: f003 0304 and.w r3, r3, #4
|
|
80166ec: 73bb strb r3, [r7, #14]
|
|
remainder = useg->len - split;
|
|
80166ee: 697b ldr r3, [r7, #20]
|
|
80166f0: 891a ldrh r2, [r3, #8]
|
|
80166f2: 887b ldrh r3, [r7, #2]
|
|
80166f4: 1ad3 subs r3, r2, r3
|
|
80166f6: 81bb strh r3, [r7, #12]
|
|
|
|
/* Create new pbuf for the remainder of the split */
|
|
p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM);
|
|
80166f8: 7bbb ldrb r3, [r7, #14]
|
|
80166fa: b29a uxth r2, r3
|
|
80166fc: 89bb ldrh r3, [r7, #12]
|
|
80166fe: 4413 add r3, r2
|
|
8016700: b29b uxth r3, r3
|
|
8016702: f44f 7220 mov.w r2, #640 ; 0x280
|
|
8016706: 4619 mov r1, r3
|
|
8016708: 2036 movs r0, #54 ; 0x36
|
|
801670a: f7fb fac5 bl 8011c98 <pbuf_alloc>
|
|
801670e: 6138 str r0, [r7, #16]
|
|
if (p == NULL) {
|
|
8016710: 693b ldr r3, [r7, #16]
|
|
8016712: 2b00 cmp r3, #0
|
|
8016714: f000 80b7 beq.w 8016886 <tcp_split_unsent_seg+0x23e>
|
|
("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder));
|
|
goto memerr;
|
|
}
|
|
|
|
/* Offset into the original pbuf is past TCP/IP headers, options, and split amount */
|
|
offset = useg->p->tot_len - useg->len + split;
|
|
8016718: 697b ldr r3, [r7, #20]
|
|
801671a: 685b ldr r3, [r3, #4]
|
|
801671c: 891a ldrh r2, [r3, #8]
|
|
801671e: 697b ldr r3, [r7, #20]
|
|
8016720: 891b ldrh r3, [r3, #8]
|
|
8016722: 1ad3 subs r3, r2, r3
|
|
8016724: b29a uxth r2, r3
|
|
8016726: 887b ldrh r3, [r7, #2]
|
|
8016728: 4413 add r3, r2
|
|
801672a: 817b strh r3, [r7, #10]
|
|
/* Copy remainder into new pbuf, headers and options will not be filled out */
|
|
if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) {
|
|
801672c: 697b ldr r3, [r7, #20]
|
|
801672e: 6858 ldr r0, [r3, #4]
|
|
8016730: 693b ldr r3, [r7, #16]
|
|
8016732: 685a ldr r2, [r3, #4]
|
|
8016734: 7bbb ldrb r3, [r7, #14]
|
|
8016736: 18d1 adds r1, r2, r3
|
|
8016738: 897b ldrh r3, [r7, #10]
|
|
801673a: 89ba ldrh r2, [r7, #12]
|
|
801673c: f7fb ff92 bl 8012664 <pbuf_copy_partial>
|
|
8016740: 4603 mov r3, r0
|
|
8016742: 461a mov r2, r3
|
|
8016744: 89bb ldrh r3, [r7, #12]
|
|
8016746: 4293 cmp r3, r2
|
|
8016748: f040 809f bne.w 801688a <tcp_split_unsent_seg+0x242>
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
|
|
/* Options are created when calling tcp_output() */
|
|
|
|
/* Migrate flags from original segment */
|
|
split_flags = TCPH_FLAGS(useg->tcphdr);
|
|
801674c: 697b ldr r3, [r7, #20]
|
|
801674e: 68db ldr r3, [r3, #12]
|
|
8016750: 899b ldrh r3, [r3, #12]
|
|
8016752: b29b uxth r3, r3
|
|
8016754: 4618 mov r0, r3
|
|
8016756: f7fa f9cb bl 8010af0 <lwip_htons>
|
|
801675a: 4603 mov r3, r0
|
|
801675c: b2db uxtb r3, r3
|
|
801675e: f003 033f and.w r3, r3, #63 ; 0x3f
|
|
8016762: 76fb strb r3, [r7, #27]
|
|
remainder_flags = 0; /* ACK added in tcp_output() */
|
|
8016764: 2300 movs r3, #0
|
|
8016766: 76bb strb r3, [r7, #26]
|
|
|
|
if (split_flags & TCP_PSH) {
|
|
8016768: 7efb ldrb r3, [r7, #27]
|
|
801676a: f003 0308 and.w r3, r3, #8
|
|
801676e: 2b00 cmp r3, #0
|
|
8016770: d007 beq.n 8016782 <tcp_split_unsent_seg+0x13a>
|
|
split_flags &= ~TCP_PSH;
|
|
8016772: 7efb ldrb r3, [r7, #27]
|
|
8016774: f023 0308 bic.w r3, r3, #8
|
|
8016778: 76fb strb r3, [r7, #27]
|
|
remainder_flags |= TCP_PSH;
|
|
801677a: 7ebb ldrb r3, [r7, #26]
|
|
801677c: f043 0308 orr.w r3, r3, #8
|
|
8016780: 76bb strb r3, [r7, #26]
|
|
}
|
|
if (split_flags & TCP_FIN) {
|
|
8016782: 7efb ldrb r3, [r7, #27]
|
|
8016784: f003 0301 and.w r3, r3, #1
|
|
8016788: 2b00 cmp r3, #0
|
|
801678a: d007 beq.n 801679c <tcp_split_unsent_seg+0x154>
|
|
split_flags &= ~TCP_FIN;
|
|
801678c: 7efb ldrb r3, [r7, #27]
|
|
801678e: f023 0301 bic.w r3, r3, #1
|
|
8016792: 76fb strb r3, [r7, #27]
|
|
remainder_flags |= TCP_FIN;
|
|
8016794: 7ebb ldrb r3, [r7, #26]
|
|
8016796: f043 0301 orr.w r3, r3, #1
|
|
801679a: 76bb strb r3, [r7, #26]
|
|
}
|
|
/* SYN should be left on split, RST should not be present with data */
|
|
|
|
seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags);
|
|
801679c: 697b ldr r3, [r7, #20]
|
|
801679e: 68db ldr r3, [r3, #12]
|
|
80167a0: 685b ldr r3, [r3, #4]
|
|
80167a2: 4618 mov r0, r3
|
|
80167a4: f7fa f9b9 bl 8010b1a <lwip_htonl>
|
|
80167a8: 4602 mov r2, r0
|
|
80167aa: 887b ldrh r3, [r7, #2]
|
|
80167ac: 18d1 adds r1, r2, r3
|
|
80167ae: 7eba ldrb r2, [r7, #26]
|
|
80167b0: 7bfb ldrb r3, [r7, #15]
|
|
80167b2: 9300 str r3, [sp, #0]
|
|
80167b4: 460b mov r3, r1
|
|
80167b6: 6939 ldr r1, [r7, #16]
|
|
80167b8: 6878 ldr r0, [r7, #4]
|
|
80167ba: f7ff fea7 bl 801650c <tcp_create_segment>
|
|
80167be: 61f8 str r0, [r7, #28]
|
|
if (seg == NULL) {
|
|
80167c0: 69fb ldr r3, [r7, #28]
|
|
80167c2: 2b00 cmp r3, #0
|
|
80167c4: d063 beq.n 801688e <tcp_split_unsent_seg+0x246>
|
|
seg->chksum_swapped = chksum_swapped;
|
|
seg->flags |= TF_SEG_DATA_CHECKSUMMED;
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
|
|
/* Remove this segment from the queue since trimming it may free pbufs */
|
|
pcb->snd_queuelen -= pbuf_clen(useg->p);
|
|
80167c6: 697b ldr r3, [r7, #20]
|
|
80167c8: 685b ldr r3, [r3, #4]
|
|
80167ca: 4618 mov r0, r3
|
|
80167cc: f7fb fdd2 bl 8012374 <pbuf_clen>
|
|
80167d0: 4603 mov r3, r0
|
|
80167d2: 461a mov r2, r3
|
|
80167d4: 687b ldr r3, [r7, #4]
|
|
80167d6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
80167da: 1a9b subs r3, r3, r2
|
|
80167dc: b29a uxth r2, r3
|
|
80167de: 687b ldr r3, [r7, #4]
|
|
80167e0: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
|
|
/* Trim the original pbuf into our split size. At this point our remainder segment must be setup
|
|
successfully because we are modifying the original segment */
|
|
pbuf_realloc(useg->p, useg->p->tot_len - remainder);
|
|
80167e4: 697b ldr r3, [r7, #20]
|
|
80167e6: 6858 ldr r0, [r3, #4]
|
|
80167e8: 697b ldr r3, [r7, #20]
|
|
80167ea: 685b ldr r3, [r3, #4]
|
|
80167ec: 891a ldrh r2, [r3, #8]
|
|
80167ee: 89bb ldrh r3, [r7, #12]
|
|
80167f0: 1ad3 subs r3, r2, r3
|
|
80167f2: b29b uxth r3, r3
|
|
80167f4: 4619 mov r1, r3
|
|
80167f6: f7fb fba9 bl 8011f4c <pbuf_realloc>
|
|
useg->len -= remainder;
|
|
80167fa: 697b ldr r3, [r7, #20]
|
|
80167fc: 891a ldrh r2, [r3, #8]
|
|
80167fe: 89bb ldrh r3, [r7, #12]
|
|
8016800: 1ad3 subs r3, r2, r3
|
|
8016802: b29a uxth r2, r3
|
|
8016804: 697b ldr r3, [r7, #20]
|
|
8016806: 811a strh r2, [r3, #8]
|
|
TCPH_SET_FLAG(useg->tcphdr, split_flags);
|
|
8016808: 697b ldr r3, [r7, #20]
|
|
801680a: 68db ldr r3, [r3, #12]
|
|
801680c: 899b ldrh r3, [r3, #12]
|
|
801680e: b29c uxth r4, r3
|
|
8016810: 7efb ldrb r3, [r7, #27]
|
|
8016812: b29b uxth r3, r3
|
|
8016814: 4618 mov r0, r3
|
|
8016816: f7fa f96b bl 8010af0 <lwip_htons>
|
|
801681a: 4603 mov r3, r0
|
|
801681c: 461a mov r2, r3
|
|
801681e: 697b ldr r3, [r7, #20]
|
|
8016820: 68db ldr r3, [r3, #12]
|
|
8016822: 4322 orrs r2, r4
|
|
8016824: b292 uxth r2, r2
|
|
8016826: 819a strh r2, [r3, #12]
|
|
/* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */
|
|
useg->oversize_left = 0;
|
|
#endif /* TCP_OVERSIZE_DBGCHECK */
|
|
|
|
/* Add back to the queue with new trimmed pbuf */
|
|
pcb->snd_queuelen += pbuf_clen(useg->p);
|
|
8016828: 697b ldr r3, [r7, #20]
|
|
801682a: 685b ldr r3, [r3, #4]
|
|
801682c: 4618 mov r0, r3
|
|
801682e: f7fb fda1 bl 8012374 <pbuf_clen>
|
|
8016832: 4603 mov r3, r0
|
|
8016834: 461a mov r2, r3
|
|
8016836: 687b ldr r3, [r7, #4]
|
|
8016838: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
801683c: 4413 add r3, r2
|
|
801683e: b29a uxth r2, r3
|
|
8016840: 687b ldr r3, [r7, #4]
|
|
8016842: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
#endif /* TCP_CHECKSUM_ON_COPY */
|
|
|
|
/* Update number of segments on the queues. Note that length now may
|
|
* exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf
|
|
* because the total amount of data is constant when packet is split */
|
|
pcb->snd_queuelen += pbuf_clen(seg->p);
|
|
8016846: 69fb ldr r3, [r7, #28]
|
|
8016848: 685b ldr r3, [r3, #4]
|
|
801684a: 4618 mov r0, r3
|
|
801684c: f7fb fd92 bl 8012374 <pbuf_clen>
|
|
8016850: 4603 mov r3, r0
|
|
8016852: 461a mov r2, r3
|
|
8016854: 687b ldr r3, [r7, #4]
|
|
8016856: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
801685a: 4413 add r3, r2
|
|
801685c: b29a uxth r2, r3
|
|
801685e: 687b ldr r3, [r7, #4]
|
|
8016860: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
|
|
/* Finally insert remainder into queue after split (which stays head) */
|
|
seg->next = useg->next;
|
|
8016864: 697b ldr r3, [r7, #20]
|
|
8016866: 681a ldr r2, [r3, #0]
|
|
8016868: 69fb ldr r3, [r7, #28]
|
|
801686a: 601a str r2, [r3, #0]
|
|
useg->next = seg;
|
|
801686c: 697b ldr r3, [r7, #20]
|
|
801686e: 69fa ldr r2, [r7, #28]
|
|
8016870: 601a str r2, [r3, #0]
|
|
|
|
#if TCP_OVERSIZE
|
|
/* If remainder is last segment on the unsent, ensure we clear the oversize amount
|
|
* because the remainder is always sized to the exact remaining amount */
|
|
if (seg->next == NULL) {
|
|
8016872: 69fb ldr r3, [r7, #28]
|
|
8016874: 681b ldr r3, [r3, #0]
|
|
8016876: 2b00 cmp r3, #0
|
|
8016878: d103 bne.n 8016882 <tcp_split_unsent_seg+0x23a>
|
|
pcb->unsent_oversize = 0;
|
|
801687a: 687b ldr r3, [r7, #4]
|
|
801687c: 2200 movs r2, #0
|
|
801687e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
}
|
|
#endif /* TCP_OVERSIZE */
|
|
|
|
return ERR_OK;
|
|
8016882: 2300 movs r3, #0
|
|
8016884: e016 b.n 80168b4 <tcp_split_unsent_seg+0x26c>
|
|
goto memerr;
|
|
8016886: bf00 nop
|
|
8016888: e002 b.n 8016890 <tcp_split_unsent_seg+0x248>
|
|
goto memerr;
|
|
801688a: bf00 nop
|
|
801688c: e000 b.n 8016890 <tcp_split_unsent_seg+0x248>
|
|
goto memerr;
|
|
801688e: bf00 nop
|
|
memerr:
|
|
TCP_STATS_INC(tcp.memerr);
|
|
|
|
LWIP_ASSERT("seg == NULL", seg == NULL);
|
|
8016890: 69fb ldr r3, [r7, #28]
|
|
8016892: 2b00 cmp r3, #0
|
|
8016894: d006 beq.n 80168a4 <tcp_split_unsent_seg+0x25c>
|
|
8016896: 4b09 ldr r3, [pc, #36] ; (80168bc <tcp_split_unsent_seg+0x274>)
|
|
8016898: f44f 7276 mov.w r2, #984 ; 0x3d8
|
|
801689c: 490d ldr r1, [pc, #52] ; (80168d4 <tcp_split_unsent_seg+0x28c>)
|
|
801689e: 4809 ldr r0, [pc, #36] ; (80168c4 <tcp_split_unsent_seg+0x27c>)
|
|
80168a0: f006 fa0a bl 801ccb8 <iprintf>
|
|
if (p != NULL) {
|
|
80168a4: 693b ldr r3, [r7, #16]
|
|
80168a6: 2b00 cmp r3, #0
|
|
80168a8: d002 beq.n 80168b0 <tcp_split_unsent_seg+0x268>
|
|
pbuf_free(p);
|
|
80168aa: 6938 ldr r0, [r7, #16]
|
|
80168ac: f7fb fcd4 bl 8012258 <pbuf_free>
|
|
}
|
|
|
|
return ERR_MEM;
|
|
80168b0: f04f 33ff mov.w r3, #4294967295
|
|
}
|
|
80168b4: 4618 mov r0, r3
|
|
80168b6: 3724 adds r7, #36 ; 0x24
|
|
80168b8: 46bd mov sp, r7
|
|
80168ba: bd90 pop {r4, r7, pc}
|
|
80168bc: 0801f730 .word 0x0801f730
|
|
80168c0: 0801fac4 .word 0x0801fac4
|
|
80168c4: 0801f784 .word 0x0801f784
|
|
80168c8: 0801fae8 .word 0x0801fae8
|
|
80168cc: 0801fb0c .word 0x0801fb0c
|
|
80168d0: 0801fb1c .word 0x0801fb1c
|
|
80168d4: 0801fb2c .word 0x0801fb2c
|
|
|
|
080168d8 <tcp_send_fin>:
|
|
* @param pcb the tcp_pcb over which to send a segment
|
|
* @return ERR_OK if sent, another err_t otherwise
|
|
*/
|
|
err_t
|
|
tcp_send_fin(struct tcp_pcb *pcb)
|
|
{
|
|
80168d8: b590 push {r4, r7, lr}
|
|
80168da: b085 sub sp, #20
|
|
80168dc: af00 add r7, sp, #0
|
|
80168de: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL);
|
|
80168e0: 687b ldr r3, [r7, #4]
|
|
80168e2: 2b00 cmp r3, #0
|
|
80168e4: d106 bne.n 80168f4 <tcp_send_fin+0x1c>
|
|
80168e6: 4b21 ldr r3, [pc, #132] ; (801696c <tcp_send_fin+0x94>)
|
|
80168e8: f240 32eb movw r2, #1003 ; 0x3eb
|
|
80168ec: 4920 ldr r1, [pc, #128] ; (8016970 <tcp_send_fin+0x98>)
|
|
80168ee: 4821 ldr r0, [pc, #132] ; (8016974 <tcp_send_fin+0x9c>)
|
|
80168f0: f006 f9e2 bl 801ccb8 <iprintf>
|
|
|
|
/* first, try to add the fin to the last unsent segment */
|
|
if (pcb->unsent != NULL) {
|
|
80168f4: 687b ldr r3, [r7, #4]
|
|
80168f6: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
80168f8: 2b00 cmp r3, #0
|
|
80168fa: d02e beq.n 801695a <tcp_send_fin+0x82>
|
|
struct tcp_seg *last_unsent;
|
|
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
|
|
80168fc: 687b ldr r3, [r7, #4]
|
|
80168fe: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016900: 60fb str r3, [r7, #12]
|
|
8016902: e002 b.n 801690a <tcp_send_fin+0x32>
|
|
last_unsent = last_unsent->next);
|
|
8016904: 68fb ldr r3, [r7, #12]
|
|
8016906: 681b ldr r3, [r3, #0]
|
|
8016908: 60fb str r3, [r7, #12]
|
|
for (last_unsent = pcb->unsent; last_unsent->next != NULL;
|
|
801690a: 68fb ldr r3, [r7, #12]
|
|
801690c: 681b ldr r3, [r3, #0]
|
|
801690e: 2b00 cmp r3, #0
|
|
8016910: d1f8 bne.n 8016904 <tcp_send_fin+0x2c>
|
|
|
|
if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) {
|
|
8016912: 68fb ldr r3, [r7, #12]
|
|
8016914: 68db ldr r3, [r3, #12]
|
|
8016916: 899b ldrh r3, [r3, #12]
|
|
8016918: b29b uxth r3, r3
|
|
801691a: 4618 mov r0, r3
|
|
801691c: f7fa f8e8 bl 8010af0 <lwip_htons>
|
|
8016920: 4603 mov r3, r0
|
|
8016922: b2db uxtb r3, r3
|
|
8016924: f003 0307 and.w r3, r3, #7
|
|
8016928: 2b00 cmp r3, #0
|
|
801692a: d116 bne.n 801695a <tcp_send_fin+0x82>
|
|
/* no SYN/FIN/RST flag in the header, we can add the FIN flag */
|
|
TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN);
|
|
801692c: 68fb ldr r3, [r7, #12]
|
|
801692e: 68db ldr r3, [r3, #12]
|
|
8016930: 899b ldrh r3, [r3, #12]
|
|
8016932: b29c uxth r4, r3
|
|
8016934: 2001 movs r0, #1
|
|
8016936: f7fa f8db bl 8010af0 <lwip_htons>
|
|
801693a: 4603 mov r3, r0
|
|
801693c: 461a mov r2, r3
|
|
801693e: 68fb ldr r3, [r7, #12]
|
|
8016940: 68db ldr r3, [r3, #12]
|
|
8016942: 4322 orrs r2, r4
|
|
8016944: b292 uxth r2, r2
|
|
8016946: 819a strh r2, [r3, #12]
|
|
tcp_set_flags(pcb, TF_FIN);
|
|
8016948: 687b ldr r3, [r7, #4]
|
|
801694a: 8b5b ldrh r3, [r3, #26]
|
|
801694c: f043 0320 orr.w r3, r3, #32
|
|
8016950: b29a uxth r2, r3
|
|
8016952: 687b ldr r3, [r7, #4]
|
|
8016954: 835a strh r2, [r3, #26]
|
|
return ERR_OK;
|
|
8016956: 2300 movs r3, #0
|
|
8016958: e004 b.n 8016964 <tcp_send_fin+0x8c>
|
|
}
|
|
}
|
|
/* no data, no length, flags, copy=1, no optdata */
|
|
return tcp_enqueue_flags(pcb, TCP_FIN);
|
|
801695a: 2101 movs r1, #1
|
|
801695c: 6878 ldr r0, [r7, #4]
|
|
801695e: f000 f80b bl 8016978 <tcp_enqueue_flags>
|
|
8016962: 4603 mov r3, r0
|
|
}
|
|
8016964: 4618 mov r0, r3
|
|
8016966: 3714 adds r7, #20
|
|
8016968: 46bd mov sp, r7
|
|
801696a: bd90 pop {r4, r7, pc}
|
|
801696c: 0801f730 .word 0x0801f730
|
|
8016970: 0801fb38 .word 0x0801fb38
|
|
8016974: 0801f784 .word 0x0801f784
|
|
|
|
08016978 <tcp_enqueue_flags>:
|
|
* @param pcb Protocol control block for the TCP connection.
|
|
* @param flags TCP header flags to set in the outgoing segment.
|
|
*/
|
|
err_t
|
|
tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags)
|
|
{
|
|
8016978: b580 push {r7, lr}
|
|
801697a: b08a sub sp, #40 ; 0x28
|
|
801697c: af02 add r7, sp, #8
|
|
801697e: 6078 str r0, [r7, #4]
|
|
8016980: 460b mov r3, r1
|
|
8016982: 70fb strb r3, [r7, #3]
|
|
struct pbuf *p;
|
|
struct tcp_seg *seg;
|
|
u8_t optflags = 0;
|
|
8016984: 2300 movs r3, #0
|
|
8016986: 77fb strb r3, [r7, #31]
|
|
u8_t optlen = 0;
|
|
8016988: 2300 movs r3, #0
|
|
801698a: 75fb strb r3, [r7, #23]
|
|
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen));
|
|
|
|
LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)",
|
|
801698c: 78fb ldrb r3, [r7, #3]
|
|
801698e: f003 0303 and.w r3, r3, #3
|
|
8016992: 2b00 cmp r3, #0
|
|
8016994: d106 bne.n 80169a4 <tcp_enqueue_flags+0x2c>
|
|
8016996: 4b67 ldr r3, [pc, #412] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
8016998: f240 4212 movw r2, #1042 ; 0x412
|
|
801699c: 4966 ldr r1, [pc, #408] ; (8016b38 <tcp_enqueue_flags+0x1c0>)
|
|
801699e: 4867 ldr r0, [pc, #412] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
80169a0: f006 f98a bl 801ccb8 <iprintf>
|
|
(flags & (TCP_SYN | TCP_FIN)) != 0);
|
|
LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL);
|
|
80169a4: 687b ldr r3, [r7, #4]
|
|
80169a6: 2b00 cmp r3, #0
|
|
80169a8: d106 bne.n 80169b8 <tcp_enqueue_flags+0x40>
|
|
80169aa: 4b62 ldr r3, [pc, #392] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
80169ac: f240 4213 movw r2, #1043 ; 0x413
|
|
80169b0: 4963 ldr r1, [pc, #396] ; (8016b40 <tcp_enqueue_flags+0x1c8>)
|
|
80169b2: 4862 ldr r0, [pc, #392] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
80169b4: f006 f980 bl 801ccb8 <iprintf>
|
|
|
|
/* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */
|
|
|
|
/* Get options for this segment. This is a special case since this is the
|
|
only place where a SYN can be sent. */
|
|
if (flags & TCP_SYN) {
|
|
80169b8: 78fb ldrb r3, [r7, #3]
|
|
80169ba: f003 0302 and.w r3, r3, #2
|
|
80169be: 2b00 cmp r3, #0
|
|
80169c0: d001 beq.n 80169c6 <tcp_enqueue_flags+0x4e>
|
|
optflags = TF_SEG_OPTS_MSS;
|
|
80169c2: 2301 movs r3, #1
|
|
80169c4: 77fb strb r3, [r7, #31]
|
|
/* Make sure the timestamp option is only included in data segments if we
|
|
agreed about it with the remote host (and in active open SYN segments). */
|
|
optflags |= TF_SEG_OPTS_TS;
|
|
}
|
|
#endif /* LWIP_TCP_TIMESTAMPS */
|
|
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
|
|
80169c6: 7ffb ldrb r3, [r7, #31]
|
|
80169c8: 009b lsls r3, r3, #2
|
|
80169ca: b2db uxtb r3, r3
|
|
80169cc: f003 0304 and.w r3, r3, #4
|
|
80169d0: 75fb strb r3, [r7, #23]
|
|
|
|
/* Allocate pbuf with room for TCP header + options */
|
|
if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) {
|
|
80169d2: 7dfb ldrb r3, [r7, #23]
|
|
80169d4: b29b uxth r3, r3
|
|
80169d6: f44f 7220 mov.w r2, #640 ; 0x280
|
|
80169da: 4619 mov r1, r3
|
|
80169dc: 2036 movs r0, #54 ; 0x36
|
|
80169de: f7fb f95b bl 8011c98 <pbuf_alloc>
|
|
80169e2: 6138 str r0, [r7, #16]
|
|
80169e4: 693b ldr r3, [r7, #16]
|
|
80169e6: 2b00 cmp r3, #0
|
|
80169e8: d109 bne.n 80169fe <tcp_enqueue_flags+0x86>
|
|
tcp_set_flags(pcb, TF_NAGLEMEMERR);
|
|
80169ea: 687b ldr r3, [r7, #4]
|
|
80169ec: 8b5b ldrh r3, [r3, #26]
|
|
80169ee: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
80169f2: b29a uxth r2, r3
|
|
80169f4: 687b ldr r3, [r7, #4]
|
|
80169f6: 835a strh r2, [r3, #26]
|
|
TCP_STATS_INC(tcp.memerr);
|
|
return ERR_MEM;
|
|
80169f8: f04f 33ff mov.w r3, #4294967295
|
|
80169fc: e095 b.n 8016b2a <tcp_enqueue_flags+0x1b2>
|
|
}
|
|
LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen",
|
|
80169fe: 693b ldr r3, [r7, #16]
|
|
8016a00: 895a ldrh r2, [r3, #10]
|
|
8016a02: 7dfb ldrb r3, [r7, #23]
|
|
8016a04: b29b uxth r3, r3
|
|
8016a06: 429a cmp r2, r3
|
|
8016a08: d206 bcs.n 8016a18 <tcp_enqueue_flags+0xa0>
|
|
8016a0a: 4b4a ldr r3, [pc, #296] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
8016a0c: f240 423a movw r2, #1082 ; 0x43a
|
|
8016a10: 494c ldr r1, [pc, #304] ; (8016b44 <tcp_enqueue_flags+0x1cc>)
|
|
8016a12: 484a ldr r0, [pc, #296] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
8016a14: f006 f950 bl 801ccb8 <iprintf>
|
|
(p->len >= optlen));
|
|
|
|
/* Allocate memory for tcp_seg, and fill in fields. */
|
|
if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) {
|
|
8016a18: 687b ldr r3, [r7, #4]
|
|
8016a1a: 6dd9 ldr r1, [r3, #92] ; 0x5c
|
|
8016a1c: 78fa ldrb r2, [r7, #3]
|
|
8016a1e: 7ffb ldrb r3, [r7, #31]
|
|
8016a20: 9300 str r3, [sp, #0]
|
|
8016a22: 460b mov r3, r1
|
|
8016a24: 6939 ldr r1, [r7, #16]
|
|
8016a26: 6878 ldr r0, [r7, #4]
|
|
8016a28: f7ff fd70 bl 801650c <tcp_create_segment>
|
|
8016a2c: 60f8 str r0, [r7, #12]
|
|
8016a2e: 68fb ldr r3, [r7, #12]
|
|
8016a30: 2b00 cmp r3, #0
|
|
8016a32: d109 bne.n 8016a48 <tcp_enqueue_flags+0xd0>
|
|
tcp_set_flags(pcb, TF_NAGLEMEMERR);
|
|
8016a34: 687b ldr r3, [r7, #4]
|
|
8016a36: 8b5b ldrh r3, [r3, #26]
|
|
8016a38: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8016a3c: b29a uxth r2, r3
|
|
8016a3e: 687b ldr r3, [r7, #4]
|
|
8016a40: 835a strh r2, [r3, #26]
|
|
TCP_STATS_INC(tcp.memerr);
|
|
return ERR_MEM;
|
|
8016a42: f04f 33ff mov.w r3, #4294967295
|
|
8016a46: e070 b.n 8016b2a <tcp_enqueue_flags+0x1b2>
|
|
}
|
|
LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0);
|
|
8016a48: 68fb ldr r3, [r7, #12]
|
|
8016a4a: 68db ldr r3, [r3, #12]
|
|
8016a4c: f003 0303 and.w r3, r3, #3
|
|
8016a50: 2b00 cmp r3, #0
|
|
8016a52: d006 beq.n 8016a62 <tcp_enqueue_flags+0xea>
|
|
8016a54: 4b37 ldr r3, [pc, #220] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
8016a56: f240 4242 movw r2, #1090 ; 0x442
|
|
8016a5a: 493b ldr r1, [pc, #236] ; (8016b48 <tcp_enqueue_flags+0x1d0>)
|
|
8016a5c: 4837 ldr r0, [pc, #220] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
8016a5e: f006 f92b bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0);
|
|
8016a62: 68fb ldr r3, [r7, #12]
|
|
8016a64: 891b ldrh r3, [r3, #8]
|
|
8016a66: 2b00 cmp r3, #0
|
|
8016a68: d006 beq.n 8016a78 <tcp_enqueue_flags+0x100>
|
|
8016a6a: 4b32 ldr r3, [pc, #200] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
8016a6c: f240 4243 movw r2, #1091 ; 0x443
|
|
8016a70: 4936 ldr r1, [pc, #216] ; (8016b4c <tcp_enqueue_flags+0x1d4>)
|
|
8016a72: 4832 ldr r0, [pc, #200] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
8016a74: f006 f920 bl 801ccb8 <iprintf>
|
|
lwip_ntohl(seg->tcphdr->seqno),
|
|
lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg),
|
|
(u16_t)flags));
|
|
|
|
/* Now append seg to pcb->unsent queue */
|
|
if (pcb->unsent == NULL) {
|
|
8016a78: 687b ldr r3, [r7, #4]
|
|
8016a7a: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016a7c: 2b00 cmp r3, #0
|
|
8016a7e: d103 bne.n 8016a88 <tcp_enqueue_flags+0x110>
|
|
pcb->unsent = seg;
|
|
8016a80: 687b ldr r3, [r7, #4]
|
|
8016a82: 68fa ldr r2, [r7, #12]
|
|
8016a84: 66da str r2, [r3, #108] ; 0x6c
|
|
8016a86: e00d b.n 8016aa4 <tcp_enqueue_flags+0x12c>
|
|
} else {
|
|
struct tcp_seg *useg;
|
|
for (useg = pcb->unsent; useg->next != NULL; useg = useg->next);
|
|
8016a88: 687b ldr r3, [r7, #4]
|
|
8016a8a: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016a8c: 61bb str r3, [r7, #24]
|
|
8016a8e: e002 b.n 8016a96 <tcp_enqueue_flags+0x11e>
|
|
8016a90: 69bb ldr r3, [r7, #24]
|
|
8016a92: 681b ldr r3, [r3, #0]
|
|
8016a94: 61bb str r3, [r7, #24]
|
|
8016a96: 69bb ldr r3, [r7, #24]
|
|
8016a98: 681b ldr r3, [r3, #0]
|
|
8016a9a: 2b00 cmp r3, #0
|
|
8016a9c: d1f8 bne.n 8016a90 <tcp_enqueue_flags+0x118>
|
|
useg->next = seg;
|
|
8016a9e: 69bb ldr r3, [r7, #24]
|
|
8016aa0: 68fa ldr r2, [r7, #12]
|
|
8016aa2: 601a str r2, [r3, #0]
|
|
}
|
|
#if TCP_OVERSIZE
|
|
/* The new unsent tail has no space */
|
|
pcb->unsent_oversize = 0;
|
|
8016aa4: 687b ldr r3, [r7, #4]
|
|
8016aa6: 2200 movs r2, #0
|
|
8016aa8: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
#endif /* TCP_OVERSIZE */
|
|
|
|
/* SYN and FIN bump the sequence number */
|
|
if ((flags & TCP_SYN) || (flags & TCP_FIN)) {
|
|
8016aac: 78fb ldrb r3, [r7, #3]
|
|
8016aae: f003 0302 and.w r3, r3, #2
|
|
8016ab2: 2b00 cmp r3, #0
|
|
8016ab4: d104 bne.n 8016ac0 <tcp_enqueue_flags+0x148>
|
|
8016ab6: 78fb ldrb r3, [r7, #3]
|
|
8016ab8: f003 0301 and.w r3, r3, #1
|
|
8016abc: 2b00 cmp r3, #0
|
|
8016abe: d004 beq.n 8016aca <tcp_enqueue_flags+0x152>
|
|
pcb->snd_lbb++;
|
|
8016ac0: 687b ldr r3, [r7, #4]
|
|
8016ac2: 6ddb ldr r3, [r3, #92] ; 0x5c
|
|
8016ac4: 1c5a adds r2, r3, #1
|
|
8016ac6: 687b ldr r3, [r7, #4]
|
|
8016ac8: 65da str r2, [r3, #92] ; 0x5c
|
|
/* optlen does not influence snd_buf */
|
|
}
|
|
if (flags & TCP_FIN) {
|
|
8016aca: 78fb ldrb r3, [r7, #3]
|
|
8016acc: f003 0301 and.w r3, r3, #1
|
|
8016ad0: 2b00 cmp r3, #0
|
|
8016ad2: d006 beq.n 8016ae2 <tcp_enqueue_flags+0x16a>
|
|
tcp_set_flags(pcb, TF_FIN);
|
|
8016ad4: 687b ldr r3, [r7, #4]
|
|
8016ad6: 8b5b ldrh r3, [r3, #26]
|
|
8016ad8: f043 0320 orr.w r3, r3, #32
|
|
8016adc: b29a uxth r2, r3
|
|
8016ade: 687b ldr r3, [r7, #4]
|
|
8016ae0: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
/* update number of segments on the queues */
|
|
pcb->snd_queuelen += pbuf_clen(seg->p);
|
|
8016ae2: 68fb ldr r3, [r7, #12]
|
|
8016ae4: 685b ldr r3, [r3, #4]
|
|
8016ae6: 4618 mov r0, r3
|
|
8016ae8: f7fb fc44 bl 8012374 <pbuf_clen>
|
|
8016aec: 4603 mov r3, r0
|
|
8016aee: 461a mov r2, r3
|
|
8016af0: 687b ldr r3, [r7, #4]
|
|
8016af2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
8016af6: 4413 add r3, r2
|
|
8016af8: b29a uxth r2, r3
|
|
8016afa: 687b ldr r3, [r7, #4]
|
|
8016afc: f8a3 2066 strh.w r2, [r3, #102] ; 0x66
|
|
LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen));
|
|
if (pcb->snd_queuelen != 0) {
|
|
8016b00: 687b ldr r3, [r7, #4]
|
|
8016b02: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
8016b06: 2b00 cmp r3, #0
|
|
8016b08: d00e beq.n 8016b28 <tcp_enqueue_flags+0x1b0>
|
|
LWIP_ASSERT("tcp_enqueue_flags: invalid queue length",
|
|
8016b0a: 687b ldr r3, [r7, #4]
|
|
8016b0c: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8016b0e: 2b00 cmp r3, #0
|
|
8016b10: d10a bne.n 8016b28 <tcp_enqueue_flags+0x1b0>
|
|
8016b12: 687b ldr r3, [r7, #4]
|
|
8016b14: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016b16: 2b00 cmp r3, #0
|
|
8016b18: d106 bne.n 8016b28 <tcp_enqueue_flags+0x1b0>
|
|
8016b1a: 4b06 ldr r3, [pc, #24] ; (8016b34 <tcp_enqueue_flags+0x1bc>)
|
|
8016b1c: f240 4266 movw r2, #1126 ; 0x466
|
|
8016b20: 490b ldr r1, [pc, #44] ; (8016b50 <tcp_enqueue_flags+0x1d8>)
|
|
8016b22: 4806 ldr r0, [pc, #24] ; (8016b3c <tcp_enqueue_flags+0x1c4>)
|
|
8016b24: f006 f8c8 bl 801ccb8 <iprintf>
|
|
pcb->unacked != NULL || pcb->unsent != NULL);
|
|
}
|
|
|
|
return ERR_OK;
|
|
8016b28: 2300 movs r3, #0
|
|
}
|
|
8016b2a: 4618 mov r0, r3
|
|
8016b2c: 3720 adds r7, #32
|
|
8016b2e: 46bd mov sp, r7
|
|
8016b30: bd80 pop {r7, pc}
|
|
8016b32: bf00 nop
|
|
8016b34: 0801f730 .word 0x0801f730
|
|
8016b38: 0801fb54 .word 0x0801fb54
|
|
8016b3c: 0801f784 .word 0x0801f784
|
|
8016b40: 0801fbac .word 0x0801fbac
|
|
8016b44: 0801fbcc .word 0x0801fbcc
|
|
8016b48: 0801fc08 .word 0x0801fc08
|
|
8016b4c: 0801fc20 .word 0x0801fc20
|
|
8016b50: 0801fc4c .word 0x0801fc4c
|
|
|
|
08016b54 <tcp_output>:
|
|
* @return ERR_OK if data has been sent or nothing to send
|
|
* another err_t on error
|
|
*/
|
|
err_t
|
|
tcp_output(struct tcp_pcb *pcb)
|
|
{
|
|
8016b54: b5b0 push {r4, r5, r7, lr}
|
|
8016b56: b08a sub sp, #40 ; 0x28
|
|
8016b58: af00 add r7, sp, #0
|
|
8016b5a: 6078 str r0, [r7, #4]
|
|
s16_t i = 0;
|
|
#endif /* TCP_CWND_DEBUG */
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL);
|
|
8016b5c: 687b ldr r3, [r7, #4]
|
|
8016b5e: 2b00 cmp r3, #0
|
|
8016b60: d106 bne.n 8016b70 <tcp_output+0x1c>
|
|
8016b62: 4ba0 ldr r3, [pc, #640] ; (8016de4 <tcp_output+0x290>)
|
|
8016b64: f240 42e1 movw r2, #1249 ; 0x4e1
|
|
8016b68: 499f ldr r1, [pc, #636] ; (8016de8 <tcp_output+0x294>)
|
|
8016b6a: 48a0 ldr r0, [pc, #640] ; (8016dec <tcp_output+0x298>)
|
|
8016b6c: f006 f8a4 bl 801ccb8 <iprintf>
|
|
/* pcb->state LISTEN not allowed here */
|
|
LWIP_ASSERT("don't call tcp_output for listen-pcbs",
|
|
8016b70: 687b ldr r3, [r7, #4]
|
|
8016b72: 7d1b ldrb r3, [r3, #20]
|
|
8016b74: 2b01 cmp r3, #1
|
|
8016b76: d106 bne.n 8016b86 <tcp_output+0x32>
|
|
8016b78: 4b9a ldr r3, [pc, #616] ; (8016de4 <tcp_output+0x290>)
|
|
8016b7a: f240 42e4 movw r2, #1252 ; 0x4e4
|
|
8016b7e: 499c ldr r1, [pc, #624] ; (8016df0 <tcp_output+0x29c>)
|
|
8016b80: 489a ldr r0, [pc, #616] ; (8016dec <tcp_output+0x298>)
|
|
8016b82: f006 f899 bl 801ccb8 <iprintf>
|
|
|
|
/* First, check if we are invoked by the TCP input processing
|
|
code. If so, we do not output anything. Instead, we rely on the
|
|
input processing code to call us when input processing is done
|
|
with. */
|
|
if (tcp_input_pcb == pcb) {
|
|
8016b86: 4b9b ldr r3, [pc, #620] ; (8016df4 <tcp_output+0x2a0>)
|
|
8016b88: 681b ldr r3, [r3, #0]
|
|
8016b8a: 687a ldr r2, [r7, #4]
|
|
8016b8c: 429a cmp r2, r3
|
|
8016b8e: d101 bne.n 8016b94 <tcp_output+0x40>
|
|
return ERR_OK;
|
|
8016b90: 2300 movs r3, #0
|
|
8016b92: e1d2 b.n 8016f3a <tcp_output+0x3e6>
|
|
}
|
|
|
|
wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd);
|
|
8016b94: 687b ldr r3, [r7, #4]
|
|
8016b96: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60
|
|
8016b9a: 687b ldr r3, [r7, #4]
|
|
8016b9c: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8016ba0: 429a cmp r2, r3
|
|
8016ba2: d203 bcs.n 8016bac <tcp_output+0x58>
|
|
8016ba4: 687b ldr r3, [r7, #4]
|
|
8016ba6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
8016baa: e002 b.n 8016bb2 <tcp_output+0x5e>
|
|
8016bac: 687b ldr r3, [r7, #4]
|
|
8016bae: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
8016bb2: 61bb str r3, [r7, #24]
|
|
|
|
seg = pcb->unsent;
|
|
8016bb4: 687b ldr r3, [r7, #4]
|
|
8016bb6: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016bb8: 627b str r3, [r7, #36] ; 0x24
|
|
|
|
if (seg == NULL) {
|
|
8016bba: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016bbc: 2b00 cmp r3, #0
|
|
8016bbe: d10b bne.n 8016bd8 <tcp_output+0x84>
|
|
", seg == NULL, ack %"U32_F"\n",
|
|
pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack));
|
|
|
|
/* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct
|
|
* an empty ACK segment and send it. */
|
|
if (pcb->flags & TF_ACK_NOW) {
|
|
8016bc0: 687b ldr r3, [r7, #4]
|
|
8016bc2: 8b5b ldrh r3, [r3, #26]
|
|
8016bc4: f003 0302 and.w r3, r3, #2
|
|
8016bc8: 2b00 cmp r3, #0
|
|
8016bca: f000 81a9 beq.w 8016f20 <tcp_output+0x3cc>
|
|
return tcp_send_empty_ack(pcb);
|
|
8016bce: 6878 ldr r0, [r7, #4]
|
|
8016bd0: f000 fdd8 bl 8017784 <tcp_send_empty_ack>
|
|
8016bd4: 4603 mov r3, r0
|
|
8016bd6: e1b0 b.n 8016f3a <tcp_output+0x3e6>
|
|
pcb->snd_wnd, pcb->cwnd, wnd,
|
|
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len,
|
|
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack));
|
|
}
|
|
|
|
netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip);
|
|
8016bd8: 6879 ldr r1, [r7, #4]
|
|
8016bda: 687b ldr r3, [r7, #4]
|
|
8016bdc: 3304 adds r3, #4
|
|
8016bde: 461a mov r2, r3
|
|
8016be0: 6878 ldr r0, [r7, #4]
|
|
8016be2: f7ff fc77 bl 80164d4 <tcp_route>
|
|
8016be6: 6178 str r0, [r7, #20]
|
|
if (netif == NULL) {
|
|
8016be8: 697b ldr r3, [r7, #20]
|
|
8016bea: 2b00 cmp r3, #0
|
|
8016bec: d102 bne.n 8016bf4 <tcp_output+0xa0>
|
|
return ERR_RTE;
|
|
8016bee: f06f 0303 mvn.w r3, #3
|
|
8016bf2: e1a2 b.n 8016f3a <tcp_output+0x3e6>
|
|
}
|
|
|
|
/* If we don't have a local IP address, we get one from netif */
|
|
if (ip_addr_isany(&pcb->local_ip)) {
|
|
8016bf4: 687b ldr r3, [r7, #4]
|
|
8016bf6: 2b00 cmp r3, #0
|
|
8016bf8: d003 beq.n 8016c02 <tcp_output+0xae>
|
|
8016bfa: 687b ldr r3, [r7, #4]
|
|
8016bfc: 681b ldr r3, [r3, #0]
|
|
8016bfe: 2b00 cmp r3, #0
|
|
8016c00: d111 bne.n 8016c26 <tcp_output+0xd2>
|
|
const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip);
|
|
8016c02: 697b ldr r3, [r7, #20]
|
|
8016c04: 2b00 cmp r3, #0
|
|
8016c06: d002 beq.n 8016c0e <tcp_output+0xba>
|
|
8016c08: 697b ldr r3, [r7, #20]
|
|
8016c0a: 3304 adds r3, #4
|
|
8016c0c: e000 b.n 8016c10 <tcp_output+0xbc>
|
|
8016c0e: 2300 movs r3, #0
|
|
8016c10: 613b str r3, [r7, #16]
|
|
if (local_ip == NULL) {
|
|
8016c12: 693b ldr r3, [r7, #16]
|
|
8016c14: 2b00 cmp r3, #0
|
|
8016c16: d102 bne.n 8016c1e <tcp_output+0xca>
|
|
return ERR_RTE;
|
|
8016c18: f06f 0303 mvn.w r3, #3
|
|
8016c1c: e18d b.n 8016f3a <tcp_output+0x3e6>
|
|
}
|
|
ip_addr_copy(pcb->local_ip, *local_ip);
|
|
8016c1e: 693b ldr r3, [r7, #16]
|
|
8016c20: 681a ldr r2, [r3, #0]
|
|
8016c22: 687b ldr r3, [r7, #4]
|
|
8016c24: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Handle the current segment not fitting within the window */
|
|
if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) {
|
|
8016c26: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016c28: 68db ldr r3, [r3, #12]
|
|
8016c2a: 685b ldr r3, [r3, #4]
|
|
8016c2c: 4618 mov r0, r3
|
|
8016c2e: f7f9 ff74 bl 8010b1a <lwip_htonl>
|
|
8016c32: 4602 mov r2, r0
|
|
8016c34: 687b ldr r3, [r7, #4]
|
|
8016c36: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8016c38: 1ad3 subs r3, r2, r3
|
|
8016c3a: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8016c3c: 8912 ldrh r2, [r2, #8]
|
|
8016c3e: 4413 add r3, r2
|
|
8016c40: 69ba ldr r2, [r7, #24]
|
|
8016c42: 429a cmp r2, r3
|
|
8016c44: d227 bcs.n 8016c96 <tcp_output+0x142>
|
|
* within the remaining (could be 0) send window and RTO timer is not running (we
|
|
* have no in-flight data). If window is still too small after persist timer fires,
|
|
* then we split the segment. We don't consider the congestion window since a cwnd
|
|
* smaller than 1 SMSS implies in-flight data
|
|
*/
|
|
if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) {
|
|
8016c46: 687b ldr r3, [r7, #4]
|
|
8016c48: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
8016c4c: 461a mov r2, r3
|
|
8016c4e: 69bb ldr r3, [r7, #24]
|
|
8016c50: 4293 cmp r3, r2
|
|
8016c52: d114 bne.n 8016c7e <tcp_output+0x12a>
|
|
8016c54: 687b ldr r3, [r7, #4]
|
|
8016c56: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8016c58: 2b00 cmp r3, #0
|
|
8016c5a: d110 bne.n 8016c7e <tcp_output+0x12a>
|
|
8016c5c: 687b ldr r3, [r7, #4]
|
|
8016c5e: f893 3099 ldrb.w r3, [r3, #153] ; 0x99
|
|
8016c62: 2b00 cmp r3, #0
|
|
8016c64: d10b bne.n 8016c7e <tcp_output+0x12a>
|
|
pcb->persist_cnt = 0;
|
|
8016c66: 687b ldr r3, [r7, #4]
|
|
8016c68: 2200 movs r2, #0
|
|
8016c6a: f883 2098 strb.w r2, [r3, #152] ; 0x98
|
|
pcb->persist_backoff = 1;
|
|
8016c6e: 687b ldr r3, [r7, #4]
|
|
8016c70: 2201 movs r2, #1
|
|
8016c72: f883 2099 strb.w r2, [r3, #153] ; 0x99
|
|
pcb->persist_probe = 0;
|
|
8016c76: 687b ldr r3, [r7, #4]
|
|
8016c78: 2200 movs r2, #0
|
|
8016c7a: f883 209a strb.w r2, [r3, #154] ; 0x9a
|
|
}
|
|
/* We need an ACK, but can't send data now, so send an empty ACK */
|
|
if (pcb->flags & TF_ACK_NOW) {
|
|
8016c7e: 687b ldr r3, [r7, #4]
|
|
8016c80: 8b5b ldrh r3, [r3, #26]
|
|
8016c82: f003 0302 and.w r3, r3, #2
|
|
8016c86: 2b00 cmp r3, #0
|
|
8016c88: f000 814c beq.w 8016f24 <tcp_output+0x3d0>
|
|
return tcp_send_empty_ack(pcb);
|
|
8016c8c: 6878 ldr r0, [r7, #4]
|
|
8016c8e: f000 fd79 bl 8017784 <tcp_send_empty_ack>
|
|
8016c92: 4603 mov r3, r0
|
|
8016c94: e151 b.n 8016f3a <tcp_output+0x3e6>
|
|
}
|
|
goto output_done;
|
|
}
|
|
/* Stop persist timer, above conditions are not active */
|
|
pcb->persist_backoff = 0;
|
|
8016c96: 687b ldr r3, [r7, #4]
|
|
8016c98: 2200 movs r2, #0
|
|
8016c9a: f883 2099 strb.w r2, [r3, #153] ; 0x99
|
|
|
|
/* useg should point to last segment on unacked queue */
|
|
useg = pcb->unacked;
|
|
8016c9e: 687b ldr r3, [r7, #4]
|
|
8016ca0: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8016ca2: 623b str r3, [r7, #32]
|
|
if (useg != NULL) {
|
|
8016ca4: 6a3b ldr r3, [r7, #32]
|
|
8016ca6: 2b00 cmp r3, #0
|
|
8016ca8: f000 811b beq.w 8016ee2 <tcp_output+0x38e>
|
|
for (; useg->next != NULL; useg = useg->next);
|
|
8016cac: e002 b.n 8016cb4 <tcp_output+0x160>
|
|
8016cae: 6a3b ldr r3, [r7, #32]
|
|
8016cb0: 681b ldr r3, [r3, #0]
|
|
8016cb2: 623b str r3, [r7, #32]
|
|
8016cb4: 6a3b ldr r3, [r7, #32]
|
|
8016cb6: 681b ldr r3, [r3, #0]
|
|
8016cb8: 2b00 cmp r3, #0
|
|
8016cba: d1f8 bne.n 8016cae <tcp_output+0x15a>
|
|
}
|
|
/* data available and window allows it to be sent? */
|
|
while (seg != NULL &&
|
|
8016cbc: e111 b.n 8016ee2 <tcp_output+0x38e>
|
|
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
|
|
LWIP_ASSERT("RST not expected here!",
|
|
8016cbe: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016cc0: 68db ldr r3, [r3, #12]
|
|
8016cc2: 899b ldrh r3, [r3, #12]
|
|
8016cc4: b29b uxth r3, r3
|
|
8016cc6: 4618 mov r0, r3
|
|
8016cc8: f7f9 ff12 bl 8010af0 <lwip_htons>
|
|
8016ccc: 4603 mov r3, r0
|
|
8016cce: b2db uxtb r3, r3
|
|
8016cd0: f003 0304 and.w r3, r3, #4
|
|
8016cd4: 2b00 cmp r3, #0
|
|
8016cd6: d006 beq.n 8016ce6 <tcp_output+0x192>
|
|
8016cd8: 4b42 ldr r3, [pc, #264] ; (8016de4 <tcp_output+0x290>)
|
|
8016cda: f240 5237 movw r2, #1335 ; 0x537
|
|
8016cde: 4946 ldr r1, [pc, #280] ; (8016df8 <tcp_output+0x2a4>)
|
|
8016ce0: 4842 ldr r0, [pc, #264] ; (8016dec <tcp_output+0x298>)
|
|
8016ce2: f005 ffe9 bl 801ccb8 <iprintf>
|
|
* - if tcp_write had a memory error before (prevent delayed ACK timeout) or
|
|
* - if FIN was already enqueued for this PCB (SYN is always alone in a segment -
|
|
* either seg->next != NULL or pcb->unacked == NULL;
|
|
* RST is no sent using tcp_write/tcp_output.
|
|
*/
|
|
if ((tcp_do_output_nagle(pcb) == 0) &&
|
|
8016ce6: 687b ldr r3, [r7, #4]
|
|
8016ce8: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8016cea: 2b00 cmp r3, #0
|
|
8016cec: d01f beq.n 8016d2e <tcp_output+0x1da>
|
|
8016cee: 687b ldr r3, [r7, #4]
|
|
8016cf0: 8b5b ldrh r3, [r3, #26]
|
|
8016cf2: f003 0344 and.w r3, r3, #68 ; 0x44
|
|
8016cf6: 2b00 cmp r3, #0
|
|
8016cf8: d119 bne.n 8016d2e <tcp_output+0x1da>
|
|
8016cfa: 687b ldr r3, [r7, #4]
|
|
8016cfc: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016cfe: 2b00 cmp r3, #0
|
|
8016d00: d00b beq.n 8016d1a <tcp_output+0x1c6>
|
|
8016d02: 687b ldr r3, [r7, #4]
|
|
8016d04: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016d06: 681b ldr r3, [r3, #0]
|
|
8016d08: 2b00 cmp r3, #0
|
|
8016d0a: d110 bne.n 8016d2e <tcp_output+0x1da>
|
|
8016d0c: 687b ldr r3, [r7, #4]
|
|
8016d0e: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016d10: 891a ldrh r2, [r3, #8]
|
|
8016d12: 687b ldr r3, [r7, #4]
|
|
8016d14: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8016d16: 429a cmp r2, r3
|
|
8016d18: d209 bcs.n 8016d2e <tcp_output+0x1da>
|
|
8016d1a: 687b ldr r3, [r7, #4]
|
|
8016d1c: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64
|
|
8016d20: 2b00 cmp r3, #0
|
|
8016d22: d004 beq.n 8016d2e <tcp_output+0x1da>
|
|
8016d24: 687b ldr r3, [r7, #4]
|
|
8016d26: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66
|
|
8016d2a: 2b08 cmp r3, #8
|
|
8016d2c: d901 bls.n 8016d32 <tcp_output+0x1de>
|
|
8016d2e: 2301 movs r3, #1
|
|
8016d30: e000 b.n 8016d34 <tcp_output+0x1e0>
|
|
8016d32: 2300 movs r3, #0
|
|
8016d34: 2b00 cmp r3, #0
|
|
8016d36: d106 bne.n 8016d46 <tcp_output+0x1f2>
|
|
((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) {
|
|
8016d38: 687b ldr r3, [r7, #4]
|
|
8016d3a: 8b5b ldrh r3, [r3, #26]
|
|
8016d3c: f003 03a0 and.w r3, r3, #160 ; 0xa0
|
|
if ((tcp_do_output_nagle(pcb) == 0) &&
|
|
8016d40: 2b00 cmp r3, #0
|
|
8016d42: f000 80e3 beq.w 8016f0c <tcp_output+0x3b8>
|
|
pcb->lastack,
|
|
lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i));
|
|
++i;
|
|
#endif /* TCP_CWND_DEBUG */
|
|
|
|
if (pcb->state != SYN_SENT) {
|
|
8016d46: 687b ldr r3, [r7, #4]
|
|
8016d48: 7d1b ldrb r3, [r3, #20]
|
|
8016d4a: 2b02 cmp r3, #2
|
|
8016d4c: d00d beq.n 8016d6a <tcp_output+0x216>
|
|
TCPH_SET_FLAG(seg->tcphdr, TCP_ACK);
|
|
8016d4e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016d50: 68db ldr r3, [r3, #12]
|
|
8016d52: 899b ldrh r3, [r3, #12]
|
|
8016d54: b29c uxth r4, r3
|
|
8016d56: 2010 movs r0, #16
|
|
8016d58: f7f9 feca bl 8010af0 <lwip_htons>
|
|
8016d5c: 4603 mov r3, r0
|
|
8016d5e: 461a mov r2, r3
|
|
8016d60: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016d62: 68db ldr r3, [r3, #12]
|
|
8016d64: 4322 orrs r2, r4
|
|
8016d66: b292 uxth r2, r2
|
|
8016d68: 819a strh r2, [r3, #12]
|
|
}
|
|
|
|
err = tcp_output_segment(seg, pcb, netif);
|
|
8016d6a: 697a ldr r2, [r7, #20]
|
|
8016d6c: 6879 ldr r1, [r7, #4]
|
|
8016d6e: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
8016d70: f000 f908 bl 8016f84 <tcp_output_segment>
|
|
8016d74: 4603 mov r3, r0
|
|
8016d76: 73fb strb r3, [r7, #15]
|
|
if (err != ERR_OK) {
|
|
8016d78: f997 300f ldrsb.w r3, [r7, #15]
|
|
8016d7c: 2b00 cmp r3, #0
|
|
8016d7e: d009 beq.n 8016d94 <tcp_output+0x240>
|
|
/* segment could not be sent, for whatever reason */
|
|
tcp_set_flags(pcb, TF_NAGLEMEMERR);
|
|
8016d80: 687b ldr r3, [r7, #4]
|
|
8016d82: 8b5b ldrh r3, [r3, #26]
|
|
8016d84: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
8016d88: b29a uxth r2, r3
|
|
8016d8a: 687b ldr r3, [r7, #4]
|
|
8016d8c: 835a strh r2, [r3, #26]
|
|
return err;
|
|
8016d8e: f997 300f ldrsb.w r3, [r7, #15]
|
|
8016d92: e0d2 b.n 8016f3a <tcp_output+0x3e6>
|
|
}
|
|
#if TCP_OVERSIZE_DBGCHECK
|
|
seg->oversize_left = 0;
|
|
#endif /* TCP_OVERSIZE_DBGCHECK */
|
|
pcb->unsent = seg->next;
|
|
8016d94: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016d96: 681a ldr r2, [r3, #0]
|
|
8016d98: 687b ldr r3, [r7, #4]
|
|
8016d9a: 66da str r2, [r3, #108] ; 0x6c
|
|
if (pcb->state != SYN_SENT) {
|
|
8016d9c: 687b ldr r3, [r7, #4]
|
|
8016d9e: 7d1b ldrb r3, [r3, #20]
|
|
8016da0: 2b02 cmp r3, #2
|
|
8016da2: d006 beq.n 8016db2 <tcp_output+0x25e>
|
|
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
|
|
8016da4: 687b ldr r3, [r7, #4]
|
|
8016da6: 8b5b ldrh r3, [r3, #26]
|
|
8016da8: f023 0303 bic.w r3, r3, #3
|
|
8016dac: b29a uxth r2, r3
|
|
8016dae: 687b ldr r3, [r7, #4]
|
|
8016db0: 835a strh r2, [r3, #26]
|
|
}
|
|
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
|
|
8016db2: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016db4: 68db ldr r3, [r3, #12]
|
|
8016db6: 685b ldr r3, [r3, #4]
|
|
8016db8: 4618 mov r0, r3
|
|
8016dba: f7f9 feae bl 8010b1a <lwip_htonl>
|
|
8016dbe: 4604 mov r4, r0
|
|
8016dc0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016dc2: 891b ldrh r3, [r3, #8]
|
|
8016dc4: 461d mov r5, r3
|
|
8016dc6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016dc8: 68db ldr r3, [r3, #12]
|
|
8016dca: 899b ldrh r3, [r3, #12]
|
|
8016dcc: b29b uxth r3, r3
|
|
8016dce: 4618 mov r0, r3
|
|
8016dd0: f7f9 fe8e bl 8010af0 <lwip_htons>
|
|
8016dd4: 4603 mov r3, r0
|
|
8016dd6: b2db uxtb r3, r3
|
|
8016dd8: f003 0303 and.w r3, r3, #3
|
|
8016ddc: 2b00 cmp r3, #0
|
|
8016dde: d00d beq.n 8016dfc <tcp_output+0x2a8>
|
|
8016de0: 2301 movs r3, #1
|
|
8016de2: e00c b.n 8016dfe <tcp_output+0x2aa>
|
|
8016de4: 0801f730 .word 0x0801f730
|
|
8016de8: 0801fc74 .word 0x0801fc74
|
|
8016dec: 0801f784 .word 0x0801f784
|
|
8016df0: 0801fc8c .word 0x0801fc8c
|
|
8016df4: 2000f810 .word 0x2000f810
|
|
8016df8: 0801fcb4 .word 0x0801fcb4
|
|
8016dfc: 2300 movs r3, #0
|
|
8016dfe: 442b add r3, r5
|
|
8016e00: 4423 add r3, r4
|
|
8016e02: 60bb str r3, [r7, #8]
|
|
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
|
|
8016e04: 687b ldr r3, [r7, #4]
|
|
8016e06: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
8016e08: 68bb ldr r3, [r7, #8]
|
|
8016e0a: 1ad3 subs r3, r2, r3
|
|
8016e0c: 2b00 cmp r3, #0
|
|
8016e0e: da02 bge.n 8016e16 <tcp_output+0x2c2>
|
|
pcb->snd_nxt = snd_nxt;
|
|
8016e10: 687b ldr r3, [r7, #4]
|
|
8016e12: 68ba ldr r2, [r7, #8]
|
|
8016e14: 651a str r2, [r3, #80] ; 0x50
|
|
}
|
|
/* put segment on unacknowledged list if length > 0 */
|
|
if (TCP_TCPLEN(seg) > 0) {
|
|
8016e16: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016e18: 891b ldrh r3, [r3, #8]
|
|
8016e1a: 461c mov r4, r3
|
|
8016e1c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016e1e: 68db ldr r3, [r3, #12]
|
|
8016e20: 899b ldrh r3, [r3, #12]
|
|
8016e22: b29b uxth r3, r3
|
|
8016e24: 4618 mov r0, r3
|
|
8016e26: f7f9 fe63 bl 8010af0 <lwip_htons>
|
|
8016e2a: 4603 mov r3, r0
|
|
8016e2c: b2db uxtb r3, r3
|
|
8016e2e: f003 0303 and.w r3, r3, #3
|
|
8016e32: 2b00 cmp r3, #0
|
|
8016e34: d001 beq.n 8016e3a <tcp_output+0x2e6>
|
|
8016e36: 2301 movs r3, #1
|
|
8016e38: e000 b.n 8016e3c <tcp_output+0x2e8>
|
|
8016e3a: 2300 movs r3, #0
|
|
8016e3c: 4423 add r3, r4
|
|
8016e3e: 2b00 cmp r3, #0
|
|
8016e40: d049 beq.n 8016ed6 <tcp_output+0x382>
|
|
seg->next = NULL;
|
|
8016e42: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016e44: 2200 movs r2, #0
|
|
8016e46: 601a str r2, [r3, #0]
|
|
/* unacked list is empty? */
|
|
if (pcb->unacked == NULL) {
|
|
8016e48: 687b ldr r3, [r7, #4]
|
|
8016e4a: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8016e4c: 2b00 cmp r3, #0
|
|
8016e4e: d105 bne.n 8016e5c <tcp_output+0x308>
|
|
pcb->unacked = seg;
|
|
8016e50: 687b ldr r3, [r7, #4]
|
|
8016e52: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8016e54: 671a str r2, [r3, #112] ; 0x70
|
|
useg = seg;
|
|
8016e56: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016e58: 623b str r3, [r7, #32]
|
|
8016e5a: e03f b.n 8016edc <tcp_output+0x388>
|
|
/* unacked list is not empty? */
|
|
} else {
|
|
/* In the case of fast retransmit, the packet should not go to the tail
|
|
* of the unacked queue, but rather somewhere before it. We need to check for
|
|
* this case. -STJ Jul 27, 2004 */
|
|
if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) {
|
|
8016e5c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016e5e: 68db ldr r3, [r3, #12]
|
|
8016e60: 685b ldr r3, [r3, #4]
|
|
8016e62: 4618 mov r0, r3
|
|
8016e64: f7f9 fe59 bl 8010b1a <lwip_htonl>
|
|
8016e68: 4604 mov r4, r0
|
|
8016e6a: 6a3b ldr r3, [r7, #32]
|
|
8016e6c: 68db ldr r3, [r3, #12]
|
|
8016e6e: 685b ldr r3, [r3, #4]
|
|
8016e70: 4618 mov r0, r3
|
|
8016e72: f7f9 fe52 bl 8010b1a <lwip_htonl>
|
|
8016e76: 4603 mov r3, r0
|
|
8016e78: 1ae3 subs r3, r4, r3
|
|
8016e7a: 2b00 cmp r3, #0
|
|
8016e7c: da24 bge.n 8016ec8 <tcp_output+0x374>
|
|
/* add segment to before tail of unacked list, keeping the list sorted */
|
|
struct tcp_seg **cur_seg = &(pcb->unacked);
|
|
8016e7e: 687b ldr r3, [r7, #4]
|
|
8016e80: 3370 adds r3, #112 ; 0x70
|
|
8016e82: 61fb str r3, [r7, #28]
|
|
while (*cur_seg &&
|
|
8016e84: e002 b.n 8016e8c <tcp_output+0x338>
|
|
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
|
|
cur_seg = &((*cur_seg)->next );
|
|
8016e86: 69fb ldr r3, [r7, #28]
|
|
8016e88: 681b ldr r3, [r3, #0]
|
|
8016e8a: 61fb str r3, [r7, #28]
|
|
while (*cur_seg &&
|
|
8016e8c: 69fb ldr r3, [r7, #28]
|
|
8016e8e: 681b ldr r3, [r3, #0]
|
|
8016e90: 2b00 cmp r3, #0
|
|
8016e92: d011 beq.n 8016eb8 <tcp_output+0x364>
|
|
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
|
|
8016e94: 69fb ldr r3, [r7, #28]
|
|
8016e96: 681b ldr r3, [r3, #0]
|
|
8016e98: 68db ldr r3, [r3, #12]
|
|
8016e9a: 685b ldr r3, [r3, #4]
|
|
8016e9c: 4618 mov r0, r3
|
|
8016e9e: f7f9 fe3c bl 8010b1a <lwip_htonl>
|
|
8016ea2: 4604 mov r4, r0
|
|
8016ea4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016ea6: 68db ldr r3, [r3, #12]
|
|
8016ea8: 685b ldr r3, [r3, #4]
|
|
8016eaa: 4618 mov r0, r3
|
|
8016eac: f7f9 fe35 bl 8010b1a <lwip_htonl>
|
|
8016eb0: 4603 mov r3, r0
|
|
8016eb2: 1ae3 subs r3, r4, r3
|
|
while (*cur_seg &&
|
|
8016eb4: 2b00 cmp r3, #0
|
|
8016eb6: dbe6 blt.n 8016e86 <tcp_output+0x332>
|
|
}
|
|
seg->next = (*cur_seg);
|
|
8016eb8: 69fb ldr r3, [r7, #28]
|
|
8016eba: 681a ldr r2, [r3, #0]
|
|
8016ebc: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016ebe: 601a str r2, [r3, #0]
|
|
(*cur_seg) = seg;
|
|
8016ec0: 69fb ldr r3, [r7, #28]
|
|
8016ec2: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8016ec4: 601a str r2, [r3, #0]
|
|
8016ec6: e009 b.n 8016edc <tcp_output+0x388>
|
|
} else {
|
|
/* add segment to tail of unacked list */
|
|
useg->next = seg;
|
|
8016ec8: 6a3b ldr r3, [r7, #32]
|
|
8016eca: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8016ecc: 601a str r2, [r3, #0]
|
|
useg = useg->next;
|
|
8016ece: 6a3b ldr r3, [r7, #32]
|
|
8016ed0: 681b ldr r3, [r3, #0]
|
|
8016ed2: 623b str r3, [r7, #32]
|
|
8016ed4: e002 b.n 8016edc <tcp_output+0x388>
|
|
}
|
|
}
|
|
/* do not queue empty segments on the unacked list */
|
|
} else {
|
|
tcp_seg_free(seg);
|
|
8016ed6: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
8016ed8: f7fc fc42 bl 8013760 <tcp_seg_free>
|
|
}
|
|
seg = pcb->unsent;
|
|
8016edc: 687b ldr r3, [r7, #4]
|
|
8016ede: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016ee0: 627b str r3, [r7, #36] ; 0x24
|
|
while (seg != NULL &&
|
|
8016ee2: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016ee4: 2b00 cmp r3, #0
|
|
8016ee6: d012 beq.n 8016f0e <tcp_output+0x3ba>
|
|
lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) {
|
|
8016ee8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8016eea: 68db ldr r3, [r3, #12]
|
|
8016eec: 685b ldr r3, [r3, #4]
|
|
8016eee: 4618 mov r0, r3
|
|
8016ef0: f7f9 fe13 bl 8010b1a <lwip_htonl>
|
|
8016ef4: 4602 mov r2, r0
|
|
8016ef6: 687b ldr r3, [r7, #4]
|
|
8016ef8: 6c5b ldr r3, [r3, #68] ; 0x44
|
|
8016efa: 1ad3 subs r3, r2, r3
|
|
8016efc: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
8016efe: 8912 ldrh r2, [r2, #8]
|
|
8016f00: 4413 add r3, r2
|
|
while (seg != NULL &&
|
|
8016f02: 69ba ldr r2, [r7, #24]
|
|
8016f04: 429a cmp r2, r3
|
|
8016f06: f4bf aeda bcs.w 8016cbe <tcp_output+0x16a>
|
|
8016f0a: e000 b.n 8016f0e <tcp_output+0x3ba>
|
|
break;
|
|
8016f0c: bf00 nop
|
|
}
|
|
#if TCP_OVERSIZE
|
|
if (pcb->unsent == NULL) {
|
|
8016f0e: 687b ldr r3, [r7, #4]
|
|
8016f10: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
8016f12: 2b00 cmp r3, #0
|
|
8016f14: d108 bne.n 8016f28 <tcp_output+0x3d4>
|
|
/* last unsent has been removed, reset unsent_oversize */
|
|
pcb->unsent_oversize = 0;
|
|
8016f16: 687b ldr r3, [r7, #4]
|
|
8016f18: 2200 movs r2, #0
|
|
8016f1a: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
8016f1e: e004 b.n 8016f2a <tcp_output+0x3d6>
|
|
goto output_done;
|
|
8016f20: bf00 nop
|
|
8016f22: e002 b.n 8016f2a <tcp_output+0x3d6>
|
|
goto output_done;
|
|
8016f24: bf00 nop
|
|
8016f26: e000 b.n 8016f2a <tcp_output+0x3d6>
|
|
}
|
|
#endif /* TCP_OVERSIZE */
|
|
|
|
output_done:
|
|
8016f28: bf00 nop
|
|
tcp_clear_flags(pcb, TF_NAGLEMEMERR);
|
|
8016f2a: 687b ldr r3, [r7, #4]
|
|
8016f2c: 8b5b ldrh r3, [r3, #26]
|
|
8016f2e: f023 0380 bic.w r3, r3, #128 ; 0x80
|
|
8016f32: b29a uxth r2, r3
|
|
8016f34: 687b ldr r3, [r7, #4]
|
|
8016f36: 835a strh r2, [r3, #26]
|
|
return ERR_OK;
|
|
8016f38: 2300 movs r3, #0
|
|
}
|
|
8016f3a: 4618 mov r0, r3
|
|
8016f3c: 3728 adds r7, #40 ; 0x28
|
|
8016f3e: 46bd mov sp, r7
|
|
8016f40: bdb0 pop {r4, r5, r7, pc}
|
|
8016f42: bf00 nop
|
|
|
|
08016f44 <tcp_output_segment_busy>:
|
|
* @arg seg the tcp segment to check
|
|
* @return 1 if ref != 1, 0 if ref == 1
|
|
*/
|
|
static int
|
|
tcp_output_segment_busy(const struct tcp_seg *seg)
|
|
{
|
|
8016f44: b580 push {r7, lr}
|
|
8016f46: b082 sub sp, #8
|
|
8016f48: af00 add r7, sp, #0
|
|
8016f4a: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL);
|
|
8016f4c: 687b ldr r3, [r7, #4]
|
|
8016f4e: 2b00 cmp r3, #0
|
|
8016f50: d106 bne.n 8016f60 <tcp_output_segment_busy+0x1c>
|
|
8016f52: 4b09 ldr r3, [pc, #36] ; (8016f78 <tcp_output_segment_busy+0x34>)
|
|
8016f54: f240 529a movw r2, #1434 ; 0x59a
|
|
8016f58: 4908 ldr r1, [pc, #32] ; (8016f7c <tcp_output_segment_busy+0x38>)
|
|
8016f5a: 4809 ldr r0, [pc, #36] ; (8016f80 <tcp_output_segment_busy+0x3c>)
|
|
8016f5c: f005 feac bl 801ccb8 <iprintf>
|
|
|
|
/* We only need to check the first pbuf here:
|
|
If a pbuf is queued for transmission, a driver calls pbuf_ref(),
|
|
which only changes the ref count of the first pbuf */
|
|
if (seg->p->ref != 1) {
|
|
8016f60: 687b ldr r3, [r7, #4]
|
|
8016f62: 685b ldr r3, [r3, #4]
|
|
8016f64: 7b9b ldrb r3, [r3, #14]
|
|
8016f66: 2b01 cmp r3, #1
|
|
8016f68: d001 beq.n 8016f6e <tcp_output_segment_busy+0x2a>
|
|
/* other reference found */
|
|
return 1;
|
|
8016f6a: 2301 movs r3, #1
|
|
8016f6c: e000 b.n 8016f70 <tcp_output_segment_busy+0x2c>
|
|
}
|
|
/* no other references found */
|
|
return 0;
|
|
8016f6e: 2300 movs r3, #0
|
|
}
|
|
8016f70: 4618 mov r0, r3
|
|
8016f72: 3708 adds r7, #8
|
|
8016f74: 46bd mov sp, r7
|
|
8016f76: bd80 pop {r7, pc}
|
|
8016f78: 0801f730 .word 0x0801f730
|
|
8016f7c: 0801fccc .word 0x0801fccc
|
|
8016f80: 0801f784 .word 0x0801f784
|
|
|
|
08016f84 <tcp_output_segment>:
|
|
* @param pcb the tcp_pcb for the TCP connection used to send the segment
|
|
* @param netif the netif used to send the segment
|
|
*/
|
|
static err_t
|
|
tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif)
|
|
{
|
|
8016f84: b5b0 push {r4, r5, r7, lr}
|
|
8016f86: b08c sub sp, #48 ; 0x30
|
|
8016f88: af04 add r7, sp, #16
|
|
8016f8a: 60f8 str r0, [r7, #12]
|
|
8016f8c: 60b9 str r1, [r7, #8]
|
|
8016f8e: 607a str r2, [r7, #4]
|
|
u32_t *opts;
|
|
#if TCP_CHECKSUM_ON_COPY
|
|
int seg_chksum_was_swapped = 0;
|
|
#endif
|
|
|
|
LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL);
|
|
8016f90: 68fb ldr r3, [r7, #12]
|
|
8016f92: 2b00 cmp r3, #0
|
|
8016f94: d106 bne.n 8016fa4 <tcp_output_segment+0x20>
|
|
8016f96: 4b64 ldr r3, [pc, #400] ; (8017128 <tcp_output_segment+0x1a4>)
|
|
8016f98: f44f 62b7 mov.w r2, #1464 ; 0x5b8
|
|
8016f9c: 4963 ldr r1, [pc, #396] ; (801712c <tcp_output_segment+0x1a8>)
|
|
8016f9e: 4864 ldr r0, [pc, #400] ; (8017130 <tcp_output_segment+0x1ac>)
|
|
8016fa0: f005 fe8a bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL);
|
|
8016fa4: 68bb ldr r3, [r7, #8]
|
|
8016fa6: 2b00 cmp r3, #0
|
|
8016fa8: d106 bne.n 8016fb8 <tcp_output_segment+0x34>
|
|
8016faa: 4b5f ldr r3, [pc, #380] ; (8017128 <tcp_output_segment+0x1a4>)
|
|
8016fac: f240 52b9 movw r2, #1465 ; 0x5b9
|
|
8016fb0: 4960 ldr r1, [pc, #384] ; (8017134 <tcp_output_segment+0x1b0>)
|
|
8016fb2: 485f ldr r0, [pc, #380] ; (8017130 <tcp_output_segment+0x1ac>)
|
|
8016fb4: f005 fe80 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL);
|
|
8016fb8: 687b ldr r3, [r7, #4]
|
|
8016fba: 2b00 cmp r3, #0
|
|
8016fbc: d106 bne.n 8016fcc <tcp_output_segment+0x48>
|
|
8016fbe: 4b5a ldr r3, [pc, #360] ; (8017128 <tcp_output_segment+0x1a4>)
|
|
8016fc0: f240 52ba movw r2, #1466 ; 0x5ba
|
|
8016fc4: 495c ldr r1, [pc, #368] ; (8017138 <tcp_output_segment+0x1b4>)
|
|
8016fc6: 485a ldr r0, [pc, #360] ; (8017130 <tcp_output_segment+0x1ac>)
|
|
8016fc8: f005 fe76 bl 801ccb8 <iprintf>
|
|
|
|
if (tcp_output_segment_busy(seg)) {
|
|
8016fcc: 68f8 ldr r0, [r7, #12]
|
|
8016fce: f7ff ffb9 bl 8016f44 <tcp_output_segment_busy>
|
|
8016fd2: 4603 mov r3, r0
|
|
8016fd4: 2b00 cmp r3, #0
|
|
8016fd6: d001 beq.n 8016fdc <tcp_output_segment+0x58>
|
|
/* This should not happen: rexmit functions should have checked this.
|
|
However, since this function modifies p->len, we must not continue in this case. */
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n"));
|
|
return ERR_OK;
|
|
8016fd8: 2300 movs r3, #0
|
|
8016fda: e0a0 b.n 801711e <tcp_output_segment+0x19a>
|
|
}
|
|
|
|
/* The TCP header has already been constructed, but the ackno and
|
|
wnd fields remain. */
|
|
seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt);
|
|
8016fdc: 68bb ldr r3, [r7, #8]
|
|
8016fde: 6a5a ldr r2, [r3, #36] ; 0x24
|
|
8016fe0: 68fb ldr r3, [r7, #12]
|
|
8016fe2: 68dc ldr r4, [r3, #12]
|
|
8016fe4: 4610 mov r0, r2
|
|
8016fe6: f7f9 fd98 bl 8010b1a <lwip_htonl>
|
|
8016fea: 4603 mov r3, r0
|
|
8016fec: 60a3 str r3, [r4, #8]
|
|
the window scale option) is never scaled. */
|
|
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd));
|
|
} else
|
|
#endif /* LWIP_WND_SCALE */
|
|
{
|
|
seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
|
|
8016fee: 68bb ldr r3, [r7, #8]
|
|
8016ff0: 8d5a ldrh r2, [r3, #42] ; 0x2a
|
|
8016ff2: 68fb ldr r3, [r7, #12]
|
|
8016ff4: 68dc ldr r4, [r3, #12]
|
|
8016ff6: 4610 mov r0, r2
|
|
8016ff8: f7f9 fd7a bl 8010af0 <lwip_htons>
|
|
8016ffc: 4603 mov r3, r0
|
|
8016ffe: 81e3 strh r3, [r4, #14]
|
|
}
|
|
|
|
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
|
|
8017000: 68bb ldr r3, [r7, #8]
|
|
8017002: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8017004: 68ba ldr r2, [r7, #8]
|
|
8017006: 8d52 ldrh r2, [r2, #42] ; 0x2a
|
|
8017008: 441a add r2, r3
|
|
801700a: 68bb ldr r3, [r7, #8]
|
|
801700c: 62da str r2, [r3, #44] ; 0x2c
|
|
|
|
/* Add any requested options. NB MSS option is only set on SYN
|
|
packets, so ignore it here */
|
|
/* cast through void* to get rid of alignment warnings */
|
|
opts = (u32_t *)(void *)(seg->tcphdr + 1);
|
|
801700e: 68fb ldr r3, [r7, #12]
|
|
8017010: 68db ldr r3, [r3, #12]
|
|
8017012: 3314 adds r3, #20
|
|
8017014: 61fb str r3, [r7, #28]
|
|
if (seg->flags & TF_SEG_OPTS_MSS) {
|
|
8017016: 68fb ldr r3, [r7, #12]
|
|
8017018: 7a9b ldrb r3, [r3, #10]
|
|
801701a: f003 0301 and.w r3, r3, #1
|
|
801701e: 2b00 cmp r3, #0
|
|
8017020: d015 beq.n 801704e <tcp_output_segment+0xca>
|
|
u16_t mss;
|
|
#if TCP_CALCULATE_EFF_SEND_MSS
|
|
mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip);
|
|
8017022: 68bb ldr r3, [r7, #8]
|
|
8017024: 3304 adds r3, #4
|
|
8017026: 461a mov r2, r3
|
|
8017028: 6879 ldr r1, [r7, #4]
|
|
801702a: f44f 7006 mov.w r0, #536 ; 0x218
|
|
801702e: f7fc fe8d bl 8013d4c <tcp_eff_send_mss_netif>
|
|
8017032: 4603 mov r3, r0
|
|
8017034: 837b strh r3, [r7, #26]
|
|
#else /* TCP_CALCULATE_EFF_SEND_MSS */
|
|
mss = TCP_MSS;
|
|
#endif /* TCP_CALCULATE_EFF_SEND_MSS */
|
|
*opts = TCP_BUILD_MSS_OPTION(mss);
|
|
8017036: 8b7b ldrh r3, [r7, #26]
|
|
8017038: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000
|
|
801703c: 4618 mov r0, r3
|
|
801703e: f7f9 fd6c bl 8010b1a <lwip_htonl>
|
|
8017042: 4602 mov r2, r0
|
|
8017044: 69fb ldr r3, [r7, #28]
|
|
8017046: 601a str r2, [r3, #0]
|
|
opts += 1;
|
|
8017048: 69fb ldr r3, [r7, #28]
|
|
801704a: 3304 adds r3, #4
|
|
801704c: 61fb str r3, [r7, #28]
|
|
}
|
|
#endif
|
|
|
|
/* Set retransmission timer running if it is not currently enabled
|
|
This must be set before checking the route. */
|
|
if (pcb->rtime < 0) {
|
|
801704e: 68bb ldr r3, [r7, #8]
|
|
8017050: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30
|
|
8017054: 2b00 cmp r3, #0
|
|
8017056: da02 bge.n 801705e <tcp_output_segment+0xda>
|
|
pcb->rtime = 0;
|
|
8017058: 68bb ldr r3, [r7, #8]
|
|
801705a: 2200 movs r2, #0
|
|
801705c: 861a strh r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
if (pcb->rttest == 0) {
|
|
801705e: 68bb ldr r3, [r7, #8]
|
|
8017060: 6b5b ldr r3, [r3, #52] ; 0x34
|
|
8017062: 2b00 cmp r3, #0
|
|
8017064: d10c bne.n 8017080 <tcp_output_segment+0xfc>
|
|
pcb->rttest = tcp_ticks;
|
|
8017066: 4b35 ldr r3, [pc, #212] ; (801713c <tcp_output_segment+0x1b8>)
|
|
8017068: 681a ldr r2, [r3, #0]
|
|
801706a: 68bb ldr r3, [r7, #8]
|
|
801706c: 635a str r2, [r3, #52] ; 0x34
|
|
pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno);
|
|
801706e: 68fb ldr r3, [r7, #12]
|
|
8017070: 68db ldr r3, [r3, #12]
|
|
8017072: 685b ldr r3, [r3, #4]
|
|
8017074: 4618 mov r0, r3
|
|
8017076: f7f9 fd50 bl 8010b1a <lwip_htonl>
|
|
801707a: 4602 mov r2, r0
|
|
801707c: 68bb ldr r3, [r7, #8]
|
|
801707e: 639a str r2, [r3, #56] ; 0x38
|
|
}
|
|
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n",
|
|
lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) +
|
|
seg->len));
|
|
|
|
len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload);
|
|
8017080: 68fb ldr r3, [r7, #12]
|
|
8017082: 68db ldr r3, [r3, #12]
|
|
8017084: 461a mov r2, r3
|
|
8017086: 68fb ldr r3, [r7, #12]
|
|
8017088: 685b ldr r3, [r3, #4]
|
|
801708a: 685b ldr r3, [r3, #4]
|
|
801708c: 1ad3 subs r3, r2, r3
|
|
801708e: 833b strh r3, [r7, #24]
|
|
if (len == 0) {
|
|
/** Exclude retransmitted segments from this count. */
|
|
MIB2_STATS_INC(mib2.tcpoutsegs);
|
|
}
|
|
|
|
seg->p->len -= len;
|
|
8017090: 68fb ldr r3, [r7, #12]
|
|
8017092: 685b ldr r3, [r3, #4]
|
|
8017094: 8959 ldrh r1, [r3, #10]
|
|
8017096: 68fb ldr r3, [r7, #12]
|
|
8017098: 685b ldr r3, [r3, #4]
|
|
801709a: 8b3a ldrh r2, [r7, #24]
|
|
801709c: 1a8a subs r2, r1, r2
|
|
801709e: b292 uxth r2, r2
|
|
80170a0: 815a strh r2, [r3, #10]
|
|
seg->p->tot_len -= len;
|
|
80170a2: 68fb ldr r3, [r7, #12]
|
|
80170a4: 685b ldr r3, [r3, #4]
|
|
80170a6: 8919 ldrh r1, [r3, #8]
|
|
80170a8: 68fb ldr r3, [r7, #12]
|
|
80170aa: 685b ldr r3, [r3, #4]
|
|
80170ac: 8b3a ldrh r2, [r7, #24]
|
|
80170ae: 1a8a subs r2, r1, r2
|
|
80170b0: b292 uxth r2, r2
|
|
80170b2: 811a strh r2, [r3, #8]
|
|
|
|
seg->p->payload = seg->tcphdr;
|
|
80170b4: 68fb ldr r3, [r7, #12]
|
|
80170b6: 685b ldr r3, [r3, #4]
|
|
80170b8: 68fa ldr r2, [r7, #12]
|
|
80170ba: 68d2 ldr r2, [r2, #12]
|
|
80170bc: 605a str r2, [r3, #4]
|
|
|
|
seg->tcphdr->chksum = 0;
|
|
80170be: 68fb ldr r3, [r7, #12]
|
|
80170c0: 68db ldr r3, [r3, #12]
|
|
80170c2: 2200 movs r2, #0
|
|
80170c4: 741a strb r2, [r3, #16]
|
|
80170c6: 2200 movs r2, #0
|
|
80170c8: 745a strb r2, [r3, #17]
|
|
|
|
#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS
|
|
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts);
|
|
#endif
|
|
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb));
|
|
80170ca: 68fb ldr r3, [r7, #12]
|
|
80170cc: 68db ldr r3, [r3, #12]
|
|
80170ce: f103 0214 add.w r2, r3, #20
|
|
80170d2: 68fb ldr r3, [r7, #12]
|
|
80170d4: 7a9b ldrb r3, [r3, #10]
|
|
80170d6: 009b lsls r3, r3, #2
|
|
80170d8: f003 0304 and.w r3, r3, #4
|
|
80170dc: 4413 add r3, r2
|
|
80170de: 69fa ldr r2, [r7, #28]
|
|
80170e0: 429a cmp r2, r3
|
|
80170e2: d006 beq.n 80170f2 <tcp_output_segment+0x16e>
|
|
80170e4: 4b10 ldr r3, [pc, #64] ; (8017128 <tcp_output_segment+0x1a4>)
|
|
80170e6: f240 621c movw r2, #1564 ; 0x61c
|
|
80170ea: 4915 ldr r1, [pc, #84] ; (8017140 <tcp_output_segment+0x1bc>)
|
|
80170ec: 4810 ldr r0, [pc, #64] ; (8017130 <tcp_output_segment+0x1ac>)
|
|
80170ee: f005 fde3 bl 801ccb8 <iprintf>
|
|
}
|
|
#endif /* CHECKSUM_GEN_TCP */
|
|
TCP_STATS_INC(tcp.xmit);
|
|
|
|
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
|
|
err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl,
|
|
80170f2: 68fb ldr r3, [r7, #12]
|
|
80170f4: 6858 ldr r0, [r3, #4]
|
|
80170f6: 68b9 ldr r1, [r7, #8]
|
|
80170f8: 68bb ldr r3, [r7, #8]
|
|
80170fa: 1d1c adds r4, r3, #4
|
|
80170fc: 68bb ldr r3, [r7, #8]
|
|
80170fe: 7add ldrb r5, [r3, #11]
|
|
8017100: 68bb ldr r3, [r7, #8]
|
|
8017102: 7a9b ldrb r3, [r3, #10]
|
|
8017104: 687a ldr r2, [r7, #4]
|
|
8017106: 9202 str r2, [sp, #8]
|
|
8017108: 2206 movs r2, #6
|
|
801710a: 9201 str r2, [sp, #4]
|
|
801710c: 9300 str r3, [sp, #0]
|
|
801710e: 462b mov r3, r5
|
|
8017110: 4622 mov r2, r4
|
|
8017112: f004 fc37 bl 801b984 <ip4_output_if>
|
|
8017116: 4603 mov r3, r0
|
|
8017118: 75fb strb r3, [r7, #23]
|
|
seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum);
|
|
seg->chksum_swapped = 1;
|
|
}
|
|
#endif
|
|
|
|
return err;
|
|
801711a: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
801711e: 4618 mov r0, r3
|
|
8017120: 3720 adds r7, #32
|
|
8017122: 46bd mov sp, r7
|
|
8017124: bdb0 pop {r4, r5, r7, pc}
|
|
8017126: bf00 nop
|
|
8017128: 0801f730 .word 0x0801f730
|
|
801712c: 0801fcf4 .word 0x0801fcf4
|
|
8017130: 0801f784 .word 0x0801f784
|
|
8017134: 0801fd14 .word 0x0801fd14
|
|
8017138: 0801fd34 .word 0x0801fd34
|
|
801713c: 2000f800 .word 0x2000f800
|
|
8017140: 0801fd58 .word 0x0801fd58
|
|
|
|
08017144 <tcp_rexmit_rto_prepare>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
|
|
*/
|
|
err_t
|
|
tcp_rexmit_rto_prepare(struct tcp_pcb *pcb)
|
|
{
|
|
8017144: b5b0 push {r4, r5, r7, lr}
|
|
8017146: b084 sub sp, #16
|
|
8017148: af00 add r7, sp, #0
|
|
801714a: 6078 str r0, [r7, #4]
|
|
struct tcp_seg *seg;
|
|
|
|
LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL);
|
|
801714c: 687b ldr r3, [r7, #4]
|
|
801714e: 2b00 cmp r3, #0
|
|
8017150: d106 bne.n 8017160 <tcp_rexmit_rto_prepare+0x1c>
|
|
8017152: 4b31 ldr r3, [pc, #196] ; (8017218 <tcp_rexmit_rto_prepare+0xd4>)
|
|
8017154: f240 6263 movw r2, #1635 ; 0x663
|
|
8017158: 4930 ldr r1, [pc, #192] ; (801721c <tcp_rexmit_rto_prepare+0xd8>)
|
|
801715a: 4831 ldr r0, [pc, #196] ; (8017220 <tcp_rexmit_rto_prepare+0xdc>)
|
|
801715c: f005 fdac bl 801ccb8 <iprintf>
|
|
|
|
if (pcb->unacked == NULL) {
|
|
8017160: 687b ldr r3, [r7, #4]
|
|
8017162: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8017164: 2b00 cmp r3, #0
|
|
8017166: d102 bne.n 801716e <tcp_rexmit_rto_prepare+0x2a>
|
|
return ERR_VAL;
|
|
8017168: f06f 0305 mvn.w r3, #5
|
|
801716c: e050 b.n 8017210 <tcp_rexmit_rto_prepare+0xcc>
|
|
|
|
/* Move all unacked segments to the head of the unsent queue.
|
|
However, give up if any of the unsent pbufs are still referenced by the
|
|
netif driver due to deferred transmission. No point loading the link further
|
|
if it is struggling to flush its buffered writes. */
|
|
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
|
|
801716e: 687b ldr r3, [r7, #4]
|
|
8017170: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
8017172: 60fb str r3, [r7, #12]
|
|
8017174: e00b b.n 801718e <tcp_rexmit_rto_prepare+0x4a>
|
|
if (tcp_output_segment_busy(seg)) {
|
|
8017176: 68f8 ldr r0, [r7, #12]
|
|
8017178: f7ff fee4 bl 8016f44 <tcp_output_segment_busy>
|
|
801717c: 4603 mov r3, r0
|
|
801717e: 2b00 cmp r3, #0
|
|
8017180: d002 beq.n 8017188 <tcp_rexmit_rto_prepare+0x44>
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
|
|
return ERR_VAL;
|
|
8017182: f06f 0305 mvn.w r3, #5
|
|
8017186: e043 b.n 8017210 <tcp_rexmit_rto_prepare+0xcc>
|
|
for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) {
|
|
8017188: 68fb ldr r3, [r7, #12]
|
|
801718a: 681b ldr r3, [r3, #0]
|
|
801718c: 60fb str r3, [r7, #12]
|
|
801718e: 68fb ldr r3, [r7, #12]
|
|
8017190: 681b ldr r3, [r3, #0]
|
|
8017192: 2b00 cmp r3, #0
|
|
8017194: d1ef bne.n 8017176 <tcp_rexmit_rto_prepare+0x32>
|
|
}
|
|
}
|
|
if (tcp_output_segment_busy(seg)) {
|
|
8017196: 68f8 ldr r0, [r7, #12]
|
|
8017198: f7ff fed4 bl 8016f44 <tcp_output_segment_busy>
|
|
801719c: 4603 mov r3, r0
|
|
801719e: 2b00 cmp r3, #0
|
|
80171a0: d002 beq.n 80171a8 <tcp_rexmit_rto_prepare+0x64>
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n"));
|
|
return ERR_VAL;
|
|
80171a2: f06f 0305 mvn.w r3, #5
|
|
80171a6: e033 b.n 8017210 <tcp_rexmit_rto_prepare+0xcc>
|
|
}
|
|
/* concatenate unsent queue after unacked queue */
|
|
seg->next = pcb->unsent;
|
|
80171a8: 687b ldr r3, [r7, #4]
|
|
80171aa: 6eda ldr r2, [r3, #108] ; 0x6c
|
|
80171ac: 68fb ldr r3, [r7, #12]
|
|
80171ae: 601a str r2, [r3, #0]
|
|
if (pcb->unsent == NULL) {
|
|
pcb->unsent_oversize = seg->oversize_left;
|
|
}
|
|
#endif /* TCP_OVERSIZE_DBGCHECK */
|
|
/* unsent queue is the concatenated queue (of unacked, unsent) */
|
|
pcb->unsent = pcb->unacked;
|
|
80171b0: 687b ldr r3, [r7, #4]
|
|
80171b2: 6f1a ldr r2, [r3, #112] ; 0x70
|
|
80171b4: 687b ldr r3, [r7, #4]
|
|
80171b6: 66da str r2, [r3, #108] ; 0x6c
|
|
/* unacked queue is now empty */
|
|
pcb->unacked = NULL;
|
|
80171b8: 687b ldr r3, [r7, #4]
|
|
80171ba: 2200 movs r2, #0
|
|
80171bc: 671a str r2, [r3, #112] ; 0x70
|
|
|
|
/* Mark RTO in-progress */
|
|
tcp_set_flags(pcb, TF_RTO);
|
|
80171be: 687b ldr r3, [r7, #4]
|
|
80171c0: 8b5b ldrh r3, [r3, #26]
|
|
80171c2: f443 6300 orr.w r3, r3, #2048 ; 0x800
|
|
80171c6: b29a uxth r2, r3
|
|
80171c8: 687b ldr r3, [r7, #4]
|
|
80171ca: 835a strh r2, [r3, #26]
|
|
/* Record the next byte following retransmit */
|
|
pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg);
|
|
80171cc: 68fb ldr r3, [r7, #12]
|
|
80171ce: 68db ldr r3, [r3, #12]
|
|
80171d0: 685b ldr r3, [r3, #4]
|
|
80171d2: 4618 mov r0, r3
|
|
80171d4: f7f9 fca1 bl 8010b1a <lwip_htonl>
|
|
80171d8: 4604 mov r4, r0
|
|
80171da: 68fb ldr r3, [r7, #12]
|
|
80171dc: 891b ldrh r3, [r3, #8]
|
|
80171de: 461d mov r5, r3
|
|
80171e0: 68fb ldr r3, [r7, #12]
|
|
80171e2: 68db ldr r3, [r3, #12]
|
|
80171e4: 899b ldrh r3, [r3, #12]
|
|
80171e6: b29b uxth r3, r3
|
|
80171e8: 4618 mov r0, r3
|
|
80171ea: f7f9 fc81 bl 8010af0 <lwip_htons>
|
|
80171ee: 4603 mov r3, r0
|
|
80171f0: b2db uxtb r3, r3
|
|
80171f2: f003 0303 and.w r3, r3, #3
|
|
80171f6: 2b00 cmp r3, #0
|
|
80171f8: d001 beq.n 80171fe <tcp_rexmit_rto_prepare+0xba>
|
|
80171fa: 2301 movs r3, #1
|
|
80171fc: e000 b.n 8017200 <tcp_rexmit_rto_prepare+0xbc>
|
|
80171fe: 2300 movs r3, #0
|
|
8017200: 442b add r3, r5
|
|
8017202: 18e2 adds r2, r4, r3
|
|
8017204: 687b ldr r3, [r7, #4]
|
|
8017206: 64da str r2, [r3, #76] ; 0x4c
|
|
/* Don't take any RTT measurements after retransmitting. */
|
|
pcb->rttest = 0;
|
|
8017208: 687b ldr r3, [r7, #4]
|
|
801720a: 2200 movs r2, #0
|
|
801720c: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
return ERR_OK;
|
|
801720e: 2300 movs r3, #0
|
|
}
|
|
8017210: 4618 mov r0, r3
|
|
8017212: 3710 adds r7, #16
|
|
8017214: 46bd mov sp, r7
|
|
8017216: bdb0 pop {r4, r5, r7, pc}
|
|
8017218: 0801f730 .word 0x0801f730
|
|
801721c: 0801fd6c .word 0x0801fd6c
|
|
8017220: 0801f784 .word 0x0801f784
|
|
|
|
08017224 <tcp_rexmit_rto_commit>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
|
|
*/
|
|
void
|
|
tcp_rexmit_rto_commit(struct tcp_pcb *pcb)
|
|
{
|
|
8017224: b580 push {r7, lr}
|
|
8017226: b082 sub sp, #8
|
|
8017228: af00 add r7, sp, #0
|
|
801722a: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL);
|
|
801722c: 687b ldr r3, [r7, #4]
|
|
801722e: 2b00 cmp r3, #0
|
|
8017230: d106 bne.n 8017240 <tcp_rexmit_rto_commit+0x1c>
|
|
8017232: 4b0d ldr r3, [pc, #52] ; (8017268 <tcp_rexmit_rto_commit+0x44>)
|
|
8017234: f44f 62d3 mov.w r2, #1688 ; 0x698
|
|
8017238: 490c ldr r1, [pc, #48] ; (801726c <tcp_rexmit_rto_commit+0x48>)
|
|
801723a: 480d ldr r0, [pc, #52] ; (8017270 <tcp_rexmit_rto_commit+0x4c>)
|
|
801723c: f005 fd3c bl 801ccb8 <iprintf>
|
|
|
|
/* increment number of retransmissions */
|
|
if (pcb->nrtx < 0xFF) {
|
|
8017240: 687b ldr r3, [r7, #4]
|
|
8017242: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8017246: 2bff cmp r3, #255 ; 0xff
|
|
8017248: d007 beq.n 801725a <tcp_rexmit_rto_commit+0x36>
|
|
++pcb->nrtx;
|
|
801724a: 687b ldr r3, [r7, #4]
|
|
801724c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8017250: 3301 adds r3, #1
|
|
8017252: b2da uxtb r2, r3
|
|
8017254: 687b ldr r3, [r7, #4]
|
|
8017256: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
}
|
|
/* Do the actual retransmission */
|
|
tcp_output(pcb);
|
|
801725a: 6878 ldr r0, [r7, #4]
|
|
801725c: f7ff fc7a bl 8016b54 <tcp_output>
|
|
}
|
|
8017260: bf00 nop
|
|
8017262: 3708 adds r7, #8
|
|
8017264: 46bd mov sp, r7
|
|
8017266: bd80 pop {r7, pc}
|
|
8017268: 0801f730 .word 0x0801f730
|
|
801726c: 0801fd90 .word 0x0801fd90
|
|
8017270: 0801f784 .word 0x0801f784
|
|
|
|
08017274 <tcp_rexmit_rto>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to re-enqueue all unacked segments
|
|
*/
|
|
void
|
|
tcp_rexmit_rto(struct tcp_pcb *pcb)
|
|
{
|
|
8017274: b580 push {r7, lr}
|
|
8017276: b082 sub sp, #8
|
|
8017278: af00 add r7, sp, #0
|
|
801727a: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL);
|
|
801727c: 687b ldr r3, [r7, #4]
|
|
801727e: 2b00 cmp r3, #0
|
|
8017280: d106 bne.n 8017290 <tcp_rexmit_rto+0x1c>
|
|
8017282: 4b0a ldr r3, [pc, #40] ; (80172ac <tcp_rexmit_rto+0x38>)
|
|
8017284: f240 62ad movw r2, #1709 ; 0x6ad
|
|
8017288: 4909 ldr r1, [pc, #36] ; (80172b0 <tcp_rexmit_rto+0x3c>)
|
|
801728a: 480a ldr r0, [pc, #40] ; (80172b4 <tcp_rexmit_rto+0x40>)
|
|
801728c: f005 fd14 bl 801ccb8 <iprintf>
|
|
|
|
if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) {
|
|
8017290: 6878 ldr r0, [r7, #4]
|
|
8017292: f7ff ff57 bl 8017144 <tcp_rexmit_rto_prepare>
|
|
8017296: 4603 mov r3, r0
|
|
8017298: 2b00 cmp r3, #0
|
|
801729a: d102 bne.n 80172a2 <tcp_rexmit_rto+0x2e>
|
|
tcp_rexmit_rto_commit(pcb);
|
|
801729c: 6878 ldr r0, [r7, #4]
|
|
801729e: f7ff ffc1 bl 8017224 <tcp_rexmit_rto_commit>
|
|
}
|
|
}
|
|
80172a2: bf00 nop
|
|
80172a4: 3708 adds r7, #8
|
|
80172a6: 46bd mov sp, r7
|
|
80172a8: bd80 pop {r7, pc}
|
|
80172aa: bf00 nop
|
|
80172ac: 0801f730 .word 0x0801f730
|
|
80172b0: 0801fdb4 .word 0x0801fdb4
|
|
80172b4: 0801f784 .word 0x0801f784
|
|
|
|
080172b8 <tcp_rexmit>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
|
|
*/
|
|
err_t
|
|
tcp_rexmit(struct tcp_pcb *pcb)
|
|
{
|
|
80172b8: b590 push {r4, r7, lr}
|
|
80172ba: b085 sub sp, #20
|
|
80172bc: af00 add r7, sp, #0
|
|
80172be: 6078 str r0, [r7, #4]
|
|
struct tcp_seg *seg;
|
|
struct tcp_seg **cur_seg;
|
|
|
|
LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL);
|
|
80172c0: 687b ldr r3, [r7, #4]
|
|
80172c2: 2b00 cmp r3, #0
|
|
80172c4: d106 bne.n 80172d4 <tcp_rexmit+0x1c>
|
|
80172c6: 4b2f ldr r3, [pc, #188] ; (8017384 <tcp_rexmit+0xcc>)
|
|
80172c8: f240 62c1 movw r2, #1729 ; 0x6c1
|
|
80172cc: 492e ldr r1, [pc, #184] ; (8017388 <tcp_rexmit+0xd0>)
|
|
80172ce: 482f ldr r0, [pc, #188] ; (801738c <tcp_rexmit+0xd4>)
|
|
80172d0: f005 fcf2 bl 801ccb8 <iprintf>
|
|
|
|
if (pcb->unacked == NULL) {
|
|
80172d4: 687b ldr r3, [r7, #4]
|
|
80172d6: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80172d8: 2b00 cmp r3, #0
|
|
80172da: d102 bne.n 80172e2 <tcp_rexmit+0x2a>
|
|
return ERR_VAL;
|
|
80172dc: f06f 0305 mvn.w r3, #5
|
|
80172e0: e04c b.n 801737c <tcp_rexmit+0xc4>
|
|
}
|
|
|
|
seg = pcb->unacked;
|
|
80172e2: 687b ldr r3, [r7, #4]
|
|
80172e4: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80172e6: 60bb str r3, [r7, #8]
|
|
|
|
/* Give up if the segment is still referenced by the netif driver
|
|
due to deferred transmission. */
|
|
if (tcp_output_segment_busy(seg)) {
|
|
80172e8: 68b8 ldr r0, [r7, #8]
|
|
80172ea: f7ff fe2b bl 8016f44 <tcp_output_segment_busy>
|
|
80172ee: 4603 mov r3, r0
|
|
80172f0: 2b00 cmp r3, #0
|
|
80172f2: d002 beq.n 80172fa <tcp_rexmit+0x42>
|
|
LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n"));
|
|
return ERR_VAL;
|
|
80172f4: f06f 0305 mvn.w r3, #5
|
|
80172f8: e040 b.n 801737c <tcp_rexmit+0xc4>
|
|
}
|
|
|
|
/* Move the first unacked segment to the unsent queue */
|
|
/* Keep the unsent queue sorted. */
|
|
pcb->unacked = seg->next;
|
|
80172fa: 68bb ldr r3, [r7, #8]
|
|
80172fc: 681a ldr r2, [r3, #0]
|
|
80172fe: 687b ldr r3, [r7, #4]
|
|
8017300: 671a str r2, [r3, #112] ; 0x70
|
|
|
|
cur_seg = &(pcb->unsent);
|
|
8017302: 687b ldr r3, [r7, #4]
|
|
8017304: 336c adds r3, #108 ; 0x6c
|
|
8017306: 60fb str r3, [r7, #12]
|
|
while (*cur_seg &&
|
|
8017308: e002 b.n 8017310 <tcp_rexmit+0x58>
|
|
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
|
|
cur_seg = &((*cur_seg)->next );
|
|
801730a: 68fb ldr r3, [r7, #12]
|
|
801730c: 681b ldr r3, [r3, #0]
|
|
801730e: 60fb str r3, [r7, #12]
|
|
while (*cur_seg &&
|
|
8017310: 68fb ldr r3, [r7, #12]
|
|
8017312: 681b ldr r3, [r3, #0]
|
|
8017314: 2b00 cmp r3, #0
|
|
8017316: d011 beq.n 801733c <tcp_rexmit+0x84>
|
|
TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) {
|
|
8017318: 68fb ldr r3, [r7, #12]
|
|
801731a: 681b ldr r3, [r3, #0]
|
|
801731c: 68db ldr r3, [r3, #12]
|
|
801731e: 685b ldr r3, [r3, #4]
|
|
8017320: 4618 mov r0, r3
|
|
8017322: f7f9 fbfa bl 8010b1a <lwip_htonl>
|
|
8017326: 4604 mov r4, r0
|
|
8017328: 68bb ldr r3, [r7, #8]
|
|
801732a: 68db ldr r3, [r3, #12]
|
|
801732c: 685b ldr r3, [r3, #4]
|
|
801732e: 4618 mov r0, r3
|
|
8017330: f7f9 fbf3 bl 8010b1a <lwip_htonl>
|
|
8017334: 4603 mov r3, r0
|
|
8017336: 1ae3 subs r3, r4, r3
|
|
while (*cur_seg &&
|
|
8017338: 2b00 cmp r3, #0
|
|
801733a: dbe6 blt.n 801730a <tcp_rexmit+0x52>
|
|
}
|
|
seg->next = *cur_seg;
|
|
801733c: 68fb ldr r3, [r7, #12]
|
|
801733e: 681a ldr r2, [r3, #0]
|
|
8017340: 68bb ldr r3, [r7, #8]
|
|
8017342: 601a str r2, [r3, #0]
|
|
*cur_seg = seg;
|
|
8017344: 68fb ldr r3, [r7, #12]
|
|
8017346: 68ba ldr r2, [r7, #8]
|
|
8017348: 601a str r2, [r3, #0]
|
|
#if TCP_OVERSIZE
|
|
if (seg->next == NULL) {
|
|
801734a: 68bb ldr r3, [r7, #8]
|
|
801734c: 681b ldr r3, [r3, #0]
|
|
801734e: 2b00 cmp r3, #0
|
|
8017350: d103 bne.n 801735a <tcp_rexmit+0xa2>
|
|
/* the retransmitted segment is last in unsent, so reset unsent_oversize */
|
|
pcb->unsent_oversize = 0;
|
|
8017352: 687b ldr r3, [r7, #4]
|
|
8017354: 2200 movs r2, #0
|
|
8017356: f8a3 2068 strh.w r2, [r3, #104] ; 0x68
|
|
}
|
|
#endif /* TCP_OVERSIZE */
|
|
|
|
if (pcb->nrtx < 0xFF) {
|
|
801735a: 687b ldr r3, [r7, #4]
|
|
801735c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
8017360: 2bff cmp r3, #255 ; 0xff
|
|
8017362: d007 beq.n 8017374 <tcp_rexmit+0xbc>
|
|
++pcb->nrtx;
|
|
8017364: 687b ldr r3, [r7, #4]
|
|
8017366: f893 3042 ldrb.w r3, [r3, #66] ; 0x42
|
|
801736a: 3301 adds r3, #1
|
|
801736c: b2da uxtb r2, r3
|
|
801736e: 687b ldr r3, [r7, #4]
|
|
8017370: f883 2042 strb.w r2, [r3, #66] ; 0x42
|
|
}
|
|
|
|
/* Don't take any rtt measurements after retransmitting. */
|
|
pcb->rttest = 0;
|
|
8017374: 687b ldr r3, [r7, #4]
|
|
8017376: 2200 movs r2, #0
|
|
8017378: 635a str r2, [r3, #52] ; 0x34
|
|
|
|
/* Do the actual retransmission. */
|
|
MIB2_STATS_INC(mib2.tcpretranssegs);
|
|
/* No need to call tcp_output: we are always called from tcp_input()
|
|
and thus tcp_output directly returns. */
|
|
return ERR_OK;
|
|
801737a: 2300 movs r3, #0
|
|
}
|
|
801737c: 4618 mov r0, r3
|
|
801737e: 3714 adds r7, #20
|
|
8017380: 46bd mov sp, r7
|
|
8017382: bd90 pop {r4, r7, pc}
|
|
8017384: 0801f730 .word 0x0801f730
|
|
8017388: 0801fdd0 .word 0x0801fdd0
|
|
801738c: 0801f784 .word 0x0801f784
|
|
|
|
08017390 <tcp_rexmit_fast>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to retransmit the first unacked segment
|
|
*/
|
|
void
|
|
tcp_rexmit_fast(struct tcp_pcb *pcb)
|
|
{
|
|
8017390: b580 push {r7, lr}
|
|
8017392: b082 sub sp, #8
|
|
8017394: af00 add r7, sp, #0
|
|
8017396: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL);
|
|
8017398: 687b ldr r3, [r7, #4]
|
|
801739a: 2b00 cmp r3, #0
|
|
801739c: d106 bne.n 80173ac <tcp_rexmit_fast+0x1c>
|
|
801739e: 4b2f ldr r3, [pc, #188] ; (801745c <tcp_rexmit_fast+0xcc>)
|
|
80173a0: f240 62f9 movw r2, #1785 ; 0x6f9
|
|
80173a4: 492e ldr r1, [pc, #184] ; (8017460 <tcp_rexmit_fast+0xd0>)
|
|
80173a6: 482f ldr r0, [pc, #188] ; (8017464 <tcp_rexmit_fast+0xd4>)
|
|
80173a8: f005 fc86 bl 801ccb8 <iprintf>
|
|
|
|
if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) {
|
|
80173ac: 687b ldr r3, [r7, #4]
|
|
80173ae: 6f1b ldr r3, [r3, #112] ; 0x70
|
|
80173b0: 2b00 cmp r3, #0
|
|
80173b2: d04f beq.n 8017454 <tcp_rexmit_fast+0xc4>
|
|
80173b4: 687b ldr r3, [r7, #4]
|
|
80173b6: 8b5b ldrh r3, [r3, #26]
|
|
80173b8: f003 0304 and.w r3, r3, #4
|
|
80173bc: 2b00 cmp r3, #0
|
|
80173be: d149 bne.n 8017454 <tcp_rexmit_fast+0xc4>
|
|
LWIP_DEBUGF(TCP_FR_DEBUG,
|
|
("tcp_receive: dupacks %"U16_F" (%"U32_F
|
|
"), fast retransmit %"U32_F"\n",
|
|
(u16_t)pcb->dupacks, pcb->lastack,
|
|
lwip_ntohl(pcb->unacked->tcphdr->seqno)));
|
|
if (tcp_rexmit(pcb) == ERR_OK) {
|
|
80173c0: 6878 ldr r0, [r7, #4]
|
|
80173c2: f7ff ff79 bl 80172b8 <tcp_rexmit>
|
|
80173c6: 4603 mov r3, r0
|
|
80173c8: 2b00 cmp r3, #0
|
|
80173ca: d143 bne.n 8017454 <tcp_rexmit_fast+0xc4>
|
|
/* Set ssthresh to half of the minimum of the current
|
|
* cwnd and the advertised window */
|
|
pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2;
|
|
80173cc: 687b ldr r3, [r7, #4]
|
|
80173ce: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48
|
|
80173d2: 687b ldr r3, [r7, #4]
|
|
80173d4: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
80173d8: 429a cmp r2, r3
|
|
80173da: d208 bcs.n 80173ee <tcp_rexmit_fast+0x5e>
|
|
80173dc: 687b ldr r3, [r7, #4]
|
|
80173de: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48
|
|
80173e2: 2b00 cmp r3, #0
|
|
80173e4: da00 bge.n 80173e8 <tcp_rexmit_fast+0x58>
|
|
80173e6: 3301 adds r3, #1
|
|
80173e8: 105b asrs r3, r3, #1
|
|
80173ea: b29b uxth r3, r3
|
|
80173ec: e007 b.n 80173fe <tcp_rexmit_fast+0x6e>
|
|
80173ee: 687b ldr r3, [r7, #4]
|
|
80173f0: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60
|
|
80173f4: 2b00 cmp r3, #0
|
|
80173f6: da00 bge.n 80173fa <tcp_rexmit_fast+0x6a>
|
|
80173f8: 3301 adds r3, #1
|
|
80173fa: 105b asrs r3, r3, #1
|
|
80173fc: b29b uxth r3, r3
|
|
80173fe: 687a ldr r2, [r7, #4]
|
|
8017400: f8a2 304a strh.w r3, [r2, #74] ; 0x4a
|
|
|
|
/* The minimum value for ssthresh should be 2 MSS */
|
|
if (pcb->ssthresh < (2U * pcb->mss)) {
|
|
8017404: 687b ldr r3, [r7, #4]
|
|
8017406: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a
|
|
801740a: 461a mov r2, r3
|
|
801740c: 687b ldr r3, [r7, #4]
|
|
801740e: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
8017410: 005b lsls r3, r3, #1
|
|
8017412: 429a cmp r2, r3
|
|
8017414: d206 bcs.n 8017424 <tcp_rexmit_fast+0x94>
|
|
LWIP_DEBUGF(TCP_FR_DEBUG,
|
|
("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F
|
|
" should be min 2 mss %"U16_F"...\n",
|
|
pcb->ssthresh, (u16_t)(2 * pcb->mss)));
|
|
pcb->ssthresh = 2 * pcb->mss;
|
|
8017416: 687b ldr r3, [r7, #4]
|
|
8017418: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
801741a: 005b lsls r3, r3, #1
|
|
801741c: b29a uxth r2, r3
|
|
801741e: 687b ldr r3, [r7, #4]
|
|
8017420: f8a3 204a strh.w r2, [r3, #74] ; 0x4a
|
|
}
|
|
|
|
pcb->cwnd = pcb->ssthresh + 3 * pcb->mss;
|
|
8017424: 687b ldr r3, [r7, #4]
|
|
8017426: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a
|
|
801742a: 687b ldr r3, [r7, #4]
|
|
801742c: 8e5b ldrh r3, [r3, #50] ; 0x32
|
|
801742e: 4619 mov r1, r3
|
|
8017430: 0049 lsls r1, r1, #1
|
|
8017432: 440b add r3, r1
|
|
8017434: b29b uxth r3, r3
|
|
8017436: 4413 add r3, r2
|
|
8017438: b29a uxth r2, r3
|
|
801743a: 687b ldr r3, [r7, #4]
|
|
801743c: f8a3 2048 strh.w r2, [r3, #72] ; 0x48
|
|
tcp_set_flags(pcb, TF_INFR);
|
|
8017440: 687b ldr r3, [r7, #4]
|
|
8017442: 8b5b ldrh r3, [r3, #26]
|
|
8017444: f043 0304 orr.w r3, r3, #4
|
|
8017448: b29a uxth r2, r3
|
|
801744a: 687b ldr r3, [r7, #4]
|
|
801744c: 835a strh r2, [r3, #26]
|
|
|
|
/* Reset the retransmission timer to prevent immediate rto retransmissions */
|
|
pcb->rtime = 0;
|
|
801744e: 687b ldr r3, [r7, #4]
|
|
8017450: 2200 movs r2, #0
|
|
8017452: 861a strh r2, [r3, #48] ; 0x30
|
|
}
|
|
}
|
|
}
|
|
8017454: bf00 nop
|
|
8017456: 3708 adds r7, #8
|
|
8017458: 46bd mov sp, r7
|
|
801745a: bd80 pop {r7, pc}
|
|
801745c: 0801f730 .word 0x0801f730
|
|
8017460: 0801fde8 .word 0x0801fde8
|
|
8017464: 0801f784 .word 0x0801f784
|
|
|
|
08017468 <tcp_output_alloc_header_common>:
|
|
|
|
static struct pbuf *
|
|
tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen,
|
|
u32_t seqno_be /* already in network byte order */,
|
|
u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd)
|
|
{
|
|
8017468: b580 push {r7, lr}
|
|
801746a: b086 sub sp, #24
|
|
801746c: af00 add r7, sp, #0
|
|
801746e: 60f8 str r0, [r7, #12]
|
|
8017470: 607b str r3, [r7, #4]
|
|
8017472: 460b mov r3, r1
|
|
8017474: 817b strh r3, [r7, #10]
|
|
8017476: 4613 mov r3, r2
|
|
8017478: 813b strh r3, [r7, #8]
|
|
struct tcp_hdr *tcphdr;
|
|
struct pbuf *p;
|
|
|
|
p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM);
|
|
801747a: 897a ldrh r2, [r7, #10]
|
|
801747c: 893b ldrh r3, [r7, #8]
|
|
801747e: 4413 add r3, r2
|
|
8017480: b29b uxth r3, r3
|
|
8017482: 3314 adds r3, #20
|
|
8017484: b29b uxth r3, r3
|
|
8017486: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801748a: 4619 mov r1, r3
|
|
801748c: 2022 movs r0, #34 ; 0x22
|
|
801748e: f7fa fc03 bl 8011c98 <pbuf_alloc>
|
|
8017492: 6178 str r0, [r7, #20]
|
|
if (p != NULL) {
|
|
8017494: 697b ldr r3, [r7, #20]
|
|
8017496: 2b00 cmp r3, #0
|
|
8017498: d04e beq.n 8017538 <tcp_output_alloc_header_common+0xd0>
|
|
LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr",
|
|
801749a: 697b ldr r3, [r7, #20]
|
|
801749c: 895b ldrh r3, [r3, #10]
|
|
801749e: 461a mov r2, r3
|
|
80174a0: 897b ldrh r3, [r7, #10]
|
|
80174a2: 3314 adds r3, #20
|
|
80174a4: 429a cmp r2, r3
|
|
80174a6: da06 bge.n 80174b6 <tcp_output_alloc_header_common+0x4e>
|
|
80174a8: 4b26 ldr r3, [pc, #152] ; (8017544 <tcp_output_alloc_header_common+0xdc>)
|
|
80174aa: f240 7224 movw r2, #1828 ; 0x724
|
|
80174ae: 4926 ldr r1, [pc, #152] ; (8017548 <tcp_output_alloc_header_common+0xe0>)
|
|
80174b0: 4826 ldr r0, [pc, #152] ; (801754c <tcp_output_alloc_header_common+0xe4>)
|
|
80174b2: f005 fc01 bl 801ccb8 <iprintf>
|
|
(p->len >= TCP_HLEN + optlen));
|
|
tcphdr = (struct tcp_hdr *)p->payload;
|
|
80174b6: 697b ldr r3, [r7, #20]
|
|
80174b8: 685b ldr r3, [r3, #4]
|
|
80174ba: 613b str r3, [r7, #16]
|
|
tcphdr->src = lwip_htons(src_port);
|
|
80174bc: 8c3b ldrh r3, [r7, #32]
|
|
80174be: 4618 mov r0, r3
|
|
80174c0: f7f9 fb16 bl 8010af0 <lwip_htons>
|
|
80174c4: 4603 mov r3, r0
|
|
80174c6: 461a mov r2, r3
|
|
80174c8: 693b ldr r3, [r7, #16]
|
|
80174ca: 801a strh r2, [r3, #0]
|
|
tcphdr->dest = lwip_htons(dst_port);
|
|
80174cc: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
80174ce: 4618 mov r0, r3
|
|
80174d0: f7f9 fb0e bl 8010af0 <lwip_htons>
|
|
80174d4: 4603 mov r3, r0
|
|
80174d6: 461a mov r2, r3
|
|
80174d8: 693b ldr r3, [r7, #16]
|
|
80174da: 805a strh r2, [r3, #2]
|
|
tcphdr->seqno = seqno_be;
|
|
80174dc: 693b ldr r3, [r7, #16]
|
|
80174de: 687a ldr r2, [r7, #4]
|
|
80174e0: 605a str r2, [r3, #4]
|
|
tcphdr->ackno = lwip_htonl(ackno);
|
|
80174e2: 68f8 ldr r0, [r7, #12]
|
|
80174e4: f7f9 fb19 bl 8010b1a <lwip_htonl>
|
|
80174e8: 4602 mov r2, r0
|
|
80174ea: 693b ldr r3, [r7, #16]
|
|
80174ec: 609a str r2, [r3, #8]
|
|
TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags);
|
|
80174ee: 897b ldrh r3, [r7, #10]
|
|
80174f0: 089b lsrs r3, r3, #2
|
|
80174f2: b29b uxth r3, r3
|
|
80174f4: 3305 adds r3, #5
|
|
80174f6: b29b uxth r3, r3
|
|
80174f8: 031b lsls r3, r3, #12
|
|
80174fa: b29a uxth r2, r3
|
|
80174fc: f897 3028 ldrb.w r3, [r7, #40] ; 0x28
|
|
8017500: b29b uxth r3, r3
|
|
8017502: 4313 orrs r3, r2
|
|
8017504: b29b uxth r3, r3
|
|
8017506: 4618 mov r0, r3
|
|
8017508: f7f9 faf2 bl 8010af0 <lwip_htons>
|
|
801750c: 4603 mov r3, r0
|
|
801750e: 461a mov r2, r3
|
|
8017510: 693b ldr r3, [r7, #16]
|
|
8017512: 819a strh r2, [r3, #12]
|
|
tcphdr->wnd = lwip_htons(wnd);
|
|
8017514: 8dbb ldrh r3, [r7, #44] ; 0x2c
|
|
8017516: 4618 mov r0, r3
|
|
8017518: f7f9 faea bl 8010af0 <lwip_htons>
|
|
801751c: 4603 mov r3, r0
|
|
801751e: 461a mov r2, r3
|
|
8017520: 693b ldr r3, [r7, #16]
|
|
8017522: 81da strh r2, [r3, #14]
|
|
tcphdr->chksum = 0;
|
|
8017524: 693b ldr r3, [r7, #16]
|
|
8017526: 2200 movs r2, #0
|
|
8017528: 741a strb r2, [r3, #16]
|
|
801752a: 2200 movs r2, #0
|
|
801752c: 745a strb r2, [r3, #17]
|
|
tcphdr->urgp = 0;
|
|
801752e: 693b ldr r3, [r7, #16]
|
|
8017530: 2200 movs r2, #0
|
|
8017532: 749a strb r2, [r3, #18]
|
|
8017534: 2200 movs r2, #0
|
|
8017536: 74da strb r2, [r3, #19]
|
|
}
|
|
return p;
|
|
8017538: 697b ldr r3, [r7, #20]
|
|
}
|
|
801753a: 4618 mov r0, r3
|
|
801753c: 3718 adds r7, #24
|
|
801753e: 46bd mov sp, r7
|
|
8017540: bd80 pop {r7, pc}
|
|
8017542: bf00 nop
|
|
8017544: 0801f730 .word 0x0801f730
|
|
8017548: 0801fe08 .word 0x0801fe08
|
|
801754c: 0801f784 .word 0x0801f784
|
|
|
|
08017550 <tcp_output_alloc_header>:
|
|
* @return pbuf with p->payload being the tcp_hdr
|
|
*/
|
|
static struct pbuf *
|
|
tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen,
|
|
u32_t seqno_be /* already in network byte order */)
|
|
{
|
|
8017550: b5b0 push {r4, r5, r7, lr}
|
|
8017552: b08a sub sp, #40 ; 0x28
|
|
8017554: af04 add r7, sp, #16
|
|
8017556: 60f8 str r0, [r7, #12]
|
|
8017558: 607b str r3, [r7, #4]
|
|
801755a: 460b mov r3, r1
|
|
801755c: 817b strh r3, [r7, #10]
|
|
801755e: 4613 mov r3, r2
|
|
8017560: 813b strh r3, [r7, #8]
|
|
struct pbuf *p;
|
|
|
|
LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL);
|
|
8017562: 68fb ldr r3, [r7, #12]
|
|
8017564: 2b00 cmp r3, #0
|
|
8017566: d106 bne.n 8017576 <tcp_output_alloc_header+0x26>
|
|
8017568: 4b15 ldr r3, [pc, #84] ; (80175c0 <tcp_output_alloc_header+0x70>)
|
|
801756a: f240 7242 movw r2, #1858 ; 0x742
|
|
801756e: 4915 ldr r1, [pc, #84] ; (80175c4 <tcp_output_alloc_header+0x74>)
|
|
8017570: 4815 ldr r0, [pc, #84] ; (80175c8 <tcp_output_alloc_header+0x78>)
|
|
8017572: f005 fba1 bl 801ccb8 <iprintf>
|
|
|
|
p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen,
|
|
8017576: 68fb ldr r3, [r7, #12]
|
|
8017578: 6a58 ldr r0, [r3, #36] ; 0x24
|
|
801757a: 68fb ldr r3, [r7, #12]
|
|
801757c: 8adb ldrh r3, [r3, #22]
|
|
801757e: 68fa ldr r2, [r7, #12]
|
|
8017580: 8b12 ldrh r2, [r2, #24]
|
|
8017582: 68f9 ldr r1, [r7, #12]
|
|
8017584: 8d49 ldrh r1, [r1, #42] ; 0x2a
|
|
8017586: 893d ldrh r5, [r7, #8]
|
|
8017588: 897c ldrh r4, [r7, #10]
|
|
801758a: 9103 str r1, [sp, #12]
|
|
801758c: 2110 movs r1, #16
|
|
801758e: 9102 str r1, [sp, #8]
|
|
8017590: 9201 str r2, [sp, #4]
|
|
8017592: 9300 str r3, [sp, #0]
|
|
8017594: 687b ldr r3, [r7, #4]
|
|
8017596: 462a mov r2, r5
|
|
8017598: 4621 mov r1, r4
|
|
801759a: f7ff ff65 bl 8017468 <tcp_output_alloc_header_common>
|
|
801759e: 6178 str r0, [r7, #20]
|
|
seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK,
|
|
TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd)));
|
|
if (p != NULL) {
|
|
80175a0: 697b ldr r3, [r7, #20]
|
|
80175a2: 2b00 cmp r3, #0
|
|
80175a4: d006 beq.n 80175b4 <tcp_output_alloc_header+0x64>
|
|
/* If we're sending a packet, update the announced right window edge */
|
|
pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd;
|
|
80175a6: 68fb ldr r3, [r7, #12]
|
|
80175a8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80175aa: 68fa ldr r2, [r7, #12]
|
|
80175ac: 8d52 ldrh r2, [r2, #42] ; 0x2a
|
|
80175ae: 441a add r2, r3
|
|
80175b0: 68fb ldr r3, [r7, #12]
|
|
80175b2: 62da str r2, [r3, #44] ; 0x2c
|
|
}
|
|
return p;
|
|
80175b4: 697b ldr r3, [r7, #20]
|
|
}
|
|
80175b6: 4618 mov r0, r3
|
|
80175b8: 3718 adds r7, #24
|
|
80175ba: 46bd mov sp, r7
|
|
80175bc: bdb0 pop {r4, r5, r7, pc}
|
|
80175be: bf00 nop
|
|
80175c0: 0801f730 .word 0x0801f730
|
|
80175c4: 0801fe38 .word 0x0801fe38
|
|
80175c8: 0801f784 .word 0x0801f784
|
|
|
|
080175cc <tcp_output_fill_options>:
|
|
|
|
/* Fill in options for control segments */
|
|
static void
|
|
tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks)
|
|
{
|
|
80175cc: b580 push {r7, lr}
|
|
80175ce: b088 sub sp, #32
|
|
80175d0: af00 add r7, sp, #0
|
|
80175d2: 60f8 str r0, [r7, #12]
|
|
80175d4: 60b9 str r1, [r7, #8]
|
|
80175d6: 4611 mov r1, r2
|
|
80175d8: 461a mov r2, r3
|
|
80175da: 460b mov r3, r1
|
|
80175dc: 71fb strb r3, [r7, #7]
|
|
80175de: 4613 mov r3, r2
|
|
80175e0: 71bb strb r3, [r7, #6]
|
|
struct tcp_hdr *tcphdr;
|
|
u32_t *opts;
|
|
u16_t sacks_len = 0;
|
|
80175e2: 2300 movs r3, #0
|
|
80175e4: 83fb strh r3, [r7, #30]
|
|
|
|
LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL);
|
|
80175e6: 68bb ldr r3, [r7, #8]
|
|
80175e8: 2b00 cmp r3, #0
|
|
80175ea: d106 bne.n 80175fa <tcp_output_fill_options+0x2e>
|
|
80175ec: 4b13 ldr r3, [pc, #76] ; (801763c <tcp_output_fill_options+0x70>)
|
|
80175ee: f240 7256 movw r2, #1878 ; 0x756
|
|
80175f2: 4913 ldr r1, [pc, #76] ; (8017640 <tcp_output_fill_options+0x74>)
|
|
80175f4: 4813 ldr r0, [pc, #76] ; (8017644 <tcp_output_fill_options+0x78>)
|
|
80175f6: f005 fb5f bl 801ccb8 <iprintf>
|
|
|
|
tcphdr = (struct tcp_hdr *)p->payload;
|
|
80175fa: 68bb ldr r3, [r7, #8]
|
|
80175fc: 685b ldr r3, [r3, #4]
|
|
80175fe: 61bb str r3, [r7, #24]
|
|
opts = (u32_t *)(void *)(tcphdr + 1);
|
|
8017600: 69bb ldr r3, [r7, #24]
|
|
8017602: 3314 adds r3, #20
|
|
8017604: 617b str r3, [r7, #20]
|
|
opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts);
|
|
#endif
|
|
|
|
LWIP_UNUSED_ARG(pcb);
|
|
LWIP_UNUSED_ARG(sacks_len);
|
|
LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb));
|
|
8017606: 69bb ldr r3, [r7, #24]
|
|
8017608: f103 0214 add.w r2, r3, #20
|
|
801760c: 8bfb ldrh r3, [r7, #30]
|
|
801760e: 009b lsls r3, r3, #2
|
|
8017610: 4619 mov r1, r3
|
|
8017612: 79fb ldrb r3, [r7, #7]
|
|
8017614: 009b lsls r3, r3, #2
|
|
8017616: f003 0304 and.w r3, r3, #4
|
|
801761a: 440b add r3, r1
|
|
801761c: 4413 add r3, r2
|
|
801761e: 697a ldr r2, [r7, #20]
|
|
8017620: 429a cmp r2, r3
|
|
8017622: d006 beq.n 8017632 <tcp_output_fill_options+0x66>
|
|
8017624: 4b05 ldr r3, [pc, #20] ; (801763c <tcp_output_fill_options+0x70>)
|
|
8017626: f240 7275 movw r2, #1909 ; 0x775
|
|
801762a: 4907 ldr r1, [pc, #28] ; (8017648 <tcp_output_fill_options+0x7c>)
|
|
801762c: 4805 ldr r0, [pc, #20] ; (8017644 <tcp_output_fill_options+0x78>)
|
|
801762e: f005 fb43 bl 801ccb8 <iprintf>
|
|
LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */
|
|
LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */
|
|
}
|
|
8017632: bf00 nop
|
|
8017634: 3720 adds r7, #32
|
|
8017636: 46bd mov sp, r7
|
|
8017638: bd80 pop {r7, pc}
|
|
801763a: bf00 nop
|
|
801763c: 0801f730 .word 0x0801f730
|
|
8017640: 0801fe60 .word 0x0801fe60
|
|
8017644: 0801f784 .word 0x0801f784
|
|
8017648: 0801fd58 .word 0x0801fd58
|
|
|
|
0801764c <tcp_output_control_segment>:
|
|
* header checksum and calling ip_output_if while handling netif hints and stats.
|
|
*/
|
|
static err_t
|
|
tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p,
|
|
const ip_addr_t *src, const ip_addr_t *dst)
|
|
{
|
|
801764c: b580 push {r7, lr}
|
|
801764e: b08a sub sp, #40 ; 0x28
|
|
8017650: af04 add r7, sp, #16
|
|
8017652: 60f8 str r0, [r7, #12]
|
|
8017654: 60b9 str r1, [r7, #8]
|
|
8017656: 607a str r2, [r7, #4]
|
|
8017658: 603b str r3, [r7, #0]
|
|
err_t err;
|
|
struct netif *netif;
|
|
|
|
LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL);
|
|
801765a: 68bb ldr r3, [r7, #8]
|
|
801765c: 2b00 cmp r3, #0
|
|
801765e: d106 bne.n 801766e <tcp_output_control_segment+0x22>
|
|
8017660: 4b1c ldr r3, [pc, #112] ; (80176d4 <tcp_output_control_segment+0x88>)
|
|
8017662: f240 7287 movw r2, #1927 ; 0x787
|
|
8017666: 491c ldr r1, [pc, #112] ; (80176d8 <tcp_output_control_segment+0x8c>)
|
|
8017668: 481c ldr r0, [pc, #112] ; (80176dc <tcp_output_control_segment+0x90>)
|
|
801766a: f005 fb25 bl 801ccb8 <iprintf>
|
|
|
|
netif = tcp_route(pcb, src, dst);
|
|
801766e: 683a ldr r2, [r7, #0]
|
|
8017670: 6879 ldr r1, [r7, #4]
|
|
8017672: 68f8 ldr r0, [r7, #12]
|
|
8017674: f7fe ff2e bl 80164d4 <tcp_route>
|
|
8017678: 6138 str r0, [r7, #16]
|
|
if (netif == NULL) {
|
|
801767a: 693b ldr r3, [r7, #16]
|
|
801767c: 2b00 cmp r3, #0
|
|
801767e: d102 bne.n 8017686 <tcp_output_control_segment+0x3a>
|
|
err = ERR_RTE;
|
|
8017680: 23fc movs r3, #252 ; 0xfc
|
|
8017682: 75fb strb r3, [r7, #23]
|
|
8017684: e01c b.n 80176c0 <tcp_output_control_segment+0x74>
|
|
struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload;
|
|
tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len,
|
|
src, dst);
|
|
}
|
|
#endif
|
|
if (pcb != NULL) {
|
|
8017686: 68fb ldr r3, [r7, #12]
|
|
8017688: 2b00 cmp r3, #0
|
|
801768a: d006 beq.n 801769a <tcp_output_control_segment+0x4e>
|
|
NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints)));
|
|
ttl = pcb->ttl;
|
|
801768c: 68fb ldr r3, [r7, #12]
|
|
801768e: 7adb ldrb r3, [r3, #11]
|
|
8017690: 75bb strb r3, [r7, #22]
|
|
tos = pcb->tos;
|
|
8017692: 68fb ldr r3, [r7, #12]
|
|
8017694: 7a9b ldrb r3, [r3, #10]
|
|
8017696: 757b strb r3, [r7, #21]
|
|
8017698: e003 b.n 80176a2 <tcp_output_control_segment+0x56>
|
|
} else {
|
|
/* Send output with hardcoded TTL/HL since we have no access to the pcb */
|
|
ttl = TCP_TTL;
|
|
801769a: 23ff movs r3, #255 ; 0xff
|
|
801769c: 75bb strb r3, [r7, #22]
|
|
tos = 0;
|
|
801769e: 2300 movs r3, #0
|
|
80176a0: 757b strb r3, [r7, #21]
|
|
}
|
|
TCP_STATS_INC(tcp.xmit);
|
|
err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif);
|
|
80176a2: 7dba ldrb r2, [r7, #22]
|
|
80176a4: 693b ldr r3, [r7, #16]
|
|
80176a6: 9302 str r3, [sp, #8]
|
|
80176a8: 2306 movs r3, #6
|
|
80176aa: 9301 str r3, [sp, #4]
|
|
80176ac: 7d7b ldrb r3, [r7, #21]
|
|
80176ae: 9300 str r3, [sp, #0]
|
|
80176b0: 4613 mov r3, r2
|
|
80176b2: 683a ldr r2, [r7, #0]
|
|
80176b4: 6879 ldr r1, [r7, #4]
|
|
80176b6: 68b8 ldr r0, [r7, #8]
|
|
80176b8: f004 f964 bl 801b984 <ip4_output_if>
|
|
80176bc: 4603 mov r3, r0
|
|
80176be: 75fb strb r3, [r7, #23]
|
|
NETIF_RESET_HINTS(netif);
|
|
}
|
|
pbuf_free(p);
|
|
80176c0: 68b8 ldr r0, [r7, #8]
|
|
80176c2: f7fa fdc9 bl 8012258 <pbuf_free>
|
|
return err;
|
|
80176c6: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
80176ca: 4618 mov r0, r3
|
|
80176cc: 3718 adds r7, #24
|
|
80176ce: 46bd mov sp, r7
|
|
80176d0: bd80 pop {r7, pc}
|
|
80176d2: bf00 nop
|
|
80176d4: 0801f730 .word 0x0801f730
|
|
80176d8: 0801fe88 .word 0x0801fe88
|
|
80176dc: 0801f784 .word 0x0801f784
|
|
|
|
080176e0 <tcp_rst>:
|
|
*/
|
|
void
|
|
tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno,
|
|
const ip_addr_t *local_ip, const ip_addr_t *remote_ip,
|
|
u16_t local_port, u16_t remote_port)
|
|
{
|
|
80176e0: b590 push {r4, r7, lr}
|
|
80176e2: b08b sub sp, #44 ; 0x2c
|
|
80176e4: af04 add r7, sp, #16
|
|
80176e6: 60f8 str r0, [r7, #12]
|
|
80176e8: 60b9 str r1, [r7, #8]
|
|
80176ea: 607a str r2, [r7, #4]
|
|
80176ec: 603b str r3, [r7, #0]
|
|
struct pbuf *p;
|
|
u16_t wnd;
|
|
u8_t optlen;
|
|
|
|
LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL);
|
|
80176ee: 683b ldr r3, [r7, #0]
|
|
80176f0: 2b00 cmp r3, #0
|
|
80176f2: d106 bne.n 8017702 <tcp_rst+0x22>
|
|
80176f4: 4b1f ldr r3, [pc, #124] ; (8017774 <tcp_rst+0x94>)
|
|
80176f6: f240 72c4 movw r2, #1988 ; 0x7c4
|
|
80176fa: 491f ldr r1, [pc, #124] ; (8017778 <tcp_rst+0x98>)
|
|
80176fc: 481f ldr r0, [pc, #124] ; (801777c <tcp_rst+0x9c>)
|
|
80176fe: f005 fadb bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL);
|
|
8017702: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8017704: 2b00 cmp r3, #0
|
|
8017706: d106 bne.n 8017716 <tcp_rst+0x36>
|
|
8017708: 4b1a ldr r3, [pc, #104] ; (8017774 <tcp_rst+0x94>)
|
|
801770a: f240 72c5 movw r2, #1989 ; 0x7c5
|
|
801770e: 491c ldr r1, [pc, #112] ; (8017780 <tcp_rst+0xa0>)
|
|
8017710: 481a ldr r0, [pc, #104] ; (801777c <tcp_rst+0x9c>)
|
|
8017712: f005 fad1 bl 801ccb8 <iprintf>
|
|
|
|
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
|
|
8017716: 2300 movs r3, #0
|
|
8017718: 75fb strb r3, [r7, #23]
|
|
|
|
#if LWIP_WND_SCALE
|
|
wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF));
|
|
#else
|
|
wnd = PP_HTONS(TCP_WND);
|
|
801771a: f246 0308 movw r3, #24584 ; 0x6008
|
|
801771e: 82bb strh r3, [r7, #20]
|
|
#endif
|
|
|
|
p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port,
|
|
8017720: 7dfb ldrb r3, [r7, #23]
|
|
8017722: b29c uxth r4, r3
|
|
8017724: 68b8 ldr r0, [r7, #8]
|
|
8017726: f7f9 f9f8 bl 8010b1a <lwip_htonl>
|
|
801772a: 4602 mov r2, r0
|
|
801772c: 8abb ldrh r3, [r7, #20]
|
|
801772e: 9303 str r3, [sp, #12]
|
|
8017730: 2314 movs r3, #20
|
|
8017732: 9302 str r3, [sp, #8]
|
|
8017734: 8e3b ldrh r3, [r7, #48] ; 0x30
|
|
8017736: 9301 str r3, [sp, #4]
|
|
8017738: 8dbb ldrh r3, [r7, #44] ; 0x2c
|
|
801773a: 9300 str r3, [sp, #0]
|
|
801773c: 4613 mov r3, r2
|
|
801773e: 2200 movs r2, #0
|
|
8017740: 4621 mov r1, r4
|
|
8017742: 6878 ldr r0, [r7, #4]
|
|
8017744: f7ff fe90 bl 8017468 <tcp_output_alloc_header_common>
|
|
8017748: 6138 str r0, [r7, #16]
|
|
remote_port, TCP_RST | TCP_ACK, wnd);
|
|
if (p == NULL) {
|
|
801774a: 693b ldr r3, [r7, #16]
|
|
801774c: 2b00 cmp r3, #0
|
|
801774e: d00c beq.n 801776a <tcp_rst+0x8a>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n"));
|
|
return;
|
|
}
|
|
tcp_output_fill_options(pcb, p, 0, optlen);
|
|
8017750: 7dfb ldrb r3, [r7, #23]
|
|
8017752: 2200 movs r2, #0
|
|
8017754: 6939 ldr r1, [r7, #16]
|
|
8017756: 68f8 ldr r0, [r7, #12]
|
|
8017758: f7ff ff38 bl 80175cc <tcp_output_fill_options>
|
|
|
|
MIB2_STATS_INC(mib2.tcpoutrsts);
|
|
|
|
tcp_output_control_segment(pcb, p, local_ip, remote_ip);
|
|
801775c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801775e: 683a ldr r2, [r7, #0]
|
|
8017760: 6939 ldr r1, [r7, #16]
|
|
8017762: 68f8 ldr r0, [r7, #12]
|
|
8017764: f7ff ff72 bl 801764c <tcp_output_control_segment>
|
|
8017768: e000 b.n 801776c <tcp_rst+0x8c>
|
|
return;
|
|
801776a: bf00 nop
|
|
LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno));
|
|
}
|
|
801776c: 371c adds r7, #28
|
|
801776e: 46bd mov sp, r7
|
|
8017770: bd90 pop {r4, r7, pc}
|
|
8017772: bf00 nop
|
|
8017774: 0801f730 .word 0x0801f730
|
|
8017778: 0801feb4 .word 0x0801feb4
|
|
801777c: 0801f784 .word 0x0801f784
|
|
8017780: 0801fed0 .word 0x0801fed0
|
|
|
|
08017784 <tcp_send_empty_ack>:
|
|
*
|
|
* @param pcb Protocol control block for the TCP connection to send the ACK
|
|
*/
|
|
err_t
|
|
tcp_send_empty_ack(struct tcp_pcb *pcb)
|
|
{
|
|
8017784: b590 push {r4, r7, lr}
|
|
8017786: b087 sub sp, #28
|
|
8017788: af00 add r7, sp, #0
|
|
801778a: 6078 str r0, [r7, #4]
|
|
err_t err;
|
|
struct pbuf *p;
|
|
u8_t optlen, optflags = 0;
|
|
801778c: 2300 movs r3, #0
|
|
801778e: 75fb strb r3, [r7, #23]
|
|
u8_t num_sacks = 0;
|
|
8017790: 2300 movs r3, #0
|
|
8017792: 75bb strb r3, [r7, #22]
|
|
|
|
LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL);
|
|
8017794: 687b ldr r3, [r7, #4]
|
|
8017796: 2b00 cmp r3, #0
|
|
8017798: d106 bne.n 80177a8 <tcp_send_empty_ack+0x24>
|
|
801779a: 4b28 ldr r3, [pc, #160] ; (801783c <tcp_send_empty_ack+0xb8>)
|
|
801779c: f240 72ea movw r2, #2026 ; 0x7ea
|
|
80177a0: 4927 ldr r1, [pc, #156] ; (8017840 <tcp_send_empty_ack+0xbc>)
|
|
80177a2: 4828 ldr r0, [pc, #160] ; (8017844 <tcp_send_empty_ack+0xc0>)
|
|
80177a4: f005 fa88 bl 801ccb8 <iprintf>
|
|
#if LWIP_TCP_TIMESTAMPS
|
|
if (pcb->flags & TF_TIMESTAMP) {
|
|
optflags = TF_SEG_OPTS_TS;
|
|
}
|
|
#endif
|
|
optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb);
|
|
80177a8: 7dfb ldrb r3, [r7, #23]
|
|
80177aa: 009b lsls r3, r3, #2
|
|
80177ac: b2db uxtb r3, r3
|
|
80177ae: f003 0304 and.w r3, r3, #4
|
|
80177b2: 757b strb r3, [r7, #21]
|
|
if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) {
|
|
optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */
|
|
}
|
|
#endif
|
|
|
|
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt));
|
|
80177b4: 7d7b ldrb r3, [r7, #21]
|
|
80177b6: b29c uxth r4, r3
|
|
80177b8: 687b ldr r3, [r7, #4]
|
|
80177ba: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
80177bc: 4618 mov r0, r3
|
|
80177be: f7f9 f9ac bl 8010b1a <lwip_htonl>
|
|
80177c2: 4603 mov r3, r0
|
|
80177c4: 2200 movs r2, #0
|
|
80177c6: 4621 mov r1, r4
|
|
80177c8: 6878 ldr r0, [r7, #4]
|
|
80177ca: f7ff fec1 bl 8017550 <tcp_output_alloc_header>
|
|
80177ce: 6138 str r0, [r7, #16]
|
|
if (p == NULL) {
|
|
80177d0: 693b ldr r3, [r7, #16]
|
|
80177d2: 2b00 cmp r3, #0
|
|
80177d4: d109 bne.n 80177ea <tcp_send_empty_ack+0x66>
|
|
/* let tcp_fasttmr retry sending this ACK */
|
|
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
|
|
80177d6: 687b ldr r3, [r7, #4]
|
|
80177d8: 8b5b ldrh r3, [r3, #26]
|
|
80177da: f043 0303 orr.w r3, r3, #3
|
|
80177de: b29a uxth r2, r3
|
|
80177e0: 687b ldr r3, [r7, #4]
|
|
80177e2: 835a strh r2, [r3, #26]
|
|
LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n"));
|
|
return ERR_BUF;
|
|
80177e4: f06f 0301 mvn.w r3, #1
|
|
80177e8: e023 b.n 8017832 <tcp_send_empty_ack+0xae>
|
|
}
|
|
tcp_output_fill_options(pcb, p, optflags, num_sacks);
|
|
80177ea: 7dbb ldrb r3, [r7, #22]
|
|
80177ec: 7dfa ldrb r2, [r7, #23]
|
|
80177ee: 6939 ldr r1, [r7, #16]
|
|
80177f0: 6878 ldr r0, [r7, #4]
|
|
80177f2: f7ff feeb bl 80175cc <tcp_output_fill_options>
|
|
pcb->ts_lastacksent = pcb->rcv_nxt;
|
|
#endif
|
|
|
|
LWIP_DEBUGF(TCP_OUTPUT_DEBUG,
|
|
("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt));
|
|
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
|
|
80177f6: 687a ldr r2, [r7, #4]
|
|
80177f8: 687b ldr r3, [r7, #4]
|
|
80177fa: 3304 adds r3, #4
|
|
80177fc: 6939 ldr r1, [r7, #16]
|
|
80177fe: 6878 ldr r0, [r7, #4]
|
|
8017800: f7ff ff24 bl 801764c <tcp_output_control_segment>
|
|
8017804: 4603 mov r3, r0
|
|
8017806: 73fb strb r3, [r7, #15]
|
|
if (err != ERR_OK) {
|
|
8017808: f997 300f ldrsb.w r3, [r7, #15]
|
|
801780c: 2b00 cmp r3, #0
|
|
801780e: d007 beq.n 8017820 <tcp_send_empty_ack+0x9c>
|
|
/* let tcp_fasttmr retry sending this ACK */
|
|
tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
|
|
8017810: 687b ldr r3, [r7, #4]
|
|
8017812: 8b5b ldrh r3, [r3, #26]
|
|
8017814: f043 0303 orr.w r3, r3, #3
|
|
8017818: b29a uxth r2, r3
|
|
801781a: 687b ldr r3, [r7, #4]
|
|
801781c: 835a strh r2, [r3, #26]
|
|
801781e: e006 b.n 801782e <tcp_send_empty_ack+0xaa>
|
|
} else {
|
|
/* remove ACK flags from the PCB, as we sent an empty ACK now */
|
|
tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW);
|
|
8017820: 687b ldr r3, [r7, #4]
|
|
8017822: 8b5b ldrh r3, [r3, #26]
|
|
8017824: f023 0303 bic.w r3, r3, #3
|
|
8017828: b29a uxth r2, r3
|
|
801782a: 687b ldr r3, [r7, #4]
|
|
801782c: 835a strh r2, [r3, #26]
|
|
}
|
|
|
|
return err;
|
|
801782e: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
8017832: 4618 mov r0, r3
|
|
8017834: 371c adds r7, #28
|
|
8017836: 46bd mov sp, r7
|
|
8017838: bd90 pop {r4, r7, pc}
|
|
801783a: bf00 nop
|
|
801783c: 0801f730 .word 0x0801f730
|
|
8017840: 0801feec .word 0x0801feec
|
|
8017844: 0801f784 .word 0x0801f784
|
|
|
|
08017848 <tcp_keepalive>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to send a keepalive packet
|
|
*/
|
|
err_t
|
|
tcp_keepalive(struct tcp_pcb *pcb)
|
|
{
|
|
8017848: b590 push {r4, r7, lr}
|
|
801784a: b087 sub sp, #28
|
|
801784c: af00 add r7, sp, #0
|
|
801784e: 6078 str r0, [r7, #4]
|
|
err_t err;
|
|
struct pbuf *p;
|
|
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
|
|
8017850: 2300 movs r3, #0
|
|
8017852: 75fb strb r3, [r7, #23]
|
|
|
|
LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL);
|
|
8017854: 687b ldr r3, [r7, #4]
|
|
8017856: 2b00 cmp r3, #0
|
|
8017858: d106 bne.n 8017868 <tcp_keepalive+0x20>
|
|
801785a: 4b18 ldr r3, [pc, #96] ; (80178bc <tcp_keepalive+0x74>)
|
|
801785c: f640 0224 movw r2, #2084 ; 0x824
|
|
8017860: 4917 ldr r1, [pc, #92] ; (80178c0 <tcp_keepalive+0x78>)
|
|
8017862: 4818 ldr r0, [pc, #96] ; (80178c4 <tcp_keepalive+0x7c>)
|
|
8017864: f005 fa28 bl 801ccb8 <iprintf>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("\n"));
|
|
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
|
|
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
|
|
|
|
p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1));
|
|
8017868: 7dfb ldrb r3, [r7, #23]
|
|
801786a: b29c uxth r4, r3
|
|
801786c: 687b ldr r3, [r7, #4]
|
|
801786e: 6d1b ldr r3, [r3, #80] ; 0x50
|
|
8017870: 3b01 subs r3, #1
|
|
8017872: 4618 mov r0, r3
|
|
8017874: f7f9 f951 bl 8010b1a <lwip_htonl>
|
|
8017878: 4603 mov r3, r0
|
|
801787a: 2200 movs r2, #0
|
|
801787c: 4621 mov r1, r4
|
|
801787e: 6878 ldr r0, [r7, #4]
|
|
8017880: f7ff fe66 bl 8017550 <tcp_output_alloc_header>
|
|
8017884: 6138 str r0, [r7, #16]
|
|
if (p == NULL) {
|
|
8017886: 693b ldr r3, [r7, #16]
|
|
8017888: 2b00 cmp r3, #0
|
|
801788a: d102 bne.n 8017892 <tcp_keepalive+0x4a>
|
|
LWIP_DEBUGF(TCP_DEBUG,
|
|
("tcp_keepalive: could not allocate memory for pbuf\n"));
|
|
return ERR_MEM;
|
|
801788c: f04f 33ff mov.w r3, #4294967295
|
|
8017890: e010 b.n 80178b4 <tcp_keepalive+0x6c>
|
|
}
|
|
tcp_output_fill_options(pcb, p, 0, optlen);
|
|
8017892: 7dfb ldrb r3, [r7, #23]
|
|
8017894: 2200 movs r2, #0
|
|
8017896: 6939 ldr r1, [r7, #16]
|
|
8017898: 6878 ldr r0, [r7, #4]
|
|
801789a: f7ff fe97 bl 80175cc <tcp_output_fill_options>
|
|
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
|
|
801789e: 687a ldr r2, [r7, #4]
|
|
80178a0: 687b ldr r3, [r7, #4]
|
|
80178a2: 3304 adds r3, #4
|
|
80178a4: 6939 ldr r1, [r7, #16]
|
|
80178a6: 6878 ldr r0, [r7, #4]
|
|
80178a8: f7ff fed0 bl 801764c <tcp_output_control_segment>
|
|
80178ac: 4603 mov r3, r0
|
|
80178ae: 73fb strb r3, [r7, #15]
|
|
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n",
|
|
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
|
|
return err;
|
|
80178b0: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
80178b4: 4618 mov r0, r3
|
|
80178b6: 371c adds r7, #28
|
|
80178b8: 46bd mov sp, r7
|
|
80178ba: bd90 pop {r4, r7, pc}
|
|
80178bc: 0801f730 .word 0x0801f730
|
|
80178c0: 0801ff0c .word 0x0801ff0c
|
|
80178c4: 0801f784 .word 0x0801f784
|
|
|
|
080178c8 <tcp_zero_window_probe>:
|
|
*
|
|
* @param pcb the tcp_pcb for which to send a zero-window probe packet
|
|
*/
|
|
err_t
|
|
tcp_zero_window_probe(struct tcp_pcb *pcb)
|
|
{
|
|
80178c8: b590 push {r4, r7, lr}
|
|
80178ca: b08b sub sp, #44 ; 0x2c
|
|
80178cc: af00 add r7, sp, #0
|
|
80178ce: 6078 str r0, [r7, #4]
|
|
struct tcp_hdr *tcphdr;
|
|
struct tcp_seg *seg;
|
|
u16_t len;
|
|
u8_t is_fin;
|
|
u32_t snd_nxt;
|
|
u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb);
|
|
80178d0: 2300 movs r3, #0
|
|
80178d2: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
|
|
LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL);
|
|
80178d6: 687b ldr r3, [r7, #4]
|
|
80178d8: 2b00 cmp r3, #0
|
|
80178da: d106 bne.n 80178ea <tcp_zero_window_probe+0x22>
|
|
80178dc: 4b4c ldr r3, [pc, #304] ; (8017a10 <tcp_zero_window_probe+0x148>)
|
|
80178de: f640 024f movw r2, #2127 ; 0x84f
|
|
80178e2: 494c ldr r1, [pc, #304] ; (8017a14 <tcp_zero_window_probe+0x14c>)
|
|
80178e4: 484c ldr r0, [pc, #304] ; (8017a18 <tcp_zero_window_probe+0x150>)
|
|
80178e6: f005 f9e7 bl 801ccb8 <iprintf>
|
|
("tcp_zero_window_probe: tcp_ticks %"U32_F
|
|
" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n",
|
|
tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent));
|
|
|
|
/* Only consider unsent, persist timer should be off when there is data in-flight */
|
|
seg = pcb->unsent;
|
|
80178ea: 687b ldr r3, [r7, #4]
|
|
80178ec: 6edb ldr r3, [r3, #108] ; 0x6c
|
|
80178ee: 623b str r3, [r7, #32]
|
|
if (seg == NULL) {
|
|
80178f0: 6a3b ldr r3, [r7, #32]
|
|
80178f2: 2b00 cmp r3, #0
|
|
80178f4: d101 bne.n 80178fa <tcp_zero_window_probe+0x32>
|
|
/* Not expected, persist timer should be off when the send buffer is empty */
|
|
return ERR_OK;
|
|
80178f6: 2300 movs r3, #0
|
|
80178f8: e086 b.n 8017a08 <tcp_zero_window_probe+0x140>
|
|
|
|
/* increment probe count. NOTE: we record probe even if it fails
|
|
to actually transmit due to an error. This ensures memory exhaustion/
|
|
routing problem doesn't leave a zero-window pcb as an indefinite zombie.
|
|
RTO mechanism has similar behavior, see pcb->nrtx */
|
|
if (pcb->persist_probe < 0xFF) {
|
|
80178fa: 687b ldr r3, [r7, #4]
|
|
80178fc: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
|
|
8017900: 2bff cmp r3, #255 ; 0xff
|
|
8017902: d007 beq.n 8017914 <tcp_zero_window_probe+0x4c>
|
|
++pcb->persist_probe;
|
|
8017904: 687b ldr r3, [r7, #4]
|
|
8017906: f893 309a ldrb.w r3, [r3, #154] ; 0x9a
|
|
801790a: 3301 adds r3, #1
|
|
801790c: b2da uxtb r2, r3
|
|
801790e: 687b ldr r3, [r7, #4]
|
|
8017910: f883 209a strb.w r2, [r3, #154] ; 0x9a
|
|
}
|
|
|
|
is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0);
|
|
8017914: 6a3b ldr r3, [r7, #32]
|
|
8017916: 68db ldr r3, [r3, #12]
|
|
8017918: 899b ldrh r3, [r3, #12]
|
|
801791a: b29b uxth r3, r3
|
|
801791c: 4618 mov r0, r3
|
|
801791e: f7f9 f8e7 bl 8010af0 <lwip_htons>
|
|
8017922: 4603 mov r3, r0
|
|
8017924: b2db uxtb r3, r3
|
|
8017926: f003 0301 and.w r3, r3, #1
|
|
801792a: 2b00 cmp r3, #0
|
|
801792c: d005 beq.n 801793a <tcp_zero_window_probe+0x72>
|
|
801792e: 6a3b ldr r3, [r7, #32]
|
|
8017930: 891b ldrh r3, [r3, #8]
|
|
8017932: 2b00 cmp r3, #0
|
|
8017934: d101 bne.n 801793a <tcp_zero_window_probe+0x72>
|
|
8017936: 2301 movs r3, #1
|
|
8017938: e000 b.n 801793c <tcp_zero_window_probe+0x74>
|
|
801793a: 2300 movs r3, #0
|
|
801793c: 77fb strb r3, [r7, #31]
|
|
/* we want to send one seqno: either FIN or data (no options) */
|
|
len = is_fin ? 0 : 1;
|
|
801793e: 7ffb ldrb r3, [r7, #31]
|
|
8017940: 2b00 cmp r3, #0
|
|
8017942: bf0c ite eq
|
|
8017944: 2301 moveq r3, #1
|
|
8017946: 2300 movne r3, #0
|
|
8017948: b2db uxtb r3, r3
|
|
801794a: 83bb strh r3, [r7, #28]
|
|
|
|
p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno);
|
|
801794c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8017950: b299 uxth r1, r3
|
|
8017952: 6a3b ldr r3, [r7, #32]
|
|
8017954: 68db ldr r3, [r3, #12]
|
|
8017956: 685b ldr r3, [r3, #4]
|
|
8017958: 8bba ldrh r2, [r7, #28]
|
|
801795a: 6878 ldr r0, [r7, #4]
|
|
801795c: f7ff fdf8 bl 8017550 <tcp_output_alloc_header>
|
|
8017960: 61b8 str r0, [r7, #24]
|
|
if (p == NULL) {
|
|
8017962: 69bb ldr r3, [r7, #24]
|
|
8017964: 2b00 cmp r3, #0
|
|
8017966: d102 bne.n 801796e <tcp_zero_window_probe+0xa6>
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n"));
|
|
return ERR_MEM;
|
|
8017968: f04f 33ff mov.w r3, #4294967295
|
|
801796c: e04c b.n 8017a08 <tcp_zero_window_probe+0x140>
|
|
}
|
|
tcphdr = (struct tcp_hdr *)p->payload;
|
|
801796e: 69bb ldr r3, [r7, #24]
|
|
8017970: 685b ldr r3, [r3, #4]
|
|
8017972: 617b str r3, [r7, #20]
|
|
|
|
if (is_fin) {
|
|
8017974: 7ffb ldrb r3, [r7, #31]
|
|
8017976: 2b00 cmp r3, #0
|
|
8017978: d011 beq.n 801799e <tcp_zero_window_probe+0xd6>
|
|
/* FIN segment, no data */
|
|
TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN);
|
|
801797a: 697b ldr r3, [r7, #20]
|
|
801797c: 899b ldrh r3, [r3, #12]
|
|
801797e: b29b uxth r3, r3
|
|
8017980: b21b sxth r3, r3
|
|
8017982: f423 537c bic.w r3, r3, #16128 ; 0x3f00
|
|
8017986: b21c sxth r4, r3
|
|
8017988: 2011 movs r0, #17
|
|
801798a: f7f9 f8b1 bl 8010af0 <lwip_htons>
|
|
801798e: 4603 mov r3, r0
|
|
8017990: b21b sxth r3, r3
|
|
8017992: 4323 orrs r3, r4
|
|
8017994: b21b sxth r3, r3
|
|
8017996: b29a uxth r2, r3
|
|
8017998: 697b ldr r3, [r7, #20]
|
|
801799a: 819a strh r2, [r3, #12]
|
|
801799c: e010 b.n 80179c0 <tcp_zero_window_probe+0xf8>
|
|
} else {
|
|
/* Data segment, copy in one byte from the head of the unacked queue */
|
|
char *d = ((char *)p->payload + TCP_HLEN);
|
|
801799e: 69bb ldr r3, [r7, #24]
|
|
80179a0: 685b ldr r3, [r3, #4]
|
|
80179a2: 3314 adds r3, #20
|
|
80179a4: 613b str r3, [r7, #16]
|
|
/* Depending on whether the segment has already been sent (unacked) or not
|
|
(unsent), seg->p->payload points to the IP header or TCP header.
|
|
Ensure we copy the first TCP data byte: */
|
|
pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len);
|
|
80179a6: 6a3b ldr r3, [r7, #32]
|
|
80179a8: 6858 ldr r0, [r3, #4]
|
|
80179aa: 6a3b ldr r3, [r7, #32]
|
|
80179ac: 685b ldr r3, [r3, #4]
|
|
80179ae: 891a ldrh r2, [r3, #8]
|
|
80179b0: 6a3b ldr r3, [r7, #32]
|
|
80179b2: 891b ldrh r3, [r3, #8]
|
|
80179b4: 1ad3 subs r3, r2, r3
|
|
80179b6: b29b uxth r3, r3
|
|
80179b8: 2201 movs r2, #1
|
|
80179ba: 6939 ldr r1, [r7, #16]
|
|
80179bc: f7fa fe52 bl 8012664 <pbuf_copy_partial>
|
|
}
|
|
|
|
/* The byte may be acknowledged without the window being opened. */
|
|
snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1;
|
|
80179c0: 6a3b ldr r3, [r7, #32]
|
|
80179c2: 68db ldr r3, [r3, #12]
|
|
80179c4: 685b ldr r3, [r3, #4]
|
|
80179c6: 4618 mov r0, r3
|
|
80179c8: f7f9 f8a7 bl 8010b1a <lwip_htonl>
|
|
80179cc: 4603 mov r3, r0
|
|
80179ce: 3301 adds r3, #1
|
|
80179d0: 60fb str r3, [r7, #12]
|
|
if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) {
|
|
80179d2: 687b ldr r3, [r7, #4]
|
|
80179d4: 6d1a ldr r2, [r3, #80] ; 0x50
|
|
80179d6: 68fb ldr r3, [r7, #12]
|
|
80179d8: 1ad3 subs r3, r2, r3
|
|
80179da: 2b00 cmp r3, #0
|
|
80179dc: da02 bge.n 80179e4 <tcp_zero_window_probe+0x11c>
|
|
pcb->snd_nxt = snd_nxt;
|
|
80179de: 687b ldr r3, [r7, #4]
|
|
80179e0: 68fa ldr r2, [r7, #12]
|
|
80179e2: 651a str r2, [r3, #80] ; 0x50
|
|
}
|
|
tcp_output_fill_options(pcb, p, 0, optlen);
|
|
80179e4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
80179e8: 2200 movs r2, #0
|
|
80179ea: 69b9 ldr r1, [r7, #24]
|
|
80179ec: 6878 ldr r0, [r7, #4]
|
|
80179ee: f7ff fded bl 80175cc <tcp_output_fill_options>
|
|
|
|
err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip);
|
|
80179f2: 687a ldr r2, [r7, #4]
|
|
80179f4: 687b ldr r3, [r7, #4]
|
|
80179f6: 3304 adds r3, #4
|
|
80179f8: 69b9 ldr r1, [r7, #24]
|
|
80179fa: 6878 ldr r0, [r7, #4]
|
|
80179fc: f7ff fe26 bl 801764c <tcp_output_control_segment>
|
|
8017a00: 4603 mov r3, r0
|
|
8017a02: 72fb strb r3, [r7, #11]
|
|
|
|
LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F
|
|
" ackno %"U32_F" err %d.\n",
|
|
pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err));
|
|
return err;
|
|
8017a04: f997 300b ldrsb.w r3, [r7, #11]
|
|
}
|
|
8017a08: 4618 mov r0, r3
|
|
8017a0a: 372c adds r7, #44 ; 0x2c
|
|
8017a0c: 46bd mov sp, r7
|
|
8017a0e: bd90 pop {r4, r7, pc}
|
|
8017a10: 0801f730 .word 0x0801f730
|
|
8017a14: 0801ff28 .word 0x0801ff28
|
|
8017a18: 0801f784 .word 0x0801f784
|
|
|
|
08017a1c <tcpip_tcp_timer>:
|
|
*
|
|
* @param arg unused argument
|
|
*/
|
|
static void
|
|
tcpip_tcp_timer(void *arg)
|
|
{
|
|
8017a1c: b580 push {r7, lr}
|
|
8017a1e: b082 sub sp, #8
|
|
8017a20: af00 add r7, sp, #0
|
|
8017a22: 6078 str r0, [r7, #4]
|
|
LWIP_UNUSED_ARG(arg);
|
|
|
|
/* call TCP timer handler */
|
|
tcp_tmr();
|
|
8017a24: f7fa ff0c bl 8012840 <tcp_tmr>
|
|
/* timer still needed? */
|
|
if (tcp_active_pcbs || tcp_tw_pcbs) {
|
|
8017a28: 4b0a ldr r3, [pc, #40] ; (8017a54 <tcpip_tcp_timer+0x38>)
|
|
8017a2a: 681b ldr r3, [r3, #0]
|
|
8017a2c: 2b00 cmp r3, #0
|
|
8017a2e: d103 bne.n 8017a38 <tcpip_tcp_timer+0x1c>
|
|
8017a30: 4b09 ldr r3, [pc, #36] ; (8017a58 <tcpip_tcp_timer+0x3c>)
|
|
8017a32: 681b ldr r3, [r3, #0]
|
|
8017a34: 2b00 cmp r3, #0
|
|
8017a36: d005 beq.n 8017a44 <tcpip_tcp_timer+0x28>
|
|
/* restart timer */
|
|
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
|
|
8017a38: 2200 movs r2, #0
|
|
8017a3a: 4908 ldr r1, [pc, #32] ; (8017a5c <tcpip_tcp_timer+0x40>)
|
|
8017a3c: 20fa movs r0, #250 ; 0xfa
|
|
8017a3e: f000 f8f1 bl 8017c24 <sys_timeout>
|
|
8017a42: e002 b.n 8017a4a <tcpip_tcp_timer+0x2e>
|
|
} else {
|
|
/* disable timer */
|
|
tcpip_tcp_timer_active = 0;
|
|
8017a44: 4b06 ldr r3, [pc, #24] ; (8017a60 <tcpip_tcp_timer+0x44>)
|
|
8017a46: 2200 movs r2, #0
|
|
8017a48: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
8017a4a: bf00 nop
|
|
8017a4c: 3708 adds r7, #8
|
|
8017a4e: 46bd mov sp, r7
|
|
8017a50: bd80 pop {r7, pc}
|
|
8017a52: bf00 nop
|
|
8017a54: 2000f7fc .word 0x2000f7fc
|
|
8017a58: 2000f80c .word 0x2000f80c
|
|
8017a5c: 08017a1d .word 0x08017a1d
|
|
8017a60: 20008768 .word 0x20008768
|
|
|
|
08017a64 <tcp_timer_needed>:
|
|
* the reason is to have the TCP timer only running when
|
|
* there are active (or time-wait) PCBs.
|
|
*/
|
|
void
|
|
tcp_timer_needed(void)
|
|
{
|
|
8017a64: b580 push {r7, lr}
|
|
8017a66: af00 add r7, sp, #0
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
/* timer is off but needed again? */
|
|
if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) {
|
|
8017a68: 4b0a ldr r3, [pc, #40] ; (8017a94 <tcp_timer_needed+0x30>)
|
|
8017a6a: 681b ldr r3, [r3, #0]
|
|
8017a6c: 2b00 cmp r3, #0
|
|
8017a6e: d10f bne.n 8017a90 <tcp_timer_needed+0x2c>
|
|
8017a70: 4b09 ldr r3, [pc, #36] ; (8017a98 <tcp_timer_needed+0x34>)
|
|
8017a72: 681b ldr r3, [r3, #0]
|
|
8017a74: 2b00 cmp r3, #0
|
|
8017a76: d103 bne.n 8017a80 <tcp_timer_needed+0x1c>
|
|
8017a78: 4b08 ldr r3, [pc, #32] ; (8017a9c <tcp_timer_needed+0x38>)
|
|
8017a7a: 681b ldr r3, [r3, #0]
|
|
8017a7c: 2b00 cmp r3, #0
|
|
8017a7e: d007 beq.n 8017a90 <tcp_timer_needed+0x2c>
|
|
/* enable and start timer */
|
|
tcpip_tcp_timer_active = 1;
|
|
8017a80: 4b04 ldr r3, [pc, #16] ; (8017a94 <tcp_timer_needed+0x30>)
|
|
8017a82: 2201 movs r2, #1
|
|
8017a84: 601a str r2, [r3, #0]
|
|
sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL);
|
|
8017a86: 2200 movs r2, #0
|
|
8017a88: 4905 ldr r1, [pc, #20] ; (8017aa0 <tcp_timer_needed+0x3c>)
|
|
8017a8a: 20fa movs r0, #250 ; 0xfa
|
|
8017a8c: f000 f8ca bl 8017c24 <sys_timeout>
|
|
}
|
|
}
|
|
8017a90: bf00 nop
|
|
8017a92: bd80 pop {r7, pc}
|
|
8017a94: 20008768 .word 0x20008768
|
|
8017a98: 2000f7fc .word 0x2000f7fc
|
|
8017a9c: 2000f80c .word 0x2000f80c
|
|
8017aa0: 08017a1d .word 0x08017a1d
|
|
|
|
08017aa4 <sys_timeout_abs>:
|
|
#if LWIP_DEBUG_TIMERNAMES
|
|
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name)
|
|
#else /* LWIP_DEBUG_TIMERNAMES */
|
|
sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg)
|
|
#endif
|
|
{
|
|
8017aa4: b580 push {r7, lr}
|
|
8017aa6: b086 sub sp, #24
|
|
8017aa8: af00 add r7, sp, #0
|
|
8017aaa: 60f8 str r0, [r7, #12]
|
|
8017aac: 60b9 str r1, [r7, #8]
|
|
8017aae: 607a str r2, [r7, #4]
|
|
struct sys_timeo *timeout, *t;
|
|
|
|
timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT);
|
|
8017ab0: 200a movs r0, #10
|
|
8017ab2: f7f9 fcd3 bl 801145c <memp_malloc>
|
|
8017ab6: 6138 str r0, [r7, #16]
|
|
if (timeout == NULL) {
|
|
8017ab8: 693b ldr r3, [r7, #16]
|
|
8017aba: 2b00 cmp r3, #0
|
|
8017abc: d109 bne.n 8017ad2 <sys_timeout_abs+0x2e>
|
|
LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL);
|
|
8017abe: 693b ldr r3, [r7, #16]
|
|
8017ac0: 2b00 cmp r3, #0
|
|
8017ac2: d151 bne.n 8017b68 <sys_timeout_abs+0xc4>
|
|
8017ac4: 4b2a ldr r3, [pc, #168] ; (8017b70 <sys_timeout_abs+0xcc>)
|
|
8017ac6: 22be movs r2, #190 ; 0xbe
|
|
8017ac8: 492a ldr r1, [pc, #168] ; (8017b74 <sys_timeout_abs+0xd0>)
|
|
8017aca: 482b ldr r0, [pc, #172] ; (8017b78 <sys_timeout_abs+0xd4>)
|
|
8017acc: f005 f8f4 bl 801ccb8 <iprintf>
|
|
return;
|
|
8017ad0: e04a b.n 8017b68 <sys_timeout_abs+0xc4>
|
|
}
|
|
|
|
timeout->next = NULL;
|
|
8017ad2: 693b ldr r3, [r7, #16]
|
|
8017ad4: 2200 movs r2, #0
|
|
8017ad6: 601a str r2, [r3, #0]
|
|
timeout->h = handler;
|
|
8017ad8: 693b ldr r3, [r7, #16]
|
|
8017ada: 68ba ldr r2, [r7, #8]
|
|
8017adc: 609a str r2, [r3, #8]
|
|
timeout->arg = arg;
|
|
8017ade: 693b ldr r3, [r7, #16]
|
|
8017ae0: 687a ldr r2, [r7, #4]
|
|
8017ae2: 60da str r2, [r3, #12]
|
|
timeout->time = abs_time;
|
|
8017ae4: 693b ldr r3, [r7, #16]
|
|
8017ae6: 68fa ldr r2, [r7, #12]
|
|
8017ae8: 605a str r2, [r3, #4]
|
|
timeout->handler_name = handler_name;
|
|
LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n",
|
|
(void *)timeout, abs_time, handler_name, (void *)arg));
|
|
#endif /* LWIP_DEBUG_TIMERNAMES */
|
|
|
|
if (next_timeout == NULL) {
|
|
8017aea: 4b24 ldr r3, [pc, #144] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017aec: 681b ldr r3, [r3, #0]
|
|
8017aee: 2b00 cmp r3, #0
|
|
8017af0: d103 bne.n 8017afa <sys_timeout_abs+0x56>
|
|
next_timeout = timeout;
|
|
8017af2: 4a22 ldr r2, [pc, #136] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017af4: 693b ldr r3, [r7, #16]
|
|
8017af6: 6013 str r3, [r2, #0]
|
|
return;
|
|
8017af8: e037 b.n 8017b6a <sys_timeout_abs+0xc6>
|
|
}
|
|
if (TIME_LESS_THAN(timeout->time, next_timeout->time)) {
|
|
8017afa: 693b ldr r3, [r7, #16]
|
|
8017afc: 685a ldr r2, [r3, #4]
|
|
8017afe: 4b1f ldr r3, [pc, #124] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017b00: 681b ldr r3, [r3, #0]
|
|
8017b02: 685b ldr r3, [r3, #4]
|
|
8017b04: 1ad3 subs r3, r2, r3
|
|
8017b06: 0fdb lsrs r3, r3, #31
|
|
8017b08: f003 0301 and.w r3, r3, #1
|
|
8017b0c: b2db uxtb r3, r3
|
|
8017b0e: 2b00 cmp r3, #0
|
|
8017b10: d007 beq.n 8017b22 <sys_timeout_abs+0x7e>
|
|
timeout->next = next_timeout;
|
|
8017b12: 4b1a ldr r3, [pc, #104] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017b14: 681a ldr r2, [r3, #0]
|
|
8017b16: 693b ldr r3, [r7, #16]
|
|
8017b18: 601a str r2, [r3, #0]
|
|
next_timeout = timeout;
|
|
8017b1a: 4a18 ldr r2, [pc, #96] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017b1c: 693b ldr r3, [r7, #16]
|
|
8017b1e: 6013 str r3, [r2, #0]
|
|
8017b20: e023 b.n 8017b6a <sys_timeout_abs+0xc6>
|
|
} else {
|
|
for (t = next_timeout; t != NULL; t = t->next) {
|
|
8017b22: 4b16 ldr r3, [pc, #88] ; (8017b7c <sys_timeout_abs+0xd8>)
|
|
8017b24: 681b ldr r3, [r3, #0]
|
|
8017b26: 617b str r3, [r7, #20]
|
|
8017b28: e01a b.n 8017b60 <sys_timeout_abs+0xbc>
|
|
if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) {
|
|
8017b2a: 697b ldr r3, [r7, #20]
|
|
8017b2c: 681b ldr r3, [r3, #0]
|
|
8017b2e: 2b00 cmp r3, #0
|
|
8017b30: d00b beq.n 8017b4a <sys_timeout_abs+0xa6>
|
|
8017b32: 693b ldr r3, [r7, #16]
|
|
8017b34: 685a ldr r2, [r3, #4]
|
|
8017b36: 697b ldr r3, [r7, #20]
|
|
8017b38: 681b ldr r3, [r3, #0]
|
|
8017b3a: 685b ldr r3, [r3, #4]
|
|
8017b3c: 1ad3 subs r3, r2, r3
|
|
8017b3e: 0fdb lsrs r3, r3, #31
|
|
8017b40: f003 0301 and.w r3, r3, #1
|
|
8017b44: b2db uxtb r3, r3
|
|
8017b46: 2b00 cmp r3, #0
|
|
8017b48: d007 beq.n 8017b5a <sys_timeout_abs+0xb6>
|
|
timeout->next = t->next;
|
|
8017b4a: 697b ldr r3, [r7, #20]
|
|
8017b4c: 681a ldr r2, [r3, #0]
|
|
8017b4e: 693b ldr r3, [r7, #16]
|
|
8017b50: 601a str r2, [r3, #0]
|
|
t->next = timeout;
|
|
8017b52: 697b ldr r3, [r7, #20]
|
|
8017b54: 693a ldr r2, [r7, #16]
|
|
8017b56: 601a str r2, [r3, #0]
|
|
break;
|
|
8017b58: e007 b.n 8017b6a <sys_timeout_abs+0xc6>
|
|
for (t = next_timeout; t != NULL; t = t->next) {
|
|
8017b5a: 697b ldr r3, [r7, #20]
|
|
8017b5c: 681b ldr r3, [r3, #0]
|
|
8017b5e: 617b str r3, [r7, #20]
|
|
8017b60: 697b ldr r3, [r7, #20]
|
|
8017b62: 2b00 cmp r3, #0
|
|
8017b64: d1e1 bne.n 8017b2a <sys_timeout_abs+0x86>
|
|
8017b66: e000 b.n 8017b6a <sys_timeout_abs+0xc6>
|
|
return;
|
|
8017b68: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8017b6a: 3718 adds r7, #24
|
|
8017b6c: 46bd mov sp, r7
|
|
8017b6e: bd80 pop {r7, pc}
|
|
8017b70: 0801ff4c .word 0x0801ff4c
|
|
8017b74: 0801ff80 .word 0x0801ff80
|
|
8017b78: 0801ffc0 .word 0x0801ffc0
|
|
8017b7c: 20008760 .word 0x20008760
|
|
|
|
08017b80 <lwip_cyclic_timer>:
|
|
#if !LWIP_TESTMODE
|
|
static
|
|
#endif
|
|
void
|
|
lwip_cyclic_timer(void *arg)
|
|
{
|
|
8017b80: b580 push {r7, lr}
|
|
8017b82: b086 sub sp, #24
|
|
8017b84: af00 add r7, sp, #0
|
|
8017b86: 6078 str r0, [r7, #4]
|
|
u32_t now;
|
|
u32_t next_timeout_time;
|
|
const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg;
|
|
8017b88: 687b ldr r3, [r7, #4]
|
|
8017b8a: 617b str r3, [r7, #20]
|
|
|
|
#if LWIP_DEBUG_TIMERNAMES
|
|
LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name));
|
|
#endif
|
|
cyclic->handler();
|
|
8017b8c: 697b ldr r3, [r7, #20]
|
|
8017b8e: 685b ldr r3, [r3, #4]
|
|
8017b90: 4798 blx r3
|
|
|
|
now = sys_now();
|
|
8017b92: f7f5 fc59 bl 800d448 <sys_now>
|
|
8017b96: 6138 str r0, [r7, #16]
|
|
next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */
|
|
8017b98: 697b ldr r3, [r7, #20]
|
|
8017b9a: 681a ldr r2, [r3, #0]
|
|
8017b9c: 4b0f ldr r3, [pc, #60] ; (8017bdc <lwip_cyclic_timer+0x5c>)
|
|
8017b9e: 681b ldr r3, [r3, #0]
|
|
8017ba0: 4413 add r3, r2
|
|
8017ba2: 60fb str r3, [r7, #12]
|
|
if (TIME_LESS_THAN(next_timeout_time, now)) {
|
|
8017ba4: 68fa ldr r2, [r7, #12]
|
|
8017ba6: 693b ldr r3, [r7, #16]
|
|
8017ba8: 1ad3 subs r3, r2, r3
|
|
8017baa: 0fdb lsrs r3, r3, #31
|
|
8017bac: f003 0301 and.w r3, r3, #1
|
|
8017bb0: b2db uxtb r3, r3
|
|
8017bb2: 2b00 cmp r3, #0
|
|
8017bb4: d009 beq.n 8017bca <lwip_cyclic_timer+0x4a>
|
|
/* timer would immediately expire again -> "overload" -> restart without any correction */
|
|
#if LWIP_DEBUG_TIMERNAMES
|
|
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name);
|
|
#else
|
|
sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg);
|
|
8017bb6: 697b ldr r3, [r7, #20]
|
|
8017bb8: 681a ldr r2, [r3, #0]
|
|
8017bba: 693b ldr r3, [r7, #16]
|
|
8017bbc: 4413 add r3, r2
|
|
8017bbe: 687a ldr r2, [r7, #4]
|
|
8017bc0: 4907 ldr r1, [pc, #28] ; (8017be0 <lwip_cyclic_timer+0x60>)
|
|
8017bc2: 4618 mov r0, r3
|
|
8017bc4: f7ff ff6e bl 8017aa4 <sys_timeout_abs>
|
|
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name);
|
|
#else
|
|
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
|
|
#endif
|
|
}
|
|
}
|
|
8017bc8: e004 b.n 8017bd4 <lwip_cyclic_timer+0x54>
|
|
sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg);
|
|
8017bca: 687a ldr r2, [r7, #4]
|
|
8017bcc: 4904 ldr r1, [pc, #16] ; (8017be0 <lwip_cyclic_timer+0x60>)
|
|
8017bce: 68f8 ldr r0, [r7, #12]
|
|
8017bd0: f7ff ff68 bl 8017aa4 <sys_timeout_abs>
|
|
}
|
|
8017bd4: bf00 nop
|
|
8017bd6: 3718 adds r7, #24
|
|
8017bd8: 46bd mov sp, r7
|
|
8017bda: bd80 pop {r7, pc}
|
|
8017bdc: 20008764 .word 0x20008764
|
|
8017be0: 08017b81 .word 0x08017b81
|
|
|
|
08017be4 <sys_timeouts_init>:
|
|
|
|
/** Initialize this module */
|
|
void sys_timeouts_init(void)
|
|
{
|
|
8017be4: b580 push {r7, lr}
|
|
8017be6: b082 sub sp, #8
|
|
8017be8: af00 add r7, sp, #0
|
|
size_t i;
|
|
/* tcp_tmr() at index 0 is started on demand */
|
|
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
|
|
8017bea: 2301 movs r3, #1
|
|
8017bec: 607b str r3, [r7, #4]
|
|
8017bee: e00e b.n 8017c0e <sys_timeouts_init+0x2a>
|
|
/* we have to cast via size_t to get rid of const warning
|
|
(this is OK as cyclic_timer() casts back to const* */
|
|
sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i]));
|
|
8017bf0: 4a0a ldr r2, [pc, #40] ; (8017c1c <sys_timeouts_init+0x38>)
|
|
8017bf2: 687b ldr r3, [r7, #4]
|
|
8017bf4: f852 0033 ldr.w r0, [r2, r3, lsl #3]
|
|
8017bf8: 687b ldr r3, [r7, #4]
|
|
8017bfa: 00db lsls r3, r3, #3
|
|
8017bfc: 4a07 ldr r2, [pc, #28] ; (8017c1c <sys_timeouts_init+0x38>)
|
|
8017bfe: 4413 add r3, r2
|
|
8017c00: 461a mov r2, r3
|
|
8017c02: 4907 ldr r1, [pc, #28] ; (8017c20 <sys_timeouts_init+0x3c>)
|
|
8017c04: f000 f80e bl 8017c24 <sys_timeout>
|
|
for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) {
|
|
8017c08: 687b ldr r3, [r7, #4]
|
|
8017c0a: 3301 adds r3, #1
|
|
8017c0c: 607b str r3, [r7, #4]
|
|
8017c0e: 687b ldr r3, [r7, #4]
|
|
8017c10: 2b04 cmp r3, #4
|
|
8017c12: d9ed bls.n 8017bf0 <sys_timeouts_init+0xc>
|
|
}
|
|
}
|
|
8017c14: bf00 nop
|
|
8017c16: 3708 adds r7, #8
|
|
8017c18: 46bd mov sp, r7
|
|
8017c1a: bd80 pop {r7, pc}
|
|
8017c1c: 08022e40 .word 0x08022e40
|
|
8017c20: 08017b81 .word 0x08017b81
|
|
|
|
08017c24 <sys_timeout>:
|
|
sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name)
|
|
#else /* LWIP_DEBUG_TIMERNAMES */
|
|
void
|
|
sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg)
|
|
#endif /* LWIP_DEBUG_TIMERNAMES */
|
|
{
|
|
8017c24: b580 push {r7, lr}
|
|
8017c26: b086 sub sp, #24
|
|
8017c28: af00 add r7, sp, #0
|
|
8017c2a: 60f8 str r0, [r7, #12]
|
|
8017c2c: 60b9 str r1, [r7, #8]
|
|
8017c2e: 607a str r2, [r7, #4]
|
|
u32_t next_timeout_time;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4));
|
|
8017c30: 68fb ldr r3, [r7, #12]
|
|
8017c32: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
|
|
8017c36: d306 bcc.n 8017c46 <sys_timeout+0x22>
|
|
8017c38: 4b0a ldr r3, [pc, #40] ; (8017c64 <sys_timeout+0x40>)
|
|
8017c3a: f240 1229 movw r2, #297 ; 0x129
|
|
8017c3e: 490a ldr r1, [pc, #40] ; (8017c68 <sys_timeout+0x44>)
|
|
8017c40: 480a ldr r0, [pc, #40] ; (8017c6c <sys_timeout+0x48>)
|
|
8017c42: f005 f839 bl 801ccb8 <iprintf>
|
|
|
|
next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */
|
|
8017c46: f7f5 fbff bl 800d448 <sys_now>
|
|
8017c4a: 4602 mov r2, r0
|
|
8017c4c: 68fb ldr r3, [r7, #12]
|
|
8017c4e: 4413 add r3, r2
|
|
8017c50: 617b str r3, [r7, #20]
|
|
|
|
#if LWIP_DEBUG_TIMERNAMES
|
|
sys_timeout_abs(next_timeout_time, handler, arg, handler_name);
|
|
#else
|
|
sys_timeout_abs(next_timeout_time, handler, arg);
|
|
8017c52: 687a ldr r2, [r7, #4]
|
|
8017c54: 68b9 ldr r1, [r7, #8]
|
|
8017c56: 6978 ldr r0, [r7, #20]
|
|
8017c58: f7ff ff24 bl 8017aa4 <sys_timeout_abs>
|
|
#endif
|
|
}
|
|
8017c5c: bf00 nop
|
|
8017c5e: 3718 adds r7, #24
|
|
8017c60: 46bd mov sp, r7
|
|
8017c62: bd80 pop {r7, pc}
|
|
8017c64: 0801ff4c .word 0x0801ff4c
|
|
8017c68: 0801ffe8 .word 0x0801ffe8
|
|
8017c6c: 0801ffc0 .word 0x0801ffc0
|
|
|
|
08017c70 <sys_check_timeouts>:
|
|
*
|
|
* Must be called periodically from your main loop.
|
|
*/
|
|
void
|
|
sys_check_timeouts(void)
|
|
{
|
|
8017c70: b580 push {r7, lr}
|
|
8017c72: b084 sub sp, #16
|
|
8017c74: af00 add r7, sp, #0
|
|
u32_t now;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
/* Process only timers expired at the start of the function. */
|
|
now = sys_now();
|
|
8017c76: f7f5 fbe7 bl 800d448 <sys_now>
|
|
8017c7a: 60f8 str r0, [r7, #12]
|
|
sys_timeout_handler handler;
|
|
void *arg;
|
|
|
|
PBUF_CHECK_FREE_OOSEQ();
|
|
|
|
tmptimeout = next_timeout;
|
|
8017c7c: 4b17 ldr r3, [pc, #92] ; (8017cdc <sys_check_timeouts+0x6c>)
|
|
8017c7e: 681b ldr r3, [r3, #0]
|
|
8017c80: 60bb str r3, [r7, #8]
|
|
if (tmptimeout == NULL) {
|
|
8017c82: 68bb ldr r3, [r7, #8]
|
|
8017c84: 2b00 cmp r3, #0
|
|
8017c86: d022 beq.n 8017cce <sys_check_timeouts+0x5e>
|
|
return;
|
|
}
|
|
|
|
if (TIME_LESS_THAN(now, tmptimeout->time)) {
|
|
8017c88: 68bb ldr r3, [r7, #8]
|
|
8017c8a: 685b ldr r3, [r3, #4]
|
|
8017c8c: 68fa ldr r2, [r7, #12]
|
|
8017c8e: 1ad3 subs r3, r2, r3
|
|
8017c90: 0fdb lsrs r3, r3, #31
|
|
8017c92: f003 0301 and.w r3, r3, #1
|
|
8017c96: b2db uxtb r3, r3
|
|
8017c98: 2b00 cmp r3, #0
|
|
8017c9a: d11a bne.n 8017cd2 <sys_check_timeouts+0x62>
|
|
return;
|
|
}
|
|
|
|
/* Timeout has expired */
|
|
next_timeout = tmptimeout->next;
|
|
8017c9c: 68bb ldr r3, [r7, #8]
|
|
8017c9e: 681b ldr r3, [r3, #0]
|
|
8017ca0: 4a0e ldr r2, [pc, #56] ; (8017cdc <sys_check_timeouts+0x6c>)
|
|
8017ca2: 6013 str r3, [r2, #0]
|
|
handler = tmptimeout->h;
|
|
8017ca4: 68bb ldr r3, [r7, #8]
|
|
8017ca6: 689b ldr r3, [r3, #8]
|
|
8017ca8: 607b str r3, [r7, #4]
|
|
arg = tmptimeout->arg;
|
|
8017caa: 68bb ldr r3, [r7, #8]
|
|
8017cac: 68db ldr r3, [r3, #12]
|
|
8017cae: 603b str r3, [r7, #0]
|
|
current_timeout_due_time = tmptimeout->time;
|
|
8017cb0: 68bb ldr r3, [r7, #8]
|
|
8017cb2: 685b ldr r3, [r3, #4]
|
|
8017cb4: 4a0a ldr r2, [pc, #40] ; (8017ce0 <sys_check_timeouts+0x70>)
|
|
8017cb6: 6013 str r3, [r2, #0]
|
|
if (handler != NULL) {
|
|
LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n",
|
|
tmptimeout->handler_name, sys_now() - tmptimeout->time, arg));
|
|
}
|
|
#endif /* LWIP_DEBUG_TIMERNAMES */
|
|
memp_free(MEMP_SYS_TIMEOUT, tmptimeout);
|
|
8017cb8: 68b9 ldr r1, [r7, #8]
|
|
8017cba: 200a movs r0, #10
|
|
8017cbc: f7f9 fc20 bl 8011500 <memp_free>
|
|
if (handler != NULL) {
|
|
8017cc0: 687b ldr r3, [r7, #4]
|
|
8017cc2: 2b00 cmp r3, #0
|
|
8017cc4: d0da beq.n 8017c7c <sys_check_timeouts+0xc>
|
|
handler(arg);
|
|
8017cc6: 687b ldr r3, [r7, #4]
|
|
8017cc8: 6838 ldr r0, [r7, #0]
|
|
8017cca: 4798 blx r3
|
|
do {
|
|
8017ccc: e7d6 b.n 8017c7c <sys_check_timeouts+0xc>
|
|
return;
|
|
8017cce: bf00 nop
|
|
8017cd0: e000 b.n 8017cd4 <sys_check_timeouts+0x64>
|
|
return;
|
|
8017cd2: bf00 nop
|
|
}
|
|
LWIP_TCPIP_THREAD_ALIVE();
|
|
|
|
/* Repeat until all expired timers have been called */
|
|
} while (1);
|
|
}
|
|
8017cd4: 3710 adds r7, #16
|
|
8017cd6: 46bd mov sp, r7
|
|
8017cd8: bd80 pop {r7, pc}
|
|
8017cda: bf00 nop
|
|
8017cdc: 20008760 .word 0x20008760
|
|
8017ce0: 20008764 .word 0x20008764
|
|
|
|
08017ce4 <sys_timeouts_sleeptime>:
|
|
/** Return the time left before the next timeout is due. If no timeouts are
|
|
* enqueued, returns 0xffffffff
|
|
*/
|
|
u32_t
|
|
sys_timeouts_sleeptime(void)
|
|
{
|
|
8017ce4: b580 push {r7, lr}
|
|
8017ce6: b082 sub sp, #8
|
|
8017ce8: af00 add r7, sp, #0
|
|
u32_t now;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
if (next_timeout == NULL) {
|
|
8017cea: 4b16 ldr r3, [pc, #88] ; (8017d44 <sys_timeouts_sleeptime+0x60>)
|
|
8017cec: 681b ldr r3, [r3, #0]
|
|
8017cee: 2b00 cmp r3, #0
|
|
8017cf0: d102 bne.n 8017cf8 <sys_timeouts_sleeptime+0x14>
|
|
return SYS_TIMEOUTS_SLEEPTIME_INFINITE;
|
|
8017cf2: f04f 33ff mov.w r3, #4294967295
|
|
8017cf6: e020 b.n 8017d3a <sys_timeouts_sleeptime+0x56>
|
|
}
|
|
now = sys_now();
|
|
8017cf8: f7f5 fba6 bl 800d448 <sys_now>
|
|
8017cfc: 6078 str r0, [r7, #4]
|
|
if (TIME_LESS_THAN(next_timeout->time, now)) {
|
|
8017cfe: 4b11 ldr r3, [pc, #68] ; (8017d44 <sys_timeouts_sleeptime+0x60>)
|
|
8017d00: 681b ldr r3, [r3, #0]
|
|
8017d02: 685a ldr r2, [r3, #4]
|
|
8017d04: 687b ldr r3, [r7, #4]
|
|
8017d06: 1ad3 subs r3, r2, r3
|
|
8017d08: 0fdb lsrs r3, r3, #31
|
|
8017d0a: f003 0301 and.w r3, r3, #1
|
|
8017d0e: b2db uxtb r3, r3
|
|
8017d10: 2b00 cmp r3, #0
|
|
8017d12: d001 beq.n 8017d18 <sys_timeouts_sleeptime+0x34>
|
|
return 0;
|
|
8017d14: 2300 movs r3, #0
|
|
8017d16: e010 b.n 8017d3a <sys_timeouts_sleeptime+0x56>
|
|
} else {
|
|
u32_t ret = (u32_t)(next_timeout->time - now);
|
|
8017d18: 4b0a ldr r3, [pc, #40] ; (8017d44 <sys_timeouts_sleeptime+0x60>)
|
|
8017d1a: 681b ldr r3, [r3, #0]
|
|
8017d1c: 685a ldr r2, [r3, #4]
|
|
8017d1e: 687b ldr r3, [r7, #4]
|
|
8017d20: 1ad3 subs r3, r2, r3
|
|
8017d22: 603b str r3, [r7, #0]
|
|
LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT);
|
|
8017d24: 683b ldr r3, [r7, #0]
|
|
8017d26: 2b00 cmp r3, #0
|
|
8017d28: da06 bge.n 8017d38 <sys_timeouts_sleeptime+0x54>
|
|
8017d2a: 4b07 ldr r3, [pc, #28] ; (8017d48 <sys_timeouts_sleeptime+0x64>)
|
|
8017d2c: f44f 72dc mov.w r2, #440 ; 0x1b8
|
|
8017d30: 4906 ldr r1, [pc, #24] ; (8017d4c <sys_timeouts_sleeptime+0x68>)
|
|
8017d32: 4807 ldr r0, [pc, #28] ; (8017d50 <sys_timeouts_sleeptime+0x6c>)
|
|
8017d34: f004 ffc0 bl 801ccb8 <iprintf>
|
|
return ret;
|
|
8017d38: 683b ldr r3, [r7, #0]
|
|
}
|
|
}
|
|
8017d3a: 4618 mov r0, r3
|
|
8017d3c: 3708 adds r7, #8
|
|
8017d3e: 46bd mov sp, r7
|
|
8017d40: bd80 pop {r7, pc}
|
|
8017d42: bf00 nop
|
|
8017d44: 20008760 .word 0x20008760
|
|
8017d48: 0801ff4c .word 0x0801ff4c
|
|
8017d4c: 08020020 .word 0x08020020
|
|
8017d50: 0801ffc0 .word 0x0801ffc0
|
|
|
|
08017d54 <udp_init>:
|
|
/**
|
|
* Initialize this module.
|
|
*/
|
|
void
|
|
udp_init(void)
|
|
{
|
|
8017d54: b580 push {r7, lr}
|
|
8017d56: af00 add r7, sp, #0
|
|
#ifdef LWIP_RAND
|
|
udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND());
|
|
8017d58: f004 ffc6 bl 801cce8 <rand>
|
|
8017d5c: 4603 mov r3, r0
|
|
8017d5e: b29b uxth r3, r3
|
|
8017d60: f3c3 030d ubfx r3, r3, #0, #14
|
|
8017d64: b29b uxth r3, r3
|
|
8017d66: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000
|
|
8017d6a: b29a uxth r2, r3
|
|
8017d6c: 4b01 ldr r3, [pc, #4] ; (8017d74 <udp_init+0x20>)
|
|
8017d6e: 801a strh r2, [r3, #0]
|
|
#endif /* LWIP_RAND */
|
|
}
|
|
8017d70: bf00 nop
|
|
8017d72: bd80 pop {r7, pc}
|
|
8017d74: 2000007c .word 0x2000007c
|
|
|
|
08017d78 <udp_new_port>:
|
|
*
|
|
* @return a new (free) local UDP port number
|
|
*/
|
|
static u16_t
|
|
udp_new_port(void)
|
|
{
|
|
8017d78: b480 push {r7}
|
|
8017d7a: b083 sub sp, #12
|
|
8017d7c: af00 add r7, sp, #0
|
|
u16_t n = 0;
|
|
8017d7e: 2300 movs r3, #0
|
|
8017d80: 80fb strh r3, [r7, #6]
|
|
struct udp_pcb *pcb;
|
|
|
|
again:
|
|
if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) {
|
|
8017d82: 4b17 ldr r3, [pc, #92] ; (8017de0 <udp_new_port+0x68>)
|
|
8017d84: 881b ldrh r3, [r3, #0]
|
|
8017d86: 1c5a adds r2, r3, #1
|
|
8017d88: b291 uxth r1, r2
|
|
8017d8a: 4a15 ldr r2, [pc, #84] ; (8017de0 <udp_new_port+0x68>)
|
|
8017d8c: 8011 strh r1, [r2, #0]
|
|
8017d8e: f64f 72ff movw r2, #65535 ; 0xffff
|
|
8017d92: 4293 cmp r3, r2
|
|
8017d94: d103 bne.n 8017d9e <udp_new_port+0x26>
|
|
udp_port = UDP_LOCAL_PORT_RANGE_START;
|
|
8017d96: 4b12 ldr r3, [pc, #72] ; (8017de0 <udp_new_port+0x68>)
|
|
8017d98: f44f 4240 mov.w r2, #49152 ; 0xc000
|
|
8017d9c: 801a strh r2, [r3, #0]
|
|
}
|
|
/* Check all PCBs. */
|
|
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8017d9e: 4b11 ldr r3, [pc, #68] ; (8017de4 <udp_new_port+0x6c>)
|
|
8017da0: 681b ldr r3, [r3, #0]
|
|
8017da2: 603b str r3, [r7, #0]
|
|
8017da4: e011 b.n 8017dca <udp_new_port+0x52>
|
|
if (pcb->local_port == udp_port) {
|
|
8017da6: 683b ldr r3, [r7, #0]
|
|
8017da8: 8a5a ldrh r2, [r3, #18]
|
|
8017daa: 4b0d ldr r3, [pc, #52] ; (8017de0 <udp_new_port+0x68>)
|
|
8017dac: 881b ldrh r3, [r3, #0]
|
|
8017dae: 429a cmp r2, r3
|
|
8017db0: d108 bne.n 8017dc4 <udp_new_port+0x4c>
|
|
if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) {
|
|
8017db2: 88fb ldrh r3, [r7, #6]
|
|
8017db4: 3301 adds r3, #1
|
|
8017db6: 80fb strh r3, [r7, #6]
|
|
8017db8: 88fb ldrh r3, [r7, #6]
|
|
8017dba: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
|
|
8017dbe: d3e0 bcc.n 8017d82 <udp_new_port+0xa>
|
|
return 0;
|
|
8017dc0: 2300 movs r3, #0
|
|
8017dc2: e007 b.n 8017dd4 <udp_new_port+0x5c>
|
|
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8017dc4: 683b ldr r3, [r7, #0]
|
|
8017dc6: 68db ldr r3, [r3, #12]
|
|
8017dc8: 603b str r3, [r7, #0]
|
|
8017dca: 683b ldr r3, [r7, #0]
|
|
8017dcc: 2b00 cmp r3, #0
|
|
8017dce: d1ea bne.n 8017da6 <udp_new_port+0x2e>
|
|
}
|
|
goto again;
|
|
}
|
|
}
|
|
return udp_port;
|
|
8017dd0: 4b03 ldr r3, [pc, #12] ; (8017de0 <udp_new_port+0x68>)
|
|
8017dd2: 881b ldrh r3, [r3, #0]
|
|
}
|
|
8017dd4: 4618 mov r0, r3
|
|
8017dd6: 370c adds r7, #12
|
|
8017dd8: 46bd mov sp, r7
|
|
8017dda: f85d 7b04 ldr.w r7, [sp], #4
|
|
8017dde: 4770 bx lr
|
|
8017de0: 2000007c .word 0x2000007c
|
|
8017de4: 2000f814 .word 0x2000f814
|
|
|
|
08017de8 <udp_input_local_match>:
|
|
* @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4)
|
|
* @return 1 on match, 0 otherwise
|
|
*/
|
|
static u8_t
|
|
udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast)
|
|
{
|
|
8017de8: b580 push {r7, lr}
|
|
8017dea: b084 sub sp, #16
|
|
8017dec: af00 add r7, sp, #0
|
|
8017dee: 60f8 str r0, [r7, #12]
|
|
8017df0: 60b9 str r1, [r7, #8]
|
|
8017df2: 4613 mov r3, r2
|
|
8017df4: 71fb strb r3, [r7, #7]
|
|
LWIP_UNUSED_ARG(inp); /* in IPv6 only case */
|
|
LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */
|
|
|
|
LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL);
|
|
8017df6: 68fb ldr r3, [r7, #12]
|
|
8017df8: 2b00 cmp r3, #0
|
|
8017dfa: d105 bne.n 8017e08 <udp_input_local_match+0x20>
|
|
8017dfc: 4b27 ldr r3, [pc, #156] ; (8017e9c <udp_input_local_match+0xb4>)
|
|
8017dfe: 2287 movs r2, #135 ; 0x87
|
|
8017e00: 4927 ldr r1, [pc, #156] ; (8017ea0 <udp_input_local_match+0xb8>)
|
|
8017e02: 4828 ldr r0, [pc, #160] ; (8017ea4 <udp_input_local_match+0xbc>)
|
|
8017e04: f004 ff58 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL);
|
|
8017e08: 68bb ldr r3, [r7, #8]
|
|
8017e0a: 2b00 cmp r3, #0
|
|
8017e0c: d105 bne.n 8017e1a <udp_input_local_match+0x32>
|
|
8017e0e: 4b23 ldr r3, [pc, #140] ; (8017e9c <udp_input_local_match+0xb4>)
|
|
8017e10: 2288 movs r2, #136 ; 0x88
|
|
8017e12: 4925 ldr r1, [pc, #148] ; (8017ea8 <udp_input_local_match+0xc0>)
|
|
8017e14: 4823 ldr r0, [pc, #140] ; (8017ea4 <udp_input_local_match+0xbc>)
|
|
8017e16: f004 ff4f bl 801ccb8 <iprintf>
|
|
|
|
/* check if PCB is bound to specific netif */
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
8017e1a: 68fb ldr r3, [r7, #12]
|
|
8017e1c: 7a1b ldrb r3, [r3, #8]
|
|
8017e1e: 2b00 cmp r3, #0
|
|
8017e20: d00b beq.n 8017e3a <udp_input_local_match+0x52>
|
|
(pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) {
|
|
8017e22: 68fb ldr r3, [r7, #12]
|
|
8017e24: 7a1a ldrb r2, [r3, #8]
|
|
8017e26: 4b21 ldr r3, [pc, #132] ; (8017eac <udp_input_local_match+0xc4>)
|
|
8017e28: 685b ldr r3, [r3, #4]
|
|
8017e2a: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
8017e2e: 3301 adds r3, #1
|
|
8017e30: b2db uxtb r3, r3
|
|
if ((pcb->netif_idx != NETIF_NO_INDEX) &&
|
|
8017e32: 429a cmp r2, r3
|
|
8017e34: d001 beq.n 8017e3a <udp_input_local_match+0x52>
|
|
return 0;
|
|
8017e36: 2300 movs r3, #0
|
|
8017e38: e02b b.n 8017e92 <udp_input_local_match+0xaa>
|
|
/* Only need to check PCB if incoming IP version matches PCB IP version */
|
|
if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) {
|
|
#if LWIP_IPV4
|
|
/* Special case: IPv4 broadcast: all or broadcasts in my subnet
|
|
* Note: broadcast variable can only be 1 if it is an IPv4 broadcast */
|
|
if (broadcast != 0) {
|
|
8017e3a: 79fb ldrb r3, [r7, #7]
|
|
8017e3c: 2b00 cmp r3, #0
|
|
8017e3e: d018 beq.n 8017e72 <udp_input_local_match+0x8a>
|
|
#if IP_SOF_BROADCAST_RECV
|
|
if (ip_get_option(pcb, SOF_BROADCAST))
|
|
#endif /* IP_SOF_BROADCAST_RECV */
|
|
{
|
|
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
|
|
8017e40: 68fb ldr r3, [r7, #12]
|
|
8017e42: 2b00 cmp r3, #0
|
|
8017e44: d013 beq.n 8017e6e <udp_input_local_match+0x86>
|
|
8017e46: 68fb ldr r3, [r7, #12]
|
|
8017e48: 681b ldr r3, [r3, #0]
|
|
8017e4a: 2b00 cmp r3, #0
|
|
8017e4c: d00f beq.n 8017e6e <udp_input_local_match+0x86>
|
|
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
|
|
8017e4e: 4b17 ldr r3, [pc, #92] ; (8017eac <udp_input_local_match+0xc4>)
|
|
8017e50: 695b ldr r3, [r3, #20]
|
|
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
|
|
8017e52: f1b3 3fff cmp.w r3, #4294967295
|
|
8017e56: d00a beq.n 8017e6e <udp_input_local_match+0x86>
|
|
ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) {
|
|
8017e58: 68fb ldr r3, [r7, #12]
|
|
8017e5a: 681a ldr r2, [r3, #0]
|
|
8017e5c: 4b13 ldr r3, [pc, #76] ; (8017eac <udp_input_local_match+0xc4>)
|
|
8017e5e: 695b ldr r3, [r3, #20]
|
|
8017e60: 405a eors r2, r3
|
|
8017e62: 68bb ldr r3, [r7, #8]
|
|
8017e64: 3308 adds r3, #8
|
|
8017e66: 681b ldr r3, [r3, #0]
|
|
8017e68: 4013 ands r3, r2
|
|
((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) ||
|
|
8017e6a: 2b00 cmp r3, #0
|
|
8017e6c: d110 bne.n 8017e90 <udp_input_local_match+0xa8>
|
|
return 1;
|
|
8017e6e: 2301 movs r3, #1
|
|
8017e70: e00f b.n 8017e92 <udp_input_local_match+0xaa>
|
|
}
|
|
}
|
|
} else
|
|
#endif /* LWIP_IPV4 */
|
|
/* Handle IPv4 and IPv6: all or exact match */
|
|
if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) {
|
|
8017e72: 68fb ldr r3, [r7, #12]
|
|
8017e74: 2b00 cmp r3, #0
|
|
8017e76: d009 beq.n 8017e8c <udp_input_local_match+0xa4>
|
|
8017e78: 68fb ldr r3, [r7, #12]
|
|
8017e7a: 681b ldr r3, [r3, #0]
|
|
8017e7c: 2b00 cmp r3, #0
|
|
8017e7e: d005 beq.n 8017e8c <udp_input_local_match+0xa4>
|
|
8017e80: 68fb ldr r3, [r7, #12]
|
|
8017e82: 681a ldr r2, [r3, #0]
|
|
8017e84: 4b09 ldr r3, [pc, #36] ; (8017eac <udp_input_local_match+0xc4>)
|
|
8017e86: 695b ldr r3, [r3, #20]
|
|
8017e88: 429a cmp r2, r3
|
|
8017e8a: d101 bne.n 8017e90 <udp_input_local_match+0xa8>
|
|
return 1;
|
|
8017e8c: 2301 movs r3, #1
|
|
8017e8e: e000 b.n 8017e92 <udp_input_local_match+0xaa>
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
8017e90: 2300 movs r3, #0
|
|
}
|
|
8017e92: 4618 mov r0, r3
|
|
8017e94: 3710 adds r7, #16
|
|
8017e96: 46bd mov sp, r7
|
|
8017e98: bd80 pop {r7, pc}
|
|
8017e9a: bf00 nop
|
|
8017e9c: 08020034 .word 0x08020034
|
|
8017ea0: 08020064 .word 0x08020064
|
|
8017ea4: 08020088 .word 0x08020088
|
|
8017ea8: 080200b0 .word 0x080200b0
|
|
8017eac: 2000c0c8 .word 0x2000c0c8
|
|
|
|
08017eb0 <udp_input>:
|
|
* @param inp network interface on which the datagram was received.
|
|
*
|
|
*/
|
|
void
|
|
udp_input(struct pbuf *p, struct netif *inp)
|
|
{
|
|
8017eb0: b590 push {r4, r7, lr}
|
|
8017eb2: b08d sub sp, #52 ; 0x34
|
|
8017eb4: af02 add r7, sp, #8
|
|
8017eb6: 6078 str r0, [r7, #4]
|
|
8017eb8: 6039 str r1, [r7, #0]
|
|
struct udp_hdr *udphdr;
|
|
struct udp_pcb *pcb, *prev;
|
|
struct udp_pcb *uncon_pcb;
|
|
u16_t src, dest;
|
|
u8_t broadcast;
|
|
u8_t for_us = 0;
|
|
8017eba: 2300 movs r3, #0
|
|
8017ebc: 76fb strb r3, [r7, #27]
|
|
|
|
LWIP_UNUSED_ARG(inp);
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ASSERT("udp_input: invalid pbuf", p != NULL);
|
|
8017ebe: 687b ldr r3, [r7, #4]
|
|
8017ec0: 2b00 cmp r3, #0
|
|
8017ec2: d105 bne.n 8017ed0 <udp_input+0x20>
|
|
8017ec4: 4b7c ldr r3, [pc, #496] ; (80180b8 <udp_input+0x208>)
|
|
8017ec6: 22cf movs r2, #207 ; 0xcf
|
|
8017ec8: 497c ldr r1, [pc, #496] ; (80180bc <udp_input+0x20c>)
|
|
8017eca: 487d ldr r0, [pc, #500] ; (80180c0 <udp_input+0x210>)
|
|
8017ecc: f004 fef4 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("udp_input: invalid netif", inp != NULL);
|
|
8017ed0: 683b ldr r3, [r7, #0]
|
|
8017ed2: 2b00 cmp r3, #0
|
|
8017ed4: d105 bne.n 8017ee2 <udp_input+0x32>
|
|
8017ed6: 4b78 ldr r3, [pc, #480] ; (80180b8 <udp_input+0x208>)
|
|
8017ed8: 22d0 movs r2, #208 ; 0xd0
|
|
8017eda: 497a ldr r1, [pc, #488] ; (80180c4 <udp_input+0x214>)
|
|
8017edc: 4878 ldr r0, [pc, #480] ; (80180c0 <udp_input+0x210>)
|
|
8017ede: f004 feeb bl 801ccb8 <iprintf>
|
|
PERF_START;
|
|
|
|
UDP_STATS_INC(udp.recv);
|
|
|
|
/* Check minimum length (UDP header) */
|
|
if (p->len < UDP_HLEN) {
|
|
8017ee2: 687b ldr r3, [r7, #4]
|
|
8017ee4: 895b ldrh r3, [r3, #10]
|
|
8017ee6: 2b07 cmp r3, #7
|
|
8017ee8: d803 bhi.n 8017ef2 <udp_input+0x42>
|
|
LWIP_DEBUGF(UDP_DEBUG,
|
|
("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len));
|
|
UDP_STATS_INC(udp.lenerr);
|
|
UDP_STATS_INC(udp.drop);
|
|
MIB2_STATS_INC(mib2.udpinerrors);
|
|
pbuf_free(p);
|
|
8017eea: 6878 ldr r0, [r7, #4]
|
|
8017eec: f7fa f9b4 bl 8012258 <pbuf_free>
|
|
goto end;
|
|
8017ef0: e0de b.n 80180b0 <udp_input+0x200>
|
|
}
|
|
|
|
udphdr = (struct udp_hdr *)p->payload;
|
|
8017ef2: 687b ldr r3, [r7, #4]
|
|
8017ef4: 685b ldr r3, [r3, #4]
|
|
8017ef6: 617b str r3, [r7, #20]
|
|
|
|
/* is broadcast packet ? */
|
|
broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif());
|
|
8017ef8: 4b73 ldr r3, [pc, #460] ; (80180c8 <udp_input+0x218>)
|
|
8017efa: 695a ldr r2, [r3, #20]
|
|
8017efc: 4b72 ldr r3, [pc, #456] ; (80180c8 <udp_input+0x218>)
|
|
8017efe: 681b ldr r3, [r3, #0]
|
|
8017f00: 4619 mov r1, r3
|
|
8017f02: 4610 mov r0, r2
|
|
8017f04: f003 fe16 bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
8017f08: 4603 mov r3, r0
|
|
8017f0a: 74fb strb r3, [r7, #19]
|
|
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len));
|
|
|
|
/* convert src and dest ports to host byte order */
|
|
src = lwip_ntohs(udphdr->src);
|
|
8017f0c: 697b ldr r3, [r7, #20]
|
|
8017f0e: 881b ldrh r3, [r3, #0]
|
|
8017f10: b29b uxth r3, r3
|
|
8017f12: 4618 mov r0, r3
|
|
8017f14: f7f8 fdec bl 8010af0 <lwip_htons>
|
|
8017f18: 4603 mov r3, r0
|
|
8017f1a: 823b strh r3, [r7, #16]
|
|
dest = lwip_ntohs(udphdr->dest);
|
|
8017f1c: 697b ldr r3, [r7, #20]
|
|
8017f1e: 885b ldrh r3, [r3, #2]
|
|
8017f20: b29b uxth r3, r3
|
|
8017f22: 4618 mov r0, r3
|
|
8017f24: f7f8 fde4 bl 8010af0 <lwip_htons>
|
|
8017f28: 4603 mov r3, r0
|
|
8017f2a: 81fb strh r3, [r7, #14]
|
|
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr());
|
|
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest)));
|
|
ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr());
|
|
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src)));
|
|
|
|
pcb = NULL;
|
|
8017f2c: 2300 movs r3, #0
|
|
8017f2e: 627b str r3, [r7, #36] ; 0x24
|
|
prev = NULL;
|
|
8017f30: 2300 movs r3, #0
|
|
8017f32: 623b str r3, [r7, #32]
|
|
uncon_pcb = NULL;
|
|
8017f34: 2300 movs r3, #0
|
|
8017f36: 61fb str r3, [r7, #28]
|
|
/* Iterate through the UDP pcb list for a matching pcb.
|
|
* 'Perfect match' pcbs (connected to the remote port & ip address) are
|
|
* preferred. If no perfect match is found, the first unconnected pcb that
|
|
* matches the local port and ip address gets the datagram. */
|
|
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8017f38: 4b64 ldr r3, [pc, #400] ; (80180cc <udp_input+0x21c>)
|
|
8017f3a: 681b ldr r3, [r3, #0]
|
|
8017f3c: 627b str r3, [r7, #36] ; 0x24
|
|
8017f3e: e054 b.n 8017fea <udp_input+0x13a>
|
|
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port));
|
|
ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip);
|
|
LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port));
|
|
|
|
/* compare PCB local addr+port to UDP destination addr+port */
|
|
if ((pcb->local_port == dest) &&
|
|
8017f40: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017f42: 8a5b ldrh r3, [r3, #18]
|
|
8017f44: 89fa ldrh r2, [r7, #14]
|
|
8017f46: 429a cmp r2, r3
|
|
8017f48: d14a bne.n 8017fe0 <udp_input+0x130>
|
|
(udp_input_local_match(pcb, inp, broadcast) != 0)) {
|
|
8017f4a: 7cfb ldrb r3, [r7, #19]
|
|
8017f4c: 461a mov r2, r3
|
|
8017f4e: 6839 ldr r1, [r7, #0]
|
|
8017f50: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
8017f52: f7ff ff49 bl 8017de8 <udp_input_local_match>
|
|
8017f56: 4603 mov r3, r0
|
|
if ((pcb->local_port == dest) &&
|
|
8017f58: 2b00 cmp r3, #0
|
|
8017f5a: d041 beq.n 8017fe0 <udp_input+0x130>
|
|
if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) {
|
|
8017f5c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017f5e: 7c1b ldrb r3, [r3, #16]
|
|
8017f60: f003 0304 and.w r3, r3, #4
|
|
8017f64: 2b00 cmp r3, #0
|
|
8017f66: d11d bne.n 8017fa4 <udp_input+0xf4>
|
|
if (uncon_pcb == NULL) {
|
|
8017f68: 69fb ldr r3, [r7, #28]
|
|
8017f6a: 2b00 cmp r3, #0
|
|
8017f6c: d102 bne.n 8017f74 <udp_input+0xc4>
|
|
/* the first unconnected matching PCB */
|
|
uncon_pcb = pcb;
|
|
8017f6e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017f70: 61fb str r3, [r7, #28]
|
|
8017f72: e017 b.n 8017fa4 <udp_input+0xf4>
|
|
#if LWIP_IPV4
|
|
} else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) {
|
|
8017f74: 7cfb ldrb r3, [r7, #19]
|
|
8017f76: 2b00 cmp r3, #0
|
|
8017f78: d014 beq.n 8017fa4 <udp_input+0xf4>
|
|
8017f7a: 4b53 ldr r3, [pc, #332] ; (80180c8 <udp_input+0x218>)
|
|
8017f7c: 695b ldr r3, [r3, #20]
|
|
8017f7e: f1b3 3fff cmp.w r3, #4294967295
|
|
8017f82: d10f bne.n 8017fa4 <udp_input+0xf4>
|
|
/* global broadcast address (only valid for IPv4; match was checked before) */
|
|
if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) {
|
|
8017f84: 69fb ldr r3, [r7, #28]
|
|
8017f86: 681a ldr r2, [r3, #0]
|
|
8017f88: 683b ldr r3, [r7, #0]
|
|
8017f8a: 3304 adds r3, #4
|
|
8017f8c: 681b ldr r3, [r3, #0]
|
|
8017f8e: 429a cmp r2, r3
|
|
8017f90: d008 beq.n 8017fa4 <udp_input+0xf4>
|
|
/* uncon_pcb does not match the input netif, check this pcb */
|
|
if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) {
|
|
8017f92: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017f94: 681a ldr r2, [r3, #0]
|
|
8017f96: 683b ldr r3, [r7, #0]
|
|
8017f98: 3304 adds r3, #4
|
|
8017f9a: 681b ldr r3, [r3, #0]
|
|
8017f9c: 429a cmp r2, r3
|
|
8017f9e: d101 bne.n 8017fa4 <udp_input+0xf4>
|
|
/* better match */
|
|
uncon_pcb = pcb;
|
|
8017fa0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fa2: 61fb str r3, [r7, #28]
|
|
}
|
|
#endif /* SO_REUSE */
|
|
}
|
|
|
|
/* compare PCB remote addr+port to UDP source addr+port */
|
|
if ((pcb->remote_port == src) &&
|
|
8017fa4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fa6: 8a9b ldrh r3, [r3, #20]
|
|
8017fa8: 8a3a ldrh r2, [r7, #16]
|
|
8017faa: 429a cmp r2, r3
|
|
8017fac: d118 bne.n 8017fe0 <udp_input+0x130>
|
|
(ip_addr_isany_val(pcb->remote_ip) ||
|
|
8017fae: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fb0: 685b ldr r3, [r3, #4]
|
|
if ((pcb->remote_port == src) &&
|
|
8017fb2: 2b00 cmp r3, #0
|
|
8017fb4: d005 beq.n 8017fc2 <udp_input+0x112>
|
|
ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) {
|
|
8017fb6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fb8: 685a ldr r2, [r3, #4]
|
|
8017fba: 4b43 ldr r3, [pc, #268] ; (80180c8 <udp_input+0x218>)
|
|
8017fbc: 691b ldr r3, [r3, #16]
|
|
(ip_addr_isany_val(pcb->remote_ip) ||
|
|
8017fbe: 429a cmp r2, r3
|
|
8017fc0: d10e bne.n 8017fe0 <udp_input+0x130>
|
|
/* the first fully matching PCB */
|
|
if (prev != NULL) {
|
|
8017fc2: 6a3b ldr r3, [r7, #32]
|
|
8017fc4: 2b00 cmp r3, #0
|
|
8017fc6: d014 beq.n 8017ff2 <udp_input+0x142>
|
|
/* move the pcb to the front of udp_pcbs so that is
|
|
found faster next time */
|
|
prev->next = pcb->next;
|
|
8017fc8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fca: 68da ldr r2, [r3, #12]
|
|
8017fcc: 6a3b ldr r3, [r7, #32]
|
|
8017fce: 60da str r2, [r3, #12]
|
|
pcb->next = udp_pcbs;
|
|
8017fd0: 4b3e ldr r3, [pc, #248] ; (80180cc <udp_input+0x21c>)
|
|
8017fd2: 681a ldr r2, [r3, #0]
|
|
8017fd4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fd6: 60da str r2, [r3, #12]
|
|
udp_pcbs = pcb;
|
|
8017fd8: 4a3c ldr r2, [pc, #240] ; (80180cc <udp_input+0x21c>)
|
|
8017fda: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fdc: 6013 str r3, [r2, #0]
|
|
} else {
|
|
UDP_STATS_INC(udp.cachehit);
|
|
}
|
|
break;
|
|
8017fde: e008 b.n 8017ff2 <udp_input+0x142>
|
|
}
|
|
}
|
|
|
|
prev = pcb;
|
|
8017fe0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fe2: 623b str r3, [r7, #32]
|
|
for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) {
|
|
8017fe4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fe6: 68db ldr r3, [r3, #12]
|
|
8017fe8: 627b str r3, [r7, #36] ; 0x24
|
|
8017fea: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017fec: 2b00 cmp r3, #0
|
|
8017fee: d1a7 bne.n 8017f40 <udp_input+0x90>
|
|
8017ff0: e000 b.n 8017ff4 <udp_input+0x144>
|
|
break;
|
|
8017ff2: bf00 nop
|
|
}
|
|
/* no fully matching pcb found? then look for an unconnected pcb */
|
|
if (pcb == NULL) {
|
|
8017ff4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8017ff6: 2b00 cmp r3, #0
|
|
8017ff8: d101 bne.n 8017ffe <udp_input+0x14e>
|
|
pcb = uncon_pcb;
|
|
8017ffa: 69fb ldr r3, [r7, #28]
|
|
8017ffc: 627b str r3, [r7, #36] ; 0x24
|
|
}
|
|
|
|
/* Check checksum if this is a match or if it was directed at us. */
|
|
if (pcb != NULL) {
|
|
8017ffe: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8018000: 2b00 cmp r3, #0
|
|
8018002: d002 beq.n 801800a <udp_input+0x15a>
|
|
for_us = 1;
|
|
8018004: 2301 movs r3, #1
|
|
8018006: 76fb strb r3, [r7, #27]
|
|
8018008: e00a b.n 8018020 <udp_input+0x170>
|
|
for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0;
|
|
}
|
|
#endif /* LWIP_IPV6 */
|
|
#if LWIP_IPV4
|
|
if (!ip_current_is_v6()) {
|
|
for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr());
|
|
801800a: 683b ldr r3, [r7, #0]
|
|
801800c: 3304 adds r3, #4
|
|
801800e: 681a ldr r2, [r3, #0]
|
|
8018010: 4b2d ldr r3, [pc, #180] ; (80180c8 <udp_input+0x218>)
|
|
8018012: 695b ldr r3, [r3, #20]
|
|
8018014: 429a cmp r2, r3
|
|
8018016: bf0c ite eq
|
|
8018018: 2301 moveq r3, #1
|
|
801801a: 2300 movne r3, #0
|
|
801801c: b2db uxtb r3, r3
|
|
801801e: 76fb strb r3, [r7, #27]
|
|
}
|
|
#endif /* LWIP_IPV4 */
|
|
}
|
|
|
|
if (for_us) {
|
|
8018020: 7efb ldrb r3, [r7, #27]
|
|
8018022: 2b00 cmp r3, #0
|
|
8018024: d041 beq.n 80180aa <udp_input+0x1fa>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#endif /* CHECKSUM_CHECK_UDP */
|
|
if (pbuf_remove_header(p, UDP_HLEN)) {
|
|
8018026: 2108 movs r1, #8
|
|
8018028: 6878 ldr r0, [r7, #4]
|
|
801802a: f7fa f88f bl 801214c <pbuf_remove_header>
|
|
801802e: 4603 mov r3, r0
|
|
8018030: 2b00 cmp r3, #0
|
|
8018032: d00a beq.n 801804a <udp_input+0x19a>
|
|
/* Can we cope with this failing? Just assert for now */
|
|
LWIP_ASSERT("pbuf_remove_header failed\n", 0);
|
|
8018034: 4b20 ldr r3, [pc, #128] ; (80180b8 <udp_input+0x208>)
|
|
8018036: f44f 72b8 mov.w r2, #368 ; 0x170
|
|
801803a: 4925 ldr r1, [pc, #148] ; (80180d0 <udp_input+0x220>)
|
|
801803c: 4820 ldr r0, [pc, #128] ; (80180c0 <udp_input+0x210>)
|
|
801803e: f004 fe3b bl 801ccb8 <iprintf>
|
|
UDP_STATS_INC(udp.drop);
|
|
MIB2_STATS_INC(mib2.udpinerrors);
|
|
pbuf_free(p);
|
|
8018042: 6878 ldr r0, [r7, #4]
|
|
8018044: f7fa f908 bl 8012258 <pbuf_free>
|
|
goto end;
|
|
8018048: e032 b.n 80180b0 <udp_input+0x200>
|
|
}
|
|
|
|
if (pcb != NULL) {
|
|
801804a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801804c: 2b00 cmp r3, #0
|
|
801804e: d012 beq.n 8018076 <udp_input+0x1c6>
|
|
}
|
|
}
|
|
}
|
|
#endif /* SO_REUSE && SO_REUSE_RXTOALL */
|
|
/* callback */
|
|
if (pcb->recv != NULL) {
|
|
8018050: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
8018052: 699b ldr r3, [r3, #24]
|
|
8018054: 2b00 cmp r3, #0
|
|
8018056: d00a beq.n 801806e <udp_input+0x1be>
|
|
/* now the recv function is responsible for freeing p */
|
|
pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src);
|
|
8018058: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801805a: 699c ldr r4, [r3, #24]
|
|
801805c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801805e: 69d8 ldr r0, [r3, #28]
|
|
8018060: 8a3b ldrh r3, [r7, #16]
|
|
8018062: 9300 str r3, [sp, #0]
|
|
8018064: 4b1b ldr r3, [pc, #108] ; (80180d4 <udp_input+0x224>)
|
|
8018066: 687a ldr r2, [r7, #4]
|
|
8018068: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
801806a: 47a0 blx r4
|
|
} else {
|
|
pbuf_free(p);
|
|
}
|
|
end:
|
|
PERF_STOP("udp_input");
|
|
return;
|
|
801806c: e021 b.n 80180b2 <udp_input+0x202>
|
|
pbuf_free(p);
|
|
801806e: 6878 ldr r0, [r7, #4]
|
|
8018070: f7fa f8f2 bl 8012258 <pbuf_free>
|
|
goto end;
|
|
8018074: e01c b.n 80180b0 <udp_input+0x200>
|
|
if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) {
|
|
8018076: 7cfb ldrb r3, [r7, #19]
|
|
8018078: 2b00 cmp r3, #0
|
|
801807a: d112 bne.n 80180a2 <udp_input+0x1f2>
|
|
801807c: 4b12 ldr r3, [pc, #72] ; (80180c8 <udp_input+0x218>)
|
|
801807e: 695b ldr r3, [r3, #20]
|
|
8018080: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
8018084: 2be0 cmp r3, #224 ; 0xe0
|
|
8018086: d00c beq.n 80180a2 <udp_input+0x1f2>
|
|
pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN));
|
|
8018088: 4b0f ldr r3, [pc, #60] ; (80180c8 <udp_input+0x218>)
|
|
801808a: 899b ldrh r3, [r3, #12]
|
|
801808c: 3308 adds r3, #8
|
|
801808e: b29b uxth r3, r3
|
|
8018090: b21b sxth r3, r3
|
|
8018092: 4619 mov r1, r3
|
|
8018094: 6878 ldr r0, [r7, #4]
|
|
8018096: f7fa f8cc bl 8012232 <pbuf_header_force>
|
|
icmp_port_unreach(ip_current_is_v6(), p);
|
|
801809a: 2103 movs r1, #3
|
|
801809c: 6878 ldr r0, [r7, #4]
|
|
801809e: f003 fa0d bl 801b4bc <icmp_dest_unreach>
|
|
pbuf_free(p);
|
|
80180a2: 6878 ldr r0, [r7, #4]
|
|
80180a4: f7fa f8d8 bl 8012258 <pbuf_free>
|
|
return;
|
|
80180a8: e003 b.n 80180b2 <udp_input+0x202>
|
|
pbuf_free(p);
|
|
80180aa: 6878 ldr r0, [r7, #4]
|
|
80180ac: f7fa f8d4 bl 8012258 <pbuf_free>
|
|
return;
|
|
80180b0: bf00 nop
|
|
UDP_STATS_INC(udp.drop);
|
|
MIB2_STATS_INC(mib2.udpinerrors);
|
|
pbuf_free(p);
|
|
PERF_STOP("udp_input");
|
|
#endif /* CHECKSUM_CHECK_UDP */
|
|
}
|
|
80180b2: 372c adds r7, #44 ; 0x2c
|
|
80180b4: 46bd mov sp, r7
|
|
80180b6: bd90 pop {r4, r7, pc}
|
|
80180b8: 08020034 .word 0x08020034
|
|
80180bc: 080200d8 .word 0x080200d8
|
|
80180c0: 08020088 .word 0x08020088
|
|
80180c4: 080200f0 .word 0x080200f0
|
|
80180c8: 2000c0c8 .word 0x2000c0c8
|
|
80180cc: 2000f814 .word 0x2000f814
|
|
80180d0: 0802010c .word 0x0802010c
|
|
80180d4: 2000c0d8 .word 0x2000c0d8
|
|
|
|
080180d8 <udp_sendto_if>:
|
|
* @see udp_disconnect() udp_send()
|
|
*/
|
|
err_t
|
|
udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p,
|
|
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif)
|
|
{
|
|
80180d8: b580 push {r7, lr}
|
|
80180da: b088 sub sp, #32
|
|
80180dc: af02 add r7, sp, #8
|
|
80180de: 60f8 str r0, [r7, #12]
|
|
80180e0: 60b9 str r1, [r7, #8]
|
|
80180e2: 607a str r2, [r7, #4]
|
|
80180e4: 807b strh r3, [r7, #2]
|
|
u16_t chksum)
|
|
{
|
|
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
|
|
const ip_addr_t *src_ip;
|
|
|
|
LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
80180e6: 68fb ldr r3, [r7, #12]
|
|
80180e8: 2b00 cmp r3, #0
|
|
80180ea: d109 bne.n 8018100 <udp_sendto_if+0x28>
|
|
80180ec: 4b2e ldr r3, [pc, #184] ; (80181a8 <udp_sendto_if+0xd0>)
|
|
80180ee: f44f 7220 mov.w r2, #640 ; 0x280
|
|
80180f2: 492e ldr r1, [pc, #184] ; (80181ac <udp_sendto_if+0xd4>)
|
|
80180f4: 482e ldr r0, [pc, #184] ; (80181b0 <udp_sendto_if+0xd8>)
|
|
80180f6: f004 fddf bl 801ccb8 <iprintf>
|
|
80180fa: f06f 030f mvn.w r3, #15
|
|
80180fe: e04f b.n 80181a0 <udp_sendto_if+0xc8>
|
|
LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG);
|
|
8018100: 68bb ldr r3, [r7, #8]
|
|
8018102: 2b00 cmp r3, #0
|
|
8018104: d109 bne.n 801811a <udp_sendto_if+0x42>
|
|
8018106: 4b28 ldr r3, [pc, #160] ; (80181a8 <udp_sendto_if+0xd0>)
|
|
8018108: f240 2281 movw r2, #641 ; 0x281
|
|
801810c: 4929 ldr r1, [pc, #164] ; (80181b4 <udp_sendto_if+0xdc>)
|
|
801810e: 4828 ldr r0, [pc, #160] ; (80181b0 <udp_sendto_if+0xd8>)
|
|
8018110: f004 fdd2 bl 801ccb8 <iprintf>
|
|
8018114: f06f 030f mvn.w r3, #15
|
|
8018118: e042 b.n 80181a0 <udp_sendto_if+0xc8>
|
|
LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
|
|
801811a: 687b ldr r3, [r7, #4]
|
|
801811c: 2b00 cmp r3, #0
|
|
801811e: d109 bne.n 8018134 <udp_sendto_if+0x5c>
|
|
8018120: 4b21 ldr r3, [pc, #132] ; (80181a8 <udp_sendto_if+0xd0>)
|
|
8018122: f240 2282 movw r2, #642 ; 0x282
|
|
8018126: 4924 ldr r1, [pc, #144] ; (80181b8 <udp_sendto_if+0xe0>)
|
|
8018128: 4821 ldr r0, [pc, #132] ; (80181b0 <udp_sendto_if+0xd8>)
|
|
801812a: f004 fdc5 bl 801ccb8 <iprintf>
|
|
801812e: f06f 030f mvn.w r3, #15
|
|
8018132: e035 b.n 80181a0 <udp_sendto_if+0xc8>
|
|
LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG);
|
|
8018134: 6a3b ldr r3, [r7, #32]
|
|
8018136: 2b00 cmp r3, #0
|
|
8018138: d109 bne.n 801814e <udp_sendto_if+0x76>
|
|
801813a: 4b1b ldr r3, [pc, #108] ; (80181a8 <udp_sendto_if+0xd0>)
|
|
801813c: f240 2283 movw r2, #643 ; 0x283
|
|
8018140: 491e ldr r1, [pc, #120] ; (80181bc <udp_sendto_if+0xe4>)
|
|
8018142: 481b ldr r0, [pc, #108] ; (80181b0 <udp_sendto_if+0xd8>)
|
|
8018144: f004 fdb8 bl 801ccb8 <iprintf>
|
|
8018148: f06f 030f mvn.w r3, #15
|
|
801814c: e028 b.n 80181a0 <udp_sendto_if+0xc8>
|
|
#endif /* LWIP_IPV6 */
|
|
#if LWIP_IPV4 && LWIP_IPV6
|
|
else
|
|
#endif /* LWIP_IPV4 && LWIP_IPV6 */
|
|
#if LWIP_IPV4
|
|
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
|
|
801814e: 68fb ldr r3, [r7, #12]
|
|
8018150: 2b00 cmp r3, #0
|
|
8018152: d009 beq.n 8018168 <udp_sendto_if+0x90>
|
|
8018154: 68fb ldr r3, [r7, #12]
|
|
8018156: 681b ldr r3, [r3, #0]
|
|
8018158: 2b00 cmp r3, #0
|
|
801815a: d005 beq.n 8018168 <udp_sendto_if+0x90>
|
|
ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) {
|
|
801815c: 68fb ldr r3, [r7, #12]
|
|
801815e: 681b ldr r3, [r3, #0]
|
|
8018160: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) ||
|
|
8018164: 2be0 cmp r3, #224 ; 0xe0
|
|
8018166: d103 bne.n 8018170 <udp_sendto_if+0x98>
|
|
/* if the local_ip is any or multicast
|
|
* use the outgoing network interface IP address as source address */
|
|
src_ip = netif_ip_addr4(netif);
|
|
8018168: 6a3b ldr r3, [r7, #32]
|
|
801816a: 3304 adds r3, #4
|
|
801816c: 617b str r3, [r7, #20]
|
|
801816e: e00b b.n 8018188 <udp_sendto_if+0xb0>
|
|
} else {
|
|
/* check if UDP PCB local IP address is correct
|
|
* this could be an old address if netif->ip_addr has changed */
|
|
if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) {
|
|
8018170: 68fb ldr r3, [r7, #12]
|
|
8018172: 681a ldr r2, [r3, #0]
|
|
8018174: 6a3b ldr r3, [r7, #32]
|
|
8018176: 3304 adds r3, #4
|
|
8018178: 681b ldr r3, [r3, #0]
|
|
801817a: 429a cmp r2, r3
|
|
801817c: d002 beq.n 8018184 <udp_sendto_if+0xac>
|
|
/* local_ip doesn't match, drop the packet */
|
|
return ERR_RTE;
|
|
801817e: f06f 0303 mvn.w r3, #3
|
|
8018182: e00d b.n 80181a0 <udp_sendto_if+0xc8>
|
|
}
|
|
/* use UDP PCB local IP address as source address */
|
|
src_ip = &pcb->local_ip;
|
|
8018184: 68fb ldr r3, [r7, #12]
|
|
8018186: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* LWIP_IPV4 */
|
|
#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP
|
|
return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip);
|
|
#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
|
|
return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip);
|
|
8018188: 887a ldrh r2, [r7, #2]
|
|
801818a: 697b ldr r3, [r7, #20]
|
|
801818c: 9301 str r3, [sp, #4]
|
|
801818e: 6a3b ldr r3, [r7, #32]
|
|
8018190: 9300 str r3, [sp, #0]
|
|
8018192: 4613 mov r3, r2
|
|
8018194: 687a ldr r2, [r7, #4]
|
|
8018196: 68b9 ldr r1, [r7, #8]
|
|
8018198: 68f8 ldr r0, [r7, #12]
|
|
801819a: f000 f811 bl 80181c0 <udp_sendto_if_src>
|
|
801819e: 4603 mov r3, r0
|
|
#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */
|
|
}
|
|
80181a0: 4618 mov r0, r3
|
|
80181a2: 3718 adds r7, #24
|
|
80181a4: 46bd mov sp, r7
|
|
80181a6: bd80 pop {r7, pc}
|
|
80181a8: 08020034 .word 0x08020034
|
|
80181ac: 080201a8 .word 0x080201a8
|
|
80181b0: 08020088 .word 0x08020088
|
|
80181b4: 080201c4 .word 0x080201c4
|
|
80181b8: 080201e0 .word 0x080201e0
|
|
80181bc: 08020200 .word 0x08020200
|
|
|
|
080181c0 <udp_sendto_if_src>:
|
|
/** @ingroup udp_raw
|
|
* Same as @ref udp_sendto_if, but with source address */
|
|
err_t
|
|
udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p,
|
|
const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip)
|
|
{
|
|
80181c0: b580 push {r7, lr}
|
|
80181c2: b08c sub sp, #48 ; 0x30
|
|
80181c4: af04 add r7, sp, #16
|
|
80181c6: 60f8 str r0, [r7, #12]
|
|
80181c8: 60b9 str r1, [r7, #8]
|
|
80181ca: 607a str r2, [r7, #4]
|
|
80181cc: 807b strh r3, [r7, #2]
|
|
u8_t ip_proto;
|
|
u8_t ttl;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
80181ce: 68fb ldr r3, [r7, #12]
|
|
80181d0: 2b00 cmp r3, #0
|
|
80181d2: d109 bne.n 80181e8 <udp_sendto_if_src+0x28>
|
|
80181d4: 4b65 ldr r3, [pc, #404] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
80181d6: f240 22d1 movw r2, #721 ; 0x2d1
|
|
80181da: 4965 ldr r1, [pc, #404] ; (8018370 <udp_sendto_if_src+0x1b0>)
|
|
80181dc: 4865 ldr r0, [pc, #404] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
80181de: f004 fd6b bl 801ccb8 <iprintf>
|
|
80181e2: f06f 030f mvn.w r3, #15
|
|
80181e6: e0bc b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG);
|
|
80181e8: 68bb ldr r3, [r7, #8]
|
|
80181ea: 2b00 cmp r3, #0
|
|
80181ec: d109 bne.n 8018202 <udp_sendto_if_src+0x42>
|
|
80181ee: 4b5f ldr r3, [pc, #380] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
80181f0: f240 22d2 movw r2, #722 ; 0x2d2
|
|
80181f4: 4960 ldr r1, [pc, #384] ; (8018378 <udp_sendto_if_src+0x1b8>)
|
|
80181f6: 485f ldr r0, [pc, #380] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
80181f8: f004 fd5e bl 801ccb8 <iprintf>
|
|
80181fc: f06f 030f mvn.w r3, #15
|
|
8018200: e0af b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG);
|
|
8018202: 687b ldr r3, [r7, #4]
|
|
8018204: 2b00 cmp r3, #0
|
|
8018206: d109 bne.n 801821c <udp_sendto_if_src+0x5c>
|
|
8018208: 4b58 ldr r3, [pc, #352] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
801820a: f240 22d3 movw r2, #723 ; 0x2d3
|
|
801820e: 495b ldr r1, [pc, #364] ; (801837c <udp_sendto_if_src+0x1bc>)
|
|
8018210: 4858 ldr r0, [pc, #352] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
8018212: f004 fd51 bl 801ccb8 <iprintf>
|
|
8018216: f06f 030f mvn.w r3, #15
|
|
801821a: e0a2 b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG);
|
|
801821c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801821e: 2b00 cmp r3, #0
|
|
8018220: d109 bne.n 8018236 <udp_sendto_if_src+0x76>
|
|
8018222: 4b52 ldr r3, [pc, #328] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
8018224: f44f 7235 mov.w r2, #724 ; 0x2d4
|
|
8018228: 4955 ldr r1, [pc, #340] ; (8018380 <udp_sendto_if_src+0x1c0>)
|
|
801822a: 4852 ldr r0, [pc, #328] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
801822c: f004 fd44 bl 801ccb8 <iprintf>
|
|
8018230: f06f 030f mvn.w r3, #15
|
|
8018234: e095 b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG);
|
|
8018236: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8018238: 2b00 cmp r3, #0
|
|
801823a: d109 bne.n 8018250 <udp_sendto_if_src+0x90>
|
|
801823c: 4b4b ldr r3, [pc, #300] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
801823e: f240 22d5 movw r2, #725 ; 0x2d5
|
|
8018242: 4950 ldr r1, [pc, #320] ; (8018384 <udp_sendto_if_src+0x1c4>)
|
|
8018244: 484b ldr r0, [pc, #300] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
8018246: f004 fd37 bl 801ccb8 <iprintf>
|
|
801824a: f06f 030f mvn.w r3, #15
|
|
801824e: e088 b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
return ERR_VAL;
|
|
}
|
|
#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */
|
|
|
|
/* if the PCB is not yet bound to a port, bind it here */
|
|
if (pcb->local_port == 0) {
|
|
8018250: 68fb ldr r3, [r7, #12]
|
|
8018252: 8a5b ldrh r3, [r3, #18]
|
|
8018254: 2b00 cmp r3, #0
|
|
8018256: d10f bne.n 8018278 <udp_sendto_if_src+0xb8>
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n"));
|
|
err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
|
|
8018258: 68f9 ldr r1, [r7, #12]
|
|
801825a: 68fb ldr r3, [r7, #12]
|
|
801825c: 8a5b ldrh r3, [r3, #18]
|
|
801825e: 461a mov r2, r3
|
|
8018260: 68f8 ldr r0, [r7, #12]
|
|
8018262: f000 f893 bl 801838c <udp_bind>
|
|
8018266: 4603 mov r3, r0
|
|
8018268: 76fb strb r3, [r7, #27]
|
|
if (err != ERR_OK) {
|
|
801826a: f997 301b ldrsb.w r3, [r7, #27]
|
|
801826e: 2b00 cmp r3, #0
|
|
8018270: d002 beq.n 8018278 <udp_sendto_if_src+0xb8>
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n"));
|
|
return err;
|
|
8018272: f997 301b ldrsb.w r3, [r7, #27]
|
|
8018276: e074 b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
}
|
|
}
|
|
|
|
/* packet too large to add a UDP header without causing an overflow? */
|
|
if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) {
|
|
8018278: 68bb ldr r3, [r7, #8]
|
|
801827a: 891b ldrh r3, [r3, #8]
|
|
801827c: f64f 72f7 movw r2, #65527 ; 0xfff7
|
|
8018280: 4293 cmp r3, r2
|
|
8018282: d902 bls.n 801828a <udp_sendto_if_src+0xca>
|
|
return ERR_MEM;
|
|
8018284: f04f 33ff mov.w r3, #4294967295
|
|
8018288: e06b b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
}
|
|
/* not enough space to add an UDP header to first pbuf in given p chain? */
|
|
if (pbuf_add_header(p, UDP_HLEN)) {
|
|
801828a: 2108 movs r1, #8
|
|
801828c: 68b8 ldr r0, [r7, #8]
|
|
801828e: f7f9 ff4d bl 801212c <pbuf_add_header>
|
|
8018292: 4603 mov r3, r0
|
|
8018294: 2b00 cmp r3, #0
|
|
8018296: d015 beq.n 80182c4 <udp_sendto_if_src+0x104>
|
|
/* allocate header in a separate new pbuf */
|
|
q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM);
|
|
8018298: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801829c: 2108 movs r1, #8
|
|
801829e: 2022 movs r0, #34 ; 0x22
|
|
80182a0: f7f9 fcfa bl 8011c98 <pbuf_alloc>
|
|
80182a4: 61f8 str r0, [r7, #28]
|
|
/* new header pbuf could not be allocated? */
|
|
if (q == NULL) {
|
|
80182a6: 69fb ldr r3, [r7, #28]
|
|
80182a8: 2b00 cmp r3, #0
|
|
80182aa: d102 bne.n 80182b2 <udp_sendto_if_src+0xf2>
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n"));
|
|
return ERR_MEM;
|
|
80182ac: f04f 33ff mov.w r3, #4294967295
|
|
80182b0: e057 b.n 8018362 <udp_sendto_if_src+0x1a2>
|
|
}
|
|
if (p->tot_len != 0) {
|
|
80182b2: 68bb ldr r3, [r7, #8]
|
|
80182b4: 891b ldrh r3, [r3, #8]
|
|
80182b6: 2b00 cmp r3, #0
|
|
80182b8: d006 beq.n 80182c8 <udp_sendto_if_src+0x108>
|
|
/* chain header q in front of given pbuf p (only if p contains data) */
|
|
pbuf_chain(q, p);
|
|
80182ba: 68b9 ldr r1, [r7, #8]
|
|
80182bc: 69f8 ldr r0, [r7, #28]
|
|
80182be: f7fa f8ef bl 80124a0 <pbuf_chain>
|
|
80182c2: e001 b.n 80182c8 <udp_sendto_if_src+0x108>
|
|
LWIP_DEBUGF(UDP_DEBUG,
|
|
("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p));
|
|
} else {
|
|
/* adding space for header within p succeeded */
|
|
/* first pbuf q equals given pbuf */
|
|
q = p;
|
|
80182c4: 68bb ldr r3, [r7, #8]
|
|
80182c6: 61fb str r3, [r7, #28]
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p));
|
|
}
|
|
LWIP_ASSERT("check that first pbuf can hold struct udp_hdr",
|
|
80182c8: 69fb ldr r3, [r7, #28]
|
|
80182ca: 895b ldrh r3, [r3, #10]
|
|
80182cc: 2b07 cmp r3, #7
|
|
80182ce: d806 bhi.n 80182de <udp_sendto_if_src+0x11e>
|
|
80182d0: 4b26 ldr r3, [pc, #152] ; (801836c <udp_sendto_if_src+0x1ac>)
|
|
80182d2: f240 320e movw r2, #782 ; 0x30e
|
|
80182d6: 492c ldr r1, [pc, #176] ; (8018388 <udp_sendto_if_src+0x1c8>)
|
|
80182d8: 4826 ldr r0, [pc, #152] ; (8018374 <udp_sendto_if_src+0x1b4>)
|
|
80182da: f004 fced bl 801ccb8 <iprintf>
|
|
(q->len >= sizeof(struct udp_hdr)));
|
|
/* q now represents the packet to be sent */
|
|
udphdr = (struct udp_hdr *)q->payload;
|
|
80182de: 69fb ldr r3, [r7, #28]
|
|
80182e0: 685b ldr r3, [r3, #4]
|
|
80182e2: 617b str r3, [r7, #20]
|
|
udphdr->src = lwip_htons(pcb->local_port);
|
|
80182e4: 68fb ldr r3, [r7, #12]
|
|
80182e6: 8a5b ldrh r3, [r3, #18]
|
|
80182e8: 4618 mov r0, r3
|
|
80182ea: f7f8 fc01 bl 8010af0 <lwip_htons>
|
|
80182ee: 4603 mov r3, r0
|
|
80182f0: 461a mov r2, r3
|
|
80182f2: 697b ldr r3, [r7, #20]
|
|
80182f4: 801a strh r2, [r3, #0]
|
|
udphdr->dest = lwip_htons(dst_port);
|
|
80182f6: 887b ldrh r3, [r7, #2]
|
|
80182f8: 4618 mov r0, r3
|
|
80182fa: f7f8 fbf9 bl 8010af0 <lwip_htons>
|
|
80182fe: 4603 mov r3, r0
|
|
8018300: 461a mov r2, r3
|
|
8018302: 697b ldr r3, [r7, #20]
|
|
8018304: 805a strh r2, [r3, #2]
|
|
/* in UDP, 0 checksum means 'no checksum' */
|
|
udphdr->chksum = 0x0000;
|
|
8018306: 697b ldr r3, [r7, #20]
|
|
8018308: 2200 movs r2, #0
|
|
801830a: 719a strb r2, [r3, #6]
|
|
801830c: 2200 movs r2, #0
|
|
801830e: 71da strb r2, [r3, #7]
|
|
ip_proto = IP_PROTO_UDPLITE;
|
|
} else
|
|
#endif /* LWIP_UDPLITE */
|
|
{ /* UDP */
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len));
|
|
udphdr->len = lwip_htons(q->tot_len);
|
|
8018310: 69fb ldr r3, [r7, #28]
|
|
8018312: 891b ldrh r3, [r3, #8]
|
|
8018314: 4618 mov r0, r3
|
|
8018316: f7f8 fbeb bl 8010af0 <lwip_htons>
|
|
801831a: 4603 mov r3, r0
|
|
801831c: 461a mov r2, r3
|
|
801831e: 697b ldr r3, [r7, #20]
|
|
8018320: 809a strh r2, [r3, #4]
|
|
}
|
|
udphdr->chksum = udpchksum;
|
|
}
|
|
}
|
|
#endif /* CHECKSUM_GEN_UDP */
|
|
ip_proto = IP_PROTO_UDP;
|
|
8018322: 2311 movs r3, #17
|
|
8018324: 74fb strb r3, [r7, #19]
|
|
|
|
/* Determine TTL to use */
|
|
#if LWIP_MULTICAST_TX_OPTIONS
|
|
ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl);
|
|
#else /* LWIP_MULTICAST_TX_OPTIONS */
|
|
ttl = pcb->ttl;
|
|
8018326: 68fb ldr r3, [r7, #12]
|
|
8018328: 7adb ldrb r3, [r3, #11]
|
|
801832a: 74bb strb r3, [r7, #18]
|
|
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum));
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto));
|
|
/* output to IP */
|
|
NETIF_SET_HINTS(netif, &(pcb->netif_hints));
|
|
err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif);
|
|
801832c: 68fb ldr r3, [r7, #12]
|
|
801832e: 7a9b ldrb r3, [r3, #10]
|
|
8018330: 7cb9 ldrb r1, [r7, #18]
|
|
8018332: 6aba ldr r2, [r7, #40] ; 0x28
|
|
8018334: 9202 str r2, [sp, #8]
|
|
8018336: 7cfa ldrb r2, [r7, #19]
|
|
8018338: 9201 str r2, [sp, #4]
|
|
801833a: 9300 str r3, [sp, #0]
|
|
801833c: 460b mov r3, r1
|
|
801833e: 687a ldr r2, [r7, #4]
|
|
8018340: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
8018342: 69f8 ldr r0, [r7, #28]
|
|
8018344: f003 fb48 bl 801b9d8 <ip4_output_if_src>
|
|
8018348: 4603 mov r3, r0
|
|
801834a: 76fb strb r3, [r7, #27]
|
|
|
|
/* @todo: must this be increased even if error occurred? */
|
|
MIB2_STATS_INC(mib2.udpoutdatagrams);
|
|
|
|
/* did we chain a separate header pbuf earlier? */
|
|
if (q != p) {
|
|
801834c: 69fa ldr r2, [r7, #28]
|
|
801834e: 68bb ldr r3, [r7, #8]
|
|
8018350: 429a cmp r2, r3
|
|
8018352: d004 beq.n 801835e <udp_sendto_if_src+0x19e>
|
|
/* free the header pbuf */
|
|
pbuf_free(q);
|
|
8018354: 69f8 ldr r0, [r7, #28]
|
|
8018356: f7f9 ff7f bl 8012258 <pbuf_free>
|
|
q = NULL;
|
|
801835a: 2300 movs r3, #0
|
|
801835c: 61fb str r3, [r7, #28]
|
|
/* p is still referenced by the caller, and will live on */
|
|
}
|
|
|
|
UDP_STATS_INC(udp.xmit);
|
|
return err;
|
|
801835e: f997 301b ldrsb.w r3, [r7, #27]
|
|
}
|
|
8018362: 4618 mov r0, r3
|
|
8018364: 3720 adds r7, #32
|
|
8018366: 46bd mov sp, r7
|
|
8018368: bd80 pop {r7, pc}
|
|
801836a: bf00 nop
|
|
801836c: 08020034 .word 0x08020034
|
|
8018370: 08020220 .word 0x08020220
|
|
8018374: 08020088 .word 0x08020088
|
|
8018378: 08020240 .word 0x08020240
|
|
801837c: 08020260 .word 0x08020260
|
|
8018380: 08020284 .word 0x08020284
|
|
8018384: 080202a8 .word 0x080202a8
|
|
8018388: 080202cc .word 0x080202cc
|
|
|
|
0801838c <udp_bind>:
|
|
*
|
|
* @see udp_disconnect()
|
|
*/
|
|
err_t
|
|
udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
|
|
{
|
|
801838c: b580 push {r7, lr}
|
|
801838e: b086 sub sp, #24
|
|
8018390: af00 add r7, sp, #0
|
|
8018392: 60f8 str r0, [r7, #12]
|
|
8018394: 60b9 str r1, [r7, #8]
|
|
8018396: 4613 mov r3, r2
|
|
8018398: 80fb strh r3, [r7, #6]
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
#if LWIP_IPV4
|
|
/* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */
|
|
if (ipaddr == NULL) {
|
|
801839a: 68bb ldr r3, [r7, #8]
|
|
801839c: 2b00 cmp r3, #0
|
|
801839e: d101 bne.n 80183a4 <udp_bind+0x18>
|
|
ipaddr = IP4_ADDR_ANY;
|
|
80183a0: 4b39 ldr r3, [pc, #228] ; (8018488 <udp_bind+0xfc>)
|
|
80183a2: 60bb str r3, [r7, #8]
|
|
}
|
|
#else /* LWIP_IPV4 */
|
|
LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
|
|
#endif /* LWIP_IPV4 */
|
|
|
|
LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
80183a4: 68fb ldr r3, [r7, #12]
|
|
80183a6: 2b00 cmp r3, #0
|
|
80183a8: d109 bne.n 80183be <udp_bind+0x32>
|
|
80183aa: 4b38 ldr r3, [pc, #224] ; (801848c <udp_bind+0x100>)
|
|
80183ac: f240 32b7 movw r2, #951 ; 0x3b7
|
|
80183b0: 4937 ldr r1, [pc, #220] ; (8018490 <udp_bind+0x104>)
|
|
80183b2: 4838 ldr r0, [pc, #224] ; (8018494 <udp_bind+0x108>)
|
|
80183b4: f004 fc80 bl 801ccb8 <iprintf>
|
|
80183b8: f06f 030f mvn.w r3, #15
|
|
80183bc: e060 b.n 8018480 <udp_bind+0xf4>
|
|
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = "));
|
|
ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr);
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port));
|
|
|
|
rebind = 0;
|
|
80183be: 2300 movs r3, #0
|
|
80183c0: 74fb strb r3, [r7, #19]
|
|
/* Check for double bind and rebind of the same pcb */
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
80183c2: 4b35 ldr r3, [pc, #212] ; (8018498 <udp_bind+0x10c>)
|
|
80183c4: 681b ldr r3, [r3, #0]
|
|
80183c6: 617b str r3, [r7, #20]
|
|
80183c8: e009 b.n 80183de <udp_bind+0x52>
|
|
/* is this UDP PCB already on active list? */
|
|
if (pcb == ipcb) {
|
|
80183ca: 68fa ldr r2, [r7, #12]
|
|
80183cc: 697b ldr r3, [r7, #20]
|
|
80183ce: 429a cmp r2, r3
|
|
80183d0: d102 bne.n 80183d8 <udp_bind+0x4c>
|
|
rebind = 1;
|
|
80183d2: 2301 movs r3, #1
|
|
80183d4: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80183d6: e005 b.n 80183e4 <udp_bind+0x58>
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
80183d8: 697b ldr r3, [r7, #20]
|
|
80183da: 68db ldr r3, [r3, #12]
|
|
80183dc: 617b str r3, [r7, #20]
|
|
80183de: 697b ldr r3, [r7, #20]
|
|
80183e0: 2b00 cmp r3, #0
|
|
80183e2: d1f2 bne.n 80183ca <udp_bind+0x3e>
|
|
ipaddr = &zoned_ipaddr;
|
|
}
|
|
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
|
|
|
|
/* no port specified? */
|
|
if (port == 0) {
|
|
80183e4: 88fb ldrh r3, [r7, #6]
|
|
80183e6: 2b00 cmp r3, #0
|
|
80183e8: d109 bne.n 80183fe <udp_bind+0x72>
|
|
port = udp_new_port();
|
|
80183ea: f7ff fcc5 bl 8017d78 <udp_new_port>
|
|
80183ee: 4603 mov r3, r0
|
|
80183f0: 80fb strh r3, [r7, #6]
|
|
if (port == 0) {
|
|
80183f2: 88fb ldrh r3, [r7, #6]
|
|
80183f4: 2b00 cmp r3, #0
|
|
80183f6: d12c bne.n 8018452 <udp_bind+0xc6>
|
|
/* no more ports available in local range */
|
|
LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n"));
|
|
return ERR_USE;
|
|
80183f8: f06f 0307 mvn.w r3, #7
|
|
80183fc: e040 b.n 8018480 <udp_bind+0xf4>
|
|
}
|
|
} else {
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
80183fe: 4b26 ldr r3, [pc, #152] ; (8018498 <udp_bind+0x10c>)
|
|
8018400: 681b ldr r3, [r3, #0]
|
|
8018402: 617b str r3, [r7, #20]
|
|
8018404: e022 b.n 801844c <udp_bind+0xc0>
|
|
if (pcb != ipcb) {
|
|
8018406: 68fa ldr r2, [r7, #12]
|
|
8018408: 697b ldr r3, [r7, #20]
|
|
801840a: 429a cmp r2, r3
|
|
801840c: d01b beq.n 8018446 <udp_bind+0xba>
|
|
if (!ip_get_option(pcb, SOF_REUSEADDR) ||
|
|
!ip_get_option(ipcb, SOF_REUSEADDR))
|
|
#endif /* SO_REUSE */
|
|
{
|
|
/* port matches that of PCB in list and REUSEADDR not set -> reject */
|
|
if ((ipcb->local_port == port) &&
|
|
801840e: 697b ldr r3, [r7, #20]
|
|
8018410: 8a5b ldrh r3, [r3, #18]
|
|
8018412: 88fa ldrh r2, [r7, #6]
|
|
8018414: 429a cmp r2, r3
|
|
8018416: d116 bne.n 8018446 <udp_bind+0xba>
|
|
/* IP address matches or any IP used? */
|
|
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
|
|
8018418: 697b ldr r3, [r7, #20]
|
|
801841a: 681a ldr r2, [r3, #0]
|
|
801841c: 68bb ldr r3, [r7, #8]
|
|
801841e: 681b ldr r3, [r3, #0]
|
|
if ((ipcb->local_port == port) &&
|
|
8018420: 429a cmp r2, r3
|
|
8018422: d00d beq.n 8018440 <udp_bind+0xb4>
|
|
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
|
|
8018424: 68bb ldr r3, [r7, #8]
|
|
8018426: 2b00 cmp r3, #0
|
|
8018428: d00a beq.n 8018440 <udp_bind+0xb4>
|
|
801842a: 68bb ldr r3, [r7, #8]
|
|
801842c: 681b ldr r3, [r3, #0]
|
|
801842e: 2b00 cmp r3, #0
|
|
8018430: d006 beq.n 8018440 <udp_bind+0xb4>
|
|
ip_addr_isany(&ipcb->local_ip))) {
|
|
8018432: 697b ldr r3, [r7, #20]
|
|
(ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) ||
|
|
8018434: 2b00 cmp r3, #0
|
|
8018436: d003 beq.n 8018440 <udp_bind+0xb4>
|
|
ip_addr_isany(&ipcb->local_ip))) {
|
|
8018438: 697b ldr r3, [r7, #20]
|
|
801843a: 681b ldr r3, [r3, #0]
|
|
801843c: 2b00 cmp r3, #0
|
|
801843e: d102 bne.n 8018446 <udp_bind+0xba>
|
|
/* other PCB already binds to this local IP and port */
|
|
LWIP_DEBUGF(UDP_DEBUG,
|
|
("udp_bind: local port %"U16_F" already bound by another pcb\n", port));
|
|
return ERR_USE;
|
|
8018440: f06f 0307 mvn.w r3, #7
|
|
8018444: e01c b.n 8018480 <udp_bind+0xf4>
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
8018446: 697b ldr r3, [r7, #20]
|
|
8018448: 68db ldr r3, [r3, #12]
|
|
801844a: 617b str r3, [r7, #20]
|
|
801844c: 697b ldr r3, [r7, #20]
|
|
801844e: 2b00 cmp r3, #0
|
|
8018450: d1d9 bne.n 8018406 <udp_bind+0x7a>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
ip_addr_set_ipaddr(&pcb->local_ip, ipaddr);
|
|
8018452: 68bb ldr r3, [r7, #8]
|
|
8018454: 2b00 cmp r3, #0
|
|
8018456: d002 beq.n 801845e <udp_bind+0xd2>
|
|
8018458: 68bb ldr r3, [r7, #8]
|
|
801845a: 681b ldr r3, [r3, #0]
|
|
801845c: e000 b.n 8018460 <udp_bind+0xd4>
|
|
801845e: 2300 movs r3, #0
|
|
8018460: 68fa ldr r2, [r7, #12]
|
|
8018462: 6013 str r3, [r2, #0]
|
|
|
|
pcb->local_port = port;
|
|
8018464: 68fb ldr r3, [r7, #12]
|
|
8018466: 88fa ldrh r2, [r7, #6]
|
|
8018468: 825a strh r2, [r3, #18]
|
|
mib2_udp_bind(pcb);
|
|
/* pcb not active yet? */
|
|
if (rebind == 0) {
|
|
801846a: 7cfb ldrb r3, [r7, #19]
|
|
801846c: 2b00 cmp r3, #0
|
|
801846e: d106 bne.n 801847e <udp_bind+0xf2>
|
|
/* place the PCB on the active list if not already there */
|
|
pcb->next = udp_pcbs;
|
|
8018470: 4b09 ldr r3, [pc, #36] ; (8018498 <udp_bind+0x10c>)
|
|
8018472: 681a ldr r2, [r3, #0]
|
|
8018474: 68fb ldr r3, [r7, #12]
|
|
8018476: 60da str r2, [r3, #12]
|
|
udp_pcbs = pcb;
|
|
8018478: 4a07 ldr r2, [pc, #28] ; (8018498 <udp_bind+0x10c>)
|
|
801847a: 68fb ldr r3, [r7, #12]
|
|
801847c: 6013 str r3, [r2, #0]
|
|
}
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to "));
|
|
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip);
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port));
|
|
return ERR_OK;
|
|
801847e: 2300 movs r3, #0
|
|
}
|
|
8018480: 4618 mov r0, r3
|
|
8018482: 3718 adds r7, #24
|
|
8018484: 46bd mov sp, r7
|
|
8018486: bd80 pop {r7, pc}
|
|
8018488: 08022e68 .word 0x08022e68
|
|
801848c: 08020034 .word 0x08020034
|
|
8018490: 080202fc .word 0x080202fc
|
|
8018494: 08020088 .word 0x08020088
|
|
8018498: 2000f814 .word 0x2000f814
|
|
|
|
0801849c <udp_connect>:
|
|
*
|
|
* @see udp_disconnect()
|
|
*/
|
|
err_t
|
|
udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port)
|
|
{
|
|
801849c: b580 push {r7, lr}
|
|
801849e: b086 sub sp, #24
|
|
80184a0: af00 add r7, sp, #0
|
|
80184a2: 60f8 str r0, [r7, #12]
|
|
80184a4: 60b9 str r1, [r7, #8]
|
|
80184a6: 4613 mov r3, r2
|
|
80184a8: 80fb strh r3, [r7, #6]
|
|
struct udp_pcb *ipcb;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG);
|
|
80184aa: 68fb ldr r3, [r7, #12]
|
|
80184ac: 2b00 cmp r3, #0
|
|
80184ae: d109 bne.n 80184c4 <udp_connect+0x28>
|
|
80184b0: 4b2c ldr r3, [pc, #176] ; (8018564 <udp_connect+0xc8>)
|
|
80184b2: f240 4235 movw r2, #1077 ; 0x435
|
|
80184b6: 492c ldr r1, [pc, #176] ; (8018568 <udp_connect+0xcc>)
|
|
80184b8: 482c ldr r0, [pc, #176] ; (801856c <udp_connect+0xd0>)
|
|
80184ba: f004 fbfd bl 801ccb8 <iprintf>
|
|
80184be: f06f 030f mvn.w r3, #15
|
|
80184c2: e04b b.n 801855c <udp_connect+0xc0>
|
|
LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG);
|
|
80184c4: 68bb ldr r3, [r7, #8]
|
|
80184c6: 2b00 cmp r3, #0
|
|
80184c8: d109 bne.n 80184de <udp_connect+0x42>
|
|
80184ca: 4b26 ldr r3, [pc, #152] ; (8018564 <udp_connect+0xc8>)
|
|
80184cc: f240 4236 movw r2, #1078 ; 0x436
|
|
80184d0: 4927 ldr r1, [pc, #156] ; (8018570 <udp_connect+0xd4>)
|
|
80184d2: 4826 ldr r0, [pc, #152] ; (801856c <udp_connect+0xd0>)
|
|
80184d4: f004 fbf0 bl 801ccb8 <iprintf>
|
|
80184d8: f06f 030f mvn.w r3, #15
|
|
80184dc: e03e b.n 801855c <udp_connect+0xc0>
|
|
|
|
if (pcb->local_port == 0) {
|
|
80184de: 68fb ldr r3, [r7, #12]
|
|
80184e0: 8a5b ldrh r3, [r3, #18]
|
|
80184e2: 2b00 cmp r3, #0
|
|
80184e4: d10f bne.n 8018506 <udp_connect+0x6a>
|
|
err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port);
|
|
80184e6: 68f9 ldr r1, [r7, #12]
|
|
80184e8: 68fb ldr r3, [r7, #12]
|
|
80184ea: 8a5b ldrh r3, [r3, #18]
|
|
80184ec: 461a mov r2, r3
|
|
80184ee: 68f8 ldr r0, [r7, #12]
|
|
80184f0: f7ff ff4c bl 801838c <udp_bind>
|
|
80184f4: 4603 mov r3, r0
|
|
80184f6: 74fb strb r3, [r7, #19]
|
|
if (err != ERR_OK) {
|
|
80184f8: f997 3013 ldrsb.w r3, [r7, #19]
|
|
80184fc: 2b00 cmp r3, #0
|
|
80184fe: d002 beq.n 8018506 <udp_connect+0x6a>
|
|
return err;
|
|
8018500: f997 3013 ldrsb.w r3, [r7, #19]
|
|
8018504: e02a b.n 801855c <udp_connect+0xc0>
|
|
}
|
|
}
|
|
|
|
ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr);
|
|
8018506: 68bb ldr r3, [r7, #8]
|
|
8018508: 2b00 cmp r3, #0
|
|
801850a: d002 beq.n 8018512 <udp_connect+0x76>
|
|
801850c: 68bb ldr r3, [r7, #8]
|
|
801850e: 681b ldr r3, [r3, #0]
|
|
8018510: e000 b.n 8018514 <udp_connect+0x78>
|
|
8018512: 2300 movs r3, #0
|
|
8018514: 68fa ldr r2, [r7, #12]
|
|
8018516: 6053 str r3, [r2, #4]
|
|
ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) {
|
|
ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip));
|
|
}
|
|
#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */
|
|
|
|
pcb->remote_port = port;
|
|
8018518: 68fb ldr r3, [r7, #12]
|
|
801851a: 88fa ldrh r2, [r7, #6]
|
|
801851c: 829a strh r2, [r3, #20]
|
|
pcb->flags |= UDP_FLAGS_CONNECTED;
|
|
801851e: 68fb ldr r3, [r7, #12]
|
|
8018520: 7c1b ldrb r3, [r3, #16]
|
|
8018522: f043 0304 orr.w r3, r3, #4
|
|
8018526: b2da uxtb r2, r3
|
|
8018528: 68fb ldr r3, [r7, #12]
|
|
801852a: 741a strb r2, [r3, #16]
|
|
ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
|
|
pcb->remote_ip);
|
|
LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port));
|
|
|
|
/* Insert UDP PCB into the list of active UDP PCBs. */
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
801852c: 4b11 ldr r3, [pc, #68] ; (8018574 <udp_connect+0xd8>)
|
|
801852e: 681b ldr r3, [r3, #0]
|
|
8018530: 617b str r3, [r7, #20]
|
|
8018532: e008 b.n 8018546 <udp_connect+0xaa>
|
|
if (pcb == ipcb) {
|
|
8018534: 68fa ldr r2, [r7, #12]
|
|
8018536: 697b ldr r3, [r7, #20]
|
|
8018538: 429a cmp r2, r3
|
|
801853a: d101 bne.n 8018540 <udp_connect+0xa4>
|
|
/* already on the list, just return */
|
|
return ERR_OK;
|
|
801853c: 2300 movs r3, #0
|
|
801853e: e00d b.n 801855c <udp_connect+0xc0>
|
|
for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) {
|
|
8018540: 697b ldr r3, [r7, #20]
|
|
8018542: 68db ldr r3, [r3, #12]
|
|
8018544: 617b str r3, [r7, #20]
|
|
8018546: 697b ldr r3, [r7, #20]
|
|
8018548: 2b00 cmp r3, #0
|
|
801854a: d1f3 bne.n 8018534 <udp_connect+0x98>
|
|
}
|
|
}
|
|
/* PCB not yet on the list, add PCB now */
|
|
pcb->next = udp_pcbs;
|
|
801854c: 4b09 ldr r3, [pc, #36] ; (8018574 <udp_connect+0xd8>)
|
|
801854e: 681a ldr r2, [r3, #0]
|
|
8018550: 68fb ldr r3, [r7, #12]
|
|
8018552: 60da str r2, [r3, #12]
|
|
udp_pcbs = pcb;
|
|
8018554: 4a07 ldr r2, [pc, #28] ; (8018574 <udp_connect+0xd8>)
|
|
8018556: 68fb ldr r3, [r7, #12]
|
|
8018558: 6013 str r3, [r2, #0]
|
|
return ERR_OK;
|
|
801855a: 2300 movs r3, #0
|
|
}
|
|
801855c: 4618 mov r0, r3
|
|
801855e: 3718 adds r7, #24
|
|
8018560: 46bd mov sp, r7
|
|
8018562: bd80 pop {r7, pc}
|
|
8018564: 08020034 .word 0x08020034
|
|
8018568: 08020314 .word 0x08020314
|
|
801856c: 08020088 .word 0x08020088
|
|
8018570: 08020330 .word 0x08020330
|
|
8018574: 2000f814 .word 0x2000f814
|
|
|
|
08018578 <udp_recv>:
|
|
* @param recv function pointer of the callback function
|
|
* @param recv_arg additional argument to pass to the callback function
|
|
*/
|
|
void
|
|
udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg)
|
|
{
|
|
8018578: b580 push {r7, lr}
|
|
801857a: b084 sub sp, #16
|
|
801857c: af00 add r7, sp, #0
|
|
801857e: 60f8 str r0, [r7, #12]
|
|
8018580: 60b9 str r1, [r7, #8]
|
|
8018582: 607a str r2, [r7, #4]
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return);
|
|
8018584: 68fb ldr r3, [r7, #12]
|
|
8018586: 2b00 cmp r3, #0
|
|
8018588: d107 bne.n 801859a <udp_recv+0x22>
|
|
801858a: 4b08 ldr r3, [pc, #32] ; (80185ac <udp_recv+0x34>)
|
|
801858c: f240 428a movw r2, #1162 ; 0x48a
|
|
8018590: 4907 ldr r1, [pc, #28] ; (80185b0 <udp_recv+0x38>)
|
|
8018592: 4808 ldr r0, [pc, #32] ; (80185b4 <udp_recv+0x3c>)
|
|
8018594: f004 fb90 bl 801ccb8 <iprintf>
|
|
8018598: e005 b.n 80185a6 <udp_recv+0x2e>
|
|
|
|
/* remember recv() callback and user data */
|
|
pcb->recv = recv;
|
|
801859a: 68fb ldr r3, [r7, #12]
|
|
801859c: 68ba ldr r2, [r7, #8]
|
|
801859e: 619a str r2, [r3, #24]
|
|
pcb->recv_arg = recv_arg;
|
|
80185a0: 68fb ldr r3, [r7, #12]
|
|
80185a2: 687a ldr r2, [r7, #4]
|
|
80185a4: 61da str r2, [r3, #28]
|
|
}
|
|
80185a6: 3710 adds r7, #16
|
|
80185a8: 46bd mov sp, r7
|
|
80185aa: bd80 pop {r7, pc}
|
|
80185ac: 08020034 .word 0x08020034
|
|
80185b0: 08020368 .word 0x08020368
|
|
80185b4: 08020088 .word 0x08020088
|
|
|
|
080185b8 <udp_remove>:
|
|
*
|
|
* @see udp_new()
|
|
*/
|
|
void
|
|
udp_remove(struct udp_pcb *pcb)
|
|
{
|
|
80185b8: b580 push {r7, lr}
|
|
80185ba: b084 sub sp, #16
|
|
80185bc: af00 add r7, sp, #0
|
|
80185be: 6078 str r0, [r7, #4]
|
|
struct udp_pcb *pcb2;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return);
|
|
80185c0: 687b ldr r3, [r7, #4]
|
|
80185c2: 2b00 cmp r3, #0
|
|
80185c4: d107 bne.n 80185d6 <udp_remove+0x1e>
|
|
80185c6: 4b19 ldr r3, [pc, #100] ; (801862c <udp_remove+0x74>)
|
|
80185c8: f240 42a1 movw r2, #1185 ; 0x4a1
|
|
80185cc: 4918 ldr r1, [pc, #96] ; (8018630 <udp_remove+0x78>)
|
|
80185ce: 4819 ldr r0, [pc, #100] ; (8018634 <udp_remove+0x7c>)
|
|
80185d0: f004 fb72 bl 801ccb8 <iprintf>
|
|
80185d4: e026 b.n 8018624 <udp_remove+0x6c>
|
|
|
|
mib2_udp_unbind(pcb);
|
|
/* pcb to be removed is first in list? */
|
|
if (udp_pcbs == pcb) {
|
|
80185d6: 4b18 ldr r3, [pc, #96] ; (8018638 <udp_remove+0x80>)
|
|
80185d8: 681b ldr r3, [r3, #0]
|
|
80185da: 687a ldr r2, [r7, #4]
|
|
80185dc: 429a cmp r2, r3
|
|
80185de: d105 bne.n 80185ec <udp_remove+0x34>
|
|
/* make list start at 2nd pcb */
|
|
udp_pcbs = udp_pcbs->next;
|
|
80185e0: 4b15 ldr r3, [pc, #84] ; (8018638 <udp_remove+0x80>)
|
|
80185e2: 681b ldr r3, [r3, #0]
|
|
80185e4: 68db ldr r3, [r3, #12]
|
|
80185e6: 4a14 ldr r2, [pc, #80] ; (8018638 <udp_remove+0x80>)
|
|
80185e8: 6013 str r3, [r2, #0]
|
|
80185ea: e017 b.n 801861c <udp_remove+0x64>
|
|
/* pcb not 1st in list */
|
|
} else {
|
|
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
|
|
80185ec: 4b12 ldr r3, [pc, #72] ; (8018638 <udp_remove+0x80>)
|
|
80185ee: 681b ldr r3, [r3, #0]
|
|
80185f0: 60fb str r3, [r7, #12]
|
|
80185f2: e010 b.n 8018616 <udp_remove+0x5e>
|
|
/* find pcb in udp_pcbs list */
|
|
if (pcb2->next != NULL && pcb2->next == pcb) {
|
|
80185f4: 68fb ldr r3, [r7, #12]
|
|
80185f6: 68db ldr r3, [r3, #12]
|
|
80185f8: 2b00 cmp r3, #0
|
|
80185fa: d009 beq.n 8018610 <udp_remove+0x58>
|
|
80185fc: 68fb ldr r3, [r7, #12]
|
|
80185fe: 68db ldr r3, [r3, #12]
|
|
8018600: 687a ldr r2, [r7, #4]
|
|
8018602: 429a cmp r2, r3
|
|
8018604: d104 bne.n 8018610 <udp_remove+0x58>
|
|
/* remove pcb from list */
|
|
pcb2->next = pcb->next;
|
|
8018606: 687b ldr r3, [r7, #4]
|
|
8018608: 68da ldr r2, [r3, #12]
|
|
801860a: 68fb ldr r3, [r7, #12]
|
|
801860c: 60da str r2, [r3, #12]
|
|
break;
|
|
801860e: e005 b.n 801861c <udp_remove+0x64>
|
|
for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) {
|
|
8018610: 68fb ldr r3, [r7, #12]
|
|
8018612: 68db ldr r3, [r3, #12]
|
|
8018614: 60fb str r3, [r7, #12]
|
|
8018616: 68fb ldr r3, [r7, #12]
|
|
8018618: 2b00 cmp r3, #0
|
|
801861a: d1eb bne.n 80185f4 <udp_remove+0x3c>
|
|
}
|
|
}
|
|
}
|
|
memp_free(MEMP_UDP_PCB, pcb);
|
|
801861c: 6879 ldr r1, [r7, #4]
|
|
801861e: 2000 movs r0, #0
|
|
8018620: f7f8 ff6e bl 8011500 <memp_free>
|
|
}
|
|
8018624: 3710 adds r7, #16
|
|
8018626: 46bd mov sp, r7
|
|
8018628: bd80 pop {r7, pc}
|
|
801862a: bf00 nop
|
|
801862c: 08020034 .word 0x08020034
|
|
8018630: 08020380 .word 0x08020380
|
|
8018634: 08020088 .word 0x08020088
|
|
8018638: 2000f814 .word 0x2000f814
|
|
|
|
0801863c <udp_new>:
|
|
*
|
|
* @see udp_remove()
|
|
*/
|
|
struct udp_pcb *
|
|
udp_new(void)
|
|
{
|
|
801863c: b580 push {r7, lr}
|
|
801863e: b082 sub sp, #8
|
|
8018640: af00 add r7, sp, #0
|
|
struct udp_pcb *pcb;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB);
|
|
8018642: 2000 movs r0, #0
|
|
8018644: f7f8 ff0a bl 801145c <memp_malloc>
|
|
8018648: 6078 str r0, [r7, #4]
|
|
/* could allocate UDP PCB? */
|
|
if (pcb != NULL) {
|
|
801864a: 687b ldr r3, [r7, #4]
|
|
801864c: 2b00 cmp r3, #0
|
|
801864e: d007 beq.n 8018660 <udp_new+0x24>
|
|
/* UDP Lite: by initializing to all zeroes, chksum_len is set to 0
|
|
* which means checksum is generated over the whole datagram per default
|
|
* (recommended as default by RFC 3828). */
|
|
/* initialize PCB to all zeroes */
|
|
memset(pcb, 0, sizeof(struct udp_pcb));
|
|
8018650: 2220 movs r2, #32
|
|
8018652: 2100 movs r1, #0
|
|
8018654: 6878 ldr r0, [r7, #4]
|
|
8018656: f004 fb26 bl 801cca6 <memset>
|
|
pcb->ttl = UDP_TTL;
|
|
801865a: 687b ldr r3, [r7, #4]
|
|
801865c: 22ff movs r2, #255 ; 0xff
|
|
801865e: 72da strb r2, [r3, #11]
|
|
#if LWIP_MULTICAST_TX_OPTIONS
|
|
udp_set_multicast_ttl(pcb, UDP_TTL);
|
|
#endif /* LWIP_MULTICAST_TX_OPTIONS */
|
|
}
|
|
return pcb;
|
|
8018660: 687b ldr r3, [r7, #4]
|
|
}
|
|
8018662: 4618 mov r0, r3
|
|
8018664: 3708 adds r7, #8
|
|
8018666: 46bd mov sp, r7
|
|
8018668: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0801866c <udp_netif_ip_addr_changed>:
|
|
*
|
|
* @param old_addr IP address of the netif before change
|
|
* @param new_addr IP address of the netif after change
|
|
*/
|
|
void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr)
|
|
{
|
|
801866c: b480 push {r7}
|
|
801866e: b085 sub sp, #20
|
|
8018670: af00 add r7, sp, #0
|
|
8018672: 6078 str r0, [r7, #4]
|
|
8018674: 6039 str r1, [r7, #0]
|
|
struct udp_pcb *upcb;
|
|
|
|
if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) {
|
|
8018676: 687b ldr r3, [r7, #4]
|
|
8018678: 2b00 cmp r3, #0
|
|
801867a: d01e beq.n 80186ba <udp_netif_ip_addr_changed+0x4e>
|
|
801867c: 687b ldr r3, [r7, #4]
|
|
801867e: 681b ldr r3, [r3, #0]
|
|
8018680: 2b00 cmp r3, #0
|
|
8018682: d01a beq.n 80186ba <udp_netif_ip_addr_changed+0x4e>
|
|
8018684: 683b ldr r3, [r7, #0]
|
|
8018686: 2b00 cmp r3, #0
|
|
8018688: d017 beq.n 80186ba <udp_netif_ip_addr_changed+0x4e>
|
|
801868a: 683b ldr r3, [r7, #0]
|
|
801868c: 681b ldr r3, [r3, #0]
|
|
801868e: 2b00 cmp r3, #0
|
|
8018690: d013 beq.n 80186ba <udp_netif_ip_addr_changed+0x4e>
|
|
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
|
|
8018692: 4b0d ldr r3, [pc, #52] ; (80186c8 <udp_netif_ip_addr_changed+0x5c>)
|
|
8018694: 681b ldr r3, [r3, #0]
|
|
8018696: 60fb str r3, [r7, #12]
|
|
8018698: e00c b.n 80186b4 <udp_netif_ip_addr_changed+0x48>
|
|
/* PCB bound to current local interface address? */
|
|
if (ip_addr_cmp(&upcb->local_ip, old_addr)) {
|
|
801869a: 68fb ldr r3, [r7, #12]
|
|
801869c: 681a ldr r2, [r3, #0]
|
|
801869e: 687b ldr r3, [r7, #4]
|
|
80186a0: 681b ldr r3, [r3, #0]
|
|
80186a2: 429a cmp r2, r3
|
|
80186a4: d103 bne.n 80186ae <udp_netif_ip_addr_changed+0x42>
|
|
/* The PCB is bound to the old ipaddr and
|
|
* is set to bound to the new one instead */
|
|
ip_addr_copy(upcb->local_ip, *new_addr);
|
|
80186a6: 683b ldr r3, [r7, #0]
|
|
80186a8: 681a ldr r2, [r3, #0]
|
|
80186aa: 68fb ldr r3, [r7, #12]
|
|
80186ac: 601a str r2, [r3, #0]
|
|
for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) {
|
|
80186ae: 68fb ldr r3, [r7, #12]
|
|
80186b0: 68db ldr r3, [r3, #12]
|
|
80186b2: 60fb str r3, [r7, #12]
|
|
80186b4: 68fb ldr r3, [r7, #12]
|
|
80186b6: 2b00 cmp r3, #0
|
|
80186b8: d1ef bne.n 801869a <udp_netif_ip_addr_changed+0x2e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
80186ba: bf00 nop
|
|
80186bc: 3714 adds r7, #20
|
|
80186be: 46bd mov sp, r7
|
|
80186c0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80186c4: 4770 bx lr
|
|
80186c6: bf00 nop
|
|
80186c8: 2000f814 .word 0x2000f814
|
|
|
|
080186cc <dhcp_inc_pcb_refcount>:
|
|
static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out);
|
|
|
|
/** Ensure DHCP PCB is allocated and bound */
|
|
static err_t
|
|
dhcp_inc_pcb_refcount(void)
|
|
{
|
|
80186cc: b580 push {r7, lr}
|
|
80186ce: af00 add r7, sp, #0
|
|
if (dhcp_pcb_refcount == 0) {
|
|
80186d0: 4b20 ldr r3, [pc, #128] ; (8018754 <dhcp_inc_pcb_refcount+0x88>)
|
|
80186d2: 781b ldrb r3, [r3, #0]
|
|
80186d4: 2b00 cmp r3, #0
|
|
80186d6: d133 bne.n 8018740 <dhcp_inc_pcb_refcount+0x74>
|
|
LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL);
|
|
80186d8: 4b1f ldr r3, [pc, #124] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
80186da: 681b ldr r3, [r3, #0]
|
|
80186dc: 2b00 cmp r3, #0
|
|
80186de: d005 beq.n 80186ec <dhcp_inc_pcb_refcount+0x20>
|
|
80186e0: 4b1e ldr r3, [pc, #120] ; (801875c <dhcp_inc_pcb_refcount+0x90>)
|
|
80186e2: 22e5 movs r2, #229 ; 0xe5
|
|
80186e4: 491e ldr r1, [pc, #120] ; (8018760 <dhcp_inc_pcb_refcount+0x94>)
|
|
80186e6: 481f ldr r0, [pc, #124] ; (8018764 <dhcp_inc_pcb_refcount+0x98>)
|
|
80186e8: f004 fae6 bl 801ccb8 <iprintf>
|
|
|
|
/* allocate UDP PCB */
|
|
dhcp_pcb = udp_new();
|
|
80186ec: f7ff ffa6 bl 801863c <udp_new>
|
|
80186f0: 4602 mov r2, r0
|
|
80186f2: 4b19 ldr r3, [pc, #100] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
80186f4: 601a str r2, [r3, #0]
|
|
|
|
if (dhcp_pcb == NULL) {
|
|
80186f6: 4b18 ldr r3, [pc, #96] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
80186f8: 681b ldr r3, [r3, #0]
|
|
80186fa: 2b00 cmp r3, #0
|
|
80186fc: d102 bne.n 8018704 <dhcp_inc_pcb_refcount+0x38>
|
|
return ERR_MEM;
|
|
80186fe: f04f 33ff mov.w r3, #4294967295
|
|
8018702: e024 b.n 801874e <dhcp_inc_pcb_refcount+0x82>
|
|
}
|
|
|
|
ip_set_option(dhcp_pcb, SOF_BROADCAST);
|
|
8018704: 4b14 ldr r3, [pc, #80] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
8018706: 681b ldr r3, [r3, #0]
|
|
8018708: 7a5a ldrb r2, [r3, #9]
|
|
801870a: 4b13 ldr r3, [pc, #76] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
801870c: 681b ldr r3, [r3, #0]
|
|
801870e: f042 0220 orr.w r2, r2, #32
|
|
8018712: b2d2 uxtb r2, r2
|
|
8018714: 725a strb r2, [r3, #9]
|
|
|
|
/* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */
|
|
udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT);
|
|
8018716: 4b10 ldr r3, [pc, #64] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
8018718: 681b ldr r3, [r3, #0]
|
|
801871a: 2244 movs r2, #68 ; 0x44
|
|
801871c: 4912 ldr r1, [pc, #72] ; (8018768 <dhcp_inc_pcb_refcount+0x9c>)
|
|
801871e: 4618 mov r0, r3
|
|
8018720: f7ff fe34 bl 801838c <udp_bind>
|
|
udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER);
|
|
8018724: 4b0c ldr r3, [pc, #48] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
8018726: 681b ldr r3, [r3, #0]
|
|
8018728: 2243 movs r2, #67 ; 0x43
|
|
801872a: 490f ldr r1, [pc, #60] ; (8018768 <dhcp_inc_pcb_refcount+0x9c>)
|
|
801872c: 4618 mov r0, r3
|
|
801872e: f7ff feb5 bl 801849c <udp_connect>
|
|
udp_recv(dhcp_pcb, dhcp_recv, NULL);
|
|
8018732: 4b09 ldr r3, [pc, #36] ; (8018758 <dhcp_inc_pcb_refcount+0x8c>)
|
|
8018734: 681b ldr r3, [r3, #0]
|
|
8018736: 2200 movs r2, #0
|
|
8018738: 490c ldr r1, [pc, #48] ; (801876c <dhcp_inc_pcb_refcount+0xa0>)
|
|
801873a: 4618 mov r0, r3
|
|
801873c: f7ff ff1c bl 8018578 <udp_recv>
|
|
}
|
|
|
|
dhcp_pcb_refcount++;
|
|
8018740: 4b04 ldr r3, [pc, #16] ; (8018754 <dhcp_inc_pcb_refcount+0x88>)
|
|
8018742: 781b ldrb r3, [r3, #0]
|
|
8018744: 3301 adds r3, #1
|
|
8018746: b2da uxtb r2, r3
|
|
8018748: 4b02 ldr r3, [pc, #8] ; (8018754 <dhcp_inc_pcb_refcount+0x88>)
|
|
801874a: 701a strb r2, [r3, #0]
|
|
|
|
return ERR_OK;
|
|
801874c: 2300 movs r3, #0
|
|
}
|
|
801874e: 4618 mov r0, r3
|
|
8018750: bd80 pop {r7, pc}
|
|
8018752: bf00 nop
|
|
8018754: 20008770 .word 0x20008770
|
|
8018758: 2000876c .word 0x2000876c
|
|
801875c: 08020398 .word 0x08020398
|
|
8018760: 080203d0 .word 0x080203d0
|
|
8018764: 080203f8 .word 0x080203f8
|
|
8018768: 08022e68 .word 0x08022e68
|
|
801876c: 0801a029 .word 0x0801a029
|
|
|
|
08018770 <dhcp_dec_pcb_refcount>:
|
|
|
|
/** Free DHCP PCB if the last netif stops using it */
|
|
static void
|
|
dhcp_dec_pcb_refcount(void)
|
|
{
|
|
8018770: b580 push {r7, lr}
|
|
8018772: af00 add r7, sp, #0
|
|
LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0));
|
|
8018774: 4b0e ldr r3, [pc, #56] ; (80187b0 <dhcp_dec_pcb_refcount+0x40>)
|
|
8018776: 781b ldrb r3, [r3, #0]
|
|
8018778: 2b00 cmp r3, #0
|
|
801877a: d105 bne.n 8018788 <dhcp_dec_pcb_refcount+0x18>
|
|
801877c: 4b0d ldr r3, [pc, #52] ; (80187b4 <dhcp_dec_pcb_refcount+0x44>)
|
|
801877e: 22ff movs r2, #255 ; 0xff
|
|
8018780: 490d ldr r1, [pc, #52] ; (80187b8 <dhcp_dec_pcb_refcount+0x48>)
|
|
8018782: 480e ldr r0, [pc, #56] ; (80187bc <dhcp_dec_pcb_refcount+0x4c>)
|
|
8018784: f004 fa98 bl 801ccb8 <iprintf>
|
|
dhcp_pcb_refcount--;
|
|
8018788: 4b09 ldr r3, [pc, #36] ; (80187b0 <dhcp_dec_pcb_refcount+0x40>)
|
|
801878a: 781b ldrb r3, [r3, #0]
|
|
801878c: 3b01 subs r3, #1
|
|
801878e: b2da uxtb r2, r3
|
|
8018790: 4b07 ldr r3, [pc, #28] ; (80187b0 <dhcp_dec_pcb_refcount+0x40>)
|
|
8018792: 701a strb r2, [r3, #0]
|
|
|
|
if (dhcp_pcb_refcount == 0) {
|
|
8018794: 4b06 ldr r3, [pc, #24] ; (80187b0 <dhcp_dec_pcb_refcount+0x40>)
|
|
8018796: 781b ldrb r3, [r3, #0]
|
|
8018798: 2b00 cmp r3, #0
|
|
801879a: d107 bne.n 80187ac <dhcp_dec_pcb_refcount+0x3c>
|
|
udp_remove(dhcp_pcb);
|
|
801879c: 4b08 ldr r3, [pc, #32] ; (80187c0 <dhcp_dec_pcb_refcount+0x50>)
|
|
801879e: 681b ldr r3, [r3, #0]
|
|
80187a0: 4618 mov r0, r3
|
|
80187a2: f7ff ff09 bl 80185b8 <udp_remove>
|
|
dhcp_pcb = NULL;
|
|
80187a6: 4b06 ldr r3, [pc, #24] ; (80187c0 <dhcp_dec_pcb_refcount+0x50>)
|
|
80187a8: 2200 movs r2, #0
|
|
80187aa: 601a str r2, [r3, #0]
|
|
}
|
|
}
|
|
80187ac: bf00 nop
|
|
80187ae: bd80 pop {r7, pc}
|
|
80187b0: 20008770 .word 0x20008770
|
|
80187b4: 08020398 .word 0x08020398
|
|
80187b8: 08020420 .word 0x08020420
|
|
80187bc: 080203f8 .word 0x080203f8
|
|
80187c0: 2000876c .word 0x2000876c
|
|
|
|
080187c4 <dhcp_handle_nak>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_handle_nak(struct netif *netif)
|
|
{
|
|
80187c4: b580 push {r7, lr}
|
|
80187c6: b084 sub sp, #16
|
|
80187c8: af00 add r7, sp, #0
|
|
80187ca: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
80187cc: 687b ldr r3, [r7, #4]
|
|
80187ce: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80187d0: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n",
|
|
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
|
|
/* Change to a defined state - set this before assigning the address
|
|
to ensure the callback can use dhcp_supplied_address() */
|
|
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
|
|
80187d2: 210c movs r1, #12
|
|
80187d4: 68f8 ldr r0, [r7, #12]
|
|
80187d6: f001 f869 bl 80198ac <dhcp_set_state>
|
|
/* remove IP address from interface (must no longer be used, as per RFC2131) */
|
|
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
|
|
80187da: 4b06 ldr r3, [pc, #24] ; (80187f4 <dhcp_handle_nak+0x30>)
|
|
80187dc: 4a05 ldr r2, [pc, #20] ; (80187f4 <dhcp_handle_nak+0x30>)
|
|
80187de: 4905 ldr r1, [pc, #20] ; (80187f4 <dhcp_handle_nak+0x30>)
|
|
80187e0: 6878 ldr r0, [r7, #4]
|
|
80187e2: f7f9 f82f bl 8011844 <netif_set_addr>
|
|
/* We can immediately restart discovery */
|
|
dhcp_discover(netif);
|
|
80187e6: 6878 ldr r0, [r7, #4]
|
|
80187e8: f000 fc5c bl 80190a4 <dhcp_discover>
|
|
}
|
|
80187ec: bf00 nop
|
|
80187ee: 3710 adds r7, #16
|
|
80187f0: 46bd mov sp, r7
|
|
80187f2: bd80 pop {r7, pc}
|
|
80187f4: 08022e68 .word 0x08022e68
|
|
|
|
080187f8 <dhcp_check>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_check(struct netif *netif)
|
|
{
|
|
80187f8: b580 push {r7, lr}
|
|
80187fa: b084 sub sp, #16
|
|
80187fc: af00 add r7, sp, #0
|
|
80187fe: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018800: 687b ldr r3, [r7, #4]
|
|
8018802: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018804: 60fb str r3, [r7, #12]
|
|
err_t result;
|
|
u16_t msecs;
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0],
|
|
(s16_t)netif->name[1]));
|
|
dhcp_set_state(dhcp, DHCP_STATE_CHECKING);
|
|
8018806: 2108 movs r1, #8
|
|
8018808: 68f8 ldr r0, [r7, #12]
|
|
801880a: f001 f84f bl 80198ac <dhcp_set_state>
|
|
/* create an ARP query for the offered IP address, expecting that no host
|
|
responds, as the IP address should not be in use. */
|
|
result = etharp_query(netif, &dhcp->offered_ip_addr, NULL);
|
|
801880e: 68fb ldr r3, [r7, #12]
|
|
8018810: 331c adds r3, #28
|
|
8018812: 2200 movs r2, #0
|
|
8018814: 4619 mov r1, r3
|
|
8018816: 6878 ldr r0, [r7, #4]
|
|
8018818: f002 fb4e bl 801aeb8 <etharp_query>
|
|
801881c: 4603 mov r3, r0
|
|
801881e: 72fb strb r3, [r7, #11]
|
|
if (result != ERR_OK) {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n"));
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
8018820: 68fb ldr r3, [r7, #12]
|
|
8018822: 799b ldrb r3, [r3, #6]
|
|
8018824: 2bff cmp r3, #255 ; 0xff
|
|
8018826: d005 beq.n 8018834 <dhcp_check+0x3c>
|
|
dhcp->tries++;
|
|
8018828: 68fb ldr r3, [r7, #12]
|
|
801882a: 799b ldrb r3, [r3, #6]
|
|
801882c: 3301 adds r3, #1
|
|
801882e: b2da uxtb r2, r3
|
|
8018830: 68fb ldr r3, [r7, #12]
|
|
8018832: 719a strb r2, [r3, #6]
|
|
}
|
|
msecs = 500;
|
|
8018834: f44f 73fa mov.w r3, #500 ; 0x1f4
|
|
8018838: 813b strh r3, [r7, #8]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
801883a: 893b ldrh r3, [r7, #8]
|
|
801883c: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
8018840: 4a06 ldr r2, [pc, #24] ; (801885c <dhcp_check+0x64>)
|
|
8018842: fb82 1203 smull r1, r2, r2, r3
|
|
8018846: 1152 asrs r2, r2, #5
|
|
8018848: 17db asrs r3, r3, #31
|
|
801884a: 1ad3 subs r3, r2, r3
|
|
801884c: b29a uxth r2, r3
|
|
801884e: 68fb ldr r3, [r7, #12]
|
|
8018850: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs));
|
|
}
|
|
8018852: bf00 nop
|
|
8018854: 3710 adds r7, #16
|
|
8018856: 46bd mov sp, r7
|
|
8018858: bd80 pop {r7, pc}
|
|
801885a: bf00 nop
|
|
801885c: 10624dd3 .word 0x10624dd3
|
|
|
|
08018860 <dhcp_handle_offer>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in)
|
|
{
|
|
8018860: b580 push {r7, lr}
|
|
8018862: b084 sub sp, #16
|
|
8018864: af00 add r7, sp, #0
|
|
8018866: 6078 str r0, [r7, #4]
|
|
8018868: 6039 str r1, [r7, #0]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
801886a: 687b ldr r3, [r7, #4]
|
|
801886c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801886e: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n",
|
|
(void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
|
|
/* obtain the server address */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) {
|
|
8018870: 4b0c ldr r3, [pc, #48] ; (80188a4 <dhcp_handle_offer+0x44>)
|
|
8018872: 789b ldrb r3, [r3, #2]
|
|
8018874: 2b00 cmp r3, #0
|
|
8018876: d011 beq.n 801889c <dhcp_handle_offer+0x3c>
|
|
dhcp->request_timeout = 0; /* stop timer */
|
|
8018878: 68fb ldr r3, [r7, #12]
|
|
801887a: 2200 movs r2, #0
|
|
801887c: 811a strh r2, [r3, #8]
|
|
|
|
ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID)));
|
|
801887e: 4b0a ldr r3, [pc, #40] ; (80188a8 <dhcp_handle_offer+0x48>)
|
|
8018880: 689b ldr r3, [r3, #8]
|
|
8018882: 4618 mov r0, r3
|
|
8018884: f7f8 f949 bl 8010b1a <lwip_htonl>
|
|
8018888: 4602 mov r2, r0
|
|
801888a: 68fb ldr r3, [r7, #12]
|
|
801888c: 619a str r2, [r3, #24]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n",
|
|
ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
|
|
/* remember offered address */
|
|
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
|
|
801888e: 683b ldr r3, [r7, #0]
|
|
8018890: 691a ldr r2, [r3, #16]
|
|
8018892: 68fb ldr r3, [r7, #12]
|
|
8018894: 61da str r2, [r3, #28]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n",
|
|
ip4_addr_get_u32(&dhcp->offered_ip_addr)));
|
|
|
|
dhcp_select(netif);
|
|
8018896: 6878 ldr r0, [r7, #4]
|
|
8018898: f000 f808 bl 80188ac <dhcp_select>
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
|
|
("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif));
|
|
}
|
|
}
|
|
801889c: bf00 nop
|
|
801889e: 3710 adds r7, #16
|
|
80188a0: 46bd mov sp, r7
|
|
80188a2: bd80 pop {r7, pc}
|
|
80188a4: 2000f818 .word 0x2000f818
|
|
80188a8: 2000f820 .word 0x2000f820
|
|
|
|
080188ac <dhcp_select>:
|
|
* @param netif the netif under DHCP control
|
|
* @return lwIP specific error (see error.h)
|
|
*/
|
|
static err_t
|
|
dhcp_select(struct netif *netif)
|
|
{
|
|
80188ac: b5b0 push {r4, r5, r7, lr}
|
|
80188ae: b08a sub sp, #40 ; 0x28
|
|
80188b0: af02 add r7, sp, #8
|
|
80188b2: 6078 str r0, [r7, #4]
|
|
u16_t msecs;
|
|
u8_t i;
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;);
|
|
80188b4: 687b ldr r3, [r7, #4]
|
|
80188b6: 2b00 cmp r3, #0
|
|
80188b8: d109 bne.n 80188ce <dhcp_select+0x22>
|
|
80188ba: 4b71 ldr r3, [pc, #452] ; (8018a80 <dhcp_select+0x1d4>)
|
|
80188bc: f240 1277 movw r2, #375 ; 0x177
|
|
80188c0: 4970 ldr r1, [pc, #448] ; (8018a84 <dhcp_select+0x1d8>)
|
|
80188c2: 4871 ldr r0, [pc, #452] ; (8018a88 <dhcp_select+0x1dc>)
|
|
80188c4: f004 f9f8 bl 801ccb8 <iprintf>
|
|
80188c8: f06f 030f mvn.w r3, #15
|
|
80188cc: e0d3 b.n 8018a76 <dhcp_select+0x1ca>
|
|
dhcp = netif_dhcp_data(netif);
|
|
80188ce: 687b ldr r3, [r7, #4]
|
|
80188d0: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80188d2: 61bb str r3, [r7, #24]
|
|
LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;);
|
|
80188d4: 69bb ldr r3, [r7, #24]
|
|
80188d6: 2b00 cmp r3, #0
|
|
80188d8: d109 bne.n 80188ee <dhcp_select+0x42>
|
|
80188da: 4b69 ldr r3, [pc, #420] ; (8018a80 <dhcp_select+0x1d4>)
|
|
80188dc: f240 1279 movw r2, #377 ; 0x179
|
|
80188e0: 496a ldr r1, [pc, #424] ; (8018a8c <dhcp_select+0x1e0>)
|
|
80188e2: 4869 ldr r0, [pc, #420] ; (8018a88 <dhcp_select+0x1dc>)
|
|
80188e4: f004 f9e8 bl 801ccb8 <iprintf>
|
|
80188e8: f06f 0305 mvn.w r3, #5
|
|
80188ec: e0c3 b.n 8018a76 <dhcp_select+0x1ca>
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
|
|
dhcp_set_state(dhcp, DHCP_STATE_REQUESTING);
|
|
80188ee: 2101 movs r1, #1
|
|
80188f0: 69b8 ldr r0, [r7, #24]
|
|
80188f2: f000 ffdb bl 80198ac <dhcp_set_state>
|
|
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
|
|
80188f6: f107 030c add.w r3, r7, #12
|
|
80188fa: 2203 movs r2, #3
|
|
80188fc: 69b9 ldr r1, [r7, #24]
|
|
80188fe: 6878 ldr r0, [r7, #4]
|
|
8018900: f001 fc5e bl 801a1c0 <dhcp_create_msg>
|
|
8018904: 6178 str r0, [r7, #20]
|
|
if (p_out != NULL) {
|
|
8018906: 697b ldr r3, [r7, #20]
|
|
8018908: 2b00 cmp r3, #0
|
|
801890a: f000 8085 beq.w 8018a18 <dhcp_select+0x16c>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
801890e: 697b ldr r3, [r7, #20]
|
|
8018910: 685b ldr r3, [r3, #4]
|
|
8018912: 613b str r3, [r7, #16]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
|
|
8018914: 89b8 ldrh r0, [r7, #12]
|
|
8018916: 693b ldr r3, [r7, #16]
|
|
8018918: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801891c: 2302 movs r3, #2
|
|
801891e: 2239 movs r2, #57 ; 0x39
|
|
8018920: f000 ffde bl 80198e0 <dhcp_option>
|
|
8018924: 4603 mov r3, r0
|
|
8018926: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
|
|
8018928: 89b8 ldrh r0, [r7, #12]
|
|
801892a: 693b ldr r3, [r7, #16]
|
|
801892c: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8018930: 687b ldr r3, [r7, #4]
|
|
8018932: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8018934: 461a mov r2, r3
|
|
8018936: f001 f82d bl 8019994 <dhcp_option_short>
|
|
801893a: 4603 mov r3, r0
|
|
801893c: 81bb strh r3, [r7, #12]
|
|
|
|
/* MUST request the offered IP address */
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
|
|
801893e: 89b8 ldrh r0, [r7, #12]
|
|
8018940: 693b ldr r3, [r7, #16]
|
|
8018942: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8018946: 2304 movs r3, #4
|
|
8018948: 2232 movs r2, #50 ; 0x32
|
|
801894a: f000 ffc9 bl 80198e0 <dhcp_option>
|
|
801894e: 4603 mov r3, r0
|
|
8018950: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
|
|
8018952: 89bc ldrh r4, [r7, #12]
|
|
8018954: 693b ldr r3, [r7, #16]
|
|
8018956: f103 05f0 add.w r5, r3, #240 ; 0xf0
|
|
801895a: 69bb ldr r3, [r7, #24]
|
|
801895c: 69db ldr r3, [r3, #28]
|
|
801895e: 4618 mov r0, r3
|
|
8018960: f7f8 f8db bl 8010b1a <lwip_htonl>
|
|
8018964: 4603 mov r3, r0
|
|
8018966: 461a mov r2, r3
|
|
8018968: 4629 mov r1, r5
|
|
801896a: 4620 mov r0, r4
|
|
801896c: f001 f844 bl 80199f8 <dhcp_option_long>
|
|
8018970: 4603 mov r3, r0
|
|
8018972: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
|
|
8018974: 89b8 ldrh r0, [r7, #12]
|
|
8018976: 693b ldr r3, [r7, #16]
|
|
8018978: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801897c: 2304 movs r3, #4
|
|
801897e: 2236 movs r2, #54 ; 0x36
|
|
8018980: f000 ffae bl 80198e0 <dhcp_option>
|
|
8018984: 4603 mov r3, r0
|
|
8018986: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr))));
|
|
8018988: 89bc ldrh r4, [r7, #12]
|
|
801898a: 693b ldr r3, [r7, #16]
|
|
801898c: f103 05f0 add.w r5, r3, #240 ; 0xf0
|
|
8018990: 69bb ldr r3, [r7, #24]
|
|
8018992: 699b ldr r3, [r3, #24]
|
|
8018994: 4618 mov r0, r3
|
|
8018996: f7f8 f8c0 bl 8010b1a <lwip_htonl>
|
|
801899a: 4603 mov r3, r0
|
|
801899c: 461a mov r2, r3
|
|
801899e: 4629 mov r1, r5
|
|
80189a0: 4620 mov r0, r4
|
|
80189a2: f001 f829 bl 80199f8 <dhcp_option_long>
|
|
80189a6: 4603 mov r3, r0
|
|
80189a8: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
|
|
80189aa: 89b8 ldrh r0, [r7, #12]
|
|
80189ac: 693b ldr r3, [r7, #16]
|
|
80189ae: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80189b2: 2303 movs r3, #3
|
|
80189b4: 2237 movs r2, #55 ; 0x37
|
|
80189b6: f000 ff93 bl 80198e0 <dhcp_option>
|
|
80189ba: 4603 mov r3, r0
|
|
80189bc: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
80189be: 2300 movs r3, #0
|
|
80189c0: 77bb strb r3, [r7, #30]
|
|
80189c2: e00e b.n 80189e2 <dhcp_select+0x136>
|
|
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
|
|
80189c4: 89b8 ldrh r0, [r7, #12]
|
|
80189c6: 693b ldr r3, [r7, #16]
|
|
80189c8: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80189cc: 7fbb ldrb r3, [r7, #30]
|
|
80189ce: 4a30 ldr r2, [pc, #192] ; (8018a90 <dhcp_select+0x1e4>)
|
|
80189d0: 5cd3 ldrb r3, [r2, r3]
|
|
80189d2: 461a mov r2, r3
|
|
80189d4: f000 ffb8 bl 8019948 <dhcp_option_byte>
|
|
80189d8: 4603 mov r3, r0
|
|
80189da: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
80189dc: 7fbb ldrb r3, [r7, #30]
|
|
80189de: 3301 adds r3, #1
|
|
80189e0: 77bb strb r3, [r7, #30]
|
|
80189e2: 7fbb ldrb r3, [r7, #30]
|
|
80189e4: 2b02 cmp r3, #2
|
|
80189e6: d9ed bls.n 80189c4 <dhcp_select+0x118>
|
|
#if LWIP_NETIF_HOSTNAME
|
|
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
|
|
#endif /* LWIP_NETIF_HOSTNAME */
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
80189e8: 89b8 ldrh r0, [r7, #12]
|
|
80189ea: 693b ldr r3, [r7, #16]
|
|
80189ec: 33f0 adds r3, #240 ; 0xf0
|
|
80189ee: 697a ldr r2, [r7, #20]
|
|
80189f0: 4619 mov r1, r3
|
|
80189f2: f001 fcbb bl 801a36c <dhcp_option_trailer>
|
|
|
|
/* send broadcast to any DHCP server */
|
|
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
|
|
80189f6: 4b27 ldr r3, [pc, #156] ; (8018a94 <dhcp_select+0x1e8>)
|
|
80189f8: 6818 ldr r0, [r3, #0]
|
|
80189fa: 4b27 ldr r3, [pc, #156] ; (8018a98 <dhcp_select+0x1ec>)
|
|
80189fc: 9301 str r3, [sp, #4]
|
|
80189fe: 687b ldr r3, [r7, #4]
|
|
8018a00: 9300 str r3, [sp, #0]
|
|
8018a02: 2343 movs r3, #67 ; 0x43
|
|
8018a04: 4a25 ldr r2, [pc, #148] ; (8018a9c <dhcp_select+0x1f0>)
|
|
8018a06: 6979 ldr r1, [r7, #20]
|
|
8018a08: f7ff fbda bl 80181c0 <udp_sendto_if_src>
|
|
8018a0c: 4603 mov r3, r0
|
|
8018a0e: 77fb strb r3, [r7, #31]
|
|
pbuf_free(p_out);
|
|
8018a10: 6978 ldr r0, [r7, #20]
|
|
8018a12: f7f9 fc21 bl 8012258 <pbuf_free>
|
|
8018a16: e001 b.n 8018a1c <dhcp_select+0x170>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n"));
|
|
result = ERR_MEM;
|
|
8018a18: 23ff movs r3, #255 ; 0xff
|
|
8018a1a: 77fb strb r3, [r7, #31]
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
8018a1c: 69bb ldr r3, [r7, #24]
|
|
8018a1e: 799b ldrb r3, [r3, #6]
|
|
8018a20: 2bff cmp r3, #255 ; 0xff
|
|
8018a22: d005 beq.n 8018a30 <dhcp_select+0x184>
|
|
dhcp->tries++;
|
|
8018a24: 69bb ldr r3, [r7, #24]
|
|
8018a26: 799b ldrb r3, [r3, #6]
|
|
8018a28: 3301 adds r3, #1
|
|
8018a2a: b2da uxtb r2, r3
|
|
8018a2c: 69bb ldr r3, [r7, #24]
|
|
8018a2e: 719a strb r2, [r3, #6]
|
|
}
|
|
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
|
|
8018a30: 69bb ldr r3, [r7, #24]
|
|
8018a32: 799b ldrb r3, [r3, #6]
|
|
8018a34: 2b05 cmp r3, #5
|
|
8018a36: d80d bhi.n 8018a54 <dhcp_select+0x1a8>
|
|
8018a38: 69bb ldr r3, [r7, #24]
|
|
8018a3a: 799b ldrb r3, [r3, #6]
|
|
8018a3c: 461a mov r2, r3
|
|
8018a3e: 2301 movs r3, #1
|
|
8018a40: 4093 lsls r3, r2
|
|
8018a42: b29b uxth r3, r3
|
|
8018a44: 461a mov r2, r3
|
|
8018a46: 0152 lsls r2, r2, #5
|
|
8018a48: 1ad2 subs r2, r2, r3
|
|
8018a4a: 0092 lsls r2, r2, #2
|
|
8018a4c: 4413 add r3, r2
|
|
8018a4e: 00db lsls r3, r3, #3
|
|
8018a50: b29b uxth r3, r3
|
|
8018a52: e001 b.n 8018a58 <dhcp_select+0x1ac>
|
|
8018a54: f64e 2360 movw r3, #60000 ; 0xea60
|
|
8018a58: 81fb strh r3, [r7, #14]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
8018a5a: 89fb ldrh r3, [r7, #14]
|
|
8018a5c: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
8018a60: 4a0f ldr r2, [pc, #60] ; (8018aa0 <dhcp_select+0x1f4>)
|
|
8018a62: fb82 1203 smull r1, r2, r2, r3
|
|
8018a66: 1152 asrs r2, r2, #5
|
|
8018a68: 17db asrs r3, r3, #31
|
|
8018a6a: 1ad3 subs r3, r2, r3
|
|
8018a6c: b29a uxth r2, r3
|
|
8018a6e: 69bb ldr r3, [r7, #24]
|
|
8018a70: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
8018a72: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
8018a76: 4618 mov r0, r3
|
|
8018a78: 3720 adds r7, #32
|
|
8018a7a: 46bd mov sp, r7
|
|
8018a7c: bdb0 pop {r4, r5, r7, pc}
|
|
8018a7e: bf00 nop
|
|
8018a80: 08020398 .word 0x08020398
|
|
8018a84: 08020444 .word 0x08020444
|
|
8018a88: 080203f8 .word 0x080203f8
|
|
8018a8c: 08020460 .word 0x08020460
|
|
8018a90: 20000080 .word 0x20000080
|
|
8018a94: 2000876c .word 0x2000876c
|
|
8018a98: 08022e68 .word 0x08022e68
|
|
8018a9c: 08022e6c .word 0x08022e6c
|
|
8018aa0: 10624dd3 .word 0x10624dd3
|
|
|
|
08018aa4 <dhcp_coarse_tmr>:
|
|
* The DHCP timer that checks for lease renewal/rebind timeouts.
|
|
* Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS).
|
|
*/
|
|
void
|
|
dhcp_coarse_tmr(void)
|
|
{
|
|
8018aa4: b580 push {r7, lr}
|
|
8018aa6: b082 sub sp, #8
|
|
8018aa8: af00 add r7, sp, #0
|
|
struct netif *netif;
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n"));
|
|
/* iterate through all network interfaces */
|
|
NETIF_FOREACH(netif) {
|
|
8018aaa: 4b27 ldr r3, [pc, #156] ; (8018b48 <dhcp_coarse_tmr+0xa4>)
|
|
8018aac: 681b ldr r3, [r3, #0]
|
|
8018aae: 607b str r3, [r7, #4]
|
|
8018ab0: e042 b.n 8018b38 <dhcp_coarse_tmr+0x94>
|
|
/* only act on DHCP configured interfaces */
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018ab2: 687b ldr r3, [r7, #4]
|
|
8018ab4: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018ab6: 603b str r3, [r7, #0]
|
|
if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) {
|
|
8018ab8: 683b ldr r3, [r7, #0]
|
|
8018aba: 2b00 cmp r3, #0
|
|
8018abc: d039 beq.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
8018abe: 683b ldr r3, [r7, #0]
|
|
8018ac0: 795b ldrb r3, [r3, #5]
|
|
8018ac2: 2b00 cmp r3, #0
|
|
8018ac4: d035 beq.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
/* compare lease time to expire timeout */
|
|
if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) {
|
|
8018ac6: 683b ldr r3, [r7, #0]
|
|
8018ac8: 8a9b ldrh r3, [r3, #20]
|
|
8018aca: 2b00 cmp r3, #0
|
|
8018acc: d012 beq.n 8018af4 <dhcp_coarse_tmr+0x50>
|
|
8018ace: 683b ldr r3, [r7, #0]
|
|
8018ad0: 8a5b ldrh r3, [r3, #18]
|
|
8018ad2: 3301 adds r3, #1
|
|
8018ad4: b29a uxth r2, r3
|
|
8018ad6: 683b ldr r3, [r7, #0]
|
|
8018ad8: 825a strh r2, [r3, #18]
|
|
8018ada: 683b ldr r3, [r7, #0]
|
|
8018adc: 8a5a ldrh r2, [r3, #18]
|
|
8018ade: 683b ldr r3, [r7, #0]
|
|
8018ae0: 8a9b ldrh r3, [r3, #20]
|
|
8018ae2: 429a cmp r2, r3
|
|
8018ae4: d106 bne.n 8018af4 <dhcp_coarse_tmr+0x50>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n"));
|
|
/* this clients' lease time has expired */
|
|
dhcp_release_and_stop(netif);
|
|
8018ae6: 6878 ldr r0, [r7, #4]
|
|
8018ae8: f000 fe46 bl 8019778 <dhcp_release_and_stop>
|
|
dhcp_start(netif);
|
|
8018aec: 6878 ldr r0, [r7, #4]
|
|
8018aee: f000 f96b bl 8018dc8 <dhcp_start>
|
|
8018af2: e01e b.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
/* timer is active (non zero), and triggers (zeroes) now? */
|
|
} else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) {
|
|
8018af4: 683b ldr r3, [r7, #0]
|
|
8018af6: 8a1b ldrh r3, [r3, #16]
|
|
8018af8: 2b00 cmp r3, #0
|
|
8018afa: d00b beq.n 8018b14 <dhcp_coarse_tmr+0x70>
|
|
8018afc: 683b ldr r3, [r7, #0]
|
|
8018afe: 8a1b ldrh r3, [r3, #16]
|
|
8018b00: 1e5a subs r2, r3, #1
|
|
8018b02: b291 uxth r1, r2
|
|
8018b04: 683a ldr r2, [r7, #0]
|
|
8018b06: 8211 strh r1, [r2, #16]
|
|
8018b08: 2b01 cmp r3, #1
|
|
8018b0a: d103 bne.n 8018b14 <dhcp_coarse_tmr+0x70>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n"));
|
|
/* this clients' rebind timeout triggered */
|
|
dhcp_t2_timeout(netif);
|
|
8018b0c: 6878 ldr r0, [r7, #4]
|
|
8018b0e: f000 f8c7 bl 8018ca0 <dhcp_t2_timeout>
|
|
8018b12: e00e b.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
/* timer is active (non zero), and triggers (zeroes) now */
|
|
} else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) {
|
|
8018b14: 683b ldr r3, [r7, #0]
|
|
8018b16: 89db ldrh r3, [r3, #14]
|
|
8018b18: 2b00 cmp r3, #0
|
|
8018b1a: d00a beq.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
8018b1c: 683b ldr r3, [r7, #0]
|
|
8018b1e: 89db ldrh r3, [r3, #14]
|
|
8018b20: 1e5a subs r2, r3, #1
|
|
8018b22: b291 uxth r1, r2
|
|
8018b24: 683a ldr r2, [r7, #0]
|
|
8018b26: 81d1 strh r1, [r2, #14]
|
|
8018b28: 2b01 cmp r3, #1
|
|
8018b2a: d102 bne.n 8018b32 <dhcp_coarse_tmr+0x8e>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n"));
|
|
/* this clients' renewal timeout triggered */
|
|
dhcp_t1_timeout(netif);
|
|
8018b2c: 6878 ldr r0, [r7, #4]
|
|
8018b2e: f000 f888 bl 8018c42 <dhcp_t1_timeout>
|
|
NETIF_FOREACH(netif) {
|
|
8018b32: 687b ldr r3, [r7, #4]
|
|
8018b34: 681b ldr r3, [r3, #0]
|
|
8018b36: 607b str r3, [r7, #4]
|
|
8018b38: 687b ldr r3, [r7, #4]
|
|
8018b3a: 2b00 cmp r3, #0
|
|
8018b3c: d1b9 bne.n 8018ab2 <dhcp_coarse_tmr+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8018b3e: bf00 nop
|
|
8018b40: 3708 adds r7, #8
|
|
8018b42: 46bd mov sp, r7
|
|
8018b44: bd80 pop {r7, pc}
|
|
8018b46: bf00 nop
|
|
8018b48: 2000f7ec .word 0x2000f7ec
|
|
|
|
08018b4c <dhcp_fine_tmr>:
|
|
* A DHCP server is expected to respond within a short period of time.
|
|
* This timer checks whether an outstanding DHCP request is timed out.
|
|
*/
|
|
void
|
|
dhcp_fine_tmr(void)
|
|
{
|
|
8018b4c: b580 push {r7, lr}
|
|
8018b4e: b082 sub sp, #8
|
|
8018b50: af00 add r7, sp, #0
|
|
struct netif *netif;
|
|
/* loop through netif's */
|
|
NETIF_FOREACH(netif) {
|
|
8018b52: 4b16 ldr r3, [pc, #88] ; (8018bac <dhcp_fine_tmr+0x60>)
|
|
8018b54: 681b ldr r3, [r3, #0]
|
|
8018b56: 607b str r3, [r7, #4]
|
|
8018b58: e020 b.n 8018b9c <dhcp_fine_tmr+0x50>
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018b5a: 687b ldr r3, [r7, #4]
|
|
8018b5c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018b5e: 603b str r3, [r7, #0]
|
|
/* only act on DHCP configured interfaces */
|
|
if (dhcp != NULL) {
|
|
8018b60: 683b ldr r3, [r7, #0]
|
|
8018b62: 2b00 cmp r3, #0
|
|
8018b64: d017 beq.n 8018b96 <dhcp_fine_tmr+0x4a>
|
|
/* timer is active (non zero), and is about to trigger now */
|
|
if (dhcp->request_timeout > 1) {
|
|
8018b66: 683b ldr r3, [r7, #0]
|
|
8018b68: 891b ldrh r3, [r3, #8]
|
|
8018b6a: 2b01 cmp r3, #1
|
|
8018b6c: d906 bls.n 8018b7c <dhcp_fine_tmr+0x30>
|
|
dhcp->request_timeout--;
|
|
8018b6e: 683b ldr r3, [r7, #0]
|
|
8018b70: 891b ldrh r3, [r3, #8]
|
|
8018b72: 3b01 subs r3, #1
|
|
8018b74: b29a uxth r2, r3
|
|
8018b76: 683b ldr r3, [r7, #0]
|
|
8018b78: 811a strh r2, [r3, #8]
|
|
8018b7a: e00c b.n 8018b96 <dhcp_fine_tmr+0x4a>
|
|
} else if (dhcp->request_timeout == 1) {
|
|
8018b7c: 683b ldr r3, [r7, #0]
|
|
8018b7e: 891b ldrh r3, [r3, #8]
|
|
8018b80: 2b01 cmp r3, #1
|
|
8018b82: d108 bne.n 8018b96 <dhcp_fine_tmr+0x4a>
|
|
dhcp->request_timeout--;
|
|
8018b84: 683b ldr r3, [r7, #0]
|
|
8018b86: 891b ldrh r3, [r3, #8]
|
|
8018b88: 3b01 subs r3, #1
|
|
8018b8a: b29a uxth r2, r3
|
|
8018b8c: 683b ldr r3, [r7, #0]
|
|
8018b8e: 811a strh r2, [r3, #8]
|
|
/* { dhcp->request_timeout == 0 } */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n"));
|
|
/* this client's request timeout triggered */
|
|
dhcp_timeout(netif);
|
|
8018b90: 6878 ldr r0, [r7, #4]
|
|
8018b92: f000 f80d bl 8018bb0 <dhcp_timeout>
|
|
NETIF_FOREACH(netif) {
|
|
8018b96: 687b ldr r3, [r7, #4]
|
|
8018b98: 681b ldr r3, [r3, #0]
|
|
8018b9a: 607b str r3, [r7, #4]
|
|
8018b9c: 687b ldr r3, [r7, #4]
|
|
8018b9e: 2b00 cmp r3, #0
|
|
8018ba0: d1db bne.n 8018b5a <dhcp_fine_tmr+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8018ba2: bf00 nop
|
|
8018ba4: 3708 adds r7, #8
|
|
8018ba6: 46bd mov sp, r7
|
|
8018ba8: bd80 pop {r7, pc}
|
|
8018baa: bf00 nop
|
|
8018bac: 2000f7ec .word 0x2000f7ec
|
|
|
|
08018bb0 <dhcp_timeout>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_timeout(struct netif *netif)
|
|
{
|
|
8018bb0: b580 push {r7, lr}
|
|
8018bb2: b084 sub sp, #16
|
|
8018bb4: af00 add r7, sp, #0
|
|
8018bb6: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018bb8: 687b ldr r3, [r7, #4]
|
|
8018bba: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018bbc: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n"));
|
|
/* back-off period has passed, or server selection timed out */
|
|
if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) {
|
|
8018bbe: 68fb ldr r3, [r7, #12]
|
|
8018bc0: 795b ldrb r3, [r3, #5]
|
|
8018bc2: 2b0c cmp r3, #12
|
|
8018bc4: d003 beq.n 8018bce <dhcp_timeout+0x1e>
|
|
8018bc6: 68fb ldr r3, [r7, #12]
|
|
8018bc8: 795b ldrb r3, [r3, #5]
|
|
8018bca: 2b06 cmp r3, #6
|
|
8018bcc: d103 bne.n 8018bd6 <dhcp_timeout+0x26>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n"));
|
|
dhcp_discover(netif);
|
|
8018bce: 6878 ldr r0, [r7, #4]
|
|
8018bd0: f000 fa68 bl 80190a4 <dhcp_discover>
|
|
dhcp_reboot(netif);
|
|
} else {
|
|
dhcp_discover(netif);
|
|
}
|
|
}
|
|
}
|
|
8018bd4: e031 b.n 8018c3a <dhcp_timeout+0x8a>
|
|
} else if (dhcp->state == DHCP_STATE_REQUESTING) {
|
|
8018bd6: 68fb ldr r3, [r7, #12]
|
|
8018bd8: 795b ldrb r3, [r3, #5]
|
|
8018bda: 2b01 cmp r3, #1
|
|
8018bdc: d10e bne.n 8018bfc <dhcp_timeout+0x4c>
|
|
if (dhcp->tries <= 5) {
|
|
8018bde: 68fb ldr r3, [r7, #12]
|
|
8018be0: 799b ldrb r3, [r3, #6]
|
|
8018be2: 2b05 cmp r3, #5
|
|
8018be4: d803 bhi.n 8018bee <dhcp_timeout+0x3e>
|
|
dhcp_select(netif);
|
|
8018be6: 6878 ldr r0, [r7, #4]
|
|
8018be8: f7ff fe60 bl 80188ac <dhcp_select>
|
|
}
|
|
8018bec: e025 b.n 8018c3a <dhcp_timeout+0x8a>
|
|
dhcp_release_and_stop(netif);
|
|
8018bee: 6878 ldr r0, [r7, #4]
|
|
8018bf0: f000 fdc2 bl 8019778 <dhcp_release_and_stop>
|
|
dhcp_start(netif);
|
|
8018bf4: 6878 ldr r0, [r7, #4]
|
|
8018bf6: f000 f8e7 bl 8018dc8 <dhcp_start>
|
|
}
|
|
8018bfa: e01e b.n 8018c3a <dhcp_timeout+0x8a>
|
|
} else if (dhcp->state == DHCP_STATE_CHECKING) {
|
|
8018bfc: 68fb ldr r3, [r7, #12]
|
|
8018bfe: 795b ldrb r3, [r3, #5]
|
|
8018c00: 2b08 cmp r3, #8
|
|
8018c02: d10b bne.n 8018c1c <dhcp_timeout+0x6c>
|
|
if (dhcp->tries <= 1) {
|
|
8018c04: 68fb ldr r3, [r7, #12]
|
|
8018c06: 799b ldrb r3, [r3, #6]
|
|
8018c08: 2b01 cmp r3, #1
|
|
8018c0a: d803 bhi.n 8018c14 <dhcp_timeout+0x64>
|
|
dhcp_check(netif);
|
|
8018c0c: 6878 ldr r0, [r7, #4]
|
|
8018c0e: f7ff fdf3 bl 80187f8 <dhcp_check>
|
|
}
|
|
8018c12: e012 b.n 8018c3a <dhcp_timeout+0x8a>
|
|
dhcp_bind(netif);
|
|
8018c14: 6878 ldr r0, [r7, #4]
|
|
8018c16: f000 fae7 bl 80191e8 <dhcp_bind>
|
|
}
|
|
8018c1a: e00e b.n 8018c3a <dhcp_timeout+0x8a>
|
|
} else if (dhcp->state == DHCP_STATE_REBOOTING) {
|
|
8018c1c: 68fb ldr r3, [r7, #12]
|
|
8018c1e: 795b ldrb r3, [r3, #5]
|
|
8018c20: 2b03 cmp r3, #3
|
|
8018c22: d10a bne.n 8018c3a <dhcp_timeout+0x8a>
|
|
if (dhcp->tries < REBOOT_TRIES) {
|
|
8018c24: 68fb ldr r3, [r7, #12]
|
|
8018c26: 799b ldrb r3, [r3, #6]
|
|
8018c28: 2b01 cmp r3, #1
|
|
8018c2a: d803 bhi.n 8018c34 <dhcp_timeout+0x84>
|
|
dhcp_reboot(netif);
|
|
8018c2c: 6878 ldr r0, [r7, #4]
|
|
8018c2e: f000 fced bl 801960c <dhcp_reboot>
|
|
}
|
|
8018c32: e002 b.n 8018c3a <dhcp_timeout+0x8a>
|
|
dhcp_discover(netif);
|
|
8018c34: 6878 ldr r0, [r7, #4]
|
|
8018c36: f000 fa35 bl 80190a4 <dhcp_discover>
|
|
}
|
|
8018c3a: bf00 nop
|
|
8018c3c: 3710 adds r7, #16
|
|
8018c3e: 46bd mov sp, r7
|
|
8018c40: bd80 pop {r7, pc}
|
|
|
|
08018c42 <dhcp_t1_timeout>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_t1_timeout(struct netif *netif)
|
|
{
|
|
8018c42: b580 push {r7, lr}
|
|
8018c44: b084 sub sp, #16
|
|
8018c46: af00 add r7, sp, #0
|
|
8018c48: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018c4a: 687b ldr r3, [r7, #4]
|
|
8018c4c: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018c4e: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n"));
|
|
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
|
|
8018c50: 68fb ldr r3, [r7, #12]
|
|
8018c52: 795b ldrb r3, [r3, #5]
|
|
8018c54: 2b01 cmp r3, #1
|
|
8018c56: d007 beq.n 8018c68 <dhcp_t1_timeout+0x26>
|
|
8018c58: 68fb ldr r3, [r7, #12]
|
|
8018c5a: 795b ldrb r3, [r3, #5]
|
|
8018c5c: 2b0a cmp r3, #10
|
|
8018c5e: d003 beq.n 8018c68 <dhcp_t1_timeout+0x26>
|
|
(dhcp->state == DHCP_STATE_RENEWING)) {
|
|
8018c60: 68fb ldr r3, [r7, #12]
|
|
8018c62: 795b ldrb r3, [r3, #5]
|
|
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
|
|
8018c64: 2b05 cmp r3, #5
|
|
8018c66: d117 bne.n 8018c98 <dhcp_t1_timeout+0x56>
|
|
* eventually time-out if renew tries fail. */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
|
|
("dhcp_t1_timeout(): must renew\n"));
|
|
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
|
|
DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */
|
|
dhcp_renew(netif);
|
|
8018c68: 6878 ldr r0, [r7, #4]
|
|
8018c6a: f000 fb97 bl 801939c <dhcp_renew>
|
|
/* Calculate next timeout */
|
|
if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
|
|
8018c6e: 68fb ldr r3, [r7, #12]
|
|
8018c70: 899b ldrh r3, [r3, #12]
|
|
8018c72: 461a mov r2, r3
|
|
8018c74: 68fb ldr r3, [r7, #12]
|
|
8018c76: 8a5b ldrh r3, [r3, #18]
|
|
8018c78: 1ad3 subs r3, r2, r3
|
|
8018c7a: 2b01 cmp r3, #1
|
|
8018c7c: dd0c ble.n 8018c98 <dhcp_t1_timeout+0x56>
|
|
dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2);
|
|
8018c7e: 68fb ldr r3, [r7, #12]
|
|
8018c80: 899b ldrh r3, [r3, #12]
|
|
8018c82: 461a mov r2, r3
|
|
8018c84: 68fb ldr r3, [r7, #12]
|
|
8018c86: 8a5b ldrh r3, [r3, #18]
|
|
8018c88: 1ad3 subs r3, r2, r3
|
|
8018c8a: 2b00 cmp r3, #0
|
|
8018c8c: da00 bge.n 8018c90 <dhcp_t1_timeout+0x4e>
|
|
8018c8e: 3301 adds r3, #1
|
|
8018c90: 105b asrs r3, r3, #1
|
|
8018c92: b29a uxth r2, r3
|
|
8018c94: 68fb ldr r3, [r7, #12]
|
|
8018c96: 81da strh r2, [r3, #14]
|
|
}
|
|
}
|
|
}
|
|
8018c98: bf00 nop
|
|
8018c9a: 3710 adds r7, #16
|
|
8018c9c: 46bd mov sp, r7
|
|
8018c9e: bd80 pop {r7, pc}
|
|
|
|
08018ca0 <dhcp_t2_timeout>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_t2_timeout(struct netif *netif)
|
|
{
|
|
8018ca0: b580 push {r7, lr}
|
|
8018ca2: b084 sub sp, #16
|
|
8018ca4: af00 add r7, sp, #0
|
|
8018ca6: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018ca8: 687b ldr r3, [r7, #4]
|
|
8018caa: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018cac: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n"));
|
|
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
|
|
8018cae: 68fb ldr r3, [r7, #12]
|
|
8018cb0: 795b ldrb r3, [r3, #5]
|
|
8018cb2: 2b01 cmp r3, #1
|
|
8018cb4: d00b beq.n 8018cce <dhcp_t2_timeout+0x2e>
|
|
8018cb6: 68fb ldr r3, [r7, #12]
|
|
8018cb8: 795b ldrb r3, [r3, #5]
|
|
8018cba: 2b0a cmp r3, #10
|
|
8018cbc: d007 beq.n 8018cce <dhcp_t2_timeout+0x2e>
|
|
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
|
|
8018cbe: 68fb ldr r3, [r7, #12]
|
|
8018cc0: 795b ldrb r3, [r3, #5]
|
|
if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) ||
|
|
8018cc2: 2b05 cmp r3, #5
|
|
8018cc4: d003 beq.n 8018cce <dhcp_t2_timeout+0x2e>
|
|
(dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) {
|
|
8018cc6: 68fb ldr r3, [r7, #12]
|
|
8018cc8: 795b ldrb r3, [r3, #5]
|
|
8018cca: 2b04 cmp r3, #4
|
|
8018ccc: d117 bne.n 8018cfe <dhcp_t2_timeout+0x5e>
|
|
/* just retry to rebind */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE,
|
|
("dhcp_t2_timeout(): must rebind\n"));
|
|
/* This slightly different to RFC2131: DHCPREQUEST will be sent from state
|
|
DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */
|
|
dhcp_rebind(netif);
|
|
8018cce: 6878 ldr r0, [r7, #4]
|
|
8018cd0: f000 fc00 bl 80194d4 <dhcp_rebind>
|
|
/* Calculate next timeout */
|
|
if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) {
|
|
8018cd4: 68fb ldr r3, [r7, #12]
|
|
8018cd6: 8a9b ldrh r3, [r3, #20]
|
|
8018cd8: 461a mov r2, r3
|
|
8018cda: 68fb ldr r3, [r7, #12]
|
|
8018cdc: 8a5b ldrh r3, [r3, #18]
|
|
8018cde: 1ad3 subs r3, r2, r3
|
|
8018ce0: 2b01 cmp r3, #1
|
|
8018ce2: dd0c ble.n 8018cfe <dhcp_t2_timeout+0x5e>
|
|
dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2);
|
|
8018ce4: 68fb ldr r3, [r7, #12]
|
|
8018ce6: 8a9b ldrh r3, [r3, #20]
|
|
8018ce8: 461a mov r2, r3
|
|
8018cea: 68fb ldr r3, [r7, #12]
|
|
8018cec: 8a5b ldrh r3, [r3, #18]
|
|
8018cee: 1ad3 subs r3, r2, r3
|
|
8018cf0: 2b00 cmp r3, #0
|
|
8018cf2: da00 bge.n 8018cf6 <dhcp_t2_timeout+0x56>
|
|
8018cf4: 3301 adds r3, #1
|
|
8018cf6: 105b asrs r3, r3, #1
|
|
8018cf8: b29a uxth r2, r3
|
|
8018cfa: 68fb ldr r3, [r7, #12]
|
|
8018cfc: 821a strh r2, [r3, #16]
|
|
}
|
|
}
|
|
}
|
|
8018cfe: bf00 nop
|
|
8018d00: 3710 adds r7, #16
|
|
8018d02: 46bd mov sp, r7
|
|
8018d04: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08018d08 <dhcp_handle_ack>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static void
|
|
dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in)
|
|
{
|
|
8018d08: b580 push {r7, lr}
|
|
8018d0a: b084 sub sp, #16
|
|
8018d0c: af00 add r7, sp, #0
|
|
8018d0e: 6078 str r0, [r7, #4]
|
|
8018d10: 6039 str r1, [r7, #0]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018d12: 687b ldr r3, [r7, #4]
|
|
8018d14: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018d16: 60fb str r3, [r7, #12]
|
|
#if LWIP_DHCP_GET_NTP_SRV
|
|
ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS];
|
|
#endif
|
|
|
|
/* clear options we might not get from the ACK */
|
|
ip4_addr_set_zero(&dhcp->offered_sn_mask);
|
|
8018d18: 68fb ldr r3, [r7, #12]
|
|
8018d1a: 2200 movs r2, #0
|
|
8018d1c: 621a str r2, [r3, #32]
|
|
ip4_addr_set_zero(&dhcp->offered_gw_addr);
|
|
8018d1e: 68fb ldr r3, [r7, #12]
|
|
8018d20: 2200 movs r2, #0
|
|
8018d22: 625a str r2, [r3, #36] ; 0x24
|
|
#if LWIP_DHCP_BOOTP_FILE
|
|
ip4_addr_set_zero(&dhcp->offered_si_addr);
|
|
#endif /* LWIP_DHCP_BOOTP_FILE */
|
|
|
|
/* lease time given? */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) {
|
|
8018d24: 4b26 ldr r3, [pc, #152] ; (8018dc0 <dhcp_handle_ack+0xb8>)
|
|
8018d26: 78db ldrb r3, [r3, #3]
|
|
8018d28: 2b00 cmp r3, #0
|
|
8018d2a: d003 beq.n 8018d34 <dhcp_handle_ack+0x2c>
|
|
/* remember offered lease time */
|
|
dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME);
|
|
8018d2c: 4b25 ldr r3, [pc, #148] ; (8018dc4 <dhcp_handle_ack+0xbc>)
|
|
8018d2e: 68da ldr r2, [r3, #12]
|
|
8018d30: 68fb ldr r3, [r7, #12]
|
|
8018d32: 629a str r2, [r3, #40] ; 0x28
|
|
}
|
|
/* renewal period given? */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) {
|
|
8018d34: 4b22 ldr r3, [pc, #136] ; (8018dc0 <dhcp_handle_ack+0xb8>)
|
|
8018d36: 791b ldrb r3, [r3, #4]
|
|
8018d38: 2b00 cmp r3, #0
|
|
8018d3a: d004 beq.n 8018d46 <dhcp_handle_ack+0x3e>
|
|
/* remember given renewal period */
|
|
dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1);
|
|
8018d3c: 4b21 ldr r3, [pc, #132] ; (8018dc4 <dhcp_handle_ack+0xbc>)
|
|
8018d3e: 691a ldr r2, [r3, #16]
|
|
8018d40: 68fb ldr r3, [r7, #12]
|
|
8018d42: 62da str r2, [r3, #44] ; 0x2c
|
|
8018d44: e004 b.n 8018d50 <dhcp_handle_ack+0x48>
|
|
} else {
|
|
/* calculate safe periods for renewal */
|
|
dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2;
|
|
8018d46: 68fb ldr r3, [r7, #12]
|
|
8018d48: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8018d4a: 085a lsrs r2, r3, #1
|
|
8018d4c: 68fb ldr r3, [r7, #12]
|
|
8018d4e: 62da str r2, [r3, #44] ; 0x2c
|
|
}
|
|
|
|
/* renewal period given? */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) {
|
|
8018d50: 4b1b ldr r3, [pc, #108] ; (8018dc0 <dhcp_handle_ack+0xb8>)
|
|
8018d52: 795b ldrb r3, [r3, #5]
|
|
8018d54: 2b00 cmp r3, #0
|
|
8018d56: d004 beq.n 8018d62 <dhcp_handle_ack+0x5a>
|
|
/* remember given rebind period */
|
|
dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2);
|
|
8018d58: 4b1a ldr r3, [pc, #104] ; (8018dc4 <dhcp_handle_ack+0xbc>)
|
|
8018d5a: 695a ldr r2, [r3, #20]
|
|
8018d5c: 68fb ldr r3, [r7, #12]
|
|
8018d5e: 631a str r2, [r3, #48] ; 0x30
|
|
8018d60: e007 b.n 8018d72 <dhcp_handle_ack+0x6a>
|
|
} else {
|
|
/* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/
|
|
dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U;
|
|
8018d62: 68fb ldr r3, [r7, #12]
|
|
8018d64: 6a9a ldr r2, [r3, #40] ; 0x28
|
|
8018d66: 4613 mov r3, r2
|
|
8018d68: 00db lsls r3, r3, #3
|
|
8018d6a: 1a9b subs r3, r3, r2
|
|
8018d6c: 08da lsrs r2, r3, #3
|
|
8018d6e: 68fb ldr r3, [r7, #12]
|
|
8018d70: 631a str r2, [r3, #48] ; 0x30
|
|
}
|
|
|
|
/* (y)our internet address */
|
|
ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr);
|
|
8018d72: 683b ldr r3, [r7, #0]
|
|
8018d74: 691a ldr r2, [r3, #16]
|
|
8018d76: 68fb ldr r3, [r7, #12]
|
|
8018d78: 61da str r2, [r3, #28]
|
|
boot file name copied in dhcp_parse_reply if not overloaded */
|
|
ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr);
|
|
#endif /* LWIP_DHCP_BOOTP_FILE */
|
|
|
|
/* subnet mask given? */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) {
|
|
8018d7a: 4b11 ldr r3, [pc, #68] ; (8018dc0 <dhcp_handle_ack+0xb8>)
|
|
8018d7c: 799b ldrb r3, [r3, #6]
|
|
8018d7e: 2b00 cmp r3, #0
|
|
8018d80: d00b beq.n 8018d9a <dhcp_handle_ack+0x92>
|
|
/* remember given subnet mask */
|
|
ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)));
|
|
8018d82: 4b10 ldr r3, [pc, #64] ; (8018dc4 <dhcp_handle_ack+0xbc>)
|
|
8018d84: 699b ldr r3, [r3, #24]
|
|
8018d86: 4618 mov r0, r3
|
|
8018d88: f7f7 fec7 bl 8010b1a <lwip_htonl>
|
|
8018d8c: 4602 mov r2, r0
|
|
8018d8e: 68fb ldr r3, [r7, #12]
|
|
8018d90: 621a str r2, [r3, #32]
|
|
dhcp->subnet_mask_given = 1;
|
|
8018d92: 68fb ldr r3, [r7, #12]
|
|
8018d94: 2201 movs r2, #1
|
|
8018d96: 71da strb r2, [r3, #7]
|
|
8018d98: e002 b.n 8018da0 <dhcp_handle_ack+0x98>
|
|
} else {
|
|
dhcp->subnet_mask_given = 0;
|
|
8018d9a: 68fb ldr r3, [r7, #12]
|
|
8018d9c: 2200 movs r2, #0
|
|
8018d9e: 71da strb r2, [r3, #7]
|
|
}
|
|
|
|
/* gateway router */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) {
|
|
8018da0: 4b07 ldr r3, [pc, #28] ; (8018dc0 <dhcp_handle_ack+0xb8>)
|
|
8018da2: 79db ldrb r3, [r3, #7]
|
|
8018da4: 2b00 cmp r3, #0
|
|
8018da6: d007 beq.n 8018db8 <dhcp_handle_ack+0xb0>
|
|
ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER)));
|
|
8018da8: 4b06 ldr r3, [pc, #24] ; (8018dc4 <dhcp_handle_ack+0xbc>)
|
|
8018daa: 69db ldr r3, [r3, #28]
|
|
8018dac: 4618 mov r0, r3
|
|
8018dae: f7f7 feb4 bl 8010b1a <lwip_htonl>
|
|
8018db2: 4602 mov r2, r0
|
|
8018db4: 68fb ldr r3, [r7, #12]
|
|
8018db6: 625a str r2, [r3, #36] ; 0x24
|
|
ip_addr_t dns_addr;
|
|
ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n)));
|
|
dns_setserver(n, &dns_addr);
|
|
}
|
|
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
|
|
}
|
|
8018db8: bf00 nop
|
|
8018dba: 3710 adds r7, #16
|
|
8018dbc: 46bd mov sp, r7
|
|
8018dbe: bd80 pop {r7, pc}
|
|
8018dc0: 2000f818 .word 0x2000f818
|
|
8018dc4: 2000f820 .word 0x2000f820
|
|
|
|
08018dc8 <dhcp_start>:
|
|
* - ERR_OK - No error
|
|
* - ERR_MEM - Out of memory
|
|
*/
|
|
err_t
|
|
dhcp_start(struct netif *netif)
|
|
{
|
|
8018dc8: b580 push {r7, lr}
|
|
8018dca: b084 sub sp, #16
|
|
8018dcc: af00 add r7, sp, #0
|
|
8018dce: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp;
|
|
err_t result;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;);
|
|
8018dd0: 687b ldr r3, [r7, #4]
|
|
8018dd2: 2b00 cmp r3, #0
|
|
8018dd4: d109 bne.n 8018dea <dhcp_start+0x22>
|
|
8018dd6: 4b37 ldr r3, [pc, #220] ; (8018eb4 <dhcp_start+0xec>)
|
|
8018dd8: f240 22e7 movw r2, #743 ; 0x2e7
|
|
8018ddc: 4936 ldr r1, [pc, #216] ; (8018eb8 <dhcp_start+0xf0>)
|
|
8018dde: 4837 ldr r0, [pc, #220] ; (8018ebc <dhcp_start+0xf4>)
|
|
8018de0: f003 ff6a bl 801ccb8 <iprintf>
|
|
8018de4: f06f 030f mvn.w r3, #15
|
|
8018de8: e060 b.n 8018eac <dhcp_start+0xe4>
|
|
LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;);
|
|
8018dea: 687b ldr r3, [r7, #4]
|
|
8018dec: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8018df0: f003 0301 and.w r3, r3, #1
|
|
8018df4: 2b00 cmp r3, #0
|
|
8018df6: d109 bne.n 8018e0c <dhcp_start+0x44>
|
|
8018df8: 4b2e ldr r3, [pc, #184] ; (8018eb4 <dhcp_start+0xec>)
|
|
8018dfa: f44f 723a mov.w r2, #744 ; 0x2e8
|
|
8018dfe: 4930 ldr r1, [pc, #192] ; (8018ec0 <dhcp_start+0xf8>)
|
|
8018e00: 482e ldr r0, [pc, #184] ; (8018ebc <dhcp_start+0xf4>)
|
|
8018e02: f003 ff59 bl 801ccb8 <iprintf>
|
|
8018e06: f06f 030f mvn.w r3, #15
|
|
8018e0a: e04f b.n 8018eac <dhcp_start+0xe4>
|
|
dhcp = netif_dhcp_data(netif);
|
|
8018e0c: 687b ldr r3, [r7, #4]
|
|
8018e0e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018e10: 60fb str r3, [r7, #12]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
|
|
|
|
/* check MTU of the netif */
|
|
if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) {
|
|
8018e12: 687b ldr r3, [r7, #4]
|
|
8018e14: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8018e16: f5b3 7f10 cmp.w r3, #576 ; 0x240
|
|
8018e1a: d202 bcs.n 8018e22 <dhcp_start+0x5a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n"));
|
|
return ERR_MEM;
|
|
8018e1c: f04f 33ff mov.w r3, #4294967295
|
|
8018e20: e044 b.n 8018eac <dhcp_start+0xe4>
|
|
}
|
|
|
|
/* no DHCP client attached yet? */
|
|
if (dhcp == NULL) {
|
|
8018e22: 68fb ldr r3, [r7, #12]
|
|
8018e24: 2b00 cmp r3, #0
|
|
8018e26: d10d bne.n 8018e44 <dhcp_start+0x7c>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n"));
|
|
dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp));
|
|
8018e28: 2034 movs r0, #52 ; 0x34
|
|
8018e2a: f7f8 f995 bl 8011158 <mem_malloc>
|
|
8018e2e: 60f8 str r0, [r7, #12]
|
|
if (dhcp == NULL) {
|
|
8018e30: 68fb ldr r3, [r7, #12]
|
|
8018e32: 2b00 cmp r3, #0
|
|
8018e34: d102 bne.n 8018e3c <dhcp_start+0x74>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n"));
|
|
return ERR_MEM;
|
|
8018e36: f04f 33ff mov.w r3, #4294967295
|
|
8018e3a: e037 b.n 8018eac <dhcp_start+0xe4>
|
|
}
|
|
|
|
/* store this dhcp client in the netif */
|
|
netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp);
|
|
8018e3c: 687b ldr r3, [r7, #4]
|
|
8018e3e: 68fa ldr r2, [r7, #12]
|
|
8018e40: 625a str r2, [r3, #36] ; 0x24
|
|
8018e42: e005 b.n 8018e50 <dhcp_start+0x88>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp"));
|
|
/* already has DHCP client attached */
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n"));
|
|
|
|
if (dhcp->pcb_allocated != 0) {
|
|
8018e44: 68fb ldr r3, [r7, #12]
|
|
8018e46: 791b ldrb r3, [r3, #4]
|
|
8018e48: 2b00 cmp r3, #0
|
|
8018e4a: d001 beq.n 8018e50 <dhcp_start+0x88>
|
|
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
|
|
8018e4c: f7ff fc90 bl 8018770 <dhcp_dec_pcb_refcount>
|
|
}
|
|
/* dhcp is cleared below, no need to reset flag*/
|
|
}
|
|
|
|
/* clear data structure */
|
|
memset(dhcp, 0, sizeof(struct dhcp));
|
|
8018e50: 2234 movs r2, #52 ; 0x34
|
|
8018e52: 2100 movs r1, #0
|
|
8018e54: 68f8 ldr r0, [r7, #12]
|
|
8018e56: f003 ff26 bl 801cca6 <memset>
|
|
/* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n"));
|
|
|
|
if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */
|
|
8018e5a: f7ff fc37 bl 80186cc <dhcp_inc_pcb_refcount>
|
|
8018e5e: 4603 mov r3, r0
|
|
8018e60: 2b00 cmp r3, #0
|
|
8018e62: d002 beq.n 8018e6a <dhcp_start+0xa2>
|
|
return ERR_MEM;
|
|
8018e64: f04f 33ff mov.w r3, #4294967295
|
|
8018e68: e020 b.n 8018eac <dhcp_start+0xe4>
|
|
}
|
|
dhcp->pcb_allocated = 1;
|
|
8018e6a: 68fb ldr r3, [r7, #12]
|
|
8018e6c: 2201 movs r2, #1
|
|
8018e6e: 711a strb r2, [r3, #4]
|
|
|
|
if (!netif_is_link_up(netif)) {
|
|
8018e70: 687b ldr r3, [r7, #4]
|
|
8018e72: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
8018e76: f003 0304 and.w r3, r3, #4
|
|
8018e7a: 2b00 cmp r3, #0
|
|
8018e7c: d105 bne.n 8018e8a <dhcp_start+0xc2>
|
|
/* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */
|
|
dhcp_set_state(dhcp, DHCP_STATE_INIT);
|
|
8018e7e: 2102 movs r1, #2
|
|
8018e80: 68f8 ldr r0, [r7, #12]
|
|
8018e82: f000 fd13 bl 80198ac <dhcp_set_state>
|
|
return ERR_OK;
|
|
8018e86: 2300 movs r3, #0
|
|
8018e88: e010 b.n 8018eac <dhcp_start+0xe4>
|
|
}
|
|
|
|
/* (re)start the DHCP negotiation */
|
|
result = dhcp_discover(netif);
|
|
8018e8a: 6878 ldr r0, [r7, #4]
|
|
8018e8c: f000 f90a bl 80190a4 <dhcp_discover>
|
|
8018e90: 4603 mov r3, r0
|
|
8018e92: 72fb strb r3, [r7, #11]
|
|
if (result != ERR_OK) {
|
|
8018e94: f997 300b ldrsb.w r3, [r7, #11]
|
|
8018e98: 2b00 cmp r3, #0
|
|
8018e9a: d005 beq.n 8018ea8 <dhcp_start+0xe0>
|
|
/* free resources allocated above */
|
|
dhcp_release_and_stop(netif);
|
|
8018e9c: 6878 ldr r0, [r7, #4]
|
|
8018e9e: f000 fc6b bl 8019778 <dhcp_release_and_stop>
|
|
return ERR_MEM;
|
|
8018ea2: f04f 33ff mov.w r3, #4294967295
|
|
8018ea6: e001 b.n 8018eac <dhcp_start+0xe4>
|
|
}
|
|
return result;
|
|
8018ea8: f997 300b ldrsb.w r3, [r7, #11]
|
|
}
|
|
8018eac: 4618 mov r0, r3
|
|
8018eae: 3710 adds r7, #16
|
|
8018eb0: 46bd mov sp, r7
|
|
8018eb2: bd80 pop {r7, pc}
|
|
8018eb4: 08020398 .word 0x08020398
|
|
8018eb8: 0802047c .word 0x0802047c
|
|
8018ebc: 080203f8 .word 0x080203f8
|
|
8018ec0: 080204c0 .word 0x080204c0
|
|
|
|
08018ec4 <dhcp_network_changed>:
|
|
* This enters the REBOOTING state to verify that the currently bound
|
|
* address is still valid.
|
|
*/
|
|
void
|
|
dhcp_network_changed(struct netif *netif)
|
|
{
|
|
8018ec4: b580 push {r7, lr}
|
|
8018ec6: b084 sub sp, #16
|
|
8018ec8: af00 add r7, sp, #0
|
|
8018eca: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018ecc: 687b ldr r3, [r7, #4]
|
|
8018ece: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018ed0: 60fb str r3, [r7, #12]
|
|
|
|
if (!dhcp) {
|
|
8018ed2: 68fb ldr r3, [r7, #12]
|
|
8018ed4: 2b00 cmp r3, #0
|
|
8018ed6: d037 beq.n 8018f48 <dhcp_network_changed+0x84>
|
|
return;
|
|
}
|
|
switch (dhcp->state) {
|
|
8018ed8: 68fb ldr r3, [r7, #12]
|
|
8018eda: 795b ldrb r3, [r3, #5]
|
|
8018edc: 2b0a cmp r3, #10
|
|
8018ede: d820 bhi.n 8018f22 <dhcp_network_changed+0x5e>
|
|
8018ee0: a201 add r2, pc, #4 ; (adr r2, 8018ee8 <dhcp_network_changed+0x24>)
|
|
8018ee2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8018ee6: bf00 nop
|
|
8018ee8: 08018f4d .word 0x08018f4d
|
|
8018eec: 08018f23 .word 0x08018f23
|
|
8018ef0: 08018f23 .word 0x08018f23
|
|
8018ef4: 08018f15 .word 0x08018f15
|
|
8018ef8: 08018f15 .word 0x08018f15
|
|
8018efc: 08018f15 .word 0x08018f15
|
|
8018f00: 08018f23 .word 0x08018f23
|
|
8018f04: 08018f23 .word 0x08018f23
|
|
8018f08: 08018f23 .word 0x08018f23
|
|
8018f0c: 08018f23 .word 0x08018f23
|
|
8018f10: 08018f15 .word 0x08018f15
|
|
case DHCP_STATE_REBINDING:
|
|
case DHCP_STATE_RENEWING:
|
|
case DHCP_STATE_BOUND:
|
|
case DHCP_STATE_REBOOTING:
|
|
dhcp->tries = 0;
|
|
8018f14: 68fb ldr r3, [r7, #12]
|
|
8018f16: 2200 movs r2, #0
|
|
8018f18: 719a strb r2, [r3, #6]
|
|
dhcp_reboot(netif);
|
|
8018f1a: 6878 ldr r0, [r7, #4]
|
|
8018f1c: f000 fb76 bl 801960c <dhcp_reboot>
|
|
break;
|
|
8018f20: e015 b.n 8018f4e <dhcp_network_changed+0x8a>
|
|
case DHCP_STATE_OFF:
|
|
/* stay off */
|
|
break;
|
|
default:
|
|
LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF);
|
|
8018f22: 68fb ldr r3, [r7, #12]
|
|
8018f24: 795b ldrb r3, [r3, #5]
|
|
8018f26: 2b0c cmp r3, #12
|
|
8018f28: d906 bls.n 8018f38 <dhcp_network_changed+0x74>
|
|
8018f2a: 4b0a ldr r3, [pc, #40] ; (8018f54 <dhcp_network_changed+0x90>)
|
|
8018f2c: f240 326d movw r2, #877 ; 0x36d
|
|
8018f30: 4909 ldr r1, [pc, #36] ; (8018f58 <dhcp_network_changed+0x94>)
|
|
8018f32: 480a ldr r0, [pc, #40] ; (8018f5c <dhcp_network_changed+0x98>)
|
|
8018f34: f003 fec0 bl 801ccb8 <iprintf>
|
|
autoip_stop(netif);
|
|
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
|
|
}
|
|
#endif /* LWIP_DHCP_AUTOIP_COOP */
|
|
/* ensure we start with short timeouts, even if already discovering */
|
|
dhcp->tries = 0;
|
|
8018f38: 68fb ldr r3, [r7, #12]
|
|
8018f3a: 2200 movs r2, #0
|
|
8018f3c: 719a strb r2, [r3, #6]
|
|
dhcp_discover(netif);
|
|
8018f3e: 6878 ldr r0, [r7, #4]
|
|
8018f40: f000 f8b0 bl 80190a4 <dhcp_discover>
|
|
break;
|
|
8018f44: bf00 nop
|
|
8018f46: e002 b.n 8018f4e <dhcp_network_changed+0x8a>
|
|
return;
|
|
8018f48: bf00 nop
|
|
8018f4a: e000 b.n 8018f4e <dhcp_network_changed+0x8a>
|
|
break;
|
|
8018f4c: bf00 nop
|
|
}
|
|
}
|
|
8018f4e: 3710 adds r7, #16
|
|
8018f50: 46bd mov sp, r7
|
|
8018f52: bd80 pop {r7, pc}
|
|
8018f54: 08020398 .word 0x08020398
|
|
8018f58: 080204e4 .word 0x080204e4
|
|
8018f5c: 080203f8 .word 0x080203f8
|
|
|
|
08018f60 <dhcp_arp_reply>:
|
|
* @param netif the network interface on which the reply was received
|
|
* @param addr The IP address we received a reply from
|
|
*/
|
|
void
|
|
dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr)
|
|
{
|
|
8018f60: b580 push {r7, lr}
|
|
8018f62: b084 sub sp, #16
|
|
8018f64: af00 add r7, sp, #0
|
|
8018f66: 6078 str r0, [r7, #4]
|
|
8018f68: 6039 str r1, [r7, #0]
|
|
struct dhcp *dhcp;
|
|
|
|
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
|
|
8018f6a: 687b ldr r3, [r7, #4]
|
|
8018f6c: 2b00 cmp r3, #0
|
|
8018f6e: d107 bne.n 8018f80 <dhcp_arp_reply+0x20>
|
|
8018f70: 4b0e ldr r3, [pc, #56] ; (8018fac <dhcp_arp_reply+0x4c>)
|
|
8018f72: f240 328b movw r2, #907 ; 0x38b
|
|
8018f76: 490e ldr r1, [pc, #56] ; (8018fb0 <dhcp_arp_reply+0x50>)
|
|
8018f78: 480e ldr r0, [pc, #56] ; (8018fb4 <dhcp_arp_reply+0x54>)
|
|
8018f7a: f003 fe9d bl 801ccb8 <iprintf>
|
|
8018f7e: e012 b.n 8018fa6 <dhcp_arp_reply+0x46>
|
|
dhcp = netif_dhcp_data(netif);
|
|
8018f80: 687b ldr r3, [r7, #4]
|
|
8018f82: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018f84: 60fb str r3, [r7, #12]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n"));
|
|
/* is a DHCP client doing an ARP check? */
|
|
if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) {
|
|
8018f86: 68fb ldr r3, [r7, #12]
|
|
8018f88: 2b00 cmp r3, #0
|
|
8018f8a: d00c beq.n 8018fa6 <dhcp_arp_reply+0x46>
|
|
8018f8c: 68fb ldr r3, [r7, #12]
|
|
8018f8e: 795b ldrb r3, [r3, #5]
|
|
8018f90: 2b08 cmp r3, #8
|
|
8018f92: d108 bne.n 8018fa6 <dhcp_arp_reply+0x46>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n",
|
|
ip4_addr_get_u32(addr)));
|
|
/* did a host respond with the address we
|
|
were offered by the DHCP server? */
|
|
if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) {
|
|
8018f94: 683b ldr r3, [r7, #0]
|
|
8018f96: 681a ldr r2, [r3, #0]
|
|
8018f98: 68fb ldr r3, [r7, #12]
|
|
8018f9a: 69db ldr r3, [r3, #28]
|
|
8018f9c: 429a cmp r2, r3
|
|
8018f9e: d102 bne.n 8018fa6 <dhcp_arp_reply+0x46>
|
|
/* we will not accept the offered address */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING,
|
|
("dhcp_arp_reply(): arp reply matched with offered address, declining\n"));
|
|
dhcp_decline(netif);
|
|
8018fa0: 6878 ldr r0, [r7, #4]
|
|
8018fa2: f000 f809 bl 8018fb8 <dhcp_decline>
|
|
}
|
|
}
|
|
}
|
|
8018fa6: 3710 adds r7, #16
|
|
8018fa8: 46bd mov sp, r7
|
|
8018faa: bd80 pop {r7, pc}
|
|
8018fac: 08020398 .word 0x08020398
|
|
8018fb0: 0802047c .word 0x0802047c
|
|
8018fb4: 080203f8 .word 0x080203f8
|
|
|
|
08018fb8 <dhcp_decline>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static err_t
|
|
dhcp_decline(struct netif *netif)
|
|
{
|
|
8018fb8: b5b0 push {r4, r5, r7, lr}
|
|
8018fba: b08a sub sp, #40 ; 0x28
|
|
8018fbc: af02 add r7, sp, #8
|
|
8018fbe: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8018fc0: 687b ldr r3, [r7, #4]
|
|
8018fc2: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8018fc4: 61bb str r3, [r7, #24]
|
|
u16_t msecs;
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n"));
|
|
dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF);
|
|
8018fc6: 210c movs r1, #12
|
|
8018fc8: 69b8 ldr r0, [r7, #24]
|
|
8018fca: f000 fc6f bl 80198ac <dhcp_set_state>
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len);
|
|
8018fce: f107 030c add.w r3, r7, #12
|
|
8018fd2: 2204 movs r2, #4
|
|
8018fd4: 69b9 ldr r1, [r7, #24]
|
|
8018fd6: 6878 ldr r0, [r7, #4]
|
|
8018fd8: f001 f8f2 bl 801a1c0 <dhcp_create_msg>
|
|
8018fdc: 6178 str r0, [r7, #20]
|
|
if (p_out != NULL) {
|
|
8018fde: 697b ldr r3, [r7, #20]
|
|
8018fe0: 2b00 cmp r3, #0
|
|
8018fe2: d035 beq.n 8019050 <dhcp_decline+0x98>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
8018fe4: 697b ldr r3, [r7, #20]
|
|
8018fe6: 685b ldr r3, [r3, #4]
|
|
8018fe8: 613b str r3, [r7, #16]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
|
|
8018fea: 89b8 ldrh r0, [r7, #12]
|
|
8018fec: 693b ldr r3, [r7, #16]
|
|
8018fee: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8018ff2: 2304 movs r3, #4
|
|
8018ff4: 2232 movs r2, #50 ; 0x32
|
|
8018ff6: f000 fc73 bl 80198e0 <dhcp_option>
|
|
8018ffa: 4603 mov r3, r0
|
|
8018ffc: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
|
|
8018ffe: 89bc ldrh r4, [r7, #12]
|
|
8019000: 693b ldr r3, [r7, #16]
|
|
8019002: f103 05f0 add.w r5, r3, #240 ; 0xf0
|
|
8019006: 69bb ldr r3, [r7, #24]
|
|
8019008: 69db ldr r3, [r3, #28]
|
|
801900a: 4618 mov r0, r3
|
|
801900c: f7f7 fd85 bl 8010b1a <lwip_htonl>
|
|
8019010: 4603 mov r3, r0
|
|
8019012: 461a mov r2, r3
|
|
8019014: 4629 mov r1, r5
|
|
8019016: 4620 mov r0, r4
|
|
8019018: f000 fcee bl 80199f8 <dhcp_option_long>
|
|
801901c: 4603 mov r3, r0
|
|
801901e: 81bb strh r3, [r7, #12]
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
8019020: 89b8 ldrh r0, [r7, #12]
|
|
8019022: 693b ldr r3, [r7, #16]
|
|
8019024: 33f0 adds r3, #240 ; 0xf0
|
|
8019026: 697a ldr r2, [r7, #20]
|
|
8019028: 4619 mov r1, r3
|
|
801902a: f001 f99f bl 801a36c <dhcp_option_trailer>
|
|
|
|
/* per section 4.4.4, broadcast DECLINE messages */
|
|
result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
|
|
801902e: 4b19 ldr r3, [pc, #100] ; (8019094 <dhcp_decline+0xdc>)
|
|
8019030: 6818 ldr r0, [r3, #0]
|
|
8019032: 4b19 ldr r3, [pc, #100] ; (8019098 <dhcp_decline+0xe0>)
|
|
8019034: 9301 str r3, [sp, #4]
|
|
8019036: 687b ldr r3, [r7, #4]
|
|
8019038: 9300 str r3, [sp, #0]
|
|
801903a: 2343 movs r3, #67 ; 0x43
|
|
801903c: 4a17 ldr r2, [pc, #92] ; (801909c <dhcp_decline+0xe4>)
|
|
801903e: 6979 ldr r1, [r7, #20]
|
|
8019040: f7ff f8be bl 80181c0 <udp_sendto_if_src>
|
|
8019044: 4603 mov r3, r0
|
|
8019046: 77fb strb r3, [r7, #31]
|
|
pbuf_free(p_out);
|
|
8019048: 6978 ldr r0, [r7, #20]
|
|
801904a: f7f9 f905 bl 8012258 <pbuf_free>
|
|
801904e: e001 b.n 8019054 <dhcp_decline+0x9c>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
|
|
("dhcp_decline: could not allocate DHCP request\n"));
|
|
result = ERR_MEM;
|
|
8019050: 23ff movs r3, #255 ; 0xff
|
|
8019052: 77fb strb r3, [r7, #31]
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
8019054: 69bb ldr r3, [r7, #24]
|
|
8019056: 799b ldrb r3, [r3, #6]
|
|
8019058: 2bff cmp r3, #255 ; 0xff
|
|
801905a: d005 beq.n 8019068 <dhcp_decline+0xb0>
|
|
dhcp->tries++;
|
|
801905c: 69bb ldr r3, [r7, #24]
|
|
801905e: 799b ldrb r3, [r3, #6]
|
|
8019060: 3301 adds r3, #1
|
|
8019062: b2da uxtb r2, r3
|
|
8019064: 69bb ldr r3, [r7, #24]
|
|
8019066: 719a strb r2, [r3, #6]
|
|
}
|
|
msecs = 10 * 1000;
|
|
8019068: f242 7310 movw r3, #10000 ; 0x2710
|
|
801906c: 81fb strh r3, [r7, #14]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
801906e: 89fb ldrh r3, [r7, #14]
|
|
8019070: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
8019074: 4a0a ldr r2, [pc, #40] ; (80190a0 <dhcp_decline+0xe8>)
|
|
8019076: fb82 1203 smull r1, r2, r2, r3
|
|
801907a: 1152 asrs r2, r2, #5
|
|
801907c: 17db asrs r3, r3, #31
|
|
801907e: 1ad3 subs r3, r2, r3
|
|
8019080: b29a uxth r2, r3
|
|
8019082: 69bb ldr r3, [r7, #24]
|
|
8019084: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
8019086: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
801908a: 4618 mov r0, r3
|
|
801908c: 3720 adds r7, #32
|
|
801908e: 46bd mov sp, r7
|
|
8019090: bdb0 pop {r4, r5, r7, pc}
|
|
8019092: bf00 nop
|
|
8019094: 2000876c .word 0x2000876c
|
|
8019098: 08022e68 .word 0x08022e68
|
|
801909c: 08022e6c .word 0x08022e6c
|
|
80190a0: 10624dd3 .word 0x10624dd3
|
|
|
|
080190a4 <dhcp_discover>:
|
|
*
|
|
* @param netif the netif under DHCP control
|
|
*/
|
|
static err_t
|
|
dhcp_discover(struct netif *netif)
|
|
{
|
|
80190a4: b580 push {r7, lr}
|
|
80190a6: b08a sub sp, #40 ; 0x28
|
|
80190a8: af02 add r7, sp, #8
|
|
80190aa: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
80190ac: 687b ldr r3, [r7, #4]
|
|
80190ae: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80190b0: 61bb str r3, [r7, #24]
|
|
err_t result = ERR_OK;
|
|
80190b2: 2300 movs r3, #0
|
|
80190b4: 75fb strb r3, [r7, #23]
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n"));
|
|
|
|
ip4_addr_set_any(&dhcp->offered_ip_addr);
|
|
80190b6: 69bb ldr r3, [r7, #24]
|
|
80190b8: 2200 movs r2, #0
|
|
80190ba: 61da str r2, [r3, #28]
|
|
dhcp_set_state(dhcp, DHCP_STATE_SELECTING);
|
|
80190bc: 2106 movs r1, #6
|
|
80190be: 69b8 ldr r0, [r7, #24]
|
|
80190c0: f000 fbf4 bl 80198ac <dhcp_set_state>
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len);
|
|
80190c4: f107 0308 add.w r3, r7, #8
|
|
80190c8: 2201 movs r2, #1
|
|
80190ca: 69b9 ldr r1, [r7, #24]
|
|
80190cc: 6878 ldr r0, [r7, #4]
|
|
80190ce: f001 f877 bl 801a1c0 <dhcp_create_msg>
|
|
80190d2: 6138 str r0, [r7, #16]
|
|
if (p_out != NULL) {
|
|
80190d4: 693b ldr r3, [r7, #16]
|
|
80190d6: 2b00 cmp r3, #0
|
|
80190d8: d04b beq.n 8019172 <dhcp_discover+0xce>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
80190da: 693b ldr r3, [r7, #16]
|
|
80190dc: 685b ldr r3, [r3, #4]
|
|
80190de: 60fb str r3, [r7, #12]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n"));
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
|
|
80190e0: 8938 ldrh r0, [r7, #8]
|
|
80190e2: 68fb ldr r3, [r7, #12]
|
|
80190e4: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80190e8: 2302 movs r3, #2
|
|
80190ea: 2239 movs r2, #57 ; 0x39
|
|
80190ec: f000 fbf8 bl 80198e0 <dhcp_option>
|
|
80190f0: 4603 mov r3, r0
|
|
80190f2: 813b strh r3, [r7, #8]
|
|
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
|
|
80190f4: 8938 ldrh r0, [r7, #8]
|
|
80190f6: 68fb ldr r3, [r7, #12]
|
|
80190f8: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80190fc: 687b ldr r3, [r7, #4]
|
|
80190fe: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8019100: 461a mov r2, r3
|
|
8019102: f000 fc47 bl 8019994 <dhcp_option_short>
|
|
8019106: 4603 mov r3, r0
|
|
8019108: 813b strh r3, [r7, #8]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
|
|
801910a: 8938 ldrh r0, [r7, #8]
|
|
801910c: 68fb ldr r3, [r7, #12]
|
|
801910e: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019112: 2303 movs r3, #3
|
|
8019114: 2237 movs r2, #55 ; 0x37
|
|
8019116: f000 fbe3 bl 80198e0 <dhcp_option>
|
|
801911a: 4603 mov r3, r0
|
|
801911c: 813b strh r3, [r7, #8]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
801911e: 2300 movs r3, #0
|
|
8019120: 77fb strb r3, [r7, #31]
|
|
8019122: e00e b.n 8019142 <dhcp_discover+0x9e>
|
|
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
|
|
8019124: 8938 ldrh r0, [r7, #8]
|
|
8019126: 68fb ldr r3, [r7, #12]
|
|
8019128: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801912c: 7ffb ldrb r3, [r7, #31]
|
|
801912e: 4a29 ldr r2, [pc, #164] ; (80191d4 <dhcp_discover+0x130>)
|
|
8019130: 5cd3 ldrb r3, [r2, r3]
|
|
8019132: 461a mov r2, r3
|
|
8019134: f000 fc08 bl 8019948 <dhcp_option_byte>
|
|
8019138: 4603 mov r3, r0
|
|
801913a: 813b strh r3, [r7, #8]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
801913c: 7ffb ldrb r3, [r7, #31]
|
|
801913e: 3301 adds r3, #1
|
|
8019140: 77fb strb r3, [r7, #31]
|
|
8019142: 7ffb ldrb r3, [r7, #31]
|
|
8019144: 2b02 cmp r3, #2
|
|
8019146: d9ed bls.n 8019124 <dhcp_discover+0x80>
|
|
}
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
8019148: 8938 ldrh r0, [r7, #8]
|
|
801914a: 68fb ldr r3, [r7, #12]
|
|
801914c: 33f0 adds r3, #240 ; 0xf0
|
|
801914e: 693a ldr r2, [r7, #16]
|
|
8019150: 4619 mov r1, r3
|
|
8019152: f001 f90b bl 801a36c <dhcp_option_trailer>
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n"));
|
|
udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY);
|
|
8019156: 4b20 ldr r3, [pc, #128] ; (80191d8 <dhcp_discover+0x134>)
|
|
8019158: 6818 ldr r0, [r3, #0]
|
|
801915a: 4b20 ldr r3, [pc, #128] ; (80191dc <dhcp_discover+0x138>)
|
|
801915c: 9301 str r3, [sp, #4]
|
|
801915e: 687b ldr r3, [r7, #4]
|
|
8019160: 9300 str r3, [sp, #0]
|
|
8019162: 2343 movs r3, #67 ; 0x43
|
|
8019164: 4a1e ldr r2, [pc, #120] ; (80191e0 <dhcp_discover+0x13c>)
|
|
8019166: 6939 ldr r1, [r7, #16]
|
|
8019168: f7ff f82a bl 80181c0 <udp_sendto_if_src>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n"));
|
|
pbuf_free(p_out);
|
|
801916c: 6938 ldr r0, [r7, #16]
|
|
801916e: f7f9 f873 bl 8012258 <pbuf_free>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n"));
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
8019172: 69bb ldr r3, [r7, #24]
|
|
8019174: 799b ldrb r3, [r3, #6]
|
|
8019176: 2bff cmp r3, #255 ; 0xff
|
|
8019178: d005 beq.n 8019186 <dhcp_discover+0xe2>
|
|
dhcp->tries++;
|
|
801917a: 69bb ldr r3, [r7, #24]
|
|
801917c: 799b ldrb r3, [r3, #6]
|
|
801917e: 3301 adds r3, #1
|
|
8019180: b2da uxtb r2, r3
|
|
8019182: 69bb ldr r3, [r7, #24]
|
|
8019184: 719a strb r2, [r3, #6]
|
|
if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) {
|
|
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON;
|
|
autoip_start(netif);
|
|
}
|
|
#endif /* LWIP_DHCP_AUTOIP_COOP */
|
|
msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000);
|
|
8019186: 69bb ldr r3, [r7, #24]
|
|
8019188: 799b ldrb r3, [r3, #6]
|
|
801918a: 2b05 cmp r3, #5
|
|
801918c: d80d bhi.n 80191aa <dhcp_discover+0x106>
|
|
801918e: 69bb ldr r3, [r7, #24]
|
|
8019190: 799b ldrb r3, [r3, #6]
|
|
8019192: 461a mov r2, r3
|
|
8019194: 2301 movs r3, #1
|
|
8019196: 4093 lsls r3, r2
|
|
8019198: b29b uxth r3, r3
|
|
801919a: 461a mov r2, r3
|
|
801919c: 0152 lsls r2, r2, #5
|
|
801919e: 1ad2 subs r2, r2, r3
|
|
80191a0: 0092 lsls r2, r2, #2
|
|
80191a2: 4413 add r3, r2
|
|
80191a4: 00db lsls r3, r3, #3
|
|
80191a6: b29b uxth r3, r3
|
|
80191a8: e001 b.n 80191ae <dhcp_discover+0x10a>
|
|
80191aa: f64e 2360 movw r3, #60000 ; 0xea60
|
|
80191ae: 817b strh r3, [r7, #10]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
80191b0: 897b ldrh r3, [r7, #10]
|
|
80191b2: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
80191b6: 4a0b ldr r2, [pc, #44] ; (80191e4 <dhcp_discover+0x140>)
|
|
80191b8: fb82 1203 smull r1, r2, r2, r3
|
|
80191bc: 1152 asrs r2, r2, #5
|
|
80191be: 17db asrs r3, r3, #31
|
|
80191c0: 1ad3 subs r3, r2, r3
|
|
80191c2: b29a uxth r2, r3
|
|
80191c4: 69bb ldr r3, [r7, #24]
|
|
80191c6: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
80191c8: f997 3017 ldrsb.w r3, [r7, #23]
|
|
}
|
|
80191cc: 4618 mov r0, r3
|
|
80191ce: 3720 adds r7, #32
|
|
80191d0: 46bd mov sp, r7
|
|
80191d2: bd80 pop {r7, pc}
|
|
80191d4: 20000080 .word 0x20000080
|
|
80191d8: 2000876c .word 0x2000876c
|
|
80191dc: 08022e68 .word 0x08022e68
|
|
80191e0: 08022e6c .word 0x08022e6c
|
|
80191e4: 10624dd3 .word 0x10624dd3
|
|
|
|
080191e8 <dhcp_bind>:
|
|
*
|
|
* @param netif network interface to bind to the offered address
|
|
*/
|
|
static void
|
|
dhcp_bind(struct netif *netif)
|
|
{
|
|
80191e8: b580 push {r7, lr}
|
|
80191ea: b088 sub sp, #32
|
|
80191ec: af00 add r7, sp, #0
|
|
80191ee: 6078 str r0, [r7, #4]
|
|
u32_t timeout;
|
|
struct dhcp *dhcp;
|
|
ip4_addr_t sn_mask, gw_addr;
|
|
LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;);
|
|
80191f0: 687b ldr r3, [r7, #4]
|
|
80191f2: 2b00 cmp r3, #0
|
|
80191f4: d107 bne.n 8019206 <dhcp_bind+0x1e>
|
|
80191f6: 4b64 ldr r3, [pc, #400] ; (8019388 <dhcp_bind+0x1a0>)
|
|
80191f8: f240 4215 movw r2, #1045 ; 0x415
|
|
80191fc: 4963 ldr r1, [pc, #396] ; (801938c <dhcp_bind+0x1a4>)
|
|
80191fe: 4864 ldr r0, [pc, #400] ; (8019390 <dhcp_bind+0x1a8>)
|
|
8019200: f003 fd5a bl 801ccb8 <iprintf>
|
|
8019204: e0bc b.n 8019380 <dhcp_bind+0x198>
|
|
dhcp = netif_dhcp_data(netif);
|
|
8019206: 687b ldr r3, [r7, #4]
|
|
8019208: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801920a: 61bb str r3, [r7, #24]
|
|
LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;);
|
|
801920c: 69bb ldr r3, [r7, #24]
|
|
801920e: 2b00 cmp r3, #0
|
|
8019210: d107 bne.n 8019222 <dhcp_bind+0x3a>
|
|
8019212: 4b5d ldr r3, [pc, #372] ; (8019388 <dhcp_bind+0x1a0>)
|
|
8019214: f240 4217 movw r2, #1047 ; 0x417
|
|
8019218: 495e ldr r1, [pc, #376] ; (8019394 <dhcp_bind+0x1ac>)
|
|
801921a: 485d ldr r0, [pc, #372] ; (8019390 <dhcp_bind+0x1a8>)
|
|
801921c: f003 fd4c bl 801ccb8 <iprintf>
|
|
8019220: e0ae b.n 8019380 <dhcp_bind+0x198>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num));
|
|
|
|
/* reset time used of lease */
|
|
dhcp->lease_used = 0;
|
|
8019222: 69bb ldr r3, [r7, #24]
|
|
8019224: 2200 movs r2, #0
|
|
8019226: 825a strh r2, [r3, #18]
|
|
|
|
if (dhcp->offered_t0_lease != 0xffffffffUL) {
|
|
8019228: 69bb ldr r3, [r7, #24]
|
|
801922a: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
801922c: f1b3 3fff cmp.w r3, #4294967295
|
|
8019230: d019 beq.n 8019266 <dhcp_bind+0x7e>
|
|
/* set renewal period timer */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease));
|
|
timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
|
|
8019232: 69bb ldr r3, [r7, #24]
|
|
8019234: 6a9b ldr r3, [r3, #40] ; 0x28
|
|
8019236: 331e adds r3, #30
|
|
8019238: 4a57 ldr r2, [pc, #348] ; (8019398 <dhcp_bind+0x1b0>)
|
|
801923a: fba2 2303 umull r2, r3, r2, r3
|
|
801923e: 095b lsrs r3, r3, #5
|
|
8019240: 61fb str r3, [r7, #28]
|
|
if (timeout > 0xffff) {
|
|
8019242: 69fb ldr r3, [r7, #28]
|
|
8019244: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8019248: d302 bcc.n 8019250 <dhcp_bind+0x68>
|
|
timeout = 0xffff;
|
|
801924a: f64f 73ff movw r3, #65535 ; 0xffff
|
|
801924e: 61fb str r3, [r7, #28]
|
|
}
|
|
dhcp->t0_timeout = (u16_t)timeout;
|
|
8019250: 69fb ldr r3, [r7, #28]
|
|
8019252: b29a uxth r2, r3
|
|
8019254: 69bb ldr r3, [r7, #24]
|
|
8019256: 829a strh r2, [r3, #20]
|
|
if (dhcp->t0_timeout == 0) {
|
|
8019258: 69bb ldr r3, [r7, #24]
|
|
801925a: 8a9b ldrh r3, [r3, #20]
|
|
801925c: 2b00 cmp r3, #0
|
|
801925e: d102 bne.n 8019266 <dhcp_bind+0x7e>
|
|
dhcp->t0_timeout = 1;
|
|
8019260: 69bb ldr r3, [r7, #24]
|
|
8019262: 2201 movs r2, #1
|
|
8019264: 829a strh r2, [r3, #20]
|
|
}
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000));
|
|
}
|
|
|
|
/* temporary DHCP lease? */
|
|
if (dhcp->offered_t1_renew != 0xffffffffUL) {
|
|
8019266: 69bb ldr r3, [r7, #24]
|
|
8019268: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
801926a: f1b3 3fff cmp.w r3, #4294967295
|
|
801926e: d01d beq.n 80192ac <dhcp_bind+0xc4>
|
|
/* set renewal period timer */
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew));
|
|
timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
|
|
8019270: 69bb ldr r3, [r7, #24]
|
|
8019272: 6adb ldr r3, [r3, #44] ; 0x2c
|
|
8019274: 331e adds r3, #30
|
|
8019276: 4a48 ldr r2, [pc, #288] ; (8019398 <dhcp_bind+0x1b0>)
|
|
8019278: fba2 2303 umull r2, r3, r2, r3
|
|
801927c: 095b lsrs r3, r3, #5
|
|
801927e: 61fb str r3, [r7, #28]
|
|
if (timeout > 0xffff) {
|
|
8019280: 69fb ldr r3, [r7, #28]
|
|
8019282: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8019286: d302 bcc.n 801928e <dhcp_bind+0xa6>
|
|
timeout = 0xffff;
|
|
8019288: f64f 73ff movw r3, #65535 ; 0xffff
|
|
801928c: 61fb str r3, [r7, #28]
|
|
}
|
|
dhcp->t1_timeout = (u16_t)timeout;
|
|
801928e: 69fb ldr r3, [r7, #28]
|
|
8019290: b29a uxth r2, r3
|
|
8019292: 69bb ldr r3, [r7, #24]
|
|
8019294: 815a strh r2, [r3, #10]
|
|
if (dhcp->t1_timeout == 0) {
|
|
8019296: 69bb ldr r3, [r7, #24]
|
|
8019298: 895b ldrh r3, [r3, #10]
|
|
801929a: 2b00 cmp r3, #0
|
|
801929c: d102 bne.n 80192a4 <dhcp_bind+0xbc>
|
|
dhcp->t1_timeout = 1;
|
|
801929e: 69bb ldr r3, [r7, #24]
|
|
80192a0: 2201 movs r2, #1
|
|
80192a2: 815a strh r2, [r3, #10]
|
|
}
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000));
|
|
dhcp->t1_renew_time = dhcp->t1_timeout;
|
|
80192a4: 69bb ldr r3, [r7, #24]
|
|
80192a6: 895a ldrh r2, [r3, #10]
|
|
80192a8: 69bb ldr r3, [r7, #24]
|
|
80192aa: 81da strh r2, [r3, #14]
|
|
}
|
|
/* set renewal period timer */
|
|
if (dhcp->offered_t2_rebind != 0xffffffffUL) {
|
|
80192ac: 69bb ldr r3, [r7, #24]
|
|
80192ae: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80192b0: f1b3 3fff cmp.w r3, #4294967295
|
|
80192b4: d01d beq.n 80192f2 <dhcp_bind+0x10a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind));
|
|
timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS;
|
|
80192b6: 69bb ldr r3, [r7, #24]
|
|
80192b8: 6b1b ldr r3, [r3, #48] ; 0x30
|
|
80192ba: 331e adds r3, #30
|
|
80192bc: 4a36 ldr r2, [pc, #216] ; (8019398 <dhcp_bind+0x1b0>)
|
|
80192be: fba2 2303 umull r2, r3, r2, r3
|
|
80192c2: 095b lsrs r3, r3, #5
|
|
80192c4: 61fb str r3, [r7, #28]
|
|
if (timeout > 0xffff) {
|
|
80192c6: 69fb ldr r3, [r7, #28]
|
|
80192c8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
80192cc: d302 bcc.n 80192d4 <dhcp_bind+0xec>
|
|
timeout = 0xffff;
|
|
80192ce: f64f 73ff movw r3, #65535 ; 0xffff
|
|
80192d2: 61fb str r3, [r7, #28]
|
|
}
|
|
dhcp->t2_timeout = (u16_t)timeout;
|
|
80192d4: 69fb ldr r3, [r7, #28]
|
|
80192d6: b29a uxth r2, r3
|
|
80192d8: 69bb ldr r3, [r7, #24]
|
|
80192da: 819a strh r2, [r3, #12]
|
|
if (dhcp->t2_timeout == 0) {
|
|
80192dc: 69bb ldr r3, [r7, #24]
|
|
80192de: 899b ldrh r3, [r3, #12]
|
|
80192e0: 2b00 cmp r3, #0
|
|
80192e2: d102 bne.n 80192ea <dhcp_bind+0x102>
|
|
dhcp->t2_timeout = 1;
|
|
80192e4: 69bb ldr r3, [r7, #24]
|
|
80192e6: 2201 movs r2, #1
|
|
80192e8: 819a strh r2, [r3, #12]
|
|
}
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000));
|
|
dhcp->t2_rebind_time = dhcp->t2_timeout;
|
|
80192ea: 69bb ldr r3, [r7, #24]
|
|
80192ec: 899a ldrh r2, [r3, #12]
|
|
80192ee: 69bb ldr r3, [r7, #24]
|
|
80192f0: 821a strh r2, [r3, #16]
|
|
}
|
|
|
|
/* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */
|
|
if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) {
|
|
80192f2: 69bb ldr r3, [r7, #24]
|
|
80192f4: 895a ldrh r2, [r3, #10]
|
|
80192f6: 69bb ldr r3, [r7, #24]
|
|
80192f8: 899b ldrh r3, [r3, #12]
|
|
80192fa: 429a cmp r2, r3
|
|
80192fc: d306 bcc.n 801930c <dhcp_bind+0x124>
|
|
80192fe: 69bb ldr r3, [r7, #24]
|
|
8019300: 899b ldrh r3, [r3, #12]
|
|
8019302: 2b00 cmp r3, #0
|
|
8019304: d002 beq.n 801930c <dhcp_bind+0x124>
|
|
dhcp->t1_timeout = 0;
|
|
8019306: 69bb ldr r3, [r7, #24]
|
|
8019308: 2200 movs r2, #0
|
|
801930a: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
if (dhcp->subnet_mask_given) {
|
|
801930c: 69bb ldr r3, [r7, #24]
|
|
801930e: 79db ldrb r3, [r3, #7]
|
|
8019310: 2b00 cmp r3, #0
|
|
8019312: d003 beq.n 801931c <dhcp_bind+0x134>
|
|
/* copy offered network mask */
|
|
ip4_addr_copy(sn_mask, dhcp->offered_sn_mask);
|
|
8019314: 69bb ldr r3, [r7, #24]
|
|
8019316: 6a1b ldr r3, [r3, #32]
|
|
8019318: 613b str r3, [r7, #16]
|
|
801931a: e014 b.n 8019346 <dhcp_bind+0x15e>
|
|
} else {
|
|
/* subnet mask not given, choose a safe subnet mask given the network class */
|
|
u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr);
|
|
801931c: 69bb ldr r3, [r7, #24]
|
|
801931e: 331c adds r3, #28
|
|
8019320: 781b ldrb r3, [r3, #0]
|
|
8019322: 75fb strb r3, [r7, #23]
|
|
if (first_octet <= 127) {
|
|
8019324: f997 3017 ldrsb.w r3, [r7, #23]
|
|
8019328: 2b00 cmp r3, #0
|
|
801932a: db02 blt.n 8019332 <dhcp_bind+0x14a>
|
|
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL));
|
|
801932c: 23ff movs r3, #255 ; 0xff
|
|
801932e: 613b str r3, [r7, #16]
|
|
8019330: e009 b.n 8019346 <dhcp_bind+0x15e>
|
|
} else if (first_octet >= 192) {
|
|
8019332: 7dfb ldrb r3, [r7, #23]
|
|
8019334: 2bbf cmp r3, #191 ; 0xbf
|
|
8019336: d903 bls.n 8019340 <dhcp_bind+0x158>
|
|
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL));
|
|
8019338: f06f 437f mvn.w r3, #4278190080 ; 0xff000000
|
|
801933c: 613b str r3, [r7, #16]
|
|
801933e: e002 b.n 8019346 <dhcp_bind+0x15e>
|
|
} else {
|
|
ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL));
|
|
8019340: f64f 73ff movw r3, #65535 ; 0xffff
|
|
8019344: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
|
|
ip4_addr_copy(gw_addr, dhcp->offered_gw_addr);
|
|
8019346: 69bb ldr r3, [r7, #24]
|
|
8019348: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801934a: 60fb str r3, [r7, #12]
|
|
/* gateway address not given? */
|
|
if (ip4_addr_isany_val(gw_addr)) {
|
|
801934c: 68fb ldr r3, [r7, #12]
|
|
801934e: 2b00 cmp r3, #0
|
|
8019350: d108 bne.n 8019364 <dhcp_bind+0x17c>
|
|
/* copy network address */
|
|
ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask);
|
|
8019352: 69bb ldr r3, [r7, #24]
|
|
8019354: 69da ldr r2, [r3, #28]
|
|
8019356: 693b ldr r3, [r7, #16]
|
|
8019358: 4013 ands r3, r2
|
|
801935a: 60fb str r3, [r7, #12]
|
|
/* use first host address on network as gateway */
|
|
ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL));
|
|
801935c: 68fb ldr r3, [r7, #12]
|
|
801935e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
|
|
8019362: 60fb str r3, [r7, #12]
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n",
|
|
ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr)));
|
|
/* netif is now bound to DHCP leased address - set this before assigning the address
|
|
to ensure the callback can use dhcp_supplied_address() */
|
|
dhcp_set_state(dhcp, DHCP_STATE_BOUND);
|
|
8019364: 210a movs r1, #10
|
|
8019366: 69b8 ldr r0, [r7, #24]
|
|
8019368: f000 faa0 bl 80198ac <dhcp_set_state>
|
|
|
|
netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr);
|
|
801936c: 69bb ldr r3, [r7, #24]
|
|
801936e: f103 011c add.w r1, r3, #28
|
|
8019372: f107 030c add.w r3, r7, #12
|
|
8019376: f107 0210 add.w r2, r7, #16
|
|
801937a: 6878 ldr r0, [r7, #4]
|
|
801937c: f7f8 fa62 bl 8011844 <netif_set_addr>
|
|
/* interface is used by routing now that an address is set */
|
|
}
|
|
8019380: 3720 adds r7, #32
|
|
8019382: 46bd mov sp, r7
|
|
8019384: bd80 pop {r7, pc}
|
|
8019386: bf00 nop
|
|
8019388: 08020398 .word 0x08020398
|
|
801938c: 080204f8 .word 0x080204f8
|
|
8019390: 080203f8 .word 0x080203f8
|
|
8019394: 08020514 .word 0x08020514
|
|
8019398: 88888889 .word 0x88888889
|
|
|
|
0801939c <dhcp_renew>:
|
|
*
|
|
* @param netif network interface which must renew its lease
|
|
*/
|
|
err_t
|
|
dhcp_renew(struct netif *netif)
|
|
{
|
|
801939c: b580 push {r7, lr}
|
|
801939e: b08a sub sp, #40 ; 0x28
|
|
80193a0: af02 add r7, sp, #8
|
|
80193a2: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
80193a4: 687b ldr r3, [r7, #4]
|
|
80193a6: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80193a8: 61bb str r3, [r7, #24]
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n"));
|
|
dhcp_set_state(dhcp, DHCP_STATE_RENEWING);
|
|
80193aa: 2105 movs r1, #5
|
|
80193ac: 69b8 ldr r0, [r7, #24]
|
|
80193ae: f000 fa7d bl 80198ac <dhcp_set_state>
|
|
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
|
|
80193b2: f107 030c add.w r3, r7, #12
|
|
80193b6: 2203 movs r2, #3
|
|
80193b8: 69b9 ldr r1, [r7, #24]
|
|
80193ba: 6878 ldr r0, [r7, #4]
|
|
80193bc: f000 ff00 bl 801a1c0 <dhcp_create_msg>
|
|
80193c0: 6178 str r0, [r7, #20]
|
|
if (p_out != NULL) {
|
|
80193c2: 697b ldr r3, [r7, #20]
|
|
80193c4: 2b00 cmp r3, #0
|
|
80193c6: d04e beq.n 8019466 <dhcp_renew+0xca>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
80193c8: 697b ldr r3, [r7, #20]
|
|
80193ca: 685b ldr r3, [r3, #4]
|
|
80193cc: 613b str r3, [r7, #16]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
|
|
80193ce: 89b8 ldrh r0, [r7, #12]
|
|
80193d0: 693b ldr r3, [r7, #16]
|
|
80193d2: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80193d6: 2302 movs r3, #2
|
|
80193d8: 2239 movs r2, #57 ; 0x39
|
|
80193da: f000 fa81 bl 80198e0 <dhcp_option>
|
|
80193de: 4603 mov r3, r0
|
|
80193e0: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
|
|
80193e2: 89b8 ldrh r0, [r7, #12]
|
|
80193e4: 693b ldr r3, [r7, #16]
|
|
80193e6: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80193ea: 687b ldr r3, [r7, #4]
|
|
80193ec: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
80193ee: 461a mov r2, r3
|
|
80193f0: f000 fad0 bl 8019994 <dhcp_option_short>
|
|
80193f4: 4603 mov r3, r0
|
|
80193f6: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
|
|
80193f8: 89b8 ldrh r0, [r7, #12]
|
|
80193fa: 693b ldr r3, [r7, #16]
|
|
80193fc: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019400: 2303 movs r3, #3
|
|
8019402: 2237 movs r2, #55 ; 0x37
|
|
8019404: f000 fa6c bl 80198e0 <dhcp_option>
|
|
8019408: 4603 mov r3, r0
|
|
801940a: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
801940c: 2300 movs r3, #0
|
|
801940e: 77bb strb r3, [r7, #30]
|
|
8019410: e00e b.n 8019430 <dhcp_renew+0x94>
|
|
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
|
|
8019412: 89b8 ldrh r0, [r7, #12]
|
|
8019414: 693b ldr r3, [r7, #16]
|
|
8019416: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801941a: 7fbb ldrb r3, [r7, #30]
|
|
801941c: 4a2a ldr r2, [pc, #168] ; (80194c8 <dhcp_renew+0x12c>)
|
|
801941e: 5cd3 ldrb r3, [r2, r3]
|
|
8019420: 461a mov r2, r3
|
|
8019422: f000 fa91 bl 8019948 <dhcp_option_byte>
|
|
8019426: 4603 mov r3, r0
|
|
8019428: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
801942a: 7fbb ldrb r3, [r7, #30]
|
|
801942c: 3301 adds r3, #1
|
|
801942e: 77bb strb r3, [r7, #30]
|
|
8019430: 7fbb ldrb r3, [r7, #30]
|
|
8019432: 2b02 cmp r3, #2
|
|
8019434: d9ed bls.n 8019412 <dhcp_renew+0x76>
|
|
#if LWIP_NETIF_HOSTNAME
|
|
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
|
|
#endif /* LWIP_NETIF_HOSTNAME */
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
8019436: 89b8 ldrh r0, [r7, #12]
|
|
8019438: 693b ldr r3, [r7, #16]
|
|
801943a: 33f0 adds r3, #240 ; 0xf0
|
|
801943c: 697a ldr r2, [r7, #20]
|
|
801943e: 4619 mov r1, r3
|
|
8019440: f000 ff94 bl 801a36c <dhcp_option_trailer>
|
|
|
|
result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
|
|
8019444: 4b21 ldr r3, [pc, #132] ; (80194cc <dhcp_renew+0x130>)
|
|
8019446: 6818 ldr r0, [r3, #0]
|
|
8019448: 69bb ldr r3, [r7, #24]
|
|
801944a: f103 0218 add.w r2, r3, #24
|
|
801944e: 687b ldr r3, [r7, #4]
|
|
8019450: 9300 str r3, [sp, #0]
|
|
8019452: 2343 movs r3, #67 ; 0x43
|
|
8019454: 6979 ldr r1, [r7, #20]
|
|
8019456: f7fe fe3f bl 80180d8 <udp_sendto_if>
|
|
801945a: 4603 mov r3, r0
|
|
801945c: 77fb strb r3, [r7, #31]
|
|
pbuf_free(p_out);
|
|
801945e: 6978 ldr r0, [r7, #20]
|
|
8019460: f7f8 fefa bl 8012258 <pbuf_free>
|
|
8019464: e001 b.n 801946a <dhcp_renew+0xce>
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n"));
|
|
result = ERR_MEM;
|
|
8019466: 23ff movs r3, #255 ; 0xff
|
|
8019468: 77fb strb r3, [r7, #31]
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
801946a: 69bb ldr r3, [r7, #24]
|
|
801946c: 799b ldrb r3, [r3, #6]
|
|
801946e: 2bff cmp r3, #255 ; 0xff
|
|
8019470: d005 beq.n 801947e <dhcp_renew+0xe2>
|
|
dhcp->tries++;
|
|
8019472: 69bb ldr r3, [r7, #24]
|
|
8019474: 799b ldrb r3, [r3, #6]
|
|
8019476: 3301 adds r3, #1
|
|
8019478: b2da uxtb r2, r3
|
|
801947a: 69bb ldr r3, [r7, #24]
|
|
801947c: 719a strb r2, [r3, #6]
|
|
}
|
|
/* back-off on retries, but to a maximum of 20 seconds */
|
|
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000);
|
|
801947e: 69bb ldr r3, [r7, #24]
|
|
8019480: 799b ldrb r3, [r3, #6]
|
|
8019482: 2b09 cmp r3, #9
|
|
8019484: d80a bhi.n 801949c <dhcp_renew+0x100>
|
|
8019486: 69bb ldr r3, [r7, #24]
|
|
8019488: 799b ldrb r3, [r3, #6]
|
|
801948a: b29b uxth r3, r3
|
|
801948c: 461a mov r2, r3
|
|
801948e: 0152 lsls r2, r2, #5
|
|
8019490: 1ad2 subs r2, r2, r3
|
|
8019492: 0092 lsls r2, r2, #2
|
|
8019494: 4413 add r3, r2
|
|
8019496: 011b lsls r3, r3, #4
|
|
8019498: b29b uxth r3, r3
|
|
801949a: e001 b.n 80194a0 <dhcp_renew+0x104>
|
|
801949c: f644 6320 movw r3, #20000 ; 0x4e20
|
|
80194a0: 81fb strh r3, [r7, #14]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
80194a2: 89fb ldrh r3, [r7, #14]
|
|
80194a4: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
80194a8: 4a09 ldr r2, [pc, #36] ; (80194d0 <dhcp_renew+0x134>)
|
|
80194aa: fb82 1203 smull r1, r2, r2, r3
|
|
80194ae: 1152 asrs r2, r2, #5
|
|
80194b0: 17db asrs r3, r3, #31
|
|
80194b2: 1ad3 subs r3, r2, r3
|
|
80194b4: b29a uxth r2, r3
|
|
80194b6: 69bb ldr r3, [r7, #24]
|
|
80194b8: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
80194ba: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
80194be: 4618 mov r0, r3
|
|
80194c0: 3720 adds r7, #32
|
|
80194c2: 46bd mov sp, r7
|
|
80194c4: bd80 pop {r7, pc}
|
|
80194c6: bf00 nop
|
|
80194c8: 20000080 .word 0x20000080
|
|
80194cc: 2000876c .word 0x2000876c
|
|
80194d0: 10624dd3 .word 0x10624dd3
|
|
|
|
080194d4 <dhcp_rebind>:
|
|
*
|
|
* @param netif network interface which must rebind with a DHCP server
|
|
*/
|
|
static err_t
|
|
dhcp_rebind(struct netif *netif)
|
|
{
|
|
80194d4: b580 push {r7, lr}
|
|
80194d6: b08a sub sp, #40 ; 0x28
|
|
80194d8: af02 add r7, sp, #8
|
|
80194da: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
80194dc: 687b ldr r3, [r7, #4]
|
|
80194de: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
80194e0: 61bb str r3, [r7, #24]
|
|
u8_t i;
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n"));
|
|
dhcp_set_state(dhcp, DHCP_STATE_REBINDING);
|
|
80194e2: 2104 movs r1, #4
|
|
80194e4: 69b8 ldr r0, [r7, #24]
|
|
80194e6: f000 f9e1 bl 80198ac <dhcp_set_state>
|
|
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
|
|
80194ea: f107 030c add.w r3, r7, #12
|
|
80194ee: 2203 movs r2, #3
|
|
80194f0: 69b9 ldr r1, [r7, #24]
|
|
80194f2: 6878 ldr r0, [r7, #4]
|
|
80194f4: f000 fe64 bl 801a1c0 <dhcp_create_msg>
|
|
80194f8: 6178 str r0, [r7, #20]
|
|
if (p_out != NULL) {
|
|
80194fa: 697b ldr r3, [r7, #20]
|
|
80194fc: 2b00 cmp r3, #0
|
|
80194fe: d04c beq.n 801959a <dhcp_rebind+0xc6>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
8019500: 697b ldr r3, [r7, #20]
|
|
8019502: 685b ldr r3, [r3, #4]
|
|
8019504: 613b str r3, [r7, #16]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
|
|
8019506: 89b8 ldrh r0, [r7, #12]
|
|
8019508: 693b ldr r3, [r7, #16]
|
|
801950a: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801950e: 2302 movs r3, #2
|
|
8019510: 2239 movs r2, #57 ; 0x39
|
|
8019512: f000 f9e5 bl 80198e0 <dhcp_option>
|
|
8019516: 4603 mov r3, r0
|
|
8019518: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif));
|
|
801951a: 89b8 ldrh r0, [r7, #12]
|
|
801951c: 693b ldr r3, [r7, #16]
|
|
801951e: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019522: 687b ldr r3, [r7, #4]
|
|
8019524: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
8019526: 461a mov r2, r3
|
|
8019528: f000 fa34 bl 8019994 <dhcp_option_short>
|
|
801952c: 4603 mov r3, r0
|
|
801952e: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
|
|
8019530: 89b8 ldrh r0, [r7, #12]
|
|
8019532: 693b ldr r3, [r7, #16]
|
|
8019534: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019538: 2303 movs r3, #3
|
|
801953a: 2237 movs r2, #55 ; 0x37
|
|
801953c: f000 f9d0 bl 80198e0 <dhcp_option>
|
|
8019540: 4603 mov r3, r0
|
|
8019542: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
8019544: 2300 movs r3, #0
|
|
8019546: 77bb strb r3, [r7, #30]
|
|
8019548: e00e b.n 8019568 <dhcp_rebind+0x94>
|
|
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
|
|
801954a: 89b8 ldrh r0, [r7, #12]
|
|
801954c: 693b ldr r3, [r7, #16]
|
|
801954e: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019552: 7fbb ldrb r3, [r7, #30]
|
|
8019554: 4a29 ldr r2, [pc, #164] ; (80195fc <dhcp_rebind+0x128>)
|
|
8019556: 5cd3 ldrb r3, [r2, r3]
|
|
8019558: 461a mov r2, r3
|
|
801955a: f000 f9f5 bl 8019948 <dhcp_option_byte>
|
|
801955e: 4603 mov r3, r0
|
|
8019560: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
8019562: 7fbb ldrb r3, [r7, #30]
|
|
8019564: 3301 adds r3, #1
|
|
8019566: 77bb strb r3, [r7, #30]
|
|
8019568: 7fbb ldrb r3, [r7, #30]
|
|
801956a: 2b02 cmp r3, #2
|
|
801956c: d9ed bls.n 801954a <dhcp_rebind+0x76>
|
|
#if LWIP_NETIF_HOSTNAME
|
|
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
|
|
#endif /* LWIP_NETIF_HOSTNAME */
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
801956e: 89b8 ldrh r0, [r7, #12]
|
|
8019570: 693b ldr r3, [r7, #16]
|
|
8019572: 33f0 adds r3, #240 ; 0xf0
|
|
8019574: 697a ldr r2, [r7, #20]
|
|
8019576: 4619 mov r1, r3
|
|
8019578: f000 fef8 bl 801a36c <dhcp_option_trailer>
|
|
|
|
/* broadcast to server */
|
|
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
|
|
801957c: 4b20 ldr r3, [pc, #128] ; (8019600 <dhcp_rebind+0x12c>)
|
|
801957e: 6818 ldr r0, [r3, #0]
|
|
8019580: 687b ldr r3, [r7, #4]
|
|
8019582: 9300 str r3, [sp, #0]
|
|
8019584: 2343 movs r3, #67 ; 0x43
|
|
8019586: 4a1f ldr r2, [pc, #124] ; (8019604 <dhcp_rebind+0x130>)
|
|
8019588: 6979 ldr r1, [r7, #20]
|
|
801958a: f7fe fda5 bl 80180d8 <udp_sendto_if>
|
|
801958e: 4603 mov r3, r0
|
|
8019590: 77fb strb r3, [r7, #31]
|
|
pbuf_free(p_out);
|
|
8019592: 6978 ldr r0, [r7, #20]
|
|
8019594: f7f8 fe60 bl 8012258 <pbuf_free>
|
|
8019598: e001 b.n 801959e <dhcp_rebind+0xca>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n"));
|
|
result = ERR_MEM;
|
|
801959a: 23ff movs r3, #255 ; 0xff
|
|
801959c: 77fb strb r3, [r7, #31]
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
801959e: 69bb ldr r3, [r7, #24]
|
|
80195a0: 799b ldrb r3, [r3, #6]
|
|
80195a2: 2bff cmp r3, #255 ; 0xff
|
|
80195a4: d005 beq.n 80195b2 <dhcp_rebind+0xde>
|
|
dhcp->tries++;
|
|
80195a6: 69bb ldr r3, [r7, #24]
|
|
80195a8: 799b ldrb r3, [r3, #6]
|
|
80195aa: 3301 adds r3, #1
|
|
80195ac: b2da uxtb r2, r3
|
|
80195ae: 69bb ldr r3, [r7, #24]
|
|
80195b0: 719a strb r2, [r3, #6]
|
|
}
|
|
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
|
|
80195b2: 69bb ldr r3, [r7, #24]
|
|
80195b4: 799b ldrb r3, [r3, #6]
|
|
80195b6: 2b09 cmp r3, #9
|
|
80195b8: d80a bhi.n 80195d0 <dhcp_rebind+0xfc>
|
|
80195ba: 69bb ldr r3, [r7, #24]
|
|
80195bc: 799b ldrb r3, [r3, #6]
|
|
80195be: b29b uxth r3, r3
|
|
80195c0: 461a mov r2, r3
|
|
80195c2: 0152 lsls r2, r2, #5
|
|
80195c4: 1ad2 subs r2, r2, r3
|
|
80195c6: 0092 lsls r2, r2, #2
|
|
80195c8: 4413 add r3, r2
|
|
80195ca: 00db lsls r3, r3, #3
|
|
80195cc: b29b uxth r3, r3
|
|
80195ce: e001 b.n 80195d4 <dhcp_rebind+0x100>
|
|
80195d0: f242 7310 movw r3, #10000 ; 0x2710
|
|
80195d4: 81fb strh r3, [r7, #14]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
80195d6: 89fb ldrh r3, [r7, #14]
|
|
80195d8: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
80195dc: 4a0a ldr r2, [pc, #40] ; (8019608 <dhcp_rebind+0x134>)
|
|
80195de: fb82 1203 smull r1, r2, r2, r3
|
|
80195e2: 1152 asrs r2, r2, #5
|
|
80195e4: 17db asrs r3, r3, #31
|
|
80195e6: 1ad3 subs r3, r2, r3
|
|
80195e8: b29a uxth r2, r3
|
|
80195ea: 69bb ldr r3, [r7, #24]
|
|
80195ec: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
80195ee: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
80195f2: 4618 mov r0, r3
|
|
80195f4: 3720 adds r7, #32
|
|
80195f6: 46bd mov sp, r7
|
|
80195f8: bd80 pop {r7, pc}
|
|
80195fa: bf00 nop
|
|
80195fc: 20000080 .word 0x20000080
|
|
8019600: 2000876c .word 0x2000876c
|
|
8019604: 08022e6c .word 0x08022e6c
|
|
8019608: 10624dd3 .word 0x10624dd3
|
|
|
|
0801960c <dhcp_reboot>:
|
|
*
|
|
* @param netif network interface which must reboot
|
|
*/
|
|
static err_t
|
|
dhcp_reboot(struct netif *netif)
|
|
{
|
|
801960c: b5b0 push {r4, r5, r7, lr}
|
|
801960e: b08a sub sp, #40 ; 0x28
|
|
8019610: af02 add r7, sp, #8
|
|
8019612: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8019614: 687b ldr r3, [r7, #4]
|
|
8019616: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8019618: 61bb str r3, [r7, #24]
|
|
u8_t i;
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n"));
|
|
dhcp_set_state(dhcp, DHCP_STATE_REBOOTING);
|
|
801961a: 2103 movs r1, #3
|
|
801961c: 69b8 ldr r0, [r7, #24]
|
|
801961e: f000 f945 bl 80198ac <dhcp_set_state>
|
|
|
|
/* create and initialize the DHCP message header */
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len);
|
|
8019622: f107 030c add.w r3, r7, #12
|
|
8019626: 2203 movs r2, #3
|
|
8019628: 69b9 ldr r1, [r7, #24]
|
|
801962a: 6878 ldr r0, [r7, #4]
|
|
801962c: f000 fdc8 bl 801a1c0 <dhcp_create_msg>
|
|
8019630: 6178 str r0, [r7, #20]
|
|
if (p_out != NULL) {
|
|
8019632: 697b ldr r3, [r7, #20]
|
|
8019634: 2b00 cmp r3, #0
|
|
8019636: d066 beq.n 8019706 <dhcp_reboot+0xfa>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
8019638: 697b ldr r3, [r7, #20]
|
|
801963a: 685b ldr r3, [r3, #4]
|
|
801963c: 613b str r3, [r7, #16]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN);
|
|
801963e: 89b8 ldrh r0, [r7, #12]
|
|
8019640: 693b ldr r3, [r7, #16]
|
|
8019642: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
8019646: 2302 movs r3, #2
|
|
8019648: 2239 movs r2, #57 ; 0x39
|
|
801964a: f000 f949 bl 80198e0 <dhcp_option>
|
|
801964e: 4603 mov r3, r0
|
|
8019650: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED);
|
|
8019652: 89b8 ldrh r0, [r7, #12]
|
|
8019654: 693b ldr r3, [r7, #16]
|
|
8019656: 33f0 adds r3, #240 ; 0xf0
|
|
8019658: f44f 7210 mov.w r2, #576 ; 0x240
|
|
801965c: 4619 mov r1, r3
|
|
801965e: f000 f999 bl 8019994 <dhcp_option_short>
|
|
8019662: 4603 mov r3, r0
|
|
8019664: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4);
|
|
8019666: 89b8 ldrh r0, [r7, #12]
|
|
8019668: 693b ldr r3, [r7, #16]
|
|
801966a: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801966e: 2304 movs r3, #4
|
|
8019670: 2232 movs r2, #50 ; 0x32
|
|
8019672: f000 f935 bl 80198e0 <dhcp_option>
|
|
8019676: 4603 mov r3, r0
|
|
8019678: 81bb strh r3, [r7, #12]
|
|
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr)));
|
|
801967a: 89bc ldrh r4, [r7, #12]
|
|
801967c: 693b ldr r3, [r7, #16]
|
|
801967e: f103 05f0 add.w r5, r3, #240 ; 0xf0
|
|
8019682: 69bb ldr r3, [r7, #24]
|
|
8019684: 69db ldr r3, [r3, #28]
|
|
8019686: 4618 mov r0, r3
|
|
8019688: f7f7 fa47 bl 8010b1a <lwip_htonl>
|
|
801968c: 4603 mov r3, r0
|
|
801968e: 461a mov r2, r3
|
|
8019690: 4629 mov r1, r5
|
|
8019692: 4620 mov r0, r4
|
|
8019694: f000 f9b0 bl 80199f8 <dhcp_option_long>
|
|
8019698: 4603 mov r3, r0
|
|
801969a: 81bb strh r3, [r7, #12]
|
|
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options));
|
|
801969c: 89b8 ldrh r0, [r7, #12]
|
|
801969e: 693b ldr r3, [r7, #16]
|
|
80196a0: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80196a4: 2303 movs r3, #3
|
|
80196a6: 2237 movs r2, #55 ; 0x37
|
|
80196a8: f000 f91a bl 80198e0 <dhcp_option>
|
|
80196ac: 4603 mov r3, r0
|
|
80196ae: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
80196b0: 2300 movs r3, #0
|
|
80196b2: 77bb strb r3, [r7, #30]
|
|
80196b4: e00e b.n 80196d4 <dhcp_reboot+0xc8>
|
|
options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]);
|
|
80196b6: 89b8 ldrh r0, [r7, #12]
|
|
80196b8: 693b ldr r3, [r7, #16]
|
|
80196ba: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
80196be: 7fbb ldrb r3, [r7, #30]
|
|
80196c0: 4a29 ldr r2, [pc, #164] ; (8019768 <dhcp_reboot+0x15c>)
|
|
80196c2: 5cd3 ldrb r3, [r2, r3]
|
|
80196c4: 461a mov r2, r3
|
|
80196c6: f000 f93f bl 8019948 <dhcp_option_byte>
|
|
80196ca: 4603 mov r3, r0
|
|
80196cc: 81bb strh r3, [r7, #12]
|
|
for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) {
|
|
80196ce: 7fbb ldrb r3, [r7, #30]
|
|
80196d0: 3301 adds r3, #1
|
|
80196d2: 77bb strb r3, [r7, #30]
|
|
80196d4: 7fbb ldrb r3, [r7, #30]
|
|
80196d6: 2b02 cmp r3, #2
|
|
80196d8: d9ed bls.n 80196b6 <dhcp_reboot+0xaa>
|
|
#if LWIP_NETIF_HOSTNAME
|
|
options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif);
|
|
#endif /* LWIP_NETIF_HOSTNAME */
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
80196da: 89b8 ldrh r0, [r7, #12]
|
|
80196dc: 693b ldr r3, [r7, #16]
|
|
80196de: 33f0 adds r3, #240 ; 0xf0
|
|
80196e0: 697a ldr r2, [r7, #20]
|
|
80196e2: 4619 mov r1, r3
|
|
80196e4: f000 fe42 bl 801a36c <dhcp_option_trailer>
|
|
|
|
/* broadcast to server */
|
|
result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif);
|
|
80196e8: 4b20 ldr r3, [pc, #128] ; (801976c <dhcp_reboot+0x160>)
|
|
80196ea: 6818 ldr r0, [r3, #0]
|
|
80196ec: 687b ldr r3, [r7, #4]
|
|
80196ee: 9300 str r3, [sp, #0]
|
|
80196f0: 2343 movs r3, #67 ; 0x43
|
|
80196f2: 4a1f ldr r2, [pc, #124] ; (8019770 <dhcp_reboot+0x164>)
|
|
80196f4: 6979 ldr r1, [r7, #20]
|
|
80196f6: f7fe fcef bl 80180d8 <udp_sendto_if>
|
|
80196fa: 4603 mov r3, r0
|
|
80196fc: 77fb strb r3, [r7, #31]
|
|
pbuf_free(p_out);
|
|
80196fe: 6978 ldr r0, [r7, #20]
|
|
8019700: f7f8 fdaa bl 8012258 <pbuf_free>
|
|
8019704: e001 b.n 801970a <dhcp_reboot+0xfe>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n"));
|
|
result = ERR_MEM;
|
|
8019706: 23ff movs r3, #255 ; 0xff
|
|
8019708: 77fb strb r3, [r7, #31]
|
|
}
|
|
if (dhcp->tries < 255) {
|
|
801970a: 69bb ldr r3, [r7, #24]
|
|
801970c: 799b ldrb r3, [r3, #6]
|
|
801970e: 2bff cmp r3, #255 ; 0xff
|
|
8019710: d005 beq.n 801971e <dhcp_reboot+0x112>
|
|
dhcp->tries++;
|
|
8019712: 69bb ldr r3, [r7, #24]
|
|
8019714: 799b ldrb r3, [r3, #6]
|
|
8019716: 3301 adds r3, #1
|
|
8019718: b2da uxtb r2, r3
|
|
801971a: 69bb ldr r3, [r7, #24]
|
|
801971c: 719a strb r2, [r3, #6]
|
|
}
|
|
msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000);
|
|
801971e: 69bb ldr r3, [r7, #24]
|
|
8019720: 799b ldrb r3, [r3, #6]
|
|
8019722: 2b09 cmp r3, #9
|
|
8019724: d80a bhi.n 801973c <dhcp_reboot+0x130>
|
|
8019726: 69bb ldr r3, [r7, #24]
|
|
8019728: 799b ldrb r3, [r3, #6]
|
|
801972a: b29b uxth r3, r3
|
|
801972c: 461a mov r2, r3
|
|
801972e: 0152 lsls r2, r2, #5
|
|
8019730: 1ad2 subs r2, r2, r3
|
|
8019732: 0092 lsls r2, r2, #2
|
|
8019734: 4413 add r3, r2
|
|
8019736: 00db lsls r3, r3, #3
|
|
8019738: b29b uxth r3, r3
|
|
801973a: e001 b.n 8019740 <dhcp_reboot+0x134>
|
|
801973c: f242 7310 movw r3, #10000 ; 0x2710
|
|
8019740: 81fb strh r3, [r7, #14]
|
|
dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS);
|
|
8019742: 89fb ldrh r3, [r7, #14]
|
|
8019744: f203 13f3 addw r3, r3, #499 ; 0x1f3
|
|
8019748: 4a0a ldr r2, [pc, #40] ; (8019774 <dhcp_reboot+0x168>)
|
|
801974a: fb82 1203 smull r1, r2, r2, r3
|
|
801974e: 1152 asrs r2, r2, #5
|
|
8019750: 17db asrs r3, r3, #31
|
|
8019752: 1ad3 subs r3, r2, r3
|
|
8019754: b29a uxth r2, r3
|
|
8019756: 69bb ldr r3, [r7, #24]
|
|
8019758: 811a strh r2, [r3, #8]
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs));
|
|
return result;
|
|
801975a: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
801975e: 4618 mov r0, r3
|
|
8019760: 3720 adds r7, #32
|
|
8019762: 46bd mov sp, r7
|
|
8019764: bdb0 pop {r4, r5, r7, pc}
|
|
8019766: bf00 nop
|
|
8019768: 20000080 .word 0x20000080
|
|
801976c: 2000876c .word 0x2000876c
|
|
8019770: 08022e6c .word 0x08022e6c
|
|
8019774: 10624dd3 .word 0x10624dd3
|
|
|
|
08019778 <dhcp_release_and_stop>:
|
|
*
|
|
* @param netif network interface
|
|
*/
|
|
void
|
|
dhcp_release_and_stop(struct netif *netif)
|
|
{
|
|
8019778: b5b0 push {r4, r5, r7, lr}
|
|
801977a: b08a sub sp, #40 ; 0x28
|
|
801977c: af02 add r7, sp, #8
|
|
801977e: 6078 str r0, [r7, #4]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
8019780: 687b ldr r3, [r7, #4]
|
|
8019782: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
8019784: 61fb str r3, [r7, #28]
|
|
ip_addr_t server_ip_addr;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n"));
|
|
if (dhcp == NULL) {
|
|
8019786: 69fb ldr r3, [r7, #28]
|
|
8019788: 2b00 cmp r3, #0
|
|
801978a: f000 8084 beq.w 8019896 <dhcp_release_and_stop+0x11e>
|
|
return;
|
|
}
|
|
|
|
/* already off? -> nothing to do */
|
|
if (dhcp->state == DHCP_STATE_OFF) {
|
|
801978e: 69fb ldr r3, [r7, #28]
|
|
8019790: 795b ldrb r3, [r3, #5]
|
|
8019792: 2b00 cmp r3, #0
|
|
8019794: f000 8081 beq.w 801989a <dhcp_release_and_stop+0x122>
|
|
return;
|
|
}
|
|
|
|
ip_addr_copy(server_ip_addr, dhcp->server_ip_addr);
|
|
8019798: 69fb ldr r3, [r7, #28]
|
|
801979a: 699b ldr r3, [r3, #24]
|
|
801979c: 613b str r3, [r7, #16]
|
|
|
|
/* clean old DHCP offer */
|
|
ip_addr_set_zero_ip4(&dhcp->server_ip_addr);
|
|
801979e: 69fb ldr r3, [r7, #28]
|
|
80197a0: 2200 movs r2, #0
|
|
80197a2: 619a str r2, [r3, #24]
|
|
ip4_addr_set_zero(&dhcp->offered_ip_addr);
|
|
80197a4: 69fb ldr r3, [r7, #28]
|
|
80197a6: 2200 movs r2, #0
|
|
80197a8: 61da str r2, [r3, #28]
|
|
ip4_addr_set_zero(&dhcp->offered_sn_mask);
|
|
80197aa: 69fb ldr r3, [r7, #28]
|
|
80197ac: 2200 movs r2, #0
|
|
80197ae: 621a str r2, [r3, #32]
|
|
ip4_addr_set_zero(&dhcp->offered_gw_addr);
|
|
80197b0: 69fb ldr r3, [r7, #28]
|
|
80197b2: 2200 movs r2, #0
|
|
80197b4: 625a str r2, [r3, #36] ; 0x24
|
|
#if LWIP_DHCP_BOOTP_FILE
|
|
ip4_addr_set_zero(&dhcp->offered_si_addr);
|
|
#endif /* LWIP_DHCP_BOOTP_FILE */
|
|
dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0;
|
|
80197b6: 69fb ldr r3, [r7, #28]
|
|
80197b8: 2200 movs r2, #0
|
|
80197ba: 631a str r2, [r3, #48] ; 0x30
|
|
80197bc: 69fb ldr r3, [r7, #28]
|
|
80197be: 6b1a ldr r2, [r3, #48] ; 0x30
|
|
80197c0: 69fb ldr r3, [r7, #28]
|
|
80197c2: 62da str r2, [r3, #44] ; 0x2c
|
|
80197c4: 69fb ldr r3, [r7, #28]
|
|
80197c6: 6ada ldr r2, [r3, #44] ; 0x2c
|
|
80197c8: 69fb ldr r3, [r7, #28]
|
|
80197ca: 629a str r2, [r3, #40] ; 0x28
|
|
dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0;
|
|
80197cc: 69fb ldr r3, [r7, #28]
|
|
80197ce: 2200 movs r2, #0
|
|
80197d0: 829a strh r2, [r3, #20]
|
|
80197d2: 69fb ldr r3, [r7, #28]
|
|
80197d4: 8a9a ldrh r2, [r3, #20]
|
|
80197d6: 69fb ldr r3, [r7, #28]
|
|
80197d8: 825a strh r2, [r3, #18]
|
|
80197da: 69fb ldr r3, [r7, #28]
|
|
80197dc: 8a5a ldrh r2, [r3, #18]
|
|
80197de: 69fb ldr r3, [r7, #28]
|
|
80197e0: 821a strh r2, [r3, #16]
|
|
80197e2: 69fb ldr r3, [r7, #28]
|
|
80197e4: 8a1a ldrh r2, [r3, #16]
|
|
80197e6: 69fb ldr r3, [r7, #28]
|
|
80197e8: 81da strh r2, [r3, #14]
|
|
|
|
/* send release message when current IP was assigned via DHCP */
|
|
if (dhcp_supplied_address(netif)) {
|
|
80197ea: 6878 ldr r0, [r7, #4]
|
|
80197ec: f000 fdec bl 801a3c8 <dhcp_supplied_address>
|
|
80197f0: 4603 mov r3, r0
|
|
80197f2: 2b00 cmp r3, #0
|
|
80197f4: d03b beq.n 801986e <dhcp_release_and_stop+0xf6>
|
|
/* create and initialize the DHCP message header */
|
|
struct pbuf *p_out;
|
|
u16_t options_out_len;
|
|
p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len);
|
|
80197f6: f107 030e add.w r3, r7, #14
|
|
80197fa: 2207 movs r2, #7
|
|
80197fc: 69f9 ldr r1, [r7, #28]
|
|
80197fe: 6878 ldr r0, [r7, #4]
|
|
8019800: f000 fcde bl 801a1c0 <dhcp_create_msg>
|
|
8019804: 61b8 str r0, [r7, #24]
|
|
if (p_out != NULL) {
|
|
8019806: 69bb ldr r3, [r7, #24]
|
|
8019808: 2b00 cmp r3, #0
|
|
801980a: d030 beq.n 801986e <dhcp_release_and_stop+0xf6>
|
|
struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload;
|
|
801980c: 69bb ldr r3, [r7, #24]
|
|
801980e: 685b ldr r3, [r3, #4]
|
|
8019810: 617b str r3, [r7, #20]
|
|
options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4);
|
|
8019812: 89f8 ldrh r0, [r7, #14]
|
|
8019814: 697b ldr r3, [r7, #20]
|
|
8019816: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801981a: 2304 movs r3, #4
|
|
801981c: 2236 movs r2, #54 ; 0x36
|
|
801981e: f000 f85f bl 80198e0 <dhcp_option>
|
|
8019822: 4603 mov r3, r0
|
|
8019824: 81fb strh r3, [r7, #14]
|
|
options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr))));
|
|
8019826: 89fc ldrh r4, [r7, #14]
|
|
8019828: 697b ldr r3, [r7, #20]
|
|
801982a: f103 05f0 add.w r5, r3, #240 ; 0xf0
|
|
801982e: 693b ldr r3, [r7, #16]
|
|
8019830: 4618 mov r0, r3
|
|
8019832: f7f7 f972 bl 8010b1a <lwip_htonl>
|
|
8019836: 4603 mov r3, r0
|
|
8019838: 461a mov r2, r3
|
|
801983a: 4629 mov r1, r5
|
|
801983c: 4620 mov r0, r4
|
|
801983e: f000 f8db bl 80199f8 <dhcp_option_long>
|
|
8019842: 4603 mov r3, r0
|
|
8019844: 81fb strh r3, [r7, #14]
|
|
|
|
LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len);
|
|
dhcp_option_trailer(options_out_len, msg_out->options, p_out);
|
|
8019846: 89f8 ldrh r0, [r7, #14]
|
|
8019848: 697b ldr r3, [r7, #20]
|
|
801984a: 33f0 adds r3, #240 ; 0xf0
|
|
801984c: 69ba ldr r2, [r7, #24]
|
|
801984e: 4619 mov r1, r3
|
|
8019850: f000 fd8c bl 801a36c <dhcp_option_trailer>
|
|
|
|
udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif);
|
|
8019854: 4b13 ldr r3, [pc, #76] ; (80198a4 <dhcp_release_and_stop+0x12c>)
|
|
8019856: 6818 ldr r0, [r3, #0]
|
|
8019858: f107 0210 add.w r2, r7, #16
|
|
801985c: 687b ldr r3, [r7, #4]
|
|
801985e: 9300 str r3, [sp, #0]
|
|
8019860: 2343 movs r3, #67 ; 0x43
|
|
8019862: 69b9 ldr r1, [r7, #24]
|
|
8019864: f7fe fc38 bl 80180d8 <udp_sendto_if>
|
|
pbuf_free(p_out);
|
|
8019868: 69b8 ldr r0, [r7, #24]
|
|
801986a: f7f8 fcf5 bl 8012258 <pbuf_free>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n"));
|
|
}
|
|
}
|
|
|
|
/* remove IP address from interface (prevents routing from selecting this interface) */
|
|
netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4);
|
|
801986e: 4b0e ldr r3, [pc, #56] ; (80198a8 <dhcp_release_and_stop+0x130>)
|
|
8019870: 4a0d ldr r2, [pc, #52] ; (80198a8 <dhcp_release_and_stop+0x130>)
|
|
8019872: 490d ldr r1, [pc, #52] ; (80198a8 <dhcp_release_and_stop+0x130>)
|
|
8019874: 6878 ldr r0, [r7, #4]
|
|
8019876: f7f7 ffe5 bl 8011844 <netif_set_addr>
|
|
autoip_stop(netif);
|
|
dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF;
|
|
}
|
|
#endif /* LWIP_DHCP_AUTOIP_COOP */
|
|
|
|
dhcp_set_state(dhcp, DHCP_STATE_OFF);
|
|
801987a: 2100 movs r1, #0
|
|
801987c: 69f8 ldr r0, [r7, #28]
|
|
801987e: f000 f815 bl 80198ac <dhcp_set_state>
|
|
|
|
if (dhcp->pcb_allocated != 0) {
|
|
8019882: 69fb ldr r3, [r7, #28]
|
|
8019884: 791b ldrb r3, [r3, #4]
|
|
8019886: 2b00 cmp r3, #0
|
|
8019888: d008 beq.n 801989c <dhcp_release_and_stop+0x124>
|
|
dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */
|
|
801988a: f7fe ff71 bl 8018770 <dhcp_dec_pcb_refcount>
|
|
dhcp->pcb_allocated = 0;
|
|
801988e: 69fb ldr r3, [r7, #28]
|
|
8019890: 2200 movs r2, #0
|
|
8019892: 711a strb r2, [r3, #4]
|
|
8019894: e002 b.n 801989c <dhcp_release_and_stop+0x124>
|
|
return;
|
|
8019896: bf00 nop
|
|
8019898: e000 b.n 801989c <dhcp_release_and_stop+0x124>
|
|
return;
|
|
801989a: bf00 nop
|
|
}
|
|
}
|
|
801989c: 3720 adds r7, #32
|
|
801989e: 46bd mov sp, r7
|
|
80198a0: bdb0 pop {r4, r5, r7, pc}
|
|
80198a2: bf00 nop
|
|
80198a4: 2000876c .word 0x2000876c
|
|
80198a8: 08022e68 .word 0x08022e68
|
|
|
|
080198ac <dhcp_set_state>:
|
|
*
|
|
* If the state changed, reset the number of tries.
|
|
*/
|
|
static void
|
|
dhcp_set_state(struct dhcp *dhcp, u8_t new_state)
|
|
{
|
|
80198ac: b480 push {r7}
|
|
80198ae: b083 sub sp, #12
|
|
80198b0: af00 add r7, sp, #0
|
|
80198b2: 6078 str r0, [r7, #4]
|
|
80198b4: 460b mov r3, r1
|
|
80198b6: 70fb strb r3, [r7, #3]
|
|
if (new_state != dhcp->state) {
|
|
80198b8: 687b ldr r3, [r7, #4]
|
|
80198ba: 795b ldrb r3, [r3, #5]
|
|
80198bc: 78fa ldrb r2, [r7, #3]
|
|
80198be: 429a cmp r2, r3
|
|
80198c0: d008 beq.n 80198d4 <dhcp_set_state+0x28>
|
|
dhcp->state = new_state;
|
|
80198c2: 687b ldr r3, [r7, #4]
|
|
80198c4: 78fa ldrb r2, [r7, #3]
|
|
80198c6: 715a strb r2, [r3, #5]
|
|
dhcp->tries = 0;
|
|
80198c8: 687b ldr r3, [r7, #4]
|
|
80198ca: 2200 movs r2, #0
|
|
80198cc: 719a strb r2, [r3, #6]
|
|
dhcp->request_timeout = 0;
|
|
80198ce: 687b ldr r3, [r7, #4]
|
|
80198d0: 2200 movs r2, #0
|
|
80198d2: 811a strh r2, [r3, #8]
|
|
}
|
|
}
|
|
80198d4: bf00 nop
|
|
80198d6: 370c adds r7, #12
|
|
80198d8: 46bd mov sp, r7
|
|
80198da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80198de: 4770 bx lr
|
|
|
|
080198e0 <dhcp_option>:
|
|
* DHCP message.
|
|
*
|
|
*/
|
|
static u16_t
|
|
dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len)
|
|
{
|
|
80198e0: b580 push {r7, lr}
|
|
80198e2: b082 sub sp, #8
|
|
80198e4: af00 add r7, sp, #0
|
|
80198e6: 6039 str r1, [r7, #0]
|
|
80198e8: 4611 mov r1, r2
|
|
80198ea: 461a mov r2, r3
|
|
80198ec: 4603 mov r3, r0
|
|
80198ee: 80fb strh r3, [r7, #6]
|
|
80198f0: 460b mov r3, r1
|
|
80198f2: 717b strb r3, [r7, #5]
|
|
80198f4: 4613 mov r3, r2
|
|
80198f6: 713b strb r3, [r7, #4]
|
|
LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN);
|
|
80198f8: 88fa ldrh r2, [r7, #6]
|
|
80198fa: 793b ldrb r3, [r7, #4]
|
|
80198fc: 4413 add r3, r2
|
|
80198fe: 3302 adds r3, #2
|
|
8019900: 2b44 cmp r3, #68 ; 0x44
|
|
8019902: d906 bls.n 8019912 <dhcp_option+0x32>
|
|
8019904: 4b0d ldr r3, [pc, #52] ; (801993c <dhcp_option+0x5c>)
|
|
8019906: f240 529a movw r2, #1434 ; 0x59a
|
|
801990a: 490d ldr r1, [pc, #52] ; (8019940 <dhcp_option+0x60>)
|
|
801990c: 480d ldr r0, [pc, #52] ; (8019944 <dhcp_option+0x64>)
|
|
801990e: f003 f9d3 bl 801ccb8 <iprintf>
|
|
options[options_out_len++] = option_type;
|
|
8019912: 88fb ldrh r3, [r7, #6]
|
|
8019914: 1c5a adds r2, r3, #1
|
|
8019916: 80fa strh r2, [r7, #6]
|
|
8019918: 461a mov r2, r3
|
|
801991a: 683b ldr r3, [r7, #0]
|
|
801991c: 4413 add r3, r2
|
|
801991e: 797a ldrb r2, [r7, #5]
|
|
8019920: 701a strb r2, [r3, #0]
|
|
options[options_out_len++] = option_len;
|
|
8019922: 88fb ldrh r3, [r7, #6]
|
|
8019924: 1c5a adds r2, r3, #1
|
|
8019926: 80fa strh r2, [r7, #6]
|
|
8019928: 461a mov r2, r3
|
|
801992a: 683b ldr r3, [r7, #0]
|
|
801992c: 4413 add r3, r2
|
|
801992e: 793a ldrb r2, [r7, #4]
|
|
8019930: 701a strb r2, [r3, #0]
|
|
return options_out_len;
|
|
8019932: 88fb ldrh r3, [r7, #6]
|
|
}
|
|
8019934: 4618 mov r0, r3
|
|
8019936: 3708 adds r7, #8
|
|
8019938: 46bd mov sp, r7
|
|
801993a: bd80 pop {r7, pc}
|
|
801993c: 08020398 .word 0x08020398
|
|
8019940: 0802052c .word 0x0802052c
|
|
8019944: 080203f8 .word 0x080203f8
|
|
|
|
08019948 <dhcp_option_byte>:
|
|
* Concatenate a single byte to the outgoing DHCP message.
|
|
*
|
|
*/
|
|
static u16_t
|
|
dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value)
|
|
{
|
|
8019948: b580 push {r7, lr}
|
|
801994a: b082 sub sp, #8
|
|
801994c: af00 add r7, sp, #0
|
|
801994e: 4603 mov r3, r0
|
|
8019950: 6039 str r1, [r7, #0]
|
|
8019952: 80fb strh r3, [r7, #6]
|
|
8019954: 4613 mov r3, r2
|
|
8019956: 717b strb r3, [r7, #5]
|
|
LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN);
|
|
8019958: 88fb ldrh r3, [r7, #6]
|
|
801995a: 2b43 cmp r3, #67 ; 0x43
|
|
801995c: d906 bls.n 801996c <dhcp_option_byte+0x24>
|
|
801995e: 4b0a ldr r3, [pc, #40] ; (8019988 <dhcp_option_byte+0x40>)
|
|
8019960: f240 52a6 movw r2, #1446 ; 0x5a6
|
|
8019964: 4909 ldr r1, [pc, #36] ; (801998c <dhcp_option_byte+0x44>)
|
|
8019966: 480a ldr r0, [pc, #40] ; (8019990 <dhcp_option_byte+0x48>)
|
|
8019968: f003 f9a6 bl 801ccb8 <iprintf>
|
|
options[options_out_len++] = value;
|
|
801996c: 88fb ldrh r3, [r7, #6]
|
|
801996e: 1c5a adds r2, r3, #1
|
|
8019970: 80fa strh r2, [r7, #6]
|
|
8019972: 461a mov r2, r3
|
|
8019974: 683b ldr r3, [r7, #0]
|
|
8019976: 4413 add r3, r2
|
|
8019978: 797a ldrb r2, [r7, #5]
|
|
801997a: 701a strb r2, [r3, #0]
|
|
return options_out_len;
|
|
801997c: 88fb ldrh r3, [r7, #6]
|
|
}
|
|
801997e: 4618 mov r0, r3
|
|
8019980: 3708 adds r7, #8
|
|
8019982: 46bd mov sp, r7
|
|
8019984: bd80 pop {r7, pc}
|
|
8019986: bf00 nop
|
|
8019988: 08020398 .word 0x08020398
|
|
801998c: 08020570 .word 0x08020570
|
|
8019990: 080203f8 .word 0x080203f8
|
|
|
|
08019994 <dhcp_option_short>:
|
|
|
|
static u16_t
|
|
dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value)
|
|
{
|
|
8019994: b580 push {r7, lr}
|
|
8019996: b082 sub sp, #8
|
|
8019998: af00 add r7, sp, #0
|
|
801999a: 4603 mov r3, r0
|
|
801999c: 6039 str r1, [r7, #0]
|
|
801999e: 80fb strh r3, [r7, #6]
|
|
80199a0: 4613 mov r3, r2
|
|
80199a2: 80bb strh r3, [r7, #4]
|
|
LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN);
|
|
80199a4: 88fb ldrh r3, [r7, #6]
|
|
80199a6: 3302 adds r3, #2
|
|
80199a8: 2b44 cmp r3, #68 ; 0x44
|
|
80199aa: d906 bls.n 80199ba <dhcp_option_short+0x26>
|
|
80199ac: 4b0f ldr r3, [pc, #60] ; (80199ec <dhcp_option_short+0x58>)
|
|
80199ae: f240 52ae movw r2, #1454 ; 0x5ae
|
|
80199b2: 490f ldr r1, [pc, #60] ; (80199f0 <dhcp_option_short+0x5c>)
|
|
80199b4: 480f ldr r0, [pc, #60] ; (80199f4 <dhcp_option_short+0x60>)
|
|
80199b6: f003 f97f bl 801ccb8 <iprintf>
|
|
options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8);
|
|
80199ba: 88bb ldrh r3, [r7, #4]
|
|
80199bc: 0a1b lsrs r3, r3, #8
|
|
80199be: b29a uxth r2, r3
|
|
80199c0: 88fb ldrh r3, [r7, #6]
|
|
80199c2: 1c59 adds r1, r3, #1
|
|
80199c4: 80f9 strh r1, [r7, #6]
|
|
80199c6: 4619 mov r1, r3
|
|
80199c8: 683b ldr r3, [r7, #0]
|
|
80199ca: 440b add r3, r1
|
|
80199cc: b2d2 uxtb r2, r2
|
|
80199ce: 701a strb r2, [r3, #0]
|
|
options[options_out_len++] = (u8_t) (value & 0x00ffU);
|
|
80199d0: 88fb ldrh r3, [r7, #6]
|
|
80199d2: 1c5a adds r2, r3, #1
|
|
80199d4: 80fa strh r2, [r7, #6]
|
|
80199d6: 461a mov r2, r3
|
|
80199d8: 683b ldr r3, [r7, #0]
|
|
80199da: 4413 add r3, r2
|
|
80199dc: 88ba ldrh r2, [r7, #4]
|
|
80199de: b2d2 uxtb r2, r2
|
|
80199e0: 701a strb r2, [r3, #0]
|
|
return options_out_len;
|
|
80199e2: 88fb ldrh r3, [r7, #6]
|
|
}
|
|
80199e4: 4618 mov r0, r3
|
|
80199e6: 3708 adds r7, #8
|
|
80199e8: 46bd mov sp, r7
|
|
80199ea: bd80 pop {r7, pc}
|
|
80199ec: 08020398 .word 0x08020398
|
|
80199f0: 080205a8 .word 0x080205a8
|
|
80199f4: 080203f8 .word 0x080203f8
|
|
|
|
080199f8 <dhcp_option_long>:
|
|
|
|
static u16_t
|
|
dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value)
|
|
{
|
|
80199f8: b580 push {r7, lr}
|
|
80199fa: b084 sub sp, #16
|
|
80199fc: af00 add r7, sp, #0
|
|
80199fe: 4603 mov r3, r0
|
|
8019a00: 60b9 str r1, [r7, #8]
|
|
8019a02: 607a str r2, [r7, #4]
|
|
8019a04: 81fb strh r3, [r7, #14]
|
|
LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN);
|
|
8019a06: 89fb ldrh r3, [r7, #14]
|
|
8019a08: 3304 adds r3, #4
|
|
8019a0a: 2b44 cmp r3, #68 ; 0x44
|
|
8019a0c: d906 bls.n 8019a1c <dhcp_option_long+0x24>
|
|
8019a0e: 4b19 ldr r3, [pc, #100] ; (8019a74 <dhcp_option_long+0x7c>)
|
|
8019a10: f240 52b7 movw r2, #1463 ; 0x5b7
|
|
8019a14: 4918 ldr r1, [pc, #96] ; (8019a78 <dhcp_option_long+0x80>)
|
|
8019a16: 4819 ldr r0, [pc, #100] ; (8019a7c <dhcp_option_long+0x84>)
|
|
8019a18: f003 f94e bl 801ccb8 <iprintf>
|
|
options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24);
|
|
8019a1c: 687b ldr r3, [r7, #4]
|
|
8019a1e: 0e1a lsrs r2, r3, #24
|
|
8019a20: 89fb ldrh r3, [r7, #14]
|
|
8019a22: 1c59 adds r1, r3, #1
|
|
8019a24: 81f9 strh r1, [r7, #14]
|
|
8019a26: 4619 mov r1, r3
|
|
8019a28: 68bb ldr r3, [r7, #8]
|
|
8019a2a: 440b add r3, r1
|
|
8019a2c: b2d2 uxtb r2, r2
|
|
8019a2e: 701a strb r2, [r3, #0]
|
|
options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16);
|
|
8019a30: 687b ldr r3, [r7, #4]
|
|
8019a32: 0c1a lsrs r2, r3, #16
|
|
8019a34: 89fb ldrh r3, [r7, #14]
|
|
8019a36: 1c59 adds r1, r3, #1
|
|
8019a38: 81f9 strh r1, [r7, #14]
|
|
8019a3a: 4619 mov r1, r3
|
|
8019a3c: 68bb ldr r3, [r7, #8]
|
|
8019a3e: 440b add r3, r1
|
|
8019a40: b2d2 uxtb r2, r2
|
|
8019a42: 701a strb r2, [r3, #0]
|
|
options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8);
|
|
8019a44: 687b ldr r3, [r7, #4]
|
|
8019a46: 0a1a lsrs r2, r3, #8
|
|
8019a48: 89fb ldrh r3, [r7, #14]
|
|
8019a4a: 1c59 adds r1, r3, #1
|
|
8019a4c: 81f9 strh r1, [r7, #14]
|
|
8019a4e: 4619 mov r1, r3
|
|
8019a50: 68bb ldr r3, [r7, #8]
|
|
8019a52: 440b add r3, r1
|
|
8019a54: b2d2 uxtb r2, r2
|
|
8019a56: 701a strb r2, [r3, #0]
|
|
options[options_out_len++] = (u8_t)((value & 0x000000ffUL));
|
|
8019a58: 89fb ldrh r3, [r7, #14]
|
|
8019a5a: 1c5a adds r2, r3, #1
|
|
8019a5c: 81fa strh r2, [r7, #14]
|
|
8019a5e: 461a mov r2, r3
|
|
8019a60: 68bb ldr r3, [r7, #8]
|
|
8019a62: 4413 add r3, r2
|
|
8019a64: 687a ldr r2, [r7, #4]
|
|
8019a66: b2d2 uxtb r2, r2
|
|
8019a68: 701a strb r2, [r3, #0]
|
|
return options_out_len;
|
|
8019a6a: 89fb ldrh r3, [r7, #14]
|
|
}
|
|
8019a6c: 4618 mov r0, r3
|
|
8019a6e: 3710 adds r7, #16
|
|
8019a70: 46bd mov sp, r7
|
|
8019a72: bd80 pop {r7, pc}
|
|
8019a74: 08020398 .word 0x08020398
|
|
8019a78: 080205e4 .word 0x080205e4
|
|
8019a7c: 080203f8 .word 0x080203f8
|
|
|
|
08019a80 <dhcp_parse_reply>:
|
|
* use that further on.
|
|
*
|
|
*/
|
|
static err_t
|
|
dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp)
|
|
{
|
|
8019a80: b580 push {r7, lr}
|
|
8019a82: b090 sub sp, #64 ; 0x40
|
|
8019a84: af00 add r7, sp, #0
|
|
8019a86: 6078 str r0, [r7, #4]
|
|
8019a88: 6039 str r1, [r7, #0]
|
|
u16_t offset;
|
|
u16_t offset_max;
|
|
u16_t options_idx;
|
|
u16_t options_idx_max;
|
|
struct pbuf *q;
|
|
int parse_file_as_options = 0;
|
|
8019a8a: 2300 movs r3, #0
|
|
8019a8c: 62fb str r3, [r7, #44] ; 0x2c
|
|
int parse_sname_as_options = 0;
|
|
8019a8e: 2300 movs r3, #0
|
|
8019a90: 62bb str r3, [r7, #40] ; 0x28
|
|
#endif
|
|
|
|
LWIP_UNUSED_ARG(dhcp);
|
|
|
|
/* clear received options */
|
|
dhcp_clear_all_options(dhcp);
|
|
8019a92: 2208 movs r2, #8
|
|
8019a94: 2100 movs r1, #0
|
|
8019a96: 48be ldr r0, [pc, #760] ; (8019d90 <dhcp_parse_reply+0x310>)
|
|
8019a98: f003 f905 bl 801cca6 <memset>
|
|
/* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */
|
|
if (p->len < DHCP_SNAME_OFS) {
|
|
8019a9c: 687b ldr r3, [r7, #4]
|
|
8019a9e: 895b ldrh r3, [r3, #10]
|
|
8019aa0: 2b2b cmp r3, #43 ; 0x2b
|
|
8019aa2: d802 bhi.n 8019aaa <dhcp_parse_reply+0x2a>
|
|
return ERR_BUF;
|
|
8019aa4: f06f 0301 mvn.w r3, #1
|
|
8019aa8: e2a8 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
msg_in = (struct dhcp_msg *)p->payload;
|
|
8019aaa: 687b ldr r3, [r7, #4]
|
|
8019aac: 685b ldr r3, [r3, #4]
|
|
8019aae: 61bb str r3, [r7, #24]
|
|
#endif /* LWIP_DHCP_BOOTP_FILE */
|
|
|
|
/* parse options */
|
|
|
|
/* start with options field */
|
|
options_idx = DHCP_OPTIONS_OFS;
|
|
8019ab0: 23f0 movs r3, #240 ; 0xf0
|
|
8019ab2: 86fb strh r3, [r7, #54] ; 0x36
|
|
/* parse options to the end of the received packet */
|
|
options_idx_max = p->tot_len;
|
|
8019ab4: 687b ldr r3, [r7, #4]
|
|
8019ab6: 891b ldrh r3, [r3, #8]
|
|
8019ab8: 86bb strh r3, [r7, #52] ; 0x34
|
|
again:
|
|
q = p;
|
|
8019aba: 687b ldr r3, [r7, #4]
|
|
8019abc: 633b str r3, [r7, #48] ; 0x30
|
|
while ((q != NULL) && (options_idx >= q->len)) {
|
|
8019abe: e00c b.n 8019ada <dhcp_parse_reply+0x5a>
|
|
options_idx = (u16_t)(options_idx - q->len);
|
|
8019ac0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019ac2: 895b ldrh r3, [r3, #10]
|
|
8019ac4: 8efa ldrh r2, [r7, #54] ; 0x36
|
|
8019ac6: 1ad3 subs r3, r2, r3
|
|
8019ac8: 86fb strh r3, [r7, #54] ; 0x36
|
|
options_idx_max = (u16_t)(options_idx_max - q->len);
|
|
8019aca: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019acc: 895b ldrh r3, [r3, #10]
|
|
8019ace: 8eba ldrh r2, [r7, #52] ; 0x34
|
|
8019ad0: 1ad3 subs r3, r2, r3
|
|
8019ad2: 86bb strh r3, [r7, #52] ; 0x34
|
|
q = q->next;
|
|
8019ad4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019ad6: 681b ldr r3, [r3, #0]
|
|
8019ad8: 633b str r3, [r7, #48] ; 0x30
|
|
while ((q != NULL) && (options_idx >= q->len)) {
|
|
8019ada: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019adc: 2b00 cmp r3, #0
|
|
8019ade: d004 beq.n 8019aea <dhcp_parse_reply+0x6a>
|
|
8019ae0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019ae2: 895b ldrh r3, [r3, #10]
|
|
8019ae4: 8efa ldrh r2, [r7, #54] ; 0x36
|
|
8019ae6: 429a cmp r2, r3
|
|
8019ae8: d2ea bcs.n 8019ac0 <dhcp_parse_reply+0x40>
|
|
}
|
|
if (q == NULL) {
|
|
8019aea: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019aec: 2b00 cmp r3, #0
|
|
8019aee: d102 bne.n 8019af6 <dhcp_parse_reply+0x76>
|
|
return ERR_BUF;
|
|
8019af0: f06f 0301 mvn.w r3, #1
|
|
8019af4: e282 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
offset = options_idx;
|
|
8019af6: 8efb ldrh r3, [r7, #54] ; 0x36
|
|
8019af8: 877b strh r3, [r7, #58] ; 0x3a
|
|
offset_max = options_idx_max;
|
|
8019afa: 8ebb ldrh r3, [r7, #52] ; 0x34
|
|
8019afc: 873b strh r3, [r7, #56] ; 0x38
|
|
options = (u8_t *)q->payload;
|
|
8019afe: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019b00: 685b ldr r3, [r3, #4]
|
|
8019b02: 63fb str r3, [r7, #60] ; 0x3c
|
|
/* at least 1 byte to read and no end marker, then at least 3 bytes to read? */
|
|
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
|
|
8019b04: e23a b.n 8019f7c <dhcp_parse_reply+0x4fc>
|
|
u8_t op = options[offset];
|
|
8019b06: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019b08: 6bfa ldr r2, [r7, #60] ; 0x3c
|
|
8019b0a: 4413 add r3, r2
|
|
8019b0c: 781b ldrb r3, [r3, #0]
|
|
8019b0e: 75fb strb r3, [r7, #23]
|
|
u8_t len;
|
|
u8_t decode_len = 0;
|
|
8019b10: 2300 movs r3, #0
|
|
8019b12: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
int decode_idx = -1;
|
|
8019b16: f04f 33ff mov.w r3, #4294967295
|
|
8019b1a: 623b str r3, [r7, #32]
|
|
u16_t val_offset = (u16_t)(offset + 2);
|
|
8019b1c: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019b1e: 3302 adds r3, #2
|
|
8019b20: 83fb strh r3, [r7, #30]
|
|
if (val_offset < offset) {
|
|
8019b22: 8bfa ldrh r2, [r7, #30]
|
|
8019b24: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019b26: 429a cmp r2, r3
|
|
8019b28: d202 bcs.n 8019b30 <dhcp_parse_reply+0xb0>
|
|
/* overflow */
|
|
return ERR_BUF;
|
|
8019b2a: f06f 0301 mvn.w r3, #1
|
|
8019b2e: e265 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
/* len byte might be in the next pbuf */
|
|
if ((offset + 1) < q->len) {
|
|
8019b30: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019b32: 3301 adds r3, #1
|
|
8019b34: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
8019b36: 8952 ldrh r2, [r2, #10]
|
|
8019b38: 4293 cmp r3, r2
|
|
8019b3a: da07 bge.n 8019b4c <dhcp_parse_reply+0xcc>
|
|
len = options[offset + 1];
|
|
8019b3c: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019b3e: 3301 adds r3, #1
|
|
8019b40: 6bfa ldr r2, [r7, #60] ; 0x3c
|
|
8019b42: 4413 add r3, r2
|
|
8019b44: 781b ldrb r3, [r3, #0]
|
|
8019b46: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8019b4a: e00b b.n 8019b64 <dhcp_parse_reply+0xe4>
|
|
} else {
|
|
len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0);
|
|
8019b4c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019b4e: 681b ldr r3, [r3, #0]
|
|
8019b50: 2b00 cmp r3, #0
|
|
8019b52: d004 beq.n 8019b5e <dhcp_parse_reply+0xde>
|
|
8019b54: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019b56: 681b ldr r3, [r3, #0]
|
|
8019b58: 685b ldr r3, [r3, #4]
|
|
8019b5a: 781b ldrb r3, [r3, #0]
|
|
8019b5c: e000 b.n 8019b60 <dhcp_parse_reply+0xe0>
|
|
8019b5e: 2300 movs r3, #0
|
|
8019b60: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
/* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */
|
|
decode_len = len;
|
|
8019b64: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019b68: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
switch (op) {
|
|
8019b6c: 7dfb ldrb r3, [r7, #23]
|
|
8019b6e: 2b3b cmp r3, #59 ; 0x3b
|
|
8019b70: f200 812d bhi.w 8019dce <dhcp_parse_reply+0x34e>
|
|
8019b74: a201 add r2, pc, #4 ; (adr r2, 8019b7c <dhcp_parse_reply+0xfc>)
|
|
8019b76: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8019b7a: bf00 nop
|
|
8019b7c: 08019c6d .word 0x08019c6d
|
|
8019b80: 08019c7d .word 0x08019c7d
|
|
8019b84: 08019dcf .word 0x08019dcf
|
|
8019b88: 08019c9f .word 0x08019c9f
|
|
8019b8c: 08019dcf .word 0x08019dcf
|
|
8019b90: 08019dcf .word 0x08019dcf
|
|
8019b94: 08019dcf .word 0x08019dcf
|
|
8019b98: 08019dcf .word 0x08019dcf
|
|
8019b9c: 08019dcf .word 0x08019dcf
|
|
8019ba0: 08019dcf .word 0x08019dcf
|
|
8019ba4: 08019dcf .word 0x08019dcf
|
|
8019ba8: 08019dcf .word 0x08019dcf
|
|
8019bac: 08019dcf .word 0x08019dcf
|
|
8019bb0: 08019dcf .word 0x08019dcf
|
|
8019bb4: 08019dcf .word 0x08019dcf
|
|
8019bb8: 08019dcf .word 0x08019dcf
|
|
8019bbc: 08019dcf .word 0x08019dcf
|
|
8019bc0: 08019dcf .word 0x08019dcf
|
|
8019bc4: 08019dcf .word 0x08019dcf
|
|
8019bc8: 08019dcf .word 0x08019dcf
|
|
8019bcc: 08019dcf .word 0x08019dcf
|
|
8019bd0: 08019dcf .word 0x08019dcf
|
|
8019bd4: 08019dcf .word 0x08019dcf
|
|
8019bd8: 08019dcf .word 0x08019dcf
|
|
8019bdc: 08019dcf .word 0x08019dcf
|
|
8019be0: 08019dcf .word 0x08019dcf
|
|
8019be4: 08019dcf .word 0x08019dcf
|
|
8019be8: 08019dcf .word 0x08019dcf
|
|
8019bec: 08019dcf .word 0x08019dcf
|
|
8019bf0: 08019dcf .word 0x08019dcf
|
|
8019bf4: 08019dcf .word 0x08019dcf
|
|
8019bf8: 08019dcf .word 0x08019dcf
|
|
8019bfc: 08019dcf .word 0x08019dcf
|
|
8019c00: 08019dcf .word 0x08019dcf
|
|
8019c04: 08019dcf .word 0x08019dcf
|
|
8019c08: 08019dcf .word 0x08019dcf
|
|
8019c0c: 08019dcf .word 0x08019dcf
|
|
8019c10: 08019dcf .word 0x08019dcf
|
|
8019c14: 08019dcf .word 0x08019dcf
|
|
8019c18: 08019dcf .word 0x08019dcf
|
|
8019c1c: 08019dcf .word 0x08019dcf
|
|
8019c20: 08019dcf .word 0x08019dcf
|
|
8019c24: 08019dcf .word 0x08019dcf
|
|
8019c28: 08019dcf .word 0x08019dcf
|
|
8019c2c: 08019dcf .word 0x08019dcf
|
|
8019c30: 08019dcf .word 0x08019dcf
|
|
8019c34: 08019dcf .word 0x08019dcf
|
|
8019c38: 08019dcf .word 0x08019dcf
|
|
8019c3c: 08019dcf .word 0x08019dcf
|
|
8019c40: 08019dcf .word 0x08019dcf
|
|
8019c44: 08019dcf .word 0x08019dcf
|
|
8019c48: 08019ccb .word 0x08019ccb
|
|
8019c4c: 08019ced .word 0x08019ced
|
|
8019c50: 08019d29 .word 0x08019d29
|
|
8019c54: 08019d4b .word 0x08019d4b
|
|
8019c58: 08019dcf .word 0x08019dcf
|
|
8019c5c: 08019dcf .word 0x08019dcf
|
|
8019c60: 08019dcf .word 0x08019dcf
|
|
8019c64: 08019d6d .word 0x08019d6d
|
|
8019c68: 08019dad .word 0x08019dad
|
|
/* case(DHCP_OPTION_END): handled above */
|
|
case (DHCP_OPTION_PAD):
|
|
/* special option: no len encoded */
|
|
decode_len = len = 0;
|
|
8019c6c: 2300 movs r3, #0
|
|
8019c6e: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
8019c72: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019c76: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
/* will be increased below */
|
|
break;
|
|
8019c7a: e0ac b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
case (DHCP_OPTION_SUBNET_MASK):
|
|
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
|
|
8019c7c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019c80: 2b04 cmp r3, #4
|
|
8019c82: d009 beq.n 8019c98 <dhcp_parse_reply+0x218>
|
|
8019c84: 4b43 ldr r3, [pc, #268] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019c86: f240 622e movw r2, #1582 ; 0x62e
|
|
8019c8a: 4943 ldr r1, [pc, #268] ; (8019d98 <dhcp_parse_reply+0x318>)
|
|
8019c8c: 4843 ldr r0, [pc, #268] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019c8e: f003 f813 bl 801ccb8 <iprintf>
|
|
8019c92: f06f 0305 mvn.w r3, #5
|
|
8019c96: e1b1 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_SUBNET_MASK;
|
|
8019c98: 2306 movs r3, #6
|
|
8019c9a: 623b str r3, [r7, #32]
|
|
break;
|
|
8019c9c: e09b b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
case (DHCP_OPTION_ROUTER):
|
|
decode_len = 4; /* only copy the first given router */
|
|
8019c9e: 2304 movs r3, #4
|
|
8019ca0: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
|
|
8019ca4: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
|
|
8019ca8: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019cac: 429a cmp r2, r3
|
|
8019cae: d209 bcs.n 8019cc4 <dhcp_parse_reply+0x244>
|
|
8019cb0: 4b38 ldr r3, [pc, #224] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019cb2: f240 6233 movw r2, #1587 ; 0x633
|
|
8019cb6: 493a ldr r1, [pc, #232] ; (8019da0 <dhcp_parse_reply+0x320>)
|
|
8019cb8: 4838 ldr r0, [pc, #224] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019cba: f002 fffd bl 801ccb8 <iprintf>
|
|
8019cbe: f06f 0305 mvn.w r3, #5
|
|
8019cc2: e19b b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_ROUTER;
|
|
8019cc4: 2307 movs r3, #7
|
|
8019cc6: 623b str r3, [r7, #32]
|
|
break;
|
|
8019cc8: e085 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
|
|
decode_idx = DHCP_OPTION_IDX_DNS_SERVER;
|
|
break;
|
|
#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */
|
|
case (DHCP_OPTION_LEASE_TIME):
|
|
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
|
|
8019cca: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019cce: 2b04 cmp r3, #4
|
|
8019cd0: d009 beq.n 8019ce6 <dhcp_parse_reply+0x266>
|
|
8019cd2: 4b30 ldr r3, [pc, #192] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019cd4: f240 6241 movw r2, #1601 ; 0x641
|
|
8019cd8: 492f ldr r1, [pc, #188] ; (8019d98 <dhcp_parse_reply+0x318>)
|
|
8019cda: 4830 ldr r0, [pc, #192] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019cdc: f002 ffec bl 801ccb8 <iprintf>
|
|
8019ce0: f06f 0305 mvn.w r3, #5
|
|
8019ce4: e18a b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_LEASE_TIME;
|
|
8019ce6: 2303 movs r3, #3
|
|
8019ce8: 623b str r3, [r7, #32]
|
|
break;
|
|
8019cea: e074 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;);
|
|
decode_idx = DHCP_OPTION_IDX_NTP_SERVER;
|
|
break;
|
|
#endif /* LWIP_DHCP_GET_NTP_SRV*/
|
|
case (DHCP_OPTION_OVERLOAD):
|
|
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
|
|
8019cec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019cf0: 2b01 cmp r3, #1
|
|
8019cf2: d009 beq.n 8019d08 <dhcp_parse_reply+0x288>
|
|
8019cf4: 4b27 ldr r3, [pc, #156] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019cf6: f240 624f movw r2, #1615 ; 0x64f
|
|
8019cfa: 492a ldr r1, [pc, #168] ; (8019da4 <dhcp_parse_reply+0x324>)
|
|
8019cfc: 4827 ldr r0, [pc, #156] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019cfe: f002 ffdb bl 801ccb8 <iprintf>
|
|
8019d02: f06f 0305 mvn.w r3, #5
|
|
8019d06: e179 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
/* decode overload only in options, not in file/sname: invalid packet */
|
|
LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;);
|
|
8019d08: 8efb ldrh r3, [r7, #54] ; 0x36
|
|
8019d0a: 2bf0 cmp r3, #240 ; 0xf0
|
|
8019d0c: d009 beq.n 8019d22 <dhcp_parse_reply+0x2a2>
|
|
8019d0e: 4b21 ldr r3, [pc, #132] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019d10: f240 6251 movw r2, #1617 ; 0x651
|
|
8019d14: 4924 ldr r1, [pc, #144] ; (8019da8 <dhcp_parse_reply+0x328>)
|
|
8019d16: 4821 ldr r0, [pc, #132] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019d18: f002 ffce bl 801ccb8 <iprintf>
|
|
8019d1c: f06f 0305 mvn.w r3, #5
|
|
8019d20: e16c b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_OVERLOAD;
|
|
8019d22: 2300 movs r3, #0
|
|
8019d24: 623b str r3, [r7, #32]
|
|
break;
|
|
8019d26: e056 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
case (DHCP_OPTION_MESSAGE_TYPE):
|
|
LWIP_ERROR("len == 1", len == 1, return ERR_VAL;);
|
|
8019d28: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019d2c: 2b01 cmp r3, #1
|
|
8019d2e: d009 beq.n 8019d44 <dhcp_parse_reply+0x2c4>
|
|
8019d30: 4b18 ldr r3, [pc, #96] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019d32: f240 6255 movw r2, #1621 ; 0x655
|
|
8019d36: 491b ldr r1, [pc, #108] ; (8019da4 <dhcp_parse_reply+0x324>)
|
|
8019d38: 4818 ldr r0, [pc, #96] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019d3a: f002 ffbd bl 801ccb8 <iprintf>
|
|
8019d3e: f06f 0305 mvn.w r3, #5
|
|
8019d42: e15b b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_MSG_TYPE;
|
|
8019d44: 2301 movs r3, #1
|
|
8019d46: 623b str r3, [r7, #32]
|
|
break;
|
|
8019d48: e045 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
case (DHCP_OPTION_SERVER_ID):
|
|
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
|
|
8019d4a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019d4e: 2b04 cmp r3, #4
|
|
8019d50: d009 beq.n 8019d66 <dhcp_parse_reply+0x2e6>
|
|
8019d52: 4b10 ldr r3, [pc, #64] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019d54: f240 6259 movw r2, #1625 ; 0x659
|
|
8019d58: 490f ldr r1, [pc, #60] ; (8019d98 <dhcp_parse_reply+0x318>)
|
|
8019d5a: 4810 ldr r0, [pc, #64] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019d5c: f002 ffac bl 801ccb8 <iprintf>
|
|
8019d60: f06f 0305 mvn.w r3, #5
|
|
8019d64: e14a b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_SERVER_ID;
|
|
8019d66: 2302 movs r3, #2
|
|
8019d68: 623b str r3, [r7, #32]
|
|
break;
|
|
8019d6a: e034 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
case (DHCP_OPTION_T1):
|
|
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
|
|
8019d6c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019d70: 2b04 cmp r3, #4
|
|
8019d72: d009 beq.n 8019d88 <dhcp_parse_reply+0x308>
|
|
8019d74: 4b07 ldr r3, [pc, #28] ; (8019d94 <dhcp_parse_reply+0x314>)
|
|
8019d76: f240 625d movw r2, #1629 ; 0x65d
|
|
8019d7a: 4907 ldr r1, [pc, #28] ; (8019d98 <dhcp_parse_reply+0x318>)
|
|
8019d7c: 4807 ldr r0, [pc, #28] ; (8019d9c <dhcp_parse_reply+0x31c>)
|
|
8019d7e: f002 ff9b bl 801ccb8 <iprintf>
|
|
8019d82: f06f 0305 mvn.w r3, #5
|
|
8019d86: e139 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_T1;
|
|
8019d88: 2304 movs r3, #4
|
|
8019d8a: 623b str r3, [r7, #32]
|
|
break;
|
|
8019d8c: e023 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
8019d8e: bf00 nop
|
|
8019d90: 2000f818 .word 0x2000f818
|
|
8019d94: 08020398 .word 0x08020398
|
|
8019d98: 08020620 .word 0x08020620
|
|
8019d9c: 080203f8 .word 0x080203f8
|
|
8019da0: 0802062c .word 0x0802062c
|
|
8019da4: 08020640 .word 0x08020640
|
|
8019da8: 0802064c .word 0x0802064c
|
|
case (DHCP_OPTION_T2):
|
|
LWIP_ERROR("len == 4", len == 4, return ERR_VAL;);
|
|
8019dac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019db0: 2b04 cmp r3, #4
|
|
8019db2: d009 beq.n 8019dc8 <dhcp_parse_reply+0x348>
|
|
8019db4: 4b93 ldr r3, [pc, #588] ; (801a004 <dhcp_parse_reply+0x584>)
|
|
8019db6: f240 6261 movw r2, #1633 ; 0x661
|
|
8019dba: 4993 ldr r1, [pc, #588] ; (801a008 <dhcp_parse_reply+0x588>)
|
|
8019dbc: 4893 ldr r0, [pc, #588] ; (801a00c <dhcp_parse_reply+0x58c>)
|
|
8019dbe: f002 ff7b bl 801ccb8 <iprintf>
|
|
8019dc2: f06f 0305 mvn.w r3, #5
|
|
8019dc6: e119 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
decode_idx = DHCP_OPTION_IDX_T2;
|
|
8019dc8: 2305 movs r3, #5
|
|
8019dca: 623b str r3, [r7, #32]
|
|
break;
|
|
8019dcc: e003 b.n 8019dd6 <dhcp_parse_reply+0x356>
|
|
default:
|
|
decode_len = 0;
|
|
8019dce: 2300 movs r3, #0
|
|
8019dd0: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op));
|
|
LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in,
|
|
dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0,
|
|
op, len, q, val_offset);
|
|
break;
|
|
8019dd4: bf00 nop
|
|
}
|
|
if (op == DHCP_OPTION_PAD) {
|
|
8019dd6: 7dfb ldrb r3, [r7, #23]
|
|
8019dd8: 2b00 cmp r3, #0
|
|
8019dda: d103 bne.n 8019de4 <dhcp_parse_reply+0x364>
|
|
offset++;
|
|
8019ddc: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019dde: 3301 adds r3, #1
|
|
8019de0: 877b strh r3, [r7, #58] ; 0x3a
|
|
8019de2: e0a1 b.n 8019f28 <dhcp_parse_reply+0x4a8>
|
|
} else {
|
|
if (offset + len + 2 > 0xFFFF) {
|
|
8019de4: 8f7a ldrh r2, [r7, #58] ; 0x3a
|
|
8019de6: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019dea: 4413 add r3, r2
|
|
8019dec: 3302 adds r3, #2
|
|
8019dee: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
8019df2: db02 blt.n 8019dfa <dhcp_parse_reply+0x37a>
|
|
/* overflow */
|
|
return ERR_BUF;
|
|
8019df4: f06f 0301 mvn.w r3, #1
|
|
8019df8: e100 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
offset = (u16_t)(offset + len + 2);
|
|
8019dfa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
8019dfe: b29a uxth r2, r3
|
|
8019e00: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019e02: 4413 add r3, r2
|
|
8019e04: b29b uxth r3, r3
|
|
8019e06: 3302 adds r3, #2
|
|
8019e08: 877b strh r3, [r7, #58] ; 0x3a
|
|
if (decode_len > 0) {
|
|
8019e0a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019e0e: 2b00 cmp r3, #0
|
|
8019e10: f000 808a beq.w 8019f28 <dhcp_parse_reply+0x4a8>
|
|
u32_t value = 0;
|
|
8019e14: 2300 movs r3, #0
|
|
8019e16: 60bb str r3, [r7, #8]
|
|
u16_t copy_len;
|
|
decode_next:
|
|
LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX);
|
|
8019e18: 6a3b ldr r3, [r7, #32]
|
|
8019e1a: 2b00 cmp r3, #0
|
|
8019e1c: db02 blt.n 8019e24 <dhcp_parse_reply+0x3a4>
|
|
8019e1e: 6a3b ldr r3, [r7, #32]
|
|
8019e20: 2b07 cmp r3, #7
|
|
8019e22: dd06 ble.n 8019e32 <dhcp_parse_reply+0x3b2>
|
|
8019e24: 4b77 ldr r3, [pc, #476] ; (801a004 <dhcp_parse_reply+0x584>)
|
|
8019e26: f44f 62cf mov.w r2, #1656 ; 0x678
|
|
8019e2a: 4979 ldr r1, [pc, #484] ; (801a010 <dhcp_parse_reply+0x590>)
|
|
8019e2c: 4877 ldr r0, [pc, #476] ; (801a00c <dhcp_parse_reply+0x58c>)
|
|
8019e2e: f002 ff43 bl 801ccb8 <iprintf>
|
|
if (!dhcp_option_given(dhcp, decode_idx)) {
|
|
8019e32: 4a78 ldr r2, [pc, #480] ; (801a014 <dhcp_parse_reply+0x594>)
|
|
8019e34: 6a3b ldr r3, [r7, #32]
|
|
8019e36: 4413 add r3, r2
|
|
8019e38: 781b ldrb r3, [r3, #0]
|
|
8019e3a: 2b00 cmp r3, #0
|
|
8019e3c: d174 bne.n 8019f28 <dhcp_parse_reply+0x4a8>
|
|
copy_len = LWIP_MIN(decode_len, 4);
|
|
8019e3e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019e42: 2b04 cmp r3, #4
|
|
8019e44: bf28 it cs
|
|
8019e46: 2304 movcs r3, #4
|
|
8019e48: b2db uxtb r3, r3
|
|
8019e4a: 82bb strh r3, [r7, #20]
|
|
if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) {
|
|
8019e4c: 8bfb ldrh r3, [r7, #30]
|
|
8019e4e: 8aba ldrh r2, [r7, #20]
|
|
8019e50: f107 0108 add.w r1, r7, #8
|
|
8019e54: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
8019e56: f7f8 fc05 bl 8012664 <pbuf_copy_partial>
|
|
8019e5a: 4603 mov r3, r0
|
|
8019e5c: 461a mov r2, r3
|
|
8019e5e: 8abb ldrh r3, [r7, #20]
|
|
8019e60: 4293 cmp r3, r2
|
|
8019e62: d002 beq.n 8019e6a <dhcp_parse_reply+0x3ea>
|
|
return ERR_BUF;
|
|
8019e64: f06f 0301 mvn.w r3, #1
|
|
8019e68: e0c8 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
if (decode_len > 4) {
|
|
8019e6a: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019e6e: 2b04 cmp r3, #4
|
|
8019e70: d933 bls.n 8019eda <dhcp_parse_reply+0x45a>
|
|
/* decode more than one u32_t */
|
|
u16_t next_val_offset;
|
|
LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;);
|
|
8019e72: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019e76: f003 0303 and.w r3, r3, #3
|
|
8019e7a: b2db uxtb r3, r3
|
|
8019e7c: 2b00 cmp r3, #0
|
|
8019e7e: d009 beq.n 8019e94 <dhcp_parse_reply+0x414>
|
|
8019e80: 4b60 ldr r3, [pc, #384] ; (801a004 <dhcp_parse_reply+0x584>)
|
|
8019e82: f240 6281 movw r2, #1665 ; 0x681
|
|
8019e86: 4964 ldr r1, [pc, #400] ; (801a018 <dhcp_parse_reply+0x598>)
|
|
8019e88: 4860 ldr r0, [pc, #384] ; (801a00c <dhcp_parse_reply+0x58c>)
|
|
8019e8a: f002 ff15 bl 801ccb8 <iprintf>
|
|
8019e8e: f06f 0305 mvn.w r3, #5
|
|
8019e92: e0b3 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
dhcp_got_option(dhcp, decode_idx);
|
|
8019e94: 4a5f ldr r2, [pc, #380] ; (801a014 <dhcp_parse_reply+0x594>)
|
|
8019e96: 6a3b ldr r3, [r7, #32]
|
|
8019e98: 4413 add r3, r2
|
|
8019e9a: 2201 movs r2, #1
|
|
8019e9c: 701a strb r2, [r3, #0]
|
|
dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value));
|
|
8019e9e: 68bb ldr r3, [r7, #8]
|
|
8019ea0: 4618 mov r0, r3
|
|
8019ea2: f7f6 fe3a bl 8010b1a <lwip_htonl>
|
|
8019ea6: 4601 mov r1, r0
|
|
8019ea8: 4a5c ldr r2, [pc, #368] ; (801a01c <dhcp_parse_reply+0x59c>)
|
|
8019eaa: 6a3b ldr r3, [r7, #32]
|
|
8019eac: f842 1023 str.w r1, [r2, r3, lsl #2]
|
|
decode_len = (u8_t)(decode_len - 4);
|
|
8019eb0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019eb4: 3b04 subs r3, #4
|
|
8019eb6: f887 3026 strb.w r3, [r7, #38] ; 0x26
|
|
next_val_offset = (u16_t)(val_offset + 4);
|
|
8019eba: 8bfb ldrh r3, [r7, #30]
|
|
8019ebc: 3304 adds r3, #4
|
|
8019ebe: 827b strh r3, [r7, #18]
|
|
if (next_val_offset < val_offset) {
|
|
8019ec0: 8a7a ldrh r2, [r7, #18]
|
|
8019ec2: 8bfb ldrh r3, [r7, #30]
|
|
8019ec4: 429a cmp r2, r3
|
|
8019ec6: d202 bcs.n 8019ece <dhcp_parse_reply+0x44e>
|
|
/* overflow */
|
|
return ERR_BUF;
|
|
8019ec8: f06f 0301 mvn.w r3, #1
|
|
8019ecc: e096 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
}
|
|
val_offset = next_val_offset;
|
|
8019ece: 8a7b ldrh r3, [r7, #18]
|
|
8019ed0: 83fb strh r3, [r7, #30]
|
|
decode_idx++;
|
|
8019ed2: 6a3b ldr r3, [r7, #32]
|
|
8019ed4: 3301 adds r3, #1
|
|
8019ed6: 623b str r3, [r7, #32]
|
|
goto decode_next;
|
|
8019ed8: e79e b.n 8019e18 <dhcp_parse_reply+0x398>
|
|
} else if (decode_len == 4) {
|
|
8019eda: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019ede: 2b04 cmp r3, #4
|
|
8019ee0: d106 bne.n 8019ef0 <dhcp_parse_reply+0x470>
|
|
value = lwip_ntohl(value);
|
|
8019ee2: 68bb ldr r3, [r7, #8]
|
|
8019ee4: 4618 mov r0, r3
|
|
8019ee6: f7f6 fe18 bl 8010b1a <lwip_htonl>
|
|
8019eea: 4603 mov r3, r0
|
|
8019eec: 60bb str r3, [r7, #8]
|
|
8019eee: e011 b.n 8019f14 <dhcp_parse_reply+0x494>
|
|
} else {
|
|
LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;);
|
|
8019ef0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
|
|
8019ef4: 2b01 cmp r3, #1
|
|
8019ef6: d009 beq.n 8019f0c <dhcp_parse_reply+0x48c>
|
|
8019ef8: 4b42 ldr r3, [pc, #264] ; (801a004 <dhcp_parse_reply+0x584>)
|
|
8019efa: f44f 62d2 mov.w r2, #1680 ; 0x690
|
|
8019efe: 4948 ldr r1, [pc, #288] ; (801a020 <dhcp_parse_reply+0x5a0>)
|
|
8019f00: 4842 ldr r0, [pc, #264] ; (801a00c <dhcp_parse_reply+0x58c>)
|
|
8019f02: f002 fed9 bl 801ccb8 <iprintf>
|
|
8019f06: f06f 0305 mvn.w r3, #5
|
|
8019f0a: e077 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
value = ((u8_t *)&value)[0];
|
|
8019f0c: f107 0308 add.w r3, r7, #8
|
|
8019f10: 781b ldrb r3, [r3, #0]
|
|
8019f12: 60bb str r3, [r7, #8]
|
|
}
|
|
dhcp_got_option(dhcp, decode_idx);
|
|
8019f14: 4a3f ldr r2, [pc, #252] ; (801a014 <dhcp_parse_reply+0x594>)
|
|
8019f16: 6a3b ldr r3, [r7, #32]
|
|
8019f18: 4413 add r3, r2
|
|
8019f1a: 2201 movs r2, #1
|
|
8019f1c: 701a strb r2, [r3, #0]
|
|
dhcp_set_option_value(dhcp, decode_idx, value);
|
|
8019f1e: 68ba ldr r2, [r7, #8]
|
|
8019f20: 493e ldr r1, [pc, #248] ; (801a01c <dhcp_parse_reply+0x59c>)
|
|
8019f22: 6a3b ldr r3, [r7, #32]
|
|
8019f24: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
}
|
|
}
|
|
}
|
|
if (offset >= q->len) {
|
|
8019f28: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f2a: 895b ldrh r3, [r3, #10]
|
|
8019f2c: 8f7a ldrh r2, [r7, #58] ; 0x3a
|
|
8019f2e: 429a cmp r2, r3
|
|
8019f30: d324 bcc.n 8019f7c <dhcp_parse_reply+0x4fc>
|
|
offset = (u16_t)(offset - q->len);
|
|
8019f32: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f34: 895b ldrh r3, [r3, #10]
|
|
8019f36: 8f7a ldrh r2, [r7, #58] ; 0x3a
|
|
8019f38: 1ad3 subs r3, r2, r3
|
|
8019f3a: 877b strh r3, [r7, #58] ; 0x3a
|
|
offset_max = (u16_t)(offset_max - q->len);
|
|
8019f3c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f3e: 895b ldrh r3, [r3, #10]
|
|
8019f40: 8f3a ldrh r2, [r7, #56] ; 0x38
|
|
8019f42: 1ad3 subs r3, r2, r3
|
|
8019f44: 873b strh r3, [r7, #56] ; 0x38
|
|
if (offset < offset_max) {
|
|
8019f46: 8f7a ldrh r2, [r7, #58] ; 0x3a
|
|
8019f48: 8f3b ldrh r3, [r7, #56] ; 0x38
|
|
8019f4a: 429a cmp r2, r3
|
|
8019f4c: d213 bcs.n 8019f76 <dhcp_parse_reply+0x4f6>
|
|
q = q->next;
|
|
8019f4e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f50: 681b ldr r3, [r3, #0]
|
|
8019f52: 633b str r3, [r7, #48] ; 0x30
|
|
LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;);
|
|
8019f54: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f56: 2b00 cmp r3, #0
|
|
8019f58: d109 bne.n 8019f6e <dhcp_parse_reply+0x4ee>
|
|
8019f5a: 4b2a ldr r3, [pc, #168] ; (801a004 <dhcp_parse_reply+0x584>)
|
|
8019f5c: f240 629d movw r2, #1693 ; 0x69d
|
|
8019f60: 4930 ldr r1, [pc, #192] ; (801a024 <dhcp_parse_reply+0x5a4>)
|
|
8019f62: 482a ldr r0, [pc, #168] ; (801a00c <dhcp_parse_reply+0x58c>)
|
|
8019f64: f002 fea8 bl 801ccb8 <iprintf>
|
|
8019f68: f06f 0305 mvn.w r3, #5
|
|
8019f6c: e046 b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
options = (u8_t *)q->payload;
|
|
8019f6e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f70: 685b ldr r3, [r3, #4]
|
|
8019f72: 63fb str r3, [r7, #60] ; 0x3c
|
|
8019f74: e002 b.n 8019f7c <dhcp_parse_reply+0x4fc>
|
|
} else {
|
|
/* We've run out of bytes, probably no end marker. Don't proceed. */
|
|
return ERR_BUF;
|
|
8019f76: f06f 0301 mvn.w r3, #1
|
|
8019f7a: e03f b.n 8019ffc <dhcp_parse_reply+0x57c>
|
|
while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) {
|
|
8019f7c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
8019f7e: 2b00 cmp r3, #0
|
|
8019f80: d00a beq.n 8019f98 <dhcp_parse_reply+0x518>
|
|
8019f82: 8f7a ldrh r2, [r7, #58] ; 0x3a
|
|
8019f84: 8f3b ldrh r3, [r7, #56] ; 0x38
|
|
8019f86: 429a cmp r2, r3
|
|
8019f88: d206 bcs.n 8019f98 <dhcp_parse_reply+0x518>
|
|
8019f8a: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
8019f8c: 6bfa ldr r2, [r7, #60] ; 0x3c
|
|
8019f8e: 4413 add r3, r2
|
|
8019f90: 781b ldrb r3, [r3, #0]
|
|
8019f92: 2bff cmp r3, #255 ; 0xff
|
|
8019f94: f47f adb7 bne.w 8019b06 <dhcp_parse_reply+0x86>
|
|
}
|
|
}
|
|
}
|
|
/* is this an overloaded message? */
|
|
if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) {
|
|
8019f98: 4b1e ldr r3, [pc, #120] ; (801a014 <dhcp_parse_reply+0x594>)
|
|
8019f9a: 781b ldrb r3, [r3, #0]
|
|
8019f9c: 2b00 cmp r3, #0
|
|
8019f9e: d018 beq.n 8019fd2 <dhcp_parse_reply+0x552>
|
|
u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD);
|
|
8019fa0: 4b1e ldr r3, [pc, #120] ; (801a01c <dhcp_parse_reply+0x59c>)
|
|
8019fa2: 681b ldr r3, [r3, #0]
|
|
8019fa4: 60fb str r3, [r7, #12]
|
|
dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD);
|
|
8019fa6: 4b1b ldr r3, [pc, #108] ; (801a014 <dhcp_parse_reply+0x594>)
|
|
8019fa8: 2200 movs r2, #0
|
|
8019faa: 701a strb r2, [r3, #0]
|
|
if (overload == DHCP_OVERLOAD_FILE) {
|
|
8019fac: 68fb ldr r3, [r7, #12]
|
|
8019fae: 2b01 cmp r3, #1
|
|
8019fb0: d102 bne.n 8019fb8 <dhcp_parse_reply+0x538>
|
|
parse_file_as_options = 1;
|
|
8019fb2: 2301 movs r3, #1
|
|
8019fb4: 62fb str r3, [r7, #44] ; 0x2c
|
|
8019fb6: e00c b.n 8019fd2 <dhcp_parse_reply+0x552>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n"));
|
|
} else if (overload == DHCP_OVERLOAD_SNAME) {
|
|
8019fb8: 68fb ldr r3, [r7, #12]
|
|
8019fba: 2b02 cmp r3, #2
|
|
8019fbc: d102 bne.n 8019fc4 <dhcp_parse_reply+0x544>
|
|
parse_sname_as_options = 1;
|
|
8019fbe: 2301 movs r3, #1
|
|
8019fc0: 62bb str r3, [r7, #40] ; 0x28
|
|
8019fc2: e006 b.n 8019fd2 <dhcp_parse_reply+0x552>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n"));
|
|
} else if (overload == DHCP_OVERLOAD_SNAME_FILE) {
|
|
8019fc4: 68fb ldr r3, [r7, #12]
|
|
8019fc6: 2b03 cmp r3, #3
|
|
8019fc8: d103 bne.n 8019fd2 <dhcp_parse_reply+0x552>
|
|
parse_sname_as_options = 1;
|
|
8019fca: 2301 movs r3, #1
|
|
8019fcc: 62bb str r3, [r7, #40] ; 0x28
|
|
parse_file_as_options = 1;
|
|
8019fce: 2301 movs r3, #1
|
|
8019fd0: 62fb str r3, [r7, #44] ; 0x2c
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n"));
|
|
} else {
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload));
|
|
}
|
|
}
|
|
if (parse_file_as_options) {
|
|
8019fd2: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
8019fd4: 2b00 cmp r3, #0
|
|
8019fd6: d006 beq.n 8019fe6 <dhcp_parse_reply+0x566>
|
|
/* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */
|
|
parse_file_as_options = 0;
|
|
8019fd8: 2300 movs r3, #0
|
|
8019fda: 62fb str r3, [r7, #44] ; 0x2c
|
|
options_idx = DHCP_FILE_OFS;
|
|
8019fdc: 236c movs r3, #108 ; 0x6c
|
|
8019fde: 86fb strh r3, [r7, #54] ; 0x36
|
|
options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN;
|
|
8019fe0: 23ec movs r3, #236 ; 0xec
|
|
8019fe2: 86bb strh r3, [r7, #52] ; 0x34
|
|
#if LWIP_DHCP_BOOTP_FILE
|
|
file_overloaded = 1;
|
|
#endif
|
|
goto again;
|
|
8019fe4: e569 b.n 8019aba <dhcp_parse_reply+0x3a>
|
|
} else if (parse_sname_as_options) {
|
|
8019fe6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
8019fe8: 2b00 cmp r3, #0
|
|
8019fea: d006 beq.n 8019ffa <dhcp_parse_reply+0x57a>
|
|
parse_sname_as_options = 0;
|
|
8019fec: 2300 movs r3, #0
|
|
8019fee: 62bb str r3, [r7, #40] ; 0x28
|
|
options_idx = DHCP_SNAME_OFS;
|
|
8019ff0: 232c movs r3, #44 ; 0x2c
|
|
8019ff2: 86fb strh r3, [r7, #54] ; 0x36
|
|
options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN;
|
|
8019ff4: 236c movs r3, #108 ; 0x6c
|
|
8019ff6: 86bb strh r3, [r7, #52] ; 0x34
|
|
goto again;
|
|
8019ff8: e55f b.n 8019aba <dhcp_parse_reply+0x3a>
|
|
}
|
|
/* make sure the string is really NULL-terminated */
|
|
dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0;
|
|
}
|
|
#endif /* LWIP_DHCP_BOOTP_FILE */
|
|
return ERR_OK;
|
|
8019ffa: 2300 movs r3, #0
|
|
}
|
|
8019ffc: 4618 mov r0, r3
|
|
8019ffe: 3740 adds r7, #64 ; 0x40
|
|
801a000: 46bd mov sp, r7
|
|
801a002: bd80 pop {r7, pc}
|
|
801a004: 08020398 .word 0x08020398
|
|
801a008: 08020620 .word 0x08020620
|
|
801a00c: 080203f8 .word 0x080203f8
|
|
801a010: 08020664 .word 0x08020664
|
|
801a014: 2000f818 .word 0x2000f818
|
|
801a018: 08020678 .word 0x08020678
|
|
801a01c: 2000f820 .word 0x2000f820
|
|
801a020: 08020690 .word 0x08020690
|
|
801a024: 080206a4 .word 0x080206a4
|
|
|
|
0801a028 <dhcp_recv>:
|
|
/**
|
|
* If an incoming DHCP message is in response to us, then trigger the state machine
|
|
*/
|
|
static void
|
|
dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port)
|
|
{
|
|
801a028: b580 push {r7, lr}
|
|
801a02a: b08a sub sp, #40 ; 0x28
|
|
801a02c: af00 add r7, sp, #0
|
|
801a02e: 60f8 str r0, [r7, #12]
|
|
801a030: 60b9 str r1, [r7, #8]
|
|
801a032: 607a str r2, [r7, #4]
|
|
801a034: 603b str r3, [r7, #0]
|
|
struct netif *netif = ip_current_input_netif();
|
|
801a036: 4b5f ldr r3, [pc, #380] ; (801a1b4 <dhcp_recv+0x18c>)
|
|
801a038: 685b ldr r3, [r3, #4]
|
|
801a03a: 623b str r3, [r7, #32]
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
801a03c: 6a3b ldr r3, [r7, #32]
|
|
801a03e: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801a040: 61fb str r3, [r7, #28]
|
|
struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload;
|
|
801a042: 687b ldr r3, [r7, #4]
|
|
801a044: 685b ldr r3, [r3, #4]
|
|
801a046: 61bb str r3, [r7, #24]
|
|
struct dhcp_msg *msg_in;
|
|
|
|
LWIP_UNUSED_ARG(arg);
|
|
|
|
/* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */
|
|
if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) {
|
|
801a048: 69fb ldr r3, [r7, #28]
|
|
801a04a: 2b00 cmp r3, #0
|
|
801a04c: f000 809d beq.w 801a18a <dhcp_recv+0x162>
|
|
801a050: 69fb ldr r3, [r7, #28]
|
|
801a052: 791b ldrb r3, [r3, #4]
|
|
801a054: 2b00 cmp r3, #0
|
|
801a056: f000 8098 beq.w 801a18a <dhcp_recv+0x162>
|
|
/* prevent warnings about unused arguments */
|
|
LWIP_UNUSED_ARG(pcb);
|
|
LWIP_UNUSED_ARG(addr);
|
|
LWIP_UNUSED_ARG(port);
|
|
|
|
if (p->len < DHCP_MIN_REPLY_LEN) {
|
|
801a05a: 687b ldr r3, [r7, #4]
|
|
801a05c: 895b ldrh r3, [r3, #10]
|
|
801a05e: 2b2b cmp r3, #43 ; 0x2b
|
|
801a060: f240 8095 bls.w 801a18e <dhcp_recv+0x166>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n"));
|
|
goto free_pbuf_and_return;
|
|
}
|
|
|
|
if (reply_msg->op != DHCP_BOOTREPLY) {
|
|
801a064: 69bb ldr r3, [r7, #24]
|
|
801a066: 781b ldrb r3, [r3, #0]
|
|
801a068: 2b02 cmp r3, #2
|
|
801a06a: f040 8092 bne.w 801a192 <dhcp_recv+0x16a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op));
|
|
goto free_pbuf_and_return;
|
|
}
|
|
/* iterate through hardware address and match against DHCP message */
|
|
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
|
|
801a06e: 2300 movs r3, #0
|
|
801a070: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
801a074: e012 b.n 801a09c <dhcp_recv+0x74>
|
|
if (netif->hwaddr[i] != reply_msg->chaddr[i]) {
|
|
801a076: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
801a07a: 6a3a ldr r2, [r7, #32]
|
|
801a07c: 4413 add r3, r2
|
|
801a07e: f893 202a ldrb.w r2, [r3, #42] ; 0x2a
|
|
801a082: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
801a086: 69b9 ldr r1, [r7, #24]
|
|
801a088: 440b add r3, r1
|
|
801a08a: 7f1b ldrb r3, [r3, #28]
|
|
801a08c: 429a cmp r2, r3
|
|
801a08e: f040 8082 bne.w 801a196 <dhcp_recv+0x16e>
|
|
for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
|
|
801a092: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
801a096: 3301 adds r3, #1
|
|
801a098: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
801a09c: 6a3b ldr r3, [r7, #32]
|
|
801a09e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
801a0a2: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
|
|
801a0a6: 429a cmp r2, r3
|
|
801a0a8: d203 bcs.n 801a0b2 <dhcp_recv+0x8a>
|
|
801a0aa: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
|
|
801a0ae: 2b05 cmp r3, #5
|
|
801a0b0: d9e1 bls.n 801a076 <dhcp_recv+0x4e>
|
|
(u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i]));
|
|
goto free_pbuf_and_return;
|
|
}
|
|
}
|
|
/* match transaction ID against what we expected */
|
|
if (lwip_ntohl(reply_msg->xid) != dhcp->xid) {
|
|
801a0b2: 69bb ldr r3, [r7, #24]
|
|
801a0b4: 685b ldr r3, [r3, #4]
|
|
801a0b6: 4618 mov r0, r3
|
|
801a0b8: f7f6 fd2f bl 8010b1a <lwip_htonl>
|
|
801a0bc: 4602 mov r2, r0
|
|
801a0be: 69fb ldr r3, [r7, #28]
|
|
801a0c0: 681b ldr r3, [r3, #0]
|
|
801a0c2: 429a cmp r2, r3
|
|
801a0c4: d169 bne.n 801a19a <dhcp_recv+0x172>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
|
|
("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid));
|
|
goto free_pbuf_and_return;
|
|
}
|
|
/* option fields could be unfold? */
|
|
if (dhcp_parse_reply(p, dhcp) != ERR_OK) {
|
|
801a0c6: 69f9 ldr r1, [r7, #28]
|
|
801a0c8: 6878 ldr r0, [r7, #4]
|
|
801a0ca: f7ff fcd9 bl 8019a80 <dhcp_parse_reply>
|
|
801a0ce: 4603 mov r3, r0
|
|
801a0d0: 2b00 cmp r3, #0
|
|
801a0d2: d164 bne.n 801a19e <dhcp_recv+0x176>
|
|
goto free_pbuf_and_return;
|
|
}
|
|
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n"));
|
|
/* obtain pointer to DHCP message type */
|
|
if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) {
|
|
801a0d4: 4b38 ldr r3, [pc, #224] ; (801a1b8 <dhcp_recv+0x190>)
|
|
801a0d6: 785b ldrb r3, [r3, #1]
|
|
801a0d8: 2b00 cmp r3, #0
|
|
801a0da: d062 beq.n 801a1a2 <dhcp_recv+0x17a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n"));
|
|
goto free_pbuf_and_return;
|
|
}
|
|
|
|
msg_in = (struct dhcp_msg *)p->payload;
|
|
801a0dc: 687b ldr r3, [r7, #4]
|
|
801a0de: 685b ldr r3, [r3, #4]
|
|
801a0e0: 617b str r3, [r7, #20]
|
|
/* read DHCP message type */
|
|
msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE);
|
|
801a0e2: 4b36 ldr r3, [pc, #216] ; (801a1bc <dhcp_recv+0x194>)
|
|
801a0e4: 685b ldr r3, [r3, #4]
|
|
801a0e6: 74fb strb r3, [r7, #19]
|
|
/* message type is DHCP ACK? */
|
|
if (msg_type == DHCP_ACK) {
|
|
801a0e8: 7cfb ldrb r3, [r7, #19]
|
|
801a0ea: 2b05 cmp r3, #5
|
|
801a0ec: d12a bne.n 801a144 <dhcp_recv+0x11c>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n"));
|
|
/* in requesting state? */
|
|
if (dhcp->state == DHCP_STATE_REQUESTING) {
|
|
801a0ee: 69fb ldr r3, [r7, #28]
|
|
801a0f0: 795b ldrb r3, [r3, #5]
|
|
801a0f2: 2b01 cmp r3, #1
|
|
801a0f4: d112 bne.n 801a11c <dhcp_recv+0xf4>
|
|
dhcp_handle_ack(netif, msg_in);
|
|
801a0f6: 6979 ldr r1, [r7, #20]
|
|
801a0f8: 6a38 ldr r0, [r7, #32]
|
|
801a0fa: f7fe fe05 bl 8018d08 <dhcp_handle_ack>
|
|
#if DHCP_DOES_ARP_CHECK
|
|
if ((netif->flags & NETIF_FLAG_ETHARP) != 0) {
|
|
801a0fe: 6a3b ldr r3, [r7, #32]
|
|
801a100: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801a104: f003 0308 and.w r3, r3, #8
|
|
801a108: 2b00 cmp r3, #0
|
|
801a10a: d003 beq.n 801a114 <dhcp_recv+0xec>
|
|
/* check if the acknowledged lease address is already in use */
|
|
dhcp_check(netif);
|
|
801a10c: 6a38 ldr r0, [r7, #32]
|
|
801a10e: f7fe fb73 bl 80187f8 <dhcp_check>
|
|
801a112: e047 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
} else {
|
|
/* bind interface to the acknowledged lease address */
|
|
dhcp_bind(netif);
|
|
801a114: 6a38 ldr r0, [r7, #32]
|
|
801a116: f7ff f867 bl 80191e8 <dhcp_bind>
|
|
801a11a: e043 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
/* bind interface to the acknowledged lease address */
|
|
dhcp_bind(netif);
|
|
#endif
|
|
}
|
|
/* already bound to the given lease address? */
|
|
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
|
|
801a11c: 69fb ldr r3, [r7, #28]
|
|
801a11e: 795b ldrb r3, [r3, #5]
|
|
801a120: 2b03 cmp r3, #3
|
|
801a122: d007 beq.n 801a134 <dhcp_recv+0x10c>
|
|
801a124: 69fb ldr r3, [r7, #28]
|
|
801a126: 795b ldrb r3, [r3, #5]
|
|
801a128: 2b04 cmp r3, #4
|
|
801a12a: d003 beq.n 801a134 <dhcp_recv+0x10c>
|
|
(dhcp->state == DHCP_STATE_RENEWING)) {
|
|
801a12c: 69fb ldr r3, [r7, #28]
|
|
801a12e: 795b ldrb r3, [r3, #5]
|
|
else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) ||
|
|
801a130: 2b05 cmp r3, #5
|
|
801a132: d137 bne.n 801a1a4 <dhcp_recv+0x17c>
|
|
dhcp_handle_ack(netif, msg_in);
|
|
801a134: 6979 ldr r1, [r7, #20]
|
|
801a136: 6a38 ldr r0, [r7, #32]
|
|
801a138: f7fe fde6 bl 8018d08 <dhcp_handle_ack>
|
|
dhcp_bind(netif);
|
|
801a13c: 6a38 ldr r0, [r7, #32]
|
|
801a13e: f7ff f853 bl 80191e8 <dhcp_bind>
|
|
801a142: e02f b.n 801a1a4 <dhcp_recv+0x17c>
|
|
}
|
|
}
|
|
/* received a DHCP_NAK in appropriate state? */
|
|
else if ((msg_type == DHCP_NAK) &&
|
|
801a144: 7cfb ldrb r3, [r7, #19]
|
|
801a146: 2b06 cmp r3, #6
|
|
801a148: d113 bne.n 801a172 <dhcp_recv+0x14a>
|
|
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
|
|
801a14a: 69fb ldr r3, [r7, #28]
|
|
801a14c: 795b ldrb r3, [r3, #5]
|
|
else if ((msg_type == DHCP_NAK) &&
|
|
801a14e: 2b03 cmp r3, #3
|
|
801a150: d00b beq.n 801a16a <dhcp_recv+0x142>
|
|
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
|
|
801a152: 69fb ldr r3, [r7, #28]
|
|
801a154: 795b ldrb r3, [r3, #5]
|
|
801a156: 2b01 cmp r3, #1
|
|
801a158: d007 beq.n 801a16a <dhcp_recv+0x142>
|
|
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
|
|
801a15a: 69fb ldr r3, [r7, #28]
|
|
801a15c: 795b ldrb r3, [r3, #5]
|
|
((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) ||
|
|
801a15e: 2b04 cmp r3, #4
|
|
801a160: d003 beq.n 801a16a <dhcp_recv+0x142>
|
|
(dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) {
|
|
801a162: 69fb ldr r3, [r7, #28]
|
|
801a164: 795b ldrb r3, [r3, #5]
|
|
801a166: 2b05 cmp r3, #5
|
|
801a168: d103 bne.n 801a172 <dhcp_recv+0x14a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n"));
|
|
dhcp_handle_nak(netif);
|
|
801a16a: 6a38 ldr r0, [r7, #32]
|
|
801a16c: f7fe fb2a bl 80187c4 <dhcp_handle_nak>
|
|
801a170: e018 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
}
|
|
/* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */
|
|
else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) {
|
|
801a172: 7cfb ldrb r3, [r7, #19]
|
|
801a174: 2b02 cmp r3, #2
|
|
801a176: d108 bne.n 801a18a <dhcp_recv+0x162>
|
|
801a178: 69fb ldr r3, [r7, #28]
|
|
801a17a: 795b ldrb r3, [r3, #5]
|
|
801a17c: 2b06 cmp r3, #6
|
|
801a17e: d104 bne.n 801a18a <dhcp_recv+0x162>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n"));
|
|
/* remember offered lease */
|
|
dhcp_handle_offer(netif, msg_in);
|
|
801a180: 6979 ldr r1, [r7, #20]
|
|
801a182: 6a38 ldr r0, [r7, #32]
|
|
801a184: f7fe fb6c bl 8018860 <dhcp_handle_offer>
|
|
801a188: e00c b.n 801a1a4 <dhcp_recv+0x17c>
|
|
}
|
|
|
|
free_pbuf_and_return:
|
|
801a18a: bf00 nop
|
|
801a18c: e00a b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a18e: bf00 nop
|
|
801a190: e008 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a192: bf00 nop
|
|
801a194: e006 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a196: bf00 nop
|
|
801a198: e004 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a19a: bf00 nop
|
|
801a19c: e002 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a19e: bf00 nop
|
|
801a1a0: e000 b.n 801a1a4 <dhcp_recv+0x17c>
|
|
goto free_pbuf_and_return;
|
|
801a1a2: bf00 nop
|
|
pbuf_free(p);
|
|
801a1a4: 6878 ldr r0, [r7, #4]
|
|
801a1a6: f7f8 f857 bl 8012258 <pbuf_free>
|
|
}
|
|
801a1aa: bf00 nop
|
|
801a1ac: 3728 adds r7, #40 ; 0x28
|
|
801a1ae: 46bd mov sp, r7
|
|
801a1b0: bd80 pop {r7, pc}
|
|
801a1b2: bf00 nop
|
|
801a1b4: 2000c0c8 .word 0x2000c0c8
|
|
801a1b8: 2000f818 .word 0x2000f818
|
|
801a1bc: 2000f820 .word 0x2000f820
|
|
|
|
0801a1c0 <dhcp_create_msg>:
|
|
* @param dhcp dhcp control struct
|
|
* @param message_type message type of the request
|
|
*/
|
|
static struct pbuf *
|
|
dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len)
|
|
{
|
|
801a1c0: b580 push {r7, lr}
|
|
801a1c2: b088 sub sp, #32
|
|
801a1c4: af00 add r7, sp, #0
|
|
801a1c6: 60f8 str r0, [r7, #12]
|
|
801a1c8: 60b9 str r1, [r7, #8]
|
|
801a1ca: 603b str r3, [r7, #0]
|
|
801a1cc: 4613 mov r3, r2
|
|
801a1ce: 71fb strb r3, [r7, #7]
|
|
if (!xid_initialised) {
|
|
xid = DHCP_GLOBAL_XID;
|
|
xid_initialised = !xid_initialised;
|
|
}
|
|
#endif
|
|
LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;);
|
|
801a1d0: 68fb ldr r3, [r7, #12]
|
|
801a1d2: 2b00 cmp r3, #0
|
|
801a1d4: d108 bne.n 801a1e8 <dhcp_create_msg+0x28>
|
|
801a1d6: 4b5f ldr r3, [pc, #380] ; (801a354 <dhcp_create_msg+0x194>)
|
|
801a1d8: f240 7269 movw r2, #1897 ; 0x769
|
|
801a1dc: 495e ldr r1, [pc, #376] ; (801a358 <dhcp_create_msg+0x198>)
|
|
801a1de: 485f ldr r0, [pc, #380] ; (801a35c <dhcp_create_msg+0x19c>)
|
|
801a1e0: f002 fd6a bl 801ccb8 <iprintf>
|
|
801a1e4: 2300 movs r3, #0
|
|
801a1e6: e0b1 b.n 801a34c <dhcp_create_msg+0x18c>
|
|
LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;);
|
|
801a1e8: 68bb ldr r3, [r7, #8]
|
|
801a1ea: 2b00 cmp r3, #0
|
|
801a1ec: d108 bne.n 801a200 <dhcp_create_msg+0x40>
|
|
801a1ee: 4b59 ldr r3, [pc, #356] ; (801a354 <dhcp_create_msg+0x194>)
|
|
801a1f0: f240 726a movw r2, #1898 ; 0x76a
|
|
801a1f4: 495a ldr r1, [pc, #360] ; (801a360 <dhcp_create_msg+0x1a0>)
|
|
801a1f6: 4859 ldr r0, [pc, #356] ; (801a35c <dhcp_create_msg+0x19c>)
|
|
801a1f8: f002 fd5e bl 801ccb8 <iprintf>
|
|
801a1fc: 2300 movs r3, #0
|
|
801a1fe: e0a5 b.n 801a34c <dhcp_create_msg+0x18c>
|
|
p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM);
|
|
801a200: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801a204: f44f 719a mov.w r1, #308 ; 0x134
|
|
801a208: 2036 movs r0, #54 ; 0x36
|
|
801a20a: f7f7 fd45 bl 8011c98 <pbuf_alloc>
|
|
801a20e: 61b8 str r0, [r7, #24]
|
|
if (p_out == NULL) {
|
|
801a210: 69bb ldr r3, [r7, #24]
|
|
801a212: 2b00 cmp r3, #0
|
|
801a214: d101 bne.n 801a21a <dhcp_create_msg+0x5a>
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
|
|
("dhcp_create_msg(): could not allocate pbuf\n"));
|
|
return NULL;
|
|
801a216: 2300 movs r3, #0
|
|
801a218: e098 b.n 801a34c <dhcp_create_msg+0x18c>
|
|
}
|
|
LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg",
|
|
801a21a: 69bb ldr r3, [r7, #24]
|
|
801a21c: 895b ldrh r3, [r3, #10]
|
|
801a21e: f5b3 7f9a cmp.w r3, #308 ; 0x134
|
|
801a222: d206 bcs.n 801a232 <dhcp_create_msg+0x72>
|
|
801a224: 4b4b ldr r3, [pc, #300] ; (801a354 <dhcp_create_msg+0x194>)
|
|
801a226: f240 7272 movw r2, #1906 ; 0x772
|
|
801a22a: 494e ldr r1, [pc, #312] ; (801a364 <dhcp_create_msg+0x1a4>)
|
|
801a22c: 484b ldr r0, [pc, #300] ; (801a35c <dhcp_create_msg+0x19c>)
|
|
801a22e: f002 fd43 bl 801ccb8 <iprintf>
|
|
(p_out->len >= sizeof(struct dhcp_msg)));
|
|
|
|
/* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */
|
|
if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) {
|
|
801a232: 79fb ldrb r3, [r7, #7]
|
|
801a234: 2b03 cmp r3, #3
|
|
801a236: d103 bne.n 801a240 <dhcp_create_msg+0x80>
|
|
801a238: 68bb ldr r3, [r7, #8]
|
|
801a23a: 795b ldrb r3, [r3, #5]
|
|
801a23c: 2b03 cmp r3, #3
|
|
801a23e: d10d bne.n 801a25c <dhcp_create_msg+0x9c>
|
|
/* reuse transaction identifier in retransmissions */
|
|
if (dhcp->tries == 0) {
|
|
801a240: 68bb ldr r3, [r7, #8]
|
|
801a242: 799b ldrb r3, [r3, #6]
|
|
801a244: 2b00 cmp r3, #0
|
|
801a246: d105 bne.n 801a254 <dhcp_create_msg+0x94>
|
|
#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND)
|
|
xid = LWIP_RAND();
|
|
801a248: f002 fd4e bl 801cce8 <rand>
|
|
801a24c: 4603 mov r3, r0
|
|
801a24e: 461a mov r2, r3
|
|
801a250: 4b45 ldr r3, [pc, #276] ; (801a368 <dhcp_create_msg+0x1a8>)
|
|
801a252: 601a str r2, [r3, #0]
|
|
#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
|
|
xid++;
|
|
#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */
|
|
}
|
|
dhcp->xid = xid;
|
|
801a254: 4b44 ldr r3, [pc, #272] ; (801a368 <dhcp_create_msg+0x1a8>)
|
|
801a256: 681a ldr r2, [r3, #0]
|
|
801a258: 68bb ldr r3, [r7, #8]
|
|
801a25a: 601a str r2, [r3, #0]
|
|
}
|
|
LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE,
|
|
("transaction id xid(%"X32_F")\n", xid));
|
|
|
|
msg_out = (struct dhcp_msg *)p_out->payload;
|
|
801a25c: 69bb ldr r3, [r7, #24]
|
|
801a25e: 685b ldr r3, [r3, #4]
|
|
801a260: 617b str r3, [r7, #20]
|
|
memset(msg_out, 0, sizeof(struct dhcp_msg));
|
|
801a262: f44f 729a mov.w r2, #308 ; 0x134
|
|
801a266: 2100 movs r1, #0
|
|
801a268: 6978 ldr r0, [r7, #20]
|
|
801a26a: f002 fd1c bl 801cca6 <memset>
|
|
|
|
msg_out->op = DHCP_BOOTREQUEST;
|
|
801a26e: 697b ldr r3, [r7, #20]
|
|
801a270: 2201 movs r2, #1
|
|
801a272: 701a strb r2, [r3, #0]
|
|
/* @todo: make link layer independent */
|
|
msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET;
|
|
801a274: 697b ldr r3, [r7, #20]
|
|
801a276: 2201 movs r2, #1
|
|
801a278: 705a strb r2, [r3, #1]
|
|
msg_out->hlen = netif->hwaddr_len;
|
|
801a27a: 68fb ldr r3, [r7, #12]
|
|
801a27c: f893 2030 ldrb.w r2, [r3, #48] ; 0x30
|
|
801a280: 697b ldr r3, [r7, #20]
|
|
801a282: 709a strb r2, [r3, #2]
|
|
msg_out->xid = lwip_htonl(dhcp->xid);
|
|
801a284: 68bb ldr r3, [r7, #8]
|
|
801a286: 681b ldr r3, [r3, #0]
|
|
801a288: 4618 mov r0, r3
|
|
801a28a: f7f6 fc46 bl 8010b1a <lwip_htonl>
|
|
801a28e: 4602 mov r2, r0
|
|
801a290: 697b ldr r3, [r7, #20]
|
|
801a292: 605a str r2, [r3, #4]
|
|
/* we don't need the broadcast flag since we can receive unicast traffic
|
|
before being fully configured! */
|
|
/* set ciaddr to netif->ip_addr based on message_type and state */
|
|
if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) ||
|
|
801a294: 79fb ldrb r3, [r7, #7]
|
|
801a296: 2b08 cmp r3, #8
|
|
801a298: d010 beq.n 801a2bc <dhcp_create_msg+0xfc>
|
|
801a29a: 79fb ldrb r3, [r7, #7]
|
|
801a29c: 2b04 cmp r3, #4
|
|
801a29e: d00d beq.n 801a2bc <dhcp_create_msg+0xfc>
|
|
801a2a0: 79fb ldrb r3, [r7, #7]
|
|
801a2a2: 2b07 cmp r3, #7
|
|
801a2a4: d00a beq.n 801a2bc <dhcp_create_msg+0xfc>
|
|
801a2a6: 79fb ldrb r3, [r7, #7]
|
|
801a2a8: 2b03 cmp r3, #3
|
|
801a2aa: d10c bne.n 801a2c6 <dhcp_create_msg+0x106>
|
|
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
|
|
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
|
|
801a2ac: 68bb ldr r3, [r7, #8]
|
|
801a2ae: 795b ldrb r3, [r3, #5]
|
|
((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */
|
|
801a2b0: 2b05 cmp r3, #5
|
|
801a2b2: d003 beq.n 801a2bc <dhcp_create_msg+0xfc>
|
|
((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) {
|
|
801a2b4: 68bb ldr r3, [r7, #8]
|
|
801a2b6: 795b ldrb r3, [r3, #5]
|
|
801a2b8: 2b04 cmp r3, #4
|
|
801a2ba: d104 bne.n 801a2c6 <dhcp_create_msg+0x106>
|
|
ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif));
|
|
801a2bc: 68fb ldr r3, [r7, #12]
|
|
801a2be: 3304 adds r3, #4
|
|
801a2c0: 681a ldr r2, [r3, #0]
|
|
801a2c2: 697b ldr r3, [r7, #20]
|
|
801a2c4: 60da str r2, [r3, #12]
|
|
}
|
|
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
|
|
801a2c6: 2300 movs r3, #0
|
|
801a2c8: 83fb strh r3, [r7, #30]
|
|
801a2ca: e00c b.n 801a2e6 <dhcp_create_msg+0x126>
|
|
/* copy netif hardware address (padded with zeroes through memset already) */
|
|
msg_out->chaddr[i] = netif->hwaddr[i];
|
|
801a2cc: 8bfa ldrh r2, [r7, #30]
|
|
801a2ce: 8bfb ldrh r3, [r7, #30]
|
|
801a2d0: 68f9 ldr r1, [r7, #12]
|
|
801a2d2: 440a add r2, r1
|
|
801a2d4: f892 102a ldrb.w r1, [r2, #42] ; 0x2a
|
|
801a2d8: 697a ldr r2, [r7, #20]
|
|
801a2da: 4413 add r3, r2
|
|
801a2dc: 460a mov r2, r1
|
|
801a2de: 771a strb r2, [r3, #28]
|
|
for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) {
|
|
801a2e0: 8bfb ldrh r3, [r7, #30]
|
|
801a2e2: 3301 adds r3, #1
|
|
801a2e4: 83fb strh r3, [r7, #30]
|
|
801a2e6: 8bfb ldrh r3, [r7, #30]
|
|
801a2e8: 2b05 cmp r3, #5
|
|
801a2ea: d9ef bls.n 801a2cc <dhcp_create_msg+0x10c>
|
|
}
|
|
msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE);
|
|
801a2ec: 697b ldr r3, [r7, #20]
|
|
801a2ee: 2200 movs r2, #0
|
|
801a2f0: f042 0263 orr.w r2, r2, #99 ; 0x63
|
|
801a2f4: f883 20ec strb.w r2, [r3, #236] ; 0xec
|
|
801a2f8: 2200 movs r2, #0
|
|
801a2fa: f062 027d orn r2, r2, #125 ; 0x7d
|
|
801a2fe: f883 20ed strb.w r2, [r3, #237] ; 0xed
|
|
801a302: 2200 movs r2, #0
|
|
801a304: f042 0253 orr.w r2, r2, #83 ; 0x53
|
|
801a308: f883 20ee strb.w r2, [r3, #238] ; 0xee
|
|
801a30c: 2200 movs r2, #0
|
|
801a30e: f042 0263 orr.w r2, r2, #99 ; 0x63
|
|
801a312: f883 20ef strb.w r2, [r3, #239] ; 0xef
|
|
/* Add option MESSAGE_TYPE */
|
|
options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN);
|
|
801a316: 697b ldr r3, [r7, #20]
|
|
801a318: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801a31c: 2301 movs r3, #1
|
|
801a31e: 2235 movs r2, #53 ; 0x35
|
|
801a320: 2000 movs r0, #0
|
|
801a322: f7ff fadd bl 80198e0 <dhcp_option>
|
|
801a326: 4603 mov r3, r0
|
|
801a328: 827b strh r3, [r7, #18]
|
|
options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type);
|
|
801a32a: 697b ldr r3, [r7, #20]
|
|
801a32c: f103 01f0 add.w r1, r3, #240 ; 0xf0
|
|
801a330: 79fa ldrb r2, [r7, #7]
|
|
801a332: 8a7b ldrh r3, [r7, #18]
|
|
801a334: 4618 mov r0, r3
|
|
801a336: f7ff fb07 bl 8019948 <dhcp_option_byte>
|
|
801a33a: 4603 mov r3, r0
|
|
801a33c: 827b strh r3, [r7, #18]
|
|
if (options_out_len) {
|
|
801a33e: 683b ldr r3, [r7, #0]
|
|
801a340: 2b00 cmp r3, #0
|
|
801a342: d002 beq.n 801a34a <dhcp_create_msg+0x18a>
|
|
*options_out_len = options_out_len_loc;
|
|
801a344: 683b ldr r3, [r7, #0]
|
|
801a346: 8a7a ldrh r2, [r7, #18]
|
|
801a348: 801a strh r2, [r3, #0]
|
|
}
|
|
return p_out;
|
|
801a34a: 69bb ldr r3, [r7, #24]
|
|
}
|
|
801a34c: 4618 mov r0, r3
|
|
801a34e: 3720 adds r7, #32
|
|
801a350: 46bd mov sp, r7
|
|
801a352: bd80 pop {r7, pc}
|
|
801a354: 08020398 .word 0x08020398
|
|
801a358: 080206b8 .word 0x080206b8
|
|
801a35c: 080203f8 .word 0x080203f8
|
|
801a360: 080206d8 .word 0x080206d8
|
|
801a364: 080206f8 .word 0x080206f8
|
|
801a368: 20008774 .word 0x20008774
|
|
|
|
0801a36c <dhcp_option_trailer>:
|
|
* Adds the END option to the DHCP message, and if
|
|
* necessary, up to three padding bytes.
|
|
*/
|
|
static void
|
|
dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out)
|
|
{
|
|
801a36c: b580 push {r7, lr}
|
|
801a36e: b084 sub sp, #16
|
|
801a370: af00 add r7, sp, #0
|
|
801a372: 4603 mov r3, r0
|
|
801a374: 60b9 str r1, [r7, #8]
|
|
801a376: 607a str r2, [r7, #4]
|
|
801a378: 81fb strh r3, [r7, #14]
|
|
options[options_out_len++] = DHCP_OPTION_END;
|
|
801a37a: 89fb ldrh r3, [r7, #14]
|
|
801a37c: 1c5a adds r2, r3, #1
|
|
801a37e: 81fa strh r2, [r7, #14]
|
|
801a380: 461a mov r2, r3
|
|
801a382: 68bb ldr r3, [r7, #8]
|
|
801a384: 4413 add r3, r2
|
|
801a386: 22ff movs r2, #255 ; 0xff
|
|
801a388: 701a strb r2, [r3, #0]
|
|
/* packet is too small, or not 4 byte aligned? */
|
|
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
|
|
801a38a: e007 b.n 801a39c <dhcp_option_trailer+0x30>
|
|
(options_out_len < DHCP_OPTIONS_LEN)) {
|
|
/* add a fill/padding byte */
|
|
options[options_out_len++] = 0;
|
|
801a38c: 89fb ldrh r3, [r7, #14]
|
|
801a38e: 1c5a adds r2, r3, #1
|
|
801a390: 81fa strh r2, [r7, #14]
|
|
801a392: 461a mov r2, r3
|
|
801a394: 68bb ldr r3, [r7, #8]
|
|
801a396: 4413 add r3, r2
|
|
801a398: 2200 movs r2, #0
|
|
801a39a: 701a strb r2, [r3, #0]
|
|
while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) &&
|
|
801a39c: 89fb ldrh r3, [r7, #14]
|
|
801a39e: 2b43 cmp r3, #67 ; 0x43
|
|
801a3a0: d904 bls.n 801a3ac <dhcp_option_trailer+0x40>
|
|
801a3a2: 89fb ldrh r3, [r7, #14]
|
|
801a3a4: f003 0303 and.w r3, r3, #3
|
|
801a3a8: 2b00 cmp r3, #0
|
|
801a3aa: d002 beq.n 801a3b2 <dhcp_option_trailer+0x46>
|
|
801a3ac: 89fb ldrh r3, [r7, #14]
|
|
801a3ae: 2b43 cmp r3, #67 ; 0x43
|
|
801a3b0: d9ec bls.n 801a38c <dhcp_option_trailer+0x20>
|
|
}
|
|
/* shrink the pbuf to the actual content length */
|
|
pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len));
|
|
801a3b2: 89fb ldrh r3, [r7, #14]
|
|
801a3b4: 33f0 adds r3, #240 ; 0xf0
|
|
801a3b6: b29b uxth r3, r3
|
|
801a3b8: 4619 mov r1, r3
|
|
801a3ba: 6878 ldr r0, [r7, #4]
|
|
801a3bc: f7f7 fdc6 bl 8011f4c <pbuf_realloc>
|
|
}
|
|
801a3c0: bf00 nop
|
|
801a3c2: 3710 adds r7, #16
|
|
801a3c4: 46bd mov sp, r7
|
|
801a3c6: bd80 pop {r7, pc}
|
|
|
|
0801a3c8 <dhcp_supplied_address>:
|
|
* @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING),
|
|
* 0 otherwise
|
|
*/
|
|
u8_t
|
|
dhcp_supplied_address(const struct netif *netif)
|
|
{
|
|
801a3c8: b480 push {r7}
|
|
801a3ca: b085 sub sp, #20
|
|
801a3cc: af00 add r7, sp, #0
|
|
801a3ce: 6078 str r0, [r7, #4]
|
|
if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) {
|
|
801a3d0: 687b ldr r3, [r7, #4]
|
|
801a3d2: 2b00 cmp r3, #0
|
|
801a3d4: d017 beq.n 801a406 <dhcp_supplied_address+0x3e>
|
|
801a3d6: 687b ldr r3, [r7, #4]
|
|
801a3d8: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801a3da: 2b00 cmp r3, #0
|
|
801a3dc: d013 beq.n 801a406 <dhcp_supplied_address+0x3e>
|
|
struct dhcp *dhcp = netif_dhcp_data(netif);
|
|
801a3de: 687b ldr r3, [r7, #4]
|
|
801a3e0: 6a5b ldr r3, [r3, #36] ; 0x24
|
|
801a3e2: 60fb str r3, [r7, #12]
|
|
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
|
|
801a3e4: 68fb ldr r3, [r7, #12]
|
|
801a3e6: 795b ldrb r3, [r3, #5]
|
|
801a3e8: 2b0a cmp r3, #10
|
|
801a3ea: d007 beq.n 801a3fc <dhcp_supplied_address+0x34>
|
|
801a3ec: 68fb ldr r3, [r7, #12]
|
|
801a3ee: 795b ldrb r3, [r3, #5]
|
|
801a3f0: 2b05 cmp r3, #5
|
|
801a3f2: d003 beq.n 801a3fc <dhcp_supplied_address+0x34>
|
|
(dhcp->state == DHCP_STATE_REBINDING);
|
|
801a3f4: 68fb ldr r3, [r7, #12]
|
|
801a3f6: 795b ldrb r3, [r3, #5]
|
|
return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) ||
|
|
801a3f8: 2b04 cmp r3, #4
|
|
801a3fa: d101 bne.n 801a400 <dhcp_supplied_address+0x38>
|
|
801a3fc: 2301 movs r3, #1
|
|
801a3fe: e000 b.n 801a402 <dhcp_supplied_address+0x3a>
|
|
801a400: 2300 movs r3, #0
|
|
801a402: b2db uxtb r3, r3
|
|
801a404: e000 b.n 801a408 <dhcp_supplied_address+0x40>
|
|
}
|
|
return 0;
|
|
801a406: 2300 movs r3, #0
|
|
}
|
|
801a408: 4618 mov r0, r3
|
|
801a40a: 3714 adds r7, #20
|
|
801a40c: 46bd mov sp, r7
|
|
801a40e: f85d 7b04 ldr.w r7, [sp], #4
|
|
801a412: 4770 bx lr
|
|
|
|
0801a414 <etharp_free_entry>:
|
|
#endif /* ARP_QUEUEING */
|
|
|
|
/** Clean up ARP table entries */
|
|
static void
|
|
etharp_free_entry(int i)
|
|
{
|
|
801a414: b580 push {r7, lr}
|
|
801a416: b082 sub sp, #8
|
|
801a418: af00 add r7, sp, #0
|
|
801a41a: 6078 str r0, [r7, #4]
|
|
/* remove from SNMP ARP index tree */
|
|
mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr);
|
|
/* and empty packet queue */
|
|
if (arp_table[i].q != NULL) {
|
|
801a41c: 4915 ldr r1, [pc, #84] ; (801a474 <etharp_free_entry+0x60>)
|
|
801a41e: 687a ldr r2, [r7, #4]
|
|
801a420: 4613 mov r3, r2
|
|
801a422: 005b lsls r3, r3, #1
|
|
801a424: 4413 add r3, r2
|
|
801a426: 00db lsls r3, r3, #3
|
|
801a428: 440b add r3, r1
|
|
801a42a: 681b ldr r3, [r3, #0]
|
|
801a42c: 2b00 cmp r3, #0
|
|
801a42e: d013 beq.n 801a458 <etharp_free_entry+0x44>
|
|
/* remove all queued packets */
|
|
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q)));
|
|
free_etharp_q(arp_table[i].q);
|
|
801a430: 4910 ldr r1, [pc, #64] ; (801a474 <etharp_free_entry+0x60>)
|
|
801a432: 687a ldr r2, [r7, #4]
|
|
801a434: 4613 mov r3, r2
|
|
801a436: 005b lsls r3, r3, #1
|
|
801a438: 4413 add r3, r2
|
|
801a43a: 00db lsls r3, r3, #3
|
|
801a43c: 440b add r3, r1
|
|
801a43e: 681b ldr r3, [r3, #0]
|
|
801a440: 4618 mov r0, r3
|
|
801a442: f7f7 ff09 bl 8012258 <pbuf_free>
|
|
arp_table[i].q = NULL;
|
|
801a446: 490b ldr r1, [pc, #44] ; (801a474 <etharp_free_entry+0x60>)
|
|
801a448: 687a ldr r2, [r7, #4]
|
|
801a44a: 4613 mov r3, r2
|
|
801a44c: 005b lsls r3, r3, #1
|
|
801a44e: 4413 add r3, r2
|
|
801a450: 00db lsls r3, r3, #3
|
|
801a452: 440b add r3, r1
|
|
801a454: 2200 movs r2, #0
|
|
801a456: 601a str r2, [r3, #0]
|
|
}
|
|
/* recycle entry for re-use */
|
|
arp_table[i].state = ETHARP_STATE_EMPTY;
|
|
801a458: 4906 ldr r1, [pc, #24] ; (801a474 <etharp_free_entry+0x60>)
|
|
801a45a: 687a ldr r2, [r7, #4]
|
|
801a45c: 4613 mov r3, r2
|
|
801a45e: 005b lsls r3, r3, #1
|
|
801a460: 4413 add r3, r2
|
|
801a462: 00db lsls r3, r3, #3
|
|
801a464: 440b add r3, r1
|
|
801a466: 3314 adds r3, #20
|
|
801a468: 2200 movs r2, #0
|
|
801a46a: 701a strb r2, [r3, #0]
|
|
arp_table[i].ctime = 0;
|
|
arp_table[i].netif = NULL;
|
|
ip4_addr_set_zero(&arp_table[i].ipaddr);
|
|
arp_table[i].ethaddr = ethzero;
|
|
#endif /* LWIP_DEBUG */
|
|
}
|
|
801a46c: bf00 nop
|
|
801a46e: 3708 adds r7, #8
|
|
801a470: 46bd mov sp, r7
|
|
801a472: bd80 pop {r7, pc}
|
|
801a474: 20008778 .word 0x20008778
|
|
|
|
0801a478 <etharp_tmr>:
|
|
* This function should be called every ARP_TMR_INTERVAL milliseconds (1 second),
|
|
* in order to expire entries in the ARP table.
|
|
*/
|
|
void
|
|
etharp_tmr(void)
|
|
{
|
|
801a478: b580 push {r7, lr}
|
|
801a47a: b082 sub sp, #8
|
|
801a47c: af00 add r7, sp, #0
|
|
int i;
|
|
|
|
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n"));
|
|
/* remove expired entries from the ARP table */
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801a47e: 2300 movs r3, #0
|
|
801a480: 607b str r3, [r7, #4]
|
|
801a482: e096 b.n 801a5b2 <etharp_tmr+0x13a>
|
|
u8_t state = arp_table[i].state;
|
|
801a484: 494f ldr r1, [pc, #316] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a486: 687a ldr r2, [r7, #4]
|
|
801a488: 4613 mov r3, r2
|
|
801a48a: 005b lsls r3, r3, #1
|
|
801a48c: 4413 add r3, r2
|
|
801a48e: 00db lsls r3, r3, #3
|
|
801a490: 440b add r3, r1
|
|
801a492: 3314 adds r3, #20
|
|
801a494: 781b ldrb r3, [r3, #0]
|
|
801a496: 70fb strb r3, [r7, #3]
|
|
if (state != ETHARP_STATE_EMPTY
|
|
801a498: 78fb ldrb r3, [r7, #3]
|
|
801a49a: 2b00 cmp r3, #0
|
|
801a49c: f000 8086 beq.w 801a5ac <etharp_tmr+0x134>
|
|
#if ETHARP_SUPPORT_STATIC_ENTRIES
|
|
&& (state != ETHARP_STATE_STATIC)
|
|
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
|
|
) {
|
|
arp_table[i].ctime++;
|
|
801a4a0: 4948 ldr r1, [pc, #288] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a4a2: 687a ldr r2, [r7, #4]
|
|
801a4a4: 4613 mov r3, r2
|
|
801a4a6: 005b lsls r3, r3, #1
|
|
801a4a8: 4413 add r3, r2
|
|
801a4aa: 00db lsls r3, r3, #3
|
|
801a4ac: 440b add r3, r1
|
|
801a4ae: 3312 adds r3, #18
|
|
801a4b0: 881b ldrh r3, [r3, #0]
|
|
801a4b2: 3301 adds r3, #1
|
|
801a4b4: b298 uxth r0, r3
|
|
801a4b6: 4943 ldr r1, [pc, #268] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a4b8: 687a ldr r2, [r7, #4]
|
|
801a4ba: 4613 mov r3, r2
|
|
801a4bc: 005b lsls r3, r3, #1
|
|
801a4be: 4413 add r3, r2
|
|
801a4c0: 00db lsls r3, r3, #3
|
|
801a4c2: 440b add r3, r1
|
|
801a4c4: 3312 adds r3, #18
|
|
801a4c6: 4602 mov r2, r0
|
|
801a4c8: 801a strh r2, [r3, #0]
|
|
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
|
|
801a4ca: 493e ldr r1, [pc, #248] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a4cc: 687a ldr r2, [r7, #4]
|
|
801a4ce: 4613 mov r3, r2
|
|
801a4d0: 005b lsls r3, r3, #1
|
|
801a4d2: 4413 add r3, r2
|
|
801a4d4: 00db lsls r3, r3, #3
|
|
801a4d6: 440b add r3, r1
|
|
801a4d8: 3312 adds r3, #18
|
|
801a4da: 881b ldrh r3, [r3, #0]
|
|
801a4dc: f5b3 7f96 cmp.w r3, #300 ; 0x12c
|
|
801a4e0: d215 bcs.n 801a50e <etharp_tmr+0x96>
|
|
((arp_table[i].state == ETHARP_STATE_PENDING) &&
|
|
801a4e2: 4938 ldr r1, [pc, #224] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a4e4: 687a ldr r2, [r7, #4]
|
|
801a4e6: 4613 mov r3, r2
|
|
801a4e8: 005b lsls r3, r3, #1
|
|
801a4ea: 4413 add r3, r2
|
|
801a4ec: 00db lsls r3, r3, #3
|
|
801a4ee: 440b add r3, r1
|
|
801a4f0: 3314 adds r3, #20
|
|
801a4f2: 781b ldrb r3, [r3, #0]
|
|
if ((arp_table[i].ctime >= ARP_MAXAGE) ||
|
|
801a4f4: 2b01 cmp r3, #1
|
|
801a4f6: d10e bne.n 801a516 <etharp_tmr+0x9e>
|
|
(arp_table[i].ctime >= ARP_MAXPENDING))) {
|
|
801a4f8: 4932 ldr r1, [pc, #200] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a4fa: 687a ldr r2, [r7, #4]
|
|
801a4fc: 4613 mov r3, r2
|
|
801a4fe: 005b lsls r3, r3, #1
|
|
801a500: 4413 add r3, r2
|
|
801a502: 00db lsls r3, r3, #3
|
|
801a504: 440b add r3, r1
|
|
801a506: 3312 adds r3, #18
|
|
801a508: 881b ldrh r3, [r3, #0]
|
|
((arp_table[i].state == ETHARP_STATE_PENDING) &&
|
|
801a50a: 2b04 cmp r3, #4
|
|
801a50c: d903 bls.n 801a516 <etharp_tmr+0x9e>
|
|
/* pending or stable entry has become old! */
|
|
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n",
|
|
arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i));
|
|
/* clean up entries that have just been expired */
|
|
etharp_free_entry(i);
|
|
801a50e: 6878 ldr r0, [r7, #4]
|
|
801a510: f7ff ff80 bl 801a414 <etharp_free_entry>
|
|
801a514: e04a b.n 801a5ac <etharp_tmr+0x134>
|
|
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) {
|
|
801a516: 492b ldr r1, [pc, #172] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a518: 687a ldr r2, [r7, #4]
|
|
801a51a: 4613 mov r3, r2
|
|
801a51c: 005b lsls r3, r3, #1
|
|
801a51e: 4413 add r3, r2
|
|
801a520: 00db lsls r3, r3, #3
|
|
801a522: 440b add r3, r1
|
|
801a524: 3314 adds r3, #20
|
|
801a526: 781b ldrb r3, [r3, #0]
|
|
801a528: 2b03 cmp r3, #3
|
|
801a52a: d10a bne.n 801a542 <etharp_tmr+0xca>
|
|
/* Don't send more than one request every 2 seconds. */
|
|
arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2;
|
|
801a52c: 4925 ldr r1, [pc, #148] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a52e: 687a ldr r2, [r7, #4]
|
|
801a530: 4613 mov r3, r2
|
|
801a532: 005b lsls r3, r3, #1
|
|
801a534: 4413 add r3, r2
|
|
801a536: 00db lsls r3, r3, #3
|
|
801a538: 440b add r3, r1
|
|
801a53a: 3314 adds r3, #20
|
|
801a53c: 2204 movs r2, #4
|
|
801a53e: 701a strb r2, [r3, #0]
|
|
801a540: e034 b.n 801a5ac <etharp_tmr+0x134>
|
|
} else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) {
|
|
801a542: 4920 ldr r1, [pc, #128] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a544: 687a ldr r2, [r7, #4]
|
|
801a546: 4613 mov r3, r2
|
|
801a548: 005b lsls r3, r3, #1
|
|
801a54a: 4413 add r3, r2
|
|
801a54c: 00db lsls r3, r3, #3
|
|
801a54e: 440b add r3, r1
|
|
801a550: 3314 adds r3, #20
|
|
801a552: 781b ldrb r3, [r3, #0]
|
|
801a554: 2b04 cmp r3, #4
|
|
801a556: d10a bne.n 801a56e <etharp_tmr+0xf6>
|
|
/* Reset state to stable, so that the next transmitted packet will
|
|
re-send an ARP request. */
|
|
arp_table[i].state = ETHARP_STATE_STABLE;
|
|
801a558: 491a ldr r1, [pc, #104] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a55a: 687a ldr r2, [r7, #4]
|
|
801a55c: 4613 mov r3, r2
|
|
801a55e: 005b lsls r3, r3, #1
|
|
801a560: 4413 add r3, r2
|
|
801a562: 00db lsls r3, r3, #3
|
|
801a564: 440b add r3, r1
|
|
801a566: 3314 adds r3, #20
|
|
801a568: 2202 movs r2, #2
|
|
801a56a: 701a strb r2, [r3, #0]
|
|
801a56c: e01e b.n 801a5ac <etharp_tmr+0x134>
|
|
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
|
|
801a56e: 4915 ldr r1, [pc, #84] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a570: 687a ldr r2, [r7, #4]
|
|
801a572: 4613 mov r3, r2
|
|
801a574: 005b lsls r3, r3, #1
|
|
801a576: 4413 add r3, r2
|
|
801a578: 00db lsls r3, r3, #3
|
|
801a57a: 440b add r3, r1
|
|
801a57c: 3314 adds r3, #20
|
|
801a57e: 781b ldrb r3, [r3, #0]
|
|
801a580: 2b01 cmp r3, #1
|
|
801a582: d113 bne.n 801a5ac <etharp_tmr+0x134>
|
|
/* still pending, resend an ARP query */
|
|
etharp_request(arp_table[i].netif, &arp_table[i].ipaddr);
|
|
801a584: 490f ldr r1, [pc, #60] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a586: 687a ldr r2, [r7, #4]
|
|
801a588: 4613 mov r3, r2
|
|
801a58a: 005b lsls r3, r3, #1
|
|
801a58c: 4413 add r3, r2
|
|
801a58e: 00db lsls r3, r3, #3
|
|
801a590: 440b add r3, r1
|
|
801a592: 3308 adds r3, #8
|
|
801a594: 6818 ldr r0, [r3, #0]
|
|
801a596: 687a ldr r2, [r7, #4]
|
|
801a598: 4613 mov r3, r2
|
|
801a59a: 005b lsls r3, r3, #1
|
|
801a59c: 4413 add r3, r2
|
|
801a59e: 00db lsls r3, r3, #3
|
|
801a5a0: 4a08 ldr r2, [pc, #32] ; (801a5c4 <etharp_tmr+0x14c>)
|
|
801a5a2: 4413 add r3, r2
|
|
801a5a4: 3304 adds r3, #4
|
|
801a5a6: 4619 mov r1, r3
|
|
801a5a8: f000 fe72 bl 801b290 <etharp_request>
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801a5ac: 687b ldr r3, [r7, #4]
|
|
801a5ae: 3301 adds r3, #1
|
|
801a5b0: 607b str r3, [r7, #4]
|
|
801a5b2: 687b ldr r3, [r7, #4]
|
|
801a5b4: 2b09 cmp r3, #9
|
|
801a5b6: f77f af65 ble.w 801a484 <etharp_tmr+0xc>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
801a5ba: bf00 nop
|
|
801a5bc: 3708 adds r7, #8
|
|
801a5be: 46bd mov sp, r7
|
|
801a5c0: bd80 pop {r7, pc}
|
|
801a5c2: bf00 nop
|
|
801a5c4: 20008778 .word 0x20008778
|
|
|
|
0801a5c8 <etharp_find_entry>:
|
|
* @return The ARP entry index that matched or is created, ERR_MEM if no
|
|
* entry is found or could be recycled.
|
|
*/
|
|
static s16_t
|
|
etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif)
|
|
{
|
|
801a5c8: b580 push {r7, lr}
|
|
801a5ca: b08a sub sp, #40 ; 0x28
|
|
801a5cc: af00 add r7, sp, #0
|
|
801a5ce: 60f8 str r0, [r7, #12]
|
|
801a5d0: 460b mov r3, r1
|
|
801a5d2: 607a str r2, [r7, #4]
|
|
801a5d4: 72fb strb r3, [r7, #11]
|
|
s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE;
|
|
801a5d6: 230a movs r3, #10
|
|
801a5d8: 84fb strh r3, [r7, #38] ; 0x26
|
|
801a5da: 230a movs r3, #10
|
|
801a5dc: 84bb strh r3, [r7, #36] ; 0x24
|
|
s16_t empty = ARP_TABLE_SIZE;
|
|
801a5de: 230a movs r3, #10
|
|
801a5e0: 847b strh r3, [r7, #34] ; 0x22
|
|
s16_t i = 0;
|
|
801a5e2: 2300 movs r3, #0
|
|
801a5e4: 843b strh r3, [r7, #32]
|
|
/* oldest entry with packets on queue */
|
|
s16_t old_queue = ARP_TABLE_SIZE;
|
|
801a5e6: 230a movs r3, #10
|
|
801a5e8: 83fb strh r3, [r7, #30]
|
|
/* its age */
|
|
u16_t age_queue = 0, age_pending = 0, age_stable = 0;
|
|
801a5ea: 2300 movs r3, #0
|
|
801a5ec: 83bb strh r3, [r7, #28]
|
|
801a5ee: 2300 movs r3, #0
|
|
801a5f0: 837b strh r3, [r7, #26]
|
|
801a5f2: 2300 movs r3, #0
|
|
801a5f4: 833b strh r3, [r7, #24]
|
|
* 4) remember the oldest pending entry with queued packets (if any)
|
|
* 5) search for a matching IP entry, either pending or stable
|
|
* until 5 matches, or all entries are searched for.
|
|
*/
|
|
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801a5f6: 2300 movs r3, #0
|
|
801a5f8: 843b strh r3, [r7, #32]
|
|
801a5fa: e0ae b.n 801a75a <etharp_find_entry+0x192>
|
|
u8_t state = arp_table[i].state;
|
|
801a5fc: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a600: 49a6 ldr r1, [pc, #664] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a602: 4613 mov r3, r2
|
|
801a604: 005b lsls r3, r3, #1
|
|
801a606: 4413 add r3, r2
|
|
801a608: 00db lsls r3, r3, #3
|
|
801a60a: 440b add r3, r1
|
|
801a60c: 3314 adds r3, #20
|
|
801a60e: 781b ldrb r3, [r3, #0]
|
|
801a610: 75fb strb r3, [r7, #23]
|
|
/* no empty entry found yet and now we do find one? */
|
|
if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) {
|
|
801a612: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
|
|
801a616: 2b0a cmp r3, #10
|
|
801a618: d105 bne.n 801a626 <etharp_find_entry+0x5e>
|
|
801a61a: 7dfb ldrb r3, [r7, #23]
|
|
801a61c: 2b00 cmp r3, #0
|
|
801a61e: d102 bne.n 801a626 <etharp_find_entry+0x5e>
|
|
LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i));
|
|
/* remember first empty entry */
|
|
empty = i;
|
|
801a620: 8c3b ldrh r3, [r7, #32]
|
|
801a622: 847b strh r3, [r7, #34] ; 0x22
|
|
801a624: e095 b.n 801a752 <etharp_find_entry+0x18a>
|
|
} else if (state != ETHARP_STATE_EMPTY) {
|
|
801a626: 7dfb ldrb r3, [r7, #23]
|
|
801a628: 2b00 cmp r3, #0
|
|
801a62a: f000 8092 beq.w 801a752 <etharp_find_entry+0x18a>
|
|
LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE",
|
|
801a62e: 7dfb ldrb r3, [r7, #23]
|
|
801a630: 2b01 cmp r3, #1
|
|
801a632: d009 beq.n 801a648 <etharp_find_entry+0x80>
|
|
801a634: 7dfb ldrb r3, [r7, #23]
|
|
801a636: 2b01 cmp r3, #1
|
|
801a638: d806 bhi.n 801a648 <etharp_find_entry+0x80>
|
|
801a63a: 4b99 ldr r3, [pc, #612] ; (801a8a0 <etharp_find_entry+0x2d8>)
|
|
801a63c: f44f 7292 mov.w r2, #292 ; 0x124
|
|
801a640: 4998 ldr r1, [pc, #608] ; (801a8a4 <etharp_find_entry+0x2dc>)
|
|
801a642: 4899 ldr r0, [pc, #612] ; (801a8a8 <etharp_find_entry+0x2e0>)
|
|
801a644: f002 fb38 bl 801ccb8 <iprintf>
|
|
state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE);
|
|
/* if given, does IP address match IP address in ARP entry? */
|
|
if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr)
|
|
801a648: 68fb ldr r3, [r7, #12]
|
|
801a64a: 2b00 cmp r3, #0
|
|
801a64c: d020 beq.n 801a690 <etharp_find_entry+0xc8>
|
|
801a64e: 68fb ldr r3, [r7, #12]
|
|
801a650: 6819 ldr r1, [r3, #0]
|
|
801a652: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a656: 4891 ldr r0, [pc, #580] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a658: 4613 mov r3, r2
|
|
801a65a: 005b lsls r3, r3, #1
|
|
801a65c: 4413 add r3, r2
|
|
801a65e: 00db lsls r3, r3, #3
|
|
801a660: 4403 add r3, r0
|
|
801a662: 3304 adds r3, #4
|
|
801a664: 681b ldr r3, [r3, #0]
|
|
801a666: 4299 cmp r1, r3
|
|
801a668: d112 bne.n 801a690 <etharp_find_entry+0xc8>
|
|
#if ETHARP_TABLE_MATCH_NETIF
|
|
&& ((netif == NULL) || (netif == arp_table[i].netif))
|
|
801a66a: 687b ldr r3, [r7, #4]
|
|
801a66c: 2b00 cmp r3, #0
|
|
801a66e: d00c beq.n 801a68a <etharp_find_entry+0xc2>
|
|
801a670: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a674: 4989 ldr r1, [pc, #548] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a676: 4613 mov r3, r2
|
|
801a678: 005b lsls r3, r3, #1
|
|
801a67a: 4413 add r3, r2
|
|
801a67c: 00db lsls r3, r3, #3
|
|
801a67e: 440b add r3, r1
|
|
801a680: 3308 adds r3, #8
|
|
801a682: 681b ldr r3, [r3, #0]
|
|
801a684: 687a ldr r2, [r7, #4]
|
|
801a686: 429a cmp r2, r3
|
|
801a688: d102 bne.n 801a690 <etharp_find_entry+0xc8>
|
|
#endif /* ETHARP_TABLE_MATCH_NETIF */
|
|
) {
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i));
|
|
/* found exact IP address match, simply bail out */
|
|
return i;
|
|
801a68a: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
801a68e: e100 b.n 801a892 <etharp_find_entry+0x2ca>
|
|
}
|
|
/* pending entry? */
|
|
if (state == ETHARP_STATE_PENDING) {
|
|
801a690: 7dfb ldrb r3, [r7, #23]
|
|
801a692: 2b01 cmp r3, #1
|
|
801a694: d140 bne.n 801a718 <etharp_find_entry+0x150>
|
|
/* pending with queued packets? */
|
|
if (arp_table[i].q != NULL) {
|
|
801a696: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a69a: 4980 ldr r1, [pc, #512] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a69c: 4613 mov r3, r2
|
|
801a69e: 005b lsls r3, r3, #1
|
|
801a6a0: 4413 add r3, r2
|
|
801a6a2: 00db lsls r3, r3, #3
|
|
801a6a4: 440b add r3, r1
|
|
801a6a6: 681b ldr r3, [r3, #0]
|
|
801a6a8: 2b00 cmp r3, #0
|
|
801a6aa: d01a beq.n 801a6e2 <etharp_find_entry+0x11a>
|
|
if (arp_table[i].ctime >= age_queue) {
|
|
801a6ac: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a6b0: 497a ldr r1, [pc, #488] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a6b2: 4613 mov r3, r2
|
|
801a6b4: 005b lsls r3, r3, #1
|
|
801a6b6: 4413 add r3, r2
|
|
801a6b8: 00db lsls r3, r3, #3
|
|
801a6ba: 440b add r3, r1
|
|
801a6bc: 3312 adds r3, #18
|
|
801a6be: 881b ldrh r3, [r3, #0]
|
|
801a6c0: 8bba ldrh r2, [r7, #28]
|
|
801a6c2: 429a cmp r2, r3
|
|
801a6c4: d845 bhi.n 801a752 <etharp_find_entry+0x18a>
|
|
old_queue = i;
|
|
801a6c6: 8c3b ldrh r3, [r7, #32]
|
|
801a6c8: 83fb strh r3, [r7, #30]
|
|
age_queue = arp_table[i].ctime;
|
|
801a6ca: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a6ce: 4973 ldr r1, [pc, #460] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a6d0: 4613 mov r3, r2
|
|
801a6d2: 005b lsls r3, r3, #1
|
|
801a6d4: 4413 add r3, r2
|
|
801a6d6: 00db lsls r3, r3, #3
|
|
801a6d8: 440b add r3, r1
|
|
801a6da: 3312 adds r3, #18
|
|
801a6dc: 881b ldrh r3, [r3, #0]
|
|
801a6de: 83bb strh r3, [r7, #28]
|
|
801a6e0: e037 b.n 801a752 <etharp_find_entry+0x18a>
|
|
}
|
|
} else
|
|
/* pending without queued packets? */
|
|
{
|
|
if (arp_table[i].ctime >= age_pending) {
|
|
801a6e2: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a6e6: 496d ldr r1, [pc, #436] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a6e8: 4613 mov r3, r2
|
|
801a6ea: 005b lsls r3, r3, #1
|
|
801a6ec: 4413 add r3, r2
|
|
801a6ee: 00db lsls r3, r3, #3
|
|
801a6f0: 440b add r3, r1
|
|
801a6f2: 3312 adds r3, #18
|
|
801a6f4: 881b ldrh r3, [r3, #0]
|
|
801a6f6: 8b7a ldrh r2, [r7, #26]
|
|
801a6f8: 429a cmp r2, r3
|
|
801a6fa: d82a bhi.n 801a752 <etharp_find_entry+0x18a>
|
|
old_pending = i;
|
|
801a6fc: 8c3b ldrh r3, [r7, #32]
|
|
801a6fe: 84fb strh r3, [r7, #38] ; 0x26
|
|
age_pending = arp_table[i].ctime;
|
|
801a700: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a704: 4965 ldr r1, [pc, #404] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a706: 4613 mov r3, r2
|
|
801a708: 005b lsls r3, r3, #1
|
|
801a70a: 4413 add r3, r2
|
|
801a70c: 00db lsls r3, r3, #3
|
|
801a70e: 440b add r3, r1
|
|
801a710: 3312 adds r3, #18
|
|
801a712: 881b ldrh r3, [r3, #0]
|
|
801a714: 837b strh r3, [r7, #26]
|
|
801a716: e01c b.n 801a752 <etharp_find_entry+0x18a>
|
|
}
|
|
}
|
|
/* stable entry? */
|
|
} else if (state >= ETHARP_STATE_STABLE) {
|
|
801a718: 7dfb ldrb r3, [r7, #23]
|
|
801a71a: 2b01 cmp r3, #1
|
|
801a71c: d919 bls.n 801a752 <etharp_find_entry+0x18a>
|
|
/* don't record old_stable for static entries since they never expire */
|
|
if (state < ETHARP_STATE_STATIC)
|
|
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
|
|
{
|
|
/* remember entry with oldest stable entry in oldest, its age in maxtime */
|
|
if (arp_table[i].ctime >= age_stable) {
|
|
801a71e: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a722: 495e ldr r1, [pc, #376] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a724: 4613 mov r3, r2
|
|
801a726: 005b lsls r3, r3, #1
|
|
801a728: 4413 add r3, r2
|
|
801a72a: 00db lsls r3, r3, #3
|
|
801a72c: 440b add r3, r1
|
|
801a72e: 3312 adds r3, #18
|
|
801a730: 881b ldrh r3, [r3, #0]
|
|
801a732: 8b3a ldrh r2, [r7, #24]
|
|
801a734: 429a cmp r2, r3
|
|
801a736: d80c bhi.n 801a752 <etharp_find_entry+0x18a>
|
|
old_stable = i;
|
|
801a738: 8c3b ldrh r3, [r7, #32]
|
|
801a73a: 84bb strh r3, [r7, #36] ; 0x24
|
|
age_stable = arp_table[i].ctime;
|
|
801a73c: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a740: 4956 ldr r1, [pc, #344] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a742: 4613 mov r3, r2
|
|
801a744: 005b lsls r3, r3, #1
|
|
801a746: 4413 add r3, r2
|
|
801a748: 00db lsls r3, r3, #3
|
|
801a74a: 440b add r3, r1
|
|
801a74c: 3312 adds r3, #18
|
|
801a74e: 881b ldrh r3, [r3, #0]
|
|
801a750: 833b strh r3, [r7, #24]
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801a752: 8c3b ldrh r3, [r7, #32]
|
|
801a754: 3301 adds r3, #1
|
|
801a756: b29b uxth r3, r3
|
|
801a758: 843b strh r3, [r7, #32]
|
|
801a75a: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
801a75e: 2b09 cmp r3, #9
|
|
801a760: f77f af4c ble.w 801a5fc <etharp_find_entry+0x34>
|
|
}
|
|
}
|
|
/* { we have no match } => try to create a new entry */
|
|
|
|
/* don't create new entry, only search? */
|
|
if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) ||
|
|
801a764: 7afb ldrb r3, [r7, #11]
|
|
801a766: f003 0302 and.w r3, r3, #2
|
|
801a76a: 2b00 cmp r3, #0
|
|
801a76c: d108 bne.n 801a780 <etharp_find_entry+0x1b8>
|
|
801a76e: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
|
|
801a772: 2b0a cmp r3, #10
|
|
801a774: d107 bne.n 801a786 <etharp_find_entry+0x1be>
|
|
/* or no empty entry found and not allowed to recycle? */
|
|
((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) {
|
|
801a776: 7afb ldrb r3, [r7, #11]
|
|
801a778: f003 0301 and.w r3, r3, #1
|
|
801a77c: 2b00 cmp r3, #0
|
|
801a77e: d102 bne.n 801a786 <etharp_find_entry+0x1be>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n"));
|
|
return (s16_t)ERR_MEM;
|
|
801a780: f04f 33ff mov.w r3, #4294967295
|
|
801a784: e085 b.n 801a892 <etharp_find_entry+0x2ca>
|
|
*
|
|
* { ETHARP_FLAG_TRY_HARD is set at this point }
|
|
*/
|
|
|
|
/* 1) empty entry available? */
|
|
if (empty < ARP_TABLE_SIZE) {
|
|
801a786: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22
|
|
801a78a: 2b09 cmp r3, #9
|
|
801a78c: dc02 bgt.n 801a794 <etharp_find_entry+0x1cc>
|
|
i = empty;
|
|
801a78e: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801a790: 843b strh r3, [r7, #32]
|
|
801a792: e039 b.n 801a808 <etharp_find_entry+0x240>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i));
|
|
} else {
|
|
/* 2) found recyclable stable entry? */
|
|
if (old_stable < ARP_TABLE_SIZE) {
|
|
801a794: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24
|
|
801a798: 2b09 cmp r3, #9
|
|
801a79a: dc14 bgt.n 801a7c6 <etharp_find_entry+0x1fe>
|
|
/* recycle oldest stable*/
|
|
i = old_stable;
|
|
801a79c: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
801a79e: 843b strh r3, [r7, #32]
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i));
|
|
/* no queued packets should exist on stable entries */
|
|
LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL);
|
|
801a7a0: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a7a4: 493d ldr r1, [pc, #244] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a7a6: 4613 mov r3, r2
|
|
801a7a8: 005b lsls r3, r3, #1
|
|
801a7aa: 4413 add r3, r2
|
|
801a7ac: 00db lsls r3, r3, #3
|
|
801a7ae: 440b add r3, r1
|
|
801a7b0: 681b ldr r3, [r3, #0]
|
|
801a7b2: 2b00 cmp r3, #0
|
|
801a7b4: d018 beq.n 801a7e8 <etharp_find_entry+0x220>
|
|
801a7b6: 4b3a ldr r3, [pc, #232] ; (801a8a0 <etharp_find_entry+0x2d8>)
|
|
801a7b8: f240 126d movw r2, #365 ; 0x16d
|
|
801a7bc: 493b ldr r1, [pc, #236] ; (801a8ac <etharp_find_entry+0x2e4>)
|
|
801a7be: 483a ldr r0, [pc, #232] ; (801a8a8 <etharp_find_entry+0x2e0>)
|
|
801a7c0: f002 fa7a bl 801ccb8 <iprintf>
|
|
801a7c4: e010 b.n 801a7e8 <etharp_find_entry+0x220>
|
|
/* 3) found recyclable pending entry without queued packets? */
|
|
} else if (old_pending < ARP_TABLE_SIZE) {
|
|
801a7c6: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26
|
|
801a7ca: 2b09 cmp r3, #9
|
|
801a7cc: dc02 bgt.n 801a7d4 <etharp_find_entry+0x20c>
|
|
/* recycle oldest pending */
|
|
i = old_pending;
|
|
801a7ce: 8cfb ldrh r3, [r7, #38] ; 0x26
|
|
801a7d0: 843b strh r3, [r7, #32]
|
|
801a7d2: e009 b.n 801a7e8 <etharp_find_entry+0x220>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i));
|
|
/* 4) found recyclable pending entry with queued packets? */
|
|
} else if (old_queue < ARP_TABLE_SIZE) {
|
|
801a7d4: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
801a7d8: 2b09 cmp r3, #9
|
|
801a7da: dc02 bgt.n 801a7e2 <etharp_find_entry+0x21a>
|
|
/* recycle oldest pending (queued packets are free in etharp_free_entry) */
|
|
i = old_queue;
|
|
801a7dc: 8bfb ldrh r3, [r7, #30]
|
|
801a7de: 843b strh r3, [r7, #32]
|
|
801a7e0: e002 b.n 801a7e8 <etharp_find_entry+0x220>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q)));
|
|
/* no empty or recyclable entries found */
|
|
} else {
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n"));
|
|
return (s16_t)ERR_MEM;
|
|
801a7e2: f04f 33ff mov.w r3, #4294967295
|
|
801a7e6: e054 b.n 801a892 <etharp_find_entry+0x2ca>
|
|
}
|
|
|
|
/* { empty or recyclable entry found } */
|
|
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
|
|
801a7e8: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
801a7ec: 2b09 cmp r3, #9
|
|
801a7ee: dd06 ble.n 801a7fe <etharp_find_entry+0x236>
|
|
801a7f0: 4b2b ldr r3, [pc, #172] ; (801a8a0 <etharp_find_entry+0x2d8>)
|
|
801a7f2: f240 127f movw r2, #383 ; 0x17f
|
|
801a7f6: 492e ldr r1, [pc, #184] ; (801a8b0 <etharp_find_entry+0x2e8>)
|
|
801a7f8: 482b ldr r0, [pc, #172] ; (801a8a8 <etharp_find_entry+0x2e0>)
|
|
801a7fa: f002 fa5d bl 801ccb8 <iprintf>
|
|
etharp_free_entry(i);
|
|
801a7fe: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
801a802: 4618 mov r0, r3
|
|
801a804: f7ff fe06 bl 801a414 <etharp_free_entry>
|
|
}
|
|
|
|
LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE);
|
|
801a808: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
801a80c: 2b09 cmp r3, #9
|
|
801a80e: dd06 ble.n 801a81e <etharp_find_entry+0x256>
|
|
801a810: 4b23 ldr r3, [pc, #140] ; (801a8a0 <etharp_find_entry+0x2d8>)
|
|
801a812: f240 1283 movw r2, #387 ; 0x183
|
|
801a816: 4926 ldr r1, [pc, #152] ; (801a8b0 <etharp_find_entry+0x2e8>)
|
|
801a818: 4823 ldr r0, [pc, #140] ; (801a8a8 <etharp_find_entry+0x2e0>)
|
|
801a81a: f002 fa4d bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY",
|
|
801a81e: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a822: 491e ldr r1, [pc, #120] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a824: 4613 mov r3, r2
|
|
801a826: 005b lsls r3, r3, #1
|
|
801a828: 4413 add r3, r2
|
|
801a82a: 00db lsls r3, r3, #3
|
|
801a82c: 440b add r3, r1
|
|
801a82e: 3314 adds r3, #20
|
|
801a830: 781b ldrb r3, [r3, #0]
|
|
801a832: 2b00 cmp r3, #0
|
|
801a834: d006 beq.n 801a844 <etharp_find_entry+0x27c>
|
|
801a836: 4b1a ldr r3, [pc, #104] ; (801a8a0 <etharp_find_entry+0x2d8>)
|
|
801a838: f240 1285 movw r2, #389 ; 0x185
|
|
801a83c: 491d ldr r1, [pc, #116] ; (801a8b4 <etharp_find_entry+0x2ec>)
|
|
801a83e: 481a ldr r0, [pc, #104] ; (801a8a8 <etharp_find_entry+0x2e0>)
|
|
801a840: f002 fa3a bl 801ccb8 <iprintf>
|
|
arp_table[i].state == ETHARP_STATE_EMPTY);
|
|
|
|
/* IP address given? */
|
|
if (ipaddr != NULL) {
|
|
801a844: 68fb ldr r3, [r7, #12]
|
|
801a846: 2b00 cmp r3, #0
|
|
801a848: d00b beq.n 801a862 <etharp_find_entry+0x29a>
|
|
/* set IP address */
|
|
ip4_addr_copy(arp_table[i].ipaddr, *ipaddr);
|
|
801a84a: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a84e: 68fb ldr r3, [r7, #12]
|
|
801a850: 6819 ldr r1, [r3, #0]
|
|
801a852: 4812 ldr r0, [pc, #72] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a854: 4613 mov r3, r2
|
|
801a856: 005b lsls r3, r3, #1
|
|
801a858: 4413 add r3, r2
|
|
801a85a: 00db lsls r3, r3, #3
|
|
801a85c: 4403 add r3, r0
|
|
801a85e: 3304 adds r3, #4
|
|
801a860: 6019 str r1, [r3, #0]
|
|
}
|
|
arp_table[i].ctime = 0;
|
|
801a862: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a866: 490d ldr r1, [pc, #52] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a868: 4613 mov r3, r2
|
|
801a86a: 005b lsls r3, r3, #1
|
|
801a86c: 4413 add r3, r2
|
|
801a86e: 00db lsls r3, r3, #3
|
|
801a870: 440b add r3, r1
|
|
801a872: 3312 adds r3, #18
|
|
801a874: 2200 movs r2, #0
|
|
801a876: 801a strh r2, [r3, #0]
|
|
#if ETHARP_TABLE_MATCH_NETIF
|
|
arp_table[i].netif = netif;
|
|
801a878: f9b7 2020 ldrsh.w r2, [r7, #32]
|
|
801a87c: 4907 ldr r1, [pc, #28] ; (801a89c <etharp_find_entry+0x2d4>)
|
|
801a87e: 4613 mov r3, r2
|
|
801a880: 005b lsls r3, r3, #1
|
|
801a882: 4413 add r3, r2
|
|
801a884: 00db lsls r3, r3, #3
|
|
801a886: 440b add r3, r1
|
|
801a888: 3308 adds r3, #8
|
|
801a88a: 687a ldr r2, [r7, #4]
|
|
801a88c: 601a str r2, [r3, #0]
|
|
#endif /* ETHARP_TABLE_MATCH_NETIF */
|
|
return (s16_t)i;
|
|
801a88e: f9b7 3020 ldrsh.w r3, [r7, #32]
|
|
}
|
|
801a892: 4618 mov r0, r3
|
|
801a894: 3728 adds r7, #40 ; 0x28
|
|
801a896: 46bd mov sp, r7
|
|
801a898: bd80 pop {r7, pc}
|
|
801a89a: bf00 nop
|
|
801a89c: 20008778 .word 0x20008778
|
|
801a8a0: 08020738 .word 0x08020738
|
|
801a8a4: 08020770 .word 0x08020770
|
|
801a8a8: 080207b0 .word 0x080207b0
|
|
801a8ac: 080207d8 .word 0x080207d8
|
|
801a8b0: 080207f0 .word 0x080207f0
|
|
801a8b4: 08020804 .word 0x08020804
|
|
|
|
0801a8b8 <etharp_update_arp_entry>:
|
|
*
|
|
* @see pbuf_free()
|
|
*/
|
|
static err_t
|
|
etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags)
|
|
{
|
|
801a8b8: b580 push {r7, lr}
|
|
801a8ba: b088 sub sp, #32
|
|
801a8bc: af02 add r7, sp, #8
|
|
801a8be: 60f8 str r0, [r7, #12]
|
|
801a8c0: 60b9 str r1, [r7, #8]
|
|
801a8c2: 607a str r2, [r7, #4]
|
|
801a8c4: 70fb strb r3, [r7, #3]
|
|
s16_t i;
|
|
LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN);
|
|
801a8c6: 68fb ldr r3, [r7, #12]
|
|
801a8c8: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
801a8cc: 2b06 cmp r3, #6
|
|
801a8ce: d006 beq.n 801a8de <etharp_update_arp_entry+0x26>
|
|
801a8d0: 4b48 ldr r3, [pc, #288] ; (801a9f4 <etharp_update_arp_entry+0x13c>)
|
|
801a8d2: f240 12a9 movw r2, #425 ; 0x1a9
|
|
801a8d6: 4948 ldr r1, [pc, #288] ; (801a9f8 <etharp_update_arp_entry+0x140>)
|
|
801a8d8: 4848 ldr r0, [pc, #288] ; (801a9fc <etharp_update_arp_entry+0x144>)
|
|
801a8da: f002 f9ed bl 801ccb8 <iprintf>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n",
|
|
ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr),
|
|
(u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2],
|
|
(u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5]));
|
|
/* non-unicast address? */
|
|
if (ip4_addr_isany(ipaddr) ||
|
|
801a8de: 68bb ldr r3, [r7, #8]
|
|
801a8e0: 2b00 cmp r3, #0
|
|
801a8e2: d012 beq.n 801a90a <etharp_update_arp_entry+0x52>
|
|
801a8e4: 68bb ldr r3, [r7, #8]
|
|
801a8e6: 681b ldr r3, [r3, #0]
|
|
801a8e8: 2b00 cmp r3, #0
|
|
801a8ea: d00e beq.n 801a90a <etharp_update_arp_entry+0x52>
|
|
ip4_addr_isbroadcast(ipaddr, netif) ||
|
|
801a8ec: 68bb ldr r3, [r7, #8]
|
|
801a8ee: 681b ldr r3, [r3, #0]
|
|
801a8f0: 68f9 ldr r1, [r7, #12]
|
|
801a8f2: 4618 mov r0, r3
|
|
801a8f4: f001 f91e bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801a8f8: 4603 mov r3, r0
|
|
if (ip4_addr_isany(ipaddr) ||
|
|
801a8fa: 2b00 cmp r3, #0
|
|
801a8fc: d105 bne.n 801a90a <etharp_update_arp_entry+0x52>
|
|
ip4_addr_ismulticast(ipaddr)) {
|
|
801a8fe: 68bb ldr r3, [r7, #8]
|
|
801a900: 681b ldr r3, [r3, #0]
|
|
801a902: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
ip4_addr_isbroadcast(ipaddr, netif) ||
|
|
801a906: 2be0 cmp r3, #224 ; 0xe0
|
|
801a908: d102 bne.n 801a910 <etharp_update_arp_entry+0x58>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n"));
|
|
return ERR_ARG;
|
|
801a90a: f06f 030f mvn.w r3, #15
|
|
801a90e: e06c b.n 801a9ea <etharp_update_arp_entry+0x132>
|
|
}
|
|
/* find or create ARP entry */
|
|
i = etharp_find_entry(ipaddr, flags, netif);
|
|
801a910: 78fb ldrb r3, [r7, #3]
|
|
801a912: 68fa ldr r2, [r7, #12]
|
|
801a914: 4619 mov r1, r3
|
|
801a916: 68b8 ldr r0, [r7, #8]
|
|
801a918: f7ff fe56 bl 801a5c8 <etharp_find_entry>
|
|
801a91c: 4603 mov r3, r0
|
|
801a91e: 82fb strh r3, [r7, #22]
|
|
/* bail out if no entry could be found */
|
|
if (i < 0) {
|
|
801a920: f9b7 3016 ldrsh.w r3, [r7, #22]
|
|
801a924: 2b00 cmp r3, #0
|
|
801a926: da02 bge.n 801a92e <etharp_update_arp_entry+0x76>
|
|
return (err_t)i;
|
|
801a928: 8afb ldrh r3, [r7, #22]
|
|
801a92a: b25b sxtb r3, r3
|
|
801a92c: e05d b.n 801a9ea <etharp_update_arp_entry+0x132>
|
|
return ERR_VAL;
|
|
} else
|
|
#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */
|
|
{
|
|
/* mark it stable */
|
|
arp_table[i].state = ETHARP_STATE_STABLE;
|
|
801a92e: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a932: 4933 ldr r1, [pc, #204] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a934: 4613 mov r3, r2
|
|
801a936: 005b lsls r3, r3, #1
|
|
801a938: 4413 add r3, r2
|
|
801a93a: 00db lsls r3, r3, #3
|
|
801a93c: 440b add r3, r1
|
|
801a93e: 3314 adds r3, #20
|
|
801a940: 2202 movs r2, #2
|
|
801a942: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* record network interface */
|
|
arp_table[i].netif = netif;
|
|
801a944: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a948: 492d ldr r1, [pc, #180] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a94a: 4613 mov r3, r2
|
|
801a94c: 005b lsls r3, r3, #1
|
|
801a94e: 4413 add r3, r2
|
|
801a950: 00db lsls r3, r3, #3
|
|
801a952: 440b add r3, r1
|
|
801a954: 3308 adds r3, #8
|
|
801a956: 68fa ldr r2, [r7, #12]
|
|
801a958: 601a str r2, [r3, #0]
|
|
/* insert in SNMP ARP index tree */
|
|
mib2_add_arp_entry(netif, &arp_table[i].ipaddr);
|
|
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i));
|
|
/* update address */
|
|
SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN);
|
|
801a95a: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a95e: 4613 mov r3, r2
|
|
801a960: 005b lsls r3, r3, #1
|
|
801a962: 4413 add r3, r2
|
|
801a964: 00db lsls r3, r3, #3
|
|
801a966: 3308 adds r3, #8
|
|
801a968: 4a25 ldr r2, [pc, #148] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a96a: 4413 add r3, r2
|
|
801a96c: 3304 adds r3, #4
|
|
801a96e: 2206 movs r2, #6
|
|
801a970: 6879 ldr r1, [r7, #4]
|
|
801a972: 4618 mov r0, r3
|
|
801a974: f002 f973 bl 801cc5e <memcpy>
|
|
/* reset time stamp */
|
|
arp_table[i].ctime = 0;
|
|
801a978: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a97c: 4920 ldr r1, [pc, #128] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a97e: 4613 mov r3, r2
|
|
801a980: 005b lsls r3, r3, #1
|
|
801a982: 4413 add r3, r2
|
|
801a984: 00db lsls r3, r3, #3
|
|
801a986: 440b add r3, r1
|
|
801a988: 3312 adds r3, #18
|
|
801a98a: 2200 movs r2, #0
|
|
801a98c: 801a strh r2, [r3, #0]
|
|
/* get the packet pointer */
|
|
p = q->p;
|
|
/* now queue entry can be freed */
|
|
memp_free(MEMP_ARP_QUEUE, q);
|
|
#else /* ARP_QUEUEING */
|
|
if (arp_table[i].q != NULL) {
|
|
801a98e: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a992: 491b ldr r1, [pc, #108] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a994: 4613 mov r3, r2
|
|
801a996: 005b lsls r3, r3, #1
|
|
801a998: 4413 add r3, r2
|
|
801a99a: 00db lsls r3, r3, #3
|
|
801a99c: 440b add r3, r1
|
|
801a99e: 681b ldr r3, [r3, #0]
|
|
801a9a0: 2b00 cmp r3, #0
|
|
801a9a2: d021 beq.n 801a9e8 <etharp_update_arp_entry+0x130>
|
|
struct pbuf *p = arp_table[i].q;
|
|
801a9a4: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a9a8: 4915 ldr r1, [pc, #84] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a9aa: 4613 mov r3, r2
|
|
801a9ac: 005b lsls r3, r3, #1
|
|
801a9ae: 4413 add r3, r2
|
|
801a9b0: 00db lsls r3, r3, #3
|
|
801a9b2: 440b add r3, r1
|
|
801a9b4: 681b ldr r3, [r3, #0]
|
|
801a9b6: 613b str r3, [r7, #16]
|
|
arp_table[i].q = NULL;
|
|
801a9b8: f9b7 2016 ldrsh.w r2, [r7, #22]
|
|
801a9bc: 4910 ldr r1, [pc, #64] ; (801aa00 <etharp_update_arp_entry+0x148>)
|
|
801a9be: 4613 mov r3, r2
|
|
801a9c0: 005b lsls r3, r3, #1
|
|
801a9c2: 4413 add r3, r2
|
|
801a9c4: 00db lsls r3, r3, #3
|
|
801a9c6: 440b add r3, r1
|
|
801a9c8: 2200 movs r2, #0
|
|
801a9ca: 601a str r2, [r3, #0]
|
|
#endif /* ARP_QUEUEING */
|
|
/* send the queued IP packet */
|
|
ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP);
|
|
801a9cc: 68fb ldr r3, [r7, #12]
|
|
801a9ce: f103 022a add.w r2, r3, #42 ; 0x2a
|
|
801a9d2: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
801a9d6: 9300 str r3, [sp, #0]
|
|
801a9d8: 687b ldr r3, [r7, #4]
|
|
801a9da: 6939 ldr r1, [r7, #16]
|
|
801a9dc: 68f8 ldr r0, [r7, #12]
|
|
801a9de: f001 ffad bl 801c93c <ethernet_output>
|
|
/* free the queued IP packet */
|
|
pbuf_free(p);
|
|
801a9e2: 6938 ldr r0, [r7, #16]
|
|
801a9e4: f7f7 fc38 bl 8012258 <pbuf_free>
|
|
}
|
|
return ERR_OK;
|
|
801a9e8: 2300 movs r3, #0
|
|
}
|
|
801a9ea: 4618 mov r0, r3
|
|
801a9ec: 3718 adds r7, #24
|
|
801a9ee: 46bd mov sp, r7
|
|
801a9f0: bd80 pop {r7, pc}
|
|
801a9f2: bf00 nop
|
|
801a9f4: 08020738 .word 0x08020738
|
|
801a9f8: 08020830 .word 0x08020830
|
|
801a9fc: 080207b0 .word 0x080207b0
|
|
801aa00: 20008778 .word 0x20008778
|
|
|
|
0801aa04 <etharp_cleanup_netif>:
|
|
*
|
|
* @param netif points to a network interface
|
|
*/
|
|
void
|
|
etharp_cleanup_netif(struct netif *netif)
|
|
{
|
|
801aa04: b580 push {r7, lr}
|
|
801aa06: b084 sub sp, #16
|
|
801aa08: af00 add r7, sp, #0
|
|
801aa0a: 6078 str r0, [r7, #4]
|
|
int i;
|
|
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801aa0c: 2300 movs r3, #0
|
|
801aa0e: 60fb str r3, [r7, #12]
|
|
801aa10: e01e b.n 801aa50 <etharp_cleanup_netif+0x4c>
|
|
u8_t state = arp_table[i].state;
|
|
801aa12: 4913 ldr r1, [pc, #76] ; (801aa60 <etharp_cleanup_netif+0x5c>)
|
|
801aa14: 68fa ldr r2, [r7, #12]
|
|
801aa16: 4613 mov r3, r2
|
|
801aa18: 005b lsls r3, r3, #1
|
|
801aa1a: 4413 add r3, r2
|
|
801aa1c: 00db lsls r3, r3, #3
|
|
801aa1e: 440b add r3, r1
|
|
801aa20: 3314 adds r3, #20
|
|
801aa22: 781b ldrb r3, [r3, #0]
|
|
801aa24: 72fb strb r3, [r7, #11]
|
|
if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) {
|
|
801aa26: 7afb ldrb r3, [r7, #11]
|
|
801aa28: 2b00 cmp r3, #0
|
|
801aa2a: d00e beq.n 801aa4a <etharp_cleanup_netif+0x46>
|
|
801aa2c: 490c ldr r1, [pc, #48] ; (801aa60 <etharp_cleanup_netif+0x5c>)
|
|
801aa2e: 68fa ldr r2, [r7, #12]
|
|
801aa30: 4613 mov r3, r2
|
|
801aa32: 005b lsls r3, r3, #1
|
|
801aa34: 4413 add r3, r2
|
|
801aa36: 00db lsls r3, r3, #3
|
|
801aa38: 440b add r3, r1
|
|
801aa3a: 3308 adds r3, #8
|
|
801aa3c: 681b ldr r3, [r3, #0]
|
|
801aa3e: 687a ldr r2, [r7, #4]
|
|
801aa40: 429a cmp r2, r3
|
|
801aa42: d102 bne.n 801aa4a <etharp_cleanup_netif+0x46>
|
|
etharp_free_entry(i);
|
|
801aa44: 68f8 ldr r0, [r7, #12]
|
|
801aa46: f7ff fce5 bl 801a414 <etharp_free_entry>
|
|
for (i = 0; i < ARP_TABLE_SIZE; ++i) {
|
|
801aa4a: 68fb ldr r3, [r7, #12]
|
|
801aa4c: 3301 adds r3, #1
|
|
801aa4e: 60fb str r3, [r7, #12]
|
|
801aa50: 68fb ldr r3, [r7, #12]
|
|
801aa52: 2b09 cmp r3, #9
|
|
801aa54: dddd ble.n 801aa12 <etharp_cleanup_netif+0xe>
|
|
}
|
|
}
|
|
}
|
|
801aa56: bf00 nop
|
|
801aa58: 3710 adds r7, #16
|
|
801aa5a: 46bd mov sp, r7
|
|
801aa5c: bd80 pop {r7, pc}
|
|
801aa5e: bf00 nop
|
|
801aa60: 20008778 .word 0x20008778
|
|
|
|
0801aa64 <etharp_input>:
|
|
*
|
|
* @see pbuf_free()
|
|
*/
|
|
void
|
|
etharp_input(struct pbuf *p, struct netif *netif)
|
|
{
|
|
801aa64: b5b0 push {r4, r5, r7, lr}
|
|
801aa66: b08a sub sp, #40 ; 0x28
|
|
801aa68: af04 add r7, sp, #16
|
|
801aa6a: 6078 str r0, [r7, #4]
|
|
801aa6c: 6039 str r1, [r7, #0]
|
|
ip4_addr_t sipaddr, dipaddr;
|
|
u8_t for_us;
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
LWIP_ERROR("netif != NULL", (netif != NULL), return;);
|
|
801aa6e: 683b ldr r3, [r7, #0]
|
|
801aa70: 2b00 cmp r3, #0
|
|
801aa72: d107 bne.n 801aa84 <etharp_input+0x20>
|
|
801aa74: 4b3f ldr r3, [pc, #252] ; (801ab74 <etharp_input+0x110>)
|
|
801aa76: f240 228a movw r2, #650 ; 0x28a
|
|
801aa7a: 493f ldr r1, [pc, #252] ; (801ab78 <etharp_input+0x114>)
|
|
801aa7c: 483f ldr r0, [pc, #252] ; (801ab7c <etharp_input+0x118>)
|
|
801aa7e: f002 f91b bl 801ccb8 <iprintf>
|
|
801aa82: e074 b.n 801ab6e <etharp_input+0x10a>
|
|
|
|
hdr = (struct etharp_hdr *)p->payload;
|
|
801aa84: 687b ldr r3, [r7, #4]
|
|
801aa86: 685b ldr r3, [r3, #4]
|
|
801aa88: 613b str r3, [r7, #16]
|
|
|
|
/* RFC 826 "Packet Reception": */
|
|
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
|
|
801aa8a: 693b ldr r3, [r7, #16]
|
|
801aa8c: 881b ldrh r3, [r3, #0]
|
|
801aa8e: b29b uxth r3, r3
|
|
801aa90: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
801aa94: d10c bne.n 801aab0 <etharp_input+0x4c>
|
|
(hdr->hwlen != ETH_HWADDR_LEN) ||
|
|
801aa96: 693b ldr r3, [r7, #16]
|
|
801aa98: 791b ldrb r3, [r3, #4]
|
|
if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) ||
|
|
801aa9a: 2b06 cmp r3, #6
|
|
801aa9c: d108 bne.n 801aab0 <etharp_input+0x4c>
|
|
(hdr->protolen != sizeof(ip4_addr_t)) ||
|
|
801aa9e: 693b ldr r3, [r7, #16]
|
|
801aaa0: 795b ldrb r3, [r3, #5]
|
|
(hdr->hwlen != ETH_HWADDR_LEN) ||
|
|
801aaa2: 2b04 cmp r3, #4
|
|
801aaa4: d104 bne.n 801aab0 <etharp_input+0x4c>
|
|
(hdr->proto != PP_HTONS(ETHTYPE_IP))) {
|
|
801aaa6: 693b ldr r3, [r7, #16]
|
|
801aaa8: 885b ldrh r3, [r3, #2]
|
|
801aaaa: b29b uxth r3, r3
|
|
(hdr->protolen != sizeof(ip4_addr_t)) ||
|
|
801aaac: 2b08 cmp r3, #8
|
|
801aaae: d003 beq.n 801aab8 <etharp_input+0x54>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING,
|
|
("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n",
|
|
hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen));
|
|
ETHARP_STATS_INC(etharp.proterr);
|
|
ETHARP_STATS_INC(etharp.drop);
|
|
pbuf_free(p);
|
|
801aab0: 6878 ldr r0, [r7, #4]
|
|
801aab2: f7f7 fbd1 bl 8012258 <pbuf_free>
|
|
return;
|
|
801aab6: e05a b.n 801ab6e <etharp_input+0x10a>
|
|
autoip_arp_reply(netif, hdr);
|
|
#endif /* LWIP_AUTOIP */
|
|
|
|
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
|
|
* structure packing (not using structure copy which breaks strict-aliasing rules). */
|
|
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr);
|
|
801aab8: 693b ldr r3, [r7, #16]
|
|
801aaba: 330e adds r3, #14
|
|
801aabc: 681b ldr r3, [r3, #0]
|
|
801aabe: 60fb str r3, [r7, #12]
|
|
IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr);
|
|
801aac0: 693b ldr r3, [r7, #16]
|
|
801aac2: 3318 adds r3, #24
|
|
801aac4: 681b ldr r3, [r3, #0]
|
|
801aac6: 60bb str r3, [r7, #8]
|
|
|
|
/* this interface is not configured? */
|
|
if (ip4_addr_isany_val(*netif_ip4_addr(netif))) {
|
|
801aac8: 683b ldr r3, [r7, #0]
|
|
801aaca: 3304 adds r3, #4
|
|
801aacc: 681b ldr r3, [r3, #0]
|
|
801aace: 2b00 cmp r3, #0
|
|
801aad0: d102 bne.n 801aad8 <etharp_input+0x74>
|
|
for_us = 0;
|
|
801aad2: 2300 movs r3, #0
|
|
801aad4: 75fb strb r3, [r7, #23]
|
|
801aad6: e009 b.n 801aaec <etharp_input+0x88>
|
|
} else {
|
|
/* ARP packet directed to us? */
|
|
for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif));
|
|
801aad8: 68ba ldr r2, [r7, #8]
|
|
801aada: 683b ldr r3, [r7, #0]
|
|
801aadc: 3304 adds r3, #4
|
|
801aade: 681b ldr r3, [r3, #0]
|
|
801aae0: 429a cmp r2, r3
|
|
801aae2: bf0c ite eq
|
|
801aae4: 2301 moveq r3, #1
|
|
801aae6: 2300 movne r3, #0
|
|
801aae8: b2db uxtb r3, r3
|
|
801aaea: 75fb strb r3, [r7, #23]
|
|
/* ARP message directed to us?
|
|
-> add IP address in ARP cache; assume requester wants to talk to us,
|
|
can result in directly sending the queued packets for this host.
|
|
ARP message not directed to us?
|
|
-> update the source IP address in the cache, if present */
|
|
etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr),
|
|
801aaec: 693b ldr r3, [r7, #16]
|
|
801aaee: f103 0208 add.w r2, r3, #8
|
|
801aaf2: 7dfb ldrb r3, [r7, #23]
|
|
801aaf4: 2b00 cmp r3, #0
|
|
801aaf6: d001 beq.n 801aafc <etharp_input+0x98>
|
|
801aaf8: 2301 movs r3, #1
|
|
801aafa: e000 b.n 801aafe <etharp_input+0x9a>
|
|
801aafc: 2302 movs r3, #2
|
|
801aafe: f107 010c add.w r1, r7, #12
|
|
801ab02: 6838 ldr r0, [r7, #0]
|
|
801ab04: f7ff fed8 bl 801a8b8 <etharp_update_arp_entry>
|
|
for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY);
|
|
|
|
/* now act on the message itself */
|
|
switch (hdr->opcode) {
|
|
801ab08: 693b ldr r3, [r7, #16]
|
|
801ab0a: 88db ldrh r3, [r3, #6]
|
|
801ab0c: b29b uxth r3, r3
|
|
801ab0e: f5b3 7f80 cmp.w r3, #256 ; 0x100
|
|
801ab12: d003 beq.n 801ab1c <etharp_input+0xb8>
|
|
801ab14: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
801ab18: d01e beq.n 801ab58 <etharp_input+0xf4>
|
|
#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */
|
|
break;
|
|
default:
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode)));
|
|
ETHARP_STATS_INC(etharp.err);
|
|
break;
|
|
801ab1a: e025 b.n 801ab68 <etharp_input+0x104>
|
|
if (for_us) {
|
|
801ab1c: 7dfb ldrb r3, [r7, #23]
|
|
801ab1e: 2b00 cmp r3, #0
|
|
801ab20: d021 beq.n 801ab66 <etharp_input+0x102>
|
|
(struct eth_addr *)netif->hwaddr, &hdr->shwaddr,
|
|
801ab22: 683b ldr r3, [r7, #0]
|
|
801ab24: f103 002a add.w r0, r3, #42 ; 0x2a
|
|
801ab28: 693b ldr r3, [r7, #16]
|
|
801ab2a: f103 0408 add.w r4, r3, #8
|
|
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif),
|
|
801ab2e: 683b ldr r3, [r7, #0]
|
|
801ab30: f103 052a add.w r5, r3, #42 ; 0x2a
|
|
801ab34: 683b ldr r3, [r7, #0]
|
|
801ab36: 3304 adds r3, #4
|
|
&hdr->shwaddr, &sipaddr,
|
|
801ab38: 693a ldr r2, [r7, #16]
|
|
801ab3a: 3208 adds r2, #8
|
|
etharp_raw(netif,
|
|
801ab3c: 2102 movs r1, #2
|
|
801ab3e: 9103 str r1, [sp, #12]
|
|
801ab40: f107 010c add.w r1, r7, #12
|
|
801ab44: 9102 str r1, [sp, #8]
|
|
801ab46: 9201 str r2, [sp, #4]
|
|
801ab48: 9300 str r3, [sp, #0]
|
|
801ab4a: 462b mov r3, r5
|
|
801ab4c: 4622 mov r2, r4
|
|
801ab4e: 4601 mov r1, r0
|
|
801ab50: 6838 ldr r0, [r7, #0]
|
|
801ab52: f000 faef bl 801b134 <etharp_raw>
|
|
break;
|
|
801ab56: e006 b.n 801ab66 <etharp_input+0x102>
|
|
dhcp_arp_reply(netif, &sipaddr);
|
|
801ab58: f107 030c add.w r3, r7, #12
|
|
801ab5c: 4619 mov r1, r3
|
|
801ab5e: 6838 ldr r0, [r7, #0]
|
|
801ab60: f7fe f9fe bl 8018f60 <dhcp_arp_reply>
|
|
break;
|
|
801ab64: e000 b.n 801ab68 <etharp_input+0x104>
|
|
break;
|
|
801ab66: bf00 nop
|
|
}
|
|
/* free ARP packet */
|
|
pbuf_free(p);
|
|
801ab68: 6878 ldr r0, [r7, #4]
|
|
801ab6a: f7f7 fb75 bl 8012258 <pbuf_free>
|
|
}
|
|
801ab6e: 3718 adds r7, #24
|
|
801ab70: 46bd mov sp, r7
|
|
801ab72: bdb0 pop {r4, r5, r7, pc}
|
|
801ab74: 08020738 .word 0x08020738
|
|
801ab78: 08020888 .word 0x08020888
|
|
801ab7c: 080207b0 .word 0x080207b0
|
|
|
|
0801ab80 <etharp_output_to_arp_index>:
|
|
/** Just a small helper function that sends a pbuf to an ethernet address
|
|
* in the arp_table specified by the index 'arp_idx'.
|
|
*/
|
|
static err_t
|
|
etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx)
|
|
{
|
|
801ab80: b580 push {r7, lr}
|
|
801ab82: b086 sub sp, #24
|
|
801ab84: af02 add r7, sp, #8
|
|
801ab86: 60f8 str r0, [r7, #12]
|
|
801ab88: 60b9 str r1, [r7, #8]
|
|
801ab8a: 4613 mov r3, r2
|
|
801ab8c: 71fb strb r3, [r7, #7]
|
|
LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE",
|
|
801ab8e: 79fa ldrb r2, [r7, #7]
|
|
801ab90: 4944 ldr r1, [pc, #272] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ab92: 4613 mov r3, r2
|
|
801ab94: 005b lsls r3, r3, #1
|
|
801ab96: 4413 add r3, r2
|
|
801ab98: 00db lsls r3, r3, #3
|
|
801ab9a: 440b add r3, r1
|
|
801ab9c: 3314 adds r3, #20
|
|
801ab9e: 781b ldrb r3, [r3, #0]
|
|
801aba0: 2b01 cmp r3, #1
|
|
801aba2: d806 bhi.n 801abb2 <etharp_output_to_arp_index+0x32>
|
|
801aba4: 4b40 ldr r3, [pc, #256] ; (801aca8 <etharp_output_to_arp_index+0x128>)
|
|
801aba6: f240 22ef movw r2, #751 ; 0x2ef
|
|
801abaa: 4940 ldr r1, [pc, #256] ; (801acac <etharp_output_to_arp_index+0x12c>)
|
|
801abac: 4840 ldr r0, [pc, #256] ; (801acb0 <etharp_output_to_arp_index+0x130>)
|
|
801abae: f002 f883 bl 801ccb8 <iprintf>
|
|
arp_table[arp_idx].state >= ETHARP_STATE_STABLE);
|
|
/* if arp table entry is about to expire: re-request it,
|
|
but only if its state is ETHARP_STATE_STABLE to prevent flooding the
|
|
network with ARP requests if this address is used frequently. */
|
|
if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) {
|
|
801abb2: 79fa ldrb r2, [r7, #7]
|
|
801abb4: 493b ldr r1, [pc, #236] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801abb6: 4613 mov r3, r2
|
|
801abb8: 005b lsls r3, r3, #1
|
|
801abba: 4413 add r3, r2
|
|
801abbc: 00db lsls r3, r3, #3
|
|
801abbe: 440b add r3, r1
|
|
801abc0: 3314 adds r3, #20
|
|
801abc2: 781b ldrb r3, [r3, #0]
|
|
801abc4: 2b02 cmp r3, #2
|
|
801abc6: d153 bne.n 801ac70 <etharp_output_to_arp_index+0xf0>
|
|
if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) {
|
|
801abc8: 79fa ldrb r2, [r7, #7]
|
|
801abca: 4936 ldr r1, [pc, #216] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801abcc: 4613 mov r3, r2
|
|
801abce: 005b lsls r3, r3, #1
|
|
801abd0: 4413 add r3, r2
|
|
801abd2: 00db lsls r3, r3, #3
|
|
801abd4: 440b add r3, r1
|
|
801abd6: 3312 adds r3, #18
|
|
801abd8: 881b ldrh r3, [r3, #0]
|
|
801abda: f5b3 7f8e cmp.w r3, #284 ; 0x11c
|
|
801abde: d919 bls.n 801ac14 <etharp_output_to_arp_index+0x94>
|
|
/* issue a standard request using broadcast */
|
|
if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) {
|
|
801abe0: 79fa ldrb r2, [r7, #7]
|
|
801abe2: 4613 mov r3, r2
|
|
801abe4: 005b lsls r3, r3, #1
|
|
801abe6: 4413 add r3, r2
|
|
801abe8: 00db lsls r3, r3, #3
|
|
801abea: 4a2e ldr r2, [pc, #184] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801abec: 4413 add r3, r2
|
|
801abee: 3304 adds r3, #4
|
|
801abf0: 4619 mov r1, r3
|
|
801abf2: 68f8 ldr r0, [r7, #12]
|
|
801abf4: f000 fb4c bl 801b290 <etharp_request>
|
|
801abf8: 4603 mov r3, r0
|
|
801abfa: 2b00 cmp r3, #0
|
|
801abfc: d138 bne.n 801ac70 <etharp_output_to_arp_index+0xf0>
|
|
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
|
|
801abfe: 79fa ldrb r2, [r7, #7]
|
|
801ac00: 4928 ldr r1, [pc, #160] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac02: 4613 mov r3, r2
|
|
801ac04: 005b lsls r3, r3, #1
|
|
801ac06: 4413 add r3, r2
|
|
801ac08: 00db lsls r3, r3, #3
|
|
801ac0a: 440b add r3, r1
|
|
801ac0c: 3314 adds r3, #20
|
|
801ac0e: 2203 movs r2, #3
|
|
801ac10: 701a strb r2, [r3, #0]
|
|
801ac12: e02d b.n 801ac70 <etharp_output_to_arp_index+0xf0>
|
|
}
|
|
} else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) {
|
|
801ac14: 79fa ldrb r2, [r7, #7]
|
|
801ac16: 4923 ldr r1, [pc, #140] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac18: 4613 mov r3, r2
|
|
801ac1a: 005b lsls r3, r3, #1
|
|
801ac1c: 4413 add r3, r2
|
|
801ac1e: 00db lsls r3, r3, #3
|
|
801ac20: 440b add r3, r1
|
|
801ac22: 3312 adds r3, #18
|
|
801ac24: 881b ldrh r3, [r3, #0]
|
|
801ac26: f5b3 7f87 cmp.w r3, #270 ; 0x10e
|
|
801ac2a: d321 bcc.n 801ac70 <etharp_output_to_arp_index+0xf0>
|
|
/* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */
|
|
if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) {
|
|
801ac2c: 79fa ldrb r2, [r7, #7]
|
|
801ac2e: 4613 mov r3, r2
|
|
801ac30: 005b lsls r3, r3, #1
|
|
801ac32: 4413 add r3, r2
|
|
801ac34: 00db lsls r3, r3, #3
|
|
801ac36: 4a1b ldr r2, [pc, #108] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac38: 4413 add r3, r2
|
|
801ac3a: 1d19 adds r1, r3, #4
|
|
801ac3c: 79fa ldrb r2, [r7, #7]
|
|
801ac3e: 4613 mov r3, r2
|
|
801ac40: 005b lsls r3, r3, #1
|
|
801ac42: 4413 add r3, r2
|
|
801ac44: 00db lsls r3, r3, #3
|
|
801ac46: 3308 adds r3, #8
|
|
801ac48: 4a16 ldr r2, [pc, #88] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac4a: 4413 add r3, r2
|
|
801ac4c: 3304 adds r3, #4
|
|
801ac4e: 461a mov r2, r3
|
|
801ac50: 68f8 ldr r0, [r7, #12]
|
|
801ac52: f000 fafb bl 801b24c <etharp_request_dst>
|
|
801ac56: 4603 mov r3, r0
|
|
801ac58: 2b00 cmp r3, #0
|
|
801ac5a: d109 bne.n 801ac70 <etharp_output_to_arp_index+0xf0>
|
|
arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1;
|
|
801ac5c: 79fa ldrb r2, [r7, #7]
|
|
801ac5e: 4911 ldr r1, [pc, #68] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac60: 4613 mov r3, r2
|
|
801ac62: 005b lsls r3, r3, #1
|
|
801ac64: 4413 add r3, r2
|
|
801ac66: 00db lsls r3, r3, #3
|
|
801ac68: 440b add r3, r1
|
|
801ac6a: 3314 adds r3, #20
|
|
801ac6c: 2203 movs r2, #3
|
|
801ac6e: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
}
|
|
|
|
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP);
|
|
801ac70: 68fb ldr r3, [r7, #12]
|
|
801ac72: f103 012a add.w r1, r3, #42 ; 0x2a
|
|
801ac76: 79fa ldrb r2, [r7, #7]
|
|
801ac78: 4613 mov r3, r2
|
|
801ac7a: 005b lsls r3, r3, #1
|
|
801ac7c: 4413 add r3, r2
|
|
801ac7e: 00db lsls r3, r3, #3
|
|
801ac80: 3308 adds r3, #8
|
|
801ac82: 4a08 ldr r2, [pc, #32] ; (801aca4 <etharp_output_to_arp_index+0x124>)
|
|
801ac84: 4413 add r3, r2
|
|
801ac86: 1d1a adds r2, r3, #4
|
|
801ac88: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
801ac8c: 9300 str r3, [sp, #0]
|
|
801ac8e: 4613 mov r3, r2
|
|
801ac90: 460a mov r2, r1
|
|
801ac92: 68b9 ldr r1, [r7, #8]
|
|
801ac94: 68f8 ldr r0, [r7, #12]
|
|
801ac96: f001 fe51 bl 801c93c <ethernet_output>
|
|
801ac9a: 4603 mov r3, r0
|
|
}
|
|
801ac9c: 4618 mov r0, r3
|
|
801ac9e: 3710 adds r7, #16
|
|
801aca0: 46bd mov sp, r7
|
|
801aca2: bd80 pop {r7, pc}
|
|
801aca4: 20008778 .word 0x20008778
|
|
801aca8: 08020738 .word 0x08020738
|
|
801acac: 080208a8 .word 0x080208a8
|
|
801acb0: 080207b0 .word 0x080207b0
|
|
|
|
0801acb4 <etharp_output>:
|
|
* - ERR_RTE No route to destination (no gateway to external networks),
|
|
* or the return type of either etharp_query() or ethernet_output().
|
|
*/
|
|
err_t
|
|
etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr)
|
|
{
|
|
801acb4: b580 push {r7, lr}
|
|
801acb6: b08a sub sp, #40 ; 0x28
|
|
801acb8: af02 add r7, sp, #8
|
|
801acba: 60f8 str r0, [r7, #12]
|
|
801acbc: 60b9 str r1, [r7, #8]
|
|
801acbe: 607a str r2, [r7, #4]
|
|
const struct eth_addr *dest;
|
|
struct eth_addr mcastaddr;
|
|
const ip4_addr_t *dst_addr = ipaddr;
|
|
801acc0: 687b ldr r3, [r7, #4]
|
|
801acc2: 61bb str r3, [r7, #24]
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_ASSERT("netif != NULL", netif != NULL);
|
|
801acc4: 68fb ldr r3, [r7, #12]
|
|
801acc6: 2b00 cmp r3, #0
|
|
801acc8: d106 bne.n 801acd8 <etharp_output+0x24>
|
|
801acca: 4b73 ldr r3, [pc, #460] ; (801ae98 <etharp_output+0x1e4>)
|
|
801accc: f240 321e movw r2, #798 ; 0x31e
|
|
801acd0: 4972 ldr r1, [pc, #456] ; (801ae9c <etharp_output+0x1e8>)
|
|
801acd2: 4873 ldr r0, [pc, #460] ; (801aea0 <etharp_output+0x1ec>)
|
|
801acd4: f001 fff0 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("q != NULL", q != NULL);
|
|
801acd8: 68bb ldr r3, [r7, #8]
|
|
801acda: 2b00 cmp r3, #0
|
|
801acdc: d106 bne.n 801acec <etharp_output+0x38>
|
|
801acde: 4b6e ldr r3, [pc, #440] ; (801ae98 <etharp_output+0x1e4>)
|
|
801ace0: f240 321f movw r2, #799 ; 0x31f
|
|
801ace4: 496f ldr r1, [pc, #444] ; (801aea4 <etharp_output+0x1f0>)
|
|
801ace6: 486e ldr r0, [pc, #440] ; (801aea0 <etharp_output+0x1ec>)
|
|
801ace8: f001 ffe6 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL);
|
|
801acec: 687b ldr r3, [r7, #4]
|
|
801acee: 2b00 cmp r3, #0
|
|
801acf0: d106 bne.n 801ad00 <etharp_output+0x4c>
|
|
801acf2: 4b69 ldr r3, [pc, #420] ; (801ae98 <etharp_output+0x1e4>)
|
|
801acf4: f44f 7248 mov.w r2, #800 ; 0x320
|
|
801acf8: 496b ldr r1, [pc, #428] ; (801aea8 <etharp_output+0x1f4>)
|
|
801acfa: 4869 ldr r0, [pc, #420] ; (801aea0 <etharp_output+0x1ec>)
|
|
801acfc: f001 ffdc bl 801ccb8 <iprintf>
|
|
|
|
/* Determine on destination hardware address. Broadcasts and multicasts
|
|
* are special, other IP addresses are looked up in the ARP table. */
|
|
|
|
/* broadcast destination IP address? */
|
|
if (ip4_addr_isbroadcast(ipaddr, netif)) {
|
|
801ad00: 687b ldr r3, [r7, #4]
|
|
801ad02: 681b ldr r3, [r3, #0]
|
|
801ad04: 68f9 ldr r1, [r7, #12]
|
|
801ad06: 4618 mov r0, r3
|
|
801ad08: f000 ff14 bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801ad0c: 4603 mov r3, r0
|
|
801ad0e: 2b00 cmp r3, #0
|
|
801ad10: d002 beq.n 801ad18 <etharp_output+0x64>
|
|
/* broadcast on Ethernet also */
|
|
dest = (const struct eth_addr *)ðbroadcast;
|
|
801ad12: 4b66 ldr r3, [pc, #408] ; (801aeac <etharp_output+0x1f8>)
|
|
801ad14: 61fb str r3, [r7, #28]
|
|
801ad16: e0af b.n 801ae78 <etharp_output+0x1c4>
|
|
/* multicast destination IP address? */
|
|
} else if (ip4_addr_ismulticast(ipaddr)) {
|
|
801ad18: 687b ldr r3, [r7, #4]
|
|
801ad1a: 681b ldr r3, [r3, #0]
|
|
801ad1c: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
801ad20: 2be0 cmp r3, #224 ; 0xe0
|
|
801ad22: d118 bne.n 801ad56 <etharp_output+0xa2>
|
|
/* Hash IP multicast address to MAC address.*/
|
|
mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0;
|
|
801ad24: 2301 movs r3, #1
|
|
801ad26: 743b strb r3, [r7, #16]
|
|
mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1;
|
|
801ad28: 2300 movs r3, #0
|
|
801ad2a: 747b strb r3, [r7, #17]
|
|
mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2;
|
|
801ad2c: 235e movs r3, #94 ; 0x5e
|
|
801ad2e: 74bb strb r3, [r7, #18]
|
|
mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f;
|
|
801ad30: 687b ldr r3, [r7, #4]
|
|
801ad32: 3301 adds r3, #1
|
|
801ad34: 781b ldrb r3, [r3, #0]
|
|
801ad36: f003 037f and.w r3, r3, #127 ; 0x7f
|
|
801ad3a: b2db uxtb r3, r3
|
|
801ad3c: 74fb strb r3, [r7, #19]
|
|
mcastaddr.addr[4] = ip4_addr3(ipaddr);
|
|
801ad3e: 687b ldr r3, [r7, #4]
|
|
801ad40: 3302 adds r3, #2
|
|
801ad42: 781b ldrb r3, [r3, #0]
|
|
801ad44: 753b strb r3, [r7, #20]
|
|
mcastaddr.addr[5] = ip4_addr4(ipaddr);
|
|
801ad46: 687b ldr r3, [r7, #4]
|
|
801ad48: 3303 adds r3, #3
|
|
801ad4a: 781b ldrb r3, [r3, #0]
|
|
801ad4c: 757b strb r3, [r7, #21]
|
|
/* destination Ethernet address is multicast */
|
|
dest = &mcastaddr;
|
|
801ad4e: f107 0310 add.w r3, r7, #16
|
|
801ad52: 61fb str r3, [r7, #28]
|
|
801ad54: e090 b.n 801ae78 <etharp_output+0x1c4>
|
|
/* unicast destination IP address? */
|
|
} else {
|
|
netif_addr_idx_t i;
|
|
/* outside local network? if so, this can neither be a global broadcast nor
|
|
a subnet broadcast. */
|
|
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
|
|
801ad56: 687b ldr r3, [r7, #4]
|
|
801ad58: 681a ldr r2, [r3, #0]
|
|
801ad5a: 68fb ldr r3, [r7, #12]
|
|
801ad5c: 3304 adds r3, #4
|
|
801ad5e: 681b ldr r3, [r3, #0]
|
|
801ad60: 405a eors r2, r3
|
|
801ad62: 68fb ldr r3, [r7, #12]
|
|
801ad64: 3308 adds r3, #8
|
|
801ad66: 681b ldr r3, [r3, #0]
|
|
801ad68: 4013 ands r3, r2
|
|
801ad6a: 2b00 cmp r3, #0
|
|
801ad6c: d012 beq.n 801ad94 <etharp_output+0xe0>
|
|
!ip4_addr_islinklocal(ipaddr)) {
|
|
801ad6e: 687b ldr r3, [r7, #4]
|
|
801ad70: 681b ldr r3, [r3, #0]
|
|
801ad72: b29b uxth r3, r3
|
|
if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) &&
|
|
801ad74: f64f 62a9 movw r2, #65193 ; 0xfea9
|
|
801ad78: 4293 cmp r3, r2
|
|
801ad7a: d00b beq.n 801ad94 <etharp_output+0xe0>
|
|
dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr);
|
|
if (dst_addr == NULL)
|
|
#endif /* LWIP_HOOK_ETHARP_GET_GW */
|
|
{
|
|
/* interface has default gateway? */
|
|
if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) {
|
|
801ad7c: 68fb ldr r3, [r7, #12]
|
|
801ad7e: 330c adds r3, #12
|
|
801ad80: 681b ldr r3, [r3, #0]
|
|
801ad82: 2b00 cmp r3, #0
|
|
801ad84: d003 beq.n 801ad8e <etharp_output+0xda>
|
|
/* send to hardware address of default gateway IP address */
|
|
dst_addr = netif_ip4_gw(netif);
|
|
801ad86: 68fb ldr r3, [r7, #12]
|
|
801ad88: 330c adds r3, #12
|
|
801ad8a: 61bb str r3, [r7, #24]
|
|
801ad8c: e002 b.n 801ad94 <etharp_output+0xe0>
|
|
/* no default gateway available */
|
|
} else {
|
|
/* no route to destination error (default gateway missing) */
|
|
return ERR_RTE;
|
|
801ad8e: f06f 0303 mvn.w r3, #3
|
|
801ad92: e07d b.n 801ae90 <etharp_output+0x1dc>
|
|
if (netif->hints != NULL) {
|
|
/* per-pcb cached entry was given */
|
|
netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint;
|
|
if (etharp_cached_entry < ARP_TABLE_SIZE) {
|
|
#endif /* LWIP_NETIF_HWADDRHINT */
|
|
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
|
|
801ad94: 4b46 ldr r3, [pc, #280] ; (801aeb0 <etharp_output+0x1fc>)
|
|
801ad96: 781b ldrb r3, [r3, #0]
|
|
801ad98: 4619 mov r1, r3
|
|
801ad9a: 4a46 ldr r2, [pc, #280] ; (801aeb4 <etharp_output+0x200>)
|
|
801ad9c: 460b mov r3, r1
|
|
801ad9e: 005b lsls r3, r3, #1
|
|
801ada0: 440b add r3, r1
|
|
801ada2: 00db lsls r3, r3, #3
|
|
801ada4: 4413 add r3, r2
|
|
801ada6: 3314 adds r3, #20
|
|
801ada8: 781b ldrb r3, [r3, #0]
|
|
801adaa: 2b01 cmp r3, #1
|
|
801adac: d925 bls.n 801adfa <etharp_output+0x146>
|
|
#if ETHARP_TABLE_MATCH_NETIF
|
|
(arp_table[etharp_cached_entry].netif == netif) &&
|
|
801adae: 4b40 ldr r3, [pc, #256] ; (801aeb0 <etharp_output+0x1fc>)
|
|
801adb0: 781b ldrb r3, [r3, #0]
|
|
801adb2: 4619 mov r1, r3
|
|
801adb4: 4a3f ldr r2, [pc, #252] ; (801aeb4 <etharp_output+0x200>)
|
|
801adb6: 460b mov r3, r1
|
|
801adb8: 005b lsls r3, r3, #1
|
|
801adba: 440b add r3, r1
|
|
801adbc: 00db lsls r3, r3, #3
|
|
801adbe: 4413 add r3, r2
|
|
801adc0: 3308 adds r3, #8
|
|
801adc2: 681b ldr r3, [r3, #0]
|
|
if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) &&
|
|
801adc4: 68fa ldr r2, [r7, #12]
|
|
801adc6: 429a cmp r2, r3
|
|
801adc8: d117 bne.n 801adfa <etharp_output+0x146>
|
|
#endif
|
|
(ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) {
|
|
801adca: 69bb ldr r3, [r7, #24]
|
|
801adcc: 681a ldr r2, [r3, #0]
|
|
801adce: 4b38 ldr r3, [pc, #224] ; (801aeb0 <etharp_output+0x1fc>)
|
|
801add0: 781b ldrb r3, [r3, #0]
|
|
801add2: 4618 mov r0, r3
|
|
801add4: 4937 ldr r1, [pc, #220] ; (801aeb4 <etharp_output+0x200>)
|
|
801add6: 4603 mov r3, r0
|
|
801add8: 005b lsls r3, r3, #1
|
|
801adda: 4403 add r3, r0
|
|
801addc: 00db lsls r3, r3, #3
|
|
801adde: 440b add r3, r1
|
|
801ade0: 3304 adds r3, #4
|
|
801ade2: 681b ldr r3, [r3, #0]
|
|
(arp_table[etharp_cached_entry].netif == netif) &&
|
|
801ade4: 429a cmp r2, r3
|
|
801ade6: d108 bne.n 801adfa <etharp_output+0x146>
|
|
/* the per-pcb-cached entry is stable and the right one! */
|
|
ETHARP_STATS_INC(etharp.cachehit);
|
|
return etharp_output_to_arp_index(netif, q, etharp_cached_entry);
|
|
801ade8: 4b31 ldr r3, [pc, #196] ; (801aeb0 <etharp_output+0x1fc>)
|
|
801adea: 781b ldrb r3, [r3, #0]
|
|
801adec: 461a mov r2, r3
|
|
801adee: 68b9 ldr r1, [r7, #8]
|
|
801adf0: 68f8 ldr r0, [r7, #12]
|
|
801adf2: f7ff fec5 bl 801ab80 <etharp_output_to_arp_index>
|
|
801adf6: 4603 mov r3, r0
|
|
801adf8: e04a b.n 801ae90 <etharp_output+0x1dc>
|
|
}
|
|
#endif /* LWIP_NETIF_HWADDRHINT */
|
|
|
|
/* find stable entry: do this here since this is a critical path for
|
|
throughput and etharp_find_entry() is kind of slow */
|
|
for (i = 0; i < ARP_TABLE_SIZE; i++) {
|
|
801adfa: 2300 movs r3, #0
|
|
801adfc: 75fb strb r3, [r7, #23]
|
|
801adfe: e031 b.n 801ae64 <etharp_output+0x1b0>
|
|
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
|
|
801ae00: 7dfa ldrb r2, [r7, #23]
|
|
801ae02: 492c ldr r1, [pc, #176] ; (801aeb4 <etharp_output+0x200>)
|
|
801ae04: 4613 mov r3, r2
|
|
801ae06: 005b lsls r3, r3, #1
|
|
801ae08: 4413 add r3, r2
|
|
801ae0a: 00db lsls r3, r3, #3
|
|
801ae0c: 440b add r3, r1
|
|
801ae0e: 3314 adds r3, #20
|
|
801ae10: 781b ldrb r3, [r3, #0]
|
|
801ae12: 2b01 cmp r3, #1
|
|
801ae14: d923 bls.n 801ae5e <etharp_output+0x1aa>
|
|
#if ETHARP_TABLE_MATCH_NETIF
|
|
(arp_table[i].netif == netif) &&
|
|
801ae16: 7dfa ldrb r2, [r7, #23]
|
|
801ae18: 4926 ldr r1, [pc, #152] ; (801aeb4 <etharp_output+0x200>)
|
|
801ae1a: 4613 mov r3, r2
|
|
801ae1c: 005b lsls r3, r3, #1
|
|
801ae1e: 4413 add r3, r2
|
|
801ae20: 00db lsls r3, r3, #3
|
|
801ae22: 440b add r3, r1
|
|
801ae24: 3308 adds r3, #8
|
|
801ae26: 681b ldr r3, [r3, #0]
|
|
if ((arp_table[i].state >= ETHARP_STATE_STABLE) &&
|
|
801ae28: 68fa ldr r2, [r7, #12]
|
|
801ae2a: 429a cmp r2, r3
|
|
801ae2c: d117 bne.n 801ae5e <etharp_output+0x1aa>
|
|
#endif
|
|
(ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) {
|
|
801ae2e: 69bb ldr r3, [r7, #24]
|
|
801ae30: 6819 ldr r1, [r3, #0]
|
|
801ae32: 7dfa ldrb r2, [r7, #23]
|
|
801ae34: 481f ldr r0, [pc, #124] ; (801aeb4 <etharp_output+0x200>)
|
|
801ae36: 4613 mov r3, r2
|
|
801ae38: 005b lsls r3, r3, #1
|
|
801ae3a: 4413 add r3, r2
|
|
801ae3c: 00db lsls r3, r3, #3
|
|
801ae3e: 4403 add r3, r0
|
|
801ae40: 3304 adds r3, #4
|
|
801ae42: 681b ldr r3, [r3, #0]
|
|
(arp_table[i].netif == netif) &&
|
|
801ae44: 4299 cmp r1, r3
|
|
801ae46: d10a bne.n 801ae5e <etharp_output+0x1aa>
|
|
/* found an existing, stable entry */
|
|
ETHARP_SET_ADDRHINT(netif, i);
|
|
801ae48: 4a19 ldr r2, [pc, #100] ; (801aeb0 <etharp_output+0x1fc>)
|
|
801ae4a: 7dfb ldrb r3, [r7, #23]
|
|
801ae4c: 7013 strb r3, [r2, #0]
|
|
return etharp_output_to_arp_index(netif, q, i);
|
|
801ae4e: 7dfb ldrb r3, [r7, #23]
|
|
801ae50: 461a mov r2, r3
|
|
801ae52: 68b9 ldr r1, [r7, #8]
|
|
801ae54: 68f8 ldr r0, [r7, #12]
|
|
801ae56: f7ff fe93 bl 801ab80 <etharp_output_to_arp_index>
|
|
801ae5a: 4603 mov r3, r0
|
|
801ae5c: e018 b.n 801ae90 <etharp_output+0x1dc>
|
|
for (i = 0; i < ARP_TABLE_SIZE; i++) {
|
|
801ae5e: 7dfb ldrb r3, [r7, #23]
|
|
801ae60: 3301 adds r3, #1
|
|
801ae62: 75fb strb r3, [r7, #23]
|
|
801ae64: 7dfb ldrb r3, [r7, #23]
|
|
801ae66: 2b09 cmp r3, #9
|
|
801ae68: d9ca bls.n 801ae00 <etharp_output+0x14c>
|
|
}
|
|
}
|
|
/* no stable entry found, use the (slower) query function:
|
|
queue on destination Ethernet address belonging to ipaddr */
|
|
return etharp_query(netif, dst_addr, q);
|
|
801ae6a: 68ba ldr r2, [r7, #8]
|
|
801ae6c: 69b9 ldr r1, [r7, #24]
|
|
801ae6e: 68f8 ldr r0, [r7, #12]
|
|
801ae70: f000 f822 bl 801aeb8 <etharp_query>
|
|
801ae74: 4603 mov r3, r0
|
|
801ae76: e00b b.n 801ae90 <etharp_output+0x1dc>
|
|
}
|
|
|
|
/* continuation for multicast/broadcast destinations */
|
|
/* obtain source Ethernet address of the given interface */
|
|
/* send packet directly on the link */
|
|
return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP);
|
|
801ae78: 68fb ldr r3, [r7, #12]
|
|
801ae7a: f103 022a add.w r2, r3, #42 ; 0x2a
|
|
801ae7e: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
801ae82: 9300 str r3, [sp, #0]
|
|
801ae84: 69fb ldr r3, [r7, #28]
|
|
801ae86: 68b9 ldr r1, [r7, #8]
|
|
801ae88: 68f8 ldr r0, [r7, #12]
|
|
801ae8a: f001 fd57 bl 801c93c <ethernet_output>
|
|
801ae8e: 4603 mov r3, r0
|
|
}
|
|
801ae90: 4618 mov r0, r3
|
|
801ae92: 3720 adds r7, #32
|
|
801ae94: 46bd mov sp, r7
|
|
801ae96: bd80 pop {r7, pc}
|
|
801ae98: 08020738 .word 0x08020738
|
|
801ae9c: 08020888 .word 0x08020888
|
|
801aea0: 080207b0 .word 0x080207b0
|
|
801aea4: 080208d8 .word 0x080208d8
|
|
801aea8: 08020878 .word 0x08020878
|
|
801aeac: 08022e70 .word 0x08022e70
|
|
801aeb0: 20008868 .word 0x20008868
|
|
801aeb4: 20008778 .word 0x20008778
|
|
|
|
0801aeb8 <etharp_query>:
|
|
* - ERR_ARG Non-unicast address given, those will not appear in ARP cache.
|
|
*
|
|
*/
|
|
err_t
|
|
etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q)
|
|
{
|
|
801aeb8: b580 push {r7, lr}
|
|
801aeba: b08c sub sp, #48 ; 0x30
|
|
801aebc: af02 add r7, sp, #8
|
|
801aebe: 60f8 str r0, [r7, #12]
|
|
801aec0: 60b9 str r1, [r7, #8]
|
|
801aec2: 607a str r2, [r7, #4]
|
|
struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr;
|
|
801aec4: 68fb ldr r3, [r7, #12]
|
|
801aec6: 332a adds r3, #42 ; 0x2a
|
|
801aec8: 617b str r3, [r7, #20]
|
|
err_t result = ERR_MEM;
|
|
801aeca: 23ff movs r3, #255 ; 0xff
|
|
801aecc: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
int is_new_entry = 0;
|
|
801aed0: 2300 movs r3, #0
|
|
801aed2: 623b str r3, [r7, #32]
|
|
s16_t i_err;
|
|
netif_addr_idx_t i;
|
|
|
|
/* non-unicast address? */
|
|
if (ip4_addr_isbroadcast(ipaddr, netif) ||
|
|
801aed4: 68bb ldr r3, [r7, #8]
|
|
801aed6: 681b ldr r3, [r3, #0]
|
|
801aed8: 68f9 ldr r1, [r7, #12]
|
|
801aeda: 4618 mov r0, r3
|
|
801aedc: f000 fe2a bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801aee0: 4603 mov r3, r0
|
|
801aee2: 2b00 cmp r3, #0
|
|
801aee4: d10c bne.n 801af00 <etharp_query+0x48>
|
|
ip4_addr_ismulticast(ipaddr) ||
|
|
801aee6: 68bb ldr r3, [r7, #8]
|
|
801aee8: 681b ldr r3, [r3, #0]
|
|
801aeea: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
if (ip4_addr_isbroadcast(ipaddr, netif) ||
|
|
801aeee: 2be0 cmp r3, #224 ; 0xe0
|
|
801aef0: d006 beq.n 801af00 <etharp_query+0x48>
|
|
ip4_addr_ismulticast(ipaddr) ||
|
|
801aef2: 68bb ldr r3, [r7, #8]
|
|
801aef4: 2b00 cmp r3, #0
|
|
801aef6: d003 beq.n 801af00 <etharp_query+0x48>
|
|
ip4_addr_isany(ipaddr)) {
|
|
801aef8: 68bb ldr r3, [r7, #8]
|
|
801aefa: 681b ldr r3, [r3, #0]
|
|
801aefc: 2b00 cmp r3, #0
|
|
801aefe: d102 bne.n 801af06 <etharp_query+0x4e>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n"));
|
|
return ERR_ARG;
|
|
801af00: f06f 030f mvn.w r3, #15
|
|
801af04: e102 b.n 801b10c <etharp_query+0x254>
|
|
}
|
|
|
|
/* find entry in ARP cache, ask to create entry if queueing packet */
|
|
i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif);
|
|
801af06: 68fa ldr r2, [r7, #12]
|
|
801af08: 2101 movs r1, #1
|
|
801af0a: 68b8 ldr r0, [r7, #8]
|
|
801af0c: f7ff fb5c bl 801a5c8 <etharp_find_entry>
|
|
801af10: 4603 mov r3, r0
|
|
801af12: 827b strh r3, [r7, #18]
|
|
|
|
/* could not find or create entry? */
|
|
if (i_err < 0) {
|
|
801af14: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
801af18: 2b00 cmp r3, #0
|
|
801af1a: da02 bge.n 801af22 <etharp_query+0x6a>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n"));
|
|
if (q) {
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n"));
|
|
ETHARP_STATS_INC(etharp.memerr);
|
|
}
|
|
return (err_t)i_err;
|
|
801af1c: 8a7b ldrh r3, [r7, #18]
|
|
801af1e: b25b sxtb r3, r3
|
|
801af20: e0f4 b.n 801b10c <etharp_query+0x254>
|
|
}
|
|
LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX);
|
|
801af22: 8a7b ldrh r3, [r7, #18]
|
|
801af24: 2b7e cmp r3, #126 ; 0x7e
|
|
801af26: d906 bls.n 801af36 <etharp_query+0x7e>
|
|
801af28: 4b7a ldr r3, [pc, #488] ; (801b114 <etharp_query+0x25c>)
|
|
801af2a: f240 32c1 movw r2, #961 ; 0x3c1
|
|
801af2e: 497a ldr r1, [pc, #488] ; (801b118 <etharp_query+0x260>)
|
|
801af30: 487a ldr r0, [pc, #488] ; (801b11c <etharp_query+0x264>)
|
|
801af32: f001 fec1 bl 801ccb8 <iprintf>
|
|
i = (netif_addr_idx_t)i_err;
|
|
801af36: 8a7b ldrh r3, [r7, #18]
|
|
801af38: 747b strb r3, [r7, #17]
|
|
|
|
/* mark a fresh entry as pending (we just sent a request) */
|
|
if (arp_table[i].state == ETHARP_STATE_EMPTY) {
|
|
801af3a: 7c7a ldrb r2, [r7, #17]
|
|
801af3c: 4978 ldr r1, [pc, #480] ; (801b120 <etharp_query+0x268>)
|
|
801af3e: 4613 mov r3, r2
|
|
801af40: 005b lsls r3, r3, #1
|
|
801af42: 4413 add r3, r2
|
|
801af44: 00db lsls r3, r3, #3
|
|
801af46: 440b add r3, r1
|
|
801af48: 3314 adds r3, #20
|
|
801af4a: 781b ldrb r3, [r3, #0]
|
|
801af4c: 2b00 cmp r3, #0
|
|
801af4e: d115 bne.n 801af7c <etharp_query+0xc4>
|
|
is_new_entry = 1;
|
|
801af50: 2301 movs r3, #1
|
|
801af52: 623b str r3, [r7, #32]
|
|
arp_table[i].state = ETHARP_STATE_PENDING;
|
|
801af54: 7c7a ldrb r2, [r7, #17]
|
|
801af56: 4972 ldr r1, [pc, #456] ; (801b120 <etharp_query+0x268>)
|
|
801af58: 4613 mov r3, r2
|
|
801af5a: 005b lsls r3, r3, #1
|
|
801af5c: 4413 add r3, r2
|
|
801af5e: 00db lsls r3, r3, #3
|
|
801af60: 440b add r3, r1
|
|
801af62: 3314 adds r3, #20
|
|
801af64: 2201 movs r2, #1
|
|
801af66: 701a strb r2, [r3, #0]
|
|
/* record network interface for re-sending arp request in etharp_tmr */
|
|
arp_table[i].netif = netif;
|
|
801af68: 7c7a ldrb r2, [r7, #17]
|
|
801af6a: 496d ldr r1, [pc, #436] ; (801b120 <etharp_query+0x268>)
|
|
801af6c: 4613 mov r3, r2
|
|
801af6e: 005b lsls r3, r3, #1
|
|
801af70: 4413 add r3, r2
|
|
801af72: 00db lsls r3, r3, #3
|
|
801af74: 440b add r3, r1
|
|
801af76: 3308 adds r3, #8
|
|
801af78: 68fa ldr r2, [r7, #12]
|
|
801af7a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* { i is either a STABLE or (new or existing) PENDING entry } */
|
|
LWIP_ASSERT("arp_table[i].state == PENDING or STABLE",
|
|
801af7c: 7c7a ldrb r2, [r7, #17]
|
|
801af7e: 4968 ldr r1, [pc, #416] ; (801b120 <etharp_query+0x268>)
|
|
801af80: 4613 mov r3, r2
|
|
801af82: 005b lsls r3, r3, #1
|
|
801af84: 4413 add r3, r2
|
|
801af86: 00db lsls r3, r3, #3
|
|
801af88: 440b add r3, r1
|
|
801af8a: 3314 adds r3, #20
|
|
801af8c: 781b ldrb r3, [r3, #0]
|
|
801af8e: 2b01 cmp r3, #1
|
|
801af90: d011 beq.n 801afb6 <etharp_query+0xfe>
|
|
801af92: 7c7a ldrb r2, [r7, #17]
|
|
801af94: 4962 ldr r1, [pc, #392] ; (801b120 <etharp_query+0x268>)
|
|
801af96: 4613 mov r3, r2
|
|
801af98: 005b lsls r3, r3, #1
|
|
801af9a: 4413 add r3, r2
|
|
801af9c: 00db lsls r3, r3, #3
|
|
801af9e: 440b add r3, r1
|
|
801afa0: 3314 adds r3, #20
|
|
801afa2: 781b ldrb r3, [r3, #0]
|
|
801afa4: 2b01 cmp r3, #1
|
|
801afa6: d806 bhi.n 801afb6 <etharp_query+0xfe>
|
|
801afa8: 4b5a ldr r3, [pc, #360] ; (801b114 <etharp_query+0x25c>)
|
|
801afaa: f240 32cf movw r2, #975 ; 0x3cf
|
|
801afae: 495d ldr r1, [pc, #372] ; (801b124 <etharp_query+0x26c>)
|
|
801afb0: 485a ldr r0, [pc, #360] ; (801b11c <etharp_query+0x264>)
|
|
801afb2: f001 fe81 bl 801ccb8 <iprintf>
|
|
((arp_table[i].state == ETHARP_STATE_PENDING) ||
|
|
(arp_table[i].state >= ETHARP_STATE_STABLE)));
|
|
|
|
/* do we have a new entry? or an implicit query request? */
|
|
if (is_new_entry || (q == NULL)) {
|
|
801afb6: 6a3b ldr r3, [r7, #32]
|
|
801afb8: 2b00 cmp r3, #0
|
|
801afba: d102 bne.n 801afc2 <etharp_query+0x10a>
|
|
801afbc: 687b ldr r3, [r7, #4]
|
|
801afbe: 2b00 cmp r3, #0
|
|
801afc0: d10c bne.n 801afdc <etharp_query+0x124>
|
|
/* try to resolve it; send out ARP request */
|
|
result = etharp_request(netif, ipaddr);
|
|
801afc2: 68b9 ldr r1, [r7, #8]
|
|
801afc4: 68f8 ldr r0, [r7, #12]
|
|
801afc6: f000 f963 bl 801b290 <etharp_request>
|
|
801afca: 4603 mov r3, r0
|
|
801afcc: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
/* ARP request couldn't be sent */
|
|
/* We don't re-send arp request in etharp_tmr, but we still queue packets,
|
|
since this failure could be temporary, and the next packet calling
|
|
etharp_query again could lead to sending the queued packets. */
|
|
}
|
|
if (q == NULL) {
|
|
801afd0: 687b ldr r3, [r7, #4]
|
|
801afd2: 2b00 cmp r3, #0
|
|
801afd4: d102 bne.n 801afdc <etharp_query+0x124>
|
|
return result;
|
|
801afd6: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
801afda: e097 b.n 801b10c <etharp_query+0x254>
|
|
}
|
|
}
|
|
|
|
/* packet given? */
|
|
LWIP_ASSERT("q != NULL", q != NULL);
|
|
801afdc: 687b ldr r3, [r7, #4]
|
|
801afde: 2b00 cmp r3, #0
|
|
801afe0: d106 bne.n 801aff0 <etharp_query+0x138>
|
|
801afe2: 4b4c ldr r3, [pc, #304] ; (801b114 <etharp_query+0x25c>)
|
|
801afe4: f240 32e1 movw r2, #993 ; 0x3e1
|
|
801afe8: 494f ldr r1, [pc, #316] ; (801b128 <etharp_query+0x270>)
|
|
801afea: 484c ldr r0, [pc, #304] ; (801b11c <etharp_query+0x264>)
|
|
801afec: f001 fe64 bl 801ccb8 <iprintf>
|
|
/* stable entry? */
|
|
if (arp_table[i].state >= ETHARP_STATE_STABLE) {
|
|
801aff0: 7c7a ldrb r2, [r7, #17]
|
|
801aff2: 494b ldr r1, [pc, #300] ; (801b120 <etharp_query+0x268>)
|
|
801aff4: 4613 mov r3, r2
|
|
801aff6: 005b lsls r3, r3, #1
|
|
801aff8: 4413 add r3, r2
|
|
801affa: 00db lsls r3, r3, #3
|
|
801affc: 440b add r3, r1
|
|
801affe: 3314 adds r3, #20
|
|
801b000: 781b ldrb r3, [r3, #0]
|
|
801b002: 2b01 cmp r3, #1
|
|
801b004: d918 bls.n 801b038 <etharp_query+0x180>
|
|
/* we have a valid IP->Ethernet address mapping */
|
|
ETHARP_SET_ADDRHINT(netif, i);
|
|
801b006: 4a49 ldr r2, [pc, #292] ; (801b12c <etharp_query+0x274>)
|
|
801b008: 7c7b ldrb r3, [r7, #17]
|
|
801b00a: 7013 strb r3, [r2, #0]
|
|
/* send the packet */
|
|
result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP);
|
|
801b00c: 7c7a ldrb r2, [r7, #17]
|
|
801b00e: 4613 mov r3, r2
|
|
801b010: 005b lsls r3, r3, #1
|
|
801b012: 4413 add r3, r2
|
|
801b014: 00db lsls r3, r3, #3
|
|
801b016: 3308 adds r3, #8
|
|
801b018: 4a41 ldr r2, [pc, #260] ; (801b120 <etharp_query+0x268>)
|
|
801b01a: 4413 add r3, r2
|
|
801b01c: 1d1a adds r2, r3, #4
|
|
801b01e: f44f 6300 mov.w r3, #2048 ; 0x800
|
|
801b022: 9300 str r3, [sp, #0]
|
|
801b024: 4613 mov r3, r2
|
|
801b026: 697a ldr r2, [r7, #20]
|
|
801b028: 6879 ldr r1, [r7, #4]
|
|
801b02a: 68f8 ldr r0, [r7, #12]
|
|
801b02c: f001 fc86 bl 801c93c <ethernet_output>
|
|
801b030: 4603 mov r3, r0
|
|
801b032: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
801b036: e067 b.n 801b108 <etharp_query+0x250>
|
|
/* pending entry? (either just created or already pending */
|
|
} else if (arp_table[i].state == ETHARP_STATE_PENDING) {
|
|
801b038: 7c7a ldrb r2, [r7, #17]
|
|
801b03a: 4939 ldr r1, [pc, #228] ; (801b120 <etharp_query+0x268>)
|
|
801b03c: 4613 mov r3, r2
|
|
801b03e: 005b lsls r3, r3, #1
|
|
801b040: 4413 add r3, r2
|
|
801b042: 00db lsls r3, r3, #3
|
|
801b044: 440b add r3, r1
|
|
801b046: 3314 adds r3, #20
|
|
801b048: 781b ldrb r3, [r3, #0]
|
|
801b04a: 2b01 cmp r3, #1
|
|
801b04c: d15c bne.n 801b108 <etharp_query+0x250>
|
|
/* entry is still pending, queue the given packet 'q' */
|
|
struct pbuf *p;
|
|
int copy_needed = 0;
|
|
801b04e: 2300 movs r3, #0
|
|
801b050: 61bb str r3, [r7, #24]
|
|
/* IF q includes a pbuf that must be copied, copy the whole chain into a
|
|
* new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */
|
|
p = q;
|
|
801b052: 687b ldr r3, [r7, #4]
|
|
801b054: 61fb str r3, [r7, #28]
|
|
while (p) {
|
|
801b056: e01c b.n 801b092 <etharp_query+0x1da>
|
|
LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0));
|
|
801b058: 69fb ldr r3, [r7, #28]
|
|
801b05a: 895a ldrh r2, [r3, #10]
|
|
801b05c: 69fb ldr r3, [r7, #28]
|
|
801b05e: 891b ldrh r3, [r3, #8]
|
|
801b060: 429a cmp r2, r3
|
|
801b062: d10a bne.n 801b07a <etharp_query+0x1c2>
|
|
801b064: 69fb ldr r3, [r7, #28]
|
|
801b066: 681b ldr r3, [r3, #0]
|
|
801b068: 2b00 cmp r3, #0
|
|
801b06a: d006 beq.n 801b07a <etharp_query+0x1c2>
|
|
801b06c: 4b29 ldr r3, [pc, #164] ; (801b114 <etharp_query+0x25c>)
|
|
801b06e: f240 32f1 movw r2, #1009 ; 0x3f1
|
|
801b072: 492f ldr r1, [pc, #188] ; (801b130 <etharp_query+0x278>)
|
|
801b074: 4829 ldr r0, [pc, #164] ; (801b11c <etharp_query+0x264>)
|
|
801b076: f001 fe1f bl 801ccb8 <iprintf>
|
|
if (PBUF_NEEDS_COPY(p)) {
|
|
801b07a: 69fb ldr r3, [r7, #28]
|
|
801b07c: 7b1b ldrb r3, [r3, #12]
|
|
801b07e: f003 0340 and.w r3, r3, #64 ; 0x40
|
|
801b082: 2b00 cmp r3, #0
|
|
801b084: d002 beq.n 801b08c <etharp_query+0x1d4>
|
|
copy_needed = 1;
|
|
801b086: 2301 movs r3, #1
|
|
801b088: 61bb str r3, [r7, #24]
|
|
break;
|
|
801b08a: e005 b.n 801b098 <etharp_query+0x1e0>
|
|
}
|
|
p = p->next;
|
|
801b08c: 69fb ldr r3, [r7, #28]
|
|
801b08e: 681b ldr r3, [r3, #0]
|
|
801b090: 61fb str r3, [r7, #28]
|
|
while (p) {
|
|
801b092: 69fb ldr r3, [r7, #28]
|
|
801b094: 2b00 cmp r3, #0
|
|
801b096: d1df bne.n 801b058 <etharp_query+0x1a0>
|
|
}
|
|
if (copy_needed) {
|
|
801b098: 69bb ldr r3, [r7, #24]
|
|
801b09a: 2b00 cmp r3, #0
|
|
801b09c: d007 beq.n 801b0ae <etharp_query+0x1f6>
|
|
/* copy the whole packet into new pbufs */
|
|
p = pbuf_clone(PBUF_LINK, PBUF_RAM, q);
|
|
801b09e: 687a ldr r2, [r7, #4]
|
|
801b0a0: f44f 7120 mov.w r1, #640 ; 0x280
|
|
801b0a4: 200e movs r0, #14
|
|
801b0a6: f7f7 fb4f bl 8012748 <pbuf_clone>
|
|
801b0aa: 61f8 str r0, [r7, #28]
|
|
801b0ac: e004 b.n 801b0b8 <etharp_query+0x200>
|
|
} else {
|
|
/* referencing the old pbuf is enough */
|
|
p = q;
|
|
801b0ae: 687b ldr r3, [r7, #4]
|
|
801b0b0: 61fb str r3, [r7, #28]
|
|
pbuf_ref(p);
|
|
801b0b2: 69f8 ldr r0, [r7, #28]
|
|
801b0b4: f7f7 f976 bl 80123a4 <pbuf_ref>
|
|
}
|
|
/* packet could be taken over? */
|
|
if (p != NULL) {
|
|
801b0b8: 69fb ldr r3, [r7, #28]
|
|
801b0ba: 2b00 cmp r3, #0
|
|
801b0bc: d021 beq.n 801b102 <etharp_query+0x24a>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
|
|
result = ERR_MEM;
|
|
}
|
|
#else /* ARP_QUEUEING */
|
|
/* always queue one packet per ARP request only, freeing a previously queued packet */
|
|
if (arp_table[i].q != NULL) {
|
|
801b0be: 7c7a ldrb r2, [r7, #17]
|
|
801b0c0: 4917 ldr r1, [pc, #92] ; (801b120 <etharp_query+0x268>)
|
|
801b0c2: 4613 mov r3, r2
|
|
801b0c4: 005b lsls r3, r3, #1
|
|
801b0c6: 4413 add r3, r2
|
|
801b0c8: 00db lsls r3, r3, #3
|
|
801b0ca: 440b add r3, r1
|
|
801b0cc: 681b ldr r3, [r3, #0]
|
|
801b0ce: 2b00 cmp r3, #0
|
|
801b0d0: d00a beq.n 801b0e8 <etharp_query+0x230>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
|
|
pbuf_free(arp_table[i].q);
|
|
801b0d2: 7c7a ldrb r2, [r7, #17]
|
|
801b0d4: 4912 ldr r1, [pc, #72] ; (801b120 <etharp_query+0x268>)
|
|
801b0d6: 4613 mov r3, r2
|
|
801b0d8: 005b lsls r3, r3, #1
|
|
801b0da: 4413 add r3, r2
|
|
801b0dc: 00db lsls r3, r3, #3
|
|
801b0de: 440b add r3, r1
|
|
801b0e0: 681b ldr r3, [r3, #0]
|
|
801b0e2: 4618 mov r0, r3
|
|
801b0e4: f7f7 f8b8 bl 8012258 <pbuf_free>
|
|
}
|
|
arp_table[i].q = p;
|
|
801b0e8: 7c7a ldrb r2, [r7, #17]
|
|
801b0ea: 490d ldr r1, [pc, #52] ; (801b120 <etharp_query+0x268>)
|
|
801b0ec: 4613 mov r3, r2
|
|
801b0ee: 005b lsls r3, r3, #1
|
|
801b0f0: 4413 add r3, r2
|
|
801b0f2: 00db lsls r3, r3, #3
|
|
801b0f4: 440b add r3, r1
|
|
801b0f6: 69fa ldr r2, [r7, #28]
|
|
801b0f8: 601a str r2, [r3, #0]
|
|
result = ERR_OK;
|
|
801b0fa: 2300 movs r3, #0
|
|
801b0fc: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
801b100: e002 b.n 801b108 <etharp_query+0x250>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i));
|
|
#endif /* ARP_QUEUEING */
|
|
} else {
|
|
ETHARP_STATS_INC(etharp.memerr);
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q));
|
|
result = ERR_MEM;
|
|
801b102: 23ff movs r3, #255 ; 0xff
|
|
801b104: f887 3027 strb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
}
|
|
return result;
|
|
801b108: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27
|
|
}
|
|
801b10c: 4618 mov r0, r3
|
|
801b10e: 3728 adds r7, #40 ; 0x28
|
|
801b110: 46bd mov sp, r7
|
|
801b112: bd80 pop {r7, pc}
|
|
801b114: 08020738 .word 0x08020738
|
|
801b118: 080208e4 .word 0x080208e4
|
|
801b11c: 080207b0 .word 0x080207b0
|
|
801b120: 20008778 .word 0x20008778
|
|
801b124: 080208f4 .word 0x080208f4
|
|
801b128: 080208d8 .word 0x080208d8
|
|
801b12c: 20008868 .word 0x20008868
|
|
801b130: 0802091c .word 0x0802091c
|
|
|
|
0801b134 <etharp_raw>:
|
|
etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr,
|
|
const struct eth_addr *ethdst_addr,
|
|
const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr,
|
|
const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr,
|
|
const u16_t opcode)
|
|
{
|
|
801b134: b580 push {r7, lr}
|
|
801b136: b08a sub sp, #40 ; 0x28
|
|
801b138: af02 add r7, sp, #8
|
|
801b13a: 60f8 str r0, [r7, #12]
|
|
801b13c: 60b9 str r1, [r7, #8]
|
|
801b13e: 607a str r2, [r7, #4]
|
|
801b140: 603b str r3, [r7, #0]
|
|
struct pbuf *p;
|
|
err_t result = ERR_OK;
|
|
801b142: 2300 movs r3, #0
|
|
801b144: 77fb strb r3, [r7, #31]
|
|
struct etharp_hdr *hdr;
|
|
|
|
LWIP_ASSERT("netif != NULL", netif != NULL);
|
|
801b146: 68fb ldr r3, [r7, #12]
|
|
801b148: 2b00 cmp r3, #0
|
|
801b14a: d106 bne.n 801b15a <etharp_raw+0x26>
|
|
801b14c: 4b3a ldr r3, [pc, #232] ; (801b238 <etharp_raw+0x104>)
|
|
801b14e: f240 4257 movw r2, #1111 ; 0x457
|
|
801b152: 493a ldr r1, [pc, #232] ; (801b23c <etharp_raw+0x108>)
|
|
801b154: 483a ldr r0, [pc, #232] ; (801b240 <etharp_raw+0x10c>)
|
|
801b156: f001 fdaf bl 801ccb8 <iprintf>
|
|
|
|
/* allocate a pbuf for the outgoing ARP request packet */
|
|
p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM);
|
|
801b15a: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801b15e: 211c movs r1, #28
|
|
801b160: 200e movs r0, #14
|
|
801b162: f7f6 fd99 bl 8011c98 <pbuf_alloc>
|
|
801b166: 61b8 str r0, [r7, #24]
|
|
/* could allocate a pbuf for an ARP request? */
|
|
if (p == NULL) {
|
|
801b168: 69bb ldr r3, [r7, #24]
|
|
801b16a: 2b00 cmp r3, #0
|
|
801b16c: d102 bne.n 801b174 <etharp_raw+0x40>
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
|
|
("etharp_raw: could not allocate pbuf for ARP request.\n"));
|
|
ETHARP_STATS_INC(etharp.memerr);
|
|
return ERR_MEM;
|
|
801b16e: f04f 33ff mov.w r3, #4294967295
|
|
801b172: e05d b.n 801b230 <etharp_raw+0xfc>
|
|
}
|
|
LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr",
|
|
801b174: 69bb ldr r3, [r7, #24]
|
|
801b176: 895b ldrh r3, [r3, #10]
|
|
801b178: 2b1b cmp r3, #27
|
|
801b17a: d806 bhi.n 801b18a <etharp_raw+0x56>
|
|
801b17c: 4b2e ldr r3, [pc, #184] ; (801b238 <etharp_raw+0x104>)
|
|
801b17e: f240 4263 movw r2, #1123 ; 0x463
|
|
801b182: 4930 ldr r1, [pc, #192] ; (801b244 <etharp_raw+0x110>)
|
|
801b184: 482e ldr r0, [pc, #184] ; (801b240 <etharp_raw+0x10c>)
|
|
801b186: f001 fd97 bl 801ccb8 <iprintf>
|
|
(p->len >= SIZEOF_ETHARP_HDR));
|
|
|
|
hdr = (struct etharp_hdr *)p->payload;
|
|
801b18a: 69bb ldr r3, [r7, #24]
|
|
801b18c: 685b ldr r3, [r3, #4]
|
|
801b18e: 617b str r3, [r7, #20]
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n"));
|
|
hdr->opcode = lwip_htons(opcode);
|
|
801b190: 8ebb ldrh r3, [r7, #52] ; 0x34
|
|
801b192: 4618 mov r0, r3
|
|
801b194: f7f5 fcac bl 8010af0 <lwip_htons>
|
|
801b198: 4603 mov r3, r0
|
|
801b19a: 461a mov r2, r3
|
|
801b19c: 697b ldr r3, [r7, #20]
|
|
801b19e: 80da strh r2, [r3, #6]
|
|
|
|
LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!",
|
|
801b1a0: 68fb ldr r3, [r7, #12]
|
|
801b1a2: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
801b1a6: 2b06 cmp r3, #6
|
|
801b1a8: d006 beq.n 801b1b8 <etharp_raw+0x84>
|
|
801b1aa: 4b23 ldr r3, [pc, #140] ; (801b238 <etharp_raw+0x104>)
|
|
801b1ac: f240 426a movw r2, #1130 ; 0x46a
|
|
801b1b0: 4925 ldr r1, [pc, #148] ; (801b248 <etharp_raw+0x114>)
|
|
801b1b2: 4823 ldr r0, [pc, #140] ; (801b240 <etharp_raw+0x10c>)
|
|
801b1b4: f001 fd80 bl 801ccb8 <iprintf>
|
|
(netif->hwaddr_len == ETH_HWADDR_LEN));
|
|
|
|
/* Write the ARP MAC-Addresses */
|
|
SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN);
|
|
801b1b8: 697b ldr r3, [r7, #20]
|
|
801b1ba: 3308 adds r3, #8
|
|
801b1bc: 2206 movs r2, #6
|
|
801b1be: 6839 ldr r1, [r7, #0]
|
|
801b1c0: 4618 mov r0, r3
|
|
801b1c2: f001 fd4c bl 801cc5e <memcpy>
|
|
SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN);
|
|
801b1c6: 697b ldr r3, [r7, #20]
|
|
801b1c8: 3312 adds r3, #18
|
|
801b1ca: 2206 movs r2, #6
|
|
801b1cc: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
801b1ce: 4618 mov r0, r3
|
|
801b1d0: f001 fd45 bl 801cc5e <memcpy>
|
|
/* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without
|
|
* structure packing. */
|
|
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr);
|
|
801b1d4: 697b ldr r3, [r7, #20]
|
|
801b1d6: 330e adds r3, #14
|
|
801b1d8: 6aba ldr r2, [r7, #40] ; 0x28
|
|
801b1da: 6812 ldr r2, [r2, #0]
|
|
801b1dc: 601a str r2, [r3, #0]
|
|
IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr);
|
|
801b1de: 697b ldr r3, [r7, #20]
|
|
801b1e0: 3318 adds r3, #24
|
|
801b1e2: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
801b1e4: 6812 ldr r2, [r2, #0]
|
|
801b1e6: 601a str r2, [r3, #0]
|
|
|
|
hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET);
|
|
801b1e8: 697b ldr r3, [r7, #20]
|
|
801b1ea: 2200 movs r2, #0
|
|
801b1ec: 701a strb r2, [r3, #0]
|
|
801b1ee: 2200 movs r2, #0
|
|
801b1f0: f042 0201 orr.w r2, r2, #1
|
|
801b1f4: 705a strb r2, [r3, #1]
|
|
hdr->proto = PP_HTONS(ETHTYPE_IP);
|
|
801b1f6: 697b ldr r3, [r7, #20]
|
|
801b1f8: 2200 movs r2, #0
|
|
801b1fa: f042 0208 orr.w r2, r2, #8
|
|
801b1fe: 709a strb r2, [r3, #2]
|
|
801b200: 2200 movs r2, #0
|
|
801b202: 70da strb r2, [r3, #3]
|
|
/* set hwlen and protolen */
|
|
hdr->hwlen = ETH_HWADDR_LEN;
|
|
801b204: 697b ldr r3, [r7, #20]
|
|
801b206: 2206 movs r2, #6
|
|
801b208: 711a strb r2, [r3, #4]
|
|
hdr->protolen = sizeof(ip4_addr_t);
|
|
801b20a: 697b ldr r3, [r7, #20]
|
|
801b20c: 2204 movs r2, #4
|
|
801b20e: 715a strb r2, [r3, #5]
|
|
if (ip4_addr_islinklocal(ipsrc_addr)) {
|
|
ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP);
|
|
} else
|
|
#endif /* LWIP_AUTOIP */
|
|
{
|
|
ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP);
|
|
801b210: f640 0306 movw r3, #2054 ; 0x806
|
|
801b214: 9300 str r3, [sp, #0]
|
|
801b216: 687b ldr r3, [r7, #4]
|
|
801b218: 68ba ldr r2, [r7, #8]
|
|
801b21a: 69b9 ldr r1, [r7, #24]
|
|
801b21c: 68f8 ldr r0, [r7, #12]
|
|
801b21e: f001 fb8d bl 801c93c <ethernet_output>
|
|
}
|
|
|
|
ETHARP_STATS_INC(etharp.xmit);
|
|
/* free ARP query packet */
|
|
pbuf_free(p);
|
|
801b222: 69b8 ldr r0, [r7, #24]
|
|
801b224: f7f7 f818 bl 8012258 <pbuf_free>
|
|
p = NULL;
|
|
801b228: 2300 movs r3, #0
|
|
801b22a: 61bb str r3, [r7, #24]
|
|
/* could not allocate pbuf for ARP request */
|
|
|
|
return result;
|
|
801b22c: f997 301f ldrsb.w r3, [r7, #31]
|
|
}
|
|
801b230: 4618 mov r0, r3
|
|
801b232: 3720 adds r7, #32
|
|
801b234: 46bd mov sp, r7
|
|
801b236: bd80 pop {r7, pc}
|
|
801b238: 08020738 .word 0x08020738
|
|
801b23c: 08020888 .word 0x08020888
|
|
801b240: 080207b0 .word 0x080207b0
|
|
801b244: 08020938 .word 0x08020938
|
|
801b248: 0802096c .word 0x0802096c
|
|
|
|
0801b24c <etharp_request_dst>:
|
|
* ERR_MEM if the ARP packet couldn't be allocated
|
|
* any other err_t on failure
|
|
*/
|
|
static err_t
|
|
etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr)
|
|
{
|
|
801b24c: b580 push {r7, lr}
|
|
801b24e: b088 sub sp, #32
|
|
801b250: af04 add r7, sp, #16
|
|
801b252: 60f8 str r0, [r7, #12]
|
|
801b254: 60b9 str r1, [r7, #8]
|
|
801b256: 607a str r2, [r7, #4]
|
|
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
|
|
801b258: 68fb ldr r3, [r7, #12]
|
|
801b25a: f103 012a add.w r1, r3, #42 ; 0x2a
|
|
(struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero,
|
|
801b25e: 68fb ldr r3, [r7, #12]
|
|
801b260: f103 002a add.w r0, r3, #42 ; 0x2a
|
|
801b264: 68fb ldr r3, [r7, #12]
|
|
801b266: 3304 adds r3, #4
|
|
return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr,
|
|
801b268: 2201 movs r2, #1
|
|
801b26a: 9203 str r2, [sp, #12]
|
|
801b26c: 68ba ldr r2, [r7, #8]
|
|
801b26e: 9202 str r2, [sp, #8]
|
|
801b270: 4a06 ldr r2, [pc, #24] ; (801b28c <etharp_request_dst+0x40>)
|
|
801b272: 9201 str r2, [sp, #4]
|
|
801b274: 9300 str r3, [sp, #0]
|
|
801b276: 4603 mov r3, r0
|
|
801b278: 687a ldr r2, [r7, #4]
|
|
801b27a: 68f8 ldr r0, [r7, #12]
|
|
801b27c: f7ff ff5a bl 801b134 <etharp_raw>
|
|
801b280: 4603 mov r3, r0
|
|
ipaddr, ARP_REQUEST);
|
|
}
|
|
801b282: 4618 mov r0, r3
|
|
801b284: 3710 adds r7, #16
|
|
801b286: 46bd mov sp, r7
|
|
801b288: bd80 pop {r7, pc}
|
|
801b28a: bf00 nop
|
|
801b28c: 08022e78 .word 0x08022e78
|
|
|
|
0801b290 <etharp_request>:
|
|
* ERR_MEM if the ARP packet couldn't be allocated
|
|
* any other err_t on failure
|
|
*/
|
|
err_t
|
|
etharp_request(struct netif *netif, const ip4_addr_t *ipaddr)
|
|
{
|
|
801b290: b580 push {r7, lr}
|
|
801b292: b082 sub sp, #8
|
|
801b294: af00 add r7, sp, #0
|
|
801b296: 6078 str r0, [r7, #4]
|
|
801b298: 6039 str r1, [r7, #0]
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n"));
|
|
return etharp_request_dst(netif, ipaddr, ðbroadcast);
|
|
801b29a: 4a05 ldr r2, [pc, #20] ; (801b2b0 <etharp_request+0x20>)
|
|
801b29c: 6839 ldr r1, [r7, #0]
|
|
801b29e: 6878 ldr r0, [r7, #4]
|
|
801b2a0: f7ff ffd4 bl 801b24c <etharp_request_dst>
|
|
801b2a4: 4603 mov r3, r0
|
|
}
|
|
801b2a6: 4618 mov r0, r3
|
|
801b2a8: 3708 adds r7, #8
|
|
801b2aa: 46bd mov sp, r7
|
|
801b2ac: bd80 pop {r7, pc}
|
|
801b2ae: bf00 nop
|
|
801b2b0: 08022e70 .word 0x08022e70
|
|
|
|
0801b2b4 <icmp_input>:
|
|
* @param p the icmp echo request packet, p->payload pointing to the icmp header
|
|
* @param inp the netif on which this packet was received
|
|
*/
|
|
void
|
|
icmp_input(struct pbuf *p, struct netif *inp)
|
|
{
|
|
801b2b4: b580 push {r7, lr}
|
|
801b2b6: b08e sub sp, #56 ; 0x38
|
|
801b2b8: af04 add r7, sp, #16
|
|
801b2ba: 6078 str r0, [r7, #4]
|
|
801b2bc: 6039 str r1, [r7, #0]
|
|
const ip4_addr_t *src;
|
|
|
|
ICMP_STATS_INC(icmp.recv);
|
|
MIB2_STATS_INC(mib2.icmpinmsgs);
|
|
|
|
iphdr_in = ip4_current_header();
|
|
801b2be: 4b79 ldr r3, [pc, #484] ; (801b4a4 <icmp_input+0x1f0>)
|
|
801b2c0: 689b ldr r3, [r3, #8]
|
|
801b2c2: 627b str r3, [r7, #36] ; 0x24
|
|
hlen = IPH_HL_BYTES(iphdr_in);
|
|
801b2c4: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801b2c6: 781b ldrb r3, [r3, #0]
|
|
801b2c8: f003 030f and.w r3, r3, #15
|
|
801b2cc: b2db uxtb r3, r3
|
|
801b2ce: 009b lsls r3, r3, #2
|
|
801b2d0: b2db uxtb r3, r3
|
|
801b2d2: 847b strh r3, [r7, #34] ; 0x22
|
|
if (hlen < IP_HLEN) {
|
|
801b2d4: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b2d6: 2b13 cmp r3, #19
|
|
801b2d8: f240 80cd bls.w 801b476 <icmp_input+0x1c2>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen));
|
|
goto lenerr;
|
|
}
|
|
if (p->len < sizeof(u16_t) * 2) {
|
|
801b2dc: 687b ldr r3, [r7, #4]
|
|
801b2de: 895b ldrh r3, [r3, #10]
|
|
801b2e0: 2b03 cmp r3, #3
|
|
801b2e2: f240 80ca bls.w 801b47a <icmp_input+0x1c6>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len));
|
|
goto lenerr;
|
|
}
|
|
|
|
type = *((u8_t *)p->payload);
|
|
801b2e6: 687b ldr r3, [r7, #4]
|
|
801b2e8: 685b ldr r3, [r3, #4]
|
|
801b2ea: 781b ldrb r3, [r3, #0]
|
|
801b2ec: f887 3021 strb.w r3, [r7, #33] ; 0x21
|
|
#ifdef LWIP_DEBUG
|
|
code = *(((u8_t *)p->payload) + 1);
|
|
/* if debug is enabled but debug statement below is somehow disabled: */
|
|
LWIP_UNUSED_ARG(code);
|
|
#endif /* LWIP_DEBUG */
|
|
switch (type) {
|
|
801b2f0: f897 3021 ldrb.w r3, [r7, #33] ; 0x21
|
|
801b2f4: 2b00 cmp r3, #0
|
|
801b2f6: f000 80b7 beq.w 801b468 <icmp_input+0x1b4>
|
|
801b2fa: 2b08 cmp r3, #8
|
|
801b2fc: f040 80b7 bne.w 801b46e <icmp_input+0x1ba>
|
|
(as obviously, an echo request has been sent, too). */
|
|
MIB2_STATS_INC(mib2.icmpinechoreps);
|
|
break;
|
|
case ICMP_ECHO:
|
|
MIB2_STATS_INC(mib2.icmpinechos);
|
|
src = ip4_current_dest_addr();
|
|
801b300: 4b69 ldr r3, [pc, #420] ; (801b4a8 <icmp_input+0x1f4>)
|
|
801b302: 61fb str r3, [r7, #28]
|
|
/* multicast destination address? */
|
|
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
|
|
801b304: 4b67 ldr r3, [pc, #412] ; (801b4a4 <icmp_input+0x1f0>)
|
|
801b306: 695b ldr r3, [r3, #20]
|
|
801b308: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
801b30c: 2be0 cmp r3, #224 ; 0xe0
|
|
801b30e: f000 80bb beq.w 801b488 <icmp_input+0x1d4>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n"));
|
|
goto icmperr;
|
|
#endif /* LWIP_MULTICAST_PING */
|
|
}
|
|
/* broadcast destination address? */
|
|
if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) {
|
|
801b312: 4b64 ldr r3, [pc, #400] ; (801b4a4 <icmp_input+0x1f0>)
|
|
801b314: 695a ldr r2, [r3, #20]
|
|
801b316: 4b63 ldr r3, [pc, #396] ; (801b4a4 <icmp_input+0x1f0>)
|
|
801b318: 681b ldr r3, [r3, #0]
|
|
801b31a: 4619 mov r1, r3
|
|
801b31c: 4610 mov r0, r2
|
|
801b31e: f000 fc09 bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801b322: 4603 mov r3, r0
|
|
801b324: 2b00 cmp r3, #0
|
|
801b326: f040 80b1 bne.w 801b48c <icmp_input+0x1d8>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n"));
|
|
goto icmperr;
|
|
#endif /* LWIP_BROADCAST_PING */
|
|
}
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n"));
|
|
if (p->tot_len < sizeof(struct icmp_echo_hdr)) {
|
|
801b32a: 687b ldr r3, [r7, #4]
|
|
801b32c: 891b ldrh r3, [r3, #8]
|
|
801b32e: 2b07 cmp r3, #7
|
|
801b330: f240 80a5 bls.w 801b47e <icmp_input+0x1ca>
|
|
return;
|
|
}
|
|
}
|
|
#endif
|
|
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN
|
|
if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
|
|
801b334: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b336: 330e adds r3, #14
|
|
801b338: 4619 mov r1, r3
|
|
801b33a: 6878 ldr r0, [r7, #4]
|
|
801b33c: f7f6 fef6 bl 801212c <pbuf_add_header>
|
|
801b340: 4603 mov r3, r0
|
|
801b342: 2b00 cmp r3, #0
|
|
801b344: d04b beq.n 801b3de <icmp_input+0x12a>
|
|
/* p is not big enough to contain link headers
|
|
* allocate a new one and copy p into it
|
|
*/
|
|
struct pbuf *r;
|
|
u16_t alloc_len = (u16_t)(p->tot_len + hlen);
|
|
801b346: 687b ldr r3, [r7, #4]
|
|
801b348: 891a ldrh r2, [r3, #8]
|
|
801b34a: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b34c: 4413 add r3, r2
|
|
801b34e: 837b strh r3, [r7, #26]
|
|
if (alloc_len < p->tot_len) {
|
|
801b350: 687b ldr r3, [r7, #4]
|
|
801b352: 891b ldrh r3, [r3, #8]
|
|
801b354: 8b7a ldrh r2, [r7, #26]
|
|
801b356: 429a cmp r2, r3
|
|
801b358: f0c0 809a bcc.w 801b490 <icmp_input+0x1dc>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n"));
|
|
goto icmperr;
|
|
}
|
|
/* allocate new packet buffer with space for link headers */
|
|
r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM);
|
|
801b35c: 8b7b ldrh r3, [r7, #26]
|
|
801b35e: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801b362: 4619 mov r1, r3
|
|
801b364: 200e movs r0, #14
|
|
801b366: f7f6 fc97 bl 8011c98 <pbuf_alloc>
|
|
801b36a: 6178 str r0, [r7, #20]
|
|
if (r == NULL) {
|
|
801b36c: 697b ldr r3, [r7, #20]
|
|
801b36e: 2b00 cmp r3, #0
|
|
801b370: f000 8090 beq.w 801b494 <icmp_input+0x1e0>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n"));
|
|
goto icmperr;
|
|
}
|
|
if (r->len < hlen + sizeof(struct icmp_echo_hdr)) {
|
|
801b374: 697b ldr r3, [r7, #20]
|
|
801b376: 895b ldrh r3, [r3, #10]
|
|
801b378: 461a mov r2, r3
|
|
801b37a: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b37c: 3308 adds r3, #8
|
|
801b37e: 429a cmp r2, r3
|
|
801b380: d203 bcs.n 801b38a <icmp_input+0xd6>
|
|
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header"));
|
|
pbuf_free(r);
|
|
801b382: 6978 ldr r0, [r7, #20]
|
|
801b384: f7f6 ff68 bl 8012258 <pbuf_free>
|
|
goto icmperr;
|
|
801b388: e085 b.n 801b496 <icmp_input+0x1e2>
|
|
}
|
|
/* copy the ip header */
|
|
MEMCPY(r->payload, iphdr_in, hlen);
|
|
801b38a: 697b ldr r3, [r7, #20]
|
|
801b38c: 685b ldr r3, [r3, #4]
|
|
801b38e: 8c7a ldrh r2, [r7, #34] ; 0x22
|
|
801b390: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
801b392: 4618 mov r0, r3
|
|
801b394: f001 fc63 bl 801cc5e <memcpy>
|
|
/* switch r->payload back to icmp header (cannot fail) */
|
|
if (pbuf_remove_header(r, hlen)) {
|
|
801b398: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b39a: 4619 mov r1, r3
|
|
801b39c: 6978 ldr r0, [r7, #20]
|
|
801b39e: f7f6 fed5 bl 801214c <pbuf_remove_header>
|
|
801b3a2: 4603 mov r3, r0
|
|
801b3a4: 2b00 cmp r3, #0
|
|
801b3a6: d009 beq.n 801b3bc <icmp_input+0x108>
|
|
LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0);
|
|
801b3a8: 4b40 ldr r3, [pc, #256] ; (801b4ac <icmp_input+0x1f8>)
|
|
801b3aa: 22b6 movs r2, #182 ; 0xb6
|
|
801b3ac: 4940 ldr r1, [pc, #256] ; (801b4b0 <icmp_input+0x1fc>)
|
|
801b3ae: 4841 ldr r0, [pc, #260] ; (801b4b4 <icmp_input+0x200>)
|
|
801b3b0: f001 fc82 bl 801ccb8 <iprintf>
|
|
pbuf_free(r);
|
|
801b3b4: 6978 ldr r0, [r7, #20]
|
|
801b3b6: f7f6 ff4f bl 8012258 <pbuf_free>
|
|
goto icmperr;
|
|
801b3ba: e06c b.n 801b496 <icmp_input+0x1e2>
|
|
}
|
|
/* copy the rest of the packet without ip header */
|
|
if (pbuf_copy(r, p) != ERR_OK) {
|
|
801b3bc: 6879 ldr r1, [r7, #4]
|
|
801b3be: 6978 ldr r0, [r7, #20]
|
|
801b3c0: f7f7 f87e bl 80124c0 <pbuf_copy>
|
|
801b3c4: 4603 mov r3, r0
|
|
801b3c6: 2b00 cmp r3, #0
|
|
801b3c8: d003 beq.n 801b3d2 <icmp_input+0x11e>
|
|
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed"));
|
|
pbuf_free(r);
|
|
801b3ca: 6978 ldr r0, [r7, #20]
|
|
801b3cc: f7f6 ff44 bl 8012258 <pbuf_free>
|
|
goto icmperr;
|
|
801b3d0: e061 b.n 801b496 <icmp_input+0x1e2>
|
|
}
|
|
/* free the original p */
|
|
pbuf_free(p);
|
|
801b3d2: 6878 ldr r0, [r7, #4]
|
|
801b3d4: f7f6 ff40 bl 8012258 <pbuf_free>
|
|
/* we now have an identical copy of p that has room for link headers */
|
|
p = r;
|
|
801b3d8: 697b ldr r3, [r7, #20]
|
|
801b3da: 607b str r3, [r7, #4]
|
|
801b3dc: e00f b.n 801b3fe <icmp_input+0x14a>
|
|
} else {
|
|
/* restore p->payload to point to icmp header (cannot fail) */
|
|
if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) {
|
|
801b3de: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b3e0: 330e adds r3, #14
|
|
801b3e2: 4619 mov r1, r3
|
|
801b3e4: 6878 ldr r0, [r7, #4]
|
|
801b3e6: f7f6 feb1 bl 801214c <pbuf_remove_header>
|
|
801b3ea: 4603 mov r3, r0
|
|
801b3ec: 2b00 cmp r3, #0
|
|
801b3ee: d006 beq.n 801b3fe <icmp_input+0x14a>
|
|
LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0);
|
|
801b3f0: 4b2e ldr r3, [pc, #184] ; (801b4ac <icmp_input+0x1f8>)
|
|
801b3f2: 22c7 movs r2, #199 ; 0xc7
|
|
801b3f4: 4930 ldr r1, [pc, #192] ; (801b4b8 <icmp_input+0x204>)
|
|
801b3f6: 482f ldr r0, [pc, #188] ; (801b4b4 <icmp_input+0x200>)
|
|
801b3f8: f001 fc5e bl 801ccb8 <iprintf>
|
|
goto icmperr;
|
|
801b3fc: e04b b.n 801b496 <icmp_input+0x1e2>
|
|
}
|
|
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */
|
|
/* At this point, all checks are OK. */
|
|
/* We generate an answer by switching the dest and src ip addresses,
|
|
* setting the icmp type to ECHO_RESPONSE and updating the checksum. */
|
|
iecho = (struct icmp_echo_hdr *)p->payload;
|
|
801b3fe: 687b ldr r3, [r7, #4]
|
|
801b400: 685b ldr r3, [r3, #4]
|
|
801b402: 613b str r3, [r7, #16]
|
|
if (pbuf_add_header(p, hlen)) {
|
|
801b404: 8c7b ldrh r3, [r7, #34] ; 0x22
|
|
801b406: 4619 mov r1, r3
|
|
801b408: 6878 ldr r0, [r7, #4]
|
|
801b40a: f7f6 fe8f bl 801212c <pbuf_add_header>
|
|
801b40e: 4603 mov r3, r0
|
|
801b410: 2b00 cmp r3, #0
|
|
801b412: d12b bne.n 801b46c <icmp_input+0x1b8>
|
|
LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet"));
|
|
} else {
|
|
err_t ret;
|
|
struct ip_hdr *iphdr = (struct ip_hdr *)p->payload;
|
|
801b414: 687b ldr r3, [r7, #4]
|
|
801b416: 685b ldr r3, [r3, #4]
|
|
801b418: 60fb str r3, [r7, #12]
|
|
ip4_addr_copy(iphdr->src, *src);
|
|
801b41a: 69fb ldr r3, [r7, #28]
|
|
801b41c: 681a ldr r2, [r3, #0]
|
|
801b41e: 68fb ldr r3, [r7, #12]
|
|
801b420: 60da str r2, [r3, #12]
|
|
ip4_addr_copy(iphdr->dest, *ip4_current_src_addr());
|
|
801b422: 4b20 ldr r3, [pc, #128] ; (801b4a4 <icmp_input+0x1f0>)
|
|
801b424: 691a ldr r2, [r3, #16]
|
|
801b426: 68fb ldr r3, [r7, #12]
|
|
801b428: 611a str r2, [r3, #16]
|
|
ICMPH_TYPE_SET(iecho, ICMP_ER);
|
|
801b42a: 693b ldr r3, [r7, #16]
|
|
801b42c: 2200 movs r2, #0
|
|
801b42e: 701a strb r2, [r3, #0]
|
|
else {
|
|
iecho->chksum = 0;
|
|
}
|
|
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */
|
|
#else /* CHECKSUM_GEN_ICMP */
|
|
iecho->chksum = 0;
|
|
801b430: 693b ldr r3, [r7, #16]
|
|
801b432: 2200 movs r2, #0
|
|
801b434: 709a strb r2, [r3, #2]
|
|
801b436: 2200 movs r2, #0
|
|
801b438: 70da strb r2, [r3, #3]
|
|
#endif /* CHECKSUM_GEN_ICMP */
|
|
|
|
/* Set the correct TTL and recalculate the header checksum. */
|
|
IPH_TTL_SET(iphdr, ICMP_TTL);
|
|
801b43a: 68fb ldr r3, [r7, #12]
|
|
801b43c: 22ff movs r2, #255 ; 0xff
|
|
801b43e: 721a strb r2, [r3, #8]
|
|
IPH_CHKSUM_SET(iphdr, 0);
|
|
801b440: 68fb ldr r3, [r7, #12]
|
|
801b442: 2200 movs r2, #0
|
|
801b444: 729a strb r2, [r3, #10]
|
|
801b446: 2200 movs r2, #0
|
|
801b448: 72da strb r2, [r3, #11]
|
|
MIB2_STATS_INC(mib2.icmpoutmsgs);
|
|
/* increase number of echo replies attempted to send */
|
|
MIB2_STATS_INC(mib2.icmpoutechoreps);
|
|
|
|
/* send an ICMP packet */
|
|
ret = ip4_output_if(p, src, LWIP_IP_HDRINCL,
|
|
801b44a: 683b ldr r3, [r7, #0]
|
|
801b44c: 9302 str r3, [sp, #8]
|
|
801b44e: 2301 movs r3, #1
|
|
801b450: 9301 str r3, [sp, #4]
|
|
801b452: 2300 movs r3, #0
|
|
801b454: 9300 str r3, [sp, #0]
|
|
801b456: 23ff movs r3, #255 ; 0xff
|
|
801b458: 2200 movs r2, #0
|
|
801b45a: 69f9 ldr r1, [r7, #28]
|
|
801b45c: 6878 ldr r0, [r7, #4]
|
|
801b45e: f000 fa91 bl 801b984 <ip4_output_if>
|
|
801b462: 4603 mov r3, r0
|
|
801b464: 72fb strb r3, [r7, #11]
|
|
ICMP_TTL, 0, IP_PROTO_ICMP, inp);
|
|
if (ret != ERR_OK) {
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret)));
|
|
}
|
|
}
|
|
break;
|
|
801b466: e001 b.n 801b46c <icmp_input+0x1b8>
|
|
break;
|
|
801b468: bf00 nop
|
|
801b46a: e000 b.n 801b46e <icmp_input+0x1ba>
|
|
break;
|
|
801b46c: bf00 nop
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n",
|
|
(s16_t)type, (s16_t)code));
|
|
ICMP_STATS_INC(icmp.proterr);
|
|
ICMP_STATS_INC(icmp.drop);
|
|
}
|
|
pbuf_free(p);
|
|
801b46e: 6878 ldr r0, [r7, #4]
|
|
801b470: f7f6 fef2 bl 8012258 <pbuf_free>
|
|
return;
|
|
801b474: e013 b.n 801b49e <icmp_input+0x1ea>
|
|
goto lenerr;
|
|
801b476: bf00 nop
|
|
801b478: e002 b.n 801b480 <icmp_input+0x1cc>
|
|
goto lenerr;
|
|
801b47a: bf00 nop
|
|
801b47c: e000 b.n 801b480 <icmp_input+0x1cc>
|
|
goto lenerr;
|
|
801b47e: bf00 nop
|
|
lenerr:
|
|
pbuf_free(p);
|
|
801b480: 6878 ldr r0, [r7, #4]
|
|
801b482: f7f6 fee9 bl 8012258 <pbuf_free>
|
|
ICMP_STATS_INC(icmp.lenerr);
|
|
MIB2_STATS_INC(mib2.icmpinerrors);
|
|
return;
|
|
801b486: e00a b.n 801b49e <icmp_input+0x1ea>
|
|
goto icmperr;
|
|
801b488: bf00 nop
|
|
801b48a: e004 b.n 801b496 <icmp_input+0x1e2>
|
|
goto icmperr;
|
|
801b48c: bf00 nop
|
|
801b48e: e002 b.n 801b496 <icmp_input+0x1e2>
|
|
goto icmperr;
|
|
801b490: bf00 nop
|
|
801b492: e000 b.n 801b496 <icmp_input+0x1e2>
|
|
goto icmperr;
|
|
801b494: bf00 nop
|
|
#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING
|
|
icmperr:
|
|
pbuf_free(p);
|
|
801b496: 6878 ldr r0, [r7, #4]
|
|
801b498: f7f6 fede bl 8012258 <pbuf_free>
|
|
ICMP_STATS_INC(icmp.err);
|
|
MIB2_STATS_INC(mib2.icmpinerrors);
|
|
return;
|
|
801b49c: bf00 nop
|
|
#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */
|
|
}
|
|
801b49e: 3728 adds r7, #40 ; 0x28
|
|
801b4a0: 46bd mov sp, r7
|
|
801b4a2: bd80 pop {r7, pc}
|
|
801b4a4: 2000c0c8 .word 0x2000c0c8
|
|
801b4a8: 2000c0dc .word 0x2000c0dc
|
|
801b4ac: 080209b0 .word 0x080209b0
|
|
801b4b0: 080209e8 .word 0x080209e8
|
|
801b4b4: 08020a20 .word 0x08020a20
|
|
801b4b8: 08020a48 .word 0x08020a48
|
|
|
|
0801b4bc <icmp_dest_unreach>:
|
|
* p->payload pointing to the IP header
|
|
* @param t type of the 'unreachable' packet
|
|
*/
|
|
void
|
|
icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t)
|
|
{
|
|
801b4bc: b580 push {r7, lr}
|
|
801b4be: b082 sub sp, #8
|
|
801b4c0: af00 add r7, sp, #0
|
|
801b4c2: 6078 str r0, [r7, #4]
|
|
801b4c4: 460b mov r3, r1
|
|
801b4c6: 70fb strb r3, [r7, #3]
|
|
MIB2_STATS_INC(mib2.icmpoutdestunreachs);
|
|
icmp_send_response(p, ICMP_DUR, t);
|
|
801b4c8: 78fb ldrb r3, [r7, #3]
|
|
801b4ca: 461a mov r2, r3
|
|
801b4cc: 2103 movs r1, #3
|
|
801b4ce: 6878 ldr r0, [r7, #4]
|
|
801b4d0: f000 f814 bl 801b4fc <icmp_send_response>
|
|
}
|
|
801b4d4: bf00 nop
|
|
801b4d6: 3708 adds r7, #8
|
|
801b4d8: 46bd mov sp, r7
|
|
801b4da: bd80 pop {r7, pc}
|
|
|
|
0801b4dc <icmp_time_exceeded>:
|
|
* p->payload pointing to the IP header
|
|
* @param t type of the 'time exceeded' packet
|
|
*/
|
|
void
|
|
icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t)
|
|
{
|
|
801b4dc: b580 push {r7, lr}
|
|
801b4de: b082 sub sp, #8
|
|
801b4e0: af00 add r7, sp, #0
|
|
801b4e2: 6078 str r0, [r7, #4]
|
|
801b4e4: 460b mov r3, r1
|
|
801b4e6: 70fb strb r3, [r7, #3]
|
|
MIB2_STATS_INC(mib2.icmpouttimeexcds);
|
|
icmp_send_response(p, ICMP_TE, t);
|
|
801b4e8: 78fb ldrb r3, [r7, #3]
|
|
801b4ea: 461a mov r2, r3
|
|
801b4ec: 210b movs r1, #11
|
|
801b4ee: 6878 ldr r0, [r7, #4]
|
|
801b4f0: f000 f804 bl 801b4fc <icmp_send_response>
|
|
}
|
|
801b4f4: bf00 nop
|
|
801b4f6: 3708 adds r7, #8
|
|
801b4f8: 46bd mov sp, r7
|
|
801b4fa: bd80 pop {r7, pc}
|
|
|
|
0801b4fc <icmp_send_response>:
|
|
* @param type Type of the ICMP header
|
|
* @param code Code of the ICMP header
|
|
*/
|
|
static void
|
|
icmp_send_response(struct pbuf *p, u8_t type, u8_t code)
|
|
{
|
|
801b4fc: b580 push {r7, lr}
|
|
801b4fe: b08c sub sp, #48 ; 0x30
|
|
801b500: af04 add r7, sp, #16
|
|
801b502: 6078 str r0, [r7, #4]
|
|
801b504: 460b mov r3, r1
|
|
801b506: 70fb strb r3, [r7, #3]
|
|
801b508: 4613 mov r3, r2
|
|
801b50a: 70bb strb r3, [r7, #2]
|
|
|
|
/* increase number of messages attempted to send */
|
|
MIB2_STATS_INC(mib2.icmpoutmsgs);
|
|
|
|
/* ICMP header + IP header + 8 bytes of data */
|
|
q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE,
|
|
801b50c: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801b510: 2124 movs r1, #36 ; 0x24
|
|
801b512: 2022 movs r0, #34 ; 0x22
|
|
801b514: f7f6 fbc0 bl 8011c98 <pbuf_alloc>
|
|
801b518: 61f8 str r0, [r7, #28]
|
|
PBUF_RAM);
|
|
if (q == NULL) {
|
|
801b51a: 69fb ldr r3, [r7, #28]
|
|
801b51c: 2b00 cmp r3, #0
|
|
801b51e: d04c beq.n 801b5ba <icmp_send_response+0xbe>
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n"));
|
|
MIB2_STATS_INC(mib2.icmpouterrors);
|
|
return;
|
|
}
|
|
LWIP_ASSERT("check that first pbuf can hold icmp message",
|
|
801b520: 69fb ldr r3, [r7, #28]
|
|
801b522: 895b ldrh r3, [r3, #10]
|
|
801b524: 2b23 cmp r3, #35 ; 0x23
|
|
801b526: d806 bhi.n 801b536 <icmp_send_response+0x3a>
|
|
801b528: 4b26 ldr r3, [pc, #152] ; (801b5c4 <icmp_send_response+0xc8>)
|
|
801b52a: f240 1269 movw r2, #361 ; 0x169
|
|
801b52e: 4926 ldr r1, [pc, #152] ; (801b5c8 <icmp_send_response+0xcc>)
|
|
801b530: 4826 ldr r0, [pc, #152] ; (801b5cc <icmp_send_response+0xd0>)
|
|
801b532: f001 fbc1 bl 801ccb8 <iprintf>
|
|
(q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE)));
|
|
|
|
iphdr = (struct ip_hdr *)p->payload;
|
|
801b536: 687b ldr r3, [r7, #4]
|
|
801b538: 685b ldr r3, [r3, #4]
|
|
801b53a: 61bb str r3, [r7, #24]
|
|
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src);
|
|
LWIP_DEBUGF(ICMP_DEBUG, (" to "));
|
|
ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest);
|
|
LWIP_DEBUGF(ICMP_DEBUG, ("\n"));
|
|
|
|
icmphdr = (struct icmp_echo_hdr *)q->payload;
|
|
801b53c: 69fb ldr r3, [r7, #28]
|
|
801b53e: 685b ldr r3, [r3, #4]
|
|
801b540: 617b str r3, [r7, #20]
|
|
icmphdr->type = type;
|
|
801b542: 697b ldr r3, [r7, #20]
|
|
801b544: 78fa ldrb r2, [r7, #3]
|
|
801b546: 701a strb r2, [r3, #0]
|
|
icmphdr->code = code;
|
|
801b548: 697b ldr r3, [r7, #20]
|
|
801b54a: 78ba ldrb r2, [r7, #2]
|
|
801b54c: 705a strb r2, [r3, #1]
|
|
icmphdr->id = 0;
|
|
801b54e: 697b ldr r3, [r7, #20]
|
|
801b550: 2200 movs r2, #0
|
|
801b552: 711a strb r2, [r3, #4]
|
|
801b554: 2200 movs r2, #0
|
|
801b556: 715a strb r2, [r3, #5]
|
|
icmphdr->seqno = 0;
|
|
801b558: 697b ldr r3, [r7, #20]
|
|
801b55a: 2200 movs r2, #0
|
|
801b55c: 719a strb r2, [r3, #6]
|
|
801b55e: 2200 movs r2, #0
|
|
801b560: 71da strb r2, [r3, #7]
|
|
|
|
/* copy fields from original packet */
|
|
SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload,
|
|
801b562: 69fb ldr r3, [r7, #28]
|
|
801b564: 685b ldr r3, [r3, #4]
|
|
801b566: f103 0008 add.w r0, r3, #8
|
|
801b56a: 687b ldr r3, [r7, #4]
|
|
801b56c: 685b ldr r3, [r3, #4]
|
|
801b56e: 221c movs r2, #28
|
|
801b570: 4619 mov r1, r3
|
|
801b572: f001 fb74 bl 801cc5e <memcpy>
|
|
IP_HLEN + ICMP_DEST_UNREACH_DATASIZE);
|
|
|
|
ip4_addr_copy(iphdr_src, iphdr->src);
|
|
801b576: 69bb ldr r3, [r7, #24]
|
|
801b578: 68db ldr r3, [r3, #12]
|
|
801b57a: 60fb str r3, [r7, #12]
|
|
ip4_addr_t iphdr_dst;
|
|
ip4_addr_copy(iphdr_dst, iphdr->dest);
|
|
netif = ip4_route_src(&iphdr_dst, &iphdr_src);
|
|
}
|
|
#else
|
|
netif = ip4_route(&iphdr_src);
|
|
801b57c: f107 030c add.w r3, r7, #12
|
|
801b580: 4618 mov r0, r3
|
|
801b582: f000 f825 bl 801b5d0 <ip4_route>
|
|
801b586: 6138 str r0, [r7, #16]
|
|
#endif
|
|
if (netif != NULL) {
|
|
801b588: 693b ldr r3, [r7, #16]
|
|
801b58a: 2b00 cmp r3, #0
|
|
801b58c: d011 beq.n 801b5b2 <icmp_send_response+0xb6>
|
|
/* calculate checksum */
|
|
icmphdr->chksum = 0;
|
|
801b58e: 697b ldr r3, [r7, #20]
|
|
801b590: 2200 movs r2, #0
|
|
801b592: 709a strb r2, [r3, #2]
|
|
801b594: 2200 movs r2, #0
|
|
801b596: 70da strb r2, [r3, #3]
|
|
IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) {
|
|
icmphdr->chksum = inet_chksum(icmphdr, q->len);
|
|
}
|
|
#endif
|
|
ICMP_STATS_INC(icmp.xmit);
|
|
ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif);
|
|
801b598: f107 020c add.w r2, r7, #12
|
|
801b59c: 693b ldr r3, [r7, #16]
|
|
801b59e: 9302 str r3, [sp, #8]
|
|
801b5a0: 2301 movs r3, #1
|
|
801b5a2: 9301 str r3, [sp, #4]
|
|
801b5a4: 2300 movs r3, #0
|
|
801b5a6: 9300 str r3, [sp, #0]
|
|
801b5a8: 23ff movs r3, #255 ; 0xff
|
|
801b5aa: 2100 movs r1, #0
|
|
801b5ac: 69f8 ldr r0, [r7, #28]
|
|
801b5ae: f000 f9e9 bl 801b984 <ip4_output_if>
|
|
}
|
|
pbuf_free(q);
|
|
801b5b2: 69f8 ldr r0, [r7, #28]
|
|
801b5b4: f7f6 fe50 bl 8012258 <pbuf_free>
|
|
801b5b8: e000 b.n 801b5bc <icmp_send_response+0xc0>
|
|
return;
|
|
801b5ba: bf00 nop
|
|
}
|
|
801b5bc: 3720 adds r7, #32
|
|
801b5be: 46bd mov sp, r7
|
|
801b5c0: bd80 pop {r7, pc}
|
|
801b5c2: bf00 nop
|
|
801b5c4: 080209b0 .word 0x080209b0
|
|
801b5c8: 08020a7c .word 0x08020a7c
|
|
801b5cc: 08020a20 .word 0x08020a20
|
|
|
|
0801b5d0 <ip4_route>:
|
|
* @param dest the destination IP address for which to find the route
|
|
* @return the netif on which to send to reach dest
|
|
*/
|
|
struct netif *
|
|
ip4_route(const ip4_addr_t *dest)
|
|
{
|
|
801b5d0: b480 push {r7}
|
|
801b5d2: b085 sub sp, #20
|
|
801b5d4: af00 add r7, sp, #0
|
|
801b5d6: 6078 str r0, [r7, #4]
|
|
|
|
/* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */
|
|
LWIP_UNUSED_ARG(dest);
|
|
|
|
/* iterate through netifs */
|
|
NETIF_FOREACH(netif) {
|
|
801b5d8: 4b33 ldr r3, [pc, #204] ; (801b6a8 <ip4_route+0xd8>)
|
|
801b5da: 681b ldr r3, [r3, #0]
|
|
801b5dc: 60fb str r3, [r7, #12]
|
|
801b5de: e036 b.n 801b64e <ip4_route+0x7e>
|
|
/* is the netif up, does it have a link and a valid address? */
|
|
if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) {
|
|
801b5e0: 68fb ldr r3, [r7, #12]
|
|
801b5e2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b5e6: f003 0301 and.w r3, r3, #1
|
|
801b5ea: b2db uxtb r3, r3
|
|
801b5ec: 2b00 cmp r3, #0
|
|
801b5ee: d02b beq.n 801b648 <ip4_route+0x78>
|
|
801b5f0: 68fb ldr r3, [r7, #12]
|
|
801b5f2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b5f6: 089b lsrs r3, r3, #2
|
|
801b5f8: f003 0301 and.w r3, r3, #1
|
|
801b5fc: b2db uxtb r3, r3
|
|
801b5fe: 2b00 cmp r3, #0
|
|
801b600: d022 beq.n 801b648 <ip4_route+0x78>
|
|
801b602: 68fb ldr r3, [r7, #12]
|
|
801b604: 3304 adds r3, #4
|
|
801b606: 681b ldr r3, [r3, #0]
|
|
801b608: 2b00 cmp r3, #0
|
|
801b60a: d01d beq.n 801b648 <ip4_route+0x78>
|
|
/* network mask matches? */
|
|
if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) {
|
|
801b60c: 687b ldr r3, [r7, #4]
|
|
801b60e: 681a ldr r2, [r3, #0]
|
|
801b610: 68fb ldr r3, [r7, #12]
|
|
801b612: 3304 adds r3, #4
|
|
801b614: 681b ldr r3, [r3, #0]
|
|
801b616: 405a eors r2, r3
|
|
801b618: 68fb ldr r3, [r7, #12]
|
|
801b61a: 3308 adds r3, #8
|
|
801b61c: 681b ldr r3, [r3, #0]
|
|
801b61e: 4013 ands r3, r2
|
|
801b620: 2b00 cmp r3, #0
|
|
801b622: d101 bne.n 801b628 <ip4_route+0x58>
|
|
/* return netif on which to forward IP packet */
|
|
return netif;
|
|
801b624: 68fb ldr r3, [r7, #12]
|
|
801b626: e038 b.n 801b69a <ip4_route+0xca>
|
|
}
|
|
/* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */
|
|
if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) {
|
|
801b628: 68fb ldr r3, [r7, #12]
|
|
801b62a: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b62e: f003 0302 and.w r3, r3, #2
|
|
801b632: 2b00 cmp r3, #0
|
|
801b634: d108 bne.n 801b648 <ip4_route+0x78>
|
|
801b636: 687b ldr r3, [r7, #4]
|
|
801b638: 681a ldr r2, [r3, #0]
|
|
801b63a: 68fb ldr r3, [r7, #12]
|
|
801b63c: 330c adds r3, #12
|
|
801b63e: 681b ldr r3, [r3, #0]
|
|
801b640: 429a cmp r2, r3
|
|
801b642: d101 bne.n 801b648 <ip4_route+0x78>
|
|
/* return netif on which to forward IP packet */
|
|
return netif;
|
|
801b644: 68fb ldr r3, [r7, #12]
|
|
801b646: e028 b.n 801b69a <ip4_route+0xca>
|
|
NETIF_FOREACH(netif) {
|
|
801b648: 68fb ldr r3, [r7, #12]
|
|
801b64a: 681b ldr r3, [r3, #0]
|
|
801b64c: 60fb str r3, [r7, #12]
|
|
801b64e: 68fb ldr r3, [r7, #12]
|
|
801b650: 2b00 cmp r3, #0
|
|
801b652: d1c5 bne.n 801b5e0 <ip4_route+0x10>
|
|
return netif;
|
|
}
|
|
#endif
|
|
#endif /* !LWIP_SINGLE_NETIF */
|
|
|
|
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
|
|
801b654: 4b15 ldr r3, [pc, #84] ; (801b6ac <ip4_route+0xdc>)
|
|
801b656: 681b ldr r3, [r3, #0]
|
|
801b658: 2b00 cmp r3, #0
|
|
801b65a: d01a beq.n 801b692 <ip4_route+0xc2>
|
|
801b65c: 4b13 ldr r3, [pc, #76] ; (801b6ac <ip4_route+0xdc>)
|
|
801b65e: 681b ldr r3, [r3, #0]
|
|
801b660: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b664: f003 0301 and.w r3, r3, #1
|
|
801b668: 2b00 cmp r3, #0
|
|
801b66a: d012 beq.n 801b692 <ip4_route+0xc2>
|
|
801b66c: 4b0f ldr r3, [pc, #60] ; (801b6ac <ip4_route+0xdc>)
|
|
801b66e: 681b ldr r3, [r3, #0]
|
|
801b670: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b674: f003 0304 and.w r3, r3, #4
|
|
801b678: 2b00 cmp r3, #0
|
|
801b67a: d00a beq.n 801b692 <ip4_route+0xc2>
|
|
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
|
|
801b67c: 4b0b ldr r3, [pc, #44] ; (801b6ac <ip4_route+0xdc>)
|
|
801b67e: 681b ldr r3, [r3, #0]
|
|
801b680: 3304 adds r3, #4
|
|
801b682: 681b ldr r3, [r3, #0]
|
|
if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) ||
|
|
801b684: 2b00 cmp r3, #0
|
|
801b686: d004 beq.n 801b692 <ip4_route+0xc2>
|
|
ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) {
|
|
801b688: 687b ldr r3, [r7, #4]
|
|
801b68a: 681b ldr r3, [r3, #0]
|
|
801b68c: b2db uxtb r3, r3
|
|
801b68e: 2b7f cmp r3, #127 ; 0x7f
|
|
801b690: d101 bne.n 801b696 <ip4_route+0xc6>
|
|
If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n",
|
|
ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest)));
|
|
IP_STATS_INC(ip.rterr);
|
|
MIB2_STATS_INC(mib2.ipoutnoroutes);
|
|
return NULL;
|
|
801b692: 2300 movs r3, #0
|
|
801b694: e001 b.n 801b69a <ip4_route+0xca>
|
|
}
|
|
|
|
return netif_default;
|
|
801b696: 4b05 ldr r3, [pc, #20] ; (801b6ac <ip4_route+0xdc>)
|
|
801b698: 681b ldr r3, [r3, #0]
|
|
}
|
|
801b69a: 4618 mov r0, r3
|
|
801b69c: 3714 adds r7, #20
|
|
801b69e: 46bd mov sp, r7
|
|
801b6a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
801b6a4: 4770 bx lr
|
|
801b6a6: bf00 nop
|
|
801b6a8: 2000f7ec .word 0x2000f7ec
|
|
801b6ac: 2000f7f0 .word 0x2000f7f0
|
|
|
|
0801b6b0 <ip4_input_accept>:
|
|
#endif /* IP_FORWARD */
|
|
|
|
/** Return true if the current input packet should be accepted on this netif */
|
|
static int
|
|
ip4_input_accept(struct netif *netif)
|
|
{
|
|
801b6b0: b580 push {r7, lr}
|
|
801b6b2: b082 sub sp, #8
|
|
801b6b4: af00 add r7, sp, #0
|
|
801b6b6: 6078 str r0, [r7, #4]
|
|
ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
|
|
ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)),
|
|
ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif))));
|
|
|
|
/* interface is up and configured? */
|
|
if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) {
|
|
801b6b8: 687b ldr r3, [r7, #4]
|
|
801b6ba: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b6be: f003 0301 and.w r3, r3, #1
|
|
801b6c2: b2db uxtb r3, r3
|
|
801b6c4: 2b00 cmp r3, #0
|
|
801b6c6: d016 beq.n 801b6f6 <ip4_input_accept+0x46>
|
|
801b6c8: 687b ldr r3, [r7, #4]
|
|
801b6ca: 3304 adds r3, #4
|
|
801b6cc: 681b ldr r3, [r3, #0]
|
|
801b6ce: 2b00 cmp r3, #0
|
|
801b6d0: d011 beq.n 801b6f6 <ip4_input_accept+0x46>
|
|
/* unicast to this interface address? */
|
|
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
|
|
801b6d2: 4b0b ldr r3, [pc, #44] ; (801b700 <ip4_input_accept+0x50>)
|
|
801b6d4: 695a ldr r2, [r3, #20]
|
|
801b6d6: 687b ldr r3, [r7, #4]
|
|
801b6d8: 3304 adds r3, #4
|
|
801b6da: 681b ldr r3, [r3, #0]
|
|
801b6dc: 429a cmp r2, r3
|
|
801b6de: d008 beq.n 801b6f2 <ip4_input_accept+0x42>
|
|
/* or broadcast on this interface network address? */
|
|
ip4_addr_isbroadcast(ip4_current_dest_addr(), netif)
|
|
801b6e0: 4b07 ldr r3, [pc, #28] ; (801b700 <ip4_input_accept+0x50>)
|
|
801b6e2: 695b ldr r3, [r3, #20]
|
|
801b6e4: 6879 ldr r1, [r7, #4]
|
|
801b6e6: 4618 mov r0, r3
|
|
801b6e8: f000 fa24 bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801b6ec: 4603 mov r3, r0
|
|
if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) ||
|
|
801b6ee: 2b00 cmp r3, #0
|
|
801b6f0: d001 beq.n 801b6f6 <ip4_input_accept+0x46>
|
|
#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */
|
|
) {
|
|
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n",
|
|
netif->name[0], netif->name[1]));
|
|
/* accept on this netif */
|
|
return 1;
|
|
801b6f2: 2301 movs r3, #1
|
|
801b6f4: e000 b.n 801b6f8 <ip4_input_accept+0x48>
|
|
/* accept on this netif */
|
|
return 1;
|
|
}
|
|
#endif /* LWIP_AUTOIP */
|
|
}
|
|
return 0;
|
|
801b6f6: 2300 movs r3, #0
|
|
}
|
|
801b6f8: 4618 mov r0, r3
|
|
801b6fa: 3708 adds r7, #8
|
|
801b6fc: 46bd mov sp, r7
|
|
801b6fe: bd80 pop {r7, pc}
|
|
801b700: 2000c0c8 .word 0x2000c0c8
|
|
|
|
0801b704 <ip4_input>:
|
|
* @return ERR_OK if the packet was processed (could return ERR_* if it wasn't
|
|
* processed, but currently always returns ERR_OK)
|
|
*/
|
|
err_t
|
|
ip4_input(struct pbuf *p, struct netif *inp)
|
|
{
|
|
801b704: b580 push {r7, lr}
|
|
801b706: b088 sub sp, #32
|
|
801b708: af00 add r7, sp, #0
|
|
801b70a: 6078 str r0, [r7, #4]
|
|
801b70c: 6039 str r1, [r7, #0]
|
|
const struct ip_hdr *iphdr;
|
|
struct netif *netif;
|
|
u16_t iphdr_hlen;
|
|
u16_t iphdr_len;
|
|
#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP
|
|
int check_ip_src = 1;
|
|
801b70e: 2301 movs r3, #1
|
|
801b710: 617b str r3, [r7, #20]
|
|
|
|
IP_STATS_INC(ip.recv);
|
|
MIB2_STATS_INC(mib2.ipinreceives);
|
|
|
|
/* identify the IP header */
|
|
iphdr = (struct ip_hdr *)p->payload;
|
|
801b712: 687b ldr r3, [r7, #4]
|
|
801b714: 685b ldr r3, [r3, #4]
|
|
801b716: 61fb str r3, [r7, #28]
|
|
if (IPH_V(iphdr) != 4) {
|
|
801b718: 69fb ldr r3, [r7, #28]
|
|
801b71a: 781b ldrb r3, [r3, #0]
|
|
801b71c: 091b lsrs r3, r3, #4
|
|
801b71e: b2db uxtb r3, r3
|
|
801b720: 2b04 cmp r3, #4
|
|
801b722: d004 beq.n 801b72e <ip4_input+0x2a>
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr)));
|
|
ip4_debug_print(p);
|
|
pbuf_free(p);
|
|
801b724: 6878 ldr r0, [r7, #4]
|
|
801b726: f7f6 fd97 bl 8012258 <pbuf_free>
|
|
IP_STATS_INC(ip.err);
|
|
IP_STATS_INC(ip.drop);
|
|
MIB2_STATS_INC(mib2.ipinhdrerrors);
|
|
return ERR_OK;
|
|
801b72a: 2300 movs r3, #0
|
|
801b72c: e121 b.n 801b972 <ip4_input+0x26e>
|
|
return ERR_OK;
|
|
}
|
|
#endif
|
|
|
|
/* obtain IP header length in bytes */
|
|
iphdr_hlen = IPH_HL_BYTES(iphdr);
|
|
801b72e: 69fb ldr r3, [r7, #28]
|
|
801b730: 781b ldrb r3, [r3, #0]
|
|
801b732: f003 030f and.w r3, r3, #15
|
|
801b736: b2db uxtb r3, r3
|
|
801b738: 009b lsls r3, r3, #2
|
|
801b73a: b2db uxtb r3, r3
|
|
801b73c: 827b strh r3, [r7, #18]
|
|
/* obtain ip length in bytes */
|
|
iphdr_len = lwip_ntohs(IPH_LEN(iphdr));
|
|
801b73e: 69fb ldr r3, [r7, #28]
|
|
801b740: 885b ldrh r3, [r3, #2]
|
|
801b742: b29b uxth r3, r3
|
|
801b744: 4618 mov r0, r3
|
|
801b746: f7f5 f9d3 bl 8010af0 <lwip_htons>
|
|
801b74a: 4603 mov r3, r0
|
|
801b74c: 823b strh r3, [r7, #16]
|
|
|
|
/* Trim pbuf. This is especially required for packets < 60 bytes. */
|
|
if (iphdr_len < p->tot_len) {
|
|
801b74e: 687b ldr r3, [r7, #4]
|
|
801b750: 891b ldrh r3, [r3, #8]
|
|
801b752: 8a3a ldrh r2, [r7, #16]
|
|
801b754: 429a cmp r2, r3
|
|
801b756: d204 bcs.n 801b762 <ip4_input+0x5e>
|
|
pbuf_realloc(p, iphdr_len);
|
|
801b758: 8a3b ldrh r3, [r7, #16]
|
|
801b75a: 4619 mov r1, r3
|
|
801b75c: 6878 ldr r0, [r7, #4]
|
|
801b75e: f7f6 fbf5 bl 8011f4c <pbuf_realloc>
|
|
}
|
|
|
|
/* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */
|
|
if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) {
|
|
801b762: 687b ldr r3, [r7, #4]
|
|
801b764: 895b ldrh r3, [r3, #10]
|
|
801b766: 8a7a ldrh r2, [r7, #18]
|
|
801b768: 429a cmp r2, r3
|
|
801b76a: d807 bhi.n 801b77c <ip4_input+0x78>
|
|
801b76c: 687b ldr r3, [r7, #4]
|
|
801b76e: 891b ldrh r3, [r3, #8]
|
|
801b770: 8a3a ldrh r2, [r7, #16]
|
|
801b772: 429a cmp r2, r3
|
|
801b774: d802 bhi.n 801b77c <ip4_input+0x78>
|
|
801b776: 8a7b ldrh r3, [r7, #18]
|
|
801b778: 2b13 cmp r3, #19
|
|
801b77a: d804 bhi.n 801b786 <ip4_input+0x82>
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS,
|
|
("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n",
|
|
iphdr_len, p->tot_len));
|
|
}
|
|
/* free (drop) packet pbufs */
|
|
pbuf_free(p);
|
|
801b77c: 6878 ldr r0, [r7, #4]
|
|
801b77e: f7f6 fd6b bl 8012258 <pbuf_free>
|
|
IP_STATS_INC(ip.lenerr);
|
|
IP_STATS_INC(ip.drop);
|
|
MIB2_STATS_INC(mib2.ipindiscards);
|
|
return ERR_OK;
|
|
801b782: 2300 movs r3, #0
|
|
801b784: e0f5 b.n 801b972 <ip4_input+0x26e>
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* copy IP addresses to aligned ip_addr_t */
|
|
ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest);
|
|
801b786: 69fb ldr r3, [r7, #28]
|
|
801b788: 691b ldr r3, [r3, #16]
|
|
801b78a: 4a7c ldr r2, [pc, #496] ; (801b97c <ip4_input+0x278>)
|
|
801b78c: 6153 str r3, [r2, #20]
|
|
ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src);
|
|
801b78e: 69fb ldr r3, [r7, #28]
|
|
801b790: 68db ldr r3, [r3, #12]
|
|
801b792: 4a7a ldr r2, [pc, #488] ; (801b97c <ip4_input+0x278>)
|
|
801b794: 6113 str r3, [r2, #16]
|
|
|
|
/* match packet against an interface, i.e. is this packet for us? */
|
|
if (ip4_addr_ismulticast(ip4_current_dest_addr())) {
|
|
801b796: 4b79 ldr r3, [pc, #484] ; (801b97c <ip4_input+0x278>)
|
|
801b798: 695b ldr r3, [r3, #20]
|
|
801b79a: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
801b79e: 2be0 cmp r3, #224 ; 0xe0
|
|
801b7a0: d112 bne.n 801b7c8 <ip4_input+0xc4>
|
|
netif = inp;
|
|
} else {
|
|
netif = NULL;
|
|
}
|
|
#else /* LWIP_IGMP */
|
|
if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) {
|
|
801b7a2: 683b ldr r3, [r7, #0]
|
|
801b7a4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801b7a8: f003 0301 and.w r3, r3, #1
|
|
801b7ac: b2db uxtb r3, r3
|
|
801b7ae: 2b00 cmp r3, #0
|
|
801b7b0: d007 beq.n 801b7c2 <ip4_input+0xbe>
|
|
801b7b2: 683b ldr r3, [r7, #0]
|
|
801b7b4: 3304 adds r3, #4
|
|
801b7b6: 681b ldr r3, [r3, #0]
|
|
801b7b8: 2b00 cmp r3, #0
|
|
801b7ba: d002 beq.n 801b7c2 <ip4_input+0xbe>
|
|
netif = inp;
|
|
801b7bc: 683b ldr r3, [r7, #0]
|
|
801b7be: 61bb str r3, [r7, #24]
|
|
801b7c0: e02a b.n 801b818 <ip4_input+0x114>
|
|
} else {
|
|
netif = NULL;
|
|
801b7c2: 2300 movs r3, #0
|
|
801b7c4: 61bb str r3, [r7, #24]
|
|
801b7c6: e027 b.n 801b818 <ip4_input+0x114>
|
|
}
|
|
#endif /* LWIP_IGMP */
|
|
} else {
|
|
/* start trying with inp. if that's not acceptable, start walking the
|
|
list of configured netifs. */
|
|
if (ip4_input_accept(inp)) {
|
|
801b7c8: 6838 ldr r0, [r7, #0]
|
|
801b7ca: f7ff ff71 bl 801b6b0 <ip4_input_accept>
|
|
801b7ce: 4603 mov r3, r0
|
|
801b7d0: 2b00 cmp r3, #0
|
|
801b7d2: d002 beq.n 801b7da <ip4_input+0xd6>
|
|
netif = inp;
|
|
801b7d4: 683b ldr r3, [r7, #0]
|
|
801b7d6: 61bb str r3, [r7, #24]
|
|
801b7d8: e01e b.n 801b818 <ip4_input+0x114>
|
|
} else {
|
|
netif = NULL;
|
|
801b7da: 2300 movs r3, #0
|
|
801b7dc: 61bb str r3, [r7, #24]
|
|
#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF
|
|
/* Packets sent to the loopback address must not be accepted on an
|
|
* interface that does not have the loopback address assigned to it,
|
|
* unless a non-loopback interface is used for loopback traffic. */
|
|
if (!ip4_addr_isloopback(ip4_current_dest_addr()))
|
|
801b7de: 4b67 ldr r3, [pc, #412] ; (801b97c <ip4_input+0x278>)
|
|
801b7e0: 695b ldr r3, [r3, #20]
|
|
801b7e2: b2db uxtb r3, r3
|
|
801b7e4: 2b7f cmp r3, #127 ; 0x7f
|
|
801b7e6: d017 beq.n 801b818 <ip4_input+0x114>
|
|
#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */
|
|
{
|
|
#if !LWIP_SINGLE_NETIF
|
|
NETIF_FOREACH(netif) {
|
|
801b7e8: 4b65 ldr r3, [pc, #404] ; (801b980 <ip4_input+0x27c>)
|
|
801b7ea: 681b ldr r3, [r3, #0]
|
|
801b7ec: 61bb str r3, [r7, #24]
|
|
801b7ee: e00e b.n 801b80e <ip4_input+0x10a>
|
|
if (netif == inp) {
|
|
801b7f0: 69ba ldr r2, [r7, #24]
|
|
801b7f2: 683b ldr r3, [r7, #0]
|
|
801b7f4: 429a cmp r2, r3
|
|
801b7f6: d006 beq.n 801b806 <ip4_input+0x102>
|
|
/* we checked that before already */
|
|
continue;
|
|
}
|
|
if (ip4_input_accept(netif)) {
|
|
801b7f8: 69b8 ldr r0, [r7, #24]
|
|
801b7fa: f7ff ff59 bl 801b6b0 <ip4_input_accept>
|
|
801b7fe: 4603 mov r3, r0
|
|
801b800: 2b00 cmp r3, #0
|
|
801b802: d108 bne.n 801b816 <ip4_input+0x112>
|
|
801b804: e000 b.n 801b808 <ip4_input+0x104>
|
|
continue;
|
|
801b806: bf00 nop
|
|
NETIF_FOREACH(netif) {
|
|
801b808: 69bb ldr r3, [r7, #24]
|
|
801b80a: 681b ldr r3, [r3, #0]
|
|
801b80c: 61bb str r3, [r7, #24]
|
|
801b80e: 69bb ldr r3, [r7, #24]
|
|
801b810: 2b00 cmp r3, #0
|
|
801b812: d1ed bne.n 801b7f0 <ip4_input+0xec>
|
|
801b814: e000 b.n 801b818 <ip4_input+0x114>
|
|
break;
|
|
801b816: bf00 nop
|
|
* If you want to accept private broadcast communication while a netif is down,
|
|
* define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.:
|
|
*
|
|
* #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345))
|
|
*/
|
|
if (netif == NULL) {
|
|
801b818: 69bb ldr r3, [r7, #24]
|
|
801b81a: 2b00 cmp r3, #0
|
|
801b81c: d111 bne.n 801b842 <ip4_input+0x13e>
|
|
/* remote port is DHCP server? */
|
|
if (IPH_PROTO(iphdr) == IP_PROTO_UDP) {
|
|
801b81e: 69fb ldr r3, [r7, #28]
|
|
801b820: 7a5b ldrb r3, [r3, #9]
|
|
801b822: 2b11 cmp r3, #17
|
|
801b824: d10d bne.n 801b842 <ip4_input+0x13e>
|
|
const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen);
|
|
801b826: 8a7b ldrh r3, [r7, #18]
|
|
801b828: 69fa ldr r2, [r7, #28]
|
|
801b82a: 4413 add r3, r2
|
|
801b82c: 60fb str r3, [r7, #12]
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n",
|
|
lwip_ntohs(udphdr->dest)));
|
|
if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) {
|
|
801b82e: 68fb ldr r3, [r7, #12]
|
|
801b830: 885b ldrh r3, [r3, #2]
|
|
801b832: b29b uxth r3, r3
|
|
801b834: f5b3 4f88 cmp.w r3, #17408 ; 0x4400
|
|
801b838: d103 bne.n 801b842 <ip4_input+0x13e>
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n"));
|
|
netif = inp;
|
|
801b83a: 683b ldr r3, [r7, #0]
|
|
801b83c: 61bb str r3, [r7, #24]
|
|
check_ip_src = 0;
|
|
801b83e: 2300 movs r3, #0
|
|
801b840: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
|
|
|
|
/* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */
|
|
#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING
|
|
if (check_ip_src
|
|
801b842: 697b ldr r3, [r7, #20]
|
|
801b844: 2b00 cmp r3, #0
|
|
801b846: d017 beq.n 801b878 <ip4_input+0x174>
|
|
#if IP_ACCEPT_LINK_LAYER_ADDRESSING
|
|
/* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */
|
|
&& !ip4_addr_isany_val(*ip4_current_src_addr())
|
|
801b848: 4b4c ldr r3, [pc, #304] ; (801b97c <ip4_input+0x278>)
|
|
801b84a: 691b ldr r3, [r3, #16]
|
|
801b84c: 2b00 cmp r3, #0
|
|
801b84e: d013 beq.n 801b878 <ip4_input+0x174>
|
|
#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */
|
|
)
|
|
#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */
|
|
{
|
|
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
|
|
801b850: 4b4a ldr r3, [pc, #296] ; (801b97c <ip4_input+0x278>)
|
|
801b852: 691b ldr r3, [r3, #16]
|
|
801b854: 6839 ldr r1, [r7, #0]
|
|
801b856: 4618 mov r0, r3
|
|
801b858: f000 f96c bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801b85c: 4603 mov r3, r0
|
|
801b85e: 2b00 cmp r3, #0
|
|
801b860: d105 bne.n 801b86e <ip4_input+0x16a>
|
|
(ip4_addr_ismulticast(ip4_current_src_addr()))) {
|
|
801b862: 4b46 ldr r3, [pc, #280] ; (801b97c <ip4_input+0x278>)
|
|
801b864: 691b ldr r3, [r3, #16]
|
|
801b866: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) ||
|
|
801b86a: 2be0 cmp r3, #224 ; 0xe0
|
|
801b86c: d104 bne.n 801b878 <ip4_input+0x174>
|
|
/* packet source is not valid */
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n"));
|
|
/* free (drop) packet pbufs */
|
|
pbuf_free(p);
|
|
801b86e: 6878 ldr r0, [r7, #4]
|
|
801b870: f7f6 fcf2 bl 8012258 <pbuf_free>
|
|
IP_STATS_INC(ip.drop);
|
|
MIB2_STATS_INC(mib2.ipinaddrerrors);
|
|
MIB2_STATS_INC(mib2.ipindiscards);
|
|
return ERR_OK;
|
|
801b874: 2300 movs r3, #0
|
|
801b876: e07c b.n 801b972 <ip4_input+0x26e>
|
|
}
|
|
}
|
|
|
|
/* packet not for us? */
|
|
if (netif == NULL) {
|
|
801b878: 69bb ldr r3, [r7, #24]
|
|
801b87a: 2b00 cmp r3, #0
|
|
801b87c: d104 bne.n 801b888 <ip4_input+0x184>
|
|
{
|
|
IP_STATS_INC(ip.drop);
|
|
MIB2_STATS_INC(mib2.ipinaddrerrors);
|
|
MIB2_STATS_INC(mib2.ipindiscards);
|
|
}
|
|
pbuf_free(p);
|
|
801b87e: 6878 ldr r0, [r7, #4]
|
|
801b880: f7f6 fcea bl 8012258 <pbuf_free>
|
|
return ERR_OK;
|
|
801b884: 2300 movs r3, #0
|
|
801b886: e074 b.n 801b972 <ip4_input+0x26e>
|
|
}
|
|
/* packet consists of multiple fragments? */
|
|
if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) {
|
|
801b888: 69fb ldr r3, [r7, #28]
|
|
801b88a: 88db ldrh r3, [r3, #6]
|
|
801b88c: b29b uxth r3, r3
|
|
801b88e: 461a mov r2, r3
|
|
801b890: f64f 733f movw r3, #65343 ; 0xff3f
|
|
801b894: 4013 ands r3, r2
|
|
801b896: 2b00 cmp r3, #0
|
|
801b898: d00b beq.n 801b8b2 <ip4_input+0x1ae>
|
|
#if IP_REASSEMBLY /* packet fragment reassembly code present? */
|
|
LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n",
|
|
lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8)));
|
|
/* reassemble the packet*/
|
|
p = ip4_reass(p);
|
|
801b89a: 6878 ldr r0, [r7, #4]
|
|
801b89c: f000 fc90 bl 801c1c0 <ip4_reass>
|
|
801b8a0: 6078 str r0, [r7, #4]
|
|
/* packet not fully reassembled yet? */
|
|
if (p == NULL) {
|
|
801b8a2: 687b ldr r3, [r7, #4]
|
|
801b8a4: 2b00 cmp r3, #0
|
|
801b8a6: d101 bne.n 801b8ac <ip4_input+0x1a8>
|
|
return ERR_OK;
|
|
801b8a8: 2300 movs r3, #0
|
|
801b8aa: e062 b.n 801b972 <ip4_input+0x26e>
|
|
}
|
|
iphdr = (const struct ip_hdr *)p->payload;
|
|
801b8ac: 687b ldr r3, [r7, #4]
|
|
801b8ae: 685b ldr r3, [r3, #4]
|
|
801b8b0: 61fb str r3, [r7, #28]
|
|
/* send to upper layers */
|
|
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n"));
|
|
ip4_debug_print(p);
|
|
LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len));
|
|
|
|
ip_data.current_netif = netif;
|
|
801b8b2: 4a32 ldr r2, [pc, #200] ; (801b97c <ip4_input+0x278>)
|
|
801b8b4: 69bb ldr r3, [r7, #24]
|
|
801b8b6: 6013 str r3, [r2, #0]
|
|
ip_data.current_input_netif = inp;
|
|
801b8b8: 4a30 ldr r2, [pc, #192] ; (801b97c <ip4_input+0x278>)
|
|
801b8ba: 683b ldr r3, [r7, #0]
|
|
801b8bc: 6053 str r3, [r2, #4]
|
|
ip_data.current_ip4_header = iphdr;
|
|
801b8be: 4a2f ldr r2, [pc, #188] ; (801b97c <ip4_input+0x278>)
|
|
801b8c0: 69fb ldr r3, [r7, #28]
|
|
801b8c2: 6093 str r3, [r2, #8]
|
|
ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr);
|
|
801b8c4: 69fb ldr r3, [r7, #28]
|
|
801b8c6: 781b ldrb r3, [r3, #0]
|
|
801b8c8: f003 030f and.w r3, r3, #15
|
|
801b8cc: b2db uxtb r3, r3
|
|
801b8ce: 009b lsls r3, r3, #2
|
|
801b8d0: b2db uxtb r3, r3
|
|
801b8d2: b29a uxth r2, r3
|
|
801b8d4: 4b29 ldr r3, [pc, #164] ; (801b97c <ip4_input+0x278>)
|
|
801b8d6: 819a strh r2, [r3, #12]
|
|
/* raw input did not eat the packet? */
|
|
raw_status = raw_input(p, inp);
|
|
if (raw_status != RAW_INPUT_EATEN)
|
|
#endif /* LWIP_RAW */
|
|
{
|
|
pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */
|
|
801b8d8: 8a7b ldrh r3, [r7, #18]
|
|
801b8da: 4619 mov r1, r3
|
|
801b8dc: 6878 ldr r0, [r7, #4]
|
|
801b8de: f7f6 fc35 bl 801214c <pbuf_remove_header>
|
|
|
|
switch (IPH_PROTO(iphdr)) {
|
|
801b8e2: 69fb ldr r3, [r7, #28]
|
|
801b8e4: 7a5b ldrb r3, [r3, #9]
|
|
801b8e6: 2b06 cmp r3, #6
|
|
801b8e8: d009 beq.n 801b8fe <ip4_input+0x1fa>
|
|
801b8ea: 2b11 cmp r3, #17
|
|
801b8ec: d002 beq.n 801b8f4 <ip4_input+0x1f0>
|
|
801b8ee: 2b01 cmp r3, #1
|
|
801b8f0: d00a beq.n 801b908 <ip4_input+0x204>
|
|
801b8f2: e00e b.n 801b912 <ip4_input+0x20e>
|
|
case IP_PROTO_UDP:
|
|
#if LWIP_UDPLITE
|
|
case IP_PROTO_UDPLITE:
|
|
#endif /* LWIP_UDPLITE */
|
|
MIB2_STATS_INC(mib2.ipindelivers);
|
|
udp_input(p, inp);
|
|
801b8f4: 6839 ldr r1, [r7, #0]
|
|
801b8f6: 6878 ldr r0, [r7, #4]
|
|
801b8f8: f7fc fada bl 8017eb0 <udp_input>
|
|
break;
|
|
801b8fc: e026 b.n 801b94c <ip4_input+0x248>
|
|
#endif /* LWIP_UDP */
|
|
#if LWIP_TCP
|
|
case IP_PROTO_TCP:
|
|
MIB2_STATS_INC(mib2.ipindelivers);
|
|
tcp_input(p, inp);
|
|
801b8fe: 6839 ldr r1, [r7, #0]
|
|
801b900: 6878 ldr r0, [r7, #4]
|
|
801b902: f7f8 fae1 bl 8013ec8 <tcp_input>
|
|
break;
|
|
801b906: e021 b.n 801b94c <ip4_input+0x248>
|
|
#endif /* LWIP_TCP */
|
|
#if LWIP_ICMP
|
|
case IP_PROTO_ICMP:
|
|
MIB2_STATS_INC(mib2.ipindelivers);
|
|
icmp_input(p, inp);
|
|
801b908: 6839 ldr r1, [r7, #0]
|
|
801b90a: 6878 ldr r0, [r7, #4]
|
|
801b90c: f7ff fcd2 bl 801b2b4 <icmp_input>
|
|
break;
|
|
801b910: e01c b.n 801b94c <ip4_input+0x248>
|
|
} else
|
|
#endif /* LWIP_RAW */
|
|
{
|
|
#if LWIP_ICMP
|
|
/* send ICMP destination protocol unreachable unless is was a broadcast */
|
|
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
|
|
801b912: 4b1a ldr r3, [pc, #104] ; (801b97c <ip4_input+0x278>)
|
|
801b914: 695b ldr r3, [r3, #20]
|
|
801b916: 69b9 ldr r1, [r7, #24]
|
|
801b918: 4618 mov r0, r3
|
|
801b91a: f000 f90b bl 801bb34 <ip4_addr_isbroadcast_u32>
|
|
801b91e: 4603 mov r3, r0
|
|
801b920: 2b00 cmp r3, #0
|
|
801b922: d10f bne.n 801b944 <ip4_input+0x240>
|
|
!ip4_addr_ismulticast(ip4_current_dest_addr())) {
|
|
801b924: 4b15 ldr r3, [pc, #84] ; (801b97c <ip4_input+0x278>)
|
|
801b926: 695b ldr r3, [r3, #20]
|
|
801b928: f003 03f0 and.w r3, r3, #240 ; 0xf0
|
|
if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) &&
|
|
801b92c: 2be0 cmp r3, #224 ; 0xe0
|
|
801b92e: d009 beq.n 801b944 <ip4_input+0x240>
|
|
pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */
|
|
801b930: f9b7 3012 ldrsh.w r3, [r7, #18]
|
|
801b934: 4619 mov r1, r3
|
|
801b936: 6878 ldr r0, [r7, #4]
|
|
801b938: f7f6 fc7b bl 8012232 <pbuf_header_force>
|
|
icmp_dest_unreach(p, ICMP_DUR_PROTO);
|
|
801b93c: 2102 movs r1, #2
|
|
801b93e: 6878 ldr r0, [r7, #4]
|
|
801b940: f7ff fdbc bl 801b4bc <icmp_dest_unreach>
|
|
|
|
IP_STATS_INC(ip.proterr);
|
|
IP_STATS_INC(ip.drop);
|
|
MIB2_STATS_INC(mib2.ipinunknownprotos);
|
|
}
|
|
pbuf_free(p);
|
|
801b944: 6878 ldr r0, [r7, #4]
|
|
801b946: f7f6 fc87 bl 8012258 <pbuf_free>
|
|
break;
|
|
801b94a: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* @todo: this is not really necessary... */
|
|
ip_data.current_netif = NULL;
|
|
801b94c: 4b0b ldr r3, [pc, #44] ; (801b97c <ip4_input+0x278>)
|
|
801b94e: 2200 movs r2, #0
|
|
801b950: 601a str r2, [r3, #0]
|
|
ip_data.current_input_netif = NULL;
|
|
801b952: 4b0a ldr r3, [pc, #40] ; (801b97c <ip4_input+0x278>)
|
|
801b954: 2200 movs r2, #0
|
|
801b956: 605a str r2, [r3, #4]
|
|
ip_data.current_ip4_header = NULL;
|
|
801b958: 4b08 ldr r3, [pc, #32] ; (801b97c <ip4_input+0x278>)
|
|
801b95a: 2200 movs r2, #0
|
|
801b95c: 609a str r2, [r3, #8]
|
|
ip_data.current_ip_header_tot_len = 0;
|
|
801b95e: 4b07 ldr r3, [pc, #28] ; (801b97c <ip4_input+0x278>)
|
|
801b960: 2200 movs r2, #0
|
|
801b962: 819a strh r2, [r3, #12]
|
|
ip4_addr_set_any(ip4_current_src_addr());
|
|
801b964: 4b05 ldr r3, [pc, #20] ; (801b97c <ip4_input+0x278>)
|
|
801b966: 2200 movs r2, #0
|
|
801b968: 611a str r2, [r3, #16]
|
|
ip4_addr_set_any(ip4_current_dest_addr());
|
|
801b96a: 4b04 ldr r3, [pc, #16] ; (801b97c <ip4_input+0x278>)
|
|
801b96c: 2200 movs r2, #0
|
|
801b96e: 615a str r2, [r3, #20]
|
|
|
|
return ERR_OK;
|
|
801b970: 2300 movs r3, #0
|
|
}
|
|
801b972: 4618 mov r0, r3
|
|
801b974: 3720 adds r7, #32
|
|
801b976: 46bd mov sp, r7
|
|
801b978: bd80 pop {r7, pc}
|
|
801b97a: bf00 nop
|
|
801b97c: 2000c0c8 .word 0x2000c0c8
|
|
801b980: 2000f7ec .word 0x2000f7ec
|
|
|
|
0801b984 <ip4_output_if>:
|
|
*/
|
|
err_t
|
|
ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
|
|
u8_t ttl, u8_t tos,
|
|
u8_t proto, struct netif *netif)
|
|
{
|
|
801b984: b580 push {r7, lr}
|
|
801b986: b08a sub sp, #40 ; 0x28
|
|
801b988: af04 add r7, sp, #16
|
|
801b98a: 60f8 str r0, [r7, #12]
|
|
801b98c: 60b9 str r1, [r7, #8]
|
|
801b98e: 607a str r2, [r7, #4]
|
|
801b990: 70fb strb r3, [r7, #3]
|
|
ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
|
|
u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options,
|
|
u16_t optlen)
|
|
{
|
|
#endif /* IP_OPTIONS_SEND */
|
|
const ip4_addr_t *src_used = src;
|
|
801b992: 68bb ldr r3, [r7, #8]
|
|
801b994: 617b str r3, [r7, #20]
|
|
if (dest != LWIP_IP_HDRINCL) {
|
|
801b996: 687b ldr r3, [r7, #4]
|
|
801b998: 2b00 cmp r3, #0
|
|
801b99a: d009 beq.n 801b9b0 <ip4_output_if+0x2c>
|
|
if (ip4_addr_isany(src)) {
|
|
801b99c: 68bb ldr r3, [r7, #8]
|
|
801b99e: 2b00 cmp r3, #0
|
|
801b9a0: d003 beq.n 801b9aa <ip4_output_if+0x26>
|
|
801b9a2: 68bb ldr r3, [r7, #8]
|
|
801b9a4: 681b ldr r3, [r3, #0]
|
|
801b9a6: 2b00 cmp r3, #0
|
|
801b9a8: d102 bne.n 801b9b0 <ip4_output_if+0x2c>
|
|
src_used = netif_ip4_addr(netif);
|
|
801b9aa: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801b9ac: 3304 adds r3, #4
|
|
801b9ae: 617b str r3, [r7, #20]
|
|
|
|
#if IP_OPTIONS_SEND
|
|
return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif,
|
|
ip_options, optlen);
|
|
#else /* IP_OPTIONS_SEND */
|
|
return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif);
|
|
801b9b0: 78fa ldrb r2, [r7, #3]
|
|
801b9b2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801b9b4: 9302 str r3, [sp, #8]
|
|
801b9b6: f897 3024 ldrb.w r3, [r7, #36] ; 0x24
|
|
801b9ba: 9301 str r3, [sp, #4]
|
|
801b9bc: f897 3020 ldrb.w r3, [r7, #32]
|
|
801b9c0: 9300 str r3, [sp, #0]
|
|
801b9c2: 4613 mov r3, r2
|
|
801b9c4: 687a ldr r2, [r7, #4]
|
|
801b9c6: 6979 ldr r1, [r7, #20]
|
|
801b9c8: 68f8 ldr r0, [r7, #12]
|
|
801b9ca: f000 f805 bl 801b9d8 <ip4_output_if_src>
|
|
801b9ce: 4603 mov r3, r0
|
|
#endif /* IP_OPTIONS_SEND */
|
|
}
|
|
801b9d0: 4618 mov r0, r3
|
|
801b9d2: 3718 adds r7, #24
|
|
801b9d4: 46bd mov sp, r7
|
|
801b9d6: bd80 pop {r7, pc}
|
|
|
|
0801b9d8 <ip4_output_if_src>:
|
|
*/
|
|
err_t
|
|
ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest,
|
|
u8_t ttl, u8_t tos,
|
|
u8_t proto, struct netif *netif)
|
|
{
|
|
801b9d8: b580 push {r7, lr}
|
|
801b9da: b088 sub sp, #32
|
|
801b9dc: af00 add r7, sp, #0
|
|
801b9de: 60f8 str r0, [r7, #12]
|
|
801b9e0: 60b9 str r1, [r7, #8]
|
|
801b9e2: 607a str r2, [r7, #4]
|
|
801b9e4: 70fb strb r3, [r7, #3]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
u32_t chk_sum = 0;
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p);
|
|
801b9e6: 68fb ldr r3, [r7, #12]
|
|
801b9e8: 7b9b ldrb r3, [r3, #14]
|
|
801b9ea: 2b01 cmp r3, #1
|
|
801b9ec: d006 beq.n 801b9fc <ip4_output_if_src+0x24>
|
|
801b9ee: 4b4b ldr r3, [pc, #300] ; (801bb1c <ip4_output_if_src+0x144>)
|
|
801b9f0: f44f 7255 mov.w r2, #852 ; 0x354
|
|
801b9f4: 494a ldr r1, [pc, #296] ; (801bb20 <ip4_output_if_src+0x148>)
|
|
801b9f6: 484b ldr r0, [pc, #300] ; (801bb24 <ip4_output_if_src+0x14c>)
|
|
801b9f8: f001 f95e bl 801ccb8 <iprintf>
|
|
|
|
MIB2_STATS_INC(mib2.ipoutrequests);
|
|
|
|
/* Should the IP header be generated or is it already included in p? */
|
|
if (dest != LWIP_IP_HDRINCL) {
|
|
801b9fc: 687b ldr r3, [r7, #4]
|
|
801b9fe: 2b00 cmp r3, #0
|
|
801ba00: d060 beq.n 801bac4 <ip4_output_if_src+0xec>
|
|
u16_t ip_hlen = IP_HLEN;
|
|
801ba02: 2314 movs r3, #20
|
|
801ba04: 837b strh r3, [r7, #26]
|
|
}
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
}
|
|
#endif /* IP_OPTIONS_SEND */
|
|
/* generate IP header */
|
|
if (pbuf_add_header(p, IP_HLEN)) {
|
|
801ba06: 2114 movs r1, #20
|
|
801ba08: 68f8 ldr r0, [r7, #12]
|
|
801ba0a: f7f6 fb8f bl 801212c <pbuf_add_header>
|
|
801ba0e: 4603 mov r3, r0
|
|
801ba10: 2b00 cmp r3, #0
|
|
801ba12: d002 beq.n 801ba1a <ip4_output_if_src+0x42>
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n"));
|
|
|
|
IP_STATS_INC(ip.err);
|
|
MIB2_STATS_INC(mib2.ipoutdiscards);
|
|
return ERR_BUF;
|
|
801ba14: f06f 0301 mvn.w r3, #1
|
|
801ba18: e07c b.n 801bb14 <ip4_output_if_src+0x13c>
|
|
}
|
|
|
|
iphdr = (struct ip_hdr *)p->payload;
|
|
801ba1a: 68fb ldr r3, [r7, #12]
|
|
801ba1c: 685b ldr r3, [r3, #4]
|
|
801ba1e: 61fb str r3, [r7, #28]
|
|
LWIP_ASSERT("check that first pbuf can hold struct ip_hdr",
|
|
801ba20: 68fb ldr r3, [r7, #12]
|
|
801ba22: 895b ldrh r3, [r3, #10]
|
|
801ba24: 2b13 cmp r3, #19
|
|
801ba26: d806 bhi.n 801ba36 <ip4_output_if_src+0x5e>
|
|
801ba28: 4b3c ldr r3, [pc, #240] ; (801bb1c <ip4_output_if_src+0x144>)
|
|
801ba2a: f240 3289 movw r2, #905 ; 0x389
|
|
801ba2e: 493e ldr r1, [pc, #248] ; (801bb28 <ip4_output_if_src+0x150>)
|
|
801ba30: 483c ldr r0, [pc, #240] ; (801bb24 <ip4_output_if_src+0x14c>)
|
|
801ba32: f001 f941 bl 801ccb8 <iprintf>
|
|
(p->len >= sizeof(struct ip_hdr)));
|
|
|
|
IPH_TTL_SET(iphdr, ttl);
|
|
801ba36: 69fb ldr r3, [r7, #28]
|
|
801ba38: 78fa ldrb r2, [r7, #3]
|
|
801ba3a: 721a strb r2, [r3, #8]
|
|
IPH_PROTO_SET(iphdr, proto);
|
|
801ba3c: 69fb ldr r3, [r7, #28]
|
|
801ba3e: f897 202c ldrb.w r2, [r7, #44] ; 0x2c
|
|
801ba42: 725a strb r2, [r3, #9]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
chk_sum += PP_NTOHS(proto | (ttl << 8));
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
|
|
/* dest cannot be NULL here */
|
|
ip4_addr_copy(iphdr->dest, *dest);
|
|
801ba44: 687b ldr r3, [r7, #4]
|
|
801ba46: 681a ldr r2, [r3, #0]
|
|
801ba48: 69fb ldr r3, [r7, #28]
|
|
801ba4a: 611a str r2, [r3, #16]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF;
|
|
chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16;
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
|
|
IPH_VHL_SET(iphdr, 4, ip_hlen / 4);
|
|
801ba4c: 8b7b ldrh r3, [r7, #26]
|
|
801ba4e: 089b lsrs r3, r3, #2
|
|
801ba50: b29b uxth r3, r3
|
|
801ba52: b2db uxtb r3, r3
|
|
801ba54: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
801ba58: b2da uxtb r2, r3
|
|
801ba5a: 69fb ldr r3, [r7, #28]
|
|
801ba5c: 701a strb r2, [r3, #0]
|
|
IPH_TOS_SET(iphdr, tos);
|
|
801ba5e: 69fb ldr r3, [r7, #28]
|
|
801ba60: f897 2028 ldrb.w r2, [r7, #40] ; 0x28
|
|
801ba64: 705a strb r2, [r3, #1]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8));
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
IPH_LEN_SET(iphdr, lwip_htons(p->tot_len));
|
|
801ba66: 68fb ldr r3, [r7, #12]
|
|
801ba68: 891b ldrh r3, [r3, #8]
|
|
801ba6a: 4618 mov r0, r3
|
|
801ba6c: f7f5 f840 bl 8010af0 <lwip_htons>
|
|
801ba70: 4603 mov r3, r0
|
|
801ba72: 461a mov r2, r3
|
|
801ba74: 69fb ldr r3, [r7, #28]
|
|
801ba76: 805a strh r2, [r3, #2]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
chk_sum += iphdr->_len;
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
IPH_OFFSET_SET(iphdr, 0);
|
|
801ba78: 69fb ldr r3, [r7, #28]
|
|
801ba7a: 2200 movs r2, #0
|
|
801ba7c: 719a strb r2, [r3, #6]
|
|
801ba7e: 2200 movs r2, #0
|
|
801ba80: 71da strb r2, [r3, #7]
|
|
IPH_ID_SET(iphdr, lwip_htons(ip_id));
|
|
801ba82: 4b2a ldr r3, [pc, #168] ; (801bb2c <ip4_output_if_src+0x154>)
|
|
801ba84: 881b ldrh r3, [r3, #0]
|
|
801ba86: 4618 mov r0, r3
|
|
801ba88: f7f5 f832 bl 8010af0 <lwip_htons>
|
|
801ba8c: 4603 mov r3, r0
|
|
801ba8e: 461a mov r2, r3
|
|
801ba90: 69fb ldr r3, [r7, #28]
|
|
801ba92: 809a strh r2, [r3, #4]
|
|
#if CHECKSUM_GEN_IP_INLINE
|
|
chk_sum += iphdr->_id;
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
++ip_id;
|
|
801ba94: 4b25 ldr r3, [pc, #148] ; (801bb2c <ip4_output_if_src+0x154>)
|
|
801ba96: 881b ldrh r3, [r3, #0]
|
|
801ba98: 3301 adds r3, #1
|
|
801ba9a: b29a uxth r2, r3
|
|
801ba9c: 4b23 ldr r3, [pc, #140] ; (801bb2c <ip4_output_if_src+0x154>)
|
|
801ba9e: 801a strh r2, [r3, #0]
|
|
|
|
if (src == NULL) {
|
|
801baa0: 68bb ldr r3, [r7, #8]
|
|
801baa2: 2b00 cmp r3, #0
|
|
801baa4: d104 bne.n 801bab0 <ip4_output_if_src+0xd8>
|
|
ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4);
|
|
801baa6: 4b22 ldr r3, [pc, #136] ; (801bb30 <ip4_output_if_src+0x158>)
|
|
801baa8: 681a ldr r2, [r3, #0]
|
|
801baaa: 69fb ldr r3, [r7, #28]
|
|
801baac: 60da str r2, [r3, #12]
|
|
801baae: e003 b.n 801bab8 <ip4_output_if_src+0xe0>
|
|
} else {
|
|
/* src cannot be NULL here */
|
|
ip4_addr_copy(iphdr->src, *src);
|
|
801bab0: 68bb ldr r3, [r7, #8]
|
|
801bab2: 681a ldr r2, [r3, #0]
|
|
801bab4: 69fb ldr r3, [r7, #28]
|
|
801bab6: 60da str r2, [r3, #12]
|
|
else {
|
|
IPH_CHKSUM_SET(iphdr, 0);
|
|
}
|
|
#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/
|
|
#else /* CHECKSUM_GEN_IP_INLINE */
|
|
IPH_CHKSUM_SET(iphdr, 0);
|
|
801bab8: 69fb ldr r3, [r7, #28]
|
|
801baba: 2200 movs r2, #0
|
|
801babc: 729a strb r2, [r3, #10]
|
|
801babe: 2200 movs r2, #0
|
|
801bac0: 72da strb r2, [r3, #11]
|
|
801bac2: e00f b.n 801bae4 <ip4_output_if_src+0x10c>
|
|
}
|
|
#endif /* CHECKSUM_GEN_IP */
|
|
#endif /* CHECKSUM_GEN_IP_INLINE */
|
|
} else {
|
|
/* IP header already included in p */
|
|
if (p->len < IP_HLEN) {
|
|
801bac4: 68fb ldr r3, [r7, #12]
|
|
801bac6: 895b ldrh r3, [r3, #10]
|
|
801bac8: 2b13 cmp r3, #19
|
|
801baca: d802 bhi.n 801bad2 <ip4_output_if_src+0xfa>
|
|
LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n"));
|
|
IP_STATS_INC(ip.err);
|
|
MIB2_STATS_INC(mib2.ipoutdiscards);
|
|
return ERR_BUF;
|
|
801bacc: f06f 0301 mvn.w r3, #1
|
|
801bad0: e020 b.n 801bb14 <ip4_output_if_src+0x13c>
|
|
}
|
|
iphdr = (struct ip_hdr *)p->payload;
|
|
801bad2: 68fb ldr r3, [r7, #12]
|
|
801bad4: 685b ldr r3, [r3, #4]
|
|
801bad6: 61fb str r3, [r7, #28]
|
|
ip4_addr_copy(dest_addr, iphdr->dest);
|
|
801bad8: 69fb ldr r3, [r7, #28]
|
|
801bada: 691b ldr r3, [r3, #16]
|
|
801badc: 617b str r3, [r7, #20]
|
|
dest = &dest_addr;
|
|
801bade: f107 0314 add.w r3, r7, #20
|
|
801bae2: 607b str r3, [r7, #4]
|
|
}
|
|
#endif /* LWIP_MULTICAST_TX_OPTIONS */
|
|
#endif /* ENABLE_LOOPBACK */
|
|
#if IP_FRAG
|
|
/* don't fragment if interface has mtu set to 0 [loopif] */
|
|
if (netif->mtu && (p->tot_len > netif->mtu)) {
|
|
801bae4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801bae6: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
801bae8: 2b00 cmp r3, #0
|
|
801baea: d00c beq.n 801bb06 <ip4_output_if_src+0x12e>
|
|
801baec: 68fb ldr r3, [r7, #12]
|
|
801baee: 891a ldrh r2, [r3, #8]
|
|
801baf0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801baf2: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
801baf4: 429a cmp r2, r3
|
|
801baf6: d906 bls.n 801bb06 <ip4_output_if_src+0x12e>
|
|
return ip4_frag(p, netif, dest);
|
|
801baf8: 687a ldr r2, [r7, #4]
|
|
801bafa: 6b39 ldr r1, [r7, #48] ; 0x30
|
|
801bafc: 68f8 ldr r0, [r7, #12]
|
|
801bafe: f000 fd4b bl 801c598 <ip4_frag>
|
|
801bb02: 4603 mov r3, r0
|
|
801bb04: e006 b.n 801bb14 <ip4_output_if_src+0x13c>
|
|
}
|
|
#endif /* IP_FRAG */
|
|
|
|
LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n"));
|
|
return netif->output(netif, p, dest);
|
|
801bb06: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801bb08: 695b ldr r3, [r3, #20]
|
|
801bb0a: 687a ldr r2, [r7, #4]
|
|
801bb0c: 68f9 ldr r1, [r7, #12]
|
|
801bb0e: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
801bb10: 4798 blx r3
|
|
801bb12: 4603 mov r3, r0
|
|
}
|
|
801bb14: 4618 mov r0, r3
|
|
801bb16: 3720 adds r7, #32
|
|
801bb18: 46bd mov sp, r7
|
|
801bb1a: bd80 pop {r7, pc}
|
|
801bb1c: 08020aa8 .word 0x08020aa8
|
|
801bb20: 08020adc .word 0x08020adc
|
|
801bb24: 08020ae8 .word 0x08020ae8
|
|
801bb28: 08020b10 .word 0x08020b10
|
|
801bb2c: 2000886a .word 0x2000886a
|
|
801bb30: 08022e68 .word 0x08022e68
|
|
|
|
0801bb34 <ip4_addr_isbroadcast_u32>:
|
|
* @param netif the network interface against which the address is checked
|
|
* @return returns non-zero if the address is a broadcast address
|
|
*/
|
|
u8_t
|
|
ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif)
|
|
{
|
|
801bb34: b480 push {r7}
|
|
801bb36: b085 sub sp, #20
|
|
801bb38: af00 add r7, sp, #0
|
|
801bb3a: 6078 str r0, [r7, #4]
|
|
801bb3c: 6039 str r1, [r7, #0]
|
|
ip4_addr_t ipaddr;
|
|
ip4_addr_set_u32(&ipaddr, addr);
|
|
801bb3e: 687b ldr r3, [r7, #4]
|
|
801bb40: 60fb str r3, [r7, #12]
|
|
|
|
/* all ones (broadcast) or all zeroes (old skool broadcast) */
|
|
if ((~addr == IPADDR_ANY) ||
|
|
801bb42: 687b ldr r3, [r7, #4]
|
|
801bb44: f1b3 3fff cmp.w r3, #4294967295
|
|
801bb48: d002 beq.n 801bb50 <ip4_addr_isbroadcast_u32+0x1c>
|
|
801bb4a: 687b ldr r3, [r7, #4]
|
|
801bb4c: 2b00 cmp r3, #0
|
|
801bb4e: d101 bne.n 801bb54 <ip4_addr_isbroadcast_u32+0x20>
|
|
(addr == IPADDR_ANY)) {
|
|
return 1;
|
|
801bb50: 2301 movs r3, #1
|
|
801bb52: e02a b.n 801bbaa <ip4_addr_isbroadcast_u32+0x76>
|
|
/* no broadcast support on this network interface? */
|
|
} else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) {
|
|
801bb54: 683b ldr r3, [r7, #0]
|
|
801bb56: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801bb5a: f003 0302 and.w r3, r3, #2
|
|
801bb5e: 2b00 cmp r3, #0
|
|
801bb60: d101 bne.n 801bb66 <ip4_addr_isbroadcast_u32+0x32>
|
|
/* the given address cannot be a broadcast address
|
|
* nor can we check against any broadcast addresses */
|
|
return 0;
|
|
801bb62: 2300 movs r3, #0
|
|
801bb64: e021 b.n 801bbaa <ip4_addr_isbroadcast_u32+0x76>
|
|
/* address matches network interface address exactly? => no broadcast */
|
|
} else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) {
|
|
801bb66: 683b ldr r3, [r7, #0]
|
|
801bb68: 3304 adds r3, #4
|
|
801bb6a: 681b ldr r3, [r3, #0]
|
|
801bb6c: 687a ldr r2, [r7, #4]
|
|
801bb6e: 429a cmp r2, r3
|
|
801bb70: d101 bne.n 801bb76 <ip4_addr_isbroadcast_u32+0x42>
|
|
return 0;
|
|
801bb72: 2300 movs r3, #0
|
|
801bb74: e019 b.n 801bbaa <ip4_addr_isbroadcast_u32+0x76>
|
|
/* on the same (sub) network... */
|
|
} else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif))
|
|
801bb76: 68fa ldr r2, [r7, #12]
|
|
801bb78: 683b ldr r3, [r7, #0]
|
|
801bb7a: 3304 adds r3, #4
|
|
801bb7c: 681b ldr r3, [r3, #0]
|
|
801bb7e: 405a eors r2, r3
|
|
801bb80: 683b ldr r3, [r7, #0]
|
|
801bb82: 3308 adds r3, #8
|
|
801bb84: 681b ldr r3, [r3, #0]
|
|
801bb86: 4013 ands r3, r2
|
|
801bb88: 2b00 cmp r3, #0
|
|
801bb8a: d10d bne.n 801bba8 <ip4_addr_isbroadcast_u32+0x74>
|
|
/* ...and host identifier bits are all ones? =>... */
|
|
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
|
|
801bb8c: 683b ldr r3, [r7, #0]
|
|
801bb8e: 3308 adds r3, #8
|
|
801bb90: 681b ldr r3, [r3, #0]
|
|
801bb92: 43da mvns r2, r3
|
|
801bb94: 687b ldr r3, [r7, #4]
|
|
801bb96: 401a ands r2, r3
|
|
(IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) {
|
|
801bb98: 683b ldr r3, [r7, #0]
|
|
801bb9a: 3308 adds r3, #8
|
|
801bb9c: 681b ldr r3, [r3, #0]
|
|
801bb9e: 43db mvns r3, r3
|
|
&& ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) ==
|
|
801bba0: 429a cmp r2, r3
|
|
801bba2: d101 bne.n 801bba8 <ip4_addr_isbroadcast_u32+0x74>
|
|
/* => network broadcast address */
|
|
return 1;
|
|
801bba4: 2301 movs r3, #1
|
|
801bba6: e000 b.n 801bbaa <ip4_addr_isbroadcast_u32+0x76>
|
|
} else {
|
|
return 0;
|
|
801bba8: 2300 movs r3, #0
|
|
}
|
|
}
|
|
801bbaa: 4618 mov r0, r3
|
|
801bbac: 3714 adds r7, #20
|
|
801bbae: 46bd mov sp, r7
|
|
801bbb0: f85d 7b04 ldr.w r7, [sp], #4
|
|
801bbb4: 4770 bx lr
|
|
...
|
|
|
|
0801bbb8 <ip_reass_tmr>:
|
|
*
|
|
* Should be called every 1000 msec (defined by IP_TMR_INTERVAL).
|
|
*/
|
|
void
|
|
ip_reass_tmr(void)
|
|
{
|
|
801bbb8: b580 push {r7, lr}
|
|
801bbba: b084 sub sp, #16
|
|
801bbbc: af00 add r7, sp, #0
|
|
struct ip_reassdata *r, *prev = NULL;
|
|
801bbbe: 2300 movs r3, #0
|
|
801bbc0: 60bb str r3, [r7, #8]
|
|
|
|
r = reassdatagrams;
|
|
801bbc2: 4b12 ldr r3, [pc, #72] ; (801bc0c <ip_reass_tmr+0x54>)
|
|
801bbc4: 681b ldr r3, [r3, #0]
|
|
801bbc6: 60fb str r3, [r7, #12]
|
|
while (r != NULL) {
|
|
801bbc8: e018 b.n 801bbfc <ip_reass_tmr+0x44>
|
|
/* Decrement the timer. Once it reaches 0,
|
|
* clean up the incomplete fragment assembly */
|
|
if (r->timer > 0) {
|
|
801bbca: 68fb ldr r3, [r7, #12]
|
|
801bbcc: 7fdb ldrb r3, [r3, #31]
|
|
801bbce: 2b00 cmp r3, #0
|
|
801bbd0: d00b beq.n 801bbea <ip_reass_tmr+0x32>
|
|
r->timer--;
|
|
801bbd2: 68fb ldr r3, [r7, #12]
|
|
801bbd4: 7fdb ldrb r3, [r3, #31]
|
|
801bbd6: 3b01 subs r3, #1
|
|
801bbd8: b2da uxtb r2, r3
|
|
801bbda: 68fb ldr r3, [r7, #12]
|
|
801bbdc: 77da strb r2, [r3, #31]
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer));
|
|
prev = r;
|
|
801bbde: 68fb ldr r3, [r7, #12]
|
|
801bbe0: 60bb str r3, [r7, #8]
|
|
r = r->next;
|
|
801bbe2: 68fb ldr r3, [r7, #12]
|
|
801bbe4: 681b ldr r3, [r3, #0]
|
|
801bbe6: 60fb str r3, [r7, #12]
|
|
801bbe8: e008 b.n 801bbfc <ip_reass_tmr+0x44>
|
|
} else {
|
|
/* reassembly timed out */
|
|
struct ip_reassdata *tmp;
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n"));
|
|
tmp = r;
|
|
801bbea: 68fb ldr r3, [r7, #12]
|
|
801bbec: 607b str r3, [r7, #4]
|
|
/* get the next pointer before freeing */
|
|
r = r->next;
|
|
801bbee: 68fb ldr r3, [r7, #12]
|
|
801bbf0: 681b ldr r3, [r3, #0]
|
|
801bbf2: 60fb str r3, [r7, #12]
|
|
/* free the helper struct and all enqueued pbufs */
|
|
ip_reass_free_complete_datagram(tmp, prev);
|
|
801bbf4: 68b9 ldr r1, [r7, #8]
|
|
801bbf6: 6878 ldr r0, [r7, #4]
|
|
801bbf8: f000 f80a bl 801bc10 <ip_reass_free_complete_datagram>
|
|
while (r != NULL) {
|
|
801bbfc: 68fb ldr r3, [r7, #12]
|
|
801bbfe: 2b00 cmp r3, #0
|
|
801bc00: d1e3 bne.n 801bbca <ip_reass_tmr+0x12>
|
|
}
|
|
}
|
|
}
|
|
801bc02: bf00 nop
|
|
801bc04: 3710 adds r7, #16
|
|
801bc06: 46bd mov sp, r7
|
|
801bc08: bd80 pop {r7, pc}
|
|
801bc0a: bf00 nop
|
|
801bc0c: 2000886c .word 0x2000886c
|
|
|
|
0801bc10 <ip_reass_free_complete_datagram>:
|
|
* @param prev the previous datagram in the linked list
|
|
* @return the number of pbufs freed
|
|
*/
|
|
static int
|
|
ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
|
|
{
|
|
801bc10: b580 push {r7, lr}
|
|
801bc12: b088 sub sp, #32
|
|
801bc14: af00 add r7, sp, #0
|
|
801bc16: 6078 str r0, [r7, #4]
|
|
801bc18: 6039 str r1, [r7, #0]
|
|
u16_t pbufs_freed = 0;
|
|
801bc1a: 2300 movs r3, #0
|
|
801bc1c: 83fb strh r3, [r7, #30]
|
|
u16_t clen;
|
|
struct pbuf *p;
|
|
struct ip_reass_helper *iprh;
|
|
|
|
LWIP_ASSERT("prev != ipr", prev != ipr);
|
|
801bc1e: 683a ldr r2, [r7, #0]
|
|
801bc20: 687b ldr r3, [r7, #4]
|
|
801bc22: 429a cmp r2, r3
|
|
801bc24: d105 bne.n 801bc32 <ip_reass_free_complete_datagram+0x22>
|
|
801bc26: 4b45 ldr r3, [pc, #276] ; (801bd3c <ip_reass_free_complete_datagram+0x12c>)
|
|
801bc28: 22ab movs r2, #171 ; 0xab
|
|
801bc2a: 4945 ldr r1, [pc, #276] ; (801bd40 <ip_reass_free_complete_datagram+0x130>)
|
|
801bc2c: 4845 ldr r0, [pc, #276] ; (801bd44 <ip_reass_free_complete_datagram+0x134>)
|
|
801bc2e: f001 f843 bl 801ccb8 <iprintf>
|
|
if (prev != NULL) {
|
|
801bc32: 683b ldr r3, [r7, #0]
|
|
801bc34: 2b00 cmp r3, #0
|
|
801bc36: d00a beq.n 801bc4e <ip_reass_free_complete_datagram+0x3e>
|
|
LWIP_ASSERT("prev->next == ipr", prev->next == ipr);
|
|
801bc38: 683b ldr r3, [r7, #0]
|
|
801bc3a: 681b ldr r3, [r3, #0]
|
|
801bc3c: 687a ldr r2, [r7, #4]
|
|
801bc3e: 429a cmp r2, r3
|
|
801bc40: d005 beq.n 801bc4e <ip_reass_free_complete_datagram+0x3e>
|
|
801bc42: 4b3e ldr r3, [pc, #248] ; (801bd3c <ip_reass_free_complete_datagram+0x12c>)
|
|
801bc44: 22ad movs r2, #173 ; 0xad
|
|
801bc46: 4940 ldr r1, [pc, #256] ; (801bd48 <ip_reass_free_complete_datagram+0x138>)
|
|
801bc48: 483e ldr r0, [pc, #248] ; (801bd44 <ip_reass_free_complete_datagram+0x134>)
|
|
801bc4a: f001 f835 bl 801ccb8 <iprintf>
|
|
}
|
|
|
|
MIB2_STATS_INC(mib2.ipreasmfails);
|
|
#if LWIP_ICMP
|
|
iprh = (struct ip_reass_helper *)ipr->p->payload;
|
|
801bc4e: 687b ldr r3, [r7, #4]
|
|
801bc50: 685b ldr r3, [r3, #4]
|
|
801bc52: 685b ldr r3, [r3, #4]
|
|
801bc54: 617b str r3, [r7, #20]
|
|
if (iprh->start == 0) {
|
|
801bc56: 697b ldr r3, [r7, #20]
|
|
801bc58: 889b ldrh r3, [r3, #4]
|
|
801bc5a: b29b uxth r3, r3
|
|
801bc5c: 2b00 cmp r3, #0
|
|
801bc5e: d12a bne.n 801bcb6 <ip_reass_free_complete_datagram+0xa6>
|
|
/* The first fragment was received, send ICMP time exceeded. */
|
|
/* First, de-queue the first pbuf from r->p. */
|
|
p = ipr->p;
|
|
801bc60: 687b ldr r3, [r7, #4]
|
|
801bc62: 685b ldr r3, [r3, #4]
|
|
801bc64: 61bb str r3, [r7, #24]
|
|
ipr->p = iprh->next_pbuf;
|
|
801bc66: 697b ldr r3, [r7, #20]
|
|
801bc68: 681a ldr r2, [r3, #0]
|
|
801bc6a: 687b ldr r3, [r7, #4]
|
|
801bc6c: 605a str r2, [r3, #4]
|
|
/* Then, copy the original header into it. */
|
|
SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN);
|
|
801bc6e: 69bb ldr r3, [r7, #24]
|
|
801bc70: 6858 ldr r0, [r3, #4]
|
|
801bc72: 687b ldr r3, [r7, #4]
|
|
801bc74: 3308 adds r3, #8
|
|
801bc76: 2214 movs r2, #20
|
|
801bc78: 4619 mov r1, r3
|
|
801bc7a: f000 fff0 bl 801cc5e <memcpy>
|
|
icmp_time_exceeded(p, ICMP_TE_FRAG);
|
|
801bc7e: 2101 movs r1, #1
|
|
801bc80: 69b8 ldr r0, [r7, #24]
|
|
801bc82: f7ff fc2b bl 801b4dc <icmp_time_exceeded>
|
|
clen = pbuf_clen(p);
|
|
801bc86: 69b8 ldr r0, [r7, #24]
|
|
801bc88: f7f6 fb74 bl 8012374 <pbuf_clen>
|
|
801bc8c: 4603 mov r3, r0
|
|
801bc8e: 827b strh r3, [r7, #18]
|
|
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
|
|
801bc90: 8bfa ldrh r2, [r7, #30]
|
|
801bc92: 8a7b ldrh r3, [r7, #18]
|
|
801bc94: 4413 add r3, r2
|
|
801bc96: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
801bc9a: db05 blt.n 801bca8 <ip_reass_free_complete_datagram+0x98>
|
|
801bc9c: 4b27 ldr r3, [pc, #156] ; (801bd3c <ip_reass_free_complete_datagram+0x12c>)
|
|
801bc9e: 22bc movs r2, #188 ; 0xbc
|
|
801bca0: 492a ldr r1, [pc, #168] ; (801bd4c <ip_reass_free_complete_datagram+0x13c>)
|
|
801bca2: 4828 ldr r0, [pc, #160] ; (801bd44 <ip_reass_free_complete_datagram+0x134>)
|
|
801bca4: f001 f808 bl 801ccb8 <iprintf>
|
|
pbufs_freed = (u16_t)(pbufs_freed + clen);
|
|
801bca8: 8bfa ldrh r2, [r7, #30]
|
|
801bcaa: 8a7b ldrh r3, [r7, #18]
|
|
801bcac: 4413 add r3, r2
|
|
801bcae: 83fb strh r3, [r7, #30]
|
|
pbuf_free(p);
|
|
801bcb0: 69b8 ldr r0, [r7, #24]
|
|
801bcb2: f7f6 fad1 bl 8012258 <pbuf_free>
|
|
}
|
|
#endif /* LWIP_ICMP */
|
|
|
|
/* First, free all received pbufs. The individual pbufs need to be released
|
|
separately as they have not yet been chained */
|
|
p = ipr->p;
|
|
801bcb6: 687b ldr r3, [r7, #4]
|
|
801bcb8: 685b ldr r3, [r3, #4]
|
|
801bcba: 61bb str r3, [r7, #24]
|
|
while (p != NULL) {
|
|
801bcbc: e01f b.n 801bcfe <ip_reass_free_complete_datagram+0xee>
|
|
struct pbuf *pcur;
|
|
iprh = (struct ip_reass_helper *)p->payload;
|
|
801bcbe: 69bb ldr r3, [r7, #24]
|
|
801bcc0: 685b ldr r3, [r3, #4]
|
|
801bcc2: 617b str r3, [r7, #20]
|
|
pcur = p;
|
|
801bcc4: 69bb ldr r3, [r7, #24]
|
|
801bcc6: 60fb str r3, [r7, #12]
|
|
/* get the next pointer before freeing */
|
|
p = iprh->next_pbuf;
|
|
801bcc8: 697b ldr r3, [r7, #20]
|
|
801bcca: 681b ldr r3, [r3, #0]
|
|
801bccc: 61bb str r3, [r7, #24]
|
|
clen = pbuf_clen(pcur);
|
|
801bcce: 68f8 ldr r0, [r7, #12]
|
|
801bcd0: f7f6 fb50 bl 8012374 <pbuf_clen>
|
|
801bcd4: 4603 mov r3, r0
|
|
801bcd6: 827b strh r3, [r7, #18]
|
|
LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff);
|
|
801bcd8: 8bfa ldrh r2, [r7, #30]
|
|
801bcda: 8a7b ldrh r3, [r7, #18]
|
|
801bcdc: 4413 add r3, r2
|
|
801bcde: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
|
|
801bce2: db05 blt.n 801bcf0 <ip_reass_free_complete_datagram+0xe0>
|
|
801bce4: 4b15 ldr r3, [pc, #84] ; (801bd3c <ip_reass_free_complete_datagram+0x12c>)
|
|
801bce6: 22cc movs r2, #204 ; 0xcc
|
|
801bce8: 4918 ldr r1, [pc, #96] ; (801bd4c <ip_reass_free_complete_datagram+0x13c>)
|
|
801bcea: 4816 ldr r0, [pc, #88] ; (801bd44 <ip_reass_free_complete_datagram+0x134>)
|
|
801bcec: f000 ffe4 bl 801ccb8 <iprintf>
|
|
pbufs_freed = (u16_t)(pbufs_freed + clen);
|
|
801bcf0: 8bfa ldrh r2, [r7, #30]
|
|
801bcf2: 8a7b ldrh r3, [r7, #18]
|
|
801bcf4: 4413 add r3, r2
|
|
801bcf6: 83fb strh r3, [r7, #30]
|
|
pbuf_free(pcur);
|
|
801bcf8: 68f8 ldr r0, [r7, #12]
|
|
801bcfa: f7f6 faad bl 8012258 <pbuf_free>
|
|
while (p != NULL) {
|
|
801bcfe: 69bb ldr r3, [r7, #24]
|
|
801bd00: 2b00 cmp r3, #0
|
|
801bd02: d1dc bne.n 801bcbe <ip_reass_free_complete_datagram+0xae>
|
|
}
|
|
/* Then, unchain the struct ip_reassdata from the list and free it. */
|
|
ip_reass_dequeue_datagram(ipr, prev);
|
|
801bd04: 6839 ldr r1, [r7, #0]
|
|
801bd06: 6878 ldr r0, [r7, #4]
|
|
801bd08: f000 f8c2 bl 801be90 <ip_reass_dequeue_datagram>
|
|
LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed);
|
|
801bd0c: 4b10 ldr r3, [pc, #64] ; (801bd50 <ip_reass_free_complete_datagram+0x140>)
|
|
801bd0e: 881b ldrh r3, [r3, #0]
|
|
801bd10: 8bfa ldrh r2, [r7, #30]
|
|
801bd12: 429a cmp r2, r3
|
|
801bd14: d905 bls.n 801bd22 <ip_reass_free_complete_datagram+0x112>
|
|
801bd16: 4b09 ldr r3, [pc, #36] ; (801bd3c <ip_reass_free_complete_datagram+0x12c>)
|
|
801bd18: 22d2 movs r2, #210 ; 0xd2
|
|
801bd1a: 490e ldr r1, [pc, #56] ; (801bd54 <ip_reass_free_complete_datagram+0x144>)
|
|
801bd1c: 4809 ldr r0, [pc, #36] ; (801bd44 <ip_reass_free_complete_datagram+0x134>)
|
|
801bd1e: f000 ffcb bl 801ccb8 <iprintf>
|
|
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed);
|
|
801bd22: 4b0b ldr r3, [pc, #44] ; (801bd50 <ip_reass_free_complete_datagram+0x140>)
|
|
801bd24: 881a ldrh r2, [r3, #0]
|
|
801bd26: 8bfb ldrh r3, [r7, #30]
|
|
801bd28: 1ad3 subs r3, r2, r3
|
|
801bd2a: b29a uxth r2, r3
|
|
801bd2c: 4b08 ldr r3, [pc, #32] ; (801bd50 <ip_reass_free_complete_datagram+0x140>)
|
|
801bd2e: 801a strh r2, [r3, #0]
|
|
|
|
return pbufs_freed;
|
|
801bd30: 8bfb ldrh r3, [r7, #30]
|
|
}
|
|
801bd32: 4618 mov r0, r3
|
|
801bd34: 3720 adds r7, #32
|
|
801bd36: 46bd mov sp, r7
|
|
801bd38: bd80 pop {r7, pc}
|
|
801bd3a: bf00 nop
|
|
801bd3c: 08020b40 .word 0x08020b40
|
|
801bd40: 08020b7c .word 0x08020b7c
|
|
801bd44: 08020b88 .word 0x08020b88
|
|
801bd48: 08020bb0 .word 0x08020bb0
|
|
801bd4c: 08020bc4 .word 0x08020bc4
|
|
801bd50: 20008870 .word 0x20008870
|
|
801bd54: 08020be4 .word 0x08020be4
|
|
|
|
0801bd58 <ip_reass_remove_oldest_datagram>:
|
|
* (used for freeing other datagrams if not enough space)
|
|
* @return the number of pbufs freed
|
|
*/
|
|
static int
|
|
ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed)
|
|
{
|
|
801bd58: b580 push {r7, lr}
|
|
801bd5a: b08a sub sp, #40 ; 0x28
|
|
801bd5c: af00 add r7, sp, #0
|
|
801bd5e: 6078 str r0, [r7, #4]
|
|
801bd60: 6039 str r1, [r7, #0]
|
|
/* @todo Can't we simply remove the last datagram in the
|
|
* linked list behind reassdatagrams?
|
|
*/
|
|
struct ip_reassdata *r, *oldest, *prev, *oldest_prev;
|
|
int pbufs_freed = 0, pbufs_freed_current;
|
|
801bd62: 2300 movs r3, #0
|
|
801bd64: 617b str r3, [r7, #20]
|
|
int other_datagrams;
|
|
|
|
/* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs,
|
|
* but don't free the datagram that 'fraghdr' belongs to! */
|
|
do {
|
|
oldest = NULL;
|
|
801bd66: 2300 movs r3, #0
|
|
801bd68: 623b str r3, [r7, #32]
|
|
prev = NULL;
|
|
801bd6a: 2300 movs r3, #0
|
|
801bd6c: 61fb str r3, [r7, #28]
|
|
oldest_prev = NULL;
|
|
801bd6e: 2300 movs r3, #0
|
|
801bd70: 61bb str r3, [r7, #24]
|
|
other_datagrams = 0;
|
|
801bd72: 2300 movs r3, #0
|
|
801bd74: 613b str r3, [r7, #16]
|
|
r = reassdatagrams;
|
|
801bd76: 4b28 ldr r3, [pc, #160] ; (801be18 <ip_reass_remove_oldest_datagram+0xc0>)
|
|
801bd78: 681b ldr r3, [r3, #0]
|
|
801bd7a: 627b str r3, [r7, #36] ; 0x24
|
|
while (r != NULL) {
|
|
801bd7c: e030 b.n 801bde0 <ip_reass_remove_oldest_datagram+0x88>
|
|
if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) {
|
|
801bd7e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bd80: 695a ldr r2, [r3, #20]
|
|
801bd82: 687b ldr r3, [r7, #4]
|
|
801bd84: 68db ldr r3, [r3, #12]
|
|
801bd86: 429a cmp r2, r3
|
|
801bd88: d10c bne.n 801bda4 <ip_reass_remove_oldest_datagram+0x4c>
|
|
801bd8a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bd8c: 699a ldr r2, [r3, #24]
|
|
801bd8e: 687b ldr r3, [r7, #4]
|
|
801bd90: 691b ldr r3, [r3, #16]
|
|
801bd92: 429a cmp r2, r3
|
|
801bd94: d106 bne.n 801bda4 <ip_reass_remove_oldest_datagram+0x4c>
|
|
801bd96: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bd98: 899a ldrh r2, [r3, #12]
|
|
801bd9a: 687b ldr r3, [r7, #4]
|
|
801bd9c: 889b ldrh r3, [r3, #4]
|
|
801bd9e: b29b uxth r3, r3
|
|
801bda0: 429a cmp r2, r3
|
|
801bda2: d014 beq.n 801bdce <ip_reass_remove_oldest_datagram+0x76>
|
|
/* Not the same datagram as fraghdr */
|
|
other_datagrams++;
|
|
801bda4: 693b ldr r3, [r7, #16]
|
|
801bda6: 3301 adds r3, #1
|
|
801bda8: 613b str r3, [r7, #16]
|
|
if (oldest == NULL) {
|
|
801bdaa: 6a3b ldr r3, [r7, #32]
|
|
801bdac: 2b00 cmp r3, #0
|
|
801bdae: d104 bne.n 801bdba <ip_reass_remove_oldest_datagram+0x62>
|
|
oldest = r;
|
|
801bdb0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bdb2: 623b str r3, [r7, #32]
|
|
oldest_prev = prev;
|
|
801bdb4: 69fb ldr r3, [r7, #28]
|
|
801bdb6: 61bb str r3, [r7, #24]
|
|
801bdb8: e009 b.n 801bdce <ip_reass_remove_oldest_datagram+0x76>
|
|
} else if (r->timer <= oldest->timer) {
|
|
801bdba: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bdbc: 7fda ldrb r2, [r3, #31]
|
|
801bdbe: 6a3b ldr r3, [r7, #32]
|
|
801bdc0: 7fdb ldrb r3, [r3, #31]
|
|
801bdc2: 429a cmp r2, r3
|
|
801bdc4: d803 bhi.n 801bdce <ip_reass_remove_oldest_datagram+0x76>
|
|
/* older than the previous oldest */
|
|
oldest = r;
|
|
801bdc6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bdc8: 623b str r3, [r7, #32]
|
|
oldest_prev = prev;
|
|
801bdca: 69fb ldr r3, [r7, #28]
|
|
801bdcc: 61bb str r3, [r7, #24]
|
|
}
|
|
}
|
|
if (r->next != NULL) {
|
|
801bdce: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bdd0: 681b ldr r3, [r3, #0]
|
|
801bdd2: 2b00 cmp r3, #0
|
|
801bdd4: d001 beq.n 801bdda <ip_reass_remove_oldest_datagram+0x82>
|
|
prev = r;
|
|
801bdd6: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bdd8: 61fb str r3, [r7, #28]
|
|
}
|
|
r = r->next;
|
|
801bdda: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bddc: 681b ldr r3, [r3, #0]
|
|
801bdde: 627b str r3, [r7, #36] ; 0x24
|
|
while (r != NULL) {
|
|
801bde0: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bde2: 2b00 cmp r3, #0
|
|
801bde4: d1cb bne.n 801bd7e <ip_reass_remove_oldest_datagram+0x26>
|
|
}
|
|
if (oldest != NULL) {
|
|
801bde6: 6a3b ldr r3, [r7, #32]
|
|
801bde8: 2b00 cmp r3, #0
|
|
801bdea: d008 beq.n 801bdfe <ip_reass_remove_oldest_datagram+0xa6>
|
|
pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev);
|
|
801bdec: 69b9 ldr r1, [r7, #24]
|
|
801bdee: 6a38 ldr r0, [r7, #32]
|
|
801bdf0: f7ff ff0e bl 801bc10 <ip_reass_free_complete_datagram>
|
|
801bdf4: 60f8 str r0, [r7, #12]
|
|
pbufs_freed += pbufs_freed_current;
|
|
801bdf6: 697a ldr r2, [r7, #20]
|
|
801bdf8: 68fb ldr r3, [r7, #12]
|
|
801bdfa: 4413 add r3, r2
|
|
801bdfc: 617b str r3, [r7, #20]
|
|
}
|
|
} while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1));
|
|
801bdfe: 697a ldr r2, [r7, #20]
|
|
801be00: 683b ldr r3, [r7, #0]
|
|
801be02: 429a cmp r2, r3
|
|
801be04: da02 bge.n 801be0c <ip_reass_remove_oldest_datagram+0xb4>
|
|
801be06: 693b ldr r3, [r7, #16]
|
|
801be08: 2b01 cmp r3, #1
|
|
801be0a: dcac bgt.n 801bd66 <ip_reass_remove_oldest_datagram+0xe>
|
|
return pbufs_freed;
|
|
801be0c: 697b ldr r3, [r7, #20]
|
|
}
|
|
801be0e: 4618 mov r0, r3
|
|
801be10: 3728 adds r7, #40 ; 0x28
|
|
801be12: 46bd mov sp, r7
|
|
801be14: bd80 pop {r7, pc}
|
|
801be16: bf00 nop
|
|
801be18: 2000886c .word 0x2000886c
|
|
|
|
0801be1c <ip_reass_enqueue_new_datagram>:
|
|
* @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space)
|
|
* @return A pointer to the queue location into which the fragment was enqueued
|
|
*/
|
|
static struct ip_reassdata *
|
|
ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen)
|
|
{
|
|
801be1c: b580 push {r7, lr}
|
|
801be1e: b084 sub sp, #16
|
|
801be20: af00 add r7, sp, #0
|
|
801be22: 6078 str r0, [r7, #4]
|
|
801be24: 6039 str r1, [r7, #0]
|
|
#if ! IP_REASS_FREE_OLDEST
|
|
LWIP_UNUSED_ARG(clen);
|
|
#endif
|
|
|
|
/* No matching previous fragment found, allocate a new reassdata struct */
|
|
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
|
|
801be26: 2004 movs r0, #4
|
|
801be28: f7f5 fb18 bl 801145c <memp_malloc>
|
|
801be2c: 60f8 str r0, [r7, #12]
|
|
if (ipr == NULL) {
|
|
801be2e: 68fb ldr r3, [r7, #12]
|
|
801be30: 2b00 cmp r3, #0
|
|
801be32: d110 bne.n 801be56 <ip_reass_enqueue_new_datagram+0x3a>
|
|
#if IP_REASS_FREE_OLDEST
|
|
if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) {
|
|
801be34: 6839 ldr r1, [r7, #0]
|
|
801be36: 6878 ldr r0, [r7, #4]
|
|
801be38: f7ff ff8e bl 801bd58 <ip_reass_remove_oldest_datagram>
|
|
801be3c: 4602 mov r2, r0
|
|
801be3e: 683b ldr r3, [r7, #0]
|
|
801be40: 4293 cmp r3, r2
|
|
801be42: dc03 bgt.n 801be4c <ip_reass_enqueue_new_datagram+0x30>
|
|
ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA);
|
|
801be44: 2004 movs r0, #4
|
|
801be46: f7f5 fb09 bl 801145c <memp_malloc>
|
|
801be4a: 60f8 str r0, [r7, #12]
|
|
}
|
|
if (ipr == NULL)
|
|
801be4c: 68fb ldr r3, [r7, #12]
|
|
801be4e: 2b00 cmp r3, #0
|
|
801be50: d101 bne.n 801be56 <ip_reass_enqueue_new_datagram+0x3a>
|
|
#endif /* IP_REASS_FREE_OLDEST */
|
|
{
|
|
IPFRAG_STATS_INC(ip_frag.memerr);
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n"));
|
|
return NULL;
|
|
801be52: 2300 movs r3, #0
|
|
801be54: e016 b.n 801be84 <ip_reass_enqueue_new_datagram+0x68>
|
|
}
|
|
}
|
|
memset(ipr, 0, sizeof(struct ip_reassdata));
|
|
801be56: 2220 movs r2, #32
|
|
801be58: 2100 movs r1, #0
|
|
801be5a: 68f8 ldr r0, [r7, #12]
|
|
801be5c: f000 ff23 bl 801cca6 <memset>
|
|
ipr->timer = IP_REASS_MAXAGE;
|
|
801be60: 68fb ldr r3, [r7, #12]
|
|
801be62: 220f movs r2, #15
|
|
801be64: 77da strb r2, [r3, #31]
|
|
|
|
/* enqueue the new structure to the front of the list */
|
|
ipr->next = reassdatagrams;
|
|
801be66: 4b09 ldr r3, [pc, #36] ; (801be8c <ip_reass_enqueue_new_datagram+0x70>)
|
|
801be68: 681a ldr r2, [r3, #0]
|
|
801be6a: 68fb ldr r3, [r7, #12]
|
|
801be6c: 601a str r2, [r3, #0]
|
|
reassdatagrams = ipr;
|
|
801be6e: 4a07 ldr r2, [pc, #28] ; (801be8c <ip_reass_enqueue_new_datagram+0x70>)
|
|
801be70: 68fb ldr r3, [r7, #12]
|
|
801be72: 6013 str r3, [r2, #0]
|
|
/* copy the ip header for later tests and input */
|
|
/* @todo: no ip options supported? */
|
|
SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN);
|
|
801be74: 68fb ldr r3, [r7, #12]
|
|
801be76: 3308 adds r3, #8
|
|
801be78: 2214 movs r2, #20
|
|
801be7a: 6879 ldr r1, [r7, #4]
|
|
801be7c: 4618 mov r0, r3
|
|
801be7e: f000 feee bl 801cc5e <memcpy>
|
|
return ipr;
|
|
801be82: 68fb ldr r3, [r7, #12]
|
|
}
|
|
801be84: 4618 mov r0, r3
|
|
801be86: 3710 adds r7, #16
|
|
801be88: 46bd mov sp, r7
|
|
801be8a: bd80 pop {r7, pc}
|
|
801be8c: 2000886c .word 0x2000886c
|
|
|
|
0801be90 <ip_reass_dequeue_datagram>:
|
|
* Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs.
|
|
* @param ipr points to the queue entry to dequeue
|
|
*/
|
|
static void
|
|
ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev)
|
|
{
|
|
801be90: b580 push {r7, lr}
|
|
801be92: b082 sub sp, #8
|
|
801be94: af00 add r7, sp, #0
|
|
801be96: 6078 str r0, [r7, #4]
|
|
801be98: 6039 str r1, [r7, #0]
|
|
/* dequeue the reass struct */
|
|
if (reassdatagrams == ipr) {
|
|
801be9a: 4b10 ldr r3, [pc, #64] ; (801bedc <ip_reass_dequeue_datagram+0x4c>)
|
|
801be9c: 681b ldr r3, [r3, #0]
|
|
801be9e: 687a ldr r2, [r7, #4]
|
|
801bea0: 429a cmp r2, r3
|
|
801bea2: d104 bne.n 801beae <ip_reass_dequeue_datagram+0x1e>
|
|
/* it was the first in the list */
|
|
reassdatagrams = ipr->next;
|
|
801bea4: 687b ldr r3, [r7, #4]
|
|
801bea6: 681b ldr r3, [r3, #0]
|
|
801bea8: 4a0c ldr r2, [pc, #48] ; (801bedc <ip_reass_dequeue_datagram+0x4c>)
|
|
801beaa: 6013 str r3, [r2, #0]
|
|
801beac: e00d b.n 801beca <ip_reass_dequeue_datagram+0x3a>
|
|
} else {
|
|
/* it wasn't the first, so it must have a valid 'prev' */
|
|
LWIP_ASSERT("sanity check linked list", prev != NULL);
|
|
801beae: 683b ldr r3, [r7, #0]
|
|
801beb0: 2b00 cmp r3, #0
|
|
801beb2: d106 bne.n 801bec2 <ip_reass_dequeue_datagram+0x32>
|
|
801beb4: 4b0a ldr r3, [pc, #40] ; (801bee0 <ip_reass_dequeue_datagram+0x50>)
|
|
801beb6: f240 1245 movw r2, #325 ; 0x145
|
|
801beba: 490a ldr r1, [pc, #40] ; (801bee4 <ip_reass_dequeue_datagram+0x54>)
|
|
801bebc: 480a ldr r0, [pc, #40] ; (801bee8 <ip_reass_dequeue_datagram+0x58>)
|
|
801bebe: f000 fefb bl 801ccb8 <iprintf>
|
|
prev->next = ipr->next;
|
|
801bec2: 687b ldr r3, [r7, #4]
|
|
801bec4: 681a ldr r2, [r3, #0]
|
|
801bec6: 683b ldr r3, [r7, #0]
|
|
801bec8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* now we can free the ip_reassdata struct */
|
|
memp_free(MEMP_REASSDATA, ipr);
|
|
801beca: 6879 ldr r1, [r7, #4]
|
|
801becc: 2004 movs r0, #4
|
|
801bece: f7f5 fb17 bl 8011500 <memp_free>
|
|
}
|
|
801bed2: bf00 nop
|
|
801bed4: 3708 adds r7, #8
|
|
801bed6: 46bd mov sp, r7
|
|
801bed8: bd80 pop {r7, pc}
|
|
801beda: bf00 nop
|
|
801bedc: 2000886c .word 0x2000886c
|
|
801bee0: 08020b40 .word 0x08020b40
|
|
801bee4: 08020c08 .word 0x08020c08
|
|
801bee8: 08020b88 .word 0x08020b88
|
|
|
|
0801beec <ip_reass_chain_frag_into_datagram_and_validate>:
|
|
* @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet)
|
|
* @return see IP_REASS_VALIDATE_* defines
|
|
*/
|
|
static int
|
|
ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last)
|
|
{
|
|
801beec: b580 push {r7, lr}
|
|
801beee: b08c sub sp, #48 ; 0x30
|
|
801bef0: af00 add r7, sp, #0
|
|
801bef2: 60f8 str r0, [r7, #12]
|
|
801bef4: 60b9 str r1, [r7, #8]
|
|
801bef6: 607a str r2, [r7, #4]
|
|
struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL;
|
|
801bef8: 2300 movs r3, #0
|
|
801befa: 62bb str r3, [r7, #40] ; 0x28
|
|
struct pbuf *q;
|
|
u16_t offset, len;
|
|
u8_t hlen;
|
|
struct ip_hdr *fraghdr;
|
|
int valid = 1;
|
|
801befc: 2301 movs r3, #1
|
|
801befe: 623b str r3, [r7, #32]
|
|
|
|
/* Extract length and fragment offset from current fragment */
|
|
fraghdr = (struct ip_hdr *)new_p->payload;
|
|
801bf00: 68bb ldr r3, [r7, #8]
|
|
801bf02: 685b ldr r3, [r3, #4]
|
|
801bf04: 61fb str r3, [r7, #28]
|
|
len = lwip_ntohs(IPH_LEN(fraghdr));
|
|
801bf06: 69fb ldr r3, [r7, #28]
|
|
801bf08: 885b ldrh r3, [r3, #2]
|
|
801bf0a: b29b uxth r3, r3
|
|
801bf0c: 4618 mov r0, r3
|
|
801bf0e: f7f4 fdef bl 8010af0 <lwip_htons>
|
|
801bf12: 4603 mov r3, r0
|
|
801bf14: 837b strh r3, [r7, #26]
|
|
hlen = IPH_HL_BYTES(fraghdr);
|
|
801bf16: 69fb ldr r3, [r7, #28]
|
|
801bf18: 781b ldrb r3, [r3, #0]
|
|
801bf1a: f003 030f and.w r3, r3, #15
|
|
801bf1e: b2db uxtb r3, r3
|
|
801bf20: 009b lsls r3, r3, #2
|
|
801bf22: 767b strb r3, [r7, #25]
|
|
if (hlen > len) {
|
|
801bf24: 7e7b ldrb r3, [r7, #25]
|
|
801bf26: b29b uxth r3, r3
|
|
801bf28: 8b7a ldrh r2, [r7, #26]
|
|
801bf2a: 429a cmp r2, r3
|
|
801bf2c: d202 bcs.n 801bf34 <ip_reass_chain_frag_into_datagram_and_validate+0x48>
|
|
/* invalid datagram */
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801bf2e: f04f 33ff mov.w r3, #4294967295
|
|
801bf32: e135 b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
}
|
|
len = (u16_t)(len - hlen);
|
|
801bf34: 7e7b ldrb r3, [r7, #25]
|
|
801bf36: b29b uxth r3, r3
|
|
801bf38: 8b7a ldrh r2, [r7, #26]
|
|
801bf3a: 1ad3 subs r3, r2, r3
|
|
801bf3c: 837b strh r3, [r7, #26]
|
|
offset = IPH_OFFSET_BYTES(fraghdr);
|
|
801bf3e: 69fb ldr r3, [r7, #28]
|
|
801bf40: 88db ldrh r3, [r3, #6]
|
|
801bf42: b29b uxth r3, r3
|
|
801bf44: 4618 mov r0, r3
|
|
801bf46: f7f4 fdd3 bl 8010af0 <lwip_htons>
|
|
801bf4a: 4603 mov r3, r0
|
|
801bf4c: f3c3 030c ubfx r3, r3, #0, #13
|
|
801bf50: b29b uxth r3, r3
|
|
801bf52: 00db lsls r3, r3, #3
|
|
801bf54: 82fb strh r3, [r7, #22]
|
|
/* overwrite the fragment's ip header from the pbuf with our helper struct,
|
|
* and setup the embedded helper structure. */
|
|
/* make sure the struct ip_reass_helper fits into the IP header */
|
|
LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN",
|
|
sizeof(struct ip_reass_helper) <= IP_HLEN);
|
|
iprh = (struct ip_reass_helper *)new_p->payload;
|
|
801bf56: 68bb ldr r3, [r7, #8]
|
|
801bf58: 685b ldr r3, [r3, #4]
|
|
801bf5a: 62fb str r3, [r7, #44] ; 0x2c
|
|
iprh->next_pbuf = NULL;
|
|
801bf5c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bf5e: 2200 movs r2, #0
|
|
801bf60: 701a strb r2, [r3, #0]
|
|
801bf62: 2200 movs r2, #0
|
|
801bf64: 705a strb r2, [r3, #1]
|
|
801bf66: 2200 movs r2, #0
|
|
801bf68: 709a strb r2, [r3, #2]
|
|
801bf6a: 2200 movs r2, #0
|
|
801bf6c: 70da strb r2, [r3, #3]
|
|
iprh->start = offset;
|
|
801bf6e: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bf70: 8afa ldrh r2, [r7, #22]
|
|
801bf72: 809a strh r2, [r3, #4]
|
|
iprh->end = (u16_t)(offset + len);
|
|
801bf74: 8afa ldrh r2, [r7, #22]
|
|
801bf76: 8b7b ldrh r3, [r7, #26]
|
|
801bf78: 4413 add r3, r2
|
|
801bf7a: b29a uxth r2, r3
|
|
801bf7c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bf7e: 80da strh r2, [r3, #6]
|
|
if (iprh->end < offset) {
|
|
801bf80: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bf82: 88db ldrh r3, [r3, #6]
|
|
801bf84: b29b uxth r3, r3
|
|
801bf86: 8afa ldrh r2, [r7, #22]
|
|
801bf88: 429a cmp r2, r3
|
|
801bf8a: d902 bls.n 801bf92 <ip_reass_chain_frag_into_datagram_and_validate+0xa6>
|
|
/* u16_t overflow, cannot handle this */
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801bf8c: f04f 33ff mov.w r3, #4294967295
|
|
801bf90: e106 b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
}
|
|
|
|
/* Iterate through until we either get to the end of the list (append),
|
|
* or we find one with a larger offset (insert). */
|
|
for (q = ipr->p; q != NULL;) {
|
|
801bf92: 68fb ldr r3, [r7, #12]
|
|
801bf94: 685b ldr r3, [r3, #4]
|
|
801bf96: 627b str r3, [r7, #36] ; 0x24
|
|
801bf98: e068 b.n 801c06c <ip_reass_chain_frag_into_datagram_and_validate+0x180>
|
|
iprh_tmp = (struct ip_reass_helper *)q->payload;
|
|
801bf9a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801bf9c: 685b ldr r3, [r3, #4]
|
|
801bf9e: 613b str r3, [r7, #16]
|
|
if (iprh->start < iprh_tmp->start) {
|
|
801bfa0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bfa2: 889b ldrh r3, [r3, #4]
|
|
801bfa4: b29a uxth r2, r3
|
|
801bfa6: 693b ldr r3, [r7, #16]
|
|
801bfa8: 889b ldrh r3, [r3, #4]
|
|
801bfaa: b29b uxth r3, r3
|
|
801bfac: 429a cmp r2, r3
|
|
801bfae: d235 bcs.n 801c01c <ip_reass_chain_frag_into_datagram_and_validate+0x130>
|
|
/* the new pbuf should be inserted before this */
|
|
iprh->next_pbuf = q;
|
|
801bfb0: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bfb2: 6a7a ldr r2, [r7, #36] ; 0x24
|
|
801bfb4: 601a str r2, [r3, #0]
|
|
if (iprh_prev != NULL) {
|
|
801bfb6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801bfb8: 2b00 cmp r3, #0
|
|
801bfba: d020 beq.n 801bffe <ip_reass_chain_frag_into_datagram_and_validate+0x112>
|
|
/* not the fragment with the lowest offset */
|
|
#if IP_REASS_CHECK_OVERLAP
|
|
if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) {
|
|
801bfbc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bfbe: 889b ldrh r3, [r3, #4]
|
|
801bfc0: b29a uxth r2, r3
|
|
801bfc2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801bfc4: 88db ldrh r3, [r3, #6]
|
|
801bfc6: b29b uxth r3, r3
|
|
801bfc8: 429a cmp r2, r3
|
|
801bfca: d307 bcc.n 801bfdc <ip_reass_chain_frag_into_datagram_and_validate+0xf0>
|
|
801bfcc: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bfce: 88db ldrh r3, [r3, #6]
|
|
801bfd0: b29a uxth r2, r3
|
|
801bfd2: 693b ldr r3, [r7, #16]
|
|
801bfd4: 889b ldrh r3, [r3, #4]
|
|
801bfd6: b29b uxth r3, r3
|
|
801bfd8: 429a cmp r2, r3
|
|
801bfda: d902 bls.n 801bfe2 <ip_reass_chain_frag_into_datagram_and_validate+0xf6>
|
|
/* fragment overlaps with previous or following, throw away */
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801bfdc: f04f 33ff mov.w r3, #4294967295
|
|
801bfe0: e0de b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
}
|
|
#endif /* IP_REASS_CHECK_OVERLAP */
|
|
iprh_prev->next_pbuf = new_p;
|
|
801bfe2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801bfe4: 68ba ldr r2, [r7, #8]
|
|
801bfe6: 601a str r2, [r3, #0]
|
|
if (iprh_prev->end != iprh->start) {
|
|
801bfe8: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801bfea: 88db ldrh r3, [r3, #6]
|
|
801bfec: b29a uxth r2, r3
|
|
801bfee: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801bff0: 889b ldrh r3, [r3, #4]
|
|
801bff2: b29b uxth r3, r3
|
|
801bff4: 429a cmp r2, r3
|
|
801bff6: d03d beq.n 801c074 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
|
|
/* There is a fragment missing between the current
|
|
* and the previous fragment */
|
|
valid = 0;
|
|
801bff8: 2300 movs r3, #0
|
|
801bffa: 623b str r3, [r7, #32]
|
|
}
|
|
#endif /* IP_REASS_CHECK_OVERLAP */
|
|
/* fragment with the lowest offset */
|
|
ipr->p = new_p;
|
|
}
|
|
break;
|
|
801bffc: e03a b.n 801c074 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
|
|
if (iprh->end > iprh_tmp->start) {
|
|
801bffe: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c000: 88db ldrh r3, [r3, #6]
|
|
801c002: b29a uxth r2, r3
|
|
801c004: 693b ldr r3, [r7, #16]
|
|
801c006: 889b ldrh r3, [r3, #4]
|
|
801c008: b29b uxth r3, r3
|
|
801c00a: 429a cmp r2, r3
|
|
801c00c: d902 bls.n 801c014 <ip_reass_chain_frag_into_datagram_and_validate+0x128>
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801c00e: f04f 33ff mov.w r3, #4294967295
|
|
801c012: e0c5 b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
ipr->p = new_p;
|
|
801c014: 68fb ldr r3, [r7, #12]
|
|
801c016: 68ba ldr r2, [r7, #8]
|
|
801c018: 605a str r2, [r3, #4]
|
|
break;
|
|
801c01a: e02b b.n 801c074 <ip_reass_chain_frag_into_datagram_and_validate+0x188>
|
|
} else if (iprh->start == iprh_tmp->start) {
|
|
801c01c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c01e: 889b ldrh r3, [r3, #4]
|
|
801c020: b29a uxth r2, r3
|
|
801c022: 693b ldr r3, [r7, #16]
|
|
801c024: 889b ldrh r3, [r3, #4]
|
|
801c026: b29b uxth r3, r3
|
|
801c028: 429a cmp r2, r3
|
|
801c02a: d102 bne.n 801c032 <ip_reass_chain_frag_into_datagram_and_validate+0x146>
|
|
/* received the same datagram twice: no need to keep the datagram */
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801c02c: f04f 33ff mov.w r3, #4294967295
|
|
801c030: e0b6 b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
#if IP_REASS_CHECK_OVERLAP
|
|
} else if (iprh->start < iprh_tmp->end) {
|
|
801c032: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c034: 889b ldrh r3, [r3, #4]
|
|
801c036: b29a uxth r2, r3
|
|
801c038: 693b ldr r3, [r7, #16]
|
|
801c03a: 88db ldrh r3, [r3, #6]
|
|
801c03c: b29b uxth r3, r3
|
|
801c03e: 429a cmp r2, r3
|
|
801c040: d202 bcs.n 801c048 <ip_reass_chain_frag_into_datagram_and_validate+0x15c>
|
|
/* overlap: no need to keep the new datagram */
|
|
return IP_REASS_VALIDATE_PBUF_DROPPED;
|
|
801c042: f04f 33ff mov.w r3, #4294967295
|
|
801c046: e0ab b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
#endif /* IP_REASS_CHECK_OVERLAP */
|
|
} else {
|
|
/* Check if the fragments received so far have no holes. */
|
|
if (iprh_prev != NULL) {
|
|
801c048: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c04a: 2b00 cmp r3, #0
|
|
801c04c: d009 beq.n 801c062 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
|
|
if (iprh_prev->end != iprh_tmp->start) {
|
|
801c04e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c050: 88db ldrh r3, [r3, #6]
|
|
801c052: b29a uxth r2, r3
|
|
801c054: 693b ldr r3, [r7, #16]
|
|
801c056: 889b ldrh r3, [r3, #4]
|
|
801c058: b29b uxth r3, r3
|
|
801c05a: 429a cmp r2, r3
|
|
801c05c: d001 beq.n 801c062 <ip_reass_chain_frag_into_datagram_and_validate+0x176>
|
|
/* There is a fragment missing between the current
|
|
* and the previous fragment */
|
|
valid = 0;
|
|
801c05e: 2300 movs r3, #0
|
|
801c060: 623b str r3, [r7, #32]
|
|
}
|
|
}
|
|
}
|
|
q = iprh_tmp->next_pbuf;
|
|
801c062: 693b ldr r3, [r7, #16]
|
|
801c064: 681b ldr r3, [r3, #0]
|
|
801c066: 627b str r3, [r7, #36] ; 0x24
|
|
iprh_prev = iprh_tmp;
|
|
801c068: 693b ldr r3, [r7, #16]
|
|
801c06a: 62bb str r3, [r7, #40] ; 0x28
|
|
for (q = ipr->p; q != NULL;) {
|
|
801c06c: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c06e: 2b00 cmp r3, #0
|
|
801c070: d193 bne.n 801bf9a <ip_reass_chain_frag_into_datagram_and_validate+0xae>
|
|
801c072: e000 b.n 801c076 <ip_reass_chain_frag_into_datagram_and_validate+0x18a>
|
|
break;
|
|
801c074: bf00 nop
|
|
}
|
|
|
|
/* If q is NULL, then we made it to the end of the list. Determine what to do now */
|
|
if (q == NULL) {
|
|
801c076: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c078: 2b00 cmp r3, #0
|
|
801c07a: d12d bne.n 801c0d8 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
|
|
if (iprh_prev != NULL) {
|
|
801c07c: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c07e: 2b00 cmp r3, #0
|
|
801c080: d01c beq.n 801c0bc <ip_reass_chain_frag_into_datagram_and_validate+0x1d0>
|
|
/* this is (for now), the fragment with the highest offset:
|
|
* chain it to the last fragment */
|
|
#if IP_REASS_CHECK_OVERLAP
|
|
LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start);
|
|
801c082: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c084: 88db ldrh r3, [r3, #6]
|
|
801c086: b29a uxth r2, r3
|
|
801c088: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c08a: 889b ldrh r3, [r3, #4]
|
|
801c08c: b29b uxth r3, r3
|
|
801c08e: 429a cmp r2, r3
|
|
801c090: d906 bls.n 801c0a0 <ip_reass_chain_frag_into_datagram_and_validate+0x1b4>
|
|
801c092: 4b45 ldr r3, [pc, #276] ; (801c1a8 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
|
|
801c094: f44f 72db mov.w r2, #438 ; 0x1b6
|
|
801c098: 4944 ldr r1, [pc, #272] ; (801c1ac <ip_reass_chain_frag_into_datagram_and_validate+0x2c0>)
|
|
801c09a: 4845 ldr r0, [pc, #276] ; (801c1b0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
|
|
801c09c: f000 fe0c bl 801ccb8 <iprintf>
|
|
#endif /* IP_REASS_CHECK_OVERLAP */
|
|
iprh_prev->next_pbuf = new_p;
|
|
801c0a0: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c0a2: 68ba ldr r2, [r7, #8]
|
|
801c0a4: 601a str r2, [r3, #0]
|
|
if (iprh_prev->end != iprh->start) {
|
|
801c0a6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c0a8: 88db ldrh r3, [r3, #6]
|
|
801c0aa: b29a uxth r2, r3
|
|
801c0ac: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c0ae: 889b ldrh r3, [r3, #4]
|
|
801c0b0: b29b uxth r3, r3
|
|
801c0b2: 429a cmp r2, r3
|
|
801c0b4: d010 beq.n 801c0d8 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
|
|
valid = 0;
|
|
801c0b6: 2300 movs r3, #0
|
|
801c0b8: 623b str r3, [r7, #32]
|
|
801c0ba: e00d b.n 801c0d8 <ip_reass_chain_frag_into_datagram_and_validate+0x1ec>
|
|
}
|
|
} else {
|
|
#if IP_REASS_CHECK_OVERLAP
|
|
LWIP_ASSERT("no previous fragment, this must be the first fragment!",
|
|
801c0bc: 68fb ldr r3, [r7, #12]
|
|
801c0be: 685b ldr r3, [r3, #4]
|
|
801c0c0: 2b00 cmp r3, #0
|
|
801c0c2: d006 beq.n 801c0d2 <ip_reass_chain_frag_into_datagram_and_validate+0x1e6>
|
|
801c0c4: 4b38 ldr r3, [pc, #224] ; (801c1a8 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
|
|
801c0c6: f240 12bf movw r2, #447 ; 0x1bf
|
|
801c0ca: 493a ldr r1, [pc, #232] ; (801c1b4 <ip_reass_chain_frag_into_datagram_and_validate+0x2c8>)
|
|
801c0cc: 4838 ldr r0, [pc, #224] ; (801c1b0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
|
|
801c0ce: f000 fdf3 bl 801ccb8 <iprintf>
|
|
ipr->p == NULL);
|
|
#endif /* IP_REASS_CHECK_OVERLAP */
|
|
/* this is the first fragment we ever received for this ip datagram */
|
|
ipr->p = new_p;
|
|
801c0d2: 68fb ldr r3, [r7, #12]
|
|
801c0d4: 68ba ldr r2, [r7, #8]
|
|
801c0d6: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* At this point, the validation part begins: */
|
|
/* If we already received the last fragment */
|
|
if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) {
|
|
801c0d8: 687b ldr r3, [r7, #4]
|
|
801c0da: 2b00 cmp r3, #0
|
|
801c0dc: d105 bne.n 801c0ea <ip_reass_chain_frag_into_datagram_and_validate+0x1fe>
|
|
801c0de: 68fb ldr r3, [r7, #12]
|
|
801c0e0: 7f9b ldrb r3, [r3, #30]
|
|
801c0e2: f003 0301 and.w r3, r3, #1
|
|
801c0e6: 2b00 cmp r3, #0
|
|
801c0e8: d059 beq.n 801c19e <ip_reass_chain_frag_into_datagram_and_validate+0x2b2>
|
|
/* and had no holes so far */
|
|
if (valid) {
|
|
801c0ea: 6a3b ldr r3, [r7, #32]
|
|
801c0ec: 2b00 cmp r3, #0
|
|
801c0ee: d04f beq.n 801c190 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
|
|
/* then check if the rest of the fragments is here */
|
|
/* Check if the queue starts with the first datagram */
|
|
if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) {
|
|
801c0f0: 68fb ldr r3, [r7, #12]
|
|
801c0f2: 685b ldr r3, [r3, #4]
|
|
801c0f4: 2b00 cmp r3, #0
|
|
801c0f6: d006 beq.n 801c106 <ip_reass_chain_frag_into_datagram_and_validate+0x21a>
|
|
801c0f8: 68fb ldr r3, [r7, #12]
|
|
801c0fa: 685b ldr r3, [r3, #4]
|
|
801c0fc: 685b ldr r3, [r3, #4]
|
|
801c0fe: 889b ldrh r3, [r3, #4]
|
|
801c100: b29b uxth r3, r3
|
|
801c102: 2b00 cmp r3, #0
|
|
801c104: d002 beq.n 801c10c <ip_reass_chain_frag_into_datagram_and_validate+0x220>
|
|
valid = 0;
|
|
801c106: 2300 movs r3, #0
|
|
801c108: 623b str r3, [r7, #32]
|
|
801c10a: e041 b.n 801c190 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
|
|
} else {
|
|
/* and check that there are no holes after this datagram */
|
|
iprh_prev = iprh;
|
|
801c10c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c10e: 62bb str r3, [r7, #40] ; 0x28
|
|
q = iprh->next_pbuf;
|
|
801c110: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c112: 681b ldr r3, [r3, #0]
|
|
801c114: 627b str r3, [r7, #36] ; 0x24
|
|
while (q != NULL) {
|
|
801c116: e012 b.n 801c13e <ip_reass_chain_frag_into_datagram_and_validate+0x252>
|
|
iprh = (struct ip_reass_helper *)q->payload;
|
|
801c118: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c11a: 685b ldr r3, [r3, #4]
|
|
801c11c: 62fb str r3, [r7, #44] ; 0x2c
|
|
if (iprh_prev->end != iprh->start) {
|
|
801c11e: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c120: 88db ldrh r3, [r3, #6]
|
|
801c122: b29a uxth r2, r3
|
|
801c124: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c126: 889b ldrh r3, [r3, #4]
|
|
801c128: b29b uxth r3, r3
|
|
801c12a: 429a cmp r2, r3
|
|
801c12c: d002 beq.n 801c134 <ip_reass_chain_frag_into_datagram_and_validate+0x248>
|
|
valid = 0;
|
|
801c12e: 2300 movs r3, #0
|
|
801c130: 623b str r3, [r7, #32]
|
|
break;
|
|
801c132: e007 b.n 801c144 <ip_reass_chain_frag_into_datagram_and_validate+0x258>
|
|
}
|
|
iprh_prev = iprh;
|
|
801c134: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c136: 62bb str r3, [r7, #40] ; 0x28
|
|
q = iprh->next_pbuf;
|
|
801c138: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c13a: 681b ldr r3, [r3, #0]
|
|
801c13c: 627b str r3, [r7, #36] ; 0x24
|
|
while (q != NULL) {
|
|
801c13e: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c140: 2b00 cmp r3, #0
|
|
801c142: d1e9 bne.n 801c118 <ip_reass_chain_frag_into_datagram_and_validate+0x22c>
|
|
}
|
|
/* if still valid, all fragments are received
|
|
* (because to the MF==0 already arrived */
|
|
if (valid) {
|
|
801c144: 6a3b ldr r3, [r7, #32]
|
|
801c146: 2b00 cmp r3, #0
|
|
801c148: d022 beq.n 801c190 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
|
|
LWIP_ASSERT("sanity check", ipr->p != NULL);
|
|
801c14a: 68fb ldr r3, [r7, #12]
|
|
801c14c: 685b ldr r3, [r3, #4]
|
|
801c14e: 2b00 cmp r3, #0
|
|
801c150: d106 bne.n 801c160 <ip_reass_chain_frag_into_datagram_and_validate+0x274>
|
|
801c152: 4b15 ldr r3, [pc, #84] ; (801c1a8 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
|
|
801c154: f240 12df movw r2, #479 ; 0x1df
|
|
801c158: 4917 ldr r1, [pc, #92] ; (801c1b8 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
|
|
801c15a: 4815 ldr r0, [pc, #84] ; (801c1b0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
|
|
801c15c: f000 fdac bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("sanity check",
|
|
801c160: 68fb ldr r3, [r7, #12]
|
|
801c162: 685b ldr r3, [r3, #4]
|
|
801c164: 685b ldr r3, [r3, #4]
|
|
801c166: 6afa ldr r2, [r7, #44] ; 0x2c
|
|
801c168: 429a cmp r2, r3
|
|
801c16a: d106 bne.n 801c17a <ip_reass_chain_frag_into_datagram_and_validate+0x28e>
|
|
801c16c: 4b0e ldr r3, [pc, #56] ; (801c1a8 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
|
|
801c16e: f240 12e1 movw r2, #481 ; 0x1e1
|
|
801c172: 4911 ldr r1, [pc, #68] ; (801c1b8 <ip_reass_chain_frag_into_datagram_and_validate+0x2cc>)
|
|
801c174: 480e ldr r0, [pc, #56] ; (801c1b0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
|
|
801c176: f000 fd9f bl 801ccb8 <iprintf>
|
|
((struct ip_reass_helper *)ipr->p->payload) != iprh);
|
|
LWIP_ASSERT("validate_datagram:next_pbuf!=NULL",
|
|
801c17a: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c17c: 681b ldr r3, [r3, #0]
|
|
801c17e: 2b00 cmp r3, #0
|
|
801c180: d006 beq.n 801c190 <ip_reass_chain_frag_into_datagram_and_validate+0x2a4>
|
|
801c182: 4b09 ldr r3, [pc, #36] ; (801c1a8 <ip_reass_chain_frag_into_datagram_and_validate+0x2bc>)
|
|
801c184: f240 12e3 movw r2, #483 ; 0x1e3
|
|
801c188: 490c ldr r1, [pc, #48] ; (801c1bc <ip_reass_chain_frag_into_datagram_and_validate+0x2d0>)
|
|
801c18a: 4809 ldr r0, [pc, #36] ; (801c1b0 <ip_reass_chain_frag_into_datagram_and_validate+0x2c4>)
|
|
801c18c: f000 fd94 bl 801ccb8 <iprintf>
|
|
}
|
|
}
|
|
/* If valid is 0 here, there are some fragments missing in the middle
|
|
* (since MF == 0 has already arrived). Such datagrams simply time out if
|
|
* no more fragments are received... */
|
|
return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED;
|
|
801c190: 6a3b ldr r3, [r7, #32]
|
|
801c192: 2b00 cmp r3, #0
|
|
801c194: bf14 ite ne
|
|
801c196: 2301 movne r3, #1
|
|
801c198: 2300 moveq r3, #0
|
|
801c19a: b2db uxtb r3, r3
|
|
801c19c: e000 b.n 801c1a0 <ip_reass_chain_frag_into_datagram_and_validate+0x2b4>
|
|
}
|
|
/* If we come here, not all fragments were received, yet! */
|
|
return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */
|
|
801c19e: 2300 movs r3, #0
|
|
}
|
|
801c1a0: 4618 mov r0, r3
|
|
801c1a2: 3730 adds r7, #48 ; 0x30
|
|
801c1a4: 46bd mov sp, r7
|
|
801c1a6: bd80 pop {r7, pc}
|
|
801c1a8: 08020b40 .word 0x08020b40
|
|
801c1ac: 08020c24 .word 0x08020c24
|
|
801c1b0: 08020b88 .word 0x08020b88
|
|
801c1b4: 08020c44 .word 0x08020c44
|
|
801c1b8: 08020c7c .word 0x08020c7c
|
|
801c1bc: 08020c8c .word 0x08020c8c
|
|
|
|
0801c1c0 <ip4_reass>:
|
|
* @param p points to a pbuf chain of the fragment
|
|
* @return NULL if reassembly is incomplete, ? otherwise
|
|
*/
|
|
struct pbuf *
|
|
ip4_reass(struct pbuf *p)
|
|
{
|
|
801c1c0: b580 push {r7, lr}
|
|
801c1c2: b08e sub sp, #56 ; 0x38
|
|
801c1c4: af00 add r7, sp, #0
|
|
801c1c6: 6078 str r0, [r7, #4]
|
|
int is_last;
|
|
|
|
IPFRAG_STATS_INC(ip_frag.recv);
|
|
MIB2_STATS_INC(mib2.ipreasmreqds);
|
|
|
|
fraghdr = (struct ip_hdr *)p->payload;
|
|
801c1c8: 687b ldr r3, [r7, #4]
|
|
801c1ca: 685b ldr r3, [r3, #4]
|
|
801c1cc: 62bb str r3, [r7, #40] ; 0x28
|
|
|
|
if (IPH_HL_BYTES(fraghdr) != IP_HLEN) {
|
|
801c1ce: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c1d0: 781b ldrb r3, [r3, #0]
|
|
801c1d2: f003 030f and.w r3, r3, #15
|
|
801c1d6: b2db uxtb r3, r3
|
|
801c1d8: 009b lsls r3, r3, #2
|
|
801c1da: b2db uxtb r3, r3
|
|
801c1dc: 2b14 cmp r3, #20
|
|
801c1de: f040 8167 bne.w 801c4b0 <ip4_reass+0x2f0>
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n"));
|
|
IPFRAG_STATS_INC(ip_frag.err);
|
|
goto nullreturn;
|
|
}
|
|
|
|
offset = IPH_OFFSET_BYTES(fraghdr);
|
|
801c1e2: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c1e4: 88db ldrh r3, [r3, #6]
|
|
801c1e6: b29b uxth r3, r3
|
|
801c1e8: 4618 mov r0, r3
|
|
801c1ea: f7f4 fc81 bl 8010af0 <lwip_htons>
|
|
801c1ee: 4603 mov r3, r0
|
|
801c1f0: f3c3 030c ubfx r3, r3, #0, #13
|
|
801c1f4: b29b uxth r3, r3
|
|
801c1f6: 00db lsls r3, r3, #3
|
|
801c1f8: 84fb strh r3, [r7, #38] ; 0x26
|
|
len = lwip_ntohs(IPH_LEN(fraghdr));
|
|
801c1fa: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c1fc: 885b ldrh r3, [r3, #2]
|
|
801c1fe: b29b uxth r3, r3
|
|
801c200: 4618 mov r0, r3
|
|
801c202: f7f4 fc75 bl 8010af0 <lwip_htons>
|
|
801c206: 4603 mov r3, r0
|
|
801c208: 84bb strh r3, [r7, #36] ; 0x24
|
|
hlen = IPH_HL_BYTES(fraghdr);
|
|
801c20a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c20c: 781b ldrb r3, [r3, #0]
|
|
801c20e: f003 030f and.w r3, r3, #15
|
|
801c212: b2db uxtb r3, r3
|
|
801c214: 009b lsls r3, r3, #2
|
|
801c216: f887 3023 strb.w r3, [r7, #35] ; 0x23
|
|
if (hlen > len) {
|
|
801c21a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
|
801c21e: b29b uxth r3, r3
|
|
801c220: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
801c222: 429a cmp r2, r3
|
|
801c224: f0c0 8146 bcc.w 801c4b4 <ip4_reass+0x2f4>
|
|
/* invalid datagram */
|
|
goto nullreturn;
|
|
}
|
|
len = (u16_t)(len - hlen);
|
|
801c228: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
|
|
801c22c: b29b uxth r3, r3
|
|
801c22e: 8cba ldrh r2, [r7, #36] ; 0x24
|
|
801c230: 1ad3 subs r3, r2, r3
|
|
801c232: 84bb strh r3, [r7, #36] ; 0x24
|
|
|
|
/* Check if we are allowed to enqueue more datagrams. */
|
|
clen = pbuf_clen(p);
|
|
801c234: 6878 ldr r0, [r7, #4]
|
|
801c236: f7f6 f89d bl 8012374 <pbuf_clen>
|
|
801c23a: 4603 mov r3, r0
|
|
801c23c: 843b strh r3, [r7, #32]
|
|
if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) {
|
|
801c23e: 4ba3 ldr r3, [pc, #652] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c240: 881b ldrh r3, [r3, #0]
|
|
801c242: 461a mov r2, r3
|
|
801c244: 8c3b ldrh r3, [r7, #32]
|
|
801c246: 4413 add r3, r2
|
|
801c248: 2b0a cmp r3, #10
|
|
801c24a: dd10 ble.n 801c26e <ip4_reass+0xae>
|
|
#if IP_REASS_FREE_OLDEST
|
|
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
|
|
801c24c: 8c3b ldrh r3, [r7, #32]
|
|
801c24e: 4619 mov r1, r3
|
|
801c250: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
801c252: f7ff fd81 bl 801bd58 <ip_reass_remove_oldest_datagram>
|
|
801c256: 4603 mov r3, r0
|
|
801c258: 2b00 cmp r3, #0
|
|
801c25a: f000 812d beq.w 801c4b8 <ip4_reass+0x2f8>
|
|
((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS))
|
|
801c25e: 4b9b ldr r3, [pc, #620] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c260: 881b ldrh r3, [r3, #0]
|
|
801c262: 461a mov r2, r3
|
|
801c264: 8c3b ldrh r3, [r7, #32]
|
|
801c266: 4413 add r3, r2
|
|
if (!ip_reass_remove_oldest_datagram(fraghdr, clen) ||
|
|
801c268: 2b0a cmp r3, #10
|
|
801c26a: f300 8125 bgt.w 801c4b8 <ip4_reass+0x2f8>
|
|
}
|
|
}
|
|
|
|
/* Look for the datagram the fragment belongs to in the current datagram queue,
|
|
* remembering the previous in the queue for later dequeueing. */
|
|
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
|
|
801c26e: 4b98 ldr r3, [pc, #608] ; (801c4d0 <ip4_reass+0x310>)
|
|
801c270: 681b ldr r3, [r3, #0]
|
|
801c272: 633b str r3, [r7, #48] ; 0x30
|
|
801c274: e015 b.n 801c2a2 <ip4_reass+0xe2>
|
|
/* Check if the incoming fragment matches the one currently present
|
|
in the reassembly buffer. If so, we proceed with copying the
|
|
fragment into the buffer. */
|
|
if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) {
|
|
801c276: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c278: 695a ldr r2, [r3, #20]
|
|
801c27a: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c27c: 68db ldr r3, [r3, #12]
|
|
801c27e: 429a cmp r2, r3
|
|
801c280: d10c bne.n 801c29c <ip4_reass+0xdc>
|
|
801c282: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c284: 699a ldr r2, [r3, #24]
|
|
801c286: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c288: 691b ldr r3, [r3, #16]
|
|
801c28a: 429a cmp r2, r3
|
|
801c28c: d106 bne.n 801c29c <ip4_reass+0xdc>
|
|
801c28e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c290: 899a ldrh r2, [r3, #12]
|
|
801c292: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c294: 889b ldrh r3, [r3, #4]
|
|
801c296: b29b uxth r3, r3
|
|
801c298: 429a cmp r2, r3
|
|
801c29a: d006 beq.n 801c2aa <ip4_reass+0xea>
|
|
for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) {
|
|
801c29c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c29e: 681b ldr r3, [r3, #0]
|
|
801c2a0: 633b str r3, [r7, #48] ; 0x30
|
|
801c2a2: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c2a4: 2b00 cmp r3, #0
|
|
801c2a6: d1e6 bne.n 801c276 <ip4_reass+0xb6>
|
|
801c2a8: e000 b.n 801c2ac <ip4_reass+0xec>
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n",
|
|
lwip_ntohs(IPH_ID(fraghdr))));
|
|
IPFRAG_STATS_INC(ip_frag.cachehit);
|
|
break;
|
|
801c2aa: bf00 nop
|
|
}
|
|
}
|
|
|
|
if (ipr == NULL) {
|
|
801c2ac: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c2ae: 2b00 cmp r3, #0
|
|
801c2b0: d109 bne.n 801c2c6 <ip4_reass+0x106>
|
|
/* Enqueue a new datagram into the datagram queue */
|
|
ipr = ip_reass_enqueue_new_datagram(fraghdr, clen);
|
|
801c2b2: 8c3b ldrh r3, [r7, #32]
|
|
801c2b4: 4619 mov r1, r3
|
|
801c2b6: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
801c2b8: f7ff fdb0 bl 801be1c <ip_reass_enqueue_new_datagram>
|
|
801c2bc: 6338 str r0, [r7, #48] ; 0x30
|
|
/* Bail if unable to enqueue */
|
|
if (ipr == NULL) {
|
|
801c2be: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c2c0: 2b00 cmp r3, #0
|
|
801c2c2: d11c bne.n 801c2fe <ip4_reass+0x13e>
|
|
goto nullreturn;
|
|
801c2c4: e0f9 b.n 801c4ba <ip4_reass+0x2fa>
|
|
}
|
|
} else {
|
|
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
|
|
801c2c6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c2c8: 88db ldrh r3, [r3, #6]
|
|
801c2ca: b29b uxth r3, r3
|
|
801c2cc: 4618 mov r0, r3
|
|
801c2ce: f7f4 fc0f bl 8010af0 <lwip_htons>
|
|
801c2d2: 4603 mov r3, r0
|
|
801c2d4: f3c3 030c ubfx r3, r3, #0, #13
|
|
801c2d8: 2b00 cmp r3, #0
|
|
801c2da: d110 bne.n 801c2fe <ip4_reass+0x13e>
|
|
((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) {
|
|
801c2dc: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c2de: 89db ldrh r3, [r3, #14]
|
|
801c2e0: 4618 mov r0, r3
|
|
801c2e2: f7f4 fc05 bl 8010af0 <lwip_htons>
|
|
801c2e6: 4603 mov r3, r0
|
|
801c2e8: f3c3 030c ubfx r3, r3, #0, #13
|
|
if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) &&
|
|
801c2ec: 2b00 cmp r3, #0
|
|
801c2ee: d006 beq.n 801c2fe <ip4_reass+0x13e>
|
|
/* ipr->iphdr is not the header from the first fragment, but fraghdr is
|
|
* -> copy fraghdr into ipr->iphdr since we want to have the header
|
|
* of the first fragment (for ICMP time exceeded and later, for copying
|
|
* all options, if supported)*/
|
|
SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN);
|
|
801c2f0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c2f2: 3308 adds r3, #8
|
|
801c2f4: 2214 movs r2, #20
|
|
801c2f6: 6ab9 ldr r1, [r7, #40] ; 0x28
|
|
801c2f8: 4618 mov r0, r3
|
|
801c2fa: f000 fcb0 bl 801cc5e <memcpy>
|
|
|
|
/* At this point, we have either created a new entry or pointing
|
|
* to an existing one */
|
|
|
|
/* check for 'no more fragments', and update queue entry*/
|
|
is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0;
|
|
801c2fe: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c300: 88db ldrh r3, [r3, #6]
|
|
801c302: b29b uxth r3, r3
|
|
801c304: f003 0320 and.w r3, r3, #32
|
|
801c308: 2b00 cmp r3, #0
|
|
801c30a: bf0c ite eq
|
|
801c30c: 2301 moveq r3, #1
|
|
801c30e: 2300 movne r3, #0
|
|
801c310: b2db uxtb r3, r3
|
|
801c312: 61fb str r3, [r7, #28]
|
|
if (is_last) {
|
|
801c314: 69fb ldr r3, [r7, #28]
|
|
801c316: 2b00 cmp r3, #0
|
|
801c318: d00e beq.n 801c338 <ip4_reass+0x178>
|
|
u16_t datagram_len = (u16_t)(offset + len);
|
|
801c31a: 8cfa ldrh r2, [r7, #38] ; 0x26
|
|
801c31c: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
801c31e: 4413 add r3, r2
|
|
801c320: 837b strh r3, [r7, #26]
|
|
if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) {
|
|
801c322: 8b7a ldrh r2, [r7, #26]
|
|
801c324: 8cfb ldrh r3, [r7, #38] ; 0x26
|
|
801c326: 429a cmp r2, r3
|
|
801c328: f0c0 80a0 bcc.w 801c46c <ip4_reass+0x2ac>
|
|
801c32c: 8b7b ldrh r3, [r7, #26]
|
|
801c32e: f64f 72eb movw r2, #65515 ; 0xffeb
|
|
801c332: 4293 cmp r3, r2
|
|
801c334: f200 809a bhi.w 801c46c <ip4_reass+0x2ac>
|
|
goto nullreturn_ipr;
|
|
}
|
|
}
|
|
/* find the right place to insert this pbuf */
|
|
/* @todo: trim pbufs if fragments are overlapping */
|
|
valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last);
|
|
801c338: 69fa ldr r2, [r7, #28]
|
|
801c33a: 6879 ldr r1, [r7, #4]
|
|
801c33c: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
801c33e: f7ff fdd5 bl 801beec <ip_reass_chain_frag_into_datagram_and_validate>
|
|
801c342: 6178 str r0, [r7, #20]
|
|
if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) {
|
|
801c344: 697b ldr r3, [r7, #20]
|
|
801c346: f1b3 3fff cmp.w r3, #4294967295
|
|
801c34a: f000 8091 beq.w 801c470 <ip4_reass+0x2b0>
|
|
/* if we come here, the pbuf has been enqueued */
|
|
|
|
/* Track the current number of pbufs current 'in-flight', in order to limit
|
|
the number of fragments that may be enqueued at any one time
|
|
(overflow checked by testing against IP_REASS_MAX_PBUFS) */
|
|
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen);
|
|
801c34e: 4b5f ldr r3, [pc, #380] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c350: 881a ldrh r2, [r3, #0]
|
|
801c352: 8c3b ldrh r3, [r7, #32]
|
|
801c354: 4413 add r3, r2
|
|
801c356: b29a uxth r2, r3
|
|
801c358: 4b5c ldr r3, [pc, #368] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c35a: 801a strh r2, [r3, #0]
|
|
if (is_last) {
|
|
801c35c: 69fb ldr r3, [r7, #28]
|
|
801c35e: 2b00 cmp r3, #0
|
|
801c360: d00d beq.n 801c37e <ip4_reass+0x1be>
|
|
u16_t datagram_len = (u16_t)(offset + len);
|
|
801c362: 8cfa ldrh r2, [r7, #38] ; 0x26
|
|
801c364: 8cbb ldrh r3, [r7, #36] ; 0x24
|
|
801c366: 4413 add r3, r2
|
|
801c368: 827b strh r3, [r7, #18]
|
|
ipr->datagram_len = datagram_len;
|
|
801c36a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c36c: 8a7a ldrh r2, [r7, #18]
|
|
801c36e: 839a strh r2, [r3, #28]
|
|
ipr->flags |= IP_REASS_FLAG_LASTFRAG;
|
|
801c370: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c372: 7f9b ldrb r3, [r3, #30]
|
|
801c374: f043 0301 orr.w r3, r3, #1
|
|
801c378: b2da uxtb r2, r3
|
|
801c37a: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c37c: 779a strb r2, [r3, #30]
|
|
LWIP_DEBUGF(IP_REASS_DEBUG,
|
|
("ip4_reass: last fragment seen, total len %"S16_F"\n",
|
|
ipr->datagram_len));
|
|
}
|
|
|
|
if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) {
|
|
801c37e: 697b ldr r3, [r7, #20]
|
|
801c380: 2b01 cmp r3, #1
|
|
801c382: d171 bne.n 801c468 <ip4_reass+0x2a8>
|
|
struct ip_reassdata *ipr_prev;
|
|
/* the totally last fragment (flag more fragments = 0) was received at least
|
|
* once AND all fragments are received */
|
|
u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN);
|
|
801c384: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c386: 8b9b ldrh r3, [r3, #28]
|
|
801c388: 3314 adds r3, #20
|
|
801c38a: 823b strh r3, [r7, #16]
|
|
|
|
/* save the second pbuf before copying the header over the pointer */
|
|
r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf;
|
|
801c38c: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c38e: 685b ldr r3, [r3, #4]
|
|
801c390: 685b ldr r3, [r3, #4]
|
|
801c392: 681b ldr r3, [r3, #0]
|
|
801c394: 637b str r3, [r7, #52] ; 0x34
|
|
|
|
/* copy the original ip header back to the first pbuf */
|
|
fraghdr = (struct ip_hdr *)(ipr->p->payload);
|
|
801c396: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c398: 685b ldr r3, [r3, #4]
|
|
801c39a: 685b ldr r3, [r3, #4]
|
|
801c39c: 62bb str r3, [r7, #40] ; 0x28
|
|
SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN);
|
|
801c39e: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c3a0: 3308 adds r3, #8
|
|
801c3a2: 2214 movs r2, #20
|
|
801c3a4: 4619 mov r1, r3
|
|
801c3a6: 6ab8 ldr r0, [r7, #40] ; 0x28
|
|
801c3a8: f000 fc59 bl 801cc5e <memcpy>
|
|
IPH_LEN_SET(fraghdr, lwip_htons(datagram_len));
|
|
801c3ac: 8a3b ldrh r3, [r7, #16]
|
|
801c3ae: 4618 mov r0, r3
|
|
801c3b0: f7f4 fb9e bl 8010af0 <lwip_htons>
|
|
801c3b4: 4603 mov r3, r0
|
|
801c3b6: 461a mov r2, r3
|
|
801c3b8: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c3ba: 805a strh r2, [r3, #2]
|
|
IPH_OFFSET_SET(fraghdr, 0);
|
|
801c3bc: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c3be: 2200 movs r2, #0
|
|
801c3c0: 719a strb r2, [r3, #6]
|
|
801c3c2: 2200 movs r2, #0
|
|
801c3c4: 71da strb r2, [r3, #7]
|
|
IPH_CHKSUM_SET(fraghdr, 0);
|
|
801c3c6: 6abb ldr r3, [r7, #40] ; 0x28
|
|
801c3c8: 2200 movs r2, #0
|
|
801c3ca: 729a strb r2, [r3, #10]
|
|
801c3cc: 2200 movs r2, #0
|
|
801c3ce: 72da strb r2, [r3, #11]
|
|
IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) {
|
|
IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN));
|
|
}
|
|
#endif /* CHECKSUM_GEN_IP */
|
|
|
|
p = ipr->p;
|
|
801c3d0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c3d2: 685b ldr r3, [r3, #4]
|
|
801c3d4: 607b str r3, [r7, #4]
|
|
|
|
/* chain together the pbufs contained within the reass_data list. */
|
|
while (r != NULL) {
|
|
801c3d6: e00d b.n 801c3f4 <ip4_reass+0x234>
|
|
iprh = (struct ip_reass_helper *)r->payload;
|
|
801c3d8: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801c3da: 685b ldr r3, [r3, #4]
|
|
801c3dc: 60fb str r3, [r7, #12]
|
|
|
|
/* hide the ip header for every succeeding fragment */
|
|
pbuf_remove_header(r, IP_HLEN);
|
|
801c3de: 2114 movs r1, #20
|
|
801c3e0: 6b78 ldr r0, [r7, #52] ; 0x34
|
|
801c3e2: f7f5 feb3 bl 801214c <pbuf_remove_header>
|
|
pbuf_cat(p, r);
|
|
801c3e6: 6b79 ldr r1, [r7, #52] ; 0x34
|
|
801c3e8: 6878 ldr r0, [r7, #4]
|
|
801c3ea: f7f6 f803 bl 80123f4 <pbuf_cat>
|
|
r = iprh->next_pbuf;
|
|
801c3ee: 68fb ldr r3, [r7, #12]
|
|
801c3f0: 681b ldr r3, [r3, #0]
|
|
801c3f2: 637b str r3, [r7, #52] ; 0x34
|
|
while (r != NULL) {
|
|
801c3f4: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801c3f6: 2b00 cmp r3, #0
|
|
801c3f8: d1ee bne.n 801c3d8 <ip4_reass+0x218>
|
|
}
|
|
|
|
/* find the previous entry in the linked list */
|
|
if (ipr == reassdatagrams) {
|
|
801c3fa: 4b35 ldr r3, [pc, #212] ; (801c4d0 <ip4_reass+0x310>)
|
|
801c3fc: 681b ldr r3, [r3, #0]
|
|
801c3fe: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
801c400: 429a cmp r2, r3
|
|
801c402: d102 bne.n 801c40a <ip4_reass+0x24a>
|
|
ipr_prev = NULL;
|
|
801c404: 2300 movs r3, #0
|
|
801c406: 62fb str r3, [r7, #44] ; 0x2c
|
|
801c408: e010 b.n 801c42c <ip4_reass+0x26c>
|
|
} else {
|
|
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
|
|
801c40a: 4b31 ldr r3, [pc, #196] ; (801c4d0 <ip4_reass+0x310>)
|
|
801c40c: 681b ldr r3, [r3, #0]
|
|
801c40e: 62fb str r3, [r7, #44] ; 0x2c
|
|
801c410: e007 b.n 801c422 <ip4_reass+0x262>
|
|
if (ipr_prev->next == ipr) {
|
|
801c412: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c414: 681b ldr r3, [r3, #0]
|
|
801c416: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
801c418: 429a cmp r2, r3
|
|
801c41a: d006 beq.n 801c42a <ip4_reass+0x26a>
|
|
for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) {
|
|
801c41c: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c41e: 681b ldr r3, [r3, #0]
|
|
801c420: 62fb str r3, [r7, #44] ; 0x2c
|
|
801c422: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c424: 2b00 cmp r3, #0
|
|
801c426: d1f4 bne.n 801c412 <ip4_reass+0x252>
|
|
801c428: e000 b.n 801c42c <ip4_reass+0x26c>
|
|
break;
|
|
801c42a: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
|
|
/* release the sources allocate for the fragment queue entry */
|
|
ip_reass_dequeue_datagram(ipr, ipr_prev);
|
|
801c42c: 6af9 ldr r1, [r7, #44] ; 0x2c
|
|
801c42e: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
801c430: f7ff fd2e bl 801be90 <ip_reass_dequeue_datagram>
|
|
|
|
/* and adjust the number of pbufs currently queued for reassembly. */
|
|
clen = pbuf_clen(p);
|
|
801c434: 6878 ldr r0, [r7, #4]
|
|
801c436: f7f5 ff9d bl 8012374 <pbuf_clen>
|
|
801c43a: 4603 mov r3, r0
|
|
801c43c: 843b strh r3, [r7, #32]
|
|
LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen);
|
|
801c43e: 4b23 ldr r3, [pc, #140] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c440: 881b ldrh r3, [r3, #0]
|
|
801c442: 8c3a ldrh r2, [r7, #32]
|
|
801c444: 429a cmp r2, r3
|
|
801c446: d906 bls.n 801c456 <ip4_reass+0x296>
|
|
801c448: 4b22 ldr r3, [pc, #136] ; (801c4d4 <ip4_reass+0x314>)
|
|
801c44a: f240 229b movw r2, #667 ; 0x29b
|
|
801c44e: 4922 ldr r1, [pc, #136] ; (801c4d8 <ip4_reass+0x318>)
|
|
801c450: 4822 ldr r0, [pc, #136] ; (801c4dc <ip4_reass+0x31c>)
|
|
801c452: f000 fc31 bl 801ccb8 <iprintf>
|
|
ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen);
|
|
801c456: 4b1d ldr r3, [pc, #116] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c458: 881a ldrh r2, [r3, #0]
|
|
801c45a: 8c3b ldrh r3, [r7, #32]
|
|
801c45c: 1ad3 subs r3, r2, r3
|
|
801c45e: b29a uxth r2, r3
|
|
801c460: 4b1a ldr r3, [pc, #104] ; (801c4cc <ip4_reass+0x30c>)
|
|
801c462: 801a strh r2, [r3, #0]
|
|
|
|
MIB2_STATS_INC(mib2.ipreasmoks);
|
|
|
|
/* Return the pbuf chain */
|
|
return p;
|
|
801c464: 687b ldr r3, [r7, #4]
|
|
801c466: e02c b.n 801c4c2 <ip4_reass+0x302>
|
|
}
|
|
/* the datagram is not (yet?) reassembled completely */
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount));
|
|
return NULL;
|
|
801c468: 2300 movs r3, #0
|
|
801c46a: e02a b.n 801c4c2 <ip4_reass+0x302>
|
|
|
|
nullreturn_ipr:
|
|
801c46c: bf00 nop
|
|
801c46e: e000 b.n 801c472 <ip4_reass+0x2b2>
|
|
goto nullreturn_ipr;
|
|
801c470: bf00 nop
|
|
LWIP_ASSERT("ipr != NULL", ipr != NULL);
|
|
801c472: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c474: 2b00 cmp r3, #0
|
|
801c476: d106 bne.n 801c486 <ip4_reass+0x2c6>
|
|
801c478: 4b16 ldr r3, [pc, #88] ; (801c4d4 <ip4_reass+0x314>)
|
|
801c47a: f44f 722a mov.w r2, #680 ; 0x2a8
|
|
801c47e: 4918 ldr r1, [pc, #96] ; (801c4e0 <ip4_reass+0x320>)
|
|
801c480: 4816 ldr r0, [pc, #88] ; (801c4dc <ip4_reass+0x31c>)
|
|
801c482: f000 fc19 bl 801ccb8 <iprintf>
|
|
if (ipr->p == NULL) {
|
|
801c486: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c488: 685b ldr r3, [r3, #4]
|
|
801c48a: 2b00 cmp r3, #0
|
|
801c48c: d114 bne.n 801c4b8 <ip4_reass+0x2f8>
|
|
/* dropped pbuf after creating a new datagram entry: remove the entry, too */
|
|
LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams);
|
|
801c48e: 4b10 ldr r3, [pc, #64] ; (801c4d0 <ip4_reass+0x310>)
|
|
801c490: 681b ldr r3, [r3, #0]
|
|
801c492: 6b3a ldr r2, [r7, #48] ; 0x30
|
|
801c494: 429a cmp r2, r3
|
|
801c496: d006 beq.n 801c4a6 <ip4_reass+0x2e6>
|
|
801c498: 4b0e ldr r3, [pc, #56] ; (801c4d4 <ip4_reass+0x314>)
|
|
801c49a: f240 22ab movw r2, #683 ; 0x2ab
|
|
801c49e: 4911 ldr r1, [pc, #68] ; (801c4e4 <ip4_reass+0x324>)
|
|
801c4a0: 480e ldr r0, [pc, #56] ; (801c4dc <ip4_reass+0x31c>)
|
|
801c4a2: f000 fc09 bl 801ccb8 <iprintf>
|
|
ip_reass_dequeue_datagram(ipr, NULL);
|
|
801c4a6: 2100 movs r1, #0
|
|
801c4a8: 6b38 ldr r0, [r7, #48] ; 0x30
|
|
801c4aa: f7ff fcf1 bl 801be90 <ip_reass_dequeue_datagram>
|
|
801c4ae: e004 b.n 801c4ba <ip4_reass+0x2fa>
|
|
goto nullreturn;
|
|
801c4b0: bf00 nop
|
|
801c4b2: e002 b.n 801c4ba <ip4_reass+0x2fa>
|
|
goto nullreturn;
|
|
801c4b4: bf00 nop
|
|
801c4b6: e000 b.n 801c4ba <ip4_reass+0x2fa>
|
|
}
|
|
|
|
nullreturn:
|
|
801c4b8: bf00 nop
|
|
LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n"));
|
|
IPFRAG_STATS_INC(ip_frag.drop);
|
|
pbuf_free(p);
|
|
801c4ba: 6878 ldr r0, [r7, #4]
|
|
801c4bc: f7f5 fecc bl 8012258 <pbuf_free>
|
|
return NULL;
|
|
801c4c0: 2300 movs r3, #0
|
|
}
|
|
801c4c2: 4618 mov r0, r3
|
|
801c4c4: 3738 adds r7, #56 ; 0x38
|
|
801c4c6: 46bd mov sp, r7
|
|
801c4c8: bd80 pop {r7, pc}
|
|
801c4ca: bf00 nop
|
|
801c4cc: 20008870 .word 0x20008870
|
|
801c4d0: 2000886c .word 0x2000886c
|
|
801c4d4: 08020b40 .word 0x08020b40
|
|
801c4d8: 08020cb0 .word 0x08020cb0
|
|
801c4dc: 08020b88 .word 0x08020b88
|
|
801c4e0: 08020ccc .word 0x08020ccc
|
|
801c4e4: 08020cd8 .word 0x08020cd8
|
|
|
|
0801c4e8 <ip_frag_alloc_pbuf_custom_ref>:
|
|
#if IP_FRAG
|
|
#if !LWIP_NETIF_TX_SINGLE_PBUF
|
|
/** Allocate a new struct pbuf_custom_ref */
|
|
static struct pbuf_custom_ref *
|
|
ip_frag_alloc_pbuf_custom_ref(void)
|
|
{
|
|
801c4e8: b580 push {r7, lr}
|
|
801c4ea: af00 add r7, sp, #0
|
|
return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF);
|
|
801c4ec: 2005 movs r0, #5
|
|
801c4ee: f7f4 ffb5 bl 801145c <memp_malloc>
|
|
801c4f2: 4603 mov r3, r0
|
|
}
|
|
801c4f4: 4618 mov r0, r3
|
|
801c4f6: bd80 pop {r7, pc}
|
|
|
|
0801c4f8 <ip_frag_free_pbuf_custom_ref>:
|
|
|
|
/** Free a struct pbuf_custom_ref */
|
|
static void
|
|
ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p)
|
|
{
|
|
801c4f8: b580 push {r7, lr}
|
|
801c4fa: b082 sub sp, #8
|
|
801c4fc: af00 add r7, sp, #0
|
|
801c4fe: 6078 str r0, [r7, #4]
|
|
LWIP_ASSERT("p != NULL", p != NULL);
|
|
801c500: 687b ldr r3, [r7, #4]
|
|
801c502: 2b00 cmp r3, #0
|
|
801c504: d106 bne.n 801c514 <ip_frag_free_pbuf_custom_ref+0x1c>
|
|
801c506: 4b07 ldr r3, [pc, #28] ; (801c524 <ip_frag_free_pbuf_custom_ref+0x2c>)
|
|
801c508: f44f 7231 mov.w r2, #708 ; 0x2c4
|
|
801c50c: 4906 ldr r1, [pc, #24] ; (801c528 <ip_frag_free_pbuf_custom_ref+0x30>)
|
|
801c50e: 4807 ldr r0, [pc, #28] ; (801c52c <ip_frag_free_pbuf_custom_ref+0x34>)
|
|
801c510: f000 fbd2 bl 801ccb8 <iprintf>
|
|
memp_free(MEMP_FRAG_PBUF, p);
|
|
801c514: 6879 ldr r1, [r7, #4]
|
|
801c516: 2005 movs r0, #5
|
|
801c518: f7f4 fff2 bl 8011500 <memp_free>
|
|
}
|
|
801c51c: bf00 nop
|
|
801c51e: 3708 adds r7, #8
|
|
801c520: 46bd mov sp, r7
|
|
801c522: bd80 pop {r7, pc}
|
|
801c524: 08020b40 .word 0x08020b40
|
|
801c528: 08020cf8 .word 0x08020cf8
|
|
801c52c: 08020b88 .word 0x08020b88
|
|
|
|
0801c530 <ipfrag_free_pbuf_custom>:
|
|
|
|
/** Free-callback function to free a 'struct pbuf_custom_ref', called by
|
|
* pbuf_free. */
|
|
static void
|
|
ipfrag_free_pbuf_custom(struct pbuf *p)
|
|
{
|
|
801c530: b580 push {r7, lr}
|
|
801c532: b084 sub sp, #16
|
|
801c534: af00 add r7, sp, #0
|
|
801c536: 6078 str r0, [r7, #4]
|
|
struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p;
|
|
801c538: 687b ldr r3, [r7, #4]
|
|
801c53a: 60fb str r3, [r7, #12]
|
|
LWIP_ASSERT("pcr != NULL", pcr != NULL);
|
|
801c53c: 68fb ldr r3, [r7, #12]
|
|
801c53e: 2b00 cmp r3, #0
|
|
801c540: d106 bne.n 801c550 <ipfrag_free_pbuf_custom+0x20>
|
|
801c542: 4b11 ldr r3, [pc, #68] ; (801c588 <ipfrag_free_pbuf_custom+0x58>)
|
|
801c544: f240 22ce movw r2, #718 ; 0x2ce
|
|
801c548: 4910 ldr r1, [pc, #64] ; (801c58c <ipfrag_free_pbuf_custom+0x5c>)
|
|
801c54a: 4811 ldr r0, [pc, #68] ; (801c590 <ipfrag_free_pbuf_custom+0x60>)
|
|
801c54c: f000 fbb4 bl 801ccb8 <iprintf>
|
|
LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p);
|
|
801c550: 68fa ldr r2, [r7, #12]
|
|
801c552: 687b ldr r3, [r7, #4]
|
|
801c554: 429a cmp r2, r3
|
|
801c556: d006 beq.n 801c566 <ipfrag_free_pbuf_custom+0x36>
|
|
801c558: 4b0b ldr r3, [pc, #44] ; (801c588 <ipfrag_free_pbuf_custom+0x58>)
|
|
801c55a: f240 22cf movw r2, #719 ; 0x2cf
|
|
801c55e: 490d ldr r1, [pc, #52] ; (801c594 <ipfrag_free_pbuf_custom+0x64>)
|
|
801c560: 480b ldr r0, [pc, #44] ; (801c590 <ipfrag_free_pbuf_custom+0x60>)
|
|
801c562: f000 fba9 bl 801ccb8 <iprintf>
|
|
if (pcr->original != NULL) {
|
|
801c566: 68fb ldr r3, [r7, #12]
|
|
801c568: 695b ldr r3, [r3, #20]
|
|
801c56a: 2b00 cmp r3, #0
|
|
801c56c: d004 beq.n 801c578 <ipfrag_free_pbuf_custom+0x48>
|
|
pbuf_free(pcr->original);
|
|
801c56e: 68fb ldr r3, [r7, #12]
|
|
801c570: 695b ldr r3, [r3, #20]
|
|
801c572: 4618 mov r0, r3
|
|
801c574: f7f5 fe70 bl 8012258 <pbuf_free>
|
|
}
|
|
ip_frag_free_pbuf_custom_ref(pcr);
|
|
801c578: 68f8 ldr r0, [r7, #12]
|
|
801c57a: f7ff ffbd bl 801c4f8 <ip_frag_free_pbuf_custom_ref>
|
|
}
|
|
801c57e: bf00 nop
|
|
801c580: 3710 adds r7, #16
|
|
801c582: 46bd mov sp, r7
|
|
801c584: bd80 pop {r7, pc}
|
|
801c586: bf00 nop
|
|
801c588: 08020b40 .word 0x08020b40
|
|
801c58c: 08020d04 .word 0x08020d04
|
|
801c590: 08020b88 .word 0x08020b88
|
|
801c594: 08020d10 .word 0x08020d10
|
|
|
|
0801c598 <ip4_frag>:
|
|
*
|
|
* @return ERR_OK if sent successfully, err_t otherwise
|
|
*/
|
|
err_t
|
|
ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest)
|
|
{
|
|
801c598: b580 push {r7, lr}
|
|
801c59a: b094 sub sp, #80 ; 0x50
|
|
801c59c: af02 add r7, sp, #8
|
|
801c59e: 60f8 str r0, [r7, #12]
|
|
801c5a0: 60b9 str r1, [r7, #8]
|
|
801c5a2: 607a str r2, [r7, #4]
|
|
struct pbuf *rambuf;
|
|
#if !LWIP_NETIF_TX_SINGLE_PBUF
|
|
struct pbuf *newpbuf;
|
|
u16_t newpbuflen = 0;
|
|
801c5a4: 2300 movs r3, #0
|
|
801c5a6: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
|
|
u16_t left_to_copy;
|
|
#endif
|
|
struct ip_hdr *original_iphdr;
|
|
struct ip_hdr *iphdr;
|
|
const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8);
|
|
801c5aa: 68bb ldr r3, [r7, #8]
|
|
801c5ac: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
801c5ae: 3b14 subs r3, #20
|
|
801c5b0: 2b00 cmp r3, #0
|
|
801c5b2: da00 bge.n 801c5b6 <ip4_frag+0x1e>
|
|
801c5b4: 3307 adds r3, #7
|
|
801c5b6: 10db asrs r3, r3, #3
|
|
801c5b8: 877b strh r3, [r7, #58] ; 0x3a
|
|
u16_t left, fragsize;
|
|
u16_t ofo;
|
|
int last;
|
|
u16_t poff = IP_HLEN;
|
|
801c5ba: 2314 movs r3, #20
|
|
801c5bc: 87fb strh r3, [r7, #62] ; 0x3e
|
|
u16_t tmp;
|
|
int mf_set;
|
|
|
|
original_iphdr = (struct ip_hdr *)p->payload;
|
|
801c5be: 68fb ldr r3, [r7, #12]
|
|
801c5c0: 685b ldr r3, [r3, #4]
|
|
801c5c2: 637b str r3, [r7, #52] ; 0x34
|
|
iphdr = original_iphdr;
|
|
801c5c4: 6b7b ldr r3, [r7, #52] ; 0x34
|
|
801c5c6: 633b str r3, [r7, #48] ; 0x30
|
|
if (IPH_HL_BYTES(iphdr) != IP_HLEN) {
|
|
801c5c8: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c5ca: 781b ldrb r3, [r3, #0]
|
|
801c5cc: f003 030f and.w r3, r3, #15
|
|
801c5d0: b2db uxtb r3, r3
|
|
801c5d2: 009b lsls r3, r3, #2
|
|
801c5d4: b2db uxtb r3, r3
|
|
801c5d6: 2b14 cmp r3, #20
|
|
801c5d8: d002 beq.n 801c5e0 <ip4_frag+0x48>
|
|
/* ip4_frag() does not support IP options */
|
|
return ERR_VAL;
|
|
801c5da: f06f 0305 mvn.w r3, #5
|
|
801c5de: e10f b.n 801c800 <ip4_frag+0x268>
|
|
}
|
|
LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL);
|
|
801c5e0: 68fb ldr r3, [r7, #12]
|
|
801c5e2: 895b ldrh r3, [r3, #10]
|
|
801c5e4: 2b13 cmp r3, #19
|
|
801c5e6: d809 bhi.n 801c5fc <ip4_frag+0x64>
|
|
801c5e8: 4b87 ldr r3, [pc, #540] ; (801c808 <ip4_frag+0x270>)
|
|
801c5ea: f44f 723f mov.w r2, #764 ; 0x2fc
|
|
801c5ee: 4987 ldr r1, [pc, #540] ; (801c80c <ip4_frag+0x274>)
|
|
801c5f0: 4887 ldr r0, [pc, #540] ; (801c810 <ip4_frag+0x278>)
|
|
801c5f2: f000 fb61 bl 801ccb8 <iprintf>
|
|
801c5f6: f06f 0305 mvn.w r3, #5
|
|
801c5fa: e101 b.n 801c800 <ip4_frag+0x268>
|
|
|
|
/* Save original offset */
|
|
tmp = lwip_ntohs(IPH_OFFSET(iphdr));
|
|
801c5fc: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c5fe: 88db ldrh r3, [r3, #6]
|
|
801c600: b29b uxth r3, r3
|
|
801c602: 4618 mov r0, r3
|
|
801c604: f7f4 fa74 bl 8010af0 <lwip_htons>
|
|
801c608: 4603 mov r3, r0
|
|
801c60a: 87bb strh r3, [r7, #60] ; 0x3c
|
|
ofo = tmp & IP_OFFMASK;
|
|
801c60c: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
801c60e: f3c3 030c ubfx r3, r3, #0, #13
|
|
801c612: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
|
|
/* already fragmented? if so, the last fragment we create must have MF, too */
|
|
mf_set = tmp & IP_MF;
|
|
801c616: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
801c618: f403 5300 and.w r3, r3, #8192 ; 0x2000
|
|
801c61c: 62fb str r3, [r7, #44] ; 0x2c
|
|
|
|
left = (u16_t)(p->tot_len - IP_HLEN);
|
|
801c61e: 68fb ldr r3, [r7, #12]
|
|
801c620: 891b ldrh r3, [r3, #8]
|
|
801c622: 3b14 subs r3, #20
|
|
801c624: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
|
|
|
while (left) {
|
|
801c628: e0e0 b.n 801c7ec <ip4_frag+0x254>
|
|
/* Fill this fragment */
|
|
fragsize = LWIP_MIN(left, (u16_t)(nfb * 8));
|
|
801c62a: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
801c62c: 00db lsls r3, r3, #3
|
|
801c62e: b29b uxth r3, r3
|
|
801c630: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
801c634: 4293 cmp r3, r2
|
|
801c636: bf28 it cs
|
|
801c638: 4613 movcs r3, r2
|
|
801c63a: 857b strh r3, [r7, #42] ; 0x2a
|
|
/* When not using a static buffer, create a chain of pbufs.
|
|
* The first will be a PBUF_RAM holding the link and IP header.
|
|
* The rest will be PBUF_REFs mirroring the pbuf chain to be fragged,
|
|
* but limited to the size of an mtu.
|
|
*/
|
|
rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM);
|
|
801c63c: f44f 7220 mov.w r2, #640 ; 0x280
|
|
801c640: 2114 movs r1, #20
|
|
801c642: 200e movs r0, #14
|
|
801c644: f7f5 fb28 bl 8011c98 <pbuf_alloc>
|
|
801c648: 6278 str r0, [r7, #36] ; 0x24
|
|
if (rambuf == NULL) {
|
|
801c64a: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c64c: 2b00 cmp r3, #0
|
|
801c64e: f000 80d4 beq.w 801c7fa <ip4_frag+0x262>
|
|
goto memerr;
|
|
}
|
|
LWIP_ASSERT("this needs a pbuf in one piece!",
|
|
801c652: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c654: 895b ldrh r3, [r3, #10]
|
|
801c656: 2b13 cmp r3, #19
|
|
801c658: d806 bhi.n 801c668 <ip4_frag+0xd0>
|
|
801c65a: 4b6b ldr r3, [pc, #428] ; (801c808 <ip4_frag+0x270>)
|
|
801c65c: f240 3225 movw r2, #805 ; 0x325
|
|
801c660: 496c ldr r1, [pc, #432] ; (801c814 <ip4_frag+0x27c>)
|
|
801c662: 486b ldr r0, [pc, #428] ; (801c810 <ip4_frag+0x278>)
|
|
801c664: f000 fb28 bl 801ccb8 <iprintf>
|
|
(rambuf->len >= (IP_HLEN)));
|
|
SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN);
|
|
801c668: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c66a: 685b ldr r3, [r3, #4]
|
|
801c66c: 2214 movs r2, #20
|
|
801c66e: 6b79 ldr r1, [r7, #52] ; 0x34
|
|
801c670: 4618 mov r0, r3
|
|
801c672: f000 faf4 bl 801cc5e <memcpy>
|
|
iphdr = (struct ip_hdr *)rambuf->payload;
|
|
801c676: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801c678: 685b ldr r3, [r3, #4]
|
|
801c67a: 633b str r3, [r7, #48] ; 0x30
|
|
|
|
left_to_copy = fragsize;
|
|
801c67c: 8d7b ldrh r3, [r7, #42] ; 0x2a
|
|
801c67e: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
|
|
while (left_to_copy) {
|
|
801c682: e064 b.n 801c74e <ip4_frag+0x1b6>
|
|
struct pbuf_custom_ref *pcr;
|
|
u16_t plen = (u16_t)(p->len - poff);
|
|
801c684: 68fb ldr r3, [r7, #12]
|
|
801c686: 895a ldrh r2, [r3, #10]
|
|
801c688: 8ffb ldrh r3, [r7, #62] ; 0x3e
|
|
801c68a: 1ad3 subs r3, r2, r3
|
|
801c68c: 83fb strh r3, [r7, #30]
|
|
LWIP_ASSERT("p->len >= poff", p->len >= poff);
|
|
801c68e: 68fb ldr r3, [r7, #12]
|
|
801c690: 895b ldrh r3, [r3, #10]
|
|
801c692: 8ffa ldrh r2, [r7, #62] ; 0x3e
|
|
801c694: 429a cmp r2, r3
|
|
801c696: d906 bls.n 801c6a6 <ip4_frag+0x10e>
|
|
801c698: 4b5b ldr r3, [pc, #364] ; (801c808 <ip4_frag+0x270>)
|
|
801c69a: f240 322d movw r2, #813 ; 0x32d
|
|
801c69e: 495e ldr r1, [pc, #376] ; (801c818 <ip4_frag+0x280>)
|
|
801c6a0: 485b ldr r0, [pc, #364] ; (801c810 <ip4_frag+0x278>)
|
|
801c6a2: f000 fb09 bl 801ccb8 <iprintf>
|
|
newpbuflen = LWIP_MIN(left_to_copy, plen);
|
|
801c6a6: 8bfa ldrh r2, [r7, #30]
|
|
801c6a8: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
|
|
801c6ac: 4293 cmp r3, r2
|
|
801c6ae: bf28 it cs
|
|
801c6b0: 4613 movcs r3, r2
|
|
801c6b2: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
|
|
/* Is this pbuf already empty? */
|
|
if (!newpbuflen) {
|
|
801c6b6: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
|
|
801c6ba: 2b00 cmp r3, #0
|
|
801c6bc: d105 bne.n 801c6ca <ip4_frag+0x132>
|
|
poff = 0;
|
|
801c6be: 2300 movs r3, #0
|
|
801c6c0: 87fb strh r3, [r7, #62] ; 0x3e
|
|
p = p->next;
|
|
801c6c2: 68fb ldr r3, [r7, #12]
|
|
801c6c4: 681b ldr r3, [r3, #0]
|
|
801c6c6: 60fb str r3, [r7, #12]
|
|
continue;
|
|
801c6c8: e041 b.n 801c74e <ip4_frag+0x1b6>
|
|
}
|
|
pcr = ip_frag_alloc_pbuf_custom_ref();
|
|
801c6ca: f7ff ff0d bl 801c4e8 <ip_frag_alloc_pbuf_custom_ref>
|
|
801c6ce: 61b8 str r0, [r7, #24]
|
|
if (pcr == NULL) {
|
|
801c6d0: 69bb ldr r3, [r7, #24]
|
|
801c6d2: 2b00 cmp r3, #0
|
|
801c6d4: d103 bne.n 801c6de <ip4_frag+0x146>
|
|
pbuf_free(rambuf);
|
|
801c6d6: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
801c6d8: f7f5 fdbe bl 8012258 <pbuf_free>
|
|
goto memerr;
|
|
801c6dc: e08e b.n 801c7fc <ip4_frag+0x264>
|
|
}
|
|
/* Mirror this pbuf, although we might not need all of it. */
|
|
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
|
|
801c6de: 69b8 ldr r0, [r7, #24]
|
|
(u8_t *)p->payload + poff, newpbuflen);
|
|
801c6e0: 68fb ldr r3, [r7, #12]
|
|
801c6e2: 685a ldr r2, [r3, #4]
|
|
newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc,
|
|
801c6e4: 8ffb ldrh r3, [r7, #62] ; 0x3e
|
|
801c6e6: 4413 add r3, r2
|
|
801c6e8: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46
|
|
801c6ec: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
|
|
801c6f0: 9201 str r2, [sp, #4]
|
|
801c6f2: 9300 str r3, [sp, #0]
|
|
801c6f4: 4603 mov r3, r0
|
|
801c6f6: 2241 movs r2, #65 ; 0x41
|
|
801c6f8: 2000 movs r0, #0
|
|
801c6fa: f7f5 fbf3 bl 8011ee4 <pbuf_alloced_custom>
|
|
801c6fe: 6178 str r0, [r7, #20]
|
|
if (newpbuf == NULL) {
|
|
801c700: 697b ldr r3, [r7, #20]
|
|
801c702: 2b00 cmp r3, #0
|
|
801c704: d106 bne.n 801c714 <ip4_frag+0x17c>
|
|
ip_frag_free_pbuf_custom_ref(pcr);
|
|
801c706: 69b8 ldr r0, [r7, #24]
|
|
801c708: f7ff fef6 bl 801c4f8 <ip_frag_free_pbuf_custom_ref>
|
|
pbuf_free(rambuf);
|
|
801c70c: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
801c70e: f7f5 fda3 bl 8012258 <pbuf_free>
|
|
goto memerr;
|
|
801c712: e073 b.n 801c7fc <ip4_frag+0x264>
|
|
}
|
|
pbuf_ref(p);
|
|
801c714: 68f8 ldr r0, [r7, #12]
|
|
801c716: f7f5 fe45 bl 80123a4 <pbuf_ref>
|
|
pcr->original = p;
|
|
801c71a: 69bb ldr r3, [r7, #24]
|
|
801c71c: 68fa ldr r2, [r7, #12]
|
|
801c71e: 615a str r2, [r3, #20]
|
|
pcr->pc.custom_free_function = ipfrag_free_pbuf_custom;
|
|
801c720: 69bb ldr r3, [r7, #24]
|
|
801c722: 4a3e ldr r2, [pc, #248] ; (801c81c <ip4_frag+0x284>)
|
|
801c724: 611a str r2, [r3, #16]
|
|
|
|
/* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain
|
|
* so that it is removed when pbuf_dechain is later called on rambuf.
|
|
*/
|
|
pbuf_cat(rambuf, newpbuf);
|
|
801c726: 6979 ldr r1, [r7, #20]
|
|
801c728: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
801c72a: f7f5 fe63 bl 80123f4 <pbuf_cat>
|
|
left_to_copy = (u16_t)(left_to_copy - newpbuflen);
|
|
801c72e: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44
|
|
801c732: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
|
|
801c736: 1ad3 subs r3, r2, r3
|
|
801c738: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
|
|
if (left_to_copy) {
|
|
801c73c: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
|
|
801c740: 2b00 cmp r3, #0
|
|
801c742: d004 beq.n 801c74e <ip4_frag+0x1b6>
|
|
poff = 0;
|
|
801c744: 2300 movs r3, #0
|
|
801c746: 87fb strh r3, [r7, #62] ; 0x3e
|
|
p = p->next;
|
|
801c748: 68fb ldr r3, [r7, #12]
|
|
801c74a: 681b ldr r3, [r3, #0]
|
|
801c74c: 60fb str r3, [r7, #12]
|
|
while (left_to_copy) {
|
|
801c74e: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
|
|
801c752: 2b00 cmp r3, #0
|
|
801c754: d196 bne.n 801c684 <ip4_frag+0xec>
|
|
}
|
|
}
|
|
poff = (u16_t)(poff + newpbuflen);
|
|
801c756: 8ffa ldrh r2, [r7, #62] ; 0x3e
|
|
801c758: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46
|
|
801c75c: 4413 add r3, r2
|
|
801c75e: 87fb strh r3, [r7, #62] ; 0x3e
|
|
#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
|
|
|
|
/* Correct header */
|
|
last = (left <= netif->mtu - IP_HLEN);
|
|
801c760: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
801c764: 68bb ldr r3, [r7, #8]
|
|
801c766: 8d1b ldrh r3, [r3, #40] ; 0x28
|
|
801c768: 3b14 subs r3, #20
|
|
801c76a: 429a cmp r2, r3
|
|
801c76c: bfd4 ite le
|
|
801c76e: 2301 movle r3, #1
|
|
801c770: 2300 movgt r3, #0
|
|
801c772: b2db uxtb r3, r3
|
|
801c774: 623b str r3, [r7, #32]
|
|
|
|
/* Set new offset and MF flag */
|
|
tmp = (IP_OFFMASK & (ofo));
|
|
801c776: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40
|
|
801c77a: f3c3 030c ubfx r3, r3, #0, #13
|
|
801c77e: 87bb strh r3, [r7, #60] ; 0x3c
|
|
if (!last || mf_set) {
|
|
801c780: 6a3b ldr r3, [r7, #32]
|
|
801c782: 2b00 cmp r3, #0
|
|
801c784: d002 beq.n 801c78c <ip4_frag+0x1f4>
|
|
801c786: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801c788: 2b00 cmp r3, #0
|
|
801c78a: d003 beq.n 801c794 <ip4_frag+0x1fc>
|
|
/* the last fragment has MF set if the input frame had it */
|
|
tmp = tmp | IP_MF;
|
|
801c78c: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
801c78e: f443 5300 orr.w r3, r3, #8192 ; 0x2000
|
|
801c792: 87bb strh r3, [r7, #60] ; 0x3c
|
|
}
|
|
IPH_OFFSET_SET(iphdr, lwip_htons(tmp));
|
|
801c794: 8fbb ldrh r3, [r7, #60] ; 0x3c
|
|
801c796: 4618 mov r0, r3
|
|
801c798: f7f4 f9aa bl 8010af0 <lwip_htons>
|
|
801c79c: 4603 mov r3, r0
|
|
801c79e: 461a mov r2, r3
|
|
801c7a0: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c7a2: 80da strh r2, [r3, #6]
|
|
IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN)));
|
|
801c7a4: 8d7b ldrh r3, [r7, #42] ; 0x2a
|
|
801c7a6: 3314 adds r3, #20
|
|
801c7a8: b29b uxth r3, r3
|
|
801c7aa: 4618 mov r0, r3
|
|
801c7ac: f7f4 f9a0 bl 8010af0 <lwip_htons>
|
|
801c7b0: 4603 mov r3, r0
|
|
801c7b2: 461a mov r2, r3
|
|
801c7b4: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c7b6: 805a strh r2, [r3, #2]
|
|
IPH_CHKSUM_SET(iphdr, 0);
|
|
801c7b8: 6b3b ldr r3, [r7, #48] ; 0x30
|
|
801c7ba: 2200 movs r2, #0
|
|
801c7bc: 729a strb r2, [r3, #10]
|
|
801c7be: 2200 movs r2, #0
|
|
801c7c0: 72da strb r2, [r3, #11]
|
|
#endif /* CHECKSUM_GEN_IP */
|
|
|
|
/* No need for separate header pbuf - we allowed room for it in rambuf
|
|
* when allocated.
|
|
*/
|
|
netif->output(netif, rambuf, dest);
|
|
801c7c2: 68bb ldr r3, [r7, #8]
|
|
801c7c4: 695b ldr r3, [r3, #20]
|
|
801c7c6: 687a ldr r2, [r7, #4]
|
|
801c7c8: 6a79 ldr r1, [r7, #36] ; 0x24
|
|
801c7ca: 68b8 ldr r0, [r7, #8]
|
|
801c7cc: 4798 blx r3
|
|
* recreate it next time round the loop. If we're lucky the hardware
|
|
* will have already sent the packet, the free will really free, and
|
|
* there will be zero memory penalty.
|
|
*/
|
|
|
|
pbuf_free(rambuf);
|
|
801c7ce: 6a78 ldr r0, [r7, #36] ; 0x24
|
|
801c7d0: f7f5 fd42 bl 8012258 <pbuf_free>
|
|
left = (u16_t)(left - fragsize);
|
|
801c7d4: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42
|
|
801c7d8: 8d7b ldrh r3, [r7, #42] ; 0x2a
|
|
801c7da: 1ad3 subs r3, r2, r3
|
|
801c7dc: f8a7 3042 strh.w r3, [r7, #66] ; 0x42
|
|
ofo = (u16_t)(ofo + nfb);
|
|
801c7e0: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40
|
|
801c7e4: 8f7b ldrh r3, [r7, #58] ; 0x3a
|
|
801c7e6: 4413 add r3, r2
|
|
801c7e8: f8a7 3040 strh.w r3, [r7, #64] ; 0x40
|
|
while (left) {
|
|
801c7ec: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42
|
|
801c7f0: 2b00 cmp r3, #0
|
|
801c7f2: f47f af1a bne.w 801c62a <ip4_frag+0x92>
|
|
}
|
|
MIB2_STATS_INC(mib2.ipfragoks);
|
|
return ERR_OK;
|
|
801c7f6: 2300 movs r3, #0
|
|
801c7f8: e002 b.n 801c800 <ip4_frag+0x268>
|
|
goto memerr;
|
|
801c7fa: bf00 nop
|
|
memerr:
|
|
MIB2_STATS_INC(mib2.ipfragfails);
|
|
return ERR_MEM;
|
|
801c7fc: f04f 33ff mov.w r3, #4294967295
|
|
}
|
|
801c800: 4618 mov r0, r3
|
|
801c802: 3748 adds r7, #72 ; 0x48
|
|
801c804: 46bd mov sp, r7
|
|
801c806: bd80 pop {r7, pc}
|
|
801c808: 08020b40 .word 0x08020b40
|
|
801c80c: 08020d1c .word 0x08020d1c
|
|
801c810: 08020b88 .word 0x08020b88
|
|
801c814: 08020d38 .word 0x08020d38
|
|
801c818: 08020d58 .word 0x08020d58
|
|
801c81c: 0801c531 .word 0x0801c531
|
|
|
|
0801c820 <ethernet_input>:
|
|
* @see ETHARP_SUPPORT_VLAN
|
|
* @see LWIP_HOOK_VLAN_CHECK
|
|
*/
|
|
err_t
|
|
ethernet_input(struct pbuf *p, struct netif *netif)
|
|
{
|
|
801c820: b580 push {r7, lr}
|
|
801c822: b086 sub sp, #24
|
|
801c824: af00 add r7, sp, #0
|
|
801c826: 6078 str r0, [r7, #4]
|
|
801c828: 6039 str r1, [r7, #0]
|
|
struct eth_hdr *ethhdr;
|
|
u16_t type;
|
|
#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6
|
|
u16_t next_hdr_offset = SIZEOF_ETH_HDR;
|
|
801c82a: 230e movs r3, #14
|
|
801c82c: 82fb strh r3, [r7, #22]
|
|
#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
if (p->len <= SIZEOF_ETH_HDR) {
|
|
801c82e: 687b ldr r3, [r7, #4]
|
|
801c830: 895b ldrh r3, [r3, #10]
|
|
801c832: 2b0e cmp r3, #14
|
|
801c834: d96e bls.n 801c914 <ethernet_input+0xf4>
|
|
ETHARP_STATS_INC(etharp.drop);
|
|
MIB2_STATS_NETIF_INC(netif, ifinerrors);
|
|
goto free_and_return;
|
|
}
|
|
|
|
if (p->if_idx == NETIF_NO_INDEX) {
|
|
801c836: 687b ldr r3, [r7, #4]
|
|
801c838: 7bdb ldrb r3, [r3, #15]
|
|
801c83a: 2b00 cmp r3, #0
|
|
801c83c: d106 bne.n 801c84c <ethernet_input+0x2c>
|
|
p->if_idx = netif_get_index(netif);
|
|
801c83e: 683b ldr r3, [r7, #0]
|
|
801c840: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
|
|
801c844: 3301 adds r3, #1
|
|
801c846: b2da uxtb r2, r3
|
|
801c848: 687b ldr r3, [r7, #4]
|
|
801c84a: 73da strb r2, [r3, #15]
|
|
}
|
|
|
|
/* points to packet payload, which starts with an Ethernet header */
|
|
ethhdr = (struct eth_hdr *)p->payload;
|
|
801c84c: 687b ldr r3, [r7, #4]
|
|
801c84e: 685b ldr r3, [r3, #4]
|
|
801c850: 613b str r3, [r7, #16]
|
|
(unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5],
|
|
(unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2],
|
|
(unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5],
|
|
lwip_htons(ethhdr->type)));
|
|
|
|
type = ethhdr->type;
|
|
801c852: 693b ldr r3, [r7, #16]
|
|
801c854: 7b1a ldrb r2, [r3, #12]
|
|
801c856: 7b5b ldrb r3, [r3, #13]
|
|
801c858: 021b lsls r3, r3, #8
|
|
801c85a: 4313 orrs r3, r2
|
|
801c85c: 81fb strh r3, [r7, #14]
|
|
|
|
#if LWIP_ARP_FILTER_NETIF
|
|
netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type));
|
|
#endif /* LWIP_ARP_FILTER_NETIF*/
|
|
|
|
if (ethhdr->dest.addr[0] & 1) {
|
|
801c85e: 693b ldr r3, [r7, #16]
|
|
801c860: 781b ldrb r3, [r3, #0]
|
|
801c862: f003 0301 and.w r3, r3, #1
|
|
801c866: 2b00 cmp r3, #0
|
|
801c868: d023 beq.n 801c8b2 <ethernet_input+0x92>
|
|
/* this might be a multicast or broadcast packet */
|
|
if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) {
|
|
801c86a: 693b ldr r3, [r7, #16]
|
|
801c86c: 781b ldrb r3, [r3, #0]
|
|
801c86e: 2b01 cmp r3, #1
|
|
801c870: d10f bne.n 801c892 <ethernet_input+0x72>
|
|
#if LWIP_IPV4
|
|
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
|
|
801c872: 693b ldr r3, [r7, #16]
|
|
801c874: 785b ldrb r3, [r3, #1]
|
|
801c876: 2b00 cmp r3, #0
|
|
801c878: d11b bne.n 801c8b2 <ethernet_input+0x92>
|
|
(ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) {
|
|
801c87a: 693b ldr r3, [r7, #16]
|
|
801c87c: 789b ldrb r3, [r3, #2]
|
|
if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) &&
|
|
801c87e: 2b5e cmp r3, #94 ; 0x5e
|
|
801c880: d117 bne.n 801c8b2 <ethernet_input+0x92>
|
|
/* mark the pbuf as link-layer multicast */
|
|
p->flags |= PBUF_FLAG_LLMCAST;
|
|
801c882: 687b ldr r3, [r7, #4]
|
|
801c884: 7b5b ldrb r3, [r3, #13]
|
|
801c886: f043 0310 orr.w r3, r3, #16
|
|
801c88a: b2da uxtb r2, r3
|
|
801c88c: 687b ldr r3, [r7, #4]
|
|
801c88e: 735a strb r2, [r3, #13]
|
|
801c890: e00f b.n 801c8b2 <ethernet_input+0x92>
|
|
(ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) {
|
|
/* mark the pbuf as link-layer multicast */
|
|
p->flags |= PBUF_FLAG_LLMCAST;
|
|
}
|
|
#endif /* LWIP_IPV6 */
|
|
else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) {
|
|
801c892: 693b ldr r3, [r7, #16]
|
|
801c894: 2206 movs r2, #6
|
|
801c896: 4928 ldr r1, [pc, #160] ; (801c938 <ethernet_input+0x118>)
|
|
801c898: 4618 mov r0, r3
|
|
801c89a: f000 f9d1 bl 801cc40 <memcmp>
|
|
801c89e: 4603 mov r3, r0
|
|
801c8a0: 2b00 cmp r3, #0
|
|
801c8a2: d106 bne.n 801c8b2 <ethernet_input+0x92>
|
|
/* mark the pbuf as link-layer broadcast */
|
|
p->flags |= PBUF_FLAG_LLBCAST;
|
|
801c8a4: 687b ldr r3, [r7, #4]
|
|
801c8a6: 7b5b ldrb r3, [r3, #13]
|
|
801c8a8: f043 0308 orr.w r3, r3, #8
|
|
801c8ac: b2da uxtb r2, r3
|
|
801c8ae: 687b ldr r3, [r7, #4]
|
|
801c8b0: 735a strb r2, [r3, #13]
|
|
}
|
|
}
|
|
|
|
switch (type) {
|
|
801c8b2: 89fb ldrh r3, [r7, #14]
|
|
801c8b4: 2b08 cmp r3, #8
|
|
801c8b6: d003 beq.n 801c8c0 <ethernet_input+0xa0>
|
|
801c8b8: f5b3 6fc1 cmp.w r3, #1544 ; 0x608
|
|
801c8bc: d014 beq.n 801c8e8 <ethernet_input+0xc8>
|
|
}
|
|
#endif
|
|
ETHARP_STATS_INC(etharp.proterr);
|
|
ETHARP_STATS_INC(etharp.drop);
|
|
MIB2_STATS_NETIF_INC(netif, ifinunknownprotos);
|
|
goto free_and_return;
|
|
801c8be: e032 b.n 801c926 <ethernet_input+0x106>
|
|
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
|
|
801c8c0: 683b ldr r3, [r7, #0]
|
|
801c8c2: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801c8c6: f003 0308 and.w r3, r3, #8
|
|
801c8ca: 2b00 cmp r3, #0
|
|
801c8cc: d024 beq.n 801c918 <ethernet_input+0xf8>
|
|
if (pbuf_remove_header(p, next_hdr_offset)) {
|
|
801c8ce: 8afb ldrh r3, [r7, #22]
|
|
801c8d0: 4619 mov r1, r3
|
|
801c8d2: 6878 ldr r0, [r7, #4]
|
|
801c8d4: f7f5 fc3a bl 801214c <pbuf_remove_header>
|
|
801c8d8: 4603 mov r3, r0
|
|
801c8da: 2b00 cmp r3, #0
|
|
801c8dc: d11e bne.n 801c91c <ethernet_input+0xfc>
|
|
ip4_input(p, netif);
|
|
801c8de: 6839 ldr r1, [r7, #0]
|
|
801c8e0: 6878 ldr r0, [r7, #4]
|
|
801c8e2: f7fe ff0f bl 801b704 <ip4_input>
|
|
break;
|
|
801c8e6: e013 b.n 801c910 <ethernet_input+0xf0>
|
|
if (!(netif->flags & NETIF_FLAG_ETHARP)) {
|
|
801c8e8: 683b ldr r3, [r7, #0]
|
|
801c8ea: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
|
|
801c8ee: f003 0308 and.w r3, r3, #8
|
|
801c8f2: 2b00 cmp r3, #0
|
|
801c8f4: d014 beq.n 801c920 <ethernet_input+0x100>
|
|
if (pbuf_remove_header(p, next_hdr_offset)) {
|
|
801c8f6: 8afb ldrh r3, [r7, #22]
|
|
801c8f8: 4619 mov r1, r3
|
|
801c8fa: 6878 ldr r0, [r7, #4]
|
|
801c8fc: f7f5 fc26 bl 801214c <pbuf_remove_header>
|
|
801c900: 4603 mov r3, r0
|
|
801c902: 2b00 cmp r3, #0
|
|
801c904: d10e bne.n 801c924 <ethernet_input+0x104>
|
|
etharp_input(p, netif);
|
|
801c906: 6839 ldr r1, [r7, #0]
|
|
801c908: 6878 ldr r0, [r7, #4]
|
|
801c90a: f7fe f8ab bl 801aa64 <etharp_input>
|
|
break;
|
|
801c90e: bf00 nop
|
|
}
|
|
|
|
/* This means the pbuf is freed or consumed,
|
|
so the caller doesn't have to free it again */
|
|
return ERR_OK;
|
|
801c910: 2300 movs r3, #0
|
|
801c912: e00c b.n 801c92e <ethernet_input+0x10e>
|
|
goto free_and_return;
|
|
801c914: bf00 nop
|
|
801c916: e006 b.n 801c926 <ethernet_input+0x106>
|
|
goto free_and_return;
|
|
801c918: bf00 nop
|
|
801c91a: e004 b.n 801c926 <ethernet_input+0x106>
|
|
goto free_and_return;
|
|
801c91c: bf00 nop
|
|
801c91e: e002 b.n 801c926 <ethernet_input+0x106>
|
|
goto free_and_return;
|
|
801c920: bf00 nop
|
|
801c922: e000 b.n 801c926 <ethernet_input+0x106>
|
|
goto free_and_return;
|
|
801c924: bf00 nop
|
|
|
|
free_and_return:
|
|
pbuf_free(p);
|
|
801c926: 6878 ldr r0, [r7, #4]
|
|
801c928: f7f5 fc96 bl 8012258 <pbuf_free>
|
|
return ERR_OK;
|
|
801c92c: 2300 movs r3, #0
|
|
}
|
|
801c92e: 4618 mov r0, r3
|
|
801c930: 3718 adds r7, #24
|
|
801c932: 46bd mov sp, r7
|
|
801c934: bd80 pop {r7, pc}
|
|
801c936: bf00 nop
|
|
801c938: 08022e70 .word 0x08022e70
|
|
|
|
0801c93c <ethernet_output>:
|
|
* @return ERR_OK if the packet was sent, any other err_t on failure
|
|
*/
|
|
err_t
|
|
ethernet_output(struct netif * netif, struct pbuf * p,
|
|
const struct eth_addr * src, const struct eth_addr * dst,
|
|
u16_t eth_type) {
|
|
801c93c: b580 push {r7, lr}
|
|
801c93e: b086 sub sp, #24
|
|
801c940: af00 add r7, sp, #0
|
|
801c942: 60f8 str r0, [r7, #12]
|
|
801c944: 60b9 str r1, [r7, #8]
|
|
801c946: 607a str r2, [r7, #4]
|
|
801c948: 603b str r3, [r7, #0]
|
|
struct eth_hdr *ethhdr;
|
|
u16_t eth_type_be = lwip_htons(eth_type);
|
|
801c94a: 8c3b ldrh r3, [r7, #32]
|
|
801c94c: 4618 mov r0, r3
|
|
801c94e: f7f4 f8cf bl 8010af0 <lwip_htons>
|
|
801c952: 4603 mov r3, r0
|
|
801c954: 82fb strh r3, [r7, #22]
|
|
|
|
eth_type_be = PP_HTONS(ETHTYPE_VLAN);
|
|
} else
|
|
#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */
|
|
{
|
|
if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) {
|
|
801c956: 210e movs r1, #14
|
|
801c958: 68b8 ldr r0, [r7, #8]
|
|
801c95a: f7f5 fbe7 bl 801212c <pbuf_add_header>
|
|
801c95e: 4603 mov r3, r0
|
|
801c960: 2b00 cmp r3, #0
|
|
801c962: d125 bne.n 801c9b0 <ethernet_output+0x74>
|
|
}
|
|
}
|
|
|
|
LWIP_ASSERT_CORE_LOCKED();
|
|
|
|
ethhdr = (struct eth_hdr *)p->payload;
|
|
801c964: 68bb ldr r3, [r7, #8]
|
|
801c966: 685b ldr r3, [r3, #4]
|
|
801c968: 613b str r3, [r7, #16]
|
|
ethhdr->type = eth_type_be;
|
|
801c96a: 693b ldr r3, [r7, #16]
|
|
801c96c: 8afa ldrh r2, [r7, #22]
|
|
801c96e: 819a strh r2, [r3, #12]
|
|
SMEMCPY(ðhdr->dest, dst, ETH_HWADDR_LEN);
|
|
801c970: 693b ldr r3, [r7, #16]
|
|
801c972: 2206 movs r2, #6
|
|
801c974: 6839 ldr r1, [r7, #0]
|
|
801c976: 4618 mov r0, r3
|
|
801c978: f000 f971 bl 801cc5e <memcpy>
|
|
SMEMCPY(ðhdr->src, src, ETH_HWADDR_LEN);
|
|
801c97c: 693b ldr r3, [r7, #16]
|
|
801c97e: 3306 adds r3, #6
|
|
801c980: 2206 movs r2, #6
|
|
801c982: 6879 ldr r1, [r7, #4]
|
|
801c984: 4618 mov r0, r3
|
|
801c986: f000 f96a bl 801cc5e <memcpy>
|
|
|
|
LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!",
|
|
801c98a: 68fb ldr r3, [r7, #12]
|
|
801c98c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
|
|
801c990: 2b06 cmp r3, #6
|
|
801c992: d006 beq.n 801c9a2 <ethernet_output+0x66>
|
|
801c994: 4b0a ldr r3, [pc, #40] ; (801c9c0 <ethernet_output+0x84>)
|
|
801c996: f240 1233 movw r2, #307 ; 0x133
|
|
801c99a: 490a ldr r1, [pc, #40] ; (801c9c4 <ethernet_output+0x88>)
|
|
801c99c: 480a ldr r0, [pc, #40] ; (801c9c8 <ethernet_output+0x8c>)
|
|
801c99e: f000 f98b bl 801ccb8 <iprintf>
|
|
(netif->hwaddr_len == ETH_HWADDR_LEN));
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE,
|
|
("ethernet_output: sending packet %p\n", (void *)p));
|
|
|
|
/* send the packet */
|
|
return netif->linkoutput(netif, p);
|
|
801c9a2: 68fb ldr r3, [r7, #12]
|
|
801c9a4: 699b ldr r3, [r3, #24]
|
|
801c9a6: 68b9 ldr r1, [r7, #8]
|
|
801c9a8: 68f8 ldr r0, [r7, #12]
|
|
801c9aa: 4798 blx r3
|
|
801c9ac: 4603 mov r3, r0
|
|
801c9ae: e002 b.n 801c9b6 <ethernet_output+0x7a>
|
|
goto pbuf_header_failed;
|
|
801c9b0: bf00 nop
|
|
|
|
pbuf_header_failed:
|
|
LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS,
|
|
("ethernet_output: could not allocate room for header.\n"));
|
|
LINK_STATS_INC(link.lenerr);
|
|
return ERR_BUF;
|
|
801c9b2: f06f 0301 mvn.w r3, #1
|
|
}
|
|
801c9b6: 4618 mov r0, r3
|
|
801c9b8: 3718 adds r7, #24
|
|
801c9ba: 46bd mov sp, r7
|
|
801c9bc: bd80 pop {r7, pc}
|
|
801c9be: bf00 nop
|
|
801c9c0: 08020d68 .word 0x08020d68
|
|
801c9c4: 08020da0 .word 0x08020da0
|
|
801c9c8: 08020dd4 .word 0x08020dd4
|
|
|
|
0801c9cc <sys_mbox_new>:
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------------------*/
|
|
// Creates an empty mailbox.
|
|
err_t sys_mbox_new(sys_mbox_t *mbox, int size)
|
|
{
|
|
801c9cc: b580 push {r7, lr}
|
|
801c9ce: b086 sub sp, #24
|
|
801c9d0: af00 add r7, sp, #0
|
|
801c9d2: 6078 str r0, [r7, #4]
|
|
801c9d4: 6039 str r1, [r7, #0]
|
|
#if (osCMSIS < 0x20000U)
|
|
osMessageQDef(QUEUE, size, void *);
|
|
801c9d6: 683b ldr r3, [r7, #0]
|
|
801c9d8: 60bb str r3, [r7, #8]
|
|
801c9da: 2304 movs r3, #4
|
|
801c9dc: 60fb str r3, [r7, #12]
|
|
801c9de: 2300 movs r3, #0
|
|
801c9e0: 613b str r3, [r7, #16]
|
|
801c9e2: 2300 movs r3, #0
|
|
801c9e4: 617b str r3, [r7, #20]
|
|
*mbox = osMessageCreate(osMessageQ(QUEUE), NULL);
|
|
801c9e6: f107 0308 add.w r3, r7, #8
|
|
801c9ea: 2100 movs r1, #0
|
|
801c9ec: 4618 mov r0, r3
|
|
801c9ee: f7f0 fff7 bl 800d9e0 <osMessageCreate>
|
|
801c9f2: 4602 mov r2, r0
|
|
801c9f4: 687b ldr r3, [r7, #4]
|
|
801c9f6: 601a str r2, [r3, #0]
|
|
if(lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used)
|
|
{
|
|
lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used;
|
|
}
|
|
#endif /* SYS_STATS */
|
|
if(*mbox == NULL)
|
|
801c9f8: 687b ldr r3, [r7, #4]
|
|
801c9fa: 681b ldr r3, [r3, #0]
|
|
801c9fc: 2b00 cmp r3, #0
|
|
801c9fe: d102 bne.n 801ca06 <sys_mbox_new+0x3a>
|
|
return ERR_MEM;
|
|
801ca00: f04f 33ff mov.w r3, #4294967295
|
|
801ca04: e000 b.n 801ca08 <sys_mbox_new+0x3c>
|
|
|
|
return ERR_OK;
|
|
801ca06: 2300 movs r3, #0
|
|
}
|
|
801ca08: 4618 mov r0, r3
|
|
801ca0a: 3718 adds r7, #24
|
|
801ca0c: 46bd mov sp, r7
|
|
801ca0e: bd80 pop {r7, pc}
|
|
|
|
0801ca10 <sys_mbox_trypost>:
|
|
|
|
|
|
/*-----------------------------------------------------------------------------------*/
|
|
// Try to post the "msg" to the mailbox.
|
|
err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg)
|
|
{
|
|
801ca10: b580 push {r7, lr}
|
|
801ca12: b084 sub sp, #16
|
|
801ca14: af00 add r7, sp, #0
|
|
801ca16: 6078 str r0, [r7, #4]
|
|
801ca18: 6039 str r1, [r7, #0]
|
|
err_t result;
|
|
#if (osCMSIS < 0x20000U)
|
|
if(osMessagePut(*mbox, (uint32_t)msg, 0) == osOK)
|
|
801ca1a: 687b ldr r3, [r7, #4]
|
|
801ca1c: 681b ldr r3, [r3, #0]
|
|
801ca1e: 6839 ldr r1, [r7, #0]
|
|
801ca20: 2200 movs r2, #0
|
|
801ca22: 4618 mov r0, r3
|
|
801ca24: f7f1 f806 bl 800da34 <osMessagePut>
|
|
801ca28: 4603 mov r3, r0
|
|
801ca2a: 2b00 cmp r3, #0
|
|
801ca2c: d102 bne.n 801ca34 <sys_mbox_trypost+0x24>
|
|
#else
|
|
if(osMessageQueuePut(*mbox, &msg, 0, 0) == osOK)
|
|
#endif
|
|
{
|
|
result = ERR_OK;
|
|
801ca2e: 2300 movs r3, #0
|
|
801ca30: 73fb strb r3, [r7, #15]
|
|
801ca32: e001 b.n 801ca38 <sys_mbox_trypost+0x28>
|
|
}
|
|
else
|
|
{
|
|
// could not post, queue must be full
|
|
result = ERR_MEM;
|
|
801ca34: 23ff movs r3, #255 ; 0xff
|
|
801ca36: 73fb strb r3, [r7, #15]
|
|
#if SYS_STATS
|
|
lwip_stats.sys.mbox.err++;
|
|
#endif /* SYS_STATS */
|
|
}
|
|
|
|
return result;
|
|
801ca38: f997 300f ldrsb.w r3, [r7, #15]
|
|
}
|
|
801ca3c: 4618 mov r0, r3
|
|
801ca3e: 3710 adds r7, #16
|
|
801ca40: 46bd mov sp, r7
|
|
801ca42: bd80 pop {r7, pc}
|
|
|
|
0801ca44 <sys_arch_mbox_fetch>:
|
|
|
|
Note that a function with a similar name, sys_mbox_fetch(), is
|
|
implemented by lwIP.
|
|
*/
|
|
u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout)
|
|
{
|
|
801ca44: b580 push {r7, lr}
|
|
801ca46: b08c sub sp, #48 ; 0x30
|
|
801ca48: af00 add r7, sp, #0
|
|
801ca4a: 61f8 str r0, [r7, #28]
|
|
801ca4c: 61b9 str r1, [r7, #24]
|
|
801ca4e: 617a str r2, [r7, #20]
|
|
#if (osCMSIS < 0x20000U)
|
|
osEvent event;
|
|
uint32_t starttime = osKernelSysTick();
|
|
801ca50: f7f0 fdf5 bl 800d63e <osKernelSysTick>
|
|
801ca54: 62f8 str r0, [r7, #44] ; 0x2c
|
|
#else
|
|
osStatus_t status;
|
|
uint32_t starttime = osKernelGetTickCount();
|
|
#endif
|
|
if(timeout != 0)
|
|
801ca56: 697b ldr r3, [r7, #20]
|
|
801ca58: 2b00 cmp r3, #0
|
|
801ca5a: d017 beq.n 801ca8c <sys_arch_mbox_fetch+0x48>
|
|
{
|
|
#if (osCMSIS < 0x20000U)
|
|
event = osMessageGet (*mbox, timeout);
|
|
801ca5c: 69fb ldr r3, [r7, #28]
|
|
801ca5e: 6819 ldr r1, [r3, #0]
|
|
801ca60: f107 0320 add.w r3, r7, #32
|
|
801ca64: 697a ldr r2, [r7, #20]
|
|
801ca66: 4618 mov r0, r3
|
|
801ca68: f7f1 f824 bl 800dab4 <osMessageGet>
|
|
|
|
if(event.status == osEventMessage)
|
|
801ca6c: 6a3b ldr r3, [r7, #32]
|
|
801ca6e: 2b10 cmp r3, #16
|
|
801ca70: d109 bne.n 801ca86 <sys_arch_mbox_fetch+0x42>
|
|
{
|
|
*msg = (void *)event.value.v;
|
|
801ca72: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801ca74: 461a mov r2, r3
|
|
801ca76: 69bb ldr r3, [r7, #24]
|
|
801ca78: 601a str r2, [r3, #0]
|
|
return (osKernelSysTick() - starttime);
|
|
801ca7a: f7f0 fde0 bl 800d63e <osKernelSysTick>
|
|
801ca7e: 4602 mov r2, r0
|
|
801ca80: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801ca82: 1ad3 subs r3, r2, r3
|
|
801ca84: e019 b.n 801caba <sys_arch_mbox_fetch+0x76>
|
|
return (osKernelGetTickCount() - starttime);
|
|
}
|
|
#endif
|
|
else
|
|
{
|
|
return SYS_ARCH_TIMEOUT;
|
|
801ca86: f04f 33ff mov.w r3, #4294967295
|
|
801ca8a: e016 b.n 801caba <sys_arch_mbox_fetch+0x76>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
#if (osCMSIS < 0x20000U)
|
|
event = osMessageGet (*mbox, osWaitForever);
|
|
801ca8c: 69fb ldr r3, [r7, #28]
|
|
801ca8e: 6819 ldr r1, [r3, #0]
|
|
801ca90: 463b mov r3, r7
|
|
801ca92: f04f 32ff mov.w r2, #4294967295
|
|
801ca96: 4618 mov r0, r3
|
|
801ca98: f7f1 f80c bl 800dab4 <osMessageGet>
|
|
801ca9c: f107 0320 add.w r3, r7, #32
|
|
801caa0: 463a mov r2, r7
|
|
801caa2: ca07 ldmia r2, {r0, r1, r2}
|
|
801caa4: e883 0007 stmia.w r3, {r0, r1, r2}
|
|
*msg = (void *)event.value.v;
|
|
801caa8: 6a7b ldr r3, [r7, #36] ; 0x24
|
|
801caaa: 461a mov r2, r3
|
|
801caac: 69bb ldr r3, [r7, #24]
|
|
801caae: 601a str r2, [r3, #0]
|
|
return (osKernelSysTick() - starttime);
|
|
801cab0: f7f0 fdc5 bl 800d63e <osKernelSysTick>
|
|
801cab4: 4602 mov r2, r0
|
|
801cab6: 6afb ldr r3, [r7, #44] ; 0x2c
|
|
801cab8: 1ad3 subs r3, r2, r3
|
|
#else
|
|
osMessageQueueGet(*mbox, msg, 0, osWaitForever );
|
|
return (osKernelGetTickCount() - starttime);
|
|
#endif
|
|
}
|
|
}
|
|
801caba: 4618 mov r0, r3
|
|
801cabc: 3730 adds r7, #48 ; 0x30
|
|
801cabe: 46bd mov sp, r7
|
|
801cac0: bd80 pop {r7, pc}
|
|
|
|
0801cac2 <sys_mbox_valid>:
|
|
return SYS_MBOX_EMPTY;
|
|
}
|
|
}
|
|
/*----------------------------------------------------------------------------------*/
|
|
int sys_mbox_valid(sys_mbox_t *mbox)
|
|
{
|
|
801cac2: b480 push {r7}
|
|
801cac4: b083 sub sp, #12
|
|
801cac6: af00 add r7, sp, #0
|
|
801cac8: 6078 str r0, [r7, #4]
|
|
if (*mbox == SYS_MBOX_NULL)
|
|
801caca: 687b ldr r3, [r7, #4]
|
|
801cacc: 681b ldr r3, [r3, #0]
|
|
801cace: 2b00 cmp r3, #0
|
|
801cad0: d101 bne.n 801cad6 <sys_mbox_valid+0x14>
|
|
return 0;
|
|
801cad2: 2300 movs r3, #0
|
|
801cad4: e000 b.n 801cad8 <sys_mbox_valid+0x16>
|
|
else
|
|
return 1;
|
|
801cad6: 2301 movs r3, #1
|
|
}
|
|
801cad8: 4618 mov r0, r3
|
|
801cada: 370c adds r7, #12
|
|
801cadc: 46bd mov sp, r7
|
|
801cade: f85d 7b04 ldr.w r7, [sp], #4
|
|
801cae2: 4770 bx lr
|
|
|
|
0801cae4 <sys_init>:
|
|
#else
|
|
osMutexId_t lwip_sys_mutex;
|
|
#endif
|
|
// Initialize sys arch
|
|
void sys_init(void)
|
|
{
|
|
801cae4: b580 push {r7, lr}
|
|
801cae6: af00 add r7, sp, #0
|
|
#if (osCMSIS < 0x20000U)
|
|
lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex));
|
|
801cae8: 4803 ldr r0, [pc, #12] ; (801caf8 <sys_init+0x14>)
|
|
801caea: f7f0 fe18 bl 800d71e <osMutexCreate>
|
|
801caee: 4602 mov r2, r0
|
|
801caf0: 4b02 ldr r3, [pc, #8] ; (801cafc <sys_init+0x18>)
|
|
801caf2: 601a str r2, [r3, #0]
|
|
#else
|
|
lwip_sys_mutex = osMutexNew(NULL);
|
|
#endif
|
|
}
|
|
801caf4: bf00 nop
|
|
801caf6: bd80 pop {r7, pc}
|
|
801caf8: 08022e80 .word 0x08022e80
|
|
801cafc: 2000f844 .word 0x2000f844
|
|
|
|
0801cb00 <sys_mutex_new>:
|
|
/* Mutexes*/
|
|
/*-----------------------------------------------------------------------------------*/
|
|
/*-----------------------------------------------------------------------------------*/
|
|
#if LWIP_COMPAT_MUTEX == 0
|
|
/* Create a new mutex*/
|
|
err_t sys_mutex_new(sys_mutex_t *mutex) {
|
|
801cb00: b580 push {r7, lr}
|
|
801cb02: b084 sub sp, #16
|
|
801cb04: af00 add r7, sp, #0
|
|
801cb06: 6078 str r0, [r7, #4]
|
|
|
|
#if (osCMSIS < 0x20000U)
|
|
osMutexDef(MUTEX);
|
|
801cb08: 2300 movs r3, #0
|
|
801cb0a: 60bb str r3, [r7, #8]
|
|
801cb0c: 2300 movs r3, #0
|
|
801cb0e: 60fb str r3, [r7, #12]
|
|
*mutex = osMutexCreate(osMutex(MUTEX));
|
|
801cb10: f107 0308 add.w r3, r7, #8
|
|
801cb14: 4618 mov r0, r3
|
|
801cb16: f7f0 fe02 bl 800d71e <osMutexCreate>
|
|
801cb1a: 4602 mov r2, r0
|
|
801cb1c: 687b ldr r3, [r7, #4]
|
|
801cb1e: 601a str r2, [r3, #0]
|
|
#else
|
|
*mutex = osMutexNew(NULL);
|
|
#endif
|
|
|
|
if(*mutex == NULL)
|
|
801cb20: 687b ldr r3, [r7, #4]
|
|
801cb22: 681b ldr r3, [r3, #0]
|
|
801cb24: 2b00 cmp r3, #0
|
|
801cb26: d102 bne.n 801cb2e <sys_mutex_new+0x2e>
|
|
{
|
|
#if SYS_STATS
|
|
++lwip_stats.sys.mutex.err;
|
|
#endif /* SYS_STATS */
|
|
return ERR_MEM;
|
|
801cb28: f04f 33ff mov.w r3, #4294967295
|
|
801cb2c: e000 b.n 801cb30 <sys_mutex_new+0x30>
|
|
++lwip_stats.sys.mutex.used;
|
|
if (lwip_stats.sys.mutex.max < lwip_stats.sys.mutex.used) {
|
|
lwip_stats.sys.mutex.max = lwip_stats.sys.mutex.used;
|
|
}
|
|
#endif /* SYS_STATS */
|
|
return ERR_OK;
|
|
801cb2e: 2300 movs r3, #0
|
|
}
|
|
801cb30: 4618 mov r0, r3
|
|
801cb32: 3710 adds r7, #16
|
|
801cb34: 46bd mov sp, r7
|
|
801cb36: bd80 pop {r7, pc}
|
|
|
|
0801cb38 <sys_mutex_lock>:
|
|
osMutexDelete(*mutex);
|
|
}
|
|
/*-----------------------------------------------------------------------------------*/
|
|
/* Lock a mutex*/
|
|
void sys_mutex_lock(sys_mutex_t *mutex)
|
|
{
|
|
801cb38: b580 push {r7, lr}
|
|
801cb3a: b082 sub sp, #8
|
|
801cb3c: af00 add r7, sp, #0
|
|
801cb3e: 6078 str r0, [r7, #4]
|
|
#if (osCMSIS < 0x20000U)
|
|
osMutexWait(*mutex, osWaitForever);
|
|
801cb40: 687b ldr r3, [r7, #4]
|
|
801cb42: 681b ldr r3, [r3, #0]
|
|
801cb44: f04f 31ff mov.w r1, #4294967295
|
|
801cb48: 4618 mov r0, r3
|
|
801cb4a: f7f0 fe01 bl 800d750 <osMutexWait>
|
|
#else
|
|
osMutexAcquire(*mutex, osWaitForever);
|
|
#endif
|
|
}
|
|
801cb4e: bf00 nop
|
|
801cb50: 3708 adds r7, #8
|
|
801cb52: 46bd mov sp, r7
|
|
801cb54: bd80 pop {r7, pc}
|
|
|
|
0801cb56 <sys_mutex_unlock>:
|
|
|
|
/*-----------------------------------------------------------------------------------*/
|
|
/* Unlock a mutex*/
|
|
void sys_mutex_unlock(sys_mutex_t *mutex)
|
|
{
|
|
801cb56: b580 push {r7, lr}
|
|
801cb58: b082 sub sp, #8
|
|
801cb5a: af00 add r7, sp, #0
|
|
801cb5c: 6078 str r0, [r7, #4]
|
|
osMutexRelease(*mutex);
|
|
801cb5e: 687b ldr r3, [r7, #4]
|
|
801cb60: 681b ldr r3, [r3, #0]
|
|
801cb62: 4618 mov r0, r3
|
|
801cb64: f7f0 fe42 bl 800d7ec <osMutexRelease>
|
|
}
|
|
801cb68: bf00 nop
|
|
801cb6a: 3708 adds r7, #8
|
|
801cb6c: 46bd mov sp, r7
|
|
801cb6e: bd80 pop {r7, pc}
|
|
|
|
0801cb70 <sys_thread_new>:
|
|
function "thread()". The "arg" argument will be passed as an argument to the
|
|
thread() function. The id of the new thread is returned. Both the id and
|
|
the priority are system dependent.
|
|
*/
|
|
sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread , void *arg, int stacksize, int prio)
|
|
{
|
|
801cb70: b580 push {r7, lr}
|
|
801cb72: b08c sub sp, #48 ; 0x30
|
|
801cb74: af00 add r7, sp, #0
|
|
801cb76: 60f8 str r0, [r7, #12]
|
|
801cb78: 60b9 str r1, [r7, #8]
|
|
801cb7a: 607a str r2, [r7, #4]
|
|
801cb7c: 603b str r3, [r7, #0]
|
|
#if (osCMSIS < 0x20000U)
|
|
const osThreadDef_t os_thread_def = { (char *)name, (os_pthread)thread, (osPriority)prio, 0, stacksize};
|
|
801cb7e: f107 0314 add.w r3, r7, #20
|
|
801cb82: 2200 movs r2, #0
|
|
801cb84: 601a str r2, [r3, #0]
|
|
801cb86: 605a str r2, [r3, #4]
|
|
801cb88: 609a str r2, [r3, #8]
|
|
801cb8a: 60da str r2, [r3, #12]
|
|
801cb8c: 611a str r2, [r3, #16]
|
|
801cb8e: 615a str r2, [r3, #20]
|
|
801cb90: 619a str r2, [r3, #24]
|
|
801cb92: 68fb ldr r3, [r7, #12]
|
|
801cb94: 617b str r3, [r7, #20]
|
|
801cb96: 68bb ldr r3, [r7, #8]
|
|
801cb98: 61bb str r3, [r7, #24]
|
|
801cb9a: 6bbb ldr r3, [r7, #56] ; 0x38
|
|
801cb9c: b21b sxth r3, r3
|
|
801cb9e: 83bb strh r3, [r7, #28]
|
|
801cba0: 683b ldr r3, [r7, #0]
|
|
801cba2: 627b str r3, [r7, #36] ; 0x24
|
|
return osThreadCreate(&os_thread_def, arg);
|
|
801cba4: f107 0314 add.w r3, r7, #20
|
|
801cba8: 6879 ldr r1, [r7, #4]
|
|
801cbaa: 4618 mov r0, r3
|
|
801cbac: f7f0 fd57 bl 800d65e <osThreadCreate>
|
|
801cbb0: 4603 mov r3, r0
|
|
.stack_size = stacksize,
|
|
.priority = (osPriority_t)prio,
|
|
};
|
|
return osThreadNew(thread, arg, &attributes);
|
|
#endif
|
|
}
|
|
801cbb2: 4618 mov r0, r3
|
|
801cbb4: 3730 adds r7, #48 ; 0x30
|
|
801cbb6: 46bd mov sp, r7
|
|
801cbb8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0801cbbc <sys_arch_protect>:
|
|
|
|
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
|
|
API is available
|
|
*/
|
|
sys_prot_t sys_arch_protect(void)
|
|
{
|
|
801cbbc: b580 push {r7, lr}
|
|
801cbbe: af00 add r7, sp, #0
|
|
#if (osCMSIS < 0x20000U)
|
|
osMutexWait(lwip_sys_mutex, osWaitForever);
|
|
801cbc0: 4b04 ldr r3, [pc, #16] ; (801cbd4 <sys_arch_protect+0x18>)
|
|
801cbc2: 681b ldr r3, [r3, #0]
|
|
801cbc4: f04f 31ff mov.w r1, #4294967295
|
|
801cbc8: 4618 mov r0, r3
|
|
801cbca: f7f0 fdc1 bl 800d750 <osMutexWait>
|
|
#else
|
|
osMutexAcquire(lwip_sys_mutex, osWaitForever);
|
|
#endif
|
|
return (sys_prot_t)1;
|
|
801cbce: 2301 movs r3, #1
|
|
}
|
|
801cbd0: 4618 mov r0, r3
|
|
801cbd2: bd80 pop {r7, pc}
|
|
801cbd4: 2000f844 .word 0x2000f844
|
|
|
|
0801cbd8 <sys_arch_unprotect>:
|
|
|
|
Note: This function is based on FreeRTOS API, because no equivalent CMSIS-RTOS
|
|
API is available
|
|
*/
|
|
void sys_arch_unprotect(sys_prot_t pval)
|
|
{
|
|
801cbd8: b580 push {r7, lr}
|
|
801cbda: b082 sub sp, #8
|
|
801cbdc: af00 add r7, sp, #0
|
|
801cbde: 6078 str r0, [r7, #4]
|
|
( void ) pval;
|
|
osMutexRelease(lwip_sys_mutex);
|
|
801cbe0: 4b04 ldr r3, [pc, #16] ; (801cbf4 <sys_arch_unprotect+0x1c>)
|
|
801cbe2: 681b ldr r3, [r3, #0]
|
|
801cbe4: 4618 mov r0, r3
|
|
801cbe6: f7f0 fe01 bl 800d7ec <osMutexRelease>
|
|
}
|
|
801cbea: bf00 nop
|
|
801cbec: 3708 adds r7, #8
|
|
801cbee: 46bd mov sp, r7
|
|
801cbf0: bd80 pop {r7, pc}
|
|
801cbf2: bf00 nop
|
|
801cbf4: 2000f844 .word 0x2000f844
|
|
|
|
0801cbf8 <__libc_init_array>:
|
|
801cbf8: b570 push {r4, r5, r6, lr}
|
|
801cbfa: 4e0d ldr r6, [pc, #52] ; (801cc30 <__libc_init_array+0x38>)
|
|
801cbfc: 4c0d ldr r4, [pc, #52] ; (801cc34 <__libc_init_array+0x3c>)
|
|
801cbfe: 1ba4 subs r4, r4, r6
|
|
801cc00: 10a4 asrs r4, r4, #2
|
|
801cc02: 2500 movs r5, #0
|
|
801cc04: 42a5 cmp r5, r4
|
|
801cc06: d109 bne.n 801cc1c <__libc_init_array+0x24>
|
|
801cc08: 4e0b ldr r6, [pc, #44] ; (801cc38 <__libc_init_array+0x40>)
|
|
801cc0a: 4c0c ldr r4, [pc, #48] ; (801cc3c <__libc_init_array+0x44>)
|
|
801cc0c: f001 f914 bl 801de38 <_init>
|
|
801cc10: 1ba4 subs r4, r4, r6
|
|
801cc12: 10a4 asrs r4, r4, #2
|
|
801cc14: 2500 movs r5, #0
|
|
801cc16: 42a5 cmp r5, r4
|
|
801cc18: d105 bne.n 801cc26 <__libc_init_array+0x2e>
|
|
801cc1a: bd70 pop {r4, r5, r6, pc}
|
|
801cc1c: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
801cc20: 4798 blx r3
|
|
801cc22: 3501 adds r5, #1
|
|
801cc24: e7ee b.n 801cc04 <__libc_init_array+0xc>
|
|
801cc26: f856 3025 ldr.w r3, [r6, r5, lsl #2]
|
|
801cc2a: 4798 blx r3
|
|
801cc2c: 3501 adds r5, #1
|
|
801cc2e: e7f2 b.n 801cc16 <__libc_init_array+0x1e>
|
|
801cc30: 08022f28 .word 0x08022f28
|
|
801cc34: 08022f28 .word 0x08022f28
|
|
801cc38: 08022f28 .word 0x08022f28
|
|
801cc3c: 08022f2c .word 0x08022f2c
|
|
|
|
0801cc40 <memcmp>:
|
|
801cc40: b530 push {r4, r5, lr}
|
|
801cc42: 2400 movs r4, #0
|
|
801cc44: 42a2 cmp r2, r4
|
|
801cc46: d101 bne.n 801cc4c <memcmp+0xc>
|
|
801cc48: 2000 movs r0, #0
|
|
801cc4a: e007 b.n 801cc5c <memcmp+0x1c>
|
|
801cc4c: 5d03 ldrb r3, [r0, r4]
|
|
801cc4e: 3401 adds r4, #1
|
|
801cc50: 190d adds r5, r1, r4
|
|
801cc52: f815 5c01 ldrb.w r5, [r5, #-1]
|
|
801cc56: 42ab cmp r3, r5
|
|
801cc58: d0f4 beq.n 801cc44 <memcmp+0x4>
|
|
801cc5a: 1b58 subs r0, r3, r5
|
|
801cc5c: bd30 pop {r4, r5, pc}
|
|
|
|
0801cc5e <memcpy>:
|
|
801cc5e: b510 push {r4, lr}
|
|
801cc60: 1e43 subs r3, r0, #1
|
|
801cc62: 440a add r2, r1
|
|
801cc64: 4291 cmp r1, r2
|
|
801cc66: d100 bne.n 801cc6a <memcpy+0xc>
|
|
801cc68: bd10 pop {r4, pc}
|
|
801cc6a: f811 4b01 ldrb.w r4, [r1], #1
|
|
801cc6e: f803 4f01 strb.w r4, [r3, #1]!
|
|
801cc72: e7f7 b.n 801cc64 <memcpy+0x6>
|
|
|
|
0801cc74 <memmove>:
|
|
801cc74: 4288 cmp r0, r1
|
|
801cc76: b510 push {r4, lr}
|
|
801cc78: eb01 0302 add.w r3, r1, r2
|
|
801cc7c: d807 bhi.n 801cc8e <memmove+0x1a>
|
|
801cc7e: 1e42 subs r2, r0, #1
|
|
801cc80: 4299 cmp r1, r3
|
|
801cc82: d00a beq.n 801cc9a <memmove+0x26>
|
|
801cc84: f811 4b01 ldrb.w r4, [r1], #1
|
|
801cc88: f802 4f01 strb.w r4, [r2, #1]!
|
|
801cc8c: e7f8 b.n 801cc80 <memmove+0xc>
|
|
801cc8e: 4283 cmp r3, r0
|
|
801cc90: d9f5 bls.n 801cc7e <memmove+0xa>
|
|
801cc92: 1881 adds r1, r0, r2
|
|
801cc94: 1ad2 subs r2, r2, r3
|
|
801cc96: 42d3 cmn r3, r2
|
|
801cc98: d100 bne.n 801cc9c <memmove+0x28>
|
|
801cc9a: bd10 pop {r4, pc}
|
|
801cc9c: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
801cca0: f801 4d01 strb.w r4, [r1, #-1]!
|
|
801cca4: e7f7 b.n 801cc96 <memmove+0x22>
|
|
|
|
0801cca6 <memset>:
|
|
801cca6: 4402 add r2, r0
|
|
801cca8: 4603 mov r3, r0
|
|
801ccaa: 4293 cmp r3, r2
|
|
801ccac: d100 bne.n 801ccb0 <memset+0xa>
|
|
801ccae: 4770 bx lr
|
|
801ccb0: f803 1b01 strb.w r1, [r3], #1
|
|
801ccb4: e7f9 b.n 801ccaa <memset+0x4>
|
|
...
|
|
|
|
0801ccb8 <iprintf>:
|
|
801ccb8: b40f push {r0, r1, r2, r3}
|
|
801ccba: 4b0a ldr r3, [pc, #40] ; (801cce4 <iprintf+0x2c>)
|
|
801ccbc: b513 push {r0, r1, r4, lr}
|
|
801ccbe: 681c ldr r4, [r3, #0]
|
|
801ccc0: b124 cbz r4, 801cccc <iprintf+0x14>
|
|
801ccc2: 69a3 ldr r3, [r4, #24]
|
|
801ccc4: b913 cbnz r3, 801cccc <iprintf+0x14>
|
|
801ccc6: 4620 mov r0, r4
|
|
801ccc8: f000 f8a2 bl 801ce10 <__sinit>
|
|
801cccc: ab05 add r3, sp, #20
|
|
801ccce: 9a04 ldr r2, [sp, #16]
|
|
801ccd0: 68a1 ldr r1, [r4, #8]
|
|
801ccd2: 9301 str r3, [sp, #4]
|
|
801ccd4: 4620 mov r0, r4
|
|
801ccd6: f000 fb51 bl 801d37c <_vfiprintf_r>
|
|
801ccda: b002 add sp, #8
|
|
801ccdc: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
801cce0: b004 add sp, #16
|
|
801cce2: 4770 bx lr
|
|
801cce4: 20000084 .word 0x20000084
|
|
|
|
0801cce8 <rand>:
|
|
801cce8: b538 push {r3, r4, r5, lr}
|
|
801ccea: 4b13 ldr r3, [pc, #76] ; (801cd38 <rand+0x50>)
|
|
801ccec: 681c ldr r4, [r3, #0]
|
|
801ccee: 6ba3 ldr r3, [r4, #56] ; 0x38
|
|
801ccf0: b97b cbnz r3, 801cd12 <rand+0x2a>
|
|
801ccf2: 2018 movs r0, #24
|
|
801ccf4: f000 f916 bl 801cf24 <malloc>
|
|
801ccf8: 4a10 ldr r2, [pc, #64] ; (801cd3c <rand+0x54>)
|
|
801ccfa: 4b11 ldr r3, [pc, #68] ; (801cd40 <rand+0x58>)
|
|
801ccfc: 63a0 str r0, [r4, #56] ; 0x38
|
|
801ccfe: e9c0 2300 strd r2, r3, [r0]
|
|
801cd02: 4b10 ldr r3, [pc, #64] ; (801cd44 <rand+0x5c>)
|
|
801cd04: 6083 str r3, [r0, #8]
|
|
801cd06: 230b movs r3, #11
|
|
801cd08: 8183 strh r3, [r0, #12]
|
|
801cd0a: 2201 movs r2, #1
|
|
801cd0c: 2300 movs r3, #0
|
|
801cd0e: e9c0 2304 strd r2, r3, [r0, #16]
|
|
801cd12: 6ba1 ldr r1, [r4, #56] ; 0x38
|
|
801cd14: 480c ldr r0, [pc, #48] ; (801cd48 <rand+0x60>)
|
|
801cd16: 690a ldr r2, [r1, #16]
|
|
801cd18: 694b ldr r3, [r1, #20]
|
|
801cd1a: 4c0c ldr r4, [pc, #48] ; (801cd4c <rand+0x64>)
|
|
801cd1c: 4350 muls r0, r2
|
|
801cd1e: fb04 0003 mla r0, r4, r3, r0
|
|
801cd22: fba2 2304 umull r2, r3, r2, r4
|
|
801cd26: 4403 add r3, r0
|
|
801cd28: 1c54 adds r4, r2, #1
|
|
801cd2a: f143 0500 adc.w r5, r3, #0
|
|
801cd2e: e9c1 4504 strd r4, r5, [r1, #16]
|
|
801cd32: f025 4000 bic.w r0, r5, #2147483648 ; 0x80000000
|
|
801cd36: bd38 pop {r3, r4, r5, pc}
|
|
801cd38: 20000084 .word 0x20000084
|
|
801cd3c: abcd330e .word 0xabcd330e
|
|
801cd40: e66d1234 .word 0xe66d1234
|
|
801cd44: 0005deec .word 0x0005deec
|
|
801cd48: 5851f42d .word 0x5851f42d
|
|
801cd4c: 4c957f2d .word 0x4c957f2d
|
|
|
|
0801cd50 <siprintf>:
|
|
801cd50: b40e push {r1, r2, r3}
|
|
801cd52: b500 push {lr}
|
|
801cd54: b09c sub sp, #112 ; 0x70
|
|
801cd56: ab1d add r3, sp, #116 ; 0x74
|
|
801cd58: 9002 str r0, [sp, #8]
|
|
801cd5a: 9006 str r0, [sp, #24]
|
|
801cd5c: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
|
|
801cd60: 4809 ldr r0, [pc, #36] ; (801cd88 <siprintf+0x38>)
|
|
801cd62: 9107 str r1, [sp, #28]
|
|
801cd64: 9104 str r1, [sp, #16]
|
|
801cd66: 4909 ldr r1, [pc, #36] ; (801cd8c <siprintf+0x3c>)
|
|
801cd68: f853 2b04 ldr.w r2, [r3], #4
|
|
801cd6c: 9105 str r1, [sp, #20]
|
|
801cd6e: 6800 ldr r0, [r0, #0]
|
|
801cd70: 9301 str r3, [sp, #4]
|
|
801cd72: a902 add r1, sp, #8
|
|
801cd74: f000 f9e0 bl 801d138 <_svfiprintf_r>
|
|
801cd78: 9b02 ldr r3, [sp, #8]
|
|
801cd7a: 2200 movs r2, #0
|
|
801cd7c: 701a strb r2, [r3, #0]
|
|
801cd7e: b01c add sp, #112 ; 0x70
|
|
801cd80: f85d eb04 ldr.w lr, [sp], #4
|
|
801cd84: b003 add sp, #12
|
|
801cd86: 4770 bx lr
|
|
801cd88: 20000084 .word 0x20000084
|
|
801cd8c: ffff0208 .word 0xffff0208
|
|
|
|
0801cd90 <std>:
|
|
801cd90: 2300 movs r3, #0
|
|
801cd92: b510 push {r4, lr}
|
|
801cd94: 4604 mov r4, r0
|
|
801cd96: e9c0 3300 strd r3, r3, [r0]
|
|
801cd9a: 6083 str r3, [r0, #8]
|
|
801cd9c: 8181 strh r1, [r0, #12]
|
|
801cd9e: 6643 str r3, [r0, #100] ; 0x64
|
|
801cda0: 81c2 strh r2, [r0, #14]
|
|
801cda2: e9c0 3304 strd r3, r3, [r0, #16]
|
|
801cda6: 6183 str r3, [r0, #24]
|
|
801cda8: 4619 mov r1, r3
|
|
801cdaa: 2208 movs r2, #8
|
|
801cdac: 305c adds r0, #92 ; 0x5c
|
|
801cdae: f7ff ff7a bl 801cca6 <memset>
|
|
801cdb2: 4b05 ldr r3, [pc, #20] ; (801cdc8 <std+0x38>)
|
|
801cdb4: 6263 str r3, [r4, #36] ; 0x24
|
|
801cdb6: 4b05 ldr r3, [pc, #20] ; (801cdcc <std+0x3c>)
|
|
801cdb8: 62a3 str r3, [r4, #40] ; 0x28
|
|
801cdba: 4b05 ldr r3, [pc, #20] ; (801cdd0 <std+0x40>)
|
|
801cdbc: 62e3 str r3, [r4, #44] ; 0x2c
|
|
801cdbe: 4b05 ldr r3, [pc, #20] ; (801cdd4 <std+0x44>)
|
|
801cdc0: 6224 str r4, [r4, #32]
|
|
801cdc2: 6323 str r3, [r4, #48] ; 0x30
|
|
801cdc4: bd10 pop {r4, pc}
|
|
801cdc6: bf00 nop
|
|
801cdc8: 0801d8d9 .word 0x0801d8d9
|
|
801cdcc: 0801d8fb .word 0x0801d8fb
|
|
801cdd0: 0801d933 .word 0x0801d933
|
|
801cdd4: 0801d957 .word 0x0801d957
|
|
|
|
0801cdd8 <_cleanup_r>:
|
|
801cdd8: 4901 ldr r1, [pc, #4] ; (801cde0 <_cleanup_r+0x8>)
|
|
801cdda: f000 b885 b.w 801cee8 <_fwalk_reent>
|
|
801cdde: bf00 nop
|
|
801cde0: 0801dc31 .word 0x0801dc31
|
|
|
|
0801cde4 <__sfmoreglue>:
|
|
801cde4: b570 push {r4, r5, r6, lr}
|
|
801cde6: 1e4a subs r2, r1, #1
|
|
801cde8: 2568 movs r5, #104 ; 0x68
|
|
801cdea: 4355 muls r5, r2
|
|
801cdec: 460e mov r6, r1
|
|
801cdee: f105 0174 add.w r1, r5, #116 ; 0x74
|
|
801cdf2: f000 f8ed bl 801cfd0 <_malloc_r>
|
|
801cdf6: 4604 mov r4, r0
|
|
801cdf8: b140 cbz r0, 801ce0c <__sfmoreglue+0x28>
|
|
801cdfa: 2100 movs r1, #0
|
|
801cdfc: e9c0 1600 strd r1, r6, [r0]
|
|
801ce00: 300c adds r0, #12
|
|
801ce02: 60a0 str r0, [r4, #8]
|
|
801ce04: f105 0268 add.w r2, r5, #104 ; 0x68
|
|
801ce08: f7ff ff4d bl 801cca6 <memset>
|
|
801ce0c: 4620 mov r0, r4
|
|
801ce0e: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0801ce10 <__sinit>:
|
|
801ce10: 6983 ldr r3, [r0, #24]
|
|
801ce12: b510 push {r4, lr}
|
|
801ce14: 4604 mov r4, r0
|
|
801ce16: bb33 cbnz r3, 801ce66 <__sinit+0x56>
|
|
801ce18: e9c0 3312 strd r3, r3, [r0, #72] ; 0x48
|
|
801ce1c: 6503 str r3, [r0, #80] ; 0x50
|
|
801ce1e: 4b12 ldr r3, [pc, #72] ; (801ce68 <__sinit+0x58>)
|
|
801ce20: 4a12 ldr r2, [pc, #72] ; (801ce6c <__sinit+0x5c>)
|
|
801ce22: 681b ldr r3, [r3, #0]
|
|
801ce24: 6282 str r2, [r0, #40] ; 0x28
|
|
801ce26: 4298 cmp r0, r3
|
|
801ce28: bf04 itt eq
|
|
801ce2a: 2301 moveq r3, #1
|
|
801ce2c: 6183 streq r3, [r0, #24]
|
|
801ce2e: f000 f81f bl 801ce70 <__sfp>
|
|
801ce32: 6060 str r0, [r4, #4]
|
|
801ce34: 4620 mov r0, r4
|
|
801ce36: f000 f81b bl 801ce70 <__sfp>
|
|
801ce3a: 60a0 str r0, [r4, #8]
|
|
801ce3c: 4620 mov r0, r4
|
|
801ce3e: f000 f817 bl 801ce70 <__sfp>
|
|
801ce42: 2200 movs r2, #0
|
|
801ce44: 60e0 str r0, [r4, #12]
|
|
801ce46: 2104 movs r1, #4
|
|
801ce48: 6860 ldr r0, [r4, #4]
|
|
801ce4a: f7ff ffa1 bl 801cd90 <std>
|
|
801ce4e: 2201 movs r2, #1
|
|
801ce50: 2109 movs r1, #9
|
|
801ce52: 68a0 ldr r0, [r4, #8]
|
|
801ce54: f7ff ff9c bl 801cd90 <std>
|
|
801ce58: 2202 movs r2, #2
|
|
801ce5a: 2112 movs r1, #18
|
|
801ce5c: 68e0 ldr r0, [r4, #12]
|
|
801ce5e: f7ff ff97 bl 801cd90 <std>
|
|
801ce62: 2301 movs r3, #1
|
|
801ce64: 61a3 str r3, [r4, #24]
|
|
801ce66: bd10 pop {r4, pc}
|
|
801ce68: 08022e88 .word 0x08022e88
|
|
801ce6c: 0801cdd9 .word 0x0801cdd9
|
|
|
|
0801ce70 <__sfp>:
|
|
801ce70: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801ce72: 4b1b ldr r3, [pc, #108] ; (801cee0 <__sfp+0x70>)
|
|
801ce74: 681e ldr r6, [r3, #0]
|
|
801ce76: 69b3 ldr r3, [r6, #24]
|
|
801ce78: 4607 mov r7, r0
|
|
801ce7a: b913 cbnz r3, 801ce82 <__sfp+0x12>
|
|
801ce7c: 4630 mov r0, r6
|
|
801ce7e: f7ff ffc7 bl 801ce10 <__sinit>
|
|
801ce82: 3648 adds r6, #72 ; 0x48
|
|
801ce84: e9d6 3401 ldrd r3, r4, [r6, #4]
|
|
801ce88: 3b01 subs r3, #1
|
|
801ce8a: d503 bpl.n 801ce94 <__sfp+0x24>
|
|
801ce8c: 6833 ldr r3, [r6, #0]
|
|
801ce8e: b133 cbz r3, 801ce9e <__sfp+0x2e>
|
|
801ce90: 6836 ldr r6, [r6, #0]
|
|
801ce92: e7f7 b.n 801ce84 <__sfp+0x14>
|
|
801ce94: f9b4 500c ldrsh.w r5, [r4, #12]
|
|
801ce98: b16d cbz r5, 801ceb6 <__sfp+0x46>
|
|
801ce9a: 3468 adds r4, #104 ; 0x68
|
|
801ce9c: e7f4 b.n 801ce88 <__sfp+0x18>
|
|
801ce9e: 2104 movs r1, #4
|
|
801cea0: 4638 mov r0, r7
|
|
801cea2: f7ff ff9f bl 801cde4 <__sfmoreglue>
|
|
801cea6: 6030 str r0, [r6, #0]
|
|
801cea8: 2800 cmp r0, #0
|
|
801ceaa: d1f1 bne.n 801ce90 <__sfp+0x20>
|
|
801ceac: 230c movs r3, #12
|
|
801ceae: 603b str r3, [r7, #0]
|
|
801ceb0: 4604 mov r4, r0
|
|
801ceb2: 4620 mov r0, r4
|
|
801ceb4: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
801ceb6: 4b0b ldr r3, [pc, #44] ; (801cee4 <__sfp+0x74>)
|
|
801ceb8: 6665 str r5, [r4, #100] ; 0x64
|
|
801ceba: e9c4 5500 strd r5, r5, [r4]
|
|
801cebe: 60a5 str r5, [r4, #8]
|
|
801cec0: e9c4 3503 strd r3, r5, [r4, #12]
|
|
801cec4: e9c4 5505 strd r5, r5, [r4, #20]
|
|
801cec8: 2208 movs r2, #8
|
|
801ceca: 4629 mov r1, r5
|
|
801cecc: f104 005c add.w r0, r4, #92 ; 0x5c
|
|
801ced0: f7ff fee9 bl 801cca6 <memset>
|
|
801ced4: e9c4 550d strd r5, r5, [r4, #52] ; 0x34
|
|
801ced8: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48
|
|
801cedc: e7e9 b.n 801ceb2 <__sfp+0x42>
|
|
801cede: bf00 nop
|
|
801cee0: 08022e88 .word 0x08022e88
|
|
801cee4: ffff0001 .word 0xffff0001
|
|
|
|
0801cee8 <_fwalk_reent>:
|
|
801cee8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
801ceec: 4680 mov r8, r0
|
|
801ceee: 4689 mov r9, r1
|
|
801cef0: f100 0448 add.w r4, r0, #72 ; 0x48
|
|
801cef4: 2600 movs r6, #0
|
|
801cef6: b914 cbnz r4, 801cefe <_fwalk_reent+0x16>
|
|
801cef8: 4630 mov r0, r6
|
|
801cefa: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
801cefe: e9d4 7501 ldrd r7, r5, [r4, #4]
|
|
801cf02: 3f01 subs r7, #1
|
|
801cf04: d501 bpl.n 801cf0a <_fwalk_reent+0x22>
|
|
801cf06: 6824 ldr r4, [r4, #0]
|
|
801cf08: e7f5 b.n 801cef6 <_fwalk_reent+0xe>
|
|
801cf0a: 89ab ldrh r3, [r5, #12]
|
|
801cf0c: 2b01 cmp r3, #1
|
|
801cf0e: d907 bls.n 801cf20 <_fwalk_reent+0x38>
|
|
801cf10: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
801cf14: 3301 adds r3, #1
|
|
801cf16: d003 beq.n 801cf20 <_fwalk_reent+0x38>
|
|
801cf18: 4629 mov r1, r5
|
|
801cf1a: 4640 mov r0, r8
|
|
801cf1c: 47c8 blx r9
|
|
801cf1e: 4306 orrs r6, r0
|
|
801cf20: 3568 adds r5, #104 ; 0x68
|
|
801cf22: e7ee b.n 801cf02 <_fwalk_reent+0x1a>
|
|
|
|
0801cf24 <malloc>:
|
|
801cf24: 4b02 ldr r3, [pc, #8] ; (801cf30 <malloc+0xc>)
|
|
801cf26: 4601 mov r1, r0
|
|
801cf28: 6818 ldr r0, [r3, #0]
|
|
801cf2a: f000 b851 b.w 801cfd0 <_malloc_r>
|
|
801cf2e: bf00 nop
|
|
801cf30: 20000084 .word 0x20000084
|
|
|
|
0801cf34 <_free_r>:
|
|
801cf34: b538 push {r3, r4, r5, lr}
|
|
801cf36: 4605 mov r5, r0
|
|
801cf38: 2900 cmp r1, #0
|
|
801cf3a: d045 beq.n 801cfc8 <_free_r+0x94>
|
|
801cf3c: f851 3c04 ldr.w r3, [r1, #-4]
|
|
801cf40: 1f0c subs r4, r1, #4
|
|
801cf42: 2b00 cmp r3, #0
|
|
801cf44: bfb8 it lt
|
|
801cf46: 18e4 addlt r4, r4, r3
|
|
801cf48: f000 ff12 bl 801dd70 <__malloc_lock>
|
|
801cf4c: 4a1f ldr r2, [pc, #124] ; (801cfcc <_free_r+0x98>)
|
|
801cf4e: 6813 ldr r3, [r2, #0]
|
|
801cf50: 4610 mov r0, r2
|
|
801cf52: b933 cbnz r3, 801cf62 <_free_r+0x2e>
|
|
801cf54: 6063 str r3, [r4, #4]
|
|
801cf56: 6014 str r4, [r2, #0]
|
|
801cf58: 4628 mov r0, r5
|
|
801cf5a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
801cf5e: f000 bf08 b.w 801dd72 <__malloc_unlock>
|
|
801cf62: 42a3 cmp r3, r4
|
|
801cf64: d90c bls.n 801cf80 <_free_r+0x4c>
|
|
801cf66: 6821 ldr r1, [r4, #0]
|
|
801cf68: 1862 adds r2, r4, r1
|
|
801cf6a: 4293 cmp r3, r2
|
|
801cf6c: bf04 itt eq
|
|
801cf6e: 681a ldreq r2, [r3, #0]
|
|
801cf70: 685b ldreq r3, [r3, #4]
|
|
801cf72: 6063 str r3, [r4, #4]
|
|
801cf74: bf04 itt eq
|
|
801cf76: 1852 addeq r2, r2, r1
|
|
801cf78: 6022 streq r2, [r4, #0]
|
|
801cf7a: 6004 str r4, [r0, #0]
|
|
801cf7c: e7ec b.n 801cf58 <_free_r+0x24>
|
|
801cf7e: 4613 mov r3, r2
|
|
801cf80: 685a ldr r2, [r3, #4]
|
|
801cf82: b10a cbz r2, 801cf88 <_free_r+0x54>
|
|
801cf84: 42a2 cmp r2, r4
|
|
801cf86: d9fa bls.n 801cf7e <_free_r+0x4a>
|
|
801cf88: 6819 ldr r1, [r3, #0]
|
|
801cf8a: 1858 adds r0, r3, r1
|
|
801cf8c: 42a0 cmp r0, r4
|
|
801cf8e: d10b bne.n 801cfa8 <_free_r+0x74>
|
|
801cf90: 6820 ldr r0, [r4, #0]
|
|
801cf92: 4401 add r1, r0
|
|
801cf94: 1858 adds r0, r3, r1
|
|
801cf96: 4282 cmp r2, r0
|
|
801cf98: 6019 str r1, [r3, #0]
|
|
801cf9a: d1dd bne.n 801cf58 <_free_r+0x24>
|
|
801cf9c: 6810 ldr r0, [r2, #0]
|
|
801cf9e: 6852 ldr r2, [r2, #4]
|
|
801cfa0: 605a str r2, [r3, #4]
|
|
801cfa2: 4401 add r1, r0
|
|
801cfa4: 6019 str r1, [r3, #0]
|
|
801cfa6: e7d7 b.n 801cf58 <_free_r+0x24>
|
|
801cfa8: d902 bls.n 801cfb0 <_free_r+0x7c>
|
|
801cfaa: 230c movs r3, #12
|
|
801cfac: 602b str r3, [r5, #0]
|
|
801cfae: e7d3 b.n 801cf58 <_free_r+0x24>
|
|
801cfb0: 6820 ldr r0, [r4, #0]
|
|
801cfb2: 1821 adds r1, r4, r0
|
|
801cfb4: 428a cmp r2, r1
|
|
801cfb6: bf04 itt eq
|
|
801cfb8: 6811 ldreq r1, [r2, #0]
|
|
801cfba: 6852 ldreq r2, [r2, #4]
|
|
801cfbc: 6062 str r2, [r4, #4]
|
|
801cfbe: bf04 itt eq
|
|
801cfc0: 1809 addeq r1, r1, r0
|
|
801cfc2: 6021 streq r1, [r4, #0]
|
|
801cfc4: 605c str r4, [r3, #4]
|
|
801cfc6: e7c7 b.n 801cf58 <_free_r+0x24>
|
|
801cfc8: bd38 pop {r3, r4, r5, pc}
|
|
801cfca: bf00 nop
|
|
801cfcc: 20008874 .word 0x20008874
|
|
|
|
0801cfd0 <_malloc_r>:
|
|
801cfd0: b570 push {r4, r5, r6, lr}
|
|
801cfd2: 1ccd adds r5, r1, #3
|
|
801cfd4: f025 0503 bic.w r5, r5, #3
|
|
801cfd8: 3508 adds r5, #8
|
|
801cfda: 2d0c cmp r5, #12
|
|
801cfdc: bf38 it cc
|
|
801cfde: 250c movcc r5, #12
|
|
801cfe0: 2d00 cmp r5, #0
|
|
801cfe2: 4606 mov r6, r0
|
|
801cfe4: db01 blt.n 801cfea <_malloc_r+0x1a>
|
|
801cfe6: 42a9 cmp r1, r5
|
|
801cfe8: d903 bls.n 801cff2 <_malloc_r+0x22>
|
|
801cfea: 230c movs r3, #12
|
|
801cfec: 6033 str r3, [r6, #0]
|
|
801cfee: 2000 movs r0, #0
|
|
801cff0: bd70 pop {r4, r5, r6, pc}
|
|
801cff2: f000 febd bl 801dd70 <__malloc_lock>
|
|
801cff6: 4a21 ldr r2, [pc, #132] ; (801d07c <_malloc_r+0xac>)
|
|
801cff8: 6814 ldr r4, [r2, #0]
|
|
801cffa: 4621 mov r1, r4
|
|
801cffc: b991 cbnz r1, 801d024 <_malloc_r+0x54>
|
|
801cffe: 4c20 ldr r4, [pc, #128] ; (801d080 <_malloc_r+0xb0>)
|
|
801d000: 6823 ldr r3, [r4, #0]
|
|
801d002: b91b cbnz r3, 801d00c <_malloc_r+0x3c>
|
|
801d004: 4630 mov r0, r6
|
|
801d006: f000 fc57 bl 801d8b8 <_sbrk_r>
|
|
801d00a: 6020 str r0, [r4, #0]
|
|
801d00c: 4629 mov r1, r5
|
|
801d00e: 4630 mov r0, r6
|
|
801d010: f000 fc52 bl 801d8b8 <_sbrk_r>
|
|
801d014: 1c43 adds r3, r0, #1
|
|
801d016: d124 bne.n 801d062 <_malloc_r+0x92>
|
|
801d018: 230c movs r3, #12
|
|
801d01a: 6033 str r3, [r6, #0]
|
|
801d01c: 4630 mov r0, r6
|
|
801d01e: f000 fea8 bl 801dd72 <__malloc_unlock>
|
|
801d022: e7e4 b.n 801cfee <_malloc_r+0x1e>
|
|
801d024: 680b ldr r3, [r1, #0]
|
|
801d026: 1b5b subs r3, r3, r5
|
|
801d028: d418 bmi.n 801d05c <_malloc_r+0x8c>
|
|
801d02a: 2b0b cmp r3, #11
|
|
801d02c: d90f bls.n 801d04e <_malloc_r+0x7e>
|
|
801d02e: 600b str r3, [r1, #0]
|
|
801d030: 50cd str r5, [r1, r3]
|
|
801d032: 18cc adds r4, r1, r3
|
|
801d034: 4630 mov r0, r6
|
|
801d036: f000 fe9c bl 801dd72 <__malloc_unlock>
|
|
801d03a: f104 000b add.w r0, r4, #11
|
|
801d03e: 1d23 adds r3, r4, #4
|
|
801d040: f020 0007 bic.w r0, r0, #7
|
|
801d044: 1ac3 subs r3, r0, r3
|
|
801d046: d0d3 beq.n 801cff0 <_malloc_r+0x20>
|
|
801d048: 425a negs r2, r3
|
|
801d04a: 50e2 str r2, [r4, r3]
|
|
801d04c: e7d0 b.n 801cff0 <_malloc_r+0x20>
|
|
801d04e: 428c cmp r4, r1
|
|
801d050: 684b ldr r3, [r1, #4]
|
|
801d052: bf16 itet ne
|
|
801d054: 6063 strne r3, [r4, #4]
|
|
801d056: 6013 streq r3, [r2, #0]
|
|
801d058: 460c movne r4, r1
|
|
801d05a: e7eb b.n 801d034 <_malloc_r+0x64>
|
|
801d05c: 460c mov r4, r1
|
|
801d05e: 6849 ldr r1, [r1, #4]
|
|
801d060: e7cc b.n 801cffc <_malloc_r+0x2c>
|
|
801d062: 1cc4 adds r4, r0, #3
|
|
801d064: f024 0403 bic.w r4, r4, #3
|
|
801d068: 42a0 cmp r0, r4
|
|
801d06a: d005 beq.n 801d078 <_malloc_r+0xa8>
|
|
801d06c: 1a21 subs r1, r4, r0
|
|
801d06e: 4630 mov r0, r6
|
|
801d070: f000 fc22 bl 801d8b8 <_sbrk_r>
|
|
801d074: 3001 adds r0, #1
|
|
801d076: d0cf beq.n 801d018 <_malloc_r+0x48>
|
|
801d078: 6025 str r5, [r4, #0]
|
|
801d07a: e7db b.n 801d034 <_malloc_r+0x64>
|
|
801d07c: 20008874 .word 0x20008874
|
|
801d080: 20008878 .word 0x20008878
|
|
|
|
0801d084 <__ssputs_r>:
|
|
801d084: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801d088: 688e ldr r6, [r1, #8]
|
|
801d08a: 429e cmp r6, r3
|
|
801d08c: 4682 mov sl, r0
|
|
801d08e: 460c mov r4, r1
|
|
801d090: 4690 mov r8, r2
|
|
801d092: 4699 mov r9, r3
|
|
801d094: d837 bhi.n 801d106 <__ssputs_r+0x82>
|
|
801d096: 898a ldrh r2, [r1, #12]
|
|
801d098: f412 6f90 tst.w r2, #1152 ; 0x480
|
|
801d09c: d031 beq.n 801d102 <__ssputs_r+0x7e>
|
|
801d09e: 6825 ldr r5, [r4, #0]
|
|
801d0a0: 6909 ldr r1, [r1, #16]
|
|
801d0a2: 1a6f subs r7, r5, r1
|
|
801d0a4: 6965 ldr r5, [r4, #20]
|
|
801d0a6: 2302 movs r3, #2
|
|
801d0a8: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
801d0ac: fb95 f5f3 sdiv r5, r5, r3
|
|
801d0b0: f109 0301 add.w r3, r9, #1
|
|
801d0b4: 443b add r3, r7
|
|
801d0b6: 429d cmp r5, r3
|
|
801d0b8: bf38 it cc
|
|
801d0ba: 461d movcc r5, r3
|
|
801d0bc: 0553 lsls r3, r2, #21
|
|
801d0be: d530 bpl.n 801d122 <__ssputs_r+0x9e>
|
|
801d0c0: 4629 mov r1, r5
|
|
801d0c2: f7ff ff85 bl 801cfd0 <_malloc_r>
|
|
801d0c6: 4606 mov r6, r0
|
|
801d0c8: b950 cbnz r0, 801d0e0 <__ssputs_r+0x5c>
|
|
801d0ca: 230c movs r3, #12
|
|
801d0cc: f8ca 3000 str.w r3, [sl]
|
|
801d0d0: 89a3 ldrh r3, [r4, #12]
|
|
801d0d2: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
801d0d6: 81a3 strh r3, [r4, #12]
|
|
801d0d8: f04f 30ff mov.w r0, #4294967295
|
|
801d0dc: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801d0e0: 463a mov r2, r7
|
|
801d0e2: 6921 ldr r1, [r4, #16]
|
|
801d0e4: f7ff fdbb bl 801cc5e <memcpy>
|
|
801d0e8: 89a3 ldrh r3, [r4, #12]
|
|
801d0ea: f423 6390 bic.w r3, r3, #1152 ; 0x480
|
|
801d0ee: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
801d0f2: 81a3 strh r3, [r4, #12]
|
|
801d0f4: 6126 str r6, [r4, #16]
|
|
801d0f6: 6165 str r5, [r4, #20]
|
|
801d0f8: 443e add r6, r7
|
|
801d0fa: 1bed subs r5, r5, r7
|
|
801d0fc: 6026 str r6, [r4, #0]
|
|
801d0fe: 60a5 str r5, [r4, #8]
|
|
801d100: 464e mov r6, r9
|
|
801d102: 454e cmp r6, r9
|
|
801d104: d900 bls.n 801d108 <__ssputs_r+0x84>
|
|
801d106: 464e mov r6, r9
|
|
801d108: 4632 mov r2, r6
|
|
801d10a: 4641 mov r1, r8
|
|
801d10c: 6820 ldr r0, [r4, #0]
|
|
801d10e: f7ff fdb1 bl 801cc74 <memmove>
|
|
801d112: 68a3 ldr r3, [r4, #8]
|
|
801d114: 1b9b subs r3, r3, r6
|
|
801d116: 60a3 str r3, [r4, #8]
|
|
801d118: 6823 ldr r3, [r4, #0]
|
|
801d11a: 441e add r6, r3
|
|
801d11c: 6026 str r6, [r4, #0]
|
|
801d11e: 2000 movs r0, #0
|
|
801d120: e7dc b.n 801d0dc <__ssputs_r+0x58>
|
|
801d122: 462a mov r2, r5
|
|
801d124: f000 fe26 bl 801dd74 <_realloc_r>
|
|
801d128: 4606 mov r6, r0
|
|
801d12a: 2800 cmp r0, #0
|
|
801d12c: d1e2 bne.n 801d0f4 <__ssputs_r+0x70>
|
|
801d12e: 6921 ldr r1, [r4, #16]
|
|
801d130: 4650 mov r0, sl
|
|
801d132: f7ff feff bl 801cf34 <_free_r>
|
|
801d136: e7c8 b.n 801d0ca <__ssputs_r+0x46>
|
|
|
|
0801d138 <_svfiprintf_r>:
|
|
801d138: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801d13c: 461d mov r5, r3
|
|
801d13e: 898b ldrh r3, [r1, #12]
|
|
801d140: 061f lsls r7, r3, #24
|
|
801d142: b09d sub sp, #116 ; 0x74
|
|
801d144: 4680 mov r8, r0
|
|
801d146: 460c mov r4, r1
|
|
801d148: 4616 mov r6, r2
|
|
801d14a: d50f bpl.n 801d16c <_svfiprintf_r+0x34>
|
|
801d14c: 690b ldr r3, [r1, #16]
|
|
801d14e: b96b cbnz r3, 801d16c <_svfiprintf_r+0x34>
|
|
801d150: 2140 movs r1, #64 ; 0x40
|
|
801d152: f7ff ff3d bl 801cfd0 <_malloc_r>
|
|
801d156: 6020 str r0, [r4, #0]
|
|
801d158: 6120 str r0, [r4, #16]
|
|
801d15a: b928 cbnz r0, 801d168 <_svfiprintf_r+0x30>
|
|
801d15c: 230c movs r3, #12
|
|
801d15e: f8c8 3000 str.w r3, [r8]
|
|
801d162: f04f 30ff mov.w r0, #4294967295
|
|
801d166: e0c8 b.n 801d2fa <_svfiprintf_r+0x1c2>
|
|
801d168: 2340 movs r3, #64 ; 0x40
|
|
801d16a: 6163 str r3, [r4, #20]
|
|
801d16c: 2300 movs r3, #0
|
|
801d16e: 9309 str r3, [sp, #36] ; 0x24
|
|
801d170: 2320 movs r3, #32
|
|
801d172: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
801d176: 2330 movs r3, #48 ; 0x30
|
|
801d178: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
801d17c: 9503 str r5, [sp, #12]
|
|
801d17e: f04f 0b01 mov.w fp, #1
|
|
801d182: 4637 mov r7, r6
|
|
801d184: 463d mov r5, r7
|
|
801d186: f815 3b01 ldrb.w r3, [r5], #1
|
|
801d18a: b10b cbz r3, 801d190 <_svfiprintf_r+0x58>
|
|
801d18c: 2b25 cmp r3, #37 ; 0x25
|
|
801d18e: d13e bne.n 801d20e <_svfiprintf_r+0xd6>
|
|
801d190: ebb7 0a06 subs.w sl, r7, r6
|
|
801d194: d00b beq.n 801d1ae <_svfiprintf_r+0x76>
|
|
801d196: 4653 mov r3, sl
|
|
801d198: 4632 mov r2, r6
|
|
801d19a: 4621 mov r1, r4
|
|
801d19c: 4640 mov r0, r8
|
|
801d19e: f7ff ff71 bl 801d084 <__ssputs_r>
|
|
801d1a2: 3001 adds r0, #1
|
|
801d1a4: f000 80a4 beq.w 801d2f0 <_svfiprintf_r+0x1b8>
|
|
801d1a8: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
801d1aa: 4453 add r3, sl
|
|
801d1ac: 9309 str r3, [sp, #36] ; 0x24
|
|
801d1ae: 783b ldrb r3, [r7, #0]
|
|
801d1b0: 2b00 cmp r3, #0
|
|
801d1b2: f000 809d beq.w 801d2f0 <_svfiprintf_r+0x1b8>
|
|
801d1b6: 2300 movs r3, #0
|
|
801d1b8: f04f 32ff mov.w r2, #4294967295
|
|
801d1bc: e9cd 2305 strd r2, r3, [sp, #20]
|
|
801d1c0: 9304 str r3, [sp, #16]
|
|
801d1c2: 9307 str r3, [sp, #28]
|
|
801d1c4: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
801d1c8: 931a str r3, [sp, #104] ; 0x68
|
|
801d1ca: 462f mov r7, r5
|
|
801d1cc: 2205 movs r2, #5
|
|
801d1ce: f817 1b01 ldrb.w r1, [r7], #1
|
|
801d1d2: 4850 ldr r0, [pc, #320] ; (801d314 <_svfiprintf_r+0x1dc>)
|
|
801d1d4: f7e3 f81c bl 8000210 <memchr>
|
|
801d1d8: 9b04 ldr r3, [sp, #16]
|
|
801d1da: b9d0 cbnz r0, 801d212 <_svfiprintf_r+0xda>
|
|
801d1dc: 06d9 lsls r1, r3, #27
|
|
801d1de: bf44 itt mi
|
|
801d1e0: 2220 movmi r2, #32
|
|
801d1e2: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
|
|
801d1e6: 071a lsls r2, r3, #28
|
|
801d1e8: bf44 itt mi
|
|
801d1ea: 222b movmi r2, #43 ; 0x2b
|
|
801d1ec: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
|
|
801d1f0: 782a ldrb r2, [r5, #0]
|
|
801d1f2: 2a2a cmp r2, #42 ; 0x2a
|
|
801d1f4: d015 beq.n 801d222 <_svfiprintf_r+0xea>
|
|
801d1f6: 9a07 ldr r2, [sp, #28]
|
|
801d1f8: 462f mov r7, r5
|
|
801d1fa: 2000 movs r0, #0
|
|
801d1fc: 250a movs r5, #10
|
|
801d1fe: 4639 mov r1, r7
|
|
801d200: f811 3b01 ldrb.w r3, [r1], #1
|
|
801d204: 3b30 subs r3, #48 ; 0x30
|
|
801d206: 2b09 cmp r3, #9
|
|
801d208: d94d bls.n 801d2a6 <_svfiprintf_r+0x16e>
|
|
801d20a: b1b8 cbz r0, 801d23c <_svfiprintf_r+0x104>
|
|
801d20c: e00f b.n 801d22e <_svfiprintf_r+0xf6>
|
|
801d20e: 462f mov r7, r5
|
|
801d210: e7b8 b.n 801d184 <_svfiprintf_r+0x4c>
|
|
801d212: 4a40 ldr r2, [pc, #256] ; (801d314 <_svfiprintf_r+0x1dc>)
|
|
801d214: 1a80 subs r0, r0, r2
|
|
801d216: fa0b f000 lsl.w r0, fp, r0
|
|
801d21a: 4318 orrs r0, r3
|
|
801d21c: 9004 str r0, [sp, #16]
|
|
801d21e: 463d mov r5, r7
|
|
801d220: e7d3 b.n 801d1ca <_svfiprintf_r+0x92>
|
|
801d222: 9a03 ldr r2, [sp, #12]
|
|
801d224: 1d11 adds r1, r2, #4
|
|
801d226: 6812 ldr r2, [r2, #0]
|
|
801d228: 9103 str r1, [sp, #12]
|
|
801d22a: 2a00 cmp r2, #0
|
|
801d22c: db01 blt.n 801d232 <_svfiprintf_r+0xfa>
|
|
801d22e: 9207 str r2, [sp, #28]
|
|
801d230: e004 b.n 801d23c <_svfiprintf_r+0x104>
|
|
801d232: 4252 negs r2, r2
|
|
801d234: f043 0302 orr.w r3, r3, #2
|
|
801d238: 9207 str r2, [sp, #28]
|
|
801d23a: 9304 str r3, [sp, #16]
|
|
801d23c: 783b ldrb r3, [r7, #0]
|
|
801d23e: 2b2e cmp r3, #46 ; 0x2e
|
|
801d240: d10c bne.n 801d25c <_svfiprintf_r+0x124>
|
|
801d242: 787b ldrb r3, [r7, #1]
|
|
801d244: 2b2a cmp r3, #42 ; 0x2a
|
|
801d246: d133 bne.n 801d2b0 <_svfiprintf_r+0x178>
|
|
801d248: 9b03 ldr r3, [sp, #12]
|
|
801d24a: 1d1a adds r2, r3, #4
|
|
801d24c: 681b ldr r3, [r3, #0]
|
|
801d24e: 9203 str r2, [sp, #12]
|
|
801d250: 2b00 cmp r3, #0
|
|
801d252: bfb8 it lt
|
|
801d254: f04f 33ff movlt.w r3, #4294967295
|
|
801d258: 3702 adds r7, #2
|
|
801d25a: 9305 str r3, [sp, #20]
|
|
801d25c: 4d2e ldr r5, [pc, #184] ; (801d318 <_svfiprintf_r+0x1e0>)
|
|
801d25e: 7839 ldrb r1, [r7, #0]
|
|
801d260: 2203 movs r2, #3
|
|
801d262: 4628 mov r0, r5
|
|
801d264: f7e2 ffd4 bl 8000210 <memchr>
|
|
801d268: b138 cbz r0, 801d27a <_svfiprintf_r+0x142>
|
|
801d26a: 2340 movs r3, #64 ; 0x40
|
|
801d26c: 1b40 subs r0, r0, r5
|
|
801d26e: fa03 f000 lsl.w r0, r3, r0
|
|
801d272: 9b04 ldr r3, [sp, #16]
|
|
801d274: 4303 orrs r3, r0
|
|
801d276: 3701 adds r7, #1
|
|
801d278: 9304 str r3, [sp, #16]
|
|
801d27a: 7839 ldrb r1, [r7, #0]
|
|
801d27c: 4827 ldr r0, [pc, #156] ; (801d31c <_svfiprintf_r+0x1e4>)
|
|
801d27e: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
801d282: 2206 movs r2, #6
|
|
801d284: 1c7e adds r6, r7, #1
|
|
801d286: f7e2 ffc3 bl 8000210 <memchr>
|
|
801d28a: 2800 cmp r0, #0
|
|
801d28c: d038 beq.n 801d300 <_svfiprintf_r+0x1c8>
|
|
801d28e: 4b24 ldr r3, [pc, #144] ; (801d320 <_svfiprintf_r+0x1e8>)
|
|
801d290: bb13 cbnz r3, 801d2d8 <_svfiprintf_r+0x1a0>
|
|
801d292: 9b03 ldr r3, [sp, #12]
|
|
801d294: 3307 adds r3, #7
|
|
801d296: f023 0307 bic.w r3, r3, #7
|
|
801d29a: 3308 adds r3, #8
|
|
801d29c: 9303 str r3, [sp, #12]
|
|
801d29e: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
801d2a0: 444b add r3, r9
|
|
801d2a2: 9309 str r3, [sp, #36] ; 0x24
|
|
801d2a4: e76d b.n 801d182 <_svfiprintf_r+0x4a>
|
|
801d2a6: fb05 3202 mla r2, r5, r2, r3
|
|
801d2aa: 2001 movs r0, #1
|
|
801d2ac: 460f mov r7, r1
|
|
801d2ae: e7a6 b.n 801d1fe <_svfiprintf_r+0xc6>
|
|
801d2b0: 2300 movs r3, #0
|
|
801d2b2: 3701 adds r7, #1
|
|
801d2b4: 9305 str r3, [sp, #20]
|
|
801d2b6: 4619 mov r1, r3
|
|
801d2b8: 250a movs r5, #10
|
|
801d2ba: 4638 mov r0, r7
|
|
801d2bc: f810 2b01 ldrb.w r2, [r0], #1
|
|
801d2c0: 3a30 subs r2, #48 ; 0x30
|
|
801d2c2: 2a09 cmp r2, #9
|
|
801d2c4: d903 bls.n 801d2ce <_svfiprintf_r+0x196>
|
|
801d2c6: 2b00 cmp r3, #0
|
|
801d2c8: d0c8 beq.n 801d25c <_svfiprintf_r+0x124>
|
|
801d2ca: 9105 str r1, [sp, #20]
|
|
801d2cc: e7c6 b.n 801d25c <_svfiprintf_r+0x124>
|
|
801d2ce: fb05 2101 mla r1, r5, r1, r2
|
|
801d2d2: 2301 movs r3, #1
|
|
801d2d4: 4607 mov r7, r0
|
|
801d2d6: e7f0 b.n 801d2ba <_svfiprintf_r+0x182>
|
|
801d2d8: ab03 add r3, sp, #12
|
|
801d2da: 9300 str r3, [sp, #0]
|
|
801d2dc: 4622 mov r2, r4
|
|
801d2de: 4b11 ldr r3, [pc, #68] ; (801d324 <_svfiprintf_r+0x1ec>)
|
|
801d2e0: a904 add r1, sp, #16
|
|
801d2e2: 4640 mov r0, r8
|
|
801d2e4: f3af 8000 nop.w
|
|
801d2e8: f1b0 3fff cmp.w r0, #4294967295
|
|
801d2ec: 4681 mov r9, r0
|
|
801d2ee: d1d6 bne.n 801d29e <_svfiprintf_r+0x166>
|
|
801d2f0: 89a3 ldrh r3, [r4, #12]
|
|
801d2f2: 065b lsls r3, r3, #25
|
|
801d2f4: f53f af35 bmi.w 801d162 <_svfiprintf_r+0x2a>
|
|
801d2f8: 9809 ldr r0, [sp, #36] ; 0x24
|
|
801d2fa: b01d add sp, #116 ; 0x74
|
|
801d2fc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801d300: ab03 add r3, sp, #12
|
|
801d302: 9300 str r3, [sp, #0]
|
|
801d304: 4622 mov r2, r4
|
|
801d306: 4b07 ldr r3, [pc, #28] ; (801d324 <_svfiprintf_r+0x1ec>)
|
|
801d308: a904 add r1, sp, #16
|
|
801d30a: 4640 mov r0, r8
|
|
801d30c: f000 f9c2 bl 801d694 <_printf_i>
|
|
801d310: e7ea b.n 801d2e8 <_svfiprintf_r+0x1b0>
|
|
801d312: bf00 nop
|
|
801d314: 08022eec .word 0x08022eec
|
|
801d318: 08022ef2 .word 0x08022ef2
|
|
801d31c: 08022ef6 .word 0x08022ef6
|
|
801d320: 00000000 .word 0x00000000
|
|
801d324: 0801d085 .word 0x0801d085
|
|
|
|
0801d328 <__sfputc_r>:
|
|
801d328: 6893 ldr r3, [r2, #8]
|
|
801d32a: 3b01 subs r3, #1
|
|
801d32c: 2b00 cmp r3, #0
|
|
801d32e: b410 push {r4}
|
|
801d330: 6093 str r3, [r2, #8]
|
|
801d332: da08 bge.n 801d346 <__sfputc_r+0x1e>
|
|
801d334: 6994 ldr r4, [r2, #24]
|
|
801d336: 42a3 cmp r3, r4
|
|
801d338: db01 blt.n 801d33e <__sfputc_r+0x16>
|
|
801d33a: 290a cmp r1, #10
|
|
801d33c: d103 bne.n 801d346 <__sfputc_r+0x1e>
|
|
801d33e: f85d 4b04 ldr.w r4, [sp], #4
|
|
801d342: f000 bb0d b.w 801d960 <__swbuf_r>
|
|
801d346: 6813 ldr r3, [r2, #0]
|
|
801d348: 1c58 adds r0, r3, #1
|
|
801d34a: 6010 str r0, [r2, #0]
|
|
801d34c: 7019 strb r1, [r3, #0]
|
|
801d34e: 4608 mov r0, r1
|
|
801d350: f85d 4b04 ldr.w r4, [sp], #4
|
|
801d354: 4770 bx lr
|
|
|
|
0801d356 <__sfputs_r>:
|
|
801d356: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801d358: 4606 mov r6, r0
|
|
801d35a: 460f mov r7, r1
|
|
801d35c: 4614 mov r4, r2
|
|
801d35e: 18d5 adds r5, r2, r3
|
|
801d360: 42ac cmp r4, r5
|
|
801d362: d101 bne.n 801d368 <__sfputs_r+0x12>
|
|
801d364: 2000 movs r0, #0
|
|
801d366: e007 b.n 801d378 <__sfputs_r+0x22>
|
|
801d368: 463a mov r2, r7
|
|
801d36a: f814 1b01 ldrb.w r1, [r4], #1
|
|
801d36e: 4630 mov r0, r6
|
|
801d370: f7ff ffda bl 801d328 <__sfputc_r>
|
|
801d374: 1c43 adds r3, r0, #1
|
|
801d376: d1f3 bne.n 801d360 <__sfputs_r+0xa>
|
|
801d378: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
0801d37c <_vfiprintf_r>:
|
|
801d37c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
801d380: 460c mov r4, r1
|
|
801d382: b09d sub sp, #116 ; 0x74
|
|
801d384: 4617 mov r7, r2
|
|
801d386: 461d mov r5, r3
|
|
801d388: 4606 mov r6, r0
|
|
801d38a: b118 cbz r0, 801d394 <_vfiprintf_r+0x18>
|
|
801d38c: 6983 ldr r3, [r0, #24]
|
|
801d38e: b90b cbnz r3, 801d394 <_vfiprintf_r+0x18>
|
|
801d390: f7ff fd3e bl 801ce10 <__sinit>
|
|
801d394: 4b7c ldr r3, [pc, #496] ; (801d588 <_vfiprintf_r+0x20c>)
|
|
801d396: 429c cmp r4, r3
|
|
801d398: d158 bne.n 801d44c <_vfiprintf_r+0xd0>
|
|
801d39a: 6874 ldr r4, [r6, #4]
|
|
801d39c: 89a3 ldrh r3, [r4, #12]
|
|
801d39e: 0718 lsls r0, r3, #28
|
|
801d3a0: d55e bpl.n 801d460 <_vfiprintf_r+0xe4>
|
|
801d3a2: 6923 ldr r3, [r4, #16]
|
|
801d3a4: 2b00 cmp r3, #0
|
|
801d3a6: d05b beq.n 801d460 <_vfiprintf_r+0xe4>
|
|
801d3a8: 2300 movs r3, #0
|
|
801d3aa: 9309 str r3, [sp, #36] ; 0x24
|
|
801d3ac: 2320 movs r3, #32
|
|
801d3ae: f88d 3029 strb.w r3, [sp, #41] ; 0x29
|
|
801d3b2: 2330 movs r3, #48 ; 0x30
|
|
801d3b4: f88d 302a strb.w r3, [sp, #42] ; 0x2a
|
|
801d3b8: 9503 str r5, [sp, #12]
|
|
801d3ba: f04f 0b01 mov.w fp, #1
|
|
801d3be: 46b8 mov r8, r7
|
|
801d3c0: 4645 mov r5, r8
|
|
801d3c2: f815 3b01 ldrb.w r3, [r5], #1
|
|
801d3c6: b10b cbz r3, 801d3cc <_vfiprintf_r+0x50>
|
|
801d3c8: 2b25 cmp r3, #37 ; 0x25
|
|
801d3ca: d154 bne.n 801d476 <_vfiprintf_r+0xfa>
|
|
801d3cc: ebb8 0a07 subs.w sl, r8, r7
|
|
801d3d0: d00b beq.n 801d3ea <_vfiprintf_r+0x6e>
|
|
801d3d2: 4653 mov r3, sl
|
|
801d3d4: 463a mov r2, r7
|
|
801d3d6: 4621 mov r1, r4
|
|
801d3d8: 4630 mov r0, r6
|
|
801d3da: f7ff ffbc bl 801d356 <__sfputs_r>
|
|
801d3de: 3001 adds r0, #1
|
|
801d3e0: f000 80c2 beq.w 801d568 <_vfiprintf_r+0x1ec>
|
|
801d3e4: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
801d3e6: 4453 add r3, sl
|
|
801d3e8: 9309 str r3, [sp, #36] ; 0x24
|
|
801d3ea: f898 3000 ldrb.w r3, [r8]
|
|
801d3ee: 2b00 cmp r3, #0
|
|
801d3f0: f000 80ba beq.w 801d568 <_vfiprintf_r+0x1ec>
|
|
801d3f4: 2300 movs r3, #0
|
|
801d3f6: f04f 32ff mov.w r2, #4294967295
|
|
801d3fa: e9cd 2305 strd r2, r3, [sp, #20]
|
|
801d3fe: 9304 str r3, [sp, #16]
|
|
801d400: 9307 str r3, [sp, #28]
|
|
801d402: f88d 3053 strb.w r3, [sp, #83] ; 0x53
|
|
801d406: 931a str r3, [sp, #104] ; 0x68
|
|
801d408: 46a8 mov r8, r5
|
|
801d40a: 2205 movs r2, #5
|
|
801d40c: f818 1b01 ldrb.w r1, [r8], #1
|
|
801d410: 485e ldr r0, [pc, #376] ; (801d58c <_vfiprintf_r+0x210>)
|
|
801d412: f7e2 fefd bl 8000210 <memchr>
|
|
801d416: 9b04 ldr r3, [sp, #16]
|
|
801d418: bb78 cbnz r0, 801d47a <_vfiprintf_r+0xfe>
|
|
801d41a: 06d9 lsls r1, r3, #27
|
|
801d41c: bf44 itt mi
|
|
801d41e: 2220 movmi r2, #32
|
|
801d420: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
|
|
801d424: 071a lsls r2, r3, #28
|
|
801d426: bf44 itt mi
|
|
801d428: 222b movmi r2, #43 ; 0x2b
|
|
801d42a: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
|
|
801d42e: 782a ldrb r2, [r5, #0]
|
|
801d430: 2a2a cmp r2, #42 ; 0x2a
|
|
801d432: d02a beq.n 801d48a <_vfiprintf_r+0x10e>
|
|
801d434: 9a07 ldr r2, [sp, #28]
|
|
801d436: 46a8 mov r8, r5
|
|
801d438: 2000 movs r0, #0
|
|
801d43a: 250a movs r5, #10
|
|
801d43c: 4641 mov r1, r8
|
|
801d43e: f811 3b01 ldrb.w r3, [r1], #1
|
|
801d442: 3b30 subs r3, #48 ; 0x30
|
|
801d444: 2b09 cmp r3, #9
|
|
801d446: d969 bls.n 801d51c <_vfiprintf_r+0x1a0>
|
|
801d448: b360 cbz r0, 801d4a4 <_vfiprintf_r+0x128>
|
|
801d44a: e024 b.n 801d496 <_vfiprintf_r+0x11a>
|
|
801d44c: 4b50 ldr r3, [pc, #320] ; (801d590 <_vfiprintf_r+0x214>)
|
|
801d44e: 429c cmp r4, r3
|
|
801d450: d101 bne.n 801d456 <_vfiprintf_r+0xda>
|
|
801d452: 68b4 ldr r4, [r6, #8]
|
|
801d454: e7a2 b.n 801d39c <_vfiprintf_r+0x20>
|
|
801d456: 4b4f ldr r3, [pc, #316] ; (801d594 <_vfiprintf_r+0x218>)
|
|
801d458: 429c cmp r4, r3
|
|
801d45a: bf08 it eq
|
|
801d45c: 68f4 ldreq r4, [r6, #12]
|
|
801d45e: e79d b.n 801d39c <_vfiprintf_r+0x20>
|
|
801d460: 4621 mov r1, r4
|
|
801d462: 4630 mov r0, r6
|
|
801d464: f000 fae0 bl 801da28 <__swsetup_r>
|
|
801d468: 2800 cmp r0, #0
|
|
801d46a: d09d beq.n 801d3a8 <_vfiprintf_r+0x2c>
|
|
801d46c: f04f 30ff mov.w r0, #4294967295
|
|
801d470: b01d add sp, #116 ; 0x74
|
|
801d472: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
801d476: 46a8 mov r8, r5
|
|
801d478: e7a2 b.n 801d3c0 <_vfiprintf_r+0x44>
|
|
801d47a: 4a44 ldr r2, [pc, #272] ; (801d58c <_vfiprintf_r+0x210>)
|
|
801d47c: 1a80 subs r0, r0, r2
|
|
801d47e: fa0b f000 lsl.w r0, fp, r0
|
|
801d482: 4318 orrs r0, r3
|
|
801d484: 9004 str r0, [sp, #16]
|
|
801d486: 4645 mov r5, r8
|
|
801d488: e7be b.n 801d408 <_vfiprintf_r+0x8c>
|
|
801d48a: 9a03 ldr r2, [sp, #12]
|
|
801d48c: 1d11 adds r1, r2, #4
|
|
801d48e: 6812 ldr r2, [r2, #0]
|
|
801d490: 9103 str r1, [sp, #12]
|
|
801d492: 2a00 cmp r2, #0
|
|
801d494: db01 blt.n 801d49a <_vfiprintf_r+0x11e>
|
|
801d496: 9207 str r2, [sp, #28]
|
|
801d498: e004 b.n 801d4a4 <_vfiprintf_r+0x128>
|
|
801d49a: 4252 negs r2, r2
|
|
801d49c: f043 0302 orr.w r3, r3, #2
|
|
801d4a0: 9207 str r2, [sp, #28]
|
|
801d4a2: 9304 str r3, [sp, #16]
|
|
801d4a4: f898 3000 ldrb.w r3, [r8]
|
|
801d4a8: 2b2e cmp r3, #46 ; 0x2e
|
|
801d4aa: d10e bne.n 801d4ca <_vfiprintf_r+0x14e>
|
|
801d4ac: f898 3001 ldrb.w r3, [r8, #1]
|
|
801d4b0: 2b2a cmp r3, #42 ; 0x2a
|
|
801d4b2: d138 bne.n 801d526 <_vfiprintf_r+0x1aa>
|
|
801d4b4: 9b03 ldr r3, [sp, #12]
|
|
801d4b6: 1d1a adds r2, r3, #4
|
|
801d4b8: 681b ldr r3, [r3, #0]
|
|
801d4ba: 9203 str r2, [sp, #12]
|
|
801d4bc: 2b00 cmp r3, #0
|
|
801d4be: bfb8 it lt
|
|
801d4c0: f04f 33ff movlt.w r3, #4294967295
|
|
801d4c4: f108 0802 add.w r8, r8, #2
|
|
801d4c8: 9305 str r3, [sp, #20]
|
|
801d4ca: 4d33 ldr r5, [pc, #204] ; (801d598 <_vfiprintf_r+0x21c>)
|
|
801d4cc: f898 1000 ldrb.w r1, [r8]
|
|
801d4d0: 2203 movs r2, #3
|
|
801d4d2: 4628 mov r0, r5
|
|
801d4d4: f7e2 fe9c bl 8000210 <memchr>
|
|
801d4d8: b140 cbz r0, 801d4ec <_vfiprintf_r+0x170>
|
|
801d4da: 2340 movs r3, #64 ; 0x40
|
|
801d4dc: 1b40 subs r0, r0, r5
|
|
801d4de: fa03 f000 lsl.w r0, r3, r0
|
|
801d4e2: 9b04 ldr r3, [sp, #16]
|
|
801d4e4: 4303 orrs r3, r0
|
|
801d4e6: f108 0801 add.w r8, r8, #1
|
|
801d4ea: 9304 str r3, [sp, #16]
|
|
801d4ec: f898 1000 ldrb.w r1, [r8]
|
|
801d4f0: 482a ldr r0, [pc, #168] ; (801d59c <_vfiprintf_r+0x220>)
|
|
801d4f2: f88d 1028 strb.w r1, [sp, #40] ; 0x28
|
|
801d4f6: 2206 movs r2, #6
|
|
801d4f8: f108 0701 add.w r7, r8, #1
|
|
801d4fc: f7e2 fe88 bl 8000210 <memchr>
|
|
801d500: 2800 cmp r0, #0
|
|
801d502: d037 beq.n 801d574 <_vfiprintf_r+0x1f8>
|
|
801d504: 4b26 ldr r3, [pc, #152] ; (801d5a0 <_vfiprintf_r+0x224>)
|
|
801d506: bb1b cbnz r3, 801d550 <_vfiprintf_r+0x1d4>
|
|
801d508: 9b03 ldr r3, [sp, #12]
|
|
801d50a: 3307 adds r3, #7
|
|
801d50c: f023 0307 bic.w r3, r3, #7
|
|
801d510: 3308 adds r3, #8
|
|
801d512: 9303 str r3, [sp, #12]
|
|
801d514: 9b09 ldr r3, [sp, #36] ; 0x24
|
|
801d516: 444b add r3, r9
|
|
801d518: 9309 str r3, [sp, #36] ; 0x24
|
|
801d51a: e750 b.n 801d3be <_vfiprintf_r+0x42>
|
|
801d51c: fb05 3202 mla r2, r5, r2, r3
|
|
801d520: 2001 movs r0, #1
|
|
801d522: 4688 mov r8, r1
|
|
801d524: e78a b.n 801d43c <_vfiprintf_r+0xc0>
|
|
801d526: 2300 movs r3, #0
|
|
801d528: f108 0801 add.w r8, r8, #1
|
|
801d52c: 9305 str r3, [sp, #20]
|
|
801d52e: 4619 mov r1, r3
|
|
801d530: 250a movs r5, #10
|
|
801d532: 4640 mov r0, r8
|
|
801d534: f810 2b01 ldrb.w r2, [r0], #1
|
|
801d538: 3a30 subs r2, #48 ; 0x30
|
|
801d53a: 2a09 cmp r2, #9
|
|
801d53c: d903 bls.n 801d546 <_vfiprintf_r+0x1ca>
|
|
801d53e: 2b00 cmp r3, #0
|
|
801d540: d0c3 beq.n 801d4ca <_vfiprintf_r+0x14e>
|
|
801d542: 9105 str r1, [sp, #20]
|
|
801d544: e7c1 b.n 801d4ca <_vfiprintf_r+0x14e>
|
|
801d546: fb05 2101 mla r1, r5, r1, r2
|
|
801d54a: 2301 movs r3, #1
|
|
801d54c: 4680 mov r8, r0
|
|
801d54e: e7f0 b.n 801d532 <_vfiprintf_r+0x1b6>
|
|
801d550: ab03 add r3, sp, #12
|
|
801d552: 9300 str r3, [sp, #0]
|
|
801d554: 4622 mov r2, r4
|
|
801d556: 4b13 ldr r3, [pc, #76] ; (801d5a4 <_vfiprintf_r+0x228>)
|
|
801d558: a904 add r1, sp, #16
|
|
801d55a: 4630 mov r0, r6
|
|
801d55c: f3af 8000 nop.w
|
|
801d560: f1b0 3fff cmp.w r0, #4294967295
|
|
801d564: 4681 mov r9, r0
|
|
801d566: d1d5 bne.n 801d514 <_vfiprintf_r+0x198>
|
|
801d568: 89a3 ldrh r3, [r4, #12]
|
|
801d56a: 065b lsls r3, r3, #25
|
|
801d56c: f53f af7e bmi.w 801d46c <_vfiprintf_r+0xf0>
|
|
801d570: 9809 ldr r0, [sp, #36] ; 0x24
|
|
801d572: e77d b.n 801d470 <_vfiprintf_r+0xf4>
|
|
801d574: ab03 add r3, sp, #12
|
|
801d576: 9300 str r3, [sp, #0]
|
|
801d578: 4622 mov r2, r4
|
|
801d57a: 4b0a ldr r3, [pc, #40] ; (801d5a4 <_vfiprintf_r+0x228>)
|
|
801d57c: a904 add r1, sp, #16
|
|
801d57e: 4630 mov r0, r6
|
|
801d580: f000 f888 bl 801d694 <_printf_i>
|
|
801d584: e7ec b.n 801d560 <_vfiprintf_r+0x1e4>
|
|
801d586: bf00 nop
|
|
801d588: 08022eac .word 0x08022eac
|
|
801d58c: 08022eec .word 0x08022eec
|
|
801d590: 08022ecc .word 0x08022ecc
|
|
801d594: 08022e8c .word 0x08022e8c
|
|
801d598: 08022ef2 .word 0x08022ef2
|
|
801d59c: 08022ef6 .word 0x08022ef6
|
|
801d5a0: 00000000 .word 0x00000000
|
|
801d5a4: 0801d357 .word 0x0801d357
|
|
|
|
0801d5a8 <_printf_common>:
|
|
801d5a8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
801d5ac: 4691 mov r9, r2
|
|
801d5ae: 461f mov r7, r3
|
|
801d5b0: 688a ldr r2, [r1, #8]
|
|
801d5b2: 690b ldr r3, [r1, #16]
|
|
801d5b4: f8dd 8020 ldr.w r8, [sp, #32]
|
|
801d5b8: 4293 cmp r3, r2
|
|
801d5ba: bfb8 it lt
|
|
801d5bc: 4613 movlt r3, r2
|
|
801d5be: f8c9 3000 str.w r3, [r9]
|
|
801d5c2: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
|
|
801d5c6: 4606 mov r6, r0
|
|
801d5c8: 460c mov r4, r1
|
|
801d5ca: b112 cbz r2, 801d5d2 <_printf_common+0x2a>
|
|
801d5cc: 3301 adds r3, #1
|
|
801d5ce: f8c9 3000 str.w r3, [r9]
|
|
801d5d2: 6823 ldr r3, [r4, #0]
|
|
801d5d4: 0699 lsls r1, r3, #26
|
|
801d5d6: bf42 ittt mi
|
|
801d5d8: f8d9 3000 ldrmi.w r3, [r9]
|
|
801d5dc: 3302 addmi r3, #2
|
|
801d5de: f8c9 3000 strmi.w r3, [r9]
|
|
801d5e2: 6825 ldr r5, [r4, #0]
|
|
801d5e4: f015 0506 ands.w r5, r5, #6
|
|
801d5e8: d107 bne.n 801d5fa <_printf_common+0x52>
|
|
801d5ea: f104 0a19 add.w sl, r4, #25
|
|
801d5ee: 68e3 ldr r3, [r4, #12]
|
|
801d5f0: f8d9 2000 ldr.w r2, [r9]
|
|
801d5f4: 1a9b subs r3, r3, r2
|
|
801d5f6: 42ab cmp r3, r5
|
|
801d5f8: dc28 bgt.n 801d64c <_printf_common+0xa4>
|
|
801d5fa: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
|
|
801d5fe: 6822 ldr r2, [r4, #0]
|
|
801d600: 3300 adds r3, #0
|
|
801d602: bf18 it ne
|
|
801d604: 2301 movne r3, #1
|
|
801d606: 0692 lsls r2, r2, #26
|
|
801d608: d42d bmi.n 801d666 <_printf_common+0xbe>
|
|
801d60a: f104 0243 add.w r2, r4, #67 ; 0x43
|
|
801d60e: 4639 mov r1, r7
|
|
801d610: 4630 mov r0, r6
|
|
801d612: 47c0 blx r8
|
|
801d614: 3001 adds r0, #1
|
|
801d616: d020 beq.n 801d65a <_printf_common+0xb2>
|
|
801d618: 6823 ldr r3, [r4, #0]
|
|
801d61a: 68e5 ldr r5, [r4, #12]
|
|
801d61c: f8d9 2000 ldr.w r2, [r9]
|
|
801d620: f003 0306 and.w r3, r3, #6
|
|
801d624: 2b04 cmp r3, #4
|
|
801d626: bf08 it eq
|
|
801d628: 1aad subeq r5, r5, r2
|
|
801d62a: 68a3 ldr r3, [r4, #8]
|
|
801d62c: 6922 ldr r2, [r4, #16]
|
|
801d62e: bf0c ite eq
|
|
801d630: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
801d634: 2500 movne r5, #0
|
|
801d636: 4293 cmp r3, r2
|
|
801d638: bfc4 itt gt
|
|
801d63a: 1a9b subgt r3, r3, r2
|
|
801d63c: 18ed addgt r5, r5, r3
|
|
801d63e: f04f 0900 mov.w r9, #0
|
|
801d642: 341a adds r4, #26
|
|
801d644: 454d cmp r5, r9
|
|
801d646: d11a bne.n 801d67e <_printf_common+0xd6>
|
|
801d648: 2000 movs r0, #0
|
|
801d64a: e008 b.n 801d65e <_printf_common+0xb6>
|
|
801d64c: 2301 movs r3, #1
|
|
801d64e: 4652 mov r2, sl
|
|
801d650: 4639 mov r1, r7
|
|
801d652: 4630 mov r0, r6
|
|
801d654: 47c0 blx r8
|
|
801d656: 3001 adds r0, #1
|
|
801d658: d103 bne.n 801d662 <_printf_common+0xba>
|
|
801d65a: f04f 30ff mov.w r0, #4294967295
|
|
801d65e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
801d662: 3501 adds r5, #1
|
|
801d664: e7c3 b.n 801d5ee <_printf_common+0x46>
|
|
801d666: 18e1 adds r1, r4, r3
|
|
801d668: 1c5a adds r2, r3, #1
|
|
801d66a: 2030 movs r0, #48 ; 0x30
|
|
801d66c: f881 0043 strb.w r0, [r1, #67] ; 0x43
|
|
801d670: 4422 add r2, r4
|
|
801d672: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
|
|
801d676: f882 1043 strb.w r1, [r2, #67] ; 0x43
|
|
801d67a: 3302 adds r3, #2
|
|
801d67c: e7c5 b.n 801d60a <_printf_common+0x62>
|
|
801d67e: 2301 movs r3, #1
|
|
801d680: 4622 mov r2, r4
|
|
801d682: 4639 mov r1, r7
|
|
801d684: 4630 mov r0, r6
|
|
801d686: 47c0 blx r8
|
|
801d688: 3001 adds r0, #1
|
|
801d68a: d0e6 beq.n 801d65a <_printf_common+0xb2>
|
|
801d68c: f109 0901 add.w r9, r9, #1
|
|
801d690: e7d8 b.n 801d644 <_printf_common+0x9c>
|
|
...
|
|
|
|
0801d694 <_printf_i>:
|
|
801d694: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
|
|
801d698: f101 0c43 add.w ip, r1, #67 ; 0x43
|
|
801d69c: 460c mov r4, r1
|
|
801d69e: 7e09 ldrb r1, [r1, #24]
|
|
801d6a0: b085 sub sp, #20
|
|
801d6a2: 296e cmp r1, #110 ; 0x6e
|
|
801d6a4: 4617 mov r7, r2
|
|
801d6a6: 4606 mov r6, r0
|
|
801d6a8: 4698 mov r8, r3
|
|
801d6aa: 9a0c ldr r2, [sp, #48] ; 0x30
|
|
801d6ac: f000 80b3 beq.w 801d816 <_printf_i+0x182>
|
|
801d6b0: d822 bhi.n 801d6f8 <_printf_i+0x64>
|
|
801d6b2: 2963 cmp r1, #99 ; 0x63
|
|
801d6b4: d036 beq.n 801d724 <_printf_i+0x90>
|
|
801d6b6: d80a bhi.n 801d6ce <_printf_i+0x3a>
|
|
801d6b8: 2900 cmp r1, #0
|
|
801d6ba: f000 80b9 beq.w 801d830 <_printf_i+0x19c>
|
|
801d6be: 2958 cmp r1, #88 ; 0x58
|
|
801d6c0: f000 8083 beq.w 801d7ca <_printf_i+0x136>
|
|
801d6c4: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
801d6c8: f884 1042 strb.w r1, [r4, #66] ; 0x42
|
|
801d6cc: e032 b.n 801d734 <_printf_i+0xa0>
|
|
801d6ce: 2964 cmp r1, #100 ; 0x64
|
|
801d6d0: d001 beq.n 801d6d6 <_printf_i+0x42>
|
|
801d6d2: 2969 cmp r1, #105 ; 0x69
|
|
801d6d4: d1f6 bne.n 801d6c4 <_printf_i+0x30>
|
|
801d6d6: 6820 ldr r0, [r4, #0]
|
|
801d6d8: 6813 ldr r3, [r2, #0]
|
|
801d6da: 0605 lsls r5, r0, #24
|
|
801d6dc: f103 0104 add.w r1, r3, #4
|
|
801d6e0: d52a bpl.n 801d738 <_printf_i+0xa4>
|
|
801d6e2: 681b ldr r3, [r3, #0]
|
|
801d6e4: 6011 str r1, [r2, #0]
|
|
801d6e6: 2b00 cmp r3, #0
|
|
801d6e8: da03 bge.n 801d6f2 <_printf_i+0x5e>
|
|
801d6ea: 222d movs r2, #45 ; 0x2d
|
|
801d6ec: 425b negs r3, r3
|
|
801d6ee: f884 2043 strb.w r2, [r4, #67] ; 0x43
|
|
801d6f2: 486f ldr r0, [pc, #444] ; (801d8b0 <_printf_i+0x21c>)
|
|
801d6f4: 220a movs r2, #10
|
|
801d6f6: e039 b.n 801d76c <_printf_i+0xd8>
|
|
801d6f8: 2973 cmp r1, #115 ; 0x73
|
|
801d6fa: f000 809d beq.w 801d838 <_printf_i+0x1a4>
|
|
801d6fe: d808 bhi.n 801d712 <_printf_i+0x7e>
|
|
801d700: 296f cmp r1, #111 ; 0x6f
|
|
801d702: d020 beq.n 801d746 <_printf_i+0xb2>
|
|
801d704: 2970 cmp r1, #112 ; 0x70
|
|
801d706: d1dd bne.n 801d6c4 <_printf_i+0x30>
|
|
801d708: 6823 ldr r3, [r4, #0]
|
|
801d70a: f043 0320 orr.w r3, r3, #32
|
|
801d70e: 6023 str r3, [r4, #0]
|
|
801d710: e003 b.n 801d71a <_printf_i+0x86>
|
|
801d712: 2975 cmp r1, #117 ; 0x75
|
|
801d714: d017 beq.n 801d746 <_printf_i+0xb2>
|
|
801d716: 2978 cmp r1, #120 ; 0x78
|
|
801d718: d1d4 bne.n 801d6c4 <_printf_i+0x30>
|
|
801d71a: 2378 movs r3, #120 ; 0x78
|
|
801d71c: f884 3045 strb.w r3, [r4, #69] ; 0x45
|
|
801d720: 4864 ldr r0, [pc, #400] ; (801d8b4 <_printf_i+0x220>)
|
|
801d722: e055 b.n 801d7d0 <_printf_i+0x13c>
|
|
801d724: 6813 ldr r3, [r2, #0]
|
|
801d726: 1d19 adds r1, r3, #4
|
|
801d728: 681b ldr r3, [r3, #0]
|
|
801d72a: 6011 str r1, [r2, #0]
|
|
801d72c: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
801d730: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
801d734: 2301 movs r3, #1
|
|
801d736: e08c b.n 801d852 <_printf_i+0x1be>
|
|
801d738: 681b ldr r3, [r3, #0]
|
|
801d73a: 6011 str r1, [r2, #0]
|
|
801d73c: f010 0f40 tst.w r0, #64 ; 0x40
|
|
801d740: bf18 it ne
|
|
801d742: b21b sxthne r3, r3
|
|
801d744: e7cf b.n 801d6e6 <_printf_i+0x52>
|
|
801d746: 6813 ldr r3, [r2, #0]
|
|
801d748: 6825 ldr r5, [r4, #0]
|
|
801d74a: 1d18 adds r0, r3, #4
|
|
801d74c: 6010 str r0, [r2, #0]
|
|
801d74e: 0628 lsls r0, r5, #24
|
|
801d750: d501 bpl.n 801d756 <_printf_i+0xc2>
|
|
801d752: 681b ldr r3, [r3, #0]
|
|
801d754: e002 b.n 801d75c <_printf_i+0xc8>
|
|
801d756: 0668 lsls r0, r5, #25
|
|
801d758: d5fb bpl.n 801d752 <_printf_i+0xbe>
|
|
801d75a: 881b ldrh r3, [r3, #0]
|
|
801d75c: 4854 ldr r0, [pc, #336] ; (801d8b0 <_printf_i+0x21c>)
|
|
801d75e: 296f cmp r1, #111 ; 0x6f
|
|
801d760: bf14 ite ne
|
|
801d762: 220a movne r2, #10
|
|
801d764: 2208 moveq r2, #8
|
|
801d766: 2100 movs r1, #0
|
|
801d768: f884 1043 strb.w r1, [r4, #67] ; 0x43
|
|
801d76c: 6865 ldr r5, [r4, #4]
|
|
801d76e: 60a5 str r5, [r4, #8]
|
|
801d770: 2d00 cmp r5, #0
|
|
801d772: f2c0 8095 blt.w 801d8a0 <_printf_i+0x20c>
|
|
801d776: 6821 ldr r1, [r4, #0]
|
|
801d778: f021 0104 bic.w r1, r1, #4
|
|
801d77c: 6021 str r1, [r4, #0]
|
|
801d77e: 2b00 cmp r3, #0
|
|
801d780: d13d bne.n 801d7fe <_printf_i+0x16a>
|
|
801d782: 2d00 cmp r5, #0
|
|
801d784: f040 808e bne.w 801d8a4 <_printf_i+0x210>
|
|
801d788: 4665 mov r5, ip
|
|
801d78a: 2a08 cmp r2, #8
|
|
801d78c: d10b bne.n 801d7a6 <_printf_i+0x112>
|
|
801d78e: 6823 ldr r3, [r4, #0]
|
|
801d790: 07db lsls r3, r3, #31
|
|
801d792: d508 bpl.n 801d7a6 <_printf_i+0x112>
|
|
801d794: 6923 ldr r3, [r4, #16]
|
|
801d796: 6862 ldr r2, [r4, #4]
|
|
801d798: 429a cmp r2, r3
|
|
801d79a: bfde ittt le
|
|
801d79c: 2330 movle r3, #48 ; 0x30
|
|
801d79e: f805 3c01 strble.w r3, [r5, #-1]
|
|
801d7a2: f105 35ff addle.w r5, r5, #4294967295
|
|
801d7a6: ebac 0305 sub.w r3, ip, r5
|
|
801d7aa: 6123 str r3, [r4, #16]
|
|
801d7ac: f8cd 8000 str.w r8, [sp]
|
|
801d7b0: 463b mov r3, r7
|
|
801d7b2: aa03 add r2, sp, #12
|
|
801d7b4: 4621 mov r1, r4
|
|
801d7b6: 4630 mov r0, r6
|
|
801d7b8: f7ff fef6 bl 801d5a8 <_printf_common>
|
|
801d7bc: 3001 adds r0, #1
|
|
801d7be: d14d bne.n 801d85c <_printf_i+0x1c8>
|
|
801d7c0: f04f 30ff mov.w r0, #4294967295
|
|
801d7c4: b005 add sp, #20
|
|
801d7c6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
801d7ca: 4839 ldr r0, [pc, #228] ; (801d8b0 <_printf_i+0x21c>)
|
|
801d7cc: f884 1045 strb.w r1, [r4, #69] ; 0x45
|
|
801d7d0: 6813 ldr r3, [r2, #0]
|
|
801d7d2: 6821 ldr r1, [r4, #0]
|
|
801d7d4: 1d1d adds r5, r3, #4
|
|
801d7d6: 681b ldr r3, [r3, #0]
|
|
801d7d8: 6015 str r5, [r2, #0]
|
|
801d7da: 060a lsls r2, r1, #24
|
|
801d7dc: d50b bpl.n 801d7f6 <_printf_i+0x162>
|
|
801d7de: 07ca lsls r2, r1, #31
|
|
801d7e0: bf44 itt mi
|
|
801d7e2: f041 0120 orrmi.w r1, r1, #32
|
|
801d7e6: 6021 strmi r1, [r4, #0]
|
|
801d7e8: b91b cbnz r3, 801d7f2 <_printf_i+0x15e>
|
|
801d7ea: 6822 ldr r2, [r4, #0]
|
|
801d7ec: f022 0220 bic.w r2, r2, #32
|
|
801d7f0: 6022 str r2, [r4, #0]
|
|
801d7f2: 2210 movs r2, #16
|
|
801d7f4: e7b7 b.n 801d766 <_printf_i+0xd2>
|
|
801d7f6: 064d lsls r5, r1, #25
|
|
801d7f8: bf48 it mi
|
|
801d7fa: b29b uxthmi r3, r3
|
|
801d7fc: e7ef b.n 801d7de <_printf_i+0x14a>
|
|
801d7fe: 4665 mov r5, ip
|
|
801d800: fbb3 f1f2 udiv r1, r3, r2
|
|
801d804: fb02 3311 mls r3, r2, r1, r3
|
|
801d808: 5cc3 ldrb r3, [r0, r3]
|
|
801d80a: f805 3d01 strb.w r3, [r5, #-1]!
|
|
801d80e: 460b mov r3, r1
|
|
801d810: 2900 cmp r1, #0
|
|
801d812: d1f5 bne.n 801d800 <_printf_i+0x16c>
|
|
801d814: e7b9 b.n 801d78a <_printf_i+0xf6>
|
|
801d816: 6813 ldr r3, [r2, #0]
|
|
801d818: 6825 ldr r5, [r4, #0]
|
|
801d81a: 6961 ldr r1, [r4, #20]
|
|
801d81c: 1d18 adds r0, r3, #4
|
|
801d81e: 6010 str r0, [r2, #0]
|
|
801d820: 0628 lsls r0, r5, #24
|
|
801d822: 681b ldr r3, [r3, #0]
|
|
801d824: d501 bpl.n 801d82a <_printf_i+0x196>
|
|
801d826: 6019 str r1, [r3, #0]
|
|
801d828: e002 b.n 801d830 <_printf_i+0x19c>
|
|
801d82a: 066a lsls r2, r5, #25
|
|
801d82c: d5fb bpl.n 801d826 <_printf_i+0x192>
|
|
801d82e: 8019 strh r1, [r3, #0]
|
|
801d830: 2300 movs r3, #0
|
|
801d832: 6123 str r3, [r4, #16]
|
|
801d834: 4665 mov r5, ip
|
|
801d836: e7b9 b.n 801d7ac <_printf_i+0x118>
|
|
801d838: 6813 ldr r3, [r2, #0]
|
|
801d83a: 1d19 adds r1, r3, #4
|
|
801d83c: 6011 str r1, [r2, #0]
|
|
801d83e: 681d ldr r5, [r3, #0]
|
|
801d840: 6862 ldr r2, [r4, #4]
|
|
801d842: 2100 movs r1, #0
|
|
801d844: 4628 mov r0, r5
|
|
801d846: f7e2 fce3 bl 8000210 <memchr>
|
|
801d84a: b108 cbz r0, 801d850 <_printf_i+0x1bc>
|
|
801d84c: 1b40 subs r0, r0, r5
|
|
801d84e: 6060 str r0, [r4, #4]
|
|
801d850: 6863 ldr r3, [r4, #4]
|
|
801d852: 6123 str r3, [r4, #16]
|
|
801d854: 2300 movs r3, #0
|
|
801d856: f884 3043 strb.w r3, [r4, #67] ; 0x43
|
|
801d85a: e7a7 b.n 801d7ac <_printf_i+0x118>
|
|
801d85c: 6923 ldr r3, [r4, #16]
|
|
801d85e: 462a mov r2, r5
|
|
801d860: 4639 mov r1, r7
|
|
801d862: 4630 mov r0, r6
|
|
801d864: 47c0 blx r8
|
|
801d866: 3001 adds r0, #1
|
|
801d868: d0aa beq.n 801d7c0 <_printf_i+0x12c>
|
|
801d86a: 6823 ldr r3, [r4, #0]
|
|
801d86c: 079b lsls r3, r3, #30
|
|
801d86e: d413 bmi.n 801d898 <_printf_i+0x204>
|
|
801d870: 68e0 ldr r0, [r4, #12]
|
|
801d872: 9b03 ldr r3, [sp, #12]
|
|
801d874: 4298 cmp r0, r3
|
|
801d876: bfb8 it lt
|
|
801d878: 4618 movlt r0, r3
|
|
801d87a: e7a3 b.n 801d7c4 <_printf_i+0x130>
|
|
801d87c: 2301 movs r3, #1
|
|
801d87e: 464a mov r2, r9
|
|
801d880: 4639 mov r1, r7
|
|
801d882: 4630 mov r0, r6
|
|
801d884: 47c0 blx r8
|
|
801d886: 3001 adds r0, #1
|
|
801d888: d09a beq.n 801d7c0 <_printf_i+0x12c>
|
|
801d88a: 3501 adds r5, #1
|
|
801d88c: 68e3 ldr r3, [r4, #12]
|
|
801d88e: 9a03 ldr r2, [sp, #12]
|
|
801d890: 1a9b subs r3, r3, r2
|
|
801d892: 42ab cmp r3, r5
|
|
801d894: dcf2 bgt.n 801d87c <_printf_i+0x1e8>
|
|
801d896: e7eb b.n 801d870 <_printf_i+0x1dc>
|
|
801d898: 2500 movs r5, #0
|
|
801d89a: f104 0919 add.w r9, r4, #25
|
|
801d89e: e7f5 b.n 801d88c <_printf_i+0x1f8>
|
|
801d8a0: 2b00 cmp r3, #0
|
|
801d8a2: d1ac bne.n 801d7fe <_printf_i+0x16a>
|
|
801d8a4: 7803 ldrb r3, [r0, #0]
|
|
801d8a6: f884 3042 strb.w r3, [r4, #66] ; 0x42
|
|
801d8aa: f104 0542 add.w r5, r4, #66 ; 0x42
|
|
801d8ae: e76c b.n 801d78a <_printf_i+0xf6>
|
|
801d8b0: 08022efd .word 0x08022efd
|
|
801d8b4: 08022f0e .word 0x08022f0e
|
|
|
|
0801d8b8 <_sbrk_r>:
|
|
801d8b8: b538 push {r3, r4, r5, lr}
|
|
801d8ba: 4c06 ldr r4, [pc, #24] ; (801d8d4 <_sbrk_r+0x1c>)
|
|
801d8bc: 2300 movs r3, #0
|
|
801d8be: 4605 mov r5, r0
|
|
801d8c0: 4608 mov r0, r1
|
|
801d8c2: 6023 str r3, [r4, #0]
|
|
801d8c4: f7e7 fc74 bl 80051b0 <_sbrk>
|
|
801d8c8: 1c43 adds r3, r0, #1
|
|
801d8ca: d102 bne.n 801d8d2 <_sbrk_r+0x1a>
|
|
801d8cc: 6823 ldr r3, [r4, #0]
|
|
801d8ce: b103 cbz r3, 801d8d2 <_sbrk_r+0x1a>
|
|
801d8d0: 602b str r3, [r5, #0]
|
|
801d8d2: bd38 pop {r3, r4, r5, pc}
|
|
801d8d4: 2000f840 .word 0x2000f840
|
|
|
|
0801d8d8 <__sread>:
|
|
801d8d8: b510 push {r4, lr}
|
|
801d8da: 460c mov r4, r1
|
|
801d8dc: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801d8e0: f000 fa6e bl 801ddc0 <_read_r>
|
|
801d8e4: 2800 cmp r0, #0
|
|
801d8e6: bfab itete ge
|
|
801d8e8: 6d63 ldrge r3, [r4, #84] ; 0x54
|
|
801d8ea: 89a3 ldrhlt r3, [r4, #12]
|
|
801d8ec: 181b addge r3, r3, r0
|
|
801d8ee: f423 5380 biclt.w r3, r3, #4096 ; 0x1000
|
|
801d8f2: bfac ite ge
|
|
801d8f4: 6563 strge r3, [r4, #84] ; 0x54
|
|
801d8f6: 81a3 strhlt r3, [r4, #12]
|
|
801d8f8: bd10 pop {r4, pc}
|
|
|
|
0801d8fa <__swrite>:
|
|
801d8fa: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801d8fe: 461f mov r7, r3
|
|
801d900: 898b ldrh r3, [r1, #12]
|
|
801d902: 05db lsls r3, r3, #23
|
|
801d904: 4605 mov r5, r0
|
|
801d906: 460c mov r4, r1
|
|
801d908: 4616 mov r6, r2
|
|
801d90a: d505 bpl.n 801d918 <__swrite+0x1e>
|
|
801d90c: 2302 movs r3, #2
|
|
801d90e: 2200 movs r2, #0
|
|
801d910: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801d914: f000 f9b6 bl 801dc84 <_lseek_r>
|
|
801d918: 89a3 ldrh r3, [r4, #12]
|
|
801d91a: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
801d91e: f423 5380 bic.w r3, r3, #4096 ; 0x1000
|
|
801d922: 81a3 strh r3, [r4, #12]
|
|
801d924: 4632 mov r2, r6
|
|
801d926: 463b mov r3, r7
|
|
801d928: 4628 mov r0, r5
|
|
801d92a: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
801d92e: f000 b869 b.w 801da04 <_write_r>
|
|
|
|
0801d932 <__sseek>:
|
|
801d932: b510 push {r4, lr}
|
|
801d934: 460c mov r4, r1
|
|
801d936: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801d93a: f000 f9a3 bl 801dc84 <_lseek_r>
|
|
801d93e: 1c43 adds r3, r0, #1
|
|
801d940: 89a3 ldrh r3, [r4, #12]
|
|
801d942: bf15 itete ne
|
|
801d944: 6560 strne r0, [r4, #84] ; 0x54
|
|
801d946: f423 5380 biceq.w r3, r3, #4096 ; 0x1000
|
|
801d94a: f443 5380 orrne.w r3, r3, #4096 ; 0x1000
|
|
801d94e: 81a3 strheq r3, [r4, #12]
|
|
801d950: bf18 it ne
|
|
801d952: 81a3 strhne r3, [r4, #12]
|
|
801d954: bd10 pop {r4, pc}
|
|
|
|
0801d956 <__sclose>:
|
|
801d956: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801d95a: f000 b8d3 b.w 801db04 <_close_r>
|
|
...
|
|
|
|
0801d960 <__swbuf_r>:
|
|
801d960: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801d962: 460e mov r6, r1
|
|
801d964: 4614 mov r4, r2
|
|
801d966: 4605 mov r5, r0
|
|
801d968: b118 cbz r0, 801d972 <__swbuf_r+0x12>
|
|
801d96a: 6983 ldr r3, [r0, #24]
|
|
801d96c: b90b cbnz r3, 801d972 <__swbuf_r+0x12>
|
|
801d96e: f7ff fa4f bl 801ce10 <__sinit>
|
|
801d972: 4b21 ldr r3, [pc, #132] ; (801d9f8 <__swbuf_r+0x98>)
|
|
801d974: 429c cmp r4, r3
|
|
801d976: d12a bne.n 801d9ce <__swbuf_r+0x6e>
|
|
801d978: 686c ldr r4, [r5, #4]
|
|
801d97a: 69a3 ldr r3, [r4, #24]
|
|
801d97c: 60a3 str r3, [r4, #8]
|
|
801d97e: 89a3 ldrh r3, [r4, #12]
|
|
801d980: 071a lsls r2, r3, #28
|
|
801d982: d52e bpl.n 801d9e2 <__swbuf_r+0x82>
|
|
801d984: 6923 ldr r3, [r4, #16]
|
|
801d986: b363 cbz r3, 801d9e2 <__swbuf_r+0x82>
|
|
801d988: 6923 ldr r3, [r4, #16]
|
|
801d98a: 6820 ldr r0, [r4, #0]
|
|
801d98c: 1ac0 subs r0, r0, r3
|
|
801d98e: 6963 ldr r3, [r4, #20]
|
|
801d990: b2f6 uxtb r6, r6
|
|
801d992: 4283 cmp r3, r0
|
|
801d994: 4637 mov r7, r6
|
|
801d996: dc04 bgt.n 801d9a2 <__swbuf_r+0x42>
|
|
801d998: 4621 mov r1, r4
|
|
801d99a: 4628 mov r0, r5
|
|
801d99c: f000 f948 bl 801dc30 <_fflush_r>
|
|
801d9a0: bb28 cbnz r0, 801d9ee <__swbuf_r+0x8e>
|
|
801d9a2: 68a3 ldr r3, [r4, #8]
|
|
801d9a4: 3b01 subs r3, #1
|
|
801d9a6: 60a3 str r3, [r4, #8]
|
|
801d9a8: 6823 ldr r3, [r4, #0]
|
|
801d9aa: 1c5a adds r2, r3, #1
|
|
801d9ac: 6022 str r2, [r4, #0]
|
|
801d9ae: 701e strb r6, [r3, #0]
|
|
801d9b0: 6963 ldr r3, [r4, #20]
|
|
801d9b2: 3001 adds r0, #1
|
|
801d9b4: 4283 cmp r3, r0
|
|
801d9b6: d004 beq.n 801d9c2 <__swbuf_r+0x62>
|
|
801d9b8: 89a3 ldrh r3, [r4, #12]
|
|
801d9ba: 07db lsls r3, r3, #31
|
|
801d9bc: d519 bpl.n 801d9f2 <__swbuf_r+0x92>
|
|
801d9be: 2e0a cmp r6, #10
|
|
801d9c0: d117 bne.n 801d9f2 <__swbuf_r+0x92>
|
|
801d9c2: 4621 mov r1, r4
|
|
801d9c4: 4628 mov r0, r5
|
|
801d9c6: f000 f933 bl 801dc30 <_fflush_r>
|
|
801d9ca: b190 cbz r0, 801d9f2 <__swbuf_r+0x92>
|
|
801d9cc: e00f b.n 801d9ee <__swbuf_r+0x8e>
|
|
801d9ce: 4b0b ldr r3, [pc, #44] ; (801d9fc <__swbuf_r+0x9c>)
|
|
801d9d0: 429c cmp r4, r3
|
|
801d9d2: d101 bne.n 801d9d8 <__swbuf_r+0x78>
|
|
801d9d4: 68ac ldr r4, [r5, #8]
|
|
801d9d6: e7d0 b.n 801d97a <__swbuf_r+0x1a>
|
|
801d9d8: 4b09 ldr r3, [pc, #36] ; (801da00 <__swbuf_r+0xa0>)
|
|
801d9da: 429c cmp r4, r3
|
|
801d9dc: bf08 it eq
|
|
801d9de: 68ec ldreq r4, [r5, #12]
|
|
801d9e0: e7cb b.n 801d97a <__swbuf_r+0x1a>
|
|
801d9e2: 4621 mov r1, r4
|
|
801d9e4: 4628 mov r0, r5
|
|
801d9e6: f000 f81f bl 801da28 <__swsetup_r>
|
|
801d9ea: 2800 cmp r0, #0
|
|
801d9ec: d0cc beq.n 801d988 <__swbuf_r+0x28>
|
|
801d9ee: f04f 37ff mov.w r7, #4294967295
|
|
801d9f2: 4638 mov r0, r7
|
|
801d9f4: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
801d9f6: bf00 nop
|
|
801d9f8: 08022eac .word 0x08022eac
|
|
801d9fc: 08022ecc .word 0x08022ecc
|
|
801da00: 08022e8c .word 0x08022e8c
|
|
|
|
0801da04 <_write_r>:
|
|
801da04: b538 push {r3, r4, r5, lr}
|
|
801da06: 4c07 ldr r4, [pc, #28] ; (801da24 <_write_r+0x20>)
|
|
801da08: 4605 mov r5, r0
|
|
801da0a: 4608 mov r0, r1
|
|
801da0c: 4611 mov r1, r2
|
|
801da0e: 2200 movs r2, #0
|
|
801da10: 6022 str r2, [r4, #0]
|
|
801da12: 461a mov r2, r3
|
|
801da14: f7e7 fb7b bl 800510e <_write>
|
|
801da18: 1c43 adds r3, r0, #1
|
|
801da1a: d102 bne.n 801da22 <_write_r+0x1e>
|
|
801da1c: 6823 ldr r3, [r4, #0]
|
|
801da1e: b103 cbz r3, 801da22 <_write_r+0x1e>
|
|
801da20: 602b str r3, [r5, #0]
|
|
801da22: bd38 pop {r3, r4, r5, pc}
|
|
801da24: 2000f840 .word 0x2000f840
|
|
|
|
0801da28 <__swsetup_r>:
|
|
801da28: 4b32 ldr r3, [pc, #200] ; (801daf4 <__swsetup_r+0xcc>)
|
|
801da2a: b570 push {r4, r5, r6, lr}
|
|
801da2c: 681d ldr r5, [r3, #0]
|
|
801da2e: 4606 mov r6, r0
|
|
801da30: 460c mov r4, r1
|
|
801da32: b125 cbz r5, 801da3e <__swsetup_r+0x16>
|
|
801da34: 69ab ldr r3, [r5, #24]
|
|
801da36: b913 cbnz r3, 801da3e <__swsetup_r+0x16>
|
|
801da38: 4628 mov r0, r5
|
|
801da3a: f7ff f9e9 bl 801ce10 <__sinit>
|
|
801da3e: 4b2e ldr r3, [pc, #184] ; (801daf8 <__swsetup_r+0xd0>)
|
|
801da40: 429c cmp r4, r3
|
|
801da42: d10f bne.n 801da64 <__swsetup_r+0x3c>
|
|
801da44: 686c ldr r4, [r5, #4]
|
|
801da46: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801da4a: b29a uxth r2, r3
|
|
801da4c: 0715 lsls r5, r2, #28
|
|
801da4e: d42c bmi.n 801daaa <__swsetup_r+0x82>
|
|
801da50: 06d0 lsls r0, r2, #27
|
|
801da52: d411 bmi.n 801da78 <__swsetup_r+0x50>
|
|
801da54: 2209 movs r2, #9
|
|
801da56: 6032 str r2, [r6, #0]
|
|
801da58: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
801da5c: 81a3 strh r3, [r4, #12]
|
|
801da5e: f04f 30ff mov.w r0, #4294967295
|
|
801da62: e03e b.n 801dae2 <__swsetup_r+0xba>
|
|
801da64: 4b25 ldr r3, [pc, #148] ; (801dafc <__swsetup_r+0xd4>)
|
|
801da66: 429c cmp r4, r3
|
|
801da68: d101 bne.n 801da6e <__swsetup_r+0x46>
|
|
801da6a: 68ac ldr r4, [r5, #8]
|
|
801da6c: e7eb b.n 801da46 <__swsetup_r+0x1e>
|
|
801da6e: 4b24 ldr r3, [pc, #144] ; (801db00 <__swsetup_r+0xd8>)
|
|
801da70: 429c cmp r4, r3
|
|
801da72: bf08 it eq
|
|
801da74: 68ec ldreq r4, [r5, #12]
|
|
801da76: e7e6 b.n 801da46 <__swsetup_r+0x1e>
|
|
801da78: 0751 lsls r1, r2, #29
|
|
801da7a: d512 bpl.n 801daa2 <__swsetup_r+0x7a>
|
|
801da7c: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
801da7e: b141 cbz r1, 801da92 <__swsetup_r+0x6a>
|
|
801da80: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
801da84: 4299 cmp r1, r3
|
|
801da86: d002 beq.n 801da8e <__swsetup_r+0x66>
|
|
801da88: 4630 mov r0, r6
|
|
801da8a: f7ff fa53 bl 801cf34 <_free_r>
|
|
801da8e: 2300 movs r3, #0
|
|
801da90: 6363 str r3, [r4, #52] ; 0x34
|
|
801da92: 89a3 ldrh r3, [r4, #12]
|
|
801da94: f023 0324 bic.w r3, r3, #36 ; 0x24
|
|
801da98: 81a3 strh r3, [r4, #12]
|
|
801da9a: 2300 movs r3, #0
|
|
801da9c: 6063 str r3, [r4, #4]
|
|
801da9e: 6923 ldr r3, [r4, #16]
|
|
801daa0: 6023 str r3, [r4, #0]
|
|
801daa2: 89a3 ldrh r3, [r4, #12]
|
|
801daa4: f043 0308 orr.w r3, r3, #8
|
|
801daa8: 81a3 strh r3, [r4, #12]
|
|
801daaa: 6923 ldr r3, [r4, #16]
|
|
801daac: b94b cbnz r3, 801dac2 <__swsetup_r+0x9a>
|
|
801daae: 89a3 ldrh r3, [r4, #12]
|
|
801dab0: f403 7320 and.w r3, r3, #640 ; 0x280
|
|
801dab4: f5b3 7f00 cmp.w r3, #512 ; 0x200
|
|
801dab8: d003 beq.n 801dac2 <__swsetup_r+0x9a>
|
|
801daba: 4621 mov r1, r4
|
|
801dabc: 4630 mov r0, r6
|
|
801dabe: f000 f917 bl 801dcf0 <__smakebuf_r>
|
|
801dac2: 89a2 ldrh r2, [r4, #12]
|
|
801dac4: f012 0301 ands.w r3, r2, #1
|
|
801dac8: d00c beq.n 801dae4 <__swsetup_r+0xbc>
|
|
801daca: 2300 movs r3, #0
|
|
801dacc: 60a3 str r3, [r4, #8]
|
|
801dace: 6963 ldr r3, [r4, #20]
|
|
801dad0: 425b negs r3, r3
|
|
801dad2: 61a3 str r3, [r4, #24]
|
|
801dad4: 6923 ldr r3, [r4, #16]
|
|
801dad6: b953 cbnz r3, 801daee <__swsetup_r+0xc6>
|
|
801dad8: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801dadc: f013 0080 ands.w r0, r3, #128 ; 0x80
|
|
801dae0: d1ba bne.n 801da58 <__swsetup_r+0x30>
|
|
801dae2: bd70 pop {r4, r5, r6, pc}
|
|
801dae4: 0792 lsls r2, r2, #30
|
|
801dae6: bf58 it pl
|
|
801dae8: 6963 ldrpl r3, [r4, #20]
|
|
801daea: 60a3 str r3, [r4, #8]
|
|
801daec: e7f2 b.n 801dad4 <__swsetup_r+0xac>
|
|
801daee: 2000 movs r0, #0
|
|
801daf0: e7f7 b.n 801dae2 <__swsetup_r+0xba>
|
|
801daf2: bf00 nop
|
|
801daf4: 20000084 .word 0x20000084
|
|
801daf8: 08022eac .word 0x08022eac
|
|
801dafc: 08022ecc .word 0x08022ecc
|
|
801db00: 08022e8c .word 0x08022e8c
|
|
|
|
0801db04 <_close_r>:
|
|
801db04: b538 push {r3, r4, r5, lr}
|
|
801db06: 4c06 ldr r4, [pc, #24] ; (801db20 <_close_r+0x1c>)
|
|
801db08: 2300 movs r3, #0
|
|
801db0a: 4605 mov r5, r0
|
|
801db0c: 4608 mov r0, r1
|
|
801db0e: 6023 str r3, [r4, #0]
|
|
801db10: f7e7 fb19 bl 8005146 <_close>
|
|
801db14: 1c43 adds r3, r0, #1
|
|
801db16: d102 bne.n 801db1e <_close_r+0x1a>
|
|
801db18: 6823 ldr r3, [r4, #0]
|
|
801db1a: b103 cbz r3, 801db1e <_close_r+0x1a>
|
|
801db1c: 602b str r3, [r5, #0]
|
|
801db1e: bd38 pop {r3, r4, r5, pc}
|
|
801db20: 2000f840 .word 0x2000f840
|
|
|
|
0801db24 <__sflush_r>:
|
|
801db24: 898a ldrh r2, [r1, #12]
|
|
801db26: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
801db2a: 4605 mov r5, r0
|
|
801db2c: 0710 lsls r0, r2, #28
|
|
801db2e: 460c mov r4, r1
|
|
801db30: d458 bmi.n 801dbe4 <__sflush_r+0xc0>
|
|
801db32: 684b ldr r3, [r1, #4]
|
|
801db34: 2b00 cmp r3, #0
|
|
801db36: dc05 bgt.n 801db44 <__sflush_r+0x20>
|
|
801db38: 6c0b ldr r3, [r1, #64] ; 0x40
|
|
801db3a: 2b00 cmp r3, #0
|
|
801db3c: dc02 bgt.n 801db44 <__sflush_r+0x20>
|
|
801db3e: 2000 movs r0, #0
|
|
801db40: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
801db44: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
801db46: 2e00 cmp r6, #0
|
|
801db48: d0f9 beq.n 801db3e <__sflush_r+0x1a>
|
|
801db4a: 2300 movs r3, #0
|
|
801db4c: f412 5280 ands.w r2, r2, #4096 ; 0x1000
|
|
801db50: 682f ldr r7, [r5, #0]
|
|
801db52: 6a21 ldr r1, [r4, #32]
|
|
801db54: 602b str r3, [r5, #0]
|
|
801db56: d032 beq.n 801dbbe <__sflush_r+0x9a>
|
|
801db58: 6d60 ldr r0, [r4, #84] ; 0x54
|
|
801db5a: 89a3 ldrh r3, [r4, #12]
|
|
801db5c: 075a lsls r2, r3, #29
|
|
801db5e: d505 bpl.n 801db6c <__sflush_r+0x48>
|
|
801db60: 6863 ldr r3, [r4, #4]
|
|
801db62: 1ac0 subs r0, r0, r3
|
|
801db64: 6b63 ldr r3, [r4, #52] ; 0x34
|
|
801db66: b10b cbz r3, 801db6c <__sflush_r+0x48>
|
|
801db68: 6c23 ldr r3, [r4, #64] ; 0x40
|
|
801db6a: 1ac0 subs r0, r0, r3
|
|
801db6c: 2300 movs r3, #0
|
|
801db6e: 4602 mov r2, r0
|
|
801db70: 6ae6 ldr r6, [r4, #44] ; 0x2c
|
|
801db72: 6a21 ldr r1, [r4, #32]
|
|
801db74: 4628 mov r0, r5
|
|
801db76: 47b0 blx r6
|
|
801db78: 1c43 adds r3, r0, #1
|
|
801db7a: 89a3 ldrh r3, [r4, #12]
|
|
801db7c: d106 bne.n 801db8c <__sflush_r+0x68>
|
|
801db7e: 6829 ldr r1, [r5, #0]
|
|
801db80: 291d cmp r1, #29
|
|
801db82: d848 bhi.n 801dc16 <__sflush_r+0xf2>
|
|
801db84: 4a29 ldr r2, [pc, #164] ; (801dc2c <__sflush_r+0x108>)
|
|
801db86: 40ca lsrs r2, r1
|
|
801db88: 07d6 lsls r6, r2, #31
|
|
801db8a: d544 bpl.n 801dc16 <__sflush_r+0xf2>
|
|
801db8c: 2200 movs r2, #0
|
|
801db8e: 6062 str r2, [r4, #4]
|
|
801db90: 04d9 lsls r1, r3, #19
|
|
801db92: 6922 ldr r2, [r4, #16]
|
|
801db94: 6022 str r2, [r4, #0]
|
|
801db96: d504 bpl.n 801dba2 <__sflush_r+0x7e>
|
|
801db98: 1c42 adds r2, r0, #1
|
|
801db9a: d101 bne.n 801dba0 <__sflush_r+0x7c>
|
|
801db9c: 682b ldr r3, [r5, #0]
|
|
801db9e: b903 cbnz r3, 801dba2 <__sflush_r+0x7e>
|
|
801dba0: 6560 str r0, [r4, #84] ; 0x54
|
|
801dba2: 6b61 ldr r1, [r4, #52] ; 0x34
|
|
801dba4: 602f str r7, [r5, #0]
|
|
801dba6: 2900 cmp r1, #0
|
|
801dba8: d0c9 beq.n 801db3e <__sflush_r+0x1a>
|
|
801dbaa: f104 0344 add.w r3, r4, #68 ; 0x44
|
|
801dbae: 4299 cmp r1, r3
|
|
801dbb0: d002 beq.n 801dbb8 <__sflush_r+0x94>
|
|
801dbb2: 4628 mov r0, r5
|
|
801dbb4: f7ff f9be bl 801cf34 <_free_r>
|
|
801dbb8: 2000 movs r0, #0
|
|
801dbba: 6360 str r0, [r4, #52] ; 0x34
|
|
801dbbc: e7c0 b.n 801db40 <__sflush_r+0x1c>
|
|
801dbbe: 2301 movs r3, #1
|
|
801dbc0: 4628 mov r0, r5
|
|
801dbc2: 47b0 blx r6
|
|
801dbc4: 1c41 adds r1, r0, #1
|
|
801dbc6: d1c8 bne.n 801db5a <__sflush_r+0x36>
|
|
801dbc8: 682b ldr r3, [r5, #0]
|
|
801dbca: 2b00 cmp r3, #0
|
|
801dbcc: d0c5 beq.n 801db5a <__sflush_r+0x36>
|
|
801dbce: 2b1d cmp r3, #29
|
|
801dbd0: d001 beq.n 801dbd6 <__sflush_r+0xb2>
|
|
801dbd2: 2b16 cmp r3, #22
|
|
801dbd4: d101 bne.n 801dbda <__sflush_r+0xb6>
|
|
801dbd6: 602f str r7, [r5, #0]
|
|
801dbd8: e7b1 b.n 801db3e <__sflush_r+0x1a>
|
|
801dbda: 89a3 ldrh r3, [r4, #12]
|
|
801dbdc: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
801dbe0: 81a3 strh r3, [r4, #12]
|
|
801dbe2: e7ad b.n 801db40 <__sflush_r+0x1c>
|
|
801dbe4: 690f ldr r7, [r1, #16]
|
|
801dbe6: 2f00 cmp r7, #0
|
|
801dbe8: d0a9 beq.n 801db3e <__sflush_r+0x1a>
|
|
801dbea: 0793 lsls r3, r2, #30
|
|
801dbec: 680e ldr r6, [r1, #0]
|
|
801dbee: bf08 it eq
|
|
801dbf0: 694b ldreq r3, [r1, #20]
|
|
801dbf2: 600f str r7, [r1, #0]
|
|
801dbf4: bf18 it ne
|
|
801dbf6: 2300 movne r3, #0
|
|
801dbf8: eba6 0807 sub.w r8, r6, r7
|
|
801dbfc: 608b str r3, [r1, #8]
|
|
801dbfe: f1b8 0f00 cmp.w r8, #0
|
|
801dc02: dd9c ble.n 801db3e <__sflush_r+0x1a>
|
|
801dc04: 4643 mov r3, r8
|
|
801dc06: 463a mov r2, r7
|
|
801dc08: 6a21 ldr r1, [r4, #32]
|
|
801dc0a: 6aa6 ldr r6, [r4, #40] ; 0x28
|
|
801dc0c: 4628 mov r0, r5
|
|
801dc0e: 47b0 blx r6
|
|
801dc10: 2800 cmp r0, #0
|
|
801dc12: dc06 bgt.n 801dc22 <__sflush_r+0xfe>
|
|
801dc14: 89a3 ldrh r3, [r4, #12]
|
|
801dc16: f043 0340 orr.w r3, r3, #64 ; 0x40
|
|
801dc1a: 81a3 strh r3, [r4, #12]
|
|
801dc1c: f04f 30ff mov.w r0, #4294967295
|
|
801dc20: e78e b.n 801db40 <__sflush_r+0x1c>
|
|
801dc22: 4407 add r7, r0
|
|
801dc24: eba8 0800 sub.w r8, r8, r0
|
|
801dc28: e7e9 b.n 801dbfe <__sflush_r+0xda>
|
|
801dc2a: bf00 nop
|
|
801dc2c: 20400001 .word 0x20400001
|
|
|
|
0801dc30 <_fflush_r>:
|
|
801dc30: b538 push {r3, r4, r5, lr}
|
|
801dc32: 690b ldr r3, [r1, #16]
|
|
801dc34: 4605 mov r5, r0
|
|
801dc36: 460c mov r4, r1
|
|
801dc38: b1db cbz r3, 801dc72 <_fflush_r+0x42>
|
|
801dc3a: b118 cbz r0, 801dc44 <_fflush_r+0x14>
|
|
801dc3c: 6983 ldr r3, [r0, #24]
|
|
801dc3e: b90b cbnz r3, 801dc44 <_fflush_r+0x14>
|
|
801dc40: f7ff f8e6 bl 801ce10 <__sinit>
|
|
801dc44: 4b0c ldr r3, [pc, #48] ; (801dc78 <_fflush_r+0x48>)
|
|
801dc46: 429c cmp r4, r3
|
|
801dc48: d109 bne.n 801dc5e <_fflush_r+0x2e>
|
|
801dc4a: 686c ldr r4, [r5, #4]
|
|
801dc4c: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801dc50: b17b cbz r3, 801dc72 <_fflush_r+0x42>
|
|
801dc52: 4621 mov r1, r4
|
|
801dc54: 4628 mov r0, r5
|
|
801dc56: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
801dc5a: f7ff bf63 b.w 801db24 <__sflush_r>
|
|
801dc5e: 4b07 ldr r3, [pc, #28] ; (801dc7c <_fflush_r+0x4c>)
|
|
801dc60: 429c cmp r4, r3
|
|
801dc62: d101 bne.n 801dc68 <_fflush_r+0x38>
|
|
801dc64: 68ac ldr r4, [r5, #8]
|
|
801dc66: e7f1 b.n 801dc4c <_fflush_r+0x1c>
|
|
801dc68: 4b05 ldr r3, [pc, #20] ; (801dc80 <_fflush_r+0x50>)
|
|
801dc6a: 429c cmp r4, r3
|
|
801dc6c: bf08 it eq
|
|
801dc6e: 68ec ldreq r4, [r5, #12]
|
|
801dc70: e7ec b.n 801dc4c <_fflush_r+0x1c>
|
|
801dc72: 2000 movs r0, #0
|
|
801dc74: bd38 pop {r3, r4, r5, pc}
|
|
801dc76: bf00 nop
|
|
801dc78: 08022eac .word 0x08022eac
|
|
801dc7c: 08022ecc .word 0x08022ecc
|
|
801dc80: 08022e8c .word 0x08022e8c
|
|
|
|
0801dc84 <_lseek_r>:
|
|
801dc84: b538 push {r3, r4, r5, lr}
|
|
801dc86: 4c07 ldr r4, [pc, #28] ; (801dca4 <_lseek_r+0x20>)
|
|
801dc88: 4605 mov r5, r0
|
|
801dc8a: 4608 mov r0, r1
|
|
801dc8c: 4611 mov r1, r2
|
|
801dc8e: 2200 movs r2, #0
|
|
801dc90: 6022 str r2, [r4, #0]
|
|
801dc92: 461a mov r2, r3
|
|
801dc94: f7e7 fa7e bl 8005194 <_lseek>
|
|
801dc98: 1c43 adds r3, r0, #1
|
|
801dc9a: d102 bne.n 801dca2 <_lseek_r+0x1e>
|
|
801dc9c: 6823 ldr r3, [r4, #0]
|
|
801dc9e: b103 cbz r3, 801dca2 <_lseek_r+0x1e>
|
|
801dca0: 602b str r3, [r5, #0]
|
|
801dca2: bd38 pop {r3, r4, r5, pc}
|
|
801dca4: 2000f840 .word 0x2000f840
|
|
|
|
0801dca8 <__swhatbuf_r>:
|
|
801dca8: b570 push {r4, r5, r6, lr}
|
|
801dcaa: 460e mov r6, r1
|
|
801dcac: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
801dcb0: 2900 cmp r1, #0
|
|
801dcb2: b096 sub sp, #88 ; 0x58
|
|
801dcb4: 4614 mov r4, r2
|
|
801dcb6: 461d mov r5, r3
|
|
801dcb8: da07 bge.n 801dcca <__swhatbuf_r+0x22>
|
|
801dcba: 2300 movs r3, #0
|
|
801dcbc: 602b str r3, [r5, #0]
|
|
801dcbe: 89b3 ldrh r3, [r6, #12]
|
|
801dcc0: 061a lsls r2, r3, #24
|
|
801dcc2: d410 bmi.n 801dce6 <__swhatbuf_r+0x3e>
|
|
801dcc4: f44f 6380 mov.w r3, #1024 ; 0x400
|
|
801dcc8: e00e b.n 801dce8 <__swhatbuf_r+0x40>
|
|
801dcca: 466a mov r2, sp
|
|
801dccc: f000 f88a bl 801dde4 <_fstat_r>
|
|
801dcd0: 2800 cmp r0, #0
|
|
801dcd2: dbf2 blt.n 801dcba <__swhatbuf_r+0x12>
|
|
801dcd4: 9a01 ldr r2, [sp, #4]
|
|
801dcd6: f402 4270 and.w r2, r2, #61440 ; 0xf000
|
|
801dcda: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000
|
|
801dcde: 425a negs r2, r3
|
|
801dce0: 415a adcs r2, r3
|
|
801dce2: 602a str r2, [r5, #0]
|
|
801dce4: e7ee b.n 801dcc4 <__swhatbuf_r+0x1c>
|
|
801dce6: 2340 movs r3, #64 ; 0x40
|
|
801dce8: 2000 movs r0, #0
|
|
801dcea: 6023 str r3, [r4, #0]
|
|
801dcec: b016 add sp, #88 ; 0x58
|
|
801dcee: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0801dcf0 <__smakebuf_r>:
|
|
801dcf0: 898b ldrh r3, [r1, #12]
|
|
801dcf2: b573 push {r0, r1, r4, r5, r6, lr}
|
|
801dcf4: 079d lsls r5, r3, #30
|
|
801dcf6: 4606 mov r6, r0
|
|
801dcf8: 460c mov r4, r1
|
|
801dcfa: d507 bpl.n 801dd0c <__smakebuf_r+0x1c>
|
|
801dcfc: f104 0347 add.w r3, r4, #71 ; 0x47
|
|
801dd00: 6023 str r3, [r4, #0]
|
|
801dd02: 6123 str r3, [r4, #16]
|
|
801dd04: 2301 movs r3, #1
|
|
801dd06: 6163 str r3, [r4, #20]
|
|
801dd08: b002 add sp, #8
|
|
801dd0a: bd70 pop {r4, r5, r6, pc}
|
|
801dd0c: ab01 add r3, sp, #4
|
|
801dd0e: 466a mov r2, sp
|
|
801dd10: f7ff ffca bl 801dca8 <__swhatbuf_r>
|
|
801dd14: 9900 ldr r1, [sp, #0]
|
|
801dd16: 4605 mov r5, r0
|
|
801dd18: 4630 mov r0, r6
|
|
801dd1a: f7ff f959 bl 801cfd0 <_malloc_r>
|
|
801dd1e: b948 cbnz r0, 801dd34 <__smakebuf_r+0x44>
|
|
801dd20: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
801dd24: 059a lsls r2, r3, #22
|
|
801dd26: d4ef bmi.n 801dd08 <__smakebuf_r+0x18>
|
|
801dd28: f023 0303 bic.w r3, r3, #3
|
|
801dd2c: f043 0302 orr.w r3, r3, #2
|
|
801dd30: 81a3 strh r3, [r4, #12]
|
|
801dd32: e7e3 b.n 801dcfc <__smakebuf_r+0xc>
|
|
801dd34: 4b0d ldr r3, [pc, #52] ; (801dd6c <__smakebuf_r+0x7c>)
|
|
801dd36: 62b3 str r3, [r6, #40] ; 0x28
|
|
801dd38: 89a3 ldrh r3, [r4, #12]
|
|
801dd3a: 6020 str r0, [r4, #0]
|
|
801dd3c: f043 0380 orr.w r3, r3, #128 ; 0x80
|
|
801dd40: 81a3 strh r3, [r4, #12]
|
|
801dd42: 9b00 ldr r3, [sp, #0]
|
|
801dd44: 6163 str r3, [r4, #20]
|
|
801dd46: 9b01 ldr r3, [sp, #4]
|
|
801dd48: 6120 str r0, [r4, #16]
|
|
801dd4a: b15b cbz r3, 801dd64 <__smakebuf_r+0x74>
|
|
801dd4c: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
801dd50: 4630 mov r0, r6
|
|
801dd52: f000 f859 bl 801de08 <_isatty_r>
|
|
801dd56: b128 cbz r0, 801dd64 <__smakebuf_r+0x74>
|
|
801dd58: 89a3 ldrh r3, [r4, #12]
|
|
801dd5a: f023 0303 bic.w r3, r3, #3
|
|
801dd5e: f043 0301 orr.w r3, r3, #1
|
|
801dd62: 81a3 strh r3, [r4, #12]
|
|
801dd64: 89a3 ldrh r3, [r4, #12]
|
|
801dd66: 431d orrs r5, r3
|
|
801dd68: 81a5 strh r5, [r4, #12]
|
|
801dd6a: e7cd b.n 801dd08 <__smakebuf_r+0x18>
|
|
801dd6c: 0801cdd9 .word 0x0801cdd9
|
|
|
|
0801dd70 <__malloc_lock>:
|
|
801dd70: 4770 bx lr
|
|
|
|
0801dd72 <__malloc_unlock>:
|
|
801dd72: 4770 bx lr
|
|
|
|
0801dd74 <_realloc_r>:
|
|
801dd74: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801dd76: 4607 mov r7, r0
|
|
801dd78: 4614 mov r4, r2
|
|
801dd7a: 460e mov r6, r1
|
|
801dd7c: b921 cbnz r1, 801dd88 <_realloc_r+0x14>
|
|
801dd7e: 4611 mov r1, r2
|
|
801dd80: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
|
|
801dd84: f7ff b924 b.w 801cfd0 <_malloc_r>
|
|
801dd88: b922 cbnz r2, 801dd94 <_realloc_r+0x20>
|
|
801dd8a: f7ff f8d3 bl 801cf34 <_free_r>
|
|
801dd8e: 4625 mov r5, r4
|
|
801dd90: 4628 mov r0, r5
|
|
801dd92: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
801dd94: f000 f848 bl 801de28 <_malloc_usable_size_r>
|
|
801dd98: 42a0 cmp r0, r4
|
|
801dd9a: d20f bcs.n 801ddbc <_realloc_r+0x48>
|
|
801dd9c: 4621 mov r1, r4
|
|
801dd9e: 4638 mov r0, r7
|
|
801dda0: f7ff f916 bl 801cfd0 <_malloc_r>
|
|
801dda4: 4605 mov r5, r0
|
|
801dda6: 2800 cmp r0, #0
|
|
801dda8: d0f2 beq.n 801dd90 <_realloc_r+0x1c>
|
|
801ddaa: 4631 mov r1, r6
|
|
801ddac: 4622 mov r2, r4
|
|
801ddae: f7fe ff56 bl 801cc5e <memcpy>
|
|
801ddb2: 4631 mov r1, r6
|
|
801ddb4: 4638 mov r0, r7
|
|
801ddb6: f7ff f8bd bl 801cf34 <_free_r>
|
|
801ddba: e7e9 b.n 801dd90 <_realloc_r+0x1c>
|
|
801ddbc: 4635 mov r5, r6
|
|
801ddbe: e7e7 b.n 801dd90 <_realloc_r+0x1c>
|
|
|
|
0801ddc0 <_read_r>:
|
|
801ddc0: b538 push {r3, r4, r5, lr}
|
|
801ddc2: 4c07 ldr r4, [pc, #28] ; (801dde0 <_read_r+0x20>)
|
|
801ddc4: 4605 mov r5, r0
|
|
801ddc6: 4608 mov r0, r1
|
|
801ddc8: 4611 mov r1, r2
|
|
801ddca: 2200 movs r2, #0
|
|
801ddcc: 6022 str r2, [r4, #0]
|
|
801ddce: 461a mov r2, r3
|
|
801ddd0: f7e7 f980 bl 80050d4 <_read>
|
|
801ddd4: 1c43 adds r3, r0, #1
|
|
801ddd6: d102 bne.n 801ddde <_read_r+0x1e>
|
|
801ddd8: 6823 ldr r3, [r4, #0]
|
|
801ddda: b103 cbz r3, 801ddde <_read_r+0x1e>
|
|
801dddc: 602b str r3, [r5, #0]
|
|
801ddde: bd38 pop {r3, r4, r5, pc}
|
|
801dde0: 2000f840 .word 0x2000f840
|
|
|
|
0801dde4 <_fstat_r>:
|
|
801dde4: b538 push {r3, r4, r5, lr}
|
|
801dde6: 4c07 ldr r4, [pc, #28] ; (801de04 <_fstat_r+0x20>)
|
|
801dde8: 2300 movs r3, #0
|
|
801ddea: 4605 mov r5, r0
|
|
801ddec: 4608 mov r0, r1
|
|
801ddee: 4611 mov r1, r2
|
|
801ddf0: 6023 str r3, [r4, #0]
|
|
801ddf2: f7e7 f9b4 bl 800515e <_fstat>
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801ddf6: 1c43 adds r3, r0, #1
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801ddf8: d102 bne.n 801de00 <_fstat_r+0x1c>
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801ddfa: 6823 ldr r3, [r4, #0]
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801ddfc: b103 cbz r3, 801de00 <_fstat_r+0x1c>
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801ddfe: 602b str r3, [r5, #0]
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801de00: bd38 pop {r3, r4, r5, pc}
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801de02: bf00 nop
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801de04: 2000f840 .word 0x2000f840
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|
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0801de08 <_isatty_r>:
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801de08: b538 push {r3, r4, r5, lr}
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801de0a: 4c06 ldr r4, [pc, #24] ; (801de24 <_isatty_r+0x1c>)
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801de0c: 2300 movs r3, #0
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801de0e: 4605 mov r5, r0
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801de10: 4608 mov r0, r1
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|
801de12: 6023 str r3, [r4, #0]
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801de14: f7e7 f9b3 bl 800517e <_isatty>
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|
801de18: 1c43 adds r3, r0, #1
|
|
801de1a: d102 bne.n 801de22 <_isatty_r+0x1a>
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|
801de1c: 6823 ldr r3, [r4, #0]
|
|
801de1e: b103 cbz r3, 801de22 <_isatty_r+0x1a>
|
|
801de20: 602b str r3, [r5, #0]
|
|
801de22: bd38 pop {r3, r4, r5, pc}
|
|
801de24: 2000f840 .word 0x2000f840
|
|
|
|
0801de28 <_malloc_usable_size_r>:
|
|
801de28: f851 3c04 ldr.w r3, [r1, #-4]
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|
801de2c: 1f18 subs r0, r3, #4
|
|
801de2e: 2b00 cmp r3, #0
|
|
801de30: bfbc itt lt
|
|
801de32: 580b ldrlt r3, [r1, r0]
|
|
801de34: 18c0 addlt r0, r0, r3
|
|
801de36: 4770 bx lr
|
|
|
|
0801de38 <_init>:
|
|
801de38: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801de3a: bf00 nop
|
|
801de3c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
801de3e: bc08 pop {r3}
|
|
801de40: 469e mov lr, r3
|
|
801de42: 4770 bx lr
|
|
|
|
0801de44 <_fini>:
|
|
801de44: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
801de46: bf00 nop
|
|
801de48: bcf8 pop {r3, r4, r5, r6, r7}
|
|
801de4a: bc08 pop {r3}
|
|
801de4c: 469e mov lr, r3
|
|
801de4e: 4770 bx lr
|