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Space_Invaders/Debug/prog_demo_2021.list
= 1c13bad270 Initial commit 
Fichier de base de M.Juton
2021-03-30 15:04:17 +02:00

33288 lines
1.2 MiB
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prog_demo_2021.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c8 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000c210 080001d0 080001d0 000101d0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00001fe4 0800c3e0 0800c3e0 0001c3e0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800e3c4 0800e3c4 000200b0 2**0
CONTENTS
4 .ARM 00000008 0800e3c4 0800e3c4 0001e3c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800e3cc 0800e3cc 000200b0 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800e3cc 0800e3cc 0001e3cc 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 0800e3d0 0800e3d0 0001e3d0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 000000b0 20000000 0800e3d4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00008a4c 200000b0 0800e484 000200b0 2**2
ALLOC
10 ._user_heap_stack 00000604 20008afc 0800e484 00028afc 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 000200b0 2**0
CONTENTS, READONLY
12 .debug_info 00029de5 00000000 00000000 000200e0 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 000051ee 00000000 00000000 00049ec5 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00002490 00000000 00000000 0004f0b8 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00002208 00000000 00000000 00051548 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 0002df43 00000000 00000000 00053750 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 0001dc92 00000000 00000000 00081693 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 00114119 00000000 00000000 0009f325 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 001b343e 2**0
CONTENTS, READONLY
20 .debug_frame 00009d9c 00000000 00000000 001b34bc 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080001d0 <__do_global_dtors_aux>:
80001d0: b510 push {r4, lr}
80001d2: 4c05 ldr r4, [pc, #20] ; (80001e8 <__do_global_dtors_aux+0x18>)
80001d4: 7823 ldrb r3, [r4, #0]
80001d6: b933 cbnz r3, 80001e6 <__do_global_dtors_aux+0x16>
80001d8: 4b04 ldr r3, [pc, #16] ; (80001ec <__do_global_dtors_aux+0x1c>)
80001da: b113 cbz r3, 80001e2 <__do_global_dtors_aux+0x12>
80001dc: 4804 ldr r0, [pc, #16] ; (80001f0 <__do_global_dtors_aux+0x20>)
80001de: f3af 8000 nop.w
80001e2: 2301 movs r3, #1
80001e4: 7023 strb r3, [r4, #0]
80001e6: bd10 pop {r4, pc}
80001e8: 200000b0 .word 0x200000b0
80001ec: 00000000 .word 0x00000000
80001f0: 0800c3c8 .word 0x0800c3c8
080001f4 <frame_dummy>:
80001f4: b508 push {r3, lr}
80001f6: 4b03 ldr r3, [pc, #12] ; (8000204 <frame_dummy+0x10>)
80001f8: b11b cbz r3, 8000202 <frame_dummy+0xe>
80001fa: 4903 ldr r1, [pc, #12] ; (8000208 <frame_dummy+0x14>)
80001fc: 4803 ldr r0, [pc, #12] ; (800020c <frame_dummy+0x18>)
80001fe: f3af 8000 nop.w
8000202: bd08 pop {r3, pc}
8000204: 00000000 .word 0x00000000
8000208: 200000b4 .word 0x200000b4
800020c: 0800c3c8 .word 0x0800c3c8
08000210 <memchr>:
8000210: f001 01ff and.w r1, r1, #255 ; 0xff
8000214: 2a10 cmp r2, #16
8000216: db2b blt.n 8000270 <memchr+0x60>
8000218: f010 0f07 tst.w r0, #7
800021c: d008 beq.n 8000230 <memchr+0x20>
800021e: f810 3b01 ldrb.w r3, [r0], #1
8000222: 3a01 subs r2, #1
8000224: 428b cmp r3, r1
8000226: d02d beq.n 8000284 <memchr+0x74>
8000228: f010 0f07 tst.w r0, #7
800022c: b342 cbz r2, 8000280 <memchr+0x70>
800022e: d1f6 bne.n 800021e <memchr+0xe>
8000230: b4f0 push {r4, r5, r6, r7}
8000232: ea41 2101 orr.w r1, r1, r1, lsl #8
8000236: ea41 4101 orr.w r1, r1, r1, lsl #16
800023a: f022 0407 bic.w r4, r2, #7
800023e: f07f 0700 mvns.w r7, #0
8000242: 2300 movs r3, #0
8000244: e8f0 5602 ldrd r5, r6, [r0], #8
8000248: 3c08 subs r4, #8
800024a: ea85 0501 eor.w r5, r5, r1
800024e: ea86 0601 eor.w r6, r6, r1
8000252: fa85 f547 uadd8 r5, r5, r7
8000256: faa3 f587 sel r5, r3, r7
800025a: fa86 f647 uadd8 r6, r6, r7
800025e: faa5 f687 sel r6, r5, r7
8000262: b98e cbnz r6, 8000288 <memchr+0x78>
8000264: d1ee bne.n 8000244 <memchr+0x34>
8000266: bcf0 pop {r4, r5, r6, r7}
8000268: f001 01ff and.w r1, r1, #255 ; 0xff
800026c: f002 0207 and.w r2, r2, #7
8000270: b132 cbz r2, 8000280 <memchr+0x70>
8000272: f810 3b01 ldrb.w r3, [r0], #1
8000276: 3a01 subs r2, #1
8000278: ea83 0301 eor.w r3, r3, r1
800027c: b113 cbz r3, 8000284 <memchr+0x74>
800027e: d1f8 bne.n 8000272 <memchr+0x62>
8000280: 2000 movs r0, #0
8000282: 4770 bx lr
8000284: 3801 subs r0, #1
8000286: 4770 bx lr
8000288: 2d00 cmp r5, #0
800028a: bf06 itte eq
800028c: 4635 moveq r5, r6
800028e: 3803 subeq r0, #3
8000290: 3807 subne r0, #7
8000292: f015 0f01 tst.w r5, #1
8000296: d107 bne.n 80002a8 <memchr+0x98>
8000298: 3001 adds r0, #1
800029a: f415 7f80 tst.w r5, #256 ; 0x100
800029e: bf02 ittt eq
80002a0: 3001 addeq r0, #1
80002a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000
80002a6: 3001 addeq r0, #1
80002a8: bcf0 pop {r4, r5, r6, r7}
80002aa: 3801 subs r0, #1
80002ac: 4770 bx lr
80002ae: bf00 nop
080002b0 <__aeabi_uldivmod>:
80002b0: b953 cbnz r3, 80002c8 <__aeabi_uldivmod+0x18>
80002b2: b94a cbnz r2, 80002c8 <__aeabi_uldivmod+0x18>
80002b4: 2900 cmp r1, #0
80002b6: bf08 it eq
80002b8: 2800 cmpeq r0, #0
80002ba: bf1c itt ne
80002bc: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
80002c0: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
80002c4: f000 b972 b.w 80005ac <__aeabi_idiv0>
80002c8: f1ad 0c08 sub.w ip, sp, #8
80002cc: e96d ce04 strd ip, lr, [sp, #-16]!
80002d0: f000 f806 bl 80002e0 <__udivmoddi4>
80002d4: f8dd e004 ldr.w lr, [sp, #4]
80002d8: e9dd 2302 ldrd r2, r3, [sp, #8]
80002dc: b004 add sp, #16
80002de: 4770 bx lr
080002e0 <__udivmoddi4>:
80002e0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80002e4: 9e08 ldr r6, [sp, #32]
80002e6: 4604 mov r4, r0
80002e8: 4688 mov r8, r1
80002ea: 2b00 cmp r3, #0
80002ec: d14b bne.n 8000386 <__udivmoddi4+0xa6>
80002ee: 428a cmp r2, r1
80002f0: 4615 mov r5, r2
80002f2: d967 bls.n 80003c4 <__udivmoddi4+0xe4>
80002f4: fab2 f282 clz r2, r2
80002f8: b14a cbz r2, 800030e <__udivmoddi4+0x2e>
80002fa: f1c2 0720 rsb r7, r2, #32
80002fe: fa01 f302 lsl.w r3, r1, r2
8000302: fa20 f707 lsr.w r7, r0, r7
8000306: 4095 lsls r5, r2
8000308: ea47 0803 orr.w r8, r7, r3
800030c: 4094 lsls r4, r2
800030e: ea4f 4e15 mov.w lr, r5, lsr #16
8000312: 0c23 lsrs r3, r4, #16
8000314: fbb8 f7fe udiv r7, r8, lr
8000318: fa1f fc85 uxth.w ip, r5
800031c: fb0e 8817 mls r8, lr, r7, r8
8000320: ea43 4308 orr.w r3, r3, r8, lsl #16
8000324: fb07 f10c mul.w r1, r7, ip
8000328: 4299 cmp r1, r3
800032a: d909 bls.n 8000340 <__udivmoddi4+0x60>
800032c: 18eb adds r3, r5, r3
800032e: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff
8000332: f080 811b bcs.w 800056c <__udivmoddi4+0x28c>
8000336: 4299 cmp r1, r3
8000338: f240 8118 bls.w 800056c <__udivmoddi4+0x28c>
800033c: 3f02 subs r7, #2
800033e: 442b add r3, r5
8000340: 1a5b subs r3, r3, r1
8000342: b2a4 uxth r4, r4
8000344: fbb3 f0fe udiv r0, r3, lr
8000348: fb0e 3310 mls r3, lr, r0, r3
800034c: ea44 4403 orr.w r4, r4, r3, lsl #16
8000350: fb00 fc0c mul.w ip, r0, ip
8000354: 45a4 cmp ip, r4
8000356: d909 bls.n 800036c <__udivmoddi4+0x8c>
8000358: 192c adds r4, r5, r4
800035a: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
800035e: f080 8107 bcs.w 8000570 <__udivmoddi4+0x290>
8000362: 45a4 cmp ip, r4
8000364: f240 8104 bls.w 8000570 <__udivmoddi4+0x290>
8000368: 3802 subs r0, #2
800036a: 442c add r4, r5
800036c: ea40 4007 orr.w r0, r0, r7, lsl #16
8000370: eba4 040c sub.w r4, r4, ip
8000374: 2700 movs r7, #0
8000376: b11e cbz r6, 8000380 <__udivmoddi4+0xa0>
8000378: 40d4 lsrs r4, r2
800037a: 2300 movs r3, #0
800037c: e9c6 4300 strd r4, r3, [r6]
8000380: 4639 mov r1, r7
8000382: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000386: 428b cmp r3, r1
8000388: d909 bls.n 800039e <__udivmoddi4+0xbe>
800038a: 2e00 cmp r6, #0
800038c: f000 80eb beq.w 8000566 <__udivmoddi4+0x286>
8000390: 2700 movs r7, #0
8000392: e9c6 0100 strd r0, r1, [r6]
8000396: 4638 mov r0, r7
8000398: 4639 mov r1, r7
800039a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800039e: fab3 f783 clz r7, r3
80003a2: 2f00 cmp r7, #0
80003a4: d147 bne.n 8000436 <__udivmoddi4+0x156>
80003a6: 428b cmp r3, r1
80003a8: d302 bcc.n 80003b0 <__udivmoddi4+0xd0>
80003aa: 4282 cmp r2, r0
80003ac: f200 80fa bhi.w 80005a4 <__udivmoddi4+0x2c4>
80003b0: 1a84 subs r4, r0, r2
80003b2: eb61 0303 sbc.w r3, r1, r3
80003b6: 2001 movs r0, #1
80003b8: 4698 mov r8, r3
80003ba: 2e00 cmp r6, #0
80003bc: d0e0 beq.n 8000380 <__udivmoddi4+0xa0>
80003be: e9c6 4800 strd r4, r8, [r6]
80003c2: e7dd b.n 8000380 <__udivmoddi4+0xa0>
80003c4: b902 cbnz r2, 80003c8 <__udivmoddi4+0xe8>
80003c6: deff udf #255 ; 0xff
80003c8: fab2 f282 clz r2, r2
80003cc: 2a00 cmp r2, #0
80003ce: f040 808f bne.w 80004f0 <__udivmoddi4+0x210>
80003d2: 1b49 subs r1, r1, r5
80003d4: ea4f 4e15 mov.w lr, r5, lsr #16
80003d8: fa1f f885 uxth.w r8, r5
80003dc: 2701 movs r7, #1
80003de: fbb1 fcfe udiv ip, r1, lr
80003e2: 0c23 lsrs r3, r4, #16
80003e4: fb0e 111c mls r1, lr, ip, r1
80003e8: ea43 4301 orr.w r3, r3, r1, lsl #16
80003ec: fb08 f10c mul.w r1, r8, ip
80003f0: 4299 cmp r1, r3
80003f2: d907 bls.n 8000404 <__udivmoddi4+0x124>
80003f4: 18eb adds r3, r5, r3
80003f6: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
80003fa: d202 bcs.n 8000402 <__udivmoddi4+0x122>
80003fc: 4299 cmp r1, r3
80003fe: f200 80cd bhi.w 800059c <__udivmoddi4+0x2bc>
8000402: 4684 mov ip, r0
8000404: 1a59 subs r1, r3, r1
8000406: b2a3 uxth r3, r4
8000408: fbb1 f0fe udiv r0, r1, lr
800040c: fb0e 1410 mls r4, lr, r0, r1
8000410: ea43 4404 orr.w r4, r3, r4, lsl #16
8000414: fb08 f800 mul.w r8, r8, r0
8000418: 45a0 cmp r8, r4
800041a: d907 bls.n 800042c <__udivmoddi4+0x14c>
800041c: 192c adds r4, r5, r4
800041e: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
8000422: d202 bcs.n 800042a <__udivmoddi4+0x14a>
8000424: 45a0 cmp r8, r4
8000426: f200 80b6 bhi.w 8000596 <__udivmoddi4+0x2b6>
800042a: 4618 mov r0, r3
800042c: eba4 0408 sub.w r4, r4, r8
8000430: ea40 400c orr.w r0, r0, ip, lsl #16
8000434: e79f b.n 8000376 <__udivmoddi4+0x96>
8000436: f1c7 0c20 rsb ip, r7, #32
800043a: 40bb lsls r3, r7
800043c: fa22 fe0c lsr.w lr, r2, ip
8000440: ea4e 0e03 orr.w lr, lr, r3
8000444: fa01 f407 lsl.w r4, r1, r7
8000448: fa20 f50c lsr.w r5, r0, ip
800044c: fa21 f30c lsr.w r3, r1, ip
8000450: ea4f 481e mov.w r8, lr, lsr #16
8000454: 4325 orrs r5, r4
8000456: fbb3 f9f8 udiv r9, r3, r8
800045a: 0c2c lsrs r4, r5, #16
800045c: fb08 3319 mls r3, r8, r9, r3
8000460: fa1f fa8e uxth.w sl, lr
8000464: ea44 4303 orr.w r3, r4, r3, lsl #16
8000468: fb09 f40a mul.w r4, r9, sl
800046c: 429c cmp r4, r3
800046e: fa02 f207 lsl.w r2, r2, r7
8000472: fa00 f107 lsl.w r1, r0, r7
8000476: d90b bls.n 8000490 <__udivmoddi4+0x1b0>
8000478: eb1e 0303 adds.w r3, lr, r3
800047c: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
8000480: f080 8087 bcs.w 8000592 <__udivmoddi4+0x2b2>
8000484: 429c cmp r4, r3
8000486: f240 8084 bls.w 8000592 <__udivmoddi4+0x2b2>
800048a: f1a9 0902 sub.w r9, r9, #2
800048e: 4473 add r3, lr
8000490: 1b1b subs r3, r3, r4
8000492: b2ad uxth r5, r5
8000494: fbb3 f0f8 udiv r0, r3, r8
8000498: fb08 3310 mls r3, r8, r0, r3
800049c: ea45 4403 orr.w r4, r5, r3, lsl #16
80004a0: fb00 fa0a mul.w sl, r0, sl
80004a4: 45a2 cmp sl, r4
80004a6: d908 bls.n 80004ba <__udivmoddi4+0x1da>
80004a8: eb1e 0404 adds.w r4, lr, r4
80004ac: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
80004b0: d26b bcs.n 800058a <__udivmoddi4+0x2aa>
80004b2: 45a2 cmp sl, r4
80004b4: d969 bls.n 800058a <__udivmoddi4+0x2aa>
80004b6: 3802 subs r0, #2
80004b8: 4474 add r4, lr
80004ba: ea40 4009 orr.w r0, r0, r9, lsl #16
80004be: fba0 8902 umull r8, r9, r0, r2
80004c2: eba4 040a sub.w r4, r4, sl
80004c6: 454c cmp r4, r9
80004c8: 46c2 mov sl, r8
80004ca: 464b mov r3, r9
80004cc: d354 bcc.n 8000578 <__udivmoddi4+0x298>
80004ce: d051 beq.n 8000574 <__udivmoddi4+0x294>
80004d0: 2e00 cmp r6, #0
80004d2: d069 beq.n 80005a8 <__udivmoddi4+0x2c8>
80004d4: ebb1 050a subs.w r5, r1, sl
80004d8: eb64 0403 sbc.w r4, r4, r3
80004dc: fa04 fc0c lsl.w ip, r4, ip
80004e0: 40fd lsrs r5, r7
80004e2: 40fc lsrs r4, r7
80004e4: ea4c 0505 orr.w r5, ip, r5
80004e8: e9c6 5400 strd r5, r4, [r6]
80004ec: 2700 movs r7, #0
80004ee: e747 b.n 8000380 <__udivmoddi4+0xa0>
80004f0: f1c2 0320 rsb r3, r2, #32
80004f4: fa20 f703 lsr.w r7, r0, r3
80004f8: 4095 lsls r5, r2
80004fa: fa01 f002 lsl.w r0, r1, r2
80004fe: fa21 f303 lsr.w r3, r1, r3
8000502: ea4f 4e15 mov.w lr, r5, lsr #16
8000506: 4338 orrs r0, r7
8000508: 0c01 lsrs r1, r0, #16
800050a: fbb3 f7fe udiv r7, r3, lr
800050e: fa1f f885 uxth.w r8, r5
8000512: fb0e 3317 mls r3, lr, r7, r3
8000516: ea41 4103 orr.w r1, r1, r3, lsl #16
800051a: fb07 f308 mul.w r3, r7, r8
800051e: 428b cmp r3, r1
8000520: fa04 f402 lsl.w r4, r4, r2
8000524: d907 bls.n 8000536 <__udivmoddi4+0x256>
8000526: 1869 adds r1, r5, r1
8000528: f107 3cff add.w ip, r7, #4294967295 ; 0xffffffff
800052c: d22f bcs.n 800058e <__udivmoddi4+0x2ae>
800052e: 428b cmp r3, r1
8000530: d92d bls.n 800058e <__udivmoddi4+0x2ae>
8000532: 3f02 subs r7, #2
8000534: 4429 add r1, r5
8000536: 1acb subs r3, r1, r3
8000538: b281 uxth r1, r0
800053a: fbb3 f0fe udiv r0, r3, lr
800053e: fb0e 3310 mls r3, lr, r0, r3
8000542: ea41 4103 orr.w r1, r1, r3, lsl #16
8000546: fb00 f308 mul.w r3, r0, r8
800054a: 428b cmp r3, r1
800054c: d907 bls.n 800055e <__udivmoddi4+0x27e>
800054e: 1869 adds r1, r5, r1
8000550: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
8000554: d217 bcs.n 8000586 <__udivmoddi4+0x2a6>
8000556: 428b cmp r3, r1
8000558: d915 bls.n 8000586 <__udivmoddi4+0x2a6>
800055a: 3802 subs r0, #2
800055c: 4429 add r1, r5
800055e: 1ac9 subs r1, r1, r3
8000560: ea40 4707 orr.w r7, r0, r7, lsl #16
8000564: e73b b.n 80003de <__udivmoddi4+0xfe>
8000566: 4637 mov r7, r6
8000568: 4630 mov r0, r6
800056a: e709 b.n 8000380 <__udivmoddi4+0xa0>
800056c: 4607 mov r7, r0
800056e: e6e7 b.n 8000340 <__udivmoddi4+0x60>
8000570: 4618 mov r0, r3
8000572: e6fb b.n 800036c <__udivmoddi4+0x8c>
8000574: 4541 cmp r1, r8
8000576: d2ab bcs.n 80004d0 <__udivmoddi4+0x1f0>
8000578: ebb8 0a02 subs.w sl, r8, r2
800057c: eb69 020e sbc.w r2, r9, lr
8000580: 3801 subs r0, #1
8000582: 4613 mov r3, r2
8000584: e7a4 b.n 80004d0 <__udivmoddi4+0x1f0>
8000586: 4660 mov r0, ip
8000588: e7e9 b.n 800055e <__udivmoddi4+0x27e>
800058a: 4618 mov r0, r3
800058c: e795 b.n 80004ba <__udivmoddi4+0x1da>
800058e: 4667 mov r7, ip
8000590: e7d1 b.n 8000536 <__udivmoddi4+0x256>
8000592: 4681 mov r9, r0
8000594: e77c b.n 8000490 <__udivmoddi4+0x1b0>
8000596: 3802 subs r0, #2
8000598: 442c add r4, r5
800059a: e747 b.n 800042c <__udivmoddi4+0x14c>
800059c: f1ac 0c02 sub.w ip, ip, #2
80005a0: 442b add r3, r5
80005a2: e72f b.n 8000404 <__udivmoddi4+0x124>
80005a4: 4638 mov r0, r7
80005a6: e708 b.n 80003ba <__udivmoddi4+0xda>
80005a8: 4637 mov r7, r6
80005aa: e6e9 b.n 8000380 <__udivmoddi4+0xa0>
080005ac <__aeabi_idiv0>:
80005ac: 4770 bx lr
80005ae: bf00 nop
080005b0 <vApplicationStackOverflowHook>:
}
/* USER CODE END 2 */
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
80005b0: b480 push {r7}
80005b2: b083 sub sp, #12
80005b4: af00 add r7, sp, #0
80005b6: 6078 str r0, [r7, #4]
80005b8: 6039 str r1, [r7, #0]
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
80005ba: bf00 nop
80005bc: 370c adds r7, #12
80005be: 46bd mov sp, r7
80005c0: f85d 7b04 ldr.w r7, [sp], #4
80005c4: 4770 bx lr
080005c6 <vApplicationMallocFailedHook>:
/* USER CODE END 4 */
/* USER CODE BEGIN 5 */
__weak void vApplicationMallocFailedHook(void)
{
80005c6: b480 push {r7}
80005c8: af00 add r7, sp, #0
demo application. If heap_1.c or heap_2.c are used, then the size of the
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
to query the size of free heap space that remains (although it does not
provide information on how the remaining heap might be fragmented). */
}
80005ca: bf00 nop
80005cc: 46bd mov sp, r7
80005ce: f85d 7b04 ldr.w r7, [sp], #4
80005d2: 4770 bx lr
080005d4 <ft5336_Init>:
* from MCU to FT5336 : ie I2C channel initialization (if required).
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Init(uint16_t DeviceAddr)
{
80005d4: b580 push {r7, lr}
80005d6: b082 sub sp, #8
80005d8: af00 add r7, sp, #0
80005da: 4603 mov r3, r0
80005dc: 80fb strh r3, [r7, #6]
/* Wait at least 200ms after power up before accessing registers
* Trsi timing (Time of starting to report point after resetting) from FT5336GQQ datasheet */
TS_IO_Delay(200);
80005de: 20c8 movs r0, #200 ; 0xc8
80005e0: f001 fe16 bl 8002210 <TS_IO_Delay>
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
80005e4: f000 fa7a bl 8000adc <ft5336_I2C_InitializeIfRequired>
}
80005e8: bf00 nop
80005ea: 3708 adds r7, #8
80005ec: 46bd mov sp, r7
80005ee: bd80 pop {r7, pc}
080005f0 <ft5336_Reset>:
* @note : Not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_Reset(uint16_t DeviceAddr)
{
80005f0: b480 push {r7}
80005f2: b083 sub sp, #12
80005f4: af00 add r7, sp, #0
80005f6: 4603 mov r3, r0
80005f8: 80fb strh r3, [r7, #6]
/* Do nothing */
/* No software reset sequence available in FT5336 IC */
}
80005fa: bf00 nop
80005fc: 370c adds r7, #12
80005fe: 46bd mov sp, r7
8000600: f85d 7b04 ldr.w r7, [sp], #4
8000604: 4770 bx lr
08000606 <ft5336_ReadID>:
* able to read the FT5336 device ID, and verify this is a FT5336.
* @param DeviceAddr: I2C FT5336 Slave address.
* @retval The Device ID (two bytes).
*/
uint16_t ft5336_ReadID(uint16_t DeviceAddr)
{
8000606: b580 push {r7, lr}
8000608: b084 sub sp, #16
800060a: af00 add r7, sp, #0
800060c: 4603 mov r3, r0
800060e: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadId = 0;
8000610: 2300 movs r3, #0
8000612: 737b strb r3, [r7, #13]
uint8_t nbReadAttempts = 0;
8000614: 2300 movs r3, #0
8000616: 73fb strb r3, [r7, #15]
uint8_t bFoundDevice = 0; /* Device not found by default */
8000618: 2300 movs r3, #0
800061a: 73bb strb r3, [r7, #14]
/* Initialize I2C link if needed */
ft5336_I2C_InitializeIfRequired();
800061c: f000 fa5e bl 8000adc <ft5336_I2C_InitializeIfRequired>
/* At maximum 4 attempts to read ID : exit at first finding of the searched device ID */
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000620: 2300 movs r3, #0
8000622: 73fb strb r3, [r7, #15]
8000624: e010 b.n 8000648 <ft5336_ReadID+0x42>
{
/* Read register FT5336_CHIP_ID_REG as DeviceID detection */
ucReadId = TS_IO_Read(DeviceAddr, FT5336_CHIP_ID_REG);
8000626: 88fb ldrh r3, [r7, #6]
8000628: b2db uxtb r3, r3
800062a: 21a8 movs r1, #168 ; 0xa8
800062c: 4618 mov r0, r3
800062e: f001 fdd1 bl 80021d4 <TS_IO_Read>
8000632: 4603 mov r3, r0
8000634: 737b strb r3, [r7, #13]
/* Found the searched device ID ? */
if(ucReadId == FT5336_ID_VALUE)
8000636: 7b7b ldrb r3, [r7, #13]
8000638: b2db uxtb r3, r3
800063a: 2b51 cmp r3, #81 ; 0x51
800063c: d101 bne.n 8000642 <ft5336_ReadID+0x3c>
{
/* Set device as found */
bFoundDevice = 1;
800063e: 2301 movs r3, #1
8000640: 73bb strb r3, [r7, #14]
for(nbReadAttempts = 0; ((nbReadAttempts < 3) && !(bFoundDevice)); nbReadAttempts++)
8000642: 7bfb ldrb r3, [r7, #15]
8000644: 3301 adds r3, #1
8000646: 73fb strb r3, [r7, #15]
8000648: 7bfb ldrb r3, [r7, #15]
800064a: 2b02 cmp r3, #2
800064c: d802 bhi.n 8000654 <ft5336_ReadID+0x4e>
800064e: 7bbb ldrb r3, [r7, #14]
8000650: 2b00 cmp r3, #0
8000652: d0e8 beq.n 8000626 <ft5336_ReadID+0x20>
}
}
/* Return the device ID value */
return (ucReadId);
8000654: 7b7b ldrb r3, [r7, #13]
8000656: b2db uxtb r3, r3
8000658: b29b uxth r3, r3
}
800065a: 4618 mov r0, r3
800065c: 3710 adds r7, #16
800065e: 46bd mov sp, r7
8000660: bd80 pop {r7, pc}
08000662 <ft5336_TS_Start>:
* @brief Configures the touch Screen IC device to start detecting touches
* @param DeviceAddr: Device address on communication Bus (I2C slave address).
* @retval None.
*/
void ft5336_TS_Start(uint16_t DeviceAddr)
{
8000662: b580 push {r7, lr}
8000664: b082 sub sp, #8
8000666: af00 add r7, sp, #0
8000668: 4603 mov r3, r0
800066a: 80fb strh r3, [r7, #6]
/* Minimum static configuration of FT5336 */
FT5336_ASSERT(ft5336_TS_Configure(DeviceAddr));
800066c: 88fb ldrh r3, [r7, #6]
800066e: 4618 mov r0, r3
8000670: f000 fa44 bl 8000afc <ft5336_TS_Configure>
/* By default set FT5336 IC in Polling mode : no INT generation on FT5336 for new touch available */
/* Note TS_INT is active low */
ft5336_TS_DisableIT(DeviceAddr);
8000674: 88fb ldrh r3, [r7, #6]
8000676: 4618 mov r0, r3
8000678: f000 f932 bl 80008e0 <ft5336_TS_DisableIT>
}
800067c: bf00 nop
800067e: 3708 adds r7, #8
8000680: 46bd mov sp, r7
8000682: bd80 pop {r7, pc}
08000684 <ft5336_TS_DetectTouch>:
* variables).
* @param DeviceAddr: Device address on communication Bus.
* @retval : Number of active touches detected (can be 0, 1 or 2).
*/
uint8_t ft5336_TS_DetectTouch(uint16_t DeviceAddr)
{
8000684: b580 push {r7, lr}
8000686: b084 sub sp, #16
8000688: af00 add r7, sp, #0
800068a: 4603 mov r3, r0
800068c: 80fb strh r3, [r7, #6]
volatile uint8_t nbTouch = 0;
800068e: 2300 movs r3, #0
8000690: 73fb strb r3, [r7, #15]
/* Read register FT5336_TD_STAT_REG to check number of touches detection */
nbTouch = TS_IO_Read(DeviceAddr, FT5336_TD_STAT_REG);
8000692: 88fb ldrh r3, [r7, #6]
8000694: b2db uxtb r3, r3
8000696: 2102 movs r1, #2
8000698: 4618 mov r0, r3
800069a: f001 fd9b bl 80021d4 <TS_IO_Read>
800069e: 4603 mov r3, r0
80006a0: 73fb strb r3, [r7, #15]
nbTouch &= FT5336_TD_STAT_MASK;
80006a2: 7bfb ldrb r3, [r7, #15]
80006a4: b2db uxtb r3, r3
80006a6: f003 030f and.w r3, r3, #15
80006aa: b2db uxtb r3, r3
80006ac: 73fb strb r3, [r7, #15]
if(nbTouch > FT5336_MAX_DETECTABLE_TOUCH)
80006ae: 7bfb ldrb r3, [r7, #15]
80006b0: b2db uxtb r3, r3
80006b2: 2b05 cmp r3, #5
80006b4: d901 bls.n 80006ba <ft5336_TS_DetectTouch+0x36>
{
/* If invalid number of touch detected, set it to zero */
nbTouch = 0;
80006b6: 2300 movs r3, #0
80006b8: 73fb strb r3, [r7, #15]
}
/* Update ft5336 driver internal global : current number of active touches */
ft5336_handle.currActiveTouchNb = nbTouch;
80006ba: 7bfb ldrb r3, [r7, #15]
80006bc: b2da uxtb r2, r3
80006be: 4b05 ldr r3, [pc, #20] ; (80006d4 <ft5336_TS_DetectTouch+0x50>)
80006c0: 705a strb r2, [r3, #1]
/* Reset current active touch index on which to work on */
ft5336_handle.currActiveTouchIdx = 0;
80006c2: 4b04 ldr r3, [pc, #16] ; (80006d4 <ft5336_TS_DetectTouch+0x50>)
80006c4: 2200 movs r2, #0
80006c6: 709a strb r2, [r3, #2]
return(nbTouch);
80006c8: 7bfb ldrb r3, [r7, #15]
80006ca: b2db uxtb r3, r3
}
80006cc: 4618 mov r0, r3
80006ce: 3710 adds r7, #16
80006d0: 46bd mov sp, r7
80006d2: bd80 pop {r7, pc}
80006d4: 200000cc .word 0x200000cc
080006d8 <ft5336_TS_GetXY>:
* @param X: Pointer to X position value
* @param Y: Pointer to Y position value
* @retval None.
*/
void ft5336_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
{
80006d8: b580 push {r7, lr}
80006da: b086 sub sp, #24
80006dc: af00 add r7, sp, #0
80006de: 4603 mov r3, r0
80006e0: 60b9 str r1, [r7, #8]
80006e2: 607a str r2, [r7, #4]
80006e4: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
80006e6: 2300 movs r3, #0
80006e8: 74fb strb r3, [r7, #19]
static uint16_t coord;
uint8_t regAddressXLow = 0;
80006ea: 2300 movs r3, #0
80006ec: 75fb strb r3, [r7, #23]
uint8_t regAddressXHigh = 0;
80006ee: 2300 movs r3, #0
80006f0: 75bb strb r3, [r7, #22]
uint8_t regAddressYLow = 0;
80006f2: 2300 movs r3, #0
80006f4: 757b strb r3, [r7, #21]
uint8_t regAddressYHigh = 0;
80006f6: 2300 movs r3, #0
80006f8: 753b strb r3, [r7, #20]
if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb)
80006fa: 4b6d ldr r3, [pc, #436] ; (80008b0 <ft5336_TS_GetXY+0x1d8>)
80006fc: 789a ldrb r2, [r3, #2]
80006fe: 4b6c ldr r3, [pc, #432] ; (80008b0 <ft5336_TS_GetXY+0x1d8>)
8000700: 785b ldrb r3, [r3, #1]
8000702: 429a cmp r2, r3
8000704: f080 80cf bcs.w 80008a6 <ft5336_TS_GetXY+0x1ce>
{
switch(ft5336_handle.currActiveTouchIdx)
8000708: 4b69 ldr r3, [pc, #420] ; (80008b0 <ft5336_TS_GetXY+0x1d8>)
800070a: 789b ldrb r3, [r3, #2]
800070c: 2b09 cmp r3, #9
800070e: d871 bhi.n 80007f4 <ft5336_TS_GetXY+0x11c>
8000710: a201 add r2, pc, #4 ; (adr r2, 8000718 <ft5336_TS_GetXY+0x40>)
8000712: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8000716: bf00 nop
8000718: 08000741 .word 0x08000741
800071c: 08000753 .word 0x08000753
8000720: 08000765 .word 0x08000765
8000724: 08000777 .word 0x08000777
8000728: 08000789 .word 0x08000789
800072c: 0800079b .word 0x0800079b
8000730: 080007ad .word 0x080007ad
8000734: 080007bf .word 0x080007bf
8000738: 080007d1 .word 0x080007d1
800073c: 080007e3 .word 0x080007e3
{
case 0 :
regAddressXLow = FT5336_P1_XL_REG;
8000740: 2304 movs r3, #4
8000742: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P1_XH_REG;
8000744: 2303 movs r3, #3
8000746: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P1_YL_REG;
8000748: 2306 movs r3, #6
800074a: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P1_YH_REG;
800074c: 2305 movs r3, #5
800074e: 753b strb r3, [r7, #20]
break;
8000750: e051 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 1 :
regAddressXLow = FT5336_P2_XL_REG;
8000752: 230a movs r3, #10
8000754: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P2_XH_REG;
8000756: 2309 movs r3, #9
8000758: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P2_YL_REG;
800075a: 230c movs r3, #12
800075c: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P2_YH_REG;
800075e: 230b movs r3, #11
8000760: 753b strb r3, [r7, #20]
break;
8000762: e048 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 2 :
regAddressXLow = FT5336_P3_XL_REG;
8000764: 2310 movs r3, #16
8000766: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P3_XH_REG;
8000768: 230f movs r3, #15
800076a: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P3_YL_REG;
800076c: 2312 movs r3, #18
800076e: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P3_YH_REG;
8000770: 2311 movs r3, #17
8000772: 753b strb r3, [r7, #20]
break;
8000774: e03f b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 3 :
regAddressXLow = FT5336_P4_XL_REG;
8000776: 2316 movs r3, #22
8000778: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P4_XH_REG;
800077a: 2315 movs r3, #21
800077c: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P4_YL_REG;
800077e: 2318 movs r3, #24
8000780: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P4_YH_REG;
8000782: 2317 movs r3, #23
8000784: 753b strb r3, [r7, #20]
break;
8000786: e036 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 4 :
regAddressXLow = FT5336_P5_XL_REG;
8000788: 231c movs r3, #28
800078a: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P5_XH_REG;
800078c: 231b movs r3, #27
800078e: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P5_YL_REG;
8000790: 231e movs r3, #30
8000792: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P5_YH_REG;
8000794: 231d movs r3, #29
8000796: 753b strb r3, [r7, #20]
break;
8000798: e02d b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 5 :
regAddressXLow = FT5336_P6_XL_REG;
800079a: 2322 movs r3, #34 ; 0x22
800079c: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P6_XH_REG;
800079e: 2321 movs r3, #33 ; 0x21
80007a0: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P6_YL_REG;
80007a2: 2324 movs r3, #36 ; 0x24
80007a4: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P6_YH_REG;
80007a6: 2323 movs r3, #35 ; 0x23
80007a8: 753b strb r3, [r7, #20]
break;
80007aa: e024 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 6 :
regAddressXLow = FT5336_P7_XL_REG;
80007ac: 2328 movs r3, #40 ; 0x28
80007ae: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P7_XH_REG;
80007b0: 2327 movs r3, #39 ; 0x27
80007b2: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P7_YL_REG;
80007b4: 232a movs r3, #42 ; 0x2a
80007b6: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P7_YH_REG;
80007b8: 2329 movs r3, #41 ; 0x29
80007ba: 753b strb r3, [r7, #20]
break;
80007bc: e01b b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 7 :
regAddressXLow = FT5336_P8_XL_REG;
80007be: 232e movs r3, #46 ; 0x2e
80007c0: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P8_XH_REG;
80007c2: 232d movs r3, #45 ; 0x2d
80007c4: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P8_YL_REG;
80007c6: 2330 movs r3, #48 ; 0x30
80007c8: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P8_YH_REG;
80007ca: 232f movs r3, #47 ; 0x2f
80007cc: 753b strb r3, [r7, #20]
break;
80007ce: e012 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 8 :
regAddressXLow = FT5336_P9_XL_REG;
80007d0: 2334 movs r3, #52 ; 0x34
80007d2: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P9_XH_REG;
80007d4: 2333 movs r3, #51 ; 0x33
80007d6: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P9_YL_REG;
80007d8: 2336 movs r3, #54 ; 0x36
80007da: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P9_YH_REG;
80007dc: 2335 movs r3, #53 ; 0x35
80007de: 753b strb r3, [r7, #20]
break;
80007e0: e009 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
case 9 :
regAddressXLow = FT5336_P10_XL_REG;
80007e2: 233a movs r3, #58 ; 0x3a
80007e4: 75fb strb r3, [r7, #23]
regAddressXHigh = FT5336_P10_XH_REG;
80007e6: 2339 movs r3, #57 ; 0x39
80007e8: 75bb strb r3, [r7, #22]
regAddressYLow = FT5336_P10_YL_REG;
80007ea: 233c movs r3, #60 ; 0x3c
80007ec: 757b strb r3, [r7, #21]
regAddressYHigh = FT5336_P10_YH_REG;
80007ee: 233b movs r3, #59 ; 0x3b
80007f0: 753b strb r3, [r7, #20]
break;
80007f2: e000 b.n 80007f6 <ft5336_TS_GetXY+0x11e>
default :
break;
80007f4: bf00 nop
} /* end switch(ft5336_handle.currActiveTouchIdx) */
/* Read low part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXLow);
80007f6: 89fb ldrh r3, [r7, #14]
80007f8: b2db uxtb r3, r3
80007fa: 7dfa ldrb r2, [r7, #23]
80007fc: 4611 mov r1, r2
80007fe: 4618 mov r0, r3
8000800: f001 fce8 bl 80021d4 <TS_IO_Read>
8000804: 4603 mov r3, r0
8000806: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
8000808: 7cfb ldrb r3, [r7, #19]
800080a: b2db uxtb r3, r3
800080c: b29a uxth r2, r3
800080e: 4b29 ldr r3, [pc, #164] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000810: 801a strh r2, [r3, #0]
/* Read high part of X position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000812: 89fb ldrh r3, [r7, #14]
8000814: b2db uxtb r3, r3
8000816: 7dba ldrb r2, [r7, #22]
8000818: 4611 mov r1, r2
800081a: 4618 mov r0, r3
800081c: f001 fcda bl 80021d4 <TS_IO_Read>
8000820: 4603 mov r3, r0
8000822: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
8000824: 7cfb ldrb r3, [r7, #19]
8000826: b2db uxtb r3, r3
8000828: 021b lsls r3, r3, #8
800082a: f403 6370 and.w r3, r3, #3840 ; 0xf00
800082e: b21a sxth r2, r3
8000830: 4b20 ldr r3, [pc, #128] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000832: 881b ldrh r3, [r3, #0]
8000834: b21b sxth r3, r3
8000836: 4313 orrs r3, r2
8000838: b21b sxth r3, r3
800083a: b29a uxth r2, r3
800083c: 4b1d ldr r3, [pc, #116] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
800083e: 801a strh r2, [r3, #0]
/* Send back ready X position to caller */
*X = coord;
8000840: 4b1c ldr r3, [pc, #112] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000842: 881a ldrh r2, [r3, #0]
8000844: 68bb ldr r3, [r7, #8]
8000846: 801a strh r2, [r3, #0]
/* Read low part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYLow);
8000848: 89fb ldrh r3, [r7, #14]
800084a: b2db uxtb r3, r3
800084c: 7d7a ldrb r2, [r7, #21]
800084e: 4611 mov r1, r2
8000850: 4618 mov r0, r3
8000852: f001 fcbf bl 80021d4 <TS_IO_Read>
8000856: 4603 mov r3, r0
8000858: 74fb strb r3, [r7, #19]
coord = (ucReadData & FT5336_TOUCH_POS_LSB_MASK) >> FT5336_TOUCH_POS_LSB_SHIFT;
800085a: 7cfb ldrb r3, [r7, #19]
800085c: b2db uxtb r3, r3
800085e: b29a uxth r2, r3
8000860: 4b14 ldr r3, [pc, #80] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000862: 801a strh r2, [r3, #0]
/* Read high part of Y position */
ucReadData = TS_IO_Read(DeviceAddr, regAddressYHigh);
8000864: 89fb ldrh r3, [r7, #14]
8000866: b2db uxtb r3, r3
8000868: 7d3a ldrb r2, [r7, #20]
800086a: 4611 mov r1, r2
800086c: 4618 mov r0, r3
800086e: f001 fcb1 bl 80021d4 <TS_IO_Read>
8000872: 4603 mov r3, r0
8000874: 74fb strb r3, [r7, #19]
coord |= ((ucReadData & FT5336_TOUCH_POS_MSB_MASK) >> FT5336_TOUCH_POS_MSB_SHIFT) << 8;
8000876: 7cfb ldrb r3, [r7, #19]
8000878: b2db uxtb r3, r3
800087a: 021b lsls r3, r3, #8
800087c: f403 6370 and.w r3, r3, #3840 ; 0xf00
8000880: b21a sxth r2, r3
8000882: 4b0c ldr r3, [pc, #48] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000884: 881b ldrh r3, [r3, #0]
8000886: b21b sxth r3, r3
8000888: 4313 orrs r3, r2
800088a: b21b sxth r3, r3
800088c: b29a uxth r2, r3
800088e: 4b09 ldr r3, [pc, #36] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000890: 801a strh r2, [r3, #0]
/* Send back ready Y position to caller */
*Y = coord;
8000892: 4b08 ldr r3, [pc, #32] ; (80008b4 <ft5336_TS_GetXY+0x1dc>)
8000894: 881a ldrh r2, [r3, #0]
8000896: 687b ldr r3, [r7, #4]
8000898: 801a strh r2, [r3, #0]
ft5336_handle.currActiveTouchIdx++; /* next call will work on next touch */
800089a: 4b05 ldr r3, [pc, #20] ; (80008b0 <ft5336_TS_GetXY+0x1d8>)
800089c: 789b ldrb r3, [r3, #2]
800089e: 3301 adds r3, #1
80008a0: b2da uxtb r2, r3
80008a2: 4b03 ldr r3, [pc, #12] ; (80008b0 <ft5336_TS_GetXY+0x1d8>)
80008a4: 709a strb r2, [r3, #2]
} /* of if(ft5336_handle.currActiveTouchIdx < ft5336_handle.currActiveTouchNb) */
}
80008a6: bf00 nop
80008a8: 3718 adds r7, #24
80008aa: 46bd mov sp, r7
80008ac: bd80 pop {r7, pc}
80008ae: bf00 nop
80008b0: 200000cc .word 0x200000cc
80008b4: 200000d0 .word 0x200000d0
080008b8 <ft5336_TS_EnableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_EnableIT(uint16_t DeviceAddr)
{
80008b8: b580 push {r7, lr}
80008ba: b084 sub sp, #16
80008bc: af00 add r7, sp, #0
80008be: 4603 mov r3, r0
80008c0: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
80008c2: 2300 movs r3, #0
80008c4: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_TRIGGER & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
80008c6: 2301 movs r3, #1
80008c8: 73fb strb r3, [r7, #15]
/* Set interrupt trigger mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
80008ca: 88fb ldrh r3, [r7, #6]
80008cc: b2db uxtb r3, r3
80008ce: 7bfa ldrb r2, [r7, #15]
80008d0: 21a4 movs r1, #164 ; 0xa4
80008d2: 4618 mov r0, r3
80008d4: f001 fc64 bl 80021a0 <TS_IO_Write>
}
80008d8: bf00 nop
80008da: 3710 adds r7, #16
80008dc: 46bd mov sp, r7
80008de: bd80 pop {r7, pc}
080008e0 <ft5336_TS_DisableIT>:
* connected to MCU as EXTI.
* @param DeviceAddr: Device address on communication Bus (Slave I2C address of FT5336).
* @retval None
*/
void ft5336_TS_DisableIT(uint16_t DeviceAddr)
{
80008e0: b580 push {r7, lr}
80008e2: b084 sub sp, #16
80008e4: af00 add r7, sp, #0
80008e6: 4603 mov r3, r0
80008e8: 80fb strh r3, [r7, #6]
uint8_t regValue = 0;
80008ea: 2300 movs r3, #0
80008ec: 73fb strb r3, [r7, #15]
regValue = (FT5336_G_MODE_INTERRUPT_POLLING & (FT5336_G_MODE_INTERRUPT_MASK >> FT5336_G_MODE_INTERRUPT_SHIFT)) << FT5336_G_MODE_INTERRUPT_SHIFT;
80008ee: 2300 movs r3, #0
80008f0: 73fb strb r3, [r7, #15]
/* Set interrupt polling mode in FT5336_GMODE_REG */
TS_IO_Write(DeviceAddr, FT5336_GMODE_REG, regValue);
80008f2: 88fb ldrh r3, [r7, #6]
80008f4: b2db uxtb r3, r3
80008f6: 7bfa ldrb r2, [r7, #15]
80008f8: 21a4 movs r1, #164 ; 0xa4
80008fa: 4618 mov r0, r3
80008fc: f001 fc50 bl 80021a0 <TS_IO_Write>
}
8000900: bf00 nop
8000902: 3710 adds r7, #16
8000904: 46bd mov sp, r7
8000906: bd80 pop {r7, pc}
08000908 <ft5336_TS_ITStatus>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval TS interrupts status : always return 0 here
*/
uint8_t ft5336_TS_ITStatus(uint16_t DeviceAddr)
{
8000908: b480 push {r7}
800090a: b083 sub sp, #12
800090c: af00 add r7, sp, #0
800090e: 4603 mov r3, r0
8000910: 80fb strh r3, [r7, #6]
/* Always return 0 as feature not applicable to FT5336 */
return 0;
8000912: 2300 movs r3, #0
}
8000914: 4618 mov r0, r3
8000916: 370c adds r7, #12
8000918: 46bd mov sp, r7
800091a: f85d 7b04 ldr.w r7, [sp], #4
800091e: 4770 bx lr
08000920 <ft5336_TS_ClearIT>:
* @note : This feature is not applicable to FT5336.
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @retval None
*/
void ft5336_TS_ClearIT(uint16_t DeviceAddr)
{
8000920: b480 push {r7}
8000922: b083 sub sp, #12
8000924: af00 add r7, sp, #0
8000926: 4603 mov r3, r0
8000928: 80fb strh r3, [r7, #6]
/* Nothing to be done here for FT5336 */
}
800092a: bf00 nop
800092c: 370c adds r7, #12
800092e: 46bd mov sp, r7
8000930: f85d 7b04 ldr.w r7, [sp], #4
8000934: 4770 bx lr
08000936 <ft5336_TS_GetGestureID>:
* @param DeviceAddr: Device address on communication Bus (I2C slave address of FT5336).
* @param pGestureId : Pointer to get last touch gesture Identification.
* @retval None.
*/
void ft5336_TS_GetGestureID(uint16_t DeviceAddr, uint32_t * pGestureId)
{
8000936: b580 push {r7, lr}
8000938: b084 sub sp, #16
800093a: af00 add r7, sp, #0
800093c: 4603 mov r3, r0
800093e: 6039 str r1, [r7, #0]
8000940: 80fb strh r3, [r7, #6]
volatile uint8_t ucReadData = 0;
8000942: 2300 movs r3, #0
8000944: 73fb strb r3, [r7, #15]
ucReadData = TS_IO_Read(DeviceAddr, FT5336_GEST_ID_REG);
8000946: 88fb ldrh r3, [r7, #6]
8000948: b2db uxtb r3, r3
800094a: 2101 movs r1, #1
800094c: 4618 mov r0, r3
800094e: f001 fc41 bl 80021d4 <TS_IO_Read>
8000952: 4603 mov r3, r0
8000954: 73fb strb r3, [r7, #15]
* pGestureId = ucReadData;
8000956: 7bfb ldrb r3, [r7, #15]
8000958: b2db uxtb r3, r3
800095a: 461a mov r2, r3
800095c: 683b ldr r3, [r7, #0]
800095e: 601a str r2, [r3, #0]
}
8000960: bf00 nop
8000962: 3710 adds r7, #16
8000964: 46bd mov sp, r7
8000966: bd80 pop {r7, pc}
08000968 <ft5336_TS_GetTouchInfo>:
void ft5336_TS_GetTouchInfo(uint16_t DeviceAddr,
uint32_t touchIdx,
uint32_t * pWeight,
uint32_t * pArea,
uint32_t * pEvent)
{
8000968: b580 push {r7, lr}
800096a: b086 sub sp, #24
800096c: af00 add r7, sp, #0
800096e: 60b9 str r1, [r7, #8]
8000970: 607a str r2, [r7, #4]
8000972: 603b str r3, [r7, #0]
8000974: 4603 mov r3, r0
8000976: 81fb strh r3, [r7, #14]
volatile uint8_t ucReadData = 0;
8000978: 2300 movs r3, #0
800097a: 753b strb r3, [r7, #20]
uint8_t regAddressXHigh = 0;
800097c: 2300 movs r3, #0
800097e: 75fb strb r3, [r7, #23]
uint8_t regAddressPWeight = 0;
8000980: 2300 movs r3, #0
8000982: 75bb strb r3, [r7, #22]
uint8_t regAddressPMisc = 0;
8000984: 2300 movs r3, #0
8000986: 757b strb r3, [r7, #21]
if(touchIdx < ft5336_handle.currActiveTouchNb)
8000988: 4b4d ldr r3, [pc, #308] ; (8000ac0 <ft5336_TS_GetTouchInfo+0x158>)
800098a: 785b ldrb r3, [r3, #1]
800098c: 461a mov r2, r3
800098e: 68bb ldr r3, [r7, #8]
8000990: 4293 cmp r3, r2
8000992: f080 8090 bcs.w 8000ab6 <ft5336_TS_GetTouchInfo+0x14e>
{
switch(touchIdx)
8000996: 68bb ldr r3, [r7, #8]
8000998: 2b09 cmp r3, #9
800099a: d85d bhi.n 8000a58 <ft5336_TS_GetTouchInfo+0xf0>
800099c: a201 add r2, pc, #4 ; (adr r2, 80009a4 <ft5336_TS_GetTouchInfo+0x3c>)
800099e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80009a2: bf00 nop
80009a4: 080009cd .word 0x080009cd
80009a8: 080009db .word 0x080009db
80009ac: 080009e9 .word 0x080009e9
80009b0: 080009f7 .word 0x080009f7
80009b4: 08000a05 .word 0x08000a05
80009b8: 08000a13 .word 0x08000a13
80009bc: 08000a21 .word 0x08000a21
80009c0: 08000a2f .word 0x08000a2f
80009c4: 08000a3d .word 0x08000a3d
80009c8: 08000a4b .word 0x08000a4b
{
case 0 :
regAddressXHigh = FT5336_P1_XH_REG;
80009cc: 2303 movs r3, #3
80009ce: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P1_WEIGHT_REG;
80009d0: 2307 movs r3, #7
80009d2: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P1_MISC_REG;
80009d4: 2308 movs r3, #8
80009d6: 757b strb r3, [r7, #21]
break;
80009d8: e03f b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 1 :
regAddressXHigh = FT5336_P2_XH_REG;
80009da: 2309 movs r3, #9
80009dc: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P2_WEIGHT_REG;
80009de: 230d movs r3, #13
80009e0: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P2_MISC_REG;
80009e2: 230e movs r3, #14
80009e4: 757b strb r3, [r7, #21]
break;
80009e6: e038 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 2 :
regAddressXHigh = FT5336_P3_XH_REG;
80009e8: 230f movs r3, #15
80009ea: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P3_WEIGHT_REG;
80009ec: 2313 movs r3, #19
80009ee: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P3_MISC_REG;
80009f0: 2314 movs r3, #20
80009f2: 757b strb r3, [r7, #21]
break;
80009f4: e031 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 3 :
regAddressXHigh = FT5336_P4_XH_REG;
80009f6: 2315 movs r3, #21
80009f8: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P4_WEIGHT_REG;
80009fa: 2319 movs r3, #25
80009fc: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P4_MISC_REG;
80009fe: 231a movs r3, #26
8000a00: 757b strb r3, [r7, #21]
break;
8000a02: e02a b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 4 :
regAddressXHigh = FT5336_P5_XH_REG;
8000a04: 231b movs r3, #27
8000a06: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P5_WEIGHT_REG;
8000a08: 231f movs r3, #31
8000a0a: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P5_MISC_REG;
8000a0c: 2320 movs r3, #32
8000a0e: 757b strb r3, [r7, #21]
break;
8000a10: e023 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 5 :
regAddressXHigh = FT5336_P6_XH_REG;
8000a12: 2321 movs r3, #33 ; 0x21
8000a14: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P6_WEIGHT_REG;
8000a16: 2325 movs r3, #37 ; 0x25
8000a18: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P6_MISC_REG;
8000a1a: 2326 movs r3, #38 ; 0x26
8000a1c: 757b strb r3, [r7, #21]
break;
8000a1e: e01c b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 6 :
regAddressXHigh = FT5336_P7_XH_REG;
8000a20: 2327 movs r3, #39 ; 0x27
8000a22: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P7_WEIGHT_REG;
8000a24: 232b movs r3, #43 ; 0x2b
8000a26: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P7_MISC_REG;
8000a28: 232c movs r3, #44 ; 0x2c
8000a2a: 757b strb r3, [r7, #21]
break;
8000a2c: e015 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 7 :
regAddressXHigh = FT5336_P8_XH_REG;
8000a2e: 232d movs r3, #45 ; 0x2d
8000a30: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P8_WEIGHT_REG;
8000a32: 2331 movs r3, #49 ; 0x31
8000a34: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P8_MISC_REG;
8000a36: 2332 movs r3, #50 ; 0x32
8000a38: 757b strb r3, [r7, #21]
break;
8000a3a: e00e b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 8 :
regAddressXHigh = FT5336_P9_XH_REG;
8000a3c: 2333 movs r3, #51 ; 0x33
8000a3e: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P9_WEIGHT_REG;
8000a40: 2337 movs r3, #55 ; 0x37
8000a42: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P9_MISC_REG;
8000a44: 2338 movs r3, #56 ; 0x38
8000a46: 757b strb r3, [r7, #21]
break;
8000a48: e007 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
case 9 :
regAddressXHigh = FT5336_P10_XH_REG;
8000a4a: 2339 movs r3, #57 ; 0x39
8000a4c: 75fb strb r3, [r7, #23]
regAddressPWeight = FT5336_P10_WEIGHT_REG;
8000a4e: 233d movs r3, #61 ; 0x3d
8000a50: 75bb strb r3, [r7, #22]
regAddressPMisc = FT5336_P10_MISC_REG;
8000a52: 233e movs r3, #62 ; 0x3e
8000a54: 757b strb r3, [r7, #21]
break;
8000a56: e000 b.n 8000a5a <ft5336_TS_GetTouchInfo+0xf2>
default :
break;
8000a58: bf00 nop
} /* end switch(touchIdx) */
/* Read Event Id of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressXHigh);
8000a5a: 89fb ldrh r3, [r7, #14]
8000a5c: b2db uxtb r3, r3
8000a5e: 7dfa ldrb r2, [r7, #23]
8000a60: 4611 mov r1, r2
8000a62: 4618 mov r0, r3
8000a64: f001 fbb6 bl 80021d4 <TS_IO_Read>
8000a68: 4603 mov r3, r0
8000a6a: 753b strb r3, [r7, #20]
* pEvent = (ucReadData & FT5336_TOUCH_EVT_FLAG_MASK) >> FT5336_TOUCH_EVT_FLAG_SHIFT;
8000a6c: 7d3b ldrb r3, [r7, #20]
8000a6e: b2db uxtb r3, r3
8000a70: 119b asrs r3, r3, #6
8000a72: f003 0203 and.w r2, r3, #3
8000a76: 6a3b ldr r3, [r7, #32]
8000a78: 601a str r2, [r3, #0]
/* Read weight of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPWeight);
8000a7a: 89fb ldrh r3, [r7, #14]
8000a7c: b2db uxtb r3, r3
8000a7e: 7dba ldrb r2, [r7, #22]
8000a80: 4611 mov r1, r2
8000a82: 4618 mov r0, r3
8000a84: f001 fba6 bl 80021d4 <TS_IO_Read>
8000a88: 4603 mov r3, r0
8000a8a: 753b strb r3, [r7, #20]
* pWeight = (ucReadData & FT5336_TOUCH_WEIGHT_MASK) >> FT5336_TOUCH_WEIGHT_SHIFT;
8000a8c: 7d3b ldrb r3, [r7, #20]
8000a8e: b2db uxtb r3, r3
8000a90: 461a mov r2, r3
8000a92: 687b ldr r3, [r7, #4]
8000a94: 601a str r2, [r3, #0]
/* Read area of touch index */
ucReadData = TS_IO_Read(DeviceAddr, regAddressPMisc);
8000a96: 89fb ldrh r3, [r7, #14]
8000a98: b2db uxtb r3, r3
8000a9a: 7d7a ldrb r2, [r7, #21]
8000a9c: 4611 mov r1, r2
8000a9e: 4618 mov r0, r3
8000aa0: f001 fb98 bl 80021d4 <TS_IO_Read>
8000aa4: 4603 mov r3, r0
8000aa6: 753b strb r3, [r7, #20]
* pArea = (ucReadData & FT5336_TOUCH_AREA_MASK) >> FT5336_TOUCH_AREA_SHIFT;
8000aa8: 7d3b ldrb r3, [r7, #20]
8000aaa: b2db uxtb r3, r3
8000aac: 111b asrs r3, r3, #4
8000aae: f003 0204 and.w r2, r3, #4
8000ab2: 683b ldr r3, [r7, #0]
8000ab4: 601a str r2, [r3, #0]
} /* of if(touchIdx < ft5336_handle.currActiveTouchNb) */
}
8000ab6: bf00 nop
8000ab8: 3718 adds r7, #24
8000aba: 46bd mov sp, r7
8000abc: bd80 pop {r7, pc}
8000abe: bf00 nop
8000ac0: 200000cc .word 0x200000cc
08000ac4 <ft5336_Get_I2C_InitializedStatus>:
* @brief Return the status of I2C was initialized or not.
* @param None.
* @retval : I2C initialization status.
*/
static uint8_t ft5336_Get_I2C_InitializedStatus(void)
{
8000ac4: b480 push {r7}
8000ac6: af00 add r7, sp, #0
return(ft5336_handle.i2cInitialized);
8000ac8: 4b03 ldr r3, [pc, #12] ; (8000ad8 <ft5336_Get_I2C_InitializedStatus+0x14>)
8000aca: 781b ldrb r3, [r3, #0]
}
8000acc: 4618 mov r0, r3
8000ace: 46bd mov sp, r7
8000ad0: f85d 7b04 ldr.w r7, [sp], #4
8000ad4: 4770 bx lr
8000ad6: bf00 nop
8000ad8: 200000cc .word 0x200000cc
08000adc <ft5336_I2C_InitializeIfRequired>:
* @brief I2C initialize if needed.
* @param None.
* @retval : None.
*/
static void ft5336_I2C_InitializeIfRequired(void)
{
8000adc: b580 push {r7, lr}
8000ade: af00 add r7, sp, #0
if(ft5336_Get_I2C_InitializedStatus() == FT5336_I2C_NOT_INITIALIZED)
8000ae0: f7ff fff0 bl 8000ac4 <ft5336_Get_I2C_InitializedStatus>
8000ae4: 4603 mov r3, r0
8000ae6: 2b00 cmp r3, #0
8000ae8: d104 bne.n 8000af4 <ft5336_I2C_InitializeIfRequired+0x18>
{
/* Initialize TS IO BUS layer (I2C) */
TS_IO_Init();
8000aea: f001 fb4f bl 800218c <TS_IO_Init>
/* Set state to initialized */
ft5336_handle.i2cInitialized = FT5336_I2C_INITIALIZED;
8000aee: 4b02 ldr r3, [pc, #8] ; (8000af8 <ft5336_I2C_InitializeIfRequired+0x1c>)
8000af0: 2201 movs r2, #1
8000af2: 701a strb r2, [r3, #0]
}
}
8000af4: bf00 nop
8000af6: bd80 pop {r7, pc}
8000af8: 200000cc .word 0x200000cc
08000afc <ft5336_TS_Configure>:
* @brief Basic static configuration of TouchScreen
* @param DeviceAddr: FT5336 Device address for communication on I2C Bus.
* @retval Status FT5336_STATUS_OK or FT5336_STATUS_NOT_OK.
*/
static uint32_t ft5336_TS_Configure(uint16_t DeviceAddr)
{
8000afc: b480 push {r7}
8000afe: b085 sub sp, #20
8000b00: af00 add r7, sp, #0
8000b02: 4603 mov r3, r0
8000b04: 80fb strh r3, [r7, #6]
uint32_t status = FT5336_STATUS_OK;
8000b06: 2300 movs r3, #0
8000b08: 60fb str r3, [r7, #12]
/* Nothing special to be done for FT5336 */
return(status);
8000b0a: 68fb ldr r3, [r7, #12]
}
8000b0c: 4618 mov r0, r3
8000b0e: 3714 adds r7, #20
8000b10: 46bd mov sp, r7
8000b12: f85d 7b04 ldr.w r7, [sp], #4
8000b16: 4770 bx lr
08000b18 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000b18: b5b0 push {r4, r5, r7, lr}
8000b1a: b09e sub sp, #120 ; 0x78
8000b1c: af02 add r7, sp, #8
/* USER CODE BEGIN 1 */
char text[50]={};
8000b1e: f107 032c add.w r3, r7, #44 ; 0x2c
8000b22: 2232 movs r2, #50 ; 0x32
8000b24: 2100 movs r1, #0
8000b26: 4618 mov r0, r3
8000b28: f00b f849 bl 800bbbe <memset>
static TS_StateTypeDef TS_State;
uint32_t potl,potr,joystick_h, joystick_v;
ADC_ChannelConfTypeDef sConfig = {0};
8000b2c: f107 031c add.w r3, r7, #28
8000b30: 2200 movs r2, #0
8000b32: 601a str r2, [r3, #0]
8000b34: 605a str r2, [r3, #4]
8000b36: 609a str r2, [r3, #8]
8000b38: 60da str r2, [r3, #12]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000b3a: 2301 movs r3, #1
8000b3c: 623b str r3, [r7, #32]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000b3e: 2300 movs r3, #0
8000b40: 627b str r3, [r7, #36] ; 0x24
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000b42: f003 fcb4 bl 80044ae <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000b46: f000 f925 bl 8000d94 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000b4a: f000 ffbf bl 8001acc <MX_GPIO_Init>
MX_ADC3_Init();
8000b4e: f000 fa23 bl 8000f98 <MX_ADC3_Init>
MX_I2C1_Init();
8000b52: f000 facf bl 80010f4 <MX_I2C1_Init>
MX_I2C3_Init();
8000b56: f000 fb0d bl 8001174 <MX_I2C3_Init>
MX_LTDC_Init();
8000b5a: f000 fb4b bl 80011f4 <MX_LTDC_Init>
MX_RTC_Init();
8000b5e: f000 fbcb bl 80012f8 <MX_RTC_Init>
MX_SPI2_Init();
8000b62: f000 fc6f bl 8001444 <MX_SPI2_Init>
MX_TIM1_Init();
8000b66: f000 fcab bl 80014c0 <MX_TIM1_Init>
MX_TIM2_Init();
8000b6a: f000 fcfd bl 8001568 <MX_TIM2_Init>
MX_TIM3_Init();
8000b6e: f000 fd49 bl 8001604 <MX_TIM3_Init>
MX_TIM5_Init();
8000b72: f000 fdd5 bl 8001720 <MX_TIM5_Init>
MX_TIM8_Init();
8000b76: f000 fe21 bl 80017bc <MX_TIM8_Init>
MX_USART1_UART_Init();
8000b7a: f000 fef9 bl 8001970 <MX_USART1_UART_Init>
MX_USART6_UART_Init();
8000b7e: f000 ff27 bl 80019d0 <MX_USART6_UART_Init>
MX_ADC1_Init();
8000b82: f000 f9b7 bl 8000ef4 <MX_ADC1_Init>
MX_DAC_Init();
8000b86: f000 fa59 bl 800103c <MX_DAC_Init>
MX_UART7_Init();
8000b8a: f000 fec1 bl 8001910 <MX_UART7_Init>
MX_FMC_Init();
8000b8e: f000 ff4f bl 8001a30 <MX_FMC_Init>
MX_DMA2D_Init();
8000b92: f000 fa7d bl 8001090 <MX_DMA2D_Init>
/* USER CODE BEGIN 2 */
BSP_LCD_Init();
8000b96: f001 fb47 bl 8002228 <BSP_LCD_Init>
BSP_LCD_LayerDefaultInit(0, LCD_FB_START_ADDRESS);
8000b9a: f04f 4140 mov.w r1, #3221225472 ; 0xc0000000
8000b9e: 2000 movs r0, #0
8000ba0: f001 fbda bl 8002358 <BSP_LCD_LayerDefaultInit>
BSP_LCD_LayerDefaultInit(1, LCD_FB_START_ADDRESS+ BSP_LCD_GetXSize()*BSP_LCD_GetYSize()*4);
8000ba4: f001 fbb0 bl 8002308 <BSP_LCD_GetXSize>
8000ba8: 4604 mov r4, r0
8000baa: f001 fbc1 bl 8002330 <BSP_LCD_GetYSize>
8000bae: 4603 mov r3, r0
8000bb0: fb03 f304 mul.w r3, r3, r4
8000bb4: f103 5340 add.w r3, r3, #805306368 ; 0x30000000
8000bb8: 009b lsls r3, r3, #2
8000bba: 4619 mov r1, r3
8000bbc: 2001 movs r0, #1
8000bbe: f001 fbcb bl 8002358 <BSP_LCD_LayerDefaultInit>
BSP_LCD_DisplayOn();
8000bc2: f002 f819 bl 8002bf8 <BSP_LCD_DisplayOn>
BSP_LCD_SelectLayer(1);
8000bc6: 2001 movs r0, #1
8000bc8: f001 fc26 bl 8002418 <BSP_LCD_SelectLayer>
BSP_LCD_Clear(LCD_COLOR_LIGHTGREEN);
8000bcc: f06f 107f mvn.w r0, #8323199 ; 0x7f007f
8000bd0: f001 fc94 bl 80024fc <BSP_LCD_Clear>
BSP_LCD_SetFont(&Font12);
8000bd4: 4863 ldr r0, [pc, #396] ; (8000d64 <main+0x24c>)
8000bd6: f001 fc61 bl 800249c <BSP_LCD_SetFont>
BSP_LCD_SetTextColor(LCD_COLOR_BLUE);
8000bda: 4863 ldr r0, [pc, #396] ; (8000d68 <main+0x250>)
8000bdc: f001 fc2c bl 8002438 <BSP_LCD_SetTextColor>
BSP_LCD_SetBackColor(LCD_COLOR_LIGHTGREEN);
8000be0: f06f 107f mvn.w r0, #8323199 ; 0x7f007f
8000be4: f001 fc40 bl 8002468 <BSP_LCD_SetBackColor>
BSP_TS_Init(BSP_LCD_GetXSize(), BSP_LCD_GetYSize());
8000be8: f001 fb8e bl 8002308 <BSP_LCD_GetXSize>
8000bec: 4603 mov r3, r0
8000bee: b29c uxth r4, r3
8000bf0: f001 fb9e bl 8002330 <BSP_LCD_GetYSize>
8000bf4: 4603 mov r3, r0
8000bf6: b29b uxth r3, r3
8000bf8: 4619 mov r1, r3
8000bfa: 4620 mov r0, r4
8000bfc: f002 fbca bl 8003394 <BSP_TS_Init>
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* definition and creation of defaultTask */
osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096);
8000c00: 4b5a ldr r3, [pc, #360] ; (8000d6c <main+0x254>)
8000c02: 463c mov r4, r7
8000c04: 461d mov r5, r3
8000c06: cd0f ldmia r5!, {r0, r1, r2, r3}
8000c08: c40f stmia r4!, {r0, r1, r2, r3}
8000c0a: e895 0007 ldmia.w r5, {r0, r1, r2}
8000c0e: e884 0007 stmia.w r4, {r0, r1, r2}
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
8000c12: 463b mov r3, r7
8000c14: 2100 movs r1, #0
8000c16: 4618 mov r0, r3
8000c18: f009 fef2 bl 800aa00 <osThreadCreate>
8000c1c: 4602 mov r2, r0
8000c1e: 4b54 ldr r3, [pc, #336] ; (8000d70 <main+0x258>)
8000c20: 601a str r2, [r3, #0]
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
HAL_GPIO_WritePin(LED13_GPIO_Port,LED13_Pin,HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin));
8000c22: f44f 7180 mov.w r1, #256 ; 0x100
8000c26: 4853 ldr r0, [pc, #332] ; (8000d74 <main+0x25c>)
8000c28: f005 f916 bl 8005e58 <HAL_GPIO_ReadPin>
8000c2c: 4603 mov r3, r0
8000c2e: 461a mov r2, r3
8000c30: f44f 4180 mov.w r1, #16384 ; 0x4000
8000c34: 4850 ldr r0, [pc, #320] ; (8000d78 <main+0x260>)
8000c36: f005 f927 bl 8005e88 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED14_GPIO_Port,LED14_Pin,HAL_GPIO_ReadPin(BP2_GPIO_Port,BP2_Pin));
8000c3a: f44f 4100 mov.w r1, #32768 ; 0x8000
8000c3e: 484d ldr r0, [pc, #308] ; (8000d74 <main+0x25c>)
8000c40: f005 f90a bl 8005e58 <HAL_GPIO_ReadPin>
8000c44: 4603 mov r3, r0
8000c46: 461a mov r2, r3
8000c48: 2120 movs r1, #32
8000c4a: 484c ldr r0, [pc, #304] ; (8000d7c <main+0x264>)
8000c4c: f005 f91c bl 8005e88 <HAL_GPIO_WritePin>
sprintf(text,"BP1 : %d",HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin));
8000c50: f44f 7180 mov.w r1, #256 ; 0x100
8000c54: 4847 ldr r0, [pc, #284] ; (8000d74 <main+0x25c>)
8000c56: f005 f8ff bl 8005e58 <HAL_GPIO_ReadPin>
8000c5a: 4603 mov r3, r0
8000c5c: 461a mov r2, r3
8000c5e: f107 032c add.w r3, r7, #44 ; 0x2c
8000c62: 4947 ldr r1, [pc, #284] ; (8000d80 <main+0x268>)
8000c64: 4618 mov r0, r3
8000c66: f00a ffb3 bl 800bbd0 <siprintf>
BSP_LCD_DisplayStringAtLine(5,(uint8_t*) text);
8000c6a: f107 032c add.w r3, r7, #44 ; 0x2c
8000c6e: 4619 mov r1, r3
8000c70: 2005 movs r0, #5
8000c72: f001 fd73 bl 800275c <BSP_LCD_DisplayStringAtLine>
sConfig.Channel = ADC_CHANNEL_6;
8000c76: 2306 movs r3, #6
8000c78: 61fb str r3, [r7, #28]
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000c7a: f107 031c add.w r3, r7, #28
8000c7e: 4619 mov r1, r3
8000c80: 4840 ldr r0, [pc, #256] ; (8000d84 <main+0x26c>)
8000c82: f003 fdf9 bl 8004878 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000c86: 483f ldr r0, [pc, #252] ; (8000d84 <main+0x26c>)
8000c88: f003 fca4 bl 80045d4 <HAL_ADC_Start>
while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK);
8000c8c: bf00 nop
8000c8e: 2164 movs r1, #100 ; 0x64
8000c90: 483c ldr r0, [pc, #240] ; (8000d84 <main+0x26c>)
8000c92: f003 fd5f bl 8004754 <HAL_ADC_PollForConversion>
8000c96: 4603 mov r3, r0
8000c98: 2b00 cmp r3, #0
8000c9a: d1f8 bne.n 8000c8e <main+0x176>
potr = HAL_ADC_GetValue(&hadc3);
8000c9c: 4839 ldr r0, [pc, #228] ; (8000d84 <main+0x26c>)
8000c9e: f003 fddd bl 800485c <HAL_ADC_GetValue>
8000ca2: 66f8 str r0, [r7, #108] ; 0x6c
sConfig.Channel = ADC_CHANNEL_7;
8000ca4: 2307 movs r3, #7
8000ca6: 61fb str r3, [r7, #28]
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000ca8: f107 031c add.w r3, r7, #28
8000cac: 4619 mov r1, r3
8000cae: 4835 ldr r0, [pc, #212] ; (8000d84 <main+0x26c>)
8000cb0: f003 fde2 bl 8004878 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000cb4: 4833 ldr r0, [pc, #204] ; (8000d84 <main+0x26c>)
8000cb6: f003 fc8d bl 80045d4 <HAL_ADC_Start>
while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK);
8000cba: bf00 nop
8000cbc: 2164 movs r1, #100 ; 0x64
8000cbe: 4831 ldr r0, [pc, #196] ; (8000d84 <main+0x26c>)
8000cc0: f003 fd48 bl 8004754 <HAL_ADC_PollForConversion>
8000cc4: 4603 mov r3, r0
8000cc6: 2b00 cmp r3, #0
8000cc8: d1f8 bne.n 8000cbc <main+0x1a4>
potl = HAL_ADC_GetValue(&hadc3);
8000cca: 482e ldr r0, [pc, #184] ; (8000d84 <main+0x26c>)
8000ccc: f003 fdc6 bl 800485c <HAL_ADC_GetValue>
8000cd0: 66b8 str r0, [r7, #104] ; 0x68
sConfig.Channel = ADC_CHANNEL_8;
8000cd2: 2308 movs r3, #8
8000cd4: 61fb str r3, [r7, #28]
HAL_ADC_ConfigChannel(&hadc3, &sConfig);
8000cd6: f107 031c add.w r3, r7, #28
8000cda: 4619 mov r1, r3
8000cdc: 4829 ldr r0, [pc, #164] ; (8000d84 <main+0x26c>)
8000cde: f003 fdcb bl 8004878 <HAL_ADC_ConfigChannel>
HAL_ADC_Start(&hadc3);
8000ce2: 4828 ldr r0, [pc, #160] ; (8000d84 <main+0x26c>)
8000ce4: f003 fc76 bl 80045d4 <HAL_ADC_Start>
while(HAL_ADC_PollForConversion(&hadc3, 100)!=HAL_OK);
8000ce8: bf00 nop
8000cea: 2164 movs r1, #100 ; 0x64
8000cec: 4825 ldr r0, [pc, #148] ; (8000d84 <main+0x26c>)
8000cee: f003 fd31 bl 8004754 <HAL_ADC_PollForConversion>
8000cf2: 4603 mov r3, r0
8000cf4: 2b00 cmp r3, #0
8000cf6: d1f8 bne.n 8000cea <main+0x1d2>
joystick_v = HAL_ADC_GetValue(&hadc3);
8000cf8: 4822 ldr r0, [pc, #136] ; (8000d84 <main+0x26c>)
8000cfa: f003 fdaf bl 800485c <HAL_ADC_GetValue>
8000cfe: 6678 str r0, [r7, #100] ; 0x64
HAL_ADC_Start(&hadc1);
8000d00: 4821 ldr r0, [pc, #132] ; (8000d88 <main+0x270>)
8000d02: f003 fc67 bl 80045d4 <HAL_ADC_Start>
while(HAL_ADC_PollForConversion(&hadc1, 100)!=HAL_OK);
8000d06: bf00 nop
8000d08: 2164 movs r1, #100 ; 0x64
8000d0a: 481f ldr r0, [pc, #124] ; (8000d88 <main+0x270>)
8000d0c: f003 fd22 bl 8004754 <HAL_ADC_PollForConversion>
8000d10: 4603 mov r3, r0
8000d12: 2b00 cmp r3, #0
8000d14: d1f8 bne.n 8000d08 <main+0x1f0>
joystick_h = HAL_ADC_GetValue(&hadc1);
8000d16: 481c ldr r0, [pc, #112] ; (8000d88 <main+0x270>)
8000d18: f003 fda0 bl 800485c <HAL_ADC_GetValue>
8000d1c: 6638 str r0, [r7, #96] ; 0x60
sprintf(text,"POTL : %4u POTR : %4u joy_v : %4u joy_h : %4u",(uint)potl,(uint)potr,(uint)joystick_v,(uint)joystick_h);
8000d1e: f107 002c add.w r0, r7, #44 ; 0x2c
8000d22: 6e3b ldr r3, [r7, #96] ; 0x60
8000d24: 9301 str r3, [sp, #4]
8000d26: 6e7b ldr r3, [r7, #100] ; 0x64
8000d28: 9300 str r3, [sp, #0]
8000d2a: 6efb ldr r3, [r7, #108] ; 0x6c
8000d2c: 6eba ldr r2, [r7, #104] ; 0x68
8000d2e: 4917 ldr r1, [pc, #92] ; (8000d8c <main+0x274>)
8000d30: f00a ff4e bl 800bbd0 <siprintf>
BSP_LCD_DisplayStringAtLine(9,(uint8_t*) text);
8000d34: f107 032c add.w r3, r7, #44 ; 0x2c
8000d38: 4619 mov r1, r3
8000d3a: 2009 movs r0, #9
8000d3c: f001 fd0e bl 800275c <BSP_LCD_DisplayStringAtLine>
BSP_TS_GetState(&TS_State);
8000d40: 4813 ldr r0, [pc, #76] ; (8000d90 <main+0x278>)
8000d42: f002 fb67 bl 8003414 <BSP_TS_GetState>
if(TS_State.touchDetected){
8000d46: 4b12 ldr r3, [pc, #72] ; (8000d90 <main+0x278>)
8000d48: 781b ldrb r3, [r3, #0]
8000d4a: 2b00 cmp r3, #0
8000d4c: f43f af69 beq.w 8000c22 <main+0x10a>
BSP_LCD_FillCircle(TS_State.touchX[0],TS_State.touchY[0],4);
8000d50: 4b0f ldr r3, [pc, #60] ; (8000d90 <main+0x278>)
8000d52: 8858 ldrh r0, [r3, #2]
8000d54: 4b0e ldr r3, [pc, #56] ; (8000d90 <main+0x278>)
8000d56: 899b ldrh r3, [r3, #12]
8000d58: 2204 movs r2, #4
8000d5a: 4619 mov r1, r3
8000d5c: f001 feac bl 8002ab8 <BSP_LCD_FillCircle>
HAL_GPIO_WritePin(LED13_GPIO_Port,LED13_Pin,HAL_GPIO_ReadPin(BP1_GPIO_Port,BP1_Pin));
8000d60: e75f b.n 8000c22 <main+0x10a>
8000d62: bf00 nop
8000d64: 20000030 .word 0x20000030
8000d68: ff0000ff .word 0xff0000ff
8000d6c: 0800c428 .word 0x0800c428
8000d70: 20008438 .word 0x20008438
8000d74: 40020000 .word 0x40020000
8000d78: 40021c00 .word 0x40021c00
8000d7c: 40021000 .word 0x40021000
8000d80: 0800c3e0 .word 0x0800c3e0
8000d84: 20008768 .word 0x20008768
8000d88: 20008720 .word 0x20008720
8000d8c: 0800c3ec .word 0x0800c3ec
8000d90: 200000d4 .word 0x200000d4
08000d94 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000d94: b580 push {r7, lr}
8000d96: b0b4 sub sp, #208 ; 0xd0
8000d98: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000d9a: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000d9e: 2230 movs r2, #48 ; 0x30
8000da0: 2100 movs r1, #0
8000da2: 4618 mov r0, r3
8000da4: f00a ff0b bl 800bbbe <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000da8: f107 038c add.w r3, r7, #140 ; 0x8c
8000dac: 2200 movs r2, #0
8000dae: 601a str r2, [r3, #0]
8000db0: 605a str r2, [r3, #4]
8000db2: 609a str r2, [r3, #8]
8000db4: 60da str r2, [r3, #12]
8000db6: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000db8: f107 0308 add.w r3, r7, #8
8000dbc: 2284 movs r2, #132 ; 0x84
8000dbe: 2100 movs r1, #0
8000dc0: 4618 mov r0, r3
8000dc2: f00a fefc bl 800bbbe <memset>
/** Configure LSE Drive Capability
*/
HAL_PWR_EnableBkUpAccess();
8000dc6: f006 f9a1 bl 800710c <HAL_PWR_EnableBkUpAccess>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000dca: 4b47 ldr r3, [pc, #284] ; (8000ee8 <SystemClock_Config+0x154>)
8000dcc: 6c1b ldr r3, [r3, #64] ; 0x40
8000dce: 4a46 ldr r2, [pc, #280] ; (8000ee8 <SystemClock_Config+0x154>)
8000dd0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000dd4: 6413 str r3, [r2, #64] ; 0x40
8000dd6: 4b44 ldr r3, [pc, #272] ; (8000ee8 <SystemClock_Config+0x154>)
8000dd8: 6c1b ldr r3, [r3, #64] ; 0x40
8000dda: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000dde: 607b str r3, [r7, #4]
8000de0: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000de2: 4b42 ldr r3, [pc, #264] ; (8000eec <SystemClock_Config+0x158>)
8000de4: 681b ldr r3, [r3, #0]
8000de6: 4a41 ldr r2, [pc, #260] ; (8000eec <SystemClock_Config+0x158>)
8000de8: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8000dec: 6013 str r3, [r2, #0]
8000dee: 4b3f ldr r3, [pc, #252] ; (8000eec <SystemClock_Config+0x158>)
8000df0: 681b ldr r3, [r3, #0]
8000df2: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000df6: 603b str r3, [r7, #0]
8000df8: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
8000dfa: 2309 movs r3, #9
8000dfc: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000e00: f44f 3380 mov.w r3, #65536 ; 0x10000
8000e04: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
8000e08: 2301 movs r3, #1
8000e0a: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000e0e: 2302 movs r3, #2
8000e10: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000e14: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000e18: f8c7 30bc str.w r3, [r7, #188] ; 0xbc
RCC_OscInitStruct.PLL.PLLM = 25;
8000e1c: 2319 movs r3, #25
8000e1e: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
RCC_OscInitStruct.PLL.PLLN = 400;
8000e22: f44f 73c8 mov.w r3, #400 ; 0x190
8000e26: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000e2a: 2302 movs r3, #2
8000e2c: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
RCC_OscInitStruct.PLL.PLLQ = 9;
8000e30: 2309 movs r3, #9
8000e32: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000e36: f107 03a0 add.w r3, r7, #160 ; 0xa0
8000e3a: 4618 mov r0, r3
8000e3c: f006 f9c6 bl 80071cc <HAL_RCC_OscConfig>
8000e40: 4603 mov r3, r0
8000e42: 2b00 cmp r3, #0
8000e44: d001 beq.n 8000e4a <SystemClock_Config+0xb6>
{
Error_Handler();
8000e46: f001 f847 bl 8001ed8 <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
8000e4a: f006 f96f bl 800712c <HAL_PWREx_EnableOverDrive>
8000e4e: 4603 mov r3, r0
8000e50: 2b00 cmp r3, #0
8000e52: d001 beq.n 8000e58 <SystemClock_Config+0xc4>
{
Error_Handler();
8000e54: f001 f840 bl 8001ed8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000e58: 230f movs r3, #15
8000e5a: f8c7 308c str.w r3, [r7, #140] ; 0x8c
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000e5e: 2302 movs r3, #2
8000e60: f8c7 3090 str.w r3, [r7, #144] ; 0x90
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000e64: 2300 movs r3, #0
8000e66: f8c7 3094 str.w r3, [r7, #148] ; 0x94
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000e6a: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000e6e: f8c7 3098 str.w r3, [r7, #152] ; 0x98
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000e72: f44f 5380 mov.w r3, #4096 ; 0x1000
8000e76: f8c7 309c str.w r3, [r7, #156] ; 0x9c
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK)
8000e7a: f107 038c add.w r3, r7, #140 ; 0x8c
8000e7e: 2106 movs r1, #6
8000e80: 4618 mov r0, r3
8000e82: f006 fc47 bl 8007714 <HAL_RCC_ClockConfig>
8000e86: 4603 mov r3, r0
8000e88: 2b00 cmp r3, #0
8000e8a: d001 beq.n 8000e90 <SystemClock_Config+0xfc>
{
Error_Handler();
8000e8c: f001 f824 bl 8001ed8 <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_RTC
8000e90: 4b17 ldr r3, [pc, #92] ; (8000ef0 <SystemClock_Config+0x15c>)
8000e92: 60bb str r3, [r7, #8]
|RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART6
|RCC_PERIPHCLK_UART7|RCC_PERIPHCLK_I2C1
|RCC_PERIPHCLK_I2C3;
PeriphClkInitStruct.PLLSAI.PLLSAIN = 384;
8000e94: f44f 73c0 mov.w r3, #384 ; 0x180
8000e98: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
8000e9a: 2305 movs r3, #5
8000e9c: 627b str r3, [r7, #36] ; 0x24
PeriphClkInitStruct.PLLSAI.PLLSAIQ = 2;
8000e9e: 2302 movs r3, #2
8000ea0: 623b str r3, [r7, #32]
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;
8000ea2: 2303 movs r3, #3
8000ea4: 62bb str r3, [r7, #40] ; 0x28
PeriphClkInitStruct.PLLSAIDivQ = 1;
8000ea6: 2301 movs r3, #1
8000ea8: 633b str r3, [r7, #48] ; 0x30
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
8000eaa: f44f 3300 mov.w r3, #131072 ; 0x20000
8000eae: 637b str r3, [r7, #52] ; 0x34
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
8000eb0: f44f 7300 mov.w r3, #512 ; 0x200
8000eb4: 63bb str r3, [r7, #56] ; 0x38
PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
8000eb6: 2300 movs r3, #0
8000eb8: 64fb str r3, [r7, #76] ; 0x4c
PeriphClkInitStruct.Usart6ClockSelection = RCC_USART6CLKSOURCE_PCLK2;
8000eba: 2300 movs r3, #0
8000ebc: 663b str r3, [r7, #96] ; 0x60
PeriphClkInitStruct.Uart7ClockSelection = RCC_UART7CLKSOURCE_PCLK1;
8000ebe: 2300 movs r3, #0
8000ec0: 667b str r3, [r7, #100] ; 0x64
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
8000ec2: 2300 movs r3, #0
8000ec4: 66fb str r3, [r7, #108] ; 0x6c
PeriphClkInitStruct.I2c3ClockSelection = RCC_I2C3CLKSOURCE_PCLK1;
8000ec6: 2300 movs r3, #0
8000ec8: 677b str r3, [r7, #116] ; 0x74
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000eca: f107 0308 add.w r3, r7, #8
8000ece: 4618 mov r0, r3
8000ed0: f006 fe24 bl 8007b1c <HAL_RCCEx_PeriphCLKConfig>
8000ed4: 4603 mov r3, r0
8000ed6: 2b00 cmp r3, #0
8000ed8: d001 beq.n 8000ede <SystemClock_Config+0x14a>
{
Error_Handler();
8000eda: f000 fffd bl 8001ed8 <Error_Handler>
}
}
8000ede: bf00 nop
8000ee0: 37d0 adds r7, #208 ; 0xd0
8000ee2: 46bd mov sp, r7
8000ee4: bd80 pop {r7, pc}
8000ee6: bf00 nop
8000ee8: 40023800 .word 0x40023800
8000eec: 40007000 .word 0x40007000
8000ef0: 00015868 .word 0x00015868
08000ef4 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
8000ef4: b580 push {r7, lr}
8000ef6: b084 sub sp, #16
8000ef8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000efa: 463b mov r3, r7
8000efc: 2200 movs r2, #0
8000efe: 601a str r2, [r3, #0]
8000f00: 605a str r2, [r3, #4]
8000f02: 609a str r2, [r3, #8]
8000f04: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
8000f06: 4b21 ldr r3, [pc, #132] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f08: 4a21 ldr r2, [pc, #132] ; (8000f90 <MX_ADC1_Init+0x9c>)
8000f0a: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000f0c: 4b1f ldr r3, [pc, #124] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f0e: f44f 3280 mov.w r2, #65536 ; 0x10000
8000f12: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8000f14: 4b1d ldr r3, [pc, #116] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f16: 2200 movs r2, #0
8000f18: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000f1a: 4b1c ldr r3, [pc, #112] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f1c: 2200 movs r2, #0
8000f1e: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000f20: 4b1a ldr r3, [pc, #104] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f22: 2200 movs r2, #0
8000f24: 619a str r2, [r3, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000f26: 4b19 ldr r3, [pc, #100] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f28: 2200 movs r2, #0
8000f2a: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000f2e: 4b17 ldr r3, [pc, #92] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f30: 2200 movs r2, #0
8000f32: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000f34: 4b15 ldr r3, [pc, #84] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f36: 4a17 ldr r2, [pc, #92] ; (8000f94 <MX_ADC1_Init+0xa0>)
8000f38: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000f3a: 4b14 ldr r3, [pc, #80] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f3c: 2200 movs r2, #0
8000f3e: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 1;
8000f40: 4b12 ldr r3, [pc, #72] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f42: 2201 movs r2, #1
8000f44: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = DISABLE;
8000f46: 4b11 ldr r3, [pc, #68] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f48: 2200 movs r2, #0
8000f4a: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000f4e: 4b0f ldr r3, [pc, #60] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f50: 2201 movs r2, #1
8000f52: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000f54: 480d ldr r0, [pc, #52] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f56: f003 faf9 bl 800454c <HAL_ADC_Init>
8000f5a: 4603 mov r3, r0
8000f5c: 2b00 cmp r3, #0
8000f5e: d001 beq.n 8000f64 <MX_ADC1_Init+0x70>
{
Error_Handler();
8000f60: f000 ffba bl 8001ed8 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_0;
8000f64: 2300 movs r3, #0
8000f66: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000f68: 2301 movs r3, #1
8000f6a: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8000f6c: 2300 movs r3, #0
8000f6e: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000f70: 463b mov r3, r7
8000f72: 4619 mov r1, r3
8000f74: 4805 ldr r0, [pc, #20] ; (8000f8c <MX_ADC1_Init+0x98>)
8000f76: f003 fc7f bl 8004878 <HAL_ADC_ConfigChannel>
8000f7a: 4603 mov r3, r0
8000f7c: 2b00 cmp r3, #0
8000f7e: d001 beq.n 8000f84 <MX_ADC1_Init+0x90>
{
Error_Handler();
8000f80: f000 ffaa bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000f84: bf00 nop
8000f86: 3710 adds r7, #16
8000f88: 46bd mov sp, r7
8000f8a: bd80 pop {r7, pc}
8000f8c: 20008720 .word 0x20008720
8000f90: 40012000 .word 0x40012000
8000f94: 0f000001 .word 0x0f000001
08000f98 <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000f98: b580 push {r7, lr}
8000f9a: b084 sub sp, #16
8000f9c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
8000f9e: 463b mov r3, r7
8000fa0: 2200 movs r2, #0
8000fa2: 601a str r2, [r3, #0]
8000fa4: 605a str r2, [r3, #4]
8000fa6: 609a str r2, [r3, #8]
8000fa8: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
8000faa: 4b21 ldr r3, [pc, #132] ; (8001030 <MX_ADC3_Init+0x98>)
8000fac: 4a21 ldr r2, [pc, #132] ; (8001034 <MX_ADC3_Init+0x9c>)
8000fae: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
8000fb0: 4b1f ldr r3, [pc, #124] ; (8001030 <MX_ADC3_Init+0x98>)
8000fb2: f44f 3280 mov.w r2, #65536 ; 0x10000
8000fb6: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
8000fb8: 4b1d ldr r3, [pc, #116] ; (8001030 <MX_ADC3_Init+0x98>)
8000fba: 2200 movs r2, #0
8000fbc: 609a str r2, [r3, #8]
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000fbe: 4b1c ldr r3, [pc, #112] ; (8001030 <MX_ADC3_Init+0x98>)
8000fc0: 2200 movs r2, #0
8000fc2: 611a str r2, [r3, #16]
hadc3.Init.ContinuousConvMode = DISABLE;
8000fc4: 4b1a ldr r3, [pc, #104] ; (8001030 <MX_ADC3_Init+0x98>)
8000fc6: 2200 movs r2, #0
8000fc8: 619a str r2, [r3, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
8000fca: 4b19 ldr r3, [pc, #100] ; (8001030 <MX_ADC3_Init+0x98>)
8000fcc: 2200 movs r2, #0
8000fce: f883 2020 strb.w r2, [r3, #32]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000fd2: 4b17 ldr r3, [pc, #92] ; (8001030 <MX_ADC3_Init+0x98>)
8000fd4: 2200 movs r2, #0
8000fd6: 62da str r2, [r3, #44] ; 0x2c
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000fd8: 4b15 ldr r3, [pc, #84] ; (8001030 <MX_ADC3_Init+0x98>)
8000fda: 4a17 ldr r2, [pc, #92] ; (8001038 <MX_ADC3_Init+0xa0>)
8000fdc: 629a str r2, [r3, #40] ; 0x28
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000fde: 4b14 ldr r3, [pc, #80] ; (8001030 <MX_ADC3_Init+0x98>)
8000fe0: 2200 movs r2, #0
8000fe2: 60da str r2, [r3, #12]
hadc3.Init.NbrOfConversion = 1;
8000fe4: 4b12 ldr r3, [pc, #72] ; (8001030 <MX_ADC3_Init+0x98>)
8000fe6: 2201 movs r2, #1
8000fe8: 61da str r2, [r3, #28]
hadc3.Init.DMAContinuousRequests = DISABLE;
8000fea: 4b11 ldr r3, [pc, #68] ; (8001030 <MX_ADC3_Init+0x98>)
8000fec: 2200 movs r2, #0
8000fee: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000ff2: 4b0f ldr r3, [pc, #60] ; (8001030 <MX_ADC3_Init+0x98>)
8000ff4: 2201 movs r2, #1
8000ff6: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
8000ff8: 480d ldr r0, [pc, #52] ; (8001030 <MX_ADC3_Init+0x98>)
8000ffa: f003 faa7 bl 800454c <HAL_ADC_Init>
8000ffe: 4603 mov r3, r0
8001000: 2b00 cmp r3, #0
8001002: d001 beq.n 8001008 <MX_ADC3_Init+0x70>
{
Error_Handler();
8001004: f000 ff68 bl 8001ed8 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_6;
8001008: 2306 movs r3, #6
800100a: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
800100c: 2301 movs r3, #1
800100e: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
8001010: 2300 movs r3, #0
8001012: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
8001014: 463b mov r3, r7
8001016: 4619 mov r1, r3
8001018: 4805 ldr r0, [pc, #20] ; (8001030 <MX_ADC3_Init+0x98>)
800101a: f003 fc2d bl 8004878 <HAL_ADC_ConfigChannel>
800101e: 4603 mov r3, r0
8001020: 2b00 cmp r3, #0
8001022: d001 beq.n 8001028 <MX_ADC3_Init+0x90>
{
Error_Handler();
8001024: f000 ff58 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
8001028: bf00 nop
800102a: 3710 adds r7, #16
800102c: 46bd mov sp, r7
800102e: bd80 pop {r7, pc}
8001030: 20008768 .word 0x20008768
8001034: 40012200 .word 0x40012200
8001038: 0f000001 .word 0x0f000001
0800103c <MX_DAC_Init>:
* @brief DAC Initialization Function
* @param None
* @retval None
*/
static void MX_DAC_Init(void)
{
800103c: b580 push {r7, lr}
800103e: b082 sub sp, #8
8001040: af00 add r7, sp, #0
/* USER CODE BEGIN DAC_Init 0 */
/* USER CODE END DAC_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
8001042: 463b mov r3, r7
8001044: 2200 movs r2, #0
8001046: 601a str r2, [r3, #0]
8001048: 605a str r2, [r3, #4]
/* USER CODE BEGIN DAC_Init 1 */
/* USER CODE END DAC_Init 1 */
/** DAC Initialization
*/
hdac.Instance = DAC;
800104a: 4b0f ldr r3, [pc, #60] ; (8001088 <MX_DAC_Init+0x4c>)
800104c: 4a0f ldr r2, [pc, #60] ; (800108c <MX_DAC_Init+0x50>)
800104e: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac) != HAL_OK)
8001050: 480d ldr r0, [pc, #52] ; (8001088 <MX_DAC_Init+0x4c>)
8001052: f003 ff37 bl 8004ec4 <HAL_DAC_Init>
8001056: 4603 mov r3, r0
8001058: 2b00 cmp r3, #0
800105a: d001 beq.n 8001060 <MX_DAC_Init+0x24>
{
Error_Handler();
800105c: f000 ff3c bl 8001ed8 <Error_Handler>
}
/** DAC channel OUT1 config
*/
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
8001060: 2300 movs r3, #0
8001062: 603b str r3, [r7, #0]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
8001064: 2300 movs r3, #0
8001066: 607b str r3, [r7, #4]
if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_1) != HAL_OK)
8001068: 463b mov r3, r7
800106a: 2200 movs r2, #0
800106c: 4619 mov r1, r3
800106e: 4806 ldr r0, [pc, #24] ; (8001088 <MX_DAC_Init+0x4c>)
8001070: f003 ff9e bl 8004fb0 <HAL_DAC_ConfigChannel>
8001074: 4603 mov r3, r0
8001076: 2b00 cmp r3, #0
8001078: d001 beq.n 800107e <MX_DAC_Init+0x42>
{
Error_Handler();
800107a: f000 ff2d bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN DAC_Init 2 */
/* USER CODE END DAC_Init 2 */
}
800107e: bf00 nop
8001080: 3708 adds r7, #8
8001082: 46bd mov sp, r7
8001084: bd80 pop {r7, pc}
8001086: bf00 nop
8001088: 20008830 .word 0x20008830
800108c: 40007400 .word 0x40007400
08001090 <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
8001090: b580 push {r7, lr}
8001092: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
8001094: 4b15 ldr r3, [pc, #84] ; (80010ec <MX_DMA2D_Init+0x5c>)
8001096: 4a16 ldr r2, [pc, #88] ; (80010f0 <MX_DMA2D_Init+0x60>)
8001098: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
800109a: 4b14 ldr r3, [pc, #80] ; (80010ec <MX_DMA2D_Init+0x5c>)
800109c: 2200 movs r2, #0
800109e: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
80010a0: 4b12 ldr r3, [pc, #72] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010a2: 2200 movs r2, #0
80010a4: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
80010a6: 4b11 ldr r3, [pc, #68] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010a8: 2200 movs r2, #0
80010aa: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
80010ac: 4b0f ldr r3, [pc, #60] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010ae: 2200 movs r2, #0
80010b0: 629a str r2, [r3, #40] ; 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
80010b2: 4b0e ldr r3, [pc, #56] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010b4: 2200 movs r2, #0
80010b6: 62da str r2, [r3, #44] ; 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
80010b8: 4b0c ldr r3, [pc, #48] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010ba: 2200 movs r2, #0
80010bc: 631a str r2, [r3, #48] ; 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
80010be: 4b0b ldr r3, [pc, #44] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010c0: 2200 movs r2, #0
80010c2: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
80010c4: 4809 ldr r0, [pc, #36] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010c6: f004 f987 bl 80053d8 <HAL_DMA2D_Init>
80010ca: 4603 mov r3, r0
80010cc: 2b00 cmp r3, #0
80010ce: d001 beq.n 80010d4 <MX_DMA2D_Init+0x44>
{
Error_Handler();
80010d0: f000 ff02 bl 8001ed8 <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
80010d4: 2101 movs r1, #1
80010d6: 4805 ldr r0, [pc, #20] ; (80010ec <MX_DMA2D_Init+0x5c>)
80010d8: f004 fadc bl 8005694 <HAL_DMA2D_ConfigLayer>
80010dc: 4603 mov r3, r0
80010de: 2b00 cmp r3, #0
80010e0: d001 beq.n 80010e6 <MX_DMA2D_Init+0x56>
{
Error_Handler();
80010e2: f000 fef9 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
80010e6: bf00 nop
80010e8: bd80 pop {r7, pc}
80010ea: bf00 nop
80010ec: 20008924 .word 0x20008924
80010f0: 4002b000 .word 0x4002b000
080010f4 <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
80010f4: b580 push {r7, lr}
80010f6: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
80010f8: 4b1b ldr r3, [pc, #108] ; (8001168 <MX_I2C1_Init+0x74>)
80010fa: 4a1c ldr r2, [pc, #112] ; (800116c <MX_I2C1_Init+0x78>)
80010fc: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x00C0EAFF;
80010fe: 4b1a ldr r3, [pc, #104] ; (8001168 <MX_I2C1_Init+0x74>)
8001100: 4a1b ldr r2, [pc, #108] ; (8001170 <MX_I2C1_Init+0x7c>)
8001102: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
8001104: 4b18 ldr r3, [pc, #96] ; (8001168 <MX_I2C1_Init+0x74>)
8001106: 2200 movs r2, #0
8001108: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
800110a: 4b17 ldr r3, [pc, #92] ; (8001168 <MX_I2C1_Init+0x74>)
800110c: 2201 movs r2, #1
800110e: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001110: 4b15 ldr r3, [pc, #84] ; (8001168 <MX_I2C1_Init+0x74>)
8001112: 2200 movs r2, #0
8001114: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
8001116: 4b14 ldr r3, [pc, #80] ; (8001168 <MX_I2C1_Init+0x74>)
8001118: 2200 movs r2, #0
800111a: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
800111c: 4b12 ldr r3, [pc, #72] ; (8001168 <MX_I2C1_Init+0x74>)
800111e: 2200 movs r2, #0
8001120: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8001122: 4b11 ldr r3, [pc, #68] ; (8001168 <MX_I2C1_Init+0x74>)
8001124: 2200 movs r2, #0
8001126: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8001128: 4b0f ldr r3, [pc, #60] ; (8001168 <MX_I2C1_Init+0x74>)
800112a: 2200 movs r2, #0
800112c: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
800112e: 480e ldr r0, [pc, #56] ; (8001168 <MX_I2C1_Init+0x74>)
8001130: f004 fec4 bl 8005ebc <HAL_I2C_Init>
8001134: 4603 mov r3, r0
8001136: 2b00 cmp r3, #0
8001138: d001 beq.n 800113e <MX_I2C1_Init+0x4a>
{
Error_Handler();
800113a: f000 fecd bl 8001ed8 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
800113e: 2100 movs r1, #0
8001140: 4809 ldr r0, [pc, #36] ; (8001168 <MX_I2C1_Init+0x74>)
8001142: f005 fbd3 bl 80068ec <HAL_I2CEx_ConfigAnalogFilter>
8001146: 4603 mov r3, r0
8001148: 2b00 cmp r3, #0
800114a: d001 beq.n 8001150 <MX_I2C1_Init+0x5c>
{
Error_Handler();
800114c: f000 fec4 bl 8001ed8 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
8001150: 2100 movs r1, #0
8001152: 4805 ldr r0, [pc, #20] ; (8001168 <MX_I2C1_Init+0x74>)
8001154: f005 fc15 bl 8006982 <HAL_I2CEx_ConfigDigitalFilter>
8001158: 4603 mov r3, r0
800115a: 2b00 cmp r3, #0
800115c: d001 beq.n 8001162 <MX_I2C1_Init+0x6e>
{
Error_Handler();
800115e: f000 febb bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
8001162: bf00 nop
8001164: bd80 pop {r7, pc}
8001166: bf00 nop
8001168: 200085ac .word 0x200085ac
800116c: 40005400 .word 0x40005400
8001170: 00c0eaff .word 0x00c0eaff
08001174 <MX_I2C3_Init>:
* @brief I2C3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C3_Init(void)
{
8001174: b580 push {r7, lr}
8001176: af00 add r7, sp, #0
/* USER CODE END I2C3_Init 0 */
/* USER CODE BEGIN I2C3_Init 1 */
/* USER CODE END I2C3_Init 1 */
hi2c3.Instance = I2C3;
8001178: 4b1b ldr r3, [pc, #108] ; (80011e8 <MX_I2C3_Init+0x74>)
800117a: 4a1c ldr r2, [pc, #112] ; (80011ec <MX_I2C3_Init+0x78>)
800117c: 601a str r2, [r3, #0]
hi2c3.Init.Timing = 0x00C0EAFF;
800117e: 4b1a ldr r3, [pc, #104] ; (80011e8 <MX_I2C3_Init+0x74>)
8001180: 4a1b ldr r2, [pc, #108] ; (80011f0 <MX_I2C3_Init+0x7c>)
8001182: 605a str r2, [r3, #4]
hi2c3.Init.OwnAddress1 = 0;
8001184: 4b18 ldr r3, [pc, #96] ; (80011e8 <MX_I2C3_Init+0x74>)
8001186: 2200 movs r2, #0
8001188: 609a str r2, [r3, #8]
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
800118a: 4b17 ldr r3, [pc, #92] ; (80011e8 <MX_I2C3_Init+0x74>)
800118c: 2201 movs r2, #1
800118e: 60da str r2, [r3, #12]
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001190: 4b15 ldr r3, [pc, #84] ; (80011e8 <MX_I2C3_Init+0x74>)
8001192: 2200 movs r2, #0
8001194: 611a str r2, [r3, #16]
hi2c3.Init.OwnAddress2 = 0;
8001196: 4b14 ldr r3, [pc, #80] ; (80011e8 <MX_I2C3_Init+0x74>)
8001198: 2200 movs r2, #0
800119a: 615a str r2, [r3, #20]
hi2c3.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
800119c: 4b12 ldr r3, [pc, #72] ; (80011e8 <MX_I2C3_Init+0x74>)
800119e: 2200 movs r2, #0
80011a0: 619a str r2, [r3, #24]
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80011a2: 4b11 ldr r3, [pc, #68] ; (80011e8 <MX_I2C3_Init+0x74>)
80011a4: 2200 movs r2, #0
80011a6: 61da str r2, [r3, #28]
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80011a8: 4b0f ldr r3, [pc, #60] ; (80011e8 <MX_I2C3_Init+0x74>)
80011aa: 2200 movs r2, #0
80011ac: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
80011ae: 480e ldr r0, [pc, #56] ; (80011e8 <MX_I2C3_Init+0x74>)
80011b0: f004 fe84 bl 8005ebc <HAL_I2C_Init>
80011b4: 4603 mov r3, r0
80011b6: 2b00 cmp r3, #0
80011b8: d001 beq.n 80011be <MX_I2C3_Init+0x4a>
{
Error_Handler();
80011ba: f000 fe8d bl 8001ed8 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
80011be: 2100 movs r1, #0
80011c0: 4809 ldr r0, [pc, #36] ; (80011e8 <MX_I2C3_Init+0x74>)
80011c2: f005 fb93 bl 80068ec <HAL_I2CEx_ConfigAnalogFilter>
80011c6: 4603 mov r3, r0
80011c8: 2b00 cmp r3, #0
80011ca: d001 beq.n 80011d0 <MX_I2C3_Init+0x5c>
{
Error_Handler();
80011cc: f000 fe84 bl 8001ed8 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
80011d0: 2100 movs r1, #0
80011d2: 4805 ldr r0, [pc, #20] ; (80011e8 <MX_I2C3_Init+0x74>)
80011d4: f005 fbd5 bl 8006982 <HAL_I2CEx_ConfigDigitalFilter>
80011d8: 4603 mov r3, r0
80011da: 2b00 cmp r3, #0
80011dc: d001 beq.n 80011e2 <MX_I2C3_Init+0x6e>
{
Error_Handler();
80011de: f000 fe7b bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN I2C3_Init 2 */
/* USER CODE END I2C3_Init 2 */
}
80011e2: bf00 nop
80011e4: bd80 pop {r7, pc}
80011e6: bf00 nop
80011e8: 2000843c .word 0x2000843c
80011ec: 40005c00 .word 0x40005c00
80011f0: 00c0eaff .word 0x00c0eaff
080011f4 <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
80011f4: b580 push {r7, lr}
80011f6: b08e sub sp, #56 ; 0x38
80011f8: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
80011fa: 1d3b adds r3, r7, #4
80011fc: 2234 movs r2, #52 ; 0x34
80011fe: 2100 movs r1, #0
8001200: 4618 mov r0, r3
8001202: f00a fcdc bl 800bbbe <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
8001206: 4b3a ldr r3, [pc, #232] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001208: 4a3a ldr r2, [pc, #232] ; (80012f4 <MX_LTDC_Init+0x100>)
800120a: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
800120c: 4b38 ldr r3, [pc, #224] ; (80012f0 <MX_LTDC_Init+0xfc>)
800120e: 2200 movs r2, #0
8001210: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
8001212: 4b37 ldr r3, [pc, #220] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001214: 2200 movs r2, #0
8001216: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
8001218: 4b35 ldr r3, [pc, #212] ; (80012f0 <MX_LTDC_Init+0xfc>)
800121a: 2200 movs r2, #0
800121c: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
800121e: 4b34 ldr r3, [pc, #208] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001220: 2200 movs r2, #0
8001222: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 40;
8001224: 4b32 ldr r3, [pc, #200] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001226: 2228 movs r2, #40 ; 0x28
8001228: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 9;
800122a: 4b31 ldr r3, [pc, #196] ; (80012f0 <MX_LTDC_Init+0xfc>)
800122c: 2209 movs r2, #9
800122e: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 53;
8001230: 4b2f ldr r3, [pc, #188] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001232: 2235 movs r2, #53 ; 0x35
8001234: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 11;
8001236: 4b2e ldr r3, [pc, #184] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001238: 220b movs r2, #11
800123a: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 533;
800123c: 4b2c ldr r3, [pc, #176] ; (80012f0 <MX_LTDC_Init+0xfc>)
800123e: f240 2215 movw r2, #533 ; 0x215
8001242: 625a str r2, [r3, #36] ; 0x24
hltdc.Init.AccumulatedActiveH = 283;
8001244: 4b2a ldr r3, [pc, #168] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001246: f240 121b movw r2, #283 ; 0x11b
800124a: 629a str r2, [r3, #40] ; 0x28
hltdc.Init.TotalWidth = 565;
800124c: 4b28 ldr r3, [pc, #160] ; (80012f0 <MX_LTDC_Init+0xfc>)
800124e: f240 2235 movw r2, #565 ; 0x235
8001252: 62da str r2, [r3, #44] ; 0x2c
hltdc.Init.TotalHeigh = 285;
8001254: 4b26 ldr r3, [pc, #152] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001256: f240 121d movw r2, #285 ; 0x11d
800125a: 631a str r2, [r3, #48] ; 0x30
hltdc.Init.Backcolor.Blue = 0;
800125c: 4b24 ldr r3, [pc, #144] ; (80012f0 <MX_LTDC_Init+0xfc>)
800125e: 2200 movs r2, #0
8001260: f883 2034 strb.w r2, [r3, #52] ; 0x34
hltdc.Init.Backcolor.Green = 0;
8001264: 4b22 ldr r3, [pc, #136] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001266: 2200 movs r2, #0
8001268: f883 2035 strb.w r2, [r3, #53] ; 0x35
hltdc.Init.Backcolor.Red = 0;
800126c: 4b20 ldr r3, [pc, #128] ; (80012f0 <MX_LTDC_Init+0xfc>)
800126e: 2200 movs r2, #0
8001270: f883 2036 strb.w r2, [r3, #54] ; 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
8001274: 481e ldr r0, [pc, #120] ; (80012f0 <MX_LTDC_Init+0xfc>)
8001276: f005 fbd1 bl 8006a1c <HAL_LTDC_Init>
800127a: 4603 mov r3, r0
800127c: 2b00 cmp r3, #0
800127e: d001 beq.n 8001284 <MX_LTDC_Init+0x90>
{
Error_Handler();
8001280: f000 fe2a bl 8001ed8 <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
8001284: 2300 movs r3, #0
8001286: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 480;
8001288: f44f 73f0 mov.w r3, #480 ; 0x1e0
800128c: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
800128e: 2300 movs r3, #0
8001290: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 272;
8001292: f44f 7388 mov.w r3, #272 ; 0x110
8001296: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
8001298: 2302 movs r3, #2
800129a: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
800129c: 23ff movs r3, #255 ; 0xff
800129e: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
80012a0: 2300 movs r3, #0
80012a2: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
80012a4: f44f 63c0 mov.w r3, #1536 ; 0x600
80012a8: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
80012aa: 2307 movs r3, #7
80012ac: 627b str r3, [r7, #36] ; 0x24
pLayerCfg.FBStartAdress = 0xC0000000;
80012ae: f04f 4340 mov.w r3, #3221225472 ; 0xc0000000
80012b2: 62bb str r3, [r7, #40] ; 0x28
pLayerCfg.ImageWidth = 480;
80012b4: f44f 73f0 mov.w r3, #480 ; 0x1e0
80012b8: 62fb str r3, [r7, #44] ; 0x2c
pLayerCfg.ImageHeight = 272;
80012ba: f44f 7388 mov.w r3, #272 ; 0x110
80012be: 633b str r3, [r7, #48] ; 0x30
pLayerCfg.Backcolor.Blue = 0;
80012c0: 2300 movs r3, #0
80012c2: f887 3034 strb.w r3, [r7, #52] ; 0x34
pLayerCfg.Backcolor.Green = 0;
80012c6: 2300 movs r3, #0
80012c8: f887 3035 strb.w r3, [r7, #53] ; 0x35
pLayerCfg.Backcolor.Red = 0;
80012cc: 2300 movs r3, #0
80012ce: f887 3036 strb.w r3, [r7, #54] ; 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
80012d2: 1d3b adds r3, r7, #4
80012d4: 2200 movs r2, #0
80012d6: 4619 mov r1, r3
80012d8: 4805 ldr r0, [pc, #20] ; (80012f0 <MX_LTDC_Init+0xfc>)
80012da: f005 fd31 bl 8006d40 <HAL_LTDC_ConfigLayer>
80012de: 4603 mov r3, r0
80012e0: 2b00 cmp r3, #0
80012e2: d001 beq.n 80012e8 <MX_LTDC_Init+0xf4>
{
Error_Handler();
80012e4: f000 fdf8 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
80012e8: bf00 nop
80012ea: 3738 adds r7, #56 ; 0x38
80012ec: 46bd mov sp, r7
80012ee: bd80 pop {r7, pc}
80012f0: 20008678 .word 0x20008678
80012f4: 40016800 .word 0x40016800
080012f8 <MX_RTC_Init>:
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
80012f8: b580 push {r7, lr}
80012fa: b092 sub sp, #72 ; 0x48
80012fc: af00 add r7, sp, #0
/* USER CODE BEGIN RTC_Init 0 */
/* USER CODE END RTC_Init 0 */
RTC_TimeTypeDef sTime = {0};
80012fe: f107 0330 add.w r3, r7, #48 ; 0x30
8001302: 2200 movs r2, #0
8001304: 601a str r2, [r3, #0]
8001306: 605a str r2, [r3, #4]
8001308: 609a str r2, [r3, #8]
800130a: 60da str r2, [r3, #12]
800130c: 611a str r2, [r3, #16]
800130e: 615a str r2, [r3, #20]
RTC_DateTypeDef sDate = {0};
8001310: 2300 movs r3, #0
8001312: 62fb str r3, [r7, #44] ; 0x2c
RTC_AlarmTypeDef sAlarm = {0};
8001314: 463b mov r3, r7
8001316: 222c movs r2, #44 ; 0x2c
8001318: 2100 movs r1, #0
800131a: 4618 mov r0, r3
800131c: f00a fc4f bl 800bbbe <memset>
/* USER CODE BEGIN RTC_Init 1 */
/* USER CODE END RTC_Init 1 */
/** Initialize RTC Only
*/
hrtc.Instance = RTC;
8001320: 4b46 ldr r3, [pc, #280] ; (800143c <MX_RTC_Init+0x144>)
8001322: 4a47 ldr r2, [pc, #284] ; (8001440 <MX_RTC_Init+0x148>)
8001324: 601a str r2, [r3, #0]
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
8001326: 4b45 ldr r3, [pc, #276] ; (800143c <MX_RTC_Init+0x144>)
8001328: 2200 movs r2, #0
800132a: 605a str r2, [r3, #4]
hrtc.Init.AsynchPrediv = 127;
800132c: 4b43 ldr r3, [pc, #268] ; (800143c <MX_RTC_Init+0x144>)
800132e: 227f movs r2, #127 ; 0x7f
8001330: 609a str r2, [r3, #8]
hrtc.Init.SynchPrediv = 255;
8001332: 4b42 ldr r3, [pc, #264] ; (800143c <MX_RTC_Init+0x144>)
8001334: 22ff movs r2, #255 ; 0xff
8001336: 60da str r2, [r3, #12]
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
8001338: 4b40 ldr r3, [pc, #256] ; (800143c <MX_RTC_Init+0x144>)
800133a: 2200 movs r2, #0
800133c: 611a str r2, [r3, #16]
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
800133e: 4b3f ldr r3, [pc, #252] ; (800143c <MX_RTC_Init+0x144>)
8001340: 2200 movs r2, #0
8001342: 615a str r2, [r3, #20]
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
8001344: 4b3d ldr r3, [pc, #244] ; (800143c <MX_RTC_Init+0x144>)
8001346: 2200 movs r2, #0
8001348: 619a str r2, [r3, #24]
if (HAL_RTC_Init(&hrtc) != HAL_OK)
800134a: 483c ldr r0, [pc, #240] ; (800143c <MX_RTC_Init+0x144>)
800134c: f006 ffd4 bl 80082f8 <HAL_RTC_Init>
8001350: 4603 mov r3, r0
8001352: 2b00 cmp r3, #0
8001354: d001 beq.n 800135a <MX_RTC_Init+0x62>
{
Error_Handler();
8001356: f000 fdbf bl 8001ed8 <Error_Handler>
/* USER CODE END Check_RTC_BKUP */
/** Initialize RTC and set the Time and Date
*/
sTime.Hours = 0x0;
800135a: 2300 movs r3, #0
800135c: f887 3030 strb.w r3, [r7, #48] ; 0x30
sTime.Minutes = 0x0;
8001360: 2300 movs r3, #0
8001362: f887 3031 strb.w r3, [r7, #49] ; 0x31
sTime.Seconds = 0x0;
8001366: 2300 movs r3, #0
8001368: f887 3032 strb.w r3, [r7, #50] ; 0x32
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
800136c: 2300 movs r3, #0
800136e: 643b str r3, [r7, #64] ; 0x40
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
8001370: 2300 movs r3, #0
8001372: 647b str r3, [r7, #68] ; 0x44
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
8001374: f107 0330 add.w r3, r7, #48 ; 0x30
8001378: 2201 movs r2, #1
800137a: 4619 mov r1, r3
800137c: 482f ldr r0, [pc, #188] ; (800143c <MX_RTC_Init+0x144>)
800137e: f007 f837 bl 80083f0 <HAL_RTC_SetTime>
8001382: 4603 mov r3, r0
8001384: 2b00 cmp r3, #0
8001386: d001 beq.n 800138c <MX_RTC_Init+0x94>
{
Error_Handler();
8001388: f000 fda6 bl 8001ed8 <Error_Handler>
}
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
800138c: 2301 movs r3, #1
800138e: f887 302c strb.w r3, [r7, #44] ; 0x2c
sDate.Month = RTC_MONTH_JANUARY;
8001392: 2301 movs r3, #1
8001394: f887 302d strb.w r3, [r7, #45] ; 0x2d
sDate.Date = 0x1;
8001398: 2301 movs r3, #1
800139a: f887 302e strb.w r3, [r7, #46] ; 0x2e
sDate.Year = 0x0;
800139e: 2300 movs r3, #0
80013a0: f887 302f strb.w r3, [r7, #47] ; 0x2f
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
80013a4: f107 032c add.w r3, r7, #44 ; 0x2c
80013a8: 2201 movs r2, #1
80013aa: 4619 mov r1, r3
80013ac: 4823 ldr r0, [pc, #140] ; (800143c <MX_RTC_Init+0x144>)
80013ae: f007 f8dd bl 800856c <HAL_RTC_SetDate>
80013b2: 4603 mov r3, r0
80013b4: 2b00 cmp r3, #0
80013b6: d001 beq.n 80013bc <MX_RTC_Init+0xc4>
{
Error_Handler();
80013b8: f000 fd8e bl 8001ed8 <Error_Handler>
}
/** Enable the Alarm A
*/
sAlarm.AlarmTime.Hours = 0x0;
80013bc: 2300 movs r3, #0
80013be: 703b strb r3, [r7, #0]
sAlarm.AlarmTime.Minutes = 0x0;
80013c0: 2300 movs r3, #0
80013c2: 707b strb r3, [r7, #1]
sAlarm.AlarmTime.Seconds = 0x0;
80013c4: 2300 movs r3, #0
80013c6: 70bb strb r3, [r7, #2]
sAlarm.AlarmTime.SubSeconds = 0x0;
80013c8: 2300 movs r3, #0
80013ca: 607b str r3, [r7, #4]
sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
80013cc: 2300 movs r3, #0
80013ce: 613b str r3, [r7, #16]
sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET;
80013d0: 2300 movs r3, #0
80013d2: 617b str r3, [r7, #20]
sAlarm.AlarmMask = RTC_ALARMMASK_NONE;
80013d4: 2300 movs r3, #0
80013d6: 61bb str r3, [r7, #24]
sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL;
80013d8: 2300 movs r3, #0
80013da: 61fb str r3, [r7, #28]
sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_DATE;
80013dc: 2300 movs r3, #0
80013de: 623b str r3, [r7, #32]
sAlarm.AlarmDateWeekDay = 0x1;
80013e0: 2301 movs r3, #1
80013e2: f887 3024 strb.w r3, [r7, #36] ; 0x24
sAlarm.Alarm = RTC_ALARM_A;
80013e6: f44f 7380 mov.w r3, #256 ; 0x100
80013ea: 62bb str r3, [r7, #40] ; 0x28
if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
80013ec: 463b mov r3, r7
80013ee: 2201 movs r2, #1
80013f0: 4619 mov r1, r3
80013f2: 4812 ldr r0, [pc, #72] ; (800143c <MX_RTC_Init+0x144>)
80013f4: f007 f962 bl 80086bc <HAL_RTC_SetAlarm>
80013f8: 4603 mov r3, r0
80013fa: 2b00 cmp r3, #0
80013fc: d001 beq.n 8001402 <MX_RTC_Init+0x10a>
{
Error_Handler();
80013fe: f000 fd6b bl 8001ed8 <Error_Handler>
}
/** Enable the Alarm B
*/
sAlarm.Alarm = RTC_ALARM_B;
8001402: f44f 7300 mov.w r3, #512 ; 0x200
8001406: 62bb str r3, [r7, #40] ; 0x28
if (HAL_RTC_SetAlarm(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK)
8001408: 463b mov r3, r7
800140a: 2201 movs r2, #1
800140c: 4619 mov r1, r3
800140e: 480b ldr r0, [pc, #44] ; (800143c <MX_RTC_Init+0x144>)
8001410: f007 f954 bl 80086bc <HAL_RTC_SetAlarm>
8001414: 4603 mov r3, r0
8001416: 2b00 cmp r3, #0
8001418: d001 beq.n 800141e <MX_RTC_Init+0x126>
{
Error_Handler();
800141a: f000 fd5d bl 8001ed8 <Error_Handler>
}
/** Enable the TimeStamp
*/
if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_POS1) != HAL_OK)
800141e: 2202 movs r2, #2
8001420: 2100 movs r1, #0
8001422: 4806 ldr r0, [pc, #24] ; (800143c <MX_RTC_Init+0x144>)
8001424: f007 fad4 bl 80089d0 <HAL_RTCEx_SetTimeStamp>
8001428: 4603 mov r3, r0
800142a: 2b00 cmp r3, #0
800142c: d001 beq.n 8001432 <MX_RTC_Init+0x13a>
{
Error_Handler();
800142e: f000 fd53 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN RTC_Init 2 */
/* USER CODE END RTC_Init 2 */
}
8001432: bf00 nop
8001434: 3748 adds r7, #72 ; 0x48
8001436: 46bd mov sp, r7
8001438: bd80 pop {r7, pc}
800143a: bf00 nop
800143c: 20008844 .word 0x20008844
8001440: 40002800 .word 0x40002800
08001444 <MX_SPI2_Init>:
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
8001444: b580 push {r7, lr}
8001446: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
8001448: 4b1b ldr r3, [pc, #108] ; (80014b8 <MX_SPI2_Init+0x74>)
800144a: 4a1c ldr r2, [pc, #112] ; (80014bc <MX_SPI2_Init+0x78>)
800144c: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
800144e: 4b1a ldr r3, [pc, #104] ; (80014b8 <MX_SPI2_Init+0x74>)
8001450: f44f 7282 mov.w r2, #260 ; 0x104
8001454: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
8001456: 4b18 ldr r3, [pc, #96] ; (80014b8 <MX_SPI2_Init+0x74>)
8001458: 2200 movs r2, #0
800145a: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
800145c: 4b16 ldr r3, [pc, #88] ; (80014b8 <MX_SPI2_Init+0x74>)
800145e: f44f 7240 mov.w r2, #768 ; 0x300
8001462: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
8001464: 4b14 ldr r3, [pc, #80] ; (80014b8 <MX_SPI2_Init+0x74>)
8001466: 2200 movs r2, #0
8001468: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
800146a: 4b13 ldr r3, [pc, #76] ; (80014b8 <MX_SPI2_Init+0x74>)
800146c: 2200 movs r2, #0
800146e: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;
8001470: 4b11 ldr r3, [pc, #68] ; (80014b8 <MX_SPI2_Init+0x74>)
8001472: f44f 2280 mov.w r2, #262144 ; 0x40000
8001476: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8001478: 4b0f ldr r3, [pc, #60] ; (80014b8 <MX_SPI2_Init+0x74>)
800147a: 2200 movs r2, #0
800147c: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
800147e: 4b0e ldr r3, [pc, #56] ; (80014b8 <MX_SPI2_Init+0x74>)
8001480: 2200 movs r2, #0
8001482: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
8001484: 4b0c ldr r3, [pc, #48] ; (80014b8 <MX_SPI2_Init+0x74>)
8001486: 2200 movs r2, #0
8001488: 625a str r2, [r3, #36] ; 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800148a: 4b0b ldr r3, [pc, #44] ; (80014b8 <MX_SPI2_Init+0x74>)
800148c: 2200 movs r2, #0
800148e: 629a str r2, [r3, #40] ; 0x28
hspi2.Init.CRCPolynomial = 7;
8001490: 4b09 ldr r3, [pc, #36] ; (80014b8 <MX_SPI2_Init+0x74>)
8001492: 2207 movs r2, #7
8001494: 62da str r2, [r3, #44] ; 0x2c
hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
8001496: 4b08 ldr r3, [pc, #32] ; (80014b8 <MX_SPI2_Init+0x74>)
8001498: 2200 movs r2, #0
800149a: 631a str r2, [r3, #48] ; 0x30
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
800149c: 4b06 ldr r3, [pc, #24] ; (80014b8 <MX_SPI2_Init+0x74>)
800149e: 2208 movs r2, #8
80014a0: 635a str r2, [r3, #52] ; 0x34
if (HAL_SPI_Init(&hspi2) != HAL_OK)
80014a2: 4805 ldr r0, [pc, #20] ; (80014b8 <MX_SPI2_Init+0x74>)
80014a4: f007 fb69 bl 8008b7a <HAL_SPI_Init>
80014a8: 4603 mov r3, r0
80014aa: 2b00 cmp r3, #0
80014ac: d001 beq.n 80014b2 <MX_SPI2_Init+0x6e>
{
Error_Handler();
80014ae: f000 fd13 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
80014b2: bf00 nop
80014b4: bd80 pop {r7, pc}
80014b6: bf00 nop
80014b8: 20008488 .word 0x20008488
80014bc: 40003800 .word 0x40003800
080014c0 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
80014c0: b580 push {r7, lr}
80014c2: b088 sub sp, #32
80014c4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80014c6: f107 0310 add.w r3, r7, #16
80014ca: 2200 movs r2, #0
80014cc: 601a str r2, [r3, #0]
80014ce: 605a str r2, [r3, #4]
80014d0: 609a str r2, [r3, #8]
80014d2: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80014d4: 1d3b adds r3, r7, #4
80014d6: 2200 movs r2, #0
80014d8: 601a str r2, [r3, #0]
80014da: 605a str r2, [r3, #4]
80014dc: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
80014de: 4b20 ldr r3, [pc, #128] ; (8001560 <MX_TIM1_Init+0xa0>)
80014e0: 4a20 ldr r2, [pc, #128] ; (8001564 <MX_TIM1_Init+0xa4>)
80014e2: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
80014e4: 4b1e ldr r3, [pc, #120] ; (8001560 <MX_TIM1_Init+0xa0>)
80014e6: 2200 movs r2, #0
80014e8: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
80014ea: 4b1d ldr r3, [pc, #116] ; (8001560 <MX_TIM1_Init+0xa0>)
80014ec: 2200 movs r2, #0
80014ee: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
80014f0: 4b1b ldr r3, [pc, #108] ; (8001560 <MX_TIM1_Init+0xa0>)
80014f2: f64f 72ff movw r2, #65535 ; 0xffff
80014f6: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80014f8: 4b19 ldr r3, [pc, #100] ; (8001560 <MX_TIM1_Init+0xa0>)
80014fa: 2200 movs r2, #0
80014fc: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
80014fe: 4b18 ldr r3, [pc, #96] ; (8001560 <MX_TIM1_Init+0xa0>)
8001500: 2200 movs r2, #0
8001502: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001504: 4b16 ldr r3, [pc, #88] ; (8001560 <MX_TIM1_Init+0xa0>)
8001506: 2200 movs r2, #0
8001508: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
800150a: 4815 ldr r0, [pc, #84] ; (8001560 <MX_TIM1_Init+0xa0>)
800150c: f007 fbc7 bl 8008c9e <HAL_TIM_Base_Init>
8001510: 4603 mov r3, r0
8001512: 2b00 cmp r3, #0
8001514: d001 beq.n 800151a <MX_TIM1_Init+0x5a>
{
Error_Handler();
8001516: f000 fcdf bl 8001ed8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800151a: f44f 5380 mov.w r3, #4096 ; 0x1000
800151e: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001520: f107 0310 add.w r3, r7, #16
8001524: 4619 mov r1, r3
8001526: 480e ldr r0, [pc, #56] ; (8001560 <MX_TIM1_Init+0xa0>)
8001528: f007 fe7a bl 8009220 <HAL_TIM_ConfigClockSource>
800152c: 4603 mov r3, r0
800152e: 2b00 cmp r3, #0
8001530: d001 beq.n 8001536 <MX_TIM1_Init+0x76>
{
Error_Handler();
8001532: f000 fcd1 bl 8001ed8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001536: 2300 movs r3, #0
8001538: 607b str r3, [r7, #4]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
800153a: 2300 movs r3, #0
800153c: 60bb str r3, [r7, #8]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800153e: 2300 movs r3, #0
8001540: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8001542: 1d3b adds r3, r7, #4
8001544: 4619 mov r1, r3
8001546: 4806 ldr r0, [pc, #24] ; (8001560 <MX_TIM1_Init+0xa0>)
8001548: f008 fbae bl 8009ca8 <HAL_TIMEx_MasterConfigSynchronization>
800154c: 4603 mov r3, r0
800154e: 2b00 cmp r3, #0
8001550: d001 beq.n 8001556 <MX_TIM1_Init+0x96>
{
Error_Handler();
8001552: f000 fcc1 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
8001556: bf00 nop
8001558: 3720 adds r7, #32
800155a: 46bd mov sp, r7
800155c: bd80 pop {r7, pc}
800155e: bf00 nop
8001560: 20008864 .word 0x20008864
8001564: 40010000 .word 0x40010000
08001568 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
8001568: b580 push {r7, lr}
800156a: b088 sub sp, #32
800156c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800156e: f107 0310 add.w r3, r7, #16
8001572: 2200 movs r2, #0
8001574: 601a str r2, [r3, #0]
8001576: 605a str r2, [r3, #4]
8001578: 609a str r2, [r3, #8]
800157a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800157c: 1d3b adds r3, r7, #4
800157e: 2200 movs r2, #0
8001580: 601a str r2, [r3, #0]
8001582: 605a str r2, [r3, #4]
8001584: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
8001586: 4b1e ldr r3, [pc, #120] ; (8001600 <MX_TIM2_Init+0x98>)
8001588: f04f 4280 mov.w r2, #1073741824 ; 0x40000000
800158c: 601a str r2, [r3, #0]
htim2.Init.Prescaler = 0;
800158e: 4b1c ldr r3, [pc, #112] ; (8001600 <MX_TIM2_Init+0x98>)
8001590: 2200 movs r2, #0
8001592: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
8001594: 4b1a ldr r3, [pc, #104] ; (8001600 <MX_TIM2_Init+0x98>)
8001596: 2200 movs r2, #0
8001598: 609a str r2, [r3, #8]
htim2.Init.Period = 4294967295;
800159a: 4b19 ldr r3, [pc, #100] ; (8001600 <MX_TIM2_Init+0x98>)
800159c: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
80015a0: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80015a2: 4b17 ldr r3, [pc, #92] ; (8001600 <MX_TIM2_Init+0x98>)
80015a4: 2200 movs r2, #0
80015a6: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80015a8: 4b15 ldr r3, [pc, #84] ; (8001600 <MX_TIM2_Init+0x98>)
80015aa: 2200 movs r2, #0
80015ac: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
80015ae: 4814 ldr r0, [pc, #80] ; (8001600 <MX_TIM2_Init+0x98>)
80015b0: f007 fb75 bl 8008c9e <HAL_TIM_Base_Init>
80015b4: 4603 mov r3, r0
80015b6: 2b00 cmp r3, #0
80015b8: d001 beq.n 80015be <MX_TIM2_Init+0x56>
{
Error_Handler();
80015ba: f000 fc8d bl 8001ed8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80015be: f44f 5380 mov.w r3, #4096 ; 0x1000
80015c2: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
80015c4: f107 0310 add.w r3, r7, #16
80015c8: 4619 mov r1, r3
80015ca: 480d ldr r0, [pc, #52] ; (8001600 <MX_TIM2_Init+0x98>)
80015cc: f007 fe28 bl 8009220 <HAL_TIM_ConfigClockSource>
80015d0: 4603 mov r3, r0
80015d2: 2b00 cmp r3, #0
80015d4: d001 beq.n 80015da <MX_TIM2_Init+0x72>
{
Error_Handler();
80015d6: f000 fc7f bl 8001ed8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80015da: 2300 movs r3, #0
80015dc: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80015de: 2300 movs r3, #0
80015e0: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
80015e2: 1d3b adds r3, r7, #4
80015e4: 4619 mov r1, r3
80015e6: 4806 ldr r0, [pc, #24] ; (8001600 <MX_TIM2_Init+0x98>)
80015e8: f008 fb5e bl 8009ca8 <HAL_TIMEx_MasterConfigSynchronization>
80015ec: 4603 mov r3, r0
80015ee: 2b00 cmp r3, #0
80015f0: d001 beq.n 80015f6 <MX_TIM2_Init+0x8e>
{
Error_Handler();
80015f2: f000 fc71 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
}
80015f6: bf00 nop
80015f8: 3720 adds r7, #32
80015fa: 46bd mov sp, r7
80015fc: bd80 pop {r7, pc}
80015fe: bf00 nop
8001600: 20008964 .word 0x20008964
08001604 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8001604: b580 push {r7, lr}
8001606: b094 sub sp, #80 ; 0x50
8001608: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800160a: f107 0340 add.w r3, r7, #64 ; 0x40
800160e: 2200 movs r2, #0
8001610: 601a str r2, [r3, #0]
8001612: 605a str r2, [r3, #4]
8001614: 609a str r2, [r3, #8]
8001616: 60da str r2, [r3, #12]
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
8001618: f107 032c add.w r3, r7, #44 ; 0x2c
800161c: 2200 movs r2, #0
800161e: 601a str r2, [r3, #0]
8001620: 605a str r2, [r3, #4]
8001622: 609a str r2, [r3, #8]
8001624: 60da str r2, [r3, #12]
8001626: 611a str r2, [r3, #16]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001628: f107 0320 add.w r3, r7, #32
800162c: 2200 movs r2, #0
800162e: 601a str r2, [r3, #0]
8001630: 605a str r2, [r3, #4]
8001632: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8001634: 1d3b adds r3, r7, #4
8001636: 2200 movs r2, #0
8001638: 601a str r2, [r3, #0]
800163a: 605a str r2, [r3, #4]
800163c: 609a str r2, [r3, #8]
800163e: 60da str r2, [r3, #12]
8001640: 611a str r2, [r3, #16]
8001642: 615a str r2, [r3, #20]
8001644: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8001646: 4b34 ldr r3, [pc, #208] ; (8001718 <MX_TIM3_Init+0x114>)
8001648: 4a34 ldr r2, [pc, #208] ; (800171c <MX_TIM3_Init+0x118>)
800164a: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 0;
800164c: 4b32 ldr r3, [pc, #200] ; (8001718 <MX_TIM3_Init+0x114>)
800164e: 2200 movs r2, #0
8001650: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8001652: 4b31 ldr r3, [pc, #196] ; (8001718 <MX_TIM3_Init+0x114>)
8001654: 2200 movs r2, #0
8001656: 609a str r2, [r3, #8]
htim3.Init.Period = 65535;
8001658: 4b2f ldr r3, [pc, #188] ; (8001718 <MX_TIM3_Init+0x114>)
800165a: f64f 72ff movw r2, #65535 ; 0xffff
800165e: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001660: 4b2d ldr r3, [pc, #180] ; (8001718 <MX_TIM3_Init+0x114>)
8001662: 2200 movs r2, #0
8001664: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001666: 4b2c ldr r3, [pc, #176] ; (8001718 <MX_TIM3_Init+0x114>)
8001668: 2200 movs r2, #0
800166a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
800166c: 482a ldr r0, [pc, #168] ; (8001718 <MX_TIM3_Init+0x114>)
800166e: f007 fb16 bl 8008c9e <HAL_TIM_Base_Init>
8001672: 4603 mov r3, r0
8001674: 2b00 cmp r3, #0
8001676: d001 beq.n 800167c <MX_TIM3_Init+0x78>
{
Error_Handler();
8001678: f000 fc2e bl 8001ed8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800167c: f44f 5380 mov.w r3, #4096 ; 0x1000
8001680: 643b str r3, [r7, #64] ; 0x40
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8001682: f107 0340 add.w r3, r7, #64 ; 0x40
8001686: 4619 mov r1, r3
8001688: 4823 ldr r0, [pc, #140] ; (8001718 <MX_TIM3_Init+0x114>)
800168a: f007 fdc9 bl 8009220 <HAL_TIM_ConfigClockSource>
800168e: 4603 mov r3, r0
8001690: 2b00 cmp r3, #0
8001692: d001 beq.n 8001698 <MX_TIM3_Init+0x94>
{
Error_Handler();
8001694: f000 fc20 bl 8001ed8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
8001698: 481f ldr r0, [pc, #124] ; (8001718 <MX_TIM3_Init+0x114>)
800169a: f007 fb55 bl 8008d48 <HAL_TIM_PWM_Init>
800169e: 4603 mov r3, r0
80016a0: 2b00 cmp r3, #0
80016a2: d001 beq.n 80016a8 <MX_TIM3_Init+0xa4>
{
Error_Handler();
80016a4: f000 fc18 bl 8001ed8 <Error_Handler>
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_DISABLE;
80016a8: 2300 movs r3, #0
80016aa: 62fb str r3, [r7, #44] ; 0x2c
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
80016ac: 2300 movs r3, #0
80016ae: 633b str r3, [r7, #48] ; 0x30
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
80016b0: f107 032c add.w r3, r7, #44 ; 0x2c
80016b4: 4619 mov r1, r3
80016b6: 4818 ldr r0, [pc, #96] ; (8001718 <MX_TIM3_Init+0x114>)
80016b8: f007 fe6c bl 8009394 <HAL_TIM_SlaveConfigSynchro>
80016bc: 4603 mov r3, r0
80016be: 2b00 cmp r3, #0
80016c0: d001 beq.n 80016c6 <MX_TIM3_Init+0xc2>
{
Error_Handler();
80016c2: f000 fc09 bl 8001ed8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80016c6: 2300 movs r3, #0
80016c8: 623b str r3, [r7, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80016ca: 2300 movs r3, #0
80016cc: 62bb str r3, [r7, #40] ; 0x28
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80016ce: f107 0320 add.w r3, r7, #32
80016d2: 4619 mov r1, r3
80016d4: 4810 ldr r0, [pc, #64] ; (8001718 <MX_TIM3_Init+0x114>)
80016d6: f008 fae7 bl 8009ca8 <HAL_TIMEx_MasterConfigSynchronization>
80016da: 4603 mov r3, r0
80016dc: 2b00 cmp r3, #0
80016de: d001 beq.n 80016e4 <MX_TIM3_Init+0xe0>
{
Error_Handler();
80016e0: f000 fbfa bl 8001ed8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80016e4: 2360 movs r3, #96 ; 0x60
80016e6: 607b str r3, [r7, #4]
sConfigOC.Pulse = 0;
80016e8: 2300 movs r3, #0
80016ea: 60bb str r3, [r7, #8]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80016ec: 2300 movs r3, #0
80016ee: 60fb str r3, [r7, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80016f0: 2300 movs r3, #0
80016f2: 617b str r3, [r7, #20]
if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80016f4: 1d3b adds r3, r7, #4
80016f6: 2200 movs r2, #0
80016f8: 4619 mov r1, r3
80016fa: 4807 ldr r0, [pc, #28] ; (8001718 <MX_TIM3_Init+0x114>)
80016fc: f007 fc78 bl 8008ff0 <HAL_TIM_PWM_ConfigChannel>
8001700: 4603 mov r3, r0
8001702: 2b00 cmp r3, #0
8001704: d001 beq.n 800170a <MX_TIM3_Init+0x106>
{
Error_Handler();
8001706: f000 fbe7 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
HAL_TIM_MspPostInit(&htim3);
800170a: 4803 ldr r0, [pc, #12] ; (8001718 <MX_TIM3_Init+0x114>)
800170c: f002 fc16 bl 8003f3c <HAL_TIM_MspPostInit>
}
8001710: bf00 nop
8001712: 3750 adds r7, #80 ; 0x50
8001714: 46bd mov sp, r7
8001716: bd80 pop {r7, pc}
8001718: 20008638 .word 0x20008638
800171c: 40000400 .word 0x40000400
08001720 <MX_TIM5_Init>:
* @brief TIM5 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM5_Init(void)
{
8001720: b580 push {r7, lr}
8001722: b088 sub sp, #32
8001724: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001726: f107 0310 add.w r3, r7, #16
800172a: 2200 movs r2, #0
800172c: 601a str r2, [r3, #0]
800172e: 605a str r2, [r3, #4]
8001730: 609a str r2, [r3, #8]
8001732: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001734: 1d3b adds r3, r7, #4
8001736: 2200 movs r2, #0
8001738: 601a str r2, [r3, #0]
800173a: 605a str r2, [r3, #4]
800173c: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
800173e: 4b1d ldr r3, [pc, #116] ; (80017b4 <MX_TIM5_Init+0x94>)
8001740: 4a1d ldr r2, [pc, #116] ; (80017b8 <MX_TIM5_Init+0x98>)
8001742: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
8001744: 4b1b ldr r3, [pc, #108] ; (80017b4 <MX_TIM5_Init+0x94>)
8001746: 2200 movs r2, #0
8001748: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
800174a: 4b1a ldr r3, [pc, #104] ; (80017b4 <MX_TIM5_Init+0x94>)
800174c: 2200 movs r2, #0
800174e: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
8001750: 4b18 ldr r3, [pc, #96] ; (80017b4 <MX_TIM5_Init+0x94>)
8001752: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8001756: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001758: 4b16 ldr r3, [pc, #88] ; (80017b4 <MX_TIM5_Init+0x94>)
800175a: 2200 movs r2, #0
800175c: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800175e: 4b15 ldr r3, [pc, #84] ; (80017b4 <MX_TIM5_Init+0x94>)
8001760: 2200 movs r2, #0
8001762: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
8001764: 4813 ldr r0, [pc, #76] ; (80017b4 <MX_TIM5_Init+0x94>)
8001766: f007 fa9a bl 8008c9e <HAL_TIM_Base_Init>
800176a: 4603 mov r3, r0
800176c: 2b00 cmp r3, #0
800176e: d001 beq.n 8001774 <MX_TIM5_Init+0x54>
{
Error_Handler();
8001770: f000 fbb2 bl 8001ed8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001774: f44f 5380 mov.w r3, #4096 ; 0x1000
8001778: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
800177a: f107 0310 add.w r3, r7, #16
800177e: 4619 mov r1, r3
8001780: 480c ldr r0, [pc, #48] ; (80017b4 <MX_TIM5_Init+0x94>)
8001782: f007 fd4d bl 8009220 <HAL_TIM_ConfigClockSource>
8001786: 4603 mov r3, r0
8001788: 2b00 cmp r3, #0
800178a: d001 beq.n 8001790 <MX_TIM5_Init+0x70>
{
Error_Handler();
800178c: f000 fba4 bl 8001ed8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001790: 2300 movs r3, #0
8001792: 607b str r3, [r7, #4]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001794: 2300 movs r3, #0
8001796: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
8001798: 1d3b adds r3, r7, #4
800179a: 4619 mov r1, r3
800179c: 4805 ldr r0, [pc, #20] ; (80017b4 <MX_TIM5_Init+0x94>)
800179e: f008 fa83 bl 8009ca8 <HAL_TIMEx_MasterConfigSynchronization>
80017a2: 4603 mov r3, r0
80017a4: 2b00 cmp r3, #0
80017a6: d001 beq.n 80017ac <MX_TIM5_Init+0x8c>
{
Error_Handler();
80017a8: f000 fb96 bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
80017ac: bf00 nop
80017ae: 3720 adds r7, #32
80017b0: 46bd mov sp, r7
80017b2: bd80 pop {r7, pc}
80017b4: 200085f8 .word 0x200085f8
80017b8: 40000c00 .word 0x40000c00
080017bc <MX_TIM8_Init>:
* @brief TIM8 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM8_Init(void)
{
80017bc: b580 push {r7, lr}
80017be: b09a sub sp, #104 ; 0x68
80017c0: af00 add r7, sp, #0
/* USER CODE BEGIN TIM8_Init 0 */
/* USER CODE END TIM8_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80017c2: f107 0358 add.w r3, r7, #88 ; 0x58
80017c6: 2200 movs r2, #0
80017c8: 601a str r2, [r3, #0]
80017ca: 605a str r2, [r3, #4]
80017cc: 609a str r2, [r3, #8]
80017ce: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80017d0: f107 034c add.w r3, r7, #76 ; 0x4c
80017d4: 2200 movs r2, #0
80017d6: 601a str r2, [r3, #0]
80017d8: 605a str r2, [r3, #4]
80017da: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
80017dc: f107 0330 add.w r3, r7, #48 ; 0x30
80017e0: 2200 movs r2, #0
80017e2: 601a str r2, [r3, #0]
80017e4: 605a str r2, [r3, #4]
80017e6: 609a str r2, [r3, #8]
80017e8: 60da str r2, [r3, #12]
80017ea: 611a str r2, [r3, #16]
80017ec: 615a str r2, [r3, #20]
80017ee: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
80017f0: 1d3b adds r3, r7, #4
80017f2: 222c movs r2, #44 ; 0x2c
80017f4: 2100 movs r1, #0
80017f6: 4618 mov r0, r3
80017f8: f00a f9e1 bl 800bbbe <memset>
/* USER CODE BEGIN TIM8_Init 1 */
/* USER CODE END TIM8_Init 1 */
htim8.Instance = TIM8;
80017fc: 4b42 ldr r3, [pc, #264] ; (8001908 <MX_TIM8_Init+0x14c>)
80017fe: 4a43 ldr r2, [pc, #268] ; (800190c <MX_TIM8_Init+0x150>)
8001800: 601a str r2, [r3, #0]
htim8.Init.Prescaler = 0;
8001802: 4b41 ldr r3, [pc, #260] ; (8001908 <MX_TIM8_Init+0x14c>)
8001804: 2200 movs r2, #0
8001806: 605a str r2, [r3, #4]
htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
8001808: 4b3f ldr r3, [pc, #252] ; (8001908 <MX_TIM8_Init+0x14c>)
800180a: 2200 movs r2, #0
800180c: 609a str r2, [r3, #8]
htim8.Init.Period = 65535;
800180e: 4b3e ldr r3, [pc, #248] ; (8001908 <MX_TIM8_Init+0x14c>)
8001810: f64f 72ff movw r2, #65535 ; 0xffff
8001814: 60da str r2, [r3, #12]
htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001816: 4b3c ldr r3, [pc, #240] ; (8001908 <MX_TIM8_Init+0x14c>)
8001818: 2200 movs r2, #0
800181a: 611a str r2, [r3, #16]
htim8.Init.RepetitionCounter = 0;
800181c: 4b3a ldr r3, [pc, #232] ; (8001908 <MX_TIM8_Init+0x14c>)
800181e: 2200 movs r2, #0
8001820: 615a str r2, [r3, #20]
htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001822: 4b39 ldr r3, [pc, #228] ; (8001908 <MX_TIM8_Init+0x14c>)
8001824: 2200 movs r2, #0
8001826: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
8001828: 4837 ldr r0, [pc, #220] ; (8001908 <MX_TIM8_Init+0x14c>)
800182a: f007 fa38 bl 8008c9e <HAL_TIM_Base_Init>
800182e: 4603 mov r3, r0
8001830: 2b00 cmp r3, #0
8001832: d001 beq.n 8001838 <MX_TIM8_Init+0x7c>
{
Error_Handler();
8001834: f000 fb50 bl 8001ed8 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001838: f44f 5380 mov.w r3, #4096 ; 0x1000
800183c: 65bb str r3, [r7, #88] ; 0x58
if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
800183e: f107 0358 add.w r3, r7, #88 ; 0x58
8001842: 4619 mov r1, r3
8001844: 4830 ldr r0, [pc, #192] ; (8001908 <MX_TIM8_Init+0x14c>)
8001846: f007 fceb bl 8009220 <HAL_TIM_ConfigClockSource>
800184a: 4603 mov r3, r0
800184c: 2b00 cmp r3, #0
800184e: d001 beq.n 8001854 <MX_TIM8_Init+0x98>
{
Error_Handler();
8001850: f000 fb42 bl 8001ed8 <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
8001854: 482c ldr r0, [pc, #176] ; (8001908 <MX_TIM8_Init+0x14c>)
8001856: f007 fa77 bl 8008d48 <HAL_TIM_PWM_Init>
800185a: 4603 mov r3, r0
800185c: 2b00 cmp r3, #0
800185e: d001 beq.n 8001864 <MX_TIM8_Init+0xa8>
{
Error_Handler();
8001860: f000 fb3a bl 8001ed8 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001864: 2300 movs r3, #0
8001866: 64fb str r3, [r7, #76] ; 0x4c
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8001868: 2300 movs r3, #0
800186a: 653b str r3, [r7, #80] ; 0x50
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800186c: 2300 movs r3, #0
800186e: 657b str r3, [r7, #84] ; 0x54
if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
8001870: f107 034c add.w r3, r7, #76 ; 0x4c
8001874: 4619 mov r1, r3
8001876: 4824 ldr r0, [pc, #144] ; (8001908 <MX_TIM8_Init+0x14c>)
8001878: f008 fa16 bl 8009ca8 <HAL_TIMEx_MasterConfigSynchronization>
800187c: 4603 mov r3, r0
800187e: 2b00 cmp r3, #0
8001880: d001 beq.n 8001886 <MX_TIM8_Init+0xca>
{
Error_Handler();
8001882: f000 fb29 bl 8001ed8 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001886: 2360 movs r3, #96 ; 0x60
8001888: 633b str r3, [r7, #48] ; 0x30
sConfigOC.Pulse = 0;
800188a: 2300 movs r3, #0
800188c: 637b str r3, [r7, #52] ; 0x34
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
800188e: 2300 movs r3, #0
8001890: 63bb str r3, [r7, #56] ; 0x38
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001892: 2300 movs r3, #0
8001894: 643b str r3, [r7, #64] ; 0x40
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8001896: 2300 movs r3, #0
8001898: 647b str r3, [r7, #68] ; 0x44
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
800189a: 2300 movs r3, #0
800189c: 64bb str r3, [r7, #72] ; 0x48
if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
800189e: f107 0330 add.w r3, r7, #48 ; 0x30
80018a2: 220c movs r2, #12
80018a4: 4619 mov r1, r3
80018a6: 4818 ldr r0, [pc, #96] ; (8001908 <MX_TIM8_Init+0x14c>)
80018a8: f007 fba2 bl 8008ff0 <HAL_TIM_PWM_ConfigChannel>
80018ac: 4603 mov r3, r0
80018ae: 2b00 cmp r3, #0
80018b0: d001 beq.n 80018b6 <MX_TIM8_Init+0xfa>
{
Error_Handler();
80018b2: f000 fb11 bl 8001ed8 <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
80018b6: 2300 movs r3, #0
80018b8: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
80018ba: 2300 movs r3, #0
80018bc: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
80018be: 2300 movs r3, #0
80018c0: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
80018c2: 2300 movs r3, #0
80018c4: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
80018c6: 2300 movs r3, #0
80018c8: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
80018ca: f44f 5300 mov.w r3, #8192 ; 0x2000
80018ce: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.BreakFilter = 0;
80018d0: 2300 movs r3, #0
80018d2: 61fb str r3, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
80018d4: 2300 movs r3, #0
80018d6: 623b str r3, [r7, #32]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
80018d8: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80018dc: 627b str r3, [r7, #36] ; 0x24
sBreakDeadTimeConfig.Break2Filter = 0;
80018de: 2300 movs r3, #0
80018e0: 62bb str r3, [r7, #40] ; 0x28
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
80018e2: 2300 movs r3, #0
80018e4: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
80018e6: 1d3b adds r3, r7, #4
80018e8: 4619 mov r1, r3
80018ea: 4807 ldr r0, [pc, #28] ; (8001908 <MX_TIM8_Init+0x14c>)
80018ec: f008 fa6a bl 8009dc4 <HAL_TIMEx_ConfigBreakDeadTime>
80018f0: 4603 mov r3, r0
80018f2: 2b00 cmp r3, #0
80018f4: d001 beq.n 80018fa <MX_TIM8_Init+0x13e>
{
Error_Handler();
80018f6: f000 faef bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN TIM8_Init 2 */
/* USER CODE END TIM8_Init 2 */
HAL_TIM_MspPostInit(&htim8);
80018fa: 4803 ldr r0, [pc, #12] ; (8001908 <MX_TIM8_Init+0x14c>)
80018fc: f002 fb1e bl 8003f3c <HAL_TIM_MspPostInit>
}
8001900: bf00 nop
8001902: 3768 adds r7, #104 ; 0x68
8001904: 46bd mov sp, r7
8001906: bd80 pop {r7, pc}
8001908: 2000856c .word 0x2000856c
800190c: 40010400 .word 0x40010400
08001910 <MX_UART7_Init>:
* @brief UART7 Initialization Function
* @param None
* @retval None
*/
static void MX_UART7_Init(void)
{
8001910: b580 push {r7, lr}
8001912: af00 add r7, sp, #0
/* USER CODE END UART7_Init 0 */
/* USER CODE BEGIN UART7_Init 1 */
/* USER CODE END UART7_Init 1 */
huart7.Instance = UART7;
8001914: 4b14 ldr r3, [pc, #80] ; (8001968 <MX_UART7_Init+0x58>)
8001916: 4a15 ldr r2, [pc, #84] ; (800196c <MX_UART7_Init+0x5c>)
8001918: 601a str r2, [r3, #0]
huart7.Init.BaudRate = 115200;
800191a: 4b13 ldr r3, [pc, #76] ; (8001968 <MX_UART7_Init+0x58>)
800191c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8001920: 605a str r2, [r3, #4]
huart7.Init.WordLength = UART_WORDLENGTH_8B;
8001922: 4b11 ldr r3, [pc, #68] ; (8001968 <MX_UART7_Init+0x58>)
8001924: 2200 movs r2, #0
8001926: 609a str r2, [r3, #8]
huart7.Init.StopBits = UART_STOPBITS_1;
8001928: 4b0f ldr r3, [pc, #60] ; (8001968 <MX_UART7_Init+0x58>)
800192a: 2200 movs r2, #0
800192c: 60da str r2, [r3, #12]
huart7.Init.Parity = UART_PARITY_NONE;
800192e: 4b0e ldr r3, [pc, #56] ; (8001968 <MX_UART7_Init+0x58>)
8001930: 2200 movs r2, #0
8001932: 611a str r2, [r3, #16]
huart7.Init.Mode = UART_MODE_TX_RX;
8001934: 4b0c ldr r3, [pc, #48] ; (8001968 <MX_UART7_Init+0x58>)
8001936: 220c movs r2, #12
8001938: 615a str r2, [r3, #20]
huart7.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800193a: 4b0b ldr r3, [pc, #44] ; (8001968 <MX_UART7_Init+0x58>)
800193c: 2200 movs r2, #0
800193e: 619a str r2, [r3, #24]
huart7.Init.OverSampling = UART_OVERSAMPLING_16;
8001940: 4b09 ldr r3, [pc, #36] ; (8001968 <MX_UART7_Init+0x58>)
8001942: 2200 movs r2, #0
8001944: 61da str r2, [r3, #28]
huart7.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8001946: 4b08 ldr r3, [pc, #32] ; (8001968 <MX_UART7_Init+0x58>)
8001948: 2200 movs r2, #0
800194a: 621a str r2, [r3, #32]
huart7.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
800194c: 4b06 ldr r3, [pc, #24] ; (8001968 <MX_UART7_Init+0x58>)
800194e: 2200 movs r2, #0
8001950: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart7) != HAL_OK)
8001952: 4805 ldr r0, [pc, #20] ; (8001968 <MX_UART7_Init+0x58>)
8001954: f008 fad2 bl 8009efc <HAL_UART_Init>
8001958: 4603 mov r3, r0
800195a: 2b00 cmp r3, #0
800195c: d001 beq.n 8001962 <MX_UART7_Init+0x52>
{
Error_Handler();
800195e: f000 fabb bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN UART7_Init 2 */
/* USER CODE END UART7_Init 2 */
}
8001962: bf00 nop
8001964: bd80 pop {r7, pc}
8001966: bf00 nop
8001968: 200084ec .word 0x200084ec
800196c: 40007800 .word 0x40007800
08001970 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8001970: b580 push {r7, lr}
8001972: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8001974: 4b14 ldr r3, [pc, #80] ; (80019c8 <MX_USART1_UART_Init+0x58>)
8001976: 4a15 ldr r2, [pc, #84] ; (80019cc <MX_USART1_UART_Init+0x5c>)
8001978: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
800197a: 4b13 ldr r3, [pc, #76] ; (80019c8 <MX_USART1_UART_Init+0x58>)
800197c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8001980: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8001982: 4b11 ldr r3, [pc, #68] ; (80019c8 <MX_USART1_UART_Init+0x58>)
8001984: 2200 movs r2, #0
8001986: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8001988: 4b0f ldr r3, [pc, #60] ; (80019c8 <MX_USART1_UART_Init+0x58>)
800198a: 2200 movs r2, #0
800198c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800198e: 4b0e ldr r3, [pc, #56] ; (80019c8 <MX_USART1_UART_Init+0x58>)
8001990: 2200 movs r2, #0
8001992: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8001994: 4b0c ldr r3, [pc, #48] ; (80019c8 <MX_USART1_UART_Init+0x58>)
8001996: 220c movs r2, #12
8001998: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800199a: 4b0b ldr r3, [pc, #44] ; (80019c8 <MX_USART1_UART_Init+0x58>)
800199c: 2200 movs r2, #0
800199e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80019a0: 4b09 ldr r3, [pc, #36] ; (80019c8 <MX_USART1_UART_Init+0x58>)
80019a2: 2200 movs r2, #0
80019a4: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
80019a6: 4b08 ldr r3, [pc, #32] ; (80019c8 <MX_USART1_UART_Init+0x58>)
80019a8: 2200 movs r2, #0
80019aa: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
80019ac: 4b06 ldr r3, [pc, #24] ; (80019c8 <MX_USART1_UART_Init+0x58>)
80019ae: 2200 movs r2, #0
80019b0: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
80019b2: 4805 ldr r0, [pc, #20] ; (80019c8 <MX_USART1_UART_Init+0x58>)
80019b4: f008 faa2 bl 8009efc <HAL_UART_Init>
80019b8: 4603 mov r3, r0
80019ba: 2b00 cmp r3, #0
80019bc: d001 beq.n 80019c2 <MX_USART1_UART_Init+0x52>
{
Error_Handler();
80019be: f000 fa8b bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80019c2: bf00 nop
80019c4: bd80 pop {r7, pc}
80019c6: bf00 nop
80019c8: 200087b0 .word 0x200087b0
80019cc: 40011000 .word 0x40011000
080019d0 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
80019d0: b580 push {r7, lr}
80019d2: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
80019d4: 4b14 ldr r3, [pc, #80] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019d6: 4a15 ldr r2, [pc, #84] ; (8001a2c <MX_USART6_UART_Init+0x5c>)
80019d8: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
80019da: 4b13 ldr r3, [pc, #76] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019dc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80019e0: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
80019e2: 4b11 ldr r3, [pc, #68] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019e4: 2200 movs r2, #0
80019e6: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
80019e8: 4b0f ldr r3, [pc, #60] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019ea: 2200 movs r2, #0
80019ec: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
80019ee: 4b0e ldr r3, [pc, #56] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019f0: 2200 movs r2, #0
80019f2: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
80019f4: 4b0c ldr r3, [pc, #48] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019f6: 220c movs r2, #12
80019f8: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80019fa: 4b0b ldr r3, [pc, #44] ; (8001a28 <MX_USART6_UART_Init+0x58>)
80019fc: 2200 movs r2, #0
80019fe: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
8001a00: 4b09 ldr r3, [pc, #36] ; (8001a28 <MX_USART6_UART_Init+0x58>)
8001a02: 2200 movs r2, #0
8001a04: 61da str r2, [r3, #28]
huart6.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8001a06: 4b08 ldr r3, [pc, #32] ; (8001a28 <MX_USART6_UART_Init+0x58>)
8001a08: 2200 movs r2, #0
8001a0a: 621a str r2, [r3, #32]
huart6.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8001a0c: 4b06 ldr r3, [pc, #24] ; (8001a28 <MX_USART6_UART_Init+0x58>)
8001a0e: 2200 movs r2, #0
8001a10: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart6) != HAL_OK)
8001a12: 4805 ldr r0, [pc, #20] ; (8001a28 <MX_USART6_UART_Init+0x58>)
8001a14: f008 fa72 bl 8009efc <HAL_UART_Init>
8001a18: 4603 mov r3, r0
8001a1a: 2b00 cmp r3, #0
8001a1c: d001 beq.n 8001a22 <MX_USART6_UART_Init+0x52>
{
Error_Handler();
8001a1e: f000 fa5b bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
8001a22: bf00 nop
8001a24: bd80 pop {r7, pc}
8001a26: bf00 nop
8001a28: 200088a4 .word 0x200088a4
8001a2c: 40011400 .word 0x40011400
08001a30 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8001a30: b580 push {r7, lr}
8001a32: b088 sub sp, #32
8001a34: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
8001a36: 1d3b adds r3, r7, #4
8001a38: 2200 movs r2, #0
8001a3a: 601a str r2, [r3, #0]
8001a3c: 605a str r2, [r3, #4]
8001a3e: 609a str r2, [r3, #8]
8001a40: 60da str r2, [r3, #12]
8001a42: 611a str r2, [r3, #16]
8001a44: 615a str r2, [r3, #20]
8001a46: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8001a48: 4b1e ldr r3, [pc, #120] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a4a: 4a1f ldr r2, [pc, #124] ; (8001ac8 <MX_FMC_Init+0x98>)
8001a4c: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
8001a4e: 4b1d ldr r3, [pc, #116] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a50: 2200 movs r2, #0
8001a52: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
8001a54: 4b1b ldr r3, [pc, #108] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a56: 2200 movs r2, #0
8001a58: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
8001a5a: 4b1a ldr r3, [pc, #104] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a5c: 2204 movs r2, #4
8001a5e: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
8001a60: 4b18 ldr r3, [pc, #96] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a62: 2210 movs r2, #16
8001a64: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
8001a66: 4b17 ldr r3, [pc, #92] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a68: 2240 movs r2, #64 ; 0x40
8001a6a: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
8001a6c: 4b15 ldr r3, [pc, #84] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a6e: 2280 movs r2, #128 ; 0x80
8001a70: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
8001a72: 4b14 ldr r3, [pc, #80] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a74: 2200 movs r2, #0
8001a76: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
8001a78: 4b12 ldr r3, [pc, #72] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a7a: 2200 movs r2, #0
8001a7c: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
8001a7e: 4b11 ldr r3, [pc, #68] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a80: 2200 movs r2, #0
8001a82: 625a str r2, [r3, #36] ; 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
8001a84: 4b0f ldr r3, [pc, #60] ; (8001ac4 <MX_FMC_Init+0x94>)
8001a86: 2200 movs r2, #0
8001a88: 629a str r2, [r3, #40] ; 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 16;
8001a8a: 2310 movs r3, #16
8001a8c: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 16;
8001a8e: 2310 movs r3, #16
8001a90: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 16;
8001a92: 2310 movs r3, #16
8001a94: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 16;
8001a96: 2310 movs r3, #16
8001a98: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 16;
8001a9a: 2310 movs r3, #16
8001a9c: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 16;
8001a9e: 2310 movs r3, #16
8001aa0: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 16;
8001aa2: 2310 movs r3, #16
8001aa4: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
8001aa6: 1d3b adds r3, r7, #4
8001aa8: 4619 mov r1, r3
8001aaa: 4806 ldr r0, [pc, #24] ; (8001ac4 <MX_FMC_Init+0x94>)
8001aac: f006 ffe6 bl 8008a7c <HAL_SDRAM_Init>
8001ab0: 4603 mov r3, r0
8001ab2: 2b00 cmp r3, #0
8001ab4: d001 beq.n 8001aba <MX_FMC_Init+0x8a>
{
Error_Handler( );
8001ab6: f000 fa0f bl 8001ed8 <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8001aba: bf00 nop
8001abc: 3720 adds r7, #32
8001abe: 46bd mov sp, r7
8001ac0: bd80 pop {r7, pc}
8001ac2: bf00 nop
8001ac4: 200089a4 .word 0x200089a4
8001ac8: a0000140 .word 0xa0000140
08001acc <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001acc: b580 push {r7, lr}
8001ace: b090 sub sp, #64 ; 0x40
8001ad0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001ad2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ad6: 2200 movs r2, #0
8001ad8: 601a str r2, [r3, #0]
8001ada: 605a str r2, [r3, #4]
8001adc: 609a str r2, [r3, #8]
8001ade: 60da str r2, [r3, #12]
8001ae0: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8001ae2: 4bb0 ldr r3, [pc, #704] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001ae4: 6b1b ldr r3, [r3, #48] ; 0x30
8001ae6: 4aaf ldr r2, [pc, #700] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001ae8: f043 0310 orr.w r3, r3, #16
8001aec: 6313 str r3, [r2, #48] ; 0x30
8001aee: 4bad ldr r3, [pc, #692] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001af0: 6b1b ldr r3, [r3, #48] ; 0x30
8001af2: f003 0310 and.w r3, r3, #16
8001af6: 62bb str r3, [r7, #40] ; 0x28
8001af8: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_GPIOB_CLK_ENABLE();
8001afa: 4baa ldr r3, [pc, #680] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001afc: 6b1b ldr r3, [r3, #48] ; 0x30
8001afe: 4aa9 ldr r2, [pc, #676] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b00: f043 0302 orr.w r3, r3, #2
8001b04: 6313 str r3, [r2, #48] ; 0x30
8001b06: 4ba7 ldr r3, [pc, #668] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b08: 6b1b ldr r3, [r3, #48] ; 0x30
8001b0a: f003 0302 and.w r3, r3, #2
8001b0e: 627b str r3, [r7, #36] ; 0x24
8001b10: 6a7b ldr r3, [r7, #36] ; 0x24
__HAL_RCC_GPIOA_CLK_ENABLE();
8001b12: 4ba4 ldr r3, [pc, #656] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b14: 6b1b ldr r3, [r3, #48] ; 0x30
8001b16: 4aa3 ldr r2, [pc, #652] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b18: f043 0301 orr.w r3, r3, #1
8001b1c: 6313 str r3, [r2, #48] ; 0x30
8001b1e: 4ba1 ldr r3, [pc, #644] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b20: 6b1b ldr r3, [r3, #48] ; 0x30
8001b22: f003 0301 and.w r3, r3, #1
8001b26: 623b str r3, [r7, #32]
8001b28: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOG_CLK_ENABLE();
8001b2a: 4b9e ldr r3, [pc, #632] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b2c: 6b1b ldr r3, [r3, #48] ; 0x30
8001b2e: 4a9d ldr r2, [pc, #628] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b30: f043 0340 orr.w r3, r3, #64 ; 0x40
8001b34: 6313 str r3, [r2, #48] ; 0x30
8001b36: 4b9b ldr r3, [pc, #620] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b38: 6b1b ldr r3, [r3, #48] ; 0x30
8001b3a: f003 0340 and.w r3, r3, #64 ; 0x40
8001b3e: 61fb str r3, [r7, #28]
8001b40: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8001b42: 4b98 ldr r3, [pc, #608] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b44: 6b1b ldr r3, [r3, #48] ; 0x30
8001b46: 4a97 ldr r2, [pc, #604] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b48: f443 7300 orr.w r3, r3, #512 ; 0x200
8001b4c: 6313 str r3, [r2, #48] ; 0x30
8001b4e: 4b95 ldr r3, [pc, #596] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b50: 6b1b ldr r3, [r3, #48] ; 0x30
8001b52: f403 7300 and.w r3, r3, #512 ; 0x200
8001b56: 61bb str r3, [r7, #24]
8001b58: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001b5a: 4b92 ldr r3, [pc, #584] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b5c: 6b1b ldr r3, [r3, #48] ; 0x30
8001b5e: 4a91 ldr r2, [pc, #580] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b60: f043 0308 orr.w r3, r3, #8
8001b64: 6313 str r3, [r2, #48] ; 0x30
8001b66: 4b8f ldr r3, [pc, #572] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b68: 6b1b ldr r3, [r3, #48] ; 0x30
8001b6a: f003 0308 and.w r3, r3, #8
8001b6e: 617b str r3, [r7, #20]
8001b70: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOI_CLK_ENABLE();
8001b72: 4b8c ldr r3, [pc, #560] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b74: 6b1b ldr r3, [r3, #48] ; 0x30
8001b76: 4a8b ldr r2, [pc, #556] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b78: f443 7380 orr.w r3, r3, #256 ; 0x100
8001b7c: 6313 str r3, [r2, #48] ; 0x30
8001b7e: 4b89 ldr r3, [pc, #548] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b80: 6b1b ldr r3, [r3, #48] ; 0x30
8001b82: f403 7380 and.w r3, r3, #256 ; 0x100
8001b86: 613b str r3, [r7, #16]
8001b88: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOK_CLK_ENABLE();
8001b8a: 4b86 ldr r3, [pc, #536] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b8c: 6b1b ldr r3, [r3, #48] ; 0x30
8001b8e: 4a85 ldr r2, [pc, #532] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b90: f443 6380 orr.w r3, r3, #1024 ; 0x400
8001b94: 6313 str r3, [r2, #48] ; 0x30
8001b96: 4b83 ldr r3, [pc, #524] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001b98: 6b1b ldr r3, [r3, #48] ; 0x30
8001b9a: f403 6380 and.w r3, r3, #1024 ; 0x400
8001b9e: 60fb str r3, [r7, #12]
8001ba0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ba2: 4b80 ldr r3, [pc, #512] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001ba4: 6b1b ldr r3, [r3, #48] ; 0x30
8001ba6: 4a7f ldr r2, [pc, #508] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001ba8: f043 0304 orr.w r3, r3, #4
8001bac: 6313 str r3, [r2, #48] ; 0x30
8001bae: 4b7d ldr r3, [pc, #500] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bb0: 6b1b ldr r3, [r3, #48] ; 0x30
8001bb2: f003 0304 and.w r3, r3, #4
8001bb6: 60bb str r3, [r7, #8]
8001bb8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOF_CLK_ENABLE();
8001bba: 4b7a ldr r3, [pc, #488] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bbc: 6b1b ldr r3, [r3, #48] ; 0x30
8001bbe: 4a79 ldr r2, [pc, #484] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bc0: f043 0320 orr.w r3, r3, #32
8001bc4: 6313 str r3, [r2, #48] ; 0x30
8001bc6: 4b77 ldr r3, [pc, #476] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bc8: 6b1b ldr r3, [r3, #48] ; 0x30
8001bca: f003 0320 and.w r3, r3, #32
8001bce: 607b str r3, [r7, #4]
8001bd0: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOH_CLK_ENABLE();
8001bd2: 4b74 ldr r3, [pc, #464] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bd4: 6b1b ldr r3, [r3, #48] ; 0x30
8001bd6: 4a73 ldr r2, [pc, #460] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001bd8: f043 0380 orr.w r3, r3, #128 ; 0x80
8001bdc: 6313 str r3, [r2, #48] ; 0x30
8001bde: 4b71 ldr r3, [pc, #452] ; (8001da4 <MX_GPIO_Init+0x2d8>)
8001be0: 6b1b ldr r3, [r3, #48] ; 0x30
8001be2: f003 0380 and.w r3, r3, #128 ; 0x80
8001be6: 603b str r3, [r7, #0]
8001be8: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, LED14_Pin|LED15_Pin, GPIO_PIN_RESET);
8001bea: 2200 movs r2, #0
8001bec: 2160 movs r1, #96 ; 0x60
8001bee: 486e ldr r0, [pc, #440] ; (8001da8 <MX_GPIO_Init+0x2dc>)
8001bf0: f004 f94a bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(OTG_FS_PowerSwitchOn_GPIO_Port, OTG_FS_PowerSwitchOn_Pin, GPIO_PIN_SET);
8001bf4: 2201 movs r2, #1
8001bf6: 2120 movs r1, #32
8001bf8: 486c ldr r0, [pc, #432] ; (8001dac <MX_GPIO_Init+0x2e0>)
8001bfa: f004 f945 bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED16_GPIO_Port, LED16_Pin, GPIO_PIN_RESET);
8001bfe: 2200 movs r2, #0
8001c00: 2108 movs r1, #8
8001c02: 486a ldr r0, [pc, #424] ; (8001dac <MX_GPIO_Init+0x2e0>)
8001c04: f004 f940 bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, GPIO_PIN_RESET);
8001c08: 2200 movs r2, #0
8001c0a: 2108 movs r1, #8
8001c0c: 4868 ldr r0, [pc, #416] ; (8001db0 <MX_GPIO_Init+0x2e4>)
8001c0e: f004 f93b bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_Port, LCD_BL_CTRL_Pin, GPIO_PIN_SET);
8001c12: 2201 movs r2, #1
8001c14: 2108 movs r1, #8
8001c16: 4867 ldr r0, [pc, #412] ; (8001db4 <MX_GPIO_Init+0x2e8>)
8001c18: f004 f936 bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LCD_DISP_GPIO_Port, LCD_DISP_Pin, GPIO_PIN_SET);
8001c1c: 2201 movs r2, #1
8001c1e: f44f 5180 mov.w r1, #4096 ; 0x1000
8001c22: 4863 ldr r0, [pc, #396] ; (8001db0 <MX_GPIO_Init+0x2e4>)
8001c24: f004 f930 bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOH, LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001c28: 2200 movs r2, #0
8001c2a: f645 6140 movw r1, #24128 ; 0x5e40
8001c2e: 4862 ldr r0, [pc, #392] ; (8001db8 <MX_GPIO_Init+0x2ec>)
8001c30: f004 f92a bl 8005e88 <HAL_GPIO_WritePin>
|LED2_Pin|LED18_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(EXT_RST_GPIO_Port, EXT_RST_Pin, GPIO_PIN_RESET);
8001c34: 2200 movs r2, #0
8001c36: 2108 movs r1, #8
8001c38: 4860 ldr r0, [pc, #384] ; (8001dbc <MX_GPIO_Init+0x2f0>)
8001c3a: f004 f925 bl 8005e88 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PE3 */
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001c3e: 2308 movs r3, #8
8001c40: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001c42: 2300 movs r3, #0
8001c44: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c46: 2300 movs r3, #0
8001c48: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001c4a: f107 032c add.w r3, r7, #44 ; 0x2c
8001c4e: 4619 mov r1, r3
8001c50: 4855 ldr r0, [pc, #340] ; (8001da8 <MX_GPIO_Init+0x2dc>)
8001c52: f003 fe4d bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_D7_Pin ULPI_D6_Pin ULPI_D5_Pin ULPI_D2_Pin
ULPI_D1_Pin ULPI_D4_Pin */
GPIO_InitStruct.Pin = ULPI_D7_Pin|ULPI_D6_Pin|ULPI_D5_Pin|ULPI_D2_Pin
8001c56: f643 0323 movw r3, #14371 ; 0x3823
8001c5a: 62fb str r3, [r7, #44] ; 0x2c
|ULPI_D1_Pin|ULPI_D4_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c5c: 2302 movs r3, #2
8001c5e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c60: 2300 movs r3, #0
8001c62: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c64: 2303 movs r3, #3
8001c66: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001c68: 230a movs r3, #10
8001c6a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001c6c: f107 032c add.w r3, r7, #44 ; 0x2c
8001c70: 4619 mov r1, r3
8001c72: 4853 ldr r0, [pc, #332] ; (8001dc0 <MX_GPIO_Init+0x2f4>)
8001c74: f003 fe3c bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : BP2_Pin BP1_Pin */
GPIO_InitStruct.Pin = BP2_Pin|BP1_Pin;
8001c78: f44f 4301 mov.w r3, #33024 ; 0x8100
8001c7c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001c7e: 2300 movs r3, #0
8001c80: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c82: 2300 movs r3, #0
8001c84: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001c86: f107 032c add.w r3, r7, #44 ; 0x2c
8001c8a: 4619 mov r1, r3
8001c8c: 484d ldr r0, [pc, #308] ; (8001dc4 <MX_GPIO_Init+0x2f8>)
8001c8e: f003 fe2f bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : LED14_Pin LED15_Pin */
GPIO_InitStruct.Pin = LED14_Pin|LED15_Pin;
8001c92: 2360 movs r3, #96 ; 0x60
8001c94: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001c96: 2301 movs r3, #1
8001c98: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c9a: 2300 movs r3, #0
8001c9c: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001c9e: 2300 movs r3, #0
8001ca0: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001ca2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ca6: 4619 mov r1, r3
8001ca8: 483f ldr r0, [pc, #252] ; (8001da8 <MX_GPIO_Init+0x2dc>)
8001caa: f003 fe21 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_VBUS_Pin */
GPIO_InitStruct.Pin = OTG_FS_VBUS_Pin;
8001cae: f44f 5380 mov.w r3, #4096 ; 0x1000
8001cb2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001cb4: 2300 movs r3, #0
8001cb6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001cb8: 2300 movs r3, #0
8001cba: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(OTG_FS_VBUS_GPIO_Port, &GPIO_InitStruct);
8001cbc: f107 032c add.w r3, r7, #44 ; 0x2c
8001cc0: 4619 mov r1, r3
8001cc2: 4841 ldr r0, [pc, #260] ; (8001dc8 <MX_GPIO_Init+0x2fc>)
8001cc4: f003 fe14 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : Audio_INT_Pin */
GPIO_InitStruct.Pin = Audio_INT_Pin;
8001cc8: 2340 movs r3, #64 ; 0x40
8001cca: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001ccc: 4b3f ldr r3, [pc, #252] ; (8001dcc <MX_GPIO_Init+0x300>)
8001cce: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001cd0: 2300 movs r3, #0
8001cd2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(Audio_INT_GPIO_Port, &GPIO_InitStruct);
8001cd4: f107 032c add.w r3, r7, #44 ; 0x2c
8001cd8: 4619 mov r1, r3
8001cda: 4834 ldr r0, [pc, #208] ; (8001dac <MX_GPIO_Init+0x2e0>)
8001cdc: f003 fe08 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_FS_PowerSwitchOn_Pin LED16_Pin */
GPIO_InitStruct.Pin = OTG_FS_PowerSwitchOn_Pin|LED16_Pin;
8001ce0: 2328 movs r3, #40 ; 0x28
8001ce2: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001ce4: 2301 movs r3, #1
8001ce6: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001ce8: 2300 movs r3, #0
8001cea: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001cec: 2300 movs r3, #0
8001cee: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001cf0: f107 032c add.w r3, r7, #44 ; 0x2c
8001cf4: 4619 mov r1, r3
8001cf6: 482d ldr r0, [pc, #180] ; (8001dac <MX_GPIO_Init+0x2e0>)
8001cf8: f003 fdfa bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : LED3_Pin LCD_DISP_Pin */
GPIO_InitStruct.Pin = LED3_Pin|LCD_DISP_Pin;
8001cfc: f241 0308 movw r3, #4104 ; 0x1008
8001d00: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001d02: 2301 movs r3, #1
8001d04: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d06: 2300 movs r3, #0
8001d08: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001d0a: 2300 movs r3, #0
8001d0c: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8001d0e: f107 032c add.w r3, r7, #44 ; 0x2c
8001d12: 4619 mov r1, r3
8001d14: 4826 ldr r0, [pc, #152] ; (8001db0 <MX_GPIO_Init+0x2e4>)
8001d16: f003 fdeb bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : uSD_Detect_Pin */
GPIO_InitStruct.Pin = uSD_Detect_Pin;
8001d1a: f44f 5300 mov.w r3, #8192 ; 0x2000
8001d1e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001d20: 2300 movs r3, #0
8001d22: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d24: 2300 movs r3, #0
8001d26: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(uSD_Detect_GPIO_Port, &GPIO_InitStruct);
8001d28: f107 032c add.w r3, r7, #44 ; 0x2c
8001d2c: 4619 mov r1, r3
8001d2e: 4828 ldr r0, [pc, #160] ; (8001dd0 <MX_GPIO_Init+0x304>)
8001d30: f003 fdde bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : LCD_BL_CTRL_Pin */
GPIO_InitStruct.Pin = LCD_BL_CTRL_Pin;
8001d34: 2308 movs r3, #8
8001d36: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001d38: 2301 movs r3, #1
8001d3a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d3c: 2300 movs r3, #0
8001d3e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001d40: 2300 movs r3, #0
8001d42: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_Port, &GPIO_InitStruct);
8001d44: f107 032c add.w r3, r7, #44 ; 0x2c
8001d48: 4619 mov r1, r3
8001d4a: 481a ldr r0, [pc, #104] ; (8001db4 <MX_GPIO_Init+0x2e8>)
8001d4c: f003 fdd0 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OverCurrent_Pin */
GPIO_InitStruct.Pin = OTG_FS_OverCurrent_Pin;
8001d50: 2310 movs r3, #16
8001d52: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001d54: 2300 movs r3, #0
8001d56: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d58: 2300 movs r3, #0
8001d5a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(OTG_FS_OverCurrent_GPIO_Port, &GPIO_InitStruct);
8001d5c: f107 032c add.w r3, r7, #44 ; 0x2c
8001d60: 4619 mov r1, r3
8001d62: 4812 ldr r0, [pc, #72] ; (8001dac <MX_GPIO_Init+0x2e0>)
8001d64: f003 fdc4 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : TP3_Pin NC2_Pin */
GPIO_InitStruct.Pin = TP3_Pin|NC2_Pin;
8001d68: f248 0304 movw r3, #32772 ; 0x8004
8001d6c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001d6e: 2300 movs r3, #0
8001d70: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d72: 2300 movs r3, #0
8001d74: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001d76: f107 032c add.w r3, r7, #44 ; 0x2c
8001d7a: 4619 mov r1, r3
8001d7c: 480e ldr r0, [pc, #56] ; (8001db8 <MX_GPIO_Init+0x2ec>)
8001d7e: f003 fdb7 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : LED13_Pin LED17_Pin LED11_Pin LED12_Pin
LED2_Pin LED18_Pin */
GPIO_InitStruct.Pin = LED13_Pin|LED17_Pin|LED11_Pin|LED12_Pin
8001d82: f645 6340 movw r3, #24128 ; 0x5e40
8001d86: 62fb str r3, [r7, #44] ; 0x2c
|LED2_Pin|LED18_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001d88: 2301 movs r3, #1
8001d8a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001d8c: 2300 movs r3, #0
8001d8e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001d90: 2300 movs r3, #0
8001d92: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8001d94: f107 032c add.w r3, r7, #44 ; 0x2c
8001d98: 4619 mov r1, r3
8001d9a: 4807 ldr r0, [pc, #28] ; (8001db8 <MX_GPIO_Init+0x2ec>)
8001d9c: f003 fda8 bl 80058f0 <HAL_GPIO_Init>
8001da0: e018 b.n 8001dd4 <MX_GPIO_Init+0x308>
8001da2: bf00 nop
8001da4: 40023800 .word 0x40023800
8001da8: 40021000 .word 0x40021000
8001dac: 40020c00 .word 0x40020c00
8001db0: 40022000 .word 0x40022000
8001db4: 40022800 .word 0x40022800
8001db8: 40021c00 .word 0x40021c00
8001dbc: 40021800 .word 0x40021800
8001dc0: 40020400 .word 0x40020400
8001dc4: 40020000 .word 0x40020000
8001dc8: 40022400 .word 0x40022400
8001dcc: 10120000 .word 0x10120000
8001dd0: 40020800 .word 0x40020800
/*Configure GPIO pin : LCD_INT_Pin */
GPIO_InitStruct.Pin = LCD_INT_Pin;
8001dd4: f44f 5300 mov.w r3, #8192 ; 0x2000
8001dd8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8001dda: 4b2c ldr r3, [pc, #176] ; (8001e8c <MX_GPIO_Init+0x3c0>)
8001ddc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001dde: 2300 movs r3, #0
8001de0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_INT_GPIO_Port, &GPIO_InitStruct);
8001de2: f107 032c add.w r3, r7, #44 ; 0x2c
8001de6: 4619 mov r1, r3
8001de8: 4829 ldr r0, [pc, #164] ; (8001e90 <MX_GPIO_Init+0x3c4>)
8001dea: f003 fd81 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : ULPI_NXT_Pin */
GPIO_InitStruct.Pin = ULPI_NXT_Pin;
8001dee: 2310 movs r3, #16
8001df0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001df2: 2302 movs r3, #2
8001df4: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001df6: 2300 movs r3, #0
8001df8: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001dfa: 2303 movs r3, #3
8001dfc: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001dfe: 230a movs r3, #10
8001e00: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(ULPI_NXT_GPIO_Port, &GPIO_InitStruct);
8001e02: f107 032c add.w r3, r7, #44 ; 0x2c
8001e06: 4619 mov r1, r3
8001e08: 4822 ldr r0, [pc, #136] ; (8001e94 <MX_GPIO_Init+0x3c8>)
8001e0a: f003 fd71 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : BP_JOYSTICK_Pin RMII_RXER_Pin */
GPIO_InitStruct.Pin = BP_JOYSTICK_Pin|RMII_RXER_Pin;
8001e0e: 2384 movs r3, #132 ; 0x84
8001e10: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8001e12: 2300 movs r3, #0
8001e14: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e16: 2300 movs r3, #0
8001e18: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001e1a: f107 032c add.w r3, r7, #44 ; 0x2c
8001e1e: 4619 mov r1, r3
8001e20: 481d ldr r0, [pc, #116] ; (8001e98 <MX_GPIO_Init+0x3cc>)
8001e22: f003 fd65 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_STP_Pin ULPI_DIR_Pin */
GPIO_InitStruct.Pin = ULPI_STP_Pin|ULPI_DIR_Pin;
8001e26: 2305 movs r3, #5
8001e28: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001e2a: 2302 movs r3, #2
8001e2c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e2e: 2300 movs r3, #0
8001e30: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001e32: 2303 movs r3, #3
8001e34: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001e36: 230a movs r3, #10
8001e38: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001e3a: f107 032c add.w r3, r7, #44 ; 0x2c
8001e3e: 4619 mov r1, r3
8001e40: 4816 ldr r0, [pc, #88] ; (8001e9c <MX_GPIO_Init+0x3d0>)
8001e42: f003 fd55 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pin : EXT_RST_Pin */
GPIO_InitStruct.Pin = EXT_RST_Pin;
8001e46: 2308 movs r3, #8
8001e48: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001e4a: 2301 movs r3, #1
8001e4c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e4e: 2300 movs r3, #0
8001e50: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001e52: 2300 movs r3, #0
8001e54: 63bb str r3, [r7, #56] ; 0x38
HAL_GPIO_Init(EXT_RST_GPIO_Port, &GPIO_InitStruct);
8001e56: f107 032c add.w r3, r7, #44 ; 0x2c
8001e5a: 4619 mov r1, r3
8001e5c: 480e ldr r0, [pc, #56] ; (8001e98 <MX_GPIO_Init+0x3cc>)
8001e5e: f003 fd47 bl 80058f0 <HAL_GPIO_Init>
/*Configure GPIO pins : ULPI_CLK_Pin ULPI_D0_Pin */
GPIO_InitStruct.Pin = ULPI_CLK_Pin|ULPI_D0_Pin;
8001e62: 2328 movs r3, #40 ; 0x28
8001e64: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001e66: 2302 movs r3, #2
8001e68: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e6a: 2300 movs r3, #0
8001e6c: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001e6e: 2303 movs r3, #3
8001e70: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS;
8001e72: 230a movs r3, #10
8001e74: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001e76: f107 032c add.w r3, r7, #44 ; 0x2c
8001e7a: 4619 mov r1, r3
8001e7c: 4808 ldr r0, [pc, #32] ; (8001ea0 <MX_GPIO_Init+0x3d4>)
8001e7e: f003 fd37 bl 80058f0 <HAL_GPIO_Init>
}
8001e82: bf00 nop
8001e84: 3740 adds r7, #64 ; 0x40
8001e86: 46bd mov sp, r7
8001e88: bd80 pop {r7, pc}
8001e8a: bf00 nop
8001e8c: 10120000 .word 0x10120000
8001e90: 40022000 .word 0x40022000
8001e94: 40021c00 .word 0x40021c00
8001e98: 40021800 .word 0x40021800
8001e9c: 40020800 .word 0x40020800
8001ea0: 40020000 .word 0x40020000
08001ea4 <StartDefaultTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartDefaultTask */
void StartDefaultTask(void const * argument)
{
8001ea4: b580 push {r7, lr}
8001ea6: b082 sub sp, #8
8001ea8: af00 add r7, sp, #0
8001eaa: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 5 */
/* Infinite loop */
for(;;)
{
osDelay(1);
8001eac: 2001 movs r0, #1
8001eae: f008 fdf3 bl 800aa98 <osDelay>
8001eb2: e7fb b.n 8001eac <StartDefaultTask+0x8>
08001eb4 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8001eb4: b580 push {r7, lr}
8001eb6: b082 sub sp, #8
8001eb8: af00 add r7, sp, #0
8001eba: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
8001ebc: 687b ldr r3, [r7, #4]
8001ebe: 681b ldr r3, [r3, #0]
8001ec0: 4a04 ldr r2, [pc, #16] ; (8001ed4 <HAL_TIM_PeriodElapsedCallback+0x20>)
8001ec2: 4293 cmp r3, r2
8001ec4: d101 bne.n 8001eca <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8001ec6: f002 faff bl 80044c8 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8001eca: bf00 nop
8001ecc: 3708 adds r7, #8
8001ece: 46bd mov sp, r7
8001ed0: bd80 pop {r7, pc}
8001ed2: bf00 nop
8001ed4: 40001000 .word 0x40001000
08001ed8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001ed8: b480 push {r7}
8001eda: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001edc: b672 cpsid i
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001ede: e7fe b.n 8001ede <Error_Handler+0x6>
08001ee0 <I2Cx_MspInit>:
* @brief Initializes I2C MSP.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_MspInit(I2C_HandleTypeDef *i2c_handler)
{
8001ee0: b580 push {r7, lr}
8001ee2: b08c sub sp, #48 ; 0x30
8001ee4: af00 add r7, sp, #0
8001ee6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef gpio_init_structure;
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
8001ee8: 687b ldr r3, [r7, #4]
8001eea: 4a51 ldr r2, [pc, #324] ; (8002030 <I2Cx_MspInit+0x150>)
8001eec: 4293 cmp r3, r2
8001eee: d14d bne.n 8001f8c <I2Cx_MspInit+0xac>
{
/* AUDIO and LCD I2C MSP init */
/*** Configure the GPIOs ***/
/* Enable GPIO clock */
DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
8001ef0: 4b50 ldr r3, [pc, #320] ; (8002034 <I2Cx_MspInit+0x154>)
8001ef2: 6b1b ldr r3, [r3, #48] ; 0x30
8001ef4: 4a4f ldr r2, [pc, #316] ; (8002034 <I2Cx_MspInit+0x154>)
8001ef6: f043 0380 orr.w r3, r3, #128 ; 0x80
8001efa: 6313 str r3, [r2, #48] ; 0x30
8001efc: 4b4d ldr r3, [pc, #308] ; (8002034 <I2Cx_MspInit+0x154>)
8001efe: 6b1b ldr r3, [r3, #48] ; 0x30
8001f00: f003 0380 and.w r3, r3, #128 ; 0x80
8001f04: 61bb str r3, [r7, #24]
8001f06: 69bb ldr r3, [r7, #24]
/* Configure I2C Tx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SCL_PIN;
8001f08: 2380 movs r3, #128 ; 0x80
8001f0a: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
8001f0c: 2312 movs r3, #18
8001f0e: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
8001f10: 2300 movs r3, #0
8001f12: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8001f14: 2302 movs r3, #2
8001f16: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_AUDIO_I2Cx_SCL_SDA_AF;
8001f18: 2304 movs r3, #4
8001f1a: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8001f1c: f107 031c add.w r3, r7, #28
8001f20: 4619 mov r1, r3
8001f22: 4845 ldr r0, [pc, #276] ; (8002038 <I2Cx_MspInit+0x158>)
8001f24: f003 fce4 bl 80058f0 <HAL_GPIO_Init>
/* Configure I2C Rx as alternate function */
gpio_init_structure.Pin = DISCOVERY_AUDIO_I2Cx_SDA_PIN;
8001f28: f44f 7380 mov.w r3, #256 ; 0x100
8001f2c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_AUDIO_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8001f2e: f107 031c add.w r3, r7, #28
8001f32: 4619 mov r1, r3
8001f34: 4840 ldr r0, [pc, #256] ; (8002038 <I2Cx_MspInit+0x158>)
8001f36: f003 fcdb bl 80058f0 <HAL_GPIO_Init>
/*** Configure the I2C peripheral ***/
/* Enable I2C clock */
DISCOVERY_AUDIO_I2Cx_CLK_ENABLE();
8001f3a: 4b3e ldr r3, [pc, #248] ; (8002034 <I2Cx_MspInit+0x154>)
8001f3c: 6c1b ldr r3, [r3, #64] ; 0x40
8001f3e: 4a3d ldr r2, [pc, #244] ; (8002034 <I2Cx_MspInit+0x154>)
8001f40: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8001f44: 6413 str r3, [r2, #64] ; 0x40
8001f46: 4b3b ldr r3, [pc, #236] ; (8002034 <I2Cx_MspInit+0x154>)
8001f48: 6c1b ldr r3, [r3, #64] ; 0x40
8001f4a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8001f4e: 617b str r3, [r7, #20]
8001f50: 697b ldr r3, [r7, #20]
/* Force the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_FORCE_RESET();
8001f52: 4b38 ldr r3, [pc, #224] ; (8002034 <I2Cx_MspInit+0x154>)
8001f54: 6a1b ldr r3, [r3, #32]
8001f56: 4a37 ldr r2, [pc, #220] ; (8002034 <I2Cx_MspInit+0x154>)
8001f58: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8001f5c: 6213 str r3, [r2, #32]
/* Release the I2C peripheral clock reset */
DISCOVERY_AUDIO_I2Cx_RELEASE_RESET();
8001f5e: 4b35 ldr r3, [pc, #212] ; (8002034 <I2Cx_MspInit+0x154>)
8001f60: 6a1b ldr r3, [r3, #32]
8001f62: 4a34 ldr r2, [pc, #208] ; (8002034 <I2Cx_MspInit+0x154>)
8001f64: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8001f68: 6213 str r3, [r2, #32]
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_EV_IRQn, 0x0F, 0);
8001f6a: 2200 movs r2, #0
8001f6c: 210f movs r1, #15
8001f6e: 2048 movs r0, #72 ; 0x48
8001f70: f002 ff7e bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_EV_IRQn);
8001f74: 2048 movs r0, #72 ; 0x48
8001f76: f002 ff97 bl 8004ea8 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_AUDIO_I2Cx_ER_IRQn, 0x0F, 0);
8001f7a: 2200 movs r2, #0
8001f7c: 210f movs r1, #15
8001f7e: 2049 movs r0, #73 ; 0x49
8001f80: f002 ff76 bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_AUDIO_I2Cx_ER_IRQn);
8001f84: 2049 movs r0, #73 ; 0x49
8001f86: f002 ff8f bl 8004ea8 <HAL_NVIC_EnableIRQ>
/* Enable and set I2Cx Interrupt to a lower priority */
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
}
}
8001f8a: e04d b.n 8002028 <I2Cx_MspInit+0x148>
DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_CLK_ENABLE();
8001f8c: 4b29 ldr r3, [pc, #164] ; (8002034 <I2Cx_MspInit+0x154>)
8001f8e: 6b1b ldr r3, [r3, #48] ; 0x30
8001f90: 4a28 ldr r2, [pc, #160] ; (8002034 <I2Cx_MspInit+0x154>)
8001f92: f043 0302 orr.w r3, r3, #2
8001f96: 6313 str r3, [r2, #48] ; 0x30
8001f98: 4b26 ldr r3, [pc, #152] ; (8002034 <I2Cx_MspInit+0x154>)
8001f9a: 6b1b ldr r3, [r3, #48] ; 0x30
8001f9c: f003 0302 and.w r3, r3, #2
8001fa0: 613b str r3, [r7, #16]
8001fa2: 693b ldr r3, [r7, #16]
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SCL_PIN;
8001fa4: f44f 7380 mov.w r3, #256 ; 0x100
8001fa8: 61fb str r3, [r7, #28]
gpio_init_structure.Mode = GPIO_MODE_AF_OD;
8001faa: 2312 movs r3, #18
8001fac: 623b str r3, [r7, #32]
gpio_init_structure.Pull = GPIO_NOPULL;
8001fae: 2300 movs r3, #0
8001fb0: 627b str r3, [r7, #36] ; 0x24
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8001fb2: 2302 movs r3, #2
8001fb4: 62bb str r3, [r7, #40] ; 0x28
gpio_init_structure.Alternate = DISCOVERY_EXT_I2Cx_SCL_SDA_AF;
8001fb6: 2304 movs r3, #4
8001fb8: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8001fba: f107 031c add.w r3, r7, #28
8001fbe: 4619 mov r1, r3
8001fc0: 481e ldr r0, [pc, #120] ; (800203c <I2Cx_MspInit+0x15c>)
8001fc2: f003 fc95 bl 80058f0 <HAL_GPIO_Init>
gpio_init_structure.Pin = DISCOVERY_EXT_I2Cx_SDA_PIN;
8001fc6: f44f 7300 mov.w r3, #512 ; 0x200
8001fca: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DISCOVERY_EXT_I2Cx_SCL_SDA_GPIO_PORT, &gpio_init_structure);
8001fcc: f107 031c add.w r3, r7, #28
8001fd0: 4619 mov r1, r3
8001fd2: 481a ldr r0, [pc, #104] ; (800203c <I2Cx_MspInit+0x15c>)
8001fd4: f003 fc8c bl 80058f0 <HAL_GPIO_Init>
DISCOVERY_EXT_I2Cx_CLK_ENABLE();
8001fd8: 4b16 ldr r3, [pc, #88] ; (8002034 <I2Cx_MspInit+0x154>)
8001fda: 6c1b ldr r3, [r3, #64] ; 0x40
8001fdc: 4a15 ldr r2, [pc, #84] ; (8002034 <I2Cx_MspInit+0x154>)
8001fde: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8001fe2: 6413 str r3, [r2, #64] ; 0x40
8001fe4: 4b13 ldr r3, [pc, #76] ; (8002034 <I2Cx_MspInit+0x154>)
8001fe6: 6c1b ldr r3, [r3, #64] ; 0x40
8001fe8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001fec: 60fb str r3, [r7, #12]
8001fee: 68fb ldr r3, [r7, #12]
DISCOVERY_EXT_I2Cx_FORCE_RESET();
8001ff0: 4b10 ldr r3, [pc, #64] ; (8002034 <I2Cx_MspInit+0x154>)
8001ff2: 6a1b ldr r3, [r3, #32]
8001ff4: 4a0f ldr r2, [pc, #60] ; (8002034 <I2Cx_MspInit+0x154>)
8001ff6: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8001ffa: 6213 str r3, [r2, #32]
DISCOVERY_EXT_I2Cx_RELEASE_RESET();
8001ffc: 4b0d ldr r3, [pc, #52] ; (8002034 <I2Cx_MspInit+0x154>)
8001ffe: 6a1b ldr r3, [r3, #32]
8002000: 4a0c ldr r2, [pc, #48] ; (8002034 <I2Cx_MspInit+0x154>)
8002002: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
8002006: 6213 str r3, [r2, #32]
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_EV_IRQn, 0x0F, 0);
8002008: 2200 movs r2, #0
800200a: 210f movs r1, #15
800200c: 201f movs r0, #31
800200e: f002 ff2f bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_EV_IRQn);
8002012: 201f movs r0, #31
8002014: f002 ff48 bl 8004ea8 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(DISCOVERY_EXT_I2Cx_ER_IRQn, 0x0F, 0);
8002018: 2200 movs r2, #0
800201a: 210f movs r1, #15
800201c: 2020 movs r0, #32
800201e: f002 ff27 bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DISCOVERY_EXT_I2Cx_ER_IRQn);
8002022: 2020 movs r0, #32
8002024: f002 ff40 bl 8004ea8 <HAL_NVIC_EnableIRQ>
}
8002028: bf00 nop
800202a: 3730 adds r7, #48 ; 0x30
800202c: 46bd mov sp, r7
800202e: bd80 pop {r7, pc}
8002030: 20000100 .word 0x20000100
8002034: 40023800 .word 0x40023800
8002038: 40021c00 .word 0x40021c00
800203c: 40020400 .word 0x40020400
08002040 <I2Cx_Init>:
* @brief Initializes I2C HAL.
* @param i2c_handler : I2C handler
* @retval None
*/
static void I2Cx_Init(I2C_HandleTypeDef *i2c_handler)
{
8002040: b580 push {r7, lr}
8002042: b082 sub sp, #8
8002044: af00 add r7, sp, #0
8002046: 6078 str r0, [r7, #4]
if(HAL_I2C_GetState(i2c_handler) == HAL_I2C_STATE_RESET)
8002048: 6878 ldr r0, [r7, #4]
800204a: f004 fa25 bl 8006498 <HAL_I2C_GetState>
800204e: 4603 mov r3, r0
8002050: 2b00 cmp r3, #0
8002052: d125 bne.n 80020a0 <I2Cx_Init+0x60>
{
if (i2c_handler == (I2C_HandleTypeDef*)(&hI2cAudioHandler))
8002054: 687b ldr r3, [r7, #4]
8002056: 4a14 ldr r2, [pc, #80] ; (80020a8 <I2Cx_Init+0x68>)
8002058: 4293 cmp r3, r2
800205a: d103 bne.n 8002064 <I2Cx_Init+0x24>
{
/* Audio and LCD I2C configuration */
i2c_handler->Instance = DISCOVERY_AUDIO_I2Cx;
800205c: 687b ldr r3, [r7, #4]
800205e: 4a13 ldr r2, [pc, #76] ; (80020ac <I2Cx_Init+0x6c>)
8002060: 601a str r2, [r3, #0]
8002062: e002 b.n 800206a <I2Cx_Init+0x2a>
}
else
{
/* External, camera and Arduino connector I2C configuration */
i2c_handler->Instance = DISCOVERY_EXT_I2Cx;
8002064: 687b ldr r3, [r7, #4]
8002066: 4a12 ldr r2, [pc, #72] ; (80020b0 <I2Cx_Init+0x70>)
8002068: 601a str r2, [r3, #0]
}
i2c_handler->Init.Timing = DISCOVERY_I2Cx_TIMING;
800206a: 687b ldr r3, [r7, #4]
800206c: 4a11 ldr r2, [pc, #68] ; (80020b4 <I2Cx_Init+0x74>)
800206e: 605a str r2, [r3, #4]
i2c_handler->Init.OwnAddress1 = 0;
8002070: 687b ldr r3, [r7, #4]
8002072: 2200 movs r2, #0
8002074: 609a str r2, [r3, #8]
i2c_handler->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8002076: 687b ldr r3, [r7, #4]
8002078: 2201 movs r2, #1
800207a: 60da str r2, [r3, #12]
i2c_handler->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800207c: 687b ldr r3, [r7, #4]
800207e: 2200 movs r2, #0
8002080: 611a str r2, [r3, #16]
i2c_handler->Init.OwnAddress2 = 0;
8002082: 687b ldr r3, [r7, #4]
8002084: 2200 movs r2, #0
8002086: 615a str r2, [r3, #20]
i2c_handler->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8002088: 687b ldr r3, [r7, #4]
800208a: 2200 movs r2, #0
800208c: 61da str r2, [r3, #28]
i2c_handler->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800208e: 687b ldr r3, [r7, #4]
8002090: 2200 movs r2, #0
8002092: 621a str r2, [r3, #32]
/* Init the I2C */
I2Cx_MspInit(i2c_handler);
8002094: 6878 ldr r0, [r7, #4]
8002096: f7ff ff23 bl 8001ee0 <I2Cx_MspInit>
HAL_I2C_Init(i2c_handler);
800209a: 6878 ldr r0, [r7, #4]
800209c: f003 ff0e bl 8005ebc <HAL_I2C_Init>
}
}
80020a0: bf00 nop
80020a2: 3708 adds r7, #8
80020a4: 46bd mov sp, r7
80020a6: bd80 pop {r7, pc}
80020a8: 20000100 .word 0x20000100
80020ac: 40005c00 .word 0x40005c00
80020b0: 40005400 .word 0x40005400
80020b4: 40912732 .word 0x40912732
080020b8 <I2Cx_ReadMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
80020b8: b580 push {r7, lr}
80020ba: b08a sub sp, #40 ; 0x28
80020bc: af04 add r7, sp, #16
80020be: 60f8 str r0, [r7, #12]
80020c0: 4608 mov r0, r1
80020c2: 4611 mov r1, r2
80020c4: 461a mov r2, r3
80020c6: 4603 mov r3, r0
80020c8: 72fb strb r3, [r7, #11]
80020ca: 460b mov r3, r1
80020cc: 813b strh r3, [r7, #8]
80020ce: 4613 mov r3, r2
80020d0: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
80020d2: 2300 movs r3, #0
80020d4: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Read(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
80020d6: 7afb ldrb r3, [r7, #11]
80020d8: b299 uxth r1, r3
80020da: 88f8 ldrh r0, [r7, #6]
80020dc: 893a ldrh r2, [r7, #8]
80020de: f44f 737a mov.w r3, #1000 ; 0x3e8
80020e2: 9302 str r3, [sp, #8]
80020e4: 8cbb ldrh r3, [r7, #36] ; 0x24
80020e6: 9301 str r3, [sp, #4]
80020e8: 6a3b ldr r3, [r7, #32]
80020ea: 9300 str r3, [sp, #0]
80020ec: 4603 mov r3, r0
80020ee: 68f8 ldr r0, [r7, #12]
80020f0: f004 f8b8 bl 8006264 <HAL_I2C_Mem_Read>
80020f4: 4603 mov r3, r0
80020f6: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
80020f8: 7dfb ldrb r3, [r7, #23]
80020fa: 2b00 cmp r3, #0
80020fc: d004 beq.n 8002108 <I2Cx_ReadMultiple+0x50>
{
/* I2C error occurred */
I2Cx_Error(i2c_handler, Addr);
80020fe: 7afb ldrb r3, [r7, #11]
8002100: 4619 mov r1, r3
8002102: 68f8 ldr r0, [r7, #12]
8002104: f000 f832 bl 800216c <I2Cx_Error>
}
return status;
8002108: 7dfb ldrb r3, [r7, #23]
}
800210a: 4618 mov r0, r3
800210c: 3718 adds r7, #24
800210e: 46bd mov sp, r7
8002110: bd80 pop {r7, pc}
08002112 <I2Cx_WriteMultiple>:
uint8_t Addr,
uint16_t Reg,
uint16_t MemAddress,
uint8_t *Buffer,
uint16_t Length)
{
8002112: b580 push {r7, lr}
8002114: b08a sub sp, #40 ; 0x28
8002116: af04 add r7, sp, #16
8002118: 60f8 str r0, [r7, #12]
800211a: 4608 mov r0, r1
800211c: 4611 mov r1, r2
800211e: 461a mov r2, r3
8002120: 4603 mov r3, r0
8002122: 72fb strb r3, [r7, #11]
8002124: 460b mov r3, r1
8002126: 813b strh r3, [r7, #8]
8002128: 4613 mov r3, r2
800212a: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef status = HAL_OK;
800212c: 2300 movs r3, #0
800212e: 75fb strb r3, [r7, #23]
status = HAL_I2C_Mem_Write(i2c_handler, Addr, (uint16_t)Reg, MemAddress, Buffer, Length, 1000);
8002130: 7afb ldrb r3, [r7, #11]
8002132: b299 uxth r1, r3
8002134: 88f8 ldrh r0, [r7, #6]
8002136: 893a ldrh r2, [r7, #8]
8002138: f44f 737a mov.w r3, #1000 ; 0x3e8
800213c: 9302 str r3, [sp, #8]
800213e: 8cbb ldrh r3, [r7, #36] ; 0x24
8002140: 9301 str r3, [sp, #4]
8002142: 6a3b ldr r3, [r7, #32]
8002144: 9300 str r3, [sp, #0]
8002146: 4603 mov r3, r0
8002148: 68f8 ldr r0, [r7, #12]
800214a: f003 ff77 bl 800603c <HAL_I2C_Mem_Write>
800214e: 4603 mov r3, r0
8002150: 75fb strb r3, [r7, #23]
/* Check the communication status */
if(status != HAL_OK)
8002152: 7dfb ldrb r3, [r7, #23]
8002154: 2b00 cmp r3, #0
8002156: d004 beq.n 8002162 <I2Cx_WriteMultiple+0x50>
{
/* Re-Initiaize the I2C Bus */
I2Cx_Error(i2c_handler, Addr);
8002158: 7afb ldrb r3, [r7, #11]
800215a: 4619 mov r1, r3
800215c: 68f8 ldr r0, [r7, #12]
800215e: f000 f805 bl 800216c <I2Cx_Error>
}
return status;
8002162: 7dfb ldrb r3, [r7, #23]
}
8002164: 4618 mov r0, r3
8002166: 3718 adds r7, #24
8002168: 46bd mov sp, r7
800216a: bd80 pop {r7, pc}
0800216c <I2Cx_Error>:
* @param i2c_handler : I2C handler
* @param Addr: I2C Address
* @retval None
*/
static void I2Cx_Error(I2C_HandleTypeDef *i2c_handler, uint8_t Addr)
{
800216c: b580 push {r7, lr}
800216e: b082 sub sp, #8
8002170: af00 add r7, sp, #0
8002172: 6078 str r0, [r7, #4]
8002174: 460b mov r3, r1
8002176: 70fb strb r3, [r7, #3]
/* De-initialize the I2C communication bus */
HAL_I2C_DeInit(i2c_handler);
8002178: 6878 ldr r0, [r7, #4]
800217a: f003 ff2f bl 8005fdc <HAL_I2C_DeInit>
/* Re-Initialize the I2C communication bus */
I2Cx_Init(i2c_handler);
800217e: 6878 ldr r0, [r7, #4]
8002180: f7ff ff5e bl 8002040 <I2Cx_Init>
}
8002184: bf00 nop
8002186: 3708 adds r7, #8
8002188: 46bd mov sp, r7
800218a: bd80 pop {r7, pc}
0800218c <TS_IO_Init>:
/**
* @brief Initializes Touchscreen low level.
* @retval None
*/
void TS_IO_Init(void)
{
800218c: b580 push {r7, lr}
800218e: af00 add r7, sp, #0
I2Cx_Init(&hI2cAudioHandler);
8002190: 4802 ldr r0, [pc, #8] ; (800219c <TS_IO_Init+0x10>)
8002192: f7ff ff55 bl 8002040 <I2Cx_Init>
}
8002196: bf00 nop
8002198: bd80 pop {r7, pc}
800219a: bf00 nop
800219c: 20000100 .word 0x20000100
080021a0 <TS_IO_Write>:
* @param Reg: Reg address
* @param Value: Data to be written
* @retval None
*/
void TS_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
{
80021a0: b580 push {r7, lr}
80021a2: b084 sub sp, #16
80021a4: af02 add r7, sp, #8
80021a6: 4603 mov r3, r0
80021a8: 71fb strb r3, [r7, #7]
80021aa: 460b mov r3, r1
80021ac: 71bb strb r3, [r7, #6]
80021ae: 4613 mov r3, r2
80021b0: 717b strb r3, [r7, #5]
I2Cx_WriteMultiple(&hI2cAudioHandler, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT,(uint8_t*)&Value, 1);
80021b2: 79bb ldrb r3, [r7, #6]
80021b4: b29a uxth r2, r3
80021b6: 79f9 ldrb r1, [r7, #7]
80021b8: 2301 movs r3, #1
80021ba: 9301 str r3, [sp, #4]
80021bc: 1d7b adds r3, r7, #5
80021be: 9300 str r3, [sp, #0]
80021c0: 2301 movs r3, #1
80021c2: 4803 ldr r0, [pc, #12] ; (80021d0 <TS_IO_Write+0x30>)
80021c4: f7ff ffa5 bl 8002112 <I2Cx_WriteMultiple>
}
80021c8: bf00 nop
80021ca: 3708 adds r7, #8
80021cc: 46bd mov sp, r7
80021ce: bd80 pop {r7, pc}
80021d0: 20000100 .word 0x20000100
080021d4 <TS_IO_Read>:
* @param Addr: I2C address
* @param Reg: Reg address
* @retval Data to be read
*/
uint8_t TS_IO_Read(uint8_t Addr, uint8_t Reg)
{
80021d4: b580 push {r7, lr}
80021d6: b086 sub sp, #24
80021d8: af02 add r7, sp, #8
80021da: 4603 mov r3, r0
80021dc: 460a mov r2, r1
80021de: 71fb strb r3, [r7, #7]
80021e0: 4613 mov r3, r2
80021e2: 71bb strb r3, [r7, #6]
uint8_t read_value = 0;
80021e4: 2300 movs r3, #0
80021e6: 73fb strb r3, [r7, #15]
I2Cx_ReadMultiple(&hI2cAudioHandler, Addr, Reg, I2C_MEMADD_SIZE_8BIT, (uint8_t*)&read_value, 1);
80021e8: 79bb ldrb r3, [r7, #6]
80021ea: b29a uxth r2, r3
80021ec: 79f9 ldrb r1, [r7, #7]
80021ee: 2301 movs r3, #1
80021f0: 9301 str r3, [sp, #4]
80021f2: f107 030f add.w r3, r7, #15
80021f6: 9300 str r3, [sp, #0]
80021f8: 2301 movs r3, #1
80021fa: 4804 ldr r0, [pc, #16] ; (800220c <TS_IO_Read+0x38>)
80021fc: f7ff ff5c bl 80020b8 <I2Cx_ReadMultiple>
return read_value;
8002200: 7bfb ldrb r3, [r7, #15]
}
8002202: 4618 mov r0, r3
8002204: 3710 adds r7, #16
8002206: 46bd mov sp, r7
8002208: bd80 pop {r7, pc}
800220a: bf00 nop
800220c: 20000100 .word 0x20000100
08002210 <TS_IO_Delay>:
* @brief TS delay
* @param Delay: Delay in ms
* @retval None
*/
void TS_IO_Delay(uint32_t Delay)
{
8002210: b580 push {r7, lr}
8002212: b082 sub sp, #8
8002214: af00 add r7, sp, #0
8002216: 6078 str r0, [r7, #4]
HAL_Delay(Delay);
8002218: 6878 ldr r0, [r7, #4]
800221a: f002 f975 bl 8004508 <HAL_Delay>
}
800221e: bf00 nop
8002220: 3708 adds r7, #8
8002222: 46bd mov sp, r7
8002224: bd80 pop {r7, pc}
...
08002228 <BSP_LCD_Init>:
/**
* @brief Initializes the LCD.
* @retval LCD state
*/
uint8_t BSP_LCD_Init(void)
{
8002228: b580 push {r7, lr}
800222a: af00 add r7, sp, #0
/* Select the used LCD */
/* The RK043FN48H LCD 480x272 is selected */
/* Timing Configuration */
hLtdcHandler.Init.HorizontalSync = (RK043FN48H_HSYNC - 1);
800222c: 4b31 ldr r3, [pc, #196] ; (80022f4 <BSP_LCD_Init+0xcc>)
800222e: 2228 movs r2, #40 ; 0x28
8002230: 615a str r2, [r3, #20]
hLtdcHandler.Init.VerticalSync = (RK043FN48H_VSYNC - 1);
8002232: 4b30 ldr r3, [pc, #192] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002234: 2209 movs r2, #9
8002236: 619a str r2, [r3, #24]
hLtdcHandler.Init.AccumulatedHBP = (RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
8002238: 4b2e ldr r3, [pc, #184] ; (80022f4 <BSP_LCD_Init+0xcc>)
800223a: 2235 movs r2, #53 ; 0x35
800223c: 61da str r2, [r3, #28]
hLtdcHandler.Init.AccumulatedVBP = (RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
800223e: 4b2d ldr r3, [pc, #180] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002240: 220b movs r2, #11
8002242: 621a str r2, [r3, #32]
hLtdcHandler.Init.AccumulatedActiveH = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP - 1);
8002244: 4b2b ldr r3, [pc, #172] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002246: f240 121b movw r2, #283 ; 0x11b
800224a: 629a str r2, [r3, #40] ; 0x28
hLtdcHandler.Init.AccumulatedActiveW = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP - 1);
800224c: 4b29 ldr r3, [pc, #164] ; (80022f4 <BSP_LCD_Init+0xcc>)
800224e: f240 2215 movw r2, #533 ; 0x215
8002252: 625a str r2, [r3, #36] ; 0x24
hLtdcHandler.Init.TotalHeigh = (RK043FN48H_HEIGHT + RK043FN48H_VSYNC + RK043FN48H_VBP + RK043FN48H_VFP - 1);
8002254: 4b27 ldr r3, [pc, #156] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002256: f240 121d movw r2, #285 ; 0x11d
800225a: 631a str r2, [r3, #48] ; 0x30
hLtdcHandler.Init.TotalWidth = (RK043FN48H_WIDTH + RK043FN48H_HSYNC + RK043FN48H_HBP + RK043FN48H_HFP - 1);
800225c: 4b25 ldr r3, [pc, #148] ; (80022f4 <BSP_LCD_Init+0xcc>)
800225e: f240 2235 movw r2, #565 ; 0x235
8002262: 62da str r2, [r3, #44] ; 0x2c
/* LCD clock configuration */
BSP_LCD_ClockConfig(&hLtdcHandler, NULL);
8002264: 2100 movs r1, #0
8002266: 4823 ldr r0, [pc, #140] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002268: f000 fdbe bl 8002de8 <BSP_LCD_ClockConfig>
/* Initialize the LCD pixel width and pixel height */
hLtdcHandler.LayerCfg->ImageWidth = RK043FN48H_WIDTH;
800226c: 4b21 ldr r3, [pc, #132] ; (80022f4 <BSP_LCD_Init+0xcc>)
800226e: f44f 72f0 mov.w r2, #480 ; 0x1e0
8002272: 661a str r2, [r3, #96] ; 0x60
hLtdcHandler.LayerCfg->ImageHeight = RK043FN48H_HEIGHT;
8002274: 4b1f ldr r3, [pc, #124] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002276: f44f 7288 mov.w r2, #272 ; 0x110
800227a: 665a str r2, [r3, #100] ; 0x64
/* Background value */
hLtdcHandler.Init.Backcolor.Blue = 0;
800227c: 4b1d ldr r3, [pc, #116] ; (80022f4 <BSP_LCD_Init+0xcc>)
800227e: 2200 movs r2, #0
8002280: f883 2034 strb.w r2, [r3, #52] ; 0x34
hLtdcHandler.Init.Backcolor.Green = 0;
8002284: 4b1b ldr r3, [pc, #108] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002286: 2200 movs r2, #0
8002288: f883 2035 strb.w r2, [r3, #53] ; 0x35
hLtdcHandler.Init.Backcolor.Red = 0;
800228c: 4b19 ldr r3, [pc, #100] ; (80022f4 <BSP_LCD_Init+0xcc>)
800228e: 2200 movs r2, #0
8002290: f883 2036 strb.w r2, [r3, #54] ; 0x36
/* Polarity */
hLtdcHandler.Init.HSPolarity = LTDC_HSPOLARITY_AL;
8002294: 4b17 ldr r3, [pc, #92] ; (80022f4 <BSP_LCD_Init+0xcc>)
8002296: 2200 movs r2, #0
8002298: 605a str r2, [r3, #4]
hLtdcHandler.Init.VSPolarity = LTDC_VSPOLARITY_AL;
800229a: 4b16 ldr r3, [pc, #88] ; (80022f4 <BSP_LCD_Init+0xcc>)
800229c: 2200 movs r2, #0
800229e: 609a str r2, [r3, #8]
hLtdcHandler.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80022a0: 4b14 ldr r3, [pc, #80] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022a2: 2200 movs r2, #0
80022a4: 60da str r2, [r3, #12]
hLtdcHandler.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80022a6: 4b13 ldr r3, [pc, #76] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022a8: 2200 movs r2, #0
80022aa: 611a str r2, [r3, #16]
hLtdcHandler.Instance = LTDC;
80022ac: 4b11 ldr r3, [pc, #68] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022ae: 4a12 ldr r2, [pc, #72] ; (80022f8 <BSP_LCD_Init+0xd0>)
80022b0: 601a str r2, [r3, #0]
if(HAL_LTDC_GetState(&hLtdcHandler) == HAL_LTDC_STATE_RESET)
80022b2: 4810 ldr r0, [pc, #64] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022b4: f004 fd82 bl 8006dbc <HAL_LTDC_GetState>
80022b8: 4603 mov r3, r0
80022ba: 2b00 cmp r3, #0
80022bc: d103 bne.n 80022c6 <BSP_LCD_Init+0x9e>
{
/* Initialize the LCD Msp: this __weak function can be rewritten by the application */
BSP_LCD_MspInit(&hLtdcHandler, NULL);
80022be: 2100 movs r1, #0
80022c0: 480c ldr r0, [pc, #48] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022c2: f000 fcb7 bl 8002c34 <BSP_LCD_MspInit>
}
HAL_LTDC_Init(&hLtdcHandler);
80022c6: 480b ldr r0, [pc, #44] ; (80022f4 <BSP_LCD_Init+0xcc>)
80022c8: f004 fba8 bl 8006a1c <HAL_LTDC_Init>
/* Assert display enable LCD_DISP pin */
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
80022cc: 2201 movs r2, #1
80022ce: f44f 5180 mov.w r1, #4096 ; 0x1000
80022d2: 480a ldr r0, [pc, #40] ; (80022fc <BSP_LCD_Init+0xd4>)
80022d4: f003 fdd8 bl 8005e88 <HAL_GPIO_WritePin>
/* Assert backlight LCD_BL_CTRL pin */
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
80022d8: 2201 movs r2, #1
80022da: 2108 movs r1, #8
80022dc: 4808 ldr r0, [pc, #32] ; (8002300 <BSP_LCD_Init+0xd8>)
80022de: f003 fdd3 bl 8005e88 <HAL_GPIO_WritePin>
#if !defined(DATA_IN_ExtSDRAM)
/* Initialize the SDRAM */
BSP_SDRAM_Init();
80022e2: f000 fea1 bl 8003028 <BSP_SDRAM_Init>
#endif
/* Initialize the font */
BSP_LCD_SetFont(&LCD_DEFAULT_FONT);
80022e6: 4807 ldr r0, [pc, #28] ; (8002304 <BSP_LCD_Init+0xdc>)
80022e8: f000 f8d8 bl 800249c <BSP_LCD_SetFont>
return LCD_OK;
80022ec: 2300 movs r3, #0
}
80022ee: 4618 mov r0, r3
80022f0: bd80 pop {r7, pc}
80022f2: bf00 nop
80022f4: 200089d8 .word 0x200089d8
80022f8: 40016800 .word 0x40016800
80022fc: 40022000 .word 0x40022000
8002300: 40022800 .word 0x40022800
8002304: 20000028 .word 0x20000028
08002308 <BSP_LCD_GetXSize>:
/**
* @brief Gets the LCD X size.
* @retval Used LCD X size
*/
uint32_t BSP_LCD_GetXSize(void)
{
8002308: b480 push {r7}
800230a: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageWidth;
800230c: 4b06 ldr r3, [pc, #24] ; (8002328 <BSP_LCD_GetXSize+0x20>)
800230e: 681b ldr r3, [r3, #0]
8002310: 4a06 ldr r2, [pc, #24] ; (800232c <BSP_LCD_GetXSize+0x24>)
8002312: 2134 movs r1, #52 ; 0x34
8002314: fb01 f303 mul.w r3, r1, r3
8002318: 4413 add r3, r2
800231a: 3360 adds r3, #96 ; 0x60
800231c: 681b ldr r3, [r3, #0]
}
800231e: 4618 mov r0, r3
8002320: 46bd mov sp, r7
8002322: f85d 7b04 ldr.w r7, [sp], #4
8002326: 4770 bx lr
8002328: 2000018c .word 0x2000018c
800232c: 200089d8 .word 0x200089d8
08002330 <BSP_LCD_GetYSize>:
/**
* @brief Gets the LCD Y size.
* @retval Used LCD Y size
*/
uint32_t BSP_LCD_GetYSize(void)
{
8002330: b480 push {r7}
8002332: af00 add r7, sp, #0
return hLtdcHandler.LayerCfg[ActiveLayer].ImageHeight;
8002334: 4b06 ldr r3, [pc, #24] ; (8002350 <BSP_LCD_GetYSize+0x20>)
8002336: 681b ldr r3, [r3, #0]
8002338: 4a06 ldr r2, [pc, #24] ; (8002354 <BSP_LCD_GetYSize+0x24>)
800233a: 2134 movs r1, #52 ; 0x34
800233c: fb01 f303 mul.w r3, r1, r3
8002340: 4413 add r3, r2
8002342: 3364 adds r3, #100 ; 0x64
8002344: 681b ldr r3, [r3, #0]
}
8002346: 4618 mov r0, r3
8002348: 46bd mov sp, r7
800234a: f85d 7b04 ldr.w r7, [sp], #4
800234e: 4770 bx lr
8002350: 2000018c .word 0x2000018c
8002354: 200089d8 .word 0x200089d8
08002358 <BSP_LCD_LayerDefaultInit>:
* @param LayerIndex: Layer foreground or background
* @param FB_Address: Layer frame buffer
* @retval None
*/
void BSP_LCD_LayerDefaultInit(uint16_t LayerIndex, uint32_t FB_Address)
{
8002358: b580 push {r7, lr}
800235a: b090 sub sp, #64 ; 0x40
800235c: af00 add r7, sp, #0
800235e: 4603 mov r3, r0
8002360: 6039 str r1, [r7, #0]
8002362: 80fb strh r3, [r7, #6]
LCD_LayerCfgTypeDef layer_cfg;
/* Layer Init */
layer_cfg.WindowX0 = 0;
8002364: 2300 movs r3, #0
8002366: 60fb str r3, [r7, #12]
layer_cfg.WindowX1 = BSP_LCD_GetXSize();
8002368: f7ff ffce bl 8002308 <BSP_LCD_GetXSize>
800236c: 4603 mov r3, r0
800236e: 613b str r3, [r7, #16]
layer_cfg.WindowY0 = 0;
8002370: 2300 movs r3, #0
8002372: 617b str r3, [r7, #20]
layer_cfg.WindowY1 = BSP_LCD_GetYSize();
8002374: f7ff ffdc bl 8002330 <BSP_LCD_GetYSize>
8002378: 4603 mov r3, r0
800237a: 61bb str r3, [r7, #24]
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
800237c: 2300 movs r3, #0
800237e: 61fb str r3, [r7, #28]
layer_cfg.FBStartAdress = FB_Address;
8002380: 683b ldr r3, [r7, #0]
8002382: 633b str r3, [r7, #48] ; 0x30
layer_cfg.Alpha = 255;
8002384: 23ff movs r3, #255 ; 0xff
8002386: 623b str r3, [r7, #32]
layer_cfg.Alpha0 = 0;
8002388: 2300 movs r3, #0
800238a: 627b str r3, [r7, #36] ; 0x24
layer_cfg.Backcolor.Blue = 0;
800238c: 2300 movs r3, #0
800238e: f887 303c strb.w r3, [r7, #60] ; 0x3c
layer_cfg.Backcolor.Green = 0;
8002392: 2300 movs r3, #0
8002394: f887 303d strb.w r3, [r7, #61] ; 0x3d
layer_cfg.Backcolor.Red = 0;
8002398: 2300 movs r3, #0
800239a: f887 303e strb.w r3, [r7, #62] ; 0x3e
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
800239e: f44f 63c0 mov.w r3, #1536 ; 0x600
80023a2: 62bb str r3, [r7, #40] ; 0x28
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
80023a4: 2307 movs r3, #7
80023a6: 62fb str r3, [r7, #44] ; 0x2c
layer_cfg.ImageWidth = BSP_LCD_GetXSize();
80023a8: f7ff ffae bl 8002308 <BSP_LCD_GetXSize>
80023ac: 4603 mov r3, r0
80023ae: 637b str r3, [r7, #52] ; 0x34
layer_cfg.ImageHeight = BSP_LCD_GetYSize();
80023b0: f7ff ffbe bl 8002330 <BSP_LCD_GetYSize>
80023b4: 4603 mov r3, r0
80023b6: 63bb str r3, [r7, #56] ; 0x38
HAL_LTDC_ConfigLayer(&hLtdcHandler, &layer_cfg, LayerIndex);
80023b8: 88fa ldrh r2, [r7, #6]
80023ba: f107 030c add.w r3, r7, #12
80023be: 4619 mov r1, r3
80023c0: 4812 ldr r0, [pc, #72] ; (800240c <BSP_LCD_LayerDefaultInit+0xb4>)
80023c2: f004 fcbd bl 8006d40 <HAL_LTDC_ConfigLayer>
DrawProp[LayerIndex].BackColor = LCD_COLOR_WHITE;
80023c6: 88fa ldrh r2, [r7, #6]
80023c8: 4911 ldr r1, [pc, #68] ; (8002410 <BSP_LCD_LayerDefaultInit+0xb8>)
80023ca: 4613 mov r3, r2
80023cc: 005b lsls r3, r3, #1
80023ce: 4413 add r3, r2
80023d0: 009b lsls r3, r3, #2
80023d2: 440b add r3, r1
80023d4: 3304 adds r3, #4
80023d6: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
80023da: 601a str r2, [r3, #0]
DrawProp[LayerIndex].pFont = &Font24;
80023dc: 88fa ldrh r2, [r7, #6]
80023de: 490c ldr r1, [pc, #48] ; (8002410 <BSP_LCD_LayerDefaultInit+0xb8>)
80023e0: 4613 mov r3, r2
80023e2: 005b lsls r3, r3, #1
80023e4: 4413 add r3, r2
80023e6: 009b lsls r3, r3, #2
80023e8: 440b add r3, r1
80023ea: 3308 adds r3, #8
80023ec: 4a09 ldr r2, [pc, #36] ; (8002414 <BSP_LCD_LayerDefaultInit+0xbc>)
80023ee: 601a str r2, [r3, #0]
DrawProp[LayerIndex].TextColor = LCD_COLOR_BLACK;
80023f0: 88fa ldrh r2, [r7, #6]
80023f2: 4907 ldr r1, [pc, #28] ; (8002410 <BSP_LCD_LayerDefaultInit+0xb8>)
80023f4: 4613 mov r3, r2
80023f6: 005b lsls r3, r3, #1
80023f8: 4413 add r3, r2
80023fa: 009b lsls r3, r3, #2
80023fc: 440b add r3, r1
80023fe: f04f 427f mov.w r2, #4278190080 ; 0xff000000
8002402: 601a str r2, [r3, #0]
}
8002404: bf00 nop
8002406: 3740 adds r7, #64 ; 0x40
8002408: 46bd mov sp, r7
800240a: bd80 pop {r7, pc}
800240c: 200089d8 .word 0x200089d8
8002410: 20000190 .word 0x20000190
8002414: 20000028 .word 0x20000028
08002418 <BSP_LCD_SelectLayer>:
* @brief Selects the LCD Layer.
* @param LayerIndex: Layer foreground or background
* @retval None
*/
void BSP_LCD_SelectLayer(uint32_t LayerIndex)
{
8002418: b480 push {r7}
800241a: b083 sub sp, #12
800241c: af00 add r7, sp, #0
800241e: 6078 str r0, [r7, #4]
ActiveLayer = LayerIndex;
8002420: 4a04 ldr r2, [pc, #16] ; (8002434 <BSP_LCD_SelectLayer+0x1c>)
8002422: 687b ldr r3, [r7, #4]
8002424: 6013 str r3, [r2, #0]
}
8002426: bf00 nop
8002428: 370c adds r7, #12
800242a: 46bd mov sp, r7
800242c: f85d 7b04 ldr.w r7, [sp], #4
8002430: 4770 bx lr
8002432: bf00 nop
8002434: 2000018c .word 0x2000018c
08002438 <BSP_LCD_SetTextColor>:
* @brief Sets the LCD text color.
* @param Color: Text color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetTextColor(uint32_t Color)
{
8002438: b480 push {r7}
800243a: b083 sub sp, #12
800243c: af00 add r7, sp, #0
800243e: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].TextColor = Color;
8002440: 4b07 ldr r3, [pc, #28] ; (8002460 <BSP_LCD_SetTextColor+0x28>)
8002442: 681a ldr r2, [r3, #0]
8002444: 4907 ldr r1, [pc, #28] ; (8002464 <BSP_LCD_SetTextColor+0x2c>)
8002446: 4613 mov r3, r2
8002448: 005b lsls r3, r3, #1
800244a: 4413 add r3, r2
800244c: 009b lsls r3, r3, #2
800244e: 440b add r3, r1
8002450: 687a ldr r2, [r7, #4]
8002452: 601a str r2, [r3, #0]
}
8002454: bf00 nop
8002456: 370c adds r7, #12
8002458: 46bd mov sp, r7
800245a: f85d 7b04 ldr.w r7, [sp], #4
800245e: 4770 bx lr
8002460: 2000018c .word 0x2000018c
8002464: 20000190 .word 0x20000190
08002468 <BSP_LCD_SetBackColor>:
* @brief Sets the LCD background color.
* @param Color: Layer background color code ARGB(8-8-8-8)
* @retval None
*/
void BSP_LCD_SetBackColor(uint32_t Color)
{
8002468: b480 push {r7}
800246a: b083 sub sp, #12
800246c: af00 add r7, sp, #0
800246e: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].BackColor = Color;
8002470: 4b08 ldr r3, [pc, #32] ; (8002494 <BSP_LCD_SetBackColor+0x2c>)
8002472: 681a ldr r2, [r3, #0]
8002474: 4908 ldr r1, [pc, #32] ; (8002498 <BSP_LCD_SetBackColor+0x30>)
8002476: 4613 mov r3, r2
8002478: 005b lsls r3, r3, #1
800247a: 4413 add r3, r2
800247c: 009b lsls r3, r3, #2
800247e: 440b add r3, r1
8002480: 3304 adds r3, #4
8002482: 687a ldr r2, [r7, #4]
8002484: 601a str r2, [r3, #0]
}
8002486: bf00 nop
8002488: 370c adds r7, #12
800248a: 46bd mov sp, r7
800248c: f85d 7b04 ldr.w r7, [sp], #4
8002490: 4770 bx lr
8002492: bf00 nop
8002494: 2000018c .word 0x2000018c
8002498: 20000190 .word 0x20000190
0800249c <BSP_LCD_SetFont>:
* @brief Sets the LCD text font.
* @param fonts: Layer font to be used
* @retval None
*/
void BSP_LCD_SetFont(sFONT *fonts)
{
800249c: b480 push {r7}
800249e: b083 sub sp, #12
80024a0: af00 add r7, sp, #0
80024a2: 6078 str r0, [r7, #4]
DrawProp[ActiveLayer].pFont = fonts;
80024a4: 4b08 ldr r3, [pc, #32] ; (80024c8 <BSP_LCD_SetFont+0x2c>)
80024a6: 681a ldr r2, [r3, #0]
80024a8: 4908 ldr r1, [pc, #32] ; (80024cc <BSP_LCD_SetFont+0x30>)
80024aa: 4613 mov r3, r2
80024ac: 005b lsls r3, r3, #1
80024ae: 4413 add r3, r2
80024b0: 009b lsls r3, r3, #2
80024b2: 440b add r3, r1
80024b4: 3308 adds r3, #8
80024b6: 687a ldr r2, [r7, #4]
80024b8: 601a str r2, [r3, #0]
}
80024ba: bf00 nop
80024bc: 370c adds r7, #12
80024be: 46bd mov sp, r7
80024c0: f85d 7b04 ldr.w r7, [sp], #4
80024c4: 4770 bx lr
80024c6: bf00 nop
80024c8: 2000018c .word 0x2000018c
80024cc: 20000190 .word 0x20000190
080024d0 <BSP_LCD_GetFont>:
/**
* @brief Gets the LCD text font.
* @retval Used layer font
*/
sFONT *BSP_LCD_GetFont(void)
{
80024d0: b480 push {r7}
80024d2: af00 add r7, sp, #0
return DrawProp[ActiveLayer].pFont;
80024d4: 4b07 ldr r3, [pc, #28] ; (80024f4 <BSP_LCD_GetFont+0x24>)
80024d6: 681a ldr r2, [r3, #0]
80024d8: 4907 ldr r1, [pc, #28] ; (80024f8 <BSP_LCD_GetFont+0x28>)
80024da: 4613 mov r3, r2
80024dc: 005b lsls r3, r3, #1
80024de: 4413 add r3, r2
80024e0: 009b lsls r3, r3, #2
80024e2: 440b add r3, r1
80024e4: 3308 adds r3, #8
80024e6: 681b ldr r3, [r3, #0]
}
80024e8: 4618 mov r0, r3
80024ea: 46bd mov sp, r7
80024ec: f85d 7b04 ldr.w r7, [sp], #4
80024f0: 4770 bx lr
80024f2: bf00 nop
80024f4: 2000018c .word 0x2000018c
80024f8: 20000190 .word 0x20000190
080024fc <BSP_LCD_Clear>:
* @brief Clears the hole LCD.
* @param Color: Color of the background
* @retval None
*/
void BSP_LCD_Clear(uint32_t Color)
{
80024fc: b5f0 push {r4, r5, r6, r7, lr}
80024fe: b085 sub sp, #20
8002500: af02 add r7, sp, #8
8002502: 6078 str r0, [r7, #4]
/* Clear the LCD */
LL_FillBuffer(ActiveLayer, (uint32_t *)(hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress), BSP_LCD_GetXSize(), BSP_LCD_GetYSize(), 0, Color);
8002504: 4b0f ldr r3, [pc, #60] ; (8002544 <BSP_LCD_Clear+0x48>)
8002506: 681c ldr r4, [r3, #0]
8002508: 4b0e ldr r3, [pc, #56] ; (8002544 <BSP_LCD_Clear+0x48>)
800250a: 681b ldr r3, [r3, #0]
800250c: 4a0e ldr r2, [pc, #56] ; (8002548 <BSP_LCD_Clear+0x4c>)
800250e: 2134 movs r1, #52 ; 0x34
8002510: fb01 f303 mul.w r3, r1, r3
8002514: 4413 add r3, r2
8002516: 335c adds r3, #92 ; 0x5c
8002518: 681b ldr r3, [r3, #0]
800251a: 461d mov r5, r3
800251c: f7ff fef4 bl 8002308 <BSP_LCD_GetXSize>
8002520: 4606 mov r6, r0
8002522: f7ff ff05 bl 8002330 <BSP_LCD_GetYSize>
8002526: 4602 mov r2, r0
8002528: 687b ldr r3, [r7, #4]
800252a: 9301 str r3, [sp, #4]
800252c: 2300 movs r3, #0
800252e: 9300 str r3, [sp, #0]
8002530: 4613 mov r3, r2
8002532: 4632 mov r2, r6
8002534: 4629 mov r1, r5
8002536: 4620 mov r0, r4
8002538: f000 fd2a bl 8002f90 <LL_FillBuffer>
}
800253c: bf00 nop
800253e: 370c adds r7, #12
8002540: 46bd mov sp, r7
8002542: bdf0 pop {r4, r5, r6, r7, pc}
8002544: 2000018c .word 0x2000018c
8002548: 200089d8 .word 0x200089d8
0800254c <BSP_LCD_DisplayChar>:
* @param Ascii: Character ascii code
* This parameter must be a number between Min_Data = 0x20 and Max_Data = 0x7E
* @retval None
*/
void BSP_LCD_DisplayChar(uint16_t Xpos, uint16_t Ypos, uint8_t Ascii)
{
800254c: b590 push {r4, r7, lr}
800254e: b083 sub sp, #12
8002550: af00 add r7, sp, #0
8002552: 4603 mov r3, r0
8002554: 80fb strh r3, [r7, #6]
8002556: 460b mov r3, r1
8002558: 80bb strh r3, [r7, #4]
800255a: 4613 mov r3, r2
800255c: 70fb strb r3, [r7, #3]
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
800255e: 4b1b ldr r3, [pc, #108] ; (80025cc <BSP_LCD_DisplayChar+0x80>)
8002560: 681a ldr r2, [r3, #0]
8002562: 491b ldr r1, [pc, #108] ; (80025d0 <BSP_LCD_DisplayChar+0x84>)
8002564: 4613 mov r3, r2
8002566: 005b lsls r3, r3, #1
8002568: 4413 add r3, r2
800256a: 009b lsls r3, r3, #2
800256c: 440b add r3, r1
800256e: 3308 adds r3, #8
8002570: 681b ldr r3, [r3, #0]
8002572: 6819 ldr r1, [r3, #0]
8002574: 78fb ldrb r3, [r7, #3]
8002576: f1a3 0020 sub.w r0, r3, #32
DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);
800257a: 4b14 ldr r3, [pc, #80] ; (80025cc <BSP_LCD_DisplayChar+0x80>)
800257c: 681a ldr r2, [r3, #0]
800257e: 4c14 ldr r4, [pc, #80] ; (80025d0 <BSP_LCD_DisplayChar+0x84>)
8002580: 4613 mov r3, r2
8002582: 005b lsls r3, r3, #1
8002584: 4413 add r3, r2
8002586: 009b lsls r3, r3, #2
8002588: 4423 add r3, r4
800258a: 3308 adds r3, #8
800258c: 681b ldr r3, [r3, #0]
800258e: 88db ldrh r3, [r3, #6]
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
8002590: fb03 f000 mul.w r0, r3, r0
DrawProp[ActiveLayer].pFont->Height * ((DrawProp[ActiveLayer].pFont->Width + 7) / 8)]);
8002594: 4b0d ldr r3, [pc, #52] ; (80025cc <BSP_LCD_DisplayChar+0x80>)
8002596: 681a ldr r2, [r3, #0]
8002598: 4c0d ldr r4, [pc, #52] ; (80025d0 <BSP_LCD_DisplayChar+0x84>)
800259a: 4613 mov r3, r2
800259c: 005b lsls r3, r3, #1
800259e: 4413 add r3, r2
80025a0: 009b lsls r3, r3, #2
80025a2: 4423 add r3, r4
80025a4: 3308 adds r3, #8
80025a6: 681b ldr r3, [r3, #0]
80025a8: 889b ldrh r3, [r3, #4]
80025aa: 3307 adds r3, #7
80025ac: 2b00 cmp r3, #0
80025ae: da00 bge.n 80025b2 <BSP_LCD_DisplayChar+0x66>
80025b0: 3307 adds r3, #7
80025b2: 10db asrs r3, r3, #3
80025b4: fb03 f300 mul.w r3, r3, r0
DrawChar(Xpos, Ypos, &DrawProp[ActiveLayer].pFont->table[(Ascii-' ') *\
80025b8: 18ca adds r2, r1, r3
80025ba: 88b9 ldrh r1, [r7, #4]
80025bc: 88fb ldrh r3, [r7, #6]
80025be: 4618 mov r0, r3
80025c0: f000 fc2e bl 8002e20 <DrawChar>
}
80025c4: bf00 nop
80025c6: 370c adds r7, #12
80025c8: 46bd mov sp, r7
80025ca: bd90 pop {r4, r7, pc}
80025cc: 2000018c .word 0x2000018c
80025d0: 20000190 .word 0x20000190
080025d4 <BSP_LCD_DisplayStringAt>:
* @arg RIGHT_MODE
* @arg LEFT_MODE
* @retval None
*/
void BSP_LCD_DisplayStringAt(uint16_t Xpos, uint16_t Ypos, uint8_t *Text, Text_AlignModeTypdef Mode)
{
80025d4: b5b0 push {r4, r5, r7, lr}
80025d6: b088 sub sp, #32
80025d8: af00 add r7, sp, #0
80025da: 60ba str r2, [r7, #8]
80025dc: 461a mov r2, r3
80025de: 4603 mov r3, r0
80025e0: 81fb strh r3, [r7, #14]
80025e2: 460b mov r3, r1
80025e4: 81bb strh r3, [r7, #12]
80025e6: 4613 mov r3, r2
80025e8: 71fb strb r3, [r7, #7]
uint16_t ref_column = 1, i = 0;
80025ea: 2301 movs r3, #1
80025ec: 83fb strh r3, [r7, #30]
80025ee: 2300 movs r3, #0
80025f0: 83bb strh r3, [r7, #28]
uint32_t size = 0, xsize = 0;
80025f2: 2300 movs r3, #0
80025f4: 61bb str r3, [r7, #24]
80025f6: 2300 movs r3, #0
80025f8: 613b str r3, [r7, #16]
uint8_t *ptr = Text;
80025fa: 68bb ldr r3, [r7, #8]
80025fc: 617b str r3, [r7, #20]
/* Get the text size */
while (*ptr++) size ++ ;
80025fe: e002 b.n 8002606 <BSP_LCD_DisplayStringAt+0x32>
8002600: 69bb ldr r3, [r7, #24]
8002602: 3301 adds r3, #1
8002604: 61bb str r3, [r7, #24]
8002606: 697b ldr r3, [r7, #20]
8002608: 1c5a adds r2, r3, #1
800260a: 617a str r2, [r7, #20]
800260c: 781b ldrb r3, [r3, #0]
800260e: 2b00 cmp r3, #0
8002610: d1f6 bne.n 8002600 <BSP_LCD_DisplayStringAt+0x2c>
/* Characters number per line */
xsize = (BSP_LCD_GetXSize()/DrawProp[ActiveLayer].pFont->Width);
8002612: f7ff fe79 bl 8002308 <BSP_LCD_GetXSize>
8002616: 4b4f ldr r3, [pc, #316] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
8002618: 681a ldr r2, [r3, #0]
800261a: 494f ldr r1, [pc, #316] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
800261c: 4613 mov r3, r2
800261e: 005b lsls r3, r3, #1
8002620: 4413 add r3, r2
8002622: 009b lsls r3, r3, #2
8002624: 440b add r3, r1
8002626: 3308 adds r3, #8
8002628: 681b ldr r3, [r3, #0]
800262a: 889b ldrh r3, [r3, #4]
800262c: fbb0 f3f3 udiv r3, r0, r3
8002630: 613b str r3, [r7, #16]
switch (Mode)
8002632: 79fb ldrb r3, [r7, #7]
8002634: 2b02 cmp r3, #2
8002636: d01c beq.n 8002672 <BSP_LCD_DisplayStringAt+0x9e>
8002638: 2b03 cmp r3, #3
800263a: d017 beq.n 800266c <BSP_LCD_DisplayStringAt+0x98>
800263c: 2b01 cmp r3, #1
800263e: d12e bne.n 800269e <BSP_LCD_DisplayStringAt+0xca>
{
case CENTER_MODE:
{
ref_column = Xpos + ((xsize - size)* DrawProp[ActiveLayer].pFont->Width) / 2;
8002640: 693a ldr r2, [r7, #16]
8002642: 69bb ldr r3, [r7, #24]
8002644: 1ad1 subs r1, r2, r3
8002646: 4b43 ldr r3, [pc, #268] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
8002648: 681a ldr r2, [r3, #0]
800264a: 4843 ldr r0, [pc, #268] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
800264c: 4613 mov r3, r2
800264e: 005b lsls r3, r3, #1
8002650: 4413 add r3, r2
8002652: 009b lsls r3, r3, #2
8002654: 4403 add r3, r0
8002656: 3308 adds r3, #8
8002658: 681b ldr r3, [r3, #0]
800265a: 889b ldrh r3, [r3, #4]
800265c: fb03 f301 mul.w r3, r3, r1
8002660: 085b lsrs r3, r3, #1
8002662: b29a uxth r2, r3
8002664: 89fb ldrh r3, [r7, #14]
8002666: 4413 add r3, r2
8002668: 83fb strh r3, [r7, #30]
break;
800266a: e01b b.n 80026a4 <BSP_LCD_DisplayStringAt+0xd0>
}
case LEFT_MODE:
{
ref_column = Xpos;
800266c: 89fb ldrh r3, [r7, #14]
800266e: 83fb strh r3, [r7, #30]
break;
8002670: e018 b.n 80026a4 <BSP_LCD_DisplayStringAt+0xd0>
}
case RIGHT_MODE:
{
ref_column = - Xpos + ((xsize - size)*DrawProp[ActiveLayer].pFont->Width);
8002672: 693a ldr r2, [r7, #16]
8002674: 69bb ldr r3, [r7, #24]
8002676: 1ad3 subs r3, r2, r3
8002678: b299 uxth r1, r3
800267a: 4b36 ldr r3, [pc, #216] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
800267c: 681a ldr r2, [r3, #0]
800267e: 4836 ldr r0, [pc, #216] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
8002680: 4613 mov r3, r2
8002682: 005b lsls r3, r3, #1
8002684: 4413 add r3, r2
8002686: 009b lsls r3, r3, #2
8002688: 4403 add r3, r0
800268a: 3308 adds r3, #8
800268c: 681b ldr r3, [r3, #0]
800268e: 889b ldrh r3, [r3, #4]
8002690: fb11 f303 smulbb r3, r1, r3
8002694: b29a uxth r2, r3
8002696: 89fb ldrh r3, [r7, #14]
8002698: 1ad3 subs r3, r2, r3
800269a: 83fb strh r3, [r7, #30]
break;
800269c: e002 b.n 80026a4 <BSP_LCD_DisplayStringAt+0xd0>
}
default:
{
ref_column = Xpos;
800269e: 89fb ldrh r3, [r7, #14]
80026a0: 83fb strh r3, [r7, #30]
break;
80026a2: bf00 nop
}
}
/* Check that the Start column is located in the screen */
if ((ref_column < 1) || (ref_column >= 0x8000))
80026a4: 8bfb ldrh r3, [r7, #30]
80026a6: 2b00 cmp r3, #0
80026a8: d003 beq.n 80026b2 <BSP_LCD_DisplayStringAt+0xde>
80026aa: f9b7 301e ldrsh.w r3, [r7, #30]
80026ae: 2b00 cmp r3, #0
80026b0: da1d bge.n 80026ee <BSP_LCD_DisplayStringAt+0x11a>
{
ref_column = 1;
80026b2: 2301 movs r3, #1
80026b4: 83fb strh r3, [r7, #30]
}
/* Send the string character by character on LCD */
while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))
80026b6: e01a b.n 80026ee <BSP_LCD_DisplayStringAt+0x11a>
{
/* Display one character on LCD */
BSP_LCD_DisplayChar(ref_column, Ypos, *Text);
80026b8: 68bb ldr r3, [r7, #8]
80026ba: 781a ldrb r2, [r3, #0]
80026bc: 89b9 ldrh r1, [r7, #12]
80026be: 8bfb ldrh r3, [r7, #30]
80026c0: 4618 mov r0, r3
80026c2: f7ff ff43 bl 800254c <BSP_LCD_DisplayChar>
/* Decrement the column position by 16 */
ref_column += DrawProp[ActiveLayer].pFont->Width;
80026c6: 4b23 ldr r3, [pc, #140] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
80026c8: 681a ldr r2, [r3, #0]
80026ca: 4923 ldr r1, [pc, #140] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
80026cc: 4613 mov r3, r2
80026ce: 005b lsls r3, r3, #1
80026d0: 4413 add r3, r2
80026d2: 009b lsls r3, r3, #2
80026d4: 440b add r3, r1
80026d6: 3308 adds r3, #8
80026d8: 681b ldr r3, [r3, #0]
80026da: 889a ldrh r2, [r3, #4]
80026dc: 8bfb ldrh r3, [r7, #30]
80026de: 4413 add r3, r2
80026e0: 83fb strh r3, [r7, #30]
/* Point on the next character */
Text++;
80026e2: 68bb ldr r3, [r7, #8]
80026e4: 3301 adds r3, #1
80026e6: 60bb str r3, [r7, #8]
i++;
80026e8: 8bbb ldrh r3, [r7, #28]
80026ea: 3301 adds r3, #1
80026ec: 83bb strh r3, [r7, #28]
while ((*Text != 0) & (((BSP_LCD_GetXSize() - (i*DrawProp[ActiveLayer].pFont->Width)) & 0xFFFF) >= DrawProp[ActiveLayer].pFont->Width))
80026ee: 68bb ldr r3, [r7, #8]
80026f0: 781b ldrb r3, [r3, #0]
80026f2: 2b00 cmp r3, #0
80026f4: bf14 ite ne
80026f6: 2301 movne r3, #1
80026f8: 2300 moveq r3, #0
80026fa: b2dc uxtb r4, r3
80026fc: f7ff fe04 bl 8002308 <BSP_LCD_GetXSize>
8002700: 4605 mov r5, r0
8002702: 8bb9 ldrh r1, [r7, #28]
8002704: 4b13 ldr r3, [pc, #76] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
8002706: 681a ldr r2, [r3, #0]
8002708: 4813 ldr r0, [pc, #76] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
800270a: 4613 mov r3, r2
800270c: 005b lsls r3, r3, #1
800270e: 4413 add r3, r2
8002710: 009b lsls r3, r3, #2
8002712: 4403 add r3, r0
8002714: 3308 adds r3, #8
8002716: 681b ldr r3, [r3, #0]
8002718: 889b ldrh r3, [r3, #4]
800271a: fb03 f301 mul.w r3, r3, r1
800271e: 1aeb subs r3, r5, r3
8002720: b299 uxth r1, r3
8002722: 4b0c ldr r3, [pc, #48] ; (8002754 <BSP_LCD_DisplayStringAt+0x180>)
8002724: 681a ldr r2, [r3, #0]
8002726: 480c ldr r0, [pc, #48] ; (8002758 <BSP_LCD_DisplayStringAt+0x184>)
8002728: 4613 mov r3, r2
800272a: 005b lsls r3, r3, #1
800272c: 4413 add r3, r2
800272e: 009b lsls r3, r3, #2
8002730: 4403 add r3, r0
8002732: 3308 adds r3, #8
8002734: 681b ldr r3, [r3, #0]
8002736: 889b ldrh r3, [r3, #4]
8002738: 4299 cmp r1, r3
800273a: bf2c ite cs
800273c: 2301 movcs r3, #1
800273e: 2300 movcc r3, #0
8002740: b2db uxtb r3, r3
8002742: 4023 ands r3, r4
8002744: b2db uxtb r3, r3
8002746: 2b00 cmp r3, #0
8002748: d1b6 bne.n 80026b8 <BSP_LCD_DisplayStringAt+0xe4>
}
}
800274a: bf00 nop
800274c: 3720 adds r7, #32
800274e: 46bd mov sp, r7
8002750: bdb0 pop {r4, r5, r7, pc}
8002752: bf00 nop
8002754: 2000018c .word 0x2000018c
8002758: 20000190 .word 0x20000190
0800275c <BSP_LCD_DisplayStringAtLine>:
* @param Line: Line where to display the character shape
* @param ptr: Pointer to string to display on LCD
* @retval None
*/
void BSP_LCD_DisplayStringAtLine(uint16_t Line, uint8_t *ptr)
{
800275c: b580 push {r7, lr}
800275e: b082 sub sp, #8
8002760: af00 add r7, sp, #0
8002762: 4603 mov r3, r0
8002764: 6039 str r1, [r7, #0]
8002766: 80fb strh r3, [r7, #6]
BSP_LCD_DisplayStringAt(0, LINE(Line), ptr, LEFT_MODE);
8002768: f7ff feb2 bl 80024d0 <BSP_LCD_GetFont>
800276c: 4603 mov r3, r0
800276e: 88db ldrh r3, [r3, #6]
8002770: 88fa ldrh r2, [r7, #6]
8002772: fb12 f303 smulbb r3, r2, r3
8002776: b299 uxth r1, r3
8002778: 2303 movs r3, #3
800277a: 683a ldr r2, [r7, #0]
800277c: 2000 movs r0, #0
800277e: f7ff ff29 bl 80025d4 <BSP_LCD_DisplayStringAt>
}
8002782: bf00 nop
8002784: 3708 adds r7, #8
8002786: 46bd mov sp, r7
8002788: bd80 pop {r7, pc}
...
0800278c <BSP_LCD_DrawHLine>:
* @param Ypos: Y position
* @param Length: Line length
* @retval None
*/
void BSP_LCD_DrawHLine(uint16_t Xpos, uint16_t Ypos, uint16_t Length)
{
800278c: b5b0 push {r4, r5, r7, lr}
800278e: b086 sub sp, #24
8002790: af02 add r7, sp, #8
8002792: 4603 mov r3, r0
8002794: 80fb strh r3, [r7, #6]
8002796: 460b mov r3, r1
8002798: 80bb strh r3, [r7, #4]
800279a: 4613 mov r3, r2
800279c: 807b strh r3, [r7, #2]
uint32_t Xaddress = 0;
800279e: 2300 movs r3, #0
80027a0: 60fb str r3, [r7, #12]
/* Get the line address */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
80027a2: 4b26 ldr r3, [pc, #152] ; (800283c <BSP_LCD_DrawHLine+0xb0>)
80027a4: 681b ldr r3, [r3, #0]
80027a6: 4a26 ldr r2, [pc, #152] ; (8002840 <BSP_LCD_DrawHLine+0xb4>)
80027a8: 2134 movs r1, #52 ; 0x34
80027aa: fb01 f303 mul.w r3, r1, r3
80027ae: 4413 add r3, r2
80027b0: 3348 adds r3, #72 ; 0x48
80027b2: 681b ldr r3, [r3, #0]
80027b4: 2b02 cmp r3, #2
80027b6: d114 bne.n 80027e2 <BSP_LCD_DrawHLine+0x56>
{ /* RGB565 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 2*(BSP_LCD_GetXSize()*Ypos + Xpos);
80027b8: 4b20 ldr r3, [pc, #128] ; (800283c <BSP_LCD_DrawHLine+0xb0>)
80027ba: 681b ldr r3, [r3, #0]
80027bc: 4a20 ldr r2, [pc, #128] ; (8002840 <BSP_LCD_DrawHLine+0xb4>)
80027be: 2134 movs r1, #52 ; 0x34
80027c0: fb01 f303 mul.w r3, r1, r3
80027c4: 4413 add r3, r2
80027c6: 335c adds r3, #92 ; 0x5c
80027c8: 681c ldr r4, [r3, #0]
80027ca: f7ff fd9d bl 8002308 <BSP_LCD_GetXSize>
80027ce: 4602 mov r2, r0
80027d0: 88bb ldrh r3, [r7, #4]
80027d2: fb03 f202 mul.w r2, r3, r2
80027d6: 88fb ldrh r3, [r7, #6]
80027d8: 4413 add r3, r2
80027da: 005b lsls r3, r3, #1
80027dc: 4423 add r3, r4
80027de: 60fb str r3, [r7, #12]
80027e0: e013 b.n 800280a <BSP_LCD_DrawHLine+0x7e>
}
else
{ /* ARGB8888 format */
Xaddress = (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress) + 4*(BSP_LCD_GetXSize()*Ypos + Xpos);
80027e2: 4b16 ldr r3, [pc, #88] ; (800283c <BSP_LCD_DrawHLine+0xb0>)
80027e4: 681b ldr r3, [r3, #0]
80027e6: 4a16 ldr r2, [pc, #88] ; (8002840 <BSP_LCD_DrawHLine+0xb4>)
80027e8: 2134 movs r1, #52 ; 0x34
80027ea: fb01 f303 mul.w r3, r1, r3
80027ee: 4413 add r3, r2
80027f0: 335c adds r3, #92 ; 0x5c
80027f2: 681c ldr r4, [r3, #0]
80027f4: f7ff fd88 bl 8002308 <BSP_LCD_GetXSize>
80027f8: 4602 mov r2, r0
80027fa: 88bb ldrh r3, [r7, #4]
80027fc: fb03 f202 mul.w r2, r3, r2
8002800: 88fb ldrh r3, [r7, #6]
8002802: 4413 add r3, r2
8002804: 009b lsls r3, r3, #2
8002806: 4423 add r3, r4
8002808: 60fb str r3, [r7, #12]
}
/* Write line */
LL_FillBuffer(ActiveLayer, (uint32_t *)Xaddress, Length, 1, 0, DrawProp[ActiveLayer].TextColor);
800280a: 4b0c ldr r3, [pc, #48] ; (800283c <BSP_LCD_DrawHLine+0xb0>)
800280c: 6818 ldr r0, [r3, #0]
800280e: 68fc ldr r4, [r7, #12]
8002810: 887d ldrh r5, [r7, #2]
8002812: 4b0a ldr r3, [pc, #40] ; (800283c <BSP_LCD_DrawHLine+0xb0>)
8002814: 681a ldr r2, [r3, #0]
8002816: 490b ldr r1, [pc, #44] ; (8002844 <BSP_LCD_DrawHLine+0xb8>)
8002818: 4613 mov r3, r2
800281a: 005b lsls r3, r3, #1
800281c: 4413 add r3, r2
800281e: 009b lsls r3, r3, #2
8002820: 440b add r3, r1
8002822: 681b ldr r3, [r3, #0]
8002824: 9301 str r3, [sp, #4]
8002826: 2300 movs r3, #0
8002828: 9300 str r3, [sp, #0]
800282a: 2301 movs r3, #1
800282c: 462a mov r2, r5
800282e: 4621 mov r1, r4
8002830: f000 fbae bl 8002f90 <LL_FillBuffer>
}
8002834: bf00 nop
8002836: 3710 adds r7, #16
8002838: 46bd mov sp, r7
800283a: bdb0 pop {r4, r5, r7, pc}
800283c: 2000018c .word 0x2000018c
8002840: 200089d8 .word 0x200089d8
8002844: 20000190 .word 0x20000190
08002848 <BSP_LCD_DrawCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_DrawCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
8002848: b590 push {r4, r7, lr}
800284a: b087 sub sp, #28
800284c: af00 add r7, sp, #0
800284e: 4603 mov r3, r0
8002850: 80fb strh r3, [r7, #6]
8002852: 460b mov r3, r1
8002854: 80bb strh r3, [r7, #4]
8002856: 4613 mov r3, r2
8002858: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
800285a: 887b ldrh r3, [r7, #2]
800285c: 005b lsls r3, r3, #1
800285e: f1c3 0303 rsb r3, r3, #3
8002862: 617b str r3, [r7, #20]
current_x = 0;
8002864: 2300 movs r3, #0
8002866: 613b str r3, [r7, #16]
current_y = Radius;
8002868: 887b ldrh r3, [r7, #2]
800286a: 60fb str r3, [r7, #12]
while (current_x <= current_y)
800286c: e0cf b.n 8002a0e <BSP_LCD_DrawCircle+0x1c6>
{
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
800286e: 693b ldr r3, [r7, #16]
8002870: b29a uxth r2, r3
8002872: 88fb ldrh r3, [r7, #6]
8002874: 4413 add r3, r2
8002876: b298 uxth r0, r3
8002878: 68fb ldr r3, [r7, #12]
800287a: b29b uxth r3, r3
800287c: 88ba ldrh r2, [r7, #4]
800287e: 1ad3 subs r3, r2, r3
8002880: b29c uxth r4, r3
8002882: 4b67 ldr r3, [pc, #412] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
8002884: 681a ldr r2, [r3, #0]
8002886: 4967 ldr r1, [pc, #412] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
8002888: 4613 mov r3, r2
800288a: 005b lsls r3, r3, #1
800288c: 4413 add r3, r2
800288e: 009b lsls r3, r3, #2
8002890: 440b add r3, r1
8002892: 681b ldr r3, [r3, #0]
8002894: 461a mov r2, r3
8002896: 4621 mov r1, r4
8002898: f000 f8c6 bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos - current_y), DrawProp[ActiveLayer].TextColor);
800289c: 693b ldr r3, [r7, #16]
800289e: b29b uxth r3, r3
80028a0: 88fa ldrh r2, [r7, #6]
80028a2: 1ad3 subs r3, r2, r3
80028a4: b298 uxth r0, r3
80028a6: 68fb ldr r3, [r7, #12]
80028a8: b29b uxth r3, r3
80028aa: 88ba ldrh r2, [r7, #4]
80028ac: 1ad3 subs r3, r2, r3
80028ae: b29c uxth r4, r3
80028b0: 4b5b ldr r3, [pc, #364] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
80028b2: 681a ldr r2, [r3, #0]
80028b4: 495b ldr r1, [pc, #364] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
80028b6: 4613 mov r3, r2
80028b8: 005b lsls r3, r3, #1
80028ba: 4413 add r3, r2
80028bc: 009b lsls r3, r3, #2
80028be: 440b add r3, r1
80028c0: 681b ldr r3, [r3, #0]
80028c2: 461a mov r2, r3
80028c4: 4621 mov r1, r4
80028c6: f000 f8af bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
80028ca: 68fb ldr r3, [r7, #12]
80028cc: b29a uxth r2, r3
80028ce: 88fb ldrh r3, [r7, #6]
80028d0: 4413 add r3, r2
80028d2: b298 uxth r0, r3
80028d4: 693b ldr r3, [r7, #16]
80028d6: b29b uxth r3, r3
80028d8: 88ba ldrh r2, [r7, #4]
80028da: 1ad3 subs r3, r2, r3
80028dc: b29c uxth r4, r3
80028de: 4b50 ldr r3, [pc, #320] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
80028e0: 681a ldr r2, [r3, #0]
80028e2: 4950 ldr r1, [pc, #320] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
80028e4: 4613 mov r3, r2
80028e6: 005b lsls r3, r3, #1
80028e8: 4413 add r3, r2
80028ea: 009b lsls r3, r3, #2
80028ec: 440b add r3, r1
80028ee: 681b ldr r3, [r3, #0]
80028f0: 461a mov r2, r3
80028f2: 4621 mov r1, r4
80028f4: f000 f898 bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos - current_x), DrawProp[ActiveLayer].TextColor);
80028f8: 68fb ldr r3, [r7, #12]
80028fa: b29b uxth r3, r3
80028fc: 88fa ldrh r2, [r7, #6]
80028fe: 1ad3 subs r3, r2, r3
8002900: b298 uxth r0, r3
8002902: 693b ldr r3, [r7, #16]
8002904: b29b uxth r3, r3
8002906: 88ba ldrh r2, [r7, #4]
8002908: 1ad3 subs r3, r2, r3
800290a: b29c uxth r4, r3
800290c: 4b44 ldr r3, [pc, #272] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
800290e: 681a ldr r2, [r3, #0]
8002910: 4944 ldr r1, [pc, #272] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
8002912: 4613 mov r3, r2
8002914: 005b lsls r3, r3, #1
8002916: 4413 add r3, r2
8002918: 009b lsls r3, r3, #2
800291a: 440b add r3, r1
800291c: 681b ldr r3, [r3, #0]
800291e: 461a mov r2, r3
8002920: 4621 mov r1, r4
8002922: f000 f881 bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002926: 693b ldr r3, [r7, #16]
8002928: b29a uxth r2, r3
800292a: 88fb ldrh r3, [r7, #6]
800292c: 4413 add r3, r2
800292e: b298 uxth r0, r3
8002930: 68fb ldr r3, [r7, #12]
8002932: b29a uxth r2, r3
8002934: 88bb ldrh r3, [r7, #4]
8002936: 4413 add r3, r2
8002938: b29c uxth r4, r3
800293a: 4b39 ldr r3, [pc, #228] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
800293c: 681a ldr r2, [r3, #0]
800293e: 4939 ldr r1, [pc, #228] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
8002940: 4613 mov r3, r2
8002942: 005b lsls r3, r3, #1
8002944: 4413 add r3, r2
8002946: 009b lsls r3, r3, #2
8002948: 440b add r3, r1
800294a: 681b ldr r3, [r3, #0]
800294c: 461a mov r2, r3
800294e: 4621 mov r1, r4
8002950: f000 f86a bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_x), (Ypos + current_y), DrawProp[ActiveLayer].TextColor);
8002954: 693b ldr r3, [r7, #16]
8002956: b29b uxth r3, r3
8002958: 88fa ldrh r2, [r7, #6]
800295a: 1ad3 subs r3, r2, r3
800295c: b298 uxth r0, r3
800295e: 68fb ldr r3, [r7, #12]
8002960: b29a uxth r2, r3
8002962: 88bb ldrh r3, [r7, #4]
8002964: 4413 add r3, r2
8002966: b29c uxth r4, r3
8002968: 4b2d ldr r3, [pc, #180] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
800296a: 681a ldr r2, [r3, #0]
800296c: 492d ldr r1, [pc, #180] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
800296e: 4613 mov r3, r2
8002970: 005b lsls r3, r3, #1
8002972: 4413 add r3, r2
8002974: 009b lsls r3, r3, #2
8002976: 440b add r3, r1
8002978: 681b ldr r3, [r3, #0]
800297a: 461a mov r2, r3
800297c: 4621 mov r1, r4
800297e: f000 f853 bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos + current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
8002982: 68fb ldr r3, [r7, #12]
8002984: b29a uxth r2, r3
8002986: 88fb ldrh r3, [r7, #6]
8002988: 4413 add r3, r2
800298a: b298 uxth r0, r3
800298c: 693b ldr r3, [r7, #16]
800298e: b29a uxth r2, r3
8002990: 88bb ldrh r3, [r7, #4]
8002992: 4413 add r3, r2
8002994: b29c uxth r4, r3
8002996: 4b22 ldr r3, [pc, #136] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
8002998: 681a ldr r2, [r3, #0]
800299a: 4922 ldr r1, [pc, #136] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
800299c: 4613 mov r3, r2
800299e: 005b lsls r3, r3, #1
80029a0: 4413 add r3, r2
80029a2: 009b lsls r3, r3, #2
80029a4: 440b add r3, r1
80029a6: 681b ldr r3, [r3, #0]
80029a8: 461a mov r2, r3
80029aa: 4621 mov r1, r4
80029ac: f000 f83c bl 8002a28 <BSP_LCD_DrawPixel>
BSP_LCD_DrawPixel((Xpos - current_y), (Ypos + current_x), DrawProp[ActiveLayer].TextColor);
80029b0: 68fb ldr r3, [r7, #12]
80029b2: b29b uxth r3, r3
80029b4: 88fa ldrh r2, [r7, #6]
80029b6: 1ad3 subs r3, r2, r3
80029b8: b298 uxth r0, r3
80029ba: 693b ldr r3, [r7, #16]
80029bc: b29a uxth r2, r3
80029be: 88bb ldrh r3, [r7, #4]
80029c0: 4413 add r3, r2
80029c2: b29c uxth r4, r3
80029c4: 4b16 ldr r3, [pc, #88] ; (8002a20 <BSP_LCD_DrawCircle+0x1d8>)
80029c6: 681a ldr r2, [r3, #0]
80029c8: 4916 ldr r1, [pc, #88] ; (8002a24 <BSP_LCD_DrawCircle+0x1dc>)
80029ca: 4613 mov r3, r2
80029cc: 005b lsls r3, r3, #1
80029ce: 4413 add r3, r2
80029d0: 009b lsls r3, r3, #2
80029d2: 440b add r3, r1
80029d4: 681b ldr r3, [r3, #0]
80029d6: 461a mov r2, r3
80029d8: 4621 mov r1, r4
80029da: f000 f825 bl 8002a28 <BSP_LCD_DrawPixel>
if (decision < 0)
80029de: 697b ldr r3, [r7, #20]
80029e0: 2b00 cmp r3, #0
80029e2: da06 bge.n 80029f2 <BSP_LCD_DrawCircle+0x1aa>
{
decision += (current_x << 2) + 6;
80029e4: 693b ldr r3, [r7, #16]
80029e6: 009a lsls r2, r3, #2
80029e8: 697b ldr r3, [r7, #20]
80029ea: 4413 add r3, r2
80029ec: 3306 adds r3, #6
80029ee: 617b str r3, [r7, #20]
80029f0: e00a b.n 8002a08 <BSP_LCD_DrawCircle+0x1c0>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
80029f2: 693a ldr r2, [r7, #16]
80029f4: 68fb ldr r3, [r7, #12]
80029f6: 1ad3 subs r3, r2, r3
80029f8: 009a lsls r2, r3, #2
80029fa: 697b ldr r3, [r7, #20]
80029fc: 4413 add r3, r2
80029fe: 330a adds r3, #10
8002a00: 617b str r3, [r7, #20]
current_y--;
8002a02: 68fb ldr r3, [r7, #12]
8002a04: 3b01 subs r3, #1
8002a06: 60fb str r3, [r7, #12]
}
current_x++;
8002a08: 693b ldr r3, [r7, #16]
8002a0a: 3301 adds r3, #1
8002a0c: 613b str r3, [r7, #16]
while (current_x <= current_y)
8002a0e: 693a ldr r2, [r7, #16]
8002a10: 68fb ldr r3, [r7, #12]
8002a12: 429a cmp r2, r3
8002a14: f67f af2b bls.w 800286e <BSP_LCD_DrawCircle+0x26>
}
}
8002a18: bf00 nop
8002a1a: 371c adds r7, #28
8002a1c: 46bd mov sp, r7
8002a1e: bd90 pop {r4, r7, pc}
8002a20: 2000018c .word 0x2000018c
8002a24: 20000190 .word 0x20000190
08002a28 <BSP_LCD_DrawPixel>:
* @param Ypos: Y position
* @param RGB_Code: Pixel color in ARGB mode (8-8-8-8)
* @retval None
*/
void BSP_LCD_DrawPixel(uint16_t Xpos, uint16_t Ypos, uint32_t RGB_Code)
{
8002a28: b5b0 push {r4, r5, r7, lr}
8002a2a: b082 sub sp, #8
8002a2c: af00 add r7, sp, #0
8002a2e: 4603 mov r3, r0
8002a30: 603a str r2, [r7, #0]
8002a32: 80fb strh r3, [r7, #6]
8002a34: 460b mov r3, r1
8002a36: 80bb strh r3, [r7, #4]
/* Write data value to all SDRAM memory */
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002a38: 4b1d ldr r3, [pc, #116] ; (8002ab0 <BSP_LCD_DrawPixel+0x88>)
8002a3a: 681b ldr r3, [r3, #0]
8002a3c: 4a1d ldr r2, [pc, #116] ; (8002ab4 <BSP_LCD_DrawPixel+0x8c>)
8002a3e: 2134 movs r1, #52 ; 0x34
8002a40: fb01 f303 mul.w r3, r1, r3
8002a44: 4413 add r3, r2
8002a46: 3348 adds r3, #72 ; 0x48
8002a48: 681b ldr r3, [r3, #0]
8002a4a: 2b02 cmp r3, #2
8002a4c: d116 bne.n 8002a7c <BSP_LCD_DrawPixel+0x54>
{ /* RGB565 format */
*(__IO uint16_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (2*(Ypos*BSP_LCD_GetXSize() + Xpos))) = (uint16_t)RGB_Code;
8002a4e: 4b18 ldr r3, [pc, #96] ; (8002ab0 <BSP_LCD_DrawPixel+0x88>)
8002a50: 681b ldr r3, [r3, #0]
8002a52: 4a18 ldr r2, [pc, #96] ; (8002ab4 <BSP_LCD_DrawPixel+0x8c>)
8002a54: 2134 movs r1, #52 ; 0x34
8002a56: fb01 f303 mul.w r3, r1, r3
8002a5a: 4413 add r3, r2
8002a5c: 335c adds r3, #92 ; 0x5c
8002a5e: 681c ldr r4, [r3, #0]
8002a60: 88bd ldrh r5, [r7, #4]
8002a62: f7ff fc51 bl 8002308 <BSP_LCD_GetXSize>
8002a66: 4603 mov r3, r0
8002a68: fb03 f205 mul.w r2, r3, r5
8002a6c: 88fb ldrh r3, [r7, #6]
8002a6e: 4413 add r3, r2
8002a70: 005b lsls r3, r3, #1
8002a72: 4423 add r3, r4
8002a74: 683a ldr r2, [r7, #0]
8002a76: b292 uxth r2, r2
8002a78: 801a strh r2, [r3, #0]
}
else
{ /* ARGB8888 format */
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
}
}
8002a7a: e015 b.n 8002aa8 <BSP_LCD_DrawPixel+0x80>
*(__IO uint32_t*) (hLtdcHandler.LayerCfg[ActiveLayer].FBStartAdress + (4*(Ypos*BSP_LCD_GetXSize() + Xpos))) = RGB_Code;
8002a7c: 4b0c ldr r3, [pc, #48] ; (8002ab0 <BSP_LCD_DrawPixel+0x88>)
8002a7e: 681b ldr r3, [r3, #0]
8002a80: 4a0c ldr r2, [pc, #48] ; (8002ab4 <BSP_LCD_DrawPixel+0x8c>)
8002a82: 2134 movs r1, #52 ; 0x34
8002a84: fb01 f303 mul.w r3, r1, r3
8002a88: 4413 add r3, r2
8002a8a: 335c adds r3, #92 ; 0x5c
8002a8c: 681c ldr r4, [r3, #0]
8002a8e: 88bd ldrh r5, [r7, #4]
8002a90: f7ff fc3a bl 8002308 <BSP_LCD_GetXSize>
8002a94: 4603 mov r3, r0
8002a96: fb03 f205 mul.w r2, r3, r5
8002a9a: 88fb ldrh r3, [r7, #6]
8002a9c: 4413 add r3, r2
8002a9e: 009b lsls r3, r3, #2
8002aa0: 4423 add r3, r4
8002aa2: 461a mov r2, r3
8002aa4: 683b ldr r3, [r7, #0]
8002aa6: 6013 str r3, [r2, #0]
}
8002aa8: bf00 nop
8002aaa: 3708 adds r7, #8
8002aac: 46bd mov sp, r7
8002aae: bdb0 pop {r4, r5, r7, pc}
8002ab0: 2000018c .word 0x2000018c
8002ab4: 200089d8 .word 0x200089d8
08002ab8 <BSP_LCD_FillCircle>:
* @param Ypos: Y position
* @param Radius: Circle radius
* @retval None
*/
void BSP_LCD_FillCircle(uint16_t Xpos, uint16_t Ypos, uint16_t Radius)
{
8002ab8: b580 push {r7, lr}
8002aba: b086 sub sp, #24
8002abc: af00 add r7, sp, #0
8002abe: 4603 mov r3, r0
8002ac0: 80fb strh r3, [r7, #6]
8002ac2: 460b mov r3, r1
8002ac4: 80bb strh r3, [r7, #4]
8002ac6: 4613 mov r3, r2
8002ac8: 807b strh r3, [r7, #2]
int32_t decision; /* Decision Variable */
uint32_t current_x; /* Current X Value */
uint32_t current_y; /* Current Y Value */
decision = 3 - (Radius << 1);
8002aca: 887b ldrh r3, [r7, #2]
8002acc: 005b lsls r3, r3, #1
8002ace: f1c3 0303 rsb r3, r3, #3
8002ad2: 617b str r3, [r7, #20]
current_x = 0;
8002ad4: 2300 movs r3, #0
8002ad6: 613b str r3, [r7, #16]
current_y = Radius;
8002ad8: 887b ldrh r3, [r7, #2]
8002ada: 60fb str r3, [r7, #12]
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8002adc: 4b44 ldr r3, [pc, #272] ; (8002bf0 <BSP_LCD_FillCircle+0x138>)
8002ade: 681a ldr r2, [r3, #0]
8002ae0: 4944 ldr r1, [pc, #272] ; (8002bf4 <BSP_LCD_FillCircle+0x13c>)
8002ae2: 4613 mov r3, r2
8002ae4: 005b lsls r3, r3, #1
8002ae6: 4413 add r3, r2
8002ae8: 009b lsls r3, r3, #2
8002aea: 440b add r3, r1
8002aec: 681b ldr r3, [r3, #0]
8002aee: 4618 mov r0, r3
8002af0: f7ff fca2 bl 8002438 <BSP_LCD_SetTextColor>
while (current_x <= current_y)
8002af4: e061 b.n 8002bba <BSP_LCD_FillCircle+0x102>
{
if(current_y > 0)
8002af6: 68fb ldr r3, [r7, #12]
8002af8: 2b00 cmp r3, #0
8002afa: d021 beq.n 8002b40 <BSP_LCD_FillCircle+0x88>
{
BSP_LCD_DrawHLine(Xpos - current_y, Ypos + current_x, 2*current_y);
8002afc: 68fb ldr r3, [r7, #12]
8002afe: b29b uxth r3, r3
8002b00: 88fa ldrh r2, [r7, #6]
8002b02: 1ad3 subs r3, r2, r3
8002b04: b298 uxth r0, r3
8002b06: 693b ldr r3, [r7, #16]
8002b08: b29a uxth r2, r3
8002b0a: 88bb ldrh r3, [r7, #4]
8002b0c: 4413 add r3, r2
8002b0e: b299 uxth r1, r3
8002b10: 68fb ldr r3, [r7, #12]
8002b12: b29b uxth r3, r3
8002b14: 005b lsls r3, r3, #1
8002b16: b29b uxth r3, r3
8002b18: 461a mov r2, r3
8002b1a: f7ff fe37 bl 800278c <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_y, Ypos - current_x, 2*current_y);
8002b1e: 68fb ldr r3, [r7, #12]
8002b20: b29b uxth r3, r3
8002b22: 88fa ldrh r2, [r7, #6]
8002b24: 1ad3 subs r3, r2, r3
8002b26: b298 uxth r0, r3
8002b28: 693b ldr r3, [r7, #16]
8002b2a: b29b uxth r3, r3
8002b2c: 88ba ldrh r2, [r7, #4]
8002b2e: 1ad3 subs r3, r2, r3
8002b30: b299 uxth r1, r3
8002b32: 68fb ldr r3, [r7, #12]
8002b34: b29b uxth r3, r3
8002b36: 005b lsls r3, r3, #1
8002b38: b29b uxth r3, r3
8002b3a: 461a mov r2, r3
8002b3c: f7ff fe26 bl 800278c <BSP_LCD_DrawHLine>
}
if(current_x > 0)
8002b40: 693b ldr r3, [r7, #16]
8002b42: 2b00 cmp r3, #0
8002b44: d021 beq.n 8002b8a <BSP_LCD_FillCircle+0xd2>
{
BSP_LCD_DrawHLine(Xpos - current_x, Ypos - current_y, 2*current_x);
8002b46: 693b ldr r3, [r7, #16]
8002b48: b29b uxth r3, r3
8002b4a: 88fa ldrh r2, [r7, #6]
8002b4c: 1ad3 subs r3, r2, r3
8002b4e: b298 uxth r0, r3
8002b50: 68fb ldr r3, [r7, #12]
8002b52: b29b uxth r3, r3
8002b54: 88ba ldrh r2, [r7, #4]
8002b56: 1ad3 subs r3, r2, r3
8002b58: b299 uxth r1, r3
8002b5a: 693b ldr r3, [r7, #16]
8002b5c: b29b uxth r3, r3
8002b5e: 005b lsls r3, r3, #1
8002b60: b29b uxth r3, r3
8002b62: 461a mov r2, r3
8002b64: f7ff fe12 bl 800278c <BSP_LCD_DrawHLine>
BSP_LCD_DrawHLine(Xpos - current_x, Ypos + current_y, 2*current_x);
8002b68: 693b ldr r3, [r7, #16]
8002b6a: b29b uxth r3, r3
8002b6c: 88fa ldrh r2, [r7, #6]
8002b6e: 1ad3 subs r3, r2, r3
8002b70: b298 uxth r0, r3
8002b72: 68fb ldr r3, [r7, #12]
8002b74: b29a uxth r2, r3
8002b76: 88bb ldrh r3, [r7, #4]
8002b78: 4413 add r3, r2
8002b7a: b299 uxth r1, r3
8002b7c: 693b ldr r3, [r7, #16]
8002b7e: b29b uxth r3, r3
8002b80: 005b lsls r3, r3, #1
8002b82: b29b uxth r3, r3
8002b84: 461a mov r2, r3
8002b86: f7ff fe01 bl 800278c <BSP_LCD_DrawHLine>
}
if (decision < 0)
8002b8a: 697b ldr r3, [r7, #20]
8002b8c: 2b00 cmp r3, #0
8002b8e: da06 bge.n 8002b9e <BSP_LCD_FillCircle+0xe6>
{
decision += (current_x << 2) + 6;
8002b90: 693b ldr r3, [r7, #16]
8002b92: 009a lsls r2, r3, #2
8002b94: 697b ldr r3, [r7, #20]
8002b96: 4413 add r3, r2
8002b98: 3306 adds r3, #6
8002b9a: 617b str r3, [r7, #20]
8002b9c: e00a b.n 8002bb4 <BSP_LCD_FillCircle+0xfc>
}
else
{
decision += ((current_x - current_y) << 2) + 10;
8002b9e: 693a ldr r2, [r7, #16]
8002ba0: 68fb ldr r3, [r7, #12]
8002ba2: 1ad3 subs r3, r2, r3
8002ba4: 009a lsls r2, r3, #2
8002ba6: 697b ldr r3, [r7, #20]
8002ba8: 4413 add r3, r2
8002baa: 330a adds r3, #10
8002bac: 617b str r3, [r7, #20]
current_y--;
8002bae: 68fb ldr r3, [r7, #12]
8002bb0: 3b01 subs r3, #1
8002bb2: 60fb str r3, [r7, #12]
}
current_x++;
8002bb4: 693b ldr r3, [r7, #16]
8002bb6: 3301 adds r3, #1
8002bb8: 613b str r3, [r7, #16]
while (current_x <= current_y)
8002bba: 693a ldr r2, [r7, #16]
8002bbc: 68fb ldr r3, [r7, #12]
8002bbe: 429a cmp r2, r3
8002bc0: d999 bls.n 8002af6 <BSP_LCD_FillCircle+0x3e>
}
BSP_LCD_SetTextColor(DrawProp[ActiveLayer].TextColor);
8002bc2: 4b0b ldr r3, [pc, #44] ; (8002bf0 <BSP_LCD_FillCircle+0x138>)
8002bc4: 681a ldr r2, [r3, #0]
8002bc6: 490b ldr r1, [pc, #44] ; (8002bf4 <BSP_LCD_FillCircle+0x13c>)
8002bc8: 4613 mov r3, r2
8002bca: 005b lsls r3, r3, #1
8002bcc: 4413 add r3, r2
8002bce: 009b lsls r3, r3, #2
8002bd0: 440b add r3, r1
8002bd2: 681b ldr r3, [r3, #0]
8002bd4: 4618 mov r0, r3
8002bd6: f7ff fc2f bl 8002438 <BSP_LCD_SetTextColor>
BSP_LCD_DrawCircle(Xpos, Ypos, Radius);
8002bda: 887a ldrh r2, [r7, #2]
8002bdc: 88b9 ldrh r1, [r7, #4]
8002bde: 88fb ldrh r3, [r7, #6]
8002be0: 4618 mov r0, r3
8002be2: f7ff fe31 bl 8002848 <BSP_LCD_DrawCircle>
}
8002be6: bf00 nop
8002be8: 3718 adds r7, #24
8002bea: 46bd mov sp, r7
8002bec: bd80 pop {r7, pc}
8002bee: bf00 nop
8002bf0: 2000018c .word 0x2000018c
8002bf4: 20000190 .word 0x20000190
08002bf8 <BSP_LCD_DisplayOn>:
/**
* @brief Enables the display.
* @retval None
*/
void BSP_LCD_DisplayOn(void)
{
8002bf8: b580 push {r7, lr}
8002bfa: af00 add r7, sp, #0
/* Display On */
__HAL_LTDC_ENABLE(&hLtdcHandler);
8002bfc: 4b0a ldr r3, [pc, #40] ; (8002c28 <BSP_LCD_DisplayOn+0x30>)
8002bfe: 681b ldr r3, [r3, #0]
8002c00: 699a ldr r2, [r3, #24]
8002c02: 4b09 ldr r3, [pc, #36] ; (8002c28 <BSP_LCD_DisplayOn+0x30>)
8002c04: 681b ldr r3, [r3, #0]
8002c06: f042 0201 orr.w r2, r2, #1
8002c0a: 619a str r2, [r3, #24]
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); /* Assert LCD_DISP pin */
8002c0c: 2201 movs r2, #1
8002c0e: f44f 5180 mov.w r1, #4096 ; 0x1000
8002c12: 4806 ldr r0, [pc, #24] ; (8002c2c <BSP_LCD_DisplayOn+0x34>)
8002c14: f003 f938 bl 8005e88 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); /* Assert LCD_BL_CTRL pin */
8002c18: 2201 movs r2, #1
8002c1a: 2108 movs r1, #8
8002c1c: 4804 ldr r0, [pc, #16] ; (8002c30 <BSP_LCD_DisplayOn+0x38>)
8002c1e: f003 f933 bl 8005e88 <HAL_GPIO_WritePin>
}
8002c22: bf00 nop
8002c24: bd80 pop {r7, pc}
8002c26: bf00 nop
8002c28: 200089d8 .word 0x200089d8
8002c2c: 40022000 .word 0x40022000
8002c30: 40022800 .word 0x40022800
08002c34 <BSP_LCD_MspInit>:
* @param hltdc: LTDC handle
* @param Params
* @retval None
*/
__weak void BSP_LCD_MspInit(LTDC_HandleTypeDef *hltdc, void *Params)
{
8002c34: b580 push {r7, lr}
8002c36: b090 sub sp, #64 ; 0x40
8002c38: af00 add r7, sp, #0
8002c3a: 6078 str r0, [r7, #4]
8002c3c: 6039 str r1, [r7, #0]
GPIO_InitTypeDef gpio_init_structure;
/* Enable the LTDC and DMA2D clocks */
__HAL_RCC_LTDC_CLK_ENABLE();
8002c3e: 4b64 ldr r3, [pc, #400] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c40: 6c5b ldr r3, [r3, #68] ; 0x44
8002c42: 4a63 ldr r2, [pc, #396] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c44: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8002c48: 6453 str r3, [r2, #68] ; 0x44
8002c4a: 4b61 ldr r3, [pc, #388] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c4c: 6c5b ldr r3, [r3, #68] ; 0x44
8002c4e: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8002c52: 62bb str r3, [r7, #40] ; 0x28
8002c54: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_DMA2D_CLK_ENABLE();
8002c56: 4b5e ldr r3, [pc, #376] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c58: 6b1b ldr r3, [r3, #48] ; 0x30
8002c5a: 4a5d ldr r2, [pc, #372] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c5c: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8002c60: 6313 str r3, [r2, #48] ; 0x30
8002c62: 4b5b ldr r3, [pc, #364] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c64: 6b1b ldr r3, [r3, #48] ; 0x30
8002c66: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8002c6a: 627b str r3, [r7, #36] ; 0x24
8002c6c: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOE_CLK_ENABLE();
8002c6e: 4b58 ldr r3, [pc, #352] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c70: 6b1b ldr r3, [r3, #48] ; 0x30
8002c72: 4a57 ldr r2, [pc, #348] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c74: f043 0310 orr.w r3, r3, #16
8002c78: 6313 str r3, [r2, #48] ; 0x30
8002c7a: 4b55 ldr r3, [pc, #340] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c7c: 6b1b ldr r3, [r3, #48] ; 0x30
8002c7e: f003 0310 and.w r3, r3, #16
8002c82: 623b str r3, [r7, #32]
8002c84: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOG_CLK_ENABLE();
8002c86: 4b52 ldr r3, [pc, #328] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c88: 6b1b ldr r3, [r3, #48] ; 0x30
8002c8a: 4a51 ldr r2, [pc, #324] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c8c: f043 0340 orr.w r3, r3, #64 ; 0x40
8002c90: 6313 str r3, [r2, #48] ; 0x30
8002c92: 4b4f ldr r3, [pc, #316] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002c94: 6b1b ldr r3, [r3, #48] ; 0x30
8002c96: f003 0340 and.w r3, r3, #64 ; 0x40
8002c9a: 61fb str r3, [r7, #28]
8002c9c: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOI_CLK_ENABLE();
8002c9e: 4b4c ldr r3, [pc, #304] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002ca0: 6b1b ldr r3, [r3, #48] ; 0x30
8002ca2: 4a4b ldr r2, [pc, #300] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002ca4: f443 7380 orr.w r3, r3, #256 ; 0x100
8002ca8: 6313 str r3, [r2, #48] ; 0x30
8002caa: 4b49 ldr r3, [pc, #292] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cac: 6b1b ldr r3, [r3, #48] ; 0x30
8002cae: f403 7380 and.w r3, r3, #256 ; 0x100
8002cb2: 61bb str r3, [r7, #24]
8002cb4: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8002cb6: 4b46 ldr r3, [pc, #280] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cb8: 6b1b ldr r3, [r3, #48] ; 0x30
8002cba: 4a45 ldr r2, [pc, #276] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cbc: f443 7300 orr.w r3, r3, #512 ; 0x200
8002cc0: 6313 str r3, [r2, #48] ; 0x30
8002cc2: 4b43 ldr r3, [pc, #268] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cc4: 6b1b ldr r3, [r3, #48] ; 0x30
8002cc6: f403 7300 and.w r3, r3, #512 ; 0x200
8002cca: 617b str r3, [r7, #20]
8002ccc: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOK_CLK_ENABLE();
8002cce: 4b40 ldr r3, [pc, #256] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cd0: 6b1b ldr r3, [r3, #48] ; 0x30
8002cd2: 4a3f ldr r2, [pc, #252] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cd4: f443 6380 orr.w r3, r3, #1024 ; 0x400
8002cd8: 6313 str r3, [r2, #48] ; 0x30
8002cda: 4b3d ldr r3, [pc, #244] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cdc: 6b1b ldr r3, [r3, #48] ; 0x30
8002cde: f403 6380 and.w r3, r3, #1024 ; 0x400
8002ce2: 613b str r3, [r7, #16]
8002ce4: 693b ldr r3, [r7, #16]
LCD_DISP_GPIO_CLK_ENABLE();
8002ce6: 4b3a ldr r3, [pc, #232] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002ce8: 6b1b ldr r3, [r3, #48] ; 0x30
8002cea: 4a39 ldr r2, [pc, #228] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cec: f443 7380 orr.w r3, r3, #256 ; 0x100
8002cf0: 6313 str r3, [r2, #48] ; 0x30
8002cf2: 4b37 ldr r3, [pc, #220] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002cf4: 6b1b ldr r3, [r3, #48] ; 0x30
8002cf6: f403 7380 and.w r3, r3, #256 ; 0x100
8002cfa: 60fb str r3, [r7, #12]
8002cfc: 68fb ldr r3, [r7, #12]
LCD_BL_CTRL_GPIO_CLK_ENABLE();
8002cfe: 4b34 ldr r3, [pc, #208] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002d00: 6b1b ldr r3, [r3, #48] ; 0x30
8002d02: 4a33 ldr r2, [pc, #204] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002d04: f443 6380 orr.w r3, r3, #1024 ; 0x400
8002d08: 6313 str r3, [r2, #48] ; 0x30
8002d0a: 4b31 ldr r3, [pc, #196] ; (8002dd0 <BSP_LCD_MspInit+0x19c>)
8002d0c: 6b1b ldr r3, [r3, #48] ; 0x30
8002d0e: f403 6380 and.w r3, r3, #1024 ; 0x400
8002d12: 60bb str r3, [r7, #8]
8002d14: 68bb ldr r3, [r7, #8]
/*** LTDC Pins configuration ***/
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_4;
8002d16: 2310 movs r3, #16
8002d18: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8002d1a: 2302 movs r3, #2
8002d1c: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_NOPULL;
8002d1e: 2300 movs r3, #0
8002d20: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8002d22: 2302 movs r3, #2
8002d24: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8002d26: 230e movs r3, #14
8002d28: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
8002d2a: f107 032c add.w r3, r7, #44 ; 0x2c
8002d2e: 4619 mov r1, r3
8002d30: 4828 ldr r0, [pc, #160] ; (8002dd4 <BSP_LCD_MspInit+0x1a0>)
8002d32: f002 fddd bl 80058f0 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_12;
8002d36: f44f 5380 mov.w r3, #4096 ; 0x1000
8002d3a: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8002d3c: 2302 movs r3, #2
8002d3e: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
8002d40: 2309 movs r3, #9
8002d42: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
8002d44: f107 032c add.w r3, r7, #44 ; 0x2c
8002d48: 4619 mov r1, r3
8002d4a: 4823 ldr r0, [pc, #140] ; (8002dd8 <BSP_LCD_MspInit+0x1a4>)
8002d4c: f002 fdd0 bl 80058f0 <HAL_GPIO_Init>
/* GPIOI LTDC alternate configuration */
gpio_init_structure.Pin = GPIO_PIN_9 | GPIO_PIN_10 | \
8002d50: f44f 4366 mov.w r3, #58880 ; 0xe600
8002d54: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8002d56: 2302 movs r3, #2
8002d58: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8002d5a: 230e movs r3, #14
8002d5c: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
8002d5e: f107 032c add.w r3, r7, #44 ; 0x2c
8002d62: 4619 mov r1, r3
8002d64: 481d ldr r0, [pc, #116] ; (8002ddc <BSP_LCD_MspInit+0x1a8>)
8002d66: f002 fdc3 bl 80058f0 <HAL_GPIO_Init>
/* GPIOJ configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
8002d6a: f64e 73ff movw r3, #61439 ; 0xefff
8002d6e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8002d70: 2302 movs r3, #2
8002d72: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8002d74: 230e movs r3, #14
8002d76: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
8002d78: f107 032c add.w r3, r7, #44 ; 0x2c
8002d7c: 4619 mov r1, r3
8002d7e: 4818 ldr r0, [pc, #96] ; (8002de0 <BSP_LCD_MspInit+0x1ac>)
8002d80: f002 fdb6 bl 80058f0 <HAL_GPIO_Init>
/* GPIOK configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
8002d84: 23f7 movs r3, #247 ; 0xf7
8002d86: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
8002d88: 2302 movs r3, #2
8002d8a: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
8002d8c: 230e movs r3, #14
8002d8e: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
8002d90: f107 032c add.w r3, r7, #44 ; 0x2c
8002d94: 4619 mov r1, r3
8002d96: 4813 ldr r0, [pc, #76] ; (8002de4 <BSP_LCD_MspInit+0x1b0>)
8002d98: f002 fdaa bl 80058f0 <HAL_GPIO_Init>
/* LCD_DISP GPIO configuration */
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
8002d9c: f44f 5380 mov.w r3, #4096 ; 0x1000
8002da0: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
8002da2: 2301 movs r3, #1
8002da4: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
8002da6: f107 032c add.w r3, r7, #44 ; 0x2c
8002daa: 4619 mov r1, r3
8002dac: 480b ldr r0, [pc, #44] ; (8002ddc <BSP_LCD_MspInit+0x1a8>)
8002dae: f002 fd9f bl 80058f0 <HAL_GPIO_Init>
/* LCD_BL_CTRL GPIO configuration */
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
8002db2: 2308 movs r3, #8
8002db4: 62fb str r3, [r7, #44] ; 0x2c
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
8002db6: 2301 movs r3, #1
8002db8: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
8002dba: f107 032c add.w r3, r7, #44 ; 0x2c
8002dbe: 4619 mov r1, r3
8002dc0: 4808 ldr r0, [pc, #32] ; (8002de4 <BSP_LCD_MspInit+0x1b0>)
8002dc2: f002 fd95 bl 80058f0 <HAL_GPIO_Init>
}
8002dc6: bf00 nop
8002dc8: 3740 adds r7, #64 ; 0x40
8002dca: 46bd mov sp, r7
8002dcc: bd80 pop {r7, pc}
8002dce: bf00 nop
8002dd0: 40023800 .word 0x40023800
8002dd4: 40021000 .word 0x40021000
8002dd8: 40021800 .word 0x40021800
8002ddc: 40022000 .word 0x40022000
8002de0: 40022400 .word 0x40022400
8002de4: 40022800 .word 0x40022800
08002de8 <BSP_LCD_ClockConfig>:
* @note This API is called by BSP_LCD_Init()
* Being __weak it can be overwritten by the application
* @retval None
*/
__weak void BSP_LCD_ClockConfig(LTDC_HandleTypeDef *hltdc, void *Params)
{
8002de8: b580 push {r7, lr}
8002dea: b082 sub sp, #8
8002dec: af00 add r7, sp, #0
8002dee: 6078 str r0, [r7, #4]
8002df0: 6039 str r1, [r7, #0]
/* RK043FN48H LCD clock configuration */
/* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
/* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz */
/* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz */
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
8002df2: 4b0a ldr r3, [pc, #40] ; (8002e1c <BSP_LCD_ClockConfig+0x34>)
8002df4: 2208 movs r2, #8
8002df6: 601a str r2, [r3, #0]
periph_clk_init_struct.PLLSAI.PLLSAIN = 192;
8002df8: 4b08 ldr r3, [pc, #32] ; (8002e1c <BSP_LCD_ClockConfig+0x34>)
8002dfa: 22c0 movs r2, #192 ; 0xc0
8002dfc: 615a str r2, [r3, #20]
periph_clk_init_struct.PLLSAI.PLLSAIR = RK043FN48H_FREQUENCY_DIVIDER;
8002dfe: 4b07 ldr r3, [pc, #28] ; (8002e1c <BSP_LCD_ClockConfig+0x34>)
8002e00: 2205 movs r2, #5
8002e02: 61da str r2, [r3, #28]
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_4;
8002e04: 4b05 ldr r3, [pc, #20] ; (8002e1c <BSP_LCD_ClockConfig+0x34>)
8002e06: f44f 3280 mov.w r2, #65536 ; 0x10000
8002e0a: 62da str r2, [r3, #44] ; 0x2c
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
8002e0c: 4803 ldr r0, [pc, #12] ; (8002e1c <BSP_LCD_ClockConfig+0x34>)
8002e0e: f004 fe85 bl 8007b1c <HAL_RCCEx_PeriphCLKConfig>
}
8002e12: bf00 nop
8002e14: 3708 adds r7, #8
8002e16: 46bd mov sp, r7
8002e18: bd80 pop {r7, pc}
8002e1a: bf00 nop
8002e1c: 200001a8 .word 0x200001a8
08002e20 <DrawChar>:
* @param Ypos: Start column address
* @param c: Pointer to the character data
* @retval None
*/
static void DrawChar(uint16_t Xpos, uint16_t Ypos, const uint8_t *c)
{
8002e20: b580 push {r7, lr}
8002e22: b088 sub sp, #32
8002e24: af00 add r7, sp, #0
8002e26: 4603 mov r3, r0
8002e28: 603a str r2, [r7, #0]
8002e2a: 80fb strh r3, [r7, #6]
8002e2c: 460b mov r3, r1
8002e2e: 80bb strh r3, [r7, #4]
uint32_t i = 0, j = 0;
8002e30: 2300 movs r3, #0
8002e32: 61fb str r3, [r7, #28]
8002e34: 2300 movs r3, #0
8002e36: 61bb str r3, [r7, #24]
uint16_t height, width;
uint8_t offset;
uint8_t *pchar;
uint32_t line;
height = DrawProp[ActiveLayer].pFont->Height;
8002e38: 4b53 ldr r3, [pc, #332] ; (8002f88 <DrawChar+0x168>)
8002e3a: 681a ldr r2, [r3, #0]
8002e3c: 4953 ldr r1, [pc, #332] ; (8002f8c <DrawChar+0x16c>)
8002e3e: 4613 mov r3, r2
8002e40: 005b lsls r3, r3, #1
8002e42: 4413 add r3, r2
8002e44: 009b lsls r3, r3, #2
8002e46: 440b add r3, r1
8002e48: 3308 adds r3, #8
8002e4a: 681b ldr r3, [r3, #0]
8002e4c: 88db ldrh r3, [r3, #6]
8002e4e: 827b strh r3, [r7, #18]
width = DrawProp[ActiveLayer].pFont->Width;
8002e50: 4b4d ldr r3, [pc, #308] ; (8002f88 <DrawChar+0x168>)
8002e52: 681a ldr r2, [r3, #0]
8002e54: 494d ldr r1, [pc, #308] ; (8002f8c <DrawChar+0x16c>)
8002e56: 4613 mov r3, r2
8002e58: 005b lsls r3, r3, #1
8002e5a: 4413 add r3, r2
8002e5c: 009b lsls r3, r3, #2
8002e5e: 440b add r3, r1
8002e60: 3308 adds r3, #8
8002e62: 681b ldr r3, [r3, #0]
8002e64: 889b ldrh r3, [r3, #4]
8002e66: 823b strh r3, [r7, #16]
offset = 8 *((width + 7)/8) - width ;
8002e68: 8a3b ldrh r3, [r7, #16]
8002e6a: 3307 adds r3, #7
8002e6c: 2b00 cmp r3, #0
8002e6e: da00 bge.n 8002e72 <DrawChar+0x52>
8002e70: 3307 adds r3, #7
8002e72: 10db asrs r3, r3, #3
8002e74: b2db uxtb r3, r3
8002e76: 00db lsls r3, r3, #3
8002e78: b2da uxtb r2, r3
8002e7a: 8a3b ldrh r3, [r7, #16]
8002e7c: b2db uxtb r3, r3
8002e7e: 1ad3 subs r3, r2, r3
8002e80: 73fb strb r3, [r7, #15]
for(i = 0; i < height; i++)
8002e82: 2300 movs r3, #0
8002e84: 61fb str r3, [r7, #28]
8002e86: e076 b.n 8002f76 <DrawChar+0x156>
{
pchar = ((uint8_t *)c + (width + 7)/8 * i);
8002e88: 8a3b ldrh r3, [r7, #16]
8002e8a: 3307 adds r3, #7
8002e8c: 2b00 cmp r3, #0
8002e8e: da00 bge.n 8002e92 <DrawChar+0x72>
8002e90: 3307 adds r3, #7
8002e92: 10db asrs r3, r3, #3
8002e94: 461a mov r2, r3
8002e96: 69fb ldr r3, [r7, #28]
8002e98: fb03 f302 mul.w r3, r3, r2
8002e9c: 683a ldr r2, [r7, #0]
8002e9e: 4413 add r3, r2
8002ea0: 60bb str r3, [r7, #8]
switch(((width + 7)/8))
8002ea2: 8a3b ldrh r3, [r7, #16]
8002ea4: 3307 adds r3, #7
8002ea6: 2b00 cmp r3, #0
8002ea8: da00 bge.n 8002eac <DrawChar+0x8c>
8002eaa: 3307 adds r3, #7
8002eac: 10db asrs r3, r3, #3
8002eae: 2b01 cmp r3, #1
8002eb0: d002 beq.n 8002eb8 <DrawChar+0x98>
8002eb2: 2b02 cmp r3, #2
8002eb4: d004 beq.n 8002ec0 <DrawChar+0xa0>
8002eb6: e00c b.n 8002ed2 <DrawChar+0xb2>
{
case 1:
line = pchar[0];
8002eb8: 68bb ldr r3, [r7, #8]
8002eba: 781b ldrb r3, [r3, #0]
8002ebc: 617b str r3, [r7, #20]
break;
8002ebe: e016 b.n 8002eee <DrawChar+0xce>
case 2:
line = (pchar[0]<< 8) | pchar[1];
8002ec0: 68bb ldr r3, [r7, #8]
8002ec2: 781b ldrb r3, [r3, #0]
8002ec4: 021b lsls r3, r3, #8
8002ec6: 68ba ldr r2, [r7, #8]
8002ec8: 3201 adds r2, #1
8002eca: 7812 ldrb r2, [r2, #0]
8002ecc: 4313 orrs r3, r2
8002ece: 617b str r3, [r7, #20]
break;
8002ed0: e00d b.n 8002eee <DrawChar+0xce>
case 3:
default:
line = (pchar[0]<< 16) | (pchar[1]<< 8) | pchar[2];
8002ed2: 68bb ldr r3, [r7, #8]
8002ed4: 781b ldrb r3, [r3, #0]
8002ed6: 041a lsls r2, r3, #16
8002ed8: 68bb ldr r3, [r7, #8]
8002eda: 3301 adds r3, #1
8002edc: 781b ldrb r3, [r3, #0]
8002ede: 021b lsls r3, r3, #8
8002ee0: 4313 orrs r3, r2
8002ee2: 68ba ldr r2, [r7, #8]
8002ee4: 3202 adds r2, #2
8002ee6: 7812 ldrb r2, [r2, #0]
8002ee8: 4313 orrs r3, r2
8002eea: 617b str r3, [r7, #20]
break;
8002eec: bf00 nop
}
for (j = 0; j < width; j++)
8002eee: 2300 movs r3, #0
8002ef0: 61bb str r3, [r7, #24]
8002ef2: e036 b.n 8002f62 <DrawChar+0x142>
{
if(line & (1 << (width- j + offset- 1)))
8002ef4: 8a3a ldrh r2, [r7, #16]
8002ef6: 69bb ldr r3, [r7, #24]
8002ef8: 1ad2 subs r2, r2, r3
8002efa: 7bfb ldrb r3, [r7, #15]
8002efc: 4413 add r3, r2
8002efe: 3b01 subs r3, #1
8002f00: 2201 movs r2, #1
8002f02: fa02 f303 lsl.w r3, r2, r3
8002f06: 461a mov r2, r3
8002f08: 697b ldr r3, [r7, #20]
8002f0a: 4013 ands r3, r2
8002f0c: 2b00 cmp r3, #0
8002f0e: d012 beq.n 8002f36 <DrawChar+0x116>
{
BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].TextColor);
8002f10: 69bb ldr r3, [r7, #24]
8002f12: b29a uxth r2, r3
8002f14: 88fb ldrh r3, [r7, #6]
8002f16: 4413 add r3, r2
8002f18: b298 uxth r0, r3
8002f1a: 4b1b ldr r3, [pc, #108] ; (8002f88 <DrawChar+0x168>)
8002f1c: 681a ldr r2, [r3, #0]
8002f1e: 491b ldr r1, [pc, #108] ; (8002f8c <DrawChar+0x16c>)
8002f20: 4613 mov r3, r2
8002f22: 005b lsls r3, r3, #1
8002f24: 4413 add r3, r2
8002f26: 009b lsls r3, r3, #2
8002f28: 440b add r3, r1
8002f2a: 681a ldr r2, [r3, #0]
8002f2c: 88bb ldrh r3, [r7, #4]
8002f2e: 4619 mov r1, r3
8002f30: f7ff fd7a bl 8002a28 <BSP_LCD_DrawPixel>
8002f34: e012 b.n 8002f5c <DrawChar+0x13c>
}
else
{
BSP_LCD_DrawPixel((Xpos + j), Ypos, DrawProp[ActiveLayer].BackColor);
8002f36: 69bb ldr r3, [r7, #24]
8002f38: b29a uxth r2, r3
8002f3a: 88fb ldrh r3, [r7, #6]
8002f3c: 4413 add r3, r2
8002f3e: b298 uxth r0, r3
8002f40: 4b11 ldr r3, [pc, #68] ; (8002f88 <DrawChar+0x168>)
8002f42: 681a ldr r2, [r3, #0]
8002f44: 4911 ldr r1, [pc, #68] ; (8002f8c <DrawChar+0x16c>)
8002f46: 4613 mov r3, r2
8002f48: 005b lsls r3, r3, #1
8002f4a: 4413 add r3, r2
8002f4c: 009b lsls r3, r3, #2
8002f4e: 440b add r3, r1
8002f50: 3304 adds r3, #4
8002f52: 681a ldr r2, [r3, #0]
8002f54: 88bb ldrh r3, [r7, #4]
8002f56: 4619 mov r1, r3
8002f58: f7ff fd66 bl 8002a28 <BSP_LCD_DrawPixel>
for (j = 0; j < width; j++)
8002f5c: 69bb ldr r3, [r7, #24]
8002f5e: 3301 adds r3, #1
8002f60: 61bb str r3, [r7, #24]
8002f62: 8a3b ldrh r3, [r7, #16]
8002f64: 69ba ldr r2, [r7, #24]
8002f66: 429a cmp r2, r3
8002f68: d3c4 bcc.n 8002ef4 <DrawChar+0xd4>
}
}
Ypos++;
8002f6a: 88bb ldrh r3, [r7, #4]
8002f6c: 3301 adds r3, #1
8002f6e: 80bb strh r3, [r7, #4]
for(i = 0; i < height; i++)
8002f70: 69fb ldr r3, [r7, #28]
8002f72: 3301 adds r3, #1
8002f74: 61fb str r3, [r7, #28]
8002f76: 8a7b ldrh r3, [r7, #18]
8002f78: 69fa ldr r2, [r7, #28]
8002f7a: 429a cmp r2, r3
8002f7c: d384 bcc.n 8002e88 <DrawChar+0x68>
}
}
8002f7e: bf00 nop
8002f80: 3720 adds r7, #32
8002f82: 46bd mov sp, r7
8002f84: bd80 pop {r7, pc}
8002f86: bf00 nop
8002f88: 2000018c .word 0x2000018c
8002f8c: 20000190 .word 0x20000190
08002f90 <LL_FillBuffer>:
* @param OffLine: Offset
* @param ColorIndex: Color index
* @retval None
*/
static void LL_FillBuffer(uint32_t LayerIndex, void *pDst, uint32_t xSize, uint32_t ySize, uint32_t OffLine, uint32_t ColorIndex)
{
8002f90: b580 push {r7, lr}
8002f92: b086 sub sp, #24
8002f94: af02 add r7, sp, #8
8002f96: 60f8 str r0, [r7, #12]
8002f98: 60b9 str r1, [r7, #8]
8002f9a: 607a str r2, [r7, #4]
8002f9c: 603b str r3, [r7, #0]
/* Register to memory mode with ARGB8888 as color Mode */
hDma2dHandler.Init.Mode = DMA2D_R2M;
8002f9e: 4b1e ldr r3, [pc, #120] ; (8003018 <LL_FillBuffer+0x88>)
8002fa0: f44f 3240 mov.w r2, #196608 ; 0x30000
8002fa4: 605a str r2, [r3, #4]
if(hLtdcHandler.LayerCfg[ActiveLayer].PixelFormat == LTDC_PIXEL_FORMAT_RGB565)
8002fa6: 4b1d ldr r3, [pc, #116] ; (800301c <LL_FillBuffer+0x8c>)
8002fa8: 681b ldr r3, [r3, #0]
8002faa: 4a1d ldr r2, [pc, #116] ; (8003020 <LL_FillBuffer+0x90>)
8002fac: 2134 movs r1, #52 ; 0x34
8002fae: fb01 f303 mul.w r3, r1, r3
8002fb2: 4413 add r3, r2
8002fb4: 3348 adds r3, #72 ; 0x48
8002fb6: 681b ldr r3, [r3, #0]
8002fb8: 2b02 cmp r3, #2
8002fba: d103 bne.n 8002fc4 <LL_FillBuffer+0x34>
{ /* RGB565 format */
hDma2dHandler.Init.ColorMode = DMA2D_RGB565;
8002fbc: 4b16 ldr r3, [pc, #88] ; (8003018 <LL_FillBuffer+0x88>)
8002fbe: 2202 movs r2, #2
8002fc0: 609a str r2, [r3, #8]
8002fc2: e002 b.n 8002fca <LL_FillBuffer+0x3a>
}
else
{ /* ARGB8888 format */
hDma2dHandler.Init.ColorMode = DMA2D_ARGB8888;
8002fc4: 4b14 ldr r3, [pc, #80] ; (8003018 <LL_FillBuffer+0x88>)
8002fc6: 2200 movs r2, #0
8002fc8: 609a str r2, [r3, #8]
}
hDma2dHandler.Init.OutputOffset = OffLine;
8002fca: 4a13 ldr r2, [pc, #76] ; (8003018 <LL_FillBuffer+0x88>)
8002fcc: 69bb ldr r3, [r7, #24]
8002fce: 60d3 str r3, [r2, #12]
hDma2dHandler.Instance = DMA2D;
8002fd0: 4b11 ldr r3, [pc, #68] ; (8003018 <LL_FillBuffer+0x88>)
8002fd2: 4a14 ldr r2, [pc, #80] ; (8003024 <LL_FillBuffer+0x94>)
8002fd4: 601a str r2, [r3, #0]
/* DMA2D Initialization */
if(HAL_DMA2D_Init(&hDma2dHandler) == HAL_OK)
8002fd6: 4810 ldr r0, [pc, #64] ; (8003018 <LL_FillBuffer+0x88>)
8002fd8: f002 f9fe bl 80053d8 <HAL_DMA2D_Init>
8002fdc: 4603 mov r3, r0
8002fde: 2b00 cmp r3, #0
8002fe0: d115 bne.n 800300e <LL_FillBuffer+0x7e>
{
if(HAL_DMA2D_ConfigLayer(&hDma2dHandler, LayerIndex) == HAL_OK)
8002fe2: 68f9 ldr r1, [r7, #12]
8002fe4: 480c ldr r0, [pc, #48] ; (8003018 <LL_FillBuffer+0x88>)
8002fe6: f002 fb55 bl 8005694 <HAL_DMA2D_ConfigLayer>
8002fea: 4603 mov r3, r0
8002fec: 2b00 cmp r3, #0
8002fee: d10e bne.n 800300e <LL_FillBuffer+0x7e>
{
if (HAL_DMA2D_Start(&hDma2dHandler, ColorIndex, (uint32_t)pDst, xSize, ySize) == HAL_OK)
8002ff0: 68ba ldr r2, [r7, #8]
8002ff2: 683b ldr r3, [r7, #0]
8002ff4: 9300 str r3, [sp, #0]
8002ff6: 687b ldr r3, [r7, #4]
8002ff8: 69f9 ldr r1, [r7, #28]
8002ffa: 4807 ldr r0, [pc, #28] ; (8003018 <LL_FillBuffer+0x88>)
8002ffc: f002 fa36 bl 800546c <HAL_DMA2D_Start>
8003000: 4603 mov r3, r0
8003002: 2b00 cmp r3, #0
8003004: d103 bne.n 800300e <LL_FillBuffer+0x7e>
{
/* Polling For DMA transfer */
HAL_DMA2D_PollForTransfer(&hDma2dHandler, 10);
8003006: 210a movs r1, #10
8003008: 4803 ldr r0, [pc, #12] ; (8003018 <LL_FillBuffer+0x88>)
800300a: f002 fa5a bl 80054c2 <HAL_DMA2D_PollForTransfer>
}
}
}
}
800300e: bf00 nop
8003010: 3710 adds r7, #16
8003012: 46bd mov sp, r7
8003014: bd80 pop {r7, pc}
8003016: bf00 nop
8003018: 2000014c .word 0x2000014c
800301c: 2000018c .word 0x2000018c
8003020: 200089d8 .word 0x200089d8
8003024: 4002b000 .word 0x4002b000
08003028 <BSP_SDRAM_Init>:
/**
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
{
8003028: b580 push {r7, lr}
800302a: af00 add r7, sp, #0
static uint8_t sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
800302c: 4b29 ldr r3, [pc, #164] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800302e: 4a2a ldr r2, [pc, #168] ; (80030d8 <BSP_SDRAM_Init+0xb0>)
8003030: 601a str r2, [r3, #0]
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
Timing.LoadToActiveDelay = 2;
8003032: 4b2a ldr r3, [pc, #168] ; (80030dc <BSP_SDRAM_Init+0xb4>)
8003034: 2202 movs r2, #2
8003036: 601a str r2, [r3, #0]
Timing.ExitSelfRefreshDelay = 7;
8003038: 4b28 ldr r3, [pc, #160] ; (80030dc <BSP_SDRAM_Init+0xb4>)
800303a: 2207 movs r2, #7
800303c: 605a str r2, [r3, #4]
Timing.SelfRefreshTime = 4;
800303e: 4b27 ldr r3, [pc, #156] ; (80030dc <BSP_SDRAM_Init+0xb4>)
8003040: 2204 movs r2, #4
8003042: 609a str r2, [r3, #8]
Timing.RowCycleDelay = 7;
8003044: 4b25 ldr r3, [pc, #148] ; (80030dc <BSP_SDRAM_Init+0xb4>)
8003046: 2207 movs r2, #7
8003048: 60da str r2, [r3, #12]
Timing.WriteRecoveryTime = 2;
800304a: 4b24 ldr r3, [pc, #144] ; (80030dc <BSP_SDRAM_Init+0xb4>)
800304c: 2202 movs r2, #2
800304e: 611a str r2, [r3, #16]
Timing.RPDelay = 2;
8003050: 4b22 ldr r3, [pc, #136] ; (80030dc <BSP_SDRAM_Init+0xb4>)
8003052: 2202 movs r2, #2
8003054: 615a str r2, [r3, #20]
Timing.RCDDelay = 2;
8003056: 4b21 ldr r3, [pc, #132] ; (80030dc <BSP_SDRAM_Init+0xb4>)
8003058: 2202 movs r2, #2
800305a: 619a str r2, [r3, #24]
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
800305c: 4b1d ldr r3, [pc, #116] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800305e: 2200 movs r2, #0
8003060: 605a str r2, [r3, #4]
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
8003062: 4b1c ldr r3, [pc, #112] ; (80030d4 <BSP_SDRAM_Init+0xac>)
8003064: 2200 movs r2, #0
8003066: 609a str r2, [r3, #8]
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
8003068: 4b1a ldr r3, [pc, #104] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800306a: 2204 movs r2, #4
800306c: 60da str r2, [r3, #12]
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
800306e: 4b19 ldr r3, [pc, #100] ; (80030d4 <BSP_SDRAM_Init+0xac>)
8003070: 2210 movs r2, #16
8003072: 611a str r2, [r3, #16]
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
8003074: 4b17 ldr r3, [pc, #92] ; (80030d4 <BSP_SDRAM_Init+0xac>)
8003076: 2240 movs r2, #64 ; 0x40
8003078: 615a str r2, [r3, #20]
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
800307a: 4b16 ldr r3, [pc, #88] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800307c: f44f 7280 mov.w r2, #256 ; 0x100
8003080: 619a str r2, [r3, #24]
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
8003082: 4b14 ldr r3, [pc, #80] ; (80030d4 <BSP_SDRAM_Init+0xac>)
8003084: 2200 movs r2, #0
8003086: 61da str r2, [r3, #28]
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
8003088: 4b12 ldr r3, [pc, #72] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800308a: f44f 6200 mov.w r2, #2048 ; 0x800
800308e: 621a str r2, [r3, #32]
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
8003090: 4b10 ldr r3, [pc, #64] ; (80030d4 <BSP_SDRAM_Init+0xac>)
8003092: f44f 5280 mov.w r2, #4096 ; 0x1000
8003096: 625a str r2, [r3, #36] ; 0x24
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
8003098: 4b0e ldr r3, [pc, #56] ; (80030d4 <BSP_SDRAM_Init+0xac>)
800309a: 2200 movs r2, #0
800309c: 629a str r2, [r3, #40] ; 0x28
/* SDRAM controller initialization */
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
800309e: 2100 movs r1, #0
80030a0: 480c ldr r0, [pc, #48] ; (80030d4 <BSP_SDRAM_Init+0xac>)
80030a2: f000 f87f bl 80031a4 <BSP_SDRAM_MspInit>
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
80030a6: 490d ldr r1, [pc, #52] ; (80030dc <BSP_SDRAM_Init+0xb4>)
80030a8: 480a ldr r0, [pc, #40] ; (80030d4 <BSP_SDRAM_Init+0xac>)
80030aa: f005 fce7 bl 8008a7c <HAL_SDRAM_Init>
80030ae: 4603 mov r3, r0
80030b0: 2b00 cmp r3, #0
80030b2: d003 beq.n 80030bc <BSP_SDRAM_Init+0x94>
{
sdramstatus = SDRAM_ERROR;
80030b4: 4b0a ldr r3, [pc, #40] ; (80030e0 <BSP_SDRAM_Init+0xb8>)
80030b6: 2201 movs r2, #1
80030b8: 701a strb r2, [r3, #0]
80030ba: e002 b.n 80030c2 <BSP_SDRAM_Init+0x9a>
}
else
{
sdramstatus = SDRAM_OK;
80030bc: 4b08 ldr r3, [pc, #32] ; (80030e0 <BSP_SDRAM_Init+0xb8>)
80030be: 2200 movs r2, #0
80030c0: 701a strb r2, [r3, #0]
}
/* SDRAM initialization sequence */
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
80030c2: f240 6003 movw r0, #1539 ; 0x603
80030c6: f000 f80d bl 80030e4 <BSP_SDRAM_Initialization_sequence>
return sdramstatus;
80030ca: 4b05 ldr r3, [pc, #20] ; (80030e0 <BSP_SDRAM_Init+0xb8>)
80030cc: 781b ldrb r3, [r3, #0]
}
80030ce: 4618 mov r0, r3
80030d0: bd80 pop {r7, pc}
80030d2: bf00 nop
80030d4: 20008a80 .word 0x20008a80
80030d8: a0000140 .word 0xa0000140
80030dc: 2000022c .word 0x2000022c
80030e0: 20000038 .word 0x20000038
080030e4 <BSP_SDRAM_Initialization_sequence>:
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
* @retval None
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
{
80030e4: b580 push {r7, lr}
80030e6: b084 sub sp, #16
80030e8: af00 add r7, sp, #0
80030ea: 6078 str r0, [r7, #4]
__IO uint32_t tmpmrd = 0;
80030ec: 2300 movs r3, #0
80030ee: 60fb str r3, [r7, #12]
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
80030f0: 4b2a ldr r3, [pc, #168] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
80030f2: 2201 movs r2, #1
80030f4: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
80030f6: 4b29 ldr r3, [pc, #164] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
80030f8: 2210 movs r2, #16
80030fa: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
80030fc: 4b27 ldr r3, [pc, #156] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
80030fe: 2201 movs r2, #1
8003100: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003102: 4b26 ldr r3, [pc, #152] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003104: 2200 movs r2, #0
8003106: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003108: f64f 72ff movw r2, #65535 ; 0xffff
800310c: 4923 ldr r1, [pc, #140] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800310e: 4824 ldr r0, [pc, #144] ; (80031a0 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003110: f005 fce8 bl 8008ae4 <HAL_SDRAM_SendCommand>
/* Step 2: Insert 100 us minimum delay */
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
HAL_Delay(1);
8003114: 2001 movs r0, #1
8003116: f001 f9f7 bl 8004508 <HAL_Delay>
/* Step 3: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
800311a: 4b20 ldr r3, [pc, #128] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800311c: 2202 movs r2, #2
800311e: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003120: 4b1e ldr r3, [pc, #120] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003122: 2210 movs r2, #16
8003124: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003126: 4b1d ldr r3, [pc, #116] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003128: 2201 movs r2, #1
800312a: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
800312c: 4b1b ldr r3, [pc, #108] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800312e: 2200 movs r2, #0
8003130: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003132: f64f 72ff movw r2, #65535 ; 0xffff
8003136: 4919 ldr r1, [pc, #100] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003138: 4819 ldr r0, [pc, #100] ; (80031a0 <BSP_SDRAM_Initialization_sequence+0xbc>)
800313a: f005 fcd3 bl 8008ae4 <HAL_SDRAM_SendCommand>
/* Step 4: Configure an Auto Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
800313e: 4b17 ldr r3, [pc, #92] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003140: 2203 movs r2, #3
8003142: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
8003144: 4b15 ldr r3, [pc, #84] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003146: 2210 movs r2, #16
8003148: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 8;
800314a: 4b14 ldr r3, [pc, #80] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800314c: 2208 movs r2, #8
800314e: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = 0;
8003150: 4b12 ldr r3, [pc, #72] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003152: 2200 movs r2, #0
8003154: 60da str r2, [r3, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003156: f64f 72ff movw r2, #65535 ; 0xffff
800315a: 4910 ldr r1, [pc, #64] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800315c: 4810 ldr r0, [pc, #64] ; (80031a0 <BSP_SDRAM_Initialization_sequence+0xbc>)
800315e: f005 fcc1 bl 8008ae4 <HAL_SDRAM_SendCommand>
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
8003162: f44f 7308 mov.w r3, #544 ; 0x220
8003166: 60fb str r3, [r7, #12]
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_2 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
8003168: 4b0c ldr r3, [pc, #48] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800316a: 2204 movs r2, #4
800316c: 601a str r2, [r3, #0]
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
800316e: 4b0b ldr r3, [pc, #44] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003170: 2210 movs r2, #16
8003172: 605a str r2, [r3, #4]
Command.AutoRefreshNumber = 1;
8003174: 4b09 ldr r3, [pc, #36] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003176: 2201 movs r2, #1
8003178: 609a str r2, [r3, #8]
Command.ModeRegisterDefinition = tmpmrd;
800317a: 68fb ldr r3, [r7, #12]
800317c: 4a07 ldr r2, [pc, #28] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
800317e: 60d3 str r3, [r2, #12]
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
8003180: f64f 72ff movw r2, #65535 ; 0xffff
8003184: 4905 ldr r1, [pc, #20] ; (800319c <BSP_SDRAM_Initialization_sequence+0xb8>)
8003186: 4806 ldr r0, [pc, #24] ; (80031a0 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003188: f005 fcac bl 8008ae4 <HAL_SDRAM_SendCommand>
/* Step 6: Set the refresh rate counter */
/* Set the device refresh rate */
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
800318c: 6879 ldr r1, [r7, #4]
800318e: 4804 ldr r0, [pc, #16] ; (80031a0 <BSP_SDRAM_Initialization_sequence+0xbc>)
8003190: f005 fcd3 bl 8008b3a <HAL_SDRAM_ProgramRefreshRate>
}
8003194: bf00 nop
8003196: 3710 adds r7, #16
8003198: 46bd mov sp, r7
800319a: bd80 pop {r7, pc}
800319c: 20000248 .word 0x20000248
80031a0: 20008a80 .word 0x20008a80
080031a4 <BSP_SDRAM_MspInit>:
* @param hsdram: SDRAM handle
* @param Params
* @retval None
*/
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
{
80031a4: b580 push {r7, lr}
80031a6: b090 sub sp, #64 ; 0x40
80031a8: af00 add r7, sp, #0
80031aa: 6078 str r0, [r7, #4]
80031ac: 6039 str r1, [r7, #0]
static DMA_HandleTypeDef dma_handle;
GPIO_InitTypeDef gpio_init_structure;
/* Enable FMC clock */
__HAL_RCC_FMC_CLK_ENABLE();
80031ae: 4b70 ldr r3, [pc, #448] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031b0: 6b9b ldr r3, [r3, #56] ; 0x38
80031b2: 4a6f ldr r2, [pc, #444] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031b4: f043 0301 orr.w r3, r3, #1
80031b8: 6393 str r3, [r2, #56] ; 0x38
80031ba: 4b6d ldr r3, [pc, #436] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031bc: 6b9b ldr r3, [r3, #56] ; 0x38
80031be: f003 0301 and.w r3, r3, #1
80031c2: 62bb str r3, [r7, #40] ; 0x28
80031c4: 6abb ldr r3, [r7, #40] ; 0x28
/* Enable chosen DMAx clock */
__DMAx_CLK_ENABLE();
80031c6: 4b6a ldr r3, [pc, #424] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031c8: 6b1b ldr r3, [r3, #48] ; 0x30
80031ca: 4a69 ldr r2, [pc, #420] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031cc: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
80031d0: 6313 str r3, [r2, #48] ; 0x30
80031d2: 4b67 ldr r3, [pc, #412] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031d4: 6b1b ldr r3, [r3, #48] ; 0x30
80031d6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80031da: 627b str r3, [r7, #36] ; 0x24
80031dc: 6a7b ldr r3, [r7, #36] ; 0x24
/* Enable GPIOs clock */
__HAL_RCC_GPIOC_CLK_ENABLE();
80031de: 4b64 ldr r3, [pc, #400] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031e0: 6b1b ldr r3, [r3, #48] ; 0x30
80031e2: 4a63 ldr r2, [pc, #396] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031e4: f043 0304 orr.w r3, r3, #4
80031e8: 6313 str r3, [r2, #48] ; 0x30
80031ea: 4b61 ldr r3, [pc, #388] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031ec: 6b1b ldr r3, [r3, #48] ; 0x30
80031ee: f003 0304 and.w r3, r3, #4
80031f2: 623b str r3, [r7, #32]
80031f4: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOD_CLK_ENABLE();
80031f6: 4b5e ldr r3, [pc, #376] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031f8: 6b1b ldr r3, [r3, #48] ; 0x30
80031fa: 4a5d ldr r2, [pc, #372] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
80031fc: f043 0308 orr.w r3, r3, #8
8003200: 6313 str r3, [r2, #48] ; 0x30
8003202: 4b5b ldr r3, [pc, #364] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003204: 6b1b ldr r3, [r3, #48] ; 0x30
8003206: f003 0308 and.w r3, r3, #8
800320a: 61fb str r3, [r7, #28]
800320c: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOE_CLK_ENABLE();
800320e: 4b58 ldr r3, [pc, #352] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003210: 6b1b ldr r3, [r3, #48] ; 0x30
8003212: 4a57 ldr r2, [pc, #348] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003214: f043 0310 orr.w r3, r3, #16
8003218: 6313 str r3, [r2, #48] ; 0x30
800321a: 4b55 ldr r3, [pc, #340] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
800321c: 6b1b ldr r3, [r3, #48] ; 0x30
800321e: f003 0310 and.w r3, r3, #16
8003222: 61bb str r3, [r7, #24]
8003224: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003226: 4b52 ldr r3, [pc, #328] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003228: 6b1b ldr r3, [r3, #48] ; 0x30
800322a: 4a51 ldr r2, [pc, #324] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
800322c: f043 0320 orr.w r3, r3, #32
8003230: 6313 str r3, [r2, #48] ; 0x30
8003232: 4b4f ldr r3, [pc, #316] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003234: 6b1b ldr r3, [r3, #48] ; 0x30
8003236: f003 0320 and.w r3, r3, #32
800323a: 617b str r3, [r7, #20]
800323c: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
800323e: 4b4c ldr r3, [pc, #304] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003240: 6b1b ldr r3, [r3, #48] ; 0x30
8003242: 4a4b ldr r2, [pc, #300] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003244: f043 0340 orr.w r3, r3, #64 ; 0x40
8003248: 6313 str r3, [r2, #48] ; 0x30
800324a: 4b49 ldr r3, [pc, #292] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
800324c: 6b1b ldr r3, [r3, #48] ; 0x30
800324e: f003 0340 and.w r3, r3, #64 ; 0x40
8003252: 613b str r3, [r7, #16]
8003254: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
8003256: 4b46 ldr r3, [pc, #280] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003258: 6b1b ldr r3, [r3, #48] ; 0x30
800325a: 4a45 ldr r2, [pc, #276] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
800325c: f043 0380 orr.w r3, r3, #128 ; 0x80
8003260: 6313 str r3, [r2, #48] ; 0x30
8003262: 4b43 ldr r3, [pc, #268] ; (8003370 <BSP_SDRAM_MspInit+0x1cc>)
8003264: 6b1b ldr r3, [r3, #48] ; 0x30
8003266: f003 0380 and.w r3, r3, #128 ; 0x80
800326a: 60fb str r3, [r7, #12]
800326c: 68fb ldr r3, [r7, #12]
/* Common GPIO configuration */
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
800326e: 2302 movs r3, #2
8003270: 633b str r3, [r7, #48] ; 0x30
gpio_init_structure.Pull = GPIO_PULLUP;
8003272: 2301 movs r3, #1
8003274: 637b str r3, [r7, #52] ; 0x34
gpio_init_structure.Speed = GPIO_SPEED_FAST;
8003276: 2302 movs r3, #2
8003278: 63bb str r3, [r7, #56] ; 0x38
gpio_init_structure.Alternate = GPIO_AF12_FMC;
800327a: 230c movs r3, #12
800327c: 63fb str r3, [r7, #60] ; 0x3c
/* GPIOC configuration */
gpio_init_structure.Pin = GPIO_PIN_3;
800327e: 2308 movs r3, #8
8003280: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
8003282: f107 032c add.w r3, r7, #44 ; 0x2c
8003286: 4619 mov r1, r3
8003288: 483a ldr r0, [pc, #232] ; (8003374 <BSP_SDRAM_MspInit+0x1d0>)
800328a: f002 fb31 bl 80058f0 <HAL_GPIO_Init>
/* GPIOD configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
800328e: f24c 7303 movw r3, #50947 ; 0xc703
8003292: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
8003294: f107 032c add.w r3, r7, #44 ; 0x2c
8003298: 4619 mov r1, r3
800329a: 4837 ldr r0, [pc, #220] ; (8003378 <BSP_SDRAM_MspInit+0x1d4>)
800329c: f002 fb28 bl 80058f0 <HAL_GPIO_Init>
/* GPIOE configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
80032a0: f64f 7383 movw r3, #65411 ; 0xff83
80032a4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
80032a6: f107 032c add.w r3, r7, #44 ; 0x2c
80032aa: 4619 mov r1, r3
80032ac: 4833 ldr r0, [pc, #204] ; (800337c <BSP_SDRAM_MspInit+0x1d8>)
80032ae: f002 fb1f bl 80058f0 <HAL_GPIO_Init>
/* GPIOF configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
80032b2: f64f 033f movw r3, #63551 ; 0xf83f
80032b6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
80032b8: f107 032c add.w r3, r7, #44 ; 0x2c
80032bc: 4619 mov r1, r3
80032be: 4830 ldr r0, [pc, #192] ; (8003380 <BSP_SDRAM_MspInit+0x1dc>)
80032c0: f002 fb16 bl 80058f0 <HAL_GPIO_Init>
/* GPIOG configuration */
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
80032c4: f248 1333 movw r3, #33075 ; 0x8133
80032c8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
80032ca: f107 032c add.w r3, r7, #44 ; 0x2c
80032ce: 4619 mov r1, r3
80032d0: 482c ldr r0, [pc, #176] ; (8003384 <BSP_SDRAM_MspInit+0x1e0>)
80032d2: f002 fb0d bl 80058f0 <HAL_GPIO_Init>
/* GPIOH configuration */
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
80032d6: 2328 movs r3, #40 ; 0x28
80032d8: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
80032da: f107 032c add.w r3, r7, #44 ; 0x2c
80032de: 4619 mov r1, r3
80032e0: 4829 ldr r0, [pc, #164] ; (8003388 <BSP_SDRAM_MspInit+0x1e4>)
80032e2: f002 fb05 bl 80058f0 <HAL_GPIO_Init>
/* Configure common DMA parameters */
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
80032e6: 4b29 ldr r3, [pc, #164] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
80032e8: 2200 movs r2, #0
80032ea: 605a str r2, [r3, #4]
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
80032ec: 4b27 ldr r3, [pc, #156] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
80032ee: 2280 movs r2, #128 ; 0x80
80032f0: 609a str r2, [r3, #8]
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
80032f2: 4b26 ldr r3, [pc, #152] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
80032f4: f44f 7200 mov.w r2, #512 ; 0x200
80032f8: 60da str r2, [r3, #12]
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
80032fa: 4b24 ldr r3, [pc, #144] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
80032fc: f44f 6280 mov.w r2, #1024 ; 0x400
8003300: 611a str r2, [r3, #16]
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
8003302: 4b22 ldr r3, [pc, #136] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003304: f44f 5280 mov.w r2, #4096 ; 0x1000
8003308: 615a str r2, [r3, #20]
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
800330a: 4b20 ldr r3, [pc, #128] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
800330c: f44f 4280 mov.w r2, #16384 ; 0x4000
8003310: 619a str r2, [r3, #24]
dma_handle.Init.Mode = DMA_NORMAL;
8003312: 4b1e ldr r3, [pc, #120] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003314: 2200 movs r2, #0
8003316: 61da str r2, [r3, #28]
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
8003318: 4b1c ldr r3, [pc, #112] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
800331a: f44f 3200 mov.w r2, #131072 ; 0x20000
800331e: 621a str r2, [r3, #32]
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
8003320: 4b1a ldr r3, [pc, #104] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003322: 2200 movs r2, #0
8003324: 625a str r2, [r3, #36] ; 0x24
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
8003326: 4b19 ldr r3, [pc, #100] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003328: 2203 movs r2, #3
800332a: 629a str r2, [r3, #40] ; 0x28
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
800332c: 4b17 ldr r3, [pc, #92] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
800332e: 2200 movs r2, #0
8003330: 62da str r2, [r3, #44] ; 0x2c
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
8003332: 4b16 ldr r3, [pc, #88] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003334: 2200 movs r2, #0
8003336: 631a str r2, [r3, #48] ; 0x30
dma_handle.Instance = SDRAM_DMAx_STREAM;
8003338: 4b14 ldr r3, [pc, #80] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
800333a: 4a15 ldr r2, [pc, #84] ; (8003390 <BSP_SDRAM_MspInit+0x1ec>)
800333c: 601a str r2, [r3, #0]
/* Associate the DMA handle */
__HAL_LINKDMA(hsdram, hdma, dma_handle);
800333e: 687b ldr r3, [r7, #4]
8003340: 4a12 ldr r2, [pc, #72] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003342: 631a str r2, [r3, #48] ; 0x30
8003344: 4a11 ldr r2, [pc, #68] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003346: 687b ldr r3, [r7, #4]
8003348: 6393 str r3, [r2, #56] ; 0x38
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dma_handle);
800334a: 4810 ldr r0, [pc, #64] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
800334c: f001 ff36 bl 80051bc <HAL_DMA_DeInit>
/* Configure the DMA stream */
HAL_DMA_Init(&dma_handle);
8003350: 480e ldr r0, [pc, #56] ; (800338c <BSP_SDRAM_MspInit+0x1e8>)
8003352: f001 fe85 bl 8005060 <HAL_DMA_Init>
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0x0F, 0);
8003356: 2200 movs r2, #0
8003358: 210f movs r1, #15
800335a: 2038 movs r0, #56 ; 0x38
800335c: f001 fd88 bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
8003360: 2038 movs r0, #56 ; 0x38
8003362: f001 fda1 bl 8004ea8 <HAL_NVIC_EnableIRQ>
}
8003366: bf00 nop
8003368: 3740 adds r7, #64 ; 0x40
800336a: 46bd mov sp, r7
800336c: bd80 pop {r7, pc}
800336e: bf00 nop
8003370: 40023800 .word 0x40023800
8003374: 40020800 .word 0x40020800
8003378: 40020c00 .word 0x40020c00
800337c: 40021000 .word 0x40021000
8003380: 40021400 .word 0x40021400
8003384: 40021800 .word 0x40021800
8003388: 40021c00 .word 0x40021c00
800338c: 20000258 .word 0x20000258
8003390: 40026410 .word 0x40026410
08003394 <BSP_TS_Init>:
* @param ts_SizeX: Maximum X size of the TS area on LCD
* @param ts_SizeY: Maximum Y size of the TS area on LCD
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Init(uint16_t ts_SizeX, uint16_t ts_SizeY)
{
8003394: b580 push {r7, lr}
8003396: b084 sub sp, #16
8003398: af00 add r7, sp, #0
800339a: 4603 mov r3, r0
800339c: 460a mov r2, r1
800339e: 80fb strh r3, [r7, #6]
80033a0: 4613 mov r3, r2
80033a2: 80bb strh r3, [r7, #4]
uint8_t status = TS_OK;
80033a4: 2300 movs r3, #0
80033a6: 73fb strb r3, [r7, #15]
tsXBoundary = ts_SizeX;
80033a8: 4a14 ldr r2, [pc, #80] ; (80033fc <BSP_TS_Init+0x68>)
80033aa: 88fb ldrh r3, [r7, #6]
80033ac: 8013 strh r3, [r2, #0]
tsYBoundary = ts_SizeY;
80033ae: 4a14 ldr r2, [pc, #80] ; (8003400 <BSP_TS_Init+0x6c>)
80033b0: 88bb ldrh r3, [r7, #4]
80033b2: 8013 strh r3, [r2, #0]
/* Read ID and verify if the touch screen driver is ready */
ft5336_ts_drv.Init(TS_I2C_ADDRESS);
80033b4: 4b13 ldr r3, [pc, #76] ; (8003404 <BSP_TS_Init+0x70>)
80033b6: 681b ldr r3, [r3, #0]
80033b8: 2070 movs r0, #112 ; 0x70
80033ba: 4798 blx r3
if(ft5336_ts_drv.ReadID(TS_I2C_ADDRESS) == FT5336_ID_VALUE)
80033bc: 4b11 ldr r3, [pc, #68] ; (8003404 <BSP_TS_Init+0x70>)
80033be: 685b ldr r3, [r3, #4]
80033c0: 2070 movs r0, #112 ; 0x70
80033c2: 4798 blx r3
80033c4: 4603 mov r3, r0
80033c6: 2b51 cmp r3, #81 ; 0x51
80033c8: d111 bne.n 80033ee <BSP_TS_Init+0x5a>
{
/* Initialize the TS driver structure */
tsDriver = &ft5336_ts_drv;
80033ca: 4b0f ldr r3, [pc, #60] ; (8003408 <BSP_TS_Init+0x74>)
80033cc: 4a0d ldr r2, [pc, #52] ; (8003404 <BSP_TS_Init+0x70>)
80033ce: 601a str r2, [r3, #0]
I2cAddress = TS_I2C_ADDRESS;
80033d0: 4b0e ldr r3, [pc, #56] ; (800340c <BSP_TS_Init+0x78>)
80033d2: 2270 movs r2, #112 ; 0x70
80033d4: 701a strb r2, [r3, #0]
tsOrientation = TS_SWAP_XY;
80033d6: 4b0e ldr r3, [pc, #56] ; (8003410 <BSP_TS_Init+0x7c>)
80033d8: 2208 movs r2, #8
80033da: 701a strb r2, [r3, #0]
/* Initialize the TS driver */
tsDriver->Start(I2cAddress);
80033dc: 4b0a ldr r3, [pc, #40] ; (8003408 <BSP_TS_Init+0x74>)
80033de: 681b ldr r3, [r3, #0]
80033e0: 68db ldr r3, [r3, #12]
80033e2: 4a0a ldr r2, [pc, #40] ; (800340c <BSP_TS_Init+0x78>)
80033e4: 7812 ldrb r2, [r2, #0]
80033e6: b292 uxth r2, r2
80033e8: 4610 mov r0, r2
80033ea: 4798 blx r3
80033ec: e001 b.n 80033f2 <BSP_TS_Init+0x5e>
}
else
{
status = TS_DEVICE_NOT_FOUND;
80033ee: 2303 movs r3, #3
80033f0: 73fb strb r3, [r7, #15]
}
return status;
80033f2: 7bfb ldrb r3, [r7, #15]
}
80033f4: 4618 mov r0, r3
80033f6: 3710 adds r7, #16
80033f8: 46bd mov sp, r7
80033fa: bd80 pop {r7, pc}
80033fc: 200002bc .word 0x200002bc
8003400: 200002be .word 0x200002be
8003404: 20000000 .word 0x20000000
8003408: 200002b8 .word 0x200002b8
800340c: 200002c1 .word 0x200002c1
8003410: 200002c0 .word 0x200002c0
08003414 <BSP_TS_GetState>:
* @brief Returns status and positions of the touch screen.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_GetState(TS_StateTypeDef *TS_State)
{
8003414: b590 push {r4, r7, lr}
8003416: b097 sub sp, #92 ; 0x5c
8003418: af02 add r7, sp, #8
800341a: 6078 str r0, [r7, #4]
static uint32_t _x[TS_MAX_NB_TOUCH] = {0, 0};
static uint32_t _y[TS_MAX_NB_TOUCH] = {0, 0};
uint8_t ts_status = TS_OK;
800341c: 2300 movs r3, #0
800341e: f887 304f strb.w r3, [r7, #79] ; 0x4f
uint16_t brute_y[TS_MAX_NB_TOUCH];
uint16_t x_diff;
uint16_t y_diff;
uint32_t index;
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
uint32_t weight = 0;
8003422: 2300 movs r3, #0
8003424: 613b str r3, [r7, #16]
uint32_t area = 0;
8003426: 2300 movs r3, #0
8003428: 60fb str r3, [r7, #12]
uint32_t event = 0;
800342a: 2300 movs r3, #0
800342c: 60bb str r3, [r7, #8]
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
/* Check and update the number of touches active detected */
TS_State->touchDetected = tsDriver->DetectTouch(I2cAddress);
800342e: 4b97 ldr r3, [pc, #604] ; (800368c <BSP_TS_GetState+0x278>)
8003430: 681b ldr r3, [r3, #0]
8003432: 691b ldr r3, [r3, #16]
8003434: 4a96 ldr r2, [pc, #600] ; (8003690 <BSP_TS_GetState+0x27c>)
8003436: 7812 ldrb r2, [r2, #0]
8003438: b292 uxth r2, r2
800343a: 4610 mov r0, r2
800343c: 4798 blx r3
800343e: 4603 mov r3, r0
8003440: 461a mov r2, r3
8003442: 687b ldr r3, [r7, #4]
8003444: 701a strb r2, [r3, #0]
if(TS_State->touchDetected)
8003446: 687b ldr r3, [r7, #4]
8003448: 781b ldrb r3, [r3, #0]
800344a: 2b00 cmp r3, #0
800344c: f000 81a8 beq.w 80037a0 <BSP_TS_GetState+0x38c>
{
for(index=0; index < TS_State->touchDetected; index++)
8003450: 2300 movs r3, #0
8003452: 64bb str r3, [r7, #72] ; 0x48
8003454: e197 b.n 8003786 <BSP_TS_GetState+0x372>
{
/* Get each touch coordinates */
tsDriver->GetXY(I2cAddress, &(brute_x[index]), &(brute_y[index]));
8003456: 4b8d ldr r3, [pc, #564] ; (800368c <BSP_TS_GetState+0x278>)
8003458: 681b ldr r3, [r3, #0]
800345a: 695b ldr r3, [r3, #20]
800345c: 4a8c ldr r2, [pc, #560] ; (8003690 <BSP_TS_GetState+0x27c>)
800345e: 7812 ldrb r2, [r2, #0]
8003460: b290 uxth r0, r2
8003462: f107 0120 add.w r1, r7, #32
8003466: 6cba ldr r2, [r7, #72] ; 0x48
8003468: 0052 lsls r2, r2, #1
800346a: 188c adds r4, r1, r2
800346c: f107 0114 add.w r1, r7, #20
8003470: 6cba ldr r2, [r7, #72] ; 0x48
8003472: 0052 lsls r2, r2, #1
8003474: 440a add r2, r1
8003476: 4621 mov r1, r4
8003478: 4798 blx r3
if(tsOrientation == TS_SWAP_NONE)
800347a: 4b86 ldr r3, [pc, #536] ; (8003694 <BSP_TS_GetState+0x280>)
800347c: 781b ldrb r3, [r3, #0]
800347e: 2b01 cmp r3, #1
8003480: d11b bne.n 80034ba <BSP_TS_GetState+0xa6>
{
x[index] = brute_x[index];
8003482: 6cbb ldr r3, [r7, #72] ; 0x48
8003484: 005b lsls r3, r3, #1
8003486: f107 0250 add.w r2, r7, #80 ; 0x50
800348a: 4413 add r3, r2
800348c: f833 2c30 ldrh.w r2, [r3, #-48]
8003490: 6cbb ldr r3, [r7, #72] ; 0x48
8003492: 005b lsls r3, r3, #1
8003494: f107 0150 add.w r1, r7, #80 ; 0x50
8003498: 440b add r3, r1
800349a: f823 2c18 strh.w r2, [r3, #-24]
y[index] = brute_y[index];
800349e: 6cbb ldr r3, [r7, #72] ; 0x48
80034a0: 005b lsls r3, r3, #1
80034a2: f107 0250 add.w r2, r7, #80 ; 0x50
80034a6: 4413 add r3, r2
80034a8: f833 2c3c ldrh.w r2, [r3, #-60]
80034ac: 6cbb ldr r3, [r7, #72] ; 0x48
80034ae: 005b lsls r3, r3, #1
80034b0: f107 0150 add.w r1, r7, #80 ; 0x50
80034b4: 440b add r3, r1
80034b6: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_X)
80034ba: 4b76 ldr r3, [pc, #472] ; (8003694 <BSP_TS_GetState+0x280>)
80034bc: 781b ldrb r3, [r3, #0]
80034be: f003 0302 and.w r3, r3, #2
80034c2: 2b00 cmp r3, #0
80034c4: d010 beq.n 80034e8 <BSP_TS_GetState+0xd4>
{
x[index] = 4096 - brute_x[index];
80034c6: 6cbb ldr r3, [r7, #72] ; 0x48
80034c8: 005b lsls r3, r3, #1
80034ca: f107 0250 add.w r2, r7, #80 ; 0x50
80034ce: 4413 add r3, r2
80034d0: f833 3c30 ldrh.w r3, [r3, #-48]
80034d4: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
80034d8: b29a uxth r2, r3
80034da: 6cbb ldr r3, [r7, #72] ; 0x48
80034dc: 005b lsls r3, r3, #1
80034de: f107 0150 add.w r1, r7, #80 ; 0x50
80034e2: 440b add r3, r1
80034e4: f823 2c18 strh.w r2, [r3, #-24]
}
if(tsOrientation & TS_SWAP_Y)
80034e8: 4b6a ldr r3, [pc, #424] ; (8003694 <BSP_TS_GetState+0x280>)
80034ea: 781b ldrb r3, [r3, #0]
80034ec: f003 0304 and.w r3, r3, #4
80034f0: 2b00 cmp r3, #0
80034f2: d010 beq.n 8003516 <BSP_TS_GetState+0x102>
{
y[index] = 4096 - brute_y[index];
80034f4: 6cbb ldr r3, [r7, #72] ; 0x48
80034f6: 005b lsls r3, r3, #1
80034f8: f107 0250 add.w r2, r7, #80 ; 0x50
80034fc: 4413 add r3, r2
80034fe: f833 3c3c ldrh.w r3, [r3, #-60]
8003502: f5c3 5380 rsb r3, r3, #4096 ; 0x1000
8003506: b29a uxth r2, r3
8003508: 6cbb ldr r3, [r7, #72] ; 0x48
800350a: 005b lsls r3, r3, #1
800350c: f107 0150 add.w r1, r7, #80 ; 0x50
8003510: 440b add r3, r1
8003512: f823 2c24 strh.w r2, [r3, #-36]
}
if(tsOrientation & TS_SWAP_XY)
8003516: 4b5f ldr r3, [pc, #380] ; (8003694 <BSP_TS_GetState+0x280>)
8003518: 781b ldrb r3, [r3, #0]
800351a: f003 0308 and.w r3, r3, #8
800351e: 2b00 cmp r3, #0
8003520: d01b beq.n 800355a <BSP_TS_GetState+0x146>
{
y[index] = brute_x[index];
8003522: 6cbb ldr r3, [r7, #72] ; 0x48
8003524: 005b lsls r3, r3, #1
8003526: f107 0250 add.w r2, r7, #80 ; 0x50
800352a: 4413 add r3, r2
800352c: f833 2c30 ldrh.w r2, [r3, #-48]
8003530: 6cbb ldr r3, [r7, #72] ; 0x48
8003532: 005b lsls r3, r3, #1
8003534: f107 0150 add.w r1, r7, #80 ; 0x50
8003538: 440b add r3, r1
800353a: f823 2c24 strh.w r2, [r3, #-36]
x[index] = brute_y[index];
800353e: 6cbb ldr r3, [r7, #72] ; 0x48
8003540: 005b lsls r3, r3, #1
8003542: f107 0250 add.w r2, r7, #80 ; 0x50
8003546: 4413 add r3, r2
8003548: f833 2c3c ldrh.w r2, [r3, #-60]
800354c: 6cbb ldr r3, [r7, #72] ; 0x48
800354e: 005b lsls r3, r3, #1
8003550: f107 0150 add.w r1, r7, #80 ; 0x50
8003554: 440b add r3, r1
8003556: f823 2c18 strh.w r2, [r3, #-24]
}
x_diff = x[index] > _x[index]? (x[index] - _x[index]): (_x[index] - x[index]);
800355a: 6cbb ldr r3, [r7, #72] ; 0x48
800355c: 005b lsls r3, r3, #1
800355e: f107 0250 add.w r2, r7, #80 ; 0x50
8003562: 4413 add r3, r2
8003564: f833 3c18 ldrh.w r3, [r3, #-24]
8003568: 4619 mov r1, r3
800356a: 4a4b ldr r2, [pc, #300] ; (8003698 <BSP_TS_GetState+0x284>)
800356c: 6cbb ldr r3, [r7, #72] ; 0x48
800356e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003572: 4299 cmp r1, r3
8003574: d90e bls.n 8003594 <BSP_TS_GetState+0x180>
8003576: 6cbb ldr r3, [r7, #72] ; 0x48
8003578: 005b lsls r3, r3, #1
800357a: f107 0250 add.w r2, r7, #80 ; 0x50
800357e: 4413 add r3, r2
8003580: f833 2c18 ldrh.w r2, [r3, #-24]
8003584: 4944 ldr r1, [pc, #272] ; (8003698 <BSP_TS_GetState+0x284>)
8003586: 6cbb ldr r3, [r7, #72] ; 0x48
8003588: f851 3023 ldr.w r3, [r1, r3, lsl #2]
800358c: b29b uxth r3, r3
800358e: 1ad3 subs r3, r2, r3
8003590: b29b uxth r3, r3
8003592: e00d b.n 80035b0 <BSP_TS_GetState+0x19c>
8003594: 4a40 ldr r2, [pc, #256] ; (8003698 <BSP_TS_GetState+0x284>)
8003596: 6cbb ldr r3, [r7, #72] ; 0x48
8003598: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800359c: b29a uxth r2, r3
800359e: 6cbb ldr r3, [r7, #72] ; 0x48
80035a0: 005b lsls r3, r3, #1
80035a2: f107 0150 add.w r1, r7, #80 ; 0x50
80035a6: 440b add r3, r1
80035a8: f833 3c18 ldrh.w r3, [r3, #-24]
80035ac: 1ad3 subs r3, r2, r3
80035ae: b29b uxth r3, r3
80035b0: f8a7 3046 strh.w r3, [r7, #70] ; 0x46
y_diff = y[index] > _y[index]? (y[index] - _y[index]): (_y[index] - y[index]);
80035b4: 6cbb ldr r3, [r7, #72] ; 0x48
80035b6: 005b lsls r3, r3, #1
80035b8: f107 0250 add.w r2, r7, #80 ; 0x50
80035bc: 4413 add r3, r2
80035be: f833 3c24 ldrh.w r3, [r3, #-36]
80035c2: 4619 mov r1, r3
80035c4: 4a35 ldr r2, [pc, #212] ; (800369c <BSP_TS_GetState+0x288>)
80035c6: 6cbb ldr r3, [r7, #72] ; 0x48
80035c8: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80035cc: 4299 cmp r1, r3
80035ce: d90e bls.n 80035ee <BSP_TS_GetState+0x1da>
80035d0: 6cbb ldr r3, [r7, #72] ; 0x48
80035d2: 005b lsls r3, r3, #1
80035d4: f107 0250 add.w r2, r7, #80 ; 0x50
80035d8: 4413 add r3, r2
80035da: f833 2c24 ldrh.w r2, [r3, #-36]
80035de: 492f ldr r1, [pc, #188] ; (800369c <BSP_TS_GetState+0x288>)
80035e0: 6cbb ldr r3, [r7, #72] ; 0x48
80035e2: f851 3023 ldr.w r3, [r1, r3, lsl #2]
80035e6: b29b uxth r3, r3
80035e8: 1ad3 subs r3, r2, r3
80035ea: b29b uxth r3, r3
80035ec: e00d b.n 800360a <BSP_TS_GetState+0x1f6>
80035ee: 4a2b ldr r2, [pc, #172] ; (800369c <BSP_TS_GetState+0x288>)
80035f0: 6cbb ldr r3, [r7, #72] ; 0x48
80035f2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80035f6: b29a uxth r2, r3
80035f8: 6cbb ldr r3, [r7, #72] ; 0x48
80035fa: 005b lsls r3, r3, #1
80035fc: f107 0150 add.w r1, r7, #80 ; 0x50
8003600: 440b add r3, r1
8003602: f833 3c24 ldrh.w r3, [r3, #-36]
8003606: 1ad3 subs r3, r2, r3
8003608: b29b uxth r3, r3
800360a: f8a7 3044 strh.w r3, [r7, #68] ; 0x44
if ((x_diff + y_diff) > 5)
800360e: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46
8003612: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44
8003616: 4413 add r3, r2
8003618: 2b05 cmp r3, #5
800361a: dd17 ble.n 800364c <BSP_TS_GetState+0x238>
{
_x[index] = x[index];
800361c: 6cbb ldr r3, [r7, #72] ; 0x48
800361e: 005b lsls r3, r3, #1
8003620: f107 0250 add.w r2, r7, #80 ; 0x50
8003624: 4413 add r3, r2
8003626: f833 3c18 ldrh.w r3, [r3, #-24]
800362a: 4619 mov r1, r3
800362c: 4a1a ldr r2, [pc, #104] ; (8003698 <BSP_TS_GetState+0x284>)
800362e: 6cbb ldr r3, [r7, #72] ; 0x48
8003630: f842 1023 str.w r1, [r2, r3, lsl #2]
_y[index] = y[index];
8003634: 6cbb ldr r3, [r7, #72] ; 0x48
8003636: 005b lsls r3, r3, #1
8003638: f107 0250 add.w r2, r7, #80 ; 0x50
800363c: 4413 add r3, r2
800363e: f833 3c24 ldrh.w r3, [r3, #-36]
8003642: 4619 mov r1, r3
8003644: 4a15 ldr r2, [pc, #84] ; (800369c <BSP_TS_GetState+0x288>)
8003646: 6cbb ldr r3, [r7, #72] ; 0x48
8003648: f842 1023 str.w r1, [r2, r3, lsl #2]
}
if(I2cAddress == FT5336_I2C_SLAVE_ADDRESS)
800364c: 4b10 ldr r3, [pc, #64] ; (8003690 <BSP_TS_GetState+0x27c>)
800364e: 781b ldrb r3, [r3, #0]
8003650: 2b70 cmp r3, #112 ; 0x70
8003652: d125 bne.n 80036a0 <BSP_TS_GetState+0x28c>
{
TS_State->touchX[index] = x[index];
8003654: 6cbb ldr r3, [r7, #72] ; 0x48
8003656: 005b lsls r3, r3, #1
8003658: f107 0250 add.w r2, r7, #80 ; 0x50
800365c: 4413 add r3, r2
800365e: f833 1c18 ldrh.w r1, [r3, #-24]
8003662: 687a ldr r2, [r7, #4]
8003664: 6cbb ldr r3, [r7, #72] ; 0x48
8003666: 005b lsls r3, r3, #1
8003668: 4413 add r3, r2
800366a: 460a mov r2, r1
800366c: 805a strh r2, [r3, #2]
TS_State->touchY[index] = y[index];
800366e: 6cbb ldr r3, [r7, #72] ; 0x48
8003670: 005b lsls r3, r3, #1
8003672: f107 0250 add.w r2, r7, #80 ; 0x50
8003676: 4413 add r3, r2
8003678: f833 1c24 ldrh.w r1, [r3, #-36]
800367c: 687a ldr r2, [r7, #4]
800367e: 6cbb ldr r3, [r7, #72] ; 0x48
8003680: 3304 adds r3, #4
8003682: 005b lsls r3, r3, #1
8003684: 4413 add r3, r2
8003686: 460a mov r2, r1
8003688: 809a strh r2, [r3, #4]
800368a: e02c b.n 80036e6 <BSP_TS_GetState+0x2d2>
800368c: 200002b8 .word 0x200002b8
8003690: 200002c1 .word 0x200002c1
8003694: 200002c0 .word 0x200002c0
8003698: 200002c4 .word 0x200002c4
800369c: 200002d8 .word 0x200002d8
}
else
{
/* 2^12 = 4096 : indexes are expressed on a dynamic of 4096 */
TS_State->touchX[index] = (tsXBoundary * _x[index]) >> 12;
80036a0: 4b42 ldr r3, [pc, #264] ; (80037ac <BSP_TS_GetState+0x398>)
80036a2: 881b ldrh r3, [r3, #0]
80036a4: 4619 mov r1, r3
80036a6: 4a42 ldr r2, [pc, #264] ; (80037b0 <BSP_TS_GetState+0x39c>)
80036a8: 6cbb ldr r3, [r7, #72] ; 0x48
80036aa: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80036ae: fb03 f301 mul.w r3, r3, r1
80036b2: 0b1b lsrs r3, r3, #12
80036b4: b299 uxth r1, r3
80036b6: 687a ldr r2, [r7, #4]
80036b8: 6cbb ldr r3, [r7, #72] ; 0x48
80036ba: 005b lsls r3, r3, #1
80036bc: 4413 add r3, r2
80036be: 460a mov r2, r1
80036c0: 805a strh r2, [r3, #2]
TS_State->touchY[index] = (tsYBoundary * _y[index]) >> 12;
80036c2: 4b3c ldr r3, [pc, #240] ; (80037b4 <BSP_TS_GetState+0x3a0>)
80036c4: 881b ldrh r3, [r3, #0]
80036c6: 4619 mov r1, r3
80036c8: 4a3b ldr r2, [pc, #236] ; (80037b8 <BSP_TS_GetState+0x3a4>)
80036ca: 6cbb ldr r3, [r7, #72] ; 0x48
80036cc: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80036d0: fb03 f301 mul.w r3, r3, r1
80036d4: 0b1b lsrs r3, r3, #12
80036d6: b299 uxth r1, r3
80036d8: 687a ldr r2, [r7, #4]
80036da: 6cbb ldr r3, [r7, #72] ; 0x48
80036dc: 3304 adds r3, #4
80036de: 005b lsls r3, r3, #1
80036e0: 4413 add r3, r2
80036e2: 460a mov r2, r1
80036e4: 809a strh r2, [r3, #4]
}
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get touch info related to the current touch */
ft5336_TS_GetTouchInfo(I2cAddress, index, &weight, &area, &event);
80036e6: 4b35 ldr r3, [pc, #212] ; (80037bc <BSP_TS_GetState+0x3a8>)
80036e8: 781b ldrb r3, [r3, #0]
80036ea: b298 uxth r0, r3
80036ec: f107 010c add.w r1, r7, #12
80036f0: f107 0210 add.w r2, r7, #16
80036f4: f107 0308 add.w r3, r7, #8
80036f8: 9300 str r3, [sp, #0]
80036fa: 460b mov r3, r1
80036fc: 6cb9 ldr r1, [r7, #72] ; 0x48
80036fe: f7fd f933 bl 8000968 <ft5336_TS_GetTouchInfo>
/* Update TS_State structure */
TS_State->touchWeight[index] = weight;
8003702: 693b ldr r3, [r7, #16]
8003704: b2d9 uxtb r1, r3
8003706: 687a ldr r2, [r7, #4]
8003708: 6cbb ldr r3, [r7, #72] ; 0x48
800370a: 4413 add r3, r2
800370c: 3316 adds r3, #22
800370e: 460a mov r2, r1
8003710: 701a strb r2, [r3, #0]
TS_State->touchArea[index] = area;
8003712: 68fb ldr r3, [r7, #12]
8003714: b2d9 uxtb r1, r3
8003716: 687a ldr r2, [r7, #4]
8003718: 6cbb ldr r3, [r7, #72] ; 0x48
800371a: 4413 add r3, r2
800371c: 3320 adds r3, #32
800371e: 460a mov r2, r1
8003720: 701a strb r2, [r3, #0]
/* Remap touch event */
switch(event)
8003722: 68bb ldr r3, [r7, #8]
8003724: 2b03 cmp r3, #3
8003726: d827 bhi.n 8003778 <BSP_TS_GetState+0x364>
8003728: a201 add r2, pc, #4 ; (adr r2, 8003730 <BSP_TS_GetState+0x31c>)
800372a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800372e: bf00 nop
8003730: 08003741 .word 0x08003741
8003734: 0800374f .word 0x0800374f
8003738: 0800375d .word 0x0800375d
800373c: 0800376b .word 0x0800376b
{
case FT5336_TOUCH_EVT_FLAG_PRESS_DOWN :
TS_State->touchEventId[index] = TOUCH_EVENT_PRESS_DOWN;
8003740: 687a ldr r2, [r7, #4]
8003742: 6cbb ldr r3, [r7, #72] ; 0x48
8003744: 4413 add r3, r2
8003746: 331b adds r3, #27
8003748: 2201 movs r2, #1
800374a: 701a strb r2, [r3, #0]
break;
800374c: e018 b.n 8003780 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_LIFT_UP :
TS_State->touchEventId[index] = TOUCH_EVENT_LIFT_UP;
800374e: 687a ldr r2, [r7, #4]
8003750: 6cbb ldr r3, [r7, #72] ; 0x48
8003752: 4413 add r3, r2
8003754: 331b adds r3, #27
8003756: 2202 movs r2, #2
8003758: 701a strb r2, [r3, #0]
break;
800375a: e011 b.n 8003780 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_CONTACT :
TS_State->touchEventId[index] = TOUCH_EVENT_CONTACT;
800375c: 687a ldr r2, [r7, #4]
800375e: 6cbb ldr r3, [r7, #72] ; 0x48
8003760: 4413 add r3, r2
8003762: 331b adds r3, #27
8003764: 2203 movs r2, #3
8003766: 701a strb r2, [r3, #0]
break;
8003768: e00a b.n 8003780 <BSP_TS_GetState+0x36c>
case FT5336_TOUCH_EVT_FLAG_NO_EVENT :
TS_State->touchEventId[index] = TOUCH_EVENT_NO_EVT;
800376a: 687a ldr r2, [r7, #4]
800376c: 6cbb ldr r3, [r7, #72] ; 0x48
800376e: 4413 add r3, r2
8003770: 331b adds r3, #27
8003772: 2200 movs r2, #0
8003774: 701a strb r2, [r3, #0]
break;
8003776: e003 b.n 8003780 <BSP_TS_GetState+0x36c>
default :
ts_status = TS_ERROR;
8003778: 2301 movs r3, #1
800377a: f887 304f strb.w r3, [r7, #79] ; 0x4f
break;
800377e: bf00 nop
for(index=0; index < TS_State->touchDetected; index++)
8003780: 6cbb ldr r3, [r7, #72] ; 0x48
8003782: 3301 adds r3, #1
8003784: 64bb str r3, [r7, #72] ; 0x48
8003786: 687b ldr r3, [r7, #4]
8003788: 781b ldrb r3, [r3, #0]
800378a: 461a mov r2, r3
800378c: 6cbb ldr r3, [r7, #72] ; 0x48
800378e: 4293 cmp r3, r2
8003790: f4ff ae61 bcc.w 8003456 <BSP_TS_GetState+0x42>
} /* of for(index=0; index < TS_State->touchDetected; index++) */
#if (TS_MULTI_TOUCH_SUPPORTED == 1)
/* Get gesture Id */
ts_status = BSP_TS_Get_GestureId(TS_State);
8003794: 6878 ldr r0, [r7, #4]
8003796: f000 f813 bl 80037c0 <BSP_TS_Get_GestureId>
800379a: 4603 mov r3, r0
800379c: f887 304f strb.w r3, [r7, #79] ; 0x4f
#endif /* TS_MULTI_TOUCH_SUPPORTED == 1 */
} /* end of if(TS_State->touchDetected != 0) */
return (ts_status);
80037a0: f897 304f ldrb.w r3, [r7, #79] ; 0x4f
}
80037a4: 4618 mov r0, r3
80037a6: 3754 adds r7, #84 ; 0x54
80037a8: 46bd mov sp, r7
80037aa: bd90 pop {r4, r7, pc}
80037ac: 200002bc .word 0x200002bc
80037b0: 200002c4 .word 0x200002c4
80037b4: 200002be .word 0x200002be
80037b8: 200002d8 .word 0x200002d8
80037bc: 200002c1 .word 0x200002c1
080037c0 <BSP_TS_Get_GestureId>:
* @brief Update gesture Id following a touch detected.
* @param TS_State: Pointer to touch screen current state structure
* @retval TS_OK if all initializations are OK. Other value if error.
*/
uint8_t BSP_TS_Get_GestureId(TS_StateTypeDef *TS_State)
{
80037c0: b580 push {r7, lr}
80037c2: b084 sub sp, #16
80037c4: af00 add r7, sp, #0
80037c6: 6078 str r0, [r7, #4]
uint32_t gestureId = 0;
80037c8: 2300 movs r3, #0
80037ca: 60bb str r3, [r7, #8]
uint8_t ts_status = TS_OK;
80037cc: 2300 movs r3, #0
80037ce: 73fb strb r3, [r7, #15]
/* Get gesture Id */
ft5336_TS_GetGestureID(I2cAddress, &gestureId);
80037d0: 4b1f ldr r3, [pc, #124] ; (8003850 <BSP_TS_Get_GestureId+0x90>)
80037d2: 781b ldrb r3, [r3, #0]
80037d4: b29b uxth r3, r3
80037d6: f107 0208 add.w r2, r7, #8
80037da: 4611 mov r1, r2
80037dc: 4618 mov r0, r3
80037de: f7fd f8aa bl 8000936 <ft5336_TS_GetGestureID>
/* Remap gesture Id to a TS_GestureIdTypeDef value */
switch(gestureId)
80037e2: 68bb ldr r3, [r7, #8]
80037e4: 2b18 cmp r3, #24
80037e6: d01b beq.n 8003820 <BSP_TS_Get_GestureId+0x60>
80037e8: 2b18 cmp r3, #24
80037ea: d806 bhi.n 80037fa <BSP_TS_Get_GestureId+0x3a>
80037ec: 2b10 cmp r3, #16
80037ee: d00f beq.n 8003810 <BSP_TS_Get_GestureId+0x50>
80037f0: 2b14 cmp r3, #20
80037f2: d011 beq.n 8003818 <BSP_TS_Get_GestureId+0x58>
80037f4: 2b00 cmp r3, #0
80037f6: d007 beq.n 8003808 <BSP_TS_Get_GestureId+0x48>
80037f8: e022 b.n 8003840 <BSP_TS_Get_GestureId+0x80>
80037fa: 2b40 cmp r3, #64 ; 0x40
80037fc: d018 beq.n 8003830 <BSP_TS_Get_GestureId+0x70>
80037fe: 2b49 cmp r3, #73 ; 0x49
8003800: d01a beq.n 8003838 <BSP_TS_Get_GestureId+0x78>
8003802: 2b1c cmp r3, #28
8003804: d010 beq.n 8003828 <BSP_TS_Get_GestureId+0x68>
8003806: e01b b.n 8003840 <BSP_TS_Get_GestureId+0x80>
{
case FT5336_GEST_ID_NO_GESTURE :
TS_State->gestureId = GEST_ID_NO_GESTURE;
8003808: 687b ldr r3, [r7, #4]
800380a: 2200 movs r2, #0
800380c: 629a str r2, [r3, #40] ; 0x28
break;
800380e: e01a b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_UP :
TS_State->gestureId = GEST_ID_MOVE_UP;
8003810: 687b ldr r3, [r7, #4]
8003812: 2201 movs r2, #1
8003814: 629a str r2, [r3, #40] ; 0x28
break;
8003816: e016 b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_RIGHT :
TS_State->gestureId = GEST_ID_MOVE_RIGHT;
8003818: 687b ldr r3, [r7, #4]
800381a: 2202 movs r2, #2
800381c: 629a str r2, [r3, #40] ; 0x28
break;
800381e: e012 b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_DOWN :
TS_State->gestureId = GEST_ID_MOVE_DOWN;
8003820: 687b ldr r3, [r7, #4]
8003822: 2203 movs r2, #3
8003824: 629a str r2, [r3, #40] ; 0x28
break;
8003826: e00e b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_MOVE_LEFT :
TS_State->gestureId = GEST_ID_MOVE_LEFT;
8003828: 687b ldr r3, [r7, #4]
800382a: 2204 movs r2, #4
800382c: 629a str r2, [r3, #40] ; 0x28
break;
800382e: e00a b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_IN :
TS_State->gestureId = GEST_ID_ZOOM_IN;
8003830: 687b ldr r3, [r7, #4]
8003832: 2205 movs r2, #5
8003834: 629a str r2, [r3, #40] ; 0x28
break;
8003836: e006 b.n 8003846 <BSP_TS_Get_GestureId+0x86>
case FT5336_GEST_ID_ZOOM_OUT :
TS_State->gestureId = GEST_ID_ZOOM_OUT;
8003838: 687b ldr r3, [r7, #4]
800383a: 2206 movs r2, #6
800383c: 629a str r2, [r3, #40] ; 0x28
break;
800383e: e002 b.n 8003846 <BSP_TS_Get_GestureId+0x86>
default :
ts_status = TS_ERROR;
8003840: 2301 movs r3, #1
8003842: 73fb strb r3, [r7, #15]
break;
8003844: bf00 nop
} /* of switch(gestureId) */
return(ts_status);
8003846: 7bfb ldrb r3, [r7, #15]
}
8003848: 4618 mov r0, r3
800384a: 3710 adds r7, #16
800384c: 46bd mov sp, r7
800384e: bd80 pop {r7, pc}
8003850: 200002c1 .word 0x200002c1
08003854 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8003854: b580 push {r7, lr}
8003856: b082 sub sp, #8
8003858: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_PWR_CLK_ENABLE();
800385a: 4b11 ldr r3, [pc, #68] ; (80038a0 <HAL_MspInit+0x4c>)
800385c: 6c1b ldr r3, [r3, #64] ; 0x40
800385e: 4a10 ldr r2, [pc, #64] ; (80038a0 <HAL_MspInit+0x4c>)
8003860: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003864: 6413 str r3, [r2, #64] ; 0x40
8003866: 4b0e ldr r3, [pc, #56] ; (80038a0 <HAL_MspInit+0x4c>)
8003868: 6c1b ldr r3, [r3, #64] ; 0x40
800386a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800386e: 607b str r3, [r7, #4]
8003870: 687b ldr r3, [r7, #4]
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003872: 4b0b ldr r3, [pc, #44] ; (80038a0 <HAL_MspInit+0x4c>)
8003874: 6c5b ldr r3, [r3, #68] ; 0x44
8003876: 4a0a ldr r2, [pc, #40] ; (80038a0 <HAL_MspInit+0x4c>)
8003878: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800387c: 6453 str r3, [r2, #68] ; 0x44
800387e: 4b08 ldr r3, [pc, #32] ; (80038a0 <HAL_MspInit+0x4c>)
8003880: 6c5b ldr r3, [r3, #68] ; 0x44
8003882: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003886: 603b str r3, [r7, #0]
8003888: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
800388a: 2200 movs r2, #0
800388c: 210f movs r1, #15
800388e: f06f 0001 mvn.w r0, #1
8003892: f001 faed bl 8004e70 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8003896: bf00 nop
8003898: 3708 adds r7, #8
800389a: 46bd mov sp, r7
800389c: bd80 pop {r7, pc}
800389e: bf00 nop
80038a0: 40023800 .word 0x40023800
080038a4 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
80038a4: b580 push {r7, lr}
80038a6: b08c sub sp, #48 ; 0x30
80038a8: af00 add r7, sp, #0
80038aa: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80038ac: f107 031c add.w r3, r7, #28
80038b0: 2200 movs r2, #0
80038b2: 601a str r2, [r3, #0]
80038b4: 605a str r2, [r3, #4]
80038b6: 609a str r2, [r3, #8]
80038b8: 60da str r2, [r3, #12]
80038ba: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
80038bc: 687b ldr r3, [r7, #4]
80038be: 681b ldr r3, [r3, #0]
80038c0: 4a2a ldr r2, [pc, #168] ; (800396c <HAL_ADC_MspInit+0xc8>)
80038c2: 4293 cmp r3, r2
80038c4: d124 bne.n 8003910 <HAL_ADC_MspInit+0x6c>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
80038c6: 4b2a ldr r3, [pc, #168] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038c8: 6c5b ldr r3, [r3, #68] ; 0x44
80038ca: 4a29 ldr r2, [pc, #164] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038cc: f443 7380 orr.w r3, r3, #256 ; 0x100
80038d0: 6453 str r3, [r2, #68] ; 0x44
80038d2: 4b27 ldr r3, [pc, #156] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038d4: 6c5b ldr r3, [r3, #68] ; 0x44
80038d6: f403 7380 and.w r3, r3, #256 ; 0x100
80038da: 61bb str r3, [r7, #24]
80038dc: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
80038de: 4b24 ldr r3, [pc, #144] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038e0: 6b1b ldr r3, [r3, #48] ; 0x30
80038e2: 4a23 ldr r2, [pc, #140] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038e4: f043 0301 orr.w r3, r3, #1
80038e8: 6313 str r3, [r2, #48] ; 0x30
80038ea: 4b21 ldr r3, [pc, #132] ; (8003970 <HAL_ADC_MspInit+0xcc>)
80038ec: 6b1b ldr r3, [r3, #48] ; 0x30
80038ee: f003 0301 and.w r3, r3, #1
80038f2: 617b str r3, [r7, #20]
80038f4: 697b ldr r3, [r7, #20]
/**ADC1 GPIO Configuration
PA0/WKUP ------> ADC1_IN0
*/
GPIO_InitStruct.Pin = GPIO_PIN_0;
80038f6: 2301 movs r3, #1
80038f8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80038fa: 2303 movs r3, #3
80038fc: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80038fe: 2300 movs r3, #0
8003900: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8003902: f107 031c add.w r3, r7, #28
8003906: 4619 mov r1, r3
8003908: 481a ldr r0, [pc, #104] ; (8003974 <HAL_ADC_MspInit+0xd0>)
800390a: f001 fff1 bl 80058f0 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
800390e: e029 b.n 8003964 <HAL_ADC_MspInit+0xc0>
else if(hadc->Instance==ADC3)
8003910: 687b ldr r3, [r7, #4]
8003912: 681b ldr r3, [r3, #0]
8003914: 4a18 ldr r2, [pc, #96] ; (8003978 <HAL_ADC_MspInit+0xd4>)
8003916: 4293 cmp r3, r2
8003918: d124 bne.n 8003964 <HAL_ADC_MspInit+0xc0>
__HAL_RCC_ADC3_CLK_ENABLE();
800391a: 4b15 ldr r3, [pc, #84] ; (8003970 <HAL_ADC_MspInit+0xcc>)
800391c: 6c5b ldr r3, [r3, #68] ; 0x44
800391e: 4a14 ldr r2, [pc, #80] ; (8003970 <HAL_ADC_MspInit+0xcc>)
8003920: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003924: 6453 str r3, [r2, #68] ; 0x44
8003926: 4b12 ldr r3, [pc, #72] ; (8003970 <HAL_ADC_MspInit+0xcc>)
8003928: 6c5b ldr r3, [r3, #68] ; 0x44
800392a: f403 6380 and.w r3, r3, #1024 ; 0x400
800392e: 613b str r3, [r7, #16]
8003930: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
8003932: 4b0f ldr r3, [pc, #60] ; (8003970 <HAL_ADC_MspInit+0xcc>)
8003934: 6b1b ldr r3, [r3, #48] ; 0x30
8003936: 4a0e ldr r2, [pc, #56] ; (8003970 <HAL_ADC_MspInit+0xcc>)
8003938: f043 0320 orr.w r3, r3, #32
800393c: 6313 str r3, [r2, #48] ; 0x30
800393e: 4b0c ldr r3, [pc, #48] ; (8003970 <HAL_ADC_MspInit+0xcc>)
8003940: 6b1b ldr r3, [r3, #48] ; 0x30
8003942: f003 0320 and.w r3, r3, #32
8003946: 60fb str r3, [r7, #12]
8003948: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
800394a: f44f 63e0 mov.w r3, #1792 ; 0x700
800394e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8003950: 2303 movs r3, #3
8003952: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003954: 2300 movs r3, #0
8003956: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8003958: f107 031c add.w r3, r7, #28
800395c: 4619 mov r1, r3
800395e: 4807 ldr r0, [pc, #28] ; (800397c <HAL_ADC_MspInit+0xd8>)
8003960: f001 ffc6 bl 80058f0 <HAL_GPIO_Init>
}
8003964: bf00 nop
8003966: 3730 adds r7, #48 ; 0x30
8003968: 46bd mov sp, r7
800396a: bd80 pop {r7, pc}
800396c: 40012000 .word 0x40012000
8003970: 40023800 .word 0x40023800
8003974: 40020000 .word 0x40020000
8003978: 40012200 .word 0x40012200
800397c: 40021400 .word 0x40021400
08003980 <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
8003980: b580 push {r7, lr}
8003982: b08a sub sp, #40 ; 0x28
8003984: af00 add r7, sp, #0
8003986: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003988: f107 0314 add.w r3, r7, #20
800398c: 2200 movs r2, #0
800398e: 601a str r2, [r3, #0]
8003990: 605a str r2, [r3, #4]
8003992: 609a str r2, [r3, #8]
8003994: 60da str r2, [r3, #12]
8003996: 611a str r2, [r3, #16]
if(hdac->Instance==DAC)
8003998: 687b ldr r3, [r7, #4]
800399a: 681b ldr r3, [r3, #0]
800399c: 4a19 ldr r2, [pc, #100] ; (8003a04 <HAL_DAC_MspInit+0x84>)
800399e: 4293 cmp r3, r2
80039a0: d12b bne.n 80039fa <HAL_DAC_MspInit+0x7a>
{
/* USER CODE BEGIN DAC_MspInit 0 */
/* USER CODE END DAC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC_CLK_ENABLE();
80039a2: 4b19 ldr r3, [pc, #100] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039a4: 6c1b ldr r3, [r3, #64] ; 0x40
80039a6: 4a18 ldr r2, [pc, #96] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039a8: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
80039ac: 6413 str r3, [r2, #64] ; 0x40
80039ae: 4b16 ldr r3, [pc, #88] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039b0: 6c1b ldr r3, [r3, #64] ; 0x40
80039b2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80039b6: 613b str r3, [r7, #16]
80039b8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80039ba: 4b13 ldr r3, [pc, #76] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039bc: 6b1b ldr r3, [r3, #48] ; 0x30
80039be: 4a12 ldr r2, [pc, #72] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039c0: f043 0301 orr.w r3, r3, #1
80039c4: 6313 str r3, [r2, #48] ; 0x30
80039c6: 4b10 ldr r3, [pc, #64] ; (8003a08 <HAL_DAC_MspInit+0x88>)
80039c8: 6b1b ldr r3, [r3, #48] ; 0x30
80039ca: f003 0301 and.w r3, r3, #1
80039ce: 60fb str r3, [r7, #12]
80039d0: 68fb ldr r3, [r7, #12]
/**DAC GPIO Configuration
PA4 ------> DAC_OUT1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
80039d2: 2310 movs r3, #16
80039d4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
80039d6: 2303 movs r3, #3
80039d8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80039da: 2300 movs r3, #0
80039dc: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80039de: f107 0314 add.w r3, r7, #20
80039e2: 4619 mov r1, r3
80039e4: 4809 ldr r0, [pc, #36] ; (8003a0c <HAL_DAC_MspInit+0x8c>)
80039e6: f001 ff83 bl 80058f0 <HAL_GPIO_Init>
/* DAC interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
80039ea: 2200 movs r2, #0
80039ec: 2100 movs r1, #0
80039ee: 2036 movs r0, #54 ; 0x36
80039f0: f001 fa3e bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
80039f4: 2036 movs r0, #54 ; 0x36
80039f6: f001 fa57 bl 8004ea8 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN DAC_MspInit 1 */
/* USER CODE END DAC_MspInit 1 */
}
}
80039fa: bf00 nop
80039fc: 3728 adds r7, #40 ; 0x28
80039fe: 46bd mov sp, r7
8003a00: bd80 pop {r7, pc}
8003a02: bf00 nop
8003a04: 40007400 .word 0x40007400
8003a08: 40023800 .word 0x40023800
8003a0c: 40020000 .word 0x40020000
08003a10 <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
8003a10: b480 push {r7}
8003a12: b085 sub sp, #20
8003a14: af00 add r7, sp, #0
8003a16: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
8003a18: 687b ldr r3, [r7, #4]
8003a1a: 681b ldr r3, [r3, #0]
8003a1c: 4a0a ldr r2, [pc, #40] ; (8003a48 <HAL_DMA2D_MspInit+0x38>)
8003a1e: 4293 cmp r3, r2
8003a20: d10b bne.n 8003a3a <HAL_DMA2D_MspInit+0x2a>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
8003a22: 4b0a ldr r3, [pc, #40] ; (8003a4c <HAL_DMA2D_MspInit+0x3c>)
8003a24: 6b1b ldr r3, [r3, #48] ; 0x30
8003a26: 4a09 ldr r2, [pc, #36] ; (8003a4c <HAL_DMA2D_MspInit+0x3c>)
8003a28: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8003a2c: 6313 str r3, [r2, #48] ; 0x30
8003a2e: 4b07 ldr r3, [pc, #28] ; (8003a4c <HAL_DMA2D_MspInit+0x3c>)
8003a30: 6b1b ldr r3, [r3, #48] ; 0x30
8003a32: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8003a36: 60fb str r3, [r7, #12]
8003a38: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
8003a3a: bf00 nop
8003a3c: 3714 adds r7, #20
8003a3e: 46bd mov sp, r7
8003a40: f85d 7b04 ldr.w r7, [sp], #4
8003a44: 4770 bx lr
8003a46: bf00 nop
8003a48: 4002b000 .word 0x4002b000
8003a4c: 40023800 .word 0x40023800
08003a50 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8003a50: b580 push {r7, lr}
8003a52: b08c sub sp, #48 ; 0x30
8003a54: af00 add r7, sp, #0
8003a56: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003a58: f107 031c add.w r3, r7, #28
8003a5c: 2200 movs r2, #0
8003a5e: 601a str r2, [r3, #0]
8003a60: 605a str r2, [r3, #4]
8003a62: 609a str r2, [r3, #8]
8003a64: 60da str r2, [r3, #12]
8003a66: 611a str r2, [r3, #16]
if(hi2c->Instance==I2C1)
8003a68: 687b ldr r3, [r7, #4]
8003a6a: 681b ldr r3, [r3, #0]
8003a6c: 4a2f ldr r2, [pc, #188] ; (8003b2c <HAL_I2C_MspInit+0xdc>)
8003a6e: 4293 cmp r3, r2
8003a70: d129 bne.n 8003ac6 <HAL_I2C_MspInit+0x76>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8003a72: 4b2f ldr r3, [pc, #188] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003a74: 6b1b ldr r3, [r3, #48] ; 0x30
8003a76: 4a2e ldr r2, [pc, #184] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003a78: f043 0302 orr.w r3, r3, #2
8003a7c: 6313 str r3, [r2, #48] ; 0x30
8003a7e: 4b2c ldr r3, [pc, #176] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003a80: 6b1b ldr r3, [r3, #48] ; 0x30
8003a82: f003 0302 and.w r3, r3, #2
8003a86: 61bb str r3, [r7, #24]
8003a88: 69bb ldr r3, [r7, #24]
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = ARDUINO_SCL_D15_Pin|ARDUINO_SDA_D14_Pin;
8003a8a: f44f 7340 mov.w r3, #768 ; 0x300
8003a8e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8003a90: 2312 movs r3, #18
8003a92: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8003a94: 2301 movs r3, #1
8003a96: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003a98: 2300 movs r3, #0
8003a9a: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8003a9c: 2304 movs r3, #4
8003a9e: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8003aa0: f107 031c add.w r3, r7, #28
8003aa4: 4619 mov r1, r3
8003aa6: 4823 ldr r0, [pc, #140] ; (8003b34 <HAL_I2C_MspInit+0xe4>)
8003aa8: f001 ff22 bl 80058f0 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8003aac: 4b20 ldr r3, [pc, #128] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003aae: 6c1b ldr r3, [r3, #64] ; 0x40
8003ab0: 4a1f ldr r2, [pc, #124] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003ab2: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8003ab6: 6413 str r3, [r2, #64] ; 0x40
8003ab8: 4b1d ldr r3, [pc, #116] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003aba: 6c1b ldr r3, [r3, #64] ; 0x40
8003abc: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8003ac0: 617b str r3, [r7, #20]
8003ac2: 697b ldr r3, [r7, #20]
/* USER CODE BEGIN I2C3_MspInit 1 */
/* USER CODE END I2C3_MspInit 1 */
}
}
8003ac4: e02d b.n 8003b22 <HAL_I2C_MspInit+0xd2>
else if(hi2c->Instance==I2C3)
8003ac6: 687b ldr r3, [r7, #4]
8003ac8: 681b ldr r3, [r3, #0]
8003aca: 4a1b ldr r2, [pc, #108] ; (8003b38 <HAL_I2C_MspInit+0xe8>)
8003acc: 4293 cmp r3, r2
8003ace: d128 bne.n 8003b22 <HAL_I2C_MspInit+0xd2>
__HAL_RCC_GPIOH_CLK_ENABLE();
8003ad0: 4b17 ldr r3, [pc, #92] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003ad2: 6b1b ldr r3, [r3, #48] ; 0x30
8003ad4: 4a16 ldr r2, [pc, #88] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003ad6: f043 0380 orr.w r3, r3, #128 ; 0x80
8003ada: 6313 str r3, [r2, #48] ; 0x30
8003adc: 4b14 ldr r3, [pc, #80] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003ade: 6b1b ldr r3, [r3, #48] ; 0x30
8003ae0: f003 0380 and.w r3, r3, #128 ; 0x80
8003ae4: 613b str r3, [r7, #16]
8003ae6: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = LCD_SCL_Pin|LCD_SDA_Pin;
8003ae8: f44f 73c0 mov.w r3, #384 ; 0x180
8003aec: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8003aee: 2312 movs r3, #18
8003af0: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8003af2: 2301 movs r3, #1
8003af4: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8003af6: 2303 movs r3, #3
8003af8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8003afa: 2304 movs r3, #4
8003afc: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8003afe: f107 031c add.w r3, r7, #28
8003b02: 4619 mov r1, r3
8003b04: 480d ldr r0, [pc, #52] ; (8003b3c <HAL_I2C_MspInit+0xec>)
8003b06: f001 fef3 bl 80058f0 <HAL_GPIO_Init>
__HAL_RCC_I2C3_CLK_ENABLE();
8003b0a: 4b09 ldr r3, [pc, #36] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003b0c: 6c1b ldr r3, [r3, #64] ; 0x40
8003b0e: 4a08 ldr r2, [pc, #32] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003b10: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8003b14: 6413 str r3, [r2, #64] ; 0x40
8003b16: 4b06 ldr r3, [pc, #24] ; (8003b30 <HAL_I2C_MspInit+0xe0>)
8003b18: 6c1b ldr r3, [r3, #64] ; 0x40
8003b1a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8003b1e: 60fb str r3, [r7, #12]
8003b20: 68fb ldr r3, [r7, #12]
}
8003b22: bf00 nop
8003b24: 3730 adds r7, #48 ; 0x30
8003b26: 46bd mov sp, r7
8003b28: bd80 pop {r7, pc}
8003b2a: bf00 nop
8003b2c: 40005400 .word 0x40005400
8003b30: 40023800 .word 0x40023800
8003b34: 40020400 .word 0x40020400
8003b38: 40005c00 .word 0x40005c00
8003b3c: 40021c00 .word 0x40021c00
08003b40 <HAL_I2C_MspDeInit>:
* This function freeze the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c)
{
8003b40: b580 push {r7, lr}
8003b42: b082 sub sp, #8
8003b44: af00 add r7, sp, #0
8003b46: 6078 str r0, [r7, #4]
if(hi2c->Instance==I2C1)
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 681b ldr r3, [r3, #0]
8003b4c: 4a15 ldr r2, [pc, #84] ; (8003ba4 <HAL_I2C_MspDeInit+0x64>)
8003b4e: 4293 cmp r3, r2
8003b50: d110 bne.n 8003b74 <HAL_I2C_MspDeInit+0x34>
{
/* USER CODE BEGIN I2C1_MspDeInit 0 */
/* USER CODE END I2C1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_I2C1_CLK_DISABLE();
8003b52: 4b15 ldr r3, [pc, #84] ; (8003ba8 <HAL_I2C_MspDeInit+0x68>)
8003b54: 6c1b ldr r3, [r3, #64] ; 0x40
8003b56: 4a14 ldr r2, [pc, #80] ; (8003ba8 <HAL_I2C_MspDeInit+0x68>)
8003b58: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
8003b5c: 6413 str r3, [r2, #64] ; 0x40
/**I2C1 GPIO Configuration
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
HAL_GPIO_DeInit(ARDUINO_SCL_D15_GPIO_Port, ARDUINO_SCL_D15_Pin);
8003b5e: f44f 7180 mov.w r1, #256 ; 0x100
8003b62: 4812 ldr r0, [pc, #72] ; (8003bac <HAL_I2C_MspDeInit+0x6c>)
8003b64: f002 f86e bl 8005c44 <HAL_GPIO_DeInit>
HAL_GPIO_DeInit(ARDUINO_SDA_D14_GPIO_Port, ARDUINO_SDA_D14_Pin);
8003b68: f44f 7100 mov.w r1, #512 ; 0x200
8003b6c: 480f ldr r0, [pc, #60] ; (8003bac <HAL_I2C_MspDeInit+0x6c>)
8003b6e: f002 f869 bl 8005c44 <HAL_GPIO_DeInit>
/* USER CODE BEGIN I2C3_MspDeInit 1 */
/* USER CODE END I2C3_MspDeInit 1 */
}
}
8003b72: e013 b.n 8003b9c <HAL_I2C_MspDeInit+0x5c>
else if(hi2c->Instance==I2C3)
8003b74: 687b ldr r3, [r7, #4]
8003b76: 681b ldr r3, [r3, #0]
8003b78: 4a0d ldr r2, [pc, #52] ; (8003bb0 <HAL_I2C_MspDeInit+0x70>)
8003b7a: 4293 cmp r3, r2
8003b7c: d10e bne.n 8003b9c <HAL_I2C_MspDeInit+0x5c>
__HAL_RCC_I2C3_CLK_DISABLE();
8003b7e: 4b0a ldr r3, [pc, #40] ; (8003ba8 <HAL_I2C_MspDeInit+0x68>)
8003b80: 6c1b ldr r3, [r3, #64] ; 0x40
8003b82: 4a09 ldr r2, [pc, #36] ; (8003ba8 <HAL_I2C_MspDeInit+0x68>)
8003b84: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8003b88: 6413 str r3, [r2, #64] ; 0x40
HAL_GPIO_DeInit(LCD_SCL_GPIO_Port, LCD_SCL_Pin);
8003b8a: 2180 movs r1, #128 ; 0x80
8003b8c: 4809 ldr r0, [pc, #36] ; (8003bb4 <HAL_I2C_MspDeInit+0x74>)
8003b8e: f002 f859 bl 8005c44 <HAL_GPIO_DeInit>
HAL_GPIO_DeInit(LCD_SDA_GPIO_Port, LCD_SDA_Pin);
8003b92: f44f 7180 mov.w r1, #256 ; 0x100
8003b96: 4807 ldr r0, [pc, #28] ; (8003bb4 <HAL_I2C_MspDeInit+0x74>)
8003b98: f002 f854 bl 8005c44 <HAL_GPIO_DeInit>
}
8003b9c: bf00 nop
8003b9e: 3708 adds r7, #8
8003ba0: 46bd mov sp, r7
8003ba2: bd80 pop {r7, pc}
8003ba4: 40005400 .word 0x40005400
8003ba8: 40023800 .word 0x40023800
8003bac: 40020400 .word 0x40020400
8003bb0: 40005c00 .word 0x40005c00
8003bb4: 40021c00 .word 0x40021c00
08003bb8 <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
8003bb8: b580 push {r7, lr}
8003bba: b08e sub sp, #56 ; 0x38
8003bbc: af00 add r7, sp, #0
8003bbe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003bc0: f107 0324 add.w r3, r7, #36 ; 0x24
8003bc4: 2200 movs r2, #0
8003bc6: 601a str r2, [r3, #0]
8003bc8: 605a str r2, [r3, #4]
8003bca: 609a str r2, [r3, #8]
8003bcc: 60da str r2, [r3, #12]
8003bce: 611a str r2, [r3, #16]
if(hltdc->Instance==LTDC)
8003bd0: 687b ldr r3, [r7, #4]
8003bd2: 681b ldr r3, [r3, #0]
8003bd4: 4a55 ldr r2, [pc, #340] ; (8003d2c <HAL_LTDC_MspInit+0x174>)
8003bd6: 4293 cmp r3, r2
8003bd8: f040 80a3 bne.w 8003d22 <HAL_LTDC_MspInit+0x16a>
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8003bdc: 4b54 ldr r3, [pc, #336] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003bde: 6c5b ldr r3, [r3, #68] ; 0x44
8003be0: 4a53 ldr r2, [pc, #332] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003be2: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8003be6: 6453 str r3, [r2, #68] ; 0x44
8003be8: 4b51 ldr r3, [pc, #324] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003bea: 6c5b ldr r3, [r3, #68] ; 0x44
8003bec: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003bf0: 623b str r3, [r7, #32]
8003bf2: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOE_CLK_ENABLE();
8003bf4: 4b4e ldr r3, [pc, #312] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003bf6: 6b1b ldr r3, [r3, #48] ; 0x30
8003bf8: 4a4d ldr r2, [pc, #308] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003bfa: f043 0310 orr.w r3, r3, #16
8003bfe: 6313 str r3, [r2, #48] ; 0x30
8003c00: 4b4b ldr r3, [pc, #300] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c02: 6b1b ldr r3, [r3, #48] ; 0x30
8003c04: f003 0310 and.w r3, r3, #16
8003c08: 61fb str r3, [r7, #28]
8003c0a: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOJ_CLK_ENABLE();
8003c0c: 4b48 ldr r3, [pc, #288] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c0e: 6b1b ldr r3, [r3, #48] ; 0x30
8003c10: 4a47 ldr r2, [pc, #284] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c12: f443 7300 orr.w r3, r3, #512 ; 0x200
8003c16: 6313 str r3, [r2, #48] ; 0x30
8003c18: 4b45 ldr r3, [pc, #276] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c1a: 6b1b ldr r3, [r3, #48] ; 0x30
8003c1c: f403 7300 and.w r3, r3, #512 ; 0x200
8003c20: 61bb str r3, [r7, #24]
8003c22: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOK_CLK_ENABLE();
8003c24: 4b42 ldr r3, [pc, #264] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c26: 6b1b ldr r3, [r3, #48] ; 0x30
8003c28: 4a41 ldr r2, [pc, #260] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c2a: f443 6380 orr.w r3, r3, #1024 ; 0x400
8003c2e: 6313 str r3, [r2, #48] ; 0x30
8003c30: 4b3f ldr r3, [pc, #252] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c32: 6b1b ldr r3, [r3, #48] ; 0x30
8003c34: f403 6380 and.w r3, r3, #1024 ; 0x400
8003c38: 617b str r3, [r7, #20]
8003c3a: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8003c3c: 4b3c ldr r3, [pc, #240] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c3e: 6b1b ldr r3, [r3, #48] ; 0x30
8003c40: 4a3b ldr r2, [pc, #236] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c42: f043 0340 orr.w r3, r3, #64 ; 0x40
8003c46: 6313 str r3, [r2, #48] ; 0x30
8003c48: 4b39 ldr r3, [pc, #228] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c4a: 6b1b ldr r3, [r3, #48] ; 0x30
8003c4c: f003 0340 and.w r3, r3, #64 ; 0x40
8003c50: 613b str r3, [r7, #16]
8003c52: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
8003c54: 4b36 ldr r3, [pc, #216] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c56: 6b1b ldr r3, [r3, #48] ; 0x30
8003c58: 4a35 ldr r2, [pc, #212] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c5a: f443 7380 orr.w r3, r3, #256 ; 0x100
8003c5e: 6313 str r3, [r2, #48] ; 0x30
8003c60: 4b33 ldr r3, [pc, #204] ; (8003d30 <HAL_LTDC_MspInit+0x178>)
8003c62: 6b1b ldr r3, [r3, #48] ; 0x30
8003c64: f403 7380 and.w r3, r3, #256 ; 0x100
8003c68: 60fb str r3, [r7, #12]
8003c6a: 68fb ldr r3, [r7, #12]
PJ3 ------> LTDC_R4
PJ2 ------> LTDC_R3
PJ0 ------> LTDC_R1
PJ1 ------> LTDC_R2
*/
GPIO_InitStruct.Pin = LCD_B0_Pin;
8003c6c: 2310 movs r3, #16
8003c6e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003c70: 2302 movs r3, #2
8003c72: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003c74: 2300 movs r3, #0
8003c76: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003c78: 2300 movs r3, #0
8003c7a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8003c7c: 230e movs r3, #14
8003c7e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B0_GPIO_Port, &GPIO_InitStruct);
8003c80: f107 0324 add.w r3, r7, #36 ; 0x24
8003c84: 4619 mov r1, r3
8003c86: 482b ldr r0, [pc, #172] ; (8003d34 <HAL_LTDC_MspInit+0x17c>)
8003c88: f001 fe32 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B1_Pin|LCD_B2_Pin|LCD_B3_Pin|LCD_G4_Pin
8003c8c: f64e 73ff movw r3, #61439 ; 0xefff
8003c90: 627b str r3, [r7, #36] ; 0x24
|LCD_G1_Pin|LCD_G3_Pin|LCD_G0_Pin|LCD_G2_Pin
|LCD_R7_Pin|LCD_R5_Pin|LCD_R6_Pin|LCD_R4_Pin
|LCD_R3_Pin|LCD_R1_Pin|LCD_R2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003c92: 2302 movs r3, #2
8003c94: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003c96: 2300 movs r3, #0
8003c98: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003c9a: 2300 movs r3, #0
8003c9c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8003c9e: 230e movs r3, #14
8003ca0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
8003ca2: f107 0324 add.w r3, r7, #36 ; 0x24
8003ca6: 4619 mov r1, r3
8003ca8: 4823 ldr r0, [pc, #140] ; (8003d38 <HAL_LTDC_MspInit+0x180>)
8003caa: f001 fe21 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_DE_Pin|LCD_B7_Pin|LCD_B6_Pin|LCD_B5_Pin
8003cae: 23f7 movs r3, #247 ; 0xf7
8003cb0: 627b str r3, [r7, #36] ; 0x24
|LCD_G6_Pin|LCD_G7_Pin|LCD_G5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003cb2: 2302 movs r3, #2
8003cb4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003cb6: 2300 movs r3, #0
8003cb8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003cba: 2300 movs r3, #0
8003cbc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8003cbe: 230e movs r3, #14
8003cc0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
8003cc2: f107 0324 add.w r3, r7, #36 ; 0x24
8003cc6: 4619 mov r1, r3
8003cc8: 481c ldr r0, [pc, #112] ; (8003d3c <HAL_LTDC_MspInit+0x184>)
8003cca: f001 fe11 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_B4_Pin;
8003cce: f44f 5380 mov.w r3, #4096 ; 0x1000
8003cd2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003cd4: 2302 movs r3, #2
8003cd6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003cd8: 2300 movs r3, #0
8003cda: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003cdc: 2300 movs r3, #0
8003cde: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8003ce0: 2309 movs r3, #9
8003ce2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(LCD_B4_GPIO_Port, &GPIO_InitStruct);
8003ce4: f107 0324 add.w r3, r7, #36 ; 0x24
8003ce8: 4619 mov r1, r3
8003cea: 4815 ldr r0, [pc, #84] ; (8003d40 <HAL_LTDC_MspInit+0x188>)
8003cec: f001 fe00 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LCD_HSYNC_Pin|LCD_VSYNC_Pin|LCD_R0_Pin|LCD_CLK_Pin;
8003cf0: f44f 4346 mov.w r3, #50688 ; 0xc600
8003cf4: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003cf6: 2302 movs r3, #2
8003cf8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003cfa: 2300 movs r3, #0
8003cfc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003cfe: 2300 movs r3, #0
8003d00: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8003d02: 230e movs r3, #14
8003d04: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8003d06: f107 0324 add.w r3, r7, #36 ; 0x24
8003d0a: 4619 mov r1, r3
8003d0c: 480d ldr r0, [pc, #52] ; (8003d44 <HAL_LTDC_MspInit+0x18c>)
8003d0e: f001 fdef bl 80058f0 <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
8003d12: 2200 movs r2, #0
8003d14: 2105 movs r1, #5
8003d16: 2058 movs r0, #88 ; 0x58
8003d18: f001 f8aa bl 8004e70 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
8003d1c: 2058 movs r0, #88 ; 0x58
8003d1e: f001 f8c3 bl 8004ea8 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
8003d22: bf00 nop
8003d24: 3738 adds r7, #56 ; 0x38
8003d26: 46bd mov sp, r7
8003d28: bd80 pop {r7, pc}
8003d2a: bf00 nop
8003d2c: 40016800 .word 0x40016800
8003d30: 40023800 .word 0x40023800
8003d34: 40021000 .word 0x40021000
8003d38: 40022400 .word 0x40022400
8003d3c: 40022800 .word 0x40022800
8003d40: 40021800 .word 0x40021800
8003d44: 40022000 .word 0x40022000
08003d48 <HAL_RTC_MspInit>:
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
8003d48: b480 push {r7}
8003d4a: b083 sub sp, #12
8003d4c: af00 add r7, sp, #0
8003d4e: 6078 str r0, [r7, #4]
if(hrtc->Instance==RTC)
8003d50: 687b ldr r3, [r7, #4]
8003d52: 681b ldr r3, [r3, #0]
8003d54: 4a07 ldr r2, [pc, #28] ; (8003d74 <HAL_RTC_MspInit+0x2c>)
8003d56: 4293 cmp r3, r2
8003d58: d105 bne.n 8003d66 <HAL_RTC_MspInit+0x1e>
{
/* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE();
8003d5a: 4b07 ldr r3, [pc, #28] ; (8003d78 <HAL_RTC_MspInit+0x30>)
8003d5c: 6f1b ldr r3, [r3, #112] ; 0x70
8003d5e: 4a06 ldr r2, [pc, #24] ; (8003d78 <HAL_RTC_MspInit+0x30>)
8003d60: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8003d64: 6713 str r3, [r2, #112] ; 0x70
/* USER CODE BEGIN RTC_MspInit 1 */
/* USER CODE END RTC_MspInit 1 */
}
}
8003d66: bf00 nop
8003d68: 370c adds r7, #12
8003d6a: 46bd mov sp, r7
8003d6c: f85d 7b04 ldr.w r7, [sp], #4
8003d70: 4770 bx lr
8003d72: bf00 nop
8003d74: 40002800 .word 0x40002800
8003d78: 40023800 .word 0x40023800
08003d7c <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8003d7c: b580 push {r7, lr}
8003d7e: b08a sub sp, #40 ; 0x28
8003d80: af00 add r7, sp, #0
8003d82: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003d84: f107 0314 add.w r3, r7, #20
8003d88: 2200 movs r2, #0
8003d8a: 601a str r2, [r3, #0]
8003d8c: 605a str r2, [r3, #4]
8003d8e: 609a str r2, [r3, #8]
8003d90: 60da str r2, [r3, #12]
8003d92: 611a str r2, [r3, #16]
if(hspi->Instance==SPI2)
8003d94: 687b ldr r3, [r7, #4]
8003d96: 681b ldr r3, [r3, #0]
8003d98: 4a2d ldr r2, [pc, #180] ; (8003e50 <HAL_SPI_MspInit+0xd4>)
8003d9a: 4293 cmp r3, r2
8003d9c: d154 bne.n 8003e48 <HAL_SPI_MspInit+0xcc>
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
8003d9e: 4b2d ldr r3, [pc, #180] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003da0: 6c1b ldr r3, [r3, #64] ; 0x40
8003da2: 4a2c ldr r2, [pc, #176] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003da4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8003da8: 6413 str r3, [r2, #64] ; 0x40
8003daa: 4b2a ldr r3, [pc, #168] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003dac: 6c1b ldr r3, [r3, #64] ; 0x40
8003dae: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003db2: 613b str r3, [r7, #16]
8003db4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOI_CLK_ENABLE();
8003db6: 4b27 ldr r3, [pc, #156] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003db8: 6b1b ldr r3, [r3, #48] ; 0x30
8003dba: 4a26 ldr r2, [pc, #152] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003dbc: f443 7380 orr.w r3, r3, #256 ; 0x100
8003dc0: 6313 str r3, [r2, #48] ; 0x30
8003dc2: 4b24 ldr r3, [pc, #144] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003dc4: 6b1b ldr r3, [r3, #48] ; 0x30
8003dc6: f403 7380 and.w r3, r3, #256 ; 0x100
8003dca: 60fb str r3, [r7, #12]
8003dcc: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8003dce: 4b21 ldr r3, [pc, #132] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003dd0: 6b1b ldr r3, [r3, #48] ; 0x30
8003dd2: 4a20 ldr r2, [pc, #128] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003dd4: f043 0302 orr.w r3, r3, #2
8003dd8: 6313 str r3, [r2, #48] ; 0x30
8003dda: 4b1e ldr r3, [pc, #120] ; (8003e54 <HAL_SPI_MspInit+0xd8>)
8003ddc: 6b1b ldr r3, [r3, #48] ; 0x30
8003dde: f003 0302 and.w r3, r3, #2
8003de2: 60bb str r3, [r7, #8]
8003de4: 68bb ldr r3, [r7, #8]
PI1 ------> SPI2_SCK
PI0 ------> SPI2_NSS
PB14 ------> SPI2_MISO
PB15 ------> SPI2_MOSI
*/
GPIO_InitStruct.Pin = ARDUINO_SCK_D13_Pin;
8003de6: 2302 movs r3, #2
8003de8: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003dea: 2302 movs r3, #2
8003dec: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003dee: 2300 movs r3, #0
8003df0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003df2: 2300 movs r3, #0
8003df4: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8003df6: 2305 movs r3, #5
8003df8: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(ARDUINO_SCK_D13_GPIO_Port, &GPIO_InitStruct);
8003dfa: f107 0314 add.w r3, r7, #20
8003dfe: 4619 mov r1, r3
8003e00: 4815 ldr r0, [pc, #84] ; (8003e58 <HAL_SPI_MspInit+0xdc>)
8003e02: f001 fd75 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0;
8003e06: 2301 movs r3, #1
8003e08: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003e0a: 2302 movs r3, #2
8003e0c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e0e: 2300 movs r3, #0
8003e10: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8003e12: 2303 movs r3, #3
8003e14: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8003e16: 2305 movs r3, #5
8003e18: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8003e1a: f107 0314 add.w r3, r7, #20
8003e1e: 4619 mov r1, r3
8003e20: 480d ldr r0, [pc, #52] ; (8003e58 <HAL_SPI_MspInit+0xdc>)
8003e22: f001 fd65 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
8003e26: f44f 4340 mov.w r3, #49152 ; 0xc000
8003e2a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003e2c: 2302 movs r3, #2
8003e2e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003e30: 2300 movs r3, #0
8003e32: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8003e34: 2303 movs r3, #3
8003e36: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8003e38: 2305 movs r3, #5
8003e3a: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8003e3c: f107 0314 add.w r3, r7, #20
8003e40: 4619 mov r1, r3
8003e42: 4806 ldr r0, [pc, #24] ; (8003e5c <HAL_SPI_MspInit+0xe0>)
8003e44: f001 fd54 bl 80058f0 <HAL_GPIO_Init>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8003e48: bf00 nop
8003e4a: 3728 adds r7, #40 ; 0x28
8003e4c: 46bd mov sp, r7
8003e4e: bd80 pop {r7, pc}
8003e50: 40003800 .word 0x40003800
8003e54: 40023800 .word 0x40023800
8003e58: 40022000 .word 0x40022000
8003e5c: 40020400 .word 0x40020400
08003e60 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8003e60: b480 push {r7}
8003e62: b089 sub sp, #36 ; 0x24
8003e64: af00 add r7, sp, #0
8003e66: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8003e68: 687b ldr r3, [r7, #4]
8003e6a: 681b ldr r3, [r3, #0]
8003e6c: 4a2e ldr r2, [pc, #184] ; (8003f28 <HAL_TIM_Base_MspInit+0xc8>)
8003e6e: 4293 cmp r3, r2
8003e70: d10c bne.n 8003e8c <HAL_TIM_Base_MspInit+0x2c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
8003e72: 4b2e ldr r3, [pc, #184] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003e74: 6c5b ldr r3, [r3, #68] ; 0x44
8003e76: 4a2d ldr r2, [pc, #180] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003e78: f043 0301 orr.w r3, r3, #1
8003e7c: 6453 str r3, [r2, #68] ; 0x44
8003e7e: 4b2b ldr r3, [pc, #172] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003e80: 6c5b ldr r3, [r3, #68] ; 0x44
8003e82: f003 0301 and.w r3, r3, #1
8003e86: 61fb str r3, [r7, #28]
8003e88: 69fb ldr r3, [r7, #28]
/* USER CODE BEGIN TIM8_MspInit 1 */
/* USER CODE END TIM8_MspInit 1 */
}
}
8003e8a: e046 b.n 8003f1a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM2)
8003e8c: 687b ldr r3, [r7, #4]
8003e8e: 681b ldr r3, [r3, #0]
8003e90: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003e94: d10c bne.n 8003eb0 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM2_CLK_ENABLE();
8003e96: 4b25 ldr r3, [pc, #148] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003e98: 6c1b ldr r3, [r3, #64] ; 0x40
8003e9a: 4a24 ldr r2, [pc, #144] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003e9c: f043 0301 orr.w r3, r3, #1
8003ea0: 6413 str r3, [r2, #64] ; 0x40
8003ea2: 4b22 ldr r3, [pc, #136] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ea4: 6c1b ldr r3, [r3, #64] ; 0x40
8003ea6: f003 0301 and.w r3, r3, #1
8003eaa: 61bb str r3, [r7, #24]
8003eac: 69bb ldr r3, [r7, #24]
}
8003eae: e034 b.n 8003f1a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM3)
8003eb0: 687b ldr r3, [r7, #4]
8003eb2: 681b ldr r3, [r3, #0]
8003eb4: 4a1e ldr r2, [pc, #120] ; (8003f30 <HAL_TIM_Base_MspInit+0xd0>)
8003eb6: 4293 cmp r3, r2
8003eb8: d10c bne.n 8003ed4 <HAL_TIM_Base_MspInit+0x74>
__HAL_RCC_TIM3_CLK_ENABLE();
8003eba: 4b1c ldr r3, [pc, #112] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ebc: 6c1b ldr r3, [r3, #64] ; 0x40
8003ebe: 4a1b ldr r2, [pc, #108] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ec0: f043 0302 orr.w r3, r3, #2
8003ec4: 6413 str r3, [r2, #64] ; 0x40
8003ec6: 4b19 ldr r3, [pc, #100] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ec8: 6c1b ldr r3, [r3, #64] ; 0x40
8003eca: f003 0302 and.w r3, r3, #2
8003ece: 617b str r3, [r7, #20]
8003ed0: 697b ldr r3, [r7, #20]
}
8003ed2: e022 b.n 8003f1a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM5)
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 681b ldr r3, [r3, #0]
8003ed8: 4a16 ldr r2, [pc, #88] ; (8003f34 <HAL_TIM_Base_MspInit+0xd4>)
8003eda: 4293 cmp r3, r2
8003edc: d10c bne.n 8003ef8 <HAL_TIM_Base_MspInit+0x98>
__HAL_RCC_TIM5_CLK_ENABLE();
8003ede: 4b13 ldr r3, [pc, #76] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ee0: 6c1b ldr r3, [r3, #64] ; 0x40
8003ee2: 4a12 ldr r2, [pc, #72] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003ee4: f043 0308 orr.w r3, r3, #8
8003ee8: 6413 str r3, [r2, #64] ; 0x40
8003eea: 4b10 ldr r3, [pc, #64] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003eec: 6c1b ldr r3, [r3, #64] ; 0x40
8003eee: f003 0308 and.w r3, r3, #8
8003ef2: 613b str r3, [r7, #16]
8003ef4: 693b ldr r3, [r7, #16]
}
8003ef6: e010 b.n 8003f1a <HAL_TIM_Base_MspInit+0xba>
else if(htim_base->Instance==TIM8)
8003ef8: 687b ldr r3, [r7, #4]
8003efa: 681b ldr r3, [r3, #0]
8003efc: 4a0e ldr r2, [pc, #56] ; (8003f38 <HAL_TIM_Base_MspInit+0xd8>)
8003efe: 4293 cmp r3, r2
8003f00: d10b bne.n 8003f1a <HAL_TIM_Base_MspInit+0xba>
__HAL_RCC_TIM8_CLK_ENABLE();
8003f02: 4b0a ldr r3, [pc, #40] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003f04: 6c5b ldr r3, [r3, #68] ; 0x44
8003f06: 4a09 ldr r2, [pc, #36] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003f08: f043 0302 orr.w r3, r3, #2
8003f0c: 6453 str r3, [r2, #68] ; 0x44
8003f0e: 4b07 ldr r3, [pc, #28] ; (8003f2c <HAL_TIM_Base_MspInit+0xcc>)
8003f10: 6c5b ldr r3, [r3, #68] ; 0x44
8003f12: f003 0302 and.w r3, r3, #2
8003f16: 60fb str r3, [r7, #12]
8003f18: 68fb ldr r3, [r7, #12]
}
8003f1a: bf00 nop
8003f1c: 3724 adds r7, #36 ; 0x24
8003f1e: 46bd mov sp, r7
8003f20: f85d 7b04 ldr.w r7, [sp], #4
8003f24: 4770 bx lr
8003f26: bf00 nop
8003f28: 40010000 .word 0x40010000
8003f2c: 40023800 .word 0x40023800
8003f30: 40000400 .word 0x40000400
8003f34: 40000c00 .word 0x40000c00
8003f38: 40010400 .word 0x40010400
08003f3c <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
8003f3c: b580 push {r7, lr}
8003f3e: b08a sub sp, #40 ; 0x28
8003f40: af00 add r7, sp, #0
8003f42: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8003f44: f107 0314 add.w r3, r7, #20
8003f48: 2200 movs r2, #0
8003f4a: 601a str r2, [r3, #0]
8003f4c: 605a str r2, [r3, #4]
8003f4e: 609a str r2, [r3, #8]
8003f50: 60da str r2, [r3, #12]
8003f52: 611a str r2, [r3, #16]
if(htim->Instance==TIM3)
8003f54: 687b ldr r3, [r7, #4]
8003f56: 681b ldr r3, [r3, #0]
8003f58: 4a22 ldr r2, [pc, #136] ; (8003fe4 <HAL_TIM_MspPostInit+0xa8>)
8003f5a: 4293 cmp r3, r2
8003f5c: d11c bne.n 8003f98 <HAL_TIM_MspPostInit+0x5c>
{
/* USER CODE BEGIN TIM3_MspPostInit 0 */
/* USER CODE END TIM3_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
8003f5e: 4b22 ldr r3, [pc, #136] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003f60: 6b1b ldr r3, [r3, #48] ; 0x30
8003f62: 4a21 ldr r2, [pc, #132] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003f64: f043 0302 orr.w r3, r3, #2
8003f68: 6313 str r3, [r2, #48] ; 0x30
8003f6a: 4b1f ldr r3, [pc, #124] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003f6c: 6b1b ldr r3, [r3, #48] ; 0x30
8003f6e: f003 0302 and.w r3, r3, #2
8003f72: 613b str r3, [r7, #16]
8003f74: 693b ldr r3, [r7, #16]
/**TIM3 GPIO Configuration
PB4 ------> TIM3_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_4;
8003f76: 2310 movs r3, #16
8003f78: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003f7a: 2302 movs r3, #2
8003f7c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003f7e: 2300 movs r3, #0
8003f80: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003f82: 2300 movs r3, #0
8003f84: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
8003f86: 2302 movs r3, #2
8003f88: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8003f8a: f107 0314 add.w r3, r7, #20
8003f8e: 4619 mov r1, r3
8003f90: 4816 ldr r0, [pc, #88] ; (8003fec <HAL_TIM_MspPostInit+0xb0>)
8003f92: f001 fcad bl 80058f0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM8_MspPostInit 1 */
/* USER CODE END TIM8_MspPostInit 1 */
}
}
8003f96: e020 b.n 8003fda <HAL_TIM_MspPostInit+0x9e>
else if(htim->Instance==TIM8)
8003f98: 687b ldr r3, [r7, #4]
8003f9a: 681b ldr r3, [r3, #0]
8003f9c: 4a14 ldr r2, [pc, #80] ; (8003ff0 <HAL_TIM_MspPostInit+0xb4>)
8003f9e: 4293 cmp r3, r2
8003fa0: d11b bne.n 8003fda <HAL_TIM_MspPostInit+0x9e>
__HAL_RCC_GPIOI_CLK_ENABLE();
8003fa2: 4b11 ldr r3, [pc, #68] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003fa4: 6b1b ldr r3, [r3, #48] ; 0x30
8003fa6: 4a10 ldr r2, [pc, #64] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003fa8: f443 7380 orr.w r3, r3, #256 ; 0x100
8003fac: 6313 str r3, [r2, #48] ; 0x30
8003fae: 4b0e ldr r3, [pc, #56] ; (8003fe8 <HAL_TIM_MspPostInit+0xac>)
8003fb0: 6b1b ldr r3, [r3, #48] ; 0x30
8003fb2: f403 7380 and.w r3, r3, #256 ; 0x100
8003fb6: 60fb str r3, [r7, #12]
8003fb8: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_2;
8003fba: 2304 movs r3, #4
8003fbc: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8003fbe: 2302 movs r3, #2
8003fc0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8003fc2: 2300 movs r3, #0
8003fc4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8003fc6: 2300 movs r3, #0
8003fc8: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF3_TIM8;
8003fca: 2303 movs r3, #3
8003fcc: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
8003fce: f107 0314 add.w r3, r7, #20
8003fd2: 4619 mov r1, r3
8003fd4: 4807 ldr r0, [pc, #28] ; (8003ff4 <HAL_TIM_MspPostInit+0xb8>)
8003fd6: f001 fc8b bl 80058f0 <HAL_GPIO_Init>
}
8003fda: bf00 nop
8003fdc: 3728 adds r7, #40 ; 0x28
8003fde: 46bd mov sp, r7
8003fe0: bd80 pop {r7, pc}
8003fe2: bf00 nop
8003fe4: 40000400 .word 0x40000400
8003fe8: 40023800 .word 0x40023800
8003fec: 40020400 .word 0x40020400
8003ff0: 40010400 .word 0x40010400
8003ff4: 40022000 .word 0x40022000
08003ff8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8003ff8: b580 push {r7, lr}
8003ffa: b08e sub sp, #56 ; 0x38
8003ffc: af00 add r7, sp, #0
8003ffe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8004000: f107 0324 add.w r3, r7, #36 ; 0x24
8004004: 2200 movs r2, #0
8004006: 601a str r2, [r3, #0]
8004008: 605a str r2, [r3, #4]
800400a: 609a str r2, [r3, #8]
800400c: 60da str r2, [r3, #12]
800400e: 611a str r2, [r3, #16]
if(huart->Instance==UART7)
8004010: 687b ldr r3, [r7, #4]
8004012: 681b ldr r3, [r3, #0]
8004014: 4a53 ldr r2, [pc, #332] ; (8004164 <HAL_UART_MspInit+0x16c>)
8004016: 4293 cmp r3, r2
8004018: d128 bne.n 800406c <HAL_UART_MspInit+0x74>
{
/* USER CODE BEGIN UART7_MspInit 0 */
/* USER CODE END UART7_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_UART7_CLK_ENABLE();
800401a: 4b53 ldr r3, [pc, #332] ; (8004168 <HAL_UART_MspInit+0x170>)
800401c: 6c1b ldr r3, [r3, #64] ; 0x40
800401e: 4a52 ldr r2, [pc, #328] ; (8004168 <HAL_UART_MspInit+0x170>)
8004020: f043 4380 orr.w r3, r3, #1073741824 ; 0x40000000
8004024: 6413 str r3, [r2, #64] ; 0x40
8004026: 4b50 ldr r3, [pc, #320] ; (8004168 <HAL_UART_MspInit+0x170>)
8004028: 6c1b ldr r3, [r3, #64] ; 0x40
800402a: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
800402e: 623b str r3, [r7, #32]
8004030: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOF_CLK_ENABLE();
8004032: 4b4d ldr r3, [pc, #308] ; (8004168 <HAL_UART_MspInit+0x170>)
8004034: 6b1b ldr r3, [r3, #48] ; 0x30
8004036: 4a4c ldr r2, [pc, #304] ; (8004168 <HAL_UART_MspInit+0x170>)
8004038: f043 0320 orr.w r3, r3, #32
800403c: 6313 str r3, [r2, #48] ; 0x30
800403e: 4b4a ldr r3, [pc, #296] ; (8004168 <HAL_UART_MspInit+0x170>)
8004040: 6b1b ldr r3, [r3, #48] ; 0x30
8004042: f003 0320 and.w r3, r3, #32
8004046: 61fb str r3, [r7, #28]
8004048: 69fb ldr r3, [r7, #28]
/**UART7 GPIO Configuration
PF7 ------> UART7_TX
PF6 ------> UART7_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
800404a: 23c0 movs r3, #192 ; 0xc0
800404c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800404e: 2302 movs r3, #2
8004050: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004052: 2300 movs r3, #0
8004054: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004056: 2303 movs r3, #3
8004058: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_UART7;
800405a: 2308 movs r3, #8
800405c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
800405e: f107 0324 add.w r3, r7, #36 ; 0x24
8004062: 4619 mov r1, r3
8004064: 4841 ldr r0, [pc, #260] ; (800416c <HAL_UART_MspInit+0x174>)
8004066: f001 fc43 bl 80058f0 <HAL_GPIO_Init>
/* USER CODE BEGIN USART6_MspInit 1 */
/* USER CODE END USART6_MspInit 1 */
}
}
800406a: e077 b.n 800415c <HAL_UART_MspInit+0x164>
else if(huart->Instance==USART1)
800406c: 687b ldr r3, [r7, #4]
800406e: 681b ldr r3, [r3, #0]
8004070: 4a3f ldr r2, [pc, #252] ; (8004170 <HAL_UART_MspInit+0x178>)
8004072: 4293 cmp r3, r2
8004074: d145 bne.n 8004102 <HAL_UART_MspInit+0x10a>
__HAL_RCC_USART1_CLK_ENABLE();
8004076: 4b3c ldr r3, [pc, #240] ; (8004168 <HAL_UART_MspInit+0x170>)
8004078: 6c5b ldr r3, [r3, #68] ; 0x44
800407a: 4a3b ldr r2, [pc, #236] ; (8004168 <HAL_UART_MspInit+0x170>)
800407c: f043 0310 orr.w r3, r3, #16
8004080: 6453 str r3, [r2, #68] ; 0x44
8004082: 4b39 ldr r3, [pc, #228] ; (8004168 <HAL_UART_MspInit+0x170>)
8004084: 6c5b ldr r3, [r3, #68] ; 0x44
8004086: f003 0310 and.w r3, r3, #16
800408a: 61bb str r3, [r7, #24]
800408c: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
800408e: 4b36 ldr r3, [pc, #216] ; (8004168 <HAL_UART_MspInit+0x170>)
8004090: 6b1b ldr r3, [r3, #48] ; 0x30
8004092: 4a35 ldr r2, [pc, #212] ; (8004168 <HAL_UART_MspInit+0x170>)
8004094: f043 0302 orr.w r3, r3, #2
8004098: 6313 str r3, [r2, #48] ; 0x30
800409a: 4b33 ldr r3, [pc, #204] ; (8004168 <HAL_UART_MspInit+0x170>)
800409c: 6b1b ldr r3, [r3, #48] ; 0x30
800409e: f003 0302 and.w r3, r3, #2
80040a2: 617b str r3, [r7, #20]
80040a4: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
80040a6: 4b30 ldr r3, [pc, #192] ; (8004168 <HAL_UART_MspInit+0x170>)
80040a8: 6b1b ldr r3, [r3, #48] ; 0x30
80040aa: 4a2f ldr r2, [pc, #188] ; (8004168 <HAL_UART_MspInit+0x170>)
80040ac: f043 0301 orr.w r3, r3, #1
80040b0: 6313 str r3, [r2, #48] ; 0x30
80040b2: 4b2d ldr r3, [pc, #180] ; (8004168 <HAL_UART_MspInit+0x170>)
80040b4: 6b1b ldr r3, [r3, #48] ; 0x30
80040b6: f003 0301 and.w r3, r3, #1
80040ba: 613b str r3, [r7, #16]
80040bc: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = VCP_RX_Pin;
80040be: 2380 movs r3, #128 ; 0x80
80040c0: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80040c2: 2302 movs r3, #2
80040c4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80040c6: 2300 movs r3, #0
80040c8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80040ca: 2300 movs r3, #0
80040cc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
80040ce: 2307 movs r3, #7
80040d0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(VCP_RX_GPIO_Port, &GPIO_InitStruct);
80040d2: f107 0324 add.w r3, r7, #36 ; 0x24
80040d6: 4619 mov r1, r3
80040d8: 4826 ldr r0, [pc, #152] ; (8004174 <HAL_UART_MspInit+0x17c>)
80040da: f001 fc09 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = VCP_TX_Pin;
80040de: f44f 7300 mov.w r3, #512 ; 0x200
80040e2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80040e4: 2302 movs r3, #2
80040e6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80040e8: 2300 movs r3, #0
80040ea: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80040ec: 2300 movs r3, #0
80040ee: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
80040f0: 2307 movs r3, #7
80040f2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(VCP_TX_GPIO_Port, &GPIO_InitStruct);
80040f4: f107 0324 add.w r3, r7, #36 ; 0x24
80040f8: 4619 mov r1, r3
80040fa: 481f ldr r0, [pc, #124] ; (8004178 <HAL_UART_MspInit+0x180>)
80040fc: f001 fbf8 bl 80058f0 <HAL_GPIO_Init>
}
8004100: e02c b.n 800415c <HAL_UART_MspInit+0x164>
else if(huart->Instance==USART6)
8004102: 687b ldr r3, [r7, #4]
8004104: 681b ldr r3, [r3, #0]
8004106: 4a1d ldr r2, [pc, #116] ; (800417c <HAL_UART_MspInit+0x184>)
8004108: 4293 cmp r3, r2
800410a: d127 bne.n 800415c <HAL_UART_MspInit+0x164>
__HAL_RCC_USART6_CLK_ENABLE();
800410c: 4b16 ldr r3, [pc, #88] ; (8004168 <HAL_UART_MspInit+0x170>)
800410e: 6c5b ldr r3, [r3, #68] ; 0x44
8004110: 4a15 ldr r2, [pc, #84] ; (8004168 <HAL_UART_MspInit+0x170>)
8004112: f043 0320 orr.w r3, r3, #32
8004116: 6453 str r3, [r2, #68] ; 0x44
8004118: 4b13 ldr r3, [pc, #76] ; (8004168 <HAL_UART_MspInit+0x170>)
800411a: 6c5b ldr r3, [r3, #68] ; 0x44
800411c: f003 0320 and.w r3, r3, #32
8004120: 60fb str r3, [r7, #12]
8004122: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
8004124: 4b10 ldr r3, [pc, #64] ; (8004168 <HAL_UART_MspInit+0x170>)
8004126: 6b1b ldr r3, [r3, #48] ; 0x30
8004128: 4a0f ldr r2, [pc, #60] ; (8004168 <HAL_UART_MspInit+0x170>)
800412a: f043 0304 orr.w r3, r3, #4
800412e: 6313 str r3, [r2, #48] ; 0x30
8004130: 4b0d ldr r3, [pc, #52] ; (8004168 <HAL_UART_MspInit+0x170>)
8004132: 6b1b ldr r3, [r3, #48] ; 0x30
8004134: f003 0304 and.w r3, r3, #4
8004138: 60bb str r3, [r7, #8]
800413a: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6;
800413c: 23c0 movs r3, #192 ; 0xc0
800413e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004140: 2302 movs r3, #2
8004142: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004144: 2300 movs r3, #0
8004146: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004148: 2303 movs r3, #3
800414a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
800414c: 2308 movs r3, #8
800414e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8004150: f107 0324 add.w r3, r7, #36 ; 0x24
8004154: 4619 mov r1, r3
8004156: 480a ldr r0, [pc, #40] ; (8004180 <HAL_UART_MspInit+0x188>)
8004158: f001 fbca bl 80058f0 <HAL_GPIO_Init>
}
800415c: bf00 nop
800415e: 3738 adds r7, #56 ; 0x38
8004160: 46bd mov sp, r7
8004162: bd80 pop {r7, pc}
8004164: 40007800 .word 0x40007800
8004168: 40023800 .word 0x40023800
800416c: 40021400 .word 0x40021400
8004170: 40011000 .word 0x40011000
8004174: 40020400 .word 0x40020400
8004178: 40020000 .word 0x40020000
800417c: 40011400 .word 0x40011400
8004180: 40020800 .word 0x40020800
08004184 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
8004184: b580 push {r7, lr}
8004186: b086 sub sp, #24
8004188: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
800418a: 1d3b adds r3, r7, #4
800418c: 2200 movs r2, #0
800418e: 601a str r2, [r3, #0]
8004190: 605a str r2, [r3, #4]
8004192: 609a str r2, [r3, #8]
8004194: 60da str r2, [r3, #12]
8004196: 611a str r2, [r3, #16]
if (FMC_Initialized) {
8004198: 4b3a ldr r3, [pc, #232] ; (8004284 <HAL_FMC_MspInit+0x100>)
800419a: 681b ldr r3, [r3, #0]
800419c: 2b00 cmp r3, #0
800419e: d16d bne.n 800427c <HAL_FMC_MspInit+0xf8>
return;
}
FMC_Initialized = 1;
80041a0: 4b38 ldr r3, [pc, #224] ; (8004284 <HAL_FMC_MspInit+0x100>)
80041a2: 2201 movs r2, #1
80041a4: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
80041a6: 4b38 ldr r3, [pc, #224] ; (8004288 <HAL_FMC_MspInit+0x104>)
80041a8: 6b9b ldr r3, [r3, #56] ; 0x38
80041aa: 4a37 ldr r2, [pc, #220] ; (8004288 <HAL_FMC_MspInit+0x104>)
80041ac: f043 0301 orr.w r3, r3, #1
80041b0: 6393 str r3, [r2, #56] ; 0x38
80041b2: 4b35 ldr r3, [pc, #212] ; (8004288 <HAL_FMC_MspInit+0x104>)
80041b4: 6b9b ldr r3, [r3, #56] ; 0x38
80041b6: f003 0301 and.w r3, r3, #1
80041ba: 603b str r3, [r7, #0]
80041bc: 683b ldr r3, [r7, #0]
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
PE13 ------> FMC_D10
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9
80041be: f64f 7383 movw r3, #65411 ; 0xff83
80041c2: 607b str r3, [r7, #4]
|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7|GPIO_PIN_10
|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041c4: 2302 movs r3, #2
80041c6: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041c8: 2300 movs r3, #0
80041ca: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80041cc: 2303 movs r3, #3
80041ce: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80041d0: 230c movs r3, #12
80041d2: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
80041d4: 1d3b adds r3, r7, #4
80041d6: 4619 mov r1, r3
80041d8: 482c ldr r0, [pc, #176] ; (800428c <HAL_FMC_MspInit+0x108>)
80041da: f001 fb89 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_1|GPIO_PIN_0
80041de: f248 1333 movw r3, #33075 ; 0x8133
80041e2: 607b str r3, [r7, #4]
|GPIO_PIN_5|GPIO_PIN_4;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80041e4: 2302 movs r3, #2
80041e6: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80041e8: 2300 movs r3, #0
80041ea: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80041ec: 2303 movs r3, #3
80041ee: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80041f0: 230c movs r3, #12
80041f2: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
80041f4: 1d3b adds r3, r7, #4
80041f6: 4619 mov r1, r3
80041f8: 4825 ldr r0, [pc, #148] ; (8004290 <HAL_FMC_MspInit+0x10c>)
80041fa: f001 fb79 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10
80041fe: f24c 7303 movw r3, #50947 ; 0xc703
8004202: 607b str r3, [r7, #4]
|GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004204: 2302 movs r3, #2
8004206: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004208: 2300 movs r3, #0
800420a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800420c: 2303 movs r3, #3
800420e: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004210: 230c movs r3, #12
8004212: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8004214: 1d3b adds r3, r7, #4
8004216: 4619 mov r1, r3
8004218: 481e ldr r0, [pc, #120] ; (8004294 <HAL_FMC_MspInit+0x110>)
800421a: f001 fb69 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
800421e: f64f 033f movw r3, #63551 ; 0xf83f
8004222: 607b str r3, [r7, #4]
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15
|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004224: 2302 movs r3, #2
8004226: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004228: 2300 movs r3, #0
800422a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800422c: 2303 movs r3, #3
800422e: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8004230: 230c movs r3, #12
8004232: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8004234: 1d3b adds r3, r7, #4
8004236: 4619 mov r1, r3
8004238: 4817 ldr r0, [pc, #92] ; (8004298 <HAL_FMC_MspInit+0x114>)
800423a: f001 fb59 bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
800423e: 2328 movs r3, #40 ; 0x28
8004240: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004242: 2302 movs r3, #2
8004244: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004246: 2300 movs r3, #0
8004248: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800424a: 2303 movs r3, #3
800424c: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
800424e: 230c movs r3, #12
8004250: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
8004252: 1d3b adds r3, r7, #4
8004254: 4619 mov r1, r3
8004256: 4811 ldr r0, [pc, #68] ; (800429c <HAL_FMC_MspInit+0x118>)
8004258: f001 fb4a bl 80058f0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_3;
800425c: 2308 movs r3, #8
800425e: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8004260: 2302 movs r3, #2
8004262: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8004264: 2300 movs r3, #0
8004266: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8004268: 2303 movs r3, #3
800426a: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
800426c: 230c movs r3, #12
800426e: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8004270: 1d3b adds r3, r7, #4
8004272: 4619 mov r1, r3
8004274: 480a ldr r0, [pc, #40] ; (80042a0 <HAL_FMC_MspInit+0x11c>)
8004276: f001 fb3b bl 80058f0 <HAL_GPIO_Init>
800427a: e000 b.n 800427e <HAL_FMC_MspInit+0xfa>
return;
800427c: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
800427e: 3718 adds r7, #24
8004280: 46bd mov sp, r7
8004282: bd80 pop {r7, pc}
8004284: 200002ec .word 0x200002ec
8004288: 40023800 .word 0x40023800
800428c: 40021000 .word 0x40021000
8004290: 40021800 .word 0x40021800
8004294: 40020c00 .word 0x40020c00
8004298: 40021400 .word 0x40021400
800429c: 40021c00 .word 0x40021c00
80042a0: 40020800 .word 0x40020800
080042a4 <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
80042a4: b580 push {r7, lr}
80042a6: b082 sub sp, #8
80042a8: af00 add r7, sp, #0
80042aa: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
80042ac: f7ff ff6a bl 8004184 <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
80042b0: bf00 nop
80042b2: 3708 adds r7, #8
80042b4: 46bd mov sp, r7
80042b6: bd80 pop {r7, pc}
080042b8 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80042b8: b580 push {r7, lr}
80042ba: b08c sub sp, #48 ; 0x30
80042bc: af00 add r7, sp, #0
80042be: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
80042c0: 2300 movs r3, #0
80042c2: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
80042c4: 2300 movs r3, #0
80042c6: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
80042c8: 2200 movs r2, #0
80042ca: 6879 ldr r1, [r7, #4]
80042cc: 2036 movs r0, #54 ; 0x36
80042ce: f000 fdcf bl 8004e70 <HAL_NVIC_SetPriority>
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
80042d2: 2036 movs r0, #54 ; 0x36
80042d4: f000 fde8 bl 8004ea8 <HAL_NVIC_EnableIRQ>
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
80042d8: 4b1f ldr r3, [pc, #124] ; (8004358 <HAL_InitTick+0xa0>)
80042da: 6c1b ldr r3, [r3, #64] ; 0x40
80042dc: 4a1e ldr r2, [pc, #120] ; (8004358 <HAL_InitTick+0xa0>)
80042de: f043 0310 orr.w r3, r3, #16
80042e2: 6413 str r3, [r2, #64] ; 0x40
80042e4: 4b1c ldr r3, [pc, #112] ; (8004358 <HAL_InitTick+0xa0>)
80042e6: 6c1b ldr r3, [r3, #64] ; 0x40
80042e8: f003 0310 and.w r3, r3, #16
80042ec: 60fb str r3, [r7, #12]
80042ee: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
80042f0: f107 0210 add.w r2, r7, #16
80042f4: f107 0314 add.w r3, r7, #20
80042f8: 4611 mov r1, r2
80042fa: 4618 mov r0, r3
80042fc: f003 fbdc bl 8007ab8 <HAL_RCC_GetClockConfig>
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
8004300: f003 fbb2 bl 8007a68 <HAL_RCC_GetPCLK1Freq>
8004304: 4603 mov r3, r0
8004306: 005b lsls r3, r3, #1
8004308: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
800430a: 6afb ldr r3, [r7, #44] ; 0x2c
800430c: 4a13 ldr r2, [pc, #76] ; (800435c <HAL_InitTick+0xa4>)
800430e: fba2 2303 umull r2, r3, r2, r3
8004312: 0c9b lsrs r3, r3, #18
8004314: 3b01 subs r3, #1
8004316: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
8004318: 4b11 ldr r3, [pc, #68] ; (8004360 <HAL_InitTick+0xa8>)
800431a: 4a12 ldr r2, [pc, #72] ; (8004364 <HAL_InitTick+0xac>)
800431c: 601a str r2, [r3, #0]
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
800431e: 4b10 ldr r3, [pc, #64] ; (8004360 <HAL_InitTick+0xa8>)
8004320: f240 32e7 movw r2, #999 ; 0x3e7
8004324: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
8004326: 4a0e ldr r2, [pc, #56] ; (8004360 <HAL_InitTick+0xa8>)
8004328: 6abb ldr r3, [r7, #40] ; 0x28
800432a: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
800432c: 4b0c ldr r3, [pc, #48] ; (8004360 <HAL_InitTick+0xa8>)
800432e: 2200 movs r2, #0
8004330: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
8004332: 4b0b ldr r3, [pc, #44] ; (8004360 <HAL_InitTick+0xa8>)
8004334: 2200 movs r2, #0
8004336: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
8004338: 4809 ldr r0, [pc, #36] ; (8004360 <HAL_InitTick+0xa8>)
800433a: f004 fcb0 bl 8008c9e <HAL_TIM_Base_Init>
800433e: 4603 mov r3, r0
8004340: 2b00 cmp r3, #0
8004342: d104 bne.n 800434e <HAL_InitTick+0x96>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
8004344: 4806 ldr r0, [pc, #24] ; (8004360 <HAL_InitTick+0xa8>)
8004346: f004 fcd5 bl 8008cf4 <HAL_TIM_Base_Start_IT>
800434a: 4603 mov r3, r0
800434c: e000 b.n 8004350 <HAL_InitTick+0x98>
}
/* Return function status */
return HAL_ERROR;
800434e: 2301 movs r3, #1
}
8004350: 4618 mov r0, r3
8004352: 3730 adds r7, #48 ; 0x30
8004354: 46bd mov sp, r7
8004356: bd80 pop {r7, pc}
8004358: 40023800 .word 0x40023800
800435c: 431bde83 .word 0x431bde83
8004360: 20008ab4 .word 0x20008ab4
8004364: 40001000 .word 0x40001000
08004368 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8004368: b480 push {r7}
800436a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800436c: e7fe b.n 800436c <NMI_Handler+0x4>
0800436e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800436e: b480 push {r7}
8004370: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8004372: e7fe b.n 8004372 <HardFault_Handler+0x4>
08004374 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8004374: b480 push {r7}
8004376: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8004378: e7fe b.n 8004378 <MemManage_Handler+0x4>
0800437a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800437a: b480 push {r7}
800437c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800437e: e7fe b.n 800437e <BusFault_Handler+0x4>
08004380 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8004380: b480 push {r7}
8004382: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8004384: e7fe b.n 8004384 <UsageFault_Handler+0x4>
08004386 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8004386: b480 push {r7}
8004388: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800438a: bf00 nop
800438c: 46bd mov sp, r7
800438e: f85d 7b04 ldr.w r7, [sp], #4
8004392: 4770 bx lr
08004394 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
8004394: b580 push {r7, lr}
8004396: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_DAC_IRQHandler(&hdac);
8004398: 4803 ldr r0, [pc, #12] ; (80043a8 <TIM6_DAC_IRQHandler+0x14>)
800439a: f000 fdb5 bl 8004f08 <HAL_DAC_IRQHandler>
HAL_TIM_IRQHandler(&htim6);
800439e: 4803 ldr r0, [pc, #12] ; (80043ac <TIM6_DAC_IRQHandler+0x18>)
80043a0: f004 fd07 bl 8008db2 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
80043a4: bf00 nop
80043a6: bd80 pop {r7, pc}
80043a8: 20008830 .word 0x20008830
80043ac: 20008ab4 .word 0x20008ab4
080043b0 <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
80043b0: b580 push {r7, lr}
80043b2: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
80043b4: 4802 ldr r0, [pc, #8] ; (80043c0 <LTDC_IRQHandler+0x10>)
80043b6: f002 fc01 bl 8006bbc <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
80043ba: bf00 nop
80043bc: bd80 pop {r7, pc}
80043be: bf00 nop
80043c0: 20008678 .word 0x20008678
080043c4 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
80043c4: b580 push {r7, lr}
80043c6: b086 sub sp, #24
80043c8: af00 add r7, sp, #0
80043ca: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
80043cc: 4a14 ldr r2, [pc, #80] ; (8004420 <_sbrk+0x5c>)
80043ce: 4b15 ldr r3, [pc, #84] ; (8004424 <_sbrk+0x60>)
80043d0: 1ad3 subs r3, r2, r3
80043d2: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
80043d4: 697b ldr r3, [r7, #20]
80043d6: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
80043d8: 4b13 ldr r3, [pc, #76] ; (8004428 <_sbrk+0x64>)
80043da: 681b ldr r3, [r3, #0]
80043dc: 2b00 cmp r3, #0
80043de: d102 bne.n 80043e6 <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
80043e0: 4b11 ldr r3, [pc, #68] ; (8004428 <_sbrk+0x64>)
80043e2: 4a12 ldr r2, [pc, #72] ; (800442c <_sbrk+0x68>)
80043e4: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
80043e6: 4b10 ldr r3, [pc, #64] ; (8004428 <_sbrk+0x64>)
80043e8: 681a ldr r2, [r3, #0]
80043ea: 687b ldr r3, [r7, #4]
80043ec: 4413 add r3, r2
80043ee: 693a ldr r2, [r7, #16]
80043f0: 429a cmp r2, r3
80043f2: d207 bcs.n 8004404 <_sbrk+0x40>
{
errno = ENOMEM;
80043f4: f007 fbae bl 800bb54 <__errno>
80043f8: 4602 mov r2, r0
80043fa: 230c movs r3, #12
80043fc: 6013 str r3, [r2, #0]
return (void *)-1;
80043fe: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
8004402: e009 b.n 8004418 <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8004404: 4b08 ldr r3, [pc, #32] ; (8004428 <_sbrk+0x64>)
8004406: 681b ldr r3, [r3, #0]
8004408: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
800440a: 4b07 ldr r3, [pc, #28] ; (8004428 <_sbrk+0x64>)
800440c: 681a ldr r2, [r3, #0]
800440e: 687b ldr r3, [r7, #4]
8004410: 4413 add r3, r2
8004412: 4a05 ldr r2, [pc, #20] ; (8004428 <_sbrk+0x64>)
8004414: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8004416: 68fb ldr r3, [r7, #12]
}
8004418: 4618 mov r0, r3
800441a: 3718 adds r7, #24
800441c: 46bd mov sp, r7
800441e: bd80 pop {r7, pc}
8004420: 20050000 .word 0x20050000
8004424: 00000400 .word 0x00000400
8004428: 200002f0 .word 0x200002f0
800442c: 20008b00 .word 0x20008b00
08004430 <SystemInit>:
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
8004430: b480 push {r7}
8004432: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8004434: 4b08 ldr r3, [pc, #32] ; (8004458 <SystemInit+0x28>)
8004436: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800443a: 4a07 ldr r2, [pc, #28] ; (8004458 <SystemInit+0x28>)
800443c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8004440: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8004444: 4b04 ldr r3, [pc, #16] ; (8004458 <SystemInit+0x28>)
8004446: f04f 6200 mov.w r2, #134217728 ; 0x8000000
800444a: 609a str r2, [r3, #8]
#endif
}
800444c: bf00 nop
800444e: 46bd mov sp, r7
8004450: f85d 7b04 ldr.w r7, [sp], #4
8004454: 4770 bx lr
8004456: bf00 nop
8004458: e000ed00 .word 0xe000ed00
0800445c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
800445c: f8df d034 ldr.w sp, [pc, #52] ; 8004494 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8004460: 2100 movs r1, #0
b LoopCopyDataInit
8004462: e003 b.n 800446c <LoopCopyDataInit>
08004464 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8004464: 4b0c ldr r3, [pc, #48] ; (8004498 <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
8004466: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8004468: 5043 str r3, [r0, r1]
adds r1, r1, #4
800446a: 3104 adds r1, #4
0800446c <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
800446c: 480b ldr r0, [pc, #44] ; (800449c <LoopFillZerobss+0x1c>)
ldr r3, =_edata
800446e: 4b0c ldr r3, [pc, #48] ; (80044a0 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8004470: 1842 adds r2, r0, r1
cmp r2, r3
8004472: 429a cmp r2, r3
bcc CopyDataInit
8004474: d3f6 bcc.n 8004464 <CopyDataInit>
ldr r2, =_sbss
8004476: 4a0b ldr r2, [pc, #44] ; (80044a4 <LoopFillZerobss+0x24>)
b LoopFillZerobss
8004478: e002 b.n 8004480 <LoopFillZerobss>
0800447a <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800447a: 2300 movs r3, #0
str r3, [r2], #4
800447c: f842 3b04 str.w r3, [r2], #4
08004480 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8004480: 4b09 ldr r3, [pc, #36] ; (80044a8 <LoopFillZerobss+0x28>)
cmp r2, r3
8004482: 429a cmp r2, r3
bcc FillZerobss
8004484: d3f9 bcc.n 800447a <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8004486: f7ff ffd3 bl 8004430 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800448a: f007 fb69 bl 800bb60 <__libc_init_array>
/* Call the application's entry point.*/
bl main
800448e: f7fc fb43 bl 8000b18 <main>
bx lr
8004492: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8004494: 20050000 .word 0x20050000
ldr r3, =_sidata
8004498: 0800e3d4 .word 0x0800e3d4
ldr r0, =_sdata
800449c: 20000000 .word 0x20000000
ldr r3, =_edata
80044a0: 200000b0 .word 0x200000b0
ldr r2, =_sbss
80044a4: 200000b0 .word 0x200000b0
ldr r3, = _ebss
80044a8: 20008afc .word 0x20008afc
080044ac <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80044ac: e7fe b.n 80044ac <ADC_IRQHandler>
080044ae <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80044ae: b580 push {r7, lr}
80044b0: af00 add r7, sp, #0
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80044b2: 2003 movs r0, #3
80044b4: f000 fcd1 bl 8004e5a <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80044b8: 2000 movs r0, #0
80044ba: f7ff fefd bl 80042b8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80044be: f7ff f9c9 bl 8003854 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80044c2: 2300 movs r3, #0
}
80044c4: 4618 mov r0, r3
80044c6: bd80 pop {r7, pc}
080044c8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80044c8: b480 push {r7}
80044ca: af00 add r7, sp, #0
uwTick += uwTickFreq;
80044cc: 4b06 ldr r3, [pc, #24] ; (80044e8 <HAL_IncTick+0x20>)
80044ce: 781b ldrb r3, [r3, #0]
80044d0: 461a mov r2, r3
80044d2: 4b06 ldr r3, [pc, #24] ; (80044ec <HAL_IncTick+0x24>)
80044d4: 681b ldr r3, [r3, #0]
80044d6: 4413 add r3, r2
80044d8: 4a04 ldr r2, [pc, #16] ; (80044ec <HAL_IncTick+0x24>)
80044da: 6013 str r3, [r2, #0]
}
80044dc: bf00 nop
80044de: 46bd mov sp, r7
80044e0: f85d 7b04 ldr.w r7, [sp], #4
80044e4: 4770 bx lr
80044e6: bf00 nop
80044e8: 20000044 .word 0x20000044
80044ec: 20008af4 .word 0x20008af4
080044f0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80044f0: b480 push {r7}
80044f2: af00 add r7, sp, #0
return uwTick;
80044f4: 4b03 ldr r3, [pc, #12] ; (8004504 <HAL_GetTick+0x14>)
80044f6: 681b ldr r3, [r3, #0]
}
80044f8: 4618 mov r0, r3
80044fa: 46bd mov sp, r7
80044fc: f85d 7b04 ldr.w r7, [sp], #4
8004500: 4770 bx lr
8004502: bf00 nop
8004504: 20008af4 .word 0x20008af4
08004508 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8004508: b580 push {r7, lr}
800450a: b084 sub sp, #16
800450c: af00 add r7, sp, #0
800450e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8004510: f7ff ffee bl 80044f0 <HAL_GetTick>
8004514: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8004516: 687b ldr r3, [r7, #4]
8004518: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
800451a: 68fb ldr r3, [r7, #12]
800451c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8004520: d005 beq.n 800452e <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8004522: 4b09 ldr r3, [pc, #36] ; (8004548 <HAL_Delay+0x40>)
8004524: 781b ldrb r3, [r3, #0]
8004526: 461a mov r2, r3
8004528: 68fb ldr r3, [r7, #12]
800452a: 4413 add r3, r2
800452c: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
800452e: bf00 nop
8004530: f7ff ffde bl 80044f0 <HAL_GetTick>
8004534: 4602 mov r2, r0
8004536: 68bb ldr r3, [r7, #8]
8004538: 1ad3 subs r3, r2, r3
800453a: 68fa ldr r2, [r7, #12]
800453c: 429a cmp r2, r3
800453e: d8f7 bhi.n 8004530 <HAL_Delay+0x28>
{
}
}
8004540: bf00 nop
8004542: 3710 adds r7, #16
8004544: 46bd mov sp, r7
8004546: bd80 pop {r7, pc}
8004548: 20000044 .word 0x20000044
0800454c <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
800454c: b580 push {r7, lr}
800454e: b084 sub sp, #16
8004550: af00 add r7, sp, #0
8004552: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8004554: 2300 movs r3, #0
8004556: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
8004558: 687b ldr r3, [r7, #4]
800455a: 2b00 cmp r3, #0
800455c: d101 bne.n 8004562 <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
800455e: 2301 movs r3, #1
8004560: e031 b.n 80045c6 <HAL_ADC_Init+0x7a>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8004562: 687b ldr r3, [r7, #4]
8004564: 6c1b ldr r3, [r3, #64] ; 0x40
8004566: 2b00 cmp r3, #0
8004568: d109 bne.n 800457e <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
800456a: 6878 ldr r0, [r7, #4]
800456c: f7ff f99a bl 80038a4 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8004570: 687b ldr r3, [r7, #4]
8004572: 2200 movs r2, #0
8004574: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8004576: 687b ldr r3, [r7, #4]
8004578: 2200 movs r2, #0
800457a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
800457e: 687b ldr r3, [r7, #4]
8004580: 6c1b ldr r3, [r3, #64] ; 0x40
8004582: f003 0310 and.w r3, r3, #16
8004586: 2b00 cmp r3, #0
8004588: d116 bne.n 80045b8 <HAL_ADC_Init+0x6c>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800458a: 687b ldr r3, [r7, #4]
800458c: 6c1a ldr r2, [r3, #64] ; 0x40
800458e: 4b10 ldr r3, [pc, #64] ; (80045d0 <HAL_ADC_Init+0x84>)
8004590: 4013 ands r3, r2
8004592: f043 0202 orr.w r2, r3, #2
8004596: 687b ldr r3, [r7, #4]
8004598: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
800459a: 6878 ldr r0, [r7, #4]
800459c: f000 fab6 bl 8004b0c <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
80045a0: 687b ldr r3, [r7, #4]
80045a2: 2200 movs r2, #0
80045a4: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
80045a6: 687b ldr r3, [r7, #4]
80045a8: 6c1b ldr r3, [r3, #64] ; 0x40
80045aa: f023 0303 bic.w r3, r3, #3
80045ae: f043 0201 orr.w r2, r3, #1
80045b2: 687b ldr r3, [r7, #4]
80045b4: 641a str r2, [r3, #64] ; 0x40
80045b6: e001 b.n 80045bc <HAL_ADC_Init+0x70>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
80045b8: 2301 movs r3, #1
80045ba: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
80045bc: 687b ldr r3, [r7, #4]
80045be: 2200 movs r2, #0
80045c0: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
80045c4: 7bfb ldrb r3, [r7, #15]
}
80045c6: 4618 mov r0, r3
80045c8: 3710 adds r7, #16
80045ca: 46bd mov sp, r7
80045cc: bd80 pop {r7, pc}
80045ce: bf00 nop
80045d0: ffffeefd .word 0xffffeefd
080045d4 <HAL_ADC_Start>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
80045d4: b480 push {r7}
80045d6: b085 sub sp, #20
80045d8: af00 add r7, sp, #0
80045da: 6078 str r0, [r7, #4]
__IO uint32_t counter = 0;
80045dc: 2300 movs r3, #0
80045de: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
80045e0: 687b ldr r3, [r7, #4]
80045e2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80045e6: 2b01 cmp r3, #1
80045e8: d101 bne.n 80045ee <HAL_ADC_Start+0x1a>
80045ea: 2302 movs r3, #2
80045ec: e0a0 b.n 8004730 <HAL_ADC_Start+0x15c>
80045ee: 687b ldr r3, [r7, #4]
80045f0: 2201 movs r2, #1
80045f2: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
80045f6: 687b ldr r3, [r7, #4]
80045f8: 681b ldr r3, [r3, #0]
80045fa: 689b ldr r3, [r3, #8]
80045fc: f003 0301 and.w r3, r3, #1
8004600: 2b01 cmp r3, #1
8004602: d018 beq.n 8004636 <HAL_ADC_Start+0x62>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8004604: 687b ldr r3, [r7, #4]
8004606: 681b ldr r3, [r3, #0]
8004608: 689a ldr r2, [r3, #8]
800460a: 687b ldr r3, [r7, #4]
800460c: 681b ldr r3, [r3, #0]
800460e: f042 0201 orr.w r2, r2, #1
8004612: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
8004614: 4b49 ldr r3, [pc, #292] ; (800473c <HAL_ADC_Start+0x168>)
8004616: 681b ldr r3, [r3, #0]
8004618: 4a49 ldr r2, [pc, #292] ; (8004740 <HAL_ADC_Start+0x16c>)
800461a: fba2 2303 umull r2, r3, r2, r3
800461e: 0c9a lsrs r2, r3, #18
8004620: 4613 mov r3, r2
8004622: 005b lsls r3, r3, #1
8004624: 4413 add r3, r2
8004626: 60fb str r3, [r7, #12]
while(counter != 0)
8004628: e002 b.n 8004630 <HAL_ADC_Start+0x5c>
{
counter--;
800462a: 68fb ldr r3, [r7, #12]
800462c: 3b01 subs r3, #1
800462e: 60fb str r3, [r7, #12]
while(counter != 0)
8004630: 68fb ldr r3, [r7, #12]
8004632: 2b00 cmp r3, #0
8004634: d1f9 bne.n 800462a <HAL_ADC_Start+0x56>
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
8004636: 687b ldr r3, [r7, #4]
8004638: 681b ldr r3, [r3, #0]
800463a: 689b ldr r3, [r3, #8]
800463c: f003 0301 and.w r3, r3, #1
8004640: 2b01 cmp r3, #1
8004642: d174 bne.n 800472e <HAL_ADC_Start+0x15a>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
8004644: 687b ldr r3, [r7, #4]
8004646: 6c1a ldr r2, [r3, #64] ; 0x40
8004648: 4b3e ldr r3, [pc, #248] ; (8004744 <HAL_ADC_Start+0x170>)
800464a: 4013 ands r3, r2
800464c: f443 7280 orr.w r2, r3, #256 ; 0x100
8004650: 687b ldr r3, [r7, #4]
8004652: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
8004654: 687b ldr r3, [r7, #4]
8004656: 681b ldr r3, [r3, #0]
8004658: 685b ldr r3, [r3, #4]
800465a: f403 6380 and.w r3, r3, #1024 ; 0x400
800465e: 2b00 cmp r3, #0
8004660: d007 beq.n 8004672 <HAL_ADC_Start+0x9e>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
8004662: 687b ldr r3, [r7, #4]
8004664: 6c1b ldr r3, [r3, #64] ; 0x40
8004666: f423 5340 bic.w r3, r3, #12288 ; 0x3000
800466a: f443 5280 orr.w r2, r3, #4096 ; 0x1000
800466e: 687b ldr r3, [r7, #4]
8004670: 641a str r2, [r3, #64] ; 0x40
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8004672: 687b ldr r3, [r7, #4]
8004674: 6c1b ldr r3, [r3, #64] ; 0x40
8004676: f403 5380 and.w r3, r3, #4096 ; 0x1000
800467a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800467e: d106 bne.n 800468e <HAL_ADC_Start+0xba>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8004680: 687b ldr r3, [r7, #4]
8004682: 6c5b ldr r3, [r3, #68] ; 0x44
8004684: f023 0206 bic.w r2, r3, #6
8004688: 687b ldr r3, [r7, #4]
800468a: 645a str r2, [r3, #68] ; 0x44
800468c: e002 b.n 8004694 <HAL_ADC_Start+0xc0>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
800468e: 687b ldr r3, [r7, #4]
8004690: 2200 movs r2, #0
8004692: 645a str r2, [r3, #68] ; 0x44
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8004694: 687b ldr r3, [r7, #4]
8004696: 2200 movs r2, #0
8004698: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
800469c: 687b ldr r3, [r7, #4]
800469e: 681b ldr r3, [r3, #0]
80046a0: f06f 0222 mvn.w r2, #34 ; 0x22
80046a4: 601a str r2, [r3, #0]
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
80046a6: 4b28 ldr r3, [pc, #160] ; (8004748 <HAL_ADC_Start+0x174>)
80046a8: 685b ldr r3, [r3, #4]
80046aa: f003 031f and.w r3, r3, #31
80046ae: 2b00 cmp r3, #0
80046b0: d10f bne.n 80046d2 <HAL_ADC_Start+0xfe>
{
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
80046b2: 687b ldr r3, [r7, #4]
80046b4: 681b ldr r3, [r3, #0]
80046b6: 689b ldr r3, [r3, #8]
80046b8: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80046bc: 2b00 cmp r3, #0
80046be: d136 bne.n 800472e <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
80046c0: 687b ldr r3, [r7, #4]
80046c2: 681b ldr r3, [r3, #0]
80046c4: 689a ldr r2, [r3, #8]
80046c6: 687b ldr r3, [r7, #4]
80046c8: 681b ldr r3, [r3, #0]
80046ca: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
80046ce: 609a str r2, [r3, #8]
80046d0: e02d b.n 800472e <HAL_ADC_Start+0x15a>
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
80046d2: 687b ldr r3, [r7, #4]
80046d4: 681b ldr r3, [r3, #0]
80046d6: 4a1d ldr r2, [pc, #116] ; (800474c <HAL_ADC_Start+0x178>)
80046d8: 4293 cmp r3, r2
80046da: d10e bne.n 80046fa <HAL_ADC_Start+0x126>
80046dc: 687b ldr r3, [r7, #4]
80046de: 681b ldr r3, [r3, #0]
80046e0: 689b ldr r3, [r3, #8]
80046e2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80046e6: 2b00 cmp r3, #0
80046e8: d107 bne.n 80046fa <HAL_ADC_Start+0x126>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
80046ea: 687b ldr r3, [r7, #4]
80046ec: 681b ldr r3, [r3, #0]
80046ee: 689a ldr r2, [r3, #8]
80046f0: 687b ldr r3, [r7, #4]
80046f2: 681b ldr r3, [r3, #0]
80046f4: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
80046f8: 609a str r2, [r3, #8]
}
/* if dual mode is selected, ADC3 works independently. */
/* check if the mode selected is not triple */
if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) )
80046fa: 4b13 ldr r3, [pc, #76] ; (8004748 <HAL_ADC_Start+0x174>)
80046fc: 685b ldr r3, [r3, #4]
80046fe: f003 0310 and.w r3, r3, #16
8004702: 2b00 cmp r3, #0
8004704: d113 bne.n 800472e <HAL_ADC_Start+0x15a>
{
/* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8004706: 687b ldr r3, [r7, #4]
8004708: 681b ldr r3, [r3, #0]
800470a: 4a11 ldr r2, [pc, #68] ; (8004750 <HAL_ADC_Start+0x17c>)
800470c: 4293 cmp r3, r2
800470e: d10e bne.n 800472e <HAL_ADC_Start+0x15a>
8004710: 687b ldr r3, [r7, #4]
8004712: 681b ldr r3, [r3, #0]
8004714: 689b ldr r3, [r3, #8]
8004716: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
800471a: 2b00 cmp r3, #0
800471c: d107 bne.n 800472e <HAL_ADC_Start+0x15a>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
800471e: 687b ldr r3, [r7, #4]
8004720: 681b ldr r3, [r3, #0]
8004722: 689a ldr r2, [r3, #8]
8004724: 687b ldr r3, [r7, #4]
8004726: 681b ldr r3, [r3, #0]
8004728: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
800472c: 609a str r2, [r3, #8]
}
}
}
/* Return function status */
return HAL_OK;
800472e: 2300 movs r3, #0
}
8004730: 4618 mov r0, r3
8004732: 3714 adds r7, #20
8004734: 46bd mov sp, r7
8004736: f85d 7b04 ldr.w r7, [sp], #4
800473a: 4770 bx lr
800473c: 2000003c .word 0x2000003c
8004740: 431bde83 .word 0x431bde83
8004744: fffff8fe .word 0xfffff8fe
8004748: 40012300 .word 0x40012300
800474c: 40012000 .word 0x40012000
8004750: 40012200 .word 0x40012200
08004754 <HAL_ADC_PollForConversion>:
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
8004754: b580 push {r7, lr}
8004756: b084 sub sp, #16
8004758: af00 add r7, sp, #0
800475a: 6078 str r0, [r7, #4]
800475c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
800475e: 2300 movs r3, #0
8004760: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8004762: 687b ldr r3, [r7, #4]
8004764: 681b ldr r3, [r3, #0]
8004766: 689b ldr r3, [r3, #8]
8004768: f403 6380 and.w r3, r3, #1024 ; 0x400
800476c: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8004770: d113 bne.n 800479a <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
8004772: 687b ldr r3, [r7, #4]
8004774: 681b ldr r3, [r3, #0]
8004776: 689b ldr r3, [r3, #8]
8004778: f403 7380 and.w r3, r3, #256 ; 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
800477c: f5b3 7f80 cmp.w r3, #256 ; 0x100
8004780: d10b bne.n 800479a <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8004782: 687b ldr r3, [r7, #4]
8004784: 6c1b ldr r3, [r3, #64] ; 0x40
8004786: f043 0220 orr.w r2, r3, #32
800478a: 687b ldr r3, [r7, #4]
800478c: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
800478e: 687b ldr r3, [r7, #4]
8004790: 2200 movs r2, #0
8004792: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8004796: 2301 movs r3, #1
8004798: e05c b.n 8004854 <HAL_ADC_PollForConversion+0x100>
}
/* Get tick */
tickstart = HAL_GetTick();
800479a: f7ff fea9 bl 80044f0 <HAL_GetTick>
800479e: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
80047a0: e01a b.n 80047d8 <HAL_ADC_PollForConversion+0x84>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
80047a2: 683b ldr r3, [r7, #0]
80047a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80047a8: d016 beq.n 80047d8 <HAL_ADC_PollForConversion+0x84>
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
80047aa: 683b ldr r3, [r7, #0]
80047ac: 2b00 cmp r3, #0
80047ae: d007 beq.n 80047c0 <HAL_ADC_PollForConversion+0x6c>
80047b0: f7ff fe9e bl 80044f0 <HAL_GetTick>
80047b4: 4602 mov r2, r0
80047b6: 68fb ldr r3, [r7, #12]
80047b8: 1ad3 subs r3, r2, r3
80047ba: 683a ldr r2, [r7, #0]
80047bc: 429a cmp r2, r3
80047be: d20b bcs.n 80047d8 <HAL_ADC_PollForConversion+0x84>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
80047c0: 687b ldr r3, [r7, #4]
80047c2: 6c1b ldr r3, [r3, #64] ; 0x40
80047c4: f043 0204 orr.w r2, r3, #4
80047c8: 687b ldr r3, [r7, #4]
80047ca: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
80047cc: 687b ldr r3, [r7, #4]
80047ce: 2200 movs r2, #0
80047d0: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
80047d4: 2303 movs r3, #3
80047d6: e03d b.n 8004854 <HAL_ADC_PollForConversion+0x100>
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
80047d8: 687b ldr r3, [r7, #4]
80047da: 681b ldr r3, [r3, #0]
80047dc: 681b ldr r3, [r3, #0]
80047de: f003 0302 and.w r3, r3, #2
80047e2: 2b02 cmp r3, #2
80047e4: d1dd bne.n 80047a2 <HAL_ADC_PollForConversion+0x4e>
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
80047e6: 687b ldr r3, [r7, #4]
80047e8: 681b ldr r3, [r3, #0]
80047ea: f06f 0212 mvn.w r2, #18
80047ee: 601a str r2, [r3, #0]
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
80047f0: 687b ldr r3, [r7, #4]
80047f2: 6c1b ldr r3, [r3, #64] ; 0x40
80047f4: f443 7200 orr.w r2, r3, #512 ; 0x200
80047f8: 687b ldr r3, [r7, #4]
80047fa: 641a str r2, [r3, #64] ; 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F7, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
80047fc: 687b ldr r3, [r7, #4]
80047fe: 681b ldr r3, [r3, #0]
8004800: 689b ldr r3, [r3, #8]
8004802: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8004806: 2b00 cmp r3, #0
8004808: d123 bne.n 8004852 <HAL_ADC_PollForConversion+0xfe>
(hadc->Init.ContinuousConvMode == DISABLE) &&
800480a: 687b ldr r3, [r7, #4]
800480c: 699b ldr r3, [r3, #24]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
800480e: 2b00 cmp r3, #0
8004810: d11f bne.n 8004852 <HAL_ADC_PollForConversion+0xfe>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8004812: 687b ldr r3, [r7, #4]
8004814: 681b ldr r3, [r3, #0]
8004816: 6adb ldr r3, [r3, #44] ; 0x2c
8004818: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
800481c: 2b00 cmp r3, #0
800481e: d006 beq.n 800482e <HAL_ADC_PollForConversion+0xda>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
8004820: 687b ldr r3, [r7, #4]
8004822: 681b ldr r3, [r3, #0]
8004824: 689b ldr r3, [r3, #8]
8004826: f403 6380 and.w r3, r3, #1024 ; 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
800482a: 2b00 cmp r3, #0
800482c: d111 bne.n 8004852 <HAL_ADC_PollForConversion+0xfe>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
800482e: 687b ldr r3, [r7, #4]
8004830: 6c1b ldr r3, [r3, #64] ; 0x40
8004832: f423 7280 bic.w r2, r3, #256 ; 0x100
8004836: 687b ldr r3, [r7, #4]
8004838: 641a str r2, [r3, #64] ; 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
800483a: 687b ldr r3, [r7, #4]
800483c: 6c1b ldr r3, [r3, #64] ; 0x40
800483e: f403 5380 and.w r3, r3, #4096 ; 0x1000
8004842: 2b00 cmp r3, #0
8004844: d105 bne.n 8004852 <HAL_ADC_PollForConversion+0xfe>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8004846: 687b ldr r3, [r7, #4]
8004848: 6c1b ldr r3, [r3, #64] ; 0x40
800484a: f043 0201 orr.w r2, r3, #1
800484e: 687b ldr r3, [r7, #4]
8004850: 641a str r2, [r3, #64] ; 0x40
}
}
/* Return ADC state */
return HAL_OK;
8004852: 2300 movs r3, #0
}
8004854: 4618 mov r0, r3
8004856: 3710 adds r7, #16
8004858: 46bd mov sp, r7
800485a: bd80 pop {r7, pc}
0800485c <HAL_ADC_GetValue>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
800485c: b480 push {r7}
800485e: b083 sub sp, #12
8004860: af00 add r7, sp, #0
8004862: 6078 str r0, [r7, #4]
/* Return the selected ADC converted value */
return hadc->Instance->DR;
8004864: 687b ldr r3, [r7, #4]
8004866: 681b ldr r3, [r3, #0]
8004868: 6cdb ldr r3, [r3, #76] ; 0x4c
}
800486a: 4618 mov r0, r3
800486c: 370c adds r7, #12
800486e: 46bd mov sp, r7
8004870: f85d 7b04 ldr.w r7, [sp], #4
8004874: 4770 bx lr
...
08004878 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8004878: b480 push {r7}
800487a: b085 sub sp, #20
800487c: af00 add r7, sp, #0
800487e: 6078 str r0, [r7, #4]
8004880: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0;
8004882: 2300 movs r3, #0
8004884: 60fb str r3, [r7, #12]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8004886: 687b ldr r3, [r7, #4]
8004888: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800488c: 2b01 cmp r3, #1
800488e: d101 bne.n 8004894 <HAL_ADC_ConfigChannel+0x1c>
8004890: 2302 movs r3, #2
8004892: e12a b.n 8004aea <HAL_ADC_ConfigChannel+0x272>
8004894: 687b ldr r3, [r7, #4]
8004896: 2201 movs r2, #1
8004898: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE))
800489c: 683b ldr r3, [r7, #0]
800489e: 681b ldr r3, [r3, #0]
80048a0: 2b09 cmp r3, #9
80048a2: d93a bls.n 800491a <HAL_ADC_ConfigChannel+0xa2>
80048a4: 683b ldr r3, [r7, #0]
80048a6: 681b ldr r3, [r3, #0]
80048a8: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
80048ac: d035 beq.n 800491a <HAL_ADC_ConfigChannel+0xa2>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
80048ae: 687b ldr r3, [r7, #4]
80048b0: 681b ldr r3, [r3, #0]
80048b2: 68d9 ldr r1, [r3, #12]
80048b4: 683b ldr r3, [r7, #0]
80048b6: 681b ldr r3, [r3, #0]
80048b8: b29b uxth r3, r3
80048ba: 461a mov r2, r3
80048bc: 4613 mov r3, r2
80048be: 005b lsls r3, r3, #1
80048c0: 4413 add r3, r2
80048c2: 3b1e subs r3, #30
80048c4: 2207 movs r2, #7
80048c6: fa02 f303 lsl.w r3, r2, r3
80048ca: 43da mvns r2, r3
80048cc: 687b ldr r3, [r7, #4]
80048ce: 681b ldr r3, [r3, #0]
80048d0: 400a ands r2, r1
80048d2: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80048d4: 683b ldr r3, [r7, #0]
80048d6: 681b ldr r3, [r3, #0]
80048d8: 4a87 ldr r2, [pc, #540] ; (8004af8 <HAL_ADC_ConfigChannel+0x280>)
80048da: 4293 cmp r3, r2
80048dc: d10a bne.n 80048f4 <HAL_ADC_ConfigChannel+0x7c>
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18);
80048de: 687b ldr r3, [r7, #4]
80048e0: 681b ldr r3, [r3, #0]
80048e2: 68d9 ldr r1, [r3, #12]
80048e4: 683b ldr r3, [r7, #0]
80048e6: 689b ldr r3, [r3, #8]
80048e8: 061a lsls r2, r3, #24
80048ea: 687b ldr r3, [r7, #4]
80048ec: 681b ldr r3, [r3, #0]
80048ee: 430a orrs r2, r1
80048f0: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
80048f2: e035 b.n 8004960 <HAL_ADC_ConfigChannel+0xe8>
}
else
{
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
80048f4: 687b ldr r3, [r7, #4]
80048f6: 681b ldr r3, [r3, #0]
80048f8: 68d9 ldr r1, [r3, #12]
80048fa: 683b ldr r3, [r7, #0]
80048fc: 689a ldr r2, [r3, #8]
80048fe: 683b ldr r3, [r7, #0]
8004900: 681b ldr r3, [r3, #0]
8004902: b29b uxth r3, r3
8004904: 4618 mov r0, r3
8004906: 4603 mov r3, r0
8004908: 005b lsls r3, r3, #1
800490a: 4403 add r3, r0
800490c: 3b1e subs r3, #30
800490e: 409a lsls r2, r3
8004910: 687b ldr r3, [r7, #4]
8004912: 681b ldr r3, [r3, #0]
8004914: 430a orrs r2, r1
8004916: 60da str r2, [r3, #12]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004918: e022 b.n 8004960 <HAL_ADC_ConfigChannel+0xe8>
}
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
800491a: 687b ldr r3, [r7, #4]
800491c: 681b ldr r3, [r3, #0]
800491e: 6919 ldr r1, [r3, #16]
8004920: 683b ldr r3, [r7, #0]
8004922: 681b ldr r3, [r3, #0]
8004924: b29b uxth r3, r3
8004926: 461a mov r2, r3
8004928: 4613 mov r3, r2
800492a: 005b lsls r3, r3, #1
800492c: 4413 add r3, r2
800492e: 2207 movs r2, #7
8004930: fa02 f303 lsl.w r3, r2, r3
8004934: 43da mvns r2, r3
8004936: 687b ldr r3, [r7, #4]
8004938: 681b ldr r3, [r3, #0]
800493a: 400a ands r2, r1
800493c: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
800493e: 687b ldr r3, [r7, #4]
8004940: 681b ldr r3, [r3, #0]
8004942: 6919 ldr r1, [r3, #16]
8004944: 683b ldr r3, [r7, #0]
8004946: 689a ldr r2, [r3, #8]
8004948: 683b ldr r3, [r7, #0]
800494a: 681b ldr r3, [r3, #0]
800494c: b29b uxth r3, r3
800494e: 4618 mov r0, r3
8004950: 4603 mov r3, r0
8004952: 005b lsls r3, r3, #1
8004954: 4403 add r3, r0
8004956: 409a lsls r2, r3
8004958: 687b ldr r3, [r7, #4]
800495a: 681b ldr r3, [r3, #0]
800495c: 430a orrs r2, r1
800495e: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
8004960: 683b ldr r3, [r7, #0]
8004962: 685b ldr r3, [r3, #4]
8004964: 2b06 cmp r3, #6
8004966: d824 bhi.n 80049b2 <HAL_ADC_ConfigChannel+0x13a>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8004968: 687b ldr r3, [r7, #4]
800496a: 681b ldr r3, [r3, #0]
800496c: 6b59 ldr r1, [r3, #52] ; 0x34
800496e: 683b ldr r3, [r7, #0]
8004970: 685a ldr r2, [r3, #4]
8004972: 4613 mov r3, r2
8004974: 009b lsls r3, r3, #2
8004976: 4413 add r3, r2
8004978: 3b05 subs r3, #5
800497a: 221f movs r2, #31
800497c: fa02 f303 lsl.w r3, r2, r3
8004980: 43da mvns r2, r3
8004982: 687b ldr r3, [r7, #4]
8004984: 681b ldr r3, [r3, #0]
8004986: 400a ands r2, r1
8004988: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
800498a: 687b ldr r3, [r7, #4]
800498c: 681b ldr r3, [r3, #0]
800498e: 6b59 ldr r1, [r3, #52] ; 0x34
8004990: 683b ldr r3, [r7, #0]
8004992: 681b ldr r3, [r3, #0]
8004994: b29b uxth r3, r3
8004996: 4618 mov r0, r3
8004998: 683b ldr r3, [r7, #0]
800499a: 685a ldr r2, [r3, #4]
800499c: 4613 mov r3, r2
800499e: 009b lsls r3, r3, #2
80049a0: 4413 add r3, r2
80049a2: 3b05 subs r3, #5
80049a4: fa00 f203 lsl.w r2, r0, r3
80049a8: 687b ldr r3, [r7, #4]
80049aa: 681b ldr r3, [r3, #0]
80049ac: 430a orrs r2, r1
80049ae: 635a str r2, [r3, #52] ; 0x34
80049b0: e04c b.n 8004a4c <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
80049b2: 683b ldr r3, [r7, #0]
80049b4: 685b ldr r3, [r3, #4]
80049b6: 2b0c cmp r3, #12
80049b8: d824 bhi.n 8004a04 <HAL_ADC_ConfigChannel+0x18c>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
80049ba: 687b ldr r3, [r7, #4]
80049bc: 681b ldr r3, [r3, #0]
80049be: 6b19 ldr r1, [r3, #48] ; 0x30
80049c0: 683b ldr r3, [r7, #0]
80049c2: 685a ldr r2, [r3, #4]
80049c4: 4613 mov r3, r2
80049c6: 009b lsls r3, r3, #2
80049c8: 4413 add r3, r2
80049ca: 3b23 subs r3, #35 ; 0x23
80049cc: 221f movs r2, #31
80049ce: fa02 f303 lsl.w r3, r2, r3
80049d2: 43da mvns r2, r3
80049d4: 687b ldr r3, [r7, #4]
80049d6: 681b ldr r3, [r3, #0]
80049d8: 400a ands r2, r1
80049da: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
80049dc: 687b ldr r3, [r7, #4]
80049de: 681b ldr r3, [r3, #0]
80049e0: 6b19 ldr r1, [r3, #48] ; 0x30
80049e2: 683b ldr r3, [r7, #0]
80049e4: 681b ldr r3, [r3, #0]
80049e6: b29b uxth r3, r3
80049e8: 4618 mov r0, r3
80049ea: 683b ldr r3, [r7, #0]
80049ec: 685a ldr r2, [r3, #4]
80049ee: 4613 mov r3, r2
80049f0: 009b lsls r3, r3, #2
80049f2: 4413 add r3, r2
80049f4: 3b23 subs r3, #35 ; 0x23
80049f6: fa00 f203 lsl.w r2, r0, r3
80049fa: 687b ldr r3, [r7, #4]
80049fc: 681b ldr r3, [r3, #0]
80049fe: 430a orrs r2, r1
8004a00: 631a str r2, [r3, #48] ; 0x30
8004a02: e023 b.n 8004a4c <HAL_ADC_ConfigChannel+0x1d4>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
8004a04: 687b ldr r3, [r7, #4]
8004a06: 681b ldr r3, [r3, #0]
8004a08: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004a0a: 683b ldr r3, [r7, #0]
8004a0c: 685a ldr r2, [r3, #4]
8004a0e: 4613 mov r3, r2
8004a10: 009b lsls r3, r3, #2
8004a12: 4413 add r3, r2
8004a14: 3b41 subs r3, #65 ; 0x41
8004a16: 221f movs r2, #31
8004a18: fa02 f303 lsl.w r3, r2, r3
8004a1c: 43da mvns r2, r3
8004a1e: 687b ldr r3, [r7, #4]
8004a20: 681b ldr r3, [r3, #0]
8004a22: 400a ands r2, r1
8004a24: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8004a26: 687b ldr r3, [r7, #4]
8004a28: 681b ldr r3, [r3, #0]
8004a2a: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004a2c: 683b ldr r3, [r7, #0]
8004a2e: 681b ldr r3, [r3, #0]
8004a30: b29b uxth r3, r3
8004a32: 4618 mov r0, r3
8004a34: 683b ldr r3, [r7, #0]
8004a36: 685a ldr r2, [r3, #4]
8004a38: 4613 mov r3, r2
8004a3a: 009b lsls r3, r3, #2
8004a3c: 4413 add r3, r2
8004a3e: 3b41 subs r3, #65 ; 0x41
8004a40: fa00 f203 lsl.w r2, r0, r3
8004a44: 687b ldr r3, [r7, #4]
8004a46: 681b ldr r3, [r3, #0]
8004a48: 430a orrs r2, r1
8004a4a: 62da str r2, [r3, #44] ; 0x2c
}
/* if no internal channel selected */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE))
8004a4c: 687b ldr r3, [r7, #4]
8004a4e: 681b ldr r3, [r3, #0]
8004a50: 4a2a ldr r2, [pc, #168] ; (8004afc <HAL_ADC_ConfigChannel+0x284>)
8004a52: 4293 cmp r3, r2
8004a54: d10a bne.n 8004a6c <HAL_ADC_ConfigChannel+0x1f4>
8004a56: 683b ldr r3, [r7, #0]
8004a58: 681b ldr r3, [r3, #0]
8004a5a: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000
8004a5e: d105 bne.n 8004a6c <HAL_ADC_ConfigChannel+0x1f4>
{
/* Disable the VBAT & TSVREFE channel*/
ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE);
8004a60: 4b27 ldr r3, [pc, #156] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004a62: 685b ldr r3, [r3, #4]
8004a64: 4a26 ldr r2, [pc, #152] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004a66: f423 0340 bic.w r3, r3, #12582912 ; 0xc00000
8004a6a: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
8004a6c: 687b ldr r3, [r7, #4]
8004a6e: 681b ldr r3, [r3, #0]
8004a70: 4a22 ldr r2, [pc, #136] ; (8004afc <HAL_ADC_ConfigChannel+0x284>)
8004a72: 4293 cmp r3, r2
8004a74: d109 bne.n 8004a8a <HAL_ADC_ConfigChannel+0x212>
8004a76: 683b ldr r3, [r7, #0]
8004a78: 681b ldr r3, [r3, #0]
8004a7a: 2b12 cmp r3, #18
8004a7c: d105 bne.n 8004a8a <HAL_ADC_ConfigChannel+0x212>
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
8004a7e: 4b20 ldr r3, [pc, #128] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004a80: 685b ldr r3, [r3, #4]
8004a82: 4a1f ldr r2, [pc, #124] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004a84: f443 0380 orr.w r3, r3, #4194304 ; 0x400000
8004a88: 6053 str r3, [r2, #4]
}
/* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8004a8a: 687b ldr r3, [r7, #4]
8004a8c: 681b ldr r3, [r3, #0]
8004a8e: 4a1b ldr r2, [pc, #108] ; (8004afc <HAL_ADC_ConfigChannel+0x284>)
8004a90: 4293 cmp r3, r2
8004a92: d125 bne.n 8004ae0 <HAL_ADC_ConfigChannel+0x268>
8004a94: 683b ldr r3, [r7, #0]
8004a96: 681b ldr r3, [r3, #0]
8004a98: 4a17 ldr r2, [pc, #92] ; (8004af8 <HAL_ADC_ConfigChannel+0x280>)
8004a9a: 4293 cmp r3, r2
8004a9c: d003 beq.n 8004aa6 <HAL_ADC_ConfigChannel+0x22e>
8004a9e: 683b ldr r3, [r7, #0]
8004aa0: 681b ldr r3, [r3, #0]
8004aa2: 2b11 cmp r3, #17
8004aa4: d11c bne.n 8004ae0 <HAL_ADC_ConfigChannel+0x268>
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
8004aa6: 4b16 ldr r3, [pc, #88] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004aa8: 685b ldr r3, [r3, #4]
8004aaa: 4a15 ldr r2, [pc, #84] ; (8004b00 <HAL_ADC_ConfigChannel+0x288>)
8004aac: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8004ab0: 6053 str r3, [r2, #4]
if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8004ab2: 683b ldr r3, [r7, #0]
8004ab4: 681b ldr r3, [r3, #0]
8004ab6: 4a10 ldr r2, [pc, #64] ; (8004af8 <HAL_ADC_ConfigChannel+0x280>)
8004ab8: 4293 cmp r3, r2
8004aba: d111 bne.n 8004ae0 <HAL_ADC_ConfigChannel+0x268>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
8004abc: 4b11 ldr r3, [pc, #68] ; (8004b04 <HAL_ADC_ConfigChannel+0x28c>)
8004abe: 681b ldr r3, [r3, #0]
8004ac0: 4a11 ldr r2, [pc, #68] ; (8004b08 <HAL_ADC_ConfigChannel+0x290>)
8004ac2: fba2 2303 umull r2, r3, r2, r3
8004ac6: 0c9a lsrs r2, r3, #18
8004ac8: 4613 mov r3, r2
8004aca: 009b lsls r3, r3, #2
8004acc: 4413 add r3, r2
8004ace: 005b lsls r3, r3, #1
8004ad0: 60fb str r3, [r7, #12]
while(counter != 0)
8004ad2: e002 b.n 8004ada <HAL_ADC_ConfigChannel+0x262>
{
counter--;
8004ad4: 68fb ldr r3, [r7, #12]
8004ad6: 3b01 subs r3, #1
8004ad8: 60fb str r3, [r7, #12]
while(counter != 0)
8004ada: 68fb ldr r3, [r7, #12]
8004adc: 2b00 cmp r3, #0
8004ade: d1f9 bne.n 8004ad4 <HAL_ADC_ConfigChannel+0x25c>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8004ae0: 687b ldr r3, [r7, #4]
8004ae2: 2200 movs r2, #0
8004ae4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8004ae8: 2300 movs r3, #0
}
8004aea: 4618 mov r0, r3
8004aec: 3714 adds r7, #20
8004aee: 46bd mov sp, r7
8004af0: f85d 7b04 ldr.w r7, [sp], #4
8004af4: 4770 bx lr
8004af6: bf00 nop
8004af8: 10000012 .word 0x10000012
8004afc: 40012000 .word 0x40012000
8004b00: 40012300 .word 0x40012300
8004b04: 2000003c .word 0x2000003c
8004b08: 431bde83 .word 0x431bde83
08004b0c <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
8004b0c: b480 push {r7}
8004b0e: b083 sub sp, #12
8004b10: af00 add r7, sp, #0
8004b12: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Set the ADC clock prescaler */
ADC->CCR &= ~(ADC_CCR_ADCPRE);
8004b14: 4b78 ldr r3, [pc, #480] ; (8004cf8 <ADC_Init+0x1ec>)
8004b16: 685b ldr r3, [r3, #4]
8004b18: 4a77 ldr r2, [pc, #476] ; (8004cf8 <ADC_Init+0x1ec>)
8004b1a: f423 3340 bic.w r3, r3, #196608 ; 0x30000
8004b1e: 6053 str r3, [r2, #4]
ADC->CCR |= hadc->Init.ClockPrescaler;
8004b20: 4b75 ldr r3, [pc, #468] ; (8004cf8 <ADC_Init+0x1ec>)
8004b22: 685a ldr r2, [r3, #4]
8004b24: 687b ldr r3, [r7, #4]
8004b26: 685b ldr r3, [r3, #4]
8004b28: 4973 ldr r1, [pc, #460] ; (8004cf8 <ADC_Init+0x1ec>)
8004b2a: 4313 orrs r3, r2
8004b2c: 604b str r3, [r1, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
8004b2e: 687b ldr r3, [r7, #4]
8004b30: 681b ldr r3, [r3, #0]
8004b32: 685a ldr r2, [r3, #4]
8004b34: 687b ldr r3, [r7, #4]
8004b36: 681b ldr r3, [r3, #0]
8004b38: f422 7280 bic.w r2, r2, #256 ; 0x100
8004b3c: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
8004b3e: 687b ldr r3, [r7, #4]
8004b40: 681b ldr r3, [r3, #0]
8004b42: 6859 ldr r1, [r3, #4]
8004b44: 687b ldr r3, [r7, #4]
8004b46: 691b ldr r3, [r3, #16]
8004b48: 021a lsls r2, r3, #8
8004b4a: 687b ldr r3, [r7, #4]
8004b4c: 681b ldr r3, [r3, #0]
8004b4e: 430a orrs r2, r1
8004b50: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
8004b52: 687b ldr r3, [r7, #4]
8004b54: 681b ldr r3, [r3, #0]
8004b56: 685a ldr r2, [r3, #4]
8004b58: 687b ldr r3, [r7, #4]
8004b5a: 681b ldr r3, [r3, #0]
8004b5c: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
8004b60: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
8004b62: 687b ldr r3, [r7, #4]
8004b64: 681b ldr r3, [r3, #0]
8004b66: 6859 ldr r1, [r3, #4]
8004b68: 687b ldr r3, [r7, #4]
8004b6a: 689a ldr r2, [r3, #8]
8004b6c: 687b ldr r3, [r7, #4]
8004b6e: 681b ldr r3, [r3, #0]
8004b70: 430a orrs r2, r1
8004b72: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
8004b74: 687b ldr r3, [r7, #4]
8004b76: 681b ldr r3, [r3, #0]
8004b78: 689a ldr r2, [r3, #8]
8004b7a: 687b ldr r3, [r7, #4]
8004b7c: 681b ldr r3, [r3, #0]
8004b7e: f422 6200 bic.w r2, r2, #2048 ; 0x800
8004b82: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
8004b84: 687b ldr r3, [r7, #4]
8004b86: 681b ldr r3, [r3, #0]
8004b88: 6899 ldr r1, [r3, #8]
8004b8a: 687b ldr r3, [r7, #4]
8004b8c: 68da ldr r2, [r3, #12]
8004b8e: 687b ldr r3, [r7, #4]
8004b90: 681b ldr r3, [r3, #0]
8004b92: 430a orrs r2, r1
8004b94: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8004b96: 687b ldr r3, [r7, #4]
8004b98: 6a9b ldr r3, [r3, #40] ; 0x28
8004b9a: 4a58 ldr r2, [pc, #352] ; (8004cfc <ADC_Init+0x1f0>)
8004b9c: 4293 cmp r3, r2
8004b9e: d022 beq.n 8004be6 <ADC_Init+0xda>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8004ba0: 687b ldr r3, [r7, #4]
8004ba2: 681b ldr r3, [r3, #0]
8004ba4: 689a ldr r2, [r3, #8]
8004ba6: 687b ldr r3, [r7, #4]
8004ba8: 681b ldr r3, [r3, #0]
8004baa: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8004bae: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
8004bb0: 687b ldr r3, [r7, #4]
8004bb2: 681b ldr r3, [r3, #0]
8004bb4: 6899 ldr r1, [r3, #8]
8004bb6: 687b ldr r3, [r7, #4]
8004bb8: 6a9a ldr r2, [r3, #40] ; 0x28
8004bba: 687b ldr r3, [r7, #4]
8004bbc: 681b ldr r3, [r3, #0]
8004bbe: 430a orrs r2, r1
8004bc0: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8004bc2: 687b ldr r3, [r7, #4]
8004bc4: 681b ldr r3, [r3, #0]
8004bc6: 689a ldr r2, [r3, #8]
8004bc8: 687b ldr r3, [r7, #4]
8004bca: 681b ldr r3, [r3, #0]
8004bcc: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8004bd0: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
8004bd2: 687b ldr r3, [r7, #4]
8004bd4: 681b ldr r3, [r3, #0]
8004bd6: 6899 ldr r1, [r3, #8]
8004bd8: 687b ldr r3, [r7, #4]
8004bda: 6ada ldr r2, [r3, #44] ; 0x2c
8004bdc: 687b ldr r3, [r7, #4]
8004bde: 681b ldr r3, [r3, #0]
8004be0: 430a orrs r2, r1
8004be2: 609a str r2, [r3, #8]
8004be4: e00f b.n 8004c06 <ADC_Init+0xfa>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8004be6: 687b ldr r3, [r7, #4]
8004be8: 681b ldr r3, [r3, #0]
8004bea: 689a ldr r2, [r3, #8]
8004bec: 687b ldr r3, [r7, #4]
8004bee: 681b ldr r3, [r3, #0]
8004bf0: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8004bf4: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8004bf6: 687b ldr r3, [r7, #4]
8004bf8: 681b ldr r3, [r3, #0]
8004bfa: 689a ldr r2, [r3, #8]
8004bfc: 687b ldr r3, [r7, #4]
8004bfe: 681b ldr r3, [r3, #0]
8004c00: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8004c04: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
8004c06: 687b ldr r3, [r7, #4]
8004c08: 681b ldr r3, [r3, #0]
8004c0a: 689a ldr r2, [r3, #8]
8004c0c: 687b ldr r3, [r7, #4]
8004c0e: 681b ldr r3, [r3, #0]
8004c10: f022 0202 bic.w r2, r2, #2
8004c14: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
8004c16: 687b ldr r3, [r7, #4]
8004c18: 681b ldr r3, [r3, #0]
8004c1a: 6899 ldr r1, [r3, #8]
8004c1c: 687b ldr r3, [r7, #4]
8004c1e: 699b ldr r3, [r3, #24]
8004c20: 005a lsls r2, r3, #1
8004c22: 687b ldr r3, [r7, #4]
8004c24: 681b ldr r3, [r3, #0]
8004c26: 430a orrs r2, r1
8004c28: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
8004c2a: 687b ldr r3, [r7, #4]
8004c2c: f893 3020 ldrb.w r3, [r3, #32]
8004c30: 2b00 cmp r3, #0
8004c32: d01b beq.n 8004c6c <ADC_Init+0x160>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
8004c34: 687b ldr r3, [r7, #4]
8004c36: 681b ldr r3, [r3, #0]
8004c38: 685a ldr r2, [r3, #4]
8004c3a: 687b ldr r3, [r7, #4]
8004c3c: 681b ldr r3, [r3, #0]
8004c3e: f442 6200 orr.w r2, r2, #2048 ; 0x800
8004c42: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
8004c44: 687b ldr r3, [r7, #4]
8004c46: 681b ldr r3, [r3, #0]
8004c48: 685a ldr r2, [r3, #4]
8004c4a: 687b ldr r3, [r7, #4]
8004c4c: 681b ldr r3, [r3, #0]
8004c4e: f422 4260 bic.w r2, r2, #57344 ; 0xe000
8004c52: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
8004c54: 687b ldr r3, [r7, #4]
8004c56: 681b ldr r3, [r3, #0]
8004c58: 6859 ldr r1, [r3, #4]
8004c5a: 687b ldr r3, [r7, #4]
8004c5c: 6a5b ldr r3, [r3, #36] ; 0x24
8004c5e: 3b01 subs r3, #1
8004c60: 035a lsls r2, r3, #13
8004c62: 687b ldr r3, [r7, #4]
8004c64: 681b ldr r3, [r3, #0]
8004c66: 430a orrs r2, r1
8004c68: 605a str r2, [r3, #4]
8004c6a: e007 b.n 8004c7c <ADC_Init+0x170>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
8004c6c: 687b ldr r3, [r7, #4]
8004c6e: 681b ldr r3, [r3, #0]
8004c70: 685a ldr r2, [r3, #4]
8004c72: 687b ldr r3, [r7, #4]
8004c74: 681b ldr r3, [r3, #0]
8004c76: f422 6200 bic.w r2, r2, #2048 ; 0x800
8004c7a: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
8004c7c: 687b ldr r3, [r7, #4]
8004c7e: 681b ldr r3, [r3, #0]
8004c80: 6ada ldr r2, [r3, #44] ; 0x2c
8004c82: 687b ldr r3, [r7, #4]
8004c84: 681b ldr r3, [r3, #0]
8004c86: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
8004c8a: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
8004c8c: 687b ldr r3, [r7, #4]
8004c8e: 681b ldr r3, [r3, #0]
8004c90: 6ad9 ldr r1, [r3, #44] ; 0x2c
8004c92: 687b ldr r3, [r7, #4]
8004c94: 69db ldr r3, [r3, #28]
8004c96: 3b01 subs r3, #1
8004c98: 051a lsls r2, r3, #20
8004c9a: 687b ldr r3, [r7, #4]
8004c9c: 681b ldr r3, [r3, #0]
8004c9e: 430a orrs r2, r1
8004ca0: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
8004ca2: 687b ldr r3, [r7, #4]
8004ca4: 681b ldr r3, [r3, #0]
8004ca6: 689a ldr r2, [r3, #8]
8004ca8: 687b ldr r3, [r7, #4]
8004caa: 681b ldr r3, [r3, #0]
8004cac: f422 7200 bic.w r2, r2, #512 ; 0x200
8004cb0: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
8004cb2: 687b ldr r3, [r7, #4]
8004cb4: 681b ldr r3, [r3, #0]
8004cb6: 6899 ldr r1, [r3, #8]
8004cb8: 687b ldr r3, [r7, #4]
8004cba: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8004cbe: 025a lsls r2, r3, #9
8004cc0: 687b ldr r3, [r7, #4]
8004cc2: 681b ldr r3, [r3, #0]
8004cc4: 430a orrs r2, r1
8004cc6: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8004cc8: 687b ldr r3, [r7, #4]
8004cca: 681b ldr r3, [r3, #0]
8004ccc: 689a ldr r2, [r3, #8]
8004cce: 687b ldr r3, [r7, #4]
8004cd0: 681b ldr r3, [r3, #0]
8004cd2: f422 6280 bic.w r2, r2, #1024 ; 0x400
8004cd6: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8004cd8: 687b ldr r3, [r7, #4]
8004cda: 681b ldr r3, [r3, #0]
8004cdc: 6899 ldr r1, [r3, #8]
8004cde: 687b ldr r3, [r7, #4]
8004ce0: 695b ldr r3, [r3, #20]
8004ce2: 029a lsls r2, r3, #10
8004ce4: 687b ldr r3, [r7, #4]
8004ce6: 681b ldr r3, [r3, #0]
8004ce8: 430a orrs r2, r1
8004cea: 609a str r2, [r3, #8]
}
8004cec: bf00 nop
8004cee: 370c adds r7, #12
8004cf0: 46bd mov sp, r7
8004cf2: f85d 7b04 ldr.w r7, [sp], #4
8004cf6: 4770 bx lr
8004cf8: 40012300 .word 0x40012300
8004cfc: 0f000001 .word 0x0f000001
08004d00 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8004d00: b480 push {r7}
8004d02: b085 sub sp, #20
8004d04: af00 add r7, sp, #0
8004d06: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8004d08: 687b ldr r3, [r7, #4]
8004d0a: f003 0307 and.w r3, r3, #7
8004d0e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8004d10: 4b0b ldr r3, [pc, #44] ; (8004d40 <__NVIC_SetPriorityGrouping+0x40>)
8004d12: 68db ldr r3, [r3, #12]
8004d14: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8004d16: 68ba ldr r2, [r7, #8]
8004d18: f64f 03ff movw r3, #63743 ; 0xf8ff
8004d1c: 4013 ands r3, r2
8004d1e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8004d20: 68fb ldr r3, [r7, #12]
8004d22: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8004d24: 68bb ldr r3, [r7, #8]
8004d26: 431a orrs r2, r3
reg_value = (reg_value |
8004d28: 4b06 ldr r3, [pc, #24] ; (8004d44 <__NVIC_SetPriorityGrouping+0x44>)
8004d2a: 4313 orrs r3, r2
8004d2c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8004d2e: 4a04 ldr r2, [pc, #16] ; (8004d40 <__NVIC_SetPriorityGrouping+0x40>)
8004d30: 68bb ldr r3, [r7, #8]
8004d32: 60d3 str r3, [r2, #12]
}
8004d34: bf00 nop
8004d36: 3714 adds r7, #20
8004d38: 46bd mov sp, r7
8004d3a: f85d 7b04 ldr.w r7, [sp], #4
8004d3e: 4770 bx lr
8004d40: e000ed00 .word 0xe000ed00
8004d44: 05fa0000 .word 0x05fa0000
08004d48 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8004d48: b480 push {r7}
8004d4a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8004d4c: 4b04 ldr r3, [pc, #16] ; (8004d60 <__NVIC_GetPriorityGrouping+0x18>)
8004d4e: 68db ldr r3, [r3, #12]
8004d50: 0a1b lsrs r3, r3, #8
8004d52: f003 0307 and.w r3, r3, #7
}
8004d56: 4618 mov r0, r3
8004d58: 46bd mov sp, r7
8004d5a: f85d 7b04 ldr.w r7, [sp], #4
8004d5e: 4770 bx lr
8004d60: e000ed00 .word 0xe000ed00
08004d64 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8004d64: b480 push {r7}
8004d66: b083 sub sp, #12
8004d68: af00 add r7, sp, #0
8004d6a: 4603 mov r3, r0
8004d6c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8004d6e: f997 3007 ldrsb.w r3, [r7, #7]
8004d72: 2b00 cmp r3, #0
8004d74: db0b blt.n 8004d8e <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8004d76: 79fb ldrb r3, [r7, #7]
8004d78: f003 021f and.w r2, r3, #31
8004d7c: 4907 ldr r1, [pc, #28] ; (8004d9c <__NVIC_EnableIRQ+0x38>)
8004d7e: f997 3007 ldrsb.w r3, [r7, #7]
8004d82: 095b lsrs r3, r3, #5
8004d84: 2001 movs r0, #1
8004d86: fa00 f202 lsl.w r2, r0, r2
8004d8a: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8004d8e: bf00 nop
8004d90: 370c adds r7, #12
8004d92: 46bd mov sp, r7
8004d94: f85d 7b04 ldr.w r7, [sp], #4
8004d98: 4770 bx lr
8004d9a: bf00 nop
8004d9c: e000e100 .word 0xe000e100
08004da0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8004da0: b480 push {r7}
8004da2: b083 sub sp, #12
8004da4: af00 add r7, sp, #0
8004da6: 4603 mov r3, r0
8004da8: 6039 str r1, [r7, #0]
8004daa: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8004dac: f997 3007 ldrsb.w r3, [r7, #7]
8004db0: 2b00 cmp r3, #0
8004db2: db0a blt.n 8004dca <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8004db4: 683b ldr r3, [r7, #0]
8004db6: b2da uxtb r2, r3
8004db8: 490c ldr r1, [pc, #48] ; (8004dec <__NVIC_SetPriority+0x4c>)
8004dba: f997 3007 ldrsb.w r3, [r7, #7]
8004dbe: 0112 lsls r2, r2, #4
8004dc0: b2d2 uxtb r2, r2
8004dc2: 440b add r3, r1
8004dc4: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8004dc8: e00a b.n 8004de0 <__NVIC_SetPriority+0x40>
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8004dca: 683b ldr r3, [r7, #0]
8004dcc: b2da uxtb r2, r3
8004dce: 4908 ldr r1, [pc, #32] ; (8004df0 <__NVIC_SetPriority+0x50>)
8004dd0: 79fb ldrb r3, [r7, #7]
8004dd2: f003 030f and.w r3, r3, #15
8004dd6: 3b04 subs r3, #4
8004dd8: 0112 lsls r2, r2, #4
8004dda: b2d2 uxtb r2, r2
8004ddc: 440b add r3, r1
8004dde: 761a strb r2, [r3, #24]
}
8004de0: bf00 nop
8004de2: 370c adds r7, #12
8004de4: 46bd mov sp, r7
8004de6: f85d 7b04 ldr.w r7, [sp], #4
8004dea: 4770 bx lr
8004dec: e000e100 .word 0xe000e100
8004df0: e000ed00 .word 0xe000ed00
08004df4 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8004df4: b480 push {r7}
8004df6: b089 sub sp, #36 ; 0x24
8004df8: af00 add r7, sp, #0
8004dfa: 60f8 str r0, [r7, #12]
8004dfc: 60b9 str r1, [r7, #8]
8004dfe: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8004e00: 68fb ldr r3, [r7, #12]
8004e02: f003 0307 and.w r3, r3, #7
8004e06: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8004e08: 69fb ldr r3, [r7, #28]
8004e0a: f1c3 0307 rsb r3, r3, #7
8004e0e: 2b04 cmp r3, #4
8004e10: bf28 it cs
8004e12: 2304 movcs r3, #4
8004e14: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8004e16: 69fb ldr r3, [r7, #28]
8004e18: 3304 adds r3, #4
8004e1a: 2b06 cmp r3, #6
8004e1c: d902 bls.n 8004e24 <NVIC_EncodePriority+0x30>
8004e1e: 69fb ldr r3, [r7, #28]
8004e20: 3b03 subs r3, #3
8004e22: e000 b.n 8004e26 <NVIC_EncodePriority+0x32>
8004e24: 2300 movs r3, #0
8004e26: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8004e28: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8004e2c: 69bb ldr r3, [r7, #24]
8004e2e: fa02 f303 lsl.w r3, r2, r3
8004e32: 43da mvns r2, r3
8004e34: 68bb ldr r3, [r7, #8]
8004e36: 401a ands r2, r3
8004e38: 697b ldr r3, [r7, #20]
8004e3a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8004e3c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
8004e40: 697b ldr r3, [r7, #20]
8004e42: fa01 f303 lsl.w r3, r1, r3
8004e46: 43d9 mvns r1, r3
8004e48: 687b ldr r3, [r7, #4]
8004e4a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8004e4c: 4313 orrs r3, r2
);
}
8004e4e: 4618 mov r0, r3
8004e50: 3724 adds r7, #36 ; 0x24
8004e52: 46bd mov sp, r7
8004e54: f85d 7b04 ldr.w r7, [sp], #4
8004e58: 4770 bx lr
08004e5a <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8004e5a: b580 push {r7, lr}
8004e5c: b082 sub sp, #8
8004e5e: af00 add r7, sp, #0
8004e60: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8004e62: 6878 ldr r0, [r7, #4]
8004e64: f7ff ff4c bl 8004d00 <__NVIC_SetPriorityGrouping>
}
8004e68: bf00 nop
8004e6a: 3708 adds r7, #8
8004e6c: 46bd mov sp, r7
8004e6e: bd80 pop {r7, pc}
08004e70 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8004e70: b580 push {r7, lr}
8004e72: b086 sub sp, #24
8004e74: af00 add r7, sp, #0
8004e76: 4603 mov r3, r0
8004e78: 60b9 str r1, [r7, #8]
8004e7a: 607a str r2, [r7, #4]
8004e7c: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00;
8004e7e: 2300 movs r3, #0
8004e80: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8004e82: f7ff ff61 bl 8004d48 <__NVIC_GetPriorityGrouping>
8004e86: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8004e88: 687a ldr r2, [r7, #4]
8004e8a: 68b9 ldr r1, [r7, #8]
8004e8c: 6978 ldr r0, [r7, #20]
8004e8e: f7ff ffb1 bl 8004df4 <NVIC_EncodePriority>
8004e92: 4602 mov r2, r0
8004e94: f997 300f ldrsb.w r3, [r7, #15]
8004e98: 4611 mov r1, r2
8004e9a: 4618 mov r0, r3
8004e9c: f7ff ff80 bl 8004da0 <__NVIC_SetPriority>
}
8004ea0: bf00 nop
8004ea2: 3718 adds r7, #24
8004ea4: 46bd mov sp, r7
8004ea6: bd80 pop {r7, pc}
08004ea8 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8004ea8: b580 push {r7, lr}
8004eaa: b082 sub sp, #8
8004eac: af00 add r7, sp, #0
8004eae: 4603 mov r3, r0
8004eb0: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8004eb2: f997 3007 ldrsb.w r3, [r7, #7]
8004eb6: 4618 mov r0, r3
8004eb8: f7ff ff54 bl 8004d64 <__NVIC_EnableIRQ>
}
8004ebc: bf00 nop
8004ebe: 3708 adds r7, #8
8004ec0: 46bd mov sp, r7
8004ec2: bd80 pop {r7, pc}
08004ec4 <HAL_DAC_Init>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
{
8004ec4: b580 push {r7, lr}
8004ec6: b082 sub sp, #8
8004ec8: af00 add r7, sp, #0
8004eca: 6078 str r0, [r7, #4]
/* Check DAC handle */
if(hdac == NULL)
8004ecc: 687b ldr r3, [r7, #4]
8004ece: 2b00 cmp r3, #0
8004ed0: d101 bne.n 8004ed6 <HAL_DAC_Init+0x12>
{
return HAL_ERROR;
8004ed2: 2301 movs r3, #1
8004ed4: e014 b.n 8004f00 <HAL_DAC_Init+0x3c>
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if(hdac->State == HAL_DAC_STATE_RESET)
8004ed6: 687b ldr r3, [r7, #4]
8004ed8: 791b ldrb r3, [r3, #4]
8004eda: b2db uxtb r3, r3
8004edc: 2b00 cmp r3, #0
8004ede: d105 bne.n 8004eec <HAL_DAC_Init+0x28>
{
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
8004ee0: 687b ldr r3, [r7, #4]
8004ee2: 2200 movs r2, #0
8004ee4: 715a strb r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
8004ee6: 6878 ldr r0, [r7, #4]
8004ee8: f7fe fd4a bl 8003980 <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
8004eec: 687b ldr r3, [r7, #4]
8004eee: 2202 movs r2, #2
8004ef0: 711a strb r2, [r3, #4]
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
8004ef2: 687b ldr r3, [r7, #4]
8004ef4: 2200 movs r2, #0
8004ef6: 611a str r2, [r3, #16]
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
8004ef8: 687b ldr r3, [r7, #4]
8004efa: 2201 movs r2, #1
8004efc: 711a strb r2, [r3, #4]
/* Return function status */
return HAL_OK;
8004efe: 2300 movs r3, #0
}
8004f00: 4618 mov r0, r3
8004f02: 3708 adds r7, #8
8004f04: 46bd mov sp, r7
8004f06: bd80 pop {r7, pc}
08004f08 <HAL_DAC_IRQHandler>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
8004f08: b580 push {r7, lr}
8004f0a: b082 sub sp, #8
8004f0c: af00 add r7, sp, #0
8004f0e: 6078 str r0, [r7, #4]
/* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
8004f10: 687b ldr r3, [r7, #4]
8004f12: 681b ldr r3, [r3, #0]
8004f14: 6b5b ldr r3, [r3, #52] ; 0x34
8004f16: f403 5300 and.w r3, r3, #8192 ; 0x2000
8004f1a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8004f1e: d118 bne.n 8004f52 <HAL_DAC_IRQHandler+0x4a>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
8004f20: 687b ldr r3, [r7, #4]
8004f22: 2204 movs r2, #4
8004f24: 711a strb r2, [r3, #4]
/* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
8004f26: 687b ldr r3, [r7, #4]
8004f28: 691b ldr r3, [r3, #16]
8004f2a: f043 0201 orr.w r2, r3, #1
8004f2e: 687b ldr r3, [r7, #4]
8004f30: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
8004f32: 687b ldr r3, [r7, #4]
8004f34: 681b ldr r3, [r3, #0]
8004f36: f44f 5200 mov.w r2, #8192 ; 0x2000
8004f3a: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
8004f3c: 687b ldr r3, [r7, #4]
8004f3e: 681b ldr r3, [r3, #0]
8004f40: 681a ldr r2, [r3, #0]
8004f42: 687b ldr r3, [r7, #4]
8004f44: 681b ldr r3, [r3, #0]
8004f46: f422 5280 bic.w r2, r2, #4096 ; 0x1000
8004f4a: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh1(hdac);
#else
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
8004f4c: 6878 ldr r0, [r7, #4]
8004f4e: f000 f825 bl 8004f9c <HAL_DAC_DMAUnderrunCallbackCh1>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
8004f52: 687b ldr r3, [r7, #4]
8004f54: 681b ldr r3, [r3, #0]
8004f56: 6b5b ldr r3, [r3, #52] ; 0x34
8004f58: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8004f5c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8004f60: d118 bne.n 8004f94 <HAL_DAC_IRQHandler+0x8c>
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
8004f62: 687b ldr r3, [r7, #4]
8004f64: 2204 movs r2, #4
8004f66: 711a strb r2, [r3, #4]
/* Set DAC error code to channel2 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
8004f68: 687b ldr r3, [r7, #4]
8004f6a: 691b ldr r3, [r3, #16]
8004f6c: f043 0202 orr.w r2, r3, #2
8004f70: 687b ldr r3, [r7, #4]
8004f72: 611a str r2, [r3, #16]
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
8004f74: 687b ldr r3, [r7, #4]
8004f76: 681b ldr r3, [r3, #0]
8004f78: f04f 5200 mov.w r2, #536870912 ; 0x20000000
8004f7c: 635a str r2, [r3, #52] ; 0x34
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
8004f7e: 687b ldr r3, [r7, #4]
8004f80: 681b ldr r3, [r3, #0]
8004f82: 681a ldr r2, [r3, #0]
8004f84: 687b ldr r3, [r7, #4]
8004f86: 681b ldr r3, [r3, #0]
8004f88: f022 5280 bic.w r2, r2, #268435456 ; 0x10000000
8004f8c: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
hdac->DMAUnderrunCallbackCh2(hdac);
#else
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
8004f8e: 6878 ldr r0, [r7, #4]
8004f90: f000 f85b bl 800504a <HAL_DACEx_DMAUnderrunCallbackCh2>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
}
8004f94: bf00 nop
8004f96: 3708 adds r7, #8
8004f98: 46bd mov sp, r7
8004f9a: bd80 pop {r7, pc}
08004f9c <HAL_DAC_DMAUnderrunCallbackCh1>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
8004f9c: b480 push {r7}
8004f9e: b083 sub sp, #12
8004fa0: af00 add r7, sp, #0
8004fa2: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
8004fa4: bf00 nop
8004fa6: 370c adds r7, #12
8004fa8: 46bd mov sp, r7
8004faa: f85d 7b04 ldr.w r7, [sp], #4
8004fae: 4770 bx lr
08004fb0 <HAL_DAC_ConfigChannel>:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
8004fb0: b480 push {r7}
8004fb2: b087 sub sp, #28
8004fb4: af00 add r7, sp, #0
8004fb6: 60f8 str r0, [r7, #12]
8004fb8: 60b9 str r1, [r7, #8]
8004fba: 607a str r2, [r7, #4]
uint32_t tmpreg1 = 0, tmpreg2 = 0;
8004fbc: 2300 movs r3, #0
8004fbe: 617b str r3, [r7, #20]
8004fc0: 2300 movs r3, #0
8004fc2: 613b str r3, [r7, #16]
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
8004fc4: 68fb ldr r3, [r7, #12]
8004fc6: 795b ldrb r3, [r3, #5]
8004fc8: 2b01 cmp r3, #1
8004fca: d101 bne.n 8004fd0 <HAL_DAC_ConfigChannel+0x20>
8004fcc: 2302 movs r3, #2
8004fce: e036 b.n 800503e <HAL_DAC_ConfigChannel+0x8e>
8004fd0: 68fb ldr r3, [r7, #12]
8004fd2: 2201 movs r2, #1
8004fd4: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
8004fd6: 68fb ldr r3, [r7, #12]
8004fd8: 2202 movs r2, #2
8004fda: 711a strb r2, [r3, #4]
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
8004fdc: 68fb ldr r3, [r7, #12]
8004fde: 681b ldr r3, [r3, #0]
8004fe0: 681b ldr r3, [r3, #0]
8004fe2: 617b str r3, [r7, #20]
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
8004fe4: f640 72fe movw r2, #4094 ; 0xffe
8004fe8: 687b ldr r3, [r7, #4]
8004fea: fa02 f303 lsl.w r3, r2, r3
8004fee: 43db mvns r3, r3
8004ff0: 697a ldr r2, [r7, #20]
8004ff2: 4013 ands r3, r2
8004ff4: 617b str r3, [r7, #20]
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
8004ff6: 68bb ldr r3, [r7, #8]
8004ff8: 681a ldr r2, [r3, #0]
8004ffa: 68bb ldr r3, [r7, #8]
8004ffc: 685b ldr r3, [r3, #4]
8004ffe: 4313 orrs r3, r2
8005000: 613b str r3, [r7, #16]
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
8005002: 693a ldr r2, [r7, #16]
8005004: 687b ldr r3, [r7, #4]
8005006: fa02 f303 lsl.w r3, r2, r3
800500a: 697a ldr r2, [r7, #20]
800500c: 4313 orrs r3, r2
800500e: 617b str r3, [r7, #20]
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
8005010: 68fb ldr r3, [r7, #12]
8005012: 681b ldr r3, [r3, #0]
8005014: 697a ldr r2, [r7, #20]
8005016: 601a str r2, [r3, #0]
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
8005018: 68fb ldr r3, [r7, #12]
800501a: 681b ldr r3, [r3, #0]
800501c: 6819 ldr r1, [r3, #0]
800501e: 22c0 movs r2, #192 ; 0xc0
8005020: 687b ldr r3, [r7, #4]
8005022: fa02 f303 lsl.w r3, r2, r3
8005026: 43da mvns r2, r3
8005028: 68fb ldr r3, [r7, #12]
800502a: 681b ldr r3, [r3, #0]
800502c: 400a ands r2, r1
800502e: 601a str r2, [r3, #0]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
8005030: 68fb ldr r3, [r7, #12]
8005032: 2201 movs r2, #1
8005034: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
8005036: 68fb ldr r3, [r7, #12]
8005038: 2200 movs r2, #0
800503a: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
800503c: 2300 movs r3, #0
}
800503e: 4618 mov r0, r3
8005040: 371c adds r7, #28
8005042: 46bd mov sp, r7
8005044: f85d 7b04 ldr.w r7, [sp], #4
8005048: 4770 bx lr
0800504a <HAL_DACEx_DMAUnderrunCallbackCh2>:
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
800504a: b480 push {r7}
800504c: b083 sub sp, #12
800504e: af00 add r7, sp, #0
8005050: 6078 str r0, [r7, #4]
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
8005052: bf00 nop
8005054: 370c adds r7, #12
8005056: 46bd mov sp, r7
8005058: f85d 7b04 ldr.w r7, [sp], #4
800505c: 4770 bx lr
...
08005060 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
8005060: b580 push {r7, lr}
8005062: b086 sub sp, #24
8005064: af00 add r7, sp, #0
8005066: 6078 str r0, [r7, #4]
uint32_t tmp = 0U;
8005068: 2300 movs r3, #0
800506a: 617b str r3, [r7, #20]
uint32_t tickstart = HAL_GetTick();
800506c: f7ff fa40 bl 80044f0 <HAL_GetTick>
8005070: 6138 str r0, [r7, #16]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
8005072: 687b ldr r3, [r7, #4]
8005074: 2b00 cmp r3, #0
8005076: d101 bne.n 800507c <HAL_DMA_Init+0x1c>
{
return HAL_ERROR;
8005078: 2301 movs r3, #1
800507a: e099 b.n 80051b0 <HAL_DMA_Init+0x150>
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
}
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
800507c: 687b ldr r3, [r7, #4]
800507e: 2200 movs r2, #0
8005080: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8005084: 687b ldr r3, [r7, #4]
8005086: 2202 movs r2, #2
8005088: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
800508c: 687b ldr r3, [r7, #4]
800508e: 681b ldr r3, [r3, #0]
8005090: 681a ldr r2, [r3, #0]
8005092: 687b ldr r3, [r7, #4]
8005094: 681b ldr r3, [r3, #0]
8005096: f022 0201 bic.w r2, r2, #1
800509a: 601a str r2, [r3, #0]
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
800509c: e00f b.n 80050be <HAL_DMA_Init+0x5e>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
800509e: f7ff fa27 bl 80044f0 <HAL_GetTick>
80050a2: 4602 mov r2, r0
80050a4: 693b ldr r3, [r7, #16]
80050a6: 1ad3 subs r3, r2, r3
80050a8: 2b05 cmp r3, #5
80050aa: d908 bls.n 80050be <HAL_DMA_Init+0x5e>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
80050ac: 687b ldr r3, [r7, #4]
80050ae: 2220 movs r2, #32
80050b0: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
80050b2: 687b ldr r3, [r7, #4]
80050b4: 2203 movs r2, #3
80050b6: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_TIMEOUT;
80050ba: 2303 movs r3, #3
80050bc: e078 b.n 80051b0 <HAL_DMA_Init+0x150>
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
80050be: 687b ldr r3, [r7, #4]
80050c0: 681b ldr r3, [r3, #0]
80050c2: 681b ldr r3, [r3, #0]
80050c4: f003 0301 and.w r3, r3, #1
80050c8: 2b00 cmp r3, #0
80050ca: d1e8 bne.n 800509e <HAL_DMA_Init+0x3e>
}
}
/* Get the CR register value */
tmp = hdma->Instance->CR;
80050cc: 687b ldr r3, [r7, #4]
80050ce: 681b ldr r3, [r3, #0]
80050d0: 681b ldr r3, [r3, #0]
80050d2: 617b str r3, [r7, #20]
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
80050d4: 697a ldr r2, [r7, #20]
80050d6: 4b38 ldr r3, [pc, #224] ; (80051b8 <HAL_DMA_Init+0x158>)
80050d8: 4013 ands r3, r2
80050da: 617b str r3, [r7, #20]
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
/* Prepare the DMA Stream configuration */
tmp |= hdma->Init.Channel | hdma->Init.Direction |
80050dc: 687b ldr r3, [r7, #4]
80050de: 685a ldr r2, [r3, #4]
80050e0: 687b ldr r3, [r7, #4]
80050e2: 689b ldr r3, [r3, #8]
80050e4: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80050e6: 687b ldr r3, [r7, #4]
80050e8: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Channel | hdma->Init.Direction |
80050ea: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
80050ec: 687b ldr r3, [r7, #4]
80050ee: 691b ldr r3, [r3, #16]
80050f0: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80050f2: 687b ldr r3, [r7, #4]
80050f4: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
80050f6: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
80050f8: 687b ldr r3, [r7, #4]
80050fa: 699b ldr r3, [r3, #24]
80050fc: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
80050fe: 687b ldr r3, [r7, #4]
8005100: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8005102: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8005104: 687b ldr r3, [r7, #4]
8005106: 6a1b ldr r3, [r3, #32]
8005108: 4313 orrs r3, r2
tmp |= hdma->Init.Channel | hdma->Init.Direction |
800510a: 697a ldr r2, [r7, #20]
800510c: 4313 orrs r3, r2
800510e: 617b str r3, [r7, #20]
/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
8005110: 687b ldr r3, [r7, #4]
8005112: 6a5b ldr r3, [r3, #36] ; 0x24
8005114: 2b04 cmp r3, #4
8005116: d107 bne.n 8005128 <HAL_DMA_Init+0xc8>
{
/* Get memory burst and peripheral burst */
tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
8005118: 687b ldr r3, [r7, #4]
800511a: 6ada ldr r2, [r3, #44] ; 0x2c
800511c: 687b ldr r3, [r7, #4]
800511e: 6b1b ldr r3, [r3, #48] ; 0x30
8005120: 4313 orrs r3, r2
8005122: 697a ldr r2, [r7, #20]
8005124: 4313 orrs r3, r2
8005126: 617b str r3, [r7, #20]
}
/* Write to DMA Stream CR register */
hdma->Instance->CR = tmp;
8005128: 687b ldr r3, [r7, #4]
800512a: 681b ldr r3, [r3, #0]
800512c: 697a ldr r2, [r7, #20]
800512e: 601a str r2, [r3, #0]
/* Get the FCR register value */
tmp = hdma->Instance->FCR;
8005130: 687b ldr r3, [r7, #4]
8005132: 681b ldr r3, [r3, #0]
8005134: 695b ldr r3, [r3, #20]
8005136: 617b str r3, [r7, #20]
/* Clear Direct mode and FIFO threshold bits */
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
8005138: 697b ldr r3, [r7, #20]
800513a: f023 0307 bic.w r3, r3, #7
800513e: 617b str r3, [r7, #20]
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
8005140: 687b ldr r3, [r7, #4]
8005142: 6a5b ldr r3, [r3, #36] ; 0x24
8005144: 697a ldr r2, [r7, #20]
8005146: 4313 orrs r3, r2
8005148: 617b str r3, [r7, #20]
/* The FIFO threshold is not used when the FIFO mode is disabled */
if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
800514a: 687b ldr r3, [r7, #4]
800514c: 6a5b ldr r3, [r3, #36] ; 0x24
800514e: 2b04 cmp r3, #4
8005150: d117 bne.n 8005182 <HAL_DMA_Init+0x122>
{
/* Get the FIFO threshold */
tmp |= hdma->Init.FIFOThreshold;
8005152: 687b ldr r3, [r7, #4]
8005154: 6a9b ldr r3, [r3, #40] ; 0x28
8005156: 697a ldr r2, [r7, #20]
8005158: 4313 orrs r3, r2
800515a: 617b str r3, [r7, #20]
/* Check compatibility between FIFO threshold level and size of the memory burst */
/* for INCR4, INCR8, INCR16 bursts */
if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
800515c: 687b ldr r3, [r7, #4]
800515e: 6adb ldr r3, [r3, #44] ; 0x2c
8005160: 2b00 cmp r3, #0
8005162: d00e beq.n 8005182 <HAL_DMA_Init+0x122>
{
if (DMA_CheckFifoParam(hdma) != HAL_OK)
8005164: 6878 ldr r0, [r7, #4]
8005166: f000 f8bd bl 80052e4 <DMA_CheckFifoParam>
800516a: 4603 mov r3, r0
800516c: 2b00 cmp r3, #0
800516e: d008 beq.n 8005182 <HAL_DMA_Init+0x122>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
8005170: 687b ldr r3, [r7, #4]
8005172: 2240 movs r2, #64 ; 0x40
8005174: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8005176: 687b ldr r3, [r7, #4]
8005178: 2201 movs r2, #1
800517a: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_ERROR;
800517e: 2301 movs r3, #1
8005180: e016 b.n 80051b0 <HAL_DMA_Init+0x150>
}
}
}
/* Write to DMA Stream FCR */
hdma->Instance->FCR = tmp;
8005182: 687b ldr r3, [r7, #4]
8005184: 681b ldr r3, [r3, #0]
8005186: 697a ldr r2, [r7, #20]
8005188: 615a str r2, [r3, #20]
/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
800518a: 6878 ldr r0, [r7, #4]
800518c: f000 f874 bl 8005278 <DMA_CalcBaseAndBitshift>
8005190: 4603 mov r3, r0
8005192: 60fb str r3, [r7, #12]
/* Clear all interrupt flags */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8005194: 687b ldr r3, [r7, #4]
8005196: 6ddb ldr r3, [r3, #92] ; 0x5c
8005198: 223f movs r2, #63 ; 0x3f
800519a: 409a lsls r2, r3
800519c: 68fb ldr r3, [r7, #12]
800519e: 609a str r2, [r3, #8]
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80051a0: 687b ldr r3, [r7, #4]
80051a2: 2200 movs r2, #0
80051a4: 655a str r2, [r3, #84] ; 0x54
/* Initialize the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80051a6: 687b ldr r3, [r7, #4]
80051a8: 2201 movs r2, #1
80051aa: f883 2035 strb.w r2, [r3, #53] ; 0x35
return HAL_OK;
80051ae: 2300 movs r3, #0
}
80051b0: 4618 mov r0, r3
80051b2: 3718 adds r7, #24
80051b4: 46bd mov sp, r7
80051b6: bd80 pop {r7, pc}
80051b8: f010803f .word 0xf010803f
080051bc <HAL_DMA_DeInit>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{
80051bc: b580 push {r7, lr}
80051be: b084 sub sp, #16
80051c0: af00 add r7, sp, #0
80051c2: 6078 str r0, [r7, #4]
DMA_Base_Registers *regs;
/* Check the DMA peripheral state */
if(hdma == NULL)
80051c4: 687b ldr r3, [r7, #4]
80051c6: 2b00 cmp r3, #0
80051c8: d101 bne.n 80051ce <HAL_DMA_DeInit+0x12>
{
return HAL_ERROR;
80051ca: 2301 movs r3, #1
80051cc: e050 b.n 8005270 <HAL_DMA_DeInit+0xb4>
}
/* Check the DMA peripheral state */
if(hdma->State == HAL_DMA_STATE_BUSY)
80051ce: 687b ldr r3, [r7, #4]
80051d0: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
80051d4: b2db uxtb r3, r3
80051d6: 2b02 cmp r3, #2
80051d8: d101 bne.n 80051de <HAL_DMA_DeInit+0x22>
{
/* Return error status */
return HAL_BUSY;
80051da: 2302 movs r3, #2
80051dc: e048 b.n 8005270 <HAL_DMA_DeInit+0xb4>
/* Check the parameters */
assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
/* Disable the selected DMA Streamx */
__HAL_DMA_DISABLE(hdma);
80051de: 687b ldr r3, [r7, #4]
80051e0: 681b ldr r3, [r3, #0]
80051e2: 681a ldr r2, [r3, #0]
80051e4: 687b ldr r3, [r7, #4]
80051e6: 681b ldr r3, [r3, #0]
80051e8: f022 0201 bic.w r2, r2, #1
80051ec: 601a str r2, [r3, #0]
/* Reset DMA Streamx control register */
hdma->Instance->CR = 0U;
80051ee: 687b ldr r3, [r7, #4]
80051f0: 681b ldr r3, [r3, #0]
80051f2: 2200 movs r2, #0
80051f4: 601a str r2, [r3, #0]
/* Reset DMA Streamx number of data to transfer register */
hdma->Instance->NDTR = 0U;
80051f6: 687b ldr r3, [r7, #4]
80051f8: 681b ldr r3, [r3, #0]
80051fa: 2200 movs r2, #0
80051fc: 605a str r2, [r3, #4]
/* Reset DMA Streamx peripheral address register */
hdma->Instance->PAR = 0U;
80051fe: 687b ldr r3, [r7, #4]
8005200: 681b ldr r3, [r3, #0]
8005202: 2200 movs r2, #0
8005204: 609a str r2, [r3, #8]
/* Reset DMA Streamx memory 0 address register */
hdma->Instance->M0AR = 0U;
8005206: 687b ldr r3, [r7, #4]
8005208: 681b ldr r3, [r3, #0]
800520a: 2200 movs r2, #0
800520c: 60da str r2, [r3, #12]
/* Reset DMA Streamx memory 1 address register */
hdma->Instance->M1AR = 0U;
800520e: 687b ldr r3, [r7, #4]
8005210: 681b ldr r3, [r3, #0]
8005212: 2200 movs r2, #0
8005214: 611a str r2, [r3, #16]
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021U;
8005216: 687b ldr r3, [r7, #4]
8005218: 681b ldr r3, [r3, #0]
800521a: 2221 movs r2, #33 ; 0x21
800521c: 615a str r2, [r3, #20]
/* Get DMA steam Base Address */
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
800521e: 6878 ldr r0, [r7, #4]
8005220: f000 f82a bl 8005278 <DMA_CalcBaseAndBitshift>
8005224: 4603 mov r3, r0
8005226: 60fb str r3, [r7, #12]
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8005228: 687b ldr r3, [r7, #4]
800522a: 6ddb ldr r3, [r3, #92] ; 0x5c
800522c: 223f movs r2, #63 ; 0x3f
800522e: 409a lsls r2, r3
8005230: 68fb ldr r3, [r7, #12]
8005232: 609a str r2, [r3, #8]
/* Clean all callbacks */
hdma->XferCpltCallback = NULL;
8005234: 687b ldr r3, [r7, #4]
8005236: 2200 movs r2, #0
8005238: 63da str r2, [r3, #60] ; 0x3c
hdma->XferHalfCpltCallback = NULL;
800523a: 687b ldr r3, [r7, #4]
800523c: 2200 movs r2, #0
800523e: 641a str r2, [r3, #64] ; 0x40
hdma->XferM1CpltCallback = NULL;
8005240: 687b ldr r3, [r7, #4]
8005242: 2200 movs r2, #0
8005244: 645a str r2, [r3, #68] ; 0x44
hdma->XferM1HalfCpltCallback = NULL;
8005246: 687b ldr r3, [r7, #4]
8005248: 2200 movs r2, #0
800524a: 649a str r2, [r3, #72] ; 0x48
hdma->XferErrorCallback = NULL;
800524c: 687b ldr r3, [r7, #4]
800524e: 2200 movs r2, #0
8005250: 64da str r2, [r3, #76] ; 0x4c
hdma->XferAbortCallback = NULL;
8005252: 687b ldr r3, [r7, #4]
8005254: 2200 movs r2, #0
8005256: 651a str r2, [r3, #80] ; 0x50
/* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8005258: 687b ldr r3, [r7, #4]
800525a: 2200 movs r2, #0
800525c: 655a str r2, [r3, #84] ; 0x54
/* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
800525e: 687b ldr r3, [r7, #4]
8005260: 2200 movs r2, #0
8005262: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Release Lock */
__HAL_UNLOCK(hdma);
8005266: 687b ldr r3, [r7, #4]
8005268: 2200 movs r2, #0
800526a: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_OK;
800526e: 2300 movs r3, #0
}
8005270: 4618 mov r0, r3
8005272: 3710 adds r7, #16
8005274: 46bd mov sp, r7
8005276: bd80 pop {r7, pc}
08005278 <DMA_CalcBaseAndBitshift>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
{
8005278: b480 push {r7}
800527a: b085 sub sp, #20
800527c: af00 add r7, sp, #0
800527e: 6078 str r0, [r7, #4]
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
8005280: 687b ldr r3, [r7, #4]
8005282: 681b ldr r3, [r3, #0]
8005284: b2db uxtb r3, r3
8005286: 3b10 subs r3, #16
8005288: 4a13 ldr r2, [pc, #76] ; (80052d8 <DMA_CalcBaseAndBitshift+0x60>)
800528a: fba2 2303 umull r2, r3, r2, r3
800528e: 091b lsrs r3, r3, #4
8005290: 60fb str r3, [r7, #12]
/* lookup table for necessary bitshift of flags within status registers */
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
hdma->StreamIndex = flagBitshiftOffset[stream_number];
8005292: 4a12 ldr r2, [pc, #72] ; (80052dc <DMA_CalcBaseAndBitshift+0x64>)
8005294: 68fb ldr r3, [r7, #12]
8005296: 4413 add r3, r2
8005298: 781b ldrb r3, [r3, #0]
800529a: 461a mov r2, r3
800529c: 687b ldr r3, [r7, #4]
800529e: 65da str r2, [r3, #92] ; 0x5c
if (stream_number > 3U)
80052a0: 68fb ldr r3, [r7, #12]
80052a2: 2b03 cmp r3, #3
80052a4: d908 bls.n 80052b8 <DMA_CalcBaseAndBitshift+0x40>
{
/* return pointer to HISR and HIFCR */
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
80052a6: 687b ldr r3, [r7, #4]
80052a8: 681b ldr r3, [r3, #0]
80052aa: 461a mov r2, r3
80052ac: 4b0c ldr r3, [pc, #48] ; (80052e0 <DMA_CalcBaseAndBitshift+0x68>)
80052ae: 4013 ands r3, r2
80052b0: 1d1a adds r2, r3, #4
80052b2: 687b ldr r3, [r7, #4]
80052b4: 659a str r2, [r3, #88] ; 0x58
80052b6: e006 b.n 80052c6 <DMA_CalcBaseAndBitshift+0x4e>
}
else
{
/* return pointer to LISR and LIFCR */
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
80052b8: 687b ldr r3, [r7, #4]
80052ba: 681b ldr r3, [r3, #0]
80052bc: 461a mov r2, r3
80052be: 4b08 ldr r3, [pc, #32] ; (80052e0 <DMA_CalcBaseAndBitshift+0x68>)
80052c0: 4013 ands r3, r2
80052c2: 687a ldr r2, [r7, #4]
80052c4: 6593 str r3, [r2, #88] ; 0x58
}
return hdma->StreamBaseAddress;
80052c6: 687b ldr r3, [r7, #4]
80052c8: 6d9b ldr r3, [r3, #88] ; 0x58
}
80052ca: 4618 mov r0, r3
80052cc: 3714 adds r7, #20
80052ce: 46bd mov sp, r7
80052d0: f85d 7b04 ldr.w r7, [sp], #4
80052d4: 4770 bx lr
80052d6: bf00 nop
80052d8: aaaaaaab .word 0xaaaaaaab
80052dc: 0800e388 .word 0x0800e388
80052e0: fffffc00 .word 0xfffffc00
080052e4 <DMA_CheckFifoParam>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{
80052e4: b480 push {r7}
80052e6: b085 sub sp, #20
80052e8: af00 add r7, sp, #0
80052ea: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80052ec: 2300 movs r3, #0
80052ee: 73fb strb r3, [r7, #15]
uint32_t tmp = hdma->Init.FIFOThreshold;
80052f0: 687b ldr r3, [r7, #4]
80052f2: 6a9b ldr r3, [r3, #40] ; 0x28
80052f4: 60bb str r3, [r7, #8]
/* Memory Data size equal to Byte */
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
80052f6: 687b ldr r3, [r7, #4]
80052f8: 699b ldr r3, [r3, #24]
80052fa: 2b00 cmp r3, #0
80052fc: d11f bne.n 800533e <DMA_CheckFifoParam+0x5a>
{
switch (tmp)
80052fe: 68bb ldr r3, [r7, #8]
8005300: 2b03 cmp r3, #3
8005302: d855 bhi.n 80053b0 <DMA_CheckFifoParam+0xcc>
8005304: a201 add r2, pc, #4 ; (adr r2, 800530c <DMA_CheckFifoParam+0x28>)
8005306: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800530a: bf00 nop
800530c: 0800531d .word 0x0800531d
8005310: 0800532f .word 0x0800532f
8005314: 0800531d .word 0x0800531d
8005318: 080053b1 .word 0x080053b1
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
800531c: 687b ldr r3, [r7, #4]
800531e: 6adb ldr r3, [r3, #44] ; 0x2c
8005320: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005324: 2b00 cmp r3, #0
8005326: d045 beq.n 80053b4 <DMA_CheckFifoParam+0xd0>
{
status = HAL_ERROR;
8005328: 2301 movs r3, #1
800532a: 73fb strb r3, [r7, #15]
}
break;
800532c: e042 b.n 80053b4 <DMA_CheckFifoParam+0xd0>
case DMA_FIFO_THRESHOLD_HALFFULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
800532e: 687b ldr r3, [r7, #4]
8005330: 6adb ldr r3, [r3, #44] ; 0x2c
8005332: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
8005336: d13f bne.n 80053b8 <DMA_CheckFifoParam+0xd4>
{
status = HAL_ERROR;
8005338: 2301 movs r3, #1
800533a: 73fb strb r3, [r7, #15]
}
break;
800533c: e03c b.n 80053b8 <DMA_CheckFifoParam+0xd4>
break;
}
}
/* Memory Data size equal to Half-Word */
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
800533e: 687b ldr r3, [r7, #4]
8005340: 699b ldr r3, [r3, #24]
8005342: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8005346: d121 bne.n 800538c <DMA_CheckFifoParam+0xa8>
{
switch (tmp)
8005348: 68bb ldr r3, [r7, #8]
800534a: 2b03 cmp r3, #3
800534c: d836 bhi.n 80053bc <DMA_CheckFifoParam+0xd8>
800534e: a201 add r2, pc, #4 ; (adr r2, 8005354 <DMA_CheckFifoParam+0x70>)
8005350: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005354: 08005365 .word 0x08005365
8005358: 0800536b .word 0x0800536b
800535c: 08005365 .word 0x08005365
8005360: 0800537d .word 0x0800537d
{
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
status = HAL_ERROR;
8005364: 2301 movs r3, #1
8005366: 73fb strb r3, [r7, #15]
break;
8005368: e02f b.n 80053ca <DMA_CheckFifoParam+0xe6>
case DMA_FIFO_THRESHOLD_HALFFULL:
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
800536a: 687b ldr r3, [r7, #4]
800536c: 6adb ldr r3, [r3, #44] ; 0x2c
800536e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8005372: 2b00 cmp r3, #0
8005374: d024 beq.n 80053c0 <DMA_CheckFifoParam+0xdc>
{
status = HAL_ERROR;
8005376: 2301 movs r3, #1
8005378: 73fb strb r3, [r7, #15]
}
break;
800537a: e021 b.n 80053c0 <DMA_CheckFifoParam+0xdc>
case DMA_FIFO_THRESHOLD_FULL:
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
800537c: 687b ldr r3, [r7, #4]
800537e: 6adb ldr r3, [r3, #44] ; 0x2c
8005380: f1b3 7fc0 cmp.w r3, #25165824 ; 0x1800000
8005384: d11e bne.n 80053c4 <DMA_CheckFifoParam+0xe0>
{
status = HAL_ERROR;
8005386: 2301 movs r3, #1
8005388: 73fb strb r3, [r7, #15]
}
break;
800538a: e01b b.n 80053c4 <DMA_CheckFifoParam+0xe0>
}
/* Memory Data size equal to Word */
else
{
switch (tmp)
800538c: 68bb ldr r3, [r7, #8]
800538e: 2b02 cmp r3, #2
8005390: d902 bls.n 8005398 <DMA_CheckFifoParam+0xb4>
8005392: 2b03 cmp r3, #3
8005394: d003 beq.n 800539e <DMA_CheckFifoParam+0xba>
{
status = HAL_ERROR;
}
break;
default:
break;
8005396: e018 b.n 80053ca <DMA_CheckFifoParam+0xe6>
status = HAL_ERROR;
8005398: 2301 movs r3, #1
800539a: 73fb strb r3, [r7, #15]
break;
800539c: e015 b.n 80053ca <DMA_CheckFifoParam+0xe6>
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
800539e: 687b ldr r3, [r7, #4]
80053a0: 6adb ldr r3, [r3, #44] ; 0x2c
80053a2: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80053a6: 2b00 cmp r3, #0
80053a8: d00e beq.n 80053c8 <DMA_CheckFifoParam+0xe4>
status = HAL_ERROR;
80053aa: 2301 movs r3, #1
80053ac: 73fb strb r3, [r7, #15]
break;
80053ae: e00b b.n 80053c8 <DMA_CheckFifoParam+0xe4>
break;
80053b0: bf00 nop
80053b2: e00a b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053b4: bf00 nop
80053b6: e008 b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053b8: bf00 nop
80053ba: e006 b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053bc: bf00 nop
80053be: e004 b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053c0: bf00 nop
80053c2: e002 b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053c4: bf00 nop
80053c6: e000 b.n 80053ca <DMA_CheckFifoParam+0xe6>
break;
80053c8: bf00 nop
}
}
return status;
80053ca: 7bfb ldrb r3, [r7, #15]
}
80053cc: 4618 mov r0, r3
80053ce: 3714 adds r7, #20
80053d0: 46bd mov sp, r7
80053d2: f85d 7b04 ldr.w r7, [sp], #4
80053d6: 4770 bx lr
080053d8 <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
80053d8: b580 push {r7, lr}
80053da: b082 sub sp, #8
80053dc: af00 add r7, sp, #0
80053de: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if(hdma2d == NULL)
80053e0: 687b ldr r3, [r7, #4]
80053e2: 2b00 cmp r3, #0
80053e4: d101 bne.n 80053ea <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
80053e6: 2301 movs r3, #1
80053e8: e039 b.n 800545e <HAL_DMA2D_Init+0x86>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
80053ea: 687b ldr r3, [r7, #4]
80053ec: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
80053f0: b2db uxtb r3, r3
80053f2: 2b00 cmp r3, #0
80053f4: d106 bne.n 8005404 <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
80053f6: 687b ldr r3, [r7, #4]
80053f8: 2200 movs r2, #0
80053fa: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
80053fe: 6878 ldr r0, [r7, #4]
8005400: f7fe fb06 bl 8003a10 <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005404: 687b ldr r3, [r7, #4]
8005406: 2202 movs r2, #2
8005408: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
800540c: 687b ldr r3, [r7, #4]
800540e: 681b ldr r3, [r3, #0]
8005410: 681b ldr r3, [r3, #0]
8005412: f423 3140 bic.w r1, r3, #196608 ; 0x30000
8005416: 687b ldr r3, [r7, #4]
8005418: 685a ldr r2, [r3, #4]
800541a: 687b ldr r3, [r7, #4]
800541c: 681b ldr r3, [r3, #0]
800541e: 430a orrs r2, r1
8005420: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
8005422: 687b ldr r3, [r7, #4]
8005424: 681b ldr r3, [r3, #0]
8005426: 6b5b ldr r3, [r3, #52] ; 0x34
8005428: f023 0107 bic.w r1, r3, #7
800542c: 687b ldr r3, [r7, #4]
800542e: 689a ldr r2, [r3, #8]
8005430: 687b ldr r3, [r7, #4]
8005432: 681b ldr r3, [r3, #0]
8005434: 430a orrs r2, r1
8005436: 635a str r2, [r3, #52] ; 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
8005438: 687b ldr r3, [r7, #4]
800543a: 681b ldr r3, [r3, #0]
800543c: 6c1a ldr r2, [r3, #64] ; 0x40
800543e: 4b0a ldr r3, [pc, #40] ; (8005468 <HAL_DMA2D_Init+0x90>)
8005440: 4013 ands r3, r2
8005442: 687a ldr r2, [r7, #4]
8005444: 68d1 ldr r1, [r2, #12]
8005446: 687a ldr r2, [r7, #4]
8005448: 6812 ldr r2, [r2, #0]
800544a: 430b orrs r3, r1
800544c: 6413 str r3, [r2, #64] ; 0x40
MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
800544e: 687b ldr r3, [r7, #4]
8005450: 2200 movs r2, #0
8005452: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005454: 687b ldr r3, [r7, #4]
8005456: 2201 movs r2, #1
8005458: f883 2039 strb.w r2, [r3, #57] ; 0x39
return HAL_OK;
800545c: 2300 movs r3, #0
}
800545e: 4618 mov r0, r3
8005460: 3708 adds r7, #8
8005462: 46bd mov sp, r7
8005464: bd80 pop {r7, pc}
8005466: bf00 nop
8005468: ffffc000 .word 0xffffc000
0800546c <HAL_DMA2D_Start>:
* @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
* @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
800546c: b580 push {r7, lr}
800546e: b086 sub sp, #24
8005470: af02 add r7, sp, #8
8005472: 60f8 str r0, [r7, #12]
8005474: 60b9 str r1, [r7, #8]
8005476: 607a str r2, [r7, #4]
8005478: 603b str r3, [r7, #0]
/* Check the parameters */
assert_param(IS_DMA2D_LINE(Height));
assert_param(IS_DMA2D_PIXEL(Width));
/* Process locked */
__HAL_LOCK(hdma2d);
800547a: 68fb ldr r3, [r7, #12]
800547c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8005480: 2b01 cmp r3, #1
8005482: d101 bne.n 8005488 <HAL_DMA2D_Start+0x1c>
8005484: 2302 movs r3, #2
8005486: e018 b.n 80054ba <HAL_DMA2D_Start+0x4e>
8005488: 68fb ldr r3, [r7, #12]
800548a: 2201 movs r2, #1
800548c: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8005490: 68fb ldr r3, [r7, #12]
8005492: 2202 movs r2, #2
8005494: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Configure the source, destination address and the data size */
DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
8005498: 69bb ldr r3, [r7, #24]
800549a: 9300 str r3, [sp, #0]
800549c: 683b ldr r3, [r7, #0]
800549e: 687a ldr r2, [r7, #4]
80054a0: 68b9 ldr r1, [r7, #8]
80054a2: 68f8 ldr r0, [r7, #12]
80054a4: f000 f988 bl 80057b8 <DMA2D_SetConfig>
/* Enable the Peripheral */
__HAL_DMA2D_ENABLE(hdma2d);
80054a8: 68fb ldr r3, [r7, #12]
80054aa: 681b ldr r3, [r3, #0]
80054ac: 681a ldr r2, [r3, #0]
80054ae: 68fb ldr r3, [r7, #12]
80054b0: 681b ldr r3, [r3, #0]
80054b2: f042 0201 orr.w r2, r2, #1
80054b6: 601a str r2, [r3, #0]
return HAL_OK;
80054b8: 2300 movs r3, #0
}
80054ba: 4618 mov r0, r3
80054bc: 3710 adds r7, #16
80054be: 46bd mov sp, r7
80054c0: bd80 pop {r7, pc}
080054c2 <HAL_DMA2D_PollForTransfer>:
* the configuration information for the DMA2D.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
{
80054c2: b580 push {r7, lr}
80054c4: b086 sub sp, #24
80054c6: af00 add r7, sp, #0
80054c8: 6078 str r0, [r7, #4]
80054ca: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t layer_start;
__IO uint32_t isrflags = 0x0U;
80054cc: 2300 movs r3, #0
80054ce: 60fb str r3, [r7, #12]
/* Polling for DMA2D transfer */
if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
80054d0: 687b ldr r3, [r7, #4]
80054d2: 681b ldr r3, [r3, #0]
80054d4: 681b ldr r3, [r3, #0]
80054d6: f003 0301 and.w r3, r3, #1
80054da: 2b00 cmp r3, #0
80054dc: d056 beq.n 800558c <HAL_DMA2D_PollForTransfer+0xca>
{
/* Get tick */
tickstart = HAL_GetTick();
80054de: f7ff f807 bl 80044f0 <HAL_GetTick>
80054e2: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
80054e4: e04b b.n 800557e <HAL_DMA2D_PollForTransfer+0xbc>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
80054e6: 687b ldr r3, [r7, #4]
80054e8: 681b ldr r3, [r3, #0]
80054ea: 685b ldr r3, [r3, #4]
80054ec: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
80054ee: 68fb ldr r3, [r7, #12]
80054f0: f003 0321 and.w r3, r3, #33 ; 0x21
80054f4: 2b00 cmp r3, #0
80054f6: d023 beq.n 8005540 <HAL_DMA2D_PollForTransfer+0x7e>
{
if ((isrflags & DMA2D_FLAG_CE) != 0U)
80054f8: 68fb ldr r3, [r7, #12]
80054fa: f003 0320 and.w r3, r3, #32
80054fe: 2b00 cmp r3, #0
8005500: d005 beq.n 800550e <HAL_DMA2D_PollForTransfer+0x4c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8005502: 687b ldr r3, [r7, #4]
8005504: 6bdb ldr r3, [r3, #60] ; 0x3c
8005506: f043 0202 orr.w r2, r3, #2
800550a: 687b ldr r3, [r7, #4]
800550c: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
800550e: 68fb ldr r3, [r7, #12]
8005510: f003 0301 and.w r3, r3, #1
8005514: 2b00 cmp r3, #0
8005516: d005 beq.n 8005524 <HAL_DMA2D_PollForTransfer+0x62>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8005518: 687b ldr r3, [r7, #4]
800551a: 6bdb ldr r3, [r3, #60] ; 0x3c
800551c: f043 0201 orr.w r2, r3, #1
8005520: 687b ldr r3, [r7, #4]
8005522: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the transfer and configuration error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
8005524: 687b ldr r3, [r7, #4]
8005526: 681b ldr r3, [r3, #0]
8005528: 2221 movs r2, #33 ; 0x21
800552a: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
800552c: 687b ldr r3, [r7, #4]
800552e: 2204 movs r2, #4
8005530: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005534: 687b ldr r3, [r7, #4]
8005536: 2200 movs r2, #0
8005538: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
800553c: 2301 movs r3, #1
800553e: e0a5 b.n 800568c <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005540: 683b ldr r3, [r7, #0]
8005542: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8005546: d01a beq.n 800557e <HAL_DMA2D_PollForTransfer+0xbc>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
8005548: f7fe ffd2 bl 80044f0 <HAL_GetTick>
800554c: 4602 mov r2, r0
800554e: 697b ldr r3, [r7, #20]
8005550: 1ad3 subs r3, r2, r3
8005552: 683a ldr r2, [r7, #0]
8005554: 429a cmp r2, r3
8005556: d302 bcc.n 800555e <HAL_DMA2D_PollForTransfer+0x9c>
8005558: 683b ldr r3, [r7, #0]
800555a: 2b00 cmp r3, #0
800555c: d10f bne.n 800557e <HAL_DMA2D_PollForTransfer+0xbc>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
800555e: 687b ldr r3, [r7, #4]
8005560: 6bdb ldr r3, [r3, #60] ; 0x3c
8005562: f043 0220 orr.w r2, r3, #32
8005566: 687b ldr r3, [r7, #4]
8005568: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
800556a: 687b ldr r3, [r7, #4]
800556c: 2203 movs r2, #3
800556e: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005572: 687b ldr r3, [r7, #4]
8005574: 2200 movs r2, #0
8005576: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
800557a: 2303 movs r3, #3
800557c: e086 b.n 800568c <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
800557e: 687b ldr r3, [r7, #4]
8005580: 681b ldr r3, [r3, #0]
8005582: 685b ldr r3, [r3, #4]
8005584: f003 0302 and.w r3, r3, #2
8005588: 2b00 cmp r3, #0
800558a: d0ac beq.n 80054e6 <HAL_DMA2D_PollForTransfer+0x24>
}
}
}
}
/* Polling for CLUT loading (foreground or background) */
layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
800558c: 687b ldr r3, [r7, #4]
800558e: 681b ldr r3, [r3, #0]
8005590: 69db ldr r3, [r3, #28]
8005592: f003 0320 and.w r3, r3, #32
8005596: 613b str r3, [r7, #16]
layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
8005598: 687b ldr r3, [r7, #4]
800559a: 681b ldr r3, [r3, #0]
800559c: 6a5b ldr r3, [r3, #36] ; 0x24
800559e: f003 0320 and.w r3, r3, #32
80055a2: 693a ldr r2, [r7, #16]
80055a4: 4313 orrs r3, r2
80055a6: 613b str r3, [r7, #16]
if (layer_start != 0U)
80055a8: 693b ldr r3, [r7, #16]
80055aa: 2b00 cmp r3, #0
80055ac: d061 beq.n 8005672 <HAL_DMA2D_PollForTransfer+0x1b0>
{
/* Get tick */
tickstart = HAL_GetTick();
80055ae: f7fe ff9f bl 80044f0 <HAL_GetTick>
80055b2: 6178 str r0, [r7, #20]
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
80055b4: e056 b.n 8005664 <HAL_DMA2D_PollForTransfer+0x1a2>
{
isrflags = READ_REG(hdma2d->Instance->ISR);
80055b6: 687b ldr r3, [r7, #4]
80055b8: 681b ldr r3, [r3, #0]
80055ba: 685b ldr r3, [r3, #4]
80055bc: 60fb str r3, [r7, #12]
if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
80055be: 68fb ldr r3, [r7, #12]
80055c0: f003 0329 and.w r3, r3, #41 ; 0x29
80055c4: 2b00 cmp r3, #0
80055c6: d02e beq.n 8005626 <HAL_DMA2D_PollForTransfer+0x164>
{
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
80055c8: 68fb ldr r3, [r7, #12]
80055ca: f003 0308 and.w r3, r3, #8
80055ce: 2b00 cmp r3, #0
80055d0: d005 beq.n 80055de <HAL_DMA2D_PollForTransfer+0x11c>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
80055d2: 687b ldr r3, [r7, #4]
80055d4: 6bdb ldr r3, [r3, #60] ; 0x3c
80055d6: f043 0204 orr.w r2, r3, #4
80055da: 687b ldr r3, [r7, #4]
80055dc: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_CE) != 0U)
80055de: 68fb ldr r3, [r7, #12]
80055e0: f003 0320 and.w r3, r3, #32
80055e4: 2b00 cmp r3, #0
80055e6: d005 beq.n 80055f4 <HAL_DMA2D_PollForTransfer+0x132>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
80055e8: 687b ldr r3, [r7, #4]
80055ea: 6bdb ldr r3, [r3, #60] ; 0x3c
80055ec: f043 0202 orr.w r2, r3, #2
80055f0: 687b ldr r3, [r7, #4]
80055f2: 63da str r2, [r3, #60] ; 0x3c
}
if ((isrflags & DMA2D_FLAG_TE) != 0U)
80055f4: 68fb ldr r3, [r7, #12]
80055f6: f003 0301 and.w r3, r3, #1
80055fa: 2b00 cmp r3, #0
80055fc: d005 beq.n 800560a <HAL_DMA2D_PollForTransfer+0x148>
{
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
80055fe: 687b ldr r3, [r7, #4]
8005600: 6bdb ldr r3, [r3, #60] ; 0x3c
8005602: f043 0201 orr.w r2, r3, #1
8005606: 687b ldr r3, [r7, #4]
8005608: 63da str r2, [r3, #60] ; 0x3c
}
/* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
800560a: 687b ldr r3, [r7, #4]
800560c: 681b ldr r3, [r3, #0]
800560e: 2229 movs r2, #41 ; 0x29
8005610: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_ERROR;
8005612: 687b ldr r3, [r7, #4]
8005614: 2204 movs r2, #4
8005616: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
800561a: 687b ldr r3, [r7, #4]
800561c: 2200 movs r2, #0
800561e: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_ERROR;
8005622: 2301 movs r3, #1
8005624: e032 b.n 800568c <HAL_DMA2D_PollForTransfer+0x1ca>
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
8005626: 683b ldr r3, [r7, #0]
8005628: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800562c: d01a beq.n 8005664 <HAL_DMA2D_PollForTransfer+0x1a2>
{
if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
800562e: f7fe ff5f bl 80044f0 <HAL_GetTick>
8005632: 4602 mov r2, r0
8005634: 697b ldr r3, [r7, #20]
8005636: 1ad3 subs r3, r2, r3
8005638: 683a ldr r2, [r7, #0]
800563a: 429a cmp r2, r3
800563c: d302 bcc.n 8005644 <HAL_DMA2D_PollForTransfer+0x182>
800563e: 683b ldr r3, [r7, #0]
8005640: 2b00 cmp r3, #0
8005642: d10f bne.n 8005664 <HAL_DMA2D_PollForTransfer+0x1a2>
{
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
8005644: 687b ldr r3, [r7, #4]
8005646: 6bdb ldr r3, [r3, #60] ; 0x3c
8005648: f043 0220 orr.w r2, r3, #32
800564c: 687b ldr r3, [r7, #4]
800564e: 63da str r2, [r3, #60] ; 0x3c
/* Change the DMA2D state */
hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
8005650: 687b ldr r3, [r7, #4]
8005652: 2203 movs r2, #3
8005654: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005658: 687b ldr r3, [r7, #4]
800565a: 2200 movs r2, #0
800565c: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_TIMEOUT;
8005660: 2303 movs r3, #3
8005662: e013 b.n 800568c <HAL_DMA2D_PollForTransfer+0x1ca>
while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
8005664: 687b ldr r3, [r7, #4]
8005666: 681b ldr r3, [r3, #0]
8005668: 685b ldr r3, [r3, #4]
800566a: f003 0310 and.w r3, r3, #16
800566e: 2b00 cmp r3, #0
8005670: d0a1 beq.n 80055b6 <HAL_DMA2D_PollForTransfer+0xf4>
}
}
}
/* Clear the transfer complete and CLUT loading flags */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
8005672: 687b ldr r3, [r7, #4]
8005674: 681b ldr r3, [r3, #0]
8005676: 2212 movs r2, #18
8005678: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
800567a: 687b ldr r3, [r7, #4]
800567c: 2201 movs r2, #1
800567e: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8005682: 687b ldr r3, [r7, #4]
8005684: 2200 movs r2, #0
8005686: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
800568a: 2300 movs r3, #0
}
800568c: 4618 mov r0, r3
800568e: 3718 adds r7, #24
8005690: 46bd mov sp, r7
8005692: bd80 pop {r7, pc}
08005694 <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8005694: b480 push {r7}
8005696: b087 sub sp, #28
8005698: af00 add r7, sp, #0
800569a: 6078 str r0, [r7, #4]
800569c: 6039 str r1, [r7, #0]
uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
800569e: 687b ldr r3, [r7, #4]
80056a0: 685b ldr r3, [r3, #4]
80056a2: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Process locked */
__HAL_LOCK(hdma2d);
80056a6: 687b ldr r3, [r7, #4]
80056a8: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
80056ac: 2b01 cmp r3, #1
80056ae: d101 bne.n 80056b4 <HAL_DMA2D_ConfigLayer+0x20>
80056b0: 2302 movs r3, #2
80056b2: e079 b.n 80057a8 <HAL_DMA2D_ConfigLayer+0x114>
80056b4: 687b ldr r3, [r7, #4]
80056b6: 2201 movs r2, #1
80056b8: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
80056bc: 687b ldr r3, [r7, #4]
80056be: 2202 movs r2, #2
80056c0: f883 2039 strb.w r2, [r3, #57] ; 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
80056c4: 683b ldr r3, [r7, #0]
80056c6: 011b lsls r3, r3, #4
80056c8: 3318 adds r3, #24
80056ca: 687a ldr r2, [r7, #4]
80056cc: 4413 add r3, r2
80056ce: 613b str r3, [r7, #16]
#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
(pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
#else
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
80056d0: 693b ldr r3, [r7, #16]
80056d2: 685a ldr r2, [r3, #4]
80056d4: 693b ldr r3, [r7, #16]
80056d6: 689b ldr r3, [r3, #8]
80056d8: 041b lsls r3, r3, #16
80056da: 4313 orrs r3, r2
80056dc: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
80056de: 4b35 ldr r3, [pc, #212] ; (80057b4 <HAL_DMA2D_ConfigLayer+0x120>)
80056e0: 60fb str r3, [r7, #12]
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
80056e2: 693b ldr r3, [r7, #16]
80056e4: 685b ldr r3, [r3, #4]
80056e6: 2b0a cmp r3, #10
80056e8: d003 beq.n 80056f2 <HAL_DMA2D_ConfigLayer+0x5e>
80056ea: 693b ldr r3, [r7, #16]
80056ec: 685b ldr r3, [r3, #4]
80056ee: 2b09 cmp r3, #9
80056f0: d107 bne.n 8005702 <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
80056f2: 693b ldr r3, [r7, #16]
80056f4: 68db ldr r3, [r3, #12]
80056f6: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
80056fa: 697a ldr r2, [r7, #20]
80056fc: 4313 orrs r3, r2
80056fe: 617b str r3, [r7, #20]
8005700: e005 b.n 800570e <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8005702: 693b ldr r3, [r7, #16]
8005704: 68db ldr r3, [r3, #12]
8005706: 061b lsls r3, r3, #24
8005708: 697a ldr r2, [r7, #20]
800570a: 4313 orrs r3, r2
800570c: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
800570e: 683b ldr r3, [r7, #0]
8005710: 2b00 cmp r3, #0
8005712: d120 bne.n 8005756 <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8005714: 687b ldr r3, [r7, #4]
8005716: 681b ldr r3, [r3, #0]
8005718: 6a5a ldr r2, [r3, #36] ; 0x24
800571a: 68fb ldr r3, [r7, #12]
800571c: 43db mvns r3, r3
800571e: ea02 0103 and.w r1, r2, r3
8005722: 687b ldr r3, [r7, #4]
8005724: 681b ldr r3, [r3, #0]
8005726: 697a ldr r2, [r7, #20]
8005728: 430a orrs r2, r1
800572a: 625a str r2, [r3, #36] ; 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
800572c: 687b ldr r3, [r7, #4]
800572e: 681b ldr r3, [r3, #0]
8005730: 693a ldr r2, [r7, #16]
8005732: 6812 ldr r2, [r2, #0]
8005734: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005736: 693b ldr r3, [r7, #16]
8005738: 685b ldr r3, [r3, #4]
800573a: 2b0a cmp r3, #10
800573c: d003 beq.n 8005746 <HAL_DMA2D_ConfigLayer+0xb2>
800573e: 693b ldr r3, [r7, #16]
8005740: 685b ldr r3, [r3, #4]
8005742: 2b09 cmp r3, #9
8005744: d127 bne.n 8005796 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
8005746: 693b ldr r3, [r7, #16]
8005748: 68da ldr r2, [r3, #12]
800574a: 687b ldr r3, [r7, #4]
800574c: 681b ldr r3, [r3, #0]
800574e: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005752: 629a str r2, [r3, #40] ; 0x28
8005754: e01f b.n 8005796 <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8005756: 687b ldr r3, [r7, #4]
8005758: 681b ldr r3, [r3, #0]
800575a: 69da ldr r2, [r3, #28]
800575c: 68fb ldr r3, [r7, #12]
800575e: 43db mvns r3, r3
8005760: ea02 0103 and.w r1, r2, r3
8005764: 687b ldr r3, [r7, #4]
8005766: 681b ldr r3, [r3, #0]
8005768: 697a ldr r2, [r7, #20]
800576a: 430a orrs r2, r1
800576c: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
800576e: 687b ldr r3, [r7, #4]
8005770: 681b ldr r3, [r3, #0]
8005772: 693a ldr r2, [r7, #16]
8005774: 6812 ldr r2, [r2, #0]
8005776: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8005778: 693b ldr r3, [r7, #16]
800577a: 685b ldr r3, [r3, #4]
800577c: 2b0a cmp r3, #10
800577e: d003 beq.n 8005788 <HAL_DMA2D_ConfigLayer+0xf4>
8005780: 693b ldr r3, [r7, #16]
8005782: 685b ldr r3, [r3, #4]
8005784: 2b09 cmp r3, #9
8005786: d106 bne.n 8005796 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
8005788: 693b ldr r3, [r7, #16]
800578a: 68da ldr r2, [r3, #12]
800578c: 687b ldr r3, [r7, #4]
800578e: 681b ldr r3, [r3, #0]
8005790: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8005794: 621a str r2, [r3, #32]
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8005796: 687b ldr r3, [r7, #4]
8005798: 2201 movs r2, #1
800579a: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
800579e: 687b ldr r3, [r7, #4]
80057a0: 2200 movs r2, #0
80057a2: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
80057a6: 2300 movs r3, #0
}
80057a8: 4618 mov r0, r3
80057aa: 371c adds r7, #28
80057ac: 46bd mov sp, r7
80057ae: f85d 7b04 ldr.w r7, [sp], #4
80057b2: 4770 bx lr
80057b4: ff03000f .word 0xff03000f
080057b8 <DMA2D_SetConfig>:
* @param Width The width of data to be transferred from source to destination.
* @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
{
80057b8: b480 push {r7}
80057ba: b08b sub sp, #44 ; 0x2c
80057bc: af00 add r7, sp, #0
80057be: 60f8 str r0, [r7, #12]
80057c0: 60b9 str r1, [r7, #8]
80057c2: 607a str r2, [r7, #4]
80057c4: 603b str r3, [r7, #0]
uint32_t tmp2;
uint32_t tmp3;
uint32_t tmp4;
/* Configure DMA2D data size */
MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
80057c6: 68fb ldr r3, [r7, #12]
80057c8: 681b ldr r3, [r3, #0]
80057ca: 6c5b ldr r3, [r3, #68] ; 0x44
80057cc: f003 4140 and.w r1, r3, #3221225472 ; 0xc0000000
80057d0: 683b ldr r3, [r7, #0]
80057d2: 041a lsls r2, r3, #16
80057d4: 6b3b ldr r3, [r7, #48] ; 0x30
80057d6: 431a orrs r2, r3
80057d8: 68fb ldr r3, [r7, #12]
80057da: 681b ldr r3, [r3, #0]
80057dc: 430a orrs r2, r1
80057de: 645a str r2, [r3, #68] ; 0x44
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
80057e0: 68fb ldr r3, [r7, #12]
80057e2: 681b ldr r3, [r3, #0]
80057e4: 687a ldr r2, [r7, #4]
80057e6: 63da str r2, [r3, #60] ; 0x3c
/* Register to memory DMA2D mode selected */
if (hdma2d->Init.Mode == DMA2D_R2M)
80057e8: 68fb ldr r3, [r7, #12]
80057ea: 685b ldr r3, [r3, #4]
80057ec: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
80057f0: d174 bne.n 80058dc <DMA2D_SetConfig+0x124>
{
tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
80057f2: 68bb ldr r3, [r7, #8]
80057f4: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
80057f8: 623b str r3, [r7, #32]
tmp2 = pdata & DMA2D_OCOLR_RED_1;
80057fa: 68bb ldr r3, [r7, #8]
80057fc: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8005800: 61fb str r3, [r7, #28]
tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
8005802: 68bb ldr r3, [r7, #8]
8005804: f403 437f and.w r3, r3, #65280 ; 0xff00
8005808: 61bb str r3, [r7, #24]
tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
800580a: 68bb ldr r3, [r7, #8]
800580c: b2db uxtb r3, r3
800580e: 617b str r3, [r7, #20]
/* Prepare the value to be written to the OCOLR register according to the color mode */
if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
8005810: 68fb ldr r3, [r7, #12]
8005812: 689b ldr r3, [r3, #8]
8005814: 2b00 cmp r3, #0
8005816: d108 bne.n 800582a <DMA2D_SetConfig+0x72>
{
tmp = (tmp3 | tmp2 | tmp1| tmp4);
8005818: 69ba ldr r2, [r7, #24]
800581a: 69fb ldr r3, [r7, #28]
800581c: 431a orrs r2, r3
800581e: 6a3b ldr r3, [r7, #32]
8005820: 4313 orrs r3, r2
8005822: 697a ldr r2, [r7, #20]
8005824: 4313 orrs r3, r2
8005826: 627b str r3, [r7, #36] ; 0x24
8005828: e053 b.n 80058d2 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
800582a: 68fb ldr r3, [r7, #12]
800582c: 689b ldr r3, [r3, #8]
800582e: 2b01 cmp r3, #1
8005830: d106 bne.n 8005840 <DMA2D_SetConfig+0x88>
{
tmp = (tmp3 | tmp2 | tmp4);
8005832: 69ba ldr r2, [r7, #24]
8005834: 69fb ldr r3, [r7, #28]
8005836: 4313 orrs r3, r2
8005838: 697a ldr r2, [r7, #20]
800583a: 4313 orrs r3, r2
800583c: 627b str r3, [r7, #36] ; 0x24
800583e: e048 b.n 80058d2 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
8005840: 68fb ldr r3, [r7, #12]
8005842: 689b ldr r3, [r3, #8]
8005844: 2b02 cmp r3, #2
8005846: d111 bne.n 800586c <DMA2D_SetConfig+0xb4>
{
tmp2 = (tmp2 >> 19U);
8005848: 69fb ldr r3, [r7, #28]
800584a: 0cdb lsrs r3, r3, #19
800584c: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 10U);
800584e: 69bb ldr r3, [r7, #24]
8005850: 0a9b lsrs r3, r3, #10
8005852: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005854: 697b ldr r3, [r7, #20]
8005856: 08db lsrs r3, r3, #3
8005858: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
800585a: 69bb ldr r3, [r7, #24]
800585c: 015a lsls r2, r3, #5
800585e: 69fb ldr r3, [r7, #28]
8005860: 02db lsls r3, r3, #11
8005862: 4313 orrs r3, r2
8005864: 697a ldr r2, [r7, #20]
8005866: 4313 orrs r3, r2
8005868: 627b str r3, [r7, #36] ; 0x24
800586a: e032 b.n 80058d2 <DMA2D_SetConfig+0x11a>
}
else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
800586c: 68fb ldr r3, [r7, #12]
800586e: 689b ldr r3, [r3, #8]
8005870: 2b03 cmp r3, #3
8005872: d117 bne.n 80058a4 <DMA2D_SetConfig+0xec>
{
tmp1 = (tmp1 >> 31U);
8005874: 6a3b ldr r3, [r7, #32]
8005876: 0fdb lsrs r3, r3, #31
8005878: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 19U);
800587a: 69fb ldr r3, [r7, #28]
800587c: 0cdb lsrs r3, r3, #19
800587e: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 11U);
8005880: 69bb ldr r3, [r7, #24]
8005882: 0adb lsrs r3, r3, #11
8005884: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 3U );
8005886: 697b ldr r3, [r7, #20]
8005888: 08db lsrs r3, r3, #3
800588a: 617b str r3, [r7, #20]
tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
800588c: 69bb ldr r3, [r7, #24]
800588e: 015a lsls r2, r3, #5
8005890: 69fb ldr r3, [r7, #28]
8005892: 029b lsls r3, r3, #10
8005894: 431a orrs r2, r3
8005896: 6a3b ldr r3, [r7, #32]
8005898: 03db lsls r3, r3, #15
800589a: 4313 orrs r3, r2
800589c: 697a ldr r2, [r7, #20]
800589e: 4313 orrs r3, r2
80058a0: 627b str r3, [r7, #36] ; 0x24
80058a2: e016 b.n 80058d2 <DMA2D_SetConfig+0x11a>
}
else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
{
tmp1 = (tmp1 >> 28U);
80058a4: 6a3b ldr r3, [r7, #32]
80058a6: 0f1b lsrs r3, r3, #28
80058a8: 623b str r3, [r7, #32]
tmp2 = (tmp2 >> 20U);
80058aa: 69fb ldr r3, [r7, #28]
80058ac: 0d1b lsrs r3, r3, #20
80058ae: 61fb str r3, [r7, #28]
tmp3 = (tmp3 >> 12U);
80058b0: 69bb ldr r3, [r7, #24]
80058b2: 0b1b lsrs r3, r3, #12
80058b4: 61bb str r3, [r7, #24]
tmp4 = (tmp4 >> 4U );
80058b6: 697b ldr r3, [r7, #20]
80058b8: 091b lsrs r3, r3, #4
80058ba: 617b str r3, [r7, #20]
tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
80058bc: 69bb ldr r3, [r7, #24]
80058be: 011a lsls r2, r3, #4
80058c0: 69fb ldr r3, [r7, #28]
80058c2: 021b lsls r3, r3, #8
80058c4: 431a orrs r2, r3
80058c6: 6a3b ldr r3, [r7, #32]
80058c8: 031b lsls r3, r3, #12
80058ca: 4313 orrs r3, r2
80058cc: 697a ldr r2, [r7, #20]
80058ce: 4313 orrs r3, r2
80058d0: 627b str r3, [r7, #36] ; 0x24
}
/* Write to DMA2D OCOLR register */
WRITE_REG(hdma2d->Instance->OCOLR, tmp);
80058d2: 68fb ldr r3, [r7, #12]
80058d4: 681b ldr r3, [r3, #0]
80058d6: 6a7a ldr r2, [r7, #36] ; 0x24
80058d8: 639a str r2, [r3, #56] ; 0x38
else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
{
/* Configure DMA2D source address */
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
}
}
80058da: e003 b.n 80058e4 <DMA2D_SetConfig+0x12c>
WRITE_REG(hdma2d->Instance->FGMAR, pdata);
80058dc: 68fb ldr r3, [r7, #12]
80058de: 681b ldr r3, [r3, #0]
80058e0: 68ba ldr r2, [r7, #8]
80058e2: 60da str r2, [r3, #12]
}
80058e4: bf00 nop
80058e6: 372c adds r7, #44 ; 0x2c
80058e8: 46bd mov sp, r7
80058ea: f85d 7b04 ldr.w r7, [sp], #4
80058ee: 4770 bx lr
080058f0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80058f0: b480 push {r7}
80058f2: b089 sub sp, #36 ; 0x24
80058f4: af00 add r7, sp, #0
80058f6: 6078 str r0, [r7, #4]
80058f8: 6039 str r1, [r7, #0]
uint32_t position = 0x00;
80058fa: 2300 movs r3, #0
80058fc: 61fb str r3, [r7, #28]
uint32_t ioposition = 0x00;
80058fe: 2300 movs r3, #0
8005900: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00;
8005902: 2300 movs r3, #0
8005904: 613b str r3, [r7, #16]
uint32_t temp = 0x00;
8005906: 2300 movs r3, #0
8005908: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
800590a: 2300 movs r3, #0
800590c: 61fb str r3, [r7, #28]
800590e: e175 b.n 8005bfc <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8005910: 2201 movs r2, #1
8005912: 69fb ldr r3, [r7, #28]
8005914: fa02 f303 lsl.w r3, r2, r3
8005918: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
800591a: 683b ldr r3, [r7, #0]
800591c: 681b ldr r3, [r3, #0]
800591e: 697a ldr r2, [r7, #20]
8005920: 4013 ands r3, r2
8005922: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8005924: 693a ldr r2, [r7, #16]
8005926: 697b ldr r3, [r7, #20]
8005928: 429a cmp r2, r3
800592a: f040 8164 bne.w 8005bf6 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
800592e: 683b ldr r3, [r7, #0]
8005930: 685b ldr r3, [r3, #4]
8005932: 2b01 cmp r3, #1
8005934: d00b beq.n 800594e <HAL_GPIO_Init+0x5e>
8005936: 683b ldr r3, [r7, #0]
8005938: 685b ldr r3, [r3, #4]
800593a: 2b02 cmp r3, #2
800593c: d007 beq.n 800594e <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
800593e: 683b ldr r3, [r7, #0]
8005940: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8005942: 2b11 cmp r3, #17
8005944: d003 beq.n 800594e <HAL_GPIO_Init+0x5e>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8005946: 683b ldr r3, [r7, #0]
8005948: 685b ldr r3, [r3, #4]
800594a: 2b12 cmp r3, #18
800594c: d130 bne.n 80059b0 <HAL_GPIO_Init+0xc0>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
800594e: 687b ldr r3, [r7, #4]
8005950: 689b ldr r3, [r3, #8]
8005952: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8005954: 69fb ldr r3, [r7, #28]
8005956: 005b lsls r3, r3, #1
8005958: 2203 movs r2, #3
800595a: fa02 f303 lsl.w r3, r2, r3
800595e: 43db mvns r3, r3
8005960: 69ba ldr r2, [r7, #24]
8005962: 4013 ands r3, r2
8005964: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2));
8005966: 683b ldr r3, [r7, #0]
8005968: 68da ldr r2, [r3, #12]
800596a: 69fb ldr r3, [r7, #28]
800596c: 005b lsls r3, r3, #1
800596e: fa02 f303 lsl.w r3, r2, r3
8005972: 69ba ldr r2, [r7, #24]
8005974: 4313 orrs r3, r2
8005976: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8005978: 687b ldr r3, [r7, #4]
800597a: 69ba ldr r2, [r7, #24]
800597c: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800597e: 687b ldr r3, [r7, #4]
8005980: 685b ldr r3, [r3, #4]
8005982: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8005984: 2201 movs r2, #1
8005986: 69fb ldr r3, [r7, #28]
8005988: fa02 f303 lsl.w r3, r2, r3
800598c: 43db mvns r3, r3
800598e: 69ba ldr r2, [r7, #24]
8005990: 4013 ands r3, r2
8005992: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
8005994: 683b ldr r3, [r7, #0]
8005996: 685b ldr r3, [r3, #4]
8005998: 091b lsrs r3, r3, #4
800599a: f003 0201 and.w r2, r3, #1
800599e: 69fb ldr r3, [r7, #28]
80059a0: fa02 f303 lsl.w r3, r2, r3
80059a4: 69ba ldr r2, [r7, #24]
80059a6: 4313 orrs r3, r2
80059a8: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
80059aa: 687b ldr r3, [r7, #4]
80059ac: 69ba ldr r2, [r7, #24]
80059ae: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80059b0: 687b ldr r3, [r7, #4]
80059b2: 68db ldr r3, [r3, #12]
80059b4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
80059b6: 69fb ldr r3, [r7, #28]
80059b8: 005b lsls r3, r3, #1
80059ba: 2203 movs r2, #3
80059bc: fa02 f303 lsl.w r3, r2, r3
80059c0: 43db mvns r3, r3
80059c2: 69ba ldr r2, [r7, #24]
80059c4: 4013 ands r3, r2
80059c6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2));
80059c8: 683b ldr r3, [r7, #0]
80059ca: 689a ldr r2, [r3, #8]
80059cc: 69fb ldr r3, [r7, #28]
80059ce: 005b lsls r3, r3, #1
80059d0: fa02 f303 lsl.w r3, r2, r3
80059d4: 69ba ldr r2, [r7, #24]
80059d6: 4313 orrs r3, r2
80059d8: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
80059da: 687b ldr r3, [r7, #4]
80059dc: 69ba ldr r2, [r7, #24]
80059de: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
80059e0: 683b ldr r3, [r7, #0]
80059e2: 685b ldr r3, [r3, #4]
80059e4: 2b02 cmp r3, #2
80059e6: d003 beq.n 80059f0 <HAL_GPIO_Init+0x100>
80059e8: 683b ldr r3, [r7, #0]
80059ea: 685b ldr r3, [r3, #4]
80059ec: 2b12 cmp r3, #18
80059ee: d123 bne.n 8005a38 <HAL_GPIO_Init+0x148>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
80059f0: 69fb ldr r3, [r7, #28]
80059f2: 08da lsrs r2, r3, #3
80059f4: 687b ldr r3, [r7, #4]
80059f6: 3208 adds r2, #8
80059f8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80059fc: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
80059fe: 69fb ldr r3, [r7, #28]
8005a00: f003 0307 and.w r3, r3, #7
8005a04: 009b lsls r3, r3, #2
8005a06: 220f movs r2, #15
8005a08: fa02 f303 lsl.w r3, r2, r3
8005a0c: 43db mvns r3, r3
8005a0e: 69ba ldr r2, [r7, #24]
8005a10: 4013 ands r3, r2
8005a12: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
8005a14: 683b ldr r3, [r7, #0]
8005a16: 691a ldr r2, [r3, #16]
8005a18: 69fb ldr r3, [r7, #28]
8005a1a: f003 0307 and.w r3, r3, #7
8005a1e: 009b lsls r3, r3, #2
8005a20: fa02 f303 lsl.w r3, r2, r3
8005a24: 69ba ldr r2, [r7, #24]
8005a26: 4313 orrs r3, r2
8005a28: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3] = temp;
8005a2a: 69fb ldr r3, [r7, #28]
8005a2c: 08da lsrs r2, r3, #3
8005a2e: 687b ldr r3, [r7, #4]
8005a30: 3208 adds r2, #8
8005a32: 69b9 ldr r1, [r7, #24]
8005a34: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8005a38: 687b ldr r3, [r7, #4]
8005a3a: 681b ldr r3, [r3, #0]
8005a3c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
8005a3e: 69fb ldr r3, [r7, #28]
8005a40: 005b lsls r3, r3, #1
8005a42: 2203 movs r2, #3
8005a44: fa02 f303 lsl.w r3, r2, r3
8005a48: 43db mvns r3, r3
8005a4a: 69ba ldr r2, [r7, #24]
8005a4c: 4013 ands r3, r2
8005a4e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
8005a50: 683b ldr r3, [r7, #0]
8005a52: 685b ldr r3, [r3, #4]
8005a54: f003 0203 and.w r2, r3, #3
8005a58: 69fb ldr r3, [r7, #28]
8005a5a: 005b lsls r3, r3, #1
8005a5c: fa02 f303 lsl.w r3, r2, r3
8005a60: 69ba ldr r2, [r7, #24]
8005a62: 4313 orrs r3, r2
8005a64: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8005a66: 687b ldr r3, [r7, #4]
8005a68: 69ba ldr r2, [r7, #24]
8005a6a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8005a6c: 683b ldr r3, [r7, #0]
8005a6e: 685b ldr r3, [r3, #4]
8005a70: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8005a74: 2b00 cmp r3, #0
8005a76: f000 80be beq.w 8005bf6 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8005a7a: 4b65 ldr r3, [pc, #404] ; (8005c10 <HAL_GPIO_Init+0x320>)
8005a7c: 6c5b ldr r3, [r3, #68] ; 0x44
8005a7e: 4a64 ldr r2, [pc, #400] ; (8005c10 <HAL_GPIO_Init+0x320>)
8005a80: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8005a84: 6453 str r3, [r2, #68] ; 0x44
8005a86: 4b62 ldr r3, [pc, #392] ; (8005c10 <HAL_GPIO_Init+0x320>)
8005a88: 6c5b ldr r3, [r3, #68] ; 0x44
8005a8a: f403 4380 and.w r3, r3, #16384 ; 0x4000
8005a8e: 60fb str r3, [r7, #12]
8005a90: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2];
8005a92: 4a60 ldr r2, [pc, #384] ; (8005c14 <HAL_GPIO_Init+0x324>)
8005a94: 69fb ldr r3, [r7, #28]
8005a96: 089b lsrs r3, r3, #2
8005a98: 3302 adds r3, #2
8005a9a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8005a9e: 61bb str r3, [r7, #24]
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
8005aa0: 69fb ldr r3, [r7, #28]
8005aa2: f003 0303 and.w r3, r3, #3
8005aa6: 009b lsls r3, r3, #2
8005aa8: 220f movs r2, #15
8005aaa: fa02 f303 lsl.w r3, r2, r3
8005aae: 43db mvns r3, r3
8005ab0: 69ba ldr r2, [r7, #24]
8005ab2: 4013 ands r3, r2
8005ab4: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
8005ab6: 687b ldr r3, [r7, #4]
8005ab8: 4a57 ldr r2, [pc, #348] ; (8005c18 <HAL_GPIO_Init+0x328>)
8005aba: 4293 cmp r3, r2
8005abc: d037 beq.n 8005b2e <HAL_GPIO_Init+0x23e>
8005abe: 687b ldr r3, [r7, #4]
8005ac0: 4a56 ldr r2, [pc, #344] ; (8005c1c <HAL_GPIO_Init+0x32c>)
8005ac2: 4293 cmp r3, r2
8005ac4: d031 beq.n 8005b2a <HAL_GPIO_Init+0x23a>
8005ac6: 687b ldr r3, [r7, #4]
8005ac8: 4a55 ldr r2, [pc, #340] ; (8005c20 <HAL_GPIO_Init+0x330>)
8005aca: 4293 cmp r3, r2
8005acc: d02b beq.n 8005b26 <HAL_GPIO_Init+0x236>
8005ace: 687b ldr r3, [r7, #4]
8005ad0: 4a54 ldr r2, [pc, #336] ; (8005c24 <HAL_GPIO_Init+0x334>)
8005ad2: 4293 cmp r3, r2
8005ad4: d025 beq.n 8005b22 <HAL_GPIO_Init+0x232>
8005ad6: 687b ldr r3, [r7, #4]
8005ad8: 4a53 ldr r2, [pc, #332] ; (8005c28 <HAL_GPIO_Init+0x338>)
8005ada: 4293 cmp r3, r2
8005adc: d01f beq.n 8005b1e <HAL_GPIO_Init+0x22e>
8005ade: 687b ldr r3, [r7, #4]
8005ae0: 4a52 ldr r2, [pc, #328] ; (8005c2c <HAL_GPIO_Init+0x33c>)
8005ae2: 4293 cmp r3, r2
8005ae4: d019 beq.n 8005b1a <HAL_GPIO_Init+0x22a>
8005ae6: 687b ldr r3, [r7, #4]
8005ae8: 4a51 ldr r2, [pc, #324] ; (8005c30 <HAL_GPIO_Init+0x340>)
8005aea: 4293 cmp r3, r2
8005aec: d013 beq.n 8005b16 <HAL_GPIO_Init+0x226>
8005aee: 687b ldr r3, [r7, #4]
8005af0: 4a50 ldr r2, [pc, #320] ; (8005c34 <HAL_GPIO_Init+0x344>)
8005af2: 4293 cmp r3, r2
8005af4: d00d beq.n 8005b12 <HAL_GPIO_Init+0x222>
8005af6: 687b ldr r3, [r7, #4]
8005af8: 4a4f ldr r2, [pc, #316] ; (8005c38 <HAL_GPIO_Init+0x348>)
8005afa: 4293 cmp r3, r2
8005afc: d007 beq.n 8005b0e <HAL_GPIO_Init+0x21e>
8005afe: 687b ldr r3, [r7, #4]
8005b00: 4a4e ldr r2, [pc, #312] ; (8005c3c <HAL_GPIO_Init+0x34c>)
8005b02: 4293 cmp r3, r2
8005b04: d101 bne.n 8005b0a <HAL_GPIO_Init+0x21a>
8005b06: 2309 movs r3, #9
8005b08: e012 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b0a: 230a movs r3, #10
8005b0c: e010 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b0e: 2308 movs r3, #8
8005b10: e00e b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b12: 2307 movs r3, #7
8005b14: e00c b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b16: 2306 movs r3, #6
8005b18: e00a b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b1a: 2305 movs r3, #5
8005b1c: e008 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b1e: 2304 movs r3, #4
8005b20: e006 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b22: 2303 movs r3, #3
8005b24: e004 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b26: 2302 movs r3, #2
8005b28: e002 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b2a: 2301 movs r3, #1
8005b2c: e000 b.n 8005b30 <HAL_GPIO_Init+0x240>
8005b2e: 2300 movs r3, #0
8005b30: 69fa ldr r2, [r7, #28]
8005b32: f002 0203 and.w r2, r2, #3
8005b36: 0092 lsls r2, r2, #2
8005b38: 4093 lsls r3, r2
8005b3a: 69ba ldr r2, [r7, #24]
8005b3c: 4313 orrs r3, r2
8005b3e: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2] = temp;
8005b40: 4934 ldr r1, [pc, #208] ; (8005c14 <HAL_GPIO_Init+0x324>)
8005b42: 69fb ldr r3, [r7, #28]
8005b44: 089b lsrs r3, r3, #2
8005b46: 3302 adds r3, #2
8005b48: 69ba ldr r2, [r7, #24]
8005b4a: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8005b4e: 4b3c ldr r3, [pc, #240] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005b50: 681b ldr r3, [r3, #0]
8005b52: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8005b54: 693b ldr r3, [r7, #16]
8005b56: 43db mvns r3, r3
8005b58: 69ba ldr r2, [r7, #24]
8005b5a: 4013 ands r3, r2
8005b5c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8005b5e: 683b ldr r3, [r7, #0]
8005b60: 685b ldr r3, [r3, #4]
8005b62: f403 3380 and.w r3, r3, #65536 ; 0x10000
8005b66: 2b00 cmp r3, #0
8005b68: d003 beq.n 8005b72 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
8005b6a: 69ba ldr r2, [r7, #24]
8005b6c: 693b ldr r3, [r7, #16]
8005b6e: 4313 orrs r3, r2
8005b70: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8005b72: 4a33 ldr r2, [pc, #204] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005b74: 69bb ldr r3, [r7, #24]
8005b76: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8005b78: 4b31 ldr r3, [pc, #196] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005b7a: 685b ldr r3, [r3, #4]
8005b7c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8005b7e: 693b ldr r3, [r7, #16]
8005b80: 43db mvns r3, r3
8005b82: 69ba ldr r2, [r7, #24]
8005b84: 4013 ands r3, r2
8005b86: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8005b88: 683b ldr r3, [r7, #0]
8005b8a: 685b ldr r3, [r3, #4]
8005b8c: f403 3300 and.w r3, r3, #131072 ; 0x20000
8005b90: 2b00 cmp r3, #0
8005b92: d003 beq.n 8005b9c <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8005b94: 69ba ldr r2, [r7, #24]
8005b96: 693b ldr r3, [r7, #16]
8005b98: 4313 orrs r3, r2
8005b9a: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8005b9c: 4a28 ldr r2, [pc, #160] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005b9e: 69bb ldr r3, [r7, #24]
8005ba0: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8005ba2: 4b27 ldr r3, [pc, #156] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005ba4: 689b ldr r3, [r3, #8]
8005ba6: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8005ba8: 693b ldr r3, [r7, #16]
8005baa: 43db mvns r3, r3
8005bac: 69ba ldr r2, [r7, #24]
8005bae: 4013 ands r3, r2
8005bb0: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8005bb2: 683b ldr r3, [r7, #0]
8005bb4: 685b ldr r3, [r3, #4]
8005bb6: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8005bba: 2b00 cmp r3, #0
8005bbc: d003 beq.n 8005bc6 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8005bbe: 69ba ldr r2, [r7, #24]
8005bc0: 693b ldr r3, [r7, #16]
8005bc2: 4313 orrs r3, r2
8005bc4: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8005bc6: 4a1e ldr r2, [pc, #120] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005bc8: 69bb ldr r3, [r7, #24]
8005bca: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8005bcc: 4b1c ldr r3, [pc, #112] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005bce: 68db ldr r3, [r3, #12]
8005bd0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8005bd2: 693b ldr r3, [r7, #16]
8005bd4: 43db mvns r3, r3
8005bd6: 69ba ldr r2, [r7, #24]
8005bd8: 4013 ands r3, r2
8005bda: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8005bdc: 683b ldr r3, [r7, #0]
8005bde: 685b ldr r3, [r3, #4]
8005be0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8005be4: 2b00 cmp r3, #0
8005be6: d003 beq.n 8005bf0 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8005be8: 69ba ldr r2, [r7, #24]
8005bea: 693b ldr r3, [r7, #16]
8005bec: 4313 orrs r3, r2
8005bee: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8005bf0: 4a13 ldr r2, [pc, #76] ; (8005c40 <HAL_GPIO_Init+0x350>)
8005bf2: 69bb ldr r3, [r7, #24]
8005bf4: 60d3 str r3, [r2, #12]
for(position = 0; position < GPIO_NUMBER; position++)
8005bf6: 69fb ldr r3, [r7, #28]
8005bf8: 3301 adds r3, #1
8005bfa: 61fb str r3, [r7, #28]
8005bfc: 69fb ldr r3, [r7, #28]
8005bfe: 2b0f cmp r3, #15
8005c00: f67f ae86 bls.w 8005910 <HAL_GPIO_Init+0x20>
}
}
}
}
8005c04: bf00 nop
8005c06: 3724 adds r7, #36 ; 0x24
8005c08: 46bd mov sp, r7
8005c0a: f85d 7b04 ldr.w r7, [sp], #4
8005c0e: 4770 bx lr
8005c10: 40023800 .word 0x40023800
8005c14: 40013800 .word 0x40013800
8005c18: 40020000 .word 0x40020000
8005c1c: 40020400 .word 0x40020400
8005c20: 40020800 .word 0x40020800
8005c24: 40020c00 .word 0x40020c00
8005c28: 40021000 .word 0x40021000
8005c2c: 40021400 .word 0x40021400
8005c30: 40021800 .word 0x40021800
8005c34: 40021c00 .word 0x40021c00
8005c38: 40022000 .word 0x40022000
8005c3c: 40022400 .word 0x40022400
8005c40: 40013c00 .word 0x40013c00
08005c44 <HAL_GPIO_DeInit>:
* @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
8005c44: b480 push {r7}
8005c46: b087 sub sp, #28
8005c48: af00 add r7, sp, #0
8005c4a: 6078 str r0, [r7, #4]
8005c4c: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00;
8005c4e: 2300 movs r3, #0
8005c50: 613b str r3, [r7, #16]
uint32_t iocurrent = 0x00;
8005c52: 2300 movs r3, #0
8005c54: 60fb str r3, [r7, #12]
uint32_t tmp = 0x00;
8005c56: 2300 movs r3, #0
8005c58: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
8005c5a: 2300 movs r3, #0
8005c5c: 617b str r3, [r7, #20]
8005c5e: e0d9 b.n 8005e14 <HAL_GPIO_DeInit+0x1d0>
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
8005c60: 2201 movs r2, #1
8005c62: 697b ldr r3, [r7, #20]
8005c64: fa02 f303 lsl.w r3, r2, r3
8005c68: 613b str r3, [r7, #16]
/* Get the current IO position */
iocurrent = (GPIO_Pin) & ioposition;
8005c6a: 683a ldr r2, [r7, #0]
8005c6c: 693b ldr r3, [r7, #16]
8005c6e: 4013 ands r3, r2
8005c70: 60fb str r3, [r7, #12]
if(iocurrent == ioposition)
8005c72: 68fa ldr r2, [r7, #12]
8005c74: 693b ldr r3, [r7, #16]
8005c76: 429a cmp r2, r3
8005c78: f040 80c9 bne.w 8005e0e <HAL_GPIO_DeInit+0x1ca>
{
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2];
8005c7c: 4a6a ldr r2, [pc, #424] ; (8005e28 <HAL_GPIO_DeInit+0x1e4>)
8005c7e: 697b ldr r3, [r7, #20]
8005c80: 089b lsrs r3, r3, #2
8005c82: 3302 adds r3, #2
8005c84: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8005c88: 60bb str r3, [r7, #8]
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
8005c8a: 697b ldr r3, [r7, #20]
8005c8c: f003 0303 and.w r3, r3, #3
8005c90: 009b lsls r3, r3, #2
8005c92: 220f movs r2, #15
8005c94: fa02 f303 lsl.w r3, r2, r3
8005c98: 68ba ldr r2, [r7, #8]
8005c9a: 4013 ands r3, r2
8005c9c: 60bb str r3, [r7, #8]
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
8005c9e: 687b ldr r3, [r7, #4]
8005ca0: 4a62 ldr r2, [pc, #392] ; (8005e2c <HAL_GPIO_DeInit+0x1e8>)
8005ca2: 4293 cmp r3, r2
8005ca4: d037 beq.n 8005d16 <HAL_GPIO_DeInit+0xd2>
8005ca6: 687b ldr r3, [r7, #4]
8005ca8: 4a61 ldr r2, [pc, #388] ; (8005e30 <HAL_GPIO_DeInit+0x1ec>)
8005caa: 4293 cmp r3, r2
8005cac: d031 beq.n 8005d12 <HAL_GPIO_DeInit+0xce>
8005cae: 687b ldr r3, [r7, #4]
8005cb0: 4a60 ldr r2, [pc, #384] ; (8005e34 <HAL_GPIO_DeInit+0x1f0>)
8005cb2: 4293 cmp r3, r2
8005cb4: d02b beq.n 8005d0e <HAL_GPIO_DeInit+0xca>
8005cb6: 687b ldr r3, [r7, #4]
8005cb8: 4a5f ldr r2, [pc, #380] ; (8005e38 <HAL_GPIO_DeInit+0x1f4>)
8005cba: 4293 cmp r3, r2
8005cbc: d025 beq.n 8005d0a <HAL_GPIO_DeInit+0xc6>
8005cbe: 687b ldr r3, [r7, #4]
8005cc0: 4a5e ldr r2, [pc, #376] ; (8005e3c <HAL_GPIO_DeInit+0x1f8>)
8005cc2: 4293 cmp r3, r2
8005cc4: d01f beq.n 8005d06 <HAL_GPIO_DeInit+0xc2>
8005cc6: 687b ldr r3, [r7, #4]
8005cc8: 4a5d ldr r2, [pc, #372] ; (8005e40 <HAL_GPIO_DeInit+0x1fc>)
8005cca: 4293 cmp r3, r2
8005ccc: d019 beq.n 8005d02 <HAL_GPIO_DeInit+0xbe>
8005cce: 687b ldr r3, [r7, #4]
8005cd0: 4a5c ldr r2, [pc, #368] ; (8005e44 <HAL_GPIO_DeInit+0x200>)
8005cd2: 4293 cmp r3, r2
8005cd4: d013 beq.n 8005cfe <HAL_GPIO_DeInit+0xba>
8005cd6: 687b ldr r3, [r7, #4]
8005cd8: 4a5b ldr r2, [pc, #364] ; (8005e48 <HAL_GPIO_DeInit+0x204>)
8005cda: 4293 cmp r3, r2
8005cdc: d00d beq.n 8005cfa <HAL_GPIO_DeInit+0xb6>
8005cde: 687b ldr r3, [r7, #4]
8005ce0: 4a5a ldr r2, [pc, #360] ; (8005e4c <HAL_GPIO_DeInit+0x208>)
8005ce2: 4293 cmp r3, r2
8005ce4: d007 beq.n 8005cf6 <HAL_GPIO_DeInit+0xb2>
8005ce6: 687b ldr r3, [r7, #4]
8005ce8: 4a59 ldr r2, [pc, #356] ; (8005e50 <HAL_GPIO_DeInit+0x20c>)
8005cea: 4293 cmp r3, r2
8005cec: d101 bne.n 8005cf2 <HAL_GPIO_DeInit+0xae>
8005cee: 2309 movs r3, #9
8005cf0: e012 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005cf2: 230a movs r3, #10
8005cf4: e010 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005cf6: 2308 movs r3, #8
8005cf8: e00e b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005cfa: 2307 movs r3, #7
8005cfc: e00c b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005cfe: 2306 movs r3, #6
8005d00: e00a b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d02: 2305 movs r3, #5
8005d04: e008 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d06: 2304 movs r3, #4
8005d08: e006 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d0a: 2303 movs r3, #3
8005d0c: e004 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d0e: 2302 movs r3, #2
8005d10: e002 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d12: 2301 movs r3, #1
8005d14: e000 b.n 8005d18 <HAL_GPIO_DeInit+0xd4>
8005d16: 2300 movs r3, #0
8005d18: 697a ldr r2, [r7, #20]
8005d1a: f002 0203 and.w r2, r2, #3
8005d1e: 0092 lsls r2, r2, #2
8005d20: 4093 lsls r3, r2
8005d22: 68ba ldr r2, [r7, #8]
8005d24: 429a cmp r2, r3
8005d26: d132 bne.n 8005d8e <HAL_GPIO_DeInit+0x14a>
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
8005d28: 4b4a ldr r3, [pc, #296] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d2a: 681a ldr r2, [r3, #0]
8005d2c: 68fb ldr r3, [r7, #12]
8005d2e: 43db mvns r3, r3
8005d30: 4948 ldr r1, [pc, #288] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d32: 4013 ands r3, r2
8005d34: 600b str r3, [r1, #0]
EXTI->EMR &= ~((uint32_t)iocurrent);
8005d36: 4b47 ldr r3, [pc, #284] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d38: 685a ldr r2, [r3, #4]
8005d3a: 68fb ldr r3, [r7, #12]
8005d3c: 43db mvns r3, r3
8005d3e: 4945 ldr r1, [pc, #276] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d40: 4013 ands r3, r2
8005d42: 604b str r3, [r1, #4]
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
8005d44: 4b43 ldr r3, [pc, #268] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d46: 689a ldr r2, [r3, #8]
8005d48: 68fb ldr r3, [r7, #12]
8005d4a: 43db mvns r3, r3
8005d4c: 4941 ldr r1, [pc, #260] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d4e: 4013 ands r3, r2
8005d50: 608b str r3, [r1, #8]
EXTI->FTSR &= ~((uint32_t)iocurrent);
8005d52: 4b40 ldr r3, [pc, #256] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d54: 68da ldr r2, [r3, #12]
8005d56: 68fb ldr r3, [r7, #12]
8005d58: 43db mvns r3, r3
8005d5a: 493e ldr r1, [pc, #248] ; (8005e54 <HAL_GPIO_DeInit+0x210>)
8005d5c: 4013 ands r3, r2
8005d5e: 60cb str r3, [r1, #12]
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
8005d60: 697b ldr r3, [r7, #20]
8005d62: f003 0303 and.w r3, r3, #3
8005d66: 009b lsls r3, r3, #2
8005d68: 220f movs r2, #15
8005d6a: fa02 f303 lsl.w r3, r2, r3
8005d6e: 60bb str r3, [r7, #8]
SYSCFG->EXTICR[position >> 2] &= ~tmp;
8005d70: 4a2d ldr r2, [pc, #180] ; (8005e28 <HAL_GPIO_DeInit+0x1e4>)
8005d72: 697b ldr r3, [r7, #20]
8005d74: 089b lsrs r3, r3, #2
8005d76: 3302 adds r3, #2
8005d78: f852 1023 ldr.w r1, [r2, r3, lsl #2]
8005d7c: 68bb ldr r3, [r7, #8]
8005d7e: 43da mvns r2, r3
8005d80: 4829 ldr r0, [pc, #164] ; (8005e28 <HAL_GPIO_DeInit+0x1e4>)
8005d82: 697b ldr r3, [r7, #20]
8005d84: 089b lsrs r3, r3, #2
8005d86: 400a ands r2, r1
8005d88: 3302 adds r3, #2
8005d8a: f840 2023 str.w r2, [r0, r3, lsl #2]
}
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floating Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
8005d8e: 687b ldr r3, [r7, #4]
8005d90: 681a ldr r2, [r3, #0]
8005d92: 697b ldr r3, [r7, #20]
8005d94: 005b lsls r3, r3, #1
8005d96: 2103 movs r1, #3
8005d98: fa01 f303 lsl.w r3, r1, r3
8005d9c: 43db mvns r3, r3
8005d9e: 401a ands r2, r3
8005da0: 687b ldr r3, [r7, #4]
8005da2: 601a str r2, [r3, #0]
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
8005da4: 697b ldr r3, [r7, #20]
8005da6: 08da lsrs r2, r3, #3
8005da8: 687b ldr r3, [r7, #4]
8005daa: 3208 adds r2, #8
8005dac: f853 1022 ldr.w r1, [r3, r2, lsl #2]
8005db0: 697b ldr r3, [r7, #20]
8005db2: f003 0307 and.w r3, r3, #7
8005db6: 009b lsls r3, r3, #2
8005db8: 220f movs r2, #15
8005dba: fa02 f303 lsl.w r3, r2, r3
8005dbe: 43db mvns r3, r3
8005dc0: 697a ldr r2, [r7, #20]
8005dc2: 08d2 lsrs r2, r2, #3
8005dc4: 4019 ands r1, r3
8005dc6: 687b ldr r3, [r7, #4]
8005dc8: 3208 adds r2, #8
8005dca: f843 1022 str.w r1, [r3, r2, lsl #2]
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
8005dce: 687b ldr r3, [r7, #4]
8005dd0: 68da ldr r2, [r3, #12]
8005dd2: 697b ldr r3, [r7, #20]
8005dd4: 005b lsls r3, r3, #1
8005dd6: 2103 movs r1, #3
8005dd8: fa01 f303 lsl.w r3, r1, r3
8005ddc: 43db mvns r3, r3
8005dde: 401a ands r2, r3
8005de0: 687b ldr r3, [r7, #4]
8005de2: 60da str r2, [r3, #12]
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
8005de4: 687b ldr r3, [r7, #4]
8005de6: 685a ldr r2, [r3, #4]
8005de8: 2101 movs r1, #1
8005dea: 697b ldr r3, [r7, #20]
8005dec: fa01 f303 lsl.w r3, r1, r3
8005df0: 43db mvns r3, r3
8005df2: 401a ands r2, r3
8005df4: 687b ldr r3, [r7, #4]
8005df6: 605a str r2, [r3, #4]
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
8005df8: 687b ldr r3, [r7, #4]
8005dfa: 689a ldr r2, [r3, #8]
8005dfc: 697b ldr r3, [r7, #20]
8005dfe: 005b lsls r3, r3, #1
8005e00: 2103 movs r1, #3
8005e02: fa01 f303 lsl.w r3, r1, r3
8005e06: 43db mvns r3, r3
8005e08: 401a ands r2, r3
8005e0a: 687b ldr r3, [r7, #4]
8005e0c: 609a str r2, [r3, #8]
for(position = 0; position < GPIO_NUMBER; position++)
8005e0e: 697b ldr r3, [r7, #20]
8005e10: 3301 adds r3, #1
8005e12: 617b str r3, [r7, #20]
8005e14: 697b ldr r3, [r7, #20]
8005e16: 2b0f cmp r3, #15
8005e18: f67f af22 bls.w 8005c60 <HAL_GPIO_DeInit+0x1c>
}
}
}
8005e1c: bf00 nop
8005e1e: 371c adds r7, #28
8005e20: 46bd mov sp, r7
8005e22: f85d 7b04 ldr.w r7, [sp], #4
8005e26: 4770 bx lr
8005e28: 40013800 .word 0x40013800
8005e2c: 40020000 .word 0x40020000
8005e30: 40020400 .word 0x40020400
8005e34: 40020800 .word 0x40020800
8005e38: 40020c00 .word 0x40020c00
8005e3c: 40021000 .word 0x40021000
8005e40: 40021400 .word 0x40021400
8005e44: 40021800 .word 0x40021800
8005e48: 40021c00 .word 0x40021c00
8005e4c: 40022000 .word 0x40022000
8005e50: 40022400 .word 0x40022400
8005e54: 40013c00 .word 0x40013c00
08005e58 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8005e58: b480 push {r7}
8005e5a: b085 sub sp, #20
8005e5c: af00 add r7, sp, #0
8005e5e: 6078 str r0, [r7, #4]
8005e60: 460b mov r3, r1
8005e62: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8005e64: 687b ldr r3, [r7, #4]
8005e66: 691a ldr r2, [r3, #16]
8005e68: 887b ldrh r3, [r7, #2]
8005e6a: 4013 ands r3, r2
8005e6c: 2b00 cmp r3, #0
8005e6e: d002 beq.n 8005e76 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8005e70: 2301 movs r3, #1
8005e72: 73fb strb r3, [r7, #15]
8005e74: e001 b.n 8005e7a <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8005e76: 2300 movs r3, #0
8005e78: 73fb strb r3, [r7, #15]
}
return bitstatus;
8005e7a: 7bfb ldrb r3, [r7, #15]
}
8005e7c: 4618 mov r0, r3
8005e7e: 3714 adds r7, #20
8005e80: 46bd mov sp, r7
8005e82: f85d 7b04 ldr.w r7, [sp], #4
8005e86: 4770 bx lr
08005e88 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8005e88: b480 push {r7}
8005e8a: b083 sub sp, #12
8005e8c: af00 add r7, sp, #0
8005e8e: 6078 str r0, [r7, #4]
8005e90: 460b mov r3, r1
8005e92: 807b strh r3, [r7, #2]
8005e94: 4613 mov r3, r2
8005e96: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8005e98: 787b ldrb r3, [r7, #1]
8005e9a: 2b00 cmp r3, #0
8005e9c: d003 beq.n 8005ea6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8005e9e: 887a ldrh r2, [r7, #2]
8005ea0: 687b ldr r3, [r7, #4]
8005ea2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
8005ea4: e003 b.n 8005eae <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
8005ea6: 887b ldrh r3, [r7, #2]
8005ea8: 041a lsls r2, r3, #16
8005eaa: 687b ldr r3, [r7, #4]
8005eac: 619a str r2, [r3, #24]
}
8005eae: bf00 nop
8005eb0: 370c adds r7, #12
8005eb2: 46bd mov sp, r7
8005eb4: f85d 7b04 ldr.w r7, [sp], #4
8005eb8: 4770 bx lr
...
08005ebc <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8005ebc: b580 push {r7, lr}
8005ebe: b082 sub sp, #8
8005ec0: af00 add r7, sp, #0
8005ec2: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8005ec4: 687b ldr r3, [r7, #4]
8005ec6: 2b00 cmp r3, #0
8005ec8: d101 bne.n 8005ece <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8005eca: 2301 movs r3, #1
8005ecc: e07f b.n 8005fce <HAL_I2C_Init+0x112>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8005ece: 687b ldr r3, [r7, #4]
8005ed0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8005ed4: b2db uxtb r3, r3
8005ed6: 2b00 cmp r3, #0
8005ed8: d106 bne.n 8005ee8 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8005eda: 687b ldr r3, [r7, #4]
8005edc: 2200 movs r2, #0
8005ede: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8005ee2: 6878 ldr r0, [r7, #4]
8005ee4: f7fd fdb4 bl 8003a50 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8005ee8: 687b ldr r3, [r7, #4]
8005eea: 2224 movs r2, #36 ; 0x24
8005eec: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8005ef0: 687b ldr r3, [r7, #4]
8005ef2: 681b ldr r3, [r3, #0]
8005ef4: 681a ldr r2, [r3, #0]
8005ef6: 687b ldr r3, [r7, #4]
8005ef8: 681b ldr r3, [r3, #0]
8005efa: f022 0201 bic.w r2, r2, #1
8005efe: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8005f00: 687b ldr r3, [r7, #4]
8005f02: 685a ldr r2, [r3, #4]
8005f04: 687b ldr r3, [r7, #4]
8005f06: 681b ldr r3, [r3, #0]
8005f08: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8005f0c: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8005f0e: 687b ldr r3, [r7, #4]
8005f10: 681b ldr r3, [r3, #0]
8005f12: 689a ldr r2, [r3, #8]
8005f14: 687b ldr r3, [r7, #4]
8005f16: 681b ldr r3, [r3, #0]
8005f18: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8005f1c: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
8005f1e: 687b ldr r3, [r7, #4]
8005f20: 68db ldr r3, [r3, #12]
8005f22: 2b01 cmp r3, #1
8005f24: d107 bne.n 8005f36 <HAL_I2C_Init+0x7a>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
8005f26: 687b ldr r3, [r7, #4]
8005f28: 689a ldr r2, [r3, #8]
8005f2a: 687b ldr r3, [r7, #4]
8005f2c: 681b ldr r3, [r3, #0]
8005f2e: f442 4200 orr.w r2, r2, #32768 ; 0x8000
8005f32: 609a str r2, [r3, #8]
8005f34: e006 b.n 8005f44 <HAL_I2C_Init+0x88>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
8005f36: 687b ldr r3, [r7, #4]
8005f38: 689a ldr r2, [r3, #8]
8005f3a: 687b ldr r3, [r7, #4]
8005f3c: 681b ldr r3, [r3, #0]
8005f3e: f442 4204 orr.w r2, r2, #33792 ; 0x8400
8005f42: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
8005f44: 687b ldr r3, [r7, #4]
8005f46: 68db ldr r3, [r3, #12]
8005f48: 2b02 cmp r3, #2
8005f4a: d104 bne.n 8005f56 <HAL_I2C_Init+0x9a>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
8005f4c: 687b ldr r3, [r7, #4]
8005f4e: 681b ldr r3, [r3, #0]
8005f50: f44f 6200 mov.w r2, #2048 ; 0x800
8005f54: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
8005f56: 687b ldr r3, [r7, #4]
8005f58: 681b ldr r3, [r3, #0]
8005f5a: 6859 ldr r1, [r3, #4]
8005f5c: 687b ldr r3, [r7, #4]
8005f5e: 681a ldr r2, [r3, #0]
8005f60: 4b1d ldr r3, [pc, #116] ; (8005fd8 <HAL_I2C_Init+0x11c>)
8005f62: 430b orrs r3, r1
8005f64: 6053 str r3, [r2, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
8005f66: 687b ldr r3, [r7, #4]
8005f68: 681b ldr r3, [r3, #0]
8005f6a: 68da ldr r2, [r3, #12]
8005f6c: 687b ldr r3, [r7, #4]
8005f6e: 681b ldr r3, [r3, #0]
8005f70: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8005f74: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
8005f76: 687b ldr r3, [r7, #4]
8005f78: 691a ldr r2, [r3, #16]
8005f7a: 687b ldr r3, [r7, #4]
8005f7c: 695b ldr r3, [r3, #20]
8005f7e: ea42 0103 orr.w r1, r2, r3
8005f82: 687b ldr r3, [r7, #4]
8005f84: 699b ldr r3, [r3, #24]
8005f86: 021a lsls r2, r3, #8
8005f88: 687b ldr r3, [r7, #4]
8005f8a: 681b ldr r3, [r3, #0]
8005f8c: 430a orrs r2, r1
8005f8e: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8005f90: 687b ldr r3, [r7, #4]
8005f92: 69d9 ldr r1, [r3, #28]
8005f94: 687b ldr r3, [r7, #4]
8005f96: 6a1a ldr r2, [r3, #32]
8005f98: 687b ldr r3, [r7, #4]
8005f9a: 681b ldr r3, [r3, #0]
8005f9c: 430a orrs r2, r1
8005f9e: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8005fa0: 687b ldr r3, [r7, #4]
8005fa2: 681b ldr r3, [r3, #0]
8005fa4: 681a ldr r2, [r3, #0]
8005fa6: 687b ldr r3, [r7, #4]
8005fa8: 681b ldr r3, [r3, #0]
8005faa: f042 0201 orr.w r2, r2, #1
8005fae: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8005fb0: 687b ldr r3, [r7, #4]
8005fb2: 2200 movs r2, #0
8005fb4: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8005fb6: 687b ldr r3, [r7, #4]
8005fb8: 2220 movs r2, #32
8005fba: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
8005fbe: 687b ldr r3, [r7, #4]
8005fc0: 2200 movs r2, #0
8005fc2: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8005fc4: 687b ldr r3, [r7, #4]
8005fc6: 2200 movs r2, #0
8005fc8: f883 2042 strb.w r2, [r3, #66] ; 0x42
return HAL_OK;
8005fcc: 2300 movs r3, #0
}
8005fce: 4618 mov r0, r3
8005fd0: 3708 adds r7, #8
8005fd2: 46bd mov sp, r7
8005fd4: bd80 pop {r7, pc}
8005fd6: bf00 nop
8005fd8: 02008000 .word 0x02008000
08005fdc <HAL_I2C_DeInit>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
8005fdc: b580 push {r7, lr}
8005fde: b082 sub sp, #8
8005fe0: af00 add r7, sp, #0
8005fe2: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8005fe4: 687b ldr r3, [r7, #4]
8005fe6: 2b00 cmp r3, #0
8005fe8: d101 bne.n 8005fee <HAL_I2C_DeInit+0x12>
{
return HAL_ERROR;
8005fea: 2301 movs r3, #1
8005fec: e021 b.n 8006032 <HAL_I2C_DeInit+0x56>
}
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
hi2c->State = HAL_I2C_STATE_BUSY;
8005fee: 687b ldr r3, [r7, #4]
8005ff0: 2224 movs r2, #36 ; 0x24
8005ff2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
8005ff6: 687b ldr r3, [r7, #4]
8005ff8: 681b ldr r3, [r3, #0]
8005ffa: 681a ldr r2, [r3, #0]
8005ffc: 687b ldr r3, [r7, #4]
8005ffe: 681b ldr r3, [r3, #0]
8006000: f022 0201 bic.w r2, r2, #1
8006004: 601a str r2, [r3, #0]
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hi2c->MspDeInitCallback(hi2c);
#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
8006006: 6878 ldr r0, [r7, #4]
8006008: f7fd fd9a bl 8003b40 <HAL_I2C_MspDeInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800600c: 687b ldr r3, [r7, #4]
800600e: 2200 movs r2, #0
8006010: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_RESET;
8006012: 687b ldr r3, [r7, #4]
8006014: 2200 movs r2, #0
8006016: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->PreviousState = I2C_STATE_NONE;
800601a: 687b ldr r3, [r7, #4]
800601c: 2200 movs r2, #0
800601e: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8006020: 687b ldr r3, [r7, #4]
8006022: 2200 movs r2, #0
8006024: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Release Lock */
__HAL_UNLOCK(hi2c);
8006028: 687b ldr r3, [r7, #4]
800602a: 2200 movs r2, #0
800602c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8006030: 2300 movs r3, #0
}
8006032: 4618 mov r0, r3
8006034: 3708 adds r7, #8
8006036: 46bd mov sp, r7
8006038: bd80 pop {r7, pc}
...
0800603c <HAL_I2C_Mem_Write>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800603c: b580 push {r7, lr}
800603e: b088 sub sp, #32
8006040: af02 add r7, sp, #8
8006042: 60f8 str r0, [r7, #12]
8006044: 4608 mov r0, r1
8006046: 4611 mov r1, r2
8006048: 461a mov r2, r3
800604a: 4603 mov r3, r0
800604c: 817b strh r3, [r7, #10]
800604e: 460b mov r3, r1
8006050: 813b strh r3, [r7, #8]
8006052: 4613 mov r3, r2
8006054: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
8006056: 68fb ldr r3, [r7, #12]
8006058: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
800605c: b2db uxtb r3, r3
800605e: 2b20 cmp r3, #32
8006060: f040 80f9 bne.w 8006256 <HAL_I2C_Mem_Write+0x21a>
{
if ((pData == NULL) || (Size == 0U))
8006064: 6a3b ldr r3, [r7, #32]
8006066: 2b00 cmp r3, #0
8006068: d002 beq.n 8006070 <HAL_I2C_Mem_Write+0x34>
800606a: 8cbb ldrh r3, [r7, #36] ; 0x24
800606c: 2b00 cmp r3, #0
800606e: d105 bne.n 800607c <HAL_I2C_Mem_Write+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8006070: 68fb ldr r3, [r7, #12]
8006072: f44f 7200 mov.w r2, #512 ; 0x200
8006076: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8006078: 2301 movs r3, #1
800607a: e0ed b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
/* Process Locked */
__HAL_LOCK(hi2c);
800607c: 68fb ldr r3, [r7, #12]
800607e: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8006082: 2b01 cmp r3, #1
8006084: d101 bne.n 800608a <HAL_I2C_Mem_Write+0x4e>
8006086: 2302 movs r3, #2
8006088: e0e6 b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
800608a: 68fb ldr r3, [r7, #12]
800608c: 2201 movs r2, #1
800608e: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8006092: f7fe fa2d bl 80044f0 <HAL_GetTick>
8006096: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
8006098: 697b ldr r3, [r7, #20]
800609a: 9300 str r3, [sp, #0]
800609c: 2319 movs r3, #25
800609e: 2201 movs r2, #1
80060a0: f44f 4100 mov.w r1, #32768 ; 0x8000
80060a4: 68f8 ldr r0, [r7, #12]
80060a6: f000 fad1 bl 800664c <I2C_WaitOnFlagUntilTimeout>
80060aa: 4603 mov r3, r0
80060ac: 2b00 cmp r3, #0
80060ae: d001 beq.n 80060b4 <HAL_I2C_Mem_Write+0x78>
{
return HAL_ERROR;
80060b0: 2301 movs r3, #1
80060b2: e0d1 b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
80060b4: 68fb ldr r3, [r7, #12]
80060b6: 2221 movs r2, #33 ; 0x21
80060b8: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80060bc: 68fb ldr r3, [r7, #12]
80060be: 2240 movs r2, #64 ; 0x40
80060c0: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80060c4: 68fb ldr r3, [r7, #12]
80060c6: 2200 movs r2, #0
80060c8: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80060ca: 68fb ldr r3, [r7, #12]
80060cc: 6a3a ldr r2, [r7, #32]
80060ce: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80060d0: 68fb ldr r3, [r7, #12]
80060d2: 8cba ldrh r2, [r7, #36] ; 0x24
80060d4: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80060d6: 68fb ldr r3, [r7, #12]
80060d8: 2200 movs r2, #0
80060da: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
80060dc: 88f8 ldrh r0, [r7, #6]
80060de: 893a ldrh r2, [r7, #8]
80060e0: 8979 ldrh r1, [r7, #10]
80060e2: 697b ldr r3, [r7, #20]
80060e4: 9301 str r3, [sp, #4]
80060e6: 6abb ldr r3, [r7, #40] ; 0x28
80060e8: 9300 str r3, [sp, #0]
80060ea: 4603 mov r3, r0
80060ec: 68f8 ldr r0, [r7, #12]
80060ee: f000 f9e1 bl 80064b4 <I2C_RequestMemoryWrite>
80060f2: 4603 mov r3, r0
80060f4: 2b00 cmp r3, #0
80060f6: d005 beq.n 8006104 <HAL_I2C_Mem_Write+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80060f8: 68fb ldr r3, [r7, #12]
80060fa: 2200 movs r2, #0
80060fc: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8006100: 2301 movs r3, #1
8006102: e0a9 b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8006104: 68fb ldr r3, [r7, #12]
8006106: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006108: b29b uxth r3, r3
800610a: 2bff cmp r3, #255 ; 0xff
800610c: d90e bls.n 800612c <HAL_I2C_Mem_Write+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
800610e: 68fb ldr r3, [r7, #12]
8006110: 22ff movs r2, #255 ; 0xff
8006112: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
8006114: 68fb ldr r3, [r7, #12]
8006116: 8d1b ldrh r3, [r3, #40] ; 0x28
8006118: b2da uxtb r2, r3
800611a: 8979 ldrh r1, [r7, #10]
800611c: 2300 movs r3, #0
800611e: 9300 str r3, [sp, #0]
8006120: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8006124: 68f8 ldr r0, [r7, #12]
8006126: f000 fbb3 bl 8006890 <I2C_TransferConfig>
800612a: e00f b.n 800614c <HAL_I2C_Mem_Write+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
800612c: 68fb ldr r3, [r7, #12]
800612e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006130: b29a uxth r2, r3
8006132: 68fb ldr r3, [r7, #12]
8006134: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
8006136: 68fb ldr r3, [r7, #12]
8006138: 8d1b ldrh r3, [r3, #40] ; 0x28
800613a: b2da uxtb r2, r3
800613c: 8979 ldrh r1, [r7, #10]
800613e: 2300 movs r3, #0
8006140: 9300 str r3, [sp, #0]
8006142: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8006146: 68f8 ldr r0, [r7, #12]
8006148: f000 fba2 bl 8006890 <I2C_TransferConfig>
}
do
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800614c: 697a ldr r2, [r7, #20]
800614e: 6ab9 ldr r1, [r7, #40] ; 0x28
8006150: 68f8 ldr r0, [r7, #12]
8006152: f000 fabb bl 80066cc <I2C_WaitOnTXISFlagUntilTimeout>
8006156: 4603 mov r3, r0
8006158: 2b00 cmp r3, #0
800615a: d001 beq.n 8006160 <HAL_I2C_Mem_Write+0x124>
{
return HAL_ERROR;
800615c: 2301 movs r3, #1
800615e: e07b b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8006160: 68fb ldr r3, [r7, #12]
8006162: 6a5b ldr r3, [r3, #36] ; 0x24
8006164: 781a ldrb r2, [r3, #0]
8006166: 68fb ldr r3, [r7, #12]
8006168: 681b ldr r3, [r3, #0]
800616a: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800616c: 68fb ldr r3, [r7, #12]
800616e: 6a5b ldr r3, [r3, #36] ; 0x24
8006170: 1c5a adds r2, r3, #1
8006172: 68fb ldr r3, [r7, #12]
8006174: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
8006176: 68fb ldr r3, [r7, #12]
8006178: 8d5b ldrh r3, [r3, #42] ; 0x2a
800617a: b29b uxth r3, r3
800617c: 3b01 subs r3, #1
800617e: b29a uxth r2, r3
8006180: 68fb ldr r3, [r7, #12]
8006182: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
8006184: 68fb ldr r3, [r7, #12]
8006186: 8d1b ldrh r3, [r3, #40] ; 0x28
8006188: 3b01 subs r3, #1
800618a: b29a uxth r2, r3
800618c: 68fb ldr r3, [r7, #12]
800618e: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
8006190: 68fb ldr r3, [r7, #12]
8006192: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006194: b29b uxth r3, r3
8006196: 2b00 cmp r3, #0
8006198: d034 beq.n 8006204 <HAL_I2C_Mem_Write+0x1c8>
800619a: 68fb ldr r3, [r7, #12]
800619c: 8d1b ldrh r3, [r3, #40] ; 0x28
800619e: 2b00 cmp r3, #0
80061a0: d130 bne.n 8006204 <HAL_I2C_Mem_Write+0x1c8>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80061a2: 697b ldr r3, [r7, #20]
80061a4: 9300 str r3, [sp, #0]
80061a6: 6abb ldr r3, [r7, #40] ; 0x28
80061a8: 2200 movs r2, #0
80061aa: 2180 movs r1, #128 ; 0x80
80061ac: 68f8 ldr r0, [r7, #12]
80061ae: f000 fa4d bl 800664c <I2C_WaitOnFlagUntilTimeout>
80061b2: 4603 mov r3, r0
80061b4: 2b00 cmp r3, #0
80061b6: d001 beq.n 80061bc <HAL_I2C_Mem_Write+0x180>
{
return HAL_ERROR;
80061b8: 2301 movs r3, #1
80061ba: e04d b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80061bc: 68fb ldr r3, [r7, #12]
80061be: 8d5b ldrh r3, [r3, #42] ; 0x2a
80061c0: b29b uxth r3, r3
80061c2: 2bff cmp r3, #255 ; 0xff
80061c4: d90e bls.n 80061e4 <HAL_I2C_Mem_Write+0x1a8>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80061c6: 68fb ldr r3, [r7, #12]
80061c8: 22ff movs r2, #255 ; 0xff
80061ca: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80061cc: 68fb ldr r3, [r7, #12]
80061ce: 8d1b ldrh r3, [r3, #40] ; 0x28
80061d0: b2da uxtb r2, r3
80061d2: 8979 ldrh r1, [r7, #10]
80061d4: 2300 movs r3, #0
80061d6: 9300 str r3, [sp, #0]
80061d8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80061dc: 68f8 ldr r0, [r7, #12]
80061de: f000 fb57 bl 8006890 <I2C_TransferConfig>
80061e2: e00f b.n 8006204 <HAL_I2C_Mem_Write+0x1c8>
}
else
{
hi2c->XferSize = hi2c->XferCount;
80061e4: 68fb ldr r3, [r7, #12]
80061e6: 8d5b ldrh r3, [r3, #42] ; 0x2a
80061e8: b29a uxth r2, r3
80061ea: 68fb ldr r3, [r7, #12]
80061ec: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
80061ee: 68fb ldr r3, [r7, #12]
80061f0: 8d1b ldrh r3, [r3, #40] ; 0x28
80061f2: b2da uxtb r2, r3
80061f4: 8979 ldrh r1, [r7, #10]
80061f6: 2300 movs r3, #0
80061f8: 9300 str r3, [sp, #0]
80061fa: f04f 7300 mov.w r3, #33554432 ; 0x2000000
80061fe: 68f8 ldr r0, [r7, #12]
8006200: f000 fb46 bl 8006890 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
8006204: 68fb ldr r3, [r7, #12]
8006206: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006208: b29b uxth r3, r3
800620a: 2b00 cmp r3, #0
800620c: d19e bne.n 800614c <HAL_I2C_Mem_Write+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800620e: 697a ldr r2, [r7, #20]
8006210: 6ab9 ldr r1, [r7, #40] ; 0x28
8006212: 68f8 ldr r0, [r7, #12]
8006214: f000 fa9a bl 800674c <I2C_WaitOnSTOPFlagUntilTimeout>
8006218: 4603 mov r3, r0
800621a: 2b00 cmp r3, #0
800621c: d001 beq.n 8006222 <HAL_I2C_Mem_Write+0x1e6>
{
return HAL_ERROR;
800621e: 2301 movs r3, #1
8006220: e01a b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8006222: 68fb ldr r3, [r7, #12]
8006224: 681b ldr r3, [r3, #0]
8006226: 2220 movs r2, #32
8006228: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800622a: 68fb ldr r3, [r7, #12]
800622c: 681b ldr r3, [r3, #0]
800622e: 6859 ldr r1, [r3, #4]
8006230: 68fb ldr r3, [r7, #12]
8006232: 681a ldr r2, [r3, #0]
8006234: 4b0a ldr r3, [pc, #40] ; (8006260 <HAL_I2C_Mem_Write+0x224>)
8006236: 400b ands r3, r1
8006238: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800623a: 68fb ldr r3, [r7, #12]
800623c: 2220 movs r2, #32
800623e: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006242: 68fb ldr r3, [r7, #12]
8006244: 2200 movs r2, #0
8006246: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800624a: 68fb ldr r3, [r7, #12]
800624c: 2200 movs r2, #0
800624e: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8006252: 2300 movs r3, #0
8006254: e000 b.n 8006258 <HAL_I2C_Mem_Write+0x21c>
}
else
{
return HAL_BUSY;
8006256: 2302 movs r3, #2
}
}
8006258: 4618 mov r0, r3
800625a: 3718 adds r7, #24
800625c: 46bd mov sp, r7
800625e: bd80 pop {r7, pc}
8006260: fe00e800 .word 0xfe00e800
08006264 <HAL_I2C_Mem_Read>:
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8006264: b580 push {r7, lr}
8006266: b088 sub sp, #32
8006268: af02 add r7, sp, #8
800626a: 60f8 str r0, [r7, #12]
800626c: 4608 mov r0, r1
800626e: 4611 mov r1, r2
8006270: 461a mov r2, r3
8006272: 4603 mov r3, r0
8006274: 817b strh r3, [r7, #10]
8006276: 460b mov r3, r1
8006278: 813b strh r3, [r7, #8]
800627a: 4613 mov r3, r2
800627c: 80fb strh r3, [r7, #6]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
800627e: 68fb ldr r3, [r7, #12]
8006280: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8006284: b2db uxtb r3, r3
8006286: 2b20 cmp r3, #32
8006288: f040 80fd bne.w 8006486 <HAL_I2C_Mem_Read+0x222>
{
if ((pData == NULL) || (Size == 0U))
800628c: 6a3b ldr r3, [r7, #32]
800628e: 2b00 cmp r3, #0
8006290: d002 beq.n 8006298 <HAL_I2C_Mem_Read+0x34>
8006292: 8cbb ldrh r3, [r7, #36] ; 0x24
8006294: 2b00 cmp r3, #0
8006296: d105 bne.n 80062a4 <HAL_I2C_Mem_Read+0x40>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8006298: 68fb ldr r3, [r7, #12]
800629a: f44f 7200 mov.w r2, #512 ; 0x200
800629e: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
80062a0: 2301 movs r3, #1
80062a2: e0f1 b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
/* Process Locked */
__HAL_LOCK(hi2c);
80062a4: 68fb ldr r3, [r7, #12]
80062a6: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
80062aa: 2b01 cmp r3, #1
80062ac: d101 bne.n 80062b2 <HAL_I2C_Mem_Read+0x4e>
80062ae: 2302 movs r3, #2
80062b0: e0ea b.n 8006488 <HAL_I2C_Mem_Read+0x224>
80062b2: 68fb ldr r3, [r7, #12]
80062b4: 2201 movs r2, #1
80062b6: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80062ba: f7fe f919 bl 80044f0 <HAL_GetTick>
80062be: 6178 str r0, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
80062c0: 697b ldr r3, [r7, #20]
80062c2: 9300 str r3, [sp, #0]
80062c4: 2319 movs r3, #25
80062c6: 2201 movs r2, #1
80062c8: f44f 4100 mov.w r1, #32768 ; 0x8000
80062cc: 68f8 ldr r0, [r7, #12]
80062ce: f000 f9bd bl 800664c <I2C_WaitOnFlagUntilTimeout>
80062d2: 4603 mov r3, r0
80062d4: 2b00 cmp r3, #0
80062d6: d001 beq.n 80062dc <HAL_I2C_Mem_Read+0x78>
{
return HAL_ERROR;
80062d8: 2301 movs r3, #1
80062da: e0d5 b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
80062dc: 68fb ldr r3, [r7, #12]
80062de: 2222 movs r2, #34 ; 0x22
80062e0: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_MEM;
80062e4: 68fb ldr r3, [r7, #12]
80062e6: 2240 movs r2, #64 ; 0x40
80062e8: f883 2042 strb.w r2, [r3, #66] ; 0x42
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80062ec: 68fb ldr r3, [r7, #12]
80062ee: 2200 movs r2, #0
80062f0: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
80062f2: 68fb ldr r3, [r7, #12]
80062f4: 6a3a ldr r2, [r7, #32]
80062f6: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount = Size;
80062f8: 68fb ldr r3, [r7, #12]
80062fa: 8cba ldrh r2, [r7, #36] ; 0x24
80062fc: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferISR = NULL;
80062fe: 68fb ldr r3, [r7, #12]
8006300: 2200 movs r2, #0
8006302: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
8006304: 88f8 ldrh r0, [r7, #6]
8006306: 893a ldrh r2, [r7, #8]
8006308: 8979 ldrh r1, [r7, #10]
800630a: 697b ldr r3, [r7, #20]
800630c: 9301 str r3, [sp, #4]
800630e: 6abb ldr r3, [r7, #40] ; 0x28
8006310: 9300 str r3, [sp, #0]
8006312: 4603 mov r3, r0
8006314: 68f8 ldr r0, [r7, #12]
8006316: f000 f921 bl 800655c <I2C_RequestMemoryRead>
800631a: 4603 mov r3, r0
800631c: 2b00 cmp r3, #0
800631e: d005 beq.n 800632c <HAL_I2C_Mem_Read+0xc8>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006320: 68fb ldr r3, [r7, #12]
8006322: 2200 movs r2, #0
8006324: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8006328: 2301 movs r3, #1
800632a: e0ad b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800632c: 68fb ldr r3, [r7, #12]
800632e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006330: b29b uxth r3, r3
8006332: 2bff cmp r3, #255 ; 0xff
8006334: d90e bls.n 8006354 <HAL_I2C_Mem_Read+0xf0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8006336: 68fb ldr r3, [r7, #12]
8006338: 22ff movs r2, #255 ; 0xff
800633a: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
800633c: 68fb ldr r3, [r7, #12]
800633e: 8d1b ldrh r3, [r3, #40] ; 0x28
8006340: b2da uxtb r2, r3
8006342: 8979 ldrh r1, [r7, #10]
8006344: 4b52 ldr r3, [pc, #328] ; (8006490 <HAL_I2C_Mem_Read+0x22c>)
8006346: 9300 str r3, [sp, #0]
8006348: f04f 7380 mov.w r3, #16777216 ; 0x1000000
800634c: 68f8 ldr r0, [r7, #12]
800634e: f000 fa9f bl 8006890 <I2C_TransferConfig>
8006352: e00f b.n 8006374 <HAL_I2C_Mem_Read+0x110>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8006354: 68fb ldr r3, [r7, #12]
8006356: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006358: b29a uxth r2, r3
800635a: 68fb ldr r3, [r7, #12]
800635c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
800635e: 68fb ldr r3, [r7, #12]
8006360: 8d1b ldrh r3, [r3, #40] ; 0x28
8006362: b2da uxtb r2, r3
8006364: 8979 ldrh r1, [r7, #10]
8006366: 4b4a ldr r3, [pc, #296] ; (8006490 <HAL_I2C_Mem_Read+0x22c>)
8006368: 9300 str r3, [sp, #0]
800636a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800636e: 68f8 ldr r0, [r7, #12]
8006370: f000 fa8e bl 8006890 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
8006374: 697b ldr r3, [r7, #20]
8006376: 9300 str r3, [sp, #0]
8006378: 6abb ldr r3, [r7, #40] ; 0x28
800637a: 2200 movs r2, #0
800637c: 2104 movs r1, #4
800637e: 68f8 ldr r0, [r7, #12]
8006380: f000 f964 bl 800664c <I2C_WaitOnFlagUntilTimeout>
8006384: 4603 mov r3, r0
8006386: 2b00 cmp r3, #0
8006388: d001 beq.n 800638e <HAL_I2C_Mem_Read+0x12a>
{
return HAL_ERROR;
800638a: 2301 movs r3, #1
800638c: e07c b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
800638e: 68fb ldr r3, [r7, #12]
8006390: 681b ldr r3, [r3, #0]
8006392: 6a5a ldr r2, [r3, #36] ; 0x24
8006394: 68fb ldr r3, [r7, #12]
8006396: 6a5b ldr r3, [r3, #36] ; 0x24
8006398: b2d2 uxtb r2, r2
800639a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
800639c: 68fb ldr r3, [r7, #12]
800639e: 6a5b ldr r3, [r3, #36] ; 0x24
80063a0: 1c5a adds r2, r3, #1
80063a2: 68fb ldr r3, [r7, #12]
80063a4: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
80063a6: 68fb ldr r3, [r7, #12]
80063a8: 8d1b ldrh r3, [r3, #40] ; 0x28
80063aa: 3b01 subs r3, #1
80063ac: b29a uxth r2, r3
80063ae: 68fb ldr r3, [r7, #12]
80063b0: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
80063b2: 68fb ldr r3, [r7, #12]
80063b4: 8d5b ldrh r3, [r3, #42] ; 0x2a
80063b6: b29b uxth r3, r3
80063b8: 3b01 subs r3, #1
80063ba: b29a uxth r2, r3
80063bc: 68fb ldr r3, [r7, #12]
80063be: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
80063c0: 68fb ldr r3, [r7, #12]
80063c2: 8d5b ldrh r3, [r3, #42] ; 0x2a
80063c4: b29b uxth r3, r3
80063c6: 2b00 cmp r3, #0
80063c8: d034 beq.n 8006434 <HAL_I2C_Mem_Read+0x1d0>
80063ca: 68fb ldr r3, [r7, #12]
80063cc: 8d1b ldrh r3, [r3, #40] ; 0x28
80063ce: 2b00 cmp r3, #0
80063d0: d130 bne.n 8006434 <HAL_I2C_Mem_Read+0x1d0>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
80063d2: 697b ldr r3, [r7, #20]
80063d4: 9300 str r3, [sp, #0]
80063d6: 6abb ldr r3, [r7, #40] ; 0x28
80063d8: 2200 movs r2, #0
80063da: 2180 movs r1, #128 ; 0x80
80063dc: 68f8 ldr r0, [r7, #12]
80063de: f000 f935 bl 800664c <I2C_WaitOnFlagUntilTimeout>
80063e2: 4603 mov r3, r0
80063e4: 2b00 cmp r3, #0
80063e6: d001 beq.n 80063ec <HAL_I2C_Mem_Read+0x188>
{
return HAL_ERROR;
80063e8: 2301 movs r3, #1
80063ea: e04d b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80063ec: 68fb ldr r3, [r7, #12]
80063ee: 8d5b ldrh r3, [r3, #42] ; 0x2a
80063f0: b29b uxth r3, r3
80063f2: 2bff cmp r3, #255 ; 0xff
80063f4: d90e bls.n 8006414 <HAL_I2C_Mem_Read+0x1b0>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80063f6: 68fb ldr r3, [r7, #12]
80063f8: 22ff movs r2, #255 ; 0xff
80063fa: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
80063fc: 68fb ldr r3, [r7, #12]
80063fe: 8d1b ldrh r3, [r3, #40] ; 0x28
8006400: b2da uxtb r2, r3
8006402: 8979 ldrh r1, [r7, #10]
8006404: 2300 movs r3, #0
8006406: 9300 str r3, [sp, #0]
8006408: f04f 7380 mov.w r3, #16777216 ; 0x1000000
800640c: 68f8 ldr r0, [r7, #12]
800640e: f000 fa3f bl 8006890 <I2C_TransferConfig>
8006412: e00f b.n 8006434 <HAL_I2C_Mem_Read+0x1d0>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8006414: 68fb ldr r3, [r7, #12]
8006416: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006418: b29a uxth r2, r3
800641a: 68fb ldr r3, [r7, #12]
800641c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
800641e: 68fb ldr r3, [r7, #12]
8006420: 8d1b ldrh r3, [r3, #40] ; 0x28
8006422: b2da uxtb r2, r3
8006424: 8979 ldrh r1, [r7, #10]
8006426: 2300 movs r3, #0
8006428: 9300 str r3, [sp, #0]
800642a: f04f 7300 mov.w r3, #33554432 ; 0x2000000
800642e: 68f8 ldr r0, [r7, #12]
8006430: f000 fa2e bl 8006890 <I2C_TransferConfig>
}
}
}
while (hi2c->XferCount > 0U);
8006434: 68fb ldr r3, [r7, #12]
8006436: 8d5b ldrh r3, [r3, #42] ; 0x2a
8006438: b29b uxth r3, r3
800643a: 2b00 cmp r3, #0
800643c: d19a bne.n 8006374 <HAL_I2C_Mem_Read+0x110>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
800643e: 697a ldr r2, [r7, #20]
8006440: 6ab9 ldr r1, [r7, #40] ; 0x28
8006442: 68f8 ldr r0, [r7, #12]
8006444: f000 f982 bl 800674c <I2C_WaitOnSTOPFlagUntilTimeout>
8006448: 4603 mov r3, r0
800644a: 2b00 cmp r3, #0
800644c: d001 beq.n 8006452 <HAL_I2C_Mem_Read+0x1ee>
{
return HAL_ERROR;
800644e: 2301 movs r3, #1
8006450: e01a b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8006452: 68fb ldr r3, [r7, #12]
8006454: 681b ldr r3, [r3, #0]
8006456: 2220 movs r2, #32
8006458: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800645a: 68fb ldr r3, [r7, #12]
800645c: 681b ldr r3, [r3, #0]
800645e: 6859 ldr r1, [r3, #4]
8006460: 68fb ldr r3, [r7, #12]
8006462: 681a ldr r2, [r3, #0]
8006464: 4b0b ldr r3, [pc, #44] ; (8006494 <HAL_I2C_Mem_Read+0x230>)
8006466: 400b ands r3, r1
8006468: 6053 str r3, [r2, #4]
hi2c->State = HAL_I2C_STATE_READY;
800646a: 68fb ldr r3, [r7, #12]
800646c: 2220 movs r2, #32
800646e: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006472: 68fb ldr r3, [r7, #12]
8006474: 2200 movs r2, #0
8006476: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800647a: 68fb ldr r3, [r7, #12]
800647c: 2200 movs r2, #0
800647e: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8006482: 2300 movs r3, #0
8006484: e000 b.n 8006488 <HAL_I2C_Mem_Read+0x224>
}
else
{
return HAL_BUSY;
8006486: 2302 movs r3, #2
}
}
8006488: 4618 mov r0, r3
800648a: 3718 adds r7, #24
800648c: 46bd mov sp, r7
800648e: bd80 pop {r7, pc}
8006490: 80002400 .word 0x80002400
8006494: fe00e800 .word 0xfe00e800
08006498 <HAL_I2C_GetState>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL state
*/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
{
8006498: b480 push {r7}
800649a: b083 sub sp, #12
800649c: af00 add r7, sp, #0
800649e: 6078 str r0, [r7, #4]
/* Return I2C handle state */
return hi2c->State;
80064a0: 687b ldr r3, [r7, #4]
80064a2: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80064a6: b2db uxtb r3, r3
}
80064a8: 4618 mov r0, r3
80064aa: 370c adds r7, #12
80064ac: 46bd mov sp, r7
80064ae: f85d 7b04 ldr.w r7, [sp], #4
80064b2: 4770 bx lr
080064b4 <I2C_RequestMemoryWrite>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
80064b4: b580 push {r7, lr}
80064b6: b086 sub sp, #24
80064b8: af02 add r7, sp, #8
80064ba: 60f8 str r0, [r7, #12]
80064bc: 4608 mov r0, r1
80064be: 4611 mov r1, r2
80064c0: 461a mov r2, r3
80064c2: 4603 mov r3, r0
80064c4: 817b strh r3, [r7, #10]
80064c6: 460b mov r3, r1
80064c8: 813b strh r3, [r7, #8]
80064ca: 4613 mov r3, r2
80064cc: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
80064ce: 88fb ldrh r3, [r7, #6]
80064d0: b2da uxtb r2, r3
80064d2: 8979 ldrh r1, [r7, #10]
80064d4: 4b20 ldr r3, [pc, #128] ; (8006558 <I2C_RequestMemoryWrite+0xa4>)
80064d6: 9300 str r3, [sp, #0]
80064d8: f04f 7380 mov.w r3, #16777216 ; 0x1000000
80064dc: 68f8 ldr r0, [r7, #12]
80064de: f000 f9d7 bl 8006890 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
80064e2: 69fa ldr r2, [r7, #28]
80064e4: 69b9 ldr r1, [r7, #24]
80064e6: 68f8 ldr r0, [r7, #12]
80064e8: f000 f8f0 bl 80066cc <I2C_WaitOnTXISFlagUntilTimeout>
80064ec: 4603 mov r3, r0
80064ee: 2b00 cmp r3, #0
80064f0: d001 beq.n 80064f6 <I2C_RequestMemoryWrite+0x42>
{
return HAL_ERROR;
80064f2: 2301 movs r3, #1
80064f4: e02c b.n 8006550 <I2C_RequestMemoryWrite+0x9c>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
80064f6: 88fb ldrh r3, [r7, #6]
80064f8: 2b01 cmp r3, #1
80064fa: d105 bne.n 8006508 <I2C_RequestMemoryWrite+0x54>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80064fc: 893b ldrh r3, [r7, #8]
80064fe: b2da uxtb r2, r3
8006500: 68fb ldr r3, [r7, #12]
8006502: 681b ldr r3, [r3, #0]
8006504: 629a str r2, [r3, #40] ; 0x28
8006506: e015 b.n 8006534 <I2C_RequestMemoryWrite+0x80>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
8006508: 893b ldrh r3, [r7, #8]
800650a: 0a1b lsrs r3, r3, #8
800650c: b29b uxth r3, r3
800650e: b2da uxtb r2, r3
8006510: 68fb ldr r3, [r7, #12]
8006512: 681b ldr r3, [r3, #0]
8006514: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8006516: 69fa ldr r2, [r7, #28]
8006518: 69b9 ldr r1, [r7, #24]
800651a: 68f8 ldr r0, [r7, #12]
800651c: f000 f8d6 bl 80066cc <I2C_WaitOnTXISFlagUntilTimeout>
8006520: 4603 mov r3, r0
8006522: 2b00 cmp r3, #0
8006524: d001 beq.n 800652a <I2C_RequestMemoryWrite+0x76>
{
return HAL_ERROR;
8006526: 2301 movs r3, #1
8006528: e012 b.n 8006550 <I2C_RequestMemoryWrite+0x9c>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
800652a: 893b ldrh r3, [r7, #8]
800652c: b2da uxtb r2, r3
800652e: 68fb ldr r3, [r7, #12]
8006530: 681b ldr r3, [r3, #0]
8006532: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
8006534: 69fb ldr r3, [r7, #28]
8006536: 9300 str r3, [sp, #0]
8006538: 69bb ldr r3, [r7, #24]
800653a: 2200 movs r2, #0
800653c: 2180 movs r1, #128 ; 0x80
800653e: 68f8 ldr r0, [r7, #12]
8006540: f000 f884 bl 800664c <I2C_WaitOnFlagUntilTimeout>
8006544: 4603 mov r3, r0
8006546: 2b00 cmp r3, #0
8006548: d001 beq.n 800654e <I2C_RequestMemoryWrite+0x9a>
{
return HAL_ERROR;
800654a: 2301 movs r3, #1
800654c: e000 b.n 8006550 <I2C_RequestMemoryWrite+0x9c>
}
return HAL_OK;
800654e: 2300 movs r3, #0
}
8006550: 4618 mov r0, r3
8006552: 3710 adds r7, #16
8006554: 46bd mov sp, r7
8006556: bd80 pop {r7, pc}
8006558: 80002000 .word 0x80002000
0800655c <I2C_RequestMemoryRead>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
800655c: b580 push {r7, lr}
800655e: b086 sub sp, #24
8006560: af02 add r7, sp, #8
8006562: 60f8 str r0, [r7, #12]
8006564: 4608 mov r0, r1
8006566: 4611 mov r1, r2
8006568: 461a mov r2, r3
800656a: 4603 mov r3, r0
800656c: 817b strh r3, [r7, #10]
800656e: 460b mov r3, r1
8006570: 813b strh r3, [r7, #8]
8006572: 4613 mov r3, r2
8006574: 80fb strh r3, [r7, #6]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
8006576: 88fb ldrh r3, [r7, #6]
8006578: b2da uxtb r2, r3
800657a: 8979 ldrh r1, [r7, #10]
800657c: 4b20 ldr r3, [pc, #128] ; (8006600 <I2C_RequestMemoryRead+0xa4>)
800657e: 9300 str r3, [sp, #0]
8006580: 2300 movs r3, #0
8006582: 68f8 ldr r0, [r7, #12]
8006584: f000 f984 bl 8006890 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
8006588: 69fa ldr r2, [r7, #28]
800658a: 69b9 ldr r1, [r7, #24]
800658c: 68f8 ldr r0, [r7, #12]
800658e: f000 f89d bl 80066cc <I2C_WaitOnTXISFlagUntilTimeout>
8006592: 4603 mov r3, r0
8006594: 2b00 cmp r3, #0
8006596: d001 beq.n 800659c <I2C_RequestMemoryRead+0x40>
{
return HAL_ERROR;
8006598: 2301 movs r3, #1
800659a: e02c b.n 80065f6 <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
800659c: 88fb ldrh r3, [r7, #6]
800659e: 2b01 cmp r3, #1
80065a0: d105 bne.n 80065ae <I2C_RequestMemoryRead+0x52>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80065a2: 893b ldrh r3, [r7, #8]
80065a4: b2da uxtb r2, r3
80065a6: 68fb ldr r3, [r7, #12]
80065a8: 681b ldr r3, [r3, #0]
80065aa: 629a str r2, [r3, #40] ; 0x28
80065ac: e015 b.n 80065da <I2C_RequestMemoryRead+0x7e>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
80065ae: 893b ldrh r3, [r7, #8]
80065b0: 0a1b lsrs r3, r3, #8
80065b2: b29b uxth r3, r3
80065b4: b2da uxtb r2, r3
80065b6: 68fb ldr r3, [r7, #12]
80065b8: 681b ldr r3, [r3, #0]
80065ba: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
80065bc: 69fa ldr r2, [r7, #28]
80065be: 69b9 ldr r1, [r7, #24]
80065c0: 68f8 ldr r0, [r7, #12]
80065c2: f000 f883 bl 80066cc <I2C_WaitOnTXISFlagUntilTimeout>
80065c6: 4603 mov r3, r0
80065c8: 2b00 cmp r3, #0
80065ca: d001 beq.n 80065d0 <I2C_RequestMemoryRead+0x74>
{
return HAL_ERROR;
80065cc: 2301 movs r3, #1
80065ce: e012 b.n 80065f6 <I2C_RequestMemoryRead+0x9a>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
80065d0: 893b ldrh r3, [r7, #8]
80065d2: b2da uxtb r2, r3
80065d4: 68fb ldr r3, [r7, #12]
80065d6: 681b ldr r3, [r3, #0]
80065d8: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
80065da: 69fb ldr r3, [r7, #28]
80065dc: 9300 str r3, [sp, #0]
80065de: 69bb ldr r3, [r7, #24]
80065e0: 2200 movs r2, #0
80065e2: 2140 movs r1, #64 ; 0x40
80065e4: 68f8 ldr r0, [r7, #12]
80065e6: f000 f831 bl 800664c <I2C_WaitOnFlagUntilTimeout>
80065ea: 4603 mov r3, r0
80065ec: 2b00 cmp r3, #0
80065ee: d001 beq.n 80065f4 <I2C_RequestMemoryRead+0x98>
{
return HAL_ERROR;
80065f0: 2301 movs r3, #1
80065f2: e000 b.n 80065f6 <I2C_RequestMemoryRead+0x9a>
}
return HAL_OK;
80065f4: 2300 movs r3, #0
}
80065f6: 4618 mov r0, r3
80065f8: 3710 adds r7, #16
80065fa: 46bd mov sp, r7
80065fc: bd80 pop {r7, pc}
80065fe: bf00 nop
8006600: 80002000 .word 0x80002000
08006604 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8006604: b480 push {r7}
8006606: b083 sub sp, #12
8006608: af00 add r7, sp, #0
800660a: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
800660c: 687b ldr r3, [r7, #4]
800660e: 681b ldr r3, [r3, #0]
8006610: 699b ldr r3, [r3, #24]
8006612: f003 0302 and.w r3, r3, #2
8006616: 2b02 cmp r3, #2
8006618: d103 bne.n 8006622 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
800661a: 687b ldr r3, [r7, #4]
800661c: 681b ldr r3, [r3, #0]
800661e: 2200 movs r2, #0
8006620: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8006622: 687b ldr r3, [r7, #4]
8006624: 681b ldr r3, [r3, #0]
8006626: 699b ldr r3, [r3, #24]
8006628: f003 0301 and.w r3, r3, #1
800662c: 2b01 cmp r3, #1
800662e: d007 beq.n 8006640 <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8006630: 687b ldr r3, [r7, #4]
8006632: 681b ldr r3, [r3, #0]
8006634: 699a ldr r2, [r3, #24]
8006636: 687b ldr r3, [r7, #4]
8006638: 681b ldr r3, [r3, #0]
800663a: f042 0201 orr.w r2, r2, #1
800663e: 619a str r2, [r3, #24]
}
}
8006640: bf00 nop
8006642: 370c adds r7, #12
8006644: 46bd mov sp, r7
8006646: f85d 7b04 ldr.w r7, [sp], #4
800664a: 4770 bx lr
0800664c <I2C_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
800664c: b580 push {r7, lr}
800664e: b084 sub sp, #16
8006650: af00 add r7, sp, #0
8006652: 60f8 str r0, [r7, #12]
8006654: 60b9 str r1, [r7, #8]
8006656: 603b str r3, [r7, #0]
8006658: 4613 mov r3, r2
800665a: 71fb strb r3, [r7, #7]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
800665c: e022 b.n 80066a4 <I2C_WaitOnFlagUntilTimeout+0x58>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800665e: 683b ldr r3, [r7, #0]
8006660: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8006664: d01e beq.n 80066a4 <I2C_WaitOnFlagUntilTimeout+0x58>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8006666: f7fd ff43 bl 80044f0 <HAL_GetTick>
800666a: 4602 mov r2, r0
800666c: 69bb ldr r3, [r7, #24]
800666e: 1ad3 subs r3, r2, r3
8006670: 683a ldr r2, [r7, #0]
8006672: 429a cmp r2, r3
8006674: d302 bcc.n 800667c <I2C_WaitOnFlagUntilTimeout+0x30>
8006676: 683b ldr r3, [r7, #0]
8006678: 2b00 cmp r3, #0
800667a: d113 bne.n 80066a4 <I2C_WaitOnFlagUntilTimeout+0x58>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
800667c: 68fb ldr r3, [r7, #12]
800667e: 6c5b ldr r3, [r3, #68] ; 0x44
8006680: f043 0220 orr.w r2, r3, #32
8006684: 68fb ldr r3, [r7, #12]
8006686: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8006688: 68fb ldr r3, [r7, #12]
800668a: 2220 movs r2, #32
800668c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006690: 68fb ldr r3, [r7, #12]
8006692: 2200 movs r2, #0
8006694: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006698: 68fb ldr r3, [r7, #12]
800669a: 2200 movs r2, #0
800669c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
80066a0: 2301 movs r3, #1
80066a2: e00f b.n 80066c4 <I2C_WaitOnFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
80066a4: 68fb ldr r3, [r7, #12]
80066a6: 681b ldr r3, [r3, #0]
80066a8: 699a ldr r2, [r3, #24]
80066aa: 68bb ldr r3, [r7, #8]
80066ac: 4013 ands r3, r2
80066ae: 68ba ldr r2, [r7, #8]
80066b0: 429a cmp r2, r3
80066b2: bf0c ite eq
80066b4: 2301 moveq r3, #1
80066b6: 2300 movne r3, #0
80066b8: b2db uxtb r3, r3
80066ba: 461a mov r2, r3
80066bc: 79fb ldrb r3, [r7, #7]
80066be: 429a cmp r2, r3
80066c0: d0cd beq.n 800665e <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
80066c2: 2300 movs r3, #0
}
80066c4: 4618 mov r0, r3
80066c6: 3710 adds r7, #16
80066c8: 46bd mov sp, r7
80066ca: bd80 pop {r7, pc}
080066cc <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
80066cc: b580 push {r7, lr}
80066ce: b084 sub sp, #16
80066d0: af00 add r7, sp, #0
80066d2: 60f8 str r0, [r7, #12]
80066d4: 60b9 str r1, [r7, #8]
80066d6: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
80066d8: e02c b.n 8006734 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
80066da: 687a ldr r2, [r7, #4]
80066dc: 68b9 ldr r1, [r7, #8]
80066de: 68f8 ldr r0, [r7, #12]
80066e0: f000 f870 bl 80067c4 <I2C_IsAcknowledgeFailed>
80066e4: 4603 mov r3, r0
80066e6: 2b00 cmp r3, #0
80066e8: d001 beq.n 80066ee <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
80066ea: 2301 movs r3, #1
80066ec: e02a b.n 8006744 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80066ee: 68bb ldr r3, [r7, #8]
80066f0: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80066f4: d01e beq.n 8006734 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80066f6: f7fd fefb bl 80044f0 <HAL_GetTick>
80066fa: 4602 mov r2, r0
80066fc: 687b ldr r3, [r7, #4]
80066fe: 1ad3 subs r3, r2, r3
8006700: 68ba ldr r2, [r7, #8]
8006702: 429a cmp r2, r3
8006704: d302 bcc.n 800670c <I2C_WaitOnTXISFlagUntilTimeout+0x40>
8006706: 68bb ldr r3, [r7, #8]
8006708: 2b00 cmp r3, #0
800670a: d113 bne.n 8006734 <I2C_WaitOnTXISFlagUntilTimeout+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
800670c: 68fb ldr r3, [r7, #12]
800670e: 6c5b ldr r3, [r3, #68] ; 0x44
8006710: f043 0220 orr.w r2, r3, #32
8006714: 68fb ldr r3, [r7, #12]
8006716: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8006718: 68fb ldr r3, [r7, #12]
800671a: 2220 movs r2, #32
800671c: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006720: 68fb ldr r3, [r7, #12]
8006722: 2200 movs r2, #0
8006724: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006728: 68fb ldr r3, [r7, #12]
800672a: 2200 movs r2, #0
800672c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8006730: 2301 movs r3, #1
8006732: e007 b.n 8006744 <I2C_WaitOnTXISFlagUntilTimeout+0x78>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
8006734: 68fb ldr r3, [r7, #12]
8006736: 681b ldr r3, [r3, #0]
8006738: 699b ldr r3, [r3, #24]
800673a: f003 0302 and.w r3, r3, #2
800673e: 2b02 cmp r3, #2
8006740: d1cb bne.n 80066da <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
8006742: 2300 movs r3, #0
}
8006744: 4618 mov r0, r3
8006746: 3710 adds r7, #16
8006748: 46bd mov sp, r7
800674a: bd80 pop {r7, pc}
0800674c <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
800674c: b580 push {r7, lr}
800674e: b084 sub sp, #16
8006750: af00 add r7, sp, #0
8006752: 60f8 str r0, [r7, #12]
8006754: 60b9 str r1, [r7, #8]
8006756: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8006758: e028 b.n 80067ac <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
800675a: 687a ldr r2, [r7, #4]
800675c: 68b9 ldr r1, [r7, #8]
800675e: 68f8 ldr r0, [r7, #12]
8006760: f000 f830 bl 80067c4 <I2C_IsAcknowledgeFailed>
8006764: 4603 mov r3, r0
8006766: 2b00 cmp r3, #0
8006768: d001 beq.n 800676e <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
800676a: 2301 movs r3, #1
800676c: e026 b.n 80067bc <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800676e: f7fd febf bl 80044f0 <HAL_GetTick>
8006772: 4602 mov r2, r0
8006774: 687b ldr r3, [r7, #4]
8006776: 1ad3 subs r3, r2, r3
8006778: 68ba ldr r2, [r7, #8]
800677a: 429a cmp r2, r3
800677c: d302 bcc.n 8006784 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
800677e: 68bb ldr r3, [r7, #8]
8006780: 2b00 cmp r3, #0
8006782: d113 bne.n 80067ac <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
8006784: 68fb ldr r3, [r7, #12]
8006786: 6c5b ldr r3, [r3, #68] ; 0x44
8006788: f043 0220 orr.w r2, r3, #32
800678c: 68fb ldr r3, [r7, #12]
800678e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8006790: 68fb ldr r3, [r7, #12]
8006792: 2220 movs r2, #32
8006794: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006798: 68fb ldr r3, [r7, #12]
800679a: 2200 movs r2, #0
800679c: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80067a0: 68fb ldr r3, [r7, #12]
80067a2: 2200 movs r2, #0
80067a4: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
80067a8: 2301 movs r3, #1
80067aa: e007 b.n 80067bc <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80067ac: 68fb ldr r3, [r7, #12]
80067ae: 681b ldr r3, [r3, #0]
80067b0: 699b ldr r3, [r3, #24]
80067b2: f003 0320 and.w r3, r3, #32
80067b6: 2b20 cmp r3, #32
80067b8: d1cf bne.n 800675a <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
80067ba: 2300 movs r3, #0
}
80067bc: 4618 mov r0, r3
80067be: 3710 adds r7, #16
80067c0: 46bd mov sp, r7
80067c2: bd80 pop {r7, pc}
080067c4 <I2C_IsAcknowledgeFailed>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
80067c4: b580 push {r7, lr}
80067c6: b084 sub sp, #16
80067c8: af00 add r7, sp, #0
80067ca: 60f8 str r0, [r7, #12]
80067cc: 60b9 str r1, [r7, #8]
80067ce: 607a str r2, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
80067d0: 68fb ldr r3, [r7, #12]
80067d2: 681b ldr r3, [r3, #0]
80067d4: 699b ldr r3, [r3, #24]
80067d6: f003 0310 and.w r3, r3, #16
80067da: 2b10 cmp r3, #16
80067dc: d151 bne.n 8006882 <I2C_IsAcknowledgeFailed+0xbe>
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
80067de: e022 b.n 8006826 <I2C_IsAcknowledgeFailed+0x62>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80067e0: 68bb ldr r3, [r7, #8]
80067e2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80067e6: d01e beq.n 8006826 <I2C_IsAcknowledgeFailed+0x62>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80067e8: f7fd fe82 bl 80044f0 <HAL_GetTick>
80067ec: 4602 mov r2, r0
80067ee: 687b ldr r3, [r7, #4]
80067f0: 1ad3 subs r3, r2, r3
80067f2: 68ba ldr r2, [r7, #8]
80067f4: 429a cmp r2, r3
80067f6: d302 bcc.n 80067fe <I2C_IsAcknowledgeFailed+0x3a>
80067f8: 68bb ldr r3, [r7, #8]
80067fa: 2b00 cmp r3, #0
80067fc: d113 bne.n 8006826 <I2C_IsAcknowledgeFailed+0x62>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
80067fe: 68fb ldr r3, [r7, #12]
8006800: 6c5b ldr r3, [r3, #68] ; 0x44
8006802: f043 0220 orr.w r2, r3, #32
8006806: 68fb ldr r3, [r7, #12]
8006808: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
800680a: 68fb ldr r3, [r7, #12]
800680c: 2220 movs r2, #32
800680e: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
8006812: 68fb ldr r3, [r7, #12]
8006814: 2200 movs r2, #0
8006816: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800681a: 68fb ldr r3, [r7, #12]
800681c: 2200 movs r2, #0
800681e: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
8006822: 2301 movs r3, #1
8006824: e02e b.n 8006884 <I2C_IsAcknowledgeFailed+0xc0>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
8006826: 68fb ldr r3, [r7, #12]
8006828: 681b ldr r3, [r3, #0]
800682a: 699b ldr r3, [r3, #24]
800682c: f003 0320 and.w r3, r3, #32
8006830: 2b20 cmp r3, #32
8006832: d1d5 bne.n 80067e0 <I2C_IsAcknowledgeFailed+0x1c>
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8006834: 68fb ldr r3, [r7, #12]
8006836: 681b ldr r3, [r3, #0]
8006838: 2210 movs r2, #16
800683a: 61da str r2, [r3, #28]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
800683c: 68fb ldr r3, [r7, #12]
800683e: 681b ldr r3, [r3, #0]
8006840: 2220 movs r2, #32
8006842: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8006844: 68f8 ldr r0, [r7, #12]
8006846: f7ff fedd bl 8006604 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
800684a: 68fb ldr r3, [r7, #12]
800684c: 681b ldr r3, [r3, #0]
800684e: 6859 ldr r1, [r3, #4]
8006850: 68fb ldr r3, [r7, #12]
8006852: 681a ldr r2, [r3, #0]
8006854: 4b0d ldr r3, [pc, #52] ; (800688c <I2C_IsAcknowledgeFailed+0xc8>)
8006856: 400b ands r3, r1
8006858: 6053 str r3, [r2, #4]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800685a: 68fb ldr r3, [r7, #12]
800685c: 6c5b ldr r3, [r3, #68] ; 0x44
800685e: f043 0204 orr.w r2, r3, #4
8006862: 68fb ldr r3, [r7, #12]
8006864: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
8006866: 68fb ldr r3, [r7, #12]
8006868: 2220 movs r2, #32
800686a: f883 2041 strb.w r2, [r3, #65] ; 0x41
hi2c->Mode = HAL_I2C_MODE_NONE;
800686e: 68fb ldr r3, [r7, #12]
8006870: 2200 movs r2, #0
8006872: f883 2042 strb.w r2, [r3, #66] ; 0x42
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006876: 68fb ldr r3, [r7, #12]
8006878: 2200 movs r2, #0
800687a: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_ERROR;
800687e: 2301 movs r3, #1
8006880: e000 b.n 8006884 <I2C_IsAcknowledgeFailed+0xc0>
}
return HAL_OK;
8006882: 2300 movs r3, #0
}
8006884: 4618 mov r0, r3
8006886: 3710 adds r7, #16
8006888: 46bd mov sp, r7
800688a: bd80 pop {r7, pc}
800688c: fe00e800 .word 0xfe00e800
08006890 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
8006890: b480 push {r7}
8006892: b085 sub sp, #20
8006894: af00 add r7, sp, #0
8006896: 60f8 str r0, [r7, #12]
8006898: 607b str r3, [r7, #4]
800689a: 460b mov r3, r1
800689c: 817b strh r3, [r7, #10]
800689e: 4613 mov r3, r2
80068a0: 727b strb r3, [r7, #9]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
80068a2: 68fb ldr r3, [r7, #12]
80068a4: 681b ldr r3, [r3, #0]
80068a6: 685a ldr r2, [r3, #4]
80068a8: 69bb ldr r3, [r7, #24]
80068aa: 0d5b lsrs r3, r3, #21
80068ac: f403 6180 and.w r1, r3, #1024 ; 0x400
80068b0: 4b0d ldr r3, [pc, #52] ; (80068e8 <I2C_TransferConfig+0x58>)
80068b2: 430b orrs r3, r1
80068b4: 43db mvns r3, r3
80068b6: ea02 0103 and.w r1, r2, r3
80068ba: 897b ldrh r3, [r7, #10]
80068bc: f3c3 0209 ubfx r2, r3, #0, #10
80068c0: 7a7b ldrb r3, [r7, #9]
80068c2: 041b lsls r3, r3, #16
80068c4: f403 037f and.w r3, r3, #16711680 ; 0xff0000
80068c8: 431a orrs r2, r3
80068ca: 687b ldr r3, [r7, #4]
80068cc: 431a orrs r2, r3
80068ce: 69bb ldr r3, [r7, #24]
80068d0: 431a orrs r2, r3
80068d2: 68fb ldr r3, [r7, #12]
80068d4: 681b ldr r3, [r3, #0]
80068d6: 430a orrs r2, r1
80068d8: 605a str r2, [r3, #4]
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
80068da: bf00 nop
80068dc: 3714 adds r7, #20
80068de: 46bd mov sp, r7
80068e0: f85d 7b04 ldr.w r7, [sp], #4
80068e4: 4770 bx lr
80068e6: bf00 nop
80068e8: 03ff63ff .word 0x03ff63ff
080068ec <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
80068ec: b480 push {r7}
80068ee: b083 sub sp, #12
80068f0: af00 add r7, sp, #0
80068f2: 6078 str r0, [r7, #4]
80068f4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80068f6: 687b ldr r3, [r7, #4]
80068f8: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
80068fc: b2db uxtb r3, r3
80068fe: 2b20 cmp r3, #32
8006900: d138 bne.n 8006974 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8006902: 687b ldr r3, [r7, #4]
8006904: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
8006908: 2b01 cmp r3, #1
800690a: d101 bne.n 8006910 <HAL_I2CEx_ConfigAnalogFilter+0x24>
800690c: 2302 movs r3, #2
800690e: e032 b.n 8006976 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8006910: 687b ldr r3, [r7, #4]
8006912: 2201 movs r2, #1
8006914: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
8006918: 687b ldr r3, [r7, #4]
800691a: 2224 movs r2, #36 ; 0x24
800691c: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8006920: 687b ldr r3, [r7, #4]
8006922: 681b ldr r3, [r3, #0]
8006924: 681a ldr r2, [r3, #0]
8006926: 687b ldr r3, [r7, #4]
8006928: 681b ldr r3, [r3, #0]
800692a: f022 0201 bic.w r2, r2, #1
800692e: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8006930: 687b ldr r3, [r7, #4]
8006932: 681b ldr r3, [r3, #0]
8006934: 681a ldr r2, [r3, #0]
8006936: 687b ldr r3, [r7, #4]
8006938: 681b ldr r3, [r3, #0]
800693a: f422 5280 bic.w r2, r2, #4096 ; 0x1000
800693e: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
8006940: 687b ldr r3, [r7, #4]
8006942: 681b ldr r3, [r3, #0]
8006944: 6819 ldr r1, [r3, #0]
8006946: 687b ldr r3, [r7, #4]
8006948: 681b ldr r3, [r3, #0]
800694a: 683a ldr r2, [r7, #0]
800694c: 430a orrs r2, r1
800694e: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8006950: 687b ldr r3, [r7, #4]
8006952: 681b ldr r3, [r3, #0]
8006954: 681a ldr r2, [r3, #0]
8006956: 687b ldr r3, [r7, #4]
8006958: 681b ldr r3, [r3, #0]
800695a: f042 0201 orr.w r2, r2, #1
800695e: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8006960: 687b ldr r3, [r7, #4]
8006962: 2220 movs r2, #32
8006964: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006968: 687b ldr r3, [r7, #4]
800696a: 2200 movs r2, #0
800696c: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8006970: 2300 movs r3, #0
8006972: e000 b.n 8006976 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
8006974: 2302 movs r3, #2
}
}
8006976: 4618 mov r0, r3
8006978: 370c adds r7, #12
800697a: 46bd mov sp, r7
800697c: f85d 7b04 ldr.w r7, [sp], #4
8006980: 4770 bx lr
08006982 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8006982: b480 push {r7}
8006984: b085 sub sp, #20
8006986: af00 add r7, sp, #0
8006988: 6078 str r0, [r7, #4]
800698a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800698c: 687b ldr r3, [r7, #4]
800698e: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8006992: b2db uxtb r3, r3
8006994: 2b20 cmp r3, #32
8006996: d139 bne.n 8006a0c <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8006998: 687b ldr r3, [r7, #4]
800699a: f893 3040 ldrb.w r3, [r3, #64] ; 0x40
800699e: 2b01 cmp r3, #1
80069a0: d101 bne.n 80069a6 <HAL_I2CEx_ConfigDigitalFilter+0x24>
80069a2: 2302 movs r3, #2
80069a4: e033 b.n 8006a0e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
80069a6: 687b ldr r3, [r7, #4]
80069a8: 2201 movs r2, #1
80069aa: f883 2040 strb.w r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_BUSY;
80069ae: 687b ldr r3, [r7, #4]
80069b0: 2224 movs r2, #36 ; 0x24
80069b2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80069b6: 687b ldr r3, [r7, #4]
80069b8: 681b ldr r3, [r3, #0]
80069ba: 681a ldr r2, [r3, #0]
80069bc: 687b ldr r3, [r7, #4]
80069be: 681b ldr r3, [r3, #0]
80069c0: f022 0201 bic.w r2, r2, #1
80069c4: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
80069c6: 687b ldr r3, [r7, #4]
80069c8: 681b ldr r3, [r3, #0]
80069ca: 681b ldr r3, [r3, #0]
80069cc: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
80069ce: 68fb ldr r3, [r7, #12]
80069d0: f423 6370 bic.w r3, r3, #3840 ; 0xf00
80069d4: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
80069d6: 683b ldr r3, [r7, #0]
80069d8: 021b lsls r3, r3, #8
80069da: 68fa ldr r2, [r7, #12]
80069dc: 4313 orrs r3, r2
80069de: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
80069e0: 687b ldr r3, [r7, #4]
80069e2: 681b ldr r3, [r3, #0]
80069e4: 68fa ldr r2, [r7, #12]
80069e6: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80069e8: 687b ldr r3, [r7, #4]
80069ea: 681b ldr r3, [r3, #0]
80069ec: 681a ldr r2, [r3, #0]
80069ee: 687b ldr r3, [r7, #4]
80069f0: 681b ldr r3, [r3, #0]
80069f2: f042 0201 orr.w r2, r2, #1
80069f6: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80069f8: 687b ldr r3, [r7, #4]
80069fa: 2220 movs r2, #32
80069fc: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8006a00: 687b ldr r3, [r7, #4]
8006a02: 2200 movs r2, #0
8006a04: f883 2040 strb.w r2, [r3, #64] ; 0x40
return HAL_OK;
8006a08: 2300 movs r3, #0
8006a0a: e000 b.n 8006a0e <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
8006a0c: 2302 movs r3, #2
}
}
8006a0e: 4618 mov r0, r3
8006a10: 3714 adds r7, #20
8006a12: 46bd mov sp, r7
8006a14: f85d 7b04 ldr.w r7, [sp], #4
8006a18: 4770 bx lr
...
08006a1c <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
8006a1c: b580 push {r7, lr}
8006a1e: b084 sub sp, #16
8006a20: af00 add r7, sp, #0
8006a22: 6078 str r0, [r7, #4]
uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
8006a24: 687b ldr r3, [r7, #4]
8006a26: 2b00 cmp r3, #0
8006a28: d101 bne.n 8006a2e <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
8006a2a: 2301 movs r3, #1
8006a2c: e0bf b.n 8006bae <HAL_LTDC_Init+0x192>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
8006a2e: 687b ldr r3, [r7, #4]
8006a30: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8006a34: b2db uxtb r3, r3
8006a36: 2b00 cmp r3, #0
8006a38: d106 bne.n 8006a48 <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
8006a3a: 687b ldr r3, [r7, #4]
8006a3c: 2200 movs r2, #0
8006a3e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
8006a42: 6878 ldr r0, [r7, #4]
8006a44: f7fd f8b8 bl 8003bb8 <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8006a48: 687b ldr r3, [r7, #4]
8006a4a: 2202 movs r2, #2
8006a4c: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
8006a50: 687b ldr r3, [r7, #4]
8006a52: 681b ldr r3, [r3, #0]
8006a54: 699a ldr r2, [r3, #24]
8006a56: 687b ldr r3, [r7, #4]
8006a58: 681b ldr r3, [r3, #0]
8006a5a: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
8006a5e: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8006a60: 687b ldr r3, [r7, #4]
8006a62: 681b ldr r3, [r3, #0]
8006a64: 6999 ldr r1, [r3, #24]
8006a66: 687b ldr r3, [r7, #4]
8006a68: 685a ldr r2, [r3, #4]
8006a6a: 687b ldr r3, [r7, #4]
8006a6c: 689b ldr r3, [r3, #8]
8006a6e: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8006a70: 687b ldr r3, [r7, #4]
8006a72: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8006a74: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8006a76: 687b ldr r3, [r7, #4]
8006a78: 691b ldr r3, [r3, #16]
8006a7a: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8006a7c: 687b ldr r3, [r7, #4]
8006a7e: 681b ldr r3, [r3, #0]
8006a80: 430a orrs r2, r1
8006a82: 619a str r2, [r3, #24]
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
8006a84: 687b ldr r3, [r7, #4]
8006a86: 681b ldr r3, [r3, #0]
8006a88: 6899 ldr r1, [r3, #8]
8006a8a: 687b ldr r3, [r7, #4]
8006a8c: 681a ldr r2, [r3, #0]
8006a8e: 4b4a ldr r3, [pc, #296] ; (8006bb8 <HAL_LTDC_Init+0x19c>)
8006a90: 400b ands r3, r1
8006a92: 6093 str r3, [r2, #8]
tmp = (hltdc->Init.HorizontalSync << 16U);
8006a94: 687b ldr r3, [r7, #4]
8006a96: 695b ldr r3, [r3, #20]
8006a98: 041b lsls r3, r3, #16
8006a9a: 60fb str r3, [r7, #12]
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
8006a9c: 687b ldr r3, [r7, #4]
8006a9e: 681b ldr r3, [r3, #0]
8006aa0: 6899 ldr r1, [r3, #8]
8006aa2: 687b ldr r3, [r7, #4]
8006aa4: 699a ldr r2, [r3, #24]
8006aa6: 68fb ldr r3, [r7, #12]
8006aa8: 431a orrs r2, r3
8006aaa: 687b ldr r3, [r7, #4]
8006aac: 681b ldr r3, [r3, #0]
8006aae: 430a orrs r2, r1
8006ab0: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
8006ab2: 687b ldr r3, [r7, #4]
8006ab4: 681b ldr r3, [r3, #0]
8006ab6: 68d9 ldr r1, [r3, #12]
8006ab8: 687b ldr r3, [r7, #4]
8006aba: 681a ldr r2, [r3, #0]
8006abc: 4b3e ldr r3, [pc, #248] ; (8006bb8 <HAL_LTDC_Init+0x19c>)
8006abe: 400b ands r3, r1
8006ac0: 60d3 str r3, [r2, #12]
tmp = (hltdc->Init.AccumulatedHBP << 16U);
8006ac2: 687b ldr r3, [r7, #4]
8006ac4: 69db ldr r3, [r3, #28]
8006ac6: 041b lsls r3, r3, #16
8006ac8: 60fb str r3, [r7, #12]
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
8006aca: 687b ldr r3, [r7, #4]
8006acc: 681b ldr r3, [r3, #0]
8006ace: 68d9 ldr r1, [r3, #12]
8006ad0: 687b ldr r3, [r7, #4]
8006ad2: 6a1a ldr r2, [r3, #32]
8006ad4: 68fb ldr r3, [r7, #12]
8006ad6: 431a orrs r2, r3
8006ad8: 687b ldr r3, [r7, #4]
8006ada: 681b ldr r3, [r3, #0]
8006adc: 430a orrs r2, r1
8006ade: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
8006ae0: 687b ldr r3, [r7, #4]
8006ae2: 681b ldr r3, [r3, #0]
8006ae4: 6919 ldr r1, [r3, #16]
8006ae6: 687b ldr r3, [r7, #4]
8006ae8: 681a ldr r2, [r3, #0]
8006aea: 4b33 ldr r3, [pc, #204] ; (8006bb8 <HAL_LTDC_Init+0x19c>)
8006aec: 400b ands r3, r1
8006aee: 6113 str r3, [r2, #16]
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
8006af0: 687b ldr r3, [r7, #4]
8006af2: 6a5b ldr r3, [r3, #36] ; 0x24
8006af4: 041b lsls r3, r3, #16
8006af6: 60fb str r3, [r7, #12]
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
8006af8: 687b ldr r3, [r7, #4]
8006afa: 681b ldr r3, [r3, #0]
8006afc: 6919 ldr r1, [r3, #16]
8006afe: 687b ldr r3, [r7, #4]
8006b00: 6a9a ldr r2, [r3, #40] ; 0x28
8006b02: 68fb ldr r3, [r7, #12]
8006b04: 431a orrs r2, r3
8006b06: 687b ldr r3, [r7, #4]
8006b08: 681b ldr r3, [r3, #0]
8006b0a: 430a orrs r2, r1
8006b0c: 611a str r2, [r3, #16]
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
8006b0e: 687b ldr r3, [r7, #4]
8006b10: 681b ldr r3, [r3, #0]
8006b12: 6959 ldr r1, [r3, #20]
8006b14: 687b ldr r3, [r7, #4]
8006b16: 681a ldr r2, [r3, #0]
8006b18: 4b27 ldr r3, [pc, #156] ; (8006bb8 <HAL_LTDC_Init+0x19c>)
8006b1a: 400b ands r3, r1
8006b1c: 6153 str r3, [r2, #20]
tmp = (hltdc->Init.TotalWidth << 16U);
8006b1e: 687b ldr r3, [r7, #4]
8006b20: 6adb ldr r3, [r3, #44] ; 0x2c
8006b22: 041b lsls r3, r3, #16
8006b24: 60fb str r3, [r7, #12]
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
8006b26: 687b ldr r3, [r7, #4]
8006b28: 681b ldr r3, [r3, #0]
8006b2a: 6959 ldr r1, [r3, #20]
8006b2c: 687b ldr r3, [r7, #4]
8006b2e: 6b1a ldr r2, [r3, #48] ; 0x30
8006b30: 68fb ldr r3, [r7, #12]
8006b32: 431a orrs r2, r3
8006b34: 687b ldr r3, [r7, #4]
8006b36: 681b ldr r3, [r3, #0]
8006b38: 430a orrs r2, r1
8006b3a: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
8006b3c: 687b ldr r3, [r7, #4]
8006b3e: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8006b42: 021b lsls r3, r3, #8
8006b44: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
8006b46: 687b ldr r3, [r7, #4]
8006b48: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
8006b4c: 041b lsls r3, r3, #16
8006b4e: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
8006b50: 687b ldr r3, [r7, #4]
8006b52: 681b ldr r3, [r3, #0]
8006b54: 6ada ldr r2, [r3, #44] ; 0x2c
8006b56: 687b ldr r3, [r7, #4]
8006b58: 681b ldr r3, [r3, #0]
8006b5a: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
8006b5e: 62da str r2, [r3, #44] ; 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8006b60: 687b ldr r3, [r7, #4]
8006b62: 681b ldr r3, [r3, #0]
8006b64: 6ad9 ldr r1, [r3, #44] ; 0x2c
8006b66: 68ba ldr r2, [r7, #8]
8006b68: 68fb ldr r3, [r7, #12]
8006b6a: 4313 orrs r3, r2
8006b6c: 687a ldr r2, [r7, #4]
8006b6e: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
8006b72: 431a orrs r2, r3
8006b74: 687b ldr r3, [r7, #4]
8006b76: 681b ldr r3, [r3, #0]
8006b78: 430a orrs r2, r1
8006b7a: 62da str r2, [r3, #44] ; 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
8006b7c: 687b ldr r3, [r7, #4]
8006b7e: 681b ldr r3, [r3, #0]
8006b80: 6b5a ldr r2, [r3, #52] ; 0x34
8006b82: 687b ldr r3, [r7, #4]
8006b84: 681b ldr r3, [r3, #0]
8006b86: f042 0206 orr.w r2, r2, #6
8006b8a: 635a str r2, [r3, #52] ; 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
8006b8c: 687b ldr r3, [r7, #4]
8006b8e: 681b ldr r3, [r3, #0]
8006b90: 699a ldr r2, [r3, #24]
8006b92: 687b ldr r3, [r7, #4]
8006b94: 681b ldr r3, [r3, #0]
8006b96: f042 0201 orr.w r2, r2, #1
8006b9a: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
8006b9c: 687b ldr r3, [r7, #4]
8006b9e: 2200 movs r2, #0
8006ba0: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8006ba4: 687b ldr r3, [r7, #4]
8006ba6: 2201 movs r2, #1
8006ba8: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
return HAL_OK;
8006bac: 2300 movs r3, #0
}
8006bae: 4618 mov r0, r3
8006bb0: 3710 adds r7, #16
8006bb2: 46bd mov sp, r7
8006bb4: bd80 pop {r7, pc}
8006bb6: bf00 nop
8006bb8: f000f800 .word 0xf000f800
08006bbc <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
8006bbc: b580 push {r7, lr}
8006bbe: b084 sub sp, #16
8006bc0: af00 add r7, sp, #0
8006bc2: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
8006bc4: 687b ldr r3, [r7, #4]
8006bc6: 681b ldr r3, [r3, #0]
8006bc8: 6b9b ldr r3, [r3, #56] ; 0x38
8006bca: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
8006bcc: 687b ldr r3, [r7, #4]
8006bce: 681b ldr r3, [r3, #0]
8006bd0: 6b5b ldr r3, [r3, #52] ; 0x34
8006bd2: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
8006bd4: 68fb ldr r3, [r7, #12]
8006bd6: f003 0304 and.w r3, r3, #4
8006bda: 2b00 cmp r3, #0
8006bdc: d023 beq.n 8006c26 <HAL_LTDC_IRQHandler+0x6a>
8006bde: 68bb ldr r3, [r7, #8]
8006be0: f003 0304 and.w r3, r3, #4
8006be4: 2b00 cmp r3, #0
8006be6: d01e beq.n 8006c26 <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
8006be8: 687b ldr r3, [r7, #4]
8006bea: 681b ldr r3, [r3, #0]
8006bec: 6b5a ldr r2, [r3, #52] ; 0x34
8006bee: 687b ldr r3, [r7, #4]
8006bf0: 681b ldr r3, [r3, #0]
8006bf2: f022 0204 bic.w r2, r2, #4
8006bf6: 635a str r2, [r3, #52] ; 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
8006bf8: 687b ldr r3, [r7, #4]
8006bfa: 681b ldr r3, [r3, #0]
8006bfc: 2204 movs r2, #4
8006bfe: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
8006c00: 687b ldr r3, [r7, #4]
8006c02: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
8006c06: f043 0201 orr.w r2, r3, #1
8006c0a: 687b ldr r3, [r7, #4]
8006c0c: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
8006c10: 687b ldr r3, [r7, #4]
8006c12: 2204 movs r2, #4
8006c14: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8006c18: 687b ldr r3, [r7, #4]
8006c1a: 2200 movs r2, #0
8006c1c: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
8006c20: 6878 ldr r0, [r7, #4]
8006c22: f000 f86f bl 8006d04 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
8006c26: 68fb ldr r3, [r7, #12]
8006c28: f003 0302 and.w r3, r3, #2
8006c2c: 2b00 cmp r3, #0
8006c2e: d023 beq.n 8006c78 <HAL_LTDC_IRQHandler+0xbc>
8006c30: 68bb ldr r3, [r7, #8]
8006c32: f003 0302 and.w r3, r3, #2
8006c36: 2b00 cmp r3, #0
8006c38: d01e beq.n 8006c78 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
8006c3a: 687b ldr r3, [r7, #4]
8006c3c: 681b ldr r3, [r3, #0]
8006c3e: 6b5a ldr r2, [r3, #52] ; 0x34
8006c40: 687b ldr r3, [r7, #4]
8006c42: 681b ldr r3, [r3, #0]
8006c44: f022 0202 bic.w r2, r2, #2
8006c48: 635a str r2, [r3, #52] ; 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
8006c4a: 687b ldr r3, [r7, #4]
8006c4c: 681b ldr r3, [r3, #0]
8006c4e: 2202 movs r2, #2
8006c50: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
8006c52: 687b ldr r3, [r7, #4]
8006c54: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
8006c58: f043 0202 orr.w r2, r3, #2
8006c5c: 687b ldr r3, [r7, #4]
8006c5e: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
8006c62: 687b ldr r3, [r7, #4]
8006c64: 2204 movs r2, #4
8006c66: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8006c6a: 687b ldr r3, [r7, #4]
8006c6c: 2200 movs r2, #0
8006c6e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
8006c72: 6878 ldr r0, [r7, #4]
8006c74: f000 f846 bl 8006d04 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
8006c78: 68fb ldr r3, [r7, #12]
8006c7a: f003 0301 and.w r3, r3, #1
8006c7e: 2b00 cmp r3, #0
8006c80: d01b beq.n 8006cba <HAL_LTDC_IRQHandler+0xfe>
8006c82: 68bb ldr r3, [r7, #8]
8006c84: f003 0301 and.w r3, r3, #1
8006c88: 2b00 cmp r3, #0
8006c8a: d016 beq.n 8006cba <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
8006c8c: 687b ldr r3, [r7, #4]
8006c8e: 681b ldr r3, [r3, #0]
8006c90: 6b5a ldr r2, [r3, #52] ; 0x34
8006c92: 687b ldr r3, [r7, #4]
8006c94: 681b ldr r3, [r3, #0]
8006c96: f022 0201 bic.w r2, r2, #1
8006c9a: 635a str r2, [r3, #52] ; 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
8006c9c: 687b ldr r3, [r7, #4]
8006c9e: 681b ldr r3, [r3, #0]
8006ca0: 2201 movs r2, #1
8006ca2: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8006ca4: 687b ldr r3, [r7, #4]
8006ca6: 2201 movs r2, #1
8006ca8: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8006cac: 687b ldr r3, [r7, #4]
8006cae: 2200 movs r2, #0
8006cb0: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
8006cb4: 6878 ldr r0, [r7, #4]
8006cb6: f000 f82f bl 8006d18 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
8006cba: 68fb ldr r3, [r7, #12]
8006cbc: f003 0308 and.w r3, r3, #8
8006cc0: 2b00 cmp r3, #0
8006cc2: d01b beq.n 8006cfc <HAL_LTDC_IRQHandler+0x140>
8006cc4: 68bb ldr r3, [r7, #8]
8006cc6: f003 0308 and.w r3, r3, #8
8006cca: 2b00 cmp r3, #0
8006ccc: d016 beq.n 8006cfc <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
8006cce: 687b ldr r3, [r7, #4]
8006cd0: 681b ldr r3, [r3, #0]
8006cd2: 6b5a ldr r2, [r3, #52] ; 0x34
8006cd4: 687b ldr r3, [r7, #4]
8006cd6: 681b ldr r3, [r3, #0]
8006cd8: f022 0208 bic.w r2, r2, #8
8006cdc: 635a str r2, [r3, #52] ; 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
8006cde: 687b ldr r3, [r7, #4]
8006ce0: 681b ldr r3, [r3, #0]
8006ce2: 2208 movs r2, #8
8006ce4: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8006ce6: 687b ldr r3, [r7, #4]
8006ce8: 2201 movs r2, #1
8006cea: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8006cee: 687b ldr r3, [r7, #4]
8006cf0: 2200 movs r2, #0
8006cf2: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
8006cf6: 6878 ldr r0, [r7, #4]
8006cf8: f000 f818 bl 8006d2c <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
8006cfc: bf00 nop
8006cfe: 3710 adds r7, #16
8006d00: 46bd mov sp, r7
8006d02: bd80 pop {r7, pc}
08006d04 <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
8006d04: b480 push {r7}
8006d06: b083 sub sp, #12
8006d08: af00 add r7, sp, #0
8006d0a: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
8006d0c: bf00 nop
8006d0e: 370c adds r7, #12
8006d10: 46bd mov sp, r7
8006d12: f85d 7b04 ldr.w r7, [sp], #4
8006d16: 4770 bx lr
08006d18 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
8006d18: b480 push {r7}
8006d1a: b083 sub sp, #12
8006d1c: af00 add r7, sp, #0
8006d1e: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
8006d20: bf00 nop
8006d22: 370c adds r7, #12
8006d24: 46bd mov sp, r7
8006d26: f85d 7b04 ldr.w r7, [sp], #4
8006d2a: 4770 bx lr
08006d2c <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
8006d2c: b480 push {r7}
8006d2e: b083 sub sp, #12
8006d30: af00 add r7, sp, #0
8006d32: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
8006d34: bf00 nop
8006d36: 370c adds r7, #12
8006d38: 46bd mov sp, r7
8006d3a: f85d 7b04 ldr.w r7, [sp], #4
8006d3e: 4770 bx lr
08006d40 <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8006d40: b5b0 push {r4, r5, r7, lr}
8006d42: b084 sub sp, #16
8006d44: af00 add r7, sp, #0
8006d46: 60f8 str r0, [r7, #12]
8006d48: 60b9 str r1, [r7, #8]
8006d4a: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
8006d4c: 68fb ldr r3, [r7, #12]
8006d4e: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
8006d52: 2b01 cmp r3, #1
8006d54: d101 bne.n 8006d5a <HAL_LTDC_ConfigLayer+0x1a>
8006d56: 2302 movs r3, #2
8006d58: e02c b.n 8006db4 <HAL_LTDC_ConfigLayer+0x74>
8006d5a: 68fb ldr r3, [r7, #12]
8006d5c: 2201 movs r2, #1
8006d5e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8006d62: 68fb ldr r3, [r7, #12]
8006d64: 2202 movs r2, #2
8006d66: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
8006d6a: 68fa ldr r2, [r7, #12]
8006d6c: 687b ldr r3, [r7, #4]
8006d6e: 2134 movs r1, #52 ; 0x34
8006d70: fb01 f303 mul.w r3, r1, r3
8006d74: 4413 add r3, r2
8006d76: f103 0238 add.w r2, r3, #56 ; 0x38
8006d7a: 68bb ldr r3, [r7, #8]
8006d7c: 4614 mov r4, r2
8006d7e: 461d mov r5, r3
8006d80: cd0f ldmia r5!, {r0, r1, r2, r3}
8006d82: c40f stmia r4!, {r0, r1, r2, r3}
8006d84: cd0f ldmia r5!, {r0, r1, r2, r3}
8006d86: c40f stmia r4!, {r0, r1, r2, r3}
8006d88: cd0f ldmia r5!, {r0, r1, r2, r3}
8006d8a: c40f stmia r4!, {r0, r1, r2, r3}
8006d8c: 682b ldr r3, [r5, #0]
8006d8e: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
8006d90: 687a ldr r2, [r7, #4]
8006d92: 68b9 ldr r1, [r7, #8]
8006d94: 68f8 ldr r0, [r7, #12]
8006d96: f000 f81f bl 8006dd8 <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
8006d9a: 68fb ldr r3, [r7, #12]
8006d9c: 681b ldr r3, [r3, #0]
8006d9e: 2201 movs r2, #1
8006da0: 625a str r2, [r3, #36] ; 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8006da2: 68fb ldr r3, [r7, #12]
8006da4: 2201 movs r2, #1
8006da6: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8006daa: 68fb ldr r3, [r7, #12]
8006dac: 2200 movs r2, #0
8006dae: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
return HAL_OK;
8006db2: 2300 movs r3, #0
}
8006db4: 4618 mov r0, r3
8006db6: 3710 adds r7, #16
8006db8: 46bd mov sp, r7
8006dba: bdb0 pop {r4, r5, r7, pc}
08006dbc <HAL_LTDC_GetState>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc)
{
8006dbc: b480 push {r7}
8006dbe: b083 sub sp, #12
8006dc0: af00 add r7, sp, #0
8006dc2: 6078 str r0, [r7, #4]
return hltdc->State;
8006dc4: 687b ldr r3, [r7, #4]
8006dc6: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8006dca: b2db uxtb r3, r3
}
8006dcc: 4618 mov r0, r3
8006dce: 370c adds r7, #12
8006dd0: 46bd mov sp, r7
8006dd2: f85d 7b04 ldr.w r7, [sp], #4
8006dd6: 4770 bx lr
08006dd8 <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8006dd8: b480 push {r7}
8006dda: b089 sub sp, #36 ; 0x24
8006ddc: af00 add r7, sp, #0
8006dde: 60f8 str r0, [r7, #12]
8006de0: 60b9 str r1, [r7, #8]
8006de2: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
8006de4: 68bb ldr r3, [r7, #8]
8006de6: 685a ldr r2, [r3, #4]
8006de8: 68fb ldr r3, [r7, #12]
8006dea: 681b ldr r3, [r3, #0]
8006dec: 68db ldr r3, [r3, #12]
8006dee: 0c1b lsrs r3, r3, #16
8006df0: f3c3 030b ubfx r3, r3, #0, #12
8006df4: 4413 add r3, r2
8006df6: 041b lsls r3, r3, #16
8006df8: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
8006dfa: 68fb ldr r3, [r7, #12]
8006dfc: 681b ldr r3, [r3, #0]
8006dfe: 461a mov r2, r3
8006e00: 687b ldr r3, [r7, #4]
8006e02: 01db lsls r3, r3, #7
8006e04: 4413 add r3, r2
8006e06: 3384 adds r3, #132 ; 0x84
8006e08: 685b ldr r3, [r3, #4]
8006e0a: 68fa ldr r2, [r7, #12]
8006e0c: 6812 ldr r2, [r2, #0]
8006e0e: 4611 mov r1, r2
8006e10: 687a ldr r2, [r7, #4]
8006e12: 01d2 lsls r2, r2, #7
8006e14: 440a add r2, r1
8006e16: 3284 adds r2, #132 ; 0x84
8006e18: f403 4370 and.w r3, r3, #61440 ; 0xf000
8006e1c: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
8006e1e: 68bb ldr r3, [r7, #8]
8006e20: 681a ldr r2, [r3, #0]
8006e22: 68fb ldr r3, [r7, #12]
8006e24: 681b ldr r3, [r3, #0]
8006e26: 68db ldr r3, [r3, #12]
8006e28: 0c1b lsrs r3, r3, #16
8006e2a: f3c3 030b ubfx r3, r3, #0, #12
8006e2e: 4413 add r3, r2
8006e30: 1c5a adds r2, r3, #1
8006e32: 68fb ldr r3, [r7, #12]
8006e34: 681b ldr r3, [r3, #0]
8006e36: 4619 mov r1, r3
8006e38: 687b ldr r3, [r7, #4]
8006e3a: 01db lsls r3, r3, #7
8006e3c: 440b add r3, r1
8006e3e: 3384 adds r3, #132 ; 0x84
8006e40: 4619 mov r1, r3
8006e42: 69fb ldr r3, [r7, #28]
8006e44: 4313 orrs r3, r2
8006e46: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
8006e48: 68bb ldr r3, [r7, #8]
8006e4a: 68da ldr r2, [r3, #12]
8006e4c: 68fb ldr r3, [r7, #12]
8006e4e: 681b ldr r3, [r3, #0]
8006e50: 68db ldr r3, [r3, #12]
8006e52: f3c3 030a ubfx r3, r3, #0, #11
8006e56: 4413 add r3, r2
8006e58: 041b lsls r3, r3, #16
8006e5a: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
8006e5c: 68fb ldr r3, [r7, #12]
8006e5e: 681b ldr r3, [r3, #0]
8006e60: 461a mov r2, r3
8006e62: 687b ldr r3, [r7, #4]
8006e64: 01db lsls r3, r3, #7
8006e66: 4413 add r3, r2
8006e68: 3384 adds r3, #132 ; 0x84
8006e6a: 689b ldr r3, [r3, #8]
8006e6c: 68fa ldr r2, [r7, #12]
8006e6e: 6812 ldr r2, [r2, #0]
8006e70: 4611 mov r1, r2
8006e72: 687a ldr r2, [r7, #4]
8006e74: 01d2 lsls r2, r2, #7
8006e76: 440a add r2, r1
8006e78: 3284 adds r2, #132 ; 0x84
8006e7a: f403 4370 and.w r3, r3, #61440 ; 0xf000
8006e7e: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
8006e80: 68bb ldr r3, [r7, #8]
8006e82: 689a ldr r2, [r3, #8]
8006e84: 68fb ldr r3, [r7, #12]
8006e86: 681b ldr r3, [r3, #0]
8006e88: 68db ldr r3, [r3, #12]
8006e8a: f3c3 030a ubfx r3, r3, #0, #11
8006e8e: 4413 add r3, r2
8006e90: 1c5a adds r2, r3, #1
8006e92: 68fb ldr r3, [r7, #12]
8006e94: 681b ldr r3, [r3, #0]
8006e96: 4619 mov r1, r3
8006e98: 687b ldr r3, [r7, #4]
8006e9a: 01db lsls r3, r3, #7
8006e9c: 440b add r3, r1
8006e9e: 3384 adds r3, #132 ; 0x84
8006ea0: 4619 mov r1, r3
8006ea2: 69fb ldr r3, [r7, #28]
8006ea4: 4313 orrs r3, r2
8006ea6: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
8006ea8: 68fb ldr r3, [r7, #12]
8006eaa: 681b ldr r3, [r3, #0]
8006eac: 461a mov r2, r3
8006eae: 687b ldr r3, [r7, #4]
8006eb0: 01db lsls r3, r3, #7
8006eb2: 4413 add r3, r2
8006eb4: 3384 adds r3, #132 ; 0x84
8006eb6: 691b ldr r3, [r3, #16]
8006eb8: 68fa ldr r2, [r7, #12]
8006eba: 6812 ldr r2, [r2, #0]
8006ebc: 4611 mov r1, r2
8006ebe: 687a ldr r2, [r7, #4]
8006ec0: 01d2 lsls r2, r2, #7
8006ec2: 440a add r2, r1
8006ec4: 3284 adds r2, #132 ; 0x84
8006ec6: f023 0307 bic.w r3, r3, #7
8006eca: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
8006ecc: 68fb ldr r3, [r7, #12]
8006ece: 681b ldr r3, [r3, #0]
8006ed0: 461a mov r2, r3
8006ed2: 687b ldr r3, [r7, #4]
8006ed4: 01db lsls r3, r3, #7
8006ed6: 4413 add r3, r2
8006ed8: 3384 adds r3, #132 ; 0x84
8006eda: 461a mov r2, r3
8006edc: 68bb ldr r3, [r7, #8]
8006ede: 691b ldr r3, [r3, #16]
8006ee0: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
8006ee2: 68bb ldr r3, [r7, #8]
8006ee4: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
8006ee8: 021b lsls r3, r3, #8
8006eea: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
8006eec: 68bb ldr r3, [r7, #8]
8006eee: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
8006ef2: 041b lsls r3, r3, #16
8006ef4: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
8006ef6: 68bb ldr r3, [r7, #8]
8006ef8: 699b ldr r3, [r3, #24]
8006efa: 061b lsls r3, r3, #24
8006efc: 617b str r3, [r7, #20]
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
8006efe: 68fb ldr r3, [r7, #12]
8006f00: 681b ldr r3, [r3, #0]
8006f02: 461a mov r2, r3
8006f04: 687b ldr r3, [r7, #4]
8006f06: 01db lsls r3, r3, #7
8006f08: 4413 add r3, r2
8006f0a: 3384 adds r3, #132 ; 0x84
8006f0c: 699b ldr r3, [r3, #24]
8006f0e: 68fb ldr r3, [r7, #12]
8006f10: 681b ldr r3, [r3, #0]
8006f12: 461a mov r2, r3
8006f14: 687b ldr r3, [r7, #4]
8006f16: 01db lsls r3, r3, #7
8006f18: 4413 add r3, r2
8006f1a: 3384 adds r3, #132 ; 0x84
8006f1c: 461a mov r2, r3
8006f1e: 2300 movs r3, #0
8006f20: 6193 str r3, [r2, #24]
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
8006f22: 68bb ldr r3, [r7, #8]
8006f24: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
8006f28: 461a mov r2, r3
8006f2a: 69fb ldr r3, [r7, #28]
8006f2c: 431a orrs r2, r3
8006f2e: 69bb ldr r3, [r7, #24]
8006f30: 431a orrs r2, r3
8006f32: 68fb ldr r3, [r7, #12]
8006f34: 681b ldr r3, [r3, #0]
8006f36: 4619 mov r1, r3
8006f38: 687b ldr r3, [r7, #4]
8006f3a: 01db lsls r3, r3, #7
8006f3c: 440b add r3, r1
8006f3e: 3384 adds r3, #132 ; 0x84
8006f40: 4619 mov r1, r3
8006f42: 697b ldr r3, [r7, #20]
8006f44: 4313 orrs r3, r2
8006f46: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
8006f48: 68fb ldr r3, [r7, #12]
8006f4a: 681b ldr r3, [r3, #0]
8006f4c: 461a mov r2, r3
8006f4e: 687b ldr r3, [r7, #4]
8006f50: 01db lsls r3, r3, #7
8006f52: 4413 add r3, r2
8006f54: 3384 adds r3, #132 ; 0x84
8006f56: 695b ldr r3, [r3, #20]
8006f58: 68fa ldr r2, [r7, #12]
8006f5a: 6812 ldr r2, [r2, #0]
8006f5c: 4611 mov r1, r2
8006f5e: 687a ldr r2, [r7, #4]
8006f60: 01d2 lsls r2, r2, #7
8006f62: 440a add r2, r1
8006f64: 3284 adds r2, #132 ; 0x84
8006f66: f023 03ff bic.w r3, r3, #255 ; 0xff
8006f6a: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
8006f6c: 68fb ldr r3, [r7, #12]
8006f6e: 681b ldr r3, [r3, #0]
8006f70: 461a mov r2, r3
8006f72: 687b ldr r3, [r7, #4]
8006f74: 01db lsls r3, r3, #7
8006f76: 4413 add r3, r2
8006f78: 3384 adds r3, #132 ; 0x84
8006f7a: 461a mov r2, r3
8006f7c: 68bb ldr r3, [r7, #8]
8006f7e: 695b ldr r3, [r3, #20]
8006f80: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
8006f82: 68fb ldr r3, [r7, #12]
8006f84: 681b ldr r3, [r3, #0]
8006f86: 461a mov r2, r3
8006f88: 687b ldr r3, [r7, #4]
8006f8a: 01db lsls r3, r3, #7
8006f8c: 4413 add r3, r2
8006f8e: 3384 adds r3, #132 ; 0x84
8006f90: 69da ldr r2, [r3, #28]
8006f92: 68fb ldr r3, [r7, #12]
8006f94: 681b ldr r3, [r3, #0]
8006f96: 4619 mov r1, r3
8006f98: 687b ldr r3, [r7, #4]
8006f9a: 01db lsls r3, r3, #7
8006f9c: 440b add r3, r1
8006f9e: 3384 adds r3, #132 ; 0x84
8006fa0: 4619 mov r1, r3
8006fa2: 4b58 ldr r3, [pc, #352] ; (8007104 <LTDC_SetConfig+0x32c>)
8006fa4: 4013 ands r3, r2
8006fa6: 61cb str r3, [r1, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
8006fa8: 68bb ldr r3, [r7, #8]
8006faa: 69da ldr r2, [r3, #28]
8006fac: 68bb ldr r3, [r7, #8]
8006fae: 6a1b ldr r3, [r3, #32]
8006fb0: 68f9 ldr r1, [r7, #12]
8006fb2: 6809 ldr r1, [r1, #0]
8006fb4: 4608 mov r0, r1
8006fb6: 6879 ldr r1, [r7, #4]
8006fb8: 01c9 lsls r1, r1, #7
8006fba: 4401 add r1, r0
8006fbc: 3184 adds r1, #132 ; 0x84
8006fbe: 4313 orrs r3, r2
8006fc0: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
8006fc2: 68fb ldr r3, [r7, #12]
8006fc4: 681b ldr r3, [r3, #0]
8006fc6: 461a mov r2, r3
8006fc8: 687b ldr r3, [r7, #4]
8006fca: 01db lsls r3, r3, #7
8006fcc: 4413 add r3, r2
8006fce: 3384 adds r3, #132 ; 0x84
8006fd0: 6a9b ldr r3, [r3, #40] ; 0x28
8006fd2: 68fb ldr r3, [r7, #12]
8006fd4: 681b ldr r3, [r3, #0]
8006fd6: 461a mov r2, r3
8006fd8: 687b ldr r3, [r7, #4]
8006fda: 01db lsls r3, r3, #7
8006fdc: 4413 add r3, r2
8006fde: 3384 adds r3, #132 ; 0x84
8006fe0: 461a mov r2, r3
8006fe2: 2300 movs r3, #0
8006fe4: 6293 str r3, [r2, #40] ; 0x28
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
8006fe6: 68fb ldr r3, [r7, #12]
8006fe8: 681b ldr r3, [r3, #0]
8006fea: 461a mov r2, r3
8006fec: 687b ldr r3, [r7, #4]
8006fee: 01db lsls r3, r3, #7
8006ff0: 4413 add r3, r2
8006ff2: 3384 adds r3, #132 ; 0x84
8006ff4: 461a mov r2, r3
8006ff6: 68bb ldr r3, [r7, #8]
8006ff8: 6a5b ldr r3, [r3, #36] ; 0x24
8006ffa: 6293 str r3, [r2, #40] ; 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
8006ffc: 68bb ldr r3, [r7, #8]
8006ffe: 691b ldr r3, [r3, #16]
8007000: 2b00 cmp r3, #0
8007002: d102 bne.n 800700a <LTDC_SetConfig+0x232>
{
tmp = 4U;
8007004: 2304 movs r3, #4
8007006: 61fb str r3, [r7, #28]
8007008: e01b b.n 8007042 <LTDC_SetConfig+0x26a>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
800700a: 68bb ldr r3, [r7, #8]
800700c: 691b ldr r3, [r3, #16]
800700e: 2b01 cmp r3, #1
8007010: d102 bne.n 8007018 <LTDC_SetConfig+0x240>
{
tmp = 3U;
8007012: 2303 movs r3, #3
8007014: 61fb str r3, [r7, #28]
8007016: e014 b.n 8007042 <LTDC_SetConfig+0x26a>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
8007018: 68bb ldr r3, [r7, #8]
800701a: 691b ldr r3, [r3, #16]
800701c: 2b04 cmp r3, #4
800701e: d00b beq.n 8007038 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
8007020: 68bb ldr r3, [r7, #8]
8007022: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
8007024: 2b02 cmp r3, #2
8007026: d007 beq.n 8007038 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
8007028: 68bb ldr r3, [r7, #8]
800702a: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
800702c: 2b03 cmp r3, #3
800702e: d003 beq.n 8007038 <LTDC_SetConfig+0x260>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
8007030: 68bb ldr r3, [r7, #8]
8007032: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
8007034: 2b07 cmp r3, #7
8007036: d102 bne.n 800703e <LTDC_SetConfig+0x266>
{
tmp = 2U;
8007038: 2302 movs r3, #2
800703a: 61fb str r3, [r7, #28]
800703c: e001 b.n 8007042 <LTDC_SetConfig+0x26a>
}
else
{
tmp = 1U;
800703e: 2301 movs r3, #1
8007040: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
8007042: 68fb ldr r3, [r7, #12]
8007044: 681b ldr r3, [r3, #0]
8007046: 461a mov r2, r3
8007048: 687b ldr r3, [r7, #4]
800704a: 01db lsls r3, r3, #7
800704c: 4413 add r3, r2
800704e: 3384 adds r3, #132 ; 0x84
8007050: 6adb ldr r3, [r3, #44] ; 0x2c
8007052: 68fa ldr r2, [r7, #12]
8007054: 6812 ldr r2, [r2, #0]
8007056: 4611 mov r1, r2
8007058: 687a ldr r2, [r7, #4]
800705a: 01d2 lsls r2, r2, #7
800705c: 440a add r2, r1
800705e: 3284 adds r2, #132 ; 0x84
8007060: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
8007064: 62d3 str r3, [r2, #44] ; 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
8007066: 68bb ldr r3, [r7, #8]
8007068: 6a9b ldr r3, [r3, #40] ; 0x28
800706a: 69fa ldr r2, [r7, #28]
800706c: fb02 f303 mul.w r3, r2, r3
8007070: 041a lsls r2, r3, #16
8007072: 68bb ldr r3, [r7, #8]
8007074: 6859 ldr r1, [r3, #4]
8007076: 68bb ldr r3, [r7, #8]
8007078: 681b ldr r3, [r3, #0]
800707a: 1acb subs r3, r1, r3
800707c: 69f9 ldr r1, [r7, #28]
800707e: fb01 f303 mul.w r3, r1, r3
8007082: 3303 adds r3, #3
8007084: 68f9 ldr r1, [r7, #12]
8007086: 6809 ldr r1, [r1, #0]
8007088: 4608 mov r0, r1
800708a: 6879 ldr r1, [r7, #4]
800708c: 01c9 lsls r1, r1, #7
800708e: 4401 add r1, r0
8007090: 3184 adds r1, #132 ; 0x84
8007092: 4313 orrs r3, r2
8007094: 62cb str r3, [r1, #44] ; 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
8007096: 68fb ldr r3, [r7, #12]
8007098: 681b ldr r3, [r3, #0]
800709a: 461a mov r2, r3
800709c: 687b ldr r3, [r7, #4]
800709e: 01db lsls r3, r3, #7
80070a0: 4413 add r3, r2
80070a2: 3384 adds r3, #132 ; 0x84
80070a4: 6b1a ldr r2, [r3, #48] ; 0x30
80070a6: 68fb ldr r3, [r7, #12]
80070a8: 681b ldr r3, [r3, #0]
80070aa: 4619 mov r1, r3
80070ac: 687b ldr r3, [r7, #4]
80070ae: 01db lsls r3, r3, #7
80070b0: 440b add r3, r1
80070b2: 3384 adds r3, #132 ; 0x84
80070b4: 4619 mov r1, r3
80070b6: 4b14 ldr r3, [pc, #80] ; (8007108 <LTDC_SetConfig+0x330>)
80070b8: 4013 ands r3, r2
80070ba: 630b str r3, [r1, #48] ; 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
80070bc: 68fb ldr r3, [r7, #12]
80070be: 681b ldr r3, [r3, #0]
80070c0: 461a mov r2, r3
80070c2: 687b ldr r3, [r7, #4]
80070c4: 01db lsls r3, r3, #7
80070c6: 4413 add r3, r2
80070c8: 3384 adds r3, #132 ; 0x84
80070ca: 461a mov r2, r3
80070cc: 68bb ldr r3, [r7, #8]
80070ce: 6adb ldr r3, [r3, #44] ; 0x2c
80070d0: 6313 str r3, [r2, #48] ; 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
80070d2: 68fb ldr r3, [r7, #12]
80070d4: 681b ldr r3, [r3, #0]
80070d6: 461a mov r2, r3
80070d8: 687b ldr r3, [r7, #4]
80070da: 01db lsls r3, r3, #7
80070dc: 4413 add r3, r2
80070de: 3384 adds r3, #132 ; 0x84
80070e0: 681b ldr r3, [r3, #0]
80070e2: 68fa ldr r2, [r7, #12]
80070e4: 6812 ldr r2, [r2, #0]
80070e6: 4611 mov r1, r2
80070e8: 687a ldr r2, [r7, #4]
80070ea: 01d2 lsls r2, r2, #7
80070ec: 440a add r2, r1
80070ee: 3284 adds r2, #132 ; 0x84
80070f0: f043 0301 orr.w r3, r3, #1
80070f4: 6013 str r3, [r2, #0]
}
80070f6: bf00 nop
80070f8: 3724 adds r7, #36 ; 0x24
80070fa: 46bd mov sp, r7
80070fc: f85d 7b04 ldr.w r7, [sp], #4
8007100: 4770 bx lr
8007102: bf00 nop
8007104: fffff8f8 .word 0xfffff8f8
8007108: fffff800 .word 0xfffff800
0800710c <HAL_PWR_EnableBkUpAccess>:
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
800710c: b480 push {r7}
800710e: af00 add r7, sp, #0
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8007110: 4b05 ldr r3, [pc, #20] ; (8007128 <HAL_PWR_EnableBkUpAccess+0x1c>)
8007112: 681b ldr r3, [r3, #0]
8007114: 4a04 ldr r2, [pc, #16] ; (8007128 <HAL_PWR_EnableBkUpAccess+0x1c>)
8007116: f443 7380 orr.w r3, r3, #256 ; 0x100
800711a: 6013 str r3, [r2, #0]
}
800711c: bf00 nop
800711e: 46bd mov sp, r7
8007120: f85d 7b04 ldr.w r7, [sp], #4
8007124: 4770 bx lr
8007126: bf00 nop
8007128: 40007000 .word 0x40007000
0800712c <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
800712c: b580 push {r7, lr}
800712e: b082 sub sp, #8
8007130: af00 add r7, sp, #0
uint32_t tickstart = 0;
8007132: 2300 movs r3, #0
8007134: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8007136: 4b23 ldr r3, [pc, #140] ; (80071c4 <HAL_PWREx_EnableOverDrive+0x98>)
8007138: 6c1b ldr r3, [r3, #64] ; 0x40
800713a: 4a22 ldr r2, [pc, #136] ; (80071c4 <HAL_PWREx_EnableOverDrive+0x98>)
800713c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8007140: 6413 str r3, [r2, #64] ; 0x40
8007142: 4b20 ldr r3, [pc, #128] ; (80071c4 <HAL_PWREx_EnableOverDrive+0x98>)
8007144: 6c1b ldr r3, [r3, #64] ; 0x40
8007146: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800714a: 603b str r3, [r7, #0]
800714c: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
800714e: 4b1e ldr r3, [pc, #120] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
8007150: 681b ldr r3, [r3, #0]
8007152: 4a1d ldr r2, [pc, #116] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
8007154: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8007158: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
800715a: f7fd f9c9 bl 80044f0 <HAL_GetTick>
800715e: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8007160: e009 b.n 8007176 <HAL_PWREx_EnableOverDrive+0x4a>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8007162: f7fd f9c5 bl 80044f0 <HAL_GetTick>
8007166: 4602 mov r2, r0
8007168: 687b ldr r3, [r7, #4]
800716a: 1ad3 subs r3, r2, r3
800716c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8007170: d901 bls.n 8007176 <HAL_PWREx_EnableOverDrive+0x4a>
{
return HAL_TIMEOUT;
8007172: 2303 movs r3, #3
8007174: e022 b.n 80071bc <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8007176: 4b14 ldr r3, [pc, #80] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
8007178: 685b ldr r3, [r3, #4]
800717a: f403 3380 and.w r3, r3, #65536 ; 0x10000
800717e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8007182: d1ee bne.n 8007162 <HAL_PWREx_EnableOverDrive+0x36>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8007184: 4b10 ldr r3, [pc, #64] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
8007186: 681b ldr r3, [r3, #0]
8007188: 4a0f ldr r2, [pc, #60] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
800718a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800718e: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8007190: f7fd f9ae bl 80044f0 <HAL_GetTick>
8007194: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8007196: e009 b.n 80071ac <HAL_PWREx_EnableOverDrive+0x80>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8007198: f7fd f9aa bl 80044f0 <HAL_GetTick>
800719c: 4602 mov r2, r0
800719e: 687b ldr r3, [r7, #4]
80071a0: 1ad3 subs r3, r2, r3
80071a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
80071a6: d901 bls.n 80071ac <HAL_PWREx_EnableOverDrive+0x80>
{
return HAL_TIMEOUT;
80071a8: 2303 movs r3, #3
80071aa: e007 b.n 80071bc <HAL_PWREx_EnableOverDrive+0x90>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
80071ac: 4b06 ldr r3, [pc, #24] ; (80071c8 <HAL_PWREx_EnableOverDrive+0x9c>)
80071ae: 685b ldr r3, [r3, #4]
80071b0: f403 3300 and.w r3, r3, #131072 ; 0x20000
80071b4: f5b3 3f00 cmp.w r3, #131072 ; 0x20000
80071b8: d1ee bne.n 8007198 <HAL_PWREx_EnableOverDrive+0x6c>
}
}
return HAL_OK;
80071ba: 2300 movs r3, #0
}
80071bc: 4618 mov r0, r3
80071be: 3708 adds r7, #8
80071c0: 46bd mov sp, r7
80071c2: bd80 pop {r7, pc}
80071c4: 40023800 .word 0x40023800
80071c8: 40007000 .word 0x40007000
080071cc <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80071cc: b580 push {r7, lr}
80071ce: b086 sub sp, #24
80071d0: af00 add r7, sp, #0
80071d2: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
FlagStatus pwrclkchanged = RESET;
80071d4: 2300 movs r3, #0
80071d6: 75fb strb r3, [r7, #23]
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80071d8: 687b ldr r3, [r7, #4]
80071da: 2b00 cmp r3, #0
80071dc: d101 bne.n 80071e2 <HAL_RCC_OscConfig+0x16>
{
return HAL_ERROR;
80071de: 2301 movs r3, #1
80071e0: e291 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80071e2: 687b ldr r3, [r7, #4]
80071e4: 681b ldr r3, [r3, #0]
80071e6: f003 0301 and.w r3, r3, #1
80071ea: 2b00 cmp r3, #0
80071ec: f000 8087 beq.w 80072fe <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
80071f0: 4b96 ldr r3, [pc, #600] ; (800744c <HAL_RCC_OscConfig+0x280>)
80071f2: 689b ldr r3, [r3, #8]
80071f4: f003 030c and.w r3, r3, #12
80071f8: 2b04 cmp r3, #4
80071fa: d00c beq.n 8007216 <HAL_RCC_OscConfig+0x4a>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80071fc: 4b93 ldr r3, [pc, #588] ; (800744c <HAL_RCC_OscConfig+0x280>)
80071fe: 689b ldr r3, [r3, #8]
8007200: f003 030c and.w r3, r3, #12
8007204: 2b08 cmp r3, #8
8007206: d112 bne.n 800722e <HAL_RCC_OscConfig+0x62>
8007208: 4b90 ldr r3, [pc, #576] ; (800744c <HAL_RCC_OscConfig+0x280>)
800720a: 685b ldr r3, [r3, #4]
800720c: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8007210: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8007214: d10b bne.n 800722e <HAL_RCC_OscConfig+0x62>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8007216: 4b8d ldr r3, [pc, #564] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007218: 681b ldr r3, [r3, #0]
800721a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800721e: 2b00 cmp r3, #0
8007220: d06c beq.n 80072fc <HAL_RCC_OscConfig+0x130>
8007222: 687b ldr r3, [r7, #4]
8007224: 685b ldr r3, [r3, #4]
8007226: 2b00 cmp r3, #0
8007228: d168 bne.n 80072fc <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
800722a: 2301 movs r3, #1
800722c: e26b b.n 8007706 <HAL_RCC_OscConfig+0x53a>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800722e: 687b ldr r3, [r7, #4]
8007230: 685b ldr r3, [r3, #4]
8007232: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8007236: d106 bne.n 8007246 <HAL_RCC_OscConfig+0x7a>
8007238: 4b84 ldr r3, [pc, #528] ; (800744c <HAL_RCC_OscConfig+0x280>)
800723a: 681b ldr r3, [r3, #0]
800723c: 4a83 ldr r2, [pc, #524] ; (800744c <HAL_RCC_OscConfig+0x280>)
800723e: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8007242: 6013 str r3, [r2, #0]
8007244: e02e b.n 80072a4 <HAL_RCC_OscConfig+0xd8>
8007246: 687b ldr r3, [r7, #4]
8007248: 685b ldr r3, [r3, #4]
800724a: 2b00 cmp r3, #0
800724c: d10c bne.n 8007268 <HAL_RCC_OscConfig+0x9c>
800724e: 4b7f ldr r3, [pc, #508] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007250: 681b ldr r3, [r3, #0]
8007252: 4a7e ldr r2, [pc, #504] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007254: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8007258: 6013 str r3, [r2, #0]
800725a: 4b7c ldr r3, [pc, #496] ; (800744c <HAL_RCC_OscConfig+0x280>)
800725c: 681b ldr r3, [r3, #0]
800725e: 4a7b ldr r2, [pc, #492] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007260: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8007264: 6013 str r3, [r2, #0]
8007266: e01d b.n 80072a4 <HAL_RCC_OscConfig+0xd8>
8007268: 687b ldr r3, [r7, #4]
800726a: 685b ldr r3, [r3, #4]
800726c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8007270: d10c bne.n 800728c <HAL_RCC_OscConfig+0xc0>
8007272: 4b76 ldr r3, [pc, #472] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007274: 681b ldr r3, [r3, #0]
8007276: 4a75 ldr r2, [pc, #468] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007278: f443 2380 orr.w r3, r3, #262144 ; 0x40000
800727c: 6013 str r3, [r2, #0]
800727e: 4b73 ldr r3, [pc, #460] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007280: 681b ldr r3, [r3, #0]
8007282: 4a72 ldr r2, [pc, #456] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007284: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8007288: 6013 str r3, [r2, #0]
800728a: e00b b.n 80072a4 <HAL_RCC_OscConfig+0xd8>
800728c: 4b6f ldr r3, [pc, #444] ; (800744c <HAL_RCC_OscConfig+0x280>)
800728e: 681b ldr r3, [r3, #0]
8007290: 4a6e ldr r2, [pc, #440] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007292: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8007296: 6013 str r3, [r2, #0]
8007298: 4b6c ldr r3, [pc, #432] ; (800744c <HAL_RCC_OscConfig+0x280>)
800729a: 681b ldr r3, [r3, #0]
800729c: 4a6b ldr r2, [pc, #428] ; (800744c <HAL_RCC_OscConfig+0x280>)
800729e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
80072a2: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80072a4: 687b ldr r3, [r7, #4]
80072a6: 685b ldr r3, [r3, #4]
80072a8: 2b00 cmp r3, #0
80072aa: d013 beq.n 80072d4 <HAL_RCC_OscConfig+0x108>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80072ac: f7fd f920 bl 80044f0 <HAL_GetTick>
80072b0: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80072b2: e008 b.n 80072c6 <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80072b4: f7fd f91c bl 80044f0 <HAL_GetTick>
80072b8: 4602 mov r2, r0
80072ba: 693b ldr r3, [r7, #16]
80072bc: 1ad3 subs r3, r2, r3
80072be: 2b64 cmp r3, #100 ; 0x64
80072c0: d901 bls.n 80072c6 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80072c2: 2303 movs r3, #3
80072c4: e21f b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80072c6: 4b61 ldr r3, [pc, #388] ; (800744c <HAL_RCC_OscConfig+0x280>)
80072c8: 681b ldr r3, [r3, #0]
80072ca: f403 3300 and.w r3, r3, #131072 ; 0x20000
80072ce: 2b00 cmp r3, #0
80072d0: d0f0 beq.n 80072b4 <HAL_RCC_OscConfig+0xe8>
80072d2: e014 b.n 80072fe <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80072d4: f7fd f90c bl 80044f0 <HAL_GetTick>
80072d8: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80072da: e008 b.n 80072ee <HAL_RCC_OscConfig+0x122>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80072dc: f7fd f908 bl 80044f0 <HAL_GetTick>
80072e0: 4602 mov r2, r0
80072e2: 693b ldr r3, [r7, #16]
80072e4: 1ad3 subs r3, r2, r3
80072e6: 2b64 cmp r3, #100 ; 0x64
80072e8: d901 bls.n 80072ee <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
80072ea: 2303 movs r3, #3
80072ec: e20b b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80072ee: 4b57 ldr r3, [pc, #348] ; (800744c <HAL_RCC_OscConfig+0x280>)
80072f0: 681b ldr r3, [r3, #0]
80072f2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80072f6: 2b00 cmp r3, #0
80072f8: d1f0 bne.n 80072dc <HAL_RCC_OscConfig+0x110>
80072fa: e000 b.n 80072fe <HAL_RCC_OscConfig+0x132>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80072fc: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80072fe: 687b ldr r3, [r7, #4]
8007300: 681b ldr r3, [r3, #0]
8007302: f003 0302 and.w r3, r3, #2
8007306: 2b00 cmp r3, #0
8007308: d069 beq.n 80073de <HAL_RCC_OscConfig+0x212>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
800730a: 4b50 ldr r3, [pc, #320] ; (800744c <HAL_RCC_OscConfig+0x280>)
800730c: 689b ldr r3, [r3, #8]
800730e: f003 030c and.w r3, r3, #12
8007312: 2b00 cmp r3, #0
8007314: d00b beq.n 800732e <HAL_RCC_OscConfig+0x162>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8007316: 4b4d ldr r3, [pc, #308] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007318: 689b ldr r3, [r3, #8]
800731a: f003 030c and.w r3, r3, #12
800731e: 2b08 cmp r3, #8
8007320: d11c bne.n 800735c <HAL_RCC_OscConfig+0x190>
8007322: 4b4a ldr r3, [pc, #296] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007324: 685b ldr r3, [r3, #4]
8007326: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800732a: 2b00 cmp r3, #0
800732c: d116 bne.n 800735c <HAL_RCC_OscConfig+0x190>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800732e: 4b47 ldr r3, [pc, #284] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007330: 681b ldr r3, [r3, #0]
8007332: f003 0302 and.w r3, r3, #2
8007336: 2b00 cmp r3, #0
8007338: d005 beq.n 8007346 <HAL_RCC_OscConfig+0x17a>
800733a: 687b ldr r3, [r7, #4]
800733c: 68db ldr r3, [r3, #12]
800733e: 2b01 cmp r3, #1
8007340: d001 beq.n 8007346 <HAL_RCC_OscConfig+0x17a>
{
return HAL_ERROR;
8007342: 2301 movs r3, #1
8007344: e1df b.n 8007706 <HAL_RCC_OscConfig+0x53a>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8007346: 4b41 ldr r3, [pc, #260] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007348: 681b ldr r3, [r3, #0]
800734a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800734e: 687b ldr r3, [r7, #4]
8007350: 691b ldr r3, [r3, #16]
8007352: 00db lsls r3, r3, #3
8007354: 493d ldr r1, [pc, #244] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007356: 4313 orrs r3, r2
8007358: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800735a: e040 b.n 80073de <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
800735c: 687b ldr r3, [r7, #4]
800735e: 68db ldr r3, [r3, #12]
8007360: 2b00 cmp r3, #0
8007362: d023 beq.n 80073ac <HAL_RCC_OscConfig+0x1e0>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8007364: 4b39 ldr r3, [pc, #228] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007366: 681b ldr r3, [r3, #0]
8007368: 4a38 ldr r2, [pc, #224] ; (800744c <HAL_RCC_OscConfig+0x280>)
800736a: f043 0301 orr.w r3, r3, #1
800736e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007370: f7fd f8be bl 80044f0 <HAL_GetTick>
8007374: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8007376: e008 b.n 800738a <HAL_RCC_OscConfig+0x1be>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8007378: f7fd f8ba bl 80044f0 <HAL_GetTick>
800737c: 4602 mov r2, r0
800737e: 693b ldr r3, [r7, #16]
8007380: 1ad3 subs r3, r2, r3
8007382: 2b02 cmp r3, #2
8007384: d901 bls.n 800738a <HAL_RCC_OscConfig+0x1be>
{
return HAL_TIMEOUT;
8007386: 2303 movs r3, #3
8007388: e1bd b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800738a: 4b30 ldr r3, [pc, #192] ; (800744c <HAL_RCC_OscConfig+0x280>)
800738c: 681b ldr r3, [r3, #0]
800738e: f003 0302 and.w r3, r3, #2
8007392: 2b00 cmp r3, #0
8007394: d0f0 beq.n 8007378 <HAL_RCC_OscConfig+0x1ac>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8007396: 4b2d ldr r3, [pc, #180] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007398: 681b ldr r3, [r3, #0]
800739a: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800739e: 687b ldr r3, [r7, #4]
80073a0: 691b ldr r3, [r3, #16]
80073a2: 00db lsls r3, r3, #3
80073a4: 4929 ldr r1, [pc, #164] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073a6: 4313 orrs r3, r2
80073a8: 600b str r3, [r1, #0]
80073aa: e018 b.n 80073de <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80073ac: 4b27 ldr r3, [pc, #156] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073ae: 681b ldr r3, [r3, #0]
80073b0: 4a26 ldr r2, [pc, #152] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073b2: f023 0301 bic.w r3, r3, #1
80073b6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80073b8: f7fd f89a bl 80044f0 <HAL_GetTick>
80073bc: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80073be: e008 b.n 80073d2 <HAL_RCC_OscConfig+0x206>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80073c0: f7fd f896 bl 80044f0 <HAL_GetTick>
80073c4: 4602 mov r2, r0
80073c6: 693b ldr r3, [r7, #16]
80073c8: 1ad3 subs r3, r2, r3
80073ca: 2b02 cmp r3, #2
80073cc: d901 bls.n 80073d2 <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
80073ce: 2303 movs r3, #3
80073d0: e199 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80073d2: 4b1e ldr r3, [pc, #120] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073d4: 681b ldr r3, [r3, #0]
80073d6: f003 0302 and.w r3, r3, #2
80073da: 2b00 cmp r3, #0
80073dc: d1f0 bne.n 80073c0 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80073de: 687b ldr r3, [r7, #4]
80073e0: 681b ldr r3, [r3, #0]
80073e2: f003 0308 and.w r3, r3, #8
80073e6: 2b00 cmp r3, #0
80073e8: d038 beq.n 800745c <HAL_RCC_OscConfig+0x290>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80073ea: 687b ldr r3, [r7, #4]
80073ec: 695b ldr r3, [r3, #20]
80073ee: 2b00 cmp r3, #0
80073f0: d019 beq.n 8007426 <HAL_RCC_OscConfig+0x25a>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80073f2: 4b16 ldr r3, [pc, #88] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073f4: 6f5b ldr r3, [r3, #116] ; 0x74
80073f6: 4a15 ldr r2, [pc, #84] ; (800744c <HAL_RCC_OscConfig+0x280>)
80073f8: f043 0301 orr.w r3, r3, #1
80073fc: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
80073fe: f7fd f877 bl 80044f0 <HAL_GetTick>
8007402: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8007404: e008 b.n 8007418 <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8007406: f7fd f873 bl 80044f0 <HAL_GetTick>
800740a: 4602 mov r2, r0
800740c: 693b ldr r3, [r7, #16]
800740e: 1ad3 subs r3, r2, r3
8007410: 2b02 cmp r3, #2
8007412: d901 bls.n 8007418 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8007414: 2303 movs r3, #3
8007416: e176 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8007418: 4b0c ldr r3, [pc, #48] ; (800744c <HAL_RCC_OscConfig+0x280>)
800741a: 6f5b ldr r3, [r3, #116] ; 0x74
800741c: f003 0302 and.w r3, r3, #2
8007420: 2b00 cmp r3, #0
8007422: d0f0 beq.n 8007406 <HAL_RCC_OscConfig+0x23a>
8007424: e01a b.n 800745c <HAL_RCC_OscConfig+0x290>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8007426: 4b09 ldr r3, [pc, #36] ; (800744c <HAL_RCC_OscConfig+0x280>)
8007428: 6f5b ldr r3, [r3, #116] ; 0x74
800742a: 4a08 ldr r2, [pc, #32] ; (800744c <HAL_RCC_OscConfig+0x280>)
800742c: f023 0301 bic.w r3, r3, #1
8007430: 6753 str r3, [r2, #116] ; 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007432: f7fd f85d bl 80044f0 <HAL_GetTick>
8007436: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8007438: e00a b.n 8007450 <HAL_RCC_OscConfig+0x284>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800743a: f7fd f859 bl 80044f0 <HAL_GetTick>
800743e: 4602 mov r2, r0
8007440: 693b ldr r3, [r7, #16]
8007442: 1ad3 subs r3, r2, r3
8007444: 2b02 cmp r3, #2
8007446: d903 bls.n 8007450 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8007448: 2303 movs r3, #3
800744a: e15c b.n 8007706 <HAL_RCC_OscConfig+0x53a>
800744c: 40023800 .word 0x40023800
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8007450: 4b91 ldr r3, [pc, #580] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007452: 6f5b ldr r3, [r3, #116] ; 0x74
8007454: f003 0302 and.w r3, r3, #2
8007458: 2b00 cmp r3, #0
800745a: d1ee bne.n 800743a <HAL_RCC_OscConfig+0x26e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800745c: 687b ldr r3, [r7, #4]
800745e: 681b ldr r3, [r3, #0]
8007460: f003 0304 and.w r3, r3, #4
8007464: 2b00 cmp r3, #0
8007466: f000 80a4 beq.w 80075b2 <HAL_RCC_OscConfig+0x3e6>
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800746a: 4b8b ldr r3, [pc, #556] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800746c: 6c1b ldr r3, [r3, #64] ; 0x40
800746e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8007472: 2b00 cmp r3, #0
8007474: d10d bne.n 8007492 <HAL_RCC_OscConfig+0x2c6>
{
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8007476: 4b88 ldr r3, [pc, #544] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007478: 6c1b ldr r3, [r3, #64] ; 0x40
800747a: 4a87 ldr r2, [pc, #540] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800747c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8007480: 6413 str r3, [r2, #64] ; 0x40
8007482: 4b85 ldr r3, [pc, #532] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007484: 6c1b ldr r3, [r3, #64] ; 0x40
8007486: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800748a: 60bb str r3, [r7, #8]
800748c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800748e: 2301 movs r3, #1
8007490: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
8007492: 4b82 ldr r3, [pc, #520] ; (800769c <HAL_RCC_OscConfig+0x4d0>)
8007494: 681b ldr r3, [r3, #0]
8007496: f403 7380 and.w r3, r3, #256 ; 0x100
800749a: 2b00 cmp r3, #0
800749c: d118 bne.n 80074d0 <HAL_RCC_OscConfig+0x304>
{
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
800749e: 4b7f ldr r3, [pc, #508] ; (800769c <HAL_RCC_OscConfig+0x4d0>)
80074a0: 681b ldr r3, [r3, #0]
80074a2: 4a7e ldr r2, [pc, #504] ; (800769c <HAL_RCC_OscConfig+0x4d0>)
80074a4: f443 7380 orr.w r3, r3, #256 ; 0x100
80074a8: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80074aa: f7fd f821 bl 80044f0 <HAL_GetTick>
80074ae: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80074b0: e008 b.n 80074c4 <HAL_RCC_OscConfig+0x2f8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80074b2: f7fd f81d bl 80044f0 <HAL_GetTick>
80074b6: 4602 mov r2, r0
80074b8: 693b ldr r3, [r7, #16]
80074ba: 1ad3 subs r3, r2, r3
80074bc: 2b64 cmp r3, #100 ; 0x64
80074be: d901 bls.n 80074c4 <HAL_RCC_OscConfig+0x2f8>
{
return HAL_TIMEOUT;
80074c0: 2303 movs r3, #3
80074c2: e120 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80074c4: 4b75 ldr r3, [pc, #468] ; (800769c <HAL_RCC_OscConfig+0x4d0>)
80074c6: 681b ldr r3, [r3, #0]
80074c8: f403 7380 and.w r3, r3, #256 ; 0x100
80074cc: 2b00 cmp r3, #0
80074ce: d0f0 beq.n 80074b2 <HAL_RCC_OscConfig+0x2e6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80074d0: 687b ldr r3, [r7, #4]
80074d2: 689b ldr r3, [r3, #8]
80074d4: 2b01 cmp r3, #1
80074d6: d106 bne.n 80074e6 <HAL_RCC_OscConfig+0x31a>
80074d8: 4b6f ldr r3, [pc, #444] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80074da: 6f1b ldr r3, [r3, #112] ; 0x70
80074dc: 4a6e ldr r2, [pc, #440] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80074de: f043 0301 orr.w r3, r3, #1
80074e2: 6713 str r3, [r2, #112] ; 0x70
80074e4: e02d b.n 8007542 <HAL_RCC_OscConfig+0x376>
80074e6: 687b ldr r3, [r7, #4]
80074e8: 689b ldr r3, [r3, #8]
80074ea: 2b00 cmp r3, #0
80074ec: d10c bne.n 8007508 <HAL_RCC_OscConfig+0x33c>
80074ee: 4b6a ldr r3, [pc, #424] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80074f0: 6f1b ldr r3, [r3, #112] ; 0x70
80074f2: 4a69 ldr r2, [pc, #420] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80074f4: f023 0301 bic.w r3, r3, #1
80074f8: 6713 str r3, [r2, #112] ; 0x70
80074fa: 4b67 ldr r3, [pc, #412] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80074fc: 6f1b ldr r3, [r3, #112] ; 0x70
80074fe: 4a66 ldr r2, [pc, #408] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007500: f023 0304 bic.w r3, r3, #4
8007504: 6713 str r3, [r2, #112] ; 0x70
8007506: e01c b.n 8007542 <HAL_RCC_OscConfig+0x376>
8007508: 687b ldr r3, [r7, #4]
800750a: 689b ldr r3, [r3, #8]
800750c: 2b05 cmp r3, #5
800750e: d10c bne.n 800752a <HAL_RCC_OscConfig+0x35e>
8007510: 4b61 ldr r3, [pc, #388] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007512: 6f1b ldr r3, [r3, #112] ; 0x70
8007514: 4a60 ldr r2, [pc, #384] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007516: f043 0304 orr.w r3, r3, #4
800751a: 6713 str r3, [r2, #112] ; 0x70
800751c: 4b5e ldr r3, [pc, #376] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800751e: 6f1b ldr r3, [r3, #112] ; 0x70
8007520: 4a5d ldr r2, [pc, #372] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007522: f043 0301 orr.w r3, r3, #1
8007526: 6713 str r3, [r2, #112] ; 0x70
8007528: e00b b.n 8007542 <HAL_RCC_OscConfig+0x376>
800752a: 4b5b ldr r3, [pc, #364] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800752c: 6f1b ldr r3, [r3, #112] ; 0x70
800752e: 4a5a ldr r2, [pc, #360] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007530: f023 0301 bic.w r3, r3, #1
8007534: 6713 str r3, [r2, #112] ; 0x70
8007536: 4b58 ldr r3, [pc, #352] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007538: 6f1b ldr r3, [r3, #112] ; 0x70
800753a: 4a57 ldr r2, [pc, #348] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800753c: f023 0304 bic.w r3, r3, #4
8007540: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8007542: 687b ldr r3, [r7, #4]
8007544: 689b ldr r3, [r3, #8]
8007546: 2b00 cmp r3, #0
8007548: d015 beq.n 8007576 <HAL_RCC_OscConfig+0x3aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800754a: f7fc ffd1 bl 80044f0 <HAL_GetTick>
800754e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8007550: e00a b.n 8007568 <HAL_RCC_OscConfig+0x39c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8007552: f7fc ffcd bl 80044f0 <HAL_GetTick>
8007556: 4602 mov r2, r0
8007558: 693b ldr r3, [r7, #16]
800755a: 1ad3 subs r3, r2, r3
800755c: f241 3288 movw r2, #5000 ; 0x1388
8007560: 4293 cmp r3, r2
8007562: d901 bls.n 8007568 <HAL_RCC_OscConfig+0x39c>
{
return HAL_TIMEOUT;
8007564: 2303 movs r3, #3
8007566: e0ce b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8007568: 4b4b ldr r3, [pc, #300] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800756a: 6f1b ldr r3, [r3, #112] ; 0x70
800756c: f003 0302 and.w r3, r3, #2
8007570: 2b00 cmp r3, #0
8007572: d0ee beq.n 8007552 <HAL_RCC_OscConfig+0x386>
8007574: e014 b.n 80075a0 <HAL_RCC_OscConfig+0x3d4>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007576: f7fc ffbb bl 80044f0 <HAL_GetTick>
800757a: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800757c: e00a b.n 8007594 <HAL_RCC_OscConfig+0x3c8>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800757e: f7fc ffb7 bl 80044f0 <HAL_GetTick>
8007582: 4602 mov r2, r0
8007584: 693b ldr r3, [r7, #16]
8007586: 1ad3 subs r3, r2, r3
8007588: f241 3288 movw r2, #5000 ; 0x1388
800758c: 4293 cmp r3, r2
800758e: d901 bls.n 8007594 <HAL_RCC_OscConfig+0x3c8>
{
return HAL_TIMEOUT;
8007590: 2303 movs r3, #3
8007592: e0b8 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8007594: 4b40 ldr r3, [pc, #256] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007596: 6f1b ldr r3, [r3, #112] ; 0x70
8007598: f003 0302 and.w r3, r3, #2
800759c: 2b00 cmp r3, #0
800759e: d1ee bne.n 800757e <HAL_RCC_OscConfig+0x3b2>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80075a0: 7dfb ldrb r3, [r7, #23]
80075a2: 2b01 cmp r3, #1
80075a4: d105 bne.n 80075b2 <HAL_RCC_OscConfig+0x3e6>
{
__HAL_RCC_PWR_CLK_DISABLE();
80075a6: 4b3c ldr r3, [pc, #240] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075a8: 6c1b ldr r3, [r3, #64] ; 0x40
80075aa: 4a3b ldr r2, [pc, #236] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075ac: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80075b0: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80075b2: 687b ldr r3, [r7, #4]
80075b4: 699b ldr r3, [r3, #24]
80075b6: 2b00 cmp r3, #0
80075b8: f000 80a4 beq.w 8007704 <HAL_RCC_OscConfig+0x538>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80075bc: 4b36 ldr r3, [pc, #216] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075be: 689b ldr r3, [r3, #8]
80075c0: f003 030c and.w r3, r3, #12
80075c4: 2b08 cmp r3, #8
80075c6: d06b beq.n 80076a0 <HAL_RCC_OscConfig+0x4d4>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80075c8: 687b ldr r3, [r7, #4]
80075ca: 699b ldr r3, [r3, #24]
80075cc: 2b02 cmp r3, #2
80075ce: d149 bne.n 8007664 <HAL_RCC_OscConfig+0x498>
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80075d0: 4b31 ldr r3, [pc, #196] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075d2: 681b ldr r3, [r3, #0]
80075d4: 4a30 ldr r2, [pc, #192] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075d6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
80075da: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80075dc: f7fc ff88 bl 80044f0 <HAL_GetTick>
80075e0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80075e2: e008 b.n 80075f6 <HAL_RCC_OscConfig+0x42a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80075e4: f7fc ff84 bl 80044f0 <HAL_GetTick>
80075e8: 4602 mov r2, r0
80075ea: 693b ldr r3, [r7, #16]
80075ec: 1ad3 subs r3, r2, r3
80075ee: 2b02 cmp r3, #2
80075f0: d901 bls.n 80075f6 <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
80075f2: 2303 movs r3, #3
80075f4: e087 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80075f6: 4b28 ldr r3, [pc, #160] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
80075f8: 681b ldr r3, [r3, #0]
80075fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80075fe: 2b00 cmp r3, #0
8007600: d1f0 bne.n 80075e4 <HAL_RCC_OscConfig+0x418>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8007602: 687b ldr r3, [r7, #4]
8007604: 69da ldr r2, [r3, #28]
8007606: 687b ldr r3, [r7, #4]
8007608: 6a1b ldr r3, [r3, #32]
800760a: 431a orrs r2, r3
800760c: 687b ldr r3, [r7, #4]
800760e: 6a5b ldr r3, [r3, #36] ; 0x24
8007610: 019b lsls r3, r3, #6
8007612: 431a orrs r2, r3
8007614: 687b ldr r3, [r7, #4]
8007616: 6a9b ldr r3, [r3, #40] ; 0x28
8007618: 085b lsrs r3, r3, #1
800761a: 3b01 subs r3, #1
800761c: 041b lsls r3, r3, #16
800761e: 431a orrs r2, r3
8007620: 687b ldr r3, [r7, #4]
8007622: 6adb ldr r3, [r3, #44] ; 0x2c
8007624: 061b lsls r3, r3, #24
8007626: 4313 orrs r3, r2
8007628: 4a1b ldr r2, [pc, #108] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800762a: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000
800762e: 6053 str r3, [r2, #4]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
#endif
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8007630: 4b19 ldr r3, [pc, #100] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007632: 681b ldr r3, [r3, #0]
8007634: 4a18 ldr r2, [pc, #96] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007636: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000
800763a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800763c: f7fc ff58 bl 80044f0 <HAL_GetTick>
8007640: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8007642: e008 b.n 8007656 <HAL_RCC_OscConfig+0x48a>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8007644: f7fc ff54 bl 80044f0 <HAL_GetTick>
8007648: 4602 mov r2, r0
800764a: 693b ldr r3, [r7, #16]
800764c: 1ad3 subs r3, r2, r3
800764e: 2b02 cmp r3, #2
8007650: d901 bls.n 8007656 <HAL_RCC_OscConfig+0x48a>
{
return HAL_TIMEOUT;
8007652: 2303 movs r3, #3
8007654: e057 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8007656: 4b10 ldr r3, [pc, #64] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007658: 681b ldr r3, [r3, #0]
800765a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800765e: 2b00 cmp r3, #0
8007660: d0f0 beq.n 8007644 <HAL_RCC_OscConfig+0x478>
8007662: e04f b.n 8007704 <HAL_RCC_OscConfig+0x538>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8007664: 4b0c ldr r3, [pc, #48] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
8007666: 681b ldr r3, [r3, #0]
8007668: 4a0b ldr r2, [pc, #44] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800766a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
800766e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007670: f7fc ff3e bl 80044f0 <HAL_GetTick>
8007674: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8007676: e008 b.n 800768a <HAL_RCC_OscConfig+0x4be>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8007678: f7fc ff3a bl 80044f0 <HAL_GetTick>
800767c: 4602 mov r2, r0
800767e: 693b ldr r3, [r7, #16]
8007680: 1ad3 subs r3, r2, r3
8007682: 2b02 cmp r3, #2
8007684: d901 bls.n 800768a <HAL_RCC_OscConfig+0x4be>
{
return HAL_TIMEOUT;
8007686: 2303 movs r3, #3
8007688: e03d b.n 8007706 <HAL_RCC_OscConfig+0x53a>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800768a: 4b03 ldr r3, [pc, #12] ; (8007698 <HAL_RCC_OscConfig+0x4cc>)
800768c: 681b ldr r3, [r3, #0]
800768e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8007692: 2b00 cmp r3, #0
8007694: d1f0 bne.n 8007678 <HAL_RCC_OscConfig+0x4ac>
8007696: e035 b.n 8007704 <HAL_RCC_OscConfig+0x538>
8007698: 40023800 .word 0x40023800
800769c: 40007000 .word 0x40007000
}
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
80076a0: 4b1b ldr r3, [pc, #108] ; (8007710 <HAL_RCC_OscConfig+0x544>)
80076a2: 685b ldr r3, [r3, #4]
80076a4: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80076a6: 687b ldr r3, [r7, #4]
80076a8: 699b ldr r3, [r3, #24]
80076aa: 2b01 cmp r3, #1
80076ac: d028 beq.n 8007700 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80076ae: 68fb ldr r3, [r7, #12]
80076b0: f403 0280 and.w r2, r3, #4194304 ; 0x400000
80076b4: 687b ldr r3, [r7, #4]
80076b6: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80076b8: 429a cmp r2, r3
80076ba: d121 bne.n 8007700 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80076bc: 68fb ldr r3, [r7, #12]
80076be: f003 023f and.w r2, r3, #63 ; 0x3f
80076c2: 687b ldr r3, [r7, #4]
80076c4: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80076c6: 429a cmp r2, r3
80076c8: d11a bne.n 8007700 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80076ca: 68fa ldr r2, [r7, #12]
80076cc: f647 73c0 movw r3, #32704 ; 0x7fc0
80076d0: 4013 ands r3, r2
80076d2: 687a ldr r2, [r7, #4]
80076d4: 6a52 ldr r2, [r2, #36] ; 0x24
80076d6: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80076d8: 4293 cmp r3, r2
80076da: d111 bne.n 8007700 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
80076dc: 68fb ldr r3, [r7, #12]
80076de: f403 3240 and.w r2, r3, #196608 ; 0x30000
80076e2: 687b ldr r3, [r7, #4]
80076e4: 6a9b ldr r3, [r3, #40] ; 0x28
80076e6: 085b lsrs r3, r3, #1
80076e8: 3b01 subs r3, #1
80076ea: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80076ec: 429a cmp r2, r3
80076ee: d107 bne.n 8007700 <HAL_RCC_OscConfig+0x534>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80076f0: 68fb ldr r3, [r7, #12]
80076f2: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
80076f6: 687b ldr r3, [r7, #4]
80076f8: 6adb ldr r3, [r3, #44] ; 0x2c
80076fa: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) ||
80076fc: 429a cmp r2, r3
80076fe: d001 beq.n 8007704 <HAL_RCC_OscConfig+0x538>
#endif
{
return HAL_ERROR;
8007700: 2301 movs r3, #1
8007702: e000 b.n 8007706 <HAL_RCC_OscConfig+0x53a>
}
}
}
return HAL_OK;
8007704: 2300 movs r3, #0
}
8007706: 4618 mov r0, r3
8007708: 3718 adds r7, #24
800770a: 46bd mov sp, r7
800770c: bd80 pop {r7, pc}
800770e: bf00 nop
8007710: 40023800 .word 0x40023800
08007714 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8007714: b580 push {r7, lr}
8007716: b084 sub sp, #16
8007718: af00 add r7, sp, #0
800771a: 6078 str r0, [r7, #4]
800771c: 6039 str r1, [r7, #0]
uint32_t tickstart = 0;
800771e: 2300 movs r3, #0
8007720: 60fb str r3, [r7, #12]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8007722: 687b ldr r3, [r7, #4]
8007724: 2b00 cmp r3, #0
8007726: d101 bne.n 800772c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8007728: 2301 movs r3, #1
800772a: e0d0 b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
800772c: 4b6a ldr r3, [pc, #424] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
800772e: 681b ldr r3, [r3, #0]
8007730: f003 030f and.w r3, r3, #15
8007734: 683a ldr r2, [r7, #0]
8007736: 429a cmp r2, r3
8007738: d910 bls.n 800775c <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800773a: 4b67 ldr r3, [pc, #412] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
800773c: 681b ldr r3, [r3, #0]
800773e: f023 020f bic.w r2, r3, #15
8007742: 4965 ldr r1, [pc, #404] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
8007744: 683b ldr r3, [r7, #0]
8007746: 4313 orrs r3, r2
8007748: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
800774a: 4b63 ldr r3, [pc, #396] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
800774c: 681b ldr r3, [r3, #0]
800774e: f003 030f and.w r3, r3, #15
8007752: 683a ldr r2, [r7, #0]
8007754: 429a cmp r2, r3
8007756: d001 beq.n 800775c <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8007758: 2301 movs r3, #1
800775a: e0b8 b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800775c: 687b ldr r3, [r7, #4]
800775e: 681b ldr r3, [r3, #0]
8007760: f003 0302 and.w r3, r3, #2
8007764: 2b00 cmp r3, #0
8007766: d020 beq.n 80077aa <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8007768: 687b ldr r3, [r7, #4]
800776a: 681b ldr r3, [r3, #0]
800776c: f003 0304 and.w r3, r3, #4
8007770: 2b00 cmp r3, #0
8007772: d005 beq.n 8007780 <HAL_RCC_ClockConfig+0x6c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8007774: 4b59 ldr r3, [pc, #356] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007776: 689b ldr r3, [r3, #8]
8007778: 4a58 ldr r2, [pc, #352] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
800777a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
800777e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8007780: 687b ldr r3, [r7, #4]
8007782: 681b ldr r3, [r3, #0]
8007784: f003 0308 and.w r3, r3, #8
8007788: 2b00 cmp r3, #0
800778a: d005 beq.n 8007798 <HAL_RCC_ClockConfig+0x84>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800778c: 4b53 ldr r3, [pc, #332] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
800778e: 689b ldr r3, [r3, #8]
8007790: 4a52 ldr r2, [pc, #328] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007792: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8007796: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8007798: 4b50 ldr r3, [pc, #320] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
800779a: 689b ldr r3, [r3, #8]
800779c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80077a0: 687b ldr r3, [r7, #4]
80077a2: 689b ldr r3, [r3, #8]
80077a4: 494d ldr r1, [pc, #308] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80077a6: 4313 orrs r3, r2
80077a8: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80077aa: 687b ldr r3, [r7, #4]
80077ac: 681b ldr r3, [r3, #0]
80077ae: f003 0301 and.w r3, r3, #1
80077b2: 2b00 cmp r3, #0
80077b4: d040 beq.n 8007838 <HAL_RCC_ClockConfig+0x124>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80077b6: 687b ldr r3, [r7, #4]
80077b8: 685b ldr r3, [r3, #4]
80077ba: 2b01 cmp r3, #1
80077bc: d107 bne.n 80077ce <HAL_RCC_ClockConfig+0xba>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80077be: 4b47 ldr r3, [pc, #284] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80077c0: 681b ldr r3, [r3, #0]
80077c2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80077c6: 2b00 cmp r3, #0
80077c8: d115 bne.n 80077f6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80077ca: 2301 movs r3, #1
80077cc: e07f b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
80077ce: 687b ldr r3, [r7, #4]
80077d0: 685b ldr r3, [r3, #4]
80077d2: 2b02 cmp r3, #2
80077d4: d107 bne.n 80077e6 <HAL_RCC_ClockConfig+0xd2>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80077d6: 4b41 ldr r3, [pc, #260] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80077d8: 681b ldr r3, [r3, #0]
80077da: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80077de: 2b00 cmp r3, #0
80077e0: d109 bne.n 80077f6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80077e2: 2301 movs r3, #1
80077e4: e073 b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80077e6: 4b3d ldr r3, [pc, #244] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80077e8: 681b ldr r3, [r3, #0]
80077ea: f003 0302 and.w r3, r3, #2
80077ee: 2b00 cmp r3, #0
80077f0: d101 bne.n 80077f6 <HAL_RCC_ClockConfig+0xe2>
{
return HAL_ERROR;
80077f2: 2301 movs r3, #1
80077f4: e06b b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80077f6: 4b39 ldr r3, [pc, #228] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80077f8: 689b ldr r3, [r3, #8]
80077fa: f023 0203 bic.w r2, r3, #3
80077fe: 687b ldr r3, [r7, #4]
8007800: 685b ldr r3, [r3, #4]
8007802: 4936 ldr r1, [pc, #216] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007804: 4313 orrs r3, r2
8007806: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007808: f7fc fe72 bl 80044f0 <HAL_GetTick>
800780c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800780e: e00a b.n 8007826 <HAL_RCC_ClockConfig+0x112>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8007810: f7fc fe6e bl 80044f0 <HAL_GetTick>
8007814: 4602 mov r2, r0
8007816: 68fb ldr r3, [r7, #12]
8007818: 1ad3 subs r3, r2, r3
800781a: f241 3288 movw r2, #5000 ; 0x1388
800781e: 4293 cmp r3, r2
8007820: d901 bls.n 8007826 <HAL_RCC_ClockConfig+0x112>
{
return HAL_TIMEOUT;
8007822: 2303 movs r3, #3
8007824: e053 b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8007826: 4b2d ldr r3, [pc, #180] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007828: 689b ldr r3, [r3, #8]
800782a: f003 020c and.w r2, r3, #12
800782e: 687b ldr r3, [r7, #4]
8007830: 685b ldr r3, [r3, #4]
8007832: 009b lsls r3, r3, #2
8007834: 429a cmp r2, r3
8007836: d1eb bne.n 8007810 <HAL_RCC_ClockConfig+0xfc>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8007838: 4b27 ldr r3, [pc, #156] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
800783a: 681b ldr r3, [r3, #0]
800783c: f003 030f and.w r3, r3, #15
8007840: 683a ldr r2, [r7, #0]
8007842: 429a cmp r2, r3
8007844: d210 bcs.n 8007868 <HAL_RCC_ClockConfig+0x154>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8007846: 4b24 ldr r3, [pc, #144] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
8007848: 681b ldr r3, [r3, #0]
800784a: f023 020f bic.w r2, r3, #15
800784e: 4922 ldr r1, [pc, #136] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
8007850: 683b ldr r3, [r7, #0]
8007852: 4313 orrs r3, r2
8007854: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8007856: 4b20 ldr r3, [pc, #128] ; (80078d8 <HAL_RCC_ClockConfig+0x1c4>)
8007858: 681b ldr r3, [r3, #0]
800785a: f003 030f and.w r3, r3, #15
800785e: 683a ldr r2, [r7, #0]
8007860: 429a cmp r2, r3
8007862: d001 beq.n 8007868 <HAL_RCC_ClockConfig+0x154>
{
return HAL_ERROR;
8007864: 2301 movs r3, #1
8007866: e032 b.n 80078ce <HAL_RCC_ClockConfig+0x1ba>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8007868: 687b ldr r3, [r7, #4]
800786a: 681b ldr r3, [r3, #0]
800786c: f003 0304 and.w r3, r3, #4
8007870: 2b00 cmp r3, #0
8007872: d008 beq.n 8007886 <HAL_RCC_ClockConfig+0x172>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8007874: 4b19 ldr r3, [pc, #100] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007876: 689b ldr r3, [r3, #8]
8007878: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
800787c: 687b ldr r3, [r7, #4]
800787e: 68db ldr r3, [r3, #12]
8007880: 4916 ldr r1, [pc, #88] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007882: 4313 orrs r3, r2
8007884: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8007886: 687b ldr r3, [r7, #4]
8007888: 681b ldr r3, [r3, #0]
800788a: f003 0308 and.w r3, r3, #8
800788e: 2b00 cmp r3, #0
8007890: d009 beq.n 80078a6 <HAL_RCC_ClockConfig+0x192>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
8007892: 4b12 ldr r3, [pc, #72] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
8007894: 689b ldr r3, [r3, #8]
8007896: f423 4260 bic.w r2, r3, #57344 ; 0xe000
800789a: 687b ldr r3, [r7, #4]
800789c: 691b ldr r3, [r3, #16]
800789e: 00db lsls r3, r3, #3
80078a0: 490e ldr r1, [pc, #56] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80078a2: 4313 orrs r3, r2
80078a4: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
80078a6: f000 f821 bl 80078ec <HAL_RCC_GetSysClockFreq>
80078aa: 4601 mov r1, r0
80078ac: 4b0b ldr r3, [pc, #44] ; (80078dc <HAL_RCC_ClockConfig+0x1c8>)
80078ae: 689b ldr r3, [r3, #8]
80078b0: 091b lsrs r3, r3, #4
80078b2: f003 030f and.w r3, r3, #15
80078b6: 4a0a ldr r2, [pc, #40] ; (80078e0 <HAL_RCC_ClockConfig+0x1cc>)
80078b8: 5cd3 ldrb r3, [r2, r3]
80078ba: fa21 f303 lsr.w r3, r1, r3
80078be: 4a09 ldr r2, [pc, #36] ; (80078e4 <HAL_RCC_ClockConfig+0x1d0>)
80078c0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick(uwTickPrio);
80078c2: 4b09 ldr r3, [pc, #36] ; (80078e8 <HAL_RCC_ClockConfig+0x1d4>)
80078c4: 681b ldr r3, [r3, #0]
80078c6: 4618 mov r0, r3
80078c8: f7fc fcf6 bl 80042b8 <HAL_InitTick>
return HAL_OK;
80078cc: 2300 movs r3, #0
}
80078ce: 4618 mov r0, r3
80078d0: 3710 adds r7, #16
80078d2: 46bd mov sp, r7
80078d4: bd80 pop {r7, pc}
80078d6: bf00 nop
80078d8: 40023c00 .word 0x40023c00
80078dc: 40023800 .word 0x40023800
80078e0: 0800e370 .word 0x0800e370
80078e4: 2000003c .word 0x2000003c
80078e8: 20000040 .word 0x20000040
080078ec <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
80078ec: b5f0 push {r4, r5, r6, r7, lr}
80078ee: b085 sub sp, #20
80078f0: af00 add r7, sp, #0
uint32_t pllm = 0, pllvco = 0, pllp = 0;
80078f2: 2300 movs r3, #0
80078f4: 607b str r3, [r7, #4]
80078f6: 2300 movs r3, #0
80078f8: 60fb str r3, [r7, #12]
80078fa: 2300 movs r3, #0
80078fc: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0;
80078fe: 2300 movs r3, #0
8007900: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8007902: 4b50 ldr r3, [pc, #320] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
8007904: 689b ldr r3, [r3, #8]
8007906: f003 030c and.w r3, r3, #12
800790a: 2b04 cmp r3, #4
800790c: d007 beq.n 800791e <HAL_RCC_GetSysClockFreq+0x32>
800790e: 2b08 cmp r3, #8
8007910: d008 beq.n 8007924 <HAL_RCC_GetSysClockFreq+0x38>
8007912: 2b00 cmp r3, #0
8007914: f040 808d bne.w 8007a32 <HAL_RCC_GetSysClockFreq+0x146>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8007918: 4b4b ldr r3, [pc, #300] ; (8007a48 <HAL_RCC_GetSysClockFreq+0x15c>)
800791a: 60bb str r3, [r7, #8]
break;
800791c: e08c b.n 8007a38 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
800791e: 4b4b ldr r3, [pc, #300] ; (8007a4c <HAL_RCC_GetSysClockFreq+0x160>)
8007920: 60bb str r3, [r7, #8]
break;
8007922: e089 b.n 8007a38 <HAL_RCC_GetSysClockFreq+0x14c>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8007924: 4b47 ldr r3, [pc, #284] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
8007926: 685b ldr r3, [r3, #4]
8007928: f003 033f and.w r3, r3, #63 ; 0x3f
800792c: 607b str r3, [r7, #4]
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
800792e: 4b45 ldr r3, [pc, #276] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
8007930: 685b ldr r3, [r3, #4]
8007932: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8007936: 2b00 cmp r3, #0
8007938: d023 beq.n 8007982 <HAL_RCC_GetSysClockFreq+0x96>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800793a: 4b42 ldr r3, [pc, #264] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
800793c: 685b ldr r3, [r3, #4]
800793e: 099b lsrs r3, r3, #6
8007940: f04f 0400 mov.w r4, #0
8007944: f240 11ff movw r1, #511 ; 0x1ff
8007948: f04f 0200 mov.w r2, #0
800794c: ea03 0501 and.w r5, r3, r1
8007950: ea04 0602 and.w r6, r4, r2
8007954: 4a3d ldr r2, [pc, #244] ; (8007a4c <HAL_RCC_GetSysClockFreq+0x160>)
8007956: fb02 f106 mul.w r1, r2, r6
800795a: 2200 movs r2, #0
800795c: fb02 f205 mul.w r2, r2, r5
8007960: 440a add r2, r1
8007962: 493a ldr r1, [pc, #232] ; (8007a4c <HAL_RCC_GetSysClockFreq+0x160>)
8007964: fba5 0101 umull r0, r1, r5, r1
8007968: 1853 adds r3, r2, r1
800796a: 4619 mov r1, r3
800796c: 687b ldr r3, [r7, #4]
800796e: f04f 0400 mov.w r4, #0
8007972: 461a mov r2, r3
8007974: 4623 mov r3, r4
8007976: f7f8 fc9b bl 80002b0 <__aeabi_uldivmod>
800797a: 4603 mov r3, r0
800797c: 460c mov r4, r1
800797e: 60fb str r3, [r7, #12]
8007980: e049 b.n 8007a16 <HAL_RCC_GetSysClockFreq+0x12a>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8007982: 4b30 ldr r3, [pc, #192] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
8007984: 685b ldr r3, [r3, #4]
8007986: 099b lsrs r3, r3, #6
8007988: f04f 0400 mov.w r4, #0
800798c: f240 11ff movw r1, #511 ; 0x1ff
8007990: f04f 0200 mov.w r2, #0
8007994: ea03 0501 and.w r5, r3, r1
8007998: ea04 0602 and.w r6, r4, r2
800799c: 4629 mov r1, r5
800799e: 4632 mov r2, r6
80079a0: f04f 0300 mov.w r3, #0
80079a4: f04f 0400 mov.w r4, #0
80079a8: 0154 lsls r4, r2, #5
80079aa: ea44 64d1 orr.w r4, r4, r1, lsr #27
80079ae: 014b lsls r3, r1, #5
80079b0: 4619 mov r1, r3
80079b2: 4622 mov r2, r4
80079b4: 1b49 subs r1, r1, r5
80079b6: eb62 0206 sbc.w r2, r2, r6
80079ba: f04f 0300 mov.w r3, #0
80079be: f04f 0400 mov.w r4, #0
80079c2: 0194 lsls r4, r2, #6
80079c4: ea44 6491 orr.w r4, r4, r1, lsr #26
80079c8: 018b lsls r3, r1, #6
80079ca: 1a5b subs r3, r3, r1
80079cc: eb64 0402 sbc.w r4, r4, r2
80079d0: f04f 0100 mov.w r1, #0
80079d4: f04f 0200 mov.w r2, #0
80079d8: 00e2 lsls r2, r4, #3
80079da: ea42 7253 orr.w r2, r2, r3, lsr #29
80079de: 00d9 lsls r1, r3, #3
80079e0: 460b mov r3, r1
80079e2: 4614 mov r4, r2
80079e4: 195b adds r3, r3, r5
80079e6: eb44 0406 adc.w r4, r4, r6
80079ea: f04f 0100 mov.w r1, #0
80079ee: f04f 0200 mov.w r2, #0
80079f2: 02a2 lsls r2, r4, #10
80079f4: ea42 5293 orr.w r2, r2, r3, lsr #22
80079f8: 0299 lsls r1, r3, #10
80079fa: 460b mov r3, r1
80079fc: 4614 mov r4, r2
80079fe: 4618 mov r0, r3
8007a00: 4621 mov r1, r4
8007a02: 687b ldr r3, [r7, #4]
8007a04: f04f 0400 mov.w r4, #0
8007a08: 461a mov r2, r3
8007a0a: 4623 mov r3, r4
8007a0c: f7f8 fc50 bl 80002b0 <__aeabi_uldivmod>
8007a10: 4603 mov r3, r0
8007a12: 460c mov r4, r1
8007a14: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
8007a16: 4b0b ldr r3, [pc, #44] ; (8007a44 <HAL_RCC_GetSysClockFreq+0x158>)
8007a18: 685b ldr r3, [r3, #4]
8007a1a: 0c1b lsrs r3, r3, #16
8007a1c: f003 0303 and.w r3, r3, #3
8007a20: 3301 adds r3, #1
8007a22: 005b lsls r3, r3, #1
8007a24: 603b str r3, [r7, #0]
sysclockfreq = pllvco / pllp;
8007a26: 68fa ldr r2, [r7, #12]
8007a28: 683b ldr r3, [r7, #0]
8007a2a: fbb2 f3f3 udiv r3, r2, r3
8007a2e: 60bb str r3, [r7, #8]
break;
8007a30: e002 b.n 8007a38 <HAL_RCC_GetSysClockFreq+0x14c>
}
default:
{
sysclockfreq = HSI_VALUE;
8007a32: 4b05 ldr r3, [pc, #20] ; (8007a48 <HAL_RCC_GetSysClockFreq+0x15c>)
8007a34: 60bb str r3, [r7, #8]
break;
8007a36: bf00 nop
}
}
return sysclockfreq;
8007a38: 68bb ldr r3, [r7, #8]
}
8007a3a: 4618 mov r0, r3
8007a3c: 3714 adds r7, #20
8007a3e: 46bd mov sp, r7
8007a40: bdf0 pop {r4, r5, r6, r7, pc}
8007a42: bf00 nop
8007a44: 40023800 .word 0x40023800
8007a48: 00f42400 .word 0x00f42400
8007a4c: 017d7840 .word 0x017d7840
08007a50 <HAL_RCC_GetHCLKFreq>:
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8007a50: b480 push {r7}
8007a52: af00 add r7, sp, #0
return SystemCoreClock;
8007a54: 4b03 ldr r3, [pc, #12] ; (8007a64 <HAL_RCC_GetHCLKFreq+0x14>)
8007a56: 681b ldr r3, [r3, #0]
}
8007a58: 4618 mov r0, r3
8007a5a: 46bd mov sp, r7
8007a5c: f85d 7b04 ldr.w r7, [sp], #4
8007a60: 4770 bx lr
8007a62: bf00 nop
8007a64: 2000003c .word 0x2000003c
08007a68 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8007a68: b580 push {r7, lr}
8007a6a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8007a6c: f7ff fff0 bl 8007a50 <HAL_RCC_GetHCLKFreq>
8007a70: 4601 mov r1, r0
8007a72: 4b05 ldr r3, [pc, #20] ; (8007a88 <HAL_RCC_GetPCLK1Freq+0x20>)
8007a74: 689b ldr r3, [r3, #8]
8007a76: 0a9b lsrs r3, r3, #10
8007a78: f003 0307 and.w r3, r3, #7
8007a7c: 4a03 ldr r2, [pc, #12] ; (8007a8c <HAL_RCC_GetPCLK1Freq+0x24>)
8007a7e: 5cd3 ldrb r3, [r2, r3]
8007a80: fa21 f303 lsr.w r3, r1, r3
}
8007a84: 4618 mov r0, r3
8007a86: bd80 pop {r7, pc}
8007a88: 40023800 .word 0x40023800
8007a8c: 0800e380 .word 0x0800e380
08007a90 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8007a90: b580 push {r7, lr}
8007a92: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8007a94: f7ff ffdc bl 8007a50 <HAL_RCC_GetHCLKFreq>
8007a98: 4601 mov r1, r0
8007a9a: 4b05 ldr r3, [pc, #20] ; (8007ab0 <HAL_RCC_GetPCLK2Freq+0x20>)
8007a9c: 689b ldr r3, [r3, #8]
8007a9e: 0b5b lsrs r3, r3, #13
8007aa0: f003 0307 and.w r3, r3, #7
8007aa4: 4a03 ldr r2, [pc, #12] ; (8007ab4 <HAL_RCC_GetPCLK2Freq+0x24>)
8007aa6: 5cd3 ldrb r3, [r2, r3]
8007aa8: fa21 f303 lsr.w r3, r1, r3
}
8007aac: 4618 mov r0, r3
8007aae: bd80 pop {r7, pc}
8007ab0: 40023800 .word 0x40023800
8007ab4: 0800e380 .word 0x0800e380
08007ab8 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8007ab8: b480 push {r7}
8007aba: b083 sub sp, #12
8007abc: af00 add r7, sp, #0
8007abe: 6078 str r0, [r7, #4]
8007ac0: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8007ac2: 687b ldr r3, [r7, #4]
8007ac4: 220f movs r2, #15
8007ac6: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8007ac8: 4b12 ldr r3, [pc, #72] ; (8007b14 <HAL_RCC_GetClockConfig+0x5c>)
8007aca: 689b ldr r3, [r3, #8]
8007acc: f003 0203 and.w r2, r3, #3
8007ad0: 687b ldr r3, [r7, #4]
8007ad2: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8007ad4: 4b0f ldr r3, [pc, #60] ; (8007b14 <HAL_RCC_GetClockConfig+0x5c>)
8007ad6: 689b ldr r3, [r3, #8]
8007ad8: f003 02f0 and.w r2, r3, #240 ; 0xf0
8007adc: 687b ldr r3, [r7, #4]
8007ade: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8007ae0: 4b0c ldr r3, [pc, #48] ; (8007b14 <HAL_RCC_GetClockConfig+0x5c>)
8007ae2: 689b ldr r3, [r3, #8]
8007ae4: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8007ae8: 687b ldr r3, [r7, #4]
8007aea: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
8007aec: 4b09 ldr r3, [pc, #36] ; (8007b14 <HAL_RCC_GetClockConfig+0x5c>)
8007aee: 689b ldr r3, [r3, #8]
8007af0: 08db lsrs r3, r3, #3
8007af2: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8007af6: 687b ldr r3, [r7, #4]
8007af8: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8007afa: 4b07 ldr r3, [pc, #28] ; (8007b18 <HAL_RCC_GetClockConfig+0x60>)
8007afc: 681b ldr r3, [r3, #0]
8007afe: f003 020f and.w r2, r3, #15
8007b02: 683b ldr r3, [r7, #0]
8007b04: 601a str r2, [r3, #0]
}
8007b06: bf00 nop
8007b08: 370c adds r7, #12
8007b0a: 46bd mov sp, r7
8007b0c: f85d 7b04 ldr.w r7, [sp], #4
8007b10: 4770 bx lr
8007b12: bf00 nop
8007b14: 40023800 .word 0x40023800
8007b18: 40023c00 .word 0x40023c00
08007b1c <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8007b1c: b580 push {r7, lr}
8007b1e: b088 sub sp, #32
8007b20: af00 add r7, sp, #0
8007b22: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8007b24: 2300 movs r3, #0
8007b26: 617b str r3, [r7, #20]
uint32_t tmpreg0 = 0;
8007b28: 2300 movs r3, #0
8007b2a: 613b str r3, [r7, #16]
uint32_t tmpreg1 = 0;
8007b2c: 2300 movs r3, #0
8007b2e: 60fb str r3, [r7, #12]
uint32_t plli2sused = 0;
8007b30: 2300 movs r3, #0
8007b32: 61fb str r3, [r7, #28]
uint32_t pllsaiused = 0;
8007b34: 2300 movs r3, #0
8007b36: 61bb str r3, [r7, #24]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*----------------------------------- I2S configuration ----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8007b38: 687b ldr r3, [r7, #4]
8007b3a: 681b ldr r3, [r3, #0]
8007b3c: f003 0301 and.w r3, r3, #1
8007b40: 2b00 cmp r3, #0
8007b42: d012 beq.n 8007b6a <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure I2S Clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8007b44: 4b69 ldr r3, [pc, #420] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b46: 689b ldr r3, [r3, #8]
8007b48: 4a68 ldr r2, [pc, #416] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b4a: f423 0300 bic.w r3, r3, #8388608 ; 0x800000
8007b4e: 6093 str r3, [r2, #8]
8007b50: 4b66 ldr r3, [pc, #408] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b52: 689a ldr r2, [r3, #8]
8007b54: 687b ldr r3, [r7, #4]
8007b56: 6b5b ldr r3, [r3, #52] ; 0x34
8007b58: 4964 ldr r1, [pc, #400] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b5a: 4313 orrs r3, r2
8007b5c: 608b str r3, [r1, #8]
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)
8007b5e: 687b ldr r3, [r7, #4]
8007b60: 6b5b ldr r3, [r3, #52] ; 0x34
8007b62: 2b00 cmp r3, #0
8007b64: d101 bne.n 8007b6a <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
plli2sused = 1;
8007b66: 2301 movs r3, #1
8007b68: 61fb str r3, [r7, #28]
}
}
/*------------------------------------ SAI1 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
8007b6a: 687b ldr r3, [r7, #4]
8007b6c: 681b ldr r3, [r3, #0]
8007b6e: f403 2300 and.w r3, r3, #524288 ; 0x80000
8007b72: 2b00 cmp r3, #0
8007b74: d017 beq.n 8007ba6 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8007b76: 4b5d ldr r3, [pc, #372] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b78: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8007b7c: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8007b80: 687b ldr r3, [r7, #4]
8007b82: 6bdb ldr r3, [r3, #60] ; 0x3c
8007b84: 4959 ldr r1, [pc, #356] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007b86: 4313 orrs r3, r2
8007b88: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
8007b8c: 687b ldr r3, [r7, #4]
8007b8e: 6bdb ldr r3, [r3, #60] ; 0x3c
8007b90: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8007b94: d101 bne.n 8007b9a <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
plli2sused = 1;
8007b96: 2301 movs r3, #1
8007b98: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
8007b9a: 687b ldr r3, [r7, #4]
8007b9c: 6bdb ldr r3, [r3, #60] ; 0x3c
8007b9e: 2b00 cmp r3, #0
8007ba0: d101 bne.n 8007ba6 <HAL_RCCEx_PeriphCLKConfig+0x8a>
{
pllsaiused = 1;
8007ba2: 2301 movs r3, #1
8007ba4: 61bb str r3, [r7, #24]
}
}
/*------------------------------------ SAI2 configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
8007ba6: 687b ldr r3, [r7, #4]
8007ba8: 681b ldr r3, [r3, #0]
8007baa: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8007bae: 2b00 cmp r3, #0
8007bb0: d017 beq.n 8007be2 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
8007bb2: 4b4e ldr r3, [pc, #312] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007bb4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8007bb8: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8007bbc: 687b ldr r3, [r7, #4]
8007bbe: 6c1b ldr r3, [r3, #64] ; 0x40
8007bc0: 494a ldr r1, [pc, #296] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007bc2: 4313 orrs r3, r2
8007bc4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
8007bc8: 687b ldr r3, [r7, #4]
8007bca: 6c1b ldr r3, [r3, #64] ; 0x40
8007bcc: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8007bd0: d101 bne.n 8007bd6 <HAL_RCCEx_PeriphCLKConfig+0xba>
{
plli2sused = 1;
8007bd2: 2301 movs r3, #1
8007bd4: 61fb str r3, [r7, #28]
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
8007bd6: 687b ldr r3, [r7, #4]
8007bd8: 6c1b ldr r3, [r3, #64] ; 0x40
8007bda: 2b00 cmp r3, #0
8007bdc: d101 bne.n 8007be2 <HAL_RCCEx_PeriphCLKConfig+0xc6>
{
pllsaiused = 1;
8007bde: 2301 movs r3, #1
8007be0: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8007be2: 687b ldr r3, [r7, #4]
8007be4: 681b ldr r3, [r3, #0]
8007be6: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8007bea: 2b00 cmp r3, #0
8007bec: d001 beq.n 8007bf2 <HAL_RCCEx_PeriphCLKConfig+0xd6>
{
plli2sused = 1;
8007bee: 2301 movs r3, #1
8007bf0: 61fb str r3, [r7, #28]
}
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8007bf2: 687b ldr r3, [r7, #4]
8007bf4: 681b ldr r3, [r3, #0]
8007bf6: f003 0320 and.w r3, r3, #32
8007bfa: 2b00 cmp r3, #0
8007bfc: f000 808b beq.w 8007d16 <HAL_RCCEx_PeriphCLKConfig+0x1fa>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8007c00: 4b3a ldr r3, [pc, #232] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c02: 6c1b ldr r3, [r3, #64] ; 0x40
8007c04: 4a39 ldr r2, [pc, #228] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c06: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8007c0a: 6413 str r3, [r2, #64] ; 0x40
8007c0c: 4b37 ldr r3, [pc, #220] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c0e: 6c1b ldr r3, [r3, #64] ; 0x40
8007c10: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8007c14: 60bb str r3, [r7, #8]
8007c16: 68bb ldr r3, [r7, #8]
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
8007c18: 4b35 ldr r3, [pc, #212] ; (8007cf0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8007c1a: 681b ldr r3, [r3, #0]
8007c1c: 4a34 ldr r2, [pc, #208] ; (8007cf0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8007c1e: f443 7380 orr.w r3, r3, #256 ; 0x100
8007c22: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007c24: f7fc fc64 bl 80044f0 <HAL_GetTick>
8007c28: 6178 str r0, [r7, #20]
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
8007c2a: e008 b.n 8007c3e <HAL_RCCEx_PeriphCLKConfig+0x122>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8007c2c: f7fc fc60 bl 80044f0 <HAL_GetTick>
8007c30: 4602 mov r2, r0
8007c32: 697b ldr r3, [r7, #20]
8007c34: 1ad3 subs r3, r2, r3
8007c36: 2b64 cmp r3, #100 ; 0x64
8007c38: d901 bls.n 8007c3e <HAL_RCCEx_PeriphCLKConfig+0x122>
{
return HAL_TIMEOUT;
8007c3a: 2303 movs r3, #3
8007c3c: e355 b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
8007c3e: 4b2c ldr r3, [pc, #176] ; (8007cf0 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8007c40: 681b ldr r3, [r3, #0]
8007c42: f403 7380 and.w r3, r3, #256 ; 0x100
8007c46: 2b00 cmp r3, #0
8007c48: d0f0 beq.n 8007c2c <HAL_RCCEx_PeriphCLKConfig+0x110>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
8007c4a: 4b28 ldr r3, [pc, #160] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c4c: 6f1b ldr r3, [r3, #112] ; 0x70
8007c4e: f403 7340 and.w r3, r3, #768 ; 0x300
8007c52: 613b str r3, [r7, #16]
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8007c54: 693b ldr r3, [r7, #16]
8007c56: 2b00 cmp r3, #0
8007c58: d035 beq.n 8007cc6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
8007c5a: 687b ldr r3, [r7, #4]
8007c5c: 6b1b ldr r3, [r3, #48] ; 0x30
8007c5e: f403 7340 and.w r3, r3, #768 ; 0x300
8007c62: 693a ldr r2, [r7, #16]
8007c64: 429a cmp r2, r3
8007c66: d02e beq.n 8007cc6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8007c68: 4b20 ldr r3, [pc, #128] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c6a: 6f1b ldr r3, [r3, #112] ; 0x70
8007c6c: f423 7340 bic.w r3, r3, #768 ; 0x300
8007c70: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8007c72: 4b1e ldr r3, [pc, #120] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c74: 6f1b ldr r3, [r3, #112] ; 0x70
8007c76: 4a1d ldr r2, [pc, #116] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c78: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8007c7c: 6713 str r3, [r2, #112] ; 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
8007c7e: 4b1b ldr r3, [pc, #108] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c80: 6f1b ldr r3, [r3, #112] ; 0x70
8007c82: 4a1a ldr r2, [pc, #104] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c84: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8007c88: 6713 str r3, [r2, #112] ; 0x70
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
8007c8a: 4a18 ldr r2, [pc, #96] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c8c: 693b ldr r3, [r7, #16]
8007c8e: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8007c90: 4b16 ldr r3, [pc, #88] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007c92: 6f1b ldr r3, [r3, #112] ; 0x70
8007c94: f003 0301 and.w r3, r3, #1
8007c98: 2b01 cmp r3, #1
8007c9a: d114 bne.n 8007cc6 <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007c9c: f7fc fc28 bl 80044f0 <HAL_GetTick>
8007ca0: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8007ca2: e00a b.n 8007cba <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8007ca4: f7fc fc24 bl 80044f0 <HAL_GetTick>
8007ca8: 4602 mov r2, r0
8007caa: 697b ldr r3, [r7, #20]
8007cac: 1ad3 subs r3, r2, r3
8007cae: f241 3288 movw r2, #5000 ; 0x1388
8007cb2: 4293 cmp r3, r2
8007cb4: d901 bls.n 8007cba <HAL_RCCEx_PeriphCLKConfig+0x19e>
{
return HAL_TIMEOUT;
8007cb6: 2303 movs r3, #3
8007cb8: e317 b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8007cba: 4b0c ldr r3, [pc, #48] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007cbc: 6f1b ldr r3, [r3, #112] ; 0x70
8007cbe: f003 0302 and.w r3, r3, #2
8007cc2: 2b00 cmp r3, #0
8007cc4: d0ee beq.n 8007ca4 <HAL_RCCEx_PeriphCLKConfig+0x188>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8007cc6: 687b ldr r3, [r7, #4]
8007cc8: 6b1b ldr r3, [r3, #48] ; 0x30
8007cca: f403 7340 and.w r3, r3, #768 ; 0x300
8007cce: f5b3 7f40 cmp.w r3, #768 ; 0x300
8007cd2: d111 bne.n 8007cf8 <HAL_RCCEx_PeriphCLKConfig+0x1dc>
8007cd4: 4b05 ldr r3, [pc, #20] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007cd6: 689b ldr r3, [r3, #8]
8007cd8: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
8007cdc: 687b ldr r3, [r7, #4]
8007cde: 6b19 ldr r1, [r3, #48] ; 0x30
8007ce0: 4b04 ldr r3, [pc, #16] ; (8007cf4 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
8007ce2: 400b ands r3, r1
8007ce4: 4901 ldr r1, [pc, #4] ; (8007cec <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8007ce6: 4313 orrs r3, r2
8007ce8: 608b str r3, [r1, #8]
8007cea: e00b b.n 8007d04 <HAL_RCCEx_PeriphCLKConfig+0x1e8>
8007cec: 40023800 .word 0x40023800
8007cf0: 40007000 .word 0x40007000
8007cf4: 0ffffcff .word 0x0ffffcff
8007cf8: 4bb0 ldr r3, [pc, #704] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007cfa: 689b ldr r3, [r3, #8]
8007cfc: 4aaf ldr r2, [pc, #700] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007cfe: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
8007d02: 6093 str r3, [r2, #8]
8007d04: 4bad ldr r3, [pc, #692] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d06: 6f1a ldr r2, [r3, #112] ; 0x70
8007d08: 687b ldr r3, [r7, #4]
8007d0a: 6b1b ldr r3, [r3, #48] ; 0x30
8007d0c: f3c3 030b ubfx r3, r3, #0, #12
8007d10: 49aa ldr r1, [pc, #680] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d12: 4313 orrs r3, r2
8007d14: 670b str r3, [r1, #112] ; 0x70
}
/*------------------------------------ TIM configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8007d16: 687b ldr r3, [r7, #4]
8007d18: 681b ldr r3, [r3, #0]
8007d1a: f003 0310 and.w r3, r3, #16
8007d1e: 2b00 cmp r3, #0
8007d20: d010 beq.n 8007d44 <HAL_RCCEx_PeriphCLKConfig+0x228>
{
/* Check the parameters */
assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
/* Configure Timer Prescaler */
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8007d22: 4ba6 ldr r3, [pc, #664] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d24: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
8007d28: 4aa4 ldr r2, [pc, #656] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d2a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000
8007d2e: f8c2 308c str.w r3, [r2, #140] ; 0x8c
8007d32: 4ba2 ldr r3, [pc, #648] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d34: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c
8007d38: 687b ldr r3, [r7, #4]
8007d3a: 6b9b ldr r3, [r3, #56] ; 0x38
8007d3c: 499f ldr r1, [pc, #636] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d3e: 4313 orrs r3, r2
8007d40: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*-------------------------------------- I2C1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8007d44: 687b ldr r3, [r7, #4]
8007d46: 681b ldr r3, [r3, #0]
8007d48: f403 4380 and.w r3, r3, #16384 ; 0x4000
8007d4c: 2b00 cmp r3, #0
8007d4e: d00a beq.n 8007d66 <HAL_RCCEx_PeriphCLKConfig+0x24a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8007d50: 4b9a ldr r3, [pc, #616] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d52: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007d56: f423 3240 bic.w r2, r3, #196608 ; 0x30000
8007d5a: 687b ldr r3, [r7, #4]
8007d5c: 6e5b ldr r3, [r3, #100] ; 0x64
8007d5e: 4997 ldr r1, [pc, #604] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d60: 4313 orrs r3, r2
8007d62: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8007d66: 687b ldr r3, [r7, #4]
8007d68: 681b ldr r3, [r3, #0]
8007d6a: f403 4300 and.w r3, r3, #32768 ; 0x8000
8007d6e: 2b00 cmp r3, #0
8007d70: d00a beq.n 8007d88 <HAL_RCCEx_PeriphCLKConfig+0x26c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8007d72: 4b92 ldr r3, [pc, #584] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d74: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007d78: f423 2240 bic.w r2, r3, #786432 ; 0xc0000
8007d7c: 687b ldr r3, [r7, #4]
8007d7e: 6e9b ldr r3, [r3, #104] ; 0x68
8007d80: 498e ldr r1, [pc, #568] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d82: 4313 orrs r3, r2
8007d84: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
8007d88: 687b ldr r3, [r7, #4]
8007d8a: 681b ldr r3, [r3, #0]
8007d8c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8007d90: 2b00 cmp r3, #0
8007d92: d00a beq.n 8007daa <HAL_RCCEx_PeriphCLKConfig+0x28e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
8007d94: 4b89 ldr r3, [pc, #548] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007d96: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007d9a: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
8007d9e: 687b ldr r3, [r7, #4]
8007da0: 6edb ldr r3, [r3, #108] ; 0x6c
8007da2: 4986 ldr r1, [pc, #536] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007da4: 4313 orrs r3, r2
8007da6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- I2C4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8007daa: 687b ldr r3, [r7, #4]
8007dac: 681b ldr r3, [r3, #0]
8007dae: f403 3300 and.w r3, r3, #131072 ; 0x20000
8007db2: 2b00 cmp r3, #0
8007db4: d00a beq.n 8007dcc <HAL_RCCEx_PeriphCLKConfig+0x2b0>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8007db6: 4b81 ldr r3, [pc, #516] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007db8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007dbc: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000
8007dc0: 687b ldr r3, [r7, #4]
8007dc2: 6f1b ldr r3, [r3, #112] ; 0x70
8007dc4: 497d ldr r1, [pc, #500] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007dc6: 4313 orrs r3, r2
8007dc8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8007dcc: 687b ldr r3, [r7, #4]
8007dce: 681b ldr r3, [r3, #0]
8007dd0: f003 0340 and.w r3, r3, #64 ; 0x40
8007dd4: 2b00 cmp r3, #0
8007dd6: d00a beq.n 8007dee <HAL_RCCEx_PeriphCLKConfig+0x2d2>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8007dd8: 4b78 ldr r3, [pc, #480] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007dda: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007dde: f023 0203 bic.w r2, r3, #3
8007de2: 687b ldr r3, [r7, #4]
8007de4: 6c5b ldr r3, [r3, #68] ; 0x44
8007de6: 4975 ldr r1, [pc, #468] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007de8: 4313 orrs r3, r2
8007dea: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART2 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8007dee: 687b ldr r3, [r7, #4]
8007df0: 681b ldr r3, [r3, #0]
8007df2: f003 0380 and.w r3, r3, #128 ; 0x80
8007df6: 2b00 cmp r3, #0
8007df8: d00a beq.n 8007e10 <HAL_RCCEx_PeriphCLKConfig+0x2f4>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8007dfa: 4b70 ldr r3, [pc, #448] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007dfc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007e00: f023 020c bic.w r2, r3, #12
8007e04: 687b ldr r3, [r7, #4]
8007e06: 6c9b ldr r3, [r3, #72] ; 0x48
8007e08: 496c ldr r1, [pc, #432] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e0a: 4313 orrs r3, r2
8007e0c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART3 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
8007e10: 687b ldr r3, [r7, #4]
8007e12: 681b ldr r3, [r3, #0]
8007e14: f403 7380 and.w r3, r3, #256 ; 0x100
8007e18: 2b00 cmp r3, #0
8007e1a: d00a beq.n 8007e32 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
8007e1c: 4b67 ldr r3, [pc, #412] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007e22: f023 0230 bic.w r2, r3, #48 ; 0x30
8007e26: 687b ldr r3, [r7, #4]
8007e28: 6cdb ldr r3, [r3, #76] ; 0x4c
8007e2a: 4964 ldr r1, [pc, #400] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e2c: 4313 orrs r3, r2
8007e2e: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART4 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
8007e32: 687b ldr r3, [r7, #4]
8007e34: 681b ldr r3, [r3, #0]
8007e36: f403 7300 and.w r3, r3, #512 ; 0x200
8007e3a: 2b00 cmp r3, #0
8007e3c: d00a beq.n 8007e54 <HAL_RCCEx_PeriphCLKConfig+0x338>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
8007e3e: 4b5f ldr r3, [pc, #380] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e40: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007e44: f023 02c0 bic.w r2, r3, #192 ; 0xc0
8007e48: 687b ldr r3, [r7, #4]
8007e4a: 6d1b ldr r3, [r3, #80] ; 0x50
8007e4c: 495b ldr r1, [pc, #364] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e4e: 4313 orrs r3, r2
8007e50: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART5 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8007e54: 687b ldr r3, [r7, #4]
8007e56: 681b ldr r3, [r3, #0]
8007e58: f403 6380 and.w r3, r3, #1024 ; 0x400
8007e5c: 2b00 cmp r3, #0
8007e5e: d00a beq.n 8007e76 <HAL_RCCEx_PeriphCLKConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
8007e60: 4b56 ldr r3, [pc, #344] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007e66: f423 7240 bic.w r2, r3, #768 ; 0x300
8007e6a: 687b ldr r3, [r7, #4]
8007e6c: 6d5b ldr r3, [r3, #84] ; 0x54
8007e6e: 4953 ldr r1, [pc, #332] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e70: 4313 orrs r3, r2
8007e72: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- USART6 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
8007e76: 687b ldr r3, [r7, #4]
8007e78: 681b ldr r3, [r3, #0]
8007e7a: f403 6300 and.w r3, r3, #2048 ; 0x800
8007e7e: 2b00 cmp r3, #0
8007e80: d00a beq.n 8007e98 <HAL_RCCEx_PeriphCLKConfig+0x37c>
{
/* Check the parameters */
assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
/* Configure the USART6 clock source */
__HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
8007e82: 4b4e ldr r3, [pc, #312] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007e88: f423 6240 bic.w r2, r3, #3072 ; 0xc00
8007e8c: 687b ldr r3, [r7, #4]
8007e8e: 6d9b ldr r3, [r3, #88] ; 0x58
8007e90: 494a ldr r1, [pc, #296] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007e92: 4313 orrs r3, r2
8007e94: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART7 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7)
8007e98: 687b ldr r3, [r7, #4]
8007e9a: 681b ldr r3, [r3, #0]
8007e9c: f403 5380 and.w r3, r3, #4096 ; 0x1000
8007ea0: 2b00 cmp r3, #0
8007ea2: d00a beq.n 8007eba <HAL_RCCEx_PeriphCLKConfig+0x39e>
{
/* Check the parameters */
assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection));
/* Configure the UART7 clock source */
__HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection);
8007ea4: 4b45 ldr r3, [pc, #276] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007ea6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007eaa: f423 5240 bic.w r2, r3, #12288 ; 0x3000
8007eae: 687b ldr r3, [r7, #4]
8007eb0: 6ddb ldr r3, [r3, #92] ; 0x5c
8007eb2: 4942 ldr r1, [pc, #264] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007eb4: 4313 orrs r3, r2
8007eb6: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- UART8 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8)
8007eba: 687b ldr r3, [r7, #4]
8007ebc: 681b ldr r3, [r3, #0]
8007ebe: f403 5300 and.w r3, r3, #8192 ; 0x2000
8007ec2: 2b00 cmp r3, #0
8007ec4: d00a beq.n 8007edc <HAL_RCCEx_PeriphCLKConfig+0x3c0>
{
/* Check the parameters */
assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection));
/* Configure the UART8 clock source */
__HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection);
8007ec6: 4b3d ldr r3, [pc, #244] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007ec8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007ecc: f423 4240 bic.w r2, r3, #49152 ; 0xc000
8007ed0: 687b ldr r3, [r7, #4]
8007ed2: 6e1b ldr r3, [r3, #96] ; 0x60
8007ed4: 4939 ldr r1, [pc, #228] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007ed6: 4313 orrs r3, r2
8007ed8: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*--------------------------------------- CEC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8007edc: 687b ldr r3, [r7, #4]
8007ede: 681b ldr r3, [r3, #0]
8007ee0: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8007ee4: 2b00 cmp r3, #0
8007ee6: d00a beq.n 8007efe <HAL_RCCEx_PeriphCLKConfig+0x3e2>
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8007ee8: 4b34 ldr r3, [pc, #208] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007eea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007eee: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000
8007ef2: 687b ldr r3, [r7, #4]
8007ef4: 6f9b ldr r3, [r3, #120] ; 0x78
8007ef6: 4931 ldr r1, [pc, #196] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007ef8: 4313 orrs r3, r2
8007efa: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*-------------------------------------- CK48 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
8007efe: 687b ldr r3, [r7, #4]
8007f00: 681b ldr r3, [r3, #0]
8007f02: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8007f06: 2b00 cmp r3, #0
8007f08: d011 beq.n 8007f2e <HAL_RCCEx_PeriphCLKConfig+0x412>
{
/* Check the parameters */
assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection));
/* Configure the CLK48 source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
8007f0a: 4b2c ldr r3, [pc, #176] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007f10: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000
8007f14: 687b ldr r3, [r7, #4]
8007f16: 6fdb ldr r3, [r3, #124] ; 0x7c
8007f18: 4928 ldr r1, [pc, #160] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f1a: 4313 orrs r3, r2
8007f1c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
/* Enable the PLLSAI when it's used as clock source for CK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)
8007f20: 687b ldr r3, [r7, #4]
8007f22: 6fdb ldr r3, [r3, #124] ; 0x7c
8007f24: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
8007f28: d101 bne.n 8007f2e <HAL_RCCEx_PeriphCLKConfig+0x412>
{
pllsaiused = 1;
8007f2a: 2301 movs r3, #1
8007f2c: 61bb str r3, [r7, #24]
}
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
8007f2e: 687b ldr r3, [r7, #4]
8007f30: 681b ldr r3, [r3, #0]
8007f32: f003 0308 and.w r3, r3, #8
8007f36: 2b00 cmp r3, #0
8007f38: d001 beq.n 8007f3e <HAL_RCCEx_PeriphCLKConfig+0x422>
{
pllsaiused = 1;
8007f3a: 2301 movs r3, #1
8007f3c: 61bb str r3, [r7, #24]
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8007f3e: 687b ldr r3, [r7, #4]
8007f40: 681b ldr r3, [r3, #0]
8007f42: f403 2380 and.w r3, r3, #262144 ; 0x40000
8007f46: 2b00 cmp r3, #0
8007f48: d00a beq.n 8007f60 <HAL_RCCEx_PeriphCLKConfig+0x444>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LTPIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8007f4a: 4b1c ldr r3, [pc, #112] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f4c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007f50: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000
8007f54: 687b ldr r3, [r7, #4]
8007f56: 6f5b ldr r3, [r3, #116] ; 0x74
8007f58: 4918 ldr r1, [pc, #96] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f5a: 4313 orrs r3, r2
8007f5c: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
/*------------------------------------- SDMMC1 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)
8007f60: 687b ldr r3, [r7, #4]
8007f62: 681b ldr r3, [r3, #0]
8007f64: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8007f68: 2b00 cmp r3, #0
8007f6a: d00b beq.n 8007f84 <HAL_RCCEx_PeriphCLKConfig+0x468>
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
8007f6c: 4b13 ldr r3, [pc, #76] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f6e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
8007f72: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000
8007f76: 687b ldr r3, [r7, #4]
8007f78: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8007f7c: 490f ldr r1, [pc, #60] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f7e: 4313 orrs r3, r2
8007f80: f8c1 3090 str.w r3, [r1, #144] ; 0x90
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
8007f84: 69fb ldr r3, [r7, #28]
8007f86: 2b01 cmp r3, #1
8007f88: d005 beq.n 8007f96 <HAL_RCCEx_PeriphCLKConfig+0x47a>
8007f8a: 687b ldr r3, [r7, #4]
8007f8c: 681b ldr r3, [r3, #0]
8007f8e: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
8007f92: f040 80d8 bne.w 8008146 <HAL_RCCEx_PeriphCLKConfig+0x62a>
{
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8007f96: 4b09 ldr r3, [pc, #36] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f98: 681b ldr r3, [r3, #0]
8007f9a: 4a08 ldr r2, [pc, #32] ; (8007fbc <HAL_RCCEx_PeriphCLKConfig+0x4a0>)
8007f9c: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000
8007fa0: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8007fa2: f7fc faa5 bl 80044f0 <HAL_GetTick>
8007fa6: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8007fa8: e00a b.n 8007fc0 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8007faa: f7fc faa1 bl 80044f0 <HAL_GetTick>
8007fae: 4602 mov r2, r0
8007fb0: 697b ldr r3, [r7, #20]
8007fb2: 1ad3 subs r3, r2, r3
8007fb4: 2b64 cmp r3, #100 ; 0x64
8007fb6: d903 bls.n 8007fc0 <HAL_RCCEx_PeriphCLKConfig+0x4a4>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8007fb8: 2303 movs r3, #3
8007fba: e196 b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
8007fbc: 40023800 .word 0x40023800
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8007fc0: 4b6c ldr r3, [pc, #432] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8007fc2: 681b ldr r3, [r3, #0]
8007fc4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8007fc8: 2b00 cmp r3, #0
8007fca: d1ee bne.n 8007faa <HAL_RCCEx_PeriphCLKConfig+0x48e>
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S)))
8007fcc: 687b ldr r3, [r7, #4]
8007fce: 681b ldr r3, [r3, #0]
8007fd0: f003 0301 and.w r3, r3, #1
8007fd4: 2b00 cmp r3, #0
8007fd6: d021 beq.n 800801c <HAL_RCCEx_PeriphCLKConfig+0x500>
8007fd8: 687b ldr r3, [r7, #4]
8007fda: 6b5b ldr r3, [r3, #52] ; 0x34
8007fdc: 2b00 cmp r3, #0
8007fde: d11d bne.n 800801c <HAL_RCCEx_PeriphCLKConfig+0x500>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8007fe0: 4b64 ldr r3, [pc, #400] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8007fe2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8007fe6: 0c1b lsrs r3, r3, #16
8007fe8: f003 0303 and.w r3, r3, #3
8007fec: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
8007fee: 4b61 ldr r3, [pc, #388] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8007ff0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8007ff4: 0e1b lsrs r3, r3, #24
8007ff6: f003 030f and.w r3, r3, #15
8007ffa: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR);
8007ffc: 687b ldr r3, [r7, #4]
8007ffe: 685b ldr r3, [r3, #4]
8008000: 019a lsls r2, r3, #6
8008002: 693b ldr r3, [r7, #16]
8008004: 041b lsls r3, r3, #16
8008006: 431a orrs r2, r3
8008008: 68fb ldr r3, [r7, #12]
800800a: 061b lsls r3, r3, #24
800800c: 431a orrs r2, r3
800800e: 687b ldr r3, [r7, #4]
8008010: 689b ldr r3, [r3, #8]
8008012: 071b lsls r3, r3, #28
8008014: 4957 ldr r1, [pc, #348] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008016: 4313 orrs r3, r2
8008018: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
800801c: 687b ldr r3, [r7, #4]
800801e: 681b ldr r3, [r3, #0]
8008020: f403 2300 and.w r3, r3, #524288 ; 0x80000
8008024: 2b00 cmp r3, #0
8008026: d004 beq.n 8008032 <HAL_RCCEx_PeriphCLKConfig+0x516>
8008028: 687b ldr r3, [r7, #4]
800802a: 6bdb ldr r3, [r3, #60] ; 0x3c
800802c: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
8008030: d00a beq.n 8008048 <HAL_RCCEx_PeriphCLKConfig+0x52c>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
8008032: 687b ldr r3, [r7, #4]
8008034: 681b ldr r3, [r3, #0]
8008036: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
800803a: 2b00 cmp r3, #0
800803c: d02e beq.n 800809c <HAL_RCCEx_PeriphCLKConfig+0x580>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
800803e: 687b ldr r3, [r7, #4]
8008040: 6c1b ldr r3, [r3, #64] ; 0x40
8008042: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8008046: d129 bne.n 800809c <HAL_RCCEx_PeriphCLKConfig+0x580>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
8008048: 4b4a ldr r3, [pc, #296] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800804a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800804e: 0c1b lsrs r3, r3, #16
8008050: f003 0303 and.w r3, r3, #3
8008054: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8008056: 4b47 ldr r3, [pc, #284] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008058: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
800805c: 0f1b lsrs r3, r3, #28
800805e: f003 0307 and.w r3, r3, #7
8008062: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
8008064: 687b ldr r3, [r7, #4]
8008066: 685b ldr r3, [r3, #4]
8008068: 019a lsls r2, r3, #6
800806a: 693b ldr r3, [r7, #16]
800806c: 041b lsls r3, r3, #16
800806e: 431a orrs r2, r3
8008070: 687b ldr r3, [r7, #4]
8008072: 68db ldr r3, [r3, #12]
8008074: 061b lsls r3, r3, #24
8008076: 431a orrs r2, r3
8008078: 68fb ldr r3, [r7, #12]
800807a: 071b lsls r3, r3, #28
800807c: 493d ldr r1, [pc, #244] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800807e: 4313 orrs r3, r2
8008080: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8008084: 4b3b ldr r3, [pc, #236] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008086: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
800808a: f023 021f bic.w r2, r3, #31
800808e: 687b ldr r3, [r7, #4]
8008090: 6a5b ldr r3, [r3, #36] ; 0x24
8008092: 3b01 subs r3, #1
8008094: 4937 ldr r1, [pc, #220] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008096: 4313 orrs r3, r2
8008098: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
800809c: 687b ldr r3, [r7, #4]
800809e: 681b ldr r3, [r3, #0]
80080a0: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
80080a4: 2b00 cmp r3, #0
80080a6: d01d beq.n 80080e4 <HAL_RCCEx_PeriphCLKConfig+0x5c8>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
80080a8: 4b32 ldr r3, [pc, #200] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80080aa: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80080ae: 0e1b lsrs r3, r3, #24
80080b0: f003 030f and.w r3, r3, #15
80080b4: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
80080b6: 4b2f ldr r3, [pc, #188] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80080b8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
80080bc: 0f1b lsrs r3, r3, #28
80080be: f003 0307 and.w r3, r3, #7
80080c2: 60fb str r3, [r7, #12]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1);
80080c4: 687b ldr r3, [r7, #4]
80080c6: 685b ldr r3, [r3, #4]
80080c8: 019a lsls r2, r3, #6
80080ca: 687b ldr r3, [r7, #4]
80080cc: 691b ldr r3, [r3, #16]
80080ce: 041b lsls r3, r3, #16
80080d0: 431a orrs r2, r3
80080d2: 693b ldr r3, [r7, #16]
80080d4: 061b lsls r3, r3, #24
80080d6: 431a orrs r2, r3
80080d8: 68fb ldr r3, [r7, #12]
80080da: 071b lsls r3, r3, #28
80080dc: 4925 ldr r1, [pc, #148] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
80080de: 4313 orrs r3, r2
80080e0: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
80080e4: 687b ldr r3, [r7, #4]
80080e6: 681b ldr r3, [r3, #0]
80080e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80080ec: 2b00 cmp r3, #0
80080ee: d011 beq.n 8008114 <HAL_RCCEx_PeriphCLKConfig+0x5f8>
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
80080f0: 687b ldr r3, [r7, #4]
80080f2: 685b ldr r3, [r3, #4]
80080f4: 019a lsls r2, r3, #6
80080f6: 687b ldr r3, [r7, #4]
80080f8: 691b ldr r3, [r3, #16]
80080fa: 041b lsls r3, r3, #16
80080fc: 431a orrs r2, r3
80080fe: 687b ldr r3, [r7, #4]
8008100: 68db ldr r3, [r3, #12]
8008102: 061b lsls r3, r3, #24
8008104: 431a orrs r2, r3
8008106: 687b ldr r3, [r7, #4]
8008108: 689b ldr r3, [r3, #8]
800810a: 071b lsls r3, r3, #28
800810c: 4919 ldr r1, [pc, #100] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800810e: 4313 orrs r3, r2
8008110: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8008114: 4b17 ldr r3, [pc, #92] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008116: 681b ldr r3, [r3, #0]
8008118: 4a16 ldr r2, [pc, #88] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800811a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800811e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8008120: f7fc f9e6 bl 80044f0 <HAL_GetTick>
8008124: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8008126: e008 b.n 800813a <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8008128: f7fc f9e2 bl 80044f0 <HAL_GetTick>
800812c: 4602 mov r2, r0
800812e: 697b ldr r3, [r7, #20]
8008130: 1ad3 subs r3, r2, r3
8008132: 2b64 cmp r3, #100 ; 0x64
8008134: d901 bls.n 800813a <HAL_RCCEx_PeriphCLKConfig+0x61e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8008136: 2303 movs r3, #3
8008138: e0d7 b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
800813a: 4b0e ldr r3, [pc, #56] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
800813c: 681b ldr r3, [r3, #0]
800813e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8008142: 2b00 cmp r3, #0
8008144: d0f0 beq.n 8008128 <HAL_RCCEx_PeriphCLKConfig+0x60c>
}
}
/*-------------------------------------- PLLSAI Configuration ---------------------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */
if(pllsaiused == 1)
8008146: 69bb ldr r3, [r7, #24]
8008148: 2b01 cmp r3, #1
800814a: f040 80cd bne.w 80082e8 <HAL_RCCEx_PeriphCLKConfig+0x7cc>
{
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
800814e: 4b09 ldr r3, [pc, #36] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008150: 681b ldr r3, [r3, #0]
8008152: 4a08 ldr r2, [pc, #32] ; (8008174 <HAL_RCCEx_PeriphCLKConfig+0x658>)
8008154: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8008158: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800815a: f7fc f9c9 bl 80044f0 <HAL_GetTick>
800815e: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8008160: e00a b.n 8008178 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8008162: f7fc f9c5 bl 80044f0 <HAL_GetTick>
8008166: 4602 mov r2, r0
8008168: 697b ldr r3, [r7, #20]
800816a: 1ad3 subs r3, r2, r3
800816c: 2b64 cmp r3, #100 ; 0x64
800816e: d903 bls.n 8008178 <HAL_RCCEx_PeriphCLKConfig+0x65c>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8008170: 2303 movs r3, #3
8008172: e0ba b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
8008174: 40023800 .word 0x40023800
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8008178: 4b5e ldr r3, [pc, #376] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800817a: 681b ldr r3, [r3, #0]
800817c: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8008180: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8008184: d0ed beq.n 8008162 <HAL_RCCEx_PeriphCLKConfig+0x646>
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
8008186: 687b ldr r3, [r7, #4]
8008188: 681b ldr r3, [r3, #0]
800818a: f403 2300 and.w r3, r3, #524288 ; 0x80000
800818e: 2b00 cmp r3, #0
8008190: d003 beq.n 800819a <HAL_RCCEx_PeriphCLKConfig+0x67e>
8008192: 687b ldr r3, [r7, #4]
8008194: 6bdb ldr r3, [r3, #60] ; 0x3c
8008196: 2b00 cmp r3, #0
8008198: d009 beq.n 80081ae <HAL_RCCEx_PeriphCLKConfig+0x692>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
800819a: 687b ldr r3, [r7, #4]
800819c: 681b ldr r3, [r3, #0]
800819e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\
80081a2: 2b00 cmp r3, #0
80081a4: d02e beq.n 8008204 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
80081a6: 687b ldr r3, [r7, #4]
80081a8: 6c1b ldr r3, [r3, #64] ; 0x40
80081aa: 2b00 cmp r3, #0
80081ac: d12a bne.n 8008204 <HAL_RCCEx_PeriphCLKConfig+0x6e8>
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
80081ae: 4b51 ldr r3, [pc, #324] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80081b0: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80081b4: 0c1b lsrs r3, r3, #16
80081b6: f003 0303 and.w r3, r3, #3
80081ba: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
80081bc: 4b4d ldr r3, [pc, #308] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80081be: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80081c2: 0f1b lsrs r3, r3, #28
80081c4: f003 0307 and.w r3, r3, #7
80081c8: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
80081ca: 687b ldr r3, [r7, #4]
80081cc: 695b ldr r3, [r3, #20]
80081ce: 019a lsls r2, r3, #6
80081d0: 693b ldr r3, [r7, #16]
80081d2: 041b lsls r3, r3, #16
80081d4: 431a orrs r2, r3
80081d6: 687b ldr r3, [r7, #4]
80081d8: 699b ldr r3, [r3, #24]
80081da: 061b lsls r3, r3, #24
80081dc: 431a orrs r2, r3
80081de: 68fb ldr r3, [r7, #12]
80081e0: 071b lsls r3, r3, #28
80081e2: 4944 ldr r1, [pc, #272] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80081e4: 4313 orrs r3, r2
80081e6: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
80081ea: 4b42 ldr r3, [pc, #264] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80081ec: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80081f0: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
80081f4: 687b ldr r3, [r7, #4]
80081f6: 6a9b ldr r3, [r3, #40] ; 0x28
80081f8: 3b01 subs r3, #1
80081fa: 021b lsls r3, r3, #8
80081fc: 493d ldr r1, [pc, #244] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80081fe: 4313 orrs r3, r2
8008200: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/
/* In Case of PLLI2S is selected as source clock for CK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP))
8008204: 687b ldr r3, [r7, #4]
8008206: 681b ldr r3, [r3, #0]
8008208: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800820c: 2b00 cmp r3, #0
800820e: d022 beq.n 8008256 <HAL_RCCEx_PeriphCLKConfig+0x73a>
8008210: 687b ldr r3, [r7, #4]
8008212: 6fdb ldr r3, [r3, #124] ; 0x7c
8008214: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000
8008218: d11d bne.n 8008256 <HAL_RCCEx_PeriphCLKConfig+0x73a>
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
800821a: 4b36 ldr r3, [pc, #216] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800821c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8008220: 0e1b lsrs r3, r3, #24
8008222: f003 030f and.w r3, r3, #15
8008226: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8008228: 4b32 ldr r3, [pc, #200] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
800822a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800822e: 0f1b lsrs r3, r3, #28
8008230: f003 0307 and.w r3, r3, #7
8008234: 60fb str r3, [r7, #12]
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
8008236: 687b ldr r3, [r7, #4]
8008238: 695b ldr r3, [r3, #20]
800823a: 019a lsls r2, r3, #6
800823c: 687b ldr r3, [r7, #4]
800823e: 6a1b ldr r3, [r3, #32]
8008240: 041b lsls r3, r3, #16
8008242: 431a orrs r2, r3
8008244: 693b ldr r3, [r7, #16]
8008246: 061b lsls r3, r3, #24
8008248: 431a orrs r2, r3
800824a: 68fb ldr r3, [r7, #12]
800824c: 071b lsls r3, r3, #28
800824e: 4929 ldr r1, [pc, #164] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8008250: 4313 orrs r3, r2
8008252: f8c1 3088 str.w r3, [r1, #136] ; 0x88
}
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
8008256: 687b ldr r3, [r7, #4]
8008258: 681b ldr r3, [r3, #0]
800825a: f003 0308 and.w r3, r3, #8
800825e: 2b00 cmp r3, #0
8008260: d028 beq.n 80082b4 <HAL_RCCEx_PeriphCLKConfig+0x798>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8008262: 4b24 ldr r3, [pc, #144] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8008264: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8008268: 0e1b lsrs r3, r3, #24
800826a: f003 030f and.w r3, r3, #15
800826e: 613b str r3, [r7, #16]
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
8008270: 4b20 ldr r3, [pc, #128] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8008272: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8008276: 0c1b lsrs r3, r3, #16
8008278: f003 0303 and.w r3, r3, #3
800827c: 60fb str r3, [r7, #12]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR);
800827e: 687b ldr r3, [r7, #4]
8008280: 695b ldr r3, [r3, #20]
8008282: 019a lsls r2, r3, #6
8008284: 68fb ldr r3, [r7, #12]
8008286: 041b lsls r3, r3, #16
8008288: 431a orrs r2, r3
800828a: 693b ldr r3, [r7, #16]
800828c: 061b lsls r3, r3, #24
800828e: 431a orrs r2, r3
8008290: 687b ldr r3, [r7, #4]
8008292: 69db ldr r3, [r3, #28]
8008294: 071b lsls r3, r3, #28
8008296: 4917 ldr r1, [pc, #92] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
8008298: 4313 orrs r3, r2
800829a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
800829e: 4b15 ldr r3, [pc, #84] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80082a0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80082a4: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80082a8: 687b ldr r3, [r7, #4]
80082aa: 6adb ldr r3, [r3, #44] ; 0x2c
80082ac: 4911 ldr r1, [pc, #68] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80082ae: 4313 orrs r3, r2
80082b0: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
80082b4: 4b0f ldr r3, [pc, #60] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80082b6: 681b ldr r3, [r3, #0]
80082b8: 4a0e ldr r2, [pc, #56] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80082ba: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80082be: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80082c0: f7fc f916 bl 80044f0 <HAL_GetTick>
80082c4: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
80082c6: e008 b.n 80082da <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80082c8: f7fc f912 bl 80044f0 <HAL_GetTick>
80082cc: 4602 mov r2, r0
80082ce: 697b ldr r3, [r7, #20]
80082d0: 1ad3 subs r3, r2, r3
80082d2: 2b64 cmp r3, #100 ; 0x64
80082d4: d901 bls.n 80082da <HAL_RCCEx_PeriphCLKConfig+0x7be>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80082d6: 2303 movs r3, #3
80082d8: e007 b.n 80082ea <HAL_RCCEx_PeriphCLKConfig+0x7ce>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
80082da: 4b06 ldr r3, [pc, #24] ; (80082f4 <HAL_RCCEx_PeriphCLKConfig+0x7d8>)
80082dc: 681b ldr r3, [r3, #0]
80082de: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
80082e2: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
80082e6: d1ef bne.n 80082c8 <HAL_RCCEx_PeriphCLKConfig+0x7ac>
}
}
}
return HAL_OK;
80082e8: 2300 movs r3, #0
}
80082ea: 4618 mov r0, r3
80082ec: 3720 adds r7, #32
80082ee: 46bd mov sp, r7
80082f0: bd80 pop {r7, pc}
80082f2: bf00 nop
80082f4: 40023800 .word 0x40023800
080082f8 <HAL_RTC_Init>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
80082f8: b580 push {r7, lr}
80082fa: b082 sub sp, #8
80082fc: af00 add r7, sp, #0
80082fe: 6078 str r0, [r7, #4]
/* Check the RTC peripheral state */
if(hrtc == NULL)
8008300: 687b ldr r3, [r7, #4]
8008302: 2b00 cmp r3, #0
8008304: d101 bne.n 800830a <HAL_RTC_Init+0x12>
{
return HAL_ERROR;
8008306: 2301 movs r3, #1
8008308: e06b b.n 80083e2 <HAL_RTC_Init+0xea>
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
#else
if(hrtc->State == HAL_RTC_STATE_RESET)
800830a: 687b ldr r3, [r7, #4]
800830c: 7f5b ldrb r3, [r3, #29]
800830e: b2db uxtb r3, r3
8008310: 2b00 cmp r3, #0
8008312: d105 bne.n 8008320 <HAL_RTC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
8008314: 687b ldr r3, [r7, #4]
8008316: 2200 movs r2, #0
8008318: 771a strb r2, [r3, #28]
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
800831a: 6878 ldr r0, [r7, #4]
800831c: f7fb fd14 bl 8003d48 <HAL_RTC_MspInit>
}
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
8008320: 687b ldr r3, [r7, #4]
8008322: 2202 movs r2, #2
8008324: 775a strb r2, [r3, #29]
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
8008326: 687b ldr r3, [r7, #4]
8008328: 681b ldr r3, [r3, #0]
800832a: 22ca movs r2, #202 ; 0xca
800832c: 625a str r2, [r3, #36] ; 0x24
800832e: 687b ldr r3, [r7, #4]
8008330: 681b ldr r3, [r3, #0]
8008332: 2253 movs r2, #83 ; 0x53
8008334: 625a str r2, [r3, #36] ; 0x24
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
8008336: 6878 ldr r0, [r7, #4]
8008338: f000 fb00 bl 800893c <RTC_EnterInitMode>
800833c: 4603 mov r3, r0
800833e: 2b00 cmp r3, #0
8008340: d008 beq.n 8008354 <HAL_RTC_Init+0x5c>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008342: 687b ldr r3, [r7, #4]
8008344: 681b ldr r3, [r3, #0]
8008346: 22ff movs r2, #255 ; 0xff
8008348: 625a str r2, [r3, #36] ; 0x24
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
800834a: 687b ldr r3, [r7, #4]
800834c: 2204 movs r2, #4
800834e: 775a strb r2, [r3, #29]
return HAL_ERROR;
8008350: 2301 movs r3, #1
8008352: e046 b.n 80083e2 <HAL_RTC_Init+0xea>
}
else
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
8008354: 687b ldr r3, [r7, #4]
8008356: 681b ldr r3, [r3, #0]
8008358: 6899 ldr r1, [r3, #8]
800835a: 687b ldr r3, [r7, #4]
800835c: 681a ldr r2, [r3, #0]
800835e: 4b23 ldr r3, [pc, #140] ; (80083ec <HAL_RTC_Init+0xf4>)
8008360: 400b ands r3, r1
8008362: 6093 str r3, [r2, #8]
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
8008364: 687b ldr r3, [r7, #4]
8008366: 681b ldr r3, [r3, #0]
8008368: 6899 ldr r1, [r3, #8]
800836a: 687b ldr r3, [r7, #4]
800836c: 685a ldr r2, [r3, #4]
800836e: 687b ldr r3, [r7, #4]
8008370: 691b ldr r3, [r3, #16]
8008372: 431a orrs r2, r3
8008374: 687b ldr r3, [r7, #4]
8008376: 695b ldr r3, [r3, #20]
8008378: 431a orrs r2, r3
800837a: 687b ldr r3, [r7, #4]
800837c: 681b ldr r3, [r3, #0]
800837e: 430a orrs r2, r1
8008380: 609a str r2, [r3, #8]
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
8008382: 687b ldr r3, [r7, #4]
8008384: 681b ldr r3, [r3, #0]
8008386: 687a ldr r2, [r7, #4]
8008388: 68d2 ldr r2, [r2, #12]
800838a: 611a str r2, [r3, #16]
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
800838c: 687b ldr r3, [r7, #4]
800838e: 681b ldr r3, [r3, #0]
8008390: 6919 ldr r1, [r3, #16]
8008392: 687b ldr r3, [r7, #4]
8008394: 689b ldr r3, [r3, #8]
8008396: 041a lsls r2, r3, #16
8008398: 687b ldr r3, [r7, #4]
800839a: 681b ldr r3, [r3, #0]
800839c: 430a orrs r2, r1
800839e: 611a str r2, [r3, #16]
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
80083a0: 687b ldr r3, [r7, #4]
80083a2: 681b ldr r3, [r3, #0]
80083a4: 68da ldr r2, [r3, #12]
80083a6: 687b ldr r3, [r7, #4]
80083a8: 681b ldr r3, [r3, #0]
80083aa: f022 0280 bic.w r2, r2, #128 ; 0x80
80083ae: 60da str r2, [r3, #12]
hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE;
80083b0: 687b ldr r3, [r7, #4]
80083b2: 681b ldr r3, [r3, #0]
80083b4: 6cda ldr r2, [r3, #76] ; 0x4c
80083b6: 687b ldr r3, [r7, #4]
80083b8: 681b ldr r3, [r3, #0]
80083ba: f022 0208 bic.w r2, r2, #8
80083be: 64da str r2, [r3, #76] ; 0x4c
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
80083c0: 687b ldr r3, [r7, #4]
80083c2: 681b ldr r3, [r3, #0]
80083c4: 6cd9 ldr r1, [r3, #76] ; 0x4c
80083c6: 687b ldr r3, [r7, #4]
80083c8: 699a ldr r2, [r3, #24]
80083ca: 687b ldr r3, [r7, #4]
80083cc: 681b ldr r3, [r3, #0]
80083ce: 430a orrs r2, r1
80083d0: 64da str r2, [r3, #76] ; 0x4c
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
80083d2: 687b ldr r3, [r7, #4]
80083d4: 681b ldr r3, [r3, #0]
80083d6: 22ff movs r2, #255 ; 0xff
80083d8: 625a str r2, [r3, #36] ; 0x24
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
80083da: 687b ldr r3, [r7, #4]
80083dc: 2201 movs r2, #1
80083de: 775a strb r2, [r3, #29]
return HAL_OK;
80083e0: 2300 movs r3, #0
}
}
80083e2: 4618 mov r0, r3
80083e4: 3708 adds r7, #8
80083e6: 46bd mov sp, r7
80083e8: bd80 pop {r7, pc}
80083ea: bf00 nop
80083ec: ff8fffbf .word 0xff8fffbf
080083f0 <HAL_RTC_SetTime>:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
80083f0: b590 push {r4, r7, lr}
80083f2: b087 sub sp, #28
80083f4: af00 add r7, sp, #0
80083f6: 60f8 str r0, [r7, #12]
80083f8: 60b9 str r1, [r7, #8]
80083fa: 607a str r2, [r7, #4]
uint32_t tmpreg = 0;
80083fc: 2300 movs r3, #0
80083fe: 617b str r3, [r7, #20]
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
/* Process Locked */
__HAL_LOCK(hrtc);
8008400: 68fb ldr r3, [r7, #12]
8008402: 7f1b ldrb r3, [r3, #28]
8008404: 2b01 cmp r3, #1
8008406: d101 bne.n 800840c <HAL_RTC_SetTime+0x1c>
8008408: 2302 movs r3, #2
800840a: e0a8 b.n 800855e <HAL_RTC_SetTime+0x16e>
800840c: 68fb ldr r3, [r7, #12]
800840e: 2201 movs r2, #1
8008410: 771a strb r2, [r3, #28]
hrtc->State = HAL_RTC_STATE_BUSY;
8008412: 68fb ldr r3, [r7, #12]
8008414: 2202 movs r2, #2
8008416: 775a strb r2, [r3, #29]
if(Format == RTC_FORMAT_BIN)
8008418: 687b ldr r3, [r7, #4]
800841a: 2b00 cmp r3, #0
800841c: d126 bne.n 800846c <HAL_RTC_SetTime+0x7c>
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
800841e: 68fb ldr r3, [r7, #12]
8008420: 681b ldr r3, [r3, #0]
8008422: 689b ldr r3, [r3, #8]
8008424: f003 0340 and.w r3, r3, #64 ; 0x40
8008428: 2b00 cmp r3, #0
800842a: d102 bne.n 8008432 <HAL_RTC_SetTime+0x42>
assert_param(IS_RTC_HOUR12(sTime->Hours));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
{
sTime->TimeFormat = 0x00;
800842c: 68bb ldr r3, [r7, #8]
800842e: 2200 movs r2, #0
8008430: 731a strb r2, [r3, #12]
assert_param(IS_RTC_HOUR24(sTime->Hours));
}
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
8008432: 68bb ldr r3, [r7, #8]
8008434: 781b ldrb r3, [r3, #0]
8008436: 4618 mov r0, r3
8008438: f000 faac bl 8008994 <RTC_ByteToBcd2>
800843c: 4603 mov r3, r0
800843e: 041c lsls r4, r3, #16
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
8008440: 68bb ldr r3, [r7, #8]
8008442: 785b ldrb r3, [r3, #1]
8008444: 4618 mov r0, r3
8008446: f000 faa5 bl 8008994 <RTC_ByteToBcd2>
800844a: 4603 mov r3, r0
800844c: 021b lsls r3, r3, #8
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
800844e: 431c orrs r4, r3
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
8008450: 68bb ldr r3, [r7, #8]
8008452: 789b ldrb r3, [r3, #2]
8008454: 4618 mov r0, r3
8008456: f000 fa9d bl 8008994 <RTC_ByteToBcd2>
800845a: 4603 mov r3, r0
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
800845c: ea44 0203 orr.w r2, r4, r3
(((uint32_t)sTime->TimeFormat) << 16));
8008460: 68bb ldr r3, [r7, #8]
8008462: 7b1b ldrb r3, [r3, #12]
8008464: 041b lsls r3, r3, #16
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
8008466: 4313 orrs r3, r2
8008468: 617b str r3, [r7, #20]
800846a: e018 b.n 800849e <HAL_RTC_SetTime+0xae>
}
else
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
800846c: 68fb ldr r3, [r7, #12]
800846e: 681b ldr r3, [r3, #0]
8008470: 689b ldr r3, [r3, #8]
8008472: f003 0340 and.w r3, r3, #64 ; 0x40
8008476: 2b00 cmp r3, #0
8008478: d102 bne.n 8008480 <HAL_RTC_SetTime+0x90>
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
}
else
{
sTime->TimeFormat = 0x00;
800847a: 68bb ldr r3, [r7, #8]
800847c: 2200 movs r2, #0
800847e: 731a strb r2, [r3, #12]
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
8008480: 68bb ldr r3, [r7, #8]
8008482: 781b ldrb r3, [r3, #0]
8008484: 041a lsls r2, r3, #16
((uint32_t)(sTime->Minutes) << 8) | \
8008486: 68bb ldr r3, [r7, #8]
8008488: 785b ldrb r3, [r3, #1]
800848a: 021b lsls r3, r3, #8
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
800848c: 4313 orrs r3, r2
((uint32_t)sTime->Seconds) | \
800848e: 68ba ldr r2, [r7, #8]
8008490: 7892 ldrb r2, [r2, #2]
((uint32_t)(sTime->Minutes) << 8) | \
8008492: 431a orrs r2, r3
((uint32_t)(sTime->TimeFormat) << 16));
8008494: 68bb ldr r3, [r7, #8]
8008496: 7b1b ldrb r3, [r3, #12]
8008498: 041b lsls r3, r3, #16
tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
800849a: 4313 orrs r3, r2
800849c: 617b str r3, [r7, #20]
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
800849e: 68fb ldr r3, [r7, #12]
80084a0: 681b ldr r3, [r3, #0]
80084a2: 22ca movs r2, #202 ; 0xca
80084a4: 625a str r2, [r3, #36] ; 0x24
80084a6: 68fb ldr r3, [r7, #12]
80084a8: 681b ldr r3, [r3, #0]
80084aa: 2253 movs r2, #83 ; 0x53
80084ac: 625a str r2, [r3, #36] ; 0x24
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
80084ae: 68f8 ldr r0, [r7, #12]
80084b0: f000 fa44 bl 800893c <RTC_EnterInitMode>
80084b4: 4603 mov r3, r0
80084b6: 2b00 cmp r3, #0
80084b8: d00b beq.n 80084d2 <HAL_RTC_SetTime+0xe2>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
80084ba: 68fb ldr r3, [r7, #12]
80084bc: 681b ldr r3, [r3, #0]
80084be: 22ff movs r2, #255 ; 0xff
80084c0: 625a str r2, [r3, #36] ; 0x24
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
80084c2: 68fb ldr r3, [r7, #12]
80084c4: 2204 movs r2, #4
80084c6: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
80084c8: 68fb ldr r3, [r7, #12]
80084ca: 2200 movs r2, #0
80084cc: 771a strb r2, [r3, #28]
return HAL_ERROR;
80084ce: 2301 movs r3, #1
80084d0: e045 b.n 800855e <HAL_RTC_SetTime+0x16e>
}
else
{
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
80084d2: 68fb ldr r3, [r7, #12]
80084d4: 681a ldr r2, [r3, #0]
80084d6: 6979 ldr r1, [r7, #20]
80084d8: 4b23 ldr r3, [pc, #140] ; (8008568 <HAL_RTC_SetTime+0x178>)
80084da: 400b ands r3, r1
80084dc: 6013 str r3, [r2, #0]
/* Clear the bits to be configured */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
80084de: 68fb ldr r3, [r7, #12]
80084e0: 681b ldr r3, [r3, #0]
80084e2: 689a ldr r2, [r3, #8]
80084e4: 68fb ldr r3, [r7, #12]
80084e6: 681b ldr r3, [r3, #0]
80084e8: f422 2280 bic.w r2, r2, #262144 ; 0x40000
80084ec: 609a str r2, [r3, #8]
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
80084ee: 68fb ldr r3, [r7, #12]
80084f0: 681b ldr r3, [r3, #0]
80084f2: 6899 ldr r1, [r3, #8]
80084f4: 68bb ldr r3, [r7, #8]
80084f6: 691a ldr r2, [r3, #16]
80084f8: 68bb ldr r3, [r7, #8]
80084fa: 695b ldr r3, [r3, #20]
80084fc: 431a orrs r2, r3
80084fe: 68fb ldr r3, [r7, #12]
8008500: 681b ldr r3, [r3, #0]
8008502: 430a orrs r2, r1
8008504: 609a str r2, [r3, #8]
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
8008506: 68fb ldr r3, [r7, #12]
8008508: 681b ldr r3, [r3, #0]
800850a: 68da ldr r2, [r3, #12]
800850c: 68fb ldr r3, [r7, #12]
800850e: 681b ldr r3, [r3, #0]
8008510: f022 0280 bic.w r2, r2, #128 ; 0x80
8008514: 60da str r2, [r3, #12]
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
8008516: 68fb ldr r3, [r7, #12]
8008518: 681b ldr r3, [r3, #0]
800851a: 689b ldr r3, [r3, #8]
800851c: f003 0320 and.w r3, r3, #32
8008520: 2b00 cmp r3, #0
8008522: d111 bne.n 8008548 <HAL_RTC_SetTime+0x158>
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
8008524: 68f8 ldr r0, [r7, #12]
8008526: f000 f9e1 bl 80088ec <HAL_RTC_WaitForSynchro>
800852a: 4603 mov r3, r0
800852c: 2b00 cmp r3, #0
800852e: d00b beq.n 8008548 <HAL_RTC_SetTime+0x158>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008530: 68fb ldr r3, [r7, #12]
8008532: 681b ldr r3, [r3, #0]
8008534: 22ff movs r2, #255 ; 0xff
8008536: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_ERROR;
8008538: 68fb ldr r3, [r7, #12]
800853a: 2204 movs r2, #4
800853c: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
800853e: 68fb ldr r3, [r7, #12]
8008540: 2200 movs r2, #0
8008542: 771a strb r2, [r3, #28]
return HAL_ERROR;
8008544: 2301 movs r3, #1
8008546: e00a b.n 800855e <HAL_RTC_SetTime+0x16e>
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008548: 68fb ldr r3, [r7, #12]
800854a: 681b ldr r3, [r3, #0]
800854c: 22ff movs r2, #255 ; 0xff
800854e: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_READY;
8008550: 68fb ldr r3, [r7, #12]
8008552: 2201 movs r2, #1
8008554: 775a strb r2, [r3, #29]
__HAL_UNLOCK(hrtc);
8008556: 68fb ldr r3, [r7, #12]
8008558: 2200 movs r2, #0
800855a: 771a strb r2, [r3, #28]
return HAL_OK;
800855c: 2300 movs r3, #0
}
}
800855e: 4618 mov r0, r3
8008560: 371c adds r7, #28
8008562: 46bd mov sp, r7
8008564: bd90 pop {r4, r7, pc}
8008566: bf00 nop
8008568: 007f7f7f .word 0x007f7f7f
0800856c <HAL_RTC_SetDate>:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
800856c: b590 push {r4, r7, lr}
800856e: b087 sub sp, #28
8008570: af00 add r7, sp, #0
8008572: 60f8 str r0, [r7, #12]
8008574: 60b9 str r1, [r7, #8]
8008576: 607a str r2, [r7, #4]
uint32_t datetmpreg = 0;
8008578: 2300 movs r3, #0
800857a: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
/* Process Locked */
__HAL_LOCK(hrtc);
800857c: 68fb ldr r3, [r7, #12]
800857e: 7f1b ldrb r3, [r3, #28]
8008580: 2b01 cmp r3, #1
8008582: d101 bne.n 8008588 <HAL_RTC_SetDate+0x1c>
8008584: 2302 movs r3, #2
8008586: e092 b.n 80086ae <HAL_RTC_SetDate+0x142>
8008588: 68fb ldr r3, [r7, #12]
800858a: 2201 movs r2, #1
800858c: 771a strb r2, [r3, #28]
hrtc->State = HAL_RTC_STATE_BUSY;
800858e: 68fb ldr r3, [r7, #12]
8008590: 2202 movs r2, #2
8008592: 775a strb r2, [r3, #29]
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
8008594: 687b ldr r3, [r7, #4]
8008596: 2b00 cmp r3, #0
8008598: d10e bne.n 80085b8 <HAL_RTC_SetDate+0x4c>
800859a: 68bb ldr r3, [r7, #8]
800859c: 785b ldrb r3, [r3, #1]
800859e: f003 0310 and.w r3, r3, #16
80085a2: 2b00 cmp r3, #0
80085a4: d008 beq.n 80085b8 <HAL_RTC_SetDate+0x4c>
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
80085a6: 68bb ldr r3, [r7, #8]
80085a8: 785b ldrb r3, [r3, #1]
80085aa: f023 0310 bic.w r3, r3, #16
80085ae: b2db uxtb r3, r3
80085b0: 330a adds r3, #10
80085b2: b2da uxtb r2, r3
80085b4: 68bb ldr r3, [r7, #8]
80085b6: 705a strb r2, [r3, #1]
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
if(Format == RTC_FORMAT_BIN)
80085b8: 687b ldr r3, [r7, #4]
80085ba: 2b00 cmp r3, #0
80085bc: d11c bne.n 80085f8 <HAL_RTC_SetDate+0x8c>
{
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
80085be: 68bb ldr r3, [r7, #8]
80085c0: 78db ldrb r3, [r3, #3]
80085c2: 4618 mov r0, r3
80085c4: f000 f9e6 bl 8008994 <RTC_ByteToBcd2>
80085c8: 4603 mov r3, r0
80085ca: 041c lsls r4, r3, #16
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
80085cc: 68bb ldr r3, [r7, #8]
80085ce: 785b ldrb r3, [r3, #1]
80085d0: 4618 mov r0, r3
80085d2: f000 f9df bl 8008994 <RTC_ByteToBcd2>
80085d6: 4603 mov r3, r0
80085d8: 021b lsls r3, r3, #8
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
80085da: 431c orrs r4, r3
((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
80085dc: 68bb ldr r3, [r7, #8]
80085de: 789b ldrb r3, [r3, #2]
80085e0: 4618 mov r0, r3
80085e2: f000 f9d7 bl 8008994 <RTC_ByteToBcd2>
80085e6: 4603 mov r3, r0
((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
80085e8: ea44 0203 orr.w r2, r4, r3
((uint32_t)sDate->WeekDay << 13));
80085ec: 68bb ldr r3, [r7, #8]
80085ee: 781b ldrb r3, [r3, #0]
80085f0: 035b lsls r3, r3, #13
datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
80085f2: 4313 orrs r3, r2
80085f4: 617b str r3, [r7, #20]
80085f6: e00e b.n 8008616 <HAL_RTC_SetDate+0xaa>
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
80085f8: 68bb ldr r3, [r7, #8]
80085fa: 78db ldrb r3, [r3, #3]
80085fc: 041a lsls r2, r3, #16
(((uint32_t)sDate->Month) << 8) | \
80085fe: 68bb ldr r3, [r7, #8]
8008600: 785b ldrb r3, [r3, #1]
8008602: 021b lsls r3, r3, #8
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
8008604: 4313 orrs r3, r2
((uint32_t)sDate->Date) | \
8008606: 68ba ldr r2, [r7, #8]
8008608: 7892 ldrb r2, [r2, #2]
(((uint32_t)sDate->Month) << 8) | \
800860a: 431a orrs r2, r3
(((uint32_t)sDate->WeekDay) << 13));
800860c: 68bb ldr r3, [r7, #8]
800860e: 781b ldrb r3, [r3, #0]
8008610: 035b lsls r3, r3, #13
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
8008612: 4313 orrs r3, r2
8008614: 617b str r3, [r7, #20]
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
8008616: 68fb ldr r3, [r7, #12]
8008618: 681b ldr r3, [r3, #0]
800861a: 22ca movs r2, #202 ; 0xca
800861c: 625a str r2, [r3, #36] ; 0x24
800861e: 68fb ldr r3, [r7, #12]
8008620: 681b ldr r3, [r3, #0]
8008622: 2253 movs r2, #83 ; 0x53
8008624: 625a str r2, [r3, #36] ; 0x24
/* Set Initialization mode */
if(RTC_EnterInitMode(hrtc) != HAL_OK)
8008626: 68f8 ldr r0, [r7, #12]
8008628: f000 f988 bl 800893c <RTC_EnterInitMode>
800862c: 4603 mov r3, r0
800862e: 2b00 cmp r3, #0
8008630: d00b beq.n 800864a <HAL_RTC_SetDate+0xde>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008632: 68fb ldr r3, [r7, #12]
8008634: 681b ldr r3, [r3, #0]
8008636: 22ff movs r2, #255 ; 0xff
8008638: 625a str r2, [r3, #36] ; 0x24
/* Set RTC state*/
hrtc->State = HAL_RTC_STATE_ERROR;
800863a: 68fb ldr r3, [r7, #12]
800863c: 2204 movs r2, #4
800863e: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
8008640: 68fb ldr r3, [r7, #12]
8008642: 2200 movs r2, #0
8008644: 771a strb r2, [r3, #28]
return HAL_ERROR;
8008646: 2301 movs r3, #1
8008648: e031 b.n 80086ae <HAL_RTC_SetDate+0x142>
}
else
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
800864a: 68fb ldr r3, [r7, #12]
800864c: 681a ldr r2, [r3, #0]
800864e: 6979 ldr r1, [r7, #20]
8008650: 4b19 ldr r3, [pc, #100] ; (80086b8 <HAL_RTC_SetDate+0x14c>)
8008652: 400b ands r3, r1
8008654: 6053 str r3, [r2, #4]
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
8008656: 68fb ldr r3, [r7, #12]
8008658: 681b ldr r3, [r3, #0]
800865a: 68da ldr r2, [r3, #12]
800865c: 68fb ldr r3, [r7, #12]
800865e: 681b ldr r3, [r3, #0]
8008660: f022 0280 bic.w r2, r2, #128 ; 0x80
8008664: 60da str r2, [r3, #12]
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
8008666: 68fb ldr r3, [r7, #12]
8008668: 681b ldr r3, [r3, #0]
800866a: 689b ldr r3, [r3, #8]
800866c: f003 0320 and.w r3, r3, #32
8008670: 2b00 cmp r3, #0
8008672: d111 bne.n 8008698 <HAL_RTC_SetDate+0x12c>
{
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
8008674: 68f8 ldr r0, [r7, #12]
8008676: f000 f939 bl 80088ec <HAL_RTC_WaitForSynchro>
800867a: 4603 mov r3, r0
800867c: 2b00 cmp r3, #0
800867e: d00b beq.n 8008698 <HAL_RTC_SetDate+0x12c>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008680: 68fb ldr r3, [r7, #12]
8008682: 681b ldr r3, [r3, #0]
8008684: 22ff movs r2, #255 ; 0xff
8008686: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_ERROR;
8008688: 68fb ldr r3, [r7, #12]
800868a: 2204 movs r2, #4
800868c: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
800868e: 68fb ldr r3, [r7, #12]
8008690: 2200 movs r2, #0
8008692: 771a strb r2, [r3, #28]
return HAL_ERROR;
8008694: 2301 movs r3, #1
8008696: e00a b.n 80086ae <HAL_RTC_SetDate+0x142>
}
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008698: 68fb ldr r3, [r7, #12]
800869a: 681b ldr r3, [r3, #0]
800869c: 22ff movs r2, #255 ; 0xff
800869e: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_READY ;
80086a0: 68fb ldr r3, [r7, #12]
80086a2: 2201 movs r2, #1
80086a4: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
80086a6: 68fb ldr r3, [r7, #12]
80086a8: 2200 movs r2, #0
80086aa: 771a strb r2, [r3, #28]
return HAL_OK;
80086ac: 2300 movs r3, #0
}
}
80086ae: 4618 mov r0, r3
80086b0: 371c adds r7, #28
80086b2: 46bd mov sp, r7
80086b4: bd90 pop {r4, r7, pc}
80086b6: bf00 nop
80086b8: 00ffff3f .word 0x00ffff3f
080086bc <HAL_RTC_SetAlarm>:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
80086bc: b590 push {r4, r7, lr}
80086be: b089 sub sp, #36 ; 0x24
80086c0: af00 add r7, sp, #0
80086c2: 60f8 str r0, [r7, #12]
80086c4: 60b9 str r1, [r7, #8]
80086c6: 607a str r2, [r7, #4]
uint32_t tickstart = 0;
80086c8: 2300 movs r3, #0
80086ca: 61bb str r3, [r7, #24]
uint32_t tmpreg = 0, subsecondtmpreg = 0;
80086cc: 2300 movs r3, #0
80086ce: 61fb str r3, [r7, #28]
80086d0: 2300 movs r3, #0
80086d2: 617b str r3, [r7, #20]
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
/* Process Locked */
__HAL_LOCK(hrtc);
80086d4: 68fb ldr r3, [r7, #12]
80086d6: 7f1b ldrb r3, [r3, #28]
80086d8: 2b01 cmp r3, #1
80086da: d101 bne.n 80086e0 <HAL_RTC_SetAlarm+0x24>
80086dc: 2302 movs r3, #2
80086de: e101 b.n 80088e4 <HAL_RTC_SetAlarm+0x228>
80086e0: 68fb ldr r3, [r7, #12]
80086e2: 2201 movs r2, #1
80086e4: 771a strb r2, [r3, #28]
hrtc->State = HAL_RTC_STATE_BUSY;
80086e6: 68fb ldr r3, [r7, #12]
80086e8: 2202 movs r2, #2
80086ea: 775a strb r2, [r3, #29]
if(Format == RTC_FORMAT_BIN)
80086ec: 687b ldr r3, [r7, #4]
80086ee: 2b00 cmp r3, #0
80086f0: d137 bne.n 8008762 <HAL_RTC_SetAlarm+0xa6>
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
80086f2: 68fb ldr r3, [r7, #12]
80086f4: 681b ldr r3, [r3, #0]
80086f6: 689b ldr r3, [r3, #8]
80086f8: f003 0340 and.w r3, r3, #64 ; 0x40
80086fc: 2b00 cmp r3, #0
80086fe: d102 bne.n 8008706 <HAL_RTC_SetAlarm+0x4a>
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
8008700: 68bb ldr r3, [r7, #8]
8008702: 2200 movs r2, #0
8008704: 731a strb r2, [r3, #12]
else
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
8008706: 68bb ldr r3, [r7, #8]
8008708: 781b ldrb r3, [r3, #0]
800870a: 4618 mov r0, r3
800870c: f000 f942 bl 8008994 <RTC_ByteToBcd2>
8008710: 4603 mov r3, r0
8008712: 041c lsls r4, r3, #16
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
8008714: 68bb ldr r3, [r7, #8]
8008716: 785b ldrb r3, [r3, #1]
8008718: 4618 mov r0, r3
800871a: f000 f93b bl 8008994 <RTC_ByteToBcd2>
800871e: 4603 mov r3, r0
8008720: 021b lsls r3, r3, #8
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
8008722: 431c orrs r4, r3
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
8008724: 68bb ldr r3, [r7, #8]
8008726: 789b ldrb r3, [r3, #2]
8008728: 4618 mov r0, r3
800872a: f000 f933 bl 8008994 <RTC_ByteToBcd2>
800872e: 4603 mov r3, r0
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
8008730: ea44 0203 orr.w r2, r4, r3
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
8008734: 68bb ldr r3, [r7, #8]
8008736: 7b1b ldrb r3, [r3, #12]
8008738: 041b lsls r3, r3, #16
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
800873a: ea42 0403 orr.w r4, r2, r3
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
800873e: 68bb ldr r3, [r7, #8]
8008740: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8008744: 4618 mov r0, r3
8008746: f000 f925 bl 8008994 <RTC_ByteToBcd2>
800874a: 4603 mov r3, r0
800874c: 061b lsls r3, r3, #24
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
800874e: ea44 0203 orr.w r2, r4, r3
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
8008752: 68bb ldr r3, [r7, #8]
8008754: 6a1b ldr r3, [r3, #32]
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
8008756: 431a orrs r2, r3
((uint32_t)sAlarm->AlarmMask));
8008758: 68bb ldr r3, [r7, #8]
800875a: 699b ldr r3, [r3, #24]
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
800875c: 4313 orrs r3, r2
800875e: 61fb str r3, [r7, #28]
8008760: e023 b.n 80087aa <HAL_RTC_SetAlarm+0xee>
}
else
{
if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
8008762: 68fb ldr r3, [r7, #12]
8008764: 681b ldr r3, [r3, #0]
8008766: 689b ldr r3, [r3, #8]
8008768: f003 0340 and.w r3, r3, #64 ; 0x40
800876c: 2b00 cmp r3, #0
800876e: d102 bne.n 8008776 <HAL_RTC_SetAlarm+0xba>
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
}
else
{
sAlarm->AlarmTime.TimeFormat = 0x00;
8008770: 68bb ldr r3, [r7, #8]
8008772: 2200 movs r2, #0
8008774: 731a strb r2, [r3, #12]
else
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
8008776: 68bb ldr r3, [r7, #8]
8008778: 781b ldrb r3, [r3, #0]
800877a: 041a lsls r2, r3, #16
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
800877c: 68bb ldr r3, [r7, #8]
800877e: 785b ldrb r3, [r3, #1]
8008780: 021b lsls r3, r3, #8
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
8008782: 4313 orrs r3, r2
((uint32_t) sAlarm->AlarmTime.Seconds) | \
8008784: 68ba ldr r2, [r7, #8]
8008786: 7892 ldrb r2, [r2, #2]
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
8008788: 431a orrs r2, r3
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
800878a: 68bb ldr r3, [r7, #8]
800878c: 7b1b ldrb r3, [r3, #12]
800878e: 041b lsls r3, r3, #16
((uint32_t) sAlarm->AlarmTime.Seconds) | \
8008790: 431a orrs r2, r3
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
8008792: 68bb ldr r3, [r7, #8]
8008794: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
8008798: 061b lsls r3, r3, #24
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
800879a: 431a orrs r2, r3
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
800879c: 68bb ldr r3, [r7, #8]
800879e: 6a1b ldr r3, [r3, #32]
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
80087a0: 431a orrs r2, r3
((uint32_t)sAlarm->AlarmMask));
80087a2: 68bb ldr r3, [r7, #8]
80087a4: 699b ldr r3, [r3, #24]
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
80087a6: 4313 orrs r3, r2
80087a8: 61fb str r3, [r7, #28]
}
/* Configure the Alarm A or Alarm B Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
80087aa: 68bb ldr r3, [r7, #8]
80087ac: 685a ldr r2, [r3, #4]
80087ae: 68bb ldr r3, [r7, #8]
80087b0: 69db ldr r3, [r3, #28]
80087b2: 4313 orrs r3, r2
80087b4: 617b str r3, [r7, #20]
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
80087b6: 68fb ldr r3, [r7, #12]
80087b8: 681b ldr r3, [r3, #0]
80087ba: 22ca movs r2, #202 ; 0xca
80087bc: 625a str r2, [r3, #36] ; 0x24
80087be: 68fb ldr r3, [r7, #12]
80087c0: 681b ldr r3, [r3, #0]
80087c2: 2253 movs r2, #83 ; 0x53
80087c4: 625a str r2, [r3, #36] ; 0x24
/* Configure the Alarm register */
if(sAlarm->Alarm == RTC_ALARM_A)
80087c6: 68bb ldr r3, [r7, #8]
80087c8: 6a9b ldr r3, [r3, #40] ; 0x28
80087ca: f5b3 7f80 cmp.w r3, #256 ; 0x100
80087ce: d13f bne.n 8008850 <HAL_RTC_SetAlarm+0x194>
{
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(hrtc);
80087d0: 68fb ldr r3, [r7, #12]
80087d2: 681b ldr r3, [r3, #0]
80087d4: 689a ldr r2, [r3, #8]
80087d6: 68fb ldr r3, [r7, #12]
80087d8: 681b ldr r3, [r3, #0]
80087da: f422 7280 bic.w r2, r2, #256 ; 0x100
80087de: 609a str r2, [r3, #8]
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
80087e0: 68fb ldr r3, [r7, #12]
80087e2: 681b ldr r3, [r3, #0]
80087e4: 689a ldr r2, [r3, #8]
80087e6: 68fb ldr r3, [r7, #12]
80087e8: 681b ldr r3, [r3, #0]
80087ea: f422 5280 bic.w r2, r2, #4096 ; 0x1000
80087ee: 609a str r2, [r3, #8]
/* Get tick */
tickstart = HAL_GetTick();
80087f0: f7fb fe7e bl 80044f0 <HAL_GetTick>
80087f4: 61b8 str r0, [r7, #24]
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
80087f6: e013 b.n 8008820 <HAL_RTC_SetAlarm+0x164>
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
80087f8: f7fb fe7a bl 80044f0 <HAL_GetTick>
80087fc: 4602 mov r2, r0
80087fe: 69bb ldr r3, [r7, #24]
8008800: 1ad3 subs r3, r2, r3
8008802: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008806: d90b bls.n 8008820 <HAL_RTC_SetAlarm+0x164>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008808: 68fb ldr r3, [r7, #12]
800880a: 681b ldr r3, [r3, #0]
800880c: 22ff movs r2, #255 ; 0xff
800880e: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_TIMEOUT;
8008810: 68fb ldr r3, [r7, #12]
8008812: 2203 movs r2, #3
8008814: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
8008816: 68fb ldr r3, [r7, #12]
8008818: 2200 movs r2, #0
800881a: 771a strb r2, [r3, #28]
return HAL_TIMEOUT;
800881c: 2303 movs r3, #3
800881e: e061 b.n 80088e4 <HAL_RTC_SetAlarm+0x228>
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
8008820: 68fb ldr r3, [r7, #12]
8008822: 681b ldr r3, [r3, #0]
8008824: 68db ldr r3, [r3, #12]
8008826: f003 0301 and.w r3, r3, #1
800882a: 2b00 cmp r3, #0
800882c: d0e4 beq.n 80087f8 <HAL_RTC_SetAlarm+0x13c>
}
}
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
800882e: 68fb ldr r3, [r7, #12]
8008830: 681b ldr r3, [r3, #0]
8008832: 69fa ldr r2, [r7, #28]
8008834: 61da str r2, [r3, #28]
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
8008836: 68fb ldr r3, [r7, #12]
8008838: 681b ldr r3, [r3, #0]
800883a: 697a ldr r2, [r7, #20]
800883c: 645a str r2, [r3, #68] ; 0x44
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(hrtc);
800883e: 68fb ldr r3, [r7, #12]
8008840: 681b ldr r3, [r3, #0]
8008842: 689a ldr r2, [r3, #8]
8008844: 68fb ldr r3, [r7, #12]
8008846: 681b ldr r3, [r3, #0]
8008848: f442 7280 orr.w r2, r2, #256 ; 0x100
800884c: 609a str r2, [r3, #8]
800884e: e03e b.n 80088ce <HAL_RTC_SetAlarm+0x212>
}
else
{
/* Disable the Alarm B interrupt */
__HAL_RTC_ALARMB_DISABLE(hrtc);
8008850: 68fb ldr r3, [r7, #12]
8008852: 681b ldr r3, [r3, #0]
8008854: 689a ldr r2, [r3, #8]
8008856: 68fb ldr r3, [r7, #12]
8008858: 681b ldr r3, [r3, #0]
800885a: f422 7200 bic.w r2, r2, #512 ; 0x200
800885e: 609a str r2, [r3, #8]
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
8008860: 68fb ldr r3, [r7, #12]
8008862: 681b ldr r3, [r3, #0]
8008864: 689a ldr r2, [r3, #8]
8008866: 68fb ldr r3, [r7, #12]
8008868: 681b ldr r3, [r3, #0]
800886a: f422 5200 bic.w r2, r2, #8192 ; 0x2000
800886e: 609a str r2, [r3, #8]
/* Get tick */
tickstart = HAL_GetTick();
8008870: f7fb fe3e bl 80044f0 <HAL_GetTick>
8008874: 61b8 str r0, [r7, #24]
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
8008876: e013 b.n 80088a0 <HAL_RTC_SetAlarm+0x1e4>
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
8008878: f7fb fe3a bl 80044f0 <HAL_GetTick>
800887c: 4602 mov r2, r0
800887e: 69bb ldr r3, [r7, #24]
8008880: 1ad3 subs r3, r2, r3
8008882: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008886: d90b bls.n 80088a0 <HAL_RTC_SetAlarm+0x1e4>
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008888: 68fb ldr r3, [r7, #12]
800888a: 681b ldr r3, [r3, #0]
800888c: 22ff movs r2, #255 ; 0xff
800888e: 625a str r2, [r3, #36] ; 0x24
hrtc->State = HAL_RTC_STATE_TIMEOUT;
8008890: 68fb ldr r3, [r7, #12]
8008892: 2203 movs r2, #3
8008894: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
8008896: 68fb ldr r3, [r7, #12]
8008898: 2200 movs r2, #0
800889a: 771a strb r2, [r3, #28]
return HAL_TIMEOUT;
800889c: 2303 movs r3, #3
800889e: e021 b.n 80088e4 <HAL_RTC_SetAlarm+0x228>
while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
80088a0: 68fb ldr r3, [r7, #12]
80088a2: 681b ldr r3, [r3, #0]
80088a4: 68db ldr r3, [r3, #12]
80088a6: f003 0302 and.w r3, r3, #2
80088aa: 2b00 cmp r3, #0
80088ac: d0e4 beq.n 8008878 <HAL_RTC_SetAlarm+0x1bc>
}
}
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
80088ae: 68fb ldr r3, [r7, #12]
80088b0: 681b ldr r3, [r3, #0]
80088b2: 69fa ldr r2, [r7, #28]
80088b4: 621a str r2, [r3, #32]
/* Configure the Alarm B Sub Second register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
80088b6: 68fb ldr r3, [r7, #12]
80088b8: 681b ldr r3, [r3, #0]
80088ba: 697a ldr r2, [r7, #20]
80088bc: 649a str r2, [r3, #72] ; 0x48
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMB_ENABLE(hrtc);
80088be: 68fb ldr r3, [r7, #12]
80088c0: 681b ldr r3, [r3, #0]
80088c2: 689a ldr r2, [r3, #8]
80088c4: 68fb ldr r3, [r7, #12]
80088c6: 681b ldr r3, [r3, #0]
80088c8: f442 7200 orr.w r2, r2, #512 ; 0x200
80088cc: 609a str r2, [r3, #8]
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
80088ce: 68fb ldr r3, [r7, #12]
80088d0: 681b ldr r3, [r3, #0]
80088d2: 22ff movs r2, #255 ; 0xff
80088d4: 625a str r2, [r3, #36] ; 0x24
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
80088d6: 68fb ldr r3, [r7, #12]
80088d8: 2201 movs r2, #1
80088da: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
80088dc: 68fb ldr r3, [r7, #12]
80088de: 2200 movs r2, #0
80088e0: 771a strb r2, [r3, #28]
return HAL_OK;
80088e2: 2300 movs r3, #0
}
80088e4: 4618 mov r0, r3
80088e6: 3724 adds r7, #36 ; 0x24
80088e8: 46bd mov sp, r7
80088ea: bd90 pop {r4, r7, pc}
080088ec <HAL_RTC_WaitForSynchro>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
80088ec: b580 push {r7, lr}
80088ee: b084 sub sp, #16
80088f0: af00 add r7, sp, #0
80088f2: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
80088f4: 2300 movs r3, #0
80088f6: 60fb str r3, [r7, #12]
/* Clear RSF flag */
hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
80088f8: 687b ldr r3, [r7, #4]
80088fa: 681b ldr r3, [r3, #0]
80088fc: 68da ldr r2, [r3, #12]
80088fe: 687b ldr r3, [r7, #4]
8008900: 681b ldr r3, [r3, #0]
8008902: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8008906: 60da str r2, [r3, #12]
/* Get tick */
tickstart = HAL_GetTick();
8008908: f7fb fdf2 bl 80044f0 <HAL_GetTick>
800890c: 60f8 str r0, [r7, #12]
/* Wait the registers to be synchronised */
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
800890e: e009 b.n 8008924 <HAL_RTC_WaitForSynchro+0x38>
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
8008910: f7fb fdee bl 80044f0 <HAL_GetTick>
8008914: 4602 mov r2, r0
8008916: 68fb ldr r3, [r7, #12]
8008918: 1ad3 subs r3, r2, r3
800891a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
800891e: d901 bls.n 8008924 <HAL_RTC_WaitForSynchro+0x38>
{
return HAL_TIMEOUT;
8008920: 2303 movs r3, #3
8008922: e007 b.n 8008934 <HAL_RTC_WaitForSynchro+0x48>
while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
8008924: 687b ldr r3, [r7, #4]
8008926: 681b ldr r3, [r3, #0]
8008928: 68db ldr r3, [r3, #12]
800892a: f003 0320 and.w r3, r3, #32
800892e: 2b00 cmp r3, #0
8008930: d0ee beq.n 8008910 <HAL_RTC_WaitForSynchro+0x24>
}
}
return HAL_OK;
8008932: 2300 movs r3, #0
}
8008934: 4618 mov r0, r3
8008936: 3710 adds r7, #16
8008938: 46bd mov sp, r7
800893a: bd80 pop {r7, pc}
0800893c <RTC_EnterInitMode>:
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
800893c: b580 push {r7, lr}
800893e: b084 sub sp, #16
8008940: af00 add r7, sp, #0
8008942: 6078 str r0, [r7, #4]
uint32_t tickstart = 0;
8008944: 2300 movs r3, #0
8008946: 60fb str r3, [r7, #12]
/* Check if the Initialization mode is set */
if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
8008948: 687b ldr r3, [r7, #4]
800894a: 681b ldr r3, [r3, #0]
800894c: 68db ldr r3, [r3, #12]
800894e: f003 0340 and.w r3, r3, #64 ; 0x40
8008952: 2b00 cmp r3, #0
8008954: d119 bne.n 800898a <RTC_EnterInitMode+0x4e>
{
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
8008956: 687b ldr r3, [r7, #4]
8008958: 681b ldr r3, [r3, #0]
800895a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800895e: 60da str r2, [r3, #12]
/* Get tick */
tickstart = HAL_GetTick();
8008960: f7fb fdc6 bl 80044f0 <HAL_GetTick>
8008964: 60f8 str r0, [r7, #12]
/* Wait till RTC is in INIT state and if Time out is reached exit */
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
8008966: e009 b.n 800897c <RTC_EnterInitMode+0x40>
{
if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
8008968: f7fb fdc2 bl 80044f0 <HAL_GetTick>
800896c: 4602 mov r2, r0
800896e: 68fb ldr r3, [r7, #12]
8008970: 1ad3 subs r3, r2, r3
8008972: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8
8008976: d901 bls.n 800897c <RTC_EnterInitMode+0x40>
{
return HAL_TIMEOUT;
8008978: 2303 movs r3, #3
800897a: e007 b.n 800898c <RTC_EnterInitMode+0x50>
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
800897c: 687b ldr r3, [r7, #4]
800897e: 681b ldr r3, [r3, #0]
8008980: 68db ldr r3, [r3, #12]
8008982: f003 0340 and.w r3, r3, #64 ; 0x40
8008986: 2b00 cmp r3, #0
8008988: d0ee beq.n 8008968 <RTC_EnterInitMode+0x2c>
}
}
}
return HAL_OK;
800898a: 2300 movs r3, #0
}
800898c: 4618 mov r0, r3
800898e: 3710 adds r7, #16
8008990: 46bd mov sp, r7
8008992: bd80 pop {r7, pc}
08008994 <RTC_ByteToBcd2>:
* @brief Converts a 2 digit decimal to BCD format.
* @param Value Byte to be converted
* @retval Converted byte
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
8008994: b480 push {r7}
8008996: b085 sub sp, #20
8008998: af00 add r7, sp, #0
800899a: 4603 mov r3, r0
800899c: 71fb strb r3, [r7, #7]
uint32_t bcdhigh = 0;
800899e: 2300 movs r3, #0
80089a0: 60fb str r3, [r7, #12]
while(Value >= 10)
80089a2: e005 b.n 80089b0 <RTC_ByteToBcd2+0x1c>
{
bcdhigh++;
80089a4: 68fb ldr r3, [r7, #12]
80089a6: 3301 adds r3, #1
80089a8: 60fb str r3, [r7, #12]
Value -= 10;
80089aa: 79fb ldrb r3, [r7, #7]
80089ac: 3b0a subs r3, #10
80089ae: 71fb strb r3, [r7, #7]
while(Value >= 10)
80089b0: 79fb ldrb r3, [r7, #7]
80089b2: 2b09 cmp r3, #9
80089b4: d8f6 bhi.n 80089a4 <RTC_ByteToBcd2+0x10>
}
return ((uint8_t)(bcdhigh << 4) | Value);
80089b6: 68fb ldr r3, [r7, #12]
80089b8: b2db uxtb r3, r3
80089ba: 011b lsls r3, r3, #4
80089bc: b2da uxtb r2, r3
80089be: 79fb ldrb r3, [r7, #7]
80089c0: 4313 orrs r3, r2
80089c2: b2db uxtb r3, r3
}
80089c4: 4618 mov r0, r3
80089c6: 3714 adds r7, #20
80089c8: 46bd mov sp, r7
80089ca: f85d 7b04 ldr.w r7, [sp], #4
80089ce: 4770 bx lr
080089d0 <HAL_RTCEx_SetTimeStamp>:
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PC1: PC1 is selected as RTC TimeStamp Pin.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
{
80089d0: b480 push {r7}
80089d2: b087 sub sp, #28
80089d4: af00 add r7, sp, #0
80089d6: 60f8 str r0, [r7, #12]
80089d8: 60b9 str r1, [r7, #8]
80089da: 607a str r2, [r7, #4]
uint32_t tmpreg = 0;
80089dc: 2300 movs r3, #0
80089de: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
/* Process Locked */
__HAL_LOCK(hrtc);
80089e0: 68fb ldr r3, [r7, #12]
80089e2: 7f1b ldrb r3, [r3, #28]
80089e4: 2b01 cmp r3, #1
80089e6: d101 bne.n 80089ec <HAL_RTCEx_SetTimeStamp+0x1c>
80089e8: 2302 movs r3, #2
80089ea: e03e b.n 8008a6a <HAL_RTCEx_SetTimeStamp+0x9a>
80089ec: 68fb ldr r3, [r7, #12]
80089ee: 2201 movs r2, #1
80089f0: 771a strb r2, [r3, #28]
hrtc->State = HAL_RTC_STATE_BUSY;
80089f2: 68fb ldr r3, [r7, #12]
80089f4: 2202 movs r2, #2
80089f6: 775a strb r2, [r3, #29]
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
80089f8: 68fb ldr r3, [r7, #12]
80089fa: 681b ldr r3, [r3, #0]
80089fc: 689a ldr r2, [r3, #8]
80089fe: 4b1e ldr r3, [pc, #120] ; (8008a78 <HAL_RTCEx_SetTimeStamp+0xa8>)
8008a00: 4013 ands r3, r2
8008a02: 617b str r3, [r7, #20]
tmpreg|= TimeStampEdge;
8008a04: 697a ldr r2, [r7, #20]
8008a06: 68bb ldr r3, [r7, #8]
8008a08: 4313 orrs r3, r2
8008a0a: 617b str r3, [r7, #20]
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
8008a0c: 68fb ldr r3, [r7, #12]
8008a0e: 681b ldr r3, [r3, #0]
8008a10: 22ca movs r2, #202 ; 0xca
8008a12: 625a str r2, [r3, #36] ; 0x24
8008a14: 68fb ldr r3, [r7, #12]
8008a16: 681b ldr r3, [r3, #0]
8008a18: 2253 movs r2, #83 ; 0x53
8008a1a: 625a str r2, [r3, #36] ; 0x24
hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL;
8008a1c: 68fb ldr r3, [r7, #12]
8008a1e: 681b ldr r3, [r3, #0]
8008a20: 6cda ldr r2, [r3, #76] ; 0x4c
8008a22: 68fb ldr r3, [r7, #12]
8008a24: 681b ldr r3, [r3, #0]
8008a26: f022 0206 bic.w r2, r2, #6
8008a2a: 64da str r2, [r3, #76] ; 0x4c
hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin);
8008a2c: 68fb ldr r3, [r7, #12]
8008a2e: 681b ldr r3, [r3, #0]
8008a30: 6cd9 ldr r1, [r3, #76] ; 0x4c
8008a32: 68fb ldr r3, [r7, #12]
8008a34: 681b ldr r3, [r3, #0]
8008a36: 687a ldr r2, [r7, #4]
8008a38: 430a orrs r2, r1
8008a3a: 64da str r2, [r3, #76] ; 0x4c
/* Configure the Time Stamp TSEDGE and Enable bits */
hrtc->Instance->CR = (uint32_t)tmpreg;
8008a3c: 68fb ldr r3, [r7, #12]
8008a3e: 681b ldr r3, [r3, #0]
8008a40: 697a ldr r2, [r7, #20]
8008a42: 609a str r2, [r3, #8]
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
8008a44: 68fb ldr r3, [r7, #12]
8008a46: 681b ldr r3, [r3, #0]
8008a48: 689a ldr r2, [r3, #8]
8008a4a: 68fb ldr r3, [r7, #12]
8008a4c: 681b ldr r3, [r3, #0]
8008a4e: f442 6200 orr.w r2, r2, #2048 ; 0x800
8008a52: 609a str r2, [r3, #8]
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
8008a54: 68fb ldr r3, [r7, #12]
8008a56: 681b ldr r3, [r3, #0]
8008a58: 22ff movs r2, #255 ; 0xff
8008a5a: 625a str r2, [r3, #36] ; 0x24
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
8008a5c: 68fb ldr r3, [r7, #12]
8008a5e: 2201 movs r2, #1
8008a60: 775a strb r2, [r3, #29]
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
8008a62: 68fb ldr r3, [r7, #12]
8008a64: 2200 movs r2, #0
8008a66: 771a strb r2, [r3, #28]
return HAL_OK;
8008a68: 2300 movs r3, #0
}
8008a6a: 4618 mov r0, r3
8008a6c: 371c adds r7, #28
8008a6e: 46bd mov sp, r7
8008a70: f85d 7b04 ldr.w r7, [sp], #4
8008a74: 4770 bx lr
8008a76: bf00 nop
8008a78: fffff7f7 .word 0xfffff7f7
08008a7c <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
8008a7c: b580 push {r7, lr}
8008a7e: b082 sub sp, #8
8008a80: af00 add r7, sp, #0
8008a82: 6078 str r0, [r7, #4]
8008a84: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
8008a86: 687b ldr r3, [r7, #4]
8008a88: 2b00 cmp r3, #0
8008a8a: d101 bne.n 8008a90 <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
8008a8c: 2301 movs r3, #1
8008a8e: e025 b.n 8008adc <HAL_SDRAM_Init+0x60>
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
8008a90: 687b ldr r3, [r7, #4]
8008a92: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8008a96: b2db uxtb r3, r3
8008a98: 2b00 cmp r3, #0
8008a9a: d106 bne.n 8008aaa <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
8008a9c: 687b ldr r3, [r7, #4]
8008a9e: 2200 movs r2, #0
8008aa0: f883 202d strb.w r2, [r3, #45] ; 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
8008aa4: 6878 ldr r0, [r7, #4]
8008aa6: f7fb fbfd bl 80042a4 <HAL_SDRAM_MspInit>
#endif
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8008aaa: 687b ldr r3, [r7, #4]
8008aac: 2202 movs r2, #2
8008aae: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
8008ab2: 687b ldr r3, [r7, #4]
8008ab4: 681a ldr r2, [r3, #0]
8008ab6: 687b ldr r3, [r7, #4]
8008ab8: 3304 adds r3, #4
8008aba: 4619 mov r1, r3
8008abc: 4610 mov r0, r2
8008abe: f001 fe61 bl 800a784 <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
8008ac2: 687b ldr r3, [r7, #4]
8008ac4: 6818 ldr r0, [r3, #0]
8008ac6: 687b ldr r3, [r7, #4]
8008ac8: 685b ldr r3, [r3, #4]
8008aca: 461a mov r2, r3
8008acc: 6839 ldr r1, [r7, #0]
8008ace: f001 fecb bl 800a868 <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
8008ad2: 687b ldr r3, [r7, #4]
8008ad4: 2201 movs r2, #1
8008ad6: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8008ada: 2300 movs r3, #0
}
8008adc: 4618 mov r0, r3
8008ade: 3708 adds r7, #8
8008ae0: 46bd mov sp, r7
8008ae2: bd80 pop {r7, pc}
08008ae4 <HAL_SDRAM_SendCommand>:
* @param Command SDRAM command structure
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
8008ae4: b580 push {r7, lr}
8008ae6: b084 sub sp, #16
8008ae8: af00 add r7, sp, #0
8008aea: 60f8 str r0, [r7, #12]
8008aec: 60b9 str r1, [r7, #8]
8008aee: 607a str r2, [r7, #4]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8008af0: 68fb ldr r3, [r7, #12]
8008af2: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8008af6: b2db uxtb r3, r3
8008af8: 2b02 cmp r3, #2
8008afa: d101 bne.n 8008b00 <HAL_SDRAM_SendCommand+0x1c>
{
return HAL_BUSY;
8008afc: 2302 movs r3, #2
8008afe: e018 b.n 8008b32 <HAL_SDRAM_SendCommand+0x4e>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8008b00: 68fb ldr r3, [r7, #12]
8008b02: 2202 movs r2, #2
8008b04: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
8008b08: 68fb ldr r3, [r7, #12]
8008b0a: 681b ldr r3, [r3, #0]
8008b0c: 687a ldr r2, [r7, #4]
8008b0e: 68b9 ldr r1, [r7, #8]
8008b10: 4618 mov r0, r3
8008b12: f001 ff29 bl 800a968 <FMC_SDRAM_SendCommand>
/* Update the SDRAM controller state state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
8008b16: 68bb ldr r3, [r7, #8]
8008b18: 681b ldr r3, [r3, #0]
8008b1a: 2b02 cmp r3, #2
8008b1c: d104 bne.n 8008b28 <HAL_SDRAM_SendCommand+0x44>
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
8008b1e: 68fb ldr r3, [r7, #12]
8008b20: 2205 movs r2, #5
8008b22: f883 202c strb.w r2, [r3, #44] ; 0x2c
8008b26: e003 b.n 8008b30 <HAL_SDRAM_SendCommand+0x4c>
}
else
{
hsdram->State = HAL_SDRAM_STATE_READY;
8008b28: 68fb ldr r3, [r7, #12]
8008b2a: 2201 movs r2, #1
8008b2c: f883 202c strb.w r2, [r3, #44] ; 0x2c
}
return HAL_OK;
8008b30: 2300 movs r3, #0
}
8008b32: 4618 mov r0, r3
8008b34: 3710 adds r7, #16
8008b36: 46bd mov sp, r7
8008b38: bd80 pop {r7, pc}
08008b3a <HAL_SDRAM_ProgramRefreshRate>:
* the configuration information for SDRAM module.
* @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
8008b3a: b580 push {r7, lr}
8008b3c: b082 sub sp, #8
8008b3e: af00 add r7, sp, #0
8008b40: 6078 str r0, [r7, #4]
8008b42: 6039 str r1, [r7, #0]
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
8008b44: 687b ldr r3, [r7, #4]
8008b46: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8008b4a: b2db uxtb r3, r3
8008b4c: 2b02 cmp r3, #2
8008b4e: d101 bne.n 8008b54 <HAL_SDRAM_ProgramRefreshRate+0x1a>
{
return HAL_BUSY;
8008b50: 2302 movs r3, #2
8008b52: e00e b.n 8008b72 <HAL_SDRAM_ProgramRefreshRate+0x38>
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8008b54: 687b ldr r3, [r7, #4]
8008b56: 2202 movs r2, #2
8008b58: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Program the refresh rate */
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
8008b5c: 687b ldr r3, [r7, #4]
8008b5e: 681b ldr r3, [r3, #0]
8008b60: 6839 ldr r1, [r7, #0]
8008b62: 4618 mov r0, r3
8008b64: f001 ff21 bl 800a9aa <FMC_SDRAM_ProgramRefreshRate>
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
8008b68: 687b ldr r3, [r7, #4]
8008b6a: 2201 movs r2, #1
8008b6c: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8008b70: 2300 movs r3, #0
}
8008b72: 4618 mov r0, r3
8008b74: 3708 adds r7, #8
8008b76: 46bd mov sp, r7
8008b78: bd80 pop {r7, pc}
08008b7a <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8008b7a: b580 push {r7, lr}
8008b7c: b084 sub sp, #16
8008b7e: af00 add r7, sp, #0
8008b80: 6078 str r0, [r7, #4]
uint32_t frxth;
/* Check the SPI handle allocation */
if (hspi == NULL)
8008b82: 687b ldr r3, [r7, #4]
8008b84: 2b00 cmp r3, #0
8008b86: d101 bne.n 8008b8c <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8008b88: 2301 movs r3, #1
8008b8a: e084 b.n 8008c96 <HAL_SPI_Init+0x11c>
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8008b8c: 687b ldr r3, [r7, #4]
8008b8e: 2200 movs r2, #0
8008b90: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
8008b92: 687b ldr r3, [r7, #4]
8008b94: f893 305d ldrb.w r3, [r3, #93] ; 0x5d
8008b98: b2db uxtb r3, r3
8008b9a: 2b00 cmp r3, #0
8008b9c: d106 bne.n 8008bac <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8008b9e: 687b ldr r3, [r7, #4]
8008ba0: 2200 movs r2, #0
8008ba2: f883 205c strb.w r2, [r3, #92] ; 0x5c
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8008ba6: 6878 ldr r0, [r7, #4]
8008ba8: f7fb f8e8 bl 8003d7c <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8008bac: 687b ldr r3, [r7, #4]
8008bae: 2202 movs r2, #2
8008bb0: f883 205d strb.w r2, [r3, #93] ; 0x5d
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8008bb4: 687b ldr r3, [r7, #4]
8008bb6: 681b ldr r3, [r3, #0]
8008bb8: 681a ldr r2, [r3, #0]
8008bba: 687b ldr r3, [r7, #4]
8008bbc: 681b ldr r3, [r3, #0]
8008bbe: f022 0240 bic.w r2, r2, #64 ; 0x40
8008bc2: 601a str r2, [r3, #0]
/* Align by default the rs fifo threshold on the data size */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8008bc4: 687b ldr r3, [r7, #4]
8008bc6: 68db ldr r3, [r3, #12]
8008bc8: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8008bcc: d902 bls.n 8008bd4 <HAL_SPI_Init+0x5a>
{
frxth = SPI_RXFIFO_THRESHOLD_HF;
8008bce: 2300 movs r3, #0
8008bd0: 60fb str r3, [r7, #12]
8008bd2: e002 b.n 8008bda <HAL_SPI_Init+0x60>
}
else
{
frxth = SPI_RXFIFO_THRESHOLD_QF;
8008bd4: f44f 5380 mov.w r3, #4096 ; 0x1000
8008bd8: 60fb str r3, [r7, #12]
}
/* CRC calculation is valid only for 16Bit and 8 Bit */
if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
8008bda: 687b ldr r3, [r7, #4]
8008bdc: 68db ldr r3, [r3, #12]
8008bde: f5b3 6f70 cmp.w r3, #3840 ; 0xf00
8008be2: d007 beq.n 8008bf4 <HAL_SPI_Init+0x7a>
8008be4: 687b ldr r3, [r7, #4]
8008be6: 68db ldr r3, [r3, #12]
8008be8: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8008bec: d002 beq.n 8008bf4 <HAL_SPI_Init+0x7a>
{
/* CRC must be disabled */
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8008bee: 687b ldr r3, [r7, #4]
8008bf0: 2200 movs r2, #0
8008bf2: 629a str r2, [r3, #40] ; 0x28
}
/* Align the CRC Length on the data size */
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
8008bf4: 687b ldr r3, [r7, #4]
8008bf6: 6b1b ldr r3, [r3, #48] ; 0x30
8008bf8: 2b00 cmp r3, #0
8008bfa: d10b bne.n 8008c14 <HAL_SPI_Init+0x9a>
{
/* CRC Length aligned on the data size : value set by default */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8008bfc: 687b ldr r3, [r7, #4]
8008bfe: 68db ldr r3, [r3, #12]
8008c00: f5b3 6fe0 cmp.w r3, #1792 ; 0x700
8008c04: d903 bls.n 8008c0e <HAL_SPI_Init+0x94>
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
8008c06: 687b ldr r3, [r7, #4]
8008c08: 2202 movs r2, #2
8008c0a: 631a str r2, [r3, #48] ; 0x30
8008c0c: e002 b.n 8008c14 <HAL_SPI_Init+0x9a>
}
else
{
hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
8008c0e: 687b ldr r3, [r7, #4]
8008c10: 2201 movs r2, #1
8008c12: 631a str r2, [r3, #48] ; 0x30
}
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
8008c14: 687b ldr r3, [r7, #4]
8008c16: 685a ldr r2, [r3, #4]
8008c18: 687b ldr r3, [r7, #4]
8008c1a: 689b ldr r3, [r3, #8]
8008c1c: 431a orrs r2, r3
8008c1e: 687b ldr r3, [r7, #4]
8008c20: 691b ldr r3, [r3, #16]
8008c22: 431a orrs r2, r3
8008c24: 687b ldr r3, [r7, #4]
8008c26: 695b ldr r3, [r3, #20]
8008c28: 431a orrs r2, r3
8008c2a: 687b ldr r3, [r7, #4]
8008c2c: 699b ldr r3, [r3, #24]
8008c2e: f403 7300 and.w r3, r3, #512 ; 0x200
8008c32: 431a orrs r2, r3
8008c34: 687b ldr r3, [r7, #4]
8008c36: 69db ldr r3, [r3, #28]
8008c38: 431a orrs r2, r3
8008c3a: 687b ldr r3, [r7, #4]
8008c3c: 6a1b ldr r3, [r3, #32]
8008c3e: ea42 0103 orr.w r1, r2, r3
8008c42: 687b ldr r3, [r7, #4]
8008c44: 6a9a ldr r2, [r3, #40] ; 0x28
8008c46: 687b ldr r3, [r7, #4]
8008c48: 681b ldr r3, [r3, #0]
8008c4a: 430a orrs r2, r1
8008c4c: 601a str r2, [r3, #0]
hspi->Instance->CR1 |= SPI_CR1_CRCL;
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
8008c4e: 687b ldr r3, [r7, #4]
8008c50: 699b ldr r3, [r3, #24]
8008c52: 0c1b lsrs r3, r3, #16
8008c54: f003 0204 and.w r2, r3, #4
8008c58: 687b ldr r3, [r7, #4]
8008c5a: 6a5b ldr r3, [r3, #36] ; 0x24
8008c5c: 431a orrs r2, r3
8008c5e: 687b ldr r3, [r7, #4]
8008c60: 6b5b ldr r3, [r3, #52] ; 0x34
8008c62: 431a orrs r2, r3
8008c64: 687b ldr r3, [r7, #4]
8008c66: 68db ldr r3, [r3, #12]
8008c68: ea42 0103 orr.w r1, r2, r3
8008c6c: 687b ldr r3, [r7, #4]
8008c6e: 681b ldr r3, [r3, #0]
8008c70: 68fa ldr r2, [r7, #12]
8008c72: 430a orrs r2, r1
8008c74: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8008c76: 687b ldr r3, [r7, #4]
8008c78: 681b ldr r3, [r3, #0]
8008c7a: 69da ldr r2, [r3, #28]
8008c7c: 687b ldr r3, [r7, #4]
8008c7e: 681b ldr r3, [r3, #0]
8008c80: f422 6200 bic.w r2, r2, #2048 ; 0x800
8008c84: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8008c86: 687b ldr r3, [r7, #4]
8008c88: 2200 movs r2, #0
8008c8a: 661a str r2, [r3, #96] ; 0x60
hspi->State = HAL_SPI_STATE_READY;
8008c8c: 687b ldr r3, [r7, #4]
8008c8e: 2201 movs r2, #1
8008c90: f883 205d strb.w r2, [r3, #93] ; 0x5d
return HAL_OK;
8008c94: 2300 movs r3, #0
}
8008c96: 4618 mov r0, r3
8008c98: 3710 adds r7, #16
8008c9a: 46bd mov sp, r7
8008c9c: bd80 pop {r7, pc}
08008c9e <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8008c9e: b580 push {r7, lr}
8008ca0: b082 sub sp, #8
8008ca2: af00 add r7, sp, #0
8008ca4: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8008ca6: 687b ldr r3, [r7, #4]
8008ca8: 2b00 cmp r3, #0
8008caa: d101 bne.n 8008cb0 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8008cac: 2301 movs r3, #1
8008cae: e01d b.n 8008cec <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8008cb0: 687b ldr r3, [r7, #4]
8008cb2: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8008cb6: b2db uxtb r3, r3
8008cb8: 2b00 cmp r3, #0
8008cba: d106 bne.n 8008cca <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8008cbc: 687b ldr r3, [r7, #4]
8008cbe: 2200 movs r2, #0
8008cc0: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8008cc4: 6878 ldr r0, [r7, #4]
8008cc6: f7fb f8cb bl 8003e60 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8008cca: 687b ldr r3, [r7, #4]
8008ccc: 2202 movs r2, #2
8008cce: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8008cd2: 687b ldr r3, [r7, #4]
8008cd4: 681a ldr r2, [r3, #0]
8008cd6: 687b ldr r3, [r7, #4]
8008cd8: 3304 adds r3, #4
8008cda: 4619 mov r1, r3
8008cdc: 4610 mov r0, r2
8008cde: f000 fbc3 bl 8009468 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8008ce2: 687b ldr r3, [r7, #4]
8008ce4: 2201 movs r2, #1
8008ce6: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8008cea: 2300 movs r3, #0
}
8008cec: 4618 mov r0, r3
8008cee: 3708 adds r7, #8
8008cf0: 46bd mov sp, r7
8008cf2: bd80 pop {r7, pc}
08008cf4 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8008cf4: b480 push {r7}
8008cf6: b085 sub sp, #20
8008cf8: af00 add r7, sp, #0
8008cfa: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8008cfc: 687b ldr r3, [r7, #4]
8008cfe: 681b ldr r3, [r3, #0]
8008d00: 68da ldr r2, [r3, #12]
8008d02: 687b ldr r3, [r7, #4]
8008d04: 681b ldr r3, [r3, #0]
8008d06: f042 0201 orr.w r2, r2, #1
8008d0a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8008d0c: 687b ldr r3, [r7, #4]
8008d0e: 681b ldr r3, [r3, #0]
8008d10: 689a ldr r2, [r3, #8]
8008d12: 4b0c ldr r3, [pc, #48] ; (8008d44 <HAL_TIM_Base_Start_IT+0x50>)
8008d14: 4013 ands r3, r2
8008d16: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8008d18: 68fb ldr r3, [r7, #12]
8008d1a: 2b06 cmp r3, #6
8008d1c: d00b beq.n 8008d36 <HAL_TIM_Base_Start_IT+0x42>
8008d1e: 68fb ldr r3, [r7, #12]
8008d20: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8008d24: d007 beq.n 8008d36 <HAL_TIM_Base_Start_IT+0x42>
{
__HAL_TIM_ENABLE(htim);
8008d26: 687b ldr r3, [r7, #4]
8008d28: 681b ldr r3, [r3, #0]
8008d2a: 681a ldr r2, [r3, #0]
8008d2c: 687b ldr r3, [r7, #4]
8008d2e: 681b ldr r3, [r3, #0]
8008d30: f042 0201 orr.w r2, r2, #1
8008d34: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8008d36: 2300 movs r3, #0
}
8008d38: 4618 mov r0, r3
8008d3a: 3714 adds r7, #20
8008d3c: 46bd mov sp, r7
8008d3e: f85d 7b04 ldr.w r7, [sp], #4
8008d42: 4770 bx lr
8008d44: 00010007 .word 0x00010007
08008d48 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8008d48: b580 push {r7, lr}
8008d4a: b082 sub sp, #8
8008d4c: af00 add r7, sp, #0
8008d4e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8008d50: 687b ldr r3, [r7, #4]
8008d52: 2b00 cmp r3, #0
8008d54: d101 bne.n 8008d5a <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8008d56: 2301 movs r3, #1
8008d58: e01d b.n 8008d96 <HAL_TIM_PWM_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8008d5a: 687b ldr r3, [r7, #4]
8008d5c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8008d60: b2db uxtb r3, r3
8008d62: 2b00 cmp r3, #0
8008d64: d106 bne.n 8008d74 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8008d66: 687b ldr r3, [r7, #4]
8008d68: 2200 movs r2, #0
8008d6a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
8008d6e: 6878 ldr r0, [r7, #4]
8008d70: f000 f815 bl 8008d9e <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8008d74: 687b ldr r3, [r7, #4]
8008d76: 2202 movs r2, #2
8008d78: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8008d7c: 687b ldr r3, [r7, #4]
8008d7e: 681a ldr r2, [r3, #0]
8008d80: 687b ldr r3, [r7, #4]
8008d82: 3304 adds r3, #4
8008d84: 4619 mov r1, r3
8008d86: 4610 mov r0, r2
8008d88: f000 fb6e bl 8009468 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8008d8c: 687b ldr r3, [r7, #4]
8008d8e: 2201 movs r2, #1
8008d90: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8008d94: 2300 movs r3, #0
}
8008d96: 4618 mov r0, r3
8008d98: 3708 adds r7, #8
8008d9a: 46bd mov sp, r7
8008d9c: bd80 pop {r7, pc}
08008d9e <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8008d9e: b480 push {r7}
8008da0: b083 sub sp, #12
8008da2: af00 add r7, sp, #0
8008da4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
8008da6: bf00 nop
8008da8: 370c adds r7, #12
8008daa: 46bd mov sp, r7
8008dac: f85d 7b04 ldr.w r7, [sp], #4
8008db0: 4770 bx lr
08008db2 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8008db2: b580 push {r7, lr}
8008db4: b082 sub sp, #8
8008db6: af00 add r7, sp, #0
8008db8: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8008dba: 687b ldr r3, [r7, #4]
8008dbc: 681b ldr r3, [r3, #0]
8008dbe: 691b ldr r3, [r3, #16]
8008dc0: f003 0302 and.w r3, r3, #2
8008dc4: 2b02 cmp r3, #2
8008dc6: d122 bne.n 8008e0e <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8008dc8: 687b ldr r3, [r7, #4]
8008dca: 681b ldr r3, [r3, #0]
8008dcc: 68db ldr r3, [r3, #12]
8008dce: f003 0302 and.w r3, r3, #2
8008dd2: 2b02 cmp r3, #2
8008dd4: d11b bne.n 8008e0e <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8008dd6: 687b ldr r3, [r7, #4]
8008dd8: 681b ldr r3, [r3, #0]
8008dda: f06f 0202 mvn.w r2, #2
8008dde: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8008de0: 687b ldr r3, [r7, #4]
8008de2: 2201 movs r2, #1
8008de4: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8008de6: 687b ldr r3, [r7, #4]
8008de8: 681b ldr r3, [r3, #0]
8008dea: 699b ldr r3, [r3, #24]
8008dec: f003 0303 and.w r3, r3, #3
8008df0: 2b00 cmp r3, #0
8008df2: d003 beq.n 8008dfc <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8008df4: 6878 ldr r0, [r7, #4]
8008df6: f000 fb19 bl 800942c <HAL_TIM_IC_CaptureCallback>
8008dfa: e005 b.n 8008e08 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8008dfc: 6878 ldr r0, [r7, #4]
8008dfe: f000 fb0b bl 8009418 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8008e02: 6878 ldr r0, [r7, #4]
8008e04: f000 fb1c bl 8009440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8008e08: 687b ldr r3, [r7, #4]
8008e0a: 2200 movs r2, #0
8008e0c: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8008e0e: 687b ldr r3, [r7, #4]
8008e10: 681b ldr r3, [r3, #0]
8008e12: 691b ldr r3, [r3, #16]
8008e14: f003 0304 and.w r3, r3, #4
8008e18: 2b04 cmp r3, #4
8008e1a: d122 bne.n 8008e62 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8008e1c: 687b ldr r3, [r7, #4]
8008e1e: 681b ldr r3, [r3, #0]
8008e20: 68db ldr r3, [r3, #12]
8008e22: f003 0304 and.w r3, r3, #4
8008e26: 2b04 cmp r3, #4
8008e28: d11b bne.n 8008e62 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8008e2a: 687b ldr r3, [r7, #4]
8008e2c: 681b ldr r3, [r3, #0]
8008e2e: f06f 0204 mvn.w r2, #4
8008e32: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8008e34: 687b ldr r3, [r7, #4]
8008e36: 2202 movs r2, #2
8008e38: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8008e3a: 687b ldr r3, [r7, #4]
8008e3c: 681b ldr r3, [r3, #0]
8008e3e: 699b ldr r3, [r3, #24]
8008e40: f403 7340 and.w r3, r3, #768 ; 0x300
8008e44: 2b00 cmp r3, #0
8008e46: d003 beq.n 8008e50 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8008e48: 6878 ldr r0, [r7, #4]
8008e4a: f000 faef bl 800942c <HAL_TIM_IC_CaptureCallback>
8008e4e: e005 b.n 8008e5c <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8008e50: 6878 ldr r0, [r7, #4]
8008e52: f000 fae1 bl 8009418 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8008e56: 6878 ldr r0, [r7, #4]
8008e58: f000 faf2 bl 8009440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8008e5c: 687b ldr r3, [r7, #4]
8008e5e: 2200 movs r2, #0
8008e60: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8008e62: 687b ldr r3, [r7, #4]
8008e64: 681b ldr r3, [r3, #0]
8008e66: 691b ldr r3, [r3, #16]
8008e68: f003 0308 and.w r3, r3, #8
8008e6c: 2b08 cmp r3, #8
8008e6e: d122 bne.n 8008eb6 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8008e70: 687b ldr r3, [r7, #4]
8008e72: 681b ldr r3, [r3, #0]
8008e74: 68db ldr r3, [r3, #12]
8008e76: f003 0308 and.w r3, r3, #8
8008e7a: 2b08 cmp r3, #8
8008e7c: d11b bne.n 8008eb6 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8008e7e: 687b ldr r3, [r7, #4]
8008e80: 681b ldr r3, [r3, #0]
8008e82: f06f 0208 mvn.w r2, #8
8008e86: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8008e88: 687b ldr r3, [r7, #4]
8008e8a: 2204 movs r2, #4
8008e8c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8008e8e: 687b ldr r3, [r7, #4]
8008e90: 681b ldr r3, [r3, #0]
8008e92: 69db ldr r3, [r3, #28]
8008e94: f003 0303 and.w r3, r3, #3
8008e98: 2b00 cmp r3, #0
8008e9a: d003 beq.n 8008ea4 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8008e9c: 6878 ldr r0, [r7, #4]
8008e9e: f000 fac5 bl 800942c <HAL_TIM_IC_CaptureCallback>
8008ea2: e005 b.n 8008eb0 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8008ea4: 6878 ldr r0, [r7, #4]
8008ea6: f000 fab7 bl 8009418 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8008eaa: 6878 ldr r0, [r7, #4]
8008eac: f000 fac8 bl 8009440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8008eb0: 687b ldr r3, [r7, #4]
8008eb2: 2200 movs r2, #0
8008eb4: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8008eb6: 687b ldr r3, [r7, #4]
8008eb8: 681b ldr r3, [r3, #0]
8008eba: 691b ldr r3, [r3, #16]
8008ebc: f003 0310 and.w r3, r3, #16
8008ec0: 2b10 cmp r3, #16
8008ec2: d122 bne.n 8008f0a <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8008ec4: 687b ldr r3, [r7, #4]
8008ec6: 681b ldr r3, [r3, #0]
8008ec8: 68db ldr r3, [r3, #12]
8008eca: f003 0310 and.w r3, r3, #16
8008ece: 2b10 cmp r3, #16
8008ed0: d11b bne.n 8008f0a <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8008ed2: 687b ldr r3, [r7, #4]
8008ed4: 681b ldr r3, [r3, #0]
8008ed6: f06f 0210 mvn.w r2, #16
8008eda: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8008edc: 687b ldr r3, [r7, #4]
8008ede: 2208 movs r2, #8
8008ee0: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8008ee2: 687b ldr r3, [r7, #4]
8008ee4: 681b ldr r3, [r3, #0]
8008ee6: 69db ldr r3, [r3, #28]
8008ee8: f403 7340 and.w r3, r3, #768 ; 0x300
8008eec: 2b00 cmp r3, #0
8008eee: d003 beq.n 8008ef8 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8008ef0: 6878 ldr r0, [r7, #4]
8008ef2: f000 fa9b bl 800942c <HAL_TIM_IC_CaptureCallback>
8008ef6: e005 b.n 8008f04 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8008ef8: 6878 ldr r0, [r7, #4]
8008efa: f000 fa8d bl 8009418 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8008efe: 6878 ldr r0, [r7, #4]
8008f00: f000 fa9e bl 8009440 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8008f04: 687b ldr r3, [r7, #4]
8008f06: 2200 movs r2, #0
8008f08: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8008f0a: 687b ldr r3, [r7, #4]
8008f0c: 681b ldr r3, [r3, #0]
8008f0e: 691b ldr r3, [r3, #16]
8008f10: f003 0301 and.w r3, r3, #1
8008f14: 2b01 cmp r3, #1
8008f16: d10e bne.n 8008f36 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8008f18: 687b ldr r3, [r7, #4]
8008f1a: 681b ldr r3, [r3, #0]
8008f1c: 68db ldr r3, [r3, #12]
8008f1e: f003 0301 and.w r3, r3, #1
8008f22: 2b01 cmp r3, #1
8008f24: d107 bne.n 8008f36 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8008f26: 687b ldr r3, [r7, #4]
8008f28: 681b ldr r3, [r3, #0]
8008f2a: f06f 0201 mvn.w r2, #1
8008f2e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8008f30: 6878 ldr r0, [r7, #4]
8008f32: f7f8 ffbf bl 8001eb4 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8008f36: 687b ldr r3, [r7, #4]
8008f38: 681b ldr r3, [r3, #0]
8008f3a: 691b ldr r3, [r3, #16]
8008f3c: f003 0380 and.w r3, r3, #128 ; 0x80
8008f40: 2b80 cmp r3, #128 ; 0x80
8008f42: d10e bne.n 8008f62 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8008f44: 687b ldr r3, [r7, #4]
8008f46: 681b ldr r3, [r3, #0]
8008f48: 68db ldr r3, [r3, #12]
8008f4a: f003 0380 and.w r3, r3, #128 ; 0x80
8008f4e: 2b80 cmp r3, #128 ; 0x80
8008f50: d107 bne.n 8008f62 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8008f52: 687b ldr r3, [r7, #4]
8008f54: 681b ldr r3, [r3, #0]
8008f56: f06f 0280 mvn.w r2, #128 ; 0x80
8008f5a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8008f5c: 6878 ldr r0, [r7, #4]
8008f5e: f000 ffb9 bl 8009ed4 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
8008f62: 687b ldr r3, [r7, #4]
8008f64: 681b ldr r3, [r3, #0]
8008f66: 691b ldr r3, [r3, #16]
8008f68: f403 7380 and.w r3, r3, #256 ; 0x100
8008f6c: f5b3 7f80 cmp.w r3, #256 ; 0x100
8008f70: d10e bne.n 8008f90 <HAL_TIM_IRQHandler+0x1de>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8008f72: 687b ldr r3, [r7, #4]
8008f74: 681b ldr r3, [r3, #0]
8008f76: 68db ldr r3, [r3, #12]
8008f78: f003 0380 and.w r3, r3, #128 ; 0x80
8008f7c: 2b80 cmp r3, #128 ; 0x80
8008f7e: d107 bne.n 8008f90 <HAL_TIM_IRQHandler+0x1de>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8008f80: 687b ldr r3, [r7, #4]
8008f82: 681b ldr r3, [r3, #0]
8008f84: f46f 7280 mvn.w r2, #256 ; 0x100
8008f88: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8008f8a: 6878 ldr r0, [r7, #4]
8008f8c: f000 ffac bl 8009ee8 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8008f90: 687b ldr r3, [r7, #4]
8008f92: 681b ldr r3, [r3, #0]
8008f94: 691b ldr r3, [r3, #16]
8008f96: f003 0340 and.w r3, r3, #64 ; 0x40
8008f9a: 2b40 cmp r3, #64 ; 0x40
8008f9c: d10e bne.n 8008fbc <HAL_TIM_IRQHandler+0x20a>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8008f9e: 687b ldr r3, [r7, #4]
8008fa0: 681b ldr r3, [r3, #0]
8008fa2: 68db ldr r3, [r3, #12]
8008fa4: f003 0340 and.w r3, r3, #64 ; 0x40
8008fa8: 2b40 cmp r3, #64 ; 0x40
8008faa: d107 bne.n 8008fbc <HAL_TIM_IRQHandler+0x20a>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8008fac: 687b ldr r3, [r7, #4]
8008fae: 681b ldr r3, [r3, #0]
8008fb0: f06f 0240 mvn.w r2, #64 ; 0x40
8008fb4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8008fb6: 6878 ldr r0, [r7, #4]
8008fb8: f000 fa4c bl 8009454 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8008fbc: 687b ldr r3, [r7, #4]
8008fbe: 681b ldr r3, [r3, #0]
8008fc0: 691b ldr r3, [r3, #16]
8008fc2: f003 0320 and.w r3, r3, #32
8008fc6: 2b20 cmp r3, #32
8008fc8: d10e bne.n 8008fe8 <HAL_TIM_IRQHandler+0x236>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8008fca: 687b ldr r3, [r7, #4]
8008fcc: 681b ldr r3, [r3, #0]
8008fce: 68db ldr r3, [r3, #12]
8008fd0: f003 0320 and.w r3, r3, #32
8008fd4: 2b20 cmp r3, #32
8008fd6: d107 bne.n 8008fe8 <HAL_TIM_IRQHandler+0x236>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8008fd8: 687b ldr r3, [r7, #4]
8008fda: 681b ldr r3, [r3, #0]
8008fdc: f06f 0220 mvn.w r2, #32
8008fe0: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8008fe2: 6878 ldr r0, [r7, #4]
8008fe4: f000 ff6c bl 8009ec0 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8008fe8: bf00 nop
8008fea: 3708 adds r7, #8
8008fec: 46bd mov sp, r7
8008fee: bd80 pop {r7, pc}
08008ff0 <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8008ff0: b580 push {r7, lr}
8008ff2: b084 sub sp, #16
8008ff4: af00 add r7, sp, #0
8008ff6: 60f8 str r0, [r7, #12]
8008ff8: 60b9 str r1, [r7, #8]
8008ffa: 607a str r2, [r7, #4]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
8008ffc: 68fb ldr r3, [r7, #12]
8008ffe: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009002: 2b01 cmp r3, #1
8009004: d101 bne.n 800900a <HAL_TIM_PWM_ConfigChannel+0x1a>
8009006: 2302 movs r3, #2
8009008: e105 b.n 8009216 <HAL_TIM_PWM_ConfigChannel+0x226>
800900a: 68fb ldr r3, [r7, #12]
800900c: 2201 movs r2, #1
800900e: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8009012: 68fb ldr r3, [r7, #12]
8009014: 2202 movs r2, #2
8009016: f883 203d strb.w r2, [r3, #61] ; 0x3d
switch (Channel)
800901a: 687b ldr r3, [r7, #4]
800901c: 2b14 cmp r3, #20
800901e: f200 80f0 bhi.w 8009202 <HAL_TIM_PWM_ConfigChannel+0x212>
8009022: a201 add r2, pc, #4 ; (adr r2, 8009028 <HAL_TIM_PWM_ConfigChannel+0x38>)
8009024: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009028: 0800907d .word 0x0800907d
800902c: 08009203 .word 0x08009203
8009030: 08009203 .word 0x08009203
8009034: 08009203 .word 0x08009203
8009038: 080090bd .word 0x080090bd
800903c: 08009203 .word 0x08009203
8009040: 08009203 .word 0x08009203
8009044: 08009203 .word 0x08009203
8009048: 080090ff .word 0x080090ff
800904c: 08009203 .word 0x08009203
8009050: 08009203 .word 0x08009203
8009054: 08009203 .word 0x08009203
8009058: 0800913f .word 0x0800913f
800905c: 08009203 .word 0x08009203
8009060: 08009203 .word 0x08009203
8009064: 08009203 .word 0x08009203
8009068: 08009181 .word 0x08009181
800906c: 08009203 .word 0x08009203
8009070: 08009203 .word 0x08009203
8009074: 08009203 .word 0x08009203
8009078: 080091c1 .word 0x080091c1
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
800907c: 68fb ldr r3, [r7, #12]
800907e: 681b ldr r3, [r3, #0]
8009080: 68b9 ldr r1, [r7, #8]
8009082: 4618 mov r0, r3
8009084: f000 fa90 bl 80095a8 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8009088: 68fb ldr r3, [r7, #12]
800908a: 681b ldr r3, [r3, #0]
800908c: 699a ldr r2, [r3, #24]
800908e: 68fb ldr r3, [r7, #12]
8009090: 681b ldr r3, [r3, #0]
8009092: f042 0208 orr.w r2, r2, #8
8009096: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8009098: 68fb ldr r3, [r7, #12]
800909a: 681b ldr r3, [r3, #0]
800909c: 699a ldr r2, [r3, #24]
800909e: 68fb ldr r3, [r7, #12]
80090a0: 681b ldr r3, [r3, #0]
80090a2: f022 0204 bic.w r2, r2, #4
80090a6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80090a8: 68fb ldr r3, [r7, #12]
80090aa: 681b ldr r3, [r3, #0]
80090ac: 6999 ldr r1, [r3, #24]
80090ae: 68bb ldr r3, [r7, #8]
80090b0: 691a ldr r2, [r3, #16]
80090b2: 68fb ldr r3, [r7, #12]
80090b4: 681b ldr r3, [r3, #0]
80090b6: 430a orrs r2, r1
80090b8: 619a str r2, [r3, #24]
break;
80090ba: e0a3 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80090bc: 68fb ldr r3, [r7, #12]
80090be: 681b ldr r3, [r3, #0]
80090c0: 68b9 ldr r1, [r7, #8]
80090c2: 4618 mov r0, r3
80090c4: f000 fae2 bl 800968c <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80090c8: 68fb ldr r3, [r7, #12]
80090ca: 681b ldr r3, [r3, #0]
80090cc: 699a ldr r2, [r3, #24]
80090ce: 68fb ldr r3, [r7, #12]
80090d0: 681b ldr r3, [r3, #0]
80090d2: f442 6200 orr.w r2, r2, #2048 ; 0x800
80090d6: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80090d8: 68fb ldr r3, [r7, #12]
80090da: 681b ldr r3, [r3, #0]
80090dc: 699a ldr r2, [r3, #24]
80090de: 68fb ldr r3, [r7, #12]
80090e0: 681b ldr r3, [r3, #0]
80090e2: f422 6280 bic.w r2, r2, #1024 ; 0x400
80090e6: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80090e8: 68fb ldr r3, [r7, #12]
80090ea: 681b ldr r3, [r3, #0]
80090ec: 6999 ldr r1, [r3, #24]
80090ee: 68bb ldr r3, [r7, #8]
80090f0: 691b ldr r3, [r3, #16]
80090f2: 021a lsls r2, r3, #8
80090f4: 68fb ldr r3, [r7, #12]
80090f6: 681b ldr r3, [r3, #0]
80090f8: 430a orrs r2, r1
80090fa: 619a str r2, [r3, #24]
break;
80090fc: e082 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
80090fe: 68fb ldr r3, [r7, #12]
8009100: 681b ldr r3, [r3, #0]
8009102: 68b9 ldr r1, [r7, #8]
8009104: 4618 mov r0, r3
8009106: f000 fb39 bl 800977c <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800910a: 68fb ldr r3, [r7, #12]
800910c: 681b ldr r3, [r3, #0]
800910e: 69da ldr r2, [r3, #28]
8009110: 68fb ldr r3, [r7, #12]
8009112: 681b ldr r3, [r3, #0]
8009114: f042 0208 orr.w r2, r2, #8
8009118: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
800911a: 68fb ldr r3, [r7, #12]
800911c: 681b ldr r3, [r3, #0]
800911e: 69da ldr r2, [r3, #28]
8009120: 68fb ldr r3, [r7, #12]
8009122: 681b ldr r3, [r3, #0]
8009124: f022 0204 bic.w r2, r2, #4
8009128: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
800912a: 68fb ldr r3, [r7, #12]
800912c: 681b ldr r3, [r3, #0]
800912e: 69d9 ldr r1, [r3, #28]
8009130: 68bb ldr r3, [r7, #8]
8009132: 691a ldr r2, [r3, #16]
8009134: 68fb ldr r3, [r7, #12]
8009136: 681b ldr r3, [r3, #0]
8009138: 430a orrs r2, r1
800913a: 61da str r2, [r3, #28]
break;
800913c: e062 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
800913e: 68fb ldr r3, [r7, #12]
8009140: 681b ldr r3, [r3, #0]
8009142: 68b9 ldr r1, [r7, #8]
8009144: 4618 mov r0, r3
8009146: f000 fb8f bl 8009868 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
800914a: 68fb ldr r3, [r7, #12]
800914c: 681b ldr r3, [r3, #0]
800914e: 69da ldr r2, [r3, #28]
8009150: 68fb ldr r3, [r7, #12]
8009152: 681b ldr r3, [r3, #0]
8009154: f442 6200 orr.w r2, r2, #2048 ; 0x800
8009158: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
800915a: 68fb ldr r3, [r7, #12]
800915c: 681b ldr r3, [r3, #0]
800915e: 69da ldr r2, [r3, #28]
8009160: 68fb ldr r3, [r7, #12]
8009162: 681b ldr r3, [r3, #0]
8009164: f422 6280 bic.w r2, r2, #1024 ; 0x400
8009168: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800916a: 68fb ldr r3, [r7, #12]
800916c: 681b ldr r3, [r3, #0]
800916e: 69d9 ldr r1, [r3, #28]
8009170: 68bb ldr r3, [r7, #8]
8009172: 691b ldr r3, [r3, #16]
8009174: 021a lsls r2, r3, #8
8009176: 68fb ldr r3, [r7, #12]
8009178: 681b ldr r3, [r3, #0]
800917a: 430a orrs r2, r1
800917c: 61da str r2, [r3, #28]
break;
800917e: e041 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the Channel 5 in PWM mode */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8009180: 68fb ldr r3, [r7, #12]
8009182: 681b ldr r3, [r3, #0]
8009184: 68b9 ldr r1, [r7, #8]
8009186: 4618 mov r0, r3
8009188: f000 fbc6 bl 8009918 <TIM_OC5_SetConfig>
/* Set the Preload enable bit for channel5*/
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
800918c: 68fb ldr r3, [r7, #12]
800918e: 681b ldr r3, [r3, #0]
8009190: 6d5a ldr r2, [r3, #84] ; 0x54
8009192: 68fb ldr r3, [r7, #12]
8009194: 681b ldr r3, [r3, #0]
8009196: f042 0208 orr.w r2, r2, #8
800919a: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
800919c: 68fb ldr r3, [r7, #12]
800919e: 681b ldr r3, [r3, #0]
80091a0: 6d5a ldr r2, [r3, #84] ; 0x54
80091a2: 68fb ldr r3, [r7, #12]
80091a4: 681b ldr r3, [r3, #0]
80091a6: f022 0204 bic.w r2, r2, #4
80091aa: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
80091ac: 68fb ldr r3, [r7, #12]
80091ae: 681b ldr r3, [r3, #0]
80091b0: 6d59 ldr r1, [r3, #84] ; 0x54
80091b2: 68bb ldr r3, [r7, #8]
80091b4: 691a ldr r2, [r3, #16]
80091b6: 68fb ldr r3, [r7, #12]
80091b8: 681b ldr r3, [r3, #0]
80091ba: 430a orrs r2, r1
80091bc: 655a str r2, [r3, #84] ; 0x54
break;
80091be: e021 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the Channel 6 in PWM mode */
TIM_OC6_SetConfig(htim->Instance, sConfig);
80091c0: 68fb ldr r3, [r7, #12]
80091c2: 681b ldr r3, [r3, #0]
80091c4: 68b9 ldr r1, [r7, #8]
80091c6: 4618 mov r0, r3
80091c8: f000 fbf8 bl 80099bc <TIM_OC6_SetConfig>
/* Set the Preload enable bit for channel6 */
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
80091cc: 68fb ldr r3, [r7, #12]
80091ce: 681b ldr r3, [r3, #0]
80091d0: 6d5a ldr r2, [r3, #84] ; 0x54
80091d2: 68fb ldr r3, [r7, #12]
80091d4: 681b ldr r3, [r3, #0]
80091d6: f442 6200 orr.w r2, r2, #2048 ; 0x800
80091da: 655a str r2, [r3, #84] ; 0x54
/* Configure the Output Fast mode */
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
80091dc: 68fb ldr r3, [r7, #12]
80091de: 681b ldr r3, [r3, #0]
80091e0: 6d5a ldr r2, [r3, #84] ; 0x54
80091e2: 68fb ldr r3, [r7, #12]
80091e4: 681b ldr r3, [r3, #0]
80091e6: f422 6280 bic.w r2, r2, #1024 ; 0x400
80091ea: 655a str r2, [r3, #84] ; 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
80091ec: 68fb ldr r3, [r7, #12]
80091ee: 681b ldr r3, [r3, #0]
80091f0: 6d59 ldr r1, [r3, #84] ; 0x54
80091f2: 68bb ldr r3, [r7, #8]
80091f4: 691b ldr r3, [r3, #16]
80091f6: 021a lsls r2, r3, #8
80091f8: 68fb ldr r3, [r7, #12]
80091fa: 681b ldr r3, [r3, #0]
80091fc: 430a orrs r2, r1
80091fe: 655a str r2, [r3, #84] ; 0x54
break;
8009200: e000 b.n 8009204 <HAL_TIM_PWM_ConfigChannel+0x214>
}
default:
break;
8009202: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8009204: 68fb ldr r3, [r7, #12]
8009206: 2201 movs r2, #1
8009208: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800920c: 68fb ldr r3, [r7, #12]
800920e: 2200 movs r2, #0
8009210: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8009214: 2300 movs r3, #0
}
8009216: 4618 mov r0, r3
8009218: 3710 adds r7, #16
800921a: 46bd mov sp, r7
800921c: bd80 pop {r7, pc}
800921e: bf00 nop
08009220 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8009220: b580 push {r7, lr}
8009222: b084 sub sp, #16
8009224: af00 add r7, sp, #0
8009226: 6078 str r0, [r7, #4]
8009228: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800922a: 687b ldr r3, [r7, #4]
800922c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009230: 2b01 cmp r3, #1
8009232: d101 bne.n 8009238 <HAL_TIM_ConfigClockSource+0x18>
8009234: 2302 movs r3, #2
8009236: e0a6 b.n 8009386 <HAL_TIM_ConfigClockSource+0x166>
8009238: 687b ldr r3, [r7, #4]
800923a: 2201 movs r2, #1
800923c: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8009240: 687b ldr r3, [r7, #4]
8009242: 2202 movs r2, #2
8009244: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8009248: 687b ldr r3, [r7, #4]
800924a: 681b ldr r3, [r3, #0]
800924c: 689b ldr r3, [r3, #8]
800924e: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8009250: 68fa ldr r2, [r7, #12]
8009252: 4b4f ldr r3, [pc, #316] ; (8009390 <HAL_TIM_ConfigClockSource+0x170>)
8009254: 4013 ands r3, r2
8009256: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8009258: 68fb ldr r3, [r7, #12]
800925a: f423 437f bic.w r3, r3, #65280 ; 0xff00
800925e: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8009260: 687b ldr r3, [r7, #4]
8009262: 681b ldr r3, [r3, #0]
8009264: 68fa ldr r2, [r7, #12]
8009266: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8009268: 683b ldr r3, [r7, #0]
800926a: 681b ldr r3, [r3, #0]
800926c: 2b40 cmp r3, #64 ; 0x40
800926e: d067 beq.n 8009340 <HAL_TIM_ConfigClockSource+0x120>
8009270: 2b40 cmp r3, #64 ; 0x40
8009272: d80b bhi.n 800928c <HAL_TIM_ConfigClockSource+0x6c>
8009274: 2b10 cmp r3, #16
8009276: d073 beq.n 8009360 <HAL_TIM_ConfigClockSource+0x140>
8009278: 2b10 cmp r3, #16
800927a: d802 bhi.n 8009282 <HAL_TIM_ConfigClockSource+0x62>
800927c: 2b00 cmp r3, #0
800927e: d06f beq.n 8009360 <HAL_TIM_ConfigClockSource+0x140>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
8009280: e078 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
8009282: 2b20 cmp r3, #32
8009284: d06c beq.n 8009360 <HAL_TIM_ConfigClockSource+0x140>
8009286: 2b30 cmp r3, #48 ; 0x30
8009288: d06a beq.n 8009360 <HAL_TIM_ConfigClockSource+0x140>
break;
800928a: e073 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800928c: 2b70 cmp r3, #112 ; 0x70
800928e: d00d beq.n 80092ac <HAL_TIM_ConfigClockSource+0x8c>
8009290: 2b70 cmp r3, #112 ; 0x70
8009292: d804 bhi.n 800929e <HAL_TIM_ConfigClockSource+0x7e>
8009294: 2b50 cmp r3, #80 ; 0x50
8009296: d033 beq.n 8009300 <HAL_TIM_ConfigClockSource+0xe0>
8009298: 2b60 cmp r3, #96 ; 0x60
800929a: d041 beq.n 8009320 <HAL_TIM_ConfigClockSource+0x100>
break;
800929c: e06a b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
800929e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80092a2: d066 beq.n 8009372 <HAL_TIM_ConfigClockSource+0x152>
80092a4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
80092a8: d017 beq.n 80092da <HAL_TIM_ConfigClockSource+0xba>
break;
80092aa: e063 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
80092ac: 687b ldr r3, [r7, #4]
80092ae: 6818 ldr r0, [r3, #0]
80092b0: 683b ldr r3, [r7, #0]
80092b2: 6899 ldr r1, [r3, #8]
80092b4: 683b ldr r3, [r7, #0]
80092b6: 685a ldr r2, [r3, #4]
80092b8: 683b ldr r3, [r7, #0]
80092ba: 68db ldr r3, [r3, #12]
80092bc: f000 fcd4 bl 8009c68 <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
80092c0: 687b ldr r3, [r7, #4]
80092c2: 681b ldr r3, [r3, #0]
80092c4: 689b ldr r3, [r3, #8]
80092c6: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80092c8: 68fb ldr r3, [r7, #12]
80092ca: f043 0377 orr.w r3, r3, #119 ; 0x77
80092ce: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
80092d0: 687b ldr r3, [r7, #4]
80092d2: 681b ldr r3, [r3, #0]
80092d4: 68fa ldr r2, [r7, #12]
80092d6: 609a str r2, [r3, #8]
break;
80092d8: e04c b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
80092da: 687b ldr r3, [r7, #4]
80092dc: 6818 ldr r0, [r3, #0]
80092de: 683b ldr r3, [r7, #0]
80092e0: 6899 ldr r1, [r3, #8]
80092e2: 683b ldr r3, [r7, #0]
80092e4: 685a ldr r2, [r3, #4]
80092e6: 683b ldr r3, [r7, #0]
80092e8: 68db ldr r3, [r3, #12]
80092ea: f000 fcbd bl 8009c68 <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
80092ee: 687b ldr r3, [r7, #4]
80092f0: 681b ldr r3, [r3, #0]
80092f2: 689a ldr r2, [r3, #8]
80092f4: 687b ldr r3, [r7, #4]
80092f6: 681b ldr r3, [r3, #0]
80092f8: f442 4280 orr.w r2, r2, #16384 ; 0x4000
80092fc: 609a str r2, [r3, #8]
break;
80092fe: e039 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
8009300: 687b ldr r3, [r7, #4]
8009302: 6818 ldr r0, [r3, #0]
8009304: 683b ldr r3, [r7, #0]
8009306: 6859 ldr r1, [r3, #4]
8009308: 683b ldr r3, [r7, #0]
800930a: 68db ldr r3, [r3, #12]
800930c: 461a mov r2, r3
800930e: f000 fc31 bl 8009b74 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8009312: 687b ldr r3, [r7, #4]
8009314: 681b ldr r3, [r3, #0]
8009316: 2150 movs r1, #80 ; 0x50
8009318: 4618 mov r0, r3
800931a: f000 fc8a bl 8009c32 <TIM_ITRx_SetConfig>
break;
800931e: e029 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI2_ConfigInputStage(htim->Instance,
8009320: 687b ldr r3, [r7, #4]
8009322: 6818 ldr r0, [r3, #0]
8009324: 683b ldr r3, [r7, #0]
8009326: 6859 ldr r1, [r3, #4]
8009328: 683b ldr r3, [r7, #0]
800932a: 68db ldr r3, [r3, #12]
800932c: 461a mov r2, r3
800932e: f000 fc50 bl 8009bd2 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8009332: 687b ldr r3, [r7, #4]
8009334: 681b ldr r3, [r3, #0]
8009336: 2160 movs r1, #96 ; 0x60
8009338: 4618 mov r0, r3
800933a: f000 fc7a bl 8009c32 <TIM_ITRx_SetConfig>
break;
800933e: e019 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
8009340: 687b ldr r3, [r7, #4]
8009342: 6818 ldr r0, [r3, #0]
8009344: 683b ldr r3, [r7, #0]
8009346: 6859 ldr r1, [r3, #4]
8009348: 683b ldr r3, [r7, #0]
800934a: 68db ldr r3, [r3, #12]
800934c: 461a mov r2, r3
800934e: f000 fc11 bl 8009b74 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8009352: 687b ldr r3, [r7, #4]
8009354: 681b ldr r3, [r3, #0]
8009356: 2140 movs r1, #64 ; 0x40
8009358: 4618 mov r0, r3
800935a: f000 fc6a bl 8009c32 <TIM_ITRx_SetConfig>
break;
800935e: e009 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8009360: 687b ldr r3, [r7, #4]
8009362: 681a ldr r2, [r3, #0]
8009364: 683b ldr r3, [r7, #0]
8009366: 681b ldr r3, [r3, #0]
8009368: 4619 mov r1, r3
800936a: 4610 mov r0, r2
800936c: f000 fc61 bl 8009c32 <TIM_ITRx_SetConfig>
break;
8009370: e000 b.n 8009374 <HAL_TIM_ConfigClockSource+0x154>
break;
8009372: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8009374: 687b ldr r3, [r7, #4]
8009376: 2201 movs r2, #1
8009378: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800937c: 687b ldr r3, [r7, #4]
800937e: 2200 movs r2, #0
8009380: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8009384: 2300 movs r3, #0
}
8009386: 4618 mov r0, r3
8009388: 3710 adds r7, #16
800938a: 46bd mov sp, r7
800938c: bd80 pop {r7, pc}
800938e: bf00 nop
8009390: fffeff88 .word 0xfffeff88
08009394 <HAL_TIM_SlaveConfigSynchro>:
* timer input or external trigger input) and the Slave mode
* (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
8009394: b580 push {r7, lr}
8009396: b082 sub sp, #8
8009398: af00 add r7, sp, #0
800939a: 6078 str r0, [r7, #4]
800939c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
__HAL_LOCK(htim);
800939e: 687b ldr r3, [r7, #4]
80093a0: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80093a4: 2b01 cmp r3, #1
80093a6: d101 bne.n 80093ac <HAL_TIM_SlaveConfigSynchro+0x18>
80093a8: 2302 movs r3, #2
80093aa: e031 b.n 8009410 <HAL_TIM_SlaveConfigSynchro+0x7c>
80093ac: 687b ldr r3, [r7, #4]
80093ae: 2201 movs r2, #1
80093b0: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
80093b4: 687b ldr r3, [r7, #4]
80093b6: 2202 movs r2, #2
80093b8: f883 203d strb.w r2, [r3, #61] ; 0x3d
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
80093bc: 6839 ldr r1, [r7, #0]
80093be: 6878 ldr r0, [r7, #4]
80093c0: f000 fb50 bl 8009a64 <TIM_SlaveTimer_SetConfig>
80093c4: 4603 mov r3, r0
80093c6: 2b00 cmp r3, #0
80093c8: d009 beq.n 80093de <HAL_TIM_SlaveConfigSynchro+0x4a>
{
htim->State = HAL_TIM_STATE_READY;
80093ca: 687b ldr r3, [r7, #4]
80093cc: 2201 movs r2, #1
80093ce: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
80093d2: 687b ldr r3, [r7, #4]
80093d4: 2200 movs r2, #0
80093d6: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
80093da: 2301 movs r3, #1
80093dc: e018 b.n 8009410 <HAL_TIM_SlaveConfigSynchro+0x7c>
}
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
80093de: 687b ldr r3, [r7, #4]
80093e0: 681b ldr r3, [r3, #0]
80093e2: 68da ldr r2, [r3, #12]
80093e4: 687b ldr r3, [r7, #4]
80093e6: 681b ldr r3, [r3, #0]
80093e8: f022 0240 bic.w r2, r2, #64 ; 0x40
80093ec: 60da str r2, [r3, #12]
/* Disable Trigger DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
80093ee: 687b ldr r3, [r7, #4]
80093f0: 681b ldr r3, [r3, #0]
80093f2: 68da ldr r2, [r3, #12]
80093f4: 687b ldr r3, [r7, #4]
80093f6: 681b ldr r3, [r3, #0]
80093f8: f422 4280 bic.w r2, r2, #16384 ; 0x4000
80093fc: 60da str r2, [r3, #12]
htim->State = HAL_TIM_STATE_READY;
80093fe: 687b ldr r3, [r7, #4]
8009400: 2201 movs r2, #1
8009402: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8009406: 687b ldr r3, [r7, #4]
8009408: 2200 movs r2, #0
800940a: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
800940e: 2300 movs r3, #0
}
8009410: 4618 mov r0, r3
8009412: 3708 adds r7, #8
8009414: 46bd mov sp, r7
8009416: bd80 pop {r7, pc}
08009418 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8009418: b480 push {r7}
800941a: b083 sub sp, #12
800941c: af00 add r7, sp, #0
800941e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8009420: bf00 nop
8009422: 370c adds r7, #12
8009424: 46bd mov sp, r7
8009426: f85d 7b04 ldr.w r7, [sp], #4
800942a: 4770 bx lr
0800942c <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800942c: b480 push {r7}
800942e: b083 sub sp, #12
8009430: af00 add r7, sp, #0
8009432: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8009434: bf00 nop
8009436: 370c adds r7, #12
8009438: 46bd mov sp, r7
800943a: f85d 7b04 ldr.w r7, [sp], #4
800943e: 4770 bx lr
08009440 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8009440: b480 push {r7}
8009442: b083 sub sp, #12
8009444: af00 add r7, sp, #0
8009446: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8009448: bf00 nop
800944a: 370c adds r7, #12
800944c: 46bd mov sp, r7
800944e: f85d 7b04 ldr.w r7, [sp], #4
8009452: 4770 bx lr
08009454 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8009454: b480 push {r7}
8009456: b083 sub sp, #12
8009458: af00 add r7, sp, #0
800945a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800945c: bf00 nop
800945e: 370c adds r7, #12
8009460: 46bd mov sp, r7
8009462: f85d 7b04 ldr.w r7, [sp], #4
8009466: 4770 bx lr
08009468 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8009468: b480 push {r7}
800946a: b085 sub sp, #20
800946c: af00 add r7, sp, #0
800946e: 6078 str r0, [r7, #4]
8009470: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8009472: 687b ldr r3, [r7, #4]
8009474: 681b ldr r3, [r3, #0]
8009476: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8009478: 687b ldr r3, [r7, #4]
800947a: 4a40 ldr r2, [pc, #256] ; (800957c <TIM_Base_SetConfig+0x114>)
800947c: 4293 cmp r3, r2
800947e: d013 beq.n 80094a8 <TIM_Base_SetConfig+0x40>
8009480: 687b ldr r3, [r7, #4]
8009482: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8009486: d00f beq.n 80094a8 <TIM_Base_SetConfig+0x40>
8009488: 687b ldr r3, [r7, #4]
800948a: 4a3d ldr r2, [pc, #244] ; (8009580 <TIM_Base_SetConfig+0x118>)
800948c: 4293 cmp r3, r2
800948e: d00b beq.n 80094a8 <TIM_Base_SetConfig+0x40>
8009490: 687b ldr r3, [r7, #4]
8009492: 4a3c ldr r2, [pc, #240] ; (8009584 <TIM_Base_SetConfig+0x11c>)
8009494: 4293 cmp r3, r2
8009496: d007 beq.n 80094a8 <TIM_Base_SetConfig+0x40>
8009498: 687b ldr r3, [r7, #4]
800949a: 4a3b ldr r2, [pc, #236] ; (8009588 <TIM_Base_SetConfig+0x120>)
800949c: 4293 cmp r3, r2
800949e: d003 beq.n 80094a8 <TIM_Base_SetConfig+0x40>
80094a0: 687b ldr r3, [r7, #4]
80094a2: 4a3a ldr r2, [pc, #232] ; (800958c <TIM_Base_SetConfig+0x124>)
80094a4: 4293 cmp r3, r2
80094a6: d108 bne.n 80094ba <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
80094a8: 68fb ldr r3, [r7, #12]
80094aa: f023 0370 bic.w r3, r3, #112 ; 0x70
80094ae: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80094b0: 683b ldr r3, [r7, #0]
80094b2: 685b ldr r3, [r3, #4]
80094b4: 68fa ldr r2, [r7, #12]
80094b6: 4313 orrs r3, r2
80094b8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80094ba: 687b ldr r3, [r7, #4]
80094bc: 4a2f ldr r2, [pc, #188] ; (800957c <TIM_Base_SetConfig+0x114>)
80094be: 4293 cmp r3, r2
80094c0: d02b beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094c2: 687b ldr r3, [r7, #4]
80094c4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80094c8: d027 beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094ca: 687b ldr r3, [r7, #4]
80094cc: 4a2c ldr r2, [pc, #176] ; (8009580 <TIM_Base_SetConfig+0x118>)
80094ce: 4293 cmp r3, r2
80094d0: d023 beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094d2: 687b ldr r3, [r7, #4]
80094d4: 4a2b ldr r2, [pc, #172] ; (8009584 <TIM_Base_SetConfig+0x11c>)
80094d6: 4293 cmp r3, r2
80094d8: d01f beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094da: 687b ldr r3, [r7, #4]
80094dc: 4a2a ldr r2, [pc, #168] ; (8009588 <TIM_Base_SetConfig+0x120>)
80094de: 4293 cmp r3, r2
80094e0: d01b beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094e2: 687b ldr r3, [r7, #4]
80094e4: 4a29 ldr r2, [pc, #164] ; (800958c <TIM_Base_SetConfig+0x124>)
80094e6: 4293 cmp r3, r2
80094e8: d017 beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094ea: 687b ldr r3, [r7, #4]
80094ec: 4a28 ldr r2, [pc, #160] ; (8009590 <TIM_Base_SetConfig+0x128>)
80094ee: 4293 cmp r3, r2
80094f0: d013 beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094f2: 687b ldr r3, [r7, #4]
80094f4: 4a27 ldr r2, [pc, #156] ; (8009594 <TIM_Base_SetConfig+0x12c>)
80094f6: 4293 cmp r3, r2
80094f8: d00f beq.n 800951a <TIM_Base_SetConfig+0xb2>
80094fa: 687b ldr r3, [r7, #4]
80094fc: 4a26 ldr r2, [pc, #152] ; (8009598 <TIM_Base_SetConfig+0x130>)
80094fe: 4293 cmp r3, r2
8009500: d00b beq.n 800951a <TIM_Base_SetConfig+0xb2>
8009502: 687b ldr r3, [r7, #4]
8009504: 4a25 ldr r2, [pc, #148] ; (800959c <TIM_Base_SetConfig+0x134>)
8009506: 4293 cmp r3, r2
8009508: d007 beq.n 800951a <TIM_Base_SetConfig+0xb2>
800950a: 687b ldr r3, [r7, #4]
800950c: 4a24 ldr r2, [pc, #144] ; (80095a0 <TIM_Base_SetConfig+0x138>)
800950e: 4293 cmp r3, r2
8009510: d003 beq.n 800951a <TIM_Base_SetConfig+0xb2>
8009512: 687b ldr r3, [r7, #4]
8009514: 4a23 ldr r2, [pc, #140] ; (80095a4 <TIM_Base_SetConfig+0x13c>)
8009516: 4293 cmp r3, r2
8009518: d108 bne.n 800952c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800951a: 68fb ldr r3, [r7, #12]
800951c: f423 7340 bic.w r3, r3, #768 ; 0x300
8009520: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8009522: 683b ldr r3, [r7, #0]
8009524: 68db ldr r3, [r3, #12]
8009526: 68fa ldr r2, [r7, #12]
8009528: 4313 orrs r3, r2
800952a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800952c: 68fb ldr r3, [r7, #12]
800952e: f023 0280 bic.w r2, r3, #128 ; 0x80
8009532: 683b ldr r3, [r7, #0]
8009534: 695b ldr r3, [r3, #20]
8009536: 4313 orrs r3, r2
8009538: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800953a: 687b ldr r3, [r7, #4]
800953c: 68fa ldr r2, [r7, #12]
800953e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8009540: 683b ldr r3, [r7, #0]
8009542: 689a ldr r2, [r3, #8]
8009544: 687b ldr r3, [r7, #4]
8009546: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8009548: 683b ldr r3, [r7, #0]
800954a: 681a ldr r2, [r3, #0]
800954c: 687b ldr r3, [r7, #4]
800954e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8009550: 687b ldr r3, [r7, #4]
8009552: 4a0a ldr r2, [pc, #40] ; (800957c <TIM_Base_SetConfig+0x114>)
8009554: 4293 cmp r3, r2
8009556: d003 beq.n 8009560 <TIM_Base_SetConfig+0xf8>
8009558: 687b ldr r3, [r7, #4]
800955a: 4a0c ldr r2, [pc, #48] ; (800958c <TIM_Base_SetConfig+0x124>)
800955c: 4293 cmp r3, r2
800955e: d103 bne.n 8009568 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8009560: 683b ldr r3, [r7, #0]
8009562: 691a ldr r2, [r3, #16]
8009564: 687b ldr r3, [r7, #4]
8009566: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8009568: 687b ldr r3, [r7, #4]
800956a: 2201 movs r2, #1
800956c: 615a str r2, [r3, #20]
}
800956e: bf00 nop
8009570: 3714 adds r7, #20
8009572: 46bd mov sp, r7
8009574: f85d 7b04 ldr.w r7, [sp], #4
8009578: 4770 bx lr
800957a: bf00 nop
800957c: 40010000 .word 0x40010000
8009580: 40000400 .word 0x40000400
8009584: 40000800 .word 0x40000800
8009588: 40000c00 .word 0x40000c00
800958c: 40010400 .word 0x40010400
8009590: 40014000 .word 0x40014000
8009594: 40014400 .word 0x40014400
8009598: 40014800 .word 0x40014800
800959c: 40001800 .word 0x40001800
80095a0: 40001c00 .word 0x40001c00
80095a4: 40002000 .word 0x40002000
080095a8 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
80095a8: b480 push {r7}
80095aa: b087 sub sp, #28
80095ac: af00 add r7, sp, #0
80095ae: 6078 str r0, [r7, #4]
80095b0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80095b2: 687b ldr r3, [r7, #4]
80095b4: 6a1b ldr r3, [r3, #32]
80095b6: f023 0201 bic.w r2, r3, #1
80095ba: 687b ldr r3, [r7, #4]
80095bc: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80095be: 687b ldr r3, [r7, #4]
80095c0: 6a1b ldr r3, [r3, #32]
80095c2: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80095c4: 687b ldr r3, [r7, #4]
80095c6: 685b ldr r3, [r3, #4]
80095c8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80095ca: 687b ldr r3, [r7, #4]
80095cc: 699b ldr r3, [r3, #24]
80095ce: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
80095d0: 68fa ldr r2, [r7, #12]
80095d2: 4b2b ldr r3, [pc, #172] ; (8009680 <TIM_OC1_SetConfig+0xd8>)
80095d4: 4013 ands r3, r2
80095d6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80095d8: 68fb ldr r3, [r7, #12]
80095da: f023 0303 bic.w r3, r3, #3
80095de: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80095e0: 683b ldr r3, [r7, #0]
80095e2: 681b ldr r3, [r3, #0]
80095e4: 68fa ldr r2, [r7, #12]
80095e6: 4313 orrs r3, r2
80095e8: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
80095ea: 697b ldr r3, [r7, #20]
80095ec: f023 0302 bic.w r3, r3, #2
80095f0: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
80095f2: 683b ldr r3, [r7, #0]
80095f4: 689b ldr r3, [r3, #8]
80095f6: 697a ldr r2, [r7, #20]
80095f8: 4313 orrs r3, r2
80095fa: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
80095fc: 687b ldr r3, [r7, #4]
80095fe: 4a21 ldr r2, [pc, #132] ; (8009684 <TIM_OC1_SetConfig+0xdc>)
8009600: 4293 cmp r3, r2
8009602: d003 beq.n 800960c <TIM_OC1_SetConfig+0x64>
8009604: 687b ldr r3, [r7, #4]
8009606: 4a20 ldr r2, [pc, #128] ; (8009688 <TIM_OC1_SetConfig+0xe0>)
8009608: 4293 cmp r3, r2
800960a: d10c bne.n 8009626 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800960c: 697b ldr r3, [r7, #20]
800960e: f023 0308 bic.w r3, r3, #8
8009612: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8009614: 683b ldr r3, [r7, #0]
8009616: 68db ldr r3, [r3, #12]
8009618: 697a ldr r2, [r7, #20]
800961a: 4313 orrs r3, r2
800961c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
800961e: 697b ldr r3, [r7, #20]
8009620: f023 0304 bic.w r3, r3, #4
8009624: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8009626: 687b ldr r3, [r7, #4]
8009628: 4a16 ldr r2, [pc, #88] ; (8009684 <TIM_OC1_SetConfig+0xdc>)
800962a: 4293 cmp r3, r2
800962c: d003 beq.n 8009636 <TIM_OC1_SetConfig+0x8e>
800962e: 687b ldr r3, [r7, #4]
8009630: 4a15 ldr r2, [pc, #84] ; (8009688 <TIM_OC1_SetConfig+0xe0>)
8009632: 4293 cmp r3, r2
8009634: d111 bne.n 800965a <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8009636: 693b ldr r3, [r7, #16]
8009638: f423 7380 bic.w r3, r3, #256 ; 0x100
800963c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
800963e: 693b ldr r3, [r7, #16]
8009640: f423 7300 bic.w r3, r3, #512 ; 0x200
8009644: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8009646: 683b ldr r3, [r7, #0]
8009648: 695b ldr r3, [r3, #20]
800964a: 693a ldr r2, [r7, #16]
800964c: 4313 orrs r3, r2
800964e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8009650: 683b ldr r3, [r7, #0]
8009652: 699b ldr r3, [r3, #24]
8009654: 693a ldr r2, [r7, #16]
8009656: 4313 orrs r3, r2
8009658: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800965a: 687b ldr r3, [r7, #4]
800965c: 693a ldr r2, [r7, #16]
800965e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8009660: 687b ldr r3, [r7, #4]
8009662: 68fa ldr r2, [r7, #12]
8009664: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8009666: 683b ldr r3, [r7, #0]
8009668: 685a ldr r2, [r3, #4]
800966a: 687b ldr r3, [r7, #4]
800966c: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800966e: 687b ldr r3, [r7, #4]
8009670: 697a ldr r2, [r7, #20]
8009672: 621a str r2, [r3, #32]
}
8009674: bf00 nop
8009676: 371c adds r7, #28
8009678: 46bd mov sp, r7
800967a: f85d 7b04 ldr.w r7, [sp], #4
800967e: 4770 bx lr
8009680: fffeff8f .word 0xfffeff8f
8009684: 40010000 .word 0x40010000
8009688: 40010400 .word 0x40010400
0800968c <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800968c: b480 push {r7}
800968e: b087 sub sp, #28
8009690: af00 add r7, sp, #0
8009692: 6078 str r0, [r7, #4]
8009694: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8009696: 687b ldr r3, [r7, #4]
8009698: 6a1b ldr r3, [r3, #32]
800969a: f023 0210 bic.w r2, r3, #16
800969e: 687b ldr r3, [r7, #4]
80096a0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80096a2: 687b ldr r3, [r7, #4]
80096a4: 6a1b ldr r3, [r3, #32]
80096a6: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80096a8: 687b ldr r3, [r7, #4]
80096aa: 685b ldr r3, [r3, #4]
80096ac: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
80096ae: 687b ldr r3, [r7, #4]
80096b0: 699b ldr r3, [r3, #24]
80096b2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
80096b4: 68fa ldr r2, [r7, #12]
80096b6: 4b2e ldr r3, [pc, #184] ; (8009770 <TIM_OC2_SetConfig+0xe4>)
80096b8: 4013 ands r3, r2
80096ba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
80096bc: 68fb ldr r3, [r7, #12]
80096be: f423 7340 bic.w r3, r3, #768 ; 0x300
80096c2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80096c4: 683b ldr r3, [r7, #0]
80096c6: 681b ldr r3, [r3, #0]
80096c8: 021b lsls r3, r3, #8
80096ca: 68fa ldr r2, [r7, #12]
80096cc: 4313 orrs r3, r2
80096ce: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
80096d0: 697b ldr r3, [r7, #20]
80096d2: f023 0320 bic.w r3, r3, #32
80096d6: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
80096d8: 683b ldr r3, [r7, #0]
80096da: 689b ldr r3, [r3, #8]
80096dc: 011b lsls r3, r3, #4
80096de: 697a ldr r2, [r7, #20]
80096e0: 4313 orrs r3, r2
80096e2: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
80096e4: 687b ldr r3, [r7, #4]
80096e6: 4a23 ldr r2, [pc, #140] ; (8009774 <TIM_OC2_SetConfig+0xe8>)
80096e8: 4293 cmp r3, r2
80096ea: d003 beq.n 80096f4 <TIM_OC2_SetConfig+0x68>
80096ec: 687b ldr r3, [r7, #4]
80096ee: 4a22 ldr r2, [pc, #136] ; (8009778 <TIM_OC2_SetConfig+0xec>)
80096f0: 4293 cmp r3, r2
80096f2: d10d bne.n 8009710 <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
80096f4: 697b ldr r3, [r7, #20]
80096f6: f023 0380 bic.w r3, r3, #128 ; 0x80
80096fa: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
80096fc: 683b ldr r3, [r7, #0]
80096fe: 68db ldr r3, [r3, #12]
8009700: 011b lsls r3, r3, #4
8009702: 697a ldr r2, [r7, #20]
8009704: 4313 orrs r3, r2
8009706: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8009708: 697b ldr r3, [r7, #20]
800970a: f023 0340 bic.w r3, r3, #64 ; 0x40
800970e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8009710: 687b ldr r3, [r7, #4]
8009712: 4a18 ldr r2, [pc, #96] ; (8009774 <TIM_OC2_SetConfig+0xe8>)
8009714: 4293 cmp r3, r2
8009716: d003 beq.n 8009720 <TIM_OC2_SetConfig+0x94>
8009718: 687b ldr r3, [r7, #4]
800971a: 4a17 ldr r2, [pc, #92] ; (8009778 <TIM_OC2_SetConfig+0xec>)
800971c: 4293 cmp r3, r2
800971e: d113 bne.n 8009748 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8009720: 693b ldr r3, [r7, #16]
8009722: f423 6380 bic.w r3, r3, #1024 ; 0x400
8009726: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8009728: 693b ldr r3, [r7, #16]
800972a: f423 6300 bic.w r3, r3, #2048 ; 0x800
800972e: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8009730: 683b ldr r3, [r7, #0]
8009732: 695b ldr r3, [r3, #20]
8009734: 009b lsls r3, r3, #2
8009736: 693a ldr r2, [r7, #16]
8009738: 4313 orrs r3, r2
800973a: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
800973c: 683b ldr r3, [r7, #0]
800973e: 699b ldr r3, [r3, #24]
8009740: 009b lsls r3, r3, #2
8009742: 693a ldr r2, [r7, #16]
8009744: 4313 orrs r3, r2
8009746: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8009748: 687b ldr r3, [r7, #4]
800974a: 693a ldr r2, [r7, #16]
800974c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
800974e: 687b ldr r3, [r7, #4]
8009750: 68fa ldr r2, [r7, #12]
8009752: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8009754: 683b ldr r3, [r7, #0]
8009756: 685a ldr r2, [r3, #4]
8009758: 687b ldr r3, [r7, #4]
800975a: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800975c: 687b ldr r3, [r7, #4]
800975e: 697a ldr r2, [r7, #20]
8009760: 621a str r2, [r3, #32]
}
8009762: bf00 nop
8009764: 371c adds r7, #28
8009766: 46bd mov sp, r7
8009768: f85d 7b04 ldr.w r7, [sp], #4
800976c: 4770 bx lr
800976e: bf00 nop
8009770: feff8fff .word 0xfeff8fff
8009774: 40010000 .word 0x40010000
8009778: 40010400 .word 0x40010400
0800977c <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
800977c: b480 push {r7}
800977e: b087 sub sp, #28
8009780: af00 add r7, sp, #0
8009782: 6078 str r0, [r7, #4]
8009784: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8009786: 687b ldr r3, [r7, #4]
8009788: 6a1b ldr r3, [r3, #32]
800978a: f423 7280 bic.w r2, r3, #256 ; 0x100
800978e: 687b ldr r3, [r7, #4]
8009790: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8009792: 687b ldr r3, [r7, #4]
8009794: 6a1b ldr r3, [r3, #32]
8009796: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8009798: 687b ldr r3, [r7, #4]
800979a: 685b ldr r3, [r3, #4]
800979c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800979e: 687b ldr r3, [r7, #4]
80097a0: 69db ldr r3, [r3, #28]
80097a2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
80097a4: 68fa ldr r2, [r7, #12]
80097a6: 4b2d ldr r3, [pc, #180] ; (800985c <TIM_OC3_SetConfig+0xe0>)
80097a8: 4013 ands r3, r2
80097aa: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
80097ac: 68fb ldr r3, [r7, #12]
80097ae: f023 0303 bic.w r3, r3, #3
80097b2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80097b4: 683b ldr r3, [r7, #0]
80097b6: 681b ldr r3, [r3, #0]
80097b8: 68fa ldr r2, [r7, #12]
80097ba: 4313 orrs r3, r2
80097bc: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
80097be: 697b ldr r3, [r7, #20]
80097c0: f423 7300 bic.w r3, r3, #512 ; 0x200
80097c4: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
80097c6: 683b ldr r3, [r7, #0]
80097c8: 689b ldr r3, [r3, #8]
80097ca: 021b lsls r3, r3, #8
80097cc: 697a ldr r2, [r7, #20]
80097ce: 4313 orrs r3, r2
80097d0: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
80097d2: 687b ldr r3, [r7, #4]
80097d4: 4a22 ldr r2, [pc, #136] ; (8009860 <TIM_OC3_SetConfig+0xe4>)
80097d6: 4293 cmp r3, r2
80097d8: d003 beq.n 80097e2 <TIM_OC3_SetConfig+0x66>
80097da: 687b ldr r3, [r7, #4]
80097dc: 4a21 ldr r2, [pc, #132] ; (8009864 <TIM_OC3_SetConfig+0xe8>)
80097de: 4293 cmp r3, r2
80097e0: d10d bne.n 80097fe <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
80097e2: 697b ldr r3, [r7, #20]
80097e4: f423 6300 bic.w r3, r3, #2048 ; 0x800
80097e8: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80097ea: 683b ldr r3, [r7, #0]
80097ec: 68db ldr r3, [r3, #12]
80097ee: 021b lsls r3, r3, #8
80097f0: 697a ldr r2, [r7, #20]
80097f2: 4313 orrs r3, r2
80097f4: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80097f6: 697b ldr r3, [r7, #20]
80097f8: f423 6380 bic.w r3, r3, #1024 ; 0x400
80097fc: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80097fe: 687b ldr r3, [r7, #4]
8009800: 4a17 ldr r2, [pc, #92] ; (8009860 <TIM_OC3_SetConfig+0xe4>)
8009802: 4293 cmp r3, r2
8009804: d003 beq.n 800980e <TIM_OC3_SetConfig+0x92>
8009806: 687b ldr r3, [r7, #4]
8009808: 4a16 ldr r2, [pc, #88] ; (8009864 <TIM_OC3_SetConfig+0xe8>)
800980a: 4293 cmp r3, r2
800980c: d113 bne.n 8009836 <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
800980e: 693b ldr r3, [r7, #16]
8009810: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8009814: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
8009816: 693b ldr r3, [r7, #16]
8009818: f423 5300 bic.w r3, r3, #8192 ; 0x2000
800981c: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
800981e: 683b ldr r3, [r7, #0]
8009820: 695b ldr r3, [r3, #20]
8009822: 011b lsls r3, r3, #4
8009824: 693a ldr r2, [r7, #16]
8009826: 4313 orrs r3, r2
8009828: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
800982a: 683b ldr r3, [r7, #0]
800982c: 699b ldr r3, [r3, #24]
800982e: 011b lsls r3, r3, #4
8009830: 693a ldr r2, [r7, #16]
8009832: 4313 orrs r3, r2
8009834: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8009836: 687b ldr r3, [r7, #4]
8009838: 693a ldr r2, [r7, #16]
800983a: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800983c: 687b ldr r3, [r7, #4]
800983e: 68fa ldr r2, [r7, #12]
8009840: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
8009842: 683b ldr r3, [r7, #0]
8009844: 685a ldr r2, [r3, #4]
8009846: 687b ldr r3, [r7, #4]
8009848: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800984a: 687b ldr r3, [r7, #4]
800984c: 697a ldr r2, [r7, #20]
800984e: 621a str r2, [r3, #32]
}
8009850: bf00 nop
8009852: 371c adds r7, #28
8009854: 46bd mov sp, r7
8009856: f85d 7b04 ldr.w r7, [sp], #4
800985a: 4770 bx lr
800985c: fffeff8f .word 0xfffeff8f
8009860: 40010000 .word 0x40010000
8009864: 40010400 .word 0x40010400
08009868 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
8009868: b480 push {r7}
800986a: b087 sub sp, #28
800986c: af00 add r7, sp, #0
800986e: 6078 str r0, [r7, #4]
8009870: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
8009872: 687b ldr r3, [r7, #4]
8009874: 6a1b ldr r3, [r3, #32]
8009876: f423 5280 bic.w r2, r3, #4096 ; 0x1000
800987a: 687b ldr r3, [r7, #4]
800987c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800987e: 687b ldr r3, [r7, #4]
8009880: 6a1b ldr r3, [r3, #32]
8009882: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8009884: 687b ldr r3, [r7, #4]
8009886: 685b ldr r3, [r3, #4]
8009888: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800988a: 687b ldr r3, [r7, #4]
800988c: 69db ldr r3, [r3, #28]
800988e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8009890: 68fa ldr r2, [r7, #12]
8009892: 4b1e ldr r3, [pc, #120] ; (800990c <TIM_OC4_SetConfig+0xa4>)
8009894: 4013 ands r3, r2
8009896: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8009898: 68fb ldr r3, [r7, #12]
800989a: f423 7340 bic.w r3, r3, #768 ; 0x300
800989e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80098a0: 683b ldr r3, [r7, #0]
80098a2: 681b ldr r3, [r3, #0]
80098a4: 021b lsls r3, r3, #8
80098a6: 68fa ldr r2, [r7, #12]
80098a8: 4313 orrs r3, r2
80098aa: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80098ac: 693b ldr r3, [r7, #16]
80098ae: f423 5300 bic.w r3, r3, #8192 ; 0x2000
80098b2: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80098b4: 683b ldr r3, [r7, #0]
80098b6: 689b ldr r3, [r3, #8]
80098b8: 031b lsls r3, r3, #12
80098ba: 693a ldr r2, [r7, #16]
80098bc: 4313 orrs r3, r2
80098be: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80098c0: 687b ldr r3, [r7, #4]
80098c2: 4a13 ldr r2, [pc, #76] ; (8009910 <TIM_OC4_SetConfig+0xa8>)
80098c4: 4293 cmp r3, r2
80098c6: d003 beq.n 80098d0 <TIM_OC4_SetConfig+0x68>
80098c8: 687b ldr r3, [r7, #4]
80098ca: 4a12 ldr r2, [pc, #72] ; (8009914 <TIM_OC4_SetConfig+0xac>)
80098cc: 4293 cmp r3, r2
80098ce: d109 bne.n 80098e4 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80098d0: 697b ldr r3, [r7, #20]
80098d2: f423 4380 bic.w r3, r3, #16384 ; 0x4000
80098d6: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80098d8: 683b ldr r3, [r7, #0]
80098da: 695b ldr r3, [r3, #20]
80098dc: 019b lsls r3, r3, #6
80098de: 697a ldr r2, [r7, #20]
80098e0: 4313 orrs r3, r2
80098e2: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80098e4: 687b ldr r3, [r7, #4]
80098e6: 697a ldr r2, [r7, #20]
80098e8: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
80098ea: 687b ldr r3, [r7, #4]
80098ec: 68fa ldr r2, [r7, #12]
80098ee: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
80098f0: 683b ldr r3, [r7, #0]
80098f2: 685a ldr r2, [r3, #4]
80098f4: 687b ldr r3, [r7, #4]
80098f6: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80098f8: 687b ldr r3, [r7, #4]
80098fa: 693a ldr r2, [r7, #16]
80098fc: 621a str r2, [r3, #32]
}
80098fe: bf00 nop
8009900: 371c adds r7, #28
8009902: 46bd mov sp, r7
8009904: f85d 7b04 ldr.w r7, [sp], #4
8009908: 4770 bx lr
800990a: bf00 nop
800990c: feff8fff .word 0xfeff8fff
8009910: 40010000 .word 0x40010000
8009914: 40010400 .word 0x40010400
08009918 <TIM_OC5_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
8009918: b480 push {r7}
800991a: b087 sub sp, #28
800991c: af00 add r7, sp, #0
800991e: 6078 str r0, [r7, #4]
8009920: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8009922: 687b ldr r3, [r7, #4]
8009924: 6a1b ldr r3, [r3, #32]
8009926: f423 3280 bic.w r2, r3, #65536 ; 0x10000
800992a: 687b ldr r3, [r7, #4]
800992c: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800992e: 687b ldr r3, [r7, #4]
8009930: 6a1b ldr r3, [r3, #32]
8009932: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8009934: 687b ldr r3, [r7, #4]
8009936: 685b ldr r3, [r3, #4]
8009938: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800993a: 687b ldr r3, [r7, #4]
800993c: 6d5b ldr r3, [r3, #84] ; 0x54
800993e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8009940: 68fa ldr r2, [r7, #12]
8009942: 4b1b ldr r3, [pc, #108] ; (80099b0 <TIM_OC5_SetConfig+0x98>)
8009944: 4013 ands r3, r2
8009946: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8009948: 683b ldr r3, [r7, #0]
800994a: 681b ldr r3, [r3, #0]
800994c: 68fa ldr r2, [r7, #12]
800994e: 4313 orrs r3, r2
8009950: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8009952: 693b ldr r3, [r7, #16]
8009954: f423 3300 bic.w r3, r3, #131072 ; 0x20000
8009958: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
800995a: 683b ldr r3, [r7, #0]
800995c: 689b ldr r3, [r3, #8]
800995e: 041b lsls r3, r3, #16
8009960: 693a ldr r2, [r7, #16]
8009962: 4313 orrs r3, r2
8009964: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8009966: 687b ldr r3, [r7, #4]
8009968: 4a12 ldr r2, [pc, #72] ; (80099b4 <TIM_OC5_SetConfig+0x9c>)
800996a: 4293 cmp r3, r2
800996c: d003 beq.n 8009976 <TIM_OC5_SetConfig+0x5e>
800996e: 687b ldr r3, [r7, #4]
8009970: 4a11 ldr r2, [pc, #68] ; (80099b8 <TIM_OC5_SetConfig+0xa0>)
8009972: 4293 cmp r3, r2
8009974: d109 bne.n 800998a <TIM_OC5_SetConfig+0x72>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8009976: 697b ldr r3, [r7, #20]
8009978: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800997c: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
800997e: 683b ldr r3, [r7, #0]
8009980: 695b ldr r3, [r3, #20]
8009982: 021b lsls r3, r3, #8
8009984: 697a ldr r2, [r7, #20]
8009986: 4313 orrs r3, r2
8009988: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800998a: 687b ldr r3, [r7, #4]
800998c: 697a ldr r2, [r7, #20]
800998e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8009990: 687b ldr r3, [r7, #4]
8009992: 68fa ldr r2, [r7, #12]
8009994: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8009996: 683b ldr r3, [r7, #0]
8009998: 685a ldr r2, [r3, #4]
800999a: 687b ldr r3, [r7, #4]
800999c: 659a str r2, [r3, #88] ; 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800999e: 687b ldr r3, [r7, #4]
80099a0: 693a ldr r2, [r7, #16]
80099a2: 621a str r2, [r3, #32]
}
80099a4: bf00 nop
80099a6: 371c adds r7, #28
80099a8: 46bd mov sp, r7
80099aa: f85d 7b04 ldr.w r7, [sp], #4
80099ae: 4770 bx lr
80099b0: fffeff8f .word 0xfffeff8f
80099b4: 40010000 .word 0x40010000
80099b8: 40010400 .word 0x40010400
080099bc <TIM_OC6_SetConfig>:
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
TIM_OC_InitTypeDef *OC_Config)
{
80099bc: b480 push {r7}
80099be: b087 sub sp, #28
80099c0: af00 add r7, sp, #0
80099c2: 6078 str r0, [r7, #4]
80099c4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
80099c6: 687b ldr r3, [r7, #4]
80099c8: 6a1b ldr r3, [r3, #32]
80099ca: f423 1280 bic.w r2, r3, #1048576 ; 0x100000
80099ce: 687b ldr r3, [r7, #4]
80099d0: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
80099d2: 687b ldr r3, [r7, #4]
80099d4: 6a1b ldr r3, [r3, #32]
80099d6: 613b str r3, [r7, #16]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80099d8: 687b ldr r3, [r7, #4]
80099da: 685b ldr r3, [r3, #4]
80099dc: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
80099de: 687b ldr r3, [r7, #4]
80099e0: 6d5b ldr r3, [r3, #84] ; 0x54
80099e2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
80099e4: 68fa ldr r2, [r7, #12]
80099e6: 4b1c ldr r3, [pc, #112] ; (8009a58 <TIM_OC6_SetConfig+0x9c>)
80099e8: 4013 ands r3, r2
80099ea: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80099ec: 683b ldr r3, [r7, #0]
80099ee: 681b ldr r3, [r3, #0]
80099f0: 021b lsls r3, r3, #8
80099f2: 68fa ldr r2, [r7, #12]
80099f4: 4313 orrs r3, r2
80099f6: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
80099f8: 693b ldr r3, [r7, #16]
80099fa: f423 1300 bic.w r3, r3, #2097152 ; 0x200000
80099fe: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8009a00: 683b ldr r3, [r7, #0]
8009a02: 689b ldr r3, [r3, #8]
8009a04: 051b lsls r3, r3, #20
8009a06: 693a ldr r2, [r7, #16]
8009a08: 4313 orrs r3, r2
8009a0a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
8009a0c: 687b ldr r3, [r7, #4]
8009a0e: 4a13 ldr r2, [pc, #76] ; (8009a5c <TIM_OC6_SetConfig+0xa0>)
8009a10: 4293 cmp r3, r2
8009a12: d003 beq.n 8009a1c <TIM_OC6_SetConfig+0x60>
8009a14: 687b ldr r3, [r7, #4]
8009a16: 4a12 ldr r2, [pc, #72] ; (8009a60 <TIM_OC6_SetConfig+0xa4>)
8009a18: 4293 cmp r3, r2
8009a1a: d109 bne.n 8009a30 <TIM_OC6_SetConfig+0x74>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8009a1c: 697b ldr r3, [r7, #20]
8009a1e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8009a22: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8009a24: 683b ldr r3, [r7, #0]
8009a26: 695b ldr r3, [r3, #20]
8009a28: 029b lsls r3, r3, #10
8009a2a: 697a ldr r2, [r7, #20]
8009a2c: 4313 orrs r3, r2
8009a2e: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8009a30: 687b ldr r3, [r7, #4]
8009a32: 697a ldr r2, [r7, #20]
8009a34: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8009a36: 687b ldr r3, [r7, #4]
8009a38: 68fa ldr r2, [r7, #12]
8009a3a: 655a str r2, [r3, #84] ; 0x54
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8009a3c: 683b ldr r3, [r7, #0]
8009a3e: 685a ldr r2, [r3, #4]
8009a40: 687b ldr r3, [r7, #4]
8009a42: 65da str r2, [r3, #92] ; 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8009a44: 687b ldr r3, [r7, #4]
8009a46: 693a ldr r2, [r7, #16]
8009a48: 621a str r2, [r3, #32]
}
8009a4a: bf00 nop
8009a4c: 371c adds r7, #28
8009a4e: 46bd mov sp, r7
8009a50: f85d 7b04 ldr.w r7, [sp], #4
8009a54: 4770 bx lr
8009a56: bf00 nop
8009a58: feff8fff .word 0xfeff8fff
8009a5c: 40010000 .word 0x40010000
8009a60: 40010400 .word 0x40010400
08009a64 <TIM_SlaveTimer_SetConfig>:
* @param sSlaveConfig Slave timer configuration
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
8009a64: b580 push {r7, lr}
8009a66: b086 sub sp, #24
8009a68: af00 add r7, sp, #0
8009a6a: 6078 str r0, [r7, #4]
8009a6c: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8009a6e: 687b ldr r3, [r7, #4]
8009a70: 681b ldr r3, [r3, #0]
8009a72: 689b ldr r3, [r3, #8]
8009a74: 617b str r3, [r7, #20]
/* Reset the Trigger Selection Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8009a76: 697b ldr r3, [r7, #20]
8009a78: f023 0370 bic.w r3, r3, #112 ; 0x70
8009a7c: 617b str r3, [r7, #20]
/* Set the Input Trigger source */
tmpsmcr |= sSlaveConfig->InputTrigger;
8009a7e: 683b ldr r3, [r7, #0]
8009a80: 685b ldr r3, [r3, #4]
8009a82: 697a ldr r2, [r7, #20]
8009a84: 4313 orrs r3, r2
8009a86: 617b str r3, [r7, #20]
/* Reset the slave mode Bits */
tmpsmcr &= ~TIM_SMCR_SMS;
8009a88: 697a ldr r2, [r7, #20]
8009a8a: 4b39 ldr r3, [pc, #228] ; (8009b70 <TIM_SlaveTimer_SetConfig+0x10c>)
8009a8c: 4013 ands r3, r2
8009a8e: 617b str r3, [r7, #20]
/* Set the slave mode */
tmpsmcr |= sSlaveConfig->SlaveMode;
8009a90: 683b ldr r3, [r7, #0]
8009a92: 681b ldr r3, [r3, #0]
8009a94: 697a ldr r2, [r7, #20]
8009a96: 4313 orrs r3, r2
8009a98: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8009a9a: 687b ldr r3, [r7, #4]
8009a9c: 681b ldr r3, [r3, #0]
8009a9e: 697a ldr r2, [r7, #20]
8009aa0: 609a str r2, [r3, #8]
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
8009aa2: 683b ldr r3, [r7, #0]
8009aa4: 685b ldr r3, [r3, #4]
8009aa6: 2b30 cmp r3, #48 ; 0x30
8009aa8: d05c beq.n 8009b64 <TIM_SlaveTimer_SetConfig+0x100>
8009aaa: 2b30 cmp r3, #48 ; 0x30
8009aac: d806 bhi.n 8009abc <TIM_SlaveTimer_SetConfig+0x58>
8009aae: 2b10 cmp r3, #16
8009ab0: d058 beq.n 8009b64 <TIM_SlaveTimer_SetConfig+0x100>
8009ab2: 2b20 cmp r3, #32
8009ab4: d056 beq.n 8009b64 <TIM_SlaveTimer_SetConfig+0x100>
8009ab6: 2b00 cmp r3, #0
8009ab8: d054 beq.n 8009b64 <TIM_SlaveTimer_SetConfig+0x100>
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
break;
}
default:
break;
8009aba: e054 b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
8009abc: 2b50 cmp r3, #80 ; 0x50
8009abe: d03d beq.n 8009b3c <TIM_SlaveTimer_SetConfig+0xd8>
8009ac0: 2b50 cmp r3, #80 ; 0x50
8009ac2: d802 bhi.n 8009aca <TIM_SlaveTimer_SetConfig+0x66>
8009ac4: 2b40 cmp r3, #64 ; 0x40
8009ac6: d010 beq.n 8009aea <TIM_SlaveTimer_SetConfig+0x86>
break;
8009ac8: e04d b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
switch (sSlaveConfig->InputTrigger)
8009aca: 2b60 cmp r3, #96 ; 0x60
8009acc: d040 beq.n 8009b50 <TIM_SlaveTimer_SetConfig+0xec>
8009ace: 2b70 cmp r3, #112 ; 0x70
8009ad0: d000 beq.n 8009ad4 <TIM_SlaveTimer_SetConfig+0x70>
break;
8009ad2: e048 b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
TIM_ETR_SetConfig(htim->Instance,
8009ad4: 687b ldr r3, [r7, #4]
8009ad6: 6818 ldr r0, [r3, #0]
8009ad8: 683b ldr r3, [r7, #0]
8009ada: 68d9 ldr r1, [r3, #12]
8009adc: 683b ldr r3, [r7, #0]
8009ade: 689a ldr r2, [r3, #8]
8009ae0: 683b ldr r3, [r7, #0]
8009ae2: 691b ldr r3, [r3, #16]
8009ae4: f000 f8c0 bl 8009c68 <TIM_ETR_SetConfig>
break;
8009ae8: e03d b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
8009aea: 683b ldr r3, [r7, #0]
8009aec: 681b ldr r3, [r3, #0]
8009aee: 2b05 cmp r3, #5
8009af0: d101 bne.n 8009af6 <TIM_SlaveTimer_SetConfig+0x92>
return HAL_ERROR;
8009af2: 2301 movs r3, #1
8009af4: e038 b.n 8009b68 <TIM_SlaveTimer_SetConfig+0x104>
tmpccer = htim->Instance->CCER;
8009af6: 687b ldr r3, [r7, #4]
8009af8: 681b ldr r3, [r3, #0]
8009afa: 6a1b ldr r3, [r3, #32]
8009afc: 613b str r3, [r7, #16]
htim->Instance->CCER &= ~TIM_CCER_CC1E;
8009afe: 687b ldr r3, [r7, #4]
8009b00: 681b ldr r3, [r3, #0]
8009b02: 6a1a ldr r2, [r3, #32]
8009b04: 687b ldr r3, [r7, #4]
8009b06: 681b ldr r3, [r3, #0]
8009b08: f022 0201 bic.w r2, r2, #1
8009b0c: 621a str r2, [r3, #32]
tmpccmr1 = htim->Instance->CCMR1;
8009b0e: 687b ldr r3, [r7, #4]
8009b10: 681b ldr r3, [r3, #0]
8009b12: 699b ldr r3, [r3, #24]
8009b14: 60fb str r3, [r7, #12]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8009b16: 68fb ldr r3, [r7, #12]
8009b18: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8009b1c: 60fb str r3, [r7, #12]
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
8009b1e: 683b ldr r3, [r7, #0]
8009b20: 691b ldr r3, [r3, #16]
8009b22: 011b lsls r3, r3, #4
8009b24: 68fa ldr r2, [r7, #12]
8009b26: 4313 orrs r3, r2
8009b28: 60fb str r3, [r7, #12]
htim->Instance->CCMR1 = tmpccmr1;
8009b2a: 687b ldr r3, [r7, #4]
8009b2c: 681b ldr r3, [r3, #0]
8009b2e: 68fa ldr r2, [r7, #12]
8009b30: 619a str r2, [r3, #24]
htim->Instance->CCER = tmpccer;
8009b32: 687b ldr r3, [r7, #4]
8009b34: 681b ldr r3, [r3, #0]
8009b36: 693a ldr r2, [r7, #16]
8009b38: 621a str r2, [r3, #32]
break;
8009b3a: e014 b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI1_ConfigInputStage(htim->Instance,
8009b3c: 687b ldr r3, [r7, #4]
8009b3e: 6818 ldr r0, [r3, #0]
8009b40: 683b ldr r3, [r7, #0]
8009b42: 6899 ldr r1, [r3, #8]
8009b44: 683b ldr r3, [r7, #0]
8009b46: 691b ldr r3, [r3, #16]
8009b48: 461a mov r2, r3
8009b4a: f000 f813 bl 8009b74 <TIM_TI1_ConfigInputStage>
break;
8009b4e: e00a b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
TIM_TI2_ConfigInputStage(htim->Instance,
8009b50: 687b ldr r3, [r7, #4]
8009b52: 6818 ldr r0, [r3, #0]
8009b54: 683b ldr r3, [r7, #0]
8009b56: 6899 ldr r1, [r3, #8]
8009b58: 683b ldr r3, [r7, #0]
8009b5a: 691b ldr r3, [r3, #16]
8009b5c: 461a mov r2, r3
8009b5e: f000 f838 bl 8009bd2 <TIM_TI2_ConfigInputStage>
break;
8009b62: e000 b.n 8009b66 <TIM_SlaveTimer_SetConfig+0x102>
break;
8009b64: bf00 nop
}
return HAL_OK;
8009b66: 2300 movs r3, #0
}
8009b68: 4618 mov r0, r3
8009b6a: 3718 adds r7, #24
8009b6c: 46bd mov sp, r7
8009b6e: bd80 pop {r7, pc}
8009b70: fffefff8 .word 0xfffefff8
08009b74 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8009b74: b480 push {r7}
8009b76: b087 sub sp, #28
8009b78: af00 add r7, sp, #0
8009b7a: 60f8 str r0, [r7, #12]
8009b7c: 60b9 str r1, [r7, #8]
8009b7e: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8009b80: 68fb ldr r3, [r7, #12]
8009b82: 6a1b ldr r3, [r3, #32]
8009b84: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8009b86: 68fb ldr r3, [r7, #12]
8009b88: 6a1b ldr r3, [r3, #32]
8009b8a: f023 0201 bic.w r2, r3, #1
8009b8e: 68fb ldr r3, [r7, #12]
8009b90: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8009b92: 68fb ldr r3, [r7, #12]
8009b94: 699b ldr r3, [r3, #24]
8009b96: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8009b98: 693b ldr r3, [r7, #16]
8009b9a: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8009b9e: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8009ba0: 687b ldr r3, [r7, #4]
8009ba2: 011b lsls r3, r3, #4
8009ba4: 693a ldr r2, [r7, #16]
8009ba6: 4313 orrs r3, r2
8009ba8: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8009baa: 697b ldr r3, [r7, #20]
8009bac: f023 030a bic.w r3, r3, #10
8009bb0: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8009bb2: 697a ldr r2, [r7, #20]
8009bb4: 68bb ldr r3, [r7, #8]
8009bb6: 4313 orrs r3, r2
8009bb8: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8009bba: 68fb ldr r3, [r7, #12]
8009bbc: 693a ldr r2, [r7, #16]
8009bbe: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8009bc0: 68fb ldr r3, [r7, #12]
8009bc2: 697a ldr r2, [r7, #20]
8009bc4: 621a str r2, [r3, #32]
}
8009bc6: bf00 nop
8009bc8: 371c adds r7, #28
8009bca: 46bd mov sp, r7
8009bcc: f85d 7b04 ldr.w r7, [sp], #4
8009bd0: 4770 bx lr
08009bd2 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8009bd2: b480 push {r7}
8009bd4: b087 sub sp, #28
8009bd6: af00 add r7, sp, #0
8009bd8: 60f8 str r0, [r7, #12]
8009bda: 60b9 str r1, [r7, #8]
8009bdc: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8009bde: 68fb ldr r3, [r7, #12]
8009be0: 6a1b ldr r3, [r3, #32]
8009be2: f023 0210 bic.w r2, r3, #16
8009be6: 68fb ldr r3, [r7, #12]
8009be8: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8009bea: 68fb ldr r3, [r7, #12]
8009bec: 699b ldr r3, [r3, #24]
8009bee: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8009bf0: 68fb ldr r3, [r7, #12]
8009bf2: 6a1b ldr r3, [r3, #32]
8009bf4: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8009bf6: 697b ldr r3, [r7, #20]
8009bf8: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8009bfc: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8009bfe: 687b ldr r3, [r7, #4]
8009c00: 031b lsls r3, r3, #12
8009c02: 697a ldr r2, [r7, #20]
8009c04: 4313 orrs r3, r2
8009c06: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8009c08: 693b ldr r3, [r7, #16]
8009c0a: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8009c0e: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8009c10: 68bb ldr r3, [r7, #8]
8009c12: 011b lsls r3, r3, #4
8009c14: 693a ldr r2, [r7, #16]
8009c16: 4313 orrs r3, r2
8009c18: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8009c1a: 68fb ldr r3, [r7, #12]
8009c1c: 697a ldr r2, [r7, #20]
8009c1e: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8009c20: 68fb ldr r3, [r7, #12]
8009c22: 693a ldr r2, [r7, #16]
8009c24: 621a str r2, [r3, #32]
}
8009c26: bf00 nop
8009c28: 371c adds r7, #28
8009c2a: 46bd mov sp, r7
8009c2c: f85d 7b04 ldr.w r7, [sp], #4
8009c30: 4770 bx lr
08009c32 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8009c32: b480 push {r7}
8009c34: b085 sub sp, #20
8009c36: af00 add r7, sp, #0
8009c38: 6078 str r0, [r7, #4]
8009c3a: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8009c3c: 687b ldr r3, [r7, #4]
8009c3e: 689b ldr r3, [r3, #8]
8009c40: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8009c42: 68fb ldr r3, [r7, #12]
8009c44: f023 0370 bic.w r3, r3, #112 ; 0x70
8009c48: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8009c4a: 683a ldr r2, [r7, #0]
8009c4c: 68fb ldr r3, [r7, #12]
8009c4e: 4313 orrs r3, r2
8009c50: f043 0307 orr.w r3, r3, #7
8009c54: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8009c56: 687b ldr r3, [r7, #4]
8009c58: 68fa ldr r2, [r7, #12]
8009c5a: 609a str r2, [r3, #8]
}
8009c5c: bf00 nop
8009c5e: 3714 adds r7, #20
8009c60: 46bd mov sp, r7
8009c62: f85d 7b04 ldr.w r7, [sp], #4
8009c66: 4770 bx lr
08009c68 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8009c68: b480 push {r7}
8009c6a: b087 sub sp, #28
8009c6c: af00 add r7, sp, #0
8009c6e: 60f8 str r0, [r7, #12]
8009c70: 60b9 str r1, [r7, #8]
8009c72: 607a str r2, [r7, #4]
8009c74: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8009c76: 68fb ldr r3, [r7, #12]
8009c78: 689b ldr r3, [r3, #8]
8009c7a: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8009c7c: 697b ldr r3, [r7, #20]
8009c7e: f423 437f bic.w r3, r3, #65280 ; 0xff00
8009c82: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8009c84: 683b ldr r3, [r7, #0]
8009c86: 021a lsls r2, r3, #8
8009c88: 687b ldr r3, [r7, #4]
8009c8a: 431a orrs r2, r3
8009c8c: 68bb ldr r3, [r7, #8]
8009c8e: 4313 orrs r3, r2
8009c90: 697a ldr r2, [r7, #20]
8009c92: 4313 orrs r3, r2
8009c94: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8009c96: 68fb ldr r3, [r7, #12]
8009c98: 697a ldr r2, [r7, #20]
8009c9a: 609a str r2, [r3, #8]
}
8009c9c: bf00 nop
8009c9e: 371c adds r7, #28
8009ca0: 46bd mov sp, r7
8009ca2: f85d 7b04 ldr.w r7, [sp], #4
8009ca6: 4770 bx lr
08009ca8 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8009ca8: b480 push {r7}
8009caa: b085 sub sp, #20
8009cac: af00 add r7, sp, #0
8009cae: 6078 str r0, [r7, #4]
8009cb0: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8009cb2: 687b ldr r3, [r7, #4]
8009cb4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009cb8: 2b01 cmp r3, #1
8009cba: d101 bne.n 8009cc0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8009cbc: 2302 movs r3, #2
8009cbe: e06d b.n 8009d9c <HAL_TIMEx_MasterConfigSynchronization+0xf4>
8009cc0: 687b ldr r3, [r7, #4]
8009cc2: 2201 movs r2, #1
8009cc4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8009cc8: 687b ldr r3, [r7, #4]
8009cca: 2202 movs r2, #2
8009ccc: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8009cd0: 687b ldr r3, [r7, #4]
8009cd2: 681b ldr r3, [r3, #0]
8009cd4: 685b ldr r3, [r3, #4]
8009cd6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8009cd8: 687b ldr r3, [r7, #4]
8009cda: 681b ldr r3, [r3, #0]
8009cdc: 689b ldr r3, [r3, #8]
8009cde: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8009ce0: 687b ldr r3, [r7, #4]
8009ce2: 681b ldr r3, [r3, #0]
8009ce4: 4a30 ldr r2, [pc, #192] ; (8009da8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8009ce6: 4293 cmp r3, r2
8009ce8: d004 beq.n 8009cf4 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
8009cea: 687b ldr r3, [r7, #4]
8009cec: 681b ldr r3, [r3, #0]
8009cee: 4a2f ldr r2, [pc, #188] ; (8009dac <HAL_TIMEx_MasterConfigSynchronization+0x104>)
8009cf0: 4293 cmp r3, r2
8009cf2: d108 bne.n 8009d06 <HAL_TIMEx_MasterConfigSynchronization+0x5e>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8009cf4: 68fb ldr r3, [r7, #12]
8009cf6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
8009cfa: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8009cfc: 683b ldr r3, [r7, #0]
8009cfe: 685b ldr r3, [r3, #4]
8009d00: 68fa ldr r2, [r7, #12]
8009d02: 4313 orrs r3, r2
8009d04: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8009d06: 68fb ldr r3, [r7, #12]
8009d08: f023 0370 bic.w r3, r3, #112 ; 0x70
8009d0c: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8009d0e: 683b ldr r3, [r7, #0]
8009d10: 681b ldr r3, [r3, #0]
8009d12: 68fa ldr r2, [r7, #12]
8009d14: 4313 orrs r3, r2
8009d16: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8009d18: 687b ldr r3, [r7, #4]
8009d1a: 681b ldr r3, [r3, #0]
8009d1c: 68fa ldr r2, [r7, #12]
8009d1e: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8009d20: 687b ldr r3, [r7, #4]
8009d22: 681b ldr r3, [r3, #0]
8009d24: 4a20 ldr r2, [pc, #128] ; (8009da8 <HAL_TIMEx_MasterConfigSynchronization+0x100>)
8009d26: 4293 cmp r3, r2
8009d28: d022 beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d2a: 687b ldr r3, [r7, #4]
8009d2c: 681b ldr r3, [r3, #0]
8009d2e: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8009d32: d01d beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d34: 687b ldr r3, [r7, #4]
8009d36: 681b ldr r3, [r3, #0]
8009d38: 4a1d ldr r2, [pc, #116] ; (8009db0 <HAL_TIMEx_MasterConfigSynchronization+0x108>)
8009d3a: 4293 cmp r3, r2
8009d3c: d018 beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d3e: 687b ldr r3, [r7, #4]
8009d40: 681b ldr r3, [r3, #0]
8009d42: 4a1c ldr r2, [pc, #112] ; (8009db4 <HAL_TIMEx_MasterConfigSynchronization+0x10c>)
8009d44: 4293 cmp r3, r2
8009d46: d013 beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d48: 687b ldr r3, [r7, #4]
8009d4a: 681b ldr r3, [r3, #0]
8009d4c: 4a1a ldr r2, [pc, #104] ; (8009db8 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
8009d4e: 4293 cmp r3, r2
8009d50: d00e beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d52: 687b ldr r3, [r7, #4]
8009d54: 681b ldr r3, [r3, #0]
8009d56: 4a15 ldr r2, [pc, #84] ; (8009dac <HAL_TIMEx_MasterConfigSynchronization+0x104>)
8009d58: 4293 cmp r3, r2
8009d5a: d009 beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d5c: 687b ldr r3, [r7, #4]
8009d5e: 681b ldr r3, [r3, #0]
8009d60: 4a16 ldr r2, [pc, #88] ; (8009dbc <HAL_TIMEx_MasterConfigSynchronization+0x114>)
8009d62: 4293 cmp r3, r2
8009d64: d004 beq.n 8009d70 <HAL_TIMEx_MasterConfigSynchronization+0xc8>
8009d66: 687b ldr r3, [r7, #4]
8009d68: 681b ldr r3, [r3, #0]
8009d6a: 4a15 ldr r2, [pc, #84] ; (8009dc0 <HAL_TIMEx_MasterConfigSynchronization+0x118>)
8009d6c: 4293 cmp r3, r2
8009d6e: d10c bne.n 8009d8a <HAL_TIMEx_MasterConfigSynchronization+0xe2>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8009d70: 68bb ldr r3, [r7, #8]
8009d72: f023 0380 bic.w r3, r3, #128 ; 0x80
8009d76: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8009d78: 683b ldr r3, [r7, #0]
8009d7a: 689b ldr r3, [r3, #8]
8009d7c: 68ba ldr r2, [r7, #8]
8009d7e: 4313 orrs r3, r2
8009d80: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8009d82: 687b ldr r3, [r7, #4]
8009d84: 681b ldr r3, [r3, #0]
8009d86: 68ba ldr r2, [r7, #8]
8009d88: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8009d8a: 687b ldr r3, [r7, #4]
8009d8c: 2201 movs r2, #1
8009d8e: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8009d92: 687b ldr r3, [r7, #4]
8009d94: 2200 movs r2, #0
8009d96: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8009d9a: 2300 movs r3, #0
}
8009d9c: 4618 mov r0, r3
8009d9e: 3714 adds r7, #20
8009da0: 46bd mov sp, r7
8009da2: f85d 7b04 ldr.w r7, [sp], #4
8009da6: 4770 bx lr
8009da8: 40010000 .word 0x40010000
8009dac: 40010400 .word 0x40010400
8009db0: 40000400 .word 0x40000400
8009db4: 40000800 .word 0x40000800
8009db8: 40000c00 .word 0x40000c00
8009dbc: 40014000 .word 0x40014000
8009dc0: 40001800 .word 0x40001800
08009dc4 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8009dc4: b480 push {r7}
8009dc6: b085 sub sp, #20
8009dc8: af00 add r7, sp, #0
8009dca: 6078 str r0, [r7, #4]
8009dcc: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
8009dce: 2300 movs r3, #0
8009dd0: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8009dd2: 687b ldr r3, [r7, #4]
8009dd4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8009dd8: 2b01 cmp r3, #1
8009dda: d101 bne.n 8009de0 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
8009ddc: 2302 movs r3, #2
8009dde: e065 b.n 8009eac <HAL_TIMEx_ConfigBreakDeadTime+0xe8>
8009de0: 687b ldr r3, [r7, #4]
8009de2: 2201 movs r2, #1
8009de4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8009de8: 68fb ldr r3, [r7, #12]
8009dea: f023 02ff bic.w r2, r3, #255 ; 0xff
8009dee: 683b ldr r3, [r7, #0]
8009df0: 68db ldr r3, [r3, #12]
8009df2: 4313 orrs r3, r2
8009df4: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8009df6: 68fb ldr r3, [r7, #12]
8009df8: f423 7240 bic.w r2, r3, #768 ; 0x300
8009dfc: 683b ldr r3, [r7, #0]
8009dfe: 689b ldr r3, [r3, #8]
8009e00: 4313 orrs r3, r2
8009e02: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
8009e04: 68fb ldr r3, [r7, #12]
8009e06: f423 6280 bic.w r2, r3, #1024 ; 0x400
8009e0a: 683b ldr r3, [r7, #0]
8009e0c: 685b ldr r3, [r3, #4]
8009e0e: 4313 orrs r3, r2
8009e10: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
8009e12: 68fb ldr r3, [r7, #12]
8009e14: f423 6200 bic.w r2, r3, #2048 ; 0x800
8009e18: 683b ldr r3, [r7, #0]
8009e1a: 681b ldr r3, [r3, #0]
8009e1c: 4313 orrs r3, r2
8009e1e: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
8009e20: 68fb ldr r3, [r7, #12]
8009e22: f423 5280 bic.w r2, r3, #4096 ; 0x1000
8009e26: 683b ldr r3, [r7, #0]
8009e28: 691b ldr r3, [r3, #16]
8009e2a: 4313 orrs r3, r2
8009e2c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
8009e2e: 68fb ldr r3, [r7, #12]
8009e30: f423 5200 bic.w r2, r3, #8192 ; 0x2000
8009e34: 683b ldr r3, [r7, #0]
8009e36: 695b ldr r3, [r3, #20]
8009e38: 4313 orrs r3, r2
8009e3a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8009e3c: 68fb ldr r3, [r7, #12]
8009e3e: f423 4280 bic.w r2, r3, #16384 ; 0x4000
8009e42: 683b ldr r3, [r7, #0]
8009e44: 6a9b ldr r3, [r3, #40] ; 0x28
8009e46: 4313 orrs r3, r2
8009e48: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
8009e4a: 68fb ldr r3, [r7, #12]
8009e4c: f423 2270 bic.w r2, r3, #983040 ; 0xf0000
8009e50: 683b ldr r3, [r7, #0]
8009e52: 699b ldr r3, [r3, #24]
8009e54: 041b lsls r3, r3, #16
8009e56: 4313 orrs r3, r2
8009e58: 60fb str r3, [r7, #12]
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
8009e5a: 687b ldr r3, [r7, #4]
8009e5c: 681b ldr r3, [r3, #0]
8009e5e: 4a16 ldr r2, [pc, #88] ; (8009eb8 <HAL_TIMEx_ConfigBreakDeadTime+0xf4>)
8009e60: 4293 cmp r3, r2
8009e62: d004 beq.n 8009e6e <HAL_TIMEx_ConfigBreakDeadTime+0xaa>
8009e64: 687b ldr r3, [r7, #4]
8009e66: 681b ldr r3, [r3, #0]
8009e68: 4a14 ldr r2, [pc, #80] ; (8009ebc <HAL_TIMEx_ConfigBreakDeadTime+0xf8>)
8009e6a: 4293 cmp r3, r2
8009e6c: d115 bne.n 8009e9a <HAL_TIMEx_ConfigBreakDeadTime+0xd6>
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8009e6e: 68fb ldr r3, [r7, #12]
8009e70: f423 0270 bic.w r2, r3, #15728640 ; 0xf00000
8009e74: 683b ldr r3, [r7, #0]
8009e76: 6a5b ldr r3, [r3, #36] ; 0x24
8009e78: 051b lsls r3, r3, #20
8009e7a: 4313 orrs r3, r2
8009e7c: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
8009e7e: 68fb ldr r3, [r7, #12]
8009e80: f023 7280 bic.w r2, r3, #16777216 ; 0x1000000
8009e84: 683b ldr r3, [r7, #0]
8009e86: 69db ldr r3, [r3, #28]
8009e88: 4313 orrs r3, r2
8009e8a: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
8009e8c: 68fb ldr r3, [r7, #12]
8009e8e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000
8009e92: 683b ldr r3, [r7, #0]
8009e94: 6a1b ldr r3, [r3, #32]
8009e96: 4313 orrs r3, r2
8009e98: 60fb str r3, [r7, #12]
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8009e9a: 687b ldr r3, [r7, #4]
8009e9c: 681b ldr r3, [r3, #0]
8009e9e: 68fa ldr r2, [r7, #12]
8009ea0: 645a str r2, [r3, #68] ; 0x44
__HAL_UNLOCK(htim);
8009ea2: 687b ldr r3, [r7, #4]
8009ea4: 2200 movs r2, #0
8009ea6: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8009eaa: 2300 movs r3, #0
}
8009eac: 4618 mov r0, r3
8009eae: 3714 adds r7, #20
8009eb0: 46bd mov sp, r7
8009eb2: f85d 7b04 ldr.w r7, [sp], #4
8009eb6: 4770 bx lr
8009eb8: 40010000 .word 0x40010000
8009ebc: 40010400 .word 0x40010400
08009ec0 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8009ec0: b480 push {r7}
8009ec2: b083 sub sp, #12
8009ec4: af00 add r7, sp, #0
8009ec6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8009ec8: bf00 nop
8009eca: 370c adds r7, #12
8009ecc: 46bd mov sp, r7
8009ece: f85d 7b04 ldr.w r7, [sp], #4
8009ed2: 4770 bx lr
08009ed4 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8009ed4: b480 push {r7}
8009ed6: b083 sub sp, #12
8009ed8: af00 add r7, sp, #0
8009eda: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8009edc: bf00 nop
8009ede: 370c adds r7, #12
8009ee0: 46bd mov sp, r7
8009ee2: f85d 7b04 ldr.w r7, [sp], #4
8009ee6: 4770 bx lr
08009ee8 <HAL_TIMEx_Break2Callback>:
* @brief Hall Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
8009ee8: b480 push {r7}
8009eea: b083 sub sp, #12
8009eec: af00 add r7, sp, #0
8009eee: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8009ef0: bf00 nop
8009ef2: 370c adds r7, #12
8009ef4: 46bd mov sp, r7
8009ef6: f85d 7b04 ldr.w r7, [sp], #4
8009efa: 4770 bx lr
08009efc <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8009efc: b580 push {r7, lr}
8009efe: b082 sub sp, #8
8009f00: af00 add r7, sp, #0
8009f02: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8009f04: 687b ldr r3, [r7, #4]
8009f06: 2b00 cmp r3, #0
8009f08: d101 bne.n 8009f0e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8009f0a: 2301 movs r3, #1
8009f0c: e040 b.n 8009f90 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
8009f0e: 687b ldr r3, [r7, #4]
8009f10: 6f5b ldr r3, [r3, #116] ; 0x74
8009f12: 2b00 cmp r3, #0
8009f14: d106 bne.n 8009f24 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8009f16: 687b ldr r3, [r7, #4]
8009f18: 2200 movs r2, #0
8009f1a: f883 2070 strb.w r2, [r3, #112] ; 0x70
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8009f1e: 6878 ldr r0, [r7, #4]
8009f20: f7fa f86a bl 8003ff8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8009f24: 687b ldr r3, [r7, #4]
8009f26: 2224 movs r2, #36 ; 0x24
8009f28: 675a str r2, [r3, #116] ; 0x74
__HAL_UART_DISABLE(huart);
8009f2a: 687b ldr r3, [r7, #4]
8009f2c: 681b ldr r3, [r3, #0]
8009f2e: 681a ldr r2, [r3, #0]
8009f30: 687b ldr r3, [r7, #4]
8009f32: 681b ldr r3, [r3, #0]
8009f34: f022 0201 bic.w r2, r2, #1
8009f38: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
8009f3a: 6878 ldr r0, [r7, #4]
8009f3c: f000 f82c bl 8009f98 <UART_SetConfig>
8009f40: 4603 mov r3, r0
8009f42: 2b01 cmp r3, #1
8009f44: d101 bne.n 8009f4a <HAL_UART_Init+0x4e>
{
return HAL_ERROR;
8009f46: 2301 movs r3, #1
8009f48: e022 b.n 8009f90 <HAL_UART_Init+0x94>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8009f4a: 687b ldr r3, [r7, #4]
8009f4c: 6a5b ldr r3, [r3, #36] ; 0x24
8009f4e: 2b00 cmp r3, #0
8009f50: d002 beq.n 8009f58 <HAL_UART_Init+0x5c>
{
UART_AdvFeatureConfig(huart);
8009f52: 6878 ldr r0, [r7, #4]
8009f54: f000 faca bl 800a4ec <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8009f58: 687b ldr r3, [r7, #4]
8009f5a: 681b ldr r3, [r3, #0]
8009f5c: 685a ldr r2, [r3, #4]
8009f5e: 687b ldr r3, [r7, #4]
8009f60: 681b ldr r3, [r3, #0]
8009f62: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8009f66: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8009f68: 687b ldr r3, [r7, #4]
8009f6a: 681b ldr r3, [r3, #0]
8009f6c: 689a ldr r2, [r3, #8]
8009f6e: 687b ldr r3, [r7, #4]
8009f70: 681b ldr r3, [r3, #0]
8009f72: f022 022a bic.w r2, r2, #42 ; 0x2a
8009f76: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8009f78: 687b ldr r3, [r7, #4]
8009f7a: 681b ldr r3, [r3, #0]
8009f7c: 681a ldr r2, [r3, #0]
8009f7e: 687b ldr r3, [r7, #4]
8009f80: 681b ldr r3, [r3, #0]
8009f82: f042 0201 orr.w r2, r2, #1
8009f86: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
8009f88: 6878 ldr r0, [r7, #4]
8009f8a: f000 fb51 bl 800a630 <UART_CheckIdleState>
8009f8e: 4603 mov r3, r0
}
8009f90: 4618 mov r0, r3
8009f92: 3708 adds r7, #8
8009f94: 46bd mov sp, r7
8009f96: bd80 pop {r7, pc}
08009f98 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8009f98: b580 push {r7, lr}
8009f9a: b088 sub sp, #32
8009f9c: af00 add r7, sp, #0
8009f9e: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv = 0x00000000U;
8009fa0: 2300 movs r3, #0
8009fa2: 61bb str r3, [r7, #24]
HAL_StatusTypeDef ret = HAL_OK;
8009fa4: 2300 movs r3, #0
8009fa6: 75fb strb r3, [r7, #23]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8009fa8: 687b ldr r3, [r7, #4]
8009faa: 689a ldr r2, [r3, #8]
8009fac: 687b ldr r3, [r7, #4]
8009fae: 691b ldr r3, [r3, #16]
8009fb0: 431a orrs r2, r3
8009fb2: 687b ldr r3, [r7, #4]
8009fb4: 695b ldr r3, [r3, #20]
8009fb6: 431a orrs r2, r3
8009fb8: 687b ldr r3, [r7, #4]
8009fba: 69db ldr r3, [r3, #28]
8009fbc: 4313 orrs r3, r2
8009fbe: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8009fc0: 687b ldr r3, [r7, #4]
8009fc2: 681b ldr r3, [r3, #0]
8009fc4: 681a ldr r2, [r3, #0]
8009fc6: 4bb1 ldr r3, [pc, #708] ; (800a28c <UART_SetConfig+0x2f4>)
8009fc8: 4013 ands r3, r2
8009fca: 687a ldr r2, [r7, #4]
8009fcc: 6812 ldr r2, [r2, #0]
8009fce: 6939 ldr r1, [r7, #16]
8009fd0: 430b orrs r3, r1
8009fd2: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8009fd4: 687b ldr r3, [r7, #4]
8009fd6: 681b ldr r3, [r3, #0]
8009fd8: 685b ldr r3, [r3, #4]
8009fda: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8009fde: 687b ldr r3, [r7, #4]
8009fe0: 68da ldr r2, [r3, #12]
8009fe2: 687b ldr r3, [r7, #4]
8009fe4: 681b ldr r3, [r3, #0]
8009fe6: 430a orrs r2, r1
8009fe8: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8009fea: 687b ldr r3, [r7, #4]
8009fec: 699b ldr r3, [r3, #24]
8009fee: 613b str r3, [r7, #16]
tmpreg |= huart->Init.OneBitSampling;
8009ff0: 687b ldr r3, [r7, #4]
8009ff2: 6a1b ldr r3, [r3, #32]
8009ff4: 693a ldr r2, [r7, #16]
8009ff6: 4313 orrs r3, r2
8009ff8: 613b str r3, [r7, #16]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8009ffa: 687b ldr r3, [r7, #4]
8009ffc: 681b ldr r3, [r3, #0]
8009ffe: 689b ldr r3, [r3, #8]
800a000: f423 6130 bic.w r1, r3, #2816 ; 0xb00
800a004: 687b ldr r3, [r7, #4]
800a006: 681b ldr r3, [r3, #0]
800a008: 693a ldr r2, [r7, #16]
800a00a: 430a orrs r2, r1
800a00c: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
800a00e: 687b ldr r3, [r7, #4]
800a010: 681b ldr r3, [r3, #0]
800a012: 4a9f ldr r2, [pc, #636] ; (800a290 <UART_SetConfig+0x2f8>)
800a014: 4293 cmp r3, r2
800a016: d121 bne.n 800a05c <UART_SetConfig+0xc4>
800a018: 4b9e ldr r3, [pc, #632] ; (800a294 <UART_SetConfig+0x2fc>)
800a01a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a01e: f003 0303 and.w r3, r3, #3
800a022: 2b03 cmp r3, #3
800a024: d816 bhi.n 800a054 <UART_SetConfig+0xbc>
800a026: a201 add r2, pc, #4 ; (adr r2, 800a02c <UART_SetConfig+0x94>)
800a028: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a02c: 0800a03d .word 0x0800a03d
800a030: 0800a049 .word 0x0800a049
800a034: 0800a043 .word 0x0800a043
800a038: 0800a04f .word 0x0800a04f
800a03c: 2301 movs r3, #1
800a03e: 77fb strb r3, [r7, #31]
800a040: e151 b.n 800a2e6 <UART_SetConfig+0x34e>
800a042: 2302 movs r3, #2
800a044: 77fb strb r3, [r7, #31]
800a046: e14e b.n 800a2e6 <UART_SetConfig+0x34e>
800a048: 2304 movs r3, #4
800a04a: 77fb strb r3, [r7, #31]
800a04c: e14b b.n 800a2e6 <UART_SetConfig+0x34e>
800a04e: 2308 movs r3, #8
800a050: 77fb strb r3, [r7, #31]
800a052: e148 b.n 800a2e6 <UART_SetConfig+0x34e>
800a054: 2310 movs r3, #16
800a056: 77fb strb r3, [r7, #31]
800a058: bf00 nop
800a05a: e144 b.n 800a2e6 <UART_SetConfig+0x34e>
800a05c: 687b ldr r3, [r7, #4]
800a05e: 681b ldr r3, [r3, #0]
800a060: 4a8d ldr r2, [pc, #564] ; (800a298 <UART_SetConfig+0x300>)
800a062: 4293 cmp r3, r2
800a064: d134 bne.n 800a0d0 <UART_SetConfig+0x138>
800a066: 4b8b ldr r3, [pc, #556] ; (800a294 <UART_SetConfig+0x2fc>)
800a068: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a06c: f003 030c and.w r3, r3, #12
800a070: 2b0c cmp r3, #12
800a072: d829 bhi.n 800a0c8 <UART_SetConfig+0x130>
800a074: a201 add r2, pc, #4 ; (adr r2, 800a07c <UART_SetConfig+0xe4>)
800a076: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a07a: bf00 nop
800a07c: 0800a0b1 .word 0x0800a0b1
800a080: 0800a0c9 .word 0x0800a0c9
800a084: 0800a0c9 .word 0x0800a0c9
800a088: 0800a0c9 .word 0x0800a0c9
800a08c: 0800a0bd .word 0x0800a0bd
800a090: 0800a0c9 .word 0x0800a0c9
800a094: 0800a0c9 .word 0x0800a0c9
800a098: 0800a0c9 .word 0x0800a0c9
800a09c: 0800a0b7 .word 0x0800a0b7
800a0a0: 0800a0c9 .word 0x0800a0c9
800a0a4: 0800a0c9 .word 0x0800a0c9
800a0a8: 0800a0c9 .word 0x0800a0c9
800a0ac: 0800a0c3 .word 0x0800a0c3
800a0b0: 2300 movs r3, #0
800a0b2: 77fb strb r3, [r7, #31]
800a0b4: e117 b.n 800a2e6 <UART_SetConfig+0x34e>
800a0b6: 2302 movs r3, #2
800a0b8: 77fb strb r3, [r7, #31]
800a0ba: e114 b.n 800a2e6 <UART_SetConfig+0x34e>
800a0bc: 2304 movs r3, #4
800a0be: 77fb strb r3, [r7, #31]
800a0c0: e111 b.n 800a2e6 <UART_SetConfig+0x34e>
800a0c2: 2308 movs r3, #8
800a0c4: 77fb strb r3, [r7, #31]
800a0c6: e10e b.n 800a2e6 <UART_SetConfig+0x34e>
800a0c8: 2310 movs r3, #16
800a0ca: 77fb strb r3, [r7, #31]
800a0cc: bf00 nop
800a0ce: e10a b.n 800a2e6 <UART_SetConfig+0x34e>
800a0d0: 687b ldr r3, [r7, #4]
800a0d2: 681b ldr r3, [r3, #0]
800a0d4: 4a71 ldr r2, [pc, #452] ; (800a29c <UART_SetConfig+0x304>)
800a0d6: 4293 cmp r3, r2
800a0d8: d120 bne.n 800a11c <UART_SetConfig+0x184>
800a0da: 4b6e ldr r3, [pc, #440] ; (800a294 <UART_SetConfig+0x2fc>)
800a0dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a0e0: f003 0330 and.w r3, r3, #48 ; 0x30
800a0e4: 2b10 cmp r3, #16
800a0e6: d00f beq.n 800a108 <UART_SetConfig+0x170>
800a0e8: 2b10 cmp r3, #16
800a0ea: d802 bhi.n 800a0f2 <UART_SetConfig+0x15a>
800a0ec: 2b00 cmp r3, #0
800a0ee: d005 beq.n 800a0fc <UART_SetConfig+0x164>
800a0f0: e010 b.n 800a114 <UART_SetConfig+0x17c>
800a0f2: 2b20 cmp r3, #32
800a0f4: d005 beq.n 800a102 <UART_SetConfig+0x16a>
800a0f6: 2b30 cmp r3, #48 ; 0x30
800a0f8: d009 beq.n 800a10e <UART_SetConfig+0x176>
800a0fa: e00b b.n 800a114 <UART_SetConfig+0x17c>
800a0fc: 2300 movs r3, #0
800a0fe: 77fb strb r3, [r7, #31]
800a100: e0f1 b.n 800a2e6 <UART_SetConfig+0x34e>
800a102: 2302 movs r3, #2
800a104: 77fb strb r3, [r7, #31]
800a106: e0ee b.n 800a2e6 <UART_SetConfig+0x34e>
800a108: 2304 movs r3, #4
800a10a: 77fb strb r3, [r7, #31]
800a10c: e0eb b.n 800a2e6 <UART_SetConfig+0x34e>
800a10e: 2308 movs r3, #8
800a110: 77fb strb r3, [r7, #31]
800a112: e0e8 b.n 800a2e6 <UART_SetConfig+0x34e>
800a114: 2310 movs r3, #16
800a116: 77fb strb r3, [r7, #31]
800a118: bf00 nop
800a11a: e0e4 b.n 800a2e6 <UART_SetConfig+0x34e>
800a11c: 687b ldr r3, [r7, #4]
800a11e: 681b ldr r3, [r3, #0]
800a120: 4a5f ldr r2, [pc, #380] ; (800a2a0 <UART_SetConfig+0x308>)
800a122: 4293 cmp r3, r2
800a124: d120 bne.n 800a168 <UART_SetConfig+0x1d0>
800a126: 4b5b ldr r3, [pc, #364] ; (800a294 <UART_SetConfig+0x2fc>)
800a128: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a12c: f003 03c0 and.w r3, r3, #192 ; 0xc0
800a130: 2b40 cmp r3, #64 ; 0x40
800a132: d00f beq.n 800a154 <UART_SetConfig+0x1bc>
800a134: 2b40 cmp r3, #64 ; 0x40
800a136: d802 bhi.n 800a13e <UART_SetConfig+0x1a6>
800a138: 2b00 cmp r3, #0
800a13a: d005 beq.n 800a148 <UART_SetConfig+0x1b0>
800a13c: e010 b.n 800a160 <UART_SetConfig+0x1c8>
800a13e: 2b80 cmp r3, #128 ; 0x80
800a140: d005 beq.n 800a14e <UART_SetConfig+0x1b6>
800a142: 2bc0 cmp r3, #192 ; 0xc0
800a144: d009 beq.n 800a15a <UART_SetConfig+0x1c2>
800a146: e00b b.n 800a160 <UART_SetConfig+0x1c8>
800a148: 2300 movs r3, #0
800a14a: 77fb strb r3, [r7, #31]
800a14c: e0cb b.n 800a2e6 <UART_SetConfig+0x34e>
800a14e: 2302 movs r3, #2
800a150: 77fb strb r3, [r7, #31]
800a152: e0c8 b.n 800a2e6 <UART_SetConfig+0x34e>
800a154: 2304 movs r3, #4
800a156: 77fb strb r3, [r7, #31]
800a158: e0c5 b.n 800a2e6 <UART_SetConfig+0x34e>
800a15a: 2308 movs r3, #8
800a15c: 77fb strb r3, [r7, #31]
800a15e: e0c2 b.n 800a2e6 <UART_SetConfig+0x34e>
800a160: 2310 movs r3, #16
800a162: 77fb strb r3, [r7, #31]
800a164: bf00 nop
800a166: e0be b.n 800a2e6 <UART_SetConfig+0x34e>
800a168: 687b ldr r3, [r7, #4]
800a16a: 681b ldr r3, [r3, #0]
800a16c: 4a4d ldr r2, [pc, #308] ; (800a2a4 <UART_SetConfig+0x30c>)
800a16e: 4293 cmp r3, r2
800a170: d124 bne.n 800a1bc <UART_SetConfig+0x224>
800a172: 4b48 ldr r3, [pc, #288] ; (800a294 <UART_SetConfig+0x2fc>)
800a174: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a178: f403 7340 and.w r3, r3, #768 ; 0x300
800a17c: f5b3 7f80 cmp.w r3, #256 ; 0x100
800a180: d012 beq.n 800a1a8 <UART_SetConfig+0x210>
800a182: f5b3 7f80 cmp.w r3, #256 ; 0x100
800a186: d802 bhi.n 800a18e <UART_SetConfig+0x1f6>
800a188: 2b00 cmp r3, #0
800a18a: d007 beq.n 800a19c <UART_SetConfig+0x204>
800a18c: e012 b.n 800a1b4 <UART_SetConfig+0x21c>
800a18e: f5b3 7f00 cmp.w r3, #512 ; 0x200
800a192: d006 beq.n 800a1a2 <UART_SetConfig+0x20a>
800a194: f5b3 7f40 cmp.w r3, #768 ; 0x300
800a198: d009 beq.n 800a1ae <UART_SetConfig+0x216>
800a19a: e00b b.n 800a1b4 <UART_SetConfig+0x21c>
800a19c: 2300 movs r3, #0
800a19e: 77fb strb r3, [r7, #31]
800a1a0: e0a1 b.n 800a2e6 <UART_SetConfig+0x34e>
800a1a2: 2302 movs r3, #2
800a1a4: 77fb strb r3, [r7, #31]
800a1a6: e09e b.n 800a2e6 <UART_SetConfig+0x34e>
800a1a8: 2304 movs r3, #4
800a1aa: 77fb strb r3, [r7, #31]
800a1ac: e09b b.n 800a2e6 <UART_SetConfig+0x34e>
800a1ae: 2308 movs r3, #8
800a1b0: 77fb strb r3, [r7, #31]
800a1b2: e098 b.n 800a2e6 <UART_SetConfig+0x34e>
800a1b4: 2310 movs r3, #16
800a1b6: 77fb strb r3, [r7, #31]
800a1b8: bf00 nop
800a1ba: e094 b.n 800a2e6 <UART_SetConfig+0x34e>
800a1bc: 687b ldr r3, [r7, #4]
800a1be: 681b ldr r3, [r3, #0]
800a1c0: 4a39 ldr r2, [pc, #228] ; (800a2a8 <UART_SetConfig+0x310>)
800a1c2: 4293 cmp r3, r2
800a1c4: d124 bne.n 800a210 <UART_SetConfig+0x278>
800a1c6: 4b33 ldr r3, [pc, #204] ; (800a294 <UART_SetConfig+0x2fc>)
800a1c8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a1cc: f403 6340 and.w r3, r3, #3072 ; 0xc00
800a1d0: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800a1d4: d012 beq.n 800a1fc <UART_SetConfig+0x264>
800a1d6: f5b3 6f80 cmp.w r3, #1024 ; 0x400
800a1da: d802 bhi.n 800a1e2 <UART_SetConfig+0x24a>
800a1dc: 2b00 cmp r3, #0
800a1de: d007 beq.n 800a1f0 <UART_SetConfig+0x258>
800a1e0: e012 b.n 800a208 <UART_SetConfig+0x270>
800a1e2: f5b3 6f00 cmp.w r3, #2048 ; 0x800
800a1e6: d006 beq.n 800a1f6 <UART_SetConfig+0x25e>
800a1e8: f5b3 6f40 cmp.w r3, #3072 ; 0xc00
800a1ec: d009 beq.n 800a202 <UART_SetConfig+0x26a>
800a1ee: e00b b.n 800a208 <UART_SetConfig+0x270>
800a1f0: 2301 movs r3, #1
800a1f2: 77fb strb r3, [r7, #31]
800a1f4: e077 b.n 800a2e6 <UART_SetConfig+0x34e>
800a1f6: 2302 movs r3, #2
800a1f8: 77fb strb r3, [r7, #31]
800a1fa: e074 b.n 800a2e6 <UART_SetConfig+0x34e>
800a1fc: 2304 movs r3, #4
800a1fe: 77fb strb r3, [r7, #31]
800a200: e071 b.n 800a2e6 <UART_SetConfig+0x34e>
800a202: 2308 movs r3, #8
800a204: 77fb strb r3, [r7, #31]
800a206: e06e b.n 800a2e6 <UART_SetConfig+0x34e>
800a208: 2310 movs r3, #16
800a20a: 77fb strb r3, [r7, #31]
800a20c: bf00 nop
800a20e: e06a b.n 800a2e6 <UART_SetConfig+0x34e>
800a210: 687b ldr r3, [r7, #4]
800a212: 681b ldr r3, [r3, #0]
800a214: 4a25 ldr r2, [pc, #148] ; (800a2ac <UART_SetConfig+0x314>)
800a216: 4293 cmp r3, r2
800a218: d124 bne.n 800a264 <UART_SetConfig+0x2cc>
800a21a: 4b1e ldr r3, [pc, #120] ; (800a294 <UART_SetConfig+0x2fc>)
800a21c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a220: f403 5340 and.w r3, r3, #12288 ; 0x3000
800a224: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a228: d012 beq.n 800a250 <UART_SetConfig+0x2b8>
800a22a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800a22e: d802 bhi.n 800a236 <UART_SetConfig+0x29e>
800a230: 2b00 cmp r3, #0
800a232: d007 beq.n 800a244 <UART_SetConfig+0x2ac>
800a234: e012 b.n 800a25c <UART_SetConfig+0x2c4>
800a236: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
800a23a: d006 beq.n 800a24a <UART_SetConfig+0x2b2>
800a23c: f5b3 5f40 cmp.w r3, #12288 ; 0x3000
800a240: d009 beq.n 800a256 <UART_SetConfig+0x2be>
800a242: e00b b.n 800a25c <UART_SetConfig+0x2c4>
800a244: 2300 movs r3, #0
800a246: 77fb strb r3, [r7, #31]
800a248: e04d b.n 800a2e6 <UART_SetConfig+0x34e>
800a24a: 2302 movs r3, #2
800a24c: 77fb strb r3, [r7, #31]
800a24e: e04a b.n 800a2e6 <UART_SetConfig+0x34e>
800a250: 2304 movs r3, #4
800a252: 77fb strb r3, [r7, #31]
800a254: e047 b.n 800a2e6 <UART_SetConfig+0x34e>
800a256: 2308 movs r3, #8
800a258: 77fb strb r3, [r7, #31]
800a25a: e044 b.n 800a2e6 <UART_SetConfig+0x34e>
800a25c: 2310 movs r3, #16
800a25e: 77fb strb r3, [r7, #31]
800a260: bf00 nop
800a262: e040 b.n 800a2e6 <UART_SetConfig+0x34e>
800a264: 687b ldr r3, [r7, #4]
800a266: 681b ldr r3, [r3, #0]
800a268: 4a11 ldr r2, [pc, #68] ; (800a2b0 <UART_SetConfig+0x318>)
800a26a: 4293 cmp r3, r2
800a26c: d139 bne.n 800a2e2 <UART_SetConfig+0x34a>
800a26e: 4b09 ldr r3, [pc, #36] ; (800a294 <UART_SetConfig+0x2fc>)
800a270: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90
800a274: f403 4340 and.w r3, r3, #49152 ; 0xc000
800a278: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
800a27c: d027 beq.n 800a2ce <UART_SetConfig+0x336>
800a27e: f5b3 4f80 cmp.w r3, #16384 ; 0x4000
800a282: d817 bhi.n 800a2b4 <UART_SetConfig+0x31c>
800a284: 2b00 cmp r3, #0
800a286: d01c beq.n 800a2c2 <UART_SetConfig+0x32a>
800a288: e027 b.n 800a2da <UART_SetConfig+0x342>
800a28a: bf00 nop
800a28c: efff69f3 .word 0xefff69f3
800a290: 40011000 .word 0x40011000
800a294: 40023800 .word 0x40023800
800a298: 40004400 .word 0x40004400
800a29c: 40004800 .word 0x40004800
800a2a0: 40004c00 .word 0x40004c00
800a2a4: 40005000 .word 0x40005000
800a2a8: 40011400 .word 0x40011400
800a2ac: 40007800 .word 0x40007800
800a2b0: 40007c00 .word 0x40007c00
800a2b4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800a2b8: d006 beq.n 800a2c8 <UART_SetConfig+0x330>
800a2ba: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
800a2be: d009 beq.n 800a2d4 <UART_SetConfig+0x33c>
800a2c0: e00b b.n 800a2da <UART_SetConfig+0x342>
800a2c2: 2300 movs r3, #0
800a2c4: 77fb strb r3, [r7, #31]
800a2c6: e00e b.n 800a2e6 <UART_SetConfig+0x34e>
800a2c8: 2302 movs r3, #2
800a2ca: 77fb strb r3, [r7, #31]
800a2cc: e00b b.n 800a2e6 <UART_SetConfig+0x34e>
800a2ce: 2304 movs r3, #4
800a2d0: 77fb strb r3, [r7, #31]
800a2d2: e008 b.n 800a2e6 <UART_SetConfig+0x34e>
800a2d4: 2308 movs r3, #8
800a2d6: 77fb strb r3, [r7, #31]
800a2d8: e005 b.n 800a2e6 <UART_SetConfig+0x34e>
800a2da: 2310 movs r3, #16
800a2dc: 77fb strb r3, [r7, #31]
800a2de: bf00 nop
800a2e0: e001 b.n 800a2e6 <UART_SetConfig+0x34e>
800a2e2: 2310 movs r3, #16
800a2e4: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800a2e6: 687b ldr r3, [r7, #4]
800a2e8: 69db ldr r3, [r3, #28]
800a2ea: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800a2ee: d17f bne.n 800a3f0 <UART_SetConfig+0x458>
{
switch (clocksource)
800a2f0: 7ffb ldrb r3, [r7, #31]
800a2f2: 2b08 cmp r3, #8
800a2f4: d85c bhi.n 800a3b0 <UART_SetConfig+0x418>
800a2f6: a201 add r2, pc, #4 ; (adr r2, 800a2fc <UART_SetConfig+0x364>)
800a2f8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a2fc: 0800a321 .word 0x0800a321
800a300: 0800a341 .word 0x0800a341
800a304: 0800a361 .word 0x0800a361
800a308: 0800a3b1 .word 0x0800a3b1
800a30c: 0800a379 .word 0x0800a379
800a310: 0800a3b1 .word 0x0800a3b1
800a314: 0800a3b1 .word 0x0800a3b1
800a318: 0800a3b1 .word 0x0800a3b1
800a31c: 0800a399 .word 0x0800a399
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800a320: f7fd fba2 bl 8007a68 <HAL_RCC_GetPCLK1Freq>
800a324: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
800a326: 68fb ldr r3, [r7, #12]
800a328: 005a lsls r2, r3, #1
800a32a: 687b ldr r3, [r7, #4]
800a32c: 685b ldr r3, [r3, #4]
800a32e: 085b lsrs r3, r3, #1
800a330: 441a add r2, r3
800a332: 687b ldr r3, [r7, #4]
800a334: 685b ldr r3, [r3, #4]
800a336: fbb2 f3f3 udiv r3, r2, r3
800a33a: b29b uxth r3, r3
800a33c: 61bb str r3, [r7, #24]
break;
800a33e: e03a b.n 800a3b6 <UART_SetConfig+0x41e>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
800a340: f7fd fba6 bl 8007a90 <HAL_RCC_GetPCLK2Freq>
800a344: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
800a346: 68fb ldr r3, [r7, #12]
800a348: 005a lsls r2, r3, #1
800a34a: 687b ldr r3, [r7, #4]
800a34c: 685b ldr r3, [r3, #4]
800a34e: 085b lsrs r3, r3, #1
800a350: 441a add r2, r3
800a352: 687b ldr r3, [r7, #4]
800a354: 685b ldr r3, [r3, #4]
800a356: fbb2 f3f3 udiv r3, r2, r3
800a35a: b29b uxth r3, r3
800a35c: 61bb str r3, [r7, #24]
break;
800a35e: e02a b.n 800a3b6 <UART_SetConfig+0x41e>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
800a360: 687b ldr r3, [r7, #4]
800a362: 685b ldr r3, [r3, #4]
800a364: 085a lsrs r2, r3, #1
800a366: 4b5f ldr r3, [pc, #380] ; (800a4e4 <UART_SetConfig+0x54c>)
800a368: 4413 add r3, r2
800a36a: 687a ldr r2, [r7, #4]
800a36c: 6852 ldr r2, [r2, #4]
800a36e: fbb3 f3f2 udiv r3, r3, r2
800a372: b29b uxth r3, r3
800a374: 61bb str r3, [r7, #24]
break;
800a376: e01e b.n 800a3b6 <UART_SetConfig+0x41e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800a378: f7fd fab8 bl 80078ec <HAL_RCC_GetSysClockFreq>
800a37c: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
800a37e: 68fb ldr r3, [r7, #12]
800a380: 005a lsls r2, r3, #1
800a382: 687b ldr r3, [r7, #4]
800a384: 685b ldr r3, [r3, #4]
800a386: 085b lsrs r3, r3, #1
800a388: 441a add r2, r3
800a38a: 687b ldr r3, [r7, #4]
800a38c: 685b ldr r3, [r3, #4]
800a38e: fbb2 f3f3 udiv r3, r2, r3
800a392: b29b uxth r3, r3
800a394: 61bb str r3, [r7, #24]
break;
800a396: e00e b.n 800a3b6 <UART_SetConfig+0x41e>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
800a398: 687b ldr r3, [r7, #4]
800a39a: 685b ldr r3, [r3, #4]
800a39c: 085b lsrs r3, r3, #1
800a39e: f503 3280 add.w r2, r3, #65536 ; 0x10000
800a3a2: 687b ldr r3, [r7, #4]
800a3a4: 685b ldr r3, [r3, #4]
800a3a6: fbb2 f3f3 udiv r3, r2, r3
800a3aa: b29b uxth r3, r3
800a3ac: 61bb str r3, [r7, #24]
break;
800a3ae: e002 b.n 800a3b6 <UART_SetConfig+0x41e>
default:
ret = HAL_ERROR;
800a3b0: 2301 movs r3, #1
800a3b2: 75fb strb r3, [r7, #23]
break;
800a3b4: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800a3b6: 69bb ldr r3, [r7, #24]
800a3b8: 2b0f cmp r3, #15
800a3ba: d916 bls.n 800a3ea <UART_SetConfig+0x452>
800a3bc: 69bb ldr r3, [r7, #24]
800a3be: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800a3c2: d212 bcs.n 800a3ea <UART_SetConfig+0x452>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
800a3c4: 69bb ldr r3, [r7, #24]
800a3c6: b29b uxth r3, r3
800a3c8: f023 030f bic.w r3, r3, #15
800a3cc: 817b strh r3, [r7, #10]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
800a3ce: 69bb ldr r3, [r7, #24]
800a3d0: 085b lsrs r3, r3, #1
800a3d2: b29b uxth r3, r3
800a3d4: f003 0307 and.w r3, r3, #7
800a3d8: b29a uxth r2, r3
800a3da: 897b ldrh r3, [r7, #10]
800a3dc: 4313 orrs r3, r2
800a3de: 817b strh r3, [r7, #10]
huart->Instance->BRR = brrtemp;
800a3e0: 687b ldr r3, [r7, #4]
800a3e2: 681b ldr r3, [r3, #0]
800a3e4: 897a ldrh r2, [r7, #10]
800a3e6: 60da str r2, [r3, #12]
800a3e8: e070 b.n 800a4cc <UART_SetConfig+0x534>
}
else
{
ret = HAL_ERROR;
800a3ea: 2301 movs r3, #1
800a3ec: 75fb strb r3, [r7, #23]
800a3ee: e06d b.n 800a4cc <UART_SetConfig+0x534>
}
}
else
{
switch (clocksource)
800a3f0: 7ffb ldrb r3, [r7, #31]
800a3f2: 2b08 cmp r3, #8
800a3f4: d859 bhi.n 800a4aa <UART_SetConfig+0x512>
800a3f6: a201 add r2, pc, #4 ; (adr r2, 800a3fc <UART_SetConfig+0x464>)
800a3f8: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800a3fc: 0800a421 .word 0x0800a421
800a400: 0800a43f .word 0x0800a43f
800a404: 0800a45d .word 0x0800a45d
800a408: 0800a4ab .word 0x0800a4ab
800a40c: 0800a475 .word 0x0800a475
800a410: 0800a4ab .word 0x0800a4ab
800a414: 0800a4ab .word 0x0800a4ab
800a418: 0800a4ab .word 0x0800a4ab
800a41c: 0800a493 .word 0x0800a493
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800a420: f7fd fb22 bl 8007a68 <HAL_RCC_GetPCLK1Freq>
800a424: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
800a426: 687b ldr r3, [r7, #4]
800a428: 685b ldr r3, [r3, #4]
800a42a: 085a lsrs r2, r3, #1
800a42c: 68fb ldr r3, [r7, #12]
800a42e: 441a add r2, r3
800a430: 687b ldr r3, [r7, #4]
800a432: 685b ldr r3, [r3, #4]
800a434: fbb2 f3f3 udiv r3, r2, r3
800a438: b29b uxth r3, r3
800a43a: 61bb str r3, [r7, #24]
break;
800a43c: e038 b.n 800a4b0 <UART_SetConfig+0x518>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
800a43e: f7fd fb27 bl 8007a90 <HAL_RCC_GetPCLK2Freq>
800a442: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
800a444: 687b ldr r3, [r7, #4]
800a446: 685b ldr r3, [r3, #4]
800a448: 085a lsrs r2, r3, #1
800a44a: 68fb ldr r3, [r7, #12]
800a44c: 441a add r2, r3
800a44e: 687b ldr r3, [r7, #4]
800a450: 685b ldr r3, [r3, #4]
800a452: fbb2 f3f3 udiv r3, r2, r3
800a456: b29b uxth r3, r3
800a458: 61bb str r3, [r7, #24]
break;
800a45a: e029 b.n 800a4b0 <UART_SetConfig+0x518>
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
800a45c: 687b ldr r3, [r7, #4]
800a45e: 685b ldr r3, [r3, #4]
800a460: 085a lsrs r2, r3, #1
800a462: 4b21 ldr r3, [pc, #132] ; (800a4e8 <UART_SetConfig+0x550>)
800a464: 4413 add r3, r2
800a466: 687a ldr r2, [r7, #4]
800a468: 6852 ldr r2, [r2, #4]
800a46a: fbb3 f3f2 udiv r3, r3, r2
800a46e: b29b uxth r3, r3
800a470: 61bb str r3, [r7, #24]
break;
800a472: e01d b.n 800a4b0 <UART_SetConfig+0x518>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
800a474: f7fd fa3a bl 80078ec <HAL_RCC_GetSysClockFreq>
800a478: 60f8 str r0, [r7, #12]
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
800a47a: 687b ldr r3, [r7, #4]
800a47c: 685b ldr r3, [r3, #4]
800a47e: 085a lsrs r2, r3, #1
800a480: 68fb ldr r3, [r7, #12]
800a482: 441a add r2, r3
800a484: 687b ldr r3, [r7, #4]
800a486: 685b ldr r3, [r3, #4]
800a488: fbb2 f3f3 udiv r3, r2, r3
800a48c: b29b uxth r3, r3
800a48e: 61bb str r3, [r7, #24]
break;
800a490: e00e b.n 800a4b0 <UART_SetConfig+0x518>
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
800a492: 687b ldr r3, [r7, #4]
800a494: 685b ldr r3, [r3, #4]
800a496: 085b lsrs r3, r3, #1
800a498: f503 4200 add.w r2, r3, #32768 ; 0x8000
800a49c: 687b ldr r3, [r7, #4]
800a49e: 685b ldr r3, [r3, #4]
800a4a0: fbb2 f3f3 udiv r3, r2, r3
800a4a4: b29b uxth r3, r3
800a4a6: 61bb str r3, [r7, #24]
break;
800a4a8: e002 b.n 800a4b0 <UART_SetConfig+0x518>
default:
ret = HAL_ERROR;
800a4aa: 2301 movs r3, #1
800a4ac: 75fb strb r3, [r7, #23]
break;
800a4ae: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
800a4b0: 69bb ldr r3, [r7, #24]
800a4b2: 2b0f cmp r3, #15
800a4b4: d908 bls.n 800a4c8 <UART_SetConfig+0x530>
800a4b6: 69bb ldr r3, [r7, #24]
800a4b8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
800a4bc: d204 bcs.n 800a4c8 <UART_SetConfig+0x530>
{
huart->Instance->BRR = usartdiv;
800a4be: 687b ldr r3, [r7, #4]
800a4c0: 681b ldr r3, [r3, #0]
800a4c2: 69ba ldr r2, [r7, #24]
800a4c4: 60da str r2, [r3, #12]
800a4c6: e001 b.n 800a4cc <UART_SetConfig+0x534>
}
else
{
ret = HAL_ERROR;
800a4c8: 2301 movs r3, #1
800a4ca: 75fb strb r3, [r7, #23]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
800a4cc: 687b ldr r3, [r7, #4]
800a4ce: 2200 movs r2, #0
800a4d0: 661a str r2, [r3, #96] ; 0x60
huart->TxISR = NULL;
800a4d2: 687b ldr r3, [r7, #4]
800a4d4: 2200 movs r2, #0
800a4d6: 665a str r2, [r3, #100] ; 0x64
return ret;
800a4d8: 7dfb ldrb r3, [r7, #23]
}
800a4da: 4618 mov r0, r3
800a4dc: 3720 adds r7, #32
800a4de: 46bd mov sp, r7
800a4e0: bd80 pop {r7, pc}
800a4e2: bf00 nop
800a4e4: 01e84800 .word 0x01e84800
800a4e8: 00f42400 .word 0x00f42400
0800a4ec <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
800a4ec: b480 push {r7}
800a4ee: b083 sub sp, #12
800a4f0: af00 add r7, sp, #0
800a4f2: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
800a4f4: 687b ldr r3, [r7, #4]
800a4f6: 6a5b ldr r3, [r3, #36] ; 0x24
800a4f8: f003 0301 and.w r3, r3, #1
800a4fc: 2b00 cmp r3, #0
800a4fe: d00a beq.n 800a516 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
800a500: 687b ldr r3, [r7, #4]
800a502: 681b ldr r3, [r3, #0]
800a504: 685b ldr r3, [r3, #4]
800a506: f423 3100 bic.w r1, r3, #131072 ; 0x20000
800a50a: 687b ldr r3, [r7, #4]
800a50c: 6a9a ldr r2, [r3, #40] ; 0x28
800a50e: 687b ldr r3, [r7, #4]
800a510: 681b ldr r3, [r3, #0]
800a512: 430a orrs r2, r1
800a514: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
800a516: 687b ldr r3, [r7, #4]
800a518: 6a5b ldr r3, [r3, #36] ; 0x24
800a51a: f003 0302 and.w r3, r3, #2
800a51e: 2b00 cmp r3, #0
800a520: d00a beq.n 800a538 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
800a522: 687b ldr r3, [r7, #4]
800a524: 681b ldr r3, [r3, #0]
800a526: 685b ldr r3, [r3, #4]
800a528: f423 3180 bic.w r1, r3, #65536 ; 0x10000
800a52c: 687b ldr r3, [r7, #4]
800a52e: 6ada ldr r2, [r3, #44] ; 0x2c
800a530: 687b ldr r3, [r7, #4]
800a532: 681b ldr r3, [r3, #0]
800a534: 430a orrs r2, r1
800a536: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
800a538: 687b ldr r3, [r7, #4]
800a53a: 6a5b ldr r3, [r3, #36] ; 0x24
800a53c: f003 0304 and.w r3, r3, #4
800a540: 2b00 cmp r3, #0
800a542: d00a beq.n 800a55a <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
800a544: 687b ldr r3, [r7, #4]
800a546: 681b ldr r3, [r3, #0]
800a548: 685b ldr r3, [r3, #4]
800a54a: f423 2180 bic.w r1, r3, #262144 ; 0x40000
800a54e: 687b ldr r3, [r7, #4]
800a550: 6b1a ldr r2, [r3, #48] ; 0x30
800a552: 687b ldr r3, [r7, #4]
800a554: 681b ldr r3, [r3, #0]
800a556: 430a orrs r2, r1
800a558: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
800a55a: 687b ldr r3, [r7, #4]
800a55c: 6a5b ldr r3, [r3, #36] ; 0x24
800a55e: f003 0308 and.w r3, r3, #8
800a562: 2b00 cmp r3, #0
800a564: d00a beq.n 800a57c <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
800a566: 687b ldr r3, [r7, #4]
800a568: 681b ldr r3, [r3, #0]
800a56a: 685b ldr r3, [r3, #4]
800a56c: f423 4100 bic.w r1, r3, #32768 ; 0x8000
800a570: 687b ldr r3, [r7, #4]
800a572: 6b5a ldr r2, [r3, #52] ; 0x34
800a574: 687b ldr r3, [r7, #4]
800a576: 681b ldr r3, [r3, #0]
800a578: 430a orrs r2, r1
800a57a: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
800a57c: 687b ldr r3, [r7, #4]
800a57e: 6a5b ldr r3, [r3, #36] ; 0x24
800a580: f003 0310 and.w r3, r3, #16
800a584: 2b00 cmp r3, #0
800a586: d00a beq.n 800a59e <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
800a588: 687b ldr r3, [r7, #4]
800a58a: 681b ldr r3, [r3, #0]
800a58c: 689b ldr r3, [r3, #8]
800a58e: f423 5180 bic.w r1, r3, #4096 ; 0x1000
800a592: 687b ldr r3, [r7, #4]
800a594: 6b9a ldr r2, [r3, #56] ; 0x38
800a596: 687b ldr r3, [r7, #4]
800a598: 681b ldr r3, [r3, #0]
800a59a: 430a orrs r2, r1
800a59c: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800a59e: 687b ldr r3, [r7, #4]
800a5a0: 6a5b ldr r3, [r3, #36] ; 0x24
800a5a2: f003 0320 and.w r3, r3, #32
800a5a6: 2b00 cmp r3, #0
800a5a8: d00a beq.n 800a5c0 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
800a5aa: 687b ldr r3, [r7, #4]
800a5ac: 681b ldr r3, [r3, #0]
800a5ae: 689b ldr r3, [r3, #8]
800a5b0: f423 5100 bic.w r1, r3, #8192 ; 0x2000
800a5b4: 687b ldr r3, [r7, #4]
800a5b6: 6bda ldr r2, [r3, #60] ; 0x3c
800a5b8: 687b ldr r3, [r7, #4]
800a5ba: 681b ldr r3, [r3, #0]
800a5bc: 430a orrs r2, r1
800a5be: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
800a5c0: 687b ldr r3, [r7, #4]
800a5c2: 6a5b ldr r3, [r3, #36] ; 0x24
800a5c4: f003 0340 and.w r3, r3, #64 ; 0x40
800a5c8: 2b00 cmp r3, #0
800a5ca: d01a beq.n 800a602 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800a5cc: 687b ldr r3, [r7, #4]
800a5ce: 681b ldr r3, [r3, #0]
800a5d0: 685b ldr r3, [r3, #4]
800a5d2: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
800a5d6: 687b ldr r3, [r7, #4]
800a5d8: 6c1a ldr r2, [r3, #64] ; 0x40
800a5da: 687b ldr r3, [r7, #4]
800a5dc: 681b ldr r3, [r3, #0]
800a5de: 430a orrs r2, r1
800a5e0: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
800a5e2: 687b ldr r3, [r7, #4]
800a5e4: 6c1b ldr r3, [r3, #64] ; 0x40
800a5e6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
800a5ea: d10a bne.n 800a602 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800a5ec: 687b ldr r3, [r7, #4]
800a5ee: 681b ldr r3, [r3, #0]
800a5f0: 685b ldr r3, [r3, #4]
800a5f2: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
800a5f6: 687b ldr r3, [r7, #4]
800a5f8: 6c5a ldr r2, [r3, #68] ; 0x44
800a5fa: 687b ldr r3, [r7, #4]
800a5fc: 681b ldr r3, [r3, #0]
800a5fe: 430a orrs r2, r1
800a600: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
800a602: 687b ldr r3, [r7, #4]
800a604: 6a5b ldr r3, [r3, #36] ; 0x24
800a606: f003 0380 and.w r3, r3, #128 ; 0x80
800a60a: 2b00 cmp r3, #0
800a60c: d00a beq.n 800a624 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800a60e: 687b ldr r3, [r7, #4]
800a610: 681b ldr r3, [r3, #0]
800a612: 685b ldr r3, [r3, #4]
800a614: f423 2100 bic.w r1, r3, #524288 ; 0x80000
800a618: 687b ldr r3, [r7, #4]
800a61a: 6c9a ldr r2, [r3, #72] ; 0x48
800a61c: 687b ldr r3, [r7, #4]
800a61e: 681b ldr r3, [r3, #0]
800a620: 430a orrs r2, r1
800a622: 605a str r2, [r3, #4]
}
}
800a624: bf00 nop
800a626: 370c adds r7, #12
800a628: 46bd mov sp, r7
800a62a: f85d 7b04 ldr.w r7, [sp], #4
800a62e: 4770 bx lr
0800a630 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
800a630: b580 push {r7, lr}
800a632: b086 sub sp, #24
800a634: af02 add r7, sp, #8
800a636: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800a638: 687b ldr r3, [r7, #4]
800a63a: 2200 movs r2, #0
800a63c: 67da str r2, [r3, #124] ; 0x7c
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
800a63e: f7f9 ff57 bl 80044f0 <HAL_GetTick>
800a642: 60f8 str r0, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800a644: 687b ldr r3, [r7, #4]
800a646: 681b ldr r3, [r3, #0]
800a648: 681b ldr r3, [r3, #0]
800a64a: f003 0308 and.w r3, r3, #8
800a64e: 2b08 cmp r3, #8
800a650: d10e bne.n 800a670 <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800a652: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
800a656: 9300 str r3, [sp, #0]
800a658: 68fb ldr r3, [r7, #12]
800a65a: 2200 movs r2, #0
800a65c: f44f 1100 mov.w r1, #2097152 ; 0x200000
800a660: 6878 ldr r0, [r7, #4]
800a662: f000 f814 bl 800a68e <UART_WaitOnFlagUntilTimeout>
800a666: 4603 mov r3, r0
800a668: 2b00 cmp r3, #0
800a66a: d001 beq.n 800a670 <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
800a66c: 2303 movs r3, #3
800a66e: e00a b.n 800a686 <UART_CheckIdleState+0x56>
}
}
#endif
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800a670: 687b ldr r3, [r7, #4]
800a672: 2220 movs r2, #32
800a674: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
800a676: 687b ldr r3, [r7, #4]
800a678: 2220 movs r2, #32
800a67a: 679a str r2, [r3, #120] ; 0x78
__HAL_UNLOCK(huart);
800a67c: 687b ldr r3, [r7, #4]
800a67e: 2200 movs r2, #0
800a680: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_OK;
800a684: 2300 movs r3, #0
}
800a686: 4618 mov r0, r3
800a688: 3710 adds r7, #16
800a68a: 46bd mov sp, r7
800a68c: bd80 pop {r7, pc}
0800a68e <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
800a68e: b580 push {r7, lr}
800a690: b084 sub sp, #16
800a692: af00 add r7, sp, #0
800a694: 60f8 str r0, [r7, #12]
800a696: 60b9 str r1, [r7, #8]
800a698: 603b str r3, [r7, #0]
800a69a: 4613 mov r3, r2
800a69c: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800a69e: e05d b.n 800a75c <UART_WaitOnFlagUntilTimeout+0xce>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
800a6a0: 69bb ldr r3, [r7, #24]
800a6a2: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800a6a6: d059 beq.n 800a75c <UART_WaitOnFlagUntilTimeout+0xce>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800a6a8: f7f9 ff22 bl 80044f0 <HAL_GetTick>
800a6ac: 4602 mov r2, r0
800a6ae: 683b ldr r3, [r7, #0]
800a6b0: 1ad3 subs r3, r2, r3
800a6b2: 69ba ldr r2, [r7, #24]
800a6b4: 429a cmp r2, r3
800a6b6: d302 bcc.n 800a6be <UART_WaitOnFlagUntilTimeout+0x30>
800a6b8: 69bb ldr r3, [r7, #24]
800a6ba: 2b00 cmp r3, #0
800a6bc: d11b bne.n 800a6f6 <UART_WaitOnFlagUntilTimeout+0x68>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
800a6be: 68fb ldr r3, [r7, #12]
800a6c0: 681b ldr r3, [r3, #0]
800a6c2: 681a ldr r2, [r3, #0]
800a6c4: 68fb ldr r3, [r7, #12]
800a6c6: 681b ldr r3, [r3, #0]
800a6c8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
800a6cc: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800a6ce: 68fb ldr r3, [r7, #12]
800a6d0: 681b ldr r3, [r3, #0]
800a6d2: 689a ldr r2, [r3, #8]
800a6d4: 68fb ldr r3, [r7, #12]
800a6d6: 681b ldr r3, [r3, #0]
800a6d8: f022 0201 bic.w r2, r2, #1
800a6dc: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
800a6de: 68fb ldr r3, [r7, #12]
800a6e0: 2220 movs r2, #32
800a6e2: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
800a6e4: 68fb ldr r3, [r7, #12]
800a6e6: 2220 movs r2, #32
800a6e8: 679a str r2, [r3, #120] ; 0x78
__HAL_UNLOCK(huart);
800a6ea: 68fb ldr r3, [r7, #12]
800a6ec: 2200 movs r2, #0
800a6ee: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_TIMEOUT;
800a6f2: 2303 movs r3, #3
800a6f4: e042 b.n 800a77c <UART_WaitOnFlagUntilTimeout+0xee>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
800a6f6: 68fb ldr r3, [r7, #12]
800a6f8: 681b ldr r3, [r3, #0]
800a6fa: 681b ldr r3, [r3, #0]
800a6fc: f003 0304 and.w r3, r3, #4
800a700: 2b00 cmp r3, #0
800a702: d02b beq.n 800a75c <UART_WaitOnFlagUntilTimeout+0xce>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
800a704: 68fb ldr r3, [r7, #12]
800a706: 681b ldr r3, [r3, #0]
800a708: 69db ldr r3, [r3, #28]
800a70a: f403 6300 and.w r3, r3, #2048 ; 0x800
800a70e: f5b3 6f00 cmp.w r3, #2048 ; 0x800
800a712: d123 bne.n 800a75c <UART_WaitOnFlagUntilTimeout+0xce>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
800a714: 68fb ldr r3, [r7, #12]
800a716: 681b ldr r3, [r3, #0]
800a718: f44f 6200 mov.w r2, #2048 ; 0x800
800a71c: 621a str r2, [r3, #32]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
800a71e: 68fb ldr r3, [r7, #12]
800a720: 681b ldr r3, [r3, #0]
800a722: 681a ldr r2, [r3, #0]
800a724: 68fb ldr r3, [r7, #12]
800a726: 681b ldr r3, [r3, #0]
800a728: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
800a72c: 601a str r2, [r3, #0]
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800a72e: 68fb ldr r3, [r7, #12]
800a730: 681b ldr r3, [r3, #0]
800a732: 689a ldr r2, [r3, #8]
800a734: 68fb ldr r3, [r7, #12]
800a736: 681b ldr r3, [r3, #0]
800a738: f022 0201 bic.w r2, r2, #1
800a73c: 609a str r2, [r3, #8]
huart->gState = HAL_UART_STATE_READY;
800a73e: 68fb ldr r3, [r7, #12]
800a740: 2220 movs r2, #32
800a742: 675a str r2, [r3, #116] ; 0x74
huart->RxState = HAL_UART_STATE_READY;
800a744: 68fb ldr r3, [r7, #12]
800a746: 2220 movs r2, #32
800a748: 679a str r2, [r3, #120] ; 0x78
huart->ErrorCode = HAL_UART_ERROR_RTO;
800a74a: 68fb ldr r3, [r7, #12]
800a74c: 2220 movs r2, #32
800a74e: 67da str r2, [r3, #124] ; 0x7c
/* Process Unlocked */
__HAL_UNLOCK(huart);
800a750: 68fb ldr r3, [r7, #12]
800a752: 2200 movs r2, #0
800a754: f883 2070 strb.w r2, [r3, #112] ; 0x70
return HAL_TIMEOUT;
800a758: 2303 movs r3, #3
800a75a: e00f b.n 800a77c <UART_WaitOnFlagUntilTimeout+0xee>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800a75c: 68fb ldr r3, [r7, #12]
800a75e: 681b ldr r3, [r3, #0]
800a760: 69da ldr r2, [r3, #28]
800a762: 68bb ldr r3, [r7, #8]
800a764: 4013 ands r3, r2
800a766: 68ba ldr r2, [r7, #8]
800a768: 429a cmp r2, r3
800a76a: bf0c ite eq
800a76c: 2301 moveq r3, #1
800a76e: 2300 movne r3, #0
800a770: b2db uxtb r3, r3
800a772: 461a mov r2, r3
800a774: 79fb ldrb r3, [r7, #7]
800a776: 429a cmp r2, r3
800a778: d092 beq.n 800a6a0 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800a77a: 2300 movs r3, #0
}
800a77c: 4618 mov r0, r3
800a77e: 3710 adds r7, #16
800a780: 46bd mov sp, r7
800a782: bd80 pop {r7, pc}
0800a784 <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
800a784: b480 push {r7}
800a786: b085 sub sp, #20
800a788: af00 add r7, sp, #0
800a78a: 6078 str r0, [r7, #4]
800a78c: 6039 str r1, [r7, #0]
uint32_t tmpr1 = 0;
800a78e: 2300 movs r3, #0
800a790: 60fb str r3, [r7, #12]
uint32_t tmpr2 = 0;
800a792: 2300 movs r3, #0
800a794: 60bb str r3, [r7, #8]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
800a796: 683b ldr r3, [r7, #0]
800a798: 681b ldr r3, [r3, #0]
800a79a: 2b01 cmp r3, #1
800a79c: d027 beq.n 800a7ee <FMC_SDRAM_Init+0x6a>
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800a79e: 687b ldr r3, [r7, #4]
800a7a0: 681b ldr r3, [r3, #0]
800a7a2: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800a7a4: 68fa ldr r2, [r7, #12]
800a7a6: 4b2f ldr r3, [pc, #188] ; (800a864 <FMC_SDRAM_Init+0xe0>)
800a7a8: 4013 ands r3, r2
800a7aa: 60fb str r3, [r7, #12]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800a7ac: 683b ldr r3, [r7, #0]
800a7ae: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800a7b0: 683b ldr r3, [r7, #0]
800a7b2: 689b ldr r3, [r3, #8]
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800a7b4: 431a orrs r2, r3
Init->MemoryDataWidth |\
800a7b6: 683b ldr r3, [r7, #0]
800a7b8: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800a7ba: 431a orrs r2, r3
Init->InternalBankNumber |\
800a7bc: 683b ldr r3, [r7, #0]
800a7be: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800a7c0: 431a orrs r2, r3
Init->CASLatency |\
800a7c2: 683b ldr r3, [r7, #0]
800a7c4: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800a7c6: 431a orrs r2, r3
Init->WriteProtection |\
800a7c8: 683b ldr r3, [r7, #0]
800a7ca: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800a7cc: 431a orrs r2, r3
Init->SDClockPeriod |\
800a7ce: 683b ldr r3, [r7, #0]
800a7d0: 69db ldr r3, [r3, #28]
Init->WriteProtection |\
800a7d2: 431a orrs r2, r3
Init->ReadBurst |\
800a7d4: 683b ldr r3, [r7, #0]
800a7d6: 6a1b ldr r3, [r3, #32]
Init->SDClockPeriod |\
800a7d8: 431a orrs r2, r3
Init->ReadPipeDelay
800a7da: 683b ldr r3, [r7, #0]
800a7dc: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800a7de: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800a7e0: 68fa ldr r2, [r7, #12]
800a7e2: 4313 orrs r3, r2
800a7e4: 60fb str r3, [r7, #12]
);
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800a7e6: 687b ldr r3, [r7, #4]
800a7e8: 68fa ldr r2, [r7, #12]
800a7ea: 601a str r2, [r3, #0]
800a7ec: e032 b.n 800a854 <FMC_SDRAM_Init+0xd0>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800a7ee: 687b ldr r3, [r7, #4]
800a7f0: 681b ldr r3, [r3, #0]
800a7f2: 60fb str r3, [r7, #12]
/* Clear SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
800a7f4: 68fb ldr r3, [r7, #12]
800a7f6: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
800a7fa: 60fb str r3, [r7, #12]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800a7fc: 683b ldr r3, [r7, #0]
800a7fe: 69da ldr r2, [r3, #28]
Init->ReadBurst |\
800a800: 683b ldr r3, [r7, #0]
800a802: 6a1b ldr r3, [r3, #32]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800a804: 431a orrs r2, r3
Init->ReadPipeDelay);
800a806: 683b ldr r3, [r7, #0]
800a808: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
800a80a: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
800a80c: 68fa ldr r2, [r7, #12]
800a80e: 4313 orrs r3, r2
800a810: 60fb str r3, [r7, #12]
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
800a812: 687b ldr r3, [r7, #4]
800a814: 685b ldr r3, [r3, #4]
800a816: 60bb str r3, [r7, #8]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
800a818: 68ba ldr r2, [r7, #8]
800a81a: 4b12 ldr r3, [pc, #72] ; (800a864 <FMC_SDRAM_Init+0xe0>)
800a81c: 4013 ands r3, r2
800a81e: 60bb str r3, [r7, #8]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800a820: 683b ldr r3, [r7, #0]
800a822: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
800a824: 683b ldr r3, [r7, #0]
800a826: 689b ldr r3, [r3, #8]
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800a828: 431a orrs r2, r3
Init->MemoryDataWidth |\
800a82a: 683b ldr r3, [r7, #0]
800a82c: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
800a82e: 431a orrs r2, r3
Init->InternalBankNumber |\
800a830: 683b ldr r3, [r7, #0]
800a832: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
800a834: 431a orrs r2, r3
Init->CASLatency |\
800a836: 683b ldr r3, [r7, #0]
800a838: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
800a83a: 431a orrs r2, r3
Init->WriteProtection);
800a83c: 683b ldr r3, [r7, #0]
800a83e: 699b ldr r3, [r3, #24]
Init->CASLatency |\
800a840: 4313 orrs r3, r2
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
800a842: 68ba ldr r2, [r7, #8]
800a844: 4313 orrs r3, r2
800a846: 60bb str r3, [r7, #8]
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
800a848: 687b ldr r3, [r7, #4]
800a84a: 68fa ldr r2, [r7, #12]
800a84c: 601a str r2, [r3, #0]
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
800a84e: 687b ldr r3, [r7, #4]
800a850: 68ba ldr r2, [r7, #8]
800a852: 605a str r2, [r3, #4]
}
return HAL_OK;
800a854: 2300 movs r3, #0
}
800a856: 4618 mov r0, r3
800a858: 3714 adds r7, #20
800a85a: 46bd mov sp, r7
800a85c: f85d 7b04 ldr.w r7, [sp], #4
800a860: 4770 bx lr
800a862: bf00 nop
800a864: ffff8000 .word 0xffff8000
0800a868 <FMC_SDRAM_Timing_Init>:
* @param Timing Pointer to SDRAM Timing structure
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
800a868: b480 push {r7}
800a86a: b087 sub sp, #28
800a86c: af00 add r7, sp, #0
800a86e: 60f8 str r0, [r7, #12]
800a870: 60b9 str r1, [r7, #8]
800a872: 607a str r2, [r7, #4]
uint32_t tmpr1 = 0;
800a874: 2300 movs r3, #0
800a876: 617b str r3, [r7, #20]
uint32_t tmpr2 = 0;
800a878: 2300 movs r3, #0
800a87a: 613b str r3, [r7, #16]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
800a87c: 687b ldr r3, [r7, #4]
800a87e: 2b01 cmp r3, #1
800a880: d02e beq.n 800a8e0 <FMC_SDRAM_Timing_Init+0x78>
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800a882: 68fb ldr r3, [r7, #12]
800a884: 689b ldr r3, [r3, #8]
800a886: 617b str r3, [r7, #20]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800a888: 697b ldr r3, [r7, #20]
800a88a: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800a88e: 617b str r3, [r7, #20]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a890: 68bb ldr r3, [r7, #8]
800a892: 681b ldr r3, [r3, #0]
800a894: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800a896: 68bb ldr r3, [r7, #8]
800a898: 685b ldr r3, [r3, #4]
800a89a: 3b01 subs r3, #1
800a89c: 011b lsls r3, r3, #4
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a89e: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800a8a0: 68bb ldr r3, [r7, #8]
800a8a2: 689b ldr r3, [r3, #8]
800a8a4: 3b01 subs r3, #1
800a8a6: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800a8a8: 431a orrs r2, r3
(((Timing->RowCycleDelay)-1) << 12) |\
800a8aa: 68bb ldr r3, [r7, #8]
800a8ac: 68db ldr r3, [r3, #12]
800a8ae: 3b01 subs r3, #1
800a8b0: 031b lsls r3, r3, #12
(((Timing->SelfRefreshTime)-1) << 8) |\
800a8b2: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800a8b4: 68bb ldr r3, [r7, #8]
800a8b6: 691b ldr r3, [r3, #16]
800a8b8: 3b01 subs r3, #1
800a8ba: 041b lsls r3, r3, #16
(((Timing->RowCycleDelay)-1) << 12) |\
800a8bc: 431a orrs r2, r3
(((Timing->RPDelay)-1) << 20) |\
800a8be: 68bb ldr r3, [r7, #8]
800a8c0: 695b ldr r3, [r3, #20]
800a8c2: 3b01 subs r3, #1
800a8c4: 051b lsls r3, r3, #20
(((Timing->WriteRecoveryTime)-1) <<16) |\
800a8c6: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800a8c8: 68bb ldr r3, [r7, #8]
800a8ca: 699b ldr r3, [r3, #24]
800a8cc: 3b01 subs r3, #1
800a8ce: 061b lsls r3, r3, #24
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a8d0: 4313 orrs r3, r2
800a8d2: 697a ldr r2, [r7, #20]
800a8d4: 4313 orrs r3, r2
800a8d6: 617b str r3, [r7, #20]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800a8d8: 68fb ldr r3, [r7, #12]
800a8da: 697a ldr r2, [r7, #20]
800a8dc: 609a str r2, [r3, #8]
800a8de: e039 b.n 800a954 <FMC_SDRAM_Timing_Init+0xec>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
800a8e0: 68fb ldr r3, [r7, #12]
800a8e2: 689b ldr r3, [r3, #8]
800a8e4: 617b str r3, [r7, #20]
/* Clear TRC and TRP bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
800a8e6: 697a ldr r2, [r7, #20]
800a8e8: 4b1e ldr r3, [pc, #120] ; (800a964 <FMC_SDRAM_Timing_Init+0xfc>)
800a8ea: 4013 ands r3, r2
800a8ec: 617b str r3, [r7, #20]
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800a8ee: 68bb ldr r3, [r7, #8]
800a8f0: 68db ldr r3, [r3, #12]
800a8f2: 3b01 subs r3, #1
800a8f4: 031a lsls r2, r3, #12
(((Timing->RPDelay)-1) << 20));
800a8f6: 68bb ldr r3, [r7, #8]
800a8f8: 695b ldr r3, [r3, #20]
800a8fa: 3b01 subs r3, #1
800a8fc: 051b lsls r3, r3, #20
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
800a8fe: 4313 orrs r3, r2
800a900: 697a ldr r2, [r7, #20]
800a902: 4313 orrs r3, r2
800a904: 617b str r3, [r7, #20]
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
800a906: 68fb ldr r3, [r7, #12]
800a908: 68db ldr r3, [r3, #12]
800a90a: 613b str r3, [r7, #16]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
800a90c: 693b ldr r3, [r7, #16]
800a90e: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
800a912: 613b str r3, [r7, #16]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a914: 68bb ldr r3, [r7, #8]
800a916: 681b ldr r3, [r3, #0]
800a918: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800a91a: 68bb ldr r3, [r7, #8]
800a91c: 685b ldr r3, [r3, #4]
800a91e: 3b01 subs r3, #1
800a920: 011b lsls r3, r3, #4
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a922: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1) << 8) |\
800a924: 68bb ldr r3, [r7, #8]
800a926: 689b ldr r3, [r3, #8]
800a928: 3b01 subs r3, #1
800a92a: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
800a92c: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1) <<16) |\
800a92e: 68bb ldr r3, [r7, #8]
800a930: 691b ldr r3, [r3, #16]
800a932: 3b01 subs r3, #1
800a934: 041b lsls r3, r3, #16
(((Timing->SelfRefreshTime)-1) << 8) |\
800a936: 431a orrs r2, r3
(((Timing->RCDDelay)-1) << 24));
800a938: 68bb ldr r3, [r7, #8]
800a93a: 699b ldr r3, [r3, #24]
800a93c: 3b01 subs r3, #1
800a93e: 061b lsls r3, r3, #24
tmpr2 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
800a940: 4313 orrs r3, r2
800a942: 693a ldr r2, [r7, #16]
800a944: 4313 orrs r3, r2
800a946: 613b str r3, [r7, #16]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
800a948: 68fb ldr r3, [r7, #12]
800a94a: 697a ldr r2, [r7, #20]
800a94c: 609a str r2, [r3, #8]
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
800a94e: 68fb ldr r3, [r7, #12]
800a950: 693a ldr r2, [r7, #16]
800a952: 60da str r2, [r3, #12]
}
return HAL_OK;
800a954: 2300 movs r3, #0
}
800a956: 4618 mov r0, r3
800a958: 371c adds r7, #28
800a95a: 46bd mov sp, r7
800a95c: f85d 7b04 ldr.w r7, [sp], #4
800a960: 4770 bx lr
800a962: bf00 nop
800a964: ff0f0fff .word 0xff0f0fff
0800a968 <FMC_SDRAM_SendCommand>:
* @param Timing Pointer to SDRAM Timing structure
* @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
800a968: b480 push {r7}
800a96a: b087 sub sp, #28
800a96c: af00 add r7, sp, #0
800a96e: 60f8 str r0, [r7, #12]
800a970: 60b9 str r1, [r7, #8]
800a972: 607a str r2, [r7, #4]
__IO uint32_t tmpr = 0;
800a974: 2300 movs r3, #0
800a976: 617b str r3, [r7, #20]
assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
/* Set command register */
tmpr = (uint32_t)((Command->CommandMode) |\
800a978: 68bb ldr r3, [r7, #8]
800a97a: 681a ldr r2, [r3, #0]
(Command->CommandTarget) |\
800a97c: 68bb ldr r3, [r7, #8]
800a97e: 685b ldr r3, [r3, #4]
tmpr = (uint32_t)((Command->CommandMode) |\
800a980: 431a orrs r2, r3
(((Command->AutoRefreshNumber)-1) << 5) |\
800a982: 68bb ldr r3, [r7, #8]
800a984: 689b ldr r3, [r3, #8]
800a986: 3b01 subs r3, #1
800a988: 015b lsls r3, r3, #5
(Command->CommandTarget) |\
800a98a: 431a orrs r2, r3
((Command->ModeRegisterDefinition) << 9)
800a98c: 68bb ldr r3, [r7, #8]
800a98e: 68db ldr r3, [r3, #12]
800a990: 025b lsls r3, r3, #9
tmpr = (uint32_t)((Command->CommandMode) |\
800a992: 4313 orrs r3, r2
800a994: 617b str r3, [r7, #20]
);
Device->SDCMR = tmpr;
800a996: 697a ldr r2, [r7, #20]
800a998: 68fb ldr r3, [r7, #12]
800a99a: 611a str r2, [r3, #16]
return HAL_OK;
800a99c: 2300 movs r3, #0
}
800a99e: 4618 mov r0, r3
800a9a0: 371c adds r7, #28
800a9a2: 46bd mov sp, r7
800a9a4: f85d 7b04 ldr.w r7, [sp], #4
800a9a8: 4770 bx lr
0800a9aa <FMC_SDRAM_ProgramRefreshRate>:
* @param Device Pointer to SDRAM device instance
* @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
{
800a9aa: b480 push {r7}
800a9ac: b083 sub sp, #12
800a9ae: af00 add r7, sp, #0
800a9b0: 6078 str r0, [r7, #4]
800a9b2: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
/* Set the refresh rate in command register */
Device->SDRTR |= (RefreshRate<<1);
800a9b4: 687b ldr r3, [r7, #4]
800a9b6: 695a ldr r2, [r3, #20]
800a9b8: 683b ldr r3, [r7, #0]
800a9ba: 005b lsls r3, r3, #1
800a9bc: 431a orrs r2, r3
800a9be: 687b ldr r3, [r7, #4]
800a9c0: 615a str r2, [r3, #20]
return HAL_OK;
800a9c2: 2300 movs r3, #0
}
800a9c4: 4618 mov r0, r3
800a9c6: 370c adds r7, #12
800a9c8: 46bd mov sp, r7
800a9ca: f85d 7b04 ldr.w r7, [sp], #4
800a9ce: 4770 bx lr
0800a9d0 <makeFreeRtosPriority>:
extern void xPortSysTickHandler(void);
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
{
800a9d0: b480 push {r7}
800a9d2: b085 sub sp, #20
800a9d4: af00 add r7, sp, #0
800a9d6: 4603 mov r3, r0
800a9d8: 80fb strh r3, [r7, #6]
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
800a9da: 2300 movs r3, #0
800a9dc: 60fb str r3, [r7, #12]
if (priority != osPriorityError) {
800a9de: f9b7 3006 ldrsh.w r3, [r7, #6]
800a9e2: 2b84 cmp r3, #132 ; 0x84
800a9e4: d005 beq.n 800a9f2 <makeFreeRtosPriority+0x22>
fpriority += (priority - osPriorityIdle);
800a9e6: f9b7 2006 ldrsh.w r2, [r7, #6]
800a9ea: 68fb ldr r3, [r7, #12]
800a9ec: 4413 add r3, r2
800a9ee: 3303 adds r3, #3
800a9f0: 60fb str r3, [r7, #12]
}
return fpriority;
800a9f2: 68fb ldr r3, [r7, #12]
}
800a9f4: 4618 mov r0, r3
800a9f6: 3714 adds r7, #20
800a9f8: 46bd mov sp, r7
800a9fa: f85d 7b04 ldr.w r7, [sp], #4
800a9fe: 4770 bx lr
0800aa00 <osThreadCreate>:
* @param argument pointer that is passed to the thread function as start argument.
* @retval thread ID for reference by other functions or NULL in case of error.
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
*/
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
{
800aa00: b5f0 push {r4, r5, r6, r7, lr}
800aa02: b089 sub sp, #36 ; 0x24
800aa04: af04 add r7, sp, #16
800aa06: 6078 str r0, [r7, #4]
800aa08: 6039 str r1, [r7, #0]
TaskHandle_t handle;
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
800aa0a: 687b ldr r3, [r7, #4]
800aa0c: 695b ldr r3, [r3, #20]
800aa0e: 2b00 cmp r3, #0
800aa10: d020 beq.n 800aa54 <osThreadCreate+0x54>
800aa12: 687b ldr r3, [r7, #4]
800aa14: 699b ldr r3, [r3, #24]
800aa16: 2b00 cmp r3, #0
800aa18: d01c beq.n 800aa54 <osThreadCreate+0x54>
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800aa1a: 687b ldr r3, [r7, #4]
800aa1c: 685c ldr r4, [r3, #4]
800aa1e: 687b ldr r3, [r7, #4]
800aa20: 681d ldr r5, [r3, #0]
800aa22: 687b ldr r3, [r7, #4]
800aa24: 691e ldr r6, [r3, #16]
800aa26: 687b ldr r3, [r7, #4]
800aa28: f9b3 3008 ldrsh.w r3, [r3, #8]
800aa2c: 4618 mov r0, r3
800aa2e: f7ff ffcf bl 800a9d0 <makeFreeRtosPriority>
800aa32: 4601 mov r1, r0
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
thread_def->buffer, thread_def->controlblock);
800aa34: 687b ldr r3, [r7, #4]
800aa36: 695b ldr r3, [r3, #20]
800aa38: 687a ldr r2, [r7, #4]
800aa3a: 6992 ldr r2, [r2, #24]
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800aa3c: 9202 str r2, [sp, #8]
800aa3e: 9301 str r3, [sp, #4]
800aa40: 9100 str r1, [sp, #0]
800aa42: 683b ldr r3, [r7, #0]
800aa44: 4632 mov r2, r6
800aa46: 4629 mov r1, r5
800aa48: 4620 mov r0, r4
800aa4a: f000 f8ed bl 800ac28 <xTaskCreateStatic>
800aa4e: 4603 mov r3, r0
800aa50: 60fb str r3, [r7, #12]
800aa52: e01c b.n 800aa8e <osThreadCreate+0x8e>
}
else {
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800aa54: 687b ldr r3, [r7, #4]
800aa56: 685c ldr r4, [r3, #4]
800aa58: 687b ldr r3, [r7, #4]
800aa5a: 681d ldr r5, [r3, #0]
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
800aa5c: 687b ldr r3, [r7, #4]
800aa5e: 691b ldr r3, [r3, #16]
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
800aa60: b29e uxth r6, r3
800aa62: 687b ldr r3, [r7, #4]
800aa64: f9b3 3008 ldrsh.w r3, [r3, #8]
800aa68: 4618 mov r0, r3
800aa6a: f7ff ffb1 bl 800a9d0 <makeFreeRtosPriority>
800aa6e: 4602 mov r2, r0
800aa70: f107 030c add.w r3, r7, #12
800aa74: 9301 str r3, [sp, #4]
800aa76: 9200 str r2, [sp, #0]
800aa78: 683b ldr r3, [r7, #0]
800aa7a: 4632 mov r2, r6
800aa7c: 4629 mov r1, r5
800aa7e: 4620 mov r0, r4
800aa80: f000 f932 bl 800ace8 <xTaskCreate>
800aa84: 4603 mov r3, r0
800aa86: 2b01 cmp r3, #1
800aa88: d001 beq.n 800aa8e <osThreadCreate+0x8e>
&handle) != pdPASS) {
return NULL;
800aa8a: 2300 movs r3, #0
800aa8c: e000 b.n 800aa90 <osThreadCreate+0x90>
&handle) != pdPASS) {
return NULL;
}
#endif
return handle;
800aa8e: 68fb ldr r3, [r7, #12]
}
800aa90: 4618 mov r0, r3
800aa92: 3714 adds r7, #20
800aa94: 46bd mov sp, r7
800aa96: bdf0 pop {r4, r5, r6, r7, pc}
0800aa98 <osDelay>:
* @brief Wait for Timeout (Time Delay)
* @param millisec time delay value
* @retval status code that indicates the execution status of the function.
*/
osStatus osDelay (uint32_t millisec)
{
800aa98: b580 push {r7, lr}
800aa9a: b084 sub sp, #16
800aa9c: af00 add r7, sp, #0
800aa9e: 6078 str r0, [r7, #4]
#if INCLUDE_vTaskDelay
TickType_t ticks = millisec / portTICK_PERIOD_MS;
800aaa0: 687b ldr r3, [r7, #4]
800aaa2: 60fb str r3, [r7, #12]
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
800aaa4: 68fb ldr r3, [r7, #12]
800aaa6: 2b00 cmp r3, #0
800aaa8: d001 beq.n 800aaae <osDelay+0x16>
800aaaa: 68fb ldr r3, [r7, #12]
800aaac: e000 b.n 800aab0 <osDelay+0x18>
800aaae: 2301 movs r3, #1
800aab0: 4618 mov r0, r3
800aab2: f000 fa5b bl 800af6c <vTaskDelay>
return osOK;
800aab6: 2300 movs r3, #0
#else
(void) millisec;
return osErrorResource;
#endif
}
800aab8: 4618 mov r0, r3
800aaba: 3710 adds r7, #16
800aabc: 46bd mov sp, r7
800aabe: bd80 pop {r7, pc}
0800aac0 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
800aac0: b480 push {r7}
800aac2: b083 sub sp, #12
800aac4: af00 add r7, sp, #0
800aac6: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800aac8: 687b ldr r3, [r7, #4]
800aaca: f103 0208 add.w r2, r3, #8
800aace: 687b ldr r3, [r7, #4]
800aad0: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
800aad2: 687b ldr r3, [r7, #4]
800aad4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800aad8: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800aada: 687b ldr r3, [r7, #4]
800aadc: f103 0208 add.w r2, r3, #8
800aae0: 687b ldr r3, [r7, #4]
800aae2: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
800aae4: 687b ldr r3, [r7, #4]
800aae6: f103 0208 add.w r2, r3, #8
800aaea: 687b ldr r3, [r7, #4]
800aaec: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
800aaee: 687b ldr r3, [r7, #4]
800aaf0: 2200 movs r2, #0
800aaf2: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
800aaf4: bf00 nop
800aaf6: 370c adds r7, #12
800aaf8: 46bd mov sp, r7
800aafa: f85d 7b04 ldr.w r7, [sp], #4
800aafe: 4770 bx lr
0800ab00 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
800ab00: b480 push {r7}
800ab02: b083 sub sp, #12
800ab04: af00 add r7, sp, #0
800ab06: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
800ab08: 687b ldr r3, [r7, #4]
800ab0a: 2200 movs r2, #0
800ab0c: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
800ab0e: bf00 nop
800ab10: 370c adds r7, #12
800ab12: 46bd mov sp, r7
800ab14: f85d 7b04 ldr.w r7, [sp], #4
800ab18: 4770 bx lr
0800ab1a <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800ab1a: b480 push {r7}
800ab1c: b085 sub sp, #20
800ab1e: af00 add r7, sp, #0
800ab20: 6078 str r0, [r7, #4]
800ab22: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
800ab24: 687b ldr r3, [r7, #4]
800ab26: 685b ldr r3, [r3, #4]
800ab28: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
800ab2a: 683b ldr r3, [r7, #0]
800ab2c: 68fa ldr r2, [r7, #12]
800ab2e: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
800ab30: 68fb ldr r3, [r7, #12]
800ab32: 689a ldr r2, [r3, #8]
800ab34: 683b ldr r3, [r7, #0]
800ab36: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
800ab38: 68fb ldr r3, [r7, #12]
800ab3a: 689b ldr r3, [r3, #8]
800ab3c: 683a ldr r2, [r7, #0]
800ab3e: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
800ab40: 68fb ldr r3, [r7, #12]
800ab42: 683a ldr r2, [r7, #0]
800ab44: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
800ab46: 683b ldr r3, [r7, #0]
800ab48: 687a ldr r2, [r7, #4]
800ab4a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800ab4c: 687b ldr r3, [r7, #4]
800ab4e: 681b ldr r3, [r3, #0]
800ab50: 1c5a adds r2, r3, #1
800ab52: 687b ldr r3, [r7, #4]
800ab54: 601a str r2, [r3, #0]
}
800ab56: bf00 nop
800ab58: 3714 adds r7, #20
800ab5a: 46bd mov sp, r7
800ab5c: f85d 7b04 ldr.w r7, [sp], #4
800ab60: 4770 bx lr
0800ab62 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
800ab62: b480 push {r7}
800ab64: b085 sub sp, #20
800ab66: af00 add r7, sp, #0
800ab68: 6078 str r0, [r7, #4]
800ab6a: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
800ab6c: 683b ldr r3, [r7, #0]
800ab6e: 681b ldr r3, [r3, #0]
800ab70: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
800ab72: 68bb ldr r3, [r7, #8]
800ab74: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800ab78: d103 bne.n 800ab82 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
800ab7a: 687b ldr r3, [r7, #4]
800ab7c: 691b ldr r3, [r3, #16]
800ab7e: 60fb str r3, [r7, #12]
800ab80: e00c b.n 800ab9c <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
800ab82: 687b ldr r3, [r7, #4]
800ab84: 3308 adds r3, #8
800ab86: 60fb str r3, [r7, #12]
800ab88: e002 b.n 800ab90 <vListInsert+0x2e>
800ab8a: 68fb ldr r3, [r7, #12]
800ab8c: 685b ldr r3, [r3, #4]
800ab8e: 60fb str r3, [r7, #12]
800ab90: 68fb ldr r3, [r7, #12]
800ab92: 685b ldr r3, [r3, #4]
800ab94: 681b ldr r3, [r3, #0]
800ab96: 68ba ldr r2, [r7, #8]
800ab98: 429a cmp r2, r3
800ab9a: d2f6 bcs.n 800ab8a <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
800ab9c: 68fb ldr r3, [r7, #12]
800ab9e: 685a ldr r2, [r3, #4]
800aba0: 683b ldr r3, [r7, #0]
800aba2: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
800aba4: 683b ldr r3, [r7, #0]
800aba6: 685b ldr r3, [r3, #4]
800aba8: 683a ldr r2, [r7, #0]
800abaa: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
800abac: 683b ldr r3, [r7, #0]
800abae: 68fa ldr r2, [r7, #12]
800abb0: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
800abb2: 68fb ldr r3, [r7, #12]
800abb4: 683a ldr r2, [r7, #0]
800abb6: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
800abb8: 683b ldr r3, [r7, #0]
800abba: 687a ldr r2, [r7, #4]
800abbc: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
800abbe: 687b ldr r3, [r7, #4]
800abc0: 681b ldr r3, [r3, #0]
800abc2: 1c5a adds r2, r3, #1
800abc4: 687b ldr r3, [r7, #4]
800abc6: 601a str r2, [r3, #0]
}
800abc8: bf00 nop
800abca: 3714 adds r7, #20
800abcc: 46bd mov sp, r7
800abce: f85d 7b04 ldr.w r7, [sp], #4
800abd2: 4770 bx lr
0800abd4 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
800abd4: b480 push {r7}
800abd6: b085 sub sp, #20
800abd8: af00 add r7, sp, #0
800abda: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
800abdc: 687b ldr r3, [r7, #4]
800abde: 691b ldr r3, [r3, #16]
800abe0: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
800abe2: 687b ldr r3, [r7, #4]
800abe4: 685b ldr r3, [r3, #4]
800abe6: 687a ldr r2, [r7, #4]
800abe8: 6892 ldr r2, [r2, #8]
800abea: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
800abec: 687b ldr r3, [r7, #4]
800abee: 689b ldr r3, [r3, #8]
800abf0: 687a ldr r2, [r7, #4]
800abf2: 6852 ldr r2, [r2, #4]
800abf4: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
800abf6: 68fb ldr r3, [r7, #12]
800abf8: 685b ldr r3, [r3, #4]
800abfa: 687a ldr r2, [r7, #4]
800abfc: 429a cmp r2, r3
800abfe: d103 bne.n 800ac08 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
800ac00: 687b ldr r3, [r7, #4]
800ac02: 689a ldr r2, [r3, #8]
800ac04: 68fb ldr r3, [r7, #12]
800ac06: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
800ac08: 687b ldr r3, [r7, #4]
800ac0a: 2200 movs r2, #0
800ac0c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
800ac0e: 68fb ldr r3, [r7, #12]
800ac10: 681b ldr r3, [r3, #0]
800ac12: 1e5a subs r2, r3, #1
800ac14: 68fb ldr r3, [r7, #12]
800ac16: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
800ac18: 68fb ldr r3, [r7, #12]
800ac1a: 681b ldr r3, [r3, #0]
}
800ac1c: 4618 mov r0, r3
800ac1e: 3714 adds r7, #20
800ac20: 46bd mov sp, r7
800ac22: f85d 7b04 ldr.w r7, [sp], #4
800ac26: 4770 bx lr
0800ac28 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
800ac28: b580 push {r7, lr}
800ac2a: b08e sub sp, #56 ; 0x38
800ac2c: af04 add r7, sp, #16
800ac2e: 60f8 str r0, [r7, #12]
800ac30: 60b9 str r1, [r7, #8]
800ac32: 607a str r2, [r7, #4]
800ac34: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800ac36: 6b7b ldr r3, [r7, #52] ; 0x34
800ac38: 2b00 cmp r3, #0
800ac3a: d10b bne.n 800ac54 <xTaskCreateStatic+0x2c>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
800ac3c: f04f 0350 mov.w r3, #80 ; 0x50
800ac40: b672 cpsid i
800ac42: f383 8811 msr BASEPRI, r3
800ac46: f3bf 8f6f isb sy
800ac4a: f3bf 8f4f dsb sy
800ac4e: b662 cpsie i
800ac50: 623b str r3, [r7, #32]
800ac52: e7fe b.n 800ac52 <xTaskCreateStatic+0x2a>
configASSERT( pxTaskBuffer != NULL );
800ac54: 6bbb ldr r3, [r7, #56] ; 0x38
800ac56: 2b00 cmp r3, #0
800ac58: d10b bne.n 800ac72 <xTaskCreateStatic+0x4a>
800ac5a: f04f 0350 mov.w r3, #80 ; 0x50
800ac5e: b672 cpsid i
800ac60: f383 8811 msr BASEPRI, r3
800ac64: f3bf 8f6f isb sy
800ac68: f3bf 8f4f dsb sy
800ac6c: b662 cpsie i
800ac6e: 61fb str r3, [r7, #28]
800ac70: e7fe b.n 800ac70 <xTaskCreateStatic+0x48>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
800ac72: 2358 movs r3, #88 ; 0x58
800ac74: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800ac76: 693b ldr r3, [r7, #16]
800ac78: 2b58 cmp r3, #88 ; 0x58
800ac7a: d00b beq.n 800ac94 <xTaskCreateStatic+0x6c>
800ac7c: f04f 0350 mov.w r3, #80 ; 0x50
800ac80: b672 cpsid i
800ac82: f383 8811 msr BASEPRI, r3
800ac86: f3bf 8f6f isb sy
800ac8a: f3bf 8f4f dsb sy
800ac8e: b662 cpsie i
800ac90: 61bb str r3, [r7, #24]
800ac92: e7fe b.n 800ac92 <xTaskCreateStatic+0x6a>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800ac94: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800ac96: 6bbb ldr r3, [r7, #56] ; 0x38
800ac98: 2b00 cmp r3, #0
800ac9a: d01e beq.n 800acda <xTaskCreateStatic+0xb2>
800ac9c: 6b7b ldr r3, [r7, #52] ; 0x34
800ac9e: 2b00 cmp r3, #0
800aca0: d01b beq.n 800acda <xTaskCreateStatic+0xb2>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
800aca2: 6bbb ldr r3, [r7, #56] ; 0x38
800aca4: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800aca6: 6a7b ldr r3, [r7, #36] ; 0x24
800aca8: 6b7a ldr r2, [r7, #52] ; 0x34
800acaa: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
800acac: 6a7b ldr r3, [r7, #36] ; 0x24
800acae: 2202 movs r2, #2
800acb0: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800acb4: 2300 movs r3, #0
800acb6: 9303 str r3, [sp, #12]
800acb8: 6a7b ldr r3, [r7, #36] ; 0x24
800acba: 9302 str r3, [sp, #8]
800acbc: f107 0314 add.w r3, r7, #20
800acc0: 9301 str r3, [sp, #4]
800acc2: 6b3b ldr r3, [r7, #48] ; 0x30
800acc4: 9300 str r3, [sp, #0]
800acc6: 683b ldr r3, [r7, #0]
800acc8: 687a ldr r2, [r7, #4]
800acca: 68b9 ldr r1, [r7, #8]
800accc: 68f8 ldr r0, [r7, #12]
800acce: f000 f850 bl 800ad72 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800acd2: 6a78 ldr r0, [r7, #36] ; 0x24
800acd4: f000 f8e0 bl 800ae98 <prvAddNewTaskToReadyList>
800acd8: e001 b.n 800acde <xTaskCreateStatic+0xb6>
}
else
{
xReturn = NULL;
800acda: 2300 movs r3, #0
800acdc: 617b str r3, [r7, #20]
}
return xReturn;
800acde: 697b ldr r3, [r7, #20]
}
800ace0: 4618 mov r0, r3
800ace2: 3728 adds r7, #40 ; 0x28
800ace4: 46bd mov sp, r7
800ace6: bd80 pop {r7, pc}
0800ace8 <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
800ace8: b580 push {r7, lr}
800acea: b08c sub sp, #48 ; 0x30
800acec: af04 add r7, sp, #16
800acee: 60f8 str r0, [r7, #12]
800acf0: 60b9 str r1, [r7, #8]
800acf2: 603b str r3, [r7, #0]
800acf4: 4613 mov r3, r2
800acf6: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
800acf8: 88fb ldrh r3, [r7, #6]
800acfa: 009b lsls r3, r3, #2
800acfc: 4618 mov r0, r3
800acfe: f000 fd45 bl 800b78c <pvPortMalloc>
800ad02: 6178 str r0, [r7, #20]
if( pxStack != NULL )
800ad04: 697b ldr r3, [r7, #20]
800ad06: 2b00 cmp r3, #0
800ad08: d00e beq.n 800ad28 <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
800ad0a: 2058 movs r0, #88 ; 0x58
800ad0c: f000 fd3e bl 800b78c <pvPortMalloc>
800ad10: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
800ad12: 69fb ldr r3, [r7, #28]
800ad14: 2b00 cmp r3, #0
800ad16: d003 beq.n 800ad20 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
800ad18: 69fb ldr r3, [r7, #28]
800ad1a: 697a ldr r2, [r7, #20]
800ad1c: 631a str r2, [r3, #48] ; 0x30
800ad1e: e005 b.n 800ad2c <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
800ad20: 6978 ldr r0, [r7, #20]
800ad22: f000 fdff bl 800b924 <vPortFree>
800ad26: e001 b.n 800ad2c <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
800ad28: 2300 movs r3, #0
800ad2a: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
800ad2c: 69fb ldr r3, [r7, #28]
800ad2e: 2b00 cmp r3, #0
800ad30: d017 beq.n 800ad62 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
800ad32: 69fb ldr r3, [r7, #28]
800ad34: 2200 movs r2, #0
800ad36: f883 2055 strb.w r2, [r3, #85] ; 0x55
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
800ad3a: 88fa ldrh r2, [r7, #6]
800ad3c: 2300 movs r3, #0
800ad3e: 9303 str r3, [sp, #12]
800ad40: 69fb ldr r3, [r7, #28]
800ad42: 9302 str r3, [sp, #8]
800ad44: 6afb ldr r3, [r7, #44] ; 0x2c
800ad46: 9301 str r3, [sp, #4]
800ad48: 6abb ldr r3, [r7, #40] ; 0x28
800ad4a: 9300 str r3, [sp, #0]
800ad4c: 683b ldr r3, [r7, #0]
800ad4e: 68b9 ldr r1, [r7, #8]
800ad50: 68f8 ldr r0, [r7, #12]
800ad52: f000 f80e bl 800ad72 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800ad56: 69f8 ldr r0, [r7, #28]
800ad58: f000 f89e bl 800ae98 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
800ad5c: 2301 movs r3, #1
800ad5e: 61bb str r3, [r7, #24]
800ad60: e002 b.n 800ad68 <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
800ad62: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800ad66: 61bb str r3, [r7, #24]
}
return xReturn;
800ad68: 69bb ldr r3, [r7, #24]
}
800ad6a: 4618 mov r0, r3
800ad6c: 3720 adds r7, #32
800ad6e: 46bd mov sp, r7
800ad70: bd80 pop {r7, pc}
0800ad72 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
800ad72: b580 push {r7, lr}
800ad74: b088 sub sp, #32
800ad76: af00 add r7, sp, #0
800ad78: 60f8 str r0, [r7, #12]
800ad7a: 60b9 str r1, [r7, #8]
800ad7c: 607a str r2, [r7, #4]
800ad7e: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
800ad80: 6b3b ldr r3, [r7, #48] ; 0x30
800ad82: 6b18 ldr r0, [r3, #48] ; 0x30
800ad84: 687b ldr r3, [r7, #4]
800ad86: 009b lsls r3, r3, #2
800ad88: 461a mov r2, r3
800ad8a: 21a5 movs r1, #165 ; 0xa5
800ad8c: f000 ff17 bl 800bbbe <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
800ad90: 6b3b ldr r3, [r7, #48] ; 0x30
800ad92: 6b1a ldr r2, [r3, #48] ; 0x30
800ad94: 6879 ldr r1, [r7, #4]
800ad96: f06f 4340 mvn.w r3, #3221225472 ; 0xc0000000
800ad9a: 440b add r3, r1
800ad9c: 009b lsls r3, r3, #2
800ad9e: 4413 add r3, r2
800ada0: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
800ada2: 69bb ldr r3, [r7, #24]
800ada4: f023 0307 bic.w r3, r3, #7
800ada8: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
800adaa: 69bb ldr r3, [r7, #24]
800adac: f003 0307 and.w r3, r3, #7
800adb0: 2b00 cmp r3, #0
800adb2: d00b beq.n 800adcc <prvInitialiseNewTask+0x5a>
800adb4: f04f 0350 mov.w r3, #80 ; 0x50
800adb8: b672 cpsid i
800adba: f383 8811 msr BASEPRI, r3
800adbe: f3bf 8f6f isb sy
800adc2: f3bf 8f4f dsb sy
800adc6: b662 cpsie i
800adc8: 617b str r3, [r7, #20]
800adca: e7fe b.n 800adca <prvInitialiseNewTask+0x58>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
800adcc: 68bb ldr r3, [r7, #8]
800adce: 2b00 cmp r3, #0
800add0: d01f beq.n 800ae12 <prvInitialiseNewTask+0xa0>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800add2: 2300 movs r3, #0
800add4: 61fb str r3, [r7, #28]
800add6: e012 b.n 800adfe <prvInitialiseNewTask+0x8c>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
800add8: 68ba ldr r2, [r7, #8]
800adda: 69fb ldr r3, [r7, #28]
800addc: 4413 add r3, r2
800adde: 7819 ldrb r1, [r3, #0]
800ade0: 6b3a ldr r2, [r7, #48] ; 0x30
800ade2: 69fb ldr r3, [r7, #28]
800ade4: 4413 add r3, r2
800ade6: 3334 adds r3, #52 ; 0x34
800ade8: 460a mov r2, r1
800adea: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
800adec: 68ba ldr r2, [r7, #8]
800adee: 69fb ldr r3, [r7, #28]
800adf0: 4413 add r3, r2
800adf2: 781b ldrb r3, [r3, #0]
800adf4: 2b00 cmp r3, #0
800adf6: d006 beq.n 800ae06 <prvInitialiseNewTask+0x94>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
800adf8: 69fb ldr r3, [r7, #28]
800adfa: 3301 adds r3, #1
800adfc: 61fb str r3, [r7, #28]
800adfe: 69fb ldr r3, [r7, #28]
800ae00: 2b0f cmp r3, #15
800ae02: d9e9 bls.n 800add8 <prvInitialiseNewTask+0x66>
800ae04: e000 b.n 800ae08 <prvInitialiseNewTask+0x96>
{
break;
800ae06: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
800ae08: 6b3b ldr r3, [r7, #48] ; 0x30
800ae0a: 2200 movs r2, #0
800ae0c: f883 2043 strb.w r2, [r3, #67] ; 0x43
800ae10: e003 b.n 800ae1a <prvInitialiseNewTask+0xa8>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
800ae12: 6b3b ldr r3, [r7, #48] ; 0x30
800ae14: 2200 movs r2, #0
800ae16: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
800ae1a: 6abb ldr r3, [r7, #40] ; 0x28
800ae1c: 2b06 cmp r3, #6
800ae1e: d901 bls.n 800ae24 <prvInitialiseNewTask+0xb2>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
800ae20: 2306 movs r3, #6
800ae22: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
800ae24: 6b3b ldr r3, [r7, #48] ; 0x30
800ae26: 6aba ldr r2, [r7, #40] ; 0x28
800ae28: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
800ae2a: 6b3b ldr r3, [r7, #48] ; 0x30
800ae2c: 6aba ldr r2, [r7, #40] ; 0x28
800ae2e: 645a str r2, [r3, #68] ; 0x44
pxNewTCB->uxMutexesHeld = 0;
800ae30: 6b3b ldr r3, [r7, #48] ; 0x30
800ae32: 2200 movs r2, #0
800ae34: 649a str r2, [r3, #72] ; 0x48
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
800ae36: 6b3b ldr r3, [r7, #48] ; 0x30
800ae38: 3304 adds r3, #4
800ae3a: 4618 mov r0, r3
800ae3c: f7ff fe60 bl 800ab00 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
800ae40: 6b3b ldr r3, [r7, #48] ; 0x30
800ae42: 3318 adds r3, #24
800ae44: 4618 mov r0, r3
800ae46: f7ff fe5b bl 800ab00 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
800ae4a: 6b3b ldr r3, [r7, #48] ; 0x30
800ae4c: 6b3a ldr r2, [r7, #48] ; 0x30
800ae4e: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800ae50: 6abb ldr r3, [r7, #40] ; 0x28
800ae52: f1c3 0207 rsb r2, r3, #7
800ae56: 6b3b ldr r3, [r7, #48] ; 0x30
800ae58: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800ae5a: 6b3b ldr r3, [r7, #48] ; 0x30
800ae5c: 6b3a ldr r2, [r7, #48] ; 0x30
800ae5e: 625a str r2, [r3, #36] ; 0x24
}
#endif /* portCRITICAL_NESTING_IN_TCB */
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
{
pxNewTCB->pxTaskTag = NULL;
800ae60: 6b3b ldr r3, [r7, #48] ; 0x30
800ae62: 2200 movs r2, #0
800ae64: 64da str r2, [r3, #76] ; 0x4c
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
800ae66: 6b3b ldr r3, [r7, #48] ; 0x30
800ae68: 2200 movs r2, #0
800ae6a: 651a str r2, [r3, #80] ; 0x50
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
800ae6c: 6b3b ldr r3, [r7, #48] ; 0x30
800ae6e: 2200 movs r2, #0
800ae70: f883 2054 strb.w r2, [r3, #84] ; 0x54
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
800ae74: 683a ldr r2, [r7, #0]
800ae76: 68f9 ldr r1, [r7, #12]
800ae78: 69b8 ldr r0, [r7, #24]
800ae7a: f000 fb5b bl 800b534 <pxPortInitialiseStack>
800ae7e: 4602 mov r2, r0
800ae80: 6b3b ldr r3, [r7, #48] ; 0x30
800ae82: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
800ae84: 6afb ldr r3, [r7, #44] ; 0x2c
800ae86: 2b00 cmp r3, #0
800ae88: d002 beq.n 800ae90 <prvInitialiseNewTask+0x11e>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
800ae8a: 6afb ldr r3, [r7, #44] ; 0x2c
800ae8c: 6b3a ldr r2, [r7, #48] ; 0x30
800ae8e: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800ae90: bf00 nop
800ae92: 3720 adds r7, #32
800ae94: 46bd mov sp, r7
800ae96: bd80 pop {r7, pc}
0800ae98 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
800ae98: b580 push {r7, lr}
800ae9a: b082 sub sp, #8
800ae9c: af00 add r7, sp, #0
800ae9e: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
800aea0: f000 fbc2 bl 800b628 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
800aea4: 4b2a ldr r3, [pc, #168] ; (800af50 <prvAddNewTaskToReadyList+0xb8>)
800aea6: 681b ldr r3, [r3, #0]
800aea8: 3301 adds r3, #1
800aeaa: 4a29 ldr r2, [pc, #164] ; (800af50 <prvAddNewTaskToReadyList+0xb8>)
800aeac: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
800aeae: 4b29 ldr r3, [pc, #164] ; (800af54 <prvAddNewTaskToReadyList+0xbc>)
800aeb0: 681b ldr r3, [r3, #0]
800aeb2: 2b00 cmp r3, #0
800aeb4: d109 bne.n 800aeca <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
800aeb6: 4a27 ldr r2, [pc, #156] ; (800af54 <prvAddNewTaskToReadyList+0xbc>)
800aeb8: 687b ldr r3, [r7, #4]
800aeba: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
800aebc: 4b24 ldr r3, [pc, #144] ; (800af50 <prvAddNewTaskToReadyList+0xb8>)
800aebe: 681b ldr r3, [r3, #0]
800aec0: 2b01 cmp r3, #1
800aec2: d110 bne.n 800aee6 <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
800aec4: f000 fa70 bl 800b3a8 <prvInitialiseTaskLists>
800aec8: e00d b.n 800aee6 <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
800aeca: 4b23 ldr r3, [pc, #140] ; (800af58 <prvAddNewTaskToReadyList+0xc0>)
800aecc: 681b ldr r3, [r3, #0]
800aece: 2b00 cmp r3, #0
800aed0: d109 bne.n 800aee6 <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
800aed2: 4b20 ldr r3, [pc, #128] ; (800af54 <prvAddNewTaskToReadyList+0xbc>)
800aed4: 681b ldr r3, [r3, #0]
800aed6: 6ada ldr r2, [r3, #44] ; 0x2c
800aed8: 687b ldr r3, [r7, #4]
800aeda: 6adb ldr r3, [r3, #44] ; 0x2c
800aedc: 429a cmp r2, r3
800aede: d802 bhi.n 800aee6 <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
800aee0: 4a1c ldr r2, [pc, #112] ; (800af54 <prvAddNewTaskToReadyList+0xbc>)
800aee2: 687b ldr r3, [r7, #4]
800aee4: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
800aee6: 4b1d ldr r3, [pc, #116] ; (800af5c <prvAddNewTaskToReadyList+0xc4>)
800aee8: 681b ldr r3, [r3, #0]
800aeea: 3301 adds r3, #1
800aeec: 4a1b ldr r2, [pc, #108] ; (800af5c <prvAddNewTaskToReadyList+0xc4>)
800aeee: 6013 str r3, [r2, #0]
pxNewTCB->uxTCBNumber = uxTaskNumber;
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
800aef0: 687b ldr r3, [r7, #4]
800aef2: 6adb ldr r3, [r3, #44] ; 0x2c
800aef4: 2201 movs r2, #1
800aef6: 409a lsls r2, r3
800aef8: 4b19 ldr r3, [pc, #100] ; (800af60 <prvAddNewTaskToReadyList+0xc8>)
800aefa: 681b ldr r3, [r3, #0]
800aefc: 4313 orrs r3, r2
800aefe: 4a18 ldr r2, [pc, #96] ; (800af60 <prvAddNewTaskToReadyList+0xc8>)
800af00: 6013 str r3, [r2, #0]
800af02: 687b ldr r3, [r7, #4]
800af04: 6ada ldr r2, [r3, #44] ; 0x2c
800af06: 4613 mov r3, r2
800af08: 009b lsls r3, r3, #2
800af0a: 4413 add r3, r2
800af0c: 009b lsls r3, r3, #2
800af0e: 4a15 ldr r2, [pc, #84] ; (800af64 <prvAddNewTaskToReadyList+0xcc>)
800af10: 441a add r2, r3
800af12: 687b ldr r3, [r7, #4]
800af14: 3304 adds r3, #4
800af16: 4619 mov r1, r3
800af18: 4610 mov r0, r2
800af1a: f7ff fdfe bl 800ab1a <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
800af1e: f000 fbb5 bl 800b68c <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
800af22: 4b0d ldr r3, [pc, #52] ; (800af58 <prvAddNewTaskToReadyList+0xc0>)
800af24: 681b ldr r3, [r3, #0]
800af26: 2b00 cmp r3, #0
800af28: d00e beq.n 800af48 <prvAddNewTaskToReadyList+0xb0>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
800af2a: 4b0a ldr r3, [pc, #40] ; (800af54 <prvAddNewTaskToReadyList+0xbc>)
800af2c: 681b ldr r3, [r3, #0]
800af2e: 6ada ldr r2, [r3, #44] ; 0x2c
800af30: 687b ldr r3, [r7, #4]
800af32: 6adb ldr r3, [r3, #44] ; 0x2c
800af34: 429a cmp r2, r3
800af36: d207 bcs.n 800af48 <prvAddNewTaskToReadyList+0xb0>
{
taskYIELD_IF_USING_PREEMPTION();
800af38: 4b0b ldr r3, [pc, #44] ; (800af68 <prvAddNewTaskToReadyList+0xd0>)
800af3a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800af3e: 601a str r2, [r3, #0]
800af40: f3bf 8f4f dsb sy
800af44: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800af48: bf00 nop
800af4a: 3708 adds r7, #8
800af4c: 46bd mov sp, r7
800af4e: bd80 pop {r7, pc}
800af50: 200003f0 .word 0x200003f0
800af54: 200002f4 .word 0x200002f4
800af58: 200003fc .word 0x200003fc
800af5c: 2000040c .word 0x2000040c
800af60: 200003f8 .word 0x200003f8
800af64: 200002f8 .word 0x200002f8
800af68: e000ed04 .word 0xe000ed04
0800af6c <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
800af6c: b580 push {r7, lr}
800af6e: b084 sub sp, #16
800af70: af00 add r7, sp, #0
800af72: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
800af74: 2300 movs r3, #0
800af76: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
800af78: 687b ldr r3, [r7, #4]
800af7a: 2b00 cmp r3, #0
800af7c: d018 beq.n 800afb0 <vTaskDelay+0x44>
{
configASSERT( uxSchedulerSuspended == 0 );
800af7e: 4b14 ldr r3, [pc, #80] ; (800afd0 <vTaskDelay+0x64>)
800af80: 681b ldr r3, [r3, #0]
800af82: 2b00 cmp r3, #0
800af84: d00b beq.n 800af9e <vTaskDelay+0x32>
800af86: f04f 0350 mov.w r3, #80 ; 0x50
800af8a: b672 cpsid i
800af8c: f383 8811 msr BASEPRI, r3
800af90: f3bf 8f6f isb sy
800af94: f3bf 8f4f dsb sy
800af98: b662 cpsie i
800af9a: 60bb str r3, [r7, #8]
800af9c: e7fe b.n 800af9c <vTaskDelay+0x30>
vTaskSuspendAll();
800af9e: f000 f81b bl 800afd8 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
800afa2: 2100 movs r1, #0
800afa4: 6878 ldr r0, [r7, #4]
800afa6: f000 fa5f bl 800b468 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
800afaa: f000 f823 bl 800aff4 <xTaskResumeAll>
800afae: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
800afb0: 68fb ldr r3, [r7, #12]
800afb2: 2b00 cmp r3, #0
800afb4: d107 bne.n 800afc6 <vTaskDelay+0x5a>
{
portYIELD_WITHIN_API();
800afb6: 4b07 ldr r3, [pc, #28] ; (800afd4 <vTaskDelay+0x68>)
800afb8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800afbc: 601a str r2, [r3, #0]
800afbe: f3bf 8f4f dsb sy
800afc2: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800afc6: bf00 nop
800afc8: 3710 adds r7, #16
800afca: 46bd mov sp, r7
800afcc: bd80 pop {r7, pc}
800afce: bf00 nop
800afd0: 20000414 .word 0x20000414
800afd4: e000ed04 .word 0xe000ed04
0800afd8 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
800afd8: b480 push {r7}
800afda: af00 add r7, sp, #0
/* A critical section is not required as the variable is of type
BaseType_t. Please read Richard Barry's reply in the following link to a
post in the FreeRTOS support forum before reporting this as a bug! -
http://goo.gl/wu4acr */
++uxSchedulerSuspended;
800afdc: 4b04 ldr r3, [pc, #16] ; (800aff0 <vTaskSuspendAll+0x18>)
800afde: 681b ldr r3, [r3, #0]
800afe0: 3301 adds r3, #1
800afe2: 4a03 ldr r2, [pc, #12] ; (800aff0 <vTaskSuspendAll+0x18>)
800afe4: 6013 str r3, [r2, #0]
portMEMORY_BARRIER();
}
800afe6: bf00 nop
800afe8: 46bd mov sp, r7
800afea: f85d 7b04 ldr.w r7, [sp], #4
800afee: 4770 bx lr
800aff0: 20000414 .word 0x20000414
0800aff4 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
800aff4: b580 push {r7, lr}
800aff6: b084 sub sp, #16
800aff8: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
800affa: 2300 movs r3, #0
800affc: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
800affe: 2300 movs r3, #0
800b000: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
800b002: 4b42 ldr r3, [pc, #264] ; (800b10c <xTaskResumeAll+0x118>)
800b004: 681b ldr r3, [r3, #0]
800b006: 2b00 cmp r3, #0
800b008: d10b bne.n 800b022 <xTaskResumeAll+0x2e>
800b00a: f04f 0350 mov.w r3, #80 ; 0x50
800b00e: b672 cpsid i
800b010: f383 8811 msr BASEPRI, r3
800b014: f3bf 8f6f isb sy
800b018: f3bf 8f4f dsb sy
800b01c: b662 cpsie i
800b01e: 603b str r3, [r7, #0]
800b020: e7fe b.n 800b020 <xTaskResumeAll+0x2c>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
800b022: f000 fb01 bl 800b628 <vPortEnterCritical>
{
--uxSchedulerSuspended;
800b026: 4b39 ldr r3, [pc, #228] ; (800b10c <xTaskResumeAll+0x118>)
800b028: 681b ldr r3, [r3, #0]
800b02a: 3b01 subs r3, #1
800b02c: 4a37 ldr r2, [pc, #220] ; (800b10c <xTaskResumeAll+0x118>)
800b02e: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800b030: 4b36 ldr r3, [pc, #216] ; (800b10c <xTaskResumeAll+0x118>)
800b032: 681b ldr r3, [r3, #0]
800b034: 2b00 cmp r3, #0
800b036: d161 bne.n 800b0fc <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
800b038: 4b35 ldr r3, [pc, #212] ; (800b110 <xTaskResumeAll+0x11c>)
800b03a: 681b ldr r3, [r3, #0]
800b03c: 2b00 cmp r3, #0
800b03e: d05d beq.n 800b0fc <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800b040: e02e b.n 800b0a0 <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800b042: 4b34 ldr r3, [pc, #208] ; (800b114 <xTaskResumeAll+0x120>)
800b044: 68db ldr r3, [r3, #12]
800b046: 68db ldr r3, [r3, #12]
800b048: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800b04a: 68fb ldr r3, [r7, #12]
800b04c: 3318 adds r3, #24
800b04e: 4618 mov r0, r3
800b050: f7ff fdc0 bl 800abd4 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800b054: 68fb ldr r3, [r7, #12]
800b056: 3304 adds r3, #4
800b058: 4618 mov r0, r3
800b05a: f7ff fdbb bl 800abd4 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
800b05e: 68fb ldr r3, [r7, #12]
800b060: 6adb ldr r3, [r3, #44] ; 0x2c
800b062: 2201 movs r2, #1
800b064: 409a lsls r2, r3
800b066: 4b2c ldr r3, [pc, #176] ; (800b118 <xTaskResumeAll+0x124>)
800b068: 681b ldr r3, [r3, #0]
800b06a: 4313 orrs r3, r2
800b06c: 4a2a ldr r2, [pc, #168] ; (800b118 <xTaskResumeAll+0x124>)
800b06e: 6013 str r3, [r2, #0]
800b070: 68fb ldr r3, [r7, #12]
800b072: 6ada ldr r2, [r3, #44] ; 0x2c
800b074: 4613 mov r3, r2
800b076: 009b lsls r3, r3, #2
800b078: 4413 add r3, r2
800b07a: 009b lsls r3, r3, #2
800b07c: 4a27 ldr r2, [pc, #156] ; (800b11c <xTaskResumeAll+0x128>)
800b07e: 441a add r2, r3
800b080: 68fb ldr r3, [r7, #12]
800b082: 3304 adds r3, #4
800b084: 4619 mov r1, r3
800b086: 4610 mov r0, r2
800b088: f7ff fd47 bl 800ab1a <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800b08c: 68fb ldr r3, [r7, #12]
800b08e: 6ada ldr r2, [r3, #44] ; 0x2c
800b090: 4b23 ldr r3, [pc, #140] ; (800b120 <xTaskResumeAll+0x12c>)
800b092: 681b ldr r3, [r3, #0]
800b094: 6adb ldr r3, [r3, #44] ; 0x2c
800b096: 429a cmp r2, r3
800b098: d302 bcc.n 800b0a0 <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
800b09a: 4b22 ldr r3, [pc, #136] ; (800b124 <xTaskResumeAll+0x130>)
800b09c: 2201 movs r2, #1
800b09e: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
800b0a0: 4b1c ldr r3, [pc, #112] ; (800b114 <xTaskResumeAll+0x120>)
800b0a2: 681b ldr r3, [r3, #0]
800b0a4: 2b00 cmp r3, #0
800b0a6: d1cc bne.n 800b042 <xTaskResumeAll+0x4e>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
800b0a8: 68fb ldr r3, [r7, #12]
800b0aa: 2b00 cmp r3, #0
800b0ac: d001 beq.n 800b0b2 <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
800b0ae: f000 f9bb bl 800b428 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
800b0b2: 4b1d ldr r3, [pc, #116] ; (800b128 <xTaskResumeAll+0x134>)
800b0b4: 681b ldr r3, [r3, #0]
800b0b6: 607b str r3, [r7, #4]
if( uxPendedCounts > ( UBaseType_t ) 0U )
800b0b8: 687b ldr r3, [r7, #4]
800b0ba: 2b00 cmp r3, #0
800b0bc: d010 beq.n 800b0e0 <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
800b0be: f000 f837 bl 800b130 <xTaskIncrementTick>
800b0c2: 4603 mov r3, r0
800b0c4: 2b00 cmp r3, #0
800b0c6: d002 beq.n 800b0ce <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
800b0c8: 4b16 ldr r3, [pc, #88] ; (800b124 <xTaskResumeAll+0x130>)
800b0ca: 2201 movs r2, #1
800b0cc: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--uxPendedCounts;
800b0ce: 687b ldr r3, [r7, #4]
800b0d0: 3b01 subs r3, #1
800b0d2: 607b str r3, [r7, #4]
} while( uxPendedCounts > ( UBaseType_t ) 0U );
800b0d4: 687b ldr r3, [r7, #4]
800b0d6: 2b00 cmp r3, #0
800b0d8: d1f1 bne.n 800b0be <xTaskResumeAll+0xca>
uxPendedTicks = 0;
800b0da: 4b13 ldr r3, [pc, #76] ; (800b128 <xTaskResumeAll+0x134>)
800b0dc: 2200 movs r2, #0
800b0de: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
800b0e0: 4b10 ldr r3, [pc, #64] ; (800b124 <xTaskResumeAll+0x130>)
800b0e2: 681b ldr r3, [r3, #0]
800b0e4: 2b00 cmp r3, #0
800b0e6: d009 beq.n 800b0fc <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
800b0e8: 2301 movs r3, #1
800b0ea: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
800b0ec: 4b0f ldr r3, [pc, #60] ; (800b12c <xTaskResumeAll+0x138>)
800b0ee: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800b0f2: 601a str r2, [r3, #0]
800b0f4: f3bf 8f4f dsb sy
800b0f8: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
800b0fc: f000 fac6 bl 800b68c <vPortExitCritical>
return xAlreadyYielded;
800b100: 68bb ldr r3, [r7, #8]
}
800b102: 4618 mov r0, r3
800b104: 3710 adds r7, #16
800b106: 46bd mov sp, r7
800b108: bd80 pop {r7, pc}
800b10a: bf00 nop
800b10c: 20000414 .word 0x20000414
800b110: 200003f0 .word 0x200003f0
800b114: 200003b4 .word 0x200003b4
800b118: 200003f8 .word 0x200003f8
800b11c: 200002f8 .word 0x200002f8
800b120: 200002f4 .word 0x200002f4
800b124: 20000404 .word 0x20000404
800b128: 20000400 .word 0x20000400
800b12c: e000ed04 .word 0xe000ed04
0800b130 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
800b130: b580 push {r7, lr}
800b132: b086 sub sp, #24
800b134: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
800b136: 2300 movs r3, #0
800b138: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800b13a: 4b4f ldr r3, [pc, #316] ; (800b278 <xTaskIncrementTick+0x148>)
800b13c: 681b ldr r3, [r3, #0]
800b13e: 2b00 cmp r3, #0
800b140: f040 8089 bne.w 800b256 <xTaskIncrementTick+0x126>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
800b144: 4b4d ldr r3, [pc, #308] ; (800b27c <xTaskIncrementTick+0x14c>)
800b146: 681b ldr r3, [r3, #0]
800b148: 3301 adds r3, #1
800b14a: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
800b14c: 4a4b ldr r2, [pc, #300] ; (800b27c <xTaskIncrementTick+0x14c>)
800b14e: 693b ldr r3, [r7, #16]
800b150: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
800b152: 693b ldr r3, [r7, #16]
800b154: 2b00 cmp r3, #0
800b156: d121 bne.n 800b19c <xTaskIncrementTick+0x6c>
{
taskSWITCH_DELAYED_LISTS();
800b158: 4b49 ldr r3, [pc, #292] ; (800b280 <xTaskIncrementTick+0x150>)
800b15a: 681b ldr r3, [r3, #0]
800b15c: 681b ldr r3, [r3, #0]
800b15e: 2b00 cmp r3, #0
800b160: d00b beq.n 800b17a <xTaskIncrementTick+0x4a>
800b162: f04f 0350 mov.w r3, #80 ; 0x50
800b166: b672 cpsid i
800b168: f383 8811 msr BASEPRI, r3
800b16c: f3bf 8f6f isb sy
800b170: f3bf 8f4f dsb sy
800b174: b662 cpsie i
800b176: 603b str r3, [r7, #0]
800b178: e7fe b.n 800b178 <xTaskIncrementTick+0x48>
800b17a: 4b41 ldr r3, [pc, #260] ; (800b280 <xTaskIncrementTick+0x150>)
800b17c: 681b ldr r3, [r3, #0]
800b17e: 60fb str r3, [r7, #12]
800b180: 4b40 ldr r3, [pc, #256] ; (800b284 <xTaskIncrementTick+0x154>)
800b182: 681b ldr r3, [r3, #0]
800b184: 4a3e ldr r2, [pc, #248] ; (800b280 <xTaskIncrementTick+0x150>)
800b186: 6013 str r3, [r2, #0]
800b188: 4a3e ldr r2, [pc, #248] ; (800b284 <xTaskIncrementTick+0x154>)
800b18a: 68fb ldr r3, [r7, #12]
800b18c: 6013 str r3, [r2, #0]
800b18e: 4b3e ldr r3, [pc, #248] ; (800b288 <xTaskIncrementTick+0x158>)
800b190: 681b ldr r3, [r3, #0]
800b192: 3301 adds r3, #1
800b194: 4a3c ldr r2, [pc, #240] ; (800b288 <xTaskIncrementTick+0x158>)
800b196: 6013 str r3, [r2, #0]
800b198: f000 f946 bl 800b428 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
800b19c: 4b3b ldr r3, [pc, #236] ; (800b28c <xTaskIncrementTick+0x15c>)
800b19e: 681b ldr r3, [r3, #0]
800b1a0: 693a ldr r2, [r7, #16]
800b1a2: 429a cmp r2, r3
800b1a4: d348 bcc.n 800b238 <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800b1a6: 4b36 ldr r3, [pc, #216] ; (800b280 <xTaskIncrementTick+0x150>)
800b1a8: 681b ldr r3, [r3, #0]
800b1aa: 681b ldr r3, [r3, #0]
800b1ac: 2b00 cmp r3, #0
800b1ae: d104 bne.n 800b1ba <xTaskIncrementTick+0x8a>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
800b1b0: 4b36 ldr r3, [pc, #216] ; (800b28c <xTaskIncrementTick+0x15c>)
800b1b2: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800b1b6: 601a str r2, [r3, #0]
break;
800b1b8: e03e b.n 800b238 <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800b1ba: 4b31 ldr r3, [pc, #196] ; (800b280 <xTaskIncrementTick+0x150>)
800b1bc: 681b ldr r3, [r3, #0]
800b1be: 68db ldr r3, [r3, #12]
800b1c0: 68db ldr r3, [r3, #12]
800b1c2: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
800b1c4: 68bb ldr r3, [r7, #8]
800b1c6: 685b ldr r3, [r3, #4]
800b1c8: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
800b1ca: 693a ldr r2, [r7, #16]
800b1cc: 687b ldr r3, [r7, #4]
800b1ce: 429a cmp r2, r3
800b1d0: d203 bcs.n 800b1da <xTaskIncrementTick+0xaa>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
800b1d2: 4a2e ldr r2, [pc, #184] ; (800b28c <xTaskIncrementTick+0x15c>)
800b1d4: 687b ldr r3, [r7, #4]
800b1d6: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
800b1d8: e02e b.n 800b238 <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
800b1da: 68bb ldr r3, [r7, #8]
800b1dc: 3304 adds r3, #4
800b1de: 4618 mov r0, r3
800b1e0: f7ff fcf8 bl 800abd4 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
800b1e4: 68bb ldr r3, [r7, #8]
800b1e6: 6a9b ldr r3, [r3, #40] ; 0x28
800b1e8: 2b00 cmp r3, #0
800b1ea: d004 beq.n 800b1f6 <xTaskIncrementTick+0xc6>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800b1ec: 68bb ldr r3, [r7, #8]
800b1ee: 3318 adds r3, #24
800b1f0: 4618 mov r0, r3
800b1f2: f7ff fcef bl 800abd4 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800b1f6: 68bb ldr r3, [r7, #8]
800b1f8: 6adb ldr r3, [r3, #44] ; 0x2c
800b1fa: 2201 movs r2, #1
800b1fc: 409a lsls r2, r3
800b1fe: 4b24 ldr r3, [pc, #144] ; (800b290 <xTaskIncrementTick+0x160>)
800b200: 681b ldr r3, [r3, #0]
800b202: 4313 orrs r3, r2
800b204: 4a22 ldr r2, [pc, #136] ; (800b290 <xTaskIncrementTick+0x160>)
800b206: 6013 str r3, [r2, #0]
800b208: 68bb ldr r3, [r7, #8]
800b20a: 6ada ldr r2, [r3, #44] ; 0x2c
800b20c: 4613 mov r3, r2
800b20e: 009b lsls r3, r3, #2
800b210: 4413 add r3, r2
800b212: 009b lsls r3, r3, #2
800b214: 4a1f ldr r2, [pc, #124] ; (800b294 <xTaskIncrementTick+0x164>)
800b216: 441a add r2, r3
800b218: 68bb ldr r3, [r7, #8]
800b21a: 3304 adds r3, #4
800b21c: 4619 mov r1, r3
800b21e: 4610 mov r0, r2
800b220: f7ff fc7b bl 800ab1a <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
800b224: 68bb ldr r3, [r7, #8]
800b226: 6ada ldr r2, [r3, #44] ; 0x2c
800b228: 4b1b ldr r3, [pc, #108] ; (800b298 <xTaskIncrementTick+0x168>)
800b22a: 681b ldr r3, [r3, #0]
800b22c: 6adb ldr r3, [r3, #44] ; 0x2c
800b22e: 429a cmp r2, r3
800b230: d3b9 bcc.n 800b1a6 <xTaskIncrementTick+0x76>
{
xSwitchRequired = pdTRUE;
800b232: 2301 movs r3, #1
800b234: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800b236: e7b6 b.n 800b1a6 <xTaskIncrementTick+0x76>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800b238: 4b17 ldr r3, [pc, #92] ; (800b298 <xTaskIncrementTick+0x168>)
800b23a: 681b ldr r3, [r3, #0]
800b23c: 6ada ldr r2, [r3, #44] ; 0x2c
800b23e: 4915 ldr r1, [pc, #84] ; (800b294 <xTaskIncrementTick+0x164>)
800b240: 4613 mov r3, r2
800b242: 009b lsls r3, r3, #2
800b244: 4413 add r3, r2
800b246: 009b lsls r3, r3, #2
800b248: 440b add r3, r1
800b24a: 681b ldr r3, [r3, #0]
800b24c: 2b01 cmp r3, #1
800b24e: d907 bls.n 800b260 <xTaskIncrementTick+0x130>
{
xSwitchRequired = pdTRUE;
800b250: 2301 movs r3, #1
800b252: 617b str r3, [r7, #20]
800b254: e004 b.n 800b260 <xTaskIncrementTick+0x130>
}
#endif /* configUSE_TICK_HOOK */
}
else
{
++uxPendedTicks;
800b256: 4b11 ldr r3, [pc, #68] ; (800b29c <xTaskIncrementTick+0x16c>)
800b258: 681b ldr r3, [r3, #0]
800b25a: 3301 adds r3, #1
800b25c: 4a0f ldr r2, [pc, #60] ; (800b29c <xTaskIncrementTick+0x16c>)
800b25e: 6013 str r3, [r2, #0]
#endif
}
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
800b260: 4b0f ldr r3, [pc, #60] ; (800b2a0 <xTaskIncrementTick+0x170>)
800b262: 681b ldr r3, [r3, #0]
800b264: 2b00 cmp r3, #0
800b266: d001 beq.n 800b26c <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
800b268: 2301 movs r3, #1
800b26a: 617b str r3, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_PREEMPTION */
return xSwitchRequired;
800b26c: 697b ldr r3, [r7, #20]
}
800b26e: 4618 mov r0, r3
800b270: 3718 adds r7, #24
800b272: 46bd mov sp, r7
800b274: bd80 pop {r7, pc}
800b276: bf00 nop
800b278: 20000414 .word 0x20000414
800b27c: 200003f4 .word 0x200003f4
800b280: 200003ac .word 0x200003ac
800b284: 200003b0 .word 0x200003b0
800b288: 20000408 .word 0x20000408
800b28c: 20000410 .word 0x20000410
800b290: 200003f8 .word 0x200003f8
800b294: 200002f8 .word 0x200002f8
800b298: 200002f4 .word 0x200002f4
800b29c: 20000400 .word 0x20000400
800b2a0: 20000404 .word 0x20000404
0800b2a4 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
800b2a4: b580 push {r7, lr}
800b2a6: b088 sub sp, #32
800b2a8: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
800b2aa: 4b3a ldr r3, [pc, #232] ; (800b394 <vTaskSwitchContext+0xf0>)
800b2ac: 681b ldr r3, [r3, #0]
800b2ae: 2b00 cmp r3, #0
800b2b0: d003 beq.n 800b2ba <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
800b2b2: 4b39 ldr r3, [pc, #228] ; (800b398 <vTaskSwitchContext+0xf4>)
800b2b4: 2201 movs r2, #1
800b2b6: 601a str r2, [r3, #0]
structure specific to this task. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
800b2b8: e067 b.n 800b38a <vTaskSwitchContext+0xe6>
xYieldPending = pdFALSE;
800b2ba: 4b37 ldr r3, [pc, #220] ; (800b398 <vTaskSwitchContext+0xf4>)
800b2bc: 2200 movs r2, #0
800b2be: 601a str r2, [r3, #0]
taskCHECK_FOR_STACK_OVERFLOW();
800b2c0: 4b36 ldr r3, [pc, #216] ; (800b39c <vTaskSwitchContext+0xf8>)
800b2c2: 681b ldr r3, [r3, #0]
800b2c4: 6b1b ldr r3, [r3, #48] ; 0x30
800b2c6: 61fb str r3, [r7, #28]
800b2c8: f04f 33a5 mov.w r3, #2779096485 ; 0xa5a5a5a5
800b2cc: 61bb str r3, [r7, #24]
800b2ce: 69fb ldr r3, [r7, #28]
800b2d0: 681b ldr r3, [r3, #0]
800b2d2: 69ba ldr r2, [r7, #24]
800b2d4: 429a cmp r2, r3
800b2d6: d111 bne.n 800b2fc <vTaskSwitchContext+0x58>
800b2d8: 69fb ldr r3, [r7, #28]
800b2da: 3304 adds r3, #4
800b2dc: 681b ldr r3, [r3, #0]
800b2de: 69ba ldr r2, [r7, #24]
800b2e0: 429a cmp r2, r3
800b2e2: d10b bne.n 800b2fc <vTaskSwitchContext+0x58>
800b2e4: 69fb ldr r3, [r7, #28]
800b2e6: 3308 adds r3, #8
800b2e8: 681b ldr r3, [r3, #0]
800b2ea: 69ba ldr r2, [r7, #24]
800b2ec: 429a cmp r2, r3
800b2ee: d105 bne.n 800b2fc <vTaskSwitchContext+0x58>
800b2f0: 69fb ldr r3, [r7, #28]
800b2f2: 330c adds r3, #12
800b2f4: 681b ldr r3, [r3, #0]
800b2f6: 69ba ldr r2, [r7, #24]
800b2f8: 429a cmp r2, r3
800b2fa: d008 beq.n 800b30e <vTaskSwitchContext+0x6a>
800b2fc: 4b27 ldr r3, [pc, #156] ; (800b39c <vTaskSwitchContext+0xf8>)
800b2fe: 681a ldr r2, [r3, #0]
800b300: 4b26 ldr r3, [pc, #152] ; (800b39c <vTaskSwitchContext+0xf8>)
800b302: 681b ldr r3, [r3, #0]
800b304: 3334 adds r3, #52 ; 0x34
800b306: 4619 mov r1, r3
800b308: 4610 mov r0, r2
800b30a: f7f5 f951 bl 80005b0 <vApplicationStackOverflowHook>
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800b30e: 4b24 ldr r3, [pc, #144] ; (800b3a0 <vTaskSwitchContext+0xfc>)
800b310: 681b ldr r3, [r3, #0]
800b312: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
800b314: 68fb ldr r3, [r7, #12]
800b316: fab3 f383 clz r3, r3
800b31a: 72fb strb r3, [r7, #11]
return ucReturn;
800b31c: 7afb ldrb r3, [r7, #11]
800b31e: f1c3 031f rsb r3, r3, #31
800b322: 617b str r3, [r7, #20]
800b324: 491f ldr r1, [pc, #124] ; (800b3a4 <vTaskSwitchContext+0x100>)
800b326: 697a ldr r2, [r7, #20]
800b328: 4613 mov r3, r2
800b32a: 009b lsls r3, r3, #2
800b32c: 4413 add r3, r2
800b32e: 009b lsls r3, r3, #2
800b330: 440b add r3, r1
800b332: 681b ldr r3, [r3, #0]
800b334: 2b00 cmp r3, #0
800b336: d10b bne.n 800b350 <vTaskSwitchContext+0xac>
__asm volatile
800b338: f04f 0350 mov.w r3, #80 ; 0x50
800b33c: b672 cpsid i
800b33e: f383 8811 msr BASEPRI, r3
800b342: f3bf 8f6f isb sy
800b346: f3bf 8f4f dsb sy
800b34a: b662 cpsie i
800b34c: 607b str r3, [r7, #4]
800b34e: e7fe b.n 800b34e <vTaskSwitchContext+0xaa>
800b350: 697a ldr r2, [r7, #20]
800b352: 4613 mov r3, r2
800b354: 009b lsls r3, r3, #2
800b356: 4413 add r3, r2
800b358: 009b lsls r3, r3, #2
800b35a: 4a12 ldr r2, [pc, #72] ; (800b3a4 <vTaskSwitchContext+0x100>)
800b35c: 4413 add r3, r2
800b35e: 613b str r3, [r7, #16]
800b360: 693b ldr r3, [r7, #16]
800b362: 685b ldr r3, [r3, #4]
800b364: 685a ldr r2, [r3, #4]
800b366: 693b ldr r3, [r7, #16]
800b368: 605a str r2, [r3, #4]
800b36a: 693b ldr r3, [r7, #16]
800b36c: 685a ldr r2, [r3, #4]
800b36e: 693b ldr r3, [r7, #16]
800b370: 3308 adds r3, #8
800b372: 429a cmp r2, r3
800b374: d104 bne.n 800b380 <vTaskSwitchContext+0xdc>
800b376: 693b ldr r3, [r7, #16]
800b378: 685b ldr r3, [r3, #4]
800b37a: 685a ldr r2, [r3, #4]
800b37c: 693b ldr r3, [r7, #16]
800b37e: 605a str r2, [r3, #4]
800b380: 693b ldr r3, [r7, #16]
800b382: 685b ldr r3, [r3, #4]
800b384: 68db ldr r3, [r3, #12]
800b386: 4a05 ldr r2, [pc, #20] ; (800b39c <vTaskSwitchContext+0xf8>)
800b388: 6013 str r3, [r2, #0]
}
800b38a: bf00 nop
800b38c: 3720 adds r7, #32
800b38e: 46bd mov sp, r7
800b390: bd80 pop {r7, pc}
800b392: bf00 nop
800b394: 20000414 .word 0x20000414
800b398: 20000404 .word 0x20000404
800b39c: 200002f4 .word 0x200002f4
800b3a0: 200003f8 .word 0x200003f8
800b3a4: 200002f8 .word 0x200002f8
0800b3a8 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800b3a8: b580 push {r7, lr}
800b3aa: b082 sub sp, #8
800b3ac: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800b3ae: 2300 movs r3, #0
800b3b0: 607b str r3, [r7, #4]
800b3b2: e00c b.n 800b3ce <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
800b3b4: 687a ldr r2, [r7, #4]
800b3b6: 4613 mov r3, r2
800b3b8: 009b lsls r3, r3, #2
800b3ba: 4413 add r3, r2
800b3bc: 009b lsls r3, r3, #2
800b3be: 4a12 ldr r2, [pc, #72] ; (800b408 <prvInitialiseTaskLists+0x60>)
800b3c0: 4413 add r3, r2
800b3c2: 4618 mov r0, r3
800b3c4: f7ff fb7c bl 800aac0 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800b3c8: 687b ldr r3, [r7, #4]
800b3ca: 3301 adds r3, #1
800b3cc: 607b str r3, [r7, #4]
800b3ce: 687b ldr r3, [r7, #4]
800b3d0: 2b06 cmp r3, #6
800b3d2: d9ef bls.n 800b3b4 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
800b3d4: 480d ldr r0, [pc, #52] ; (800b40c <prvInitialiseTaskLists+0x64>)
800b3d6: f7ff fb73 bl 800aac0 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800b3da: 480d ldr r0, [pc, #52] ; (800b410 <prvInitialiseTaskLists+0x68>)
800b3dc: f7ff fb70 bl 800aac0 <vListInitialise>
vListInitialise( &xPendingReadyList );
800b3e0: 480c ldr r0, [pc, #48] ; (800b414 <prvInitialiseTaskLists+0x6c>)
800b3e2: f7ff fb6d bl 800aac0 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800b3e6: 480c ldr r0, [pc, #48] ; (800b418 <prvInitialiseTaskLists+0x70>)
800b3e8: f7ff fb6a bl 800aac0 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
800b3ec: 480b ldr r0, [pc, #44] ; (800b41c <prvInitialiseTaskLists+0x74>)
800b3ee: f7ff fb67 bl 800aac0 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
800b3f2: 4b0b ldr r3, [pc, #44] ; (800b420 <prvInitialiseTaskLists+0x78>)
800b3f4: 4a05 ldr r2, [pc, #20] ; (800b40c <prvInitialiseTaskLists+0x64>)
800b3f6: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800b3f8: 4b0a ldr r3, [pc, #40] ; (800b424 <prvInitialiseTaskLists+0x7c>)
800b3fa: 4a05 ldr r2, [pc, #20] ; (800b410 <prvInitialiseTaskLists+0x68>)
800b3fc: 601a str r2, [r3, #0]
}
800b3fe: bf00 nop
800b400: 3708 adds r7, #8
800b402: 46bd mov sp, r7
800b404: bd80 pop {r7, pc}
800b406: bf00 nop
800b408: 200002f8 .word 0x200002f8
800b40c: 20000384 .word 0x20000384
800b410: 20000398 .word 0x20000398
800b414: 200003b4 .word 0x200003b4
800b418: 200003c8 .word 0x200003c8
800b41c: 200003dc .word 0x200003dc
800b420: 200003ac .word 0x200003ac
800b424: 200003b0 .word 0x200003b0
0800b428 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
800b428: b480 push {r7}
800b42a: b083 sub sp, #12
800b42c: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800b42e: 4b0c ldr r3, [pc, #48] ; (800b460 <prvResetNextTaskUnblockTime+0x38>)
800b430: 681b ldr r3, [r3, #0]
800b432: 681b ldr r3, [r3, #0]
800b434: 2b00 cmp r3, #0
800b436: d104 bne.n 800b442 <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
800b438: 4b0a ldr r3, [pc, #40] ; (800b464 <prvResetNextTaskUnblockTime+0x3c>)
800b43a: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800b43e: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
800b440: e008 b.n 800b454 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800b442: 4b07 ldr r3, [pc, #28] ; (800b460 <prvResetNextTaskUnblockTime+0x38>)
800b444: 681b ldr r3, [r3, #0]
800b446: 68db ldr r3, [r3, #12]
800b448: 68db ldr r3, [r3, #12]
800b44a: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
800b44c: 687b ldr r3, [r7, #4]
800b44e: 685b ldr r3, [r3, #4]
800b450: 4a04 ldr r2, [pc, #16] ; (800b464 <prvResetNextTaskUnblockTime+0x3c>)
800b452: 6013 str r3, [r2, #0]
}
800b454: bf00 nop
800b456: 370c adds r7, #12
800b458: 46bd mov sp, r7
800b45a: f85d 7b04 ldr.w r7, [sp], #4
800b45e: 4770 bx lr
800b460: 200003ac .word 0x200003ac
800b464: 20000410 .word 0x20000410
0800b468 <prvAddCurrentTaskToDelayedList>:
}
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
800b468: b580 push {r7, lr}
800b46a: b084 sub sp, #16
800b46c: af00 add r7, sp, #0
800b46e: 6078 str r0, [r7, #4]
800b470: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
800b472: 4b29 ldr r3, [pc, #164] ; (800b518 <prvAddCurrentTaskToDelayedList+0xb0>)
800b474: 681b ldr r3, [r3, #0]
800b476: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800b478: 4b28 ldr r3, [pc, #160] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b47a: 681b ldr r3, [r3, #0]
800b47c: 3304 adds r3, #4
800b47e: 4618 mov r0, r3
800b480: f7ff fba8 bl 800abd4 <uxListRemove>
800b484: 4603 mov r3, r0
800b486: 2b00 cmp r3, #0
800b488: d10b bne.n 800b4a2 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
800b48a: 4b24 ldr r3, [pc, #144] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b48c: 681b ldr r3, [r3, #0]
800b48e: 6adb ldr r3, [r3, #44] ; 0x2c
800b490: 2201 movs r2, #1
800b492: fa02 f303 lsl.w r3, r2, r3
800b496: 43da mvns r2, r3
800b498: 4b21 ldr r3, [pc, #132] ; (800b520 <prvAddCurrentTaskToDelayedList+0xb8>)
800b49a: 681b ldr r3, [r3, #0]
800b49c: 4013 ands r3, r2
800b49e: 4a20 ldr r2, [pc, #128] ; (800b520 <prvAddCurrentTaskToDelayedList+0xb8>)
800b4a0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
800b4a2: 687b ldr r3, [r7, #4]
800b4a4: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800b4a8: d10a bne.n 800b4c0 <prvAddCurrentTaskToDelayedList+0x58>
800b4aa: 683b ldr r3, [r7, #0]
800b4ac: 2b00 cmp r3, #0
800b4ae: d007 beq.n 800b4c0 <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
800b4b0: 4b1a ldr r3, [pc, #104] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b4b2: 681b ldr r3, [r3, #0]
800b4b4: 3304 adds r3, #4
800b4b6: 4619 mov r1, r3
800b4b8: 481a ldr r0, [pc, #104] ; (800b524 <prvAddCurrentTaskToDelayedList+0xbc>)
800b4ba: f7ff fb2e bl 800ab1a <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
800b4be: e026 b.n 800b50e <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
800b4c0: 68fa ldr r2, [r7, #12]
800b4c2: 687b ldr r3, [r7, #4]
800b4c4: 4413 add r3, r2
800b4c6: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
800b4c8: 4b14 ldr r3, [pc, #80] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b4ca: 681b ldr r3, [r3, #0]
800b4cc: 68ba ldr r2, [r7, #8]
800b4ce: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
800b4d0: 68ba ldr r2, [r7, #8]
800b4d2: 68fb ldr r3, [r7, #12]
800b4d4: 429a cmp r2, r3
800b4d6: d209 bcs.n 800b4ec <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800b4d8: 4b13 ldr r3, [pc, #76] ; (800b528 <prvAddCurrentTaskToDelayedList+0xc0>)
800b4da: 681a ldr r2, [r3, #0]
800b4dc: 4b0f ldr r3, [pc, #60] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b4de: 681b ldr r3, [r3, #0]
800b4e0: 3304 adds r3, #4
800b4e2: 4619 mov r1, r3
800b4e4: 4610 mov r0, r2
800b4e6: f7ff fb3c bl 800ab62 <vListInsert>
}
800b4ea: e010 b.n 800b50e <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800b4ec: 4b0f ldr r3, [pc, #60] ; (800b52c <prvAddCurrentTaskToDelayedList+0xc4>)
800b4ee: 681a ldr r2, [r3, #0]
800b4f0: 4b0a ldr r3, [pc, #40] ; (800b51c <prvAddCurrentTaskToDelayedList+0xb4>)
800b4f2: 681b ldr r3, [r3, #0]
800b4f4: 3304 adds r3, #4
800b4f6: 4619 mov r1, r3
800b4f8: 4610 mov r0, r2
800b4fa: f7ff fb32 bl 800ab62 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
800b4fe: 4b0c ldr r3, [pc, #48] ; (800b530 <prvAddCurrentTaskToDelayedList+0xc8>)
800b500: 681b ldr r3, [r3, #0]
800b502: 68ba ldr r2, [r7, #8]
800b504: 429a cmp r2, r3
800b506: d202 bcs.n 800b50e <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
800b508: 4a09 ldr r2, [pc, #36] ; (800b530 <prvAddCurrentTaskToDelayedList+0xc8>)
800b50a: 68bb ldr r3, [r7, #8]
800b50c: 6013 str r3, [r2, #0]
}
800b50e: bf00 nop
800b510: 3710 adds r7, #16
800b512: 46bd mov sp, r7
800b514: bd80 pop {r7, pc}
800b516: bf00 nop
800b518: 200003f4 .word 0x200003f4
800b51c: 200002f4 .word 0x200002f4
800b520: 200003f8 .word 0x200003f8
800b524: 200003dc .word 0x200003dc
800b528: 200003b0 .word 0x200003b0
800b52c: 200003ac .word 0x200003ac
800b530: 20000410 .word 0x20000410
0800b534 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
800b534: b480 push {r7}
800b536: b085 sub sp, #20
800b538: af00 add r7, sp, #0
800b53a: 60f8 str r0, [r7, #12]
800b53c: 60b9 str r1, [r7, #8]
800b53e: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
800b540: 68fb ldr r3, [r7, #12]
800b542: 3b04 subs r3, #4
800b544: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
800b546: 68fb ldr r3, [r7, #12]
800b548: f04f 7280 mov.w r2, #16777216 ; 0x1000000
800b54c: 601a str r2, [r3, #0]
pxTopOfStack--;
800b54e: 68fb ldr r3, [r7, #12]
800b550: 3b04 subs r3, #4
800b552: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
800b554: 68bb ldr r3, [r7, #8]
800b556: f023 0201 bic.w r2, r3, #1
800b55a: 68fb ldr r3, [r7, #12]
800b55c: 601a str r2, [r3, #0]
pxTopOfStack--;
800b55e: 68fb ldr r3, [r7, #12]
800b560: 3b04 subs r3, #4
800b562: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
800b564: 4a0c ldr r2, [pc, #48] ; (800b598 <pxPortInitialiseStack+0x64>)
800b566: 68fb ldr r3, [r7, #12]
800b568: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
800b56a: 68fb ldr r3, [r7, #12]
800b56c: 3b14 subs r3, #20
800b56e: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
800b570: 687a ldr r2, [r7, #4]
800b572: 68fb ldr r3, [r7, #12]
800b574: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
800b576: 68fb ldr r3, [r7, #12]
800b578: 3b04 subs r3, #4
800b57a: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
800b57c: 68fb ldr r3, [r7, #12]
800b57e: f06f 0202 mvn.w r2, #2
800b582: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
800b584: 68fb ldr r3, [r7, #12]
800b586: 3b20 subs r3, #32
800b588: 60fb str r3, [r7, #12]
return pxTopOfStack;
800b58a: 68fb ldr r3, [r7, #12]
}
800b58c: 4618 mov r0, r3
800b58e: 3714 adds r7, #20
800b590: 46bd mov sp, r7
800b592: f85d 7b04 ldr.w r7, [sp], #4
800b596: 4770 bx lr
800b598: 0800b59d .word 0x0800b59d
0800b59c <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
800b59c: b480 push {r7}
800b59e: b085 sub sp, #20
800b5a0: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
800b5a2: 2300 movs r3, #0
800b5a4: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
800b5a6: 4b13 ldr r3, [pc, #76] ; (800b5f4 <prvTaskExitError+0x58>)
800b5a8: 681b ldr r3, [r3, #0]
800b5aa: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800b5ae: d00b beq.n 800b5c8 <prvTaskExitError+0x2c>
800b5b0: f04f 0350 mov.w r3, #80 ; 0x50
800b5b4: b672 cpsid i
800b5b6: f383 8811 msr BASEPRI, r3
800b5ba: f3bf 8f6f isb sy
800b5be: f3bf 8f4f dsb sy
800b5c2: b662 cpsie i
800b5c4: 60fb str r3, [r7, #12]
800b5c6: e7fe b.n 800b5c6 <prvTaskExitError+0x2a>
800b5c8: f04f 0350 mov.w r3, #80 ; 0x50
800b5cc: b672 cpsid i
800b5ce: f383 8811 msr BASEPRI, r3
800b5d2: f3bf 8f6f isb sy
800b5d6: f3bf 8f4f dsb sy
800b5da: b662 cpsie i
800b5dc: 60bb str r3, [r7, #8]
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
800b5de: bf00 nop
800b5e0: 687b ldr r3, [r7, #4]
800b5e2: 2b00 cmp r3, #0
800b5e4: d0fc beq.n 800b5e0 <prvTaskExitError+0x44>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
800b5e6: bf00 nop
800b5e8: 3714 adds r7, #20
800b5ea: 46bd mov sp, r7
800b5ec: f85d 7b04 ldr.w r7, [sp], #4
800b5f0: 4770 bx lr
800b5f2: bf00 nop
800b5f4: 20000048 .word 0x20000048
...
0800b600 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
800b600: 4b07 ldr r3, [pc, #28] ; (800b620 <pxCurrentTCBConst2>)
800b602: 6819 ldr r1, [r3, #0]
800b604: 6808 ldr r0, [r1, #0]
800b606: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b60a: f380 8809 msr PSP, r0
800b60e: f3bf 8f6f isb sy
800b612: f04f 0000 mov.w r0, #0
800b616: f380 8811 msr BASEPRI, r0
800b61a: 4770 bx lr
800b61c: f3af 8000 nop.w
0800b620 <pxCurrentTCBConst2>:
800b620: 200002f4 .word 0x200002f4
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
800b624: bf00 nop
800b626: bf00 nop
0800b628 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
800b628: b480 push {r7}
800b62a: b083 sub sp, #12
800b62c: af00 add r7, sp, #0
800b62e: f04f 0350 mov.w r3, #80 ; 0x50
800b632: b672 cpsid i
800b634: f383 8811 msr BASEPRI, r3
800b638: f3bf 8f6f isb sy
800b63c: f3bf 8f4f dsb sy
800b640: b662 cpsie i
800b642: 607b str r3, [r7, #4]
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
800b644: 4b0f ldr r3, [pc, #60] ; (800b684 <vPortEnterCritical+0x5c>)
800b646: 681b ldr r3, [r3, #0]
800b648: 3301 adds r3, #1
800b64a: 4a0e ldr r2, [pc, #56] ; (800b684 <vPortEnterCritical+0x5c>)
800b64c: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
800b64e: 4b0d ldr r3, [pc, #52] ; (800b684 <vPortEnterCritical+0x5c>)
800b650: 681b ldr r3, [r3, #0]
800b652: 2b01 cmp r3, #1
800b654: d110 bne.n 800b678 <vPortEnterCritical+0x50>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
800b656: 4b0c ldr r3, [pc, #48] ; (800b688 <vPortEnterCritical+0x60>)
800b658: 681b ldr r3, [r3, #0]
800b65a: b2db uxtb r3, r3
800b65c: 2b00 cmp r3, #0
800b65e: d00b beq.n 800b678 <vPortEnterCritical+0x50>
800b660: f04f 0350 mov.w r3, #80 ; 0x50
800b664: b672 cpsid i
800b666: f383 8811 msr BASEPRI, r3
800b66a: f3bf 8f6f isb sy
800b66e: f3bf 8f4f dsb sy
800b672: b662 cpsie i
800b674: 603b str r3, [r7, #0]
800b676: e7fe b.n 800b676 <vPortEnterCritical+0x4e>
}
}
800b678: bf00 nop
800b67a: 370c adds r7, #12
800b67c: 46bd mov sp, r7
800b67e: f85d 7b04 ldr.w r7, [sp], #4
800b682: 4770 bx lr
800b684: 20000048 .word 0x20000048
800b688: e000ed04 .word 0xe000ed04
0800b68c <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
800b68c: b480 push {r7}
800b68e: b083 sub sp, #12
800b690: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
800b692: 4b12 ldr r3, [pc, #72] ; (800b6dc <vPortExitCritical+0x50>)
800b694: 681b ldr r3, [r3, #0]
800b696: 2b00 cmp r3, #0
800b698: d10b bne.n 800b6b2 <vPortExitCritical+0x26>
800b69a: f04f 0350 mov.w r3, #80 ; 0x50
800b69e: b672 cpsid i
800b6a0: f383 8811 msr BASEPRI, r3
800b6a4: f3bf 8f6f isb sy
800b6a8: f3bf 8f4f dsb sy
800b6ac: b662 cpsie i
800b6ae: 607b str r3, [r7, #4]
800b6b0: e7fe b.n 800b6b0 <vPortExitCritical+0x24>
uxCriticalNesting--;
800b6b2: 4b0a ldr r3, [pc, #40] ; (800b6dc <vPortExitCritical+0x50>)
800b6b4: 681b ldr r3, [r3, #0]
800b6b6: 3b01 subs r3, #1
800b6b8: 4a08 ldr r2, [pc, #32] ; (800b6dc <vPortExitCritical+0x50>)
800b6ba: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
800b6bc: 4b07 ldr r3, [pc, #28] ; (800b6dc <vPortExitCritical+0x50>)
800b6be: 681b ldr r3, [r3, #0]
800b6c0: 2b00 cmp r3, #0
800b6c2: d104 bne.n 800b6ce <vPortExitCritical+0x42>
800b6c4: 2300 movs r3, #0
800b6c6: 603b str r3, [r7, #0]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
800b6c8: 683b ldr r3, [r7, #0]
800b6ca: f383 8811 msr BASEPRI, r3
{
portENABLE_INTERRUPTS();
}
}
800b6ce: bf00 nop
800b6d0: 370c adds r7, #12
800b6d2: 46bd mov sp, r7
800b6d4: f85d 7b04 ldr.w r7, [sp], #4
800b6d8: 4770 bx lr
800b6da: bf00 nop
800b6dc: 20000048 .word 0x20000048
0800b6e0 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
800b6e0: f3ef 8009 mrs r0, PSP
800b6e4: f3bf 8f6f isb sy
800b6e8: 4b15 ldr r3, [pc, #84] ; (800b740 <pxCurrentTCBConst>)
800b6ea: 681a ldr r2, [r3, #0]
800b6ec: f01e 0f10 tst.w lr, #16
800b6f0: bf08 it eq
800b6f2: ed20 8a10 vstmdbeq r0!, {s16-s31}
800b6f6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b6fa: 6010 str r0, [r2, #0]
800b6fc: e92d 0009 stmdb sp!, {r0, r3}
800b700: f04f 0050 mov.w r0, #80 ; 0x50
800b704: b672 cpsid i
800b706: f380 8811 msr BASEPRI, r0
800b70a: f3bf 8f4f dsb sy
800b70e: f3bf 8f6f isb sy
800b712: b662 cpsie i
800b714: f7ff fdc6 bl 800b2a4 <vTaskSwitchContext>
800b718: f04f 0000 mov.w r0, #0
800b71c: f380 8811 msr BASEPRI, r0
800b720: bc09 pop {r0, r3}
800b722: 6819 ldr r1, [r3, #0]
800b724: 6808 ldr r0, [r1, #0]
800b726: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800b72a: f01e 0f10 tst.w lr, #16
800b72e: bf08 it eq
800b730: ecb0 8a10 vldmiaeq r0!, {s16-s31}
800b734: f380 8809 msr PSP, r0
800b738: f3bf 8f6f isb sy
800b73c: 4770 bx lr
800b73e: bf00 nop
0800b740 <pxCurrentTCBConst>:
800b740: 200002f4 .word 0x200002f4
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
800b744: bf00 nop
800b746: bf00 nop
0800b748 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
800b748: b580 push {r7, lr}
800b74a: b082 sub sp, #8
800b74c: af00 add r7, sp, #0
__asm volatile
800b74e: f04f 0350 mov.w r3, #80 ; 0x50
800b752: b672 cpsid i
800b754: f383 8811 msr BASEPRI, r3
800b758: f3bf 8f6f isb sy
800b75c: f3bf 8f4f dsb sy
800b760: b662 cpsie i
800b762: 607b str r3, [r7, #4]
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
800b764: f7ff fce4 bl 800b130 <xTaskIncrementTick>
800b768: 4603 mov r3, r0
800b76a: 2b00 cmp r3, #0
800b76c: d003 beq.n 800b776 <SysTick_Handler+0x2e>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
800b76e: 4b06 ldr r3, [pc, #24] ; (800b788 <SysTick_Handler+0x40>)
800b770: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800b774: 601a str r2, [r3, #0]
800b776: 2300 movs r3, #0
800b778: 603b str r3, [r7, #0]
__asm volatile
800b77a: 683b ldr r3, [r7, #0]
800b77c: f383 8811 msr BASEPRI, r3
}
}
portENABLE_INTERRUPTS();
}
800b780: bf00 nop
800b782: 3708 adds r7, #8
800b784: 46bd mov sp, r7
800b786: bd80 pop {r7, pc}
800b788: e000ed04 .word 0xe000ed04
0800b78c <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
800b78c: b580 push {r7, lr}
800b78e: b08a sub sp, #40 ; 0x28
800b790: af00 add r7, sp, #0
800b792: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
800b794: 2300 movs r3, #0
800b796: 61fb str r3, [r7, #28]
vTaskSuspendAll();
800b798: f7ff fc1e bl 800afd8 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
800b79c: 4b5c ldr r3, [pc, #368] ; (800b910 <pvPortMalloc+0x184>)
800b79e: 681b ldr r3, [r3, #0]
800b7a0: 2b00 cmp r3, #0
800b7a2: d101 bne.n 800b7a8 <pvPortMalloc+0x1c>
{
prvHeapInit();
800b7a4: f000 f91a bl 800b9dc <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
800b7a8: 4b5a ldr r3, [pc, #360] ; (800b914 <pvPortMalloc+0x188>)
800b7aa: 681a ldr r2, [r3, #0]
800b7ac: 687b ldr r3, [r7, #4]
800b7ae: 4013 ands r3, r2
800b7b0: 2b00 cmp r3, #0
800b7b2: f040 8090 bne.w 800b8d6 <pvPortMalloc+0x14a>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
800b7b6: 687b ldr r3, [r7, #4]
800b7b8: 2b00 cmp r3, #0
800b7ba: d01e beq.n 800b7fa <pvPortMalloc+0x6e>
{
xWantedSize += xHeapStructSize;
800b7bc: 2208 movs r2, #8
800b7be: 687b ldr r3, [r7, #4]
800b7c0: 4413 add r3, r2
800b7c2: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
800b7c4: 687b ldr r3, [r7, #4]
800b7c6: f003 0307 and.w r3, r3, #7
800b7ca: 2b00 cmp r3, #0
800b7cc: d015 beq.n 800b7fa <pvPortMalloc+0x6e>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
800b7ce: 687b ldr r3, [r7, #4]
800b7d0: f023 0307 bic.w r3, r3, #7
800b7d4: 3308 adds r3, #8
800b7d6: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
800b7d8: 687b ldr r3, [r7, #4]
800b7da: f003 0307 and.w r3, r3, #7
800b7de: 2b00 cmp r3, #0
800b7e0: d00b beq.n 800b7fa <pvPortMalloc+0x6e>
__asm volatile
800b7e2: f04f 0350 mov.w r3, #80 ; 0x50
800b7e6: b672 cpsid i
800b7e8: f383 8811 msr BASEPRI, r3
800b7ec: f3bf 8f6f isb sy
800b7f0: f3bf 8f4f dsb sy
800b7f4: b662 cpsie i
800b7f6: 617b str r3, [r7, #20]
800b7f8: e7fe b.n 800b7f8 <pvPortMalloc+0x6c>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
800b7fa: 687b ldr r3, [r7, #4]
800b7fc: 2b00 cmp r3, #0
800b7fe: d06a beq.n 800b8d6 <pvPortMalloc+0x14a>
800b800: 4b45 ldr r3, [pc, #276] ; (800b918 <pvPortMalloc+0x18c>)
800b802: 681b ldr r3, [r3, #0]
800b804: 687a ldr r2, [r7, #4]
800b806: 429a cmp r2, r3
800b808: d865 bhi.n 800b8d6 <pvPortMalloc+0x14a>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
800b80a: 4b44 ldr r3, [pc, #272] ; (800b91c <pvPortMalloc+0x190>)
800b80c: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
800b80e: 4b43 ldr r3, [pc, #268] ; (800b91c <pvPortMalloc+0x190>)
800b810: 681b ldr r3, [r3, #0]
800b812: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800b814: e004 b.n 800b820 <pvPortMalloc+0x94>
{
pxPreviousBlock = pxBlock;
800b816: 6a7b ldr r3, [r7, #36] ; 0x24
800b818: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
800b81a: 6a7b ldr r3, [r7, #36] ; 0x24
800b81c: 681b ldr r3, [r3, #0]
800b81e: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800b820: 6a7b ldr r3, [r7, #36] ; 0x24
800b822: 685b ldr r3, [r3, #4]
800b824: 687a ldr r2, [r7, #4]
800b826: 429a cmp r2, r3
800b828: d903 bls.n 800b832 <pvPortMalloc+0xa6>
800b82a: 6a7b ldr r3, [r7, #36] ; 0x24
800b82c: 681b ldr r3, [r3, #0]
800b82e: 2b00 cmp r3, #0
800b830: d1f1 bne.n 800b816 <pvPortMalloc+0x8a>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800b832: 4b37 ldr r3, [pc, #220] ; (800b910 <pvPortMalloc+0x184>)
800b834: 681b ldr r3, [r3, #0]
800b836: 6a7a ldr r2, [r7, #36] ; 0x24
800b838: 429a cmp r2, r3
800b83a: d04c beq.n 800b8d6 <pvPortMalloc+0x14a>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
800b83c: 6a3b ldr r3, [r7, #32]
800b83e: 681b ldr r3, [r3, #0]
800b840: 2208 movs r2, #8
800b842: 4413 add r3, r2
800b844: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
800b846: 6a7b ldr r3, [r7, #36] ; 0x24
800b848: 681a ldr r2, [r3, #0]
800b84a: 6a3b ldr r3, [r7, #32]
800b84c: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
800b84e: 6a7b ldr r3, [r7, #36] ; 0x24
800b850: 685a ldr r2, [r3, #4]
800b852: 687b ldr r3, [r7, #4]
800b854: 1ad2 subs r2, r2, r3
800b856: 2308 movs r3, #8
800b858: 005b lsls r3, r3, #1
800b85a: 429a cmp r2, r3
800b85c: d920 bls.n 800b8a0 <pvPortMalloc+0x114>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
800b85e: 6a7a ldr r2, [r7, #36] ; 0x24
800b860: 687b ldr r3, [r7, #4]
800b862: 4413 add r3, r2
800b864: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
800b866: 69bb ldr r3, [r7, #24]
800b868: f003 0307 and.w r3, r3, #7
800b86c: 2b00 cmp r3, #0
800b86e: d00b beq.n 800b888 <pvPortMalloc+0xfc>
800b870: f04f 0350 mov.w r3, #80 ; 0x50
800b874: b672 cpsid i
800b876: f383 8811 msr BASEPRI, r3
800b87a: f3bf 8f6f isb sy
800b87e: f3bf 8f4f dsb sy
800b882: b662 cpsie i
800b884: 613b str r3, [r7, #16]
800b886: e7fe b.n 800b886 <pvPortMalloc+0xfa>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
800b888: 6a7b ldr r3, [r7, #36] ; 0x24
800b88a: 685a ldr r2, [r3, #4]
800b88c: 687b ldr r3, [r7, #4]
800b88e: 1ad2 subs r2, r2, r3
800b890: 69bb ldr r3, [r7, #24]
800b892: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800b894: 6a7b ldr r3, [r7, #36] ; 0x24
800b896: 687a ldr r2, [r7, #4]
800b898: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
800b89a: 69b8 ldr r0, [r7, #24]
800b89c: f000 f900 bl 800baa0 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
800b8a0: 4b1d ldr r3, [pc, #116] ; (800b918 <pvPortMalloc+0x18c>)
800b8a2: 681a ldr r2, [r3, #0]
800b8a4: 6a7b ldr r3, [r7, #36] ; 0x24
800b8a6: 685b ldr r3, [r3, #4]
800b8a8: 1ad3 subs r3, r2, r3
800b8aa: 4a1b ldr r2, [pc, #108] ; (800b918 <pvPortMalloc+0x18c>)
800b8ac: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
800b8ae: 4b1a ldr r3, [pc, #104] ; (800b918 <pvPortMalloc+0x18c>)
800b8b0: 681a ldr r2, [r3, #0]
800b8b2: 4b1b ldr r3, [pc, #108] ; (800b920 <pvPortMalloc+0x194>)
800b8b4: 681b ldr r3, [r3, #0]
800b8b6: 429a cmp r2, r3
800b8b8: d203 bcs.n 800b8c2 <pvPortMalloc+0x136>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
800b8ba: 4b17 ldr r3, [pc, #92] ; (800b918 <pvPortMalloc+0x18c>)
800b8bc: 681b ldr r3, [r3, #0]
800b8be: 4a18 ldr r2, [pc, #96] ; (800b920 <pvPortMalloc+0x194>)
800b8c0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800b8c2: 6a7b ldr r3, [r7, #36] ; 0x24
800b8c4: 685a ldr r2, [r3, #4]
800b8c6: 4b13 ldr r3, [pc, #76] ; (800b914 <pvPortMalloc+0x188>)
800b8c8: 681b ldr r3, [r3, #0]
800b8ca: 431a orrs r2, r3
800b8cc: 6a7b ldr r3, [r7, #36] ; 0x24
800b8ce: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
800b8d0: 6a7b ldr r3, [r7, #36] ; 0x24
800b8d2: 2200 movs r2, #0
800b8d4: 601a str r2, [r3, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
800b8d6: f7ff fb8d bl 800aff4 <xTaskResumeAll>
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
{
if( pvReturn == NULL )
800b8da: 69fb ldr r3, [r7, #28]
800b8dc: 2b00 cmp r3, #0
800b8de: d101 bne.n 800b8e4 <pvPortMalloc+0x158>
{
extern void vApplicationMallocFailedHook( void );
vApplicationMallocFailedHook();
800b8e0: f7f4 fe71 bl 80005c6 <vApplicationMallocFailedHook>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
800b8e4: 69fb ldr r3, [r7, #28]
800b8e6: f003 0307 and.w r3, r3, #7
800b8ea: 2b00 cmp r3, #0
800b8ec: d00b beq.n 800b906 <pvPortMalloc+0x17a>
800b8ee: f04f 0350 mov.w r3, #80 ; 0x50
800b8f2: b672 cpsid i
800b8f4: f383 8811 msr BASEPRI, r3
800b8f8: f3bf 8f6f isb sy
800b8fc: f3bf 8f4f dsb sy
800b900: b662 cpsie i
800b902: 60fb str r3, [r7, #12]
800b904: e7fe b.n 800b904 <pvPortMalloc+0x178>
return pvReturn;
800b906: 69fb ldr r3, [r7, #28]
}
800b908: 4618 mov r0, r3
800b90a: 3728 adds r7, #40 ; 0x28
800b90c: 46bd mov sp, r7
800b90e: bd80 pop {r7, pc}
800b910: 20008420 .word 0x20008420
800b914: 2000842c .word 0x2000842c
800b918: 20008424 .word 0x20008424
800b91c: 20008418 .word 0x20008418
800b920: 20008428 .word 0x20008428
0800b924 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
800b924: b580 push {r7, lr}
800b926: b086 sub sp, #24
800b928: af00 add r7, sp, #0
800b92a: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
800b92c: 687b ldr r3, [r7, #4]
800b92e: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800b930: 687b ldr r3, [r7, #4]
800b932: 2b00 cmp r3, #0
800b934: d04a beq.n 800b9cc <vPortFree+0xa8>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
800b936: 2308 movs r3, #8
800b938: 425b negs r3, r3
800b93a: 697a ldr r2, [r7, #20]
800b93c: 4413 add r3, r2
800b93e: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800b940: 697b ldr r3, [r7, #20]
800b942: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
800b944: 693b ldr r3, [r7, #16]
800b946: 685a ldr r2, [r3, #4]
800b948: 4b22 ldr r3, [pc, #136] ; (800b9d4 <vPortFree+0xb0>)
800b94a: 681b ldr r3, [r3, #0]
800b94c: 4013 ands r3, r2
800b94e: 2b00 cmp r3, #0
800b950: d10b bne.n 800b96a <vPortFree+0x46>
800b952: f04f 0350 mov.w r3, #80 ; 0x50
800b956: b672 cpsid i
800b958: f383 8811 msr BASEPRI, r3
800b95c: f3bf 8f6f isb sy
800b960: f3bf 8f4f dsb sy
800b964: b662 cpsie i
800b966: 60fb str r3, [r7, #12]
800b968: e7fe b.n 800b968 <vPortFree+0x44>
configASSERT( pxLink->pxNextFreeBlock == NULL );
800b96a: 693b ldr r3, [r7, #16]
800b96c: 681b ldr r3, [r3, #0]
800b96e: 2b00 cmp r3, #0
800b970: d00b beq.n 800b98a <vPortFree+0x66>
800b972: f04f 0350 mov.w r3, #80 ; 0x50
800b976: b672 cpsid i
800b978: f383 8811 msr BASEPRI, r3
800b97c: f3bf 8f6f isb sy
800b980: f3bf 8f4f dsb sy
800b984: b662 cpsie i
800b986: 60bb str r3, [r7, #8]
800b988: e7fe b.n 800b988 <vPortFree+0x64>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
800b98a: 693b ldr r3, [r7, #16]
800b98c: 685a ldr r2, [r3, #4]
800b98e: 4b11 ldr r3, [pc, #68] ; (800b9d4 <vPortFree+0xb0>)
800b990: 681b ldr r3, [r3, #0]
800b992: 4013 ands r3, r2
800b994: 2b00 cmp r3, #0
800b996: d019 beq.n 800b9cc <vPortFree+0xa8>
{
if( pxLink->pxNextFreeBlock == NULL )
800b998: 693b ldr r3, [r7, #16]
800b99a: 681b ldr r3, [r3, #0]
800b99c: 2b00 cmp r3, #0
800b99e: d115 bne.n 800b9cc <vPortFree+0xa8>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
800b9a0: 693b ldr r3, [r7, #16]
800b9a2: 685a ldr r2, [r3, #4]
800b9a4: 4b0b ldr r3, [pc, #44] ; (800b9d4 <vPortFree+0xb0>)
800b9a6: 681b ldr r3, [r3, #0]
800b9a8: 43db mvns r3, r3
800b9aa: 401a ands r2, r3
800b9ac: 693b ldr r3, [r7, #16]
800b9ae: 605a str r2, [r3, #4]
vTaskSuspendAll();
800b9b0: f7ff fb12 bl 800afd8 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800b9b4: 693b ldr r3, [r7, #16]
800b9b6: 685a ldr r2, [r3, #4]
800b9b8: 4b07 ldr r3, [pc, #28] ; (800b9d8 <vPortFree+0xb4>)
800b9ba: 681b ldr r3, [r3, #0]
800b9bc: 4413 add r3, r2
800b9be: 4a06 ldr r2, [pc, #24] ; (800b9d8 <vPortFree+0xb4>)
800b9c0: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800b9c2: 6938 ldr r0, [r7, #16]
800b9c4: f000 f86c bl 800baa0 <prvInsertBlockIntoFreeList>
}
( void ) xTaskResumeAll();
800b9c8: f7ff fb14 bl 800aff4 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
800b9cc: bf00 nop
800b9ce: 3718 adds r7, #24
800b9d0: 46bd mov sp, r7
800b9d2: bd80 pop {r7, pc}
800b9d4: 2000842c .word 0x2000842c
800b9d8: 20008424 .word 0x20008424
0800b9dc <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
800b9dc: b480 push {r7}
800b9de: b085 sub sp, #20
800b9e0: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
800b9e2: f44f 4300 mov.w r3, #32768 ; 0x8000
800b9e6: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
800b9e8: 4b27 ldr r3, [pc, #156] ; (800ba88 <prvHeapInit+0xac>)
800b9ea: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
800b9ec: 68fb ldr r3, [r7, #12]
800b9ee: f003 0307 and.w r3, r3, #7
800b9f2: 2b00 cmp r3, #0
800b9f4: d00c beq.n 800ba10 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
800b9f6: 68fb ldr r3, [r7, #12]
800b9f8: 3307 adds r3, #7
800b9fa: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800b9fc: 68fb ldr r3, [r7, #12]
800b9fe: f023 0307 bic.w r3, r3, #7
800ba02: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800ba04: 68ba ldr r2, [r7, #8]
800ba06: 68fb ldr r3, [r7, #12]
800ba08: 1ad3 subs r3, r2, r3
800ba0a: 4a1f ldr r2, [pc, #124] ; (800ba88 <prvHeapInit+0xac>)
800ba0c: 4413 add r3, r2
800ba0e: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
800ba10: 68fb ldr r3, [r7, #12]
800ba12: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
800ba14: 4a1d ldr r2, [pc, #116] ; (800ba8c <prvHeapInit+0xb0>)
800ba16: 687b ldr r3, [r7, #4]
800ba18: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
800ba1a: 4b1c ldr r3, [pc, #112] ; (800ba8c <prvHeapInit+0xb0>)
800ba1c: 2200 movs r2, #0
800ba1e: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
800ba20: 687b ldr r3, [r7, #4]
800ba22: 68ba ldr r2, [r7, #8]
800ba24: 4413 add r3, r2
800ba26: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
800ba28: 2208 movs r2, #8
800ba2a: 68fb ldr r3, [r7, #12]
800ba2c: 1a9b subs r3, r3, r2
800ba2e: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
800ba30: 68fb ldr r3, [r7, #12]
800ba32: f023 0307 bic.w r3, r3, #7
800ba36: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
800ba38: 68fb ldr r3, [r7, #12]
800ba3a: 4a15 ldr r2, [pc, #84] ; (800ba90 <prvHeapInit+0xb4>)
800ba3c: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
800ba3e: 4b14 ldr r3, [pc, #80] ; (800ba90 <prvHeapInit+0xb4>)
800ba40: 681b ldr r3, [r3, #0]
800ba42: 2200 movs r2, #0
800ba44: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800ba46: 4b12 ldr r3, [pc, #72] ; (800ba90 <prvHeapInit+0xb4>)
800ba48: 681b ldr r3, [r3, #0]
800ba4a: 2200 movs r2, #0
800ba4c: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
800ba4e: 687b ldr r3, [r7, #4]
800ba50: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800ba52: 683b ldr r3, [r7, #0]
800ba54: 68fa ldr r2, [r7, #12]
800ba56: 1ad2 subs r2, r2, r3
800ba58: 683b ldr r3, [r7, #0]
800ba5a: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
800ba5c: 4b0c ldr r3, [pc, #48] ; (800ba90 <prvHeapInit+0xb4>)
800ba5e: 681a ldr r2, [r3, #0]
800ba60: 683b ldr r3, [r7, #0]
800ba62: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ba64: 683b ldr r3, [r7, #0]
800ba66: 685b ldr r3, [r3, #4]
800ba68: 4a0a ldr r2, [pc, #40] ; (800ba94 <prvHeapInit+0xb8>)
800ba6a: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800ba6c: 683b ldr r3, [r7, #0]
800ba6e: 685b ldr r3, [r3, #4]
800ba70: 4a09 ldr r2, [pc, #36] ; (800ba98 <prvHeapInit+0xbc>)
800ba72: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800ba74: 4b09 ldr r3, [pc, #36] ; (800ba9c <prvHeapInit+0xc0>)
800ba76: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
800ba7a: 601a str r2, [r3, #0]
}
800ba7c: bf00 nop
800ba7e: 3714 adds r7, #20
800ba80: 46bd mov sp, r7
800ba82: f85d 7b04 ldr.w r7, [sp], #4
800ba86: 4770 bx lr
800ba88: 20000418 .word 0x20000418
800ba8c: 20008418 .word 0x20008418
800ba90: 20008420 .word 0x20008420
800ba94: 20008428 .word 0x20008428
800ba98: 20008424 .word 0x20008424
800ba9c: 2000842c .word 0x2000842c
0800baa0 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
800baa0: b480 push {r7}
800baa2: b085 sub sp, #20
800baa4: af00 add r7, sp, #0
800baa6: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
800baa8: 4b28 ldr r3, [pc, #160] ; (800bb4c <prvInsertBlockIntoFreeList+0xac>)
800baaa: 60fb str r3, [r7, #12]
800baac: e002 b.n 800bab4 <prvInsertBlockIntoFreeList+0x14>
800baae: 68fb ldr r3, [r7, #12]
800bab0: 681b ldr r3, [r3, #0]
800bab2: 60fb str r3, [r7, #12]
800bab4: 68fb ldr r3, [r7, #12]
800bab6: 681b ldr r3, [r3, #0]
800bab8: 687a ldr r2, [r7, #4]
800baba: 429a cmp r2, r3
800babc: d8f7 bhi.n 800baae <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
800babe: 68fb ldr r3, [r7, #12]
800bac0: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
800bac2: 68fb ldr r3, [r7, #12]
800bac4: 685b ldr r3, [r3, #4]
800bac6: 68ba ldr r2, [r7, #8]
800bac8: 4413 add r3, r2
800baca: 687a ldr r2, [r7, #4]
800bacc: 429a cmp r2, r3
800bace: d108 bne.n 800bae2 <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
800bad0: 68fb ldr r3, [r7, #12]
800bad2: 685a ldr r2, [r3, #4]
800bad4: 687b ldr r3, [r7, #4]
800bad6: 685b ldr r3, [r3, #4]
800bad8: 441a add r2, r3
800bada: 68fb ldr r3, [r7, #12]
800badc: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
800bade: 68fb ldr r3, [r7, #12]
800bae0: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
800bae2: 687b ldr r3, [r7, #4]
800bae4: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
800bae6: 687b ldr r3, [r7, #4]
800bae8: 685b ldr r3, [r3, #4]
800baea: 68ba ldr r2, [r7, #8]
800baec: 441a add r2, r3
800baee: 68fb ldr r3, [r7, #12]
800baf0: 681b ldr r3, [r3, #0]
800baf2: 429a cmp r2, r3
800baf4: d118 bne.n 800bb28 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
800baf6: 68fb ldr r3, [r7, #12]
800baf8: 681a ldr r2, [r3, #0]
800bafa: 4b15 ldr r3, [pc, #84] ; (800bb50 <prvInsertBlockIntoFreeList+0xb0>)
800bafc: 681b ldr r3, [r3, #0]
800bafe: 429a cmp r2, r3
800bb00: d00d beq.n 800bb1e <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800bb02: 687b ldr r3, [r7, #4]
800bb04: 685a ldr r2, [r3, #4]
800bb06: 68fb ldr r3, [r7, #12]
800bb08: 681b ldr r3, [r3, #0]
800bb0a: 685b ldr r3, [r3, #4]
800bb0c: 441a add r2, r3
800bb0e: 687b ldr r3, [r7, #4]
800bb10: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
800bb12: 68fb ldr r3, [r7, #12]
800bb14: 681b ldr r3, [r3, #0]
800bb16: 681a ldr r2, [r3, #0]
800bb18: 687b ldr r3, [r7, #4]
800bb1a: 601a str r2, [r3, #0]
800bb1c: e008 b.n 800bb30 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
800bb1e: 4b0c ldr r3, [pc, #48] ; (800bb50 <prvInsertBlockIntoFreeList+0xb0>)
800bb20: 681a ldr r2, [r3, #0]
800bb22: 687b ldr r3, [r7, #4]
800bb24: 601a str r2, [r3, #0]
800bb26: e003 b.n 800bb30 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
800bb28: 68fb ldr r3, [r7, #12]
800bb2a: 681a ldr r2, [r3, #0]
800bb2c: 687b ldr r3, [r7, #4]
800bb2e: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
800bb30: 68fa ldr r2, [r7, #12]
800bb32: 687b ldr r3, [r7, #4]
800bb34: 429a cmp r2, r3
800bb36: d002 beq.n 800bb3e <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
800bb38: 68fb ldr r3, [r7, #12]
800bb3a: 687a ldr r2, [r7, #4]
800bb3c: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800bb3e: bf00 nop
800bb40: 3714 adds r7, #20
800bb42: 46bd mov sp, r7
800bb44: f85d 7b04 ldr.w r7, [sp], #4
800bb48: 4770 bx lr
800bb4a: bf00 nop
800bb4c: 20008418 .word 0x20008418
800bb50: 20008420 .word 0x20008420
0800bb54 <__errno>:
800bb54: 4b01 ldr r3, [pc, #4] ; (800bb5c <__errno+0x8>)
800bb56: 6818 ldr r0, [r3, #0]
800bb58: 4770 bx lr
800bb5a: bf00 nop
800bb5c: 2000004c .word 0x2000004c
0800bb60 <__libc_init_array>:
800bb60: b570 push {r4, r5, r6, lr}
800bb62: 4e0d ldr r6, [pc, #52] ; (800bb98 <__libc_init_array+0x38>)
800bb64: 4c0d ldr r4, [pc, #52] ; (800bb9c <__libc_init_array+0x3c>)
800bb66: 1ba4 subs r4, r4, r6
800bb68: 10a4 asrs r4, r4, #2
800bb6a: 2500 movs r5, #0
800bb6c: 42a5 cmp r5, r4
800bb6e: d109 bne.n 800bb84 <__libc_init_array+0x24>
800bb70: 4e0b ldr r6, [pc, #44] ; (800bba0 <__libc_init_array+0x40>)
800bb72: 4c0c ldr r4, [pc, #48] ; (800bba4 <__libc_init_array+0x44>)
800bb74: f000 fc28 bl 800c3c8 <_init>
800bb78: 1ba4 subs r4, r4, r6
800bb7a: 10a4 asrs r4, r4, #2
800bb7c: 2500 movs r5, #0
800bb7e: 42a5 cmp r5, r4
800bb80: d105 bne.n 800bb8e <__libc_init_array+0x2e>
800bb82: bd70 pop {r4, r5, r6, pc}
800bb84: f856 3025 ldr.w r3, [r6, r5, lsl #2]
800bb88: 4798 blx r3
800bb8a: 3501 adds r5, #1
800bb8c: e7ee b.n 800bb6c <__libc_init_array+0xc>
800bb8e: f856 3025 ldr.w r3, [r6, r5, lsl #2]
800bb92: 4798 blx r3
800bb94: 3501 adds r5, #1
800bb96: e7f2 b.n 800bb7e <__libc_init_array+0x1e>
800bb98: 0800e3cc .word 0x0800e3cc
800bb9c: 0800e3cc .word 0x0800e3cc
800bba0: 0800e3cc .word 0x0800e3cc
800bba4: 0800e3d0 .word 0x0800e3d0
0800bba8 <memcpy>:
800bba8: b510 push {r4, lr}
800bbaa: 1e43 subs r3, r0, #1
800bbac: 440a add r2, r1
800bbae: 4291 cmp r1, r2
800bbb0: d100 bne.n 800bbb4 <memcpy+0xc>
800bbb2: bd10 pop {r4, pc}
800bbb4: f811 4b01 ldrb.w r4, [r1], #1
800bbb8: f803 4f01 strb.w r4, [r3, #1]!
800bbbc: e7f7 b.n 800bbae <memcpy+0x6>
0800bbbe <memset>:
800bbbe: 4402 add r2, r0
800bbc0: 4603 mov r3, r0
800bbc2: 4293 cmp r3, r2
800bbc4: d100 bne.n 800bbc8 <memset+0xa>
800bbc6: 4770 bx lr
800bbc8: f803 1b01 strb.w r1, [r3], #1
800bbcc: e7f9 b.n 800bbc2 <memset+0x4>
...
0800bbd0 <siprintf>:
800bbd0: b40e push {r1, r2, r3}
800bbd2: b500 push {lr}
800bbd4: b09c sub sp, #112 ; 0x70
800bbd6: ab1d add r3, sp, #116 ; 0x74
800bbd8: 9002 str r0, [sp, #8]
800bbda: 9006 str r0, [sp, #24]
800bbdc: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
800bbe0: 4809 ldr r0, [pc, #36] ; (800bc08 <siprintf+0x38>)
800bbe2: 9107 str r1, [sp, #28]
800bbe4: 9104 str r1, [sp, #16]
800bbe6: 4909 ldr r1, [pc, #36] ; (800bc0c <siprintf+0x3c>)
800bbe8: f853 2b04 ldr.w r2, [r3], #4
800bbec: 9105 str r1, [sp, #20]
800bbee: 6800 ldr r0, [r0, #0]
800bbf0: 9301 str r3, [sp, #4]
800bbf2: a902 add r1, sp, #8
800bbf4: f000 f866 bl 800bcc4 <_svfiprintf_r>
800bbf8: 9b02 ldr r3, [sp, #8]
800bbfa: 2200 movs r2, #0
800bbfc: 701a strb r2, [r3, #0]
800bbfe: b01c add sp, #112 ; 0x70
800bc00: f85d eb04 ldr.w lr, [sp], #4
800bc04: b003 add sp, #12
800bc06: 4770 bx lr
800bc08: 2000004c .word 0x2000004c
800bc0c: ffff0208 .word 0xffff0208
0800bc10 <__ssputs_r>:
800bc10: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800bc14: 688e ldr r6, [r1, #8]
800bc16: 429e cmp r6, r3
800bc18: 4682 mov sl, r0
800bc1a: 460c mov r4, r1
800bc1c: 4690 mov r8, r2
800bc1e: 4699 mov r9, r3
800bc20: d837 bhi.n 800bc92 <__ssputs_r+0x82>
800bc22: 898a ldrh r2, [r1, #12]
800bc24: f412 6f90 tst.w r2, #1152 ; 0x480
800bc28: d031 beq.n 800bc8e <__ssputs_r+0x7e>
800bc2a: 6825 ldr r5, [r4, #0]
800bc2c: 6909 ldr r1, [r1, #16]
800bc2e: 1a6f subs r7, r5, r1
800bc30: 6965 ldr r5, [r4, #20]
800bc32: 2302 movs r3, #2
800bc34: eb05 0545 add.w r5, r5, r5, lsl #1
800bc38: fb95 f5f3 sdiv r5, r5, r3
800bc3c: f109 0301 add.w r3, r9, #1
800bc40: 443b add r3, r7
800bc42: 429d cmp r5, r3
800bc44: bf38 it cc
800bc46: 461d movcc r5, r3
800bc48: 0553 lsls r3, r2, #21
800bc4a: d530 bpl.n 800bcae <__ssputs_r+0x9e>
800bc4c: 4629 mov r1, r5
800bc4e: f000 fb21 bl 800c294 <_malloc_r>
800bc52: 4606 mov r6, r0
800bc54: b950 cbnz r0, 800bc6c <__ssputs_r+0x5c>
800bc56: 230c movs r3, #12
800bc58: f8ca 3000 str.w r3, [sl]
800bc5c: 89a3 ldrh r3, [r4, #12]
800bc5e: f043 0340 orr.w r3, r3, #64 ; 0x40
800bc62: 81a3 strh r3, [r4, #12]
800bc64: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
800bc68: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800bc6c: 463a mov r2, r7
800bc6e: 6921 ldr r1, [r4, #16]
800bc70: f7ff ff9a bl 800bba8 <memcpy>
800bc74: 89a3 ldrh r3, [r4, #12]
800bc76: f423 6390 bic.w r3, r3, #1152 ; 0x480
800bc7a: f043 0380 orr.w r3, r3, #128 ; 0x80
800bc7e: 81a3 strh r3, [r4, #12]
800bc80: 6126 str r6, [r4, #16]
800bc82: 6165 str r5, [r4, #20]
800bc84: 443e add r6, r7
800bc86: 1bed subs r5, r5, r7
800bc88: 6026 str r6, [r4, #0]
800bc8a: 60a5 str r5, [r4, #8]
800bc8c: 464e mov r6, r9
800bc8e: 454e cmp r6, r9
800bc90: d900 bls.n 800bc94 <__ssputs_r+0x84>
800bc92: 464e mov r6, r9
800bc94: 4632 mov r2, r6
800bc96: 4641 mov r1, r8
800bc98: 6820 ldr r0, [r4, #0]
800bc9a: f000 fa93 bl 800c1c4 <memmove>
800bc9e: 68a3 ldr r3, [r4, #8]
800bca0: 1b9b subs r3, r3, r6
800bca2: 60a3 str r3, [r4, #8]
800bca4: 6823 ldr r3, [r4, #0]
800bca6: 441e add r6, r3
800bca8: 6026 str r6, [r4, #0]
800bcaa: 2000 movs r0, #0
800bcac: e7dc b.n 800bc68 <__ssputs_r+0x58>
800bcae: 462a mov r2, r5
800bcb0: f000 fb4a bl 800c348 <_realloc_r>
800bcb4: 4606 mov r6, r0
800bcb6: 2800 cmp r0, #0
800bcb8: d1e2 bne.n 800bc80 <__ssputs_r+0x70>
800bcba: 6921 ldr r1, [r4, #16]
800bcbc: 4650 mov r0, sl
800bcbe: f000 fa9b bl 800c1f8 <_free_r>
800bcc2: e7c8 b.n 800bc56 <__ssputs_r+0x46>
0800bcc4 <_svfiprintf_r>:
800bcc4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800bcc8: 461d mov r5, r3
800bcca: 898b ldrh r3, [r1, #12]
800bccc: 061f lsls r7, r3, #24
800bcce: b09d sub sp, #116 ; 0x74
800bcd0: 4680 mov r8, r0
800bcd2: 460c mov r4, r1
800bcd4: 4616 mov r6, r2
800bcd6: d50f bpl.n 800bcf8 <_svfiprintf_r+0x34>
800bcd8: 690b ldr r3, [r1, #16]
800bcda: b96b cbnz r3, 800bcf8 <_svfiprintf_r+0x34>
800bcdc: 2140 movs r1, #64 ; 0x40
800bcde: f000 fad9 bl 800c294 <_malloc_r>
800bce2: 6020 str r0, [r4, #0]
800bce4: 6120 str r0, [r4, #16]
800bce6: b928 cbnz r0, 800bcf4 <_svfiprintf_r+0x30>
800bce8: 230c movs r3, #12
800bcea: f8c8 3000 str.w r3, [r8]
800bcee: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
800bcf2: e0c8 b.n 800be86 <_svfiprintf_r+0x1c2>
800bcf4: 2340 movs r3, #64 ; 0x40
800bcf6: 6163 str r3, [r4, #20]
800bcf8: 2300 movs r3, #0
800bcfa: 9309 str r3, [sp, #36] ; 0x24
800bcfc: 2320 movs r3, #32
800bcfe: f88d 3029 strb.w r3, [sp, #41] ; 0x29
800bd02: 2330 movs r3, #48 ; 0x30
800bd04: f88d 302a strb.w r3, [sp, #42] ; 0x2a
800bd08: 9503 str r5, [sp, #12]
800bd0a: f04f 0b01 mov.w fp, #1
800bd0e: 4637 mov r7, r6
800bd10: 463d mov r5, r7
800bd12: f815 3b01 ldrb.w r3, [r5], #1
800bd16: b10b cbz r3, 800bd1c <_svfiprintf_r+0x58>
800bd18: 2b25 cmp r3, #37 ; 0x25
800bd1a: d13e bne.n 800bd9a <_svfiprintf_r+0xd6>
800bd1c: ebb7 0a06 subs.w sl, r7, r6
800bd20: d00b beq.n 800bd3a <_svfiprintf_r+0x76>
800bd22: 4653 mov r3, sl
800bd24: 4632 mov r2, r6
800bd26: 4621 mov r1, r4
800bd28: 4640 mov r0, r8
800bd2a: f7ff ff71 bl 800bc10 <__ssputs_r>
800bd2e: 3001 adds r0, #1
800bd30: f000 80a4 beq.w 800be7c <_svfiprintf_r+0x1b8>
800bd34: 9b09 ldr r3, [sp, #36] ; 0x24
800bd36: 4453 add r3, sl
800bd38: 9309 str r3, [sp, #36] ; 0x24
800bd3a: 783b ldrb r3, [r7, #0]
800bd3c: 2b00 cmp r3, #0
800bd3e: f000 809d beq.w 800be7c <_svfiprintf_r+0x1b8>
800bd42: 2300 movs r3, #0
800bd44: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800bd48: e9cd 2305 strd r2, r3, [sp, #20]
800bd4c: 9304 str r3, [sp, #16]
800bd4e: 9307 str r3, [sp, #28]
800bd50: f88d 3053 strb.w r3, [sp, #83] ; 0x53
800bd54: 931a str r3, [sp, #104] ; 0x68
800bd56: 462f mov r7, r5
800bd58: 2205 movs r2, #5
800bd5a: f817 1b01 ldrb.w r1, [r7], #1
800bd5e: 4850 ldr r0, [pc, #320] ; (800bea0 <_svfiprintf_r+0x1dc>)
800bd60: f7f4 fa56 bl 8000210 <memchr>
800bd64: 9b04 ldr r3, [sp, #16]
800bd66: b9d0 cbnz r0, 800bd9e <_svfiprintf_r+0xda>
800bd68: 06d9 lsls r1, r3, #27
800bd6a: bf44 itt mi
800bd6c: 2220 movmi r2, #32
800bd6e: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
800bd72: 071a lsls r2, r3, #28
800bd74: bf44 itt mi
800bd76: 222b movmi r2, #43 ; 0x2b
800bd78: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
800bd7c: 782a ldrb r2, [r5, #0]
800bd7e: 2a2a cmp r2, #42 ; 0x2a
800bd80: d015 beq.n 800bdae <_svfiprintf_r+0xea>
800bd82: 9a07 ldr r2, [sp, #28]
800bd84: 462f mov r7, r5
800bd86: 2000 movs r0, #0
800bd88: 250a movs r5, #10
800bd8a: 4639 mov r1, r7
800bd8c: f811 3b01 ldrb.w r3, [r1], #1
800bd90: 3b30 subs r3, #48 ; 0x30
800bd92: 2b09 cmp r3, #9
800bd94: d94d bls.n 800be32 <_svfiprintf_r+0x16e>
800bd96: b1b8 cbz r0, 800bdc8 <_svfiprintf_r+0x104>
800bd98: e00f b.n 800bdba <_svfiprintf_r+0xf6>
800bd9a: 462f mov r7, r5
800bd9c: e7b8 b.n 800bd10 <_svfiprintf_r+0x4c>
800bd9e: 4a40 ldr r2, [pc, #256] ; (800bea0 <_svfiprintf_r+0x1dc>)
800bda0: 1a80 subs r0, r0, r2
800bda2: fa0b f000 lsl.w r0, fp, r0
800bda6: 4318 orrs r0, r3
800bda8: 9004 str r0, [sp, #16]
800bdaa: 463d mov r5, r7
800bdac: e7d3 b.n 800bd56 <_svfiprintf_r+0x92>
800bdae: 9a03 ldr r2, [sp, #12]
800bdb0: 1d11 adds r1, r2, #4
800bdb2: 6812 ldr r2, [r2, #0]
800bdb4: 9103 str r1, [sp, #12]
800bdb6: 2a00 cmp r2, #0
800bdb8: db01 blt.n 800bdbe <_svfiprintf_r+0xfa>
800bdba: 9207 str r2, [sp, #28]
800bdbc: e004 b.n 800bdc8 <_svfiprintf_r+0x104>
800bdbe: 4252 negs r2, r2
800bdc0: f043 0302 orr.w r3, r3, #2
800bdc4: 9207 str r2, [sp, #28]
800bdc6: 9304 str r3, [sp, #16]
800bdc8: 783b ldrb r3, [r7, #0]
800bdca: 2b2e cmp r3, #46 ; 0x2e
800bdcc: d10c bne.n 800bde8 <_svfiprintf_r+0x124>
800bdce: 787b ldrb r3, [r7, #1]
800bdd0: 2b2a cmp r3, #42 ; 0x2a
800bdd2: d133 bne.n 800be3c <_svfiprintf_r+0x178>
800bdd4: 9b03 ldr r3, [sp, #12]
800bdd6: 1d1a adds r2, r3, #4
800bdd8: 681b ldr r3, [r3, #0]
800bdda: 9203 str r2, [sp, #12]
800bddc: 2b00 cmp r3, #0
800bdde: bfb8 it lt
800bde0: f04f 33ff movlt.w r3, #4294967295 ; 0xffffffff
800bde4: 3702 adds r7, #2
800bde6: 9305 str r3, [sp, #20]
800bde8: 4d2e ldr r5, [pc, #184] ; (800bea4 <_svfiprintf_r+0x1e0>)
800bdea: 7839 ldrb r1, [r7, #0]
800bdec: 2203 movs r2, #3
800bdee: 4628 mov r0, r5
800bdf0: f7f4 fa0e bl 8000210 <memchr>
800bdf4: b138 cbz r0, 800be06 <_svfiprintf_r+0x142>
800bdf6: 2340 movs r3, #64 ; 0x40
800bdf8: 1b40 subs r0, r0, r5
800bdfa: fa03 f000 lsl.w r0, r3, r0
800bdfe: 9b04 ldr r3, [sp, #16]
800be00: 4303 orrs r3, r0
800be02: 3701 adds r7, #1
800be04: 9304 str r3, [sp, #16]
800be06: 7839 ldrb r1, [r7, #0]
800be08: 4827 ldr r0, [pc, #156] ; (800bea8 <_svfiprintf_r+0x1e4>)
800be0a: f88d 1028 strb.w r1, [sp, #40] ; 0x28
800be0e: 2206 movs r2, #6
800be10: 1c7e adds r6, r7, #1
800be12: f7f4 f9fd bl 8000210 <memchr>
800be16: 2800 cmp r0, #0
800be18: d038 beq.n 800be8c <_svfiprintf_r+0x1c8>
800be1a: 4b24 ldr r3, [pc, #144] ; (800beac <_svfiprintf_r+0x1e8>)
800be1c: bb13 cbnz r3, 800be64 <_svfiprintf_r+0x1a0>
800be1e: 9b03 ldr r3, [sp, #12]
800be20: 3307 adds r3, #7
800be22: f023 0307 bic.w r3, r3, #7
800be26: 3308 adds r3, #8
800be28: 9303 str r3, [sp, #12]
800be2a: 9b09 ldr r3, [sp, #36] ; 0x24
800be2c: 444b add r3, r9
800be2e: 9309 str r3, [sp, #36] ; 0x24
800be30: e76d b.n 800bd0e <_svfiprintf_r+0x4a>
800be32: fb05 3202 mla r2, r5, r2, r3
800be36: 2001 movs r0, #1
800be38: 460f mov r7, r1
800be3a: e7a6 b.n 800bd8a <_svfiprintf_r+0xc6>
800be3c: 2300 movs r3, #0
800be3e: 3701 adds r7, #1
800be40: 9305 str r3, [sp, #20]
800be42: 4619 mov r1, r3
800be44: 250a movs r5, #10
800be46: 4638 mov r0, r7
800be48: f810 2b01 ldrb.w r2, [r0], #1
800be4c: 3a30 subs r2, #48 ; 0x30
800be4e: 2a09 cmp r2, #9
800be50: d903 bls.n 800be5a <_svfiprintf_r+0x196>
800be52: 2b00 cmp r3, #0
800be54: d0c8 beq.n 800bde8 <_svfiprintf_r+0x124>
800be56: 9105 str r1, [sp, #20]
800be58: e7c6 b.n 800bde8 <_svfiprintf_r+0x124>
800be5a: fb05 2101 mla r1, r5, r1, r2
800be5e: 2301 movs r3, #1
800be60: 4607 mov r7, r0
800be62: e7f0 b.n 800be46 <_svfiprintf_r+0x182>
800be64: ab03 add r3, sp, #12
800be66: 9300 str r3, [sp, #0]
800be68: 4622 mov r2, r4
800be6a: 4b11 ldr r3, [pc, #68] ; (800beb0 <_svfiprintf_r+0x1ec>)
800be6c: a904 add r1, sp, #16
800be6e: 4640 mov r0, r8
800be70: f3af 8000 nop.w
800be74: f1b0 3fff cmp.w r0, #4294967295 ; 0xffffffff
800be78: 4681 mov r9, r0
800be7a: d1d6 bne.n 800be2a <_svfiprintf_r+0x166>
800be7c: 89a3 ldrh r3, [r4, #12]
800be7e: 065b lsls r3, r3, #25
800be80: f53f af35 bmi.w 800bcee <_svfiprintf_r+0x2a>
800be84: 9809 ldr r0, [sp, #36] ; 0x24
800be86: b01d add sp, #116 ; 0x74
800be88: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
800be8c: ab03 add r3, sp, #12
800be8e: 9300 str r3, [sp, #0]
800be90: 4622 mov r2, r4
800be92: 4b07 ldr r3, [pc, #28] ; (800beb0 <_svfiprintf_r+0x1ec>)
800be94: a904 add r1, sp, #16
800be96: 4640 mov r0, r8
800be98: f000 f882 bl 800bfa0 <_printf_i>
800be9c: e7ea b.n 800be74 <_svfiprintf_r+0x1b0>
800be9e: bf00 nop
800bea0: 0800e390 .word 0x0800e390
800bea4: 0800e396 .word 0x0800e396
800bea8: 0800e39a .word 0x0800e39a
800beac: 00000000 .word 0x00000000
800beb0: 0800bc11 .word 0x0800bc11
0800beb4 <_printf_common>:
800beb4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800beb8: 4691 mov r9, r2
800beba: 461f mov r7, r3
800bebc: 688a ldr r2, [r1, #8]
800bebe: 690b ldr r3, [r1, #16]
800bec0: f8dd 8020 ldr.w r8, [sp, #32]
800bec4: 4293 cmp r3, r2
800bec6: bfb8 it lt
800bec8: 4613 movlt r3, r2
800beca: f8c9 3000 str.w r3, [r9]
800bece: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
800bed2: 4606 mov r6, r0
800bed4: 460c mov r4, r1
800bed6: b112 cbz r2, 800bede <_printf_common+0x2a>
800bed8: 3301 adds r3, #1
800beda: f8c9 3000 str.w r3, [r9]
800bede: 6823 ldr r3, [r4, #0]
800bee0: 0699 lsls r1, r3, #26
800bee2: bf42 ittt mi
800bee4: f8d9 3000 ldrmi.w r3, [r9]
800bee8: 3302 addmi r3, #2
800beea: f8c9 3000 strmi.w r3, [r9]
800beee: 6825 ldr r5, [r4, #0]
800bef0: f015 0506 ands.w r5, r5, #6
800bef4: d107 bne.n 800bf06 <_printf_common+0x52>
800bef6: f104 0a19 add.w sl, r4, #25
800befa: 68e3 ldr r3, [r4, #12]
800befc: f8d9 2000 ldr.w r2, [r9]
800bf00: 1a9b subs r3, r3, r2
800bf02: 42ab cmp r3, r5
800bf04: dc28 bgt.n 800bf58 <_printf_common+0xa4>
800bf06: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
800bf0a: 6822 ldr r2, [r4, #0]
800bf0c: 3300 adds r3, #0
800bf0e: bf18 it ne
800bf10: 2301 movne r3, #1
800bf12: 0692 lsls r2, r2, #26
800bf14: d42d bmi.n 800bf72 <_printf_common+0xbe>
800bf16: f104 0243 add.w r2, r4, #67 ; 0x43
800bf1a: 4639 mov r1, r7
800bf1c: 4630 mov r0, r6
800bf1e: 47c0 blx r8
800bf20: 3001 adds r0, #1
800bf22: d020 beq.n 800bf66 <_printf_common+0xb2>
800bf24: 6823 ldr r3, [r4, #0]
800bf26: 68e5 ldr r5, [r4, #12]
800bf28: f8d9 2000 ldr.w r2, [r9]
800bf2c: f003 0306 and.w r3, r3, #6
800bf30: 2b04 cmp r3, #4
800bf32: bf08 it eq
800bf34: 1aad subeq r5, r5, r2
800bf36: 68a3 ldr r3, [r4, #8]
800bf38: 6922 ldr r2, [r4, #16]
800bf3a: bf0c ite eq
800bf3c: ea25 75e5 biceq.w r5, r5, r5, asr #31
800bf40: 2500 movne r5, #0
800bf42: 4293 cmp r3, r2
800bf44: bfc4 itt gt
800bf46: 1a9b subgt r3, r3, r2
800bf48: 18ed addgt r5, r5, r3
800bf4a: f04f 0900 mov.w r9, #0
800bf4e: 341a adds r4, #26
800bf50: 454d cmp r5, r9
800bf52: d11a bne.n 800bf8a <_printf_common+0xd6>
800bf54: 2000 movs r0, #0
800bf56: e008 b.n 800bf6a <_printf_common+0xb6>
800bf58: 2301 movs r3, #1
800bf5a: 4652 mov r2, sl
800bf5c: 4639 mov r1, r7
800bf5e: 4630 mov r0, r6
800bf60: 47c0 blx r8
800bf62: 3001 adds r0, #1
800bf64: d103 bne.n 800bf6e <_printf_common+0xba>
800bf66: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
800bf6a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800bf6e: 3501 adds r5, #1
800bf70: e7c3 b.n 800befa <_printf_common+0x46>
800bf72: 18e1 adds r1, r4, r3
800bf74: 1c5a adds r2, r3, #1
800bf76: 2030 movs r0, #48 ; 0x30
800bf78: f881 0043 strb.w r0, [r1, #67] ; 0x43
800bf7c: 4422 add r2, r4
800bf7e: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
800bf82: f882 1043 strb.w r1, [r2, #67] ; 0x43
800bf86: 3302 adds r3, #2
800bf88: e7c5 b.n 800bf16 <_printf_common+0x62>
800bf8a: 2301 movs r3, #1
800bf8c: 4622 mov r2, r4
800bf8e: 4639 mov r1, r7
800bf90: 4630 mov r0, r6
800bf92: 47c0 blx r8
800bf94: 3001 adds r0, #1
800bf96: d0e6 beq.n 800bf66 <_printf_common+0xb2>
800bf98: f109 0901 add.w r9, r9, #1
800bf9c: e7d8 b.n 800bf50 <_printf_common+0x9c>
...
0800bfa0 <_printf_i>:
800bfa0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
800bfa4: f101 0c43 add.w ip, r1, #67 ; 0x43
800bfa8: 460c mov r4, r1
800bfaa: 7e09 ldrb r1, [r1, #24]
800bfac: b085 sub sp, #20
800bfae: 296e cmp r1, #110 ; 0x6e
800bfb0: 4617 mov r7, r2
800bfb2: 4606 mov r6, r0
800bfb4: 4698 mov r8, r3
800bfb6: 9a0c ldr r2, [sp, #48] ; 0x30
800bfb8: f000 80b3 beq.w 800c122 <_printf_i+0x182>
800bfbc: d822 bhi.n 800c004 <_printf_i+0x64>
800bfbe: 2963 cmp r1, #99 ; 0x63
800bfc0: d036 beq.n 800c030 <_printf_i+0x90>
800bfc2: d80a bhi.n 800bfda <_printf_i+0x3a>
800bfc4: 2900 cmp r1, #0
800bfc6: f000 80b9 beq.w 800c13c <_printf_i+0x19c>
800bfca: 2958 cmp r1, #88 ; 0x58
800bfcc: f000 8083 beq.w 800c0d6 <_printf_i+0x136>
800bfd0: f104 0542 add.w r5, r4, #66 ; 0x42
800bfd4: f884 1042 strb.w r1, [r4, #66] ; 0x42
800bfd8: e032 b.n 800c040 <_printf_i+0xa0>
800bfda: 2964 cmp r1, #100 ; 0x64
800bfdc: d001 beq.n 800bfe2 <_printf_i+0x42>
800bfde: 2969 cmp r1, #105 ; 0x69
800bfe0: d1f6 bne.n 800bfd0 <_printf_i+0x30>
800bfe2: 6820 ldr r0, [r4, #0]
800bfe4: 6813 ldr r3, [r2, #0]
800bfe6: 0605 lsls r5, r0, #24
800bfe8: f103 0104 add.w r1, r3, #4
800bfec: d52a bpl.n 800c044 <_printf_i+0xa4>
800bfee: 681b ldr r3, [r3, #0]
800bff0: 6011 str r1, [r2, #0]
800bff2: 2b00 cmp r3, #0
800bff4: da03 bge.n 800bffe <_printf_i+0x5e>
800bff6: 222d movs r2, #45 ; 0x2d
800bff8: 425b negs r3, r3
800bffa: f884 2043 strb.w r2, [r4, #67] ; 0x43
800bffe: 486f ldr r0, [pc, #444] ; (800c1bc <_printf_i+0x21c>)
800c000: 220a movs r2, #10
800c002: e039 b.n 800c078 <_printf_i+0xd8>
800c004: 2973 cmp r1, #115 ; 0x73
800c006: f000 809d beq.w 800c144 <_printf_i+0x1a4>
800c00a: d808 bhi.n 800c01e <_printf_i+0x7e>
800c00c: 296f cmp r1, #111 ; 0x6f
800c00e: d020 beq.n 800c052 <_printf_i+0xb2>
800c010: 2970 cmp r1, #112 ; 0x70
800c012: d1dd bne.n 800bfd0 <_printf_i+0x30>
800c014: 6823 ldr r3, [r4, #0]
800c016: f043 0320 orr.w r3, r3, #32
800c01a: 6023 str r3, [r4, #0]
800c01c: e003 b.n 800c026 <_printf_i+0x86>
800c01e: 2975 cmp r1, #117 ; 0x75
800c020: d017 beq.n 800c052 <_printf_i+0xb2>
800c022: 2978 cmp r1, #120 ; 0x78
800c024: d1d4 bne.n 800bfd0 <_printf_i+0x30>
800c026: 2378 movs r3, #120 ; 0x78
800c028: f884 3045 strb.w r3, [r4, #69] ; 0x45
800c02c: 4864 ldr r0, [pc, #400] ; (800c1c0 <_printf_i+0x220>)
800c02e: e055 b.n 800c0dc <_printf_i+0x13c>
800c030: 6813 ldr r3, [r2, #0]
800c032: 1d19 adds r1, r3, #4
800c034: 681b ldr r3, [r3, #0]
800c036: 6011 str r1, [r2, #0]
800c038: f104 0542 add.w r5, r4, #66 ; 0x42
800c03c: f884 3042 strb.w r3, [r4, #66] ; 0x42
800c040: 2301 movs r3, #1
800c042: e08c b.n 800c15e <_printf_i+0x1be>
800c044: 681b ldr r3, [r3, #0]
800c046: 6011 str r1, [r2, #0]
800c048: f010 0f40 tst.w r0, #64 ; 0x40
800c04c: bf18 it ne
800c04e: b21b sxthne r3, r3
800c050: e7cf b.n 800bff2 <_printf_i+0x52>
800c052: 6813 ldr r3, [r2, #0]
800c054: 6825 ldr r5, [r4, #0]
800c056: 1d18 adds r0, r3, #4
800c058: 6010 str r0, [r2, #0]
800c05a: 0628 lsls r0, r5, #24
800c05c: d501 bpl.n 800c062 <_printf_i+0xc2>
800c05e: 681b ldr r3, [r3, #0]
800c060: e002 b.n 800c068 <_printf_i+0xc8>
800c062: 0668 lsls r0, r5, #25
800c064: d5fb bpl.n 800c05e <_printf_i+0xbe>
800c066: 881b ldrh r3, [r3, #0]
800c068: 4854 ldr r0, [pc, #336] ; (800c1bc <_printf_i+0x21c>)
800c06a: 296f cmp r1, #111 ; 0x6f
800c06c: bf14 ite ne
800c06e: 220a movne r2, #10
800c070: 2208 moveq r2, #8
800c072: 2100 movs r1, #0
800c074: f884 1043 strb.w r1, [r4, #67] ; 0x43
800c078: 6865 ldr r5, [r4, #4]
800c07a: 60a5 str r5, [r4, #8]
800c07c: 2d00 cmp r5, #0
800c07e: f2c0 8095 blt.w 800c1ac <_printf_i+0x20c>
800c082: 6821 ldr r1, [r4, #0]
800c084: f021 0104 bic.w r1, r1, #4
800c088: 6021 str r1, [r4, #0]
800c08a: 2b00 cmp r3, #0
800c08c: d13d bne.n 800c10a <_printf_i+0x16a>
800c08e: 2d00 cmp r5, #0
800c090: f040 808e bne.w 800c1b0 <_printf_i+0x210>
800c094: 4665 mov r5, ip
800c096: 2a08 cmp r2, #8
800c098: d10b bne.n 800c0b2 <_printf_i+0x112>
800c09a: 6823 ldr r3, [r4, #0]
800c09c: 07db lsls r3, r3, #31
800c09e: d508 bpl.n 800c0b2 <_printf_i+0x112>
800c0a0: 6923 ldr r3, [r4, #16]
800c0a2: 6862 ldr r2, [r4, #4]
800c0a4: 429a cmp r2, r3
800c0a6: bfde ittt le
800c0a8: 2330 movle r3, #48 ; 0x30
800c0aa: f805 3c01 strble.w r3, [r5, #-1]
800c0ae: f105 35ff addle.w r5, r5, #4294967295 ; 0xffffffff
800c0b2: ebac 0305 sub.w r3, ip, r5
800c0b6: 6123 str r3, [r4, #16]
800c0b8: f8cd 8000 str.w r8, [sp]
800c0bc: 463b mov r3, r7
800c0be: aa03 add r2, sp, #12
800c0c0: 4621 mov r1, r4
800c0c2: 4630 mov r0, r6
800c0c4: f7ff fef6 bl 800beb4 <_printf_common>
800c0c8: 3001 adds r0, #1
800c0ca: d14d bne.n 800c168 <_printf_i+0x1c8>
800c0cc: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
800c0d0: b005 add sp, #20
800c0d2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
800c0d6: 4839 ldr r0, [pc, #228] ; (800c1bc <_printf_i+0x21c>)
800c0d8: f884 1045 strb.w r1, [r4, #69] ; 0x45
800c0dc: 6813 ldr r3, [r2, #0]
800c0de: 6821 ldr r1, [r4, #0]
800c0e0: 1d1d adds r5, r3, #4
800c0e2: 681b ldr r3, [r3, #0]
800c0e4: 6015 str r5, [r2, #0]
800c0e6: 060a lsls r2, r1, #24
800c0e8: d50b bpl.n 800c102 <_printf_i+0x162>
800c0ea: 07ca lsls r2, r1, #31
800c0ec: bf44 itt mi
800c0ee: f041 0120 orrmi.w r1, r1, #32
800c0f2: 6021 strmi r1, [r4, #0]
800c0f4: b91b cbnz r3, 800c0fe <_printf_i+0x15e>
800c0f6: 6822 ldr r2, [r4, #0]
800c0f8: f022 0220 bic.w r2, r2, #32
800c0fc: 6022 str r2, [r4, #0]
800c0fe: 2210 movs r2, #16
800c100: e7b7 b.n 800c072 <_printf_i+0xd2>
800c102: 064d lsls r5, r1, #25
800c104: bf48 it mi
800c106: b29b uxthmi r3, r3
800c108: e7ef b.n 800c0ea <_printf_i+0x14a>
800c10a: 4665 mov r5, ip
800c10c: fbb3 f1f2 udiv r1, r3, r2
800c110: fb02 3311 mls r3, r2, r1, r3
800c114: 5cc3 ldrb r3, [r0, r3]
800c116: f805 3d01 strb.w r3, [r5, #-1]!
800c11a: 460b mov r3, r1
800c11c: 2900 cmp r1, #0
800c11e: d1f5 bne.n 800c10c <_printf_i+0x16c>
800c120: e7b9 b.n 800c096 <_printf_i+0xf6>
800c122: 6813 ldr r3, [r2, #0]
800c124: 6825 ldr r5, [r4, #0]
800c126: 6961 ldr r1, [r4, #20]
800c128: 1d18 adds r0, r3, #4
800c12a: 6010 str r0, [r2, #0]
800c12c: 0628 lsls r0, r5, #24
800c12e: 681b ldr r3, [r3, #0]
800c130: d501 bpl.n 800c136 <_printf_i+0x196>
800c132: 6019 str r1, [r3, #0]
800c134: e002 b.n 800c13c <_printf_i+0x19c>
800c136: 066a lsls r2, r5, #25
800c138: d5fb bpl.n 800c132 <_printf_i+0x192>
800c13a: 8019 strh r1, [r3, #0]
800c13c: 2300 movs r3, #0
800c13e: 6123 str r3, [r4, #16]
800c140: 4665 mov r5, ip
800c142: e7b9 b.n 800c0b8 <_printf_i+0x118>
800c144: 6813 ldr r3, [r2, #0]
800c146: 1d19 adds r1, r3, #4
800c148: 6011 str r1, [r2, #0]
800c14a: 681d ldr r5, [r3, #0]
800c14c: 6862 ldr r2, [r4, #4]
800c14e: 2100 movs r1, #0
800c150: 4628 mov r0, r5
800c152: f7f4 f85d bl 8000210 <memchr>
800c156: b108 cbz r0, 800c15c <_printf_i+0x1bc>
800c158: 1b40 subs r0, r0, r5
800c15a: 6060 str r0, [r4, #4]
800c15c: 6863 ldr r3, [r4, #4]
800c15e: 6123 str r3, [r4, #16]
800c160: 2300 movs r3, #0
800c162: f884 3043 strb.w r3, [r4, #67] ; 0x43
800c166: e7a7 b.n 800c0b8 <_printf_i+0x118>
800c168: 6923 ldr r3, [r4, #16]
800c16a: 462a mov r2, r5
800c16c: 4639 mov r1, r7
800c16e: 4630 mov r0, r6
800c170: 47c0 blx r8
800c172: 3001 adds r0, #1
800c174: d0aa beq.n 800c0cc <_printf_i+0x12c>
800c176: 6823 ldr r3, [r4, #0]
800c178: 079b lsls r3, r3, #30
800c17a: d413 bmi.n 800c1a4 <_printf_i+0x204>
800c17c: 68e0 ldr r0, [r4, #12]
800c17e: 9b03 ldr r3, [sp, #12]
800c180: 4298 cmp r0, r3
800c182: bfb8 it lt
800c184: 4618 movlt r0, r3
800c186: e7a3 b.n 800c0d0 <_printf_i+0x130>
800c188: 2301 movs r3, #1
800c18a: 464a mov r2, r9
800c18c: 4639 mov r1, r7
800c18e: 4630 mov r0, r6
800c190: 47c0 blx r8
800c192: 3001 adds r0, #1
800c194: d09a beq.n 800c0cc <_printf_i+0x12c>
800c196: 3501 adds r5, #1
800c198: 68e3 ldr r3, [r4, #12]
800c19a: 9a03 ldr r2, [sp, #12]
800c19c: 1a9b subs r3, r3, r2
800c19e: 42ab cmp r3, r5
800c1a0: dcf2 bgt.n 800c188 <_printf_i+0x1e8>
800c1a2: e7eb b.n 800c17c <_printf_i+0x1dc>
800c1a4: 2500 movs r5, #0
800c1a6: f104 0919 add.w r9, r4, #25
800c1aa: e7f5 b.n 800c198 <_printf_i+0x1f8>
800c1ac: 2b00 cmp r3, #0
800c1ae: d1ac bne.n 800c10a <_printf_i+0x16a>
800c1b0: 7803 ldrb r3, [r0, #0]
800c1b2: f884 3042 strb.w r3, [r4, #66] ; 0x42
800c1b6: f104 0542 add.w r5, r4, #66 ; 0x42
800c1ba: e76c b.n 800c096 <_printf_i+0xf6>
800c1bc: 0800e3a1 .word 0x0800e3a1
800c1c0: 0800e3b2 .word 0x0800e3b2
0800c1c4 <memmove>:
800c1c4: 4288 cmp r0, r1
800c1c6: b510 push {r4, lr}
800c1c8: eb01 0302 add.w r3, r1, r2
800c1cc: d807 bhi.n 800c1de <memmove+0x1a>
800c1ce: 1e42 subs r2, r0, #1
800c1d0: 4299 cmp r1, r3
800c1d2: d00a beq.n 800c1ea <memmove+0x26>
800c1d4: f811 4b01 ldrb.w r4, [r1], #1
800c1d8: f802 4f01 strb.w r4, [r2, #1]!
800c1dc: e7f8 b.n 800c1d0 <memmove+0xc>
800c1de: 4283 cmp r3, r0
800c1e0: d9f5 bls.n 800c1ce <memmove+0xa>
800c1e2: 1881 adds r1, r0, r2
800c1e4: 1ad2 subs r2, r2, r3
800c1e6: 42d3 cmn r3, r2
800c1e8: d100 bne.n 800c1ec <memmove+0x28>
800c1ea: bd10 pop {r4, pc}
800c1ec: f813 4d01 ldrb.w r4, [r3, #-1]!
800c1f0: f801 4d01 strb.w r4, [r1, #-1]!
800c1f4: e7f7 b.n 800c1e6 <memmove+0x22>
...
0800c1f8 <_free_r>:
800c1f8: b538 push {r3, r4, r5, lr}
800c1fa: 4605 mov r5, r0
800c1fc: 2900 cmp r1, #0
800c1fe: d045 beq.n 800c28c <_free_r+0x94>
800c200: f851 3c04 ldr.w r3, [r1, #-4]
800c204: 1f0c subs r4, r1, #4
800c206: 2b00 cmp r3, #0
800c208: bfb8 it lt
800c20a: 18e4 addlt r4, r4, r3
800c20c: f000 f8d2 bl 800c3b4 <__malloc_lock>
800c210: 4a1f ldr r2, [pc, #124] ; (800c290 <_free_r+0x98>)
800c212: 6813 ldr r3, [r2, #0]
800c214: 4610 mov r0, r2
800c216: b933 cbnz r3, 800c226 <_free_r+0x2e>
800c218: 6063 str r3, [r4, #4]
800c21a: 6014 str r4, [r2, #0]
800c21c: 4628 mov r0, r5
800c21e: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
800c222: f000 b8c8 b.w 800c3b6 <__malloc_unlock>
800c226: 42a3 cmp r3, r4
800c228: d90c bls.n 800c244 <_free_r+0x4c>
800c22a: 6821 ldr r1, [r4, #0]
800c22c: 1862 adds r2, r4, r1
800c22e: 4293 cmp r3, r2
800c230: bf04 itt eq
800c232: 681a ldreq r2, [r3, #0]
800c234: 685b ldreq r3, [r3, #4]
800c236: 6063 str r3, [r4, #4]
800c238: bf04 itt eq
800c23a: 1852 addeq r2, r2, r1
800c23c: 6022 streq r2, [r4, #0]
800c23e: 6004 str r4, [r0, #0]
800c240: e7ec b.n 800c21c <_free_r+0x24>
800c242: 4613 mov r3, r2
800c244: 685a ldr r2, [r3, #4]
800c246: b10a cbz r2, 800c24c <_free_r+0x54>
800c248: 42a2 cmp r2, r4
800c24a: d9fa bls.n 800c242 <_free_r+0x4a>
800c24c: 6819 ldr r1, [r3, #0]
800c24e: 1858 adds r0, r3, r1
800c250: 42a0 cmp r0, r4
800c252: d10b bne.n 800c26c <_free_r+0x74>
800c254: 6820 ldr r0, [r4, #0]
800c256: 4401 add r1, r0
800c258: 1858 adds r0, r3, r1
800c25a: 4282 cmp r2, r0
800c25c: 6019 str r1, [r3, #0]
800c25e: d1dd bne.n 800c21c <_free_r+0x24>
800c260: 6810 ldr r0, [r2, #0]
800c262: 6852 ldr r2, [r2, #4]
800c264: 605a str r2, [r3, #4]
800c266: 4401 add r1, r0
800c268: 6019 str r1, [r3, #0]
800c26a: e7d7 b.n 800c21c <_free_r+0x24>
800c26c: d902 bls.n 800c274 <_free_r+0x7c>
800c26e: 230c movs r3, #12
800c270: 602b str r3, [r5, #0]
800c272: e7d3 b.n 800c21c <_free_r+0x24>
800c274: 6820 ldr r0, [r4, #0]
800c276: 1821 adds r1, r4, r0
800c278: 428a cmp r2, r1
800c27a: bf04 itt eq
800c27c: 6811 ldreq r1, [r2, #0]
800c27e: 6852 ldreq r2, [r2, #4]
800c280: 6062 str r2, [r4, #4]
800c282: bf04 itt eq
800c284: 1809 addeq r1, r1, r0
800c286: 6021 streq r1, [r4, #0]
800c288: 605c str r4, [r3, #4]
800c28a: e7c7 b.n 800c21c <_free_r+0x24>
800c28c: bd38 pop {r3, r4, r5, pc}
800c28e: bf00 nop
800c290: 20008430 .word 0x20008430
0800c294 <_malloc_r>:
800c294: b570 push {r4, r5, r6, lr}
800c296: 1ccd adds r5, r1, #3
800c298: f025 0503 bic.w r5, r5, #3
800c29c: 3508 adds r5, #8
800c29e: 2d0c cmp r5, #12
800c2a0: bf38 it cc
800c2a2: 250c movcc r5, #12
800c2a4: 2d00 cmp r5, #0
800c2a6: 4606 mov r6, r0
800c2a8: db01 blt.n 800c2ae <_malloc_r+0x1a>
800c2aa: 42a9 cmp r1, r5
800c2ac: d903 bls.n 800c2b6 <_malloc_r+0x22>
800c2ae: 230c movs r3, #12
800c2b0: 6033 str r3, [r6, #0]
800c2b2: 2000 movs r0, #0
800c2b4: bd70 pop {r4, r5, r6, pc}
800c2b6: f000 f87d bl 800c3b4 <__malloc_lock>
800c2ba: 4a21 ldr r2, [pc, #132] ; (800c340 <_malloc_r+0xac>)
800c2bc: 6814 ldr r4, [r2, #0]
800c2be: 4621 mov r1, r4
800c2c0: b991 cbnz r1, 800c2e8 <_malloc_r+0x54>
800c2c2: 4c20 ldr r4, [pc, #128] ; (800c344 <_malloc_r+0xb0>)
800c2c4: 6823 ldr r3, [r4, #0]
800c2c6: b91b cbnz r3, 800c2d0 <_malloc_r+0x3c>
800c2c8: 4630 mov r0, r6
800c2ca: f000 f863 bl 800c394 <_sbrk_r>
800c2ce: 6020 str r0, [r4, #0]
800c2d0: 4629 mov r1, r5
800c2d2: 4630 mov r0, r6
800c2d4: f000 f85e bl 800c394 <_sbrk_r>
800c2d8: 1c43 adds r3, r0, #1
800c2da: d124 bne.n 800c326 <_malloc_r+0x92>
800c2dc: 230c movs r3, #12
800c2de: 6033 str r3, [r6, #0]
800c2e0: 4630 mov r0, r6
800c2e2: f000 f868 bl 800c3b6 <__malloc_unlock>
800c2e6: e7e4 b.n 800c2b2 <_malloc_r+0x1e>
800c2e8: 680b ldr r3, [r1, #0]
800c2ea: 1b5b subs r3, r3, r5
800c2ec: d418 bmi.n 800c320 <_malloc_r+0x8c>
800c2ee: 2b0b cmp r3, #11
800c2f0: d90f bls.n 800c312 <_malloc_r+0x7e>
800c2f2: 600b str r3, [r1, #0]
800c2f4: 50cd str r5, [r1, r3]
800c2f6: 18cc adds r4, r1, r3
800c2f8: 4630 mov r0, r6
800c2fa: f000 f85c bl 800c3b6 <__malloc_unlock>
800c2fe: f104 000b add.w r0, r4, #11
800c302: 1d23 adds r3, r4, #4
800c304: f020 0007 bic.w r0, r0, #7
800c308: 1ac3 subs r3, r0, r3
800c30a: d0d3 beq.n 800c2b4 <_malloc_r+0x20>
800c30c: 425a negs r2, r3
800c30e: 50e2 str r2, [r4, r3]
800c310: e7d0 b.n 800c2b4 <_malloc_r+0x20>
800c312: 428c cmp r4, r1
800c314: 684b ldr r3, [r1, #4]
800c316: bf16 itet ne
800c318: 6063 strne r3, [r4, #4]
800c31a: 6013 streq r3, [r2, #0]
800c31c: 460c movne r4, r1
800c31e: e7eb b.n 800c2f8 <_malloc_r+0x64>
800c320: 460c mov r4, r1
800c322: 6849 ldr r1, [r1, #4]
800c324: e7cc b.n 800c2c0 <_malloc_r+0x2c>
800c326: 1cc4 adds r4, r0, #3
800c328: f024 0403 bic.w r4, r4, #3
800c32c: 42a0 cmp r0, r4
800c32e: d005 beq.n 800c33c <_malloc_r+0xa8>
800c330: 1a21 subs r1, r4, r0
800c332: 4630 mov r0, r6
800c334: f000 f82e bl 800c394 <_sbrk_r>
800c338: 3001 adds r0, #1
800c33a: d0cf beq.n 800c2dc <_malloc_r+0x48>
800c33c: 6025 str r5, [r4, #0]
800c33e: e7db b.n 800c2f8 <_malloc_r+0x64>
800c340: 20008430 .word 0x20008430
800c344: 20008434 .word 0x20008434
0800c348 <_realloc_r>:
800c348: b5f8 push {r3, r4, r5, r6, r7, lr}
800c34a: 4607 mov r7, r0
800c34c: 4614 mov r4, r2
800c34e: 460e mov r6, r1
800c350: b921 cbnz r1, 800c35c <_realloc_r+0x14>
800c352: 4611 mov r1, r2
800c354: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
800c358: f7ff bf9c b.w 800c294 <_malloc_r>
800c35c: b922 cbnz r2, 800c368 <_realloc_r+0x20>
800c35e: f7ff ff4b bl 800c1f8 <_free_r>
800c362: 4625 mov r5, r4
800c364: 4628 mov r0, r5
800c366: bdf8 pop {r3, r4, r5, r6, r7, pc}
800c368: f000 f826 bl 800c3b8 <_malloc_usable_size_r>
800c36c: 42a0 cmp r0, r4
800c36e: d20f bcs.n 800c390 <_realloc_r+0x48>
800c370: 4621 mov r1, r4
800c372: 4638 mov r0, r7
800c374: f7ff ff8e bl 800c294 <_malloc_r>
800c378: 4605 mov r5, r0
800c37a: 2800 cmp r0, #0
800c37c: d0f2 beq.n 800c364 <_realloc_r+0x1c>
800c37e: 4631 mov r1, r6
800c380: 4622 mov r2, r4
800c382: f7ff fc11 bl 800bba8 <memcpy>
800c386: 4631 mov r1, r6
800c388: 4638 mov r0, r7
800c38a: f7ff ff35 bl 800c1f8 <_free_r>
800c38e: e7e9 b.n 800c364 <_realloc_r+0x1c>
800c390: 4635 mov r5, r6
800c392: e7e7 b.n 800c364 <_realloc_r+0x1c>
0800c394 <_sbrk_r>:
800c394: b538 push {r3, r4, r5, lr}
800c396: 4c06 ldr r4, [pc, #24] ; (800c3b0 <_sbrk_r+0x1c>)
800c398: 2300 movs r3, #0
800c39a: 4605 mov r5, r0
800c39c: 4608 mov r0, r1
800c39e: 6023 str r3, [r4, #0]
800c3a0: f7f8 f810 bl 80043c4 <_sbrk>
800c3a4: 1c43 adds r3, r0, #1
800c3a6: d102 bne.n 800c3ae <_sbrk_r+0x1a>
800c3a8: 6823 ldr r3, [r4, #0]
800c3aa: b103 cbz r3, 800c3ae <_sbrk_r+0x1a>
800c3ac: 602b str r3, [r5, #0]
800c3ae: bd38 pop {r3, r4, r5, pc}
800c3b0: 20008af8 .word 0x20008af8
0800c3b4 <__malloc_lock>:
800c3b4: 4770 bx lr
0800c3b6 <__malloc_unlock>:
800c3b6: 4770 bx lr
0800c3b8 <_malloc_usable_size_r>:
800c3b8: f851 3c04 ldr.w r3, [r1, #-4]
800c3bc: 1f18 subs r0, r3, #4
800c3be: 2b00 cmp r3, #0
800c3c0: bfbc itt lt
800c3c2: 580b ldrlt r3, [r1, r0]
800c3c4: 18c0 addlt r0, r0, r3
800c3c6: 4770 bx lr
0800c3c8 <_init>:
800c3c8: b5f8 push {r3, r4, r5, r6, r7, lr}
800c3ca: bf00 nop
800c3cc: bcf8 pop {r3, r4, r5, r6, r7}
800c3ce: bc08 pop {r3}
800c3d0: 469e mov lr, r3
800c3d2: 4770 bx lr
0800c3d4 <_fini>:
800c3d4: b5f8 push {r3, r4, r5, r6, r7, lr}
800c3d6: bf00 nop
800c3d8: bcf8 pop {r3, r4, r5, r6, r7}
800c3da: bc08 pop {r3}
800c3dc: 469e mov lr, r3
800c3de: 4770 bx lr
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